1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
54 #include "cfglayout.h"
55 #include "tree-gimple.h"
56 #include "tree-flow.h"
57 #include "tree-stdarg.h"
59 /* Specify which cpu to schedule for. */
60 enum processor_type alpha_tune
;
62 /* Which cpu we're generating code for. */
63 enum processor_type alpha_cpu
;
65 static const char * const alpha_cpu_name
[] =
70 /* Specify how accurate floating-point traps need to be. */
72 enum alpha_trap_precision alpha_tp
;
74 /* Specify the floating-point rounding mode. */
76 enum alpha_fp_rounding_mode alpha_fprm
;
78 /* Specify which things cause traps. */
80 enum alpha_fp_trap_mode alpha_fptm
;
82 /* Specify bit size of immediate TLS offsets. */
84 int alpha_tls_size
= 32;
86 /* Strings decoded into the above options. */
88 static const char *alpha_cpu_string
; /* -mcpu= */
89 static const char *alpha_tune_string
; /* -mtune= */
90 static const char *alpha_tp_string
; /* -mtrap-precision=[p|s|i] */
91 static const char *alpha_fprm_string
; /* -mfp-rounding-mode=[n|m|c|d] */
92 static const char *alpha_fptm_string
; /* -mfp-trap-mode=[n|u|su|sui] */
93 static const char *alpha_mlat_string
; /* -mmemory-latency= */
95 /* Save information from a "cmpxx" operation until the branch or scc is
98 struct alpha_compare alpha_compare
;
100 /* Nonzero if inside of a function, because the Alpha asm can't
101 handle .files inside of functions. */
103 static int inside_function
= FALSE
;
105 /* The number of cycles of latency we should assume on memory reads. */
107 int alpha_memory_latency
= 3;
109 /* Whether the function needs the GP. */
111 static int alpha_function_needs_gp
;
113 /* The alias set for prologue/epilogue register save/restore. */
115 static GTY(()) int alpha_sr_alias_set
;
117 /* The assembler name of the current function. */
119 static const char *alpha_fnname
;
121 /* The next explicit relocation sequence number. */
122 extern GTY(()) int alpha_next_sequence_number
;
123 int alpha_next_sequence_number
= 1;
125 /* The literal and gpdisp sequence numbers for this insn, as printed
126 by %# and %* respectively. */
127 extern GTY(()) int alpha_this_literal_sequence_number
;
128 extern GTY(()) int alpha_this_gpdisp_sequence_number
;
129 int alpha_this_literal_sequence_number
;
130 int alpha_this_gpdisp_sequence_number
;
132 /* Costs of various operations on the different architectures. */
134 struct alpha_rtx_cost_data
136 unsigned char fp_add
;
137 unsigned char fp_mult
;
138 unsigned char fp_div_sf
;
139 unsigned char fp_div_df
;
140 unsigned char int_mult_si
;
141 unsigned char int_mult_di
;
142 unsigned char int_shift
;
143 unsigned char int_cmov
;
144 unsigned short int_div
;
147 static struct alpha_rtx_cost_data
const alpha_rtx_cost_data
[PROCESSOR_MAX
] =
150 COSTS_N_INSNS (6), /* fp_add */
151 COSTS_N_INSNS (6), /* fp_mult */
152 COSTS_N_INSNS (34), /* fp_div_sf */
153 COSTS_N_INSNS (63), /* fp_div_df */
154 COSTS_N_INSNS (23), /* int_mult_si */
155 COSTS_N_INSNS (23), /* int_mult_di */
156 COSTS_N_INSNS (2), /* int_shift */
157 COSTS_N_INSNS (2), /* int_cmov */
158 COSTS_N_INSNS (97), /* int_div */
161 COSTS_N_INSNS (4), /* fp_add */
162 COSTS_N_INSNS (4), /* fp_mult */
163 COSTS_N_INSNS (15), /* fp_div_sf */
164 COSTS_N_INSNS (22), /* fp_div_df */
165 COSTS_N_INSNS (8), /* int_mult_si */
166 COSTS_N_INSNS (12), /* int_mult_di */
167 COSTS_N_INSNS (1) + 1, /* int_shift */
168 COSTS_N_INSNS (1), /* int_cmov */
169 COSTS_N_INSNS (83), /* int_div */
172 COSTS_N_INSNS (4), /* fp_add */
173 COSTS_N_INSNS (4), /* fp_mult */
174 COSTS_N_INSNS (12), /* fp_div_sf */
175 COSTS_N_INSNS (15), /* fp_div_df */
176 COSTS_N_INSNS (7), /* int_mult_si */
177 COSTS_N_INSNS (7), /* int_mult_di */
178 COSTS_N_INSNS (1), /* int_shift */
179 COSTS_N_INSNS (2), /* int_cmov */
180 COSTS_N_INSNS (86), /* int_div */
184 /* Similar but tuned for code size instead of execution latency. The
185 extra +N is fractional cost tuning based on latency. It's used to
186 encourage use of cheaper insns like shift, but only if there's just
189 static struct alpha_rtx_cost_data
const alpha_rtx_cost_size
=
191 COSTS_N_INSNS (1), /* fp_add */
192 COSTS_N_INSNS (1), /* fp_mult */
193 COSTS_N_INSNS (1), /* fp_div_sf */
194 COSTS_N_INSNS (1) + 1, /* fp_div_df */
195 COSTS_N_INSNS (1) + 1, /* int_mult_si */
196 COSTS_N_INSNS (1) + 2, /* int_mult_di */
197 COSTS_N_INSNS (1), /* int_shift */
198 COSTS_N_INSNS (1), /* int_cmov */
199 COSTS_N_INSNS (6), /* int_div */
202 /* Get the number of args of a function in one of two ways. */
203 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
204 #define NUM_ARGS current_function_args_info.num_args
206 #define NUM_ARGS current_function_args_info
212 /* Declarations of static functions. */
213 static struct machine_function
*alpha_init_machine_status (void);
214 static rtx
alpha_emit_xfloating_compare (enum rtx_code
, rtx
, rtx
);
216 #if TARGET_ABI_OPEN_VMS
217 static void alpha_write_linkage (FILE *, const char *, tree
);
220 static void unicosmk_output_deferred_case_vectors (FILE *);
221 static void unicosmk_gen_dsib (unsigned long *);
222 static void unicosmk_output_ssib (FILE *, const char *);
223 static int unicosmk_need_dex (rtx
);
225 /* Implement TARGET_HANDLE_OPTION. */
228 alpha_handle_option (size_t code
, const char *arg
, int value
)
234 target_flags
|= MASK_SOFT_FP
;
238 case OPT_mieee_with_inexact
:
239 target_flags
|= MASK_IEEE_CONFORMANT
;
243 alpha_cpu_string
= arg
;
247 alpha_tune_string
= arg
;
250 case OPT_mfp_rounding_mode_
:
251 alpha_fprm_string
= arg
;
254 case OPT_mfp_trap_mode_
:
255 alpha_fptm_string
= arg
;
258 case OPT_mtrap_precision_
:
259 alpha_tp_string
= arg
;
262 case OPT_mmemory_latency_
:
263 alpha_mlat_string
= arg
;
267 if (strcmp (arg
, "16") == 0)
269 else if (strcmp (arg
, "32") == 0)
271 else if (strcmp (arg
, "64") == 0)
274 error ("bad value %qs for -mtls-size switch", arg
);
281 /* Parse target option strings. */
284 override_options (void)
286 static const struct cpu_table
{
287 const char *const name
;
288 const enum processor_type processor
;
291 { "ev4", PROCESSOR_EV4
, 0 },
292 { "ev45", PROCESSOR_EV4
, 0 },
293 { "21064", PROCESSOR_EV4
, 0 },
294 { "ev5", PROCESSOR_EV5
, 0 },
295 { "21164", PROCESSOR_EV5
, 0 },
296 { "ev56", PROCESSOR_EV5
, MASK_BWX
},
297 { "21164a", PROCESSOR_EV5
, MASK_BWX
},
298 { "pca56", PROCESSOR_EV5
, MASK_BWX
|MASK_MAX
},
299 { "21164PC",PROCESSOR_EV5
, MASK_BWX
|MASK_MAX
},
300 { "21164pc",PROCESSOR_EV5
, MASK_BWX
|MASK_MAX
},
301 { "ev6", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
},
302 { "21264", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
},
303 { "ev67", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
|MASK_CIX
},
304 { "21264a", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
|MASK_CIX
},
310 /* Unicos/Mk doesn't have shared libraries. */
311 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
313 warning ("-f%s ignored for Unicos/Mk (not supported)",
314 (flag_pic
> 1) ? "PIC" : "pic");
318 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
319 floating-point instructions. Make that the default for this target. */
320 if (TARGET_ABI_UNICOSMK
)
321 alpha_fprm
= ALPHA_FPRM_DYN
;
323 alpha_fprm
= ALPHA_FPRM_NORM
;
325 alpha_tp
= ALPHA_TP_PROG
;
326 alpha_fptm
= ALPHA_FPTM_N
;
328 /* We cannot use su and sui qualifiers for conversion instructions on
329 Unicos/Mk. I'm not sure if this is due to assembler or hardware
330 limitations. Right now, we issue a warning if -mieee is specified
331 and then ignore it; eventually, we should either get it right or
332 disable the option altogether. */
336 if (TARGET_ABI_UNICOSMK
)
337 warning ("-mieee not supported on Unicos/Mk");
340 alpha_tp
= ALPHA_TP_INSN
;
341 alpha_fptm
= ALPHA_FPTM_SU
;
345 if (TARGET_IEEE_WITH_INEXACT
)
347 if (TARGET_ABI_UNICOSMK
)
348 warning ("-mieee-with-inexact not supported on Unicos/Mk");
351 alpha_tp
= ALPHA_TP_INSN
;
352 alpha_fptm
= ALPHA_FPTM_SUI
;
358 if (! strcmp (alpha_tp_string
, "p"))
359 alpha_tp
= ALPHA_TP_PROG
;
360 else if (! strcmp (alpha_tp_string
, "f"))
361 alpha_tp
= ALPHA_TP_FUNC
;
362 else if (! strcmp (alpha_tp_string
, "i"))
363 alpha_tp
= ALPHA_TP_INSN
;
365 error ("bad value %qs for -mtrap-precision switch", alpha_tp_string
);
368 if (alpha_fprm_string
)
370 if (! strcmp (alpha_fprm_string
, "n"))
371 alpha_fprm
= ALPHA_FPRM_NORM
;
372 else if (! strcmp (alpha_fprm_string
, "m"))
373 alpha_fprm
= ALPHA_FPRM_MINF
;
374 else if (! strcmp (alpha_fprm_string
, "c"))
375 alpha_fprm
= ALPHA_FPRM_CHOP
;
376 else if (! strcmp (alpha_fprm_string
,"d"))
377 alpha_fprm
= ALPHA_FPRM_DYN
;
379 error ("bad value %qs for -mfp-rounding-mode switch",
383 if (alpha_fptm_string
)
385 if (strcmp (alpha_fptm_string
, "n") == 0)
386 alpha_fptm
= ALPHA_FPTM_N
;
387 else if (strcmp (alpha_fptm_string
, "u") == 0)
388 alpha_fptm
= ALPHA_FPTM_U
;
389 else if (strcmp (alpha_fptm_string
, "su") == 0)
390 alpha_fptm
= ALPHA_FPTM_SU
;
391 else if (strcmp (alpha_fptm_string
, "sui") == 0)
392 alpha_fptm
= ALPHA_FPTM_SUI
;
394 error ("bad value %qs for -mfp-trap-mode switch", alpha_fptm_string
);
397 if (alpha_cpu_string
)
399 for (i
= 0; cpu_table
[i
].name
; i
++)
400 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
402 alpha_tune
= alpha_cpu
= cpu_table
[i
].processor
;
403 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
);
404 target_flags
|= cpu_table
[i
].flags
;
407 if (! cpu_table
[i
].name
)
408 error ("bad value %qs for -mcpu switch", alpha_cpu_string
);
411 if (alpha_tune_string
)
413 for (i
= 0; cpu_table
[i
].name
; i
++)
414 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
416 alpha_tune
= cpu_table
[i
].processor
;
419 if (! cpu_table
[i
].name
)
420 error ("bad value %qs for -mcpu switch", alpha_tune_string
);
423 /* Do some sanity checks on the above options. */
425 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
427 warning ("trap mode not supported on Unicos/Mk");
428 alpha_fptm
= ALPHA_FPTM_N
;
431 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
432 && alpha_tp
!= ALPHA_TP_INSN
&& alpha_cpu
!= PROCESSOR_EV6
)
434 warning ("fp software completion requires -mtrap-precision=i");
435 alpha_tp
= ALPHA_TP_INSN
;
438 if (alpha_cpu
== PROCESSOR_EV6
)
440 /* Except for EV6 pass 1 (not released), we always have precise
441 arithmetic traps. Which means we can do software completion
442 without minding trap shadows. */
443 alpha_tp
= ALPHA_TP_PROG
;
446 if (TARGET_FLOAT_VAX
)
448 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
450 warning ("rounding mode not supported for VAX floats");
451 alpha_fprm
= ALPHA_FPRM_NORM
;
453 if (alpha_fptm
== ALPHA_FPTM_SUI
)
455 warning ("trap mode not supported for VAX floats");
456 alpha_fptm
= ALPHA_FPTM_SU
;
458 if (target_flags_explicit
& MASK_LONG_DOUBLE_128
)
459 warning ("128-bit long double not supported for VAX floats");
460 target_flags
&= ~MASK_LONG_DOUBLE_128
;
467 if (!alpha_mlat_string
)
468 alpha_mlat_string
= "L1";
470 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
471 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
473 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
474 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
475 && alpha_mlat_string
[2] == '\0')
477 static int const cache_latency
[][4] =
479 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
480 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
481 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
484 lat
= alpha_mlat_string
[1] - '0';
485 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_tune
][lat
-1] == -1)
487 warning ("L%d cache latency unknown for %s",
488 lat
, alpha_cpu_name
[alpha_tune
]);
492 lat
= cache_latency
[alpha_tune
][lat
-1];
494 else if (! strcmp (alpha_mlat_string
, "main"))
496 /* Most current memories have about 370ns latency. This is
497 a reasonable guess for a fast cpu. */
502 warning ("bad value %qs for -mmemory-latency", alpha_mlat_string
);
506 alpha_memory_latency
= lat
;
509 /* Default the definition of "small data" to 8 bytes. */
513 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
515 target_flags
|= MASK_SMALL_DATA
;
516 else if (flag_pic
== 2)
517 target_flags
&= ~MASK_SMALL_DATA
;
519 /* Align labels and loops for optimal branching. */
520 /* ??? Kludge these by not doing anything if we don't optimize and also if
521 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
522 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
524 if (align_loops
<= 0)
526 if (align_jumps
<= 0)
529 if (align_functions
<= 0)
530 align_functions
= 16;
532 /* Acquire a unique set number for our register saves and restores. */
533 alpha_sr_alias_set
= new_alias_set ();
535 /* Register variables and functions with the garbage collector. */
537 /* Set up function hooks. */
538 init_machine_status
= alpha_init_machine_status
;
540 /* Tell the compiler when we're using VAX floating point. */
541 if (TARGET_FLOAT_VAX
)
543 REAL_MODE_FORMAT (SFmode
) = &vax_f_format
;
544 REAL_MODE_FORMAT (DFmode
) = &vax_g_format
;
545 REAL_MODE_FORMAT (TFmode
) = NULL
;
549 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
552 zap_mask (HOST_WIDE_INT value
)
556 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
558 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
564 /* Return true if OP is valid for a particular TLS relocation.
565 We are already guaranteed that OP is a CONST. */
568 tls_symbolic_operand_1 (rtx op
, int size
, int unspec
)
572 if (GET_CODE (op
) != UNSPEC
|| XINT (op
, 1) != unspec
)
574 op
= XVECEXP (op
, 0, 0);
576 if (GET_CODE (op
) != SYMBOL_REF
)
579 if (SYMBOL_REF_LOCAL_P (op
))
581 if (alpha_tls_size
> size
)
590 switch (SYMBOL_REF_TLS_MODEL (op
))
592 case TLS_MODEL_LOCAL_DYNAMIC
:
593 return unspec
== UNSPEC_DTPREL
;
594 case TLS_MODEL_INITIAL_EXEC
:
595 return unspec
== UNSPEC_TPREL
&& size
== 64;
596 case TLS_MODEL_LOCAL_EXEC
:
597 return unspec
== UNSPEC_TPREL
;
603 /* Used by aligned_memory_operand and unaligned_memory_operand to
604 resolve what reload is going to do with OP if it's a register. */
607 resolve_reload_operand (rtx op
)
609 if (reload_in_progress
)
612 if (GET_CODE (tmp
) == SUBREG
)
613 tmp
= SUBREG_REG (tmp
);
614 if (GET_CODE (tmp
) == REG
615 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
617 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
625 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
626 the range defined for C in [I-P]. */
629 alpha_const_ok_for_letter_p (HOST_WIDE_INT value
, int c
)
634 /* An unsigned 8 bit constant. */
635 return (unsigned HOST_WIDE_INT
) value
< 0x100;
637 /* The constant zero. */
640 /* A signed 16 bit constant. */
641 return (unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000;
643 /* A shifted signed 16 bit constant appropriate for LDAH. */
644 return ((value
& 0xffff) == 0
645 && ((value
) >> 31 == -1 || value
>> 31 == 0));
647 /* A constant that can be AND'ed with using a ZAP insn. */
648 return zap_mask (value
);
650 /* A complemented unsigned 8 bit constant. */
651 return (unsigned HOST_WIDE_INT
) (~ value
) < 0x100;
653 /* A negated unsigned 8 bit constant. */
654 return (unsigned HOST_WIDE_INT
) (- value
) < 0x100;
656 /* The constant 1, 2 or 3. */
657 return value
== 1 || value
== 2 || value
== 3;
664 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
665 matches for C in [GH]. */
668 alpha_const_double_ok_for_letter_p (rtx value
, int c
)
673 /* The floating point zero constant. */
674 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
675 && value
== CONST0_RTX (GET_MODE (value
)));
678 /* A valid operand of a ZAP insn. */
679 return (GET_MODE (value
) == VOIDmode
680 && zap_mask (CONST_DOUBLE_LOW (value
))
681 && zap_mask (CONST_DOUBLE_HIGH (value
)));
688 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
692 alpha_extra_constraint (rtx value
, int c
)
697 return normal_memory_operand (value
, VOIDmode
);
699 return direct_call_operand (value
, Pmode
);
701 return (GET_CODE (value
) == CONST_INT
702 && (unsigned HOST_WIDE_INT
) INTVAL (value
) < 64);
704 return GET_CODE (value
) == HIGH
;
706 return TARGET_ABI_UNICOSMK
&& symbolic_operand (value
, VOIDmode
);
708 return (GET_CODE (value
) == CONST_VECTOR
709 && value
== CONST0_RTX (GET_MODE (value
)));
715 /* The scalar modes supported differs from the default check-what-c-supports
716 version in that sometimes TFmode is available even when long double
717 indicates only DFmode. On unicosmk, we have the situation that HImode
718 doesn't map to any C type, but of course we still support that. */
721 alpha_scalar_mode_supported_p (enum machine_mode mode
)
729 case TImode
: /* via optabs.c */
737 return TARGET_HAS_XFLOATING_LIBS
;
744 /* Alpha implements a couple of integer vector mode operations when
745 TARGET_MAX is enabled. We do not check TARGET_MAX here, however,
746 which allows the vectorizer to operate on e.g. move instructions,
747 or when expand_vector_operations can do something useful. */
750 alpha_vector_mode_supported_p (enum machine_mode mode
)
752 return mode
== V8QImode
|| mode
== V4HImode
|| mode
== V2SImode
;
755 /* Return 1 if this function can directly return via $26. */
760 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
762 && alpha_sa_size () == 0
763 && get_frame_size () == 0
764 && current_function_outgoing_args_size
== 0
765 && current_function_pretend_args_size
== 0);
768 /* Return the ADDR_VEC associated with a tablejump insn. */
771 alpha_tablejump_addr_vec (rtx insn
)
775 tmp
= JUMP_LABEL (insn
);
778 tmp
= NEXT_INSN (tmp
);
781 if (GET_CODE (tmp
) == JUMP_INSN
782 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
783 return PATTERN (tmp
);
787 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
790 alpha_tablejump_best_label (rtx insn
)
792 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
793 rtx best_label
= NULL_RTX
;
795 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
796 there for edge frequency counts from profile data. */
800 int n_labels
= XVECLEN (jump_table
, 1);
804 for (i
= 0; i
< n_labels
; i
++)
808 for (j
= i
+ 1; j
< n_labels
; j
++)
809 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
810 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
813 if (count
> best_count
)
814 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
818 return best_label
? best_label
: const0_rtx
;
821 /* Return the TLS model to use for SYMBOL. */
823 static enum tls_model
824 tls_symbolic_operand_type (rtx symbol
)
826 enum tls_model model
;
828 if (GET_CODE (symbol
) != SYMBOL_REF
)
830 model
= SYMBOL_REF_TLS_MODEL (symbol
);
832 /* Local-exec with a 64-bit size is the same code as initial-exec. */
833 if (model
== TLS_MODEL_LOCAL_EXEC
&& alpha_tls_size
== 64)
834 model
= TLS_MODEL_INITIAL_EXEC
;
839 /* Return true if the function DECL will share the same GP as any
840 function in the current unit of translation. */
843 decl_has_samegp (tree decl
)
845 /* Functions that are not local can be overridden, and thus may
846 not share the same gp. */
847 if (!(*targetm
.binds_local_p
) (decl
))
850 /* If -msmall-data is in effect, assume that there is only one GP
851 for the module, and so any local symbol has this property. We
852 need explicit relocations to be able to enforce this for symbols
853 not defined in this unit of translation, however. */
854 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
857 /* Functions that are not external are defined in this UoT. */
858 /* ??? Irritatingly, static functions not yet emitted are still
859 marked "external". Apply this to non-static functions only. */
860 return !TREE_PUBLIC (decl
) || !DECL_EXTERNAL (decl
);
863 /* Return true if EXP should be placed in the small data section. */
866 alpha_in_small_data_p (tree exp
)
868 /* We want to merge strings, so we never consider them small data. */
869 if (TREE_CODE (exp
) == STRING_CST
)
872 /* Functions are never in the small data area. Duh. */
873 if (TREE_CODE (exp
) == FUNCTION_DECL
)
876 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
878 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
879 if (strcmp (section
, ".sdata") == 0
880 || strcmp (section
, ".sbss") == 0)
885 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
887 /* If this is an incomplete type with size 0, then we can't put it
888 in sdata because it might be too big when completed. */
889 if (size
> 0 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
)
896 #if TARGET_ABI_OPEN_VMS
898 alpha_linkage_symbol_p (const char *symname
)
900 int symlen
= strlen (symname
);
903 return strcmp (&symname
[symlen
- 4], "..lk") == 0;
908 #define LINKAGE_SYMBOL_REF_P(X) \
909 ((GET_CODE (X) == SYMBOL_REF \
910 && alpha_linkage_symbol_p (XSTR (X, 0))) \
911 || (GET_CODE (X) == CONST \
912 && GET_CODE (XEXP (X, 0)) == PLUS \
913 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
914 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
917 /* legitimate_address_p recognizes an RTL expression that is a valid
918 memory address for an instruction. The MODE argument is the
919 machine mode for the MEM expression that wants to use this address.
921 For Alpha, we have either a constant address or the sum of a
922 register and a constant address, or just a register. For DImode,
923 any of those forms can be surrounded with an AND that clear the
924 low-order three bits; this is an "unaligned" access. */
927 alpha_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
929 /* If this is an ldq_u type address, discard the outer AND. */
931 && GET_CODE (x
) == AND
932 && GET_CODE (XEXP (x
, 1)) == CONST_INT
933 && INTVAL (XEXP (x
, 1)) == -8)
936 /* Discard non-paradoxical subregs. */
937 if (GET_CODE (x
) == SUBREG
938 && (GET_MODE_SIZE (GET_MODE (x
))
939 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
942 /* Unadorned general registers are valid. */
945 ? STRICT_REG_OK_FOR_BASE_P (x
)
946 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
949 /* Constant addresses (i.e. +/- 32k) are valid. */
950 if (CONSTANT_ADDRESS_P (x
))
953 #if TARGET_ABI_OPEN_VMS
954 if (LINKAGE_SYMBOL_REF_P (x
))
958 /* Register plus a small constant offset is valid. */
959 if (GET_CODE (x
) == PLUS
)
961 rtx ofs
= XEXP (x
, 1);
964 /* Discard non-paradoxical subregs. */
965 if (GET_CODE (x
) == SUBREG
966 && (GET_MODE_SIZE (GET_MODE (x
))
967 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
973 && NONSTRICT_REG_OK_FP_BASE_P (x
)
974 && GET_CODE (ofs
) == CONST_INT
)
977 ? STRICT_REG_OK_FOR_BASE_P (x
)
978 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
979 && CONSTANT_ADDRESS_P (ofs
))
984 /* If we're managing explicit relocations, LO_SUM is valid, as
985 are small data symbols. */
986 else if (TARGET_EXPLICIT_RELOCS
)
988 if (small_symbolic_operand (x
, Pmode
))
991 if (GET_CODE (x
) == LO_SUM
)
993 rtx ofs
= XEXP (x
, 1);
996 /* Discard non-paradoxical subregs. */
997 if (GET_CODE (x
) == SUBREG
998 && (GET_MODE_SIZE (GET_MODE (x
))
999 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1002 /* Must have a valid base register. */
1005 ? STRICT_REG_OK_FOR_BASE_P (x
)
1006 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
1009 /* The symbol must be local. */
1010 if (local_symbolic_operand (ofs
, Pmode
)
1011 || dtp32_symbolic_operand (ofs
, Pmode
)
1012 || tp32_symbolic_operand (ofs
, Pmode
))
1020 /* Build the SYMBOL_REF for __tls_get_addr. */
1022 static GTY(()) rtx tls_get_addr_libfunc
;
1025 get_tls_get_addr (void)
1027 if (!tls_get_addr_libfunc
)
1028 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
1029 return tls_get_addr_libfunc
;
1032 /* Try machine-dependent ways of modifying an illegitimate address
1033 to be legitimate. If we find one, return the new, valid address. */
1036 alpha_legitimize_address (rtx x
, rtx scratch
,
1037 enum machine_mode mode ATTRIBUTE_UNUSED
)
1039 HOST_WIDE_INT addend
;
1041 /* If the address is (plus reg const_int) and the CONST_INT is not a
1042 valid offset, compute the high part of the constant and add it to
1043 the register. Then our address is (plus temp low-part-const). */
1044 if (GET_CODE (x
) == PLUS
1045 && GET_CODE (XEXP (x
, 0)) == REG
1046 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1047 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
1049 addend
= INTVAL (XEXP (x
, 1));
1054 /* If the address is (const (plus FOO const_int)), find the low-order
1055 part of the CONST_INT. Then load FOO plus any high-order part of the
1056 CONST_INT into a register. Our address is (plus reg low-part-const).
1057 This is done to reduce the number of GOT entries. */
1059 && GET_CODE (x
) == CONST
1060 && GET_CODE (XEXP (x
, 0)) == PLUS
1061 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
1063 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
1064 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
1068 /* If we have a (plus reg const), emit the load as in (2), then add
1069 the two registers, and finally generate (plus reg low-part-const) as
1072 && GET_CODE (x
) == PLUS
1073 && GET_CODE (XEXP (x
, 0)) == REG
1074 && GET_CODE (XEXP (x
, 1)) == CONST
1075 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
1076 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == CONST_INT
)
1078 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
1079 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
1080 XEXP (XEXP (XEXP (x
, 1), 0), 0),
1081 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1085 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1086 if (TARGET_EXPLICIT_RELOCS
&& symbolic_operand (x
, Pmode
))
1088 rtx r0
, r16
, eqv
, tga
, tp
, insn
, dest
, seq
;
1090 switch (tls_symbolic_operand_type (x
))
1092 case TLS_MODEL_GLOBAL_DYNAMIC
:
1095 r0
= gen_rtx_REG (Pmode
, 0);
1096 r16
= gen_rtx_REG (Pmode
, 16);
1097 tga
= get_tls_get_addr ();
1098 dest
= gen_reg_rtx (Pmode
);
1099 seq
= GEN_INT (alpha_next_sequence_number
++);
1101 emit_insn (gen_movdi_er_tlsgd (r16
, pic_offset_table_rtx
, x
, seq
));
1102 insn
= gen_call_value_osf_tlsgd (r0
, tga
, seq
);
1103 insn
= emit_call_insn (insn
);
1104 CONST_OR_PURE_CALL_P (insn
) = 1;
1105 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
1107 insn
= get_insns ();
1110 emit_libcall_block (insn
, dest
, r0
, x
);
1113 case TLS_MODEL_LOCAL_DYNAMIC
:
1116 r0
= gen_rtx_REG (Pmode
, 0);
1117 r16
= gen_rtx_REG (Pmode
, 16);
1118 tga
= get_tls_get_addr ();
1119 scratch
= gen_reg_rtx (Pmode
);
1120 seq
= GEN_INT (alpha_next_sequence_number
++);
1122 emit_insn (gen_movdi_er_tlsldm (r16
, pic_offset_table_rtx
, seq
));
1123 insn
= gen_call_value_osf_tlsldm (r0
, tga
, seq
);
1124 insn
= emit_call_insn (insn
);
1125 CONST_OR_PURE_CALL_P (insn
) = 1;
1126 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
1128 insn
= get_insns ();
1131 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1132 UNSPEC_TLSLDM_CALL
);
1133 emit_libcall_block (insn
, scratch
, r0
, eqv
);
1135 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPREL
);
1136 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1138 if (alpha_tls_size
== 64)
1140 dest
= gen_reg_rtx (Pmode
);
1141 emit_insn (gen_rtx_SET (VOIDmode
, dest
, eqv
));
1142 emit_insn (gen_adddi3 (dest
, dest
, scratch
));
1145 if (alpha_tls_size
== 32)
1147 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1148 insn
= gen_rtx_PLUS (Pmode
, scratch
, insn
);
1149 scratch
= gen_reg_rtx (Pmode
);
1150 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, insn
));
1152 return gen_rtx_LO_SUM (Pmode
, scratch
, eqv
);
1154 case TLS_MODEL_INITIAL_EXEC
:
1155 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1156 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1157 tp
= gen_reg_rtx (Pmode
);
1158 scratch
= gen_reg_rtx (Pmode
);
1159 dest
= gen_reg_rtx (Pmode
);
1161 emit_insn (gen_load_tp (tp
));
1162 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, eqv
));
1163 emit_insn (gen_adddi3 (dest
, tp
, scratch
));
1166 case TLS_MODEL_LOCAL_EXEC
:
1167 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1168 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1169 tp
= gen_reg_rtx (Pmode
);
1171 emit_insn (gen_load_tp (tp
));
1172 if (alpha_tls_size
== 32)
1174 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1175 insn
= gen_rtx_PLUS (Pmode
, tp
, insn
);
1176 tp
= gen_reg_rtx (Pmode
);
1177 emit_insn (gen_rtx_SET (VOIDmode
, tp
, insn
));
1179 return gen_rtx_LO_SUM (Pmode
, tp
, eqv
);
1182 if (local_symbolic_operand (x
, Pmode
))
1184 if (small_symbolic_operand (x
, Pmode
))
1188 if (!no_new_pseudos
)
1189 scratch
= gen_reg_rtx (Pmode
);
1190 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
1191 gen_rtx_HIGH (Pmode
, x
)));
1192 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
1201 HOST_WIDE_INT low
, high
;
1203 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
1205 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1209 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
1210 (no_new_pseudos
? scratch
: NULL_RTX
),
1211 1, OPTAB_LIB_WIDEN
);
1213 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
1214 (no_new_pseudos
? scratch
: NULL_RTX
),
1215 1, OPTAB_LIB_WIDEN
);
1217 return plus_constant (x
, low
);
1221 /* Primarily this is required for TLS symbols, but given that our move
1222 patterns *ought* to be able to handle any symbol at any time, we
1223 should never be spilling symbolic operands to the constant pool, ever. */
1226 alpha_cannot_force_const_mem (rtx x
)
1228 enum rtx_code code
= GET_CODE (x
);
1229 return code
== SYMBOL_REF
|| code
== LABEL_REF
|| code
== CONST
;
1232 /* We do not allow indirect calls to be optimized into sibling calls, nor
1233 can we allow a call to a function with a different GP to be optimized
1237 alpha_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
1239 /* Can't do indirect tail calls, since we don't know if the target
1240 uses the same GP. */
1244 /* Otherwise, we can make a tail call if the target function shares
1246 return decl_has_samegp (decl
);
1250 some_small_symbolic_operand_int (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1254 /* Don't re-split. */
1255 if (GET_CODE (x
) == LO_SUM
)
1258 return small_symbolic_operand (x
, Pmode
) != 0;
1262 split_small_symbolic_operand_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1266 /* Don't re-split. */
1267 if (GET_CODE (x
) == LO_SUM
)
1270 if (small_symbolic_operand (x
, Pmode
))
1272 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
1281 split_small_symbolic_operand (rtx x
)
1284 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
1288 /* Indicate that INSN cannot be duplicated. This is true for any insn
1289 that we've marked with gpdisp relocs, since those have to stay in
1290 1-1 correspondence with one another.
1292 Technically we could copy them if we could set up a mapping from one
1293 sequence number to another, across the set of insns to be duplicated.
1294 This seems overly complicated and error-prone since interblock motion
1295 from sched-ebb could move one of the pair of insns to a different block.
1297 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
1298 then they'll be in a different block from their ldgp. Which could lead
1299 the bb reorder code to think that it would be ok to copy just the block
1300 containing the call and branch to the block containing the ldgp. */
1303 alpha_cannot_copy_insn_p (rtx insn
)
1305 if (!reload_completed
|| !TARGET_EXPLICIT_RELOCS
)
1307 if (recog_memoized (insn
) >= 0)
1308 return get_attr_cannot_copy (insn
);
1314 /* Try a machine-dependent way of reloading an illegitimate address
1315 operand. If we find one, push the reload and return the new rtx. */
1318 alpha_legitimize_reload_address (rtx x
,
1319 enum machine_mode mode ATTRIBUTE_UNUSED
,
1320 int opnum
, int type
,
1321 int ind_levels ATTRIBUTE_UNUSED
)
1323 /* We must recognize output that we have already generated ourselves. */
1324 if (GET_CODE (x
) == PLUS
1325 && GET_CODE (XEXP (x
, 0)) == PLUS
1326 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1327 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1328 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1330 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
1331 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
1336 /* We wish to handle large displacements off a base register by
1337 splitting the addend across an ldah and the mem insn. This
1338 cuts number of extra insns needed from 3 to 1. */
1339 if (GET_CODE (x
) == PLUS
1340 && GET_CODE (XEXP (x
, 0)) == REG
1341 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
1342 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
1343 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1345 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
1346 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
1348 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
1350 /* Check for 32-bit overflow. */
1351 if (high
+ low
!= val
)
1354 /* Reload the high part into a base reg; leave the low part
1355 in the mem directly. */
1356 x
= gen_rtx_PLUS (GET_MODE (x
),
1357 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
1361 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
1362 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
1370 /* Compute a (partial) cost for rtx X. Return true if the complete
1371 cost has been computed, and false if subexpressions should be
1372 scanned. In either case, *TOTAL contains the cost result. */
1375 alpha_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1377 enum machine_mode mode
= GET_MODE (x
);
1378 bool float_mode_p
= FLOAT_MODE_P (mode
);
1379 const struct alpha_rtx_cost_data
*cost_data
;
1382 cost_data
= &alpha_rtx_cost_size
;
1384 cost_data
= &alpha_rtx_cost_data
[alpha_tune
];
1389 /* If this is an 8-bit constant, return zero since it can be used
1390 nearly anywhere with no cost. If it is a valid operand for an
1391 ADD or AND, likewise return 0 if we know it will be used in that
1392 context. Otherwise, return 2 since it might be used there later.
1393 All other constants take at least two insns. */
1394 if (INTVAL (x
) >= 0 && INTVAL (x
) < 256)
1402 if (x
== CONST0_RTX (mode
))
1404 else if ((outer_code
== PLUS
&& add_operand (x
, VOIDmode
))
1405 || (outer_code
== AND
&& and_operand (x
, VOIDmode
)))
1407 else if (add_operand (x
, VOIDmode
) || and_operand (x
, VOIDmode
))
1410 *total
= COSTS_N_INSNS (2);
1416 if (TARGET_EXPLICIT_RELOCS
&& small_symbolic_operand (x
, VOIDmode
))
1417 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
1418 else if (TARGET_EXPLICIT_RELOCS
&& local_symbolic_operand (x
, VOIDmode
))
1419 *total
= COSTS_N_INSNS (1 + (outer_code
!= MEM
));
1420 else if (tls_symbolic_operand_type (x
))
1421 /* Estimate of cost for call_pal rduniq. */
1422 /* ??? How many insns do we emit here? More than one... */
1423 *total
= COSTS_N_INSNS (15);
1425 /* Otherwise we do a load from the GOT. */
1426 *total
= COSTS_N_INSNS (optimize_size
? 1 : alpha_memory_latency
);
1430 /* This is effectively an add_operand. */
1437 *total
= cost_data
->fp_add
;
1438 else if (GET_CODE (XEXP (x
, 0)) == MULT
1439 && const48_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
))
1441 *total
= (rtx_cost (XEXP (XEXP (x
, 0), 0), outer_code
)
1442 + rtx_cost (XEXP (x
, 1), outer_code
) + COSTS_N_INSNS (1));
1449 *total
= cost_data
->fp_mult
;
1450 else if (mode
== DImode
)
1451 *total
= cost_data
->int_mult_di
;
1453 *total
= cost_data
->int_mult_si
;
1457 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1458 && INTVAL (XEXP (x
, 1)) <= 3)
1460 *total
= COSTS_N_INSNS (1);
1467 *total
= cost_data
->int_shift
;
1472 *total
= cost_data
->fp_add
;
1474 *total
= cost_data
->int_cmov
;
1482 *total
= cost_data
->int_div
;
1483 else if (mode
== SFmode
)
1484 *total
= cost_data
->fp_div_sf
;
1486 *total
= cost_data
->fp_div_df
;
1490 *total
= COSTS_N_INSNS (optimize_size
? 1 : alpha_memory_latency
);
1496 *total
= COSTS_N_INSNS (1);
1504 *total
= COSTS_N_INSNS (1) + cost_data
->int_cmov
;
1510 case UNSIGNED_FLOAT
:
1514 case FLOAT_TRUNCATE
:
1515 *total
= cost_data
->fp_add
;
1523 /* REF is an alignable memory location. Place an aligned SImode
1524 reference into *PALIGNED_MEM and the number of bits to shift into
1525 *PBITNUM. SCRATCH is a free register for use in reloading out
1526 of range stack slots. */
1529 get_aligned_mem (rtx ref
, rtx
*paligned_mem
, rtx
*pbitnum
)
1532 HOST_WIDE_INT offset
= 0;
1534 if (GET_CODE (ref
) != MEM
)
1537 if (reload_in_progress
1538 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
1540 base
= find_replacement (&XEXP (ref
, 0));
1542 if (! memory_address_p (GET_MODE (ref
), base
))
1547 base
= XEXP (ref
, 0);
1550 if (GET_CODE (base
) == PLUS
)
1551 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
1554 = widen_memory_access (ref
, SImode
, (offset
& ~3) - offset
);
1556 if (WORDS_BIG_ENDIAN
)
1557 *pbitnum
= GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref
))
1558 + (offset
& 3) * 8));
1560 *pbitnum
= GEN_INT ((offset
& 3) * 8);
1563 /* Similar, but just get the address. Handle the two reload cases.
1564 Add EXTRA_OFFSET to the address we return. */
1567 get_unaligned_address (rtx ref
, int extra_offset
)
1570 HOST_WIDE_INT offset
= 0;
1572 if (GET_CODE (ref
) != MEM
)
1575 if (reload_in_progress
1576 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
1578 base
= find_replacement (&XEXP (ref
, 0));
1580 if (! memory_address_p (GET_MODE (ref
), base
))
1585 base
= XEXP (ref
, 0);
1588 if (GET_CODE (base
) == PLUS
)
1589 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
1591 return plus_constant (base
, offset
+ extra_offset
);
1594 /* On the Alpha, all (non-symbolic) constants except zero go into
1595 a floating-point register via memory. Note that we cannot
1596 return anything that is not a subset of CLASS, and that some
1597 symbolic constants cannot be dropped to memory. */
1600 alpha_preferred_reload_class(rtx x
, enum reg_class
class)
1602 /* Zero is present in any register class. */
1603 if (x
== CONST0_RTX (GET_MODE (x
)))
1606 /* These sorts of constants we can easily drop to memory. */
1607 if (GET_CODE (x
) == CONST_INT
1608 || GET_CODE (x
) == CONST_DOUBLE
1609 || GET_CODE (x
) == CONST_VECTOR
)
1611 if (class == FLOAT_REGS
)
1613 if (class == ALL_REGS
)
1614 return GENERAL_REGS
;
1618 /* All other kinds of constants should not (and in the case of HIGH
1619 cannot) be dropped to memory -- instead we use a GENERAL_REGS
1620 secondary reload. */
1622 return (class == ALL_REGS
? GENERAL_REGS
: class);
1627 /* Loading and storing HImode or QImode values to and from memory
1628 usually requires a scratch register. The exceptions are loading
1629 QImode and HImode from an aligned address to a general register
1630 unless byte instructions are permitted.
1632 We also cannot load an unaligned address or a paradoxical SUBREG
1633 into an FP register.
1635 We also cannot do integral arithmetic into FP regs, as might result
1636 from register elimination into a DImode fp register. */
1639 secondary_reload_class (enum reg_class
class, enum machine_mode mode
,
1642 if ((mode
== QImode
|| mode
== HImode
) && ! TARGET_BWX
)
1644 if (GET_CODE (x
) == MEM
1645 || (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
1646 || (GET_CODE (x
) == SUBREG
1647 && (GET_CODE (SUBREG_REG (x
)) == MEM
1648 || (GET_CODE (SUBREG_REG (x
)) == REG
1649 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
))))
1651 if (!in
|| !aligned_memory_operand(x
, mode
))
1652 return GENERAL_REGS
;
1656 if (class == FLOAT_REGS
)
1658 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
1659 return GENERAL_REGS
;
1661 if (GET_CODE (x
) == SUBREG
1662 && (GET_MODE_SIZE (GET_MODE (x
))
1663 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1664 return GENERAL_REGS
;
1666 if (in
&& INTEGRAL_MODE_P (mode
)
1667 && ! (memory_operand (x
, mode
) || x
== const0_rtx
))
1668 return GENERAL_REGS
;
1674 /* Subfunction of the following function. Update the flags of any MEM
1675 found in part of X. */
1678 alpha_set_memflags_1 (rtx
*xp
, void *data
)
1680 rtx x
= *xp
, orig
= (rtx
) data
;
1682 if (GET_CODE (x
) != MEM
)
1685 MEM_VOLATILE_P (x
) = MEM_VOLATILE_P (orig
);
1686 MEM_IN_STRUCT_P (x
) = MEM_IN_STRUCT_P (orig
);
1687 MEM_SCALAR_P (x
) = MEM_SCALAR_P (orig
);
1688 MEM_NOTRAP_P (x
) = MEM_NOTRAP_P (orig
);
1689 MEM_READONLY_P (x
) = MEM_READONLY_P (orig
);
1691 /* Sadly, we cannot use alias sets because the extra aliasing
1692 produced by the AND interferes. Given that two-byte quantities
1693 are the only thing we would be able to differentiate anyway,
1694 there does not seem to be any point in convoluting the early
1695 out of the alias check. */
1700 /* Given INSN, which is an INSN list or the PATTERN of a single insn
1701 generated to perform a memory operation, look for any MEMs in either
1702 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
1703 volatile flags from REF into each of the MEMs found. If REF is not
1704 a MEM, don't do anything. */
1707 alpha_set_memflags (rtx insn
, rtx ref
)
1711 if (GET_CODE (ref
) != MEM
)
1714 /* This is only called from alpha.md, after having had something
1715 generated from one of the insn patterns. So if everything is
1716 zero, the pattern is already up-to-date. */
1717 if (!MEM_VOLATILE_P (ref
)
1718 && !MEM_IN_STRUCT_P (ref
)
1719 && !MEM_SCALAR_P (ref
)
1720 && !MEM_NOTRAP_P (ref
)
1721 && !MEM_READONLY_P (ref
))
1725 base_ptr
= &PATTERN (insn
);
1728 for_each_rtx (base_ptr
, alpha_set_memflags_1
, (void *) ref
);
1731 static rtx
alpha_emit_set_const (rtx
, enum machine_mode
, HOST_WIDE_INT
,
1734 /* Internal routine for alpha_emit_set_const to check for N or below insns.
1735 If NO_OUTPUT is true, then we only check to see if N insns are possible,
1736 and return pc_rtx if successful. */
1739 alpha_emit_set_const_1 (rtx target
, enum machine_mode mode
,
1740 HOST_WIDE_INT c
, int n
, bool no_output
)
1744 /* Use a pseudo if highly optimizing and still generating RTL. */
1746 = (flag_expensive_optimizations
&& !no_new_pseudos
? 0 : target
);
1749 /* If this is a sign-extended 32-bit constant, we can do this in at most
1750 three insns, so do it if we have enough insns left. We always have
1751 a sign-extended 32-bit constant when compiling on a narrow machine. */
1753 if (HOST_BITS_PER_WIDE_INT
!= 64
1754 || c
>> 31 == -1 || c
>> 31 == 0)
1756 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
1757 HOST_WIDE_INT tmp1
= c
- low
;
1758 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
1759 HOST_WIDE_INT extra
= 0;
1761 /* If HIGH will be interpreted as negative but the constant is
1762 positive, we must adjust it to do two ldha insns. */
1764 if ((high
& 0x8000) != 0 && c
>= 0)
1768 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
1771 if (c
== low
|| (low
== 0 && extra
== 0))
1773 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
1774 but that meant that we can't handle INT_MIN on 32-bit machines
1775 (like NT/Alpha), because we recurse indefinitely through
1776 emit_move_insn to gen_movdi. So instead, since we know exactly
1777 what we want, create it explicitly. */
1782 target
= gen_reg_rtx (mode
);
1783 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
1786 else if (n
>= 2 + (extra
!= 0))
1792 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (high
<< 16)));
1796 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16),
1799 /* As of 2002-02-23, addsi3 is only available when not optimizing.
1800 This means that if we go through expand_binop, we'll try to
1801 generate extensions, etc, which will require new pseudos, which
1802 will fail during some split phases. The SImode add patterns
1803 still exist, but are not named. So build the insns by hand. */
1808 subtarget
= gen_reg_rtx (mode
);
1809 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
1810 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
1816 target
= gen_reg_rtx (mode
);
1817 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
1818 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
1824 /* If we couldn't do it that way, try some other methods. But if we have
1825 no instructions left, don't bother. Likewise, if this is SImode and
1826 we can't make pseudos, we can't do anything since the expand_binop
1827 and expand_unop calls will widen and try to make pseudos. */
1829 if (n
== 1 || (mode
== SImode
&& no_new_pseudos
))
1832 /* Next, see if we can load a related constant and then shift and possibly
1833 negate it to get the constant we want. Try this once each increasing
1834 numbers of insns. */
1836 for (i
= 1; i
< n
; i
++)
1838 /* First, see if minus some low bits, we've an easy load of
1841 new = ((c
& 0xffff) ^ 0x8000) - 0x8000;
1844 temp
= alpha_emit_set_const (subtarget
, mode
, c
- new, i
, no_output
);
1849 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new),
1850 target
, 0, OPTAB_WIDEN
);
1854 /* Next try complementing. */
1855 temp
= alpha_emit_set_const (subtarget
, mode
, ~c
, i
, no_output
);
1860 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
1863 /* Next try to form a constant and do a left shift. We can do this
1864 if some low-order bits are zero; the exact_log2 call below tells
1865 us that information. The bits we are shifting out could be any
1866 value, but here we'll just try the 0- and sign-extended forms of
1867 the constant. To try to increase the chance of having the same
1868 constant in more than one insn, start at the highest number of
1869 bits to shift, but try all possibilities in case a ZAPNOT will
1872 bits
= exact_log2 (c
& -c
);
1874 for (; bits
> 0; bits
--)
1877 temp
= alpha_emit_set_const (subtarget
, mode
, new, i
, no_output
);
1880 new = (unsigned HOST_WIDE_INT
)c
>> bits
;
1881 temp
= alpha_emit_set_const (subtarget
, mode
, new,
1888 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
1889 target
, 0, OPTAB_WIDEN
);
1893 /* Now try high-order zero bits. Here we try the shifted-in bits as
1894 all zero and all ones. Be careful to avoid shifting outside the
1895 mode and to avoid shifting outside the host wide int size. */
1896 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
1897 confuse the recursive call and set all of the high 32 bits. */
1899 bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
1900 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64));
1902 for (; bits
> 0; bits
--)
1905 temp
= alpha_emit_set_const (subtarget
, mode
, new, i
, no_output
);
1908 new = (c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1);
1909 temp
= alpha_emit_set_const (subtarget
, mode
, new,
1916 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
1917 target
, 1, OPTAB_WIDEN
);
1921 /* Now try high-order 1 bits. We get that with a sign-extension.
1922 But one bit isn't enough here. Be careful to avoid shifting outside
1923 the mode and to avoid shifting outside the host wide int size. */
1925 bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
1926 - floor_log2 (~ c
) - 2);
1928 for (; bits
> 0; bits
--)
1931 temp
= alpha_emit_set_const (subtarget
, mode
, new, i
, no_output
);
1934 new = (c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1);
1935 temp
= alpha_emit_set_const (subtarget
, mode
, new,
1942 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
1943 target
, 0, OPTAB_WIDEN
);
1948 #if HOST_BITS_PER_WIDE_INT == 64
1949 /* Finally, see if can load a value into the target that is the same as the
1950 constant except that all bytes that are 0 are changed to be 0xff. If we
1951 can, then we can do a ZAPNOT to obtain the desired constant. */
1954 for (i
= 0; i
< 64; i
+= 8)
1955 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
1956 new |= (HOST_WIDE_INT
) 0xff << i
;
1958 /* We are only called for SImode and DImode. If this is SImode, ensure that
1959 we are sign extended to a full word. */
1962 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
1966 temp
= alpha_emit_set_const (subtarget
, mode
, new, n
- 1, no_output
);
1971 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new),
1972 target
, 0, OPTAB_WIDEN
);
1980 /* Try to output insns to set TARGET equal to the constant C if it can be
1981 done in less than N insns. Do all computations in MODE. Returns the place
1982 where the output has been placed if it can be done and the insns have been
1983 emitted. If it would take more than N insns, zero is returned and no
1984 insns and emitted. */
1987 alpha_emit_set_const (rtx target
, enum machine_mode mode
,
1988 HOST_WIDE_INT c
, int n
, bool no_output
)
1990 enum machine_mode orig_mode
= mode
;
1991 rtx orig_target
= target
;
1995 /* If we can't make any pseudos, TARGET is an SImode hard register, we
1996 can't load this constant in one insn, do this in DImode. */
1997 if (no_new_pseudos
&& mode
== SImode
1998 && GET_CODE (target
) == REG
&& REGNO (target
) < FIRST_PSEUDO_REGISTER
)
2000 result
= alpha_emit_set_const_1 (target
, mode
, c
, 1, no_output
);
2004 target
= no_output
? NULL
: gen_lowpart (DImode
, target
);
2007 else if (mode
== V8QImode
|| mode
== V4HImode
|| mode
== V2SImode
)
2009 target
= no_output
? NULL
: gen_lowpart (DImode
, target
);
2013 /* Try 1 insn, then 2, then up to N. */
2014 for (i
= 1; i
<= n
; i
++)
2016 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
, no_output
);
2024 insn
= get_last_insn ();
2025 set
= single_set (insn
);
2026 if (! CONSTANT_P (SET_SRC (set
)))
2027 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
2032 /* Allow for the case where we changed the mode of TARGET. */
2035 if (result
== target
)
2036 result
= orig_target
;
2037 else if (mode
!= orig_mode
)
2038 result
= gen_lowpart (orig_mode
, result
);
2044 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2045 fall back to a straight forward decomposition. We do this to avoid
2046 exponential run times encountered when looking for longer sequences
2047 with alpha_emit_set_const. */
2050 alpha_emit_set_long_const (rtx target
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
2052 HOST_WIDE_INT d1
, d2
, d3
, d4
;
2054 /* Decompose the entire word */
2055 #if HOST_BITS_PER_WIDE_INT >= 64
2056 if (c2
!= -(c1
< 0))
2058 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2060 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2061 c1
= (c1
- d2
) >> 32;
2062 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2064 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2068 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2070 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2074 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
2076 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2081 /* Construct the high word */
2084 emit_move_insn (target
, GEN_INT (d4
));
2086 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
2089 emit_move_insn (target
, GEN_INT (d3
));
2091 /* Shift it into place */
2092 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
2094 /* Add in the low bits. */
2096 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
2098 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
2103 /* Given an integral CONST_INT, CONST_DOUBLE, or CONST_VECTOR, return
2107 alpha_extract_integer (rtx x
, HOST_WIDE_INT
*p0
, HOST_WIDE_INT
*p1
)
2109 HOST_WIDE_INT i0
, i1
;
2111 if (GET_CODE (x
) == CONST_VECTOR
)
2112 x
= simplify_subreg (DImode
, x
, GET_MODE (x
), 0);
2115 if (GET_CODE (x
) == CONST_INT
)
2120 else if (HOST_BITS_PER_WIDE_INT
>= 64)
2122 i0
= CONST_DOUBLE_LOW (x
);
2127 i0
= CONST_DOUBLE_LOW (x
);
2128 i1
= CONST_DOUBLE_HIGH (x
);
2135 /* Implement LEGITIMATE_CONSTANT_P. This is all constants for which we
2136 are willing to load the value into a register via a move pattern.
2137 Normally this is all symbolic constants, integral constants that
2138 take three or fewer instructions, and floating-point zero. */
2141 alpha_legitimate_constant_p (rtx x
)
2143 enum machine_mode mode
= GET_MODE (x
);
2144 HOST_WIDE_INT i0
, i1
;
2146 switch (GET_CODE (x
))
2155 if (x
== CONST0_RTX (mode
))
2157 if (FLOAT_MODE_P (mode
))
2162 if (x
== CONST0_RTX (mode
))
2164 if (GET_MODE_CLASS (mode
) != MODE_VECTOR_INT
)
2166 if (GET_MODE_SIZE (mode
) != 8)
2172 if (TARGET_BUILD_CONSTANTS
)
2174 alpha_extract_integer (x
, &i0
, &i1
);
2175 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== (-i0
< 0))
2176 return alpha_emit_set_const_1 (x
, mode
, i0
, 3, true) != NULL
;
2184 /* Operand 1 is known to be a constant, and should require more than one
2185 instruction to load. Emit that multi-part load. */
2188 alpha_split_const_mov (enum machine_mode mode
, rtx
*operands
)
2190 HOST_WIDE_INT i0
, i1
;
2191 rtx temp
= NULL_RTX
;
2193 alpha_extract_integer (operands
[1], &i0
, &i1
);
2195 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
2196 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3, false);
2198 if (!temp
&& TARGET_BUILD_CONSTANTS
)
2199 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
2203 if (!rtx_equal_p (operands
[0], temp
))
2204 emit_move_insn (operands
[0], temp
);
2211 /* Expand a move instruction; return true if all work is done.
2212 We don't handle non-bwx subword loads here. */
2215 alpha_expand_mov (enum machine_mode mode
, rtx
*operands
)
2217 /* If the output is not a register, the input must be. */
2218 if (GET_CODE (operands
[0]) == MEM
2219 && ! reg_or_0_operand (operands
[1], mode
))
2220 operands
[1] = force_reg (mode
, operands
[1]);
2222 /* Allow legitimize_address to perform some simplifications. */
2223 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
2227 tmp
= alpha_legitimize_address (operands
[1], operands
[0], mode
);
2230 if (tmp
== operands
[0])
2237 /* Early out for non-constants and valid constants. */
2238 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
2241 /* Split large integers. */
2242 if (GET_CODE (operands
[1]) == CONST_INT
2243 || GET_CODE (operands
[1]) == CONST_DOUBLE
2244 || GET_CODE (operands
[1]) == CONST_VECTOR
)
2246 if (alpha_split_const_mov (mode
, operands
))
2250 /* Otherwise we've nothing left but to drop the thing to memory. */
2251 operands
[1] = force_const_mem (mode
, operands
[1]);
2252 if (reload_in_progress
)
2254 emit_move_insn (operands
[0], XEXP (operands
[1], 0));
2255 operands
[1] = copy_rtx (operands
[1]);
2256 XEXP (operands
[1], 0) = operands
[0];
2259 operands
[1] = validize_mem (operands
[1]);
2263 /* Expand a non-bwx QImode or HImode move instruction;
2264 return true if all work is done. */
2267 alpha_expand_mov_nobwx (enum machine_mode mode
, rtx
*operands
)
2269 /* If the output is not a register, the input must be. */
2270 if (GET_CODE (operands
[0]) == MEM
)
2271 operands
[1] = force_reg (mode
, operands
[1]);
2273 /* Handle four memory cases, unaligned and aligned for either the input
2274 or the output. The only case where we can be called during reload is
2275 for aligned loads; all other cases require temporaries. */
2277 if (GET_CODE (operands
[1]) == MEM
2278 || (GET_CODE (operands
[1]) == SUBREG
2279 && GET_CODE (SUBREG_REG (operands
[1])) == MEM
)
2280 || (reload_in_progress
&& GET_CODE (operands
[1]) == REG
2281 && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
)
2282 || (reload_in_progress
&& GET_CODE (operands
[1]) == SUBREG
2283 && GET_CODE (SUBREG_REG (operands
[1])) == REG
2284 && REGNO (SUBREG_REG (operands
[1])) >= FIRST_PSEUDO_REGISTER
))
2286 if (aligned_memory_operand (operands
[1], mode
))
2288 if (reload_in_progress
)
2290 emit_insn ((mode
== QImode
2291 ? gen_reload_inqi_help
2292 : gen_reload_inhi_help
)
2293 (operands
[0], operands
[1],
2294 gen_rtx_REG (SImode
, REGNO (operands
[0]))));
2298 rtx aligned_mem
, bitnum
;
2299 rtx scratch
= gen_reg_rtx (SImode
);
2303 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
2305 subtarget
= operands
[0];
2306 if (GET_CODE (subtarget
) == REG
)
2307 subtarget
= gen_lowpart (DImode
, subtarget
), copyout
= false;
2309 subtarget
= gen_reg_rtx (DImode
), copyout
= true;
2311 emit_insn ((mode
== QImode
2312 ? gen_aligned_loadqi
2313 : gen_aligned_loadhi
)
2314 (subtarget
, aligned_mem
, bitnum
, scratch
));
2317 emit_move_insn (operands
[0], gen_lowpart (mode
, subtarget
));
2322 /* Don't pass these as parameters since that makes the generated
2323 code depend on parameter evaluation order which will cause
2324 bootstrap failures. */
2326 rtx temp1
, temp2
, seq
, subtarget
;
2329 temp1
= gen_reg_rtx (DImode
);
2330 temp2
= gen_reg_rtx (DImode
);
2332 subtarget
= operands
[0];
2333 if (GET_CODE (subtarget
) == REG
)
2334 subtarget
= gen_lowpart (DImode
, subtarget
), copyout
= false;
2336 subtarget
= gen_reg_rtx (DImode
), copyout
= true;
2338 seq
= ((mode
== QImode
2339 ? gen_unaligned_loadqi
2340 : gen_unaligned_loadhi
)
2341 (subtarget
, get_unaligned_address (operands
[1], 0),
2343 alpha_set_memflags (seq
, operands
[1]);
2347 emit_move_insn (operands
[0], gen_lowpart (mode
, subtarget
));
2352 if (GET_CODE (operands
[0]) == MEM
2353 || (GET_CODE (operands
[0]) == SUBREG
2354 && GET_CODE (SUBREG_REG (operands
[0])) == MEM
)
2355 || (reload_in_progress
&& GET_CODE (operands
[0]) == REG
2356 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
)
2357 || (reload_in_progress
&& GET_CODE (operands
[0]) == SUBREG
2358 && GET_CODE (SUBREG_REG (operands
[0])) == REG
2359 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
2361 if (aligned_memory_operand (operands
[0], mode
))
2363 rtx aligned_mem
, bitnum
;
2364 rtx temp1
= gen_reg_rtx (SImode
);
2365 rtx temp2
= gen_reg_rtx (SImode
);
2367 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
2369 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
2374 rtx temp1
= gen_reg_rtx (DImode
);
2375 rtx temp2
= gen_reg_rtx (DImode
);
2376 rtx temp3
= gen_reg_rtx (DImode
);
2377 rtx seq
= ((mode
== QImode
2378 ? gen_unaligned_storeqi
2379 : gen_unaligned_storehi
)
2380 (get_unaligned_address (operands
[0], 0),
2381 operands
[1], temp1
, temp2
, temp3
));
2383 alpha_set_memflags (seq
, operands
[0]);
2392 /* Implement the movmisalign patterns. One of the operands is a memory
2393 that is not naturally aligned. Emit instructions to load it. */
2396 alpha_expand_movmisalign (enum machine_mode mode
, rtx
*operands
)
2398 /* Honor misaligned loads, for those we promised to do so. */
2399 if (MEM_P (operands
[1]))
2403 if (register_operand (operands
[0], mode
))
2406 tmp
= gen_reg_rtx (mode
);
2408 alpha_expand_unaligned_load (tmp
, operands
[1], 8, 0, 0);
2409 if (tmp
!= operands
[0])
2410 emit_move_insn (operands
[0], tmp
);
2412 else if (MEM_P (operands
[0]))
2414 if (!reg_or_0_operand (operands
[1], mode
))
2415 operands
[1] = force_reg (mode
, operands
[1]);
2416 alpha_expand_unaligned_store (operands
[0], operands
[1], 8, 0);
2422 /* Generate an unsigned DImode to FP conversion. This is the same code
2423 optabs would emit if we didn't have TFmode patterns.
2425 For SFmode, this is the only construction I've found that can pass
2426 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2427 intermediates will work, because you'll get intermediate rounding
2428 that ruins the end result. Some of this could be fixed by turning
2429 on round-to-positive-infinity, but that requires diddling the fpsr,
2430 which kills performance. I tried turning this around and converting
2431 to a negative number, so that I could turn on /m, but either I did
2432 it wrong or there's something else cause I wound up with the exact
2433 same single-bit error. There is a branch-less form of this same code:
2444 fcmoveq $f10,$f11,$f0
2446 I'm not using it because it's the same number of instructions as
2447 this branch-full form, and it has more serialized long latency
2448 instructions on the critical path.
2450 For DFmode, we can avoid rounding errors by breaking up the word
2451 into two pieces, converting them separately, and adding them back:
2453 LC0: .long 0,0x5f800000
2458 cpyse $f11,$f31,$f10
2459 cpyse $f31,$f11,$f11
2467 This doesn't seem to be a clear-cut win over the optabs form.
2468 It probably all depends on the distribution of numbers being
2469 converted -- in the optabs form, all but high-bit-set has a
2470 much lower minimum execution time. */
2473 alpha_emit_floatuns (rtx operands
[2])
2475 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
2476 enum machine_mode mode
;
2479 in
= force_reg (DImode
, operands
[1]);
2480 mode
= GET_MODE (out
);
2481 neglab
= gen_label_rtx ();
2482 donelab
= gen_label_rtx ();
2483 i0
= gen_reg_rtx (DImode
);
2484 i1
= gen_reg_rtx (DImode
);
2485 f0
= gen_reg_rtx (mode
);
2487 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
2489 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
2490 emit_jump_insn (gen_jump (donelab
));
2493 emit_label (neglab
);
2495 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
2496 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
2497 emit_insn (gen_iordi3 (i0
, i0
, i1
));
2498 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
2499 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
2501 emit_label (donelab
);
2504 /* Generate the comparison for a conditional branch. */
2507 alpha_emit_conditional_branch (enum rtx_code code
)
2509 enum rtx_code cmp_code
, branch_code
;
2510 enum machine_mode cmp_mode
, branch_mode
= VOIDmode
;
2511 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
2514 if (alpha_compare
.fp_p
&& GET_MODE (op0
) == TFmode
)
2516 if (! TARGET_HAS_XFLOATING_LIBS
)
2519 /* X_floating library comparison functions return
2523 Convert the compare against the raw return value. */
2545 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
2547 alpha_compare
.fp_p
= 0;
2550 /* The general case: fold the comparison code to the types of compares
2551 that we have, choosing the branch as necessary. */
2554 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2556 /* We have these compares: */
2557 cmp_code
= code
, branch_code
= NE
;
2562 /* These must be reversed. */
2563 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
2566 case GE
: case GT
: case GEU
: case GTU
:
2567 /* For FP, we swap them, for INT, we reverse them. */
2568 if (alpha_compare
.fp_p
)
2570 cmp_code
= swap_condition (code
);
2572 tem
= op0
, op0
= op1
, op1
= tem
;
2576 cmp_code
= reverse_condition (code
);
2585 if (alpha_compare
.fp_p
)
2588 if (flag_unsafe_math_optimizations
)
2590 /* When we are not as concerned about non-finite values, and we
2591 are comparing against zero, we can branch directly. */
2592 if (op1
== CONST0_RTX (DFmode
))
2593 cmp_code
= UNKNOWN
, branch_code
= code
;
2594 else if (op0
== CONST0_RTX (DFmode
))
2596 /* Undo the swap we probably did just above. */
2597 tem
= op0
, op0
= op1
, op1
= tem
;
2598 branch_code
= swap_condition (cmp_code
);
2604 /* ??? We mark the branch mode to be CCmode to prevent the
2605 compare and branch from being combined, since the compare
2606 insn follows IEEE rules that the branch does not. */
2607 branch_mode
= CCmode
;
2614 /* The following optimizations are only for signed compares. */
2615 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
2617 /* Whee. Compare and branch against 0 directly. */
2618 if (op1
== const0_rtx
)
2619 cmp_code
= UNKNOWN
, branch_code
= code
;
2621 /* If the constants doesn't fit into an immediate, but can
2622 be generated by lda/ldah, we adjust the argument and
2623 compare against zero, so we can use beq/bne directly. */
2624 /* ??? Don't do this when comparing against symbols, otherwise
2625 we'll reduce (&x == 0x1234) to (&x-0x1234 == 0), which will
2626 be declared false out of hand (at least for non-weak). */
2627 else if (GET_CODE (op1
) == CONST_INT
2628 && (code
== EQ
|| code
== NE
)
2629 && !(symbolic_operand (op0
, VOIDmode
)
2630 || (GET_CODE (op0
) == REG
&& REG_POINTER (op0
))))
2632 HOST_WIDE_INT v
= INTVAL (op1
), n
= -v
;
2634 if (! CONST_OK_FOR_LETTER_P (v
, 'I')
2635 && (CONST_OK_FOR_LETTER_P (n
, 'K')
2636 || CONST_OK_FOR_LETTER_P (n
, 'L')))
2638 cmp_code
= PLUS
, branch_code
= code
;
2644 if (!reg_or_0_operand (op0
, DImode
))
2645 op0
= force_reg (DImode
, op0
);
2646 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
2647 op1
= force_reg (DImode
, op1
);
2650 /* Emit an initial compare instruction, if necessary. */
2652 if (cmp_code
!= UNKNOWN
)
2654 tem
= gen_reg_rtx (cmp_mode
);
2655 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
2658 /* Zero the operands. */
2659 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
2661 /* Return the branch comparison. */
2662 return gen_rtx_fmt_ee (branch_code
, branch_mode
, tem
, CONST0_RTX (cmp_mode
));
2665 /* Certain simplifications can be done to make invalid setcc operations
2666 valid. Return the final comparison, or NULL if we can't work. */
2669 alpha_emit_setcc (enum rtx_code code
)
2671 enum rtx_code cmp_code
;
2672 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
2673 int fp_p
= alpha_compare
.fp_p
;
2676 /* Zero the operands. */
2677 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
2679 if (fp_p
&& GET_MODE (op0
) == TFmode
)
2681 if (! TARGET_HAS_XFLOATING_LIBS
)
2684 /* X_floating library comparison functions return
2688 Convert the compare against the raw return value. */
2690 if (code
== UNORDERED
|| code
== ORDERED
)
2695 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
2699 if (code
== UNORDERED
)
2701 else if (code
== ORDERED
)
2707 if (fp_p
&& !TARGET_FIX
)
2710 /* The general case: fold the comparison code to the types of compares
2711 that we have, choosing the branch as necessary. */
2716 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2718 /* We have these compares. */
2720 cmp_code
= code
, code
= NE
;
2724 if (!fp_p
&& op1
== const0_rtx
)
2729 cmp_code
= reverse_condition (code
);
2733 case GE
: case GT
: case GEU
: case GTU
:
2734 /* These normally need swapping, but for integer zero we have
2735 special patterns that recognize swapped operands. */
2736 if (!fp_p
&& op1
== const0_rtx
)
2738 code
= swap_condition (code
);
2740 cmp_code
= code
, code
= NE
;
2741 tmp
= op0
, op0
= op1
, op1
= tmp
;
2750 if (!register_operand (op0
, DImode
))
2751 op0
= force_reg (DImode
, op0
);
2752 if (!reg_or_8bit_operand (op1
, DImode
))
2753 op1
= force_reg (DImode
, op1
);
2756 /* Emit an initial compare instruction, if necessary. */
2757 if (cmp_code
!= UNKNOWN
)
2759 enum machine_mode mode
= fp_p
? DFmode
: DImode
;
2761 tmp
= gen_reg_rtx (mode
);
2762 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
2763 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
)));
2765 op0
= fp_p
? gen_lowpart (DImode
, tmp
) : tmp
;
2769 /* Return the setcc comparison. */
2770 return gen_rtx_fmt_ee (code
, DImode
, op0
, op1
);
2774 /* Rewrite a comparison against zero CMP of the form
2775 (CODE (cc0) (const_int 0)) so it can be written validly in
2776 a conditional move (if_then_else CMP ...).
2777 If both of the operands that set cc0 are nonzero we must emit
2778 an insn to perform the compare (it can't be done within
2779 the conditional move). */
2782 alpha_emit_conditional_move (rtx cmp
, enum machine_mode mode
)
2784 enum rtx_code code
= GET_CODE (cmp
);
2785 enum rtx_code cmov_code
= NE
;
2786 rtx op0
= alpha_compare
.op0
;
2787 rtx op1
= alpha_compare
.op1
;
2788 int fp_p
= alpha_compare
.fp_p
;
2789 enum machine_mode cmp_mode
2790 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
2791 enum machine_mode cmp_op_mode
= fp_p
? DFmode
: DImode
;
2792 enum machine_mode cmov_mode
= VOIDmode
;
2793 int local_fast_math
= flag_unsafe_math_optimizations
;
2796 /* Zero the operands. */
2797 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
2799 if (fp_p
!= FLOAT_MODE_P (mode
))
2801 enum rtx_code cmp_code
;
2806 /* If we have fp<->int register move instructions, do a cmov by
2807 performing the comparison in fp registers, and move the
2808 zero/nonzero value to integer registers, where we can then
2809 use a normal cmov, or vice-versa. */
2813 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2814 /* We have these compares. */
2815 cmp_code
= code
, code
= NE
;
2819 /* This must be reversed. */
2820 cmp_code
= EQ
, code
= EQ
;
2823 case GE
: case GT
: case GEU
: case GTU
:
2824 /* These normally need swapping, but for integer zero we have
2825 special patterns that recognize swapped operands. */
2826 if (!fp_p
&& op1
== const0_rtx
)
2827 cmp_code
= code
, code
= NE
;
2830 cmp_code
= swap_condition (code
);
2832 tem
= op0
, op0
= op1
, op1
= tem
;
2840 tem
= gen_reg_rtx (cmp_op_mode
);
2841 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
2842 gen_rtx_fmt_ee (cmp_code
, cmp_op_mode
,
2845 cmp_mode
= cmp_op_mode
= fp_p
? DImode
: DFmode
;
2846 op0
= gen_lowpart (cmp_op_mode
, tem
);
2847 op1
= CONST0_RTX (cmp_op_mode
);
2849 local_fast_math
= 1;
2852 /* We may be able to use a conditional move directly.
2853 This avoids emitting spurious compares. */
2854 if (signed_comparison_operator (cmp
, VOIDmode
)
2855 && (!fp_p
|| local_fast_math
)
2856 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
2857 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
2859 /* We can't put the comparison inside the conditional move;
2860 emit a compare instruction and put that inside the
2861 conditional move. Make sure we emit only comparisons we have;
2862 swap or reverse as necessary. */
2869 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2870 /* We have these compares: */
2874 /* This must be reversed. */
2875 code
= reverse_condition (code
);
2879 case GE
: case GT
: case GEU
: case GTU
:
2880 /* These must be swapped. */
2881 if (op1
!= CONST0_RTX (cmp_mode
))
2883 code
= swap_condition (code
);
2884 tem
= op0
, op0
= op1
, op1
= tem
;
2894 if (!reg_or_0_operand (op0
, DImode
))
2895 op0
= force_reg (DImode
, op0
);
2896 if (!reg_or_8bit_operand (op1
, DImode
))
2897 op1
= force_reg (DImode
, op1
);
2900 /* ??? We mark the branch mode to be CCmode to prevent the compare
2901 and cmov from being combined, since the compare insn follows IEEE
2902 rules that the cmov does not. */
2903 if (fp_p
&& !local_fast_math
)
2906 tem
= gen_reg_rtx (cmp_op_mode
);
2907 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_op_mode
, op0
, op1
));
2908 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_op_mode
));
2911 /* Simplify a conditional move of two constants into a setcc with
2912 arithmetic. This is done with a splitter since combine would
2913 just undo the work if done during code generation. It also catches
2914 cases we wouldn't have before cse. */
2917 alpha_split_conditional_move (enum rtx_code code
, rtx dest
, rtx cond
,
2918 rtx t_rtx
, rtx f_rtx
)
2920 HOST_WIDE_INT t
, f
, diff
;
2921 enum machine_mode mode
;
2922 rtx target
, subtarget
, tmp
;
2924 mode
= GET_MODE (dest
);
2929 if (((code
== NE
|| code
== EQ
) && diff
< 0)
2930 || (code
== GE
|| code
== GT
))
2932 code
= reverse_condition (code
);
2933 diff
= t
, t
= f
, f
= diff
;
2937 subtarget
= target
= dest
;
2940 target
= gen_lowpart (DImode
, dest
);
2941 if (! no_new_pseudos
)
2942 subtarget
= gen_reg_rtx (DImode
);
2946 /* Below, we must be careful to use copy_rtx on target and subtarget
2947 in intermediate insns, as they may be a subreg rtx, which may not
2950 if (f
== 0 && exact_log2 (diff
) > 0
2951 /* On EV6, we've got enough shifters to make non-arithmetic shifts
2952 viable over a longer latency cmove. On EV5, the E0 slot is a
2953 scarce resource, and on EV4 shift has the same latency as a cmove. */
2954 && (diff
<= 8 || alpha_tune
== PROCESSOR_EV6
))
2956 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
2957 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
2959 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
2960 GEN_INT (exact_log2 (t
)));
2961 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
2963 else if (f
== 0 && t
== -1)
2965 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
2966 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
2968 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
2970 else if (diff
== 1 || diff
== 4 || diff
== 8)
2974 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
2975 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
2978 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
2981 add_op
= GEN_INT (f
);
2982 if (sext_add_operand (add_op
, mode
))
2984 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
2986 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
2987 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
2999 /* Look up the function X_floating library function name for the
3002 struct xfloating_op
GTY(())
3004 const enum rtx_code code
;
3005 const char *const GTY((skip
)) osf_func
;
3006 const char *const GTY((skip
)) vms_func
;
3010 static GTY(()) struct xfloating_op xfloating_ops
[] =
3012 { PLUS
, "_OtsAddX", "OTS$ADD_X", 0 },
3013 { MINUS
, "_OtsSubX", "OTS$SUB_X", 0 },
3014 { MULT
, "_OtsMulX", "OTS$MUL_X", 0 },
3015 { DIV
, "_OtsDivX", "OTS$DIV_X", 0 },
3016 { EQ
, "_OtsEqlX", "OTS$EQL_X", 0 },
3017 { NE
, "_OtsNeqX", "OTS$NEQ_X", 0 },
3018 { LT
, "_OtsLssX", "OTS$LSS_X", 0 },
3019 { LE
, "_OtsLeqX", "OTS$LEQ_X", 0 },
3020 { GT
, "_OtsGtrX", "OTS$GTR_X", 0 },
3021 { GE
, "_OtsGeqX", "OTS$GEQ_X", 0 },
3022 { FIX
, "_OtsCvtXQ", "OTS$CVTXQ", 0 },
3023 { FLOAT
, "_OtsCvtQX", "OTS$CVTQX", 0 },
3024 { UNSIGNED_FLOAT
, "_OtsCvtQUX", "OTS$CVTQUX", 0 },
3025 { FLOAT_EXTEND
, "_OtsConvertFloatTX", "OTS$CVT_FLOAT_T_X", 0 },
3026 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT", "OTS$CVT_FLOAT_X_T", 0 }
3029 static GTY(()) struct xfloating_op vax_cvt_ops
[] =
3031 { FLOAT_EXTEND
, "_OtsConvertFloatGX", "OTS$CVT_FLOAT_G_X", 0 },
3032 { FLOAT_TRUNCATE
, "_OtsConvertFloatXG", "OTS$CVT_FLOAT_X_G", 0 }
3036 alpha_lookup_xfloating_lib_func (enum rtx_code code
)
3038 struct xfloating_op
*ops
= xfloating_ops
;
3039 long n
= ARRAY_SIZE (xfloating_ops
);
3042 /* How irritating. Nothing to key off for the main table. */
3043 if (TARGET_FLOAT_VAX
&& (code
== FLOAT_EXTEND
|| code
== FLOAT_TRUNCATE
))
3046 n
= ARRAY_SIZE (vax_cvt_ops
);
3049 for (i
= 0; i
< n
; ++i
, ++ops
)
3050 if (ops
->code
== code
)
3052 rtx func
= ops
->libcall
;
3055 func
= init_one_libfunc (TARGET_ABI_OPEN_VMS
3056 ? ops
->vms_func
: ops
->osf_func
);
3057 ops
->libcall
= func
;
3065 /* Most X_floating operations take the rounding mode as an argument.
3066 Compute that here. */
3069 alpha_compute_xfloating_mode_arg (enum rtx_code code
,
3070 enum alpha_fp_rounding_mode round
)
3076 case ALPHA_FPRM_NORM
:
3079 case ALPHA_FPRM_MINF
:
3082 case ALPHA_FPRM_CHOP
:
3085 case ALPHA_FPRM_DYN
:
3091 /* XXX For reference, round to +inf is mode = 3. */
3094 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
3100 /* Emit an X_floating library function call.
3102 Note that these functions do not follow normal calling conventions:
3103 TFmode arguments are passed in two integer registers (as opposed to
3104 indirect); TFmode return values appear in R16+R17.
3106 FUNC is the function to call.
3107 TARGET is where the output belongs.
3108 OPERANDS are the inputs.
3109 NOPERANDS is the count of inputs.
3110 EQUIV is the expression equivalent for the function.
3114 alpha_emit_xfloating_libcall (rtx func
, rtx target
, rtx operands
[],
3115 int noperands
, rtx equiv
)
3117 rtx usage
= NULL_RTX
, tmp
, reg
;
3122 for (i
= 0; i
< noperands
; ++i
)
3124 switch (GET_MODE (operands
[i
]))
3127 reg
= gen_rtx_REG (TFmode
, regno
);
3132 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
3137 if (GET_CODE (operands
[i
]) != CONST_INT
)
3141 reg
= gen_rtx_REG (DImode
, regno
);
3149 emit_move_insn (reg
, operands
[i
]);
3150 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
3153 switch (GET_MODE (target
))
3156 reg
= gen_rtx_REG (TFmode
, 16);
3159 reg
= gen_rtx_REG (DFmode
, 32);
3162 reg
= gen_rtx_REG (DImode
, 0);
3168 tmp
= gen_rtx_MEM (QImode
, func
);
3169 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
3170 const0_rtx
, const0_rtx
));
3171 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
3172 CONST_OR_PURE_CALL_P (tmp
) = 1;
3177 emit_libcall_block (tmp
, target
, reg
, equiv
);
3180 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3183 alpha_emit_xfloating_arith (enum rtx_code code
, rtx operands
[])
3187 rtx out_operands
[3];
3189 func
= alpha_lookup_xfloating_lib_func (code
);
3190 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3192 out_operands
[0] = operands
[1];
3193 out_operands
[1] = operands
[2];
3194 out_operands
[2] = GEN_INT (mode
);
3195 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
3196 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
3200 /* Emit an X_floating library function call for a comparison. */
3203 alpha_emit_xfloating_compare (enum rtx_code code
, rtx op0
, rtx op1
)
3206 rtx out
, operands
[2];
3208 func
= alpha_lookup_xfloating_lib_func (code
);
3212 out
= gen_reg_rtx (DImode
);
3214 /* ??? Strange mode for equiv because what's actually returned
3215 is -1,0,1, not a proper boolean value. */
3216 alpha_emit_xfloating_libcall (func
, out
, operands
, 2,
3217 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
));
3222 /* Emit an X_floating library function call for a conversion. */
3225 alpha_emit_xfloating_cvt (enum rtx_code orig_code
, rtx operands
[])
3227 int noperands
= 1, mode
;
3228 rtx out_operands
[2];
3230 enum rtx_code code
= orig_code
;
3232 if (code
== UNSIGNED_FIX
)
3235 func
= alpha_lookup_xfloating_lib_func (code
);
3237 out_operands
[0] = operands
[1];
3242 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
3243 out_operands
[1] = GEN_INT (mode
);
3246 case FLOAT_TRUNCATE
:
3247 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3248 out_operands
[1] = GEN_INT (mode
);
3255 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
3256 gen_rtx_fmt_e (orig_code
,
3257 GET_MODE (operands
[0]),
3261 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3262 OP[0] into OP[0,1]. Naturally, output operand ordering is
3266 alpha_split_tfmode_pair (rtx operands
[4])
3268 if (GET_CODE (operands
[1]) == REG
)
3270 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
3271 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
3273 else if (GET_CODE (operands
[1]) == MEM
)
3275 operands
[3] = adjust_address (operands
[1], DImode
, 8);
3276 operands
[2] = adjust_address (operands
[1], DImode
, 0);
3278 else if (operands
[1] == CONST0_RTX (TFmode
))
3279 operands
[2] = operands
[3] = const0_rtx
;
3283 if (GET_CODE (operands
[0]) == REG
)
3285 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
3286 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
3288 else if (GET_CODE (operands
[0]) == MEM
)
3290 operands
[1] = adjust_address (operands
[0], DImode
, 8);
3291 operands
[0] = adjust_address (operands
[0], DImode
, 0);
3297 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3298 op2 is a register containing the sign bit, operation is the
3299 logical operation to be performed. */
3302 alpha_split_tfmode_frobsign (rtx operands
[3], rtx (*operation
) (rtx
, rtx
, rtx
))
3304 rtx high_bit
= operands
[2];
3308 alpha_split_tfmode_pair (operands
);
3310 /* Detect three flavors of operand overlap. */
3312 if (rtx_equal_p (operands
[0], operands
[2]))
3314 else if (rtx_equal_p (operands
[1], operands
[2]))
3316 if (rtx_equal_p (operands
[0], high_bit
))
3323 emit_move_insn (operands
[0], operands
[2]);
3325 /* ??? If the destination overlaps both source tf and high_bit, then
3326 assume source tf is dead in its entirety and use the other half
3327 for a scratch register. Otherwise "scratch" is just the proper
3328 destination register. */
3329 scratch
= operands
[move
< 2 ? 1 : 3];
3331 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
3335 emit_move_insn (operands
[0], operands
[2]);
3337 emit_move_insn (operands
[1], scratch
);
3341 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3345 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3346 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3347 lda r3,X(r11) lda r3,X+2(r11)
3348 extwl r1,r3,r1 extql r1,r3,r1
3349 extwh r2,r3,r2 extqh r2,r3,r2
3350 or r1.r2.r1 or r1,r2,r1
3353 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3354 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3355 lda r3,X(r11) lda r3,X(r11)
3356 extll r1,r3,r1 extll r1,r3,r1
3357 extlh r2,r3,r2 extlh r2,r3,r2
3358 or r1.r2.r1 addl r1,r2,r1
3360 quad: ldq_u r1,X(r11)
3369 alpha_expand_unaligned_load (rtx tgt
, rtx mem
, HOST_WIDE_INT size
,
3370 HOST_WIDE_INT ofs
, int sign
)
3372 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
3373 enum machine_mode mode
;
3375 if (TARGET_BWX
&& size
== 2)
3377 meml
= adjust_address (mem
, QImode
, ofs
);
3378 memh
= adjust_address (mem
, QImode
, ofs
+1);
3379 if (BYTES_BIG_ENDIAN
)
3380 tmp
= meml
, meml
= memh
, memh
= tmp
;
3381 extl
= gen_reg_rtx (DImode
);
3382 exth
= gen_reg_rtx (DImode
);
3383 emit_insn (gen_zero_extendqidi2 (extl
, meml
));
3384 emit_insn (gen_zero_extendqidi2 (exth
, memh
));
3385 exth
= expand_simple_binop (DImode
, ASHIFT
, exth
, GEN_INT (8),
3386 NULL
, 1, OPTAB_LIB_WIDEN
);
3387 addr
= expand_simple_binop (DImode
, IOR
, extl
, exth
,
3388 NULL
, 1, OPTAB_LIB_WIDEN
);
3390 if (sign
&& GET_MODE (tgt
) != HImode
)
3392 addr
= gen_lowpart (HImode
, addr
);
3393 emit_insn (gen_extend_insn (tgt
, addr
, GET_MODE (tgt
), HImode
, 0));
3397 if (GET_MODE (tgt
) != DImode
)
3398 addr
= gen_lowpart (GET_MODE (tgt
), addr
);
3399 emit_move_insn (tgt
, addr
);
3404 meml
= gen_reg_rtx (DImode
);
3405 memh
= gen_reg_rtx (DImode
);
3406 addr
= gen_reg_rtx (DImode
);
3407 extl
= gen_reg_rtx (DImode
);
3408 exth
= gen_reg_rtx (DImode
);
3410 mema
= XEXP (mem
, 0);
3411 if (GET_CODE (mema
) == LO_SUM
)
3412 mema
= force_reg (Pmode
, mema
);
3414 /* AND addresses cannot be in any alias set, since they may implicitly
3415 alias surrounding code. Ideally we'd have some alias set that
3416 covered all types except those with alignment 8 or higher. */
3418 tmp
= change_address (mem
, DImode
,
3419 gen_rtx_AND (DImode
,
3420 plus_constant (mema
, ofs
),
3422 set_mem_alias_set (tmp
, 0);
3423 emit_move_insn (meml
, tmp
);
3425 tmp
= change_address (mem
, DImode
,
3426 gen_rtx_AND (DImode
,
3427 plus_constant (mema
, ofs
+ size
- 1),
3429 set_mem_alias_set (tmp
, 0);
3430 emit_move_insn (memh
, tmp
);
3432 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
3434 emit_move_insn (addr
, plus_constant (mema
, -1));
3436 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3437 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
3439 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3440 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
3441 addr
, 1, OPTAB_WIDEN
);
3443 else if (sign
&& size
== 2)
3445 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
3447 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
3448 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3450 /* We must use tgt here for the target. Alpha-vms port fails if we use
3451 addr for the target, because addr is marked as a pointer and combine
3452 knows that pointers are always sign-extended 32 bit values. */
3453 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3454 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
3455 addr
, 1, OPTAB_WIDEN
);
3459 if (WORDS_BIG_ENDIAN
)
3461 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
3465 emit_insn (gen_extwh_be (extl
, meml
, addr
));
3470 emit_insn (gen_extlh_be (extl
, meml
, addr
));
3475 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3482 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
3486 emit_move_insn (addr
, plus_constant (mema
, ofs
));
3487 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
3491 emit_insn (gen_extwh_le (exth
, memh
, addr
));
3496 emit_insn (gen_extlh_le (exth
, memh
, addr
));
3501 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3510 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
3511 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
3516 emit_move_insn (tgt
, gen_lowpart (GET_MODE (tgt
), addr
));
3519 /* Similarly, use ins and msk instructions to perform unaligned stores. */
3522 alpha_expand_unaligned_store (rtx dst
, rtx src
,
3523 HOST_WIDE_INT size
, HOST_WIDE_INT ofs
)
3525 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
3527 if (TARGET_BWX
&& size
== 2)
3529 if (src
!= const0_rtx
)
3531 dstl
= gen_lowpart (QImode
, src
);
3532 dsth
= expand_simple_binop (DImode
, LSHIFTRT
, src
, GEN_INT (8),
3533 NULL
, 1, OPTAB_LIB_WIDEN
);
3534 dsth
= gen_lowpart (QImode
, dsth
);
3537 dstl
= dsth
= const0_rtx
;
3539 meml
= adjust_address (dst
, QImode
, ofs
);
3540 memh
= adjust_address (dst
, QImode
, ofs
+1);
3541 if (BYTES_BIG_ENDIAN
)
3542 addr
= meml
, meml
= memh
, memh
= addr
;
3544 emit_move_insn (meml
, dstl
);
3545 emit_move_insn (memh
, dsth
);
3549 dstl
= gen_reg_rtx (DImode
);
3550 dsth
= gen_reg_rtx (DImode
);
3551 insl
= gen_reg_rtx (DImode
);
3552 insh
= gen_reg_rtx (DImode
);
3554 dsta
= XEXP (dst
, 0);
3555 if (GET_CODE (dsta
) == LO_SUM
)
3556 dsta
= force_reg (Pmode
, dsta
);
3558 /* AND addresses cannot be in any alias set, since they may implicitly
3559 alias surrounding code. Ideally we'd have some alias set that
3560 covered all types except those with alignment 8 or higher. */
3562 meml
= change_address (dst
, DImode
,
3563 gen_rtx_AND (DImode
,
3564 plus_constant (dsta
, ofs
),
3566 set_mem_alias_set (meml
, 0);
3568 memh
= change_address (dst
, DImode
,
3569 gen_rtx_AND (DImode
,
3570 plus_constant (dsta
, ofs
+ size
- 1),
3572 set_mem_alias_set (memh
, 0);
3574 emit_move_insn (dsth
, memh
);
3575 emit_move_insn (dstl
, meml
);
3576 if (WORDS_BIG_ENDIAN
)
3578 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
3580 if (src
!= const0_rtx
)
3585 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
3588 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
3591 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
3594 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
3595 GEN_INT (size
*8), addr
));
3601 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
3605 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
3606 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
3610 emit_insn (gen_mskxl_be (dsth
, dsth
, constm1_rtx
, addr
));
3614 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
3618 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
3620 if (src
!= CONST0_RTX (GET_MODE (src
)))
3622 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
3623 GEN_INT (size
*8), addr
));
3628 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
3631 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
3634 emit_insn (gen_insql_le (insl
, src
, addr
));
3639 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
3644 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
3648 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
3649 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
3653 emit_insn (gen_mskxl_le (dstl
, dstl
, constm1_rtx
, addr
));
3658 if (src
!= CONST0_RTX (GET_MODE (src
)))
3660 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
3661 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
3664 if (WORDS_BIG_ENDIAN
)
3666 emit_move_insn (meml
, dstl
);
3667 emit_move_insn (memh
, dsth
);
3671 /* Must store high before low for degenerate case of aligned. */
3672 emit_move_insn (memh
, dsth
);
3673 emit_move_insn (meml
, dstl
);
3677 /* The block move code tries to maximize speed by separating loads and
3678 stores at the expense of register pressure: we load all of the data
3679 before we store it back out. There are two secondary effects worth
3680 mentioning, that this speeds copying to/from aligned and unaligned
3681 buffers, and that it makes the code significantly easier to write. */
3683 #define MAX_MOVE_WORDS 8
3685 /* Load an integral number of consecutive unaligned quadwords. */
3688 alpha_expand_unaligned_load_words (rtx
*out_regs
, rtx smem
,
3689 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
3691 rtx
const im8
= GEN_INT (-8);
3692 rtx
const i64
= GEN_INT (64);
3693 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
3694 rtx sreg
, areg
, tmp
, smema
;
3697 smema
= XEXP (smem
, 0);
3698 if (GET_CODE (smema
) == LO_SUM
)
3699 smema
= force_reg (Pmode
, smema
);
3701 /* Generate all the tmp registers we need. */
3702 for (i
= 0; i
< words
; ++i
)
3704 data_regs
[i
] = out_regs
[i
];
3705 ext_tmps
[i
] = gen_reg_rtx (DImode
);
3707 data_regs
[words
] = gen_reg_rtx (DImode
);
3710 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
3712 /* Load up all of the source data. */
3713 for (i
= 0; i
< words
; ++i
)
3715 tmp
= change_address (smem
, DImode
,
3716 gen_rtx_AND (DImode
,
3717 plus_constant (smema
, 8*i
),
3719 set_mem_alias_set (tmp
, 0);
3720 emit_move_insn (data_regs
[i
], tmp
);
3723 tmp
= change_address (smem
, DImode
,
3724 gen_rtx_AND (DImode
,
3725 plus_constant (smema
, 8*words
- 1),
3727 set_mem_alias_set (tmp
, 0);
3728 emit_move_insn (data_regs
[words
], tmp
);
3730 /* Extract the half-word fragments. Unfortunately DEC decided to make
3731 extxh with offset zero a noop instead of zeroing the register, so
3732 we must take care of that edge condition ourselves with cmov. */
3734 sreg
= copy_addr_to_reg (smema
);
3735 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
3737 if (WORDS_BIG_ENDIAN
)
3738 emit_move_insn (sreg
, plus_constant (sreg
, 7));
3739 for (i
= 0; i
< words
; ++i
)
3741 if (WORDS_BIG_ENDIAN
)
3743 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
3744 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
3748 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
3749 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
3751 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
3752 gen_rtx_IF_THEN_ELSE (DImode
,
3753 gen_rtx_EQ (DImode
, areg
,
3755 const0_rtx
, ext_tmps
[i
])));
3758 /* Merge the half-words into whole words. */
3759 for (i
= 0; i
< words
; ++i
)
3761 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
3762 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
3766 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
3767 may be NULL to store zeros. */
3770 alpha_expand_unaligned_store_words (rtx
*data_regs
, rtx dmem
,
3771 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
3773 rtx
const im8
= GEN_INT (-8);
3774 rtx
const i64
= GEN_INT (64);
3775 rtx ins_tmps
[MAX_MOVE_WORDS
];
3776 rtx st_tmp_1
, st_tmp_2
, dreg
;
3777 rtx st_addr_1
, st_addr_2
, dmema
;
3780 dmema
= XEXP (dmem
, 0);
3781 if (GET_CODE (dmema
) == LO_SUM
)
3782 dmema
= force_reg (Pmode
, dmema
);
3784 /* Generate all the tmp registers we need. */
3785 if (data_regs
!= NULL
)
3786 for (i
= 0; i
< words
; ++i
)
3787 ins_tmps
[i
] = gen_reg_rtx(DImode
);
3788 st_tmp_1
= gen_reg_rtx(DImode
);
3789 st_tmp_2
= gen_reg_rtx(DImode
);
3792 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
3794 st_addr_2
= change_address (dmem
, DImode
,
3795 gen_rtx_AND (DImode
,
3796 plus_constant (dmema
, words
*8 - 1),
3798 set_mem_alias_set (st_addr_2
, 0);
3800 st_addr_1
= change_address (dmem
, DImode
,
3801 gen_rtx_AND (DImode
, dmema
, im8
));
3802 set_mem_alias_set (st_addr_1
, 0);
3804 /* Load up the destination end bits. */
3805 emit_move_insn (st_tmp_2
, st_addr_2
);
3806 emit_move_insn (st_tmp_1
, st_addr_1
);
3808 /* Shift the input data into place. */
3809 dreg
= copy_addr_to_reg (dmema
);
3810 if (WORDS_BIG_ENDIAN
)
3811 emit_move_insn (dreg
, plus_constant (dreg
, 7));
3812 if (data_regs
!= NULL
)
3814 for (i
= words
-1; i
>= 0; --i
)
3816 if (WORDS_BIG_ENDIAN
)
3818 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
3819 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
3823 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
3824 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
3827 for (i
= words
-1; i
> 0; --i
)
3829 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
3830 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
3835 /* Split and merge the ends with the destination data. */
3836 if (WORDS_BIG_ENDIAN
)
3838 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, constm1_rtx
, dreg
));
3839 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
3843 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
3844 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, constm1_rtx
, dreg
));
3847 if (data_regs
!= NULL
)
3849 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
3850 st_tmp_2
, 1, OPTAB_WIDEN
);
3851 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
3852 st_tmp_1
, 1, OPTAB_WIDEN
);
3856 if (WORDS_BIG_ENDIAN
)
3857 emit_move_insn (st_addr_1
, st_tmp_1
);
3859 emit_move_insn (st_addr_2
, st_tmp_2
);
3860 for (i
= words
-1; i
> 0; --i
)
3862 rtx tmp
= change_address (dmem
, DImode
,
3863 gen_rtx_AND (DImode
,
3864 plus_constant(dmema
,
3865 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
3867 set_mem_alias_set (tmp
, 0);
3868 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
3870 if (WORDS_BIG_ENDIAN
)
3871 emit_move_insn (st_addr_2
, st_tmp_2
);
3873 emit_move_insn (st_addr_1
, st_tmp_1
);
3877 /* Expand string/block move operations.
3879 operands[0] is the pointer to the destination.
3880 operands[1] is the pointer to the source.
3881 operands[2] is the number of bytes to move.
3882 operands[3] is the alignment. */
3885 alpha_expand_block_move (rtx operands
[])
3887 rtx bytes_rtx
= operands
[2];
3888 rtx align_rtx
= operands
[3];
3889 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
3890 HOST_WIDE_INT bytes
= orig_bytes
;
3891 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
3892 HOST_WIDE_INT dst_align
= src_align
;
3893 rtx orig_src
= operands
[1];
3894 rtx orig_dst
= operands
[0];
3895 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
3897 unsigned int i
, words
, ofs
, nregs
= 0;
3899 if (orig_bytes
<= 0)
3901 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
3904 /* Look for additional alignment information from recorded register info. */
3906 tmp
= XEXP (orig_src
, 0);
3907 if (GET_CODE (tmp
) == REG
)
3908 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
3909 else if (GET_CODE (tmp
) == PLUS
3910 && GET_CODE (XEXP (tmp
, 0)) == REG
3911 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
3913 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
3914 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
3918 if (a
>= 64 && c
% 8 == 0)
3920 else if (a
>= 32 && c
% 4 == 0)
3922 else if (a
>= 16 && c
% 2 == 0)
3927 tmp
= XEXP (orig_dst
, 0);
3928 if (GET_CODE (tmp
) == REG
)
3929 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
3930 else if (GET_CODE (tmp
) == PLUS
3931 && GET_CODE (XEXP (tmp
, 0)) == REG
3932 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
3934 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
3935 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
3939 if (a
>= 64 && c
% 8 == 0)
3941 else if (a
>= 32 && c
% 4 == 0)
3943 else if (a
>= 16 && c
% 2 == 0)
3949 if (src_align
>= 64 && bytes
>= 8)
3953 for (i
= 0; i
< words
; ++i
)
3954 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
3956 for (i
= 0; i
< words
; ++i
)
3957 emit_move_insn (data_regs
[nregs
+ i
],
3958 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
3965 if (src_align
>= 32 && bytes
>= 4)
3969 for (i
= 0; i
< words
; ++i
)
3970 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
3972 for (i
= 0; i
< words
; ++i
)
3973 emit_move_insn (data_regs
[nregs
+ i
],
3974 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
3985 for (i
= 0; i
< words
+1; ++i
)
3986 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
3988 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
3996 if (! TARGET_BWX
&& bytes
>= 4)
3998 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
3999 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
4006 if (src_align
>= 16)
4009 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4010 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
4013 } while (bytes
>= 2);
4015 else if (! TARGET_BWX
)
4017 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4018 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
4026 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
4027 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
4032 if (nregs
> ARRAY_SIZE (data_regs
))
4035 /* Now save it back out again. */
4039 /* Write out the data in whatever chunks reading the source allowed. */
4040 if (dst_align
>= 64)
4042 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4044 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
4051 if (dst_align
>= 32)
4053 /* If the source has remaining DImode regs, write them out in
4055 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4057 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
4058 NULL_RTX
, 1, OPTAB_WIDEN
);
4060 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4061 gen_lowpart (SImode
, data_regs
[i
]));
4062 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
4063 gen_lowpart (SImode
, tmp
));
4068 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4070 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4077 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4079 /* Write out a remaining block of words using unaligned methods. */
4081 for (words
= 1; i
+ words
< nregs
; words
++)
4082 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
4086 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
4088 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
4095 /* Due to the above, this won't be aligned. */
4096 /* ??? If we have more than one of these, consider constructing full
4097 words in registers and using alpha_expand_unaligned_store_words. */
4098 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4100 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
4105 if (dst_align
>= 16)
4106 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4108 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
4113 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4115 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
4120 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == QImode
)
4122 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
4134 alpha_expand_block_clear (rtx operands
[])
4136 rtx bytes_rtx
= operands
[1];
4137 rtx align_rtx
= operands
[2];
4138 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4139 HOST_WIDE_INT bytes
= orig_bytes
;
4140 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4141 HOST_WIDE_INT alignofs
= 0;
4142 rtx orig_dst
= operands
[0];
4144 int i
, words
, ofs
= 0;
4146 if (orig_bytes
<= 0)
4148 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4151 /* Look for stricter alignment. */
4152 tmp
= XEXP (orig_dst
, 0);
4153 if (GET_CODE (tmp
) == REG
)
4154 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4155 else if (GET_CODE (tmp
) == PLUS
4156 && GET_CODE (XEXP (tmp
, 0)) == REG
4157 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4159 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4160 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4165 align
= a
, alignofs
= 8 - c
% 8;
4167 align
= a
, alignofs
= 4 - c
% 4;
4169 align
= a
, alignofs
= 2 - c
% 2;
4173 /* Handle an unaligned prefix first. */
4177 #if HOST_BITS_PER_WIDE_INT >= 64
4178 /* Given that alignofs is bounded by align, the only time BWX could
4179 generate three stores is for a 7 byte fill. Prefer two individual
4180 stores over a load/mask/store sequence. */
4181 if ((!TARGET_BWX
|| alignofs
== 7)
4183 && !(alignofs
== 4 && bytes
>= 4))
4185 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
4186 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
4190 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
4191 set_mem_alias_set (mem
, 0);
4193 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
4194 if (bytes
< alignofs
)
4196 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
4207 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
4208 NULL_RTX
, 1, OPTAB_WIDEN
);
4210 emit_move_insn (mem
, tmp
);
4214 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
4216 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4221 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
4223 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
4228 if (alignofs
== 4 && bytes
>= 4)
4230 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4236 /* If we've not used the extra lead alignment information by now,
4237 we won't be able to. Downgrade align to match what's left over. */
4240 alignofs
= alignofs
& -alignofs
;
4241 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
4245 /* Handle a block of contiguous long-words. */
4247 if (align
>= 64 && bytes
>= 8)
4251 for (i
= 0; i
< words
; ++i
)
4252 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
4259 /* If the block is large and appropriately aligned, emit a single
4260 store followed by a sequence of stq_u insns. */
4262 if (align
>= 32 && bytes
> 16)
4266 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4270 orig_dsta
= XEXP (orig_dst
, 0);
4271 if (GET_CODE (orig_dsta
) == LO_SUM
)
4272 orig_dsta
= force_reg (Pmode
, orig_dsta
);
4275 for (i
= 0; i
< words
; ++i
)
4278 = change_address (orig_dst
, DImode
,
4279 gen_rtx_AND (DImode
,
4280 plus_constant (orig_dsta
, ofs
+ i
*8),
4282 set_mem_alias_set (mem
, 0);
4283 emit_move_insn (mem
, const0_rtx
);
4286 /* Depending on the alignment, the first stq_u may have overlapped
4287 with the initial stl, which means that the last stq_u didn't
4288 write as much as it would appear. Leave those questionable bytes
4290 bytes
-= words
* 8 - 4;
4291 ofs
+= words
* 8 - 4;
4294 /* Handle a smaller block of aligned words. */
4296 if ((align
>= 64 && bytes
== 4)
4297 || (align
== 32 && bytes
>= 4))
4301 for (i
= 0; i
< words
; ++i
)
4302 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
4309 /* An unaligned block uses stq_u stores for as many as possible. */
4315 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
4321 /* Next clean up any trailing pieces. */
4323 #if HOST_BITS_PER_WIDE_INT >= 64
4324 /* Count the number of bits in BYTES for which aligned stores could
4327 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
4331 /* If we have appropriate alignment (and it wouldn't take too many
4332 instructions otherwise), mask out the bytes we need. */
4333 if (TARGET_BWX
? words
> 2 : bytes
> 0)
4340 mem
= adjust_address (orig_dst
, DImode
, ofs
);
4341 set_mem_alias_set (mem
, 0);
4343 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4345 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
4346 NULL_RTX
, 1, OPTAB_WIDEN
);
4348 emit_move_insn (mem
, tmp
);
4351 else if (align
>= 32 && bytes
< 4)
4356 mem
= adjust_address (orig_dst
, SImode
, ofs
);
4357 set_mem_alias_set (mem
, 0);
4359 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4361 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
4362 NULL_RTX
, 1, OPTAB_WIDEN
);
4364 emit_move_insn (mem
, tmp
);
4370 if (!TARGET_BWX
&& bytes
>= 4)
4372 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
4382 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
4386 } while (bytes
>= 2);
4388 else if (! TARGET_BWX
)
4390 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
4398 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4406 /* Returns a mask so that zap(x, value) == x & mask. */
4409 alpha_expand_zap_mask (HOST_WIDE_INT value
)
4414 if (HOST_BITS_PER_WIDE_INT
>= 64)
4416 HOST_WIDE_INT mask
= 0;
4418 for (i
= 7; i
>= 0; --i
)
4421 if (!((value
>> i
) & 1))
4425 result
= gen_int_mode (mask
, DImode
);
4427 else if (HOST_BITS_PER_WIDE_INT
== 32)
4429 HOST_WIDE_INT mask_lo
= 0, mask_hi
= 0;
4431 for (i
= 7; i
>= 4; --i
)
4434 if (!((value
>> i
) & 1))
4438 for (i
= 3; i
>= 0; --i
)
4441 if (!((value
>> i
) & 1))
4445 result
= immed_double_const (mask_lo
, mask_hi
, DImode
);
4454 alpha_expand_builtin_vector_binop (rtx (*gen
) (rtx
, rtx
, rtx
),
4455 enum machine_mode mode
,
4456 rtx op0
, rtx op1
, rtx op2
)
4458 op0
= gen_lowpart (mode
, op0
);
4460 if (op1
== const0_rtx
)
4461 op1
= CONST0_RTX (mode
);
4463 op1
= gen_lowpart (mode
, op1
);
4465 if (op2
== const0_rtx
)
4466 op2
= CONST0_RTX (mode
);
4468 op2
= gen_lowpart (mode
, op2
);
4470 emit_insn ((*gen
) (op0
, op1
, op2
));
4473 /* Adjust the cost of a scheduling dependency. Return the new cost of
4474 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4477 alpha_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
4479 enum attr_type insn_type
, dep_insn_type
;
4481 /* If the dependence is an anti-dependence, there is no cost. For an
4482 output dependence, there is sometimes a cost, but it doesn't seem
4483 worth handling those few cases. */
4484 if (REG_NOTE_KIND (link
) != 0)
4487 /* If we can't recognize the insns, we can't really do anything. */
4488 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
4491 insn_type
= get_attr_type (insn
);
4492 dep_insn_type
= get_attr_type (dep_insn
);
4494 /* Bring in the user-defined memory latency. */
4495 if (dep_insn_type
== TYPE_ILD
4496 || dep_insn_type
== TYPE_FLD
4497 || dep_insn_type
== TYPE_LDSYM
)
4498 cost
+= alpha_memory_latency
-1;
4500 /* Everything else handled in DFA bypasses now. */
4505 /* The number of instructions that can be issued per cycle. */
4508 alpha_issue_rate (void)
4510 return (alpha_tune
== PROCESSOR_EV4
? 2 : 4);
4513 /* How many alternative schedules to try. This should be as wide as the
4514 scheduling freedom in the DFA, but no wider. Making this value too
4515 large results extra work for the scheduler.
4517 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
4518 alternative schedules. For EV5, we can choose between E0/E1 and
4519 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
4522 alpha_multipass_dfa_lookahead (void)
4524 return (alpha_tune
== PROCESSOR_EV6
? 4 : 2);
4527 /* Machine-specific function data. */
4529 struct machine_function
GTY(())
4532 /* List of call information words for calls from this function. */
4533 struct rtx_def
*first_ciw
;
4534 struct rtx_def
*last_ciw
;
4537 /* List of deferred case vectors. */
4538 struct rtx_def
*addr_list
;
4541 const char *some_ld_name
;
4543 /* For TARGET_LD_BUGGY_LDGP. */
4544 struct rtx_def
*gp_save_rtx
;
4547 /* How to allocate a 'struct machine_function'. */
4549 static struct machine_function
*
4550 alpha_init_machine_status (void)
4552 return ((struct machine_function
*)
4553 ggc_alloc_cleared (sizeof (struct machine_function
)));
4556 /* Functions to save and restore alpha_return_addr_rtx. */
4558 /* Start the ball rolling with RETURN_ADDR_RTX. */
4561 alpha_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
4566 return get_hard_reg_initial_val (Pmode
, REG_RA
);
4569 /* Return or create a memory slot containing the gp value for the current
4570 function. Needed only if TARGET_LD_BUGGY_LDGP. */
4573 alpha_gp_save_rtx (void)
4575 rtx seq
, m
= cfun
->machine
->gp_save_rtx
;
4581 m
= assign_stack_local (DImode
, UNITS_PER_WORD
, BITS_PER_WORD
);
4582 m
= validize_mem (m
);
4583 emit_move_insn (m
, pic_offset_table_rtx
);
4587 emit_insn_after (seq
, entry_of_function ());
4589 cfun
->machine
->gp_save_rtx
= m
;
4596 alpha_ra_ever_killed (void)
4600 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
4601 return regs_ever_live
[REG_RA
];
4603 push_topmost_sequence ();
4605 pop_topmost_sequence ();
4607 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
4611 /* Return the trap mode suffix applicable to the current
4612 instruction, or NULL. */
4615 get_trap_mode_suffix (void)
4617 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
4621 case TRAP_SUFFIX_NONE
:
4624 case TRAP_SUFFIX_SU
:
4625 if (alpha_fptm
>= ALPHA_FPTM_SU
)
4629 case TRAP_SUFFIX_SUI
:
4630 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
4634 case TRAP_SUFFIX_V_SV
:
4642 case ALPHA_FPTM_SUI
:
4647 case TRAP_SUFFIX_V_SV_SVI
:
4656 case ALPHA_FPTM_SUI
:
4661 case TRAP_SUFFIX_U_SU_SUI
:
4670 case ALPHA_FPTM_SUI
:
4678 /* Return the rounding mode suffix applicable to the current
4679 instruction, or NULL. */
4682 get_round_mode_suffix (void)
4684 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
4688 case ROUND_SUFFIX_NONE
:
4690 case ROUND_SUFFIX_NORMAL
:
4693 case ALPHA_FPRM_NORM
:
4695 case ALPHA_FPRM_MINF
:
4697 case ALPHA_FPRM_CHOP
:
4699 case ALPHA_FPRM_DYN
:
4704 case ROUND_SUFFIX_C
:
4710 /* Locate some local-dynamic symbol still in use by this function
4711 so that we can print its name in some movdi_er_tlsldm pattern. */
4714 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
4718 if (GET_CODE (x
) == SYMBOL_REF
4719 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
4721 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
4729 get_some_local_dynamic_name (void)
4733 if (cfun
->machine
->some_ld_name
)
4734 return cfun
->machine
->some_ld_name
;
4736 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
4738 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
4739 return cfun
->machine
->some_ld_name
;
4744 /* Print an operand. Recognize special options, documented below. */
4747 print_operand (FILE *file
, rtx x
, int code
)
4754 /* Print the assembler name of the current function. */
4755 assemble_name (file
, alpha_fnname
);
4759 assemble_name (file
, get_some_local_dynamic_name ());
4764 const char *trap
= get_trap_mode_suffix ();
4765 const char *round
= get_round_mode_suffix ();
4768 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
4769 (trap
? trap
: ""), (round
? round
: ""));
4774 /* Generates single precision instruction suffix. */
4775 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
4779 /* Generates double precision instruction suffix. */
4780 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
4784 /* Generates a nop after a noreturn call at the very end of the
4786 if (next_real_insn (current_output_insn
) == 0)
4787 fprintf (file
, "\n\tnop");
4791 if (alpha_this_literal_sequence_number
== 0)
4792 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
4793 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
4797 if (alpha_this_gpdisp_sequence_number
== 0)
4798 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
4799 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
4803 if (GET_CODE (x
) == HIGH
)
4804 output_addr_const (file
, XEXP (x
, 0));
4806 output_operand_lossage ("invalid %%H value");
4813 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD_CALL
)
4815 x
= XVECEXP (x
, 0, 0);
4816 lituse
= "lituse_tlsgd";
4818 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM_CALL
)
4820 x
= XVECEXP (x
, 0, 0);
4821 lituse
= "lituse_tlsldm";
4823 else if (GET_CODE (x
) == CONST_INT
)
4824 lituse
= "lituse_jsr";
4827 output_operand_lossage ("invalid %%J value");
4831 if (x
!= const0_rtx
)
4832 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
4837 /* If this operand is the constant zero, write it as "$31". */
4838 if (GET_CODE (x
) == REG
)
4839 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
4840 else if (x
== CONST0_RTX (GET_MODE (x
)))
4841 fprintf (file
, "$31");
4843 output_operand_lossage ("invalid %%r value");
4847 /* Similar, but for floating-point. */
4848 if (GET_CODE (x
) == REG
)
4849 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
4850 else if (x
== CONST0_RTX (GET_MODE (x
)))
4851 fprintf (file
, "$f31");
4853 output_operand_lossage ("invalid %%R value");
4857 /* Write the 1's complement of a constant. */
4858 if (GET_CODE (x
) != CONST_INT
)
4859 output_operand_lossage ("invalid %%N value");
4861 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
4865 /* Write 1 << C, for a constant C. */
4866 if (GET_CODE (x
) != CONST_INT
)
4867 output_operand_lossage ("invalid %%P value");
4869 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
4873 /* Write the high-order 16 bits of a constant, sign-extended. */
4874 if (GET_CODE (x
) != CONST_INT
)
4875 output_operand_lossage ("invalid %%h value");
4877 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
4881 /* Write the low-order 16 bits of a constant, sign-extended. */
4882 if (GET_CODE (x
) != CONST_INT
)
4883 output_operand_lossage ("invalid %%L value");
4885 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
4886 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
4890 /* Write mask for ZAP insn. */
4891 if (GET_CODE (x
) == CONST_DOUBLE
)
4893 HOST_WIDE_INT mask
= 0;
4894 HOST_WIDE_INT value
;
4896 value
= CONST_DOUBLE_LOW (x
);
4897 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
4902 value
= CONST_DOUBLE_HIGH (x
);
4903 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
4906 mask
|= (1 << (i
+ sizeof (int)));
4908 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
4911 else if (GET_CODE (x
) == CONST_INT
)
4913 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
4915 for (i
= 0; i
< 8; i
++, value
>>= 8)
4919 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
4922 output_operand_lossage ("invalid %%m value");
4926 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
4927 if (GET_CODE (x
) != CONST_INT
4928 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
4929 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
4930 output_operand_lossage ("invalid %%M value");
4932 fprintf (file
, "%s",
4933 (INTVAL (x
) == 8 ? "b"
4934 : INTVAL (x
) == 16 ? "w"
4935 : INTVAL (x
) == 32 ? "l"
4940 /* Similar, except do it from the mask. */
4941 if (GET_CODE (x
) == CONST_INT
)
4943 HOST_WIDE_INT value
= INTVAL (x
);
4950 if (value
== 0xffff)
4955 if (value
== 0xffffffff)
4966 else if (HOST_BITS_PER_WIDE_INT
== 32
4967 && GET_CODE (x
) == CONST_DOUBLE
4968 && CONST_DOUBLE_LOW (x
) == 0xffffffff
4969 && CONST_DOUBLE_HIGH (x
) == 0)
4974 output_operand_lossage ("invalid %%U value");
4978 /* Write the constant value divided by 8 for little-endian mode or
4979 (56 - value) / 8 for big-endian mode. */
4981 if (GET_CODE (x
) != CONST_INT
4982 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
4985 || (INTVAL (x
) & 7) != 0)
4986 output_operand_lossage ("invalid %%s value");
4988 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
4990 ? (56 - INTVAL (x
)) / 8
4995 /* Same, except compute (64 - c) / 8 */
4997 if (GET_CODE (x
) != CONST_INT
4998 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
4999 && (INTVAL (x
) & 7) != 8)
5000 output_operand_lossage ("invalid %%s value");
5002 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
5007 /* On Unicos/Mk systems: use a DEX expression if the symbol
5008 clashes with a register name. */
5009 int dex
= unicosmk_need_dex (x
);
5011 fprintf (file
, "DEX(%d)", dex
);
5013 output_addr_const (file
, x
);
5017 case 'C': case 'D': case 'c': case 'd':
5018 /* Write out comparison name. */
5020 enum rtx_code c
= GET_CODE (x
);
5022 if (!COMPARISON_P (x
))
5023 output_operand_lossage ("invalid %%C value");
5025 else if (code
== 'D')
5026 c
= reverse_condition (c
);
5027 else if (code
== 'c')
5028 c
= swap_condition (c
);
5029 else if (code
== 'd')
5030 c
= swap_condition (reverse_condition (c
));
5033 fprintf (file
, "ule");
5035 fprintf (file
, "ult");
5036 else if (c
== UNORDERED
)
5037 fprintf (file
, "un");
5039 fprintf (file
, "%s", GET_RTX_NAME (c
));
5044 /* Write the divide or modulus operator. */
5045 switch (GET_CODE (x
))
5048 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
5051 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
5054 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
5057 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
5060 output_operand_lossage ("invalid %%E value");
5066 /* Write "_u" for unaligned access. */
5067 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
5068 fprintf (file
, "_u");
5072 if (GET_CODE (x
) == REG
)
5073 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5074 else if (GET_CODE (x
) == MEM
)
5075 output_address (XEXP (x
, 0));
5076 else if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == UNSPEC
)
5078 switch (XINT (XEXP (x
, 0), 1))
5082 output_addr_const (file
, XVECEXP (XEXP (x
, 0), 0, 0));
5085 output_operand_lossage ("unknown relocation unspec");
5090 output_addr_const (file
, x
);
5094 output_operand_lossage ("invalid %%xn code");
5099 print_operand_address (FILE *file
, rtx addr
)
5102 HOST_WIDE_INT offset
= 0;
5104 if (GET_CODE (addr
) == AND
)
5105 addr
= XEXP (addr
, 0);
5107 if (GET_CODE (addr
) == PLUS
5108 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
5110 offset
= INTVAL (XEXP (addr
, 1));
5111 addr
= XEXP (addr
, 0);
5114 if (GET_CODE (addr
) == LO_SUM
)
5116 const char *reloc16
, *reloclo
;
5117 rtx op1
= XEXP (addr
, 1);
5119 if (GET_CODE (op1
) == CONST
&& GET_CODE (XEXP (op1
, 0)) == UNSPEC
)
5121 op1
= XEXP (op1
, 0);
5122 switch (XINT (op1
, 1))
5126 reloclo
= (alpha_tls_size
== 16 ? "dtprel" : "dtprello");
5130 reloclo
= (alpha_tls_size
== 16 ? "tprel" : "tprello");
5133 output_operand_lossage ("unknown relocation unspec");
5137 output_addr_const (file
, XVECEXP (op1
, 0, 0));
5142 reloclo
= "gprellow";
5143 output_addr_const (file
, op1
);
5147 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
5149 addr
= XEXP (addr
, 0);
5150 if (GET_CODE (addr
) == REG
)
5151 basereg
= REGNO (addr
);
5152 else if (GET_CODE (addr
) == SUBREG
5153 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5154 basereg
= subreg_regno (addr
);
5158 fprintf (file
, "($%d)\t\t!%s", basereg
,
5159 (basereg
== 29 ? reloc16
: reloclo
));
5163 if (GET_CODE (addr
) == REG
)
5164 basereg
= REGNO (addr
);
5165 else if (GET_CODE (addr
) == SUBREG
5166 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5167 basereg
= subreg_regno (addr
);
5168 else if (GET_CODE (addr
) == CONST_INT
)
5169 offset
= INTVAL (addr
);
5171 #if TARGET_ABI_OPEN_VMS
5172 else if (GET_CODE (addr
) == SYMBOL_REF
)
5174 fprintf (file
, "%s", XSTR (addr
, 0));
5177 else if (GET_CODE (addr
) == CONST
5178 && GET_CODE (XEXP (addr
, 0)) == PLUS
5179 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
)
5181 fprintf (file
, "%s+" HOST_WIDE_INT_PRINT_DEC
,
5182 XSTR (XEXP (XEXP (addr
, 0), 0), 0),
5183 INTVAL (XEXP (XEXP (addr
, 0), 1)));
5191 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"($%d)", offset
, basereg
);
5194 /* Emit RTL insns to initialize the variable parts of a trampoline at
5195 TRAMP. FNADDR is an RTX for the address of the function's pure
5196 code. CXT is an RTX for the static chain value for the function.
5198 The three offset parameters are for the individual template's
5199 layout. A JMPOFS < 0 indicates that the trampoline does not
5200 contain instructions at all.
5202 We assume here that a function will be called many more times than
5203 its address is taken (e.g., it might be passed to qsort), so we
5204 take the trouble to initialize the "hint" field in the JMP insn.
5205 Note that the hint field is PC (new) + 4 * bits 13:0. */
5208 alpha_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
,
5209 int fnofs
, int cxtofs
, int jmpofs
)
5211 rtx temp
, temp1
, addr
;
5212 /* VMS really uses DImode pointers in memory at this point. */
5213 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
5215 #ifdef POINTERS_EXTEND_UNSIGNED
5216 fnaddr
= convert_memory_address (mode
, fnaddr
);
5217 cxt
= convert_memory_address (mode
, cxt
);
5220 /* Store function address and CXT. */
5221 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
5222 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
5223 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
5224 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
5226 /* This has been disabled since the hint only has a 32k range, and in
5227 no existing OS is the stack within 32k of the text segment. */
5228 if (0 && jmpofs
>= 0)
5230 /* Compute hint value. */
5231 temp
= force_operand (plus_constant (tramp
, jmpofs
+4), NULL_RTX
);
5232 temp
= expand_binop (DImode
, sub_optab
, fnaddr
, temp
, temp
, 1,
5234 temp
= expand_shift (RSHIFT_EXPR
, Pmode
, temp
,
5235 build_int_cst (NULL_TREE
, 2), NULL_RTX
, 1);
5236 temp
= expand_and (SImode
, gen_lowpart (SImode
, temp
),
5237 GEN_INT (0x3fff), 0);
5239 /* Merge in the hint. */
5240 addr
= memory_address (SImode
, plus_constant (tramp
, jmpofs
));
5241 temp1
= force_reg (SImode
, gen_rtx_MEM (SImode
, addr
));
5242 temp1
= expand_and (SImode
, temp1
, GEN_INT (0xffffc000), NULL_RTX
);
5243 temp1
= expand_binop (SImode
, ior_optab
, temp1
, temp
, temp1
, 1,
5245 emit_move_insn (gen_rtx_MEM (SImode
, addr
), temp1
);
5248 #ifdef ENABLE_EXECUTE_STACK
5249 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
5250 0, VOIDmode
, 1, tramp
, Pmode
);
5254 emit_insn (gen_imb ());
5257 /* Determine where to put an argument to a function.
5258 Value is zero to push the argument on the stack,
5259 or a hard register in which to store the argument.
5261 MODE is the argument's machine mode.
5262 TYPE is the data type of the argument (as a tree).
5263 This is null for libcalls where that information may
5265 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5266 the preceding args and about the function being called.
5267 NAMED is nonzero if this argument is a named parameter
5268 (otherwise it is an extra parameter matching an ellipsis).
5270 On Alpha the first 6 words of args are normally in registers
5271 and the rest are pushed. */
5274 function_arg (CUMULATIVE_ARGS cum
, enum machine_mode mode
, tree type
,
5275 int named ATTRIBUTE_UNUSED
)
5280 /* Don't get confused and pass small structures in FP registers. */
5281 if (type
&& AGGREGATE_TYPE_P (type
))
5285 #ifdef ENABLE_CHECKING
5286 /* With alpha_split_complex_arg, we shouldn't see any raw complex
5288 if (COMPLEX_MODE_P (mode
))
5292 /* Set up defaults for FP operands passed in FP registers, and
5293 integral operands passed in integer registers. */
5294 if (TARGET_FPREGS
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5300 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5301 the three platforms, so we can't avoid conditional compilation. */
5302 #if TARGET_ABI_OPEN_VMS
5304 if (mode
== VOIDmode
)
5305 return alpha_arg_info_reg_val (cum
);
5307 num_args
= cum
.num_args
;
5309 || targetm
.calls
.must_pass_in_stack (mode
, type
))
5312 #elif TARGET_ABI_UNICOSMK
5316 /* If this is the last argument, generate the call info word (CIW). */
5317 /* ??? We don't include the caller's line number in the CIW because
5318 I don't know how to determine it if debug infos are turned off. */
5319 if (mode
== VOIDmode
)
5328 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
5329 if (cum
.reg_args_type
[i
])
5330 lo
|= (1 << (7 - i
));
5332 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
5335 lo
|= cum
.num_reg_words
;
5337 #if HOST_BITS_PER_WIDE_INT == 32
5338 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
5340 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
5341 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
5344 ciw
= immed_double_const (lo
, hi
, DImode
);
5346 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
5347 UNSPEC_UMK_LOAD_CIW
);
5350 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
5351 num_args
= cum
.num_reg_words
;
5353 || cum
.num_reg_words
+ size
> 6
5354 || targetm
.calls
.must_pass_in_stack (mode
, type
))
5356 else if (type
&& TYPE_MODE (type
) == BLKmode
)
5360 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
5361 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
5363 /* The argument fits in two registers. Note that we still need to
5364 reserve a register for empty structures. */
5368 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
5371 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
5372 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
5373 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
5377 #elif TARGET_ABI_OSF
5383 /* VOID is passed as a special flag for "last argument". */
5384 if (type
== void_type_node
)
5386 else if (targetm
.calls
.must_pass_in_stack (mode
, type
))
5390 #error Unhandled ABI
5393 return gen_rtx_REG (mode
, num_args
+ basereg
);
5397 alpha_arg_partial_bytes (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
5398 enum machine_mode mode ATTRIBUTE_UNUSED
,
5399 tree type ATTRIBUTE_UNUSED
,
5400 bool named ATTRIBUTE_UNUSED
)
5404 #if TARGET_ABI_OPEN_VMS
5405 if (cum
->num_args
< 6
5406 && 6 < cum
->num_args
+ ALPHA_ARG_SIZE (mode
, type
, named
))
5407 words
= 6 - (CUM
).num_args
;
5408 #elif TARGET_ABI_UNICOSMK
5409 /* Never any split arguments. */
5410 #elif TARGET_ABI_OSF
5411 if (*cum
< 6 && 6 < *cum
+ ALPHA_ARG_SIZE (mode
, type
, named
))
5414 #error Unhandled ABI
5417 return words
* UNITS_PER_WORD
;
5421 /* Return true if TYPE must be returned in memory, instead of in registers. */
5424 alpha_return_in_memory (tree type
, tree fndecl ATTRIBUTE_UNUSED
)
5426 enum machine_mode mode
= VOIDmode
;
5431 mode
= TYPE_MODE (type
);
5433 /* All aggregates are returned in memory. */
5434 if (AGGREGATE_TYPE_P (type
))
5438 size
= GET_MODE_SIZE (mode
);
5439 switch (GET_MODE_CLASS (mode
))
5441 case MODE_VECTOR_FLOAT
:
5442 /* Pass all float vectors in memory, like an aggregate. */
5445 case MODE_COMPLEX_FLOAT
:
5446 /* We judge complex floats on the size of their element,
5447 not the size of the whole type. */
5448 size
= GET_MODE_UNIT_SIZE (mode
);
5453 case MODE_COMPLEX_INT
:
5454 case MODE_VECTOR_INT
:
5458 /* ??? We get called on all sorts of random stuff from
5459 aggregate_value_p. We can't abort, but it's not clear
5460 what's safe to return. Pretend it's a struct I guess. */
5464 /* Otherwise types must fit in one register. */
5465 return size
> UNITS_PER_WORD
;
5468 /* Return true if TYPE should be passed by invisible reference. */
5471 alpha_pass_by_reference (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
,
5472 enum machine_mode mode
,
5473 tree type ATTRIBUTE_UNUSED
,
5474 bool named ATTRIBUTE_UNUSED
)
5476 return mode
== TFmode
|| mode
== TCmode
;
5479 /* Define how to find the value returned by a function. VALTYPE is the
5480 data type of the value (as a tree). If the precise function being
5481 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
5482 MODE is set instead of VALTYPE for libcalls.
5484 On Alpha the value is found in $0 for integer functions and
5485 $f0 for floating-point functions. */
5488 function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
,
5489 enum machine_mode mode
)
5491 unsigned int regnum
, dummy
;
5492 enum mode_class
class;
5494 #ifdef ENABLE_CHECKING
5495 if (valtype
&& alpha_return_in_memory (valtype
, func
))
5500 mode
= TYPE_MODE (valtype
);
5502 class = GET_MODE_CLASS (mode
);
5506 PROMOTE_MODE (mode
, dummy
, valtype
);
5509 case MODE_COMPLEX_INT
:
5510 case MODE_VECTOR_INT
:
5518 case MODE_COMPLEX_FLOAT
:
5520 enum machine_mode cmode
= GET_MODE_INNER (mode
);
5522 return gen_rtx_PARALLEL
5525 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 32),
5527 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 33),
5528 GEN_INT (GET_MODE_SIZE (cmode
)))));
5535 return gen_rtx_REG (mode
, regnum
);
5538 /* TCmode complex values are passed by invisible reference. We
5539 should not split these values. */
5542 alpha_split_complex_arg (tree type
)
5544 return TYPE_MODE (type
) != TCmode
;
5548 alpha_build_builtin_va_list (void)
5550 tree base
, ofs
, space
, record
, type_decl
;
5552 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
5553 return ptr_type_node
;
5555 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
5556 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
5557 TREE_CHAIN (record
) = type_decl
;
5558 TYPE_NAME (record
) = type_decl
;
5560 /* C++? SET_IS_AGGR_TYPE (record, 1); */
5562 /* Dummy field to prevent alignment warnings. */
5563 space
= build_decl (FIELD_DECL
, NULL_TREE
, integer_type_node
);
5564 DECL_FIELD_CONTEXT (space
) = record
;
5565 DECL_ARTIFICIAL (space
) = 1;
5566 DECL_IGNORED_P (space
) = 1;
5568 ofs
= build_decl (FIELD_DECL
, get_identifier ("__offset"),
5570 DECL_FIELD_CONTEXT (ofs
) = record
;
5571 TREE_CHAIN (ofs
) = space
;
5573 base
= build_decl (FIELD_DECL
, get_identifier ("__base"),
5575 DECL_FIELD_CONTEXT (base
) = record
;
5576 TREE_CHAIN (base
) = ofs
;
5578 TYPE_FIELDS (record
) = base
;
5579 layout_type (record
);
5581 va_list_gpr_counter_field
= ofs
;
5586 /* Helper function for alpha_stdarg_optimize_hook. Skip over casts
5587 and constant additions. */
5590 va_list_skip_additions (tree lhs
)
5594 if (TREE_CODE (lhs
) != SSA_NAME
)
5599 stmt
= SSA_NAME_DEF_STMT (lhs
);
5601 if (TREE_CODE (stmt
) == PHI_NODE
)
5604 if (TREE_CODE (stmt
) != MODIFY_EXPR
5605 || TREE_OPERAND (stmt
, 0) != lhs
)
5608 rhs
= TREE_OPERAND (stmt
, 1);
5609 if (TREE_CODE (rhs
) == WITH_SIZE_EXPR
)
5610 rhs
= TREE_OPERAND (rhs
, 0);
5612 if ((TREE_CODE (rhs
) != NOP_EXPR
5613 && TREE_CODE (rhs
) != CONVERT_EXPR
5614 && (TREE_CODE (rhs
) != PLUS_EXPR
5615 || TREE_CODE (TREE_OPERAND (rhs
, 1)) != INTEGER_CST
5616 || !host_integerp (TREE_OPERAND (rhs
, 1), 1)))
5617 || TREE_CODE (TREE_OPERAND (rhs
, 0)) != SSA_NAME
)
5620 lhs
= TREE_OPERAND (rhs
, 0);
5624 /* Check if LHS = RHS statement is
5625 LHS = *(ap.__base + ap.__offset + cst)
5628 + ((ap.__offset + cst <= 47)
5629 ? ap.__offset + cst - 48 : ap.__offset + cst) + cst2).
5630 If the former, indicate that GPR registers are needed,
5631 if the latter, indicate that FPR registers are needed.
5632 On alpha, cfun->va_list_gpr_size is used as size of the needed
5633 regs and cfun->va_list_fpr_size is a bitmask, bit 0 set if
5634 GPR registers are needed and bit 1 set if FPR registers are needed.
5635 Return true if va_list references should not be scanned for the current
5639 alpha_stdarg_optimize_hook (struct stdarg_info
*si
, tree lhs
, tree rhs
)
5641 tree base
, offset
, arg1
, arg2
;
5644 if (TREE_CODE (rhs
) != INDIRECT_REF
5645 || TREE_CODE (TREE_OPERAND (rhs
, 0)) != SSA_NAME
)
5648 lhs
= va_list_skip_additions (TREE_OPERAND (rhs
, 0));
5649 if (lhs
== NULL_TREE
5650 || TREE_CODE (lhs
) != PLUS_EXPR
)
5653 base
= TREE_OPERAND (lhs
, 0);
5654 if (TREE_CODE (base
) == SSA_NAME
)
5655 base
= va_list_skip_additions (base
);
5657 if (TREE_CODE (base
) != COMPONENT_REF
5658 || TREE_OPERAND (base
, 1) != TYPE_FIELDS (va_list_type_node
))
5660 base
= TREE_OPERAND (lhs
, 0);
5661 if (TREE_CODE (base
) == SSA_NAME
)
5662 base
= va_list_skip_additions (base
);
5664 if (TREE_CODE (base
) != COMPONENT_REF
5665 || TREE_OPERAND (base
, 1) != TYPE_FIELDS (va_list_type_node
))
5671 base
= get_base_address (base
);
5672 if (TREE_CODE (base
) != VAR_DECL
5673 || !bitmap_bit_p (si
->va_list_vars
, var_ann (base
)->uid
))
5676 offset
= TREE_OPERAND (lhs
, offset_arg
);
5677 if (TREE_CODE (offset
) == SSA_NAME
)
5678 offset
= va_list_skip_additions (offset
);
5680 if (TREE_CODE (offset
) == PHI_NODE
)
5684 if (PHI_NUM_ARGS (offset
) != 2)
5687 arg1
= va_list_skip_additions (PHI_ARG_DEF (offset
, 0));
5688 arg2
= va_list_skip_additions (PHI_ARG_DEF (offset
, 1));
5689 if (TREE_CODE (arg2
) != MINUS_EXPR
&& TREE_CODE (arg2
) != PLUS_EXPR
)
5695 if (TREE_CODE (arg2
) != MINUS_EXPR
&& TREE_CODE (arg2
) != PLUS_EXPR
)
5698 if (!host_integerp (TREE_OPERAND (arg2
, 1), 0))
5701 sub
= tree_low_cst (TREE_OPERAND (arg2
, 1), 0);
5702 if (TREE_CODE (arg2
) == MINUS_EXPR
)
5704 if (sub
< -48 || sub
> -32)
5707 arg2
= va_list_skip_additions (TREE_OPERAND (arg2
, 0));
5711 if (TREE_CODE (arg1
) == SSA_NAME
)
5712 arg1
= va_list_skip_additions (arg1
);
5714 if (TREE_CODE (arg1
) != COMPONENT_REF
5715 || TREE_OPERAND (arg1
, 1) != va_list_gpr_counter_field
5716 || get_base_address (arg1
) != base
)
5719 /* Need floating point regs. */
5720 cfun
->va_list_fpr_size
|= 2;
5722 else if (TREE_CODE (offset
) != COMPONENT_REF
5723 || TREE_OPERAND (offset
, 1) != va_list_gpr_counter_field
5724 || get_base_address (offset
) != base
)
5727 /* Need general regs. */
5728 cfun
->va_list_fpr_size
|= 1;
5732 si
->va_list_escapes
= true;
5737 /* Perform any needed actions needed for a function that is receiving a
5738 variable number of arguments. */
5741 alpha_setup_incoming_varargs (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
5742 tree type
, int *pretend_size
, int no_rtl
)
5744 CUMULATIVE_ARGS cum
= *pcum
;
5746 /* Skip the current argument. */
5747 FUNCTION_ARG_ADVANCE (cum
, mode
, type
, 1);
5749 #if TARGET_ABI_UNICOSMK
5750 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
5751 arguments on the stack. Unfortunately, it doesn't always store the first
5752 one (i.e. the one that arrives in $16 or $f16). This is not a problem
5753 with stdargs as we always have at least one named argument there. */
5754 if (cum
.num_reg_words
< 6)
5758 emit_insn (gen_umk_mismatch_args (GEN_INT (cum
.num_reg_words
)));
5759 emit_insn (gen_arg_home_umk ());
5763 #elif TARGET_ABI_OPEN_VMS
5764 /* For VMS, we allocate space for all 6 arg registers plus a count.
5766 However, if NO registers need to be saved, don't allocate any space.
5767 This is not only because we won't need the space, but because AP
5768 includes the current_pretend_args_size and we don't want to mess up
5769 any ap-relative addresses already made. */
5770 if (cum
.num_args
< 6)
5774 emit_move_insn (gen_rtx_REG (DImode
, 1), virtual_incoming_args_rtx
);
5775 emit_insn (gen_arg_home ());
5777 *pretend_size
= 7 * UNITS_PER_WORD
;
5780 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
5781 only push those that are remaining. However, if NO registers need to
5782 be saved, don't allocate any space. This is not only because we won't
5783 need the space, but because AP includes the current_pretend_args_size
5784 and we don't want to mess up any ap-relative addresses already made.
5786 If we are not to use the floating-point registers, save the integer
5787 registers where we would put the floating-point registers. This is
5788 not the most efficient way to implement varargs with just one register
5789 class, but it isn't worth doing anything more efficient in this rare
5796 int count
, set
= get_varargs_alias_set ();
5799 count
= cfun
->va_list_gpr_size
/ UNITS_PER_WORD
;
5800 if (count
> 6 - cum
)
5803 /* Detect whether integer registers or floating-point registers
5804 are needed by the detected va_arg statements. See above for
5805 how these values are computed. Note that the "escape" value
5806 is VA_LIST_MAX_FPR_SIZE, which is 255, which has both of
5808 gcc_assert ((VA_LIST_MAX_FPR_SIZE
& 3) == 3);
5810 if (cfun
->va_list_fpr_size
& 1)
5812 tmp
= gen_rtx_MEM (BLKmode
,
5813 plus_constant (virtual_incoming_args_rtx
,
5814 (cum
+ 6) * UNITS_PER_WORD
));
5815 set_mem_alias_set (tmp
, set
);
5816 move_block_from_reg (16 + cum
, tmp
, count
);
5819 if (cfun
->va_list_fpr_size
& 2)
5821 tmp
= gen_rtx_MEM (BLKmode
,
5822 plus_constant (virtual_incoming_args_rtx
,
5823 cum
* UNITS_PER_WORD
));
5824 set_mem_alias_set (tmp
, set
);
5825 move_block_from_reg (16 + cum
+ TARGET_FPREGS
*32, tmp
, count
);
5828 *pretend_size
= 12 * UNITS_PER_WORD
;
5833 alpha_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
5835 HOST_WIDE_INT offset
;
5836 tree t
, offset_field
, base_field
;
5838 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
5841 if (TARGET_ABI_UNICOSMK
)
5842 std_expand_builtin_va_start (valist
, nextarg
);
5844 /* For Unix, TARGET_SETUP_INCOMING_VARARGS moves the starting address base
5845 up by 48, storing fp arg registers in the first 48 bytes, and the
5846 integer arg registers in the next 48 bytes. This is only done,
5847 however, if any integer registers need to be stored.
5849 If no integer registers need be stored, then we must subtract 48
5850 in order to account for the integer arg registers which are counted
5851 in argsize above, but which are not actually stored on the stack.
5852 Must further be careful here about structures straddling the last
5853 integer argument register; that futzes with pretend_args_size,
5854 which changes the meaning of AP. */
5857 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
5859 offset
= -6 * UNITS_PER_WORD
+ current_function_pretend_args_size
;
5861 if (TARGET_ABI_OPEN_VMS
)
5863 nextarg
= plus_constant (nextarg
, offset
);
5864 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
5865 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
5866 make_tree (ptr_type_node
, nextarg
));
5867 TREE_SIDE_EFFECTS (t
) = 1;
5869 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5873 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
5874 offset_field
= TREE_CHAIN (base_field
);
5876 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
5877 valist
, base_field
, NULL_TREE
);
5878 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
5879 valist
, offset_field
, NULL_TREE
);
5881 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
5882 t
= build (PLUS_EXPR
, ptr_type_node
, t
,
5883 build_int_cst (NULL_TREE
, offset
));
5884 t
= build (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
5885 TREE_SIDE_EFFECTS (t
) = 1;
5886 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5888 t
= build_int_cst (NULL_TREE
, NUM_ARGS
* UNITS_PER_WORD
);
5889 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
5890 TREE_SIDE_EFFECTS (t
) = 1;
5891 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5896 alpha_gimplify_va_arg_1 (tree type
, tree base
, tree offset
, tree
*pre_p
)
5898 tree type_size
, ptr_type
, addend
, t
, addr
, internal_post
;
5900 /* If the type could not be passed in registers, skip the block
5901 reserved for the registers. */
5902 if (targetm
.calls
.must_pass_in_stack (TYPE_MODE (type
), type
))
5904 t
= build_int_cst (TREE_TYPE (offset
), 6*8);
5905 t
= build (MODIFY_EXPR
, TREE_TYPE (offset
), offset
,
5906 build (MAX_EXPR
, TREE_TYPE (offset
), offset
, t
));
5907 gimplify_and_add (t
, pre_p
);
5911 ptr_type
= build_pointer_type (type
);
5913 if (TREE_CODE (type
) == COMPLEX_TYPE
)
5915 tree real_part
, imag_part
, real_temp
;
5917 real_part
= alpha_gimplify_va_arg_1 (TREE_TYPE (type
), base
,
5920 /* Copy the value into a new temporary, lest the formal temporary
5921 be reused out from under us. */
5922 real_temp
= get_initialized_tmp_var (real_part
, pre_p
, NULL
);
5924 imag_part
= alpha_gimplify_va_arg_1 (TREE_TYPE (type
), base
,
5927 return build (COMPLEX_EXPR
, type
, real_temp
, imag_part
);
5929 else if (TREE_CODE (type
) == REAL_TYPE
)
5931 tree fpaddend
, cond
, fourtyeight
;
5933 fourtyeight
= build_int_cst (TREE_TYPE (addend
), 6*8);
5934 fpaddend
= fold (build (MINUS_EXPR
, TREE_TYPE (addend
),
5935 addend
, fourtyeight
));
5936 cond
= fold (build (LT_EXPR
, boolean_type_node
, addend
, fourtyeight
));
5937 addend
= fold (build (COND_EXPR
, TREE_TYPE (addend
), cond
,
5941 /* Build the final address and force that value into a temporary. */
5942 addr
= build (PLUS_EXPR
, ptr_type
, fold_convert (ptr_type
, base
),
5943 fold_convert (ptr_type
, addend
));
5944 internal_post
= NULL
;
5945 gimplify_expr (&addr
, pre_p
, &internal_post
, is_gimple_val
, fb_rvalue
);
5946 append_to_statement_list (internal_post
, pre_p
);
5948 /* Update the offset field. */
5949 type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
));
5950 if (type_size
== NULL
|| TREE_OVERFLOW (type_size
))
5954 t
= size_binop (PLUS_EXPR
, type_size
, size_int (7));
5955 t
= size_binop (TRUNC_DIV_EXPR
, t
, size_int (8));
5956 t
= size_binop (MULT_EXPR
, t
, size_int (8));
5958 t
= fold_convert (TREE_TYPE (offset
), t
);
5959 t
= build (MODIFY_EXPR
, void_type_node
, offset
,
5960 build (PLUS_EXPR
, TREE_TYPE (offset
), offset
, t
));
5961 gimplify_and_add (t
, pre_p
);
5963 return build_fold_indirect_ref (addr
);
5967 alpha_gimplify_va_arg (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
5969 tree offset_field
, base_field
, offset
, base
, t
, r
;
5972 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
5973 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
5975 base_field
= TYPE_FIELDS (va_list_type_node
);
5976 offset_field
= TREE_CHAIN (base_field
);
5977 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
5978 valist
, base_field
, NULL_TREE
);
5979 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
5980 valist
, offset_field
, NULL_TREE
);
5982 /* Pull the fields of the structure out into temporaries. Since we never
5983 modify the base field, we can use a formal temporary. Sign-extend the
5984 offset field so that it's the proper width for pointer arithmetic. */
5985 base
= get_formal_tmp_var (base_field
, pre_p
);
5987 t
= fold_convert (lang_hooks
.types
.type_for_size (64, 0), offset_field
);
5988 offset
= get_initialized_tmp_var (t
, pre_p
, NULL
);
5990 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
5992 type
= build_pointer_type (type
);
5994 /* Find the value. Note that this will be a stable indirection, or
5995 a composite of stable indirections in the case of complex. */
5996 r
= alpha_gimplify_va_arg_1 (type
, base
, offset
, pre_p
);
5998 /* Stuff the offset temporary back into its field. */
5999 t
= build (MODIFY_EXPR
, void_type_node
, offset_field
,
6000 fold_convert (TREE_TYPE (offset_field
), offset
));
6001 gimplify_and_add (t
, pre_p
);
6004 r
= build_fold_indirect_ref (r
);
6013 ALPHA_BUILTIN_CMPBGE
,
6014 ALPHA_BUILTIN_EXTBL
,
6015 ALPHA_BUILTIN_EXTWL
,
6016 ALPHA_BUILTIN_EXTLL
,
6017 ALPHA_BUILTIN_EXTQL
,
6018 ALPHA_BUILTIN_EXTWH
,
6019 ALPHA_BUILTIN_EXTLH
,
6020 ALPHA_BUILTIN_EXTQH
,
6021 ALPHA_BUILTIN_INSBL
,
6022 ALPHA_BUILTIN_INSWL
,
6023 ALPHA_BUILTIN_INSLL
,
6024 ALPHA_BUILTIN_INSQL
,
6025 ALPHA_BUILTIN_INSWH
,
6026 ALPHA_BUILTIN_INSLH
,
6027 ALPHA_BUILTIN_INSQH
,
6028 ALPHA_BUILTIN_MSKBL
,
6029 ALPHA_BUILTIN_MSKWL
,
6030 ALPHA_BUILTIN_MSKLL
,
6031 ALPHA_BUILTIN_MSKQL
,
6032 ALPHA_BUILTIN_MSKWH
,
6033 ALPHA_BUILTIN_MSKLH
,
6034 ALPHA_BUILTIN_MSKQH
,
6035 ALPHA_BUILTIN_UMULH
,
6037 ALPHA_BUILTIN_ZAPNOT
,
6038 ALPHA_BUILTIN_AMASK
,
6039 ALPHA_BUILTIN_IMPLVER
,
6041 ALPHA_BUILTIN_THREAD_POINTER
,
6042 ALPHA_BUILTIN_SET_THREAD_POINTER
,
6045 ALPHA_BUILTIN_MINUB8
,
6046 ALPHA_BUILTIN_MINSB8
,
6047 ALPHA_BUILTIN_MINUW4
,
6048 ALPHA_BUILTIN_MINSW4
,
6049 ALPHA_BUILTIN_MAXUB8
,
6050 ALPHA_BUILTIN_MAXSB8
,
6051 ALPHA_BUILTIN_MAXUW4
,
6052 ALPHA_BUILTIN_MAXSW4
,
6056 ALPHA_BUILTIN_UNPKBL
,
6057 ALPHA_BUILTIN_UNPKBW
,
6062 ALPHA_BUILTIN_CTPOP
,
6067 static unsigned int const code_for_builtin
[ALPHA_BUILTIN_max
] = {
6068 CODE_FOR_builtin_cmpbge
,
6069 CODE_FOR_builtin_extbl
,
6070 CODE_FOR_builtin_extwl
,
6071 CODE_FOR_builtin_extll
,
6072 CODE_FOR_builtin_extql
,
6073 CODE_FOR_builtin_extwh
,
6074 CODE_FOR_builtin_extlh
,
6075 CODE_FOR_builtin_extqh
,
6076 CODE_FOR_builtin_insbl
,
6077 CODE_FOR_builtin_inswl
,
6078 CODE_FOR_builtin_insll
,
6079 CODE_FOR_builtin_insql
,
6080 CODE_FOR_builtin_inswh
,
6081 CODE_FOR_builtin_inslh
,
6082 CODE_FOR_builtin_insqh
,
6083 CODE_FOR_builtin_mskbl
,
6084 CODE_FOR_builtin_mskwl
,
6085 CODE_FOR_builtin_mskll
,
6086 CODE_FOR_builtin_mskql
,
6087 CODE_FOR_builtin_mskwh
,
6088 CODE_FOR_builtin_msklh
,
6089 CODE_FOR_builtin_mskqh
,
6090 CODE_FOR_umuldi3_highpart
,
6091 CODE_FOR_builtin_zap
,
6092 CODE_FOR_builtin_zapnot
,
6093 CODE_FOR_builtin_amask
,
6094 CODE_FOR_builtin_implver
,
6095 CODE_FOR_builtin_rpcc
,
6100 CODE_FOR_builtin_minub8
,
6101 CODE_FOR_builtin_minsb8
,
6102 CODE_FOR_builtin_minuw4
,
6103 CODE_FOR_builtin_minsw4
,
6104 CODE_FOR_builtin_maxub8
,
6105 CODE_FOR_builtin_maxsb8
,
6106 CODE_FOR_builtin_maxuw4
,
6107 CODE_FOR_builtin_maxsw4
,
6108 CODE_FOR_builtin_perr
,
6109 CODE_FOR_builtin_pklb
,
6110 CODE_FOR_builtin_pkwb
,
6111 CODE_FOR_builtin_unpkbl
,
6112 CODE_FOR_builtin_unpkbw
,
6117 CODE_FOR_popcountdi2
6120 struct alpha_builtin_def
6123 enum alpha_builtin code
;
6124 unsigned int target_mask
;
6128 static struct alpha_builtin_def
const zero_arg_builtins
[] = {
6129 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER
, 0, true },
6130 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC
, 0, false }
6133 static struct alpha_builtin_def
const one_arg_builtins
[] = {
6134 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK
, 0, true },
6135 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB
, MASK_MAX
, true },
6136 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB
, MASK_MAX
, true },
6137 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL
, MASK_MAX
, true },
6138 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW
, MASK_MAX
, true },
6139 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ
, MASK_CIX
, true },
6140 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ
, MASK_CIX
, true },
6141 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP
, MASK_CIX
, true }
6144 static struct alpha_builtin_def
const two_arg_builtins
[] = {
6145 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE
, 0, true },
6146 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL
, 0, true },
6147 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL
, 0, true },
6148 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL
, 0, true },
6149 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL
, 0, true },
6150 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH
, 0, true },
6151 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH
, 0, true },
6152 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH
, 0, true },
6153 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL
, 0, true },
6154 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL
, 0, true },
6155 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL
, 0, true },
6156 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL
, 0, true },
6157 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH
, 0, true },
6158 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH
, 0, true },
6159 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH
, 0, true },
6160 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL
, 0, true },
6161 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL
, 0, true },
6162 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL
, 0, true },
6163 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL
, 0, true },
6164 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH
, 0, true },
6165 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH
, 0, true },
6166 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH
, 0, true },
6167 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH
, 0, true },
6168 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP
, 0, true },
6169 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT
, 0, true },
6170 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8
, MASK_MAX
, true },
6171 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8
, MASK_MAX
, true },
6172 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4
, MASK_MAX
, true },
6173 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4
, MASK_MAX
, true },
6174 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8
, MASK_MAX
, true },
6175 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8
, MASK_MAX
, true },
6176 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4
, MASK_MAX
, true },
6177 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4
, MASK_MAX
, true },
6178 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR
, MASK_MAX
, true }
6181 static GTY(()) tree alpha_v8qi_u
;
6182 static GTY(()) tree alpha_v8qi_s
;
6183 static GTY(()) tree alpha_v4hi_u
;
6184 static GTY(()) tree alpha_v4hi_s
;
6187 alpha_init_builtins (void)
6189 const struct alpha_builtin_def
*p
;
6190 tree ftype
, attrs
[2];
6193 attrs
[0] = tree_cons (get_identifier ("nothrow"), NULL
, NULL
);
6194 attrs
[1] = tree_cons (get_identifier ("const"), NULL
, attrs
[0]);
6196 ftype
= build_function_type (long_integer_type_node
, void_list_node
);
6198 p
= zero_arg_builtins
;
6199 for (i
= 0; i
< ARRAY_SIZE (zero_arg_builtins
); ++i
, ++p
)
6200 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6201 lang_hooks
.builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6202 NULL
, attrs
[p
->is_const
]);
6204 ftype
= build_function_type_list (long_integer_type_node
,
6205 long_integer_type_node
, NULL_TREE
);
6207 p
= one_arg_builtins
;
6208 for (i
= 0; i
< ARRAY_SIZE (one_arg_builtins
); ++i
, ++p
)
6209 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6210 lang_hooks
.builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6211 NULL
, attrs
[p
->is_const
]);
6213 ftype
= build_function_type_list (long_integer_type_node
,
6214 long_integer_type_node
,
6215 long_integer_type_node
, NULL_TREE
);
6217 p
= two_arg_builtins
;
6218 for (i
= 0; i
< ARRAY_SIZE (two_arg_builtins
); ++i
, ++p
)
6219 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6220 lang_hooks
.builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6221 NULL
, attrs
[p
->is_const
]);
6223 ftype
= build_function_type (ptr_type_node
, void_list_node
);
6224 lang_hooks
.builtin_function ("__builtin_thread_pointer", ftype
,
6225 ALPHA_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
6228 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
6229 lang_hooks
.builtin_function ("__builtin_set_thread_pointer", ftype
,
6230 ALPHA_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
6233 alpha_v8qi_u
= build_vector_type (unsigned_intQI_type_node
, 8);
6234 alpha_v8qi_s
= build_vector_type (intQI_type_node
, 8);
6235 alpha_v4hi_u
= build_vector_type (unsigned_intHI_type_node
, 4);
6236 alpha_v4hi_s
= build_vector_type (intHI_type_node
, 4);
6239 /* Expand an expression EXP that calls a built-in function,
6240 with result going to TARGET if that's convenient
6241 (and in mode MODE if that's convenient).
6242 SUBTARGET may be used as the target for computing one of EXP's operands.
6243 IGNORE is nonzero if the value is to be ignored. */
6246 alpha_expand_builtin (tree exp
, rtx target
,
6247 rtx subtarget ATTRIBUTE_UNUSED
,
6248 enum machine_mode mode ATTRIBUTE_UNUSED
,
6249 int ignore ATTRIBUTE_UNUSED
)
6253 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6254 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6255 tree arglist
= TREE_OPERAND (exp
, 1);
6256 enum insn_code icode
;
6257 rtx op
[MAX_ARGS
], pat
;
6261 if (fcode
>= ALPHA_BUILTIN_max
)
6262 internal_error ("bad builtin fcode");
6263 icode
= code_for_builtin
[fcode
];
6265 internal_error ("bad builtin fcode");
6267 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
6269 for (arglist
= TREE_OPERAND (exp
, 1), arity
= 0;
6271 arglist
= TREE_CHAIN (arglist
), arity
++)
6273 const struct insn_operand_data
*insn_op
;
6275 tree arg
= TREE_VALUE (arglist
);
6276 if (arg
== error_mark_node
)
6278 if (arity
> MAX_ARGS
)
6281 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
6283 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, 0);
6285 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
6286 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
6291 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6293 || GET_MODE (target
) != tmode
6294 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6295 target
= gen_reg_rtx (tmode
);
6301 pat
= GEN_FCN (icode
) (target
);
6305 pat
= GEN_FCN (icode
) (target
, op
[0]);
6307 pat
= GEN_FCN (icode
) (op
[0]);
6310 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
6326 /* Several bits below assume HWI >= 64 bits. This should be enforced
6328 #if HOST_BITS_PER_WIDE_INT < 64
6329 # error "HOST_WIDE_INT too small"
6332 /* Fold the builtin for the CMPBGE instruction. This is a vector comparison
6333 with an 8 bit output vector. OPINT contains the integer operands; bit N
6334 of OP_CONST is set if OPINT[N] is valid. */
6337 alpha_fold_builtin_cmpbge (unsigned HOST_WIDE_INT opint
[], long op_const
)
6342 for (i
= 0, val
= 0; i
< 8; ++i
)
6344 unsigned HOST_WIDE_INT c0
= (opint
[0] >> (i
* 8)) & 0xff;
6345 unsigned HOST_WIDE_INT c1
= (opint
[1] >> (i
* 8)) & 0xff;
6349 return build_int_cst (long_integer_type_node
, val
);
6351 else if (op_const
== 2 && opint
[1] == 0)
6352 return build_int_cst (long_integer_type_node
, 0xff);
6356 /* Fold the builtin for the ZAPNOT instruction. This is essentially a
6357 specialized form of an AND operation. Other byte manipulation instructions
6358 are defined in terms of this instruction, so this is also used as a
6359 subroutine for other builtins.
6361 OP contains the tree operands; OPINT contains the extracted integer values.
6362 Bit N of OP_CONST it set if OPINT[N] is valid. OP may be null if only
6363 OPINT may be considered. */
6366 alpha_fold_builtin_zapnot (tree
*op
, unsigned HOST_WIDE_INT opint
[],
6371 unsigned HOST_WIDE_INT mask
= 0;
6374 for (i
= 0; i
< 8; ++i
)
6375 if ((opint
[1] >> i
) & 1)
6376 mask
|= (unsigned HOST_WIDE_INT
)0xff << (i
* 8);
6379 return build_int_cst (long_integer_type_node
, opint
[0] & mask
);
6382 return fold (build2 (BIT_AND_EXPR
, long_integer_type_node
, op
[0],
6383 build_int_cst (long_integer_type_node
, mask
)));
6385 else if ((op_const
& 1) && opint
[0] == 0)
6386 return build_int_cst (long_integer_type_node
, 0);
6390 /* Fold the builtins for the EXT family of instructions. */
6393 alpha_fold_builtin_extxx (tree op
[], unsigned HOST_WIDE_INT opint
[],
6394 long op_const
, unsigned HOST_WIDE_INT bytemask
,
6398 tree
*zap_op
= NULL
;
6402 unsigned HOST_WIDE_INT loc
;
6405 if (BYTES_BIG_ENDIAN
)
6413 unsigned HOST_WIDE_INT temp
= opint
[0];
6426 opint
[1] = bytemask
;
6427 return alpha_fold_builtin_zapnot (zap_op
, opint
, zap_const
);
6430 /* Fold the builtins for the INS family of instructions. */
6433 alpha_fold_builtin_insxx (tree op
[], unsigned HOST_WIDE_INT opint
[],
6434 long op_const
, unsigned HOST_WIDE_INT bytemask
,
6437 if ((op_const
& 1) && opint
[0] == 0)
6438 return build_int_cst (long_integer_type_node
, 0);
6442 unsigned HOST_WIDE_INT temp
, loc
, byteloc
;
6443 tree
*zap_op
= NULL
;
6446 if (BYTES_BIG_ENDIAN
)
6453 byteloc
= (64 - (loc
* 8)) & 0x3f;
6470 opint
[1] = bytemask
;
6471 return alpha_fold_builtin_zapnot (zap_op
, opint
, op_const
);
6478 alpha_fold_builtin_mskxx (tree op
[], unsigned HOST_WIDE_INT opint
[],
6479 long op_const
, unsigned HOST_WIDE_INT bytemask
,
6484 unsigned HOST_WIDE_INT loc
;
6487 if (BYTES_BIG_ENDIAN
)
6494 opint
[1] = bytemask
^ 0xff;
6497 return alpha_fold_builtin_zapnot (op
, opint
, op_const
);
6501 alpha_fold_builtin_umulh (unsigned HOST_WIDE_INT opint
[], long op_const
)
6507 unsigned HOST_WIDE_INT l
;
6510 mul_double (opint
[0], 0, opint
[1], 0, &l
, &h
);
6512 #if HOST_BITS_PER_WIDE_INT > 64
6516 return build_int_cst (long_integer_type_node
, h
);
6520 opint
[1] = opint
[0];
6523 /* Note that (X*1) >> 64 == 0. */
6524 if (opint
[1] == 0 || opint
[1] == 1)
6525 return build_int_cst (long_integer_type_node
, 0);
6532 alpha_fold_vector_minmax (enum tree_code code
, tree op
[], tree vtype
)
6534 tree op0
= fold_convert (vtype
, op
[0]);
6535 tree op1
= fold_convert (vtype
, op
[1]);
6536 tree val
= fold (build2 (code
, vtype
, op0
, op1
));
6537 return fold_convert (long_integer_type_node
, val
);
6541 alpha_fold_builtin_perr (unsigned HOST_WIDE_INT opint
[], long op_const
)
6543 unsigned HOST_WIDE_INT temp
= 0;
6549 for (i
= 0; i
< 8; ++i
)
6551 unsigned HOST_WIDE_INT a
= (opint
[0] >> (i
* 8)) & 0xff;
6552 unsigned HOST_WIDE_INT b
= (opint
[1] >> (i
* 8)) & 0xff;
6559 return build_int_cst (long_integer_type_node
, temp
);
6563 alpha_fold_builtin_pklb (unsigned HOST_WIDE_INT opint
[], long op_const
)
6565 unsigned HOST_WIDE_INT temp
;
6570 temp
= opint
[0] & 0xff;
6571 temp
|= (opint
[0] >> 24) & 0xff00;
6573 return build_int_cst (long_integer_type_node
, temp
);
6577 alpha_fold_builtin_pkwb (unsigned HOST_WIDE_INT opint
[], long op_const
)
6579 unsigned HOST_WIDE_INT temp
;
6584 temp
= opint
[0] & 0xff;
6585 temp
|= (opint
[0] >> 8) & 0xff00;
6586 temp
|= (opint
[0] >> 16) & 0xff0000;
6587 temp
|= (opint
[0] >> 24) & 0xff000000;
6589 return build_int_cst (long_integer_type_node
, temp
);
6593 alpha_fold_builtin_unpkbl (unsigned HOST_WIDE_INT opint
[], long op_const
)
6595 unsigned HOST_WIDE_INT temp
;
6600 temp
= opint
[0] & 0xff;
6601 temp
|= (opint
[0] & 0xff00) << 24;
6603 return build_int_cst (long_integer_type_node
, temp
);
6607 alpha_fold_builtin_unpkbw (unsigned HOST_WIDE_INT opint
[], long op_const
)
6609 unsigned HOST_WIDE_INT temp
;
6614 temp
= opint
[0] & 0xff;
6615 temp
|= (opint
[0] & 0x0000ff00) << 8;
6616 temp
|= (opint
[0] & 0x00ff0000) << 16;
6617 temp
|= (opint
[0] & 0xff000000) << 24;
6619 return build_int_cst (long_integer_type_node
, temp
);
6623 alpha_fold_builtin_cttz (unsigned HOST_WIDE_INT opint
[], long op_const
)
6625 unsigned HOST_WIDE_INT temp
;
6633 temp
= exact_log2 (opint
[0] & -opint
[0]);
6635 return build_int_cst (long_integer_type_node
, temp
);
6639 alpha_fold_builtin_ctlz (unsigned HOST_WIDE_INT opint
[], long op_const
)
6641 unsigned HOST_WIDE_INT temp
;
6649 temp
= 64 - floor_log2 (opint
[0]) - 1;
6651 return build_int_cst (long_integer_type_node
, temp
);
6655 alpha_fold_builtin_ctpop (unsigned HOST_WIDE_INT opint
[], long op_const
)
6657 unsigned HOST_WIDE_INT temp
, op
;
6665 temp
++, op
&= op
- 1;
6667 return build_int_cst (long_integer_type_node
, temp
);
6670 /* Fold one of our builtin functions. */
6673 alpha_fold_builtin (tree fndecl
, tree arglist
, bool ignore ATTRIBUTE_UNUSED
)
6675 tree op
[MAX_ARGS
], t
;
6676 unsigned HOST_WIDE_INT opint
[MAX_ARGS
];
6677 long op_const
= 0, arity
= 0;
6679 for (t
= arglist
; t
; t
= TREE_CHAIN (t
), ++arity
)
6681 tree arg
= TREE_VALUE (t
);
6682 if (arg
== error_mark_node
)
6684 if (arity
>= MAX_ARGS
)
6689 if (TREE_CODE (arg
) == INTEGER_CST
)
6691 op_const
|= 1L << arity
;
6692 opint
[arity
] = int_cst_value (arg
);
6696 switch (DECL_FUNCTION_CODE (fndecl
))
6698 case ALPHA_BUILTIN_CMPBGE
:
6699 return alpha_fold_builtin_cmpbge (opint
, op_const
);
6701 case ALPHA_BUILTIN_EXTBL
:
6702 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x01, false);
6703 case ALPHA_BUILTIN_EXTWL
:
6704 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x03, false);
6705 case ALPHA_BUILTIN_EXTLL
:
6706 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x0f, false);
6707 case ALPHA_BUILTIN_EXTQL
:
6708 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0xff, false);
6709 case ALPHA_BUILTIN_EXTWH
:
6710 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x03, true);
6711 case ALPHA_BUILTIN_EXTLH
:
6712 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x0f, true);
6713 case ALPHA_BUILTIN_EXTQH
:
6714 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0xff, true);
6716 case ALPHA_BUILTIN_INSBL
:
6717 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x01, false);
6718 case ALPHA_BUILTIN_INSWL
:
6719 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x03, false);
6720 case ALPHA_BUILTIN_INSLL
:
6721 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x0f, false);
6722 case ALPHA_BUILTIN_INSQL
:
6723 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0xff, false);
6724 case ALPHA_BUILTIN_INSWH
:
6725 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x03, true);
6726 case ALPHA_BUILTIN_INSLH
:
6727 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x0f, true);
6728 case ALPHA_BUILTIN_INSQH
:
6729 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0xff, true);
6731 case ALPHA_BUILTIN_MSKBL
:
6732 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x01, false);
6733 case ALPHA_BUILTIN_MSKWL
:
6734 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x03, false);
6735 case ALPHA_BUILTIN_MSKLL
:
6736 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x0f, false);
6737 case ALPHA_BUILTIN_MSKQL
:
6738 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0xff, false);
6739 case ALPHA_BUILTIN_MSKWH
:
6740 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x03, true);
6741 case ALPHA_BUILTIN_MSKLH
:
6742 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x0f, true);
6743 case ALPHA_BUILTIN_MSKQH
:
6744 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0xff, true);
6746 case ALPHA_BUILTIN_UMULH
:
6747 return alpha_fold_builtin_umulh (opint
, op_const
);
6749 case ALPHA_BUILTIN_ZAP
:
6752 case ALPHA_BUILTIN_ZAPNOT
:
6753 return alpha_fold_builtin_zapnot (op
, opint
, op_const
);
6755 case ALPHA_BUILTIN_MINUB8
:
6756 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v8qi_u
);
6757 case ALPHA_BUILTIN_MINSB8
:
6758 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v8qi_s
);
6759 case ALPHA_BUILTIN_MINUW4
:
6760 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v4hi_u
);
6761 case ALPHA_BUILTIN_MINSW4
:
6762 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v4hi_s
);
6763 case ALPHA_BUILTIN_MAXUB8
:
6764 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v8qi_u
);
6765 case ALPHA_BUILTIN_MAXSB8
:
6766 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v8qi_s
);
6767 case ALPHA_BUILTIN_MAXUW4
:
6768 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v4hi_u
);
6769 case ALPHA_BUILTIN_MAXSW4
:
6770 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v4hi_s
);
6772 case ALPHA_BUILTIN_PERR
:
6773 return alpha_fold_builtin_perr (opint
, op_const
);
6774 case ALPHA_BUILTIN_PKLB
:
6775 return alpha_fold_builtin_pklb (opint
, op_const
);
6776 case ALPHA_BUILTIN_PKWB
:
6777 return alpha_fold_builtin_pkwb (opint
, op_const
);
6778 case ALPHA_BUILTIN_UNPKBL
:
6779 return alpha_fold_builtin_unpkbl (opint
, op_const
);
6780 case ALPHA_BUILTIN_UNPKBW
:
6781 return alpha_fold_builtin_unpkbw (opint
, op_const
);
6783 case ALPHA_BUILTIN_CTTZ
:
6784 return alpha_fold_builtin_cttz (opint
, op_const
);
6785 case ALPHA_BUILTIN_CTLZ
:
6786 return alpha_fold_builtin_ctlz (opint
, op_const
);
6787 case ALPHA_BUILTIN_CTPOP
:
6788 return alpha_fold_builtin_ctpop (opint
, op_const
);
6790 case ALPHA_BUILTIN_AMASK
:
6791 case ALPHA_BUILTIN_IMPLVER
:
6792 case ALPHA_BUILTIN_RPCC
:
6793 case ALPHA_BUILTIN_THREAD_POINTER
:
6794 case ALPHA_BUILTIN_SET_THREAD_POINTER
:
6795 /* None of these are foldable at compile-time. */
6801 /* This page contains routines that are used to determine what the function
6802 prologue and epilogue code will do and write them out. */
6804 /* Compute the size of the save area in the stack. */
6806 /* These variables are used for communication between the following functions.
6807 They indicate various things about the current function being compiled
6808 that are used to tell what kind of prologue, epilogue and procedure
6809 descriptor to generate. */
6811 /* Nonzero if we need a stack procedure. */
6812 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
6813 static enum alpha_procedure_types alpha_procedure_type
;
6815 /* Register number (either FP or SP) that is used to unwind the frame. */
6816 static int vms_unwind_regno
;
6818 /* Register number used to save FP. We need not have one for RA since
6819 we don't modify it for register procedures. This is only defined
6820 for register frame procedures. */
6821 static int vms_save_fp_regno
;
6823 /* Register number used to reference objects off our PV. */
6824 static int vms_base_regno
;
6826 /* Compute register masks for saved registers. */
6829 alpha_sa_mask (unsigned long *imaskP
, unsigned long *fmaskP
)
6831 unsigned long imask
= 0;
6832 unsigned long fmask
= 0;
6835 /* When outputting a thunk, we don't have valid register life info,
6836 but assemble_start_function wants to output .frame and .mask
6838 if (current_function_is_thunk
)
6845 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6846 imask
|= (1UL << HARD_FRAME_POINTER_REGNUM
);
6848 /* One for every register we have to save. */
6849 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6850 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
6851 && regs_ever_live
[i
] && i
!= REG_RA
6852 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
6855 imask
|= (1UL << i
);
6857 fmask
|= (1UL << (i
- 32));
6860 /* We need to restore these for the handler. */
6861 if (current_function_calls_eh_return
)
6865 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
6866 if (regno
== INVALID_REGNUM
)
6868 imask
|= 1UL << regno
;
6872 /* If any register spilled, then spill the return address also. */
6873 /* ??? This is required by the Digital stack unwind specification
6874 and isn't needed if we're doing Dwarf2 unwinding. */
6875 if (imask
|| fmask
|| alpha_ra_ever_killed ())
6876 imask
|= (1UL << REG_RA
);
6883 alpha_sa_size (void)
6885 unsigned long mask
[2];
6889 alpha_sa_mask (&mask
[0], &mask
[1]);
6891 if (TARGET_ABI_UNICOSMK
)
6893 if (mask
[0] || mask
[1])
6898 for (j
= 0; j
< 2; ++j
)
6899 for (i
= 0; i
< 32; ++i
)
6900 if ((mask
[j
] >> i
) & 1)
6904 if (TARGET_ABI_UNICOSMK
)
6906 /* We might not need to generate a frame if we don't make any calls
6907 (including calls to __T3E_MISMATCH if this is a vararg function),
6908 don't have any local variables which require stack slots, don't
6909 use alloca and have not determined that we need a frame for other
6912 alpha_procedure_type
6913 = (sa_size
|| get_frame_size() != 0
6914 || current_function_outgoing_args_size
6915 || current_function_stdarg
|| current_function_calls_alloca
6916 || frame_pointer_needed
)
6917 ? PT_STACK
: PT_REGISTER
;
6919 /* Always reserve space for saving callee-saved registers if we
6920 need a frame as required by the calling convention. */
6921 if (alpha_procedure_type
== PT_STACK
)
6924 else if (TARGET_ABI_OPEN_VMS
)
6926 /* Start by assuming we can use a register procedure if we don't
6927 make any calls (REG_RA not used) or need to save any
6928 registers and a stack procedure if we do. */
6929 if ((mask
[0] >> REG_RA
) & 1)
6930 alpha_procedure_type
= PT_STACK
;
6931 else if (get_frame_size() != 0)
6932 alpha_procedure_type
= PT_REGISTER
;
6934 alpha_procedure_type
= PT_NULL
;
6936 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6937 made the final decision on stack procedure vs register procedure. */
6938 if (alpha_procedure_type
== PT_STACK
)
6941 /* Decide whether to refer to objects off our PV via FP or PV.
6942 If we need FP for something else or if we receive a nonlocal
6943 goto (which expects PV to contain the value), we must use PV.
6944 Otherwise, start by assuming we can use FP. */
6947 = (frame_pointer_needed
6948 || current_function_has_nonlocal_label
6949 || alpha_procedure_type
== PT_STACK
6950 || current_function_outgoing_args_size
)
6951 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
6953 /* If we want to copy PV into FP, we need to find some register
6954 in which to save FP. */
6956 vms_save_fp_regno
= -1;
6957 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
6958 for (i
= 0; i
< 32; i
++)
6959 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! regs_ever_live
[i
])
6960 vms_save_fp_regno
= i
;
6962 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
6963 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
6964 else if (alpha_procedure_type
== PT_NULL
)
6965 vms_base_regno
= REG_PV
;
6967 /* Stack unwinding should be done via FP unless we use it for PV. */
6968 vms_unwind_regno
= (vms_base_regno
== REG_PV
6969 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
6971 /* If this is a stack procedure, allow space for saving FP and RA. */
6972 if (alpha_procedure_type
== PT_STACK
)
6977 /* Our size must be even (multiple of 16 bytes). */
6985 /* Define the offset between two registers, one to be eliminated,
6986 and the other its replacement, at the start of a routine. */
6989 alpha_initial_elimination_offset (unsigned int from
,
6990 unsigned int to ATTRIBUTE_UNUSED
)
6994 ret
= alpha_sa_size ();
6995 ret
+= ALPHA_ROUND (current_function_outgoing_args_size
);
6997 if (from
== FRAME_POINTER_REGNUM
)
6999 else if (from
== ARG_POINTER_REGNUM
)
7000 ret
+= (ALPHA_ROUND (get_frame_size ()
7001 + current_function_pretend_args_size
)
7002 - current_function_pretend_args_size
);
7010 alpha_pv_save_size (void)
7013 return alpha_procedure_type
== PT_STACK
? 8 : 0;
7017 alpha_using_fp (void)
7020 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
7023 #if TARGET_ABI_OPEN_VMS
7025 const struct attribute_spec vms_attribute_table
[] =
7027 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
7028 { "overlaid", 0, 0, true, false, false, NULL
},
7029 { "global", 0, 0, true, false, false, NULL
},
7030 { "initialize", 0, 0, true, false, false, NULL
},
7031 { NULL
, 0, 0, false, false, false, NULL
}
7037 find_lo_sum_using_gp (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
7039 return GET_CODE (*px
) == LO_SUM
&& XEXP (*px
, 0) == pic_offset_table_rtx
;
7043 alpha_find_lo_sum_using_gp (rtx insn
)
7045 return for_each_rtx (&PATTERN (insn
), find_lo_sum_using_gp
, NULL
) > 0;
7049 alpha_does_function_need_gp (void)
7053 /* The GP being variable is an OSF abi thing. */
7054 if (! TARGET_ABI_OSF
)
7057 /* We need the gp to load the address of __mcount. */
7058 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7061 /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
7062 if (current_function_is_thunk
)
7065 /* The nonlocal receiver pattern assumes that the gp is valid for
7066 the nested function. Reasonable because it's almost always set
7067 correctly already. For the cases where that's wrong, make sure
7068 the nested function loads its gp on entry. */
7069 if (current_function_has_nonlocal_goto
)
7072 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
7073 Even if we are a static function, we still need to do this in case
7074 our address is taken and passed to something like qsort. */
7076 push_topmost_sequence ();
7077 insn
= get_insns ();
7078 pop_topmost_sequence ();
7080 for (; insn
; insn
= NEXT_INSN (insn
))
7082 && GET_CODE (PATTERN (insn
)) != USE
7083 && GET_CODE (PATTERN (insn
)) != CLOBBER
7084 && get_attr_usegp (insn
))
7091 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
7095 set_frame_related_p (void)
7097 rtx seq
= get_insns ();
7108 while (insn
!= NULL_RTX
)
7110 RTX_FRAME_RELATED_P (insn
) = 1;
7111 insn
= NEXT_INSN (insn
);
7113 seq
= emit_insn (seq
);
7117 seq
= emit_insn (seq
);
7118 RTX_FRAME_RELATED_P (seq
) = 1;
7123 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7125 /* Generates a store with the proper unwind info attached. VALUE is
7126 stored at BASE_REG+BASE_OFS. If FRAME_BIAS is nonzero, then BASE_REG
7127 contains SP+FRAME_BIAS, and that is the unwind info that should be
7128 generated. If FRAME_REG != VALUE, then VALUE is being stored on
7129 behalf of FRAME_REG, and FRAME_REG should be present in the unwind. */
7132 emit_frame_store_1 (rtx value
, rtx base_reg
, HOST_WIDE_INT frame_bias
,
7133 HOST_WIDE_INT base_ofs
, rtx frame_reg
)
7135 rtx addr
, mem
, insn
;
7137 addr
= plus_constant (base_reg
, base_ofs
);
7138 mem
= gen_rtx_MEM (DImode
, addr
);
7139 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7141 insn
= emit_move_insn (mem
, value
);
7142 RTX_FRAME_RELATED_P (insn
) = 1;
7144 if (frame_bias
|| value
!= frame_reg
)
7148 addr
= plus_constant (stack_pointer_rtx
, frame_bias
+ base_ofs
);
7149 mem
= gen_rtx_MEM (DImode
, addr
);
7153 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7154 gen_rtx_SET (VOIDmode
, mem
, frame_reg
),
7160 emit_frame_store (unsigned int regno
, rtx base_reg
,
7161 HOST_WIDE_INT frame_bias
, HOST_WIDE_INT base_ofs
)
7163 rtx reg
= gen_rtx_REG (DImode
, regno
);
7164 emit_frame_store_1 (reg
, base_reg
, frame_bias
, base_ofs
, reg
);
7167 /* Write function prologue. */
7169 /* On vms we have two kinds of functions:
7171 - stack frame (PROC_STACK)
7172 these are 'normal' functions with local vars and which are
7173 calling other functions
7174 - register frame (PROC_REGISTER)
7175 keeps all data in registers, needs no stack
7177 We must pass this to the assembler so it can generate the
7178 proper pdsc (procedure descriptor)
7179 This is done with the '.pdesc' command.
7181 On not-vms, we don't really differentiate between the two, as we can
7182 simply allocate stack without saving registers. */
7185 alpha_expand_prologue (void)
7187 /* Registers to save. */
7188 unsigned long imask
= 0;
7189 unsigned long fmask
= 0;
7190 /* Stack space needed for pushing registers clobbered by us. */
7191 HOST_WIDE_INT sa_size
;
7192 /* Complete stack size needed. */
7193 HOST_WIDE_INT frame_size
;
7194 /* Offset from base reg to register save area. */
7195 HOST_WIDE_INT reg_offset
;
7199 sa_size
= alpha_sa_size ();
7201 frame_size
= get_frame_size ();
7202 if (TARGET_ABI_OPEN_VMS
)
7203 frame_size
= ALPHA_ROUND (sa_size
7204 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7206 + current_function_pretend_args_size
);
7207 else if (TARGET_ABI_UNICOSMK
)
7208 /* We have to allocate space for the DSIB if we generate a frame. */
7209 frame_size
= ALPHA_ROUND (sa_size
7210 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7211 + ALPHA_ROUND (frame_size
7212 + current_function_outgoing_args_size
);
7214 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7216 + ALPHA_ROUND (frame_size
7217 + current_function_pretend_args_size
));
7219 if (TARGET_ABI_OPEN_VMS
)
7222 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7224 alpha_sa_mask (&imask
, &fmask
);
7226 /* Emit an insn to reload GP, if needed. */
7229 alpha_function_needs_gp
= alpha_does_function_need_gp ();
7230 if (alpha_function_needs_gp
)
7231 emit_insn (gen_prologue_ldgp ());
7234 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7235 the call to mcount ourselves, rather than having the linker do it
7236 magically in response to -pg. Since _mcount has special linkage,
7237 don't represent the call as a call. */
7238 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7239 emit_insn (gen_prologue_mcount ());
7241 if (TARGET_ABI_UNICOSMK
)
7242 unicosmk_gen_dsib (&imask
);
7244 /* Adjust the stack by the frame size. If the frame size is > 4096
7245 bytes, we need to be sure we probe somewhere in the first and last
7246 4096 bytes (we can probably get away without the latter test) and
7247 every 8192 bytes in between. If the frame size is > 32768, we
7248 do this in a loop. Otherwise, we generate the explicit probe
7251 Note that we are only allowed to adjust sp once in the prologue. */
7253 if (frame_size
<= 32768)
7255 if (frame_size
> 4096)
7260 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7263 while ((probed
+= 8192) < frame_size
);
7265 /* We only have to do this probe if we aren't saving registers. */
7266 if (sa_size
== 0 && probed
+ 4096 < frame_size
)
7267 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
7270 if (frame_size
!= 0)
7271 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7272 GEN_INT (TARGET_ABI_UNICOSMK
7278 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7279 number of 8192 byte blocks to probe. We then probe each block
7280 in the loop and then set SP to the proper location. If the
7281 amount remaining is > 4096, we have to do one more probe if we
7282 are not saving any registers. */
7284 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
7285 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
7286 rtx ptr
= gen_rtx_REG (DImode
, 22);
7287 rtx count
= gen_rtx_REG (DImode
, 23);
7290 emit_move_insn (count
, GEN_INT (blocks
));
7291 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
7292 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
7294 /* Because of the difficulty in emitting a new basic block this
7295 late in the compilation, generate the loop as a single insn. */
7296 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
7298 if (leftover
> 4096 && sa_size
== 0)
7300 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
7301 MEM_VOLATILE_P (last
) = 1;
7302 emit_move_insn (last
, const0_rtx
);
7305 if (TARGET_ABI_WINDOWS_NT
)
7307 /* For NT stack unwind (done by 'reverse execution'), it's
7308 not OK to take the result of a loop, even though the value
7309 is already in ptr, so we reload it via a single operation
7310 and subtract it to sp.
7312 Yes, that's correct -- we have to reload the whole constant
7313 into a temporary via ldah+lda then subtract from sp. */
7315 HOST_WIDE_INT lo
, hi
;
7316 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7317 hi
= frame_size
- lo
;
7319 emit_move_insn (ptr
, GEN_INT (hi
));
7320 emit_insn (gen_adddi3 (ptr
, ptr
, GEN_INT (lo
)));
7321 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7326 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
7327 GEN_INT (-leftover
)));
7330 /* This alternative is special, because the DWARF code cannot
7331 possibly intuit through the loop above. So we invent this
7332 note it looks at instead. */
7333 RTX_FRAME_RELATED_P (seq
) = 1;
7335 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7336 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7337 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7338 GEN_INT (TARGET_ABI_UNICOSMK
7344 if (!TARGET_ABI_UNICOSMK
)
7346 HOST_WIDE_INT sa_bias
= 0;
7348 /* Cope with very large offsets to the register save area. */
7349 sa_reg
= stack_pointer_rtx
;
7350 if (reg_offset
+ sa_size
> 0x8000)
7352 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7355 if (low
+ sa_size
<= 0x8000)
7356 sa_bias
= reg_offset
- low
, reg_offset
= low
;
7358 sa_bias
= reg_offset
, reg_offset
= 0;
7360 sa_reg
= gen_rtx_REG (DImode
, 24);
7361 sa_bias_rtx
= GEN_INT (sa_bias
);
7363 if (add_operand (sa_bias_rtx
, DImode
))
7364 emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
, sa_bias_rtx
));
7367 emit_move_insn (sa_reg
, sa_bias_rtx
);
7368 emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
, sa_reg
));
7372 /* Save regs in stack order. Beginning with VMS PV. */
7373 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7374 emit_frame_store (REG_PV
, stack_pointer_rtx
, 0, 0);
7376 /* Save register RA next. */
7377 if (imask
& (1UL << REG_RA
))
7379 emit_frame_store (REG_RA
, sa_reg
, sa_bias
, reg_offset
);
7380 imask
&= ~(1UL << REG_RA
);
7384 /* Now save any other registers required to be saved. */
7385 for (i
= 0; i
< 31; i
++)
7386 if (imask
& (1UL << i
))
7388 emit_frame_store (i
, sa_reg
, sa_bias
, reg_offset
);
7392 for (i
= 0; i
< 31; i
++)
7393 if (fmask
& (1UL << i
))
7395 emit_frame_store (i
+32, sa_reg
, sa_bias
, reg_offset
);
7399 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7401 /* The standard frame on the T3E includes space for saving registers.
7402 We just have to use it. We don't have to save the return address and
7403 the old frame pointer here - they are saved in the DSIB. */
7406 for (i
= 9; i
< 15; i
++)
7407 if (imask
& (1UL << i
))
7409 emit_frame_store (i
, hard_frame_pointer_rtx
, 0, reg_offset
);
7412 for (i
= 2; i
< 10; i
++)
7413 if (fmask
& (1UL << i
))
7415 emit_frame_store (i
+32, hard_frame_pointer_rtx
, 0, reg_offset
);
7420 if (TARGET_ABI_OPEN_VMS
)
7422 if (alpha_procedure_type
== PT_REGISTER
)
7423 /* Register frame procedures save the fp.
7424 ?? Ought to have a dwarf2 save for this. */
7425 emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
7426 hard_frame_pointer_rtx
);
7428 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
7429 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
7430 gen_rtx_REG (DImode
, REG_PV
)));
7432 if (alpha_procedure_type
!= PT_NULL
7433 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7434 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7436 /* If we have to allocate space for outgoing args, do it now. */
7437 if (current_function_outgoing_args_size
!= 0)
7440 = emit_move_insn (stack_pointer_rtx
,
7442 (hard_frame_pointer_rtx
,
7444 (current_function_outgoing_args_size
))));
7446 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
7447 if ! frame_pointer_needed. Setting the bit will change the CFA
7448 computation rule to use sp again, which would be wrong if we had
7449 frame_pointer_needed, as this means sp might move unpredictably
7453 frame_pointer_needed
7454 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
7456 current_function_outgoing_args_size != 0
7457 => alpha_procedure_type != PT_NULL,
7459 so when we are not setting the bit here, we are guaranteed to
7460 have emitted an FRP frame pointer update just before. */
7461 RTX_FRAME_RELATED_P (seq
) = ! frame_pointer_needed
;
7464 else if (!TARGET_ABI_UNICOSMK
)
7466 /* If we need a frame pointer, set it from the stack pointer. */
7467 if (frame_pointer_needed
)
7469 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
7470 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7472 /* This must always be the last instruction in the
7473 prologue, thus we emit a special move + clobber. */
7474 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
7475 stack_pointer_rtx
, sa_reg
)));
7479 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7480 the prologue, for exception handling reasons, we cannot do this for
7481 any insn that might fault. We could prevent this for mems with a
7482 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7483 have to prevent all such scheduling with a blockage.
7485 Linux, on the other hand, never bothered to implement OSF/1's
7486 exception handling, and so doesn't care about such things. Anyone
7487 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7489 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
7490 emit_insn (gen_blockage ());
7493 /* Count the number of .file directives, so that .loc is up to date. */
7494 int num_source_filenames
= 0;
7496 /* Output the textual info surrounding the prologue. */
7499 alpha_start_function (FILE *file
, const char *fnname
,
7500 tree decl ATTRIBUTE_UNUSED
)
7502 unsigned long imask
= 0;
7503 unsigned long fmask
= 0;
7504 /* Stack space needed for pushing registers clobbered by us. */
7505 HOST_WIDE_INT sa_size
;
7506 /* Complete stack size needed. */
7507 unsigned HOST_WIDE_INT frame_size
;
7508 /* Offset from base reg to register save area. */
7509 HOST_WIDE_INT reg_offset
;
7510 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
7513 /* Don't emit an extern directive for functions defined in the same file. */
7514 if (TARGET_ABI_UNICOSMK
)
7517 name_tree
= get_identifier (fnname
);
7518 TREE_ASM_WRITTEN (name_tree
) = 1;
7521 alpha_fnname
= fnname
;
7522 sa_size
= alpha_sa_size ();
7524 frame_size
= get_frame_size ();
7525 if (TARGET_ABI_OPEN_VMS
)
7526 frame_size
= ALPHA_ROUND (sa_size
7527 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7529 + current_function_pretend_args_size
);
7530 else if (TARGET_ABI_UNICOSMK
)
7531 frame_size
= ALPHA_ROUND (sa_size
7532 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7533 + ALPHA_ROUND (frame_size
7534 + current_function_outgoing_args_size
);
7536 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7538 + ALPHA_ROUND (frame_size
7539 + current_function_pretend_args_size
));
7541 if (TARGET_ABI_OPEN_VMS
)
7544 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7546 alpha_sa_mask (&imask
, &fmask
);
7548 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7549 We have to do that before the .ent directive as we cannot switch
7550 files within procedures with native ecoff because line numbers are
7551 linked to procedure descriptors.
7552 Outputting the lineno helps debugging of one line functions as they
7553 would otherwise get no line number at all. Please note that we would
7554 like to put out last_linenum from final.c, but it is not accessible. */
7556 if (write_symbols
== SDB_DEBUG
)
7558 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7559 ASM_OUTPUT_SOURCE_FILENAME (file
,
7560 DECL_SOURCE_FILE (current_function_decl
));
7562 #ifdef SDB_OUTPUT_SOURCE_LINE
7563 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
7564 SDB_OUTPUT_SOURCE_LINE (file
,
7565 DECL_SOURCE_LINE (current_function_decl
));
7569 /* Issue function start and label. */
7570 if (TARGET_ABI_OPEN_VMS
7571 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
7573 fputs ("\t.ent ", file
);
7574 assemble_name (file
, fnname
);
7577 /* If the function needs GP, we'll write the "..ng" label there.
7578 Otherwise, do it here. */
7580 && ! alpha_function_needs_gp
7581 && ! current_function_is_thunk
)
7584 assemble_name (file
, fnname
);
7585 fputs ("..ng:\n", file
);
7589 strcpy (entry_label
, fnname
);
7590 if (TARGET_ABI_OPEN_VMS
)
7591 strcat (entry_label
, "..en");
7593 /* For public functions, the label must be globalized by appending an
7594 additional colon. */
7595 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
7596 strcat (entry_label
, ":");
7598 ASM_OUTPUT_LABEL (file
, entry_label
);
7599 inside_function
= TRUE
;
7601 if (TARGET_ABI_OPEN_VMS
)
7602 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
7604 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
7605 && !flag_inhibit_size_directive
)
7607 /* Set flags in procedure descriptor to request IEEE-conformant
7608 math-library routines. The value we set it to is PDSC_EXC_IEEE
7609 (/usr/include/pdsc.h). */
7610 fputs ("\t.eflag 48\n", file
);
7613 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7614 alpha_auto_offset
= -frame_size
+ current_function_pretend_args_size
;
7615 alpha_arg_offset
= -frame_size
+ 48;
7617 /* Describe our frame. If the frame size is larger than an integer,
7618 print it as zero to avoid an assembler error. We won't be
7619 properly describing such a frame, but that's the best we can do. */
7620 if (TARGET_ABI_UNICOSMK
)
7622 else if (TARGET_ABI_OPEN_VMS
)
7623 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,"
7624 HOST_WIDE_INT_PRINT_DEC
"\n",
7626 frame_size
>= (1UL << 31) ? 0 : frame_size
,
7628 else if (!flag_inhibit_size_directive
)
7629 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,%d\n",
7630 (frame_pointer_needed
7631 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
),
7632 frame_size
>= (1UL << 31) ? 0 : frame_size
,
7633 current_function_pretend_args_size
);
7635 /* Describe which registers were spilled. */
7636 if (TARGET_ABI_UNICOSMK
)
7638 else if (TARGET_ABI_OPEN_VMS
)
7641 /* ??? Does VMS care if mask contains ra? The old code didn't
7642 set it, so I don't here. */
7643 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1UL << REG_RA
));
7645 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
7646 if (alpha_procedure_type
== PT_REGISTER
)
7647 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
7649 else if (!flag_inhibit_size_directive
)
7653 fprintf (file
, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", imask
,
7654 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
7656 for (i
= 0; i
< 32; ++i
)
7657 if (imask
& (1UL << i
))
7662 fprintf (file
, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", fmask
,
7663 frame_size
>= (1UL << 31) ? 0 : reg_offset
- frame_size
);
7666 #if TARGET_ABI_OPEN_VMS
7667 /* Ifdef'ed cause link_section are only available then. */
7668 readonly_data_section ();
7669 fprintf (file
, "\t.align 3\n");
7670 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
7671 fputs ("\t.ascii \"", file
);
7672 assemble_name (file
, fnname
);
7673 fputs ("\\0\"\n", file
);
7674 alpha_need_linkage (fnname
, 1);
7679 /* Emit the .prologue note at the scheduled end of the prologue. */
7682 alpha_output_function_end_prologue (FILE *file
)
7684 if (TARGET_ABI_UNICOSMK
)
7686 else if (TARGET_ABI_OPEN_VMS
)
7687 fputs ("\t.prologue\n", file
);
7688 else if (TARGET_ABI_WINDOWS_NT
)
7689 fputs ("\t.prologue 0\n", file
);
7690 else if (!flag_inhibit_size_directive
)
7691 fprintf (file
, "\t.prologue %d\n",
7692 alpha_function_needs_gp
|| current_function_is_thunk
);
7695 /* Write function epilogue. */
7697 /* ??? At some point we will want to support full unwind, and so will
7698 need to mark the epilogue as well. At the moment, we just confuse
7701 #define FRP(exp) exp
7704 alpha_expand_epilogue (void)
7706 /* Registers to save. */
7707 unsigned long imask
= 0;
7708 unsigned long fmask
= 0;
7709 /* Stack space needed for pushing registers clobbered by us. */
7710 HOST_WIDE_INT sa_size
;
7711 /* Complete stack size needed. */
7712 HOST_WIDE_INT frame_size
;
7713 /* Offset from base reg to register save area. */
7714 HOST_WIDE_INT reg_offset
;
7715 int fp_is_frame_pointer
, fp_offset
;
7716 rtx sa_reg
, sa_reg_exp
= NULL
;
7717 rtx sp_adj1
, sp_adj2
, mem
;
7721 sa_size
= alpha_sa_size ();
7723 frame_size
= get_frame_size ();
7724 if (TARGET_ABI_OPEN_VMS
)
7725 frame_size
= ALPHA_ROUND (sa_size
7726 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7728 + current_function_pretend_args_size
);
7729 else if (TARGET_ABI_UNICOSMK
)
7730 frame_size
= ALPHA_ROUND (sa_size
7731 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7732 + ALPHA_ROUND (frame_size
7733 + current_function_outgoing_args_size
);
7735 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7737 + ALPHA_ROUND (frame_size
7738 + current_function_pretend_args_size
));
7740 if (TARGET_ABI_OPEN_VMS
)
7742 if (alpha_procedure_type
== PT_STACK
)
7748 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7750 alpha_sa_mask (&imask
, &fmask
);
7753 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7754 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
7756 sa_reg
= stack_pointer_rtx
;
7758 if (current_function_calls_eh_return
)
7759 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
7763 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
7765 /* If we have a frame pointer, restore SP from it. */
7766 if ((TARGET_ABI_OPEN_VMS
7767 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7768 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
7769 FRP (emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7771 /* Cope with very large offsets to the register save area. */
7772 if (reg_offset
+ sa_size
> 0x8000)
7774 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7777 if (low
+ sa_size
<= 0x8000)
7778 bias
= reg_offset
- low
, reg_offset
= low
;
7780 bias
= reg_offset
, reg_offset
= 0;
7782 sa_reg
= gen_rtx_REG (DImode
, 22);
7783 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
7785 FRP (emit_move_insn (sa_reg
, sa_reg_exp
));
7788 /* Restore registers in order, excepting a true frame pointer. */
7790 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7792 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7793 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7796 imask
&= ~(1UL << REG_RA
);
7798 for (i
= 0; i
< 31; ++i
)
7799 if (imask
& (1UL << i
))
7801 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
7802 fp_offset
= reg_offset
;
7805 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
7806 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7807 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7812 for (i
= 0; i
< 31; ++i
)
7813 if (fmask
& (1UL << i
))
7815 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
7816 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7817 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7821 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7823 /* Restore callee-saved general-purpose registers. */
7827 for (i
= 9; i
< 15; i
++)
7828 if (imask
& (1UL << i
))
7830 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7832 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7833 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7837 for (i
= 2; i
< 10; i
++)
7838 if (fmask
& (1UL << i
))
7840 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
7842 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7843 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7847 /* Restore the return address from the DSIB. */
7849 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
, -8));
7850 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7851 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7854 if (frame_size
|| eh_ofs
)
7856 sp_adj1
= stack_pointer_rtx
;
7860 sp_adj1
= gen_rtx_REG (DImode
, 23);
7861 emit_move_insn (sp_adj1
,
7862 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
7865 /* If the stack size is large, begin computation into a temporary
7866 register so as not to interfere with a potential fp restore,
7867 which must be consecutive with an SP restore. */
7868 if (frame_size
< 32768
7869 && ! (TARGET_ABI_UNICOSMK
&& current_function_calls_alloca
))
7870 sp_adj2
= GEN_INT (frame_size
);
7871 else if (TARGET_ABI_UNICOSMK
)
7873 sp_adj1
= gen_rtx_REG (DImode
, 23);
7874 FRP (emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
));
7875 sp_adj2
= const0_rtx
;
7877 else if (frame_size
< 0x40007fffL
)
7879 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7881 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
7882 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
7886 sp_adj1
= gen_rtx_REG (DImode
, 23);
7887 FRP (emit_move_insn (sp_adj1
, sp_adj2
));
7889 sp_adj2
= GEN_INT (low
);
7893 rtx tmp
= gen_rtx_REG (DImode
, 23);
7894 FRP (sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
,
7898 /* We can't drop new things to memory this late, afaik,
7899 so build it up by pieces. */
7900 FRP (sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
7901 -(frame_size
< 0)));
7907 /* From now on, things must be in order. So emit blockages. */
7909 /* Restore the frame pointer. */
7910 if (TARGET_ABI_UNICOSMK
)
7912 emit_insn (gen_blockage ());
7913 mem
= gen_rtx_MEM (DImode
,
7914 plus_constant (hard_frame_pointer_rtx
, -16));
7915 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7916 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7918 else if (fp_is_frame_pointer
)
7920 emit_insn (gen_blockage ());
7921 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
7922 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7923 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7925 else if (TARGET_ABI_OPEN_VMS
)
7927 emit_insn (gen_blockage ());
7928 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7929 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7932 /* Restore the stack pointer. */
7933 emit_insn (gen_blockage ());
7934 if (sp_adj2
== const0_rtx
)
7935 FRP (emit_move_insn (stack_pointer_rtx
, sp_adj1
));
7937 FRP (emit_move_insn (stack_pointer_rtx
,
7938 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
)));
7942 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
7944 emit_insn (gen_blockage ());
7945 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7946 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7948 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
7950 /* Decrement the frame pointer if the function does not have a
7953 emit_insn (gen_blockage ());
7954 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7955 hard_frame_pointer_rtx
, constm1_rtx
)));
7960 /* Output the rest of the textual info surrounding the epilogue. */
7963 alpha_end_function (FILE *file
, const char *fnname
, tree decl ATTRIBUTE_UNUSED
)
7965 #if TARGET_ABI_OPEN_VMS
7966 alpha_write_linkage (file
, fnname
, decl
);
7969 /* End the function. */
7970 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
7972 fputs ("\t.end ", file
);
7973 assemble_name (file
, fnname
);
7976 inside_function
= FALSE
;
7978 /* Output jump tables and the static subroutine information block. */
7979 if (TARGET_ABI_UNICOSMK
)
7981 unicosmk_output_ssib (file
, fnname
);
7982 unicosmk_output_deferred_case_vectors (file
);
7987 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7989 In order to avoid the hordes of differences between generated code
7990 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7991 lots of code loading up large constants, generate rtl and emit it
7992 instead of going straight to text.
7994 Not sure why this idea hasn't been explored before... */
7997 alpha_output_mi_thunk_osf (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
7998 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
8001 HOST_WIDE_INT hi
, lo
;
8002 rtx
this, insn
, funexp
;
8004 reset_block_changes ();
8006 /* We always require a valid GP. */
8007 emit_insn (gen_prologue_ldgp ());
8008 emit_note (NOTE_INSN_PROLOGUE_END
);
8010 /* Find the "this" pointer. If the function returns a structure,
8011 the structure return pointer is in $16. */
8012 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
8013 this = gen_rtx_REG (Pmode
, 17);
8015 this = gen_rtx_REG (Pmode
, 16);
8017 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
8018 entire constant for the add. */
8019 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
8020 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8021 if (hi
+ lo
== delta
)
8024 emit_insn (gen_adddi3 (this, this, GEN_INT (hi
)));
8026 emit_insn (gen_adddi3 (this, this, GEN_INT (lo
)));
8030 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
8031 delta
, -(delta
< 0));
8032 emit_insn (gen_adddi3 (this, this, tmp
));
8035 /* Add a delta stored in the vtable at VCALL_OFFSET. */
8040 tmp
= gen_rtx_REG (Pmode
, 0);
8041 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
8043 lo
= ((vcall_offset
& 0xffff) ^ 0x8000) - 0x8000;
8044 hi
= (((vcall_offset
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8045 if (hi
+ lo
== vcall_offset
)
8048 emit_insn (gen_adddi3 (tmp
, tmp
, GEN_INT (hi
)));
8052 tmp2
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 1),
8053 vcall_offset
, -(vcall_offset
< 0));
8054 emit_insn (gen_adddi3 (tmp
, tmp
, tmp2
));
8058 tmp2
= gen_rtx_PLUS (Pmode
, tmp
, GEN_INT (lo
));
8061 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp2
));
8063 emit_insn (gen_adddi3 (this, this, tmp
));
8066 /* Generate a tail call to the target function. */
8067 if (! TREE_USED (function
))
8069 assemble_external (function
);
8070 TREE_USED (function
) = 1;
8072 funexp
= XEXP (DECL_RTL (function
), 0);
8073 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
8074 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
8075 SIBLING_CALL_P (insn
) = 1;
8077 /* Run just enough of rest_of_compilation to get the insns emitted.
8078 There's not really enough bulk here to make other passes such as
8079 instruction scheduling worth while. Note that use_thunk calls
8080 assemble_start_function and assemble_end_function. */
8081 insn
= get_insns ();
8082 insn_locators_initialize ();
8083 shorten_branches (insn
);
8084 final_start_function (insn
, file
, 1);
8085 final (insn
, file
, 1);
8086 final_end_function ();
8088 #endif /* TARGET_ABI_OSF */
8090 /* Debugging support. */
8094 /* Count the number of sdb related labels are generated (to find block
8095 start and end boundaries). */
8097 int sdb_label_count
= 0;
8099 /* Name of the file containing the current function. */
8101 static const char *current_function_file
= "";
8103 /* Offsets to alpha virtual arg/local debugging pointers. */
8105 long alpha_arg_offset
;
8106 long alpha_auto_offset
;
8108 /* Emit a new filename to a stream. */
8111 alpha_output_filename (FILE *stream
, const char *name
)
8113 static int first_time
= TRUE
;
8118 ++num_source_filenames
;
8119 current_function_file
= name
;
8120 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8121 output_quoted_string (stream
, name
);
8122 fprintf (stream
, "\n");
8123 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
8124 fprintf (stream
, "\t#@stabs\n");
8127 else if (write_symbols
== DBX_DEBUG
)
8128 /* dbxout.c will emit an appropriate .stabs directive. */
8131 else if (name
!= current_function_file
8132 && strcmp (name
, current_function_file
) != 0)
8134 if (inside_function
&& ! TARGET_GAS
)
8135 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
8138 ++num_source_filenames
;
8139 current_function_file
= name
;
8140 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8143 output_quoted_string (stream
, name
);
8144 fprintf (stream
, "\n");
8148 /* Structure to show the current status of registers and memory. */
8150 struct shadow_summary
8153 unsigned int i
: 31; /* Mask of int regs */
8154 unsigned int fp
: 31; /* Mask of fp regs */
8155 unsigned int mem
: 1; /* mem == imem | fpmem */
8159 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8160 to the summary structure. SET is nonzero if the insn is setting the
8161 object, otherwise zero. */
8164 summarize_insn (rtx x
, struct shadow_summary
*sum
, int set
)
8166 const char *format_ptr
;
8172 switch (GET_CODE (x
))
8174 /* ??? Note that this case would be incorrect if the Alpha had a
8175 ZERO_EXTRACT in SET_DEST. */
8177 summarize_insn (SET_SRC (x
), sum
, 0);
8178 summarize_insn (SET_DEST (x
), sum
, 1);
8182 summarize_insn (XEXP (x
, 0), sum
, 1);
8186 summarize_insn (XEXP (x
, 0), sum
, 0);
8190 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
8191 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
8195 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
8196 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
8200 summarize_insn (SUBREG_REG (x
), sum
, 0);
8205 int regno
= REGNO (x
);
8206 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
8208 if (regno
== 31 || regno
== 63)
8214 sum
->defd
.i
|= mask
;
8216 sum
->defd
.fp
|= mask
;
8221 sum
->used
.i
|= mask
;
8223 sum
->used
.fp
|= mask
;
8234 /* Find the regs used in memory address computation: */
8235 summarize_insn (XEXP (x
, 0), sum
, 0);
8238 case CONST_INT
: case CONST_DOUBLE
:
8239 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
8240 case SCRATCH
: case ASM_INPUT
:
8243 /* Handle common unary and binary ops for efficiency. */
8244 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
8245 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
8246 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
8247 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8248 case NE
: case EQ
: case GE
: case GT
: case LE
:
8249 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
8250 summarize_insn (XEXP (x
, 0), sum
, 0);
8251 summarize_insn (XEXP (x
, 1), sum
, 0);
8254 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
8255 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
8256 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
8257 case SQRT
: case FFS
:
8258 summarize_insn (XEXP (x
, 0), sum
, 0);
8262 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
8263 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8264 switch (format_ptr
[i
])
8267 summarize_insn (XEXP (x
, i
), sum
, 0);
8271 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8272 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
8284 /* Ensure a sufficient number of `trapb' insns are in the code when
8285 the user requests code with a trap precision of functions or
8288 In naive mode, when the user requests a trap-precision of
8289 "instruction", a trapb is needed after every instruction that may
8290 generate a trap. This ensures that the code is resumption safe but
8293 When optimizations are turned on, we delay issuing a trapb as long
8294 as possible. In this context, a trap shadow is the sequence of
8295 instructions that starts with a (potentially) trap generating
8296 instruction and extends to the next trapb or call_pal instruction
8297 (but GCC never generates call_pal by itself). We can delay (and
8298 therefore sometimes omit) a trapb subject to the following
8301 (a) On entry to the trap shadow, if any Alpha register or memory
8302 location contains a value that is used as an operand value by some
8303 instruction in the trap shadow (live on entry), then no instruction
8304 in the trap shadow may modify the register or memory location.
8306 (b) Within the trap shadow, the computation of the base register
8307 for a memory load or store instruction may not involve using the
8308 result of an instruction that might generate an UNPREDICTABLE
8311 (c) Within the trap shadow, no register may be used more than once
8312 as a destination register. (This is to make life easier for the
8315 (d) The trap shadow may not include any branch instructions. */
8318 alpha_handle_trap_shadows (void)
8320 struct shadow_summary shadow
;
8321 int trap_pending
, exception_nesting
;
8325 exception_nesting
= 0;
8328 shadow
.used
.mem
= 0;
8329 shadow
.defd
= shadow
.used
;
8331 for (i
= get_insns (); i
; i
= NEXT_INSN (i
))
8333 if (GET_CODE (i
) == NOTE
)
8335 switch (NOTE_LINE_NUMBER (i
))
8337 case NOTE_INSN_EH_REGION_BEG
:
8338 exception_nesting
++;
8343 case NOTE_INSN_EH_REGION_END
:
8344 exception_nesting
--;
8349 case NOTE_INSN_EPILOGUE_BEG
:
8350 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
8355 else if (trap_pending
)
8357 if (alpha_tp
== ALPHA_TP_FUNC
)
8359 if (GET_CODE (i
) == JUMP_INSN
8360 && GET_CODE (PATTERN (i
)) == RETURN
)
8363 else if (alpha_tp
== ALPHA_TP_INSN
)
8367 struct shadow_summary sum
;
8372 sum
.defd
= sum
.used
;
8374 switch (GET_CODE (i
))
8377 /* Annoyingly, get_attr_trap will abort on these. */
8378 if (GET_CODE (PATTERN (i
)) == USE
8379 || GET_CODE (PATTERN (i
)) == CLOBBER
)
8382 summarize_insn (PATTERN (i
), &sum
, 0);
8384 if ((sum
.defd
.i
& shadow
.defd
.i
)
8385 || (sum
.defd
.fp
& shadow
.defd
.fp
))
8387 /* (c) would be violated */
8391 /* Combine shadow with summary of current insn: */
8392 shadow
.used
.i
|= sum
.used
.i
;
8393 shadow
.used
.fp
|= sum
.used
.fp
;
8394 shadow
.used
.mem
|= sum
.used
.mem
;
8395 shadow
.defd
.i
|= sum
.defd
.i
;
8396 shadow
.defd
.fp
|= sum
.defd
.fp
;
8397 shadow
.defd
.mem
|= sum
.defd
.mem
;
8399 if ((sum
.defd
.i
& shadow
.used
.i
)
8400 || (sum
.defd
.fp
& shadow
.used
.fp
)
8401 || (sum
.defd
.mem
& shadow
.used
.mem
))
8403 /* (a) would be violated (also takes care of (b)) */
8404 if (get_attr_trap (i
) == TRAP_YES
8405 && ((sum
.defd
.i
& sum
.used
.i
)
8406 || (sum
.defd
.fp
& sum
.used
.fp
)))
8425 n
= emit_insn_before (gen_trapb (), i
);
8426 PUT_MODE (n
, TImode
);
8427 PUT_MODE (i
, TImode
);
8431 shadow
.used
.mem
= 0;
8432 shadow
.defd
= shadow
.used
;
8437 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
8438 && GET_CODE (i
) == INSN
8439 && GET_CODE (PATTERN (i
)) != USE
8440 && GET_CODE (PATTERN (i
)) != CLOBBER
8441 && get_attr_trap (i
) == TRAP_YES
)
8443 if (optimize
&& !trap_pending
)
8444 summarize_insn (PATTERN (i
), &shadow
, 0);
8450 /* Alpha can only issue instruction groups simultaneously if they are
8451 suitably aligned. This is very processor-specific. */
8453 enum alphaev4_pipe
{
8460 enum alphaev5_pipe
{
8471 static enum alphaev4_pipe
8472 alphaev4_insn_pipe (rtx insn
)
8474 if (recog_memoized (insn
) < 0)
8476 if (get_attr_length (insn
) != 4)
8479 switch (get_attr_type (insn
))
8513 static enum alphaev5_pipe
8514 alphaev5_insn_pipe (rtx insn
)
8516 if (recog_memoized (insn
) < 0)
8518 if (get_attr_length (insn
) != 4)
8521 switch (get_attr_type (insn
))
8562 /* IN_USE is a mask of the slots currently filled within the insn group.
8563 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8564 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8566 LEN is, of course, the length of the group in bytes. */
8569 alphaev4_next_group (rtx insn
, int *pin_use
, int *plen
)
8576 || GET_CODE (PATTERN (insn
)) == CLOBBER
8577 || GET_CODE (PATTERN (insn
)) == USE
)
8582 enum alphaev4_pipe pipe
;
8584 pipe
= alphaev4_insn_pipe (insn
);
8588 /* Force complex instructions to start new groups. */
8592 /* If this is a completely unrecognized insn, it's an asm.
8593 We don't know how long it is, so record length as -1 to
8594 signal a needed realignment. */
8595 if (recog_memoized (insn
) < 0)
8598 len
= get_attr_length (insn
);
8602 if (in_use
& EV4_IB0
)
8604 if (in_use
& EV4_IB1
)
8609 in_use
|= EV4_IB0
| EV4_IBX
;
8613 if (in_use
& EV4_IB0
)
8615 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
8623 if (in_use
& EV4_IB1
)
8633 /* Haifa doesn't do well scheduling branches. */
8634 if (GET_CODE (insn
) == JUMP_INSN
)
8638 insn
= next_nonnote_insn (insn
);
8640 if (!insn
|| ! INSN_P (insn
))
8643 /* Let Haifa tell us where it thinks insn group boundaries are. */
8644 if (GET_MODE (insn
) == TImode
)
8647 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8652 insn
= next_nonnote_insn (insn
);
8660 /* IN_USE is a mask of the slots currently filled within the insn group.
8661 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8662 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8664 LEN is, of course, the length of the group in bytes. */
8667 alphaev5_next_group (rtx insn
, int *pin_use
, int *plen
)
8674 || GET_CODE (PATTERN (insn
)) == CLOBBER
8675 || GET_CODE (PATTERN (insn
)) == USE
)
8680 enum alphaev5_pipe pipe
;
8682 pipe
= alphaev5_insn_pipe (insn
);
8686 /* Force complex instructions to start new groups. */
8690 /* If this is a completely unrecognized insn, it's an asm.
8691 We don't know how long it is, so record length as -1 to
8692 signal a needed realignment. */
8693 if (recog_memoized (insn
) < 0)
8696 len
= get_attr_length (insn
);
8699 /* ??? Most of the places below, we would like to abort, as
8700 it would indicate an error either in Haifa, or in the
8701 scheduling description. Unfortunately, Haifa never
8702 schedules the last instruction of the BB, so we don't
8703 have an accurate TI bit to go off. */
8705 if (in_use
& EV5_E0
)
8707 if (in_use
& EV5_E1
)
8712 in_use
|= EV5_E0
| EV5_E01
;
8716 if (in_use
& EV5_E0
)
8718 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
8726 if (in_use
& EV5_E1
)
8732 if (in_use
& EV5_FA
)
8734 if (in_use
& EV5_FM
)
8739 in_use
|= EV5_FA
| EV5_FAM
;
8743 if (in_use
& EV5_FA
)
8749 if (in_use
& EV5_FM
)
8762 /* Haifa doesn't do well scheduling branches. */
8763 /* ??? If this is predicted not-taken, slotting continues, except
8764 that no more IBR, FBR, or JSR insns may be slotted. */
8765 if (GET_CODE (insn
) == JUMP_INSN
)
8769 insn
= next_nonnote_insn (insn
);
8771 if (!insn
|| ! INSN_P (insn
))
8774 /* Let Haifa tell us where it thinks insn group boundaries are. */
8775 if (GET_MODE (insn
) == TImode
)
8778 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8783 insn
= next_nonnote_insn (insn
);
8792 alphaev4_next_nop (int *pin_use
)
8794 int in_use
= *pin_use
;
8797 if (!(in_use
& EV4_IB0
))
8802 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
8807 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
8820 alphaev5_next_nop (int *pin_use
)
8822 int in_use
= *pin_use
;
8825 if (!(in_use
& EV5_E1
))
8830 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
8835 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
8847 /* The instruction group alignment main loop. */
8850 alpha_align_insns (unsigned int max_align
,
8851 rtx (*next_group
) (rtx
, int *, int *),
8852 rtx (*next_nop
) (int *))
8854 /* ALIGN is the known alignment for the insn group. */
8856 /* OFS is the offset of the current insn in the insn group. */
8858 int prev_in_use
, in_use
, len
;
8861 /* Let shorten branches care for assigning alignments to code labels. */
8862 shorten_branches (get_insns ());
8864 if (align_functions
< 4)
8866 else if ((unsigned int) align_functions
< max_align
)
8867 align
= align_functions
;
8871 ofs
= prev_in_use
= 0;
8873 if (GET_CODE (i
) == NOTE
)
8874 i
= next_nonnote_insn (i
);
8878 next
= (*next_group
) (i
, &in_use
, &len
);
8880 /* When we see a label, resync alignment etc. */
8881 if (GET_CODE (i
) == CODE_LABEL
)
8883 unsigned int new_align
= 1 << label_to_alignment (i
);
8885 if (new_align
>= align
)
8887 align
= new_align
< max_align
? new_align
: max_align
;
8891 else if (ofs
& (new_align
-1))
8892 ofs
= (ofs
| (new_align
-1)) + 1;
8897 /* Handle complex instructions special. */
8898 else if (in_use
== 0)
8900 /* Asms will have length < 0. This is a signal that we have
8901 lost alignment knowledge. Assume, however, that the asm
8902 will not mis-align instructions. */
8911 /* If the known alignment is smaller than the recognized insn group,
8912 realign the output. */
8913 else if ((int) align
< len
)
8915 unsigned int new_log_align
= len
> 8 ? 4 : 3;
8918 where
= prev
= prev_nonnote_insn (i
);
8919 if (!where
|| GET_CODE (where
) != CODE_LABEL
)
8922 /* Can't realign between a call and its gp reload. */
8923 if (! (TARGET_EXPLICIT_RELOCS
8924 && prev
&& GET_CODE (prev
) == CALL_INSN
))
8926 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
8927 align
= 1 << new_log_align
;
8932 /* If the group won't fit in the same INT16 as the previous,
8933 we need to add padding to keep the group together. Rather
8934 than simply leaving the insn filling to the assembler, we
8935 can make use of the knowledge of what sorts of instructions
8936 were issued in the previous group to make sure that all of
8937 the added nops are really free. */
8938 else if (ofs
+ len
> (int) align
)
8940 int nop_count
= (align
- ofs
) / 4;
8943 /* Insert nops before labels, branches, and calls to truly merge
8944 the execution of the nops with the previous instruction group. */
8945 where
= prev_nonnote_insn (i
);
8948 if (GET_CODE (where
) == CODE_LABEL
)
8950 rtx where2
= prev_nonnote_insn (where
);
8951 if (where2
&& GET_CODE (where2
) == JUMP_INSN
)
8954 else if (GET_CODE (where
) == INSN
)
8961 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
8962 while (--nop_count
);
8966 ofs
= (ofs
+ len
) & (align
- 1);
8967 prev_in_use
= in_use
;
8972 /* Machine dependent reorg pass. */
8977 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
8978 alpha_handle_trap_shadows ();
8980 /* Due to the number of extra trapb insns, don't bother fixing up
8981 alignment when trap precision is instruction. Moreover, we can
8982 only do our job when sched2 is run. */
8983 if (optimize
&& !optimize_size
8984 && alpha_tp
!= ALPHA_TP_INSN
8985 && flag_schedule_insns_after_reload
)
8987 if (alpha_tune
== PROCESSOR_EV4
)
8988 alpha_align_insns (8, alphaev4_next_group
, alphaev4_next_nop
);
8989 else if (alpha_tune
== PROCESSOR_EV5
)
8990 alpha_align_insns (16, alphaev5_next_group
, alphaev5_next_nop
);
8994 #if !TARGET_ABI_UNICOSMK
9001 alpha_file_start (void)
9003 #ifdef OBJECT_FORMAT_ELF
9004 /* If emitting dwarf2 debug information, we cannot generate a .file
9005 directive to start the file, as it will conflict with dwarf2out
9006 file numbers. So it's only useful when emitting mdebug output. */
9007 targetm
.file_start_file_directive
= (write_symbols
== DBX_DEBUG
);
9010 default_file_start ();
9012 fprintf (asm_out_file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
9015 fputs ("\t.set noreorder\n", asm_out_file
);
9016 fputs ("\t.set volatile\n", asm_out_file
);
9017 if (!TARGET_ABI_OPEN_VMS
)
9018 fputs ("\t.set noat\n", asm_out_file
);
9019 if (TARGET_EXPLICIT_RELOCS
)
9020 fputs ("\t.set nomacro\n", asm_out_file
);
9021 if (TARGET_SUPPORT_ARCH
| TARGET_BWX
| TARGET_MAX
| TARGET_FIX
| TARGET_CIX
)
9025 if (alpha_cpu
== PROCESSOR_EV6
|| TARGET_FIX
|| TARGET_CIX
)
9027 else if (TARGET_MAX
)
9029 else if (TARGET_BWX
)
9031 else if (alpha_cpu
== PROCESSOR_EV5
)
9036 fprintf (asm_out_file
, "\t.arch %s\n", arch
);
9041 #ifdef OBJECT_FORMAT_ELF
9043 /* Switch to the section to which we should output X. The only thing
9044 special we do here is to honor small data. */
9047 alpha_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
9048 unsigned HOST_WIDE_INT align
)
9050 if (TARGET_SMALL_DATA
&& GET_MODE_SIZE (mode
) <= g_switch_value
)
9051 /* ??? Consider using mergeable sdata sections. */
9054 default_elf_select_rtx_section (mode
, x
, align
);
9057 #endif /* OBJECT_FORMAT_ELF */
9059 /* Structure to collect function names for final output in link section. */
9060 /* Note that items marked with GTY can't be ifdef'ed out. */
9062 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
9063 enum reloc_kind
{KIND_LINKAGE
, KIND_CODEADDR
};
9065 struct alpha_links
GTY(())
9069 enum links_kind lkind
;
9070 enum reloc_kind rkind
;
9073 struct alpha_funcs
GTY(())
9076 splay_tree
GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
9080 static GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
9081 splay_tree alpha_links_tree
;
9082 static GTY ((param1_is (tree
), param2_is (struct alpha_funcs
*)))
9083 splay_tree alpha_funcs_tree
;
9085 static GTY(()) int alpha_funcs_num
;
9087 #if TARGET_ABI_OPEN_VMS
9089 /* Return the VMS argument type corresponding to MODE. */
9092 alpha_arg_type (enum machine_mode mode
)
9097 return TARGET_FLOAT_VAX
? FF
: FS
;
9099 return TARGET_FLOAT_VAX
? FD
: FT
;
9105 /* Return an rtx for an integer representing the VMS Argument Information
9109 alpha_arg_info_reg_val (CUMULATIVE_ARGS cum
)
9111 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
9114 for (i
= 0; i
< 6; i
++)
9115 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
9117 return GEN_INT (regval
);
9120 /* Make (or fake) .linkage entry for function call.
9122 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
9124 Return an SYMBOL_REF rtx for the linkage. */
9127 alpha_need_linkage (const char *name
, int is_local
)
9129 splay_tree_node node
;
9130 struct alpha_links
*al
;
9137 struct alpha_funcs
*cfaf
;
9139 if (!alpha_funcs_tree
)
9140 alpha_funcs_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
)
9141 splay_tree_compare_pointers
);
9143 cfaf
= (struct alpha_funcs
*) ggc_alloc (sizeof (struct alpha_funcs
));
9146 cfaf
->num
= ++alpha_funcs_num
;
9148 splay_tree_insert (alpha_funcs_tree
,
9149 (splay_tree_key
) current_function_decl
,
9150 (splay_tree_value
) cfaf
);
9153 if (alpha_links_tree
)
9155 /* Is this name already defined? */
9157 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9160 al
= (struct alpha_links
*) node
->value
;
9163 /* Defined here but external assumed. */
9164 if (al
->lkind
== KIND_EXTERN
)
9165 al
->lkind
= KIND_LOCAL
;
9169 /* Used here but unused assumed. */
9170 if (al
->lkind
== KIND_UNUSED
)
9171 al
->lkind
= KIND_LOCAL
;
9177 alpha_links_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9179 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9180 name
= ggc_strdup (name
);
9182 /* Assume external if no definition. */
9183 al
->lkind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
9185 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9186 get_identifier (name
);
9188 /* Construct a SYMBOL_REF for us to call. */
9190 size_t name_len
= strlen (name
);
9191 char *linksym
= alloca (name_len
+ 6);
9193 memcpy (linksym
+ 1, name
, name_len
);
9194 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
9195 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
9196 ggc_alloc_string (linksym
, name_len
+ 5));
9199 splay_tree_insert (alpha_links_tree
, (splay_tree_key
) name
,
9200 (splay_tree_value
) al
);
9206 alpha_use_linkage (rtx linkage
, tree cfundecl
, int lflag
, int rflag
)
9208 splay_tree_node cfunnode
;
9209 struct alpha_funcs
*cfaf
;
9210 struct alpha_links
*al
;
9211 const char *name
= XSTR (linkage
, 0);
9213 cfaf
= (struct alpha_funcs
*) 0;
9214 al
= (struct alpha_links
*) 0;
9216 cfunnode
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) cfundecl
);
9217 cfaf
= (struct alpha_funcs
*) cfunnode
->value
;
9221 splay_tree_node lnode
;
9223 /* Is this name already defined? */
9225 lnode
= splay_tree_lookup (cfaf
->links
, (splay_tree_key
) name
);
9227 al
= (struct alpha_links
*) lnode
->value
;
9230 cfaf
->links
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9238 splay_tree_node node
= 0;
9239 struct alpha_links
*anl
;
9244 name_len
= strlen (name
);
9246 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9247 al
->num
= cfaf
->num
;
9249 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9252 anl
= (struct alpha_links
*) node
->value
;
9253 al
->lkind
= anl
->lkind
;
9256 sprintf (buf
, "$%d..%s..lk", cfaf
->num
, name
);
9257 buflen
= strlen (buf
);
9258 linksym
= alloca (buflen
+ 1);
9259 memcpy (linksym
, buf
, buflen
+ 1);
9261 al
->linkage
= gen_rtx_SYMBOL_REF
9262 (Pmode
, ggc_alloc_string (linksym
, buflen
+ 1));
9264 splay_tree_insert (cfaf
->links
, (splay_tree_key
) name
,
9265 (splay_tree_value
) al
);
9269 al
->rkind
= KIND_CODEADDR
;
9271 al
->rkind
= KIND_LINKAGE
;
9274 return gen_rtx_MEM (Pmode
, plus_constant (al
->linkage
, 8));
9280 alpha_write_one_linkage (splay_tree_node node
, void *data
)
9282 const char *const name
= (const char *) node
->key
;
9283 struct alpha_links
*link
= (struct alpha_links
*) node
->value
;
9284 FILE *stream
= (FILE *) data
;
9286 fprintf (stream
, "$%d..%s..lk:\n", link
->num
, name
);
9287 if (link
->rkind
== KIND_CODEADDR
)
9289 if (link
->lkind
== KIND_LOCAL
)
9291 /* Local and used */
9292 fprintf (stream
, "\t.quad %s..en\n", name
);
9296 /* External and used, request code address. */
9297 fprintf (stream
, "\t.code_address %s\n", name
);
9302 if (link
->lkind
== KIND_LOCAL
)
9304 /* Local and used, build linkage pair. */
9305 fprintf (stream
, "\t.quad %s..en\n", name
);
9306 fprintf (stream
, "\t.quad %s\n", name
);
9310 /* External and used, request linkage pair. */
9311 fprintf (stream
, "\t.linkage %s\n", name
);
9319 alpha_write_linkage (FILE *stream
, const char *funname
, tree fundecl
)
9321 splay_tree_node node
;
9322 struct alpha_funcs
*func
;
9325 fprintf (stream
, "\t.align 3\n");
9326 node
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) fundecl
);
9327 func
= (struct alpha_funcs
*) node
->value
;
9329 fputs ("\t.name ", stream
);
9330 assemble_name (stream
, funname
);
9331 fputs ("..na\n", stream
);
9332 ASM_OUTPUT_LABEL (stream
, funname
);
9333 fprintf (stream
, "\t.pdesc ");
9334 assemble_name (stream
, funname
);
9335 fprintf (stream
, "..en,%s\n",
9336 alpha_procedure_type
== PT_STACK
? "stack"
9337 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
9341 splay_tree_foreach (func
->links
, alpha_write_one_linkage
, stream
);
9342 /* splay_tree_delete (func->links); */
9346 /* Given a decl, a section name, and whether the decl initializer
9347 has relocs, choose attributes for the section. */
9349 #define SECTION_VMS_OVERLAY SECTION_FORGET
9350 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9351 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9354 vms_section_type_flags (tree decl
, const char *name
, int reloc
)
9356 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9358 if (decl
&& DECL_ATTRIBUTES (decl
)
9359 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
9360 flags
|= SECTION_VMS_OVERLAY
;
9361 if (decl
&& DECL_ATTRIBUTES (decl
)
9362 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
9363 flags
|= SECTION_VMS_GLOBAL
;
9364 if (decl
&& DECL_ATTRIBUTES (decl
)
9365 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
9366 flags
|= SECTION_VMS_INITIALIZE
;
9371 /* Switch to an arbitrary section NAME with attributes as specified
9372 by FLAGS. ALIGN specifies any known alignment requirements for
9373 the section; 0 if the default should be used. */
9376 vms_asm_named_section (const char *name
, unsigned int flags
,
9377 tree decl ATTRIBUTE_UNUSED
)
9379 fputc ('\n', asm_out_file
);
9380 fprintf (asm_out_file
, ".section\t%s", name
);
9382 if (flags
& SECTION_VMS_OVERLAY
)
9383 fprintf (asm_out_file
, ",OVR");
9384 if (flags
& SECTION_VMS_GLOBAL
)
9385 fprintf (asm_out_file
, ",GBL");
9386 if (flags
& SECTION_VMS_INITIALIZE
)
9387 fprintf (asm_out_file
, ",NOMOD");
9388 if (flags
& SECTION_DEBUG
)
9389 fprintf (asm_out_file
, ",NOWRT");
9391 fputc ('\n', asm_out_file
);
9394 /* Record an element in the table of global constructors. SYMBOL is
9395 a SYMBOL_REF of the function to be called; PRIORITY is a number
9396 between 0 and MAX_INIT_PRIORITY.
9398 Differs from default_ctors_section_asm_out_constructor in that the
9399 width of the .ctors entry is always 64 bits, rather than the 32 bits
9400 used by a normal pointer. */
9403 vms_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9406 assemble_align (BITS_PER_WORD
);
9407 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9411 vms_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9414 assemble_align (BITS_PER_WORD
);
9415 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9420 alpha_need_linkage (const char *name ATTRIBUTE_UNUSED
,
9421 int is_local ATTRIBUTE_UNUSED
)
9427 alpha_use_linkage (rtx linkage ATTRIBUTE_UNUSED
,
9428 tree cfundecl ATTRIBUTE_UNUSED
,
9429 int lflag ATTRIBUTE_UNUSED
,
9430 int rflag ATTRIBUTE_UNUSED
)
9435 #endif /* TARGET_ABI_OPEN_VMS */
9437 #if TARGET_ABI_UNICOSMK
9439 /* This evaluates to true if we do not know how to pass TYPE solely in
9440 registers. This is the case for all arguments that do not fit in two
9444 unicosmk_must_pass_in_stack (enum machine_mode mode
, tree type
)
9449 if (TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
9451 if (TREE_ADDRESSABLE (type
))
9454 return ALPHA_ARG_SIZE (mode
, type
, 0) > 2;
9457 /* Define the offset between two registers, one to be eliminated, and the
9458 other its replacement, at the start of a routine. */
9461 unicosmk_initial_elimination_offset (int from
, int to
)
9465 fixed_size
= alpha_sa_size();
9466 if (fixed_size
!= 0)
9469 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9471 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9473 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9474 return (ALPHA_ROUND (current_function_outgoing_args_size
)
9475 + ALPHA_ROUND (get_frame_size()));
9476 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9477 return (ALPHA_ROUND (fixed_size
)
9478 + ALPHA_ROUND (get_frame_size()
9479 + current_function_outgoing_args_size
));
9484 /* Output the module name for .ident and .end directives. We have to strip
9485 directories and add make sure that the module name starts with a letter
9489 unicosmk_output_module_name (FILE *file
)
9491 const char *name
= lbasename (main_input_filename
);
9492 unsigned len
= strlen (name
);
9493 char *clean_name
= alloca (len
+ 2);
9494 char *ptr
= clean_name
;
9496 /* CAM only accepts module names that start with a letter or '$'. We
9497 prefix the module name with a '$' if necessary. */
9499 if (!ISALPHA (*name
))
9501 memcpy (ptr
, name
, len
+ 1);
9502 clean_symbol_name (clean_name
);
9503 fputs (clean_name
, file
);
9506 /* Output the definition of a common variable. */
9509 unicosmk_output_common (FILE *file
, const char *name
, int size
, int align
)
9512 printf ("T3E__: common %s\n", name
);
9515 fputs("\t.endp\n\n\t.psect ", file
);
9516 assemble_name(file
, name
);
9517 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
9518 fprintf(file
, "\t.byte\t0:%d\n", size
);
9520 /* Mark the symbol as defined in this module. */
9521 name_tree
= get_identifier (name
);
9522 TREE_ASM_WRITTEN (name_tree
) = 1;
9525 #define SECTION_PUBLIC SECTION_MACH_DEP
9526 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9527 static int current_section_align
;
9530 unicosmk_section_type_flags (tree decl
, const char *name
,
9531 int reloc ATTRIBUTE_UNUSED
)
9533 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9538 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9540 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9541 if (align_functions_log
> current_section_align
)
9542 current_section_align
= align_functions_log
;
9544 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
9545 flags
|= SECTION_MAIN
;
9548 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
9550 if (TREE_PUBLIC (decl
))
9551 flags
|= SECTION_PUBLIC
;
9556 /* Generate a section name for decl and associate it with the
9560 unicosmk_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
9568 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
9569 name
= default_strip_name_encoding (name
);
9570 len
= strlen (name
);
9572 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9576 /* It is essential that we prefix the section name here because
9577 otherwise the section names generated for constructors and
9578 destructors confuse collect2. */
9580 string
= alloca (len
+ 6);
9581 sprintf (string
, "code@%s", name
);
9582 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9584 else if (TREE_PUBLIC (decl
))
9585 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
9590 string
= alloca (len
+ 6);
9591 sprintf (string
, "data@%s", name
);
9592 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9596 /* Switch to an arbitrary section NAME with attributes as specified
9597 by FLAGS. ALIGN specifies any known alignment requirements for
9598 the section; 0 if the default should be used. */
9601 unicosmk_asm_named_section (const char *name
, unsigned int flags
,
9602 tree decl ATTRIBUTE_UNUSED
)
9606 /* Close the previous section. */
9608 fputs ("\t.endp\n\n", asm_out_file
);
9610 /* Find out what kind of section we are opening. */
9612 if (flags
& SECTION_MAIN
)
9613 fputs ("\t.start\tmain\n", asm_out_file
);
9615 if (flags
& SECTION_CODE
)
9617 else if (flags
& SECTION_PUBLIC
)
9622 if (current_section_align
!= 0)
9623 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
9624 current_section_align
, kind
);
9626 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
9630 unicosmk_insert_attributes (tree decl
, tree
*attr_ptr ATTRIBUTE_UNUSED
)
9633 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
9634 unicosmk_unique_section (decl
, 0);
9637 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9638 in code sections because .align fill unused space with zeroes. */
9641 unicosmk_output_align (FILE *file
, int align
)
9643 if (inside_function
)
9644 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
9646 fprintf (file
, "\t.align\t%d\n", align
);
9649 /* Add a case vector to the current function's list of deferred case
9650 vectors. Case vectors have to be put into a separate section because CAM
9651 does not allow data definitions in code sections. */
9654 unicosmk_defer_case_vector (rtx lab
, rtx vec
)
9656 struct machine_function
*machine
= cfun
->machine
;
9658 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9659 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
9660 machine
->addr_list
);
9663 /* Output a case vector. */
9666 unicosmk_output_addr_vec (FILE *file
, rtx vec
)
9668 rtx lab
= XEXP (vec
, 0);
9669 rtx body
= XEXP (vec
, 1);
9670 int vlen
= XVECLEN (body
, 0);
9673 (*targetm
.asm_out
.internal_label
) (file
, "L", CODE_LABEL_NUMBER (lab
));
9675 for (idx
= 0; idx
< vlen
; idx
++)
9677 ASM_OUTPUT_ADDR_VEC_ELT
9678 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9682 /* Output current function's deferred case vectors. */
9685 unicosmk_output_deferred_case_vectors (FILE *file
)
9687 struct machine_function
*machine
= cfun
->machine
;
9690 if (machine
->addr_list
== NULL_RTX
)
9694 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
9695 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
9698 /* Generate the name of the SSIB section for the current function. */
9700 #define SSIB_PREFIX "__SSIB_"
9701 #define SSIB_PREFIX_LEN 7
9704 unicosmk_ssib_name (void)
9706 /* This is ok since CAM won't be able to deal with names longer than that
9709 static char name
[256];
9715 x
= DECL_RTL (cfun
->decl
);
9716 if (GET_CODE (x
) != MEM
)
9719 if (GET_CODE (x
) != SYMBOL_REF
)
9721 fnname
= XSTR (x
, 0);
9723 len
= strlen (fnname
);
9724 if (len
+ SSIB_PREFIX_LEN
> 255)
9725 len
= 255 - SSIB_PREFIX_LEN
;
9727 strcpy (name
, SSIB_PREFIX
);
9728 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
9729 name
[len
+ SSIB_PREFIX_LEN
] = 0;
9734 /* Set up the dynamic subprogram information block (DSIB) and update the
9735 frame pointer register ($15) for subroutines which have a frame. If the
9736 subroutine doesn't have a frame, simply increment $15. */
9739 unicosmk_gen_dsib (unsigned long *imaskP
)
9741 if (alpha_procedure_type
== PT_STACK
)
9743 const char *ssib_name
;
9746 /* Allocate 64 bytes for the DSIB. */
9748 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9750 emit_insn (gen_blockage ());
9752 /* Save the return address. */
9754 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
9755 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9756 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
9757 (*imaskP
) &= ~(1UL << REG_RA
);
9759 /* Save the old frame pointer. */
9761 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
9762 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9763 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
9764 (*imaskP
) &= ~(1UL << HARD_FRAME_POINTER_REGNUM
);
9766 emit_insn (gen_blockage ());
9768 /* Store the SSIB pointer. */
9770 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
9771 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
9772 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9774 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
9775 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
9776 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
9778 /* Save the CIW index. */
9780 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
9781 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9782 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
9784 emit_insn (gen_blockage ());
9786 /* Set the new frame pointer. */
9788 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9789 stack_pointer_rtx
, GEN_INT (64))));
9794 /* Increment the frame pointer register to indicate that we do not
9797 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9798 hard_frame_pointer_rtx
, const1_rtx
)));
9802 /* Output the static subroutine information block for the current
9806 unicosmk_output_ssib (FILE *file
, const char *fnname
)
9812 struct machine_function
*machine
= cfun
->machine
;
9815 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
9816 unicosmk_ssib_name ());
9818 /* Some required stuff and the function name length. */
9820 len
= strlen (fnname
);
9821 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
9824 ??? We don't do that yet. */
9826 fputs ("\t.quad\t0\n", file
);
9828 /* Function address. */
9830 fputs ("\t.quad\t", file
);
9831 assemble_name (file
, fnname
);
9834 fputs ("\t.quad\t0\n", file
);
9835 fputs ("\t.quad\t0\n", file
);
9838 ??? We do it the same way Cray CC does it but this could be
9841 for( i
= 0; i
< len
; i
++ )
9842 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
9843 if( (len
% 8) == 0 )
9844 fputs ("\t.quad\t0\n", file
);
9846 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
9848 /* All call information words used in the function. */
9850 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
9853 #if HOST_BITS_PER_WIDE_INT == 32
9854 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX
"\n",
9855 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
9857 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n", INTVAL (ciw
));
9862 /* Add a call information word (CIW) to the list of the current function's
9863 CIWs and return its index.
9865 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9868 unicosmk_add_call_info_word (rtx x
)
9871 struct machine_function
*machine
= cfun
->machine
;
9873 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
9874 if (machine
->first_ciw
== NULL_RTX
)
9875 machine
->first_ciw
= node
;
9877 XEXP (machine
->last_ciw
, 1) = node
;
9879 machine
->last_ciw
= node
;
9880 ++machine
->ciw_count
;
9882 return GEN_INT (machine
->ciw_count
9883 + strlen (current_function_name ())/8 + 5);
9886 static char unicosmk_section_buf
[100];
9889 unicosmk_text_section (void)
9891 static int count
= 0;
9892 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
9894 return unicosmk_section_buf
;
9898 unicosmk_data_section (void)
9900 static int count
= 1;
9901 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
9903 return unicosmk_section_buf
;
9906 /* The Cray assembler doesn't accept extern declarations for symbols which
9907 are defined in the same file. We have to keep track of all global
9908 symbols which are referenced and/or defined in a source file and output
9909 extern declarations for those which are referenced but not defined at
9912 /* List of identifiers for which an extern declaration might have to be
9914 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9916 struct unicosmk_extern_list
9918 struct unicosmk_extern_list
*next
;
9922 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
9924 /* Output extern declarations which are required for every asm file. */
9927 unicosmk_output_default_externs (FILE *file
)
9929 static const char *const externs
[] =
9930 { "__T3E_MISMATCH" };
9935 n
= ARRAY_SIZE (externs
);
9937 for (i
= 0; i
< n
; i
++)
9938 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
9941 /* Output extern declarations for global symbols which are have been
9942 referenced but not defined. */
9945 unicosmk_output_externs (FILE *file
)
9947 struct unicosmk_extern_list
*p
;
9948 const char *real_name
;
9952 len
= strlen (user_label_prefix
);
9953 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
9955 /* We have to strip the encoding and possibly remove user_label_prefix
9956 from the identifier in order to handle -fleading-underscore and
9957 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9958 real_name
= default_strip_name_encoding (p
->name
);
9959 if (len
&& p
->name
[0] == '*'
9960 && !memcmp (real_name
, user_label_prefix
, len
))
9963 name_tree
= get_identifier (real_name
);
9964 if (! TREE_ASM_WRITTEN (name_tree
))
9966 TREE_ASM_WRITTEN (name_tree
) = 1;
9967 fputs ("\t.extern\t", file
);
9968 assemble_name (file
, p
->name
);
9974 /* Record an extern. */
9977 unicosmk_add_extern (const char *name
)
9979 struct unicosmk_extern_list
*p
;
9981 p
= (struct unicosmk_extern_list
*)
9982 xmalloc (sizeof (struct unicosmk_extern_list
));
9983 p
->next
= unicosmk_extern_head
;
9985 unicosmk_extern_head
= p
;
9988 /* The Cray assembler generates incorrect code if identifiers which
9989 conflict with register names are used as instruction operands. We have
9990 to replace such identifiers with DEX expressions. */
9992 /* Structure to collect identifiers which have been replaced by DEX
9994 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9996 struct unicosmk_dex
{
9997 struct unicosmk_dex
*next
;
10001 /* List of identifiers which have been replaced by DEX expressions. The DEX
10002 number is determined by the position in the list. */
10004 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
10006 /* The number of elements in the DEX list. */
10008 static int unicosmk_dex_count
= 0;
10010 /* Check if NAME must be replaced by a DEX expression. */
10013 unicosmk_special_name (const char *name
)
10015 if (name
[0] == '*')
10018 if (name
[0] == '$')
10021 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
10026 case '1': case '2':
10027 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
10030 return (name
[2] == '\0'
10031 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
10034 return (ISDIGIT (name
[1]) && name
[2] == '\0');
10038 /* Return the DEX number if X must be replaced by a DEX expression and 0
10042 unicosmk_need_dex (rtx x
)
10044 struct unicosmk_dex
*dex
;
10048 if (GET_CODE (x
) != SYMBOL_REF
)
10052 if (! unicosmk_special_name (name
))
10055 i
= unicosmk_dex_count
;
10056 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10058 if (! strcmp (name
, dex
->name
))
10063 dex
= (struct unicosmk_dex
*) xmalloc (sizeof (struct unicosmk_dex
));
10065 dex
->next
= unicosmk_dex_list
;
10066 unicosmk_dex_list
= dex
;
10068 ++unicosmk_dex_count
;
10069 return unicosmk_dex_count
;
10072 /* Output the DEX definitions for this file. */
10075 unicosmk_output_dex (FILE *file
)
10077 struct unicosmk_dex
*dex
;
10080 if (unicosmk_dex_list
== NULL
)
10083 fprintf (file
, "\t.dexstart\n");
10085 i
= unicosmk_dex_count
;
10086 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10088 fprintf (file
, "\tDEX (%d) = ", i
);
10089 assemble_name (file
, dex
->name
);
10094 fprintf (file
, "\t.dexend\n");
10097 /* Output text that to appear at the beginning of an assembler file. */
10100 unicosmk_file_start (void)
10104 fputs ("\t.ident\t", asm_out_file
);
10105 unicosmk_output_module_name (asm_out_file
);
10106 fputs ("\n\n", asm_out_file
);
10108 /* The Unicos/Mk assembler uses different register names. Instead of trying
10109 to support them, we simply use micro definitions. */
10111 /* CAM has different register names: rN for the integer register N and fN
10112 for the floating-point register N. Instead of trying to use these in
10113 alpha.md, we define the symbols $N and $fN to refer to the appropriate
10116 for (i
= 0; i
< 32; ++i
)
10117 fprintf (asm_out_file
, "$%d <- r%d\n", i
, i
);
10119 for (i
= 0; i
< 32; ++i
)
10120 fprintf (asm_out_file
, "$f%d <- f%d\n", i
, i
);
10122 putc ('\n', asm_out_file
);
10124 /* The .align directive fill unused space with zeroes which does not work
10125 in code sections. We define the macro 'gcc@code@align' which uses nops
10126 instead. Note that it assumes that code sections always have the
10127 biggest possible alignment since . refers to the current offset from
10128 the beginning of the section. */
10130 fputs ("\t.macro gcc@code@align n\n", asm_out_file
);
10131 fputs ("gcc@n@bytes = 1 << n\n", asm_out_file
);
10132 fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file
);
10133 fputs ("\t.if ne, gcc@here, 0\n", asm_out_file
);
10134 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file
);
10135 fputs ("\tbis r31,r31,r31\n", asm_out_file
);
10136 fputs ("\t.endr\n", asm_out_file
);
10137 fputs ("\t.endif\n", asm_out_file
);
10138 fputs ("\t.endm gcc@code@align\n\n", asm_out_file
);
10140 /* Output extern declarations which should always be visible. */
10141 unicosmk_output_default_externs (asm_out_file
);
10143 /* Open a dummy section. We always need to be inside a section for the
10144 section-switching code to work correctly.
10145 ??? This should be a module id or something like that. I still have to
10146 figure out what the rules for those are. */
10147 fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file
);
10150 /* Output text to appear at the end of an assembler file. This includes all
10151 pending extern declarations and DEX expressions. */
10154 unicosmk_file_end (void)
10156 fputs ("\t.endp\n\n", asm_out_file
);
10158 /* Output all pending externs. */
10160 unicosmk_output_externs (asm_out_file
);
10162 /* Output dex definitions used for functions whose names conflict with
10165 unicosmk_output_dex (asm_out_file
);
10167 fputs ("\t.end\t", asm_out_file
);
10168 unicosmk_output_module_name (asm_out_file
);
10169 putc ('\n', asm_out_file
);
10175 unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED
)
10179 unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED
)
10183 unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED
,
10184 const char * fnname ATTRIBUTE_UNUSED
)
10188 unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED
)
10194 unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED
)
10199 #endif /* TARGET_ABI_UNICOSMK */
10202 alpha_init_libfuncs (void)
10204 if (TARGET_ABI_UNICOSMK
)
10206 /* Prevent gcc from generating calls to __divsi3. */
10207 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10208 set_optab_libfunc (udiv_optab
, SImode
, 0);
10210 /* Use the functions provided by the system library
10211 for DImode integer division. */
10212 set_optab_libfunc (sdiv_optab
, DImode
, "$sldiv");
10213 set_optab_libfunc (udiv_optab
, DImode
, "$uldiv");
10215 else if (TARGET_ABI_OPEN_VMS
)
10217 /* Use the VMS runtime library functions for division and
10219 set_optab_libfunc (sdiv_optab
, SImode
, "OTS$DIV_I");
10220 set_optab_libfunc (sdiv_optab
, DImode
, "OTS$DIV_L");
10221 set_optab_libfunc (udiv_optab
, SImode
, "OTS$DIV_UI");
10222 set_optab_libfunc (udiv_optab
, DImode
, "OTS$DIV_UL");
10223 set_optab_libfunc (smod_optab
, SImode
, "OTS$REM_I");
10224 set_optab_libfunc (smod_optab
, DImode
, "OTS$REM_L");
10225 set_optab_libfunc (umod_optab
, SImode
, "OTS$REM_UI");
10226 set_optab_libfunc (umod_optab
, DImode
, "OTS$REM_UL");
10231 /* Initialize the GCC target structure. */
10232 #if TARGET_ABI_OPEN_VMS
10233 # undef TARGET_ATTRIBUTE_TABLE
10234 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
10235 # undef TARGET_SECTION_TYPE_FLAGS
10236 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
10239 #undef TARGET_IN_SMALL_DATA_P
10240 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
10242 #if TARGET_ABI_UNICOSMK
10243 # undef TARGET_INSERT_ATTRIBUTES
10244 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
10245 # undef TARGET_SECTION_TYPE_FLAGS
10246 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
10247 # undef TARGET_ASM_UNIQUE_SECTION
10248 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
10249 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
10250 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
10251 # undef TARGET_ASM_GLOBALIZE_LABEL
10252 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
10253 # undef TARGET_MUST_PASS_IN_STACK
10254 # define TARGET_MUST_PASS_IN_STACK unicosmk_must_pass_in_stack
10257 #undef TARGET_ASM_ALIGNED_HI_OP
10258 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10259 #undef TARGET_ASM_ALIGNED_DI_OP
10260 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10262 /* Default unaligned ops are provided for ELF systems. To get unaligned
10263 data for non-ELF systems, we have to turn off auto alignment. */
10264 #ifndef OBJECT_FORMAT_ELF
10265 #undef TARGET_ASM_UNALIGNED_HI_OP
10266 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
10267 #undef TARGET_ASM_UNALIGNED_SI_OP
10268 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
10269 #undef TARGET_ASM_UNALIGNED_DI_OP
10270 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
10273 #ifdef OBJECT_FORMAT_ELF
10274 #undef TARGET_ASM_SELECT_RTX_SECTION
10275 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
10278 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
10279 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
10281 #undef TARGET_INIT_LIBFUNCS
10282 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
10284 #if TARGET_ABI_UNICOSMK
10285 #undef TARGET_ASM_FILE_START
10286 #define TARGET_ASM_FILE_START unicosmk_file_start
10287 #undef TARGET_ASM_FILE_END
10288 #define TARGET_ASM_FILE_END unicosmk_file_end
10290 #undef TARGET_ASM_FILE_START
10291 #define TARGET_ASM_FILE_START alpha_file_start
10292 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
10293 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
10296 #undef TARGET_SCHED_ADJUST_COST
10297 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
10298 #undef TARGET_SCHED_ISSUE_RATE
10299 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
10300 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10301 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
10302 alpha_multipass_dfa_lookahead
10304 #undef TARGET_HAVE_TLS
10305 #define TARGET_HAVE_TLS HAVE_AS_TLS
10307 #undef TARGET_INIT_BUILTINS
10308 #define TARGET_INIT_BUILTINS alpha_init_builtins
10309 #undef TARGET_EXPAND_BUILTIN
10310 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
10311 #undef TARGET_FOLD_BUILTIN
10312 #define TARGET_FOLD_BUILTIN alpha_fold_builtin
10314 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10315 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
10316 #undef TARGET_CANNOT_COPY_INSN_P
10317 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
10318 #undef TARGET_CANNOT_FORCE_CONST_MEM
10319 #define TARGET_CANNOT_FORCE_CONST_MEM alpha_cannot_force_const_mem
10322 #undef TARGET_ASM_OUTPUT_MI_THUNK
10323 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
10324 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10325 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
10326 #undef TARGET_STDARG_OPTIMIZE_HOOK
10327 #define TARGET_STDARG_OPTIMIZE_HOOK alpha_stdarg_optimize_hook
10330 #undef TARGET_RTX_COSTS
10331 #define TARGET_RTX_COSTS alpha_rtx_costs
10332 #undef TARGET_ADDRESS_COST
10333 #define TARGET_ADDRESS_COST hook_int_rtx_0
10335 #undef TARGET_MACHINE_DEPENDENT_REORG
10336 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
10338 #undef TARGET_PROMOTE_FUNCTION_ARGS
10339 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
10340 #undef TARGET_PROMOTE_FUNCTION_RETURN
10341 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
10342 #undef TARGET_PROMOTE_PROTOTYPES
10343 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_false
10344 #undef TARGET_RETURN_IN_MEMORY
10345 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
10346 #undef TARGET_PASS_BY_REFERENCE
10347 #define TARGET_PASS_BY_REFERENCE alpha_pass_by_reference
10348 #undef TARGET_SETUP_INCOMING_VARARGS
10349 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
10350 #undef TARGET_STRICT_ARGUMENT_NAMING
10351 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
10352 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
10353 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
10354 #undef TARGET_SPLIT_COMPLEX_ARG
10355 #define TARGET_SPLIT_COMPLEX_ARG alpha_split_complex_arg
10356 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10357 #define TARGET_GIMPLIFY_VA_ARG_EXPR alpha_gimplify_va_arg
10358 #undef TARGET_ARG_PARTIAL_BYTES
10359 #define TARGET_ARG_PARTIAL_BYTES alpha_arg_partial_bytes
10361 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10362 #define TARGET_SCALAR_MODE_SUPPORTED_P alpha_scalar_mode_supported_p
10363 #undef TARGET_VECTOR_MODE_SUPPORTED_P
10364 #define TARGET_VECTOR_MODE_SUPPORTED_P alpha_vector_mode_supported_p
10366 #undef TARGET_BUILD_BUILTIN_VA_LIST
10367 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
10369 /* The Alpha architecture does not require sequential consistency. See
10370 http://www.cs.umd.edu/~pugh/java/memoryModel/AlphaReordering.html
10371 for an example of how it can be violated in practice. */
10372 #undef TARGET_RELAXED_ORDERING
10373 #define TARGET_RELAXED_ORDERING true
10375 #undef TARGET_DEFAULT_TARGET_FLAGS
10376 #define TARGET_DEFAULT_TARGET_FLAGS \
10377 (TARGET_DEFAULT | TARGET_CPU_DEFAULT | TARGET_DEFAULT_EXPLICIT_RELOCS)
10378 #undef TARGET_HANDLE_OPTION
10379 #define TARGET_HANDLE_OPTION alpha_handle_option
10381 struct gcc_target targetm
= TARGET_INITIALIZER
;
10384 #include "gt-alpha.h"