1 ;;- Machine description for Renesas / SuperH SH.
2 ;; Copyright (C) 1993-2017 Free Software Foundation, Inc.
3 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
4 ;; Improved by Jim Wilson (wilson@cygnus.com).
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
23 ;; ??? Should prepend a * to all pattern names which are not used.
24 ;; This will make the compiler smaller, and rebuilds after changes faster.
26 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
27 ;; sequences. Especially the sequences for arithmetic right shifts.
29 ;; ??? Should check all DImode patterns for consistency and usefulness.
31 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
32 ;; way to generate them.
34 ;; BSR is not generated by the compiler proper, but when relaxing, it
35 ;; generates .uses pseudo-ops that allow linker relaxation to create
36 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
38 ;; Special constraints for SH machine description:
45 ;; Special formats used for outputting SH instructions:
47 ;; %. -- print a .s if insn needs delay slot
48 ;; %@ -- print rte/rts if is/isn't an interrupt function
49 ;; %# -- output a nop if there is nothing to put in the delay slot
50 ;; %O -- print a constant without the #
51 ;; %R -- print the lsw reg of a double
52 ;; %S -- print the msw reg of a double
53 ;; %T -- print next word of a double REG or MEM
55 ;; Special predicates:
57 ;; arith_operand -- operand is valid source for arithmetic op
58 ;; arith_reg_operand -- operand is valid register for arithmetic op
59 ;; general_movdst_operand -- operand is valid move destination
60 ;; general_movsrc_operand -- operand is valid move source
61 ;; logical_operand -- operand is valid source for logical op
63 ;; -------------------------------------------------------------------------
65 ;; -------------------------------------------------------------------------
79 ;; Virtual FPSCR - bits that are used by FP ops.
82 ;; Virtual FPSCR - bits that are updated by FP ops.
111 (FPSCR_PR 524288) ;; 1 << 19
112 (FPSCR_SZ 1048576) ;; 1 << 20
113 (FPSCR_FR 2097152) ;; 1 << 21
116 (define_c_enum "unspec" [
117 ;; These are used with unspec.
146 ;; (unspec [TARGET ANCHOR] UNSPEC_SYMOFF) == TARGET - ANCHOR.
148 ;; (unspec [OFFSET ANCHOR] UNSPEC_PCREL_SYMOFF) == OFFSET - (ANCHOR - .).
152 UNSPEC_GOTOFFFUNCDESC
154 UNSPEC_BUILTIN_STRLEN
157 (define_c_enum "unspecv" [
158 ;; These are used with unspec_volatile.
175 ;; -------------------------------------------------------------------------
177 ;; -------------------------------------------------------------------------
182 "sh1,sh2,sh2e,sh2a,sh3,sh3e,sh4,sh4a"
183 (const (symbol_ref "sh_cpu_attr")))
185 (define_attr "endian" "big,little"
186 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
187 (const_string "little") (const_string "big"))))
189 ;; Indicate if the default fpu mode is single precision.
190 (define_attr "fpu_single" "yes,no"
191 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
192 (const_string "yes") (const_string "no"))))
194 (define_attr "fmovd" "yes,no"
195 (const (if_then_else (symbol_ref "TARGET_FMOVD")
196 (const_string "yes") (const_string "no"))))
198 (define_attr "pipe_model" "sh1,sh4"
200 (cond [(symbol_ref "TARGET_SUPERSCALAR") (const_string "sh4")]
201 (const_string "sh1"))))
203 ;; cbranch conditional branch instructions
204 ;; jump unconditional jumps
205 ;; arith ordinary arithmetic
206 ;; arith3 a compound insn that behaves similarly to a sequence of
207 ;; three insns of type arith
208 ;; arith3b like above, but might end with a redirected branch
210 ;; load_si Likewise, SImode variant for general register.
211 ;; fload Likewise, but load to fp register.
213 ;; fstore floating point register to memory
214 ;; move general purpose register to register
215 ;; movi8 8-bit immediate to general purpose register
216 ;; mt_group other sh4 mt instructions
217 ;; fmove register to register, floating point
218 ;; smpy word precision integer multiply
219 ;; dmpy longword or doublelongword precision integer multiply
221 ;; pload load of pr reg, which can't be put into delay slot of rts
222 ;; prset copy register to pr reg, ditto
223 ;; pstore store of pr reg, which can't be put into delay slot of jsr
224 ;; prget copy pr to register, ditto
225 ;; pcload pc relative load of constant value
226 ;; pcfload Likewise, but load to fp register.
227 ;; pcload_si Likewise, SImode variant for general register.
228 ;; rte return from exception
229 ;; sfunc special function call with known used registers
230 ;; call function call
232 ;; fpscr_toggle toggle a bit in the fpscr
233 ;; fdiv floating point divide (or square root)
234 ;; gp_fpul move from general purpose register to fpul
235 ;; fpul_gp move from fpul to general purpose register
236 ;; mac_gp move from mac[lh] to general purpose register
237 ;; gp_mac move from general purpose register to mac[lh]
238 ;; mac_mem move from mac[lh] to memory
239 ;; mem_mac move from memory to mac[lh]
240 ;; dfp_arith,dfp_mul, fp_cmp,dfp_cmp,dfp_conv
241 ;; ftrc_s fix_truncsfsi2_i4
242 ;; dfdiv double precision floating point divide (or square root)
243 ;; cwb ic_invalidate_line_i
244 ;; movua SH4a unaligned load
245 ;; fsrra square root reciprocal approximate
246 ;; fsca sine and cosine approximate
247 ;; tls_load load TLS related address
248 ;; nil no-op move, will be deleted.
251 "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,
252 fload,store,fstore,move,movi8,fmove,smpy,dmpy,return,pload,prset,pstore,
253 prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fpscr_toggle,fdiv,ftrc_s,
254 dfp_arith,dfp_mul,fp_cmp,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,
255 gp_mac,mac_mem,mem_mac,mem_fpscr,gp_fpscr,cwb,movua,fsrra,fsca,tls_load,
257 (const_string "other"))
259 ;; We define a new attribute namely "insn_class".We use
260 ;; this for the DFA based pipeline description.
262 ;; mt_group SH4 "mt" group instructions.
264 ;; ex_group SH4 "ex" group instructions.
266 ;; ls_group SH4 "ls" group instructions.
268 (define_attr "insn_class"
269 "mt_group,ex_group,ls_group,br_group,fe_group,co_group,none"
270 (cond [(eq_attr "type" "move,mt_group") (const_string "mt_group")
271 (eq_attr "type" "movi8,arith,dyn_shift") (const_string "ex_group")
272 (eq_attr "type" "fmove,load,pcload,load_si,pcload_si,fload,pcfload,
273 store,fstore,gp_fpul,fpul_gp") (const_string "ls_group")
274 (eq_attr "type" "cbranch,jump") (const_string "br_group")
275 (eq_attr "type" "fp,fp_cmp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
276 (const_string "fe_group")
277 (eq_attr "type" "jump_ind,smpy,dmpy,mac_gp,return,pload,prset,pstore,
278 prget,rte,sfunc,call,dfp_cmp,mem_fpscr,gp_fpscr,cwb,
279 gp_mac,mac_mem,mem_mac") (const_string "co_group")]
280 (const_string "none")))
282 ;; nil are zero instructions, and arith3 / arith3b are multiple instructions,
283 ;; so these do not belong in an insn group, although they are modeled
284 ;; with their own define_insn_reservations.
286 ;; Indicate what precision must be selected in fpscr for this insn, if any.
287 (define_attr "fp_mode" "single,double,none" (const_string "none"))
289 ;; Indicate if the fpu mode is set by this instruction
290 ;; "unknown" must have the value as "none" in fp_mode, and means
291 ;; that the instruction/abi has left the processor in an unknown
293 ;; "none" means that nothing has changed and no mode is set.
294 ;; This attribute is only used for the Renesas ABI.
295 (define_attr "fp_set" "single,double,unknown,none" (const_string "none"))
297 ; If a conditional branch destination is within -252..258 bytes away
298 ; from the instruction it can be 2 bytes long. Something in the
299 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
300 ; branches are initially assumed to be 16 bytes long.
301 ; In machine_dependent_reorg, we split all branches that are longer than
304 ;; The maximum range used for SImode constant pool entries is 1018. A final
305 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
306 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
307 ;; instruction around the pool table, 2 bytes of alignment before the table,
308 ;; and 30 bytes of alignment after the table. That gives a maximum total
309 ;; pool size of 1058 bytes.
310 ;; Worst case code/pool content size ratio is 1:2 (using asms).
311 ;; Thus, in the worst case, there is one instruction in front of a maximum
312 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
313 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
314 ;; If we have a forward branch, the initial table will be put after the
315 ;; unconditional branch.
317 ;; ??? We could do much better by keeping track of the actual pcloads within
318 ;; the branch range and in the pcload range in front of the branch range.
320 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
322 (define_attr "short_cbranch_p" "no,yes"
323 (cond [(match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
325 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
327 (match_test "NEXT_INSN (PREV_INSN (insn)) != insn")
329 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
331 ] (const_string "no")))
333 (define_attr "med_branch_p" "no,yes"
334 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
337 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
339 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
342 ] (const_string "no")))
344 (define_attr "med_cbranch_p" "no,yes"
345 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
348 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
350 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
353 ] (const_string "no")))
355 (define_attr "braf_branch_p" "no,yes"
356 (cond [(match_test "! TARGET_SH2")
358 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
361 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
363 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
366 ] (const_string "no")))
368 (define_attr "braf_cbranch_p" "no,yes"
369 (cond [(match_test "! TARGET_SH2")
371 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
374 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
376 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
379 ] (const_string "no")))
381 ;; An unconditional jump in the range -4092..4098 can be 2 bytes long.
382 ;; For wider ranges, we need a combination of a code and a data part.
383 ;; If we can get a scratch register for a long range jump, the code
384 ;; part can be 4 bytes long; otherwise, it must be 8 bytes long.
385 ;; If the jump is in the range -32764..32770, the data part can be 2 bytes
386 ;; long; otherwise, it must be 6 bytes long.
388 ;; All other instructions are two bytes long by default.
390 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
391 ;; but getattrtab doesn't understand this.
392 (define_attr "length" ""
393 (cond [(eq_attr "type" "cbranch")
394 (cond [(eq_attr "short_cbranch_p" "yes")
396 (eq_attr "med_cbranch_p" "yes")
398 (eq_attr "braf_cbranch_p" "yes")
400 ;; ??? using pc is not computed transitively.
401 (ne (match_dup 0) (match_dup 0))
403 (match_test "flag_pic")
406 (eq_attr "type" "jump")
407 (cond [(eq_attr "med_branch_p" "yes")
409 (and (match_test "prev_nonnote_insn (insn)")
410 (and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))")
412 (eq (symbol_ref "INSN_CODE (prev_nonnote_insn (insn))")
413 (symbol_ref "code_for_indirect_jump_scratch"))))
414 (cond [(eq_attr "braf_branch_p" "yes")
416 (not (match_test "flag_pic"))
418 (match_test "TARGET_SH2")
419 (const_int 10)] (const_int 18))
420 (eq_attr "braf_branch_p" "yes")
422 ;; ??? using pc is not computed transitively.
423 (ne (match_dup 0) (match_dup 0))
425 (match_test "flag_pic")
430 ;; DFA descriptions for the pipelines
435 (include "iterators.md")
436 (include "predicates.md")
437 (include "constraints.md")
439 ;; Definitions for filling delay slots
441 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
443 (define_attr "banked" "yes,no"
444 (cond [(match_test "sh_loads_bankedreg_p (insn)")
445 (const_string "yes")]
446 (const_string "no")))
448 ;; ??? This should be (nil) instead of (const_int 0)
449 (define_attr "hit_stack" "yes,no"
450 (cond [(not (match_test "find_regno_note (insn, REG_INC, SP_REG)"))
452 (const_string "yes")))
454 (define_attr "interrupt_function" "no,yes"
455 (const (symbol_ref "current_function_interrupt")))
457 (define_attr "in_delay_slot" "yes,no"
458 (cond [(eq_attr "type" "cbranch") (const_string "no")
459 (eq_attr "type" "pcload,pcload_si") (const_string "no")
460 (eq_attr "type" "fpscr_toggle") (const_string "no")
461 (eq_attr "needs_delay_slot" "yes") (const_string "no")
462 (eq_attr "length" "2") (const_string "yes")
463 ] (const_string "no")))
465 (define_attr "cond_delay_slot" "yes,no"
466 (cond [(eq_attr "in_delay_slot" "yes") (const_string "yes")
467 ] (const_string "no")))
469 (define_attr "is_sfunc" ""
470 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
472 ;; SH4 Double-precision computation with double-precision result -
473 ;; the two halves are ready at different times.
474 (define_attr "dfp_comp" "yes,no"
475 (cond [(eq_attr "type" "dfp_arith,dfp_mul,dfp_conv,dfdiv") (const_string "yes")]
476 (const_string "no")))
478 ;; Insns for which the latency of a preceding fp insn is decreased by one.
479 (define_attr "late_fp_use" "yes,no" (const_string "no"))
480 ;; And feeding insns for which this relevant.
481 (define_attr "any_fp_comp" "yes,no"
482 (cond [(eq_attr "type" "fp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
483 (const_string "yes")]
484 (const_string "no")))
486 (define_attr "any_int_load" "yes,no"
487 (cond [(eq_attr "type" "load,load_si,pcload,pcload_si")
488 (const_string "yes")]
489 (const_string "no")))
491 (define_attr "highpart" "user, ignore, extend, depend, must_split"
492 (const_string "user"))
495 (eq_attr "needs_delay_slot" "yes")
496 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
498 ;; Since a normal return (rts) implicitly uses the PR register,
499 ;; we can't allow PR register loads in an rts delay slot.
500 ;; On the SH1* and SH2*, the rte instruction reads the return pc from the
501 ;; stack, and thus we can't put a pop instruction in its delay slot.
502 ;; On the SH3* and SH4*, the rte instruction does not use the stack, so a
503 ;; pop instruction can go in the delay slot, unless it references a banked
504 ;; register (the register bank is switched by rte).
506 (eq_attr "type" "return")
507 [(and (eq_attr "in_delay_slot" "yes")
508 (ior (and (eq_attr "interrupt_function" "no")
509 (eq_attr "type" "!pload,prset"))
510 (and (eq_attr "interrupt_function" "yes")
511 (ior (match_test "TARGET_SH3") (eq_attr "hit_stack" "no"))
512 (eq_attr "banked" "no"))))
515 ;; Since a call implicitly uses the PR register, we can't allow
516 ;; a PR register store in a jsr delay slot.
519 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
520 [(and (eq_attr "in_delay_slot" "yes")
521 (eq_attr "type" "!pstore,prget")) (nil) (nil)])
523 ;; Conditional branches with delay slots are available starting with SH2.
524 ;; If zero displacement conditional branches are fast, disable the delay
525 ;; slot if the branch jumps over only one 2-byte insn.
527 (and (eq_attr "type" "cbranch")
528 (match_test "TARGET_SH2")
529 (not (and (match_test "TARGET_ZDCBRANCH")
530 (match_test "sh_cbranch_distance (insn, 4) == 2"))))
531 [(eq_attr "cond_delay_slot" "yes") (nil) (nil)])
533 ;; -------------------------------------------------------------------------
534 ;; SImode signed integer comparisons
535 ;; -------------------------------------------------------------------------
537 ;; Patterns to generate the tst instruction which are usually formed by
539 ;; The canonical form here being used is (eq (and (op) (op)) 0).
540 ;; For some bit patterns, such as contiguous bits, we also must accept
541 ;; zero_extract forms. Single bit tests are also handled via zero_extract
542 ;; patterns in the 'bit field extract patterns' section. All variants
543 ;; are eventually converted to the 'tstsi_t' insn.
544 ;; As long as pseudos can be created (before RA), 'tstsi_t' will also accept
545 ;; constants that won't fit into 8 bits. After having captured the constant
546 ;; we can decide better whether/how to load it into a register and do other
547 ;; post-combine optimizations such as bypassing sign/zero extensions.
548 (define_insn_and_split "tstsi_t"
550 (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "%z,r")
551 (match_operand:SI 1 "arith_or_int_operand" "K08,?r"))
554 && (can_create_pseudo_p () || arith_reg_operand (operands[1], SImode)
555 || satisfies_constraint_K08 (operands[1]))"
557 "TARGET_SH1 && can_create_pseudo_p () && CONST_INT_P (operands[1])
558 && !sh_in_recog_treg_set_expr ()"
561 gcc_assert (CONST_INT_P (operands[1]));
563 HOST_WIDE_INT op1val = INTVAL (operands[1]);
564 rtx reg = operands[0];
566 reg = SUBREG_REG (reg);
567 gcc_assert (REG_P (reg));
568 bool op0_dead_after_this =
569 sh_reg_dead_or_unused_after_insn (curr_insn, REGNO (reg));
575 "tstsi_t: trying to optimize const_int 0x%08x\n",
578 /* See if we can convert a test with a reg and a constant into
579 something simpler, if the reg is known to be zero or sign
581 sh_extending_set_of_reg eop0 = sh_find_extending_set_of_reg (operands[0],
583 if (eop0.ext_code != UNKNOWN)
585 /* Adjust the constant, trying to eliminate bits that are not
586 contributing to the result. */
587 if (eop0.from_mode == QImode)
589 | (eop0.ext_code == SIGN_EXTEND && (op1val & 0xFFFFFF80)
591 else if (eop0.from_mode == HImode)
593 | (eop0.ext_code == SIGN_EXTEND && (op1val & 0xFFFF8000)
594 ? 0x8000 : 0)) & 0xFFFF;
597 fprintf (dump_file, "tstsi_t: using effective const_int: 0x%08x\n",
600 /* Try to bypass the sign/zero extension first if op0 dies after
602 if (op0_dead_after_this && eop0.can_use_as_unextended_reg ())
605 fprintf (dump_file, "tstsi_t: bypassing sign/zero extension\n");
607 operands[0] = eop0.use_as_unextended_reg (curr_insn);
609 else if ((eop0.from_mode == QImode && op1val == 0xFF)
610 || (eop0.from_mode == HImode && op1val == 0xFFFF))
613 fprintf (dump_file, "tstsi_t: converting to cmpeqsi_t\n");
614 emit_insn (gen_cmpeqsi_t (eop0.use_as_extended_reg (curr_insn),
618 else if (eop0.ext_code == SIGN_EXTEND
619 && ((eop0.from_mode == QImode && op1val == 0x80)
620 || (eop0.from_mode == HImode && op1val == 0x8000)))
623 fprintf (dump_file, "tstsi_t: converting to cmpgesi_t\n");
624 emit_insn (gen_cmpgesi_t (eop0.use_as_extended_reg (curr_insn),
628 else if (!CONST_OK_FOR_K08 (op1val))
631 fprintf (dump_file, "tstsi_t: converting const_int to signed "
634 /* If here we haven't done anything yet. Convert the constant
635 to a signed value to reduce the constant pool size. */
636 operands[0] = eop0.use_as_extended_reg (curr_insn);
638 if (eop0.from_mode == QImode)
639 op1val |= (op1val & 0x80) ? 0xFFFFFFFFFFFFFF00LL : 0;
640 else if (eop0.from_mode == HImode)
641 op1val |= (op1val & 0x8000) ? 0xFFFFFFFFFFFF0000LL : 0;
644 operands[0] = eop0.use_as_extended_reg (curr_insn);
649 fprintf (dump_file, "tstsi_t: using const_int 0x%08x\n",
652 /* Try to fit the constant into 8 bits by shuffling the value in the
654 Doing that usually results in smaller code as the constants in the
655 pools are avoided (32 bit constant = load + constant = 6 bytes).
656 However, if the constant load (LS insn) can be hoisted insn dependencies
657 can be avoided and chances for parallel execution increase. The common
663 FIXME: For now we do that only when optimizing for size until there is
666 FIXME: If there are multiple tst insns in the block with the same
667 constant, avoid the #imm variant to avoid R0 loads. Use the 'tst Rn,Rm'
668 variant instead and load the constant into a reg. For that we'd need
669 to do some analysis. */
671 if (CONST_OK_FOR_K08 (op1val))
675 else if ((op1val & 0xFFFF) == 0
676 && CONST_OK_FOR_K08 (op1val >> 16) && optimize_size)
678 /* Use a swap.w insn to do a shift + reg copy (to R0) in one insn. */
679 op1val = op1val >> 16;
680 rtx r = gen_reg_rtx (SImode);
681 emit_insn (gen_rotlsi3_16 (r, operands[0]));
684 else if ((op1val & 0xFF) == 0
685 && CONST_OK_FOR_K08 (op1val >> 8) && optimize_size)
687 /* Use a swap.b insn to do a shift + reg copy (to R0) in one insn. */
688 op1val = op1val >> 8;
689 rtx r = gen_reg_rtx (SImode);
690 emit_insn (gen_swapbsi2 (r, operands[0]));
693 else if ((op1val & 3) == 0
694 && CONST_OK_FOR_K08 (op1val >> 2) && optimize_size)
696 op1val = op1val >> 2;
697 rtx r = gen_reg_rtx (SImode);
698 emit_insn (gen_lshrsi3_k (r, operands[0], GEN_INT (2)));
701 else if ((op1val & 1) == 0
702 && CONST_OK_FOR_K08 (op1val >> 1) && optimize_size)
704 op1val = op1val >> 1;
705 rtx r = gen_reg_rtx (SImode);
706 emit_insn (gen_shlr (r, operands[0]));
710 operands[1] = GEN_INT (op1val);
712 if (!satisfies_constraint_K08 (operands[1]))
713 operands[1] = force_reg (SImode, operands[1]);
715 emit_insn (gen_tstsi_t (operands[0], operands[1]));
718 [(set_attr "type" "mt_group")])
720 ;; This pattern is used by combine when testing QI/HImode subregs with a
721 ;; negative constant. Ignore high bits by masking them out in the constant.
722 (define_insn_and_split "*tst<mode>_t"
725 (and:QIHI (match_operand:QIHI 0 "arith_reg_operand")
726 (match_operand 1 "const_int_operand")) 0)
728 "TARGET_SH1 && can_create_pseudo_p ()"
732 (eq:SI (and:SI (match_dup 0) (match_dup 1)) (const_int 0)))]
734 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
735 operands[1] = GEN_INT (INTVAL (operands[1])
736 & (<MODE>mode == HImode ? 0xFFFF : 0xFF));
739 ;; This pattern might be risky because it also tests the upper bits and not
740 ;; only the subreg. We have to check whether the operands have been sign
741 ;; or zero extended. In the worst case, a zero extension has to be inserted
742 ;; to mask out the unwanted bits.
743 (define_insn_and_split "*tst<mode>_t_subregs"
747 (and:SI (match_operand:SI 0 "arith_reg_operand")
748 (match_operand:SI 1 "arith_reg_operand")) <lowpart_le>)
750 "TARGET_SH1 && TARGET_LITTLE_ENDIAN && can_create_pseudo_p ()"
752 "&& !sh_in_recog_treg_set_expr ()"
755 sh_split_tst_subregs (curr_insn, <MODE>mode, <lowpart_le>, operands);
759 (define_insn_and_split "*tst<mode>_t_subregs"
763 (and:SI (match_operand:SI 0 "arith_reg_operand")
764 (match_operand:SI 1 "arith_reg_operand")) <lowpart_be>)
766 "TARGET_SH1 && TARGET_BIG_ENDIAN && can_create_pseudo_p ()"
768 "&& !sh_in_recog_treg_set_expr ()"
771 sh_split_tst_subregs (curr_insn, <MODE>mode, <lowpart_be>, operands);
775 ;; Extract contiguous bits and compare them against zero.
776 ;; Notice that this will not be used for single bits. Special single bit
777 ;; extraction patterns are in the 'bit field extract patterns' section.
778 (define_insn_and_split "*tst<mode>_t_zero_extract"
780 (eq:SI (zero_extract:SI (match_operand:QIHISI 0 "arith_reg_operand")
781 (match_operand 1 "const_int_operand")
782 (match_operand 2 "const_int_operand"))
784 "TARGET_SH1 && can_create_pseudo_p ()"
788 (eq:SI (and:SI (match_dup 0) (match_dup 1)) (const_int 0)))]
790 operands[1] = GEN_INT (ZERO_EXTRACT_ANDMASK (operands[1], operands[2]));
791 if (GET_MODE (operands[0]) != SImode)
792 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
795 ;; Convert '(reg << shift) & mask' into 'reg & (mask >> shift)'.
796 ;; The shifted-out bits in the mask will always be zero, since the
797 ;; shifted-in bits in the reg will also be always zero.
798 (define_insn_and_split "*tstsi_t_shift_mask"
800 (eq:SI (and:SI (ashift:SI (match_operand:SI 0 "arith_reg_operand")
801 (match_operand 1 "const_int_operand"))
802 (match_operand 2 "const_int_operand"))
804 "TARGET_SH1 && can_create_pseudo_p ()"
808 (eq:SI (and:SI (match_dup 0) (match_dup 2)) (const_int 0)))]
810 operands[2] = GEN_INT (INTVAL (operands[2]) >> INTVAL (operands[1]));
813 (define_insn "cmpeqsi_t"
815 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
816 (match_operand:SI 1 "arith_operand" "N,rI08,r")))]
822 [(set_attr "type" "mt_group")])
824 ;; Sometimes combine fails to form the (eq (and (op) (op)) 0) tst insn.
825 ;; Try to fix that in the split1 pass by looking for the previous set
826 ;; of the tested op. Also see if there is a preceeding sign/zero
827 ;; extension that can be avoided.
830 (eq:SI (match_operand:SI 0 "arith_reg_operand") (const_int 0)))]
831 "TARGET_SH1 && can_create_pseudo_p () && optimize
832 && !sh_in_recog_treg_set_expr ()"
833 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))]
836 fprintf (dump_file, "cmpeqsi_t: trying to optimize const_int 0\n");
838 /* If the tested reg is not dead after this insn, it's probably used by
839 something else after the comparison. It's probably better to leave
841 rtx reg = operands[0];
843 reg = SUBREG_REG (reg);
844 gcc_assert (REG_P (reg));
845 if (find_regno_note (curr_insn, REG_DEAD, REGNO (reg)) != NULL_RTX)
848 /* FIXME: Maybe also search the predecessor basic blocks to catch
850 set_of_reg op = sh_find_set_of_reg (operands[0], curr_insn,
851 prev_nonnote_insn_bb);
853 if (op.set_src != NULL && GET_CODE (op.set_src) == AND
854 && !sh_insn_operands_modified_between_p (op.insn, op.insn, curr_insn))
857 fprintf (dump_file, "cmpeqsi_t: found preceeding and in insn %d\n",
860 if (!(arith_reg_operand (XEXP (op.set_src, 0), SImode)
861 && (arith_reg_operand (XEXP (op.set_src, 1), SImode)
862 || CONST_INT_P (XEXP (op.set_src, 1)))))
865 /* Assume that the operands of the andsi insn are compatible with the
866 operands of the tstsi_t insn, which is generally the case. */
868 fprintf (dump_file, "cmpeqsi_t: replacing with tstsi_t\n");
869 emit_insn (gen_tstsi_t (copy_rtx (XEXP (op.set_src, 0)),
870 copy_rtx (XEXP (op.set_src, 1))));
874 /* Converting HImode into tests against 0xFFFF tends to increase the code
875 size, as it will create constant pool entries. Disable it for now. */
876 const bool enable_himode = false;
878 /* FIXME: try to keep the (eq (reg) (const_int 0)). Even if the zero
879 extended reg is used after this insn, if we know that _before_ the zero
880 extension the value was loaded via sign extending mem load, we can just
881 use the value of the mem load directly. */
882 sh_extending_set_of_reg eop = sh_find_extending_set_of_reg (operands[0],
885 if (eop.ext_code != UNKNOWN
886 && (eop.from_mode == QImode || (eop.from_mode == HImode && enable_himode))
887 && eop.can_use_as_unextended_reg ()
888 && !reg_used_between_p (operands[0], eop.insn, curr_insn))
890 /* Bypass the sign/zero extension and test against the bit mask, but
891 only if it's the only use of the sign/zero extracted value.
892 Otherwise we'd be introducing new constants in the pool. */
894 fprintf (dump_file, "cmpeqsi_t: bypassing sign/zero extension in "
895 "insn %d and using tstsi_t\n", INSN_UID (op.insn));
897 emit_insn (gen_tstsi_t (
898 eop.use_as_unextended_reg (curr_insn),
899 GEN_INT (eop.from_mode == QImode ? 0xFF : 0xFFFF)));
904 fprintf (dump_file, "cmpeqsi_t: nothing optimized\n");
908 (define_insn "cmpgtsi_t"
910 (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
911 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
916 [(set_attr "type" "mt_group")])
918 (define_insn "cmpgesi_t"
920 (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
921 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
926 [(set_attr "type" "mt_group")])
928 ;; Recombine a cmp/pz followed by a nott into a shll.
929 ;; On non-SH2A recombine a cmp/pz followed by a movrt into shll-movt.
930 ;; On SH2A cmp/pz-movrt is slightly better, as it does not mutate the input.
933 (ge:SI (match_operand:SI 0 "arith_reg_operand") (const_int 0)))]
935 "TARGET_SH1 && can_create_pseudo_p () && optimize
936 && !sh_in_recog_treg_set_expr ()"
940 fprintf (dump_file, "cmpgesi_t: trying to optimize for const_int 0\n");
942 rtx_insn* i = next_nonnote_insn_bb (curr_insn);
946 fprintf (dump_file, "cmpgesi_t: following insn is \n");
947 print_rtl_single (dump_file, i);
948 fprintf (dump_file, "\n");
951 if (sh_is_nott_insn (i))
955 "cmpgesi_t: replacing (cmp/pz, nott) with (shll)\n");
956 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
957 set_insn_deleted (i);
961 /* On non-SH2A negc is used as movrt replacement, which sets T = 1.
962 Thus we can remove it only if T is marked as dead afterwards. */
963 if (rtx dest_reg = !TARGET_SH2A
964 && sh_reg_dead_or_unused_after_insn (i, T_REG)
965 ? sh_movrt_set_dest (i) : NULL)
969 "cmpgesi_t: replacing (cmp/pz, movrt) with (shll, movt)\n");
970 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
971 add_reg_note (emit_insn (gen_movt (dest_reg, get_t_reg_rtx ())),
972 REG_DEAD, get_t_reg_rtx ());
973 set_insn_deleted (i);
978 fprintf (dump_file, "cmpgesi_t: nothing optimized\n");
983 ;; FIXME: This is actually wrong. There is no way to literally move a
984 ;; general reg to t reg. Luckily, it seems that this pattern will be only
985 ;; used when the general reg is known be either '0' or '1' during combine.
986 ;; What we actually need is reg != 0 -> T, but we have only reg == 0 -> T.
987 ;; Due to interactions with other patterns, combine fails to pick the latter
988 ;; and invert the dependent logic.
989 (define_insn "*negtstsi"
990 [(set (reg:SI T_REG) (match_operand:SI 0 "arith_reg_operand" "r"))]
991 "TARGET_SH1 && !sh_in_recog_treg_set_expr ()"
993 [(set_attr "type" "mt_group")])
995 ;; Some integer sign comparison patterns can be realized with the div0s insn.
996 ;; div0s Rm,Rn T = (Rm >> 31) ^ (Rn >> 31)
998 ;; The 'cmp_div0s' pattern is our canonical form, into which all the other
999 ;; variations are converted. The negative forms will split into a trailing
1000 ;; nott sequence, which will be eliminated either by the
1001 ;; 'any_treg_expr_to_reg' pattern, or by the 'sh_treg_combine' pass.
1002 (define_insn "cmp_div0s"
1003 [(set (reg:SI T_REG)
1004 (lshiftrt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "%r")
1005 (match_operand:SI 1 "arith_reg_operand" "r"))
1009 [(set_attr "type" "arith")])
1011 (define_insn_and_split "*cmp_div0s_1"
1012 [(set (reg:SI T_REG)
1013 (xor:SI (ge:SI (match_operand:SI 0 "arith_reg_operand")
1015 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1017 "TARGET_SH1 && can_create_pseudo_p ()"
1020 [(set (reg:SI T_REG)
1021 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))])
1023 (define_insn_and_split "*cmp_div0s_2"
1024 [(set (reg:SI T_REG)
1025 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
1027 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1029 "TARGET_SH1 && can_create_pseudo_p ()"
1032 [(set (reg:SI T_REG)
1033 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))])
1035 (define_insn_and_split "*cmp_div0s_3"
1036 [(set (reg:SI T_REG)
1037 (eq:SI (ge:SI (match_operand:SI 0 "arith_reg_operand")
1039 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1041 "TARGET_SH1 && can_create_pseudo_p ()"
1044 [(set (reg:SI T_REG)
1045 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1046 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1048 (define_insn_and_split "*cmp_div0s_4"
1049 [(set (reg:SI T_REG)
1050 (ge:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
1051 (match_operand:SI 1 "arith_reg_operand"))
1053 "TARGET_SH1 && can_create_pseudo_p ()"
1056 [(set (reg:SI T_REG)
1057 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1058 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1060 (define_insn_and_split "*cmp_div0s_5"
1061 [(set (reg:SI T_REG)
1062 (xor:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
1064 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1066 "TARGET_SH1 && can_create_pseudo_p ()"
1069 [(set (reg:SI T_REG)
1070 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1071 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1073 (define_insn_and_split "*cmp_div0s_6"
1074 [(set (reg:SI T_REG)
1075 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
1077 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
1079 "TARGET_SH1 && can_create_pseudo_p ()"
1082 [(set (reg:SI T_REG)
1083 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1084 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1086 ;; In some cases, it might be shorter to get a tested bit into bit 31 and
1087 ;; use div0s. Otherwise it's usually better to just leave the xor and tst
1088 ;; sequence. The only thing we can try to do here is avoiding the large
1090 (define_insn_and_split "*cmp_div0s_7"
1091 [(set (reg:SI T_REG)
1092 (zero_extract:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
1093 (match_operand:SI 1 "arith_reg_operand"))
1095 (match_operand 2 "const_int_operand")))]
1096 "TARGET_SH1 && can_create_pseudo_p ()
1097 && (INTVAL (operands[2]) == 7 || INTVAL (operands[2]) == 15
1098 || INTVAL (operands[2]) == 23 || INTVAL (operands[2]) == 29
1099 || INTVAL (operands[2]) == 30 || INTVAL (operands[2]) == 31)"
1104 const int bitpos = INTVAL (operands[2]);
1106 rtx op0 = gen_reg_rtx (SImode);
1107 rtx op1 = gen_reg_rtx (SImode);
1109 if (bitpos == 23 || bitpos == 30 || bitpos == 29)
1111 emit_insn (gen_ashlsi3 (op0, operands[0], GEN_INT (31 - bitpos)));
1112 emit_insn (gen_ashlsi3 (op1, operands[1], GEN_INT (31 - bitpos)));
1114 else if (bitpos == 15)
1116 emit_insn (gen_extendhisi2 (op0, gen_lowpart (HImode, operands[0])));
1117 emit_insn (gen_extendhisi2 (op1, gen_lowpart (HImode, operands[1])));
1119 else if (bitpos == 7)
1121 emit_insn (gen_extendqisi2 (op0, gen_lowpart (QImode, operands[0])));
1122 emit_insn (gen_extendqisi2 (op1, gen_lowpart (QImode, operands[1])));
1124 else if (bitpos == 31)
1132 emit_insn (gen_cmp_div0s (op0, op1));
1136 ;; For bits 0..7 using a xor and tst #imm,r0 sequence seems to be better.
1137 ;; Thus allow the following patterns only for higher bit positions where
1138 ;; we it's more likely to save the large tst constant.
1139 (define_insn_and_split "*cmp_div0s_8"
1140 [(set (reg:SI T_REG)
1141 (eq:SI (zero_extract:SI (match_operand:SI 0 "arith_reg_operand")
1143 (match_operand 2 "const_int_operand"))
1144 (zero_extract:SI (match_operand:SI 1 "arith_reg_operand")
1147 "TARGET_SH1 && can_create_pseudo_p ()
1148 && (INTVAL (operands[2]) == 15
1149 || INTVAL (operands[2]) == 23 || INTVAL (operands[2]) == 29
1150 || INTVAL (operands[2]) == 30 || INTVAL (operands[2]) == 31)"
1153 [(set (reg:SI T_REG)
1154 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
1155 (const_int 1) (match_dup 2)))
1156 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1158 (define_insn_and_split "*cmp_div0s_9"
1159 [(set (reg:SI T_REG)
1160 (zero_extract:SI (xor:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
1161 (match_operand:SI 1 "arith_reg_operand"))
1162 (match_operand 2 "const_int_operand"))
1164 (match_operand 3 "const_int_operand")))]
1165 "TARGET_SH1 && can_create_pseudo_p ()
1166 && (INTVAL (operands[2]) & 0xFFFFFFFF) == (1U << INTVAL (operands[3]))
1167 && (INTVAL (operands[3]) == 15
1168 || INTVAL (operands[3]) == 23 || INTVAL (operands[3]) == 29
1169 || INTVAL (operands[3]) == 30 || INTVAL (operands[3]) == 31)"
1172 [(set (reg:SI T_REG)
1173 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
1174 (const_int 1) (match_dup 3)))
1175 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1177 ;; -------------------------------------------------------------------------
1178 ;; SImode compare and branch
1179 ;; -------------------------------------------------------------------------
1181 (define_expand "cbranchsi4"
1183 (if_then_else (match_operator 0 "comparison_operator"
1184 [(match_operand:SI 1 "arith_operand" "")
1185 (match_operand:SI 2 "arith_operand" "")])
1186 (label_ref (match_operand 3 "" ""))
1188 (clobber (reg:SI T_REG))]
1189 "can_create_pseudo_p ()"
1191 expand_cbranchsi4 (operands, LAST_AND_UNUSED_RTX_CODE, -1);
1195 ;; Combine patterns to invert compare and branch operations for which we
1196 ;; don't have actual comparison insns. These patterns are used in cases
1197 ;; which appear after the initial cbranchsi expansion, which also does
1198 ;; some condition inversion.
1201 (if_then_else (ne (match_operand:SI 0 "arith_reg_operand" "")
1202 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1203 (label_ref (match_operand 2))
1205 (clobber (reg:SI T_REG))]
1207 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (match_dup 1)))
1208 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1209 (label_ref (match_dup 2))
1212 ;; FIXME: These don't seem to have any effect on the generated cbranch code
1213 ;; anymore, but only on some register allocation choices.
1216 (if_then_else (le (match_operand:SI 0 "arith_reg_operand" "")
1217 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1218 (label_ref (match_operand 2))
1220 (clobber (reg:SI T_REG))]
1222 [(set (reg:SI T_REG) (gt:SI (match_dup 0) (match_dup 1)))
1223 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1224 (label_ref (match_dup 2))
1229 (if_then_else (lt (match_operand:SI 0 "arith_reg_operand" "")
1230 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1231 (label_ref (match_operand 2))
1233 (clobber (reg:SI T_REG))]
1235 [(set (reg:SI T_REG) (ge:SI (match_dup 0) (match_dup 1)))
1236 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1237 (label_ref (match_dup 2))
1242 (if_then_else (leu (match_operand:SI 0 "arith_reg_operand" "")
1243 (match_operand:SI 1 "arith_reg_operand" ""))
1244 (label_ref (match_operand 2))
1246 (clobber (reg:SI T_REG))]
1248 [(set (reg:SI T_REG) (gtu:SI (match_dup 0) (match_dup 1)))
1249 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1250 (label_ref (match_dup 2))
1255 (if_then_else (ltu (match_operand:SI 0 "arith_reg_operand" "")
1256 (match_operand:SI 1 "arith_reg_operand" ""))
1257 (label_ref (match_operand 2))
1259 (clobber (reg:SI T_REG))]
1261 [(set (reg:SI T_REG) (geu:SI (match_dup 0) (match_dup 1)))
1262 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1263 (label_ref (match_dup 2))
1266 ;; -------------------------------------------------------------------------
1267 ;; SImode unsigned integer comparisons
1268 ;; -------------------------------------------------------------------------
1270 ;; Usually comparisons of 'unsigned int >= 0' are optimized away completely.
1271 ;; However, especially when optimizations are off (e.g. -O0) such comparisons
1272 ;; might remain and we have to handle them. If the '>= 0' case wasn't
1273 ;; handled here, something else would just load a '0' into the second operand
1274 ;; and do the comparison. We can do slightly better by just setting the
1276 (define_insn_and_split "cmpgeusi_t"
1277 [(set (reg:SI T_REG)
1278 (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1279 (match_operand:SI 1 "arith_reg_or_0_operand" "r")))]
1282 "&& satisfies_constraint_Z (operands[1])"
1283 [(set (reg:SI T_REG) (const_int 1))]
1285 [(set_attr "type" "mt_group")])
1287 (define_insn "cmpgtusi_t"
1288 [(set (reg:SI T_REG)
1289 (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1290 (match_operand:SI 1 "arith_reg_operand" "r")))]
1293 [(set_attr "type" "mt_group")])
1295 ;; -------------------------------------------------------------------------
1296 ;; DImode compare and branch
1297 ;; -------------------------------------------------------------------------
1299 ;; arith3 patterns don't work well with the sh4-300 branch prediction mechanism.
1300 ;; Therefore, we aim to have a set of three branches that go straight to the
1301 ;; destination, i.e. only one of them is taken at any one time.
1302 ;; This mechanism should also be slightly better for the sh4-200.
1304 (define_expand "cbranchdi4"
1306 (if_then_else (match_operator 0 "comparison_operator"
1307 [(match_operand:DI 1 "arith_operand")
1308 (match_operand:DI 2 "arith_operand")])
1309 (label_ref (match_operand 3))
1311 (clobber (reg:SI T_REG))]
1312 "TARGET_SH2 && can_create_pseudo_p ()"
1314 if (!expand_cbranchdi4 (operands, GET_CODE (operands[0])))
1319 ;; -------------------------------------------------------------------------
1320 ;; DImode signed integer comparisons
1321 ;; -------------------------------------------------------------------------
1324 [(set (reg:SI T_REG)
1325 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
1326 (match_operand:DI 1 "arith_operand" "r"))
1330 return output_branchy_insn (EQ, "tst\t%S1,%S0;bf\t%l9;tst\t%R1,%R0",
1333 [(set_attr "length" "6")
1334 (set_attr "type" "arith3b")])
1336 (define_insn "cmpeqdi_t"
1337 [(set (reg:SI T_REG)
1338 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1339 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
1342 static const char* alt[] =
1349 "cmp/eq %S1,%S0" "\n"
1351 " cmp/eq %R1,%R0" "\n"
1354 return alt[which_alternative];
1356 [(set_attr "length" "6")
1357 (set_attr "type" "arith3b")])
1360 [(set (reg:SI T_REG)
1361 (eq:SI (match_operand:DI 0 "arith_reg_operand" "")
1362 (match_operand:DI 1 "arith_reg_or_0_operand" "")))]
1363 ;; If we applied this split when not optimizing, it would only be
1364 ;; applied during the machine-dependent reorg, when no new basic blocks
1366 "TARGET_SH1 && reload_completed && optimize"
1367 [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
1368 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1369 (label_ref (match_dup 6))
1371 (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
1374 operands[2] = gen_highpart (SImode, operands[0]);
1375 operands[3] = operands[1] == const0_rtx
1377 : gen_highpart (SImode, operands[1]);
1378 operands[4] = gen_lowpart (SImode, operands[0]);
1379 operands[5] = gen_lowpart (SImode, operands[1]);
1380 operands[6] = gen_label_rtx ();
1383 (define_insn "cmpgtdi_t"
1384 [(set (reg:SI T_REG)
1385 (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1386 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1389 static const char* alt[] =
1391 "cmp/eq %S1,%S0" "\n"
1393 " cmp/gt %S1,%S0" "\n"
1394 " cmp/hi %R1,%R0" "\n"
1400 " cmp/hi %S0,%R0" "\n"
1403 return alt[which_alternative];
1405 [(set_attr "length" "8")
1406 (set_attr "type" "arith3")])
1408 (define_insn "cmpgedi_t"
1409 [(set (reg:SI T_REG)
1410 (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1411 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1414 static const char* alt[] =
1416 "cmp/eq %S1,%S0" "\n"
1418 " cmp/ge %S1,%S0" "\n"
1419 " cmp/hs %R1,%R0" "\n"
1424 return alt[which_alternative];
1426 [(set_attr "length" "8,2")
1427 (set_attr "type" "arith3,mt_group")])
1429 ;; -------------------------------------------------------------------------
1430 ;; DImode unsigned integer comparisons
1431 ;; -------------------------------------------------------------------------
1433 (define_insn "cmpgeudi_t"
1434 [(set (reg:SI T_REG)
1435 (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1436 (match_operand:DI 1 "arith_reg_operand" "r")))]
1439 return "cmp/eq %S1,%S0" "\n"
1441 " cmp/hs %S1,%S0" "\n"
1442 " cmp/hs %R1,%R0" "\n"
1445 [(set_attr "length" "8")
1446 (set_attr "type" "arith3")])
1448 (define_insn "cmpgtudi_t"
1449 [(set (reg:SI T_REG)
1450 (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1451 (match_operand:DI 1 "arith_reg_operand" "r")))]
1454 return "cmp/eq %S1,%S0" "\n"
1456 " cmp/hi %S1,%S0" "\n"
1457 " cmp/hi %R1,%R0" "\n"
1460 [(set_attr "length" "8")
1461 (set_attr "type" "arith3")])
1463 ;; -------------------------------------------------------------------------
1464 ;; Conditional move instructions
1465 ;; -------------------------------------------------------------------------
1467 (define_insn "*movsicc_t_false"
1468 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1469 (if_then_else (eq (reg:SI T_REG) (const_int 0))
1470 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1471 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1472 "TARGET_PRETEND_CMOVE
1473 && (arith_reg_operand (operands[1], SImode)
1474 || (immediate_operand (operands[1], SImode)
1475 && satisfies_constraint_I08 (operands[1])))"
1481 [(set_attr "type" "mt_group,arith") ;; poor approximation
1482 (set_attr "length" "4")])
1484 (define_insn "*movsicc_t_true"
1485 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1486 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1487 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1488 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1489 "TARGET_PRETEND_CMOVE
1490 && (arith_reg_operand (operands[1], SImode)
1491 || (immediate_operand (operands[1], SImode)
1492 && satisfies_constraint_I08 (operands[1])))"
1498 [(set_attr "type" "mt_group,arith") ;; poor approximation
1499 (set_attr "length" "4")])
1501 (define_expand "movsicc"
1502 [(set (match_operand:SI 0 "arith_reg_dest" "")
1503 (if_then_else:SI (match_operand 1 "comparison_operator" "")
1504 (match_operand:SI 2 "arith_reg_or_0_operand" "")
1505 (match_operand:SI 3 "arith_reg_operand" "")))]
1506 "TARGET_PRETEND_CMOVE"
1508 rtx_code code = GET_CODE (operands[1]);
1509 rtx_code new_code = code;
1510 rtx op0 = XEXP (operands[1], 0);
1511 rtx op1 = XEXP (operands[1], 1);
1513 if (! currently_expanding_to_rtl)
1518 case LT: case LE: case LEU: case LTU:
1519 if (GET_MODE_CLASS (GET_MODE (op0)) != MODE_INT)
1523 new_code = reverse_condition (code);
1525 case EQ: case GT: case GE: case GEU: case GTU:
1531 sh_emit_scc_to_t (new_code, op0, op1);
1532 operands[1] = gen_rtx_fmt_ee (new_code == code ? NE : EQ, VOIDmode,
1533 gen_rtx_REG (SImode, T_REG), const0_rtx);
1536 ;; -------------------------------------------------------------------------
1537 ;; Addition instructions
1538 ;; -------------------------------------------------------------------------
1540 (define_insn_and_split "adddi3"
1541 [(set (match_operand:DI 0 "arith_reg_dest")
1542 (plus:DI (match_operand:DI 1 "arith_reg_operand")
1543 (match_operand:DI 2 "arith_reg_operand")))
1544 (clobber (reg:SI T_REG))]
1547 "&& can_create_pseudo_p ()"
1550 emit_insn (gen_clrt ());
1551 emit_insn (gen_addc (gen_lowpart (SImode, operands[0]),
1552 gen_lowpart (SImode, operands[1]),
1553 gen_lowpart (SImode, operands[2])));
1554 emit_insn (gen_addc (gen_highpart (SImode, operands[0]),
1555 gen_highpart (SImode, operands[1]),
1556 gen_highpart (SImode, operands[2])));
1561 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1562 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
1563 (match_operand:SI 2 "arith_reg_operand" "r"))
1566 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
1569 [(set_attr "type" "arith")])
1571 ;; A simplified version of the addc insn, where the exact value of the
1572 ;; T bit doesn't matter. This is easier for combine to pick up.
1573 ;; We allow a reg or 0 for one of the operands in order to be able to
1574 ;; do 'reg + T' sequences.
1575 (define_insn_and_split "*addc"
1576 [(set (match_operand:SI 0 "arith_reg_dest")
1577 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand")
1578 (match_operand:SI 2 "arith_reg_or_0_operand"))
1579 (match_operand 3 "treg_set_expr")))
1580 (clobber (reg:SI T_REG))]
1581 "TARGET_SH1 && can_create_pseudo_p ()"
1586 sh_treg_insns ti = sh_split_treg_set_expr (operands[3], curr_insn);
1587 if (ti.has_trailing_nott ())
1589 if (operands[2] == const0_rtx)
1591 /* op1 + 0 + (1 - T) = op1 + 1 - T = op1 - (-1) - T */
1592 remove_insn (ti.trailing_nott ());
1593 emit_insn (gen_subc (operands[0], operands[1],
1594 force_reg (SImode, GEN_INT (-1))));
1597 else if (!TARGET_SH2A)
1599 /* op1 + op2 + (1 - T) = op1 - (0 - op2 - 1) - T = op1 - ~op2 - T
1600 On SH2A keep the nott insn, because nott-addc sequence doesn't
1601 mutate the inputs. */
1602 remove_insn (ti.trailing_nott ());
1603 rtx tmp = gen_reg_rtx (SImode);
1604 emit_insn (gen_one_cmplsi2 (tmp, operands[2]));
1605 emit_insn (gen_subc (operands[0], operands[1], tmp));
1610 emit_insn (gen_addc (operands[0], operands[1],
1611 force_reg (SImode, operands[2])));
1615 (define_insn_and_split "*addc"
1616 [(set (match_operand:SI 0 "arith_reg_dest")
1617 (plus:SI (plus:SI (match_operand 1 "treg_set_expr")
1618 (match_operand:SI 2 "arith_reg_operand"))
1619 (match_operand:SI 3 "arith_reg_operand")))
1620 (clobber (reg:SI T_REG))]
1621 "TARGET_SH1 && can_create_pseudo_p ()"
1624 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3))
1626 (clobber (reg:SI T_REG))])])
1628 (define_insn_and_split "*addc"
1629 [(set (match_operand:SI 0 "arith_reg_dest")
1630 (plus:SI (match_operand 1 "treg_set_expr")
1631 (plus:SI (match_operand:SI 2 "arith_reg_operand")
1632 (match_operand:SI 3 "arith_reg_operand"))))
1633 (clobber (reg:SI T_REG))]
1634 "TARGET_SH1 && can_create_pseudo_p ()"
1637 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3))
1639 (clobber (reg:SI T_REG))])])
1641 ;; Sometimes combine will try to do 'reg + (0-reg) + 1' if the *addc pattern
1642 ;; matched. Split this up into a simple sub add sequence, as this will save
1643 ;; us one sett insn.
1644 (define_insn_and_split "*minus_plus_one"
1645 [(set (match_operand:SI 0 "arith_reg_dest" "")
1646 (plus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
1647 (match_operand:SI 2 "arith_reg_operand" ""))
1652 [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
1653 (set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))])
1656 ;; The tree optimiziers canonicalize
1661 ;; On SH2A an add-bclr sequence will be used to handle this.
1662 ;; On non-SH2A re-emit the add-and sequence to improve register utilization.
1663 (define_insn_and_split "*round_int_even"
1664 [(set (match_operand:SI 0 "arith_reg_dest")
1665 (and:SI (plus:SI (match_operand:SI 1 "arith_reg_operand")
1668 "TARGET_SH1 && !TARGET_SH2A && can_create_pseudo_p ()
1669 && !reg_overlap_mentioned_p (operands[0], operands[1])"
1672 [(set (match_dup 0) (const_int -2))
1673 (set (match_dup 2) (plus:SI (match_dup 1) (const_int 1)))
1674 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 2)))]
1676 operands[2] = gen_reg_rtx (SImode);
1679 ;; If the *round_int_even pattern is combined with another plus,
1680 ;; convert it into an addc pattern to emit an shlr-addc sequence.
1681 ;; This split is taken by combine on non-SH2A and SH2A.
1683 [(set (match_operand:SI 0 "arith_reg_dest")
1684 (plus:SI (and:SI (plus:SI (match_operand:SI 1 "arith_reg_operand")
1687 (match_operand:SI 2 "arith_reg_operand")))]
1688 "TARGET_SH1 && can_create_pseudo_p ()"
1689 [(parallel [(set (match_dup 0)
1690 (plus:SI (plus:SI (match_dup 1) (match_dup 2))
1691 (and:SI (match_dup 1) (const_int 1))))
1692 (clobber (reg:SI T_REG))])])
1694 ;; Split 'reg + T' into 'reg + 0 + T' to utilize the addc insn.
1695 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
1696 ;; operation, as opposed to sequences such as
1700 ;; Even if the constant is not CSE-ed, a sequence such as
1703 ;; can be scheduled much better since the load of the constant can be
1704 ;; done earlier, before any comparison insns that store the result in
1706 ;; However, avoid things like 'reg + 1', which would expand into a
1707 ;; 3 insn sequence, instead of add #imm8.
1708 (define_insn_and_split "*addc_t_r"
1709 [(set (match_operand:SI 0 "arith_reg_dest")
1710 (plus:SI (match_operand 1 "treg_set_expr_not_const01")
1711 (match_operand:SI 2 "arith_reg_operand")))
1712 (clobber (reg:SI T_REG))]
1713 "TARGET_SH1 && can_create_pseudo_p ()"
1716 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (const_int 0))
1718 (clobber (reg:SI T_REG))])])
1720 (define_insn_and_split "*addc_r_t"
1721 [(set (match_operand:SI 0 "arith_reg_dest")
1722 (plus:SI (match_operand:SI 1 "arith_reg_operand")
1723 (match_operand 2 "treg_set_expr_not_const01")))
1724 (clobber (reg:SI T_REG))]
1725 "TARGET_SH1 && can_create_pseudo_p ()"
1728 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (const_int 0))
1730 (clobber (reg:SI T_REG))])])
1732 ;; Convert '2 * reg + T' into 'reg + reg + T'.
1733 (define_insn_and_split "*addc_2r_t"
1734 [(set (match_operand:SI 0 "arith_reg_dest")
1735 (plus:SI (match_operand 1 "treg_set_expr")
1736 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
1738 (clobber (reg:SI T_REG))]
1739 "TARGET_SH1 && can_create_pseudo_p ()"
1742 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 2))
1744 (clobber (reg:SI T_REG))])])
1746 (define_insn_and_split "*addc_2r_t"
1747 [(set (match_operand:SI 0 "arith_reg_dest")
1748 (plus:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
1750 (match_operand 2 "treg_set_expr")))
1751 (clobber (reg:SI T_REG))]
1752 "TARGET_SH1 && can_create_pseudo_p ()"
1755 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (match_dup 1))
1757 (clobber (reg:SI T_REG))])])
1759 ;; Convert '(op2 + T) - op3' into 'op2 + (-op3) + T'
1760 (define_insn_and_split "*addc_negreg_t"
1761 [(set (match_operand:SI 0 "arith_reg_dest")
1762 (minus:SI (plus:SI (match_operand 1 "treg_set_expr")
1763 (match_operand:SI 2 "arith_reg_operand"))
1764 (match_operand:SI 3 "arith_reg_operand")))
1765 (clobber (reg:SI T_REG))]
1766 "TARGET_SH1 && can_create_pseudo_p ()"
1769 [(set (match_dup 4) (neg:SI (match_dup 3)))
1770 (parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 4))
1772 (clobber (reg:SI T_REG))])]
1774 operands[4] = gen_reg_rtx (SImode);
1777 (define_expand "addsi3"
1778 [(set (match_operand:SI 0 "arith_reg_dest")
1779 (plus:SI (match_operand:SI 1 "arith_reg_operand")
1780 (match_operand:SI 2 "arith_or_int_operand")))]
1783 if (!arith_operand (operands[2], SImode))
1785 if (!sh_lra_p () || reg_overlap_mentioned_p (operands[0], operands[1]))
1787 emit_insn (gen_addsi3_scr (operands[0], operands[1], operands[2]));
1793 ;; The *addsi3_compact is made an insn_and_split and accepts actually
1794 ;; impossible constraints to make LRA's register elimination work well on SH.
1795 ;; The problem is that LRA expects something like
1796 ;; (set rA (plus rB (const_int N)))
1797 ;; to work. We can do that, but we have to split out an additional reg-reg
1798 ;; copy or constant load before the actual add insn.
1799 ;; Use u constraint for that case to avoid the invalid value in the stack
1801 ;; This also results in better code when LRA is not used. However, we have
1802 ;; to use different sets of patterns and the order of these patterns is
1804 ;; In some cases the constant zero might end up in operands[2] of the
1805 ;; patterns. We have to accept that and convert it into a reg-reg move.
1806 (define_insn_and_split "*addsi3_compact_lra"
1807 [(set (match_operand:SI 0 "arith_reg_dest" "=r,&u")
1808 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0,r")
1809 (match_operand:SI 2 "arith_or_int_operand" "rI08,rn")))]
1810 "TARGET_SH1 && sh_lra_p ()
1811 && (! reg_overlap_mentioned_p (operands[0], operands[1])
1812 || arith_operand (operands[2], SImode))"
1816 "&& reload_completed
1817 && ! reg_overlap_mentioned_p (operands[0], operands[1])"
1818 [(set (match_dup 0) (match_dup 2))
1819 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
1821 /* Prefer 'mov r0,r1; add #imm8,r1' over 'mov #imm8,r1; add r0,r1' */
1822 if (satisfies_constraint_I08 (operands[2]))
1823 std::swap (operands[1], operands[2]);
1825 [(set_attr "type" "arith")])
1827 (define_insn_and_split "addsi3_scr"
1828 [(set (match_operand:SI 0 "arith_reg_dest" "=r,&u,&u")
1829 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0,r,r")
1830 (match_operand:SI 2 "arith_or_int_operand" "rI08,r,n")))
1831 (clobber (match_scratch:SI 3 "=X,X,&u"))]
1837 "&& reload_completed"
1838 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1840 if (operands[2] == const0_rtx)
1842 emit_move_insn (operands[0], operands[1]);
1846 if (CONST_INT_P (operands[2]) && !satisfies_constraint_I08 (operands[2]))
1848 if (reg_overlap_mentioned_p (operands[0], operands[1]))
1850 emit_move_insn (operands[3], operands[2]);
1851 emit_move_insn (operands[0], operands[1]);
1852 operands[2] = operands[3];
1856 emit_move_insn (operands[0], operands[2]);
1857 operands[2] = operands[1];
1860 else if (!reg_overlap_mentioned_p (operands[0], operands[1]))
1862 if (!reg_overlap_mentioned_p (operands[0], operands[2]))
1863 emit_move_insn (operands[0], operands[1]);
1865 operands[2] = operands[1];
1868 [(set_attr "type" "arith")])
1870 ;; Old reload might generate add insns directly (not through the expander) for
1871 ;; address register calculations when reloading, in which case it won't try
1872 ;; the addsi_scr pattern. Because reload will sometimes try to validate
1873 ;; the generated insns and their constraints, this pattern must be
1874 ;; recognizable during and after reload. However, when reload generates
1875 ;; address register calculations for the stack pointer, we don't allow this
1876 ;; pattern. This will make reload prefer using indexed @(reg + reg) address
1877 ;; modes when the displacement of a @(disp + reg) doesn't fit.
1878 (define_insn_and_split "*addsi3"
1879 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1880 (plus:SI (match_operand:SI 1 "arith_reg_operand" "r")
1881 (match_operand:SI 2 "arith_or_int_operand" "rn")))]
1882 "TARGET_SH1 && !sh_lra_p ()
1883 && (reload_completed || reload_in_progress)
1884 && !reg_overlap_mentioned_p (operands[0], operands[1])
1885 && (!reload_in_progress
1886 || ((!REG_P (operands[1]) || REGNO (operands[1]) != SP_REG)
1887 && (!REG_P (operands[2]) || REGNO (operands[2]) != SP_REG)))"
1890 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1892 if (operands[2] == const0_rtx)
1894 emit_move_insn (operands[0], operands[1]);
1898 if (CONST_INT_P (operands[2]))
1900 if (satisfies_constraint_I08 (operands[2]))
1901 emit_move_insn (operands[0], operands[1]);
1904 emit_move_insn (operands[0], operands[2]);
1905 operands[2] = operands[1];
1908 else if (!reg_overlap_mentioned_p (operands[0], operands[2]))
1909 emit_move_insn (operands[0], operands[1]);
1911 operands[2] = operands[1];
1914 (define_insn_and_split "*addsi3"
1915 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1916 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0,r")
1917 (match_operand:SI 2 "arith_operand" "rI08,Z")))]
1918 "TARGET_SH1 && !sh_lra_p ()"
1922 "&& operands[2] == const0_rtx"
1923 [(set (match_dup 0) (match_dup 1))]
1926 [(set_attr "type" "arith")])
1928 ;; -------------------------------------------------------------------------
1929 ;; Subtraction instructions
1930 ;; -------------------------------------------------------------------------
1932 (define_insn_and_split "subdi3"
1933 [(set (match_operand:DI 0 "arith_reg_dest")
1934 (minus:DI (match_operand:DI 1 "arith_reg_operand")
1935 (match_operand:DI 2 "arith_reg_operand")))
1936 (clobber (reg:SI T_REG))]
1939 "&& can_create_pseudo_p ()"
1942 emit_insn (gen_clrt ());
1943 emit_insn (gen_subc (gen_lowpart (SImode, operands[0]),
1944 gen_lowpart (SImode, operands[1]),
1945 gen_lowpart (SImode, operands[2])));
1946 emit_insn (gen_subc (gen_highpart (SImode, operands[0]),
1947 gen_highpart (SImode, operands[1]),
1948 gen_highpart (SImode, operands[2])));
1953 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1954 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
1955 (match_operand:SI 2 "arith_reg_operand" "r"))
1958 (gtu:SI (minus:SI (minus:SI (match_dup 1) (match_dup 2))
1963 [(set_attr "type" "arith")])
1965 ;; A simplified version of the subc insn, where the exact value of the
1966 ;; T bit doesn't matter. This is easier for combine to pick up.
1967 ;; We allow a reg or 0 for one of the operands in order to be able to
1968 ;; do 'reg - T' sequences. Reload will load the constant 0 into the reg
1970 (define_insn_and_split "*subc"
1971 [(set (match_operand:SI 0 "arith_reg_dest")
1972 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand")
1973 (match_operand:SI 2 "arith_reg_or_0_operand"))
1974 (match_operand 3 "treg_set_expr")))
1975 (clobber (reg:SI T_REG))]
1976 "TARGET_SH1 && can_create_pseudo_p ()"
1981 sh_treg_insns ti = sh_split_treg_set_expr (operands[3], curr_insn);
1982 if (ti.has_trailing_nott ())
1984 if (operands[2] == const0_rtx)
1986 /* op1 - (1 - T) = op1 - 1 + T = op1 + (-1) + T */
1987 remove_insn (ti.trailing_nott ());
1988 emit_insn (gen_addc (operands[0], operands[1],
1989 force_reg (SImode, GEN_INT (-1))));
1992 else if (!TARGET_SH2A)
1994 /* op1 - op2 - (1 - T) = op1 + (0 - op2 - 1) + T = op1 + ~op2 + T
1995 On SH2A keep the nott insn, because nott-subc sequence doesn't
1996 mutate the inputs. */
1997 remove_insn (ti.trailing_nott ());
1998 rtx tmp = gen_reg_rtx (SImode);
1999 emit_insn (gen_one_cmplsi2 (tmp, operands[2]));
2000 emit_insn (gen_addc (operands[0], operands[1], tmp));
2005 emit_insn (gen_subc (operands[0], operands[1],
2006 force_reg (SImode, operands[2])));
2010 ;; Convert reg - T - reg = reg - reg - T
2011 (define_insn_and_split "*subc"
2012 [(set (match_operand:SI 0 "arith_reg_dest")
2013 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand")
2014 (match_operand 2 "treg_set_expr"))
2015 (match_operand:SI 3 "arith_reg_operand")))
2016 (clobber (reg:SI T_REG))]
2017 "TARGET_SH1 && can_create_pseudo_p ()"
2020 [(parallel [(set (match_dup 0)
2021 (minus:SI (minus:SI (match_dup 1) (match_dup 3))
2023 (clobber (reg:SI T_REG))])])
2025 ;; Split reg - reg - 1 into a sett subc sequence, as it can be scheduled
2026 ;; better, if the sett insn can be done early.
2027 ;; Notice that combine turns 'a - b - 1' into 'a + (~b)'.
2028 (define_insn_and_split "*subc"
2029 [(set (match_operand:SI 0 "arith_reg_dest" "")
2030 (plus:SI (not:SI (match_operand:SI 1 "arith_reg_operand" ""))
2031 (match_operand:SI 2 "arith_reg_operand" "")))
2032 (clobber (reg:SI T_REG))]
2033 "TARGET_SH1 && can_create_pseudo_p ()"
2036 [(parallel [(set (match_dup 0)
2037 (minus:SI (minus:SI (match_dup 2) (match_dup 1))
2039 (clobber (reg:SI T_REG))])])
2041 ;; Split 'reg - T' into 'reg - 0 - T' to utilize the subc insn.
2042 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
2043 ;; operation, as opposed to sequences such as
2047 ;; Even if the constant is not CSE-ed, a sequence such as
2050 ;; can be scheduled much better since the load of the constant can be
2051 ;; done earlier, before any comparison insns that store the result in
2053 ;; However, avoid things like 'reg - 1', which would expand into a
2054 ;; 3 insn sequence, instead of add #imm8.
2055 (define_insn_and_split "*subc"
2056 [(set (match_operand:SI 0 "arith_reg_dest" "")
2057 (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
2058 (match_operand 2 "treg_set_expr_not_const01")))
2059 (clobber (reg:SI T_REG))]
2060 "TARGET_SH1 && can_create_pseudo_p ()"
2063 [(parallel [(set (match_dup 0)
2064 (minus:SI (minus:SI (match_dup 1) (const_int 0))
2066 (clobber (reg:SI T_REG))])])
2069 ;; (1 - T) - op2 = 1 - op2 - T
2070 (define_insn_and_split "*subc_negt_reg"
2071 [(set (match_operand:SI 0 "arith_reg_dest")
2072 (minus:SI (match_operand 1 "treg_set_expr_not_const01")
2073 (match_operand:SI 2 "arith_reg_operand")))
2074 (clobber (reg:SI T_REG))]
2075 "TARGET_SH1 && can_create_pseudo_p ()"
2080 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
2081 if (ti.remove_trailing_nott ())
2083 /* (1 - T) - op2 = 1 - op2 - T */
2084 emit_insn (gen_subc (operands[0],
2085 force_reg (SImode, GEN_INT (1)), operands[2]));
2089 /* T - op2: use movt,sub sequence. */
2090 rtx tmp = gen_reg_rtx (SImode);
2091 emit_insn (gen_movt (tmp, get_t_reg_rtx ()));
2092 emit_insn (gen_subsi3 (operands[0], tmp, operands[2]));
2098 ;; op1 - (1 - T) + op3 = op1 - 1 + T + op3
2099 ;; (op1 - T) + op3 = op1 - (-op3) - T
2100 (define_insn_and_split "*subc_negreg_t"
2101 [(set (match_operand:SI 0 "arith_reg_dest")
2102 (plus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand")
2103 (match_operand 2 "treg_set_expr"))
2104 (match_operand:SI 3 "arith_reg_operand")))
2105 (clobber (reg:SI T_REG))]
2106 "TARGET_SH1 && can_create_pseudo_p ()"
2111 sh_treg_insns ti = sh_split_treg_set_expr (operands[2], curr_insn);
2112 if (ti.remove_trailing_nott ())
2114 /* op1 - (1 - T) + op3 = (op1 - 1) + op3 + T */
2115 rtx tmp = gen_reg_rtx (SImode);
2116 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (-1)));
2117 emit_insn (gen_addc (operands[0], tmp, operands[3]));
2121 /* (op1 - T) + op3' = 'op1 - (-op3) - T */
2122 rtx tmp = gen_reg_rtx (SImode);
2123 emit_insn (gen_negsi2 (tmp, operands[3]));
2124 emit_insn (gen_subc (operands[0], operands[1], tmp));
2129 (define_insn "*subsi3_internal"
2130 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2131 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2132 (match_operand:SI 2 "arith_reg_operand" "r")))]
2135 [(set_attr "type" "arith")])
2142 ;; since this will sometimes save one instruction.
2143 ;; Otherwise we might get a sequence like
2147 ;; if the source and dest regs are the same.
2148 (define_expand "subsi3"
2149 [(set (match_operand:SI 0 "arith_reg_operand" "")
2150 (minus:SI (match_operand:SI 1 "arith_operand" "")
2151 (match_operand:SI 2 "arith_reg_operand" "")))]
2154 if (CONST_INT_P (operands[1]))
2156 emit_insn (gen_negsi2 (operands[0], operands[2]));
2157 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
2162 ;; -------------------------------------------------------------------------
2163 ;; Division instructions
2164 ;; -------------------------------------------------------------------------
2166 ;; We take advantage of the library routines which don't clobber as many
2167 ;; registers as a normal function call would.
2169 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
2170 ;; also has an effect on the register that holds the address of the sfunc.
2171 ;; To make this work, we have an extra dummy insn that shows the use
2172 ;; of this register for reorg.
2174 (define_insn "use_sfunc_addr"
2175 [(set (reg:SI PR_REG)
2176 (unspec:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
2177 "TARGET_SH1 && check_use_sfunc_addr (insn, operands[0])"
2179 [(set_attr "length" "0")])
2181 (define_insn "udivsi3_sh2a"
2182 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2183 (udiv:SI (match_operand:SI 1 "arith_reg_operand" "0")
2184 (match_operand:SI 2 "arith_reg_operand" "z")))]
2187 [(set_attr "type" "arith")
2188 (set_attr "in_delay_slot" "no")])
2190 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
2191 ;; hard register 0. If we used hard register 0, then the next instruction
2192 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
2193 ;; gets allocated to a stack slot that needs its address reloaded, then
2194 ;; there is nothing to prevent reload from using r0 to reload the address.
2195 ;; This reload would clobber the value in r0 we are trying to store.
2196 ;; If we let reload allocate r0, then this problem can never happen.
2197 (define_insn "udivsi3_i1"
2198 [(set (match_operand:SI 0 "register_operand" "=z,z")
2199 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2200 (clobber (reg:SI T_REG))
2201 (clobber (reg:SI PR_REG))
2202 (clobber (reg:SI R1_REG))
2203 (clobber (reg:SI R4_REG))
2204 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2205 (use (match_operand 2 "" "Z,Ccl"))]
2206 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2210 [(set_attr "type" "sfunc")
2211 (set_attr "needs_delay_slot" "yes")])
2213 (define_insn "udivsi3_i4"
2214 [(set (match_operand:SI 0 "register_operand" "=y,y")
2215 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2216 (clobber (reg:SI T_REG))
2217 (clobber (reg:SI PR_REG))
2218 (clobber (reg:DF DR0_REG))
2219 (clobber (reg:DF DR2_REG))
2220 (clobber (reg:DF DR4_REG))
2221 (clobber (reg:SI R0_REG))
2222 (clobber (reg:SI R1_REG))
2223 (clobber (reg:SI R4_REG))
2224 (clobber (reg:SI R5_REG))
2225 (clobber (reg:SI FPSCR_STAT_REG))
2226 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2227 (use (match_operand 2 "" "Z,Ccl"))
2228 (use (reg:SI FPSCR_MODES_REG))]
2229 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2233 [(set_attr "type" "sfunc")
2234 (set_attr "fp_mode" "double")
2235 (set_attr "needs_delay_slot" "yes")])
2237 (define_insn "udivsi3_i4_single"
2238 [(set (match_operand:SI 0 "register_operand" "=y,y")
2239 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2240 (clobber (reg:SI T_REG))
2241 (clobber (reg:SI PR_REG))
2242 (clobber (reg:DF DR0_REG))
2243 (clobber (reg:DF DR2_REG))
2244 (clobber (reg:DF DR4_REG))
2245 (clobber (reg:SI R0_REG))
2246 (clobber (reg:SI R1_REG))
2247 (clobber (reg:SI R4_REG))
2248 (clobber (reg:SI R5_REG))
2249 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2250 (use (match_operand 2 "" "Z,Ccl"))]
2251 "TARGET_FPU_ANY && TARGET_FPU_SINGLE"
2255 [(set_attr "type" "sfunc")
2256 (set_attr "needs_delay_slot" "yes")])
2258 (define_insn "udivsi3_i4_int"
2259 [(set (match_operand:SI 0 "register_operand" "=z")
2260 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2261 (clobber (reg:SI T_REG))
2262 (clobber (reg:SI R1_REG))
2263 (clobber (reg:SI PR_REG))
2264 (clobber (reg:SI MACH_REG))
2265 (clobber (reg:SI MACL_REG))
2266 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2269 [(set_attr "type" "sfunc")
2270 (set_attr "needs_delay_slot" "yes")])
2273 (define_expand "udivsi3"
2274 [(set (match_operand:SI 0 "register_operand")
2275 (udiv:SI (match_operand:SI 1 "general_operand")
2276 (match_operand:SI 2 "general_operand")))]
2281 operands[3] = gen_reg_rtx (Pmode);
2282 /* Emit the move of the address to a pseudo outside of the libcall. */
2283 if (TARGET_DIVIDE_CALL_TABLE)
2285 /* libgcc2:__udivmoddi4 is not supposed to use an actual division, since
2286 that causes problems when the divide code is supposed to come from a
2287 separate library. Division by zero is undefined, so dividing 1 can be
2288 implemented by comparing with the divisor. */
2289 if (operands[1] == const1_rtx && currently_expanding_to_rtl)
2291 rtx test = gen_rtx_GEU (VOIDmode, operands[1], operands[2]);
2292 emit_insn (gen_cstoresi4 (operands[0], test,
2293 operands[1], operands[2]));
2296 else if (operands[2] == const0_rtx)
2298 emit_move_insn (operands[0], operands[2]);
2301 function_symbol (operands[3], "__udivsi3_i4i", SFUNC_GOT);
2302 last = gen_udivsi3_i4_int (operands[0], operands[3]);
2304 else if (TARGET_DIVIDE_CALL_FP)
2306 rtx lab = function_symbol (operands[3], "__udivsi3_i4", SFUNC_STATIC).lab;
2307 if (TARGET_FPU_SINGLE)
2308 last = gen_udivsi3_i4_single (operands[0], operands[3], lab);
2310 last = gen_udivsi3_i4 (operands[0], operands[3], lab);
2312 else if (TARGET_SH2A)
2314 operands[1] = force_reg (SImode, operands[1]);
2315 operands[2] = force_reg (SImode, operands[2]);
2316 emit_insn (gen_udivsi3_sh2a (operands[0], operands[1], operands[2]));
2321 rtx lab = function_symbol (operands[3], "__udivsi3", SFUNC_STATIC).lab;
2322 last = gen_udivsi3_i1 (operands[0], operands[3], lab);
2324 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2325 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2330 (define_insn "divsi3_sh2a"
2331 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2332 (div:SI (match_operand:SI 1 "arith_reg_operand" "0")
2333 (match_operand:SI 2 "arith_reg_operand" "z")))]
2336 [(set_attr "type" "arith")
2337 (set_attr "in_delay_slot" "no")])
2339 (define_insn "divsi3_i1"
2340 [(set (match_operand:SI 0 "register_operand" "=z")
2341 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2342 (clobber (reg:SI T_REG))
2343 (clobber (reg:SI PR_REG))
2344 (clobber (reg:SI R1_REG))
2345 (clobber (reg:SI R2_REG))
2346 (clobber (reg:SI R3_REG))
2347 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2348 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2350 [(set_attr "type" "sfunc")
2351 (set_attr "needs_delay_slot" "yes")])
2353 (define_insn "divsi3_i4"
2354 [(set (match_operand:SI 0 "register_operand" "=y,y")
2355 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2356 (clobber (reg:SI PR_REG))
2357 (clobber (reg:DF DR0_REG))
2358 (clobber (reg:DF DR2_REG))
2359 (clobber (reg:SI FPSCR_STAT_REG))
2360 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2361 (use (match_operand 2 "" "Z,Ccl"))
2362 (use (reg:SI FPSCR_MODES_REG))]
2363 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2367 [(set_attr "type" "sfunc")
2368 (set_attr "fp_mode" "double")
2369 (set_attr "needs_delay_slot" "yes")])
2371 (define_insn "divsi3_i4_single"
2372 [(set (match_operand:SI 0 "register_operand" "=y,y")
2373 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2374 (clobber (reg:SI PR_REG))
2375 (clobber (reg:DF DR0_REG))
2376 (clobber (reg:DF DR2_REG))
2377 (clobber (reg:SI R2_REG))
2378 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2379 (use (match_operand 2 "" "Z,Ccl"))]
2380 "TARGET_FPU_ANY && TARGET_FPU_SINGLE"
2384 [(set_attr "type" "sfunc")
2385 (set_attr "needs_delay_slot" "yes")])
2387 (define_insn "divsi3_i4_int"
2388 [(set (match_operand:SI 0 "register_operand" "=z")
2389 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2390 (clobber (reg:SI T_REG))
2391 (clobber (reg:SI PR_REG))
2392 (clobber (reg:SI R1_REG))
2393 (clobber (reg:SI MACH_REG))
2394 (clobber (reg:SI MACL_REG))
2395 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2398 [(set_attr "type" "sfunc")
2399 (set_attr "needs_delay_slot" "yes")])
2401 (define_expand "divsi3"
2402 [(set (match_operand:SI 0 "register_operand")
2403 (div:SI (match_operand:SI 1 "general_operand")
2404 (match_operand:SI 2 "general_operand")))]
2409 operands[3] = gen_reg_rtx (Pmode);
2410 /* Emit the move of the address to a pseudo outside of the libcall. */
2411 if (TARGET_DIVIDE_CALL_TABLE)
2413 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2414 last = gen_divsi3_i4_int (operands[0], operands[3]);
2416 else if (TARGET_DIVIDE_CALL_FP)
2418 rtx lab = function_symbol (operands[3], sh_divsi3_libfunc,
2420 if (TARGET_FPU_SINGLE)
2421 last = gen_divsi3_i4_single (operands[0], operands[3], lab);
2423 last = gen_divsi3_i4 (operands[0], operands[3], lab);
2425 else if (TARGET_SH2A)
2427 operands[1] = force_reg (SImode, operands[1]);
2428 operands[2] = force_reg (SImode, operands[2]);
2429 emit_insn (gen_divsi3_sh2a (operands[0], operands[1], operands[2]));
2434 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2435 last = gen_divsi3_i1 (operands[0], operands[3]);
2437 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2438 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2444 ;; -------------------------------------------------------------------------
2445 ;; Multiplication instructions
2446 ;; -------------------------------------------------------------------------
2448 (define_insn_and_split "mulhisi3"
2449 [(set (match_operand:SI 0 "arith_reg_dest")
2450 (mult:SI (sign_extend:SI (match_operand:HI 1 "arith_reg_operand"))
2451 (sign_extend:SI (match_operand:HI 2 "arith_reg_operand"))))
2452 (clobber (reg:SI MACL_REG))]
2453 "TARGET_SH1 && can_create_pseudo_p ()"
2456 [(set (reg:SI MACL_REG) (mult:SI (sign_extend:SI (match_dup 1))
2457 (sign_extend:SI (match_dup 2))))
2458 (set (match_dup 0) (reg:SI MACL_REG))])
2460 (define_insn_and_split "umulhisi3"
2461 [(set (match_operand:SI 0 "arith_reg_dest")
2462 (mult:SI (zero_extend:SI (match_operand:HI 1 "arith_reg_operand"))
2463 (zero_extend:SI (match_operand:HI 2 "arith_reg_operand"))))
2464 (clobber (reg:SI MACL_REG))]
2465 "TARGET_SH1 && can_create_pseudo_p ()"
2468 [(set (reg:SI MACL_REG) (mult:SI (zero_extend:SI (match_dup 1))
2469 (zero_extend:SI (match_dup 2))))
2470 (set (match_dup 0) (reg:SI MACL_REG))])
2472 (define_insn "umulhisi3_i"
2473 [(set (reg:SI MACL_REG)
2474 (mult:SI (zero_extend:SI
2475 (match_operand:HI 0 "arith_reg_operand" "r"))
2477 (match_operand:HI 1 "arith_reg_operand" "r"))))]
2480 [(set_attr "type" "smpy")])
2482 (define_insn "mulhisi3_i"
2483 [(set (reg:SI MACL_REG)
2484 (mult:SI (sign_extend:SI
2485 (match_operand:HI 0 "arith_reg_operand" "r"))
2487 (match_operand:HI 1 "arith_reg_operand" "r"))))]
2490 [(set_attr "type" "smpy")])
2493 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
2494 ;; a call to a routine which clobbers known registers.
2495 (define_insn "mulsi3_call"
2496 [(set (match_operand:SI 1 "register_operand" "=z")
2497 (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2498 (clobber (reg:SI MACL_REG))
2499 (clobber (reg:SI T_REG))
2500 (clobber (reg:SI PR_REG))
2501 (clobber (reg:SI R3_REG))
2502 (clobber (reg:SI R2_REG))
2503 (clobber (reg:SI R1_REG))
2504 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
2507 [(set_attr "type" "sfunc")
2508 (set_attr "needs_delay_slot" "yes")])
2510 (define_insn "mul_r"
2511 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2512 (mult:SI (match_operand:SI 1 "arith_reg_operand" "0")
2513 (match_operand:SI 2 "arith_reg_operand" "z")))]
2516 [(set_attr "type" "dmpy")])
2518 (define_insn "mul_l"
2519 [(set (reg:SI MACL_REG)
2520 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
2521 (match_operand:SI 1 "arith_reg_operand" "r")))]
2524 [(set_attr "type" "dmpy")])
2526 (define_insn_and_split "mulsi3_i"
2527 [(set (match_operand:SI 0 "arith_reg_dest")
2528 (mult:SI (match_operand:SI 1 "arith_reg_operand")
2529 (match_operand:SI 2 "arith_reg_operand")))
2530 (clobber (reg:SI MACL_REG))]
2531 "TARGET_SH2 && can_create_pseudo_p ()"
2534 [(set (reg:SI MACL_REG) (mult:SI (match_dup 1) (match_dup 2)))
2535 (set (match_dup 0) (reg:SI MACL_REG))])
2537 (define_expand "mulsi3"
2538 [(set (match_operand:SI 0 "arith_reg_dest")
2539 (mult:SI (match_operand:SI 1 "arith_reg_operand")
2540 (match_operand:SI 2 "arith_reg_operand")))]
2545 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
2546 emit_move_insn (gen_rtx_REG (SImode, R5_REG), operands[2]);
2548 rtx sym = function_symbol (NULL, "__mulsi3", SFUNC_STATIC).sym;
2550 emit_insn (gen_mulsi3_call (force_reg (SImode, sym), operands[0]));
2554 /* FIXME: For some reason, expanding the mul_l insn and the macl store
2555 insn early gives slightly better code. In particular it prevents
2556 the decrement-test loop type to be used in some cases which saves
2557 one multiplication in the loop setup code.
2559 emit_insn (gen_mulsi3_i (operands[0], operands[1], operands[2]));
2562 emit_insn (gen_mul_l (operands[1], operands[2]));
2563 emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
2568 (define_insn "mulsidi3_i"
2569 [(set (reg:SI MACH_REG)
2573 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2574 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2576 (set (reg:SI MACL_REG)
2577 (mult:SI (match_dup 0)
2581 [(set_attr "type" "dmpy")])
2583 (define_expand "mulsidi3"
2584 [(set (match_operand:DI 0 "arith_reg_dest")
2585 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2586 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand"))))]
2589 emit_insn (gen_mulsidi3_compact (operands[0], operands[1], operands[2]));
2593 (define_insn_and_split "mulsidi3_compact"
2594 [(set (match_operand:DI 0 "arith_reg_dest")
2595 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2596 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand"))))
2597 (clobber (reg:SI MACH_REG))
2598 (clobber (reg:SI MACL_REG))]
2599 "TARGET_SH2 && can_create_pseudo_p ()"
2604 rtx low_dst = gen_lowpart (SImode, operands[0]);
2605 rtx high_dst = gen_highpart (SImode, operands[0]);
2607 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
2609 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
2610 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
2611 /* We need something to tag the possible REG_EQUAL notes on to. */
2612 emit_move_insn (operands[0], operands[0]);
2616 (define_insn "umulsidi3_i"
2617 [(set (reg:SI MACH_REG)
2621 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2622 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2624 (set (reg:SI MACL_REG)
2625 (mult:SI (match_dup 0)
2629 [(set_attr "type" "dmpy")])
2631 (define_expand "umulsidi3"
2632 [(set (match_operand:DI 0 "arith_reg_dest")
2633 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2634 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand"))))]
2637 emit_insn (gen_umulsidi3_compact (operands[0], operands[1], operands[2]));
2641 (define_insn_and_split "umulsidi3_compact"
2642 [(set (match_operand:DI 0 "arith_reg_dest")
2643 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2644 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand"))))
2645 (clobber (reg:SI MACH_REG))
2646 (clobber (reg:SI MACL_REG))]
2647 "TARGET_SH2 && can_create_pseudo_p ()"
2652 rtx low_dst = gen_lowpart (SImode, operands[0]);
2653 rtx high_dst = gen_highpart (SImode, operands[0]);
2655 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
2657 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
2658 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
2659 /* We need something to tag the possible REG_EQUAL notes on to. */
2660 emit_move_insn (operands[0], operands[0]);
2664 (define_insn "smulsi3_highpart_i"
2665 [(set (reg:SI MACH_REG)
2669 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2670 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2672 (clobber (reg:SI MACL_REG))]
2675 [(set_attr "type" "dmpy")])
2677 (define_insn_and_split "smulsi3_highpart"
2678 [(set (match_operand:SI 0 "arith_reg_dest")
2682 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2683 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand")))
2685 (clobber (reg:SI MACL_REG))
2686 (clobber (reg:SI MACH_REG))]
2687 "TARGET_SH2 && can_create_pseudo_p ()"
2692 emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
2693 emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
2696 (define_insn "umulsi3_highpart_i"
2697 [(set (reg:SI MACH_REG)
2701 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2702 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2704 (clobber (reg:SI MACL_REG))]
2707 [(set_attr "type" "dmpy")])
2709 (define_insn_and_split "umulsi3_highpart"
2710 [(set (match_operand:SI 0 "arith_reg_dest")
2714 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2715 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand")))
2717 (clobber (reg:SI MACL_REG))]
2718 "TARGET_SH2 && can_create_pseudo_p ()"
2723 emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
2724 emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
2727 ;; -------------------------------------------------------------------------
2728 ;; Logical operations
2729 ;; -------------------------------------------------------------------------
2731 (define_expand "andsi3"
2732 [(set (match_operand:SI 0 "arith_reg_dest")
2733 (and:SI (match_operand:SI 1 "arith_reg_operand")
2734 (match_operand:SI 2 "logical_and_operand")))]
2737 /* If it is possible to turn the and insn into a zero extension
2738 already, redundant zero extensions will be folded, which results
2740 Ideally the splitter of *andsi_compact would be enough, if redundant
2741 zero extensions were detected after the combine pass, which does not
2742 happen at the moment. */
2744 if (satisfies_constraint_Jmb (operands[2]))
2746 emit_insn (gen_zero_extendqisi2 (operands[0],
2747 gen_lowpart (QImode, operands[1])));
2750 else if (satisfies_constraint_Jmw (operands[2]))
2752 emit_insn (gen_zero_extendhisi2 (operands[0],
2753 gen_lowpart (HImode, operands[1])));
2758 (define_insn_and_split "*andsi_compact"
2759 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r,z,r")
2760 (and:SI (match_operand:SI 1 "arith_reg_operand" "%r,r,0,0")
2761 (match_operand:SI 2 "logical_and_operand" "Jmb,Jmw,K08,r")))]
2769 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
2771 if (satisfies_constraint_Jmb (operands[2]))
2772 operands[1] = gen_lowpart (QImode, operands[1]);
2773 else if (satisfies_constraint_Jmw (operands[2]))
2774 operands[1] = gen_lowpart (HImode, operands[1]);
2778 [(set_attr "type" "arith")])
2780 (define_insn "*andsi3_bclr"
2781 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2782 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0")
2783 (match_operand:SI 2 "const_int_operand" "Psz")))]
2784 "TARGET_SH2A && satisfies_constraint_Psz (operands[2])"
2786 [(set_attr "type" "arith")])
2788 (define_expand "iorsi3"
2789 [(set (match_operand:SI 0 "arith_reg_dest")
2790 (ior:SI (match_operand:SI 1 "arith_reg_operand")
2791 (match_operand:SI 2 "logical_operand")))])
2793 (define_insn "*iorsi3_compact"
2794 [(set (match_operand:SI 0 "arith_reg_dest" "=r,z")
2795 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
2796 (match_operand:SI 2 "logical_operand" "r,K08")))]
2798 && !(TARGET_SH2A && satisfies_constraint_Pso (operands[2]))"
2800 [(set_attr "type" "arith")])
2802 (define_insn "*iorsi3_bset"
2803 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2804 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0")
2805 (match_operand:SI 2 "const_int_operand" "Pso")))]
2806 "TARGET_SH2A && satisfies_constraint_Pso (operands[2])"
2808 [(set_attr "type" "arith")])
2810 (define_insn "xorsi3"
2811 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
2812 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
2813 (match_operand:SI 2 "logical_operand" "K08,r")))]
2816 [(set_attr "type" "arith")])
2818 ;; The *logical_op_t pattern helps combine eliminating sign/zero extensions
2819 ;; of results where one of the inputs is a T bit store. Notice that this
2820 ;; pattern must not match during reload. If reload picks this pattern it
2821 ;; will be impossible to split it afterwards.
2822 (define_insn_and_split "*logical_op_t"
2823 [(set (match_operand:SI 0 "arith_reg_dest")
2824 (match_operator:SI 3 "logical_operator"
2825 [(match_operand:SI 1 "arith_reg_operand")
2826 (match_operand:SI 2 "t_reg_operand")]))]
2827 "TARGET_SH1 && can_create_pseudo_p ()"
2830 [(set (match_dup 4) (reg:SI T_REG))
2831 (set (match_dup 0) (match_dup 3))]
2833 operands[4] = gen_reg_rtx (SImode);
2834 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2835 operands[1], operands[4]);
2838 ;; -------------------------------------------------------------------------
2839 ;; Shifts and rotates
2840 ;; -------------------------------------------------------------------------
2842 ;; Let combine see that we can get the MSB and LSB into the T bit
2843 ;; via shll and shlr. This allows it to plug it into insns that can have
2844 ;; the T bit as an input (e.g. addc).
2845 ;; On SH2A use bld #0,Rn instead of shlr to avoid mutating the input.
2846 (define_insn_and_split "*reg_lsb_t"
2847 [(set (reg:SI T_REG)
2848 (and:SI (match_operand:SI 0 "arith_reg_operand")
2850 "TARGET_SH1 && can_create_pseudo_p ()"
2855 emit_insn (TARGET_SH2A ? gen_bldsi_reg (operands[0], const0_rtx)
2856 : gen_shlr (gen_reg_rtx (SImode), operands[0]));
2859 (define_insn_and_split "*reg_msb_t"
2860 [(set (reg:SI T_REG)
2861 (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
2863 "TARGET_SH1 && can_create_pseudo_p ()"
2868 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
2871 (define_expand "rotrsi3"
2872 [(set (match_operand:SI 0 "arith_reg_dest")
2873 (rotatert:SI (match_operand:SI 1 "arith_reg_operand")
2874 (match_operand:SI 2 "const_int_operand")))]
2877 HOST_WIDE_INT ival = INTVAL (operands[2]);
2880 emit_insn (gen_rotrsi3_1 (operands[0], operands[1]));
2887 (define_insn "rotrsi3_1"
2888 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2889 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
2892 (and:SI (match_dup 1) (const_int 1)))]
2895 [(set_attr "type" "arith")])
2897 ;; A slimplified version of rotr for combine.
2898 (define_insn "*rotrsi3_1"
2899 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2900 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
2902 (clobber (reg:SI T_REG))]
2905 [(set_attr "type" "arith")])
2907 (define_insn "rotlsi3_1"
2908 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2909 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
2912 (lshiftrt:SI (match_dup 1) (const_int 31)))]
2915 [(set_attr "type" "arith")])
2917 ;; A simplified version of rotl for combine.
2918 (define_insn "*rotlsi3_1"
2919 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2920 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
2922 (clobber (reg:SI T_REG))]
2925 [(set_attr "type" "arith")])
2927 (define_insn "rotlsi3_31"
2928 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2929 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
2931 (clobber (reg:SI T_REG))]
2934 [(set_attr "type" "arith")])
2936 (define_insn "rotlsi3_16"
2937 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2938 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
2942 [(set_attr "type" "arith")])
2944 (define_expand "rotlsi3"
2945 [(set (match_operand:SI 0 "arith_reg_dest")
2946 (rotate:SI (match_operand:SI 1 "arith_reg_operand")
2947 (match_operand:SI 2 "const_int_operand")))]
2950 static const char rot_tab[] = {
2951 000, 000, 000, 000, 000, 000, 010, 001,
2952 001, 001, 011, 013, 003, 003, 003, 003,
2953 003, 003, 003, 003, 003, 013, 012, 002,
2954 002, 002, 010, 000, 000, 000, 000, 000,
2957 int count = INTVAL (operands[2]);
2958 int choice = rot_tab[count];
2959 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
2965 emit_move_insn (operands[0], operands[1]);
2966 count -= (count & 16) * 2;
2969 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
2976 parts[0] = gen_reg_rtx (SImode);
2977 parts[1] = gen_reg_rtx (SImode);
2978 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
2979 emit_move_insn (parts[choice-1], operands[1]);
2980 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
2981 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
2982 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
2983 count = (count & ~16) - 8;
2987 for (; count > 0; count--)
2988 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
2989 for (; count < 0; count++)
2990 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
2995 (define_insn "rotlhi3_8"
2996 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
2997 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
3001 [(set_attr "type" "arith")])
3003 (define_expand "rotlhi3"
3004 [(set (match_operand:HI 0 "arith_reg_operand")
3005 (rotate:HI (match_operand:HI 1 "arith_reg_operand")
3006 (match_operand:HI 2 "const_int_operand")))]
3009 if (INTVAL (operands[2]) != 8)
3013 ;; The rotcr and rotcl insns are used primarily in DImode shifts by one.
3014 ;; They can also be used to implement things like
3016 ;; int x0 = (y >> 1) | (t << 31); // rotcr
3017 ;; int x1 = (y << 1) | t; // rotcl
3018 (define_insn "rotcr"
3019 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3020 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3022 (ashift:SI (match_operand:SI 2 "t_reg_operand")
3025 (and:SI (match_dup 1) (const_int 1)))]
3028 [(set_attr "type" "arith")])
3030 (define_insn "rotcl"
3031 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3032 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
3034 (match_operand:SI 2 "t_reg_operand")))
3036 (lshiftrt:SI (match_dup 1) (const_int 31)))]
3039 [(set_attr "type" "arith")])
3041 ;; Simplified rotcr version for combine, which allows arbitrary shift
3042 ;; amounts for the reg. If the shift amount is '1' rotcr can be used
3043 ;; directly. Otherwise we have to insert a shift in between.
3044 (define_insn_and_split "*rotcr"
3045 [(set (match_operand:SI 0 "arith_reg_dest")
3046 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_or_0_operand")
3047 (match_operand:SI 2 "const_int_operand"))
3048 (ashift:SI (match_operand 3 "arith_reg_or_treg_set_expr")
3050 (clobber (reg:SI T_REG))]
3051 "TARGET_SH1 && can_create_pseudo_p ()"
3056 rtx_insn *prev_set_t_insn = NULL;
3058 if (!arith_reg_operand (operands[3], SImode))
3060 sh_treg_insns ti = sh_split_treg_set_expr (operands[3], curr_insn);
3061 if (!ti.was_treg_operand ())
3062 prev_set_t_insn = ti.first_insn ();
3064 operands[3] = get_t_reg_rtx ();
3066 if (TARGET_SH2A && ti.has_trailing_nott () && operands[1] == const0_rtx)
3068 /* Convert to a movrt, rotr sequence. */
3069 remove_insn (ti.trailing_nott ());
3070 rtx tmp = gen_reg_rtx (SImode);
3071 emit_insn (gen_movnegt (tmp, get_t_reg_rtx ()));
3072 emit_insn (gen_rotrsi3_1 (operands[0], tmp));
3077 if (operands[1] == const0_rtx)
3079 operands[1] = gen_reg_rtx (SImode);
3080 emit_insn (gen_movt (operands[1], get_t_reg_rtx ()));
3083 if (INTVAL (operands[2]) > 1)
3085 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
3086 rtx tmp_t_reg = NULL_RTX;
3088 /* If we're going to emit a shift sequence that clobbers the T_REG,
3089 try to find the previous insn that sets the T_REG and emit the
3090 shift insn before that insn, to remove the T_REG dependency.
3091 If the insn that sets the T_REG cannot be found, store the T_REG
3092 in a temporary reg and restore it after the shift. */
3093 if (sh_lshrsi_clobbers_t_reg_p (shift_count)
3094 && ! sh_dynamicalize_shift_p (shift_count))
3096 if (prev_set_t_insn == NULL)
3097 prev_set_t_insn = prev_nonnote_insn_bb (curr_insn);
3099 /* Skip the nott insn, which was probably inserted by the splitter
3100 of *rotcr_neg_t. Don't use one of the recog functions
3101 here during insn splitting, since that causes problems in later
3103 if (prev_set_t_insn != NULL_RTX)
3105 rtx pat = PATTERN (prev_set_t_insn);
3106 if (GET_CODE (pat) == SET
3107 && t_reg_operand (XEXP (pat, 0), SImode)
3108 && negt_reg_operand (XEXP (pat, 1), SImode))
3109 prev_set_t_insn = prev_nonnote_insn_bb (prev_set_t_insn);
3112 if (! (prev_set_t_insn != NULL_RTX
3113 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
3114 && ! reg_referenced_p (get_t_reg_rtx (),
3115 PATTERN (prev_set_t_insn))))
3117 prev_set_t_insn = NULL;
3118 tmp_t_reg = gen_reg_rtx (SImode);
3119 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
3123 rtx shift_result = gen_reg_rtx (SImode);
3124 rtx shift_insn = gen_lshrsi3 (shift_result, operands[1], shift_count);
3125 operands[1] = shift_result;
3127 /* Emit the shift insn before the insn that sets T_REG, if possible. */
3128 if (prev_set_t_insn != NULL_RTX)
3129 emit_insn_before (shift_insn, prev_set_t_insn);
3131 emit_insn (shift_insn);
3133 /* Restore T_REG if it has been saved before. */
3134 if (tmp_t_reg != NULL_RTX)
3135 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
3138 /* For the rotcr insn to work, operands[3] must be in T_REG.
3139 If it is not we can get it there by shifting it right one bit.
3140 In this case T_REG is not an input for this insn, thus we don't have to
3141 pay attention as of where to insert the shlr insn. */
3142 if (! t_reg_operand (operands[3], SImode))
3144 /* We don't care about the shifted result here, only the T_REG. */
3145 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
3146 operands[3] = get_t_reg_rtx ();
3149 emit_insn (gen_rotcr (operands[0], operands[1], operands[3]));
3153 ;; If combine tries the same as above but with swapped operands, split
3154 ;; it so that it will try the pattern above.
3156 [(set (match_operand:SI 0 "arith_reg_dest")
3157 (ior:SI (ashift:SI (match_operand 1 "arith_reg_or_treg_set_expr")
3159 (lshiftrt:SI (match_operand:SI 2 "arith_reg_or_0_operand")
3160 (match_operand:SI 3 "const_int_operand"))))]
3161 "TARGET_SH1 && can_create_pseudo_p ()"
3162 [(parallel [(set (match_dup 0)
3163 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
3164 (ashift:SI (match_dup 1) (const_int 31))))
3165 (clobber (reg:SI T_REG))])])
3167 ;; Basically the same as the rotcr pattern above, but for rotcl.
3168 ;; FIXME: Fold copy pasted split code for rotcr and rotcl.
3169 (define_insn_and_split "*rotcl"
3170 [(set (match_operand:SI 0 "arith_reg_dest")
3171 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3172 (match_operand:SI 2 "const_int_operand"))
3173 (and:SI (match_operand:SI 3 "arith_reg_or_t_reg_operand")
3175 (clobber (reg:SI T_REG))]
3178 "&& can_create_pseudo_p ()"
3181 gcc_assert (INTVAL (operands[2]) > 0);
3183 if (INTVAL (operands[2]) > 1)
3185 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
3186 rtx_insn *prev_set_t_insn = NULL;
3187 rtx tmp_t_reg = NULL_RTX;
3189 /* If we're going to emit a shift sequence that clobbers the T_REG,
3190 try to find the previous insn that sets the T_REG and emit the
3191 shift insn before that insn, to remove the T_REG dependency.
3192 If the insn that sets the T_REG cannot be found, store the T_REG
3193 in a temporary reg and restore it after the shift. */
3194 if (sh_ashlsi_clobbers_t_reg_p (shift_count)
3195 && ! sh_dynamicalize_shift_p (shift_count))
3197 prev_set_t_insn = prev_nonnote_insn_bb (curr_insn);
3199 /* Skip the nott insn, which was probably inserted by the splitter
3200 of *rotcl_neg_t. Don't use one of the recog functions
3201 here during insn splitting, since that causes problems in later
3203 if (prev_set_t_insn != NULL_RTX)
3205 rtx pat = PATTERN (prev_set_t_insn);
3206 if (GET_CODE (pat) == SET
3207 && t_reg_operand (XEXP (pat, 0), SImode)
3208 && negt_reg_operand (XEXP (pat, 1), SImode))
3209 prev_set_t_insn = prev_nonnote_insn_bb (prev_set_t_insn);
3212 if (! (prev_set_t_insn != NULL_RTX
3213 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
3214 && ! reg_referenced_p (get_t_reg_rtx (),
3215 PATTERN (prev_set_t_insn))))
3217 prev_set_t_insn = NULL;
3218 tmp_t_reg = gen_reg_rtx (SImode);
3219 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
3223 rtx shift_result = gen_reg_rtx (SImode);
3224 rtx shift_insn = gen_ashlsi3 (shift_result, operands[1], shift_count);
3225 operands[1] = shift_result;
3227 /* Emit the shift insn before the insn that sets T_REG, if possible. */
3228 if (prev_set_t_insn != NULL_RTX)
3229 emit_insn_before (shift_insn, prev_set_t_insn);
3231 emit_insn (shift_insn);
3233 /* Restore T_REG if it has been saved before. */
3234 if (tmp_t_reg != NULL_RTX)
3235 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
3238 /* For the rotcl insn to work, operands[3] must be in T_REG.
3239 If it is not we can get it there by shifting it right one bit.
3240 In this case T_REG is not an input for this insn, thus we don't have to
3241 pay attention as of where to insert the shlr insn. */
3242 if (! t_reg_operand (operands[3], SImode))
3244 /* We don't care about the shifted result here, only the T_REG. */
3245 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
3246 operands[3] = get_t_reg_rtx ();
3249 emit_insn (gen_rotcl (operands[0], operands[1], operands[3]));
3253 ;; rotcl combine pattern variations
3254 (define_insn_and_split "*rotcl"
3255 [(set (match_operand:SI 0 "arith_reg_dest")
3256 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3257 (match_operand:SI 2 "const_int_operand"))
3258 (match_operand 3 "treg_set_expr")))
3259 (clobber (reg:SI T_REG))]
3262 "&& can_create_pseudo_p ()"
3263 [(parallel [(set (match_dup 0)
3264 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
3265 (and:SI (match_dup 3) (const_int 1))))
3266 (clobber (reg:SI T_REG))])]
3268 sh_split_treg_set_expr (operands[3], curr_insn);
3269 operands[3] = get_t_reg_rtx ();
3272 (define_insn_and_split "*rotcl"
3273 [(set (match_operand:SI 0 "arith_reg_dest")
3274 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_or_t_reg_operand")
3276 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
3277 (match_operand:SI 3 "const_int_operand"))))
3278 (clobber (reg:SI T_REG))]
3281 "&& can_create_pseudo_p ()"
3282 [(parallel [(set (match_dup 0)
3283 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
3284 (and:SI (match_dup 1) (const_int 1))))
3285 (clobber (reg:SI T_REG))])])
3287 (define_insn_and_split "*rotcl"
3288 [(set (match_operand:SI 0 "arith_reg_dest")
3289 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3290 (match_operand:SI 2 "const_int_operand"))
3291 (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
3293 (clobber (reg:SI T_REG))]
3296 "&& can_create_pseudo_p ()"
3297 [(parallel [(set (match_dup 0)
3298 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
3299 (and:SI (reg:SI T_REG) (const_int 1))))
3300 (clobber (reg:SI T_REG))])]
3302 /* We don't care about the result of the left shift, only the T_REG. */
3303 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
3306 (define_insn_and_split "*rotcl"
3307 [(set (match_operand:SI 0 "arith_reg_dest")
3308 (ior:SI (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
3310 (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3311 (match_operand:SI 2 "const_int_operand"))))
3312 (clobber (reg:SI T_REG))]
3315 "&& can_create_pseudo_p ()"
3316 [(parallel [(set (match_dup 0)
3317 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
3318 (and:SI (reg:SI T_REG) (const_int 1))))
3319 (clobber (reg:SI T_REG))])]
3321 /* We don't care about the result of the left shift, only the T_REG. */
3322 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
3325 (define_insn_and_split "*rotcl"
3326 [(set (match_operand:SI 0 "arith_reg_dest")
3327 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3328 (match_operand 2 "const_int_operand"))
3329 (zero_extract:SI (match_operand:SI 3 "arith_reg_operand")
3331 (match_operand 4 "const_int_operand"))))
3332 (clobber (reg:SI T_REG))]
3335 "&& can_create_pseudo_p ()"
3336 [(parallel [(set (match_dup 0)
3337 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
3338 (and:SI (match_dup 5) (const_int 1))))
3339 (clobber (reg:SI T_REG))])]
3341 if (TARGET_SH2A && satisfies_constraint_K03 (operands[4]))
3343 /* On SH2A we can use the bld insn to zero extract a single bit
3345 operands[5] = get_t_reg_rtx ();
3346 emit_insn (gen_bldsi_reg (operands[3], operands[4]));
3350 /* If we can't use the bld insn we have to emit a tst + nott sequence
3351 to get the extracted bit into the T bit.
3352 This will probably be worse than pre-shifting the operand. */
3353 operands[5] = gen_reg_rtx (SImode);
3354 emit_insn (gen_lshrsi3 (operands[5], operands[3], operands[4]));
3358 ;; rotcr combine bridge pattern which will make combine try out more
3359 ;; complex patterns.
3360 (define_insn_and_split "*rotcr"
3361 [(set (match_operand:SI 0 "arith_reg_dest")
3362 (ashift:SI (match_operand 1 "treg_set_expr") (const_int 31)))]
3363 "TARGET_SH1 && can_create_pseudo_p ()"
3366 [(parallel [(set (match_dup 0)
3367 (ior:SI (lshiftrt:SI (const_int 0) (const_int 1))
3368 (ashift:SI (match_dup 1) (const_int 31))))
3369 (clobber (reg:SI T_REG))])])
3371 (define_insn_and_split "*rotcr"
3372 [(set (match_operand:SI 0 "arith_reg_dest")
3373 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
3374 (const_int -2147483648)) ;; 0xffffffff80000000
3375 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
3377 (clobber (reg:SI T_REG))]
3380 "&& can_create_pseudo_p ()"
3383 rtx tmp = gen_reg_rtx (SImode);
3384 emit_insn (gen_shll (tmp, operands[1]));
3385 emit_insn (gen_rotcr (operands[0], operands[2], get_t_reg_rtx ()));
3389 (define_insn_and_split "*rotcr"
3390 [(set (match_operand:SI 0 "arith_reg_dest")
3391 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
3393 (const_int -2147483648))) ;; 0xffffffff80000000
3394 (clobber (reg:SI T_REG))]
3397 "&& can_create_pseudo_p ()"
3400 emit_insn (gen_sett ());
3401 emit_insn (gen_rotcr (operands[0], operands[1], get_t_reg_rtx ()));
3405 ;; rotcr combine patterns for rotating in the negated T_REG value.
3406 (define_insn_and_split "*rotcr_neg_t"
3407 [(set (match_operand:SI 0 "arith_reg_dest")
3408 (ior:SI (match_operand:SI 1 "negt_reg_shl31_operand")
3409 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
3410 (match_operand:SI 3 "const_int_operand"))))
3411 (clobber (reg:SI T_REG))]
3414 "&& can_create_pseudo_p ()"
3415 [(parallel [(set (match_dup 0)
3416 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
3417 (ashift:SI (reg:SI T_REG) (const_int 31))))
3418 (clobber (reg:SI T_REG))])]
3420 emit_insn (gen_nott (get_t_reg_rtx ()));
3423 (define_insn_and_split "*rotcr_neg_t"
3424 [(set (match_operand:SI 0 "arith_reg_dest")
3425 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
3426 (match_operand:SI 2 "const_int_operand"))
3427 (match_operand:SI 3 "negt_reg_shl31_operand")))
3428 (clobber (reg:SI T_REG))]
3431 "&& can_create_pseudo_p ()"
3432 [(parallel [(set (match_dup 0)
3433 (ior:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
3434 (ashift:SI (reg:SI T_REG) (const_int 31))))
3435 (clobber (reg:SI T_REG))])]
3437 emit_insn (gen_nott (get_t_reg_rtx ()));
3440 ;; rotcl combine patterns for rotating in the negated T_REG value.
3441 ;; For some strange reason these have to be specified as splits which combine
3442 ;; will pick up. If they are specified as insn_and_split like the
3443 ;; *rotcr_neg_t patterns above, combine would recognize them successfully
3444 ;; but not emit them on non-SH2A targets.
3446 [(set (match_operand:SI 0 "arith_reg_dest")
3447 (ior:SI (match_operand:SI 1 "negt_reg_operand")
3448 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
3449 (match_operand:SI 3 "const_int_operand"))))]
3451 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
3452 (parallel [(set (match_dup 0)
3453 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
3454 (and:SI (reg:SI T_REG) (const_int 1))))
3455 (clobber (reg:SI T_REG))])])
3458 [(set (match_operand:SI 0 "arith_reg_dest")
3459 (ior:SI (ashift:SI (match_operand:SI 2 "arith_reg_operand")
3460 (match_operand:SI 3 "const_int_operand"))
3461 (match_operand:SI 1 "negt_reg_operand")))]
3463 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
3464 (parallel [(set (match_dup 0)
3465 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
3466 (and:SI (reg:SI T_REG) (const_int 1))))
3467 (clobber (reg:SI T_REG))])])
3469 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3470 ;; SImode shift left
3472 (define_expand "ashlsi3"
3473 [(set (match_operand:SI 0 "arith_reg_operand" "")
3474 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
3475 (match_operand:SI 2 "shift_count_operand" "")))]
3479 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
3481 /* Don't force the constant into a reg yet. Some other optimizations
3482 might not see through the reg that holds the shift count. */
3485 /* If the ashlsi3_* insn is going to clobber the T_REG it must be
3487 if (CONST_INT_P (operands[2])
3488 && sh_ashlsi_clobbers_t_reg_p (operands[2])
3489 && ! sh_dynamicalize_shift_p (operands[2]))
3491 emit_insn (gen_ashlsi3_n_clobbers_t (operands[0], operands[1],
3496 /* Expand a library call for the dynamic shift. */
3497 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
3499 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
3500 rtx funcaddr = gen_reg_rtx (Pmode);
3501 rtx lab = function_symbol (funcaddr, "__ashlsi3_r0", SFUNC_STATIC).lab;
3502 emit_insn (gen_ashlsi3_d_call (operands[0], operands[2], funcaddr, lab));
3508 (define_insn "ashlsi3_k"
3509 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3510 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
3511 (match_operand:SI 2 "p27_shift_count_operand" "M,P27")))]
3516 [(set_attr "type" "arith")])
3518 (define_insn_and_split "ashlsi3_d"
3519 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3520 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
3521 (match_operand:SI 2 "shift_count_operand" "r")))]
3524 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
3525 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
3528 if (satisfies_constraint_P27 (operands[2]))
3530 emit_insn (gen_ashlsi3_k (operands[0], operands[1], operands[2]));
3533 else if (! satisfies_constraint_P27 (operands[2]))
3535 /* This must happen before reload, otherwise the constant will be moved
3536 into a register due to the "r" constraint, after which this split
3537 cannot be done anymore.
3538 Unfortunately the move insn will not always be eliminated.
3539 Also, here we must not create a shift sequence that clobbers the
3541 emit_move_insn (operands[0], operands[1]);
3542 gen_shifty_op (ASHIFT, operands);
3548 [(set_attr "type" "dyn_shift")])
3550 ;; If dynamic shifts are not available use a library function.
3551 ;; By specifying the pattern we reduce the number of call clobbered regs.
3552 ;; In order to make combine understand the truncation of the shift amount
3553 ;; operand we have to allow it to use pseudo regs for the shift operands.
3554 (define_insn "ashlsi3_d_call"
3555 [(set (match_operand:SI 0 "arith_reg_dest" "=z,z")
3556 (ashift:SI (reg:SI R4_REG)
3557 (and:SI (match_operand:SI 1 "arith_reg_operand" "z,z")
3559 (use (match_operand:SI 2 "arith_reg_operand" "r,r"))
3560 (use (match_operand 3 "" "Z,Ccl"))
3561 (clobber (reg:SI T_REG))
3562 (clobber (reg:SI PR_REG))]
3563 "TARGET_SH1 && !TARGET_DYNSHIFT"
3567 [(set_attr "type" "sfunc")
3568 (set_attr "needs_delay_slot" "yes")])
3570 (define_insn_and_split "ashlsi3_n"
3571 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3572 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
3573 (match_operand:SI 2 "not_p27_shift_count_operand" "")))]
3574 "TARGET_SH1 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
3576 "&& (reload_completed
3577 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
3580 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
3582 /* If this pattern was picked and dynamic shifts are supported, switch
3583 to dynamic shift pattern before reload. */
3584 operands[2] = force_reg (SImode, operands[2]);
3585 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
3588 gen_shifty_op (ASHIFT, operands);
3593 (define_insn_and_split "ashlsi3_n_clobbers_t"
3594 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3595 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
3596 (match_operand:SI 2 "not_p27_shift_count_operand" "")))
3597 (clobber (reg:SI T_REG))]
3598 "TARGET_SH1 && sh_ashlsi_clobbers_t_reg_p (operands[2])"
3600 "&& (reload_completed || INTVAL (operands[2]) == 31
3601 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
3604 if (INTVAL (operands[2]) == 31)
3606 /* If the shift amount is 31 we split into a different sequence before
3607 reload so that it gets a chance to allocate R0 for the sequence.
3608 If it fails to do so (due to pressure on R0), it will take one insn
3609 more for the and. */
3610 emit_insn (gen_andsi3 (operands[0], operands[1], const1_rtx));
3611 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
3613 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
3615 /* If this pattern was picked and dynamic shifts are supported, switch
3616 to dynamic shift pattern before reload. */
3617 operands[2] = force_reg (SImode, operands[2]);
3618 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
3621 gen_shifty_op (ASHIFT, operands);
3627 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3628 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
3630 (lt:SI (match_dup 1) (const_int 0)))]
3633 [(set_attr "type" "arith")])
3635 (define_insn "*ashlsi_c_void"
3636 [(set (reg:SI T_REG)
3637 (lt:SI (match_operand:SI 0 "arith_reg_operand" "r") (const_int 0)))
3638 (clobber (match_scratch:SI 1 "=0"))]
3639 "TARGET_SH1 && cse_not_expected"
3641 [(set_attr "type" "arith")])
3644 [(set (match_operand:SI 0 "arith_reg_dest" "") (const_int 0))
3646 (gt:SI (match_dup 0) (match_operand:SI 1 "arith_reg_operand" "")))]
3648 && peep2_reg_dead_p (2, operands[0])
3649 && peep2_reg_dead_p (2, operands[1])"
3652 emit_insn (gen_shll (operands[1], operands[1]));
3656 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3657 ;; HImode shift left
3659 (define_expand "ashlhi3"
3660 [(parallel [(set (match_operand:HI 0 "arith_reg_operand" "")
3661 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
3662 (match_operand:SI 2 "nonmemory_operand" "")))
3663 (clobber (reg:SI T_REG))])]
3666 if (!CONST_INT_P (operands[2]))
3668 /* It may be possible to call gen_ashlhi3 directly with more generic
3669 operands. Make sure operands[1] is a HImode register here. */
3670 if (!arith_reg_operand (operands[1], HImode))
3671 operands[1] = copy_to_mode_reg (HImode, operands[1]);
3674 (define_insn "ashlhi3_k"
3675 [(set (match_operand:HI 0 "arith_reg_dest" "=r,r")
3676 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
3677 (match_operand:HI 2 "const_int_operand" "M,P27")))]
3678 "TARGET_SH1 && satisfies_constraint_P27 (operands[2])"
3682 [(set_attr "type" "arith")])
3684 (define_insn_and_split "*ashlhi3_n"
3685 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
3686 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
3687 (match_operand:HI 2 "const_int_operand" "n")))
3688 (clobber (reg:SI T_REG))]
3691 "&& reload_completed"
3692 [(use (reg:SI R0_REG))]
3694 gen_shifty_hi_op (ASHIFT, operands);
3698 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3699 ;; DImode shift left
3701 (define_expand "ashldi3"
3702 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
3703 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
3704 (match_operand:DI 2 "immediate_operand" "")))
3705 (clobber (reg:SI T_REG))])]
3708 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
3710 emit_insn (gen_ashldi3_k (operands[0], operands[1]));
3713 else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 32)
3715 emit_insn (gen_ashldi3_std (operands[0], operands[1], operands[2]));
3722 ;; Expander for DImode shift left with SImode operations.
3723 (define_expand "ashldi3_std"
3724 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3725 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
3726 (match_operand:DI 2 "const_int_operand" "n")))]
3727 "TARGET_SH1 && INTVAL (operands[2]) < 32"
3729 rtx low_src = gen_lowpart (SImode, operands[1]);
3730 rtx high_src = gen_highpart (SImode, operands[1]);
3731 rtx dst = gen_reg_rtx (DImode);
3732 rtx low_dst = gen_lowpart (SImode, dst);
3733 rtx high_dst = gen_highpart (SImode, dst);
3734 rtx tmp0 = gen_reg_rtx (SImode);
3735 rtx tmp1 = gen_reg_rtx (SImode);
3737 emit_insn (gen_lshrsi3 (tmp0, low_src, GEN_INT (32 - INTVAL (operands[2]))));
3738 emit_insn (gen_ashlsi3 (low_dst, low_src, operands[2]));
3739 emit_insn (gen_ashlsi3 (tmp1, high_src, operands[2]));
3740 emit_insn (gen_iorsi3 (high_dst, tmp0, tmp1));
3741 emit_move_insn (operands[0], dst);
3745 (define_insn_and_split "ashldi3_k"
3746 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3747 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
3749 (clobber (reg:SI T_REG))]
3752 "&& reload_completed"
3755 rtx high = gen_highpart (SImode, operands[0]);
3756 rtx low = gen_lowpart (SImode, operands[0]);
3757 emit_insn (gen_shll (low, low));
3758 emit_insn (gen_rotcl (high, high, get_t_reg_rtx ()));
3762 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3763 ;; SImode arithmetic shift right
3765 ;; We can't do HImode right shifts correctly unless we start out with an
3766 ;; explicit zero / sign extension; doing that would result in worse overall
3767 ;; code, so just let the machine independent code widen the mode.
3768 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
3770 (define_expand "ashrsi3"
3771 [(parallel [(set (match_operand:SI 0 "arith_reg_dest" "")
3772 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
3773 (match_operand:SI 2 "nonmemory_operand" "")))
3774 (clobber (reg:SI T_REG))])]
3777 if (expand_ashiftrt (operands))
3784 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3785 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3788 (and:SI (match_dup 1) (const_int 1)))]
3791 [(set_attr "type" "arith")])
3793 (define_insn "ashrsi3_k"
3794 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3795 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3796 (match_operand:SI 2 "const_int_operand" "M")))
3797 (clobber (reg:SI T_REG))]
3798 "TARGET_SH1 && INTVAL (operands[2]) == 1"
3800 [(set_attr "type" "arith")])
3802 (define_insn_and_split "ashrsi2_16"
3803 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3804 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
3809 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
3810 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
3812 operands[2] = gen_lowpart (HImode, operands[0]);
3815 (define_insn_and_split "ashrsi2_31"
3816 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3817 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3819 (clobber (reg:SI T_REG))]
3825 emit_insn (gen_shll (operands[0], operands[1]));
3826 emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ()));
3830 ;; If the shift amount is changed by combine it will try to plug the
3831 ;; use on the symbol of the library function and the PR clobber.
3832 (define_insn_and_split "*ashrsi2_31"
3833 [(set (match_operand:SI 0 "arith_reg_dest")
3834 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand")
3836 (clobber (reg:SI T_REG))
3837 (clobber (reg:SI PR_REG))
3838 (use (match_operand:SI 2 "symbol_ref_operand"))]
3842 [(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))
3843 (clobber (reg:SI T_REG))])])
3845 (define_insn "ashrsi3_d"
3846 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3847 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3848 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
3851 [(set_attr "type" "dyn_shift")])
3853 (define_insn "ashrsi3_n"
3854 [(set (reg:SI R4_REG)
3855 (ashiftrt:SI (reg:SI R4_REG)
3856 (match_operand:SI 0 "const_int_operand" "i,i")))
3857 (clobber (reg:SI T_REG))
3858 (clobber (reg:SI PR_REG))
3859 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
3860 (use (match_operand 2 "" "Z,Ccl"))]
3865 [(set_attr "type" "sfunc")
3866 (set_attr "needs_delay_slot" "yes")])
3868 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3869 ;; DImode arithmetic shift right
3871 (define_expand "ashrdi3"
3872 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
3873 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
3874 (match_operand:DI 2 "immediate_operand" "")))
3875 (clobber (reg:SI T_REG))])]
3878 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
3882 (define_insn_and_split "ashrdi3_k"
3883 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3884 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
3886 (clobber (reg:SI T_REG))]
3889 "&& reload_completed"
3892 rtx high = gen_highpart (SImode, operands[0]);
3893 rtx low = gen_lowpart (SImode, operands[0]);
3894 emit_insn (gen_shar (high, high));
3895 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
3899 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3900 ;; SImode logical shift right
3902 (define_expand "lshrsi3"
3903 [(set (match_operand:SI 0 "arith_reg_dest" "")
3904 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
3905 (match_operand:SI 2 "shift_count_operand" "")))]
3908 /* If a dynamic shift is supposed to be used, expand the lshrsi3_d insn
3909 here, otherwise the pattern will never match due to the shift amount reg
3912 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
3914 /* Don't force the constant into a reg yet. Some other optimizations
3915 might not see through the reg that holds the shift count. */
3916 if (sh_lshrsi_clobbers_t_reg_p (operands[2]))
3917 emit_insn (gen_lshrsi3_n_clobbers_t (operands[0], operands[1], operands[2]));
3919 emit_insn (gen_lshrsi3_n (operands[0], operands[1], operands[2]));
3923 if (TARGET_DYNSHIFT && ! CONST_INT_P (operands[2]))
3925 rtx neg_count = gen_reg_rtx (SImode);
3926 emit_insn (gen_negsi2 (neg_count, operands[2]));
3927 emit_insn (gen_lshrsi3_d (operands[0], operands[1], neg_count));
3931 /* If the lshrsi3_* insn is going to clobber the T_REG it must be
3933 if (CONST_INT_P (operands[2])
3934 && sh_lshrsi_clobbers_t_reg_p (operands[2])
3935 && ! sh_dynamicalize_shift_p (operands[2]))
3937 emit_insn (gen_lshrsi3_n_clobbers_t (operands[0], operands[1],
3942 /* Expand a library call for the dynamic shift. */
3943 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
3945 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
3946 rtx funcaddr = gen_reg_rtx (Pmode);
3947 rtx lab = function_symbol (funcaddr, "__lshrsi3_r0", SFUNC_STATIC).lab;
3948 emit_insn (gen_lshrsi3_d_call (operands[0], operands[2], funcaddr, lab));
3953 (define_insn "lshrsi3_k"
3954 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3955 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3956 (match_operand:SI 2 "p27_rshift_count_operand" "P27")))]
3959 [(set_attr "type" "arith")])
3961 (define_insn_and_split "lshrsi3_d"
3962 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3963 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3964 (neg:SI (match_operand:SI 2 "shift_count_operand" "r"))))]
3967 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
3968 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
3971 /* The shift count const_int is a negative value for all dynamic
3972 right shift insns. */
3973 operands[2] = GEN_INT (- INTVAL (operands[2]));
3975 if (satisfies_constraint_P27 (operands[2]))
3977 /* This will not be done for a shift amount of 1, because it would
3978 clobber the T_REG. */
3979 emit_insn (gen_lshrsi3_k (operands[0], operands[1], operands[2]));
3982 else if (! satisfies_constraint_P27 (operands[2]))
3984 /* This must happen before reload, otherwise the constant will be moved
3985 into a register due to the "r" constraint, after which this split
3986 cannot be done anymore.
3987 Unfortunately the move insn will not always be eliminated.
3988 Also, here we must not create a shift sequence that clobbers the
3990 emit_move_insn (operands[0], operands[1]);
3991 gen_shifty_op (LSHIFTRT, operands);
3997 [(set_attr "type" "dyn_shift")])
3999 ;; If dynamic shifts are not available use a library function.
4000 ;; By specifying the pattern we reduce the number of call clobbered regs.
4001 ;; In order to make combine understand the truncation of the shift amount
4002 ;; operand we have to allow it to use pseudo regs for the shift operands.
4003 (define_insn "lshrsi3_d_call"
4004 [(set (match_operand:SI 0 "arith_reg_dest" "=z,z")
4005 (lshiftrt:SI (reg:SI R4_REG)
4006 (and:SI (match_operand:SI 1 "arith_reg_operand" "z,z")
4008 (use (match_operand:SI 2 "arith_reg_operand" "r,r"))
4009 (use (match_operand 3 "" "Z,Ccl"))
4010 (clobber (reg:SI T_REG))
4011 (clobber (reg:SI PR_REG))]
4012 "TARGET_SH1 && !TARGET_DYNSHIFT"
4016 [(set_attr "type" "sfunc")
4017 (set_attr "needs_delay_slot" "yes")])
4019 (define_insn_and_split "lshrsi3_n"
4020 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4021 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4022 (match_operand:SI 2 "not_p27_rshift_count_operand")))]
4023 "TARGET_SH1 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
4025 "&& (reload_completed
4026 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
4029 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
4031 /* If this pattern was picked and dynamic shifts are supported, switch
4032 to dynamic shift pattern before reload. */
4033 operands[2] = GEN_INT (- INTVAL (operands[2]));
4034 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
4037 gen_shifty_op (LSHIFTRT, operands);
4042 ;; The lshrsi3_n_clobbers_t pattern also works as a simplified version of
4043 ;; the shlr pattern.
4044 (define_insn_and_split "lshrsi3_n_clobbers_t"
4045 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4046 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4047 (match_operand:SI 2 "not_p27_rshift_count_operand")))
4048 (clobber (reg:SI T_REG))]
4049 "TARGET_SH1 && sh_lshrsi_clobbers_t_reg_p (operands[2])"
4051 "&& (reload_completed || INTVAL (operands[2]) == 31
4052 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
4055 if (INTVAL (operands[2]) == 31)
4057 emit_insn (gen_shll (operands[0], operands[1]));
4058 emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
4060 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
4062 /* If this pattern was picked and dynamic shifts are supported, switch
4063 to dynamic shift pattern before reload. */
4064 operands[2] = GEN_INT (- INTVAL (operands[2]));
4065 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
4068 gen_shifty_op (LSHIFTRT, operands);
4074 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4075 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4078 (and:SI (match_dup 1) (const_int 1)))]
4081 [(set_attr "type" "arith")])
4083 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4084 ;; DImode logical shift right
4086 (define_expand "lshrdi3"
4087 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
4088 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
4089 (match_operand:DI 2 "immediate_operand" "")))
4090 (clobber (reg:SI T_REG))])]
4093 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
4097 (define_insn_and_split "lshrdi3_k"
4098 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4099 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
4101 (clobber (reg:SI T_REG))]
4104 "&& reload_completed"
4107 rtx high = gen_highpart (SImode, operands[0]);
4108 rtx low = gen_lowpart (SImode, operands[0]);
4109 emit_insn (gen_shlr (high, high));
4110 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
4114 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4115 ;; Combined left/right shifts
4118 [(set (match_operand:SI 0 "register_operand" "")
4119 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4120 (match_operand:SI 2 "const_int_operand" ""))
4121 (match_operand:SI 3 "const_int_operand" "")))]
4122 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
4123 [(use (reg:SI R0_REG))]
4125 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
4131 [(set (match_operand:SI 0 "register_operand" "")
4132 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4133 (match_operand:SI 2 "const_int_operand" ""))
4134 (match_operand:SI 3 "const_int_operand" "")))
4135 (clobber (reg:SI T_REG))]
4136 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
4137 [(use (reg:SI R0_REG))]
4139 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
4145 [(set (match_operand:SI 0 "register_operand" "=r")
4146 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
4147 (match_operand:SI 2 "const_int_operand" "n"))
4148 (match_operand:SI 3 "const_int_operand" "n")))
4149 (clobber (reg:SI T_REG))]
4150 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 1"
4152 [(set (attr "length")
4153 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
4155 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
4157 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
4159 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
4161 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
4163 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
4165 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
4166 (const_string "16")]
4167 (const_string "18")))
4168 (set_attr "type" "arith")])
4171 [(set (match_operand:SI 0 "register_operand" "=z")
4172 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
4173 (match_operand:SI 2 "const_int_operand" "n"))
4174 (match_operand:SI 3 "const_int_operand" "n")))
4175 (clobber (reg:SI T_REG))]
4176 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 2"
4178 [(set (attr "length")
4179 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
4181 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
4183 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
4185 (const_string "10")))
4186 (set_attr "type" "arith")])
4188 ;; shift left / and combination with a scratch register: The combine pass
4189 ;; does not accept the individual instructions, even though they are
4190 ;; cheap. But it needs a precise description so that it is usable after
4192 (define_insn "and_shl_scratch"
4193 [(set (match_operand:SI 0 "register_operand" "=r,&r")
4197 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
4198 (match_operand:SI 2 "const_int_operand" "N,n"))
4199 (match_operand:SI 3 "" "0,r"))
4200 (match_operand:SI 4 "const_int_operand" "n,n"))
4201 (match_operand:SI 5 "const_int_operand" "n,n")))
4202 (clobber (reg:SI T_REG))]
4205 [(set (attr "length")
4206 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
4208 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
4210 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
4212 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
4213 (const_string "10")]
4214 (const_string "12")))
4215 (set_attr "type" "arith")])
4218 [(set (match_operand:SI 0 "register_operand" "")
4222 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
4223 (match_operand:SI 2 "const_int_operand" ""))
4224 (match_operand:SI 3 "register_operand" ""))
4225 (match_operand:SI 4 "const_int_operand" ""))
4226 (match_operand:SI 5 "const_int_operand" "")))
4227 (clobber (reg:SI T_REG))]
4229 [(use (reg:SI R0_REG))]
4231 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
4233 if (INTVAL (operands[2]))
4235 gen_shifty_op (LSHIFTRT, operands);
4237 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
4238 operands[2] = operands[4];
4239 gen_shifty_op (ASHIFT, operands);
4240 if (INTVAL (operands[5]))
4242 operands[2] = operands[5];
4243 gen_shifty_op (LSHIFTRT, operands);
4248 ;; signed left/right shift combination.
4250 [(set (match_operand:SI 0 "register_operand" "")
4252 (ashift:SI (match_operand:SI 1 "register_operand" "")
4253 (match_operand:SI 2 "const_int_operand" ""))
4254 (match_operand:SI 3 "const_int_operand" "")
4256 (clobber (reg:SI T_REG))]
4258 [(use (reg:SI R0_REG))]
4260 if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1]))
4265 (define_insn "shl_sext_ext"
4266 [(set (match_operand:SI 0 "register_operand" "=r")
4268 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4269 (match_operand:SI 2 "const_int_operand" "n"))
4270 (match_operand:SI 3 "const_int_operand" "n")
4272 (clobber (reg:SI T_REG))]
4273 "TARGET_SH1 && (unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
4275 [(set (attr "length")
4276 (cond [(match_test "shl_sext_length (insn)")
4278 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
4280 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
4282 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
4284 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
4286 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
4288 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
4290 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
4291 (const_string "16")]
4292 (const_string "18")))
4293 (set_attr "type" "arith")])
4295 (define_insn "shl_sext_sub"
4296 [(set (match_operand:SI 0 "register_operand" "=z")
4298 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4299 (match_operand:SI 2 "const_int_operand" "n"))
4300 (match_operand:SI 3 "const_int_operand" "n")
4302 (clobber (reg:SI T_REG))]
4303 "TARGET_SH1 && (shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
4305 [(set (attr "length")
4306 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
4308 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
4310 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
4312 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
4313 (const_string "12")]
4314 (const_string "14")))
4315 (set_attr "type" "arith")])
4317 ;; The xtrct_left and xtrct_right patterns are used in expansions of DImode
4318 ;; shifts by 16, and allow the xtrct instruction to be generated from C
4320 (define_insn "xtrct_left"
4321 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4322 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
4324 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
4328 [(set_attr "type" "arith")])
4330 (define_insn "xtrct_right"
4331 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4332 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4334 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
4338 [(set_attr "type" "arith")])
4340 ;; -------------------------------------------------------------------------
4342 ;; -------------------------------------------------------------------------
4345 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4346 (neg:SI (plus:SI (reg:SI T_REG)
4347 (match_operand:SI 1 "arith_reg_operand" "r"))))
4349 (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
4353 [(set_attr "type" "arith")])
4355 ;; A simplified version of the negc insn, where the exact value of the
4356 ;; T bit doesn't matter. This is easier for combine to pick up.
4357 ;; Notice that '0 - x - 1' is the same as '~x', thus we don't specify
4358 ;; extra patterns for this case.
4359 (define_insn_and_split "*negc"
4360 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4361 (minus:SI (neg:SI (match_operand:SI 1 "arith_reg_operand" "r"))
4362 (match_operand 2 "treg_set_expr")))
4363 (clobber (reg:SI T_REG))]
4364 "TARGET_SH1 && can_create_pseudo_p ()"
4369 sh_split_treg_set_expr (operands[2], curr_insn);
4370 emit_insn (gen_negc (operands[0], operands[1]));
4374 ;; Don't split into individual negc insns immediately so that neg:DI (abs:DI)
4376 (define_insn_and_split "negdi2"
4377 [(set (match_operand:DI 0 "arith_reg_dest")
4378 (neg:DI (match_operand:DI 1 "arith_reg_operand")))
4379 (clobber (reg:SI T_REG))]
4382 "&& can_create_pseudo_p ()"
4385 emit_insn (gen_clrt ());
4386 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
4387 gen_lowpart (SImode, operands[1])));
4388 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
4389 gen_highpart (SImode, operands[1])));
4393 (define_insn "negsi2"
4394 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4395 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
4398 [(set_attr "type" "arith")])
4400 (define_insn_and_split "one_cmplsi2"
4401 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4402 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
4405 "&& can_create_pseudo_p ()"
4406 [(set (reg:SI T_REG) (ge:SI (match_dup 1) (const_int 0)))
4407 (set (match_dup 0) (reg:SI T_REG))]
4410 If the result of 'unsigned int <= 0x7FFFFFFF' ends up as the following
4413 (set (reg0) (not:SI (reg0) (reg1)))
4414 (parallel [(set (reg2) (lshiftrt:SI (reg0) (const_int 31)))
4415 (clobber (reg:SI T_REG))])
4417 ... match and combine the sequence manually in the split pass after the
4418 combine pass. Notice that combine does try the target pattern of this
4419 split, but if the pattern is added it interferes with other patterns, in
4420 particular with the div0s comparisons.
4421 This could also be done with a peephole but doing it here before register
4422 allocation can save one temporary.
4423 When we're here, the not:SI pattern obviously has been matched already
4424 and we only have to see whether the following insn is the left shift. */
4426 rtx_insn *i = next_nonnote_insn_bb (curr_insn);
4427 if (i == NULL_RTX || !NONJUMP_INSN_P (i))
4430 rtx p = PATTERN (i);
4431 if (GET_CODE (p) != PARALLEL || XVECLEN (p, 0) != 2)
4434 rtx p0 = XVECEXP (p, 0, 0);
4435 rtx p1 = XVECEXP (p, 0, 1);
4437 if (/* (set (reg2) (lshiftrt:SI (reg0) (const_int 31))) */
4438 GET_CODE (p0) == SET
4439 && GET_CODE (XEXP (p0, 1)) == LSHIFTRT
4440 && REG_P (XEXP (XEXP (p0, 1), 0))
4441 && REGNO (XEXP (XEXP (p0, 1), 0)) == REGNO (operands[0])
4442 && CONST_INT_P (XEXP (XEXP (p0, 1), 1))
4443 && INTVAL (XEXP (XEXP (p0, 1), 1)) == 31
4445 /* (clobber (reg:SI T_REG)) */
4446 && GET_CODE (p1) == CLOBBER && REG_P (XEXP (p1, 0))
4447 && REGNO (XEXP (p1, 0)) == T_REG)
4449 operands[0] = XEXP (p0, 0);
4450 set_insn_deleted (i);
4455 [(set_attr "type" "arith")])
4457 (define_insn_and_split "abs<mode>2"
4458 [(set (match_operand:SIDI 0 "arith_reg_dest")
4459 (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand")))
4460 (clobber (reg:SI T_REG))]
4463 "&& can_create_pseudo_p ()"
4466 if (<MODE>mode == SImode)
4467 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
4470 rtx high_src = gen_highpart (SImode, operands[1]);
4471 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
4474 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
4479 (define_insn_and_split "*negabs<mode>2"
4480 [(set (match_operand:SIDI 0 "arith_reg_dest")
4481 (neg:SIDI (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand"))))
4482 (clobber (reg:SI T_REG))]
4485 "&& can_create_pseudo_p ()"
4488 if (<MODE>mode == SImode)
4489 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
4492 rtx high_src = gen_highpart (SImode, operands[1]);
4493 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
4496 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
4501 ;; The SH4 202 can do zero-offset branches without pipeline stalls.
4502 ;; This can be used as some kind of conditional execution, which is useful
4504 ;; Actually the instruction scheduling should decide whether to use a
4505 ;; zero-offset branch or not for any generic case involving a single
4506 ;; instruction on SH4 202.
4507 (define_insn_and_split "negsi_cond"
4508 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4510 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand" "M,N"))
4511 (match_operand:SI 1 "arith_reg_operand" "0,0")
4512 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r,r"))))]
4513 "TARGET_SH1 && TARGET_ZDCBRANCH"
4515 static const char* alt[] =
4525 return alt[which_alternative];
4527 "TARGET_SH1 && ! TARGET_ZDCBRANCH"
4530 rtx_code_label *skip_neg_label = gen_label_rtx ();
4532 emit_move_insn (operands[0], operands[1]);
4534 emit_jump_insn (INTVAL (operands[3])
4535 ? gen_branch_true (skip_neg_label)
4536 : gen_branch_false (skip_neg_label));
4538 emit_label_after (skip_neg_label,
4539 emit_insn (gen_negsi2 (operands[0], operands[1])));
4542 [(set_attr "type" "arith") ;; poor approximation
4543 (set_attr "length" "4")])
4545 (define_insn_and_split "negdi_cond"
4546 [(set (match_operand:DI 0 "arith_reg_dest")
4548 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand"))
4549 (match_operand:DI 1 "arith_reg_operand")
4550 (neg:DI (match_operand:DI 2 "arith_reg_operand"))))
4551 (clobber (reg:SI T_REG))]
4554 "&& can_create_pseudo_p ()"
4557 rtx_code_label *skip_neg_label = gen_label_rtx ();
4559 emit_move_insn (operands[0], operands[1]);
4561 emit_jump_insn (INTVAL (operands[3])
4562 ? gen_branch_true (skip_neg_label)
4563 : gen_branch_false (skip_neg_label));
4565 if (!INTVAL (operands[3]))
4566 emit_insn (gen_clrt ());
4568 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
4569 gen_lowpart (SImode, operands[1])));
4570 emit_label_after (skip_neg_label,
4571 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
4572 gen_highpart (SImode, operands[1]))));
4576 (define_expand "bswapsi2"
4577 [(set (match_operand:SI 0 "arith_reg_dest" "")
4578 (bswap:SI (match_operand:SI 1 "arith_reg_operand" "")))]
4581 if (! can_create_pseudo_p ())
4585 rtx tmp0 = gen_reg_rtx (SImode);
4586 rtx tmp1 = gen_reg_rtx (SImode);
4588 emit_insn (gen_swapbsi2 (tmp0, operands[1]));
4589 emit_insn (gen_rotlsi3_16 (tmp1, tmp0));
4590 emit_insn (gen_swapbsi2 (operands[0], tmp1));
4595 (define_insn "swapbsi2"
4596 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4597 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
4598 (const_int -65536)) ;; 0xFFFF0000
4599 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
4601 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
4602 (const_int 255)))))]
4605 [(set_attr "type" "arith")])
4607 ;; The *swapbisi2_and_shl8 pattern helps the combine pass simplifying
4608 ;; partial byte swap expressions such as...
4609 ;; ((x & 0xFF) << 8) | ((x >> 8) & 0xFF).
4610 ;; ...which are currently not handled by the tree optimizers.
4611 ;; The combine pass will not initially try to combine the full expression,
4612 ;; but only some sub-expressions. In such a case the *swapbisi2_and_shl8
4613 ;; pattern acts as an intermediate pattern that will eventually lead combine
4614 ;; to the swapbsi2 pattern above.
4615 ;; As a side effect this also improves code that does (x & 0xFF) << 8
4616 ;; or (x << 8) & 0xFF00.
4617 (define_insn_and_split "*swapbisi2_and_shl8"
4618 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4619 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
4622 (match_operand:SI 2 "arith_reg_operand" "r")))]
4623 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
4625 "&& can_create_pseudo_p ()"
4628 rtx tmp0 = gen_reg_rtx (SImode);
4629 rtx tmp1 = gen_reg_rtx (SImode);
4631 emit_insn (gen_zero_extendqisi2 (tmp0, gen_lowpart (QImode, operands[1])));
4632 emit_insn (gen_swapbsi2 (tmp1, tmp0));
4633 emit_insn (gen_iorsi3 (operands[0], tmp1, operands[2]));
4637 ;; The *swapbhisi2 pattern is, like the *swapbisi2_and_shl8 pattern, another
4638 ;; intermediate pattern that will help the combine pass arriving at swapbsi2.
4639 (define_insn_and_split "*swapbhisi2"
4640 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4641 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
4644 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))))]
4645 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
4647 "&& can_create_pseudo_p ()"
4650 rtx tmp = gen_reg_rtx (SImode);
4652 emit_insn (gen_zero_extendhisi2 (tmp, gen_lowpart (HImode, operands[1])));
4653 emit_insn (gen_swapbsi2 (operands[0], tmp));
4657 ;; In some cases the swapbsi2 pattern might leave a sequence such as...
4661 ;; which can be simplified to...
4664 [(set (match_operand:SI 0 "arith_reg_dest" "")
4665 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
4666 (const_int -65536)) ;; 0xFFFF0000
4667 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
4669 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
4671 (set (match_operand:SI 2 "arith_reg_dest" "")
4673 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
4675 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
4676 (const_int -65536)) ;; 0xFFFF0000
4677 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
4679 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
4680 (const_int 255)))))])
4682 ;; -------------------------------------------------------------------------
4683 ;; Zero extension instructions
4684 ;; -------------------------------------------------------------------------
4686 (define_expand "zero_extend<mode>si2"
4687 [(set (match_operand:SI 0 "arith_reg_dest")
4688 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand")))])
4690 (define_insn_and_split "*zero_extend<mode>si2_compact"
4691 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4692 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
4695 "&& can_create_pseudo_p ()"
4696 [(set (match_dup 0) (match_dup 2))]
4698 /* Sometimes combine fails to combine a T bit or negated T bit store to a
4699 reg with a following zero extension. In the split pass after combine,
4700 try to figure out how the extended reg was set. If it originated from
4701 the T bit we can replace the zero extension with a reg move, which will
4702 be eliminated. Notice that this also helps the *cbranch_t splitter when
4703 it tries to post-combine tests and conditional branches, as it does not
4704 check for zero extensions. */
4705 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
4706 if (operands[2] == NULL_RTX)
4709 [(set_attr "type" "arith")])
4711 (define_insn "zero_extendqihi2"
4712 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4713 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
4716 [(set_attr "type" "arith")])
4718 ;; SH2A supports two zero extending load instructions: movu.b and movu.w.
4719 ;; They could also be used for simple memory addresses like @Rn by setting
4720 ;; the displacement value to zero. However, doing so too early results in
4721 ;; missed opportunities for other optimizations such as post-inc or index
4722 ;; addressing loads.
4723 ;; We don't allow the zero extending loads to match during RTL expansion,
4724 ;; as this would pessimize other optimization opportunities such as bit
4725 ;; extractions of unsigned mems, where the zero extraction is irrelevant.
4726 ;; If the zero extracting mem loads are emitted early it will be more
4727 ;; difficult to change them back to sign extending loads (which are preferred).
4728 ;; The combine pass will also try to combine mem loads and zero extends,
4729 ;; which is prevented by 'sh_legitimate_combined_insn'.
4730 (define_insn "*zero_extend<mode>si2_disp_mem"
4731 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4733 (match_operand:QIHI 1 "zero_extend_movu_operand" "Sdd,Sra")))]
4737 movu.<bw> @(0,%t1),%0"
4738 [(set_attr "type" "load")
4739 (set_attr "length" "4")])
4741 ;; Convert the zero extending loads in sequences such as:
4742 ;; movu.b @(1,r5),r0 movu.w @(2,r5),r0
4743 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
4745 ;; back to sign extending loads like:
4746 ;; mov.b @(1,r5),r0 mov.w @(2,r5),r0
4747 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
4749 ;; if the extension type is irrelevant. The sign extending mov.{b|w} insn
4750 ;; is only 2 bytes in size if the displacement is {K04|K05}.
4751 ;; If the displacement is greater it doesn't matter, so we convert anyways.
4753 [(set (match_operand:SI 0 "arith_reg_dest" "")
4754 (zero_extend:SI (match_operand 1 "displacement_mem_operand" "")))
4755 (set (match_operand 2 "nonimmediate_operand" "")
4756 (match_operand 3 "arith_reg_operand" ""))]
4758 && REGNO (operands[0]) == REGNO (operands[3])
4759 && peep2_reg_dead_p (2, operands[0])
4760 && GET_MODE_SIZE (GET_MODE (operands[2]))
4761 <= GET_MODE_SIZE (GET_MODE (operands[1]))"
4762 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
4763 (set (match_dup 2) (match_dup 3))])
4765 ;; Fold sequences such as
4769 ;; movu.b @(0,r3),r7
4770 ;; This does not reduce the code size but the number of instructions is
4771 ;; halved, which results in faster code.
4773 [(set (match_operand:SI 0 "arith_reg_dest" "")
4774 (sign_extend:SI (match_operand 1 "simple_mem_operand" "")))
4775 (set (match_operand:SI 2 "arith_reg_dest" "")
4776 (zero_extend:SI (match_operand 3 "arith_reg_operand" "")))]
4778 && GET_MODE (operands[1]) == GET_MODE (operands[3])
4779 && (GET_MODE (operands[1]) == QImode || GET_MODE (operands[1]) == HImode)
4780 && REGNO (operands[0]) == REGNO (operands[3])
4781 && (REGNO (operands[2]) == REGNO (operands[0])
4782 || peep2_reg_dead_p (2, operands[0]))"
4783 [(set (match_dup 2) (zero_extend:SI (match_dup 4)))]
4786 = replace_equiv_address (operands[1],
4787 gen_rtx_PLUS (SImode, XEXP (operands[1], 0),
4791 ;; -------------------------------------------------------------------------
4792 ;; Sign extension instructions
4793 ;; -------------------------------------------------------------------------
4795 ;; ??? This should be a define expand.
4796 ;; ??? Or perhaps it should be dropped?
4798 ;; convert_move generates good code for SH[1-4].
4800 (define_expand "extend<mode>si2"
4801 [(set (match_operand:SI 0 "arith_reg_dest")
4802 (sign_extend:SI (match_operand:QIHI 1 "general_extend_operand")))])
4804 (define_insn_and_split "*extend<mode>si2_compact_reg"
4805 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4806 (sign_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
4809 "&& can_create_pseudo_p ()"
4810 [(set (match_dup 0) (match_dup 2))]
4812 /* Sometimes combine fails to combine a T bit or negated T bit store to a
4813 reg with a following sign extension. In the split pass after combine,
4814 try to figure the extended reg was set. If it originated from the T
4815 bit we can replace the sign extension with a reg move, which will be
4817 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
4818 if (operands[2] == NULL_RTX)
4821 [(set_attr "type" "arith")])
4823 ;; FIXME: Fold non-SH2A and SH2A alternatives with "enabled" attribute.
4825 (define_insn "*extend<mode>si2_compact_mem_disp"
4826 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
4830 (match_operand:SI 1 "arith_reg_operand" "%r,r")
4831 (match_operand:SI 2 "const_int_operand" "<disp04>,N")))))]
4832 "TARGET_SH1 && ! TARGET_SH2A
4833 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
4835 mov.<bw> @(%O2,%1),%0
4837 [(set_attr "type" "load")])
4839 (define_insn "*extend<mode>si2_compact_mem_disp"
4840 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r,r")
4844 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
4845 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>")))))]
4846 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
4848 mov.<bw> @(%O2,%1),%0
4850 mov.<bw> @(%O2,%1),%0"
4851 [(set_attr "type" "load")
4852 (set_attr "length" "2,2,4")])
4854 ;; The pre-dec and post-inc mems must be captured by the '<' and '>'
4855 ;; constraints, otherwise wrong code might get generated.
4856 (define_insn "*extend<mode>si2_predec"
4857 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
4858 (sign_extend:SI (match_operand:QIHI 1 "pre_dec_mem" "<")))]
4861 [(set_attr "type" "load")])
4863 ;; The *_snd patterns will take care of other QImode/HImode addressing
4864 ;; modes than displacement addressing. They must be defined _after_ the
4865 ;; displacement addressing patterns. Otherwise the displacement addressing
4866 ;; patterns will not be picked.
4867 (define_insn "*extend<mode>si2_compact_snd"
4868 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4870 (match_operand:QIHI 1 "movsrc_no_disp_mem_operand" "Snd")))]
4873 [(set_attr "type" "load")])
4875 (define_expand "extendqihi2"
4876 [(set (match_operand:HI 0 "arith_reg_dest")
4877 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand")))]
4880 (define_insn "*extendqihi2_compact_reg"
4881 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4882 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
4885 [(set_attr "type" "arith")])
4887 ;; -------------------------------------------------------------------------
4888 ;; Move instructions
4889 ;; -------------------------------------------------------------------------
4891 (define_expand "push"
4892 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4893 (match_operand:SI 0 "register_operand"))])
4895 (define_expand "pop"
4896 [(set (match_operand:SI 0 "register_operand")
4897 (mem:SI (post_inc:SI (reg:SI SP_REG))))])
4899 (define_expand "push_e"
4900 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG)))
4901 (match_operand:SF 0 "" ""))
4902 (use (reg:SI FPSCR_MODES_REG))
4903 (clobber (scratch:SI))])])
4905 (define_insn "push_fpul"
4906 [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
4909 [(set_attr "type" "fstore")
4910 (set_attr "late_fp_use" "yes")
4911 (set_attr "hit_stack" "yes")])
4913 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
4915 (define_expand "push_4"
4916 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG)))
4917 (match_operand:DF 0 "" ""))
4918 (use (reg:SI FPSCR_MODES_REG))
4919 (clobber (scratch:SI))])])
4921 (define_expand "pop_e"
4922 [(parallel [(set (match_operand:SF 0 "" "")
4923 (mem:SF (post_inc:SI (reg:SI SP_REG))))
4924 (use (reg:SI FPSCR_MODES_REG))
4925 (clobber (scratch:SI))])])
4927 (define_insn "pop_fpul"
4928 [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
4931 [(set_attr "type" "load")
4932 (set_attr "hit_stack" "yes")])
4934 (define_expand "pop_4"
4935 [(parallel [(set (match_operand:DF 0 "" "")
4936 (mem:DF (post_inc:SI (reg:SI SP_REG))))
4937 (use (reg:SI FPSCR_MODES_REG))
4938 (clobber (scratch:SI))])])
4940 (define_expand "push_fpscr"
4947 gen_frame_mem (SImode, gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)))),
4948 REG_INC, stack_pointer_rtx);
4952 (define_expand "pop_fpscr"
4959 gen_frame_mem (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)))),
4960 REG_INC, stack_pointer_rtx);
4964 ;; The clrt and sett patterns can happen as the result of optimization and
4966 ;; Comparisons might get simplified to a move of zero or 1 into the T reg.
4967 ;; In this case they might not disappear completely, because the T reg is
4968 ;; a fixed hard reg.
4969 ;; When DImode operations that use the T reg as carry/borrow are split into
4970 ;; individual SImode operations, the T reg is usually cleared before the
4971 ;; first SImode insn.
4973 [(set (reg:SI T_REG) (const_int 0))]
4976 [(set_attr "type" "mt_group")])
4979 [(set (reg:SI T_REG) (const_int 1))]
4982 [(set_attr "type" "mt_group")])
4984 ;; Use the combine pass to transform sequences such as
4988 ;; mov.l @(r0,r4),r0
4994 ;; See also PR 39423.
4995 ;; Notice that these patterns have a T_REG clobber, because the shift
4996 ;; sequence that will be split out might clobber the T_REG. Ideally, the
4997 ;; clobber would be added conditionally, depending on the result of
4998 ;; sh_ashlsi_clobbers_t_reg_p. When splitting out the shifts we must go
4999 ;; through the ashlsi3 expander in order to get the right shift insn --
5000 ;; a T_REG clobbering or non-clobbering shift sequence or dynamic shift.
5001 ;; FIXME: Combine never tries this kind of patterns for DImode.
5002 (define_insn_and_split "*movsi_index_disp_load"
5003 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5004 (match_operand:SI 1 "mem_index_disp_operand" "m"))
5005 (clobber (reg:SI T_REG))]
5008 "&& can_create_pseudo_p ()"
5009 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
5010 (set (match_dup 0) (match_dup 7))]
5012 rtx mem = operands[1];
5013 rtx plus0_rtx = XEXP (mem, 0);
5014 rtx plus1_rtx = XEXP (plus0_rtx, 0);
5015 rtx mult_rtx = XEXP (plus1_rtx, 0);
5017 operands[1] = XEXP (mult_rtx, 0);
5018 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
5019 operands[3] = XEXP (plus1_rtx, 1);
5020 operands[4] = XEXP (plus0_rtx, 1);
5021 operands[5] = gen_reg_rtx (SImode);
5022 operands[6] = gen_reg_rtx (SImode);
5024 replace_equiv_address (mem,
5025 gen_rtx_PLUS (SImode, operands[6], operands[4]));
5027 emit_insn (gen_ashlsi3 (operands[5], operands[1], operands[2]));
5030 (define_insn_and_split "*movhi_index_disp_load"
5031 [(set (match_operand:SI 0 "arith_reg_dest")
5032 (SZ_EXTEND:SI (match_operand:HI 1 "mem_index_disp_operand")))
5033 (clobber (reg:SI T_REG))]
5036 "&& can_create_pseudo_p ()"
5039 rtx mem = operands[1];
5040 rtx plus0_rtx = XEXP (mem, 0);
5041 rtx plus1_rtx = XEXP (plus0_rtx, 0);
5042 rtx mult_rtx = XEXP (plus1_rtx, 0);
5044 rtx op_1 = XEXP (mult_rtx, 0);
5045 rtx op_2 = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
5046 rtx op_3 = XEXP (plus1_rtx, 1);
5047 rtx op_4 = XEXP (plus0_rtx, 1);
5048 rtx op_5 = gen_reg_rtx (SImode);
5049 rtx op_6 = gen_reg_rtx (SImode);
5050 rtx op_7 = replace_equiv_address (mem, gen_rtx_PLUS (SImode, op_6, op_4));
5052 emit_insn (gen_ashlsi3 (op_5, op_1, op_2));
5053 emit_insn (gen_addsi3 (op_6, op_5, op_3));
5055 if (<CODE> == SIGN_EXTEND)
5057 emit_insn (gen_extendhisi2 (operands[0], op_7));
5060 else if (<CODE> == ZERO_EXTEND)
5062 /* On SH2A the movu.w insn can be used for zero extending loads. */
5064 emit_insn (gen_zero_extendhisi2 (operands[0], op_7));
5067 emit_insn (gen_extendhisi2 (operands[0], op_7));
5068 emit_insn (gen_zero_extendhisi2 (operands[0],
5069 gen_lowpart (HImode, operands[0])));
5077 (define_insn_and_split "*mov<mode>_index_disp_store"
5078 [(set (match_operand:HISI 0 "mem_index_disp_operand" "=m")
5079 (match_operand:HISI 1 "arith_reg_operand" "r"))
5080 (clobber (reg:SI T_REG))]
5083 "&& can_create_pseudo_p ()"
5084 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
5085 (set (match_dup 7) (match_dup 1))]
5087 rtx mem = operands[0];
5088 rtx plus0_rtx = XEXP (mem, 0);
5089 rtx plus1_rtx = XEXP (plus0_rtx, 0);
5090 rtx mult_rtx = XEXP (plus1_rtx, 0);
5092 operands[0] = XEXP (mult_rtx, 0);
5093 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
5094 operands[3] = XEXP (plus1_rtx, 1);
5095 operands[4] = XEXP (plus0_rtx, 1);
5096 operands[5] = gen_reg_rtx (SImode);
5097 operands[6] = gen_reg_rtx (SImode);
5099 replace_equiv_address (mem,
5100 gen_rtx_PLUS (SImode, operands[6], operands[4]));
5102 emit_insn (gen_ashlsi3 (operands[5], operands[0], operands[2]));
5105 ;; t/r must come after r/r, lest reload will try to reload stuff like
5106 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
5107 ;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
5108 ;; Notice that although this pattern allows movi20 and movi20s on non-SH2A,
5109 ;; those alternatives will not be taken, as they will be converted into
5110 ;; PC-relative loads.
5111 (define_insn "movsi_i"
5112 [(set (match_operand:SI 0 "general_movdst_operand"
5113 "=r,r, r, r, r, r,r,r,m,<,<,x,l,x,l,r")
5114 (match_operand:SI 1 "general_movsrc_operand"
5115 " Q,r,I08,I20,I28,mr,x,l,r,x,l,r,r,>,>,i"))]
5116 "TARGET_SH1 && !TARGET_FPU_ANY
5117 && (register_operand (operands[0], SImode)
5118 || register_operand (operands[1], SImode))"
5136 [(set_attr "type" "pcload_si,move,movi8,move,move,load_si,mac_gp,prget,store,
5137 mac_mem,pstore,gp_mac,prset,mem_mac,pload,pcload_si")
5138 (set_attr_alternative "length"
5144 (if_then_else (match_operand 1 "long_displacement_mem_operand")
5145 (const_int 4) (const_int 2))
5148 (if_then_else (match_operand 0 "long_displacement_mem_operand")
5149 (const_int 4) (const_int 2))
5158 ;; t/r must come after r/r, lest reload will try to reload stuff like
5159 ;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
5160 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
5161 ;; will require a reload.
5162 ;; ??? We can't include f/f because we need the proper FPSCR setting when
5163 ;; TARGET_FMOVD is in effect, and mode switching is done before reload.
5164 ;; Notice that although this pattern allows movi20 and movi20s on non-SH2A,
5165 ;; those alternatives will not be taken, as they will be converted into
5166 ;; PC-relative loads.
5167 (define_insn "movsi_ie"
5168 [(set (match_operand:SI 0 "general_movdst_operand"
5169 "=r,r, r, r, r, r,r,r,mr,<,<,x,l,x,l,y,<,r,y,r,*f, y,*f,y")
5170 (match_operand:SI 1 "general_movsrc_operand"
5171 " Q,r,I08,I20,I28,mr,x,l, r,x,l,r,r,>,>,>,y,i,r,y, y,*f,*f,y"))]
5172 "TARGET_SH1 && TARGET_FPU_ANY
5173 && ((register_operand (operands[0], SImode)
5174 && !fpscr_operand (operands[0], SImode))
5175 || (register_operand (operands[1], SImode)
5176 && !fpscr_operand (operands[1], SImode)))"
5201 ! move optimized away"
5202 [(set_attr "type" "pcload_si,move,movi8,move,move,load_si,mac_gp,prget,store,
5203 mac_mem,pstore,gp_mac,prset,mem_mac,pload,load,fstore,
5204 pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
5205 (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
5206 (set_attr_alternative "length"
5212 (if_then_else (match_operand 1 "long_displacement_mem_operand")
5213 (const_int 4) (const_int 2))
5216 (if_then_else (match_operand 0 "long_displacement_mem_operand")
5217 (const_int 4) (const_int 2))
5234 ;; Notice that although this pattern allows movi20 and movi20s on non-SH2A,
5235 ;; those alternatives will not be taken, as they will be converted into
5236 ;; PC-relative loads.
5237 (define_insn "movsi_i_lowpart"
5238 [(set (strict_low_part
5239 (match_operand:SI 0 "general_movdst_operand"
5240 "+r,r, r, r, r, r,r,r,m,r"))
5241 (match_operand:SI 1 "general_movsrc_operand"
5242 " Q,r,I08,I20,I28,mr,x,l,r,i"))]
5244 && (register_operand (operands[0], SImode)
5245 || register_operand (operands[1], SImode))"
5257 [(set_attr "type" "pcload,move,movi8,move,move,load,mac_gp,prget,store,
5259 (set_attr_alternative "length"
5265 (if_then_else (match_operand 1 "long_displacement_mem_operand")
5266 (const_int 4) (const_int 2))
5269 (if_then_else (match_operand 0 "long_displacement_mem_operand")
5270 (const_int 4) (const_int 2))
5273 (define_insn_and_split "load_ra"
5274 [(set (match_operand:SI 0 "general_movdst_operand" "")
5275 (unspec:SI [(match_operand:SI 1 "register_operand" "")] UNSPEC_RA))]
5278 "&& ! currently_expanding_to_rtl"
5279 [(set (match_dup 0) (match_dup 1))])
5281 (define_expand "movsi"
5282 [(set (match_operand:SI 0 "general_movdst_operand" "")
5283 (match_operand:SI 1 "general_movsrc_operand" ""))]
5286 prepare_move_operands (operands, SImode);
5289 (define_expand "ic_invalidate_line"
5290 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand")
5291 (match_dup 1)] UNSPEC_ICACHE)
5292 (clobber (scratch:SI))])]
5295 emit_insn (gen_ic_invalidate_line_sh4a (operands[0]));
5299 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
5300 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
5301 ;; the requirement *1*00 for associative address writes. The alignment of
5302 ;; %0 implies that its least significant bit is cleared,
5303 ;; thus we clear the V bit of a matching entry if there is one.
5304 (define_insn "ic_invalidate_line_i"
5305 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
5306 (match_operand:SI 1 "register_operand" "r")]
5308 (clobber (match_scratch:SI 2 "=&r"))]
5311 return "ocbwb @%0" "\n"
5312 " extu.w %0,%2" "\n"
5316 [(set_attr "length" "8")
5317 (set_attr "type" "cwb")])
5319 (define_insn "ic_invalidate_line_sh4a"
5320 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
5322 "TARGET_SH4A || TARGET_SH4_300"
5324 return "ocbwb @%0" "\n"
5328 [(set_attr "length" "6")
5329 (set_attr "type" "cwb")])
5331 (define_expand "mov<mode>"
5332 [(set (match_operand:QIHI 0 "general_movdst_operand")
5333 (match_operand:QIHI 1 "general_movsrc_operand"))]
5336 if (can_create_pseudo_p () && CONST_INT_P (operands[1])
5337 && REG_P (operands[0]) && REGNO (operands[0]) != R0_REG)
5339 rtx reg = gen_reg_rtx(SImode);
5340 emit_move_insn (reg, operands[1]);
5341 operands[1] = gen_lowpart (<MODE>mode, reg);
5344 prepare_move_operands (operands, <MODE>mode);
5347 ;; The pre-dec and post-inc mems must be captured by the '<' and '>'
5348 ;; constraints, otherwise wrong code might get generated.
5349 (define_insn "*mov<mode>_load_predec"
5350 [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z")
5351 (match_operand:QIHISI 1 "pre_dec_mem" "<"))]
5354 [(set_attr "type" "load")])
5356 (define_insn "*mov<mode>_store_postinc"
5357 [(set (match_operand:QIHISI 0 "post_inc_mem" "=>")
5358 (match_operand:QIHISI 1 "arith_reg_operand" "z"))]
5361 [(set_attr "type" "store")])
5363 ;; Specifying the displacement addressing load / store patterns separately
5364 ;; before the generic movqi / movhi pattern allows controlling the order
5365 ;; in which load / store insns are selected in a more fine grained way.
5366 ;; FIXME: The non-SH2A and SH2A variants should be combined by adding
5367 ;; "enabled" attribute as it is done in other targets.
5368 (define_insn "*mov<mode>_store_mem_disp04"
5370 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r,r")
5371 (match_operand:SI 1 "const_int_operand" "<disp04>,N")))
5372 (match_operand:QIHI 2 "arith_reg_operand" "z,r"))]
5373 "TARGET_SH1 && sh_legitimate_index_p (<MODE>mode, operands[1], false, true)"
5375 mov.<bw> %2,@(%O1,%0)
5377 [(set_attr "type" "store")])
5379 (define_insn "*mov<mode>_store_mem_disp12"
5381 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r")
5382 (match_operand:SI 1 "const_int_operand" "<disp12>")))
5383 (match_operand:QIHI 2 "arith_reg_operand" "r"))]
5384 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[1], true, true)"
5385 "mov.<bw> %2,@(%O1,%0)"
5386 [(set_attr "type" "store")
5387 (set_attr "length" "4")])
5389 (define_insn "*mov<mode>_load_mem_disp04"
5390 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r")
5392 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r")
5393 (match_operand:SI 2 "const_int_operand" "<disp04>,N"))))]
5394 "TARGET_SH1 && ! TARGET_SH2A
5395 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
5397 mov.<bw> @(%O2,%1),%0
5399 [(set_attr "type" "load")])
5401 (define_insn "*mov<mode>_load_mem_disp12"
5402 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r,r")
5405 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
5406 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>"))))]
5407 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
5409 mov.<bw> @(%O2,%1),%0
5411 mov.<bw> @(%O2,%1),%0"
5412 [(set_attr "type" "load")
5413 (set_attr "length" "2,2,4")])
5415 ;; The order of the constraint alternatives is important here.
5416 ;; Q/r has to come first, otherwise PC relative loads might wrongly get
5417 ;; placed into delay slots. Since there is no QImode PC relative load, the
5418 ;; Q constraint and general_movsrc_operand will reject it for QImode.
5419 ;; The Sid/Ssd alternatives should come before Sdd in order to avoid
5420 ;; a preference of using r0 als the register operand for addressing modes
5421 ;; other than displacement addressing.
5422 ;; The Sdd alternatives allow only r0 as register operand, even though on
5423 ;; SH2A any register could be allowed by switching to a 32 bit insn.
5424 ;; Generally sticking to the r0 is preferrable, since it generates smaller
5425 ;; code. Obvious r0 reloads can then be eliminated with a peephole on SH2A.
5426 (define_insn "*mov<mode>"
5427 [(set (match_operand:QIHI 0 "general_movdst_operand"
5428 "=r,r,r,Sid,^zr,Ssd,r, Sdd,z, r,l")
5429 (match_operand:QIHI 1 "general_movsrc_operand"
5430 "Q,r,i,^zr,Sid,r, Ssd,z, Sdd,l,r"))]
5432 && (arith_reg_operand (operands[0], <MODE>mode)
5433 || arith_reg_operand (operands[1], <MODE>mode))"
5446 [(set_attr "type" "pcload,move,movi8,store,load,store,load,store,load,prget,prset")
5447 (set (attr "length")
5448 (cond [(match_operand 0 "long_displacement_mem_operand") (const_int 4)
5449 (match_operand 1 "long_displacement_mem_operand") (const_int 4)]
5452 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
5453 ;; compiled with -m2 -ml -O3 -funroll-loops
5454 (define_insn "*movdi_i"
5455 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m, r,r,r,*!x")
5456 (match_operand:DI 1 "general_movsrc_operand" " Q,r,m,r,I08,i,x, r"))]
5458 && (arith_reg_operand (operands[0], DImode)
5459 || arith_reg_operand (operands[1], DImode))"
5461 return output_movedouble (insn, operands, DImode);
5463 [(set_attr "type" "pcload,move,load,store,move,pcload,move,move")
5464 (set (attr "length")
5465 (cond [(match_operand 0 "long_displacement_mem_operand") (const_int 8)
5466 (match_operand 1 "long_displacement_mem_operand") (const_int 8)]
5469 ;; If the output is a register and the input is memory or a register, we have
5470 ;; to be careful and see which word needs to be loaded first.
5472 [(set (match_operand:DI 0 "general_movdst_operand" "")
5473 (match_operand:DI 1 "general_movsrc_operand" ""))]
5474 "TARGET_SH1 && reload_completed"
5475 [(set (match_dup 2) (match_dup 3))
5476 (set (match_dup 4) (match_dup 5))]
5480 if ((MEM_P (operands[0])
5481 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
5482 || (MEM_P (operands[1])
5483 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
5486 switch (GET_CODE (operands[0]))
5489 regno = REGNO (operands[0]);
5492 regno = subreg_regno (operands[0]);
5501 if (regno == -1 || ! refers_to_regno_p (regno, operands[1]))
5503 operands[2] = operand_subword (operands[0], 0, 0, DImode);
5504 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5505 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5506 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5510 operands[2] = operand_subword (operands[0], 1, 0, DImode);
5511 operands[3] = operand_subword (operands[1], 1, 0, DImode);
5512 operands[4] = operand_subword (operands[0], 0, 0, DImode);
5513 operands[5] = operand_subword (operands[1], 0, 0, DImode);
5516 if (operands[2] == 0 || operands[3] == 0
5517 || operands[4] == 0 || operands[5] == 0)
5521 (define_expand "movdi"
5522 [(set (match_operand:DI 0 "general_movdst_operand" "")
5523 (match_operand:DI 1 "general_movsrc_operand" ""))]
5526 prepare_move_operands (operands, DImode);
5528 /* When the dest operand is (R0, R1) register pair, split it to
5529 two movsi of which dest is R1 and R0 so as to lower R0-register
5530 pressure on the first movsi. Apply only for simple source not
5531 to make complex rtl here. */
5532 if (REG_P (operands[0]) && REGNO (operands[0]) == R0_REG
5533 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
5535 emit_insn (gen_movsi (gen_rtx_REG (SImode, R1_REG),
5536 gen_rtx_SUBREG (SImode, operands[1], 4)));
5537 emit_insn (gen_movsi (gen_rtx_REG (SImode, R0_REG),
5538 gen_rtx_SUBREG (SImode, operands[1], 0)));
5543 ;; FIXME: This should be a define_insn_and_split.
5544 (define_insn "movdf_k"
5545 [(set (match_operand:DF 0 "general_movdst_operand" "=r, r,r,m")
5546 (match_operand:DF 1 "general_movsrc_operand" " r,FQ,m,r"))]
5548 && (!TARGET_FPU_DOUBLE || reload_completed
5549 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
5550 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
5551 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
5552 && (arith_reg_operand (operands[0], DFmode)
5553 || arith_reg_operand (operands[1], DFmode))"
5555 return output_movedouble (insn, operands, DFmode);
5557 [(set_attr "type" "move,pcload,load,store")
5558 (set (attr "length")
5559 (cond [(match_operand 0 "long_displacement_mem_operand") (const_int 8)
5560 (match_operand 1 "long_displacement_mem_operand") (const_int 8)]
5563 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
5564 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
5565 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
5566 ;; the d/m/c/X alternative, which is split later into single-precision
5567 ;; instructions. And when not optimizing, no splits are done before fixing
5568 ;; up pcloads, so we need usable length information for that.
5569 ;; A DF constant load results in the following worst-case 8 byte sequence:
5574 (define_insn "movdf_i4"
5575 [(set (match_operand:DF 0 "general_movdst_operand"
5576 "=d,r, d,d,m, r,r,m,!??r,!???d")
5577 (match_operand:DF 1 "general_movsrc_operand"
5578 " d,r, F,m,d,FQ,m,r, d, r"))
5579 (use (reg:SI FPSCR_MODES_REG))
5580 (clobber (match_scratch:SI 2
5581 "=X,X,&z,X,X, X,X,X, X, X"))]
5583 && (arith_reg_operand (operands[0], DFmode)
5584 || arith_reg_operand (operands[1], DFmode))"
5586 switch (which_alternative)
5590 return "fmov %1,%0";
5591 else if (REGNO (operands[0]) != REGNO (operands[1]) + 1)
5592 return "fmov %R1,%R0" "\n"
5595 return "fmov %S1,%S0" "\n"
5599 return "fmov.d %1,%0";
5604 [(set_attr_alternative "length"
5605 [(if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 4))
5607 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 8))
5608 (if_then_else (match_operand 1 "displacement_mem_operand")
5609 (if_then_else (eq_attr "fmovd" "yes")
5610 (const_int 4) (const_int 8))
5611 (if_then_else (eq_attr "fmovd" "yes")
5612 (const_int 2) (const_int 4)))
5613 (if_then_else (match_operand 0 "displacement_mem_operand")
5614 (if_then_else (eq_attr "fmovd" "yes")
5615 (const_int 4) (const_int 8))
5616 (if_then_else (eq_attr "fmovd" "yes")
5617 (const_int 2) (const_int 4)))
5619 (if_then_else (match_operand 1 "long_displacement_mem_operand")
5620 (const_int 8) (const_int 4))
5621 (if_then_else (match_operand 0 "long_displacement_mem_operand")
5622 (const_int 8) (const_int 4))
5625 (set_attr "type" "fmove,move,pcfload,fload,fstore,pcload,load,store,load,
5627 (set_attr "late_fp_use" "*,*,*,*,yes,*,*,*,*,*")
5628 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
5629 (const_string "double")
5630 (const_string "none")))])
5632 ;; Moving DFmode between fp/general registers through memory
5633 ;; (the top of the stack) is faster than moving through fpul even for
5634 ;; little endian. Because the type of an instruction is important for its
5635 ;; scheduling, it is beneficial to split these operations, rather than
5636 ;; emitting them in one single chunk, even if this will expose a stack
5637 ;; use that will prevent scheduling of other stack accesses beyond this
5640 [(set (match_operand:DF 0 "register_operand")
5641 (match_operand:DF 1 "register_operand"))
5642 (use (reg:SI FPSCR_MODES_REG))
5643 (clobber (match_scratch:SI 2))]
5644 "TARGET_FPU_DOUBLE && reload_completed
5645 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
5650 tos = gen_tmp_stack_mem (DFmode, gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
5651 insn = emit_insn (gen_movdf_i4 (tos, operands[1]));
5652 add_reg_note (insn, REG_INC, stack_pointer_rtx);
5653 tos = gen_tmp_stack_mem (DFmode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx));
5654 insn = emit_insn (gen_movdf_i4 (operands[0], tos));
5655 add_reg_note (insn, REG_INC, stack_pointer_rtx);
5659 ;; local-alloc sometimes allocates scratch registers even when not required,
5660 ;; so we must be prepared to handle these.
5662 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
5664 [(set (match_operand:DF 0 "general_movdst_operand" "")
5665 (match_operand:DF 1 "general_movsrc_operand" ""))
5666 (use (reg:SI FPSCR_MODES_REG))
5667 (clobber (match_scratch:SI 2))]
5670 && true_regnum (operands[0]) < 16
5671 && true_regnum (operands[1]) < 16"
5672 [(set (match_dup 0) (match_dup 1))]
5674 /* If this was a reg <-> mem operation with base + index reg addressing,
5675 we have to handle this in a special way. */
5676 rtx mem = operands[0];
5678 if (! memory_operand (mem, DFmode))
5683 if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0)
5684 mem = SUBREG_REG (mem);
5687 rtx addr = XEXP (mem, 0);
5688 if (GET_CODE (addr) == PLUS
5689 && REG_P (XEXP (addr, 0))
5690 && REG_P (XEXP (addr, 1)))
5693 rtx reg0 = gen_rtx_REG (Pmode, 0);
5694 rtx regop = operands[store_p], word0 ,word1;
5696 if (GET_CODE (regop) == SUBREG)
5697 alter_subreg (®op, true);
5698 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
5702 mem = copy_rtx (mem);
5703 PUT_MODE (mem, SImode);
5704 word0 = gen_rtx_SUBREG (SImode, regop, 0);
5705 alter_subreg (&word0, true);
5706 word1 = gen_rtx_SUBREG (SImode, regop, 4);
5707 alter_subreg (&word1, true);
5708 if (store_p || ! refers_to_regno_p (REGNO (word0), addr))
5711 ? gen_movsi_ie (mem, word0)
5712 : gen_movsi_ie (word0, mem));
5713 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
5714 mem = copy_rtx (mem);
5716 ? gen_movsi_ie (mem, word1)
5717 : gen_movsi_ie (word1, mem));
5718 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
5722 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
5723 emit_insn (gen_movsi_ie (word1, mem));
5724 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
5725 mem = copy_rtx (mem);
5726 emit_insn (gen_movsi_ie (word0, mem));
5733 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
5735 [(set (match_operand:DF 0 "register_operand" "")
5736 (match_operand:DF 1 "memory_operand" ""))
5737 (use (reg:SI FPSCR_MODES_REG))
5738 (clobber (reg:SI R0_REG))]
5739 "TARGET_FPU_DOUBLE && reload_completed"
5740 [(parallel [(set (match_dup 0) (match_dup 1))
5741 (use (reg:SI FPSCR_MODES_REG))
5742 (clobber (scratch:SI))])]
5745 (define_expand "reload_indf__frn"
5746 [(parallel [(set (match_operand:DF 0 "register_operand" "=a")
5747 (match_operand:DF 1 "immediate_operand" "FQ"))
5748 (use (reg:SI FPSCR_MODES_REG))
5749 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
5753 (define_expand "reload_outdf__RnFRm"
5754 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
5755 (match_operand:DF 1 "register_operand" "af,r"))
5756 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
5760 ;; Simplify no-op moves.
5762 [(set (match_operand:SF 0 "register_operand" "")
5763 (match_operand:SF 1 "register_operand" ""))
5764 (use (reg:SI FPSCR_MODES_REG))
5765 (clobber (match_scratch:SI 2))]
5766 "TARGET_SH2E && reload_completed
5767 && true_regnum (operands[0]) == true_regnum (operands[1])"
5768 [(set (match_dup 0) (match_dup 0))]
5771 ;; fmovd substitute post-reload splits
5773 [(set (match_operand:DF 0 "register_operand" "")
5774 (match_operand:DF 1 "register_operand" ""))
5775 (use (reg:SI FPSCR_MODES_REG))
5776 (clobber (match_scratch:SI 2))]
5777 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
5778 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
5779 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
5782 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
5783 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst),
5784 gen_rtx_REG (SFmode, src)));
5785 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst + 1),
5786 gen_rtx_REG (SFmode, src + 1)));
5791 [(set (match_operand:DF 0 "register_operand" "")
5792 (mem:DF (match_operand:SI 1 "register_operand" "")))
5793 (use (reg:SI FPSCR_MODES_REG))
5794 (clobber (match_scratch:SI 2))]
5795 "TARGET_FPU_DOUBLE && ! TARGET_FMOVD && reload_completed
5796 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
5797 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
5800 int regno = true_regnum (operands[0]);
5802 rtx mem = SET_SRC (XVECEXP (PATTERN (curr_insn), 0, 0));
5804 = change_address (mem, SFmode, gen_rtx_POST_INC (Pmode, operands[1]));
5805 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
5806 regno + SH_REG_MSW_OFFSET),
5808 add_reg_note (insn, REG_INC, operands[1]);
5809 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
5810 regno + SH_REG_LSW_OFFSET),
5811 change_address (mem, SFmode, NULL_RTX)));
5816 [(set (match_operand:DF 0 "register_operand" "")
5817 (match_operand:DF 1 "memory_operand" ""))
5818 (use (reg:SI FPSCR_MODES_REG))
5819 (clobber (match_scratch:SI 2))]
5820 "TARGET_FPU_DOUBLE && ! TARGET_FMOVD && reload_completed
5821 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
5824 int regno = true_regnum (operands[0]);
5826 rtx mem2 = change_address (operands[1], SFmode, NULL_RTX);
5827 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
5828 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
5830 operands[1] = copy_rtx (mem2);
5831 addr = XEXP (mem2, 0);
5833 switch (GET_CODE (addr))
5836 /* This is complicated. If the register is an arithmetic register
5837 we can just fall through to the REG+DISP case below. Otherwise
5838 we have to use a combination of POST_INC and REG addressing... */
5839 if (! arith_reg_operand (operands[1], SFmode))
5841 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
5842 insn = emit_insn (gen_movsf_ie (reg0, mem2));
5843 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5845 emit_insn (gen_movsf_ie (reg1, operands[1]));
5847 /* If we have modified the stack pointer, the value that we have
5848 read with post-increment might be modified by an interrupt,
5849 so write it back. */
5850 if (REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
5851 emit_insn (gen_push_e (reg0));
5853 emit_insn (gen_addsi3 (XEXP (operands[1], 0), XEXP (operands[1], 0),
5860 emit_insn (gen_movsf_ie (reg0, operands[1]));
5861 operands[1] = copy_rtx (operands[1]);
5862 XEXP (operands[1], 0) = plus_constant (Pmode, addr, 4);
5863 emit_insn (gen_movsf_ie (reg1, operands[1]));
5867 insn = emit_insn (gen_movsf_ie (reg0, operands[1]));
5868 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5870 insn = emit_insn (gen_movsf_ie (reg1, operands[1]));
5871 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5883 [(set (match_operand:DF 0 "memory_operand" "")
5884 (match_operand:DF 1 "register_operand" ""))
5885 (use (reg:SI FPSCR_MODES_REG))
5886 (clobber (match_scratch:SI 2))]
5887 "TARGET_FPU_DOUBLE && ! TARGET_FMOVD && reload_completed
5888 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
5891 int regno = true_regnum (operands[1]);
5893 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
5894 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
5896 operands[0] = copy_rtx (operands[0]);
5897 PUT_MODE (operands[0], SFmode);
5898 addr = XEXP (operands[0], 0);
5900 switch (GET_CODE (addr))
5903 /* This is complicated. If the register is an arithmetic register
5904 we can just fall through to the REG+DISP case below. Otherwise
5905 we have to use a combination of REG and PRE_DEC addressing... */
5906 if (! arith_reg_operand (operands[0], SFmode))
5908 emit_insn (gen_addsi3 (addr, addr, GEN_INT (4)));
5909 emit_insn (gen_movsf_ie (operands[0], reg1));
5911 operands[0] = copy_rtx (operands[0]);
5912 XEXP (operands[0], 0) = addr = gen_rtx_PRE_DEC (SImode, addr);
5914 insn = emit_insn (gen_movsf_ie (operands[0], reg0));
5915 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5921 /* Since REG+DISP addressing has already been decided upon by gcc
5922 we can rely upon it having chosen an arithmetic register as the
5923 register component of the address. Just emit the lower numbered
5924 register first, to the lower address, then the higher numbered
5925 register to the higher address. */
5926 emit_insn (gen_movsf_ie (operands[0], reg0));
5928 operands[0] = copy_rtx (operands[0]);
5929 XEXP (operands[0], 0) = plus_constant (Pmode, addr, 4);
5931 emit_insn (gen_movsf_ie (operands[0], reg1));
5935 /* This is easy. Output the word to go to the higher address
5936 first (ie the word in the higher numbered register) then the
5937 word to go to the lower address. */
5939 insn = emit_insn (gen_movsf_ie (operands[0], reg1));
5940 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5942 insn = emit_insn (gen_movsf_ie (operands[0], reg0));
5943 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5955 ;; If the output is a register and the input is memory or a register, we have
5956 ;; to be careful and see which word needs to be loaded first.
5958 [(set (match_operand:DF 0 "general_movdst_operand" "")
5959 (match_operand:DF 1 "general_movsrc_operand" ""))]
5960 "TARGET_SH1 && reload_completed"
5961 [(set (match_dup 2) (match_dup 3))
5962 (set (match_dup 4) (match_dup 5))]
5966 if ((MEM_P (operands[0])
5967 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
5968 || (MEM_P (operands[1])
5969 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
5972 switch (GET_CODE (operands[0]))
5975 regno = REGNO (operands[0]);
5978 regno = subreg_regno (operands[0]);
5987 if (regno == -1 || ! refers_to_regno_p (regno, operands[1]))
5989 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
5990 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
5991 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
5992 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
5996 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
5997 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
5998 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
5999 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
6002 if (operands[2] == 0 || operands[3] == 0
6003 || operands[4] == 0 || operands[5] == 0)
6007 (define_expand "movdf"
6008 [(set (match_operand:DF 0 "general_movdst_operand" "")
6009 (match_operand:DF 1 "general_movsrc_operand" ""))]
6012 prepare_move_operands (operands, DFmode);
6013 if (TARGET_FPU_DOUBLE)
6015 emit_insn (gen_movdf_i4 (operands[0], operands[1]));
6020 ;; FIXME Although the movsf_i pattern is not used when there's an FPU,
6021 ;; it somehow influences some RA choices also on FPU targets.
6022 ;; For non-FPU targets it's actually not needed.
6023 (define_insn "movsf_i"
6024 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r, r, r,m,l,r")
6025 (match_operand:SF 1 "general_movsrc_operand" "r,G,FQ,mr,r,r,l"))]
6028 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
6029 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
6030 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
6031 && (arith_reg_operand (operands[0], SFmode)
6032 || arith_reg_operand (operands[1], SFmode))"
6041 [(set_attr "type" "move,move,pcload,load,store,move,move")
6042 (set_attr_alternative "length"
6045 (if_then_else (match_operand 1 "long_displacement_mem_operand")
6046 (const_int 4) (const_int 2))
6047 (if_then_else (match_operand 1 "long_displacement_mem_operand")
6048 (const_int 4) (const_int 2))
6049 (if_then_else (match_operand 0 "long_displacement_mem_operand")
6050 (const_int 4) (const_int 2))
6054 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
6055 ;; update_flow_info would not know where to put REG_EQUAL notes
6056 ;; when the destination changes mode.
6057 (define_insn "movsf_ie"
6058 [(set (match_operand:SF 0 "general_movdst_operand"
6059 "=f,r,f,f,fy, f,m, r, r,m,f,y,y,rf,r,y,<,y,y")
6060 (match_operand:SF 1 "general_movsrc_operand"
6061 " f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
6062 (use (reg:SI FPSCR_MODES_REG))
6063 (clobber (match_scratch:SI 2 "=X,X,X,X,&z, X,X, X, X,X,X,X,X, y,X,X,X,X,X"))]
6065 && (arith_reg_operand (operands[0], SFmode)
6066 || fpul_operand (operands[0], SFmode)
6067 || arith_reg_operand (operands[1], SFmode)
6068 || fpul_operand (operands[1], SFmode)
6069 || arith_reg_operand (operands[2], SImode))"
6089 ! move optimized away"
6090 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,
6091 store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil")
6092 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
6093 (set_attr_alternative "length"
6099 (if_then_else (match_operand 1 "displacement_mem_operand")
6100 (const_int 4) (const_int 2))
6101 (if_then_else (match_operand 0 "displacement_mem_operand")
6102 (const_int 4) (const_int 2))
6104 (if_then_else (match_operand 1 "long_displacement_mem_operand")
6105 (const_int 4) (const_int 2))
6106 (if_then_else (match_operand 0 "long_displacement_mem_operand")
6107 (const_int 4) (const_int 2))
6117 (set_attr_alternative "fp_mode"
6118 [(if_then_else (eq_attr "fmovd" "yes")
6119 (const_string "single") (const_string "none"))
6120 (const_string "none")
6121 (const_string "single")
6122 (const_string "single")
6123 (const_string "none")
6124 (if_then_else (eq_attr "fmovd" "yes")
6125 (const_string "single") (const_string "none"))
6126 (if_then_else (eq_attr "fmovd" "yes")
6127 (const_string "single") (const_string "none"))
6128 (const_string "none")
6129 (const_string "none")
6130 (const_string "none")
6131 (const_string "none")
6132 (const_string "none")
6133 (const_string "none")
6134 (const_string "none")
6135 (const_string "none")
6136 (const_string "none")
6137 (const_string "none")
6138 (const_string "none")
6139 (const_string "none")])])
6141 (define_insn_and_split "movsf_ie_ra"
6142 [(set (match_operand:SF 0 "general_movdst_operand"
6143 "=f,r,f,f,fy,f,m, r,r,m,f,y,y,rf,r,y,<,y,y")
6144 (match_operand:SF 1 "general_movsrc_operand"
6145 " f,r,G,H,FQ,m,f,FQ,m,r,y,f,>,fr,y,r,y,>,y"))
6146 (use (reg:SI FPSCR_MODES_REG))
6147 (clobber (match_scratch:SF 2 "=r,r,X,X,&z,r,r, X,r,r,r,r,r, y,r,r,r,r,r"))
6150 && (arith_reg_operand (operands[0], SFmode)
6151 || fpul_operand (operands[0], SFmode)
6152 || arith_reg_operand (operands[1], SFmode)
6153 || fpul_operand (operands[1], SFmode))"
6173 ! move optimized away"
6175 && sh_movsf_ie_ra_split_p (operands[0], operands[1], operands[2])"
6178 if (! rtx_equal_p (operands[0], operands[1]))
6180 emit_insn (gen_movsf_ie (operands[2], operands[1]));
6181 emit_insn (gen_movsf_ie (operands[0], operands[2]));
6184 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,
6185 store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil")
6186 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
6187 (set_attr_alternative "length"
6193 (if_then_else (match_operand 1 "displacement_mem_operand")
6194 (const_int 4) (const_int 2))
6195 (if_then_else (match_operand 0 "displacement_mem_operand")
6196 (const_int 4) (const_int 2))
6198 (if_then_else (match_operand 1 "long_displacement_mem_operand")
6199 (const_int 4) (const_int 2))
6200 (if_then_else (match_operand 0 "long_displacement_mem_operand")
6201 (const_int 4) (const_int 2))
6211 (set_attr_alternative "fp_mode"
6212 [(if_then_else (eq_attr "fmovd" "yes")
6213 (const_string "single") (const_string "none"))
6214 (const_string "none")
6215 (const_string "single")
6216 (const_string "single")
6217 (const_string "none")
6218 (if_then_else (eq_attr "fmovd" "yes")
6219 (const_string "single") (const_string "none"))
6220 (if_then_else (eq_attr "fmovd" "yes")
6221 (const_string "single") (const_string "none"))
6222 (const_string "none")
6223 (const_string "none")
6224 (const_string "none")
6225 (const_string "none")
6226 (const_string "none")
6227 (const_string "none")
6228 (const_string "none")
6229 (const_string "none")
6230 (const_string "none")
6231 (const_string "none")
6232 (const_string "none")
6233 (const_string "none")])])
6236 [(set (match_operand:SF 0 "register_operand" "")
6237 (match_operand:SF 1 "register_operand" ""))
6238 (use (reg:SI FPSCR_MODES_REG))
6239 (clobber (reg:SI FPUL_REG))]
6241 [(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
6242 (use (reg:SI FPSCR_MODES_REG))
6243 (clobber (scratch:SI))])
6244 (parallel [(set (match_dup 0) (reg:SF FPUL_REG))
6245 (use (reg:SI FPSCR_MODES_REG))
6246 (clobber (scratch:SI))])]
6249 (define_expand "movsf"
6250 [(set (match_operand:SF 0 "general_movdst_operand" "")
6251 (match_operand:SF 1 "general_movsrc_operand" ""))]
6254 prepare_move_operands (operands, SFmode);
6257 if (lra_in_progress)
6259 if (GET_CODE (operands[0]) == SCRATCH)
6261 emit_insn (gen_movsf_ie_ra (operands[0], operands[1]));
6265 emit_insn (gen_movsf_ie (operands[0], operands[1]));
6270 (define_expand "reload_insf__frn"
6271 [(parallel [(set (match_operand:SF 0 "register_operand" "=a")
6272 (match_operand:SF 1 "immediate_operand" "FQ"))
6273 (use (reg:SI FPSCR_MODES_REG))
6274 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
6278 (define_expand "reload_insi__i_fpul"
6279 [(parallel [(set (match_operand:SI 0 "fpul_operand" "=y")
6280 (match_operand:SI 1 "immediate_operand" "i"))
6281 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
6285 (define_insn "*movsi_y"
6286 [(set (match_operand:SI 0 "register_operand" "=y,y")
6287 (match_operand:SI 1 "immediate_operand" "Qi,I08"))
6288 (clobber (match_scratch:SI 2 "=&z,r"))]
6290 && (reload_in_progress || reload_completed)"
6292 [(set_attr "length" "4")
6293 (set_attr "type" "pcload,move")])
6296 [(set (match_operand:SI 0 "register_operand" "")
6297 (match_operand:SI 1 "immediate_operand" ""))
6298 (clobber (match_operand:SI 2 "register_operand" ""))]
6300 [(set (match_dup 2) (match_dup 1))
6301 (set (match_dup 0) (match_dup 2))]
6304 ;; ------------------------------------------------------------------------
6305 ;; Define the real conditional branch instructions.
6306 ;; ------------------------------------------------------------------------
6308 (define_expand "branch_true"
6309 [(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
6310 (label_ref (match_operand 0))
6314 (define_expand "branch_false"
6315 [(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
6316 (label_ref (match_operand 0))
6320 (define_insn_and_split "*cbranch_t"
6321 [(set (pc) (if_then_else (match_operand 1 "cbranch_treg_value")
6322 (label_ref (match_operand 0))
6326 return output_branch (sh_eval_treg_value (operands[1]), insn, operands);
6331 /* Try to canonicalize the branch condition if it is not one of:
6332 (ne (reg:SI T_REG) (const_int 0))
6333 (eq (reg:SI T_REG) (const_int 0))
6335 Instead of splitting out a new insn, we modify the current insn's
6336 operands as needed. This preserves things such as REG_DEAD notes. */
6338 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
6339 && REG_P (XEXP (operands[1], 0)) && REGNO (XEXP (operands[1], 0)) == T_REG
6340 && XEXP (operands[1], 1) == const0_rtx)
6343 int branch_cond = sh_eval_treg_value (operands[1]);
6344 rtx new_cond_rtx = NULL_RTX;
6346 if (branch_cond == 0)
6347 new_cond_rtx = gen_rtx_EQ (VOIDmode, get_t_reg_rtx (), const0_rtx);
6348 else if (branch_cond == 1)
6349 new_cond_rtx = gen_rtx_NE (VOIDmode, get_t_reg_rtx (), const0_rtx);
6351 if (new_cond_rtx != NULL_RTX)
6352 validate_change (curr_insn, &XEXP (XEXP (PATTERN (curr_insn), 1), 0),
6353 new_cond_rtx, false);
6356 [(set_attr "type" "cbranch")])
6358 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
6359 ;; which destination is too far away.
6360 ;; The const_int_operand is distinct for each branch target; it avoids
6361 ;; unwanted matches with redundant_insn.
6362 (define_insn "block_branch_redirect"
6363 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BBR))]
6366 [(set_attr "length" "0")])
6368 ;; This one has the additional purpose to record a possible scratch register
6369 ;; for the following branch.
6370 ;; ??? Unfortunately, just setting the scratch register is not good enough,
6371 ;; because the insn then might be deemed dead and deleted. And we can't
6372 ;; make the use in the jump insn explicit because that would disable
6373 ;; delay slot scheduling from the target.
6374 (define_insn "indirect_jump_scratch"
6375 [(set (match_operand:SI 0 "register_operand" "=r")
6376 (unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))
6377 (set (pc) (unspec [(const_int 0)] UNSPEC_BBR))]
6380 [(set_attr "length" "0")])
6382 ;; This one is used to preemt an insn from beyond the bra / braf / jmp
6383 ;; being pulled into the delay slot of a condbranch that has been made to
6384 ;; jump around the unconditional jump because it was out of range.
6385 (define_insn "stuff_delay_slot"
6387 (unspec [(match_operand:SI 0 "const_int_operand" "") (pc)
6388 (match_operand:SI 1 "const_int_operand" "")] UNSPEC_BBR))]
6391 [(set_attr "length" "0")
6392 (set_attr "cond_delay_slot" "yes")])
6394 ;; Conditional branch insns
6396 ; operand 0 is the loop count pseudo register
6397 ; operand 1 is the label to jump to at the top of the loop
6398 (define_expand "doloop_end"
6399 [(parallel [(set (pc)
6400 (if_then_else (ne:SI (match_operand:SI 0 "" "")
6402 (label_ref (match_operand 1 "" ""))
6405 (plus:SI (match_dup 0) (const_int -1)))
6406 (clobber (reg:SI T_REG))])]
6409 if (GET_MODE (operands[0]) != SImode)
6411 emit_jump_insn (gen_doloop_end_split (operands[0], operands[1], operands[0]));
6415 (define_insn_and_split "doloop_end_split"
6417 (if_then_else (ne:SI (match_operand:SI 2 "arith_reg_dest" "0")
6419 (label_ref (match_operand 1 "" ""))
6421 (set (match_operand:SI 0 "arith_reg_dest" "=r")
6422 (plus:SI (match_dup 2) (const_int -1)))
6423 (clobber (reg:SI T_REG))]
6427 [(parallel [(set (reg:SI T_REG)
6428 (eq:SI (match_dup 2) (const_int 1)))
6429 (set (match_dup 0) (plus:SI (match_dup 2) (const_int -1)))])
6430 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
6431 (label_ref (match_dup 1))
6434 [(set_attr "type" "cbranch")])
6436 ;; ------------------------------------------------------------------------
6437 ;; Jump and linkage insns
6438 ;; ------------------------------------------------------------------------
6440 (define_insn "jump_compact"
6442 (label_ref (match_operand 0 "" "")))]
6443 "TARGET_SH1 && !CROSSING_JUMP_P (insn)"
6445 /* The length is 16 if the delay slot is unfilled. */
6446 if (get_attr_length(insn) > 4)
6447 return output_far_jump(insn, operands[0]);
6451 [(set_attr "type" "jump")
6452 (set_attr "needs_delay_slot" "yes")])
6454 (define_insn "*jump_compact_crossing"
6456 (label_ref (match_operand 0 "" "")))]
6458 && flag_reorder_blocks_and_partition
6459 && CROSSING_JUMP_P (insn)"
6461 /* The length is 16 if the delay slot is unfilled. */
6462 return output_far_jump(insn, operands[0]);
6464 [(set_attr "type" "jump")
6465 (set_attr "length" "16")])
6467 (define_expand "jump"
6469 (label_ref (match_operand 0 "" "")))]
6472 emit_jump_insn (gen_jump_compact (operands[0]));
6476 (define_insn "calli"
6477 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
6478 (match_operand 1 "" ""))
6479 (use (reg:SI FPSCR_MODES_REG))
6480 (clobber (reg:SI PR_REG))]
6481 "TARGET_SH1 && !TARGET_FDPIC"
6483 if (TARGET_SH2A && dbr_sequence_length () == 0)
6488 [(set_attr "type" "call")
6489 (set (attr "fp_mode")
6490 (if_then_else (eq_attr "fpu_single" "yes")
6491 (const_string "single") (const_string "double")))
6492 (set_attr "needs_delay_slot" "yes")
6493 (set_attr "fp_set" "unknown")])
6495 (define_insn "calli_fdpic"
6496 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
6498 (use (reg:SI FPSCR_MODES_REG))
6499 (use (reg:SI PIC_REG))
6500 (clobber (reg:SI PR_REG))]
6503 if (TARGET_SH2A && dbr_sequence_length () == 0)
6508 [(set_attr "type" "call")
6509 (set (attr "fp_mode")
6510 (if_then_else (eq_attr "fpu_single" "yes")
6511 (const_string "single") (const_string "double")))
6512 (set_attr "needs_delay_slot" "yes")
6513 (set_attr "fp_set" "unknown")])
6515 ;; This is TBR relative jump instruction for SH2A architecture.
6516 ;; Its use is enabled by assigning an attribute "function_vector"
6517 ;; and the vector number to a function during its declaration.
6518 (define_insn "calli_tbr_rel"
6519 [(call (mem (match_operand:SI 0 "symbol_ref_operand" ""))
6520 (match_operand 1 "" ""))
6521 (use (reg:SI FPSCR_MODES_REG))
6522 (clobber (reg:SI PR_REG))]
6523 "TARGET_SH2A && sh2a_is_function_vector_call (operands[0])"
6525 unsigned HOST_WIDE_INT vect_num;
6526 vect_num = sh2a_get_function_vector_number (operands[0]);
6527 operands[2] = GEN_INT (vect_num * 4);
6529 return "jsr/n @@(%O2,tbr)";
6531 [(set_attr "type" "call")
6532 (set (attr "fp_mode")
6533 (if_then_else (eq_attr "fpu_single" "yes")
6534 (const_string "single") (const_string "double")))
6535 (set_attr "needs_delay_slot" "no")
6536 (set_attr "fp_set" "unknown")])
6538 ;; This is a pc-rel call, using bsrf, for use with PIC.
6539 (define_insn "calli_pcrel"
6540 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
6541 (match_operand 1 "" ""))
6542 (use (reg:SI FPSCR_MODES_REG))
6543 (use (reg:SI PIC_REG))
6544 (use (match_operand 2 "" ""))
6545 (clobber (reg:SI PR_REG))]
6548 return "bsrf %0" "\n"
6551 [(set_attr "type" "call")
6552 (set (attr "fp_mode")
6553 (if_then_else (eq_attr "fpu_single" "yes")
6554 (const_string "single") (const_string "double")))
6555 (set_attr "needs_delay_slot" "yes")
6556 (set_attr "fp_set" "unknown")])
6558 (define_insn_and_split "call_pcrel"
6559 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
6560 (match_operand 1 "" ""))
6561 (use (reg:SI FPSCR_MODES_REG))
6562 (use (reg:SI PIC_REG))
6563 (clobber (reg:SI PR_REG))
6564 (clobber (match_scratch:SI 2 "=&r"))]
6570 rtx lab = PATTERN (gen_call_site ());
6572 sh_expand_sym_label2reg (operands[2], operands[0], lab, false);
6573 emit_call_insn (gen_calli_pcrel (operands[2], operands[1], copy_rtx (lab)));
6576 [(set_attr "type" "call")
6577 (set (attr "fp_mode")
6578 (if_then_else (eq_attr "fpu_single" "yes")
6579 (const_string "single") (const_string "double")))
6580 (set_attr "needs_delay_slot" "yes")
6581 (set_attr "fp_set" "unknown")])
6583 (define_insn "call_valuei"
6584 [(set (match_operand 0 "" "=rf")
6585 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
6586 (match_operand 2 "" "")))
6587 (use (reg:SI FPSCR_MODES_REG))
6588 (clobber (reg:SI PR_REG))]
6589 "TARGET_SH1 && !TARGET_FDPIC"
6591 if (TARGET_SH2A && dbr_sequence_length () == 0)
6596 [(set_attr "type" "call")
6597 (set (attr "fp_mode")
6598 (if_then_else (eq_attr "fpu_single" "yes")
6599 (const_string "single") (const_string "double")))
6600 (set_attr "needs_delay_slot" "yes")
6601 (set_attr "fp_set" "unknown")])
6603 (define_insn "call_valuei_fdpic"
6604 [(set (match_operand 0 "" "=rf")
6605 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
6607 (use (reg:SI FPSCR_REG))
6608 (use (reg:SI PIC_REG))
6609 (clobber (reg:SI PR_REG))]
6612 if (TARGET_SH2A && dbr_sequence_length () == 0)
6617 [(set_attr "type" "call")
6618 (set (attr "fp_mode")
6619 (if_then_else (eq_attr "fpu_single" "yes")
6620 (const_string "single") (const_string "double")))
6621 (set_attr "needs_delay_slot" "yes")
6622 (set_attr "fp_set" "unknown")])
6624 ;; This is TBR relative jump instruction for SH2A architecture.
6625 ;; Its use is enabled by assigning an attribute "function_vector"
6626 ;; and the vector number to a function during its declaration.
6627 (define_insn "call_valuei_tbr_rel"
6628 [(set (match_operand 0 "" "=rf")
6629 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
6630 (match_operand 2 "" "")))
6631 (use (reg:SI FPSCR_MODES_REG))
6632 (clobber (reg:SI PR_REG))]
6633 "TARGET_SH2A && sh2a_is_function_vector_call (operands[1])"
6635 unsigned HOST_WIDE_INT vect_num;
6636 vect_num = sh2a_get_function_vector_number (operands[1]);
6637 operands[3] = GEN_INT (vect_num * 4);
6639 return "jsr/n @@(%O3,tbr)";
6641 [(set_attr "type" "call")
6642 (set (attr "fp_mode")
6643 (if_then_else (eq_attr "fpu_single" "yes")
6644 (const_string "single") (const_string "double")))
6645 (set_attr "needs_delay_slot" "no")
6646 (set_attr "fp_set" "unknown")])
6648 (define_insn "call_valuei_pcrel"
6649 [(set (match_operand 0 "" "=rf")
6650 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
6651 (match_operand 2 "" "")))
6652 (use (reg:SI FPSCR_MODES_REG))
6653 (use (reg:SI PIC_REG))
6654 (use (match_operand 3 "" ""))
6655 (clobber (reg:SI PR_REG))]
6658 return "bsrf %1" "\n"
6661 [(set_attr "type" "call")
6662 (set (attr "fp_mode")
6663 (if_then_else (eq_attr "fpu_single" "yes")
6664 (const_string "single") (const_string "double")))
6665 (set_attr "needs_delay_slot" "yes")
6666 (set_attr "fp_set" "unknown")])
6668 (define_insn_and_split "call_value_pcrel"
6669 [(set (match_operand 0 "" "=rf")
6670 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
6671 (match_operand 2 "" "")))
6672 (use (reg:SI FPSCR_MODES_REG))
6673 (use (reg:SI PIC_REG))
6674 (clobber (reg:SI PR_REG))
6675 (clobber (match_scratch:SI 3 "=&r"))]
6681 rtx lab = PATTERN (gen_call_site ());
6683 sh_expand_sym_label2reg (operands[3], operands[1], lab, false);
6684 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
6685 operands[2], copy_rtx (lab)));
6688 [(set_attr "type" "call")
6689 (set (attr "fp_mode")
6690 (if_then_else (eq_attr "fpu_single" "yes")
6691 (const_string "single") (const_string "double")))
6692 (set_attr "needs_delay_slot" "yes")
6693 (set_attr "fp_set" "unknown")])
6695 (define_expand "call"
6696 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
6697 (match_operand 1 "" ""))
6698 (match_operand 2 "" "")
6699 (use (reg:SI FPSCR_MODES_REG))
6700 (clobber (reg:SI PR_REG))])]
6705 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
6706 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
6709 if (!flag_pic && TARGET_SH2A
6710 && MEM_P (operands[0])
6711 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6713 if (sh2a_is_function_vector_call (XEXP (operands[0], 0)))
6715 emit_call_insn (gen_calli_tbr_rel (XEXP (operands[0], 0),
6720 if (flag_pic && TARGET_SH2
6721 && MEM_P (operands[0])
6722 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6724 emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1]));
6729 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
6730 operands[1] = operands[2];
6735 operands[0] = sh_load_function_descriptor (operands[0]);
6736 emit_call_insn (gen_calli_fdpic (operands[0], operands[1]));
6739 emit_call_insn (gen_calli (operands[0], operands[1]));
6743 (define_expand "call_value"
6744 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
6745 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
6746 (match_operand 2 "" "")))
6747 (match_operand 3 "" "")
6748 (use (reg:SI FPSCR_MODES_REG))
6749 (clobber (reg:SI PR_REG))])]
6754 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
6755 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
6758 if (!flag_pic && TARGET_SH2A
6759 && MEM_P (operands[1])
6760 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6762 if (sh2a_is_function_vector_call (XEXP (operands[1], 0)))
6764 emit_call_insn (gen_call_valuei_tbr_rel (operands[0],
6765 XEXP (operands[1], 0), operands[2]));
6769 if (flag_pic && TARGET_SH2
6770 && MEM_P (operands[1])
6771 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6773 emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0),
6778 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
6782 operands[1] = sh_load_function_descriptor (operands[1]);
6783 emit_call_insn (gen_call_valuei_fdpic (operands[0], operands[1],
6787 emit_call_insn (gen_call_valuei (operands[0], operands[1], operands[2]));
6791 (define_insn "sibcalli"
6792 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
6793 (match_operand 1 "" ""))
6794 (use (reg:SI FPSCR_MODES_REG))
6796 "TARGET_SH1 && !TARGET_FDPIC"
6798 [(set_attr "needs_delay_slot" "yes")
6799 (set (attr "fp_mode")
6800 (if_then_else (eq_attr "fpu_single" "yes")
6801 (const_string "single") (const_string "double")))
6802 (set_attr "type" "jump_ind")])
6804 (define_insn "sibcalli_fdpic"
6805 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
6807 (use (reg:SI FPSCR_MODES_REG))
6808 (use (reg:SI PIC_REG))
6812 [(set_attr "needs_delay_slot" "yes")
6813 (set (attr "fp_mode")
6814 (if_then_else (eq_attr "fpu_single" "yes")
6815 (const_string "single") (const_string "double")))
6816 (set_attr "type" "jump_ind")])
6818 (define_insn "sibcalli_pcrel"
6819 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
6820 (match_operand 1 "" ""))
6821 (use (match_operand 2 "" ""))
6822 (use (reg:SI FPSCR_MODES_REG))
6824 "TARGET_SH2 && !TARGET_FDPIC"
6826 return "braf %0" "\n"
6829 [(set_attr "needs_delay_slot" "yes")
6830 (set (attr "fp_mode")
6831 (if_then_else (eq_attr "fpu_single" "yes")
6832 (const_string "single") (const_string "double")))
6833 (set_attr "type" "jump_ind")])
6835 (define_insn "sibcalli_pcrel_fdpic"
6836 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
6838 (use (match_operand 2))
6839 (use (reg:SI FPSCR_MODES_REG))
6840 (use (reg:SI PIC_REG))
6842 "TARGET_SH2 && TARGET_FDPIC"
6844 return "braf %0" "\n"
6847 [(set_attr "needs_delay_slot" "yes")
6848 (set (attr "fp_mode")
6849 (if_then_else (eq_attr "fpu_single" "yes")
6850 (const_string "single") (const_string "double")))
6851 (set_attr "type" "jump_ind")])
6853 ;; This uses an unspec to describe that the symbol_ref is very close.
6854 (define_insn "sibcalli_thunk"
6855 [(call (mem:SI (unspec:SI [(match_operand:SI 0 "symbol_ref_operand" "")]
6857 (match_operand 1 "" ""))
6858 (use (reg:SI FPSCR_MODES_REG))
6862 [(set_attr "needs_delay_slot" "yes")
6863 (set (attr "fp_mode")
6864 (if_then_else (eq_attr "fpu_single" "yes")
6865 (const_string "single") (const_string "double")))
6866 (set_attr "type" "jump")
6867 (set_attr "length" "2")])
6869 (define_insn_and_split "sibcall_pcrel"
6870 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
6871 (match_operand 1 "" ""))
6872 (use (reg:SI FPSCR_MODES_REG))
6873 (clobber (match_scratch:SI 2 "=&k"))
6875 "TARGET_SH2 && !TARGET_FDPIC"
6880 rtx lab = PATTERN (gen_call_site ());
6883 sh_expand_sym_label2reg (operands[2], operands[0], lab, true);
6884 call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
6886 SIBLING_CALL_P (call_insn) = 1;
6889 [(set_attr "needs_delay_slot" "yes")
6890 (set (attr "fp_mode")
6891 (if_then_else (eq_attr "fpu_single" "yes")
6892 (const_string "single") (const_string "double")))
6893 (set_attr "type" "jump_ind")])
6895 (define_insn_and_split "sibcall_pcrel_fdpic"
6896 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand"))
6898 (use (reg:SI FPSCR_MODES_REG))
6899 (use (reg:SI PIC_REG))
6900 (clobber (match_scratch:SI 2 "=k"))
6902 "TARGET_SH2 && TARGET_FDPIC"
6904 "&& reload_completed"
6907 rtx lab = PATTERN (gen_call_site ());
6909 sh_expand_sym_label2reg (operands[2], operands[0], lab, true);
6910 rtx i = emit_call_insn (gen_sibcalli_pcrel_fdpic (operands[2], operands[1],
6912 SIBLING_CALL_P (i) = 1;
6915 [(set_attr "needs_delay_slot" "yes")
6916 (set (attr "fp_mode")
6917 (if_then_else (eq_attr "fpu_single" "yes")
6918 (const_string "single") (const_string "double")))
6919 (set_attr "type" "jump_ind")])
6921 (define_expand "sibcall"
6923 [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
6924 (match_operand 1 "" ""))
6925 (match_operand 2 "" "")
6926 (use (reg:SI FPSCR_MODES_REG))
6932 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
6933 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
6936 if (flag_pic && TARGET_SH2
6937 && MEM_P (operands[0])
6938 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
6939 /* The PLT needs the PIC register, but the epilogue would have
6940 to restore it, so we can only use PC-relative PIC calls for
6941 static functions. */
6942 && SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
6945 emit_call_insn (gen_sibcall_pcrel_fdpic (XEXP (operands[0], 0),
6948 emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
6952 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
6956 operands[0] = sh_load_function_descriptor (operands[0]);
6957 emit_call_insn (gen_sibcalli_fdpic (operands[0], operands[1]));
6960 emit_call_insn (gen_sibcalli (operands[0], operands[1]));
6964 (define_insn "sibcall_valuei"
6965 [(set (match_operand 0 "" "=rf")
6966 (call (mem:SI (match_operand:SI 1 "register_operand" "k"))
6967 (match_operand 2 "" "")))
6968 (use (reg:SI FPSCR_MODES_REG))
6970 "TARGET_SH1 && !TARGET_FDPIC"
6972 [(set_attr "needs_delay_slot" "yes")
6973 (set (attr "fp_mode")
6974 (if_then_else (eq_attr "fpu_single" "yes")
6975 (const_string "single") (const_string "double")))
6976 (set_attr "type" "jump_ind")])
6978 (define_insn "sibcall_valuei_fdpic"
6979 [(set (match_operand 0 "" "=rf")
6980 (call (mem:SI (match_operand:SI 1 "register_operand" "k"))
6982 (use (reg:SI FPSCR_MODES_REG))
6983 (use (reg:SI PIC_REG))
6987 [(set_attr "needs_delay_slot" "yes")
6988 (set (attr "fp_mode")
6989 (if_then_else (eq_attr "fpu_single" "yes")
6990 (const_string "single") (const_string "double")))
6991 (set_attr "type" "jump_ind")])
6993 (define_insn "sibcall_valuei_pcrel"
6994 [(set (match_operand 0 "" "=rf")
6995 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k"))
6996 (match_operand 2 "" "")))
6997 (use (match_operand 3 "" ""))
6998 (use (reg:SI FPSCR_MODES_REG))
7000 "TARGET_SH2 && !TARGET_FDPIC"
7002 return "braf %1" "\n"
7005 [(set_attr "needs_delay_slot" "yes")
7006 (set (attr "fp_mode")
7007 (if_then_else (eq_attr "fpu_single" "yes")
7008 (const_string "single") (const_string "double")))
7009 (set_attr "type" "jump_ind")])
7011 (define_insn "sibcall_valuei_pcrel_fdpic"
7012 [(set (match_operand 0 "" "=rf")
7013 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k"))
7015 (use (match_operand 3))
7016 (use (reg:SI FPSCR_MODES_REG))
7017 (use (reg:SI PIC_REG))
7019 "TARGET_SH2 && TARGET_FDPIC"
7021 return "braf %1" "\n"
7024 [(set_attr "needs_delay_slot" "yes")
7025 (set (attr "fp_mode")
7026 (if_then_else (eq_attr "fpu_single" "yes")
7027 (const_string "single") (const_string "double")))
7028 (set_attr "type" "jump_ind")])
7030 ;; sibcall_value_pcrel used to have a =&k clobber for the scratch register
7031 ;; that it needs for the branch address. This causes troubles when there
7032 ;; is a big overlap of argument and return value registers. Hence, use a
7033 ;; fixed call clobbered register for the address. See also PR 67260.
7034 (define_insn_and_split "sibcall_value_pcrel"
7035 [(set (match_operand 0 "" "=rf")
7036 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
7037 (match_operand 2 "" "")))
7038 (use (reg:SI FPSCR_MODES_REG))
7039 (clobber (reg:SI R1_REG))
7041 "TARGET_SH2 && !TARGET_FDPIC"
7046 rtx lab = PATTERN (gen_call_site ());
7049 operands[3] = gen_rtx_REG (SImode, R1_REG);
7051 sh_expand_sym_label2reg (operands[3], operands[1], lab, true);
7052 call_insn = emit_call_insn (gen_sibcall_valuei_pcrel (operands[0],
7056 SIBLING_CALL_P (call_insn) = 1;
7059 [(set_attr "needs_delay_slot" "yes")
7060 (set (attr "fp_mode")
7061 (if_then_else (eq_attr "fpu_single" "yes")
7062 (const_string "single") (const_string "double")))
7063 (set_attr "type" "jump_ind")])
7065 ;; Like for sibcall_value_pcrel, use a fixed call clobbered register for
7066 ;; the branch address.
7067 (define_insn_and_split "sibcall_value_pcrel_fdpic"
7068 [(set (match_operand 0 "" "=rf")
7069 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand"))
7071 (use (reg:SI FPSCR_MODES_REG))
7072 (use (reg:SI PIC_REG))
7073 (clobber (reg:SI R1_REG))
7075 "TARGET_SH2 && TARGET_FDPIC"
7077 "&& reload_completed"
7080 rtx lab = PATTERN (gen_call_site ());
7082 operands[3] = gen_rtx_REG (SImode, R1_REG);
7084 sh_expand_sym_label2reg (operands[3], operands[1], lab, true);
7085 rtx i = emit_call_insn (gen_sibcall_valuei_pcrel_fdpic (operands[0],
7089 SIBLING_CALL_P (i) = 1;
7092 [(set_attr "needs_delay_slot" "yes")
7093 (set (attr "fp_mode")
7094 (if_then_else (eq_attr "fpu_single" "yes")
7095 (const_string "single") (const_string "double")))
7096 (set_attr "type" "jump_ind")])
7098 (define_expand "sibcall_value"
7100 [(set (match_operand 0 "arith_reg_operand" "")
7101 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
7102 (match_operand 2 "" "")))
7103 (match_operand 3 "" "")
7104 (use (reg:SI FPSCR_MODES_REG))
7110 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
7111 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
7114 if (flag_pic && TARGET_SH2
7115 && MEM_P (operands[1])
7116 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
7117 /* The PLT needs the PIC register, but the epilogue would have
7118 to restore it, so we can only use PC-relative PIC calls for
7119 static functions. */
7120 && SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
7123 emit_call_insn (gen_sibcall_value_pcrel_fdpic (operands[0],
7124 XEXP (operands[1], 0),
7127 emit_call_insn (gen_sibcall_value_pcrel (operands[0],
7128 XEXP (operands[1], 0),
7133 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
7137 operands[1] = sh_load_function_descriptor (operands[1]);
7138 emit_call_insn (gen_sibcall_valuei_fdpic (operands[0], operands[1],
7142 emit_call_insn (gen_sibcall_valuei (operands[0], operands[1], operands[2]));
7146 (define_expand "sibcall_epilogue"
7150 sh_expand_epilogue (true);
7154 (define_insn "indirect_jump_compact"
7156 (match_operand:SI 0 "arith_reg_operand" "r"))]
7159 [(set_attr "needs_delay_slot" "yes")
7160 (set_attr "type" "jump_ind")])
7162 (define_expand "indirect_jump"
7164 (match_operand 0 "register_operand" ""))]
7167 if (GET_MODE (operands[0]) != Pmode)
7168 operands[0] = gen_rtx_SUBREG (Pmode, operands[0], 0);
7171 ;; The use of operand 1 / 2 helps us distinguish case table jumps
7172 ;; which can be present in structured code from indirect jumps which can not
7173 ;; be present in structured code. This allows -fprofile-arcs to work.
7175 ;; For SH1 processors.
7176 (define_insn "casesi_jump_1"
7178 (match_operand:SI 0 "register_operand" "r"))
7179 (use (label_ref (match_operand 1 "" "")))]
7182 [(set_attr "needs_delay_slot" "yes")
7183 (set_attr "type" "jump_ind")])
7185 ;; For all later processors.
7186 (define_insn "casesi_jump_2"
7187 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
7188 (label_ref (match_operand 1 "" ""))))
7189 (use (label_ref (match_operand 2 "" "")))]
7191 && (! INSN_UID (operands[1])
7192 || prev_real_insn (as_a<rtx_insn *> (operands[1])) == insn)"
7194 [(set_attr "needs_delay_slot" "yes")
7195 (set_attr "type" "jump_ind")])
7197 ;; Call subroutine returning any type.
7198 ;; ??? This probably doesn't work.
7199 (define_expand "untyped_call"
7200 [(parallel [(call (match_operand 0 "" "")
7202 (match_operand 1 "" "")
7203 (match_operand 2 "" "")])]
7204 "TARGET_SH2E || TARGET_SH2A"
7206 /* RA does not know that the call sets the function value registers.
7207 We avoid problems by claiming that those registers are clobbered
7209 for (int i = 0; i < XVECLEN (operands[2], 0); i++)
7210 emit_clobber (SET_SRC (XVECEXP (operands[2], 0, i)));
7212 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
7214 for (int i = 0; i < XVECLEN (operands[2], 0); i++)
7216 rtx set = XVECEXP (operands[2], 0, i);
7217 emit_move_insn (SET_DEST (set), SET_SRC (set));
7220 /* The optimizer does not know that the call sets the function value
7221 registers we stored in the result block. We avoid problems by
7222 claiming that all hard registers are used and clobbered at this
7224 emit_insn (gen_blockage ());
7229 ;; ------------------------------------------------------------------------
7231 ;; ------------------------------------------------------------------------
7234 [(set (reg:SI T_REG)
7235 (eq:SI (match_operand:SI 1 "arith_reg_dest" "0") (const_int 1)))
7236 (set (match_operand:SI 0 "arith_reg_dest" "=r")
7237 (plus:SI (match_dup 1) (const_int -1)))]
7240 [(set_attr "type" "arith")])
7247 ;; Load address of a label. This is only generated by the casesi expand,
7248 ;; and by machine_dependent_reorg (fixing up fp moves).
7249 ;; This must use unspec, because this only works for labels that are
7252 [(set (reg:SI R0_REG)
7253 (unspec:SI [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
7256 [(set_attr "in_delay_slot" "no")
7257 (set_attr "type" "arith")])
7259 ;; machine_dependent_reorg will make this a `mova'.
7260 (define_insn "mova_const"
7261 [(set (reg:SI R0_REG)
7262 (unspec:SI [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
7265 [(set_attr "in_delay_slot" "no")
7266 (set_attr "type" "arith")])
7268 ;; Loads of the GOTPC relocation values must not be optimized away
7269 ;; by e.g. any kind of CSE and must stay as they are. Although there
7270 ;; are other various ways to ensure this, we use an artificial counter
7271 ;; operand to generate unique symbols.
7272 (define_expand "GOTaddr2picreg"
7273 [(set (reg:SI R0_REG)
7274 (unspec:SI [(const:SI (unspec:SI [(match_dup 2)
7275 (match_operand:SI 0 "" "")]
7276 UNSPEC_PIC))] UNSPEC_MOVA))
7278 (const:SI (unspec:SI [(match_dup 2) (match_dup 0)] UNSPEC_PIC)))
7279 (set (match_dup 1) (plus:SI (match_dup 1) (reg:SI R0_REG)))]
7282 if (TARGET_VXWORKS_RTP)
7284 rtx gott_base = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE);
7285 rtx gott_index = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7286 emit_insn (gen_vxworks_picreg (gott_base, gott_index));
7292 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
7293 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
7297 operands[1] = gen_rtx_REG (Pmode, PIC_REG);
7298 operands[2] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
7301 ;; A helper for GOTaddr2picreg to finish up the initialization of the
7303 (define_expand "vxworks_picreg"
7304 [(set (reg:SI PIC_REG)
7305 (const:SI (unspec:SI [(match_operand:SI 0 "" "")] UNSPEC_PIC)))
7306 (set (reg:SI R0_REG)
7307 (const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PIC)))
7308 (set (reg:SI PIC_REG)
7309 (mem:SI (reg:SI PIC_REG)))
7310 (set (reg:SI PIC_REG)
7311 (mem:SI (plus:SI (reg:SI PIC_REG)
7313 "TARGET_VXWORKS_RTP")
7315 (define_expand "builtin_setjmp_receiver"
7316 [(match_operand 0 "" "")]
7319 emit_insn (gen_GOTaddr2picreg (const0_rtx));
7323 (define_expand "call_site"
7324 [(unspec [(match_dup 0)] UNSPEC_CALLER)]
7327 static HOST_WIDE_INT i = 0;
7328 operands[0] = GEN_INT (i);
7332 ;; op0 = op1 + r12 but hide it before reload completed. See the comment
7333 ;; in symGOT_load expand.
7334 (define_insn_and_split "chk_guard_add"
7335 [(set (match_operand:SI 0 "register_operand" "=&r")
7336 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
7341 "TARGET_SH1 && reload_completed"
7342 [(set (match_dup 0) (reg:SI PIC_REG))
7343 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
7345 [(set_attr "type" "arith")])
7347 (define_expand "sym_label2reg"
7348 [(set (match_operand:SI 0 "" "")
7349 (const:SI (unspec:SI [(match_operand:SI 1 "" "")
7350 (const (plus:SI (match_operand:SI 2 "" "")
7355 (define_expand "symPCREL_label2reg"
7356 [(set (match_operand:SI 0 "" "")
7359 [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PCREL))
7360 (const:SI (plus:SI (match_operand:SI 2 "" "")
7361 (const_int 2)))] UNSPEC_PCREL_SYMOFF)))]
7365 (define_expand "symGOT_load"
7366 [(set (match_dup 2) (match_operand 1 "" ""))
7367 (set (match_dup 3) (plus (match_dup 2) (reg PIC_REG)))
7368 (set (match_operand 0 "" "") (mem (match_dup 3)))]
7372 bool stack_chk_guard_p = false;
7374 rtx picreg = TARGET_FDPIC ? sh_get_fdpic_reg_initial_val ()
7375 : gen_rtx_REG (Pmode, PIC_REG);
7377 operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
7378 operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
7381 && flag_stack_protect
7382 && GET_CODE (operands[1]) == CONST
7383 && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
7384 && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == SYMBOL_REF
7385 && strcmp (XSTR (XVECEXP (XEXP (operands[1], 0), 0, 0), 0),
7386 "__stack_chk_guard") == 0)
7387 stack_chk_guard_p = true;
7389 emit_move_insn (operands[2], operands[1]);
7391 /* When stack protector inserts codes after the result is set to
7392 R0, @(rX, r12) will cause a spill failure for R0. Use a unspec
7393 insn to avoid combining (set A (plus rX r12)) and (set op0 (mem A))
7394 when rX is a GOT address for the guard symbol. Ugly but doesn't
7395 matter because this is a rare situation. */
7396 if (stack_chk_guard_p)
7397 emit_insn (gen_chk_guard_add (operands[3], operands[2]));
7399 emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2], picreg));
7401 /* N.B. This is not constant for a GOTPLT relocation. */
7402 mem = gen_rtx_MEM (Pmode, operands[3]);
7403 MEM_NOTRAP_P (mem) = 1;
7404 /* ??? Should we have a special alias set for the GOT? */
7405 emit_move_insn (operands[0], mem);
7410 (define_expand "sym2GOT"
7411 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOT))]
7415 (define_expand "symGOT2reg"
7416 [(match_operand 0 "" "") (match_operand 1 "" "")]
7421 gotsym = gen_sym2GOT (operands[1]);
7422 PUT_MODE (gotsym, Pmode);
7423 insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
7425 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
7430 (define_expand "sym2GOTFUNCDESC"
7431 [(const (unspec [(match_operand 0)] UNSPEC_GOTFUNCDESC))]
7434 (define_expand "symGOTFUNCDESC2reg"
7435 [(match_operand 0) (match_operand 1)]
7438 rtx gotsym = gen_sym2GOTFUNCDESC (operands[1]);
7439 PUT_MODE (gotsym, Pmode);
7440 rtx insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
7442 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
7447 (define_expand "symGOTPLT2reg"
7448 [(match_operand 0 "" "") (match_operand 1 "" "")]
7451 rtx pltsym = gen_rtx_CONST (Pmode,
7452 gen_rtx_UNSPEC (Pmode,
7453 gen_rtvec (1, operands[1]),
7455 emit_insn (gen_symGOT_load (operands[0], pltsym));
7459 (define_expand "sym2GOTOFF"
7460 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTOFF))]
7464 (define_expand "symGOTOFF2reg"
7465 [(match_operand 0 "" "") (match_operand 1 "" "")]
7469 rtx t = (!can_create_pseudo_p ()
7471 : gen_reg_rtx (GET_MODE (operands[0])));
7473 rtx picreg = TARGET_FDPIC ? sh_get_fdpic_reg_initial_val ()
7474 : gen_rtx_REG (Pmode, PIC_REG);
7476 gotoffsym = gen_sym2GOTOFF (operands[1]);
7477 PUT_MODE (gotoffsym, Pmode);
7478 emit_move_insn (t, gotoffsym);
7479 rtx_insn *insn = emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, picreg));
7481 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
7486 (define_expand "sym2GOTOFFFUNCDESC"
7487 [(const (unspec [(match_operand 0)] UNSPEC_GOTOFFFUNCDESC))]
7490 (define_expand "symGOTOFFFUNCDESC2reg"
7491 [(match_operand 0) (match_operand 1)]
7494 rtx picreg = sh_get_fdpic_reg_initial_val ();
7495 rtx t = !can_create_pseudo_p ()
7497 : gen_reg_rtx (GET_MODE (operands[0]));
7499 rtx gotoffsym = gen_sym2GOTOFFFUNCDESC (operands[1]);
7500 PUT_MODE (gotoffsym, Pmode);
7501 emit_move_insn (t, gotoffsym);
7502 emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, picreg));
7506 (define_expand "symPLT_label2reg"
7507 [(set (match_operand:SI 0 "" "")
7510 [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PLT))
7511 (const:SI (plus:SI (match_operand:SI 2 "" "")
7512 (const_int 2)))] UNSPEC_PCREL_SYMOFF)))
7513 ;; Even though the PIC register is not really used by the call
7514 ;; sequence in which this is expanded, the PLT code assumes the PIC
7515 ;; register is set, so we must not skip its initialization. Since
7516 ;; we only use this expand as part of calling sequences, and never
7517 ;; to take the address of a function, this is the best point to
7518 ;; insert the (use). Using the PLT to take the address of a
7519 ;; function would be wrong, not only because the PLT entry could
7520 ;; then be called from a function that doesn't initialize the PIC
7521 ;; register to the proper GOT, but also because pointers to the
7522 ;; same function might not compare equal, should they be set by
7523 ;; different shared libraries.
7524 (use (reg:SI PIC_REG))]
7528 (define_expand "sym2PIC"
7529 [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_PIC))]
7533 ;; -------------------------------------------------------------------------
7534 ;; TLS code generation.
7536 ;; FIXME: The multi-insn asm blocks should be converted to use
7537 ;; define_insn_and_split.
7538 ;; See the thread [PATCH/RFA] SH TLS support on gcc-patches
7539 ;; <http://gcc.gnu.org/ml/gcc-patches/2003-02/msg01898.html>
7542 (define_insn "tls_global_dynamic"
7543 [(set (match_operand:SI 0 "register_operand" "=&z")
7544 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
7547 (use (reg:SI FPSCR_MODES_REG))
7548 (use (reg:SI PIC_REG))
7549 (clobber (reg:SI PR_REG))
7550 (clobber (scratch:SI))]
7553 return "mov.l 1f,r4" "\n"
7562 "1: .long %a1@TLSGD" "\n"
7563 "2: .long __tls_get_addr@PLT" "\n"
7566 [(set_attr "type" "tls_load")
7567 (set_attr "length" "26")])
7569 (define_insn "tls_local_dynamic"
7570 [(set (match_operand:SI 0 "register_operand" "=&z")
7571 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
7574 (use (reg:SI FPSCR_MODES_REG))
7575 (use (reg:SI PIC_REG))
7576 (clobber (reg:SI PR_REG))
7577 (clobber (scratch:SI))]
7580 return "mov.l 1f,r4" "\n"
7589 "1: .long %a1@TLSLDM" "\n"
7590 "2: .long __tls_get_addr@PLT" "\n"
7593 [(set_attr "type" "tls_load")
7594 (set_attr "length" "26")])
7596 (define_expand "sym2DTPOFF"
7597 [(const (unspec [(match_operand 0 "" "")] UNSPEC_DTPOFF))]
7601 (define_expand "symDTPOFF2reg"
7602 [(match_operand 0 "" "") (match_operand 1 "" "") (match_operand 2 "" "")]
7606 rtx t = (!can_create_pseudo_p ()
7608 : gen_reg_rtx (GET_MODE (operands[0])));
7610 dtpoffsym = gen_sym2DTPOFF (operands[1]);
7611 PUT_MODE (dtpoffsym, Pmode);
7612 emit_move_insn (t, dtpoffsym);
7613 emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, operands[2]));
7617 (define_expand "sym2GOTTPOFF"
7618 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTTPOFF))]
7622 (define_insn "tls_initial_exec"
7623 [(set (match_operand:SI 0 "register_operand" "=&r")
7624 (unspec:SI [(match_operand:SI 1 "" "")]
7626 (use (reg:SI GBR_REG))
7627 (use (reg:SI PIC_REG))
7628 (clobber (reg:SI R0_REG))]
7631 return "mov.l 1f,r0" "\n"
7633 " mov.l @(r0,r12),r0" "\n"
7640 [(set_attr "type" "tls_load")
7641 (set_attr "length" "16")])
7643 (define_expand "sym2TPOFF"
7644 [(const (unspec [(match_operand 0 "" "")] UNSPEC_TPOFF))]
7648 (define_expand "symTPOFF2reg"
7649 [(match_operand 0 "" "") (match_operand 1 "" "")]
7654 tpoffsym = gen_sym2TPOFF (operands[1]);
7655 PUT_MODE (tpoffsym, Pmode);
7656 emit_move_insn (operands[0], tpoffsym);
7660 ;;------------------------------------------------------------------------------
7661 ;; Thread pointer getter and setter.
7663 ;; On SH the thread pointer is kept in the GBR.
7664 ;; These patterns are usually expanded from the respective built-in functions.
7665 (define_expand "get_thread_pointersi"
7666 [(set (match_operand:SI 0 "arith_reg_dest") (reg:SI GBR_REG))]
7669 ;; The store_gbr insn can also be used on !TARGET_SH1 for doing TLS accesses.
7670 (define_insn "store_gbr"
7671 [(set (match_operand:SI 0 "arith_reg_dest" "=r") (reg:SI GBR_REG))]
7674 [(set_attr "type" "tls_load")])
7676 (define_expand "set_thread_pointersi"
7677 [(set (reg:SI GBR_REG)
7678 (unspec_volatile:SI [(match_operand:SI 0 "arith_reg_operand")]
7682 (define_insn "load_gbr"
7683 [(set (reg:SI GBR_REG)
7684 (unspec_volatile:SI [(match_operand:SI 0 "arith_reg_operand" "r")]
7688 [(set_attr "type" "move")])
7690 ;;------------------------------------------------------------------------------
7691 ;; Thread pointer relative memory loads and stores.
7693 ;; On SH there are GBR displacement address modes which can be utilized to
7694 ;; access memory behind the thread pointer.
7695 ;; Since we do not allow using GBR for general purpose memory accesses, these
7696 ;; GBR addressing modes are formed by the combine pass.
7697 ;; This could be done with fewer patterns than below by using a mem predicate
7698 ;; for the GBR mem, but then reload would try to reload addresses with a
7699 ;; zero displacement for some strange reason.
7701 (define_insn "*mov<mode>_gbr_load"
7702 [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z")
7703 (mem:QIHISI (plus:SI (reg:SI GBR_REG)
7704 (match_operand:QIHISI 1 "gbr_displacement"))))]
7706 "mov.<bwl> @(%O1,gbr),%0"
7707 [(set_attr "type" "load")])
7709 (define_insn "*mov<mode>_gbr_load"
7710 [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z")
7711 (mem:QIHISI (reg:SI GBR_REG)))]
7713 "mov.<bwl> @(0,gbr),%0"
7714 [(set_attr "type" "load")])
7716 (define_insn "*mov<mode>_gbr_load"
7717 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
7719 (mem:QIHI (plus:SI (reg:SI GBR_REG)
7720 (match_operand:QIHI 1 "gbr_displacement")))))]
7722 "mov.<bw> @(%O1,gbr),%0"
7723 [(set_attr "type" "load")])
7725 (define_insn "*mov<mode>_gbr_load"
7726 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
7727 (sign_extend:SI (mem:QIHI (reg:SI GBR_REG))))]
7729 "mov.<bw> @(0,gbr),%0"
7730 [(set_attr "type" "load")])
7732 (define_insn "*mov<mode>_gbr_store"
7733 [(set (mem:QIHISI (plus:SI (reg:SI GBR_REG)
7734 (match_operand:QIHISI 0 "gbr_displacement")))
7735 (match_operand:QIHISI 1 "register_operand" "z"))]
7737 "mov.<bwl> %1,@(%O0,gbr)"
7738 [(set_attr "type" "store")])
7740 (define_insn "*mov<mode>_gbr_store"
7741 [(set (mem:QIHISI (reg:SI GBR_REG))
7742 (match_operand:QIHISI 0 "register_operand" "z"))]
7744 "mov.<bwl> %0,@(0,gbr)"
7745 [(set_attr "type" "store")])
7747 ;; DImode memory accesses have to be split in two SImode accesses.
7748 ;; Split them before reload, so that it gets a better chance to figure out
7749 ;; how to deal with the R0 restriction for the individual SImode accesses.
7750 ;; Do not match this insn during or after reload because it can't be split
7752 (define_insn_and_split "*movdi_gbr_load"
7753 [(set (match_operand:DI 0 "arith_reg_dest")
7754 (match_operand:DI 1 "gbr_address_mem"))]
7755 "TARGET_SH1 && can_create_pseudo_p ()"
7758 [(set (match_dup 3) (match_dup 5))
7759 (set (match_dup 4) (match_dup 6))]
7761 /* Swap low/high part load order on little endian, so that the result reg
7762 of the second load can be used better. */
7763 int off = TARGET_LITTLE_ENDIAN ? 1 : 0;
7764 operands[3 + off] = gen_lowpart (SImode, operands[0]);
7765 operands[5 + off] = gen_lowpart (SImode, operands[1]);
7766 operands[4 - off] = gen_highpart (SImode, operands[0]);
7767 operands[6 - off] = gen_highpart (SImode, operands[1]);
7770 (define_insn_and_split "*movdi_gbr_store"
7771 [(set (match_operand:DI 0 "gbr_address_mem")
7772 (match_operand:DI 1 "register_operand"))]
7773 "TARGET_SH1 && can_create_pseudo_p ()"
7776 [(set (match_dup 3) (match_dup 5))
7777 (set (match_dup 4) (match_dup 6))]
7779 /* Swap low/high part store order on big endian, so that stores of function
7780 call results can save a reg copy. */
7781 int off = TARGET_LITTLE_ENDIAN ? 0 : 1;
7782 operands[3 + off] = gen_lowpart (SImode, operands[0]);
7783 operands[5 + off] = gen_lowpart (SImode, operands[1]);
7784 operands[4 - off] = gen_highpart (SImode, operands[0]);
7785 operands[6 - off] = gen_highpart (SImode, operands[1]);
7788 ;; Sometimes memory accesses do not get combined with the store_gbr insn,
7789 ;; in particular when the displacements are in the range of the regular move
7790 ;; insns. Thus, in the first split pass after the combine pass we search
7791 ;; for missed opportunities and try to fix them up ourselves.
7792 ;; If an equivalent GBR address can be determined the load / store is split
7793 ;; into one of the GBR load / store patterns.
7794 ;; All of that must happen before reload (GBR address modes use R0 as the
7795 ;; other operand) and there's no point of doing it if the GBR is not
7796 ;; referenced in a function at all.
7798 [(set (match_operand:QIHISIDI 0 "register_operand")
7799 (match_operand:QIHISIDI 1 "memory_operand"))]
7800 "TARGET_SH1 && !reload_in_progress && !reload_completed
7801 && df_regs_ever_live_p (GBR_REG)"
7802 [(set (match_dup 0) (match_dup 1))]
7804 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
7805 if (gbr_mem != NULL_RTX)
7806 operands[1] = replace_equiv_address (operands[1], gbr_mem);
7812 [(set (match_operand:SI 0 "register_operand")
7813 (sign_extend:SI (match_operand:QIHI 1 "memory_operand")))]
7814 "TARGET_SH1 && !reload_in_progress && !reload_completed
7815 && df_regs_ever_live_p (GBR_REG)"
7816 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
7818 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
7819 if (gbr_mem != NULL_RTX)
7820 operands[1] = replace_equiv_address (operands[1], gbr_mem);
7825 ;; On SH2A we've got movu.b and movu.w for doing zero-extending mem loads.
7826 ;; Split those so that a GBR load can be used.
7828 [(set (match_operand:SI 0 "register_operand")
7829 (zero_extend:SI (match_operand:QIHI 1 "memory_operand")))]
7830 "TARGET_SH2A && !reload_in_progress && !reload_completed
7831 && df_regs_ever_live_p (GBR_REG)"
7832 [(set (match_dup 2) (match_dup 1))
7833 (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
7835 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
7836 if (gbr_mem != NULL_RTX)
7838 operands[2] = gen_reg_rtx (GET_MODE (operands[1]));
7839 operands[1] = replace_equiv_address (operands[1], gbr_mem);
7846 [(set (match_operand:QIHISIDI 0 "memory_operand")
7847 (match_operand:QIHISIDI 1 "register_operand"))]
7848 "TARGET_SH1 && !reload_in_progress && !reload_completed
7849 && df_regs_ever_live_p (GBR_REG)"
7850 [(set (match_dup 0) (match_dup 1))]
7852 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[0]);
7853 if (gbr_mem != NULL_RTX)
7854 operands[0] = replace_equiv_address (operands[0], gbr_mem);
7859 ;;------------------------------------------------------------------------------
7860 ;; case instruction for switch statements.
7862 ;; operand 0 is index
7863 ;; operand 1 is the minimum bound
7864 ;; operand 2 is the maximum bound - minimum bound + 1
7865 ;; operand 3 is CODE_LABEL for the table;
7866 ;; operand 4 is the CODE_LABEL to go to if index out of range.
7867 (define_expand "casesi"
7868 [(match_operand:SI 0 "arith_reg_operand" "")
7869 (match_operand:SI 1 "arith_reg_operand" "")
7870 (match_operand:SI 2 "arith_reg_operand" "")
7871 (match_operand 3 "" "") (match_operand 4 "" "")]
7874 rtx reg = gen_reg_rtx (SImode);
7875 rtx reg2 = gen_reg_rtx (SImode);
7877 operands[1] = copy_to_mode_reg (SImode, operands[1]);
7878 operands[2] = copy_to_mode_reg (SImode, operands[2]);
7879 /* If optimizing, casesi_worker depends on the mode of the instruction
7880 before label it 'uses' - operands[3]. */
7881 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
7883 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
7885 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
7887 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
7888 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
7889 operands[3], but to lab. We will fix this up in
7890 machine_dependent_reorg. */
7895 (define_expand "casesi_0"
7896 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
7897 (set (match_dup 4) (minus:SI (match_dup 4)
7898 (match_operand:SI 1 "arith_operand" "")))
7900 (gtu:SI (match_dup 4)
7901 (match_operand:SI 2 "arith_reg_operand" "")))
7903 (if_then_else (ne (reg:SI T_REG)
7905 (label_ref (match_operand 3 "" ""))
7910 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
7911 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
7912 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
7914 ;; The use on the T_REG in the casesi_worker* patterns links the bounds
7915 ;; checking insns and the table memory access. See also PR 69713.
7916 (define_insn "casesi_worker_0"
7917 [(set (match_operand:SI 0 "register_operand" "=r,r")
7918 (unspec:SI [(match_operand:SI 1 "register_operand" "0,r")
7919 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7920 (clobber (match_scratch:SI 3 "=X,1"))
7921 (clobber (match_scratch:SI 4 "=&z,z"))
7922 (use (reg:SI T_REG))]
7927 [(set (match_operand:SI 0 "register_operand" "")
7928 (unspec:SI [(match_operand:SI 1 "register_operand" "")
7929 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7930 (clobber (match_scratch:SI 3 ""))
7931 (clobber (match_scratch:SI 4))
7932 (use (reg:SI T_REG))]
7933 "TARGET_SH1 && ! TARGET_SH2 && reload_completed"
7934 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
7935 (parallel [(set (match_dup 0)
7936 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
7937 (label_ref (match_dup 2))] UNSPEC_CASESI))
7938 (clobber (match_dup 3))])
7939 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
7941 if (GET_CODE (operands[2]) == CODE_LABEL)
7942 LABEL_NUSES (operands[2])++;
7946 [(set (match_operand:SI 0 "register_operand" "")
7947 (unspec:SI [(match_operand:SI 1 "register_operand" "")
7948 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7949 (clobber (match_scratch:SI 3 ""))
7950 (clobber (match_scratch:SI 4))
7951 (use (reg:SI T_REG))]
7952 "TARGET_SH2 && reload_completed"
7953 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
7954 (parallel [(set (match_dup 0)
7955 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
7956 (label_ref (match_dup 2))] UNSPEC_CASESI))
7957 (clobber (match_dup 3))])]
7959 if (GET_CODE (operands[2]) == CODE_LABEL)
7960 LABEL_NUSES (operands[2])++;
7963 ;; This may be replaced with casesi_worker_2 in sh_reorg for PIC.
7964 ;; The insn length is set to 8 for that case.
7965 (define_insn "casesi_worker_1"
7966 [(set (match_operand:SI 0 "register_operand" "=r,r")
7967 (unspec:SI [(reg:SI R0_REG)
7968 (match_operand:SI 1 "register_operand" "0,r")
7969 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7970 (clobber (match_scratch:SI 3 "=X,1"))]
7973 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2])));
7975 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
7977 switch (GET_MODE (diff_vec))
7980 return "shll2 %1" "\n"
7981 " mov.l @(r0,%1),%0";
7983 return "add %1,%1" "\n"
7984 " mov.w @(r0,%1),%0";
7986 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
7987 return "mov.b @(r0,%1),%0" "\n"
7990 return "mov.b @(r0,%1),%0";
7996 [(set_attr_alternative "length"
7997 [(if_then_else (match_test "flag_pic") (const_int 8) (const_int 4))
7998 (if_then_else (match_test "flag_pic") (const_int 8) (const_int 4))])])
8000 (define_insn "casesi_worker_2"
8001 [(set (match_operand:SI 0 "register_operand" "=r,r")
8002 (unspec:SI [(reg:SI R0_REG)
8003 (match_operand:SI 1 "register_operand" "0,r")
8004 (label_ref (match_operand 2 "" ""))
8005 (label_ref (match_operand 3 "" ""))] UNSPEC_CASESI))
8006 (clobber (match_operand:SI 4 "" "=X,1"))]
8007 "TARGET_SH2 && reload_completed && flag_pic"
8009 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2])));
8010 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
8012 switch (GET_MODE (diff_vec))
8015 return "shll2 %1" "\n"
8018 " mov.l @(r0,%1),%0";
8020 return "add %1,%1" "\n"
8023 " mov.w @(r0,%1),%0";
8025 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
8026 return "add r0,%1" "\n"
8028 " mov.b @(r0,%1),%0" "\n"
8031 return "add r0,%1" "\n"
8033 " mov.b @(r0,%1),%0";
8038 [(set_attr "length" "8")])
8040 (define_expand "simple_return"
8042 "sh_can_use_simple_return_p ()")
8044 (define_expand "return"
8046 "reload_completed && epilogue_completed")
8048 (define_insn "*<code>_i"
8052 && ! sh_cfun_trap_exit_p ()"
8054 if (TARGET_SH2A && (dbr_sequence_length () == 0)
8055 && !current_function_interrupt)
8060 [(set_attr "type" "return")
8061 (set_attr "needs_delay_slot" "yes")])
8063 ;; trapa has no delay slot.
8064 (define_insn "*return_trapa"
8066 "TARGET_SH1 && reload_completed"
8068 [(set_attr "type" "return")])
8070 (define_expand "prologue"
8074 sh_expand_prologue ();
8078 (define_expand "epilogue"
8082 sh_expand_epilogue (false);
8085 (define_expand "eh_return"
8086 [(use (match_operand 0 "register_operand" ""))]
8089 emit_insn (gen_eh_set_ra_si (operands[0]));
8093 ;; Clobber the return address on the stack. We can't expand this
8094 ;; until we know where it will be put in the stack frame.
8096 (define_insn "eh_set_ra_si"
8097 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
8099 (clobber (match_scratch:SI 1 "=&r"))]
8104 [(unspec_volatile [(match_operand 0 "register_operand" "")]
8106 (clobber (match_scratch 1 ""))]
8110 sh_set_return_address (operands[0], operands[1]);
8114 (define_insn "blockage"
8115 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8118 [(set_attr "length" "0")])
8120 ;; Define movml instructions for SH2A target. Currently they are
8121 ;; used to push and pop all banked registers only.
8123 (define_insn "movml_push_banked"
8124 [(set (match_operand:SI 0 "register_operand" "=r")
8125 (plus (match_dup 0) (const_int -32)))
8126 (set (mem:SI (plus:SI (match_dup 0) (const_int 28))) (reg:SI R7_REG))
8127 (set (mem:SI (plus:SI (match_dup 0) (const_int 24))) (reg:SI R6_REG))
8128 (set (mem:SI (plus:SI (match_dup 0) (const_int 20))) (reg:SI R5_REG))
8129 (set (mem:SI (plus:SI (match_dup 0) (const_int 16))) (reg:SI R4_REG))
8130 (set (mem:SI (plus:SI (match_dup 0) (const_int 12))) (reg:SI R3_REG))
8131 (set (mem:SI (plus:SI (match_dup 0) (const_int 8))) (reg:SI R2_REG))
8132 (set (mem:SI (plus:SI (match_dup 0) (const_int 4))) (reg:SI R1_REG))
8133 (set (mem:SI (plus:SI (match_dup 0) (const_int 0))) (reg:SI R0_REG))]
8134 "TARGET_SH2A && REGNO (operands[0]) == 15"
8136 [(set_attr "in_delay_slot" "no")])
8138 (define_insn "movml_pop_banked"
8139 [(set (match_operand:SI 0 "register_operand" "=r")
8140 (plus (match_dup 0) (const_int 32)))
8141 (set (reg:SI R0_REG) (mem:SI (plus:SI (match_dup 0) (const_int -32))))
8142 (set (reg:SI R1_REG) (mem:SI (plus:SI (match_dup 0) (const_int -28))))
8143 (set (reg:SI R2_REG) (mem:SI (plus:SI (match_dup 0) (const_int -24))))
8144 (set (reg:SI R3_REG) (mem:SI (plus:SI (match_dup 0) (const_int -20))))
8145 (set (reg:SI R4_REG) (mem:SI (plus:SI (match_dup 0) (const_int -16))))
8146 (set (reg:SI R5_REG) (mem:SI (plus:SI (match_dup 0) (const_int -12))))
8147 (set (reg:SI R6_REG) (mem:SI (plus:SI (match_dup 0) (const_int -8))))
8148 (set (reg:SI R7_REG) (mem:SI (plus:SI (match_dup 0) (const_int -4))))]
8149 "TARGET_SH2A && REGNO (operands[0]) == 15"
8151 [(set_attr "in_delay_slot" "no")])
8153 ;; ------------------------------------------------------------------------
8155 ;; ------------------------------------------------------------------------
8158 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8159 (match_operand:SI 1 "t_reg_operand"))]
8162 [(set_attr "type" "arith")])
8164 (define_insn "movrt"
8165 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8166 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
8169 [(set_attr "type" "arith")])
8171 (define_expand "cstoresi4"
8172 [(set (match_operand:SI 0 "register_operand")
8173 (match_operator:SI 1 "comparison_operator"
8174 [(match_operand:SI 2 "cmpsi_operand")
8175 (match_operand:SI 3 "arith_operand")]))]
8178 if (sh_expand_t_scc (operands))
8181 if (! currently_expanding_to_rtl)
8184 sh_emit_compare_and_set (operands, SImode);
8188 (define_expand "cstoredi4"
8189 [(set (match_operand:SI 0 "register_operand")
8190 (match_operator:SI 1 "comparison_operator"
8191 [(match_operand:DI 2 "arith_operand")
8192 (match_operand:DI 3 "arith_operand")]))]
8195 if (sh_expand_t_scc (operands))
8198 if (! currently_expanding_to_rtl)
8201 sh_emit_compare_and_set (operands, DImode);
8205 ;; Move the complement of the T reg to a reg.
8206 ;; On SH2A the movrt insn can be used.
8207 ;; On anything else than SH2A this has to be done with multiple instructions.
8208 ;; One obvious way would be:
8213 ;; However, this puts pressure on r0 in most cases and thus the following is
8219 ;; If the constant -1 can be CSE-ed or lifted out of a loop it effectively
8220 ;; becomes a one instruction operation. Moreover, care must be taken that
8221 ;; the insn can still be combined with inverted compare and branch code
8222 ;; around it. On the other hand, if a function returns the complement of
8223 ;; a previous comparison result in the T bit, the xor #1,r0 approach might
8224 ;; lead to better code.
8225 (define_expand "movnegt"
8226 [(set (match_operand:SI 0 "arith_reg_dest" "")
8227 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
8231 emit_insn (gen_movrt (operands[0], operands[1]));
8234 rtx val = force_reg (SImode, gen_int_mode (-1, SImode));
8235 emit_insn (gen_movrt_negc (operands[0], operands[1], val));
8240 (define_insn_and_split "movrt_negc"
8241 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8242 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
8243 (set (reg:SI T_REG) (const_int 1))
8244 (use (match_operand:SI 2 "arith_reg_operand" "r"))]
8247 "&& !sh_in_recog_treg_set_expr ()"
8250 if (sh_split_movrt_negc_to_movt_xor (curr_insn, operands))
8255 [(set_attr "type" "arith")])
8257 ;; The -1 constant will not be CSE-ed for the *movrt_negc pattern, but the
8258 ;; pattern can be used by the combine pass. Using a scratch reg for the
8259 ;; -1 constant results in slightly better register allocations compared to
8260 ;; generating a pseudo reg before reload.
8261 (define_insn_and_split "*movrt_negc"
8262 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8263 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
8264 (clobber (match_scratch:SI 2 "=r"))
8265 (clobber (reg:SI T_REG))]
8266 "TARGET_SH1 && ! TARGET_SH2A"
8268 "&& !sh_in_recog_treg_set_expr ()"
8271 if (sh_split_movrt_negc_to_movt_xor (curr_insn, operands))
8273 else if (reload_completed)
8275 emit_move_insn (operands[2], gen_int_mode (-1, SImode));
8276 emit_insn (gen_movrt_negc (operands[0], operands[1], operands[2]));
8283 ;; Store the negated T bit in a reg using r0 and xor. This one doesn't
8284 ;; clobber the T bit, which is useful when storing the T bit and the
8285 ;; negated T bit in parallel. On SH2A the movrt insn can be used for that.
8286 ;; Usually we don't want this insn to be matched, except for cases where the
8287 ;; T bit clobber is really not appreciated. Hence the extra use on T_REG.
8288 (define_insn_and_split "movrt_xor"
8289 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
8290 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
8291 (use (reg:SI T_REG))]
8294 "&& reload_completed"
8295 [(set (match_dup 0) (reg:SI T_REG))
8296 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))])
8299 ;; 0x7fffffff + (1-T) = 0 - 0x80000000 - T
8301 ;; Notice that 0 - 0x80000000 = 0x80000000.
8303 ;; Single bit tests are usually done with zero_extract. On non-SH2A this
8304 ;; will use a tst-negc sequence. On SH2A it will use a bld-addc sequence.
8305 ;; The zeroth bit requires a special pattern, otherwise we get a shlr-addc.
8306 ;; This is a special case of the generic treg_set_expr pattern and thus has
8307 ;; to come first or it will never match.
8308 (define_insn_and_split "*mov_t_msb_neg"
8309 [(set (match_operand:SI 0 "arith_reg_dest")
8310 (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
8312 (const_int 2147483647)))
8313 (clobber (reg:SI T_REG))]
8316 "&& can_create_pseudo_p ()"
8317 [(parallel [(set (match_dup 0)
8318 (plus:SI (zero_extract:SI (match_dup 1)
8319 (const_int 1) (const_int 0))
8320 (const_int 2147483647)))
8321 (clobber (reg:SI T_REG))])])
8323 (define_insn_and_split "*mov_t_msb_neg"
8324 [(set (match_operand:SI 0 "arith_reg_dest")
8325 (plus:SI (match_operand 1 "treg_set_expr")
8326 (const_int 2147483647))) ;; 0x7fffffff
8327 (clobber (reg:SI T_REG))]
8330 "&& can_create_pseudo_p ()"
8333 if (negt_reg_operand (operands[1], VOIDmode))
8335 emit_insn (gen_negc (operands[0],
8336 force_reg (SImode, GEN_INT (-2147483648LL))));
8340 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8341 if (ti.remove_trailing_nott ())
8342 emit_insn (gen_negc (operands[0],
8343 force_reg (SImode, GEN_INT (-2147483648LL))));
8345 emit_insn (gen_addc (operands[0],
8346 force_reg (SImode, const0_rtx),
8347 force_reg (SImode, GEN_INT (2147483647))));
8351 (define_insn_and_split "*mov_t_msb_neg"
8352 [(set (match_operand:SI 0 "arith_reg_dest")
8353 (if_then_else:SI (match_operand 1 "treg_set_expr")
8354 (match_operand 2 "const_int_operand")
8355 (match_operand 3 "const_int_operand")))
8356 (clobber (reg:SI T_REG))]
8357 "TARGET_SH1 && can_create_pseudo_p ()
8358 && ((INTVAL (operands[2]) == -2147483648LL
8359 && INTVAL (operands[3]) == 2147483647LL)
8360 || (INTVAL (operands[2]) == 2147483647LL
8361 && INTVAL (operands[3]) == -2147483648LL))"
8366 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8368 if (INTVAL (operands[2]) == -2147483648LL)
8370 if (ti.remove_trailing_nott ())
8371 emit_insn (gen_negc (operands[0],
8372 force_reg (SImode, GEN_INT (-2147483648LL))));
8374 emit_insn (gen_addc (operands[0],
8375 force_reg (SImode, const0_rtx),
8376 force_reg (SImode, operands[3])));
8379 else if (INTVAL (operands[2]) == 2147483647LL)
8381 if (ti.remove_trailing_nott ())
8382 emit_insn (gen_addc (operands[0],
8383 force_reg (SImode, const0_rtx),
8384 force_reg (SImode, GEN_INT (2147483647LL))));
8386 emit_insn (gen_negc (operands[0],
8387 force_reg (SImode, GEN_INT (-2147483648LL))));
8394 ;; Store (negated) T bit as all zeros or ones in a reg.
8395 ;; subc Rn,Rn ! Rn = Rn - Rn - T; T = T
8396 ;; not Rn,Rn ! Rn = 0 - Rn
8397 (define_insn_and_split "mov_neg_si_t"
8398 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8399 (neg:SI (match_operand 1 "treg_set_expr")))]
8402 gcc_assert (t_reg_operand (operands[1], VOIDmode));
8403 return "subc %0,%0";
8405 "&& can_create_pseudo_p () && !t_reg_operand (operands[1], VOIDmode)"
8408 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8409 emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ()));
8411 if (ti.remove_trailing_nott ())
8412 emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
8416 [(set_attr "type" "arith")])
8418 ;; Invert the T bit.
8419 ;; On SH2A we can use the nott insn. On anything else this must be done with
8420 ;; multiple insns like:
8423 ;; This requires an additional pseudo. The SH specific sh_treg_combine RTL
8424 ;; pass will look for this insn. Disallow using it if pseudos can't be
8426 ;; Don't split the nott inside the splitting of a treg_set_expr, or else
8427 ;; surrounding insns might not see and recombine it. Defer the splitting
8428 ;; of the nott until after the whole insn containing the treg_set_expr
8430 (define_insn_and_split "nott"
8431 [(set (reg:SI T_REG)
8432 (xor:SI (match_operand:SI 0 "t_reg_operand") (const_int 1)))]
8433 "TARGET_SH2A || (TARGET_SH1 && can_create_pseudo_p ())"
8435 gcc_assert (TARGET_SH2A);
8438 "!TARGET_SH2A && can_create_pseudo_p () && !sh_in_recog_treg_set_expr ()"
8439 [(set (match_dup 0) (reg:SI T_REG))
8440 (set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))]
8442 operands[0] = gen_reg_rtx (SImode);
8445 ;; Store T bit as MSB in a reg.
8446 ;; T = 0: 0x00000000 -> reg
8447 ;; T = 1: 0x80000000 -> reg
8448 (define_insn_and_split "*movt_msb"
8449 [(set (match_operand:SI 0 "arith_reg_dest")
8450 (mult:SI (match_operand:SI 1 "t_reg_operand")
8451 (const_int -2147483648))) ;; 0xffffffff80000000
8452 (clobber (reg:SI T_REG))]
8456 [(set (match_dup 0) (ashift:SI (reg:SI T_REG) (const_int 31)))])
8458 ;; Store inverted T bit as MSB in a reg.
8459 ;; T = 0: 0x80000000 -> reg
8460 ;; T = 1: 0x00000000 -> reg
8461 ;; On SH2A we can get away without clobbering the T_REG using the movrt insn.
8462 ;; On non SH2A we resort to the following sequence:
8466 ;; The T bit value will be modified during the sequence, but the rotcr insn
8467 ;; will restore its original value.
8468 (define_insn_and_split "*negt_msb"
8469 [(set (match_operand:SI 0 "arith_reg_dest")
8470 (match_operand:SI 1 "negt_reg_shl31_operand"))]
8473 "&& can_create_pseudo_p ()"
8476 rtx tmp = gen_reg_rtx (SImode);
8480 emit_insn (gen_movrt (tmp, get_t_reg_rtx ()));
8481 emit_insn (gen_rotrsi3 (operands[0], tmp, const1_rtx));
8485 emit_move_insn (tmp, get_t_reg_rtx ());
8486 emit_insn (gen_cmpeqsi_t (tmp, const0_rtx));
8487 emit_insn (gen_rotcr (operands[0], tmp, get_t_reg_rtx ()));
8492 ;; The *cset_zero patterns convert optimizations such as
8493 ;; "if (test) x = 0;"
8495 ;; "x &= -(test == 0);"
8496 ;; back to conditional branch sequences if zero-displacement branches
8498 ;; FIXME: These patterns can be removed when conditional execution patterns
8499 ;; are implemented, since ifcvt will not perform these optimizations if
8500 ;; conditional execution is supported.
8501 (define_insn "*cset_zero"
8502 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8503 (and:SI (plus:SI (match_operand:SI 1 "t_reg_operand")
8505 (match_operand:SI 2 "arith_reg_operand" "0")))]
8506 "TARGET_SH1 && TARGET_ZDCBRANCH"
8512 [(set_attr "type" "arith") ;; poor approximation
8513 (set_attr "length" "4")])
8515 (define_insn "*cset_zero"
8516 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8517 (if_then_else:SI (match_operand:SI 1 "cbranch_treg_value")
8518 (match_operand:SI 2 "arith_reg_operand" "0")
8520 "TARGET_SH1 && TARGET_ZDCBRANCH"
8522 int tval = sh_eval_treg_value (operands[1]);
8527 else if (tval == false)
8534 [(set_attr "type" "arith") ;; poor approximation
8535 (set_attr "length" "4")])
8537 (define_insn_and_split "*cset_zero"
8538 [(set (match_operand:SI 0 "arith_reg_dest")
8539 (if_then_else:SI (match_operand 1 "treg_set_expr_not_const01")
8540 (match_dup 0) (const_int 0)))
8541 (clobber (reg:SI T_REG))]
8542 "TARGET_SH1 && TARGET_ZDCBRANCH && can_create_pseudo_p ()"
8546 (if_then_else:SI (match_dup 1) (match_dup 0) (const_int 0)))]
8548 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8549 if (ti.remove_trailing_nott ())
8550 operands[1] = gen_rtx_EQ (SImode, get_t_reg_rtx (), const0_rtx);
8552 operands[1] = gen_rtx_EQ (SImode, get_t_reg_rtx (), const1_rtx);
8555 (define_expand "cstoresf4"
8556 [(set (match_operand:SI 0 "register_operand")
8557 (match_operator:SI 1 "ordered_comparison_operator"
8558 [(match_operand:SF 2 "arith_operand")
8559 (match_operand:SF 3 "arith_operand")]))]
8562 if (! currently_expanding_to_rtl)
8565 sh_emit_compare_and_set (operands, SFmode);
8569 (define_expand "cstoredf4"
8570 [(set (match_operand:SI 0 "register_operand")
8571 (match_operator:SI 1 "ordered_comparison_operator"
8572 [(match_operand:DF 2 "arith_operand")
8573 (match_operand:DF 3 "arith_operand")]))]
8576 if (! currently_expanding_to_rtl)
8579 sh_emit_compare_and_set (operands, DFmode);
8583 ;; Sometimes the T bit result of insns is needed in normal registers.
8584 ;; Instead of open coding all the pattern variations, use the treg_set_expr
8585 ;; predicate to match any T bit output insn and split it out after.
8586 ;; This pattern should be below all other related patterns so that it is
8587 ;; considered as a last resort option during matching. This allows
8588 ;; overriding it with special case patterns.
8589 (define_insn_and_split "any_treg_expr_to_reg"
8590 [(set (match_operand:SI 0 "arith_reg_dest")
8591 (match_operand 1 "treg_set_expr"))
8592 (clobber (reg:SI T_REG))]
8593 "TARGET_SH1 && can_create_pseudo_p ()"
8595 "&& !sh_in_recog_treg_set_expr ()"
8599 fprintf (dump_file, "splitting any_treg_expr_to_reg\n");
8601 if (t_reg_operand (operands[1], VOIDmode))
8604 fprintf (dump_file, "t_reg_operand: emitting movt\n");
8605 emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
8608 if (negt_reg_operand (operands[1], VOIDmode))
8611 fprintf (dump_file, "negt_reg_operand: emitting movrt\n");
8612 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
8616 /* If the split out insns ended with a nott, emit a movrt sequence,
8617 otherwise a normal movt. */
8618 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8620 if (ti.remove_trailing_nott ())
8622 /* Emit this same insn_and_split again. However, the next time it
8623 is split, it will emit the actual negc/movrt insn. This gives
8624 other surrounding insns the chance to see the trailing movrt. */
8627 "any_treg_expr_to_reg: replacing trailing nott with movrt\n");
8628 i = emit_insn (gen_any_treg_expr_to_reg (
8629 operands[0], gen_rtx_XOR (SImode, get_t_reg_rtx (),
8634 i = emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
8636 fprintf (dump_file, "any_treg_expr_to_reg: appending movt\n");
8639 add_reg_note (i, REG_UNUSED, get_t_reg_rtx ());
8643 ;; -------------------------------------------------------------------------
8644 ;; Instructions to cope with inline literal tables
8645 ;; -------------------------------------------------------------------------
8647 ;; 2 byte integer in line
8648 (define_insn "consttable_2"
8649 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
8650 (match_operand 1 "" "")]
8654 if (operands[1] != const0_rtx)
8655 assemble_integer (operands[0], 2, BITS_PER_UNIT * 2, 1);
8658 [(set_attr "length" "2")
8659 (set_attr "in_delay_slot" "no")])
8661 ;; 4 byte integer in line
8662 (define_insn "consttable_4"
8663 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
8664 (match_operand 1 "" "")]
8668 if (operands[1] != const0_rtx)
8670 assemble_integer (operands[0], 4, BITS_PER_UNIT * 4, 1);
8671 mark_symbol_refs_as_used (operands[0]);
8675 [(set_attr "length" "4")
8676 (set_attr "in_delay_slot" "no")])
8678 ;; 8 byte integer in line
8679 (define_insn "consttable_8"
8680 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
8681 (match_operand 1 "" "")]
8685 if (operands[1] != const0_rtx)
8686 assemble_integer (operands[0], 8, BITS_PER_UNIT * 8, 1);
8689 [(set_attr "length" "8")
8690 (set_attr "in_delay_slot" "no")])
8692 ;; 4 byte floating point
8693 (define_insn "consttable_sf"
8694 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")
8695 (match_operand 1 "" "")]
8699 if (operands[1] != const0_rtx)
8700 assemble_real (*CONST_DOUBLE_REAL_VALUE (operands[0]),
8701 SFmode, GET_MODE_ALIGNMENT (SFmode));
8704 [(set_attr "length" "4")
8705 (set_attr "in_delay_slot" "no")])
8707 ;; 8 byte floating point
8708 (define_insn "consttable_df"
8709 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")
8710 (match_operand 1 "" "")]
8714 if (operands[1] != const0_rtx)
8715 assemble_real (*CONST_DOUBLE_REAL_VALUE (operands[0]),
8716 DFmode, GET_MODE_ALIGNMENT (DFmode));
8719 [(set_attr "length" "8")
8720 (set_attr "in_delay_slot" "no")])
8722 ;; Alignment is needed for some constant tables; it may also be added for
8723 ;; Instructions at the start of loops, or after unconditional branches.
8724 ;; ??? We would get more accurate lengths if we did instruction
8725 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
8726 ;; here is too conservative.
8728 ;; align to a two byte boundary
8729 (define_expand "align_2"
8730 [(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)]
8734 ;; Align to a four byte boundary.
8735 ;; align_4 and align_log are instructions for the starts of loops, or
8736 ;; after unconditional branches, which may take up extra room.
8737 (define_expand "align_4"
8738 [(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)]
8742 ;; Align to a cache line boundary.
8743 (define_insn "align_log"
8744 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)]
8747 [(set_attr "length" "0")
8748 (set_attr "in_delay_slot" "no")])
8750 ;; Emitted at the end of the literal table, used to emit the
8751 ;; 32bit branch labels if needed.
8752 (define_insn "consttable_end"
8753 [(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)]
8756 return output_jump_label_table ();
8758 [(set_attr "in_delay_slot" "no")])
8760 ;; Emitted at the end of the window in the literal table.
8761 (define_insn "consttable_window_end"
8762 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_WINDOW_END)]
8765 [(set_attr "length" "0")
8766 (set_attr "in_delay_slot" "no")])
8768 ;; -------------------------------------------------------------------------
8769 ;; Minimum / maximum operations.
8770 ;; -------------------------------------------------------------------------
8772 ;; The SH2A clips.b and clips.w insns do a signed min-max function. If smin
8773 ;; and smax standard name patterns are defined, they will be used during
8774 ;; initial expansion and combine will then be able to form the actual min-max
8776 ;; The clips.b and clips.w set the SR.CS bit if the value in the register is
8777 ;; clipped, but there is currently no way of making use of this information.
8778 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
8779 (define_expand "<code>si3"
8780 [(parallel [(set (match_operand:SI 0 "arith_reg_dest")
8781 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
8782 (match_operand 2 "const_int_operand")))
8783 (clobber (reg:SI T_REG))])]
8786 /* Force the comparison value into a register, because greater-than
8787 comparisons can work only on registers. Combine will be able to pick up
8788 the constant value from the REG_EQUAL note when trying to form a min-max
8790 operands[2] = force_reg (SImode, operands[2]);
8794 ;; smax (smin (...))
8796 ;; smin (smax (...))
8797 (define_insn_and_split "*clips"
8798 [(set (match_operand:SI 0 "arith_reg_dest")
8799 (smax:SI (smin:SI (match_operand:SI 1 "arith_reg_operand")
8800 (match_operand 2 "clips_max_const_int"))
8801 (match_operand 3 "clips_min_const_int")))]
8806 (smin:SI (smax:SI (match_dup 1) (match_dup 3)) (match_dup 2)))])
8808 (define_insn "*clips"
8809 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8810 (smin:SI (smax:SI (match_operand:SI 1 "arith_reg_operand" "0")
8811 (match_operand 2 "clips_min_const_int"))
8812 (match_operand 3 "clips_max_const_int")))]
8815 if (INTVAL (operands[3]) == 127)
8816 return "clips.b %0";
8817 else if (INTVAL (operands[3]) == 32767)
8818 return "clips.w %0";
8822 [(set_attr "type" "arith")])
8824 ;; If the expanded smin or smax patterns were not combined, split them into
8825 ;; a compare and branch sequence, because there are no real smin or smax
8827 (define_insn_and_split "*<code>si3"
8828 [(set (match_operand:SI 0 "arith_reg_dest")
8829 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
8830 (match_operand:SI 2 "arith_reg_or_0_or_1_operand")))
8831 (clobber (reg:SI T_REG))]
8832 "TARGET_SH2A && can_create_pseudo_p ()"
8837 rtx_code_label *skip_label = gen_label_rtx ();
8838 emit_move_insn (operands[0], operands[1]);
8840 rtx cmp_val = operands[2];
8841 if (satisfies_constraint_M (cmp_val))
8842 cmp_val = const0_rtx;
8844 emit_insn (gen_cmpgtsi_t (operands[0], cmp_val));
8845 emit_jump_insn (<CODE> == SMIN
8846 ? gen_branch_false (skip_label)
8847 : gen_branch_true (skip_label));
8849 emit_label_after (skip_label, emit_move_insn (operands[0], operands[2]));
8853 ;; The SH2A clipu.b and clipu.w insns can be used to implement a min function
8854 ;; with a register and a constant.
8855 ;; The clipu.b and clipu.w set the SR.CS bit if the value in the register is
8856 ;; clipped, but there is currently no way of making use of this information.
8857 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
8858 (define_expand "uminsi3"
8859 [(set (match_operand:SI 0 "arith_reg_dest")
8860 (umin:SI (match_operand:SI 1 "arith_reg_operand")
8861 (match_operand 2 "const_int_operand")))]
8864 if (INTVAL (operands[2]) == 1)
8866 emit_insn (gen_clipu_one (operands[0], operands[1]));
8869 else if (! clipu_max_const_int (operands[2], VOIDmode))
8873 (define_insn "*clipu"
8874 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8875 (umin:SI (match_operand:SI 1 "arith_reg_operand" "0")
8876 (match_operand 2 "clipu_max_const_int")))]
8879 if (INTVAL (operands[2]) == 255)
8880 return "clipu.b %0";
8881 else if (INTVAL (operands[2]) == 65535)
8882 return "clipu.w %0";
8886 [(set_attr "type" "arith")])
8888 (define_insn_and_split "clipu_one"
8889 [(set (match_operand:SI 0 "arith_reg_dest")
8890 (umin:SI (match_operand:SI 1 "arith_reg_operand") (const_int 1)))
8891 (clobber (reg:SI T_REG))]
8894 "&& can_create_pseudo_p ()"
8897 emit_insn (gen_cmpeqsi_t (operands[1], const0_rtx));
8898 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
8902 ;; -------------------------------------------------------------------------
8904 ;; -------------------------------------------------------------------------
8906 ;; String/block move insn.
8908 (define_expand "movmemsi"
8909 [(parallel [(set (mem:BLK (match_operand:BLK 0))
8910 (mem:BLK (match_operand:BLK 1)))
8911 (use (match_operand:SI 2 "nonmemory_operand"))
8912 (use (match_operand:SI 3 "immediate_operand"))
8913 (clobber (reg:SI PR_REG))
8914 (clobber (reg:SI R4_REG))
8915 (clobber (reg:SI R5_REG))
8916 (clobber (reg:SI R0_REG))])]
8919 if (expand_block_move (operands))
8925 (define_insn "block_move_real"
8926 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8927 (mem:BLK (reg:SI R5_REG)))
8928 (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
8929 (use (match_operand 1 "" "Z,Ccl"))
8930 (clobber (reg:SI PR_REG))
8931 (clobber (reg:SI R0_REG))])]
8932 "TARGET_SH1 && ! TARGET_HARD_SH4"
8936 [(set_attr "type" "sfunc")
8937 (set_attr "needs_delay_slot" "yes")])
8939 (define_insn "block_lump_real"
8940 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8941 (mem:BLK (reg:SI R5_REG)))
8942 (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
8943 (use (match_operand 1 "" "Z,Ccl"))
8944 (use (reg:SI R6_REG))
8945 (clobber (reg:SI PR_REG))
8946 (clobber (reg:SI T_REG))
8947 (clobber (reg:SI R4_REG))
8948 (clobber (reg:SI R5_REG))
8949 (clobber (reg:SI R6_REG))
8950 (clobber (reg:SI R0_REG))])]
8951 "TARGET_SH1 && ! TARGET_HARD_SH4"
8955 [(set_attr "type" "sfunc")
8956 (set_attr "needs_delay_slot" "yes")])
8958 (define_insn "block_move_real_i4"
8959 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8960 (mem:BLK (reg:SI R5_REG)))
8961 (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
8962 (use (match_operand 1 "" "Z,Ccl"))
8963 (clobber (reg:SI PR_REG))
8964 (clobber (reg:SI R0_REG))
8965 (clobber (reg:SI R1_REG))
8966 (clobber (reg:SI R2_REG))])]
8971 [(set_attr "type" "sfunc")
8972 (set_attr "needs_delay_slot" "yes")])
8974 (define_insn "block_lump_real_i4"
8975 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8976 (mem:BLK (reg:SI R5_REG)))
8977 (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
8978 (use (match_operand 1 "" "Z,Ccl"))
8979 (use (reg:SI R6_REG))
8980 (clobber (reg:SI PR_REG))
8981 (clobber (reg:SI T_REG))
8982 (clobber (reg:SI R4_REG))
8983 (clobber (reg:SI R5_REG))
8984 (clobber (reg:SI R6_REG))
8985 (clobber (reg:SI R0_REG))
8986 (clobber (reg:SI R1_REG))
8987 (clobber (reg:SI R2_REG))
8988 (clobber (reg:SI R3_REG))])]
8993 [(set_attr "type" "sfunc")
8994 (set_attr "needs_delay_slot" "yes")])
8996 ;; byte compare pattern
8998 ;; !((temp & 0xF000) && (temp & 0x0F00) && (temp & 0x00F0) && (temp & 0x000F))
8999 (define_insn "cmpstr_t"
9000 [(set (reg:SI T_REG)
9005 (xor:SI (match_operand:SI 0 "arith_reg_operand" "r")
9006 (match_operand:SI 1 "arith_reg_operand" "r"))
9007 (const_int 8) (const_int 0))
9008 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
9009 (const_int 8) (const_int 8)))
9010 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
9011 (const_int 8) (const_int 16)))
9012 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
9013 (const_int 8) (const_int 24)))
9017 [(set_attr "type" "mt_group")])
9019 (define_expand "cmpstrsi"
9020 [(set (match_operand:SI 0 "register_operand")
9021 (compare:SI (match_operand:BLK 1 "memory_operand")
9022 (match_operand:BLK 2 "memory_operand")))
9023 (use (match_operand 3 "immediate_operand"))]
9024 "TARGET_SH1 && optimize"
9026 if (! optimize_insn_for_size_p () && sh_expand_cmpstr (operands))
9032 (define_expand "cmpstrnsi"
9033 [(set (match_operand:SI 0 "register_operand")
9034 (compare:SI (match_operand:BLK 1 "memory_operand")
9035 (match_operand:BLK 2 "memory_operand")))
9036 (use (match_operand:SI 3 "nonmemory_operand"))
9037 (use (match_operand:SI 4 "immediate_operand"))]
9038 "TARGET_SH1 && optimize"
9040 if (! optimize_insn_for_size_p () && sh_expand_cmpnstr (operands))
9046 (define_expand "strlensi"
9047 [(set (match_operand:SI 0 "register_operand")
9048 (unspec:SI [(match_operand:BLK 1 "memory_operand")
9049 (match_operand:SI 2 "immediate_operand")
9050 (match_operand:SI 3 "immediate_operand")]
9051 UNSPEC_BUILTIN_STRLEN))]
9052 "TARGET_SH1 && optimize"
9054 if (! optimize_insn_for_size_p () && sh_expand_strlen (operands))
9060 (define_expand "setmemqi"
9061 [(parallel [(set (match_operand:BLK 0 "memory_operand")
9062 (match_operand 2 "const_int_operand"))
9063 (use (match_operand:QI 1 "const_int_operand"))
9064 (use (match_operand:QI 3 "const_int_operand"))])]
9065 "TARGET_SH1 && optimize"
9067 if (optimize_insn_for_size_p ())
9070 sh_expand_setmem (operands);
9075 ;; -------------------------------------------------------------------------
9076 ;; Floating point instructions.
9077 ;; -------------------------------------------------------------------------
9079 ;; FIXME: For now we disallow any memory operands for fpscr loads/stores,
9080 ;; except for post-inc loads and pre-dec stores for push/pop purposes.
9081 ;; This avoids problems with reload. As a consequence, user initiated fpscr
9082 ;; stores to memory will always be ferried through a general register.
9083 ;; User initiated fpscr loads always have to undergo bit masking to preserve
9084 ;; the current fpu mode settings for the compiler generated code. Thus such
9085 ;; fpscr loads will always have to go through general registers anyways.
9086 (define_insn "lds_fpscr"
9087 [(set (reg:SI FPSCR_REG)
9088 (match_operand:SI 0 "fpscr_movsrc_operand" "r,>"))
9089 (set (reg:SI FPSCR_STAT_REG)
9090 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_STAT))
9091 (set (reg:SI FPSCR_MODES_REG)
9092 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
9097 [(set_attr "type" "gp_fpscr,mem_fpscr")])
9099 ;; A move fpscr -> reg schedules like a move mac -> reg. Thus we use mac_gp
9101 (define_insn "sts_fpscr"
9102 [(set (match_operand:SI 0 "fpscr_movdst_operand" "=r,<")
9104 (use (reg:SI FPSCR_STAT_REG))
9105 (use (reg:SI FPSCR_MODES_REG))]
9110 [(set_attr "type" "mac_gp,fstore")])
9112 (define_expand "set_fpscr"
9113 [(parallel [(set (reg:SI FPSCR_REG)
9114 (match_operand:SI 0 "general_operand"))
9115 (set (reg:SI FPSCR_STAT_REG)
9116 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))])]
9119 /* We have to mask out the FR, SZ and PR bits. To do that, we need to
9120 get the current FPSCR value first.
9121 (a & ~mask) | (b & mask) = a ^ ((a ^ b) & mask) */
9123 rtx mask = force_reg (SImode, GEN_INT (FPSCR_FR | FPSCR_SZ | FPSCR_PR));
9125 rtx a = force_reg (SImode, operands[0]);
9127 rtx b = gen_reg_rtx (SImode);
9128 emit_insn (gen_sts_fpscr (b));
9130 rtx a_xor_b = gen_reg_rtx (SImode);
9131 emit_insn (gen_xorsi3 (a_xor_b, a, b));
9133 rtx a_xor_b_and_mask = gen_reg_rtx (SImode);
9134 emit_insn (gen_andsi3 (a_xor_b_and_mask, a_xor_b, mask));
9136 rtx r = gen_reg_rtx (SImode);
9137 emit_insn (gen_xorsi3 (r, a_xor_b_and_mask, a));
9138 emit_insn (gen_lds_fpscr (r));
9143 ;; ??? This uses the fp unit, but has no type indicating that.
9144 ;; If we did that, this would either give a bogus latency or introduce
9145 ;; a bogus FIFO constraint.
9146 ;; Since this insn is currently only used for prologues/epilogues,
9147 ;; it is probably best to claim no function unit, which matches the
9149 (define_insn "toggle_sz"
9150 [(set (reg:SI FPSCR_REG)
9151 (xor:SI (reg:SI FPSCR_REG) (const_int FPSCR_SZ)))
9152 (set (reg:SI FPSCR_MODES_REG)
9153 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
9156 [(set_attr "type" "fpscr_toggle") (set_attr "fp_set" "unknown")])
9158 ;; Toggle FPU precision PR mode.
9160 (define_insn "toggle_pr"
9161 [(set (reg:SI FPSCR_REG)
9162 (xor:SI (reg:SI FPSCR_REG) (const_int FPSCR_PR)))
9163 (set (reg:SI FPSCR_MODES_REG)
9164 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
9167 [(set_attr "type" "fpscr_toggle")])
9169 (define_expand "addsf3"
9170 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9171 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand")
9172 (match_operand:SF 2 "fp_arith_reg_operand")))]
9175 emit_insn (gen_addsf3_i (operands[0], operands[1], operands[2]));
9179 (define_insn "addsf3_i"
9180 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9181 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
9182 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
9183 (clobber (reg:SI FPSCR_STAT_REG))
9184 (use (reg:SI FPSCR_MODES_REG))]
9187 [(set_attr "type" "fp")
9188 (set_attr "fp_mode" "single")])
9190 (define_expand "subsf3"
9191 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
9192 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
9193 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
9196 emit_insn (gen_subsf3_i (operands[0], operands[1], operands[2]));
9200 (define_insn "subsf3_i"
9201 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9202 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
9203 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
9204 (clobber (reg:SI FPSCR_STAT_REG))
9205 (use (reg:SI FPSCR_MODES_REG))]
9208 [(set_attr "type" "fp")
9209 (set_attr "fp_mode" "single")])
9211 (define_expand "mulsf3"
9212 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
9213 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
9214 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
9217 emit_insn (gen_mulsf3_i (operands[0], operands[1], operands[2]));
9221 (define_insn "mulsf3_i"
9222 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9223 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
9224 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
9225 (clobber (reg:SI FPSCR_STAT_REG))
9226 (use (reg:SI FPSCR_MODES_REG))]
9229 [(set_attr "type" "fp")
9230 (set_attr "fp_mode" "single")])
9232 ;; FMA (fused multiply-add) patterns
9233 (define_expand "fmasf4"
9234 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9235 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand")
9236 (match_operand:SF 2 "fp_arith_reg_operand")
9237 (match_operand:SF 3 "fp_arith_reg_operand")))]
9240 emit_insn (gen_fmasf4_i (operands[0], operands[1], operands[2], operands[3]));
9244 (define_insn "fmasf4_i"
9245 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9246 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand" "w")
9247 (match_operand:SF 2 "fp_arith_reg_operand" "f")
9248 (match_operand:SF 3 "fp_arith_reg_operand" "0")))
9249 (clobber (reg:SI FPSCR_STAT_REG))
9250 (use (reg:SI FPSCR_MODES_REG))]
9253 [(set_attr "type" "fp")
9254 (set_attr "fp_mode" "single")])
9256 ;; For some cases such as 'a * b + a' the FMA pattern is not generated by
9257 ;; previous transformations. If FMA is generally allowed, let the combine
9259 (define_insn_and_split "*fmasf4"
9260 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9261 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%w")
9262 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
9263 (match_operand:SF 3 "arith_reg_operand" "0")))
9264 (clobber (reg:SI FPSCR_STAT_REG))
9265 (use (reg:SI FPSCR_MODES_REG))]
9266 "TARGET_SH2E && flag_fp_contract_mode != FP_CONTRACT_OFF"
9268 "&& can_create_pseudo_p ()"
9269 [(parallel [(set (match_dup 0)
9270 (fma:SF (match_dup 1) (match_dup 2) (match_dup 3)))
9271 (clobber (reg:SI FPSCR_STAT_REG))
9272 (use (reg:SI FPSCR_MODES_REG))])]
9274 /* Change 'b * a + a' into 'a * b + a'.
9275 This is better for register allocation. */
9276 if (REGNO (operands[2]) == REGNO (operands[3]))
9277 std::swap (operands[1], operands[2]);
9279 [(set_attr "type" "fp")
9280 (set_attr "fp_mode" "single")])
9282 (define_expand "divsf3"
9283 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9284 (div:SF (match_operand:SF 1 "fp_arith_reg_operand")
9285 (match_operand:SF 2 "fp_arith_reg_operand")))]
9288 emit_insn (gen_divsf3_i (operands[0], operands[1], operands[2]));
9292 (define_insn "divsf3_i"
9293 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9294 (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
9295 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
9296 (clobber (reg:SI FPSCR_STAT_REG))
9297 (use (reg:SI FPSCR_MODES_REG))]
9300 [(set_attr "type" "fdiv")
9301 (set_attr "fp_mode" "single")])
9303 (define_expand "floatsisf2"
9304 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
9305 (float:SF (match_operand:SI 1 "fpul_operand" "")))]
9308 emit_insn (gen_floatsisf2_i4 (operands[0], operands[1]));
9312 (define_insn "floatsisf2_i4"
9313 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9314 (float:SF (match_operand:SI 1 "fpul_operand" "y")))
9315 (clobber (reg:SI FPSCR_STAT_REG))
9316 (use (reg:SI FPSCR_MODES_REG))]
9319 [(set_attr "type" "fp")
9320 (set_attr "fp_mode" "single")])
9322 (define_expand "fix_truncsfsi2"
9323 [(set (match_operand:SI 0 "fpul_operand")
9324 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand")))]
9327 emit_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1]));
9331 (define_insn "fix_truncsfsi2_i4"
9332 [(set (match_operand:SI 0 "fpul_operand" "=y")
9333 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))
9334 (clobber (reg:SI FPSCR_STAT_REG))
9335 (use (reg:SI FPSCR_MODES_REG))]
9338 [(set_attr "type" "ftrc_s")
9339 (set_attr "fp_mode" "single")])
9341 (define_insn "cmpgtsf_t"
9342 [(set (reg:SI T_REG)
9343 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
9344 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
9345 (clobber (reg:SI FPSCR_STAT_REG))
9346 (use (reg:SI FPSCR_MODES_REG))]
9347 "TARGET_SH2E || TARGET_SH4 || TARGET_SH2A_SINGLE"
9349 [(set_attr "type" "fp_cmp")
9350 (set_attr "fp_mode" "single")])
9352 (define_insn "cmpeqsf_t"
9353 [(set (reg:SI T_REG)
9354 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
9355 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
9356 (clobber (reg:SI FPSCR_STAT_REG))
9357 (use (reg:SI FPSCR_MODES_REG))]
9358 "TARGET_SH2E || TARGET_SH4 || TARGET_SH2A_SINGLE"
9360 [(set_attr "type" "fp_cmp")
9361 (set_attr "fp_mode" "single")])
9363 (define_insn "ieee_ccmpeqsf_t"
9364 [(set (reg:SI T_REG)
9365 (ior:SI (reg:SI T_REG)
9366 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
9367 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))
9368 (clobber (reg:SI FPSCR_STAT_REG))
9369 (use (reg:SI FPSCR_MODES_REG))]
9370 "TARGET_IEEE && TARGET_SH2E"
9372 return output_ieee_ccmpeq (insn, operands);
9374 [(set_attr "length" "4")
9375 (set_attr "fp_mode" "single")])
9377 (define_expand "cbranchsf4"
9379 (if_then_else (match_operator 0 "ordered_comparison_operator"
9380 [(match_operand:SF 1 "arith_operand" "")
9381 (match_operand:SF 2 "arith_operand" "")])
9382 (match_operand 3 "" "")
9386 sh_emit_compare_and_branch (operands, SFmode);
9390 (define_expand "negsf2"
9391 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9392 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand")))]
9395 (define_insn "*negsf2_i"
9396 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9397 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))]
9400 [(set_attr "type" "fmove")])
9402 (define_expand "sqrtsf2"
9403 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
9404 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
9407 emit_insn (gen_sqrtsf2_i (operands[0], operands[1]));
9411 (define_insn "sqrtsf2_i"
9412 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9413 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
9414 (clobber (reg:SI FPSCR_STAT_REG))
9415 (use (reg:SI FPSCR_MODES_REG))]
9418 [(set_attr "type" "fdiv")
9419 (set_attr "fp_mode" "single")])
9421 (define_insn "rsqrtsf2"
9422 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9423 (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "0")]
9425 (clobber (reg:SI FPSCR_STAT_REG))
9426 (use (reg:SI FPSCR_MODES_REG))]
9427 "TARGET_FPU_ANY && TARGET_FSRRA"
9429 [(set_attr "type" "fsrra")
9430 (set_attr "fp_mode" "single")])
9432 ;; When the sincos pattern is defined, the builtin functions sin and cos
9433 ;; will be expanded to the sincos pattern and one of the output values will
9435 (define_expand "sincossf3"
9436 [(set (match_operand:SF 0 "nonimmediate_operand")
9437 (unspec:SF [(match_operand:SF 2 "fp_arith_reg_operand")] UNSPEC_FCOSA))
9438 (set (match_operand:SF 1 "nonimmediate_operand")
9439 (unspec:SF [(match_dup 2)] UNSPEC_FSINA))]
9440 "TARGET_FPU_ANY && TARGET_FSCA"
9442 rtx scaled = gen_reg_rtx (SFmode);
9443 rtx truncated = gen_reg_rtx (SImode);
9444 rtx fsca = gen_reg_rtx (V2SFmode);
9445 rtx scale_reg = force_reg (SFmode, sh_fsca_sf2int ());
9447 emit_insn (gen_mulsf3 (scaled, operands[2], scale_reg));
9448 emit_insn (gen_fix_truncsfsi2 (truncated, scaled));
9449 emit_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf ()));
9451 emit_move_insn (operands[0], gen_rtx_SUBREG (SFmode, fsca, 4));
9452 emit_move_insn (operands[1], gen_rtx_SUBREG (SFmode, fsca, 0));
9456 (define_insn_and_split "fsca"
9457 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
9459 (unspec:SF [(mult:SF
9460 (float:SF (match_operand:SI 1 "fpul_fsca_operand" "y"))
9461 (match_operand:SF 2 "fsca_scale_factor" "i"))
9463 (unspec:SF [(mult:SF (float:SF (match_dup 1)) (match_dup 2))
9465 (clobber (reg:SI FPSCR_STAT_REG))
9466 (use (reg:SI FPSCR_MODES_REG))]
9467 "TARGET_FPU_ANY && TARGET_FSCA"
9469 "&& !fpul_operand (operands[1], SImode)"
9472 /* If operands[1] is something like (fix:SF (float:SF (reg:SI))) reduce it
9473 to a simple reg, otherwise reload will have trouble reloading the
9474 pseudo into fpul. */
9475 rtx x = XEXP (operands[1], 0);
9476 while (x != NULL_RTX && !fpul_operand (x, SImode))
9478 gcc_assert (GET_CODE (x) == FIX || GET_CODE (x) == FLOAT);
9481 gcc_assert (x != NULL_RTX && fpul_operand (x, SImode));
9482 emit_insn (gen_fsca (operands[0], x, operands[2]));
9485 [(set_attr "type" "fsca")
9486 (set_attr "fp_mode" "single")])
9488 (define_expand "abssf2"
9489 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9490 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand")))]
9493 (define_insn "*abssf2_i"
9494 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9495 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))]
9498 [(set_attr "type" "fmove")])
9500 (define_expand "adddf3"
9501 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9502 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
9503 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
9506 emit_insn (gen_adddf3_i (operands[0], operands[1], operands[2]));
9510 (define_insn "adddf3_i"
9511 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9512 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
9513 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9514 (clobber (reg:SI FPSCR_STAT_REG))
9515 (use (reg:SI FPSCR_MODES_REG))]
9518 [(set_attr "type" "dfp_arith")
9519 (set_attr "fp_mode" "double")])
9521 (define_expand "subdf3"
9522 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9523 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
9524 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
9527 emit_insn (gen_subdf3_i (operands[0], operands[1], operands[2]));
9531 (define_insn "subdf3_i"
9532 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9533 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
9534 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9535 (clobber (reg:SI FPSCR_STAT_REG))
9536 (use (reg:SI FPSCR_MODES_REG))]
9539 [(set_attr "type" "dfp_arith")
9540 (set_attr "fp_mode" "double")])
9542 (define_expand "muldf3"
9543 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9544 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
9545 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
9548 emit_insn (gen_muldf3_i (operands[0], operands[1], operands[2]));
9552 (define_insn "muldf3_i"
9553 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9554 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
9555 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9556 (clobber (reg:SI FPSCR_STAT_REG))
9557 (use (reg:SI FPSCR_MODES_REG))]
9560 [(set_attr "type" "dfp_mul")
9561 (set_attr "fp_mode" "double")])
9563 (define_expand "divdf3"
9564 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9565 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
9566 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
9569 emit_insn (gen_divdf3_i (operands[0], operands[1], operands[2]));
9573 (define_insn "divdf3_i"
9574 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9575 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
9576 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9577 (clobber (reg:SI FPSCR_STAT_REG))
9578 (use (reg:SI FPSCR_MODES_REG))]
9581 [(set_attr "type" "dfdiv")
9582 (set_attr "fp_mode" "double")])
9584 (define_expand "floatsidf2"
9585 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9586 (float:DF (match_operand:SI 1 "fpul_operand" "")))]
9589 emit_insn (gen_floatsidf2_i (operands[0], operands[1]));
9593 (define_insn "floatsidf2_i"
9594 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9595 (float:DF (match_operand:SI 1 "fpul_operand" "y")))
9596 (clobber (reg:SI FPSCR_STAT_REG))
9597 (use (reg:SI FPSCR_MODES_REG))]
9600 [(set_attr "type" "dfp_conv")
9601 (set_attr "fp_mode" "double")])
9603 (define_expand "fix_truncdfsi2"
9604 [(set (match_operand:SI 0 "fpul_operand" "")
9605 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "")))]
9608 emit_insn (gen_fix_truncdfsi2_i (operands[0], operands[1]));
9612 (define_insn "fix_truncdfsi2_i"
9613 [(set (match_operand:SI 0 "fpul_operand" "=y")
9614 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9615 (clobber (reg:SI FPSCR_STAT_REG))
9616 (use (reg:SI FPSCR_MODES_REG))]
9619 [(set_attr "type" "dfp_conv")
9620 (set_attr "dfp_comp" "no")
9621 (set_attr "fp_mode" "double")])
9623 (define_insn "cmpgtdf_t"
9624 [(set (reg:SI T_REG)
9625 (gt:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
9626 (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9627 (clobber (reg:SI FPSCR_STAT_REG))
9628 (use (reg:SI FPSCR_MODES_REG))]
9631 [(set_attr "type" "dfp_cmp")
9632 (set_attr "fp_mode" "double")])
9634 (define_insn "cmpeqdf_t"
9635 [(set (reg:SI T_REG)
9636 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
9637 (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9638 (clobber (reg:SI FPSCR_STAT_REG))
9639 (use (reg:SI FPSCR_MODES_REG))]
9642 [(set_attr "type" "dfp_cmp")
9643 (set_attr "fp_mode" "double")])
9645 (define_insn "*ieee_ccmpeqdf_t"
9646 [(set (reg:SI T_REG)
9647 (ior:SI (reg:SI T_REG)
9648 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
9649 (match_operand:DF 1 "fp_arith_reg_operand" "f"))))
9650 (clobber (reg:SI FPSCR_STAT_REG))
9651 (use (reg:SI FPSCR_MODES_REG))]
9652 "TARGET_IEEE && TARGET_FPU_DOUBLE"
9654 return output_ieee_ccmpeq (insn, operands);
9656 [(set_attr "length" "4")
9657 (set_attr "fp_mode" "double")])
9659 (define_expand "cbranchdf4"
9661 (if_then_else (match_operator 0 "ordered_comparison_operator"
9662 [(match_operand:DF 1 "arith_operand" "")
9663 (match_operand:DF 2 "arith_operand" "")])
9664 (match_operand 3 "" "")
9668 sh_emit_compare_and_branch (operands, DFmode);
9672 (define_expand "negdf2"
9673 [(set (match_operand:DF 0 "fp_arith_reg_operand")
9674 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
9675 "TARGET_FPU_DOUBLE")
9677 (define_insn "*negdf2_i"
9678 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9679 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))]
9682 [(set_attr "type" "fmove")])
9684 (define_expand "sqrtdf2"
9685 [(set (match_operand:DF 0 "fp_arith_reg_operand")
9686 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
9689 emit_insn (gen_sqrtdf2_i (operands[0], operands[1]));
9693 (define_insn "sqrtdf2_i"
9694 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9695 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
9696 (clobber (reg:SI FPSCR_STAT_REG))
9697 (use (reg:SI FPSCR_MODES_REG))]
9700 [(set_attr "type" "dfdiv")
9701 (set_attr "fp_mode" "double")])
9703 (define_expand "absdf2"
9704 [(set (match_operand:DF 0 "fp_arith_reg_operand")
9705 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
9706 "TARGET_FPU_DOUBLE")
9708 (define_insn "*absdf2_i"
9709 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9710 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))]
9713 [(set_attr "type" "fmove")])
9715 (define_expand "extendsfdf2"
9716 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9717 (float_extend:DF (match_operand:SF 1 "fpul_operand" "")))]
9720 emit_insn (gen_extendsfdf2_i4 (operands[0], operands[1]));
9724 (define_insn "extendsfdf2_i4"
9725 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9726 (float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
9727 (clobber (reg:SI FPSCR_STAT_REG))
9728 (use (reg:SI FPSCR_MODES_REG))]
9731 [(set_attr "type" "fp")
9732 (set_attr "fp_mode" "double")])
9734 (define_expand "truncdfsf2"
9735 [(set (match_operand:SF 0 "fpul_operand" "")
9736 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "")))]
9739 emit_insn (gen_truncdfsf2_i4 (operands[0], operands[1]));
9743 (define_insn "truncdfsf2_i4"
9744 [(set (match_operand:SF 0 "fpul_operand" "=y")
9745 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9746 (clobber (reg:SI FPSCR_STAT_REG))
9747 (use (reg:SI FPSCR_MODES_REG))]
9750 [(set_attr "type" "fp")
9751 (set_attr "fp_mode" "double")])
9753 ;; -------------------------------------------------------------------------
9754 ;; Bit field extract patterns.
9755 ;; -------------------------------------------------------------------------
9757 ;; These give better code for packed bitfields, because they allow
9758 ;; auto-increment addresses to be generated.
9760 (define_expand "insv"
9761 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
9762 (match_operand:SI 1 "immediate_operand" "")
9763 (match_operand:SI 2 "immediate_operand" ""))
9764 (match_operand:SI 3 "general_operand" ""))]
9765 "TARGET_SH1 && TARGET_BIG_ENDIAN"
9767 rtx addr_target, orig_address, shift_reg, qi_val;
9768 HOST_WIDE_INT bitsize, size, v = 0;
9769 rtx x = operands[3];
9771 if (TARGET_SH2A && TARGET_BITOPS
9772 && (satisfies_constraint_Sbw (operands[0])
9773 || satisfies_constraint_Sbv (operands[0]))
9774 && satisfies_constraint_M (operands[1])
9775 && satisfies_constraint_K03 (operands[2]))
9777 if (satisfies_constraint_N (operands[3]))
9779 emit_insn (gen_bclr_m2a (operands[0], operands[2]));
9782 else if (satisfies_constraint_M (operands[3]))
9784 emit_insn (gen_bset_m2a (operands[0], operands[2]));
9787 else if ((REG_P (operands[3]) && REGNO (operands[3]) == T_REG)
9788 && satisfies_constraint_M (operands[1]))
9790 emit_insn (gen_bst_m2a (operands[0], operands[2]));
9793 else if (REG_P (operands[3])
9794 && satisfies_constraint_M (operands[1]))
9796 emit_insn (gen_bldsi_reg (operands[3], const0_rtx));
9797 emit_insn (gen_bst_m2a (operands[0], operands[2]));
9801 /* ??? expmed doesn't care for non-register predicates. */
9802 if (! memory_operand (operands[0], VOIDmode)
9803 || ! immediate_operand (operands[1], VOIDmode)
9804 || ! immediate_operand (operands[2], VOIDmode)
9805 || ! general_operand (x, VOIDmode))
9807 /* If this isn't a 16 / 24 / 32 bit field, or if
9808 it doesn't start on a byte boundary, then fail. */
9809 bitsize = INTVAL (operands[1]);
9810 if (bitsize < 16 || bitsize > 32 || bitsize % 8 != 0
9811 || (INTVAL (operands[2]) % 8) != 0)
9815 orig_address = XEXP (operands[0], 0);
9816 shift_reg = gen_reg_rtx (SImode);
9817 if (CONST_INT_P (x))
9820 qi_val = force_reg (QImode, GEN_INT (trunc_int_for_mode (v, QImode)));
9824 emit_insn (gen_movsi (shift_reg, operands[3]));
9825 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
9827 addr_target = copy_addr_to_reg (plus_constant (Pmode,
9828 orig_address, size - 1));
9830 operands[0] = replace_equiv_address (operands[0], addr_target);
9831 emit_insn (gen_movqi (operands[0], qi_val));
9835 if (CONST_INT_P (x))
9837 = force_reg (QImode, GEN_INT (trunc_int_for_mode (v >>= 8, QImode)));
9840 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
9841 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
9843 emit_insn (gen_addsi3 (addr_target, addr_target, constm1_rtx));
9844 emit_insn (gen_movqi (operands[0], qi_val));
9850 (define_insn "movua"
9851 [(set (match_operand:SI 0 "register_operand" "=z")
9852 (unspec:SI [(match_operand:BLK 1 "unaligned_load_operand" "Sua>")]
9856 [(set_attr "type" "movua")])
9858 ;; We shouldn't need this, but cse replaces increments with references
9859 ;; to other regs before flow has a chance to create post_inc
9860 ;; addressing modes, and only postreload's cse_move2add brings the
9861 ;; increments back to a usable form.
9863 [(set (match_operand:SI 0 "register_operand" "")
9864 (sign_extract:SI (mem:SI (match_operand:SI 1 "register_operand" ""))
9865 (const_int 32) (const_int 0)))
9866 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
9867 "TARGET_SH4A && REGNO (operands[0]) != REGNO (operands[1])"
9868 [(set (match_operand:SI 0 "register_operand" "")
9869 (sign_extract:SI (mem:SI (post_inc:SI
9870 (match_operand:SI 1 "register_operand" "")))
9871 (const_int 32) (const_int 0)))]
9874 (define_expand "extv"
9875 [(set (match_operand:SI 0 "register_operand" "")
9876 (sign_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
9877 (match_operand 2 "const_int_operand" "")
9878 (match_operand 3 "const_int_operand" "")))]
9879 "TARGET_SH4A || TARGET_SH2A"
9881 if (TARGET_SH2A && TARGET_BITOPS
9882 && (satisfies_constraint_Sbw (operands[1])
9883 || satisfies_constraint_Sbv (operands[1]))
9884 && satisfies_constraint_M (operands[2])
9885 && satisfies_constraint_K03 (operands[3]))
9887 emit_insn (gen_bldsign_m2a (operands[1], operands[3]));
9888 if (REGNO (operands[0]) != T_REG)
9889 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
9893 && INTVAL (operands[2]) == 32
9894 && INTVAL (operands[3]) == 0
9895 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
9897 rtx src = adjust_address (operands[1], BLKmode, 0);
9898 set_mem_size (src, 4);
9899 emit_insn (gen_movua (operands[0], src));
9906 (define_expand "extzv"
9907 [(set (match_operand:SI 0 "register_operand" "")
9908 (zero_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
9909 (match_operand 2 "const_int_operand" "")
9910 (match_operand 3 "const_int_operand" "")))]
9911 "TARGET_SH4A || TARGET_SH2A"
9913 if (TARGET_SH2A && TARGET_BITOPS
9914 && (satisfies_constraint_Sbw (operands[1])
9915 || satisfies_constraint_Sbv (operands[1]))
9916 && satisfies_constraint_M (operands[2])
9917 && satisfies_constraint_K03 (operands[3]))
9919 emit_insn (gen_bld_m2a (operands[1], operands[3]));
9920 if (REGNO (operands[0]) != T_REG)
9921 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
9925 && INTVAL (operands[2]) == 32
9926 && INTVAL (operands[3]) == 0
9927 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
9929 rtx src = adjust_address (operands[1], BLKmode, 0);
9930 set_mem_size (src, 4);
9931 emit_insn (gen_movua (operands[0], src));
9938 ;; -------------------------------------------------------------------------
9939 ;; Extract negated single bit and zero extend it.
9940 ;; Generally we don't care about the exact xor const_int value, as long
9941 ;; as it contains the extracted bit. For simplicity, the pattern variations
9942 ;; that convert everything into the primary '*neg_zero_extract_0' pattern use
9943 ;; a xor const_int -1 value.
9945 (define_insn_and_split "*neg_zero_extract_0"
9946 [(set (reg:SI T_REG)
9947 (zero_extract:SI (xor:QIHISI (match_operand:QIHISI 0 "arith_reg_operand")
9948 (match_operand 1 "const_int_operand"))
9950 (match_operand 2 "const_int_operand")))]
9951 "TARGET_SH1 && can_create_pseudo_p ()
9952 && INTVAL (operands[1]) & (1LL << INTVAL (operands[2]))"
9955 [(set (reg:SI T_REG) (eq:SI (and:SI (match_dup 0) (match_dup 2))
9958 if (INTVAL (operands[2]) == 31 && <MODE>mode == SImode)
9960 /* Use cmp/pz to extract bit 31 into the T bit. */
9961 emit_insn (gen_cmpgesi_t (operands[0], const0_rtx));
9965 operands[2] = GEN_INT ((1 << INTVAL (operands[2])));
9966 if (GET_MODE (operands[0]) != SImode)
9967 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
9970 (define_insn_and_split "*neg_zero_extract_1"
9971 [(set (reg:SI T_REG)
9972 (and:SI (not:SI (match_operand:SI 0 "arith_reg_operand"))
9977 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
9978 (const_int 1) (const_int 0)))])
9980 ;; x & (1 << n) == 0: 0x00000000 + 1 = 1
9981 ;; x & (1 << n) != 0: 0xFFFFFFFF + 1 = 0
9982 (define_insn_and_split "*neg_zero_extract_2"
9983 [(set (reg:SI T_REG)
9984 (plus:SI (sign_extract:SI (match_operand:QIHISI 0 "arith_reg_operand")
9986 (match_operand 1 "const_int_operand"))
9988 "TARGET_SH1 && can_create_pseudo_p ()"
9991 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
9992 (const_int 1) (match_dup 1)))])
9994 ;; (signed)x >> 31 + 1 = (x >= 0) ^ 1
9995 (define_insn_and_split "*neg_zero_extract_3"
9996 [(set (reg:SI T_REG)
9997 (plus:SI (ashiftrt:SI (match_operand:SI 0 "arith_reg_operand")
10000 "TARGET_SH1 && can_create_pseudo_p ()"
10003 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
10004 (const_int 1) (const_int 31)))])
10006 ;; This is required for some bit patterns of DImode subregs.
10007 ;; It looks like combine gets confused by the DImode right shift and fails
10008 ;; to simplify things.
10009 (define_insn_and_split "*neg_zero_extract_4"
10010 [(set (reg:SI T_REG)
10012 (lshiftrt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
10013 (match_operand 1 "const_int_operand"))
10014 (match_operand 2 "const_int_operand"))
10015 (not:SI (ashift:SI (match_operand:SI 3 "arith_reg_operand")
10016 (match_operand 4 "const_int_operand"))))
10018 "TARGET_SH1 && can_create_pseudo_p ()
10019 && INTVAL (operands[4]) > 0
10020 && INTVAL (operands[1]) & (1LL << INTVAL (operands[2]))"
10023 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
10024 (const_int 1) (match_dup 2)))])
10026 (define_insn_and_split "*neg_zero_extract_5"
10027 [(set (reg:SI T_REG)
10028 (and:SI (not:SI (subreg:SI
10029 (lshiftrt:DI (match_operand:DI 0 "arith_reg_operand")
10030 (match_operand 1 "const_int_operand"))
10033 "TARGET_SH1 && TARGET_LITTLE_ENDIAN && can_create_pseudo_p ()
10034 && INTVAL (operands[1]) < 32"
10037 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
10038 (const_int 1) (match_dup 1)))]
10040 operands[0] = gen_lowpart (SImode, operands[0]);
10043 (define_insn_and_split "*neg_zero_extract_6"
10044 [(set (reg:SI T_REG)
10045 (and:SI (not:SI (subreg:SI
10046 (lshiftrt:DI (match_operand:DI 0 "arith_reg_operand")
10047 (match_operand 1 "const_int_operand"))
10050 "TARGET_SH1 && TARGET_BIG_ENDIAN && can_create_pseudo_p ()
10051 && INTVAL (operands[1]) < 32"
10054 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
10055 (const_int 1) (match_dup 1)))]
10057 operands[0] = gen_lowpart (SImode, operands[0]);
10060 ;; -------------------------------------------------------------------------
10061 ;; Extract single bit and zero extend it.
10062 ;; All patterns store the result bit in the T bit, although that is not
10063 ;; always possible to do with a single insn and a nott must be appended.
10064 ;; The trailing nott will be optimized away in most cases. E.g. if the
10065 ;; extracted bit is fed into a branch condition, the condition can be
10066 ;; inverted and the nott will be eliminated.
10067 ;; FIXME: In cases where the trailing nott can't be eliminated, try to
10068 ;; convert it into a (not, tst) sequence, which could be better on non-SH2A.
10070 ;; On SH2A the 'bld<mode>_reg' insn will be used if the bit position fits.
10071 (define_insn_and_split "*zero_extract_0"
10072 [(set (reg:SI T_REG)
10073 (zero_extract:SI (match_operand:QIHISI 0 "arith_reg_operand")
10075 (match_operand 1 "const_int_operand")))]
10076 "TARGET_SH1 && can_create_pseudo_p ()
10077 && !(TARGET_SH2A && satisfies_constraint_K03 (operands[1]))"
10080 [(set (reg:SI T_REG) (eq:SI (and:SI (match_dup 0) (match_dup 1))
10082 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))]
10084 if (INTVAL (operands[1]) == 31 && <MODE>mode == SImode)
10086 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
10090 operands[1] = GEN_INT (1 << INTVAL (operands[1]));
10091 if (GET_MODE (operands[0]) != SImode)
10092 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
10095 ;; This is required for some bit patterns of DImode subregs.
10096 ;; It looks like combine gets confused by the DImode right shift and fails
10097 ;; to simplify things.
10098 (define_insn_and_split "*zero_extract_1"
10099 [(set (reg:SI T_REG)
10100 (subreg:SI (zero_extract:DI (match_operand:SI 0 "arith_reg_operand")
10102 (match_operand 1 "const_int_operand"))
10104 "TARGET_SH1 && TARGET_LITTLE_ENDIAN && can_create_pseudo_p ()
10105 && INTVAL (operands[1]) < 32"
10108 [(set (reg:SI T_REG)
10109 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))])
10111 (define_insn_and_split "*zero_extract_2"
10112 [(set (reg:SI T_REG)
10113 (subreg:SI (zero_extract:DI (match_operand:SI 0 "arith_reg_operand")
10115 (match_operand 1 "const_int_operand"))
10117 "TARGET_SH1 && TARGET_BIG_ENDIAN && can_create_pseudo_p ()
10118 && INTVAL (operands[1]) < 32"
10121 [(set (reg:SI T_REG)
10122 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))])
10124 (define_insn_and_split "*zero_extract_3"
10125 [(set (match_operand:SI 0 "arith_reg_dest")
10126 (and:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
10127 (match_operand 2 "const_int_operand"))
10128 (match_operand 3 "const_int_operand")))
10129 (clobber (reg:SI T_REG))]
10130 "TARGET_SH1 && can_create_pseudo_p ()
10131 && exact_log2 (INTVAL (operands[3])) >= 0"
10136 int rshift = INTVAL (operands[2]);
10137 int lshift = exact_log2 (INTVAL (operands[3]));
10139 rtx tmp = gen_reg_rtx (SImode);
10140 emit_insn (gen_rtx_PARALLEL (VOIDmode,
10143 gen_rtx_ZERO_EXTRACT (SImode, operands[1], const1_rtx,
10144 GEN_INT (rshift + lshift))),
10145 gen_rtx_CLOBBER (VOIDmode, get_t_reg_rtx ()))));
10146 emit_insn (gen_ashlsi3 (operands[0], tmp, GEN_INT (lshift)));
10149 ;; -------------------------------------------------------------------------
10150 ;; SH2A instructions for bitwise operations.
10151 ;; FIXME: Convert multiple instruction insns to insn_and_split.
10152 ;; FIXME: Use iterators to fold at least and,xor,or insn variations.
10154 ;; Clear a bit in a memory location.
10155 (define_insn "bclr_m2a"
10156 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
10158 (not:QI (ashift:QI (const_int 1)
10159 (match_operand:QI 1 "const_int_operand" "K03,K03")))
10161 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10164 bclr.b %1,@(0,%t0)"
10165 [(set_attr "length" "4,4")])
10167 (define_insn "bclrmem_m2a"
10168 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
10169 (and:QI (match_dup 0)
10170 (match_operand:QI 1 "const_int_operand" "Psz,Psz")))]
10171 "TARGET_SH2A && satisfies_constraint_Psz (operands[1]) && TARGET_BITOPS"
10174 bclr.b %W1,@(0,%t0)"
10175 [(set_attr "length" "4,4")])
10177 ;; Set a bit in a memory location.
10178 (define_insn "bset_m2a"
10179 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
10181 (ashift:QI (const_int 1)
10182 (match_operand:QI 1 "const_int_operand" "K03,K03"))
10184 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10187 bset.b %1,@(0,%t0)"
10188 [(set_attr "length" "4,4")])
10190 (define_insn "bsetmem_m2a"
10191 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
10192 (ior:QI (match_dup 0)
10193 (match_operand:QI 1 "const_int_operand" "Pso,Pso")))]
10194 "TARGET_SH2A && satisfies_constraint_Pso (operands[1]) && TARGET_BITOPS"
10197 bset.b %V1,@(0,%t0)"
10198 [(set_attr "length" "4,4")])
10200 ;;; Transfer the contents of the T bit to a specified bit of memory.
10201 (define_insn "bst_m2a"
10202 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,m")
10203 (if_then_else (eq (reg:SI T_REG) (const_int 0))
10205 (not:QI (ashift:QI (const_int 1)
10206 (match_operand:QI 1 "const_int_operand" "K03,K03")))
10209 (ashift:QI (const_int 1) (match_dup 1))
10211 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10215 [(set_attr "length" "4")])
10217 ;; Store a specified bit of memory in the T bit.
10218 (define_insn "bld_m2a"
10219 [(set (reg:SI T_REG)
10221 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,Sbv")
10223 (match_operand 1 "const_int_operand" "K03,K03")))]
10224 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10228 [(set_attr "length" "4,4")])
10230 ;; Store a specified bit of memory in the T bit.
10231 (define_insn "bldsign_m2a"
10232 [(set (reg:SI T_REG)
10234 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
10236 (match_operand 1 "const_int_operand" "K03,K03")))]
10237 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10241 [(set_attr "length" "4,4")])
10243 ;; Store a specified bit of the LSB 8 bits of a register in the T bit.
10244 (define_insn "bld<mode>_reg"
10245 [(set (reg:SI T_REG)
10246 (zero_extract:SI (match_operand:QIHISI 0 "arith_reg_operand" "r")
10248 (match_operand 1 "const_int_operand" "K03")))]
10249 "TARGET_SH2A && satisfies_constraint_K03 (operands[1])"
10252 ;; Take logical and of a specified bit of memory with the T bit and
10253 ;; store its result in the T bit.
10254 (define_insn "band_m2a"
10255 [(set (reg:SI T_REG)
10256 (and:SI (reg:SI T_REG)
10258 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
10260 (match_operand 1 "const_int_operand" "K03,K03"))))]
10261 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10264 band.b %1,@(0,%t0)"
10265 [(set_attr "length" "4,4")])
10267 (define_insn "bandreg_m2a"
10268 [(set (match_operand:SI 0 "register_operand" "=r,r")
10269 (and:SI (zero_extract:SI
10270 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
10272 (match_operand 2 "const_int_operand" "K03,K03"))
10273 (match_operand:SI 3 "register_operand" "r,r")))]
10274 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
10276 static const char* alt[] =
10278 "band.b %2,%1" "\n"
10281 "band.b %2,@(0,%t1)" "\n"
10284 return alt[which_alternative];
10286 [(set_attr "length" "6,6")])
10288 ;; Take logical or of a specified bit of memory with the T bit and
10289 ;; store its result in the T bit.
10290 (define_insn "bor_m2a"
10291 [(set (reg:SI T_REG)
10292 (ior:SI (reg:SI T_REG)
10294 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
10296 (match_operand 1 "const_int_operand" "K03,K03"))))]
10297 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10301 [(set_attr "length" "4,4")])
10303 (define_insn "borreg_m2a"
10304 [(set (match_operand:SI 0 "register_operand" "=r,r")
10305 (ior:SI (zero_extract:SI
10306 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
10308 (match_operand 2 "const_int_operand" "K03,K03"))
10309 (match_operand:SI 3 "register_operand" "=r,r")))]
10310 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
10312 static const char* alt[] =
10317 "bor.b %2,@(0,%t1)" "\n"
10320 return alt[which_alternative];
10322 [(set_attr "length" "6,6")])
10324 ;; Take exclusive or of a specified bit of memory with the T bit and
10325 ;; store its result in the T bit.
10326 (define_insn "bxor_m2a"
10327 [(set (reg:SI T_REG)
10328 (xor:SI (reg:SI T_REG)
10330 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
10332 (match_operand 1 "const_int_operand" "K03,K03"))))]
10333 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10336 bxor.b %1,@(0,%t0)"
10337 [(set_attr "length" "4,4")])
10339 (define_insn "bxorreg_m2a"
10340 [(set (match_operand:SI 0 "register_operand" "=r,r")
10341 (xor:SI (zero_extract:SI
10342 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
10344 (match_operand 2 "const_int_operand" "K03,K03"))
10345 (match_operand:SI 3 "register_operand" "=r,r")))]
10346 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
10348 static const char* alt[] =
10350 "bxor.b %2,%1" "\n"
10353 "bxor.b %2,@(0,%t1)" "\n"
10356 return alt[which_alternative];
10358 [(set_attr "length" "6,6")])
10360 ;; -------------------------------------------------------------------------
10362 ;; -------------------------------------------------------------------------
10363 ;; This matches cases where the bit in a memory location is set.
10365 [(set (match_operand:SI 0 "register_operand")
10366 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
10368 (ior:SI (match_dup 0)
10369 (match_operand:SI 2 "const_int_operand")))
10371 (match_operand 3 "arith_reg_operand"))]
10372 "TARGET_SH2A && TARGET_BITOPS
10373 && satisfies_constraint_Pso (operands[2])
10374 && REGNO (operands[0]) == REGNO (operands[3])"
10375 [(set (match_dup 1)
10376 (ior:QI (match_dup 1) (match_dup 2)))]
10379 ;; This matches cases where the bit in a memory location is cleared.
10381 [(set (match_operand:SI 0 "register_operand")
10382 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
10384 (and:SI (match_dup 0)
10385 (match_operand:SI 2 "const_int_operand")))
10387 (match_operand 3 "arith_reg_operand"))]
10388 "TARGET_SH2A && TARGET_BITOPS
10389 && satisfies_constraint_Psz (operands[2])
10390 && REGNO (operands[0]) == REGNO (operands[3])"
10391 [(set (match_dup 1)
10392 (and:QI (match_dup 1) (match_dup 2)))]
10395 ;; This matches cases where a stack pointer increment at the start of the
10396 ;; epilogue combines with a stack slot read loading the return value.
10398 [(set (match_operand:SI 0 "arith_reg_operand" "")
10399 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
10400 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
10401 "TARGET_SH1 && REGNO (operands[1]) != REGNO (operands[0])"
10404 ;; See the comment on the dt combiner pattern above.
10406 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
10407 (plus:SI (match_dup 0)
10409 (set (reg:SI T_REG)
10410 (eq:SI (match_dup 0) (const_int 0)))]
10414 ;; The following peepholes fold load sequences for which reload was not
10415 ;; able to generate a displacement addressing move insn.
10416 ;; This can happen when reload has to transform a move insn
10417 ;; without displacement into one with displacement. Or when reload can't
10418 ;; fit a displacement into the insn's constraints. In the latter case, the
10419 ;; load destination reg remains at r0, which reload compensates by inserting
10420 ;; another mov insn.
10424 ;; mov.{b,w} @(r0,r15),r0
10427 ;; mov.{b,w} @(54,r15),r3
10430 [(set (match_operand:SI 0 "arith_reg_dest" "")
10431 (match_operand:SI 1 "const_int_operand" ""))
10432 (set (match_operand:SI 2 "arith_reg_dest" "")
10434 (mem:QI (plus:SI (match_dup 0)
10435 (match_operand:SI 3 "arith_reg_operand" "")))))
10436 (set (match_operand:QI 4 "arith_reg_dest" "")
10437 (match_operand:QI 5 "arith_reg_operand" ""))]
10439 && sh_legitimate_index_p (QImode, operands[1], true, true)
10440 && REGNO (operands[2]) == REGNO (operands[5])
10441 && peep2_reg_dead_p (3, operands[5])"
10442 [(set (match_dup 4) (mem:QI (plus:SI (match_dup 3) (match_dup 1))))]
10446 [(set (match_operand:SI 0 "arith_reg_dest" "")
10447 (match_operand:SI 1 "const_int_operand" ""))
10448 (set (match_operand:SI 2 "arith_reg_dest" "")
10450 (mem:HI (plus:SI (match_dup 0)
10451 (match_operand:SI 3 "arith_reg_operand" "")))))
10452 (set (match_operand:HI 4 "arith_reg_dest" "")
10453 (match_operand:HI 5 "arith_reg_operand" ""))]
10455 && sh_legitimate_index_p (HImode, operands[1], true, true)
10456 && REGNO (operands[2]) == REGNO (operands[5])
10457 && peep2_reg_dead_p (3, operands[5])"
10458 [(set (match_dup 4) (mem:HI (plus:SI (match_dup 3) (match_dup 1))))]
10463 ;; mov.{b,w} @(r0,r15),r1
10465 ;; mov.{b,w} @(54,r15),r1
10468 [(set (match_operand:SI 0 "arith_reg_dest" "")
10469 (match_operand:SI 1 "const_int_operand" ""))
10470 (set (match_operand:SI 2 "arith_reg_dest" "")
10472 (mem:QI (plus:SI (match_dup 0)
10473 (match_operand:SI 3 "arith_reg_operand" "")))))]
10475 && sh_legitimate_index_p (QImode, operands[1], true, true)
10476 && (peep2_reg_dead_p (2, operands[0])
10477 || REGNO (operands[0]) == REGNO (operands[2]))"
10478 [(set (match_dup 2)
10479 (sign_extend:SI (mem:QI (plus:SI (match_dup 3) (match_dup 1)))))]
10483 [(set (match_operand:SI 0 "arith_reg_dest" "")
10484 (match_operand:SI 1 "const_int_operand" ""))
10485 (set (match_operand:SI 2 "arith_reg_dest" "")
10487 (mem:HI (plus:SI (match_dup 0)
10488 (match_operand:SI 3 "arith_reg_operand" "")))))]
10490 && sh_legitimate_index_p (HImode, operands[1], true, true)
10491 && (peep2_reg_dead_p (2, operands[0])
10492 || REGNO (operands[0]) == REGNO (operands[2]))"
10493 [(set (match_dup 2)
10494 (sign_extend:SI (mem:HI (plus:SI (match_dup 3) (match_dup 1)))))]
10498 ;; mov.{b,w} @(r0,r15),r0
10501 ;; mov.{b,w} @(r0,r15),r3
10503 ;; This can happen when initially a displacement address is picked, where
10504 ;; the destination reg is fixed to r0, and then the address is transformed
10505 ;; into 'r0 + reg'.
10507 [(set (match_operand:SI 0 "arith_reg_dest" "")
10509 (mem:QI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
10510 (match_operand:SI 2 "arith_reg_operand" "")))))
10511 (set (match_operand:QI 3 "arith_reg_dest" "")
10512 (match_operand:QI 4 "arith_reg_operand" ""))]
10514 && REGNO (operands[0]) == REGNO (operands[4])
10515 && peep2_reg_dead_p (2, operands[0])"
10516 [(set (match_dup 3)
10517 (mem:QI (plus:SI (match_dup 1) (match_dup 2))))]
10521 [(set (match_operand:SI 0 "arith_reg_dest" "")
10523 (mem:HI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
10524 (match_operand:SI 2 "arith_reg_operand" "")))))
10525 (set (match_operand:HI 3 "arith_reg_dest" "")
10526 (match_operand:HI 4 "arith_reg_operand" ""))]
10528 && REGNO (operands[0]) == REGNO (operands[4])
10529 && peep2_reg_dead_p (2, operands[0])"
10530 [(set (match_dup 3)
10531 (mem:HI (plus:SI (match_dup 1) (match_dup 2))))]
10535 ;; mov b,c -> extu.bw a,c
10537 [(set (match_operand:SI 0 "arith_reg_dest")
10538 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand")))
10539 (set (match_operand:SI 2 "arith_reg_dest")
10541 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10542 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))])
10545 ;; extu.bw r1,r1 -> extu.bw r0,r1
10547 [(set (match_operand 0 "arith_reg_dest")
10548 (match_operand 1 "arith_reg_operand"))
10549 (set (match_operand:SI 2 "arith_reg_dest")
10550 (zero_extend:SI (match_operand:QIHI 3 "arith_reg_operand")))]
10552 && REGNO (operands[0]) == REGNO (operands[3])
10553 && (REGNO (operands[0]) == REGNO (operands[2])
10554 || peep2_reg_dead_p (2, operands[0]))"
10555 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))]
10557 operands[1] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));
10561 ;; mov b,a -> < nop >
10563 [(set (match_operand 0 "register_operand")
10564 (match_operand 1 "register_operand"))
10565 (set (match_operand 2 "register_operand")
10566 (match_operand 3 "register_operand"))]
10568 && REGNO (operands[0]) == REGNO (operands[3])
10569 && REGNO (operands[1]) == REGNO (operands[2])
10570 && peep2_reg_dead_p (2, operands[3])"
10574 ;; and r4,r1 -> mov r1,r0
10575 ;; mov r1,r0 and #3,r0
10576 (define_code_iterator ANDIORXOR [and ior xor])
10578 [(set (match_operand:SI 0 "register_operand")
10579 (match_operand:SI 1 "const_logical_operand"))
10580 (set (match_operand:SI 2) (ANDIORXOR:SI (match_dup 2) (match_dup 0)))
10581 (set (reg:SI R0_REG) (match_dup 2))]
10583 && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[2])"
10584 [(set (reg:SI R0_REG) (match_dup 2))
10585 (set (reg:SI R0_REG) (ANDIORXOR:SI (reg:SI R0_REG) (match_dup 1)))])
10587 ;; ... r2,r0 ... r2,r0
10588 ;; or r1,r0 -> or r0,r1
10591 (define_code_iterator ANDIORXORPLUS [and ior xor plus])
10593 [(set (match_operand:SI 0 "arith_reg_dest")
10594 (ANDIORXORPLUS:SI (match_dup 0) (match_operand:SI 1 "arith_reg_dest")))
10595 (set (match_dup 1) (match_dup 0))]
10596 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10597 [(set (match_dup 1) (ANDIORXORPLUS:SI (match_dup 1) (match_dup 0)))])
10600 ;; add #-48,r0 -> add #-48,r12
10601 ;; mov.l r0,@(4,r10) mov.l r12,@(4,r10)
10604 [(set (match_operand:SI 0 "arith_reg_dest")
10605 (match_operand:SI 1 "arith_reg_dest"))
10606 (set (match_dup 0) (plus:SI (match_dup 0)
10607 (match_operand:SI 2 "const_int_operand")))
10608 (set (match_operand:SI 3 "general_movdst_operand") (match_dup 0))]
10610 && peep2_reg_dead_p (2, operands[1]) && peep2_reg_dead_p (3, operands[0])"
10613 emit_insn (gen_addsi3 (operands[1], operands[1], operands[2]));
10614 sh_peephole_emit_move_insn (operands[3], operands[1]);
10617 ;; mov.l @(r0,r9),r1
10618 ;; mov r1,r0 -> mov @(r0,r9),r0
10620 [(set (match_operand:SI 0 "arith_reg_dest")
10621 (match_operand:SI 1 "general_movsrc_operand"))
10622 (set (match_operand:SI 2 "arith_reg_dest")
10624 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10627 sh_peephole_emit_move_insn (operands[2], operands[1]);
10631 [(set (match_operand:QIHI 0 "register_operand")
10632 (match_operand:QIHI 1 "movsrc_no_disp_mem_operand"))
10633 (set (match_operand:QIHI 2 "register_operand")
10635 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10638 sh_peephole_emit_move_insn (operands[2], operands[1]);
10642 [(set (match_operand:SI 0 "arith_reg_dest")
10643 (sign_extend:SI (match_operand:QIHI 1 "movsrc_no_disp_mem_operand")))
10644 (set (match_operand:SI 2 "arith_reg_dest")
10646 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10649 sh_check_add_incdec_notes (emit_insn (gen_extend<mode>si2 (operands[2],
10650 sh_remove_overlapping_post_inc (operands[2], operands[1]))));
10653 ;; mov.w @(18,r1),r0 (r0 = HImode)
10654 ;; mov r0,r1 (r0 = r1 = HImode) mov.w @(18,r1),r0
10655 ;; ... ..,r13 (r13 = SImode) -> ... ..,r13
10656 ;; tst r1,r13 tst r0,r13
10658 [(set (match_operand 0 "arith_reg_dest")
10659 (match_operand 1 "arith_reg_dest"))
10660 (set (match_operand:SI 2 "arith_reg_dest")
10661 (match_operand:SI 3))
10662 (set (reg:SI T_REG)
10663 (eq:SI (and:SI (match_operand:SI 4 "arith_reg_operand")
10664 (match_operand:SI 5 "arith_reg_operand"))
10667 && peep2_reg_dead_p (3, operands[0])
10668 && !reg_overlap_mentioned_p (operands[0], operands[3])
10669 && (REGNO (operands[0]) == REGNO (operands[4])
10670 || REGNO (operands[0]) == REGNO (operands[5]))
10671 && (REGNO (operands[2]) == REGNO (operands[4])
10672 || REGNO (operands[2]) == REGNO (operands[5]))"
10675 if (REGNO (operands[1]) == REGNO (operands[2]))
10676 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));
10678 // We don't know what the new set insn will be in detail. Just make sure
10679 // that it still can be recognized and the constraints are satisfied.
10680 rtx_insn* i = emit_insn (gen_rtx_SET (operands[2],
10681 sh_remove_overlapping_post_inc (operands[2], operands[3])));
10683 recog_data_d prev_recog_data = recog_data;
10684 bool i_invalid = insn_invalid_p (i, false);
10685 recog_data = prev_recog_data;
10690 sh_check_add_incdec_notes (i);
10692 emit_insn (gen_tstsi_t (operands[2],
10693 gen_rtx_REG (SImode, (REGNO (operands[1])))));
10696 ;; mov.w @(18,r1),r0 (r0 = HImode)
10697 ;; ... ..,r13 (r13 = SImode) mov.w @(18,r1),r0
10698 ;; mov r0,r1 (r0 = r1 = HImode) -> ... ..,r13
10699 ;; tst r1,r13 tst r0,r13
10701 [(set (match_operand:SI 2 "arith_reg_dest")
10702 (match_operand:SI 3))
10703 (set (match_operand 0 "arith_reg_dest")
10704 (match_operand 1 "arith_reg_operand"))
10705 (set (reg:SI T_REG)
10706 (eq:SI (and:SI (match_operand:SI 4 "arith_reg_operand")
10707 (match_operand:SI 5 "arith_reg_operand"))
10710 && peep2_reg_dead_p (3, operands[0])
10711 && !reg_overlap_mentioned_p (operands[0], operands[3])
10712 && (REGNO (operands[0]) == REGNO (operands[4])
10713 || REGNO (operands[0]) == REGNO (operands[5]))
10714 && (REGNO (operands[2]) == REGNO (operands[4])
10715 || REGNO (operands[2]) == REGNO (operands[5]))"
10718 // We don't know what the new set insn will be in detail. Just make sure
10719 // that it still can be recognized and the constraints are satisfied.
10720 rtx_insn* i = emit_insn (gen_rtx_SET (operands[2],
10721 sh_remove_overlapping_post_inc (operands[2], operands[3])));
10723 recog_data_d prev_recog_data = recog_data;
10724 bool i_invalid = insn_invalid_p (i, false);
10725 recog_data = prev_recog_data;
10730 sh_check_add_incdec_notes (i);
10732 emit_insn (gen_tstsi_t (operands[2],
10733 gen_rtx_REG (SImode, (REGNO (operands[1])))));
10736 ;; This is not a peephole, but it's here because it's actually supposed
10737 ;; to be one. It tries to convert a sequence such as
10738 ;; movt r2 -> movt r2
10739 ;; movt r13 mov r2,r13
10740 ;; This gives the schduler a bit more freedom to hoist a following
10741 ;; comparison insn. Moreover, it the reg-reg mov insn is MT group which has
10742 ;; better chances for parallel execution.
10743 ;; We can do this with a peephole2 pattern, but then the cprop_hardreg
10744 ;; pass will revert the change. See also PR 64331.
10745 ;; Thus do it manually in one of the split passes after register allocation.
10746 ;; Sometimes the cprop_hardreg pass might also eliminate the reg-reg copy.
10748 [(set (match_operand:SI 0 "arith_reg_dest")
10749 (match_operand:SI 1 "t_reg_operand"))]
10750 "TARGET_SH1 && reload_completed"
10751 [(set (match_dup 0) (match_dup 1))]
10753 rtx t_reg = get_t_reg_rtx ();
10755 for (rtx_insn* i = prev_nonnote_insn_bb (curr_insn); i != NULL;
10756 i = prev_nonnote_insn_bb (i))
10758 if (!INSN_P (i) || DEBUG_INSN_P (i))
10761 if (modified_in_p (t_reg, i) || BARRIER_P (i))
10764 if (sh_is_movt_insn (i))
10766 rtx r = sh_movt_set_dest (i);
10767 if (!modified_between_p (r, i, curr_insn))
10777 [(set (match_operand:SI 0 "register_operand" "=r")
10778 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
10779 (set (mem:SF (match_dup 0))
10780 (match_operand:SF 2 "general_movsrc_operand" ""))]
10781 "TARGET_SH1 && REGNO (operands[0]) == 0
10782 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
10783 || (GET_CODE (operands[2]) == SUBREG
10784 && REGNO (SUBREG_REG (operands[2])) < 16))
10785 && reg_unused_after (operands[0], insn)"
10786 "mov.l %2,@(%0,%1)")
10789 [(set (match_operand:SI 0 "register_operand" "=r")
10790 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
10791 (set (match_operand:SF 2 "general_movdst_operand" "")
10793 (mem:SF (match_dup 0)))]
10794 "TARGET_SH1 && REGNO (operands[0]) == 0
10795 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
10796 || (GET_CODE (operands[2]) == SUBREG
10797 && REGNO (SUBREG_REG (operands[2])) < 16))
10798 && reg_unused_after (operands[0], insn)"
10799 "mov.l @(%0,%1),%2")
10802 [(set (match_operand:SI 0 "register_operand" "=r")
10803 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
10804 (set (mem:SF (match_dup 0))
10805 (match_operand:SF 2 "general_movsrc_operand" ""))]
10806 "TARGET_SH2E && REGNO (operands[0]) == 0
10807 && ((REG_P (operands[2])
10808 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
10809 || (GET_CODE (operands[2]) == SUBREG
10810 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
10811 && reg_unused_after (operands[0], insn)"
10812 "fmov{.s|} %2,@(%0,%1)")
10815 [(set (match_operand:SI 0 "register_operand" "=r")
10816 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
10817 (set (match_operand:SF 2 "general_movdst_operand" "")
10819 (mem:SF (match_dup 0)))]
10820 "TARGET_SH2E && REGNO (operands[0]) == 0
10821 && ((REG_P (operands[2])
10822 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
10823 || (GET_CODE (operands[2]) == SUBREG
10824 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
10825 && reg_unused_after (operands[0], insn)"
10826 "fmov{.s|} @(%0,%1),%2")
10828 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF).
10829 (define_insn "sp_switch_1"
10830 [(set (reg:SI SP_REG) (unspec_volatile [(match_operand:SI 0 "" "")]
10831 UNSPECV_SP_SWITCH_B))]
10834 return "mov.l r0,@-r15" "\n"
10835 " mov.l %0,r0" "\n"
10836 " mov.l @r0,r0" "\n"
10837 " mov.l r15,@-r0" "\n"
10840 [(set_attr "length" "10")])
10842 ;; Switch back to the original stack for interrupt functions with the
10843 ;; sp_switch attribute.
10844 (define_insn "sp_switch_2"
10845 [(unspec_volatile [(const_int 0)]
10846 UNSPECV_SP_SWITCH_E)]
10849 return "mov.l @r15,r15" "\n"
10852 [(set_attr "length" "4")])
10855 ;; In user mode, the "pref" instruction will raise a RADDERR exception
10856 ;; for accesses to [0x80000000,0xffffffff]. This makes it an unsuitable
10857 ;; implementation of __builtin_prefetch for VxWorks RTPs.
10858 (define_expand "prefetch"
10859 [(prefetch (match_operand 0 "address_operand" "")
10860 (match_operand:SI 1 "const_int_operand" "")
10861 (match_operand:SI 2 "const_int_operand" ""))]
10862 "(TARGET_SH2A || TARGET_SH3) && !TARGET_VXWORKS_RTP")
10864 (define_insn "*prefetch"
10865 [(prefetch (match_operand:SI 0 "register_operand" "r")
10866 (match_operand:SI 1 "const_int_operand" "n")
10867 (match_operand:SI 2 "const_int_operand" "n"))]
10868 "(TARGET_SH2A || TARGET_SH3) && ! TARGET_VXWORKS_RTP"
10870 [(set_attr "type" "other")])
10872 ;; -------------------------------------------------------------------------
10873 ;; Stack Protector Patterns
10874 ;; -------------------------------------------------------------------------
10876 (define_expand "stack_protect_set"
10877 [(set (match_operand 0 "memory_operand" "")
10878 (match_operand 1 "memory_operand" ""))]
10881 emit_insn (gen_stack_protect_set_si (operands[0], operands[1]));
10885 (define_insn "stack_protect_set_si"
10886 [(set (match_operand:SI 0 "memory_operand" "=m")
10887 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
10888 (set (match_scratch:SI 2 "=&r") (const_int 0))]
10891 return "mov.l %1,%2" "\n"
10892 " mov.l %2,%0" "\n"
10895 [(set_attr "type" "other")
10896 (set_attr "length" "6")])
10898 (define_expand "stack_protect_test"
10899 [(match_operand 0 "memory_operand" "")
10900 (match_operand 1 "memory_operand" "")
10901 (match_operand 2 "" "")]
10904 emit_insn (gen_stack_protect_test_si (operands[0], operands[1]));
10905 emit_jump_insn (gen_branch_true (operands[2]));
10909 (define_insn "stack_protect_test_si"
10910 [(set (reg:SI T_REG)
10911 (unspec:SI [(match_operand:SI 0 "memory_operand" "m")
10912 (match_operand:SI 1 "memory_operand" "m")]
10914 (set (match_scratch:SI 2 "=&r") (const_int 0))
10915 (set (match_scratch:SI 3 "=&r") (const_int 0))]
10918 return "mov.l %0,%2" "\n"
10919 " mov.l %1,%3" "\n"
10920 " cmp/eq %2,%3" "\n"
10924 [(set_attr "type" "other")
10925 (set_attr "length" "10")])
10927 ;; -------------------------------------------------------------------------
10928 ;; Atomic operations
10929 ;; -------------------------------------------------------------------------
10931 (include "sync.md")