| blob | 10b915d7748eec477ab20b1db4628a82d2eb648a |
1 ;; ??? This file needs auditing for thumb2
2 ;; Patterns for the Intel Wireless MMX technology architecture.
3 ;; Copyright (C) 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
4 ;; Contributed by Red Hat.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it under
9 ;; the terms of the GNU General Public License as published by the Free
10 ;; Software Foundation; either version 2, or (at your option) any later
11 ;; version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 ;; Boston, MA 02110-1301, USA.
23 (define_insn "iwmmxt_iordi3"
24 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r")
25 (ior:DI (match_operand:DI 1 "register_operand" "%y,0,r")
26 (match_operand:DI 2 "register_operand" "y,r,r")))]
27 "TARGET_REALLY_IWMMXT"
28 "@
29 wor%?\\t%0, %1, %2
30 #
31 #"
32 [(set_attr "predicable" "yes")
33 (set_attr "length" "4,8,8")])
35 (define_insn "iwmmxt_xordi3"
36 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r")
37 (xor:DI (match_operand:DI 1 "register_operand" "%y,0,r")
38 (match_operand:DI 2 "register_operand" "y,r,r")))]
39 "TARGET_REALLY_IWMMXT"
40 "@
41 wxor%?\\t%0, %1, %2
42 #
43 #"
44 [(set_attr "predicable" "yes")
45 (set_attr "length" "4,8,8")])
47 (define_insn "iwmmxt_anddi3"
48 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r")
49 (and:DI (match_operand:DI 1 "register_operand" "%y,0,r")
50 (match_operand:DI 2 "register_operand" "y,r,r")))]
51 "TARGET_REALLY_IWMMXT"
52 "@
53 wand%?\\t%0, %1, %2
54 #
55 #"
56 [(set_attr "predicable" "yes")
57 (set_attr "length" "4,8,8")])
59 (define_insn "iwmmxt_nanddi3"
60 [(set (match_operand:DI 0 "register_operand" "=y")
61 (and:DI (match_operand:DI 1 "register_operand" "y")
62 (not:DI (match_operand:DI 2 "register_operand" "y"))))]
63 "TARGET_REALLY_IWMMXT"
64 "wandn%?\\t%0, %1, %2"
65 [(set_attr "predicable" "yes")])
67 (define_insn "*iwmmxt_arm_movdi"
68 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, m,y,y,yr,y,yrUy")
69 (match_operand:DI 1 "di_operand" "rIK,mi,r,y,yr,y,yrUy,y"))]
70 "TARGET_REALLY_IWMMXT
71 && ( register_operand (operands[0], DImode)
72 || register_operand (operands[1], DImode))"
73 "*
74 {
75 switch (which_alternative)
76 {
77 default:
78 return output_move_double (operands);
79 case 0:
80 return \"#\";
81 case 3:
82 return \"wmov%?\\t%0,%1\";
83 case 4:
84 return \"tmcrr%?\\t%0,%Q1,%R1\";
85 case 5:
86 return \"tmrrc%?\\t%Q0,%R0,%1\";
87 case 6:
88 return \"wldrd%?\\t%0,%1\";
89 case 7:
90 return \"wstrd%?\\t%1,%0\";
91 }
92 }"
93 [(set_attr "length" "8,8,8,4,4,4,4,4")
94 (set_attr "type" "*,load1,store2,*,*,*,*,*")
95 (set_attr "pool_range" "*,1020,*,*,*,*,*,*")
96 (set_attr "neg_pool_range" "*,1012,*,*,*,*,*,*")]
97 )
99 (define_insn "*iwmmxt_movsi_insn"
100 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r,?z,Uy,z")
101 (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z,Uy,z,z"))]
102 "TARGET_REALLY_IWMMXT
103 && ( register_operand (operands[0], SImode)
104 || register_operand (operands[1], SImode))"
105 "*
106 switch (which_alternative)
107 {
108 case 0: return \"mov\\t%0, %1\";
109 case 1: return \"mvn\\t%0, #%B1\";
110 case 2: return \"ldr\\t%0, %1\";
111 case 3: return \"str\\t%1, %0\";
112 case 4: return \"tmcr\\t%0, %1\";
113 case 5: return \"tmrc\\t%0, %1\";
114 case 6: return arm_output_load_gr (operands);
115 case 7: return \"wstrw\\t%1, %0\";
116 default:return \"wstrw\\t%1, [sp, #-4]!\;wldrw\\t%0, [sp], #4\\t@move CG reg\";
117 }"
118 [(set_attr "type" "*,*,load1,store1,*,*,load1,store1,*")
119 (set_attr "length" "*,*,*, *,*,*, 16, *,8")
120 (set_attr "pool_range" "*,*,4096, *,*,*,1024, *,*")
121 (set_attr "neg_pool_range" "*,*,4084, *,*,*, *, 1012,*")
122 ;; Note - the "predicable" attribute is not allowed to have alternatives.
123 ;; Since the wSTRw wCx instruction is not predicable, we cannot support
124 ;; predicating any of the alternatives in this template. Instead,
125 ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn.
126 (set_attr "predicable" "no")
127 ;; Also - we have to pretend that these insns clobber the condition code
128 ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize
129 ;; them.
130 (set_attr "conds" "clob")]
131 )
133 ;; Because iwmmxt_movsi_insn is not predicable, we provide the
134 ;; cond_exec version explicitly, with appropriate constraints.
136 (define_insn "*cond_iwmmxt_movsi_insn"
137 [(cond_exec
138 (match_operator 2 "arm_comparison_operator"
139 [(match_operand 3 "cc_register" "")
140 (const_int 0)])
141 (set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r")
142 (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z")))]
143 "TARGET_REALLY_IWMMXT
144 && ( register_operand (operands[0], SImode)
145 || register_operand (operands[1], SImode))"
146 "*
147 switch (which_alternative)
148 {
149 case 0: return \"mov%?\\t%0, %1\";
150 case 1: return \"mvn%?\\t%0, #%B1\";
151 case 2: return \"ldr%?\\t%0, %1\";
152 case 3: return \"str%?\\t%1, %0\";
153 case 4: return \"tmcr%?\\t%0, %1\";
154 default: return \"tmrc%?\\t%0, %1\";
155 }"
156 [(set_attr "type" "*,*,load1,store1,*,*")
157 (set_attr "pool_range" "*,*,4096, *,*,*")
158 (set_attr "neg_pool_range" "*,*,4084, *,*,*")]
159 )
161 (define_insn "movv8qi_internal"
162 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r,?r")
163 (match_operand:V8QI 1 "general_operand" "y,y,mi,y,r,r,mi"))]
164 "TARGET_REALLY_IWMMXT"
165 "*
166 switch (which_alternative)
167 {
168 case 0: return \"wmov%?\\t%0, %1\";
169 case 1: return \"wstrd%?\\t%1, %0\";
170 case 2: return \"wldrd%?\\t%0, %1\";
171 case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
172 case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
173 case 5: return \"#\";
174 default: return output_move_double (operands);
175 }"
176 [(set_attr "predicable" "yes")
177 (set_attr "length" "4, 4, 4,4,4,8, 8")
178 (set_attr "type" "*,store1,load1,*,*,*,load1")
179 (set_attr "pool_range" "*, *, 256,*,*,*, 256")
180 (set_attr "neg_pool_range" "*, *, 244,*,*,*, 244")])
182 (define_insn "movv4hi_internal"
183 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r,?r")
184 (match_operand:V4HI 1 "general_operand" "y,y,mi,y,r,r,mi"))]
185 "TARGET_REALLY_IWMMXT"
186 "*
187 switch (which_alternative)
188 {
189 case 0: return \"wmov%?\\t%0, %1\";
190 case 1: return \"wstrd%?\\t%1, %0\";
191 case 2: return \"wldrd%?\\t%0, %1\";
192 case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
193 case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
194 case 5: return \"#\";
195 default: return output_move_double (operands);
196 }"
197 [(set_attr "predicable" "yes")
198 (set_attr "length" "4, 4, 4,4,4,8, 8")
199 (set_attr "type" "*,store1,load1,*,*,*,load1")
200 (set_attr "pool_range" "*, *, 256,*,*,*, 256")
201 (set_attr "neg_pool_range" "*, *, 244,*,*,*, 244")])
203 (define_insn "movv2si_internal"
204 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r,?r")
205 (match_operand:V2SI 1 "general_operand" "y,y,mi,y,r,r,mi"))]
206 "TARGET_REALLY_IWMMXT"
207 "*
208 switch (which_alternative)
209 {
210 case 0: return \"wmov%?\\t%0, %1\";
211 case 1: return \"wstrd%?\\t%1, %0\";
212 case 2: return \"wldrd%?\\t%0, %1\";
213 case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
214 case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
215 case 5: return \"#\";
216 default: return output_move_double (operands);
217 }"
218 [(set_attr "predicable" "yes")
219 (set_attr "length" "4, 4, 4,4,4,8, 24")
220 (set_attr "type" "*,store1,load1,*,*,*,load1")
221 (set_attr "pool_range" "*, *, 256,*,*,*, 256")
222 (set_attr "neg_pool_range" "*, *, 244,*,*,*, 244")])
224 ;; This pattern should not be needed. It is to match a
225 ;; wierd case generated by GCC when no optimizations are
226 ;; enabled. (Try compiling gcc/testsuite/gcc.c-torture/
227 ;; compile/simd-5.c at -O0). The mode for operands[1] is
228 ;; deliberately omitted.
229 (define_insn "movv2si_internal_2"
230 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=?r")
231 (match_operand 1 "immediate_operand" "mi"))]
232 "TARGET_REALLY_IWMMXT"
233 "* return output_move_double (operands);"
234 [(set_attr "predicable" "yes")
235 (set_attr "length" "8")
236 (set_attr "type" "load1")
237 (set_attr "pool_range" "256")
238 (set_attr "neg_pool_range" "244")])
240 ;; Vector add/subtract
242 (define_insn "addv8qi3"
243 [(set (match_operand:V8QI 0 "register_operand" "=y")
244 (plus:V8QI (match_operand:V8QI 1 "register_operand" "y")
245 (match_operand:V8QI 2 "register_operand" "y")))]
246 "TARGET_REALLY_IWMMXT"
247 "waddb%?\\t%0, %1, %2"
248 [(set_attr "predicable" "yes")])
250 (define_insn "addv4hi3"
251 [(set (match_operand:V4HI 0 "register_operand" "=y")
252 (plus:V4HI (match_operand:V4HI 1 "register_operand" "y")
253 (match_operand:V4HI 2 "register_operand" "y")))]
254 "TARGET_REALLY_IWMMXT"
255 "waddh%?\\t%0, %1, %2"
256 [(set_attr "predicable" "yes")])
258 (define_insn "addv2si3"
259 [(set (match_operand:V2SI 0 "register_operand" "=y")
260 (plus:V2SI (match_operand:V2SI 1 "register_operand" "y")
261 (match_operand:V2SI 2 "register_operand" "y")))]
262 "TARGET_REALLY_IWMMXT"
263 "waddw%?\\t%0, %1, %2"
264 [(set_attr "predicable" "yes")])
266 (define_insn "ssaddv8qi3"
267 [(set (match_operand:V8QI 0 "register_operand" "=y")
268 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "y")
269 (match_operand:V8QI 2 "register_operand" "y")))]
270 "TARGET_REALLY_IWMMXT"
271 "waddbss%?\\t%0, %1, %2"
272 [(set_attr "predicable" "yes")])
274 (define_insn "ssaddv4hi3"
275 [(set (match_operand:V4HI 0 "register_operand" "=y")
276 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "y")
277 (match_operand:V4HI 2 "register_operand" "y")))]
278 "TARGET_REALLY_IWMMXT"
279 "waddhss%?\\t%0, %1, %2"
280 [(set_attr "predicable" "yes")])
282 (define_insn "ssaddv2si3"
283 [(set (match_operand:V2SI 0 "register_operand" "=y")
284 (ss_plus:V2SI (match_operand:V2SI 1 "register_operand" "y")
285 (match_operand:V2SI 2 "register_operand" "y")))]
286 "TARGET_REALLY_IWMMXT"
287 "waddwss%?\\t%0, %1, %2"
288 [(set_attr "predicable" "yes")])
290 (define_insn "usaddv8qi3"
291 [(set (match_operand:V8QI 0 "register_operand" "=y")
292 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "y")
293 (match_operand:V8QI 2 "register_operand" "y")))]
294 "TARGET_REALLY_IWMMXT"
295 "waddbus%?\\t%0, %1, %2"
296 [(set_attr "predicable" "yes")])
298 (define_insn "usaddv4hi3"
299 [(set (match_operand:V4HI 0 "register_operand" "=y")
300 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "y")
301 (match_operand:V4HI 2 "register_operand" "y")))]
302 "TARGET_REALLY_IWMMXT"
303 "waddhus%?\\t%0, %1, %2"
304 [(set_attr "predicable" "yes")])
306 (define_insn "usaddv2si3"
307 [(set (match_operand:V2SI 0 "register_operand" "=y")
308 (us_plus:V2SI (match_operand:V2SI 1 "register_operand" "y")
309 (match_operand:V2SI 2 "register_operand" "y")))]
310 "TARGET_REALLY_IWMMXT"
311 "waddwus%?\\t%0, %1, %2"
312 [(set_attr "predicable" "yes")])
314 (define_insn "subv8qi3"
315 [(set (match_operand:V8QI 0 "register_operand" "=y")
316 (minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
317 (match_operand:V8QI 2 "register_operand" "y")))]
318 "TARGET_REALLY_IWMMXT"
319 "wsubb%?\\t%0, %1, %2"
320 [(set_attr "predicable" "yes")])
322 (define_insn "subv4hi3"
323 [(set (match_operand:V4HI 0 "register_operand" "=y")
324 (minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
325 (match_operand:V4HI 2 "register_operand" "y")))]
326 "TARGET_REALLY_IWMMXT"
327 "wsubh%?\\t%0, %1, %2"
328 [(set_attr "predicable" "yes")])
330 (define_insn "subv2si3"
331 [(set (match_operand:V2SI 0 "register_operand" "=y")
332 (minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
333 (match_operand:V2SI 2 "register_operand" "y")))]
334 "TARGET_REALLY_IWMMXT"
335 "wsubw%?\\t%0, %1, %2"
336 [(set_attr "predicable" "yes")])
338 (define_insn "sssubv8qi3"
339 [(set (match_operand:V8QI 0 "register_operand" "=y")
340 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
341 (match_operand:V8QI 2 "register_operand" "y")))]
342 "TARGET_REALLY_IWMMXT"
343 "wsubbss%?\\t%0, %1, %2"
344 [(set_attr "predicable" "yes")])
346 (define_insn "sssubv4hi3"
347 [(set (match_operand:V4HI 0 "register_operand" "=y")
348 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
349 (match_operand:V4HI 2 "register_operand" "y")))]
350 "TARGET_REALLY_IWMMXT"
351 "wsubhss%?\\t%0, %1, %2"
352 [(set_attr "predicable" "yes")])
354 (define_insn "sssubv2si3"
355 [(set (match_operand:V2SI 0 "register_operand" "=y")
356 (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
357 (match_operand:V2SI 2 "register_operand" "y")))]
358 "TARGET_REALLY_IWMMXT"
359 "wsubwss%?\\t%0, %1, %2"
360 [(set_attr "predicable" "yes")])
362 (define_insn "ussubv8qi3"
363 [(set (match_operand:V8QI 0 "register_operand" "=y")
364 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
365 (match_operand:V8QI 2 "register_operand" "y")))]
366 "TARGET_REALLY_IWMMXT"
367 "wsubbus%?\\t%0, %1, %2"
368 [(set_attr "predicable" "yes")])
370 (define_insn "ussubv4hi3"
371 [(set (match_operand:V4HI 0 "register_operand" "=y")
372 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
373 (match_operand:V4HI 2 "register_operand" "y")))]
374 "TARGET_REALLY_IWMMXT"
375 "wsubhus%?\\t%0, %1, %2"
376 [(set_attr "predicable" "yes")])
378 (define_insn "ussubv2si3"
379 [(set (match_operand:V2SI 0 "register_operand" "=y")
380 (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
381 (match_operand:V2SI 2 "register_operand" "y")))]
382 "TARGET_REALLY_IWMMXT"
383 "wsubwus%?\\t%0, %1, %2"
384 [(set_attr "predicable" "yes")])
386 (define_insn "mulv4hi3"
387 [(set (match_operand:V4HI 0 "register_operand" "=y")
388 (mult:V4HI (match_operand:V4HI 1 "register_operand" "y")
389 (match_operand:V4HI 2 "register_operand" "y")))]
390 "TARGET_REALLY_IWMMXT"
391 "wmulul%?\\t%0, %1, %2"
392 [(set_attr "predicable" "yes")])
394 (define_insn "smulv4hi3_highpart"
395 [(set (match_operand:V4HI 0 "register_operand" "=y")
396 (truncate:V4HI
397 (lshiftrt:V4SI
398 (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
399 (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
400 (const_int 16))))]
401 "TARGET_REALLY_IWMMXT"
402 "wmulsm%?\\t%0, %1, %2"
403 [(set_attr "predicable" "yes")])
405 (define_insn "umulv4hi3_highpart"
406 [(set (match_operand:V4HI 0 "register_operand" "=y")
407 (truncate:V4HI
408 (lshiftrt:V4SI
409 (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
410 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
411 (const_int 16))))]
412 "TARGET_REALLY_IWMMXT"
413 "wmulum%?\\t%0, %1, %2"
414 [(set_attr "predicable" "yes")])
416 (define_insn "iwmmxt_wmacs"
417 [(set (match_operand:DI 0 "register_operand" "=y")
418 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
419 (match_operand:V4HI 2 "register_operand" "y")
420 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))]
421 "TARGET_REALLY_IWMMXT"
422 "wmacs%?\\t%0, %2, %3"
423 [(set_attr "predicable" "yes")])
425 (define_insn "iwmmxt_wmacsz"
426 [(set (match_operand:DI 0 "register_operand" "=y")
427 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
428 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))]
429 "TARGET_REALLY_IWMMXT"
430 "wmacsz%?\\t%0, %1, %2"
431 [(set_attr "predicable" "yes")])
433 (define_insn "iwmmxt_wmacu"
434 [(set (match_operand:DI 0 "register_operand" "=y")
435 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
436 (match_operand:V4HI 2 "register_operand" "y")
437 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))]
438 "TARGET_REALLY_IWMMXT"
439 "wmacu%?\\t%0, %2, %3"
440 [(set_attr "predicable" "yes")])
442 (define_insn "iwmmxt_wmacuz"
443 [(set (match_operand:DI 0 "register_operand" "=y")
444 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
445 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))]
446 "TARGET_REALLY_IWMMXT"
447 "wmacuz%?\\t%0, %1, %2"
448 [(set_attr "predicable" "yes")])
450 ;; Same as xordi3, but don't show input operands so that we don't think
451 ;; they are live.
452 (define_insn "iwmmxt_clrdi"
453 [(set (match_operand:DI 0 "register_operand" "=y")
454 (unspec:DI [(const_int 0)] UNSPEC_CLRDI))]
455 "TARGET_REALLY_IWMMXT"
456 "wxor%?\\t%0, %0, %0"
457 [(set_attr "predicable" "yes")])
459 ;; Seems like cse likes to generate these, so we have to support them.
461 (define_insn "*iwmmxt_clrv8qi"
462 [(set (match_operand:V8QI 0 "register_operand" "=y")
463 (const_vector:V8QI [(const_int 0) (const_int 0)
464 (const_int 0) (const_int 0)
465 (const_int 0) (const_int 0)
466 (const_int 0) (const_int 0)]))]
467 "TARGET_REALLY_IWMMXT"
468 "wxor%?\\t%0, %0, %0"
469 [(set_attr "predicable" "yes")])
471 (define_insn "*iwmmxt_clrv4hi"
472 [(set (match_operand:V4HI 0 "register_operand" "=y")
473 (const_vector:V4HI [(const_int 0) (const_int 0)
474 (const_int 0) (const_int 0)]))]
475 "TARGET_REALLY_IWMMXT"
476 "wxor%?\\t%0, %0, %0"
477 [(set_attr "predicable" "yes")])
479 (define_insn "*iwmmxt_clrv2si"
480 [(set (match_operand:V2SI 0 "register_operand" "=y")
481 (const_vector:V2SI [(const_int 0) (const_int 0)]))]
482 "TARGET_REALLY_IWMMXT"
483 "wxor%?\\t%0, %0, %0"
484 [(set_attr "predicable" "yes")])
486 ;; Unsigned averages/sum of absolute differences
488 (define_insn "iwmmxt_uavgrndv8qi3"
489 [(set (match_operand:V8QI 0 "register_operand" "=y")
490 (ashiftrt:V8QI
491 (plus:V8QI (plus:V8QI
492 (match_operand:V8QI 1 "register_operand" "y")
493 (match_operand:V8QI 2 "register_operand" "y"))
494 (const_vector:V8QI [(const_int 1)
495 (const_int 1)
496 (const_int 1)
497 (const_int 1)
498 (const_int 1)
499 (const_int 1)
500 (const_int 1)
501 (const_int 1)]))
502 (const_int 1)))]
503 "TARGET_REALLY_IWMMXT"
504 "wavg2br%?\\t%0, %1, %2"
505 [(set_attr "predicable" "yes")])
507 (define_insn "iwmmxt_uavgrndv4hi3"
508 [(set (match_operand:V4HI 0 "register_operand" "=y")
509 (ashiftrt:V4HI
510 (plus:V4HI (plus:V4HI
511 (match_operand:V4HI 1 "register_operand" "y")
512 (match_operand:V4HI 2 "register_operand" "y"))
513 (const_vector:V4HI [(const_int 1)
514 (const_int 1)
515 (const_int 1)
516 (const_int 1)]))
517 (const_int 1)))]
518 "TARGET_REALLY_IWMMXT"
519 "wavg2hr%?\\t%0, %1, %2"
520 [(set_attr "predicable" "yes")])
523 (define_insn "iwmmxt_uavgv8qi3"
524 [(set (match_operand:V8QI 0 "register_operand" "=y")
525 (ashiftrt:V8QI (plus:V8QI
526 (match_operand:V8QI 1 "register_operand" "y")
527 (match_operand:V8QI 2 "register_operand" "y"))
528 (const_int 1)))]
529 "TARGET_REALLY_IWMMXT"
530 "wavg2b%?\\t%0, %1, %2"
531 [(set_attr "predicable" "yes")])
533 (define_insn "iwmmxt_uavgv4hi3"
534 [(set (match_operand:V4HI 0 "register_operand" "=y")
535 (ashiftrt:V4HI (plus:V4HI
536 (match_operand:V4HI 1 "register_operand" "y")
537 (match_operand:V4HI 2 "register_operand" "y"))
538 (const_int 1)))]
539 "TARGET_REALLY_IWMMXT"
540 "wavg2h%?\\t%0, %1, %2"
541 [(set_attr "predicable" "yes")])
543 (define_insn "iwmmxt_psadbw"
544 [(set (match_operand:V8QI 0 "register_operand" "=y")
545 (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
546 (match_operand:V8QI 2 "register_operand" "y"))))]
547 "TARGET_REALLY_IWMMXT"
548 "psadbw%?\\t%0, %1, %2"
549 [(set_attr "predicable" "yes")])
552 ;; Insert/extract/shuffle
554 (define_insn "iwmmxt_tinsrb"
555 [(set (match_operand:V8QI 0 "register_operand" "=y")
556 (vec_merge:V8QI (match_operand:V8QI 1 "register_operand" "0")
557 (vec_duplicate:V8QI
558 (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r")))
559 (match_operand:SI 3 "immediate_operand" "i")))]
560 "TARGET_REALLY_IWMMXT"
561 "tinsrb%?\\t%0, %2, %3"
562 [(set_attr "predicable" "yes")])
564 (define_insn "iwmmxt_tinsrh"
565 [(set (match_operand:V4HI 0 "register_operand" "=y")
566 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
567 (vec_duplicate:V4HI
568 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r")))
569 (match_operand:SI 3 "immediate_operand" "i")))]
570 "TARGET_REALLY_IWMMXT"
571 "tinsrh%?\\t%0, %2, %3"
572 [(set_attr "predicable" "yes")])
574 (define_insn "iwmmxt_tinsrw"
575 [(set (match_operand:V2SI 0 "register_operand" "=y")
576 (vec_merge:V2SI (match_operand:V2SI 1 "register_operand" "0")
577 (vec_duplicate:V2SI
578 (match_operand:SI 2 "nonimmediate_operand" "r"))
579 (match_operand:SI 3 "immediate_operand" "i")))]
580 "TARGET_REALLY_IWMMXT"
581 "tinsrw%?\\t%0, %2, %3"
582 [(set_attr "predicable" "yes")])
584 (define_insn "iwmmxt_textrmub"
585 [(set (match_operand:SI 0 "register_operand" "=r")
586 (zero_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
587 (parallel
588 [(match_operand:SI 2 "immediate_operand" "i")]))))]
589 "TARGET_REALLY_IWMMXT"
590 "textrmub%?\\t%0, %1, %2"
591 [(set_attr "predicable" "yes")])
593 (define_insn "iwmmxt_textrmsb"
594 [(set (match_operand:SI 0 "register_operand" "=r")
595 (sign_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
596 (parallel
597 [(match_operand:SI 2 "immediate_operand" "i")]))))]
598 "TARGET_REALLY_IWMMXT"
599 "textrmsb%?\\t%0, %1, %2"
600 [(set_attr "predicable" "yes")])
602 (define_insn "iwmmxt_textrmuh"
603 [(set (match_operand:SI 0 "register_operand" "=r")
604 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
605 (parallel
606 [(match_operand:SI 2 "immediate_operand" "i")]))))]
607 "TARGET_REALLY_IWMMXT"
608 "textrmuh%?\\t%0, %1, %2"
609 [(set_attr "predicable" "yes")])
611 (define_insn "iwmmxt_textrmsh"
612 [(set (match_operand:SI 0 "register_operand" "=r")
613 (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
614 (parallel
615 [(match_operand:SI 2 "immediate_operand" "i")]))))]
616 "TARGET_REALLY_IWMMXT"
617 "textrmsh%?\\t%0, %1, %2"
618 [(set_attr "predicable" "yes")])
620 ;; There are signed/unsigned variants of this instruction, but they are
621 ;; pointless.
622 (define_insn "iwmmxt_textrmw"
623 [(set (match_operand:SI 0 "register_operand" "=r")
624 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
625 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
626 "TARGET_REALLY_IWMMXT"
627 "textrmsw%?\\t%0, %1, %2"
628 [(set_attr "predicable" "yes")])
630 (define_insn "iwmmxt_wshufh"
631 [(set (match_operand:V4HI 0 "register_operand" "=y")
632 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
633 (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_WSHUFH))]
634 "TARGET_REALLY_IWMMXT"
635 "wshufh%?\\t%0, %1, %2"
636 [(set_attr "predicable" "yes")])
638 ;; Mask-generating comparisons
639 ;;
640 ;; Note - you cannot use patterns like these here:
641 ;;
642 ;; (set:<vector> (match:<vector>) (<comparator>:<vector> (match:<vector>) (match:<vector>)))
643 ;;
644 ;; Because GCC will assume that the truth value (1 or 0) is installed
645 ;; into the entire destination vector, (with the '1' going into the least
646 ;; significant element of the vector). This is not how these instructions
647 ;; behave.
648 ;;
649 ;; Unfortunately the current patterns are illegal. They are SET insns
650 ;; without a SET in them. They work in most cases for ordinary code
651 ;; generation, but there are circumstances where they can cause gcc to fail.
652 ;; XXX - FIXME.
654 (define_insn "eqv8qi3"
655 [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
656 (match_operand:V8QI 1 "register_operand" "y")
657 (match_operand:V8QI 2 "register_operand" "y")]
658 VUNSPEC_WCMP_EQ)]
659 "TARGET_REALLY_IWMMXT"
660 "wcmpeqb%?\\t%0, %1, %2"
661 [(set_attr "predicable" "yes")])
663 (define_insn "eqv4hi3"
664 [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
665 (match_operand:V4HI 1 "register_operand" "y")
666 (match_operand:V4HI 2 "register_operand" "y")]
667 VUNSPEC_WCMP_EQ)]
668 "TARGET_REALLY_IWMMXT"
669 "wcmpeqh%?\\t%0, %1, %2"
670 [(set_attr "predicable" "yes")])
672 (define_insn "eqv2si3"
673 [(unspec_volatile:V2SI [(match_operand:V2SI 0 "register_operand" "=y")
674 (match_operand:V2SI 1 "register_operand" "y")
675 (match_operand:V2SI 2 "register_operand" "y")]
676 VUNSPEC_WCMP_EQ)]
677 "TARGET_REALLY_IWMMXT"
678 "wcmpeqw%?\\t%0, %1, %2"
679 [(set_attr "predicable" "yes")])
681 (define_insn "gtuv8qi3"
682 [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
683 (match_operand:V8QI 1 "register_operand" "y")
684 (match_operand:V8QI 2 "register_operand" "y")]
685 VUNSPEC_WCMP_GTU)]
686 "TARGET_REALLY_IWMMXT"
687 "wcmpgtub%?\\t%0, %1, %2"
688 [(set_attr "predicable" "yes")])
690 (define_insn "gtuv4hi3"
691 [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
692 (match_operand:V4HI 1 "register_operand" "y")
693 (match_operand:V4HI 2 "register_operand" "y")]
694 VUNSPEC_WCMP_GTU)]
695 "TARGET_REALLY_IWMMXT"
696 "wcmpgtuh%?\\t%0, %1, %2"
697 [(set_attr "predicable" "yes")])
699 (define_insn "gtuv2si3"
700 [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y")
701 (match_operand:V2SI 1 "register_operand" "y")
702 (match_operand:V2SI 2 "register_operand" "y")]
703 VUNSPEC_WCMP_GTU)]
704 "TARGET_REALLY_IWMMXT"
705 "wcmpgtuw%?\\t%0, %1, %2"
706 [(set_attr "predicable" "yes")])
708 (define_insn "gtv8qi3"
709 [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
710 (match_operand:V8QI 1 "register_operand" "y")
711 (match_operand:V8QI 2 "register_operand" "y")]
712 VUNSPEC_WCMP_GT)]
713 "TARGET_REALLY_IWMMXT"
714 "wcmpgtsb%?\\t%0, %1, %2"
715 [(set_attr "predicable" "yes")])
717 (define_insn "gtv4hi3"
718 [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
719 (match_operand:V4HI 1 "register_operand" "y")
720 (match_operand:V4HI 2 "register_operand" "y")]
721 VUNSPEC_WCMP_GT)]
722 "TARGET_REALLY_IWMMXT"
723 "wcmpgtsh%?\\t%0, %1, %2"
724 [(set_attr "predicable" "yes")])
726 (define_insn "gtv2si3"
727 [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y")
728 (match_operand:V2SI 1 "register_operand" "y")
729 (match_operand:V2SI 2 "register_operand" "y")]
730 VUNSPEC_WCMP_GT)]
731 "TARGET_REALLY_IWMMXT"
732 "wcmpgtsw%?\\t%0, %1, %2"
733 [(set_attr "predicable" "yes")])
735 ;; Max/min insns
737 (define_insn "smaxv8qi3"
738 [(set (match_operand:V8QI 0 "register_operand" "=y")
739 (smax:V8QI (match_operand:V8QI 1 "register_operand" "y")
740 (match_operand:V8QI 2 "register_operand" "y")))]
741 "TARGET_REALLY_IWMMXT"
742 "wmaxsb%?\\t%0, %1, %2"
743 [(set_attr "predicable" "yes")])
745 (define_insn "umaxv8qi3"
746 [(set (match_operand:V8QI 0 "register_operand" "=y")
747 (umax:V8QI (match_operand:V8QI 1 "register_operand" "y")
748 (match_operand:V8QI 2 "register_operand" "y")))]
749 "TARGET_REALLY_IWMMXT"
750 "wmaxub%?\\t%0, %1, %2"
751 [(set_attr "predicable" "yes")])
753 (define_insn "smaxv4hi3"
754 [(set (match_operand:V4HI 0 "register_operand" "=y")
755 (smax:V4HI (match_operand:V4HI 1 "register_operand" "y")
756 (match_operand:V4HI 2 "register_operand" "y")))]
757 "TARGET_REALLY_IWMMXT"
758 "wmaxsh%?\\t%0, %1, %2"
759 [(set_attr "predicable" "yes")])
761 (define_insn "umaxv4hi3"
762 [(set (match_operand:V4HI 0 "register_operand" "=y")
763 (umax:V4HI (match_operand:V4HI 1 "register_operand" "y")
764 (match_operand:V4HI 2 "register_operand" "y")))]
765 "TARGET_REALLY_IWMMXT"
766 "wmaxuh%?\\t%0, %1, %2"
767 [(set_attr "predicable" "yes")])
769 (define_insn "smaxv2si3"
770 [(set (match_operand:V2SI 0 "register_operand" "=y")
771 (smax:V2SI (match_operand:V2SI 1 "register_operand" "y")
772 (match_operand:V2SI 2 "register_operand" "y")))]
773 "TARGET_REALLY_IWMMXT"
774 "wmaxsw%?\\t%0, %1, %2"
775 [(set_attr "predicable" "yes")])
777 (define_insn "umaxv2si3"
778 [(set (match_operand:V2SI 0 "register_operand" "=y")
779 (umax:V2SI (match_operand:V2SI 1 "register_operand" "y")
780 (match_operand:V2SI 2 "register_operand" "y")))]
781 "TARGET_REALLY_IWMMXT"
782 "wmaxuw%?\\t%0, %1, %2"
783 [(set_attr "predicable" "yes")])
785 (define_insn "sminv8qi3"
786 [(set (match_operand:V8QI 0 "register_operand" "=y")
787 (smin:V8QI (match_operand:V8QI 1 "register_operand" "y")
788 (match_operand:V8QI 2 "register_operand" "y")))]
789 "TARGET_REALLY_IWMMXT"
790 "wminsb%?\\t%0, %1, %2"
791 [(set_attr "predicable" "yes")])
793 (define_insn "uminv8qi3"
794 [(set (match_operand:V8QI 0 "register_operand" "=y")
795 (umin:V8QI (match_operand:V8QI 1 "register_operand" "y")
796 (match_operand:V8QI 2 "register_operand" "y")))]
797 "TARGET_REALLY_IWMMXT"
798 "wminub%?\\t%0, %1, %2"
799 [(set_attr "predicable" "yes")])
801 (define_insn "sminv4hi3"
802 [(set (match_operand:V4HI 0 "register_operand" "=y")
803 (smin:V4HI (match_operand:V4HI 1 "register_operand" "y")
804 (match_operand:V4HI 2 "register_operand" "y")))]
805 "TARGET_REALLY_IWMMXT"
806 "wminsh%?\\t%0, %1, %2"
807 [(set_attr "predicable" "yes")])
809 (define_insn "uminv4hi3"
810 [(set (match_operand:V4HI 0 "register_operand" "=y")
811 (umin:V4HI (match_operand:V4HI 1 "register_operand" "y")
812 (match_operand:V4HI 2 "register_operand" "y")))]
813 "TARGET_REALLY_IWMMXT"
814 "wminuh%?\\t%0, %1, %2"
815 [(set_attr "predicable" "yes")])
817 (define_insn "sminv2si3"
818 [(set (match_operand:V2SI 0 "register_operand" "=y")
819 (smin:V2SI (match_operand:V2SI 1 "register_operand" "y")
820 (match_operand:V2SI 2 "register_operand" "y")))]
821 "TARGET_REALLY_IWMMXT"
822 "wminsw%?\\t%0, %1, %2"
823 [(set_attr "predicable" "yes")])
825 (define_insn "uminv2si3"
826 [(set (match_operand:V2SI 0 "register_operand" "=y")
827 (umin:V2SI (match_operand:V2SI 1 "register_operand" "y")
828 (match_operand:V2SI 2 "register_operand" "y")))]
829 "TARGET_REALLY_IWMMXT"
830 "wminuw%?\\t%0, %1, %2"
831 [(set_attr "predicable" "yes")])
833 ;; Pack/unpack insns.
835 (define_insn "iwmmxt_wpackhss"
836 [(set (match_operand:V8QI 0 "register_operand" "=y")
837 (vec_concat:V8QI
838 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
839 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
840 "TARGET_REALLY_IWMMXT"
841 "wpackhss%?\\t%0, %1, %2"
842 [(set_attr "predicable" "yes")])
844 (define_insn "iwmmxt_wpackwss"
845 [(set (match_operand:V4HI 0 "register_operand" "=y")
846 (vec_concat:V4HI
847 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
848 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
849 "TARGET_REALLY_IWMMXT"
850 "wpackwss%?\\t%0, %1, %2"
851 [(set_attr "predicable" "yes")])
853 (define_insn "iwmmxt_wpackdss"
854 [(set (match_operand:V2SI 0 "register_operand" "=y")
855 (vec_concat:V2SI
856 (ss_truncate:SI (match_operand:DI 1 "register_operand" "y"))
857 (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
858 "TARGET_REALLY_IWMMXT"
859 "wpackdss%?\\t%0, %1, %2"
860 [(set_attr "predicable" "yes")])
862 (define_insn "iwmmxt_wpackhus"
863 [(set (match_operand:V8QI 0 "register_operand" "=y")
864 (vec_concat:V8QI
865 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
866 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
867 "TARGET_REALLY_IWMMXT"
868 "wpackhus%?\\t%0, %1, %2"
869 [(set_attr "predicable" "yes")])
871 (define_insn "iwmmxt_wpackwus"
872 [(set (match_operand:V4HI 0 "register_operand" "=y")
873 (vec_concat:V4HI
874 (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
875 (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
876 "TARGET_REALLY_IWMMXT"
877 "wpackwus%?\\t%0, %1, %2"
878 [(set_attr "predicable" "yes")])
880 (define_insn "iwmmxt_wpackdus"
881 [(set (match_operand:V2SI 0 "register_operand" "=y")
882 (vec_concat:V2SI
883 (us_truncate:SI (match_operand:DI 1 "register_operand" "y"))
884 (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
885 "TARGET_REALLY_IWMMXT"
886 "wpackdus%?\\t%0, %1, %2"
887 [(set_attr "predicable" "yes")])
890 (define_insn "iwmmxt_wunpckihb"
891 [(set (match_operand:V8QI 0 "register_operand" "=y")
892 (vec_merge:V8QI
893 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
894 (parallel [(const_int 4)
895 (const_int 0)
896 (const_int 5)
897 (const_int 1)
898 (const_int 6)
899 (const_int 2)
900 (const_int 7)
901 (const_int 3)]))
902 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
903 (parallel [(const_int 0)
904 (const_int 4)
905 (const_int 1)
906 (const_int 5)
907 (const_int 2)
908 (const_int 6)
909 (const_int 3)
910 (const_int 7)]))
911 (const_int 85)))]
912 "TARGET_REALLY_IWMMXT"
913 "wunpckihb%?\\t%0, %1, %2"
914 [(set_attr "predicable" "yes")])
916 (define_insn "iwmmxt_wunpckihh"
917 [(set (match_operand:V4HI 0 "register_operand" "=y")
918 (vec_merge:V4HI
919 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
920 (parallel [(const_int 0)
921 (const_int 2)
922 (const_int 1)
923 (const_int 3)]))
924 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
925 (parallel [(const_int 2)
926 (const_int 0)
927 (const_int 3)
928 (const_int 1)]))
929 (const_int 5)))]
930 "TARGET_REALLY_IWMMXT"
931 "wunpckihh%?\\t%0, %1, %2"
932 [(set_attr "predicable" "yes")])
934 (define_insn "iwmmxt_wunpckihw"
935 [(set (match_operand:V2SI 0 "register_operand" "=y")
936 (vec_merge:V2SI
937 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
938 (parallel [(const_int 0)
939 (const_int 1)]))
940 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
941 (parallel [(const_int 1)
942 (const_int 0)]))
943 (const_int 1)))]
944 "TARGET_REALLY_IWMMXT"
945 "wunpckihw%?\\t%0, %1, %2"
946 [(set_attr "predicable" "yes")])
948 (define_insn "iwmmxt_wunpckilb"
949 [(set (match_operand:V8QI 0 "register_operand" "=y")
950 (vec_merge:V8QI
951 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
952 (parallel [(const_int 0)
953 (const_int 4)
954 (const_int 1)
955 (const_int 5)
956 (const_int 2)
957 (const_int 6)
958 (const_int 3)
959 (const_int 7)]))
960 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
961 (parallel [(const_int 4)
962 (const_int 0)
963 (const_int 5)
964 (const_int 1)
965 (const_int 6)
966 (const_int 2)
967 (const_int 7)
968 (const_int 3)]))
969 (const_int 85)))]
970 "TARGET_REALLY_IWMMXT"
971 "wunpckilb%?\\t%0, %1, %2"
972 [(set_attr "predicable" "yes")])
974 (define_insn "iwmmxt_wunpckilh"
975 [(set (match_operand:V4HI 0 "register_operand" "=y")
976 (vec_merge:V4HI
977 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
978 (parallel [(const_int 2)
979 (const_int 0)
980 (const_int 3)
981 (const_int 1)]))
982 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
983 (parallel [(const_int 0)
984 (const_int 2)
985 (const_int 1)
986 (const_int 3)]))
987 (const_int 5)))]
988 "TARGET_REALLY_IWMMXT"
989 "wunpckilh%?\\t%0, %1, %2"
990 [(set_attr "predicable" "yes")])
992 (define_insn "iwmmxt_wunpckilw"
993 [(set (match_operand:V2SI 0 "register_operand" "=y")
994 (vec_merge:V2SI
995 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
996 (parallel [(const_int 1)
997 (const_int 0)]))
998 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
999 (parallel [(const_int 0)
1000 (const_int 1)]))
1001 (const_int 1)))]
1002 "TARGET_REALLY_IWMMXT"
1003 "wunpckilw%?\\t%0, %1, %2"
1004 [(set_attr "predicable" "yes")])
1006 (define_insn "iwmmxt_wunpckehub"
1007 [(set (match_operand:V4HI 0 "register_operand" "=y")
1008 (zero_extend:V4HI
1009 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
1010 (parallel [(const_int 4) (const_int 5)
1011 (const_int 6) (const_int 7)]))))]
1012 "TARGET_REALLY_IWMMXT"
1013 "wunpckehub%?\\t%0, %1"
1014 [(set_attr "predicable" "yes")])
1016 (define_insn "iwmmxt_wunpckehuh"
1017 [(set (match_operand:V2SI 0 "register_operand" "=y")
1018 (zero_extend:V2SI
1019 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
1020 (parallel [(const_int 2) (const_int 3)]))))]
1021 "TARGET_REALLY_IWMMXT"
1022 "wunpckehuh%?\\t%0, %1"
1023 [(set_attr "predicable" "yes")])
1025 (define_insn "iwmmxt_wunpckehuw"
1026 [(set (match_operand:DI 0 "register_operand" "=y")
1027 (zero_extend:DI
1028 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
1029 (parallel [(const_int 1)]))))]
1030 "TARGET_REALLY_IWMMXT"
1031 "wunpckehuw%?\\t%0, %1"
1032 [(set_attr "predicable" "yes")])
1034 (define_insn "iwmmxt_wunpckehsb"
1035 [(set (match_operand:V4HI 0 "register_operand" "=y")
1036 (sign_extend:V4HI
1037 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
1038 (parallel [(const_int 4) (const_int 5)
1039 (const_int 6) (const_int 7)]))))]
1040 "TARGET_REALLY_IWMMXT"
1041 "wunpckehsb%?\\t%0, %1"
1042 [(set_attr "predicable" "yes")])
1044 (define_insn "iwmmxt_wunpckehsh"
1045 [(set (match_operand:V2SI 0 "register_operand" "=y")
1046 (sign_extend:V2SI
1047 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
1048 (parallel [(const_int 2) (const_int 3)]))))]
1049 "TARGET_REALLY_IWMMXT"
1050 "wunpckehsh%?\\t%0, %1"
1051 [(set_attr "predicable" "yes")])
1053 (define_insn "iwmmxt_wunpckehsw"
1054 [(set (match_operand:DI 0 "register_operand" "=y")
1055 (sign_extend:DI
1056 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
1057 (parallel [(const_int 1)]))))]
1058 "TARGET_REALLY_IWMMXT"
1059 "wunpckehsw%?\\t%0, %1"
1060 [(set_attr "predicable" "yes")])
1062 (define_insn "iwmmxt_wunpckelub"
1063 [(set (match_operand:V4HI 0 "register_operand" "=y")
1064 (zero_extend:V4HI
1065 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
1066 (parallel [(const_int 0) (const_int 1)
1067 (const_int 2) (const_int 3)]))))]
1068 "TARGET_REALLY_IWMMXT"
1069 "wunpckelub%?\\t%0, %1"
1070 [(set_attr "predicable" "yes")])
1072 (define_insn "iwmmxt_wunpckeluh"
1073 [(set (match_operand:V2SI 0 "register_operand" "=y")
1074 (zero_extend:V2SI
1075 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
1076 (parallel [(const_int 0) (const_int 1)]))))]
1077 "TARGET_REALLY_IWMMXT"
1078 "wunpckeluh%?\\t%0, %1"
1079 [(set_attr "predicable" "yes")])
1081 (define_insn "iwmmxt_wunpckeluw"
1082 [(set (match_operand:DI 0 "register_operand" "=y")
1083 (zero_extend:DI
1084 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
1085 (parallel [(const_int 0)]))))]
1086 "TARGET_REALLY_IWMMXT"
1087 "wunpckeluw%?\\t%0, %1"
1088 [(set_attr "predicable" "yes")])
1090 (define_insn "iwmmxt_wunpckelsb"
1091 [(set (match_operand:V4HI 0 "register_operand" "=y")
1092 (sign_extend:V4HI
1093 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
1094 (parallel [(const_int 0) (const_int 1)
1095 (const_int 2) (const_int 3)]))))]
1096 "TARGET_REALLY_IWMMXT"
1097 "wunpckelsb%?\\t%0, %1"
1098 [(set_attr "predicable" "yes")])
1100 (define_insn "iwmmxt_wunpckelsh"
1101 [(set (match_operand:V2SI 0 "register_operand" "=y")
1102 (sign_extend:V2SI
1103 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
1104 (parallel [(const_int 0) (const_int 1)]))))]
1105 "TARGET_REALLY_IWMMXT"
1106 "wunpckelsh%?\\t%0, %1"
1107 [(set_attr "predicable" "yes")])
1109 (define_insn "iwmmxt_wunpckelsw"
1110 [(set (match_operand:DI 0 "register_operand" "=y")
1111 (sign_extend:DI
1112 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
1113 (parallel [(const_int 0)]))))]
1114 "TARGET_REALLY_IWMMXT"
1115 "wunpckelsw%?\\t%0, %1"
1116 [(set_attr "predicable" "yes")])
1118 ;; Shifts
1120 (define_insn "rorv4hi3"
1121 [(set (match_operand:V4HI 0 "register_operand" "=y")
1122 (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y")
1123 (match_operand:SI 2 "register_operand" "z")))]
1124 "TARGET_REALLY_IWMMXT"
1125 "wrorhg%?\\t%0, %1, %2"
1126 [(set_attr "predicable" "yes")])
1128 (define_insn "rorv2si3"
1129 [(set (match_operand:V2SI 0 "register_operand" "=y")
1130 (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
1131 (match_operand:SI 2 "register_operand" "z")))]
1132 "TARGET_REALLY_IWMMXT"
1133 "wrorwg%?\\t%0, %1, %2"
1134 [(set_attr "predicable" "yes")])
1136 (define_insn "rordi3"
1137 [(set (match_operand:DI 0 "register_operand" "=y")
1138 (rotatert:DI (match_operand:DI 1 "register_operand" "y")
1139 (match_operand:SI 2 "register_operand" "z")))]
1140 "TARGET_REALLY_IWMMXT"
1141 "wrordg%?\\t%0, %1, %2"
1142 [(set_attr "predicable" "yes")])
1144 (define_insn "ashrv4hi3"
1145 [(set (match_operand:V4HI 0 "register_operand" "=y")
1146 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1147 (match_operand:SI 2 "register_operand" "z")))]
1148 "TARGET_REALLY_IWMMXT"
1149 "wsrahg%?\\t%0, %1, %2"
1150 [(set_attr "predicable" "yes")])
1152 (define_insn "ashrv2si3"
1153 [(set (match_operand:V2SI 0 "register_operand" "=y")
1154 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1155 (match_operand:SI 2 "register_operand" "z")))]
1156 "TARGET_REALLY_IWMMXT"
1157 "wsrawg%?\\t%0, %1, %2"
1158 [(set_attr "predicable" "yes")])
1160 (define_insn "ashrdi3_iwmmxt"
1161 [(set (match_operand:DI 0 "register_operand" "=y")
1162 (ashiftrt:DI (match_operand:DI 1 "register_operand" "y")
1163 (match_operand:SI 2 "register_operand" "z")))]
1164 "TARGET_REALLY_IWMMXT"
1165 "wsradg%?\\t%0, %1, %2"
1166 [(set_attr "predicable" "yes")])
1168 (define_insn "lshrv4hi3"
1169 [(set (match_operand:V4HI 0 "register_operand" "=y")
1170 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1171 (match_operand:SI 2 "register_operand" "z")))]
1172 "TARGET_REALLY_IWMMXT"
1173 "wsrlhg%?\\t%0, %1, %2"
1174 [(set_attr "predicable" "yes")])
1176 (define_insn "lshrv2si3"
1177 [(set (match_operand:V2SI 0 "register_operand" "=y")
1178 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1179 (match_operand:SI 2 "register_operand" "z")))]
1180 "TARGET_REALLY_IWMMXT"
1181 "wsrlwg%?\\t%0, %1, %2"
1182 [(set_attr "predicable" "yes")])
1184 (define_insn "lshrdi3_iwmmxt"
1185 [(set (match_operand:DI 0 "register_operand" "=y")
1186 (lshiftrt:DI (match_operand:DI 1 "register_operand" "y")
1187 (match_operand:SI 2 "register_operand" "z")))]
1188 "TARGET_REALLY_IWMMXT"
1189 "wsrldg%?\\t%0, %1, %2"
1190 [(set_attr "predicable" "yes")])
1192 (define_insn "ashlv4hi3"
1193 [(set (match_operand:V4HI 0 "register_operand" "=y")
1194 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y")
1195 (match_operand:SI 2 "register_operand" "z")))]
1196 "TARGET_REALLY_IWMMXT"
1197 "wsllhg%?\\t%0, %1, %2"
1198 [(set_attr "predicable" "yes")])
1200 (define_insn "ashlv2si3"
1201 [(set (match_operand:V2SI 0 "register_operand" "=y")
1202 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y")
1203 (match_operand:SI 2 "register_operand" "z")))]
1204 "TARGET_REALLY_IWMMXT"
1205 "wsllwg%?\\t%0, %1, %2"
1206 [(set_attr "predicable" "yes")])
1208 (define_insn "ashldi3_iwmmxt"
1209 [(set (match_operand:DI 0 "register_operand" "=y")
1210 (ashift:DI (match_operand:DI 1 "register_operand" "y")
1211 (match_operand:SI 2 "register_operand" "z")))]
1212 "TARGET_REALLY_IWMMXT"
1213 "wslldg%?\\t%0, %1, %2"
1214 [(set_attr "predicable" "yes")])
1216 (define_insn "rorv4hi3_di"
1217 [(set (match_operand:V4HI 0 "register_operand" "=y")
1218 (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y")
1219 (match_operand:DI 2 "register_operand" "y")))]
1220 "TARGET_REALLY_IWMMXT"
1221 "wrorh%?\\t%0, %1, %2"
1222 [(set_attr "predicable" "yes")])
1224 (define_insn "rorv2si3_di"
1225 [(set (match_operand:V2SI 0 "register_operand" "=y")
1226 (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
1227 (match_operand:DI 2 "register_operand" "y")))]
1228 "TARGET_REALLY_IWMMXT"
1229 "wrorw%?\\t%0, %1, %2"
1230 [(set_attr "predicable" "yes")])
1232 (define_insn "rordi3_di"
1233 [(set (match_operand:DI 0 "register_operand" "=y")
1234 (rotatert:DI (match_operand:DI 1 "register_operand" "y")
1235 (match_operand:DI 2 "register_operand" "y")))]
1236 "TARGET_REALLY_IWMMXT"
1237 "wrord%?\\t%0, %1, %2"
1238 [(set_attr "predicable" "yes")])
1240 (define_insn "ashrv4hi3_di"
1241 [(set (match_operand:V4HI 0 "register_operand" "=y")
1242 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1243 (match_operand:DI 2 "register_operand" "y")))]
1244 "TARGET_REALLY_IWMMXT"
1245 "wsrah%?\\t%0, %1, %2"
1246 [(set_attr "predicable" "yes")])
1248 (define_insn "ashrv2si3_di"
1249 [(set (match_operand:V2SI 0 "register_operand" "=y")
1250 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1251 (match_operand:DI 2 "register_operand" "y")))]
1252 "TARGET_REALLY_IWMMXT"
1253 "wsraw%?\\t%0, %1, %2"
1254 [(set_attr "predicable" "yes")])
1256 (define_insn "ashrdi3_di"
1257 [(set (match_operand:DI 0 "register_operand" "=y")
1258 (ashiftrt:DI (match_operand:DI 1 "register_operand" "y")
1259 (match_operand:DI 2 "register_operand" "y")))]
1260 "TARGET_REALLY_IWMMXT"
1261 "wsrad%?\\t%0, %1, %2"
1262 [(set_attr "predicable" "yes")])
1264 (define_insn "lshrv4hi3_di"
1265 [(set (match_operand:V4HI 0 "register_operand" "=y")
1266 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1267 (match_operand:DI 2 "register_operand" "y")))]
1268 "TARGET_REALLY_IWMMXT"
1269 "wsrlh%?\\t%0, %1, %2"
1270 [(set_attr "predicable" "yes")])
1272 (define_insn "lshrv2si3_di"
1273 [(set (match_operand:V2SI 0 "register_operand" "=y")
1274 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1275 (match_operand:DI 2 "register_operand" "y")))]
1276 "TARGET_REALLY_IWMMXT"
1277 "wsrlw%?\\t%0, %1, %2"
1278 [(set_attr "predicable" "yes")])
1280 (define_insn "lshrdi3_di"
1281 [(set (match_operand:DI 0 "register_operand" "=y")
1282 (lshiftrt:DI (match_operand:DI 1 "register_operand" "y")
1283 (match_operand:DI 2 "register_operand" "y")))]
1284 "TARGET_REALLY_IWMMXT"
1285 "wsrld%?\\t%0, %1, %2"
1286 [(set_attr "predicable" "yes")])
1288 (define_insn "ashlv4hi3_di"
1289 [(set (match_operand:V4HI 0 "register_operand" "=y")
1290 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y")
1291 (match_operand:DI 2 "register_operand" "y")))]
1292 "TARGET_REALLY_IWMMXT"
1293 "wsllh%?\\t%0, %1, %2"
1294 [(set_attr "predicable" "yes")])
1296 (define_insn "ashlv2si3_di"
1297 [(set (match_operand:V2SI 0 "register_operand" "=y")
1298 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y")
1299 (match_operand:DI 2 "register_operand" "y")))]
1300 "TARGET_REALLY_IWMMXT"
1301 "wsllw%?\\t%0, %1, %2"
1302 [(set_attr "predicable" "yes")])
1304 (define_insn "ashldi3_di"
1305 [(set (match_operand:DI 0 "register_operand" "=y")
1306 (ashift:DI (match_operand:DI 1 "register_operand" "y")
1307 (match_operand:DI 2 "register_operand" "y")))]
1308 "TARGET_REALLY_IWMMXT"
1309 "wslld%?\\t%0, %1, %2"
1310 [(set_attr "predicable" "yes")])
1312 (define_insn "iwmmxt_wmadds"
1313 [(set (match_operand:V4HI 0 "register_operand" "=y")
1314 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1315 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDS))]
1316 "TARGET_REALLY_IWMMXT"
1317 "wmadds%?\\t%0, %1, %2"
1318 [(set_attr "predicable" "yes")])
1320 (define_insn "iwmmxt_wmaddu"
1321 [(set (match_operand:V4HI 0 "register_operand" "=y")
1322 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1323 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDU))]
1324 "TARGET_REALLY_IWMMXT"
1325 "wmaddu%?\\t%0, %1, %2"
1326 [(set_attr "predicable" "yes")])
1328 (define_insn "iwmmxt_tmia"
1329 [(set (match_operand:DI 0 "register_operand" "=y")
1330 (plus:DI (match_operand:DI 1 "register_operand" "0")
1331 (mult:DI (sign_extend:DI
1332 (match_operand:SI 2 "register_operand" "r"))
1333 (sign_extend:DI
1334 (match_operand:SI 3 "register_operand" "r")))))]
1335 "TARGET_REALLY_IWMMXT"
1336 "tmia%?\\t%0, %2, %3"
1337 [(set_attr "predicable" "yes")])
1339 (define_insn "iwmmxt_tmiaph"
1340 [(set (match_operand:DI 0 "register_operand" "=y")
1341 (plus:DI (match_operand:DI 1 "register_operand" "0")
1342 (plus:DI
1343 (mult:DI (sign_extend:DI
1344 (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1345 (sign_extend:DI
1346 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))
1347 (mult:DI (sign_extend:DI
1348 (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16))))
1349 (sign_extend:DI
1350 (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))]
1351 "TARGET_REALLY_IWMMXT"
1352 "tmiaph%?\\t%0, %2, %3"
1353 [(set_attr "predicable" "yes")])
1355 (define_insn "iwmmxt_tmiabb"
1356 [(set (match_operand:DI 0 "register_operand" "=y")
1357 (plus:DI (match_operand:DI 1 "register_operand" "0")
1358 (mult:DI (sign_extend:DI
1359 (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1360 (sign_extend:DI
1361 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1362 "TARGET_REALLY_IWMMXT"
1363 "tmiabb%?\\t%0, %2, %3"
1364 [(set_attr "predicable" "yes")])
1366 (define_insn "iwmmxt_tmiatb"
1367 [(set (match_operand:DI 0 "register_operand" "=y")
1368 (plus:DI (match_operand:DI 1 "register_operand" "0")
1369 (mult:DI (sign_extend:DI
1370 (truncate:HI (ashiftrt:SI
1371 (match_operand:SI 2 "register_operand" "r")
1372 (const_int 16))))
1373 (sign_extend:DI
1374 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1375 "TARGET_REALLY_IWMMXT"
1376 "tmiatb%?\\t%0, %2, %3"
1377 [(set_attr "predicable" "yes")])
1379 (define_insn "iwmmxt_tmiabt"
1380 [(set (match_operand:DI 0 "register_operand" "=y")
1381 (plus:DI (match_operand:DI 1 "register_operand" "0")
1382 (mult:DI (sign_extend:DI
1383 (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1384 (sign_extend:DI
1385 (truncate:HI (ashiftrt:SI
1386 (match_operand:SI 3 "register_operand" "r")
1387 (const_int 16)))))))]
1388 "TARGET_REALLY_IWMMXT"
1389 "tmiabt%?\\t%0, %2, %3"
1390 [(set_attr "predicable" "yes")])
1392 (define_insn "iwmmxt_tmiatt"
1393 [(set (match_operand:DI 0 "register_operand" "=y")
1394 (plus:DI (match_operand:DI 1 "register_operand" "0")
1395 (mult:DI (sign_extend:DI
1396 (truncate:HI (ashiftrt:SI
1397 (match_operand:SI 2 "register_operand" "r")
1398 (const_int 16))))
1399 (sign_extend:DI
1400 (truncate:HI (ashiftrt:SI
1401 (match_operand:SI 3 "register_operand" "r")
1402 (const_int 16)))))))]
1403 "TARGET_REALLY_IWMMXT"
1404 "tmiatt%?\\t%0, %2, %3"
1405 [(set_attr "predicable" "yes")])
1407 (define_insn "iwmmxt_tbcstqi"
1408 [(set (match_operand:V8QI 0 "register_operand" "=y")
1409 (vec_duplicate:V8QI (match_operand:QI 1 "register_operand" "r")))]
1410 "TARGET_REALLY_IWMMXT"
1411 "tbcstb%?\\t%0, %1"
1412 [(set_attr "predicable" "yes")])
1414 (define_insn "iwmmxt_tbcsthi"
1415 [(set (match_operand:V4HI 0 "register_operand" "=y")
1416 (vec_duplicate:V4HI (match_operand:HI 1 "register_operand" "r")))]
1417 "TARGET_REALLY_IWMMXT"
1418 "tbcsth%?\\t%0, %1"
1419 [(set_attr "predicable" "yes")])
1421 (define_insn "iwmmxt_tbcstsi"
1422 [(set (match_operand:V2SI 0 "register_operand" "=y")
1423 (vec_duplicate:V2SI (match_operand:SI 1 "register_operand" "r")))]
1424 "TARGET_REALLY_IWMMXT"
1425 "tbcstw%?\\t%0, %1"
1426 [(set_attr "predicable" "yes")])
1428 (define_insn "iwmmxt_tmovmskb"
1429 [(set (match_operand:SI 0 "register_operand" "=r")
1430 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1431 "TARGET_REALLY_IWMMXT"
1432 "tmovmskb%?\\t%0, %1"
1433 [(set_attr "predicable" "yes")])
1435 (define_insn "iwmmxt_tmovmskh"
1436 [(set (match_operand:SI 0 "register_operand" "=r")
1437 (unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1438 "TARGET_REALLY_IWMMXT"
1439 "tmovmskh%?\\t%0, %1"
1440 [(set_attr "predicable" "yes")])
1442 (define_insn "iwmmxt_tmovmskw"
1443 [(set (match_operand:SI 0 "register_operand" "=r")
1444 (unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1445 "TARGET_REALLY_IWMMXT"
1446 "tmovmskw%?\\t%0, %1"
1447 [(set_attr "predicable" "yes")])
1449 (define_insn "iwmmxt_waccb"
1450 [(set (match_operand:DI 0 "register_operand" "=y")
1451 (unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))]
1452 "TARGET_REALLY_IWMMXT"
1453 "waccb%?\\t%0, %1"
1454 [(set_attr "predicable" "yes")])
1456 (define_insn "iwmmxt_wacch"
1457 [(set (match_operand:DI 0 "register_operand" "=y")
1458 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))]
1459 "TARGET_REALLY_IWMMXT"
1460 "wacch%?\\t%0, %1"
1461 [(set_attr "predicable" "yes")])
1463 (define_insn "iwmmxt_waccw"
1464 [(set (match_operand:DI 0 "register_operand" "=y")
1465 (unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))]
1466 "TARGET_REALLY_IWMMXT"
1467 "waccw%?\\t%0, %1"
1468 [(set_attr "predicable" "yes")])
1470 (define_insn "iwmmxt_walign"
1471 [(set (match_operand:V8QI 0 "register_operand" "=y,y")
1472 (subreg:V8QI (ashiftrt:TI
1473 (subreg:TI (vec_concat:V16QI
1474 (match_operand:V8QI 1 "register_operand" "y,y")
1475 (match_operand:V8QI 2 "register_operand" "y,y")) 0)
1476 (mult:SI
1477 (match_operand:SI 3 "nonmemory_operand" "i,z")
1478 (const_int 8))) 0))]
1479 "TARGET_REALLY_IWMMXT"
1480 "@
1481 waligni%?\\t%0, %1, %2, %3
1482 walignr%U3%?\\t%0, %1, %2"
1483 [(set_attr "predicable" "yes")])
1485 (define_insn "iwmmxt_tmrc"
1486 [(set (match_operand:SI 0 "register_operand" "=r")
1487 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")]
1488 VUNSPEC_TMRC))]
1489 "TARGET_REALLY_IWMMXT"
1490 "tmrc%?\\t%0, %w1"
1491 [(set_attr "predicable" "yes")])
1493 (define_insn "iwmmxt_tmcr"
1494 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
1495 (match_operand:SI 1 "register_operand" "r")]
1496 VUNSPEC_TMCR)]
1497 "TARGET_REALLY_IWMMXT"
1498 "tmcr%?\\t%w0, %1"
1499 [(set_attr "predicable" "yes")])
1501 (define_insn "iwmmxt_wsadb"
1502 [(set (match_operand:V8QI 0 "register_operand" "=y")
1503 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1504 (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSAD))]
1505 "TARGET_REALLY_IWMMXT"
1506 "wsadb%?\\t%0, %1, %2"
1507 [(set_attr "predicable" "yes")])
1509 (define_insn "iwmmxt_wsadh"
1510 [(set (match_operand:V4HI 0 "register_operand" "=y")
1511 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1512 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSAD))]
1513 "TARGET_REALLY_IWMMXT"
1514 "wsadh%?\\t%0, %1, %2"
1515 [(set_attr "predicable" "yes")])
1517 (define_insn "iwmmxt_wsadbz"
1518 [(set (match_operand:V8QI 0 "register_operand" "=y")
1519 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1520 (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1521 "TARGET_REALLY_IWMMXT"
1522 "wsadbz%?\\t%0, %1, %2"
1523 [(set_attr "predicable" "yes")])
1525 (define_insn "iwmmxt_wsadhz"
1526 [(set (match_operand:V4HI 0 "register_operand" "=y")
1527 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1528 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1529 "TARGET_REALLY_IWMMXT"
1530 "wsadhz%?\\t%0, %1, %2"
1531 [(set_attr "predicable" "yes")])