MIPS32R6 and MIPS64R6 support
[official-gcc.git] / gcc / config / mips / mips-modes.def
blob96d72c16ad456a4f1c842554f69a64e7609b7db2
1 /* MIPS extra machine modes.
2 Copyright (C) 2003-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 FLOAT_MODE (TF, 16, ieee_quad_format);
22 /* Vector modes. */
23 VECTOR_MODES (INT, 4); /* V4QI V2HI */
24 VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */
25 VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */
27 /* Double-sized vector modes for vec_concat. */
28 VECTOR_MODE (INT, QI, 16); /* V16QI */
29 VECTOR_MODE (INT, HI, 8); /* V8HI */
30 VECTOR_MODE (INT, SI, 4); /* V4SI */
31 VECTOR_MODE (FLOAT, SF, 4); /* V4SF */
33 VECTOR_MODES (FRACT, 4); /* V4QQ V2HQ */
34 VECTOR_MODES (UFRACT, 4); /* V4UQQ V2UHQ */
35 VECTOR_MODES (ACCUM, 4); /* V2HA */
36 VECTOR_MODES (UACCUM, 4); /* V2UHA */
38 /* Paired single comparison instructions use 2 or 4 CC. */
39 CC_MODE (CCV2);
40 ADJUST_BYTESIZE (CCV2, 8);
41 ADJUST_ALIGNMENT (CCV2, 8);
43 CC_MODE (CCV4);
44 ADJUST_BYTESIZE (CCV4, 16);
45 ADJUST_ALIGNMENT (CCV4, 16);
47 /* For MIPS DSP control registers. */
48 CC_MODE (CCDSP);
50 /* For floating point conditions in FP registers. */
51 CC_MODE (CCF);