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* system.h (ENCODE_SECTION_INFO): Poison it.
[official-gcc.git] / gcc / config / i386 / i386.h
blob277290105e75d823fbabdeb1a91b631aee1be109
1 /* Definitions of target machine for GNU compiler for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
4
5 This file is part of GNU CC.
6
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
24
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
27
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
30
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
36
37 /* Stubs for half-pic support if not OSF/1 reference platform. */
38
39 #ifndef HALF_PIC_P
40 #define HALF_PIC_P() 0
41 #define HALF_PIC_NUMBER_PTRS 0
42 #define HALF_PIC_NUMBER_REFS 0
43 #define HALF_PIC_ENCODE(DECL)
44 #define HALF_PIC_DECLARE(NAME)
45 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it")
46 #define HALF_PIC_ADDRESS_P(X) 0
47 #define HALF_PIC_PTR(X) (X)
48 #define HALF_PIC_FINISH(STREAM)
49 #endif
50
51 /* Define the specific costs for a given cpu */
52
53 struct processor_costs {
54 const int add; /* cost of an add instruction */
55 const int lea; /* cost of a lea instruction */
56 const int shift_var; /* variable shift costs */
57 const int shift_const; /* constant shift costs */
58 const int mult_init; /* cost of starting a multiply */
59 const int mult_bit; /* cost of multiply per each bit set */
60 const int divide; /* cost of a divide/mod */
61 int movsx; /* The cost of movsx operation. */
62 int movzx; /* The cost of movzx operation. */
63 const int large_insn; /* insns larger than this cost more */
64 const int move_ratio; /* The threshold of number of scalar
65 memory-to-memory move insns. */
66 const int movzbl_load; /* cost of loading using movzbl */
67 const int int_load[3]; /* cost of loading integer registers
68 in QImode, HImode and SImode relative
69 to reg-reg move (2). */
70 const int int_store[3]; /* cost of storing integer register
71 in QImode, HImode and SImode */
72 const int fp_move; /* cost of reg,reg fld/fst */
73 const int fp_load[3]; /* cost of loading FP register
74 in SFmode, DFmode and XFmode */
75 const int fp_store[3]; /* cost of storing FP register
76 in SFmode, DFmode and XFmode */
77 const int mmx_move; /* cost of moving MMX register. */
78 const int mmx_load[2]; /* cost of loading MMX register
79 in SImode and DImode */
80 const int mmx_store[2]; /* cost of storing MMX register
81 in SImode and DImode */
82 const int sse_move; /* cost of moving SSE register. */
83 const int sse_load[3]; /* cost of loading SSE register
84 in SImode, DImode and TImode*/
85 const int sse_store[3]; /* cost of storing SSE register
86 in SImode, DImode and TImode*/
87 const int mmxsse_to_integer; /* cost of moving mmxsse register to
88 integer and vice versa. */
89 const int prefetch_block; /* bytes moved to cache for prefetch. */
90 const int simultaneous_prefetches; /* number of parallel prefetch
91 operations. */
92 };
93
94 extern const struct processor_costs *ix86_cost;
95
96 /* Run-time compilation parameters selecting different hardware subsets. */
97
98 extern int target_flags;
99
100 /* Macros used in the machine description to test the flags. */
101
102 /* configure can arrange to make this 2, to force a 486. */
103
104 #ifndef TARGET_CPU_DEFAULT
105 #define TARGET_CPU_DEFAULT 0
106 #endif
107
108 /* Masks for the -m switches */
109 #define MASK_80387 0x00000001 /* Hardware floating point */
110 #define MASK_RTD 0x00000002 /* Use ret that pops args */
111 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
112 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
113 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
114 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
115 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
116 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
117 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
118 #define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */
119 #define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */
120 #define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */
121 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */
122 #define MASK_ACCUMULATE_OUTGOING_ARGS_SET 0x00002000
123 #define MASK_MMX 0x00004000 /* Support MMX regs/builtins */
124 #define MASK_MMX_SET 0x00008000
125 #define MASK_SSE 0x00010000 /* Support SSE regs/builtins */
126 #define MASK_SSE_SET 0x00020000
127 #define MASK_SSE2 0x00040000 /* Support SSE2 regs/builtins */
128 #define MASK_SSE2_SET 0x00080000
129 #define MASK_3DNOW 0x00100000 /* Support 3Dnow builtins */
130 #define MASK_3DNOW_SET 0x00200000
131 #define MASK_3DNOW_A 0x00400000 /* Support Athlon 3Dnow builtins */
132 #define MASK_3DNOW_A_SET 0x00800000
133 #define MASK_128BIT_LONG_DOUBLE 0x01000000 /* long double size is 128bit */
134 #define MASK_64BIT 0x02000000 /* Produce 64bit code */
135 /* ... overlap with subtarget options starts by 0x04000000. */
136 #define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */
137
138 /* Use the floating point instructions */
139 #define TARGET_80387 (target_flags & MASK_80387)
140
141 /* Compile using ret insn that pops args.
142 This will not work unless you use prototypes at least
143 for all functions that can take varying numbers of args. */
144 #define TARGET_RTD (target_flags & MASK_RTD)
145
146 /* Align doubles to a two word boundary. This breaks compatibility with
147 the published ABI's for structures containing doubles, but produces
148 faster code on the pentium. */
149 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
150
151 /* Use push instructions to save outgoing args. */
152 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
153
154 /* Accumulate stack adjustments to prologue/epilogue. */
155 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
156 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
157
158 /* Put uninitialized locals into bss, not data.
159 Meaningful only on svr3. */
160 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
161
162 /* Use IEEE floating point comparisons. These handle correctly the cases
163 where the result of a comparison is unordered. Normally SIGFPE is
164 generated in such cases, in which case this isn't needed. */
165 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
166
167 /* Functions that return a floating point value may return that value
168 in the 387 FPU or in 386 integer registers. If set, this flag causes
169 the 387 to be used, which is compatible with most calling conventions. */
170 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
171
172 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
173 This mode wastes cache, but avoid misaligned data accesses and simplifies
174 address calculations. */
175 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
176
177 /* Disable generation of FP sin, cos and sqrt operations for 387.
178 This is because FreeBSD lacks these in the math-emulator-code */
179 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
180
181 /* Don't create frame pointers for leaf functions */
182 #define TARGET_OMIT_LEAF_FRAME_POINTER \
183 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
184
185 /* Debug GO_IF_LEGITIMATE_ADDRESS */
186 #define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0)
187
188 /* Debug FUNCTION_ARG macros */
189 #define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0)
190
191 /* 64bit Sledgehammer mode */
192 #ifdef TARGET_BI_ARCH
193 #define TARGET_64BIT (target_flags & MASK_64BIT)
194 #else
195 #ifdef TARGET_64BIT_DEFAULT
196 #define TARGET_64BIT 1
197 #else
198 #define TARGET_64BIT 0
199 #endif
200 #endif
201
202 #define TARGET_386 (ix86_cpu == PROCESSOR_I386)
203 #define TARGET_486 (ix86_cpu == PROCESSOR_I486)
204 #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
205 #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
206 #define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
207 #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
208 #define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4)
209
210 #define CPUMASK (1 << ix86_cpu)
211 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
212 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
213 extern const int x86_branch_hints, x86_unroll_strlen;
214 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
215 extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
216 extern const int x86_use_cltd, x86_read_modify_write;
217 extern const int x86_read_modify, x86_split_long_moves;
218 extern const int x86_promote_QImode, x86_single_stringop;
219 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
220 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
221 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
222 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
223 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
224 extern const int x86_epilogue_using_move, x86_decompose_lea;
225 extern const int x86_arch_always_fancy_math_387;
226 extern int x86_prefetch_sse;
227
228 #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
229 #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
230 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
231 #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
232 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
233 /* For sane SSE instruction set generation we need fcomi instruction. It is
234 safe to enable all CMOVE instructions. */
235 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
236 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
237 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK)
238 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
239 #define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT)
240 #define TARGET_MOVX (x86_movx & CPUMASK)
241 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK)
242 #define TARGET_USE_LOOP (x86_use_loop & CPUMASK)
243 #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK)
244 #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK)
245 #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK)
246 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK)
247 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK)
248 #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK)
249 #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK)
250 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK)
251 #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK)
252 #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK)
253 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK)
254 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK)
255 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK)
256 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK)
257 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK)
258 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK)
259 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK)
260 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK)
261 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK)
262 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK)
263 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK)
264 #define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK)
265 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
266
267 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
268
269 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
270 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
271
272 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
273
274 #define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
275 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
276 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
277 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
278 && (ix86_fpmath & FPMATH_387))
279 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
280 #define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
281 #define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
282
283 #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
284
285 /* WARNING: Do not mark empty strings for translation, as calling
286 gettext on an empty string does NOT return an empty
287 string. */
288
289
290 #define TARGET_SWITCHES \
291 { { "80387", MASK_80387, N_("Use hardware fp") }, \
292 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
293 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
294 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
295 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
296 { "386", 0, "" /*Deprecated.*/}, \
297 { "486", 0, "" /*Deprecated.*/}, \
298 { "pentium", 0, "" /*Deprecated.*/}, \
299 { "pentiumpro", 0, "" /*Deprecated.*/}, \
300 { "intel-syntax", 0, "" /*Deprecated.*/}, \
301 { "no-intel-syntax", 0, "" /*Deprecated.*/}, \
302 { "rtd", MASK_RTD, \
303 N_("Alternate calling convention") }, \
304 { "no-rtd", -MASK_RTD, \
305 N_("Use normal calling convention") }, \
306 { "align-double", MASK_ALIGN_DOUBLE, \
307 N_("Align some doubles on dword boundary") }, \
308 { "no-align-double", -MASK_ALIGN_DOUBLE, \
309 N_("Align doubles on word boundary") }, \
310 { "svr3-shlib", MASK_SVR3_SHLIB, \
311 N_("Uninitialized locals in .bss") }, \
312 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
313 N_("Uninitialized locals in .data") }, \
314 { "ieee-fp", MASK_IEEE_FP, \
315 N_("Use IEEE math for fp comparisons") }, \
316 { "no-ieee-fp", -MASK_IEEE_FP, \
317 N_("Do not use IEEE math for fp comparisons") }, \
318 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
319 N_("Return values of functions in FPU registers") }, \
320 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
321 N_("Do not return values of functions in FPU registers")}, \
322 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
323 N_("Do not generate sin, cos, sqrt for FPU") }, \
324 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
325 N_("Generate sin, cos, sqrt for FPU")}, \
326 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
327 N_("Omit the frame pointer in leaf functions") }, \
328 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
329 { "stack-arg-probe", MASK_STACK_PROBE, \
330 N_("Enable stack probing") }, \
331 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
332 { "windows", 0, 0 /* undocumented */ }, \
333 { "dll", 0, 0 /* undocumented */ }, \
334 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
335 N_("Align destination of the string operations") }, \
336 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
337 N_("Do not align destination of the string operations") }, \
338 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
339 N_("Inline all known string operations") }, \
340 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
341 N_("Do not inline all known string operations") }, \
342 { "push-args", -MASK_NO_PUSH_ARGS, \
343 N_("Use push instructions to save outgoing arguments") }, \
344 { "no-push-args", MASK_NO_PUSH_ARGS, \
345 N_("Do not use push instructions to save outgoing arguments") }, \
346 { "accumulate-outgoing-args", (MASK_ACCUMULATE_OUTGOING_ARGS \
347 | MASK_ACCUMULATE_OUTGOING_ARGS_SET), \
348 N_("Use push instructions to save outgoing arguments") }, \
349 { "no-accumulate-outgoing-args",MASK_ACCUMULATE_OUTGOING_ARGS_SET, \
350 N_("Do not use push instructions to save outgoing arguments") }, \
351 { "mmx", MASK_MMX | MASK_MMX_SET, \
352 N_("Support MMX built-in functions") }, \
353 { "no-mmx", -MASK_MMX, \
354 N_("Do not support MMX built-in functions") }, \
355 { "no-mmx", MASK_MMX_SET, "" }, \
356 { "3dnow", MASK_3DNOW | MASK_3DNOW_SET, \
357 N_("Support 3DNow! built-in functions") }, \
358 { "no-3dnow", -MASK_3DNOW, "" }, \
359 { "no-3dnow", MASK_3DNOW_SET, \
360 N_("Do not support 3DNow! built-in functions") }, \
361 { "sse", MASK_SSE | MASK_SSE_SET, \
362 N_("Support MMX and SSE built-in functions and code generation") }, \
363 { "no-sse", -MASK_SSE, "" }, \
364 { "no-sse", MASK_SSE_SET, \
365 N_("Do not support MMX and SSE built-in functions and code generation") },\
366 { "sse2", MASK_SSE2 | MASK_SSE2_SET, \
367 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
368 { "no-sse2", -MASK_SSE2, "" }, \
369 { "no-sse2", MASK_SSE2_SET, \
370 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
371 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
372 N_("sizeof(long double) is 16") }, \
373 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
374 N_("sizeof(long double) is 12") }, \
375 { "64", MASK_64BIT, \
376 N_("Generate 64bit x86-64 code") }, \
377 { "32", -MASK_64BIT, \
378 N_("Generate 32bit i386 code") }, \
379 { "red-zone", -MASK_NO_RED_ZONE, \
380 N_("Use red-zone in the x86-64 code") }, \
381 { "no-red-zone", MASK_NO_RED_ZONE, \
382 N_("Do not use red-zone in the x86-64 code") }, \
383 SUBTARGET_SWITCHES \
384 { "", TARGET_DEFAULT, 0 }}
385
386 #ifdef TARGET_64BIT_DEFAULT
387 #define TARGET_DEFAULT (MASK_64BIT | TARGET_SUBTARGET_DEFAULT)
388 #else
389 #define TARGET_DEFAULT TARGET_SUBTARGET_DEFAULT
390 #endif
391
392 /* Which processor to schedule for. The cpu attribute defines a list that
393 mirrors this list, so changes to i386.md must be made at the same time. */
394
395 enum processor_type
396 {
397 PROCESSOR_I386, /* 80386 */
398 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
399 PROCESSOR_PENTIUM,
400 PROCESSOR_PENTIUMPRO,
401 PROCESSOR_K6,
402 PROCESSOR_ATHLON,
403 PROCESSOR_PENTIUM4,
404 PROCESSOR_max
405 };
406 enum fpmath_unit
407 {
408 FPMATH_387 = 1,
409 FPMATH_SSE = 2
410 };
411
412 extern enum processor_type ix86_cpu;
413 extern enum fpmath_unit ix86_fpmath;
414
415 extern int ix86_arch;
416
417 /* This macro is similar to `TARGET_SWITCHES' but defines names of
418 command options that have values. Its definition is an
419 initializer with a subgrouping for each command option.
420
421 Each subgrouping contains a string constant, that defines the
422 fixed part of the option name, and the address of a variable. The
423 variable, type `char *', is set to the variable part of the given
424 option if the fixed part matches. The actual option name is made
425 by appending `-m' to the specified name. */
426 #define TARGET_OPTIONS \
427 { { "cpu=", &ix86_cpu_string, \
428 N_("Schedule code for given CPU")}, \
429 { "fpmath=", &ix86_fpmath_string, \
430 N_("Generate floating point mathematics using given instruction set")},\
431 { "arch=", &ix86_arch_string, \
432 N_("Generate code for given CPU")}, \
433 { "regparm=", &ix86_regparm_string, \
434 N_("Number of registers used to pass integer arguments") }, \
435 { "align-loops=", &ix86_align_loops_string, \
436 N_("Loop code aligned to this power of 2") }, \
437 { "align-jumps=", &ix86_align_jumps_string, \
438 N_("Jump targets are aligned to this power of 2") }, \
439 { "align-functions=", &ix86_align_funcs_string, \
440 N_("Function starts are aligned to this power of 2") }, \
441 { "preferred-stack-boundary=", \
442 &ix86_preferred_stack_boundary_string, \
443 N_("Attempt to keep stack aligned to this power of 2") }, \
444 { "branch-cost=", &ix86_branch_cost_string, \
445 N_("Branches are this expensive (1-5, arbitrary units)") }, \
446 { "cmodel=", &ix86_cmodel_string, \
447 N_("Use given x86-64 code model") }, \
448 { "debug-arg", &ix86_debug_arg_string, \
449 "" /* Undocumented. */ }, \
450 { "debug-addr", &ix86_debug_addr_string, \
451 "" /* Undocumented. */ }, \
452 { "asm=", &ix86_asm_string, \
453 N_("Use given assembler dialect") }, \
454 SUBTARGET_OPTIONS \
455 }
456
457 /* Sometimes certain combinations of command options do not make
458 sense on a particular target machine. You can define a macro
459 `OVERRIDE_OPTIONS' to take account of this. This macro, if
460 defined, is executed once just after all the command options have
461 been parsed.
462
463 Don't use this macro to turn on various extra optimizations for
464 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
465
466 #define OVERRIDE_OPTIONS override_options ()
467
468 /* These are meant to be redefined in the host dependent files */
469 #define SUBTARGET_SWITCHES
470 #define SUBTARGET_OPTIONS
471
472 /* Define this to change the optimizations performed by default. */
473 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
474 optimization_options ((LEVEL), (SIZE))
475
476 /* Specs for the compiler proper */
477
478 #ifndef CC1_CPU_SPEC
479 #define CC1_CPU_SPEC "\
480 %{!mcpu*: \
481 %{m386:-mcpu=i386 \
482 %n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \
483 %{m486:-mcpu=i486 \
484 %n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \
485 %{mpentium:-mcpu=pentium \
486 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \
487 %{mpentiumpro:-mcpu=pentiumpro \
488 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \
489 %{mintel-syntax:-masm=intel \
490 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
491 %{mno-intel-syntax:-masm=att \
492 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
493 #endif
494 \f
495 #define TARGET_CPU_DEFAULT_i386 0
496 #define TARGET_CPU_DEFAULT_i486 1
497 #define TARGET_CPU_DEFAULT_pentium 2
498 #define TARGET_CPU_DEFAULT_pentium_mmx 3
499 #define TARGET_CPU_DEFAULT_pentiumpro 4
500 #define TARGET_CPU_DEFAULT_pentium2 5
501 #define TARGET_CPU_DEFAULT_pentium3 6
502 #define TARGET_CPU_DEFAULT_pentium4 7
503 #define TARGET_CPU_DEFAULT_k6 8
504 #define TARGET_CPU_DEFAULT_k6_2 9
505 #define TARGET_CPU_DEFAULT_k6_3 10
506 #define TARGET_CPU_DEFAULT_athlon 11
507 #define TARGET_CPU_DEFAULT_athlon_sse 12
508
509 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
510 "pentiumpro", "pentium2", "pentium3", \
511 "pentium4", "k6", "k6-2", "k6-3",\
512 "athlon", "athlon-4"}
513 #ifndef CPP_CPU_DEFAULT_SPEC
514 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_i486
515 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__"
516 #endif
517 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium
518 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__"
519 #endif
520 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium_mmx
521 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__"
522 #endif
523 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentiumpro
524 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__"
525 #endif
526 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium2
527 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
528 -D__tune_pentium2__"
529 #endif
530 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium3
531 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
532 -D__tune_pentium2__ -D__tune_pentium3__"
533 #endif
534 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium4
535 #define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__"
536 #endif
537 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6
538 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__"
539 #endif
540 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_2
541 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_2__"
542 #endif
543 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_3
544 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_3__"
545 #endif
546 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon
547 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__"
548 #endif
549 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon_sse
550 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__ -D__tune_athlon_sse__"
551 #endif
552 #ifndef CPP_CPU_DEFAULT_SPEC
553 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__"
554 #endif
555 #endif /* CPP_CPU_DEFAULT_SPEC */
556
557 #define CPP_CPU32_SPEC \
558 "-Acpu=i386 -Amachine=i386 %{!ansi:%{!std=c*:%{!std=i*:-Di386}}} -D__i386 \
559 -D__i386__"
560
561 #define CPP_CPU64_SPEC \
562 "-Acpu=x86_64 -Amachine=x86_64 -D__x86_64 -D__x86_64__"
563
564 #define CPP_CPUCOMMON_SPEC "\
565 %{march=i386:%{!mcpu*:-D__tune_i386__ }}\
566 %{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\
567 %{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
568 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\
569 %{march=pentium-mmx:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
570 -D__pentium__mmx__ \
571 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__}}\
572 %{march=pentiumpro|march=i686:-D__i686 -D__i686__ \
573 -D__pentiumpro -D__pentiumpro__ \
574 %{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\
575 %{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\
576 %{march=k6-2:-D__k6 -D__k6__ -D__k6_2__ \
577 %{!mcpu*:-D__tune_k6__ -D__tune_k6_2__ }}\
578 %{march=k6-3:-D__k6 -D__k6__ -D__k6_3__ \
579 %{!mcpu*:-D__tune_k6__ -D__tune_k6_3__ }}\
580 %{march=athlon|march=athlon-tbird:-D__athlon -D__athlon__ \
581 %{!mcpu*:-D__tune_athlon__ }}\
582 %{march=athlon-4|march=athlon-xp|march=athlon-mp:-D__athlon -D__athlon__ \
583 -D__athlon_sse__ \
584 %{!mcpu*:-D__tune_athlon__ -D__tune_athlon_sse__ }}\
585 %{march=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\
586 %{m386|mcpu=i386:-D__tune_i386__ }\
587 %{m486|mcpu=i486:-D__tune_i486__ }\
588 %{mpentium|mcpu=pentium|mcpu=i586|mcpu=pentium-mmx:-D__tune_i586__ -D__tune_pentium__ }\
589 %{mpentiumpro|mcpu=pentiumpro|mcpu=i686|cpu=pentium2|cpu=pentium3:-D__tune_i686__ \
590 -D__tune_pentiumpro__ }\
591 %{mcpu=k6|mcpu=k6-2|mcpu=k6-3:-D__tune_k6__ }\
592 %{mcpu=athlon|mcpu=athlon-tbird|mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
593 -D__tune_athlon__ }\
594 %{mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
595 -D__tune_athlon_sse__ }\
596 %{mcpu=pentium4:-D__tune_pentium4__ }\
597 %{march=athlon-tbird|march=athlon-xp|march=athlon-mp|march=pentium3|march=pentium4:\
598 -D__SSE__ }\
599 %{march=pentium-mmx|march=k6|march=k6-2|march=k6-3\
600 |march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
601 |march=athlon-mp|march=pentium2|march=pentium3|march=pentium4: -D__MMX__ }\
602 %{march=k6-2|march=k6-3\
603 |march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
604 |march=athlon-mp: -D__3dNOW__ }\
605 %{march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
606 |march=athlon-mp: -D__3dNOW_A__ }\
607 %{msse2: -D__SSE2__ }\
608 %{march=pentium4: -D__SSE2__ }\
609 %{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}"
610
611 #ifndef CPP_CPU_SPEC
612 #ifdef TARGET_BI_ARCH
613 #ifdef TARGET_64BIT_DEFAULT
614 #define CPP_CPU_SPEC "%{m32:%(cpp_cpu32)}%{!m32:%(cpp_cpu64)} %(cpp_cpucommon)"
615 #else
616 #define CPP_CPU_SPEC "%{m64:%(cpp_cpu64)}%{!m64:%(cpp_cpu32)} %(cpp_cpucommon)"
617 #endif
618 #else
619 #ifdef TARGET_64BIT_DEFAULT
620 #define CPP_CPU_SPEC "%(cpp_cpu64) %(cpp_cpucommon)"
621 #else
622 #define CPP_CPU_SPEC "%(cpp_cpu32) %(cpp_cpucommon)"
623 #endif
624 #endif
625 #endif
626
627 #ifndef CC1_SPEC
628 #define CC1_SPEC "%(cc1_cpu) "
629 #endif
630
631 /* This macro defines names of additional specifications to put in the
632 specs that can be used in various specifications like CC1_SPEC. Its
633 definition is an initializer with a subgrouping for each command option.
634
635 Each subgrouping contains a string constant, that defines the
636 specification name, and a string constant that used by the GNU CC driver
637 program.
638
639 Do not define this macro if it does not need to do anything. */
640
641 #ifndef SUBTARGET_EXTRA_SPECS
642 #define SUBTARGET_EXTRA_SPECS
643 #endif
644
645 #define EXTRA_SPECS \
646 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
647 { "cpp_cpu", CPP_CPU_SPEC }, \
648 { "cpp_cpu32", CPP_CPU32_SPEC }, \
649 { "cpp_cpu64", CPP_CPU64_SPEC }, \
650 { "cpp_cpucommon", CPP_CPUCOMMON_SPEC }, \
651 { "cc1_cpu", CC1_CPU_SPEC }, \
652 SUBTARGET_EXTRA_SPECS
653 \f
654 /* target machine storage layout */
655
656 /* Define for XFmode or TFmode extended real floating point support.
657 The XFmode is specified by i386 ABI, while TFmode may be faster
658 due to alignment and simplifications in the address calculations.
659 */
660 #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
661 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
662 #ifdef __x86_64__
663 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
664 #else
665 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
666 #endif
667 /* Tell real.c that this is the 80-bit Intel extended float format
668 packaged in a 128-bit or 96bit entity. */
669 #define INTEL_EXTENDED_IEEE_FORMAT 1
670
671
672 #define SHORT_TYPE_SIZE 16
673 #define INT_TYPE_SIZE 32
674 #define FLOAT_TYPE_SIZE 32
675 #define LONG_TYPE_SIZE BITS_PER_WORD
676 #define MAX_WCHAR_TYPE_SIZE 32
677 #define DOUBLE_TYPE_SIZE 64
678 #define LONG_LONG_TYPE_SIZE 64
679
680 #if defined (TARGET_BI_ARCH) || defined (TARGET_64BIT_DEFAULT)
681 #define MAX_BITS_PER_WORD 64
682 #define MAX_LONG_TYPE_SIZE 64
683 #else
684 #define MAX_BITS_PER_WORD 32
685 #define MAX_LONG_TYPE_SIZE 32
686 #endif
687
688 /* Define this if most significant byte of a word is the lowest numbered. */
689 /* That is true on the 80386. */
690
691 #define BITS_BIG_ENDIAN 0
692
693 /* Define this if most significant byte of a word is the lowest numbered. */
694 /* That is not true on the 80386. */
695 #define BYTES_BIG_ENDIAN 0
696
697 /* Define this if most significant word of a multiword number is the lowest
698 numbered. */
699 /* Not true for 80386 */
700 #define WORDS_BIG_ENDIAN 0
701
702 /* Width of a word, in units (bytes). */
703 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
704 #define MIN_UNITS_PER_WORD 4
705
706 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
707 #define PARM_BOUNDARY BITS_PER_WORD
708
709 /* Boundary (in *bits*) on which stack pointer should be aligned. */
710 #define STACK_BOUNDARY BITS_PER_WORD
711
712 /* Boundary (in *bits*) on which the stack pointer preferrs to be
713 aligned; the compiler cannot rely on having this alignment. */
714 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
715
716 /* As of July 2001, many runtimes to not align the stack properly when
717 entering main. This causes expand_main_function to forcably align
718 the stack, which results in aligned frames for functions called from
719 main, though it does nothing for the alignment of main itself. */
720 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
721 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
722
723 /* Allocation boundary for the code of a function. */
724 #define FUNCTION_BOUNDARY 16
725
726 /* Alignment of field after `int : 0' in a structure. */
727
728 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
729
730 /* Minimum size in bits of the largest boundary to which any
731 and all fundamental data types supported by the hardware
732 might need to be aligned. No data type wants to be aligned
733 rounder than this.
734
735 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary
736 and Pentium Pro XFmode values at 128 bit boundaries. */
737
738 #define BIGGEST_ALIGNMENT 128
739
740 /* Decide whether a variable of mode MODE must be 128 bit aligned. */
741 #define ALIGN_MODE_128(MODE) \
742 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \
743 || (MODE) == V4SFmode || (MODE) == V4SImode)
744
745 /* The published ABIs say that doubles should be aligned on word
746 boundaries, so lower the aligment for structure fields unless
747 -malign-double is set. */
748 /* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be
749 constant. Use the smaller value in that context. */
750 #ifndef IN_TARGET_LIBS
751 #define BIGGEST_FIELD_ALIGNMENT (TARGET_64BIT ? 128 : (TARGET_ALIGN_DOUBLE ? 64 : 32))
752 #else
753 #define BIGGEST_FIELD_ALIGNMENT 32
754 #endif
755
756 /* If defined, a C expression to compute the alignment given to a
757 constant that is being placed in memory. EXP is the constant
758 and ALIGN is the alignment that the object would ordinarily have.
759 The value of this macro is used instead of that alignment to align
760 the object.
761
762 If this macro is not defined, then ALIGN is used.
763
764 The typical use of this macro is to increase alignment for string
765 constants to be word aligned so that `strcpy' calls that copy
766 constants can be done inline. */
767
768 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
769
770 /* If defined, a C expression to compute the alignment for a static
771 variable. TYPE is the data type, and ALIGN is the alignment that
772 the object would ordinarily have. The value of this macro is used
773 instead of that alignment to align the object.
774
775 If this macro is not defined, then ALIGN is used.
776
777 One use of this macro is to increase alignment of medium-size
778 data to make it all fit in fewer cache lines. Another is to
779 cause character arrays to be word-aligned so that `strcpy' calls
780 that copy constants to character arrays can be done inline. */
781
782 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
783
784 /* If defined, a C expression to compute the alignment for a local
785 variable. TYPE is the data type, and ALIGN is the alignment that
786 the object would ordinarily have. The value of this macro is used
787 instead of that alignment to align the object.
788
789 If this macro is not defined, then ALIGN is used.
790
791 One use of this macro is to increase alignment of medium-size
792 data to make it all fit in fewer cache lines. */
793
794 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
795
796 /* If defined, a C expression that gives the alignment boundary, in
797 bits, of an argument with the specified mode and type. If it is
798 not defined, `PARM_BOUNDARY' is used for all arguments. */
799
800 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
801 ix86_function_arg_boundary ((MODE), (TYPE))
802
803 /* Set this non-zero if move instructions will actually fail to work
804 when given unaligned data. */
805 #define STRICT_ALIGNMENT 0
806
807 /* If bit field type is int, don't let it cross an int,
808 and give entire struct the alignment of an int. */
809 /* Required on the 386 since it doesn't have bitfield insns. */
810 #define PCC_BITFIELD_TYPE_MATTERS 1
811 \f
812 /* Standard register usage. */
813
814 /* This processor has special stack-like registers. See reg-stack.c
815 for details. */
816
817 #define STACK_REGS
818 #define IS_STACK_MODE(MODE) \
819 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \
820 || (MODE) == TFmode)
821
822 /* Number of actual hardware registers.
823 The hardware registers are assigned numbers for the compiler
824 from 0 to just below FIRST_PSEUDO_REGISTER.
825 All registers that the compiler knows about must be given numbers,
826 even those that are not normally considered general registers.
827
828 In the 80386 we give the 8 general purpose registers the numbers 0-7.
829 We number the floating point registers 8-15.
830 Note that registers 0-7 can be accessed as a short or int,
831 while only 0-3 may be used with byte `mov' instructions.
832
833 Reg 16 does not correspond to any hardware register, but instead
834 appears in the RTL as an argument pointer prior to reload, and is
835 eliminated during reloading in favor of either the stack or frame
836 pointer. */
837
838 #define FIRST_PSEUDO_REGISTER 53
839
840 /* Number of hardware registers that go into the DWARF-2 unwind info.
841 If not defined, equals FIRST_PSEUDO_REGISTER. */
842
843 #define DWARF_FRAME_REGISTERS 17
844
845 /* 1 for registers that have pervasive standard uses
846 and are not available for the register allocator.
847 On the 80386, the stack pointer is such, as is the arg pointer.
848
849 The value is an mask - bit 1 is set for fixed registers
850 for 32bit target, while 2 is set for fixed registers for 64bit.
851 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
852 */
853 #define FIXED_REGISTERS \
854 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
855 { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
856 /*arg,flags,fpsr,dir,frame*/ \
857 3, 3, 3, 3, 3, \
858 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
859 0, 0, 0, 0, 0, 0, 0, 0, \
860 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
861 0, 0, 0, 0, 0, 0, 0, 0, \
862 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
863 1, 1, 1, 1, 1, 1, 1, 1, \
864 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
865 1, 1, 1, 1, 1, 1, 1, 1}
866
867
868 /* 1 for registers not available across function calls.
869 These must include the FIXED_REGISTERS and also any
870 registers that can be used without being saved.
871 The latter must include the registers where values are returned
872 and the register where structure-value addresses are passed.
873 Aside from that, you can include as many other registers as you like.
874
875 The value is an mask - bit 1 is set for call used
876 for 32bit target, while 2 is set for call used for 64bit.
877 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
878 */
879 #define CALL_USED_REGISTERS \
880 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
881 { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
882 /*arg,flags,fpsr,dir,frame*/ \
883 3, 3, 3, 3, 3, \
884 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
885 3, 3, 3, 3, 3, 3, 3, 3, \
886 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
887 3, 3, 3, 3, 3, 3, 3, 3, \
888 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
889 3, 3, 3, 3, 1, 1, 1, 1, \
890 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
891 3, 3, 3, 3, 3, 3, 3, 3} \
892
893 /* Order in which to allocate registers. Each register must be
894 listed once, even those in FIXED_REGISTERS. List frame pointer
895 late and fixed registers last. Note that, in general, we prefer
896 registers listed in CALL_USED_REGISTERS, keeping the others
897 available for storage of persistent values.
898
899 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
900 so this is just empty initializer for array. */
901
902 #define REG_ALLOC_ORDER \
903 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
904 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
905 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
906 48, 49, 50, 51, 52 }
907
908 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
909 to be rearranged based on a particular function. When using sse math,
910 we want to allocase SSE before x87 registers and vice vera. */
911
912 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
913
914
915 /* Macro to conditionally modify fixed_regs/call_used_regs. */
916 #define CONDITIONAL_REGISTER_USAGE \
917 do { \
918 int i; \
919 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
920 { \
921 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
922 call_used_regs[i] = (call_used_regs[i] \
923 & (TARGET_64BIT ? 2 : 1)) != 0; \
924 } \
925 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
926 { \
927 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
928 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
929 } \
930 if (! TARGET_MMX) \
931 { \
932 int i; \
933 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
934 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
935 fixed_regs[i] = call_used_regs[i] = 1; \
936 } \
937 if (! TARGET_SSE) \
938 { \
939 int i; \
940 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
941 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
942 fixed_regs[i] = call_used_regs[i] = 1; \
943 } \
944 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
945 { \
946 int i; \
947 HARD_REG_SET x; \
948 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
949 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
950 if (TEST_HARD_REG_BIT (x, i)) \
951 fixed_regs[i] = call_used_regs[i] = 1; \
952 } \
953 } while (0)
954
955 /* Return number of consecutive hard regs needed starting at reg REGNO
956 to hold something of mode MODE.
957 This is ordinarily the length in words of a value of mode MODE
958 but can be less for certain modes in special long registers.
959
960 Actually there are no two word move instructions for consecutive
961 registers. And only registers 0-3 may have mov byte instructions
962 applied to them.
963 */
964
965 #define HARD_REGNO_NREGS(REGNO, MODE) \
966 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
967 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
968 : ((MODE) == TFmode \
969 ? (TARGET_64BIT ? 2 : 3) \
970 : (MODE) == TCmode \
971 ? (TARGET_64BIT ? 4 : 6) \
972 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
973
974 #define VALID_SSE2_REG_MODE(MODE) \
975 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
976 || (MODE) == V2DImode)
977
978 #define VALID_SSE_REG_MODE(MODE) \
979 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
980 || (MODE) == SFmode \
981 /* Always accept SSE2 modes so that xmmintrin.h compiles. */ \
982 || VALID_SSE2_REG_MODE (MODE) \
983 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
984
985 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
986 ((MODE) == V2SFmode || (MODE) == SFmode)
987
988 #define VALID_MMX_REG_MODE(MODE) \
989 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
990 || (MODE) == V2SImode || (MODE) == SImode)
991
992 #define VECTOR_MODE_SUPPORTED_P(MODE) \
993 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
994 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \
995 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
996
997 #define VALID_FP_MODE_P(MODE) \
998 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
999 || (!TARGET_64BIT && (MODE) == XFmode) \
1000 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \
1001 || (!TARGET_64BIT && (MODE) == XCmode))
1002
1003 #define VALID_INT_MODE_P(MODE) \
1004 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1005 || (MODE) == DImode \
1006 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1007 || (MODE) == CDImode \
1008 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode)))
1009
1010 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1011
1012 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1013 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1014
1015 /* Value is 1 if it is a good idea to tie two pseudo registers
1016 when one has mode MODE1 and one has mode MODE2.
1017 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1018 for any hard reg, then this must be 0 for correct output. */
1019
1020 #define MODES_TIEABLE_P(MODE1, MODE2) \
1021 ((MODE1) == (MODE2) \
1022 || (((MODE1) == HImode || (MODE1) == SImode \
1023 || ((MODE1) == QImode \
1024 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1025 || ((MODE1) == DImode && TARGET_64BIT)) \
1026 && ((MODE2) == HImode || (MODE2) == SImode \
1027 || ((MODE1) == QImode \
1028 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1029 || ((MODE2) == DImode && TARGET_64BIT))))
1030
1031
1032 /* Specify the modes required to caller save a given hard regno.
1033 We do this on i386 to prevent flags from being saved at all.
1034
1035 Kill any attempts to combine saving of modes. */
1036
1037 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1038 (CC_REGNO_P (REGNO) ? VOIDmode \
1039 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1040 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \
1041 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1042 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1043 : (MODE))
1044 /* Specify the registers used for certain standard purposes.
1045 The values of these macros are register numbers. */
1046
1047 /* on the 386 the pc register is %eip, and is not usable as a general
1048 register. The ordinary mov instructions won't work */
1049 /* #define PC_REGNUM */
1050
1051 /* Register to use for pushing function arguments. */
1052 #define STACK_POINTER_REGNUM 7
1053
1054 /* Base register for access to local variables of the function. */
1055 #define HARD_FRAME_POINTER_REGNUM 6
1056
1057 /* Base register for access to local variables of the function. */
1058 #define FRAME_POINTER_REGNUM 20
1059
1060 /* First floating point reg */
1061 #define FIRST_FLOAT_REG 8
1062
1063 /* First & last stack-like regs */
1064 #define FIRST_STACK_REG FIRST_FLOAT_REG
1065 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1066
1067 #define FLAGS_REG 17
1068 #define FPSR_REG 18
1069 #define DIRFLAG_REG 19
1070
1071 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1072 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1073
1074 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1075 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1076
1077 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1078 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1079
1080 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1081 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1082
1083 /* Value should be nonzero if functions must have frame pointers.
1084 Zero means the frame pointer need not be set up (and parms
1085 may be accessed via the stack pointer) in functions that seem suitable.
1086 This is computed in `reload', in reload1.c. */
1087 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1088
1089 /* Override this in other tm.h files to cope with various OS losage
1090 requiring a frame pointer. */
1091 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1092 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1093 #endif
1094
1095 /* Make sure we can access arbitrary call frames. */
1096 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1097
1098 /* Base register for access to arguments of the function. */
1099 #define ARG_POINTER_REGNUM 16
1100
1101 /* Register in which static-chain is passed to a function.
1102 We do use ECX as static chain register for 32 bit ABI. On the
1103 64bit ABI, ECX is an argument register, so we use R10 instead. */
1104 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1105
1106 /* Register to hold the addressing base for position independent
1107 code access to data items. We don't use PIC pointer for 64bit
1108 mode. Define the regnum to dummy value to prevent gcc from
1109 pessimizing code dealing with EBX. */
1110 #define PIC_OFFSET_TABLE_REGNUM \
1111 (TARGET_64BIT || !flag_pic ? INVALID_REGNUM : 3)
1112
1113 /* Register in which address to store a structure value
1114 arrives in the function. On the 386, the prologue
1115 copies this from the stack to register %eax. */
1116 #define STRUCT_VALUE_INCOMING 0
1117
1118 /* Place in which caller passes the structure value address.
1119 0 means push the value on the stack like an argument. */
1120 #define STRUCT_VALUE 0
1121
1122 /* A C expression which can inhibit the returning of certain function
1123 values in registers, based on the type of value. A nonzero value
1124 says to return the function value in memory, just as large
1125 structures are always returned. Here TYPE will be a C expression
1126 of type `tree', representing the data type of the value.
1127
1128 Note that values of mode `BLKmode' must be explicitly handled by
1129 this macro. Also, the option `-fpcc-struct-return' takes effect
1130 regardless of this macro. On most systems, it is possible to
1131 leave the macro undefined; this causes a default definition to be
1132 used, whose value is the constant 1 for `BLKmode' values, and 0
1133 otherwise.
1134
1135 Do not use this macro to indicate that structures and unions
1136 should always be returned in memory. You should instead use
1137 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1138
1139 #define RETURN_IN_MEMORY(TYPE) \
1140 ix86_return_in_memory (TYPE)
1141
1142 \f
1143 /* Define the classes of registers for register constraints in the
1144 machine description. Also define ranges of constants.
1145
1146 One of the classes must always be named ALL_REGS and include all hard regs.
1147 If there is more than one class, another class must be named NO_REGS
1148 and contain no registers.
1149
1150 The name GENERAL_REGS must be the name of a class (or an alias for
1151 another name such as ALL_REGS). This is the class of registers
1152 that is allowed by "g" or "r" in a register constraint.
1153 Also, registers outside this class are allocated only when
1154 instructions express preferences for them.
1155
1156 The classes must be numbered in nondecreasing order; that is,
1157 a larger-numbered class must never be contained completely
1158 in a smaller-numbered class.
1159
1160 For any two classes, it is very desirable that there be another
1161 class that represents their union.
1162
1163 It might seem that class BREG is unnecessary, since no useful 386
1164 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1165 and the "b" register constraint is useful in asms for syscalls.
1166
1167 The flags and fpsr registers are in no class. */
1168
1169 enum reg_class
1170 {
1171 NO_REGS,
1172 AREG, DREG, CREG, BREG, SIREG, DIREG,
1173 AD_REGS, /* %eax/%edx for DImode */
1174 Q_REGS, /* %eax %ebx %ecx %edx */
1175 NON_Q_REGS, /* %esi %edi %ebp %esp */
1176 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1177 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1178 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1179 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1180 FLOAT_REGS,
1181 SSE_REGS,
1182 MMX_REGS,
1183 FP_TOP_SSE_REGS,
1184 FP_SECOND_SSE_REGS,
1185 FLOAT_SSE_REGS,
1186 FLOAT_INT_REGS,
1187 INT_SSE_REGS,
1188 FLOAT_INT_SSE_REGS,
1189 ALL_REGS, LIM_REG_CLASSES
1190 };
1191
1192 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1193
1194 #define INTEGER_CLASS_P(CLASS) \
1195 reg_class_subset_p ((CLASS), GENERAL_REGS)
1196 #define FLOAT_CLASS_P(CLASS) \
1197 reg_class_subset_p ((CLASS), FLOAT_REGS)
1198 #define SSE_CLASS_P(CLASS) \
1199 reg_class_subset_p ((CLASS), SSE_REGS)
1200 #define MMX_CLASS_P(CLASS) \
1201 reg_class_subset_p ((CLASS), MMX_REGS)
1202 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1203 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1204 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1205 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1206 #define MAYBE_SSE_CLASS_P(CLASS) \
1207 reg_classes_intersect_p (SSE_REGS, (CLASS))
1208 #define MAYBE_MMX_CLASS_P(CLASS) \
1209 reg_classes_intersect_p (MMX_REGS, (CLASS))
1210
1211 #define Q_CLASS_P(CLASS) \
1212 reg_class_subset_p ((CLASS), Q_REGS)
1213
1214 /* Give names of register classes as strings for dump file. */
1215
1216 #define REG_CLASS_NAMES \
1217 { "NO_REGS", \
1218 "AREG", "DREG", "CREG", "BREG", \
1219 "SIREG", "DIREG", \
1220 "AD_REGS", \
1221 "Q_REGS", "NON_Q_REGS", \
1222 "INDEX_REGS", \
1223 "LEGACY_REGS", \
1224 "GENERAL_REGS", \
1225 "FP_TOP_REG", "FP_SECOND_REG", \
1226 "FLOAT_REGS", \
1227 "SSE_REGS", \
1228 "MMX_REGS", \
1229 "FP_TOP_SSE_REGS", \
1230 "FP_SECOND_SSE_REGS", \
1231 "FLOAT_SSE_REGS", \
1232 "FLOAT_INT_REGS", \
1233 "INT_SSE_REGS", \
1234 "FLOAT_INT_SSE_REGS", \
1235 "ALL_REGS" }
1236
1237 /* Define which registers fit in which classes.
1238 This is an initializer for a vector of HARD_REG_SET
1239 of length N_REG_CLASSES. */
1240
1241 #define REG_CLASS_CONTENTS \
1242 { { 0x00, 0x0 }, \
1243 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1244 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1245 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1246 { 0x03, 0x0 }, /* AD_REGS */ \
1247 { 0x0f, 0x0 }, /* Q_REGS */ \
1248 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1249 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1250 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1251 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1252 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1253 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1254 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1255 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1256 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1257 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1258 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1259 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1260 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1261 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1262 { 0xffffffff,0x1fffff } \
1263 }
1264
1265 /* The same information, inverted:
1266 Return the class number of the smallest class containing
1267 reg number REGNO. This could be a conditional expression
1268 or could index an array. */
1269
1270 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1271
1272 /* When defined, the compiler allows registers explicitly used in the
1273 rtl to be used as spill registers but prevents the compiler from
1274 extending the lifetime of these registers. */
1275
1276 #define SMALL_REGISTER_CLASSES 1
1277
1278 #define QI_REG_P(X) \
1279 (REG_P (X) && REGNO (X) < 4)
1280
1281 #define GENERAL_REGNO_P(N) \
1282 ((N) < 8 || REX_INT_REGNO_P (N))
1283
1284 #define GENERAL_REG_P(X) \
1285 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1286
1287 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1288
1289 #define NON_QI_REG_P(X) \
1290 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1291
1292 #define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
1293 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1294
1295 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1296 #define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
1297 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1298 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1299
1300 #define SSE_REGNO_P(N) \
1301 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
1302 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
1303
1304 #define SSE_REGNO(N) \
1305 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1306 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1307
1308 #define SSE_FLOAT_MODE_P(MODE) \
1309 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1310
1311 #define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
1312 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1313
1314 #define STACK_REG_P(XOP) \
1315 (REG_P (XOP) && \
1316 REGNO (XOP) >= FIRST_STACK_REG && \
1317 REGNO (XOP) <= LAST_STACK_REG)
1318
1319 #define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
1320
1321 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1322
1323 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1324 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1325
1326 /* Indicate whether hard register numbered REG_NO should be converted
1327 to SSA form. */
1328 #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \
1329 ((REG_NO) == FLAGS_REG || (REG_NO) == ARG_POINTER_REGNUM)
1330
1331 /* The class value for index registers, and the one for base regs. */
1332
1333 #define INDEX_REG_CLASS INDEX_REGS
1334 #define BASE_REG_CLASS GENERAL_REGS
1335
1336 /* Get reg_class from a letter such as appears in the machine description. */
1337
1338 #define REG_CLASS_FROM_LETTER(C) \
1339 ((C) == 'r' ? GENERAL_REGS : \
1340 (C) == 'R' ? LEGACY_REGS : \
1341 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1342 (C) == 'Q' ? Q_REGS : \
1343 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1344 ? FLOAT_REGS \
1345 : NO_REGS) : \
1346 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1347 ? FP_TOP_REG \
1348 : NO_REGS) : \
1349 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1350 ? FP_SECOND_REG \
1351 : NO_REGS) : \
1352 (C) == 'a' ? AREG : \
1353 (C) == 'b' ? BREG : \
1354 (C) == 'c' ? CREG : \
1355 (C) == 'd' ? DREG : \
1356 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1357 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1358 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1359 (C) == 'A' ? AD_REGS : \
1360 (C) == 'D' ? DIREG : \
1361 (C) == 'S' ? SIREG : NO_REGS)
1362
1363 /* The letters I, J, K, L and M in a register constraint string
1364 can be used to stand for particular ranges of immediate operands.
1365 This macro defines what the ranges are.
1366 C is the letter, and VALUE is a constant value.
1367 Return 1 if VALUE is in the range specified by C.
1368
1369 I is for non-DImode shifts.
1370 J is for DImode shifts.
1371 K is for signed imm8 operands.
1372 L is for andsi as zero-extending move.
1373 M is for shifts that can be executed by the "lea" opcode.
1374 N is for immedaite operands for out/in instructions (0-255)
1375 */
1376
1377 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1378 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1379 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1380 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1381 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1382 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1383 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1384 : 0)
1385
1386 /* Similar, but for floating constants, and defining letters G and H.
1387 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1388 TARGET_387 isn't set, because the stack register converter may need to
1389 load 0.0 into the function value register. */
1390
1391 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1392 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1393 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0))
1394
1395 /* A C expression that defines the optional machine-dependent
1396 constraint letters that can be used to segregate specific types of
1397 operands, usually memory references, for the target machine. Any
1398 letter that is not elsewhere defined and not matched by
1399 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1400 be defined.
1401
1402 If it is required for a particular target machine, it should
1403 return 1 if VALUE corresponds to the operand type represented by
1404 the constraint letter C. If C is not defined as an extra
1405 constraint, the value returned should be 0 regardless of VALUE. */
1406
1407 #define EXTRA_CONSTRAINT(VALUE, C) \
1408 ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \
1409 : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \
1410 : 0)
1411
1412 /* Place additional restrictions on the register class to use when it
1413 is necessary to be able to hold a value of mode MODE in a reload
1414 register for which class CLASS would ordinarily be used. */
1415
1416 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1417 ((MODE) == QImode && !TARGET_64BIT \
1418 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1419 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1420 ? Q_REGS : (CLASS))
1421
1422 /* Given an rtx X being reloaded into a reg required to be
1423 in class CLASS, return the class of reg to actually use.
1424 In general this is just CLASS; but on some machines
1425 in some cases it is preferable to use a more restrictive class.
1426 On the 80386 series, we prevent floating constants from being
1427 reloaded into floating registers (since no move-insn can do that)
1428 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1429
1430 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1431 QImode must go into class Q_REGS.
1432 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1433 movdf to do mem-to-mem moves through integer regs. */
1434
1435 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1436 ix86_preferred_reload_class ((X), (CLASS))
1437
1438 /* If we are copying between general and FP registers, we need a memory
1439 location. The same is true for SSE and MMX registers. */
1440 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1441 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1442
1443 /* QImode spills from non-QI registers need a scratch. This does not
1444 happen often -- the only example so far requires an uninitialized
1445 pseudo. */
1446
1447 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1448 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1449 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1450 ? Q_REGS : NO_REGS)
1451
1452 /* Return the maximum number of consecutive registers
1453 needed to represent mode MODE in a register of class CLASS. */
1454 /* On the 80386, this is the size of MODE in words,
1455 except in the FP regs, where a single reg is always enough.
1456 The TFmodes are really just 80bit values, so we use only 3 registers
1457 to hold them, instead of 4, as the size would suggest.
1458 */
1459 #define CLASS_MAX_NREGS(CLASS, MODE) \
1460 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1461 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1462 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \
1463 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1464
1465 /* A C expression whose value is nonzero if pseudos that have been
1466 assigned to registers of class CLASS would likely be spilled
1467 because registers of CLASS are needed for spill registers.
1468
1469 The default value of this macro returns 1 if CLASS has exactly one
1470 register and zero otherwise. On most machines, this default
1471 should be used. Only define this macro to some other expression
1472 if pseudo allocated by `local-alloc.c' end up in memory because
1473 their hard registers were needed for spill registers. If this
1474 macro returns nonzero for those classes, those pseudos will only
1475 be allocated by `global.c', which knows how to reallocate the
1476 pseudo to another register. If there would not be another
1477 register available for reallocation, you should not change the
1478 definition of this macro since the only effect of such a
1479 definition would be to slow down register allocation. */
1480
1481 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1482 (((CLASS) == AREG) \
1483 || ((CLASS) == DREG) \
1484 || ((CLASS) == CREG) \
1485 || ((CLASS) == BREG) \
1486 || ((CLASS) == AD_REGS) \
1487 || ((CLASS) == SIREG) \
1488 || ((CLASS) == DIREG))
1489
1490 /* A C statement that adds to CLOBBERS any hard regs the port wishes
1491 to automatically clobber for all asms.
1492
1493 We do this in the new i386 backend to maintain source compatibility
1494 with the old cc0-based compiler. */
1495
1496 #define MD_ASM_CLOBBERS(CLOBBERS) \
1497 do { \
1498 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \
1499 (CLOBBERS)); \
1500 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \
1501 (CLOBBERS)); \
1502 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \
1503 (CLOBBERS)); \
1504 } while (0)
1505 \f
1506 /* Stack layout; function entry, exit and calling. */
1507
1508 /* Define this if pushing a word on the stack
1509 makes the stack pointer a smaller address. */
1510 #define STACK_GROWS_DOWNWARD
1511
1512 /* Define this if the nominal address of the stack frame
1513 is at the high-address end of the local variables;
1514 that is, each additional local variable allocated
1515 goes at a more negative offset in the frame. */
1516 #define FRAME_GROWS_DOWNWARD
1517
1518 /* Offset within stack frame to start allocating local variables at.
1519 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1520 first local allocated. Otherwise, it is the offset to the BEGINNING
1521 of the first local allocated. */
1522 #define STARTING_FRAME_OFFSET 0
1523
1524 /* If we generate an insn to push BYTES bytes,
1525 this says how many the stack pointer really advances by.
1526 On 386 pushw decrements by exactly 2 no matter what the position was.
1527 On the 386 there is no pushb; we use pushw instead, and this
1528 has the effect of rounding up to 2.
1529
1530 For 64bit ABI we round up to 8 bytes.
1531 */
1532
1533 #define PUSH_ROUNDING(BYTES) \
1534 (TARGET_64BIT \
1535 ? (((BYTES) + 7) & (-8)) \
1536 : (((BYTES) + 1) & (-2)))
1537
1538 /* If defined, the maximum amount of space required for outgoing arguments will
1539 be computed and placed into the variable
1540 `current_function_outgoing_args_size'. No space will be pushed onto the
1541 stack for each call; instead, the function prologue should increase the stack
1542 frame size by this amount. */
1543
1544 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1545
1546 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1547 instructions to pass outgoing arguments. */
1548
1549 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1550
1551 /* Offset of first parameter from the argument pointer register value. */
1552 #define FIRST_PARM_OFFSET(FNDECL) 0
1553
1554 /* Define this macro if functions should assume that stack space has been
1555 allocated for arguments even when their values are passed in registers.
1556
1557 The value of this macro is the size, in bytes, of the area reserved for
1558 arguments passed in registers for the function represented by FNDECL.
1559
1560 This space can be allocated by the caller, or be a part of the
1561 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1562 which. */
1563 #define REG_PARM_STACK_SPACE(FNDECL) 0
1564
1565 /* Define as a C expression that evaluates to nonzero if we do not know how
1566 to pass TYPE solely in registers. The file expr.h defines a
1567 definition that is usually appropriate, refer to expr.h for additional
1568 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
1569 computed in the stack and then loaded into a register. */
1570 #define MUST_PASS_IN_STACK(MODE, TYPE) \
1571 ((TYPE) != 0 \
1572 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1573 || TREE_ADDRESSABLE (TYPE) \
1574 || ((MODE) == TImode) \
1575 || ((MODE) == BLKmode \
1576 && ! ((TYPE) != 0 \
1577 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
1578 && 0 == (int_size_in_bytes (TYPE) \
1579 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
1580 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
1581 == (BYTES_BIG_ENDIAN ? upward : downward)))))
1582
1583 /* Value is the number of bytes of arguments automatically
1584 popped when returning from a subroutine call.
1585 FUNDECL is the declaration node of the function (as a tree),
1586 FUNTYPE is the data type of the function (as a tree),
1587 or for a library call it is an identifier node for the subroutine name.
1588 SIZE is the number of bytes of arguments passed on the stack.
1589
1590 On the 80386, the RTD insn may be used to pop them if the number
1591 of args is fixed, but if the number is variable then the caller
1592 must pop them all. RTD can't be used for library calls now
1593 because the library is compiled with the Unix compiler.
1594 Use of RTD is a selectable option, since it is incompatible with
1595 standard Unix calling sequences. If the option is not selected,
1596 the caller must always pop the args.
1597
1598 The attribute stdcall is equivalent to RTD on a per module basis. */
1599
1600 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1601 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1602
1603 /* Define how to find the value returned by a function.
1604 VALTYPE is the data type of the value (as a tree).
1605 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1606 otherwise, FUNC is 0. */
1607 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1608 ix86_function_value (VALTYPE)
1609
1610 #define FUNCTION_VALUE_REGNO_P(N) \
1611 ix86_function_value_regno_p (N)
1612
1613 /* Define how to find the value returned by a library function
1614 assuming the value has mode MODE. */
1615
1616 #define LIBCALL_VALUE(MODE) \
1617 ix86_libcall_value (MODE)
1618
1619 /* Define the size of the result block used for communication between
1620 untyped_call and untyped_return. The block contains a DImode value
1621 followed by the block used by fnsave and frstor. */
1622
1623 #define APPLY_RESULT_SIZE (8+108)
1624
1625 /* 1 if N is a possible register number for function argument passing. */
1626 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1627
1628 /* Define a data type for recording info about an argument list
1629 during the scan of that argument list. This data type should
1630 hold all necessary information about the function itself
1631 and about the args processed so far, enough to enable macros
1632 such as FUNCTION_ARG to determine where the next arg should go. */
1633
1634 typedef struct ix86_args {
1635 int words; /* # words passed so far */
1636 int nregs; /* # registers available for passing */
1637 int regno; /* next available register number */
1638 int sse_words; /* # sse words passed so far */
1639 int sse_nregs; /* # sse registers available for passing */
1640 int sse_regno; /* next available sse register number */
1641 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1642 } CUMULATIVE_ARGS;
1643
1644 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1645 for a call to a function whose data type is FNTYPE.
1646 For a library call, FNTYPE is 0. */
1647
1648 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1649 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME))
1650
1651 /* Update the data in CUM to advance over an argument
1652 of mode MODE and data type TYPE.
1653 (TYPE is null for libcalls where that information may not be available.) */
1654
1655 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1656 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1657
1658 /* Define where to put the arguments to a function.
1659 Value is zero to push the argument on the stack,
1660 or a hard register in which to store the argument.
1661
1662 MODE is the argument's machine mode.
1663 TYPE is the data type of the argument (as a tree).
1664 This is null for libcalls where that information may
1665 not be available.
1666 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1667 the preceding args and about the function being called.
1668 NAMED is nonzero if this argument is a named parameter
1669 (otherwise it is an extra parameter matching an ellipsis). */
1670
1671 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1672 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1673
1674 /* For an arg passed partly in registers and partly in memory,
1675 this is the number of registers used.
1676 For args passed entirely in registers or entirely in memory, zero. */
1677
1678 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1679
1680 /* If PIC, we cannot make sibling calls to global functions
1681 because the PLT requires %ebx live.
1682 If we are returning floats on the register stack, we cannot make
1683 sibling calls to functions that return floats. (The stack adjust
1684 instruction will wind up after the sibcall jump, and not be executed.) */
1685 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1686 ((DECL) \
1687 && (! flag_pic || ! TREE_PUBLIC (DECL)) \
1688 && (! TARGET_FLOAT_RETURNS_IN_80387 \
1689 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \
1690 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl))))))
1691
1692 /* Perform any needed actions needed for a function that is receiving a
1693 variable number of arguments.
1694
1695 CUM is as above.
1696
1697 MODE and TYPE are the mode and type of the current parameter.
1698
1699 PRETEND_SIZE is a variable that should be set to the amount of stack
1700 that must be pushed by the prolog to pretend that our caller pushed
1701 it.
1702
1703 Normally, this macro will push all remaining incoming registers on the
1704 stack and set PRETEND_SIZE to the length of the registers pushed. */
1705
1706 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1707 ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \
1708 (NO_RTL))
1709
1710 /* Define the `__builtin_va_list' type for the ABI. */
1711 #define BUILD_VA_LIST_TYPE(VALIST) \
1712 ((VALIST) = ix86_build_va_list ())
1713
1714 /* Implement `va_start' for varargs and stdarg. */
1715 #define EXPAND_BUILTIN_VA_START(STDARG, VALIST, NEXTARG) \
1716 ix86_va_start ((STDARG), (VALIST), (NEXTARG))
1717
1718 /* Implement `va_arg'. */
1719 #define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \
1720 ix86_va_arg ((VALIST), (TYPE))
1721
1722 /* This macro is invoked at the end of compilation. It is used here to
1723 output code for -fpic that will load the return address into %ebx. */
1724
1725 #undef ASM_FILE_END
1726 #define ASM_FILE_END(FILE) ix86_asm_file_end (FILE)
1727
1728 /* Output assembler code to FILE to increment profiler label # LABELNO
1729 for profiling a function entry. */
1730
1731 #define FUNCTION_PROFILER(FILE, LABELNO) \
1732 do { \
1733 if (flag_pic) \
1734 { \
1735 fprintf ((FILE), "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \
1736 LPREFIX, (LABELNO)); \
1737 fprintf ((FILE), "\tcall\t*_mcount@GOT(%%ebx)\n"); \
1738 } \
1739 else \
1740 { \
1741 fprintf ((FILE), "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
1742 fprintf ((FILE), "\tcall\t_mcount\n"); \
1743 } \
1744 } while (0)
1745
1746 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1747 the stack pointer does not matter. The value is tested only in
1748 functions that have frame pointers.
1749 No definition is equivalent to always zero. */
1750 /* Note on the 386 it might be more efficient not to define this since
1751 we have to restore it ourselves from the frame pointer, in order to
1752 use pop */
1753
1754 #define EXIT_IGNORE_STACK 1
1755
1756 /* Output assembler code for a block containing the constant parts
1757 of a trampoline, leaving space for the variable parts. */
1758
1759 /* On the 386, the trampoline contains two instructions:
1760 mov #STATIC,ecx
1761 jmp FUNCTION
1762 The trampoline is generated entirely at runtime. The operand of JMP
1763 is the address of FUNCTION relative to the instruction following the
1764 JMP (which is 5 bytes long). */
1765
1766 /* Length in units of the trampoline for entering a nested function. */
1767
1768 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1769
1770 /* Emit RTL insns to initialize the variable parts of a trampoline.
1771 FNADDR is an RTX for the address of the function's pure code.
1772 CXT is an RTX for the static chain value for the function. */
1773
1774 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1775 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1776 \f
1777 /* Definitions for register eliminations.
1778
1779 This is an array of structures. Each structure initializes one pair
1780 of eliminable registers. The "from" register number is given first,
1781 followed by "to". Eliminations of the same "from" register are listed
1782 in order of preference.
1783
1784 There are two registers that can always be eliminated on the i386.
1785 The frame pointer and the arg pointer can be replaced by either the
1786 hard frame pointer or to the stack pointer, depending upon the
1787 circumstances. The hard frame pointer is not used before reload and
1788 so it is not eligible for elimination. */
1789
1790 #define ELIMINABLE_REGS \
1791 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1792 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1793 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1794 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1795
1796 /* Given FROM and TO register numbers, say whether this elimination is
1797 allowed. Frame pointer elimination is automatically handled.
1798
1799 All other eliminations are valid. */
1800
1801 #define CAN_ELIMINATE(FROM, TO) \
1802 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1803
1804 /* Define the offset between two registers, one to be eliminated, and the other
1805 its replacement, at the start of a routine. */
1806
1807 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1808 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1809 \f
1810 /* Addressing modes, and classification of registers for them. */
1811
1812 /* #define HAVE_POST_INCREMENT 0 */
1813 /* #define HAVE_POST_DECREMENT 0 */
1814
1815 /* #define HAVE_PRE_DECREMENT 0 */
1816 /* #define HAVE_PRE_INCREMENT 0 */
1817
1818 /* Macros to check register numbers against specific register classes. */
1819
1820 /* These assume that REGNO is a hard or pseudo reg number.
1821 They give nonzero only if REGNO is a hard reg of the suitable class
1822 or a pseudo reg currently allocated to a suitable hard reg.
1823 Since they use reg_renumber, they are safe only once reg_renumber
1824 has been allocated, which happens in local-alloc.c. */
1825
1826 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1827 ((REGNO) < STACK_POINTER_REGNUM \
1828 || (REGNO >= FIRST_REX_INT_REG \
1829 && (REGNO) <= LAST_REX_INT_REG) \
1830 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1831 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1832 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
1833
1834 #define REGNO_OK_FOR_BASE_P(REGNO) \
1835 ((REGNO) <= STACK_POINTER_REGNUM \
1836 || (REGNO) == ARG_POINTER_REGNUM \
1837 || (REGNO) == FRAME_POINTER_REGNUM \
1838 || (REGNO >= FIRST_REX_INT_REG \
1839 && (REGNO) <= LAST_REX_INT_REG) \
1840 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1841 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1842 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
1843
1844 #define REGNO_OK_FOR_SIREG_P(REGNO) \
1845 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1846 #define REGNO_OK_FOR_DIREG_P(REGNO) \
1847 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1848
1849 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1850 and check its validity for a certain class.
1851 We have two alternate definitions for each of them.
1852 The usual definition accepts all pseudo regs; the other rejects
1853 them unless they have been allocated suitable hard regs.
1854 The symbol REG_OK_STRICT causes the latter definition to be used.
1855
1856 Most source files want to accept pseudo regs in the hope that
1857 they will get allocated to the class that the insn wants them to be in.
1858 Source files for reload pass need to be strict.
1859 After reload, it makes no difference, since pseudo regs have
1860 been eliminated by then. */
1861
1862
1863 /* Non strict versions, pseudos are ok */
1864 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1865 (REGNO (X) < STACK_POINTER_REGNUM \
1866 || (REGNO (X) >= FIRST_REX_INT_REG \
1867 && REGNO (X) <= LAST_REX_INT_REG) \
1868 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1869
1870 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1871 (REGNO (X) <= STACK_POINTER_REGNUM \
1872 || REGNO (X) == ARG_POINTER_REGNUM \
1873 || REGNO (X) == FRAME_POINTER_REGNUM \
1874 || (REGNO (X) >= FIRST_REX_INT_REG \
1875 && REGNO (X) <= LAST_REX_INT_REG) \
1876 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1877
1878 /* Strict versions, hard registers only */
1879 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1880 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1881
1882 #ifndef REG_OK_STRICT
1883 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1884 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1885
1886 #else
1887 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1888 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1889 #endif
1890
1891 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1892 that is a valid memory address for an instruction.
1893 The MODE argument is the machine mode for the MEM expression
1894 that wants to use this address.
1895
1896 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1897 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1898
1899 See legitimize_pic_address in i386.c for details as to what
1900 constitutes a legitimate address when -fpic is used. */
1901
1902 #define MAX_REGS_PER_ADDRESS 2
1903
1904 #define CONSTANT_ADDRESS_P(X) \
1905 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1906 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1907 || GET_CODE (X) == CONST_DOUBLE)
1908
1909 /* Nonzero if the constant value X is a legitimate general operand.
1910 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1911
1912 #define LEGITIMATE_CONSTANT_P(X) 1
1913
1914 #ifdef REG_OK_STRICT
1915 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1916 do { \
1917 if (legitimate_address_p ((MODE), (X), 1)) \
1918 goto ADDR; \
1919 } while (0)
1920
1921 #else
1922 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1923 do { \
1924 if (legitimate_address_p ((MODE), (X), 0)) \
1925 goto ADDR; \
1926 } while (0)
1927
1928 #endif
1929
1930 /* If defined, a C expression to determine the base term of address X.
1931 This macro is used in only one place: `find_base_term' in alias.c.
1932
1933 It is always safe for this macro to not be defined. It exists so
1934 that alias analysis can understand machine-dependent addresses.
1935
1936 The typical use of this macro is to handle addresses containing
1937 a label_ref or symbol_ref within an UNSPEC. */
1938
1939 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1940
1941 /* Try machine-dependent ways of modifying an illegitimate address
1942 to be legitimate. If we find one, return the new, valid address.
1943 This macro is used in only one place: `memory_address' in explow.c.
1944
1945 OLDX is the address as it was before break_out_memory_refs was called.
1946 In some cases it is useful to look at this to decide what needs to be done.
1947
1948 MODE and WIN are passed so that this macro can use
1949 GO_IF_LEGITIMATE_ADDRESS.
1950
1951 It is always safe for this macro to do nothing. It exists to recognize
1952 opportunities to optimize the output.
1953
1954 For the 80386, we handle X+REG by loading X into a register R and
1955 using R+REG. R will go in a general reg and indexing will be used.
1956 However, if REG is a broken-out memory address or multiplication,
1957 nothing needs to be done because REG can certainly go in a general reg.
1958
1959 When -fpic is used, special handling is needed for symbolic references.
1960 See comments by legitimize_pic_address in i386.c for details. */
1961
1962 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1963 do { \
1964 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1965 if (memory_address_p ((MODE), (X))) \
1966 goto WIN; \
1967 } while (0)
1968
1969 #define REWRITE_ADDRESS(X) rewrite_address (X)
1970
1971 /* Nonzero if the constant value X is a legitimate general operand
1972 when generating PIC code. It is given that flag_pic is on and
1973 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1974
1975 #define LEGITIMATE_PIC_OPERAND_P(X) \
1976 (! SYMBOLIC_CONST (X) \
1977 || legitimate_pic_address_disp_p (X))
1978
1979 #define SYMBOLIC_CONST(X) \
1980 (GET_CODE (X) == SYMBOL_REF \
1981 || GET_CODE (X) == LABEL_REF \
1982 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1983
1984 /* Go to LABEL if ADDR (a legitimate address expression)
1985 has an effect that depends on the machine mode it is used for.
1986 On the 80386, only postdecrement and postincrement address depend thus
1987 (the amount of decrement or increment being the length of the operand). */
1988 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1989 do { \
1990 if (GET_CODE (ADDR) == POST_INC \
1991 || GET_CODE (ADDR) == POST_DEC) \
1992 goto LABEL; \
1993 } while (0)
1994 \f
1995 /* Codes for all the SSE/MMX builtins. */
1996 enum ix86_builtins
1997 {
1998 IX86_BUILTIN_ADDPS,
1999 IX86_BUILTIN_ADDSS,
2000 IX86_BUILTIN_DIVPS,
2001 IX86_BUILTIN_DIVSS,
2002 IX86_BUILTIN_MULPS,
2003 IX86_BUILTIN_MULSS,
2004 IX86_BUILTIN_SUBPS,
2005 IX86_BUILTIN_SUBSS,
2006
2007 IX86_BUILTIN_CMPEQPS,
2008 IX86_BUILTIN_CMPLTPS,
2009 IX86_BUILTIN_CMPLEPS,
2010 IX86_BUILTIN_CMPGTPS,
2011 IX86_BUILTIN_CMPGEPS,
2012 IX86_BUILTIN_CMPNEQPS,
2013 IX86_BUILTIN_CMPNLTPS,
2014 IX86_BUILTIN_CMPNLEPS,
2015 IX86_BUILTIN_CMPNGTPS,
2016 IX86_BUILTIN_CMPNGEPS,
2017 IX86_BUILTIN_CMPORDPS,
2018 IX86_BUILTIN_CMPUNORDPS,
2019 IX86_BUILTIN_CMPNEPS,
2020 IX86_BUILTIN_CMPEQSS,
2021 IX86_BUILTIN_CMPLTSS,
2022 IX86_BUILTIN_CMPLESS,
2023 IX86_BUILTIN_CMPGTSS,
2024 IX86_BUILTIN_CMPGESS,
2025 IX86_BUILTIN_CMPNEQSS,
2026 IX86_BUILTIN_CMPNLTSS,
2027 IX86_BUILTIN_CMPNLESS,
2028 IX86_BUILTIN_CMPNGTSS,
2029 IX86_BUILTIN_CMPNGESS,
2030 IX86_BUILTIN_CMPORDSS,
2031 IX86_BUILTIN_CMPUNORDSS,
2032 IX86_BUILTIN_CMPNESS,
2033
2034 IX86_BUILTIN_COMIEQSS,
2035 IX86_BUILTIN_COMILTSS,
2036 IX86_BUILTIN_COMILESS,
2037 IX86_BUILTIN_COMIGTSS,
2038 IX86_BUILTIN_COMIGESS,
2039 IX86_BUILTIN_COMINEQSS,
2040 IX86_BUILTIN_UCOMIEQSS,
2041 IX86_BUILTIN_UCOMILTSS,
2042 IX86_BUILTIN_UCOMILESS,
2043 IX86_BUILTIN_UCOMIGTSS,
2044 IX86_BUILTIN_UCOMIGESS,
2045 IX86_BUILTIN_UCOMINEQSS,
2046
2047 IX86_BUILTIN_CVTPI2PS,
2048 IX86_BUILTIN_CVTPS2PI,
2049 IX86_BUILTIN_CVTSI2SS,
2050 IX86_BUILTIN_CVTSS2SI,
2051 IX86_BUILTIN_CVTTPS2PI,
2052 IX86_BUILTIN_CVTTSS2SI,
2053
2054 IX86_BUILTIN_MAXPS,
2055 IX86_BUILTIN_MAXSS,
2056 IX86_BUILTIN_MINPS,
2057 IX86_BUILTIN_MINSS,
2058
2059 IX86_BUILTIN_LOADAPS,
2060 IX86_BUILTIN_LOADUPS,
2061 IX86_BUILTIN_STOREAPS,
2062 IX86_BUILTIN_STOREUPS,
2063 IX86_BUILTIN_LOADSS,
2064 IX86_BUILTIN_STORESS,
2065 IX86_BUILTIN_MOVSS,
2066
2067 IX86_BUILTIN_MOVHLPS,
2068 IX86_BUILTIN_MOVLHPS,
2069 IX86_BUILTIN_LOADHPS,
2070 IX86_BUILTIN_LOADLPS,
2071 IX86_BUILTIN_STOREHPS,
2072 IX86_BUILTIN_STORELPS,
2073
2074 IX86_BUILTIN_MASKMOVQ,
2075 IX86_BUILTIN_MOVMSKPS,
2076 IX86_BUILTIN_PMOVMSKB,
2077
2078 IX86_BUILTIN_MOVNTPS,
2079 IX86_BUILTIN_MOVNTQ,
2080
2081 IX86_BUILTIN_PACKSSWB,
2082 IX86_BUILTIN_PACKSSDW,
2083 IX86_BUILTIN_PACKUSWB,
2084
2085 IX86_BUILTIN_PADDB,
2086 IX86_BUILTIN_PADDW,
2087 IX86_BUILTIN_PADDD,
2088 IX86_BUILTIN_PADDSB,
2089 IX86_BUILTIN_PADDSW,
2090 IX86_BUILTIN_PADDUSB,
2091 IX86_BUILTIN_PADDUSW,
2092 IX86_BUILTIN_PSUBB,
2093 IX86_BUILTIN_PSUBW,
2094 IX86_BUILTIN_PSUBD,
2095 IX86_BUILTIN_PSUBSB,
2096 IX86_BUILTIN_PSUBSW,
2097 IX86_BUILTIN_PSUBUSB,
2098 IX86_BUILTIN_PSUBUSW,
2099
2100 IX86_BUILTIN_PAND,
2101 IX86_BUILTIN_PANDN,
2102 IX86_BUILTIN_POR,
2103 IX86_BUILTIN_PXOR,
2104
2105 IX86_BUILTIN_PAVGB,
2106 IX86_BUILTIN_PAVGW,
2107
2108 IX86_BUILTIN_PCMPEQB,
2109 IX86_BUILTIN_PCMPEQW,
2110 IX86_BUILTIN_PCMPEQD,
2111 IX86_BUILTIN_PCMPGTB,
2112 IX86_BUILTIN_PCMPGTW,
2113 IX86_BUILTIN_PCMPGTD,
2114
2115 IX86_BUILTIN_PEXTRW,
2116 IX86_BUILTIN_PINSRW,
2117
2118 IX86_BUILTIN_PMADDWD,
2119
2120 IX86_BUILTIN_PMAXSW,
2121 IX86_BUILTIN_PMAXUB,
2122 IX86_BUILTIN_PMINSW,
2123 IX86_BUILTIN_PMINUB,
2124
2125 IX86_BUILTIN_PMULHUW,
2126 IX86_BUILTIN_PMULHW,
2127 IX86_BUILTIN_PMULLW,
2128
2129 IX86_BUILTIN_PSADBW,
2130 IX86_BUILTIN_PSHUFW,
2131
2132 IX86_BUILTIN_PSLLW,
2133 IX86_BUILTIN_PSLLD,
2134 IX86_BUILTIN_PSLLQ,
2135 IX86_BUILTIN_PSRAW,
2136 IX86_BUILTIN_PSRAD,
2137 IX86_BUILTIN_PSRLW,
2138 IX86_BUILTIN_PSRLD,
2139 IX86_BUILTIN_PSRLQ,
2140 IX86_BUILTIN_PSLLWI,
2141 IX86_BUILTIN_PSLLDI,
2142 IX86_BUILTIN_PSLLQI,
2143 IX86_BUILTIN_PSRAWI,
2144 IX86_BUILTIN_PSRADI,
2145 IX86_BUILTIN_PSRLWI,
2146 IX86_BUILTIN_PSRLDI,
2147 IX86_BUILTIN_PSRLQI,
2148
2149 IX86_BUILTIN_PUNPCKHBW,
2150 IX86_BUILTIN_PUNPCKHWD,
2151 IX86_BUILTIN_PUNPCKHDQ,
2152 IX86_BUILTIN_PUNPCKLBW,
2153 IX86_BUILTIN_PUNPCKLWD,
2154 IX86_BUILTIN_PUNPCKLDQ,
2155
2156 IX86_BUILTIN_SHUFPS,
2157
2158 IX86_BUILTIN_RCPPS,
2159 IX86_BUILTIN_RCPSS,
2160 IX86_BUILTIN_RSQRTPS,
2161 IX86_BUILTIN_RSQRTSS,
2162 IX86_BUILTIN_SQRTPS,
2163 IX86_BUILTIN_SQRTSS,
2164
2165 IX86_BUILTIN_UNPCKHPS,
2166 IX86_BUILTIN_UNPCKLPS,
2167
2168 IX86_BUILTIN_ANDPS,
2169 IX86_BUILTIN_ANDNPS,
2170 IX86_BUILTIN_ORPS,
2171 IX86_BUILTIN_XORPS,
2172
2173 IX86_BUILTIN_EMMS,
2174 IX86_BUILTIN_LDMXCSR,
2175 IX86_BUILTIN_STMXCSR,
2176 IX86_BUILTIN_SFENCE,
2177
2178 /* 3DNow! Original */
2179 IX86_BUILTIN_FEMMS,
2180 IX86_BUILTIN_PAVGUSB,
2181 IX86_BUILTIN_PF2ID,
2182 IX86_BUILTIN_PFACC,
2183 IX86_BUILTIN_PFADD,
2184 IX86_BUILTIN_PFCMPEQ,
2185 IX86_BUILTIN_PFCMPGE,
2186 IX86_BUILTIN_PFCMPGT,
2187 IX86_BUILTIN_PFMAX,
2188 IX86_BUILTIN_PFMIN,
2189 IX86_BUILTIN_PFMUL,
2190 IX86_BUILTIN_PFRCP,
2191 IX86_BUILTIN_PFRCPIT1,
2192 IX86_BUILTIN_PFRCPIT2,
2193 IX86_BUILTIN_PFRSQIT1,
2194 IX86_BUILTIN_PFRSQRT,
2195 IX86_BUILTIN_PFSUB,
2196 IX86_BUILTIN_PFSUBR,
2197 IX86_BUILTIN_PI2FD,
2198 IX86_BUILTIN_PMULHRW,
2199
2200 /* 3DNow! Athlon Extensions */
2201 IX86_BUILTIN_PF2IW,
2202 IX86_BUILTIN_PFNACC,
2203 IX86_BUILTIN_PFPNACC,
2204 IX86_BUILTIN_PI2FW,
2205 IX86_BUILTIN_PSWAPDSI,
2206 IX86_BUILTIN_PSWAPDSF,
2207
2208 IX86_BUILTIN_SSE_ZERO,
2209 IX86_BUILTIN_MMX_ZERO,
2210
2211 /* SSE2 */
2212 IX86_BUILTIN_ADDPD,
2213 IX86_BUILTIN_ADDSD,
2214 IX86_BUILTIN_DIVPD,
2215 IX86_BUILTIN_DIVSD,
2216 IX86_BUILTIN_MULPD,
2217 IX86_BUILTIN_MULSD,
2218 IX86_BUILTIN_SUBPD,
2219 IX86_BUILTIN_SUBSD,
2220
2221 IX86_BUILTIN_CMPEQPD,
2222 IX86_BUILTIN_CMPLTPD,
2223 IX86_BUILTIN_CMPLEPD,
2224 IX86_BUILTIN_CMPGTPD,
2225 IX86_BUILTIN_CMPGEPD,
2226 IX86_BUILTIN_CMPNEQPD,
2227 IX86_BUILTIN_CMPNLTPD,
2228 IX86_BUILTIN_CMPNLEPD,
2229 IX86_BUILTIN_CMPNGTPD,
2230 IX86_BUILTIN_CMPNGEPD,
2231 IX86_BUILTIN_CMPORDPD,
2232 IX86_BUILTIN_CMPUNORDPD,
2233 IX86_BUILTIN_CMPNEPD,
2234 IX86_BUILTIN_CMPEQSD,
2235 IX86_BUILTIN_CMPLTSD,
2236 IX86_BUILTIN_CMPLESD,
2237 IX86_BUILTIN_CMPGTSD,
2238 IX86_BUILTIN_CMPGESD,
2239 IX86_BUILTIN_CMPNEQSD,
2240 IX86_BUILTIN_CMPNLTSD,
2241 IX86_BUILTIN_CMPNLESD,
2242 IX86_BUILTIN_CMPNGTSD,
2243 IX86_BUILTIN_CMPNGESD,
2244 IX86_BUILTIN_CMPORDSD,
2245 IX86_BUILTIN_CMPUNORDSD,
2246 IX86_BUILTIN_CMPNESD,
2247
2248 IX86_BUILTIN_COMIEQSD,
2249 IX86_BUILTIN_COMILTSD,
2250 IX86_BUILTIN_COMILESD,
2251 IX86_BUILTIN_COMIGTSD,
2252 IX86_BUILTIN_COMIGESD,
2253 IX86_BUILTIN_COMINEQSD,
2254 IX86_BUILTIN_UCOMIEQSD,
2255 IX86_BUILTIN_UCOMILTSD,
2256 IX86_BUILTIN_UCOMILESD,
2257 IX86_BUILTIN_UCOMIGTSD,
2258 IX86_BUILTIN_UCOMIGESD,
2259 IX86_BUILTIN_UCOMINEQSD,
2260
2261 IX86_BUILTIN_MAXPD,
2262 IX86_BUILTIN_MAXSD,
2263 IX86_BUILTIN_MINPD,
2264 IX86_BUILTIN_MINSD,
2265
2266 IX86_BUILTIN_ANDPD,
2267 IX86_BUILTIN_ANDNPD,
2268 IX86_BUILTIN_ORPD,
2269 IX86_BUILTIN_XORPD,
2270
2271 IX86_BUILTIN_SQRTPD,
2272 IX86_BUILTIN_SQRTSD,
2273
2274 IX86_BUILTIN_UNPCKHPD,
2275 IX86_BUILTIN_UNPCKLPD,
2276
2277 IX86_BUILTIN_SHUFPD,
2278
2279 IX86_BUILTIN_LOADAPD,
2280 IX86_BUILTIN_LOADUPD,
2281 IX86_BUILTIN_STOREAPD,
2282 IX86_BUILTIN_STOREUPD,
2283 IX86_BUILTIN_LOADSD,
2284 IX86_BUILTIN_STORESD,
2285 IX86_BUILTIN_MOVSD,
2286
2287 IX86_BUILTIN_LOADHPD,
2288 IX86_BUILTIN_LOADLPD,
2289 IX86_BUILTIN_STOREHPD,
2290 IX86_BUILTIN_STORELPD,
2291
2292 IX86_BUILTIN_CVTDQ2PD,
2293 IX86_BUILTIN_CVTDQ2PS,
2294
2295 IX86_BUILTIN_CVTPD2DQ,
2296 IX86_BUILTIN_CVTPD2PI,
2297 IX86_BUILTIN_CVTPD2PS,
2298 IX86_BUILTIN_CVTTPD2DQ,
2299 IX86_BUILTIN_CVTTPD2PI,
2300
2301 IX86_BUILTIN_CVTPI2PD,
2302 IX86_BUILTIN_CVTSI2SD,
2303
2304 IX86_BUILTIN_CVTSD2SI,
2305 IX86_BUILTIN_CVTSD2SS,
2306 IX86_BUILTIN_CVTSS2SD,
2307 IX86_BUILTIN_CVTTSD2SI,
2308
2309 IX86_BUILTIN_CVTPS2DQ,
2310 IX86_BUILTIN_CVTPS2PD,
2311 IX86_BUILTIN_CVTTPS2DQ,
2312
2313 IX86_BUILTIN_MOVNTI,
2314 IX86_BUILTIN_MOVNTPD,
2315 IX86_BUILTIN_MOVNTDQ,
2316
2317 IX86_BUILTIN_SETPD1,
2318 IX86_BUILTIN_SETPD,
2319 IX86_BUILTIN_CLRPD,
2320 IX86_BUILTIN_SETRPD,
2321 IX86_BUILTIN_LOADPD1,
2322 IX86_BUILTIN_LOADRPD,
2323 IX86_BUILTIN_STOREPD1,
2324 IX86_BUILTIN_STORERPD,
2325
2326 /* SSE2 MMX */
2327 IX86_BUILTIN_MASKMOVDQU,
2328 IX86_BUILTIN_MOVMSKPD,
2329 IX86_BUILTIN_PMOVMSKB128,
2330 IX86_BUILTIN_MOVQ2DQ,
2331
2332 IX86_BUILTIN_PACKSSWB128,
2333 IX86_BUILTIN_PACKSSDW128,
2334 IX86_BUILTIN_PACKUSWB128,
2335
2336 IX86_BUILTIN_PADDB128,
2337 IX86_BUILTIN_PADDW128,
2338 IX86_BUILTIN_PADDD128,
2339 IX86_BUILTIN_PADDQ128,
2340 IX86_BUILTIN_PADDSB128,
2341 IX86_BUILTIN_PADDSW128,
2342 IX86_BUILTIN_PADDUSB128,
2343 IX86_BUILTIN_PADDUSW128,
2344 IX86_BUILTIN_PSUBB128,
2345 IX86_BUILTIN_PSUBW128,
2346 IX86_BUILTIN_PSUBD128,
2347 IX86_BUILTIN_PSUBQ128,
2348 IX86_BUILTIN_PSUBSB128,
2349 IX86_BUILTIN_PSUBSW128,
2350 IX86_BUILTIN_PSUBUSB128,
2351 IX86_BUILTIN_PSUBUSW128,
2352
2353 IX86_BUILTIN_PAND128,
2354 IX86_BUILTIN_PANDN128,
2355 IX86_BUILTIN_POR128,
2356 IX86_BUILTIN_PXOR128,
2357
2358 IX86_BUILTIN_PAVGB128,
2359 IX86_BUILTIN_PAVGW128,
2360
2361 IX86_BUILTIN_PCMPEQB128,
2362 IX86_BUILTIN_PCMPEQW128,
2363 IX86_BUILTIN_PCMPEQD128,
2364 IX86_BUILTIN_PCMPGTB128,
2365 IX86_BUILTIN_PCMPGTW128,
2366 IX86_BUILTIN_PCMPGTD128,
2367
2368 IX86_BUILTIN_PEXTRW128,
2369 IX86_BUILTIN_PINSRW128,
2370
2371 IX86_BUILTIN_PMADDWD128,
2372
2373 IX86_BUILTIN_PMAXSW128,
2374 IX86_BUILTIN_PMAXUB128,
2375 IX86_BUILTIN_PMINSW128,
2376 IX86_BUILTIN_PMINUB128,
2377
2378 IX86_BUILTIN_PMULUDQ,
2379 IX86_BUILTIN_PMULUDQ128,
2380 IX86_BUILTIN_PMULHUW128,
2381 IX86_BUILTIN_PMULHW128,
2382 IX86_BUILTIN_PMULLW128,
2383
2384 IX86_BUILTIN_PSADBW128,
2385 IX86_BUILTIN_PSHUFHW,
2386 IX86_BUILTIN_PSHUFLW,
2387 IX86_BUILTIN_PSHUFD,
2388
2389 IX86_BUILTIN_PSLLW128,
2390 IX86_BUILTIN_PSLLD128,
2391 IX86_BUILTIN_PSLLQ128,
2392 IX86_BUILTIN_PSRAW128,
2393 IX86_BUILTIN_PSRAD128,
2394 IX86_BUILTIN_PSRLW128,
2395 IX86_BUILTIN_PSRLD128,
2396 IX86_BUILTIN_PSRLQ128,
2397 IX86_BUILTIN_PSLLWI128,
2398 IX86_BUILTIN_PSLLDI128,
2399 IX86_BUILTIN_PSLLQI128,
2400 IX86_BUILTIN_PSRAWI128,
2401 IX86_BUILTIN_PSRADI128,
2402 IX86_BUILTIN_PSRLWI128,
2403 IX86_BUILTIN_PSRLDI128,
2404 IX86_BUILTIN_PSRLQI128,
2405
2406 IX86_BUILTIN_PUNPCKHBW128,
2407 IX86_BUILTIN_PUNPCKHWD128,
2408 IX86_BUILTIN_PUNPCKHDQ128,
2409 IX86_BUILTIN_PUNPCKLBW128,
2410 IX86_BUILTIN_PUNPCKLWD128,
2411 IX86_BUILTIN_PUNPCKLDQ128,
2412
2413 IX86_BUILTIN_CLFLUSH,
2414 IX86_BUILTIN_MFENCE,
2415 IX86_BUILTIN_LFENCE,
2416
2417 IX86_BUILTIN_MAX
2418 };
2419 \f
2420 #define TARGET_ENCODE_SECTION_INFO i386_encode_section_info
2421
2422 /* The `FINALIZE_PIC' macro serves as a hook to emit these special
2423 codes once the function is being compiled into assembly code, but
2424 not before. (It is not done before, because in the case of
2425 compiling an inline function, it would lead to multiple PIC
2426 prologues being included in functions which used inline functions
2427 and were compiled to assembly language.) */
2428
2429 #define FINALIZE_PIC \
2430 (current_function_uses_pic_offset_table |= current_function_profile)
2431
2432 \f
2433 /* Max number of args passed in registers. If this is more than 3, we will
2434 have problems with ebx (register #4), since it is a caller save register and
2435 is also used as the pic register in ELF. So for now, don't allow more than
2436 3 registers to be passed in registers. */
2437
2438 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2439
2440 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0)
2441
2442 \f
2443 /* Specify the machine mode that this machine uses
2444 for the index in the tablejump instruction. */
2445 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
2446
2447 /* Define as C expression which evaluates to nonzero if the tablejump
2448 instruction expects the table to contain offsets from the address of the
2449 table.
2450 Do not define this if the table should contain absolute addresses. */
2451 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2452
2453 /* Define this as 1 if `char' should by default be signed; else as 0. */
2454 #define DEFAULT_SIGNED_CHAR 1
2455
2456 /* Number of bytes moved into a data cache for a single prefetch operation. */
2457 #define PREFETCH_BLOCK ix86_cost->prefetch_block
2458
2459 /* Number of prefetch operations that can be done in parallel. */
2460 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
2461
2462 /* Max number of bytes we can move from memory to memory
2463 in one reasonably fast instruction. */
2464 #define MOVE_MAX 16
2465
2466 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2467 move efficiently, as opposed to MOVE_MAX which is the maximum
2468 number of bytes we can move with a single instruction. */
2469 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2470
2471 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2472 move-instruction pairs, we will do a movstr or libcall instead.
2473 Increasing the value will always make code faster, but eventually
2474 incurs high cost in increased code size.
2475
2476 If you don't define this, a reasonable default is used. */
2477
2478 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2479
2480 /* Define if shifts truncate the shift count
2481 which implies one can omit a sign-extension or zero-extension
2482 of a shift count. */
2483 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2484
2485 /* #define SHIFT_COUNT_TRUNCATED */
2486
2487 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2488 is done just by pretending it is already truncated. */
2489 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2490
2491 /* We assume that the store-condition-codes instructions store 0 for false
2492 and some other value for true. This is the value stored for true. */
2493
2494 #define STORE_FLAG_VALUE 1
2495
2496 /* When a prototype says `char' or `short', really pass an `int'.
2497 (The 386 can't easily push less than an int.) */
2498
2499 #define PROMOTE_PROTOTYPES 1
2500
2501 /* A macro to update M and UNSIGNEDP when an object whose type is
2502 TYPE and which has the specified mode and signedness is to be
2503 stored in a register. This macro is only called when TYPE is a
2504 scalar type.
2505
2506 On i386 it is sometimes useful to promote HImode and QImode
2507 quantities to SImode. The choice depends on target type. */
2508
2509 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2510 do { \
2511 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2512 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2513 (MODE) = SImode; \
2514 } while (0)
2515
2516 /* Specify the machine mode that pointers have.
2517 After generation of rtl, the compiler makes no further distinction
2518 between pointers and any other objects of this machine mode. */
2519 #define Pmode (TARGET_64BIT ? DImode : SImode)
2520
2521 /* A function address in a call instruction
2522 is a byte address (for indexing purposes)
2523 so give the MEM rtx a byte's mode. */
2524 #define FUNCTION_MODE QImode
2525 \f
2526 /* A part of a C `switch' statement that describes the relative costs
2527 of constant RTL expressions. It must contain `case' labels for
2528 expression codes `const_int', `const', `symbol_ref', `label_ref'
2529 and `const_double'. Each case must ultimately reach a `return'
2530 statement to return the relative cost of the use of that kind of
2531 constant value in an expression. The cost may depend on the
2532 precise value of the constant, which is available for examination
2533 in X, and the rtx code of the expression in which it is contained,
2534 found in OUTER_CODE.
2535
2536 CODE is the expression code--redundant, since it can be obtained
2537 with `GET_CODE (X)'. */
2538
2539 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
2540 case CONST_INT: \
2541 case CONST: \
2542 case LABEL_REF: \
2543 case SYMBOL_REF: \
2544 if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \
2545 return 3; \
2546 if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \
2547 return 2; \
2548 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \
2549 \
2550 case CONST_DOUBLE: \
2551 if (GET_MODE (RTX) == VOIDmode) \
2552 return 0; \
2553 switch (standard_80387_constant_p (RTX)) \
2554 { \
2555 case 1: /* 0.0 */ \
2556 return 1; \
2557 case 2: /* 1.0 */ \
2558 return 2; \
2559 default: \
2560 /* Start with (MEM (SYMBOL_REF)), since that's where \
2561 it'll probably end up. Add a penalty for size. */ \
2562 return (COSTS_N_INSNS (1) + (flag_pic != 0) \
2563 + (GET_MODE (RTX) == SFmode ? 0 \
2564 : GET_MODE (RTX) == DFmode ? 1 : 2)); \
2565 }
2566
2567 /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */
2568 #define TOPLEVEL_COSTS_N_INSNS(N) \
2569 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0)
2570
2571 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2572 This can be used, for example, to indicate how costly a multiply
2573 instruction is. In writing this macro, you can use the construct
2574 `COSTS_N_INSNS (N)' to specify a cost equal to N fast
2575 instructions. OUTER_CODE is the code of the expression in which X
2576 is contained.
2577
2578 This macro is optional; do not define it if the default cost
2579 assumptions are adequate for the target machine. */
2580
2581 #define RTX_COSTS(X, CODE, OUTER_CODE) \
2582 case ZERO_EXTEND: \
2583 /* The zero extensions is often completely free on x86_64, so make \
2584 it as cheap as possible. */ \
2585 if (TARGET_64BIT && GET_MODE (X) == DImode \
2586 && GET_MODE (XEXP (X, 0)) == SImode) \
2587 { \
2588 total = 1; goto egress_rtx_costs; \
2589 } \
2590 else \
2591 TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \
2592 ix86_cost->add : ix86_cost->movzx); \
2593 break; \
2594 case SIGN_EXTEND: \
2595 TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \
2596 break; \
2597 case ASHIFT: \
2598 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2599 && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \
2600 { \
2601 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2602 if (value == 1) \
2603 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2604 if ((value == 2 || value == 3) \
2605 && !TARGET_DECOMPOSE_LEA \
2606 && ix86_cost->lea <= ix86_cost->shift_const) \
2607 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \
2608 } \
2609 /* fall through */ \
2610 \
2611 case ROTATE: \
2612 case ASHIFTRT: \
2613 case LSHIFTRT: \
2614 case ROTATERT: \
2615 if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \
2616 { \
2617 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2618 { \
2619 if (INTVAL (XEXP (X, 1)) > 32) \
2620 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \
2621 else \
2622 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \
2623 } \
2624 else \
2625 { \
2626 if (GET_CODE (XEXP (X, 1)) == AND) \
2627 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \
2628 else \
2629 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \
2630 } \
2631 } \
2632 else \
2633 { \
2634 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2635 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \
2636 else \
2637 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \
2638 } \
2639 break; \
2640 \
2641 case MULT: \
2642 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2643 { \
2644 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2645 int nbits = 0; \
2646 \
2647 while (value != 0) \
2648 { \
2649 nbits++; \
2650 value >>= 1; \
2651 } \
2652 \
2653 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2654 + nbits * ix86_cost->mult_bit); \
2655 } \
2656 else /* This is arbitrary */ \
2657 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2658 + 7 * ix86_cost->mult_bit); \
2659 \
2660 case DIV: \
2661 case UDIV: \
2662 case MOD: \
2663 case UMOD: \
2664 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \
2665 \
2666 case PLUS: \
2667 if (!TARGET_DECOMPOSE_LEA \
2668 && INTEGRAL_MODE_P (GET_MODE (X)) \
2669 && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \
2670 { \
2671 if (GET_CODE (XEXP (X, 0)) == PLUS \
2672 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \
2673 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \
2674 && CONSTANT_P (XEXP (X, 1))) \
2675 { \
2676 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\
2677 if (val == 2 || val == 4 || val == 8) \
2678 { \
2679 return (COSTS_N_INSNS (ix86_cost->lea) \
2680 + rtx_cost (XEXP (XEXP (X, 0), 1), \
2681 (OUTER_CODE)) \
2682 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), \
2683 (OUTER_CODE)) \
2684 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2685 } \
2686 } \
2687 else if (GET_CODE (XEXP (X, 0)) == MULT \
2688 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
2689 { \
2690 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
2691 if (val == 2 || val == 4 || val == 8) \
2692 { \
2693 return (COSTS_N_INSNS (ix86_cost->lea) \
2694 + rtx_cost (XEXP (XEXP (X, 0), 0), \
2695 (OUTER_CODE)) \
2696 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2697 } \
2698 } \
2699 else if (GET_CODE (XEXP (X, 0)) == PLUS) \
2700 { \
2701 return (COSTS_N_INSNS (ix86_cost->lea) \
2702 + rtx_cost (XEXP (XEXP (X, 0), 0), (OUTER_CODE)) \
2703 + rtx_cost (XEXP (XEXP (X, 0), 1), (OUTER_CODE)) \
2704 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2705 } \
2706 } \
2707 \
2708 /* fall through */ \
2709 case AND: \
2710 case IOR: \
2711 case XOR: \
2712 case MINUS: \
2713 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2714 return (COSTS_N_INSNS (ix86_cost->add) * 2 \
2715 + (rtx_cost (XEXP (X, 0), (OUTER_CODE)) \
2716 << (GET_MODE (XEXP (X, 0)) != DImode)) \
2717 + (rtx_cost (XEXP (X, 1), (OUTER_CODE)) \
2718 << (GET_MODE (XEXP (X, 1)) != DImode))); \
2719 \
2720 /* fall through */ \
2721 case NEG: \
2722 case NOT: \
2723 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2724 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \
2725 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2726 \
2727 case FLOAT_EXTEND: \
2728 TOPLEVEL_COSTS_N_INSNS (0); \
2729 \
2730 egress_rtx_costs: \
2731 break;
2732
2733
2734 /* An expression giving the cost of an addressing mode that contains
2735 ADDRESS. If not defined, the cost is computed from the ADDRESS
2736 expression and the `CONST_COSTS' values.
2737
2738 For most CISC machines, the default cost is a good approximation
2739 of the true cost of the addressing mode. However, on RISC
2740 machines, all instructions normally have the same length and
2741 execution time. Hence all addresses will have equal costs.
2742
2743 In cases where more than one form of an address is known, the form
2744 with the lowest cost will be used. If multiple forms have the
2745 same, lowest, cost, the one that is the most complex will be used.
2746
2747 For example, suppose an address that is equal to the sum of a
2748 register and a constant is used twice in the same basic block.
2749 When this macro is not defined, the address will be computed in a
2750 register and memory references will be indirect through that
2751 register. On machines where the cost of the addressing mode
2752 containing the sum is no higher than that of a simple indirect
2753 reference, this will produce an additional instruction and
2754 possibly require an additional register. Proper specification of
2755 this macro eliminates this overhead for such machines.
2756
2757 Similar use of this macro is made in strength reduction of loops.
2758
2759 ADDRESS need not be valid as an address. In such a case, the cost
2760 is not relevant and can be any value; invalid addresses need not be
2761 assigned a different cost.
2762
2763 On machines where an address involving more than one register is as
2764 cheap as an address computation involving only one register,
2765 defining `ADDRESS_COST' to reflect this can cause two registers to
2766 be live over a region of code where only one would have been if
2767 `ADDRESS_COST' were not defined in that manner. This effect should
2768 be considered in the definition of this macro. Equivalent costs
2769 should probably only be given to addresses with different numbers
2770 of registers on machines with lots of registers.
2771
2772 This macro will normally either not be defined or be defined as a
2773 constant.
2774
2775 For i386, it is better to use a complex address than let gcc copy
2776 the address into a reg and make a new pseudo. But not if the address
2777 requires to two regs - that would mean more pseudos with longer
2778 lifetimes. */
2779
2780 #define ADDRESS_COST(RTX) \
2781 ix86_address_cost (RTX)
2782
2783 /* A C expression for the cost of moving data from a register in class FROM to
2784 one in class TO. The classes are expressed using the enumeration values
2785 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2786 interpreted relative to that.
2787
2788 It is not required that the cost always equal 2 when FROM is the same as TO;
2789 on some machines it is expensive to move between registers if they are not
2790 general registers. */
2791
2792 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2793 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
2794
2795 /* A C expression for the cost of moving data of mode M between a
2796 register and memory. A value of 2 is the default; this cost is
2797 relative to those in `REGISTER_MOVE_COST'.
2798
2799 If moving between registers and memory is more expensive than
2800 between two registers, you should define this macro to express the
2801 relative cost. */
2802
2803 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
2804 ix86_memory_move_cost ((MODE), (CLASS), (IN))
2805
2806 /* A C expression for the cost of a branch instruction. A value of 1
2807 is the default; other values are interpreted relative to that. */
2808
2809 #define BRANCH_COST ix86_branch_cost
2810
2811 /* Define this macro as a C expression which is nonzero if accessing
2812 less than a word of memory (i.e. a `char' or a `short') is no
2813 faster than accessing a word of memory, i.e., if such access
2814 require more than one instruction or if there is no difference in
2815 cost between byte and (aligned) word loads.
2816
2817 When this macro is not defined, the compiler will access a field by
2818 finding the smallest containing object; when it is defined, a
2819 fullword load will be used if alignment permits. Unless bytes
2820 accesses are faster than word accesses, using word accesses is
2821 preferable since it may eliminate subsequent memory access if
2822 subsequent accesses occur to other fields in the same word of the
2823 structure, but to different bytes. */
2824
2825 #define SLOW_BYTE_ACCESS 0
2826
2827 /* Nonzero if access to memory by shorts is slow and undesirable. */
2828 #define SLOW_SHORT_ACCESS 0
2829
2830 /* Define this macro to be the value 1 if unaligned accesses have a
2831 cost many times greater than aligned accesses, for example if they
2832 are emulated in a trap handler.
2833
2834 When this macro is non-zero, the compiler will act as if
2835 `STRICT_ALIGNMENT' were non-zero when generating code for block
2836 moves. This can cause significantly more instructions to be
2837 produced. Therefore, do not set this macro non-zero if unaligned
2838 accesses only add a cycle or two to the time for a memory access.
2839
2840 If the value of this macro is always zero, it need not be defined. */
2841
2842 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2843
2844 /* Define this macro to inhibit strength reduction of memory
2845 addresses. (On some machines, such strength reduction seems to do
2846 harm rather than good.) */
2847
2848 /* #define DONT_REDUCE_ADDR */
2849
2850 /* Define this macro if it is as good or better to call a constant
2851 function address than to call an address kept in a register.
2852
2853 Desirable on the 386 because a CALL with a constant address is
2854 faster than one with a register address. */
2855
2856 #define NO_FUNCTION_CSE
2857
2858 /* Define this macro if it is as good or better for a function to call
2859 itself with an explicit address than to call an address kept in a
2860 register. */
2861
2862 #define NO_RECURSIVE_FUNCTION_CSE
2863 \f
2864 /* Add any extra modes needed to represent the condition code.
2865
2866 For the i386, we need separate modes when floating-point
2867 equality comparisons are being done.
2868
2869 Add CCNO to indicate comparisons against zero that requires
2870 Overflow flag to be unset. Sign bit test is used instead and
2871 thus can be used to form "a&b>0" type of tests.
2872
2873 Add CCGC to indicate comparisons agains zero that allows
2874 unspecified garbage in the Carry flag. This mode is used
2875 by inc/dec instructions.
2876
2877 Add CCGOC to indicate comparisons agains zero that allows
2878 unspecified garbage in the Carry and Overflow flag. This
2879 mode is used to simulate comparisons of (a-b) and (a+b)
2880 against zero using sub/cmp/add operations.
2881
2882 Add CCZ to indicate that only the Zero flag is valid. */
2883
2884 #define EXTRA_CC_MODES \
2885 CC (CCGCmode, "CCGC") \
2886 CC (CCGOCmode, "CCGOC") \
2887 CC (CCNOmode, "CCNO") \
2888 CC (CCZmode, "CCZ") \
2889 CC (CCFPmode, "CCFP") \
2890 CC (CCFPUmode, "CCFPU")
2891
2892 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2893 return the mode to be used for the comparison.
2894
2895 For floating-point equality comparisons, CCFPEQmode should be used.
2896 VOIDmode should be used in all other cases.
2897
2898 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2899 possible, to allow for more combinations. */
2900
2901 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2902
2903 /* Return non-zero if MODE implies a floating point inequality can be
2904 reversed. */
2905
2906 #define REVERSIBLE_CC_MODE(MODE) 1
2907
2908 /* A C expression whose value is reversed condition code of the CODE for
2909 comparison done in CC_MODE mode. */
2910 #define REVERSE_CONDITION(CODE, MODE) \
2911 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \
2912 : reverse_condition_maybe_unordered (CODE))
2913
2914 \f
2915 /* Control the assembler format that we output, to the extent
2916 this does not vary between assemblers. */
2917
2918 /* How to refer to registers in assembler output.
2919 This sequence is indexed by compiler's hard-register-number (see above). */
2920
2921 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2922 For non floating point regs, the following are the HImode names.
2923
2924 For float regs, the stack top is sometimes referred to as "%st(0)"
2925 instead of just "%st". PRINT_REG handles this with the "y" code. */
2926
2927 #undef HI_REGISTER_NAMES
2928 #define HI_REGISTER_NAMES \
2929 {"ax","dx","cx","bx","si","di","bp","sp", \
2930 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2931 "flags","fpsr", "dirflag", "frame", \
2932 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2933 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2934 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2935 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2936
2937 #define REGISTER_NAMES HI_REGISTER_NAMES
2938
2939 /* Table of additional register names to use in user input. */
2940
2941 #define ADDITIONAL_REGISTER_NAMES \
2942 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2943 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2944 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2945 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2946 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2947 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2948 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2949 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2950
2951 /* Note we are omitting these since currently I don't know how
2952 to get gcc to use these, since they want the same but different
2953 number as al, and ax.
2954 */
2955
2956 #define QI_REGISTER_NAMES \
2957 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2958
2959 /* These parallel the array above, and can be used to access bits 8:15
2960 of regs 0 through 3. */
2961
2962 #define QI_HIGH_REGISTER_NAMES \
2963 {"ah", "dh", "ch", "bh", }
2964
2965 /* How to renumber registers for dbx and gdb. */
2966
2967 #define DBX_REGISTER_NUMBER(N) \
2968 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2969
2970 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2971 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2972 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2973
2974 /* Before the prologue, RA is at 0(%esp). */
2975 #define INCOMING_RETURN_ADDR_RTX \
2976 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2977
2978 /* After the prologue, RA is at -4(AP) in the current frame. */
2979 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2980 ((COUNT) == 0 \
2981 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2982 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2983
2984 /* PC is dbx register 8; let's use that column for RA. */
2985 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2986
2987 /* Before the prologue, the top of the frame is at 4(%esp). */
2988 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2989
2990 /* Describe how we implement __builtin_eh_return. */
2991 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2992 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2993
2994
2995 /* Select a format to encode pointers in exception handling data. CODE
2996 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2997 true if the symbol may be affected by dynamic relocations.
2998
2999 ??? All x86 object file formats are capable of representing this.
3000 After all, the relocation needed is the same as for the call insn.
3001 Whether or not a particular assembler allows us to enter such, I
3002 guess we'll have to see. */
3003 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3004 (flag_pic \
3005 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
3006 : DW_EH_PE_absptr)
3007
3008 /* This is how to output the definition of a user-level label named NAME,
3009 such as the label on a static function or variable NAME. */
3010
3011 #define ASM_OUTPUT_LABEL(FILE, NAME) \
3012 (assemble_name ((FILE), (NAME)), fputs (":\n", (FILE)))
3013
3014 /* Store in OUTPUT a string (made with alloca) containing
3015 an assembler-name for a local static variable named NAME.
3016 LABELNO is an integer which is different for each call. */
3017
3018 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
3019 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
3020 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
3021
3022 /* This is how to output an insn to push a register on the stack.
3023 It need not be very fast code. */
3024
3025 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
3026 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)])
3027
3028 /* This is how to output an insn to pop a register from the stack.
3029 It need not be very fast code. */
3030
3031 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
3032 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)])
3033
3034 /* This is how to output an element of a case-vector that is absolute. */
3035
3036 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
3037 ix86_output_addr_vec_elt ((FILE), (VALUE))
3038
3039 /* This is how to output an element of a case-vector that is relative. */
3040
3041 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
3042 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
3043
3044 /* Under some conditions we need jump tables in the text section, because
3045 the assembler cannot handle label differences between sections. */
3046
3047 #define JUMP_TABLES_IN_TEXT_SECTION \
3048 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
3049
3050 /* A C statement that outputs an address constant appropriate to
3051 for DWARF debugging. */
3052
3053 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \
3054 i386_dwarf_output_addr_const ((FILE), (X))
3055
3056 /* Either simplify a location expression, or return the original. */
3057
3058 #define ASM_SIMPLIFY_DWARF_ADDR(X) \
3059 i386_simplify_dwarf_addr (X)
3060
3061 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
3062 and switch back. For x86 we do this only to save a few bytes that
3063 would otherwise be unused in the text section. */
3064 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3065 asm (SECTION_OP "\n\t" \
3066 "call " USER_LABEL_PREFIX #FUNC "\n" \
3067 TEXT_SECTION_ASM_OP);
3068 \f
3069 /* Print operand X (an rtx) in assembler syntax to file FILE.
3070 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3071 Effect of various CODE letters is described in i386.c near
3072 print_operand function. */
3073
3074 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
3075 ((CODE) == '*' || (CODE) == '+')
3076
3077 /* Print the name of a register based on its machine mode and number.
3078 If CODE is 'w', pretend the mode is HImode.
3079 If CODE is 'b', pretend the mode is QImode.
3080 If CODE is 'k', pretend the mode is SImode.
3081 If CODE is 'q', pretend the mode is DImode.
3082 If CODE is 'h', pretend the reg is the `high' byte register.
3083 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
3084
3085 #define PRINT_REG(X, CODE, FILE) \
3086 print_reg ((X), (CODE), (FILE))
3087
3088 #define PRINT_OPERAND(FILE, X, CODE) \
3089 print_operand ((FILE), (X), (CODE))
3090
3091 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
3092 print_operand_address ((FILE), (ADDR))
3093
3094 /* Print the name of a register for based on its machine mode and number.
3095 This macro is used to print debugging output.
3096 This macro is different from PRINT_REG in that it may be used in
3097 programs that are not linked with aux-output.o. */
3098
3099 #define DEBUG_PRINT_REG(X, CODE, FILE) \
3100 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
3101 static const char * const qi_name[] = QI_REGISTER_NAMES; \
3102 fprintf ((FILE), "%d ", REGNO (X)); \
3103 if (REGNO (X) == FLAGS_REG) \
3104 { fputs ("flags", (FILE)); break; } \
3105 if (REGNO (X) == DIRFLAG_REG) \
3106 { fputs ("dirflag", (FILE)); break; } \
3107 if (REGNO (X) == FPSR_REG) \
3108 { fputs ("fpsr", (FILE)); break; } \
3109 if (REGNO (X) == ARG_POINTER_REGNUM) \
3110 { fputs ("argp", (FILE)); break; } \
3111 if (REGNO (X) == FRAME_POINTER_REGNUM) \
3112 { fputs ("frame", (FILE)); break; } \
3113 if (STACK_TOP_P (X)) \
3114 { fputs ("st(0)", (FILE)); break; } \
3115 if (FP_REG_P (X)) \
3116 { fputs (hi_name[REGNO(X)], (FILE)); break; } \
3117 if (REX_INT_REG_P (X)) \
3118 { \
3119 switch (GET_MODE_SIZE (GET_MODE (X))) \
3120 { \
3121 default: \
3122 case 8: \
3123 fprintf ((FILE), "r%i", REGNO (X) \
3124 - FIRST_REX_INT_REG + 8); \
3125 break; \
3126 case 4: \
3127 fprintf ((FILE), "r%id", REGNO (X) \
3128 - FIRST_REX_INT_REG + 8); \
3129 break; \
3130 case 2: \
3131 fprintf ((FILE), "r%iw", REGNO (X) \
3132 - FIRST_REX_INT_REG + 8); \
3133 break; \
3134 case 1: \
3135 fprintf ((FILE), "r%ib", REGNO (X) \
3136 - FIRST_REX_INT_REG + 8); \
3137 break; \
3138 } \
3139 break; \
3140 } \
3141 switch (GET_MODE_SIZE (GET_MODE (X))) \
3142 { \
3143 case 8: \
3144 fputs ("r", (FILE)); \
3145 fputs (hi_name[REGNO (X)], (FILE)); \
3146 break; \
3147 default: \
3148 fputs ("e", (FILE)); \
3149 case 2: \
3150 fputs (hi_name[REGNO (X)], (FILE)); \
3151 break; \
3152 case 1: \
3153 fputs (qi_name[REGNO (X)], (FILE)); \
3154 break; \
3155 } \
3156 } while (0)
3157
3158 /* a letter which is not needed by the normal asm syntax, which
3159 we can use for operand syntax in the extended asm */
3160
3161 #define ASM_OPERAND_LETTER '#'
3162 #define RET return ""
3163 #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
3164 \f
3165 /* Define the codes that are matched by predicates in i386.c. */
3166
3167 #define PREDICATE_CODES \
3168 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
3169 SYMBOL_REF, LABEL_REF, CONST}}, \
3170 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3171 SYMBOL_REF, LABEL_REF, CONST}}, \
3172 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
3173 SYMBOL_REF, LABEL_REF, CONST}}, \
3174 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3175 SYMBOL_REF, LABEL_REF, CONST}}, \
3176 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3177 SYMBOL_REF, LABEL_REF, CONST}}, \
3178 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3179 SYMBOL_REF, LABEL_REF, CONST}}, \
3180 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3181 SYMBOL_REF, LABEL_REF}}, \
3182 {"shiftdi_operand", {SUBREG, REG, MEM}}, \
3183 {"const_int_1_operand", {CONST_INT}}, \
3184 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3185 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3186 LABEL_REF, SUBREG, REG, MEM}}, \
3187 {"pic_symbolic_operand", {CONST}}, \
3188 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
3189 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
3190 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
3191 {"const1_operand", {CONST_INT}}, \
3192 {"const248_operand", {CONST_INT}}, \
3193 {"incdec_operand", {CONST_INT}}, \
3194 {"mmx_reg_operand", {REG}}, \
3195 {"reg_no_sp_operand", {SUBREG, REG}}, \
3196 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3197 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
3198 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
3199 {"q_regs_operand", {SUBREG, REG}}, \
3200 {"non_q_regs_operand", {SUBREG, REG}}, \
3201 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
3202 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
3203 GE, UNGE, LTGT, UNEQ}}, \
3204 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
3205 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
3206 }}, \
3207 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
3208 GTU, UNORDERED, ORDERED, UNLE, UNLT, \
3209 UNGE, UNGT, LTGT, UNEQ }}, \
3210 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
3211 {"ext_register_operand", {SUBREG, REG}}, \
3212 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
3213 {"mult_operator", {MULT}}, \
3214 {"div_operator", {DIV}}, \
3215 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
3216 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
3217 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
3218 LSHIFTRT, ROTATERT}}, \
3219 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
3220 {"memory_displacement_operand", {MEM}}, \
3221 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3222 LABEL_REF, SUBREG, REG, MEM, AND}}, \
3223 {"long_memory_operand", {MEM}},
3224
3225 /* A list of predicates that do special things with modes, and so
3226 should not elicit warnings for VOIDmode match_operand. */
3227
3228 #define SPECIAL_MODE_PREDICATES \
3229 "ext_register_operand",
3230 \f
3231 /* CM_32 is used by 32bit ABI
3232 CM_SMALL is small model assuming that all code and data fits in the first
3233 31bits of address space.
3234 CM_KERNEL is model assuming that all code and data fits in the negative
3235 31bits of address space.
3236 CM_MEDIUM is model assuming that code fits in the first 31bits of address
3237 space. Size of data is unlimited.
3238 CM_LARGE is model making no assumptions about size of particular sections.
3239
3240 CM_SMALL_PIC is model for PIC libraries assuming that code+data+got/plt
3241 tables first in 31bits of address space.
3242 */
3243 enum cmodel {
3244 CM_32,
3245 CM_SMALL,
3246 CM_KERNEL,
3247 CM_MEDIUM,
3248 CM_LARGE,
3249 CM_SMALL_PIC
3250 };
3251
3252 /* Size of the RED_ZONE area. */
3253 #define RED_ZONE_SIZE 128
3254 /* Reserved area of the red zone for temporaries. */
3255 #define RED_ZONE_RESERVE 8
3256 extern const char *ix86_debug_arg_string, *ix86_debug_addr_string;
3257
3258 enum asm_dialect {
3259 ASM_ATT,
3260 ASM_INTEL
3261 };
3262 extern const char *ix86_asm_string;
3263 extern enum asm_dialect ix86_asm_dialect;
3264 /* Value of -mcmodel specified by user. */
3265 extern const char *ix86_cmodel_string;
3266 extern enum cmodel ix86_cmodel;
3267 \f
3268 /* Variables in i386.c */
3269 extern const char *ix86_cpu_string; /* for -mcpu=<xxx> */
3270 extern const char *ix86_arch_string; /* for -march=<xxx> */
3271 extern const char *ix86_fpmath_string; /* for -mfpmath=<xxx> */
3272 extern const char *ix86_regparm_string; /* # registers to use to pass args */
3273 extern const char *ix86_align_loops_string; /* power of two alignment for loops */
3274 extern const char *ix86_align_jumps_string; /* power of two alignment for non-loop jumps */
3275 extern const char *ix86_align_funcs_string; /* power of two alignment for functions */
3276 extern const char *ix86_preferred_stack_boundary_string;/* power of two alignment for stack boundary */
3277 extern const char *ix86_branch_cost_string; /* values 1-5: see jump.c */
3278 extern int ix86_regparm; /* ix86_regparm_string as a number */
3279 extern int ix86_preferred_stack_boundary; /* preferred stack boundary alignment in bits */
3280 extern int ix86_branch_cost; /* values 1-5: see jump.c */
3281 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; /* smalled class containing REGNO */
3282 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
3283 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
3284 \f
3285 /* To properly truncate FP values into integers, we need to set i387 control
3286 word. We can't emit proper mode switching code before reload, as spills
3287 generated by reload may truncate values incorrectly, but we still can avoid
3288 redundant computation of new control word by the mode switching pass.
3289 The fldcw instructions are still emitted redundantly, but this is probably
3290 not going to be noticeable problem, as most CPUs do have fast path for
3291 the sequence.
3292
3293 The machinery is to emit simple truncation instructions and split them
3294 before reload to instructions having USEs of two memory locations that
3295 are filled by this code to old and new control word.
3296
3297 Post-reload pass may be later used to eliminate the redundant fildcw if
3298 needed. */
3299
3300 enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY};
3301
3302 /* Define this macro if the port needs extra instructions inserted
3303 for mode switching in an optimizing compilation. */
3304
3305 #define OPTIMIZE_MODE_SWITCHING(ENTITY) 1
3306
3307 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
3308 initializer for an array of integers. Each initializer element N
3309 refers to an entity that needs mode switching, and specifies the
3310 number of different modes that might need to be set for this
3311 entity. The position of the initializer in the initializer -
3312 starting counting at zero - determines the integer that is used to
3313 refer to the mode-switched entity in question. */
3314
3315 #define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY }
3316
3317 /* ENTITY is an integer specifying a mode-switched entity. If
3318 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
3319 return an integer value not larger than the corresponding element
3320 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
3321 must be switched into prior to the execution of INSN. */
3322
3323 #define MODE_NEEDED(ENTITY, I) \
3324 (GET_CODE (I) == CALL_INSN \
3325 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
3326 || GET_CODE (PATTERN (I)) == ASM_INPUT))\
3327 ? FP_CW_UNINITIALIZED \
3328 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \
3329 ? FP_CW_ANY \
3330 : FP_CW_STORED)
3331
3332 /* This macro specifies the order in which modes for ENTITY are
3333 processed. 0 is the highest priority. */
3334
3335 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
3336
3337 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
3338 is the set of hard registers live at the point where the insn(s)
3339 are to be inserted. */
3340
3341 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3342 ((MODE) == FP_CW_STORED \
3343 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
3344 assign_386_stack_local (HImode, 2)), 0\
3345 : 0)
3346 \f
3347 /* Avoid renaming of stack registers, as doing so in combination with
3348 scheduling just increases amount of live registers at time and in
3349 the turn amount of fxch instructions needed.
3350
3351 ??? Maybe Pentium chips benefits from renaming, someone can try... */
3352
3353 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
3354 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
3355
3356 \f
3357 /*
3358 Local variables:
3359 version-control: t
3360 End:
3361 */
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