| blob | 781ed3725144b437daff3f199e5cab6e1130f54d |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
61 /* Not really meaningful values, but at least something. */
62 #ifndef SIMULTANEOUS_PREFETCHES
63 #define SIMULTANEOUS_PREFETCHES 3
64 #endif
65 #ifndef PREFETCH_BLOCK
66 #define PREFETCH_BLOCK 32
67 #endif
68 #ifndef HAVE_prefetch
69 #define HAVE_prefetch 0
70 #define CODE_FOR_prefetch 0
71 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
72 #endif
74 /* Give up the prefetch optimizations once we exceed a given threshhold.
75 It is unlikely that we would be able to optimize something in a loop
76 with so many detected prefetches. */
77 #define MAX_PREFETCHES 100
78 /* The number of prefetch blocks that are beneficial to fetch at once before
79 a loop with a known (and low) iteration count. */
80 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
81 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
82 since it is likely that the data are already in the cache. */
83 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
85 /* Parameterize some prefetch heuristics so they can be turned on and off
86 easily for performance testing on new architectures. These can be
87 defined in target-dependent files. */
89 /* Prefetch is worthwhile only when loads/stores are dense. */
90 #ifndef PREFETCH_ONLY_DENSE_MEM
91 #define PREFETCH_ONLY_DENSE_MEM 1
92 #endif
94 /* Define what we mean by "dense" loads and stores; This value divided by 256
95 is the minimum percentage of memory references that worth prefetching. */
96 #ifndef PREFETCH_DENSE_MEM
97 #define PREFETCH_DENSE_MEM 220
98 #endif
100 /* Do not prefetch for a loop whose iteration count is known to be low. */
101 #ifndef PREFETCH_NO_LOW_LOOPCNT
102 #define PREFETCH_NO_LOW_LOOPCNT 1
103 #endif
105 /* Define what we mean by a "low" iteration count. */
106 #ifndef PREFETCH_LOW_LOOPCNT
107 #define PREFETCH_LOW_LOOPCNT 32
108 #endif
110 /* Do not prefetch for a loop that contains a function call; such a loop is
111 probably not an internal loop. */
112 #ifndef PREFETCH_NO_CALL
113 #define PREFETCH_NO_CALL 1
114 #endif
116 /* Do not prefetch accesses with an extreme stride. */
117 #ifndef PREFETCH_NO_EXTREME_STRIDE
118 #define PREFETCH_NO_EXTREME_STRIDE 1
119 #endif
121 /* Define what we mean by an "extreme" stride. */
122 #ifndef PREFETCH_EXTREME_STRIDE
123 #define PREFETCH_EXTREME_STRIDE 4096
124 #endif
126 /* Define a limit to how far apart indices can be and still be merged
127 into a single prefetch. */
128 #ifndef PREFETCH_EXTREME_DIFFERENCE
129 #define PREFETCH_EXTREME_DIFFERENCE 4096
130 #endif
132 /* Issue prefetch instructions before the loop to fetch data to be used
133 in the first few loop iterations. */
134 #ifndef PREFETCH_BEFORE_LOOP
135 #define PREFETCH_BEFORE_LOOP 1
136 #endif
138 /* Do not handle reversed order prefetches (negative stride). */
139 #ifndef PREFETCH_NO_REVERSE_ORDER
140 #define PREFETCH_NO_REVERSE_ORDER 1
141 #endif
143 /* Prefetch even if the GIV is in conditional code. */
144 #ifndef PREFETCH_CONDITIONAL
145 #define PREFETCH_CONDITIONAL 1
146 #endif
148 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
149 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
151 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
152 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
153 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
155 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
156 ((REGNO) < FIRST_PSEUDO_REGISTER \
157 ? (int) HARD_REGNO_NREGS ((REGNO), GET_MODE (SET_DEST)) : 1)
160 /* Vector mapping INSN_UIDs to luids.
161 The luids are like uids but increase monotonically always.
162 We use them to see whether a jump comes from outside a given loop. */
166 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
167 number the insn is contained in. */
171 /* 1 + largest uid of any insn. */
175 /* Number of loops detected in current function. Used as index to the
176 next few tables. */
180 /* Bound on pseudo register number before loop optimization.
181 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
184 /* The value to pass to the next call of reg_scan_update. */
186 \f
187 /* During the analysis of a loop, a chain of `struct movable's
188 is made to record all the movable insns found.
189 Then the entire chain can be scanned to decide which to move. */
191 struct movable
192 {
197 of any registers used within the LIBCALL. */
199 that must be moved with this one. */
202 may be adjusted when matching movables
203 that load the same value are found. */
205 including other movables that force this
206 or match this one. */
208 a low part that we should avoid changing when
209 clearing the rest of the reg. */
213 /* If PARTIAL is 1, GLOBAL means something different:
214 that the reg is live outside the range from where it is set
215 to the following label. */
219 In particular, moving it does not make it
220 invariant. */
222 load SRC, rather than copying INSN. */
224 first insn of a consecutive sets group. */
227 the original insn with a copy from that
228 pseudo, rather than deleting it. */
232 };
237 /* Forward declarations. */
252 #if 0
254 #endif
284 rtx *));
366 {
367 rtx match;
368 rtx replacement;
369 rtx insn;
372 /* Nonzero iff INSN is between START and END, inclusive. */
373 #define INSN_IN_RANGE_P(INSN, START, END) \
374 (INSN_UID (INSN) < max_uid_for_loop \
375 && INSN_LUID (INSN) >= INSN_LUID (START) \
376 && INSN_LUID (INSN) <= INSN_LUID (END))
378 /* Indirect_jump_in_function is computed once per function. */
386 rtx));
387 \f
388 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
389 copy the value of the strength reduced giv to its original register. */
392 /* Cost of using a register, to normalize the benefits of a giv. */
395 void
397 {
403 }
404 \f
405 /* Compute the mapping from uids to luids.
406 LUIDs are numbers assigned to insns, like uids,
407 except that luids increase monotonically through the code.
408 Start at insn START and stop just before END. Assign LUIDs
409 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
410 static int
414 {
416 rtx insn;
419 {
422 /* Don't assign luids to line-number NOTEs, so that the distance in
423 luids between two insns is not affected by -g. */
427 else
428 /* Give a line number note the same luid as preceding insn. */
430 }
432 }
433 \f
434 /* Entry point of this file. Perform loop optimization
435 on the current function. F is the first insn of the function
436 and DUMPFILE is a stream for output of a trace of actions taken
437 (or 0 if none should be output). */
439 void
441 /* f is the first instruction of a chain of insns for one function */
442 rtx f;
445 {
446 rtx insn;
461 /* Count the number of loops. */
465 {
468 max_loop_num++;
469 }
471 /* Don't waste time if no loops. */
477 /* Get size to use for tables indexed by uids.
478 Leave some space for labels allocated by find_and_verify_loops. */
485 /* Allocate storage for array of loops. */
489 /* Find and process each loop.
490 First, find them, and record them in order of their beginnings. */
493 /* Allocate and initialize auxiliary loop information. */
498 /* Now find all register lifetimes. This must be done after
499 find_and_verify_loops, because it might reorder the insns in the
500 function. */
503 /* This must occur after reg_scan so that registers created by gcse
504 will have entries in the register tables.
506 We could have added a call to reg_scan after gcse_main in toplev.c,
507 but moving this call to init_alias_analysis is more efficient. */
510 /* See if we went too far. Note that get_max_uid already returns
511 one more that the maximum uid of all insn. */
514 /* Now reset it to the actual size we need. See above. */
517 /* find_and_verify_loops has already called compute_luids, but it
518 might have rearranged code afterwards, so we need to recompute
519 the luids now. */
522 /* Don't leave gaps in uid_luid for insns that have been
523 deleted. It is possible that the first or last insn
524 using some register has been deleted by cross-jumping.
525 Make sure that uid_luid for that former insn's uid
526 points to the general area where that insn used to be. */
528 {
532 }
537 /* Determine if the function has indirect jump. On some systems
538 this prevents low overhead loop instructions from being used. */
541 /* Now scan the loops, last ones first, since this means inner ones are done
542 before outer ones. */
544 {
549 }
553 /* Clean up. */
558 }
559 \f
560 /* Returns the next insn, in execution order, after INSN. START and
561 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
562 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
563 insn-stream; it is used with loops that are entered near the
564 bottom. */
566 static rtx
569 rtx insn;
570 {
574 {
576 /* Go to the top of the loop, and continue there. */
578 else
579 /* We're done. */
581 }
584 /* We're done. */
588 }
590 /* Optimize one loop described by LOOP. */
592 /* ??? Could also move memory writes out of loops if the destination address
593 is invariant, the source is invariant, the memory write is not volatile,
594 and if we can prove that no read inside the loop can read this address
595 before the write occurs. If there is a read of this address after the
596 write, then we can also mark the memory read as invariant. */
598 static void
602 {
608 rtx p;
609 /* 1 if we are scanning insns that could be executed zero times. */
611 /* 1 if we are scanning insns that might never be executed
612 due to a subroutine call which might exit before they are reached. */
614 /* Number of insns in the loop. */
618 /* The SET from an insn, if it is the only SET in the insn. */
620 /* Chain describing insns movable in current loop. */
622 /* Ratio of extra register life span we can justify
623 for saving an instruction. More if loop doesn't call subroutines
624 since in that case saving an insn makes more difference
625 and more registers are available. */
627 /* Nonzero if we are scanning instructions in a sub-loop. */
636 /* Determine whether this loop starts with a jump down to a test at
637 the end. This will occur for a small number of loops with a test
638 that is too complex to duplicate in front of the loop.
640 We search for the first insn or label in the loop, skipping NOTEs.
641 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
642 (because we might have a loop executed only once that contains a
643 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
644 (in case we have a degenerate loop).
646 Note that if we mistakenly think that a loop is entered at the top
647 when, in fact, it is entered at the exit test, the only effect will be
648 slightly poorer optimization. Making the opposite error can generate
649 incorrect code. Since very few loops now start with a jump to the
650 exit test, the code here to detect that case is very conservative. */
653 p != loop_end
659 ;
663 /* If loop end is the end of the current function, then emit a
664 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
665 note insn. This is the position we use when sinking insns out of
666 the loop. */
669 else
672 /* Set up variables describing this loop. */
676 /* If loop has a jump before the first label,
677 the true entry is the target of that jump.
678 Start scan from there.
679 But record in LOOP->TOP the place where the end-test jumps
680 back to so we can scan that after the end of the loop. */
682 /* Loop entry must be unconditional jump (and not a RETURN) */
685 /* Check to see whether the jump actually
686 jumps out of the loop (meaning it's no loop).
687 This case can happen for things like
688 do {..} while (0). If this label was generated previously
689 by loop, we can't tell anything about it and have to reject
690 the loop. */
692 {
695 }
697 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
698 as required by loop_reg_used_before_p. So skip such loops. (This
699 test may never be true, but it's best to play it safe.)
701 Also, skip loops where we do not start scanning at a label. This
702 test also rejects loops starting with a JUMP_INSN that failed the
703 test above. */
707 {
712 }
714 /* Allocate extra space for REGs that might be created by load_mems.
715 We allocate a little extra slop as well, in the hopes that we
716 won't have to reallocate the regs array. */
721 {
727 }
729 /* Scan through the loop finding insns that are safe to move.
730 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
731 this reg will be considered invariant for subsequent insns.
732 We consider whether subsequent insns use the reg
733 in deciding whether it is worth actually moving.
735 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
736 and therefore it is possible that the insns we are scanning
737 would never be executed. At such times, we must make sure
738 that it is safe to execute the insn once instead of zero times.
739 When MAYBE_NEVER is 0, all insns will be executed at least once
740 so that is not a problem. */
745 {
747 in_libcall--;
749 {
752 in_libcall++;
756 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
758 #endif
760 {
768 /* Figure out what to use as a source of this insn. If a
769 REG_EQUIV note is given or if a REG_EQUAL note with a
770 constant operand is specified, use it as the source and
771 mark that we should move this insn by calling
772 emit_move_insn rather that duplicating the insn.
774 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL
775 note is present. */
779 else
780 {
785 {
787 /* A libcall block can use regs that don't appear in
788 the equivalent expression. To move the libcall,
789 we must move those regs too. */
791 }
792 }
794 /* For parallels, add any possible uses to the dependencies, as
795 we can't move the insn without resolving them first. */
797 {
799 {
802 dependencies
804 dependencies);
805 }
806 }
809 than the one where it is set (meaning that
810 something after this point in the loop might
811 depend on its value before the set). */
813 /* And the set is not guaranteed to be executed once
814 the loop starts, or the value before the set is
815 needed before the set occurs...
817 ??? Note we have quadratic behavior here, mitigated
818 by the fact that the previous test will often fail for
819 large loops. Rather than re-scanning the entire loop
820 each time for register usage, we should build tables
821 of the register usage and use them here instead. */
822 && (maybe_never
824 /* It is unsafe to move the set. However, it may be OK to
825 move the source into a new psuedo, and subsitute a
826 reg-to-reg copy for the original insn.
828 This code used to consider it OK to move a set of a variable
829 which was not created by the user and not used in an exit
830 test.
831 That behavior is incorrect and was removed. */
834 /* Don't try to optimize a register that was made
835 by loop-optimization for an inner loop.
836 We don't know its life-span, so we can't compute
837 the benefit. */
839 ;
840 /* Don't move the source and add a reg-to-reg copy with -Os
841 (this certainly increases size) or if the source is
842 already a reg (the motion will gain nothing). */
847 ;
850 || (tem2
853 || (tem1
854 = consec_sets_invariant_p
857 p)))
858 /* If the insn can cause a trap (such as divide by zero),
859 can't move it unless it's guaranteed to be executed
860 once loop is entered. Even a function call might
861 prevent the trap insn from being reached
862 (since it might exit!) */
865 {
869 /* A potential lossage is where we have a case where two insns
870 can be combined as long as they are both in the loop, but
871 we move one of them outside the loop. For large loops,
872 this can lose. The most common case of this is the address
873 of a function being called.
875 Therefore, if this register is marked as being used
876 exactly once if we are in a loop with calls
877 (a "large loop"), see if we can replace the usage of
878 this register with the source of this SET. If we can,
879 delete this insn.
881 Don't do this if P has a REG_RETVAL note or if we have
882 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
894 && (! SMALL_REGISTER_CLASSES
898 /* This test is not redundant; SET_SRC (set) might be
899 a call-clobbered register and the life of REGNO
900 might span a call. */
907 {
908 /* Replace any usage in a REG_EQUAL note. Must copy
909 the new source, so that we don't get rtx sharing
910 between the SET_SOURCE and REG_NOTES of insn p. */
912 = (replace_rtx
918 i++)
921 }
930 m->consec
941 /* Set M->cond if either loop_invariant_p
942 or consec_sets_invariant_p returned 2
943 (only conditionally invariant). */
953 /* Add M to the end of the chain MOVABLES. */
957 {
958 /* It is possible for the first instruction to have a
959 REG_EQUAL note but a non-invariant SET_SRC, so we must
960 remember the status of the first instruction in case
961 the last instruction doesn't have a REG_EQUAL note. */
964 /* Skip this insn, not checking REG_LIBCALL notes. */
966 /* Skip the consecutive insns, if there are any. */
968 /* Back up to the last insn of the consecutive group. */
971 /* We must now reset m->move_insn, m->is_equiv, and
972 possibly m->set_src to correspond to the effects of
973 all the insns. */
977 else
978 {
982 else
985 }
986 m->is_equiv
988 }
989 }
990 /* If this register is always set within a STRICT_LOW_PART
991 or set to zero, then its high bytes are constant.
992 So clear them outside the loop and within the loop
993 just load the low bytes.
994 We must check that the machine has an instruction to do so.
995 Also, if the value loaded into the register
996 depends on the same register, this cannot be done. */
1006 {
1009 {
1024 /* If the insn may not be executed on some cycles,
1025 we can't clear the whole reg; clear just high part.
1026 Not even if the reg is used only within this loop.
1027 Consider this:
1028 while (1)
1029 while (s != t) {
1030 if (foo ()) x = *s;
1031 use (x);
1032 }
1033 Clearing x before the inner loop could clobber a value
1034 being saved from the last time around the outer loop.
1035 However, if the reg is not used outside this loop
1036 and all uses of the register are in the same
1037 basic block as the store, there is no problem.
1039 If this insn was made by loop, we don't know its
1040 INSN_LUID and hence must make a conservative
1041 assumption. */
1044 || (labels_in_range_p
1048 else
1057 i++)
1059 /* Add M to the end of the chain MOVABLES. */
1061 }
1062 }
1063 }
1064 }
1065 /* Past a call insn, we get to insns which might not be executed
1066 because the call might exit. This matters for insns that trap.
1067 Constant and pure call insns always return, so they don't count. */
1070 /* Past a label or a jump, we get to insns for which we
1071 can't count on whether or how many times they will be
1072 executed during each iteration. Therefore, we can
1073 only move out sets of trivial variables
1074 (those not used after the loop). */
1075 /* Similar code appears twice in strength_reduce. */
1077 /* If we enter the loop in the middle, and scan around to the
1078 beginning, don't set maybe_never for that. This must be an
1079 unconditional jump, otherwise the code at the top of the
1080 loop might never be executed. Unconditional jumps are
1081 followed by a barrier then the loop_end. */
1087 {
1088 /* At the virtual top of a converted loop, insns are again known to
1089 be executed: logically, the loop begins here even though the exit
1090 code has been duplicated. */
1094 loop_depth++;
1096 loop_depth--;
1097 }
1098 }
1100 /* If one movable subsumes another, ignore that other. */
1104 /* For each movable insn, see if the reg that it loads
1105 leads when it dies right into another conditionally movable insn.
1106 If so, record that the second insn "forces" the first one,
1107 since the second can be moved only if the first is. */
1111 /* See if there are multiple movable insns that load the same value.
1112 If there are, make all but the first point at the first one
1113 through the `match' field, and add the priorities of them
1114 all together as the priority of the first. */
1118 /* Now consider each movable insn to decide whether it is worth moving.
1119 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1121 For machines with few registers this increases code size, so do not
1122 move moveables when optimizing for code size on such machines.
1123 (The 18 below is the value for i386.) */
1127 {
1130 /* Recalculate regs->array if move_movables has created new
1131 registers. */
1133 {
1139 ;
1144 }
1145 }
1147 /* Now candidates that still are negative are those not moved.
1148 Change regs->array[I].set_in_loop to indicate that those are not actually
1149 invariant. */
1154 /* Now that we've moved some things out of the loop, we might be able to
1155 hoist even more memory references. */
1158 /* Recalculate regs->array if load_mems has created new registers. */
1166 ;
1173 {
1175 /* Ensure our label doesn't go away. */
1186 }
1189 /* The movable information is required for strength reduction. */
1195 }
1196 \f
1197 /* Add elements to *OUTPUT to record all the pseudo-regs
1198 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1200 void
1204 {
1212 {
1230 }
1234 {
1238 {
1247 }
1248 }
1249 }
1250 \f
1251 /* Check what regs are referred to in the libcall block ending with INSN,
1252 aside from those mentioned in the equivalent value.
1253 If there are none, return 0.
1254 If there are one or more, return an EXPR_LIST containing all of them. */
1256 rtx
1259 {
1264 /* First, find all the regs used in the libcall block
1265 that are not mentioned as inputs to the result. */
1268 {
1273 }
1276 }
1277 \f
1278 /* Return 1 if all uses of REG
1279 are between INSN and the end of the basic block. */
1281 static int
1284 {
1286 rtx p;
1291 /* Search this basic block for the already recorded last use of the reg. */
1293 {
1295 {
1301 /* Ordinary insn: if this is the last use, we win. */
1307 /* Jump insn: if this is the last use, we win. */
1310 /* Otherwise, it's the end of the basic block, so we lose. */
1315 /* It's the end of the basic block, so we lose. */
1320 }
1321 }
1323 /* The "last use" that was recorded can't be found after the first
1324 use. This can happen when the last use was deleted while
1325 processing an inner loop, this inner loop was then completely
1326 unrolled, and the outer loop is always exited after the inner loop,
1327 so that everything after the first use becomes a single basic block. */
1329 }
1330 \f
1331 /* Compute the benefit of eliminating the insns in the block whose
1332 last insn is LAST. This may be a group of insns used to compute a
1333 value directly or can contain a library call. */
1335 static int
1337 rtx last;
1338 {
1339 rtx insn;
1344 {
1347 routine. */
1351 benefit++;
1352 }
1355 }
1356 \f
1357 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1359 static rtx
1361 rtx insn;
1363 {
1365 {
1366 rtx temp;
1368 /* If first insn of libcall sequence, skip to end. */
1369 /* Do this at start of loop, since INSN is guaranteed to
1370 be an insn here. */
1375 do
1378 }
1381 }
1383 /* Ignore any movable whose insn falls within a libcall
1384 which is part of another movable.
1385 We make use of the fact that the movable for the libcall value
1386 was made later and so appears later on the chain. */
1388 static void
1391 {
1395 {
1396 /* Is this a movable for the value of a libcall? */
1399 {
1400 rtx insn;
1401 /* Check for earlier movables inside that range,
1402 and mark them invalid. We cannot use LUIDs here because
1403 insns created by loop.c for prior loops don't have LUIDs.
1404 Rather than reject all such insns from movables, we just
1405 explicitly check each insn in the libcall (since invariant
1406 libcalls aren't that common). */
1411 }
1412 }
1413 }
1415 /* For each movable insn, see if the reg that it loads
1416 leads when it dies right into another conditionally movable insn.
1417 If so, record that the second insn "forces" the first one,
1418 since the second can be moved only if the first is. */
1420 static void
1423 {
1427 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1429 {
1432 /* ??? Could this be a bug? What if CSE caused the
1433 register of M1 to be used after this insn?
1434 Since CSE does not update regno_last_uid,
1435 this insn M->insn might not be where it dies.
1436 But very likely this doesn't matter; what matters is
1437 that M's reg is computed from M1's reg. */
1442 /* If m->consec, m->set_src isn't valid. */
1446 /* Increase the priority of the moving the first insn
1447 since it permits the second to be moved as well. */
1449 {
1453 }
1454 }
1455 }
1456 \f
1457 /* Find invariant expressions that are equal and can be combined into
1458 one register. */
1460 static void
1464 {
1469 /* Regs that are set more than once are not allowed to match
1470 or be matched. I'm no longer sure why not. */
1471 /* Only pseudo registers are allowed to match or be matched,
1472 since move_movables does not validate the change. */
1473 /* Perhaps testing m->consec_sets would be more appropriate here? */
1480 {
1487 /* We want later insns to match the first one. Don't make the first
1488 one match any later ones. So start this loop at m->next. */
1494 /* A reg used outside the loop mustn't be eliminated. */
1496 /* A reg used for zero-extending mustn't be eliminated. */
1499 ||
1500 (
1501 /* Can combine regs with different modes loaded from the
1502 same constant only if the modes are the same or
1503 if both are integer modes with M wider or the same
1504 width as M1. The check for integer is redundant, but
1505 safe, since the only case of differing destination
1506 modes with equal sources is when both sources are
1507 VOIDmode, i.e., CONST_INT. */
1513 /* See if the source of M1 says it matches M. */
1520 {
1526 }
1527 }
1529 /* Now combine the regs used for zero-extension.
1530 This can be done for those not marked `global'
1531 provided their lives don't overlap. */
1535 {
1538 /* Combine all the registers for extension from mode MODE.
1539 Don't combine any that are used outside this loop. */
1543 {
1550 {
1551 /* First one: don't check for overlap, just record it. */
1554 }
1556 /* Make sure they extend to the same mode.
1557 (Almost always true.) */
1561 /* We already have one: check for overlap with those
1562 already combined together. */
1569 /* No overlap: we can combine this with the others. */
1575 overlap:
1576 ;
1577 }
1578 }
1580 /* Clean up. */
1582 }
1584 /* Returns the number of movable instructions in LOOP that were not
1585 moved outside the loop. */
1587 static int
1590 {
1599 }
1601 \f
1602 /* Return 1 if regs X and Y will become the same if moved. */
1604 static int
1608 {
1625 }
1627 /* Return 1 if X and Y are identical-looking rtx's.
1628 This is the Lisp function EQUAL for rtx arguments.
1630 If two registers are matching movables or a movable register and an
1631 equivalent constant, consider them equal. */
1633 static int
1638 {
1652 /* If we have a register and a constant, they may sometimes be
1653 equal. */
1656 {
1661 }
1664 {
1669 }
1671 /* Otherwise, rtx's of different codes cannot be equal. */
1675 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1676 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1681 /* These three types of rtx's can be compared nonrecursively. */
1690 /* Compare the elements. If any pair of corresponding elements
1691 fail to match, return 0 for the whole things. */
1695 {
1697 {
1709 /* Two vectors must have the same length. */
1713 /* And the corresponding elements must match. */
1732 /* These are just backpointers, so they don't matter. */
1738 /* It is believed that rtx's at this level will never
1739 contain anything but integers and other rtx's,
1740 except for within LABEL_REFs and SYMBOL_REFs. */
1743 }
1744 }
1746 }
1747 \f
1748 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1749 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1750 references is incremented once for each added note. */
1752 static void
1754 rtx x;
1755 rtx insns;
1756 {
1760 rtx insn;
1763 {
1764 /* This code used to ignore labels that referred to dispatch tables to
1765 avoid flow generating (slighly) worse code.
1767 We no longer ignore such label references (see LABEL_REF handling in
1768 mark_jump_label for additional information). */
1771 {
1776 }
1777 }
1781 {
1787 }
1788 }
1789 \f
1790 /* Scan MOVABLES, and move the insns that deserve to be moved.
1791 If two matching movables are combined, replace one reg with the
1792 other throughout. */
1794 static void
1800 {
1805 rtx p;
1808 /* Map of pseudo-register replacements to handle combining
1809 when we move several insns that load the same value
1810 into different pseudo-registers. */
1815 {
1816 /* Describe this movable insn. */
1819 {
1840 }
1842 /* Ignore the insn if it's already done (it matched something else).
1843 Otherwise, see if it is now safe to move. */
1855 {
1857 rtx p;
1860 /* We have an insn that is safe to move.
1861 Compute its desirability. */
1872 /* An insn MUST be moved if we already moved something else
1873 which is safe only if this one is moved too: that is,
1874 if already_moved[REGNO] is nonzero. */
1876 /* An insn is desirable to move if the new lifetime of the
1877 register is no more than THRESHOLD times the old lifetime.
1878 If it's not desirable, it means the loop is so big
1879 that moving won't speed things up much,
1880 and it is liable to make register usage worse. */
1882 /* It is also desirable to move if it can be moved at no
1883 extra cost because something else was already moved. */
1886 || flag_move_all_movables
1891 {
1900 /* Now move the insns that set the reg. */
1903 {
1906 /* Find the end of this chain of matching regs.
1907 Thus, we load each reg in the chain from that one reg.
1908 And that reg is loaded with 0 directly,
1909 since it has ->match == 0. */
1915 /* Mark the moved, invariant reg as being allowed to
1916 share a hard reg with the other matching invariant. */
1920 regs_may_share
1923 regs_may_share));
1931 }
1932 /* If we are to re-generate the item being moved with a
1933 new move insn, first delete what we have and then emit
1934 the move insn before the loop. */
1936 {
1940 {
1941 /* If this is the first insn of a library call sequence,
1942 something is very wrong. */
1947 /* If this is the last insn of a libcall sequence, then
1948 delete every insn in the sequence except the last.
1949 The last insn is handled in the normal manner. */
1952 {
1956 }
1961 /* simplify_giv_expr expects that it can walk the insns
1962 at m->insn forwards and see this old sequence we are
1963 tossing here. delete_insn does preserve the next
1964 pointers, but when we skip over a NOTE we must fix
1965 it up. Otherwise that code walks into the non-deleted
1966 insn stream. */
1971 {
1972 /* Replace the original insn with a move from
1973 our newly created temp. */
1979 }
1980 }
1999 /* The more regs we move, the less we like moving them. */
2001 }
2002 else
2003 {
2005 {
2008 /* If first insn of libcall sequence, skip to end. */
2009 /* Do this at start of loop, since p is guaranteed to
2010 be an insn here. */
2015 /* If last insn of libcall sequence, move all
2016 insns except the last before the loop. The last
2017 insn is handled in the normal manner. */
2020 {
2028 {
2029 rtx body;
2030 rtx n;
2031 rtx next;
2038 /* Find the next insn after TEMP,
2039 not counting USE or NOTE insns. */
2047 /* If that is the call, this may be the insn
2048 that loads the function address.
2050 Extract the function address from the insn
2051 that loads it into a register.
2052 If this insn was cse'd, we get incorrect code.
2054 So emit a new move insn that copies the
2055 function address into the register that the
2056 call insn will use. flow.c will delete any
2057 redundant stores that we have created. */
2062 NULL_RTX)))
2063 {
2069 }
2070 /* We have the call insn.
2071 If it uses the register we suspect it might,
2072 load it with the correct address directly. */
2077 gen_move_insn
2081 {
2083 /* Because the USAGE information potentially
2084 contains objects other than hard registers
2085 we need to copy it. */
2089 }
2090 else
2099 }
2102 }
2104 {
2105 /* P sets REG to zero; but we should clear only
2106 the bits that are not covered by the mode
2107 m->savemode. */
2109 rtx sequence;
2110 rtx tem;
2113 tem = expand_simple_binop
2126 }
2128 {
2130 /* Because the USAGE information potentially
2131 contains objects other than hard registers
2132 we need to copy it. */
2136 }
2138 {
2139 rtx seq;
2140 /* The SET_SRC might not be invariant, so we must
2141 use the REG_EQUAL note. */
2153 }
2155 {
2163 }
2164 else
2168 {
2172 /* If there is a REG_EQUAL note present whose value
2173 is not loop invariant, then delete it, since it
2174 may cause problems with later optimization passes.
2175 It is possible for cse to create such notes
2176 like this as a result of record_jump_cond. */
2181 }
2190 /* If library call, now fix the REG_NOTES that contain
2191 insn pointers, namely REG_LIBCALL on FIRST
2192 and REG_RETVAL on I1. */
2194 {
2198 }
2204 /* simplify_giv_expr expects that it can walk the insns
2205 at m->insn forwards and see this old sequence we are
2206 tossing here. delete_insn does preserve the next
2207 pointers, but when we skip over a NOTE we must fix
2208 it up. Otherwise that code walks into the non-deleted
2209 insn stream. */
2214 {
2215 rtx seq;
2216 /* Replace the original insn with a move from
2217 our newly created temp. */
2223 }
2224 }
2226 /* The more regs we move, the less we like moving them. */
2228 }
2233 {
2234 /* Any other movable that loads the same register
2235 MUST be moved. */
2238 /* This reg has been moved out of one loop. */
2241 /* The reg set here is now invariant. */
2243 {
2247 }
2249 /* Change the length-of-life info for the register
2250 to say it lives at least the full length of this loop.
2251 This will help guide optimizations in outer loops. */
2254 /* This is the old insn before all the moved insns.
2255 We can't use the moved insn because it is out of range
2256 in uid_luid. Only the old insns have luids. */
2260 }
2262 /* Combine with this moved insn any other matching movables. */
2267 {
2268 rtx temp;
2270 /* Schedule the reg loaded by M1
2271 for replacement so that shares the reg of M.
2272 If the modes differ (only possible in restricted
2273 circumstances, make a SUBREG.
2275 Note this assumes that the target dependent files
2276 treat REG and SUBREG equally, including within
2277 GO_IF_LEGITIMATE_ADDRESS and in all the
2278 predicates since we never verify that replacing the
2279 original register with a SUBREG results in a
2280 recognizable insn. */
2283 else
2288 /* Get rid of the matching insn
2289 and prevent further processing of it. */
2292 /* if library call, delete all insns. */
2294 NULL_RTX)))
2296 else
2299 /* Any other movable that loads the same register
2300 MUST be moved. */
2303 /* The reg merged here is now invariant,
2304 if the reg it matches is invariant. */
2306 {
2310 i++)
2312 }
2313 }
2314 }
2317 }
2323 }
2328 /* Go through all the instructions in the loop, making
2329 all the register substitutions scheduled in REG_MAP. */
2333 {
2337 }
2339 /* Clean up. */
2342 }
2345 static void
2349 {
2352 else
2355 }
2358 static void
2361 {
2366 {
2369 }
2370 }
2371 \f
2372 #if 0
2373 /* Scan X and replace the address of any MEM in it with ADDR.
2374 REG is the address that MEM should have before the replacement. */
2376 static void
2379 {
2388 {
2400 /* Short cut for very common case. */
2405 /* Short cut for very common case. */
2410 /* If this MEM uses a reg other than the one we expected,
2411 something is wrong. */
2419 }
2423 {
2427 {
2431 }
2432 }
2433 }
2434 #endif
2435 \f
2436 /* Return the number of memory refs to addresses that vary
2437 in the rtx X. */
2439 static int
2442 rtx x;
2443 {
2454 {
2471 }
2476 {
2480 {
2484 }
2485 }
2487 }
2488 \f
2489 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2490 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2491 `unknown_address_altered', `unknown_constant_address_altered', and
2492 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2493 list `store_mems' in LOOP. */
2495 static void
2498 {
2500 rtx insn;
2504 /* The label after END. Jumping here is just like falling off the
2505 end of the loop. We use next_nonnote_insn instead of next_label
2506 as a hedge against the (pathological) case where some actual insn
2507 might end up between the two. */
2526 /* If loop opts run twice, this was set on 1st pass for 2nd. */
2531 {
2533 {
2536 }
2537 }
2541 {
2543 {
2546 {
2548 /* Count number of loops contained in this one. */
2550 }
2557 {
2560 }
2570 {
2574 {
2579 {
2582 }
2583 else
2584 {
2587 }
2589 do
2590 {
2592 {
2594 {
2595 /* Something tricky. */
2598 }
2601 {
2602 /* A jump outside the current loop. */
2605 }
2606 }
2610 }
2612 }
2613 else
2614 {
2615 /* A return, or something tricky. */
2617 }
2618 }
2619 /* FALLTHRU */
2640 }
2641 }
2643 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2645 anywhere. */
2647 /* We don't want loads for MEMs moved to a location before the
2648 one at which their stack memory becomes allocated. (Note
2649 that this is not a problem for malloc, etc., since those
2650 require actual function calls. */
2651 && ! current_function_calls_alloca
2652 /* There are ways to leave the loop other than falling off the
2653 end. */
2659 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2660 that loop_invariant_p and load_mems can use true_dependence
2661 to determine what is really clobbered. */
2663 {
2666 loop_info->store_mems
2668 }
2670 {
2674 loop_info->store_mems
2676 }
2677 }
2678 \f
2679 /* Invalidate all loops containing LABEL. */
2681 static void
2683 rtx label;
2684 {
2688 }
2690 /* Scan the function looking for loops. Record the start and end of each loop.
2691 Also mark as invalid loops any loops that contain a setjmp or are branched
2692 to from outside the loop. */
2694 static void
2696 rtx f;
2698 {
2699 rtx insn;
2700 rtx label;
2710 /* If there are jumps to undefined labels,
2711 treat them as jumps out of any/all loops.
2712 This also avoids writing past end of tables when there are no loops. */
2715 /* Find boundaries of loops, mark which loops are contained within
2716 loops, and invalidate loops that have setjmp. */
2721 {
2724 {
2728 num_loops++;
2752 }
2756 {
2757 /* In this case, we must invalidate our current loop and any
2758 enclosing loop. */
2760 {
2766 }
2767 }
2769 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2770 enclosing loop, but this doesn't matter. */
2772 }
2774 /* Any loop containing a label used in an initializer must be invalidated,
2775 because it can be jumped into from anywhere. */
2779 /* Any loop containing a label used for an exception handler must be
2780 invalidated, because it can be jumped into from anywhere. */
2783 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2784 loop that it is not contained within, that loop is marked invalid.
2785 If any INSN or CALL_INSN uses a label's address, then the loop containing
2786 that label is marked invalid, because it could be jumped into from
2787 anywhere.
2789 Also look for blocks of code ending in an unconditional branch that
2790 exits the loop. If such a block is surrounded by a conditional
2791 branch around the block, move the block elsewhere (see below) and
2792 invert the jump to point to the code block. This may eliminate a
2793 label in our loop and will simplify processing by both us and a
2794 possible second cse pass. */
2798 {
2802 {
2806 }
2813 /* See if this is an unconditional branch outside the loop. */
2821 {
2822 rtx p;
2828 /* Go backwards until we reach the start of the loop, a label,
2829 or a JUMP_INSN. */
2836 ;
2838 /* Check for the case where we have a jump to an inner nested
2839 loop, and do not perform the optimization in that case. */
2842 {
2845 {
2850 }
2851 }
2853 /* Make sure that the target of P is within the current loop. */
2859 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2860 we have a block of code to try to move.
2862 We look backward and then forward from the target of INSN
2863 to find a BARRIER at the same loop depth as the target.
2864 If we find such a BARRIER, we make a new label for the start
2865 of the block, invert the jump in P and point it to that label,
2866 and move the block of code to the spot we found. */
2871 /* Just ignore jumps to labels that were never emitted.
2872 These always indicate compilation errors. */
2876 /* If it's not safe to move the sequence, then we
2877 mustn't try. */
2880 {
2881 rtx target
2885 rtx tmp;
2887 /* Search for possible garbage past the conditional jumps
2888 and look for the last barrier. */
2896 /* Don't move things inside a tablejump. */
2909 /* Don't move things inside a tablejump. */
2920 {
2924 /* Ensure our label doesn't go away. */
2927 /* Verify that uid_loop is large enough and that
2928 we can invert P. */
2930 {
2933 /* If no suitable BARRIER was found, create a suitable
2934 one before TARGET. Since TARGET is a fall through
2935 path, we'll need to insert a jump around our block
2936 and add a BARRIER before TARGET.
2938 This creates an extra unconditional jump outside
2939 the loop. However, the benefits of removing rarely
2940 executed instructions from inside the loop usually
2941 outweighs the cost of the extra unconditional jump
2942 outside the loop. */
2944 {
2945 rtx temp;
2952 }
2954 /* Include the BARRIER after INSN and copy the
2955 block after LOC. */
2960 /* All those insns are now in TARGET_LOOP. */
2966 /* The label jumped to by INSN is no longer a loop
2967 exit. Unless INSN does not have a label (e.g.,
2968 it is a RETURN insn), search loop->exit_labels
2969 to find its label_ref, and remove it. Also turn
2970 off LABEL_OUTSIDE_LOOP_P bit. */
2972 {
2974 r;
2977 {
2981 else
2984 }
2990 /* If we didn't find it, then something is
2991 wrong. */
2994 }
2996 /* P is now a jump outside the loop, so it must be put
2997 in loop->exit_labels, and marked as such.
2998 The easiest way to do this is to just call
2999 mark_loop_jump again for P. */
3002 /* If INSN now jumps to the insn after it,
3003 delete INSN. */
3008 }
3010 /* Continue the loop after where the conditional
3011 branch used to jump, since the only branch insn
3012 in the block (if it still remains) is an inter-loop
3013 branch and hence needs no processing. */
3019 /* This loop will be continued with NEXT_INSN (insn). */
3021 }
3022 }
3023 }
3024 }
3025 }
3027 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
3028 loops it is contained in, mark the target loop invalid.
3030 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
3032 static void
3034 rtx x;
3036 {
3042 {
3054 /* There could be a label reference in here. */
3066 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3078 /* Link together all labels that branch outside the loop. This
3079 is used by final_[bg]iv_value and the loop unrolling code. Also
3080 mark this LABEL_REF so we know that this branch should predict
3081 false. */
3083 /* A check to make sure the label is not in an inner nested loop,
3084 since this does not count as a loop exit. */
3086 {
3091 }
3092 else
3096 {
3105 }
3107 /* If this is inside a loop, but not in the current loop or one enclosed
3108 by it, it invalidates at least one loop. */
3113 /* We must invalidate every nested loop containing the target of this
3114 label, except those that also contain the jump insn. */
3117 {
3118 /* Stop when we reach a loop that also contains the jump insn. */
3123 /* If we get here, we know we need to invalidate a loop. */
3130 }
3134 /* If this is not setting pc, ignore. */
3156 /* Strictly speaking this is not a jump into the loop, only a possible
3157 jump out of the loop. However, we have no way to link the destination
3158 of this jump onto the list of exit labels. To be safe we mark this
3159 loop and any containing loops as invalid. */
3161 {
3163 {
3169 }
3170 }
3172 }
3173 }
3174 \f
3175 /* Return nonzero if there is a label in the range from
3176 insn INSN to and including the insn whose luid is END
3177 INSN must have an assigned luid (i.e., it must not have
3178 been previously created by loop.c). */
3180 static int
3182 rtx insn;
3184 {
3186 {
3190 }
3193 }
3195 /* Record that a memory reference X is being set. */
3197 static void
3199 rtx x;
3200 rtx y ATTRIBUTE_UNUSED;
3202 {
3208 /* Count number of memory writes.
3209 This affects heuristics in strength_reduce. */
3212 /* BLKmode MEM means all memory is clobbered. */
3214 {
3217 else
3221 }
3225 }
3227 /* X is a value modified by an INSN that references a biv inside a loop
3228 exit test (ie, X is somehow related to the value of the biv). If X
3229 is a pseudo that is used more than once, then the biv is (effectively)
3230 used more than once. DATA is a pointer to a loop_regs structure. */
3232 static void
3234 rtx x;
3235 rtx y ATTRIBUTE_UNUSED;
3237 {
3252 /* If we do not have usage information, or if we know the register
3253 is used more than once, note that fact for check_dbra_loop. */
3258 }
3259 \f
3260 /* Return nonzero if the rtx X is invariant over the current loop.
3262 The value is 2 if we refer to something only conditionally invariant.
3264 A memory ref is invariant if it is not volatile and does not conflict
3265 with anything stored in `loop_info->store_mems'. */
3267 int
3270 rtx x;
3271 {
3278 rtx mem_list_entry;
3284 {
3292 /* A LABEL_REF is normally invariant, however, if we are unrolling
3293 loops, and this label is inside the loop, then it isn't invariant.
3294 This is because each unrolled copy of the loop body will have
3295 a copy of this label. If this was invariant, then an insn loading
3296 the address of this label into a register might get moved outside
3297 the loop, and then each loop body would end up using the same label.
3299 We don't know the loop bounds here though, so just fail for all
3300 labels. */
3303 else
3312 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3313 since the reg might be set by initialization within the loop. */
3324 /* Out-of-range regs can occur when we are called from unrolling.
3325 These have always been created by the unroller and are set in
3326 the loop, hence are never invariant. */
3337 /* Volatile memory references must be rejected. Do this before
3338 checking for read-only items, so that volatile read-only items
3339 will be rejected also. */
3343 /* See if there is any dependence between a store and this load. */
3346 {
3352 }
3354 /* It's not invalidated by a store in memory
3355 but we must still verify the address is invariant. */
3359 /* Don't mess with insns declared volatile. */
3366 }
3370 {
3372 {
3378 }
3380 {
3383 {
3389 }
3391 }
3392 }
3395 }
3396 \f
3397 /* Return nonzero if all the insns in the loop that set REG
3398 are INSN and the immediately following insns,
3399 and if each of those insns sets REG in an invariant way
3400 (not counting uses of REG in them).
3402 The value is 2 if some of these insns are only conditionally invariant.
3404 We assume that INSN itself is the first set of REG
3405 and that its source is invariant. */
3407 static int
3412 {
3416 rtx temp;
3417 /* Number of sets we have to insist on finding after INSN. */
3423 /* If N_SETS hit the limit, we can't rely on its value. */
3430 {
3432 rtx set;
3437 /* If library call, skip to end of it. */
3446 {
3451 {
3452 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3453 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3454 notes are OK. */
3460 }
3461 }
3463 count--;
3465 {
3468 }
3469 }
3472 /* If loop_invariant_p ever returned 2, we return 2. */
3474 }
3476 #if 0
3477 /* I don't think this condition is sufficient to allow INSN
3478 to be moved, so we no longer test it. */
3480 /* Return 1 if all insns in the basic block of INSN and following INSN
3481 that set REG are invariant according to TABLE. */
3483 static int
3487 {
3492 {
3501 {
3504 }
3505 }
3506 }
3508 \f
3509 /* Look at all uses (not sets) of registers in X. For each, if it is
3510 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3511 a different insn, set USAGE[REGNO] to const0_rtx. */
3513 static void
3516 rtx insn;
3517 rtx x;
3518 {
3530 {
3531 /* Don't count SET_DEST if it is a REG; otherwise count things
3532 in SET_DEST because if a register is partially modified, it won't
3533 show up as a potential movable so we don't care how USAGE is set
3534 for it. */
3538 }
3539 else
3541 {
3547 }
3548 }
3549 \f
3550 /* Count and record any set in X which is contained in INSN. Update
3551 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3552 in X. */
3554 static void
3559 {
3561 /* Don't move a reg that has an explicit clobber.
3562 It's not worth the pain to try to do it correctly. */
3566 {
3574 {
3578 {
3579 /* If this is the first setting of this reg
3580 in current basic block, and it was set before,
3581 it must be set in two basic blocks, so it cannot
3582 be moved out of the loop. */
3586 /* If this is not first setting in current basic block,
3587 see if reg was used in between previous one and this.
3588 If so, neither one can be moved. */
3595 }
3596 }
3597 }
3598 }
3599 \f
3600 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3601 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3602 contained in insn INSN is used by any insn that precedes INSN in
3603 cyclic order starting from the loop entry point.
3605 We don't want to use INSN_LUID here because if we restrict INSN to those
3606 that have a valid INSN_LUID, it means we cannot move an invariant out
3607 from an inner loop past two loops. */
3609 static int
3613 {
3615 rtx p;
3617 /* Scan forward checking for register usage. If we hit INSN, we
3618 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3620 {
3626 }
3629 }
3630 \f
3632 /* Information we collect about arrays that we might want to prefetch. */
3633 struct prefetch_info
3634 {
3638 index. */
3639 HOST_WIDE_INT index;
3641 iteration. */
3643 prefetch area in one iteration. */
3645 This is set only for loops with known
3646 iteration counts and is 0xffffffff
3647 otherwise. */
3651 };
3653 /* Data used by check_store function. */
3654 struct check_store_data
3655 {
3656 rtx mem_address;
3658 };
3664 /* Set mem_write when mem_address is found. Used as callback to
3665 note_stores. */
3666 static void
3670 {
3675 }
3676 \f
3677 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3678 important to get some addresses combined. Later more sophisticated
3679 transformations can be added when necessary.
3681 ??? Same trick with swapping operand is done at several other places.
3682 It can be nice to develop some common way to handle this. */
3684 static int
3687 {
3701 {
3706 }
3707 /* Compare the elements. If any pair of corresponding elements fails to
3708 match, return 0 for the whole thing. */
3712 {
3714 {
3726 /* Two vectors must have the same length. */
3730 /* And the corresponding elements must match. */
3748 /* These are just backpointers, so they don't matter. */
3754 /* It is believed that rtx's at this level will never
3755 contain anything but integers and other rtx's,
3756 except for within LABEL_REFs and SYMBOL_REFs. */
3759 }
3760 }
3762 }
3763 \f
3764 /* Remove constant addition value from the expression X (when present)
3765 and return it. */
3767 static HOST_WIDE_INT
3770 {
3774 /* Avoid clobbering a shared CONST expression. */
3776 {
3780 {
3783 }
3785 }
3788 {
3791 }
3793 /* For plus expression recurse on ourself. */
3795 {
3799 /* In case our parameter was constant, remove extra zero from the
3800 expression. */
3805 }
3808 }
3810 /* Attempt to identify accesses to arrays that are most likely to cause cache
3811 misses, and emit prefetch instructions a few prefetch blocks forward.
3813 To detect the arrays we use the GIV information that was collected by the
3814 strength reduction pass.
3816 The prefetch instructions are generated after the GIV information is done
3817 and before the strength reduction process. The new GIVs are injected into
3818 the strength reduction tables, so the prefetch addresses are optimized as
3819 well.
3821 GIVs are split into base address, stride, and constant addition values.
3822 GIVs with the same address, stride and close addition values are combined
3823 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3824 for write instructions can be used for the block we write to, on machines
3825 that support write prefetches.
3827 Several heuristics are used to determine when to prefetch. They are
3828 controlled by defined symbols that can be overridden for each target. */
3830 static void
3833 {
3849 /* Consider only loops w/o calls. When a call is done, the loop is probably
3850 slow enough to read the memory. */
3852 {
3857 }
3859 /* Don't prefetch in loops known to have few iterations. */
3863 {
3868 }
3870 /* Search all induction variables and pick those interesting for the prefetch
3871 machinery. */
3873 {
3879 /* Expect all BIVs to be executed in each iteration. This makes our
3880 analysis more conservative. */
3882 {
3883 /* Discard non-constant additions that we can't handle well yet, and
3884 BIVs that are executed multiple times; such BIVs ought to be
3885 handled in the nested loop. We accept not_every_iteration BIVs,
3886 since these only result in larger strides and make our
3887 heuristics more conservative. */
3889 {
3891 {
3897 }
3899 }
3902 {
3904 {
3910 }
3912 }
3916 }
3922 {
3923 rtx address;
3924 rtx temp;
3933 /* See whether an induction variable is interesting to us and if
3934 not, report the reason. */
3938 /* We are interested only in constant stride memory references
3939 in order to be able to compute density easily. */
3943 else
3944 {
3947 {
3950 }
3952 /* On some targets, reversed order prefetches are not
3953 worthwhile. */
3957 /* Prefetch of accesses with an extreme stride might not be
3958 worthwhile, either. */
3963 /* Ignore GIVs with varying add values; we can't predict the
3964 value for the next iteration. */
3968 /* Ignore GIVs in the nested loops; they ought to have been
3969 handled already. */
3972 }
3975 {
3981 }
3983 /* Determine the pointer to the basic array we are examining. It is
3984 the sum of the BIV's initial value and the GIV's add_val. */
3994 /* When the GIV is not always executed, we might be better off by
3995 not dirtying the cache pages. */
3998 else
3999 {
4004 }
4006 /* Attempt to find another prefetch to the same array and see if we
4007 can merge this one. */
4011 {
4012 /* In case both access same array (same location
4013 just with small difference in constant indexes), merge
4014 the prefetches. Just do the later and the earlier will
4015 get prefetched from previous iteration.
4016 The artificial threshold should not be too small,
4017 but also not bigger than small portion of memory usually
4018 traversed by single loop. */
4021 {
4030 }
4034 {
4039 }
4040 }
4042 /* Merging failed. */
4044 {
4052 num_prefetches++;
4054 {
4059 }
4060 }
4061 }
4062 }
4065 {
4068 /* Attempt to calculate the total number of bytes fetched by all
4069 iterations of the loop. Avoid overflow. */
4074 else
4079 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4084 {
4089 }
4090 else
4091 {
4097 }
4098 else
4101 /* Find how many prefetch instructions we'll use within the loop. */
4103 {
4109 }
4110 }
4112 /* Determine how many iterations ahead to prefetch within the loop, based
4113 on how many prefetches we currently expect to do within the loop. */
4115 {
4117 {
4123 }
4124 }
4125 /* We'll also use AHEAD to determine how many prefetch instructions to
4126 emit before a loop, so don't leave it zero. */
4131 {
4132 /* Update if we've decided not to prefetch anything within the loop. */
4136 /* Find how many prefetch instructions we'll use before the loop. */
4138 {
4146 }
4149 {
4171 }
4172 }
4175 {
4176 /* Record that this loop uses prefetch instructions. */
4180 {
4185 }
4186 }
4189 {
4193 {
4195 rtx insn;
4199 rtx seq;
4201 /* We can save some effort by offsetting the address on
4202 architectures with offsettable memory references. */
4205 else
4206 {
4212 }
4215 /* Make sure the address operand is valid for prefetch. */
4225 /* Check all insns emitted and record the new GIV
4226 information. */
4229 {
4234 }
4235 }
4238 {
4239 /* Emit insns before the loop to fetch the first cache lines or,
4240 if we're not prefetching within the loop, everything we expect
4241 to need. */
4243 {
4251 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4252 non-constant INIT_VAL to have the same mode as REG, which
4253 in this case we know to be Pmode. */
4255 {
4256 rtx seq;
4263 }
4269 loop_start);
4270 }
4271 }
4272 }
4275 }
4276 \f
4277 /* A "basic induction variable" or biv is a pseudo reg that is set
4278 (within this loop) only by incrementing or decrementing it. */
4279 /* A "general induction variable" or giv is a pseudo reg whose
4280 value is a linear function of a biv. */
4282 /* Bivs are recognized by `basic_induction_var';
4283 Givs by `general_induction_var'. */
4285 /* Communication with routines called via `note_stores'. */
4289 /* Dummy register to have nonzero DEST_REG for DEST_ADDR type givs. */
4293 /* ??? Unfinished optimizations, and possible future optimizations,
4294 for the strength reduction code. */
4296 /* ??? The interaction of biv elimination, and recognition of 'constant'
4297 bivs, may cause problems. */
4299 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4300 performance problems.
4302 Perhaps don't eliminate things that can be combined with an addressing
4303 mode. Find all givs that have the same biv, mult_val, and add_val;
4304 then for each giv, check to see if its only use dies in a following
4305 memory address. If so, generate a new memory address and check to see
4306 if it is valid. If it is valid, then store the modified memory address,
4307 otherwise, mark the giv as not done so that it will get its own iv. */
4309 /* ??? Could try to optimize branches when it is known that a biv is always
4310 positive. */
4312 /* ??? When replace a biv in a compare insn, we should replace with closest
4313 giv so that an optimized branch can still be recognized by the combiner,
4314 e.g. the VAX acb insn. */
4316 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4317 was rerun in loop_optimize whenever a register was added or moved.
4318 Also, some of the optimizations could be a little less conservative. */
4319 \f
4320 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4321 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4322 callback.
4324 NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at
4325 least once for every loop iteration except for the last one.
4327 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4328 loop iteration.
4329 */
4330 void
4333 loop_insn_callback fncall;
4334 {
4339 rtx p;
4341 /* If loop_scan_start points to the loop exit test, we have to be wary of
4342 subversive use of gotos inside expression statements. */
4346 /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */
4350 {
4353 /* Past CODE_LABEL, we get to insns that may be executed multiple
4354 times. The only way we can be sure that they can't is if every
4355 jump insn between here and the end of the loop either
4356 returns, exits the loop, is a jump to a location that is still
4357 behind the label, or is a jump to the loop start. */
4360 {
4366 {
4371 {
4374 else
4378 }
4386 {
4389 }
4390 }
4391 }
4393 /* Past a jump, we get to insns for which we can't count
4394 on whether they will be executed during each iteration. */
4395 /* This code appears twice in strength_reduce. There is also similar
4396 code in scan_loop. */
4398 /* If we enter the loop in the middle, and scan around to the
4399 beginning, don't set not_every_iteration for that.
4400 This can be any kind of jump, since we want to know if insns
4401 will be executed if the loop is executed. */
4406 {
4409 /* If this is a jump outside the loop, then it also doesn't
4410 matter. Check to see if the target of this branch is on the
4411 loop->exits_labels list. */
4419 }
4422 {
4423 /* At the virtual top of a converted loop, insns are again known to
4424 be executed each iteration: logically, the loop begins here
4425 even though the exit code has been duplicated.
4427 Insns are also again known to be executed each iteration at
4428 the LOOP_CONT note. */
4434 loop_depth++;
4436 loop_depth--;
4437 }
4439 /* Note if we pass a loop latch. If we do, then we can not clear
4440 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4441 a loop since a jump before the last CODE_LABEL may have started
4442 a new loop iteration.
4444 Note that LOOP_TOP is only set for rotated loops and we need
4445 this check for all loops, so compare against the CODE_LABEL
4446 which immediately follows LOOP_START. */
4451 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4452 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4453 or not an insn is known to be executed each iteration of the
4454 loop, whether or not any iterations are known to occur.
4456 Therefore, if we have just passed a label and have no more labels
4457 between here and the test insn of the loop, and we have not passed
4458 a jump to the top of the loop, then we know these insns will be
4459 executed each iteration. */
4462 && !past_loop_latch
4467 }
4468 }
4469 \f
4470 static void
4473 {
4476 /* Temporary list pointers for traversing ivs->list. */
4483 /* Scan ivs->list to remove all regs that proved not to be bivs.
4484 Make a sanity check against regs->n_times_set. */
4486 {
4488 /* Above happens if register modified by subreg, etc. */
4489 /* Make sure it is not recognized as a basic induction var: */
4491 /* If never incremented, it is invariant that we decided not to
4492 move. So leave it alone. */
4494 {
4505 }
4506 else
4507 {
4512 }
4513 }
4514 }
4517 /* Determine how BIVS are initialized by looking through pre-header
4518 extended basic block. */
4519 static void
4522 {
4524 /* Temporary list pointers for traversing ivs->list. */
4527 rtx p;
4529 /* Find initial value for each biv by searching backwards from loop_start,
4530 halting at first label. Also record any test condition. */
4534 {
4535 rtx test;
4545 /* Record any test of a biv that branches around the loop if no store
4546 between it and the start of loop. We only care about tests with
4547 constants and registers and only certain of those. */
4557 {
4558 /* If an NE test, we have an initial value! */
4560 {
4564 }
4565 else
4567 }
4568 }
4569 }
4572 /* Look at the each biv and see if we can say anything better about its
4573 initial value from any initializing insns set up above. (This is done
4574 in two passes to avoid missing SETs in a PARALLEL.) */
4575 static void
4578 {
4580 /* Temporary list pointers for traversing ivs->list. */
4585 {
4586 rtx src;
4587 rtx note;
4592 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4593 is a constant, use the value of that. */
4599 else
4612 {
4616 {
4619 }
4620 }
4621 /* If we can't make it a giv,
4622 let biv keep initial value of "itself". */
4625 }
4626 }
4629 /* Search the loop for general induction variables. */
4631 static void
4634 {
4636 }
4639 /* For each giv for which we still don't know whether or not it is
4640 replaceable, check to see if it is replaceable because its final value
4641 can be calculated. */
4643 static void
4646 {
4651 {
4657 }
4658 }
4661 /* Return nonzero if it is possible to eliminate the biv BL provided
4662 all givs are reduced. This is possible if either the reg is not
4663 used outside the loop, or we can compute what its final value will
4664 be. */
4666 static int
4672 {
4673 /* For architectures with a decrement_and_branch_until_zero insn,
4674 don't do this if we put a REG_NONNEG note on the endtest for this
4675 biv. */
4677 #ifdef HAVE_decrement_and_branch_until_zero
4679 {
4684 }
4685 #endif
4687 /* Check that biv is used outside loop or if it has a final value.
4688 Compare against bl->init_insn rather than loop->start. We aren't
4689 concerned with any uses of the biv between init_insn and
4690 loop->start since these won't be affected by the value of the biv
4691 elsewhere in the function, so long as init_insn doesn't use the
4692 biv itself. */
4703 {
4711 }
4713 }
4716 /* Reduce each giv of BL that we have decided to reduce. */
4718 static void
4722 {
4726 {
4729 {
4732 /* If the code for derived givs immediately below has already
4733 allocated a new_reg, we must keep it. */
4737 #ifdef AUTO_INC_DEC
4738 /* If the target has auto-increment addressing modes, and
4739 this is an address giv, then try to put the increment
4740 immediately after its use, so that flow can create an
4741 auto-increment addressing mode. */
4744 /* We don't handle reversed biv's because bl->biv->insn
4745 does not have a valid INSN_LUID. */
4749 {
4750 /* If other giv's have been combined with this one, then
4751 this will work only if all uses of the other giv's occur
4752 before this giv's insn. This is difficult to check.
4754 We simplify this by looking for the common case where
4755 there is one DEST_REG giv, and this giv's insn is the
4756 last use of the dest_reg of that DEST_REG giv. If the
4757 increment occurs after the address giv, then we can
4758 perform the optimization. (Otherwise, the increment
4759 would have to go before other_giv, and we would not be
4760 able to combine it with the address giv to get an
4761 auto-inc address.) */
4763 {
4768 {
4771 else
4773 }
4780 }
4781 /* Check for case where increment is before the address
4782 giv. Do this test in "loop order". */
4791 else
4794 #ifdef HAVE_cc0
4795 {
4796 rtx prev;
4798 /* We can't put an insn immediately after one setting
4799 cc0, or immediately before one using cc0. */
4806 }
4807 #endif
4811 }
4812 #endif
4814 /* For each place where the biv is incremented, add an insn
4815 to increment the new, reduced reg for the giv. */
4817 {
4818 rtx insert_before;
4824 else
4832 /* A multiply is acceptable here
4833 since this is presumed to be seldom executed. */
4837 }
4839 /* Add code at loop start to initialize giv's reduced reg. */
4844 }
4845 }
4846 }
4849 /* Check for givs whose first use is their definition and whose
4850 last use is the definition of another giv. If so, it is likely
4851 dead and should not be used to derive another giv nor to
4852 eliminate a biv. */
4854 static void
4858 {
4862 {
4869 {
4875 }
4876 }
4877 }
4880 static void
4885 {
4889 {
4896 /* Update expression if this was combined, in case other giv was
4897 replaced. */
4902 /* See if this register is known to be a pointer to something. If
4903 so, see if we can find the alignment. First see if there is a
4904 destination register that is a pointer. If so, this shares the
4905 alignment too. Next see if we can deduce anything from the
4906 computational information. If not, and this is a DEST_ADDR
4907 giv, at least we know that it's a pointer, though we don't know
4908 the alignment. */
4916 {
4925 }
4929 {
4937 }
4942 /* Store reduced reg as the address in the memref where we found
4943 this giv. */
4946 {
4948 }
4949 else
4950 {
4952 rtx note;
4954 /* Not replaceable; emit an insn to set the original giv reg from
4955 the reduced giv, same as above. */
4960 /* The original insn may have a REG_EQUAL note. This note is
4961 now incorrect and may result in invalid substitutions later.
4962 The original insn is dead, but may be part of a libcall
4963 sequence, which doesn't seem worth the bother of handling. */
4967 }
4969 /* When a loop is reversed, givs which depend on the reversed
4970 biv, and which are live outside the loop, must be set to their
4971 correct final value. This insn is only needed if the giv is
4972 not replaceable. The correct final value is the same as the
4973 value that the giv starts the reversed loop with. */
4984 {
4989 }
4990 }
4991 }
4994 static int
4999 rtx test_reg;
5000 {
5009 /* Reduce benefit if not replaceable, since we will insert a
5010 move-insn to replace the insn that calculates this giv. Don't do
5011 this unless the giv is a user variable, since it will often be
5012 marked non-replaceable because of the duplication of the exit
5013 code outside the loop. In such a case, the copies we insert are
5014 dead and will be deleted. So they don't have a cost. Similar
5015 situations exist. */
5016 /* ??? The new final_[bg]iv_value code does a much better job of
5017 finding replaceable giv's, and hence this code may no longer be
5018 necessary. */
5023 /* Decrease the benefit to count the add-insns that we will insert
5024 to increment the reduced reg for the giv. ??? This can
5025 overestimate the run-time cost of the additional insns, e.g. if
5026 there are multiple basic blocks that increment the biv, but only
5027 one of these blocks is executed during each iteration. There is
5028 no good way to detect cases like this with the current structure
5029 of the loop optimizer. This code is more accurate for
5030 determining code size than run-time benefits. */
5033 /* Decide whether to strength-reduce this giv or to leave the code
5034 unchanged (recompute it from the biv each time it is used). This
5035 decision can be made independently for each giv. */
5037 #ifdef AUTO_INC_DEC
5038 /* Attempt to guess whether autoincrement will handle some of the
5039 new add insns; if so, increase BENEFIT (undo the subtraction of
5040 add_cost that was done above). */
5042 /* Increasing the benefit is risky, since this is only a guess.
5043 Avoid increasing register pressure in cases where there would
5044 be no other benefit from reducing this giv. */
5047 {
5062 }
5063 #endif
5066 }
5069 /* Free IV structures for LOOP. */
5071 static void
5074 {
5081 {
5087 {
5090 }
5092 {
5095 }
5099 }
5100 }
5103 /* Perform strength reduction and induction variable elimination.
5105 Pseudo registers created during this function will be beyond the
5106 last valid index in several tables including
5107 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5108 problem here, because the added registers cannot be givs outside of
5109 their loop, and hence will never be reconsidered. But scan_loop
5110 must check regnos to make sure they are in bounds. */
5112 static void
5116 {
5120 rtx p;
5121 /* Temporary list pointer for traversing ivs->list. */
5123 /* Ratio of extra register life span we can justify
5124 for saving an instruction. More if loop doesn't call subroutines
5125 since in that case saving an insn makes more difference
5126 and more registers are available. */
5127 /* ??? could set this to last value of threshold in move_movables */
5129 /* Map of pseudo-register replacements. */
5141 /* Find all BIVs in loop. */
5144 /* Exit if there are no bivs. */
5146 {
5147 /* Can still unroll the loop anyways, but indicate that there is no
5148 strength reduction info available. */
5154 }
5156 /* Determine how BIVS are initialized by looking through pre-header
5157 extended basic block. */
5160 /* Look at the each biv and see if we can say anything better about its
5161 initial value from any initializing insns set up above. */
5164 /* Search the loop for general induction variables. */
5167 /* Try to calculate and save the number of loop iterations. This is
5168 set to zero if the actual number can not be calculated. This must
5169 be called after all giv's have been identified, since otherwise it may
5170 fail if the iteration variable is a giv. */
5173 #ifdef HAVE_prefetch
5176 #endif
5178 /* Now for each giv for which we still don't know whether or not it is
5179 replaceable, check to see if it is replaceable because its final value
5180 can be calculated. This must be done after loop_iterations is called,
5181 so that final_giv_value will work correctly. */
5184 /* Try to prove that the loop counter variable (if any) is always
5185 nonnegative; if so, record that fact with a REG_NONNEG note
5186 so that "decrement and branch until zero" insn can be used. */
5189 /* Create reg_map to hold substitutions for replaceable giv regs.
5190 Some givs might have been made from biv increments, so look at
5191 ivs->reg_iv_type for a suitable size. */
5195 /* Examine each iv class for feasibility of strength reduction/induction
5196 variable elimination. */
5199 {
5203 /* Test whether it will be possible to eliminate this biv
5204 provided all givs are reduced. */
5207 /* This will be true at the end, if all givs which depend on this
5208 biv have been strength reduced.
5209 We can't (currently) eliminate the biv unless this is so. */
5212 /* Check each extension dependent giv in this class to see if its
5213 root biv is safe from wrapping in the interior mode. */
5216 /* Combine all giv's for this iv_class. */
5220 {
5228 /* If an insn is not to be strength reduced, then set its ignore
5229 flag, and clear bl->all_reduced. */
5231 /* A giv that depends on a reversed biv must be reduced if it is
5232 used after the loop exit, otherwise, it would have the wrong
5233 value after the loop exit. To make it simple, just reduce all
5234 of such giv's whether or not we know they are used after the loop
5235 exit. */
5240 {
5248 }
5249 else
5250 {
5251 /* Check that we can increment the reduced giv without a
5252 multiply insn. If not, reject it. */
5257 {
5265 }
5266 }
5267 }
5269 /* Check for givs whose first use is their definition and whose
5270 last use is the definition of another giv. If so, it is likely
5271 dead and should not be used to derive another giv nor to
5272 eliminate a biv. */
5275 /* Reduce each giv that we decided to reduce. */
5278 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5279 as not reduced.
5281 For each giv register that can be reduced now: if replaceable,
5282 substitute reduced reg wherever the old giv occurs;
5283 else add new move insn "giv_reg = reduced_reg". */
5286 /* All the givs based on the biv bl have been reduced if they
5287 merit it. */
5289 /* For each giv not marked as maybe dead that has been combined with a
5290 second giv, clear any "maybe dead" mark on that second giv.
5291 v->new_reg will either be or refer to the register of the giv it
5292 combined with.
5294 Doing this clearing avoids problems in biv elimination where
5295 a giv's new_reg is a complex value that can't be put in the
5296 insn but the giv combined with (with a reg as new_reg) is
5297 marked maybe_dead. Since the register will be used in either
5298 case, we'd prefer it be used from the simpler giv. */
5304 /* Try to eliminate the biv, if it is a candidate.
5305 This won't work if ! bl->all_reduced,
5306 since the givs we planned to use might not have been reduced.
5308 We have to be careful that we didn't initially think we could
5309 eliminate this biv because of a giv that we now think may be
5310 dead and shouldn't be used as a biv replacement.
5312 Also, there is the possibility that we may have a giv that looks
5313 like it can be used to eliminate a biv, but the resulting insn
5314 isn't valid. This can happen, for example, on the 88k, where a
5315 JUMP_INSN can compare a register only with zero. Attempts to
5316 replace it with a compare with a constant will fail.
5318 Note that in cases where this call fails, we may have replaced some
5319 of the occurrences of the biv with a giv, but no harm was done in
5320 doing so in the rare cases where it can occur. */
5324 {
5325 /* ?? If we created a new test to bypass the loop entirely,
5326 or otherwise drop straight in, based on this test, then
5327 we might want to rewrite it also. This way some later
5328 pass has more hope of removing the initialization of this
5329 biv entirely. */
5331 /* If final_value != 0, then the biv may be used after loop end
5332 and we must emit an insn to set it just in case.
5334 Reversed bivs already have an insn after the loop setting their
5335 value, so we don't need another one. We can't calculate the
5336 proper final value for such a biv here anyways. */
5345 }
5346 /* See above note wrt final_value. But since we couldn't eliminate
5347 the biv, we must set the value after the loop instead of before. */
5351 }
5353 /* Go through all the instructions in the loop, making all the
5354 register substitutions scheduled in REG_MAP. */
5359 {
5363 }
5366 {
5367 /* When we completely unroll a loop we will likely not need the increment
5368 of the loop BIV and we will not need the conditional branch at the
5369 end of the loop. */
5372 #ifdef HAVE_cc0
5373 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5374 need the comparison before the conditional branch at the end of the
5375 loop. */
5377 #endif
5379 /* We'll need one copy for each loop iteration. */
5382 /* A little slop to account for the ability to remove initialization
5383 code, better CSE, and other secondary benefits of completely
5384 unrolling some loops. */
5387 /* Clamp the value. */
5390 }
5392 /* Unroll loops from within strength reduction so that we can use the
5393 induction variable information that strength_reduce has already
5394 collected. Always unroll loops that would be as small or smaller
5395 unrolled than when rolled. */
5402 #ifdef HAVE_doloop_end
5407 /* In case number of iterations is known, drop branch prediction note
5408 in the branch. Do that only in second loop pass, as loop unrolling
5409 may change the number of iterations performed. */
5411 {
5412 unsigned HOST_WIDE_INT n
5417 }
5425 }
5426 \f
5427 /*Record all basic induction variables calculated in the insn. */
5428 static rtx
5431 rtx p;
5434 {
5436 rtx set;
5437 rtx dest_reg;
5438 rtx inc_val;
5439 rtx mult_val;
5445 {
5450 {
5455 {
5456 /* It is a possible basic induction variable.
5457 Create and initialize an induction structure for it. */
5465 }
5468 }
5469 }
5471 }
5472 \f
5473 /* Record all givs calculated in the insn.
5474 A register is a giv if: it is only set once, it is a function of a
5475 biv and a constant (or invariant), and it is not a biv. */
5476 static rtx
5479 rtx p;
5482 {
5485 rtx set;
5486 /* Look for a general induction variable in a register. */
5491 {
5492 rtx src_reg;
5493 rtx dest_reg;
5494 rtx add_val;
5495 rtx mult_val;
5496 rtx ext_val;
5499 rtx last_consec_insn;
5508 /* Equivalent expression is a giv. */
5513 /* Don't try to handle any regs made by loop optimization.
5514 We have nothing on them in regno_first_uid, etc. */
5516 /* Don't recognize a BASIC_INDUCT_VAR here. */
5518 /* This must be the only place where the register is set. */
5520 /* or all sets must be consecutive and make a giv. */
5525 {
5529 /* If this is a library call, increase benefit. */
5533 /* Skip the consecutive insns, if there are any. */
5541 }
5542 }
5544 #ifndef DONT_REDUCE_ADDR
5545 /* Look for givs which are memory addresses. */
5546 /* This resulted in worse code on a VAX 8600. I wonder if it
5547 still does. */
5550 maybe_multiple);
5551 #endif
5553 /* Update the status of whether giv can derive other givs. This can
5554 change when we pass a label or an insn that updates a biv. */
5559 }
5560 \f
5561 /* Return 1 if X is a valid source for an initial value (or as value being
5562 compared against in an initial test).
5564 X must be either a register or constant and must not be clobbered between
5565 the current insn and the start of the loop.
5567 INSN is the insn containing X. */
5569 static int
5571 rtx x;
5572 rtx insn;
5574 rtx loop_start;
5575 {
5579 /* Only consider pseudos we know about initialized in insns whose luids
5580 we know. */
5585 /* Don't use call-clobbered registers across a call which clobbers it. On
5586 some machines, don't use any hard registers at all. */
5588 && (SMALL_REGISTER_CLASSES
5592 /* Don't use registers that have been clobbered before the start of the
5593 loop. */
5598 }
5599 \f
5600 /* Scan X for memory refs and check each memory address
5601 as a possible giv. INSN is the insn whose pattern X comes from.
5602 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5603 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5604 more than once in each loop iteration. */
5606 static void
5609 rtx x;
5610 rtx insn;
5612 {
5622 {
5638 {
5639 rtx src_reg;
5640 rtx add_val;
5641 rtx mult_val;
5642 rtx ext_val;
5645 /* This code used to disable creating GIVs with mult_val == 1 and
5646 add_val == 0. However, this leads to lost optimizations when
5647 it comes time to combine a set of related DEST_ADDR GIVs, since
5648 this one would not be seen. */
5653 {
5654 /* Found one; record it. */
5663 }
5664 }
5669 }
5671 /* Recursively scan the subexpressions for other mem refs. */
5677 maybe_multiple);
5681 maybe_multiple);
5682 }
5683 \f
5684 /* Fill in the data about one biv update.
5685 V is the `struct induction' in which we record the biv. (It is
5686 allocated by the caller, with alloca.)
5687 INSN is the insn that sets it.
5688 DEST_REG is the biv's reg.
5690 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5691 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5692 being set to INC_VAL.
5694 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5695 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5696 can be executed more than once per iteration. If MAYBE_MULTIPLE
5697 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5698 executed exactly once per iteration. */
5700 static void
5705 rtx insn;
5706 rtx dest_reg;
5707 rtx inc_val;
5708 rtx mult_val;
5712 {
5728 /* Add this to the reg's iv_class, creating a class
5729 if this is the first incrementation of the reg. */
5733 {
5734 /* Create and initialize new iv_class. */
5744 /* Set initial value to the reg itself. */
5747 /* We haven't seen the initializing insn yet */
5757 /* Add this class to ivs->list. */
5761 /* Put it in the array of biv register classes. */
5763 }
5765 /* Update IV_CLASS entry for this biv. */
5774 }
5775 \f
5776 /* Fill in the data about one giv.
5777 V is the `struct induction' in which we record the giv. (It is
5778 allocated by the caller, with alloca.)
5779 INSN is the insn that sets it.
5780 BENEFIT estimates the savings from deleting this insn.
5781 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5782 into a register or is used as a memory address.
5784 SRC_REG is the biv reg which the giv is computed from.
5785 DEST_REG is the giv's reg (if the giv is stored in a reg).
5786 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5787 LOCATION points to the place where this giv's value appears in INSN. */
5789 static void
5794 rtx insn;
5795 rtx src_reg;
5796 rtx dest_reg;
5802 {
5807 rtx temp;
5809 /* Attempt to prove constantness of the values. Don't let simplify_rtx
5810 undo the MULT canonicalization that we performed earlier. */
5840 /* The v->always_computable field is used in update_giv_derive, to
5841 determine whether a giv can be used to derive another giv. For a
5842 DEST_REG giv, INSN computes a new value for the giv, so its value
5843 isn't computable if INSN insn't executed every iteration.
5844 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5845 it does not compute a new value. Hence the value is always computable
5846 regardless of whether INSN is executed each iteration. */
5850 else
5856 {
5859 }
5861 {
5866 /* If the lifetime is zero, it means that this register is
5867 really a dead store. So mark this as a giv that can be
5868 ignored. This will not prevent the biv from being eliminated. */
5874 }
5876 /* Add the giv to the class of givs computed from one biv. */
5880 {
5883 /* Don't count DEST_ADDR. This is supposed to count the number of
5884 insns that calculate givs. */
5888 }
5889 else
5890 /* Fatal error, biv missing for this giv? */
5894 {
5897 }
5898 else
5899 {
5900 /* The giv can be replaced outright by the reduced register only if all
5901 of the following conditions are true:
5902 - the insn that sets the giv is always executed on any iteration
5903 on which the giv is used at all
5904 (there are two ways to deduce this:
5905 either the insn is executed on every iteration,
5906 or all uses follow that insn in the same basic block),
5907 - the giv is not used outside the loop
5908 - no assignments to the biv occur during the giv's lifetime. */
5911 /* Previous line always fails if INSN was moved by loop opt. */
5914 && (! not_every_iteration
5916 {
5917 /* Now check that there are no assignments to the biv within the
5918 giv's lifetime. This requires two separate checks. */
5920 /* Check each biv update, and fail if any are between the first
5921 and last use of the giv.
5923 If this loop contains an inner loop that was unrolled, then
5924 the insn modifying the biv may have been emitted by the loop
5925 unrolling code, and hence does not have a valid luid. Just
5926 mark the biv as not replaceable in this case. It is not very
5927 useful as a biv, because it is used in two different loops.
5928 It is very unlikely that we would be able to optimize the giv
5929 using this biv anyways. */
5934 {
5940 {
5944 }
5945 }
5947 /* If there are any backwards branches that go from after the
5948 biv update to before it, then this giv is not replaceable. */
5952 {
5956 }
5957 }
5958 else
5959 {
5960 /* May still be replaceable, we don't have enough info here to
5961 decide. */
5964 }
5965 }
5967 /* Record whether the add_val contains a const_int, for later use by
5968 combine_givs. */
5969 {
5974 ;
5978 {
5980 {
5985 else
5987 }
5990 }
5991 }
5995 }
5997 /* All this does is determine whether a giv can be made replaceable because
5998 its final value can be calculated. This code can not be part of record_giv
5999 above, because final_giv_value requires that the number of loop iterations
6000 be known, and that can not be accurately calculated until after all givs
6001 have been identified. */
6003 static void
6007 {
6010 /* DEST_ADDR givs will never reach here, because they are always marked
6011 replaceable above in record_giv. */
6013 /* The giv can be replaced outright by the reduced register only if all
6014 of the following conditions are true:
6015 - the insn that sets the giv is always executed on any iteration
6016 on which the giv is used at all
6017 (there are two ways to deduce this:
6018 either the insn is executed on every iteration,
6019 or all uses follow that insn in the same basic block),
6020 - its final value can be calculated (this condition is different
6021 than the one above in record_giv)
6022 - it's not used before the it's set
6023 - no assignments to the biv occur during the giv's lifetime. */
6025 #if 0
6026 /* This is only called now when replaceable is known to be false. */
6027 /* Clear replaceable, so that it won't confuse final_giv_value. */
6029 #endif
6034 {
6037 rtx last_giv_use;
6042 /* When trying to determine whether or not a biv increment occurs
6043 during the lifetime of the giv, we can ignore uses of the variable
6044 outside the loop because final_value is true. Hence we can not
6045 use regno_last_uid and regno_first_uid as above in record_giv. */
6047 /* Search the loop to determine whether any assignments to the
6048 biv occur during the giv's lifetime. Start with the insn
6049 that sets the giv, and search around the loop until we come
6050 back to that insn again.
6052 Also fail if there is a jump within the giv's lifetime that jumps
6053 to somewhere outside the lifetime but still within the loop. This
6054 catches spaghetti code where the execution order is not linear, and
6055 hence the above test fails. Here we assume that the giv lifetime
6056 does not extend from one iteration of the loop to the next, so as
6057 to make the test easier. Since the lifetime isn't known yet,
6058 this requires two loops. See also record_giv above. */
6063 {
6066 {
6069 }
6075 {
6076 /* It is possible for the BIV increment to use the GIV if we
6077 have a cycle. Thus we must be sure to check each insn for
6078 both BIV and GIV uses, and we must check for BIV uses
6079 first. */
6086 {
6088 {
6092 }
6094 }
6095 }
6096 }
6098 /* Now that the lifetime of the giv is known, check for branches
6099 from within the lifetime to outside the lifetime if it is still
6100 replaceable. */
6103 {
6106 {
6119 {
6128 }
6129 }
6130 }
6132 /* If it is replaceable, then save the final value. */
6135 }
6140 }
6141 \f
6142 /* Update the status of whether a giv can derive other givs.
6144 We need to do something special if there is or may be an update to the biv
6145 between the time the giv is defined and the time it is used to derive
6146 another giv.
6148 In addition, a giv that is only conditionally set is not allowed to
6149 derive another giv once a label has been passed.
6151 The cases we look at are when a label or an update to a biv is passed. */
6153 static void
6156 rtx p;
6157 {
6161 rtx tem;
6164 /* Search all IV classes, then all bivs, and finally all givs.
6166 There are three cases we are concerned with. First we have the situation
6167 of a giv that is only updated conditionally. In that case, it may not
6168 derive any givs after a label is passed.
6170 The second case is when a biv update occurs, or may occur, after the
6171 definition of a giv. For certain biv updates (see below) that are
6172 known to occur between the giv definition and use, we can adjust the
6173 giv definition. For others, or when the biv update is conditional,
6174 we must prevent the giv from deriving any other givs. There are two
6175 sub-cases within this case.
6177 If this is a label, we are concerned with any biv update that is done
6178 conditionally, since it may be done after the giv is defined followed by
6179 a branch here (actually, we need to pass both a jump and a label, but
6180 this extra tracking doesn't seem worth it).
6182 If this is a jump, we are concerned about any biv update that may be
6183 executed multiple times. We are actually only concerned about
6184 backward jumps, but it is probably not worth performing the test
6185 on the jump again here.
6187 If this is a biv update, we must adjust the giv status to show that a
6188 subsequent biv update was performed. If this adjustment cannot be done,
6189 the giv cannot derive further givs. */
6195 {
6197 {
6198 /* If cant_derive is already true, there is no point in
6199 checking all of these conditions again. */
6203 /* If this giv is conditionally set and we have passed a label,
6204 it cannot derive anything. */
6208 /* Skip givs that have mult_val == 0, since
6209 they are really invariants. Also skip those that are
6210 replaceable, since we know their lifetime doesn't contain
6211 any biv update. */
6215 /* The only way we can allow this giv to derive another
6216 is if this is a biv increment and we can form the product
6217 of biv->add_val and giv->mult_val. In this case, we will
6218 be able to compute a compensation. */
6220 {
6221 rtx ext_val_dummy;
6232 tem = simplify_giv_expr
6239 else
6241 }
6245 }
6246 }
6247 }
6248 \f
6249 /* Check whether an insn is an increment legitimate for a basic induction var.
6250 X is the source of insn P, or a part of it.
6251 MODE is the mode in which X should be interpreted.
6253 DEST_REG is the putative biv, also the destination of the insn.
6254 We accept patterns of these forms:
6255 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6256 REG = INVARIANT + REG
6258 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6259 store the additive term into *INC_VAL, and store the place where
6260 we found the additive term into *LOCATION.
6262 If X is an assignment of an invariant into DEST_REG, we set
6263 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6265 We also want to detect a BIV when it corresponds to a variable
6266 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6267 of the variable may be a PLUS that adds a SUBREG of that variable to
6268 an invariant and then sign- or zero-extends the result of the PLUS
6269 into the variable.
6271 Most GIVs in such cases will be in the promoted mode, since that is the
6272 probably the natural computation mode (and almost certainly the mode
6273 used for addresses) on the machine. So we view the pseudo-reg containing
6274 the variable as the BIV, as if it were simply incremented.
6276 Note that treating the entire pseudo as a BIV will result in making
6277 simple increments to any GIVs based on it. However, if the variable
6278 overflows in its declared mode but not its promoted mode, the result will
6279 be incorrect. This is acceptable if the variable is signed, since
6280 overflows in such cases are undefined, but not if it is unsigned, since
6281 those overflows are defined. So we only check for SIGN_EXTEND and
6282 not ZERO_EXTEND.
6284 If we cannot find a biv, we return 0. */
6286 static int
6289 rtx x;
6291 rtx dest_reg;
6292 rtx p;
6296 {
6304 {
6310 {
6312 }
6317 {
6319 }
6320 else
6333 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6334 handle addition of promoted variables.
6335 ??? The comment at the start of this function is wrong: promoted
6336 variable increments don't look like it says they do. */
6342 /* If this register is assigned in a previous insn, look at its
6343 source, but don't go outside the loop or past a label. */
6345 /* If this sets a register to itself, we would repeat any previous
6346 biv increment if we applied this strategy blindly. */
6352 {
6353 rtx dest;
6354 do
6355 {
6357 }
6386 }
6387 /* Fall through. */
6389 /* Can accept constant setting of biv only when inside inner most loop.
6390 Otherwise, a biv of an inner loop may be incorrectly recognized
6391 as a biv of the outer loop,
6392 causing code to be moved INTO the inner loop. */
6399 /* convert_modes aborts if we try to convert to or from CCmode, so just
6400 exclude that case. It is very unlikely that a condition code value
6401 would be a useful iterator anyways. convert_modes aborts if we try to
6402 convert a float mode to non-float or vice versa too. */
6406 {
6407 /* Possible bug here? Perhaps we don't know the mode of X. */
6411 }
6412 else
6420 /* Similar, since this can be a sign extension. */
6425 ;
6439 location);
6444 }
6445 }
6446 \f
6447 /* A general induction variable (giv) is any quantity that is a linear
6448 function of a basic induction variable,
6449 i.e. giv = biv * mult_val + add_val.
6450 The coefficients can be any loop invariant quantity.
6451 A giv need not be computed directly from the biv;
6452 it can be computed by way of other givs. */
6454 /* Determine whether X computes a giv.
6455 If it does, return a nonzero value
6456 which is the benefit from eliminating the computation of X;
6457 set *SRC_REG to the register of the biv that it is computed from;
6458 set *ADD_VAL and *MULT_VAL to the coefficients,
6459 such that the value of X is biv * mult + add; */
6461 static int
6465 rtx x;
6473 {
6477 /* If this is an invariant, forget it, it isn't a giv. */
6488 {
6491 /* Since this is now an invariant and wasn't before, it must be a giv
6492 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6493 with. */
6500 /* This is equivalent to a BIV. */
6507 /* Either (plus (biv) (invar)) or
6508 (plus (mult (biv) (invar_1)) (invar_2)). */
6510 {
6513 }
6514 else
6515 {
6518 }
6523 /* ADD_VAL is zero. */
6531 }
6533 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6534 unless they are CONST_INT). */
6542 else
6545 /* Always return true if this is a giv so it will be detected as such,
6546 even if the benefit is zero or negative. This allows elimination
6547 of bivs that might otherwise not be eliminated. */
6549 }
6550 \f
6551 /* Given an expression, X, try to form it as a linear function of a biv.
6552 We will canonicalize it to be of the form
6553 (plus (mult (BIV) (invar_1))
6554 (invar_2))
6555 with possible degeneracies.
6557 The invariant expressions must each be of a form that can be used as a
6558 machine operand. We surround then with a USE rtx (a hack, but localized
6559 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6560 routine; it is the caller's responsibility to strip them.
6562 If no such canonicalization is possible (i.e., two biv's are used or an
6563 expression that is neither invariant nor a biv or giv), this routine
6564 returns 0.
6566 For a nonzero return, the result will have a code of CONST_INT, USE,
6567 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6569 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6574 static rtx
6577 rtx x;
6580 {
6585 rtx tem;
6587 /* If this is not an integer mode, or if we cannot do arithmetic in this
6588 mode, this can't be a giv. */
6595 {
6602 /* Put constant last, CONST_INT last if both constant. */
6610 /* Handle addition of zero, then addition of an invariant. */
6615 {
6618 /* Adding two invariants must result in an invariant, so enclose
6619 addition operation inside a USE and return it. */
6629 else
6638 /* biv + invar or mult + invar. Return sum. */
6642 /* (a + invar_1) + invar_2. Associate. */
6643 return
6649 arg1)),
6654 }
6656 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6657 MULT to reduce cases. */
6663 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6664 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6665 Recurse to associate the second PLUS. */
6670 return
6678 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6694 /* Handle "a - b" as "a + b * (-1)". */
6700 constm1_rtx)),
6709 /* Put constant last, CONST_INT last if both constant. */
6714 /* If second argument is not now constant, not giv. */
6718 /* Handle multiply by 0 or 1. */
6726 {
6728 /* biv * invar. Done. */
6732 /* Product of two constants. */
6736 /* invar * invar is a giv, but attempt to simplify it somehow. */
6742 {
6743 /* (invar_0 * invar_1) * invar_2. Associate. */
6750 arg1)),
6752 }
6753 /* Propagate the MULT expressions to the intermost nodes. */
6755 {
6756 /* (invar_0 + invar_1) * invar_2. Distribute. */
6762 arg1),
6766 arg1)),
6768 }
6772 /* (a * invar_1) * invar_2. Associate. */
6778 arg1)),
6782 /* (a + invar_1) * invar_2. Distribute. */
6787 arg1),
6790 arg1)),
6795 }
6798 /* Shift by constant is multiply by power of two. */
6802 return
6811 /* "-a" is "a * (-1)" */
6817 /* "~a" is "-a - 1". Silly, but easy. */
6821 const1_rtx),
6825 /* Already in proper form for invariant. */
6831 /* Conditionally recognize extensions of simple IVs. After we've
6832 computed loop traversal counts and verified the range of the
6833 source IV, we'll reevaluate this as a GIV. */
6835 {
6838 {
6841 }
6842 }
6846 /* If this is a new register, we can't deal with it. */
6850 /* Check for biv or giv. */
6852 {
6856 {
6859 /* Form expression from giv and add benefit. Ensure this giv
6860 can derive another and subtract any needed adjustment if so. */
6862 /* Increasing the benefit here is risky. The only case in which it
6863 is arguably correct is if this is the only use of V. In other
6864 cases, this will artificially inflate the benefit of the current
6865 giv, and lead to suboptimal code. Thus, it is disabled, since
6866 potentially not reducing an only marginally beneficial giv is
6867 less harmful than reducing many givs that are not really
6868 beneficial. */
6869 {
6873 }
6886 {
6889 }
6890 else
6891 {
6894 }
6896 }
6899 do_default:
6900 /* If it isn't an induction variable, and it is invariant, we
6901 may be able to simplify things further by looking through
6902 the bits we just moved outside the loop. */
6904 {
6910 {
6911 /* Ok, we found a match. Substitute and simplify. */
6913 /* If we match another movable, we must use that, as
6914 this one is going away. */
6919 /* If consec is nonzero, this is a member of a group of
6920 instructions that were moved together. We handle this
6921 case only to the point of seeking to the last insn and
6922 looking for a REG_EQUAL. Fail if we don't find one. */
6924 {
6927 do
6928 {
6930 }
6936 }
6937 else
6938 {
6942 }
6945 {
6946 /* What we are most interested in is pointer
6947 arithmetic on invariants -- only take
6948 patterns we may be able to do something with. */
6954 {
6956 benefit);
6959 }
6964 {
6969 }
6970 }
6972 }
6973 }
6975 }
6977 /* Fall through to general case. */
6979 /* If invariant, return as USE (unless CONST_INT).
6980 Otherwise, not giv. */
6985 {
6994 }
6995 else
6997 }
6998 }
7000 /* This routine folds invariants such that there is only ever one
7001 CONST_INT in the summation. It is only used by simplify_giv_expr. */
7003 static rtx
7006 {
7012 {
7015 }
7018 {
7021 }
7022 else
7023 {
7026 }
7027 }
7029 static rtx
7033 {
7035 {
7039 else
7042 }
7045 else
7048 }
7049 \f
7050 /* Help detect a giv that is calculated by several consecutive insns;
7051 for example,
7052 giv = biv * M
7053 giv = giv + A
7054 The caller has already identified the first insn P as having a giv as dest;
7055 we check that all other insns that set the same register follow
7056 immediately after P, that they alter nothing else,
7057 and that the result of the last is still a giv.
7059 The value is 0 if the reg set in P is not really a giv.
7060 Otherwise, the value is the amount gained by eliminating
7061 all the consecutive insns that compute the value.
7063 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
7064 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
7066 The coefficients of the ultimate giv value are stored in
7067 *MULT_VAL and *ADD_VAL. */
7069 static int
7074 rtx p;
7075 rtx src_reg;
7076 rtx dest_reg;
7081 {
7087 rtx temp;
7088 rtx set;
7090 /* Indicate that this is a giv so that we can update the value produced in
7091 each insn of the multi-insn sequence.
7093 This induction structure will be used only by the call to
7094 general_induction_var below, so we can allocate it on our stack.
7095 If this is a giv, our caller will replace the induct var entry with
7096 a new induction structure. */
7117 {
7121 /* If libcall, skip to end of call sequence. */
7132 /* Giv created by equivalent expression. */
7138 {
7142 count--;
7146 }
7148 {
7149 /* Allow insns that set something other than this giv to a
7150 constant. Such insns are needed on machines which cannot
7151 include long constants and should not disqualify a giv. */
7160 }
7161 }
7166 }
7167 \f
7168 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7169 represented by G1. If no such expression can be found, or it is clear that
7170 it cannot possibly be a valid address, 0 is returned.
7172 To perform the computation, we note that
7173 G1 = x * v + a and
7174 G2 = y * v + b
7175 where `v' is the biv.
7177 So G2 = (y/b) * G1 + (b - a*y/x).
7179 Note that MULT = y/x.
7181 Update: A and B are now allowed to be additive expressions such that
7182 B contains all variables in A. That is, computing B-A will not require
7183 subtracting variables. */
7185 static rtx
7188 {
7189 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7194 /* If MULT is not 1, we cannot handle A with non-constants, since we
7195 would then be required to subtract multiples of the registers in A.
7196 This is theoretically possible, and may even apply to some Fortran
7197 constructs, but it is a lot of work and we do not attempt it here. */
7202 /* In general these structures are sorted top to bottom (down the PLUS
7203 chain), but not left to right across the PLUS. If B is a higher
7204 order giv than A, we can strip one level and recurse. If A is higher
7205 order, we'll eventually bail out, but won't know that until the end.
7206 If they are the same, we'll strip one level around this loop. */
7209 {
7221 /* We matched: remove one reg completely. */
7224 /* An alternate match. */
7227 /* An alternate match. */
7229 else
7230 {
7231 /* Indicates an extra register in B. Strip one level from B and
7232 recurse, hoping B was the higher order expression. */
7237 }
7238 }
7240 /* Here we are at the last level of A, go through the cases hoping to
7241 get rid of everything but a constant. */
7244 {
7257 }
7259 {
7261 }
7263 {
7268 }
7270 {
7275 else
7277 }
7282 }
7284 rtx
7287 {
7290 /* The value that G1 will be multiplied by must be a constant integer. Also,
7291 the only chance we have of getting a valid address is if b*c/a (see above
7292 for notation) is also an integer. */
7295 {
7300 }
7303 else
7304 {
7305 /* ??? Find out if the one is a multiple of the other? */
7307 }
7311 {
7312 /* Failed. If we've got a multiplication factor between G1 and G2,
7313 scale G1's addend and try again. */
7315 {
7319 {
7320 HOST_WIDE_INT m;
7324 }
7325 else
7326 {
7328 mult);
7329 }
7332 }
7333 }
7337 /* Form simplified final result. */
7342 else
7347 else
7348 {
7351 {
7355 }
7358 }
7359 }
7360 \f
7361 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7362 represented by G1. This indicates that G2 should be combined with G1 and
7363 that G2 can use (either directly or via an address expression) a register
7364 used to represent G1. */
7366 static rtx
7369 {
7372 /* With the introduction of ext dependent givs, we must care for modes.
7373 G2 must not use a wider mode than G1. */
7383 /* If these givs are identical, they can be combined. We use the results
7384 of express_from because the addends are not in a canonical form, so
7385 rtx_equal_p is a weaker test. */
7386 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7387 combination to be the other way round. */
7390 {
7392 }
7394 /* If G2 can be expressed as a function of G1 and that function is valid
7395 as an address and no more expensive than using a register for G2,
7396 the expression of G2 in terms of G1 can be used. */
7403 }
7404 \f
7405 /* Check each extension dependent giv in this class to see if its
7406 root biv is safe from wrapping in the interior mode, which would
7407 make the giv illegal. */
7409 static void
7413 {
7416 HOST_WIDE_INT start_val;
7422 /* Make sure the iteration data is available. We must have
7423 constants in order to be certain of no overflow. */
7424 /* ??? An unknown iteration count with an increment of +-1
7425 combined with friendly exit tests of against an invariant
7426 value is also amenable to optimization. Not implemented. */
7432 /* Make sure the host can represent the arithmetic. */
7434 {
7436 HOST_WIDE_INT s_end_val;
7448 /* Check for host arithmetic overflow. */
7450 {
7452 HOST_WIDE_INT s_max;
7459 /* Check zero extension of biv ok. */
7461 /* Check for host arithmetic overflow. */
7462 && (neg_incr
7465 /* Check for target arithmetic overflow. */
7466 && (neg_incr
7469 {
7471 }
7473 /* Check sign extension of biv ok. */
7474 /* ??? While it is true that overflow with signed and pointer
7475 arithmetic is undefined, I fear too many programmers don't
7476 keep this fact in mind -- myself included on occasion.
7477 So leave alone with the signed overflow optimizations. */
7479 /* Check for host arithmetic overflow. */
7480 && (neg_incr
7483 /* Check for target arithmetic overflow. */
7484 && (neg_incr
7487 {
7489 }
7490 }
7491 }
7493 /* Invalidate givs that fail the tests. */
7496 {
7501 {
7510 /* We don't know whether this value is being used as either
7511 signed or unsigned, so to safely truncate we must satisfy
7512 both. The initial check here verifies the BIV itself;
7513 once that is successful we may check its range wrt the
7514 derived GIV. */
7516 {
7520 /* We know from the above that both endpoints are nonnegative,
7521 and that there is no wrapping. Verify that both endpoints
7522 are within the (signed) range of the outer mode. */
7525 }
7530 }
7533 {
7535 {
7539 }
7540 }
7541 else
7542 {
7544 {
7549 else
7550 {
7555 else
7557 }
7562 }
7565 }
7566 }
7567 }
7569 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7571 rtx
7574 rtx value;
7575 {
7581 /* Recall that check_ext_dependent_givs verified that the known bounds
7582 of a biv did not overflow or wrap with respect to the extension for
7583 the giv. Therefore, constants need no additional adjustment. */
7587 /* Otherwise, we must adjust the value to compensate for the
7588 differing modes of the biv and the giv. */
7590 }
7591 \f
7592 struct combine_givs_stats
7593 {
7596 };
7598 static int
7602 {
7609 /* Stabilize the sort. */
7613 }
7615 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7616 any other. If so, point SAME to the giv combined with and set NEW_REG to
7617 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7618 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7620 static void
7624 {
7625 /* Additional benefit to add for being combined multiple times. */
7633 /* Count givs, because bl->giv_count is incorrect here. */
7637 giv_count++;
7639 giv_array
7650 {
7652 rtx single_use;
7657 /* If a DEST_REG GIV is used only once, do not allow it to combine
7658 with anything, for in doing so we will gain nothing that cannot
7659 be had by simply letting the GIV with which we would have combined
7660 to be reduced on its own. The losage shows up in particular with
7661 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7662 be seen elsewhere as well. */
7669 /* Add an additional weight for zero addends. */
7674 {
7675 rtx this_combine;
7680 {
7683 }
7684 }
7686 }
7688 /* Iterate, combining until we can't. */
7689 restart:
7693 {
7696 {
7702 }
7704 }
7707 {
7713 /* If it has already been combined, skip. */
7718 {
7721 /* If it has already been combined, skip. */
7723 {
7728 /* For destination, we now may replace by mem expression instead
7729 of register. This changes the costs considerably, so add the
7730 compensation. */
7740 /* ??? The new final_[bg]iv_value code does a much better job
7741 of finding replaceable giv's, and hence this code may no
7742 longer be necessary. */
7746 /* To help optimize the next set of combinations, remove
7747 this giv from the benefits of other potential mates. */
7749 {
7753 }
7760 }
7761 }
7763 /* To help optimize the next set of combinations, remove
7764 this giv from the benefits of other potential mates. */
7766 {
7768 {
7772 }
7776 /* We've finished with this giv, and everything it touched.
7777 Restart the combination so that proper weights for the
7778 rest of the givs are properly taken into account. */
7779 /* ??? Ideally we would compact the arrays at this point, so
7780 as to not cover old ground. But sanely compacting
7781 can_combine is tricky. */
7783 }
7784 }
7786 /* Clean up. */
7789 }
7790 \f
7791 /* Generate sequence for REG = B * M + A. */
7793 static rtx
7799 {
7800 rtx seq;
7801 rtx result;
7804 /* Use unsigned arithmetic. */
7812 }
7815 /* Update registers created in insn sequence SEQ. */
7817 static void
7820 rtx seq;
7821 {
7822 rtx insn;
7824 /* Update register info for alias analysis. */
7830 {
7833 {
7840 }
7841 }
7845 }
7848 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. */
7850 void
7857 basic_block before_bb;
7858 rtx before_insn;
7859 {
7860 rtx seq;
7863 {
7866 }
7868 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7871 /* Increase the lifetime of any invariants moved further in code. */
7878 /* It is possible that the expansion created lots of new registers.
7879 Iterate over the sequence we just created and record them all. */
7881 }
7884 /* Emit insns in loop pre-header to set REG = B * M + A. */
7886 void
7893 {
7894 rtx seq;
7896 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7899 /* Increase the lifetime of any invariants moved further in code.
7900 ???? Is this really necessary? */
7907 /* It is possible that the expansion created lots of new registers.
7908 Iterate over the sequence we just created and record them all. */
7910 }
7913 /* Emit insns after loop to set REG = B * M + A. */
7915 void
7922 {
7923 rtx seq;
7925 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7930 /* It is possible that the expansion created lots of new registers.
7931 Iterate over the sequence we just created and record them all. */
7933 }
7937 /* Similar to gen_add_mult, but compute cost rather than generating
7938 sequence. */
7940 static int
7946 {
7956 {
7961 }
7964 }
7965 \f
7966 /* Test whether A * B can be computed without
7967 an actual multiply insn. Value is 1 if so.
7969 ??? This function stinks because it generates a ton of wasted RTL
7970 ??? and as a result fragments GC memory to no end. There are other
7971 ??? places in the compiler which are invoked a lot and do the same
7972 ??? thing, generate wasted RTL just to see if something is possible. */
7974 static int
7976 rtx a;
7977 rtx b;
7978 {
7979 rtx tmp;
7982 /* If only one is constant, make it B. */
7986 /* If first constant, both constant, so don't need multiply. */
7990 /* If second not constant, neither is constant, so would need multiply. */
7994 /* One operand is constant, so might not need multiply insn. Generate the
7995 code for the multiply and see if a call or multiply, or long sequence
7996 of insns is generated. */
8005 {
8008 {
8018 {
8021 }
8024 }
8025 }
8035 }
8036 \f
8037 /* Check to see if loop can be terminated by a "decrement and branch until
8038 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
8039 Also try reversing an increment loop to a decrement loop
8040 to see if the optimization can be performed.
8041 Value is nonzero if optimization was performed. */
8043 /* This is useful even if the architecture doesn't have such an insn,
8044 because it might change a loops which increments from 0 to n to a loop
8045 which decrements from n to 0. A loop that decrements to zero is usually
8046 faster than one that increments from zero. */
8048 /* ??? This could be rewritten to use some of the loop unrolling procedures,
8049 such as approx_final_value, biv_total_increment, loop_iterations, and
8050 final_[bg]iv_value. */
8052 static int
8056 {
8061 rtx reg;
8062 rtx jump_label;
8063 rtx final_value;
8064 rtx start_value;
8065 rtx new_add_val;
8066 rtx comparison;
8067 rtx before_comparison;
8068 rtx p;
8069 rtx jump;
8070 rtx first_compare;
8075 /* If last insn is a conditional branch, and the insn before tests a
8076 register value, try to optimize it. Otherwise, we can't do anything. */
8085 /* Try to compute whether the compare/branch at the loop end is one or
8086 two instructions. */
8092 else
8095 {
8096 /* If more than one condition is present to control the loop, then
8097 do not proceed, as this function does not know how to rewrite
8098 loop tests with more than one condition.
8100 Look backwards from the first insn in the last comparison
8101 sequence and see if we've got another comparison sequence. */
8103 rtx jump1;
8107 }
8109 /* Check all of the bivs to see if the compare uses one of them.
8110 Skip biv's set more than once because we can't guarantee that
8111 it will be zero on the last iteration. Also skip if the biv is
8112 used between its update and the test insn. */
8115 {
8120 first_compare))
8122 }
8127 /* Look for the case where the basic induction variable is always
8128 nonnegative, and equals zero on the last iteration.
8129 In this case, add a reg_note REG_NONNEG, which allows the
8130 m68k DBRA instruction to be used. */
8138 {
8139 /* Initial value must be greater than 0,
8140 init_val % -dec_value == 0 to ensure that it equals zero on
8141 the last iteration */
8147 {
8148 /* register always nonnegative, add REG_NOTE to branch */
8156 }
8158 /* If the decrement is 1 and the value was tested as >= 0 before
8159 the loop, then we can safely optimize. */
8161 {
8174 {
8182 }
8183 }
8184 }
8187 {
8188 /* Try to change inc to dec, so can apply above optimization. */
8189 /* Can do this if:
8190 all registers modified are induction variables or invariant,
8191 all memory references have non-overlapping addresses
8192 (obviously true if only one write)
8193 allow 2 insns for the compare/jump at the end of the loop. */
8194 /* Also, we must avoid any instructions which use both the reversed
8195 biv and another biv. Such instructions will fail if the loop is
8196 reversed. We meet this condition by requiring that either
8197 no_use_except_counting is true, or else that there is only
8198 one biv. */
8200 /* 1 if the iteration var is used only to count iterations. */
8202 /* 1 if the loop has no memory store, or it has a single memory store
8203 which is reversible. */
8209 {
8213 /* If there are no givs for this biv, and the only exit is the
8214 fall through at the end of the loop, then
8215 see if perhaps there are no uses except to count. */
8219 {
8224 /* An insn that sets the biv is okay. */
8225 ;
8229 {
8230 /* If either of these insns uses the biv and sets a pseudo
8231 that has more than one usage, then the biv has uses
8232 other than counting since it's used to derive a value
8233 that is used more than one time. */
8235 regs);
8237 {
8240 }
8241 }
8243 {
8246 }
8247 }
8249 /* A biv has uses besides counting if it is used to set
8250 another biv. */
8254 {
8257 }
8258 }
8261 /* No need to worry about MEMs. */
8262 ;
8264 {
8269 /* If the loop has a single store, and the destination address is
8270 invariant, then we can't reverse the loop, because this address
8271 might then have the wrong value at loop exit.
8272 This would work if the source was invariant also, however, in that
8273 case, the insn should have been moved out of the loop. */
8276 {
8279 /* If we could prove that each of the memory locations
8280 written to was different, then we could reverse the
8281 store -- but we don't presently have any way of
8282 knowing that. */
8285 /* If the store depends on a register that is set after the
8286 store, it depends on the initial value, and is thus not
8287 reversible. */
8289 {
8296 }
8297 }
8298 }
8299 else
8302 /* This code only acts for innermost loops. Also it simplifies
8303 the memory address check by only reversing loops with
8304 zero or one memory access.
8305 Two memory accesses could involve parts of the same array,
8306 and that can't be reversed.
8307 If the biv is used only for counting, than we don't need to worry
8308 about all these things. */
8314 && reversible_mem_store
8319 {
8320 rtx tem;
8322 /* Loop can be reversed. */
8326 /* Now check other conditions:
8328 The increment must be a constant, as must the initial value,
8329 and the comparison code must be LT.
8331 This test can probably be improved since +/- 1 in the constant
8332 can be obtained by changing LT to LE and vice versa; this is
8333 confusing. */
8336 /* for constants, LE gets turned into LT */
8340 {
8351 comparison_const_width
8353 else
8354 comparison_const_width
8358 comparison_sign_mask
8361 /* If the comparison value is not a loop invariant, then we
8362 can not reverse this loop.
8364 ??? If the insns which initialize the comparison value as
8365 a whole compute an invariant result, then we could move
8366 them out of the loop and proceed with loop reversal. */
8374 /* Normalize the initial value if it is an integer and
8375 has no other use except as a counter. This will allow
8376 a few more loops to be reversed. */
8380 {
8382 /* The code below requires comparison_val to be a multiple
8383 of add_val in order to do the loop reversal, so
8384 round up comparison_val to a multiple of add_val.
8385 Since comparison_value is constant, we know that the
8386 current comparison code is LT. */
8388 comparison_val
8390 /* We postpone overflow checks for COMPARISON_VAL here;
8391 even if there is an overflow, we might still be able to
8392 reverse the loop, if converting the loop exit test to
8393 NE is possible. */
8395 }
8397 /* First check if we can do a vanilla loop reversal. */
8399 /* If we have a decrement_and_branch_on_count,
8400 prefer the NE test, since this will allow that
8401 instruction to be generated. Note that we must
8402 use a vanilla loop reversal if the biv is used to
8403 calculate a giv or has a non-counting use. */
8404 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8405 && defined (HAVE_decrement_and_branch_on_count)
8409 #endif
8411 /* Now do postponed overflow checks on COMPARISON_VAL. */
8414 {
8415 /* Register will always be nonnegative, with value
8416 0 on last iteration */
8420 }
8424 {
8427 }
8428 else
8434 /* If the initial value is not zero, or if the comparison
8435 value is not an exact multiple of the increment, then we
8436 can not reverse this loop. */
8439 {
8442 }
8443 else
8444 {
8447 }
8451 /* Reset these in case we normalized the initial value
8452 and comparison value above. */
8455 {
8457 final_value
8459 }
8462 /* Save some info needed to produce the new insns. */
8467 /* Set start_value; if this is not a CONST_INT, we need
8468 to generate a SUB.
8469 Initialize biv to start_value before loop start.
8470 The old initializing insn will be deleted as a
8471 dead store by flow.c. */
8474 {
8477 }
8479 {
8487 start_value
8493 }
8495 {
8498 initial_value);
8502 start_value
8505 }
8506 else
8507 /* We could handle the other cases too, but it'll be
8508 better to have a testcase first. */
8511 /* We may not have a single insn which can increment a reg, so
8512 create a sequence to hold all the insns from expand_inc. */
8521 /* Update biv info to reflect its new status. */
8526 /* Update loop info. */
8535 /* Inc LABEL_NUSES so that delete_insn will
8536 not delete the label. */
8539 /* Emit an insn after the end of the loop to set the biv's
8540 proper exit value if it is used anywhere outside the loop. */
8546 /* Delete compare/branch at end of loop. */
8551 /* Add new compare/branch insn at end of loop. */
8563 ;
8569 {
8571 {
8572 /* Increment of LABEL_NUSES done above. */
8573 /* Register is now always nonnegative,
8574 so add REG_NONNEG note to the branch. */
8577 }
8579 }
8581 /* No insn may reference both the reversed and another biv or it
8582 will fail (see comment near the top of the loop reversal
8583 code).
8584 Earlier on, we have verified that the biv has no use except
8585 counting, or it is the only biv in this function.
8586 However, the code that computes no_use_except_counting does
8587 not verify reg notes. It's possible to have an insn that
8588 references another biv, and has a REG_EQUAL note with an
8589 expression based on the reversed biv. To avoid this case,
8590 remove all REG_EQUAL notes based on the reversed biv
8591 here. */
8594 {
8597 /* If this is a set of a GIV based on the reversed biv, any
8598 REG_EQUAL notes should still be correct. */
8605 {
8610 else
8612 }
8613 }
8615 /* Mark that this biv has been reversed. Each giv which depends
8616 on this biv, and which is also live past the end of the loop
8617 will have to be fixed up. */
8622 {
8626 else
8628 }
8631 }
8632 }
8633 }
8636 }
8637 \f
8638 /* Verify whether the biv BL appears to be eliminable,
8639 based on the insns in the loop that refer to it.
8641 If ELIMINATE_P is nonzero, actually do the elimination.
8643 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8644 determine whether invariant insns should be placed inside or at the
8645 start of the loop. */
8647 static int
8653 {
8656 rtx p;
8658 /* Scan all insns in the loop, stopping if we find one that uses the
8659 biv in a way that we cannot eliminate. */
8662 {
8666 rtx note;
8668 /* If this is a libcall that sets a giv, skip ahead to its end. */
8670 {
8674 {
8679 {
8686 }
8687 }
8688 }
8690 /* Closely examine the insn if the biv is mentioned. */
8695 {
8701 }
8703 /* If we are eliminating, kill REG_EQUAL notes mentioning the biv. */
8708 }
8711 {
8716 }
8719 }
8720 \f
8721 /* INSN and REFERENCE are instructions in the same insn chain.
8722 Return nonzero if INSN is first. */
8724 int
8727 {
8731 {
8732 /* Start with test for not first so that INSN == REFERENCE yields not
8733 first. */
8739 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8740 previous insn, hence the <= comparison below does not work if
8741 P is a note. */
8752 }
8753 }
8755 /* We are trying to eliminate BIV in INSN using GIV. Return nonzero if
8756 the offset that we have to take into account due to auto-increment /
8757 div derivation is zero. */
8758 static int
8761 rtx insn;
8762 {
8763 /* If the giv V had the auto-inc address optimization applied
8764 to it, and INSN occurs between the giv insn and the biv
8765 insn, then we'd have to adjust the value used here.
8766 This is rare, so we don't bother to make this possible. */
8775 }
8777 /* If BL appears in X (part of the pattern of INSN), see if we can
8778 eliminate its use. If so, return 1. If not, return 0.
8780 If BIV does not appear in X, return 1.
8782 If ELIMINATE_P is nonzero, actually do the elimination.
8783 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8784 Depending on how many items have been moved out of the loop, it
8785 will either be before INSN (when WHERE_INSN is nonzero) or at the
8786 start of the loop (when WHERE_INSN is zero). */
8788 static int
8794 basic_block where_bb;
8795 rtx where_insn;
8796 {
8802 #ifdef HAVE_cc0
8804 #endif
8810 {
8812 /* If we haven't already been able to do something with this BIV,
8813 we can't eliminate it. */
8819 /* If this sets the BIV, it is not a problem. */
8823 /* If this is an insn that defines a giv, it is also ok because
8824 it will go away when the giv is reduced. */
8829 #ifdef HAVE_cc0
8831 {
8832 /* Can replace with any giv that was reduced and
8833 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8834 Require a constant for MULT_VAL, so we know it's nonzero.
8835 ??? We disable this optimization to avoid potential
8836 overflows. */
8844 {
8851 /* If the giv has the opposite direction of change,
8852 then reverse the comparison. */
8856 else
8859 /* We can probably test that giv's reduced reg. */
8862 }
8864 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8865 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8866 Require a constant for MULT_VAL, so we know it's nonzero.
8867 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8868 overflow problem. */
8880 {
8887 /* If the giv has the opposite direction of change,
8888 then reverse the comparison. */
8892 else
8896 /* Replace biv with the giv's reduced register. */
8901 /* Insn doesn't support that constant or invariant. Copy it
8902 into a register (it will be a loop invariant.) */
8909 /* Substitute the new register for its invariant value in
8910 the compare expression. */
8914 }
8915 }
8916 #endif
8923 /* See if either argument is the biv. */
8928 else
8932 {
8933 /* First try to replace with any giv that has constant positive
8934 mult_val and constant add_val. We might be able to support
8935 negative mult_val, but it seems complex to do it in general. */
8947 {
8951 /* Don't eliminate if the linear combination that makes up
8952 the giv overflows when it is applied to ARG. */
8954 {
8955 rtx add_val;
8959 else
8965 }
8970 /* Replace biv with the giv's reduced reg. */
8973 /* If all constants are actually constant integers and
8974 the derived constant can be directly placed in the COMPARE,
8975 do so. */
8978 {
8981 }
8982 else
8983 {
8984 /* Otherwise, load it into a register. */
8989 }
8995 }
8997 /* Look for giv with positive constant mult_val and nonconst add_val.
8998 Insert insns to calculate new compare value.
8999 ??? Turn this off due to possible overflow. */
9007 {
9008 rtx tem;
9018 /* Replace biv with giv's reduced register. */
9022 /* Compute value to compare against. */
9026 /* Use it in this insn. */
9030 }
9031 }
9033 {
9035 {
9036 /* Look for giv with constant positive mult_val and nonconst
9037 add_val. Insert insns to compute new compare value.
9038 ??? Turn this off due to possible overflow. */
9045 {
9046 rtx tem;
9056 /* Replace biv with giv's reduced register. */
9060 /* Compute value to compare against. */
9067 }
9068 }
9070 /* This code has problems. Basically, you can't know when
9071 seeing if we will eliminate BL, whether a particular giv
9072 of ARG will be reduced. If it isn't going to be reduced,
9073 we can't eliminate BL. We can try forcing it to be reduced,
9074 but that can generate poor code.
9076 The problem is that the benefit of reducing TV, below should
9077 be increased if BL can actually be eliminated, but this means
9078 we might have to do a topological sort of the order in which
9079 we try to process biv. It doesn't seem worthwhile to do
9080 this sort of thing now. */
9082 #if 0
9083 /* Otherwise the reg compared with had better be a biv. */
9088 /* Look for a pair of givs, one for each biv,
9089 with identical coefficients. */
9091 {
9103 {
9110 /* Replace biv with its giv's reduced reg. */
9112 /* Replace other operand with the other giv's
9113 reduced reg. */
9116 }
9117 }
9118 #endif
9119 }
9121 /* If we get here, the biv can't be eliminated. */
9125 /* If this address is a DEST_ADDR giv, it doesn't matter if the
9126 biv is used in it, since it will be replaced. */
9134 }
9136 /* See if any subexpression fails elimination. */
9139 {
9141 {
9154 }
9155 }
9158 }
9159 \f
9160 /* Return nonzero if the last use of REG
9161 is in an insn following INSN in the same basic block. */
9163 static int
9165 rtx reg;
9166 rtx insn;
9167 {
9168 rtx n;
9172 {
9175 }
9177 }
9178 \f
9179 /* Called via `note_stores' to record the initial value of a biv. Here we
9180 just record the location of the set and process it later. */
9182 static void
9184 rtx dest;
9185 rtx set;
9187 {
9198 /* If this is the first set found, record it. */
9200 {
9203 }
9204 }
9205 \f
9206 /* If any of the registers in X are "old" and currently have a last use earlier
9207 than INSN, update them to have a last use of INSN. Their actual last use
9208 will be the previous insn but it will not have a valid uid_luid so we can't
9209 use it. X must be a source expression only. */
9211 static void
9213 rtx x;
9214 rtx insn;
9215 {
9216 /* Check for the case where INSN does not have a valid luid. In this case,
9217 there is no need to modify the regno_last_uid, as this can only happen
9218 when code is inserted after the loop_end to set a pseudo's final value,
9219 and hence this insn will never be the last use of x.
9220 ???? This comment is not correct. See for example loop_givs_reduce.
9221 This may insert an insn before another new insn. */
9225 {
9227 }
9228 else
9229 {
9233 {
9239 }
9240 }
9241 }
9242 \f
9243 /* Given an insn INSN and condition COND, return the condition in a
9244 canonical form to simplify testing by callers. Specifically:
9246 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9247 (2) Both operands will be machine operands; (cc0) will have been replaced.
9248 (3) If an operand is a constant, it will be the second operand.
9249 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9250 for GE, GEU, and LEU.
9252 If the condition cannot be understood, or is an inequality floating-point
9253 comparison which needs to be reversed, 0 will be returned.
9255 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
9257 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9258 insn used in locating the condition was found. If a replacement test
9259 of the condition is desired, it should be placed in front of that
9260 insn and we will be sure that the inputs are still valid.
9262 If WANT_REG is nonzero, we wish the condition to be relative to that
9263 register, if possible. Therefore, do not canonicalize the condition
9264 further. */
9266 rtx
9268 rtx insn;
9269 rtx cond;
9272 rtx want_reg;
9273 {
9276 rtx set;
9277 rtx tem;
9295 /* If we are comparing a register with zero, see if the register is set
9296 in the previous insn to a COMPARE or a comparison operation. Perform
9297 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9298 in cse.c */
9303 {
9304 /* Set nonzero when we find something of interest. */
9307 #ifdef HAVE_cc0
9308 /* If comparison with cc0, import actual comparison from compare
9309 insn. */
9311 {
9322 }
9323 #endif
9325 /* If this is a COMPARE, pick up the two things being compared. */
9327 {
9331 }
9335 /* Go back to the previous insn. Stop if it is not an INSN. We also
9336 stop if it isn't a single set or if it has a REG_INC note because
9337 we don't want to bother dealing with it. */
9351 /* If this is setting OP0, get what it sets it to if it looks
9352 relevant. */
9354 {
9356 #ifdef FLOAT_STORE_FLAG_VALUE
9357 REAL_VALUE_TYPE fsfv;
9358 #endif
9360 /* ??? We may not combine comparisons done in a CCmode with
9361 comparisons not done in a CCmode. This is to aid targets
9362 like Alpha that have an IEEE compliant EQ instruction, and
9363 a non-IEEE compliant BEQ instruction. The use of CCmode is
9364 actually artificial, simply to prevent the combination, but
9365 should not affect other platforms.
9367 However, we must allow VOIDmode comparisons to match either
9368 CCmode or non-CCmode comparison, because some ports have
9369 modeless comparisons inside branch patterns.
9371 ??? This mode check should perhaps look more like the mode check
9372 in simplify_comparison in combine. */
9380 && (STORE_FLAG_VALUE
9383 #ifdef FLOAT_STORE_FLAG_VALUE
9388 #endif
9389 ))
9400 && (STORE_FLAG_VALUE
9403 #ifdef FLOAT_STORE_FLAG_VALUE
9408 #endif
9409 ))
9415 {
9418 }
9419 else
9421 }
9424 /* If this sets OP0, but not directly, we have to give up. */
9428 {
9432 {
9437 }
9442 }
9443 }
9445 /* If constant is first, put it last. */
9449 /* If OP0 is the result of a comparison, we weren't able to find what
9450 was really being compared, so fail. */
9454 /* Canonicalize any ordered comparison with integers involving equality
9455 if we can do computations in the relevant mode and we do not
9456 overflow. */
9461 {
9464 unsigned HOST_WIDE_INT max_val
9468 {
9474 /* When cross-compiling, const_val might be sign-extended from
9475 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9495 }
9496 }
9498 /* Never return CC0; return zero instead. */
9503 }
9505 /* Given a jump insn JUMP, return the condition that will cause it to branch
9506 to its JUMP_LABEL. If the condition cannot be understood, or is an
9507 inequality floating-point comparison which needs to be reversed, 0 will
9508 be returned.
9510 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9511 insn used in locating the condition was found. If a replacement test
9512 of the condition is desired, it should be placed in front of that
9513 insn and we will be sure that the inputs are still valid. */
9515 rtx
9517 rtx jump;
9519 {
9520 rtx cond;
9522 rtx set;
9524 /* If this is not a standard conditional jump, we can't parse it. */
9532 /* If this branches to JUMP_LABEL when the condition is false, reverse
9533 the condition. */
9534 reverse
9539 }
9541 /* Similar to above routine, except that we also put an invariant last
9542 unless both operands are invariants. */
9544 rtx
9547 rtx x;
9548 {
9558 }
9560 /* Scan the function and determine whether it has indirect (computed) jumps.
9562 This is taken mostly from flow.c; similar code exists elsewhere
9563 in the compiler. It may be useful to put this into rtlanal.c. */
9564 static int
9566 rtx start;
9567 {
9568 rtx insn;
9575 }
9577 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9578 documentation for LOOP_MEMS for the definition of `appropriate'.
9579 This function is called from prescan_loop via for_each_rtx. */
9581 static int
9585 {
9594 {
9599 /* We're not interested in MEMs that are only clobbered. */
9603 /* We're not interested in the MEM associated with a
9604 CONST_DOUBLE, so there's no need to traverse into this. */
9608 /* We're not interested in any MEMs that only appear in notes. */
9612 /* This is not a MEM. */
9614 }
9616 /* See if we've already seen this MEM. */
9619 {
9621 /* The modes of the two memory accesses are different. If
9622 this happens, something tricky is going on, and we just
9623 don't optimize accesses to this MEM. */
9627 }
9629 /* Resize the array, if necessary. */
9631 {
9634 else
9640 }
9642 /* Actually insert the MEM. */
9644 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9645 because we can't put it in a register. We still store it in the
9646 table, though, so that if we see the same address later, but in a
9647 non-BLK mode, we'll not think we can optimize it at that point. */
9653 }
9656 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9658 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9659 register that is modified by an insn between FROM and TO. If the
9660 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9661 more, stop incrementing it, to avoid overflow.
9663 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9664 register I is used, if it is only used once. Otherwise, it is set
9665 to 0 (for no uses) or const0_rtx for more than one use. This
9666 parameter may be zero, in which case this processing is not done.
9668 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9669 optimize register I. */
9671 static void
9675 {
9678 /* last_set[n] is nonzero iff reg n has been set in the current
9679 basic block. In that case, it is the insn that last set reg n. */
9681 rtx insn;
9687 /* Grow the regs array if not allocated or too small. */
9689 {
9695 /* Zero the new elements. */
9698 }
9700 /* Clear previously scanned fields but do not clear n_times_set. */
9702 {
9706 }
9710 /* Scan the loop, recording register usage. */
9713 {
9715 {
9716 /* Record registers that have exactly one use. */
9719 /* Include uses in REG_EQUAL notes. */
9727 {
9731 last_set);
9732 }
9733 }
9738 /* Invalidate all registers used for function argument passing.
9739 We check rtx_varies_p for the same reason as below, to allow
9740 optimizing PIC calculations. */
9742 {
9743 rtx link;
9745 link;
9747 {
9754 }
9755 }
9756 }
9758 /* Invalidate all hard registers clobbered by calls. With one exception:
9759 a call-clobbered PIC register is still function-invariant for our
9760 purposes, since we can hoist any PIC calculations out of the loop.
9761 Thus the call to rtx_varies_p. */
9766 {
9769 }
9771 #ifdef AVOID_CCMODE_COPIES
9772 /* Don't try to move insns which set CC registers if we should not
9773 create CCmode register copies. */
9777 #endif
9779 /* Set regs->array[I].n_times_set for the new registers. */
9784 }
9786 /* Returns the number of real INSNs in the LOOP. */
9788 static int
9791 {
9793 rtx insn;
9801 }
9803 /* Move MEMs into registers for the duration of the loop. */
9805 static void
9808 {
9815 rtx end_label;
9816 /* Nonzero if the next instruction may never be executed. */
9823 /* We cannot use next_label here because it skips over normal insns. */
9828 /* Check to see if it's possible that some instructions in the loop are
9829 never executed. Also check if there is a goto out of the loop other
9830 than right after the end of the loop. */
9834 {
9838 /* If we enter the loop in the middle, and scan
9839 around to the beginning, don't set maybe_never
9840 for that. This must be an unconditional jump,
9841 otherwise the code at the top of the loop might
9842 never be executed. Unconditional jumps are
9843 followed a by barrier then loop end. */
9848 {
9849 /* If this is a jump outside of the loop but not right
9850 after the end of the loop, we would have to emit new fixup
9851 sequences for each such label. */
9853 JUMP_INSN is executed, we must be conservative. */
9862 /* Something complicated. */
9864 else
9865 /* If there are any more instructions in the loop, they
9866 might not be reached. */
9868 }
9871 }
9873 /* Find start of the extended basic block that enters the loop. */
9877 ;
9882 /* Build table of mems that get set to constant values before the
9883 loop. */
9887 /* Actually move the MEMs. */
9889 {
9890 regset_head load_copies;
9891 regset_head store_copies;
9893 rtx reg;
9895 rtx mem_list_entry;
9899 /* There's no telling whether or not MEM is modified. */
9902 /* Go through the MEMs written to in the loop to see if this
9903 one is aliased by one of them. */
9906 {
9911 {
9912 /* MEM is indeed aliased by this store. */
9915 }
9917 }
9923 /* If this MEM is written to, we must be sure that there
9924 are no reads from another MEM that aliases this one. */
9926 {
9930 {
9934 VOIDmode,
9936 rtx_varies_p))
9937 {
9938 /* It's not safe to hoist loop_info->mems[i] out of
9939 the loop because writes to it might not be
9940 seen by reads from loop_info->mems[j]. */
9943 }
9944 }
9945 }
9948 /* We can't access the MEM outside the loop; it might
9949 cause a trap that wouldn't have happened otherwise. */
9953 /* We thought we were going to lift this MEM out of the
9954 loop, but later discovered that we could not. */
9960 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9961 order to keep scan_loop from moving stores to this MEM
9962 out of the loop just because this REG is neither a
9963 user-variable nor used in the loop test. */
9968 /* Now, replace all references to the MEM with the
9969 corresponding pseudos. */
9974 {
9976 {
9977 rtx set;
9981 /* See if this copies the mem into a register that isn't
9982 modified afterwards. We'll try to do copy propagation
9983 a little further on. */
9985 /* @@@ This test is _way_ too conservative. */
9986 && ! maybe_never
9994 /* See if this copies the mem from a register that isn't
9995 modified afterwards. We'll try to remove the
9996 redundant copy later on by doing a little register
9997 renaming and copy propagation. This will help
9998 to untangle things for the BIV detection code. */
10000 && ! maybe_never
10008 /* If this is a call which uses / clobbers this memory
10009 location, we must not change the interface here. */
10013 {
10017 }
10018 else
10019 /* Replace the memory reference with the shadow register. */
10022 }
10027 }
10032 /* We couldn't replace all occurrences of the MEM. */
10034 else
10035 {
10036 /* Load the memory immediately before LOOP->START, which is
10037 the NOTE_LOOP_BEG. */
10039 rtx set;
10045 {
10049 {
10053 /* Extending hard register lifetimes causes crash
10054 on SRC targets. Doing so on non-SRC is
10055 probably also not good idea, since we most
10056 probably have pseudoregister equivalence as
10057 well. */
10060 }
10061 /* Use the constant equivalence if that is cheap enough. */
10067 {
10070 }
10072 /* If best_equiv is nonzero, we know that MEM is set to a
10073 constant or register before the loop. We will use this
10074 knowledge to initialize the shadow register with that
10075 constant or reg rather than by loading from MEM. */
10078 }
10083 {
10086 {
10089 }
10090 }
10096 {
10098 {
10101 }
10103 /* Store the memory immediately after END, which is
10104 the NOTE_LOOP_END. */
10107 }
10110 {
10115 }
10117 /* Attempt a bit of copy propagation. This helps untangle the
10118 data flow, and enables {basic,general}_induction_var to find
10119 more bivs/givs. */
10120 EXECUTE_IF_SET_IN_REG_SET
10122 {
10124 });
10127 EXECUTE_IF_SET_IN_REG_SET
10129 {
10131 });
10133 }
10134 }
10137 {
10138 /* Now, we need to replace all references to the previous exit
10139 label with the new one. */
10140 replace_label_data rr;
10146 {
10148 }
10149 }
10152 }
10154 /* For communication between note_reg_stored and its caller. */
10155 struct note_reg_stored_arg
10156 {
10158 rtx reg;
10159 };
10161 /* Called via note_stores, record in SET_SEEN whether X, which is written,
10162 is equal to ARG. */
10163 static void
10167 {
10171 }
10173 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10174 There must be exactly one insn that sets this pseudo; it will be
10175 deleted if all replacements succeed and we can prove that the register
10176 is not used after the loop. */
10178 static void
10181 rtx replacement;
10183 {
10184 /* This is the reg that we are copying from. */
10187 rtx insn;
10188 /* These help keep track of whether we replaced all uses of the reg. */
10195 {
10196 rtx set;
10198 /* Only substitute within one extended basic block from the initializing
10199 insn. */
10206 /* Is this the initializing insn? */
10211 {
10218 }
10220 /* Only substitute after seeing the initializing insn. */
10222 {
10229 /* Stop replacing when REPLACEMENT is modified. */
10234 {
10237 /* It is possible that we've turned previously valid REG_EQUAL to
10238 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10239 REPLACEMENT is modified, we get different meaning. */
10243 }
10244 }
10245 }
10249 {
10253 {
10254 rtx first;
10255 rtx retval_note;
10257 /* Assume we're just deleting INIT_INSN. */
10259 /* Look for REG_RETVAL note. If we're deleting the end of
10260 the libcall sequence, the whole sequence can go. */
10262 /* If we found a REG_RETVAL note, find the first instruction
10263 in the sequence. */
10267 /* Delete the instructions. */
10269 }
10272 }
10273 }
10275 /* Replace all the instructions from FIRST up to and including LAST
10276 with NOTE_INSN_DELETED notes. */
10278 static void
10280 rtx first;
10281 rtx last;
10282 {
10284 {
10290 /* If this was the LAST instructions we're supposed to delete,
10291 we're done. */
10296 }
10297 }
10299 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10300 loop LOOP if the order of the sets of these registers can be
10301 swapped. There must be exactly one insn within the loop that sets
10302 this pseudo followed immediately by a move insn that sets
10303 REPLACEMENT with REGNO. */
10304 static void
10307 rtx replacement;
10309 {
10310 rtx insn;
10319 {
10320 /* Search for the insn that copies REGNO to NEW_REGNO? */
10328 }
10331 {
10332 rtx prev_insn;
10333 rtx prev_set;
10335 /* Some DEF-USE info would come in handy here to make this
10336 function more general. For now, just check the previous insn
10337 which is the most likely candidate for setting REGNO. */
10345 {
10346 /* We have:
10347 (set (reg regno) (expr))
10348 (set (reg new_regno) (reg regno))
10350 so try converting this to:
10351 (set (reg new_regno) (expr))
10352 (set (reg regno) (reg new_regno))
10354 The former construct is often generated when a global
10355 variable used for an induction variable is shadowed by a
10356 register (NEW_REGNO). The latter construct improves the
10357 chances of GIV replacement and BIV elimination. */
10367 {
10374 /* Update first use of REGNO. */
10378 /* Now perform copy propagation to hopefully
10379 remove all uses of REGNO within the loop. */
10381 }
10382 }
10383 }
10384 }
10386 /* Replace MEM with its associated pseudo register. This function is
10387 called from load_mems via for_each_rtx. DATA is actually a pointer
10388 to a structure describing the instruction currently being scanned
10389 and the MEM we are currently replacing. */
10391 static int
10395 {
10403 {
10408 /* We're not interested in the MEM associated with a
10409 CONST_DOUBLE, so there's no need to traverse into one. */
10413 /* This is not a MEM. */
10415 }
10418 /* This is not the MEM we are currently replacing. */
10421 /* Actually replace the MEM. */
10425 }
10427 static void
10429 rtx insn;
10430 rtx mem;
10431 rtx reg;
10432 {
10433 loop_replace_args args;
10440 }
10442 /* Replace one register with another. Called through for_each_rtx; PX points
10443 to the rtx being scanned. DATA is actually a pointer to
10444 a structure of arguments. */
10446 static int
10450 {
10461 }
10463 static void
10465 rtx insn;
10466 rtx reg;
10467 rtx replacement;
10468 {
10469 loop_replace_args args;
10476 }
10477 \f
10478 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10479 (ignored in the interim). */
10481 static rtx
10484 basic_block where_bb ATTRIBUTE_UNUSED;
10485 rtx where_insn;
10486 rtx pattern;
10487 {
10489 }
10492 /* If WHERE_INSN is nonzero emit insn for PATTERN before WHERE_INSN
10493 in basic block WHERE_BB (ignored in the interim) within the loop
10494 otherwise hoist PATTERN into the loop pre-header. */
10496 rtx
10499 basic_block where_bb ATTRIBUTE_UNUSED;
10500 rtx where_insn;
10501 rtx pattern;
10502 {
10506 }
10509 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10510 WHERE_BB (ignored in the interim) within the loop. */
10512 static rtx
10515 basic_block where_bb ATTRIBUTE_UNUSED;
10516 rtx where_insn;
10517 rtx pattern;
10518 {
10520 }
10523 /* Hoist insn for PATTERN into the loop pre-header. */
10525 rtx
10528 rtx pattern;
10529 {
10531 }
10534 /* Hoist call insn for PATTERN into the loop pre-header. */
10536 static rtx
10539 rtx pattern;
10540 {
10542 }
10545 /* Sink insn for PATTERN after the loop end. */
10547 rtx
10550 rtx pattern;
10551 {
10553 }
10555 /* bl->final_value can be eighter general_operand or PLUS of general_operand
10556 and constant. Emit sequence of instructions to load it into REG. */
10557 static rtx
10560 {
10561 rtx seq;
10569 }
10571 /* If the loop has multiple exits, emit insn for PATTERN before the
10572 loop to ensure that it will always be executed no matter how the
10573 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10574 since this is slightly more efficient. */
10576 static rtx
10579 rtx pattern;
10580 {
10583 else
10585 }
10586 \f
10587 static void
10592 {
10600 iv_num++;
10605 {
10608 }
10609 }
10612 static void
10617 {
10619 rtx incr;
10630 {
10633 }
10635 {
10638 }
10642 {
10646 }
10649 {
10653 }
10655 /* List the increments. */
10657 {
10661 }
10663 /* List the givs. */
10665 {
10670 else
10673 }
10674 }
10677 static void
10682 {
10693 {
10697 }
10700 }
10703 static void
10708 {
10715 else
10731 {
10733 {
10745 }
10746 }
10757 {
10761 }
10764 }
10767 void
10770 {
10772 }
10775 void
10778 {
10780 }
10783 void
10786 {
10788 }
10791 void
10794 {
10796 }
10799 #define LOOP_BLOCK_NUM_1(INSN) \
10800 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10802 /* The notes do not have an assigned block, so look at the next insn. */
10803 #define LOOP_BLOCK_NUM(INSN) \
10804 ((INSN) ? (GET_CODE (INSN) == NOTE \
10805 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10806 : LOOP_BLOCK_NUM_1 (INSN)) \
10807 : -1)
10809 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10811 static void
10816 {
10817 rtx label;
10822 /* Print diagnostics to compare our concept of a loop with
10823 what the loop notes say. */
10838 {
10858 {
10861 {
10864 }
10865 }
10868 /* This can happen when a marked loop appears as two nested loops,
10869 say from while (a || b) {}. The inner loop won't match
10870 the loop markers but the outer one will. */
10873 }
10874 }
10876 /* Call this function from the debugger to dump LOOP. */
10878 void
10881 {
10883 }
10885 /* Call this function from the debugger to dump LOOPS. */
10887 void
10890 {
10892 }