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1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
106 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
138 /* Number of attempts to combine instructions in this function. */
142 /* Number of attempts that got as far as substitution in this function. */
146 /* Number of instructions combined with added SETs in this function. */
150 /* Number of instructions combined in this function. */
154 /* Totals over entire compilation. */
158 /* combine_instructions may try to replace the right hand side of the
159 second instruction with the value of an associated REG_EQUAL note
160 before throwing it at try_combine. That is problematic when there
161 is a REG_DEAD note for a register used in the old right hand side
162 and can cause distribute_notes to do wrong things. This is the
163 second instruction if it has been so modified, null otherwise. */
167 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
171 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
174 \f
176 /* Record last point of death of (hard or pseudo) register n. */
179 /* Record last point of modification of (hard or pseudo) register n. */
182 /* The next group of fields allows the recording of the last value assigned
183 to (hard or pseudo) register n. We use this information to see if an
184 operation being processed is redundant given a prior operation performed
185 on the register. For example, an `and' with a constant is redundant if
186 all the zero bits are already known to be turned off.
188 We use an approach similar to that used by cse, but change it in the
189 following ways:
191 (1) We do not want to reinitialize at each label.
192 (2) It is useful, but not critical, to know the actual value assigned
193 to a register. Often just its form is helpful.
195 Therefore, we maintain the following fields:
197 last_set_value the last value assigned
198 last_set_label records the value of label_tick when the
199 register was assigned
200 last_set_table_tick records the value of label_tick when a
201 value using the register is assigned
202 last_set_invalid set to nonzero when it is not valid
203 to use the value of this register in some
204 register's value
206 To understand the usage of these tables, it is important to understand
207 the distinction between the value in last_set_value being valid and
208 the register being validly contained in some other expression in the
209 table.
211 (The next two parameters are out of date).
213 reg_stat[i].last_set_value is valid if it is nonzero, and either
214 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
216 Register I may validly appear in any expression returned for the value
217 of another register if reg_n_sets[i] is 1. It may also appear in the
218 value for register J if reg_stat[j].last_set_invalid is zero, or
219 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
221 If an expression is found in the table containing a register which may
222 not validly appear in an expression, the register is replaced by
223 something that won't match, (clobber (const_int 0)). */
225 /* Record last value assigned to (hard or pseudo) register n. */
227 rtx last_set_value;
229 /* Record the value of label_tick when an expression involving register n
230 is placed in last_set_value. */
234 /* Record the value of label_tick when the value for register n is placed in
235 last_set_value. */
239 /* These fields are maintained in parallel with last_set_value and are
240 used to store the mode in which the register was last set, the bits
241 that were known to be zero when it was last set, and the number of
242 sign bits copies it was known to have when it was last set. */
248 /* Set nonzero if references to register n in expressions should not be
249 used. last_set_invalid is set nonzero when this register is being
250 assigned to and last_set_table_tick == label_tick. */
254 /* Some registers that are set more than once and used in more than one
255 basic block are nevertheless always set in similar ways. For example,
256 a QImode register may be loaded from memory in two places on a machine
257 where byte loads zero extend.
259 We record in the following fields if a register has some leading bits
260 that are always equal to the sign bit, and what we know about the
261 nonzero bits of a register, specifically which bits are known to be
262 zero.
264 If an entry is zero, it means that we don't know anything special. */
270 /* Record the value of the label_tick when the last truncation
271 happened. The field truncated_to_mode is only valid if
272 truncation_label == label_tick. */
276 /* Record the last truncation seen for this register. If truncation
277 is not a nop to this mode we might be able to save an explicit
278 truncation if we know that value already contains a truncated
279 value. */
287 /* One plus the highest pseudo for which we track REG_N_SETS.
288 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
289 but during combine_split_insns new pseudos can be created. As we don't have
290 updated DF information in that case, it is hard to initialize the array
291 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
292 so instead of growing the arrays, just assume all newly created pseudos
293 during combine might be set multiple times. */
297 /* Record the luid of the last insn that invalidated memory
298 (anything that writes memory, and subroutine calls, but not pushes). */
302 /* Record the luid of the last CALL_INSN
303 so we can tell whether a potential combination crosses any calls. */
307 /* When `subst' is called, this is the insn that is being modified
308 (by combining in a previous insn). The PATTERN of this insn
309 is still the old pattern partially modified and it should not be
310 looked at, but this may be used to examine the successors of the insn
311 to judge whether a simplification is valid. */
315 /* This is the lowest LUID that `subst' is currently dealing with.
316 get_last_value will not return a value if the register was set at or
317 after this LUID. If not for this mechanism, we could get confused if
318 I2 or I1 in try_combine were an insn that used the old value of a register
319 to obtain a new value. In that case, we might erroneously get the
320 new value of the register when we wanted the old one. */
324 /* This contains any hard registers that are used in newpat; reg_dead_at_p
325 must consider all these registers to be always live. */
329 /* This is an insn to which a LOG_LINKS entry has been added. If this
330 insn is the earlier than I2 or I3, combine should rescan starting at
331 that location. */
335 /* Basic block in which we are performing combines. */
339 \f
340 /* Length of the currently allocated uid_insn_cost array. */
344 /* The following array records the insn_rtx_cost for every insn
345 in the instruction stream. */
349 /* The following array records the LOG_LINKS for every insn in the
350 instruction stream as struct insn_link pointers. */
356 };
360 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
361 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
363 #define FOR_EACH_LOG_LINK(L, INSN) \
364 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
366 /* Links for LOG_LINKS are allocated from this obstack. */
370 /* Allocate a link. */
374 {
382 }
384 /* Incremented for each basic block. */
388 /* Reset to label_tick for each extended basic block in scanning order. */
392 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
393 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
397 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
398 be safely used. It is zero while computing them and after combine has
399 completed. This former test prevents propagating values based on
400 previously set values, which can be incorrect if a variable is modified
401 in a loop. */
405 \f
406 /* Record one modification to rtl structure
407 to be undone by storing old_contents into *where. */
411 struct undo
412 {
417 };
419 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
420 num_undo says how many are currently recorded.
422 other_insn is nonzero if we have modified some other insn in the process
423 of working on subst_insn. It must be verified too. */
425 struct undobuf
426 {
430 };
434 /* Number of times the pseudo being substituted for
435 was found and replaced. */
440 machine_mode,
444 machine_mode,
516 \f
518 /* It is not safe to use ordinary gen_lowpart in combine.
519 See comments in gen_lowpart_for_combine. */
520 #undef RTL_HOOKS_GEN_LOWPART
521 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
523 /* Our implementation of gen_lowpart never emits a new pseudo. */
524 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
525 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
527 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
528 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
530 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
531 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
533 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
534 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
538 \f
539 /* Convenience wrapper for the canonicalize_comparison target hook.
540 Target hooks cannot use enum rtx_code. */
544 {
548 }
550 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
551 PATTERN can not be split. Otherwise, it returns an insn sequence.
552 This is a wrapper around split_insns which ensures that the
553 reg_stat vector is made larger if the splitter creates a new
554 register. */
558 {
567 }
569 /* This is used by find_single_use to locate an rtx in LOC that
570 contains exactly one use of DEST, which is typically either a REG
571 or CC0. It returns a pointer to the innermost rtx expression
572 containing DEST. Appearances of DEST that are being used to
573 totally replace it are not counted. */
577 {
586 {
590 CASE_CONST_ANY:
595 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
596 of a REG that occupies all of the REG, the insn uses DEST if
597 it is mentioned in the destination or the source. Otherwise, we
598 need just check the source. */
618 }
620 /* If it wasn't one of the common cases above, check each expression and
621 vector of this code. Look for a unique usage of DEST. */
625 {
627 {
632 else
638 /* Duplicate usage. */
640 }
642 {
646 {
652 else
659 }
660 }
661 }
664 }
667 /* See if DEST, produced in INSN, is used only a single time in the
668 sequel. If so, return a pointer to the innermost rtx expression in which
669 it is used.
671 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
673 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
674 care about REG_DEAD notes or LOG_LINKS.
676 Otherwise, we find the single use by finding an insn that has a
677 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
678 only referenced once in that insn, we know that it must be the first
679 and last insn referencing DEST. */
683 {
684 basic_block bb;
690 {
700 }
710 {
716 {
721 }
722 }
725 }
726 \f
727 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
728 insn. The substitution can be undone by undo_all. If INTO is already
729 set to NEWVAL, do not record this change. Because computing NEWVAL might
730 also call SUBST, we have to compute it before we put anything into
731 the undo table. */
733 static void
735 {
742 /* We'd like to catch as many invalid transformations here as
743 possible. Unfortunately, there are way too many mode changes
744 that are perfectly valid, so we'd waste too much effort for
745 little gain doing the checks here. Focus on catching invalid
746 transformations involving integer constants. */
749 {
750 /* Sanity check that we're replacing oldval with a CONST_INT
751 that is a valid sign-extension for the original mode. */
755 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
756 CONST_INT is not valid, because after the replacement, the
757 original mode would be gone. Unfortunately, we can't tell
758 when do_SUBST is called to replace the operand thereof, so we
759 perform this test on oldval instead, checking whether an
760 invalid replacement took place before we got here. */
765 }
769 else
778 }
780 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
782 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
783 for the value of a HOST_WIDE_INT value (including CONST_INT) is
784 not safe. */
786 static void
788 {
797 else
806 }
808 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
810 /* Similar to SUBST, but just substitute the mode. This is used when
811 changing the mode of a pseudo-register, so that any other
812 references to the entry in the regno_reg_rtx array will change as
813 well. */
815 static void
817 {
826 else
835 }
837 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
839 #if !HAVE_cc0
840 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
842 static void
844 {
853 else
862 }
864 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
865 #endif
866 \f
867 /* Subroutine of try_combine. Determine whether the replacement patterns
868 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
869 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
870 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
871 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
872 of all the instructions can be estimated and the replacements are more
873 expensive than the original sequence. */
875 static bool
878 {
883 /* Lookup the original insn_rtx_costs. */
888 {
891 {
895 }
896 else
897 {
901 }
902 }
903 else
904 {
907 }
909 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
910 correct that. */
915 /* Calculate the replacement insn_rtx_costs. */
918 {
922 }
923 else
924 {
927 }
930 {
936 {
939 }
940 else
942 }
944 /* Disallow this combination if both new_cost and old_cost are greater than
945 zero, and new_cost is greater than old cost. */
949 {
968 else
970 }
975 /* Update the uid_insn_cost array with the replacement costs. */
979 {
983 }
986 }
989 /* Delete any insns that copy a register to itself. */
991 static void
993 {
995 basic_block bb;
998 {
1000 {
1003 {
1008 }
1009 }
1010 }
1011 }
1013 \f
1014 /* Return false if we do not want to (or cannot) combine DEF. */
1015 static bool
1017 {
1018 /* Do not consider if it is pre/post modification in MEM. */
1024 /* Do not combine frame pointer adjustments. */
1027 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1030 #endif
1031 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1033 #endif
1034 )
1038 }
1040 /* Return false if we do not want to (or cannot) combine USE. */
1041 static bool
1043 {
1044 /* Do not consider the usage of the stack pointer by function call. */
1049 }
1051 /* Fill in log links field for all insns. */
1053 static void
1055 {
1056 basic_block bb;
1063 /* Pass through each block from the end, recording the uses of each
1064 register and establishing log links when def is encountered.
1065 Note that we do not clear next_use array in order to save time,
1066 so we have to test whether the use is in the same basic block as def.
1068 There are a few cases below when we do not consider the definition or
1069 usage -- these are taken from original flow.c did. Don't ask me why it is
1070 done this way; I don't know and if it works, I don't want to know. */
1073 {
1075 {
1079 /* Log links are created only once. */
1083 {
1099 /* flow.c claimed:
1101 We don't build a LOG_LINK for hard registers contained
1102 in ASM_OPERANDs. If these registers get replaced,
1103 we might wind up changing the semantics of the insn,
1104 even if reload can make what appear to be valid
1105 assignments later. */
1110 /* Don't add duplicate links between instructions. */
1119 }
1124 }
1125 }
1128 }
1130 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1131 true if we found a LOG_LINK that proves that A feeds B. This only works
1132 if there are no instructions between A and B which could have a link
1133 depending on A, since in that case we would not record a link for B.
1134 We also check the implicit dependency created by a cc0 setter/user
1135 pair. */
1137 static bool
1139 {
1147 }
1148 \f
1149 /* Main entry point for combiner. F is the first insn of the function.
1150 NREGS is the first unused pseudo-reg number.
1152 Return nonzero if the combiner has turned an indirect jump
1153 instruction into a direct jump. */
1154 static int
1156 {
1158 #if HAVE_cc0
1160 #endif
1163 basic_block last_bb;
1183 /* Allocate array for insn info. */
1191 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1192 problems when, for example, we have j <<= 1 in a loop. */
1197 /* Scan all SETs and see if we can deduce anything about what
1198 bits are known to be zero for some registers and how many copies
1199 of the sign bit are known to exist for those registers.
1201 Also set any known values so that we can use it while searching
1202 for what bits are known to be set. */
1205 /* Allow the entry block and the first block to fall into the same EBB.
1206 Conceptually the incoming promotions are assigned to the entry block. */
1211 {
1216 label_tick++;
1224 {
1225 #ifdef AUTO_INC_DEC
1226 rtx links;
1227 #endif
1233 insn);
1236 #ifdef AUTO_INC_DEC
1240 insn);
1241 #endif
1243 /* Record the current insn_rtx_cost of this instruction. */
1246 optimize_this_for_speed_p);
1250 }
1251 }
1255 /* Now scan all the insns in forward order. */
1263 {
1269 label_tick++;
1279 {
1293 /* See if we know about function return values before this
1294 insn based upon SUBREG flags. */
1297 /* See if we can find hardregs and subreg of pseudos in
1298 narrower modes. This could help turning TRUNCATEs
1299 into SUBREGs. */
1302 /* Try this insn with each insn it links back to. */
1308 {
1311 }
1313 /* Try each sequence of three linked insns ending with this one. */
1317 {
1320 /* If the linked insn has been replaced by a note, then there
1321 is no point in pursuing this chain any further. */
1329 {
1332 }
1333 }
1335 #if HAVE_cc0
1336 /* Try to combine a jump insn that uses CC0
1337 with a preceding insn that sets CC0, and maybe with its
1338 logical predecessor as well.
1339 This is how we make decrement-and-branch insns.
1340 We need this special code because data flow connections
1341 via CC0 do not get entered in LOG_LINKS. */
1347 {
1358 }
1360 /* Do the same for an insn that explicitly references CC0. */
1367 {
1378 }
1380 /* Finally, see if any of the insns that this insn links to
1381 explicitly references CC0. If so, try this insn, that insn,
1382 and its predecessor if it sets CC0. */
1394 #endif
1396 /* Try combining an insn with two different insns whose results it
1397 uses. */
1407 {
1410 }
1412 /* Try four-instruction combinations. */
1415 {
1419 /* If the linked insn has been replaced by a note, then there
1420 is no point in pursuing this chain any further. */
1425 {
1429 /* I0 -> I1 -> I2 -> I3. */
1435 {
1438 }
1439 /* I0, I1 -> I2, I2 -> I3. */
1446 {
1449 }
1450 }
1453 {
1457 /* I0 -> I2; I1, I2 -> I3. */
1463 {
1466 }
1467 /* I0 -> I1; I1, I2 -> I3. */
1473 {
1476 }
1477 }
1478 }
1480 /* Try this insn with each REG_EQUAL note it links back to. */
1482 {
1488 /* Avoid using a register that may already been marked
1489 dead by an earlier instruction. */
1494 {
1495 /* Temporarily replace the set's source with the
1496 contents of the REG_EQUAL note. The insn will
1497 be deleted or recognized by try_combine. */
1505 last_combined_insn);
1508 {
1511 }
1513 }
1514 }
1519 retry:
1520 ;
1521 }
1522 }
1529 /* Clean up. */
1535 {
1538 {
1541 }
1543 }
1553 /* Make recognizer allow volatile MEMs again. */
1557 }
1559 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1561 static void
1563 {
1569 }
1570 \f
1571 /* Set up any promoted values for incoming argument registers. */
1573 static void
1575 {
1576 tree arg;
1581 {
1586 /* Only continue if the incoming argument is in a register. */
1590 /* Determine, if possible, whether all call sites of the current
1591 function lie within the current compilation unit. (This does
1592 take into account the exporting of a function via taking its
1593 address, and so forth.) */
1596 /* The mode and signedness of the argument before any promotions happen
1597 (equal to the mode of the pseudo holding it at that stage). */
1601 /* The mode and signedness of the argument after any source language and
1602 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1606 /* The mode and signedness of the argument as it is actually passed,
1607 see assign_parm_setup_reg in function.c. */
1611 /* The mode of the register in which the argument is being passed. */
1614 /* Eliminate sign extensions in the callee when:
1615 (a) A mode promotion has occurred; */
1618 /* (b) The mode of the register is the same as the mode of
1619 the argument as it is passed; */
1622 /* (c) There's no language level extension; */
1624 ;
1625 /* (c.1) All callers are from the current compilation unit. If that's
1626 the case we don't have to rely on an ABI, we only have to know
1627 what we're generating right now, and we know that we will do the
1628 mode1 to mode2 promotion with the given sign. */
1631 /* (c.2) The combination of the two promotions is useful. This is
1632 true when the signs match, or if the first promotion is unsigned.
1633 In the later case, (sign_extend (zero_extend x)) is the same as
1634 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1640 /* Record that the value was promoted from mode1 to mode3,
1641 so that any sign extension at the head of the current
1642 function may be eliminated. */
1646 }
1647 }
1649 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1650 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1651 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1652 because some machines (maybe most) will actually do the sign-extension and
1653 this is the conservative approach.
1655 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1656 kludge. */
1658 static rtx
1660 {
1668 }
1669 #endif
1671 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1672 and SET. */
1674 static void
1676 rtx x)
1677 {
1686 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1690 #endif
1692 /* Don't call nonzero_bits if it cannot change anything. */
1694 {
1699 }
1701 /* Don't call num_sign_bit_copies if it cannot change anything. */
1703 {
1706 {
1710 }
1713 }
1714 }
1716 /* Called via note_stores. If X is a pseudo that is narrower than
1717 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1719 If we are setting only a portion of X and we can't figure out what
1720 portion, assume all bits will be used since we don't know what will
1721 be happening.
1723 Similarly, set how many bits of X are known to be copies of the sign bit
1724 at all locations in the function. This is the smallest number implied
1725 by any set of X. */
1727 static void
1729 {
1734 /* If this register is undefined at the start of the file, we can't
1735 say what its contents were. */
1736 && ! REGNO_REG_SET_P
1739 {
1743 {
1747 }
1749 /* If this register is being initialized using itself, and the
1750 register is uninitialized in this basic block, and there are
1751 no LOG_LINKS which set the register, then part of the
1752 register is uninitialized. In that case we can't assume
1753 anything about the number of nonzero bits.
1755 ??? We could do better if we checked this in
1756 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1757 could avoid making assumptions about the insn which initially
1758 sets the register, while still using the information in other
1759 insns. We would have to be careful to check every insn
1760 involved in the combination. */
1766 {
1773 {
1777 }
1778 }
1780 /* If this is a complex assignment, see if we can convert it into a
1781 simple assignment. */
1784 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1785 set what we know about X. */
1791 else
1792 {
1795 }
1796 }
1797 }
1798 \f
1799 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1800 optionally insns that were previously combined into I3 or that will be
1801 combined into the merger of INSN and I3. The order is PRED, PRED2,
1802 INSN, SUCC, SUCC2, I3.
1804 Return 0 if the combination is not allowed for any reason.
1806 If the combination is allowed, *PDEST will be set to the single
1807 destination of INSN and *PSRC to the single source, and this function
1808 will return 1. */
1810 static int
1814 {
1819 #ifdef AUTO_INC_DEC
1820 rtx link;
1821 #endif
1826 {
1828 {
1833 }
1838 }
1842 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1843 or a PARALLEL consisting of such a SET and CLOBBERs.
1845 If INSN has CLOBBER parallel parts, ignore them for our processing.
1846 By definition, these happen during the execution of the insn. When it
1847 is merged with another insn, all bets are off. If they are, in fact,
1848 needed and aren't also supplied in I3, they may be added by
1849 recog_for_combine. Otherwise, it won't match.
1851 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1852 note.
1854 Get the source and destination of INSN. If more than one, can't
1855 combine. */
1861 {
1863 {
1867 {
1868 /* This is important to combine floating point insns
1869 for the SH4 port. */
1871 /* Combining an isolated USE doesn't make sense.
1872 We depend here on combinable_i3pat to reject them. */
1873 /* The code below this loop only verifies that the inputs of
1874 the SET in INSN do not change. We call reg_set_between_p
1875 to verify that the REG in the USE does not change between
1876 I3 and INSN.
1877 If the USE in INSN was for a pseudo register, the matching
1878 insn pattern will likely match any register; combining this
1879 with any other USE would only be safe if we knew that the
1880 used registers have identical values, or if there was
1881 something to tell them apart, e.g. different modes. For
1882 now, we forgo such complicated tests and simply disallow
1883 combining of USES of pseudo registers with any other USE. */
1886 {
1891 do
1892 {
1902 }
1904 }
1907 /* We can ignore CLOBBERs. */
1912 /* Ignore SETs whose result isn't used but not those that
1913 have side-effects. */
1919 /* If we have already found a SET, this is a second one and
1920 so we cannot combine with this insn. */
1928 /* Anything else means we can't combine. */
1930 }
1931 }
1934 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1935 so don't do anything with it. */
1938 }
1939 else
1945 /* The simplification in expand_field_assignment may call back to
1946 get_last_value, so set safe guard here. */
1952 /* Do not eliminate user-specified register if it is in an
1953 asm input because we may break the register asm usage defined
1954 in GCC manual if allow to do so.
1955 Be aware that this may cover more cases than we expect but this
1956 should be harmless. */
1961 /* Don't eliminate a store in the stack pointer. */
1963 /* Don't combine with an insn that sets a register to itself if it has
1964 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1966 /* Can't merge an ASM_OPERANDS. */
1968 /* Can't merge a function call. */
1970 /* Don't eliminate a function call argument. */
1976 /* Don't substitute into an incremented register. */
1980 /* Don't substitute into a non-local goto, this confuses CFG. */
1982 /* Make sure that DEST is not used after SUCC but before I3. */
1983 || (!all_adjacent
1984 && ((succ2
1988 /* Make sure that the value that is to be substituted for the register
1989 does not use any registers whose values alter in between. However,
1990 If the insns are adjacent, a use can't cross a set even though we
1991 think it might (this can happen for a sequence of insns each setting
1992 the same destination; last_set of that register might point to
1993 a NOTE). If INSN has a REG_EQUIV note, the register is always
1994 equivalent to the memory so the substitution is valid even if there
1995 are intervening stores. Also, don't move a volatile asm or
1996 UNSPEC_VOLATILE across any other insns. */
1997 || (! all_adjacent
2003 /* Don't combine across a CALL_INSN, because that would possibly
2004 change whether the life span of some REGs crosses calls or not,
2005 and it is a pain to update that information.
2006 Exception: if source is a constant, moving it later can't hurt.
2007 Accept that as a special case. */
2011 /* DEST must either be a REG or CC0. */
2013 {
2014 /* If register alignment is being enforced for multi-word items in all
2015 cases except for parameters, it is possible to have a register copy
2016 insn referencing a hard register that is not allowed to contain the
2017 mode being copied and which would not be valid as an operand of most
2018 insns. Eliminate this problem by not combining with such an insn.
2020 Also, on some machines we don't want to extend the life of a hard
2021 register. */
2026 /* Don't extend the life of a hard register unless it is
2027 user variable (if we have few registers) or it can't
2028 fit into the desired register (meaning something special
2029 is going on).
2030 Also avoid substituting a return register into I3, because
2031 reload can't handle a conflict with constraints of other
2032 inputs. */
2036 }
2044 {
2047 /* If the clobber represents an earlyclobber operand, we must not
2048 substitute an expression containing the clobbered register.
2049 As we do not analyze the constraint strings here, we have to
2050 make the conservative assumption. However, if the register is
2051 a fixed hard reg, the clobber cannot represent any operand;
2052 we leave it up to the machine description to either accept or
2053 reject use-and-clobber patterns. */
2059 }
2061 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2062 or not), reject, unless nothing volatile comes between it and I3 */
2065 {
2066 /* Make sure neither succ nor succ2 contains a volatile reference. */
2071 /* We'll check insns between INSN and I3 below. */
2072 }
2074 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2075 to be an explicit register variable, and was chosen for a reason. */
2081 /* If INSN contains volatile references (specifically volatile MEMs),
2082 we cannot combine across any other volatile references.
2083 Even if INSN doesn't contain volatile references, any intervening
2084 volatile insn might affect machine state. */
2087 ? volatile_refs_p
2094 /* If INSN contains an autoincrement or autodecrement, make sure that
2095 register is not used between there and I3, and not already used in
2096 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2097 Also insist that I3 not be a jump; if it were one
2098 and the incremented register were spilled, we would lose. */
2100 #ifdef AUTO_INC_DEC
2115 #endif
2117 /* Don't combine an insn that follows a CC0-setting insn.
2118 An insn that uses CC0 must not be separated from the one that sets it.
2119 We do, however, allow I2 to follow a CC0-setting insn if that insn
2120 is passed as I1; in that case it will be deleted also.
2121 We also allow combining in this case if all the insns are adjacent
2122 because that would leave the two CC0 insns adjacent as well.
2123 It would be more logical to test whether CC0 occurs inside I1 or I2,
2124 but that would be much slower, and this ought to be equivalent. */
2127 {
2132 }
2134 /* If we get here, we have passed all the tests and the combination is
2135 to be allowed. */
2141 }
2142 \f
2143 /* LOC is the location within I3 that contains its pattern or the component
2144 of a PARALLEL of the pattern. We validate that it is valid for combining.
2146 One problem is if I3 modifies its output, as opposed to replacing it
2147 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2148 doing so would produce an insn that is not equivalent to the original insns.
2150 Consider:
2152 (set (reg:DI 101) (reg:DI 100))
2153 (set (subreg:SI (reg:DI 101) 0) <foo>)
2155 This is NOT equivalent to:
2157 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2158 (set (reg:DI 101) (reg:DI 100))])
2160 Not only does this modify 100 (in which case it might still be valid
2161 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2163 We can also run into a problem if I2 sets a register that I1
2164 uses and I1 gets directly substituted into I3 (not via I2). In that
2165 case, we would be getting the wrong value of I2DEST into I3, so we
2166 must reject the combination. This case occurs when I2 and I1 both
2167 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2168 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2169 of a SET must prevent combination from occurring. The same situation
2170 can occur for I0, in which case I0_NOT_IN_SRC is set.
2172 Before doing the above check, we first try to expand a field assignment
2173 into a set of logical operations.
2175 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2176 we place a register that is both set and used within I3. If more than one
2177 such register is detected, we fail.
2179 Return 1 if the combination is valid, zero otherwise. */
2181 static int
2184 {
2188 {
2193 rtx subdest;
2200 /* Check for the case where I3 modifies its output, as discussed
2201 above. We don't want to prevent pseudos from being combined
2202 into the address of a MEM, so only prevent the combination if
2203 i1 or i2 set the same MEM. */
2213 /* This is the same test done in can_combine_p except we can't test
2214 all_adjacent; we don't have to, since this instruction will stay
2215 in place, thus we are not considering increasing the lifetime of
2216 INNER_DEST.
2218 Also, if this insn sets a function argument, combining it with
2219 something that might need a spill could clobber a previous
2220 function argument; the all_adjacent test in can_combine_p also
2221 checks this; here, we do a more specific test for this case. */
2231 /* If DEST is used in I3, it is being killed in this insn, so
2232 record that for later. We have to consider paradoxical
2233 subregs here, since they kill the whole register, but we
2234 ignore partial subregs, STRICT_LOW_PART, etc.
2235 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2236 STACK_POINTER_REGNUM, since these are always considered to be
2237 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2247 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2249 #endif
2250 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2253 #endif
2255 {
2260 }
2261 }
2264 {
2271 }
2274 }
2275 \f
2276 /* Return 1 if X is an arithmetic expression that contains a multiplication
2277 and division. We don't count multiplications by powers of two here. */
2279 static int
2281 {
2283 {
2299 }
2300 }
2301 \f
2302 /* Determine whether INSN can be used in a combination. Return nonzero if
2303 not. This is used in try_combine to detect early some cases where we
2304 can't perform combinations. */
2306 static int
2308 {
2309 rtx set;
2312 /* If this isn't really an insn, we can't do anything.
2313 This can occur when flow deletes an insn that it has merged into an
2314 auto-increment address. */
2318 /* Never combine loads and stores involving hard regs that are likely
2319 to be spilled. The register allocator can usually handle such
2320 reg-reg moves by tying. If we allow the combiner to make
2321 substitutions of likely-spilled regs, reload might die.
2322 As an exception, we allow combinations involving fixed regs; these are
2323 not available to the register allocator so there's no risk involved. */
2344 }
2346 struct likely_spilled_retval_info
2347 {
2350 };
2352 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2353 hard registers that are known to be written to / clobbered in full. */
2354 static void
2356 {
2373 else
2376 }
2378 /* Return nonzero iff part of the return value is live during INSN, and
2379 it is likely spilled. This can happen when more than one insn is needed
2380 to copy the return value, e.g. when we consider to combine into the
2381 second copy insn for a complex value. */
2383 static int
2385 {
2387 rtx reg;
2390 /* We assume here that no machine mode needs more than
2391 32 hard registers when the value overlaps with a register
2392 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2407 /* Disregard parts of the return value that are set later. */
2416 /* Check if any of the (probably) live return value registers is
2417 likely spilled. */
2418 nregs --;
2419 do
2420 {
2426 }
2428 /* Adjust INSN after we made a change to its destination.
2430 Changing the destination can invalidate notes that say something about
2431 the results of the insn and a LOG_LINK pointing to the insn. */
2433 static void
2435 {
2436 /* For notes, be conservative and simply remove them. */
2439 /* The new insn will have a destination that was previously the destination
2440 of an insn just above it. Call distribute_links to make a LOG_LINK from
2441 the next use of that destination. */
2457 }
2459 /* Return TRUE if combine can reuse reg X in mode MODE.
2460 ADDED_SETS is nonzero if the original set is still required. */
2461 static bool
2463 {
2470 /* Allow hard registers if the new mode is legal, and occupies no more
2471 registers than the old mode. */
2476 /* Or a pseudo that is only used once. */
2479 && !added_sets
2481 }
2484 /* Check whether X, the destination of a set, refers to part of
2485 the register specified by REG. */
2487 static bool
2489 {
2490 /* Check that reg is an integer mode register. */
2501 }
2503 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2504 Note that the INSN should be deleted *after* removing dead edges, so
2505 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2506 but not for a (set (pc) (label_ref FOO)). */
2508 static void
2510 {
2518 {
2523 /* Remove barriers from the footer if there are any. */
2526 {
2529 else
2533 }
2536 }
2537 }
2539 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2540 by an arbitrary number of CLOBBERs. */
2541 static bool
2543 {
2561 }
2563 #if !HAVE_cc0
2564 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2565 CLOBBERs), can be split into individual SETs in that order, without
2566 changing semantics. */
2567 static bool
2569 {
2577 {
2586 }
2589 }
2590 #endif
2592 /* Try to combine the insns I0, I1 and I2 into I3.
2593 Here I0, I1 and I2 appear earlier than I3.
2594 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2595 I3.
2597 If we are combining more than two insns and the resulting insn is not
2598 recognized, try splitting it into two insns. If that happens, I2 and I3
2599 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2600 Otherwise, I0, I1 and I2 are pseudo-deleted.
2602 Return 0 if the combination does not work. Then nothing is changed.
2603 If we did the combination, return the insn at which combine should
2604 resume scanning.
2606 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2607 new direct jump instruction.
2609 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2610 been I3 passed to an earlier try_combine within the same basic
2611 block. */
2616 {
2617 /* New patterns for I3 and I2, respectively. */
2621 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2622 dead. */
2624 /* Total number of SETs to put into I3. */
2626 /* Nonzero if I2's or I1's body now appears in I3. */
2628 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2630 /* Contains I3 if the destination of I3 is used in its source, which means
2631 that the old life of I3 is being killed. If that usage is placed into
2632 I2 and not in I3, a REG_DEAD note must be made. */
2634 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2636 /* Copy of SET_SRC of I1 and I0, if needed. */
2638 /* Set if I2DEST was reused as a scratch register. */
2640 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2642 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2647 /* Notes that must be added to REG_NOTES in I3 and I2. */
2649 /* Notes that we substituted I3 into I2 instead of the normal case. */
2651 /* Notes that I1, I2 or I3 is a MULT operation. */
2658 rtx temp_expr;
2661 rtx new_other_notes;
2664 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2665 never be). */
2669 /* Only try four-insn combinations when there's high likelihood of
2670 success. Look for simple insns, such as loads of constants or
2671 binary operations involving a constant. */
2673 {
2683 {
2686 rtx src;
2691 {
2694 }
2696 ngood++;
2699 nshift++;
2700 }
2702 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2703 are likely manipulating its value. Ideally we'll be able to combine
2704 all four insns into a bitfield insertion of some kind.
2706 Note the source in I0 might be inside a sign/zero extension and the
2707 memory modes in I0 and I3 might be different. So extract the address
2708 from the destination of I3 and search for it in the source of I0.
2710 In the event that there's a match but the source/dest do not actually
2711 refer to the same memory, the worst that happens is we try some
2712 combinations that we wouldn't have otherwise. */
2714 /* Ensure the source of SET0 is a MEM, possibly buried inside
2715 an extension. */
2721 /* Ensure the destination of SET3 is a MEM. */
2723 /* Would it be better to extract the base address for the MEM
2724 in SET3 and look for that? I don't have cases where it matters
2725 but I could envision such cases. */
2731 }
2733 /* Exit early if one of the insns involved can't be used for
2734 combinations. */
2745 combine_attempts++;
2748 /* Reset the hard register usage information. */
2752 {
2759 else
2762 }
2764 /* If multiple insns feed into one of I2 or I3, they can be in any
2765 order. To simplify the code below, reorder them in sequence. */
2775 /* First check for one important special case that the code below will
2776 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2777 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2778 we may be able to replace that destination with the destination of I3.
2779 This occurs in the common code where we compute both a quotient and
2780 remainder into a structure, in which case we want to do the computation
2781 directly into the structure to avoid register-register copies.
2783 Note that this case handles both multiple sets in I2 and also cases
2784 where I2 has a number of CLOBBERs inside the PARALLEL.
2786 We make very conservative checks below and only try to handle the
2787 most common cases of this. For example, we only handle the case
2788 where I2 and I3 are adjacent to avoid making difficult register
2789 usage tests. */
2797 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2798 below would need to check what is inside (and reg_overlap_mentioned_p
2799 doesn't support those codes anyway). Don't allow those destinations;
2800 the resulting insn isn't likely to be recognized anyway. */
2806 {
2809 /* Make sure that the destination of I3,
2810 which we are going to substitute into one output of I2,
2811 is not used within another output of I2. We must avoid making this:
2812 (parallel [(set (mem (reg 69)) ...)
2813 (set (reg 69) ...)])
2814 which is not well-defined as to order of actions.
2815 (Besides, reload can't handle output reloads for this.)
2817 The problem can also happen if the dest of I3 is a memory ref,
2818 if another dest in I2 is an indirect memory ref. */
2826 /* Make sure this PARALLEL is not an asm. We do not allow combining
2827 that usually (see can_combine_p), so do not here either. */
2837 {
2838 combine_merges++;
2848 /* Replace the dest in I2 with our dest and make the resulting
2849 insn the new pattern for I3. Then skip to where we validate
2850 the pattern. Everything was set up above. */
2855 }
2856 }
2858 /* If I2 is setting a pseudo to a constant and I3 is setting some
2859 sub-part of it to another constant, merge them by making a new
2860 constant. */
2867 {
2873 {
2876 {
2882 }
2883 }
2884 else
2885 {
2890 }
2893 {
2894 /* If this is the low part, we're done. */
2896 ;
2897 /* Handle the case where inner is twice the size of outer. */
2901 /* Otherwise give up for now. */
2902 else
2904 }
2907 {
2911 wide_int o
2916 combine_merges++;
2923 /* Replace the source in I2 with the new constant and make the
2924 resulting insn the new pattern for I3. Then skip to where we
2925 validate the pattern. Everything was set up above. */
2931 /* The dest of I3 has been replaced with the dest of I2. */
2934 }
2935 }
2937 #if !HAVE_cc0
2938 /* If we have no I1 and I2 looks like:
2939 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2940 (set Y OP)])
2941 make up a dummy I1 that is
2942 (set Y OP)
2943 and change I2 to be
2944 (set (reg:CC X) (compare:CC Y (const_int 0)))
2946 (We can ignore any trailing CLOBBERs.)
2948 This undoes a previous combination and allows us to match a branch-and-
2949 decrement insn. */
2961 {
2962 /* We make I1 with the same INSN_UID as I2. This gives it
2963 the same DF_INSN_LUID for value tracking. Our fake I1 will
2964 never appear in the insn stream so giving it the same INSN_UID
2965 as I2 will not cause a problem. */
2978 }
2980 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2981 make those two SETs separate I1 and I2 insns, and make an I0 that is
2982 the original I1. */
2988 {
2989 /* If there is no I1, there is no I0 either. */
2992 /* We make I1 with the same INSN_UID as I2. This gives it
2993 the same DF_INSN_LUID for value tracking. Our fake I1 will
2994 never appear in the insn stream so giving it the same INSN_UID
2995 as I2 will not cause a problem. */
3003 }
3004 #endif
3006 /* Verify that I2 and I1 are valid for combining. */
3012 {
3015 }
3017 /* Record whether I2DEST is used in I2SRC and similarly for the other
3018 cases. Knowing this will help in register status updating below. */
3029 /* For the earlier insns, determine which of the subsequent ones they
3030 feed. */
3037 /* Ensure that I3's pattern can be the destination of combines. */
3043 {
3046 }
3048 /* See if any of the insns is a MULT operation. Unless one is, we will
3049 reject a combination that is, since it must be slower. Be conservative
3050 here. */
3058 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3059 We used to do this EXCEPT in one case: I3 has a post-inc in an
3060 output operand. However, that exception can give rise to insns like
3061 mov r3,(r3)+
3062 which is a famous insn on the PDP-11 where the value of r3 used as the
3063 source was model-dependent. Avoid this sort of thing. */
3065 #if 0
3071 /* It's not the exception. */
3072 #endif
3073 #ifdef AUTO_INC_DEC
3074 {
3075 rtx link;
3081 {
3084 }
3085 }
3086 #endif
3088 /* See if the SETs in I1 or I2 need to be kept around in the merged
3089 instruction: whenever the value set there is still needed past I3.
3090 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3092 For the SET in I1, we have two cases: if I1 and I2 independently feed
3093 into I3, the set in I1 needs to be kept around unless I1DEST dies
3094 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3095 in I1 needs to be kept around unless I1DEST dies or is set in either
3096 I2 or I3. The same considerations apply to I0. */
3103 else
3111 else
3114 /* We are about to copy insns for the case where they need to be kept
3115 around. Check that they can be copied in the merged instruction. */
3121 {
3124 }
3126 /* If the set in I2 needs to be kept around, we must make a copy of
3127 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3128 PATTERN (I2), we are only substituting for the original I1DEST, not into
3129 an already-substituted copy. This also prevents making self-referential
3130 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3131 I2DEST. */
3134 {
3137 else
3139 }
3142 {
3145 else
3147 }
3150 {
3153 else
3155 }
3157 combine_merges++;
3159 /* Substitute in the latest insn for the regs set by the earlier ones. */
3165 /* Many machines that don't use CC0 have insns that can both perform an
3166 arithmetic operation and set the condition code. These operations will
3167 be represented as a PARALLEL with the first element of the vector
3168 being a COMPARE of an arithmetic operation with the constant zero.
3169 The second element of the vector will set some pseudo to the result
3170 of the same arithmetic operation. If we simplify the COMPARE, we won't
3171 match such a pattern and so will generate an extra insn. Here we test
3172 for this case, where both the comparison and the operation result are
3173 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3174 I2SRC. Later we will make the PARALLEL that contains I2. */
3180 {
3181 rtx newpat_dest;
3195 {
3200 }
3202 /* Do the rest only if op1 is const0_rtx, which may be the
3203 result of simplification. */
3205 {
3206 /* If a single use of the CC is found, prepare to modify it
3207 when SELECT_CC_MODE returns a new CC-class mode, or when
3208 the above simplify_compare_const() returned a new comparison
3209 operator. undobuf.other_insn is assigned the CC use insn
3210 when modifying it. */
3212 {
3213 #ifdef SELECT_CC_MODE
3214 machine_mode new_mode
3219 {
3224 else
3225 {
3228 }
3229 }
3230 #endif
3231 /* Cases for modifying the CC-using comparison. */
3233 /* ??? Do we need to verify the zero rtx? */
3235 {
3236 /* Replace cc_use_loc with entire new RTX. */
3241 }
3243 {
3244 /* Just replace the CC reg with a new mode. */
3247 }
3248 }
3250 /* Now we modify the current newpat:
3251 First, SET_DEST(newpat) is updated if the CC mode has been
3252 altered. For targets without SELECT_CC_MODE, this should be
3253 optimized away. */
3256 /* This is always done to propagate i2src into newpat. */
3259 /* Create new version of i2pat if needed; the below PARALLEL
3260 creation needs this to work correctly. */
3264 }
3265 }
3268 {
3269 /* It is possible that the source of I2 or I1 may be performing
3270 an unneeded operation, such as a ZERO_EXTEND of something
3271 that is known to have the high part zero. Handle that case
3272 by letting subst look at the inner insns.
3274 Another way to do this would be to have a function that tries
3275 to simplify a single insn instead of merging two or more
3276 insns. We don't do this because of the potential of infinite
3277 loops and because of the potential extra memory required.
3278 However, doing it the way we are is a bit of a kludge and
3279 doesn't catch all cases.
3281 But only do this if -fexpensive-optimizations since it slows
3282 things down and doesn't usually win.
3284 This is not done in the COMPARE case above because the
3285 unmodified I2PAT is used in the PARALLEL and so a pattern
3286 with a modified I2SRC would not match. */
3289 {
3290 /* Pass pc_rtx so no substitutions are done, just
3291 simplifications. */
3293 {
3296 }
3300 }
3305 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3306 copy of I2SRC each time we substitute it, in order to avoid creating
3307 self-referential RTL when we will be substituting I1SRC for I1DEST
3308 later. Likewise if I0 feeds into I2, either directly or indirectly
3309 through I1, and I0DEST is in I0SRC. */
3316 /* Record whether I2's body now appears within I3's body. */
3318 }
3320 /* If we already got a failure, don't try to do more. Otherwise, try to
3321 substitute I1 if we have it. */
3324 {
3325 /* Check that an autoincrement side-effect on I1 has not been lost.
3326 This happens if I1DEST is mentioned in I2 and dies there, and
3327 has disappeared from the new pattern. */
3329 && i1_feeds_i2_n
3332 /* Before we can do this substitution, we must redo the test done
3333 above (see detailed comments there) that ensures I1DEST isn't
3334 mentioned in any SETs in NEWPAT that are field assignments. */
3337 {
3340 }
3345 /* If the following substitution will modify I1SRC, make a copy of it
3346 for the case where it is substituted for I1DEST in I2PAT later. */
3350 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3351 copy of I1SRC each time we substitute it, in order to avoid creating
3352 self-referential RTL when we will be substituting I0SRC for I0DEST
3353 later. */
3358 /* Record whether I1's body now appears within I3's body. */
3360 }
3362 /* Likewise for I0 if we have it. */
3365 {
3372 {
3375 }
3377 /* If the following substitution will modify I0SRC, make a copy of it
3378 for the case where it is substituted for I0DEST in I1PAT later. */
3381 /* And a copy for I0DEST in I2PAT substitution. */
3390 }
3392 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3393 to count all the ways that I2SRC and I1SRC can be used. */
3404 /* Fail if we tried to make a new register. */
3406 /* Fail if we couldn't do something and have a CLOBBER. */
3408 /* Fail if this new pattern is a MULT and we didn't have one before
3409 at the outer level. */
3412 {
3415 }
3417 /* If the actions of the earlier insns must be kept
3418 in addition to substituting them into the latest one,
3419 we must make a new PARALLEL for the latest insn
3420 to hold additional the SETs. */
3423 {
3425 combine_extras++;
3428 {
3434 }
3435 else
3436 {
3441 }
3447 {
3453 }
3455 {
3464 }
3465 }
3467 validate_replacement:
3469 /* Note which hard regs this insn has as inputs. */
3472 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3473 consider splitting this pattern, we might need these clobbers. */
3476 {
3482 }
3484 /* We have recognized nothing yet. */
3487 /* See if this is a PARALLEL of two SETs where one SET's destination is
3488 a register that is unused and this isn't marked as an instruction that
3489 might trap in an EH region. In that case, we just need the other SET.
3490 We prefer this over the PARALLEL.
3492 This can occur when simplifying a divmod insn. We *must* test for this
3493 case here because the code below that splits two independent SETs doesn't
3494 handle this case correctly when it updates the register status.
3496 It's pointless doing this if we originally had two sets, one from
3497 i3, and one from i2. Combining then splitting the parallel results
3498 in the original i2 again plus an invalid insn (which we delete).
3499 The net effect is only to move instructions around, which makes
3500 debug info less accurate. */
3505 {
3516 {
3519 }
3528 {
3534 }
3538 }
3540 /* Is the result of combination a valid instruction? */
3544 /* If we were combining three insns and the result is a simple SET
3545 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3546 insns. There are two ways to do this. It can be split using a
3547 machine-specific method (like when you have an addition of a large
3548 constant) or by combine in the function find_split_point. */
3552 {
3556 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3557 use I2DEST as a scratch register will help. In the latter case,
3558 convert I2DEST to the mode of the source of NEWPAT if we can. */
3562 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3563 inputs of NEWPAT. */
3565 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3566 possible to try that as a scratch reg. This would require adding
3567 more code to make it work though. */
3570 {
3573 /* First try to split using the original register as a
3574 scratch register. */
3578 i2dest)));
3581 /* If that didn't work, try changing the mode of I2DEST if
3582 we can. */
3587 {
3589 rtx ni2dest;
3593 else
3594 {
3597 }
3599 parallel = (gen_rtx_PARALLEL
3603 ni2dest))));
3608 {
3616 }
3617 }
3620 }
3622 /* If recog_for_combine has discarded clobbers, try to use them
3623 again for the split. */
3625 {
3628 }
3631 {
3636 }
3640 {
3650 /* If I2 or I3 has multiple SETs, we won't know how to track
3651 register status, so don't use these insns. If I2's destination
3652 is used between I2 and I3, we also can't use these insns. */
3662 /* It is possible that both insns now set the destination of I3.
3663 If so, we must show an extra use of it. */
3666 {
3685 }
3686 }
3688 /* If we can split it and use I2DEST, go ahead and see if that
3689 helps things be recognized. Verify that none of the registers
3690 are set between I2 and I3. */
3694 /* We need I2DEST in the proper mode. If it is a hard register
3695 or the only use of a pseudo, we can change its mode.
3696 Make sure we don't change a hard register to have a mode that
3697 isn't valid for it, or change the number of registers. */
3704 /* We can't overwrite I2DEST if its value is still used by
3705 NEWPAT. */
3707 {
3716 /* *SPLIT may be part of I2SRC, so make sure we have the
3717 original expression around for later debug processing.
3718 We should not need I2SRC any more in other cases. */
3721 else
3724 /* Get NEWDEST as a register in the proper mode. We have already
3725 validated that we can do this. */
3727 {
3730 else
3731 {
3734 }
3735 }
3737 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3738 an ASHIFT. This can occur if it was inside a PLUS and hence
3739 appeared to be a memory address. This is a kludge. */
3744 {
3747 /* Update split_code because we may not have a multiply
3748 anymore. */
3750 }
3752 #ifdef INSN_SCHEDULING
3753 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3754 be written as a ZERO_EXTEND. */
3756 {
3757 #ifdef LOAD_EXTEND_OP
3758 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3759 what it really is. */
3764 else
3765 #endif
3768 }
3769 #endif
3771 /* Attempt to split binary operators using arithmetic identities. */
3775 {
3782 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3784 {
3789 }
3790 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3797 {
3803 /* Split both "((X op Y) op X) op Y" and
3804 "((X op Y) op Y) op X" as "T op T" where T is
3805 "X op Y". */
3808 {
3813 }
3814 /* Split "((X op X) op Y) op Y)" as "T op T" where
3815 T is "X op Y". */
3817 {
3823 }
3824 }
3825 }
3828 {
3831 }
3835 /* recog_for_combine might have added CLOBBERs to newi2pat.
3836 Make sure NEWPAT does not depend on the clobbered regs. */
3840 {
3843 {
3846 }
3847 }
3849 /* If the split point was a MULT and we didn't have one before,
3850 don't use one now. */
3853 }
3854 }
3856 /* Check for a case where we loaded from memory in a narrow mode and
3857 then sign extended it, but we need both registers. In that case,
3858 we have a PARALLEL with both loads from the same memory location.
3859 We can split this into a load from memory followed by a register-register
3860 copy. This saves at least one insn, more if register allocation can
3861 eliminate the copy.
3863 We cannot do this if the destination of the first assignment is a
3864 condition code register or cc0. We eliminate this case by making sure
3865 the SET_DEST and SET_SRC have the same mode.
3867 We cannot do this if the destination of the second assignment is
3868 a register that we have already assumed is zero-extended. Similarly
3869 for a SUBREG of such a register. */
3904 {
3905 rtx ni2dest;
3919 }
3921 /* Similarly, check for a case where we have a PARALLEL of two independent
3922 SETs but we started with three insns. In this case, we can do the sets
3923 as two separate insns. This case occurs when some SET allows two
3924 other insns to combine, but the destination of that SET is still live.
3926 Also do this if we started with two insns and (at least) one of the
3927 resulting sets is a noop; this noop will be deleted later. */
3946 {
3950 /* Normally, it doesn't matter which of the two is done first,
3951 but the one that references cc0 can't be the second, and
3952 one which uses any regs/memory set in between i2 and i3 can't
3953 be first. The PARALLEL might also have been pre-existing in i3,
3954 so we need to make sure that we won't wrongly hoist a SET to i2
3955 that would conflict with a death note present in there. */
3963 /* If I3 is a jump, ensure that set0 is a jump so that
3964 we do not create invalid RTL. */
3966 )
3967 {
3970 }
3978 /* If I3 is a jump, ensure that set1 is a jump so that
3979 we do not create invalid RTL. */
3981 )
3982 {
3985 }
3986 else
3987 {
3990 }
3995 {
3996 /* recog_for_combine might have added CLOBBERs to newi2pat.
3997 Make sure NEWPAT does not depend on the clobbered regs. */
3999 {
4002 {
4005 {
4008 }
4009 }
4010 }
4013 }
4014 }
4016 /* If it still isn't recognized, fail and change things back the way they
4017 were. */
4019 /* Is the result a reasonable ASM_OPERANDS? */
4021 {
4024 }
4026 /* If we had to change another insn, make sure it is valid also. */
4028 {
4036 {
4039 }
4040 }
4042 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4043 they are adjacent to each other or not. */
4045 {
4049 {
4052 }
4053 }
4055 /* Only allow this combination if insn_rtx_costs reports that the
4056 replacement instructions are cheaper than the originals. */
4058 {
4061 }
4064 {
4069 {
4074 /* Temporarily revert mode back. */
4078 {
4079 /* If we used i2dest as a scratch register with a
4080 different mode, substitute it for the original
4081 i2src while its original mode is temporarily
4082 restored, and then clear i2scratch so that we don't
4083 do it again later. */
4085 this_basic_block);
4087 /* Put back the new mode. */
4089 }
4090 else
4091 {
4096 {
4099 }
4100 else
4101 {
4108 }
4110 /* We're dealing with a reg that changed mode but not
4111 meaning, so we want to turn it into a subreg for
4112 the new mode. However, because of REG sharing and
4113 because its mode had already changed, we have to do
4114 it in two steps. First, replace any debug uses of
4115 reg, with its original mode temporarily restored,
4116 with this copy we have created; then, replace the
4117 copy with the SUBREG of the original shared reg,
4118 once again changed to the new mode. */
4120 this_basic_block);
4124 this_basic_block);
4125 }
4126 }
4127 }
4129 /* If we will be able to accept this, we have made a
4130 change to the destination of I3. This requires us to
4131 do a few adjustments. */
4134 {
4137 }
4139 /* We now know that we can do this combination. Merge the insns and
4140 update the status of registers and LOG_LINKS. */
4143 {
4148 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4149 ensure that they are still valid. Then add any non-duplicate
4150 notes added by recog_for_combine. */
4152 {
4162 }
4166 NULL_RTX);
4167 }
4170 {
4173 rtx ni2dest;
4175 /* I3 now uses what used to be its destination and which is now
4176 I2's destination. This requires us to do a few adjustments. */
4180 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4181 so we still will.
4183 However, some later insn might be using I2's dest and have
4184 a LOG_LINK pointing at I3. We must remove this link.
4185 The simplest way to remove the link is to point it at I1,
4186 which we know will be a NOTE. */
4188 /* newi2pat is usually a SET here; however, recog_for_combine might
4189 have added some clobbers. */
4192 else
4199 {
4201 {
4207 }
4208 }
4209 }
4211 {
4216 /* Compute which registers we expect to eliminate. newi2pat may be setting
4217 either i3dest or i2dest, so we must check it. */
4220 || !i2dest_killed
4222 /* For i1, we need to compute both local elimination and global
4223 elimination information with respect to newi2pat because i1dest
4224 may be the same as i3dest, in which case newi2pat may be setting
4225 i1dest. Global information is used when distributing REG_DEAD
4226 note for i2 and i3, in which case it does matter if newi2pat sets
4227 i1dest or not.
4229 Local information is used when distributing REG_DEAD note for i1,
4230 in which case it doesn't matter if newi2pat sets i1dest or not.
4231 See PR62151, if we have four insns combination:
4232 i0: r0 <- i0src
4233 i1: r1 <- i1src (using r0)
4234 REG_DEAD (r0)
4235 i2: r0 <- i2src (using r1)
4236 i3: r3 <- i3src (using r0)
4237 ix: using r0
4238 From i1's point of view, r0 is eliminated, no matter if it is set
4239 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4240 should be discarded.
4242 Note local information only affects cases in forms like "I1->I2->I3",
4243 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4244 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4245 i0dest anyway. */
4247 || !i1dest_killed
4252 /* Same case as i1. */
4259 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4260 clear them. */
4268 /* Ensure that we do not have something that should not be shared but
4269 occurs multiple times in the new insns. Check this by first
4270 resetting all the `used' flags and then copying anything is shared. */
4294 {
4301 {
4302 /* I2SRC must still be meaningful at this point. Some splitting
4303 operations can invalidate I2SRC, but those operations do not
4304 apply to calls. */
4307 }
4315 }
4320 /* We had one special case above where I2 had more than one set and
4321 we replaced a destination of one of those sets with the destination
4322 of I3. In that case, we have to update LOG_LINKS of insns later
4323 in this basic block. Note that this (expensive) case is rare.
4325 Also, in this case, we must pretend that all REG_NOTEs for I2
4326 actually came from I3, so that REG_UNUSED notes from I2 will be
4327 properly handled. */
4330 {
4339 temp_insn
4349 {
4354 }
4355 else
4358 }
4366 {
4369 this_basic_block);
4372 }
4373 else
4374 {
4377 this_basic_block);
4379 }
4382 {
4387 this_basic_block);
4389 }
4392 {
4397 this_basic_block);
4399 }
4401 /* Get death notes for everything that is now used in either I3 or
4402 I2 and used to die in a previous insn. If we built two new
4403 patterns, move from I1 to I2 then I2 to I3 so that we get the
4404 proper movement on registers that I2 modifies. */
4410 else
4416 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4433 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4434 know these are REG_UNUSED and want them to go to the desired insn,
4435 so we always pass it as i3. */
4439 NULL_RTX);
4443 NULL_RTX);
4445 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4446 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4447 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4448 in that case, it might delete I2. Similarly for I2 and I1.
4449 Show an additional death due to the REG_DEAD note we make here. If
4450 we discard it in distribute_notes, we will decrement it again. */
4453 {
4458 else
4461 }
4464 {
4469 else
4472 }
4475 {
4480 else
4483 }
4486 {
4491 else
4494 }
4502 {
4507 /* The insn that used to set this register doesn't exist, and
4508 this life of the register may not exist either. See if one of
4509 I3's links points to an insn that sets I2DEST. If it does,
4510 that is now the last known value for I2DEST. If we don't update
4511 this and I2 set the register to a value that depended on its old
4512 contents, we will get confused. If this insn is used, thing
4513 will be set correctly in combine_instructions. */
4521 /* If the reg formerly set in I2 died only once and that was in I3,
4522 zero its use count so it won't make `reload' do any work. */
4525 && ! i2dest_in_i2src
4528 }
4531 {
4544 && ! i1dest_in_i1src
4547 }
4550 {
4563 && ! i0dest_in_i0src
4566 }
4568 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4569 been made to this insn. The order is important, because newi2pat
4570 can affect nonzero_bits of newpat. */
4574 }
4577 {
4579 {
4582 }
4584 }
4587 {
4589 {
4592 }
4594 }
4597 {
4599 {
4602 }
4604 }
4607 {
4609 {
4612 }
4614 }
4617 {
4619 {
4622 }
4624 }
4626 /* Set new_direct_jump_p if a new return or simple jump instruction
4627 has been created. Adjust the CFG accordingly. */
4629 {
4633 }
4638 {
4641 }
4643 /* A noop might also need cleaning up of CFG, if it comes from the
4644 simplification of a jump. */
4649 {
4652 }
4659 {
4662 }
4664 combine_successes++;
4671 else
4673 }
4674 \f
4675 /* Get a marker for undoing to the current state. */
4679 {
4681 }
4683 /* Undo the modifications up to the marker. */
4685 static void
4687 {
4691 {
4696 {
4711 }
4715 }
4718 }
4720 /* Undo all the modifications recorded in undobuf. */
4722 static void
4724 {
4726 }
4728 /* We've committed to accepting the changes we made. Move all
4729 of the undos to the free list. */
4731 static void
4733 {
4737 {
4741 }
4743 }
4744 \f
4745 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4746 where we have an arithmetic expression and return that point. LOC will
4747 be inside INSN.
4749 try_combine will call this function to see if an insn can be split into
4750 two insns. */
4754 {
4763 /* First special-case some codes. */
4765 {
4767 #ifdef INSN_SCHEDULING
4768 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4769 point. */
4772 #endif
4776 #ifdef HAVE_lo_sum
4777 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4778 using LO_SUM and HIGH. */
4781 {
4789 }
4790 #endif
4792 /* If we have a PLUS whose second operand is a constant and the
4793 address is not valid, perhaps will can split it up using
4794 the machine-specific way to split large constants. We use
4795 the first pseudo-reg (one of the virtual regs) as a placeholder;
4796 it will not remain in the result. */
4801 {
4804 subst_insn);
4806 /* This should have produced two insns, each of which sets our
4807 placeholder. If the source of the second is a valid address,
4808 we can make put both sources together and make a split point
4809 in the middle. */
4822 && memory_address_addr_space_p
4825 {
4829 /* Replace the placeholder in SRC2 with SRC1. If we can
4830 find where in SRC2 it was placed, that can become our
4831 split point and we can replace this address with SRC2.
4832 Just try two obvious places. */
4843 {
4846 }
4847 }
4849 /* If that didn't work, perhaps the first operand is complex and
4850 needs to be computed separately, so make a split point there.
4851 This will occur on machines that just support REG + CONST
4852 and have a constant moved through some previous computation. */
4858 }
4860 /* If we have a PLUS whose first operand is complex, try computing it
4861 separately by making a split there. */
4872 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4873 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4874 we need to put the operand into a register. So split at that
4875 point. */
4885 /* See if we can split SET_SRC as it stands. */
4890 /* See if we can split SET_DEST as it stands. */
4895 /* See if this is a bitfield assignment with everything constant. If
4896 so, this is an IOR of an AND, so split it into that. */
4906 {
4912 unsigned HOST_WIDE_INT mask
4914 rtx or_mask;
4923 else
4924 {
4930 or_mask));
4931 }
4938 }
4940 /* Otherwise, see if this is an operation that we can split into two.
4941 If so, try to split that. */
4945 {
4947 /* If we are AND'ing with a large constant that is only a single
4948 bit and the result is only being used in a context where we
4949 need to know if it is zero or nonzero, replace it with a bit
4950 extraction. This will avoid the large constant, which might
4951 have taken more than one insn to make. If the constant were
4952 not a valid argument to the AND but took only one insn to make,
4953 this is no worse, but if it took more than one insn, it will
4954 be better. */
4964 {
4969 {
4972 }
4973 }
4977 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4978 is known to be on, this can be converted into a NEG of a shift. */
4984 {
4996 }
5002 /* We can't optimize if either mode is a partial integer
5003 mode as we don't know how many bits are significant
5004 in those modes. */
5018 {
5026 }
5031 }
5035 {
5038 /* For unsigned, we have a choice of a shift followed by an
5039 AND or two shifts. Use two shifts for field sizes where the
5040 constant might be too large. We assume here that we can
5041 always at least get 8-bit constants in an AND insn, which is
5042 true for every current RISC. */
5045 {
5046 unsigned HOST_WIDE_INT mask
5050 gen_rtx_LSHIFTRT
5058 }
5059 else
5060 {
5062 gen_rtx_fmt_ee
5073 }
5074 }
5076 /* See if this is a simple operation with a constant as the second
5077 operand. It might be that this constant is out of range and hence
5078 could be used as a split point. */
5086 /* Finally, see if this is a simple operation with its first operand
5087 not in a register. The operation might require this operand in a
5088 register, so return it as a split point. We can always do this
5089 because if the first operand were another operation, we would have
5090 already found it as a split point. */
5099 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5100 it is better to write this as (not (ior A B)) so we can split it.
5101 Similarly for IOR. */
5103 {
5111 }
5113 /* Many RISC machines have a large set of logical insns. If the
5114 second operand is a NOT, put it first so we will try to split the
5115 other operand first. */
5117 {
5121 }
5126 /* Canonicalization can produce (minus A (mult B C)), where C is a
5127 constant. It may be better to try splitting (plus (mult B -C) A)
5128 instead if this isn't a multiply by a power of two. */
5132 {
5140 mode)),
5143 }
5145 /* Split at a multiply-accumulate instruction. However if this is
5146 the SET_SRC, we likely do not have such an instruction and it's
5147 worthless to try this split. */
5153 }
5155 /* Otherwise, select our actions depending on our rtx class. */
5157 {
5163 /* ... fall through ... */
5171 /* ... fall through ... */
5173 /* Some machines have (and (shift ...) ...) insns. If X is not
5174 an AND, but XEXP (X, 0) is, use it as our split point. */
5184 /* Otherwise, we don't have a split point. */
5186 }
5187 }
5188 \f
5189 /* Throughout X, replace FROM with TO, and return the result.
5190 The result is TO if X is FROM;
5191 otherwise the result is X, but its contents may have been modified.
5192 If they were modified, a record was made in undobuf so that
5193 undo_all will (among other things) return X to its original state.
5195 If the number of changes necessary is too much to record to undo,
5196 the excess changes are not made, so the result is invalid.
5197 The changes already made can still be undone.
5198 undobuf.num_undo is incremented for such changes, so by testing that
5199 the caller can tell whether the result is valid.
5201 `n_occurrences' is incremented each time FROM is replaced.
5203 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5205 IN_COND is nonzero if we are at the top level of a condition.
5207 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5208 by copying if `n_occurrences' is nonzero. */
5210 static rtx
5212 {
5217 rtx new_rtx;
5219 /* Two expressions are equal if they are identical copies of a shared
5220 RTX or if they are both registers with the same register number
5221 and mode. */
5223 #define COMBINE_RTX_EQUAL_P(X,Y) \
5224 ((X) == (Y) \
5225 || (REG_P (X) && REG_P (Y) \
5226 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5228 /* Do not substitute into clobbers of regs -- this will never result in
5229 valid RTL. */
5234 {
5235 n_occurrences++;
5237 }
5239 /* If X and FROM are the same register but different modes, they
5240 will not have been seen as equal above. However, the log links code
5241 will make a LOG_LINKS entry for that case. If we do nothing, we
5242 will try to rerecognize our original insn and, when it succeeds,
5243 we will delete the feeding insn, which is incorrect.
5245 So force this insn not to match in this (rare) case. */
5250 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5251 of which may contain things that can be combined. */
5255 /* It is possible to have a subexpression appear twice in the insn.
5256 Suppose that FROM is a register that appears within TO.
5257 Then, after that subexpression has been scanned once by `subst',
5258 the second time it is scanned, TO may be found. If we were
5259 to scan TO here, we would find FROM within it and create a
5260 self-referent rtl structure which is completely wrong. */
5264 /* Parallel asm_operands need special attention because all of the
5265 inputs are shared across the arms. Furthermore, unsharing the
5266 rtl results in recognition failures. Failure to handle this case
5267 specially can result in circular rtl.
5269 Solve this by doing a normal pass across the first entry of the
5270 parallel, and only processing the SET_DESTs of the subsequent
5271 entries. Ug. */
5276 {
5279 /* If this substitution failed, this whole thing fails. */
5287 {
5293 {
5296 /* If this substitution failed, this whole thing fails. */
5302 }
5303 }
5304 }
5305 else
5306 {
5310 /* We don't need to process a SET_DEST that is a register, CC0,
5311 or PC, so set up to skip this common case. All other cases
5312 where we want to suppress replacing something inside a
5313 SET_SRC are handled via the IN_DEST operand. */
5320 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5321 constant. */
5326 {
5328 {
5331 {
5333 {
5336 n_occurrences++;
5337 }
5338 else
5339 {
5341 unique_copy);
5343 /* If this substitution failed, this whole thing
5344 fails. */
5348 }
5351 }
5352 }
5354 {
5355 /* If this is a register being set, ignore it. */
5362 ;
5365 {
5366 /* In general, don't install a subreg involving two
5367 modes not tieable. It can worsen register
5368 allocation, and can even make invalid reload
5369 insns, since the reg inside may need to be copied
5370 from in the outside mode, and that may be invalid
5371 if it is an fp reg copied in integer mode.
5373 We allow two exceptions to this: It is valid if
5374 it is inside another SUBREG and the mode of that
5375 SUBREG and the mode of the inside of TO is
5376 tieable and it is valid if X is a SET that copies
5377 FROM to CC0. */
5385 #if HAVE_cc0
5387 #endif
5388 )
5400 n_occurrences++;
5401 }
5402 else
5403 /* If we are in a SET_DEST, suppress most cases unless we
5404 have gone inside a MEM, in which case we want to
5405 simplify the address. We assume here that things that
5406 are actually part of the destination have their inner
5407 parts in the first expression. This is true for SUBREG,
5408 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5409 things aside from REG and MEM that should appear in a
5410 SET_DEST. */
5412 (((in_dest
5418 unique_copy);
5420 /* If we found that we will have to reject this combination,
5421 indicate that by returning the CLOBBER ourselves, rather than
5422 an expression containing it. This will speed things up as
5423 well as prevent accidents where two CLOBBERs are considered
5424 to be equal, thus producing an incorrect simplification. */
5430 {
5438 }
5441 {
5445 }
5446 else
5448 }
5449 }
5450 }
5452 /* Check if we are loading something from the constant pool via float
5453 extension; in this case we would undo compress_float_constant
5454 optimization and degenerate constant load to an immediate value. */
5458 {
5462 }
5464 /* Try to simplify X. If the simplification changed the code, it is likely
5465 that further simplification will help, so loop, but limit the number
5466 of repetitions that will be performed. */
5469 {
5470 /* If X is sufficiently simple, don't bother trying to do anything
5471 with it. */
5480 /* We no longer know the original mode of operand 0 since we
5481 have changed the form of X) */
5483 }
5486 }
5487 \f
5488 /* Simplify X, a piece of RTL. We just operate on the expression at the
5489 outer level; call `subst' to simplify recursively. Return the new
5490 expression.
5492 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5493 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5494 of a condition. */
5496 static rtx
5499 {
5502 rtx temp;
5505 /* If this is a commutative operation, put a constant last and a complex
5506 expression first. We don't need to do this for comparisons here. */
5509 {
5513 }
5515 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5516 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5517 things. Check for cases where both arms are testing the same
5518 condition.
5520 Don't do anything if all operands are very simple. */
5533 {
5538 /* If everything is a comparison, what we have is highly unlikely
5539 to be simpler, so don't use it. */
5542 {
5549 /* Simplify the alternative arms; this may collapse the true and
5550 false arms to store-flag values. Be careful to use copy_rtx
5551 here since true_rtx or false_rtx might share RTL with x as a
5552 result of the if_then_else_cond call above. */
5556 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5557 is unlikely to be simpler. */
5560 {
5563 /* Restarting if we generate a store-flag expression will cause
5564 us to loop. Just drop through in this case. */
5566 /* If the result values are STORE_FLAG_VALUE and zero, we can
5567 just make the comparison operation. */
5578 /* Likewise, we can make the negate of a comparison operation
5579 if the result values are - STORE_FLAG_VALUE and zero. */
5587 mode);
5598 mode);
5599 else
5602 mode,
5603 VOIDmode,
5604 cond,
5605 cop1),
5610 }
5611 }
5612 }
5614 /* Try to fold this expression in case we have constants that weren't
5615 present before. */
5618 {
5626 {
5629 {
5633 }
5636 }
5649 }
5652 {
5657 }
5659 /* First see if we can apply the inverse distributive law. */
5662 {
5666 }
5668 /* If CODE is an associative operation not otherwise handled, see if we
5669 can associate some operands. This can win if they are constants or
5670 if they are logically related (i.e. (a & b) & a). */
5676 {
5678 {
5682 rtx inner;
5684 /* Make sure we pass the constant operand if any as the second
5685 one if this is a commutative operation. */
5687 {
5691 }
5697 /* For commutative operations, try the other pair if that one
5698 didn't simplify. */
5700 {
5705 }
5709 }
5710 }
5712 /* A little bit of algebraic simplification here. */
5714 {
5716 /* Ensure that our address has any ASHIFTs converted to MULT in case
5717 address-recognizing predicates are called later. */
5726 /* See if this can be moved to simplify_subreg. */
5729 /* Don't call gen_lowpart if the inner mode
5730 is VOIDmode and we cannot simplify it, as SUBREG without
5731 inner mode is invalid. */
5738 {
5739 rtx temp;
5745 /* If op is known to have all lower bits zero, the result is zero. */
5755 }
5757 /* Don't change the mode of the MEM if that would change the meaning
5758 of the address. */
5765 /* Note that we cannot do any narrowing for non-constants since
5766 we might have been counting on using the fact that some bits were
5767 zero. We now do this in the SET. */
5774 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5775 replaced by (lshiftrt X C). This will convert
5776 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5784 /* If X has only a single bit that might be nonzero, say, bit I, convert
5785 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5786 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5787 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5788 or a SUBREG of one since we'd be making the expression more
5789 complex if it was just a register. */
5795 {
5796 rtx temp1 = simplify_shift_const
5802 /* If all we did was surround TEMP with the two shifts, we
5803 haven't improved anything, so don't use it. Otherwise,
5804 we are better off with TEMP1. */
5809 }
5813 /* We can't handle truncation to a partial integer mode here
5814 because we don't know the real bitsize of the partial
5815 integer mode. */
5824 /* We can truncate a constant value and return it. */
5828 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5829 whose value is a comparison can be replaced with a subreg if
5830 STORE_FLAG_VALUE permits. */
5839 /* (const (const X)) can become (const X). Do it this way rather than
5840 returning the inner CONST since CONST can be shared with a
5841 REG_EQUAL note. */
5846 #ifdef HAVE_lo_sum
5848 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5849 can add in an offset. find_split_point will split this address up
5850 again if it doesn't match. */
5855 #endif
5858 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5859 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5860 bit-field and can be replaced by either a sign_extend or a
5861 sign_extract. The `and' may be a zero_extend and the two
5862 <c>, -<c> constants may be reversed. */
5877 return simplify_shift_const
5884 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5885 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5886 the bitsize of the mode - 1. This allows simplification of
5887 "a = (b & 8) == 0;" */
5899 /* If we are adding two things that have no bits in common, convert
5900 the addition into an IOR. This will often be further simplified,
5901 for example in cases like ((a & 1) + (a & 2)), which can
5902 become a & 3. */
5907 {
5908 /* Try to simplify the expression further. */
5912 /* If we could, great. If not, do not go ahead with the IOR
5913 replacement, since PLUS appears in many special purpose
5914 address arithmetic instructions. */
5922 }
5926 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5927 (and <foo> (const_int pow2-1)) */
5937 /* If we have (mult (plus A B) C), apply the distributive law and then
5938 the inverse distributive law to see if things simplify. This
5939 occurs mostly in addresses, often when unrolling loops. */
5942 {
5946 }
5948 /* Try simplify a*(b/c) as (a*b)/c. */
5951 {
5957 }
5961 /* If this is a divide by a power of two, treat it as a shift if
5962 its first operand is a shift. */
5980 /* If the first operand is a condition code, we can't do anything
5981 with it. */
5985 {
5993 /* Simplify our comparison, if possible. */
5996 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5997 if only the low-order bit is possibly nonzero in X (such as when
5998 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5999 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6000 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6001 (plus X 1).
6003 Remove any ZERO_EXTRACT we made when thinking this was a
6004 comparison. It may now be simpler to use, e.g., an AND. If a
6005 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6006 the call to make_compound_operation in the SET case.
6008 Don't apply these optimizations if the caller would
6009 prefer a comparison rather than a value.
6010 E.g., for the condition in an IF_THEN_ELSE most targets need
6011 an explicit comparison. */
6014 ;
6030 {
6034 mode);
6035 }
6042 {
6046 const1_rtx);
6047 }
6055 {
6058 }
6060 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6061 those above. */
6063 ;
6079 {
6083 mode);
6084 }
6092 {
6096 mode);
6097 }
6099 /* If X is 0/1, (eq X 0) is X-1. */
6105 {
6108 }
6110 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6111 one bit that might be nonzero, we can convert (ne x 0) to
6112 (ashift x c) where C puts the bit in the sign bit. Remove any
6113 AND with STORE_FLAG_VALUE when we are done, since we are only
6114 going to test the sign bit. */
6121 {
6127 else
6129 }
6131 /* If the code changed, return a whole new comparison.
6132 We also need to avoid using SUBST in cases where
6133 simplify_comparison has widened a comparison with a CONST_INT,
6134 since in that case the wider CONST_INT may fail the sanity
6135 checks in do_SUBST. */
6142 /* Otherwise, keep this operation, but maybe change its operands.
6143 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6146 }
6156 /* If we are processing SET_DEST, we are done. */
6174 /* If this is a shift by a constant amount, simplify it. */
6190 }
6193 }
6194 \f
6195 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6197 static rtx
6199 {
6206 rtx temp;
6209 rtx reversed;
6211 /* Simplify storing of the truth value. */
6216 /* Also when the truth value has to be reversed. */
6222 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6223 in it is being compared against certain values. Get the true and false
6224 comparisons and see if that says anything about the value of each arm. */
6230 {
6231 HOST_WIDE_INT nzb;
6237 /* If FALSE_CODE is EQ, swap the codes and arms. */
6240 {
6243 }
6245 /* If we are comparing against zero and the expression being tested has
6246 only a single bit that might be nonzero, that is its value when it is
6247 not equal to zero. Similarly if it is known to be -1 or 0. */
6251 {
6254 }
6258 {
6261 }
6263 /* Now simplify an arm if we know the value of the register in the
6264 branch and it is used in the arm. Be careful due to the potential
6265 of locally-shared RTL. */
6282 }
6284 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6285 reversed, do so to avoid needing two sets of patterns for
6286 subtract-and-branch insns. Similarly if we have a constant in the true
6287 arm, the false arm is the same as the first operand of the comparison, or
6288 the false arm is more complicated than the true arm. */
6301 {
6310 /* It is possible that the conditional has been simplified out. */
6313 }
6315 /* If the two arms are identical, we don't need the comparison. */
6320 /* Convert a == b ? b : a to "a". */
6332 /* Look for cases where we have (abs x) or (neg (abs X)). */
6335 && comparison_p
6342 {
6348 return
6351 mode);
6354 }
6356 /* Look for MIN or MAX. */
6359 && comparison_p
6364 {
6379 }
6381 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6382 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6383 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6384 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6385 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6386 neither 1 or -1, but it isn't worth checking for. */
6389 && comparison_p
6392 {
6408 /* If an identity-zero op is commutative, check whether there
6409 would be a match if we swapped the operands. */
6429 {
6433 }
6445 {
6449 }
6465 {
6469 }
6481 {
6485 }
6488 {
6494 const_true_rtx));
6502 }
6503 }
6505 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6506 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6507 negation of a single bit, we can convert this operation to a shift. We
6508 can actually do this more generally, but it doesn't seem worth it. */
6517 return
6521 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6531 }
6532 \f
6533 /* Simplify X, a SET expression. Return the new expression. */
6535 static rtx
6537 {
6540 machine_mode mode
6545 /* (set (pc) (return)) gets written as (return). */
6549 /* Now that we know for sure which bits of SRC we are using, see if we can
6550 simplify the expression for the object knowing that we only need the
6551 low-order bits. */
6554 {
6557 }
6559 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6560 the comparison result and try to simplify it unless we already have used
6561 undobuf.other_insn. */
6569 {
6578 {
6581 {
6584 }
6585 }
6586 else
6594 {
6598 }
6599 else
6600 {
6605 /* Attempt to simplify CC user. */
6607 {
6611 }
6613 /* Convert X into a no-op move. */
6617 }
6619 /* Simplify our comparison, if possible. */
6622 #ifdef SELECT_CC_MODE
6623 /* If this machine has CC modes other than CCmode, check to see if we
6624 need to use a different CC mode here. */
6633 else
6636 /* If the mode changed, we have to change SET_DEST, the mode in the
6637 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6638 a hard register, just build new versions with the proper mode. If it
6639 is a pseudo, we lose unless it is only time we set the pseudo, in
6640 which case we can safely change its mode. */
6642 {
6644 {
6646 rtx new_dest;
6650 else
6651 {
6654 }
6661 }
6662 }
6665 /* If the code changed, we have to build a new comparison in
6666 undobuf.other_insn. */
6668 {
6677 /* If the only change we made was to change an EQ into an NE or
6678 vice versa, OP0 has only one bit that might be nonzero, and OP1
6679 is zero, check if changing the user of the condition code will
6680 produce a valid insn. If it won't, we can keep the original code
6681 in that insn by surrounding our operation with an XOR. */
6688 {
6693 {
6700 }
6701 }
6702 }
6707 /* Don't generate a compare of a CC with 0, just use that CC. */
6709 {
6712 }
6713 /* Otherwise, if we didn't previously have the same COMPARE we
6714 want, create it from scratch. */
6717 {
6720 }
6721 }
6722 else
6723 {
6724 /* Get SET_SRC in a form where we have placed back any
6725 compound expressions. Then do the checks below. */
6728 }
6730 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6731 and X being a REG or (subreg (reg)), we may be able to convert this to
6732 (set (subreg:m2 x) (op)).
6734 We can always do this if M1 is narrower than M2 because that means that
6735 we only care about the low bits of the result.
6737 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6738 perform a narrower operation than requested since the high-order bits will
6739 be undefined. On machine where it is defined, this transformation is safe
6740 as long as M1 and M2 have the same number of words. */
6748 #ifndef WORD_REGISTER_OPERATIONS
6751 #endif
6752 #ifdef CANNOT_CHANGE_MODE_CLASS
6757 #endif
6761 {
6764 dest));
6768 }
6770 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6771 in SRC. */
6777 {
6781 /* Here we make sure that we don't have a sign bit on. */
6784 {
6787 }
6788 }
6790 #ifdef LOAD_EXTEND_OP
6791 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6792 would require a paradoxical subreg. Replace the subreg with a
6793 zero_extend to avoid the reload that would otherwise be required. */
6801 {
6807 }
6808 #endif
6810 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6811 are comparing an item known to be 0 or -1 against 0, use a logical
6812 operation instead. Check for one of the arms being an IOR of the other
6813 arm with some value. We compute three terms to be IOR'ed together. In
6814 practice, at most two will be nonzero. Then we do the IOR's. */
6822 #ifdef HAVE_conditional_move
6824 #endif
6829 {
6855 false_rtx);
6861 term3));
6864 }
6866 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6867 whole thing fail. */
6872 else
6873 /* Convert this into a field assignment operation, if possible. */
6875 }
6876 \f
6877 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6878 result. */
6880 static rtx
6882 {
6888 {
6890 /* We can call simplify_and_const_int only if we don't lose
6891 any (sign) bits when converting INTVAL (op1) to
6892 "unsigned HOST_WIDE_INT". */
6896 {
6903 }
6905 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6906 apply the distributive law and then the inverse distributive
6907 law to see if things simplify. */
6909 {
6913 }
6915 {
6919 }
6923 /* If we have (ior (and A B) C), apply the distributive law and then
6924 the inverse distributive law to see if things simplify. */
6927 {
6931 }
6934 {
6938 }
6943 }
6946 }
6947 \f
6948 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6949 operations" because they can be replaced with two more basic operations.
6950 ZERO_EXTEND is also considered "compound" because it can be replaced with
6951 an AND operation, which is simpler, though only one operation.
6953 The function expand_compound_operation is called with an rtx expression
6954 and will convert it to the appropriate shifts and AND operations,
6955 simplifying at each stage.
6957 The function make_compound_operation is called to convert an expression
6958 consisting of shifts and ANDs into the equivalent compound expression.
6959 It is the inverse of this function, loosely speaking. */
6961 static rtx
6963 {
6967 rtx tem;
6970 {
6974 /* We can't necessarily use a const_int for a multiword mode;
6975 it depends on implicitly extending the value.
6976 Since we don't know the right way to extend it,
6977 we can't tell whether the implicit way is right.
6979 Even for a mode that is no wider than a const_int,
6980 we can't win, because we need to sign extend one of its bits through
6981 the rest of it, and we don't know which bit. */
6985 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6986 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6987 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6988 reloaded. If not for that, MEM's would very rarely be safe.
6990 Reject MODEs bigger than a word, because we might not be able
6991 to reference a two-register group starting with an arbitrary register
6992 (and currently gen_lowpart might crash for a SUBREG). */
6997 /* Reject MODEs that aren't scalar integers because turning vector
6998 or complex modes into shifts causes problems. */
7004 /* If the inner object has VOIDmode (the only way this can happen
7005 is if it is an ASM_OPERANDS), we can't do anything since we don't
7006 know how much masking to do. */
7015 /* ... fall through ... */
7018 /* If the operand is a CLOBBER, just return it. */
7027 /* Reject MODEs that aren't scalar integers because turning vector
7028 or complex modes into shifts causes problems. */
7036 /* This should stay within the object being extracted, fail otherwise. */
7047 }
7048 /* Convert sign extension to zero extension, if we know that the high
7049 bit is not set, as this is easier to optimize. It will be converted
7050 back to cheaper alternative in make_extraction. */
7058 {
7062 /* Make sure this is a profitable operation. */
7069 else
7071 }
7073 /* We can optimize some special cases of ZERO_EXTEND. */
7075 {
7076 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7077 know that the last value didn't have any inappropriate bits
7078 set. */
7086 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7095 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7096 is a comparison and STORE_FLAG_VALUE permits. This is like
7097 the first case, but it works even when GET_MODE (x) is larger
7098 than HOST_WIDE_INT. */
7107 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7117 }
7119 /* If we reach here, we want to return a pair of shifts. The inner
7120 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7121 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7122 logical depending on the value of UNSIGNEDP.
7124 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7125 converted into an AND of a shift.
7127 We must check for the case where the left shift would have a negative
7128 count. This can happen in a case like (x >> 31) & 255 on machines
7129 that can't shift by a constant. On those machines, we would first
7130 combine the shift with the AND to produce a variable-position
7131 extraction. Then the constant of 31 would be substituted in
7132 to produce such a position. */
7136 {
7145 }
7152 else
7153 /* Any other cases we can't handle. */
7156 /* If we couldn't do this for some reason, return the original
7157 expression. */
7162 }
7163 \f
7164 /* X is a SET which contains an assignment of one object into
7165 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7166 or certain SUBREGS). If possible, convert it into a series of
7167 logical operations.
7169 We half-heartedly support variable positions, but do not at all
7170 support variable lengths. */
7172 static const_rtx
7174 {
7175 rtx inner;
7179 machine_mode compute_mode;
7181 /* Loop until we find something we can't simplify. */
7183 {
7186 {
7190 }
7193 {
7198 /* A constant position should stay within the width of INNER. */
7204 {
7212 /* If position is ADJUST - X, new position is X. */
7214 else
7215 {
7220 pos);
7221 }
7222 }
7223 }
7225 /* A SUBREG between two modes that occupy the same numbers of words
7226 can be done by moving the SUBREG to the source. */
7228 /* We need SUBREGs to compute nonzero_bits properly. */
7229 && nonzero_sign_valid
7234 {
7236 gen_lowpart
7240 }
7241 else
7249 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7251 {
7252 machine_mode imode;
7254 /* Don't do anything for vector or complex integral types. */
7258 /* Try to find an integral mode to pun with. */
7265 }
7267 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7271 /* Now compute the equivalent expression. Make a copy of INNER
7272 for the SET_DEST in case it is a MEM into which we will substitute;
7273 we don't want shared RTL in that case. */
7275 compute_mode);
7279 compute_mode,
7281 compute_mode),
7282 inner);
7287 mask),
7288 pos);
7293 }
7296 }
7297 \f
7298 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7299 it is an RTX that represents the (variable) starting position; otherwise,
7300 POS is the (constant) starting bit position. Both are counted from the LSB.
7302 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7304 IN_DEST is nonzero if this is a reference in the destination of a SET.
7305 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7306 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7307 be used.
7309 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7310 ZERO_EXTRACT should be built even for bits starting at bit 0.
7312 MODE is the desired mode of the result (if IN_DEST == 0).
7314 The result is an RTX for the extraction or NULL_RTX if the target
7315 can't handle it. */
7317 static rtx
7321 {
7322 /* This mode describes the size of the storage area
7323 to fetch the overall value from. Within that, we
7324 ignore the POS lowest bits, etc. */
7326 machine_mode inner_mode;
7327 machine_mode wanted_inner_mode;
7334 HOST_WIDE_INT orig_pos;
7340 {
7341 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7342 consider just the QI as the memory to extract from.
7343 The subreg adds or removes high bits; its mode is
7344 irrelevant to the meaning of this extraction,
7345 since POS and LEN count from the lsb. */
7349 }
7354 {
7355 /* We're extracting the least significant bits of an rtx
7356 (ashift X (const_int C)), where LEN > C. Extract the
7357 least significant (LEN - C) bits of X, giving an rtx
7358 whose mode is MODE, then shift it left C times. */
7364 }
7370 /* See if this can be done without an extraction. We never can if the
7371 width of the field is not the same as that of some integer mode. For
7372 registers, we can only avoid the extraction if the position is at the
7373 low-order bit and this is either not in the destination or we have the
7374 appropriate STRICT_LOW_PART operation available.
7376 For MEM, we can avoid an extract if the field starts on an appropriate
7377 boundary and we can change the mode of the memory reference. */
7386 && (! in_dest
7390 && (pos
7393 /* We can't do this if we are widening INNER_MODE (it
7394 may not be aligned, for one thing). */
7400 {
7401 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7402 field. If the original and current mode are the same, we need not
7403 adjust the offset. Otherwise, we do if bytes big endian.
7405 If INNER is not a MEM, get a piece consisting of just the field
7406 of interest (in this case POS % BITS_PER_WORD must be 0). */
7409 {
7410 HOST_WIDE_INT offset;
7412 /* POS counts from lsb, but make OFFSET count in memory order. */
7415 else
7419 }
7421 {
7423 {
7424 /* We can't call gen_lowpart in a DEST since we
7425 always want a SUBREG (see below) and it would sometimes
7426 return a new hard register. */
7428 {
7443 /* Avoid creating invalid subregs, for example when
7444 simplifying (x>>32)&255. */
7449 }
7450 else
7452 }
7453 else
7455 }
7456 else
7458 len >= HOST_BITS_PER_WIDE_INT
7463 /* If this extraction is going into the destination of a SET,
7464 make a STRICT_LOW_PART unless we made a MEM. */
7479 /* If we know that no extraneous bits are set, and that the high
7480 bit is not set, convert the extraction to the cheaper of
7481 sign and zero extension, that are equivalent in these cases. */
7487 {
7491 /* Prefer ZERO_EXTENSION, since it gives more information to
7492 backends. */
7497 }
7499 /* Otherwise, sign- or zero-extend unless we already are in the
7500 proper mode. */
7504 }
7506 /* Unless this is a COMPARE or we have a funny memory reference,
7507 don't do anything with zero-extending field extracts starting at
7508 the low-order bit since they are simple AND operations. */
7513 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7514 if the position is not a constant and the length is not 1. In all
7515 other cases, we would only be going outside our object in cases when
7516 an original shift would have been undefined. */
7525 /* If INNER is not from memory, we want it to have the mode of a register
7526 extraction pattern's structure operand, or word_mode if there is no
7527 such pattern. The same applies to extraction_mode and pos_mode
7528 and their respective operands.
7530 For memory, assume that the desired extraction_mode and pos_mode
7531 are the same as for a register operation, since at present we don't
7532 have named patterns for aligned memory structures. */
7536 {
7540 }
7542 /* Never narrow an object, since that might not be safe. */
7550 else
7551 {
7552 /* Be careful not to go beyond the extracted object and maintain the
7553 natural alignment of the memory. */
7557 {
7560 }
7561 }
7566 {
7567 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7568 BITS_BIG_ENDIAN style. If position is constant, compute new
7569 position. Otherwise, build subtraction.
7570 Note that POS is relative to the mode of the original argument.
7571 If it's a MEM we need to recompute POS relative to that.
7572 However, if we're extracting from (or inserting into) a register,
7573 we want to recompute POS relative to wanted_inner_mode. */
7580 else
7581 pos_rtx
7584 pos_rtx);
7585 /* POS may be less than 0 now, but we check for that below.
7586 Note that it can only be less than 0 if !MEM_P (inner). */
7587 }
7589 /* If INNER has a wider mode, and this is a constant extraction, try to
7590 make it smaller and adjust the byte to point to the byte containing
7591 the value. */
7594 && ! pos_rtx
7599 {
7602 /* The computations below will be correct if the machine is big
7603 endian in both bits and bytes or little endian in bits and bytes.
7604 If it is mixed, we must adjust. */
7606 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7607 adjust OFFSET to compensate. */
7612 /* We can now move to the desired byte. */
7623 }
7625 /* If INNER is not memory, get it into the proper mode. If we are changing
7626 its mode, POS must be a constant and smaller than the size of the new
7627 mode. */
7629 {
7630 /* On the LHS, don't create paradoxical subregs implicitely truncating
7631 the register unless TRULY_NOOP_TRUNCATION. */
7634 wanted_inner_mode))
7646 pos_rtx
7652 }
7654 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7655 have to zero extend. Otherwise, we can just use a SUBREG. */
7658 {
7662 /* If we know that no extraneous bits are set, and that the high
7663 bit is not set, convert extraction to cheaper one - either
7664 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7665 cases. */
7673 {
7677 /* Prefer ZERO_EXTENSION, since it gives more information to
7678 backends. */
7682 }
7684 }
7686 /* Make POS_RTX unless we already have it and it is correct. If we don't
7687 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7688 be a CONST_INT. */
7695 /* Make the required operation. See if we can use existing rtx. */
7702 }
7703 \f
7704 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7705 with any other operations in X. Return X without that shift if so. */
7707 static rtx
7709 {
7712 rtx tem;
7715 {
7717 /* This is the shift itself. If it is wide enough, we will return
7718 either the value being shifted if the shift count is equal to
7719 COUNT or a shift for the difference. */
7733 /* If we can safely shift this constant and we find the inner shift,
7734 make a new operation. */
7739 {
7743 }
7748 }
7751 }
7752 \f
7753 /* Look at the expression rooted at X. Look for expressions
7754 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7755 Form these expressions.
7757 Return the new rtx, usually just X.
7759 Also, for machines like the VAX that don't have logical shift insns,
7760 try to convert logical to arithmetic shift operations in cases where
7761 they are equivalent. This undoes the canonicalizations to logical
7762 shifts done elsewhere.
7764 We try, as much as possible, to re-use rtl expressions to save memory.
7766 IN_CODE says what kind of expression we are processing. Normally, it is
7767 SET. In a memory address it is MEM. When processing the arguments of
7768 a comparison or a COMPARE against zero, it is COMPARE. */
7770 rtx
7772 {
7780 rtx tem;
7783 /* Select the code to be used in recursive calls. Once we are inside an
7784 address, we stay there. If we have a comparison, set to COMPARE,
7785 but once inside, go back to our default of SET. */
7792 /* Process depending on the code of this operation. If NEW is set
7793 nonzero, it will be returned. */
7796 {
7798 /* Convert shifts by constants into multiplications if inside
7799 an address. */
7804 {
7810 {
7813 }
7816 }
7826 {
7830 }
7833 {
7837 mode));
7839 }
7840 else
7841 {
7845 }
7856 {
7860 }
7863 {
7867 mode));
7869 }
7870 else
7871 {
7875 }
7879 /* If the second operand is not a constant, we can't do anything
7880 with it. */
7884 /* If the constant is a power of two minus one and the first operand
7885 is a logical right shift, make an extraction. */
7888 {
7892 }
7894 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7899 {
7901 next_code);
7905 }
7906 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7912 {
7913 /* Apply the distributive law, and then try to make extractions. */
7920 }
7922 /* If we are have (and (rotate X C) M) and C is larger than the number
7923 of bits in M, this is an extraction. */
7929 {
7935 }
7937 /* On machines without logical shifts, if the operand of the AND is
7938 a logical shift and our mask turns off all the propagated sign
7939 bits, we can replace the logical shift with an arithmetic shift. */
7947 {
7954 make_compound_operation
7957 }
7959 /* If the constant is one less than a power of two, this might be
7960 representable by an extraction even if no shift is present.
7961 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7962 we are in a COMPARE. */
7966 next_code),
7969 /* If we are in a comparison and this is an AND with a power of two,
7970 convert this into the appropriate bit extract. */
7975 next_code),
7981 /* If the sign bit is known to be zero, replace this with an
7982 arithmetic shift. */
7987 {
7990 next_code),
7993 }
7995 /* ... fall through ... */
8001 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8002 this is a SIGN_EXTRACT. */
8009 {
8016 }
8018 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8019 If so, try to merge the shifts into a SIGN_EXTEND. We could
8020 also do this for some cases of SIGN_EXTRACT, but it doesn't
8021 seem worth the effort; the case checked for occurs on Alpha. */
8037 /* Call ourselves recursively on the inner expression. If we are
8038 narrowing the object and it has a different RTL code from
8039 what it originally did, do this SUBREG as a force_to_mode. */
8040 {
8044 /* If in_code is COMPARE, it isn't always safe to pass it through
8045 to the recursive make_compound_operation call. */
8049 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8050 is (const_int 0), rather than
8051 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8061 simplified
8069 {
8070 rtx newer
8073 /* If we have something other than a SUBREG, we might have
8074 done an expansion, so rerun ourselves. */
8078 /* force_to_mode can expand compounds. If it just re-expanded the
8079 compound, use gen_lowpart to convert to the desired mode. */
8081 /* Likewise if it re-expanded the compound only partially.
8082 This happens for SUBREG of ZERO_EXTRACT if they extract
8083 the same number of bits. */
8092 }
8096 }
8101 }
8104 {
8107 }
8109 /* Now recursively process each operand of this operation. We need to
8110 handle ZERO_EXTEND specially so that we don't lose track of the
8111 inner mode. */
8113 {
8121 }
8126 {
8129 }
8132 {
8135 }
8137 maybe_swap:
8138 /* If this is a commutative operation, the changes to the operands
8139 may have made it noncanonical. */
8142 {
8146 }
8149 }
8150 \f
8151 /* Given M see if it is a value that would select a field of bits
8152 within an item, but not the entire word. Return -1 if not.
8153 Otherwise, return the starting position of the field, where 0 is the
8154 low-order bit.
8156 *PLEN is set to the length of the field. */
8158 static int
8160 {
8161 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8166 /* Now shift off the low-order zero bits and see if we have a
8167 power of two minus 1. */
8175 }
8176 \f
8177 /* If X refers to a register that equals REG in value, replace these
8178 references with REG. */
8179 static rtx
8181 {
8189 {
8225 {
8229 else
8231 }
8233 /* fall through */
8240 {
8243 {
8245 {
8248 }
8250 }
8251 }
8253 {
8256 {
8259 {
8261 {
8264 }
8266 }
8267 }
8268 }
8271 }
8274 }
8276 /* Return X converted to MODE. If the value is already truncated to
8277 MODE we can just return a subreg even though in the general case we
8278 would need an explicit truncation. */
8280 static rtx
8282 {
8287 {
8288 /* Bit-cast X into an integer mode. */
8293 }
8296 }
8298 /* See if X can be simplified knowing that we will only refer to it in
8299 MODE and will only refer to those bits that are nonzero in MASK.
8300 If other bits are being computed or if masking operations are done
8301 that select a superset of the bits in MASK, they can sometimes be
8302 ignored.
8304 Return a possibly simplified expression, but always convert X to
8305 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8307 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8308 are all off in X. This is used when X will be complemented, by either
8309 NOT, NEG, or XOR. */
8311 static rtx
8314 {
8317 machine_mode op_mode;
8321 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8322 code below will do the wrong thing since the mode of such an
8323 expression is VOIDmode.
8325 Also do nothing if X is a CLOBBER; this can happen if X was
8326 the return value from a call to gen_lowpart. */
8330 /* We want to perform the operation in its present mode unless we know
8331 that the operation is valid in MODE, in which case we do the operation
8332 in MODE. */
8337 /* It is not valid to do a right-shift in a narrower mode
8338 than the one it came in with. */
8343 /* Truncate MASK to fit OP_MODE. */
8347 /* When we have an arithmetic operation, or a shift whose count we
8348 do not know, we need to assume that all bits up to the highest-order
8349 bit in MASK will be needed. This is how we form such a mask. */
8352 else
8356 /* Determine what bits of X are guaranteed to be (non)zero. */
8359 /* If none of the bits in X are needed, return a zero. */
8363 /* If X is a CONST_INT, return a new one. Do this here since the
8364 test below will fail. */
8366 {
8369 else
8370 {
8373 }
8374 }
8376 /* If X is narrower than MODE and we want all the bits in X's mode, just
8377 get X in the proper mode. */
8382 /* We can ignore the effect of a SUBREG if it narrows the mode or
8383 if the constant masks to zero all the bits the mode doesn't have. */
8393 /* The arithmetic simplifications here only work for scalar integer modes. */
8398 {
8400 /* If X is a (clobber (const_int)), return it since we know we are
8401 generating something that won't match. */
8414 /* Similarly for a truncate. */
8418 /* If this is an AND with a constant, convert it into an AND
8419 whose constant is the AND of that constant with MASK. If it
8420 remains an AND of MASK, delete it since it is redundant. */
8423 {
8427 /* If X is still an AND, see if it is an AND with a mask that
8428 is just some low-order bits. If so, and it is MASK, we don't
8429 need it. */
8436 /* If it remains an AND, try making another AND with the bits
8437 in the mode mask that aren't in MASK turned on. If the
8438 constant in the AND is wide enough, this might make a
8439 cheaper constant. */
8444 {
8445 unsigned HOST_WIDE_INT cval
8448 rtx y;
8455 }
8458 }
8463 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8464 low-order bits (as in an alignment operation) and FOO is already
8465 aligned to that boundary, mask C1 to that boundary as well.
8466 This may eliminate that PLUS and, later, the AND. */
8468 {
8472 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8473 number, sign extend it. */
8486 }
8488 /* ... fall through ... */
8491 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8492 most significant bit in MASK since carries from those bits will
8493 affect the bits we are interested in. */
8498 /* If X is (minus C Y) where C's least set bit is larger than any bit
8499 in the mask, then we may replace with (neg Y). */
8502 {
8506 }
8508 /* Similarly, if C contains every bit in the fuller_mask, then we may
8509 replace with (not Y). */
8512 {
8516 }
8523 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8524 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8525 operation which may be a bitfield extraction. Ensure that the
8526 constant we form is not wider than the mode of X. */
8538 {
8547 }
8549 binop:
8550 /* For most binary operations, just propagate into the operation and
8551 change the mode if we have an operation of that mode. */
8556 /* If we ended up truncating both operands, truncate the result of the
8557 operation instead. */
8560 {
8563 }
8573 /* For left shifts, do the same, but just for the first operand.
8574 However, we cannot do anything with shifts where we cannot
8575 guarantee that the counts are smaller than the size of the mode
8576 because such a count will have a different meaning in a
8577 wider mode. */
8587 /* If the shift count is a constant and we can do arithmetic in
8588 the mode of the shift, refine which bits we need. Otherwise, use the
8589 conservative form of the mask. */
8595 else
8607 /* Here we can only do something if the shift count is a constant,
8608 this shift constant is valid for the host, and we can do arithmetic
8609 in OP_MODE. */
8615 {
8619 /* Select the mask of the bits we need for the shift operand. */
8622 /* We can only change the mode of the shift if we can do arithmetic
8623 in the mode of the shift and INNER_MASK is no wider than the
8624 width of X's mode. */
8632 }
8634 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8635 shift and AND produces only copies of the sign bit (C2 is one less
8636 than a power of two), we can do this with just a shift. */
8640 /* The shift puts one of the sign bit copies in the least significant
8641 bit. */
8646 /* Number of bits left after the shift must be more than the mask
8647 needs. */
8650 /* Must be more sign bit copies than the mask needs. */
8660 /* If we are just looking for the sign bit, we don't need this shift at
8661 all, even if it has a variable count. */
8665 /* If this is a shift by a constant, get a mask that contains those bits
8666 that are not copies of the sign bit. We then have two cases: If
8667 MASK only includes those bits, this can be a logical shift, which may
8668 allow simplifications. If MASK is a single-bit field not within
8669 those bits, we are requesting a copy of the sign bit and hence can
8670 shift the sign bit to the appropriate location. */
8674 {
8677 /* If the considered data is wider than HOST_WIDE_INT, we can't
8678 represent a mask for all its bits in a single scalar.
8679 But we only care about the lower bits, so calculate these. */
8682 {
8685 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8686 is the number of bits a full-width mask would have set.
8687 We need only shift if these are fewer than nonzero can
8688 hold. If not, we must keep all bits set in nonzero. */
8693 + HOST_BITS_PER_WIDE_INT
8695 }
8696 else
8697 {
8700 }
8703 {
8708 }
8711 {
8712 x = simplify_shift_const
8718 }
8719 }
8721 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8722 even if the shift count isn't a constant. */
8727 shiftrt:
8729 /* If this is a zero- or sign-extension operation that just affects bits
8730 we don't care about, remove it. Be sure the call above returned
8731 something that is still a shift. */
8741 next_select);
8747 /* If the shift count is constant and we can do computations
8748 in the mode of X, compute where the bits we care about are.
8749 Otherwise, we can't do anything. Don't change the mode of
8750 the shift or propagate MODE into the shift, though. */
8753 {
8763 }
8767 /* If we just want the low-order bit, the NEG isn't needed since it
8768 won't change the low-order bit. */
8772 /* We need any bits less significant than the most significant bit in
8773 MASK since carries from those bits will affect the bits we are
8774 interested in. */
8779 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8780 same as the XOR case above. Ensure that the constant we form is not
8781 wider than the mode of X. */
8789 {
8798 }
8800 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8801 use the full mask inside the NOT. */
8804 unop:
8807 next_select));
8813 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8814 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8815 which is equal to STORE_FLAG_VALUE. */
8827 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8828 written in a narrower mode. We play it safe and do not do so. */
8844 }
8846 /* Ensure we return a value of the proper mode. */
8848 }
8849 \f
8850 /* Return nonzero if X is an expression that has one of two values depending on
8851 whether some other value is zero or nonzero. In that case, we return the
8852 value that is being tested, *PTRUE is set to the value if the rtx being
8853 returned has a nonzero value, and *PFALSE is set to the other alternative.
8855 If we return zero, we set *PTRUE and *PFALSE to X. */
8857 static rtx
8859 {
8865 /* If we are comparing a value against zero, we are done. */
8868 {
8872 }
8874 /* If this is a unary operation whose operand has one of two values, apply
8875 our opcode to compute those values. */
8878 {
8883 }
8885 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8886 make can't possibly match and would suppress other optimizations. */
8888 ;
8890 /* If this is a binary operation, see if either side has only one of two
8891 values. If either one does or if both do and they are conditional on
8892 the same value, compute the new true and false values. */
8894 {
8900 {
8901 /* If if_then_else_cond returned zero, then true/false are the
8902 same rtl. We must copy one of them to prevent invalid rtl
8903 sharing. */
8910 {
8915 }
8916 else
8917 {
8920 }
8923 }
8925 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8926 operands is zero when the other is nonzero, and vice-versa,
8927 and STORE_FLAG_VALUE is 1 or -1. */
8933 {
8950 {
8957 const_true_rtx);
8959 }
8960 }
8962 /* Similarly for MULT, AND and UMIN, except that for these the result
8963 is always zero. */
8967 {
8981 {
8984 }
8985 }
8986 }
8989 {
8990 /* If we have IF_THEN_ELSE already, extract the condition and
8991 canonicalize it if it is NE or EQ. */
8997 {
9000 }
9001 else
9003 }
9005 /* If X is a SUBREG, we can narrow both the true and false values
9006 if the inner expression, if there is a condition. */
9010 {
9016 {
9020 }
9021 }
9023 /* If X is a constant, this isn't special and will cause confusions
9024 if we treat it as such. Likewise if it is equivalent to a constant. */
9027 ;
9029 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9030 will be least confusing to the rest of the compiler. */
9032 {
9035 }
9037 /* If X is known to be either 0 or -1, those are the true and
9038 false values when testing X. */
9042 {
9045 }
9047 /* Likewise for 0 or a single bit. */
9050 {
9053 }
9055 /* Otherwise fail; show no condition with true and false values the same. */
9058 }
9059 \f
9060 /* Return the value of expression X given the fact that condition COND
9061 is known to be true when applied to REG as its first operand and VAL
9062 as its second. X is known to not be shared and so can be modified in
9063 place.
9065 We only handle the simplest cases, and specifically those cases that
9066 arise with IF_THEN_ELSE expressions. */
9068 static rtx
9070 {
9078 /* If either operand of the condition is a floating point value,
9079 then we have to avoid collapsing an EQ comparison. */
9089 /* If X is (abs REG) and we know something about REG's relationship
9090 with zero, we may be able to simplify this. */
9094 {
9103 }
9105 /* The only other cases we handle are MIN, MAX, and comparisons if the
9106 operands are the same as REG and VAL. */
9109 {
9111 {
9114 }
9117 {
9119 {
9127 else
9129 }
9132 {
9135 /* Do not reverse the condition when it is NE or EQ.
9136 This is because we cannot conclude anything about
9137 the value of 'SMAX (x, y)' when x is not equal to y,
9138 but we can when x equals y. */
9144 {
9155 }
9156 }
9157 }
9158 }
9160 {
9165 {
9166 /* We must simplify subreg here, before we lose track of the
9167 original inner_mode. */
9172 else
9174 }
9177 }
9178 /* We don't have to handle SIGN_EXTEND here, because even in the
9179 case of replacing something with a modeless CONST_INT, a
9180 CONST_INT is already (supposed to be) a valid sign extension for
9181 its narrower mode, which implies it's already properly
9182 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9183 story is different. */
9185 {
9190 {
9191 /* We must simplify the zero_extend here, before we lose
9192 track of the original inner_mode. */
9197 else
9199 }
9202 }
9206 {
9213 }
9216 }
9217 \f
9218 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9219 assignment as a field assignment. */
9221 static int
9223 {
9225 {
9230 /* For big endian, adjust the memory offset. */
9235 else
9237 }
9245 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9246 Note that all SUBREGs of MEM are paradoxical; otherwise they
9247 would have been rewritten. */
9260 /* We used to see if get_last_value of X and Y were the same but that's
9261 not correct. In one direction, we'll cause the assignment to have
9262 the wrong destination and in the case, we'll import a register into this
9263 insn that might have already have been dead. So fail if none of the
9264 above cases are true. */
9266 }
9267 \f
9268 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9269 Return that assignment if so.
9271 We only handle the most common cases. */
9273 static rtx
9275 {
9278 rtx assign;
9280 HOST_WIDE_INT c1;
9281 HOST_WIDE_INT pos;
9283 rtx other;
9284 machine_mode mode;
9286 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9287 a clear of a one-bit field. We will have changed it to
9288 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9289 for a SUBREG. */
9295 {
9301 }
9311 {
9318 }
9320 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9321 one-bit field. */
9325 {
9331 }
9333 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9334 SRC is an AND with all bits of that field set, then we can discard
9335 the AND. */
9340 {
9347 else
9350 /* Complete overlap. We can remove the source AND. */
9354 /* Partial overlap. We can reduce the source AND. */
9356 {
9361 }
9362 }
9364 /* The other case we handle is assignments into a constant-position
9365 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9366 a mask that has all one bits except for a group of zero bits and
9367 OTHER is known to have zeros where C1 has ones, this is such an
9368 assignment. Compute the position and length from C1. Shift OTHER
9369 to the appropriate position, force it to the required mode, and
9370 make the extraction. Check for the AND in both operands. */
9372 /* One or more SUBREGs might obscure the constant-position field
9373 assignment. The first one we are likely to encounter is an outer
9374 narrowing SUBREG, which we can just strip for the purposes of
9375 identifying the constant-field assignment. */
9389 /* The second SUBREG that might get in the way is a paradoxical
9390 SUBREG around the first operand of the AND. We want to
9391 pretend the operand is as wide as the destination here. We
9392 do this by adjusting the MEM to wider mode for the sole
9393 purpose of the call to rtx_equal_for_field_assignment_p. Also
9394 note this trick only works for MEMs. */
9406 /* The second SUBREG that might get in the way is a paradoxical
9407 SUBREG around the first operand of the AND. We want to
9408 pretend the operand is as wide as the destination here. We
9409 do this by adjusting the MEM to wider mode for the sole
9410 purpose of the call to rtx_equal_for_field_assignment_p. Also
9411 note this trick only works for MEMs. */
9419 else
9432 /* The mode to use for the source is the mode of the assignment, or of
9433 what is inside a possible STRICT_LOW_PART. */
9437 /* Shift OTHER right POS places and make it the source, restricting it
9438 to the proper length and mode. */
9443 dest);
9450 /* If SRC is masked by an AND that does not make a difference in
9451 the value being stored, strip it. */
9462 }
9463 \f
9464 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9465 if so. */
9467 static rtx
9469 {
9473 rtx tem;
9475 /* Distributivity is not true for floating point as it can change the
9476 value. So we don't do it unless -funsafe-math-optimizations. */
9481 /* The outer operation can only be one of the following: */
9489 /* If either operand is a primitive we can't do anything, so get out
9490 fast. */
9500 /* See if the inner and outer operations distribute. */
9502 {
9507 /* These all distribute except over PLUS. */
9518 /* This is also a multiply, so it distributes over everything. */
9521 /* This used to handle SUBREG, but this turned out to be counter-
9522 productive, since (subreg (op ...)) usually is not handled by
9523 insn patterns, and this "optimization" therefore transformed
9524 recognizable patterns into unrecognizable ones. Therefore the
9525 SUBREG case was removed from here.
9527 It is possible that distributing SUBREG over arithmetic operations
9528 leads to an intermediate result than can then be optimized further,
9529 e.g. by moving the outer SUBREG to the other side of a SET as done
9530 in simplify_set. This seems to have been the original intent of
9531 handling SUBREGs here.
9533 However, with current GCC this does not appear to actually happen,
9534 at least on major platforms. If some case is found where removing
9535 the SUBREG case here prevents follow-on optimizations, distributing
9536 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9540 }
9542 /* Set LHS and RHS to the inner operands (A and B in the example
9543 above) and set OTHER to the common operand (C in the example).
9544 There is only one way to do this unless the inner operation is
9545 commutative. */
9557 else
9560 /* Form the new inner operation, seeing if it simplifies first. */
9563 /* There is one exception to the general way of distributing:
9564 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9566 {
9569 }
9571 /* We may be able to continuing distributing the result, so call
9572 ourselves recursively on the inner operation before forming the
9573 outer operation, which we return. */
9576 }
9578 /* See if X is of the form (* (+ A B) C), and if so convert to
9579 (+ (* A C) (* B C)) and try to simplify.
9581 Most of the time, this results in no change. However, if some of
9582 the operands are the same or inverses of each other, simplifications
9583 will result.
9585 For example, (and (ior A B) (not B)) can occur as the result of
9586 expanding a bit field assignment. When we apply the distributive
9587 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9588 which then simplifies to (and (A (not B))).
9590 Note that no checks happen on the validity of applying the inverse
9591 distributive law. This is pointless since we can do it in the
9592 few places where this routine is called.
9594 N is the index of the term that is decomposed (the arithmetic operation,
9595 i.e. (+ A B) in the first example above). !N is the index of the term that
9596 is distributed, i.e. of C in the first example above. */
9597 static rtx
9599 {
9600 machine_mode mode;
9604 /* Distributivity is not true for floating point as it can change the
9605 value. So we don't do it unless -funsafe-math-optimizations. */
9622 /* Special case (and (xor B C) (not A)), which is equivalent to
9623 (xor (ior A B) (ior A C)) */
9625 {
9628 }
9631 {
9632 /* Distribute the second term. */
9635 }
9636 else
9637 {
9638 /* Distribute the first term. */
9641 }
9651 }
9652 \f
9653 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9654 in MODE. Return an equivalent form, if different from (and VAROP
9655 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9657 static rtx
9660 {
9663 rtx orig_varop;
9671 /* Simplify VAROP knowing that we will be only looking at some of the
9672 bits in it.
9674 Note by passing in CONSTOP, we guarantee that the bits not set in
9675 CONSTOP are not significant and will never be examined. We must
9676 ensure that is the case by explicitly masking out those bits
9677 before returning. */
9680 /* If VAROP is a CLOBBER, we will fail so return it. */
9684 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9685 to VAROP and return the new constant. */
9689 /* See what bits may be nonzero in VAROP. Unlike the general case of
9690 a call to nonzero_bits, here we don't care about bits outside
9691 MODE. */
9695 /* Turn off all bits in the constant that are known to already be zero.
9696 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9697 which is tested below. */
9701 /* If we don't have any bits left, return zero. */
9705 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9706 a power of two, we can replace this with an ASHIFT. */
9711 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9712 or XOR, then try to apply the distributive law. This may eliminate
9713 operations if either branch can be simplified because of the AND.
9714 It may also make some cases more complex, but those cases probably
9715 won't match a pattern either with or without this. */
9718 return
9719 gen_lowpart
9721 apply_distributive_law
9726 constop),
9730 constop))));
9732 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9733 the AND and see if one of the operands simplifies to zero. If so, we
9734 may eliminate it. */
9738 {
9747 }
9749 /* Make a SUBREG if necessary. If we can't make it, fail. */
9754 /* If we are only masking insignificant bits, return VAROP. */
9761 /* Otherwise, return an AND. */
9763 }
9766 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9767 in MODE.
9769 Return an equivalent form, if different from X. Otherwise, return X. If
9770 X is zero, we are to always construct the equivalent form. */
9772 static rtx
9775 {
9786 }
9787 \f
9788 /* Given a REG, X, compute which bits in X can be nonzero.
9789 We don't care about bits outside of those defined in MODE.
9791 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9792 a shift, AND, or zero_extract, we can do better. */
9794 static rtx
9796 const_rtx known_x ATTRIBUTE_UNUSED,
9797 machine_mode known_mode ATTRIBUTE_UNUSED,
9800 {
9801 rtx tem;
9804 /* If X is a register whose nonzero bits value is current, use it.
9805 Otherwise, if X is a register whose value we can find, use that
9806 value. Otherwise, use the previously-computed global nonzero bits
9807 for this register. */
9821 && !REGNO_REG_SET_P
9824 {
9828 /* We don't know anything about the upper bits. */
9833 }
9838 {
9839 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9842 #endif
9844 }
9846 {
9850 /* We don't know anything about the upper bits. */
9854 }
9857 }
9859 /* Return the number of bits at the high-order end of X that are known to
9860 be equal to the sign bit. X will be used in mode MODE; if MODE is
9861 VOIDmode, X will be used in its own mode. The returned value will always
9862 be between 1 and the number of bits in MODE. */
9864 static rtx
9866 const_rtx known_x ATTRIBUTE_UNUSED,
9867 machine_mode known_mode
9868 ATTRIBUTE_UNUSED,
9871 {
9872 rtx tem;
9885 && !REGNO_REG_SET_P
9888 {
9891 }
9902 }
9903 \f
9904 /* Return the number of "extended" bits there are in X, when interpreted
9905 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9906 unsigned quantities, this is the number of high-order zero bits.
9907 For signed quantities, this is the number of copies of the sign bit
9908 minus 1. In both case, this function returns the number of "spare"
9909 bits. For example, if two quantities for which this function returns
9910 at least 1 are added, the addition is known not to overflow.
9912 This function will always return 0 unless called during combine, which
9913 implies that it must be called from a define_split. */
9915 unsigned int
9917 {
9927 }
9929 /* This function is called from `simplify_shift_const' to merge two
9930 outer operations. Specifically, we have already found that we need
9931 to perform operation *POP0 with constant *PCONST0 at the outermost
9932 position. We would now like to also perform OP1 with constant CONST1
9933 (with *POP0 being done last).
9935 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9936 the resulting operation. *PCOMP_P is set to 1 if we would need to
9937 complement the innermost operand, otherwise it is unchanged.
9939 MODE is the mode in which the operation will be done. No bits outside
9940 the width of this mode matter. It is assumed that the width of this mode
9941 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9943 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9944 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9945 result is simply *PCONST0.
9947 If the resulting operation cannot be expressed as one operation, we
9948 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9950 static int
9951 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
9952 {
9959 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9963 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9964 if OP0 is SET. */
9973 {
9975 {
9993 }
9994 }
9996 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10000 /* If the two constants aren't the same, we can't do anything. The
10001 remaining six cases can all be done. */
10005 else
10007 {
10010 /* (a & b) | b == b */
10013 /* (a ^ b) | b == a | b */
10014 {;}
10019 /* (a & b) ^ b == (~a) & b */
10022 /* (a | b) ^ b == a & ~b */
10028 /* (a | b) & b == b */
10031 /* (a ^ b) & b) == (~a) & b */
10036 }
10038 /* Check for NO-OP cases. */
10051 /* ??? Slightly redundant with the above mask, but not entirely.
10052 Moving this above means we'd have to sign-extend the mode mask
10053 for the final test. */
10058 }
10059 \f
10060 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10061 the shift in. The original shift operation CODE is performed on OP in
10062 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10063 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10064 result of the shift is subject to operation OUTER_CODE with operand
10065 OUTER_CONST. */
10067 static machine_mode
10071 {
10076 /* In general we can't perform in wider mode for right shift and rotate. */
10078 {
10080 /* We can still widen if the bits brought in from the left are identical
10081 to the sign bit of ORIG_MODE. */
10089 /* Similarly here but with zero bits. */
10094 /* We can also widen if the bits brought in will be masked off. This
10095 operation is performed in ORIG_MODE. */
10097 {
10103 }
10104 /* fall through */
10114 }
10115 }
10117 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10118 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10119 if we cannot simplify it. Otherwise, return a simplified value.
10121 The shift is normally computed in the widest mode we find in VAROP, as
10122 long as it isn't a different number of words than RESULT_MODE. Exceptions
10123 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10125 static rtx
10128 {
10134 unsigned int mode_words
10136 /* We form (outer_op (code varop count) (outer_const)). */
10142 /* Make sure and truncate the "natural" shift on the way in. We don't
10143 want to do this inside the loop as it makes it more difficult to
10144 combine shifts. */
10148 /* If we were given an invalid count, don't do anything except exactly
10149 what was requested. */
10156 /* Unless one of the branches of the `if' in this loop does a `continue',
10157 we will `break' the loop after the `if'. */
10160 {
10161 /* If we have an operand of (clobber (const_int 0)), fail. */
10165 /* Convert ROTATERT to ROTATE. */
10167 {
10172 else
10174 }
10179 /* Handle cases where the count is greater than the size of the mode
10180 minus 1. For ASHIFT, use the size minus one as the count (this can
10181 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10182 take the count modulo the size. For other shifts, the result is
10183 zero.
10185 Since these shifts are being produced by the compiler by combining
10186 multiple operations, each of which are defined, we know what the
10187 result is supposed to be. */
10190 {
10195 else
10196 {
10197 /* We can't simply return zero because there may be an
10198 outer op. */
10202 }
10203 }
10205 /* If we discovered we had to complement VAROP, leave. Making a NOT
10206 here would cause an infinite loop. */
10210 /* An arithmetic right shift of a quantity known to be -1 or 0
10211 is a no-op. */
10215 {
10218 }
10220 /* If we are doing an arithmetic right shift and discarding all but
10221 the sign bit copies, this is equivalent to doing a shift by the
10222 bitsize minus one. Convert it into that shift because it will often
10223 allow other simplifications. */
10230 /* We simplify the tests below and elsewhere by converting
10231 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10232 `make_compound_operation' will convert it to an ASHIFTRT for
10233 those machines (such as VAX) that don't have an LSHIFTRT. */
10250 {
10257 {
10260 }
10264 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10265 minus the width of a smaller mode, we can do this with a
10266 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10273 {
10282 }
10286 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10287 the same number of words as what we've seen so far. Then store
10288 the widest mode in MODE. */
10294 == mode_words
10297 {
10302 }
10306 /* Some machines use MULT instead of ASHIFT because MULT
10307 is cheaper. But it is still better on those machines to
10308 merge two shifts into one. */
10311 {
10312 varop
10318 }
10322 /* Similar, for when divides are cheaper. */
10325 {
10326 varop
10332 }
10336 /* If we are extracting just the sign bit of an arithmetic
10337 right shift, that shift is not needed. However, the sign
10338 bit of a wider mode may be different from what would be
10339 interpreted as the sign bit in a narrower mode, so, if
10340 the result is narrower, don't discard the shift. */
10345 {
10348 }
10350 /* ... fall through ... */
10355 /* Here we have two nested shifts. The result is usually the
10356 AND of a new shift with a mask. We compute the result below. */
10363 {
10367 rtx mask_rtx;
10369 /* We have one common special case. We can't do any merging if
10370 the inner code is an ASHIFTRT of a smaller mode. However, if
10371 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10372 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10373 we can convert it to
10374 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10375 This simplifies certain SIGN_EXTEND operations. */
10379 {
10380 /* C3 has the low-order C1 bits zero. */
10392 }
10394 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10395 than C1 high-order bits equal to the sign bit, we can convert
10396 this to either an ASHIFT or an ASHIFTRT depending on the
10397 two counts.
10399 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10405 {
10409 {
10412 }
10415 }
10417 /* There are some cases we can't do. If CODE is ASHIFTRT,
10418 we can only do this if FIRST_CODE is also ASHIFTRT.
10420 We can't do the case when CODE is ROTATE and FIRST_CODE is
10421 ASHIFTRT.
10423 If the mode of this shift is not the mode of the outer shift,
10424 we can't do this if either shift is a right shift or ROTATE.
10426 Finally, we can't do any of these if the mode is too wide
10427 unless the codes are the same.
10429 Handle the case where the shift codes are the same
10430 first. */
10433 {
10442 }
10453 /* To compute the mask to apply after the shift, shift the
10454 nonzero bits of the inner shift the same way the
10455 outer shift will. */
10458 result_mode);
10460 mask_rtx
10464 /* Give up if we can't compute an outer operation to use. */
10472 /* If the shifts are in the same direction, we add the
10473 counts. Otherwise, we subtract them. */
10477 else
10480 /* If COUNT is positive, the new shift is usually CODE,
10481 except for the two exceptions below, in which case it is
10482 FIRST_CODE. If the count is negative, FIRST_CODE should
10483 always be used */
10493 }
10495 /* If we have (A << B << C) for any shift, we can convert this to
10496 (A << C << B). This wins if A is a constant. Only try this if
10497 B is not a constant. */
10502 {
10509 }
10516 /* Make this fit the case below. */
10523 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10524 with C the size of VAROP - 1 and the shift is logical if
10525 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10526 we have an (le X 0) operation. If we have an arithmetic shift
10527 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10528 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10536 {
10539 const0_rtx);
10545 }
10547 /* If we have (shift (logical)), move the logical to the outside
10548 to allow it to possibly combine with another logical and the
10549 shift to combine with another shift. This also canonicalizes to
10550 what a ZERO_EXTRACT looks like. Also, some machines have
10551 (and (shift)) insns. */
10554 /* We can't do this if we have (ashiftrt (xor)) and the
10555 constant has its sign bit set in shift_mode with shift_mode
10556 wider than result_mode. */
10560 shift_mode))
10568 {
10571 }
10573 /* If we can't do that, try to simplify the shift in each arm of the
10574 logical expression, make a new logical expression, and apply
10575 the inverse distributive law. This also can't be done for
10576 (ashiftrt (xor)) where we've widened the shift and the constant
10577 changes the sign bit. */
10582 shift_mode)))
10583 {
10595 }
10599 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10600 says that the sign bit can be tested, FOO has mode MODE, C is
10601 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10602 that may be nonzero. */
10612 {
10616 }
10620 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10621 than the number of bits in the mode is equivalent to A. */
10625 {
10629 }
10631 /* NEG commutes with ASHIFT since it is multiplication. Move the
10632 NEG outside to allow shifts to combine. */
10636 {
10639 }
10643 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10644 is one less than the number of bits in the mode is
10645 equivalent to (xor A 1). */
10652 {
10656 }
10658 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10659 that might be nonzero in BAR are those being shifted out and those
10660 bits are known zero in FOO, we can replace the PLUS with FOO.
10661 Similarly in the other operand order. This code occurs when
10662 we are computing the size of a variable-size array. */
10669 {
10672 }
10680 result_mode)))
10681 {
10684 }
10686 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10696 {
10699 }
10701 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10702 signbit', and attempt to change the PLUS to an XOR and move it to
10703 the outer operation as is done above in the AND/IOR/XOR case
10704 leg for shift(logical). See details in logical handling above
10705 for reasoning in doing so. */
10716 {
10719 }
10724 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10725 with C the size of VAROP - 1 and the shift is logical if
10726 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10727 we have a (gt X 0) operation. If the shift is arithmetic with
10728 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10729 we have a (neg (gt X 0)) operation. */
10738 {
10741 const0_rtx);
10747 }
10751 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10752 if the truncate does not affect the value. */
10759 {
10762 varop_inner
10765 GEN_INT
10770 }
10775 }
10778 }
10783 /* We have now finished analyzing the shift. The result should be
10784 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10785 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10786 to the result of the shift. OUTER_CONST is the relevant constant,
10787 but we must turn off all bits turned off in the shift. */
10795 /* Make a SUBREG if necessary. If we can't make it, fail. */
10800 /* If we have an outer operation and we just made a shift, it is
10801 possible that we could have simplified the shift were it not
10802 for the outer operation. So try to do the simplification
10803 recursively. */
10807 else
10813 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10814 turn off all the bits that the shift would have turned off. */
10819 /* Do the remainder of the processing in RESULT_MODE. */
10822 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10823 operation. */
10828 {
10836 {
10837 /* This means that we have determined that the result is
10838 equivalent to a constant. This should be rare. */
10841 }
10844 else
10847 }
10850 }
10852 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10853 The result of the shift is RESULT_MODE. If we cannot simplify it,
10854 return X or, if it is NULL, synthesize the expression with
10855 simplify_gen_binary. Otherwise, return a simplified value.
10857 The shift is normally computed in the widest mode we find in VAROP, as
10858 long as it isn't a different number of words than RESULT_MODE. Exceptions
10859 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10861 static rtx
10864 {
10874 }
10876 \f
10877 /* A subroutine of recog_for_combine. See there for arguments and
10878 return value. */
10880 static int
10882 {
10884 rtx pat_without_clobbers;
10892 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10893 we use to indicate that something didn't match. If we find such a
10894 thing, force rejection. */
10908 {
10911 else
10914 }
10916 /* If it isn't, there is the possibility that we previously had an insn
10917 that clobbered some register as a side effect, but the combined
10918 insn doesn't need to do that. So try once more without the clobbers
10919 unless this represents an ASM insn. */
10923 {
10928 {
10931 pos++;
10932 }
10942 {
10945 else
10948 }
10949 }
10956 /* Recognize all noop sets, these will be killed by followup pass. */
10960 /* If we had any clobbers to add, make a new pattern than contains
10961 them. Then check to make sure that all of them are dead. */
10963 {
10973 else
10980 {
10985 {
10989 }
10990 }
10992 }
10996 {
11003 /* Allow targets to reject combined insn. */
11005 {
11008 dump_file);
11010 /* Callers expect recog_for_combine to strip
11011 clobbers from the pattern on failure. */
11016 }
11021 }
11027 }
11029 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11030 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11031 Return whether anything was so changed. */
11033 static bool
11035 {
11040 {
11049 {
11057 }
11062 {
11065 }
11066 else
11071 mask--;
11077 }
11080 }
11082 /* Like recog, but we receive the address of a pointer to a new pattern.
11083 We try to match the rtx that the pointer points to.
11084 If that fails, we may try to modify or replace the pattern,
11085 storing the replacement into the same pointer object.
11087 Modifications include deletion or addition of CLOBBERs. If the
11088 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11089 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11090 (and undo if that fails).
11092 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11093 the CLOBBERs are placed.
11095 The value is the final insn code from the pattern ultimately matched,
11096 or -1. */
11098 static int
11100 {
11112 {
11115 {
11119 }
11120 }
11123 {
11128 }
11131 }
11132 \f
11133 /* Like gen_lowpart_general but for use by combine. In combine it
11134 is not possible to create any new pseudoregs. However, it is
11135 safe to create invalid memory addresses, because combine will
11136 try to recognize them and all they will do is make the combine
11137 attempt fail.
11139 If for some reason this cannot do its job, an rtx
11140 (clobber (const_int 0)) is returned.
11141 An insn containing that will not be recognized. */
11143 static rtx
11145 {
11149 rtx result;
11154 /* We can only support MODE being wider than a word if X is a
11155 constant integer or has a mode the same size. */
11160 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11161 won't know what to do. So we will strip off the SUBREG here and
11162 process normally. */
11164 {
11167 /* For use in case we fall down into the address adjustments
11168 further below, we need to adjust the known mode and size of
11169 x; imode and isize, since we just adjusted x. */
11176 }
11184 {
11187 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11188 address. */
11193 /* If we want to refer to something bigger than the original memref,
11194 generate a paradoxical subreg instead. That will force a reload
11195 of the original memref X. */
11202 /* Adjust the address so that the address-after-the-data is
11203 unchanged. */
11208 }
11210 /* If X is a comparison operator, rewrite it in a new mode. This
11211 probably won't match, but may allow further simplifications. */
11215 /* If we couldn't simplify X any other way, just enclose it in a
11216 SUBREG. Normally, this SUBREG won't match, but some patterns may
11217 include an explicit SUBREG or we may simplify it further in combine. */
11218 else
11219 {
11221 rtx res;
11225 {
11230 }
11234 }
11236 fail:
11238 }
11239 \f
11240 /* Try to simplify a comparison between OP0 and a constant OP1,
11241 where CODE is the comparison code that will be tested, into a
11242 (CODE OP0 const0_rtx) form.
11244 The result is a possibly different comparison code to use.
11245 *POP1 may be updated. */
11247 static enum rtx_code
11250 {
11254 /* Get the constant we are comparing against and turn off all bits
11255 not on in our mode. */
11259 /* If we are comparing against a constant power of two and the value
11260 being compared can only have that single bit nonzero (e.g., it was
11261 `and'ed with that bit), we can replace this with a comparison
11262 with zero. */
11270 {
11273 }
11275 /* Similarly, if we are comparing a value known to be either -1 or
11276 0 with -1, change it to the opposite comparison against zero. */
11281 {
11284 }
11286 /* Do some canonicalizations based on the comparison code. We prefer
11287 comparisons against zero and then prefer equality comparisons.
11288 If we can reduce the size of a constant, we will do that too. */
11290 {
11292 /* < C is equivalent to <= (C - 1) */
11294 {
11297 /* ... fall through to LE case below. */
11298 }
11299 else
11303 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11305 {
11308 }
11310 /* If we are doing a <= 0 comparison on a value known to have
11311 a zero sign bit, we can replace this with == 0. */
11321 /* >= C is equivalent to > (C - 1). */
11323 {
11326 /* ... fall through to GT below. */
11327 }
11328 else
11332 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11334 {
11337 }
11339 /* If we are doing a > 0 comparison on a value known to have
11340 a zero sign bit, we can replace this with != 0. */
11350 /* < C is equivalent to <= (C - 1). */
11352 {
11355 /* ... fall through ... */
11356 }
11357 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11361 {
11365 }
11366 else
11370 /* unsigned <= 0 is equivalent to == 0 */
11373 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11377 {
11380 }
11384 /* >= C is equivalent to > (C - 1). */
11386 {
11389 /* ... fall through ... */
11390 }
11392 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11396 {
11400 }
11401 else
11405 /* unsigned > 0 is equivalent to != 0 */
11408 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11412 {
11415 }
11420 }
11424 }
11425 \f
11426 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11427 comparison code that will be tested.
11429 The result is a possibly different comparison code to use. *POP0 and
11430 *POP1 may be updated.
11432 It is possible that we might detect that a comparison is either always
11433 true or always false. However, we do not perform general constant
11434 folding in combine, so this knowledge isn't useful. Such tautologies
11435 should have been detected earlier. Hence we ignore all such cases. */
11437 static enum rtx_code
11439 {
11446 /* Try a few ways of applying the same transformation to both operands. */
11448 {
11449 #ifndef WORD_REGISTER_OPERATIONS
11450 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11451 so check specially. */
11466 - (GET_MODE_PRECISION
11468 {
11471 }
11472 #endif
11474 /* If both operands are the same constant shift, see if we can ignore the
11475 shift. We can if the shift is a rotate or if the bits shifted out of
11476 this shift are known to be zero for both inputs and if the type of
11477 comparison is compatible with the shift. */
11490 {
11503 else
11505 }
11507 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11508 SUBREGs are of the same mode, and, in both cases, the AND would
11509 be redundant if the comparison was done in the narrower mode,
11510 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11511 and the operand's possibly nonzero bits are 0xffffff01; in that case
11512 if we only care about QImode, we don't need the AND). This case
11513 occurs if the output mode of an scc insn is not SImode and
11514 STORE_FLAG_VALUE == 1 (e.g., the 386).
11516 Similarly, check for a case where the AND's are ZERO_EXTEND
11517 operations from some narrower mode even though a SUBREG is not
11518 present. */
11523 {
11540 {
11544 /* The resulting comparison is always unsigned since we masked
11545 off the original sign bit. */
11549 }
11556 {
11562 }
11566 }
11568 /* If both operands are NOT, we can strip off the outer operation
11569 and adjust the comparison code for swapped operands; similarly for
11570 NEG, except that this must be an equality comparison. */
11576 else
11578 }
11580 /* If the first operand is a constant, swap the operands and adjust the
11581 comparison code appropriately, but don't do this if the second operand
11582 is already a constant integer. */
11584 {
11587 }
11589 /* We now enter a loop during which we will try to simplify the comparison.
11590 For the most part, we only are concerned with comparisons with zero,
11591 but some things may really be comparisons with zero but not start
11592 out looking that way. */
11595 {
11602 HOST_WIDE_INT const_op;
11604 /* We only want to handle integral modes. This catches VOIDmode,
11605 CCmode, and the floating-point modes. An exception is that we
11606 can handle VOIDmode if OP0 is a COMPARE or a comparison
11607 operation. */
11614 /* Try to simplify the compare to constant, possibly changing the
11615 comparison op, and/or changing op1 to zero. */
11619 /* Compute some predicates to simplify code below. */
11626 /* If this is a sign bit comparison and we can do arithmetic in
11627 MODE, say that we will only be needing the sign bit of OP0. */
11634 /* Now try cases based on the opcode of OP0. If none of the cases
11635 does a "continue", we exit this loop immediately after the
11636 switch. */
11639 {
11641 /* If we are extracting a single bit from a variable position in
11642 a constant that has only a single bit set and are comparing it
11643 with zero, we can convert this into an equality comparison
11644 between the position and the location of the single bit. */
11645 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11646 have already reduced the shift count modulo the word size. */
11652 {
11660 /* Result is nonzero iff shift count is equal to I. */
11663 }
11665 /* ... fall through ... */
11670 {
11673 }
11677 /* If testing for equality, we can take the NOT of the constant. */
11680 {
11684 }
11686 /* If just looking at the sign bit, reverse the sense of the
11687 comparison. */
11689 {
11693 }
11697 /* If testing for equality, we can take the NEG of the constant. */
11700 {
11704 }
11706 /* The remaining cases only apply to comparisons with zero. */
11710 /* When X is ABS or is known positive,
11711 (neg X) is < 0 if and only if X != 0. */
11719 {
11723 }
11725 /* If we have NEG of something whose two high-order bits are the
11726 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11728 {
11732 }
11736 /* If we are testing equality and our count is a constant, we
11737 can perform the inverse operation on our RHS. */
11741 {
11745 }
11747 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11748 a particular bit. Convert it to an AND of a constant of that
11749 bit. This will be converted into a ZERO_EXTRACT. */
11753 {
11760 }
11762 /* Fall through. */
11765 /* ABS is ignorable inside an equality comparison with zero. */
11767 {
11770 }
11774 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11775 (compare FOO CONST) if CONST fits in FOO's mode and we
11776 are either testing inequality or have an unsigned
11777 comparison with ZERO_EXTEND or a signed comparison with
11778 SIGN_EXTEND. But don't do it if we don't have a compare
11779 insn of the given mode, since we'd have to revert it
11780 later on, and then we wouldn't know whether to sign- or
11781 zero-extend. */
11784 && ! unsigned_comparison_p
11788 {
11791 }
11795 /* Check for the case where we are comparing A - C1 with C2, that is
11797 (subreg:MODE (plus (A) (-C1))) op (C2)
11799 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11800 comparison in the wider mode. One of the following two conditions
11801 must be true in order for this to be valid:
11803 1. The mode extension results in the same bit pattern being added
11804 on both sides and the comparison is equality or unsigned. As
11805 C2 has been truncated to fit in MODE, the pattern can only be
11806 all 0s or all 1s.
11808 2. The mode extension results in the sign bit being copied on
11809 each side.
11811 The difficulty here is that we have predicates for A but not for
11812 (A - C1) so we need to check that C1 is within proper bounds so
11813 as to perturbate A as little as possible. */
11820 {
11829 /* (A - C1) zero-extends if it is positive and sign-extends
11830 if it is negative, C2 both zero- and sign-extends. */
11834 /* (A - C1) sign-extends if it is positive and 1-extends
11835 if it is negative, C2 both sign- and 1-extends. */
11842 /* (A - C1) always sign-extends, like C2. */
11846 {
11849 }
11850 }
11852 /* If the inner mode is narrower and we are extracting the low part,
11853 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11857 else
11860 /* ... fall through ... */
11870 {
11873 }
11877 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11878 this for equality comparisons due to pathological cases involving
11879 overflows. */
11883 {
11887 }
11889 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11892 {
11896 }
11900 /* We used to optimize signed comparisons against zero, but that
11901 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11902 arrive here as equality comparisons, or (GEU, LTU) are
11903 optimized away. No need to special-case them. */
11905 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11906 (eq B (minus A C)), whichever simplifies. We can only do
11907 this for equality comparisons due to pathological cases involving
11908 overflows. */
11912 {
11916 }
11921 {
11925 }
11927 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11928 of bits in X minus 1, is one iff X > 0. */
11933 {
11937 }
11941 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11942 if C is zero or B is a constant. */
11946 {
11950 }
11958 /* We can't do anything if OP0 is a condition code value, rather
11959 than an actual data value. */
11965 /* Get the two operands being compared. */
11968 else
11971 /* Check for the cases where we simply want the result of the
11972 earlier test or the opposite of that result. */
11976 {
11980 else
11984 {
11989 }
11990 }
11994 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11995 iff X <= 0. */
11999 {
12003 }
12007 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12008 will be converted to a ZERO_EXTRACT later. */
12012 {
12017 }
12019 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12020 zero and X is a comparison and C1 and C2 describe only bits set
12021 in STORE_FLAG_VALUE, we can compare with X. */
12029 {
12036 {
12039 }
12040 }
12042 /* If we are doing an equality comparison of an AND of a bit equal
12043 to the sign bit, replace this with a LT or GE comparison of
12044 the underlying value. */
12051 {
12055 }
12057 /* If this AND operation is really a ZERO_EXTEND from a narrower
12058 mode, the constant fits within that mode, and this is either an
12059 equality or unsigned comparison, try to do this comparison in
12060 the narrower mode.
12062 Note that in:
12064 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12065 -> (ne:DI (reg:SI 4) (const_int 0))
12067 unless TRULY_NOOP_TRUNCATION allows it or the register is
12068 known to hold a value of the required mode the
12069 transformation is invalid. */
12080 {
12083 }
12085 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
12086 fits in both M1 and M2 and the SUBREG is either paradoxical
12087 or represents the low part, permute the SUBREG and the AND
12088 and try again. */
12090 {
12093 /* Require an integral mode, to avoid creating something like
12094 (AND:SF ...). */
12096 /* It is unsafe to commute the AND into the SUBREG if the
12097 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12098 not defined. As originally written the upper bits
12099 have a defined value due to the AND operation.
12100 However, if we commute the AND inside the SUBREG then
12101 they no longer have defined values and the meaning of
12102 the code has been changed. */
12104 #ifdef WORD_REGISTER_OPERATIONS
12107 #endif
12117 {
12123 }
12124 }
12126 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12130 {
12135 }
12137 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12138 (eq (and (lshiftrt X) 1) 0).
12139 Also handle the case where (not X) is expressed using xor. */
12143 {
12155 {
12156 op0
12161 }
12162 }
12166 /* If we have (compare (ashift FOO N) (const_int C)) and
12167 the high order N bits of FOO (N+1 if an inequality comparison)
12168 are known to be zero, we can do this by comparing FOO with C
12169 shifted right N bits so long as the low-order N bits of C are
12170 zero. */
12182 {
12183 /* We must perform a logical shift, not an arithmetic one,
12184 as we want the top N bits of C to be zero. */
12191 }
12193 /* If we are doing a sign bit comparison, it means we are testing
12194 a particular bit. Convert it to the appropriate AND. */
12197 {
12204 }
12206 /* If this an equality comparison with zero and we are shifting
12207 the low bit to the sign bit, we can convert this to an AND of the
12208 low-order bit. */
12212 {
12215 }
12219 /* If this is an equality comparison with zero, we can do this
12220 as a logical shift, which might be much simpler. */
12223 {
12228 }
12230 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12231 do the comparison in a narrower mode. */
12241 {
12244 }
12246 /* Likewise if OP0 is a PLUS of a sign extension with a
12247 constant, which is usually represented with the PLUS
12248 between the shifts. */
12260 {
12268 new_const);
12270 }
12272 /* ... fall through ... */
12274 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12275 the low order N bits of FOO are known to be zero, we can do this
12276 by comparing FOO with C shifted left N bits so long as no
12277 overflow occurs. Even if the low order N bits of FOO aren't known
12278 to be zero, if the comparison is >= or < we can use the same
12279 optimization and for > or <= by setting all the low
12280 order N bits in the comparison constant. */
12291 {
12292 unsigned HOST_WIDE_INT low_bits
12297 {
12298 /* If the shift was logical, then we must make the condition
12299 unsigned. */
12307 const_op
12312 }
12313 }
12315 /* If we are using this shift to extract just the sign bit, we
12316 can replace this with an LT or GE comparison. */
12321 {
12325 }
12330 }
12333 }
12335 /* Now make any compound operations involved in this comparison. Then,
12336 check for an outmost SUBREG on OP0 that is not doing anything or is
12337 paradoxical. The latter transformation must only be performed when
12338 it is known that the "extra" bits will be the same in op0 and op1 or
12339 that they don't matter. There are three cases to consider:
12341 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12342 care bits and we can assume they have any convenient value. So
12343 making the transformation is safe.
12345 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12346 In this case the upper bits of op0 are undefined. We should not make
12347 the simplification in that case as we do not know the contents of
12348 those bits.
12350 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12351 UNKNOWN. In that case we know those bits are zeros or ones. We must
12352 also be sure that they are the same as the upper bits of op1.
12354 We can never remove a SUBREG for a non-equality comparison because
12355 the sign bit is in a different place in the underlying object. */
12364 {
12366 {
12367 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12368 implemented. */
12370 {
12373 }
12374 }
12380 {
12386 }
12387 }
12389 /* We now do the opposite procedure: Some machines don't have compare
12390 insns in all modes. If OP0's mode is an integer mode smaller than a
12391 word and we can't do a compare in that mode, see if there is a larger
12392 mode for which we can do the compare. There are a number of cases in
12393 which we can use the wider mode. */
12403 {
12406 /* If this is a test for negative, we can make an explicit
12407 test of the sign bit. Test this first so we can use
12408 a paradoxical subreg to extend OP0. */
12412 {
12413 unsigned HOST_WIDE_INT sign
12420 }
12422 /* If the only nonzero bits in OP0 and OP1 are those in the
12423 narrower mode and this is an equality or unsigned comparison,
12424 we can use the wider mode. Similarly for sign-extended
12425 values, in which case it is true for all comparisons. */
12442 {
12443 /* If OP0 is an AND and we don't have an AND in MODE either,
12444 make a new AND in the proper mode. */
12452 else
12453 {
12455 {
12458 }
12459 else
12460 {
12463 }
12465 }
12466 }
12467 }
12469 /* We may have changed the comparison operands. Re-canonicalize. */
12471 {
12474 }
12476 /* If this machine only supports a subset of valid comparisons, see if we
12477 can convert an unsupported one into a supported one. */
12484 }
12485 \f
12486 /* Utility function for record_value_for_reg. Count number of
12487 rtxs in X. */
12488 static int
12490 {
12497 {
12517 }
12528 }
12529 \f
12530 /* Utility function for following routine. Called when X is part of a value
12531 being stored into last_set_value. Sets last_set_table_tick
12532 for each register mentioned. Similar to mention_regs in cse.c */
12534 static void
12536 {
12542 {
12548 {
12551 }
12554 }
12558 {
12559 /* Check for identical subexpressions. If x contains
12560 identical subexpression we only have to traverse one of
12561 them. */
12563 {
12564 /* Note that at this point x1 has already been
12565 processed. */
12569 /* If x0 and x1 are identical then there is no need to
12570 process x0. */
12574 /* If x0 is identical to a subexpression of x1 then while
12575 processing x1, x0 has already been processed. Thus we
12576 are done with x. */
12581 /* If x1 is identical to a subexpression of x0 then we
12582 still have to process the rest of x0. */
12585 {
12588 }
12589 }
12592 }
12596 }
12598 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12599 are saying that the register is clobbered and we no longer know its
12600 value. If INSN is zero, don't update reg_stat[].last_set; this is
12601 only permitted with VALUE also zero and is used to invalidate the
12602 register. */
12604 static void
12606 {
12612 /* If VALUE contains REG and we have a previous value for REG, substitute
12613 the previous value. */
12615 {
12616 rtx tem;
12618 /* Set things up so get_last_value is allowed to see anything set up to
12619 our insn. */
12623 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12624 it isn't going to be useful and will take a lot of time to process,
12625 so just use the CLOBBER. */
12628 {
12634 {
12635 /* If there are two or more occurrences of REG in VALUE,
12636 prevent the value from growing too much. */
12639 }
12642 }
12643 }
12645 /* For each register modified, show we don't know its value, that
12646 we don't know about its bitwise content, that its value has been
12647 updated, and that we don't know the location of the death of the
12648 register. */
12650 {
12662 }
12664 /* Mark registers that are being referenced in this value. */
12668 /* Now update the status of each register being set.
12669 If someone is using this register in this block, set this register
12670 to invalid since we will get confused between the two lives in this
12671 basic block. This makes using this register always invalid. In cse, we
12672 scan the table to invalidate all entries using this register, but this
12673 is too much work for us. */
12676 {
12682 else
12684 }
12686 /* The value being assigned might refer to X (like in "x++;"). In that
12687 case, we must replace it with (clobber (const_int 0)) to prevent
12688 infinite loops. */
12691 {
12695 }
12697 /* For the main register being modified, update the value, the mode, the
12698 nonzero bits, and the number of sign bit copies. */
12703 {
12711 rsp->last_set_sign_bit_copies
12713 }
12714 }
12716 /* Called via note_stores from record_dead_and_set_regs to handle one
12717 SET or CLOBBER in an insn. DATA is the instruction in which the
12718 set is occurring. */
12720 static void
12722 {
12729 {
12733 }
12736 {
12737 /* If we are setting the whole register, we know its value. Otherwise
12738 show that we don't know the value. We can handle SUBREG in
12739 some cases. */
12750 else
12752 }
12754 /* Ignore pushes, they clobber nothing. */
12757 }
12759 /* Update the records of when each REG was most recently set or killed
12760 for the things done by INSN. This is the last thing done in processing
12761 INSN in the combiner loop.
12763 We update reg_stat[], in particular fields last_set, last_set_value,
12764 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12765 last_death, and also the similar information mem_last_set (which insn
12766 most recently modified memory) and last_call_luid (which insn was the
12767 most recent subroutine call). */
12769 static void
12771 {
12772 rtx link;
12776 {
12779 {
12784 {
12789 }
12790 }
12793 }
12796 {
12797 hard_reg_set_iterator hrsi;
12799 {
12811 }
12815 /* We can't combine into a call pattern. Remember, though, that
12816 the return value register is set at this LUID. We could
12817 still replace a register with the return value from the
12818 wrong subroutine call! */
12820 }
12821 else
12823 }
12825 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12826 register present in the SUBREG, so for each such SUBREG go back and
12827 adjust nonzero and sign bit information of the registers that are
12828 known to have some zero/sign bits set.
12830 This is needed because when combine blows the SUBREGs away, the
12831 information on zero/sign bits is lost and further combines can be
12832 missed because of that. */
12834 static void
12836 {
12838 rtx set;
12846 {
12855 {
12858 }
12862 {
12865 }
12868 {
12871 }
12872 else
12874 }
12875 }
12877 /* Check if X, a register, is known to contain a value already
12878 truncated to MODE. In this case we can use a subreg to refer to
12879 the truncated value even though in the generic case we would need
12880 an explicit truncation. */
12882 static bool
12884 {
12896 }
12898 /* If X is a hard reg or a subreg record the mode that the register is
12899 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12900 to turn a truncate into a subreg using this information. Return true
12901 if traversing X is complete. */
12903 static bool
12905 {
12906 machine_mode truncated_mode;
12910 {
12921 }
12922 /* ??? For hard-regs we now record everything. We might be able to
12923 optimize this using last_set_mode. */
12926 else
12934 {
12937 }
12940 }
12942 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12943 the modes they are used in. This can help truning TRUNCATEs into
12944 SUBREGs. */
12946 static void
12948 {
12953 }
12955 /* Scan X for promoted SUBREGs. For each one found,
12956 note what it implies to the registers used in it. */
12958 static void
12960 {
12965 else
12966 {
12972 {
12982 }
12983 }
12984 }
12985 \f
12986 /* Verify that all the registers and memory references mentioned in *LOC are
12987 still valid. *LOC was part of a value set in INSN when label_tick was
12988 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12989 the invalid references with (clobber (const_int 0)) and return 1. This
12990 replacement is useful because we often can get useful information about
12991 the form of a value (e.g., if it was produced by a shift that always
12992 produces -1 or 0) even though we don't know exactly what registers it
12993 was produced from. */
12995 static int
12997 {
13004 {
13010 {
13013 /* If this is a pseudo-register that was only set once and not
13014 live at the beginning of the function, it is always valid. */
13018 && (!REGNO_REG_SET_P
13020 regno)))
13022 {
13026 }
13027 }
13030 }
13031 /* If this is a memory reference, make sure that there were no stores after
13032 it that might have clobbered the value. We don't have alias info, so we
13033 assume any store invalidates it. Moreover, we only have local UIDs, so
13034 we also assume that there were stores in the intervening basic blocks. */
13037 {
13041 }
13044 {
13046 {
13047 /* Check for identical subexpressions. If x contains
13048 identical subexpression we only have to traverse one of
13049 them. */
13051 {
13052 /* Note that at this point x0 has already been checked
13053 and found valid. */
13057 /* If x0 and x1 are identical then x is also valid. */
13061 /* If x1 is identical to a subexpression of x0 then
13062 while checking x0, x1 has already been checked. Thus
13063 it is valid and so as x. */
13068 /* If x0 is identical to a subexpression of x1 then x is
13069 valid iff the rest of x1 is valid. */
13072 return
13076 }
13081 }
13087 }
13089 /* If we haven't found a reason for it to be invalid, it is valid. */
13091 }
13093 /* Get the last value assigned to X, if known. Some registers
13094 in the value may be replaced with (clobber (const_int 0)) if their value
13095 is known longer known reliably. */
13097 static rtx
13099 {
13101 rtx value;
13104 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13105 then convert it to the desired mode. If this is a paradoxical SUBREG,
13106 we cannot predict what values the "extra" bits might have. */
13120 /* If we don't have a value, or if it isn't for this basic block and
13121 it's either a hard register, set more than once, or it's a live
13122 at the beginning of the function, return 0.
13124 Because if it's not live at the beginning of the function then the reg
13125 is always set before being used (is never used without being set).
13126 And, if it's set only once, and it's always set before use, then all
13127 uses must have the same last value, even if it's not from this basic
13128 block. */
13135 || REGNO_REG_SET_P
13139 /* If the value was set in a later insn than the ones we are processing,
13140 we can't use it even if the register was only set once. */
13145 /* If the value has all its registers valid, return it. */
13149 /* Otherwise, make a copy and replace any invalid register with
13150 (clobber (const_int 0)). If that fails for some reason, return 0. */
13157 }
13158 \f
13159 /* Return nonzero if expression X refers to a REG or to memory
13160 that is set in an instruction more recent than FROM_LUID. */
13162 static int
13164 {
13170 {
13174 #ifdef PUSH_ROUNDING
13175 /* Don't allow uses of the stack pointer to be moved,
13176 because we don't know whether the move crosses a push insn. */
13179 #endif
13181 {
13187 }
13189 }
13197 {
13199 {
13204 }
13208 }
13210 }
13211 \f
13212 /* Define three variables used for communication between the following
13213 routines. */
13218 /* Function called via note_stores from reg_dead_at_p.
13220 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13221 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13223 static void
13225 {
13235 }
13237 /* Return nonzero if REG is known to be dead at INSN.
13239 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13240 referencing REG, it is dead. If we hit a SET referencing REG, it is
13241 live. Otherwise, see if it is live or dead at the start of the basic
13242 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13243 must be assumed to be always live. */
13245 static int
13247 {
13248 basic_block block;
13251 /* Set variables for reg_dead_at_p_1. */
13257 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13258 we allow the machine description to decide whether use-and-clobber
13259 patterns are OK. */
13261 {
13265 }
13267 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13268 beginning of basic block. */
13271 {
13273 {
13283 }
13289 }
13291 /* Look at live-in sets for the basic block that we were in. */
13297 }
13298 \f
13299 /* Note hard registers in X that are used. */
13301 static void
13303 {
13309 {
13313 CASE_CONST_ANY:
13318 /* CC0 must die in the insn after it is set, so we don't need to take
13319 special note of it here. */
13324 /* If we are clobbering a MEM, mark any hard registers inside the
13325 address as used. */
13332 /* A hard reg in a wide mode may really be multiple registers.
13333 If so, mark all of them just like the first. */
13335 {
13336 /* None of this applies to the stack, frame or arg pointers. */
13338 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
13340 #endif
13341 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
13343 #endif
13348 }
13352 {
13353 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13354 the address. */
13366 }
13371 }
13373 /* Recursively scan the operands of this expression. */
13375 {
13379 {
13383 {
13388 }
13389 }
13390 }
13391 }
13392 \f
13393 /* Remove register number REGNO from the dead registers list of INSN.
13395 Return the note used to record the death, if there was one. */
13397 rtx
13399 {
13406 }
13408 /* For each register (hardware or pseudo) used within expression X, if its
13409 death is in an instruction with luid between FROM_LUID (inclusive) and
13410 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13411 list headed by PNOTES.
13413 That said, don't move registers killed by maybe_kill_insn.
13415 This is done when X is being merged by combination into TO_INSN. These
13416 notes will then be distributed as needed. */
13418 static void
13421 {
13427 {
13431 /* Don't move the register if it gets killed in between from and to. */
13440 {
13443 /* It is possible for the call above to return 0. This can occur
13444 when last_death points to I2 or I1 that we combined with.
13445 In that case make a new note.
13447 We must also check for the case where X is a hard register
13448 and NOTE is a death note for a range of hard registers
13449 including X. In that case, we must put REG_DEAD notes for
13450 the remaining registers in place of NOTE. */
13455 {
13464 }
13466 /* If we didn't find any note, or if we found a REG_DEAD note that
13467 covers only part of the given reg, and we have a multi-reg hard
13468 register, then to be safe we must check for REG_DEAD notes
13469 for each register other than the first. They could have
13470 their own REG_DEAD notes lying around. */
13477 {
13484 else
13490 }
13493 {
13496 }
13497 else
13499 }
13502 }
13505 {
13510 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13511 that accesses one word of a multi-word item, some
13512 piece of everything register in the expression is used by
13513 this insn, so remove any old death. */
13514 /* ??? So why do we test for equality of the sizes? */
13523 {
13526 }
13528 /* If this is some other SUBREG, we know it replaces the entire
13529 value, so use that as the destination. */
13533 /* If this is a MEM, adjust deaths of anything used in the address.
13534 For a REG (the only other possibility), the entire value is
13535 being replaced so the old value is not used in this insn. */
13541 }
13550 {
13552 {
13557 }
13560 }
13561 }
13562 \f
13563 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13564 pattern of an insn. X must be a REG. */
13566 static int
13568 {
13572 {
13574 rtx target;
13581 else
13598 }
13606 }
13607 \f
13608 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13609 as appropriate. I3 and I2 are the insns resulting from the combination
13610 insns including FROM (I2 may be zero).
13612 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13613 not need REG_DEAD notes because they are being substituted for. This
13614 saves searching in the most common cases.
13616 Each note in the list is either ignored or placed on some insns, depending
13617 on the type of note. */
13619 static void
13622 {
13624 rtx tem_note;
13628 {
13633 {
13636 /* Doesn't matter much where we put this, as long as it's somewhere.
13637 It is preferable to keep these notes on branches, which is most
13638 likely to be i3. */
13645 else
13646 {
13649 }
13653 /* These notes must remain with the call or trapping instruction. */
13658 else
13659 {
13665 /* ??? Otherwise assume we've combined things such that we
13666 can now prove that the instructions can't trap. Drop the
13667 note in this case. */
13668 }
13672 /* ??? How to distribute between i3-i1. Assume i3 contains the
13673 entire adjustment. Assert i3 contains at least some adjust. */
13675 {
13677 /* fixup_args_size_notes looks at REG_NORETURN note,
13678 so ensure the note is placed there first. */
13680 {
13684 {
13690 }
13691 }
13693 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13694 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13697 && !ACCUMULATE_OUTGOING_ARGS
13699 }
13706 /* These notes must remain with the call. It should not be
13707 possible for both I2 and I3 to be a call. */
13710 else
13711 {
13714 }
13718 /* Any clobbers for i3 may still exist, and so we must process
13719 REG_UNUSED notes from that insn.
13721 Any clobbers from i2 or i1 can only exist if they were added by
13722 recog_for_combine. In that case, recog_for_combine created the
13723 necessary REG_UNUSED notes. Trying to keep any original
13724 REG_UNUSED notes from these insns can cause incorrect output
13725 if it is for the same register as the original i3 dest.
13726 In that case, we will notice that the register is set in i3,
13727 and then add a REG_UNUSED note for the destination of i3, which
13728 is wrong. However, it is possible to have REG_UNUSED notes from
13729 i2 or i1 for register which were both used and clobbered, so
13730 we keep notes from i2 or i1 if they will turn into REG_DEAD
13731 notes. */
13733 /* If this register is set or clobbered in I3, put the note there
13734 unless there is one already. */
13736 {
13744 }
13745 /* Otherwise, if this register is used by I3, then this register
13746 now dies here, so we must put a REG_DEAD note here unless there
13747 is one already. */
13753 {
13756 }
13762 /* These notes say something about results of an insn. We can
13763 only support them if they used to be on I3 in which case they
13764 remain on I3. Otherwise they are ignored.
13766 If the note refers to an expression that is not a constant, we
13767 must also ignore the note since we cannot tell whether the
13768 equivalence is still true. It might be possible to do
13769 slightly better than this (we only have a problem if I2DEST
13770 or I1DEST is present in the expression), but it doesn't
13771 seem worth the trouble. */
13779 /* These notes say something about how a register is used. They must
13780 be present on any use of the register in I2 or I3. */
13785 {
13788 else
13790 }
13795 /* This can show up in several ways -- either directly in the
13796 pattern, or hidden off in the constant pool with (or without?)
13797 a REG_EQUAL note. */
13798 /* ??? Ignore the without-reg_equal-note problem for now. */
13810 {
13813 else
13815 }
13817 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13818 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13819 there. */
13824 {
13831 }
13837 {
13845 }
13849 /* This note says something about the value of a register prior
13850 to the execution of an insn. It is too much trouble to see
13851 if the note is still correct in all situations. It is better
13852 to simply delete it. */
13856 /* If we replaced the right hand side of FROM_INSN with a
13857 REG_EQUAL note, the original use of the dying register
13858 will not have been combined into I3 and I2. In such cases,
13859 FROM_INSN is guaranteed to be the first of the combined
13860 instructions, so we simply need to search back before
13861 FROM_INSN for the previous use or set of this register,
13862 then alter the notes there appropriately.
13864 If the register is used as an input in I3, it dies there.
13865 Similarly for I2, if it is nonzero and adjacent to I3.
13867 If the register is not used as an input in either I3 or I2
13868 and it is not one of the registers we were supposed to eliminate,
13869 there are two possibilities. We might have a non-adjacent I2
13870 or we might have somehow eliminated an additional register
13871 from a computation. For example, we might have had A & B where
13872 we discover that B will always be zero. In this case we will
13873 eliminate the reference to A.
13875 In both cases, we must search to see if we can find a previous
13876 use of A and put the death note there. */
13882 else
13883 {
13894 && !(i2mod
13896 i2mod_old_rhs)))
13901 /* If the new I2 sets the same register that is marked dead
13902 in the note, the note now should not be put on I2, as the
13903 note refers to a previous incarnation of the reg. */
13906 }
13909 {
13913 {
13915 {
13919 }
13921 /* If the register is being set at TEM_INSN, see if that is all
13922 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13923 into a REG_UNUSED note instead. Don't delete sets to
13924 global register vars. */
13928 {
13939 ;
13941 /* Verify that it was the set, and not a clobber that
13942 modified the register.
13944 CC0 targets must be careful to maintain setter/user
13945 pairs. If we cannot delete the setter due to side
13946 effects, mark the user with an UNUSED note instead
13947 of deleting it. */
13951 #if HAVE_cc0
13955 #endif
13956 )
13957 {
13958 /* Move the notes and links of TEM_INSN elsewhere.
13959 This might delete other dead insns recursively.
13960 First set the pattern to something that won't use
13961 any register. */
13975 /* Delete the setter too. */
13977 {
13990 }
13991 }
13992 else
13993 {
13996 /* If there isn't already a REG_UNUSED note, put one
13997 here. Do not place a REG_DEAD note, even if
13998 the register is also used here; that would not
13999 match the algorithm used in lifetime analysis
14000 and can cause the consistency check in the
14001 scheduler to fail. */
14006 }
14007 }
14011 {
14014 /* If we are doing a 3->2 combination, and we have a
14015 register which formerly died in i3 and was not used
14016 by i2, which now no longer dies in i3 and is used in
14017 i2 but does not die in i2, and place is between i2
14018 and i3, then we may need to move a link from place to
14019 i2. */
14021 && from_insn
14024 {
14028 }
14030 }
14034 }
14036 }
14038 /* If the register is set or already dead at PLACE, we needn't do
14039 anything with this note if it is still a REG_DEAD note.
14040 We check here if it is set at all, not if is it totally replaced,
14041 which is what `dead_or_set_p' checks, so also check for it being
14042 set partially. */
14045 {
14051 {
14052 /* Unless the register previously died in PLACE, clear
14053 last_death. [I no longer understand why this is
14054 being done.] */
14058 }
14059 else
14062 /* If this is a death note for a hard reg that is occupying
14063 multiple registers, ensure that we are still using all
14064 parts of the object. If we find a piece of the object
14065 that is unused, we must arrange for an appropriate REG_DEAD
14066 note to be added for it. However, we can't just emit a USE
14067 and tag the note to it, since the register might actually
14068 be dead; so we recourse, and the recursive call then finds
14069 the previous insn that used this register. */
14072 {
14081 {
14084 }
14087 {
14088 /* Put only REG_DEAD notes for pieces that are
14089 not already dead or set. */
14093 {
14100 {
14102 NULL_RTX);
14106 NULL_RTX);
14107 }
14112 {
14114 {
14118 }
14122 {
14125 }
14126 }
14127 }
14130 }
14131 }
14132 }
14136 /* Any other notes should not be present at this point in the
14137 compilation. */
14139 }
14142 {
14145 }
14149 }
14150 }
14151 \f
14152 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14153 I3, I2, and I1 to new locations. This is also called to add a link
14154 pointing at I3 when I3's destination is changed. */
14156 static void
14158 {
14162 {
14169 /* If the insn that this link points to is a NOTE, ignore it. */
14178 {
14181 {
14197 }
14200 }
14201 else
14211 /* A LOG_LINK is defined as being placed on the first insn that uses
14212 a register and points to the insn that sets the register. Start
14213 searching at the next insn after the target of the link and stop
14214 when we reach a set of the register or the end of the basic block.
14216 Note that this correctly handles the link that used to point from
14217 I3 to I2. Also note that not much searching is typically done here
14218 since most links don't point very far away. */
14227 {
14231 }
14234 {
14237 }
14241 /* If we found a place to put the link, place it there unless there
14242 is already a link to the same insn as LINK at that point. */
14245 {
14253 {
14257 /* Set added_links_insn to the earliest insn we added a
14258 link to. */
14262 }
14263 }
14264 }
14265 }
14266 \f
14267 /* Check for any register or memory mentioned in EQUIV that is not
14268 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14269 of EXPR where some registers may have been replaced by constants. */
14271 static bool
14273 {
14276 {
14281 }
14283 }
14284 \f
14285 DEBUG_FUNCTION void
14287 {
14288 fprintf
14290 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14292 }
14294 void
14296 {
14297 fprintf
14299 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14301 }
14302 \f
14303 /* Try combining insns through substitution. */
14304 static unsigned int
14306 {
14316 rebuild_jump_labels_after_combine
14319 /* Combining insns may have turned an indirect jump into a
14320 direct jump. Rebuild the JUMP_LABEL fields of jumping
14321 instructions. */
14323 {
14328 }
14332 }
14337 {
14347 };
14350 {
14354 {}
14356 /* opt_pass methods: */
14359 {
14361 }
14367 rtl_opt_pass *
14369 {
14371 }