1 /* Expand the basic unary and binary arithmetic operations, for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "coretypes.h"
29 /* Include insn-config.h before expr.h so that HAVE_conditional_move
30 is properly defined. */
31 #include "insn-config.h"
45 #include "basic-block.h"
48 /* Each optab contains info on how this target machine
49 can perform a particular operation
50 for all sizes and kinds of operands.
52 The operation to be performed is often specified
53 by passing one of these optabs as an argument.
55 See expr.h for documentation of these optabs. */
57 optab optab_table
[OTI_MAX
];
59 rtx libfunc_table
[LTI_MAX
];
61 /* Tables of patterns for converting one mode to another. */
62 convert_optab convert_optab_table
[COI_MAX
];
64 /* Contains the optab used for each rtx code. */
65 optab code_to_optab
[NUM_RTX_CODE
+ 1];
67 /* Indexed by the rtx-code for a conditional (eg. EQ, LT,...)
68 gives the gen_function to make a branch to test that condition. */
70 rtxfun bcc_gen_fctn
[NUM_RTX_CODE
];
72 /* Indexed by the rtx-code for a conditional (eg. EQ, LT,...)
73 gives the insn code to make a store-condition insn
74 to test that condition. */
76 enum insn_code setcc_gen_code
[NUM_RTX_CODE
];
78 #ifdef HAVE_conditional_move
79 /* Indexed by the machine mode, gives the insn code to make a conditional
80 move insn. This is not indexed by the rtx-code like bcc_gen_fctn and
81 setcc_gen_code to cut down on the number of named patterns. Consider a day
82 when a lot more rtx codes are conditional (eg: for the ARM). */
84 enum insn_code movcc_gen_code
[NUM_MACHINE_MODES
];
87 /* Indexed by the machine mode, gives the insn code for vector conditional
90 enum insn_code vcond_gen_code
[NUM_MACHINE_MODES
];
91 enum insn_code vcondu_gen_code
[NUM_MACHINE_MODES
];
93 /* The insn generating function can not take an rtx_code argument.
94 TRAP_RTX is used as an rtx argument. Its code is replaced with
95 the code to be used in the trap insn and all other fields are ignored. */
96 static GTY(()) rtx trap_rtx
;
98 static int add_equal_note (rtx
, rtx
, enum rtx_code
, rtx
, rtx
);
99 static rtx
widen_operand (rtx
, enum machine_mode
, enum machine_mode
, int,
101 static void prepare_cmp_insn (rtx
*, rtx
*, enum rtx_code
*, rtx
,
102 enum machine_mode
*, int *,
103 enum can_compare_purpose
);
104 static enum insn_code
can_fix_p (enum machine_mode
, enum machine_mode
, int,
106 static enum insn_code
can_float_p (enum machine_mode
, enum machine_mode
, int);
107 static optab
new_optab (void);
108 static convert_optab
new_convert_optab (void);
109 static inline optab
init_optab (enum rtx_code
);
110 static inline optab
init_optabv (enum rtx_code
);
111 static inline convert_optab
init_convert_optab (enum rtx_code
);
112 static void init_libfuncs (optab
, int, int, const char *, int);
113 static void init_integral_libfuncs (optab
, const char *, int);
114 static void init_floating_libfuncs (optab
, const char *, int);
115 static void init_interclass_conv_libfuncs (convert_optab
, const char *,
116 enum mode_class
, enum mode_class
);
117 static void init_intraclass_conv_libfuncs (convert_optab
, const char *,
118 enum mode_class
, bool);
119 static void emit_cmp_and_jump_insn_1 (rtx
, rtx
, enum machine_mode
,
120 enum rtx_code
, int, rtx
);
121 static void prepare_float_lib_cmp (rtx
*, rtx
*, enum rtx_code
*,
122 enum machine_mode
*, int *);
123 static rtx
widen_clz (enum machine_mode
, rtx
, rtx
);
124 static rtx
expand_parity (enum machine_mode
, rtx
, rtx
);
125 static enum rtx_code
get_rtx_code (enum tree_code
, bool);
126 static rtx
vector_compare_rtx (tree
, bool, enum insn_code
);
128 #ifndef HAVE_conditional_trap
129 #define HAVE_conditional_trap 0
130 #define gen_conditional_trap(a,b) (gcc_unreachable (), NULL_RTX)
133 /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to
134 the result of operation CODE applied to OP0 (and OP1 if it is a binary
137 If the last insn does not set TARGET, don't do anything, but return 1.
139 If a previous insn sets TARGET and TARGET is one of OP0 or OP1,
140 don't add the REG_EQUAL note but return 0. Our caller can then try
141 again, ensuring that TARGET is not one of the operands. */
144 add_equal_note (rtx insns
, rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
146 rtx last_insn
, insn
, set
;
149 gcc_assert (insns
&& INSN_P (insns
) && NEXT_INSN (insns
));
151 if (GET_RTX_CLASS (code
) != RTX_COMM_ARITH
152 && GET_RTX_CLASS (code
) != RTX_BIN_ARITH
153 && GET_RTX_CLASS (code
) != RTX_COMM_COMPARE
154 && GET_RTX_CLASS (code
) != RTX_COMPARE
155 && GET_RTX_CLASS (code
) != RTX_UNARY
)
158 if (GET_CODE (target
) == ZERO_EXTRACT
)
161 for (last_insn
= insns
;
162 NEXT_INSN (last_insn
) != NULL_RTX
;
163 last_insn
= NEXT_INSN (last_insn
))
166 set
= single_set (last_insn
);
170 if (! rtx_equal_p (SET_DEST (set
), target
)
171 /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */
172 && (GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
173 || ! rtx_equal_p (XEXP (SET_DEST (set
), 0), target
)))
176 /* If TARGET is in OP0 or OP1, check if anything in SEQ sets TARGET
177 besides the last insn. */
178 if (reg_overlap_mentioned_p (target
, op0
)
179 || (op1
&& reg_overlap_mentioned_p (target
, op1
)))
181 insn
= PREV_INSN (last_insn
);
182 while (insn
!= NULL_RTX
)
184 if (reg_set_p (target
, insn
))
187 insn
= PREV_INSN (insn
);
191 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
192 note
= gen_rtx_fmt_e (code
, GET_MODE (target
), copy_rtx (op0
));
194 note
= gen_rtx_fmt_ee (code
, GET_MODE (target
), copy_rtx (op0
), copy_rtx (op1
));
196 set_unique_reg_note (last_insn
, REG_EQUAL
, note
);
201 /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP
202 says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need
203 not actually do a sign-extend or zero-extend, but can leave the
204 higher-order bits of the result rtx undefined, for example, in the case
205 of logical operations, but not right shifts. */
208 widen_operand (rtx op
, enum machine_mode mode
, enum machine_mode oldmode
,
209 int unsignedp
, int no_extend
)
213 /* If we don't have to extend and this is a constant, return it. */
214 if (no_extend
&& GET_MODE (op
) == VOIDmode
)
217 /* If we must extend do so. If OP is a SUBREG for a promoted object, also
218 extend since it will be more efficient to do so unless the signedness of
219 a promoted object differs from our extension. */
221 || (GET_CODE (op
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (op
)
222 && SUBREG_PROMOTED_UNSIGNED_P (op
) == unsignedp
))
223 return convert_modes (mode
, oldmode
, op
, unsignedp
);
225 /* If MODE is no wider than a single word, we return a paradoxical
227 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
228 return gen_rtx_SUBREG (mode
, force_reg (GET_MODE (op
), op
), 0);
230 /* Otherwise, get an object of MODE, clobber it, and set the low-order
233 result
= gen_reg_rtx (mode
);
234 emit_insn (gen_rtx_CLOBBER (VOIDmode
, result
));
235 emit_move_insn (gen_lowpart (GET_MODE (op
), result
), op
);
239 /* Return the optab used for computing the operation given by
240 the tree code, CODE. This function is not always usable (for
241 example, it cannot give complete results for multiplication
242 or division) but probably ought to be relied on more widely
243 throughout the expander. */
245 optab_for_tree_code (enum tree_code code
, tree type
)
257 return one_cmpl_optab
;
266 return TYPE_UNSIGNED (type
) ? umod_optab
: smod_optab
;
274 return TYPE_UNSIGNED (type
) ? udiv_optab
: sdiv_optab
;
280 return TYPE_UNSIGNED (type
) ? lshr_optab
: ashr_optab
;
289 return TYPE_UNSIGNED (type
) ? umax_optab
: smax_optab
;
292 return TYPE_UNSIGNED (type
) ? umin_optab
: smin_optab
;
294 case REALIGN_LOAD_EXPR
:
295 return vec_realign_load_optab
;
298 return TYPE_UNSIGNED (type
) ? reduc_umax_optab
: reduc_smax_optab
;
301 return TYPE_UNSIGNED (type
) ? reduc_umin_optab
: reduc_smin_optab
;
303 case REDUC_PLUS_EXPR
:
304 return TYPE_UNSIGNED (type
) ? reduc_uplus_optab
: reduc_splus_optab
;
306 case VEC_LSHIFT_EXPR
:
307 return vec_shl_optab
;
309 case VEC_RSHIFT_EXPR
:
310 return vec_shr_optab
;
316 trapv
= flag_trapv
&& INTEGRAL_TYPE_P (type
) && !TYPE_UNSIGNED (type
);
320 return trapv
? addv_optab
: add_optab
;
323 return trapv
? subv_optab
: sub_optab
;
326 return trapv
? smulv_optab
: smul_optab
;
329 return trapv
? negv_optab
: neg_optab
;
332 return trapv
? absv_optab
: abs_optab
;
340 /* Generate code to perform an operation specified by TERNARY_OPTAB
341 on operands OP0, OP1 and OP2, with result having machine-mode MODE.
343 UNSIGNEDP is for the case where we have to widen the operands
344 to perform the operation. It says to use zero-extension.
346 If TARGET is nonzero, the value
347 is generated there, if it is convenient to do so.
348 In all cases an rtx is returned for the locus of the value;
349 this may or may not be TARGET. */
352 expand_ternary_op (enum machine_mode mode
, optab ternary_optab
, rtx op0
,
353 rtx op1
, rtx op2
, rtx target
, int unsignedp
)
355 int icode
= (int) ternary_optab
->handlers
[(int) mode
].insn_code
;
356 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
357 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
358 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
361 rtx xop0
= op0
, xop1
= op1
, xop2
= op2
;
363 gcc_assert (ternary_optab
->handlers
[(int) mode
].insn_code
364 != CODE_FOR_nothing
);
366 if (!target
|| !insn_data
[icode
].operand
[0].predicate (target
, mode
))
367 temp
= gen_reg_rtx (mode
);
371 /* In case the insn wants input operands in modes different from
372 those of the actual operands, convert the operands. It would
373 seem that we don't need to convert CONST_INTs, but we do, so
374 that they're properly zero-extended, sign-extended or truncated
377 if (GET_MODE (op0
) != mode0
&& mode0
!= VOIDmode
)
378 xop0
= convert_modes (mode0
,
379 GET_MODE (op0
) != VOIDmode
384 if (GET_MODE (op1
) != mode1
&& mode1
!= VOIDmode
)
385 xop1
= convert_modes (mode1
,
386 GET_MODE (op1
) != VOIDmode
391 if (GET_MODE (op2
) != mode2
&& mode2
!= VOIDmode
)
392 xop2
= convert_modes (mode2
,
393 GET_MODE (op2
) != VOIDmode
398 /* Now, if insn's predicates don't allow our operands, put them into
401 if (!insn_data
[icode
].operand
[1].predicate (xop0
, mode0
)
402 && mode0
!= VOIDmode
)
403 xop0
= copy_to_mode_reg (mode0
, xop0
);
405 if (!insn_data
[icode
].operand
[2].predicate (xop1
, mode1
)
406 && mode1
!= VOIDmode
)
407 xop1
= copy_to_mode_reg (mode1
, xop1
);
409 if (!insn_data
[icode
].operand
[3].predicate (xop2
, mode2
)
410 && mode2
!= VOIDmode
)
411 xop2
= copy_to_mode_reg (mode2
, xop2
);
413 pat
= GEN_FCN (icode
) (temp
, xop0
, xop1
, xop2
);
420 /* Like expand_binop, but return a constant rtx if the result can be
421 calculated at compile time. The arguments and return value are
422 otherwise the same as for expand_binop. */
425 simplify_expand_binop (enum machine_mode mode
, optab binoptab
,
426 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
427 enum optab_methods methods
)
429 if (CONSTANT_P (op0
) && CONSTANT_P (op1
))
430 return simplify_gen_binary (binoptab
->code
, mode
, op0
, op1
);
432 return expand_binop (mode
, binoptab
, op0
, op1
, target
, unsignedp
, methods
);
435 /* Like simplify_expand_binop, but always put the result in TARGET.
436 Return true if the expansion succeeded. */
439 force_expand_binop (enum machine_mode mode
, optab binoptab
,
440 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
441 enum optab_methods methods
)
443 rtx x
= simplify_expand_binop (mode
, binoptab
, op0
, op1
,
444 target
, unsignedp
, methods
);
448 emit_move_insn (target
, x
);
452 /* Generate insns for VEC_LSHIFT_EXPR, VEC_RSHIFT_EXPR. */
455 expand_vec_shift_expr (tree vec_shift_expr
, rtx target
)
457 enum insn_code icode
;
458 rtx rtx_op1
, rtx_op2
;
459 enum machine_mode mode1
;
460 enum machine_mode mode2
;
461 enum machine_mode mode
= TYPE_MODE (TREE_TYPE (vec_shift_expr
));
462 tree vec_oprnd
= TREE_OPERAND (vec_shift_expr
, 0);
463 tree shift_oprnd
= TREE_OPERAND (vec_shift_expr
, 1);
467 switch (TREE_CODE (vec_shift_expr
))
469 case VEC_RSHIFT_EXPR
:
470 shift_optab
= vec_shr_optab
;
472 case VEC_LSHIFT_EXPR
:
473 shift_optab
= vec_shl_optab
;
479 icode
= (int) shift_optab
->handlers
[(int) mode
].insn_code
;
480 gcc_assert (icode
!= CODE_FOR_nothing
);
482 mode1
= insn_data
[icode
].operand
[1].mode
;
483 mode2
= insn_data
[icode
].operand
[2].mode
;
485 rtx_op1
= expand_expr (vec_oprnd
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
486 if (!(*insn_data
[icode
].operand
[1].predicate
) (rtx_op1
, mode1
)
487 && mode1
!= VOIDmode
)
488 rtx_op1
= force_reg (mode1
, rtx_op1
);
490 rtx_op2
= expand_expr (shift_oprnd
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
491 if (!(*insn_data
[icode
].operand
[2].predicate
) (rtx_op2
, mode2
)
492 && mode2
!= VOIDmode
)
493 rtx_op2
= force_reg (mode2
, rtx_op2
);
496 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode
))
497 target
= gen_reg_rtx (mode
);
499 /* Emit instruction */
500 pat
= GEN_FCN (icode
) (target
, rtx_op1
, rtx_op2
);
507 /* This subroutine of expand_doubleword_shift handles the cases in which
508 the effective shift value is >= BITS_PER_WORD. The arguments and return
509 value are the same as for the parent routine, except that SUPERWORD_OP1
510 is the shift count to use when shifting OUTOF_INPUT into INTO_TARGET.
511 INTO_TARGET may be null if the caller has decided to calculate it. */
514 expand_superword_shift (optab binoptab
, rtx outof_input
, rtx superword_op1
,
515 rtx outof_target
, rtx into_target
,
516 int unsignedp
, enum optab_methods methods
)
518 if (into_target
!= 0)
519 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, superword_op1
,
520 into_target
, unsignedp
, methods
))
523 if (outof_target
!= 0)
525 /* For a signed right shift, we must fill OUTOF_TARGET with copies
526 of the sign bit, otherwise we must fill it with zeros. */
527 if (binoptab
!= ashr_optab
)
528 emit_move_insn (outof_target
, CONST0_RTX (word_mode
));
530 if (!force_expand_binop (word_mode
, binoptab
,
531 outof_input
, GEN_INT (BITS_PER_WORD
- 1),
532 outof_target
, unsignedp
, methods
))
538 /* This subroutine of expand_doubleword_shift handles the cases in which
539 the effective shift value is < BITS_PER_WORD. The arguments and return
540 value are the same as for the parent routine. */
543 expand_subword_shift (enum machine_mode op1_mode
, optab binoptab
,
544 rtx outof_input
, rtx into_input
, rtx op1
,
545 rtx outof_target
, rtx into_target
,
546 int unsignedp
, enum optab_methods methods
,
547 unsigned HOST_WIDE_INT shift_mask
)
549 optab reverse_unsigned_shift
, unsigned_shift
;
552 reverse_unsigned_shift
= (binoptab
== ashl_optab
? lshr_optab
: ashl_optab
);
553 unsigned_shift
= (binoptab
== ashl_optab
? ashl_optab
: lshr_optab
);
555 /* The low OP1 bits of INTO_TARGET come from the high bits of OUTOF_INPUT.
556 We therefore need to shift OUTOF_INPUT by (BITS_PER_WORD - OP1) bits in
557 the opposite direction to BINOPTAB. */
558 if (CONSTANT_P (op1
) || shift_mask
>= BITS_PER_WORD
)
560 carries
= outof_input
;
561 tmp
= immed_double_const (BITS_PER_WORD
, 0, op1_mode
);
562 tmp
= simplify_expand_binop (op1_mode
, sub_optab
, tmp
, op1
,
567 /* We must avoid shifting by BITS_PER_WORD bits since that is either
568 the same as a zero shift (if shift_mask == BITS_PER_WORD - 1) or
569 has unknown behavior. Do a single shift first, then shift by the
570 remainder. It's OK to use ~OP1 as the remainder if shift counts
571 are truncated to the mode size. */
572 carries
= expand_binop (word_mode
, reverse_unsigned_shift
,
573 outof_input
, const1_rtx
, 0, unsignedp
, methods
);
574 if (shift_mask
== BITS_PER_WORD
- 1)
576 tmp
= immed_double_const (-1, -1, op1_mode
);
577 tmp
= simplify_expand_binop (op1_mode
, xor_optab
, op1
, tmp
,
582 tmp
= immed_double_const (BITS_PER_WORD
- 1, 0, op1_mode
);
583 tmp
= simplify_expand_binop (op1_mode
, sub_optab
, tmp
, op1
,
587 if (tmp
== 0 || carries
== 0)
589 carries
= expand_binop (word_mode
, reverse_unsigned_shift
,
590 carries
, tmp
, 0, unsignedp
, methods
);
594 /* Shift INTO_INPUT logically by OP1. This is the last use of INTO_INPUT
595 so the result can go directly into INTO_TARGET if convenient. */
596 tmp
= expand_binop (word_mode
, unsigned_shift
, into_input
, op1
,
597 into_target
, unsignedp
, methods
);
601 /* Now OR in the bits carried over from OUTOF_INPUT. */
602 if (!force_expand_binop (word_mode
, ior_optab
, tmp
, carries
,
603 into_target
, unsignedp
, methods
))
606 /* Use a standard word_mode shift for the out-of half. */
607 if (outof_target
!= 0)
608 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, op1
,
609 outof_target
, unsignedp
, methods
))
616 #ifdef HAVE_conditional_move
617 /* Try implementing expand_doubleword_shift using conditional moves.
618 The shift is by < BITS_PER_WORD if (CMP_CODE CMP1 CMP2) is true,
619 otherwise it is by >= BITS_PER_WORD. SUBWORD_OP1 and SUPERWORD_OP1
620 are the shift counts to use in the former and latter case. All other
621 arguments are the same as the parent routine. */
624 expand_doubleword_shift_condmove (enum machine_mode op1_mode
, optab binoptab
,
625 enum rtx_code cmp_code
, rtx cmp1
, rtx cmp2
,
626 rtx outof_input
, rtx into_input
,
627 rtx subword_op1
, rtx superword_op1
,
628 rtx outof_target
, rtx into_target
,
629 int unsignedp
, enum optab_methods methods
,
630 unsigned HOST_WIDE_INT shift_mask
)
632 rtx outof_superword
, into_superword
;
634 /* Put the superword version of the output into OUTOF_SUPERWORD and
636 outof_superword
= outof_target
!= 0 ? gen_reg_rtx (word_mode
) : 0;
637 if (outof_target
!= 0 && subword_op1
== superword_op1
)
639 /* The value INTO_TARGET >> SUBWORD_OP1, which we later store in
640 OUTOF_TARGET, is the same as the value of INTO_SUPERWORD. */
641 into_superword
= outof_target
;
642 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
643 outof_superword
, 0, unsignedp
, methods
))
648 into_superword
= gen_reg_rtx (word_mode
);
649 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
650 outof_superword
, into_superword
,
655 /* Put the subword version directly in OUTOF_TARGET and INTO_TARGET. */
656 if (!expand_subword_shift (op1_mode
, binoptab
,
657 outof_input
, into_input
, subword_op1
,
658 outof_target
, into_target
,
659 unsignedp
, methods
, shift_mask
))
662 /* Select between them. Do the INTO half first because INTO_SUPERWORD
663 might be the current value of OUTOF_TARGET. */
664 if (!emit_conditional_move (into_target
, cmp_code
, cmp1
, cmp2
, op1_mode
,
665 into_target
, into_superword
, word_mode
, false))
668 if (outof_target
!= 0)
669 if (!emit_conditional_move (outof_target
, cmp_code
, cmp1
, cmp2
, op1_mode
,
670 outof_target
, outof_superword
,
678 /* Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts.
679 OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first
680 input operand; the shift moves bits in the direction OUTOF_INPUT->
681 INTO_TARGET. OUTOF_TARGET and INTO_TARGET are the equivalent words
682 of the target. OP1 is the shift count and OP1_MODE is its mode.
683 If OP1 is constant, it will have been truncated as appropriate
684 and is known to be nonzero.
686 If SHIFT_MASK is zero, the result of word shifts is undefined when the
687 shift count is outside the range [0, BITS_PER_WORD). This routine must
688 avoid generating such shifts for OP1s in the range [0, BITS_PER_WORD * 2).
690 If SHIFT_MASK is nonzero, all word-mode shift counts are effectively
691 masked by it and shifts in the range [BITS_PER_WORD, SHIFT_MASK) will
692 fill with zeros or sign bits as appropriate.
694 If SHIFT_MASK is BITS_PER_WORD - 1, this routine will synthesize
695 a doubleword shift whose equivalent mask is BITS_PER_WORD * 2 - 1.
696 Doing this preserves semantics required by SHIFT_COUNT_TRUNCATED.
697 In all other cases, shifts by values outside [0, BITS_PER_UNIT * 2)
700 BINOPTAB, UNSIGNEDP and METHODS are as for expand_binop. This function
701 may not use INTO_INPUT after modifying INTO_TARGET, and similarly for
702 OUTOF_INPUT and OUTOF_TARGET. OUTOF_TARGET can be null if the parent
703 function wants to calculate it itself.
705 Return true if the shift could be successfully synthesized. */
708 expand_doubleword_shift (enum machine_mode op1_mode
, optab binoptab
,
709 rtx outof_input
, rtx into_input
, rtx op1
,
710 rtx outof_target
, rtx into_target
,
711 int unsignedp
, enum optab_methods methods
,
712 unsigned HOST_WIDE_INT shift_mask
)
714 rtx superword_op1
, tmp
, cmp1
, cmp2
;
715 rtx subword_label
, done_label
;
716 enum rtx_code cmp_code
;
718 /* See if word-mode shifts by BITS_PER_WORD...BITS_PER_WORD * 2 - 1 will
719 fill the result with sign or zero bits as appropriate. If so, the value
720 of OUTOF_TARGET will always be (SHIFT OUTOF_INPUT OP1). Recursively call
721 this routine to calculate INTO_TARGET (which depends on both OUTOF_INPUT
722 and INTO_INPUT), then emit code to set up OUTOF_TARGET.
724 This isn't worthwhile for constant shifts since the optimizers will
725 cope better with in-range shift counts. */
726 if (shift_mask
>= BITS_PER_WORD
728 && !CONSTANT_P (op1
))
730 if (!expand_doubleword_shift (op1_mode
, binoptab
,
731 outof_input
, into_input
, op1
,
733 unsignedp
, methods
, shift_mask
))
735 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, op1
,
736 outof_target
, unsignedp
, methods
))
741 /* Set CMP_CODE, CMP1 and CMP2 so that the rtx (CMP_CODE CMP1 CMP2)
742 is true when the effective shift value is less than BITS_PER_WORD.
743 Set SUPERWORD_OP1 to the shift count that should be used to shift
744 OUTOF_INPUT into INTO_TARGET when the condition is false. */
745 tmp
= immed_double_const (BITS_PER_WORD
, 0, op1_mode
);
746 if (!CONSTANT_P (op1
) && shift_mask
== BITS_PER_WORD
- 1)
748 /* Set CMP1 to OP1 & BITS_PER_WORD. The result is zero iff OP1
749 is a subword shift count. */
750 cmp1
= simplify_expand_binop (op1_mode
, and_optab
, op1
, tmp
,
752 cmp2
= CONST0_RTX (op1_mode
);
758 /* Set CMP1 to OP1 - BITS_PER_WORD. */
759 cmp1
= simplify_expand_binop (op1_mode
, sub_optab
, op1
, tmp
,
761 cmp2
= CONST0_RTX (op1_mode
);
763 superword_op1
= cmp1
;
768 /* If we can compute the condition at compile time, pick the
769 appropriate subroutine. */
770 tmp
= simplify_relational_operation (cmp_code
, SImode
, op1_mode
, cmp1
, cmp2
);
771 if (tmp
!= 0 && GET_CODE (tmp
) == CONST_INT
)
773 if (tmp
== const0_rtx
)
774 return expand_superword_shift (binoptab
, outof_input
, superword_op1
,
775 outof_target
, into_target
,
778 return expand_subword_shift (op1_mode
, binoptab
,
779 outof_input
, into_input
, op1
,
780 outof_target
, into_target
,
781 unsignedp
, methods
, shift_mask
);
784 #ifdef HAVE_conditional_move
785 /* Try using conditional moves to generate straight-line code. */
787 rtx start
= get_last_insn ();
788 if (expand_doubleword_shift_condmove (op1_mode
, binoptab
,
789 cmp_code
, cmp1
, cmp2
,
790 outof_input
, into_input
,
792 outof_target
, into_target
,
793 unsignedp
, methods
, shift_mask
))
795 delete_insns_since (start
);
799 /* As a last resort, use branches to select the correct alternative. */
800 subword_label
= gen_label_rtx ();
801 done_label
= gen_label_rtx ();
803 do_compare_rtx_and_jump (cmp1
, cmp2
, cmp_code
, false, op1_mode
,
804 0, 0, subword_label
);
806 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
807 outof_target
, into_target
,
811 emit_jump_insn (gen_jump (done_label
));
813 emit_label (subword_label
);
815 if (!expand_subword_shift (op1_mode
, binoptab
,
816 outof_input
, into_input
, op1
,
817 outof_target
, into_target
,
818 unsignedp
, methods
, shift_mask
))
821 emit_label (done_label
);
825 /* Subroutine of expand_binop. Perform a double word multiplication of
826 operands OP0 and OP1 both of mode MODE, which is exactly twice as wide
827 as the target's word_mode. This function return NULL_RTX if anything
828 goes wrong, in which case it may have already emitted instructions
829 which need to be deleted.
831 If we want to multiply two two-word values and have normal and widening
832 multiplies of single-word values, we can do this with three smaller
833 multiplications. Note that we do not make a REG_NO_CONFLICT block here
834 because we are not operating on one word at a time.
836 The multiplication proceeds as follows:
837 _______________________
838 [__op0_high_|__op0_low__]
839 _______________________
840 * [__op1_high_|__op1_low__]
841 _______________________________________________
842 _______________________
843 (1) [__op0_low__*__op1_low__]
844 _______________________
845 (2a) [__op0_low__*__op1_high_]
846 _______________________
847 (2b) [__op0_high_*__op1_low__]
848 _______________________
849 (3) [__op0_high_*__op1_high_]
852 This gives a 4-word result. Since we are only interested in the
853 lower 2 words, partial result (3) and the upper words of (2a) and
854 (2b) don't need to be calculated. Hence (2a) and (2b) can be
855 calculated using non-widening multiplication.
857 (1), however, needs to be calculated with an unsigned widening
858 multiplication. If this operation is not directly supported we
859 try using a signed widening multiplication and adjust the result.
860 This adjustment works as follows:
862 If both operands are positive then no adjustment is needed.
864 If the operands have different signs, for example op0_low < 0 and
865 op1_low >= 0, the instruction treats the most significant bit of
866 op0_low as a sign bit instead of a bit with significance
867 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low
868 with 2**BITS_PER_WORD - op0_low, and two's complements the
869 result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to
872 Similarly, if both operands are negative, we need to add
873 (op0_low + op1_low) * 2**BITS_PER_WORD.
875 We use a trick to adjust quickly. We logically shift op0_low right
876 (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to
877 op0_high (op1_high) before it is used to calculate 2b (2a). If no
878 logical shift exists, we do an arithmetic right shift and subtract
882 expand_doubleword_mult (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
883 bool umulp
, enum optab_methods methods
)
885 int low
= (WORDS_BIG_ENDIAN
? 1 : 0);
886 int high
= (WORDS_BIG_ENDIAN
? 0 : 1);
887 rtx wordm1
= umulp
? NULL_RTX
: GEN_INT (BITS_PER_WORD
- 1);
888 rtx product
, adjust
, product_high
, temp
;
890 rtx op0_high
= operand_subword_force (op0
, high
, mode
);
891 rtx op0_low
= operand_subword_force (op0
, low
, mode
);
892 rtx op1_high
= operand_subword_force (op1
, high
, mode
);
893 rtx op1_low
= operand_subword_force (op1
, low
, mode
);
895 /* If we're using an unsigned multiply to directly compute the product
896 of the low-order words of the operands and perform any required
897 adjustments of the operands, we begin by trying two more multiplications
898 and then computing the appropriate sum.
900 We have checked above that the required addition is provided.
901 Full-word addition will normally always succeed, especially if
902 it is provided at all, so we don't worry about its failure. The
903 multiplication may well fail, however, so we do handle that. */
907 /* ??? This could be done with emit_store_flag where available. */
908 temp
= expand_binop (word_mode
, lshr_optab
, op0_low
, wordm1
,
909 NULL_RTX
, 1, methods
);
911 op0_high
= expand_binop (word_mode
, add_optab
, op0_high
, temp
,
912 NULL_RTX
, 0, OPTAB_DIRECT
);
915 temp
= expand_binop (word_mode
, ashr_optab
, op0_low
, wordm1
,
916 NULL_RTX
, 0, methods
);
919 op0_high
= expand_binop (word_mode
, sub_optab
, op0_high
, temp
,
920 NULL_RTX
, 0, OPTAB_DIRECT
);
927 adjust
= expand_binop (word_mode
, smul_optab
, op0_high
, op1_low
,
928 NULL_RTX
, 0, OPTAB_DIRECT
);
932 /* OP0_HIGH should now be dead. */
936 /* ??? This could be done with emit_store_flag where available. */
937 temp
= expand_binop (word_mode
, lshr_optab
, op1_low
, wordm1
,
938 NULL_RTX
, 1, methods
);
940 op1_high
= expand_binop (word_mode
, add_optab
, op1_high
, temp
,
941 NULL_RTX
, 0, OPTAB_DIRECT
);
944 temp
= expand_binop (word_mode
, ashr_optab
, op1_low
, wordm1
,
945 NULL_RTX
, 0, methods
);
948 op1_high
= expand_binop (word_mode
, sub_optab
, op1_high
, temp
,
949 NULL_RTX
, 0, OPTAB_DIRECT
);
956 temp
= expand_binop (word_mode
, smul_optab
, op1_high
, op0_low
,
957 NULL_RTX
, 0, OPTAB_DIRECT
);
961 /* OP1_HIGH should now be dead. */
963 adjust
= expand_binop (word_mode
, add_optab
, adjust
, temp
,
964 adjust
, 0, OPTAB_DIRECT
);
966 if (target
&& !REG_P (target
))
970 product
= expand_binop (mode
, umul_widen_optab
, op0_low
, op1_low
,
971 target
, 1, OPTAB_DIRECT
);
973 product
= expand_binop (mode
, smul_widen_optab
, op0_low
, op1_low
,
974 target
, 1, OPTAB_DIRECT
);
979 product_high
= operand_subword (product
, high
, 1, mode
);
980 adjust
= expand_binop (word_mode
, add_optab
, product_high
, adjust
,
981 REG_P (product_high
) ? product_high
: adjust
,
983 emit_move_insn (product_high
, adjust
);
987 /* Wrapper around expand_binop which takes an rtx code to specify
988 the operation to perform, not an optab pointer. All other
989 arguments are the same. */
991 expand_simple_binop (enum machine_mode mode
, enum rtx_code code
, rtx op0
,
992 rtx op1
, rtx target
, int unsignedp
,
993 enum optab_methods methods
)
995 optab binop
= code_to_optab
[(int) code
];
998 return expand_binop (mode
, binop
, op0
, op1
, target
, unsignedp
, methods
);
1001 /* Generate code to perform an operation specified by BINOPTAB
1002 on operands OP0 and OP1, with result having machine-mode MODE.
1004 UNSIGNEDP is for the case where we have to widen the operands
1005 to perform the operation. It says to use zero-extension.
1007 If TARGET is nonzero, the value
1008 is generated there, if it is convenient to do so.
1009 In all cases an rtx is returned for the locus of the value;
1010 this may or may not be TARGET. */
1013 expand_binop (enum machine_mode mode
, optab binoptab
, rtx op0
, rtx op1
,
1014 rtx target
, int unsignedp
, enum optab_methods methods
)
1016 enum optab_methods next_methods
1017 = (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
1018 ? OPTAB_WIDEN
: methods
);
1019 enum mode_class
class;
1020 enum machine_mode wider_mode
;
1022 int commutative_op
= 0;
1023 int shift_op
= (binoptab
->code
== ASHIFT
1024 || binoptab
->code
== ASHIFTRT
1025 || binoptab
->code
== LSHIFTRT
1026 || binoptab
->code
== ROTATE
1027 || binoptab
->code
== ROTATERT
);
1028 rtx entry_last
= get_last_insn ();
1030 bool first_pass_p
= true;
1032 class = GET_MODE_CLASS (mode
);
1034 /* If subtracting an integer constant, convert this into an addition of
1035 the negated constant. */
1037 if (binoptab
== sub_optab
&& GET_CODE (op1
) == CONST_INT
)
1039 op1
= negate_rtx (mode
, op1
);
1040 binoptab
= add_optab
;
1043 /* If we are inside an appropriately-short loop and we are optimizing,
1044 force expensive constants into a register. */
1045 if (CONSTANT_P (op0
) && optimize
1046 && rtx_cost (op0
, binoptab
->code
) > COSTS_N_INSNS (1))
1048 if (GET_MODE (op0
) != VOIDmode
)
1049 op0
= convert_modes (mode
, VOIDmode
, op0
, unsignedp
);
1050 op0
= force_reg (mode
, op0
);
1053 if (CONSTANT_P (op1
) && optimize
1054 && ! shift_op
&& rtx_cost (op1
, binoptab
->code
) > COSTS_N_INSNS (1))
1056 if (GET_MODE (op1
) != VOIDmode
)
1057 op1
= convert_modes (mode
, VOIDmode
, op1
, unsignedp
);
1058 op1
= force_reg (mode
, op1
);
1061 /* Record where to delete back to if we backtrack. */
1062 last
= get_last_insn ();
1064 /* If operation is commutative,
1065 try to make the first operand a register.
1066 Even better, try to make it the same as the target.
1067 Also try to make the last operand a constant. */
1068 if (GET_RTX_CLASS (binoptab
->code
) == RTX_COMM_ARITH
1069 || binoptab
== smul_widen_optab
1070 || binoptab
== umul_widen_optab
1071 || binoptab
== smul_highpart_optab
1072 || binoptab
== umul_highpart_optab
)
1076 if (((target
== 0 || REG_P (target
))
1080 : rtx_equal_p (op1
, target
))
1081 || GET_CODE (op0
) == CONST_INT
)
1091 /* If we can do it with a three-operand insn, do so. */
1093 if (methods
!= OPTAB_MUST_WIDEN
1094 && binoptab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
1096 int icode
= (int) binoptab
->handlers
[(int) mode
].insn_code
;
1097 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
1098 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
1100 rtx xop0
= op0
, xop1
= op1
;
1105 temp
= gen_reg_rtx (mode
);
1107 /* If it is a commutative operator and the modes would match
1108 if we would swap the operands, we can save the conversions. */
1111 if (GET_MODE (op0
) != mode0
&& GET_MODE (op1
) != mode1
1112 && GET_MODE (op0
) == mode1
&& GET_MODE (op1
) == mode0
)
1116 tmp
= op0
; op0
= op1
; op1
= tmp
;
1117 tmp
= xop0
; xop0
= xop1
; xop1
= tmp
;
1121 /* In case the insn wants input operands in modes different from
1122 those of the actual operands, convert the operands. It would
1123 seem that we don't need to convert CONST_INTs, but we do, so
1124 that they're properly zero-extended, sign-extended or truncated
1127 if (GET_MODE (op0
) != mode0
&& mode0
!= VOIDmode
)
1128 xop0
= convert_modes (mode0
,
1129 GET_MODE (op0
) != VOIDmode
1134 if (GET_MODE (op1
) != mode1
&& mode1
!= VOIDmode
)
1135 xop1
= convert_modes (mode1
,
1136 GET_MODE (op1
) != VOIDmode
1141 /* Now, if insn's predicates don't allow our operands, put them into
1144 if (!insn_data
[icode
].operand
[1].predicate (xop0
, mode0
)
1145 && mode0
!= VOIDmode
)
1146 xop0
= copy_to_mode_reg (mode0
, xop0
);
1148 if (!insn_data
[icode
].operand
[2].predicate (xop1
, mode1
)
1149 && mode1
!= VOIDmode
)
1150 xop1
= copy_to_mode_reg (mode1
, xop1
);
1152 if (!insn_data
[icode
].operand
[0].predicate (temp
, mode
))
1153 temp
= gen_reg_rtx (mode
);
1155 pat
= GEN_FCN (icode
) (temp
, xop0
, xop1
);
1158 /* If PAT is composed of more than one insn, try to add an appropriate
1159 REG_EQUAL note to it. If we can't because TEMP conflicts with an
1160 operand, call ourselves again, this time without a target. */
1161 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
1162 && ! add_equal_note (pat
, temp
, binoptab
->code
, xop0
, xop1
))
1164 delete_insns_since (last
);
1165 return expand_binop (mode
, binoptab
, op0
, op1
, NULL_RTX
,
1166 unsignedp
, methods
);
1173 delete_insns_since (last
);
1176 /* If we were trying to rotate by a constant value, and that didn't
1177 work, try rotating the other direction before falling back to
1178 shifts and bitwise-or. */
1180 && (binoptab
== rotl_optab
|| binoptab
== rotr_optab
)
1181 && class == MODE_INT
1182 && GET_CODE (op1
) == CONST_INT
1184 && (unsigned int) INTVAL (op1
) < GET_MODE_BITSIZE (mode
))
1186 first_pass_p
= false;
1187 op1
= GEN_INT (GET_MODE_BITSIZE (mode
) - INTVAL (op1
));
1188 binoptab
= binoptab
== rotl_optab
? rotr_optab
: rotl_optab
;
1192 /* If this is a multiply, see if we can do a widening operation that
1193 takes operands of this mode and makes a wider mode. */
1195 if (binoptab
== smul_optab
&& GET_MODE_WIDER_MODE (mode
) != VOIDmode
1196 && (((unsignedp
? umul_widen_optab
: smul_widen_optab
)
1197 ->handlers
[(int) GET_MODE_WIDER_MODE (mode
)].insn_code
)
1198 != CODE_FOR_nothing
))
1200 temp
= expand_binop (GET_MODE_WIDER_MODE (mode
),
1201 unsignedp
? umul_widen_optab
: smul_widen_optab
,
1202 op0
, op1
, NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
1206 if (GET_MODE_CLASS (mode
) == MODE_INT
1207 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
1208 GET_MODE_BITSIZE (GET_MODE (temp
))))
1209 return gen_lowpart (mode
, temp
);
1211 return convert_to_mode (mode
, temp
, unsignedp
);
1215 /* Look for a wider mode of the same class for which we think we
1216 can open-code the operation. Check for a widening multiply at the
1217 wider mode as well. */
1219 if ((class == MODE_INT
|| class == MODE_FLOAT
|| class == MODE_COMPLEX_FLOAT
)
1220 && methods
!= OPTAB_DIRECT
&& methods
!= OPTAB_LIB
)
1221 for (wider_mode
= GET_MODE_WIDER_MODE (mode
); wider_mode
!= VOIDmode
;
1222 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
1224 if (binoptab
->handlers
[(int) wider_mode
].insn_code
!= CODE_FOR_nothing
1225 || (binoptab
== smul_optab
1226 && GET_MODE_WIDER_MODE (wider_mode
) != VOIDmode
1227 && (((unsignedp
? umul_widen_optab
: smul_widen_optab
)
1228 ->handlers
[(int) GET_MODE_WIDER_MODE (wider_mode
)].insn_code
)
1229 != CODE_FOR_nothing
)))
1231 rtx xop0
= op0
, xop1
= op1
;
1234 /* For certain integer operations, we need not actually extend
1235 the narrow operands, as long as we will truncate
1236 the results to the same narrowness. */
1238 if ((binoptab
== ior_optab
|| binoptab
== and_optab
1239 || binoptab
== xor_optab
1240 || binoptab
== add_optab
|| binoptab
== sub_optab
1241 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
1242 && class == MODE_INT
)
1245 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
, no_extend
);
1247 /* The second operand of a shift must always be extended. */
1248 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
1249 no_extend
&& binoptab
!= ashl_optab
);
1251 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
1252 unsignedp
, OPTAB_DIRECT
);
1255 if (class != MODE_INT
1256 || !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
1257 GET_MODE_BITSIZE (wider_mode
)))
1260 target
= gen_reg_rtx (mode
);
1261 convert_move (target
, temp
, 0);
1265 return gen_lowpart (mode
, temp
);
1268 delete_insns_since (last
);
1272 /* These can be done a word at a time. */
1273 if ((binoptab
== and_optab
|| binoptab
== ior_optab
|| binoptab
== xor_optab
)
1274 && class == MODE_INT
1275 && GET_MODE_SIZE (mode
) > UNITS_PER_WORD
1276 && binoptab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
)
1282 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1283 won't be accurate, so use a new target. */
1284 if (target
== 0 || target
== op0
|| target
== op1
)
1285 target
= gen_reg_rtx (mode
);
1289 /* Do the actual arithmetic. */
1290 for (i
= 0; i
< GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
; i
++)
1292 rtx target_piece
= operand_subword (target
, i
, 1, mode
);
1293 rtx x
= expand_binop (word_mode
, binoptab
,
1294 operand_subword_force (op0
, i
, mode
),
1295 operand_subword_force (op1
, i
, mode
),
1296 target_piece
, unsignedp
, next_methods
);
1301 if (target_piece
!= x
)
1302 emit_move_insn (target_piece
, x
);
1305 insns
= get_insns ();
1308 if (i
== GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
)
1310 if (binoptab
->code
!= UNKNOWN
)
1312 = gen_rtx_fmt_ee (binoptab
->code
, mode
,
1313 copy_rtx (op0
), copy_rtx (op1
));
1317 emit_no_conflict_block (insns
, target
, op0
, op1
, equiv_value
);
1322 /* Synthesize double word shifts from single word shifts. */
1323 if ((binoptab
== lshr_optab
|| binoptab
== ashl_optab
1324 || binoptab
== ashr_optab
)
1325 && class == MODE_INT
1326 && (GET_CODE (op1
) == CONST_INT
|| !optimize_size
)
1327 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
1328 && binoptab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
1329 && ashl_optab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
1330 && lshr_optab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
)
1332 unsigned HOST_WIDE_INT shift_mask
, double_shift_mask
;
1333 enum machine_mode op1_mode
;
1335 double_shift_mask
= targetm
.shift_truncation_mask (mode
);
1336 shift_mask
= targetm
.shift_truncation_mask (word_mode
);
1337 op1_mode
= GET_MODE (op1
) != VOIDmode
? GET_MODE (op1
) : word_mode
;
1339 /* Apply the truncation to constant shifts. */
1340 if (double_shift_mask
> 0 && GET_CODE (op1
) == CONST_INT
)
1341 op1
= GEN_INT (INTVAL (op1
) & double_shift_mask
);
1343 if (op1
== CONST0_RTX (op1_mode
))
1346 /* Make sure that this is a combination that expand_doubleword_shift
1347 can handle. See the comments there for details. */
1348 if (double_shift_mask
== 0
1349 || (shift_mask
== BITS_PER_WORD
- 1
1350 && double_shift_mask
== BITS_PER_WORD
* 2 - 1))
1352 rtx insns
, equiv_value
;
1353 rtx into_target
, outof_target
;
1354 rtx into_input
, outof_input
;
1355 int left_shift
, outof_word
;
1357 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1358 won't be accurate, so use a new target. */
1359 if (target
== 0 || target
== op0
|| target
== op1
)
1360 target
= gen_reg_rtx (mode
);
1364 /* OUTOF_* is the word we are shifting bits away from, and
1365 INTO_* is the word that we are shifting bits towards, thus
1366 they differ depending on the direction of the shift and
1367 WORDS_BIG_ENDIAN. */
1369 left_shift
= binoptab
== ashl_optab
;
1370 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
1372 outof_target
= operand_subword (target
, outof_word
, 1, mode
);
1373 into_target
= operand_subword (target
, 1 - outof_word
, 1, mode
);
1375 outof_input
= operand_subword_force (op0
, outof_word
, mode
);
1376 into_input
= operand_subword_force (op0
, 1 - outof_word
, mode
);
1378 if (expand_doubleword_shift (op1_mode
, binoptab
,
1379 outof_input
, into_input
, op1
,
1380 outof_target
, into_target
,
1381 unsignedp
, methods
, shift_mask
))
1383 insns
= get_insns ();
1386 equiv_value
= gen_rtx_fmt_ee (binoptab
->code
, mode
, op0
, op1
);
1387 emit_no_conflict_block (insns
, target
, op0
, op1
, equiv_value
);
1394 /* Synthesize double word rotates from single word shifts. */
1395 if ((binoptab
== rotl_optab
|| binoptab
== rotr_optab
)
1396 && class == MODE_INT
1397 && GET_CODE (op1
) == CONST_INT
1398 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
1399 && ashl_optab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
1400 && lshr_optab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
)
1402 rtx insns
, equiv_value
;
1403 rtx into_target
, outof_target
;
1404 rtx into_input
, outof_input
;
1406 int shift_count
, left_shift
, outof_word
;
1408 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1409 won't be accurate, so use a new target. Do this also if target is not
1410 a REG, first because having a register instead may open optimization
1411 opportunities, and second because if target and op0 happen to be MEMs
1412 designating the same location, we would risk clobbering it too early
1413 in the code sequence we generate below. */
1414 if (target
== 0 || target
== op0
|| target
== op1
|| ! REG_P (target
))
1415 target
= gen_reg_rtx (mode
);
1419 shift_count
= INTVAL (op1
);
1421 /* OUTOF_* is the word we are shifting bits away from, and
1422 INTO_* is the word that we are shifting bits towards, thus
1423 they differ depending on the direction of the shift and
1424 WORDS_BIG_ENDIAN. */
1426 left_shift
= (binoptab
== rotl_optab
);
1427 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
1429 outof_target
= operand_subword (target
, outof_word
, 1, mode
);
1430 into_target
= operand_subword (target
, 1 - outof_word
, 1, mode
);
1432 outof_input
= operand_subword_force (op0
, outof_word
, mode
);
1433 into_input
= operand_subword_force (op0
, 1 - outof_word
, mode
);
1435 if (shift_count
== BITS_PER_WORD
)
1437 /* This is just a word swap. */
1438 emit_move_insn (outof_target
, into_input
);
1439 emit_move_insn (into_target
, outof_input
);
1444 rtx into_temp1
, into_temp2
, outof_temp1
, outof_temp2
;
1445 rtx first_shift_count
, second_shift_count
;
1446 optab reverse_unsigned_shift
, unsigned_shift
;
1448 reverse_unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
1449 ? lshr_optab
: ashl_optab
);
1451 unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
1452 ? ashl_optab
: lshr_optab
);
1454 if (shift_count
> BITS_PER_WORD
)
1456 first_shift_count
= GEN_INT (shift_count
- BITS_PER_WORD
);
1457 second_shift_count
= GEN_INT (2 * BITS_PER_WORD
- shift_count
);
1461 first_shift_count
= GEN_INT (BITS_PER_WORD
- shift_count
);
1462 second_shift_count
= GEN_INT (shift_count
);
1465 into_temp1
= expand_binop (word_mode
, unsigned_shift
,
1466 outof_input
, first_shift_count
,
1467 NULL_RTX
, unsignedp
, next_methods
);
1468 into_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
1469 into_input
, second_shift_count
,
1470 NULL_RTX
, unsignedp
, next_methods
);
1472 if (into_temp1
!= 0 && into_temp2
!= 0)
1473 inter
= expand_binop (word_mode
, ior_optab
, into_temp1
, into_temp2
,
1474 into_target
, unsignedp
, next_methods
);
1478 if (inter
!= 0 && inter
!= into_target
)
1479 emit_move_insn (into_target
, inter
);
1481 outof_temp1
= expand_binop (word_mode
, unsigned_shift
,
1482 into_input
, first_shift_count
,
1483 NULL_RTX
, unsignedp
, next_methods
);
1484 outof_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
1485 outof_input
, second_shift_count
,
1486 NULL_RTX
, unsignedp
, next_methods
);
1488 if (inter
!= 0 && outof_temp1
!= 0 && outof_temp2
!= 0)
1489 inter
= expand_binop (word_mode
, ior_optab
,
1490 outof_temp1
, outof_temp2
,
1491 outof_target
, unsignedp
, next_methods
);
1493 if (inter
!= 0 && inter
!= outof_target
)
1494 emit_move_insn (outof_target
, inter
);
1497 insns
= get_insns ();
1502 if (binoptab
->code
!= UNKNOWN
)
1503 equiv_value
= gen_rtx_fmt_ee (binoptab
->code
, mode
, op0
, op1
);
1507 /* We can't make this a no conflict block if this is a word swap,
1508 because the word swap case fails if the input and output values
1509 are in the same register. */
1510 if (shift_count
!= BITS_PER_WORD
)
1511 emit_no_conflict_block (insns
, target
, op0
, op1
, equiv_value
);
1520 /* These can be done a word at a time by propagating carries. */
1521 if ((binoptab
== add_optab
|| binoptab
== sub_optab
)
1522 && class == MODE_INT
1523 && GET_MODE_SIZE (mode
) >= 2 * UNITS_PER_WORD
1524 && binoptab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
)
1527 optab otheroptab
= binoptab
== add_optab
? sub_optab
: add_optab
;
1528 const unsigned int nwords
= GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
;
1529 rtx carry_in
= NULL_RTX
, carry_out
= NULL_RTX
;
1530 rtx xop0
, xop1
, xtarget
;
1532 /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG
1533 value is one of those, use it. Otherwise, use 1 since it is the
1534 one easiest to get. */
1535 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
1536 int normalizep
= STORE_FLAG_VALUE
;
1541 /* Prepare the operands. */
1542 xop0
= force_reg (mode
, op0
);
1543 xop1
= force_reg (mode
, op1
);
1545 xtarget
= gen_reg_rtx (mode
);
1547 if (target
== 0 || !REG_P (target
))
1550 /* Indicate for flow that the entire target reg is being set. */
1552 emit_insn (gen_rtx_CLOBBER (VOIDmode
, xtarget
));
1554 /* Do the actual arithmetic. */
1555 for (i
= 0; i
< nwords
; i
++)
1557 int index
= (WORDS_BIG_ENDIAN
? nwords
- i
- 1 : i
);
1558 rtx target_piece
= operand_subword (xtarget
, index
, 1, mode
);
1559 rtx op0_piece
= operand_subword_force (xop0
, index
, mode
);
1560 rtx op1_piece
= operand_subword_force (xop1
, index
, mode
);
1563 /* Main add/subtract of the input operands. */
1564 x
= expand_binop (word_mode
, binoptab
,
1565 op0_piece
, op1_piece
,
1566 target_piece
, unsignedp
, next_methods
);
1572 /* Store carry from main add/subtract. */
1573 carry_out
= gen_reg_rtx (word_mode
);
1574 carry_out
= emit_store_flag_force (carry_out
,
1575 (binoptab
== add_optab
1578 word_mode
, 1, normalizep
);
1585 /* Add/subtract previous carry to main result. */
1586 newx
= expand_binop (word_mode
,
1587 normalizep
== 1 ? binoptab
: otheroptab
,
1589 NULL_RTX
, 1, next_methods
);
1593 /* Get out carry from adding/subtracting carry in. */
1594 rtx carry_tmp
= gen_reg_rtx (word_mode
);
1595 carry_tmp
= emit_store_flag_force (carry_tmp
,
1596 (binoptab
== add_optab
1599 word_mode
, 1, normalizep
);
1601 /* Logical-ior the two poss. carry together. */
1602 carry_out
= expand_binop (word_mode
, ior_optab
,
1603 carry_out
, carry_tmp
,
1604 carry_out
, 0, next_methods
);
1608 emit_move_insn (target_piece
, newx
);
1612 if (x
!= target_piece
)
1613 emit_move_insn (target_piece
, x
);
1616 carry_in
= carry_out
;
1619 if (i
== GET_MODE_BITSIZE (mode
) / (unsigned) BITS_PER_WORD
)
1621 if (mov_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
1622 || ! rtx_equal_p (target
, xtarget
))
1624 rtx temp
= emit_move_insn (target
, xtarget
);
1626 set_unique_reg_note (temp
,
1628 gen_rtx_fmt_ee (binoptab
->code
, mode
,
1639 delete_insns_since (last
);
1642 /* Attempt to synthesize double word multiplies using a sequence of word
1643 mode multiplications. We first attempt to generate a sequence using a
1644 more efficient unsigned widening multiply, and if that fails we then
1645 try using a signed widening multiply. */
1647 if (binoptab
== smul_optab
1648 && class == MODE_INT
1649 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
1650 && smul_optab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
1651 && add_optab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
)
1653 rtx product
= NULL_RTX
;
1655 if (umul_widen_optab
->handlers
[(int) mode
].insn_code
1656 != CODE_FOR_nothing
)
1658 product
= expand_doubleword_mult (mode
, op0
, op1
, target
,
1661 delete_insns_since (last
);
1664 if (product
== NULL_RTX
1665 && smul_widen_optab
->handlers
[(int) mode
].insn_code
1666 != CODE_FOR_nothing
)
1668 product
= expand_doubleword_mult (mode
, op0
, op1
, target
,
1671 delete_insns_since (last
);
1674 if (product
!= NULL_RTX
)
1676 if (mov_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
1678 temp
= emit_move_insn (target
? target
: product
, product
);
1679 set_unique_reg_note (temp
,
1681 gen_rtx_fmt_ee (MULT
, mode
,
1689 /* It can't be open-coded in this mode.
1690 Use a library call if one is available and caller says that's ok. */
1692 if (binoptab
->handlers
[(int) mode
].libfunc
1693 && (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
))
1697 enum machine_mode op1_mode
= mode
;
1704 op1_mode
= word_mode
;
1705 /* Specify unsigned here,
1706 since negative shift counts are meaningless. */
1707 op1x
= convert_to_mode (word_mode
, op1
, 1);
1710 if (GET_MODE (op0
) != VOIDmode
1711 && GET_MODE (op0
) != mode
)
1712 op0
= convert_to_mode (mode
, op0
, unsignedp
);
1714 /* Pass 1 for NO_QUEUE so we don't lose any increments
1715 if the libcall is cse'd or moved. */
1716 value
= emit_library_call_value (binoptab
->handlers
[(int) mode
].libfunc
,
1717 NULL_RTX
, LCT_CONST
, mode
, 2,
1718 op0
, mode
, op1x
, op1_mode
);
1720 insns
= get_insns ();
1723 target
= gen_reg_rtx (mode
);
1724 emit_libcall_block (insns
, target
, value
,
1725 gen_rtx_fmt_ee (binoptab
->code
, mode
, op0
, op1
));
1730 delete_insns_since (last
);
1732 /* It can't be done in this mode. Can we do it in a wider mode? */
1734 if (! (methods
== OPTAB_WIDEN
|| methods
== OPTAB_LIB_WIDEN
1735 || methods
== OPTAB_MUST_WIDEN
))
1737 /* Caller says, don't even try. */
1738 delete_insns_since (entry_last
);
1742 /* Compute the value of METHODS to pass to recursive calls.
1743 Don't allow widening to be tried recursively. */
1745 methods
= (methods
== OPTAB_LIB_WIDEN
? OPTAB_LIB
: OPTAB_DIRECT
);
1747 /* Look for a wider mode of the same class for which it appears we can do
1750 if (class == MODE_INT
|| class == MODE_FLOAT
|| class == MODE_COMPLEX_FLOAT
)
1752 for (wider_mode
= GET_MODE_WIDER_MODE (mode
); wider_mode
!= VOIDmode
;
1753 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
1755 if ((binoptab
->handlers
[(int) wider_mode
].insn_code
1756 != CODE_FOR_nothing
)
1757 || (methods
== OPTAB_LIB
1758 && binoptab
->handlers
[(int) wider_mode
].libfunc
))
1760 rtx xop0
= op0
, xop1
= op1
;
1763 /* For certain integer operations, we need not actually extend
1764 the narrow operands, as long as we will truncate
1765 the results to the same narrowness. */
1767 if ((binoptab
== ior_optab
|| binoptab
== and_optab
1768 || binoptab
== xor_optab
1769 || binoptab
== add_optab
|| binoptab
== sub_optab
1770 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
1771 && class == MODE_INT
)
1774 xop0
= widen_operand (xop0
, wider_mode
, mode
,
1775 unsignedp
, no_extend
);
1777 /* The second operand of a shift must always be extended. */
1778 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
1779 no_extend
&& binoptab
!= ashl_optab
);
1781 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
1782 unsignedp
, methods
);
1785 if (class != MODE_INT
1786 || !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
1787 GET_MODE_BITSIZE (wider_mode
)))
1790 target
= gen_reg_rtx (mode
);
1791 convert_move (target
, temp
, 0);
1795 return gen_lowpart (mode
, temp
);
1798 delete_insns_since (last
);
1803 delete_insns_since (entry_last
);
1807 /* Expand a binary operator which has both signed and unsigned forms.
1808 UOPTAB is the optab for unsigned operations, and SOPTAB is for
1811 If we widen unsigned operands, we may use a signed wider operation instead
1812 of an unsigned wider operation, since the result would be the same. */
1815 sign_expand_binop (enum machine_mode mode
, optab uoptab
, optab soptab
,
1816 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
1817 enum optab_methods methods
)
1820 optab direct_optab
= unsignedp
? uoptab
: soptab
;
1821 struct optab wide_soptab
;
1823 /* Do it without widening, if possible. */
1824 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
,
1825 unsignedp
, OPTAB_DIRECT
);
1826 if (temp
|| methods
== OPTAB_DIRECT
)
1829 /* Try widening to a signed int. Make a fake signed optab that
1830 hides any signed insn for direct use. */
1831 wide_soptab
= *soptab
;
1832 wide_soptab
.handlers
[(int) mode
].insn_code
= CODE_FOR_nothing
;
1833 wide_soptab
.handlers
[(int) mode
].libfunc
= 0;
1835 temp
= expand_binop (mode
, &wide_soptab
, op0
, op1
, target
,
1836 unsignedp
, OPTAB_WIDEN
);
1838 /* For unsigned operands, try widening to an unsigned int. */
1839 if (temp
== 0 && unsignedp
)
1840 temp
= expand_binop (mode
, uoptab
, op0
, op1
, target
,
1841 unsignedp
, OPTAB_WIDEN
);
1842 if (temp
|| methods
== OPTAB_WIDEN
)
1845 /* Use the right width lib call if that exists. */
1846 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
, unsignedp
, OPTAB_LIB
);
1847 if (temp
|| methods
== OPTAB_LIB
)
1850 /* Must widen and use a lib call, use either signed or unsigned. */
1851 temp
= expand_binop (mode
, &wide_soptab
, op0
, op1
, target
,
1852 unsignedp
, methods
);
1856 return expand_binop (mode
, uoptab
, op0
, op1
, target
,
1857 unsignedp
, methods
);
1861 /* Generate code to perform an operation specified by UNOPPTAB
1862 on operand OP0, with two results to TARG0 and TARG1.
1863 We assume that the order of the operands for the instruction
1864 is TARG0, TARG1, OP0.
1866 Either TARG0 or TARG1 may be zero, but what that means is that
1867 the result is not actually wanted. We will generate it into
1868 a dummy pseudo-reg and discard it. They may not both be zero.
1870 Returns 1 if this operation can be performed; 0 if not. */
1873 expand_twoval_unop (optab unoptab
, rtx op0
, rtx targ0
, rtx targ1
,
1876 enum machine_mode mode
= GET_MODE (targ0
? targ0
: targ1
);
1877 enum mode_class
class;
1878 enum machine_mode wider_mode
;
1879 rtx entry_last
= get_last_insn ();
1882 class = GET_MODE_CLASS (mode
);
1885 targ0
= gen_reg_rtx (mode
);
1887 targ1
= gen_reg_rtx (mode
);
1889 /* Record where to go back to if we fail. */
1890 last
= get_last_insn ();
1892 if (unoptab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
1894 int icode
= (int) unoptab
->handlers
[(int) mode
].insn_code
;
1895 enum machine_mode mode0
= insn_data
[icode
].operand
[2].mode
;
1899 if (GET_MODE (xop0
) != VOIDmode
1900 && GET_MODE (xop0
) != mode0
)
1901 xop0
= convert_to_mode (mode0
, xop0
, unsignedp
);
1903 /* Now, if insn doesn't accept these operands, put them into pseudos. */
1904 if (!insn_data
[icode
].operand
[2].predicate (xop0
, mode0
))
1905 xop0
= copy_to_mode_reg (mode0
, xop0
);
1907 /* We could handle this, but we should always be called with a pseudo
1908 for our targets and all insns should take them as outputs. */
1909 gcc_assert (insn_data
[icode
].operand
[0].predicate (targ0
, mode
));
1910 gcc_assert (insn_data
[icode
].operand
[1].predicate (targ1
, mode
));
1912 pat
= GEN_FCN (icode
) (targ0
, targ1
, xop0
);
1919 delete_insns_since (last
);
1922 /* It can't be done in this mode. Can we do it in a wider mode? */
1924 if (class == MODE_INT
|| class == MODE_FLOAT
|| class == MODE_COMPLEX_FLOAT
)
1926 for (wider_mode
= GET_MODE_WIDER_MODE (mode
); wider_mode
!= VOIDmode
;
1927 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
1929 if (unoptab
->handlers
[(int) wider_mode
].insn_code
1930 != CODE_FOR_nothing
)
1932 rtx t0
= gen_reg_rtx (wider_mode
);
1933 rtx t1
= gen_reg_rtx (wider_mode
);
1934 rtx cop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
1936 if (expand_twoval_unop (unoptab
, cop0
, t0
, t1
, unsignedp
))
1938 convert_move (targ0
, t0
, unsignedp
);
1939 convert_move (targ1
, t1
, unsignedp
);
1943 delete_insns_since (last
);
1948 delete_insns_since (entry_last
);
1952 /* Generate code to perform an operation specified by BINOPTAB
1953 on operands OP0 and OP1, with two results to TARG1 and TARG2.
1954 We assume that the order of the operands for the instruction
1955 is TARG0, OP0, OP1, TARG1, which would fit a pattern like
1956 [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))].
1958 Either TARG0 or TARG1 may be zero, but what that means is that
1959 the result is not actually wanted. We will generate it into
1960 a dummy pseudo-reg and discard it. They may not both be zero.
1962 Returns 1 if this operation can be performed; 0 if not. */
1965 expand_twoval_binop (optab binoptab
, rtx op0
, rtx op1
, rtx targ0
, rtx targ1
,
1968 enum machine_mode mode
= GET_MODE (targ0
? targ0
: targ1
);
1969 enum mode_class
class;
1970 enum machine_mode wider_mode
;
1971 rtx entry_last
= get_last_insn ();
1974 class = GET_MODE_CLASS (mode
);
1976 /* If we are inside an appropriately-short loop and we are optimizing,
1977 force expensive constants into a register. */
1978 if (CONSTANT_P (op0
) && optimize
1979 && rtx_cost (op0
, binoptab
->code
) > COSTS_N_INSNS (1))
1980 op0
= force_reg (mode
, op0
);
1982 if (CONSTANT_P (op1
) && optimize
1983 && rtx_cost (op1
, binoptab
->code
) > COSTS_N_INSNS (1))
1984 op1
= force_reg (mode
, op1
);
1987 targ0
= gen_reg_rtx (mode
);
1989 targ1
= gen_reg_rtx (mode
);
1991 /* Record where to go back to if we fail. */
1992 last
= get_last_insn ();
1994 if (binoptab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
1996 int icode
= (int) binoptab
->handlers
[(int) mode
].insn_code
;
1997 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
1998 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
2000 rtx xop0
= op0
, xop1
= op1
;
2002 /* In case the insn wants input operands in modes different from
2003 those of the actual operands, convert the operands. It would
2004 seem that we don't need to convert CONST_INTs, but we do, so
2005 that they're properly zero-extended, sign-extended or truncated
2008 if (GET_MODE (op0
) != mode0
&& mode0
!= VOIDmode
)
2009 xop0
= convert_modes (mode0
,
2010 GET_MODE (op0
) != VOIDmode
2015 if (GET_MODE (op1
) != mode1
&& mode1
!= VOIDmode
)
2016 xop1
= convert_modes (mode1
,
2017 GET_MODE (op1
) != VOIDmode
2022 /* Now, if insn doesn't accept these operands, put them into pseudos. */
2023 if (!insn_data
[icode
].operand
[1].predicate (xop0
, mode0
))
2024 xop0
= copy_to_mode_reg (mode0
, xop0
);
2026 if (!insn_data
[icode
].operand
[2].predicate (xop1
, mode1
))
2027 xop1
= copy_to_mode_reg (mode1
, xop1
);
2029 /* We could handle this, but we should always be called with a pseudo
2030 for our targets and all insns should take them as outputs. */
2031 gcc_assert (insn_data
[icode
].operand
[0].predicate (targ0
, mode
));
2032 gcc_assert (insn_data
[icode
].operand
[3].predicate (targ1
, mode
));
2034 pat
= GEN_FCN (icode
) (targ0
, xop0
, xop1
, targ1
);
2041 delete_insns_since (last
);
2044 /* It can't be done in this mode. Can we do it in a wider mode? */
2046 if (class == MODE_INT
|| class == MODE_FLOAT
|| class == MODE_COMPLEX_FLOAT
)
2048 for (wider_mode
= GET_MODE_WIDER_MODE (mode
); wider_mode
!= VOIDmode
;
2049 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2051 if (binoptab
->handlers
[(int) wider_mode
].insn_code
2052 != CODE_FOR_nothing
)
2054 rtx t0
= gen_reg_rtx (wider_mode
);
2055 rtx t1
= gen_reg_rtx (wider_mode
);
2056 rtx cop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
2057 rtx cop1
= convert_modes (wider_mode
, mode
, op1
, unsignedp
);
2059 if (expand_twoval_binop (binoptab
, cop0
, cop1
,
2062 convert_move (targ0
, t0
, unsignedp
);
2063 convert_move (targ1
, t1
, unsignedp
);
2067 delete_insns_since (last
);
2072 delete_insns_since (entry_last
);
2076 /* Expand the two-valued library call indicated by BINOPTAB, but
2077 preserve only one of the values. If TARG0 is non-NULL, the first
2078 value is placed into TARG0; otherwise the second value is placed
2079 into TARG1. Exactly one of TARG0 and TARG1 must be non-NULL. The
2080 value stored into TARG0 or TARG1 is equivalent to (CODE OP0 OP1).
2081 This routine assumes that the value returned by the library call is
2082 as if the return value was of an integral mode twice as wide as the
2083 mode of OP0. Returns 1 if the call was successful. */
2086 expand_twoval_binop_libfunc (optab binoptab
, rtx op0
, rtx op1
,
2087 rtx targ0
, rtx targ1
, enum rtx_code code
)
2089 enum machine_mode mode
;
2090 enum machine_mode libval_mode
;
2094 /* Exactly one of TARG0 or TARG1 should be non-NULL. */
2095 gcc_assert (!targ0
!= !targ1
);
2097 mode
= GET_MODE (op0
);
2098 if (!binoptab
->handlers
[(int) mode
].libfunc
)
2101 /* The value returned by the library function will have twice as
2102 many bits as the nominal MODE. */
2103 libval_mode
= smallest_mode_for_size (2 * GET_MODE_BITSIZE (mode
),
2106 libval
= emit_library_call_value (binoptab
->handlers
[(int) mode
].libfunc
,
2107 NULL_RTX
, LCT_CONST
,
2111 /* Get the part of VAL containing the value that we want. */
2112 libval
= simplify_gen_subreg (mode
, libval
, libval_mode
,
2113 targ0
? 0 : GET_MODE_SIZE (mode
));
2114 insns
= get_insns ();
2116 /* Move the into the desired location. */
2117 emit_libcall_block (insns
, targ0
? targ0
: targ1
, libval
,
2118 gen_rtx_fmt_ee (code
, mode
, op0
, op1
));
2124 /* Wrapper around expand_unop which takes an rtx code to specify
2125 the operation to perform, not an optab pointer. All other
2126 arguments are the same. */
2128 expand_simple_unop (enum machine_mode mode
, enum rtx_code code
, rtx op0
,
2129 rtx target
, int unsignedp
)
2131 optab unop
= code_to_optab
[(int) code
];
2134 return expand_unop (mode
, unop
, op0
, target
, unsignedp
);
2140 (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)). */
2142 widen_clz (enum machine_mode mode
, rtx op0
, rtx target
)
2144 enum mode_class
class = GET_MODE_CLASS (mode
);
2145 if (class == MODE_INT
|| class == MODE_FLOAT
|| class == MODE_COMPLEX_FLOAT
)
2147 enum machine_mode wider_mode
;
2148 for (wider_mode
= GET_MODE_WIDER_MODE (mode
); wider_mode
!= VOIDmode
;
2149 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2151 if (clz_optab
->handlers
[(int) wider_mode
].insn_code
2152 != CODE_FOR_nothing
)
2154 rtx xop0
, temp
, last
;
2156 last
= get_last_insn ();
2159 target
= gen_reg_rtx (mode
);
2160 xop0
= widen_operand (op0
, wider_mode
, mode
, true, false);
2161 temp
= expand_unop (wider_mode
, clz_optab
, xop0
, NULL_RTX
, true);
2163 temp
= expand_binop (wider_mode
, sub_optab
, temp
,
2164 GEN_INT (GET_MODE_BITSIZE (wider_mode
)
2165 - GET_MODE_BITSIZE (mode
)),
2166 target
, true, OPTAB_DIRECT
);
2168 delete_insns_since (last
);
2177 /* Try calculating (parity x) as (and (popcount x) 1), where
2178 popcount can also be done in a wider mode. */
2180 expand_parity (enum machine_mode mode
, rtx op0
, rtx target
)
2182 enum mode_class
class = GET_MODE_CLASS (mode
);
2183 if (class == MODE_INT
|| class == MODE_FLOAT
|| class == MODE_COMPLEX_FLOAT
)
2185 enum machine_mode wider_mode
;
2186 for (wider_mode
= mode
; wider_mode
!= VOIDmode
;
2187 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2189 if (popcount_optab
->handlers
[(int) wider_mode
].insn_code
2190 != CODE_FOR_nothing
)
2192 rtx xop0
, temp
, last
;
2194 last
= get_last_insn ();
2197 target
= gen_reg_rtx (mode
);
2198 xop0
= widen_operand (op0
, wider_mode
, mode
, true, false);
2199 temp
= expand_unop (wider_mode
, popcount_optab
, xop0
, NULL_RTX
,
2202 temp
= expand_binop (wider_mode
, and_optab
, temp
, const1_rtx
,
2203 target
, true, OPTAB_DIRECT
);
2205 delete_insns_since (last
);
2214 /* Extract the OMODE lowpart from VAL, which has IMODE. Under certain
2215 conditions, VAL may already be a SUBREG against which we cannot generate
2216 a further SUBREG. In this case, we expect forcing the value into a
2217 register will work around the situation. */
2220 lowpart_subreg_maybe_copy (enum machine_mode omode
, rtx val
,
2221 enum machine_mode imode
)
2224 ret
= lowpart_subreg (omode
, val
, imode
);
2227 val
= force_reg (imode
, val
);
2228 ret
= lowpart_subreg (omode
, val
, imode
);
2229 gcc_assert (ret
!= NULL
);
2234 /* Expand a floating point absolute value or negation operation via a
2235 logical operation on the sign bit. */
2238 expand_absneg_bit (enum rtx_code code
, enum machine_mode mode
,
2239 rtx op0
, rtx target
)
2241 const struct real_format
*fmt
;
2242 int bitpos
, word
, nwords
, i
;
2243 enum machine_mode imode
;
2244 HOST_WIDE_INT hi
, lo
;
2247 /* The format has to have a simple sign bit. */
2248 fmt
= REAL_MODE_FORMAT (mode
);
2252 bitpos
= fmt
->signbit_rw
;
2256 /* Don't create negative zeros if the format doesn't support them. */
2257 if (code
== NEG
&& !fmt
->has_signed_zero
)
2260 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
2262 imode
= int_mode_for_mode (mode
);
2263 if (imode
== BLKmode
)
2272 if (FLOAT_WORDS_BIG_ENDIAN
)
2273 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
2275 word
= bitpos
/ BITS_PER_WORD
;
2276 bitpos
= bitpos
% BITS_PER_WORD
;
2277 nwords
= (GET_MODE_BITSIZE (mode
) + BITS_PER_WORD
- 1) / BITS_PER_WORD
;
2280 if (bitpos
< HOST_BITS_PER_WIDE_INT
)
2283 lo
= (HOST_WIDE_INT
) 1 << bitpos
;
2287 hi
= (HOST_WIDE_INT
) 1 << (bitpos
- HOST_BITS_PER_WIDE_INT
);
2293 if (target
== 0 || target
== op0
)
2294 target
= gen_reg_rtx (mode
);
2300 for (i
= 0; i
< nwords
; ++i
)
2302 rtx targ_piece
= operand_subword (target
, i
, 1, mode
);
2303 rtx op0_piece
= operand_subword_force (op0
, i
, mode
);
2307 temp
= expand_binop (imode
, code
== ABS
? and_optab
: xor_optab
,
2309 immed_double_const (lo
, hi
, imode
),
2310 targ_piece
, 1, OPTAB_LIB_WIDEN
);
2311 if (temp
!= targ_piece
)
2312 emit_move_insn (targ_piece
, temp
);
2315 emit_move_insn (targ_piece
, op0_piece
);
2318 insns
= get_insns ();
2321 temp
= gen_rtx_fmt_e (code
, mode
, copy_rtx (op0
));
2322 emit_no_conflict_block (insns
, target
, op0
, NULL_RTX
, temp
);
2326 temp
= expand_binop (imode
, code
== ABS
? and_optab
: xor_optab
,
2327 gen_lowpart (imode
, op0
),
2328 immed_double_const (lo
, hi
, imode
),
2329 gen_lowpart (imode
, target
), 1, OPTAB_LIB_WIDEN
);
2330 target
= lowpart_subreg_maybe_copy (mode
, temp
, imode
);
2332 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
2333 gen_rtx_fmt_e (code
, mode
, copy_rtx (op0
)));
2339 /* Generate code to perform an operation specified by UNOPTAB
2340 on operand OP0, with result having machine-mode MODE.
2342 UNSIGNEDP is for the case where we have to widen the operands
2343 to perform the operation. It says to use zero-extension.
2345 If TARGET is nonzero, the value
2346 is generated there, if it is convenient to do so.
2347 In all cases an rtx is returned for the locus of the value;
2348 this may or may not be TARGET. */
2351 expand_unop (enum machine_mode mode
, optab unoptab
, rtx op0
, rtx target
,
2354 enum mode_class
class;
2355 enum machine_mode wider_mode
;
2357 rtx last
= get_last_insn ();
2360 class = GET_MODE_CLASS (mode
);
2362 if (unoptab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
2364 int icode
= (int) unoptab
->handlers
[(int) mode
].insn_code
;
2365 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
2371 temp
= gen_reg_rtx (mode
);
2373 if (GET_MODE (xop0
) != VOIDmode
2374 && GET_MODE (xop0
) != mode0
)
2375 xop0
= convert_to_mode (mode0
, xop0
, unsignedp
);
2377 /* Now, if insn doesn't accept our operand, put it into a pseudo. */
2379 if (!insn_data
[icode
].operand
[1].predicate (xop0
, mode0
))
2380 xop0
= copy_to_mode_reg (mode0
, xop0
);
2382 if (!insn_data
[icode
].operand
[0].predicate (temp
, mode
))
2383 temp
= gen_reg_rtx (mode
);
2385 pat
= GEN_FCN (icode
) (temp
, xop0
);
2388 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
2389 && ! add_equal_note (pat
, temp
, unoptab
->code
, xop0
, NULL_RTX
))
2391 delete_insns_since (last
);
2392 return expand_unop (mode
, unoptab
, op0
, NULL_RTX
, unsignedp
);
2400 delete_insns_since (last
);
2403 /* It can't be done in this mode. Can we open-code it in a wider mode? */
2405 /* Widening clz needs special treatment. */
2406 if (unoptab
== clz_optab
)
2408 temp
= widen_clz (mode
, op0
, target
);
2415 if (class == MODE_INT
|| class == MODE_FLOAT
|| class == MODE_COMPLEX_FLOAT
)
2416 for (wider_mode
= GET_MODE_WIDER_MODE (mode
); wider_mode
!= VOIDmode
;
2417 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2419 if (unoptab
->handlers
[(int) wider_mode
].insn_code
!= CODE_FOR_nothing
)
2423 /* For certain operations, we need not actually extend
2424 the narrow operand, as long as we will truncate the
2425 results to the same narrowness. */
2427 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
2428 (unoptab
== neg_optab
2429 || unoptab
== one_cmpl_optab
)
2430 && class == MODE_INT
);
2432 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
2437 if (class != MODE_INT
)
2440 target
= gen_reg_rtx (mode
);
2441 convert_move (target
, temp
, 0);
2445 return gen_lowpart (mode
, temp
);
2448 delete_insns_since (last
);
2452 /* These can be done a word at a time. */
2453 if (unoptab
== one_cmpl_optab
2454 && class == MODE_INT
2455 && GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2456 && unoptab
->handlers
[(int) word_mode
].insn_code
!= CODE_FOR_nothing
)
2461 if (target
== 0 || target
== op0
)
2462 target
= gen_reg_rtx (mode
);
2466 /* Do the actual arithmetic. */
2467 for (i
= 0; i
< GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
; i
++)
2469 rtx target_piece
= operand_subword (target
, i
, 1, mode
);
2470 rtx x
= expand_unop (word_mode
, unoptab
,
2471 operand_subword_force (op0
, i
, mode
),
2472 target_piece
, unsignedp
);
2474 if (target_piece
!= x
)
2475 emit_move_insn (target_piece
, x
);
2478 insns
= get_insns ();
2481 emit_no_conflict_block (insns
, target
, op0
, NULL_RTX
,
2482 gen_rtx_fmt_e (unoptab
->code
, mode
,
2487 if (unoptab
->code
== NEG
)
2489 /* Try negating floating point values by flipping the sign bit. */
2490 if (class == MODE_FLOAT
)
2492 temp
= expand_absneg_bit (NEG
, mode
, op0
, target
);
2497 /* If there is no negation pattern, and we have no negative zero,
2498 try subtracting from zero. */
2499 if (!HONOR_SIGNED_ZEROS (mode
))
2501 temp
= expand_binop (mode
, (unoptab
== negv_optab
2502 ? subv_optab
: sub_optab
),
2503 CONST0_RTX (mode
), op0
, target
,
2504 unsignedp
, OPTAB_DIRECT
);
2510 /* Try calculating parity (x) as popcount (x) % 2. */
2511 if (unoptab
== parity_optab
)
2513 temp
= expand_parity (mode
, op0
, target
);
2519 /* Now try a library call in this mode. */
2520 if (unoptab
->handlers
[(int) mode
].libfunc
)
2524 enum machine_mode outmode
= mode
;
2526 /* All of these functions return small values. Thus we choose to
2527 have them return something that isn't a double-word. */
2528 if (unoptab
== ffs_optab
|| unoptab
== clz_optab
|| unoptab
== ctz_optab
2529 || unoptab
== popcount_optab
|| unoptab
== parity_optab
)
2531 = GET_MODE (hard_libcall_value (TYPE_MODE (integer_type_node
)));
2535 /* Pass 1 for NO_QUEUE so we don't lose any increments
2536 if the libcall is cse'd or moved. */
2537 value
= emit_library_call_value (unoptab
->handlers
[(int) mode
].libfunc
,
2538 NULL_RTX
, LCT_CONST
, outmode
,
2540 insns
= get_insns ();
2543 target
= gen_reg_rtx (outmode
);
2544 emit_libcall_block (insns
, target
, value
,
2545 gen_rtx_fmt_e (unoptab
->code
, mode
, op0
));
2550 /* It can't be done in this mode. Can we do it in a wider mode? */
2552 if (class == MODE_INT
|| class == MODE_FLOAT
|| class == MODE_COMPLEX_FLOAT
)
2554 for (wider_mode
= GET_MODE_WIDER_MODE (mode
); wider_mode
!= VOIDmode
;
2555 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2557 if ((unoptab
->handlers
[(int) wider_mode
].insn_code
2558 != CODE_FOR_nothing
)
2559 || unoptab
->handlers
[(int) wider_mode
].libfunc
)
2563 /* For certain operations, we need not actually extend
2564 the narrow operand, as long as we will truncate the
2565 results to the same narrowness. */
2567 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
2568 (unoptab
== neg_optab
2569 || unoptab
== one_cmpl_optab
)
2570 && class == MODE_INT
);
2572 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
2575 /* If we are generating clz using wider mode, adjust the
2577 if (unoptab
== clz_optab
&& temp
!= 0)
2578 temp
= expand_binop (wider_mode
, sub_optab
, temp
,
2579 GEN_INT (GET_MODE_BITSIZE (wider_mode
)
2580 - GET_MODE_BITSIZE (mode
)),
2581 target
, true, OPTAB_DIRECT
);
2585 if (class != MODE_INT
)
2588 target
= gen_reg_rtx (mode
);
2589 convert_move (target
, temp
, 0);
2593 return gen_lowpart (mode
, temp
);
2596 delete_insns_since (last
);
2601 /* One final attempt at implementing negation via subtraction,
2602 this time allowing widening of the operand. */
2603 if (unoptab
->code
== NEG
&& !HONOR_SIGNED_ZEROS (mode
))
2606 temp
= expand_binop (mode
,
2607 unoptab
== negv_optab
? subv_optab
: sub_optab
,
2608 CONST0_RTX (mode
), op0
,
2609 target
, unsignedp
, OPTAB_LIB_WIDEN
);
2617 /* Emit code to compute the absolute value of OP0, with result to
2618 TARGET if convenient. (TARGET may be 0.) The return value says
2619 where the result actually is to be found.
2621 MODE is the mode of the operand; the mode of the result is
2622 different but can be deduced from MODE.
2627 expand_abs_nojump (enum machine_mode mode
, rtx op0
, rtx target
,
2628 int result_unsignedp
)
2633 result_unsignedp
= 1;
2635 /* First try to do it with a special abs instruction. */
2636 temp
= expand_unop (mode
, result_unsignedp
? abs_optab
: absv_optab
,
2641 /* For floating point modes, try clearing the sign bit. */
2642 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2644 temp
= expand_absneg_bit (ABS
, mode
, op0
, target
);
2649 /* If we have a MAX insn, we can do this as MAX (x, -x). */
2650 if (smax_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
2651 && !HONOR_SIGNED_ZEROS (mode
))
2653 rtx last
= get_last_insn ();
2655 temp
= expand_unop (mode
, neg_optab
, op0
, NULL_RTX
, 0);
2657 temp
= expand_binop (mode
, smax_optab
, op0
, temp
, target
, 0,
2663 delete_insns_since (last
);
2666 /* If this machine has expensive jumps, we can do integer absolute
2667 value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)),
2668 where W is the width of MODE. */
2670 if (GET_MODE_CLASS (mode
) == MODE_INT
&& BRANCH_COST
>= 2)
2672 rtx extended
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
2673 size_int (GET_MODE_BITSIZE (mode
) - 1),
2676 temp
= expand_binop (mode
, xor_optab
, extended
, op0
, target
, 0,
2679 temp
= expand_binop (mode
, result_unsignedp
? sub_optab
: subv_optab
,
2680 temp
, extended
, target
, 0, OPTAB_LIB_WIDEN
);
2690 expand_abs (enum machine_mode mode
, rtx op0
, rtx target
,
2691 int result_unsignedp
, int safe
)
2696 result_unsignedp
= 1;
2698 temp
= expand_abs_nojump (mode
, op0
, target
, result_unsignedp
);
2702 /* If that does not win, use conditional jump and negate. */
2704 /* It is safe to use the target if it is the same
2705 as the source if this is also a pseudo register */
2706 if (op0
== target
&& REG_P (op0
)
2707 && REGNO (op0
) >= FIRST_PSEUDO_REGISTER
)
2710 op1
= gen_label_rtx ();
2711 if (target
== 0 || ! safe
2712 || GET_MODE (target
) != mode
2713 || (MEM_P (target
) && MEM_VOLATILE_P (target
))
2715 && REGNO (target
) < FIRST_PSEUDO_REGISTER
))
2716 target
= gen_reg_rtx (mode
);
2718 emit_move_insn (target
, op0
);
2721 /* If this mode is an integer too wide to compare properly,
2722 compare word by word. Rely on CSE to optimize constant cases. */
2723 if (GET_MODE_CLASS (mode
) == MODE_INT
2724 && ! can_compare_p (GE
, mode
, ccp_jump
))
2725 do_jump_by_parts_greater_rtx (mode
, 0, target
, const0_rtx
,
2728 do_compare_rtx_and_jump (target
, CONST0_RTX (mode
), GE
, 0, mode
,
2729 NULL_RTX
, NULL_RTX
, op1
);
2731 op0
= expand_unop (mode
, result_unsignedp
? neg_optab
: negv_optab
,
2734 emit_move_insn (target
, op0
);
2740 /* A subroutine of expand_copysign, perform the copysign operation using the
2741 abs and neg primitives advertised to exist on the target. The assumption
2742 is that we have a split register file, and leaving op0 in fp registers,
2743 and not playing with subregs so much, will help the register allocator. */
2746 expand_copysign_absneg (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
2747 int bitpos
, bool op0_is_abs
)
2749 enum machine_mode imode
;
2750 HOST_WIDE_INT hi
, lo
;
2759 op0
= expand_unop (mode
, abs_optab
, op0
, target
, 0);
2766 if (target
== NULL_RTX
)
2767 target
= copy_to_reg (op0
);
2769 emit_move_insn (target
, op0
);
2772 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
2774 imode
= int_mode_for_mode (mode
);
2775 if (imode
== BLKmode
)
2777 op1
= gen_lowpart (imode
, op1
);
2782 if (FLOAT_WORDS_BIG_ENDIAN
)
2783 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
2785 word
= bitpos
/ BITS_PER_WORD
;
2786 bitpos
= bitpos
% BITS_PER_WORD
;
2787 op1
= operand_subword_force (op1
, word
, mode
);
2790 if (bitpos
< HOST_BITS_PER_WIDE_INT
)
2793 lo
= (HOST_WIDE_INT
) 1 << bitpos
;
2797 hi
= (HOST_WIDE_INT
) 1 << (bitpos
- HOST_BITS_PER_WIDE_INT
);
2801 op1
= expand_binop (imode
, and_optab
, op1
,
2802 immed_double_const (lo
, hi
, imode
),
2803 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
2805 label
= gen_label_rtx ();
2806 emit_cmp_and_jump_insns (op1
, const0_rtx
, EQ
, NULL_RTX
, imode
, 1, label
);
2808 if (GET_CODE (op0
) == CONST_DOUBLE
)
2809 op0
= simplify_unary_operation (NEG
, mode
, op0
, mode
);
2811 op0
= expand_unop (mode
, neg_optab
, op0
, target
, 0);
2813 emit_move_insn (target
, op0
);
2821 /* A subroutine of expand_copysign, perform the entire copysign operation
2822 with integer bitmasks. BITPOS is the position of the sign bit; OP0_IS_ABS
2823 is true if op0 is known to have its sign bit clear. */
2826 expand_copysign_bit (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
2827 int bitpos
, bool op0_is_abs
)
2829 enum machine_mode imode
;
2830 HOST_WIDE_INT hi
, lo
;
2831 int word
, nwords
, i
;
2834 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
2836 imode
= int_mode_for_mode (mode
);
2837 if (imode
== BLKmode
)
2846 if (FLOAT_WORDS_BIG_ENDIAN
)
2847 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
2849 word
= bitpos
/ BITS_PER_WORD
;
2850 bitpos
= bitpos
% BITS_PER_WORD
;
2851 nwords
= (GET_MODE_BITSIZE (mode
) + BITS_PER_WORD
- 1) / BITS_PER_WORD
;
2854 if (bitpos
< HOST_BITS_PER_WIDE_INT
)
2857 lo
= (HOST_WIDE_INT
) 1 << bitpos
;
2861 hi
= (HOST_WIDE_INT
) 1 << (bitpos
- HOST_BITS_PER_WIDE_INT
);
2865 if (target
== 0 || target
== op0
|| target
== op1
)
2866 target
= gen_reg_rtx (mode
);
2872 for (i
= 0; i
< nwords
; ++i
)
2874 rtx targ_piece
= operand_subword (target
, i
, 1, mode
);
2875 rtx op0_piece
= operand_subword_force (op0
, i
, mode
);
2880 op0_piece
= expand_binop (imode
, and_optab
, op0_piece
,
2881 immed_double_const (~lo
, ~hi
, imode
),
2882 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
2884 op1
= expand_binop (imode
, and_optab
,
2885 operand_subword_force (op1
, i
, mode
),
2886 immed_double_const (lo
, hi
, imode
),
2887 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
2889 temp
= expand_binop (imode
, ior_optab
, op0_piece
, op1
,
2890 targ_piece
, 1, OPTAB_LIB_WIDEN
);
2891 if (temp
!= targ_piece
)
2892 emit_move_insn (targ_piece
, temp
);
2895 emit_move_insn (targ_piece
, op0_piece
);
2898 insns
= get_insns ();
2901 emit_no_conflict_block (insns
, target
, op0
, op1
, NULL_RTX
);
2905 op1
= expand_binop (imode
, and_optab
, gen_lowpart (imode
, op1
),
2906 immed_double_const (lo
, hi
, imode
),
2907 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
2909 op0
= gen_lowpart (imode
, op0
);
2911 op0
= expand_binop (imode
, and_optab
, op0
,
2912 immed_double_const (~lo
, ~hi
, imode
),
2913 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
2915 temp
= expand_binop (imode
, ior_optab
, op0
, op1
,
2916 gen_lowpart (imode
, target
), 1, OPTAB_LIB_WIDEN
);
2917 target
= lowpart_subreg_maybe_copy (mode
, temp
, imode
);
2923 /* Expand the C99 copysign operation. OP0 and OP1 must be the same
2924 scalar floating point mode. Return NULL if we do not know how to
2925 expand the operation inline. */
2928 expand_copysign (rtx op0
, rtx op1
, rtx target
)
2930 enum machine_mode mode
= GET_MODE (op0
);
2931 const struct real_format
*fmt
;
2935 gcc_assert (SCALAR_FLOAT_MODE_P (mode
));
2936 gcc_assert (GET_MODE (op1
) == mode
);
2938 /* First try to do it with a special instruction. */
2939 temp
= expand_binop (mode
, copysign_optab
, op0
, op1
,
2940 target
, 0, OPTAB_DIRECT
);
2944 fmt
= REAL_MODE_FORMAT (mode
);
2945 if (fmt
== NULL
|| !fmt
->has_signed_zero
)
2949 if (GET_CODE (op0
) == CONST_DOUBLE
)
2951 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0
)))
2952 op0
= simplify_unary_operation (ABS
, mode
, op0
, mode
);
2956 if (fmt
->signbit_ro
>= 0
2957 && (GET_CODE (op0
) == CONST_DOUBLE
2958 || (neg_optab
->handlers
[mode
].insn_code
!= CODE_FOR_nothing
2959 && abs_optab
->handlers
[mode
].insn_code
!= CODE_FOR_nothing
)))
2961 temp
= expand_copysign_absneg (mode
, op0
, op1
, target
,
2962 fmt
->signbit_ro
, op0_is_abs
);
2967 if (fmt
->signbit_rw
< 0)
2969 return expand_copysign_bit (mode
, op0
, op1
, target
,
2970 fmt
->signbit_rw
, op0_is_abs
);
2973 /* Generate an instruction whose insn-code is INSN_CODE,
2974 with two operands: an output TARGET and an input OP0.
2975 TARGET *must* be nonzero, and the output is always stored there.
2976 CODE is an rtx code such that (CODE OP0) is an rtx that describes
2977 the value that is stored into TARGET. */
2980 emit_unop_insn (int icode
, rtx target
, rtx op0
, enum rtx_code code
)
2983 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
2988 /* Now, if insn does not accept our operands, put them into pseudos. */
2990 if (!insn_data
[icode
].operand
[1].predicate (op0
, mode0
))
2991 op0
= copy_to_mode_reg (mode0
, op0
);
2993 if (!insn_data
[icode
].operand
[0].predicate (temp
, GET_MODE (temp
)))
2994 temp
= gen_reg_rtx (GET_MODE (temp
));
2996 pat
= GEN_FCN (icode
) (temp
, op0
);
2998 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
&& code
!= UNKNOWN
)
2999 add_equal_note (pat
, temp
, code
, op0
, NULL_RTX
);
3004 emit_move_insn (target
, temp
);
3007 struct no_conflict_data
3009 rtx target
, first
, insn
;
3013 /* Called via note_stores by emit_no_conflict_block and emit_libcall_block.
3014 Set P->must_stay if the currently examined clobber / store has to stay
3015 in the list of insns that constitute the actual no_conflict block /
3018 no_conflict_move_test (rtx dest
, rtx set
, void *p0
)
3020 struct no_conflict_data
*p
= p0
;
3022 /* If this inns directly contributes to setting the target, it must stay. */
3023 if (reg_overlap_mentioned_p (p
->target
, dest
))
3024 p
->must_stay
= true;
3025 /* If we haven't committed to keeping any other insns in the list yet,
3026 there is nothing more to check. */
3027 else if (p
->insn
== p
->first
)
3029 /* If this insn sets / clobbers a register that feeds one of the insns
3030 already in the list, this insn has to stay too. */
3031 else if (reg_overlap_mentioned_p (dest
, PATTERN (p
->first
))
3032 || (CALL_P (p
->first
) && (find_reg_fusage (p
->first
, USE
, dest
)))
3033 || reg_used_between_p (dest
, p
->first
, p
->insn
)
3034 /* Likewise if this insn depends on a register set by a previous
3035 insn in the list, or if it sets a result (presumably a hard
3036 register) that is set or clobbered by a previous insn.
3037 N.B. the modified_*_p (SET_DEST...) tests applied to a MEM
3038 SET_DEST perform the former check on the address, and the latter
3039 check on the MEM. */
3040 || (GET_CODE (set
) == SET
3041 && (modified_in_p (SET_SRC (set
), p
->first
)
3042 || modified_in_p (SET_DEST (set
), p
->first
)
3043 || modified_between_p (SET_SRC (set
), p
->first
, p
->insn
)
3044 || modified_between_p (SET_DEST (set
), p
->first
, p
->insn
))))
3045 p
->must_stay
= true;
3048 /* Emit code to perform a series of operations on a multi-word quantity, one
3051 Such a block is preceded by a CLOBBER of the output, consists of multiple
3052 insns, each setting one word of the output, and followed by a SET copying
3053 the output to itself.
3055 Each of the insns setting words of the output receives a REG_NO_CONFLICT
3056 note indicating that it doesn't conflict with the (also multi-word)
3057 inputs. The entire block is surrounded by REG_LIBCALL and REG_RETVAL
3060 INSNS is a block of code generated to perform the operation, not including
3061 the CLOBBER and final copy. All insns that compute intermediate values
3062 are first emitted, followed by the block as described above.
3064 TARGET, OP0, and OP1 are the output and inputs of the operations,
3065 respectively. OP1 may be zero for a unary operation.
3067 EQUIV, if nonzero, is an expression to be placed into a REG_EQUAL note
3070 If TARGET is not a register, INSNS is simply emitted with no special
3071 processing. Likewise if anything in INSNS is not an INSN or if
3072 there is a libcall block inside INSNS.
3074 The final insn emitted is returned. */
3077 emit_no_conflict_block (rtx insns
, rtx target
, rtx op0
, rtx op1
, rtx equiv
)
3079 rtx prev
, next
, first
, last
, insn
;
3081 if (!REG_P (target
) || reload_in_progress
)
3082 return emit_insn (insns
);
3084 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3085 if (!NONJUMP_INSN_P (insn
)
3086 || find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
))
3087 return emit_insn (insns
);
3089 /* First emit all insns that do not store into words of the output and remove
3090 these from the list. */
3091 for (insn
= insns
; insn
; insn
= next
)
3094 struct no_conflict_data data
;
3096 next
= NEXT_INSN (insn
);
3098 /* Some ports (cris) create a libcall regions at their own. We must
3099 avoid any potential nesting of LIBCALLs. */
3100 if ((note
= find_reg_note (insn
, REG_LIBCALL
, NULL
)) != NULL
)
3101 remove_note (insn
, note
);
3102 if ((note
= find_reg_note (insn
, REG_RETVAL
, NULL
)) != NULL
)
3103 remove_note (insn
, note
);
3105 data
.target
= target
;
3109 note_stores (PATTERN (insn
), no_conflict_move_test
, &data
);
3110 if (! data
.must_stay
)
3112 if (PREV_INSN (insn
))
3113 NEXT_INSN (PREV_INSN (insn
)) = next
;
3118 PREV_INSN (next
) = PREV_INSN (insn
);
3124 prev
= get_last_insn ();
3126 /* Now write the CLOBBER of the output, followed by the setting of each
3127 of the words, followed by the final copy. */
3128 if (target
!= op0
&& target
!= op1
)
3129 emit_insn (gen_rtx_CLOBBER (VOIDmode
, target
));
3131 for (insn
= insns
; insn
; insn
= next
)
3133 next
= NEXT_INSN (insn
);
3136 if (op1
&& REG_P (op1
))
3137 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_NO_CONFLICT
, op1
,
3140 if (op0
&& REG_P (op0
))
3141 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_NO_CONFLICT
, op0
,
3145 if (mov_optab
->handlers
[(int) GET_MODE (target
)].insn_code
3146 != CODE_FOR_nothing
)
3148 last
= emit_move_insn (target
, target
);
3150 set_unique_reg_note (last
, REG_EQUAL
, equiv
);
3154 last
= get_last_insn ();
3156 /* Remove any existing REG_EQUAL note from "last", or else it will
3157 be mistaken for a note referring to the full contents of the
3158 alleged libcall value when found together with the REG_RETVAL
3159 note added below. An existing note can come from an insn
3160 expansion at "last". */
3161 remove_note (last
, find_reg_note (last
, REG_EQUAL
, NULL_RTX
));
3165 first
= get_insns ();
3167 first
= NEXT_INSN (prev
);
3169 /* Encapsulate the block so it gets manipulated as a unit. */
3170 REG_NOTES (first
) = gen_rtx_INSN_LIST (REG_LIBCALL
, last
,
3172 REG_NOTES (last
) = gen_rtx_INSN_LIST (REG_RETVAL
, first
, REG_NOTES (last
));
3177 /* Emit code to make a call to a constant function or a library call.
3179 INSNS is a list containing all insns emitted in the call.
3180 These insns leave the result in RESULT. Our block is to copy RESULT
3181 to TARGET, which is logically equivalent to EQUIV.
3183 We first emit any insns that set a pseudo on the assumption that these are
3184 loading constants into registers; doing so allows them to be safely cse'ed
3185 between blocks. Then we emit all the other insns in the block, followed by
3186 an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL
3187 note with an operand of EQUIV.
3189 Moving assignments to pseudos outside of the block is done to improve
3190 the generated code, but is not required to generate correct code,
3191 hence being unable to move an assignment is not grounds for not making
3192 a libcall block. There are two reasons why it is safe to leave these
3193 insns inside the block: First, we know that these pseudos cannot be
3194 used in generated RTL outside the block since they are created for
3195 temporary purposes within the block. Second, CSE will not record the
3196 values of anything set inside a libcall block, so we know they must
3197 be dead at the end of the block.
3199 Except for the first group of insns (the ones setting pseudos), the
3200 block is delimited by REG_RETVAL and REG_LIBCALL notes. */
3203 emit_libcall_block (rtx insns
, rtx target
, rtx result
, rtx equiv
)
3205 rtx final_dest
= target
;
3206 rtx prev
, next
, first
, last
, insn
;
3208 /* If this is a reg with REG_USERVAR_P set, then it could possibly turn
3209 into a MEM later. Protect the libcall block from this change. */
3210 if (! REG_P (target
) || REG_USERVAR_P (target
))
3211 target
= gen_reg_rtx (GET_MODE (target
));
3213 /* If we're using non-call exceptions, a libcall corresponding to an
3214 operation that may trap may also trap. */
3215 if (flag_non_call_exceptions
&& may_trap_p (equiv
))
3217 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3220 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
3222 if (note
!= 0 && INTVAL (XEXP (note
, 0)) <= 0)
3223 remove_note (insn
, note
);
3227 /* look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION
3228 reg note to indicate that this call cannot throw or execute a nonlocal
3229 goto (unless there is already a REG_EH_REGION note, in which case
3231 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3234 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
3237 XEXP (note
, 0) = constm1_rtx
;
3239 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EH_REGION
, constm1_rtx
,
3243 /* First emit all insns that set pseudos. Remove them from the list as
3244 we go. Avoid insns that set pseudos which were referenced in previous
3245 insns. These can be generated by move_by_pieces, for example,
3246 to update an address. Similarly, avoid insns that reference things
3247 set in previous insns. */
3249 for (insn
= insns
; insn
; insn
= next
)
3251 rtx set
= single_set (insn
);
3254 /* Some ports (cris) create a libcall regions at their own. We must
3255 avoid any potential nesting of LIBCALLs. */
3256 if ((note
= find_reg_note (insn
, REG_LIBCALL
, NULL
)) != NULL
)
3257 remove_note (insn
, note
);
3258 if ((note
= find_reg_note (insn
, REG_RETVAL
, NULL
)) != NULL
)
3259 remove_note (insn
, note
);
3261 next
= NEXT_INSN (insn
);
3263 if (set
!= 0 && REG_P (SET_DEST (set
))
3264 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
3266 struct no_conflict_data data
;
3268 data
.target
= const0_rtx
;
3272 note_stores (PATTERN (insn
), no_conflict_move_test
, &data
);
3273 if (! data
.must_stay
)
3275 if (PREV_INSN (insn
))
3276 NEXT_INSN (PREV_INSN (insn
)) = next
;
3281 PREV_INSN (next
) = PREV_INSN (insn
);
3287 /* Some ports use a loop to copy large arguments onto the stack.
3288 Don't move anything outside such a loop. */
3293 prev
= get_last_insn ();
3295 /* Write the remaining insns followed by the final copy. */
3297 for (insn
= insns
; insn
; insn
= next
)
3299 next
= NEXT_INSN (insn
);
3304 last
= emit_move_insn (target
, result
);
3305 if (mov_optab
->handlers
[(int) GET_MODE (target
)].insn_code
3306 != CODE_FOR_nothing
)
3307 set_unique_reg_note (last
, REG_EQUAL
, copy_rtx (equiv
));
3310 /* Remove any existing REG_EQUAL note from "last", or else it will
3311 be mistaken for a note referring to the full contents of the
3312 libcall value when found together with the REG_RETVAL note added
3313 below. An existing note can come from an insn expansion at
3315 remove_note (last
, find_reg_note (last
, REG_EQUAL
, NULL_RTX
));
3318 if (final_dest
!= target
)
3319 emit_move_insn (final_dest
, target
);
3322 first
= get_insns ();
3324 first
= NEXT_INSN (prev
);
3326 /* Encapsulate the block so it gets manipulated as a unit. */
3327 if (!flag_non_call_exceptions
|| !may_trap_p (equiv
))
3329 /* We can't attach the REG_LIBCALL and REG_RETVAL notes
3330 when the encapsulated region would not be in one basic block,
3331 i.e. when there is a control_flow_insn_p insn between FIRST and LAST.
3333 bool attach_libcall_retval_notes
= true;
3334 next
= NEXT_INSN (last
);
3335 for (insn
= first
; insn
!= next
; insn
= NEXT_INSN (insn
))
3336 if (control_flow_insn_p (insn
))
3338 attach_libcall_retval_notes
= false;
3342 if (attach_libcall_retval_notes
)
3344 REG_NOTES (first
) = gen_rtx_INSN_LIST (REG_LIBCALL
, last
,
3346 REG_NOTES (last
) = gen_rtx_INSN_LIST (REG_RETVAL
, first
,
3352 /* Nonzero if we can perform a comparison of mode MODE straightforwardly.
3353 PURPOSE describes how this comparison will be used. CODE is the rtx
3354 comparison code we will be using.
3356 ??? Actually, CODE is slightly weaker than that. A target is still
3357 required to implement all of the normal bcc operations, but not
3358 required to implement all (or any) of the unordered bcc operations. */
3361 can_compare_p (enum rtx_code code
, enum machine_mode mode
,
3362 enum can_compare_purpose purpose
)
3366 if (cmp_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
3368 if (purpose
== ccp_jump
)
3369 return bcc_gen_fctn
[(int) code
] != NULL
;
3370 else if (purpose
== ccp_store_flag
)
3371 return setcc_gen_code
[(int) code
] != CODE_FOR_nothing
;
3373 /* There's only one cmov entry point, and it's allowed to fail. */
3376 if (purpose
== ccp_jump
3377 && cbranch_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
3379 if (purpose
== ccp_cmov
3380 && cmov_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
3382 if (purpose
== ccp_store_flag
3383 && cstore_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
3385 mode
= GET_MODE_WIDER_MODE (mode
);
3387 while (mode
!= VOIDmode
);
3392 /* This function is called when we are going to emit a compare instruction that
3393 compares the values found in *PX and *PY, using the rtl operator COMPARISON.
3395 *PMODE is the mode of the inputs (in case they are const_int).
3396 *PUNSIGNEDP nonzero says that the operands are unsigned;
3397 this matters if they need to be widened.
3399 If they have mode BLKmode, then SIZE specifies the size of both operands.
3401 This function performs all the setup necessary so that the caller only has
3402 to emit a single comparison insn. This setup can involve doing a BLKmode
3403 comparison or emitting a library call to perform the comparison if no insn
3404 is available to handle it.
3405 The values which are passed in through pointers can be modified; the caller
3406 should perform the comparison on the modified values. Constant
3407 comparisons must have already been folded. */
3410 prepare_cmp_insn (rtx
*px
, rtx
*py
, enum rtx_code
*pcomparison
, rtx size
,
3411 enum machine_mode
*pmode
, int *punsignedp
,
3412 enum can_compare_purpose purpose
)
3414 enum machine_mode mode
= *pmode
;
3415 rtx x
= *px
, y
= *py
;
3416 int unsignedp
= *punsignedp
;
3417 enum mode_class
class;
3419 class = GET_MODE_CLASS (mode
);
3421 /* If we are inside an appropriately-short loop and we are optimizing,
3422 force expensive constants into a register. */
3423 if (CONSTANT_P (x
) && optimize
3424 && rtx_cost (x
, COMPARE
) > COSTS_N_INSNS (1))
3425 x
= force_reg (mode
, x
);
3427 if (CONSTANT_P (y
) && optimize
3428 && rtx_cost (y
, COMPARE
) > COSTS_N_INSNS (1))
3429 y
= force_reg (mode
, y
);
3432 /* Make sure if we have a canonical comparison. The RTL
3433 documentation states that canonical comparisons are required only
3434 for targets which have cc0. */
3435 gcc_assert (!CONSTANT_P (x
) || CONSTANT_P (y
));
3438 /* Don't let both operands fail to indicate the mode. */
3439 if (GET_MODE (x
) == VOIDmode
&& GET_MODE (y
) == VOIDmode
)
3440 x
= force_reg (mode
, x
);
3442 /* Handle all BLKmode compares. */
3444 if (mode
== BLKmode
)
3446 enum machine_mode cmp_mode
, result_mode
;
3447 enum insn_code cmp_code
;
3452 = GEN_INT (MIN (MEM_ALIGN (x
), MEM_ALIGN (y
)) / BITS_PER_UNIT
);
3456 /* Try to use a memory block compare insn - either cmpstr
3457 or cmpmem will do. */
3458 for (cmp_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
3459 cmp_mode
!= VOIDmode
;
3460 cmp_mode
= GET_MODE_WIDER_MODE (cmp_mode
))
3462 cmp_code
= cmpmem_optab
[cmp_mode
];
3463 if (cmp_code
== CODE_FOR_nothing
)
3464 cmp_code
= cmpstr_optab
[cmp_mode
];
3465 if (cmp_code
== CODE_FOR_nothing
)
3466 cmp_code
= cmpstrn_optab
[cmp_mode
];
3467 if (cmp_code
== CODE_FOR_nothing
)
3470 /* Must make sure the size fits the insn's mode. */
3471 if ((GET_CODE (size
) == CONST_INT
3472 && INTVAL (size
) >= (1 << GET_MODE_BITSIZE (cmp_mode
)))
3473 || (GET_MODE_BITSIZE (GET_MODE (size
))
3474 > GET_MODE_BITSIZE (cmp_mode
)))
3477 result_mode
= insn_data
[cmp_code
].operand
[0].mode
;
3478 result
= gen_reg_rtx (result_mode
);
3479 size
= convert_to_mode (cmp_mode
, size
, 1);
3480 emit_insn (GEN_FCN (cmp_code
) (result
, x
, y
, size
, opalign
));
3484 *pmode
= result_mode
;
3488 /* Otherwise call a library function, memcmp. */
3489 libfunc
= memcmp_libfunc
;
3490 length_type
= sizetype
;
3491 result_mode
= TYPE_MODE (integer_type_node
);
3492 cmp_mode
= TYPE_MODE (length_type
);
3493 size
= convert_to_mode (TYPE_MODE (length_type
), size
,
3494 TYPE_UNSIGNED (length_type
));
3496 result
= emit_library_call_value (libfunc
, 0, LCT_PURE_MAKE_BLOCK
,
3503 *pmode
= result_mode
;
3507 /* Don't allow operands to the compare to trap, as that can put the
3508 compare and branch in different basic blocks. */
3509 if (flag_non_call_exceptions
)
3512 x
= force_reg (mode
, x
);
3514 y
= force_reg (mode
, y
);
3519 if (can_compare_p (*pcomparison
, mode
, purpose
))
3522 /* Handle a lib call just for the mode we are using. */
3524 if (cmp_optab
->handlers
[(int) mode
].libfunc
&& class != MODE_FLOAT
)
3526 rtx libfunc
= cmp_optab
->handlers
[(int) mode
].libfunc
;
3529 /* If we want unsigned, and this mode has a distinct unsigned
3530 comparison routine, use that. */
3531 if (unsignedp
&& ucmp_optab
->handlers
[(int) mode
].libfunc
)
3532 libfunc
= ucmp_optab
->handlers
[(int) mode
].libfunc
;
3534 result
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST_MAKE_BLOCK
,
3535 word_mode
, 2, x
, mode
, y
, mode
);
3539 if (TARGET_LIB_INT_CMP_BIASED
)
3540 /* Integer comparison returns a result that must be compared
3541 against 1, so that even if we do an unsigned compare
3542 afterward, there is still a value that can represent the
3543 result "less than". */
3553 gcc_assert (class == MODE_FLOAT
);
3554 prepare_float_lib_cmp (px
, py
, pcomparison
, pmode
, punsignedp
);
3557 /* Before emitting an insn with code ICODE, make sure that X, which is going
3558 to be used for operand OPNUM of the insn, is converted from mode MODE to
3559 WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and
3560 that it is accepted by the operand predicate. Return the new value. */
3563 prepare_operand (int icode
, rtx x
, int opnum
, enum machine_mode mode
,
3564 enum machine_mode wider_mode
, int unsignedp
)
3566 if (mode
!= wider_mode
)
3567 x
= convert_modes (wider_mode
, mode
, x
, unsignedp
);
3569 if (!insn_data
[icode
].operand
[opnum
].predicate
3570 (x
, insn_data
[icode
].operand
[opnum
].mode
))
3574 x
= copy_to_mode_reg (insn_data
[icode
].operand
[opnum
].mode
, x
);
3580 /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know
3581 we can do the comparison.
3582 The arguments are the same as for emit_cmp_and_jump_insns; but LABEL may
3583 be NULL_RTX which indicates that only a comparison is to be generated. */
3586 emit_cmp_and_jump_insn_1 (rtx x
, rtx y
, enum machine_mode mode
,
3587 enum rtx_code comparison
, int unsignedp
, rtx label
)
3589 rtx test
= gen_rtx_fmt_ee (comparison
, mode
, x
, y
);
3590 enum mode_class
class = GET_MODE_CLASS (mode
);
3591 enum machine_mode wider_mode
= mode
;
3593 /* Try combined insns first. */
3596 enum insn_code icode
;
3597 PUT_MODE (test
, wider_mode
);
3601 icode
= cbranch_optab
->handlers
[(int) wider_mode
].insn_code
;
3603 if (icode
!= CODE_FOR_nothing
3604 && insn_data
[icode
].operand
[0].predicate (test
, wider_mode
))
3606 x
= prepare_operand (icode
, x
, 1, mode
, wider_mode
, unsignedp
);
3607 y
= prepare_operand (icode
, y
, 2, mode
, wider_mode
, unsignedp
);
3608 emit_jump_insn (GEN_FCN (icode
) (test
, x
, y
, label
));
3613 /* Handle some compares against zero. */
3614 icode
= (int) tst_optab
->handlers
[(int) wider_mode
].insn_code
;
3615 if (y
== CONST0_RTX (mode
) && icode
!= CODE_FOR_nothing
)
3617 x
= prepare_operand (icode
, x
, 0, mode
, wider_mode
, unsignedp
);
3618 emit_insn (GEN_FCN (icode
) (x
));
3620 emit_jump_insn (bcc_gen_fctn
[(int) comparison
] (label
));
3624 /* Handle compares for which there is a directly suitable insn. */
3626 icode
= (int) cmp_optab
->handlers
[(int) wider_mode
].insn_code
;
3627 if (icode
!= CODE_FOR_nothing
)
3629 x
= prepare_operand (icode
, x
, 0, mode
, wider_mode
, unsignedp
);
3630 y
= prepare_operand (icode
, y
, 1, mode
, wider_mode
, unsignedp
);
3631 emit_insn (GEN_FCN (icode
) (x
, y
));
3633 emit_jump_insn (bcc_gen_fctn
[(int) comparison
] (label
));
3637 if (class != MODE_INT
&& class != MODE_FLOAT
3638 && class != MODE_COMPLEX_FLOAT
)
3641 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
);
3643 while (wider_mode
!= VOIDmode
);
3648 /* Generate code to compare X with Y so that the condition codes are
3649 set and to jump to LABEL if the condition is true. If X is a
3650 constant and Y is not a constant, then the comparison is swapped to
3651 ensure that the comparison RTL has the canonical form.
3653 UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they
3654 need to be widened by emit_cmp_insn. UNSIGNEDP is also used to select
3655 the proper branch condition code.
3657 If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y.
3659 MODE is the mode of the inputs (in case they are const_int).
3661 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). It will
3662 be passed unchanged to emit_cmp_insn, then potentially converted into an
3663 unsigned variant based on UNSIGNEDP to select a proper jump instruction. */
3666 emit_cmp_and_jump_insns (rtx x
, rtx y
, enum rtx_code comparison
, rtx size
,
3667 enum machine_mode mode
, int unsignedp
, rtx label
)
3669 rtx op0
= x
, op1
= y
;
3671 /* Swap operands and condition to ensure canonical RTL. */
3672 if (swap_commutative_operands_p (x
, y
))
3674 /* If we're not emitting a branch, this means some caller
3679 comparison
= swap_condition (comparison
);
3683 /* If OP0 is still a constant, then both X and Y must be constants.
3684 Force X into a register to create canonical RTL. */
3685 if (CONSTANT_P (op0
))
3686 op0
= force_reg (mode
, op0
);
3690 comparison
= unsigned_condition (comparison
);
3692 prepare_cmp_insn (&op0
, &op1
, &comparison
, size
, &mode
, &unsignedp
,
3694 emit_cmp_and_jump_insn_1 (op0
, op1
, mode
, comparison
, unsignedp
, label
);
3697 /* Like emit_cmp_and_jump_insns, but generate only the comparison. */
3700 emit_cmp_insn (rtx x
, rtx y
, enum rtx_code comparison
, rtx size
,
3701 enum machine_mode mode
, int unsignedp
)
3703 emit_cmp_and_jump_insns (x
, y
, comparison
, size
, mode
, unsignedp
, 0);
3706 /* Emit a library call comparison between floating point X and Y.
3707 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */
3710 prepare_float_lib_cmp (rtx
*px
, rtx
*py
, enum rtx_code
*pcomparison
,
3711 enum machine_mode
*pmode
, int *punsignedp
)
3713 enum rtx_code comparison
= *pcomparison
;
3714 enum rtx_code swapped
= swap_condition (comparison
);
3715 enum rtx_code reversed
= reverse_condition_maybe_unordered (comparison
);
3718 enum machine_mode orig_mode
= GET_MODE (x
);
3719 enum machine_mode mode
;
3720 rtx value
, target
, insns
, equiv
;
3722 bool reversed_p
= false;
3724 for (mode
= orig_mode
; mode
!= VOIDmode
; mode
= GET_MODE_WIDER_MODE (mode
))
3726 if ((libfunc
= code_to_optab
[comparison
]->handlers
[mode
].libfunc
))
3729 if ((libfunc
= code_to_optab
[swapped
]->handlers
[mode
].libfunc
))
3732 tmp
= x
; x
= y
; y
= tmp
;
3733 comparison
= swapped
;
3737 if ((libfunc
= code_to_optab
[reversed
]->handlers
[mode
].libfunc
)
3738 && FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, reversed
))
3740 comparison
= reversed
;
3746 gcc_assert (mode
!= VOIDmode
);
3748 if (mode
!= orig_mode
)
3750 x
= convert_to_mode (mode
, x
, 0);
3751 y
= convert_to_mode (mode
, y
, 0);
3754 /* Attach a REG_EQUAL note describing the semantics of the libcall to
3755 the RTL. The allows the RTL optimizers to delete the libcall if the
3756 condition can be determined at compile-time. */
3757 if (comparison
== UNORDERED
)
3759 rtx temp
= simplify_gen_relational (NE
, word_mode
, mode
, x
, x
);
3760 equiv
= simplify_gen_relational (NE
, word_mode
, mode
, y
, y
);
3761 equiv
= simplify_gen_ternary (IF_THEN_ELSE
, word_mode
, word_mode
,
3762 temp
, const_true_rtx
, equiv
);
3766 equiv
= simplify_gen_relational (comparison
, word_mode
, mode
, x
, y
);
3767 if (! FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
))
3769 rtx true_rtx
, false_rtx
;
3774 true_rtx
= const0_rtx
;
3775 false_rtx
= const_true_rtx
;
3779 true_rtx
= const_true_rtx
;
3780 false_rtx
= const0_rtx
;
3784 true_rtx
= const1_rtx
;
3785 false_rtx
= const0_rtx
;
3789 true_rtx
= const0_rtx
;
3790 false_rtx
= constm1_rtx
;
3794 true_rtx
= constm1_rtx
;
3795 false_rtx
= const0_rtx
;
3799 true_rtx
= const0_rtx
;
3800 false_rtx
= const1_rtx
;
3806 equiv
= simplify_gen_ternary (IF_THEN_ELSE
, word_mode
, word_mode
,
3807 equiv
, true_rtx
, false_rtx
);
3812 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
3813 word_mode
, 2, x
, mode
, y
, mode
);
3814 insns
= get_insns ();
3817 target
= gen_reg_rtx (word_mode
);
3818 emit_libcall_block (insns
, target
, value
, equiv
);
3820 if (comparison
== UNORDERED
3821 || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
))
3822 comparison
= reversed_p
? EQ
: NE
;
3827 *pcomparison
= comparison
;
3831 /* Generate code to indirectly jump to a location given in the rtx LOC. */
3834 emit_indirect_jump (rtx loc
)
3836 if (!insn_data
[(int) CODE_FOR_indirect_jump
].operand
[0].predicate
3838 loc
= copy_to_mode_reg (Pmode
, loc
);
3840 emit_jump_insn (gen_indirect_jump (loc
));
3844 #ifdef HAVE_conditional_move
3846 /* Emit a conditional move instruction if the machine supports one for that
3847 condition and machine mode.
3849 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
3850 the mode to use should they be constants. If it is VOIDmode, they cannot
3853 OP2 should be stored in TARGET if the comparison is true, otherwise OP3
3854 should be stored there. MODE is the mode to use should they be constants.
3855 If it is VOIDmode, they cannot both be constants.
3857 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
3858 is not supported. */
3861 emit_conditional_move (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
3862 enum machine_mode cmode
, rtx op2
, rtx op3
,
3863 enum machine_mode mode
, int unsignedp
)
3865 rtx tem
, subtarget
, comparison
, insn
;
3866 enum insn_code icode
;
3867 enum rtx_code reversed
;
3869 /* If one operand is constant, make it the second one. Only do this
3870 if the other operand is not constant as well. */
3872 if (swap_commutative_operands_p (op0
, op1
))
3877 code
= swap_condition (code
);
3880 /* get_condition will prefer to generate LT and GT even if the old
3881 comparison was against zero, so undo that canonicalization here since
3882 comparisons against zero are cheaper. */
3883 if (code
== LT
&& op1
== const1_rtx
)
3884 code
= LE
, op1
= const0_rtx
;
3885 else if (code
== GT
&& op1
== constm1_rtx
)
3886 code
= GE
, op1
= const0_rtx
;
3888 if (cmode
== VOIDmode
)
3889 cmode
= GET_MODE (op0
);
3891 if (swap_commutative_operands_p (op2
, op3
)
3892 && ((reversed
= reversed_comparison_code_parts (code
, op0
, op1
, NULL
))
3901 if (mode
== VOIDmode
)
3902 mode
= GET_MODE (op2
);
3904 icode
= movcc_gen_code
[mode
];
3906 if (icode
== CODE_FOR_nothing
)
3910 target
= gen_reg_rtx (mode
);
3914 /* If the insn doesn't accept these operands, put them in pseudos. */
3916 if (!insn_data
[icode
].operand
[0].predicate
3917 (subtarget
, insn_data
[icode
].operand
[0].mode
))
3918 subtarget
= gen_reg_rtx (insn_data
[icode
].operand
[0].mode
);
3920 if (!insn_data
[icode
].operand
[2].predicate
3921 (op2
, insn_data
[icode
].operand
[2].mode
))
3922 op2
= copy_to_mode_reg (insn_data
[icode
].operand
[2].mode
, op2
);
3924 if (!insn_data
[icode
].operand
[3].predicate
3925 (op3
, insn_data
[icode
].operand
[3].mode
))
3926 op3
= copy_to_mode_reg (insn_data
[icode
].operand
[3].mode
, op3
);
3928 /* Everything should now be in the suitable form, so emit the compare insn
3929 and then the conditional move. */
3932 = compare_from_rtx (op0
, op1
, code
, unsignedp
, cmode
, NULL_RTX
);
3934 /* ??? Watch for const0_rtx (nop) and const_true_rtx (unconditional)? */
3935 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
3936 return NULL and let the caller figure out how best to deal with this
3938 if (GET_CODE (comparison
) != code
)
3941 insn
= GEN_FCN (icode
) (subtarget
, comparison
, op2
, op3
);
3943 /* If that failed, then give up. */
3949 if (subtarget
!= target
)
3950 convert_move (target
, subtarget
, 0);
3955 /* Return nonzero if a conditional move of mode MODE is supported.
3957 This function is for combine so it can tell whether an insn that looks
3958 like a conditional move is actually supported by the hardware. If we
3959 guess wrong we lose a bit on optimization, but that's it. */
3960 /* ??? sparc64 supports conditionally moving integers values based on fp
3961 comparisons, and vice versa. How do we handle them? */
3964 can_conditionally_move_p (enum machine_mode mode
)
3966 if (movcc_gen_code
[mode
] != CODE_FOR_nothing
)
3972 #endif /* HAVE_conditional_move */
3974 /* Emit a conditional addition instruction if the machine supports one for that
3975 condition and machine mode.
3977 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
3978 the mode to use should they be constants. If it is VOIDmode, they cannot
3981 OP2 should be stored in TARGET if the comparison is true, otherwise OP2+OP3
3982 should be stored there. MODE is the mode to use should they be constants.
3983 If it is VOIDmode, they cannot both be constants.
3985 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
3986 is not supported. */
3989 emit_conditional_add (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
3990 enum machine_mode cmode
, rtx op2
, rtx op3
,
3991 enum machine_mode mode
, int unsignedp
)
3993 rtx tem
, subtarget
, comparison
, insn
;
3994 enum insn_code icode
;
3995 enum rtx_code reversed
;
3997 /* If one operand is constant, make it the second one. Only do this
3998 if the other operand is not constant as well. */
4000 if (swap_commutative_operands_p (op0
, op1
))
4005 code
= swap_condition (code
);
4008 /* get_condition will prefer to generate LT and GT even if the old
4009 comparison was against zero, so undo that canonicalization here since
4010 comparisons against zero are cheaper. */
4011 if (code
== LT
&& op1
== const1_rtx
)
4012 code
= LE
, op1
= const0_rtx
;
4013 else if (code
== GT
&& op1
== constm1_rtx
)
4014 code
= GE
, op1
= const0_rtx
;
4016 if (cmode
== VOIDmode
)
4017 cmode
= GET_MODE (op0
);
4019 if (swap_commutative_operands_p (op2
, op3
)
4020 && ((reversed
= reversed_comparison_code_parts (code
, op0
, op1
, NULL
))
4029 if (mode
== VOIDmode
)
4030 mode
= GET_MODE (op2
);
4032 icode
= addcc_optab
->handlers
[(int) mode
].insn_code
;
4034 if (icode
== CODE_FOR_nothing
)
4038 target
= gen_reg_rtx (mode
);
4040 /* If the insn doesn't accept these operands, put them in pseudos. */
4042 if (!insn_data
[icode
].operand
[0].predicate
4043 (target
, insn_data
[icode
].operand
[0].mode
))
4044 subtarget
= gen_reg_rtx (insn_data
[icode
].operand
[0].mode
);
4048 if (!insn_data
[icode
].operand
[2].predicate
4049 (op2
, insn_data
[icode
].operand
[2].mode
))
4050 op2
= copy_to_mode_reg (insn_data
[icode
].operand
[2].mode
, op2
);
4052 if (!insn_data
[icode
].operand
[3].predicate
4053 (op3
, insn_data
[icode
].operand
[3].mode
))
4054 op3
= copy_to_mode_reg (insn_data
[icode
].operand
[3].mode
, op3
);
4056 /* Everything should now be in the suitable form, so emit the compare insn
4057 and then the conditional move. */
4060 = compare_from_rtx (op0
, op1
, code
, unsignedp
, cmode
, NULL_RTX
);
4062 /* ??? Watch for const0_rtx (nop) and const_true_rtx (unconditional)? */
4063 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4064 return NULL and let the caller figure out how best to deal with this
4066 if (GET_CODE (comparison
) != code
)
4069 insn
= GEN_FCN (icode
) (subtarget
, comparison
, op2
, op3
);
4071 /* If that failed, then give up. */
4077 if (subtarget
!= target
)
4078 convert_move (target
, subtarget
, 0);
4083 /* These functions attempt to generate an insn body, rather than
4084 emitting the insn, but if the gen function already emits them, we
4085 make no attempt to turn them back into naked patterns. */
4087 /* Generate and return an insn body to add Y to X. */
4090 gen_add2_insn (rtx x
, rtx y
)
4092 int icode
= (int) add_optab
->handlers
[(int) GET_MODE (x
)].insn_code
;
4094 gcc_assert (insn_data
[icode
].operand
[0].predicate
4095 (x
, insn_data
[icode
].operand
[0].mode
));
4096 gcc_assert (insn_data
[icode
].operand
[1].predicate
4097 (x
, insn_data
[icode
].operand
[1].mode
));
4098 gcc_assert (insn_data
[icode
].operand
[2].predicate
4099 (y
, insn_data
[icode
].operand
[2].mode
));
4101 return GEN_FCN (icode
) (x
, x
, y
);
4104 /* Generate and return an insn body to add r1 and c,
4105 storing the result in r0. */
4107 gen_add3_insn (rtx r0
, rtx r1
, rtx c
)
4109 int icode
= (int) add_optab
->handlers
[(int) GET_MODE (r0
)].insn_code
;
4111 if (icode
== CODE_FOR_nothing
4112 || !(insn_data
[icode
].operand
[0].predicate
4113 (r0
, insn_data
[icode
].operand
[0].mode
))
4114 || !(insn_data
[icode
].operand
[1].predicate
4115 (r1
, insn_data
[icode
].operand
[1].mode
))
4116 || !(insn_data
[icode
].operand
[2].predicate
4117 (c
, insn_data
[icode
].operand
[2].mode
)))
4120 return GEN_FCN (icode
) (r0
, r1
, c
);
4124 have_add2_insn (rtx x
, rtx y
)
4128 gcc_assert (GET_MODE (x
) != VOIDmode
);
4130 icode
= (int) add_optab
->handlers
[(int) GET_MODE (x
)].insn_code
;
4132 if (icode
== CODE_FOR_nothing
)
4135 if (!(insn_data
[icode
].operand
[0].predicate
4136 (x
, insn_data
[icode
].operand
[0].mode
))
4137 || !(insn_data
[icode
].operand
[1].predicate
4138 (x
, insn_data
[icode
].operand
[1].mode
))
4139 || !(insn_data
[icode
].operand
[2].predicate
4140 (y
, insn_data
[icode
].operand
[2].mode
)))
4146 /* Generate and return an insn body to subtract Y from X. */
4149 gen_sub2_insn (rtx x
, rtx y
)
4151 int icode
= (int) sub_optab
->handlers
[(int) GET_MODE (x
)].insn_code
;
4153 gcc_assert (insn_data
[icode
].operand
[0].predicate
4154 (x
, insn_data
[icode
].operand
[0].mode
));
4155 gcc_assert (insn_data
[icode
].operand
[1].predicate
4156 (x
, insn_data
[icode
].operand
[1].mode
));
4157 gcc_assert (insn_data
[icode
].operand
[2].predicate
4158 (y
, insn_data
[icode
].operand
[2].mode
));
4160 return GEN_FCN (icode
) (x
, x
, y
);
4163 /* Generate and return an insn body to subtract r1 and c,
4164 storing the result in r0. */
4166 gen_sub3_insn (rtx r0
, rtx r1
, rtx c
)
4168 int icode
= (int) sub_optab
->handlers
[(int) GET_MODE (r0
)].insn_code
;
4170 if (icode
== CODE_FOR_nothing
4171 || !(insn_data
[icode
].operand
[0].predicate
4172 (r0
, insn_data
[icode
].operand
[0].mode
))
4173 || !(insn_data
[icode
].operand
[1].predicate
4174 (r1
, insn_data
[icode
].operand
[1].mode
))
4175 || !(insn_data
[icode
].operand
[2].predicate
4176 (c
, insn_data
[icode
].operand
[2].mode
)))
4179 return GEN_FCN (icode
) (r0
, r1
, c
);
4183 have_sub2_insn (rtx x
, rtx y
)
4187 gcc_assert (GET_MODE (x
) != VOIDmode
);
4189 icode
= (int) sub_optab
->handlers
[(int) GET_MODE (x
)].insn_code
;
4191 if (icode
== CODE_FOR_nothing
)
4194 if (!(insn_data
[icode
].operand
[0].predicate
4195 (x
, insn_data
[icode
].operand
[0].mode
))
4196 || !(insn_data
[icode
].operand
[1].predicate
4197 (x
, insn_data
[icode
].operand
[1].mode
))
4198 || !(insn_data
[icode
].operand
[2].predicate
4199 (y
, insn_data
[icode
].operand
[2].mode
)))
4205 /* Generate the body of an instruction to copy Y into X.
4206 It may be a list of insns, if one insn isn't enough. */
4209 gen_move_insn (rtx x
, rtx y
)
4214 emit_move_insn_1 (x
, y
);
4220 /* Return the insn code used to extend FROM_MODE to TO_MODE.
4221 UNSIGNEDP specifies zero-extension instead of sign-extension. If
4222 no such operation exists, CODE_FOR_nothing will be returned. */
4225 can_extend_p (enum machine_mode to_mode
, enum machine_mode from_mode
,
4229 #ifdef HAVE_ptr_extend
4231 return CODE_FOR_ptr_extend
;
4234 tab
= unsignedp
? zext_optab
: sext_optab
;
4235 return tab
->handlers
[to_mode
][from_mode
].insn_code
;
4238 /* Generate the body of an insn to extend Y (with mode MFROM)
4239 into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */
4242 gen_extend_insn (rtx x
, rtx y
, enum machine_mode mto
,
4243 enum machine_mode mfrom
, int unsignedp
)
4245 enum insn_code icode
= can_extend_p (mto
, mfrom
, unsignedp
);
4246 return GEN_FCN (icode
) (x
, y
);
4249 /* can_fix_p and can_float_p say whether the target machine
4250 can directly convert a given fixed point type to
4251 a given floating point type, or vice versa.
4252 The returned value is the CODE_FOR_... value to use,
4253 or CODE_FOR_nothing if these modes cannot be directly converted.
4255 *TRUNCP_PTR is set to 1 if it is necessary to output
4256 an explicit FTRUNC insn before the fix insn; otherwise 0. */
4258 static enum insn_code
4259 can_fix_p (enum machine_mode fixmode
, enum machine_mode fltmode
,
4260 int unsignedp
, int *truncp_ptr
)
4263 enum insn_code icode
;
4265 tab
= unsignedp
? ufixtrunc_optab
: sfixtrunc_optab
;
4266 icode
= tab
->handlers
[fixmode
][fltmode
].insn_code
;
4267 if (icode
!= CODE_FOR_nothing
)
4273 /* FIXME: This requires a port to define both FIX and FTRUNC pattern
4274 for this to work. We need to rework the fix* and ftrunc* patterns
4275 and documentation. */
4276 tab
= unsignedp
? ufix_optab
: sfix_optab
;
4277 icode
= tab
->handlers
[fixmode
][fltmode
].insn_code
;
4278 if (icode
!= CODE_FOR_nothing
4279 && ftrunc_optab
->handlers
[fltmode
].insn_code
!= CODE_FOR_nothing
)
4286 return CODE_FOR_nothing
;
4289 static enum insn_code
4290 can_float_p (enum machine_mode fltmode
, enum machine_mode fixmode
,
4295 tab
= unsignedp
? ufloat_optab
: sfloat_optab
;
4296 return tab
->handlers
[fltmode
][fixmode
].insn_code
;
4299 /* Generate code to convert FROM to floating point
4300 and store in TO. FROM must be fixed point and not VOIDmode.
4301 UNSIGNEDP nonzero means regard FROM as unsigned.
4302 Normally this is done by correcting the final value
4303 if it is negative. */
4306 expand_float (rtx to
, rtx from
, int unsignedp
)
4308 enum insn_code icode
;
4310 enum machine_mode fmode
, imode
;
4312 /* Crash now, because we won't be able to decide which mode to use. */
4313 gcc_assert (GET_MODE (from
) != VOIDmode
);
4315 /* Look for an insn to do the conversion. Do it in the specified
4316 modes if possible; otherwise convert either input, output or both to
4317 wider mode. If the integer mode is wider than the mode of FROM,
4318 we can do the conversion signed even if the input is unsigned. */
4320 for (fmode
= GET_MODE (to
); fmode
!= VOIDmode
;
4321 fmode
= GET_MODE_WIDER_MODE (fmode
))
4322 for (imode
= GET_MODE (from
); imode
!= VOIDmode
;
4323 imode
= GET_MODE_WIDER_MODE (imode
))
4325 int doing_unsigned
= unsignedp
;
4327 if (fmode
!= GET_MODE (to
)
4328 && significand_size (fmode
) < GET_MODE_BITSIZE (GET_MODE (from
)))
4331 icode
= can_float_p (fmode
, imode
, unsignedp
);
4332 if (icode
== CODE_FOR_nothing
&& imode
!= GET_MODE (from
) && unsignedp
)
4333 icode
= can_float_p (fmode
, imode
, 0), doing_unsigned
= 0;
4335 if (icode
!= CODE_FOR_nothing
)
4337 if (imode
!= GET_MODE (from
))
4338 from
= convert_to_mode (imode
, from
, unsignedp
);
4340 if (fmode
!= GET_MODE (to
))
4341 target
= gen_reg_rtx (fmode
);
4343 emit_unop_insn (icode
, target
, from
,
4344 doing_unsigned
? UNSIGNED_FLOAT
: FLOAT
);
4347 convert_move (to
, target
, 0);
4352 /* Unsigned integer, and no way to convert directly.
4353 Convert as signed, then conditionally adjust the result. */
4356 rtx label
= gen_label_rtx ();
4358 REAL_VALUE_TYPE offset
;
4360 /* Look for a usable floating mode FMODE wider than the source and at
4361 least as wide as the target. Using FMODE will avoid rounding woes
4362 with unsigned values greater than the signed maximum value. */
4364 for (fmode
= GET_MODE (to
); fmode
!= VOIDmode
;
4365 fmode
= GET_MODE_WIDER_MODE (fmode
))
4366 if (GET_MODE_BITSIZE (GET_MODE (from
)) < GET_MODE_BITSIZE (fmode
)
4367 && can_float_p (fmode
, GET_MODE (from
), 0) != CODE_FOR_nothing
)
4370 if (fmode
== VOIDmode
)
4372 /* There is no such mode. Pretend the target is wide enough. */
4373 fmode
= GET_MODE (to
);
4375 /* Avoid double-rounding when TO is narrower than FROM. */
4376 if ((significand_size (fmode
) + 1)
4377 < GET_MODE_BITSIZE (GET_MODE (from
)))
4380 rtx neglabel
= gen_label_rtx ();
4382 /* Don't use TARGET if it isn't a register, is a hard register,
4383 or is the wrong mode. */
4385 || REGNO (target
) < FIRST_PSEUDO_REGISTER
4386 || GET_MODE (target
) != fmode
)
4387 target
= gen_reg_rtx (fmode
);
4389 imode
= GET_MODE (from
);
4390 do_pending_stack_adjust ();
4392 /* Test whether the sign bit is set. */
4393 emit_cmp_and_jump_insns (from
, const0_rtx
, LT
, NULL_RTX
, imode
,
4396 /* The sign bit is not set. Convert as signed. */
4397 expand_float (target
, from
, 0);
4398 emit_jump_insn (gen_jump (label
));
4401 /* The sign bit is set.
4402 Convert to a usable (positive signed) value by shifting right
4403 one bit, while remembering if a nonzero bit was shifted
4404 out; i.e., compute (from & 1) | (from >> 1). */
4406 emit_label (neglabel
);
4407 temp
= expand_binop (imode
, and_optab
, from
, const1_rtx
,
4408 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4409 temp1
= expand_shift (RSHIFT_EXPR
, imode
, from
, integer_one_node
,
4411 temp
= expand_binop (imode
, ior_optab
, temp
, temp1
, temp
, 1,
4413 expand_float (target
, temp
, 0);
4415 /* Multiply by 2 to undo the shift above. */
4416 temp
= expand_binop (fmode
, add_optab
, target
, target
,
4417 target
, 0, OPTAB_LIB_WIDEN
);
4419 emit_move_insn (target
, temp
);
4421 do_pending_stack_adjust ();
4427 /* If we are about to do some arithmetic to correct for an
4428 unsigned operand, do it in a pseudo-register. */
4430 if (GET_MODE (to
) != fmode
4431 || !REG_P (to
) || REGNO (to
) < FIRST_PSEUDO_REGISTER
)
4432 target
= gen_reg_rtx (fmode
);
4434 /* Convert as signed integer to floating. */
4435 expand_float (target
, from
, 0);
4437 /* If FROM is negative (and therefore TO is negative),
4438 correct its value by 2**bitwidth. */
4440 do_pending_stack_adjust ();
4441 emit_cmp_and_jump_insns (from
, const0_rtx
, GE
, NULL_RTX
, GET_MODE (from
),
4445 real_2expN (&offset
, GET_MODE_BITSIZE (GET_MODE (from
)));
4446 temp
= expand_binop (fmode
, add_optab
, target
,
4447 CONST_DOUBLE_FROM_REAL_VALUE (offset
, fmode
),
4448 target
, 0, OPTAB_LIB_WIDEN
);
4450 emit_move_insn (target
, temp
);
4452 do_pending_stack_adjust ();
4457 /* No hardware instruction available; call a library routine. */
4462 convert_optab tab
= unsignedp
? ufloat_optab
: sfloat_optab
;
4464 if (GET_MODE_SIZE (GET_MODE (from
)) < GET_MODE_SIZE (SImode
))
4465 from
= convert_to_mode (SImode
, from
, unsignedp
);
4467 libfunc
= tab
->handlers
[GET_MODE (to
)][GET_MODE (from
)].libfunc
;
4468 gcc_assert (libfunc
);
4472 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
4473 GET_MODE (to
), 1, from
,
4475 insns
= get_insns ();
4478 emit_libcall_block (insns
, target
, value
,
4479 gen_rtx_FLOAT (GET_MODE (to
), from
));
4484 /* Copy result to requested destination
4485 if we have been computing in a temp location. */
4489 if (GET_MODE (target
) == GET_MODE (to
))
4490 emit_move_insn (to
, target
);
4492 convert_move (to
, target
, 0);
4496 /* Generate code to convert FROM to fixed point and store in TO. FROM
4497 must be floating point. */
4500 expand_fix (rtx to
, rtx from
, int unsignedp
)
4502 enum insn_code icode
;
4504 enum machine_mode fmode
, imode
;
4507 /* We first try to find a pair of modes, one real and one integer, at
4508 least as wide as FROM and TO, respectively, in which we can open-code
4509 this conversion. If the integer mode is wider than the mode of TO,
4510 we can do the conversion either signed or unsigned. */
4512 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
4513 fmode
= GET_MODE_WIDER_MODE (fmode
))
4514 for (imode
= GET_MODE (to
); imode
!= VOIDmode
;
4515 imode
= GET_MODE_WIDER_MODE (imode
))
4517 int doing_unsigned
= unsignedp
;
4519 icode
= can_fix_p (imode
, fmode
, unsignedp
, &must_trunc
);
4520 if (icode
== CODE_FOR_nothing
&& imode
!= GET_MODE (to
) && unsignedp
)
4521 icode
= can_fix_p (imode
, fmode
, 0, &must_trunc
), doing_unsigned
= 0;
4523 if (icode
!= CODE_FOR_nothing
)
4525 if (fmode
!= GET_MODE (from
))
4526 from
= convert_to_mode (fmode
, from
, 0);
4530 rtx temp
= gen_reg_rtx (GET_MODE (from
));
4531 from
= expand_unop (GET_MODE (from
), ftrunc_optab
, from
,
4535 if (imode
!= GET_MODE (to
))
4536 target
= gen_reg_rtx (imode
);
4538 emit_unop_insn (icode
, target
, from
,
4539 doing_unsigned
? UNSIGNED_FIX
: FIX
);
4541 convert_move (to
, target
, unsignedp
);
4546 /* For an unsigned conversion, there is one more way to do it.
4547 If we have a signed conversion, we generate code that compares
4548 the real value to the largest representable positive number. If if
4549 is smaller, the conversion is done normally. Otherwise, subtract
4550 one plus the highest signed number, convert, and add it back.
4552 We only need to check all real modes, since we know we didn't find
4553 anything with a wider integer mode.
4555 This code used to extend FP value into mode wider than the destination.
4556 This is not needed. Consider, for instance conversion from SFmode
4559 The hot path trought the code is dealing with inputs smaller than 2^63
4560 and doing just the conversion, so there is no bits to lose.
4562 In the other path we know the value is positive in the range 2^63..2^64-1
4563 inclusive. (as for other imput overflow happens and result is undefined)
4564 So we know that the most important bit set in mantissa corresponds to
4565 2^63. The subtraction of 2^63 should not generate any rounding as it
4566 simply clears out that bit. The rest is trivial. */
4568 if (unsignedp
&& GET_MODE_BITSIZE (GET_MODE (to
)) <= HOST_BITS_PER_WIDE_INT
)
4569 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
4570 fmode
= GET_MODE_WIDER_MODE (fmode
))
4571 if (CODE_FOR_nothing
!= can_fix_p (GET_MODE (to
), fmode
, 0,
4575 REAL_VALUE_TYPE offset
;
4576 rtx limit
, lab1
, lab2
, insn
;
4578 bitsize
= GET_MODE_BITSIZE (GET_MODE (to
));
4579 real_2expN (&offset
, bitsize
- 1);
4580 limit
= CONST_DOUBLE_FROM_REAL_VALUE (offset
, fmode
);
4581 lab1
= gen_label_rtx ();
4582 lab2
= gen_label_rtx ();
4584 if (fmode
!= GET_MODE (from
))
4585 from
= convert_to_mode (fmode
, from
, 0);
4587 /* See if we need to do the subtraction. */
4588 do_pending_stack_adjust ();
4589 emit_cmp_and_jump_insns (from
, limit
, GE
, NULL_RTX
, GET_MODE (from
),
4592 /* If not, do the signed "fix" and branch around fixup code. */
4593 expand_fix (to
, from
, 0);
4594 emit_jump_insn (gen_jump (lab2
));
4597 /* Otherwise, subtract 2**(N-1), convert to signed number,
4598 then add 2**(N-1). Do the addition using XOR since this
4599 will often generate better code. */
4601 target
= expand_binop (GET_MODE (from
), sub_optab
, from
, limit
,
4602 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
4603 expand_fix (to
, target
, 0);
4604 target
= expand_binop (GET_MODE (to
), xor_optab
, to
,
4606 ((HOST_WIDE_INT
) 1 << (bitsize
- 1),
4608 to
, 1, OPTAB_LIB_WIDEN
);
4611 emit_move_insn (to
, target
);
4615 if (mov_optab
->handlers
[(int) GET_MODE (to
)].insn_code
4616 != CODE_FOR_nothing
)
4618 /* Make a place for a REG_NOTE and add it. */
4619 insn
= emit_move_insn (to
, to
);
4620 set_unique_reg_note (insn
,
4622 gen_rtx_fmt_e (UNSIGNED_FIX
,
4630 /* We can't do it with an insn, so use a library call. But first ensure
4631 that the mode of TO is at least as wide as SImode, since those are the
4632 only library calls we know about. */
4634 if (GET_MODE_SIZE (GET_MODE (to
)) < GET_MODE_SIZE (SImode
))
4636 target
= gen_reg_rtx (SImode
);
4638 expand_fix (target
, from
, unsignedp
);
4646 convert_optab tab
= unsignedp
? ufix_optab
: sfix_optab
;
4647 libfunc
= tab
->handlers
[GET_MODE (to
)][GET_MODE (from
)].libfunc
;
4648 gcc_assert (libfunc
);
4652 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
4653 GET_MODE (to
), 1, from
,
4655 insns
= get_insns ();
4658 emit_libcall_block (insns
, target
, value
,
4659 gen_rtx_fmt_e (unsignedp
? UNSIGNED_FIX
: FIX
,
4660 GET_MODE (to
), from
));
4665 if (GET_MODE (to
) == GET_MODE (target
))
4666 emit_move_insn (to
, target
);
4668 convert_move (to
, target
, 0);
4672 /* Report whether we have an instruction to perform the operation
4673 specified by CODE on operands of mode MODE. */
4675 have_insn_for (enum rtx_code code
, enum machine_mode mode
)
4677 return (code_to_optab
[(int) code
] != 0
4678 && (code_to_optab
[(int) code
]->handlers
[(int) mode
].insn_code
4679 != CODE_FOR_nothing
));
4682 /* Create a blank optab. */
4687 optab op
= ggc_alloc (sizeof (struct optab
));
4688 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4690 op
->handlers
[i
].insn_code
= CODE_FOR_nothing
;
4691 op
->handlers
[i
].libfunc
= 0;
4697 static convert_optab
4698 new_convert_optab (void)
4701 convert_optab op
= ggc_alloc (sizeof (struct convert_optab
));
4702 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4703 for (j
= 0; j
< NUM_MACHINE_MODES
; j
++)
4705 op
->handlers
[i
][j
].insn_code
= CODE_FOR_nothing
;
4706 op
->handlers
[i
][j
].libfunc
= 0;
4711 /* Same, but fill in its code as CODE, and write it into the
4712 code_to_optab table. */
4714 init_optab (enum rtx_code code
)
4716 optab op
= new_optab ();
4718 code_to_optab
[(int) code
] = op
;
4722 /* Same, but fill in its code as CODE, and do _not_ write it into
4723 the code_to_optab table. */
4725 init_optabv (enum rtx_code code
)
4727 optab op
= new_optab ();
4732 /* Conversion optabs never go in the code_to_optab table. */
4733 static inline convert_optab
4734 init_convert_optab (enum rtx_code code
)
4736 convert_optab op
= new_convert_optab ();
4741 /* Initialize the libfunc fields of an entire group of entries in some
4742 optab. Each entry is set equal to a string consisting of a leading
4743 pair of underscores followed by a generic operation name followed by
4744 a mode name (downshifted to lowercase) followed by a single character
4745 representing the number of operands for the given operation (which is
4746 usually one of the characters '2', '3', or '4').
4748 OPTABLE is the table in which libfunc fields are to be initialized.
4749 FIRST_MODE is the first machine mode index in the given optab to
4751 LAST_MODE is the last machine mode index in the given optab to
4753 OPNAME is the generic (string) name of the operation.
4754 SUFFIX is the character which specifies the number of operands for
4755 the given generic operation.
4759 init_libfuncs (optab optable
, int first_mode
, int last_mode
,
4760 const char *opname
, int suffix
)
4763 unsigned opname_len
= strlen (opname
);
4765 for (mode
= first_mode
; (int) mode
<= (int) last_mode
;
4766 mode
= (enum machine_mode
) ((int) mode
+ 1))
4768 const char *mname
= GET_MODE_NAME (mode
);
4769 unsigned mname_len
= strlen (mname
);
4770 char *libfunc_name
= alloca (2 + opname_len
+ mname_len
+ 1 + 1);
4777 for (q
= opname
; *q
; )
4779 for (q
= mname
; *q
; q
++)
4780 *p
++ = TOLOWER (*q
);
4784 optable
->handlers
[(int) mode
].libfunc
4785 = init_one_libfunc (ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
4789 /* Initialize the libfunc fields of an entire group of entries in some
4790 optab which correspond to all integer mode operations. The parameters
4791 have the same meaning as similarly named ones for the `init_libfuncs'
4792 routine. (See above). */
4795 init_integral_libfuncs (optab optable
, const char *opname
, int suffix
)
4797 int maxsize
= 2*BITS_PER_WORD
;
4798 if (maxsize
< LONG_LONG_TYPE_SIZE
)
4799 maxsize
= LONG_LONG_TYPE_SIZE
;
4800 init_libfuncs (optable
, word_mode
,
4801 mode_for_size (maxsize
, MODE_INT
, 0),
4805 /* Initialize the libfunc fields of an entire group of entries in some
4806 optab which correspond to all real mode operations. The parameters
4807 have the same meaning as similarly named ones for the `init_libfuncs'
4808 routine. (See above). */
4811 init_floating_libfuncs (optab optable
, const char *opname
, int suffix
)
4813 init_libfuncs (optable
, MIN_MODE_FLOAT
, MAX_MODE_FLOAT
, opname
, suffix
);
4816 /* Initialize the libfunc fields of an entire group of entries of an
4817 inter-mode-class conversion optab. The string formation rules are
4818 similar to the ones for init_libfuncs, above, but instead of having
4819 a mode name and an operand count these functions have two mode names
4820 and no operand count. */
4822 init_interclass_conv_libfuncs (convert_optab tab
, const char *opname
,
4823 enum mode_class from_class
,
4824 enum mode_class to_class
)
4826 enum machine_mode first_from_mode
= GET_CLASS_NARROWEST_MODE (from_class
);
4827 enum machine_mode first_to_mode
= GET_CLASS_NARROWEST_MODE (to_class
);
4828 size_t opname_len
= strlen (opname
);
4829 size_t max_mname_len
= 0;
4831 enum machine_mode fmode
, tmode
;
4832 const char *fname
, *tname
;
4834 char *libfunc_name
, *suffix
;
4837 for (fmode
= first_from_mode
;
4839 fmode
= GET_MODE_WIDER_MODE (fmode
))
4840 max_mname_len
= MAX (max_mname_len
, strlen (GET_MODE_NAME (fmode
)));
4842 for (tmode
= first_to_mode
;
4844 tmode
= GET_MODE_WIDER_MODE (tmode
))
4845 max_mname_len
= MAX (max_mname_len
, strlen (GET_MODE_NAME (tmode
)));
4847 libfunc_name
= alloca (2 + opname_len
+ 2*max_mname_len
+ 1 + 1);
4848 libfunc_name
[0] = '_';
4849 libfunc_name
[1] = '_';
4850 memcpy (&libfunc_name
[2], opname
, opname_len
);
4851 suffix
= libfunc_name
+ opname_len
+ 2;
4853 for (fmode
= first_from_mode
; fmode
!= VOIDmode
;
4854 fmode
= GET_MODE_WIDER_MODE (fmode
))
4855 for (tmode
= first_to_mode
; tmode
!= VOIDmode
;
4856 tmode
= GET_MODE_WIDER_MODE (tmode
))
4858 fname
= GET_MODE_NAME (fmode
);
4859 tname
= GET_MODE_NAME (tmode
);
4862 for (q
= fname
; *q
; p
++, q
++)
4864 for (q
= tname
; *q
; p
++, q
++)
4869 tab
->handlers
[tmode
][fmode
].libfunc
4870 = init_one_libfunc (ggc_alloc_string (libfunc_name
,
4875 /* Initialize the libfunc fields of an entire group of entries of an
4876 intra-mode-class conversion optab. The string formation rules are
4877 similar to the ones for init_libfunc, above. WIDENING says whether
4878 the optab goes from narrow to wide modes or vice versa. These functions
4879 have two mode names _and_ an operand count. */
4881 init_intraclass_conv_libfuncs (convert_optab tab
, const char *opname
,
4882 enum mode_class
class, bool widening
)
4884 enum machine_mode first_mode
= GET_CLASS_NARROWEST_MODE (class);
4885 size_t opname_len
= strlen (opname
);
4886 size_t max_mname_len
= 0;
4888 enum machine_mode nmode
, wmode
;
4889 const char *nname
, *wname
;
4891 char *libfunc_name
, *suffix
;
4894 for (nmode
= first_mode
; nmode
!= VOIDmode
;
4895 nmode
= GET_MODE_WIDER_MODE (nmode
))
4896 max_mname_len
= MAX (max_mname_len
, strlen (GET_MODE_NAME (nmode
)));
4898 libfunc_name
= alloca (2 + opname_len
+ 2*max_mname_len
+ 1 + 1);
4899 libfunc_name
[0] = '_';
4900 libfunc_name
[1] = '_';
4901 memcpy (&libfunc_name
[2], opname
, opname_len
);
4902 suffix
= libfunc_name
+ opname_len
+ 2;
4904 for (nmode
= first_mode
; nmode
!= VOIDmode
;
4905 nmode
= GET_MODE_WIDER_MODE (nmode
))
4906 for (wmode
= GET_MODE_WIDER_MODE (nmode
); wmode
!= VOIDmode
;
4907 wmode
= GET_MODE_WIDER_MODE (wmode
))
4909 nname
= GET_MODE_NAME (nmode
);
4910 wname
= GET_MODE_NAME (wmode
);
4913 for (q
= widening
? nname
: wname
; *q
; p
++, q
++)
4915 for (q
= widening
? wname
: nname
; *q
; p
++, q
++)
4921 tab
->handlers
[widening
? wmode
: nmode
]
4922 [widening
? nmode
: wmode
].libfunc
4923 = init_one_libfunc (ggc_alloc_string (libfunc_name
,
4930 init_one_libfunc (const char *name
)
4934 /* Create a FUNCTION_DECL that can be passed to
4935 targetm.encode_section_info. */
4936 /* ??? We don't have any type information except for this is
4937 a function. Pretend this is "int foo()". */
4938 tree decl
= build_decl (FUNCTION_DECL
, get_identifier (name
),
4939 build_function_type (integer_type_node
, NULL_TREE
));
4940 DECL_ARTIFICIAL (decl
) = 1;
4941 DECL_EXTERNAL (decl
) = 1;
4942 TREE_PUBLIC (decl
) = 1;
4944 symbol
= XEXP (DECL_RTL (decl
), 0);
4946 /* Zap the nonsensical SYMBOL_REF_DECL for this. What we're left with
4947 are the flags assigned by targetm.encode_section_info. */
4948 SYMBOL_REF_DECL (symbol
) = 0;
4953 /* Call this to reset the function entry for one optab (OPTABLE) in mode
4954 MODE to NAME, which should be either 0 or a string constant. */
4956 set_optab_libfunc (optab optable
, enum machine_mode mode
, const char *name
)
4959 optable
->handlers
[mode
].libfunc
= init_one_libfunc (name
);
4961 optable
->handlers
[mode
].libfunc
= 0;
4964 /* Call this to reset the function entry for one conversion optab
4965 (OPTABLE) from mode FMODE to mode TMODE to NAME, which should be
4966 either 0 or a string constant. */
4968 set_conv_libfunc (convert_optab optable
, enum machine_mode tmode
,
4969 enum machine_mode fmode
, const char *name
)
4972 optable
->handlers
[tmode
][fmode
].libfunc
= init_one_libfunc (name
);
4974 optable
->handlers
[tmode
][fmode
].libfunc
= 0;
4977 /* Call this once to initialize the contents of the optabs
4978 appropriately for the current target machine. */
4985 /* Start by initializing all tables to contain CODE_FOR_nothing. */
4987 for (i
= 0; i
< NUM_RTX_CODE
; i
++)
4988 setcc_gen_code
[i
] = CODE_FOR_nothing
;
4990 #ifdef HAVE_conditional_move
4991 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4992 movcc_gen_code
[i
] = CODE_FOR_nothing
;
4995 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4997 vcond_gen_code
[i
] = CODE_FOR_nothing
;
4998 vcondu_gen_code
[i
] = CODE_FOR_nothing
;
5001 add_optab
= init_optab (PLUS
);
5002 addv_optab
= init_optabv (PLUS
);
5003 sub_optab
= init_optab (MINUS
);
5004 subv_optab
= init_optabv (MINUS
);
5005 smul_optab
= init_optab (MULT
);
5006 smulv_optab
= init_optabv (MULT
);
5007 smul_highpart_optab
= init_optab (UNKNOWN
);
5008 umul_highpart_optab
= init_optab (UNKNOWN
);
5009 smul_widen_optab
= init_optab (UNKNOWN
);
5010 umul_widen_optab
= init_optab (UNKNOWN
);
5011 sdiv_optab
= init_optab (DIV
);
5012 sdivv_optab
= init_optabv (DIV
);
5013 sdivmod_optab
= init_optab (UNKNOWN
);
5014 udiv_optab
= init_optab (UDIV
);
5015 udivmod_optab
= init_optab (UNKNOWN
);
5016 smod_optab
= init_optab (MOD
);
5017 umod_optab
= init_optab (UMOD
);
5018 fmod_optab
= init_optab (UNKNOWN
);
5019 drem_optab
= init_optab (UNKNOWN
);
5020 ftrunc_optab
= init_optab (UNKNOWN
);
5021 and_optab
= init_optab (AND
);
5022 ior_optab
= init_optab (IOR
);
5023 xor_optab
= init_optab (XOR
);
5024 ashl_optab
= init_optab (ASHIFT
);
5025 ashr_optab
= init_optab (ASHIFTRT
);
5026 lshr_optab
= init_optab (LSHIFTRT
);
5027 rotl_optab
= init_optab (ROTATE
);
5028 rotr_optab
= init_optab (ROTATERT
);
5029 smin_optab
= init_optab (SMIN
);
5030 smax_optab
= init_optab (SMAX
);
5031 umin_optab
= init_optab (UMIN
);
5032 umax_optab
= init_optab (UMAX
);
5033 pow_optab
= init_optab (UNKNOWN
);
5034 atan2_optab
= init_optab (UNKNOWN
);
5036 /* These three have codes assigned exclusively for the sake of
5038 mov_optab
= init_optab (SET
);
5039 movstrict_optab
= init_optab (STRICT_LOW_PART
);
5040 cmp_optab
= init_optab (COMPARE
);
5042 ucmp_optab
= init_optab (UNKNOWN
);
5043 tst_optab
= init_optab (UNKNOWN
);
5045 eq_optab
= init_optab (EQ
);
5046 ne_optab
= init_optab (NE
);
5047 gt_optab
= init_optab (GT
);
5048 ge_optab
= init_optab (GE
);
5049 lt_optab
= init_optab (LT
);
5050 le_optab
= init_optab (LE
);
5051 unord_optab
= init_optab (UNORDERED
);
5053 neg_optab
= init_optab (NEG
);
5054 negv_optab
= init_optabv (NEG
);
5055 abs_optab
= init_optab (ABS
);
5056 absv_optab
= init_optabv (ABS
);
5057 addcc_optab
= init_optab (UNKNOWN
);
5058 one_cmpl_optab
= init_optab (NOT
);
5059 ffs_optab
= init_optab (FFS
);
5060 clz_optab
= init_optab (CLZ
);
5061 ctz_optab
= init_optab (CTZ
);
5062 popcount_optab
= init_optab (POPCOUNT
);
5063 parity_optab
= init_optab (PARITY
);
5064 sqrt_optab
= init_optab (SQRT
);
5065 floor_optab
= init_optab (UNKNOWN
);
5066 lfloor_optab
= init_optab (UNKNOWN
);
5067 ceil_optab
= init_optab (UNKNOWN
);
5068 lceil_optab
= init_optab (UNKNOWN
);
5069 round_optab
= init_optab (UNKNOWN
);
5070 btrunc_optab
= init_optab (UNKNOWN
);
5071 nearbyint_optab
= init_optab (UNKNOWN
);
5072 rint_optab
= init_optab (UNKNOWN
);
5073 lrint_optab
= init_optab (UNKNOWN
);
5074 sincos_optab
= init_optab (UNKNOWN
);
5075 sin_optab
= init_optab (UNKNOWN
);
5076 asin_optab
= init_optab (UNKNOWN
);
5077 cos_optab
= init_optab (UNKNOWN
);
5078 acos_optab
= init_optab (UNKNOWN
);
5079 exp_optab
= init_optab (UNKNOWN
);
5080 exp10_optab
= init_optab (UNKNOWN
);
5081 exp2_optab
= init_optab (UNKNOWN
);
5082 expm1_optab
= init_optab (UNKNOWN
);
5083 ldexp_optab
= init_optab (UNKNOWN
);
5084 logb_optab
= init_optab (UNKNOWN
);
5085 ilogb_optab
= init_optab (UNKNOWN
);
5086 log_optab
= init_optab (UNKNOWN
);
5087 log10_optab
= init_optab (UNKNOWN
);
5088 log2_optab
= init_optab (UNKNOWN
);
5089 log1p_optab
= init_optab (UNKNOWN
);
5090 tan_optab
= init_optab (UNKNOWN
);
5091 atan_optab
= init_optab (UNKNOWN
);
5092 copysign_optab
= init_optab (UNKNOWN
);
5094 strlen_optab
= init_optab (UNKNOWN
);
5095 cbranch_optab
= init_optab (UNKNOWN
);
5096 cmov_optab
= init_optab (UNKNOWN
);
5097 cstore_optab
= init_optab (UNKNOWN
);
5098 push_optab
= init_optab (UNKNOWN
);
5100 reduc_smax_optab
= init_optab (UNKNOWN
);
5101 reduc_umax_optab
= init_optab (UNKNOWN
);
5102 reduc_smin_optab
= init_optab (UNKNOWN
);
5103 reduc_umin_optab
= init_optab (UNKNOWN
);
5104 reduc_splus_optab
= init_optab (UNKNOWN
);
5105 reduc_uplus_optab
= init_optab (UNKNOWN
);
5107 vec_extract_optab
= init_optab (UNKNOWN
);
5108 vec_set_optab
= init_optab (UNKNOWN
);
5109 vec_init_optab
= init_optab (UNKNOWN
);
5110 vec_shl_optab
= init_optab (UNKNOWN
);
5111 vec_shr_optab
= init_optab (UNKNOWN
);
5112 vec_realign_load_optab
= init_optab (UNKNOWN
);
5113 movmisalign_optab
= init_optab (UNKNOWN
);
5115 powi_optab
= init_optab (UNKNOWN
);
5118 sext_optab
= init_convert_optab (SIGN_EXTEND
);
5119 zext_optab
= init_convert_optab (ZERO_EXTEND
);
5120 trunc_optab
= init_convert_optab (TRUNCATE
);
5121 sfix_optab
= init_convert_optab (FIX
);
5122 ufix_optab
= init_convert_optab (UNSIGNED_FIX
);
5123 sfixtrunc_optab
= init_convert_optab (UNKNOWN
);
5124 ufixtrunc_optab
= init_convert_optab (UNKNOWN
);
5125 sfloat_optab
= init_convert_optab (FLOAT
);
5126 ufloat_optab
= init_convert_optab (UNSIGNED_FLOAT
);
5128 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
5130 movmem_optab
[i
] = CODE_FOR_nothing
;
5131 cmpstr_optab
[i
] = CODE_FOR_nothing
;
5132 cmpstrn_optab
[i
] = CODE_FOR_nothing
;
5133 cmpmem_optab
[i
] = CODE_FOR_nothing
;
5134 setmem_optab
[i
] = CODE_FOR_nothing
;
5136 sync_add_optab
[i
] = CODE_FOR_nothing
;
5137 sync_sub_optab
[i
] = CODE_FOR_nothing
;
5138 sync_ior_optab
[i
] = CODE_FOR_nothing
;
5139 sync_and_optab
[i
] = CODE_FOR_nothing
;
5140 sync_xor_optab
[i
] = CODE_FOR_nothing
;
5141 sync_nand_optab
[i
] = CODE_FOR_nothing
;
5142 sync_old_add_optab
[i
] = CODE_FOR_nothing
;
5143 sync_old_sub_optab
[i
] = CODE_FOR_nothing
;
5144 sync_old_ior_optab
[i
] = CODE_FOR_nothing
;
5145 sync_old_and_optab
[i
] = CODE_FOR_nothing
;
5146 sync_old_xor_optab
[i
] = CODE_FOR_nothing
;
5147 sync_old_nand_optab
[i
] = CODE_FOR_nothing
;
5148 sync_new_add_optab
[i
] = CODE_FOR_nothing
;
5149 sync_new_sub_optab
[i
] = CODE_FOR_nothing
;
5150 sync_new_ior_optab
[i
] = CODE_FOR_nothing
;
5151 sync_new_and_optab
[i
] = CODE_FOR_nothing
;
5152 sync_new_xor_optab
[i
] = CODE_FOR_nothing
;
5153 sync_new_nand_optab
[i
] = CODE_FOR_nothing
;
5154 sync_compare_and_swap
[i
] = CODE_FOR_nothing
;
5155 sync_compare_and_swap_cc
[i
] = CODE_FOR_nothing
;
5156 sync_lock_test_and_set
[i
] = CODE_FOR_nothing
;
5157 sync_lock_release
[i
] = CODE_FOR_nothing
;
5159 #ifdef HAVE_SECONDARY_RELOADS
5160 reload_in_optab
[i
] = reload_out_optab
[i
] = CODE_FOR_nothing
;
5164 /* Fill in the optabs with the insns we support. */
5167 /* Initialize the optabs with the names of the library functions. */
5168 init_integral_libfuncs (add_optab
, "add", '3');
5169 init_floating_libfuncs (add_optab
, "add", '3');
5170 init_integral_libfuncs (addv_optab
, "addv", '3');
5171 init_floating_libfuncs (addv_optab
, "add", '3');
5172 init_integral_libfuncs (sub_optab
, "sub", '3');
5173 init_floating_libfuncs (sub_optab
, "sub", '3');
5174 init_integral_libfuncs (subv_optab
, "subv", '3');
5175 init_floating_libfuncs (subv_optab
, "sub", '3');
5176 init_integral_libfuncs (smul_optab
, "mul", '3');
5177 init_floating_libfuncs (smul_optab
, "mul", '3');
5178 init_integral_libfuncs (smulv_optab
, "mulv", '3');
5179 init_floating_libfuncs (smulv_optab
, "mul", '3');
5180 init_integral_libfuncs (sdiv_optab
, "div", '3');
5181 init_floating_libfuncs (sdiv_optab
, "div", '3');
5182 init_integral_libfuncs (sdivv_optab
, "divv", '3');
5183 init_integral_libfuncs (udiv_optab
, "udiv", '3');
5184 init_integral_libfuncs (sdivmod_optab
, "divmod", '4');
5185 init_integral_libfuncs (udivmod_optab
, "udivmod", '4');
5186 init_integral_libfuncs (smod_optab
, "mod", '3');
5187 init_integral_libfuncs (umod_optab
, "umod", '3');
5188 init_floating_libfuncs (ftrunc_optab
, "ftrunc", '2');
5189 init_integral_libfuncs (and_optab
, "and", '3');
5190 init_integral_libfuncs (ior_optab
, "ior", '3');
5191 init_integral_libfuncs (xor_optab
, "xor", '3');
5192 init_integral_libfuncs (ashl_optab
, "ashl", '3');
5193 init_integral_libfuncs (ashr_optab
, "ashr", '3');
5194 init_integral_libfuncs (lshr_optab
, "lshr", '3');
5195 init_integral_libfuncs (smin_optab
, "min", '3');
5196 init_floating_libfuncs (smin_optab
, "min", '3');
5197 init_integral_libfuncs (smax_optab
, "max", '3');
5198 init_floating_libfuncs (smax_optab
, "max", '3');
5199 init_integral_libfuncs (umin_optab
, "umin", '3');
5200 init_integral_libfuncs (umax_optab
, "umax", '3');
5201 init_integral_libfuncs (neg_optab
, "neg", '2');
5202 init_floating_libfuncs (neg_optab
, "neg", '2');
5203 init_integral_libfuncs (negv_optab
, "negv", '2');
5204 init_floating_libfuncs (negv_optab
, "neg", '2');
5205 init_integral_libfuncs (one_cmpl_optab
, "one_cmpl", '2');
5206 init_integral_libfuncs (ffs_optab
, "ffs", '2');
5207 init_integral_libfuncs (clz_optab
, "clz", '2');
5208 init_integral_libfuncs (ctz_optab
, "ctz", '2');
5209 init_integral_libfuncs (popcount_optab
, "popcount", '2');
5210 init_integral_libfuncs (parity_optab
, "parity", '2');
5212 /* Comparison libcalls for integers MUST come in pairs,
5214 init_integral_libfuncs (cmp_optab
, "cmp", '2');
5215 init_integral_libfuncs (ucmp_optab
, "ucmp", '2');
5216 init_floating_libfuncs (cmp_optab
, "cmp", '2');
5218 /* EQ etc are floating point only. */
5219 init_floating_libfuncs (eq_optab
, "eq", '2');
5220 init_floating_libfuncs (ne_optab
, "ne", '2');
5221 init_floating_libfuncs (gt_optab
, "gt", '2');
5222 init_floating_libfuncs (ge_optab
, "ge", '2');
5223 init_floating_libfuncs (lt_optab
, "lt", '2');
5224 init_floating_libfuncs (le_optab
, "le", '2');
5225 init_floating_libfuncs (unord_optab
, "unord", '2');
5227 init_floating_libfuncs (powi_optab
, "powi", '2');
5230 init_interclass_conv_libfuncs (sfloat_optab
, "float",
5231 MODE_INT
, MODE_FLOAT
);
5232 init_interclass_conv_libfuncs (sfix_optab
, "fix",
5233 MODE_FLOAT
, MODE_INT
);
5234 init_interclass_conv_libfuncs (ufix_optab
, "fixuns",
5235 MODE_FLOAT
, MODE_INT
);
5237 /* sext_optab is also used for FLOAT_EXTEND. */
5238 init_intraclass_conv_libfuncs (sext_optab
, "extend", MODE_FLOAT
, true);
5239 init_intraclass_conv_libfuncs (trunc_optab
, "trunc", MODE_FLOAT
, false);
5241 /* Use cabs for double complex abs, since systems generally have cabs.
5242 Don't define any libcall for float complex, so that cabs will be used. */
5243 if (complex_double_type_node
)
5244 abs_optab
->handlers
[TYPE_MODE (complex_double_type_node
)].libfunc
5245 = init_one_libfunc ("cabs");
5247 /* The ffs function operates on `int'. */
5248 ffs_optab
->handlers
[(int) mode_for_size (INT_TYPE_SIZE
, MODE_INT
, 0)].libfunc
5249 = init_one_libfunc ("ffs");
5251 abort_libfunc
= init_one_libfunc ("abort");
5252 memcpy_libfunc
= init_one_libfunc ("memcpy");
5253 memmove_libfunc
= init_one_libfunc ("memmove");
5254 memcmp_libfunc
= init_one_libfunc ("memcmp");
5255 memset_libfunc
= init_one_libfunc ("memset");
5256 setbits_libfunc
= init_one_libfunc ("__setbits");
5258 #ifndef DONT_USE_BUILTIN_SETJMP
5259 setjmp_libfunc
= init_one_libfunc ("__builtin_setjmp");
5260 longjmp_libfunc
= init_one_libfunc ("__builtin_longjmp");
5262 setjmp_libfunc
= init_one_libfunc ("setjmp");
5263 longjmp_libfunc
= init_one_libfunc ("longjmp");
5265 unwind_sjlj_register_libfunc
= init_one_libfunc ("_Unwind_SjLj_Register");
5266 unwind_sjlj_unregister_libfunc
5267 = init_one_libfunc ("_Unwind_SjLj_Unregister");
5269 /* For function entry/exit instrumentation. */
5270 profile_function_entry_libfunc
5271 = init_one_libfunc ("__cyg_profile_func_enter");
5272 profile_function_exit_libfunc
5273 = init_one_libfunc ("__cyg_profile_func_exit");
5275 gcov_flush_libfunc
= init_one_libfunc ("__gcov_flush");
5277 if (HAVE_conditional_trap
)
5278 trap_rtx
= gen_rtx_fmt_ee (EQ
, VOIDmode
, NULL_RTX
, NULL_RTX
);
5280 /* Allow the target to add more libcalls or rename some, etc. */
5281 targetm
.init_libfuncs ();
5286 /* Print information about the current contents of the optabs on
5290 debug_optab_libfuncs (void)
5296 /* Dump the arithmetic optabs. */
5297 for (i
= 0; i
!= (int) OTI_MAX
; i
++)
5298 for (j
= 0; j
< NUM_MACHINE_MODES
; ++j
)
5301 struct optab_handlers
*h
;
5304 h
= &o
->handlers
[j
];
5307 gcc_assert (GET_CODE (h
->libfunc
) = SYMBOL_REF
);
5308 fprintf (stderr
, "%s\t%s:\t%s\n",
5309 GET_RTX_NAME (o
->code
),
5311 XSTR (h
->libfunc
, 0));
5315 /* Dump the conversion optabs. */
5316 for (i
= 0; i
< (int) COI_MAX
; ++i
)
5317 for (j
= 0; j
< NUM_MACHINE_MODES
; ++j
)
5318 for (k
= 0; k
< NUM_MACHINE_MODES
; ++k
)
5321 struct optab_handlers
*h
;
5323 o
= &convert_optab_table
[i
];
5324 h
= &o
->handlers
[j
][k
];
5327 gcc_assert (GET_CODE (h
->libfunc
) = SYMBOL_REF
);
5328 fprintf (stderr
, "%s\t%s\t%s:\t%s\n",
5329 GET_RTX_NAME (o
->code
),
5332 XSTR (h
->libfunc
, 0));
5340 /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition
5341 CODE. Return 0 on failure. */
5344 gen_cond_trap (enum rtx_code code ATTRIBUTE_UNUSED
, rtx op1
,
5345 rtx op2 ATTRIBUTE_UNUSED
, rtx tcode ATTRIBUTE_UNUSED
)
5347 enum machine_mode mode
= GET_MODE (op1
);
5348 enum insn_code icode
;
5351 if (!HAVE_conditional_trap
)
5354 if (mode
== VOIDmode
)
5357 icode
= cmp_optab
->handlers
[(int) mode
].insn_code
;
5358 if (icode
== CODE_FOR_nothing
)
5362 op1
= prepare_operand (icode
, op1
, 0, mode
, mode
, 0);
5363 op2
= prepare_operand (icode
, op2
, 1, mode
, mode
, 0);
5369 emit_insn (GEN_FCN (icode
) (op1
, op2
));
5371 PUT_CODE (trap_rtx
, code
);
5372 gcc_assert (HAVE_conditional_trap
);
5373 insn
= gen_conditional_trap (trap_rtx
, tcode
);
5377 insn
= get_insns ();
5384 /* Return rtx code for TCODE. Use UNSIGNEDP to select signed
5385 or unsigned operation code. */
5387 static enum rtx_code
5388 get_rtx_code (enum tree_code tcode
, bool unsignedp
)
5400 code
= unsignedp
? LTU
: LT
;
5403 code
= unsignedp
? LEU
: LE
;
5406 code
= unsignedp
? GTU
: GT
;
5409 code
= unsignedp
? GEU
: GE
;
5412 case UNORDERED_EXPR
:
5443 /* Return comparison rtx for COND. Use UNSIGNEDP to select signed or
5444 unsigned operators. Do not generate compare instruction. */
5447 vector_compare_rtx (tree cond
, bool unsignedp
, enum insn_code icode
)
5449 enum rtx_code rcode
;
5451 rtx rtx_op0
, rtx_op1
;
5453 /* This is unlikely. While generating VEC_COND_EXPR, auto vectorizer
5454 ensures that condition is a relational operation. */
5455 gcc_assert (COMPARISON_CLASS_P (cond
));
5457 rcode
= get_rtx_code (TREE_CODE (cond
), unsignedp
);
5458 t_op0
= TREE_OPERAND (cond
, 0);
5459 t_op1
= TREE_OPERAND (cond
, 1);
5461 /* Expand operands. */
5462 rtx_op0
= expand_expr (t_op0
, NULL_RTX
, TYPE_MODE (TREE_TYPE (t_op0
)), 1);
5463 rtx_op1
= expand_expr (t_op1
, NULL_RTX
, TYPE_MODE (TREE_TYPE (t_op1
)), 1);
5465 if (!insn_data
[icode
].operand
[4].predicate (rtx_op0
, GET_MODE (rtx_op0
))
5466 && GET_MODE (rtx_op0
) != VOIDmode
)
5467 rtx_op0
= force_reg (GET_MODE (rtx_op0
), rtx_op0
);
5469 if (!insn_data
[icode
].operand
[5].predicate (rtx_op1
, GET_MODE (rtx_op1
))
5470 && GET_MODE (rtx_op1
) != VOIDmode
)
5471 rtx_op1
= force_reg (GET_MODE (rtx_op1
), rtx_op1
);
5473 return gen_rtx_fmt_ee (rcode
, VOIDmode
, rtx_op0
, rtx_op1
);
5476 /* Return insn code for VEC_COND_EXPR EXPR. */
5478 static inline enum insn_code
5479 get_vcond_icode (tree expr
, enum machine_mode mode
)
5481 enum insn_code icode
= CODE_FOR_nothing
;
5483 if (TYPE_UNSIGNED (TREE_TYPE (expr
)))
5484 icode
= vcondu_gen_code
[mode
];
5486 icode
= vcond_gen_code
[mode
];
5490 /* Return TRUE iff, appropriate vector insns are available
5491 for vector cond expr expr in VMODE mode. */
5494 expand_vec_cond_expr_p (tree expr
, enum machine_mode vmode
)
5496 if (get_vcond_icode (expr
, vmode
) == CODE_FOR_nothing
)
5501 /* Generate insns for VEC_COND_EXPR. */
5504 expand_vec_cond_expr (tree vec_cond_expr
, rtx target
)
5506 enum insn_code icode
;
5507 rtx comparison
, rtx_op1
, rtx_op2
, cc_op0
, cc_op1
;
5508 enum machine_mode mode
= TYPE_MODE (TREE_TYPE (vec_cond_expr
));
5509 bool unsignedp
= TYPE_UNSIGNED (TREE_TYPE (vec_cond_expr
));
5511 icode
= get_vcond_icode (vec_cond_expr
, mode
);
5512 if (icode
== CODE_FOR_nothing
)
5515 if (!target
|| !insn_data
[icode
].operand
[0].predicate (target
, mode
))
5516 target
= gen_reg_rtx (mode
);
5518 /* Get comparison rtx. First expand both cond expr operands. */
5519 comparison
= vector_compare_rtx (TREE_OPERAND (vec_cond_expr
, 0),
5521 cc_op0
= XEXP (comparison
, 0);
5522 cc_op1
= XEXP (comparison
, 1);
5523 /* Expand both operands and force them in reg, if required. */
5524 rtx_op1
= expand_expr (TREE_OPERAND (vec_cond_expr
, 1),
5525 NULL_RTX
, VOIDmode
, 1);
5526 if (!insn_data
[icode
].operand
[1].predicate (rtx_op1
, mode
)
5527 && mode
!= VOIDmode
)
5528 rtx_op1
= force_reg (mode
, rtx_op1
);
5530 rtx_op2
= expand_expr (TREE_OPERAND (vec_cond_expr
, 2),
5531 NULL_RTX
, VOIDmode
, 1);
5532 if (!insn_data
[icode
].operand
[2].predicate (rtx_op2
, mode
)
5533 && mode
!= VOIDmode
)
5534 rtx_op2
= force_reg (mode
, rtx_op2
);
5536 /* Emit instruction! */
5537 emit_insn (GEN_FCN (icode
) (target
, rtx_op1
, rtx_op2
,
5538 comparison
, cc_op0
, cc_op1
));
5544 /* This is an internal subroutine of the other compare_and_swap expanders.
5545 MEM, OLD_VAL and NEW_VAL are as you'd expect for a compare-and-swap
5546 operation. TARGET is an optional place to store the value result of
5547 the operation. ICODE is the particular instruction to expand. Return
5548 the result of the operation. */
5551 expand_val_compare_and_swap_1 (rtx mem
, rtx old_val
, rtx new_val
,
5552 rtx target
, enum insn_code icode
)
5554 enum machine_mode mode
= GET_MODE (mem
);
5557 if (!target
|| !insn_data
[icode
].operand
[0].predicate (target
, mode
))
5558 target
= gen_reg_rtx (mode
);
5560 if (GET_MODE (old_val
) != VOIDmode
&& GET_MODE (old_val
) != mode
)
5561 old_val
= convert_modes (mode
, GET_MODE (old_val
), old_val
, 1);
5562 if (!insn_data
[icode
].operand
[2].predicate (old_val
, mode
))
5563 old_val
= force_reg (mode
, old_val
);
5565 if (GET_MODE (new_val
) != VOIDmode
&& GET_MODE (new_val
) != mode
)
5566 new_val
= convert_modes (mode
, GET_MODE (new_val
), new_val
, 1);
5567 if (!insn_data
[icode
].operand
[3].predicate (new_val
, mode
))
5568 new_val
= force_reg (mode
, new_val
);
5570 insn
= GEN_FCN (icode
) (target
, mem
, old_val
, new_val
);
5571 if (insn
== NULL_RTX
)
5578 /* Expand a compare-and-swap operation and return its value. */
5581 expand_val_compare_and_swap (rtx mem
, rtx old_val
, rtx new_val
, rtx target
)
5583 enum machine_mode mode
= GET_MODE (mem
);
5584 enum insn_code icode
= sync_compare_and_swap
[mode
];
5586 if (icode
== CODE_FOR_nothing
)
5589 return expand_val_compare_and_swap_1 (mem
, old_val
, new_val
, target
, icode
);
5592 /* Expand a compare-and-swap operation and store true into the result if
5593 the operation was successful and false otherwise. Return the result.
5594 Unlike other routines, TARGET is not optional. */
5597 expand_bool_compare_and_swap (rtx mem
, rtx old_val
, rtx new_val
, rtx target
)
5599 enum machine_mode mode
= GET_MODE (mem
);
5600 enum insn_code icode
;
5601 rtx subtarget
, label0
, label1
;
5603 /* If the target supports a compare-and-swap pattern that simultaneously
5604 sets some flag for success, then use it. Otherwise use the regular
5605 compare-and-swap and follow that immediately with a compare insn. */
5606 icode
= sync_compare_and_swap_cc
[mode
];
5610 subtarget
= expand_val_compare_and_swap_1 (mem
, old_val
, new_val
,
5612 if (subtarget
!= NULL_RTX
)
5616 case CODE_FOR_nothing
:
5617 icode
= sync_compare_and_swap
[mode
];
5618 if (icode
== CODE_FOR_nothing
)
5621 /* Ensure that if old_val == mem, that we're not comparing
5622 against an old value. */
5623 if (MEM_P (old_val
))
5624 old_val
= force_reg (mode
, old_val
);
5626 subtarget
= expand_val_compare_and_swap_1 (mem
, old_val
, new_val
,
5628 if (subtarget
== NULL_RTX
)
5631 emit_cmp_insn (subtarget
, old_val
, EQ
, const0_rtx
, mode
, true);
5634 /* If the target has a sane STORE_FLAG_VALUE, then go ahead and use a
5635 setcc instruction from the beginning. We don't work too hard here,
5636 but it's nice to not be stupid about initial code gen either. */
5637 if (STORE_FLAG_VALUE
== 1)
5639 icode
= setcc_gen_code
[EQ
];
5640 if (icode
!= CODE_FOR_nothing
)
5642 enum machine_mode cmode
= insn_data
[icode
].operand
[0].mode
;
5646 if (!insn_data
[icode
].operand
[0].predicate (target
, cmode
))
5647 subtarget
= gen_reg_rtx (cmode
);
5649 insn
= GEN_FCN (icode
) (subtarget
);
5653 if (GET_MODE (target
) != GET_MODE (subtarget
))
5655 convert_move (target
, subtarget
, 1);
5663 /* Without an appropriate setcc instruction, use a set of branches to
5664 get 1 and 0 stored into target. Presumably if the target has a
5665 STORE_FLAG_VALUE that isn't 1, then this will get cleaned up by ifcvt. */
5667 label0
= gen_label_rtx ();
5668 label1
= gen_label_rtx ();
5670 emit_jump_insn (bcc_gen_fctn
[EQ
] (label0
));
5671 emit_move_insn (target
, const0_rtx
);
5672 emit_jump_insn (gen_jump (label1
));
5674 emit_label (label0
);
5675 emit_move_insn (target
, const1_rtx
);
5676 emit_label (label1
);
5681 /* This is a helper function for the other atomic operations. This function
5682 emits a loop that contains SEQ that iterates until a compare-and-swap
5683 operation at the end succeeds. MEM is the memory to be modified. SEQ is
5684 a set of instructions that takes a value from OLD_REG as an input and
5685 produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be
5686 set to the current contents of MEM. After SEQ, a compare-and-swap will
5687 attempt to update MEM with NEW_REG. The function returns true when the
5688 loop was generated successfully. */
5691 expand_compare_and_swap_loop (rtx mem
, rtx old_reg
, rtx new_reg
, rtx seq
)
5693 enum machine_mode mode
= GET_MODE (mem
);
5694 enum insn_code icode
;
5695 rtx label
, cmp_reg
, subtarget
;
5697 /* The loop we want to generate looks like
5703 cmp_reg = compare-and-swap(mem, old_reg, new_reg)
5704 if (cmp_reg != old_reg)
5707 Note that we only do the plain load from memory once. Subsequent
5708 iterations use the value loaded by the compare-and-swap pattern. */
5710 label
= gen_label_rtx ();
5711 cmp_reg
= gen_reg_rtx (mode
);
5713 emit_move_insn (cmp_reg
, mem
);
5715 emit_move_insn (old_reg
, cmp_reg
);
5719 /* If the target supports a compare-and-swap pattern that simultaneously
5720 sets some flag for success, then use it. Otherwise use the regular
5721 compare-and-swap and follow that immediately with a compare insn. */
5722 icode
= sync_compare_and_swap_cc
[mode
];
5726 subtarget
= expand_val_compare_and_swap_1 (mem
, old_reg
, new_reg
,
5728 if (subtarget
!= NULL_RTX
)
5730 gcc_assert (subtarget
== cmp_reg
);
5735 case CODE_FOR_nothing
:
5736 icode
= sync_compare_and_swap
[mode
];
5737 if (icode
== CODE_FOR_nothing
)
5740 subtarget
= expand_val_compare_and_swap_1 (mem
, old_reg
, new_reg
,
5742 if (subtarget
== NULL_RTX
)
5744 if (subtarget
!= cmp_reg
)
5745 emit_move_insn (cmp_reg
, subtarget
);
5747 emit_cmp_insn (cmp_reg
, old_reg
, EQ
, const0_rtx
, mode
, true);
5750 /* ??? Mark this jump predicted not taken? */
5751 emit_jump_insn (bcc_gen_fctn
[NE
] (label
));
5756 /* This function generates the atomic operation MEM CODE= VAL. In this
5757 case, we do not care about any resulting value. Returns NULL if we
5758 cannot generate the operation. */
5761 expand_sync_operation (rtx mem
, rtx val
, enum rtx_code code
)
5763 enum machine_mode mode
= GET_MODE (mem
);
5764 enum insn_code icode
;
5767 /* Look to see if the target supports the operation directly. */
5771 icode
= sync_add_optab
[mode
];
5774 icode
= sync_ior_optab
[mode
];
5777 icode
= sync_xor_optab
[mode
];
5780 icode
= sync_and_optab
[mode
];
5783 icode
= sync_nand_optab
[mode
];
5787 icode
= sync_sub_optab
[mode
];
5788 if (icode
== CODE_FOR_nothing
)
5790 icode
= sync_add_optab
[mode
];
5791 if (icode
!= CODE_FOR_nothing
)
5793 val
= expand_simple_unop (mode
, NEG
, val
, NULL_RTX
, 1);
5803 /* Generate the direct operation, if present. */
5804 if (icode
!= CODE_FOR_nothing
)
5806 if (GET_MODE (val
) != VOIDmode
&& GET_MODE (val
) != mode
)
5807 val
= convert_modes (mode
, GET_MODE (val
), val
, 1);
5808 if (!insn_data
[icode
].operand
[1].predicate (val
, mode
))
5809 val
= force_reg (mode
, val
);
5811 insn
= GEN_FCN (icode
) (mem
, val
);
5819 /* Failing that, generate a compare-and-swap loop in which we perform the
5820 operation with normal arithmetic instructions. */
5821 if (sync_compare_and_swap
[mode
] != CODE_FOR_nothing
)
5823 rtx t0
= gen_reg_rtx (mode
), t1
;
5830 t1
= expand_simple_unop (mode
, NOT
, t1
, NULL_RTX
, true);
5833 t1
= expand_simple_binop (mode
, code
, t1
, val
, NULL_RTX
,
5834 true, OPTAB_LIB_WIDEN
);
5836 insn
= get_insns ();
5839 if (t1
!= NULL
&& expand_compare_and_swap_loop (mem
, t0
, t1
, insn
))
5846 /* This function generates the atomic operation MEM CODE= VAL. In this
5847 case, we do care about the resulting value: if AFTER is true then
5848 return the value MEM holds after the operation, if AFTER is false
5849 then return the value MEM holds before the operation. TARGET is an
5850 optional place for the result value to be stored. */
5853 expand_sync_fetch_operation (rtx mem
, rtx val
, enum rtx_code code
,
5854 bool after
, rtx target
)
5856 enum machine_mode mode
= GET_MODE (mem
);
5857 enum insn_code old_code
, new_code
, icode
;
5861 /* Look to see if the target supports the operation directly. */
5865 old_code
= sync_old_add_optab
[mode
];
5866 new_code
= sync_new_add_optab
[mode
];
5869 old_code
= sync_old_ior_optab
[mode
];
5870 new_code
= sync_new_ior_optab
[mode
];
5873 old_code
= sync_old_xor_optab
[mode
];
5874 new_code
= sync_new_xor_optab
[mode
];
5877 old_code
= sync_old_and_optab
[mode
];
5878 new_code
= sync_new_and_optab
[mode
];
5881 old_code
= sync_old_nand_optab
[mode
];
5882 new_code
= sync_new_nand_optab
[mode
];
5886 old_code
= sync_old_sub_optab
[mode
];
5887 new_code
= sync_new_sub_optab
[mode
];
5888 if (old_code
== CODE_FOR_nothing
&& new_code
== CODE_FOR_nothing
)
5890 old_code
= sync_old_add_optab
[mode
];
5891 new_code
= sync_new_add_optab
[mode
];
5892 if (old_code
!= CODE_FOR_nothing
|| new_code
!= CODE_FOR_nothing
)
5894 val
= expand_simple_unop (mode
, NEG
, val
, NULL_RTX
, 1);
5904 /* If the target does supports the proper new/old operation, great. But
5905 if we only support the opposite old/new operation, check to see if we
5906 can compensate. In the case in which the old value is supported, then
5907 we can always perform the operation again with normal arithmetic. In
5908 the case in which the new value is supported, then we can only handle
5909 this in the case the operation is reversible. */
5914 if (icode
== CODE_FOR_nothing
)
5917 if (icode
!= CODE_FOR_nothing
)
5924 if (icode
== CODE_FOR_nothing
5925 && (code
== PLUS
|| code
== MINUS
|| code
== XOR
))
5928 if (icode
!= CODE_FOR_nothing
)
5933 /* If we found something supported, great. */
5934 if (icode
!= CODE_FOR_nothing
)
5936 if (!target
|| !insn_data
[icode
].operand
[0].predicate (target
, mode
))
5937 target
= gen_reg_rtx (mode
);
5939 if (GET_MODE (val
) != VOIDmode
&& GET_MODE (val
) != mode
)
5940 val
= convert_modes (mode
, GET_MODE (val
), val
, 1);
5941 if (!insn_data
[icode
].operand
[2].predicate (val
, mode
))
5942 val
= force_reg (mode
, val
);
5944 insn
= GEN_FCN (icode
) (target
, mem
, val
);
5949 /* If we need to compensate for using an operation with the
5950 wrong return value, do so now. */
5957 else if (code
== MINUS
)
5962 target
= expand_simple_unop (mode
, NOT
, target
, NULL_RTX
, true);
5963 target
= expand_simple_binop (mode
, code
, target
, val
, NULL_RTX
,
5964 true, OPTAB_LIB_WIDEN
);
5971 /* Failing that, generate a compare-and-swap loop in which we perform the
5972 operation with normal arithmetic instructions. */
5973 if (sync_compare_and_swap
[mode
] != CODE_FOR_nothing
)
5975 rtx t0
= gen_reg_rtx (mode
), t1
;
5977 if (!target
|| !register_operand (target
, mode
))
5978 target
= gen_reg_rtx (mode
);
5983 emit_move_insn (target
, t0
);
5987 t1
= expand_simple_unop (mode
, NOT
, t1
, NULL_RTX
, true);
5990 t1
= expand_simple_binop (mode
, code
, t1
, val
, NULL_RTX
,
5991 true, OPTAB_LIB_WIDEN
);
5993 emit_move_insn (target
, t1
);
5995 insn
= get_insns ();
5998 if (t1
!= NULL
&& expand_compare_and_swap_loop (mem
, t0
, t1
, insn
))
6005 /* This function expands a test-and-set operation. Ideally we atomically
6006 store VAL in MEM and return the previous value in MEM. Some targets
6007 may not support this operation and only support VAL with the constant 1;
6008 in this case while the return value will be 0/1, but the exact value
6009 stored in MEM is target defined. TARGET is an option place to stick
6010 the return value. */
6013 expand_sync_lock_test_and_set (rtx mem
, rtx val
, rtx target
)
6015 enum machine_mode mode
= GET_MODE (mem
);
6016 enum insn_code icode
;
6019 /* If the target supports the test-and-set directly, great. */
6020 icode
= sync_lock_test_and_set
[mode
];
6021 if (icode
!= CODE_FOR_nothing
)
6023 if (!target
|| !insn_data
[icode
].operand
[0].predicate (target
, mode
))
6024 target
= gen_reg_rtx (mode
);
6026 if (GET_MODE (val
) != VOIDmode
&& GET_MODE (val
) != mode
)
6027 val
= convert_modes (mode
, GET_MODE (val
), val
, 1);
6028 if (!insn_data
[icode
].operand
[2].predicate (val
, mode
))
6029 val
= force_reg (mode
, val
);
6031 insn
= GEN_FCN (icode
) (target
, mem
, val
);
6039 /* Otherwise, use a compare-and-swap loop for the exchange. */
6040 if (sync_compare_and_swap
[mode
] != CODE_FOR_nothing
)
6042 if (!target
|| !register_operand (target
, mode
))
6043 target
= gen_reg_rtx (mode
);
6044 if (GET_MODE (val
) != VOIDmode
&& GET_MODE (val
) != mode
)
6045 val
= convert_modes (mode
, GET_MODE (val
), val
, 1);
6046 if (expand_compare_and_swap_loop (mem
, target
, val
, NULL_RTX
))
6053 #include "gt-optabs.h"