PR rtl-optimization/60116
[official-gcc.git] / gcc / combine.c
blob1b598b409323ca6f230f5abed2f094d0f80a4daf
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
78 #include "config.h"
79 #include "system.h"
80 #include "coretypes.h"
81 #include "tm.h"
82 #include "rtl.h"
83 #include "tree.h"
84 #include "stor-layout.h"
85 #include "tm_p.h"
86 #include "flags.h"
87 #include "regs.h"
88 #include "hard-reg-set.h"
89 #include "basic-block.h"
90 #include "insn-config.h"
91 #include "function.h"
92 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "expr.h"
94 #include "insn-attr.h"
95 #include "recog.h"
96 #include "diagnostic-core.h"
97 #include "target.h"
98 #include "optabs.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 #include "params.h"
102 #include "tree-pass.h"
103 #include "df.h"
104 #include "valtrack.h"
105 #include "cgraph.h"
106 #include "obstack.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras;
120 /* Number of instructions combined in this function. */
122 static int combine_successes;
124 /* Totals over entire compilation. */
126 static int total_attempts, total_merges, total_extras, total_successes;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
135 static rtx i2mod;
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs;
145 typedef struct reg_stat_struct {
146 /* Record last point of death of (hard or pseudo) register n. */
147 rtx last_death;
149 /* Record last point of modification of (hard or pseudo) register n. */
150 rtx last_set;
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
159 following ways:
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
174 register's value
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
179 table.
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
197 rtx last_set_value;
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick;
204 /* Record the value of label_tick when the value for register n is placed in
205 last_set_value. */
207 int last_set_label;
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits;
215 char last_set_sign_bit_copies;
216 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
232 zero.
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies;
238 unsigned HOST_WIDE_INT nonzero_bits;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
249 value. */
251 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
252 } reg_stat_type;
255 static vec<reg_stat_type> reg_stat;
257 /* Record the luid of the last insn that invalidated memory
258 (anything that writes memory, and subroutine calls, but not pushes). */
260 static int mem_last_set;
262 /* Record the luid of the last CALL_INSN
263 so we can tell whether a potential combination crosses any calls. */
265 static int last_call_luid;
267 /* When `subst' is called, this is the insn that is being modified
268 (by combining in a previous insn). The PATTERN of this insn
269 is still the old pattern partially modified and it should not be
270 looked at, but this may be used to examine the successors of the insn
271 to judge whether a simplification is valid. */
273 static rtx subst_insn;
275 /* This is the lowest LUID that `subst' is currently dealing with.
276 get_last_value will not return a value if the register was set at or
277 after this LUID. If not for this mechanism, we could get confused if
278 I2 or I1 in try_combine were an insn that used the old value of a register
279 to obtain a new value. In that case, we might erroneously get the
280 new value of the register when we wanted the old one. */
282 static int subst_low_luid;
284 /* This contains any hard registers that are used in newpat; reg_dead_at_p
285 must consider all these registers to be always live. */
287 static HARD_REG_SET newpat_used_regs;
289 /* This is an insn to which a LOG_LINKS entry has been added. If this
290 insn is the earlier than I2 or I3, combine should rescan starting at
291 that location. */
293 static rtx added_links_insn;
295 /* Basic block in which we are performing combines. */
296 static basic_block this_basic_block;
297 static bool optimize_this_for_speed_p;
300 /* Length of the currently allocated uid_insn_cost array. */
302 static int max_uid_known;
304 /* The following array records the insn_rtx_cost for every insn
305 in the instruction stream. */
307 static int *uid_insn_cost;
309 /* The following array records the LOG_LINKS for every insn in the
310 instruction stream as struct insn_link pointers. */
312 struct insn_link {
313 rtx insn;
314 struct insn_link *next;
317 static struct insn_link **uid_log_links;
319 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
320 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
322 #define FOR_EACH_LOG_LINK(L, INSN) \
323 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
325 /* Links for LOG_LINKS are allocated from this obstack. */
327 static struct obstack insn_link_obstack;
329 /* Allocate a link. */
331 static inline struct insn_link *
332 alloc_insn_link (rtx insn, struct insn_link *next)
334 struct insn_link *l
335 = (struct insn_link *) obstack_alloc (&insn_link_obstack,
336 sizeof (struct insn_link));
337 l->insn = insn;
338 l->next = next;
339 return l;
342 /* Incremented for each basic block. */
344 static int label_tick;
346 /* Reset to label_tick for each extended basic block in scanning order. */
348 static int label_tick_ebb_start;
350 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
351 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
353 static enum machine_mode nonzero_bits_mode;
355 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
356 be safely used. It is zero while computing them and after combine has
357 completed. This former test prevents propagating values based on
358 previously set values, which can be incorrect if a variable is modified
359 in a loop. */
361 static int nonzero_sign_valid;
364 /* Record one modification to rtl structure
365 to be undone by storing old_contents into *where. */
367 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
369 struct undo
371 struct undo *next;
372 enum undo_kind kind;
373 union { rtx r; int i; enum machine_mode m; struct insn_link *l; } old_contents;
374 union { rtx *r; int *i; struct insn_link **l; } where;
377 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
378 num_undo says how many are currently recorded.
380 other_insn is nonzero if we have modified some other insn in the process
381 of working on subst_insn. It must be verified too. */
383 struct undobuf
385 struct undo *undos;
386 struct undo *frees;
387 rtx other_insn;
390 static struct undobuf undobuf;
392 /* Number of times the pseudo being substituted for
393 was found and replaced. */
395 static int n_occurrences;
397 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
398 enum machine_mode,
399 unsigned HOST_WIDE_INT,
400 unsigned HOST_WIDE_INT *);
401 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
402 enum machine_mode,
403 unsigned int, unsigned int *);
404 static void do_SUBST (rtx *, rtx);
405 static void do_SUBST_INT (int *, int);
406 static void init_reg_last (void);
407 static void setup_incoming_promotions (rtx);
408 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
409 static int cant_combine_insn_p (rtx);
410 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
411 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
412 static int contains_muldiv (rtx);
413 static rtx try_combine (rtx, rtx, rtx, rtx, int *, rtx);
414 static void undo_all (void);
415 static void undo_commit (void);
416 static rtx *find_split_point (rtx *, rtx, bool);
417 static rtx subst (rtx, rtx, rtx, int, int, int);
418 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
419 static rtx simplify_if_then_else (rtx);
420 static rtx simplify_set (rtx);
421 static rtx simplify_logical (rtx);
422 static rtx expand_compound_operation (rtx);
423 static const_rtx expand_field_assignment (const_rtx);
424 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
425 rtx, unsigned HOST_WIDE_INT, int, int, int);
426 static rtx extract_left_shift (rtx, int);
427 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
428 unsigned HOST_WIDE_INT *);
429 static rtx canon_reg_for_combine (rtx, rtx);
430 static rtx force_to_mode (rtx, enum machine_mode,
431 unsigned HOST_WIDE_INT, int);
432 static rtx if_then_else_cond (rtx, rtx *, rtx *);
433 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
434 static int rtx_equal_for_field_assignment_p (rtx, rtx);
435 static rtx make_field_assignment (rtx);
436 static rtx apply_distributive_law (rtx);
437 static rtx distribute_and_simplify_rtx (rtx, int);
438 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
439 unsigned HOST_WIDE_INT);
440 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
441 unsigned HOST_WIDE_INT);
442 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
443 HOST_WIDE_INT, enum machine_mode, int *);
444 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
445 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
446 int);
447 static int recog_for_combine (rtx *, rtx, rtx *);
448 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
449 static enum rtx_code simplify_compare_const (enum rtx_code, rtx, rtx *);
450 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
451 static void update_table_tick (rtx);
452 static void record_value_for_reg (rtx, rtx, rtx);
453 static void check_promoted_subreg (rtx, rtx);
454 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
455 static void record_dead_and_set_regs (rtx);
456 static int get_last_value_validate (rtx *, rtx, int, int);
457 static rtx get_last_value (const_rtx);
458 static int use_crosses_set_p (const_rtx, int);
459 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
460 static int reg_dead_at_p (rtx, rtx);
461 static void move_deaths (rtx, rtx, int, rtx, rtx *);
462 static int reg_bitfield_target_p (rtx, rtx);
463 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
464 static void distribute_links (struct insn_link *);
465 static void mark_used_regs_combine (rtx);
466 static void record_promoted_value (rtx, rtx);
467 static int unmentioned_reg_p_1 (rtx *, void *);
468 static bool unmentioned_reg_p (rtx, rtx);
469 static int record_truncated_value (rtx *, void *);
470 static void record_truncated_values (rtx *, void *);
471 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
472 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
475 /* It is not safe to use ordinary gen_lowpart in combine.
476 See comments in gen_lowpart_for_combine. */
477 #undef RTL_HOOKS_GEN_LOWPART
478 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
480 /* Our implementation of gen_lowpart never emits a new pseudo. */
481 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
482 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
484 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
485 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
487 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
488 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
490 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
491 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
493 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
496 /* Convenience wrapper for the canonicalize_comparison target hook.
497 Target hooks cannot use enum rtx_code. */
498 static inline void
499 target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
500 bool op0_preserve_value)
502 int code_int = (int)*code;
503 targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
504 *code = (enum rtx_code)code_int;
507 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
508 PATTERN can not be split. Otherwise, it returns an insn sequence.
509 This is a wrapper around split_insns which ensures that the
510 reg_stat vector is made larger if the splitter creates a new
511 register. */
513 static rtx
514 combine_split_insns (rtx pattern, rtx insn)
516 rtx ret;
517 unsigned int nregs;
519 ret = split_insns (pattern, insn);
520 nregs = max_reg_num ();
521 if (nregs > reg_stat.length ())
522 reg_stat.safe_grow_cleared (nregs);
523 return ret;
526 /* This is used by find_single_use to locate an rtx in LOC that
527 contains exactly one use of DEST, which is typically either a REG
528 or CC0. It returns a pointer to the innermost rtx expression
529 containing DEST. Appearances of DEST that are being used to
530 totally replace it are not counted. */
532 static rtx *
533 find_single_use_1 (rtx dest, rtx *loc)
535 rtx x = *loc;
536 enum rtx_code code = GET_CODE (x);
537 rtx *result = NULL;
538 rtx *this_result;
539 int i;
540 const char *fmt;
542 switch (code)
544 case CONST:
545 case LABEL_REF:
546 case SYMBOL_REF:
547 CASE_CONST_ANY:
548 case CLOBBER:
549 return 0;
551 case SET:
552 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
553 of a REG that occupies all of the REG, the insn uses DEST if
554 it is mentioned in the destination or the source. Otherwise, we
555 need just check the source. */
556 if (GET_CODE (SET_DEST (x)) != CC0
557 && GET_CODE (SET_DEST (x)) != PC
558 && !REG_P (SET_DEST (x))
559 && ! (GET_CODE (SET_DEST (x)) == SUBREG
560 && REG_P (SUBREG_REG (SET_DEST (x)))
561 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
562 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
563 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
564 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
565 break;
567 return find_single_use_1 (dest, &SET_SRC (x));
569 case MEM:
570 case SUBREG:
571 return find_single_use_1 (dest, &XEXP (x, 0));
573 default:
574 break;
577 /* If it wasn't one of the common cases above, check each expression and
578 vector of this code. Look for a unique usage of DEST. */
580 fmt = GET_RTX_FORMAT (code);
581 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
583 if (fmt[i] == 'e')
585 if (dest == XEXP (x, i)
586 || (REG_P (dest) && REG_P (XEXP (x, i))
587 && REGNO (dest) == REGNO (XEXP (x, i))))
588 this_result = loc;
589 else
590 this_result = find_single_use_1 (dest, &XEXP (x, i));
592 if (result == NULL)
593 result = this_result;
594 else if (this_result)
595 /* Duplicate usage. */
596 return NULL;
598 else if (fmt[i] == 'E')
600 int j;
602 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
604 if (XVECEXP (x, i, j) == dest
605 || (REG_P (dest)
606 && REG_P (XVECEXP (x, i, j))
607 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
608 this_result = loc;
609 else
610 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
612 if (result == NULL)
613 result = this_result;
614 else if (this_result)
615 return NULL;
620 return result;
624 /* See if DEST, produced in INSN, is used only a single time in the
625 sequel. If so, return a pointer to the innermost rtx expression in which
626 it is used.
628 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
630 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
631 care about REG_DEAD notes or LOG_LINKS.
633 Otherwise, we find the single use by finding an insn that has a
634 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
635 only referenced once in that insn, we know that it must be the first
636 and last insn referencing DEST. */
638 static rtx *
639 find_single_use (rtx dest, rtx insn, rtx *ploc)
641 basic_block bb;
642 rtx next;
643 rtx *result;
644 struct insn_link *link;
646 #ifdef HAVE_cc0
647 if (dest == cc0_rtx)
649 next = NEXT_INSN (insn);
650 if (next == 0
651 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
652 return 0;
654 result = find_single_use_1 (dest, &PATTERN (next));
655 if (result && ploc)
656 *ploc = next;
657 return result;
659 #endif
661 if (!REG_P (dest))
662 return 0;
664 bb = BLOCK_FOR_INSN (insn);
665 for (next = NEXT_INSN (insn);
666 next && BLOCK_FOR_INSN (next) == bb;
667 next = NEXT_INSN (next))
668 if (INSN_P (next) && dead_or_set_p (next, dest))
670 FOR_EACH_LOG_LINK (link, next)
671 if (link->insn == insn)
672 break;
674 if (link)
676 result = find_single_use_1 (dest, &PATTERN (next));
677 if (ploc)
678 *ploc = next;
679 return result;
683 return 0;
686 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
687 insn. The substitution can be undone by undo_all. If INTO is already
688 set to NEWVAL, do not record this change. Because computing NEWVAL might
689 also call SUBST, we have to compute it before we put anything into
690 the undo table. */
692 static void
693 do_SUBST (rtx *into, rtx newval)
695 struct undo *buf;
696 rtx oldval = *into;
698 if (oldval == newval)
699 return;
701 /* We'd like to catch as many invalid transformations here as
702 possible. Unfortunately, there are way too many mode changes
703 that are perfectly valid, so we'd waste too much effort for
704 little gain doing the checks here. Focus on catching invalid
705 transformations involving integer constants. */
706 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
707 && CONST_INT_P (newval))
709 /* Sanity check that we're replacing oldval with a CONST_INT
710 that is a valid sign-extension for the original mode. */
711 gcc_assert (INTVAL (newval)
712 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
714 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
715 CONST_INT is not valid, because after the replacement, the
716 original mode would be gone. Unfortunately, we can't tell
717 when do_SUBST is called to replace the operand thereof, so we
718 perform this test on oldval instead, checking whether an
719 invalid replacement took place before we got here. */
720 gcc_assert (!(GET_CODE (oldval) == SUBREG
721 && CONST_INT_P (SUBREG_REG (oldval))));
722 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
723 && CONST_INT_P (XEXP (oldval, 0))));
726 if (undobuf.frees)
727 buf = undobuf.frees, undobuf.frees = buf->next;
728 else
729 buf = XNEW (struct undo);
731 buf->kind = UNDO_RTX;
732 buf->where.r = into;
733 buf->old_contents.r = oldval;
734 *into = newval;
736 buf->next = undobuf.undos, undobuf.undos = buf;
739 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
741 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
742 for the value of a HOST_WIDE_INT value (including CONST_INT) is
743 not safe. */
745 static void
746 do_SUBST_INT (int *into, int newval)
748 struct undo *buf;
749 int oldval = *into;
751 if (oldval == newval)
752 return;
754 if (undobuf.frees)
755 buf = undobuf.frees, undobuf.frees = buf->next;
756 else
757 buf = XNEW (struct undo);
759 buf->kind = UNDO_INT;
760 buf->where.i = into;
761 buf->old_contents.i = oldval;
762 *into = newval;
764 buf->next = undobuf.undos, undobuf.undos = buf;
767 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
769 /* Similar to SUBST, but just substitute the mode. This is used when
770 changing the mode of a pseudo-register, so that any other
771 references to the entry in the regno_reg_rtx array will change as
772 well. */
774 static void
775 do_SUBST_MODE (rtx *into, enum machine_mode newval)
777 struct undo *buf;
778 enum machine_mode oldval = GET_MODE (*into);
780 if (oldval == newval)
781 return;
783 if (undobuf.frees)
784 buf = undobuf.frees, undobuf.frees = buf->next;
785 else
786 buf = XNEW (struct undo);
788 buf->kind = UNDO_MODE;
789 buf->where.r = into;
790 buf->old_contents.m = oldval;
791 adjust_reg_mode (*into, newval);
793 buf->next = undobuf.undos, undobuf.undos = buf;
796 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
798 #ifndef HAVE_cc0
799 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
801 static void
802 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
804 struct undo *buf;
805 struct insn_link * oldval = *into;
807 if (oldval == newval)
808 return;
810 if (undobuf.frees)
811 buf = undobuf.frees, undobuf.frees = buf->next;
812 else
813 buf = XNEW (struct undo);
815 buf->kind = UNDO_LINKS;
816 buf->where.l = into;
817 buf->old_contents.l = oldval;
818 *into = newval;
820 buf->next = undobuf.undos, undobuf.undos = buf;
823 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
824 #endif
826 /* Subroutine of try_combine. Determine whether the replacement patterns
827 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
828 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
829 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
830 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
831 of all the instructions can be estimated and the replacements are more
832 expensive than the original sequence. */
834 static bool
835 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
836 rtx newi2pat, rtx newotherpat)
838 int i0_cost, i1_cost, i2_cost, i3_cost;
839 int new_i2_cost, new_i3_cost;
840 int old_cost, new_cost;
842 /* Lookup the original insn_rtx_costs. */
843 i2_cost = INSN_COST (i2);
844 i3_cost = INSN_COST (i3);
846 if (i1)
848 i1_cost = INSN_COST (i1);
849 if (i0)
851 i0_cost = INSN_COST (i0);
852 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
853 ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
855 else
857 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
858 ? i1_cost + i2_cost + i3_cost : 0);
859 i0_cost = 0;
862 else
864 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
865 i1_cost = i0_cost = 0;
868 /* Calculate the replacement insn_rtx_costs. */
869 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
870 if (newi2pat)
872 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
873 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
874 ? new_i2_cost + new_i3_cost : 0;
876 else
878 new_cost = new_i3_cost;
879 new_i2_cost = 0;
882 if (undobuf.other_insn)
884 int old_other_cost, new_other_cost;
886 old_other_cost = INSN_COST (undobuf.other_insn);
887 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
888 if (old_other_cost > 0 && new_other_cost > 0)
890 old_cost += old_other_cost;
891 new_cost += new_other_cost;
893 else
894 old_cost = 0;
897 /* Disallow this combination if both new_cost and old_cost are greater than
898 zero, and new_cost is greater than old cost. */
899 if (old_cost > 0 && new_cost > old_cost)
901 if (dump_file)
903 if (i0)
905 fprintf (dump_file,
906 "rejecting combination of insns %d, %d, %d and %d\n",
907 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
908 INSN_UID (i3));
909 fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
910 i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
912 else if (i1)
914 fprintf (dump_file,
915 "rejecting combination of insns %d, %d and %d\n",
916 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
917 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
918 i1_cost, i2_cost, i3_cost, old_cost);
920 else
922 fprintf (dump_file,
923 "rejecting combination of insns %d and %d\n",
924 INSN_UID (i2), INSN_UID (i3));
925 fprintf (dump_file, "original costs %d + %d = %d\n",
926 i2_cost, i3_cost, old_cost);
929 if (newi2pat)
931 fprintf (dump_file, "replacement costs %d + %d = %d\n",
932 new_i2_cost, new_i3_cost, new_cost);
934 else
935 fprintf (dump_file, "replacement cost %d\n", new_cost);
938 return false;
941 /* Update the uid_insn_cost array with the replacement costs. */
942 INSN_COST (i2) = new_i2_cost;
943 INSN_COST (i3) = new_i3_cost;
944 if (i1)
946 INSN_COST (i1) = 0;
947 if (i0)
948 INSN_COST (i0) = 0;
951 return true;
955 /* Delete any insns that copy a register to itself. */
957 static void
958 delete_noop_moves (void)
960 rtx insn, next;
961 basic_block bb;
963 FOR_EACH_BB_FN (bb, cfun)
965 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
967 next = NEXT_INSN (insn);
968 if (INSN_P (insn) && noop_move_p (insn))
970 if (dump_file)
971 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
973 delete_insn_and_edges (insn);
980 /* Fill in log links field for all insns. */
982 static void
983 create_log_links (void)
985 basic_block bb;
986 rtx *next_use, insn;
987 df_ref *def_vec, *use_vec;
989 next_use = XCNEWVEC (rtx, max_reg_num ());
991 /* Pass through each block from the end, recording the uses of each
992 register and establishing log links when def is encountered.
993 Note that we do not clear next_use array in order to save time,
994 so we have to test whether the use is in the same basic block as def.
996 There are a few cases below when we do not consider the definition or
997 usage -- these are taken from original flow.c did. Don't ask me why it is
998 done this way; I don't know and if it works, I don't want to know. */
1000 FOR_EACH_BB_FN (bb, cfun)
1002 FOR_BB_INSNS_REVERSE (bb, insn)
1004 if (!NONDEBUG_INSN_P (insn))
1005 continue;
1007 /* Log links are created only once. */
1008 gcc_assert (!LOG_LINKS (insn));
1010 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
1012 df_ref def = *def_vec;
1013 int regno = DF_REF_REGNO (def);
1014 rtx use_insn;
1016 if (!next_use[regno])
1017 continue;
1019 /* Do not consider if it is pre/post modification in MEM. */
1020 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
1021 continue;
1023 /* Do not make the log link for frame pointer. */
1024 if ((regno == FRAME_POINTER_REGNUM
1025 && (! reload_completed || frame_pointer_needed))
1026 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1027 || (regno == HARD_FRAME_POINTER_REGNUM
1028 && (! reload_completed || frame_pointer_needed))
1029 #endif
1030 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1031 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
1032 #endif
1034 continue;
1036 use_insn = next_use[regno];
1037 if (BLOCK_FOR_INSN (use_insn) == bb)
1039 /* flow.c claimed:
1041 We don't build a LOG_LINK for hard registers contained
1042 in ASM_OPERANDs. If these registers get replaced,
1043 we might wind up changing the semantics of the insn,
1044 even if reload can make what appear to be valid
1045 assignments later. */
1046 if (regno >= FIRST_PSEUDO_REGISTER
1047 || asm_noperands (PATTERN (use_insn)) < 0)
1049 /* Don't add duplicate links between instructions. */
1050 struct insn_link *links;
1051 FOR_EACH_LOG_LINK (links, use_insn)
1052 if (insn == links->insn)
1053 break;
1055 if (!links)
1056 LOG_LINKS (use_insn)
1057 = alloc_insn_link (insn, LOG_LINKS (use_insn));
1060 next_use[regno] = NULL_RTX;
1063 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1065 df_ref use = *use_vec;
1066 int regno = DF_REF_REGNO (use);
1068 /* Do not consider the usage of the stack pointer
1069 by function call. */
1070 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1071 continue;
1073 next_use[regno] = insn;
1078 free (next_use);
1081 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1082 true if we found a LOG_LINK that proves that A feeds B. This only works
1083 if there are no instructions between A and B which could have a link
1084 depending on A, since in that case we would not record a link for B.
1085 We also check the implicit dependency created by a cc0 setter/user
1086 pair. */
1088 static bool
1089 insn_a_feeds_b (rtx a, rtx b)
1091 struct insn_link *links;
1092 FOR_EACH_LOG_LINK (links, b)
1093 if (links->insn == a)
1094 return true;
1095 #ifdef HAVE_cc0
1096 if (sets_cc0_p (a))
1097 return true;
1098 #endif
1099 return false;
1102 /* Main entry point for combiner. F is the first insn of the function.
1103 NREGS is the first unused pseudo-reg number.
1105 Return nonzero if the combiner has turned an indirect jump
1106 instruction into a direct jump. */
1107 static int
1108 combine_instructions (rtx f, unsigned int nregs)
1110 rtx insn, next;
1111 #ifdef HAVE_cc0
1112 rtx prev;
1113 #endif
1114 struct insn_link *links, *nextlinks;
1115 rtx first;
1116 basic_block last_bb;
1118 int new_direct_jump_p = 0;
1120 for (first = f; first && !INSN_P (first); )
1121 first = NEXT_INSN (first);
1122 if (!first)
1123 return 0;
1125 combine_attempts = 0;
1126 combine_merges = 0;
1127 combine_extras = 0;
1128 combine_successes = 0;
1130 rtl_hooks = combine_rtl_hooks;
1132 reg_stat.safe_grow_cleared (nregs);
1134 init_recog_no_volatile ();
1136 /* Allocate array for insn info. */
1137 max_uid_known = get_max_uid ();
1138 uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1139 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1140 gcc_obstack_init (&insn_link_obstack);
1142 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1144 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1145 problems when, for example, we have j <<= 1 in a loop. */
1147 nonzero_sign_valid = 0;
1148 label_tick = label_tick_ebb_start = 1;
1150 /* Scan all SETs and see if we can deduce anything about what
1151 bits are known to be zero for some registers and how many copies
1152 of the sign bit are known to exist for those registers.
1154 Also set any known values so that we can use it while searching
1155 for what bits are known to be set. */
1157 setup_incoming_promotions (first);
1158 /* Allow the entry block and the first block to fall into the same EBB.
1159 Conceptually the incoming promotions are assigned to the entry block. */
1160 last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1162 create_log_links ();
1163 FOR_EACH_BB_FN (this_basic_block, cfun)
1165 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1166 last_call_luid = 0;
1167 mem_last_set = -1;
1169 label_tick++;
1170 if (!single_pred_p (this_basic_block)
1171 || single_pred (this_basic_block) != last_bb)
1172 label_tick_ebb_start = label_tick;
1173 last_bb = this_basic_block;
1175 FOR_BB_INSNS (this_basic_block, insn)
1176 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1178 #ifdef AUTO_INC_DEC
1179 rtx links;
1180 #endif
1182 subst_low_luid = DF_INSN_LUID (insn);
1183 subst_insn = insn;
1185 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1186 insn);
1187 record_dead_and_set_regs (insn);
1189 #ifdef AUTO_INC_DEC
1190 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1191 if (REG_NOTE_KIND (links) == REG_INC)
1192 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1193 insn);
1194 #endif
1196 /* Record the current insn_rtx_cost of this instruction. */
1197 if (NONJUMP_INSN_P (insn))
1198 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1199 optimize_this_for_speed_p);
1200 if (dump_file)
1201 fprintf (dump_file, "insn_cost %d: %d\n",
1202 INSN_UID (insn), INSN_COST (insn));
1206 nonzero_sign_valid = 1;
1208 /* Now scan all the insns in forward order. */
1209 label_tick = label_tick_ebb_start = 1;
1210 init_reg_last ();
1211 setup_incoming_promotions (first);
1212 last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1214 FOR_EACH_BB_FN (this_basic_block, cfun)
1216 rtx last_combined_insn = NULL_RTX;
1217 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1218 last_call_luid = 0;
1219 mem_last_set = -1;
1221 label_tick++;
1222 if (!single_pred_p (this_basic_block)
1223 || single_pred (this_basic_block) != last_bb)
1224 label_tick_ebb_start = label_tick;
1225 last_bb = this_basic_block;
1227 rtl_profile_for_bb (this_basic_block);
1228 for (insn = BB_HEAD (this_basic_block);
1229 insn != NEXT_INSN (BB_END (this_basic_block));
1230 insn = next ? next : NEXT_INSN (insn))
1232 next = 0;
1233 if (NONDEBUG_INSN_P (insn))
1235 while (last_combined_insn
1236 && INSN_DELETED_P (last_combined_insn))
1237 last_combined_insn = PREV_INSN (last_combined_insn);
1238 if (last_combined_insn == NULL_RTX
1239 || BARRIER_P (last_combined_insn)
1240 || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1241 || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1242 last_combined_insn = insn;
1244 /* See if we know about function return values before this
1245 insn based upon SUBREG flags. */
1246 check_promoted_subreg (insn, PATTERN (insn));
1248 /* See if we can find hardregs and subreg of pseudos in
1249 narrower modes. This could help turning TRUNCATEs
1250 into SUBREGs. */
1251 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1253 /* Try this insn with each insn it links back to. */
1255 FOR_EACH_LOG_LINK (links, insn)
1256 if ((next = try_combine (insn, links->insn, NULL_RTX,
1257 NULL_RTX, &new_direct_jump_p,
1258 last_combined_insn)) != 0)
1259 goto retry;
1261 /* Try each sequence of three linked insns ending with this one. */
1263 FOR_EACH_LOG_LINK (links, insn)
1265 rtx link = links->insn;
1267 /* If the linked insn has been replaced by a note, then there
1268 is no point in pursuing this chain any further. */
1269 if (NOTE_P (link))
1270 continue;
1272 FOR_EACH_LOG_LINK (nextlinks, link)
1273 if ((next = try_combine (insn, link, nextlinks->insn,
1274 NULL_RTX, &new_direct_jump_p,
1275 last_combined_insn)) != 0)
1276 goto retry;
1279 #ifdef HAVE_cc0
1280 /* Try to combine a jump insn that uses CC0
1281 with a preceding insn that sets CC0, and maybe with its
1282 logical predecessor as well.
1283 This is how we make decrement-and-branch insns.
1284 We need this special code because data flow connections
1285 via CC0 do not get entered in LOG_LINKS. */
1287 if (JUMP_P (insn)
1288 && (prev = prev_nonnote_insn (insn)) != 0
1289 && NONJUMP_INSN_P (prev)
1290 && sets_cc0_p (PATTERN (prev)))
1292 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1293 &new_direct_jump_p,
1294 last_combined_insn)) != 0)
1295 goto retry;
1297 FOR_EACH_LOG_LINK (nextlinks, prev)
1298 if ((next = try_combine (insn, prev, nextlinks->insn,
1299 NULL_RTX, &new_direct_jump_p,
1300 last_combined_insn)) != 0)
1301 goto retry;
1304 /* Do the same for an insn that explicitly references CC0. */
1305 if (NONJUMP_INSN_P (insn)
1306 && (prev = prev_nonnote_insn (insn)) != 0
1307 && NONJUMP_INSN_P (prev)
1308 && sets_cc0_p (PATTERN (prev))
1309 && GET_CODE (PATTERN (insn)) == SET
1310 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1312 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1313 &new_direct_jump_p,
1314 last_combined_insn)) != 0)
1315 goto retry;
1317 FOR_EACH_LOG_LINK (nextlinks, prev)
1318 if ((next = try_combine (insn, prev, nextlinks->insn,
1319 NULL_RTX, &new_direct_jump_p,
1320 last_combined_insn)) != 0)
1321 goto retry;
1324 /* Finally, see if any of the insns that this insn links to
1325 explicitly references CC0. If so, try this insn, that insn,
1326 and its predecessor if it sets CC0. */
1327 FOR_EACH_LOG_LINK (links, insn)
1328 if (NONJUMP_INSN_P (links->insn)
1329 && GET_CODE (PATTERN (links->insn)) == SET
1330 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1331 && (prev = prev_nonnote_insn (links->insn)) != 0
1332 && NONJUMP_INSN_P (prev)
1333 && sets_cc0_p (PATTERN (prev))
1334 && (next = try_combine (insn, links->insn,
1335 prev, NULL_RTX, &new_direct_jump_p,
1336 last_combined_insn)) != 0)
1337 goto retry;
1338 #endif
1340 /* Try combining an insn with two different insns whose results it
1341 uses. */
1342 FOR_EACH_LOG_LINK (links, insn)
1343 for (nextlinks = links->next; nextlinks;
1344 nextlinks = nextlinks->next)
1345 if ((next = try_combine (insn, links->insn,
1346 nextlinks->insn, NULL_RTX,
1347 &new_direct_jump_p,
1348 last_combined_insn)) != 0)
1349 goto retry;
1351 /* Try four-instruction combinations. */
1352 FOR_EACH_LOG_LINK (links, insn)
1354 struct insn_link *next1;
1355 rtx link = links->insn;
1357 /* If the linked insn has been replaced by a note, then there
1358 is no point in pursuing this chain any further. */
1359 if (NOTE_P (link))
1360 continue;
1362 FOR_EACH_LOG_LINK (next1, link)
1364 rtx link1 = next1->insn;
1365 if (NOTE_P (link1))
1366 continue;
1367 /* I0 -> I1 -> I2 -> I3. */
1368 FOR_EACH_LOG_LINK (nextlinks, link1)
1369 if ((next = try_combine (insn, link, link1,
1370 nextlinks->insn,
1371 &new_direct_jump_p,
1372 last_combined_insn)) != 0)
1373 goto retry;
1374 /* I0, I1 -> I2, I2 -> I3. */
1375 for (nextlinks = next1->next; nextlinks;
1376 nextlinks = nextlinks->next)
1377 if ((next = try_combine (insn, link, link1,
1378 nextlinks->insn,
1379 &new_direct_jump_p,
1380 last_combined_insn)) != 0)
1381 goto retry;
1384 for (next1 = links->next; next1; next1 = next1->next)
1386 rtx link1 = next1->insn;
1387 if (NOTE_P (link1))
1388 continue;
1389 /* I0 -> I2; I1, I2 -> I3. */
1390 FOR_EACH_LOG_LINK (nextlinks, link)
1391 if ((next = try_combine (insn, link, link1,
1392 nextlinks->insn,
1393 &new_direct_jump_p,
1394 last_combined_insn)) != 0)
1395 goto retry;
1396 /* I0 -> I1; I1, I2 -> I3. */
1397 FOR_EACH_LOG_LINK (nextlinks, link1)
1398 if ((next = try_combine (insn, link, link1,
1399 nextlinks->insn,
1400 &new_direct_jump_p,
1401 last_combined_insn)) != 0)
1402 goto retry;
1406 /* Try this insn with each REG_EQUAL note it links back to. */
1407 FOR_EACH_LOG_LINK (links, insn)
1409 rtx set, note;
1410 rtx temp = links->insn;
1411 if ((set = single_set (temp)) != 0
1412 && (note = find_reg_equal_equiv_note (temp)) != 0
1413 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1414 /* Avoid using a register that may already been marked
1415 dead by an earlier instruction. */
1416 && ! unmentioned_reg_p (note, SET_SRC (set))
1417 && (GET_MODE (note) == VOIDmode
1418 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1419 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1421 /* Temporarily replace the set's source with the
1422 contents of the REG_EQUAL note. The insn will
1423 be deleted or recognized by try_combine. */
1424 rtx orig = SET_SRC (set);
1425 SET_SRC (set) = note;
1426 i2mod = temp;
1427 i2mod_old_rhs = copy_rtx (orig);
1428 i2mod_new_rhs = copy_rtx (note);
1429 next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1430 &new_direct_jump_p,
1431 last_combined_insn);
1432 i2mod = NULL_RTX;
1433 if (next)
1434 goto retry;
1435 SET_SRC (set) = orig;
1439 if (!NOTE_P (insn))
1440 record_dead_and_set_regs (insn);
1442 retry:
1448 default_rtl_profile ();
1449 clear_bb_flags ();
1450 new_direct_jump_p |= purge_all_dead_edges ();
1451 delete_noop_moves ();
1453 /* Clean up. */
1454 obstack_free (&insn_link_obstack, NULL);
1455 free (uid_log_links);
1456 free (uid_insn_cost);
1457 reg_stat.release ();
1460 struct undo *undo, *next;
1461 for (undo = undobuf.frees; undo; undo = next)
1463 next = undo->next;
1464 free (undo);
1466 undobuf.frees = 0;
1469 total_attempts += combine_attempts;
1470 total_merges += combine_merges;
1471 total_extras += combine_extras;
1472 total_successes += combine_successes;
1474 nonzero_sign_valid = 0;
1475 rtl_hooks = general_rtl_hooks;
1477 /* Make recognizer allow volatile MEMs again. */
1478 init_recog ();
1480 return new_direct_jump_p;
1483 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1485 static void
1486 init_reg_last (void)
1488 unsigned int i;
1489 reg_stat_type *p;
1491 FOR_EACH_VEC_ELT (reg_stat, i, p)
1492 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1495 /* Set up any promoted values for incoming argument registers. */
1497 static void
1498 setup_incoming_promotions (rtx first)
1500 tree arg;
1501 bool strictly_local = false;
1503 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1504 arg = DECL_CHAIN (arg))
1506 rtx x, reg = DECL_INCOMING_RTL (arg);
1507 int uns1, uns3;
1508 enum machine_mode mode1, mode2, mode3, mode4;
1510 /* Only continue if the incoming argument is in a register. */
1511 if (!REG_P (reg))
1512 continue;
1514 /* Determine, if possible, whether all call sites of the current
1515 function lie within the current compilation unit. (This does
1516 take into account the exporting of a function via taking its
1517 address, and so forth.) */
1518 strictly_local = cgraph_local_info (current_function_decl)->local;
1520 /* The mode and signedness of the argument before any promotions happen
1521 (equal to the mode of the pseudo holding it at that stage). */
1522 mode1 = TYPE_MODE (TREE_TYPE (arg));
1523 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1525 /* The mode and signedness of the argument after any source language and
1526 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1527 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1528 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1530 /* The mode and signedness of the argument as it is actually passed,
1531 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1532 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1533 TREE_TYPE (cfun->decl), 0);
1535 /* The mode of the register in which the argument is being passed. */
1536 mode4 = GET_MODE (reg);
1538 /* Eliminate sign extensions in the callee when:
1539 (a) A mode promotion has occurred; */
1540 if (mode1 == mode3)
1541 continue;
1542 /* (b) The mode of the register is the same as the mode of
1543 the argument as it is passed; */
1544 if (mode3 != mode4)
1545 continue;
1546 /* (c) There's no language level extension; */
1547 if (mode1 == mode2)
1549 /* (c.1) All callers are from the current compilation unit. If that's
1550 the case we don't have to rely on an ABI, we only have to know
1551 what we're generating right now, and we know that we will do the
1552 mode1 to mode2 promotion with the given sign. */
1553 else if (!strictly_local)
1554 continue;
1555 /* (c.2) The combination of the two promotions is useful. This is
1556 true when the signs match, or if the first promotion is unsigned.
1557 In the later case, (sign_extend (zero_extend x)) is the same as
1558 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1559 else if (uns1)
1560 uns3 = true;
1561 else if (uns3)
1562 continue;
1564 /* Record that the value was promoted from mode1 to mode3,
1565 so that any sign extension at the head of the current
1566 function may be eliminated. */
1567 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1568 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1569 record_value_for_reg (reg, first, x);
1573 /* Called via note_stores. If X is a pseudo that is narrower than
1574 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1576 If we are setting only a portion of X and we can't figure out what
1577 portion, assume all bits will be used since we don't know what will
1578 be happening.
1580 Similarly, set how many bits of X are known to be copies of the sign bit
1581 at all locations in the function. This is the smallest number implied
1582 by any set of X. */
1584 static void
1585 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1587 rtx insn = (rtx) data;
1588 unsigned int num;
1590 if (REG_P (x)
1591 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1592 /* If this register is undefined at the start of the file, we can't
1593 say what its contents were. */
1594 && ! REGNO_REG_SET_P
1595 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), REGNO (x))
1596 && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
1598 reg_stat_type *rsp = &reg_stat[REGNO (x)];
1600 if (set == 0 || GET_CODE (set) == CLOBBER)
1602 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1603 rsp->sign_bit_copies = 1;
1604 return;
1607 /* If this register is being initialized using itself, and the
1608 register is uninitialized in this basic block, and there are
1609 no LOG_LINKS which set the register, then part of the
1610 register is uninitialized. In that case we can't assume
1611 anything about the number of nonzero bits.
1613 ??? We could do better if we checked this in
1614 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1615 could avoid making assumptions about the insn which initially
1616 sets the register, while still using the information in other
1617 insns. We would have to be careful to check every insn
1618 involved in the combination. */
1620 if (insn
1621 && reg_referenced_p (x, PATTERN (insn))
1622 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1623 REGNO (x)))
1625 struct insn_link *link;
1627 FOR_EACH_LOG_LINK (link, insn)
1628 if (dead_or_set_p (link->insn, x))
1629 break;
1630 if (!link)
1632 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1633 rsp->sign_bit_copies = 1;
1634 return;
1638 /* If this is a complex assignment, see if we can convert it into a
1639 simple assignment. */
1640 set = expand_field_assignment (set);
1642 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1643 set what we know about X. */
1645 if (SET_DEST (set) == x
1646 || (paradoxical_subreg_p (SET_DEST (set))
1647 && SUBREG_REG (SET_DEST (set)) == x))
1649 rtx src = SET_SRC (set);
1651 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1652 /* If X is narrower than a word and SRC is a non-negative
1653 constant that would appear negative in the mode of X,
1654 sign-extend it for use in reg_stat[].nonzero_bits because some
1655 machines (maybe most) will actually do the sign-extension
1656 and this is the conservative approach.
1658 ??? For 2.5, try to tighten up the MD files in this regard
1659 instead of this kludge. */
1661 if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD
1662 && CONST_INT_P (src)
1663 && INTVAL (src) > 0
1664 && val_signbit_known_set_p (GET_MODE (x), INTVAL (src)))
1665 src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (GET_MODE (x)));
1666 #endif
1668 /* Don't call nonzero_bits if it cannot change anything. */
1669 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1670 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1671 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1672 if (rsp->sign_bit_copies == 0
1673 || rsp->sign_bit_copies > num)
1674 rsp->sign_bit_copies = num;
1676 else
1678 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1679 rsp->sign_bit_copies = 1;
1684 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1685 optionally insns that were previously combined into I3 or that will be
1686 combined into the merger of INSN and I3. The order is PRED, PRED2,
1687 INSN, SUCC, SUCC2, I3.
1689 Return 0 if the combination is not allowed for any reason.
1691 If the combination is allowed, *PDEST will be set to the single
1692 destination of INSN and *PSRC to the single source, and this function
1693 will return 1. */
1695 static int
1696 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1697 rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1698 rtx *pdest, rtx *psrc)
1700 int i;
1701 const_rtx set = 0;
1702 rtx src, dest;
1703 rtx p;
1704 #ifdef AUTO_INC_DEC
1705 rtx link;
1706 #endif
1707 bool all_adjacent = true;
1708 int (*is_volatile_p) (const_rtx);
1710 if (succ)
1712 if (succ2)
1714 if (next_active_insn (succ2) != i3)
1715 all_adjacent = false;
1716 if (next_active_insn (succ) != succ2)
1717 all_adjacent = false;
1719 else if (next_active_insn (succ) != i3)
1720 all_adjacent = false;
1721 if (next_active_insn (insn) != succ)
1722 all_adjacent = false;
1724 else if (next_active_insn (insn) != i3)
1725 all_adjacent = false;
1727 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1728 or a PARALLEL consisting of such a SET and CLOBBERs.
1730 If INSN has CLOBBER parallel parts, ignore them for our processing.
1731 By definition, these happen during the execution of the insn. When it
1732 is merged with another insn, all bets are off. If they are, in fact,
1733 needed and aren't also supplied in I3, they may be added by
1734 recog_for_combine. Otherwise, it won't match.
1736 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1737 note.
1739 Get the source and destination of INSN. If more than one, can't
1740 combine. */
1742 if (GET_CODE (PATTERN (insn)) == SET)
1743 set = PATTERN (insn);
1744 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1745 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1747 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1749 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1751 switch (GET_CODE (elt))
1753 /* This is important to combine floating point insns
1754 for the SH4 port. */
1755 case USE:
1756 /* Combining an isolated USE doesn't make sense.
1757 We depend here on combinable_i3pat to reject them. */
1758 /* The code below this loop only verifies that the inputs of
1759 the SET in INSN do not change. We call reg_set_between_p
1760 to verify that the REG in the USE does not change between
1761 I3 and INSN.
1762 If the USE in INSN was for a pseudo register, the matching
1763 insn pattern will likely match any register; combining this
1764 with any other USE would only be safe if we knew that the
1765 used registers have identical values, or if there was
1766 something to tell them apart, e.g. different modes. For
1767 now, we forgo such complicated tests and simply disallow
1768 combining of USES of pseudo registers with any other USE. */
1769 if (REG_P (XEXP (elt, 0))
1770 && GET_CODE (PATTERN (i3)) == PARALLEL)
1772 rtx i3pat = PATTERN (i3);
1773 int i = XVECLEN (i3pat, 0) - 1;
1774 unsigned int regno = REGNO (XEXP (elt, 0));
1778 rtx i3elt = XVECEXP (i3pat, 0, i);
1780 if (GET_CODE (i3elt) == USE
1781 && REG_P (XEXP (i3elt, 0))
1782 && (REGNO (XEXP (i3elt, 0)) == regno
1783 ? reg_set_between_p (XEXP (elt, 0),
1784 PREV_INSN (insn), i3)
1785 : regno >= FIRST_PSEUDO_REGISTER))
1786 return 0;
1788 while (--i >= 0);
1790 break;
1792 /* We can ignore CLOBBERs. */
1793 case CLOBBER:
1794 break;
1796 case SET:
1797 /* Ignore SETs whose result isn't used but not those that
1798 have side-effects. */
1799 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1800 && insn_nothrow_p (insn)
1801 && !side_effects_p (elt))
1802 break;
1804 /* If we have already found a SET, this is a second one and
1805 so we cannot combine with this insn. */
1806 if (set)
1807 return 0;
1809 set = elt;
1810 break;
1812 default:
1813 /* Anything else means we can't combine. */
1814 return 0;
1818 if (set == 0
1819 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1820 so don't do anything with it. */
1821 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1822 return 0;
1824 else
1825 return 0;
1827 if (set == 0)
1828 return 0;
1830 /* The simplification in expand_field_assignment may call back to
1831 get_last_value, so set safe guard here. */
1832 subst_low_luid = DF_INSN_LUID (insn);
1834 set = expand_field_assignment (set);
1835 src = SET_SRC (set), dest = SET_DEST (set);
1837 /* Don't eliminate a store in the stack pointer. */
1838 if (dest == stack_pointer_rtx
1839 /* Don't combine with an insn that sets a register to itself if it has
1840 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1841 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1842 /* Can't merge an ASM_OPERANDS. */
1843 || GET_CODE (src) == ASM_OPERANDS
1844 /* Can't merge a function call. */
1845 || GET_CODE (src) == CALL
1846 /* Don't eliminate a function call argument. */
1847 || (CALL_P (i3)
1848 && (find_reg_fusage (i3, USE, dest)
1849 || (REG_P (dest)
1850 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1851 && global_regs[REGNO (dest)])))
1852 /* Don't substitute into an incremented register. */
1853 || FIND_REG_INC_NOTE (i3, dest)
1854 || (succ && FIND_REG_INC_NOTE (succ, dest))
1855 || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1856 /* Don't substitute into a non-local goto, this confuses CFG. */
1857 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1858 /* Make sure that DEST is not used after SUCC but before I3. */
1859 || (!all_adjacent
1860 && ((succ2
1861 && (reg_used_between_p (dest, succ2, i3)
1862 || reg_used_between_p (dest, succ, succ2)))
1863 || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1864 /* Make sure that the value that is to be substituted for the register
1865 does not use any registers whose values alter in between. However,
1866 If the insns are adjacent, a use can't cross a set even though we
1867 think it might (this can happen for a sequence of insns each setting
1868 the same destination; last_set of that register might point to
1869 a NOTE). If INSN has a REG_EQUIV note, the register is always
1870 equivalent to the memory so the substitution is valid even if there
1871 are intervening stores. Also, don't move a volatile asm or
1872 UNSPEC_VOLATILE across any other insns. */
1873 || (! all_adjacent
1874 && (((!MEM_P (src)
1875 || ! find_reg_note (insn, REG_EQUIV, src))
1876 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1877 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1878 || GET_CODE (src) == UNSPEC_VOLATILE))
1879 /* Don't combine across a CALL_INSN, because that would possibly
1880 change whether the life span of some REGs crosses calls or not,
1881 and it is a pain to update that information.
1882 Exception: if source is a constant, moving it later can't hurt.
1883 Accept that as a special case. */
1884 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1885 return 0;
1887 /* DEST must either be a REG or CC0. */
1888 if (REG_P (dest))
1890 /* If register alignment is being enforced for multi-word items in all
1891 cases except for parameters, it is possible to have a register copy
1892 insn referencing a hard register that is not allowed to contain the
1893 mode being copied and which would not be valid as an operand of most
1894 insns. Eliminate this problem by not combining with such an insn.
1896 Also, on some machines we don't want to extend the life of a hard
1897 register. */
1899 if (REG_P (src)
1900 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1901 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1902 /* Don't extend the life of a hard register unless it is
1903 user variable (if we have few registers) or it can't
1904 fit into the desired register (meaning something special
1905 is going on).
1906 Also avoid substituting a return register into I3, because
1907 reload can't handle a conflict with constraints of other
1908 inputs. */
1909 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1910 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1911 return 0;
1913 else if (GET_CODE (dest) != CC0)
1914 return 0;
1917 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1918 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1919 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1921 /* Don't substitute for a register intended as a clobberable
1922 operand. */
1923 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1924 if (rtx_equal_p (reg, dest))
1925 return 0;
1927 /* If the clobber represents an earlyclobber operand, we must not
1928 substitute an expression containing the clobbered register.
1929 As we do not analyze the constraint strings here, we have to
1930 make the conservative assumption. However, if the register is
1931 a fixed hard reg, the clobber cannot represent any operand;
1932 we leave it up to the machine description to either accept or
1933 reject use-and-clobber patterns. */
1934 if (!REG_P (reg)
1935 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1936 || !fixed_regs[REGNO (reg)])
1937 if (reg_overlap_mentioned_p (reg, src))
1938 return 0;
1941 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1942 or not), reject, unless nothing volatile comes between it and I3 */
1944 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1946 /* Make sure neither succ nor succ2 contains a volatile reference. */
1947 if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1948 return 0;
1949 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1950 return 0;
1951 /* We'll check insns between INSN and I3 below. */
1954 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1955 to be an explicit register variable, and was chosen for a reason. */
1957 if (GET_CODE (src) == ASM_OPERANDS
1958 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1959 return 0;
1961 /* If INSN contains volatile references (specifically volatile MEMs),
1962 we cannot combine across any other volatile references.
1963 Even if INSN doesn't contain volatile references, any intervening
1964 volatile insn might affect machine state. */
1966 is_volatile_p = volatile_refs_p (PATTERN (insn))
1967 ? volatile_refs_p
1968 : volatile_insn_p;
1970 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1971 if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
1972 return 0;
1974 /* If INSN contains an autoincrement or autodecrement, make sure that
1975 register is not used between there and I3, and not already used in
1976 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1977 Also insist that I3 not be a jump; if it were one
1978 and the incremented register were spilled, we would lose. */
1980 #ifdef AUTO_INC_DEC
1981 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1982 if (REG_NOTE_KIND (link) == REG_INC
1983 && (JUMP_P (i3)
1984 || reg_used_between_p (XEXP (link, 0), insn, i3)
1985 || (pred != NULL_RTX
1986 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1987 || (pred2 != NULL_RTX
1988 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1989 || (succ != NULL_RTX
1990 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1991 || (succ2 != NULL_RTX
1992 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1993 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1994 return 0;
1995 #endif
1997 #ifdef HAVE_cc0
1998 /* Don't combine an insn that follows a CC0-setting insn.
1999 An insn that uses CC0 must not be separated from the one that sets it.
2000 We do, however, allow I2 to follow a CC0-setting insn if that insn
2001 is passed as I1; in that case it will be deleted also.
2002 We also allow combining in this case if all the insns are adjacent
2003 because that would leave the two CC0 insns adjacent as well.
2004 It would be more logical to test whether CC0 occurs inside I1 or I2,
2005 but that would be much slower, and this ought to be equivalent. */
2007 p = prev_nonnote_insn (insn);
2008 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
2009 && ! all_adjacent)
2010 return 0;
2011 #endif
2013 /* If we get here, we have passed all the tests and the combination is
2014 to be allowed. */
2016 *pdest = dest;
2017 *psrc = src;
2019 return 1;
2022 /* LOC is the location within I3 that contains its pattern or the component
2023 of a PARALLEL of the pattern. We validate that it is valid for combining.
2025 One problem is if I3 modifies its output, as opposed to replacing it
2026 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2027 doing so would produce an insn that is not equivalent to the original insns.
2029 Consider:
2031 (set (reg:DI 101) (reg:DI 100))
2032 (set (subreg:SI (reg:DI 101) 0) <foo>)
2034 This is NOT equivalent to:
2036 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2037 (set (reg:DI 101) (reg:DI 100))])
2039 Not only does this modify 100 (in which case it might still be valid
2040 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2042 We can also run into a problem if I2 sets a register that I1
2043 uses and I1 gets directly substituted into I3 (not via I2). In that
2044 case, we would be getting the wrong value of I2DEST into I3, so we
2045 must reject the combination. This case occurs when I2 and I1 both
2046 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2047 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2048 of a SET must prevent combination from occurring. The same situation
2049 can occur for I0, in which case I0_NOT_IN_SRC is set.
2051 Before doing the above check, we first try to expand a field assignment
2052 into a set of logical operations.
2054 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2055 we place a register that is both set and used within I3. If more than one
2056 such register is detected, we fail.
2058 Return 1 if the combination is valid, zero otherwise. */
2060 static int
2061 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2062 int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2064 rtx x = *loc;
2066 if (GET_CODE (x) == SET)
2068 rtx set = x ;
2069 rtx dest = SET_DEST (set);
2070 rtx src = SET_SRC (set);
2071 rtx inner_dest = dest;
2072 rtx subdest;
2074 while (GET_CODE (inner_dest) == STRICT_LOW_PART
2075 || GET_CODE (inner_dest) == SUBREG
2076 || GET_CODE (inner_dest) == ZERO_EXTRACT)
2077 inner_dest = XEXP (inner_dest, 0);
2079 /* Check for the case where I3 modifies its output, as discussed
2080 above. We don't want to prevent pseudos from being combined
2081 into the address of a MEM, so only prevent the combination if
2082 i1 or i2 set the same MEM. */
2083 if ((inner_dest != dest &&
2084 (!MEM_P (inner_dest)
2085 || rtx_equal_p (i2dest, inner_dest)
2086 || (i1dest && rtx_equal_p (i1dest, inner_dest))
2087 || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2088 && (reg_overlap_mentioned_p (i2dest, inner_dest)
2089 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2090 || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2092 /* This is the same test done in can_combine_p except we can't test
2093 all_adjacent; we don't have to, since this instruction will stay
2094 in place, thus we are not considering increasing the lifetime of
2095 INNER_DEST.
2097 Also, if this insn sets a function argument, combining it with
2098 something that might need a spill could clobber a previous
2099 function argument; the all_adjacent test in can_combine_p also
2100 checks this; here, we do a more specific test for this case. */
2102 || (REG_P (inner_dest)
2103 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2104 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2105 GET_MODE (inner_dest))))
2106 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2107 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2108 return 0;
2110 /* If DEST is used in I3, it is being killed in this insn, so
2111 record that for later. We have to consider paradoxical
2112 subregs here, since they kill the whole register, but we
2113 ignore partial subregs, STRICT_LOW_PART, etc.
2114 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2115 STACK_POINTER_REGNUM, since these are always considered to be
2116 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2117 subdest = dest;
2118 if (GET_CODE (subdest) == SUBREG
2119 && (GET_MODE_SIZE (GET_MODE (subdest))
2120 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2121 subdest = SUBREG_REG (subdest);
2122 if (pi3dest_killed
2123 && REG_P (subdest)
2124 && reg_referenced_p (subdest, PATTERN (i3))
2125 && REGNO (subdest) != FRAME_POINTER_REGNUM
2126 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2127 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2128 #endif
2129 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2130 && (REGNO (subdest) != ARG_POINTER_REGNUM
2131 || ! fixed_regs [REGNO (subdest)])
2132 #endif
2133 && REGNO (subdest) != STACK_POINTER_REGNUM)
2135 if (*pi3dest_killed)
2136 return 0;
2138 *pi3dest_killed = subdest;
2142 else if (GET_CODE (x) == PARALLEL)
2144 int i;
2146 for (i = 0; i < XVECLEN (x, 0); i++)
2147 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2148 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2149 return 0;
2152 return 1;
2155 /* Return 1 if X is an arithmetic expression that contains a multiplication
2156 and division. We don't count multiplications by powers of two here. */
2158 static int
2159 contains_muldiv (rtx x)
2161 switch (GET_CODE (x))
2163 case MOD: case DIV: case UMOD: case UDIV:
2164 return 1;
2166 case MULT:
2167 return ! (CONST_INT_P (XEXP (x, 1))
2168 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2169 default:
2170 if (BINARY_P (x))
2171 return contains_muldiv (XEXP (x, 0))
2172 || contains_muldiv (XEXP (x, 1));
2174 if (UNARY_P (x))
2175 return contains_muldiv (XEXP (x, 0));
2177 return 0;
2181 /* Determine whether INSN can be used in a combination. Return nonzero if
2182 not. This is used in try_combine to detect early some cases where we
2183 can't perform combinations. */
2185 static int
2186 cant_combine_insn_p (rtx insn)
2188 rtx set;
2189 rtx src, dest;
2191 /* If this isn't really an insn, we can't do anything.
2192 This can occur when flow deletes an insn that it has merged into an
2193 auto-increment address. */
2194 if (! INSN_P (insn))
2195 return 1;
2197 /* Never combine loads and stores involving hard regs that are likely
2198 to be spilled. The register allocator can usually handle such
2199 reg-reg moves by tying. If we allow the combiner to make
2200 substitutions of likely-spilled regs, reload might die.
2201 As an exception, we allow combinations involving fixed regs; these are
2202 not available to the register allocator so there's no risk involved. */
2204 set = single_set (insn);
2205 if (! set)
2206 return 0;
2207 src = SET_SRC (set);
2208 dest = SET_DEST (set);
2209 if (GET_CODE (src) == SUBREG)
2210 src = SUBREG_REG (src);
2211 if (GET_CODE (dest) == SUBREG)
2212 dest = SUBREG_REG (dest);
2213 if (REG_P (src) && REG_P (dest)
2214 && ((HARD_REGISTER_P (src)
2215 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2216 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2217 || (HARD_REGISTER_P (dest)
2218 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2219 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2220 return 1;
2222 return 0;
2225 struct likely_spilled_retval_info
2227 unsigned regno, nregs;
2228 unsigned mask;
2231 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2232 hard registers that are known to be written to / clobbered in full. */
2233 static void
2234 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2236 struct likely_spilled_retval_info *const info =
2237 (struct likely_spilled_retval_info *) data;
2238 unsigned regno, nregs;
2239 unsigned new_mask;
2241 if (!REG_P (XEXP (set, 0)))
2242 return;
2243 regno = REGNO (x);
2244 if (regno >= info->regno + info->nregs)
2245 return;
2246 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2247 if (regno + nregs <= info->regno)
2248 return;
2249 new_mask = (2U << (nregs - 1)) - 1;
2250 if (regno < info->regno)
2251 new_mask >>= info->regno - regno;
2252 else
2253 new_mask <<= regno - info->regno;
2254 info->mask &= ~new_mask;
2257 /* Return nonzero iff part of the return value is live during INSN, and
2258 it is likely spilled. This can happen when more than one insn is needed
2259 to copy the return value, e.g. when we consider to combine into the
2260 second copy insn for a complex value. */
2262 static int
2263 likely_spilled_retval_p (rtx insn)
2265 rtx use = BB_END (this_basic_block);
2266 rtx reg, p;
2267 unsigned regno, nregs;
2268 /* We assume here that no machine mode needs more than
2269 32 hard registers when the value overlaps with a register
2270 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2271 unsigned mask;
2272 struct likely_spilled_retval_info info;
2274 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2275 return 0;
2276 reg = XEXP (PATTERN (use), 0);
2277 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2278 return 0;
2279 regno = REGNO (reg);
2280 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2281 if (nregs == 1)
2282 return 0;
2283 mask = (2U << (nregs - 1)) - 1;
2285 /* Disregard parts of the return value that are set later. */
2286 info.regno = regno;
2287 info.nregs = nregs;
2288 info.mask = mask;
2289 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2290 if (INSN_P (p))
2291 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2292 mask = info.mask;
2294 /* Check if any of the (probably) live return value registers is
2295 likely spilled. */
2296 nregs --;
2299 if ((mask & 1 << nregs)
2300 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2301 return 1;
2302 } while (nregs--);
2303 return 0;
2306 /* Adjust INSN after we made a change to its destination.
2308 Changing the destination can invalidate notes that say something about
2309 the results of the insn and a LOG_LINK pointing to the insn. */
2311 static void
2312 adjust_for_new_dest (rtx insn)
2314 /* For notes, be conservative and simply remove them. */
2315 remove_reg_equal_equiv_notes (insn);
2317 /* The new insn will have a destination that was previously the destination
2318 of an insn just above it. Call distribute_links to make a LOG_LINK from
2319 the next use of that destination. */
2320 distribute_links (alloc_insn_link (insn, NULL));
2322 df_insn_rescan (insn);
2325 /* Return TRUE if combine can reuse reg X in mode MODE.
2326 ADDED_SETS is nonzero if the original set is still required. */
2327 static bool
2328 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2330 unsigned int regno;
2332 if (!REG_P (x))
2333 return false;
2335 regno = REGNO (x);
2336 /* Allow hard registers if the new mode is legal, and occupies no more
2337 registers than the old mode. */
2338 if (regno < FIRST_PSEUDO_REGISTER)
2339 return (HARD_REGNO_MODE_OK (regno, mode)
2340 && (hard_regno_nregs[regno][GET_MODE (x)]
2341 >= hard_regno_nregs[regno][mode]));
2343 /* Or a pseudo that is only used once. */
2344 return (REG_N_SETS (regno) == 1 && !added_sets
2345 && !REG_USERVAR_P (x));
2349 /* Check whether X, the destination of a set, refers to part of
2350 the register specified by REG. */
2352 static bool
2353 reg_subword_p (rtx x, rtx reg)
2355 /* Check that reg is an integer mode register. */
2356 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2357 return false;
2359 if (GET_CODE (x) == STRICT_LOW_PART
2360 || GET_CODE (x) == ZERO_EXTRACT)
2361 x = XEXP (x, 0);
2363 return GET_CODE (x) == SUBREG
2364 && SUBREG_REG (x) == reg
2365 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2368 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2369 Note that the INSN should be deleted *after* removing dead edges, so
2370 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2371 but not for a (set (pc) (label_ref FOO)). */
2373 static void
2374 update_cfg_for_uncondjump (rtx insn)
2376 basic_block bb = BLOCK_FOR_INSN (insn);
2377 gcc_assert (BB_END (bb) == insn);
2379 purge_dead_edges (bb);
2381 delete_insn (insn);
2382 if (EDGE_COUNT (bb->succs) == 1)
2384 rtx insn;
2386 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2388 /* Remove barriers from the footer if there are any. */
2389 for (insn = BB_FOOTER (bb); insn; insn = NEXT_INSN (insn))
2390 if (BARRIER_P (insn))
2392 if (PREV_INSN (insn))
2393 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2394 else
2395 BB_FOOTER (bb) = NEXT_INSN (insn);
2396 if (NEXT_INSN (insn))
2397 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2399 else if (LABEL_P (insn))
2400 break;
2404 /* Try to combine the insns I0, I1 and I2 into I3.
2405 Here I0, I1 and I2 appear earlier than I3.
2406 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2409 If we are combining more than two insns and the resulting insn is not
2410 recognized, try splitting it into two insns. If that happens, I2 and I3
2411 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2412 Otherwise, I0, I1 and I2 are pseudo-deleted.
2414 Return 0 if the combination does not work. Then nothing is changed.
2415 If we did the combination, return the insn at which combine should
2416 resume scanning.
2418 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2419 new direct jump instruction.
2421 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2422 been I3 passed to an earlier try_combine within the same basic
2423 block. */
2425 static rtx
2426 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p,
2427 rtx last_combined_insn)
2429 /* New patterns for I3 and I2, respectively. */
2430 rtx newpat, newi2pat = 0;
2431 rtvec newpat_vec_with_clobbers = 0;
2432 int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2433 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2434 dead. */
2435 int added_sets_0, added_sets_1, added_sets_2;
2436 /* Total number of SETs to put into I3. */
2437 int total_sets;
2438 /* Nonzero if I2's or I1's body now appears in I3. */
2439 int i2_is_used = 0, i1_is_used = 0;
2440 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2441 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2442 /* Contains I3 if the destination of I3 is used in its source, which means
2443 that the old life of I3 is being killed. If that usage is placed into
2444 I2 and not in I3, a REG_DEAD note must be made. */
2445 rtx i3dest_killed = 0;
2446 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2447 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2448 /* Copy of SET_SRC of I1 and I0, if needed. */
2449 rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2450 /* Set if I2DEST was reused as a scratch register. */
2451 bool i2scratch = false;
2452 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2453 rtx i0pat = 0, i1pat = 0, i2pat = 0;
2454 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2455 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2456 int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2457 int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2458 int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2459 /* Notes that must be added to REG_NOTES in I3 and I2. */
2460 rtx new_i3_notes, new_i2_notes;
2461 /* Notes that we substituted I3 into I2 instead of the normal case. */
2462 int i3_subst_into_i2 = 0;
2463 /* Notes that I1, I2 or I3 is a MULT operation. */
2464 int have_mult = 0;
2465 int swap_i2i3 = 0;
2466 int changed_i3_dest = 0;
2468 int maxreg;
2469 rtx temp;
2470 struct insn_link *link;
2471 rtx other_pat = 0;
2472 rtx new_other_notes;
2473 int i;
2475 /* Only try four-insn combinations when there's high likelihood of
2476 success. Look for simple insns, such as loads of constants or
2477 binary operations involving a constant. */
2478 if (i0)
2480 int i;
2481 int ngood = 0;
2482 int nshift = 0;
2484 if (!flag_expensive_optimizations)
2485 return 0;
2487 for (i = 0; i < 4; i++)
2489 rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2490 rtx set = single_set (insn);
2491 rtx src;
2492 if (!set)
2493 continue;
2494 src = SET_SRC (set);
2495 if (CONSTANT_P (src))
2497 ngood += 2;
2498 break;
2500 else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2501 ngood++;
2502 else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2503 || GET_CODE (src) == LSHIFTRT)
2504 nshift++;
2506 if (ngood < 2 && nshift < 2)
2507 return 0;
2510 /* Exit early if one of the insns involved can't be used for
2511 combinations. */
2512 if (cant_combine_insn_p (i3)
2513 || cant_combine_insn_p (i2)
2514 || (i1 && cant_combine_insn_p (i1))
2515 || (i0 && cant_combine_insn_p (i0))
2516 || likely_spilled_retval_p (i3))
2517 return 0;
2519 combine_attempts++;
2520 undobuf.other_insn = 0;
2522 /* Reset the hard register usage information. */
2523 CLEAR_HARD_REG_SET (newpat_used_regs);
2525 if (dump_file && (dump_flags & TDF_DETAILS))
2527 if (i0)
2528 fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2529 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2530 else if (i1)
2531 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2532 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2533 else
2534 fprintf (dump_file, "\nTrying %d -> %d:\n",
2535 INSN_UID (i2), INSN_UID (i3));
2538 /* If multiple insns feed into one of I2 or I3, they can be in any
2539 order. To simplify the code below, reorder them in sequence. */
2540 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2541 temp = i2, i2 = i0, i0 = temp;
2542 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2543 temp = i1, i1 = i0, i0 = temp;
2544 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2545 temp = i1, i1 = i2, i2 = temp;
2547 added_links_insn = 0;
2549 /* First check for one important special case that the code below will
2550 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2551 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2552 we may be able to replace that destination with the destination of I3.
2553 This occurs in the common code where we compute both a quotient and
2554 remainder into a structure, in which case we want to do the computation
2555 directly into the structure to avoid register-register copies.
2557 Note that this case handles both multiple sets in I2 and also cases
2558 where I2 has a number of CLOBBERs inside the PARALLEL.
2560 We make very conservative checks below and only try to handle the
2561 most common cases of this. For example, we only handle the case
2562 where I2 and I3 are adjacent to avoid making difficult register
2563 usage tests. */
2565 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2566 && REG_P (SET_SRC (PATTERN (i3)))
2567 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2568 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2569 && GET_CODE (PATTERN (i2)) == PARALLEL
2570 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2571 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2572 below would need to check what is inside (and reg_overlap_mentioned_p
2573 doesn't support those codes anyway). Don't allow those destinations;
2574 the resulting insn isn't likely to be recognized anyway. */
2575 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2576 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2577 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2578 SET_DEST (PATTERN (i3)))
2579 && next_active_insn (i2) == i3)
2581 rtx p2 = PATTERN (i2);
2583 /* Make sure that the destination of I3,
2584 which we are going to substitute into one output of I2,
2585 is not used within another output of I2. We must avoid making this:
2586 (parallel [(set (mem (reg 69)) ...)
2587 (set (reg 69) ...)])
2588 which is not well-defined as to order of actions.
2589 (Besides, reload can't handle output reloads for this.)
2591 The problem can also happen if the dest of I3 is a memory ref,
2592 if another dest in I2 is an indirect memory ref. */
2593 for (i = 0; i < XVECLEN (p2, 0); i++)
2594 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2595 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2596 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2597 SET_DEST (XVECEXP (p2, 0, i))))
2598 break;
2600 if (i == XVECLEN (p2, 0))
2601 for (i = 0; i < XVECLEN (p2, 0); i++)
2602 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2603 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2605 combine_merges++;
2607 subst_insn = i3;
2608 subst_low_luid = DF_INSN_LUID (i2);
2610 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2611 i2src = SET_SRC (XVECEXP (p2, 0, i));
2612 i2dest = SET_DEST (XVECEXP (p2, 0, i));
2613 i2dest_killed = dead_or_set_p (i2, i2dest);
2615 /* Replace the dest in I2 with our dest and make the resulting
2616 insn the new pattern for I3. Then skip to where we validate
2617 the pattern. Everything was set up above. */
2618 SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2619 newpat = p2;
2620 i3_subst_into_i2 = 1;
2621 goto validate_replacement;
2625 /* If I2 is setting a pseudo to a constant and I3 is setting some
2626 sub-part of it to another constant, merge them by making a new
2627 constant. */
2628 if (i1 == 0
2629 && (temp = single_set (i2)) != 0
2630 && CONST_SCALAR_INT_P (SET_SRC (temp))
2631 && GET_CODE (PATTERN (i3)) == SET
2632 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))
2633 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2635 rtx dest = SET_DEST (PATTERN (i3));
2636 int offset = -1;
2637 int width = 0;
2639 if (GET_CODE (dest) == ZERO_EXTRACT)
2641 if (CONST_INT_P (XEXP (dest, 1))
2642 && CONST_INT_P (XEXP (dest, 2)))
2644 width = INTVAL (XEXP (dest, 1));
2645 offset = INTVAL (XEXP (dest, 2));
2646 dest = XEXP (dest, 0);
2647 if (BITS_BIG_ENDIAN)
2648 offset = GET_MODE_PRECISION (GET_MODE (dest)) - width - offset;
2651 else
2653 if (GET_CODE (dest) == STRICT_LOW_PART)
2654 dest = XEXP (dest, 0);
2655 width = GET_MODE_PRECISION (GET_MODE (dest));
2656 offset = 0;
2659 if (offset >= 0)
2661 /* If this is the low part, we're done. */
2662 if (subreg_lowpart_p (dest))
2664 /* Handle the case where inner is twice the size of outer. */
2665 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2666 == 2 * GET_MODE_PRECISION (GET_MODE (dest)))
2667 offset += GET_MODE_PRECISION (GET_MODE (dest));
2668 /* Otherwise give up for now. */
2669 else
2670 offset = -1;
2673 if (offset >= 0
2674 && (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2675 <= HOST_BITS_PER_DOUBLE_INT))
2677 double_int m, o, i;
2678 rtx inner = SET_SRC (PATTERN (i3));
2679 rtx outer = SET_SRC (temp);
2681 o = rtx_to_double_int (outer);
2682 i = rtx_to_double_int (inner);
2684 m = double_int::mask (width);
2685 i &= m;
2686 m = m.llshift (offset, HOST_BITS_PER_DOUBLE_INT);
2687 i = i.llshift (offset, HOST_BITS_PER_DOUBLE_INT);
2688 o = o.and_not (m) | i;
2690 combine_merges++;
2691 subst_insn = i3;
2692 subst_low_luid = DF_INSN_LUID (i2);
2693 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2694 i2dest = SET_DEST (temp);
2695 i2dest_killed = dead_or_set_p (i2, i2dest);
2697 /* Replace the source in I2 with the new constant and make the
2698 resulting insn the new pattern for I3. Then skip to where we
2699 validate the pattern. Everything was set up above. */
2700 SUBST (SET_SRC (temp),
2701 immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2703 newpat = PATTERN (i2);
2705 /* The dest of I3 has been replaced with the dest of I2. */
2706 changed_i3_dest = 1;
2707 goto validate_replacement;
2711 #ifndef HAVE_cc0
2712 /* If we have no I1 and I2 looks like:
2713 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2714 (set Y OP)])
2715 make up a dummy I1 that is
2716 (set Y OP)
2717 and change I2 to be
2718 (set (reg:CC X) (compare:CC Y (const_int 0)))
2720 (We can ignore any trailing CLOBBERs.)
2722 This undoes a previous combination and allows us to match a branch-and-
2723 decrement insn. */
2725 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2726 && XVECLEN (PATTERN (i2), 0) >= 2
2727 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2728 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2729 == MODE_CC)
2730 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2731 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2732 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2733 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2734 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2735 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2737 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2738 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2739 break;
2741 if (i == 1)
2743 /* We make I1 with the same INSN_UID as I2. This gives it
2744 the same DF_INSN_LUID for value tracking. Our fake I1 will
2745 never appear in the insn stream so giving it the same INSN_UID
2746 as I2 will not cause a problem. */
2748 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2749 BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2750 INSN_LOCATION (i2), -1, NULL_RTX);
2752 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2753 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2754 SET_DEST (PATTERN (i1)));
2755 SUBST_LINK (LOG_LINKS (i2), alloc_insn_link (i1, LOG_LINKS (i2)));
2758 #endif
2760 /* Verify that I2 and I1 are valid for combining. */
2761 if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2762 || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2763 &i1dest, &i1src))
2764 || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2765 &i0dest, &i0src)))
2767 undo_all ();
2768 return 0;
2771 /* Record whether I2DEST is used in I2SRC and similarly for the other
2772 cases. Knowing this will help in register status updating below. */
2773 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2774 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2775 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2776 i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2777 i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2778 i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2779 i2dest_killed = dead_or_set_p (i2, i2dest);
2780 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2781 i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2783 /* For the earlier insns, determine which of the subsequent ones they
2784 feed. */
2785 i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2786 i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2787 i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2788 : (!reg_overlap_mentioned_p (i1dest, i0dest)
2789 && reg_overlap_mentioned_p (i0dest, i2src))));
2791 /* Ensure that I3's pattern can be the destination of combines. */
2792 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2793 i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2794 i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2795 || (i1dest_in_i0src && !i0_feeds_i1_n)),
2796 &i3dest_killed))
2798 undo_all ();
2799 return 0;
2802 /* See if any of the insns is a MULT operation. Unless one is, we will
2803 reject a combination that is, since it must be slower. Be conservative
2804 here. */
2805 if (GET_CODE (i2src) == MULT
2806 || (i1 != 0 && GET_CODE (i1src) == MULT)
2807 || (i0 != 0 && GET_CODE (i0src) == MULT)
2808 || (GET_CODE (PATTERN (i3)) == SET
2809 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2810 have_mult = 1;
2812 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2813 We used to do this EXCEPT in one case: I3 has a post-inc in an
2814 output operand. However, that exception can give rise to insns like
2815 mov r3,(r3)+
2816 which is a famous insn on the PDP-11 where the value of r3 used as the
2817 source was model-dependent. Avoid this sort of thing. */
2819 #if 0
2820 if (!(GET_CODE (PATTERN (i3)) == SET
2821 && REG_P (SET_SRC (PATTERN (i3)))
2822 && MEM_P (SET_DEST (PATTERN (i3)))
2823 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2824 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2825 /* It's not the exception. */
2826 #endif
2827 #ifdef AUTO_INC_DEC
2829 rtx link;
2830 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2831 if (REG_NOTE_KIND (link) == REG_INC
2832 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2833 || (i1 != 0
2834 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2836 undo_all ();
2837 return 0;
2840 #endif
2842 /* See if the SETs in I1 or I2 need to be kept around in the merged
2843 instruction: whenever the value set there is still needed past I3.
2844 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2846 For the SET in I1, we have two cases: if I1 and I2 independently feed
2847 into I3, the set in I1 needs to be kept around unless I1DEST dies
2848 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2849 in I1 needs to be kept around unless I1DEST dies or is set in either
2850 I2 or I3. The same considerations apply to I0. */
2852 added_sets_2 = !dead_or_set_p (i3, i2dest);
2854 if (i1)
2855 added_sets_1 = !(dead_or_set_p (i3, i1dest)
2856 || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2857 else
2858 added_sets_1 = 0;
2860 if (i0)
2861 added_sets_0 = !(dead_or_set_p (i3, i0dest)
2862 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))
2863 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
2864 && dead_or_set_p (i2, i0dest)));
2865 else
2866 added_sets_0 = 0;
2868 /* We are about to copy insns for the case where they need to be kept
2869 around. Check that they can be copied in the merged instruction. */
2871 if (targetm.cannot_copy_insn_p
2872 && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
2873 || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
2874 || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
2876 undo_all ();
2877 return 0;
2880 /* If the set in I2 needs to be kept around, we must make a copy of
2881 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2882 PATTERN (I2), we are only substituting for the original I1DEST, not into
2883 an already-substituted copy. This also prevents making self-referential
2884 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2885 I2DEST. */
2887 if (added_sets_2)
2889 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2890 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2891 else
2892 i2pat = copy_rtx (PATTERN (i2));
2895 if (added_sets_1)
2897 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2898 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2899 else
2900 i1pat = copy_rtx (PATTERN (i1));
2903 if (added_sets_0)
2905 if (GET_CODE (PATTERN (i0)) == PARALLEL)
2906 i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
2907 else
2908 i0pat = copy_rtx (PATTERN (i0));
2911 combine_merges++;
2913 /* Substitute in the latest insn for the regs set by the earlier ones. */
2915 maxreg = max_reg_num ();
2917 subst_insn = i3;
2919 #ifndef HAVE_cc0
2920 /* Many machines that don't use CC0 have insns that can both perform an
2921 arithmetic operation and set the condition code. These operations will
2922 be represented as a PARALLEL with the first element of the vector
2923 being a COMPARE of an arithmetic operation with the constant zero.
2924 The second element of the vector will set some pseudo to the result
2925 of the same arithmetic operation. If we simplify the COMPARE, we won't
2926 match such a pattern and so will generate an extra insn. Here we test
2927 for this case, where both the comparison and the operation result are
2928 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2929 I2SRC. Later we will make the PARALLEL that contains I2. */
2931 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2932 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2933 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
2934 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2936 rtx newpat_dest;
2937 rtx *cc_use_loc = NULL, cc_use_insn = NULL_RTX;
2938 rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
2939 enum machine_mode compare_mode, orig_compare_mode;
2940 enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
2942 newpat = PATTERN (i3);
2943 newpat_dest = SET_DEST (newpat);
2944 compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
2946 if (undobuf.other_insn == 0
2947 && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
2948 &cc_use_insn)))
2950 compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
2951 compare_code = simplify_compare_const (compare_code,
2952 op0, &op1);
2953 target_canonicalize_comparison (&compare_code, &op0, &op1, 1);
2956 /* Do the rest only if op1 is const0_rtx, which may be the
2957 result of simplification. */
2958 if (op1 == const0_rtx)
2960 /* If a single use of the CC is found, prepare to modify it
2961 when SELECT_CC_MODE returns a new CC-class mode, or when
2962 the above simplify_compare_const() returned a new comparison
2963 operator. undobuf.other_insn is assigned the CC use insn
2964 when modifying it. */
2965 if (cc_use_loc)
2967 #ifdef SELECT_CC_MODE
2968 enum machine_mode new_mode
2969 = SELECT_CC_MODE (compare_code, op0, op1);
2970 if (new_mode != orig_compare_mode
2971 && can_change_dest_mode (SET_DEST (newpat),
2972 added_sets_2, new_mode))
2974 unsigned int regno = REGNO (newpat_dest);
2975 compare_mode = new_mode;
2976 if (regno < FIRST_PSEUDO_REGISTER)
2977 newpat_dest = gen_rtx_REG (compare_mode, regno);
2978 else
2980 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2981 newpat_dest = regno_reg_rtx[regno];
2984 #endif
2985 /* Cases for modifying the CC-using comparison. */
2986 if (compare_code != orig_compare_code
2987 /* ??? Do we need to verify the zero rtx? */
2988 && XEXP (*cc_use_loc, 1) == const0_rtx)
2990 /* Replace cc_use_loc with entire new RTX. */
2991 SUBST (*cc_use_loc,
2992 gen_rtx_fmt_ee (compare_code, compare_mode,
2993 newpat_dest, const0_rtx));
2994 undobuf.other_insn = cc_use_insn;
2996 else if (compare_mode != orig_compare_mode)
2998 /* Just replace the CC reg with a new mode. */
2999 SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
3000 undobuf.other_insn = cc_use_insn;
3004 /* Now we modify the current newpat:
3005 First, SET_DEST(newpat) is updated if the CC mode has been
3006 altered. For targets without SELECT_CC_MODE, this should be
3007 optimized away. */
3008 if (compare_mode != orig_compare_mode)
3009 SUBST (SET_DEST (newpat), newpat_dest);
3010 /* This is always done to propagate i2src into newpat. */
3011 SUBST (SET_SRC (newpat),
3012 gen_rtx_COMPARE (compare_mode, op0, op1));
3013 /* Create new version of i2pat if needed; the below PARALLEL
3014 creation needs this to work correctly. */
3015 if (! rtx_equal_p (i2src, op0))
3016 i2pat = gen_rtx_SET (VOIDmode, i2dest, op0);
3017 i2_is_used = 1;
3020 #endif
3022 if (i2_is_used == 0)
3024 /* It is possible that the source of I2 or I1 may be performing
3025 an unneeded operation, such as a ZERO_EXTEND of something
3026 that is known to have the high part zero. Handle that case
3027 by letting subst look at the inner insns.
3029 Another way to do this would be to have a function that tries
3030 to simplify a single insn instead of merging two or more
3031 insns. We don't do this because of the potential of infinite
3032 loops and because of the potential extra memory required.
3033 However, doing it the way we are is a bit of a kludge and
3034 doesn't catch all cases.
3036 But only do this if -fexpensive-optimizations since it slows
3037 things down and doesn't usually win.
3039 This is not done in the COMPARE case above because the
3040 unmodified I2PAT is used in the PARALLEL and so a pattern
3041 with a modified I2SRC would not match. */
3043 if (flag_expensive_optimizations)
3045 /* Pass pc_rtx so no substitutions are done, just
3046 simplifications. */
3047 if (i1)
3049 subst_low_luid = DF_INSN_LUID (i1);
3050 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3053 subst_low_luid = DF_INSN_LUID (i2);
3054 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3057 n_occurrences = 0; /* `subst' counts here */
3058 subst_low_luid = DF_INSN_LUID (i2);
3060 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3061 copy of I2SRC each time we substitute it, in order to avoid creating
3062 self-referential RTL when we will be substituting I1SRC for I1DEST
3063 later. Likewise if I0 feeds into I2, either directly or indirectly
3064 through I1, and I0DEST is in I0SRC. */
3065 newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3066 (i1_feeds_i2_n && i1dest_in_i1src)
3067 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3068 && i0dest_in_i0src));
3069 substed_i2 = 1;
3071 /* Record whether I2's body now appears within I3's body. */
3072 i2_is_used = n_occurrences;
3075 /* If we already got a failure, don't try to do more. Otherwise, try to
3076 substitute I1 if we have it. */
3078 if (i1 && GET_CODE (newpat) != CLOBBER)
3080 /* Check that an autoincrement side-effect on I1 has not been lost.
3081 This happens if I1DEST is mentioned in I2 and dies there, and
3082 has disappeared from the new pattern. */
3083 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3084 && i1_feeds_i2_n
3085 && dead_or_set_p (i2, i1dest)
3086 && !reg_overlap_mentioned_p (i1dest, newpat))
3087 /* Before we can do this substitution, we must redo the test done
3088 above (see detailed comments there) that ensures I1DEST isn't
3089 mentioned in any SETs in NEWPAT that are field assignments. */
3090 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3091 0, 0, 0))
3093 undo_all ();
3094 return 0;
3097 n_occurrences = 0;
3098 subst_low_luid = DF_INSN_LUID (i1);
3100 /* If the following substitution will modify I1SRC, make a copy of it
3101 for the case where it is substituted for I1DEST in I2PAT later. */
3102 if (added_sets_2 && i1_feeds_i2_n)
3103 i1src_copy = copy_rtx (i1src);
3105 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3106 copy of I1SRC each time we substitute it, in order to avoid creating
3107 self-referential RTL when we will be substituting I0SRC for I0DEST
3108 later. */
3109 newpat = subst (newpat, i1dest, i1src, 0, 0,
3110 i0_feeds_i1_n && i0dest_in_i0src);
3111 substed_i1 = 1;
3113 /* Record whether I1's body now appears within I3's body. */
3114 i1_is_used = n_occurrences;
3117 /* Likewise for I0 if we have it. */
3119 if (i0 && GET_CODE (newpat) != CLOBBER)
3121 if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3122 && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3123 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3124 && !reg_overlap_mentioned_p (i0dest, newpat))
3125 || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3126 0, 0, 0))
3128 undo_all ();
3129 return 0;
3132 /* If the following substitution will modify I0SRC, make a copy of it
3133 for the case where it is substituted for I0DEST in I1PAT later. */
3134 if (added_sets_1 && i0_feeds_i1_n)
3135 i0src_copy = copy_rtx (i0src);
3136 /* And a copy for I0DEST in I2PAT substitution. */
3137 if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3138 || (i0_feeds_i2_n)))
3139 i0src_copy2 = copy_rtx (i0src);
3141 n_occurrences = 0;
3142 subst_low_luid = DF_INSN_LUID (i0);
3143 newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3144 substed_i0 = 1;
3147 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3148 to count all the ways that I2SRC and I1SRC can be used. */
3149 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3150 && i2_is_used + added_sets_2 > 1)
3151 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3152 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3153 > 1))
3154 || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3155 && (n_occurrences + added_sets_0
3156 + (added_sets_1 && i0_feeds_i1_n)
3157 + (added_sets_2 && i0_feeds_i2_n)
3158 > 1))
3159 /* Fail if we tried to make a new register. */
3160 || max_reg_num () != maxreg
3161 /* Fail if we couldn't do something and have a CLOBBER. */
3162 || GET_CODE (newpat) == CLOBBER
3163 /* Fail if this new pattern is a MULT and we didn't have one before
3164 at the outer level. */
3165 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3166 && ! have_mult))
3168 undo_all ();
3169 return 0;
3172 /* If the actions of the earlier insns must be kept
3173 in addition to substituting them into the latest one,
3174 we must make a new PARALLEL for the latest insn
3175 to hold additional the SETs. */
3177 if (added_sets_0 || added_sets_1 || added_sets_2)
3179 int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3180 combine_extras++;
3182 if (GET_CODE (newpat) == PARALLEL)
3184 rtvec old = XVEC (newpat, 0);
3185 total_sets = XVECLEN (newpat, 0) + extra_sets;
3186 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3187 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3188 sizeof (old->elem[0]) * old->num_elem);
3190 else
3192 rtx old = newpat;
3193 total_sets = 1 + extra_sets;
3194 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3195 XVECEXP (newpat, 0, 0) = old;
3198 if (added_sets_0)
3199 XVECEXP (newpat, 0, --total_sets) = i0pat;
3201 if (added_sets_1)
3203 rtx t = i1pat;
3204 if (i0_feeds_i1_n)
3205 t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0);
3207 XVECEXP (newpat, 0, --total_sets) = t;
3209 if (added_sets_2)
3211 rtx t = i2pat;
3212 if (i1_feeds_i2_n)
3213 t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3214 i0_feeds_i1_n && i0dest_in_i0src);
3215 if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3216 t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0);
3218 XVECEXP (newpat, 0, --total_sets) = t;
3222 validate_replacement:
3224 /* Note which hard regs this insn has as inputs. */
3225 mark_used_regs_combine (newpat);
3227 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3228 consider splitting this pattern, we might need these clobbers. */
3229 if (i1 && GET_CODE (newpat) == PARALLEL
3230 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3232 int len = XVECLEN (newpat, 0);
3234 newpat_vec_with_clobbers = rtvec_alloc (len);
3235 for (i = 0; i < len; i++)
3236 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3239 /* Is the result of combination a valid instruction? */
3240 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3242 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3243 the second SET's destination is a register that is unused and isn't
3244 marked as an instruction that might trap in an EH region. In that case,
3245 we just need the first SET. This can occur when simplifying a divmod
3246 insn. We *must* test for this case here because the code below that
3247 splits two independent SETs doesn't handle this case correctly when it
3248 updates the register status.
3250 It's pointless doing this if we originally had two sets, one from
3251 i3, and one from i2. Combining then splitting the parallel results
3252 in the original i2 again plus an invalid insn (which we delete).
3253 The net effect is only to move instructions around, which makes
3254 debug info less accurate.
3256 Also check the case where the first SET's destination is unused.
3257 That would not cause incorrect code, but does cause an unneeded
3258 insn to remain. */
3260 if (insn_code_number < 0
3261 && !(added_sets_2 && i1 == 0)
3262 && GET_CODE (newpat) == PARALLEL
3263 && XVECLEN (newpat, 0) == 2
3264 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3265 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3266 && asm_noperands (newpat) < 0)
3268 rtx set0 = XVECEXP (newpat, 0, 0);
3269 rtx set1 = XVECEXP (newpat, 0, 1);
3271 if (((REG_P (SET_DEST (set1))
3272 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3273 || (GET_CODE (SET_DEST (set1)) == SUBREG
3274 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3275 && insn_nothrow_p (i3)
3276 && !side_effects_p (SET_SRC (set1)))
3278 newpat = set0;
3279 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3282 else if (((REG_P (SET_DEST (set0))
3283 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3284 || (GET_CODE (SET_DEST (set0)) == SUBREG
3285 && find_reg_note (i3, REG_UNUSED,
3286 SUBREG_REG (SET_DEST (set0)))))
3287 && insn_nothrow_p (i3)
3288 && !side_effects_p (SET_SRC (set0)))
3290 newpat = set1;
3291 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3293 if (insn_code_number >= 0)
3294 changed_i3_dest = 1;
3298 /* If we were combining three insns and the result is a simple SET
3299 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3300 insns. There are two ways to do this. It can be split using a
3301 machine-specific method (like when you have an addition of a large
3302 constant) or by combine in the function find_split_point. */
3304 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3305 && asm_noperands (newpat) < 0)
3307 rtx parallel, m_split, *split;
3309 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3310 use I2DEST as a scratch register will help. In the latter case,
3311 convert I2DEST to the mode of the source of NEWPAT if we can. */
3313 m_split = combine_split_insns (newpat, i3);
3315 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3316 inputs of NEWPAT. */
3318 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3319 possible to try that as a scratch reg. This would require adding
3320 more code to make it work though. */
3322 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3324 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3326 /* First try to split using the original register as a
3327 scratch register. */
3328 parallel = gen_rtx_PARALLEL (VOIDmode,
3329 gen_rtvec (2, newpat,
3330 gen_rtx_CLOBBER (VOIDmode,
3331 i2dest)));
3332 m_split = combine_split_insns (parallel, i3);
3334 /* If that didn't work, try changing the mode of I2DEST if
3335 we can. */
3336 if (m_split == 0
3337 && new_mode != GET_MODE (i2dest)
3338 && new_mode != VOIDmode
3339 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3341 enum machine_mode old_mode = GET_MODE (i2dest);
3342 rtx ni2dest;
3344 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3345 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3346 else
3348 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3349 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3352 parallel = (gen_rtx_PARALLEL
3353 (VOIDmode,
3354 gen_rtvec (2, newpat,
3355 gen_rtx_CLOBBER (VOIDmode,
3356 ni2dest))));
3357 m_split = combine_split_insns (parallel, i3);
3359 if (m_split == 0
3360 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3362 struct undo *buf;
3364 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3365 buf = undobuf.undos;
3366 undobuf.undos = buf->next;
3367 buf->next = undobuf.frees;
3368 undobuf.frees = buf;
3372 i2scratch = m_split != 0;
3375 /* If recog_for_combine has discarded clobbers, try to use them
3376 again for the split. */
3377 if (m_split == 0 && newpat_vec_with_clobbers)
3379 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3380 m_split = combine_split_insns (parallel, i3);
3383 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3385 m_split = PATTERN (m_split);
3386 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3387 if (insn_code_number >= 0)
3388 newpat = m_split;
3390 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3391 && (next_nonnote_nondebug_insn (i2) == i3
3392 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3394 rtx i2set, i3set;
3395 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3396 newi2pat = PATTERN (m_split);
3398 i3set = single_set (NEXT_INSN (m_split));
3399 i2set = single_set (m_split);
3401 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3403 /* If I2 or I3 has multiple SETs, we won't know how to track
3404 register status, so don't use these insns. If I2's destination
3405 is used between I2 and I3, we also can't use these insns. */
3407 if (i2_code_number >= 0 && i2set && i3set
3408 && (next_nonnote_nondebug_insn (i2) == i3
3409 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3410 insn_code_number = recog_for_combine (&newi3pat, i3,
3411 &new_i3_notes);
3412 if (insn_code_number >= 0)
3413 newpat = newi3pat;
3415 /* It is possible that both insns now set the destination of I3.
3416 If so, we must show an extra use of it. */
3418 if (insn_code_number >= 0)
3420 rtx new_i3_dest = SET_DEST (i3set);
3421 rtx new_i2_dest = SET_DEST (i2set);
3423 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3424 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3425 || GET_CODE (new_i3_dest) == SUBREG)
3426 new_i3_dest = XEXP (new_i3_dest, 0);
3428 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3429 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3430 || GET_CODE (new_i2_dest) == SUBREG)
3431 new_i2_dest = XEXP (new_i2_dest, 0);
3433 if (REG_P (new_i3_dest)
3434 && REG_P (new_i2_dest)
3435 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3436 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3440 /* If we can split it and use I2DEST, go ahead and see if that
3441 helps things be recognized. Verify that none of the registers
3442 are set between I2 and I3. */
3443 if (insn_code_number < 0
3444 && (split = find_split_point (&newpat, i3, false)) != 0
3445 #ifdef HAVE_cc0
3446 && REG_P (i2dest)
3447 #endif
3448 /* We need I2DEST in the proper mode. If it is a hard register
3449 or the only use of a pseudo, we can change its mode.
3450 Make sure we don't change a hard register to have a mode that
3451 isn't valid for it, or change the number of registers. */
3452 && (GET_MODE (*split) == GET_MODE (i2dest)
3453 || GET_MODE (*split) == VOIDmode
3454 || can_change_dest_mode (i2dest, added_sets_2,
3455 GET_MODE (*split)))
3456 && (next_nonnote_nondebug_insn (i2) == i3
3457 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3458 /* We can't overwrite I2DEST if its value is still used by
3459 NEWPAT. */
3460 && ! reg_referenced_p (i2dest, newpat))
3462 rtx newdest = i2dest;
3463 enum rtx_code split_code = GET_CODE (*split);
3464 enum machine_mode split_mode = GET_MODE (*split);
3465 bool subst_done = false;
3466 newi2pat = NULL_RTX;
3468 i2scratch = true;
3470 /* *SPLIT may be part of I2SRC, so make sure we have the
3471 original expression around for later debug processing.
3472 We should not need I2SRC any more in other cases. */
3473 if (MAY_HAVE_DEBUG_INSNS)
3474 i2src = copy_rtx (i2src);
3475 else
3476 i2src = NULL;
3478 /* Get NEWDEST as a register in the proper mode. We have already
3479 validated that we can do this. */
3480 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3482 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3483 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3484 else
3486 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3487 newdest = regno_reg_rtx[REGNO (i2dest)];
3491 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3492 an ASHIFT. This can occur if it was inside a PLUS and hence
3493 appeared to be a memory address. This is a kludge. */
3494 if (split_code == MULT
3495 && CONST_INT_P (XEXP (*split, 1))
3496 && INTVAL (XEXP (*split, 1)) > 0
3497 && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3499 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3500 XEXP (*split, 0), GEN_INT (i)));
3501 /* Update split_code because we may not have a multiply
3502 anymore. */
3503 split_code = GET_CODE (*split);
3506 #ifdef INSN_SCHEDULING
3507 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3508 be written as a ZERO_EXTEND. */
3509 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3511 #ifdef LOAD_EXTEND_OP
3512 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3513 what it really is. */
3514 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3515 == SIGN_EXTEND)
3516 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3517 SUBREG_REG (*split)));
3518 else
3519 #endif
3520 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3521 SUBREG_REG (*split)));
3523 #endif
3525 /* Attempt to split binary operators using arithmetic identities. */
3526 if (BINARY_P (SET_SRC (newpat))
3527 && split_mode == GET_MODE (SET_SRC (newpat))
3528 && ! side_effects_p (SET_SRC (newpat)))
3530 rtx setsrc = SET_SRC (newpat);
3531 enum machine_mode mode = GET_MODE (setsrc);
3532 enum rtx_code code = GET_CODE (setsrc);
3533 rtx src_op0 = XEXP (setsrc, 0);
3534 rtx src_op1 = XEXP (setsrc, 1);
3536 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3537 if (rtx_equal_p (src_op0, src_op1))
3539 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3540 SUBST (XEXP (setsrc, 0), newdest);
3541 SUBST (XEXP (setsrc, 1), newdest);
3542 subst_done = true;
3544 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3545 else if ((code == PLUS || code == MULT)
3546 && GET_CODE (src_op0) == code
3547 && GET_CODE (XEXP (src_op0, 0)) == code
3548 && (INTEGRAL_MODE_P (mode)
3549 || (FLOAT_MODE_P (mode)
3550 && flag_unsafe_math_optimizations)))
3552 rtx p = XEXP (XEXP (src_op0, 0), 0);
3553 rtx q = XEXP (XEXP (src_op0, 0), 1);
3554 rtx r = XEXP (src_op0, 1);
3555 rtx s = src_op1;
3557 /* Split both "((X op Y) op X) op Y" and
3558 "((X op Y) op Y) op X" as "T op T" where T is
3559 "X op Y". */
3560 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3561 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3563 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3564 XEXP (src_op0, 0));
3565 SUBST (XEXP (setsrc, 0), newdest);
3566 SUBST (XEXP (setsrc, 1), newdest);
3567 subst_done = true;
3569 /* Split "((X op X) op Y) op Y)" as "T op T" where
3570 T is "X op Y". */
3571 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3573 rtx tmp = simplify_gen_binary (code, mode, p, r);
3574 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3575 SUBST (XEXP (setsrc, 0), newdest);
3576 SUBST (XEXP (setsrc, 1), newdest);
3577 subst_done = true;
3582 if (!subst_done)
3584 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3585 SUBST (*split, newdest);
3588 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3590 /* recog_for_combine might have added CLOBBERs to newi2pat.
3591 Make sure NEWPAT does not depend on the clobbered regs. */
3592 if (GET_CODE (newi2pat) == PARALLEL)
3593 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3594 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3596 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3597 if (reg_overlap_mentioned_p (reg, newpat))
3599 undo_all ();
3600 return 0;
3604 /* If the split point was a MULT and we didn't have one before,
3605 don't use one now. */
3606 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3607 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3611 /* Check for a case where we loaded from memory in a narrow mode and
3612 then sign extended it, but we need both registers. In that case,
3613 we have a PARALLEL with both loads from the same memory location.
3614 We can split this into a load from memory followed by a register-register
3615 copy. This saves at least one insn, more if register allocation can
3616 eliminate the copy.
3618 We cannot do this if the destination of the first assignment is a
3619 condition code register or cc0. We eliminate this case by making sure
3620 the SET_DEST and SET_SRC have the same mode.
3622 We cannot do this if the destination of the second assignment is
3623 a register that we have already assumed is zero-extended. Similarly
3624 for a SUBREG of such a register. */
3626 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3627 && GET_CODE (newpat) == PARALLEL
3628 && XVECLEN (newpat, 0) == 2
3629 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3630 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3631 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3632 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3633 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3634 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3635 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3636 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3637 DF_INSN_LUID (i2))
3638 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3639 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3640 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3641 (REG_P (temp)
3642 && reg_stat[REGNO (temp)].nonzero_bits != 0
3643 && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3644 && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3645 && (reg_stat[REGNO (temp)].nonzero_bits
3646 != GET_MODE_MASK (word_mode))))
3647 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3648 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3649 (REG_P (temp)
3650 && reg_stat[REGNO (temp)].nonzero_bits != 0
3651 && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3652 && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3653 && (reg_stat[REGNO (temp)].nonzero_bits
3654 != GET_MODE_MASK (word_mode)))))
3655 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3656 SET_SRC (XVECEXP (newpat, 0, 1)))
3657 && ! find_reg_note (i3, REG_UNUSED,
3658 SET_DEST (XVECEXP (newpat, 0, 0))))
3660 rtx ni2dest;
3662 newi2pat = XVECEXP (newpat, 0, 0);
3663 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3664 newpat = XVECEXP (newpat, 0, 1);
3665 SUBST (SET_SRC (newpat),
3666 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3667 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3669 if (i2_code_number >= 0)
3670 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3672 if (insn_code_number >= 0)
3673 swap_i2i3 = 1;
3676 /* Similarly, check for a case where we have a PARALLEL of two independent
3677 SETs but we started with three insns. In this case, we can do the sets
3678 as two separate insns. This case occurs when some SET allows two
3679 other insns to combine, but the destination of that SET is still live. */
3681 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3682 && GET_CODE (newpat) == PARALLEL
3683 && XVECLEN (newpat, 0) == 2
3684 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3685 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3686 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3687 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3688 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3689 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3690 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3691 XVECEXP (newpat, 0, 0))
3692 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3693 XVECEXP (newpat, 0, 1))
3694 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3695 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3697 rtx set0 = XVECEXP (newpat, 0, 0);
3698 rtx set1 = XVECEXP (newpat, 0, 1);
3700 /* Normally, it doesn't matter which of the two is done first,
3701 but the one that references cc0 can't be the second, and
3702 one which uses any regs/memory set in between i2 and i3 can't
3703 be first. The PARALLEL might also have been pre-existing in i3,
3704 so we need to make sure that we won't wrongly hoist a SET to i2
3705 that would conflict with a death note present in there. */
3706 if (!use_crosses_set_p (SET_SRC (set1), DF_INSN_LUID (i2))
3707 && !(REG_P (SET_DEST (set1))
3708 && find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
3709 && !(GET_CODE (SET_DEST (set1)) == SUBREG
3710 && find_reg_note (i2, REG_DEAD,
3711 SUBREG_REG (SET_DEST (set1))))
3712 #ifdef HAVE_cc0
3713 && !reg_referenced_p (cc0_rtx, set0)
3714 #endif
3717 newi2pat = set1;
3718 newpat = set0;
3720 else if (!use_crosses_set_p (SET_SRC (set0), DF_INSN_LUID (i2))
3721 && !(REG_P (SET_DEST (set0))
3722 && find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
3723 && !(GET_CODE (SET_DEST (set0)) == SUBREG
3724 && find_reg_note (i2, REG_DEAD,
3725 SUBREG_REG (SET_DEST (set0))))
3726 #ifdef HAVE_cc0
3727 && !reg_referenced_p (cc0_rtx, set1)
3728 #endif
3731 newi2pat = set0;
3732 newpat = set1;
3734 else
3736 undo_all ();
3737 return 0;
3740 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3742 if (i2_code_number >= 0)
3744 /* recog_for_combine might have added CLOBBERs to newi2pat.
3745 Make sure NEWPAT does not depend on the clobbered regs. */
3746 if (GET_CODE (newi2pat) == PARALLEL)
3748 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3749 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3751 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3752 if (reg_overlap_mentioned_p (reg, newpat))
3754 undo_all ();
3755 return 0;
3760 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3764 /* If it still isn't recognized, fail and change things back the way they
3765 were. */
3766 if ((insn_code_number < 0
3767 /* Is the result a reasonable ASM_OPERANDS? */
3768 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3770 undo_all ();
3771 return 0;
3774 /* If we had to change another insn, make sure it is valid also. */
3775 if (undobuf.other_insn)
3777 CLEAR_HARD_REG_SET (newpat_used_regs);
3779 other_pat = PATTERN (undobuf.other_insn);
3780 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3781 &new_other_notes);
3783 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3785 undo_all ();
3786 return 0;
3790 #ifdef HAVE_cc0
3791 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3792 they are adjacent to each other or not. */
3794 rtx p = prev_nonnote_insn (i3);
3795 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3796 && sets_cc0_p (newi2pat))
3798 undo_all ();
3799 return 0;
3802 #endif
3804 /* Only allow this combination if insn_rtx_costs reports that the
3805 replacement instructions are cheaper than the originals. */
3806 if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3808 undo_all ();
3809 return 0;
3812 if (MAY_HAVE_DEBUG_INSNS)
3814 struct undo *undo;
3816 for (undo = undobuf.undos; undo; undo = undo->next)
3817 if (undo->kind == UNDO_MODE)
3819 rtx reg = *undo->where.r;
3820 enum machine_mode new_mode = GET_MODE (reg);
3821 enum machine_mode old_mode = undo->old_contents.m;
3823 /* Temporarily revert mode back. */
3824 adjust_reg_mode (reg, old_mode);
3826 if (reg == i2dest && i2scratch)
3828 /* If we used i2dest as a scratch register with a
3829 different mode, substitute it for the original
3830 i2src while its original mode is temporarily
3831 restored, and then clear i2scratch so that we don't
3832 do it again later. */
3833 propagate_for_debug (i2, last_combined_insn, reg, i2src,
3834 this_basic_block);
3835 i2scratch = false;
3836 /* Put back the new mode. */
3837 adjust_reg_mode (reg, new_mode);
3839 else
3841 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3842 rtx first, last;
3844 if (reg == i2dest)
3846 first = i2;
3847 last = last_combined_insn;
3849 else
3851 first = i3;
3852 last = undobuf.other_insn;
3853 gcc_assert (last);
3854 if (DF_INSN_LUID (last)
3855 < DF_INSN_LUID (last_combined_insn))
3856 last = last_combined_insn;
3859 /* We're dealing with a reg that changed mode but not
3860 meaning, so we want to turn it into a subreg for
3861 the new mode. However, because of REG sharing and
3862 because its mode had already changed, we have to do
3863 it in two steps. First, replace any debug uses of
3864 reg, with its original mode temporarily restored,
3865 with this copy we have created; then, replace the
3866 copy with the SUBREG of the original shared reg,
3867 once again changed to the new mode. */
3868 propagate_for_debug (first, last, reg, tempreg,
3869 this_basic_block);
3870 adjust_reg_mode (reg, new_mode);
3871 propagate_for_debug (first, last, tempreg,
3872 lowpart_subreg (old_mode, reg, new_mode),
3873 this_basic_block);
3878 /* If we will be able to accept this, we have made a
3879 change to the destination of I3. This requires us to
3880 do a few adjustments. */
3882 if (changed_i3_dest)
3884 PATTERN (i3) = newpat;
3885 adjust_for_new_dest (i3);
3888 /* We now know that we can do this combination. Merge the insns and
3889 update the status of registers and LOG_LINKS. */
3891 if (undobuf.other_insn)
3893 rtx note, next;
3895 PATTERN (undobuf.other_insn) = other_pat;
3897 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
3898 ensure that they are still valid. Then add any non-duplicate
3899 notes added by recog_for_combine. */
3900 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3902 next = XEXP (note, 1);
3904 if ((REG_NOTE_KIND (note) == REG_DEAD
3905 && !reg_referenced_p (XEXP (note, 0),
3906 PATTERN (undobuf.other_insn)))
3907 ||(REG_NOTE_KIND (note) == REG_UNUSED
3908 && !reg_set_p (XEXP (note, 0),
3909 PATTERN (undobuf.other_insn))))
3910 remove_note (undobuf.other_insn, note);
3913 distribute_notes (new_other_notes, undobuf.other_insn,
3914 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
3915 NULL_RTX);
3918 if (swap_i2i3)
3920 rtx insn;
3921 struct insn_link *link;
3922 rtx ni2dest;
3924 /* I3 now uses what used to be its destination and which is now
3925 I2's destination. This requires us to do a few adjustments. */
3926 PATTERN (i3) = newpat;
3927 adjust_for_new_dest (i3);
3929 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3930 so we still will.
3932 However, some later insn might be using I2's dest and have
3933 a LOG_LINK pointing at I3. We must remove this link.
3934 The simplest way to remove the link is to point it at I1,
3935 which we know will be a NOTE. */
3937 /* newi2pat is usually a SET here; however, recog_for_combine might
3938 have added some clobbers. */
3939 if (GET_CODE (newi2pat) == PARALLEL)
3940 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3941 else
3942 ni2dest = SET_DEST (newi2pat);
3944 for (insn = NEXT_INSN (i3);
3945 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
3946 || insn != BB_HEAD (this_basic_block->next_bb));
3947 insn = NEXT_INSN (insn))
3949 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3951 FOR_EACH_LOG_LINK (link, insn)
3952 if (link->insn == i3)
3953 link->insn = i1;
3955 break;
3961 rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
3962 struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
3963 rtx midnotes = 0;
3964 int from_luid;
3965 /* Compute which registers we expect to eliminate. newi2pat may be setting
3966 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3967 same as i3dest, in which case newi2pat may be setting i1dest. */
3968 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3969 || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
3970 || !i2dest_killed
3971 ? 0 : i2dest);
3972 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
3973 || (newi2pat && reg_set_p (i1dest, newi2pat))
3974 || !i1dest_killed
3975 ? 0 : i1dest);
3976 rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
3977 || (newi2pat && reg_set_p (i0dest, newi2pat))
3978 || !i0dest_killed
3979 ? 0 : i0dest);
3981 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3982 clear them. */
3983 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3984 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3985 if (i1)
3986 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3987 if (i0)
3988 i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
3990 /* Ensure that we do not have something that should not be shared but
3991 occurs multiple times in the new insns. Check this by first
3992 resetting all the `used' flags and then copying anything is shared. */
3994 reset_used_flags (i3notes);
3995 reset_used_flags (i2notes);
3996 reset_used_flags (i1notes);
3997 reset_used_flags (i0notes);
3998 reset_used_flags (newpat);
3999 reset_used_flags (newi2pat);
4000 if (undobuf.other_insn)
4001 reset_used_flags (PATTERN (undobuf.other_insn));
4003 i3notes = copy_rtx_if_shared (i3notes);
4004 i2notes = copy_rtx_if_shared (i2notes);
4005 i1notes = copy_rtx_if_shared (i1notes);
4006 i0notes = copy_rtx_if_shared (i0notes);
4007 newpat = copy_rtx_if_shared (newpat);
4008 newi2pat = copy_rtx_if_shared (newi2pat);
4009 if (undobuf.other_insn)
4010 reset_used_flags (PATTERN (undobuf.other_insn));
4012 INSN_CODE (i3) = insn_code_number;
4013 PATTERN (i3) = newpat;
4015 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4017 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4019 reset_used_flags (call_usage);
4020 call_usage = copy_rtx (call_usage);
4022 if (substed_i2)
4024 /* I2SRC must still be meaningful at this point. Some splitting
4025 operations can invalidate I2SRC, but those operations do not
4026 apply to calls. */
4027 gcc_assert (i2src);
4028 replace_rtx (call_usage, i2dest, i2src);
4031 if (substed_i1)
4032 replace_rtx (call_usage, i1dest, i1src);
4033 if (substed_i0)
4034 replace_rtx (call_usage, i0dest, i0src);
4036 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4039 if (undobuf.other_insn)
4040 INSN_CODE (undobuf.other_insn) = other_code_number;
4042 /* We had one special case above where I2 had more than one set and
4043 we replaced a destination of one of those sets with the destination
4044 of I3. In that case, we have to update LOG_LINKS of insns later
4045 in this basic block. Note that this (expensive) case is rare.
4047 Also, in this case, we must pretend that all REG_NOTEs for I2
4048 actually came from I3, so that REG_UNUSED notes from I2 will be
4049 properly handled. */
4051 if (i3_subst_into_i2)
4053 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4054 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4055 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4056 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4057 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4058 && ! find_reg_note (i2, REG_UNUSED,
4059 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4060 for (temp = NEXT_INSN (i2);
4061 temp
4062 && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
4063 || BB_HEAD (this_basic_block) != temp);
4064 temp = NEXT_INSN (temp))
4065 if (temp != i3 && INSN_P (temp))
4066 FOR_EACH_LOG_LINK (link, temp)
4067 if (link->insn == i2)
4068 link->insn = i3;
4070 if (i3notes)
4072 rtx link = i3notes;
4073 while (XEXP (link, 1))
4074 link = XEXP (link, 1);
4075 XEXP (link, 1) = i2notes;
4077 else
4078 i3notes = i2notes;
4079 i2notes = 0;
4082 LOG_LINKS (i3) = NULL;
4083 REG_NOTES (i3) = 0;
4084 LOG_LINKS (i2) = NULL;
4085 REG_NOTES (i2) = 0;
4087 if (newi2pat)
4089 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4090 propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4091 this_basic_block);
4092 INSN_CODE (i2) = i2_code_number;
4093 PATTERN (i2) = newi2pat;
4095 else
4097 if (MAY_HAVE_DEBUG_INSNS && i2src)
4098 propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4099 this_basic_block);
4100 SET_INSN_DELETED (i2);
4103 if (i1)
4105 LOG_LINKS (i1) = NULL;
4106 REG_NOTES (i1) = 0;
4107 if (MAY_HAVE_DEBUG_INSNS)
4108 propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4109 this_basic_block);
4110 SET_INSN_DELETED (i1);
4113 if (i0)
4115 LOG_LINKS (i0) = NULL;
4116 REG_NOTES (i0) = 0;
4117 if (MAY_HAVE_DEBUG_INSNS)
4118 propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4119 this_basic_block);
4120 SET_INSN_DELETED (i0);
4123 /* Get death notes for everything that is now used in either I3 or
4124 I2 and used to die in a previous insn. If we built two new
4125 patterns, move from I1 to I2 then I2 to I3 so that we get the
4126 proper movement on registers that I2 modifies. */
4128 if (i0)
4129 from_luid = DF_INSN_LUID (i0);
4130 else if (i1)
4131 from_luid = DF_INSN_LUID (i1);
4132 else
4133 from_luid = DF_INSN_LUID (i2);
4134 if (newi2pat)
4135 move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4136 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4138 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4139 if (i3notes)
4140 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4141 elim_i2, elim_i1, elim_i0);
4142 if (i2notes)
4143 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4144 elim_i2, elim_i1, elim_i0);
4145 if (i1notes)
4146 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4147 elim_i2, elim_i1, elim_i0);
4148 if (i0notes)
4149 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4150 elim_i2, elim_i1, elim_i0);
4151 if (midnotes)
4152 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4153 elim_i2, elim_i1, elim_i0);
4155 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4156 know these are REG_UNUSED and want them to go to the desired insn,
4157 so we always pass it as i3. */
4159 if (newi2pat && new_i2_notes)
4160 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4161 NULL_RTX);
4163 if (new_i3_notes)
4164 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4165 NULL_RTX);
4167 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4168 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4169 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4170 in that case, it might delete I2. Similarly for I2 and I1.
4171 Show an additional death due to the REG_DEAD note we make here. If
4172 we discard it in distribute_notes, we will decrement it again. */
4174 if (i3dest_killed)
4176 rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX);
4177 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4178 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, elim_i2,
4179 elim_i1, elim_i0);
4180 else
4181 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4182 elim_i2, elim_i1, elim_i0);
4185 if (i2dest_in_i2src)
4187 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4188 if (newi2pat && reg_set_p (i2dest, newi2pat))
4189 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4190 NULL_RTX, NULL_RTX);
4191 else
4192 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4193 NULL_RTX, NULL_RTX, NULL_RTX);
4196 if (i1dest_in_i1src)
4198 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4199 if (newi2pat && reg_set_p (i1dest, newi2pat))
4200 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4201 NULL_RTX, NULL_RTX);
4202 else
4203 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4204 NULL_RTX, NULL_RTX, NULL_RTX);
4207 if (i0dest_in_i0src)
4209 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4210 if (newi2pat && reg_set_p (i0dest, newi2pat))
4211 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4212 NULL_RTX, NULL_RTX);
4213 else
4214 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4215 NULL_RTX, NULL_RTX, NULL_RTX);
4218 distribute_links (i3links);
4219 distribute_links (i2links);
4220 distribute_links (i1links);
4221 distribute_links (i0links);
4223 if (REG_P (i2dest))
4225 struct insn_link *link;
4226 rtx i2_insn = 0, i2_val = 0, set;
4228 /* The insn that used to set this register doesn't exist, and
4229 this life of the register may not exist either. See if one of
4230 I3's links points to an insn that sets I2DEST. If it does,
4231 that is now the last known value for I2DEST. If we don't update
4232 this and I2 set the register to a value that depended on its old
4233 contents, we will get confused. If this insn is used, thing
4234 will be set correctly in combine_instructions. */
4235 FOR_EACH_LOG_LINK (link, i3)
4236 if ((set = single_set (link->insn)) != 0
4237 && rtx_equal_p (i2dest, SET_DEST (set)))
4238 i2_insn = link->insn, i2_val = SET_SRC (set);
4240 record_value_for_reg (i2dest, i2_insn, i2_val);
4242 /* If the reg formerly set in I2 died only once and that was in I3,
4243 zero its use count so it won't make `reload' do any work. */
4244 if (! added_sets_2
4245 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4246 && ! i2dest_in_i2src)
4247 INC_REG_N_SETS (REGNO (i2dest), -1);
4250 if (i1 && REG_P (i1dest))
4252 struct insn_link *link;
4253 rtx i1_insn = 0, i1_val = 0, set;
4255 FOR_EACH_LOG_LINK (link, i3)
4256 if ((set = single_set (link->insn)) != 0
4257 && rtx_equal_p (i1dest, SET_DEST (set)))
4258 i1_insn = link->insn, i1_val = SET_SRC (set);
4260 record_value_for_reg (i1dest, i1_insn, i1_val);
4262 if (! added_sets_1 && ! i1dest_in_i1src)
4263 INC_REG_N_SETS (REGNO (i1dest), -1);
4266 if (i0 && REG_P (i0dest))
4268 struct insn_link *link;
4269 rtx i0_insn = 0, i0_val = 0, set;
4271 FOR_EACH_LOG_LINK (link, i3)
4272 if ((set = single_set (link->insn)) != 0
4273 && rtx_equal_p (i0dest, SET_DEST (set)))
4274 i0_insn = link->insn, i0_val = SET_SRC (set);
4276 record_value_for_reg (i0dest, i0_insn, i0_val);
4278 if (! added_sets_0 && ! i0dest_in_i0src)
4279 INC_REG_N_SETS (REGNO (i0dest), -1);
4282 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4283 been made to this insn. The order is important, because newi2pat
4284 can affect nonzero_bits of newpat. */
4285 if (newi2pat)
4286 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4287 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4290 if (undobuf.other_insn != NULL_RTX)
4292 if (dump_file)
4294 fprintf (dump_file, "modifying other_insn ");
4295 dump_insn_slim (dump_file, undobuf.other_insn);
4297 df_insn_rescan (undobuf.other_insn);
4300 if (i0 && !(NOTE_P (i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4302 if (dump_file)
4304 fprintf (dump_file, "modifying insn i0 ");
4305 dump_insn_slim (dump_file, i0);
4307 df_insn_rescan (i0);
4310 if (i1 && !(NOTE_P (i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4312 if (dump_file)
4314 fprintf (dump_file, "modifying insn i1 ");
4315 dump_insn_slim (dump_file, i1);
4317 df_insn_rescan (i1);
4320 if (i2 && !(NOTE_P (i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4322 if (dump_file)
4324 fprintf (dump_file, "modifying insn i2 ");
4325 dump_insn_slim (dump_file, i2);
4327 df_insn_rescan (i2);
4330 if (i3 && !(NOTE_P (i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4332 if (dump_file)
4334 fprintf (dump_file, "modifying insn i3 ");
4335 dump_insn_slim (dump_file, i3);
4337 df_insn_rescan (i3);
4340 /* Set new_direct_jump_p if a new return or simple jump instruction
4341 has been created. Adjust the CFG accordingly. */
4342 if (returnjump_p (i3) || any_uncondjump_p (i3))
4344 *new_direct_jump_p = 1;
4345 mark_jump_label (PATTERN (i3), i3, 0);
4346 update_cfg_for_uncondjump (i3);
4349 if (undobuf.other_insn != NULL_RTX
4350 && (returnjump_p (undobuf.other_insn)
4351 || any_uncondjump_p (undobuf.other_insn)))
4353 *new_direct_jump_p = 1;
4354 update_cfg_for_uncondjump (undobuf.other_insn);
4357 /* A noop might also need cleaning up of CFG, if it comes from the
4358 simplification of a jump. */
4359 if (JUMP_P (i3)
4360 && GET_CODE (newpat) == SET
4361 && SET_SRC (newpat) == pc_rtx
4362 && SET_DEST (newpat) == pc_rtx)
4364 *new_direct_jump_p = 1;
4365 update_cfg_for_uncondjump (i3);
4368 if (undobuf.other_insn != NULL_RTX
4369 && JUMP_P (undobuf.other_insn)
4370 && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4371 && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4372 && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4374 *new_direct_jump_p = 1;
4375 update_cfg_for_uncondjump (undobuf.other_insn);
4378 combine_successes++;
4379 undo_commit ();
4381 if (added_links_insn
4382 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4383 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4384 return added_links_insn;
4385 else
4386 return newi2pat ? i2 : i3;
4389 /* Undo all the modifications recorded in undobuf. */
4391 static void
4392 undo_all (void)
4394 struct undo *undo, *next;
4396 for (undo = undobuf.undos; undo; undo = next)
4398 next = undo->next;
4399 switch (undo->kind)
4401 case UNDO_RTX:
4402 *undo->where.r = undo->old_contents.r;
4403 break;
4404 case UNDO_INT:
4405 *undo->where.i = undo->old_contents.i;
4406 break;
4407 case UNDO_MODE:
4408 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4409 break;
4410 case UNDO_LINKS:
4411 *undo->where.l = undo->old_contents.l;
4412 break;
4413 default:
4414 gcc_unreachable ();
4417 undo->next = undobuf.frees;
4418 undobuf.frees = undo;
4421 undobuf.undos = 0;
4424 /* We've committed to accepting the changes we made. Move all
4425 of the undos to the free list. */
4427 static void
4428 undo_commit (void)
4430 struct undo *undo, *next;
4432 for (undo = undobuf.undos; undo; undo = next)
4434 next = undo->next;
4435 undo->next = undobuf.frees;
4436 undobuf.frees = undo;
4438 undobuf.undos = 0;
4441 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4442 where we have an arithmetic expression and return that point. LOC will
4443 be inside INSN.
4445 try_combine will call this function to see if an insn can be split into
4446 two insns. */
4448 static rtx *
4449 find_split_point (rtx *loc, rtx insn, bool set_src)
4451 rtx x = *loc;
4452 enum rtx_code code = GET_CODE (x);
4453 rtx *split;
4454 unsigned HOST_WIDE_INT len = 0;
4455 HOST_WIDE_INT pos = 0;
4456 int unsignedp = 0;
4457 rtx inner = NULL_RTX;
4459 /* First special-case some codes. */
4460 switch (code)
4462 case SUBREG:
4463 #ifdef INSN_SCHEDULING
4464 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4465 point. */
4466 if (MEM_P (SUBREG_REG (x)))
4467 return loc;
4468 #endif
4469 return find_split_point (&SUBREG_REG (x), insn, false);
4471 case MEM:
4472 #ifdef HAVE_lo_sum
4473 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4474 using LO_SUM and HIGH. */
4475 if (GET_CODE (XEXP (x, 0)) == CONST
4476 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4478 enum machine_mode address_mode = get_address_mode (x);
4480 SUBST (XEXP (x, 0),
4481 gen_rtx_LO_SUM (address_mode,
4482 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4483 XEXP (x, 0)));
4484 return &XEXP (XEXP (x, 0), 0);
4486 #endif
4488 /* If we have a PLUS whose second operand is a constant and the
4489 address is not valid, perhaps will can split it up using
4490 the machine-specific way to split large constants. We use
4491 the first pseudo-reg (one of the virtual regs) as a placeholder;
4492 it will not remain in the result. */
4493 if (GET_CODE (XEXP (x, 0)) == PLUS
4494 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4495 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4496 MEM_ADDR_SPACE (x)))
4498 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4499 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4500 XEXP (x, 0)),
4501 subst_insn);
4503 /* This should have produced two insns, each of which sets our
4504 placeholder. If the source of the second is a valid address,
4505 we can make put both sources together and make a split point
4506 in the middle. */
4508 if (seq
4509 && NEXT_INSN (seq) != NULL_RTX
4510 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4511 && NONJUMP_INSN_P (seq)
4512 && GET_CODE (PATTERN (seq)) == SET
4513 && SET_DEST (PATTERN (seq)) == reg
4514 && ! reg_mentioned_p (reg,
4515 SET_SRC (PATTERN (seq)))
4516 && NONJUMP_INSN_P (NEXT_INSN (seq))
4517 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4518 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4519 && memory_address_addr_space_p
4520 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4521 MEM_ADDR_SPACE (x)))
4523 rtx src1 = SET_SRC (PATTERN (seq));
4524 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4526 /* Replace the placeholder in SRC2 with SRC1. If we can
4527 find where in SRC2 it was placed, that can become our
4528 split point and we can replace this address with SRC2.
4529 Just try two obvious places. */
4531 src2 = replace_rtx (src2, reg, src1);
4532 split = 0;
4533 if (XEXP (src2, 0) == src1)
4534 split = &XEXP (src2, 0);
4535 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4536 && XEXP (XEXP (src2, 0), 0) == src1)
4537 split = &XEXP (XEXP (src2, 0), 0);
4539 if (split)
4541 SUBST (XEXP (x, 0), src2);
4542 return split;
4546 /* If that didn't work, perhaps the first operand is complex and
4547 needs to be computed separately, so make a split point there.
4548 This will occur on machines that just support REG + CONST
4549 and have a constant moved through some previous computation. */
4551 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4552 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4553 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4554 return &XEXP (XEXP (x, 0), 0);
4557 /* If we have a PLUS whose first operand is complex, try computing it
4558 separately by making a split there. */
4559 if (GET_CODE (XEXP (x, 0)) == PLUS
4560 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4561 MEM_ADDR_SPACE (x))
4562 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4563 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4564 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4565 return &XEXP (XEXP (x, 0), 0);
4566 break;
4568 case SET:
4569 #ifdef HAVE_cc0
4570 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4571 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4572 we need to put the operand into a register. So split at that
4573 point. */
4575 if (SET_DEST (x) == cc0_rtx
4576 && GET_CODE (SET_SRC (x)) != COMPARE
4577 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4578 && !OBJECT_P (SET_SRC (x))
4579 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4580 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4581 return &SET_SRC (x);
4582 #endif
4584 /* See if we can split SET_SRC as it stands. */
4585 split = find_split_point (&SET_SRC (x), insn, true);
4586 if (split && split != &SET_SRC (x))
4587 return split;
4589 /* See if we can split SET_DEST as it stands. */
4590 split = find_split_point (&SET_DEST (x), insn, false);
4591 if (split && split != &SET_DEST (x))
4592 return split;
4594 /* See if this is a bitfield assignment with everything constant. If
4595 so, this is an IOR of an AND, so split it into that. */
4596 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4597 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x), 0)))
4598 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4599 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4600 && CONST_INT_P (SET_SRC (x))
4601 && ((INTVAL (XEXP (SET_DEST (x), 1))
4602 + INTVAL (XEXP (SET_DEST (x), 2)))
4603 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0))))
4604 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4606 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4607 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4608 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4609 rtx dest = XEXP (SET_DEST (x), 0);
4610 enum machine_mode mode = GET_MODE (dest);
4611 unsigned HOST_WIDE_INT mask
4612 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4613 rtx or_mask;
4615 if (BITS_BIG_ENDIAN)
4616 pos = GET_MODE_PRECISION (mode) - len - pos;
4618 or_mask = gen_int_mode (src << pos, mode);
4619 if (src == mask)
4620 SUBST (SET_SRC (x),
4621 simplify_gen_binary (IOR, mode, dest, or_mask));
4622 else
4624 rtx negmask = gen_int_mode (~(mask << pos), mode);
4625 SUBST (SET_SRC (x),
4626 simplify_gen_binary (IOR, mode,
4627 simplify_gen_binary (AND, mode,
4628 dest, negmask),
4629 or_mask));
4632 SUBST (SET_DEST (x), dest);
4634 split = find_split_point (&SET_SRC (x), insn, true);
4635 if (split && split != &SET_SRC (x))
4636 return split;
4639 /* Otherwise, see if this is an operation that we can split into two.
4640 If so, try to split that. */
4641 code = GET_CODE (SET_SRC (x));
4643 switch (code)
4645 case AND:
4646 /* If we are AND'ing with a large constant that is only a single
4647 bit and the result is only being used in a context where we
4648 need to know if it is zero or nonzero, replace it with a bit
4649 extraction. This will avoid the large constant, which might
4650 have taken more than one insn to make. If the constant were
4651 not a valid argument to the AND but took only one insn to make,
4652 this is no worse, but if it took more than one insn, it will
4653 be better. */
4655 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4656 && REG_P (XEXP (SET_SRC (x), 0))
4657 && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4658 && REG_P (SET_DEST (x))
4659 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4660 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4661 && XEXP (*split, 0) == SET_DEST (x)
4662 && XEXP (*split, 1) == const0_rtx)
4664 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4665 XEXP (SET_SRC (x), 0),
4666 pos, NULL_RTX, 1, 1, 0, 0);
4667 if (extraction != 0)
4669 SUBST (SET_SRC (x), extraction);
4670 return find_split_point (loc, insn, false);
4673 break;
4675 case NE:
4676 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4677 is known to be on, this can be converted into a NEG of a shift. */
4678 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4679 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4680 && 1 <= (pos = exact_log2
4681 (nonzero_bits (XEXP (SET_SRC (x), 0),
4682 GET_MODE (XEXP (SET_SRC (x), 0))))))
4684 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4686 SUBST (SET_SRC (x),
4687 gen_rtx_NEG (mode,
4688 gen_rtx_LSHIFTRT (mode,
4689 XEXP (SET_SRC (x), 0),
4690 GEN_INT (pos))));
4692 split = find_split_point (&SET_SRC (x), insn, true);
4693 if (split && split != &SET_SRC (x))
4694 return split;
4696 break;
4698 case SIGN_EXTEND:
4699 inner = XEXP (SET_SRC (x), 0);
4701 /* We can't optimize if either mode is a partial integer
4702 mode as we don't know how many bits are significant
4703 in those modes. */
4704 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4705 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4706 break;
4708 pos = 0;
4709 len = GET_MODE_PRECISION (GET_MODE (inner));
4710 unsignedp = 0;
4711 break;
4713 case SIGN_EXTRACT:
4714 case ZERO_EXTRACT:
4715 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4716 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4718 inner = XEXP (SET_SRC (x), 0);
4719 len = INTVAL (XEXP (SET_SRC (x), 1));
4720 pos = INTVAL (XEXP (SET_SRC (x), 2));
4722 if (BITS_BIG_ENDIAN)
4723 pos = GET_MODE_PRECISION (GET_MODE (inner)) - len - pos;
4724 unsignedp = (code == ZERO_EXTRACT);
4726 break;
4728 default:
4729 break;
4732 if (len && pos >= 0
4733 && pos + len <= GET_MODE_PRECISION (GET_MODE (inner)))
4735 enum machine_mode mode = GET_MODE (SET_SRC (x));
4737 /* For unsigned, we have a choice of a shift followed by an
4738 AND or two shifts. Use two shifts for field sizes where the
4739 constant might be too large. We assume here that we can
4740 always at least get 8-bit constants in an AND insn, which is
4741 true for every current RISC. */
4743 if (unsignedp && len <= 8)
4745 unsigned HOST_WIDE_INT mask
4746 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4747 SUBST (SET_SRC (x),
4748 gen_rtx_AND (mode,
4749 gen_rtx_LSHIFTRT
4750 (mode, gen_lowpart (mode, inner),
4751 GEN_INT (pos)),
4752 gen_int_mode (mask, mode)));
4754 split = find_split_point (&SET_SRC (x), insn, true);
4755 if (split && split != &SET_SRC (x))
4756 return split;
4758 else
4760 SUBST (SET_SRC (x),
4761 gen_rtx_fmt_ee
4762 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4763 gen_rtx_ASHIFT (mode,
4764 gen_lowpart (mode, inner),
4765 GEN_INT (GET_MODE_PRECISION (mode)
4766 - len - pos)),
4767 GEN_INT (GET_MODE_PRECISION (mode) - len)));
4769 split = find_split_point (&SET_SRC (x), insn, true);
4770 if (split && split != &SET_SRC (x))
4771 return split;
4775 /* See if this is a simple operation with a constant as the second
4776 operand. It might be that this constant is out of range and hence
4777 could be used as a split point. */
4778 if (BINARY_P (SET_SRC (x))
4779 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4780 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4781 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4782 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4783 return &XEXP (SET_SRC (x), 1);
4785 /* Finally, see if this is a simple operation with its first operand
4786 not in a register. The operation might require this operand in a
4787 register, so return it as a split point. We can always do this
4788 because if the first operand were another operation, we would have
4789 already found it as a split point. */
4790 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4791 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4792 return &XEXP (SET_SRC (x), 0);
4794 return 0;
4796 case AND:
4797 case IOR:
4798 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4799 it is better to write this as (not (ior A B)) so we can split it.
4800 Similarly for IOR. */
4801 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4803 SUBST (*loc,
4804 gen_rtx_NOT (GET_MODE (x),
4805 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4806 GET_MODE (x),
4807 XEXP (XEXP (x, 0), 0),
4808 XEXP (XEXP (x, 1), 0))));
4809 return find_split_point (loc, insn, set_src);
4812 /* Many RISC machines have a large set of logical insns. If the
4813 second operand is a NOT, put it first so we will try to split the
4814 other operand first. */
4815 if (GET_CODE (XEXP (x, 1)) == NOT)
4817 rtx tem = XEXP (x, 0);
4818 SUBST (XEXP (x, 0), XEXP (x, 1));
4819 SUBST (XEXP (x, 1), tem);
4821 break;
4823 case PLUS:
4824 case MINUS:
4825 /* Canonicalization can produce (minus A (mult B C)), where C is a
4826 constant. It may be better to try splitting (plus (mult B -C) A)
4827 instead if this isn't a multiply by a power of two. */
4828 if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4829 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4830 && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4832 enum machine_mode mode = GET_MODE (x);
4833 unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4834 HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4835 SUBST (*loc, gen_rtx_PLUS (mode,
4836 gen_rtx_MULT (mode,
4837 XEXP (XEXP (x, 1), 0),
4838 gen_int_mode (other_int,
4839 mode)),
4840 XEXP (x, 0)));
4841 return find_split_point (loc, insn, set_src);
4844 /* Split at a multiply-accumulate instruction. However if this is
4845 the SET_SRC, we likely do not have such an instruction and it's
4846 worthless to try this split. */
4847 if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4848 return loc;
4850 default:
4851 break;
4854 /* Otherwise, select our actions depending on our rtx class. */
4855 switch (GET_RTX_CLASS (code))
4857 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4858 case RTX_TERNARY:
4859 split = find_split_point (&XEXP (x, 2), insn, false);
4860 if (split)
4861 return split;
4862 /* ... fall through ... */
4863 case RTX_BIN_ARITH:
4864 case RTX_COMM_ARITH:
4865 case RTX_COMPARE:
4866 case RTX_COMM_COMPARE:
4867 split = find_split_point (&XEXP (x, 1), insn, false);
4868 if (split)
4869 return split;
4870 /* ... fall through ... */
4871 case RTX_UNARY:
4872 /* Some machines have (and (shift ...) ...) insns. If X is not
4873 an AND, but XEXP (X, 0) is, use it as our split point. */
4874 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4875 return &XEXP (x, 0);
4877 split = find_split_point (&XEXP (x, 0), insn, false);
4878 if (split)
4879 return split;
4880 return loc;
4882 default:
4883 /* Otherwise, we don't have a split point. */
4884 return 0;
4888 /* Throughout X, replace FROM with TO, and return the result.
4889 The result is TO if X is FROM;
4890 otherwise the result is X, but its contents may have been modified.
4891 If they were modified, a record was made in undobuf so that
4892 undo_all will (among other things) return X to its original state.
4894 If the number of changes necessary is too much to record to undo,
4895 the excess changes are not made, so the result is invalid.
4896 The changes already made can still be undone.
4897 undobuf.num_undo is incremented for such changes, so by testing that
4898 the caller can tell whether the result is valid.
4900 `n_occurrences' is incremented each time FROM is replaced.
4902 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4904 IN_COND is nonzero if we are at the top level of a condition.
4906 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4907 by copying if `n_occurrences' is nonzero. */
4909 static rtx
4910 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
4912 enum rtx_code code = GET_CODE (x);
4913 enum machine_mode op0_mode = VOIDmode;
4914 const char *fmt;
4915 int len, i;
4916 rtx new_rtx;
4918 /* Two expressions are equal if they are identical copies of a shared
4919 RTX or if they are both registers with the same register number
4920 and mode. */
4922 #define COMBINE_RTX_EQUAL_P(X,Y) \
4923 ((X) == (Y) \
4924 || (REG_P (X) && REG_P (Y) \
4925 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4927 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4929 n_occurrences++;
4930 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4933 /* If X and FROM are the same register but different modes, they
4934 will not have been seen as equal above. However, the log links code
4935 will make a LOG_LINKS entry for that case. If we do nothing, we
4936 will try to rerecognize our original insn and, when it succeeds,
4937 we will delete the feeding insn, which is incorrect.
4939 So force this insn not to match in this (rare) case. */
4940 if (! in_dest && code == REG && REG_P (from)
4941 && reg_overlap_mentioned_p (x, from))
4942 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4944 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4945 of which may contain things that can be combined. */
4946 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4947 return x;
4949 /* It is possible to have a subexpression appear twice in the insn.
4950 Suppose that FROM is a register that appears within TO.
4951 Then, after that subexpression has been scanned once by `subst',
4952 the second time it is scanned, TO may be found. If we were
4953 to scan TO here, we would find FROM within it and create a
4954 self-referent rtl structure which is completely wrong. */
4955 if (COMBINE_RTX_EQUAL_P (x, to))
4956 return to;
4958 /* Parallel asm_operands need special attention because all of the
4959 inputs are shared across the arms. Furthermore, unsharing the
4960 rtl results in recognition failures. Failure to handle this case
4961 specially can result in circular rtl.
4963 Solve this by doing a normal pass across the first entry of the
4964 parallel, and only processing the SET_DESTs of the subsequent
4965 entries. Ug. */
4967 if (code == PARALLEL
4968 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4969 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4971 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
4973 /* If this substitution failed, this whole thing fails. */
4974 if (GET_CODE (new_rtx) == CLOBBER
4975 && XEXP (new_rtx, 0) == const0_rtx)
4976 return new_rtx;
4978 SUBST (XVECEXP (x, 0, 0), new_rtx);
4980 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4982 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4984 if (!REG_P (dest)
4985 && GET_CODE (dest) != CC0
4986 && GET_CODE (dest) != PC)
4988 new_rtx = subst (dest, from, to, 0, 0, unique_copy);
4990 /* If this substitution failed, this whole thing fails. */
4991 if (GET_CODE (new_rtx) == CLOBBER
4992 && XEXP (new_rtx, 0) == const0_rtx)
4993 return new_rtx;
4995 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4999 else
5001 len = GET_RTX_LENGTH (code);
5002 fmt = GET_RTX_FORMAT (code);
5004 /* We don't need to process a SET_DEST that is a register, CC0,
5005 or PC, so set up to skip this common case. All other cases
5006 where we want to suppress replacing something inside a
5007 SET_SRC are handled via the IN_DEST operand. */
5008 if (code == SET
5009 && (REG_P (SET_DEST (x))
5010 || GET_CODE (SET_DEST (x)) == CC0
5011 || GET_CODE (SET_DEST (x)) == PC))
5012 fmt = "ie";
5014 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5015 constant. */
5016 if (fmt[0] == 'e')
5017 op0_mode = GET_MODE (XEXP (x, 0));
5019 for (i = 0; i < len; i++)
5021 if (fmt[i] == 'E')
5023 int j;
5024 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5026 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5028 new_rtx = (unique_copy && n_occurrences
5029 ? copy_rtx (to) : to);
5030 n_occurrences++;
5032 else
5034 new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5035 unique_copy);
5037 /* If this substitution failed, this whole thing
5038 fails. */
5039 if (GET_CODE (new_rtx) == CLOBBER
5040 && XEXP (new_rtx, 0) == const0_rtx)
5041 return new_rtx;
5044 SUBST (XVECEXP (x, i, j), new_rtx);
5047 else if (fmt[i] == 'e')
5049 /* If this is a register being set, ignore it. */
5050 new_rtx = XEXP (x, i);
5051 if (in_dest
5052 && i == 0
5053 && (((code == SUBREG || code == ZERO_EXTRACT)
5054 && REG_P (new_rtx))
5055 || code == STRICT_LOW_PART))
5058 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5060 /* In general, don't install a subreg involving two
5061 modes not tieable. It can worsen register
5062 allocation, and can even make invalid reload
5063 insns, since the reg inside may need to be copied
5064 from in the outside mode, and that may be invalid
5065 if it is an fp reg copied in integer mode.
5067 We allow two exceptions to this: It is valid if
5068 it is inside another SUBREG and the mode of that
5069 SUBREG and the mode of the inside of TO is
5070 tieable and it is valid if X is a SET that copies
5071 FROM to CC0. */
5073 if (GET_CODE (to) == SUBREG
5074 && ! MODES_TIEABLE_P (GET_MODE (to),
5075 GET_MODE (SUBREG_REG (to)))
5076 && ! (code == SUBREG
5077 && MODES_TIEABLE_P (GET_MODE (x),
5078 GET_MODE (SUBREG_REG (to))))
5079 #ifdef HAVE_cc0
5080 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5081 #endif
5083 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5085 #ifdef CANNOT_CHANGE_MODE_CLASS
5086 if (code == SUBREG
5087 && REG_P (to)
5088 && REGNO (to) < FIRST_PSEUDO_REGISTER
5089 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5090 GET_MODE (to),
5091 GET_MODE (x)))
5092 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5093 #endif
5095 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5096 n_occurrences++;
5098 else
5099 /* If we are in a SET_DEST, suppress most cases unless we
5100 have gone inside a MEM, in which case we want to
5101 simplify the address. We assume here that things that
5102 are actually part of the destination have their inner
5103 parts in the first expression. This is true for SUBREG,
5104 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5105 things aside from REG and MEM that should appear in a
5106 SET_DEST. */
5107 new_rtx = subst (XEXP (x, i), from, to,
5108 (((in_dest
5109 && (code == SUBREG || code == STRICT_LOW_PART
5110 || code == ZERO_EXTRACT))
5111 || code == SET)
5112 && i == 0),
5113 code == IF_THEN_ELSE && i == 0,
5114 unique_copy);
5116 /* If we found that we will have to reject this combination,
5117 indicate that by returning the CLOBBER ourselves, rather than
5118 an expression containing it. This will speed things up as
5119 well as prevent accidents where two CLOBBERs are considered
5120 to be equal, thus producing an incorrect simplification. */
5122 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5123 return new_rtx;
5125 if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
5127 enum machine_mode mode = GET_MODE (x);
5129 x = simplify_subreg (GET_MODE (x), new_rtx,
5130 GET_MODE (SUBREG_REG (x)),
5131 SUBREG_BYTE (x));
5132 if (! x)
5133 x = gen_rtx_CLOBBER (mode, const0_rtx);
5135 else if (CONST_INT_P (new_rtx)
5136 && GET_CODE (x) == ZERO_EXTEND)
5138 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5139 new_rtx, GET_MODE (XEXP (x, 0)));
5140 gcc_assert (x);
5142 else
5143 SUBST (XEXP (x, i), new_rtx);
5148 /* Check if we are loading something from the constant pool via float
5149 extension; in this case we would undo compress_float_constant
5150 optimization and degenerate constant load to an immediate value. */
5151 if (GET_CODE (x) == FLOAT_EXTEND
5152 && MEM_P (XEXP (x, 0))
5153 && MEM_READONLY_P (XEXP (x, 0)))
5155 rtx tmp = avoid_constant_pool_reference (x);
5156 if (x != tmp)
5157 return x;
5160 /* Try to simplify X. If the simplification changed the code, it is likely
5161 that further simplification will help, so loop, but limit the number
5162 of repetitions that will be performed. */
5164 for (i = 0; i < 4; i++)
5166 /* If X is sufficiently simple, don't bother trying to do anything
5167 with it. */
5168 if (code != CONST_INT && code != REG && code != CLOBBER)
5169 x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5171 if (GET_CODE (x) == code)
5172 break;
5174 code = GET_CODE (x);
5176 /* We no longer know the original mode of operand 0 since we
5177 have changed the form of X) */
5178 op0_mode = VOIDmode;
5181 return x;
5184 /* Simplify X, a piece of RTL. We just operate on the expression at the
5185 outer level; call `subst' to simplify recursively. Return the new
5186 expression.
5188 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5189 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5190 of a condition. */
5192 static rtx
5193 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest,
5194 int in_cond)
5196 enum rtx_code code = GET_CODE (x);
5197 enum machine_mode mode = GET_MODE (x);
5198 rtx temp;
5199 int i;
5201 /* If this is a commutative operation, put a constant last and a complex
5202 expression first. We don't need to do this for comparisons here. */
5203 if (COMMUTATIVE_ARITH_P (x)
5204 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5206 temp = XEXP (x, 0);
5207 SUBST (XEXP (x, 0), XEXP (x, 1));
5208 SUBST (XEXP (x, 1), temp);
5211 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5212 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5213 things. Check for cases where both arms are testing the same
5214 condition.
5216 Don't do anything if all operands are very simple. */
5218 if ((BINARY_P (x)
5219 && ((!OBJECT_P (XEXP (x, 0))
5220 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5221 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5222 || (!OBJECT_P (XEXP (x, 1))
5223 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5224 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5225 || (UNARY_P (x)
5226 && (!OBJECT_P (XEXP (x, 0))
5227 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5228 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5230 rtx cond, true_rtx, false_rtx;
5232 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5233 if (cond != 0
5234 /* If everything is a comparison, what we have is highly unlikely
5235 to be simpler, so don't use it. */
5236 && ! (COMPARISON_P (x)
5237 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5239 rtx cop1 = const0_rtx;
5240 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5242 if (cond_code == NE && COMPARISON_P (cond))
5243 return x;
5245 /* Simplify the alternative arms; this may collapse the true and
5246 false arms to store-flag values. Be careful to use copy_rtx
5247 here since true_rtx or false_rtx might share RTL with x as a
5248 result of the if_then_else_cond call above. */
5249 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5250 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5252 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5253 is unlikely to be simpler. */
5254 if (general_operand (true_rtx, VOIDmode)
5255 && general_operand (false_rtx, VOIDmode))
5257 enum rtx_code reversed;
5259 /* Restarting if we generate a store-flag expression will cause
5260 us to loop. Just drop through in this case. */
5262 /* If the result values are STORE_FLAG_VALUE and zero, we can
5263 just make the comparison operation. */
5264 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5265 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5266 cond, cop1);
5267 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5268 && ((reversed = reversed_comparison_code_parts
5269 (cond_code, cond, cop1, NULL))
5270 != UNKNOWN))
5271 x = simplify_gen_relational (reversed, mode, VOIDmode,
5272 cond, cop1);
5274 /* Likewise, we can make the negate of a comparison operation
5275 if the result values are - STORE_FLAG_VALUE and zero. */
5276 else if (CONST_INT_P (true_rtx)
5277 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5278 && false_rtx == const0_rtx)
5279 x = simplify_gen_unary (NEG, mode,
5280 simplify_gen_relational (cond_code,
5281 mode, VOIDmode,
5282 cond, cop1),
5283 mode);
5284 else if (CONST_INT_P (false_rtx)
5285 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5286 && true_rtx == const0_rtx
5287 && ((reversed = reversed_comparison_code_parts
5288 (cond_code, cond, cop1, NULL))
5289 != UNKNOWN))
5290 x = simplify_gen_unary (NEG, mode,
5291 simplify_gen_relational (reversed,
5292 mode, VOIDmode,
5293 cond, cop1),
5294 mode);
5295 else
5296 return gen_rtx_IF_THEN_ELSE (mode,
5297 simplify_gen_relational (cond_code,
5298 mode,
5299 VOIDmode,
5300 cond,
5301 cop1),
5302 true_rtx, false_rtx);
5304 code = GET_CODE (x);
5305 op0_mode = VOIDmode;
5310 /* Try to fold this expression in case we have constants that weren't
5311 present before. */
5312 temp = 0;
5313 switch (GET_RTX_CLASS (code))
5315 case RTX_UNARY:
5316 if (op0_mode == VOIDmode)
5317 op0_mode = GET_MODE (XEXP (x, 0));
5318 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5319 break;
5320 case RTX_COMPARE:
5321 case RTX_COMM_COMPARE:
5323 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5324 if (cmp_mode == VOIDmode)
5326 cmp_mode = GET_MODE (XEXP (x, 1));
5327 if (cmp_mode == VOIDmode)
5328 cmp_mode = op0_mode;
5330 temp = simplify_relational_operation (code, mode, cmp_mode,
5331 XEXP (x, 0), XEXP (x, 1));
5333 break;
5334 case RTX_COMM_ARITH:
5335 case RTX_BIN_ARITH:
5336 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5337 break;
5338 case RTX_BITFIELD_OPS:
5339 case RTX_TERNARY:
5340 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5341 XEXP (x, 1), XEXP (x, 2));
5342 break;
5343 default:
5344 break;
5347 if (temp)
5349 x = temp;
5350 code = GET_CODE (temp);
5351 op0_mode = VOIDmode;
5352 mode = GET_MODE (temp);
5355 /* First see if we can apply the inverse distributive law. */
5356 if (code == PLUS || code == MINUS
5357 || code == AND || code == IOR || code == XOR)
5359 x = apply_distributive_law (x);
5360 code = GET_CODE (x);
5361 op0_mode = VOIDmode;
5364 /* If CODE is an associative operation not otherwise handled, see if we
5365 can associate some operands. This can win if they are constants or
5366 if they are logically related (i.e. (a & b) & a). */
5367 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5368 || code == AND || code == IOR || code == XOR
5369 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5370 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5371 || (flag_associative_math && FLOAT_MODE_P (mode))))
5373 if (GET_CODE (XEXP (x, 0)) == code)
5375 rtx other = XEXP (XEXP (x, 0), 0);
5376 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5377 rtx inner_op1 = XEXP (x, 1);
5378 rtx inner;
5380 /* Make sure we pass the constant operand if any as the second
5381 one if this is a commutative operation. */
5382 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5384 rtx tem = inner_op0;
5385 inner_op0 = inner_op1;
5386 inner_op1 = tem;
5388 inner = simplify_binary_operation (code == MINUS ? PLUS
5389 : code == DIV ? MULT
5390 : code,
5391 mode, inner_op0, inner_op1);
5393 /* For commutative operations, try the other pair if that one
5394 didn't simplify. */
5395 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5397 other = XEXP (XEXP (x, 0), 1);
5398 inner = simplify_binary_operation (code, mode,
5399 XEXP (XEXP (x, 0), 0),
5400 XEXP (x, 1));
5403 if (inner)
5404 return simplify_gen_binary (code, mode, other, inner);
5408 /* A little bit of algebraic simplification here. */
5409 switch (code)
5411 case MEM:
5412 /* Ensure that our address has any ASHIFTs converted to MULT in case
5413 address-recognizing predicates are called later. */
5414 temp = make_compound_operation (XEXP (x, 0), MEM);
5415 SUBST (XEXP (x, 0), temp);
5416 break;
5418 case SUBREG:
5419 if (op0_mode == VOIDmode)
5420 op0_mode = GET_MODE (SUBREG_REG (x));
5422 /* See if this can be moved to simplify_subreg. */
5423 if (CONSTANT_P (SUBREG_REG (x))
5424 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5425 /* Don't call gen_lowpart if the inner mode
5426 is VOIDmode and we cannot simplify it, as SUBREG without
5427 inner mode is invalid. */
5428 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5429 || gen_lowpart_common (mode, SUBREG_REG (x))))
5430 return gen_lowpart (mode, SUBREG_REG (x));
5432 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5433 break;
5435 rtx temp;
5436 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5437 SUBREG_BYTE (x));
5438 if (temp)
5439 return temp;
5441 /* If op is known to have all lower bits zero, the result is zero. */
5442 if (!in_dest
5443 && SCALAR_INT_MODE_P (mode)
5444 && SCALAR_INT_MODE_P (op0_mode)
5445 && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (op0_mode)
5446 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5447 && HWI_COMPUTABLE_MODE_P (op0_mode)
5448 && (nonzero_bits (SUBREG_REG (x), op0_mode)
5449 & GET_MODE_MASK (mode)) == 0)
5450 return CONST0_RTX (mode);
5453 /* Don't change the mode of the MEM if that would change the meaning
5454 of the address. */
5455 if (MEM_P (SUBREG_REG (x))
5456 && (MEM_VOLATILE_P (SUBREG_REG (x))
5457 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
5458 MEM_ADDR_SPACE (SUBREG_REG (x)))))
5459 return gen_rtx_CLOBBER (mode, const0_rtx);
5461 /* Note that we cannot do any narrowing for non-constants since
5462 we might have been counting on using the fact that some bits were
5463 zero. We now do this in the SET. */
5465 break;
5467 case NEG:
5468 temp = expand_compound_operation (XEXP (x, 0));
5470 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5471 replaced by (lshiftrt X C). This will convert
5472 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5474 if (GET_CODE (temp) == ASHIFTRT
5475 && CONST_INT_P (XEXP (temp, 1))
5476 && INTVAL (XEXP (temp, 1)) == GET_MODE_PRECISION (mode) - 1)
5477 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5478 INTVAL (XEXP (temp, 1)));
5480 /* If X has only a single bit that might be nonzero, say, bit I, convert
5481 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5482 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5483 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5484 or a SUBREG of one since we'd be making the expression more
5485 complex if it was just a register. */
5487 if (!REG_P (temp)
5488 && ! (GET_CODE (temp) == SUBREG
5489 && REG_P (SUBREG_REG (temp)))
5490 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5492 rtx temp1 = simplify_shift_const
5493 (NULL_RTX, ASHIFTRT, mode,
5494 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5495 GET_MODE_PRECISION (mode) - 1 - i),
5496 GET_MODE_PRECISION (mode) - 1 - i);
5498 /* If all we did was surround TEMP with the two shifts, we
5499 haven't improved anything, so don't use it. Otherwise,
5500 we are better off with TEMP1. */
5501 if (GET_CODE (temp1) != ASHIFTRT
5502 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5503 || XEXP (XEXP (temp1, 0), 0) != temp)
5504 return temp1;
5506 break;
5508 case TRUNCATE:
5509 /* We can't handle truncation to a partial integer mode here
5510 because we don't know the real bitsize of the partial
5511 integer mode. */
5512 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5513 break;
5515 if (HWI_COMPUTABLE_MODE_P (mode))
5516 SUBST (XEXP (x, 0),
5517 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5518 GET_MODE_MASK (mode), 0));
5520 /* We can truncate a constant value and return it. */
5521 if (CONST_INT_P (XEXP (x, 0)))
5522 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5524 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5525 whose value is a comparison can be replaced with a subreg if
5526 STORE_FLAG_VALUE permits. */
5527 if (HWI_COMPUTABLE_MODE_P (mode)
5528 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5529 && (temp = get_last_value (XEXP (x, 0)))
5530 && COMPARISON_P (temp))
5531 return gen_lowpart (mode, XEXP (x, 0));
5532 break;
5534 case CONST:
5535 /* (const (const X)) can become (const X). Do it this way rather than
5536 returning the inner CONST since CONST can be shared with a
5537 REG_EQUAL note. */
5538 if (GET_CODE (XEXP (x, 0)) == CONST)
5539 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5540 break;
5542 #ifdef HAVE_lo_sum
5543 case LO_SUM:
5544 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5545 can add in an offset. find_split_point will split this address up
5546 again if it doesn't match. */
5547 if (GET_CODE (XEXP (x, 0)) == HIGH
5548 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5549 return XEXP (x, 1);
5550 break;
5551 #endif
5553 case PLUS:
5554 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5555 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5556 bit-field and can be replaced by either a sign_extend or a
5557 sign_extract. The `and' may be a zero_extend and the two
5558 <c>, -<c> constants may be reversed. */
5559 if (GET_CODE (XEXP (x, 0)) == XOR
5560 && CONST_INT_P (XEXP (x, 1))
5561 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5562 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5563 && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5564 || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5565 && HWI_COMPUTABLE_MODE_P (mode)
5566 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5567 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5568 && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5569 == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5570 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5571 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5572 == (unsigned int) i + 1))))
5573 return simplify_shift_const
5574 (NULL_RTX, ASHIFTRT, mode,
5575 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5576 XEXP (XEXP (XEXP (x, 0), 0), 0),
5577 GET_MODE_PRECISION (mode) - (i + 1)),
5578 GET_MODE_PRECISION (mode) - (i + 1));
5580 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5581 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5582 the bitsize of the mode - 1. This allows simplification of
5583 "a = (b & 8) == 0;" */
5584 if (XEXP (x, 1) == constm1_rtx
5585 && !REG_P (XEXP (x, 0))
5586 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5587 && REG_P (SUBREG_REG (XEXP (x, 0))))
5588 && nonzero_bits (XEXP (x, 0), mode) == 1)
5589 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5590 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5591 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5592 GET_MODE_PRECISION (mode) - 1),
5593 GET_MODE_PRECISION (mode) - 1);
5595 /* If we are adding two things that have no bits in common, convert
5596 the addition into an IOR. This will often be further simplified,
5597 for example in cases like ((a & 1) + (a & 2)), which can
5598 become a & 3. */
5600 if (HWI_COMPUTABLE_MODE_P (mode)
5601 && (nonzero_bits (XEXP (x, 0), mode)
5602 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5604 /* Try to simplify the expression further. */
5605 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5606 temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
5608 /* If we could, great. If not, do not go ahead with the IOR
5609 replacement, since PLUS appears in many special purpose
5610 address arithmetic instructions. */
5611 if (GET_CODE (temp) != CLOBBER
5612 && (GET_CODE (temp) != IOR
5613 || ((XEXP (temp, 0) != XEXP (x, 0)
5614 || XEXP (temp, 1) != XEXP (x, 1))
5615 && (XEXP (temp, 0) != XEXP (x, 1)
5616 || XEXP (temp, 1) != XEXP (x, 0)))))
5617 return temp;
5619 break;
5621 case MINUS:
5622 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5623 (and <foo> (const_int pow2-1)) */
5624 if (GET_CODE (XEXP (x, 1)) == AND
5625 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5626 && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5627 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5628 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5629 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5630 break;
5632 case MULT:
5633 /* If we have (mult (plus A B) C), apply the distributive law and then
5634 the inverse distributive law to see if things simplify. This
5635 occurs mostly in addresses, often when unrolling loops. */
5637 if (GET_CODE (XEXP (x, 0)) == PLUS)
5639 rtx result = distribute_and_simplify_rtx (x, 0);
5640 if (result)
5641 return result;
5644 /* Try simplify a*(b/c) as (a*b)/c. */
5645 if (FLOAT_MODE_P (mode) && flag_associative_math
5646 && GET_CODE (XEXP (x, 0)) == DIV)
5648 rtx tem = simplify_binary_operation (MULT, mode,
5649 XEXP (XEXP (x, 0), 0),
5650 XEXP (x, 1));
5651 if (tem)
5652 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5654 break;
5656 case UDIV:
5657 /* If this is a divide by a power of two, treat it as a shift if
5658 its first operand is a shift. */
5659 if (CONST_INT_P (XEXP (x, 1))
5660 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5661 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5662 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5663 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5664 || GET_CODE (XEXP (x, 0)) == ROTATE
5665 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5666 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5667 break;
5669 case EQ: case NE:
5670 case GT: case GTU: case GE: case GEU:
5671 case LT: case LTU: case LE: case LEU:
5672 case UNEQ: case LTGT:
5673 case UNGT: case UNGE:
5674 case UNLT: case UNLE:
5675 case UNORDERED: case ORDERED:
5676 /* If the first operand is a condition code, we can't do anything
5677 with it. */
5678 if (GET_CODE (XEXP (x, 0)) == COMPARE
5679 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5680 && ! CC0_P (XEXP (x, 0))))
5682 rtx op0 = XEXP (x, 0);
5683 rtx op1 = XEXP (x, 1);
5684 enum rtx_code new_code;
5686 if (GET_CODE (op0) == COMPARE)
5687 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5689 /* Simplify our comparison, if possible. */
5690 new_code = simplify_comparison (code, &op0, &op1);
5692 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5693 if only the low-order bit is possibly nonzero in X (such as when
5694 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5695 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5696 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5697 (plus X 1).
5699 Remove any ZERO_EXTRACT we made when thinking this was a
5700 comparison. It may now be simpler to use, e.g., an AND. If a
5701 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5702 the call to make_compound_operation in the SET case.
5704 Don't apply these optimizations if the caller would
5705 prefer a comparison rather than a value.
5706 E.g., for the condition in an IF_THEN_ELSE most targets need
5707 an explicit comparison. */
5709 if (in_cond)
5712 else if (STORE_FLAG_VALUE == 1
5713 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5714 && op1 == const0_rtx
5715 && mode == GET_MODE (op0)
5716 && nonzero_bits (op0, mode) == 1)
5717 return gen_lowpart (mode,
5718 expand_compound_operation (op0));
5720 else if (STORE_FLAG_VALUE == 1
5721 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5722 && op1 == const0_rtx
5723 && mode == GET_MODE (op0)
5724 && (num_sign_bit_copies (op0, mode)
5725 == GET_MODE_PRECISION (mode)))
5727 op0 = expand_compound_operation (op0);
5728 return simplify_gen_unary (NEG, mode,
5729 gen_lowpart (mode, op0),
5730 mode);
5733 else if (STORE_FLAG_VALUE == 1
5734 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5735 && op1 == const0_rtx
5736 && mode == GET_MODE (op0)
5737 && nonzero_bits (op0, mode) == 1)
5739 op0 = expand_compound_operation (op0);
5740 return simplify_gen_binary (XOR, mode,
5741 gen_lowpart (mode, op0),
5742 const1_rtx);
5745 else if (STORE_FLAG_VALUE == 1
5746 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5747 && op1 == const0_rtx
5748 && mode == GET_MODE (op0)
5749 && (num_sign_bit_copies (op0, mode)
5750 == GET_MODE_PRECISION (mode)))
5752 op0 = expand_compound_operation (op0);
5753 return plus_constant (mode, gen_lowpart (mode, op0), 1);
5756 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5757 those above. */
5758 if (in_cond)
5761 else if (STORE_FLAG_VALUE == -1
5762 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5763 && op1 == const0_rtx
5764 && (num_sign_bit_copies (op0, mode)
5765 == GET_MODE_PRECISION (mode)))
5766 return gen_lowpart (mode,
5767 expand_compound_operation (op0));
5769 else if (STORE_FLAG_VALUE == -1
5770 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5771 && op1 == const0_rtx
5772 && mode == GET_MODE (op0)
5773 && nonzero_bits (op0, mode) == 1)
5775 op0 = expand_compound_operation (op0);
5776 return simplify_gen_unary (NEG, mode,
5777 gen_lowpart (mode, op0),
5778 mode);
5781 else if (STORE_FLAG_VALUE == -1
5782 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5783 && op1 == const0_rtx
5784 && mode == GET_MODE (op0)
5785 && (num_sign_bit_copies (op0, mode)
5786 == GET_MODE_PRECISION (mode)))
5788 op0 = expand_compound_operation (op0);
5789 return simplify_gen_unary (NOT, mode,
5790 gen_lowpart (mode, op0),
5791 mode);
5794 /* If X is 0/1, (eq X 0) is X-1. */
5795 else if (STORE_FLAG_VALUE == -1
5796 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5797 && op1 == const0_rtx
5798 && mode == GET_MODE (op0)
5799 && nonzero_bits (op0, mode) == 1)
5801 op0 = expand_compound_operation (op0);
5802 return plus_constant (mode, gen_lowpart (mode, op0), -1);
5805 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5806 one bit that might be nonzero, we can convert (ne x 0) to
5807 (ashift x c) where C puts the bit in the sign bit. Remove any
5808 AND with STORE_FLAG_VALUE when we are done, since we are only
5809 going to test the sign bit. */
5810 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5811 && HWI_COMPUTABLE_MODE_P (mode)
5812 && val_signbit_p (mode, STORE_FLAG_VALUE)
5813 && op1 == const0_rtx
5814 && mode == GET_MODE (op0)
5815 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5817 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5818 expand_compound_operation (op0),
5819 GET_MODE_PRECISION (mode) - 1 - i);
5820 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5821 return XEXP (x, 0);
5822 else
5823 return x;
5826 /* If the code changed, return a whole new comparison.
5827 We also need to avoid using SUBST in cases where
5828 simplify_comparison has widened a comparison with a CONST_INT,
5829 since in that case the wider CONST_INT may fail the sanity
5830 checks in do_SUBST. */
5831 if (new_code != code
5832 || (CONST_INT_P (op1)
5833 && GET_MODE (op0) != GET_MODE (XEXP (x, 0))
5834 && GET_MODE (op0) != GET_MODE (XEXP (x, 1))))
5835 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5837 /* Otherwise, keep this operation, but maybe change its operands.
5838 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5839 SUBST (XEXP (x, 0), op0);
5840 SUBST (XEXP (x, 1), op1);
5842 break;
5844 case IF_THEN_ELSE:
5845 return simplify_if_then_else (x);
5847 case ZERO_EXTRACT:
5848 case SIGN_EXTRACT:
5849 case ZERO_EXTEND:
5850 case SIGN_EXTEND:
5851 /* If we are processing SET_DEST, we are done. */
5852 if (in_dest)
5853 return x;
5855 return expand_compound_operation (x);
5857 case SET:
5858 return simplify_set (x);
5860 case AND:
5861 case IOR:
5862 return simplify_logical (x);
5864 case ASHIFT:
5865 case LSHIFTRT:
5866 case ASHIFTRT:
5867 case ROTATE:
5868 case ROTATERT:
5869 /* If this is a shift by a constant amount, simplify it. */
5870 if (CONST_INT_P (XEXP (x, 1)))
5871 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5872 INTVAL (XEXP (x, 1)));
5874 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5875 SUBST (XEXP (x, 1),
5876 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5877 ((unsigned HOST_WIDE_INT) 1
5878 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5879 - 1,
5880 0));
5881 break;
5883 default:
5884 break;
5887 return x;
5890 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5892 static rtx
5893 simplify_if_then_else (rtx x)
5895 enum machine_mode mode = GET_MODE (x);
5896 rtx cond = XEXP (x, 0);
5897 rtx true_rtx = XEXP (x, 1);
5898 rtx false_rtx = XEXP (x, 2);
5899 enum rtx_code true_code = GET_CODE (cond);
5900 int comparison_p = COMPARISON_P (cond);
5901 rtx temp;
5902 int i;
5903 enum rtx_code false_code;
5904 rtx reversed;
5906 /* Simplify storing of the truth value. */
5907 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5908 return simplify_gen_relational (true_code, mode, VOIDmode,
5909 XEXP (cond, 0), XEXP (cond, 1));
5911 /* Also when the truth value has to be reversed. */
5912 if (comparison_p
5913 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5914 && (reversed = reversed_comparison (cond, mode)))
5915 return reversed;
5917 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5918 in it is being compared against certain values. Get the true and false
5919 comparisons and see if that says anything about the value of each arm. */
5921 if (comparison_p
5922 && ((false_code = reversed_comparison_code (cond, NULL))
5923 != UNKNOWN)
5924 && REG_P (XEXP (cond, 0)))
5926 HOST_WIDE_INT nzb;
5927 rtx from = XEXP (cond, 0);
5928 rtx true_val = XEXP (cond, 1);
5929 rtx false_val = true_val;
5930 int swapped = 0;
5932 /* If FALSE_CODE is EQ, swap the codes and arms. */
5934 if (false_code == EQ)
5936 swapped = 1, true_code = EQ, false_code = NE;
5937 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5940 /* If we are comparing against zero and the expression being tested has
5941 only a single bit that might be nonzero, that is its value when it is
5942 not equal to zero. Similarly if it is known to be -1 or 0. */
5944 if (true_code == EQ && true_val == const0_rtx
5945 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5947 false_code = EQ;
5948 false_val = gen_int_mode (nzb, GET_MODE (from));
5950 else if (true_code == EQ && true_val == const0_rtx
5951 && (num_sign_bit_copies (from, GET_MODE (from))
5952 == GET_MODE_PRECISION (GET_MODE (from))))
5954 false_code = EQ;
5955 false_val = constm1_rtx;
5958 /* Now simplify an arm if we know the value of the register in the
5959 branch and it is used in the arm. Be careful due to the potential
5960 of locally-shared RTL. */
5962 if (reg_mentioned_p (from, true_rtx))
5963 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5964 from, true_val),
5965 pc_rtx, pc_rtx, 0, 0, 0);
5966 if (reg_mentioned_p (from, false_rtx))
5967 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5968 from, false_val),
5969 pc_rtx, pc_rtx, 0, 0, 0);
5971 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5972 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5974 true_rtx = XEXP (x, 1);
5975 false_rtx = XEXP (x, 2);
5976 true_code = GET_CODE (cond);
5979 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5980 reversed, do so to avoid needing two sets of patterns for
5981 subtract-and-branch insns. Similarly if we have a constant in the true
5982 arm, the false arm is the same as the first operand of the comparison, or
5983 the false arm is more complicated than the true arm. */
5985 if (comparison_p
5986 && reversed_comparison_code (cond, NULL) != UNKNOWN
5987 && (true_rtx == pc_rtx
5988 || (CONSTANT_P (true_rtx)
5989 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5990 || true_rtx == const0_rtx
5991 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5992 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5993 && !OBJECT_P (false_rtx))
5994 || reg_mentioned_p (true_rtx, false_rtx)
5995 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5997 true_code = reversed_comparison_code (cond, NULL);
5998 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5999 SUBST (XEXP (x, 1), false_rtx);
6000 SUBST (XEXP (x, 2), true_rtx);
6002 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
6003 cond = XEXP (x, 0);
6005 /* It is possible that the conditional has been simplified out. */
6006 true_code = GET_CODE (cond);
6007 comparison_p = COMPARISON_P (cond);
6010 /* If the two arms are identical, we don't need the comparison. */
6012 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6013 return true_rtx;
6015 /* Convert a == b ? b : a to "a". */
6016 if (true_code == EQ && ! side_effects_p (cond)
6017 && !HONOR_NANS (mode)
6018 && rtx_equal_p (XEXP (cond, 0), false_rtx)
6019 && rtx_equal_p (XEXP (cond, 1), true_rtx))
6020 return false_rtx;
6021 else if (true_code == NE && ! side_effects_p (cond)
6022 && !HONOR_NANS (mode)
6023 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6024 && rtx_equal_p (XEXP (cond, 1), false_rtx))
6025 return true_rtx;
6027 /* Look for cases where we have (abs x) or (neg (abs X)). */
6029 if (GET_MODE_CLASS (mode) == MODE_INT
6030 && comparison_p
6031 && XEXP (cond, 1) == const0_rtx
6032 && GET_CODE (false_rtx) == NEG
6033 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6034 && rtx_equal_p (true_rtx, XEXP (cond, 0))
6035 && ! side_effects_p (true_rtx))
6036 switch (true_code)
6038 case GT:
6039 case GE:
6040 return simplify_gen_unary (ABS, mode, true_rtx, mode);
6041 case LT:
6042 case LE:
6043 return
6044 simplify_gen_unary (NEG, mode,
6045 simplify_gen_unary (ABS, mode, true_rtx, mode),
6046 mode);
6047 default:
6048 break;
6051 /* Look for MIN or MAX. */
6053 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6054 && comparison_p
6055 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6056 && rtx_equal_p (XEXP (cond, 1), false_rtx)
6057 && ! side_effects_p (cond))
6058 switch (true_code)
6060 case GE:
6061 case GT:
6062 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6063 case LE:
6064 case LT:
6065 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6066 case GEU:
6067 case GTU:
6068 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6069 case LEU:
6070 case LTU:
6071 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6072 default:
6073 break;
6076 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6077 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6078 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6079 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6080 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6081 neither 1 or -1, but it isn't worth checking for. */
6083 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6084 && comparison_p
6085 && GET_MODE_CLASS (mode) == MODE_INT
6086 && ! side_effects_p (x))
6088 rtx t = make_compound_operation (true_rtx, SET);
6089 rtx f = make_compound_operation (false_rtx, SET);
6090 rtx cond_op0 = XEXP (cond, 0);
6091 rtx cond_op1 = XEXP (cond, 1);
6092 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6093 enum machine_mode m = mode;
6094 rtx z = 0, c1 = NULL_RTX;
6096 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6097 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6098 || GET_CODE (t) == ASHIFT
6099 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6100 && rtx_equal_p (XEXP (t, 0), f))
6101 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6103 /* If an identity-zero op is commutative, check whether there
6104 would be a match if we swapped the operands. */
6105 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6106 || GET_CODE (t) == XOR)
6107 && rtx_equal_p (XEXP (t, 1), f))
6108 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6109 else if (GET_CODE (t) == SIGN_EXTEND
6110 && (GET_CODE (XEXP (t, 0)) == PLUS
6111 || GET_CODE (XEXP (t, 0)) == MINUS
6112 || GET_CODE (XEXP (t, 0)) == IOR
6113 || GET_CODE (XEXP (t, 0)) == XOR
6114 || GET_CODE (XEXP (t, 0)) == ASHIFT
6115 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6116 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6117 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6118 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6119 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6120 && (num_sign_bit_copies (f, GET_MODE (f))
6121 > (unsigned int)
6122 (GET_MODE_PRECISION (mode)
6123 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6125 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6126 extend_op = SIGN_EXTEND;
6127 m = GET_MODE (XEXP (t, 0));
6129 else if (GET_CODE (t) == SIGN_EXTEND
6130 && (GET_CODE (XEXP (t, 0)) == PLUS
6131 || GET_CODE (XEXP (t, 0)) == IOR
6132 || GET_CODE (XEXP (t, 0)) == XOR)
6133 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6134 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6135 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6136 && (num_sign_bit_copies (f, GET_MODE (f))
6137 > (unsigned int)
6138 (GET_MODE_PRECISION (mode)
6139 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6141 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6142 extend_op = SIGN_EXTEND;
6143 m = GET_MODE (XEXP (t, 0));
6145 else if (GET_CODE (t) == ZERO_EXTEND
6146 && (GET_CODE (XEXP (t, 0)) == PLUS
6147 || GET_CODE (XEXP (t, 0)) == MINUS
6148 || GET_CODE (XEXP (t, 0)) == IOR
6149 || GET_CODE (XEXP (t, 0)) == XOR
6150 || GET_CODE (XEXP (t, 0)) == ASHIFT
6151 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6152 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6153 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6154 && HWI_COMPUTABLE_MODE_P (mode)
6155 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6156 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6157 && ((nonzero_bits (f, GET_MODE (f))
6158 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6159 == 0))
6161 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6162 extend_op = ZERO_EXTEND;
6163 m = GET_MODE (XEXP (t, 0));
6165 else if (GET_CODE (t) == ZERO_EXTEND
6166 && (GET_CODE (XEXP (t, 0)) == PLUS
6167 || GET_CODE (XEXP (t, 0)) == IOR
6168 || GET_CODE (XEXP (t, 0)) == XOR)
6169 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6170 && HWI_COMPUTABLE_MODE_P (mode)
6171 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6172 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6173 && ((nonzero_bits (f, GET_MODE (f))
6174 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6175 == 0))
6177 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6178 extend_op = ZERO_EXTEND;
6179 m = GET_MODE (XEXP (t, 0));
6182 if (z)
6184 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6185 cond_op0, cond_op1),
6186 pc_rtx, pc_rtx, 0, 0, 0);
6187 temp = simplify_gen_binary (MULT, m, temp,
6188 simplify_gen_binary (MULT, m, c1,
6189 const_true_rtx));
6190 temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6191 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6193 if (extend_op != UNKNOWN)
6194 temp = simplify_gen_unary (extend_op, mode, temp, m);
6196 return temp;
6200 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6201 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6202 negation of a single bit, we can convert this operation to a shift. We
6203 can actually do this more generally, but it doesn't seem worth it. */
6205 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6206 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6207 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6208 && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6209 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6210 == GET_MODE_PRECISION (mode))
6211 && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6212 return
6213 simplify_shift_const (NULL_RTX, ASHIFT, mode,
6214 gen_lowpart (mode, XEXP (cond, 0)), i);
6216 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6217 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6218 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6219 && GET_MODE (XEXP (cond, 0)) == mode
6220 && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6221 == nonzero_bits (XEXP (cond, 0), mode)
6222 && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6223 return XEXP (cond, 0);
6225 return x;
6228 /* Simplify X, a SET expression. Return the new expression. */
6230 static rtx
6231 simplify_set (rtx x)
6233 rtx src = SET_SRC (x);
6234 rtx dest = SET_DEST (x);
6235 enum machine_mode mode
6236 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6237 rtx other_insn;
6238 rtx *cc_use;
6240 /* (set (pc) (return)) gets written as (return). */
6241 if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6242 return src;
6244 /* Now that we know for sure which bits of SRC we are using, see if we can
6245 simplify the expression for the object knowing that we only need the
6246 low-order bits. */
6248 if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6250 src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6251 SUBST (SET_SRC (x), src);
6254 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6255 the comparison result and try to simplify it unless we already have used
6256 undobuf.other_insn. */
6257 if ((GET_MODE_CLASS (mode) == MODE_CC
6258 || GET_CODE (src) == COMPARE
6259 || CC0_P (dest))
6260 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6261 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6262 && COMPARISON_P (*cc_use)
6263 && rtx_equal_p (XEXP (*cc_use, 0), dest))
6265 enum rtx_code old_code = GET_CODE (*cc_use);
6266 enum rtx_code new_code;
6267 rtx op0, op1, tmp;
6268 int other_changed = 0;
6269 rtx inner_compare = NULL_RTX;
6270 enum machine_mode compare_mode = GET_MODE (dest);
6272 if (GET_CODE (src) == COMPARE)
6274 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6275 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6277 inner_compare = op0;
6278 op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6281 else
6282 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6284 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6285 op0, op1);
6286 if (!tmp)
6287 new_code = old_code;
6288 else if (!CONSTANT_P (tmp))
6290 new_code = GET_CODE (tmp);
6291 op0 = XEXP (tmp, 0);
6292 op1 = XEXP (tmp, 1);
6294 else
6296 rtx pat = PATTERN (other_insn);
6297 undobuf.other_insn = other_insn;
6298 SUBST (*cc_use, tmp);
6300 /* Attempt to simplify CC user. */
6301 if (GET_CODE (pat) == SET)
6303 rtx new_rtx = simplify_rtx (SET_SRC (pat));
6304 if (new_rtx != NULL_RTX)
6305 SUBST (SET_SRC (pat), new_rtx);
6308 /* Convert X into a no-op move. */
6309 SUBST (SET_DEST (x), pc_rtx);
6310 SUBST (SET_SRC (x), pc_rtx);
6311 return x;
6314 /* Simplify our comparison, if possible. */
6315 new_code = simplify_comparison (new_code, &op0, &op1);
6317 #ifdef SELECT_CC_MODE
6318 /* If this machine has CC modes other than CCmode, check to see if we
6319 need to use a different CC mode here. */
6320 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6321 compare_mode = GET_MODE (op0);
6322 else if (inner_compare
6323 && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6324 && new_code == old_code
6325 && op0 == XEXP (inner_compare, 0)
6326 && op1 == XEXP (inner_compare, 1))
6327 compare_mode = GET_MODE (inner_compare);
6328 else
6329 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6331 #ifndef HAVE_cc0
6332 /* If the mode changed, we have to change SET_DEST, the mode in the
6333 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6334 a hard register, just build new versions with the proper mode. If it
6335 is a pseudo, we lose unless it is only time we set the pseudo, in
6336 which case we can safely change its mode. */
6337 if (compare_mode != GET_MODE (dest))
6339 if (can_change_dest_mode (dest, 0, compare_mode))
6341 unsigned int regno = REGNO (dest);
6342 rtx new_dest;
6344 if (regno < FIRST_PSEUDO_REGISTER)
6345 new_dest = gen_rtx_REG (compare_mode, regno);
6346 else
6348 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6349 new_dest = regno_reg_rtx[regno];
6352 SUBST (SET_DEST (x), new_dest);
6353 SUBST (XEXP (*cc_use, 0), new_dest);
6354 other_changed = 1;
6356 dest = new_dest;
6359 #endif /* cc0 */
6360 #endif /* SELECT_CC_MODE */
6362 /* If the code changed, we have to build a new comparison in
6363 undobuf.other_insn. */
6364 if (new_code != old_code)
6366 int other_changed_previously = other_changed;
6367 unsigned HOST_WIDE_INT mask;
6368 rtx old_cc_use = *cc_use;
6370 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6371 dest, const0_rtx));
6372 other_changed = 1;
6374 /* If the only change we made was to change an EQ into an NE or
6375 vice versa, OP0 has only one bit that might be nonzero, and OP1
6376 is zero, check if changing the user of the condition code will
6377 produce a valid insn. If it won't, we can keep the original code
6378 in that insn by surrounding our operation with an XOR. */
6380 if (((old_code == NE && new_code == EQ)
6381 || (old_code == EQ && new_code == NE))
6382 && ! other_changed_previously && op1 == const0_rtx
6383 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6384 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6386 rtx pat = PATTERN (other_insn), note = 0;
6388 if ((recog_for_combine (&pat, other_insn, &note) < 0
6389 && ! check_asm_operands (pat)))
6391 *cc_use = old_cc_use;
6392 other_changed = 0;
6394 op0 = simplify_gen_binary (XOR, GET_MODE (op0), op0,
6395 gen_int_mode (mask,
6396 GET_MODE (op0)));
6401 if (other_changed)
6402 undobuf.other_insn = other_insn;
6404 /* Otherwise, if we didn't previously have a COMPARE in the
6405 correct mode, we need one. */
6406 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6408 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6409 src = SET_SRC (x);
6411 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6413 SUBST (SET_SRC (x), op0);
6414 src = SET_SRC (x);
6416 /* Otherwise, update the COMPARE if needed. */
6417 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6419 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6420 src = SET_SRC (x);
6423 else
6425 /* Get SET_SRC in a form where we have placed back any
6426 compound expressions. Then do the checks below. */
6427 src = make_compound_operation (src, SET);
6428 SUBST (SET_SRC (x), src);
6431 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6432 and X being a REG or (subreg (reg)), we may be able to convert this to
6433 (set (subreg:m2 x) (op)).
6435 We can always do this if M1 is narrower than M2 because that means that
6436 we only care about the low bits of the result.
6438 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6439 perform a narrower operation than requested since the high-order bits will
6440 be undefined. On machine where it is defined, this transformation is safe
6441 as long as M1 and M2 have the same number of words. */
6443 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6444 && !OBJECT_P (SUBREG_REG (src))
6445 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6446 / UNITS_PER_WORD)
6447 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6448 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6449 #ifndef WORD_REGISTER_OPERATIONS
6450 && (GET_MODE_SIZE (GET_MODE (src))
6451 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6452 #endif
6453 #ifdef CANNOT_CHANGE_MODE_CLASS
6454 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6455 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6456 GET_MODE (SUBREG_REG (src)),
6457 GET_MODE (src)))
6458 #endif
6459 && (REG_P (dest)
6460 || (GET_CODE (dest) == SUBREG
6461 && REG_P (SUBREG_REG (dest)))))
6463 SUBST (SET_DEST (x),
6464 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6465 dest));
6466 SUBST (SET_SRC (x), SUBREG_REG (src));
6468 src = SET_SRC (x), dest = SET_DEST (x);
6471 #ifdef HAVE_cc0
6472 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6473 in SRC. */
6474 if (dest == cc0_rtx
6475 && GET_CODE (src) == SUBREG
6476 && subreg_lowpart_p (src)
6477 && (GET_MODE_PRECISION (GET_MODE (src))
6478 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src)))))
6480 rtx inner = SUBREG_REG (src);
6481 enum machine_mode inner_mode = GET_MODE (inner);
6483 /* Here we make sure that we don't have a sign bit on. */
6484 if (val_signbit_known_clear_p (GET_MODE (src),
6485 nonzero_bits (inner, inner_mode)))
6487 SUBST (SET_SRC (x), inner);
6488 src = SET_SRC (x);
6491 #endif
6493 #ifdef LOAD_EXTEND_OP
6494 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6495 would require a paradoxical subreg. Replace the subreg with a
6496 zero_extend to avoid the reload that would otherwise be required. */
6498 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6499 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6500 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6501 && SUBREG_BYTE (src) == 0
6502 && paradoxical_subreg_p (src)
6503 && MEM_P (SUBREG_REG (src)))
6505 SUBST (SET_SRC (x),
6506 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6507 GET_MODE (src), SUBREG_REG (src)));
6509 src = SET_SRC (x);
6511 #endif
6513 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6514 are comparing an item known to be 0 or -1 against 0, use a logical
6515 operation instead. Check for one of the arms being an IOR of the other
6516 arm with some value. We compute three terms to be IOR'ed together. In
6517 practice, at most two will be nonzero. Then we do the IOR's. */
6519 if (GET_CODE (dest) != PC
6520 && GET_CODE (src) == IF_THEN_ELSE
6521 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6522 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6523 && XEXP (XEXP (src, 0), 1) == const0_rtx
6524 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6525 #ifdef HAVE_conditional_move
6526 && ! can_conditionally_move_p (GET_MODE (src))
6527 #endif
6528 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6529 GET_MODE (XEXP (XEXP (src, 0), 0)))
6530 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src, 0), 0))))
6531 && ! side_effects_p (src))
6533 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6534 ? XEXP (src, 1) : XEXP (src, 2));
6535 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6536 ? XEXP (src, 2) : XEXP (src, 1));
6537 rtx term1 = const0_rtx, term2, term3;
6539 if (GET_CODE (true_rtx) == IOR
6540 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6541 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6542 else if (GET_CODE (true_rtx) == IOR
6543 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6544 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6545 else if (GET_CODE (false_rtx) == IOR
6546 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6547 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6548 else if (GET_CODE (false_rtx) == IOR
6549 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6550 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6552 term2 = simplify_gen_binary (AND, GET_MODE (src),
6553 XEXP (XEXP (src, 0), 0), true_rtx);
6554 term3 = simplify_gen_binary (AND, GET_MODE (src),
6555 simplify_gen_unary (NOT, GET_MODE (src),
6556 XEXP (XEXP (src, 0), 0),
6557 GET_MODE (src)),
6558 false_rtx);
6560 SUBST (SET_SRC (x),
6561 simplify_gen_binary (IOR, GET_MODE (src),
6562 simplify_gen_binary (IOR, GET_MODE (src),
6563 term1, term2),
6564 term3));
6566 src = SET_SRC (x);
6569 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6570 whole thing fail. */
6571 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6572 return src;
6573 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6574 return dest;
6575 else
6576 /* Convert this into a field assignment operation, if possible. */
6577 return make_field_assignment (x);
6580 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6581 result. */
6583 static rtx
6584 simplify_logical (rtx x)
6586 enum machine_mode mode = GET_MODE (x);
6587 rtx op0 = XEXP (x, 0);
6588 rtx op1 = XEXP (x, 1);
6590 switch (GET_CODE (x))
6592 case AND:
6593 /* We can call simplify_and_const_int only if we don't lose
6594 any (sign) bits when converting INTVAL (op1) to
6595 "unsigned HOST_WIDE_INT". */
6596 if (CONST_INT_P (op1)
6597 && (HWI_COMPUTABLE_MODE_P (mode)
6598 || INTVAL (op1) > 0))
6600 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6601 if (GET_CODE (x) != AND)
6602 return x;
6604 op0 = XEXP (x, 0);
6605 op1 = XEXP (x, 1);
6608 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6609 apply the distributive law and then the inverse distributive
6610 law to see if things simplify. */
6611 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6613 rtx result = distribute_and_simplify_rtx (x, 0);
6614 if (result)
6615 return result;
6617 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6619 rtx result = distribute_and_simplify_rtx (x, 1);
6620 if (result)
6621 return result;
6623 break;
6625 case IOR:
6626 /* If we have (ior (and A B) C), apply the distributive law and then
6627 the inverse distributive law to see if things simplify. */
6629 if (GET_CODE (op0) == AND)
6631 rtx result = distribute_and_simplify_rtx (x, 0);
6632 if (result)
6633 return result;
6636 if (GET_CODE (op1) == AND)
6638 rtx result = distribute_and_simplify_rtx (x, 1);
6639 if (result)
6640 return result;
6642 break;
6644 default:
6645 gcc_unreachable ();
6648 return x;
6651 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6652 operations" because they can be replaced with two more basic operations.
6653 ZERO_EXTEND is also considered "compound" because it can be replaced with
6654 an AND operation, which is simpler, though only one operation.
6656 The function expand_compound_operation is called with an rtx expression
6657 and will convert it to the appropriate shifts and AND operations,
6658 simplifying at each stage.
6660 The function make_compound_operation is called to convert an expression
6661 consisting of shifts and ANDs into the equivalent compound expression.
6662 It is the inverse of this function, loosely speaking. */
6664 static rtx
6665 expand_compound_operation (rtx x)
6667 unsigned HOST_WIDE_INT pos = 0, len;
6668 int unsignedp = 0;
6669 unsigned int modewidth;
6670 rtx tem;
6672 switch (GET_CODE (x))
6674 case ZERO_EXTEND:
6675 unsignedp = 1;
6676 case SIGN_EXTEND:
6677 /* We can't necessarily use a const_int for a multiword mode;
6678 it depends on implicitly extending the value.
6679 Since we don't know the right way to extend it,
6680 we can't tell whether the implicit way is right.
6682 Even for a mode that is no wider than a const_int,
6683 we can't win, because we need to sign extend one of its bits through
6684 the rest of it, and we don't know which bit. */
6685 if (CONST_INT_P (XEXP (x, 0)))
6686 return x;
6688 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6689 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6690 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6691 reloaded. If not for that, MEM's would very rarely be safe.
6693 Reject MODEs bigger than a word, because we might not be able
6694 to reference a two-register group starting with an arbitrary register
6695 (and currently gen_lowpart might crash for a SUBREG). */
6697 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6698 return x;
6700 /* Reject MODEs that aren't scalar integers because turning vector
6701 or complex modes into shifts causes problems. */
6703 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6704 return x;
6706 len = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)));
6707 /* If the inner object has VOIDmode (the only way this can happen
6708 is if it is an ASM_OPERANDS), we can't do anything since we don't
6709 know how much masking to do. */
6710 if (len == 0)
6711 return x;
6713 break;
6715 case ZERO_EXTRACT:
6716 unsignedp = 1;
6718 /* ... fall through ... */
6720 case SIGN_EXTRACT:
6721 /* If the operand is a CLOBBER, just return it. */
6722 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6723 return XEXP (x, 0);
6725 if (!CONST_INT_P (XEXP (x, 1))
6726 || !CONST_INT_P (XEXP (x, 2))
6727 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6728 return x;
6730 /* Reject MODEs that aren't scalar integers because turning vector
6731 or complex modes into shifts causes problems. */
6733 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6734 return x;
6736 len = INTVAL (XEXP (x, 1));
6737 pos = INTVAL (XEXP (x, 2));
6739 /* This should stay within the object being extracted, fail otherwise. */
6740 if (len + pos > GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))))
6741 return x;
6743 if (BITS_BIG_ENDIAN)
6744 pos = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) - len - pos;
6746 break;
6748 default:
6749 return x;
6751 /* Convert sign extension to zero extension, if we know that the high
6752 bit is not set, as this is easier to optimize. It will be converted
6753 back to cheaper alternative in make_extraction. */
6754 if (GET_CODE (x) == SIGN_EXTEND
6755 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6756 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6757 & ~(((unsigned HOST_WIDE_INT)
6758 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6759 >> 1))
6760 == 0)))
6762 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6763 rtx temp2 = expand_compound_operation (temp);
6765 /* Make sure this is a profitable operation. */
6766 if (set_src_cost (x, optimize_this_for_speed_p)
6767 > set_src_cost (temp2, optimize_this_for_speed_p))
6768 return temp2;
6769 else if (set_src_cost (x, optimize_this_for_speed_p)
6770 > set_src_cost (temp, optimize_this_for_speed_p))
6771 return temp;
6772 else
6773 return x;
6776 /* We can optimize some special cases of ZERO_EXTEND. */
6777 if (GET_CODE (x) == ZERO_EXTEND)
6779 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6780 know that the last value didn't have any inappropriate bits
6781 set. */
6782 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6783 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6784 && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6785 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6786 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6787 return XEXP (XEXP (x, 0), 0);
6789 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6790 if (GET_CODE (XEXP (x, 0)) == SUBREG
6791 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6792 && subreg_lowpart_p (XEXP (x, 0))
6793 && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6794 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6795 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6796 return SUBREG_REG (XEXP (x, 0));
6798 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6799 is a comparison and STORE_FLAG_VALUE permits. This is like
6800 the first case, but it works even when GET_MODE (x) is larger
6801 than HOST_WIDE_INT. */
6802 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6803 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6804 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6805 && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6806 <= HOST_BITS_PER_WIDE_INT)
6807 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6808 return XEXP (XEXP (x, 0), 0);
6810 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6811 if (GET_CODE (XEXP (x, 0)) == SUBREG
6812 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6813 && subreg_lowpart_p (XEXP (x, 0))
6814 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6815 && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6816 <= HOST_BITS_PER_WIDE_INT)
6817 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6818 return SUBREG_REG (XEXP (x, 0));
6822 /* If we reach here, we want to return a pair of shifts. The inner
6823 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6824 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6825 logical depending on the value of UNSIGNEDP.
6827 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6828 converted into an AND of a shift.
6830 We must check for the case where the left shift would have a negative
6831 count. This can happen in a case like (x >> 31) & 255 on machines
6832 that can't shift by a constant. On those machines, we would first
6833 combine the shift with the AND to produce a variable-position
6834 extraction. Then the constant of 31 would be substituted in
6835 to produce such a position. */
6837 modewidth = GET_MODE_PRECISION (GET_MODE (x));
6838 if (modewidth >= pos + len)
6840 enum machine_mode mode = GET_MODE (x);
6841 tem = gen_lowpart (mode, XEXP (x, 0));
6842 if (!tem || GET_CODE (tem) == CLOBBER)
6843 return x;
6844 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6845 tem, modewidth - pos - len);
6846 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6847 mode, tem, modewidth - len);
6849 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6850 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6851 simplify_shift_const (NULL_RTX, LSHIFTRT,
6852 GET_MODE (x),
6853 XEXP (x, 0), pos),
6854 ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6855 else
6856 /* Any other cases we can't handle. */
6857 return x;
6859 /* If we couldn't do this for some reason, return the original
6860 expression. */
6861 if (GET_CODE (tem) == CLOBBER)
6862 return x;
6864 return tem;
6867 /* X is a SET which contains an assignment of one object into
6868 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6869 or certain SUBREGS). If possible, convert it into a series of
6870 logical operations.
6872 We half-heartedly support variable positions, but do not at all
6873 support variable lengths. */
6875 static const_rtx
6876 expand_field_assignment (const_rtx x)
6878 rtx inner;
6879 rtx pos; /* Always counts from low bit. */
6880 int len;
6881 rtx mask, cleared, masked;
6882 enum machine_mode compute_mode;
6884 /* Loop until we find something we can't simplify. */
6885 while (1)
6887 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6888 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6890 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6891 len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)));
6892 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6894 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6895 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6897 inner = XEXP (SET_DEST (x), 0);
6898 len = INTVAL (XEXP (SET_DEST (x), 1));
6899 pos = XEXP (SET_DEST (x), 2);
6901 /* A constant position should stay within the width of INNER. */
6902 if (CONST_INT_P (pos)
6903 && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner)))
6904 break;
6906 if (BITS_BIG_ENDIAN)
6908 if (CONST_INT_P (pos))
6909 pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len
6910 - INTVAL (pos));
6911 else if (GET_CODE (pos) == MINUS
6912 && CONST_INT_P (XEXP (pos, 1))
6913 && (INTVAL (XEXP (pos, 1))
6914 == GET_MODE_PRECISION (GET_MODE (inner)) - len))
6915 /* If position is ADJUST - X, new position is X. */
6916 pos = XEXP (pos, 0);
6917 else
6919 HOST_WIDE_INT prec = GET_MODE_PRECISION (GET_MODE (inner));
6920 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6921 gen_int_mode (prec - len,
6922 GET_MODE (pos)),
6923 pos);
6928 /* A SUBREG between two modes that occupy the same numbers of words
6929 can be done by moving the SUBREG to the source. */
6930 else if (GET_CODE (SET_DEST (x)) == SUBREG
6931 /* We need SUBREGs to compute nonzero_bits properly. */
6932 && nonzero_sign_valid
6933 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6934 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6935 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6936 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6938 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6939 gen_lowpart
6940 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6941 SET_SRC (x)));
6942 continue;
6944 else
6945 break;
6947 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6948 inner = SUBREG_REG (inner);
6950 compute_mode = GET_MODE (inner);
6952 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6953 if (! SCALAR_INT_MODE_P (compute_mode))
6955 enum machine_mode imode;
6957 /* Don't do anything for vector or complex integral types. */
6958 if (! FLOAT_MODE_P (compute_mode))
6959 break;
6961 /* Try to find an integral mode to pun with. */
6962 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6963 if (imode == BLKmode)
6964 break;
6966 compute_mode = imode;
6967 inner = gen_lowpart (imode, inner);
6970 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6971 if (len >= HOST_BITS_PER_WIDE_INT)
6972 break;
6974 /* Now compute the equivalent expression. Make a copy of INNER
6975 for the SET_DEST in case it is a MEM into which we will substitute;
6976 we don't want shared RTL in that case. */
6977 mask = gen_int_mode (((unsigned HOST_WIDE_INT) 1 << len) - 1,
6978 compute_mode);
6979 cleared = simplify_gen_binary (AND, compute_mode,
6980 simplify_gen_unary (NOT, compute_mode,
6981 simplify_gen_binary (ASHIFT,
6982 compute_mode,
6983 mask, pos),
6984 compute_mode),
6985 inner);
6986 masked = simplify_gen_binary (ASHIFT, compute_mode,
6987 simplify_gen_binary (
6988 AND, compute_mode,
6989 gen_lowpart (compute_mode, SET_SRC (x)),
6990 mask),
6991 pos);
6993 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6994 simplify_gen_binary (IOR, compute_mode,
6995 cleared, masked));
6998 return x;
7001 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7002 it is an RTX that represents the (variable) starting position; otherwise,
7003 POS is the (constant) starting bit position. Both are counted from the LSB.
7005 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7007 IN_DEST is nonzero if this is a reference in the destination of a SET.
7008 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7009 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7010 be used.
7012 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7013 ZERO_EXTRACT should be built even for bits starting at bit 0.
7015 MODE is the desired mode of the result (if IN_DEST == 0).
7017 The result is an RTX for the extraction or NULL_RTX if the target
7018 can't handle it. */
7020 static rtx
7021 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7022 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7023 int in_dest, int in_compare)
7025 /* This mode describes the size of the storage area
7026 to fetch the overall value from. Within that, we
7027 ignore the POS lowest bits, etc. */
7028 enum machine_mode is_mode = GET_MODE (inner);
7029 enum machine_mode inner_mode;
7030 enum machine_mode wanted_inner_mode;
7031 enum machine_mode wanted_inner_reg_mode = word_mode;
7032 enum machine_mode pos_mode = word_mode;
7033 enum machine_mode extraction_mode = word_mode;
7034 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7035 rtx new_rtx = 0;
7036 rtx orig_pos_rtx = pos_rtx;
7037 HOST_WIDE_INT orig_pos;
7039 if (pos_rtx && CONST_INT_P (pos_rtx))
7040 pos = INTVAL (pos_rtx), pos_rtx = 0;
7042 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7044 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7045 consider just the QI as the memory to extract from.
7046 The subreg adds or removes high bits; its mode is
7047 irrelevant to the meaning of this extraction,
7048 since POS and LEN count from the lsb. */
7049 if (MEM_P (SUBREG_REG (inner)))
7050 is_mode = GET_MODE (SUBREG_REG (inner));
7051 inner = SUBREG_REG (inner);
7053 else if (GET_CODE (inner) == ASHIFT
7054 && CONST_INT_P (XEXP (inner, 1))
7055 && pos_rtx == 0 && pos == 0
7056 && len > UINTVAL (XEXP (inner, 1)))
7058 /* We're extracting the least significant bits of an rtx
7059 (ashift X (const_int C)), where LEN > C. Extract the
7060 least significant (LEN - C) bits of X, giving an rtx
7061 whose mode is MODE, then shift it left C times. */
7062 new_rtx = make_extraction (mode, XEXP (inner, 0),
7063 0, 0, len - INTVAL (XEXP (inner, 1)),
7064 unsignedp, in_dest, in_compare);
7065 if (new_rtx != 0)
7066 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7068 else if (GET_CODE (inner) == TRUNCATE)
7069 inner = XEXP (inner, 0);
7071 inner_mode = GET_MODE (inner);
7073 /* See if this can be done without an extraction. We never can if the
7074 width of the field is not the same as that of some integer mode. For
7075 registers, we can only avoid the extraction if the position is at the
7076 low-order bit and this is either not in the destination or we have the
7077 appropriate STRICT_LOW_PART operation available.
7079 For MEM, we can avoid an extract if the field starts on an appropriate
7080 boundary and we can change the mode of the memory reference. */
7082 if (tmode != BLKmode
7083 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7084 && !MEM_P (inner)
7085 && (inner_mode == tmode
7086 || !REG_P (inner)
7087 || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7088 || reg_truncated_to_mode (tmode, inner))
7089 && (! in_dest
7090 || (REG_P (inner)
7091 && have_insn_for (STRICT_LOW_PART, tmode))))
7092 || (MEM_P (inner) && pos_rtx == 0
7093 && (pos
7094 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7095 : BITS_PER_UNIT)) == 0
7096 /* We can't do this if we are widening INNER_MODE (it
7097 may not be aligned, for one thing). */
7098 && GET_MODE_PRECISION (inner_mode) >= GET_MODE_PRECISION (tmode)
7099 && (inner_mode == tmode
7100 || (! mode_dependent_address_p (XEXP (inner, 0),
7101 MEM_ADDR_SPACE (inner))
7102 && ! MEM_VOLATILE_P (inner))))))
7104 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7105 field. If the original and current mode are the same, we need not
7106 adjust the offset. Otherwise, we do if bytes big endian.
7108 If INNER is not a MEM, get a piece consisting of just the field
7109 of interest (in this case POS % BITS_PER_WORD must be 0). */
7111 if (MEM_P (inner))
7113 HOST_WIDE_INT offset;
7115 /* POS counts from lsb, but make OFFSET count in memory order. */
7116 if (BYTES_BIG_ENDIAN)
7117 offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT;
7118 else
7119 offset = pos / BITS_PER_UNIT;
7121 new_rtx = adjust_address_nv (inner, tmode, offset);
7123 else if (REG_P (inner))
7125 if (tmode != inner_mode)
7127 /* We can't call gen_lowpart in a DEST since we
7128 always want a SUBREG (see below) and it would sometimes
7129 return a new hard register. */
7130 if (pos || in_dest)
7132 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7134 if (WORDS_BIG_ENDIAN
7135 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7136 final_word = ((GET_MODE_SIZE (inner_mode)
7137 - GET_MODE_SIZE (tmode))
7138 / UNITS_PER_WORD) - final_word;
7140 final_word *= UNITS_PER_WORD;
7141 if (BYTES_BIG_ENDIAN &&
7142 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7143 final_word += (GET_MODE_SIZE (inner_mode)
7144 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7146 /* Avoid creating invalid subregs, for example when
7147 simplifying (x>>32)&255. */
7148 if (!validate_subreg (tmode, inner_mode, inner, final_word))
7149 return NULL_RTX;
7151 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7153 else
7154 new_rtx = gen_lowpart (tmode, inner);
7156 else
7157 new_rtx = inner;
7159 else
7160 new_rtx = force_to_mode (inner, tmode,
7161 len >= HOST_BITS_PER_WIDE_INT
7162 ? ~(unsigned HOST_WIDE_INT) 0
7163 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7166 /* If this extraction is going into the destination of a SET,
7167 make a STRICT_LOW_PART unless we made a MEM. */
7169 if (in_dest)
7170 return (MEM_P (new_rtx) ? new_rtx
7171 : (GET_CODE (new_rtx) != SUBREG
7172 ? gen_rtx_CLOBBER (tmode, const0_rtx)
7173 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7175 if (mode == tmode)
7176 return new_rtx;
7178 if (CONST_SCALAR_INT_P (new_rtx))
7179 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7180 mode, new_rtx, tmode);
7182 /* If we know that no extraneous bits are set, and that the high
7183 bit is not set, convert the extraction to the cheaper of
7184 sign and zero extension, that are equivalent in these cases. */
7185 if (flag_expensive_optimizations
7186 && (HWI_COMPUTABLE_MODE_P (tmode)
7187 && ((nonzero_bits (new_rtx, tmode)
7188 & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7189 == 0)))
7191 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7192 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7194 /* Prefer ZERO_EXTENSION, since it gives more information to
7195 backends. */
7196 if (set_src_cost (temp, optimize_this_for_speed_p)
7197 <= set_src_cost (temp1, optimize_this_for_speed_p))
7198 return temp;
7199 return temp1;
7202 /* Otherwise, sign- or zero-extend unless we already are in the
7203 proper mode. */
7205 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7206 mode, new_rtx));
7209 /* Unless this is a COMPARE or we have a funny memory reference,
7210 don't do anything with zero-extending field extracts starting at
7211 the low-order bit since they are simple AND operations. */
7212 if (pos_rtx == 0 && pos == 0 && ! in_dest
7213 && ! in_compare && unsignedp)
7214 return 0;
7216 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7217 if the position is not a constant and the length is not 1. In all
7218 other cases, we would only be going outside our object in cases when
7219 an original shift would have been undefined. */
7220 if (MEM_P (inner)
7221 && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode))
7222 || (pos_rtx != 0 && len != 1)))
7223 return 0;
7225 enum extraction_pattern pattern = (in_dest ? EP_insv
7226 : unsignedp ? EP_extzv : EP_extv);
7228 /* If INNER is not from memory, we want it to have the mode of a register
7229 extraction pattern's structure operand, or word_mode if there is no
7230 such pattern. The same applies to extraction_mode and pos_mode
7231 and their respective operands.
7233 For memory, assume that the desired extraction_mode and pos_mode
7234 are the same as for a register operation, since at present we don't
7235 have named patterns for aligned memory structures. */
7236 struct extraction_insn insn;
7237 if (get_best_reg_extraction_insn (&insn, pattern,
7238 GET_MODE_BITSIZE (inner_mode), mode))
7240 wanted_inner_reg_mode = insn.struct_mode;
7241 pos_mode = insn.pos_mode;
7242 extraction_mode = insn.field_mode;
7245 /* Never narrow an object, since that might not be safe. */
7247 if (mode != VOIDmode
7248 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7249 extraction_mode = mode;
7251 if (!MEM_P (inner))
7252 wanted_inner_mode = wanted_inner_reg_mode;
7253 else
7255 /* Be careful not to go beyond the extracted object and maintain the
7256 natural alignment of the memory. */
7257 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7258 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7259 > GET_MODE_BITSIZE (wanted_inner_mode))
7261 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7262 gcc_assert (wanted_inner_mode != VOIDmode);
7266 orig_pos = pos;
7268 if (BITS_BIG_ENDIAN)
7270 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7271 BITS_BIG_ENDIAN style. If position is constant, compute new
7272 position. Otherwise, build subtraction.
7273 Note that POS is relative to the mode of the original argument.
7274 If it's a MEM we need to recompute POS relative to that.
7275 However, if we're extracting from (or inserting into) a register,
7276 we want to recompute POS relative to wanted_inner_mode. */
7277 int width = (MEM_P (inner)
7278 ? GET_MODE_BITSIZE (is_mode)
7279 : GET_MODE_BITSIZE (wanted_inner_mode));
7281 if (pos_rtx == 0)
7282 pos = width - len - pos;
7283 else
7284 pos_rtx
7285 = gen_rtx_MINUS (GET_MODE (pos_rtx),
7286 gen_int_mode (width - len, GET_MODE (pos_rtx)),
7287 pos_rtx);
7288 /* POS may be less than 0 now, but we check for that below.
7289 Note that it can only be less than 0 if !MEM_P (inner). */
7292 /* If INNER has a wider mode, and this is a constant extraction, try to
7293 make it smaller and adjust the byte to point to the byte containing
7294 the value. */
7295 if (wanted_inner_mode != VOIDmode
7296 && inner_mode != wanted_inner_mode
7297 && ! pos_rtx
7298 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7299 && MEM_P (inner)
7300 && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner))
7301 && ! MEM_VOLATILE_P (inner))
7303 int offset = 0;
7305 /* The computations below will be correct if the machine is big
7306 endian in both bits and bytes or little endian in bits and bytes.
7307 If it is mixed, we must adjust. */
7309 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7310 adjust OFFSET to compensate. */
7311 if (BYTES_BIG_ENDIAN
7312 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7313 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7315 /* We can now move to the desired byte. */
7316 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7317 * GET_MODE_SIZE (wanted_inner_mode);
7318 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7320 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7321 && is_mode != wanted_inner_mode)
7322 offset = (GET_MODE_SIZE (is_mode)
7323 - GET_MODE_SIZE (wanted_inner_mode) - offset);
7325 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7328 /* If INNER is not memory, get it into the proper mode. If we are changing
7329 its mode, POS must be a constant and smaller than the size of the new
7330 mode. */
7331 else if (!MEM_P (inner))
7333 /* On the LHS, don't create paradoxical subregs implicitely truncating
7334 the register unless TRULY_NOOP_TRUNCATION. */
7335 if (in_dest
7336 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7337 wanted_inner_mode))
7338 return NULL_RTX;
7340 if (GET_MODE (inner) != wanted_inner_mode
7341 && (pos_rtx != 0
7342 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7343 return NULL_RTX;
7345 if (orig_pos < 0)
7346 return NULL_RTX;
7348 inner = force_to_mode (inner, wanted_inner_mode,
7349 pos_rtx
7350 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7351 ? ~(unsigned HOST_WIDE_INT) 0
7352 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7353 << orig_pos),
7357 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7358 have to zero extend. Otherwise, we can just use a SUBREG. */
7359 if (pos_rtx != 0
7360 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7362 rtx temp = simplify_gen_unary (ZERO_EXTEND, pos_mode, pos_rtx,
7363 GET_MODE (pos_rtx));
7365 /* If we know that no extraneous bits are set, and that the high
7366 bit is not set, convert extraction to cheaper one - either
7367 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7368 cases. */
7369 if (flag_expensive_optimizations
7370 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7371 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7372 & ~(((unsigned HOST_WIDE_INT)
7373 GET_MODE_MASK (GET_MODE (pos_rtx)))
7374 >> 1))
7375 == 0)))
7377 rtx temp1 = simplify_gen_unary (SIGN_EXTEND, pos_mode, pos_rtx,
7378 GET_MODE (pos_rtx));
7380 /* Prefer ZERO_EXTENSION, since it gives more information to
7381 backends. */
7382 if (set_src_cost (temp1, optimize_this_for_speed_p)
7383 < set_src_cost (temp, optimize_this_for_speed_p))
7384 temp = temp1;
7386 pos_rtx = temp;
7389 /* Make POS_RTX unless we already have it and it is correct. If we don't
7390 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7391 be a CONST_INT. */
7392 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7393 pos_rtx = orig_pos_rtx;
7395 else if (pos_rtx == 0)
7396 pos_rtx = GEN_INT (pos);
7398 /* Make the required operation. See if we can use existing rtx. */
7399 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7400 extraction_mode, inner, GEN_INT (len), pos_rtx);
7401 if (! in_dest)
7402 new_rtx = gen_lowpart (mode, new_rtx);
7404 return new_rtx;
7407 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7408 with any other operations in X. Return X without that shift if so. */
7410 static rtx
7411 extract_left_shift (rtx x, int count)
7413 enum rtx_code code = GET_CODE (x);
7414 enum machine_mode mode = GET_MODE (x);
7415 rtx tem;
7417 switch (code)
7419 case ASHIFT:
7420 /* This is the shift itself. If it is wide enough, we will return
7421 either the value being shifted if the shift count is equal to
7422 COUNT or a shift for the difference. */
7423 if (CONST_INT_P (XEXP (x, 1))
7424 && INTVAL (XEXP (x, 1)) >= count)
7425 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7426 INTVAL (XEXP (x, 1)) - count);
7427 break;
7429 case NEG: case NOT:
7430 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7431 return simplify_gen_unary (code, mode, tem, mode);
7433 break;
7435 case PLUS: case IOR: case XOR: case AND:
7436 /* If we can safely shift this constant and we find the inner shift,
7437 make a new operation. */
7438 if (CONST_INT_P (XEXP (x, 1))
7439 && (UINTVAL (XEXP (x, 1))
7440 & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7441 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7443 HOST_WIDE_INT val = INTVAL (XEXP (x, 1)) >> count;
7444 return simplify_gen_binary (code, mode, tem,
7445 gen_int_mode (val, mode));
7447 break;
7449 default:
7450 break;
7453 return 0;
7456 /* Look at the expression rooted at X. Look for expressions
7457 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7458 Form these expressions.
7460 Return the new rtx, usually just X.
7462 Also, for machines like the VAX that don't have logical shift insns,
7463 try to convert logical to arithmetic shift operations in cases where
7464 they are equivalent. This undoes the canonicalizations to logical
7465 shifts done elsewhere.
7467 We try, as much as possible, to re-use rtl expressions to save memory.
7469 IN_CODE says what kind of expression we are processing. Normally, it is
7470 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7471 being kludges), it is MEM. When processing the arguments of a comparison
7472 or a COMPARE against zero, it is COMPARE. */
7475 make_compound_operation (rtx x, enum rtx_code in_code)
7477 enum rtx_code code = GET_CODE (x);
7478 enum machine_mode mode = GET_MODE (x);
7479 int mode_width = GET_MODE_PRECISION (mode);
7480 rtx rhs, lhs;
7481 enum rtx_code next_code;
7482 int i, j;
7483 rtx new_rtx = 0;
7484 rtx tem;
7485 const char *fmt;
7487 /* Select the code to be used in recursive calls. Once we are inside an
7488 address, we stay there. If we have a comparison, set to COMPARE,
7489 but once inside, go back to our default of SET. */
7491 next_code = (code == MEM ? MEM
7492 : ((code == PLUS || code == MINUS)
7493 && SCALAR_INT_MODE_P (mode)) ? MEM
7494 : ((code == COMPARE || COMPARISON_P (x))
7495 && XEXP (x, 1) == const0_rtx) ? COMPARE
7496 : in_code == COMPARE ? SET : in_code);
7498 /* Process depending on the code of this operation. If NEW is set
7499 nonzero, it will be returned. */
7501 switch (code)
7503 case ASHIFT:
7504 /* Convert shifts by constants into multiplications if inside
7505 an address. */
7506 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7507 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7508 && INTVAL (XEXP (x, 1)) >= 0
7509 && SCALAR_INT_MODE_P (mode))
7511 HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7512 HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7514 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7515 if (GET_CODE (new_rtx) == NEG)
7517 new_rtx = XEXP (new_rtx, 0);
7518 multval = -multval;
7520 multval = trunc_int_for_mode (multval, mode);
7521 new_rtx = gen_rtx_MULT (mode, new_rtx, gen_int_mode (multval, mode));
7523 break;
7525 case PLUS:
7526 lhs = XEXP (x, 0);
7527 rhs = XEXP (x, 1);
7528 lhs = make_compound_operation (lhs, next_code);
7529 rhs = make_compound_operation (rhs, next_code);
7530 if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7531 && SCALAR_INT_MODE_P (mode))
7533 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7534 XEXP (lhs, 1));
7535 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7537 else if (GET_CODE (lhs) == MULT
7538 && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7540 tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7541 simplify_gen_unary (NEG, mode,
7542 XEXP (lhs, 1),
7543 mode));
7544 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7546 else
7548 SUBST (XEXP (x, 0), lhs);
7549 SUBST (XEXP (x, 1), rhs);
7550 goto maybe_swap;
7552 x = gen_lowpart (mode, new_rtx);
7553 goto maybe_swap;
7555 case MINUS:
7556 lhs = XEXP (x, 0);
7557 rhs = XEXP (x, 1);
7558 lhs = make_compound_operation (lhs, next_code);
7559 rhs = make_compound_operation (rhs, next_code);
7560 if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7561 && SCALAR_INT_MODE_P (mode))
7563 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7564 XEXP (rhs, 1));
7565 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7567 else if (GET_CODE (rhs) == MULT
7568 && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7570 tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7571 simplify_gen_unary (NEG, mode,
7572 XEXP (rhs, 1),
7573 mode));
7574 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7576 else
7578 SUBST (XEXP (x, 0), lhs);
7579 SUBST (XEXP (x, 1), rhs);
7580 return x;
7582 return gen_lowpart (mode, new_rtx);
7584 case AND:
7585 /* If the second operand is not a constant, we can't do anything
7586 with it. */
7587 if (!CONST_INT_P (XEXP (x, 1)))
7588 break;
7590 /* If the constant is a power of two minus one and the first operand
7591 is a logical right shift, make an extraction. */
7592 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7593 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7595 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7596 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7597 0, in_code == COMPARE);
7600 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7601 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7602 && subreg_lowpart_p (XEXP (x, 0))
7603 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7604 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7606 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7607 next_code);
7608 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7609 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7610 0, in_code == COMPARE);
7612 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7613 else if ((GET_CODE (XEXP (x, 0)) == XOR
7614 || GET_CODE (XEXP (x, 0)) == IOR)
7615 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7616 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7617 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7619 /* Apply the distributive law, and then try to make extractions. */
7620 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7621 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7622 XEXP (x, 1)),
7623 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7624 XEXP (x, 1)));
7625 new_rtx = make_compound_operation (new_rtx, in_code);
7628 /* If we are have (and (rotate X C) M) and C is larger than the number
7629 of bits in M, this is an extraction. */
7631 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7632 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7633 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7634 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7636 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7637 new_rtx = make_extraction (mode, new_rtx,
7638 (GET_MODE_PRECISION (mode)
7639 - INTVAL (XEXP (XEXP (x, 0), 1))),
7640 NULL_RTX, i, 1, 0, in_code == COMPARE);
7643 /* On machines without logical shifts, if the operand of the AND is
7644 a logical shift and our mask turns off all the propagated sign
7645 bits, we can replace the logical shift with an arithmetic shift. */
7646 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7647 && !have_insn_for (LSHIFTRT, mode)
7648 && have_insn_for (ASHIFTRT, mode)
7649 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7650 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7651 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7652 && mode_width <= HOST_BITS_PER_WIDE_INT)
7654 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7656 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7657 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7658 SUBST (XEXP (x, 0),
7659 gen_rtx_ASHIFTRT (mode,
7660 make_compound_operation
7661 (XEXP (XEXP (x, 0), 0), next_code),
7662 XEXP (XEXP (x, 0), 1)));
7665 /* If the constant is one less than a power of two, this might be
7666 representable by an extraction even if no shift is present.
7667 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7668 we are in a COMPARE. */
7669 else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7670 new_rtx = make_extraction (mode,
7671 make_compound_operation (XEXP (x, 0),
7672 next_code),
7673 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7675 /* If we are in a comparison and this is an AND with a power of two,
7676 convert this into the appropriate bit extract. */
7677 else if (in_code == COMPARE
7678 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7679 new_rtx = make_extraction (mode,
7680 make_compound_operation (XEXP (x, 0),
7681 next_code),
7682 i, NULL_RTX, 1, 1, 0, 1);
7684 break;
7686 case LSHIFTRT:
7687 /* If the sign bit is known to be zero, replace this with an
7688 arithmetic shift. */
7689 if (have_insn_for (ASHIFTRT, mode)
7690 && ! have_insn_for (LSHIFTRT, mode)
7691 && mode_width <= HOST_BITS_PER_WIDE_INT
7692 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7694 new_rtx = gen_rtx_ASHIFTRT (mode,
7695 make_compound_operation (XEXP (x, 0),
7696 next_code),
7697 XEXP (x, 1));
7698 break;
7701 /* ... fall through ... */
7703 case ASHIFTRT:
7704 lhs = XEXP (x, 0);
7705 rhs = XEXP (x, 1);
7707 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7708 this is a SIGN_EXTRACT. */
7709 if (CONST_INT_P (rhs)
7710 && GET_CODE (lhs) == ASHIFT
7711 && CONST_INT_P (XEXP (lhs, 1))
7712 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7713 && INTVAL (XEXP (lhs, 1)) >= 0
7714 && INTVAL (rhs) < mode_width)
7716 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7717 new_rtx = make_extraction (mode, new_rtx,
7718 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7719 NULL_RTX, mode_width - INTVAL (rhs),
7720 code == LSHIFTRT, 0, in_code == COMPARE);
7721 break;
7724 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7725 If so, try to merge the shifts into a SIGN_EXTEND. We could
7726 also do this for some cases of SIGN_EXTRACT, but it doesn't
7727 seem worth the effort; the case checked for occurs on Alpha. */
7729 if (!OBJECT_P (lhs)
7730 && ! (GET_CODE (lhs) == SUBREG
7731 && (OBJECT_P (SUBREG_REG (lhs))))
7732 && CONST_INT_P (rhs)
7733 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7734 && INTVAL (rhs) < mode_width
7735 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7736 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7737 0, NULL_RTX, mode_width - INTVAL (rhs),
7738 code == LSHIFTRT, 0, in_code == COMPARE);
7740 break;
7742 case SUBREG:
7743 /* Call ourselves recursively on the inner expression. If we are
7744 narrowing the object and it has a different RTL code from
7745 what it originally did, do this SUBREG as a force_to_mode. */
7747 rtx inner = SUBREG_REG (x), simplified;
7748 enum rtx_code subreg_code = in_code;
7750 /* If in_code is COMPARE, it isn't always safe to pass it through
7751 to the recursive make_compound_operation call. */
7752 if (subreg_code == COMPARE
7753 && (!subreg_lowpart_p (x)
7754 || GET_CODE (inner) == SUBREG
7755 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7756 is (const_int 0), rather than
7757 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
7758 || (GET_CODE (inner) == AND
7759 && CONST_INT_P (XEXP (inner, 1))
7760 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7761 && exact_log2 (UINTVAL (XEXP (inner, 1)))
7762 >= GET_MODE_BITSIZE (mode))))
7763 subreg_code = SET;
7765 tem = make_compound_operation (inner, subreg_code);
7767 simplified
7768 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7769 if (simplified)
7770 tem = simplified;
7772 if (GET_CODE (tem) != GET_CODE (inner)
7773 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7774 && subreg_lowpart_p (x))
7776 rtx newer
7777 = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7779 /* If we have something other than a SUBREG, we might have
7780 done an expansion, so rerun ourselves. */
7781 if (GET_CODE (newer) != SUBREG)
7782 newer = make_compound_operation (newer, in_code);
7784 /* force_to_mode can expand compounds. If it just re-expanded the
7785 compound, use gen_lowpart to convert to the desired mode. */
7786 if (rtx_equal_p (newer, x)
7787 /* Likewise if it re-expanded the compound only partially.
7788 This happens for SUBREG of ZERO_EXTRACT if they extract
7789 the same number of bits. */
7790 || (GET_CODE (newer) == SUBREG
7791 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7792 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7793 && GET_CODE (inner) == AND
7794 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7795 return gen_lowpart (GET_MODE (x), tem);
7797 return newer;
7800 if (simplified)
7801 return tem;
7803 break;
7805 default:
7806 break;
7809 if (new_rtx)
7811 x = gen_lowpart (mode, new_rtx);
7812 code = GET_CODE (x);
7815 /* Now recursively process each operand of this operation. We need to
7816 handle ZERO_EXTEND specially so that we don't lose track of the
7817 inner mode. */
7818 if (GET_CODE (x) == ZERO_EXTEND)
7820 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7821 tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x),
7822 new_rtx, GET_MODE (XEXP (x, 0)));
7823 if (tem)
7824 return tem;
7825 SUBST (XEXP (x, 0), new_rtx);
7826 return x;
7829 fmt = GET_RTX_FORMAT (code);
7830 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7831 if (fmt[i] == 'e')
7833 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7834 SUBST (XEXP (x, i), new_rtx);
7836 else if (fmt[i] == 'E')
7837 for (j = 0; j < XVECLEN (x, i); j++)
7839 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7840 SUBST (XVECEXP (x, i, j), new_rtx);
7843 maybe_swap:
7844 /* If this is a commutative operation, the changes to the operands
7845 may have made it noncanonical. */
7846 if (COMMUTATIVE_ARITH_P (x)
7847 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7849 tem = XEXP (x, 0);
7850 SUBST (XEXP (x, 0), XEXP (x, 1));
7851 SUBST (XEXP (x, 1), tem);
7854 return x;
7857 /* Given M see if it is a value that would select a field of bits
7858 within an item, but not the entire word. Return -1 if not.
7859 Otherwise, return the starting position of the field, where 0 is the
7860 low-order bit.
7862 *PLEN is set to the length of the field. */
7864 static int
7865 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7867 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7868 int pos = m ? ctz_hwi (m) : -1;
7869 int len = 0;
7871 if (pos >= 0)
7872 /* Now shift off the low-order zero bits and see if we have a
7873 power of two minus 1. */
7874 len = exact_log2 ((m >> pos) + 1);
7876 if (len <= 0)
7877 pos = -1;
7879 *plen = len;
7880 return pos;
7883 /* If X refers to a register that equals REG in value, replace these
7884 references with REG. */
7885 static rtx
7886 canon_reg_for_combine (rtx x, rtx reg)
7888 rtx op0, op1, op2;
7889 const char *fmt;
7890 int i;
7891 bool copied;
7893 enum rtx_code code = GET_CODE (x);
7894 switch (GET_RTX_CLASS (code))
7896 case RTX_UNARY:
7897 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7898 if (op0 != XEXP (x, 0))
7899 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7900 GET_MODE (reg));
7901 break;
7903 case RTX_BIN_ARITH:
7904 case RTX_COMM_ARITH:
7905 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7906 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7907 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7908 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7909 break;
7911 case RTX_COMPARE:
7912 case RTX_COMM_COMPARE:
7913 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7914 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7915 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7916 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7917 GET_MODE (op0), op0, op1);
7918 break;
7920 case RTX_TERNARY:
7921 case RTX_BITFIELD_OPS:
7922 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7923 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7924 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7925 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7926 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7927 GET_MODE (op0), op0, op1, op2);
7929 case RTX_OBJ:
7930 if (REG_P (x))
7932 if (rtx_equal_p (get_last_value (reg), x)
7933 || rtx_equal_p (reg, get_last_value (x)))
7934 return reg;
7935 else
7936 break;
7939 /* fall through */
7941 default:
7942 fmt = GET_RTX_FORMAT (code);
7943 copied = false;
7944 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7945 if (fmt[i] == 'e')
7947 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7948 if (op != XEXP (x, i))
7950 if (!copied)
7952 copied = true;
7953 x = copy_rtx (x);
7955 XEXP (x, i) = op;
7958 else if (fmt[i] == 'E')
7960 int j;
7961 for (j = 0; j < XVECLEN (x, i); j++)
7963 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7964 if (op != XVECEXP (x, i, j))
7966 if (!copied)
7968 copied = true;
7969 x = copy_rtx (x);
7971 XVECEXP (x, i, j) = op;
7976 break;
7979 return x;
7982 /* Return X converted to MODE. If the value is already truncated to
7983 MODE we can just return a subreg even though in the general case we
7984 would need an explicit truncation. */
7986 static rtx
7987 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7989 if (!CONST_INT_P (x)
7990 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7991 && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
7992 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7994 /* Bit-cast X into an integer mode. */
7995 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7996 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7997 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7998 x, GET_MODE (x));
8001 return gen_lowpart (mode, x);
8004 /* See if X can be simplified knowing that we will only refer to it in
8005 MODE and will only refer to those bits that are nonzero in MASK.
8006 If other bits are being computed or if masking operations are done
8007 that select a superset of the bits in MASK, they can sometimes be
8008 ignored.
8010 Return a possibly simplified expression, but always convert X to
8011 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8013 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8014 are all off in X. This is used when X will be complemented, by either
8015 NOT, NEG, or XOR. */
8017 static rtx
8018 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
8019 int just_select)
8021 enum rtx_code code = GET_CODE (x);
8022 int next_select = just_select || code == XOR || code == NOT || code == NEG;
8023 enum machine_mode op_mode;
8024 unsigned HOST_WIDE_INT fuller_mask, nonzero;
8025 rtx op0, op1, temp;
8027 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8028 code below will do the wrong thing since the mode of such an
8029 expression is VOIDmode.
8031 Also do nothing if X is a CLOBBER; this can happen if X was
8032 the return value from a call to gen_lowpart. */
8033 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8034 return x;
8036 /* We want to perform the operation in its present mode unless we know
8037 that the operation is valid in MODE, in which case we do the operation
8038 in MODE. */
8039 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8040 && have_insn_for (code, mode))
8041 ? mode : GET_MODE (x));
8043 /* It is not valid to do a right-shift in a narrower mode
8044 than the one it came in with. */
8045 if ((code == LSHIFTRT || code == ASHIFTRT)
8046 && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (GET_MODE (x)))
8047 op_mode = GET_MODE (x);
8049 /* Truncate MASK to fit OP_MODE. */
8050 if (op_mode)
8051 mask &= GET_MODE_MASK (op_mode);
8053 /* When we have an arithmetic operation, or a shift whose count we
8054 do not know, we need to assume that all bits up to the highest-order
8055 bit in MASK will be needed. This is how we form such a mask. */
8056 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8057 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8058 else
8059 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8060 - 1);
8062 /* Determine what bits of X are guaranteed to be (non)zero. */
8063 nonzero = nonzero_bits (x, mode);
8065 /* If none of the bits in X are needed, return a zero. */
8066 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8067 x = const0_rtx;
8069 /* If X is a CONST_INT, return a new one. Do this here since the
8070 test below will fail. */
8071 if (CONST_INT_P (x))
8073 if (SCALAR_INT_MODE_P (mode))
8074 return gen_int_mode (INTVAL (x) & mask, mode);
8075 else
8077 x = GEN_INT (INTVAL (x) & mask);
8078 return gen_lowpart_common (mode, x);
8082 /* If X is narrower than MODE and we want all the bits in X's mode, just
8083 get X in the proper mode. */
8084 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8085 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8086 return gen_lowpart (mode, x);
8088 /* We can ignore the effect of a SUBREG if it narrows the mode or
8089 if the constant masks to zero all the bits the mode doesn't have. */
8090 if (GET_CODE (x) == SUBREG
8091 && subreg_lowpart_p (x)
8092 && ((GET_MODE_SIZE (GET_MODE (x))
8093 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8094 || (0 == (mask
8095 & GET_MODE_MASK (GET_MODE (x))
8096 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8097 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8099 /* The arithmetic simplifications here only work for scalar integer modes. */
8100 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8101 return gen_lowpart_or_truncate (mode, x);
8103 switch (code)
8105 case CLOBBER:
8106 /* If X is a (clobber (const_int)), return it since we know we are
8107 generating something that won't match. */
8108 return x;
8110 case SIGN_EXTEND:
8111 case ZERO_EXTEND:
8112 case ZERO_EXTRACT:
8113 case SIGN_EXTRACT:
8114 x = expand_compound_operation (x);
8115 if (GET_CODE (x) != code)
8116 return force_to_mode (x, mode, mask, next_select);
8117 break;
8119 case TRUNCATE:
8120 /* Similarly for a truncate. */
8121 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8123 case AND:
8124 /* If this is an AND with a constant, convert it into an AND
8125 whose constant is the AND of that constant with MASK. If it
8126 remains an AND of MASK, delete it since it is redundant. */
8128 if (CONST_INT_P (XEXP (x, 1)))
8130 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8131 mask & INTVAL (XEXP (x, 1)));
8133 /* If X is still an AND, see if it is an AND with a mask that
8134 is just some low-order bits. If so, and it is MASK, we don't
8135 need it. */
8137 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8138 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8139 == mask))
8140 x = XEXP (x, 0);
8142 /* If it remains an AND, try making another AND with the bits
8143 in the mode mask that aren't in MASK turned on. If the
8144 constant in the AND is wide enough, this might make a
8145 cheaper constant. */
8147 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8148 && GET_MODE_MASK (GET_MODE (x)) != mask
8149 && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
8151 unsigned HOST_WIDE_INT cval
8152 = UINTVAL (XEXP (x, 1))
8153 | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8154 rtx y;
8156 y = simplify_gen_binary (AND, GET_MODE (x), XEXP (x, 0),
8157 gen_int_mode (cval, GET_MODE (x)));
8158 if (set_src_cost (y, optimize_this_for_speed_p)
8159 < set_src_cost (x, optimize_this_for_speed_p))
8160 x = y;
8163 break;
8166 goto binop;
8168 case PLUS:
8169 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8170 low-order bits (as in an alignment operation) and FOO is already
8171 aligned to that boundary, mask C1 to that boundary as well.
8172 This may eliminate that PLUS and, later, the AND. */
8175 unsigned int width = GET_MODE_PRECISION (mode);
8176 unsigned HOST_WIDE_INT smask = mask;
8178 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8179 number, sign extend it. */
8181 if (width < HOST_BITS_PER_WIDE_INT
8182 && (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0)
8183 smask |= HOST_WIDE_INT_M1U << width;
8185 if (CONST_INT_P (XEXP (x, 1))
8186 && exact_log2 (- smask) >= 0
8187 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8188 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8189 return force_to_mode (plus_constant (GET_MODE (x), XEXP (x, 0),
8190 (INTVAL (XEXP (x, 1)) & smask)),
8191 mode, smask, next_select);
8194 /* ... fall through ... */
8196 case MULT:
8197 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8198 most significant bit in MASK since carries from those bits will
8199 affect the bits we are interested in. */
8200 mask = fuller_mask;
8201 goto binop;
8203 case MINUS:
8204 /* If X is (minus C Y) where C's least set bit is larger than any bit
8205 in the mask, then we may replace with (neg Y). */
8206 if (CONST_INT_P (XEXP (x, 0))
8207 && ((UINTVAL (XEXP (x, 0)) & -UINTVAL (XEXP (x, 0))) > mask))
8209 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8210 GET_MODE (x));
8211 return force_to_mode (x, mode, mask, next_select);
8214 /* Similarly, if C contains every bit in the fuller_mask, then we may
8215 replace with (not Y). */
8216 if (CONST_INT_P (XEXP (x, 0))
8217 && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8219 x = simplify_gen_unary (NOT, GET_MODE (x),
8220 XEXP (x, 1), GET_MODE (x));
8221 return force_to_mode (x, mode, mask, next_select);
8224 mask = fuller_mask;
8225 goto binop;
8227 case IOR:
8228 case XOR:
8229 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8230 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8231 operation which may be a bitfield extraction. Ensure that the
8232 constant we form is not wider than the mode of X. */
8234 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8235 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8236 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8237 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8238 && CONST_INT_P (XEXP (x, 1))
8239 && ((INTVAL (XEXP (XEXP (x, 0), 1))
8240 + floor_log2 (INTVAL (XEXP (x, 1))))
8241 < GET_MODE_PRECISION (GET_MODE (x)))
8242 && (UINTVAL (XEXP (x, 1))
8243 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8245 temp = gen_int_mode ((INTVAL (XEXP (x, 1)) & mask)
8246 << INTVAL (XEXP (XEXP (x, 0), 1)),
8247 GET_MODE (x));
8248 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8249 XEXP (XEXP (x, 0), 0), temp);
8250 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8251 XEXP (XEXP (x, 0), 1));
8252 return force_to_mode (x, mode, mask, next_select);
8255 binop:
8256 /* For most binary operations, just propagate into the operation and
8257 change the mode if we have an operation of that mode. */
8259 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8260 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8262 /* If we ended up truncating both operands, truncate the result of the
8263 operation instead. */
8264 if (GET_CODE (op0) == TRUNCATE
8265 && GET_CODE (op1) == TRUNCATE)
8267 op0 = XEXP (op0, 0);
8268 op1 = XEXP (op1, 0);
8271 op0 = gen_lowpart_or_truncate (op_mode, op0);
8272 op1 = gen_lowpart_or_truncate (op_mode, op1);
8274 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8275 x = simplify_gen_binary (code, op_mode, op0, op1);
8276 break;
8278 case ASHIFT:
8279 /* For left shifts, do the same, but just for the first operand.
8280 However, we cannot do anything with shifts where we cannot
8281 guarantee that the counts are smaller than the size of the mode
8282 because such a count will have a different meaning in a
8283 wider mode. */
8285 if (! (CONST_INT_P (XEXP (x, 1))
8286 && INTVAL (XEXP (x, 1)) >= 0
8287 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
8288 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8289 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8290 < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
8291 break;
8293 /* If the shift count is a constant and we can do arithmetic in
8294 the mode of the shift, refine which bits we need. Otherwise, use the
8295 conservative form of the mask. */
8296 if (CONST_INT_P (XEXP (x, 1))
8297 && INTVAL (XEXP (x, 1)) >= 0
8298 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
8299 && HWI_COMPUTABLE_MODE_P (op_mode))
8300 mask >>= INTVAL (XEXP (x, 1));
8301 else
8302 mask = fuller_mask;
8304 op0 = gen_lowpart_or_truncate (op_mode,
8305 force_to_mode (XEXP (x, 0), op_mode,
8306 mask, next_select));
8308 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8309 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8310 break;
8312 case LSHIFTRT:
8313 /* Here we can only do something if the shift count is a constant,
8314 this shift constant is valid for the host, and we can do arithmetic
8315 in OP_MODE. */
8317 if (CONST_INT_P (XEXP (x, 1))
8318 && INTVAL (XEXP (x, 1)) >= 0
8319 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8320 && HWI_COMPUTABLE_MODE_P (op_mode))
8322 rtx inner = XEXP (x, 0);
8323 unsigned HOST_WIDE_INT inner_mask;
8325 /* Select the mask of the bits we need for the shift operand. */
8326 inner_mask = mask << INTVAL (XEXP (x, 1));
8328 /* We can only change the mode of the shift if we can do arithmetic
8329 in the mode of the shift and INNER_MASK is no wider than the
8330 width of X's mode. */
8331 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8332 op_mode = GET_MODE (x);
8334 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8336 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8337 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8340 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8341 shift and AND produces only copies of the sign bit (C2 is one less
8342 than a power of two), we can do this with just a shift. */
8344 if (GET_CODE (x) == LSHIFTRT
8345 && CONST_INT_P (XEXP (x, 1))
8346 /* The shift puts one of the sign bit copies in the least significant
8347 bit. */
8348 && ((INTVAL (XEXP (x, 1))
8349 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8350 >= GET_MODE_PRECISION (GET_MODE (x)))
8351 && exact_log2 (mask + 1) >= 0
8352 /* Number of bits left after the shift must be more than the mask
8353 needs. */
8354 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8355 <= GET_MODE_PRECISION (GET_MODE (x)))
8356 /* Must be more sign bit copies than the mask needs. */
8357 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8358 >= exact_log2 (mask + 1)))
8359 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8360 GEN_INT (GET_MODE_PRECISION (GET_MODE (x))
8361 - exact_log2 (mask + 1)));
8363 goto shiftrt;
8365 case ASHIFTRT:
8366 /* If we are just looking for the sign bit, we don't need this shift at
8367 all, even if it has a variable count. */
8368 if (val_signbit_p (GET_MODE (x), mask))
8369 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8371 /* If this is a shift by a constant, get a mask that contains those bits
8372 that are not copies of the sign bit. We then have two cases: If
8373 MASK only includes those bits, this can be a logical shift, which may
8374 allow simplifications. If MASK is a single-bit field not within
8375 those bits, we are requesting a copy of the sign bit and hence can
8376 shift the sign bit to the appropriate location. */
8378 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8379 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8381 int i;
8383 /* If the considered data is wider than HOST_WIDE_INT, we can't
8384 represent a mask for all its bits in a single scalar.
8385 But we only care about the lower bits, so calculate these. */
8387 if (GET_MODE_PRECISION (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8389 nonzero = ~(unsigned HOST_WIDE_INT) 0;
8391 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8392 is the number of bits a full-width mask would have set.
8393 We need only shift if these are fewer than nonzero can
8394 hold. If not, we must keep all bits set in nonzero. */
8396 if (GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8397 < HOST_BITS_PER_WIDE_INT)
8398 nonzero >>= INTVAL (XEXP (x, 1))
8399 + HOST_BITS_PER_WIDE_INT
8400 - GET_MODE_PRECISION (GET_MODE (x)) ;
8402 else
8404 nonzero = GET_MODE_MASK (GET_MODE (x));
8405 nonzero >>= INTVAL (XEXP (x, 1));
8408 if ((mask & ~nonzero) == 0)
8410 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8411 XEXP (x, 0), INTVAL (XEXP (x, 1)));
8412 if (GET_CODE (x) != ASHIFTRT)
8413 return force_to_mode (x, mode, mask, next_select);
8416 else if ((i = exact_log2 (mask)) >= 0)
8418 x = simplify_shift_const
8419 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8420 GET_MODE_PRECISION (GET_MODE (x)) - 1 - i);
8422 if (GET_CODE (x) != ASHIFTRT)
8423 return force_to_mode (x, mode, mask, next_select);
8427 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8428 even if the shift count isn't a constant. */
8429 if (mask == 1)
8430 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8431 XEXP (x, 0), XEXP (x, 1));
8433 shiftrt:
8435 /* If this is a zero- or sign-extension operation that just affects bits
8436 we don't care about, remove it. Be sure the call above returned
8437 something that is still a shift. */
8439 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8440 && CONST_INT_P (XEXP (x, 1))
8441 && INTVAL (XEXP (x, 1)) >= 0
8442 && (INTVAL (XEXP (x, 1))
8443 <= GET_MODE_PRECISION (GET_MODE (x)) - (floor_log2 (mask) + 1))
8444 && GET_CODE (XEXP (x, 0)) == ASHIFT
8445 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8446 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8447 next_select);
8449 break;
8451 case ROTATE:
8452 case ROTATERT:
8453 /* If the shift count is constant and we can do computations
8454 in the mode of X, compute where the bits we care about are.
8455 Otherwise, we can't do anything. Don't change the mode of
8456 the shift or propagate MODE into the shift, though. */
8457 if (CONST_INT_P (XEXP (x, 1))
8458 && INTVAL (XEXP (x, 1)) >= 0)
8460 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8461 GET_MODE (x),
8462 gen_int_mode (mask, GET_MODE (x)),
8463 XEXP (x, 1));
8464 if (temp && CONST_INT_P (temp))
8465 x = simplify_gen_binary (code, GET_MODE (x),
8466 force_to_mode (XEXP (x, 0), GET_MODE (x),
8467 INTVAL (temp), next_select),
8468 XEXP (x, 1));
8470 break;
8472 case NEG:
8473 /* If we just want the low-order bit, the NEG isn't needed since it
8474 won't change the low-order bit. */
8475 if (mask == 1)
8476 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8478 /* We need any bits less significant than the most significant bit in
8479 MASK since carries from those bits will affect the bits we are
8480 interested in. */
8481 mask = fuller_mask;
8482 goto unop;
8484 case NOT:
8485 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8486 same as the XOR case above. Ensure that the constant we form is not
8487 wider than the mode of X. */
8489 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8490 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8491 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8492 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8493 < GET_MODE_PRECISION (GET_MODE (x)))
8494 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8496 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8497 GET_MODE (x));
8498 temp = simplify_gen_binary (XOR, GET_MODE (x),
8499 XEXP (XEXP (x, 0), 0), temp);
8500 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8501 temp, XEXP (XEXP (x, 0), 1));
8503 return force_to_mode (x, mode, mask, next_select);
8506 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8507 use the full mask inside the NOT. */
8508 mask = fuller_mask;
8510 unop:
8511 op0 = gen_lowpart_or_truncate (op_mode,
8512 force_to_mode (XEXP (x, 0), mode, mask,
8513 next_select));
8514 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8515 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8516 break;
8518 case NE:
8519 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8520 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8521 which is equal to STORE_FLAG_VALUE. */
8522 if ((mask & ~STORE_FLAG_VALUE) == 0
8523 && XEXP (x, 1) == const0_rtx
8524 && GET_MODE (XEXP (x, 0)) == mode
8525 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8526 && (nonzero_bits (XEXP (x, 0), mode)
8527 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8528 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8530 break;
8532 case IF_THEN_ELSE:
8533 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8534 written in a narrower mode. We play it safe and do not do so. */
8536 op0 = gen_lowpart_or_truncate (GET_MODE (x),
8537 force_to_mode (XEXP (x, 1), mode,
8538 mask, next_select));
8539 op1 = gen_lowpart_or_truncate (GET_MODE (x),
8540 force_to_mode (XEXP (x, 2), mode,
8541 mask, next_select));
8542 if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2))
8543 x = simplify_gen_ternary (IF_THEN_ELSE, GET_MODE (x),
8544 GET_MODE (XEXP (x, 0)), XEXP (x, 0),
8545 op0, op1);
8546 break;
8548 default:
8549 break;
8552 /* Ensure we return a value of the proper mode. */
8553 return gen_lowpart_or_truncate (mode, x);
8556 /* Return nonzero if X is an expression that has one of two values depending on
8557 whether some other value is zero or nonzero. In that case, we return the
8558 value that is being tested, *PTRUE is set to the value if the rtx being
8559 returned has a nonzero value, and *PFALSE is set to the other alternative.
8561 If we return zero, we set *PTRUE and *PFALSE to X. */
8563 static rtx
8564 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8566 enum machine_mode mode = GET_MODE (x);
8567 enum rtx_code code = GET_CODE (x);
8568 rtx cond0, cond1, true0, true1, false0, false1;
8569 unsigned HOST_WIDE_INT nz;
8571 /* If we are comparing a value against zero, we are done. */
8572 if ((code == NE || code == EQ)
8573 && XEXP (x, 1) == const0_rtx)
8575 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8576 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8577 return XEXP (x, 0);
8580 /* If this is a unary operation whose operand has one of two values, apply
8581 our opcode to compute those values. */
8582 else if (UNARY_P (x)
8583 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8585 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8586 *pfalse = simplify_gen_unary (code, mode, false0,
8587 GET_MODE (XEXP (x, 0)));
8588 return cond0;
8591 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8592 make can't possibly match and would suppress other optimizations. */
8593 else if (code == COMPARE)
8596 /* If this is a binary operation, see if either side has only one of two
8597 values. If either one does or if both do and they are conditional on
8598 the same value, compute the new true and false values. */
8599 else if (BINARY_P (x))
8601 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8602 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8604 if ((cond0 != 0 || cond1 != 0)
8605 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8607 /* If if_then_else_cond returned zero, then true/false are the
8608 same rtl. We must copy one of them to prevent invalid rtl
8609 sharing. */
8610 if (cond0 == 0)
8611 true0 = copy_rtx (true0);
8612 else if (cond1 == 0)
8613 true1 = copy_rtx (true1);
8615 if (COMPARISON_P (x))
8617 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8618 true0, true1);
8619 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8620 false0, false1);
8622 else
8624 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8625 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8628 return cond0 ? cond0 : cond1;
8631 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8632 operands is zero when the other is nonzero, and vice-versa,
8633 and STORE_FLAG_VALUE is 1 or -1. */
8635 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8636 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8637 || code == UMAX)
8638 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8640 rtx op0 = XEXP (XEXP (x, 0), 1);
8641 rtx op1 = XEXP (XEXP (x, 1), 1);
8643 cond0 = XEXP (XEXP (x, 0), 0);
8644 cond1 = XEXP (XEXP (x, 1), 0);
8646 if (COMPARISON_P (cond0)
8647 && COMPARISON_P (cond1)
8648 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8649 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8650 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8651 || ((swap_condition (GET_CODE (cond0))
8652 == reversed_comparison_code (cond1, NULL))
8653 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8654 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8655 && ! side_effects_p (x))
8657 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8658 *pfalse = simplify_gen_binary (MULT, mode,
8659 (code == MINUS
8660 ? simplify_gen_unary (NEG, mode,
8661 op1, mode)
8662 : op1),
8663 const_true_rtx);
8664 return cond0;
8668 /* Similarly for MULT, AND and UMIN, except that for these the result
8669 is always zero. */
8670 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8671 && (code == MULT || code == AND || code == UMIN)
8672 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8674 cond0 = XEXP (XEXP (x, 0), 0);
8675 cond1 = XEXP (XEXP (x, 1), 0);
8677 if (COMPARISON_P (cond0)
8678 && COMPARISON_P (cond1)
8679 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8680 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8681 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8682 || ((swap_condition (GET_CODE (cond0))
8683 == reversed_comparison_code (cond1, NULL))
8684 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8685 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8686 && ! side_effects_p (x))
8688 *ptrue = *pfalse = const0_rtx;
8689 return cond0;
8694 else if (code == IF_THEN_ELSE)
8696 /* If we have IF_THEN_ELSE already, extract the condition and
8697 canonicalize it if it is NE or EQ. */
8698 cond0 = XEXP (x, 0);
8699 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8700 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8701 return XEXP (cond0, 0);
8702 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8704 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8705 return XEXP (cond0, 0);
8707 else
8708 return cond0;
8711 /* If X is a SUBREG, we can narrow both the true and false values
8712 if the inner expression, if there is a condition. */
8713 else if (code == SUBREG
8714 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8715 &true0, &false0)))
8717 true0 = simplify_gen_subreg (mode, true0,
8718 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8719 false0 = simplify_gen_subreg (mode, false0,
8720 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8721 if (true0 && false0)
8723 *ptrue = true0;
8724 *pfalse = false0;
8725 return cond0;
8729 /* If X is a constant, this isn't special and will cause confusions
8730 if we treat it as such. Likewise if it is equivalent to a constant. */
8731 else if (CONSTANT_P (x)
8732 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8735 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8736 will be least confusing to the rest of the compiler. */
8737 else if (mode == BImode)
8739 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8740 return x;
8743 /* If X is known to be either 0 or -1, those are the true and
8744 false values when testing X. */
8745 else if (x == constm1_rtx || x == const0_rtx
8746 || (mode != VOIDmode
8747 && num_sign_bit_copies (x, mode) == GET_MODE_PRECISION (mode)))
8749 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8750 return x;
8753 /* Likewise for 0 or a single bit. */
8754 else if (HWI_COMPUTABLE_MODE_P (mode)
8755 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8757 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8758 return x;
8761 /* Otherwise fail; show no condition with true and false values the same. */
8762 *ptrue = *pfalse = x;
8763 return 0;
8766 /* Return the value of expression X given the fact that condition COND
8767 is known to be true when applied to REG as its first operand and VAL
8768 as its second. X is known to not be shared and so can be modified in
8769 place.
8771 We only handle the simplest cases, and specifically those cases that
8772 arise with IF_THEN_ELSE expressions. */
8774 static rtx
8775 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8777 enum rtx_code code = GET_CODE (x);
8778 rtx temp;
8779 const char *fmt;
8780 int i, j;
8782 if (side_effects_p (x))
8783 return x;
8785 /* If either operand of the condition is a floating point value,
8786 then we have to avoid collapsing an EQ comparison. */
8787 if (cond == EQ
8788 && rtx_equal_p (x, reg)
8789 && ! FLOAT_MODE_P (GET_MODE (x))
8790 && ! FLOAT_MODE_P (GET_MODE (val)))
8791 return val;
8793 if (cond == UNEQ && rtx_equal_p (x, reg))
8794 return val;
8796 /* If X is (abs REG) and we know something about REG's relationship
8797 with zero, we may be able to simplify this. */
8799 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8800 switch (cond)
8802 case GE: case GT: case EQ:
8803 return XEXP (x, 0);
8804 case LT: case LE:
8805 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8806 XEXP (x, 0),
8807 GET_MODE (XEXP (x, 0)));
8808 default:
8809 break;
8812 /* The only other cases we handle are MIN, MAX, and comparisons if the
8813 operands are the same as REG and VAL. */
8815 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8817 if (rtx_equal_p (XEXP (x, 0), val))
8818 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8820 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8822 if (COMPARISON_P (x))
8824 if (comparison_dominates_p (cond, code))
8825 return const_true_rtx;
8827 code = reversed_comparison_code (x, NULL);
8828 if (code != UNKNOWN
8829 && comparison_dominates_p (cond, code))
8830 return const0_rtx;
8831 else
8832 return x;
8834 else if (code == SMAX || code == SMIN
8835 || code == UMIN || code == UMAX)
8837 int unsignedp = (code == UMIN || code == UMAX);
8839 /* Do not reverse the condition when it is NE or EQ.
8840 This is because we cannot conclude anything about
8841 the value of 'SMAX (x, y)' when x is not equal to y,
8842 but we can when x equals y. */
8843 if ((code == SMAX || code == UMAX)
8844 && ! (cond == EQ || cond == NE))
8845 cond = reverse_condition (cond);
8847 switch (cond)
8849 case GE: case GT:
8850 return unsignedp ? x : XEXP (x, 1);
8851 case LE: case LT:
8852 return unsignedp ? x : XEXP (x, 0);
8853 case GEU: case GTU:
8854 return unsignedp ? XEXP (x, 1) : x;
8855 case LEU: case LTU:
8856 return unsignedp ? XEXP (x, 0) : x;
8857 default:
8858 break;
8863 else if (code == SUBREG)
8865 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8866 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8868 if (SUBREG_REG (x) != r)
8870 /* We must simplify subreg here, before we lose track of the
8871 original inner_mode. */
8872 new_rtx = simplify_subreg (GET_MODE (x), r,
8873 inner_mode, SUBREG_BYTE (x));
8874 if (new_rtx)
8875 return new_rtx;
8876 else
8877 SUBST (SUBREG_REG (x), r);
8880 return x;
8882 /* We don't have to handle SIGN_EXTEND here, because even in the
8883 case of replacing something with a modeless CONST_INT, a
8884 CONST_INT is already (supposed to be) a valid sign extension for
8885 its narrower mode, which implies it's already properly
8886 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8887 story is different. */
8888 else if (code == ZERO_EXTEND)
8890 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8891 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8893 if (XEXP (x, 0) != r)
8895 /* We must simplify the zero_extend here, before we lose
8896 track of the original inner_mode. */
8897 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8898 r, inner_mode);
8899 if (new_rtx)
8900 return new_rtx;
8901 else
8902 SUBST (XEXP (x, 0), r);
8905 return x;
8908 fmt = GET_RTX_FORMAT (code);
8909 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8911 if (fmt[i] == 'e')
8912 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8913 else if (fmt[i] == 'E')
8914 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8915 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8916 cond, reg, val));
8919 return x;
8922 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8923 assignment as a field assignment. */
8925 static int
8926 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8928 if (x == y || rtx_equal_p (x, y))
8929 return 1;
8931 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8932 return 0;
8934 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8935 Note that all SUBREGs of MEM are paradoxical; otherwise they
8936 would have been rewritten. */
8937 if (MEM_P (x) && GET_CODE (y) == SUBREG
8938 && MEM_P (SUBREG_REG (y))
8939 && rtx_equal_p (SUBREG_REG (y),
8940 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8941 return 1;
8943 if (MEM_P (y) && GET_CODE (x) == SUBREG
8944 && MEM_P (SUBREG_REG (x))
8945 && rtx_equal_p (SUBREG_REG (x),
8946 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8947 return 1;
8949 /* We used to see if get_last_value of X and Y were the same but that's
8950 not correct. In one direction, we'll cause the assignment to have
8951 the wrong destination and in the case, we'll import a register into this
8952 insn that might have already have been dead. So fail if none of the
8953 above cases are true. */
8954 return 0;
8957 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8958 Return that assignment if so.
8960 We only handle the most common cases. */
8962 static rtx
8963 make_field_assignment (rtx x)
8965 rtx dest = SET_DEST (x);
8966 rtx src = SET_SRC (x);
8967 rtx assign;
8968 rtx rhs, lhs;
8969 HOST_WIDE_INT c1;
8970 HOST_WIDE_INT pos;
8971 unsigned HOST_WIDE_INT len;
8972 rtx other;
8973 enum machine_mode mode;
8975 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8976 a clear of a one-bit field. We will have changed it to
8977 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8978 for a SUBREG. */
8980 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8981 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8982 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8983 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8985 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8986 1, 1, 1, 0);
8987 if (assign != 0)
8988 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8989 return x;
8992 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8993 && subreg_lowpart_p (XEXP (src, 0))
8994 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8995 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8996 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8997 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8998 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8999 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9001 assign = make_extraction (VOIDmode, dest, 0,
9002 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9003 1, 1, 1, 0);
9004 if (assign != 0)
9005 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9006 return x;
9009 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9010 one-bit field. */
9011 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9012 && XEXP (XEXP (src, 0), 0) == const1_rtx
9013 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9015 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9016 1, 1, 1, 0);
9017 if (assign != 0)
9018 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
9019 return x;
9022 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9023 SRC is an AND with all bits of that field set, then we can discard
9024 the AND. */
9025 if (GET_CODE (dest) == ZERO_EXTRACT
9026 && CONST_INT_P (XEXP (dest, 1))
9027 && GET_CODE (src) == AND
9028 && CONST_INT_P (XEXP (src, 1)))
9030 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9031 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9032 unsigned HOST_WIDE_INT ze_mask;
9034 if (width >= HOST_BITS_PER_WIDE_INT)
9035 ze_mask = -1;
9036 else
9037 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9039 /* Complete overlap. We can remove the source AND. */
9040 if ((and_mask & ze_mask) == ze_mask)
9041 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9043 /* Partial overlap. We can reduce the source AND. */
9044 if ((and_mask & ze_mask) != and_mask)
9046 mode = GET_MODE (src);
9047 src = gen_rtx_AND (mode, XEXP (src, 0),
9048 gen_int_mode (and_mask & ze_mask, mode));
9049 return gen_rtx_SET (VOIDmode, dest, src);
9053 /* The other case we handle is assignments into a constant-position
9054 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9055 a mask that has all one bits except for a group of zero bits and
9056 OTHER is known to have zeros where C1 has ones, this is such an
9057 assignment. Compute the position and length from C1. Shift OTHER
9058 to the appropriate position, force it to the required mode, and
9059 make the extraction. Check for the AND in both operands. */
9061 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9062 return x;
9064 rhs = expand_compound_operation (XEXP (src, 0));
9065 lhs = expand_compound_operation (XEXP (src, 1));
9067 if (GET_CODE (rhs) == AND
9068 && CONST_INT_P (XEXP (rhs, 1))
9069 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9070 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9071 else if (GET_CODE (lhs) == AND
9072 && CONST_INT_P (XEXP (lhs, 1))
9073 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9074 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9075 else
9076 return x;
9078 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9079 if (pos < 0 || pos + len > GET_MODE_PRECISION (GET_MODE (dest))
9080 || GET_MODE_PRECISION (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9081 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9082 return x;
9084 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9085 if (assign == 0)
9086 return x;
9088 /* The mode to use for the source is the mode of the assignment, or of
9089 what is inside a possible STRICT_LOW_PART. */
9090 mode = (GET_CODE (assign) == STRICT_LOW_PART
9091 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9093 /* Shift OTHER right POS places and make it the source, restricting it
9094 to the proper length and mode. */
9096 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9097 GET_MODE (src),
9098 other, pos),
9099 dest);
9100 src = force_to_mode (src, mode,
9101 GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT
9102 ? ~(unsigned HOST_WIDE_INT) 0
9103 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9106 /* If SRC is masked by an AND that does not make a difference in
9107 the value being stored, strip it. */
9108 if (GET_CODE (assign) == ZERO_EXTRACT
9109 && CONST_INT_P (XEXP (assign, 1))
9110 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9111 && GET_CODE (src) == AND
9112 && CONST_INT_P (XEXP (src, 1))
9113 && UINTVAL (XEXP (src, 1))
9114 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9115 src = XEXP (src, 0);
9117 return gen_rtx_SET (VOIDmode, assign, src);
9120 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9121 if so. */
9123 static rtx
9124 apply_distributive_law (rtx x)
9126 enum rtx_code code = GET_CODE (x);
9127 enum rtx_code inner_code;
9128 rtx lhs, rhs, other;
9129 rtx tem;
9131 /* Distributivity is not true for floating point as it can change the
9132 value. So we don't do it unless -funsafe-math-optimizations. */
9133 if (FLOAT_MODE_P (GET_MODE (x))
9134 && ! flag_unsafe_math_optimizations)
9135 return x;
9137 /* The outer operation can only be one of the following: */
9138 if (code != IOR && code != AND && code != XOR
9139 && code != PLUS && code != MINUS)
9140 return x;
9142 lhs = XEXP (x, 0);
9143 rhs = XEXP (x, 1);
9145 /* If either operand is a primitive we can't do anything, so get out
9146 fast. */
9147 if (OBJECT_P (lhs) || OBJECT_P (rhs))
9148 return x;
9150 lhs = expand_compound_operation (lhs);
9151 rhs = expand_compound_operation (rhs);
9152 inner_code = GET_CODE (lhs);
9153 if (inner_code != GET_CODE (rhs))
9154 return x;
9156 /* See if the inner and outer operations distribute. */
9157 switch (inner_code)
9159 case LSHIFTRT:
9160 case ASHIFTRT:
9161 case AND:
9162 case IOR:
9163 /* These all distribute except over PLUS. */
9164 if (code == PLUS || code == MINUS)
9165 return x;
9166 break;
9168 case MULT:
9169 if (code != PLUS && code != MINUS)
9170 return x;
9171 break;
9173 case ASHIFT:
9174 /* This is also a multiply, so it distributes over everything. */
9175 break;
9177 /* This used to handle SUBREG, but this turned out to be counter-
9178 productive, since (subreg (op ...)) usually is not handled by
9179 insn patterns, and this "optimization" therefore transformed
9180 recognizable patterns into unrecognizable ones. Therefore the
9181 SUBREG case was removed from here.
9183 It is possible that distributing SUBREG over arithmetic operations
9184 leads to an intermediate result than can then be optimized further,
9185 e.g. by moving the outer SUBREG to the other side of a SET as done
9186 in simplify_set. This seems to have been the original intent of
9187 handling SUBREGs here.
9189 However, with current GCC this does not appear to actually happen,
9190 at least on major platforms. If some case is found where removing
9191 the SUBREG case here prevents follow-on optimizations, distributing
9192 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9194 default:
9195 return x;
9198 /* Set LHS and RHS to the inner operands (A and B in the example
9199 above) and set OTHER to the common operand (C in the example).
9200 There is only one way to do this unless the inner operation is
9201 commutative. */
9202 if (COMMUTATIVE_ARITH_P (lhs)
9203 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9204 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9205 else if (COMMUTATIVE_ARITH_P (lhs)
9206 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9207 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9208 else if (COMMUTATIVE_ARITH_P (lhs)
9209 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9210 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9211 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9212 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9213 else
9214 return x;
9216 /* Form the new inner operation, seeing if it simplifies first. */
9217 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9219 /* There is one exception to the general way of distributing:
9220 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9221 if (code == XOR && inner_code == IOR)
9223 inner_code = AND;
9224 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9227 /* We may be able to continuing distributing the result, so call
9228 ourselves recursively on the inner operation before forming the
9229 outer operation, which we return. */
9230 return simplify_gen_binary (inner_code, GET_MODE (x),
9231 apply_distributive_law (tem), other);
9234 /* See if X is of the form (* (+ A B) C), and if so convert to
9235 (+ (* A C) (* B C)) and try to simplify.
9237 Most of the time, this results in no change. However, if some of
9238 the operands are the same or inverses of each other, simplifications
9239 will result.
9241 For example, (and (ior A B) (not B)) can occur as the result of
9242 expanding a bit field assignment. When we apply the distributive
9243 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9244 which then simplifies to (and (A (not B))).
9246 Note that no checks happen on the validity of applying the inverse
9247 distributive law. This is pointless since we can do it in the
9248 few places where this routine is called.
9250 N is the index of the term that is decomposed (the arithmetic operation,
9251 i.e. (+ A B) in the first example above). !N is the index of the term that
9252 is distributed, i.e. of C in the first example above. */
9253 static rtx
9254 distribute_and_simplify_rtx (rtx x, int n)
9256 enum machine_mode mode;
9257 enum rtx_code outer_code, inner_code;
9258 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9260 /* Distributivity is not true for floating point as it can change the
9261 value. So we don't do it unless -funsafe-math-optimizations. */
9262 if (FLOAT_MODE_P (GET_MODE (x))
9263 && ! flag_unsafe_math_optimizations)
9264 return NULL_RTX;
9266 decomposed = XEXP (x, n);
9267 if (!ARITHMETIC_P (decomposed))
9268 return NULL_RTX;
9270 mode = GET_MODE (x);
9271 outer_code = GET_CODE (x);
9272 distributed = XEXP (x, !n);
9274 inner_code = GET_CODE (decomposed);
9275 inner_op0 = XEXP (decomposed, 0);
9276 inner_op1 = XEXP (decomposed, 1);
9278 /* Special case (and (xor B C) (not A)), which is equivalent to
9279 (xor (ior A B) (ior A C)) */
9280 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9282 distributed = XEXP (distributed, 0);
9283 outer_code = IOR;
9286 if (n == 0)
9288 /* Distribute the second term. */
9289 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9290 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9292 else
9294 /* Distribute the first term. */
9295 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9296 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9299 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9300 new_op0, new_op1));
9301 if (GET_CODE (tmp) != outer_code
9302 && (set_src_cost (tmp, optimize_this_for_speed_p)
9303 < set_src_cost (x, optimize_this_for_speed_p)))
9304 return tmp;
9306 return NULL_RTX;
9309 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9310 in MODE. Return an equivalent form, if different from (and VAROP
9311 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9313 static rtx
9314 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9315 unsigned HOST_WIDE_INT constop)
9317 unsigned HOST_WIDE_INT nonzero;
9318 unsigned HOST_WIDE_INT orig_constop;
9319 rtx orig_varop;
9320 int i;
9322 orig_varop = varop;
9323 orig_constop = constop;
9324 if (GET_CODE (varop) == CLOBBER)
9325 return NULL_RTX;
9327 /* Simplify VAROP knowing that we will be only looking at some of the
9328 bits in it.
9330 Note by passing in CONSTOP, we guarantee that the bits not set in
9331 CONSTOP are not significant and will never be examined. We must
9332 ensure that is the case by explicitly masking out those bits
9333 before returning. */
9334 varop = force_to_mode (varop, mode, constop, 0);
9336 /* If VAROP is a CLOBBER, we will fail so return it. */
9337 if (GET_CODE (varop) == CLOBBER)
9338 return varop;
9340 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9341 to VAROP and return the new constant. */
9342 if (CONST_INT_P (varop))
9343 return gen_int_mode (INTVAL (varop) & constop, mode);
9345 /* See what bits may be nonzero in VAROP. Unlike the general case of
9346 a call to nonzero_bits, here we don't care about bits outside
9347 MODE. */
9349 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9351 /* Turn off all bits in the constant that are known to already be zero.
9352 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9353 which is tested below. */
9355 constop &= nonzero;
9357 /* If we don't have any bits left, return zero. */
9358 if (constop == 0)
9359 return const0_rtx;
9361 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9362 a power of two, we can replace this with an ASHIFT. */
9363 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9364 && (i = exact_log2 (constop)) >= 0)
9365 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9367 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9368 or XOR, then try to apply the distributive law. This may eliminate
9369 operations if either branch can be simplified because of the AND.
9370 It may also make some cases more complex, but those cases probably
9371 won't match a pattern either with or without this. */
9373 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9374 return
9375 gen_lowpart
9376 (mode,
9377 apply_distributive_law
9378 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9379 simplify_and_const_int (NULL_RTX,
9380 GET_MODE (varop),
9381 XEXP (varop, 0),
9382 constop),
9383 simplify_and_const_int (NULL_RTX,
9384 GET_MODE (varop),
9385 XEXP (varop, 1),
9386 constop))));
9388 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9389 the AND and see if one of the operands simplifies to zero. If so, we
9390 may eliminate it. */
9392 if (GET_CODE (varop) == PLUS
9393 && exact_log2 (constop + 1) >= 0)
9395 rtx o0, o1;
9397 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9398 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9399 if (o0 == const0_rtx)
9400 return o1;
9401 if (o1 == const0_rtx)
9402 return o0;
9405 /* Make a SUBREG if necessary. If we can't make it, fail. */
9406 varop = gen_lowpart (mode, varop);
9407 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9408 return NULL_RTX;
9410 /* If we are only masking insignificant bits, return VAROP. */
9411 if (constop == nonzero)
9412 return varop;
9414 if (varop == orig_varop && constop == orig_constop)
9415 return NULL_RTX;
9417 /* Otherwise, return an AND. */
9418 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9422 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9423 in MODE.
9425 Return an equivalent form, if different from X. Otherwise, return X. If
9426 X is zero, we are to always construct the equivalent form. */
9428 static rtx
9429 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9430 unsigned HOST_WIDE_INT constop)
9432 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9433 if (tem)
9434 return tem;
9436 if (!x)
9437 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9438 gen_int_mode (constop, mode));
9439 if (GET_MODE (x) != mode)
9440 x = gen_lowpart (mode, x);
9441 return x;
9444 /* Given a REG, X, compute which bits in X can be nonzero.
9445 We don't care about bits outside of those defined in MODE.
9447 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9448 a shift, AND, or zero_extract, we can do better. */
9450 static rtx
9451 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9452 const_rtx known_x ATTRIBUTE_UNUSED,
9453 enum machine_mode known_mode ATTRIBUTE_UNUSED,
9454 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9455 unsigned HOST_WIDE_INT *nonzero)
9457 rtx tem;
9458 reg_stat_type *rsp;
9460 /* If X is a register whose nonzero bits value is current, use it.
9461 Otherwise, if X is a register whose value we can find, use that
9462 value. Otherwise, use the previously-computed global nonzero bits
9463 for this register. */
9465 rsp = &reg_stat[REGNO (x)];
9466 if (rsp->last_set_value != 0
9467 && (rsp->last_set_mode == mode
9468 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9469 && GET_MODE_CLASS (mode) == MODE_INT))
9470 && ((rsp->last_set_label >= label_tick_ebb_start
9471 && rsp->last_set_label < label_tick)
9472 || (rsp->last_set_label == label_tick
9473 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9474 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9475 && REG_N_SETS (REGNO (x)) == 1
9476 && !REGNO_REG_SET_P
9477 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
9478 REGNO (x)))))
9480 unsigned HOST_WIDE_INT mask = rsp->last_set_nonzero_bits;
9482 if (GET_MODE_PRECISION (rsp->last_set_mode) < GET_MODE_PRECISION (mode))
9483 /* We don't know anything about the upper bits. */
9484 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (rsp->last_set_mode);
9486 *nonzero &= mask;
9487 return NULL;
9490 tem = get_last_value (x);
9492 if (tem)
9494 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9495 /* If X is narrower than MODE and TEM is a non-negative
9496 constant that would appear negative in the mode of X,
9497 sign-extend it for use in reg_nonzero_bits because some
9498 machines (maybe most) will actually do the sign-extension
9499 and this is the conservative approach.
9501 ??? For 2.5, try to tighten up the MD files in this regard
9502 instead of this kludge. */
9504 if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode)
9505 && CONST_INT_P (tem)
9506 && INTVAL (tem) > 0
9507 && val_signbit_known_set_p (GET_MODE (x), INTVAL (tem)))
9508 tem = GEN_INT (INTVAL (tem) | ~GET_MODE_MASK (GET_MODE (x)));
9509 #endif
9510 return tem;
9512 else if (nonzero_sign_valid && rsp->nonzero_bits)
9514 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9516 if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode))
9517 /* We don't know anything about the upper bits. */
9518 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9520 *nonzero &= mask;
9523 return NULL;
9526 /* Return the number of bits at the high-order end of X that are known to
9527 be equal to the sign bit. X will be used in mode MODE; if MODE is
9528 VOIDmode, X will be used in its own mode. The returned value will always
9529 be between 1 and the number of bits in MODE. */
9531 static rtx
9532 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9533 const_rtx known_x ATTRIBUTE_UNUSED,
9534 enum machine_mode known_mode
9535 ATTRIBUTE_UNUSED,
9536 unsigned int known_ret ATTRIBUTE_UNUSED,
9537 unsigned int *result)
9539 rtx tem;
9540 reg_stat_type *rsp;
9542 rsp = &reg_stat[REGNO (x)];
9543 if (rsp->last_set_value != 0
9544 && rsp->last_set_mode == mode
9545 && ((rsp->last_set_label >= label_tick_ebb_start
9546 && rsp->last_set_label < label_tick)
9547 || (rsp->last_set_label == label_tick
9548 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9549 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9550 && REG_N_SETS (REGNO (x)) == 1
9551 && !REGNO_REG_SET_P
9552 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
9553 REGNO (x)))))
9555 *result = rsp->last_set_sign_bit_copies;
9556 return NULL;
9559 tem = get_last_value (x);
9560 if (tem != 0)
9561 return tem;
9563 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9564 && GET_MODE_PRECISION (GET_MODE (x)) == GET_MODE_PRECISION (mode))
9565 *result = rsp->sign_bit_copies;
9567 return NULL;
9570 /* Return the number of "extended" bits there are in X, when interpreted
9571 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9572 unsigned quantities, this is the number of high-order zero bits.
9573 For signed quantities, this is the number of copies of the sign bit
9574 minus 1. In both case, this function returns the number of "spare"
9575 bits. For example, if two quantities for which this function returns
9576 at least 1 are added, the addition is known not to overflow.
9578 This function will always return 0 unless called during combine, which
9579 implies that it must be called from a define_split. */
9581 unsigned int
9582 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9584 if (nonzero_sign_valid == 0)
9585 return 0;
9587 return (unsignedp
9588 ? (HWI_COMPUTABLE_MODE_P (mode)
9589 ? (unsigned int) (GET_MODE_PRECISION (mode) - 1
9590 - floor_log2 (nonzero_bits (x, mode)))
9591 : 0)
9592 : num_sign_bit_copies (x, mode) - 1);
9595 /* This function is called from `simplify_shift_const' to merge two
9596 outer operations. Specifically, we have already found that we need
9597 to perform operation *POP0 with constant *PCONST0 at the outermost
9598 position. We would now like to also perform OP1 with constant CONST1
9599 (with *POP0 being done last).
9601 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9602 the resulting operation. *PCOMP_P is set to 1 if we would need to
9603 complement the innermost operand, otherwise it is unchanged.
9605 MODE is the mode in which the operation will be done. No bits outside
9606 the width of this mode matter. It is assumed that the width of this mode
9607 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9609 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9610 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9611 result is simply *PCONST0.
9613 If the resulting operation cannot be expressed as one operation, we
9614 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9616 static int
9617 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9619 enum rtx_code op0 = *pop0;
9620 HOST_WIDE_INT const0 = *pconst0;
9622 const0 &= GET_MODE_MASK (mode);
9623 const1 &= GET_MODE_MASK (mode);
9625 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9626 if (op0 == AND)
9627 const1 &= const0;
9629 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9630 if OP0 is SET. */
9632 if (op1 == UNKNOWN || op0 == SET)
9633 return 1;
9635 else if (op0 == UNKNOWN)
9636 op0 = op1, const0 = const1;
9638 else if (op0 == op1)
9640 switch (op0)
9642 case AND:
9643 const0 &= const1;
9644 break;
9645 case IOR:
9646 const0 |= const1;
9647 break;
9648 case XOR:
9649 const0 ^= const1;
9650 break;
9651 case PLUS:
9652 const0 += const1;
9653 break;
9654 case NEG:
9655 op0 = UNKNOWN;
9656 break;
9657 default:
9658 break;
9662 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9663 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9664 return 0;
9666 /* If the two constants aren't the same, we can't do anything. The
9667 remaining six cases can all be done. */
9668 else if (const0 != const1)
9669 return 0;
9671 else
9672 switch (op0)
9674 case IOR:
9675 if (op1 == AND)
9676 /* (a & b) | b == b */
9677 op0 = SET;
9678 else /* op1 == XOR */
9679 /* (a ^ b) | b == a | b */
9681 break;
9683 case XOR:
9684 if (op1 == AND)
9685 /* (a & b) ^ b == (~a) & b */
9686 op0 = AND, *pcomp_p = 1;
9687 else /* op1 == IOR */
9688 /* (a | b) ^ b == a & ~b */
9689 op0 = AND, const0 = ~const0;
9690 break;
9692 case AND:
9693 if (op1 == IOR)
9694 /* (a | b) & b == b */
9695 op0 = SET;
9696 else /* op1 == XOR */
9697 /* (a ^ b) & b) == (~a) & b */
9698 *pcomp_p = 1;
9699 break;
9700 default:
9701 break;
9704 /* Check for NO-OP cases. */
9705 const0 &= GET_MODE_MASK (mode);
9706 if (const0 == 0
9707 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9708 op0 = UNKNOWN;
9709 else if (const0 == 0 && op0 == AND)
9710 op0 = SET;
9711 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9712 && op0 == AND)
9713 op0 = UNKNOWN;
9715 *pop0 = op0;
9717 /* ??? Slightly redundant with the above mask, but not entirely.
9718 Moving this above means we'd have to sign-extend the mode mask
9719 for the final test. */
9720 if (op0 != UNKNOWN && op0 != NEG)
9721 *pconst0 = trunc_int_for_mode (const0, mode);
9723 return 1;
9726 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9727 the shift in. The original shift operation CODE is performed on OP in
9728 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9729 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9730 result of the shift is subject to operation OUTER_CODE with operand
9731 OUTER_CONST. */
9733 static enum machine_mode
9734 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9735 enum machine_mode orig_mode, enum machine_mode mode,
9736 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9738 if (orig_mode == mode)
9739 return mode;
9740 gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
9742 /* In general we can't perform in wider mode for right shift and rotate. */
9743 switch (code)
9745 case ASHIFTRT:
9746 /* We can still widen if the bits brought in from the left are identical
9747 to the sign bit of ORIG_MODE. */
9748 if (num_sign_bit_copies (op, mode)
9749 > (unsigned) (GET_MODE_PRECISION (mode)
9750 - GET_MODE_PRECISION (orig_mode)))
9751 return mode;
9752 return orig_mode;
9754 case LSHIFTRT:
9755 /* Similarly here but with zero bits. */
9756 if (HWI_COMPUTABLE_MODE_P (mode)
9757 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9758 return mode;
9760 /* We can also widen if the bits brought in will be masked off. This
9761 operation is performed in ORIG_MODE. */
9762 if (outer_code == AND)
9764 int care_bits = low_bitmask_len (orig_mode, outer_const);
9766 if (care_bits >= 0
9767 && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
9768 return mode;
9770 /* fall through */
9772 case ROTATE:
9773 return orig_mode;
9775 case ROTATERT:
9776 gcc_unreachable ();
9778 default:
9779 return mode;
9783 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9784 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9785 if we cannot simplify it. Otherwise, return a simplified value.
9787 The shift is normally computed in the widest mode we find in VAROP, as
9788 long as it isn't a different number of words than RESULT_MODE. Exceptions
9789 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9791 static rtx
9792 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9793 rtx varop, int orig_count)
9795 enum rtx_code orig_code = code;
9796 rtx orig_varop = varop;
9797 int count;
9798 enum machine_mode mode = result_mode;
9799 enum machine_mode shift_mode, tmode;
9800 unsigned int mode_words
9801 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9802 /* We form (outer_op (code varop count) (outer_const)). */
9803 enum rtx_code outer_op = UNKNOWN;
9804 HOST_WIDE_INT outer_const = 0;
9805 int complement_p = 0;
9806 rtx new_rtx, x;
9808 /* Make sure and truncate the "natural" shift on the way in. We don't
9809 want to do this inside the loop as it makes it more difficult to
9810 combine shifts. */
9811 if (SHIFT_COUNT_TRUNCATED)
9812 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9814 /* If we were given an invalid count, don't do anything except exactly
9815 what was requested. */
9817 if (orig_count < 0 || orig_count >= (int) GET_MODE_PRECISION (mode))
9818 return NULL_RTX;
9820 count = orig_count;
9822 /* Unless one of the branches of the `if' in this loop does a `continue',
9823 we will `break' the loop after the `if'. */
9825 while (count != 0)
9827 /* If we have an operand of (clobber (const_int 0)), fail. */
9828 if (GET_CODE (varop) == CLOBBER)
9829 return NULL_RTX;
9831 /* Convert ROTATERT to ROTATE. */
9832 if (code == ROTATERT)
9834 unsigned int bitsize = GET_MODE_PRECISION (result_mode);
9835 code = ROTATE;
9836 if (VECTOR_MODE_P (result_mode))
9837 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9838 else
9839 count = bitsize - count;
9842 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9843 mode, outer_op, outer_const);
9845 /* Handle cases where the count is greater than the size of the mode
9846 minus 1. For ASHIFT, use the size minus one as the count (this can
9847 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9848 take the count modulo the size. For other shifts, the result is
9849 zero.
9851 Since these shifts are being produced by the compiler by combining
9852 multiple operations, each of which are defined, we know what the
9853 result is supposed to be. */
9855 if (count > (GET_MODE_PRECISION (shift_mode) - 1))
9857 if (code == ASHIFTRT)
9858 count = GET_MODE_PRECISION (shift_mode) - 1;
9859 else if (code == ROTATE || code == ROTATERT)
9860 count %= GET_MODE_PRECISION (shift_mode);
9861 else
9863 /* We can't simply return zero because there may be an
9864 outer op. */
9865 varop = const0_rtx;
9866 count = 0;
9867 break;
9871 /* If we discovered we had to complement VAROP, leave. Making a NOT
9872 here would cause an infinite loop. */
9873 if (complement_p)
9874 break;
9876 /* An arithmetic right shift of a quantity known to be -1 or 0
9877 is a no-op. */
9878 if (code == ASHIFTRT
9879 && (num_sign_bit_copies (varop, shift_mode)
9880 == GET_MODE_PRECISION (shift_mode)))
9882 count = 0;
9883 break;
9886 /* If we are doing an arithmetic right shift and discarding all but
9887 the sign bit copies, this is equivalent to doing a shift by the
9888 bitsize minus one. Convert it into that shift because it will often
9889 allow other simplifications. */
9891 if (code == ASHIFTRT
9892 && (count + num_sign_bit_copies (varop, shift_mode)
9893 >= GET_MODE_PRECISION (shift_mode)))
9894 count = GET_MODE_PRECISION (shift_mode) - 1;
9896 /* We simplify the tests below and elsewhere by converting
9897 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9898 `make_compound_operation' will convert it to an ASHIFTRT for
9899 those machines (such as VAX) that don't have an LSHIFTRT. */
9900 if (code == ASHIFTRT
9901 && val_signbit_known_clear_p (shift_mode,
9902 nonzero_bits (varop, shift_mode)))
9903 code = LSHIFTRT;
9905 if (((code == LSHIFTRT
9906 && HWI_COMPUTABLE_MODE_P (shift_mode)
9907 && !(nonzero_bits (varop, shift_mode) >> count))
9908 || (code == ASHIFT
9909 && HWI_COMPUTABLE_MODE_P (shift_mode)
9910 && !((nonzero_bits (varop, shift_mode) << count)
9911 & GET_MODE_MASK (shift_mode))))
9912 && !side_effects_p (varop))
9913 varop = const0_rtx;
9915 switch (GET_CODE (varop))
9917 case SIGN_EXTEND:
9918 case ZERO_EXTEND:
9919 case SIGN_EXTRACT:
9920 case ZERO_EXTRACT:
9921 new_rtx = expand_compound_operation (varop);
9922 if (new_rtx != varop)
9924 varop = new_rtx;
9925 continue;
9927 break;
9929 case MEM:
9930 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9931 minus the width of a smaller mode, we can do this with a
9932 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9933 if ((code == ASHIFTRT || code == LSHIFTRT)
9934 && ! mode_dependent_address_p (XEXP (varop, 0),
9935 MEM_ADDR_SPACE (varop))
9936 && ! MEM_VOLATILE_P (varop)
9937 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9938 MODE_INT, 1)) != BLKmode)
9940 new_rtx = adjust_address_nv (varop, tmode,
9941 BYTES_BIG_ENDIAN ? 0
9942 : count / BITS_PER_UNIT);
9944 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9945 : ZERO_EXTEND, mode, new_rtx);
9946 count = 0;
9947 continue;
9949 break;
9951 case SUBREG:
9952 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9953 the same number of words as what we've seen so far. Then store
9954 the widest mode in MODE. */
9955 if (subreg_lowpart_p (varop)
9956 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9957 > GET_MODE_SIZE (GET_MODE (varop)))
9958 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9959 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9960 == mode_words
9961 && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
9962 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
9964 varop = SUBREG_REG (varop);
9965 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9966 mode = GET_MODE (varop);
9967 continue;
9969 break;
9971 case MULT:
9972 /* Some machines use MULT instead of ASHIFT because MULT
9973 is cheaper. But it is still better on those machines to
9974 merge two shifts into one. */
9975 if (CONST_INT_P (XEXP (varop, 1))
9976 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9978 varop
9979 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9980 XEXP (varop, 0),
9981 GEN_INT (exact_log2 (
9982 UINTVAL (XEXP (varop, 1)))));
9983 continue;
9985 break;
9987 case UDIV:
9988 /* Similar, for when divides are cheaper. */
9989 if (CONST_INT_P (XEXP (varop, 1))
9990 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9992 varop
9993 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9994 XEXP (varop, 0),
9995 GEN_INT (exact_log2 (
9996 UINTVAL (XEXP (varop, 1)))));
9997 continue;
9999 break;
10001 case ASHIFTRT:
10002 /* If we are extracting just the sign bit of an arithmetic
10003 right shift, that shift is not needed. However, the sign
10004 bit of a wider mode may be different from what would be
10005 interpreted as the sign bit in a narrower mode, so, if
10006 the result is narrower, don't discard the shift. */
10007 if (code == LSHIFTRT
10008 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10009 && (GET_MODE_BITSIZE (result_mode)
10010 >= GET_MODE_BITSIZE (GET_MODE (varop))))
10012 varop = XEXP (varop, 0);
10013 continue;
10016 /* ... fall through ... */
10018 case LSHIFTRT:
10019 case ASHIFT:
10020 case ROTATE:
10021 /* Here we have two nested shifts. The result is usually the
10022 AND of a new shift with a mask. We compute the result below. */
10023 if (CONST_INT_P (XEXP (varop, 1))
10024 && INTVAL (XEXP (varop, 1)) >= 0
10025 && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (GET_MODE (varop))
10026 && HWI_COMPUTABLE_MODE_P (result_mode)
10027 && HWI_COMPUTABLE_MODE_P (mode)
10028 && !VECTOR_MODE_P (result_mode))
10030 enum rtx_code first_code = GET_CODE (varop);
10031 unsigned int first_count = INTVAL (XEXP (varop, 1));
10032 unsigned HOST_WIDE_INT mask;
10033 rtx mask_rtx;
10035 /* We have one common special case. We can't do any merging if
10036 the inner code is an ASHIFTRT of a smaller mode. However, if
10037 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10038 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10039 we can convert it to
10040 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10041 This simplifies certain SIGN_EXTEND operations. */
10042 if (code == ASHIFT && first_code == ASHIFTRT
10043 && count == (GET_MODE_PRECISION (result_mode)
10044 - GET_MODE_PRECISION (GET_MODE (varop))))
10046 /* C3 has the low-order C1 bits zero. */
10048 mask = GET_MODE_MASK (mode)
10049 & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10051 varop = simplify_and_const_int (NULL_RTX, result_mode,
10052 XEXP (varop, 0), mask);
10053 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10054 varop, count);
10055 count = first_count;
10056 code = ASHIFTRT;
10057 continue;
10060 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10061 than C1 high-order bits equal to the sign bit, we can convert
10062 this to either an ASHIFT or an ASHIFTRT depending on the
10063 two counts.
10065 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10067 if (code == ASHIFTRT && first_code == ASHIFT
10068 && GET_MODE (varop) == shift_mode
10069 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10070 > first_count))
10072 varop = XEXP (varop, 0);
10073 count -= first_count;
10074 if (count < 0)
10076 count = -count;
10077 code = ASHIFT;
10080 continue;
10083 /* There are some cases we can't do. If CODE is ASHIFTRT,
10084 we can only do this if FIRST_CODE is also ASHIFTRT.
10086 We can't do the case when CODE is ROTATE and FIRST_CODE is
10087 ASHIFTRT.
10089 If the mode of this shift is not the mode of the outer shift,
10090 we can't do this if either shift is a right shift or ROTATE.
10092 Finally, we can't do any of these if the mode is too wide
10093 unless the codes are the same.
10095 Handle the case where the shift codes are the same
10096 first. */
10098 if (code == first_code)
10100 if (GET_MODE (varop) != result_mode
10101 && (code == ASHIFTRT || code == LSHIFTRT
10102 || code == ROTATE))
10103 break;
10105 count += first_count;
10106 varop = XEXP (varop, 0);
10107 continue;
10110 if (code == ASHIFTRT
10111 || (code == ROTATE && first_code == ASHIFTRT)
10112 || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
10113 || (GET_MODE (varop) != result_mode
10114 && (first_code == ASHIFTRT || first_code == LSHIFTRT
10115 || first_code == ROTATE
10116 || code == ROTATE)))
10117 break;
10119 /* To compute the mask to apply after the shift, shift the
10120 nonzero bits of the inner shift the same way the
10121 outer shift will. */
10123 mask_rtx = gen_int_mode (nonzero_bits (varop, GET_MODE (varop)),
10124 result_mode);
10126 mask_rtx
10127 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10128 GEN_INT (count));
10130 /* Give up if we can't compute an outer operation to use. */
10131 if (mask_rtx == 0
10132 || !CONST_INT_P (mask_rtx)
10133 || ! merge_outer_ops (&outer_op, &outer_const, AND,
10134 INTVAL (mask_rtx),
10135 result_mode, &complement_p))
10136 break;
10138 /* If the shifts are in the same direction, we add the
10139 counts. Otherwise, we subtract them. */
10140 if ((code == ASHIFTRT || code == LSHIFTRT)
10141 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10142 count += first_count;
10143 else
10144 count -= first_count;
10146 /* If COUNT is positive, the new shift is usually CODE,
10147 except for the two exceptions below, in which case it is
10148 FIRST_CODE. If the count is negative, FIRST_CODE should
10149 always be used */
10150 if (count > 0
10151 && ((first_code == ROTATE && code == ASHIFT)
10152 || (first_code == ASHIFTRT && code == LSHIFTRT)))
10153 code = first_code;
10154 else if (count < 0)
10155 code = first_code, count = -count;
10157 varop = XEXP (varop, 0);
10158 continue;
10161 /* If we have (A << B << C) for any shift, we can convert this to
10162 (A << C << B). This wins if A is a constant. Only try this if
10163 B is not a constant. */
10165 else if (GET_CODE (varop) == code
10166 && CONST_INT_P (XEXP (varop, 0))
10167 && !CONST_INT_P (XEXP (varop, 1)))
10169 rtx new_rtx = simplify_const_binary_operation (code, mode,
10170 XEXP (varop, 0),
10171 GEN_INT (count));
10172 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10173 count = 0;
10174 continue;
10176 break;
10178 case NOT:
10179 if (VECTOR_MODE_P (mode))
10180 break;
10182 /* Make this fit the case below. */
10183 varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
10184 continue;
10186 case IOR:
10187 case AND:
10188 case XOR:
10189 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10190 with C the size of VAROP - 1 and the shift is logical if
10191 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10192 we have an (le X 0) operation. If we have an arithmetic shift
10193 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10194 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10196 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10197 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10198 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10199 && (code == LSHIFTRT || code == ASHIFTRT)
10200 && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10201 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10203 count = 0;
10204 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10205 const0_rtx);
10207 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10208 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10210 continue;
10213 /* If we have (shift (logical)), move the logical to the outside
10214 to allow it to possibly combine with another logical and the
10215 shift to combine with another shift. This also canonicalizes to
10216 what a ZERO_EXTRACT looks like. Also, some machines have
10217 (and (shift)) insns. */
10219 if (CONST_INT_P (XEXP (varop, 1))
10220 /* We can't do this if we have (ashiftrt (xor)) and the
10221 constant has its sign bit set in shift_mode. */
10222 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10223 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10224 shift_mode))
10225 && (new_rtx = simplify_const_binary_operation
10226 (code, result_mode,
10227 gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode),
10228 GEN_INT (count))) != 0
10229 && CONST_INT_P (new_rtx)
10230 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10231 INTVAL (new_rtx), result_mode, &complement_p))
10233 varop = XEXP (varop, 0);
10234 continue;
10237 /* If we can't do that, try to simplify the shift in each arm of the
10238 logical expression, make a new logical expression, and apply
10239 the inverse distributive law. This also can't be done
10240 for some (ashiftrt (xor)). */
10241 if (CONST_INT_P (XEXP (varop, 1))
10242 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10243 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10244 shift_mode)))
10246 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10247 XEXP (varop, 0), count);
10248 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10249 XEXP (varop, 1), count);
10251 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10252 lhs, rhs);
10253 varop = apply_distributive_law (varop);
10255 count = 0;
10256 continue;
10258 break;
10260 case EQ:
10261 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10262 says that the sign bit can be tested, FOO has mode MODE, C is
10263 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10264 that may be nonzero. */
10265 if (code == LSHIFTRT
10266 && XEXP (varop, 1) == const0_rtx
10267 && GET_MODE (XEXP (varop, 0)) == result_mode
10268 && count == (GET_MODE_PRECISION (result_mode) - 1)
10269 && HWI_COMPUTABLE_MODE_P (result_mode)
10270 && STORE_FLAG_VALUE == -1
10271 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10272 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10273 &complement_p))
10275 varop = XEXP (varop, 0);
10276 count = 0;
10277 continue;
10279 break;
10281 case NEG:
10282 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10283 than the number of bits in the mode is equivalent to A. */
10284 if (code == LSHIFTRT
10285 && count == (GET_MODE_PRECISION (result_mode) - 1)
10286 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10288 varop = XEXP (varop, 0);
10289 count = 0;
10290 continue;
10293 /* NEG commutes with ASHIFT since it is multiplication. Move the
10294 NEG outside to allow shifts to combine. */
10295 if (code == ASHIFT
10296 && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10297 &complement_p))
10299 varop = XEXP (varop, 0);
10300 continue;
10302 break;
10304 case PLUS:
10305 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10306 is one less than the number of bits in the mode is
10307 equivalent to (xor A 1). */
10308 if (code == LSHIFTRT
10309 && count == (GET_MODE_PRECISION (result_mode) - 1)
10310 && XEXP (varop, 1) == constm1_rtx
10311 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10312 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10313 &complement_p))
10315 count = 0;
10316 varop = XEXP (varop, 0);
10317 continue;
10320 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10321 that might be nonzero in BAR are those being shifted out and those
10322 bits are known zero in FOO, we can replace the PLUS with FOO.
10323 Similarly in the other operand order. This code occurs when
10324 we are computing the size of a variable-size array. */
10326 if ((code == ASHIFTRT || code == LSHIFTRT)
10327 && count < HOST_BITS_PER_WIDE_INT
10328 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10329 && (nonzero_bits (XEXP (varop, 1), result_mode)
10330 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10332 varop = XEXP (varop, 0);
10333 continue;
10335 else if ((code == ASHIFTRT || code == LSHIFTRT)
10336 && count < HOST_BITS_PER_WIDE_INT
10337 && HWI_COMPUTABLE_MODE_P (result_mode)
10338 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10339 >> count)
10340 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10341 & nonzero_bits (XEXP (varop, 1),
10342 result_mode)))
10344 varop = XEXP (varop, 1);
10345 continue;
10348 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10349 if (code == ASHIFT
10350 && CONST_INT_P (XEXP (varop, 1))
10351 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10352 XEXP (varop, 1),
10353 GEN_INT (count))) != 0
10354 && CONST_INT_P (new_rtx)
10355 && merge_outer_ops (&outer_op, &outer_const, PLUS,
10356 INTVAL (new_rtx), result_mode, &complement_p))
10358 varop = XEXP (varop, 0);
10359 continue;
10362 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10363 signbit', and attempt to change the PLUS to an XOR and move it to
10364 the outer operation as is done above in the AND/IOR/XOR case
10365 leg for shift(logical). See details in logical handling above
10366 for reasoning in doing so. */
10367 if (code == LSHIFTRT
10368 && CONST_INT_P (XEXP (varop, 1))
10369 && mode_signbit_p (result_mode, XEXP (varop, 1))
10370 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10371 XEXP (varop, 1),
10372 GEN_INT (count))) != 0
10373 && CONST_INT_P (new_rtx)
10374 && merge_outer_ops (&outer_op, &outer_const, XOR,
10375 INTVAL (new_rtx), result_mode, &complement_p))
10377 varop = XEXP (varop, 0);
10378 continue;
10381 break;
10383 case MINUS:
10384 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10385 with C the size of VAROP - 1 and the shift is logical if
10386 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10387 we have a (gt X 0) operation. If the shift is arithmetic with
10388 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10389 we have a (neg (gt X 0)) operation. */
10391 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10392 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10393 && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10394 && (code == LSHIFTRT || code == ASHIFTRT)
10395 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10396 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10397 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10399 count = 0;
10400 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10401 const0_rtx);
10403 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10404 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10406 continue;
10408 break;
10410 case TRUNCATE:
10411 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10412 if the truncate does not affect the value. */
10413 if (code == LSHIFTRT
10414 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10415 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10416 && (INTVAL (XEXP (XEXP (varop, 0), 1))
10417 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop, 0)))
10418 - GET_MODE_PRECISION (GET_MODE (varop)))))
10420 rtx varop_inner = XEXP (varop, 0);
10422 varop_inner
10423 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10424 XEXP (varop_inner, 0),
10425 GEN_INT
10426 (count + INTVAL (XEXP (varop_inner, 1))));
10427 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10428 count = 0;
10429 continue;
10431 break;
10433 default:
10434 break;
10437 break;
10440 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10441 outer_op, outer_const);
10443 /* We have now finished analyzing the shift. The result should be
10444 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10445 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10446 to the result of the shift. OUTER_CONST is the relevant constant,
10447 but we must turn off all bits turned off in the shift. */
10449 if (outer_op == UNKNOWN
10450 && orig_code == code && orig_count == count
10451 && varop == orig_varop
10452 && shift_mode == GET_MODE (varop))
10453 return NULL_RTX;
10455 /* Make a SUBREG if necessary. If we can't make it, fail. */
10456 varop = gen_lowpart (shift_mode, varop);
10457 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10458 return NULL_RTX;
10460 /* If we have an outer operation and we just made a shift, it is
10461 possible that we could have simplified the shift were it not
10462 for the outer operation. So try to do the simplification
10463 recursively. */
10465 if (outer_op != UNKNOWN)
10466 x = simplify_shift_const_1 (code, shift_mode, varop, count);
10467 else
10468 x = NULL_RTX;
10470 if (x == NULL_RTX)
10471 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10473 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10474 turn off all the bits that the shift would have turned off. */
10475 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10476 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10477 GET_MODE_MASK (result_mode) >> orig_count);
10479 /* Do the remainder of the processing in RESULT_MODE. */
10480 x = gen_lowpart_or_truncate (result_mode, x);
10482 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10483 operation. */
10484 if (complement_p)
10485 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10487 if (outer_op != UNKNOWN)
10489 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10490 && GET_MODE_PRECISION (result_mode) < HOST_BITS_PER_WIDE_INT)
10491 outer_const = trunc_int_for_mode (outer_const, result_mode);
10493 if (outer_op == AND)
10494 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10495 else if (outer_op == SET)
10497 /* This means that we have determined that the result is
10498 equivalent to a constant. This should be rare. */
10499 if (!side_effects_p (x))
10500 x = GEN_INT (outer_const);
10502 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10503 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10504 else
10505 x = simplify_gen_binary (outer_op, result_mode, x,
10506 GEN_INT (outer_const));
10509 return x;
10512 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10513 The result of the shift is RESULT_MODE. If we cannot simplify it,
10514 return X or, if it is NULL, synthesize the expression with
10515 simplify_gen_binary. Otherwise, return a simplified value.
10517 The shift is normally computed in the widest mode we find in VAROP, as
10518 long as it isn't a different number of words than RESULT_MODE. Exceptions
10519 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10521 static rtx
10522 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10523 rtx varop, int count)
10525 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10526 if (tem)
10527 return tem;
10529 if (!x)
10530 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10531 if (GET_MODE (x) != result_mode)
10532 x = gen_lowpart (result_mode, x);
10533 return x;
10537 /* Like recog, but we receive the address of a pointer to a new pattern.
10538 We try to match the rtx that the pointer points to.
10539 If that fails, we may try to modify or replace the pattern,
10540 storing the replacement into the same pointer object.
10542 Modifications include deletion or addition of CLOBBERs.
10544 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10545 the CLOBBERs are placed.
10547 The value is the final insn code from the pattern ultimately matched,
10548 or -1. */
10550 static int
10551 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10553 rtx pat = *pnewpat;
10554 rtx pat_without_clobbers;
10555 int insn_code_number;
10556 int num_clobbers_to_add = 0;
10557 int i;
10558 rtx notes = NULL_RTX;
10559 rtx old_notes, old_pat;
10560 int old_icode;
10562 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10563 we use to indicate that something didn't match. If we find such a
10564 thing, force rejection. */
10565 if (GET_CODE (pat) == PARALLEL)
10566 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10567 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10568 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10569 return -1;
10571 old_pat = PATTERN (insn);
10572 old_notes = REG_NOTES (insn);
10573 PATTERN (insn) = pat;
10574 REG_NOTES (insn) = NULL_RTX;
10576 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10577 if (dump_file && (dump_flags & TDF_DETAILS))
10579 if (insn_code_number < 0)
10580 fputs ("Failed to match this instruction:\n", dump_file);
10581 else
10582 fputs ("Successfully matched this instruction:\n", dump_file);
10583 print_rtl_single (dump_file, pat);
10586 /* If it isn't, there is the possibility that we previously had an insn
10587 that clobbered some register as a side effect, but the combined
10588 insn doesn't need to do that. So try once more without the clobbers
10589 unless this represents an ASM insn. */
10591 if (insn_code_number < 0 && ! check_asm_operands (pat)
10592 && GET_CODE (pat) == PARALLEL)
10594 int pos;
10596 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10597 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10599 if (i != pos)
10600 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10601 pos++;
10604 SUBST_INT (XVECLEN (pat, 0), pos);
10606 if (pos == 1)
10607 pat = XVECEXP (pat, 0, 0);
10609 PATTERN (insn) = pat;
10610 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10611 if (dump_file && (dump_flags & TDF_DETAILS))
10613 if (insn_code_number < 0)
10614 fputs ("Failed to match this instruction:\n", dump_file);
10615 else
10616 fputs ("Successfully matched this instruction:\n", dump_file);
10617 print_rtl_single (dump_file, pat);
10621 pat_without_clobbers = pat;
10623 PATTERN (insn) = old_pat;
10624 REG_NOTES (insn) = old_notes;
10626 /* Recognize all noop sets, these will be killed by followup pass. */
10627 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10628 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10630 /* If we had any clobbers to add, make a new pattern than contains
10631 them. Then check to make sure that all of them are dead. */
10632 if (num_clobbers_to_add)
10634 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10635 rtvec_alloc (GET_CODE (pat) == PARALLEL
10636 ? (XVECLEN (pat, 0)
10637 + num_clobbers_to_add)
10638 : num_clobbers_to_add + 1));
10640 if (GET_CODE (pat) == PARALLEL)
10641 for (i = 0; i < XVECLEN (pat, 0); i++)
10642 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10643 else
10644 XVECEXP (newpat, 0, 0) = pat;
10646 add_clobbers (newpat, insn_code_number);
10648 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10649 i < XVECLEN (newpat, 0); i++)
10651 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10652 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10653 return -1;
10654 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10656 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10657 notes = alloc_reg_note (REG_UNUSED,
10658 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10661 pat = newpat;
10664 if (insn_code_number >= 0
10665 && insn_code_number != NOOP_MOVE_INSN_CODE)
10667 old_pat = PATTERN (insn);
10668 old_notes = REG_NOTES (insn);
10669 old_icode = INSN_CODE (insn);
10670 PATTERN (insn) = pat;
10671 REG_NOTES (insn) = notes;
10673 /* Allow targets to reject combined insn. */
10674 if (!targetm.legitimate_combined_insn (insn))
10676 if (dump_file && (dump_flags & TDF_DETAILS))
10677 fputs ("Instruction not appropriate for target.",
10678 dump_file);
10680 /* Callers expect recog_for_combine to strip
10681 clobbers from the pattern on failure. */
10682 pat = pat_without_clobbers;
10683 notes = NULL_RTX;
10685 insn_code_number = -1;
10688 PATTERN (insn) = old_pat;
10689 REG_NOTES (insn) = old_notes;
10690 INSN_CODE (insn) = old_icode;
10693 *pnewpat = pat;
10694 *pnotes = notes;
10696 return insn_code_number;
10699 /* Like gen_lowpart_general but for use by combine. In combine it
10700 is not possible to create any new pseudoregs. However, it is
10701 safe to create invalid memory addresses, because combine will
10702 try to recognize them and all they will do is make the combine
10703 attempt fail.
10705 If for some reason this cannot do its job, an rtx
10706 (clobber (const_int 0)) is returned.
10707 An insn containing that will not be recognized. */
10709 static rtx
10710 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10712 enum machine_mode imode = GET_MODE (x);
10713 unsigned int osize = GET_MODE_SIZE (omode);
10714 unsigned int isize = GET_MODE_SIZE (imode);
10715 rtx result;
10717 if (omode == imode)
10718 return x;
10720 /* We can only support MODE being wider than a word if X is a
10721 constant integer or has a mode the same size. */
10722 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10723 && ! (CONST_SCALAR_INT_P (x) || isize == osize))
10724 goto fail;
10726 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10727 won't know what to do. So we will strip off the SUBREG here and
10728 process normally. */
10729 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10731 x = SUBREG_REG (x);
10733 /* For use in case we fall down into the address adjustments
10734 further below, we need to adjust the known mode and size of
10735 x; imode and isize, since we just adjusted x. */
10736 imode = GET_MODE (x);
10738 if (imode == omode)
10739 return x;
10741 isize = GET_MODE_SIZE (imode);
10744 result = gen_lowpart_common (omode, x);
10746 if (result)
10747 return result;
10749 if (MEM_P (x))
10751 int offset = 0;
10753 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10754 address. */
10755 if (MEM_VOLATILE_P (x)
10756 || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x)))
10757 goto fail;
10759 /* If we want to refer to something bigger than the original memref,
10760 generate a paradoxical subreg instead. That will force a reload
10761 of the original memref X. */
10762 if (isize < osize)
10763 return gen_rtx_SUBREG (omode, x, 0);
10765 if (WORDS_BIG_ENDIAN)
10766 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10768 /* Adjust the address so that the address-after-the-data is
10769 unchanged. */
10770 if (BYTES_BIG_ENDIAN)
10771 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10773 return adjust_address_nv (x, omode, offset);
10776 /* If X is a comparison operator, rewrite it in a new mode. This
10777 probably won't match, but may allow further simplifications. */
10778 else if (COMPARISON_P (x))
10779 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10781 /* If we couldn't simplify X any other way, just enclose it in a
10782 SUBREG. Normally, this SUBREG won't match, but some patterns may
10783 include an explicit SUBREG or we may simplify it further in combine. */
10784 else
10786 int offset = 0;
10787 rtx res;
10789 offset = subreg_lowpart_offset (omode, imode);
10790 if (imode == VOIDmode)
10792 imode = int_mode_for_mode (omode);
10793 x = gen_lowpart_common (imode, x);
10794 if (x == NULL)
10795 goto fail;
10797 res = simplify_gen_subreg (omode, x, imode, offset);
10798 if (res)
10799 return res;
10802 fail:
10803 return gen_rtx_CLOBBER (omode, const0_rtx);
10806 /* Try to simplify a comparison between OP0 and a constant OP1,
10807 where CODE is the comparison code that will be tested, into a
10808 (CODE OP0 const0_rtx) form.
10810 The result is a possibly different comparison code to use.
10811 *POP1 may be updated. */
10813 static enum rtx_code
10814 simplify_compare_const (enum rtx_code code, rtx op0, rtx *pop1)
10816 enum machine_mode mode = GET_MODE (op0);
10817 unsigned int mode_width = GET_MODE_PRECISION (mode);
10818 HOST_WIDE_INT const_op = INTVAL (*pop1);
10820 /* Get the constant we are comparing against and turn off all bits
10821 not on in our mode. */
10822 if (mode != VOIDmode)
10823 const_op = trunc_int_for_mode (const_op, mode);
10825 /* If we are comparing against a constant power of two and the value
10826 being compared can only have that single bit nonzero (e.g., it was
10827 `and'ed with that bit), we can replace this with a comparison
10828 with zero. */
10829 if (const_op
10830 && (code == EQ || code == NE || code == GE || code == GEU
10831 || code == LT || code == LTU)
10832 && mode_width <= HOST_BITS_PER_WIDE_INT
10833 && exact_log2 (const_op & GET_MODE_MASK (mode)) >= 0
10834 && (nonzero_bits (op0, mode)
10835 == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (mode))))
10837 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10838 const_op = 0;
10841 /* Similarly, if we are comparing a value known to be either -1 or
10842 0 with -1, change it to the opposite comparison against zero. */
10843 if (const_op == -1
10844 && (code == EQ || code == NE || code == GT || code == LE
10845 || code == GEU || code == LTU)
10846 && num_sign_bit_copies (op0, mode) == mode_width)
10848 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10849 const_op = 0;
10852 /* Do some canonicalizations based on the comparison code. We prefer
10853 comparisons against zero and then prefer equality comparisons.
10854 If we can reduce the size of a constant, we will do that too. */
10855 switch (code)
10857 case LT:
10858 /* < C is equivalent to <= (C - 1) */
10859 if (const_op > 0)
10861 const_op -= 1;
10862 code = LE;
10863 /* ... fall through to LE case below. */
10865 else
10866 break;
10868 case LE:
10869 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10870 if (const_op < 0)
10872 const_op += 1;
10873 code = LT;
10876 /* If we are doing a <= 0 comparison on a value known to have
10877 a zero sign bit, we can replace this with == 0. */
10878 else if (const_op == 0
10879 && mode_width <= HOST_BITS_PER_WIDE_INT
10880 && (nonzero_bits (op0, mode)
10881 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10882 == 0)
10883 code = EQ;
10884 break;
10886 case GE:
10887 /* >= C is equivalent to > (C - 1). */
10888 if (const_op > 0)
10890 const_op -= 1;
10891 code = GT;
10892 /* ... fall through to GT below. */
10894 else
10895 break;
10897 case GT:
10898 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10899 if (const_op < 0)
10901 const_op += 1;
10902 code = GE;
10905 /* If we are doing a > 0 comparison on a value known to have
10906 a zero sign bit, we can replace this with != 0. */
10907 else if (const_op == 0
10908 && mode_width <= HOST_BITS_PER_WIDE_INT
10909 && (nonzero_bits (op0, mode)
10910 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10911 == 0)
10912 code = NE;
10913 break;
10915 case LTU:
10916 /* < C is equivalent to <= (C - 1). */
10917 if (const_op > 0)
10919 const_op -= 1;
10920 code = LEU;
10921 /* ... fall through ... */
10923 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10924 else if (mode_width <= HOST_BITS_PER_WIDE_INT
10925 && (unsigned HOST_WIDE_INT) const_op
10926 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10928 const_op = 0;
10929 code = GE;
10930 break;
10932 else
10933 break;
10935 case LEU:
10936 /* unsigned <= 0 is equivalent to == 0 */
10937 if (const_op == 0)
10938 code = EQ;
10939 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10940 else if (mode_width <= HOST_BITS_PER_WIDE_INT
10941 && (unsigned HOST_WIDE_INT) const_op
10942 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
10944 const_op = 0;
10945 code = GE;
10947 break;
10949 case GEU:
10950 /* >= C is equivalent to > (C - 1). */
10951 if (const_op > 1)
10953 const_op -= 1;
10954 code = GTU;
10955 /* ... fall through ... */
10958 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10959 else if (mode_width <= HOST_BITS_PER_WIDE_INT
10960 && (unsigned HOST_WIDE_INT) const_op
10961 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10963 const_op = 0;
10964 code = LT;
10965 break;
10967 else
10968 break;
10970 case GTU:
10971 /* unsigned > 0 is equivalent to != 0 */
10972 if (const_op == 0)
10973 code = NE;
10974 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10975 else if (mode_width <= HOST_BITS_PER_WIDE_INT
10976 && (unsigned HOST_WIDE_INT) const_op
10977 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
10979 const_op = 0;
10980 code = LT;
10982 break;
10984 default:
10985 break;
10988 *pop1 = GEN_INT (const_op);
10989 return code;
10992 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10993 comparison code that will be tested.
10995 The result is a possibly different comparison code to use. *POP0 and
10996 *POP1 may be updated.
10998 It is possible that we might detect that a comparison is either always
10999 true or always false. However, we do not perform general constant
11000 folding in combine, so this knowledge isn't useful. Such tautologies
11001 should have been detected earlier. Hence we ignore all such cases. */
11003 static enum rtx_code
11004 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
11006 rtx op0 = *pop0;
11007 rtx op1 = *pop1;
11008 rtx tem, tem1;
11009 int i;
11010 enum machine_mode mode, tmode;
11012 /* Try a few ways of applying the same transformation to both operands. */
11013 while (1)
11015 #ifndef WORD_REGISTER_OPERATIONS
11016 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11017 so check specially. */
11018 if (code != GTU && code != GEU && code != LTU && code != LEU
11019 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
11020 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11021 && GET_CODE (XEXP (op1, 0)) == ASHIFT
11022 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
11023 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
11024 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
11025 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
11026 && CONST_INT_P (XEXP (op0, 1))
11027 && XEXP (op0, 1) == XEXP (op1, 1)
11028 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11029 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
11030 && (INTVAL (XEXP (op0, 1))
11031 == (GET_MODE_PRECISION (GET_MODE (op0))
11032 - (GET_MODE_PRECISION
11033 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
11035 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
11036 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
11038 #endif
11040 /* If both operands are the same constant shift, see if we can ignore the
11041 shift. We can if the shift is a rotate or if the bits shifted out of
11042 this shift are known to be zero for both inputs and if the type of
11043 comparison is compatible with the shift. */
11044 if (GET_CODE (op0) == GET_CODE (op1)
11045 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
11046 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
11047 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
11048 && (code != GT && code != LT && code != GE && code != LE))
11049 || (GET_CODE (op0) == ASHIFTRT
11050 && (code != GTU && code != LTU
11051 && code != GEU && code != LEU)))
11052 && CONST_INT_P (XEXP (op0, 1))
11053 && INTVAL (XEXP (op0, 1)) >= 0
11054 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11055 && XEXP (op0, 1) == XEXP (op1, 1))
11057 enum machine_mode mode = GET_MODE (op0);
11058 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11059 int shift_count = INTVAL (XEXP (op0, 1));
11061 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
11062 mask &= (mask >> shift_count) << shift_count;
11063 else if (GET_CODE (op0) == ASHIFT)
11064 mask = (mask & (mask << shift_count)) >> shift_count;
11066 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
11067 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
11068 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
11069 else
11070 break;
11073 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11074 SUBREGs are of the same mode, and, in both cases, the AND would
11075 be redundant if the comparison was done in the narrower mode,
11076 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11077 and the operand's possibly nonzero bits are 0xffffff01; in that case
11078 if we only care about QImode, we don't need the AND). This case
11079 occurs if the output mode of an scc insn is not SImode and
11080 STORE_FLAG_VALUE == 1 (e.g., the 386).
11082 Similarly, check for a case where the AND's are ZERO_EXTEND
11083 operations from some narrower mode even though a SUBREG is not
11084 present. */
11086 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
11087 && CONST_INT_P (XEXP (op0, 1))
11088 && CONST_INT_P (XEXP (op1, 1)))
11090 rtx inner_op0 = XEXP (op0, 0);
11091 rtx inner_op1 = XEXP (op1, 0);
11092 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
11093 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
11094 int changed = 0;
11096 if (paradoxical_subreg_p (inner_op0)
11097 && GET_CODE (inner_op1) == SUBREG
11098 && (GET_MODE (SUBREG_REG (inner_op0))
11099 == GET_MODE (SUBREG_REG (inner_op1)))
11100 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0)))
11101 <= HOST_BITS_PER_WIDE_INT)
11102 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
11103 GET_MODE (SUBREG_REG (inner_op0)))))
11104 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
11105 GET_MODE (SUBREG_REG (inner_op1))))))
11107 op0 = SUBREG_REG (inner_op0);
11108 op1 = SUBREG_REG (inner_op1);
11110 /* The resulting comparison is always unsigned since we masked
11111 off the original sign bit. */
11112 code = unsigned_condition (code);
11114 changed = 1;
11117 else if (c0 == c1)
11118 for (tmode = GET_CLASS_NARROWEST_MODE
11119 (GET_MODE_CLASS (GET_MODE (op0)));
11120 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
11121 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
11123 op0 = gen_lowpart (tmode, inner_op0);
11124 op1 = gen_lowpart (tmode, inner_op1);
11125 code = unsigned_condition (code);
11126 changed = 1;
11127 break;
11130 if (! changed)
11131 break;
11134 /* If both operands are NOT, we can strip off the outer operation
11135 and adjust the comparison code for swapped operands; similarly for
11136 NEG, except that this must be an equality comparison. */
11137 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
11138 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
11139 && (code == EQ || code == NE)))
11140 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
11142 else
11143 break;
11146 /* If the first operand is a constant, swap the operands and adjust the
11147 comparison code appropriately, but don't do this if the second operand
11148 is already a constant integer. */
11149 if (swap_commutative_operands_p (op0, op1))
11151 tem = op0, op0 = op1, op1 = tem;
11152 code = swap_condition (code);
11155 /* We now enter a loop during which we will try to simplify the comparison.
11156 For the most part, we only are concerned with comparisons with zero,
11157 but some things may really be comparisons with zero but not start
11158 out looking that way. */
11160 while (CONST_INT_P (op1))
11162 enum machine_mode mode = GET_MODE (op0);
11163 unsigned int mode_width = GET_MODE_PRECISION (mode);
11164 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11165 int equality_comparison_p;
11166 int sign_bit_comparison_p;
11167 int unsigned_comparison_p;
11168 HOST_WIDE_INT const_op;
11170 /* We only want to handle integral modes. This catches VOIDmode,
11171 CCmode, and the floating-point modes. An exception is that we
11172 can handle VOIDmode if OP0 is a COMPARE or a comparison
11173 operation. */
11175 if (GET_MODE_CLASS (mode) != MODE_INT
11176 && ! (mode == VOIDmode
11177 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
11178 break;
11180 /* Try to simplify the compare to constant, possibly changing the
11181 comparison op, and/or changing op1 to zero. */
11182 code = simplify_compare_const (code, op0, &op1);
11183 const_op = INTVAL (op1);
11185 /* Compute some predicates to simplify code below. */
11187 equality_comparison_p = (code == EQ || code == NE);
11188 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11189 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11190 || code == GEU);
11192 /* If this is a sign bit comparison and we can do arithmetic in
11193 MODE, say that we will only be needing the sign bit of OP0. */
11194 if (sign_bit_comparison_p && HWI_COMPUTABLE_MODE_P (mode))
11195 op0 = force_to_mode (op0, mode,
11196 (unsigned HOST_WIDE_INT) 1
11197 << (GET_MODE_PRECISION (mode) - 1),
11200 /* Now try cases based on the opcode of OP0. If none of the cases
11201 does a "continue", we exit this loop immediately after the
11202 switch. */
11204 switch (GET_CODE (op0))
11206 case ZERO_EXTRACT:
11207 /* If we are extracting a single bit from a variable position in
11208 a constant that has only a single bit set and are comparing it
11209 with zero, we can convert this into an equality comparison
11210 between the position and the location of the single bit. */
11211 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11212 have already reduced the shift count modulo the word size. */
11213 if (!SHIFT_COUNT_TRUNCATED
11214 && CONST_INT_P (XEXP (op0, 0))
11215 && XEXP (op0, 1) == const1_rtx
11216 && equality_comparison_p && const_op == 0
11217 && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11219 if (BITS_BIG_ENDIAN)
11220 i = BITS_PER_WORD - 1 - i;
11222 op0 = XEXP (op0, 2);
11223 op1 = GEN_INT (i);
11224 const_op = i;
11226 /* Result is nonzero iff shift count is equal to I. */
11227 code = reverse_condition (code);
11228 continue;
11231 /* ... fall through ... */
11233 case SIGN_EXTRACT:
11234 tem = expand_compound_operation (op0);
11235 if (tem != op0)
11237 op0 = tem;
11238 continue;
11240 break;
11242 case NOT:
11243 /* If testing for equality, we can take the NOT of the constant. */
11244 if (equality_comparison_p
11245 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11247 op0 = XEXP (op0, 0);
11248 op1 = tem;
11249 continue;
11252 /* If just looking at the sign bit, reverse the sense of the
11253 comparison. */
11254 if (sign_bit_comparison_p)
11256 op0 = XEXP (op0, 0);
11257 code = (code == GE ? LT : GE);
11258 continue;
11260 break;
11262 case NEG:
11263 /* If testing for equality, we can take the NEG of the constant. */
11264 if (equality_comparison_p
11265 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11267 op0 = XEXP (op0, 0);
11268 op1 = tem;
11269 continue;
11272 /* The remaining cases only apply to comparisons with zero. */
11273 if (const_op != 0)
11274 break;
11276 /* When X is ABS or is known positive,
11277 (neg X) is < 0 if and only if X != 0. */
11279 if (sign_bit_comparison_p
11280 && (GET_CODE (XEXP (op0, 0)) == ABS
11281 || (mode_width <= HOST_BITS_PER_WIDE_INT
11282 && (nonzero_bits (XEXP (op0, 0), mode)
11283 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11284 == 0)))
11286 op0 = XEXP (op0, 0);
11287 code = (code == LT ? NE : EQ);
11288 continue;
11291 /* If we have NEG of something whose two high-order bits are the
11292 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11293 if (num_sign_bit_copies (op0, mode) >= 2)
11295 op0 = XEXP (op0, 0);
11296 code = swap_condition (code);
11297 continue;
11299 break;
11301 case ROTATE:
11302 /* If we are testing equality and our count is a constant, we
11303 can perform the inverse operation on our RHS. */
11304 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11305 && (tem = simplify_binary_operation (ROTATERT, mode,
11306 op1, XEXP (op0, 1))) != 0)
11308 op0 = XEXP (op0, 0);
11309 op1 = tem;
11310 continue;
11313 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11314 a particular bit. Convert it to an AND of a constant of that
11315 bit. This will be converted into a ZERO_EXTRACT. */
11316 if (const_op == 0 && sign_bit_comparison_p
11317 && CONST_INT_P (XEXP (op0, 1))
11318 && mode_width <= HOST_BITS_PER_WIDE_INT)
11320 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11321 ((unsigned HOST_WIDE_INT) 1
11322 << (mode_width - 1
11323 - INTVAL (XEXP (op0, 1)))));
11324 code = (code == LT ? NE : EQ);
11325 continue;
11328 /* Fall through. */
11330 case ABS:
11331 /* ABS is ignorable inside an equality comparison with zero. */
11332 if (const_op == 0 && equality_comparison_p)
11334 op0 = XEXP (op0, 0);
11335 continue;
11337 break;
11339 case SIGN_EXTEND:
11340 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11341 (compare FOO CONST) if CONST fits in FOO's mode and we
11342 are either testing inequality or have an unsigned
11343 comparison with ZERO_EXTEND or a signed comparison with
11344 SIGN_EXTEND. But don't do it if we don't have a compare
11345 insn of the given mode, since we'd have to revert it
11346 later on, and then we wouldn't know whether to sign- or
11347 zero-extend. */
11348 mode = GET_MODE (XEXP (op0, 0));
11349 if (GET_MODE_CLASS (mode) == MODE_INT
11350 && ! unsigned_comparison_p
11351 && HWI_COMPUTABLE_MODE_P (mode)
11352 && trunc_int_for_mode (const_op, mode) == const_op
11353 && have_insn_for (COMPARE, mode))
11355 op0 = XEXP (op0, 0);
11356 continue;
11358 break;
11360 case SUBREG:
11361 /* Check for the case where we are comparing A - C1 with C2, that is
11363 (subreg:MODE (plus (A) (-C1))) op (C2)
11365 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11366 comparison in the wider mode. One of the following two conditions
11367 must be true in order for this to be valid:
11369 1. The mode extension results in the same bit pattern being added
11370 on both sides and the comparison is equality or unsigned. As
11371 C2 has been truncated to fit in MODE, the pattern can only be
11372 all 0s or all 1s.
11374 2. The mode extension results in the sign bit being copied on
11375 each side.
11377 The difficulty here is that we have predicates for A but not for
11378 (A - C1) so we need to check that C1 is within proper bounds so
11379 as to perturbate A as little as possible. */
11381 if (mode_width <= HOST_BITS_PER_WIDE_INT
11382 && subreg_lowpart_p (op0)
11383 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) > mode_width
11384 && GET_CODE (SUBREG_REG (op0)) == PLUS
11385 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11387 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11388 rtx a = XEXP (SUBREG_REG (op0), 0);
11389 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11391 if ((c1 > 0
11392 && (unsigned HOST_WIDE_INT) c1
11393 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11394 && (equality_comparison_p || unsigned_comparison_p)
11395 /* (A - C1) zero-extends if it is positive and sign-extends
11396 if it is negative, C2 both zero- and sign-extends. */
11397 && ((0 == (nonzero_bits (a, inner_mode)
11398 & ~GET_MODE_MASK (mode))
11399 && const_op >= 0)
11400 /* (A - C1) sign-extends if it is positive and 1-extends
11401 if it is negative, C2 both sign- and 1-extends. */
11402 || (num_sign_bit_copies (a, inner_mode)
11403 > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11404 - mode_width)
11405 && const_op < 0)))
11406 || ((unsigned HOST_WIDE_INT) c1
11407 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11408 /* (A - C1) always sign-extends, like C2. */
11409 && num_sign_bit_copies (a, inner_mode)
11410 > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11411 - (mode_width - 1))))
11413 op0 = SUBREG_REG (op0);
11414 continue;
11418 /* If the inner mode is narrower and we are extracting the low part,
11419 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11420 if (subreg_lowpart_p (op0)
11421 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) < mode_width)
11422 /* Fall through */ ;
11423 else
11424 break;
11426 /* ... fall through ... */
11428 case ZERO_EXTEND:
11429 mode = GET_MODE (XEXP (op0, 0));
11430 if (GET_MODE_CLASS (mode) == MODE_INT
11431 && (unsigned_comparison_p || equality_comparison_p)
11432 && HWI_COMPUTABLE_MODE_P (mode)
11433 && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
11434 && const_op >= 0
11435 && have_insn_for (COMPARE, mode))
11437 op0 = XEXP (op0, 0);
11438 continue;
11440 break;
11442 case PLUS:
11443 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11444 this for equality comparisons due to pathological cases involving
11445 overflows. */
11446 if (equality_comparison_p
11447 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11448 op1, XEXP (op0, 1))))
11450 op0 = XEXP (op0, 0);
11451 op1 = tem;
11452 continue;
11455 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11456 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11457 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11459 op0 = XEXP (XEXP (op0, 0), 0);
11460 code = (code == LT ? EQ : NE);
11461 continue;
11463 break;
11465 case MINUS:
11466 /* We used to optimize signed comparisons against zero, but that
11467 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11468 arrive here as equality comparisons, or (GEU, LTU) are
11469 optimized away. No need to special-case them. */
11471 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11472 (eq B (minus A C)), whichever simplifies. We can only do
11473 this for equality comparisons due to pathological cases involving
11474 overflows. */
11475 if (equality_comparison_p
11476 && 0 != (tem = simplify_binary_operation (PLUS, mode,
11477 XEXP (op0, 1), op1)))
11479 op0 = XEXP (op0, 0);
11480 op1 = tem;
11481 continue;
11484 if (equality_comparison_p
11485 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11486 XEXP (op0, 0), op1)))
11488 op0 = XEXP (op0, 1);
11489 op1 = tem;
11490 continue;
11493 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11494 of bits in X minus 1, is one iff X > 0. */
11495 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11496 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11497 && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11498 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11500 op0 = XEXP (op0, 1);
11501 code = (code == GE ? LE : GT);
11502 continue;
11504 break;
11506 case XOR:
11507 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11508 if C is zero or B is a constant. */
11509 if (equality_comparison_p
11510 && 0 != (tem = simplify_binary_operation (XOR, mode,
11511 XEXP (op0, 1), op1)))
11513 op0 = XEXP (op0, 0);
11514 op1 = tem;
11515 continue;
11517 break;
11519 case EQ: case NE:
11520 case UNEQ: case LTGT:
11521 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11522 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11523 case UNORDERED: case ORDERED:
11524 /* We can't do anything if OP0 is a condition code value, rather
11525 than an actual data value. */
11526 if (const_op != 0
11527 || CC0_P (XEXP (op0, 0))
11528 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11529 break;
11531 /* Get the two operands being compared. */
11532 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11533 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11534 else
11535 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11537 /* Check for the cases where we simply want the result of the
11538 earlier test or the opposite of that result. */
11539 if (code == NE || code == EQ
11540 || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE)
11541 && (code == LT || code == GE)))
11543 enum rtx_code new_code;
11544 if (code == LT || code == NE)
11545 new_code = GET_CODE (op0);
11546 else
11547 new_code = reversed_comparison_code (op0, NULL);
11549 if (new_code != UNKNOWN)
11551 code = new_code;
11552 op0 = tem;
11553 op1 = tem1;
11554 continue;
11557 break;
11559 case IOR:
11560 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11561 iff X <= 0. */
11562 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11563 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11564 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11566 op0 = XEXP (op0, 1);
11567 code = (code == GE ? GT : LE);
11568 continue;
11570 break;
11572 case AND:
11573 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11574 will be converted to a ZERO_EXTRACT later. */
11575 if (const_op == 0 && equality_comparison_p
11576 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11577 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11579 op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11580 XEXP (XEXP (op0, 0), 1));
11581 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11582 continue;
11585 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11586 zero and X is a comparison and C1 and C2 describe only bits set
11587 in STORE_FLAG_VALUE, we can compare with X. */
11588 if (const_op == 0 && equality_comparison_p
11589 && mode_width <= HOST_BITS_PER_WIDE_INT
11590 && CONST_INT_P (XEXP (op0, 1))
11591 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11592 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11593 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11594 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11596 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11597 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11598 if ((~STORE_FLAG_VALUE & mask) == 0
11599 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11600 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11601 && COMPARISON_P (tem))))
11603 op0 = XEXP (XEXP (op0, 0), 0);
11604 continue;
11608 /* If we are doing an equality comparison of an AND of a bit equal
11609 to the sign bit, replace this with a LT or GE comparison of
11610 the underlying value. */
11611 if (equality_comparison_p
11612 && const_op == 0
11613 && CONST_INT_P (XEXP (op0, 1))
11614 && mode_width <= HOST_BITS_PER_WIDE_INT
11615 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11616 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11618 op0 = XEXP (op0, 0);
11619 code = (code == EQ ? GE : LT);
11620 continue;
11623 /* If this AND operation is really a ZERO_EXTEND from a narrower
11624 mode, the constant fits within that mode, and this is either an
11625 equality or unsigned comparison, try to do this comparison in
11626 the narrower mode.
11628 Note that in:
11630 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11631 -> (ne:DI (reg:SI 4) (const_int 0))
11633 unless TRULY_NOOP_TRUNCATION allows it or the register is
11634 known to hold a value of the required mode the
11635 transformation is invalid. */
11636 if ((equality_comparison_p || unsigned_comparison_p)
11637 && CONST_INT_P (XEXP (op0, 1))
11638 && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11639 & GET_MODE_MASK (mode))
11640 + 1)) >= 0
11641 && const_op >> i == 0
11642 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11643 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode, GET_MODE (op0))
11644 || (REG_P (XEXP (op0, 0))
11645 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11647 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11648 continue;
11651 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11652 fits in both M1 and M2 and the SUBREG is either paradoxical
11653 or represents the low part, permute the SUBREG and the AND
11654 and try again. */
11655 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11657 unsigned HOST_WIDE_INT c1;
11658 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11659 /* Require an integral mode, to avoid creating something like
11660 (AND:SF ...). */
11661 if (SCALAR_INT_MODE_P (tmode)
11662 /* It is unsafe to commute the AND into the SUBREG if the
11663 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11664 not defined. As originally written the upper bits
11665 have a defined value due to the AND operation.
11666 However, if we commute the AND inside the SUBREG then
11667 they no longer have defined values and the meaning of
11668 the code has been changed. */
11669 && (0
11670 #ifdef WORD_REGISTER_OPERATIONS
11671 || (mode_width > GET_MODE_PRECISION (tmode)
11672 && mode_width <= BITS_PER_WORD)
11673 #endif
11674 || (mode_width <= GET_MODE_PRECISION (tmode)
11675 && subreg_lowpart_p (XEXP (op0, 0))))
11676 && CONST_INT_P (XEXP (op0, 1))
11677 && mode_width <= HOST_BITS_PER_WIDE_INT
11678 && HWI_COMPUTABLE_MODE_P (tmode)
11679 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11680 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11681 && c1 != mask
11682 && c1 != GET_MODE_MASK (tmode))
11684 op0 = simplify_gen_binary (AND, tmode,
11685 SUBREG_REG (XEXP (op0, 0)),
11686 gen_int_mode (c1, tmode));
11687 op0 = gen_lowpart (mode, op0);
11688 continue;
11692 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11693 if (const_op == 0 && equality_comparison_p
11694 && XEXP (op0, 1) == const1_rtx
11695 && GET_CODE (XEXP (op0, 0)) == NOT)
11697 op0 = simplify_and_const_int (NULL_RTX, mode,
11698 XEXP (XEXP (op0, 0), 0), 1);
11699 code = (code == NE ? EQ : NE);
11700 continue;
11703 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11704 (eq (and (lshiftrt X) 1) 0).
11705 Also handle the case where (not X) is expressed using xor. */
11706 if (const_op == 0 && equality_comparison_p
11707 && XEXP (op0, 1) == const1_rtx
11708 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11710 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11711 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11713 if (GET_CODE (shift_op) == NOT
11714 || (GET_CODE (shift_op) == XOR
11715 && CONST_INT_P (XEXP (shift_op, 1))
11716 && CONST_INT_P (shift_count)
11717 && HWI_COMPUTABLE_MODE_P (mode)
11718 && (UINTVAL (XEXP (shift_op, 1))
11719 == (unsigned HOST_WIDE_INT) 1
11720 << INTVAL (shift_count))))
11723 = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11724 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11725 code = (code == NE ? EQ : NE);
11726 continue;
11729 break;
11731 case ASHIFT:
11732 /* If we have (compare (ashift FOO N) (const_int C)) and
11733 the high order N bits of FOO (N+1 if an inequality comparison)
11734 are known to be zero, we can do this by comparing FOO with C
11735 shifted right N bits so long as the low-order N bits of C are
11736 zero. */
11737 if (CONST_INT_P (XEXP (op0, 1))
11738 && INTVAL (XEXP (op0, 1)) >= 0
11739 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11740 < HOST_BITS_PER_WIDE_INT)
11741 && (((unsigned HOST_WIDE_INT) const_op
11742 & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11743 - 1)) == 0)
11744 && mode_width <= HOST_BITS_PER_WIDE_INT
11745 && (nonzero_bits (XEXP (op0, 0), mode)
11746 & ~(mask >> (INTVAL (XEXP (op0, 1))
11747 + ! equality_comparison_p))) == 0)
11749 /* We must perform a logical shift, not an arithmetic one,
11750 as we want the top N bits of C to be zero. */
11751 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11753 temp >>= INTVAL (XEXP (op0, 1));
11754 op1 = gen_int_mode (temp, mode);
11755 op0 = XEXP (op0, 0);
11756 continue;
11759 /* If we are doing a sign bit comparison, it means we are testing
11760 a particular bit. Convert it to the appropriate AND. */
11761 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11762 && mode_width <= HOST_BITS_PER_WIDE_INT)
11764 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11765 ((unsigned HOST_WIDE_INT) 1
11766 << (mode_width - 1
11767 - INTVAL (XEXP (op0, 1)))));
11768 code = (code == LT ? NE : EQ);
11769 continue;
11772 /* If this an equality comparison with zero and we are shifting
11773 the low bit to the sign bit, we can convert this to an AND of the
11774 low-order bit. */
11775 if (const_op == 0 && equality_comparison_p
11776 && CONST_INT_P (XEXP (op0, 1))
11777 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11779 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11780 continue;
11782 break;
11784 case ASHIFTRT:
11785 /* If this is an equality comparison with zero, we can do this
11786 as a logical shift, which might be much simpler. */
11787 if (equality_comparison_p && const_op == 0
11788 && CONST_INT_P (XEXP (op0, 1)))
11790 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11791 XEXP (op0, 0),
11792 INTVAL (XEXP (op0, 1)));
11793 continue;
11796 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11797 do the comparison in a narrower mode. */
11798 if (! unsigned_comparison_p
11799 && CONST_INT_P (XEXP (op0, 1))
11800 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11801 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11802 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11803 MODE_INT, 1)) != BLKmode
11804 && (((unsigned HOST_WIDE_INT) const_op
11805 + (GET_MODE_MASK (tmode) >> 1) + 1)
11806 <= GET_MODE_MASK (tmode)))
11808 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11809 continue;
11812 /* Likewise if OP0 is a PLUS of a sign extension with a
11813 constant, which is usually represented with the PLUS
11814 between the shifts. */
11815 if (! unsigned_comparison_p
11816 && CONST_INT_P (XEXP (op0, 1))
11817 && GET_CODE (XEXP (op0, 0)) == PLUS
11818 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11819 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11820 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11821 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11822 MODE_INT, 1)) != BLKmode
11823 && (((unsigned HOST_WIDE_INT) const_op
11824 + (GET_MODE_MASK (tmode) >> 1) + 1)
11825 <= GET_MODE_MASK (tmode)))
11827 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11828 rtx add_const = XEXP (XEXP (op0, 0), 1);
11829 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11830 add_const, XEXP (op0, 1));
11832 op0 = simplify_gen_binary (PLUS, tmode,
11833 gen_lowpart (tmode, inner),
11834 new_const);
11835 continue;
11838 /* ... fall through ... */
11839 case LSHIFTRT:
11840 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11841 the low order N bits of FOO are known to be zero, we can do this
11842 by comparing FOO with C shifted left N bits so long as no
11843 overflow occurs. Even if the low order N bits of FOO aren't known
11844 to be zero, if the comparison is >= or < we can use the same
11845 optimization and for > or <= by setting all the low
11846 order N bits in the comparison constant. */
11847 if (CONST_INT_P (XEXP (op0, 1))
11848 && INTVAL (XEXP (op0, 1)) > 0
11849 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11850 && mode_width <= HOST_BITS_PER_WIDE_INT
11851 && (((unsigned HOST_WIDE_INT) const_op
11852 + (GET_CODE (op0) != LSHIFTRT
11853 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11854 + 1)
11855 : 0))
11856 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11858 unsigned HOST_WIDE_INT low_bits
11859 = (nonzero_bits (XEXP (op0, 0), mode)
11860 & (((unsigned HOST_WIDE_INT) 1
11861 << INTVAL (XEXP (op0, 1))) - 1));
11862 if (low_bits == 0 || !equality_comparison_p)
11864 /* If the shift was logical, then we must make the condition
11865 unsigned. */
11866 if (GET_CODE (op0) == LSHIFTRT)
11867 code = unsigned_condition (code);
11869 const_op <<= INTVAL (XEXP (op0, 1));
11870 if (low_bits != 0
11871 && (code == GT || code == GTU
11872 || code == LE || code == LEU))
11873 const_op
11874 |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11875 op1 = GEN_INT (const_op);
11876 op0 = XEXP (op0, 0);
11877 continue;
11881 /* If we are using this shift to extract just the sign bit, we
11882 can replace this with an LT or GE comparison. */
11883 if (const_op == 0
11884 && (equality_comparison_p || sign_bit_comparison_p)
11885 && CONST_INT_P (XEXP (op0, 1))
11886 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11888 op0 = XEXP (op0, 0);
11889 code = (code == NE || code == GT ? LT : GE);
11890 continue;
11892 break;
11894 default:
11895 break;
11898 break;
11901 /* Now make any compound operations involved in this comparison. Then,
11902 check for an outmost SUBREG on OP0 that is not doing anything or is
11903 paradoxical. The latter transformation must only be performed when
11904 it is known that the "extra" bits will be the same in op0 and op1 or
11905 that they don't matter. There are three cases to consider:
11907 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11908 care bits and we can assume they have any convenient value. So
11909 making the transformation is safe.
11911 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11912 In this case the upper bits of op0 are undefined. We should not make
11913 the simplification in that case as we do not know the contents of
11914 those bits.
11916 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11917 UNKNOWN. In that case we know those bits are zeros or ones. We must
11918 also be sure that they are the same as the upper bits of op1.
11920 We can never remove a SUBREG for a non-equality comparison because
11921 the sign bit is in a different place in the underlying object. */
11923 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11924 op1 = make_compound_operation (op1, SET);
11926 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11927 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11928 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11929 && (code == NE || code == EQ))
11931 if (paradoxical_subreg_p (op0))
11933 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11934 implemented. */
11935 if (REG_P (SUBREG_REG (op0)))
11937 op0 = SUBREG_REG (op0);
11938 op1 = gen_lowpart (GET_MODE (op0), op1);
11941 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0)))
11942 <= HOST_BITS_PER_WIDE_INT)
11943 && (nonzero_bits (SUBREG_REG (op0),
11944 GET_MODE (SUBREG_REG (op0)))
11945 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11947 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11949 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11950 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11951 op0 = SUBREG_REG (op0), op1 = tem;
11955 /* We now do the opposite procedure: Some machines don't have compare
11956 insns in all modes. If OP0's mode is an integer mode smaller than a
11957 word and we can't do a compare in that mode, see if there is a larger
11958 mode for which we can do the compare. There are a number of cases in
11959 which we can use the wider mode. */
11961 mode = GET_MODE (op0);
11962 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11963 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11964 && ! have_insn_for (COMPARE, mode))
11965 for (tmode = GET_MODE_WIDER_MODE (mode);
11966 (tmode != VOIDmode && HWI_COMPUTABLE_MODE_P (tmode));
11967 tmode = GET_MODE_WIDER_MODE (tmode))
11968 if (have_insn_for (COMPARE, tmode))
11970 int zero_extended;
11972 /* If this is a test for negative, we can make an explicit
11973 test of the sign bit. Test this first so we can use
11974 a paradoxical subreg to extend OP0. */
11976 if (op1 == const0_rtx && (code == LT || code == GE)
11977 && HWI_COMPUTABLE_MODE_P (mode))
11979 unsigned HOST_WIDE_INT sign
11980 = (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1);
11981 op0 = simplify_gen_binary (AND, tmode,
11982 gen_lowpart (tmode, op0),
11983 gen_int_mode (sign, mode));
11984 code = (code == LT) ? NE : EQ;
11985 break;
11988 /* If the only nonzero bits in OP0 and OP1 are those in the
11989 narrower mode and this is an equality or unsigned comparison,
11990 we can use the wider mode. Similarly for sign-extended
11991 values, in which case it is true for all comparisons. */
11992 zero_extended = ((code == EQ || code == NE
11993 || code == GEU || code == GTU
11994 || code == LEU || code == LTU)
11995 && (nonzero_bits (op0, tmode)
11996 & ~GET_MODE_MASK (mode)) == 0
11997 && ((CONST_INT_P (op1)
11998 || (nonzero_bits (op1, tmode)
11999 & ~GET_MODE_MASK (mode)) == 0)));
12001 if (zero_extended
12002 || ((num_sign_bit_copies (op0, tmode)
12003 > (unsigned int) (GET_MODE_PRECISION (tmode)
12004 - GET_MODE_PRECISION (mode)))
12005 && (num_sign_bit_copies (op1, tmode)
12006 > (unsigned int) (GET_MODE_PRECISION (tmode)
12007 - GET_MODE_PRECISION (mode)))))
12009 /* If OP0 is an AND and we don't have an AND in MODE either,
12010 make a new AND in the proper mode. */
12011 if (GET_CODE (op0) == AND
12012 && !have_insn_for (AND, mode))
12013 op0 = simplify_gen_binary (AND, tmode,
12014 gen_lowpart (tmode,
12015 XEXP (op0, 0)),
12016 gen_lowpart (tmode,
12017 XEXP (op0, 1)));
12018 else
12020 if (zero_extended)
12022 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
12023 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
12025 else
12027 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
12028 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
12030 break;
12035 /* We may have changed the comparison operands. Re-canonicalize. */
12036 if (swap_commutative_operands_p (op0, op1))
12038 tem = op0, op0 = op1, op1 = tem;
12039 code = swap_condition (code);
12042 /* If this machine only supports a subset of valid comparisons, see if we
12043 can convert an unsupported one into a supported one. */
12044 target_canonicalize_comparison (&code, &op0, &op1, 0);
12046 *pop0 = op0;
12047 *pop1 = op1;
12049 return code;
12052 /* Utility function for record_value_for_reg. Count number of
12053 rtxs in X. */
12054 static int
12055 count_rtxs (rtx x)
12057 enum rtx_code code = GET_CODE (x);
12058 const char *fmt;
12059 int i, j, ret = 1;
12061 if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
12062 || GET_RTX_CLASS (code) == RTX_COMM_ARITH)
12064 rtx x0 = XEXP (x, 0);
12065 rtx x1 = XEXP (x, 1);
12067 if (x0 == x1)
12068 return 1 + 2 * count_rtxs (x0);
12070 if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH
12071 || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH)
12072 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12073 return 2 + 2 * count_rtxs (x0)
12074 + count_rtxs (x == XEXP (x1, 0)
12075 ? XEXP (x1, 1) : XEXP (x1, 0));
12077 if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH
12078 || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH)
12079 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12080 return 2 + 2 * count_rtxs (x1)
12081 + count_rtxs (x == XEXP (x0, 0)
12082 ? XEXP (x0, 1) : XEXP (x0, 0));
12085 fmt = GET_RTX_FORMAT (code);
12086 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12087 if (fmt[i] == 'e')
12088 ret += count_rtxs (XEXP (x, i));
12089 else if (fmt[i] == 'E')
12090 for (j = 0; j < XVECLEN (x, i); j++)
12091 ret += count_rtxs (XVECEXP (x, i, j));
12093 return ret;
12096 /* Utility function for following routine. Called when X is part of a value
12097 being stored into last_set_value. Sets last_set_table_tick
12098 for each register mentioned. Similar to mention_regs in cse.c */
12100 static void
12101 update_table_tick (rtx x)
12103 enum rtx_code code = GET_CODE (x);
12104 const char *fmt = GET_RTX_FORMAT (code);
12105 int i, j;
12107 if (code == REG)
12109 unsigned int regno = REGNO (x);
12110 unsigned int endregno = END_REGNO (x);
12111 unsigned int r;
12113 for (r = regno; r < endregno; r++)
12115 reg_stat_type *rsp = &reg_stat[r];
12116 rsp->last_set_table_tick = label_tick;
12119 return;
12122 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12123 if (fmt[i] == 'e')
12125 /* Check for identical subexpressions. If x contains
12126 identical subexpression we only have to traverse one of
12127 them. */
12128 if (i == 0 && ARITHMETIC_P (x))
12130 /* Note that at this point x1 has already been
12131 processed. */
12132 rtx x0 = XEXP (x, 0);
12133 rtx x1 = XEXP (x, 1);
12135 /* If x0 and x1 are identical then there is no need to
12136 process x0. */
12137 if (x0 == x1)
12138 break;
12140 /* If x0 is identical to a subexpression of x1 then while
12141 processing x1, x0 has already been processed. Thus we
12142 are done with x. */
12143 if (ARITHMETIC_P (x1)
12144 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12145 break;
12147 /* If x1 is identical to a subexpression of x0 then we
12148 still have to process the rest of x0. */
12149 if (ARITHMETIC_P (x0)
12150 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12152 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12153 break;
12157 update_table_tick (XEXP (x, i));
12159 else if (fmt[i] == 'E')
12160 for (j = 0; j < XVECLEN (x, i); j++)
12161 update_table_tick (XVECEXP (x, i, j));
12164 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12165 are saying that the register is clobbered and we no longer know its
12166 value. If INSN is zero, don't update reg_stat[].last_set; this is
12167 only permitted with VALUE also zero and is used to invalidate the
12168 register. */
12170 static void
12171 record_value_for_reg (rtx reg, rtx insn, rtx value)
12173 unsigned int regno = REGNO (reg);
12174 unsigned int endregno = END_REGNO (reg);
12175 unsigned int i;
12176 reg_stat_type *rsp;
12178 /* If VALUE contains REG and we have a previous value for REG, substitute
12179 the previous value. */
12180 if (value && insn && reg_overlap_mentioned_p (reg, value))
12182 rtx tem;
12184 /* Set things up so get_last_value is allowed to see anything set up to
12185 our insn. */
12186 subst_low_luid = DF_INSN_LUID (insn);
12187 tem = get_last_value (reg);
12189 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12190 it isn't going to be useful and will take a lot of time to process,
12191 so just use the CLOBBER. */
12193 if (tem)
12195 if (ARITHMETIC_P (tem)
12196 && GET_CODE (XEXP (tem, 0)) == CLOBBER
12197 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12198 tem = XEXP (tem, 0);
12199 else if (count_occurrences (value, reg, 1) >= 2)
12201 /* If there are two or more occurrences of REG in VALUE,
12202 prevent the value from growing too much. */
12203 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12204 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12207 value = replace_rtx (copy_rtx (value), reg, tem);
12211 /* For each register modified, show we don't know its value, that
12212 we don't know about its bitwise content, that its value has been
12213 updated, and that we don't know the location of the death of the
12214 register. */
12215 for (i = regno; i < endregno; i++)
12217 rsp = &reg_stat[i];
12219 if (insn)
12220 rsp->last_set = insn;
12222 rsp->last_set_value = 0;
12223 rsp->last_set_mode = VOIDmode;
12224 rsp->last_set_nonzero_bits = 0;
12225 rsp->last_set_sign_bit_copies = 0;
12226 rsp->last_death = 0;
12227 rsp->truncated_to_mode = VOIDmode;
12230 /* Mark registers that are being referenced in this value. */
12231 if (value)
12232 update_table_tick (value);
12234 /* Now update the status of each register being set.
12235 If someone is using this register in this block, set this register
12236 to invalid since we will get confused between the two lives in this
12237 basic block. This makes using this register always invalid. In cse, we
12238 scan the table to invalidate all entries using this register, but this
12239 is too much work for us. */
12241 for (i = regno; i < endregno; i++)
12243 rsp = &reg_stat[i];
12244 rsp->last_set_label = label_tick;
12245 if (!insn
12246 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12247 rsp->last_set_invalid = 1;
12248 else
12249 rsp->last_set_invalid = 0;
12252 /* The value being assigned might refer to X (like in "x++;"). In that
12253 case, we must replace it with (clobber (const_int 0)) to prevent
12254 infinite loops. */
12255 rsp = &reg_stat[regno];
12256 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12258 value = copy_rtx (value);
12259 if (!get_last_value_validate (&value, insn, label_tick, 1))
12260 value = 0;
12263 /* For the main register being modified, update the value, the mode, the
12264 nonzero bits, and the number of sign bit copies. */
12266 rsp->last_set_value = value;
12268 if (value)
12270 enum machine_mode mode = GET_MODE (reg);
12271 subst_low_luid = DF_INSN_LUID (insn);
12272 rsp->last_set_mode = mode;
12273 if (GET_MODE_CLASS (mode) == MODE_INT
12274 && HWI_COMPUTABLE_MODE_P (mode))
12275 mode = nonzero_bits_mode;
12276 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12277 rsp->last_set_sign_bit_copies
12278 = num_sign_bit_copies (value, GET_MODE (reg));
12282 /* Called via note_stores from record_dead_and_set_regs to handle one
12283 SET or CLOBBER in an insn. DATA is the instruction in which the
12284 set is occurring. */
12286 static void
12287 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12289 rtx record_dead_insn = (rtx) data;
12291 if (GET_CODE (dest) == SUBREG)
12292 dest = SUBREG_REG (dest);
12294 if (!record_dead_insn)
12296 if (REG_P (dest))
12297 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12298 return;
12301 if (REG_P (dest))
12303 /* If we are setting the whole register, we know its value. Otherwise
12304 show that we don't know the value. We can handle SUBREG in
12305 some cases. */
12306 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12307 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12308 else if (GET_CODE (setter) == SET
12309 && GET_CODE (SET_DEST (setter)) == SUBREG
12310 && SUBREG_REG (SET_DEST (setter)) == dest
12311 && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD
12312 && subreg_lowpart_p (SET_DEST (setter)))
12313 record_value_for_reg (dest, record_dead_insn,
12314 gen_lowpart (GET_MODE (dest),
12315 SET_SRC (setter)));
12316 else
12317 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12319 else if (MEM_P (dest)
12320 /* Ignore pushes, they clobber nothing. */
12321 && ! push_operand (dest, GET_MODE (dest)))
12322 mem_last_set = DF_INSN_LUID (record_dead_insn);
12325 /* Update the records of when each REG was most recently set or killed
12326 for the things done by INSN. This is the last thing done in processing
12327 INSN in the combiner loop.
12329 We update reg_stat[], in particular fields last_set, last_set_value,
12330 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12331 last_death, and also the similar information mem_last_set (which insn
12332 most recently modified memory) and last_call_luid (which insn was the
12333 most recent subroutine call). */
12335 static void
12336 record_dead_and_set_regs (rtx insn)
12338 rtx link;
12339 unsigned int i;
12341 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12343 if (REG_NOTE_KIND (link) == REG_DEAD
12344 && REG_P (XEXP (link, 0)))
12346 unsigned int regno = REGNO (XEXP (link, 0));
12347 unsigned int endregno = END_REGNO (XEXP (link, 0));
12349 for (i = regno; i < endregno; i++)
12351 reg_stat_type *rsp;
12353 rsp = &reg_stat[i];
12354 rsp->last_death = insn;
12357 else if (REG_NOTE_KIND (link) == REG_INC)
12358 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12361 if (CALL_P (insn))
12363 hard_reg_set_iterator hrsi;
12364 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, 0, i, hrsi)
12366 reg_stat_type *rsp;
12368 rsp = &reg_stat[i];
12369 rsp->last_set_invalid = 1;
12370 rsp->last_set = insn;
12371 rsp->last_set_value = 0;
12372 rsp->last_set_mode = VOIDmode;
12373 rsp->last_set_nonzero_bits = 0;
12374 rsp->last_set_sign_bit_copies = 0;
12375 rsp->last_death = 0;
12376 rsp->truncated_to_mode = VOIDmode;
12379 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12381 /* We can't combine into a call pattern. Remember, though, that
12382 the return value register is set at this LUID. We could
12383 still replace a register with the return value from the
12384 wrong subroutine call! */
12385 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12387 else
12388 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12391 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12392 register present in the SUBREG, so for each such SUBREG go back and
12393 adjust nonzero and sign bit information of the registers that are
12394 known to have some zero/sign bits set.
12396 This is needed because when combine blows the SUBREGs away, the
12397 information on zero/sign bits is lost and further combines can be
12398 missed because of that. */
12400 static void
12401 record_promoted_value (rtx insn, rtx subreg)
12403 struct insn_link *links;
12404 rtx set;
12405 unsigned int regno = REGNO (SUBREG_REG (subreg));
12406 enum machine_mode mode = GET_MODE (subreg);
12408 if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT)
12409 return;
12411 for (links = LOG_LINKS (insn); links;)
12413 reg_stat_type *rsp;
12415 insn = links->insn;
12416 set = single_set (insn);
12418 if (! set || !REG_P (SET_DEST (set))
12419 || REGNO (SET_DEST (set)) != regno
12420 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12422 links = links->next;
12423 continue;
12426 rsp = &reg_stat[regno];
12427 if (rsp->last_set == insn)
12429 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12430 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12433 if (REG_P (SET_SRC (set)))
12435 regno = REGNO (SET_SRC (set));
12436 links = LOG_LINKS (insn);
12438 else
12439 break;
12443 /* Check if X, a register, is known to contain a value already
12444 truncated to MODE. In this case we can use a subreg to refer to
12445 the truncated value even though in the generic case we would need
12446 an explicit truncation. */
12448 static bool
12449 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12451 reg_stat_type *rsp = &reg_stat[REGNO (x)];
12452 enum machine_mode truncated = rsp->truncated_to_mode;
12454 if (truncated == 0
12455 || rsp->truncation_label < label_tick_ebb_start)
12456 return false;
12457 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12458 return true;
12459 if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
12460 return true;
12461 return false;
12464 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12465 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12466 might be able to turn a truncate into a subreg using this information.
12467 Return -1 if traversing *P is complete or 0 otherwise. */
12469 static int
12470 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12472 rtx x = *p;
12473 enum machine_mode truncated_mode;
12474 reg_stat_type *rsp;
12476 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12478 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12479 truncated_mode = GET_MODE (x);
12481 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12482 return -1;
12484 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
12485 return -1;
12487 x = SUBREG_REG (x);
12489 /* ??? For hard-regs we now record everything. We might be able to
12490 optimize this using last_set_mode. */
12491 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12492 truncated_mode = GET_MODE (x);
12493 else
12494 return 0;
12496 rsp = &reg_stat[REGNO (x)];
12497 if (rsp->truncated_to_mode == 0
12498 || rsp->truncation_label < label_tick_ebb_start
12499 || (GET_MODE_SIZE (truncated_mode)
12500 < GET_MODE_SIZE (rsp->truncated_to_mode)))
12502 rsp->truncated_to_mode = truncated_mode;
12503 rsp->truncation_label = label_tick;
12506 return -1;
12509 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12510 the modes they are used in. This can help truning TRUNCATEs into
12511 SUBREGs. */
12513 static void
12514 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12516 for_each_rtx (x, record_truncated_value, NULL);
12519 /* Scan X for promoted SUBREGs. For each one found,
12520 note what it implies to the registers used in it. */
12522 static void
12523 check_promoted_subreg (rtx insn, rtx x)
12525 if (GET_CODE (x) == SUBREG
12526 && SUBREG_PROMOTED_VAR_P (x)
12527 && REG_P (SUBREG_REG (x)))
12528 record_promoted_value (insn, x);
12529 else
12531 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12532 int i, j;
12534 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12535 switch (format[i])
12537 case 'e':
12538 check_promoted_subreg (insn, XEXP (x, i));
12539 break;
12540 case 'V':
12541 case 'E':
12542 if (XVEC (x, i) != 0)
12543 for (j = 0; j < XVECLEN (x, i); j++)
12544 check_promoted_subreg (insn, XVECEXP (x, i, j));
12545 break;
12550 /* Verify that all the registers and memory references mentioned in *LOC are
12551 still valid. *LOC was part of a value set in INSN when label_tick was
12552 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12553 the invalid references with (clobber (const_int 0)) and return 1. This
12554 replacement is useful because we often can get useful information about
12555 the form of a value (e.g., if it was produced by a shift that always
12556 produces -1 or 0) even though we don't know exactly what registers it
12557 was produced from. */
12559 static int
12560 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12562 rtx x = *loc;
12563 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12564 int len = GET_RTX_LENGTH (GET_CODE (x));
12565 int i, j;
12567 if (REG_P (x))
12569 unsigned int regno = REGNO (x);
12570 unsigned int endregno = END_REGNO (x);
12571 unsigned int j;
12573 for (j = regno; j < endregno; j++)
12575 reg_stat_type *rsp = &reg_stat[j];
12576 if (rsp->last_set_invalid
12577 /* If this is a pseudo-register that was only set once and not
12578 live at the beginning of the function, it is always valid. */
12579 || (! (regno >= FIRST_PSEUDO_REGISTER
12580 && REG_N_SETS (regno) == 1
12581 && (!REGNO_REG_SET_P
12582 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
12583 regno)))
12584 && rsp->last_set_label > tick))
12586 if (replace)
12587 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12588 return replace;
12592 return 1;
12594 /* If this is a memory reference, make sure that there were no stores after
12595 it that might have clobbered the value. We don't have alias info, so we
12596 assume any store invalidates it. Moreover, we only have local UIDs, so
12597 we also assume that there were stores in the intervening basic blocks. */
12598 else if (MEM_P (x) && !MEM_READONLY_P (x)
12599 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12601 if (replace)
12602 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12603 return replace;
12606 for (i = 0; i < len; i++)
12608 if (fmt[i] == 'e')
12610 /* Check for identical subexpressions. If x contains
12611 identical subexpression we only have to traverse one of
12612 them. */
12613 if (i == 1 && ARITHMETIC_P (x))
12615 /* Note that at this point x0 has already been checked
12616 and found valid. */
12617 rtx x0 = XEXP (x, 0);
12618 rtx x1 = XEXP (x, 1);
12620 /* If x0 and x1 are identical then x is also valid. */
12621 if (x0 == x1)
12622 return 1;
12624 /* If x1 is identical to a subexpression of x0 then
12625 while checking x0, x1 has already been checked. Thus
12626 it is valid and so as x. */
12627 if (ARITHMETIC_P (x0)
12628 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12629 return 1;
12631 /* If x0 is identical to a subexpression of x1 then x is
12632 valid iff the rest of x1 is valid. */
12633 if (ARITHMETIC_P (x1)
12634 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12635 return
12636 get_last_value_validate (&XEXP (x1,
12637 x0 == XEXP (x1, 0) ? 1 : 0),
12638 insn, tick, replace);
12641 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12642 replace) == 0)
12643 return 0;
12645 else if (fmt[i] == 'E')
12646 for (j = 0; j < XVECLEN (x, i); j++)
12647 if (get_last_value_validate (&XVECEXP (x, i, j),
12648 insn, tick, replace) == 0)
12649 return 0;
12652 /* If we haven't found a reason for it to be invalid, it is valid. */
12653 return 1;
12656 /* Get the last value assigned to X, if known. Some registers
12657 in the value may be replaced with (clobber (const_int 0)) if their value
12658 is known longer known reliably. */
12660 static rtx
12661 get_last_value (const_rtx x)
12663 unsigned int regno;
12664 rtx value;
12665 reg_stat_type *rsp;
12667 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12668 then convert it to the desired mode. If this is a paradoxical SUBREG,
12669 we cannot predict what values the "extra" bits might have. */
12670 if (GET_CODE (x) == SUBREG
12671 && subreg_lowpart_p (x)
12672 && !paradoxical_subreg_p (x)
12673 && (value = get_last_value (SUBREG_REG (x))) != 0)
12674 return gen_lowpart (GET_MODE (x), value);
12676 if (!REG_P (x))
12677 return 0;
12679 regno = REGNO (x);
12680 rsp = &reg_stat[regno];
12681 value = rsp->last_set_value;
12683 /* If we don't have a value, or if it isn't for this basic block and
12684 it's either a hard register, set more than once, or it's a live
12685 at the beginning of the function, return 0.
12687 Because if it's not live at the beginning of the function then the reg
12688 is always set before being used (is never used without being set).
12689 And, if it's set only once, and it's always set before use, then all
12690 uses must have the same last value, even if it's not from this basic
12691 block. */
12693 if (value == 0
12694 || (rsp->last_set_label < label_tick_ebb_start
12695 && (regno < FIRST_PSEUDO_REGISTER
12696 || REG_N_SETS (regno) != 1
12697 || REGNO_REG_SET_P
12698 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), regno))))
12699 return 0;
12701 /* If the value was set in a later insn than the ones we are processing,
12702 we can't use it even if the register was only set once. */
12703 if (rsp->last_set_label == label_tick
12704 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12705 return 0;
12707 /* If the value has all its registers valid, return it. */
12708 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12709 return value;
12711 /* Otherwise, make a copy and replace any invalid register with
12712 (clobber (const_int 0)). If that fails for some reason, return 0. */
12714 value = copy_rtx (value);
12715 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12716 return value;
12718 return 0;
12721 /* Return nonzero if expression X refers to a REG or to memory
12722 that is set in an instruction more recent than FROM_LUID. */
12724 static int
12725 use_crosses_set_p (const_rtx x, int from_luid)
12727 const char *fmt;
12728 int i;
12729 enum rtx_code code = GET_CODE (x);
12731 if (code == REG)
12733 unsigned int regno = REGNO (x);
12734 unsigned endreg = END_REGNO (x);
12736 #ifdef PUSH_ROUNDING
12737 /* Don't allow uses of the stack pointer to be moved,
12738 because we don't know whether the move crosses a push insn. */
12739 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12740 return 1;
12741 #endif
12742 for (; regno < endreg; regno++)
12744 reg_stat_type *rsp = &reg_stat[regno];
12745 if (rsp->last_set
12746 && rsp->last_set_label == label_tick
12747 && DF_INSN_LUID (rsp->last_set) > from_luid)
12748 return 1;
12750 return 0;
12753 if (code == MEM && mem_last_set > from_luid)
12754 return 1;
12756 fmt = GET_RTX_FORMAT (code);
12758 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12760 if (fmt[i] == 'E')
12762 int j;
12763 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12764 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12765 return 1;
12767 else if (fmt[i] == 'e'
12768 && use_crosses_set_p (XEXP (x, i), from_luid))
12769 return 1;
12771 return 0;
12774 /* Define three variables used for communication between the following
12775 routines. */
12777 static unsigned int reg_dead_regno, reg_dead_endregno;
12778 static int reg_dead_flag;
12780 /* Function called via note_stores from reg_dead_at_p.
12782 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12783 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12785 static void
12786 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12788 unsigned int regno, endregno;
12790 if (!REG_P (dest))
12791 return;
12793 regno = REGNO (dest);
12794 endregno = END_REGNO (dest);
12795 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12796 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12799 /* Return nonzero if REG is known to be dead at INSN.
12801 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12802 referencing REG, it is dead. If we hit a SET referencing REG, it is
12803 live. Otherwise, see if it is live or dead at the start of the basic
12804 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12805 must be assumed to be always live. */
12807 static int
12808 reg_dead_at_p (rtx reg, rtx insn)
12810 basic_block block;
12811 unsigned int i;
12813 /* Set variables for reg_dead_at_p_1. */
12814 reg_dead_regno = REGNO (reg);
12815 reg_dead_endregno = END_REGNO (reg);
12817 reg_dead_flag = 0;
12819 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12820 we allow the machine description to decide whether use-and-clobber
12821 patterns are OK. */
12822 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12824 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12825 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12826 return 0;
12829 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12830 beginning of basic block. */
12831 block = BLOCK_FOR_INSN (insn);
12832 for (;;)
12834 if (INSN_P (insn))
12836 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12837 if (reg_dead_flag)
12838 return reg_dead_flag == 1 ? 1 : 0;
12840 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12841 return 1;
12844 if (insn == BB_HEAD (block))
12845 break;
12847 insn = PREV_INSN (insn);
12850 /* Look at live-in sets for the basic block that we were in. */
12851 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12852 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12853 return 0;
12855 return 1;
12858 /* Note hard registers in X that are used. */
12860 static void
12861 mark_used_regs_combine (rtx x)
12863 RTX_CODE code = GET_CODE (x);
12864 unsigned int regno;
12865 int i;
12867 switch (code)
12869 case LABEL_REF:
12870 case SYMBOL_REF:
12871 case CONST:
12872 CASE_CONST_ANY:
12873 case PC:
12874 case ADDR_VEC:
12875 case ADDR_DIFF_VEC:
12876 case ASM_INPUT:
12877 #ifdef HAVE_cc0
12878 /* CC0 must die in the insn after it is set, so we don't need to take
12879 special note of it here. */
12880 case CC0:
12881 #endif
12882 return;
12884 case CLOBBER:
12885 /* If we are clobbering a MEM, mark any hard registers inside the
12886 address as used. */
12887 if (MEM_P (XEXP (x, 0)))
12888 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12889 return;
12891 case REG:
12892 regno = REGNO (x);
12893 /* A hard reg in a wide mode may really be multiple registers.
12894 If so, mark all of them just like the first. */
12895 if (regno < FIRST_PSEUDO_REGISTER)
12897 /* None of this applies to the stack, frame or arg pointers. */
12898 if (regno == STACK_POINTER_REGNUM
12899 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12900 || regno == HARD_FRAME_POINTER_REGNUM
12901 #endif
12902 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12903 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12904 #endif
12905 || regno == FRAME_POINTER_REGNUM)
12906 return;
12908 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12910 return;
12912 case SET:
12914 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12915 the address. */
12916 rtx testreg = SET_DEST (x);
12918 while (GET_CODE (testreg) == SUBREG
12919 || GET_CODE (testreg) == ZERO_EXTRACT
12920 || GET_CODE (testreg) == STRICT_LOW_PART)
12921 testreg = XEXP (testreg, 0);
12923 if (MEM_P (testreg))
12924 mark_used_regs_combine (XEXP (testreg, 0));
12926 mark_used_regs_combine (SET_SRC (x));
12928 return;
12930 default:
12931 break;
12934 /* Recursively scan the operands of this expression. */
12937 const char *fmt = GET_RTX_FORMAT (code);
12939 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12941 if (fmt[i] == 'e')
12942 mark_used_regs_combine (XEXP (x, i));
12943 else if (fmt[i] == 'E')
12945 int j;
12947 for (j = 0; j < XVECLEN (x, i); j++)
12948 mark_used_regs_combine (XVECEXP (x, i, j));
12954 /* Remove register number REGNO from the dead registers list of INSN.
12956 Return the note used to record the death, if there was one. */
12959 remove_death (unsigned int regno, rtx insn)
12961 rtx note = find_regno_note (insn, REG_DEAD, regno);
12963 if (note)
12964 remove_note (insn, note);
12966 return note;
12969 /* For each register (hardware or pseudo) used within expression X, if its
12970 death is in an instruction with luid between FROM_LUID (inclusive) and
12971 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12972 list headed by PNOTES.
12974 That said, don't move registers killed by maybe_kill_insn.
12976 This is done when X is being merged by combination into TO_INSN. These
12977 notes will then be distributed as needed. */
12979 static void
12980 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12981 rtx *pnotes)
12983 const char *fmt;
12984 int len, i;
12985 enum rtx_code code = GET_CODE (x);
12987 if (code == REG)
12989 unsigned int regno = REGNO (x);
12990 rtx where_dead = reg_stat[regno].last_death;
12992 /* Don't move the register if it gets killed in between from and to. */
12993 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12994 && ! reg_referenced_p (x, maybe_kill_insn))
12995 return;
12997 if (where_dead
12998 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12999 && DF_INSN_LUID (where_dead) >= from_luid
13000 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
13002 rtx note = remove_death (regno, where_dead);
13004 /* It is possible for the call above to return 0. This can occur
13005 when last_death points to I2 or I1 that we combined with.
13006 In that case make a new note.
13008 We must also check for the case where X is a hard register
13009 and NOTE is a death note for a range of hard registers
13010 including X. In that case, we must put REG_DEAD notes for
13011 the remaining registers in place of NOTE. */
13013 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
13014 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13015 > GET_MODE_SIZE (GET_MODE (x))))
13017 unsigned int deadregno = REGNO (XEXP (note, 0));
13018 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
13019 unsigned int ourend = END_HARD_REGNO (x);
13020 unsigned int i;
13022 for (i = deadregno; i < deadend; i++)
13023 if (i < regno || i >= ourend)
13024 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
13027 /* If we didn't find any note, or if we found a REG_DEAD note that
13028 covers only part of the given reg, and we have a multi-reg hard
13029 register, then to be safe we must check for REG_DEAD notes
13030 for each register other than the first. They could have
13031 their own REG_DEAD notes lying around. */
13032 else if ((note == 0
13033 || (note != 0
13034 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13035 < GET_MODE_SIZE (GET_MODE (x)))))
13036 && regno < FIRST_PSEUDO_REGISTER
13037 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
13039 unsigned int ourend = END_HARD_REGNO (x);
13040 unsigned int i, offset;
13041 rtx oldnotes = 0;
13043 if (note)
13044 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13045 else
13046 offset = 1;
13048 for (i = regno + offset; i < ourend; i++)
13049 move_deaths (regno_reg_rtx[i],
13050 maybe_kill_insn, from_luid, to_insn, &oldnotes);
13053 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13055 XEXP (note, 1) = *pnotes;
13056 *pnotes = note;
13058 else
13059 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13062 return;
13065 else if (GET_CODE (x) == SET)
13067 rtx dest = SET_DEST (x);
13069 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13071 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13072 that accesses one word of a multi-word item, some
13073 piece of everything register in the expression is used by
13074 this insn, so remove any old death. */
13075 /* ??? So why do we test for equality of the sizes? */
13077 if (GET_CODE (dest) == ZERO_EXTRACT
13078 || GET_CODE (dest) == STRICT_LOW_PART
13079 || (GET_CODE (dest) == SUBREG
13080 && (((GET_MODE_SIZE (GET_MODE (dest))
13081 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13082 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13083 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13085 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13086 return;
13089 /* If this is some other SUBREG, we know it replaces the entire
13090 value, so use that as the destination. */
13091 if (GET_CODE (dest) == SUBREG)
13092 dest = SUBREG_REG (dest);
13094 /* If this is a MEM, adjust deaths of anything used in the address.
13095 For a REG (the only other possibility), the entire value is
13096 being replaced so the old value is not used in this insn. */
13098 if (MEM_P (dest))
13099 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13100 to_insn, pnotes);
13101 return;
13104 else if (GET_CODE (x) == CLOBBER)
13105 return;
13107 len = GET_RTX_LENGTH (code);
13108 fmt = GET_RTX_FORMAT (code);
13110 for (i = 0; i < len; i++)
13112 if (fmt[i] == 'E')
13114 int j;
13115 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13116 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13117 to_insn, pnotes);
13119 else if (fmt[i] == 'e')
13120 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13124 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13125 pattern of an insn. X must be a REG. */
13127 static int
13128 reg_bitfield_target_p (rtx x, rtx body)
13130 int i;
13132 if (GET_CODE (body) == SET)
13134 rtx dest = SET_DEST (body);
13135 rtx target;
13136 unsigned int regno, tregno, endregno, endtregno;
13138 if (GET_CODE (dest) == ZERO_EXTRACT)
13139 target = XEXP (dest, 0);
13140 else if (GET_CODE (dest) == STRICT_LOW_PART)
13141 target = SUBREG_REG (XEXP (dest, 0));
13142 else
13143 return 0;
13145 if (GET_CODE (target) == SUBREG)
13146 target = SUBREG_REG (target);
13148 if (!REG_P (target))
13149 return 0;
13151 tregno = REGNO (target), regno = REGNO (x);
13152 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13153 return target == x;
13155 endtregno = end_hard_regno (GET_MODE (target), tregno);
13156 endregno = end_hard_regno (GET_MODE (x), regno);
13158 return endregno > tregno && regno < endtregno;
13161 else if (GET_CODE (body) == PARALLEL)
13162 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13163 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13164 return 1;
13166 return 0;
13169 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13170 as appropriate. I3 and I2 are the insns resulting from the combination
13171 insns including FROM (I2 may be zero).
13173 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13174 not need REG_DEAD notes because they are being substituted for. This
13175 saves searching in the most common cases.
13177 Each note in the list is either ignored or placed on some insns, depending
13178 on the type of note. */
13180 static void
13181 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13182 rtx elim_i1, rtx elim_i0)
13184 rtx note, next_note;
13185 rtx tem;
13187 for (note = notes; note; note = next_note)
13189 rtx place = 0, place2 = 0;
13191 next_note = XEXP (note, 1);
13192 switch (REG_NOTE_KIND (note))
13194 case REG_BR_PROB:
13195 case REG_BR_PRED:
13196 /* Doesn't matter much where we put this, as long as it's somewhere.
13197 It is preferable to keep these notes on branches, which is most
13198 likely to be i3. */
13199 place = i3;
13200 break;
13202 case REG_NON_LOCAL_GOTO:
13203 if (JUMP_P (i3))
13204 place = i3;
13205 else
13207 gcc_assert (i2 && JUMP_P (i2));
13208 place = i2;
13210 break;
13212 case REG_EH_REGION:
13213 /* These notes must remain with the call or trapping instruction. */
13214 if (CALL_P (i3))
13215 place = i3;
13216 else if (i2 && CALL_P (i2))
13217 place = i2;
13218 else
13220 gcc_assert (cfun->can_throw_non_call_exceptions);
13221 if (may_trap_p (i3))
13222 place = i3;
13223 else if (i2 && may_trap_p (i2))
13224 place = i2;
13225 /* ??? Otherwise assume we've combined things such that we
13226 can now prove that the instructions can't trap. Drop the
13227 note in this case. */
13229 break;
13231 case REG_ARGS_SIZE:
13232 /* ??? How to distribute between i3-i1. Assume i3 contains the
13233 entire adjustment. Assert i3 contains at least some adjust. */
13234 if (!noop_move_p (i3))
13236 int old_size, args_size = INTVAL (XEXP (note, 0));
13237 /* fixup_args_size_notes looks at REG_NORETURN note,
13238 so ensure the note is placed there first. */
13239 if (CALL_P (i3))
13241 rtx *np;
13242 for (np = &next_note; *np; np = &XEXP (*np, 1))
13243 if (REG_NOTE_KIND (*np) == REG_NORETURN)
13245 rtx n = *np;
13246 *np = XEXP (n, 1);
13247 XEXP (n, 1) = REG_NOTES (i3);
13248 REG_NOTES (i3) = n;
13249 break;
13252 old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
13253 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13254 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13255 gcc_assert (old_size != args_size
13256 || (CALL_P (i3)
13257 && !ACCUMULATE_OUTGOING_ARGS
13258 && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
13260 break;
13262 case REG_NORETURN:
13263 case REG_SETJMP:
13264 case REG_TM:
13265 /* These notes must remain with the call. It should not be
13266 possible for both I2 and I3 to be a call. */
13267 if (CALL_P (i3))
13268 place = i3;
13269 else
13271 gcc_assert (i2 && CALL_P (i2));
13272 place = i2;
13274 break;
13276 case REG_UNUSED:
13277 /* Any clobbers for i3 may still exist, and so we must process
13278 REG_UNUSED notes from that insn.
13280 Any clobbers from i2 or i1 can only exist if they were added by
13281 recog_for_combine. In that case, recog_for_combine created the
13282 necessary REG_UNUSED notes. Trying to keep any original
13283 REG_UNUSED notes from these insns can cause incorrect output
13284 if it is for the same register as the original i3 dest.
13285 In that case, we will notice that the register is set in i3,
13286 and then add a REG_UNUSED note for the destination of i3, which
13287 is wrong. However, it is possible to have REG_UNUSED notes from
13288 i2 or i1 for register which were both used and clobbered, so
13289 we keep notes from i2 or i1 if they will turn into REG_DEAD
13290 notes. */
13292 /* If this register is set or clobbered in I3, put the note there
13293 unless there is one already. */
13294 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13296 if (from_insn != i3)
13297 break;
13299 if (! (REG_P (XEXP (note, 0))
13300 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13301 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13302 place = i3;
13304 /* Otherwise, if this register is used by I3, then this register
13305 now dies here, so we must put a REG_DEAD note here unless there
13306 is one already. */
13307 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13308 && ! (REG_P (XEXP (note, 0))
13309 ? find_regno_note (i3, REG_DEAD,
13310 REGNO (XEXP (note, 0)))
13311 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13313 PUT_REG_NOTE_KIND (note, REG_DEAD);
13314 place = i3;
13316 break;
13318 case REG_EQUAL:
13319 case REG_EQUIV:
13320 case REG_NOALIAS:
13321 /* These notes say something about results of an insn. We can
13322 only support them if they used to be on I3 in which case they
13323 remain on I3. Otherwise they are ignored.
13325 If the note refers to an expression that is not a constant, we
13326 must also ignore the note since we cannot tell whether the
13327 equivalence is still true. It might be possible to do
13328 slightly better than this (we only have a problem if I2DEST
13329 or I1DEST is present in the expression), but it doesn't
13330 seem worth the trouble. */
13332 if (from_insn == i3
13333 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13334 place = i3;
13335 break;
13337 case REG_INC:
13338 /* These notes say something about how a register is used. They must
13339 be present on any use of the register in I2 or I3. */
13340 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13341 place = i3;
13343 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13345 if (place)
13346 place2 = i2;
13347 else
13348 place = i2;
13350 break;
13352 case REG_LABEL_TARGET:
13353 case REG_LABEL_OPERAND:
13354 /* This can show up in several ways -- either directly in the
13355 pattern, or hidden off in the constant pool with (or without?)
13356 a REG_EQUAL note. */
13357 /* ??? Ignore the without-reg_equal-note problem for now. */
13358 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13359 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13360 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13361 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13362 place = i3;
13364 if (i2
13365 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13366 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13367 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13368 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13370 if (place)
13371 place2 = i2;
13372 else
13373 place = i2;
13376 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13377 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13378 there. */
13379 if (place && JUMP_P (place)
13380 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13381 && (JUMP_LABEL (place) == NULL
13382 || JUMP_LABEL (place) == XEXP (note, 0)))
13384 rtx label = JUMP_LABEL (place);
13386 if (!label)
13387 JUMP_LABEL (place) = XEXP (note, 0);
13388 else if (LABEL_P (label))
13389 LABEL_NUSES (label)--;
13392 if (place2 && JUMP_P (place2)
13393 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13394 && (JUMP_LABEL (place2) == NULL
13395 || JUMP_LABEL (place2) == XEXP (note, 0)))
13397 rtx label = JUMP_LABEL (place2);
13399 if (!label)
13400 JUMP_LABEL (place2) = XEXP (note, 0);
13401 else if (LABEL_P (label))
13402 LABEL_NUSES (label)--;
13403 place2 = 0;
13405 break;
13407 case REG_NONNEG:
13408 /* This note says something about the value of a register prior
13409 to the execution of an insn. It is too much trouble to see
13410 if the note is still correct in all situations. It is better
13411 to simply delete it. */
13412 break;
13414 case REG_DEAD:
13415 /* If we replaced the right hand side of FROM_INSN with a
13416 REG_EQUAL note, the original use of the dying register
13417 will not have been combined into I3 and I2. In such cases,
13418 FROM_INSN is guaranteed to be the first of the combined
13419 instructions, so we simply need to search back before
13420 FROM_INSN for the previous use or set of this register,
13421 then alter the notes there appropriately.
13423 If the register is used as an input in I3, it dies there.
13424 Similarly for I2, if it is nonzero and adjacent to I3.
13426 If the register is not used as an input in either I3 or I2
13427 and it is not one of the registers we were supposed to eliminate,
13428 there are two possibilities. We might have a non-adjacent I2
13429 or we might have somehow eliminated an additional register
13430 from a computation. For example, we might have had A & B where
13431 we discover that B will always be zero. In this case we will
13432 eliminate the reference to A.
13434 In both cases, we must search to see if we can find a previous
13435 use of A and put the death note there. */
13437 if (from_insn
13438 && from_insn == i2mod
13439 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13440 tem = from_insn;
13441 else
13443 if (from_insn
13444 && CALL_P (from_insn)
13445 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13446 place = from_insn;
13447 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13448 place = i3;
13449 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13450 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13451 place = i2;
13452 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13453 && !(i2mod
13454 && reg_overlap_mentioned_p (XEXP (note, 0),
13455 i2mod_old_rhs)))
13456 || rtx_equal_p (XEXP (note, 0), elim_i1)
13457 || rtx_equal_p (XEXP (note, 0), elim_i0))
13458 break;
13459 tem = i3;
13462 if (place == 0)
13464 basic_block bb = this_basic_block;
13466 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13468 if (!NONDEBUG_INSN_P (tem))
13470 if (tem == BB_HEAD (bb))
13471 break;
13472 continue;
13475 /* If the register is being set at TEM, see if that is all
13476 TEM is doing. If so, delete TEM. Otherwise, make this
13477 into a REG_UNUSED note instead. Don't delete sets to
13478 global register vars. */
13479 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13480 || !global_regs[REGNO (XEXP (note, 0))])
13481 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13483 rtx set = single_set (tem);
13484 rtx inner_dest = 0;
13485 #ifdef HAVE_cc0
13486 rtx cc0_setter = NULL_RTX;
13487 #endif
13489 if (set != 0)
13490 for (inner_dest = SET_DEST (set);
13491 (GET_CODE (inner_dest) == STRICT_LOW_PART
13492 || GET_CODE (inner_dest) == SUBREG
13493 || GET_CODE (inner_dest) == ZERO_EXTRACT);
13494 inner_dest = XEXP (inner_dest, 0))
13497 /* Verify that it was the set, and not a clobber that
13498 modified the register.
13500 CC0 targets must be careful to maintain setter/user
13501 pairs. If we cannot delete the setter due to side
13502 effects, mark the user with an UNUSED note instead
13503 of deleting it. */
13505 if (set != 0 && ! side_effects_p (SET_SRC (set))
13506 && rtx_equal_p (XEXP (note, 0), inner_dest)
13507 #ifdef HAVE_cc0
13508 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13509 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13510 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13511 #endif
13514 /* Move the notes and links of TEM elsewhere.
13515 This might delete other dead insns recursively.
13516 First set the pattern to something that won't use
13517 any register. */
13518 rtx old_notes = REG_NOTES (tem);
13520 PATTERN (tem) = pc_rtx;
13521 REG_NOTES (tem) = NULL;
13523 distribute_notes (old_notes, tem, tem, NULL_RTX,
13524 NULL_RTX, NULL_RTX, NULL_RTX);
13525 distribute_links (LOG_LINKS (tem));
13527 SET_INSN_DELETED (tem);
13528 if (tem == i2)
13529 i2 = NULL_RTX;
13531 #ifdef HAVE_cc0
13532 /* Delete the setter too. */
13533 if (cc0_setter)
13535 PATTERN (cc0_setter) = pc_rtx;
13536 old_notes = REG_NOTES (cc0_setter);
13537 REG_NOTES (cc0_setter) = NULL;
13539 distribute_notes (old_notes, cc0_setter,
13540 cc0_setter, NULL_RTX,
13541 NULL_RTX, NULL_RTX, NULL_RTX);
13542 distribute_links (LOG_LINKS (cc0_setter));
13544 SET_INSN_DELETED (cc0_setter);
13545 if (cc0_setter == i2)
13546 i2 = NULL_RTX;
13548 #endif
13550 else
13552 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13554 /* If there isn't already a REG_UNUSED note, put one
13555 here. Do not place a REG_DEAD note, even if
13556 the register is also used here; that would not
13557 match the algorithm used in lifetime analysis
13558 and can cause the consistency check in the
13559 scheduler to fail. */
13560 if (! find_regno_note (tem, REG_UNUSED,
13561 REGNO (XEXP (note, 0))))
13562 place = tem;
13563 break;
13566 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13567 || (CALL_P (tem)
13568 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13570 place = tem;
13572 /* If we are doing a 3->2 combination, and we have a
13573 register which formerly died in i3 and was not used
13574 by i2, which now no longer dies in i3 and is used in
13575 i2 but does not die in i2, and place is between i2
13576 and i3, then we may need to move a link from place to
13577 i2. */
13578 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13579 && from_insn
13580 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13581 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13583 struct insn_link *links = LOG_LINKS (place);
13584 LOG_LINKS (place) = NULL;
13585 distribute_links (links);
13587 break;
13590 if (tem == BB_HEAD (bb))
13591 break;
13596 /* If the register is set or already dead at PLACE, we needn't do
13597 anything with this note if it is still a REG_DEAD note.
13598 We check here if it is set at all, not if is it totally replaced,
13599 which is what `dead_or_set_p' checks, so also check for it being
13600 set partially. */
13602 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13604 unsigned int regno = REGNO (XEXP (note, 0));
13605 reg_stat_type *rsp = &reg_stat[regno];
13607 if (dead_or_set_p (place, XEXP (note, 0))
13608 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13610 /* Unless the register previously died in PLACE, clear
13611 last_death. [I no longer understand why this is
13612 being done.] */
13613 if (rsp->last_death != place)
13614 rsp->last_death = 0;
13615 place = 0;
13617 else
13618 rsp->last_death = place;
13620 /* If this is a death note for a hard reg that is occupying
13621 multiple registers, ensure that we are still using all
13622 parts of the object. If we find a piece of the object
13623 that is unused, we must arrange for an appropriate REG_DEAD
13624 note to be added for it. However, we can't just emit a USE
13625 and tag the note to it, since the register might actually
13626 be dead; so we recourse, and the recursive call then finds
13627 the previous insn that used this register. */
13629 if (place && regno < FIRST_PSEUDO_REGISTER
13630 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13632 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13633 bool all_used = true;
13634 unsigned int i;
13636 for (i = regno; i < endregno; i++)
13637 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13638 && ! find_regno_fusage (place, USE, i))
13639 || dead_or_set_regno_p (place, i))
13641 all_used = false;
13642 break;
13645 if (! all_used)
13647 /* Put only REG_DEAD notes for pieces that are
13648 not already dead or set. */
13650 for (i = regno; i < endregno;
13651 i += hard_regno_nregs[i][reg_raw_mode[i]])
13653 rtx piece = regno_reg_rtx[i];
13654 basic_block bb = this_basic_block;
13656 if (! dead_or_set_p (place, piece)
13657 && ! reg_bitfield_target_p (piece,
13658 PATTERN (place)))
13660 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13661 NULL_RTX);
13663 distribute_notes (new_note, place, place,
13664 NULL_RTX, NULL_RTX, NULL_RTX,
13665 NULL_RTX);
13667 else if (! refers_to_regno_p (i, i + 1,
13668 PATTERN (place), 0)
13669 && ! find_regno_fusage (place, USE, i))
13670 for (tem = PREV_INSN (place); ;
13671 tem = PREV_INSN (tem))
13673 if (!NONDEBUG_INSN_P (tem))
13675 if (tem == BB_HEAD (bb))
13676 break;
13677 continue;
13679 if (dead_or_set_p (tem, piece)
13680 || reg_bitfield_target_p (piece,
13681 PATTERN (tem)))
13683 add_reg_note (tem, REG_UNUSED, piece);
13684 break;
13689 place = 0;
13693 break;
13695 default:
13696 /* Any other notes should not be present at this point in the
13697 compilation. */
13698 gcc_unreachable ();
13701 if (place)
13703 XEXP (note, 1) = REG_NOTES (place);
13704 REG_NOTES (place) = note;
13707 if (place2)
13708 add_shallow_copy_of_reg_note (place2, note);
13712 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13713 I3, I2, and I1 to new locations. This is also called to add a link
13714 pointing at I3 when I3's destination is changed. */
13716 static void
13717 distribute_links (struct insn_link *links)
13719 struct insn_link *link, *next_link;
13721 for (link = links; link; link = next_link)
13723 rtx place = 0;
13724 rtx insn;
13725 rtx set, reg;
13727 next_link = link->next;
13729 /* If the insn that this link points to is a NOTE or isn't a single
13730 set, ignore it. In the latter case, it isn't clear what we
13731 can do other than ignore the link, since we can't tell which
13732 register it was for. Such links wouldn't be used by combine
13733 anyway.
13735 It is not possible for the destination of the target of the link to
13736 have been changed by combine. The only potential of this is if we
13737 replace I3, I2, and I1 by I3 and I2. But in that case the
13738 destination of I2 also remains unchanged. */
13740 if (NOTE_P (link->insn)
13741 || (set = single_set (link->insn)) == 0)
13742 continue;
13744 reg = SET_DEST (set);
13745 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13746 || GET_CODE (reg) == STRICT_LOW_PART)
13747 reg = XEXP (reg, 0);
13749 /* A LOG_LINK is defined as being placed on the first insn that uses
13750 a register and points to the insn that sets the register. Start
13751 searching at the next insn after the target of the link and stop
13752 when we reach a set of the register or the end of the basic block.
13754 Note that this correctly handles the link that used to point from
13755 I3 to I2. Also note that not much searching is typically done here
13756 since most links don't point very far away. */
13758 for (insn = NEXT_INSN (link->insn);
13759 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
13760 || BB_HEAD (this_basic_block->next_bb) != insn));
13761 insn = NEXT_INSN (insn))
13762 if (DEBUG_INSN_P (insn))
13763 continue;
13764 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13766 if (reg_referenced_p (reg, PATTERN (insn)))
13767 place = insn;
13768 break;
13770 else if (CALL_P (insn)
13771 && find_reg_fusage (insn, USE, reg))
13773 place = insn;
13774 break;
13776 else if (INSN_P (insn) && reg_set_p (reg, insn))
13777 break;
13779 /* If we found a place to put the link, place it there unless there
13780 is already a link to the same insn as LINK at that point. */
13782 if (place)
13784 struct insn_link *link2;
13786 FOR_EACH_LOG_LINK (link2, place)
13787 if (link2->insn == link->insn)
13788 break;
13790 if (link2 == NULL)
13792 link->next = LOG_LINKS (place);
13793 LOG_LINKS (place) = link;
13795 /* Set added_links_insn to the earliest insn we added a
13796 link to. */
13797 if (added_links_insn == 0
13798 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13799 added_links_insn = place;
13805 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13806 Check whether the expression pointer to by LOC is a register or
13807 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13808 Otherwise return zero. */
13810 static int
13811 unmentioned_reg_p_1 (rtx *loc, void *expr)
13813 rtx x = *loc;
13815 if (x != NULL_RTX
13816 && (REG_P (x) || MEM_P (x))
13817 && ! reg_mentioned_p (x, (rtx) expr))
13818 return 1;
13819 return 0;
13822 /* Check for any register or memory mentioned in EQUIV that is not
13823 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13824 of EXPR where some registers may have been replaced by constants. */
13826 static bool
13827 unmentioned_reg_p (rtx equiv, rtx expr)
13829 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13832 DEBUG_FUNCTION void
13833 dump_combine_stats (FILE *file)
13835 fprintf
13836 (file,
13837 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13838 combine_attempts, combine_merges, combine_extras, combine_successes);
13841 void
13842 dump_combine_total_stats (FILE *file)
13844 fprintf
13845 (file,
13846 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13847 total_attempts, total_merges, total_extras, total_successes);
13850 static bool
13851 gate_handle_combine (void)
13853 return (optimize > 0);
13856 /* Try combining insns through substitution. */
13857 static unsigned int
13858 rest_of_handle_combine (void)
13860 int rebuild_jump_labels_after_combine;
13862 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13863 df_note_add_problem ();
13864 df_analyze ();
13866 regstat_init_n_sets_and_refs ();
13868 rebuild_jump_labels_after_combine
13869 = combine_instructions (get_insns (), max_reg_num ());
13871 /* Combining insns may have turned an indirect jump into a
13872 direct jump. Rebuild the JUMP_LABEL fields of jumping
13873 instructions. */
13874 if (rebuild_jump_labels_after_combine)
13876 timevar_push (TV_JUMP);
13877 rebuild_jump_labels (get_insns ());
13878 cleanup_cfg (0);
13879 timevar_pop (TV_JUMP);
13882 regstat_free_n_sets_and_refs ();
13883 return 0;
13886 namespace {
13888 const pass_data pass_data_combine =
13890 RTL_PASS, /* type */
13891 "combine", /* name */
13892 OPTGROUP_NONE, /* optinfo_flags */
13893 true, /* has_gate */
13894 true, /* has_execute */
13895 TV_COMBINE, /* tv_id */
13896 PROP_cfglayout, /* properties_required */
13897 0, /* properties_provided */
13898 0, /* properties_destroyed */
13899 0, /* todo_flags_start */
13900 ( TODO_df_finish | TODO_verify_rtl_sharing ), /* todo_flags_finish */
13903 class pass_combine : public rtl_opt_pass
13905 public:
13906 pass_combine (gcc::context *ctxt)
13907 : rtl_opt_pass (pass_data_combine, ctxt)
13910 /* opt_pass methods: */
13911 bool gate () { return gate_handle_combine (); }
13912 unsigned int execute () { return rest_of_handle_combine (); }
13914 }; // class pass_combine
13916 } // anon namespace
13918 rtl_opt_pass *
13919 make_pass_combine (gcc::context *ctxt)
13921 return new pass_combine (ctxt);