1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999-2018 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com) and
5 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 3, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
24 ;; See constraints.md for a description of constraints specific to s390.
27 ;; Special formats used for outputting 390 instructions.
29 ;; %C: print opcode suffix for branch condition.
30 ;; %D: print opcode suffix for inverse branch condition.
31 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
32 ;; %G: print the size of the operand in bytes.
33 ;; %O: print only the displacement of a memory reference.
34 ;; %R: print only the base register of a memory reference.
35 ;; %S: print S-type memory reference (base+displacement).
36 ;; %N: print the second word of a DImode operand.
37 ;; %M: print the second word of a TImode operand.
38 ;; %Y: print shift count operand.
40 ;; %b: print integer X as if it's an unsigned byte.
41 ;; %c: print integer X as if it's an signed byte.
42 ;; %x: print integer X as if it's an unsigned halfword.
43 ;; %h: print integer X as if it's a signed halfword.
44 ;; %i: print the first nonzero HImode part of X.
45 ;; %j: print the first HImode part unequal to -1 of X.
46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
48 ;; %o: print integer X as if it's an unsigned 32bit word.
50 ;; We have a special constraint for pattern matching.
52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
59 (define_c_enum "unspec" [
65 ; Convert CC into a str comparison result and copy it into an
67 ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
68 UNSPEC_STRCMPCC_TO_INT
70 ; Copy CC as is into the lower 2 bits of an integer register
73 ; The right hand side of an setmem
76 ; GOT/PLT and lt-relative accesses
97 ; TLS relocation specifiers
113 ; Stack Smashing Protector
117 ; Split stack support
120 ; Test Data Class (TDC)
132 UNSPEC_FPINT_NEARBYINT
141 UNSPEC_VEC_SMULT_EVEN
142 UNSPEC_VEC_UMULT_EVEN
156 UNSPEC_VEC_INSERT_AND_ZERO
157 UNSPEC_VEC_LOAD_BNDRY
159 UNSPEC_VEC_LOAD_LEN_R
163 UNSPEC_VEC_PACK_SATURATE
164 UNSPEC_VEC_PACK_SATURATE_CC
165 UNSPEC_VEC_PACK_SATURATE_GENCC
166 UNSPEC_VEC_PACK_UNSIGNED_SATURATE
167 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC
168 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC
173 UNSPEC_VEC_STORE_LEN_R
181 UNSPEC_VEC_ADDEC_U128
186 UNSPEC_VEC_GFMSUM_128
187 UNSPEC_VEC_GFMSUM_ACCUM
188 UNSPEC_VEC_GFMSUM_ACCUM_128
205 UNSPEC_VEC_SUBEC_U128
231 UNSPEC_VEC_VFLL ; vector fp load lengthened
232 UNSPEC_VEC_VFLR ; vector fp load rounded
244 ;; UNSPEC_VOLATILE usage
247 (define_c_enum "unspecv" [
269 ; Non-branch nops used for compare-and-branch adjustments on z10
273 ; Hotpatching (unremovable NOPs)
278 ; Transactional Execution support
288 ; Set and get floating point control register
292 ; Split stack support
293 UNSPECV_SPLIT_STACK_CALL
294 UNSPECV_SPLIT_STACK_DATA
303 ; Registers with special meaning
307 ; Sibling call register.
309 ; A call-clobbered reg which can be used in indirect branch thunks
310 (INDIRECT_BRANCH_THUNK_REGNUM 1)
311 ; Literal pool base register.
313 ; Return address register.
315 ; Stack pointer register.
317 ; Condition code register.
319 ; Thread local storage pointer register.
323 ; Hardware register names
327 ; General purpose registers
332 ; Floating point registers.
356 ; Rounding modes for binary floating point numbers
359 (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1)
360 (BFP_RND_PREP_FOR_SHORT_PREC 3)
361 (BFP_RND_NEAREST_TIE_TO_EVEN 4)
363 (BFP_RND_TOWARD_INF 6)
364 (BFP_RND_TOWARD_MINF 7)])
366 ; Rounding modes for decimal floating point numbers
367 ; 1-7 were introduced with the floating point extension facility
368 ; available with z196
369 ; With these rounding modes (1-7) a quantum exception might occur
370 ; which is suppressed for the other modes.
373 (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1)
374 (DFP_RND_CURRENT_QUANTEXC 2)
375 (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC 3)
376 (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC 4)
377 (DFP_RND_TOWARD_0_QUANTEXC 5)
378 (DFP_RND_TOWARD_INF_QUANTEXC 6)
379 (DFP_RND_TOWARD_MINF_QUANTEXC 7)
380 (DFP_RND_NEAREST_TIE_TO_EVEN 8)
382 (DFP_RND_TOWARD_INF 10)
383 (DFP_RND_TOWARD_MINF 11)
384 (DFP_RND_NEAREST_TIE_AWAY_FROM_0 12)
385 (DFP_RND_NEAREST_TIE_TO_0 13)
386 (DFP_RND_AWAY_FROM_0 14)
387 (DFP_RND_PREP_FOR_SHORT_PREC 15)])
390 ;; PFPO GPR0 argument format
395 ; PFPO operation type
396 (PFPO_CONVERT 0x1000000)
398 (PFPO_OP_TYPE_SF 0x5)
399 (PFPO_OP_TYPE_DF 0x6)
400 (PFPO_OP_TYPE_TF 0x7)
401 (PFPO_OP_TYPE_SD 0x8)
402 (PFPO_OP_TYPE_DD 0x9)
403 (PFPO_OP_TYPE_TD 0xa)
404 ; Bitposition of operand types
405 (PFPO_OP0_TYPE_SHIFT 16)
406 (PFPO_OP1_TYPE_SHIFT 8)
407 ; Decide whether current DFP or BFD rounding mode should be used
408 ; for the conversion.
409 (PFPO_RND_MODE_DFP 0)
410 (PFPO_RND_MODE_BFP 1)
415 ; Immediate values which can be used as the third operand to the
416 ; perform processor assist instruction
420 (PPA_OOO_BARRIER 15)])
422 ; Immediate operands for tbegin and tbeginc
423 (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c
424 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
426 ;; Instruction operand type as used in the Principles of Operation.
427 ;; Used to determine defaults for length and other attribute values.
429 (define_attr "op_type"
430 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX,VSI"
433 ;; Instruction type attribute used for scheduling.
435 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
436 cs,vs,store,sem,idiv,
437 imulhi,imulsi,imuldi,
438 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
439 floadtf,floaddf,floadsf,fstoredf,fstoresf,
440 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
441 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
443 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
444 itoftf, itofdf, itofsf, itofdd, itoftd,
445 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
446 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
448 (cond [(eq_attr "op_type" "NN") (const_string "other")
449 (eq_attr "op_type" "SS") (const_string "cs")]
450 (const_string "integer")))
452 ;; Another attribute used for scheduling purposes:
453 ;; agen: Instruction uses the address generation unit
454 ;; reg: Instruction does not use the agen unit
456 (define_attr "atype" "agen,reg"
457 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF")
459 (const_string "agen")))
461 ;; Properties concerning Z10 execution grouping and value forwarding.
462 ;; z10_super: instruction is superscalar.
463 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
464 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
465 ;; target register. It can forward this value to a second instruction that reads
466 ;; the same register if that second instruction is issued in the same group.
467 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
468 ;; instruction in the S pipe writes to the register, then the T instruction
469 ;; can immediately read the new value.
470 ;; z10_fr: union of Z10_fwd and z10_rec.
471 ;; z10_c: second operand of instruction is a register and read with complemented bits.
473 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
476 (define_attr "z10prop" "none,
477 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
478 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
480 z10_fr, z10_fr_A3, z10_fr_E1,
482 (const_string "none"))
484 ;; Properties concerning Z196 decoding
485 ;; z196_alone: must group alone
486 ;; z196_end: ends a group
487 ;; z196_cracked: instruction is cracked or expanded
488 (define_attr "z196prop" "none,
489 z196_alone, z196_ends,
491 (const_string "none"))
493 ; mnemonics which only get defined through if_then_else currently
494 ; don't get added to the list values automatically and hence need to
496 (define_attr "mnemonic" "b,bas,basr,bc,bcr_flush,unknown" (const_string "unknown"))
500 (define_attr "length" ""
501 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
502 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)]
506 ;; Processor type. This attribute must exactly match the processor_type
507 ;; enumeration in s390.h.
509 (define_attr "cpu" "z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13,z14"
510 (const (symbol_ref "s390_tune_attr")))
512 (define_attr "cpu_facility"
513 "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13,z14,vxe"
514 (const_string "standard"))
516 (define_attr "enabled" ""
517 (cond [(eq_attr "cpu_facility" "standard")
520 (and (eq_attr "cpu_facility" "ieee")
521 (match_test "TARGET_CPU_IEEE_FLOAT"))
524 (and (eq_attr "cpu_facility" "zarch")
525 (match_test "TARGET_ZARCH"))
528 (and (eq_attr "cpu_facility" "longdisp")
529 (match_test "TARGET_LONG_DISPLACEMENT"))
532 (and (eq_attr "cpu_facility" "extimm")
533 (match_test "TARGET_EXTIMM"))
536 (and (eq_attr "cpu_facility" "dfp")
537 (match_test "TARGET_DFP"))
540 (eq_attr "cpu_facility" "cpu_zarch")
543 (and (eq_attr "cpu_facility" "z10")
544 (match_test "TARGET_Z10"))
547 (and (eq_attr "cpu_facility" "z196")
548 (match_test "TARGET_Z196"))
551 (and (eq_attr "cpu_facility" "zEC12")
552 (match_test "TARGET_ZEC12"))
555 (and (eq_attr "cpu_facility" "vx")
556 (match_test "TARGET_VX"))
559 (and (eq_attr "cpu_facility" "z13")
560 (match_test "TARGET_Z13"))
563 (and (eq_attr "cpu_facility" "z14")
564 (match_test "TARGET_Z14"))
567 (and (eq_attr "cpu_facility" "vxe")
568 (match_test "TARGET_VXE"))
573 ;; Pipeline description for z900.
576 ;; Pipeline description for z990, z9-109 and z9-ec.
579 ;; Pipeline description for z10
582 ;; Pipeline description for z196
585 ;; Pipeline description for zEC12
588 ;; Pipeline description for z13
592 (include "predicates.md")
594 ;; Constraint definitions
595 (include "constraints.md")
602 (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF])
604 ;; These mode iterators allow floating point patterns to be generated from the
606 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
607 (SD "TARGET_HARD_DFP")])
608 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
609 (define_mode_iterator BFP [TF DF SF])
610 (define_mode_iterator DFP [TD DD])
611 (define_mode_iterator DFP_ALL [TD DD SD])
612 (define_mode_iterator DSF [DF SF])
613 (define_mode_iterator SD_SF [SF SD])
614 (define_mode_iterator DD_DF [DF DD])
615 (define_mode_iterator TD_TF [TF TD])
617 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
618 ;; from the same template.
619 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
620 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
621 (define_mode_iterator DSI [DI SI])
622 (define_mode_iterator TDI [TI DI])
624 ;; These mode iterators allow :P to be used for patterns that operate on
625 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
626 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
628 ;; These macros refer to the actual word_mode of the configuration.
629 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
630 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
631 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
633 ;; Used by the umul pattern to express modes having half the size.
634 (define_mode_attr DWH [(TI "DI") (DI "SI")])
635 (define_mode_attr dwh [(TI "di") (DI "si")])
637 ;; This mode iterator allows the QI and HI patterns to be defined from
638 ;; the same template.
639 (define_mode_iterator HQI [HI QI])
641 ;; This mode iterator allows the integer patterns to be defined from the
643 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
644 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
645 (define_mode_iterator SINT [SI HI QI])
647 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
648 ;; the same template.
649 (define_code_iterator SHIFT [ashift lshiftrt])
651 ;; This iterator allows r[ox]sbg to be defined with the same template
652 (define_code_iterator IXOR [ior xor])
654 ;; This iterator is used to expand the patterns for the nearest
655 ;; integer functions.
656 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
657 UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL
658 UNSPEC_FPINT_NEARBYINT])
659 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor")
660 (UNSPEC_FPINT_BTRUNC "btrunc")
661 (UNSPEC_FPINT_ROUND "round")
662 (UNSPEC_FPINT_CEIL "ceil")
663 (UNSPEC_FPINT_NEARBYINT "nearbyint")])
664 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7")
665 (UNSPEC_FPINT_BTRUNC "5")
666 (UNSPEC_FPINT_ROUND "1")
667 (UNSPEC_FPINT_CEIL "6")
668 (UNSPEC_FPINT_NEARBYINT "0")])
670 ;; This iterator and attribute allow to combine most atomic operations.
671 (define_code_iterator ATOMIC [and ior xor plus minus mult])
672 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
673 (define_code_attr atomic [(and "and") (ior "or") (xor "xor")
674 (plus "add") (minus "sub") (mult "nand")])
675 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
677 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
678 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
679 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
681 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
682 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
684 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
686 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
687 ;; Likewise for "<RXe>".
688 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
689 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
691 ;; The decimal floating point variants of add, sub, div and mul support 3
692 ;; fp register operands. The following attributes allow to merge the bfp and
693 ;; dfp variants in a single insn definition.
695 ;; These mode attributes are supposed to be used in the `enabled' insn
696 ;; attribute to disable certain alternatives for certain modes.
697 (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")])
698 (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")])
699 (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")])
700 (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0")
701 (TD "0") (DD "0") (DD "0")
702 (TI "0") (DI "*") (SI "0")])
703 (define_mode_attr DF [(TF "0") (DF "*") (SF "0")
704 (TD "0") (DD "0") (DD "0")
705 (TI "0") (DI "0") (SI "0")])
706 (define_mode_attr SF [(TF "0") (DF "0") (SF "*")
707 (TD "0") (DD "0") (DD "0")
708 (TI "0") (DI "0") (SI "0")])
710 ;; This attribute is used in the operand constraint list
711 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
712 ;; TFmode values are represented by a fp register pair. Since the
713 ;; sign bit instructions only handle single source and target fp registers
714 ;; these instructions can only be used for TFmode values if the source and
715 ;; target operand uses the same fp register.
716 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
718 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
719 ;; within instruction mnemonics.
720 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
722 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
723 ;; modes and to an empty string for bfp modes.
724 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
726 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
727 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
728 ;; version only operates on one register.
729 (define_mode_attr d0 [(DI "d") (SI "0")])
731 ;; In combination with d0 this allows to combine instructions of which the 31bit
732 ;; version only operates on one register. The DImode version needs an additional
733 ;; register for the assembler output.
734 (define_mode_attr 1 [(DI "%1,") (SI "")])
736 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
737 ;; 'ashift' and "srdl" in 'lshiftrt'.
738 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
740 ;; In SHIFT templates, this attribute holds the correct standard name for the
741 ;; pattern itself and the corresponding function calls.
742 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
744 ;; This attribute handles differences in the instruction 'type' and will result
745 ;; in "RRE" for DImode and "RR" for SImode.
746 (define_mode_attr E [(DI "E") (SI "")])
748 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
749 ;; to result in "RXY" for DImode and "RX" for SImode.
750 (define_mode_attr Y [(DI "Y") (SI "")])
752 ;; This attribute handles differences in the instruction 'type' and will result
753 ;; in "RSE" for TImode and "RS" for DImode.
754 (define_mode_attr TE [(TI "E") (DI "")])
756 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
757 ;; and "lcr" in SImode.
758 (define_mode_attr g [(DI "g") (SI "")])
760 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
761 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
762 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
763 ;; variant for long displacements.
764 (define_mode_attr y [(DI "g") (SI "y")])
766 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
767 ;; and "cds" in DImode.
768 (define_mode_attr tg [(TI "g") (DI "")])
770 ;; In TDI templates, a string like "c<d>sg".
771 (define_mode_attr td [(TI "d") (DI "")])
773 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
774 ;; and "cfdbr" in SImode.
775 (define_mode_attr gf [(DI "g") (SI "f")])
777 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
778 ;; and sllk for SI. This way it is possible to merge the new z196 SI
779 ;; 3 operands shift instructions into the existing patterns.
780 (define_mode_attr gk [(DI "g") (SI "k")])
782 ;; ICM mask required to load MODE value into the lowest subreg
783 ;; of a SImode register.
784 (define_mode_attr icm_lo [(HI "3") (QI "1")])
786 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
787 ;; HImode and "llgc" in QImode.
788 (define_mode_attr hc [(HI "h") (QI "c")])
790 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
792 (define_mode_attr DBL [(DI "TI") (SI "DI")])
794 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
795 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
796 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
798 ;; Maximum unsigned integer that fits in MODE.
799 (define_mode_attr max_uint [(HI "65535") (QI "255")])
801 ;; Start and end field computations for RISBG et al.
802 (define_mode_attr bfstart [(DI "s") (SI "t")])
803 (define_mode_attr bfend [(DI "e") (SI "f")])
805 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
806 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
808 (define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")])
809 (define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")])
811 ;; In place of GET_MODE_SIZE (<MODE>mode)
812 (define_mode_attr modesize [(DI "8") (SI "4")])
814 ;; Allow return and simple_return to be defined from a single template.
815 (define_code_iterator ANY_RETURN [return simple_return])
819 ; Condition code modes generated by vector fp comparisons. These will
820 ; be used also in single element mode.
821 (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE])
822 ; Used with VFCMP to expand part of the mnemonic
823 ; For fp we have a mismatch: eq in the insn name - e in asm
824 (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")])
825 (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVIH "h") (CCVIHU "hl") (CCVFH "h") (CCVFHE "he")])
827 ;; Subst pattern definitions
830 (include "vector.md")
833 ;;- Compare instructions.
836 ; Test-under-Mask instructions
838 (define_insn "*tmqi_mem"
839 [(set (reg CC_REGNUM)
840 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
841 (match_operand:QI 1 "immediate_operand" "n,n"))
842 (match_operand:QI 2 "immediate_operand" "n,n")))]
843 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
847 [(set_attr "op_type" "SI,SIY")
848 (set_attr "cpu_facility" "*,longdisp")
849 (set_attr "z10prop" "z10_super,z10_super")])
851 (define_insn "*tmdi_reg"
852 [(set (reg CC_REGNUM)
853 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
854 (match_operand:DI 1 "immediate_operand"
855 "N0HD0,N1HD0,N2HD0,N3HD0"))
856 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
858 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
859 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
865 [(set_attr "op_type" "RI")
866 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
868 (define_insn "*tmsi_reg"
869 [(set (reg CC_REGNUM)
870 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
871 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
872 (match_operand:SI 2 "immediate_operand" "n,n")))]
873 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
874 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
878 [(set_attr "op_type" "RI")
879 (set_attr "z10prop" "z10_super,z10_super")])
881 (define_insn "*tm<mode>_full"
882 [(set (reg CC_REGNUM)
883 (compare (match_operand:HQI 0 "register_operand" "d")
884 (match_operand:HQI 1 "immediate_operand" "n")))]
885 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
887 [(set_attr "op_type" "RI")
888 (set_attr "z10prop" "z10_super")])
892 ; Load-and-Test instructions
895 ; tst(di|si) instruction pattern(s).
897 (define_insn "*tstdi_sign"
898 [(set (reg CC_REGNUM)
902 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0)
903 (const_int 32)) (const_int 32))
904 (match_operand:DI 1 "const0_operand" "")))
905 (set (match_operand:DI 2 "register_operand" "=d,d")
906 (sign_extend:DI (match_dup 0)))]
907 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
910 [(set_attr "op_type" "RRE,RXY")
911 (set_attr "cpu_facility" "*,z10")
912 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
915 (define_insn "*tst<mode>_extimm"
916 [(set (reg CC_REGNUM)
917 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
918 (match_operand:GPR 1 "const0_operand" "")))
919 (set (match_operand:GPR 2 "register_operand" "=d,d")
921 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
925 [(set_attr "op_type" "RR<E>,RXY")
926 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
928 ; Peephole to combine a load-and-test from volatile memory which combine does
931 [(set (match_operand:GPR 0 "register_operand")
932 (match_operand:GPR 2 "memory_operand"))
934 (compare (match_dup 0) (match_operand:GPR 1 "const0_operand")))]
935 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM
936 && GENERAL_REG_P (operands[0])
937 && satisfies_constraint_T (operands[2])"
939 [(set (reg:CCS CC_REGNUM)
940 (compare:CCS (match_dup 2) (match_dup 1)))
941 (set (match_dup 0) (match_dup 2))])])
944 (define_insn "*tst<mode>_cconly_extimm"
945 [(set (reg CC_REGNUM)
946 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
947 (match_operand:GPR 1 "const0_operand" "")))
948 (clobber (match_scratch:GPR 2 "=X,d"))]
949 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
953 [(set_attr "op_type" "RR<E>,RXY")
954 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
956 (define_insn "*tstdi"
957 [(set (reg CC_REGNUM)
958 (compare (match_operand:DI 0 "register_operand" "d")
959 (match_operand:DI 1 "const0_operand" "")))
960 (set (match_operand:DI 2 "register_operand" "=d")
962 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
964 [(set_attr "op_type" "RRE")
965 (set_attr "z10prop" "z10_fr_E1")])
967 (define_insn "*tstsi"
968 [(set (reg CC_REGNUM)
969 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
970 (match_operand:SI 1 "const0_operand" "")))
971 (set (match_operand:SI 2 "register_operand" "=d,d,d")
973 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
978 [(set_attr "op_type" "RR,RS,RSY")
979 (set_attr "cpu_facility" "*,*,longdisp")
980 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
982 (define_insn "*tstsi_cconly"
983 [(set (reg CC_REGNUM)
984 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
985 (match_operand:SI 1 "const0_operand" "")))
986 (clobber (match_scratch:SI 2 "=X,d,d"))]
987 "s390_match_ccmode(insn, CCSmode)"
992 [(set_attr "op_type" "RR,RS,RSY")
993 (set_attr "cpu_facility" "*,*,longdisp")
994 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
996 (define_insn "*tstdi_cconly_31"
997 [(set (reg CC_REGNUM)
998 (compare (match_operand:DI 0 "register_operand" "d")
999 (match_operand:DI 1 "const0_operand" "")))]
1000 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
1002 [(set_attr "op_type" "RS")
1003 (set_attr "atype" "reg")])
1006 (define_insn "*tst<mode>_cconly2"
1007 [(set (reg CC_REGNUM)
1008 (compare (match_operand:GPR 0 "register_operand" "d")
1009 (match_operand:GPR 1 "const0_operand" "")))]
1010 "s390_match_ccmode(insn, CCSmode)"
1012 [(set_attr "op_type" "RR<E>")
1013 (set_attr "z10prop" "z10_fr_E1")])
1015 ; tst(hi|qi) instruction pattern(s).
1017 (define_insn "*tst<mode>CCT"
1018 [(set (reg CC_REGNUM)
1019 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
1020 (match_operand:HQI 1 "const0_operand" "")))
1021 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
1023 "s390_match_ccmode(insn, CCTmode)"
1025 icm\t%2,<icm_lo>,%S0
1026 icmy\t%2,<icm_lo>,%S0
1028 [(set_attr "op_type" "RS,RSY,RI")
1029 (set_attr "cpu_facility" "*,longdisp,*")
1030 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
1032 (define_insn "*tsthiCCT_cconly"
1033 [(set (reg CC_REGNUM)
1034 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
1035 (match_operand:HI 1 "const0_operand" "")))
1036 (clobber (match_scratch:HI 2 "=d,d,X"))]
1037 "s390_match_ccmode(insn, CCTmode)"
1042 [(set_attr "op_type" "RS,RSY,RI")
1043 (set_attr "cpu_facility" "*,longdisp,*")
1044 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
1046 (define_insn "*tstqiCCT_cconly"
1047 [(set (reg CC_REGNUM)
1048 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
1049 (match_operand:QI 1 "const0_operand" "")))]
1050 "s390_match_ccmode(insn, CCTmode)"
1055 [(set_attr "op_type" "SI,SIY,RI")
1056 (set_attr "cpu_facility" "*,longdisp,*")
1057 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
1059 (define_insn "*tst<mode>"
1060 [(set (reg CC_REGNUM)
1061 (compare (match_operand:HQI 0 "s_operand" "Q,S")
1062 (match_operand:HQI 1 "const0_operand" "")))
1063 (set (match_operand:HQI 2 "register_operand" "=d,d")
1065 "s390_match_ccmode(insn, CCSmode)"
1067 icm\t%2,<icm_lo>,%S0
1068 icmy\t%2,<icm_lo>,%S0"
1069 [(set_attr "op_type" "RS,RSY")
1070 (set_attr "cpu_facility" "*,longdisp")
1071 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1073 (define_insn "*tst<mode>_cconly"
1074 [(set (reg CC_REGNUM)
1075 (compare (match_operand:HQI 0 "s_operand" "Q,S")
1076 (match_operand:HQI 1 "const0_operand" "")))
1077 (clobber (match_scratch:HQI 2 "=d,d"))]
1078 "s390_match_ccmode(insn, CCSmode)"
1080 icm\t%2,<icm_lo>,%S0
1081 icmy\t%2,<icm_lo>,%S0"
1082 [(set_attr "op_type" "RS,RSY")
1083 (set_attr "cpu_facility" "*,longdisp")
1084 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1087 ; Compare (equality) instructions
1089 (define_insn "*cmpdi_cct"
1090 [(set (reg CC_REGNUM)
1091 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
1092 (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))]
1093 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
1100 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
1101 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
1103 (define_insn "*cmpsi_cct"
1104 [(set (reg CC_REGNUM)
1105 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
1106 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
1107 "s390_match_ccmode (insn, CCTmode)"
1115 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
1116 (set_attr "cpu_facility" "*,*,*,*,longdisp,*")
1117 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
1119 ; Compare (signed) instructions
1121 (define_insn "*cmpdi_ccs_sign"
1122 [(set (reg CC_REGNUM)
1123 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1125 (match_operand:DI 0 "register_operand" "d, d,d")))]
1126 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
1131 [(set_attr "op_type" "RRE,RXY,RIL")
1132 (set_attr "z10prop" "z10_c,*,*")
1133 (set_attr "type" "*,*,larl")])
1137 (define_insn "*cmpsi_ccs_sign"
1138 [(set (reg CC_REGNUM)
1139 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
1140 (match_operand:SI 0 "register_operand" "d,d,d")))]
1141 "s390_match_ccmode(insn, CCSRmode)"
1146 [(set_attr "op_type" "RX,RXY,RIL")
1147 (set_attr "cpu_facility" "*,longdisp,z10")
1148 (set_attr "type" "*,*,larl")
1149 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
1151 (define_insn "*cmphi_ccs_z10"
1152 [(set (reg CC_REGNUM)
1153 (compare (match_operand:HI 0 "s_operand" "Q")
1154 (match_operand:HI 1 "immediate_operand" "K")))]
1155 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
1157 [(set_attr "op_type" "SIL")
1158 (set_attr "z196prop" "z196_cracked")])
1160 (define_insn "*cmpdi_ccs_signhi_rl"
1161 [(set (reg CC_REGNUM)
1162 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b"))
1163 (match_operand:GPR 0 "register_operand" "d,d")))]
1164 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
1168 [(set_attr "op_type" "RXY,RIL")
1169 (set_attr "type" "*,larl")])
1171 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
1172 (define_insn "*cmp<mode>_ccs"
1173 [(set (reg CC_REGNUM)
1174 (compare (match_operand:GPR 0 "nonimmediate_operand"
1176 (match_operand:GPR 1 "general_operand"
1177 "d,K,K,Os,R,T,b")))]
1178 "s390_match_ccmode(insn, CCSmode)"
1187 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
1188 (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10")
1189 (set_attr "type" "*,*,*,*,*,*,larl")
1190 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
1193 ; Compare (unsigned) instructions
1195 (define_insn "*cmpsi_ccu_zerohi_rlsi"
1196 [(set (reg CC_REGNUM)
1197 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
1198 "larl_operand" "X")))
1199 (match_operand:SI 0 "register_operand" "d")))]
1200 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1202 [(set_attr "op_type" "RIL")
1203 (set_attr "type" "larl")
1204 (set_attr "z10prop" "z10_super")])
1207 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
1208 [(set (reg CC_REGNUM)
1209 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
1210 "larl_operand" "X")))
1211 (match_operand:GPR 0 "register_operand" "d")))]
1212 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1214 [(set_attr "op_type" "RIL")
1215 (set_attr "type" "larl")
1216 (set_attr "z10prop" "z10_super")])
1218 (define_insn "*cmpdi_ccu_zero"
1219 [(set (reg CC_REGNUM)
1220 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1222 (match_operand:DI 0 "register_operand" "d,d,d")))]
1223 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
1228 [(set_attr "op_type" "RRE,RXY,RIL")
1229 (set_attr "cpu_facility" "*,*,z10")
1230 (set_attr "type" "*,*,larl")
1231 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
1233 (define_insn "*cmpdi_ccu"
1234 [(set (reg CC_REGNUM)
1235 (compare (match_operand:DI 0 "nonimmediate_operand"
1237 (match_operand:DI 1 "general_operand"
1238 "d,Op,b,D,T,BQ,Q")))]
1239 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
1248 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
1249 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
1250 (set_attr "type" "*,*,larl,*,*,*,*")
1251 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
1253 (define_insn "*cmpsi_ccu"
1254 [(set (reg CC_REGNUM)
1255 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
1256 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
1257 "s390_match_ccmode (insn, CCUmode)"
1267 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
1268 (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*")
1269 (set_attr "type" "*,*,larl,*,*,*,*,*")
1270 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
1272 (define_insn "*cmphi_ccu"
1273 [(set (reg CC_REGNUM)
1274 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
1275 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
1276 "s390_match_ccmode (insn, CCUmode)
1277 && !register_operand (operands[1], HImode)"
1284 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1285 (set_attr "cpu_facility" "*,longdisp,z10,*,*")
1286 (set_attr "z10prop" "*,*,z10_super,*,*")])
1288 (define_insn "*cmpqi_ccu"
1289 [(set (reg CC_REGNUM)
1290 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1291 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1292 "s390_match_ccmode (insn, CCUmode)
1293 && !register_operand (operands[1], QImode)"
1301 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1302 (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*")
1303 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1306 ; Block compare (CLC) instruction patterns.
1309 [(set (reg CC_REGNUM)
1310 (compare (match_operand:BLK 0 "memory_operand" "Q")
1311 (match_operand:BLK 1 "memory_operand" "Q")))
1312 (use (match_operand 2 "const_int_operand" "n"))]
1313 "s390_match_ccmode (insn, CCUmode)
1314 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1315 "clc\t%O0(%2,%R0),%S1"
1316 [(set_attr "op_type" "SS")])
1319 [(set (reg CC_REGNUM)
1320 (compare (match_operand 0 "memory_operand" "")
1321 (match_operand 1 "memory_operand" "")))]
1323 && s390_match_ccmode (insn, CCUmode)
1324 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1325 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1327 [(set (match_dup 0) (match_dup 1))
1328 (use (match_dup 2))])]
1330 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1331 operands[0] = adjust_address (operands[0], BLKmode, 0);
1332 operands[1] = adjust_address (operands[1], BLKmode, 0);
1334 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1335 operands[0], operands[1]);
1336 operands[0] = SET_DEST (PATTERN (curr_insn));
1340 ; (TF|DF|SF|TD|DD|SD) instructions
1343 ; load and test instructions turn SNaN into QNaN what is not
1344 ; acceptable if the target will be used afterwards. On the other hand
1345 ; they are quite convenient for implementing comparisons with 0.0. So
1346 ; try to enable them via splitter if the value isn't needed anymore.
1348 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1349 (define_insn "*cmp<mode>_ccs_0"
1350 [(set (reg CC_REGNUM)
1351 (compare (match_operand:FP 0 "register_operand" "f")
1352 (match_operand:FP 1 "const0_operand" "")))
1353 (clobber (match_operand:FP 2 "register_operand" "=0"))]
1354 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1355 "lt<xde><bt>r\t%0,%0"
1356 [(set_attr "op_type" "RRE")
1357 (set_attr "type" "fsimp<mode>")])
1360 [(set (match_operand 0 "cc_reg_operand")
1361 (compare (match_operand:FP 1 "register_operand")
1362 (match_operand:FP 2 "const0_operand")))]
1363 "TARGET_HARD_FLOAT && REG_P (operands[1]) && dead_or_set_p (insn, operands[1])"
1365 [(set (match_dup 0) (match_dup 3))
1366 (clobber (match_dup 1))])]
1368 /* s390_match_ccmode requires the compare to have the same CC mode
1369 as the CC destination register. */
1370 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[0]),
1371 operands[1], operands[2]);
1375 ; VX: TFmode in FPR pairs: use cxbr instead of wfcxb
1376 ; cxtr, cdtr, cxbr, cdbr, cebr, cdb, ceb, wfcsb, wfcdb
1377 (define_insn "*cmp<mode>_ccs"
1378 [(set (reg CC_REGNUM)
1379 (compare (match_operand:FP 0 "register_operand" "f,f,v,v")
1380 (match_operand:FP 1 "general_operand" "f,R,v,v")))]
1381 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1387 [(set_attr "op_type" "RRE,RXE,VRR,VRR")
1388 (set_attr "cpu_facility" "*,*,vx,vxe")
1389 (set_attr "enabled" "*,<DSF>,<DF>,<SF>")])
1391 ; Compare and Branch instructions
1393 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1394 ; The following instructions do a complementary access of their second
1395 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1396 (define_insn "*cmp_and_br_signed_<mode>"
1398 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1399 [(match_operand:GPR 1 "register_operand" "d,d")
1400 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1401 (label_ref (match_operand 3 "" ""))
1403 (clobber (reg:CC CC_REGNUM))]
1404 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1406 if (get_attr_length (insn) == 6)
1407 return which_alternative ?
1408 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1410 return which_alternative ?
1411 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1413 [(set_attr "op_type" "RIE")
1414 (set_attr "type" "branch")
1415 (set_attr "z10prop" "z10_super_c,z10_super")
1416 (set (attr "length")
1417 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1418 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1419 ; 10 byte for cgr/jg
1421 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1422 ; The following instructions do a complementary access of their second
1423 ; operand (z10 only): clrj, clgrj, clr, clgr
1424 (define_insn "*cmp_and_br_unsigned_<mode>"
1426 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1427 [(match_operand:GPR 1 "register_operand" "d,d")
1428 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1429 (label_ref (match_operand 3 "" ""))
1431 (clobber (reg:CC CC_REGNUM))]
1432 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1434 if (get_attr_length (insn) == 6)
1435 return which_alternative ?
1436 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1438 return which_alternative ?
1439 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1441 [(set_attr "op_type" "RIE")
1442 (set_attr "type" "branch")
1443 (set_attr "z10prop" "z10_super_c,z10_super")
1444 (set (attr "length")
1445 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1446 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1447 ; 10 byte for clgr/jg
1449 ; And now the same two patterns as above but with a negated CC mask.
1451 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1452 ; The following instructions do a complementary access of their second
1453 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1454 (define_insn "*icmp_and_br_signed_<mode>"
1456 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1457 [(match_operand:GPR 1 "register_operand" "d,d")
1458 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1460 (label_ref (match_operand 3 "" ""))))
1461 (clobber (reg:CC CC_REGNUM))]
1462 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1464 if (get_attr_length (insn) == 6)
1465 return which_alternative ?
1466 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1468 return which_alternative ?
1469 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1471 [(set_attr "op_type" "RIE")
1472 (set_attr "type" "branch")
1473 (set_attr "z10prop" "z10_super_c,z10_super")
1474 (set (attr "length")
1475 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1476 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1477 ; 10 byte for cgr/jg
1479 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1480 ; The following instructions do a complementary access of their second
1481 ; operand (z10 only): clrj, clgrj, clr, clgr
1482 (define_insn "*icmp_and_br_unsigned_<mode>"
1484 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1485 [(match_operand:GPR 1 "register_operand" "d,d")
1486 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1488 (label_ref (match_operand 3 "" ""))))
1489 (clobber (reg:CC CC_REGNUM))]
1490 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1492 if (get_attr_length (insn) == 6)
1493 return which_alternative ?
1494 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1496 return which_alternative ?
1497 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1499 [(set_attr "op_type" "RIE")
1500 (set_attr "type" "branch")
1501 (set_attr "z10prop" "z10_super_c,z10_super")
1502 (set (attr "length")
1503 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1504 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1505 ; 10 byte for clgr/jg
1508 ;;- Move instructions.
1512 ; movti instruction pattern(s).
1516 ; Separate out the register pair alternative since constraints (P) are
1517 ; not able to deal with const_wide_int's. But predicates do.
1518 (define_insn "*movti_bigconst"
1519 [(set (match_operand:TI 0 "register_operand" "=d")
1520 (match_operand:TI 1 "reload_const_wide_int_operand" ""))]
1524 ; FIXME: More constants are possible by enabling jxx, jyy constraints
1525 ; for TImode (use double-int for the calculations)
1526 (define_insn "movti"
1527 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v,v,d,v,R,d, d, d, d, d,o")
1528 (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,d,v,R,v,K,NxHD0,Os,NxSD0,dT,d"))]
1546 [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*,*,*,*,*")
1547 (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*,*,*,*,*")
1548 (set_attr "cpu_facility" "*,*,vx,vx,vx,vx,vx,vx,vx,*,*,*,extimm,*,*")])
1551 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1552 (match_operand:TI 1 "general_operand" ""))]
1553 "TARGET_ZARCH && reload_completed
1554 && !s_operand (operands[0], TImode)
1555 && !s_operand (operands[1], TImode)
1556 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1557 [(set (match_dup 2) (match_dup 4))
1558 (set (match_dup 3) (match_dup 5))]
1560 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1561 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1562 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1563 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1567 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1568 (match_operand:TI 1 "general_operand" ""))]
1569 "TARGET_ZARCH && reload_completed
1570 && !s_operand (operands[0], TImode)
1571 && !s_operand (operands[1], TImode)
1572 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1573 [(set (match_dup 2) (match_dup 4))
1574 (set (match_dup 3) (match_dup 5))]
1576 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1577 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1578 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1579 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1582 ; Use part of the TImode target reg to perform the address
1583 ; calculation. If the TImode value is supposed to be copied into a VR
1584 ; this splitter is not necessary.
1586 [(set (match_operand:TI 0 "register_operand" "")
1587 (match_operand:TI 1 "memory_operand" ""))]
1588 "TARGET_ZARCH && reload_completed
1589 && !VECTOR_REG_P (operands[0])
1590 && !s_operand (operands[1], VOIDmode)"
1591 [(set (match_dup 0) (match_dup 1))]
1593 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1594 addr = gen_lowpart (Pmode, addr);
1595 s390_load_address (addr, XEXP (operands[1], 0));
1596 operands[1] = replace_equiv_address (operands[1], addr);
1600 ; Split a VR -> GPR TImode move into 2 vector load GR from VR element.
1601 ; For the higher order bits we do simply a DImode move while the
1602 ; second part is done via vec extract. Both will end up as vlgvg.
1604 [(set (match_operand:TI 0 "register_operand" "")
1605 (match_operand:TI 1 "register_operand" ""))]
1606 "TARGET_VX && reload_completed
1607 && GENERAL_REG_P (operands[0])
1608 && VECTOR_REG_P (operands[1])"
1609 [(set (match_dup 2) (match_dup 4))
1610 (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)]
1611 UNSPEC_VEC_EXTRACT))]
1613 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1614 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1615 operands[4] = gen_rtx_REG (DImode, REGNO (operands[1]));
1616 operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1]));
1620 ; Patterns used for secondary reloads
1623 ; z10 provides move instructions accepting larl memory operands.
1624 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1625 ; These patterns are also used for unaligned SI and DI accesses.
1627 (define_expand "reload<ALL:mode><P:mode>_tomem_z10"
1628 [(parallel [(match_operand:ALL 0 "memory_operand" "")
1629 (match_operand:ALL 1 "register_operand" "=d")
1630 (match_operand:P 2 "register_operand" "=&a")])]
1633 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1637 (define_expand "reload<ALL:mode><P:mode>_toreg_z10"
1638 [(parallel [(match_operand:ALL 0 "register_operand" "=d")
1639 (match_operand:ALL 1 "memory_operand" "")
1640 (match_operand:P 2 "register_operand" "=a")])]
1643 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1647 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1648 [(parallel [(match_operand:P 0 "register_operand" "=d")
1649 (match_operand:P 1 "larl_operand" "")
1650 (match_operand:P 2 "register_operand" "=a")])]
1653 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1657 ; Handles loading a PLUS (load address) expression
1659 (define_expand "reload<mode>_plus"
1660 [(parallel [(match_operand:P 0 "register_operand" "=a")
1661 (match_operand:P 1 "s390_plus_operand" "")
1662 (match_operand:P 2 "register_operand" "=&a")])]
1665 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1669 ; Not all the indirect memory access instructions support the full
1670 ; format (long disp + index + base). So whenever a move from/to such
1671 ; an address is required and the instruction cannot deal with it we do
1672 ; a load address into a scratch register first and use this as the new
1674 ; This in particular is used for:
1675 ; - non-offsetable memory accesses for multiword moves
1676 ; - full vector reg moves with long displacements
1678 (define_expand "reload<mode>_la_in"
1679 [(parallel [(match_operand 0 "register_operand" "")
1680 (match_operand 1 "" "")
1681 (match_operand:P 2 "register_operand" "=&a")])]
1684 gcc_assert (MEM_P (operands[1]));
1685 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1686 operands[1] = replace_equiv_address (operands[1], operands[2]);
1687 emit_move_insn (operands[0], operands[1]);
1691 (define_expand "reload<mode>_la_out"
1692 [(parallel [(match_operand 0 "" "")
1693 (match_operand 1 "register_operand" "")
1694 (match_operand:P 2 "register_operand" "=&a")])]
1697 gcc_assert (MEM_P (operands[0]));
1698 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1699 operands[0] = replace_equiv_address (operands[0], operands[2]);
1700 emit_move_insn (operands[0], operands[1]);
1704 (define_expand "reload<mode>_PIC_addr"
1705 [(parallel [(match_operand 0 "register_operand" "=d")
1706 (match_operand 1 "larl_operand" "")
1707 (match_operand:P 2 "register_operand" "=a")])]
1710 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1711 emit_move_insn (operands[0], new_rtx);
1715 ; movdi instruction pattern(s).
1718 (define_expand "movdi"
1719 [(set (match_operand:DI 0 "general_operand" "")
1720 (match_operand:DI 1 "general_operand" ""))]
1723 /* Handle symbolic constants. */
1725 && (SYMBOLIC_CONST (operands[1])
1726 || (GET_CODE (operands[1]) == PLUS
1727 && XEXP (operands[1], 0) == pic_offset_table_rtx
1728 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1729 emit_symbolic_move (operands);
1732 (define_insn "*movdi_64"
1733 [(set (match_operand:DI 0 "nonimmediate_operand"
1734 "=d, d, d, d, d, d, d, d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R,d")
1735 (match_operand:DI 1 "general_operand"
1736 " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v,ZL"))]
1772 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1773 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,
1775 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1776 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*,
1777 *,*,*,*,*,*,*,larl")
1778 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1779 z10,*,*,*,*,*,longdisp,*,longdisp,
1780 z10,z10,*,*,*,*,vx,vx,vx,vx,vx,vx,*")
1781 (set_attr "z10prop" "z10_fwd_A1,
1811 [(set (match_operand:DI 0 "register_operand" "")
1812 (match_operand:DI 1 "register_operand" ""))]
1813 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1814 [(set (match_dup 2) (match_dup 3))
1815 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1816 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1817 "operands[2] = gen_lowpart (SImode, operands[0]);
1818 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1821 [(set (match_operand:DI 0 "register_operand" "")
1822 (match_operand:DI 1 "register_operand" ""))]
1823 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1824 && dead_or_set_p (insn, operands[1])"
1825 [(set (match_dup 3) (match_dup 2))
1826 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1827 (set (match_dup 4) (match_dup 2))]
1828 "operands[2] = gen_lowpart (SImode, operands[1]);
1829 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1832 [(set (match_operand:DI 0 "register_operand" "")
1833 (match_operand:DI 1 "register_operand" ""))]
1834 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1835 && !dead_or_set_p (insn, operands[1])"
1836 [(set (match_dup 3) (match_dup 2))
1837 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1838 (set (match_dup 4) (match_dup 2))
1839 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1840 "operands[2] = gen_lowpart (SImode, operands[1]);
1841 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1843 (define_insn "*movdi_31"
1844 [(set (match_operand:DI 0 "nonimmediate_operand"
1845 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1846 (match_operand:DI 1 "general_operand"
1847 " Q,S,d,d,dPT,d, *f, R, T,*f,*f,b"))]
1862 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1863 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1864 (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")])
1866 ; For a load from a symbol ref we can use one of the target registers
1867 ; together with larl to load the address.
1869 [(set (match_operand:DI 0 "register_operand" "")
1870 (match_operand:DI 1 "memory_operand" ""))]
1871 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1872 && larl_operand (XEXP (operands[1], 0), SImode)"
1873 [(set (match_dup 2) (match_dup 3))
1874 (set (match_dup 0) (match_dup 1))]
1876 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1877 operands[3] = XEXP (operands[1], 0);
1878 operands[1] = replace_equiv_address (operands[1], operands[2]);
1882 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1883 (match_operand:DI 1 "general_operand" ""))]
1884 "!TARGET_ZARCH && reload_completed
1885 && !s_operand (operands[0], DImode)
1886 && !s_operand (operands[1], DImode)
1887 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1888 [(set (match_dup 2) (match_dup 4))
1889 (set (match_dup 3) (match_dup 5))]
1891 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1892 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1893 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1894 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1898 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1899 (match_operand:DI 1 "general_operand" ""))]
1900 "!TARGET_ZARCH && reload_completed
1901 && !s_operand (operands[0], DImode)
1902 && !s_operand (operands[1], DImode)
1903 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1904 [(set (match_dup 2) (match_dup 4))
1905 (set (match_dup 3) (match_dup 5))]
1907 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1908 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1909 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1910 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1914 [(set (match_operand:DI 0 "register_operand" "")
1915 (match_operand:DI 1 "memory_operand" ""))]
1916 "!TARGET_ZARCH && reload_completed
1917 && !FP_REG_P (operands[0])
1918 && !s_operand (operands[1], VOIDmode)"
1919 [(set (match_dup 0) (match_dup 1))]
1921 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1922 s390_load_address (addr, XEXP (operands[1], 0));
1923 operands[1] = replace_equiv_address (operands[1], addr);
1927 [(set (match_operand:DI 0 "register_operand" "")
1928 (mem:DI (match_operand 1 "address_operand" "")))]
1930 && !FP_REG_P (operands[0])
1931 && GET_CODE (operands[1]) == SYMBOL_REF
1932 && CONSTANT_POOL_ADDRESS_P (operands[1])
1933 && get_pool_mode (operands[1]) == DImode
1934 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1935 [(set (match_dup 0) (match_dup 2))]
1936 "operands[2] = get_pool_constant (operands[1]);")
1938 (define_insn "*la_64"
1939 [(set (match_operand:DI 0 "register_operand" "=d,d")
1940 (match_operand:QI 1 "address_operand" "ZR,ZT"))]
1945 [(set_attr "op_type" "RX,RXY")
1946 (set_attr "type" "la")
1947 (set_attr "cpu_facility" "*,longdisp")
1948 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1952 [(set (match_operand:DI 0 "register_operand" "")
1953 (match_operand:QI 1 "address_operand" ""))
1954 (clobber (reg:CC CC_REGNUM))])]
1956 && preferred_la_operand_p (operands[1], const0_rtx)"
1957 [(set (match_dup 0) (match_dup 1))]
1961 [(set (match_operand:DI 0 "register_operand" "")
1962 (match_operand:DI 1 "register_operand" ""))
1965 (plus:DI (match_dup 0)
1966 (match_operand:DI 2 "nonmemory_operand" "")))
1967 (clobber (reg:CC CC_REGNUM))])]
1969 && !reg_overlap_mentioned_p (operands[0], operands[2])
1970 && preferred_la_operand_p (operands[1], operands[2])"
1971 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1975 ; movsi instruction pattern(s).
1978 (define_expand "movsi"
1979 [(set (match_operand:SI 0 "general_operand" "")
1980 (match_operand:SI 1 "general_operand" ""))]
1983 /* Handle symbolic constants. */
1985 && (SYMBOLIC_CONST (operands[1])
1986 || (GET_CODE (operands[1]) == PLUS
1987 && XEXP (operands[1], 0) == pic_offset_table_rtx
1988 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1989 emit_symbolic_move (operands);
1992 (define_insn "*movsi_larl"
1993 [(set (match_operand:SI 0 "register_operand" "=d")
1994 (match_operand:SI 1 "larl_operand" "X"))]
1996 && !FP_REG_P (operands[0])"
1998 [(set_attr "op_type" "RIL")
1999 (set_attr "type" "larl")
2000 (set_attr "z10prop" "z10_fwd_A1")])
2002 (define_insn "*movsi_zarch"
2003 [(set (match_operand:SI 0 "nonimmediate_operand"
2004 "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R")
2005 (match_operand:SI 1 "general_operand"
2006 " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))]
2039 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
2040 RR,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX")
2041 (set_attr "type" "*,
2065 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
2066 vx,*,vx,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vx,vx,vx,vx,vx,vx")
2067 (set_attr "z10prop" "z10_fwd_A1,
2092 (define_insn "*movsi_esa"
2093 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t")
2094 (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))]
2110 [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS")
2111 (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*")
2112 (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1,
2114 (set_attr "cpu_facility" "*,*,*,*,vx,*,vx,*,*,*,*,*,*")
2118 [(set (match_operand:SI 0 "register_operand" "")
2119 (mem:SI (match_operand 1 "address_operand" "")))]
2120 "!FP_REG_P (operands[0])
2121 && GET_CODE (operands[1]) == SYMBOL_REF
2122 && CONSTANT_POOL_ADDRESS_P (operands[1])
2123 && get_pool_mode (operands[1]) == SImode
2124 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
2125 [(set (match_dup 0) (match_dup 2))]
2126 "operands[2] = get_pool_constant (operands[1]);")
2128 (define_insn "*la_31"
2129 [(set (match_operand:SI 0 "register_operand" "=d,d")
2130 (match_operand:QI 1 "address_operand" "ZR,ZT"))]
2131 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
2135 [(set_attr "op_type" "RX,RXY")
2136 (set_attr "type" "la")
2137 (set_attr "cpu_facility" "*,longdisp")
2138 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2142 [(set (match_operand:SI 0 "register_operand" "")
2143 (match_operand:QI 1 "address_operand" ""))
2144 (clobber (reg:CC CC_REGNUM))])]
2146 && preferred_la_operand_p (operands[1], const0_rtx)"
2147 [(set (match_dup 0) (match_dup 1))]
2151 [(set (match_operand:SI 0 "register_operand" "")
2152 (match_operand:SI 1 "register_operand" ""))
2155 (plus:SI (match_dup 0)
2156 (match_operand:SI 2 "nonmemory_operand" "")))
2157 (clobber (reg:CC CC_REGNUM))])]
2159 && !reg_overlap_mentioned_p (operands[0], operands[2])
2160 && preferred_la_operand_p (operands[1], operands[2])"
2161 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2164 (define_insn "*la_31_and"
2165 [(set (match_operand:SI 0 "register_operand" "=d,d")
2166 (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT")
2167 (const_int 2147483647)))]
2172 [(set_attr "op_type" "RX,RXY")
2173 (set_attr "type" "la")
2174 (set_attr "cpu_facility" "*,longdisp")
2175 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2177 (define_insn_and_split "*la_31_and_cc"
2178 [(set (match_operand:SI 0 "register_operand" "=d")
2179 (and:SI (match_operand:QI 1 "address_operand" "p")
2180 (const_int 2147483647)))
2181 (clobber (reg:CC CC_REGNUM))]
2184 "&& reload_completed"
2186 (and:SI (match_dup 1) (const_int 2147483647)))]
2188 [(set_attr "op_type" "RX")
2189 (set_attr "type" "la")])
2191 (define_insn "force_la_31"
2192 [(set (match_operand:SI 0 "register_operand" "=d,d")
2193 (match_operand:QI 1 "address_operand" "ZR,ZT"))
2194 (use (const_int 0))]
2199 [(set_attr "op_type" "RX")
2200 (set_attr "type" "la")
2201 (set_attr "cpu_facility" "*,longdisp")
2202 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2205 ; movhi instruction pattern(s).
2208 (define_expand "movhi"
2209 [(set (match_operand:HI 0 "nonimmediate_operand" "")
2210 (match_operand:HI 1 "general_operand" ""))]
2213 /* Make it explicit that loading a register from memory
2214 always sign-extends (at least) to SImode. */
2215 if (optimize && can_create_pseudo_p ()
2216 && register_operand (operands[0], VOIDmode)
2217 && GET_CODE (operands[1]) == MEM)
2219 rtx tmp = gen_reg_rtx (SImode);
2220 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
2221 emit_insn (gen_rtx_SET (tmp, ext));
2222 operands[1] = gen_lowpart (HImode, tmp);
2226 (define_insn "*movhi"
2227 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R")
2228 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))]
2246 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX")
2247 (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*")
2248 (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vx,vx,vx,vx,vx,vx")
2249 (set_attr "z10prop" "z10_fr_E1,
2257 z10_super,*,*,*,*,*,*")])
2260 [(set (match_operand:HI 0 "register_operand" "")
2261 (mem:HI (match_operand 1 "address_operand" "")))]
2262 "GET_CODE (operands[1]) == SYMBOL_REF
2263 && CONSTANT_POOL_ADDRESS_P (operands[1])
2264 && get_pool_mode (operands[1]) == HImode
2265 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2266 [(set (match_dup 0) (match_dup 2))]
2267 "operands[2] = get_pool_constant (operands[1]);")
2270 ; movqi instruction pattern(s).
2273 (define_expand "movqi"
2274 [(set (match_operand:QI 0 "nonimmediate_operand" "")
2275 (match_operand:QI 1 "general_operand" ""))]
2278 /* On z/Architecture, zero-extending from memory to register
2279 is just as fast as a QImode load. */
2280 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
2281 && register_operand (operands[0], VOIDmode)
2282 && GET_CODE (operands[1]) == MEM)
2284 rtx tmp = gen_reg_rtx (DImode);
2285 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
2286 emit_insn (gen_rtx_SET (tmp, ext));
2287 operands[1] = gen_lowpart (QImode, tmp);
2291 (define_insn "*movqi"
2292 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R")
2293 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))]
2311 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX")
2312 (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*")
2313 (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vx,vx,vx,vx,vx,vx")
2314 (set_attr "z10prop" "z10_fr_E1,
2325 [(set (match_operand:QI 0 "nonimmediate_operand" "")
2326 (mem:QI (match_operand 1 "address_operand" "")))]
2327 "GET_CODE (operands[1]) == SYMBOL_REF
2328 && CONSTANT_POOL_ADDRESS_P (operands[1])
2329 && get_pool_mode (operands[1]) == QImode
2330 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2331 [(set (match_dup 0) (match_dup 2))]
2332 "operands[2] = get_pool_constant (operands[1]);")
2335 ; movstrictqi instruction pattern(s).
2338 (define_insn "*movstrictqi"
2339 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
2340 (match_operand:QI 1 "memory_operand" "R,T"))]
2345 [(set_attr "op_type" "RX,RXY")
2346 (set_attr "cpu_facility" "*,longdisp")
2347 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2350 ; movstricthi instruction pattern(s).
2353 (define_insn "*movstricthi"
2354 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
2355 (match_operand:HI 1 "memory_operand" "Q,S"))
2356 (clobber (reg:CC CC_REGNUM))]
2361 [(set_attr "op_type" "RS,RSY")
2362 (set_attr "cpu_facility" "*,longdisp")
2363 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2366 ; movstrictsi instruction pattern(s).
2369 (define_insn "movstrictsi"
2370 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2371 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2378 [(set_attr "op_type" "RR,RX,RXY,RRE")
2379 (set_attr "type" "lr,load,load,*")
2380 (set_attr "cpu_facility" "*,*,longdisp,*")
2381 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2384 ; mov(tf|td) instruction pattern(s).
2387 (define_expand "mov<mode>"
2388 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2389 (match_operand:TD_TF 1 "general_operand" ""))]
2393 (define_insn "*mov<mode>_64"
2394 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o")
2395 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))]
2406 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
2407 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
2408 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2410 (define_insn "*mov<mode>_31"
2411 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2412 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2419 [(set_attr "op_type" "RRE,RRE,*,*")
2420 (set_attr "type" "fsimptf,fsimptf,*,*")
2421 (set_attr "cpu_facility" "z196,*,*,*")])
2423 ; TFmode in GPRs splitters
2426 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2427 (match_operand:TD_TF 1 "general_operand" ""))]
2428 "TARGET_ZARCH && reload_completed
2429 && !s_operand (operands[0], <MODE>mode)
2430 && !s_operand (operands[1], <MODE>mode)
2431 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2432 [(set (match_dup 2) (match_dup 4))
2433 (set (match_dup 3) (match_dup 5))]
2435 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2436 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2437 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2438 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2442 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2443 (match_operand:TD_TF 1 "general_operand" ""))]
2444 "TARGET_ZARCH && reload_completed
2445 && !s_operand (operands[0], <MODE>mode)
2446 && !s_operand (operands[1], <MODE>mode)
2447 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2448 [(set (match_dup 2) (match_dup 4))
2449 (set (match_dup 3) (match_dup 5))]
2451 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2452 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2453 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2454 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2458 [(set (match_operand:TD_TF 0 "register_operand" "")
2459 (match_operand:TD_TF 1 "memory_operand" ""))]
2460 "TARGET_ZARCH && reload_completed
2461 && GENERAL_REG_P (operands[0])
2462 && !s_operand (operands[1], VOIDmode)"
2463 [(set (match_dup 0) (match_dup 1))]
2465 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2466 addr = gen_lowpart (Pmode, addr);
2467 s390_load_address (addr, XEXP (operands[1], 0));
2468 operands[1] = replace_equiv_address (operands[1], addr);
2471 ; TFmode in BFPs splitters
2474 [(set (match_operand:TD_TF 0 "register_operand" "")
2475 (match_operand:TD_TF 1 "memory_operand" ""))]
2476 "reload_completed && offsettable_memref_p (operands[1])
2477 && FP_REG_P (operands[0])"
2478 [(set (match_dup 2) (match_dup 4))
2479 (set (match_dup 3) (match_dup 5))]
2481 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2483 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2485 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2486 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2490 [(set (match_operand:TD_TF 0 "memory_operand" "")
2491 (match_operand:TD_TF 1 "register_operand" ""))]
2492 "reload_completed && offsettable_memref_p (operands[0])
2493 && FP_REG_P (operands[1])"
2494 [(set (match_dup 2) (match_dup 4))
2495 (set (match_dup 3) (match_dup 5))]
2497 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2498 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2499 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2501 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2506 ; mov(df|dd) instruction pattern(s).
2509 (define_expand "mov<mode>"
2510 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2511 (match_operand:DD_DF 1 "general_operand" ""))]
2515 (define_insn "*mov<mode>_64dfp"
2516 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2517 "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,v,d,v,R")
2518 (match_operand:DD_DF 1 "general_operand"
2519 " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,G,d,v,R,v"))]
2542 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
2543 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2544 fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,*,load,store")
2545 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*,*")
2546 (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx,vx")])
2548 (define_insn "*mov<mode>_64"
2549 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T")
2550 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d"))]
2565 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY")
2566 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2567 fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
2568 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2569 (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*")])
2571 (define_insn "*mov<mode>_31"
2572 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2573 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2574 (match_operand:DD_DF 1 "general_operand"
2575 " G,f,R,T,f,f,Q,S,d,d,dPT,d"))]
2590 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2591 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2592 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2593 (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")])
2596 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2597 (match_operand:DD_DF 1 "general_operand" ""))]
2598 "!TARGET_ZARCH && reload_completed
2599 && !s_operand (operands[0], <MODE>mode)
2600 && !s_operand (operands[1], <MODE>mode)
2601 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2602 [(set (match_dup 2) (match_dup 4))
2603 (set (match_dup 3) (match_dup 5))]
2605 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2606 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2607 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2608 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2612 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2613 (match_operand:DD_DF 1 "general_operand" ""))]
2614 "!TARGET_ZARCH && reload_completed
2615 && !s_operand (operands[0], <MODE>mode)
2616 && !s_operand (operands[1], <MODE>mode)
2617 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2618 [(set (match_dup 2) (match_dup 4))
2619 (set (match_dup 3) (match_dup 5))]
2621 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2622 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2623 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2624 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2628 [(set (match_operand:DD_DF 0 "register_operand" "")
2629 (match_operand:DD_DF 1 "memory_operand" ""))]
2630 "!TARGET_ZARCH && reload_completed
2631 && !FP_REG_P (operands[0])
2632 && !s_operand (operands[1], VOIDmode)"
2633 [(set (match_dup 0) (match_dup 1))]
2635 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2636 s390_load_address (addr, XEXP (operands[1], 0));
2637 operands[1] = replace_equiv_address (operands[1], addr);
2641 ; mov(sf|sd) instruction pattern(s).
2644 (define_insn "mov<mode>"
2645 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2646 "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R")
2647 (match_operand:SD_SF 1 "general_operand"
2648 " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))]
2673 [(set_attr "op_type" "RRE,RR,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
2674 (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>,
2675 fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store")
2676 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*")
2677 (set_attr "cpu_facility" "z196,vx,*,vx,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vx,vx,vx,vx,vx,vx")])
2680 ; movcc instruction pattern
2683 (define_insn "movcc"
2684 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2685 (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2695 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2696 (set_attr "type" "lr,*,*,load,load,store,store")
2697 (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp")
2698 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2699 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2702 ; Block move (MVC) patterns.
2706 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2707 (match_operand:BLK 1 "memory_operand" "Q"))
2708 (use (match_operand 2 "const_int_operand" "n"))]
2709 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2710 "mvc\t%O0(%2,%R0),%S1"
2711 [(set_attr "op_type" "SS")])
2713 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2714 ; order to have it implemented with mvc.
2717 [(set (match_operand:QI 0 "memory_operand" "")
2718 (match_operand:QI 1 "memory_operand" ""))]
2721 [(set (match_dup 0) (match_dup 1))
2722 (use (const_int 1))])]
2724 operands[0] = adjust_address (operands[0], BLKmode, 0);
2725 operands[1] = adjust_address (operands[1], BLKmode, 0);
2731 [(set (match_operand:BLK 0 "memory_operand" "")
2732 (match_operand:BLK 1 "memory_operand" ""))
2733 (use (match_operand 2 "const_int_operand" ""))])
2735 [(set (match_operand:BLK 3 "memory_operand" "")
2736 (match_operand:BLK 4 "memory_operand" ""))
2737 (use (match_operand 5 "const_int_operand" ""))])]
2738 "((INTVAL (operands[2]) > 16 && INTVAL (operands[5]) > 16)
2739 || (INTVAL (operands[2]) + INTVAL (operands[5]) <= 16))
2740 && s390_offset_p (operands[0], operands[3], operands[2])
2741 && s390_offset_p (operands[1], operands[4], operands[2])
2742 && !s390_overlap_p (operands[0], operands[1],
2743 INTVAL (operands[2]) + INTVAL (operands[5]))
2744 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2746 [(set (match_dup 6) (match_dup 7))
2747 (use (match_dup 8))])]
2748 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2749 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2750 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2754 [(set (match_operand:BLK 0 "plus16_Q_operand" "")
2755 (match_operand:BLK 1 "plus16_Q_operand" ""))
2756 (use (match_operand 2 "const_int_operand" ""))])]
2757 "INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32"
2759 [(set (match_dup 0) (match_dup 1))
2760 (use (const_int 16))])
2762 [(set (match_dup 3) (match_dup 4))
2763 (use (match_dup 5))])]
2764 "operands[3] = change_address (operands[0], VOIDmode,
2765 plus_constant (Pmode, XEXP (operands[0], 0), 16));
2766 operands[4] = change_address (operands[1], VOIDmode,
2767 plus_constant (Pmode, XEXP (operands[1], 0), 16));
2768 operands[5] = GEN_INT (INTVAL (operands[2]) - 16);")
2772 ; load_multiple pattern(s).
2774 ; ??? Due to reload problems with replacing registers inside match_parallel
2775 ; we currently support load_multiple/store_multiple only after reload.
2778 (define_expand "load_multiple"
2779 [(match_par_dup 3 [(set (match_operand 0 "" "")
2780 (match_operand 1 "" ""))
2781 (use (match_operand 2 "" ""))])]
2790 /* Support only loading a constant number of fixed-point registers from
2791 memory and only bother with this if more than two */
2792 if (GET_CODE (operands[2]) != CONST_INT
2793 || INTVAL (operands[2]) < 2
2794 || INTVAL (operands[2]) > 16
2795 || GET_CODE (operands[1]) != MEM
2796 || GET_CODE (operands[0]) != REG
2797 || REGNO (operands[0]) >= 16)
2800 count = INTVAL (operands[2]);
2801 regno = REGNO (operands[0]);
2802 mode = GET_MODE (operands[0]);
2803 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2806 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2807 if (!can_create_pseudo_p ())
2809 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2811 from = XEXP (operands[1], 0);
2814 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2815 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2816 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2818 from = XEXP (XEXP (operands[1], 0), 0);
2819 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2826 from = force_reg (Pmode, XEXP (operands[1], 0));
2830 for (i = 0; i < count; i++)
2831 XVECEXP (operands[3], 0, i)
2832 = gen_rtx_SET (gen_rtx_REG (mode, regno + i),
2833 change_address (operands[1], mode,
2834 plus_constant (Pmode, from,
2835 off + i * GET_MODE_SIZE (mode))));
2838 (define_insn "*load_multiple_di"
2839 [(match_parallel 0 "load_multiple_operation"
2840 [(set (match_operand:DI 1 "register_operand" "=r")
2841 (match_operand:DI 2 "s_operand" "S"))])]
2842 "reload_completed && TARGET_ZARCH"
2844 int words = XVECLEN (operands[0], 0);
2845 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2846 return "lmg\t%1,%0,%S2";
2848 [(set_attr "op_type" "RSY")
2849 (set_attr "type" "lm")])
2851 (define_insn "*load_multiple_si"
2852 [(match_parallel 0 "load_multiple_operation"
2853 [(set (match_operand:SI 1 "register_operand" "=r,r")
2854 (match_operand:SI 2 "s_operand" "Q,S"))])]
2857 int words = XVECLEN (operands[0], 0);
2858 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2859 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2861 [(set_attr "op_type" "RS,RSY")
2862 (set_attr "cpu_facility" "*,longdisp")
2863 (set_attr "type" "lm")])
2866 ; store multiple pattern(s).
2869 (define_expand "store_multiple"
2870 [(match_par_dup 3 [(set (match_operand 0 "" "")
2871 (match_operand 1 "" ""))
2872 (use (match_operand 2 "" ""))])]
2881 /* Support only storing a constant number of fixed-point registers to
2882 memory and only bother with this if more than two. */
2883 if (GET_CODE (operands[2]) != CONST_INT
2884 || INTVAL (operands[2]) < 2
2885 || INTVAL (operands[2]) > 16
2886 || GET_CODE (operands[0]) != MEM
2887 || GET_CODE (operands[1]) != REG
2888 || REGNO (operands[1]) >= 16)
2891 count = INTVAL (operands[2]);
2892 regno = REGNO (operands[1]);
2893 mode = GET_MODE (operands[1]);
2894 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2897 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2899 if (!can_create_pseudo_p ())
2901 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2903 to = XEXP (operands[0], 0);
2906 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2907 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2908 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2910 to = XEXP (XEXP (operands[0], 0), 0);
2911 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2918 to = force_reg (Pmode, XEXP (operands[0], 0));
2922 for (i = 0; i < count; i++)
2923 XVECEXP (operands[3], 0, i)
2924 = gen_rtx_SET (change_address (operands[0], mode,
2925 plus_constant (Pmode, to,
2926 off + i * GET_MODE_SIZE (mode))),
2927 gen_rtx_REG (mode, regno + i));
2930 (define_insn "*store_multiple_di"
2931 [(match_parallel 0 "store_multiple_operation"
2932 [(set (match_operand:DI 1 "s_operand" "=S")
2933 (match_operand:DI 2 "register_operand" "r"))])]
2934 "reload_completed && TARGET_ZARCH"
2936 int words = XVECLEN (operands[0], 0);
2937 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2938 return "stmg\t%2,%0,%S1";
2940 [(set_attr "op_type" "RSY")
2941 (set_attr "type" "stm")])
2944 (define_insn "*store_multiple_si"
2945 [(match_parallel 0 "store_multiple_operation"
2946 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2947 (match_operand:SI 2 "register_operand" "r,r"))])]
2950 int words = XVECLEN (operands[0], 0);
2951 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2952 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2954 [(set_attr "op_type" "RS,RSY")
2955 (set_attr "cpu_facility" "*,longdisp")
2956 (set_attr "type" "stm")])
2959 ;; String instructions.
2962 (define_insn "*execute_rl"
2963 [(match_parallel 0 "execute_operation"
2964 [(unspec [(match_operand 1 "register_operand" "a")
2965 (match_operand 2 "" "")
2966 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2967 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2968 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2970 [(set_attr "op_type" "RIL")
2971 (set_attr "type" "cs")])
2973 (define_insn "*execute"
2974 [(match_parallel 0 "execute_operation"
2975 [(unspec [(match_operand 1 "register_operand" "a")
2976 (match_operand:BLK 2 "memory_operand" "R")
2977 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2978 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2979 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2981 [(set_attr "op_type" "RX")
2982 (set_attr "type" "cs")])
2986 ; strlenM instruction pattern(s).
2989 (define_expand "strlen<mode>"
2990 [(match_operand:P 0 "register_operand" "") ; result
2991 (match_operand:BLK 1 "memory_operand" "") ; input string
2992 (match_operand:SI 2 "immediate_operand" "") ; search character
2993 (match_operand:SI 3 "immediate_operand" "")] ; known alignment
2996 if (!TARGET_VX || operands[2] != const0_rtx)
2997 emit_insn (gen_strlen_srst<mode> (operands[0], operands[1],
2998 operands[2], operands[3]));
3000 s390_expand_vec_strlen (operands[0], operands[1], operands[3]);
3005 (define_expand "strlen_srst<mode>"
3006 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
3009 (unspec:P [(const_int 0)
3010 (match_operand:BLK 1 "memory_operand" "")
3012 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
3013 (clobber (scratch:P))
3014 (clobber (reg:CC CC_REGNUM))])
3016 [(set (match_operand:P 0 "register_operand" "")
3017 (minus:P (match_dup 4) (match_dup 5)))
3018 (clobber (reg:CC CC_REGNUM))])]
3021 operands[4] = gen_reg_rtx (Pmode);
3022 operands[5] = gen_reg_rtx (Pmode);
3023 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
3024 operands[1] = replace_equiv_address (operands[1], operands[5]);
3027 (define_insn "*strlen<mode>"
3028 [(set (match_operand:P 0 "register_operand" "=a")
3029 (unspec:P [(match_operand:P 2 "general_operand" "0")
3030 (mem:BLK (match_operand:P 3 "register_operand" "1"))
3032 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
3033 (clobber (match_scratch:P 1 "=a"))
3034 (clobber (reg:CC CC_REGNUM))]
3036 "srst\t%0,%1\;jo\t.-4"
3037 [(set_attr "length" "8")
3038 (set_attr "type" "vs")])
3041 ; cmpstrM instruction pattern(s).
3044 (define_expand "cmpstrsi"
3045 [(set (reg:SI 0) (const_int 0))
3047 [(clobber (match_operand 3 "" ""))
3048 (clobber (match_dup 4))
3049 (set (reg:CCU CC_REGNUM)
3050 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
3051 (match_operand:BLK 2 "memory_operand" "")))
3054 [(set (match_operand:SI 0 "register_operand" "=d")
3055 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
3056 (clobber (reg:CC CC_REGNUM))])]
3059 /* As the result of CMPINT is inverted compared to what we need,
3060 we have to swap the operands. */
3061 rtx op1 = operands[2];
3062 rtx op2 = operands[1];
3063 rtx addr1 = gen_reg_rtx (Pmode);
3064 rtx addr2 = gen_reg_rtx (Pmode);
3066 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
3067 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
3068 operands[1] = replace_equiv_address_nv (op1, addr1);
3069 operands[2] = replace_equiv_address_nv (op2, addr2);
3070 operands[3] = addr1;
3071 operands[4] = addr2;
3074 (define_insn "*cmpstr<mode>"
3075 [(clobber (match_operand:P 0 "register_operand" "=d"))
3076 (clobber (match_operand:P 1 "register_operand" "=d"))
3077 (set (reg:CCU CC_REGNUM)
3078 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
3079 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
3082 "clst\t%0,%1\;jo\t.-4"
3083 [(set_attr "length" "8")
3084 (set_attr "type" "vs")])
3087 ; movstr instruction pattern.
3090 (define_expand "movstr"
3091 [(match_operand 0 "register_operand" "")
3092 (match_operand 1 "memory_operand" "")
3093 (match_operand 2 "memory_operand" "")]
3097 emit_insn (gen_movstrdi (operands[0], operands[1], operands[2]));
3099 emit_insn (gen_movstrsi (operands[0], operands[1], operands[2]));
3103 (define_expand "movstr<P:mode>"
3104 [(set (reg:SI 0) (const_int 0))
3106 [(clobber (match_dup 3))
3107 (set (match_operand:BLK 1 "memory_operand" "")
3108 (match_operand:BLK 2 "memory_operand" ""))
3109 (set (match_operand:P 0 "register_operand" "")
3110 (unspec:P [(match_dup 1)
3112 (reg:SI 0)] UNSPEC_MVST))
3113 (clobber (reg:CC CC_REGNUM))])]
3118 if (TARGET_VX && optimize_function_for_speed_p (cfun))
3120 s390_expand_vec_movstr (operands[0], operands[1], operands[2]);
3124 addr1 = gen_reg_rtx (Pmode);
3125 addr2 = gen_reg_rtx (Pmode);
3127 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3128 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
3129 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3130 operands[2] = replace_equiv_address_nv (operands[2], addr2);
3131 operands[3] = addr2;
3134 (define_insn "*movstr"
3135 [(clobber (match_operand:P 2 "register_operand" "=d"))
3136 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
3137 (mem:BLK (match_operand:P 3 "register_operand" "2")))
3138 (set (match_operand:P 0 "register_operand" "=d")
3139 (unspec:P [(mem:BLK (match_dup 1))
3140 (mem:BLK (match_dup 3))
3141 (reg:SI 0)] UNSPEC_MVST))
3142 (clobber (reg:CC CC_REGNUM))]
3144 "mvst\t%1,%2\;jo\t.-4"
3145 [(set_attr "length" "8")
3146 (set_attr "type" "vs")])
3150 ; movmemM instruction pattern(s).
3153 (define_expand "movmem<mode>"
3154 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
3155 (match_operand:BLK 1 "memory_operand" "")) ; source
3156 (use (match_operand:GPR 2 "general_operand" "")) ; count
3157 (match_operand 3 "" "")]
3160 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
3166 ; Move a block that is up to 256 bytes in length.
3167 ; The block length is taken as (operands[2] % 256) + 1.
3169 (define_expand "movmem_short"
3171 [(set (match_operand:BLK 0 "memory_operand" "")
3172 (match_operand:BLK 1 "memory_operand" ""))
3173 (use (match_operand 2 "nonmemory_operand" ""))
3174 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3175 (clobber (match_dup 3))])]
3177 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3179 (define_insn "*movmem_short"
3180 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3181 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
3182 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3183 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3184 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3185 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3187 [(set_attr "type" "cs")
3188 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3191 [(set (match_operand:BLK 0 "memory_operand" "")
3192 (match_operand:BLK 1 "memory_operand" ""))
3193 (use (match_operand 2 "const_int_operand" ""))
3194 (use (match_operand 3 "immediate_operand" ""))
3195 (clobber (scratch))]
3198 [(set (match_dup 0) (match_dup 1))
3199 (use (match_dup 2))])]
3200 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3203 [(set (match_operand:BLK 0 "memory_operand" "")
3204 (match_operand:BLK 1 "memory_operand" ""))
3205 (use (match_operand 2 "register_operand" ""))
3206 (use (match_operand 3 "memory_operand" ""))
3207 (clobber (scratch))]
3210 [(unspec [(match_dup 2) (match_dup 3)
3211 (const_int 0)] UNSPEC_EXECUTE)
3212 (set (match_dup 0) (match_dup 1))
3213 (use (const_int 1))])]
3217 [(set (match_operand:BLK 0 "memory_operand" "")
3218 (match_operand:BLK 1 "memory_operand" ""))
3219 (use (match_operand 2 "register_operand" ""))
3220 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3221 (clobber (scratch))]
3222 "TARGET_Z10 && reload_completed"
3224 [(unspec [(match_dup 2) (const_int 0)
3225 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3226 (set (match_dup 0) (match_dup 1))
3227 (use (const_int 1))])]
3228 "operands[3] = gen_label_rtx ();")
3231 [(set (match_operand:BLK 0 "memory_operand" "")
3232 (match_operand:BLK 1 "memory_operand" ""))
3233 (use (match_operand 2 "register_operand" ""))
3234 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3235 (clobber (match_operand 3 "register_operand" ""))]
3237 [(set (match_dup 3) (label_ref (match_dup 4)))
3239 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3240 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3241 (set (match_dup 0) (match_dup 1))
3242 (use (const_int 1))])]
3243 "operands[4] = gen_label_rtx ();")
3245 ; Move a block of arbitrary length.
3247 (define_expand "movmem_long"
3249 [(clobber (match_dup 2))
3250 (clobber (match_dup 3))
3251 (set (match_operand:BLK 0 "memory_operand" "")
3252 (match_operand:BLK 1 "memory_operand" ""))
3253 (use (match_operand 2 "general_operand" ""))
3255 (clobber (reg:CC CC_REGNUM))])]
3258 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3259 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3260 rtx reg0 = gen_reg_rtx (dreg_mode);
3261 rtx reg1 = gen_reg_rtx (dreg_mode);
3262 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3263 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3264 rtx len0 = gen_lowpart (Pmode, reg0);
3265 rtx len1 = gen_lowpart (Pmode, reg1);
3267 emit_clobber (reg0);
3268 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3269 emit_move_insn (len0, operands[2]);
3271 emit_clobber (reg1);
3272 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3273 emit_move_insn (len1, operands[2]);
3275 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3276 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3281 (define_insn "*movmem_long"
3282 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3283 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3284 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3285 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
3288 (clobber (reg:CC CC_REGNUM))]
3289 "TARGET_64BIT || !TARGET_ZARCH"
3290 "mvcle\t%0,%1,0\;jo\t.-4"
3291 [(set_attr "length" "8")
3292 (set_attr "type" "vs")])
3294 (define_insn "*movmem_long_31z"
3295 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3296 (clobber (match_operand:TI 1 "register_operand" "=d"))
3297 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3298 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
3301 (clobber (reg:CC CC_REGNUM))]
3302 "!TARGET_64BIT && TARGET_ZARCH"
3303 "mvcle\t%0,%1,0\;jo\t.-4"
3304 [(set_attr "length" "8")
3305 (set_attr "type" "vs")])
3312 (define_expand "signbit<mode>2"
3313 [(set (reg:CCZ CC_REGNUM)
3314 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3317 (set (match_operand:SI 0 "register_operand" "=d")
3318 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3321 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
3324 (define_expand "isinf<mode>2"
3325 [(set (reg:CCZ CC_REGNUM)
3326 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3329 (set (match_operand:SI 0 "register_operand" "=d")
3330 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3333 operands[2] = GEN_INT (S390_TDC_INFINITY);
3336 ; This extracts CC into a GPR properly shifted. The actual IPM
3337 ; instruction will be issued by reload. The constraint of operand 1
3338 ; forces reload to use a GPR. So reload will issue a movcc insn for
3339 ; copying CC into a GPR first.
3340 (define_insn_and_split "*cc_to_int"
3341 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3342 (unspec:SI [(match_operand 1 "register_operand" "0")]
3347 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
3349 ; This insn is used to generate all variants of the Test Data Class
3350 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
3351 ; is the register to be tested and the second one is the bit mask
3352 ; specifying the required test(s).
3354 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
3355 (define_insn "*TDC_insn_<mode>"
3356 [(set (reg:CCZ CC_REGNUM)
3357 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
3358 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
3360 "t<_d>c<xde><bt>\t%0,%1"
3361 [(set_attr "op_type" "RXE")
3362 (set_attr "type" "fsimp<mode>")])
3367 ; setmemM instruction pattern(s).
3370 (define_expand "setmem<mode>"
3371 [(set (match_operand:BLK 0 "memory_operand" "")
3372 (match_operand:QI 2 "general_operand" ""))
3373 (use (match_operand:GPR 1 "general_operand" ""))
3374 (match_operand 3 "" "")]
3376 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
3378 ; Clear a block that is up to 256 bytes in length.
3379 ; The block length is taken as (operands[1] % 256) + 1.
3381 (define_expand "clrmem_short"
3383 [(set (match_operand:BLK 0 "memory_operand" "")
3385 (use (match_operand 1 "nonmemory_operand" ""))
3386 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3387 (clobber (match_dup 2))
3388 (clobber (reg:CC CC_REGNUM))])]
3390 "operands[2] = gen_rtx_SCRATCH (Pmode);")
3392 (define_insn "*clrmem_short"
3393 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3395 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
3396 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
3397 (clobber (match_scratch:P 3 "=X,X,X,&a"))
3398 (clobber (reg:CC CC_REGNUM))]
3399 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
3401 [(set_attr "type" "cs")
3402 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3405 [(set (match_operand:BLK 0 "memory_operand" "")
3407 (use (match_operand 1 "const_int_operand" ""))
3408 (use (match_operand 2 "immediate_operand" ""))
3410 (clobber (reg:CC CC_REGNUM))]
3413 [(set (match_dup 0) (const_int 0))
3415 (clobber (reg:CC CC_REGNUM))])]
3416 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
3419 [(set (match_operand:BLK 0 "memory_operand" "")
3421 (use (match_operand 1 "register_operand" ""))
3422 (use (match_operand 2 "memory_operand" ""))
3424 (clobber (reg:CC CC_REGNUM))]
3427 [(unspec [(match_dup 1) (match_dup 2)
3428 (const_int 0)] UNSPEC_EXECUTE)
3429 (set (match_dup 0) (const_int 0))
3431 (clobber (reg:CC CC_REGNUM))])]
3435 [(set (match_operand:BLK 0 "memory_operand" "")
3437 (use (match_operand 1 "register_operand" ""))
3438 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3440 (clobber (reg:CC CC_REGNUM))]
3441 "TARGET_Z10 && reload_completed"
3443 [(unspec [(match_dup 1) (const_int 0)
3444 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3445 (set (match_dup 0) (const_int 0))
3447 (clobber (reg:CC CC_REGNUM))])]
3448 "operands[3] = gen_label_rtx ();")
3451 [(set (match_operand:BLK 0 "memory_operand" "")
3453 (use (match_operand 1 "register_operand" ""))
3454 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3455 (clobber (match_operand 2 "register_operand" ""))
3456 (clobber (reg:CC CC_REGNUM))]
3458 [(set (match_dup 2) (label_ref (match_dup 3)))
3460 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
3461 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3462 (set (match_dup 0) (const_int 0))
3464 (clobber (reg:CC CC_REGNUM))])]
3465 "operands[3] = gen_label_rtx ();")
3467 ; Initialize a block of arbitrary length with (operands[2] % 256).
3469 (define_expand "setmem_long_<P:mode>"
3471 [(clobber (match_dup 1))
3472 (set (match_operand:BLK 0 "memory_operand" "")
3473 (unspec:BLK [(match_operand:P 2 "setmem_operand" "")
3474 (match_dup 4)] UNSPEC_REPLICATE_BYTE))
3476 (clobber (reg:CC CC_REGNUM))])]
3479 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3480 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3481 rtx reg0 = gen_reg_rtx (dreg_mode);
3482 rtx reg1 = gen_reg_rtx (dreg_mode);
3483 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3484 rtx len0 = gen_lowpart (Pmode, reg0);
3486 emit_clobber (reg0);
3487 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3488 emit_move_insn (len0, operands[1]);
3490 emit_move_insn (reg1, const0_rtx);
3492 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3495 operands[4] = gen_lowpart (Pmode, operands[1]);
3498 ; Patterns for 31 bit + Esa and 64 bit + Zarch.
3500 (define_insn "*setmem_long"
3501 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3502 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3503 (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y")
3504 (subreg:P (match_dup 3) <modesize>)]
3505 UNSPEC_REPLICATE_BYTE))
3506 (use (match_operand:<DBL> 1 "register_operand" "d"))
3507 (clobber (reg:CC CC_REGNUM))]
3508 "TARGET_64BIT || !TARGET_ZARCH"
3509 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3510 [(set_attr "length" "8")
3511 (set_attr "type" "vs")])
3513 (define_insn "*setmem_long_and"
3514 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3515 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3516 (unspec:BLK [(zero_extend:P (match_operand:QI 2 "setmem_operand" "Y"))
3517 (subreg:P (match_dup 3) <modesize>)]
3518 UNSPEC_REPLICATE_BYTE))
3519 (use (match_operand:<DBL> 1 "register_operand" "d"))
3520 (clobber (reg:CC CC_REGNUM))]
3521 "(TARGET_64BIT || !TARGET_ZARCH)"
3522 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3523 [(set_attr "length" "8")
3524 (set_attr "type" "vs")])
3526 ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets
3527 ; of the SImode subregs.
3529 (define_insn "*setmem_long_31z"
3530 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3531 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3532 (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y")
3533 (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
3534 (use (match_operand:TI 1 "register_operand" "d"))
3535 (clobber (reg:CC CC_REGNUM))]
3536 "!TARGET_64BIT && TARGET_ZARCH"
3537 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3538 [(set_attr "length" "8")
3539 (set_attr "type" "vs")])
3541 (define_insn "*setmem_long_and_31z"
3542 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3543 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3544 (unspec:BLK [(zero_extend:SI (match_operand:QI 2 "setmem_operand" "Y"))
3545 (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
3546 (use (match_operand:TI 1 "register_operand" "d"))
3547 (clobber (reg:CC CC_REGNUM))]
3548 "(!TARGET_64BIT && TARGET_ZARCH)"
3549 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3550 [(set_attr "length" "8")
3551 (set_attr "type" "vs")])
3554 ; cmpmemM instruction pattern(s).
3557 (define_expand "cmpmemsi"
3558 [(set (match_operand:SI 0 "register_operand" "")
3559 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3560 (match_operand:BLK 2 "memory_operand" "") ) )
3561 (use (match_operand:SI 3 "general_operand" ""))
3562 (use (match_operand:SI 4 "" ""))]
3565 if (s390_expand_cmpmem (operands[0], operands[1],
3566 operands[2], operands[3]))
3572 ; Compare a block that is up to 256 bytes in length.
3573 ; The block length is taken as (operands[2] % 256) + 1.
3575 (define_expand "cmpmem_short"
3577 [(set (reg:CCU CC_REGNUM)
3578 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3579 (match_operand:BLK 1 "memory_operand" "")))
3580 (use (match_operand 2 "nonmemory_operand" ""))
3581 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3582 (clobber (match_dup 3))])]
3584 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3586 (define_insn "*cmpmem_short"
3587 [(set (reg:CCU CC_REGNUM)
3588 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3589 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3590 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3591 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3592 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3593 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3595 [(set_attr "type" "cs")
3596 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3599 [(set (reg:CCU CC_REGNUM)
3600 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3601 (match_operand:BLK 1 "memory_operand" "")))
3602 (use (match_operand 2 "const_int_operand" ""))
3603 (use (match_operand 3 "immediate_operand" ""))
3604 (clobber (scratch))]
3607 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3608 (use (match_dup 2))])]
3609 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3612 [(set (reg:CCU CC_REGNUM)
3613 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3614 (match_operand:BLK 1 "memory_operand" "")))
3615 (use (match_operand 2 "register_operand" ""))
3616 (use (match_operand 3 "memory_operand" ""))
3617 (clobber (scratch))]
3620 [(unspec [(match_dup 2) (match_dup 3)
3621 (const_int 0)] UNSPEC_EXECUTE)
3622 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3623 (use (const_int 1))])]
3627 [(set (reg:CCU CC_REGNUM)
3628 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3629 (match_operand:BLK 1 "memory_operand" "")))
3630 (use (match_operand 2 "register_operand" ""))
3631 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3632 (clobber (scratch))]
3633 "TARGET_Z10 && reload_completed"
3635 [(unspec [(match_dup 2) (const_int 0)
3636 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3637 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3638 (use (const_int 1))])]
3639 "operands[4] = gen_label_rtx ();")
3642 [(set (reg:CCU CC_REGNUM)
3643 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3644 (match_operand:BLK 1 "memory_operand" "")))
3645 (use (match_operand 2 "register_operand" ""))
3646 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3647 (clobber (match_operand 3 "register_operand" ""))]
3649 [(set (match_dup 3) (label_ref (match_dup 4)))
3651 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3652 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3653 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3654 (use (const_int 1))])]
3655 "operands[4] = gen_label_rtx ();")
3657 ; Compare a block of arbitrary length.
3659 (define_expand "cmpmem_long"
3661 [(clobber (match_dup 2))
3662 (clobber (match_dup 3))
3663 (set (reg:CCU CC_REGNUM)
3664 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3665 (match_operand:BLK 1 "memory_operand" "")))
3666 (use (match_operand 2 "general_operand" ""))
3667 (use (match_dup 3))])]
3670 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3671 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3672 rtx reg0 = gen_reg_rtx (dreg_mode);
3673 rtx reg1 = gen_reg_rtx (dreg_mode);
3674 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3675 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3676 rtx len0 = gen_lowpart (Pmode, reg0);
3677 rtx len1 = gen_lowpart (Pmode, reg1);
3679 emit_clobber (reg0);
3680 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3681 emit_move_insn (len0, operands[2]);
3683 emit_clobber (reg1);
3684 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3685 emit_move_insn (len1, operands[2]);
3687 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3688 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3693 (define_insn "*cmpmem_long"
3694 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3695 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3696 (set (reg:CCU CC_REGNUM)
3697 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3698 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3700 (use (match_dup 3))]
3701 "TARGET_64BIT || !TARGET_ZARCH"
3702 "clcle\t%0,%1,0\;jo\t.-4"
3703 [(set_attr "length" "8")
3704 (set_attr "type" "vs")])
3706 (define_insn "*cmpmem_long_31z"
3707 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3708 (clobber (match_operand:TI 1 "register_operand" "=d"))
3709 (set (reg:CCU CC_REGNUM)
3710 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3711 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3713 (use (match_dup 3))]
3714 "!TARGET_64BIT && TARGET_ZARCH"
3715 "clcle\t%0,%1,0\;jo\t.-4"
3716 [(set_attr "op_type" "NN")
3717 (set_attr "type" "vs")
3718 (set_attr "length" "8")])
3720 ; Convert CCUmode condition code to integer.
3721 ; Result is zero if EQ, positive if LTU, negative if GTU.
3723 (define_insn_and_split "cmpint"
3724 [(set (match_operand:SI 0 "register_operand" "=d")
3725 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3726 UNSPEC_STRCMPCC_TO_INT))
3727 (clobber (reg:CC CC_REGNUM))]
3731 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3733 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3734 (clobber (reg:CC CC_REGNUM))])])
3736 (define_insn_and_split "*cmpint_cc"
3737 [(set (reg CC_REGNUM)
3738 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3739 UNSPEC_STRCMPCC_TO_INT)
3741 (set (match_operand:SI 0 "register_operand" "=d")
3742 (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3743 "s390_match_ccmode (insn, CCSmode)"
3745 "&& reload_completed"
3746 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3748 [(set (match_dup 2) (match_dup 3))
3749 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3751 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3752 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3753 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3756 (define_insn_and_split "*cmpint_sign"
3757 [(set (match_operand:DI 0 "register_operand" "=d")
3758 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3759 UNSPEC_STRCMPCC_TO_INT)))
3760 (clobber (reg:CC CC_REGNUM))]
3763 "&& reload_completed"
3764 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3766 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3767 (clobber (reg:CC CC_REGNUM))])])
3769 (define_insn_and_split "*cmpint_sign_cc"
3770 [(set (reg CC_REGNUM)
3771 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3772 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3773 UNSPEC_STRCMPCC_TO_INT) 0)
3774 (const_int 32)) (const_int 32))
3776 (set (match_operand:DI 0 "register_operand" "=d")
3777 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3778 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3780 "&& reload_completed"
3781 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3783 [(set (match_dup 2) (match_dup 3))
3784 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3786 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3787 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3788 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3793 ;;- Conversion instructions.
3796 (define_insn "*sethighpartsi"
3797 [(set (match_operand:SI 0 "register_operand" "=d,d")
3798 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3799 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3800 (clobber (reg:CC CC_REGNUM))]
3805 [(set_attr "op_type" "RS,RSY")
3806 (set_attr "cpu_facility" "*,longdisp")
3807 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3809 (define_insn "*sethighpartdi_64"
3810 [(set (match_operand:DI 0 "register_operand" "=d")
3811 (unspec:DI [(match_operand:BLK 1 "s_operand" "S")
3812 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3813 (clobber (reg:CC CC_REGNUM))]
3816 [(set_attr "op_type" "RSY")
3817 (set_attr "z10prop" "z10_super")])
3819 (define_insn "*sethighpartdi_31"
3820 [(set (match_operand:DI 0 "register_operand" "=d,d")
3821 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3822 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3823 (clobber (reg:CC CC_REGNUM))]
3828 [(set_attr "op_type" "RS,RSY")
3829 (set_attr "cpu_facility" "*,longdisp")
3830 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3833 ; extv instruction patterns
3836 ; FIXME: This expander needs to be converted from DI to GPR as well
3837 ; after resolving some issues with it.
3839 (define_expand "extzv"
3841 [(set (match_operand:DI 0 "register_operand" "=d")
3843 (match_operand:DI 1 "register_operand" "d")
3844 (match_operand 2 "const_int_operand" "") ; size
3845 (match_operand 3 "const_int_operand" ""))) ; start
3846 (clobber (reg:CC CC_REGNUM))])]
3849 if (! EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 64))
3851 /* Starting with zEC12 there is risbgn not clobbering CC. */
3854 emit_move_insn (operands[0],
3855 gen_rtx_ZERO_EXTRACT (DImode,
3863 (define_insn "*extzv<mode><clobbercc_or_nocc>"
3864 [(set (match_operand:GPR 0 "register_operand" "=d")
3866 (match_operand:GPR 1 "register_operand" "d")
3867 (match_operand 2 "const_int_operand" "") ; size
3868 (match_operand 3 "const_int_operand" ""))) ; start
3870 "<z10_or_zEC12_cond>
3871 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]),
3872 GET_MODE_BITSIZE (<MODE>mode))"
3873 "<risbg_n>\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift
3874 [(set_attr "op_type" "RIE")
3875 (set_attr "z10prop" "z10_super_E1")])
3877 ; 64 bit: (a & -16) | ((b >> 8) & 15)
3878 (define_insn "*extzvdi<clobbercc_or_nocc>_lshiftrt"
3879 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3880 (match_operand 1 "const_int_operand" "") ; size
3881 (match_operand 2 "const_int_operand" "")) ; start
3882 (lshiftrt:DI (match_operand:DI 3 "register_operand" "d")
3883 (match_operand:DI 4 "nonzero_shift_count_operand" "")))]
3884 "<z10_or_zEC12_cond>
3885 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
3886 && 64 - UINTVAL (operands[4]) >= UINTVAL (operands[1])"
3887 "<risbg_n>\t%0,%3,%2,%2+%1-1,128-%2-%1-%4"
3888 [(set_attr "op_type" "RIE")
3889 (set_attr "z10prop" "z10_super_E1")])
3891 ; 32 bit: (a & -16) | ((b >> 8) & 15)
3892 (define_insn "*<risbg_n>_ior_and_sr_ze"
3893 [(set (match_operand:SI 0 "register_operand" "=d")
3895 (match_operand:SI 1 "register_operand" "0")
3896 (match_operand:SI 2 "const_int_operand" ""))
3899 (match_operand:DI 3 "register_operand" "d")
3900 (match_operand 4 "const_int_operand" "") ; size
3901 (match_operand 5 "const_int_operand" "")) ; start
3903 "<z10_or_zEC12_cond>
3904 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), 64)
3905 && UINTVAL (operands[2]) == (~(0ULL) << UINTVAL (operands[4]))"
3906 "<risbg_n>\t%0,%3,64-%4,63,%4+%5"
3907 [(set_attr "op_type" "RIE")
3908 (set_attr "z10prop" "z10_super_E1")])
3910 ; ((int)foo >> 10) & 1;
3911 (define_insn "*extract1bitdi<clobbercc_or_nocc>"
3912 [(set (match_operand:DI 0 "register_operand" "=d")
3913 (ne:DI (zero_extract:DI
3914 (match_operand:DI 1 "register_operand" "d")
3915 (const_int 1) ; size
3916 (match_operand 2 "const_int_operand" "")) ; start
3918 "<z10_or_zEC12_cond>
3919 && EXTRACT_ARGS_IN_RANGE (1, INTVAL (operands[2]), 64)"
3920 "<risbg_n>\t%0,%1,64-1,128+63,%2+1" ; dst, src, start, end, shift
3921 [(set_attr "op_type" "RIE")
3922 (set_attr "z10prop" "z10_super_E1")])
3924 (define_insn "*<risbg_n>_and_subregdi_rotr"
3925 [(set (match_operand:DI 0 "register_operand" "=d")
3927 (rotate:SINT (match_operand:SINT 1 "register_operand" "d")
3928 (match_operand:SINT 2 "const_int_operand" "")) 0)
3929 (match_operand:DI 3 "contiguous_bitmask_operand" "")))]
3930 "<z10_or_zEC12_cond>
3931 && UINTVAL (operands[3]) < (1ULL << (UINTVAL (operands[2]) & 0x3f))"
3932 "<risbg_n>\t%0,%1,%s3,128+%e3,<bitoff_plus>%2" ; dst, src, start, end, shift
3933 [(set_attr "op_type" "RIE")
3934 (set_attr "z10prop" "z10_super_E1")])
3936 (define_insn "*<risbg_n>_and_subregdi_rotl"
3937 [(set (match_operand:DI 0 "register_operand" "=d")
3939 (rotate:SINT (match_operand:SINT 1 "register_operand" "d")
3940 (match_operand:SINT 2 "const_int_operand" "")) 0)
3941 (match_operand:DI 3 "contiguous_bitmask_operand" "")))]
3942 "<z10_or_zEC12_cond>
3943 && !(UINTVAL (operands[3]) & ((1ULL << (UINTVAL (operands[2]) & 0x3f)) - 1))"
3944 "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift
3945 [(set_attr "op_type" "RIE")
3946 (set_attr "z10prop" "z10_super_E1")])
3948 (define_insn "*<risbg_n>_di_and_rot"
3949 [(set (match_operand:DI 0 "register_operand" "=d")
3950 (and:DI (rotate:DI (match_operand:DI 1 "register_operand" "d")
3951 (match_operand:DI 2 "const_int_operand" ""))
3952 (match_operand:DI 3 "contiguous_bitmask_operand" "")))]
3953 "<z10_or_zEC12_cond>"
3954 "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift
3955 [(set_attr "op_type" "RIE")
3956 (set_attr "z10prop" "z10_super_E1")])
3958 (define_insn_and_split "*pre_z10_extzv<mode>"
3959 [(set (match_operand:GPR 0 "register_operand" "=d")
3960 (zero_extract:GPR (match_operand:QI 1 "s_operand" "S")
3961 (match_operand 2 "nonzero_shift_count_operand" "")
3963 (clobber (reg:CC CC_REGNUM))]
3966 "&& reload_completed"
3968 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3969 (clobber (reg:CC CC_REGNUM))])
3970 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3972 int bitsize = INTVAL (operands[2]);
3973 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3974 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3976 operands[1] = adjust_address (operands[1], BLKmode, 0);
3977 set_mem_size (operands[1], size);
3978 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3979 operands[3] = GEN_INT (mask);
3982 (define_insn_and_split "*pre_z10_extv<mode>"
3983 [(set (match_operand:GPR 0 "register_operand" "=d")
3984 (sign_extract:GPR (match_operand:QI 1 "s_operand" "S")
3985 (match_operand 2 "nonzero_shift_count_operand" "")
3987 (clobber (reg:CC CC_REGNUM))]
3990 "&& reload_completed"
3992 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3993 (clobber (reg:CC CC_REGNUM))])
3995 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3996 (clobber (reg:CC CC_REGNUM))])]
3998 int bitsize = INTVAL (operands[2]);
3999 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
4000 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
4002 operands[1] = adjust_address (operands[1], BLKmode, 0);
4003 set_mem_size (operands[1], size);
4004 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
4005 operands[3] = GEN_INT (mask);
4009 ; insv instruction patterns
4012 (define_expand "insv"
4013 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
4014 (match_operand 1 "const_int_operand" "")
4015 (match_operand 2 "const_int_operand" ""))
4016 (match_operand 3 "general_operand" ""))]
4019 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
4025 ; The normal RTL expansion will never generate a zero_extract where
4026 ; the location operand isn't word mode. However, we do this in the
4027 ; back-end when generating atomic operations. See s390_two_part_insv.
4028 (define_insn "*insv<mode><clobbercc_or_nocc>"
4029 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
4030 (match_operand 1 "const_int_operand" "I") ; size
4031 (match_operand 2 "const_int_operand" "I")) ; pos
4032 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
4033 "<z10_or_zEC12_cond>
4034 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]),
4035 GET_MODE_BITSIZE (<MODE>mode))
4036 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
4037 "<risbg_n>\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1"
4038 [(set_attr "op_type" "RIE")
4039 (set_attr "z10prop" "z10_super_E1")])
4041 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
4042 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
4043 (define_insn "*insv<mode><clobbercc_or_nocc>_noshift"
4044 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d")
4045 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d,0")
4046 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
4047 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0,d")
4048 (match_operand:GPR 4 "const_int_operand" ""))))]
4049 "<z10_or_zEC12_cond> && INTVAL (operands[2]) == ~INTVAL (operands[4])"
4051 <risbg_n>\t%0,%1,%<bfstart>2,%<bfend>2,0
4052 <risbg_n>\t%0,%3,%<bfstart>4,%<bfend>4,0"
4053 [(set_attr "op_type" "RIE")
4054 (set_attr "z10prop" "z10_super_E1")])
4056 (define_insn "*insv_z10_noshift_cc"
4057 [(set (reg CC_REGNUM)
4060 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0")
4061 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
4062 (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d")
4063 (match_operand:DI 4 "const_int_operand" "")))
4065 (set (match_operand:DI 0 "nonimmediate_operand" "=d,d")
4066 (ior:DI (and:DI (match_dup 1) (match_dup 2))
4067 (and:DI (match_dup 3) (match_dup 4))))]
4068 "TARGET_Z10 && s390_match_ccmode (insn, CCSmode)
4069 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
4071 risbg\t%0,%1,%s2,%e2,0
4072 risbg\t%0,%3,%s4,%e4,0"
4073 [(set_attr "op_type" "RIE")
4074 (set_attr "z10prop" "z10_super_E1")])
4076 (define_insn "*insv_z10_noshift_cconly"
4081 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0")
4082 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
4083 (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d")
4084 (match_operand:DI 4 "const_int_operand" "")))
4086 (clobber (match_scratch:DI 0 "=d,d"))]
4087 "TARGET_Z10 && s390_match_ccmode (insn, CCSmode)
4088 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
4090 risbg\t%0,%1,%s2,%e2,0
4091 risbg\t%0,%3,%s4,%e4,0"
4092 [(set_attr "op_type" "RIE")
4093 (set_attr "z10prop" "z10_super_E1")])
4095 ; Implement appending Y on the left of S bits of X
4096 ; x = (y << s) | (x & ((1 << s) - 1))
4097 (define_insn "*insv<mode><clobbercc_or_nocc>_appendbitsleft"
4098 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4099 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
4100 (match_operand:GPR 2 "immediate_operand" ""))
4101 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
4102 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
4103 "<z10_or_zEC12_cond>
4104 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
4105 "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4"
4106 [(set_attr "op_type" "RIE")
4107 (set_attr "z10prop" "z10_super_E1")])
4109 ; a = ((i32)a & -16777216) | (((ui32)b) >> 8)
4110 (define_insn "*<risbg_n>_<mode>_ior_and_lshiftrt"
4111 [(set (match_operand:GPR 0 "register_operand" "=d")
4113 (match_operand:GPR 1 "register_operand" "0")
4114 (match_operand:GPR 2 "const_int_operand" ""))
4116 (match_operand:GPR 3 "register_operand" "d")
4117 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
4118 "<z10_or_zEC12_cond> && UINTVAL (operands[2])
4119 == (~(0ULL) << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))"
4120 "<risbg_n>\t%0,%3,<bitoff_plus>%4,63,64-%4"
4121 [(set_attr "op_type" "RIE")
4122 (set_attr "z10prop" "z10_super_E1")])
4124 ; (ui32)(((ui64)x) >> 48) | ((i32)y & -65536);
4125 (define_insn "*<risbg_n>_sidi_ior_and_lshiftrt"
4126 [(set (match_operand:SI 0 "register_operand" "=d")
4128 (match_operand:SI 1 "register_operand" "0")
4129 (match_operand:SI 2 "const_int_operand" ""))
4132 (match_operand:DI 3 "register_operand" "d")
4133 (match_operand:DI 4 "nonzero_shift_count_operand" "")) 4)))]
4134 "<z10_or_zEC12_cond>
4135 && UINTVAL (operands[2]) == ~(~(0ULL) >> UINTVAL (operands[4]))"
4136 "<risbg_n>\t%0,%3,%4,63,64-%4"
4137 [(set_attr "op_type" "RIE")
4138 (set_attr "z10prop" "z10_super_E1")])
4140 ; (ui32)(((ui64)x) >> 12) & -4
4141 (define_insn "*trunc_sidi_and_subreg_lshrt<clobbercc_or_nocc>"
4142 [(set (match_operand:SI 0 "register_operand" "=d")
4144 (subreg:SI (lshiftrt:DI
4145 (match_operand:DI 1 "register_operand" "d")
4146 (match_operand:DI 2 "nonzero_shift_count_operand" "")) 4)
4147 (match_operand:SI 3 "contiguous_bitmask_nowrap_operand" "")))]
4148 "<z10_or_zEC12_cond>"
4149 "<risbg_n>\t%0,%1,%t3,128+%f3,64-%2"
4150 [(set_attr "op_type" "RIE")
4151 (set_attr "z10prop" "z10_super_E1")])
4153 ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting
4154 ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1))
4155 ; -> z = y >> d; z = risbg;
4158 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
4159 (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
4160 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4161 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
4162 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
4163 "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
4165 (lshiftrt:GPR (match_dup 1) (match_dup 2)))
4167 (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
4168 (ashift:GPR (match_dup 3) (match_dup 4))))]
4170 operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
4171 if (reg_overlap_mentioned_p (operands[0], operands[3]))
4173 if (!can_create_pseudo_p ())
4175 operands[6] = gen_reg_rtx (<MODE>mode);
4178 operands[6] = operands[0];
4183 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
4184 (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
4185 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4186 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
4187 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
4188 (clobber (reg:CC CC_REGNUM))])]
4189 "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
4191 (lshiftrt:GPR (match_dup 1) (match_dup 2)))
4194 (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
4195 (ashift:GPR (match_dup 3) (match_dup 4))))
4196 (clobber (reg:CC CC_REGNUM))])]
4198 operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
4199 if (reg_overlap_mentioned_p (operands[0], operands[3]))
4201 if (!can_create_pseudo_p ())
4203 operands[6] = gen_reg_rtx (<MODE>mode);
4206 operands[6] = operands[0];
4210 (define_insn "*r<noxa>sbg_<mode>_noshift"
4211 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4213 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
4214 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
4215 (match_operand:GPR 3 "nonimmediate_operand" "0")))
4216 (clobber (reg:CC CC_REGNUM))]
4218 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
4219 [(set_attr "op_type" "RIE")])
4222 (define_insn "*r<noxa>sbg_di_rotl"
4223 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4227 (match_operand:DI 1 "nonimmediate_operand" "d")
4228 (match_operand:DI 3 "const_int_operand" ""))
4229 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
4230 (match_operand:DI 4 "nonimmediate_operand" "0")))
4231 (clobber (reg:CC CC_REGNUM))]
4233 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
4234 [(set_attr "op_type" "RIE")])
4237 (define_insn "*r<noxa>sbg_<mode>_srl_bitmask"
4238 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4242 (match_operand:GPR 1 "nonimmediate_operand" "d")
4243 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
4244 (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" ""))
4245 (match_operand:GPR 4 "nonimmediate_operand" "0")))
4246 (clobber (reg:CC CC_REGNUM))]
4248 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
4249 INTVAL (operands[2]))"
4250 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
4251 [(set_attr "op_type" "RIE")])
4254 (define_insn "*r<noxa>sbg_<mode>_sll_bitmask"
4255 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4259 (match_operand:GPR 1 "nonimmediate_operand" "d")
4260 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
4261 (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" ""))
4262 (match_operand:GPR 4 "nonimmediate_operand" "0")))
4263 (clobber (reg:CC CC_REGNUM))]
4265 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
4266 INTVAL (operands[2]))"
4267 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
4268 [(set_attr "op_type" "RIE")])
4270 ;; unsigned {int,long} a, b
4271 ;; a = a | (b << const_int)
4272 ;; a = a ^ (b << const_int)
4274 (define_insn "*r<noxa>sbg_<mode>_sll"
4275 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4278 (match_operand:GPR 1 "nonimmediate_operand" "d")
4279 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4280 (match_operand:GPR 3 "nonimmediate_operand" "0")))
4281 (clobber (reg:CC CC_REGNUM))]
4283 "r<noxa>sbg\t%0,%1,<bitoff>,63-%2,%2"
4284 [(set_attr "op_type" "RIE")])
4286 ;; unsigned {int,long} a, b
4287 ;; a = a | (b >> const_int)
4288 ;; a = a ^ (b >> const_int)
4290 (define_insn "*r<noxa>sbg_<mode>_srl"
4291 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4294 (match_operand:GPR 1 "nonimmediate_operand" "d")
4295 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4296 (match_operand:GPR 3 "nonimmediate_operand" "0")))
4297 (clobber (reg:CC CC_REGNUM))]
4299 "r<noxa>sbg\t%0,%1,<bitoff_plus>%2,63,64-%2"
4300 [(set_attr "op_type" "RIE")])
4302 ;; These two are generated by combine for s.bf &= val.
4303 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
4304 ;; shifts and ands, which results in some truly awful patterns
4305 ;; including subregs of operations. Rather unnecessisarily, IMO.
4308 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
4309 ;; (const_int 24 [0x18])
4310 ;; (const_int 0 [0]))
4311 ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
4312 ;; (const_int 40 [0x28])) 4)
4313 ;; (reg:SI 4 %r4 [ y+4 ])) 0))
4315 ;; we should instead generate
4317 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
4318 ;; (const_int 24 [0x18])
4319 ;; (const_int 0 [0]))
4320 ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
4321 ;; (const_int 40 [0x28]))
4322 ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
4324 ;; by noticing that we can push down the outer paradoxical subreg
4325 ;; into the operation.
4327 (define_insn "*insv_rnsbg_noshift"
4328 [(set (zero_extract:DI
4329 (match_operand:DI 0 "nonimmediate_operand" "+d")
4330 (match_operand 1 "const_int_operand" "")
4331 (match_operand 2 "const_int_operand" ""))
4334 (match_operand:DI 3 "nonimmediate_operand" "d")))
4335 (clobber (reg:CC CC_REGNUM))]
4337 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
4338 && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
4339 "rnsbg\t%0,%3,%2,63,0"
4340 [(set_attr "op_type" "RIE")])
4342 (define_insn "*insv_rnsbg_srl"
4343 [(set (zero_extract:DI
4344 (match_operand:DI 0 "nonimmediate_operand" "+d")
4345 (match_operand 1 "const_int_operand" "")
4346 (match_operand 2 "const_int_operand" ""))
4350 (match_operand 3 "const_int_operand" ""))
4351 (match_operand:DI 4 "nonimmediate_operand" "d")))
4352 (clobber (reg:CC CC_REGNUM))]
4354 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
4355 && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
4356 "rnsbg\t%0,%4,%2,%2+%1-1,%3"
4357 [(set_attr "op_type" "RIE")])
4359 (define_insn "*insv<mode>_mem_reg"
4360 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
4361 (match_operand 1 "const_int_operand" "n,n")
4363 (match_operand:W 2 "register_operand" "d,d"))]
4364 "EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64)
4365 && INTVAL (operands[1]) > 0
4366 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
4367 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
4369 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4371 operands[1] = GEN_INT ((1ul << size) - 1);
4372 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
4373 : "stcmy\t%2,%1,%S0";
4375 [(set_attr "op_type" "RS,RSY")
4376 (set_attr "cpu_facility" "*,longdisp")
4377 (set_attr "z10prop" "z10_super,z10_super")])
4379 (define_insn "*insvdi_mem_reghigh"
4380 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S")
4381 (match_operand 1 "const_int_operand" "n")
4383 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
4386 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64)
4387 && INTVAL (operands[1]) > 0
4388 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
4389 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
4391 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4393 operands[1] = GEN_INT ((1ul << size) - 1);
4394 return "stcmh\t%2,%1,%S0";
4396 [(set_attr "op_type" "RSY")
4397 (set_attr "z10prop" "z10_super")])
4399 (define_insn "*insvdi_reg_imm"
4400 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4402 (match_operand 1 "const_int_operand" "n"))
4403 (match_operand:DI 2 "const_int_operand" "n"))]
4405 && EXTRACT_ARGS_IN_RANGE (16, INTVAL (operands[1]), 64)
4406 && INTVAL (operands[1]) >= 0
4407 && INTVAL (operands[1]) < BITS_PER_WORD
4408 && INTVAL (operands[1]) % 16 == 0"
4410 switch (BITS_PER_WORD - INTVAL (operands[1]))
4412 case 64: return "iihh\t%0,%x2"; break;
4413 case 48: return "iihl\t%0,%x2"; break;
4414 case 32: return "iilh\t%0,%x2"; break;
4415 case 16: return "iill\t%0,%x2"; break;
4416 default: gcc_unreachable();
4419 [(set_attr "op_type" "RI")
4420 (set_attr "z10prop" "z10_super_E1")])
4422 ; Update the left-most 32 bit of a DI.
4423 (define_insn "*insv_h_di_reg_extimm"
4424 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4427 (match_operand:DI 1 "const_int_operand" "n"))]
4430 [(set_attr "op_type" "RIL")
4431 (set_attr "z10prop" "z10_fwd_E1")])
4433 ; Update the right-most 32 bit of a DI.
4434 (define_insn "*insv_l_di_reg_extimm"
4435 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4438 (match_operand:DI 1 "const_int_operand" "n"))]
4441 [(set_attr "op_type" "RIL")
4442 (set_attr "z10prop" "z10_fwd_A1")])
4445 ; extendsidi2 instruction pattern(s).
4448 (define_expand "extendsidi2"
4449 [(set (match_operand:DI 0 "register_operand" "")
4450 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4455 emit_clobber (operands[0]);
4456 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
4457 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
4458 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
4463 (define_insn "*extendsidi2"
4464 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4465 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))]
4471 [(set_attr "op_type" "RRE,RXY,RIL")
4472 (set_attr "type" "*,*,larl")
4473 (set_attr "cpu_facility" "*,*,z10")
4474 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4477 ; extend(hi|qi)(si|di)2 instruction pattern(s).
4480 (define_expand "extend<HQI:mode><DSI:mode>2"
4481 [(set (match_operand:DSI 0 "register_operand" "")
4482 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4485 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
4487 rtx tmp = gen_reg_rtx (SImode);
4488 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
4489 emit_insn (gen_extendsidi2 (operands[0], tmp));
4492 else if (!TARGET_EXTIMM)
4494 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
4496 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
4497 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
4498 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
4504 ; extendhidi2 instruction pattern(s).
4507 (define_insn "*extendhidi2_extimm"
4508 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4509 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))]
4510 "TARGET_ZARCH && TARGET_EXTIMM"
4515 [(set_attr "op_type" "RRE,RXY,RIL")
4516 (set_attr "type" "*,*,larl")
4517 (set_attr "cpu_facility" "extimm,extimm,z10")
4518 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4520 (define_insn "*extendhidi2"
4521 [(set (match_operand:DI 0 "register_operand" "=d")
4522 (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))]
4525 [(set_attr "op_type" "RXY")
4526 (set_attr "z10prop" "z10_super_E1")])
4529 ; extendhisi2 instruction pattern(s).
4532 (define_insn "*extendhisi2_extimm"
4533 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4534 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
4541 [(set_attr "op_type" "RRE,RX,RXY,RIL")
4542 (set_attr "type" "*,*,*,larl")
4543 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
4544 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
4546 (define_insn "*extendhisi2"
4547 [(set (match_operand:SI 0 "register_operand" "=d,d")
4548 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
4553 [(set_attr "op_type" "RX,RXY")
4554 (set_attr "cpu_facility" "*,longdisp")
4555 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4558 ; extendqi(si|di)2 instruction pattern(s).
4561 ; lbr, lgbr, lb, lgb
4562 (define_insn "*extendqi<mode>2_extimm"
4563 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4564 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))]
4569 [(set_attr "op_type" "RRE,RXY")
4570 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4573 (define_insn "*extendqi<mode>2"
4574 [(set (match_operand:GPR 0 "register_operand" "=d")
4575 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))]
4576 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
4578 [(set_attr "op_type" "RXY")
4579 (set_attr "z10prop" "z10_super_E1")])
4581 (define_insn_and_split "*extendqi<mode>2_short_displ"
4582 [(set (match_operand:GPR 0 "register_operand" "=d")
4583 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
4584 (clobber (reg:CC CC_REGNUM))]
4585 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
4587 "&& reload_completed"
4589 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
4590 (clobber (reg:CC CC_REGNUM))])
4592 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
4593 (clobber (reg:CC CC_REGNUM))])]
4595 operands[1] = adjust_address (operands[1], BLKmode, 0);
4596 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
4597 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
4601 ; zero_extendsidi2 instruction pattern(s).
4604 (define_expand "zero_extendsidi2"
4605 [(set (match_operand:DI 0 "register_operand" "")
4606 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4611 emit_clobber (operands[0]);
4612 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
4613 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
4618 (define_insn "*zero_extendsidi2"
4619 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4620 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))]
4626 [(set_attr "op_type" "RRE,RXY,RIL")
4627 (set_attr "type" "*,*,larl")
4628 (set_attr "cpu_facility" "*,*,z10")
4629 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
4632 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
4635 (define_insn "*llgt_sidi"
4636 [(set (match_operand:DI 0 "register_operand" "=d")
4637 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0)
4638 (const_int 2147483647)))]
4641 [(set_attr "op_type" "RXE")
4642 (set_attr "z10prop" "z10_super_E1")])
4644 (define_insn_and_split "*llgt_sidi_split"
4645 [(set (match_operand:DI 0 "register_operand" "=d")
4646 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0)
4647 (const_int 2147483647)))
4648 (clobber (reg:CC CC_REGNUM))]
4651 "&& reload_completed"
4653 (and:DI (subreg:DI (match_dup 1) 0)
4654 (const_int 2147483647)))]
4657 (define_insn "*llgt_sisi"
4658 [(set (match_operand:SI 0 "register_operand" "=d,d")
4659 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T")
4660 (const_int 2147483647)))]
4665 [(set_attr "op_type" "RRE,RXE")
4666 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4668 (define_insn "*llgt_didi"
4669 [(set (match_operand:DI 0 "register_operand" "=d,d")
4670 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
4671 (const_int 2147483647)))]
4676 [(set_attr "op_type" "RRE,RXE")
4677 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4680 [(set (match_operand:DSI 0 "register_operand" "")
4681 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
4682 (const_int 2147483647)))
4683 (clobber (reg:CC CC_REGNUM))]
4684 "TARGET_ZARCH && reload_completed"
4686 (and:DSI (match_dup 1)
4687 (const_int 2147483647)))]
4691 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
4694 (define_expand "zero_extend<mode>di2"
4695 [(set (match_operand:DI 0 "register_operand" "")
4696 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4701 rtx tmp = gen_reg_rtx (SImode);
4702 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
4703 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
4706 else if (!TARGET_EXTIMM)
4708 rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
4709 operands[1] = gen_lowpart (DImode, operands[1]);
4710 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
4711 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
4716 (define_expand "zero_extend<mode>si2"
4717 [(set (match_operand:SI 0 "register_operand" "")
4718 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4723 operands[1] = gen_lowpart (SImode, operands[1]);
4724 emit_insn (gen_andsi3 (operands[0], operands[1],
4725 GEN_INT ((1 << <HQI:bitsize>) - 1)));
4731 (define_insn "*zero_extendhi<mode>2_z10"
4732 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4733 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))]
4739 [(set_attr "op_type" "RXY,RRE,RIL")
4740 (set_attr "type" "*,*,larl")
4741 (set_attr "cpu_facility" "*,*,z10")
4742 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4744 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4745 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4746 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4747 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))]
4752 [(set_attr "op_type" "RRE,RXY")
4753 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4756 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4757 [(set (match_operand:GPR 0 "register_operand" "=d")
4758 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))]
4759 "TARGET_ZARCH && !TARGET_EXTIMM"
4761 [(set_attr "op_type" "RXY")
4762 (set_attr "z10prop" "z10_fwd_A3")])
4764 (define_insn_and_split "*zero_extendhisi2_31"
4765 [(set (match_operand:SI 0 "register_operand" "=&d")
4766 (zero_extend:SI (match_operand:HI 1 "s_operand" "S")))
4767 (clobber (reg:CC CC_REGNUM))]
4770 "&& reload_completed"
4771 [(set (match_dup 0) (const_int 0))
4773 [(set (strict_low_part (match_dup 2)) (match_dup 1))
4774 (clobber (reg:CC CC_REGNUM))])]
4775 "operands[2] = gen_lowpart (HImode, operands[0]);")
4777 (define_insn_and_split "*zero_extendqisi2_31"
4778 [(set (match_operand:SI 0 "register_operand" "=&d")
4779 (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))]
4782 "&& reload_completed"
4783 [(set (match_dup 0) (const_int 0))
4784 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4785 "operands[2] = gen_lowpart (QImode, operands[0]);")
4788 ; zero_extendqihi2 instruction pattern(s).
4791 (define_expand "zero_extendqihi2"
4792 [(set (match_operand:HI 0 "register_operand" "")
4793 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4794 "TARGET_ZARCH && !TARGET_EXTIMM"
4796 operands[1] = gen_lowpart (HImode, operands[1]);
4797 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4801 (define_insn "*zero_extendqihi2_64"
4802 [(set (match_operand:HI 0 "register_operand" "=d")
4803 (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))]
4804 "TARGET_ZARCH && !TARGET_EXTIMM"
4806 [(set_attr "op_type" "RXY")
4807 (set_attr "z10prop" "z10_fwd_A3")])
4809 (define_insn_and_split "*zero_extendqihi2_31"
4810 [(set (match_operand:HI 0 "register_operand" "=&d")
4811 (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))]
4814 "&& reload_completed"
4815 [(set (match_dup 0) (const_int 0))
4816 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4817 "operands[2] = gen_lowpart (QImode, operands[0]);")
4820 ; fixuns_trunc(dd|td|sf|df|tf)(si|di)2 expander
4823 ; This is the only entry point for fixuns_trunc. It multiplexes the
4824 ; expansion to either the *_emu expanders below for pre z196 machines
4825 ; or emits the default pattern otherwise.
4826 (define_expand "fixuns_trunc<FP:mode><GPR:mode>2"
4828 [(set (match_operand:GPR 0 "register_operand" "")
4829 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "")))
4830 (unspec:GPR [(match_dup 2)] UNSPEC_ROUND)
4831 (clobber (reg:CC CC_REGNUM))])]
4836 /* We don't provide emulation for TD|DD->SI. */
4837 if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT
4838 && <GPR:MODE>mode == SImode)
4840 emit_insn (gen_fixuns_trunc<FP:mode><GPR:mode>2_emu (operands[0],
4845 if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT)
4846 operands[2] = GEN_INT (DFP_RND_TOWARD_0);
4848 operands[2] = GEN_INT (BFP_RND_TOWARD_0);
4851 ; (sf|df|tf)->unsigned (si|di)
4853 ; Emulate the unsigned conversion with the signed version for pre z196
4855 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2_emu"
4857 [(set (match_operand:GPR 0 "register_operand" "")
4858 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4859 (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND)
4860 (clobber (reg:CC CC_REGNUM))])]
4861 "!TARGET_Z196 && TARGET_HARD_FLOAT"
4863 rtx_code_label *label1 = gen_label_rtx ();
4864 rtx_code_label *label2 = gen_label_rtx ();
4865 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4866 REAL_VALUE_TYPE cmp, sub;
4868 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4869 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4870 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4872 emit_cmp_and_jump_insns (operands[1],
4873 const_double_from_real_value (cmp, <BFP:MODE>mode),
4874 LT, NULL_RTX, VOIDmode, 0, label1);
4875 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4876 const_double_from_real_value (sub, <BFP:MODE>mode)));
4877 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4878 GEN_INT (BFP_RND_TOWARD_MINF)));
4881 emit_label (label1);
4882 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4884 GEN_INT (BFP_RND_TOWARD_0)));
4885 emit_label (label2);
4891 ; Emulate the unsigned conversion with the signed version for pre z196
4893 (define_expand "fixuns_truncdddi2_emu"
4895 [(set (match_operand:DI 0 "register_operand" "")
4896 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4897 (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
4898 (clobber (reg:CC CC_REGNUM))])]
4900 "!TARGET_Z196 && TARGET_HARD_DFP"
4902 rtx_code_label *label1 = gen_label_rtx ();
4903 rtx_code_label *label2 = gen_label_rtx ();
4904 rtx temp = gen_reg_rtx (TDmode);
4905 REAL_VALUE_TYPE cmp, sub;
4907 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4908 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4910 /* 2^63 can't be represented as 64bit DFP number with full precision. The
4911 solution is doing the check and the subtraction in TD mode and using a
4912 TD -> DI convert afterwards. */
4913 emit_insn (gen_extendddtd2 (temp, operands[1]));
4914 temp = force_reg (TDmode, temp);
4915 emit_cmp_and_jump_insns (temp,
4916 const_double_from_real_value (cmp, TDmode),
4917 LT, NULL_RTX, VOIDmode, 0, label1);
4918 emit_insn (gen_subtd3 (temp, temp,
4919 const_double_from_real_value (sub, TDmode)));
4920 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp,
4921 GEN_INT (DFP_RND_TOWARD_MINF)));
4924 emit_label (label1);
4925 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1],
4926 GEN_INT (DFP_RND_TOWARD_0)));
4927 emit_label (label2);
4933 ; Emulate the unsigned conversion with the signed version for pre z196
4935 (define_expand "fixuns_trunctddi2_emu"
4937 [(set (match_operand:DI 0 "register_operand" "")
4938 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4939 (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
4940 (clobber (reg:CC CC_REGNUM))])]
4942 "!TARGET_Z196 && TARGET_HARD_DFP"
4944 rtx_code_label *label1 = gen_label_rtx ();
4945 rtx_code_label *label2 = gen_label_rtx ();
4946 rtx temp = gen_reg_rtx (TDmode);
4947 REAL_VALUE_TYPE cmp, sub;
4949 operands[1] = force_reg (TDmode, operands[1]);
4950 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4951 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4953 emit_cmp_and_jump_insns (operands[1],
4954 const_double_from_real_value (cmp, TDmode),
4955 LT, NULL_RTX, VOIDmode, 0, label1);
4956 emit_insn (gen_subtd3 (temp, operands[1],
4957 const_double_from_real_value (sub, TDmode)));
4958 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp,
4959 GEN_INT (DFP_RND_TOWARD_MINF)));
4962 emit_label (label1);
4963 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1],
4964 GEN_INT (DFP_RND_TOWARD_0)));
4965 emit_label (label2);
4969 ; Just a dummy to make the code in the first expander a bit easier.
4970 (define_expand "fixuns_trunc<mode>si2_emu"
4972 [(set (match_operand:SI 0 "register_operand" "")
4973 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4974 (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
4975 (clobber (reg:CC CC_REGNUM))])]
4977 "!TARGET_Z196 && TARGET_HARD_DFP"
4983 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4986 (define_insn "*fixuns_truncdfdi2_vx"
4987 [(set (match_operand:DI 0 "register_operand" "=d,v")
4988 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v")))
4989 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4990 (clobber (reg:CC CC_REGNUM))]
4991 "TARGET_VX && TARGET_HARD_FLOAT"
4994 wclgdb\t%v0,%v1,0,%h2"
4995 [(set_attr "op_type" "RRF,VRR")
4996 (set_attr "type" "ftoi")])
4998 ; (dd|td|sf|df|tf)->unsigned (di|si)
4999 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
5000 ; clfdtr, clfxtr, clgdtr, clgxtr
5001 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
5002 [(set (match_operand:GPR 0 "register_operand" "=d")
5003 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
5004 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
5005 (clobber (reg:CC CC_REGNUM))]
5006 "TARGET_Z196 && TARGET_HARD_FLOAT
5007 && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)"
5008 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
5009 [(set_attr "op_type" "RRF")
5010 (set_attr "type" "ftoi")])
5012 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
5013 [(set (match_operand:GPR 0 "register_operand" "")
5014 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
5017 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
5018 GEN_INT (BFP_RND_TOWARD_0)));
5022 (define_insn "*fix_truncdfdi2_bfp_z13"
5023 [(set (match_operand:DI 0 "register_operand" "=d,v")
5024 (fix:DI (match_operand:DF 1 "register_operand" "f,v")))
5025 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
5026 (clobber (reg:CC CC_REGNUM))]
5027 "TARGET_VX && TARGET_HARD_FLOAT"
5030 wcgdb\t%v0,%v1,0,%h2"
5031 [(set_attr "op_type" "RRE,VRR")
5032 (set_attr "type" "ftoi")])
5034 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
5035 (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp"
5036 [(set (match_operand:GPR 0 "register_operand" "=d")
5037 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
5038 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
5039 (clobber (reg:CC CC_REGNUM))]
5041 && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)"
5042 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
5043 [(set_attr "op_type" "RRE")
5044 (set_attr "type" "ftoi")])
5046 (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp"
5048 [(set (match_operand:GPR 0 "register_operand" "=d")
5049 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
5050 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
5051 (clobber (reg:CC CC_REGNUM))])]
5052 "TARGET_HARD_FLOAT")
5054 ; fix_trunc(td|dd)di2 instruction pattern(s).
5057 (define_expand "fix_trunc<mode>di2"
5058 [(set (match_operand:DI 0 "register_operand" "")
5059 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
5060 "TARGET_ZARCH && TARGET_HARD_DFP"
5062 operands[1] = force_reg (<MODE>mode, operands[1]);
5063 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
5064 GEN_INT (DFP_RND_TOWARD_0)));
5069 (define_insn "fix_trunc<DFP:mode>di2_dfp"
5070 [(set (match_operand:DI 0 "register_operand" "=d")
5071 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
5072 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
5073 (clobber (reg:CC CC_REGNUM))]
5074 "TARGET_ZARCH && TARGET_HARD_DFP"
5075 "cg<DFP:xde>tr\t%0,%h2,%1"
5076 [(set_attr "op_type" "RRF")
5077 (set_attr "type" "ftoidfp")])
5081 ; fix_trunctf(si|di)2 instruction pattern(s).
5084 (define_expand "fix_trunctf<mode>2"
5085 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
5086 (fix:GPR (match_operand:TF 1 "register_operand" "")))
5087 (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND)
5088 (clobber (reg:CC CC_REGNUM))])]
5094 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
5097 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
5098 (define_insn "floatdi<mode>2"
5099 [(set (match_operand:FP 0 "register_operand" "=f,v")
5100 (float:FP (match_operand:DI 1 "register_operand" "d,v")))]
5101 "TARGET_ZARCH && TARGET_HARD_FLOAT"
5105 [(set_attr "op_type" "RRE,VRR")
5106 (set_attr "type" "itof<mode>" )
5107 (set_attr "cpu_facility" "*,vx")
5108 (set_attr "enabled" "*,<DFDI>")])
5110 ; cxfbr, cdfbr, cefbr
5111 (define_insn "floatsi<mode>2"
5112 [(set (match_operand:BFP 0 "register_operand" "=f")
5113 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
5116 [(set_attr "op_type" "RRE")
5117 (set_attr "type" "itof<mode>" )])
5120 (define_insn "floatsi<mode>2"
5121 [(set (match_operand:DFP 0 "register_operand" "=f")
5122 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
5123 "TARGET_Z196 && TARGET_HARD_FLOAT"
5124 "c<xde>ftr\t%0,0,%1,0"
5125 [(set_attr "op_type" "RRE")
5126 (set_attr "type" "itof<mode>" )])
5129 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
5132 (define_insn "*floatunsdidf2_z13"
5133 [(set (match_operand:DF 0 "register_operand" "=f,v")
5134 (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))]
5135 "TARGET_VX && TARGET_HARD_FLOAT"
5138 wcdlgb\t%v0,%v1,0,0"
5139 [(set_attr "op_type" "RRE,VRR")
5140 (set_attr "type" "itofdf")])
5142 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
5143 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
5144 (define_insn "*floatuns<GPR:mode><FP:mode>2"
5145 [(set (match_operand:FP 0 "register_operand" "=f")
5146 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
5147 "TARGET_Z196 && TARGET_HARD_FLOAT
5148 && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)"
5149 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
5150 [(set_attr "op_type" "RRE")
5151 (set_attr "type" "itof<FP:mode>")])
5153 (define_expand "floatuns<GPR:mode><FP:mode>2"
5154 [(set (match_operand:FP 0 "register_operand" "")
5155 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))]
5156 "TARGET_Z196 && TARGET_HARD_FLOAT")
5159 ; truncdfsf2 instruction pattern(s).
5162 (define_insn "truncdfsf2"
5163 [(set (match_operand:SF 0 "register_operand" "=f,v")
5164 (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))]
5168 wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed
5169 ; According to BFP rounding mode
5170 [(set_attr "op_type" "RRE,VRR")
5171 (set_attr "type" "ftruncdf")
5172 (set_attr "cpu_facility" "*,vx")])
5175 ; trunctf(df|sf)2 instruction pattern(s).
5179 (define_insn "trunctf<mode>2"
5180 [(set (match_operand:DSF 0 "register_operand" "=f")
5181 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
5182 (clobber (match_scratch:TF 2 "=f"))]
5184 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
5185 [(set_attr "length" "6")
5186 (set_attr "type" "ftrunctf")])
5189 ; trunctddd2 and truncddsd2 instruction pattern(s).
5193 (define_expand "trunctddd2"
5195 [(set (match_operand:DD 0 "register_operand" "")
5196 (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
5197 (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND)
5198 (clobber (scratch:TD))])]
5201 (define_insn "*trunctddd2"
5202 [(set (match_operand:DD 0 "register_operand" "=f")
5203 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
5204 (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND)
5205 (clobber (match_scratch:TD 3 "=f"))]
5207 "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3"
5208 [(set_attr "length" "6")
5209 (set_attr "type" "ftruncdd")])
5211 (define_insn "truncddsd2"
5212 [(set (match_operand:SD 0 "register_operand" "=f")
5213 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
5216 [(set_attr "op_type" "RRF")
5217 (set_attr "type" "ftruncsd")])
5219 (define_expand "trunctdsd2"
5222 (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
5223 (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND)
5224 (clobber (match_scratch:TD 3 ""))])
5225 (set (match_operand:SD 0 "register_operand" "")
5226 (float_truncate:SD (match_dup 2)))]
5229 operands[2] = gen_reg_rtx (DDmode);
5233 ; extend(sf|df)(df|tf)2 instruction pattern(s).
5237 (define_insn "*extendsfdf2_z13"
5238 [(set (match_operand:DF 0 "register_operand" "=f,f,v")
5239 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))]
5240 "TARGET_VX && TARGET_HARD_FLOAT"
5245 [(set_attr "op_type" "RRE,RXE,VRR")
5246 (set_attr "type" "fsimpdf, floaddf,fsimpdf")])
5248 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
5249 (define_insn "*extend<DSF:mode><BFP:mode>2"
5250 [(set (match_operand:BFP 0 "register_operand" "=f,f")
5251 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
5253 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)
5254 && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)"
5256 l<BFP:xde><DSF:xde>br\t%0,%1
5257 l<BFP:xde><DSF:xde>b\t%0,%1"
5258 [(set_attr "op_type" "RRE,RXE")
5259 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
5261 (define_expand "extend<DSF:mode><BFP:mode>2"
5262 [(set (match_operand:BFP 0 "register_operand" "")
5263 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))]
5265 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)")
5268 ; extendddtd2 and extendsddd2 instruction pattern(s).
5271 (define_insn "extendddtd2"
5272 [(set (match_operand:TD 0 "register_operand" "=f")
5273 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
5276 [(set_attr "op_type" "RRF")
5277 (set_attr "type" "fsimptf")])
5279 (define_insn "extendsddd2"
5280 [(set (match_operand:DD 0 "register_operand" "=f")
5281 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
5284 [(set_attr "op_type" "RRF")
5285 (set_attr "type" "fsimptf")])
5287 (define_expand "extendsdtd2"
5289 (float_extend:DD (match_operand:SD 1 "register_operand" "")))
5290 (set (match_operand:TD 0 "register_operand" "")
5291 (float_extend:TD (match_dup 2)))]
5294 operands[2] = gen_reg_rtx (DDmode);
5297 ; Binary Floating Point - load fp integer
5299 ; Expanders for: floor, btrunc, round, ceil, and nearbyint
5300 ; For all of them the inexact exceptions are suppressed.
5302 ; fiebra, fidbra, fixbra
5303 (define_insn "<FPINT:fpint_name><BFP:mode>2"
5304 [(set (match_operand:BFP 0 "register_operand" "=f")
5305 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
5308 "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4"
5309 [(set_attr "op_type" "RRF")
5310 (set_attr "type" "fsimp<BFP:mode>")])
5312 ; rint is supposed to raise an inexact exception so we can use the
5313 ; older instructions.
5315 ; fiebr, fidbr, fixbr
5316 (define_insn "rint<BFP:mode>2"
5317 [(set (match_operand:BFP 0 "register_operand" "=f")
5318 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
5319 UNSPEC_FPINT_RINT))]
5321 "fi<BFP:xde>br\t%0,0,%1"
5322 [(set_attr "op_type" "RRF")
5323 (set_attr "type" "fsimp<BFP:mode>")])
5326 ; Decimal Floating Point - load fp integer
5329 (define_insn "<FPINT:fpint_name><DFP:mode>2"
5330 [(set (match_operand:DFP 0 "register_operand" "=f")
5331 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
5334 "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4"
5335 [(set_attr "op_type" "RRF")
5336 (set_attr "type" "fsimp<DFP:mode>")])
5339 (define_insn "rint<DFP:mode>2"
5340 [(set (match_operand:DFP 0 "register_operand" "=f")
5341 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
5342 UNSPEC_FPINT_RINT))]
5344 "fi<DFP:xde>tr\t%0,0,%1,0"
5345 [(set_attr "op_type" "RRF")
5346 (set_attr "type" "fsimp<DFP:mode>")])
5349 ; Binary <-> Decimal floating point trunc patterns
5352 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
5353 [(set (reg:DFP_ALL FPR0_REGNUM)
5354 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
5355 (use (reg:SI GPR0_REGNUM))
5356 (clobber (reg:CC CC_REGNUM))
5357 (clobber (reg:SI GPR1_REGNUM))]
5361 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
5362 [(set (reg:BFP FPR0_REGNUM)
5363 (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
5364 (use (reg:SI GPR0_REGNUM))
5365 (clobber (reg:CC CC_REGNUM))
5366 (clobber (reg:SI GPR1_REGNUM))]
5370 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
5371 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
5372 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5374 [(set (reg:DFP_ALL FPR0_REGNUM)
5375 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
5376 (use (reg:SI GPR0_REGNUM))
5377 (clobber (reg:CC CC_REGNUM))
5378 (clobber (reg:SI GPR1_REGNUM))])
5379 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
5380 (reg:DFP_ALL FPR0_REGNUM))]
5382 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
5384 HOST_WIDE_INT flags;
5386 /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the
5387 rounding mode of the target format needs to be used. */
5389 flags = (PFPO_CONVERT |
5390 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
5391 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT |
5394 operands[2] = GEN_INT (flags);
5397 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
5398 [(set (reg:DFP_ALL FPR4_REGNUM)
5399 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5400 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5402 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
5403 (use (reg:SI GPR0_REGNUM))
5404 (clobber (reg:CC CC_REGNUM))
5405 (clobber (reg:SI GPR1_REGNUM))])
5406 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5408 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
5410 HOST_WIDE_INT flags;
5412 /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the
5413 rounding mode of the target format needs to be used. */
5415 flags = (PFPO_CONVERT |
5416 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5417 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT |
5420 operands[2] = GEN_INT (flags);
5424 ; Binary <-> Decimal floating point extend patterns
5427 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
5428 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
5429 (use (reg:SI GPR0_REGNUM))
5430 (clobber (reg:CC CC_REGNUM))
5431 (clobber (reg:SI GPR1_REGNUM))]
5435 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
5436 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5437 (use (reg:SI GPR0_REGNUM))
5438 (clobber (reg:CC CC_REGNUM))
5439 (clobber (reg:SI GPR1_REGNUM))]
5443 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
5444 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
5445 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5447 [(set (reg:DFP_ALL FPR0_REGNUM)
5448 (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
5449 (use (reg:SI GPR0_REGNUM))
5450 (clobber (reg:CC CC_REGNUM))
5451 (clobber (reg:SI GPR1_REGNUM))])
5452 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
5453 (reg:DFP_ALL FPR0_REGNUM))]
5455 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
5457 HOST_WIDE_INT flags;
5459 /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the
5460 rounding mode of the target format needs to be used. */
5462 flags = (PFPO_CONVERT |
5463 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
5464 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT |
5467 operands[2] = GEN_INT (flags);
5470 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
5471 [(set (reg:DFP_ALL FPR4_REGNUM)
5472 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5473 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5475 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5476 (use (reg:SI GPR0_REGNUM))
5477 (clobber (reg:CC CC_REGNUM))
5478 (clobber (reg:SI GPR1_REGNUM))])
5479 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5481 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
5483 HOST_WIDE_INT flags;
5485 /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the
5486 rounding mode of the target format needs to be used. */
5488 flags = (PFPO_CONVERT |
5489 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5490 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT |
5493 operands[2] = GEN_INT (flags);
5498 ;; ARITHMETIC OPERATIONS
5500 ; arithmetic operations set the ConditionCode,
5501 ; because of unpredictable Bits in Register for Halfword and Byte
5502 ; the ConditionCode can be set wrong in operations for Halfword and Byte
5505 ;;- Add instructions.
5509 ; addti3 instruction pattern(s).
5512 (define_expand "addti3"
5514 [(set (match_operand:TI 0 "register_operand" "")
5515 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
5516 (match_operand:TI 2 "general_operand" "") ) )
5517 (clobber (reg:CC CC_REGNUM))])]
5520 /* For z13 we have vaq which doesn't set CC. */
5523 emit_insn (gen_rtx_SET (operands[0],
5524 gen_rtx_PLUS (TImode,
5525 copy_to_mode_reg (TImode, operands[1]),
5526 copy_to_mode_reg (TImode, operands[2]))));
5531 (define_insn_and_split "*addti3"
5532 [(set (match_operand:TI 0 "register_operand" "=&d")
5533 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
5534 (match_operand:TI 2 "general_operand" "do") ) )
5535 (clobber (reg:CC CC_REGNUM))]
5538 "&& reload_completed"
5540 [(set (reg:CCL1 CC_REGNUM)
5541 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
5543 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
5545 [(set (match_dup 3) (plus:DI
5546 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
5547 (match_dup 4)) (match_dup 5)))
5548 (clobber (reg:CC CC_REGNUM))])]
5549 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5550 operands[4] = operand_subword (operands[1], 0, 0, TImode);
5551 operands[5] = operand_subword (operands[2], 0, 0, TImode);
5552 operands[6] = operand_subword (operands[0], 1, 0, TImode);
5553 operands[7] = operand_subword (operands[1], 1, 0, TImode);
5554 operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5555 [(set_attr "op_type" "*")
5556 (set_attr "cpu_facility" "*")])
5559 ; adddi3 instruction pattern(s).
5562 (define_expand "adddi3"
5564 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5565 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5566 (match_operand:DI 2 "general_operand" "")))
5567 (clobber (reg:CC CC_REGNUM))])]
5571 (define_insn "*adddi3_sign"
5572 [(set (match_operand:DI 0 "register_operand" "=d,d")
5573 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5574 (match_operand:DI 1 "register_operand" "0,0")))
5575 (clobber (reg:CC CC_REGNUM))]
5580 [(set_attr "op_type" "RRE,RXY")
5581 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5583 (define_insn "*adddi3_zero_cc"
5584 [(set (reg CC_REGNUM)
5585 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5586 (match_operand:DI 1 "register_operand" "0,0"))
5588 (set (match_operand:DI 0 "register_operand" "=d,d")
5589 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
5590 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5594 [(set_attr "op_type" "RRE,RXY")
5595 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5597 (define_insn "*adddi3_zero_cconly"
5598 [(set (reg CC_REGNUM)
5599 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5600 (match_operand:DI 1 "register_operand" "0,0"))
5602 (clobber (match_scratch:DI 0 "=d,d"))]
5603 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5607 [(set_attr "op_type" "RRE,RXY")
5608 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5610 (define_insn "*adddi3_zero"
5611 [(set (match_operand:DI 0 "register_operand" "=d,d")
5612 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5613 (match_operand:DI 1 "register_operand" "0,0")))
5614 (clobber (reg:CC CC_REGNUM))]
5619 [(set_attr "op_type" "RRE,RXY")
5620 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5622 (define_insn_and_split "*adddi3_31z"
5623 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5624 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5625 (match_operand:DI 2 "general_operand" "do") ) )
5626 (clobber (reg:CC CC_REGNUM))]
5629 "&& reload_completed"
5631 [(set (reg:CCL1 CC_REGNUM)
5632 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5634 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5636 [(set (match_dup 3) (plus:SI
5637 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
5638 (match_dup 4)) (match_dup 5)))
5639 (clobber (reg:CC CC_REGNUM))])]
5640 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5641 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5642 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5643 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5644 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5645 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5648 ; addsi3 instruction pattern(s).
5651 (define_expand "addsi3"
5653 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5654 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5655 (match_operand:SI 2 "general_operand" "")))
5656 (clobber (reg:CC CC_REGNUM))])]
5660 (define_insn "*addsi3_sign"
5661 [(set (match_operand:SI 0 "register_operand" "=d,d")
5662 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5663 (match_operand:SI 1 "register_operand" "0,0")))
5664 (clobber (reg:CC CC_REGNUM))]
5669 [(set_attr "op_type" "RX,RXY")
5670 (set_attr "cpu_facility" "*,longdisp")
5671 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5674 ; add(di|si)3 instruction pattern(s).
5677 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
5678 (define_insn "*add<mode>3"
5679 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S")
5680 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0")
5681 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) )
5682 (clobber (reg:CC CC_REGNUM))]
5694 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
5695 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10")
5696 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
5697 z10_super_E1,z10_super_E1,z10_super_E1")])
5699 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
5700 (define_insn "*add<mode>3_carry1_cc"
5701 [(set (reg CC_REGNUM)
5702 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5703 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
5705 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
5706 (plus:GPR (match_dup 1) (match_dup 2)))]
5707 "s390_match_ccmode (insn, CCL1mode)"
5713 al<g>hsik\t%0,%1,%h2
5717 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5718 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
5719 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5720 z10_super_E1,z10_super_E1,z10_super_E1")])
5722 ; alr, al, aly, algr, alg, alrk, algrk
5723 (define_insn "*add<mode>3_carry1_cconly"
5724 [(set (reg CC_REGNUM)
5725 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5726 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5728 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5729 "s390_match_ccmode (insn, CCL1mode)"
5735 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5736 (set_attr "cpu_facility" "*,z196,*,longdisp")
5737 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5739 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5740 (define_insn "*add<mode>3_carry2_cc"
5741 [(set (reg CC_REGNUM)
5742 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5743 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
5745 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S")
5746 (plus:GPR (match_dup 1) (match_dup 2)))]
5747 "s390_match_ccmode (insn, CCL1mode)"
5753 al<g>hsik\t%0,%1,%h2
5757 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5758 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
5759 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5760 z10_super_E1,z10_super_E1,z10_super_E1")])
5762 ; alr, al, aly, algr, alg, alrk, algrk
5763 (define_insn "*add<mode>3_carry2_cconly"
5764 [(set (reg CC_REGNUM)
5765 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5766 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5768 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5769 "s390_match_ccmode (insn, CCL1mode)"
5775 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5776 (set_attr "cpu_facility" "*,z196,*,longdisp")
5777 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5779 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5780 (define_insn "*add<mode>3_cc"
5781 [(set (reg CC_REGNUM)
5782 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5783 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
5785 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S")
5786 (plus:GPR (match_dup 1) (match_dup 2)))]
5787 "s390_match_ccmode (insn, CCLmode)"
5793 al<g>hsik\t%0,%1,%h2
5797 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5798 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
5799 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
5800 *,z10_super_E1,z10_super_E1,z10_super_E1")])
5802 ; alr, al, aly, algr, alg, alrk, algrk
5803 (define_insn "*add<mode>3_cconly"
5804 [(set (reg CC_REGNUM)
5805 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5806 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5808 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5809 "s390_match_ccmode (insn, CCLmode)"
5815 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5816 (set_attr "cpu_facility" "*,z196,*,longdisp")
5817 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5819 ; alr, al, aly, algr, alg, alrk, algrk
5820 (define_insn "*add<mode>3_cconly2"
5821 [(set (reg CC_REGNUM)
5822 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5823 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
5824 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5825 "s390_match_ccmode(insn, CCLmode)"
5831 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5832 (set_attr "cpu_facility" "*,z196,*,longdisp")
5833 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5835 ; ahi, afi, aghi, agfi, asi, agsi
5836 (define_insn "*add<mode>3_imm_cc"
5837 [(set (reg CC_REGNUM)
5838 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
5839 (match_operand:GPR 2 "const_int_operand" " K, K,Os,C"))
5841 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S")
5842 (plus:GPR (match_dup 1) (match_dup 2)))]
5843 "s390_match_ccmode (insn, CCAmode)
5844 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
5845 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
5846 /* Avoid INT32_MIN on 32 bit. */
5847 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
5853 [(set_attr "op_type" "RI,RIE,RIL,SIY")
5854 (set_attr "cpu_facility" "*,z196,extimm,z10")
5855 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5857 (define_insn "*adddi3_sign"
5858 [(set (match_operand:DI 0 "register_operand" "=d")
5859 (plus:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T"))
5860 (match_operand:DI 1 "register_operand" "0")))
5861 (clobber (reg:CC CC_REGNUM))]
5864 [(set_attr "op_type" "RXY")])
5867 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
5870 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5871 ; FIXME: wfadb does not clobber cc
5872 (define_insn "add<mode>3"
5873 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v")
5874 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v")
5875 (match_operand:FP 2 "general_operand" "f,f,R,v,v")))
5876 (clobber (reg:CC CC_REGNUM))]
5884 [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR")
5885 (set_attr "type" "fsimp<mode>")
5886 (set_attr "cpu_facility" "*,*,*,vx,vxe")
5887 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")])
5889 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5890 (define_insn "*add<mode>3_cc"
5891 [(set (reg CC_REGNUM)
5892 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
5893 (match_operand:FP 2 "general_operand" "f,f,R"))
5894 (match_operand:FP 3 "const0_operand" "")))
5895 (set (match_operand:FP 0 "register_operand" "=f,f,f")
5896 (plus:FP (match_dup 1) (match_dup 2)))]
5897 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5902 [(set_attr "op_type" "RRF,RRE,RXE")
5903 (set_attr "type" "fsimp<mode>")
5904 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
5906 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5907 (define_insn "*add<mode>3_cconly"
5908 [(set (reg CC_REGNUM)
5909 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
5910 (match_operand:FP 2 "general_operand" "f,f,R"))
5911 (match_operand:FP 3 "const0_operand" "")))
5912 (clobber (match_scratch:FP 0 "=f,f,f"))]
5913 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5918 [(set_attr "op_type" "RRF,RRE,RXE")
5919 (set_attr "type" "fsimp<mode>")
5920 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
5923 ; Pointer add instruction patterns
5926 ; This will match "*la_64"
5927 (define_expand "addptrdi3"
5928 [(set (match_operand:DI 0 "register_operand" "")
5929 (plus:DI (match_operand:DI 1 "register_operand" "")
5930 (match_operand:DI 2 "nonmemory_operand" "")))]
5933 if (GET_CODE (operands[2]) == CONST_INT)
5935 HOST_WIDE_INT c = INTVAL (operands[2]);
5937 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5938 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5940 operands[2] = force_const_mem (DImode, operands[2]);
5941 operands[2] = force_reg (DImode, operands[2]);
5943 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5944 operands[2] = force_reg (DImode, operands[2]);
5948 ; For 31 bit we have to prevent the generated pattern from matching
5949 ; normal ADDs since la only does a 31 bit add. This is supposed to
5950 ; match "force_la_31".
5951 (define_expand "addptrsi3"
5953 [(set (match_operand:SI 0 "register_operand" "")
5954 (plus:SI (match_operand:SI 1 "register_operand" "")
5955 (match_operand:SI 2 "nonmemory_operand" "")))
5956 (use (const_int 0))])]
5959 if (GET_CODE (operands[2]) == CONST_INT)
5961 HOST_WIDE_INT c = INTVAL (operands[2]);
5963 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5964 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5966 operands[2] = force_const_mem (SImode, operands[2]);
5967 operands[2] = force_reg (SImode, operands[2]);
5969 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5970 operands[2] = force_reg (SImode, operands[2]);
5975 ;;- Subtract instructions.
5979 ; subti3 instruction pattern(s).
5982 (define_expand "subti3"
5984 [(set (match_operand:TI 0 "register_operand" "")
5985 (minus:TI (match_operand:TI 1 "register_operand" "")
5986 (match_operand:TI 2 "general_operand" "") ) )
5987 (clobber (reg:CC CC_REGNUM))])]
5990 /* For z13 we have vsq which doesn't set CC. */
5993 emit_insn (gen_rtx_SET (operands[0],
5994 gen_rtx_MINUS (TImode,
5996 copy_to_mode_reg (TImode, operands[2]))));
6001 (define_insn_and_split "*subti3"
6002 [(set (match_operand:TI 0 "register_operand" "=&d")
6003 (minus:TI (match_operand:TI 1 "register_operand" "0")
6004 (match_operand:TI 2 "general_operand" "do") ) )
6005 (clobber (reg:CC CC_REGNUM))]
6008 "&& reload_completed"
6010 [(set (reg:CCL2 CC_REGNUM)
6011 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
6013 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
6015 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
6016 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
6017 (clobber (reg:CC CC_REGNUM))])]
6018 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
6019 operands[4] = operand_subword (operands[1], 0, 0, TImode);
6020 operands[5] = operand_subword (operands[2], 0, 0, TImode);
6021 operands[6] = operand_subword (operands[0], 1, 0, TImode);
6022 operands[7] = operand_subword (operands[1], 1, 0, TImode);
6023 operands[8] = operand_subword (operands[2], 1, 0, TImode);"
6024 [(set_attr "op_type" "*")
6025 (set_attr "cpu_facility" "*")])
6028 ; subdi3 instruction pattern(s).
6031 (define_expand "subdi3"
6033 [(set (match_operand:DI 0 "register_operand" "")
6034 (minus:DI (match_operand:DI 1 "register_operand" "")
6035 (match_operand:DI 2 "general_operand" "")))
6036 (clobber (reg:CC CC_REGNUM))])]
6040 (define_insn "*subdi3_sign"
6041 [(set (match_operand:DI 0 "register_operand" "=d,d")
6042 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
6043 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))))
6044 (clobber (reg:CC CC_REGNUM))]
6049 [(set_attr "op_type" "RRE,RXY")
6050 (set_attr "z10prop" "z10_c,*")
6051 (set_attr "z196prop" "z196_cracked")])
6053 (define_insn "*subdi3_zero_cc"
6054 [(set (reg CC_REGNUM)
6055 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
6056 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))
6058 (set (match_operand:DI 0 "register_operand" "=d,d")
6059 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
6060 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
6064 [(set_attr "op_type" "RRE,RXY")
6065 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
6067 (define_insn "*subdi3_zero_cconly"
6068 [(set (reg CC_REGNUM)
6069 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
6070 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))
6072 (clobber (match_scratch:DI 0 "=d,d"))]
6073 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
6077 [(set_attr "op_type" "RRE,RXY")
6078 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
6080 (define_insn "*subdi3_zero"
6081 [(set (match_operand:DI 0 "register_operand" "=d,d")
6082 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
6083 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))))
6084 (clobber (reg:CC CC_REGNUM))]
6089 [(set_attr "op_type" "RRE,RXY")
6090 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
6092 (define_insn_and_split "*subdi3_31z"
6093 [(set (match_operand:DI 0 "register_operand" "=&d")
6094 (minus:DI (match_operand:DI 1 "register_operand" "0")
6095 (match_operand:DI 2 "general_operand" "do") ) )
6096 (clobber (reg:CC CC_REGNUM))]
6099 "&& reload_completed"
6101 [(set (reg:CCL2 CC_REGNUM)
6102 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
6104 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
6106 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
6107 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
6108 (clobber (reg:CC CC_REGNUM))])]
6109 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
6110 operands[4] = operand_subword (operands[1], 0, 0, DImode);
6111 operands[5] = operand_subword (operands[2], 0, 0, DImode);
6112 operands[6] = operand_subword (operands[0], 1, 0, DImode);
6113 operands[7] = operand_subword (operands[1], 1, 0, DImode);
6114 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
6117 ; subsi3 instruction pattern(s).
6120 (define_expand "subsi3"
6122 [(set (match_operand:SI 0 "register_operand" "")
6123 (minus:SI (match_operand:SI 1 "register_operand" "")
6124 (match_operand:SI 2 "general_operand" "")))
6125 (clobber (reg:CC CC_REGNUM))])]
6129 (define_insn "*subsi3_sign"
6130 [(set (match_operand:SI 0 "register_operand" "=d,d")
6131 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6132 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
6133 (clobber (reg:CC CC_REGNUM))]
6138 [(set_attr "op_type" "RX,RXY")
6139 (set_attr "cpu_facility" "*,longdisp")
6140 (set_attr "z196prop" "z196_cracked,z196_cracked")])
6143 ; sub(di|si)3 instruction pattern(s).
6146 ; sr, s, sy, sgr, sg, srk, sgrk
6147 (define_insn "*sub<mode>3"
6148 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
6149 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6150 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
6151 (clobber (reg:CC CC_REGNUM))]
6158 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6159 (set_attr "cpu_facility" "*,z196,*,longdisp")
6160 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6162 ; slr, sl, sly, slgr, slg, slrk, slgrk
6163 (define_insn "*sub<mode>3_borrow_cc"
6164 [(set (reg CC_REGNUM)
6165 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6166 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
6168 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
6169 (minus:GPR (match_dup 1) (match_dup 2)))]
6170 "s390_match_ccmode (insn, CCL2mode)"
6176 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6177 (set_attr "cpu_facility" "*,z196,*,longdisp")
6178 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6180 ; slr, sl, sly, slgr, slg, slrk, slgrk
6181 (define_insn "*sub<mode>3_borrow_cconly"
6182 [(set (reg CC_REGNUM)
6183 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6184 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
6186 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
6187 "s390_match_ccmode (insn, CCL2mode)"
6193 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6194 (set_attr "cpu_facility" "*,z196,*,longdisp")
6195 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6197 ; slr, sl, sly, slgr, slg, slrk, slgrk
6198 (define_insn "*sub<mode>3_cc"
6199 [(set (reg CC_REGNUM)
6200 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6201 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
6203 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
6204 (minus:GPR (match_dup 1) (match_dup 2)))]
6205 "s390_match_ccmode (insn, CCLmode)"
6211 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6212 (set_attr "cpu_facility" "*,z196,*,longdisp")
6213 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6215 ; slr, sl, sly, slgr, slg, slrk, slgrk
6216 (define_insn "*sub<mode>3_cc2"
6217 [(set (reg CC_REGNUM)
6218 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
6219 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
6220 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
6221 (minus:GPR (match_dup 1) (match_dup 2)))]
6222 "s390_match_ccmode (insn, CCL3mode)"
6228 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6229 (set_attr "cpu_facility" "*,z196,*,longdisp")
6230 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6232 ; slr, sl, sly, slgr, slg, slrk, slgrk
6233 (define_insn "*sub<mode>3_cconly"
6234 [(set (reg CC_REGNUM)
6235 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6236 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
6238 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
6239 "s390_match_ccmode (insn, CCLmode)"
6245 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6246 (set_attr "cpu_facility" "*,z196,*,longdisp")
6247 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6250 ; slr, sl, sly, slgr, slg, slrk, slgrk
6251 (define_insn "*sub<mode>3_cconly2"
6252 [(set (reg CC_REGNUM)
6253 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
6254 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
6255 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
6256 "s390_match_ccmode (insn, CCL3mode)"
6262 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6263 (set_attr "cpu_facility" "*,z196,*,longdisp")
6264 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6266 (define_insn "*subdi3_sign"
6267 [(set (match_operand:DI 0 "register_operand" "=d")
6268 (minus:DI (match_operand:DI 1 "register_operand" "0")
6269 (sign_extend:DI (match_operand:HI 2 "memory_operand" "T"))))
6270 (clobber (reg:CC CC_REGNUM))]
6273 [(set_attr "op_type" "RXY")])
6277 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
6280 ; FIXME: (clobber (match_scratch:CC 3 "=c,c,c,X,X")) does not work - why?
6281 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
6282 (define_insn "sub<mode>3"
6283 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v")
6284 (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v")
6285 (match_operand:FP 2 "general_operand" "f,f,R,v,v")))
6286 (clobber (reg:CC CC_REGNUM))]
6294 [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR")
6295 (set_attr "type" "fsimp<mode>")
6296 (set_attr "cpu_facility" "*,*,*,vx,vxe")
6297 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")])
6299 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
6300 (define_insn "*sub<mode>3_cc"
6301 [(set (reg CC_REGNUM)
6302 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
6303 (match_operand:FP 2 "general_operand" "f,f,R"))
6304 (match_operand:FP 3 "const0_operand" "")))
6305 (set (match_operand:FP 0 "register_operand" "=f,f,f")
6306 (minus:FP (match_dup 1) (match_dup 2)))]
6307 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6312 [(set_attr "op_type" "RRF,RRE,RXE")
6313 (set_attr "type" "fsimp<mode>")
6314 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
6316 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
6317 (define_insn "*sub<mode>3_cconly"
6318 [(set (reg CC_REGNUM)
6319 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
6320 (match_operand:FP 2 "general_operand" "f,f,R"))
6321 (match_operand:FP 3 "const0_operand" "")))
6322 (clobber (match_scratch:FP 0 "=f,f,f"))]
6323 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6328 [(set_attr "op_type" "RRF,RRE,RXE")
6329 (set_attr "type" "fsimp<mode>")
6330 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
6334 ;;- Conditional add/subtract instructions.
6338 ; add(di|si)cc instruction pattern(s).
6341 ; the following 4 patterns are used when the result of an add with
6342 ; carry is checked for an overflow condition
6344 ; op1 + op2 + c < op1
6346 ; alcr, alc, alcgr, alcg
6347 (define_insn "*add<mode>3_alc_carry1_cc"
6348 [(set (reg CC_REGNUM)
6350 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6351 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6352 (match_operand:GPR 2 "general_operand" "d,T"))
6354 (set (match_operand:GPR 0 "register_operand" "=d,d")
6355 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6356 "s390_match_ccmode (insn, CCL1mode)"
6360 [(set_attr "op_type" "RRE,RXY")
6361 (set_attr "z196prop" "z196_alone,z196_alone")])
6363 ; alcr, alc, alcgr, alcg
6364 (define_insn "*add<mode>3_alc_carry1_cconly"
6365 [(set (reg CC_REGNUM)
6367 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6368 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6369 (match_operand:GPR 2 "general_operand" "d,T"))
6371 (clobber (match_scratch:GPR 0 "=d,d"))]
6372 "s390_match_ccmode (insn, CCL1mode)"
6376 [(set_attr "op_type" "RRE,RXY")
6377 (set_attr "z196prop" "z196_alone,z196_alone")])
6379 ; op1 + op2 + c < op2
6381 ; alcr, alc, alcgr, alcg
6382 (define_insn "*add<mode>3_alc_carry2_cc"
6383 [(set (reg CC_REGNUM)
6385 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6386 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6387 (match_operand:GPR 2 "general_operand" "d,T"))
6389 (set (match_operand:GPR 0 "register_operand" "=d,d")
6390 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6391 "s390_match_ccmode (insn, CCL1mode)"
6395 [(set_attr "op_type" "RRE,RXY")])
6397 ; alcr, alc, alcgr, alcg
6398 (define_insn "*add<mode>3_alc_carry2_cconly"
6399 [(set (reg CC_REGNUM)
6401 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6402 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6403 (match_operand:GPR 2 "general_operand" "d,T"))
6405 (clobber (match_scratch:GPR 0 "=d,d"))]
6406 "s390_match_ccmode (insn, CCL1mode)"
6410 [(set_attr "op_type" "RRE,RXY")])
6412 ; alcr, alc, alcgr, alcg
6413 (define_insn "*add<mode>3_alc_cc"
6414 [(set (reg CC_REGNUM)
6416 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6417 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6418 (match_operand:GPR 2 "general_operand" "d,T"))
6420 (set (match_operand:GPR 0 "register_operand" "=d,d")
6421 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6422 "s390_match_ccmode (insn, CCLmode)"
6426 [(set_attr "op_type" "RRE,RXY")])
6428 ; alcr, alc, alcgr, alcg
6429 (define_insn "*add<mode>3_alc"
6430 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6431 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6432 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6433 (match_operand:GPR 2 "general_operand" "d,T")))
6434 (clobber (reg:CC CC_REGNUM))]
6439 [(set_attr "op_type" "RRE,RXY")])
6441 ; slbr, slb, slbgr, slbg
6442 (define_insn "*sub<mode>3_slb_cc"
6443 [(set (reg CC_REGNUM)
6445 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6446 (match_operand:GPR 2 "general_operand" "d,T"))
6447 (match_operand:GPR 3 "s390_slb_comparison" ""))
6449 (set (match_operand:GPR 0 "register_operand" "=d,d")
6450 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
6451 "s390_match_ccmode (insn, CCLmode)"
6455 [(set_attr "op_type" "RRE,RXY")
6456 (set_attr "z10prop" "z10_c,*")])
6458 ; slbr, slb, slbgr, slbg
6459 (define_insn "*sub<mode>3_slb"
6460 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6461 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6462 (match_operand:GPR 2 "general_operand" "d,T"))
6463 (match_operand:GPR 3 "s390_slb_comparison" "")))
6464 (clobber (reg:CC CC_REGNUM))]
6469 [(set_attr "op_type" "RRE,RXY")
6470 (set_attr "z10prop" "z10_c,*")])
6472 (define_expand "add<mode>cc"
6473 [(match_operand:GPR 0 "register_operand" "")
6474 (match_operand 1 "comparison_operator" "")
6475 (match_operand:GPR 2 "register_operand" "")
6476 (match_operand:GPR 3 "const_int_operand" "")]
6478 "if (!s390_expand_addcc (GET_CODE (operands[1]),
6479 XEXP (operands[1], 0), XEXP (operands[1], 1),
6480 operands[0], operands[2],
6481 operands[3])) FAIL; DONE;")
6484 ; scond instruction pattern(s).
6487 (define_insn_and_split "*scond<mode>"
6488 [(set (match_operand:GPR 0 "register_operand" "=&d")
6489 (match_operand:GPR 1 "s390_alc_comparison" ""))
6490 (clobber (reg:CC CC_REGNUM))]
6493 "&& reload_completed"
6494 [(set (match_dup 0) (const_int 0))
6496 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
6498 (clobber (reg:CC CC_REGNUM))])]
6501 (define_insn_and_split "*scond<mode>_neg"
6502 [(set (match_operand:GPR 0 "register_operand" "=&d")
6503 (match_operand:GPR 1 "s390_slb_comparison" ""))
6504 (clobber (reg:CC CC_REGNUM))]
6507 "&& reload_completed"
6508 [(set (match_dup 0) (const_int 0))
6510 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
6512 (clobber (reg:CC CC_REGNUM))])
6514 [(set (match_dup 0) (neg:GPR (match_dup 0)))
6515 (clobber (reg:CC CC_REGNUM))])]
6519 (define_expand "cstore<mode>4"
6520 [(set (match_operand:SI 0 "register_operand" "")
6521 (match_operator:SI 1 "s390_scond_operator"
6522 [(match_operand:GPR 2 "register_operand" "")
6523 (match_operand:GPR 3 "general_operand" "")]))]
6525 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
6526 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
6528 (define_expand "cstorecc4"
6530 [(set (match_operand:SI 0 "register_operand" "")
6531 (match_operator:SI 1 "s390_eqne_operator"
6532 [(match_operand 2 "cc_reg_operand")
6533 (match_operand 3 "const0_operand")]))
6534 (clobber (reg:CC CC_REGNUM))])]
6536 "machine_mode mode = GET_MODE (operands[2]);
6541 if (GET_CODE (operands[1]) == NE)
6542 cond = gen_rtx_NE (VOIDmode, operands[2], const0_rtx);
6544 cond = gen_rtx_EQ (VOIDmode, operands[2], const0_rtx);
6545 ite = gen_rtx_IF_THEN_ELSE (SImode, cond, const1_rtx, const0_rtx);
6546 emit_insn (gen_rtx_SET (operands[0], ite));
6550 if (mode != CCZ1mode)
6552 emit_insn (gen_sne (operands[0], operands[2]));
6553 if (GET_CODE (operands[1]) == EQ)
6554 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
6558 (define_insn_and_split "sne"
6559 [(set (match_operand:SI 0 "register_operand" "=d")
6560 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
6562 (clobber (reg:CC CC_REGNUM))]
6567 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
6568 (clobber (reg:CC CC_REGNUM))])])
6572 ;; - Conditional move instructions (introduced with z196)
6575 (define_expand "mov<mode>cc"
6576 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
6577 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6578 (match_operand:GPR 2 "loc_operand" "")
6579 (match_operand:GPR 3 "loc_operand" "")))]
6582 if (!TARGET_Z13 && CONSTANT_P (operands[2]))
6583 operands[2] = force_reg (<MODE>mode, operands[2]);
6585 if (!TARGET_Z13 && CONSTANT_P (operands[3]))
6586 operands[3] = force_reg (<MODE>mode, operands[3]);
6588 /* Emit the comparison insn in case we do not already have a comparison result. */
6589 if (!s390_comparison (operands[1], VOIDmode))
6590 operands[1] = s390_emit_compare (GET_CODE (operands[1]),
6591 XEXP (operands[1], 0),
6592 XEXP (operands[1], 1));
6595 ; locr, loc, stoc, locgr, locg, stocg, lochi, locghi
6596 (define_insn "*mov<mode>cc"
6597 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S,S")
6599 (match_operator 1 "s390_comparison"
6600 [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c")
6601 (match_operand 5 "const_int_operand" "")])
6602 (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0")
6603 (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d")))]
6614 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY")
6615 (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*")])
6618 ;;- Multiply instructions.
6622 ; muldi3 instruction pattern(s).
6625 (define_expand "muldi3"
6627 [(set (match_operand:DI 0 "register_operand")
6628 (mult:DI (match_operand:DI 1 "nonimmediate_operand")
6629 (match_operand:DI 2 "general_operand")))
6630 (clobber (reg:CC CC_REGNUM))])]
6633 (define_insn "*muldi3_sign"
6634 [(set (match_operand:DI 0 "register_operand" "=d,d")
6635 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
6636 (match_operand:DI 1 "register_operand" "0,0")))]
6641 [(set_attr "op_type" "RRE,RXY")
6642 (set_attr "type" "imuldi")])
6644 (define_insn "*muldi3"
6645 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d")
6646 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0,0,0")
6647 (match_operand:DI 2 "general_operand" "d,d,K,T,Os")))
6648 (clobber (match_scratch:CC 3 "=X,c,X,X,X"))]
6656 [(set_attr "op_type" "RRE,RRF,RI,RXY,RIL")
6657 (set_attr "type" "imuldi")
6658 (set_attr "cpu_facility" "*,z14,*,*,z10")])
6660 (define_insn "mulditi3"
6661 [(set (match_operand:TI 0 "register_operand" "=d,d")
6662 (mult:TI (sign_extend:TI
6663 (match_operand:DI 1 "register_operand" "%d,0"))
6665 (match_operand:DI 2 "nonimmediate_operand" " d,T"))))]
6670 [(set_attr "op_type" "RRF,RXY")])
6672 ; Combine likes op1 and op2 to be swapped sometimes.
6673 (define_insn "mulditi3_2"
6674 [(set (match_operand:TI 0 "register_operand" "=d,d")
6675 (mult:TI (sign_extend:TI
6676 (match_operand:DI 1 "nonimmediate_operand" "%d,T"))
6678 (match_operand:DI 2 "register_operand" " d,0"))))]
6683 [(set_attr "op_type" "RRF,RXY")])
6685 (define_insn "*muldi3_sign"
6686 [(set (match_operand:DI 0 "register_operand" "=d")
6687 (mult:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T"))
6688 (match_operand:DI 1 "register_operand" "0")))]
6691 [(set_attr "op_type" "RXY")])
6695 ; mulsi3 instruction pattern(s).
6698 (define_expand "mulsi3"
6700 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d")
6701 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6702 (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os")))
6703 (clobber (reg:CC CC_REGNUM))])]
6706 (define_insn "*mulsi3_sign"
6707 [(set (match_operand:SI 0 "register_operand" "=d,d")
6708 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
6709 (match_operand:SI 1 "register_operand" "0,0")))]
6714 [(set_attr "op_type" "RX,RXY")
6715 (set_attr "type" "imulhi")
6716 (set_attr "cpu_facility" "*,z10")])
6718 (define_insn "*mulsi3"
6719 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d")
6720 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6721 (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os")))
6722 (clobber (match_scratch:CC 3 "=X,c,X,X,X,X"))]
6731 [(set_attr "op_type" "RRE,RRF,RI,RX,RXY,RIL")
6732 (set_attr "type" "imulsi,*,imulhi,imulsi,imulsi,imulsi")
6733 (set_attr "cpu_facility" "*,z14,*,*,longdisp,z10")])
6736 ; mulsidi3 instruction pattern(s).
6739 (define_insn "mulsidi3"
6740 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
6741 (mult:DI (sign_extend:DI
6742 (match_operand:SI 1 "register_operand" "%0,0,0"))
6744 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
6750 [(set_attr "op_type" "RR,RX,RXY")
6751 (set_attr "type" "imulsi")
6752 (set_attr "cpu_facility" "*,*,z10")])
6755 ; umul instruction pattern(s).
6758 ; mlr, ml, mlgr, mlg
6759 (define_insn "umul<dwh><mode>3"
6760 [(set (match_operand:DW 0 "register_operand" "=d,d")
6761 (mult:DW (zero_extend:DW
6762 (match_operand:<DWH> 1 "register_operand" "%0,0"))
6764 (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))]
6769 [(set_attr "op_type" "RRE,RXY")
6770 (set_attr "type" "imul<dwh>")])
6773 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
6776 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
6777 (define_insn "mul<mode>3"
6778 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v")
6779 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v")
6780 (match_operand:FP 2 "general_operand" "f,f,R,v,v")))]
6788 [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR")
6789 (set_attr "type" "fmul<mode>")
6790 (set_attr "cpu_facility" "*,*,*,vx,vxe")
6791 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")])
6793 ; madbr, maebr, maxb, madb, maeb
6794 (define_insn "fma<mode>4"
6795 [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v")
6796 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v")
6797 (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v")
6798 (match_operand:DSF 3 "register_operand" "0,0,v,v")))]
6803 wfmadb\t%v0,%v1,%v2,%v3
6804 wfmasb\t%v0,%v1,%v2,%v3"
6805 [(set_attr "op_type" "RRE,RXE,VRR,VRR")
6806 (set_attr "type" "fmadd<mode>")
6807 (set_attr "cpu_facility" "*,*,vx,vxe")
6808 (set_attr "enabled" "*,*,<DF>,<SF>")])
6810 ; msxbr, msdbr, msebr, msxb, msdb, mseb
6811 (define_insn "fms<mode>4"
6812 [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v")
6813 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v")
6814 (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v")
6815 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v,v"))))]
6820 wfmsdb\t%v0,%v1,%v2,%v3
6821 wfmssb\t%v0,%v1,%v2,%v3"
6822 [(set_attr "op_type" "RRE,RXE,VRR,VRR")
6823 (set_attr "type" "fmadd<mode>")
6824 (set_attr "cpu_facility" "*,*,vx,vxe")
6825 (set_attr "enabled" "*,*,<DF>,<SF>")])
6828 ;;- Divide and modulo instructions.
6832 ; divmoddi4 instruction pattern(s).
6835 (define_expand "divmoddi4"
6836 [(parallel [(set (match_operand:DI 0 "general_operand" "")
6837 (div:DI (match_operand:DI 1 "register_operand" "")
6838 (match_operand:DI 2 "general_operand" "")))
6839 (set (match_operand:DI 3 "general_operand" "")
6840 (mod:DI (match_dup 1) (match_dup 2)))])
6841 (clobber (match_dup 4))]
6844 rtx div_equal, mod_equal;
6847 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
6848 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
6850 operands[4] = gen_reg_rtx(TImode);
6851 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
6853 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6854 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6856 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6857 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6862 (define_insn "divmodtidi3"
6863 [(set (match_operand:TI 0 "register_operand" "=d,d")
6867 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6868 (match_operand:DI 2 "general_operand" "d,T")))
6870 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
6875 [(set_attr "op_type" "RRE,RXY")
6876 (set_attr "type" "idiv")])
6878 (define_insn "divmodtisi3"
6879 [(set (match_operand:TI 0 "register_operand" "=d,d")
6883 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6885 (match_operand:SI 2 "nonimmediate_operand" "d,T"))))
6888 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
6893 [(set_attr "op_type" "RRE,RXY")
6894 (set_attr "type" "idiv")])
6897 ; udivmoddi4 instruction pattern(s).
6900 (define_expand "udivmoddi4"
6901 [(parallel [(set (match_operand:DI 0 "general_operand" "")
6902 (udiv:DI (match_operand:DI 1 "general_operand" "")
6903 (match_operand:DI 2 "nonimmediate_operand" "")))
6904 (set (match_operand:DI 3 "general_operand" "")
6905 (umod:DI (match_dup 1) (match_dup 2)))])
6906 (clobber (match_dup 4))]
6909 rtx div_equal, mod_equal, equal;
6912 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
6913 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
6914 equal = gen_rtx_IOR (TImode,
6915 gen_rtx_ASHIFT (TImode,
6916 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
6918 gen_rtx_ZERO_EXTEND (TImode, div_equal));
6920 operands[4] = gen_reg_rtx(TImode);
6921 emit_clobber (operands[4]);
6922 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
6923 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
6925 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
6926 set_unique_reg_note (insn, REG_EQUAL, equal);
6928 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6929 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6931 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6932 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6937 (define_insn "udivmodtidi3"
6938 [(set (match_operand:TI 0 "register_operand" "=d,d")
6943 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
6945 (match_operand:DI 2 "nonimmediate_operand" "d,T")))))
6949 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
6954 [(set_attr "op_type" "RRE,RXY")
6955 (set_attr "type" "idiv")])
6958 ; divmodsi4 instruction pattern(s).
6961 (define_expand "divmodsi4"
6962 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6963 (div:SI (match_operand:SI 1 "general_operand" "")
6964 (match_operand:SI 2 "nonimmediate_operand" "")))
6965 (set (match_operand:SI 3 "general_operand" "")
6966 (mod:SI (match_dup 1) (match_dup 2)))])
6967 (clobber (match_dup 4))]
6970 rtx div_equal, mod_equal, equal;
6973 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
6974 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
6975 equal = gen_rtx_IOR (DImode,
6976 gen_rtx_ASHIFT (DImode,
6977 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6979 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6981 operands[4] = gen_reg_rtx(DImode);
6982 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
6984 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
6985 set_unique_reg_note (insn, REG_EQUAL, equal);
6987 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6988 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6990 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6991 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6996 (define_insn "divmoddisi3"
6997 [(set (match_operand:DI 0 "register_operand" "=d,d")
7002 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
7004 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
7008 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
7013 [(set_attr "op_type" "RR,RX")
7014 (set_attr "type" "idiv")])
7017 ; udivsi3 and umodsi3 instruction pattern(s).
7020 (define_expand "udivmodsi4"
7021 [(parallel [(set (match_operand:SI 0 "general_operand" "")
7022 (udiv:SI (match_operand:SI 1 "general_operand" "")
7023 (match_operand:SI 2 "nonimmediate_operand" "")))
7024 (set (match_operand:SI 3 "general_operand" "")
7025 (umod:SI (match_dup 1) (match_dup 2)))])
7026 (clobber (match_dup 4))]
7029 rtx div_equal, mod_equal, equal;
7032 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
7033 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
7034 equal = gen_rtx_IOR (DImode,
7035 gen_rtx_ASHIFT (DImode,
7036 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
7038 gen_rtx_ZERO_EXTEND (DImode, div_equal));
7040 operands[4] = gen_reg_rtx(DImode);
7041 emit_clobber (operands[4]);
7042 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
7043 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
7045 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
7046 set_unique_reg_note (insn, REG_EQUAL, equal);
7048 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
7049 set_unique_reg_note (insn, REG_EQUAL, div_equal);
7051 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
7052 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
7057 (define_insn "udivmoddisi3"
7058 [(set (match_operand:DI 0 "register_operand" "=d,d")
7063 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
7065 (match_operand:SI 2 "nonimmediate_operand" "d,T")))))
7069 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
7074 [(set_attr "op_type" "RRE,RXY")
7075 (set_attr "type" "idiv")])
7078 ; div(df|sf)3 instruction pattern(s).
7081 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
7082 (define_insn "div<mode>3"
7083 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v")
7084 (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v")
7085 (match_operand:FP 2 "general_operand" "f,f,R,v,v")))]
7093 [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR")
7094 (set_attr "type" "fdiv<mode>")
7095 (set_attr "cpu_facility" "*,*,*,vx,vxe")
7096 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")])
7100 ;;- And instructions.
7103 (define_expand "and<mode>3"
7104 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7105 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
7106 (match_operand:INT 2 "general_operand" "")))
7107 (clobber (reg:CC CC_REGNUM))]
7109 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
7112 ; anddi3 instruction pattern(s).
7115 (define_insn "*anddi3_cc"
7116 [(set (reg CC_REGNUM)
7118 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d")
7119 (match_operand:DI 2 "general_operand" " d,d,T,NxxDw"))
7121 (set (match_operand:DI 0 "register_operand" "=d,d,d, d")
7122 (and:DI (match_dup 1) (match_dup 2)))]
7123 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
7128 risbg\t%0,%1,%s2,128+%e2,0"
7129 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
7130 (set_attr "cpu_facility" "*,z196,*,z10")
7131 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
7133 (define_insn "*anddi3_cconly"
7134 [(set (reg CC_REGNUM)
7136 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d")
7137 (match_operand:DI 2 "general_operand" " d,d,T,NxxDw"))
7139 (clobber (match_scratch:DI 0 "=d,d,d, d"))]
7141 && s390_match_ccmode(insn, CCTmode)
7142 /* Do not steal TM patterns. */
7143 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
7148 risbg\t%0,%1,%s2,128+%e2,0"
7149 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
7150 (set_attr "cpu_facility" "*,z196,*,z10")
7151 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
7153 (define_insn "*anddi3"
7154 [(set (match_operand:DI 0 "nonimmediate_operand"
7155 "=d,d, d, d, d, d, d, d,d,d,d, d, AQ,Q")
7157 (match_operand:DI 1 "nonimmediate_operand"
7158 "%d,o, 0, 0, 0, 0, 0, 0,0,d,0, d, 0,0")
7159 (match_operand:DI 2 "general_operand"
7160 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDw,NxQDF,Q")))
7161 (clobber (reg:CC CC_REGNUM))]
7162 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7175 risbg\t%0,%1,%s2,128+%e2,0
7178 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
7179 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
7180 (set_attr "z10prop" "*,
7196 [(set (match_operand:DI 0 "s_operand" "")
7197 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7198 (clobber (reg:CC CC_REGNUM))]
7201 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7202 (clobber (reg:CC CC_REGNUM))])]
7203 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7205 ;; These two are what combine generates for (ashift (zero_extract)).
7206 (define_insn "*extzv_<mode>_srl<clobbercc_or_nocc>"
7207 [(set (match_operand:GPR 0 "register_operand" "=d")
7208 (and:GPR (lshiftrt:GPR
7209 (match_operand:GPR 1 "register_operand" "d")
7210 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
7211 (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))]
7212 "<z10_or_zEC12_cond>
7213 /* Note that even for the SImode pattern, the rotate is always DImode. */
7214 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
7215 INTVAL (operands[3]))"
7216 "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
7217 [(set_attr "op_type" "RIE")
7218 (set_attr "z10prop" "z10_super_E1")])
7220 (define_insn "*extzv_<mode>_sll<clobbercc_or_nocc>"
7221 [(set (match_operand:GPR 0 "register_operand" "=d")
7222 (and:GPR (ashift:GPR
7223 (match_operand:GPR 1 "register_operand" "d")
7224 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
7225 (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))]
7226 "<z10_or_zEC12_cond>
7227 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
7228 INTVAL (operands[3]))"
7229 "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
7230 [(set_attr "op_type" "RIE")
7231 (set_attr "z10prop" "z10_super_E1")])
7235 ; andsi3 instruction pattern(s).
7238 (define_insn "*andsi3_cc"
7239 [(set (reg CC_REGNUM)
7242 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
7243 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
7245 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
7246 (and:SI (match_dup 1) (match_dup 2)))]
7247 "s390_match_ccmode(insn, CCTmode)"
7254 risbg\t%0,%1,%t2,128+%f2,0"
7255 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
7256 (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10")
7257 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7258 z10_super_E1,z10_super_E1,z10_super_E1")])
7260 (define_insn "*andsi3_cconly"
7261 [(set (reg CC_REGNUM)
7264 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
7265 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
7267 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
7268 "s390_match_ccmode(insn, CCTmode)
7269 /* Do not steal TM patterns. */
7270 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
7277 risbg\t%0,%1,%t2,128+%f2,0"
7278 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
7279 (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10")
7280 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7281 z10_super_E1,z10_super_E1,z10_super_E1")])
7283 (define_insn "*andsi3_zarch"
7284 [(set (match_operand:SI 0 "nonimmediate_operand"
7285 "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
7286 (and:SI (match_operand:SI 1 "nonimmediate_operand"
7287 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
7288 (match_operand:SI 2 "general_operand"
7289 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSw,NxQSF,Q")))
7290 (clobber (reg:CC CC_REGNUM))]
7291 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7302 risbg\t%0,%1,%t2,128+%f2,0
7305 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
7306 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*")
7307 (set_attr "z10prop" "*,
7320 (define_insn "*andsi3_esa"
7321 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
7322 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
7323 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
7324 (clobber (reg:CC CC_REGNUM))]
7325 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7331 [(set_attr "op_type" "RR,RX,SI,SS")
7332 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7336 [(set (match_operand:SI 0 "s_operand" "")
7337 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7338 (clobber (reg:CC CC_REGNUM))]
7341 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7342 (clobber (reg:CC CC_REGNUM))])]
7343 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7346 ; andhi3 instruction pattern(s).
7349 (define_insn "*andhi3_zarch"
7350 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7351 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
7352 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
7353 (clobber (reg:CC CC_REGNUM))]
7354 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7361 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
7362 (set_attr "cpu_facility" "*,z196,*,*,*")
7363 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
7366 (define_insn "*andhi3_esa"
7367 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7368 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7369 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
7370 (clobber (reg:CC CC_REGNUM))]
7371 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7376 [(set_attr "op_type" "RR,SI,SS")
7377 (set_attr "z10prop" "z10_super_E1,*,*")
7381 [(set (match_operand:HI 0 "s_operand" "")
7382 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7383 (clobber (reg:CC CC_REGNUM))]
7386 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7387 (clobber (reg:CC CC_REGNUM))])]
7388 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7391 ; andqi3 instruction pattern(s).
7394 (define_insn "*andqi3_zarch"
7395 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7396 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7397 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
7398 (clobber (reg:CC CC_REGNUM))]
7399 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7407 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7408 (set_attr "cpu_facility" "*,z196,*,*,longdisp,*")
7409 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
7411 (define_insn "*andqi3_esa"
7412 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7413 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7414 (match_operand:QI 2 "general_operand" "d,n,Q")))
7415 (clobber (reg:CC CC_REGNUM))]
7416 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7421 [(set_attr "op_type" "RR,SI,SS")
7422 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7425 ; And with complement
7427 ; c = ~b & a = (b & a) ^ a
7429 (define_insn_and_split "*andc_split_<mode>"
7430 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
7431 (and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" ""))
7432 (match_operand:GPR 2 "general_operand" "")))
7433 (clobber (reg:CC CC_REGNUM))]
7435 && (GET_CODE (operands[0]) != MEM
7436 /* Ensure that s390_logical_operator_ok_p will succeed even
7437 on the split xor if (b & a) is stored into a pseudo. */
7438 || rtx_equal_p (operands[0], operands[2]))"
7443 [(set (match_dup 3) (and:GPR (match_dup 1) (match_dup 2)))
7444 (clobber (reg:CC CC_REGNUM))])
7446 [(set (match_dup 0) (xor:GPR (match_dup 3) (match_dup 2)))
7447 (clobber (reg:CC CC_REGNUM))])]
7449 if (reg_overlap_mentioned_p (operands[0], operands[2]))
7450 operands[3] = gen_reg_rtx (<MODE>mode);
7452 operands[3] = operands[0];
7456 ; Block and (NC) patterns.
7460 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7461 (and:BLK (match_dup 0)
7462 (match_operand:BLK 1 "memory_operand" "Q")))
7463 (use (match_operand 2 "const_int_operand" "n"))
7464 (clobber (reg:CC CC_REGNUM))]
7465 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7466 "nc\t%O0(%2,%R0),%S1"
7467 [(set_attr "op_type" "SS")
7468 (set_attr "z196prop" "z196_cracked")])
7471 [(set (match_operand 0 "memory_operand" "")
7473 (match_operand 1 "memory_operand" "")))
7474 (clobber (reg:CC CC_REGNUM))]
7476 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7477 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7479 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
7481 (clobber (reg:CC CC_REGNUM))])]
7483 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7484 operands[0] = adjust_address (operands[0], BLKmode, 0);
7485 operands[1] = adjust_address (operands[1], BLKmode, 0);
7490 [(set (match_operand:BLK 0 "memory_operand" "")
7491 (and:BLK (match_dup 0)
7492 (match_operand:BLK 1 "memory_operand" "")))
7493 (use (match_operand 2 "const_int_operand" ""))
7494 (clobber (reg:CC CC_REGNUM))])
7496 [(set (match_operand:BLK 3 "memory_operand" "")
7497 (and:BLK (match_dup 3)
7498 (match_operand:BLK 4 "memory_operand" "")))
7499 (use (match_operand 5 "const_int_operand" ""))
7500 (clobber (reg:CC CC_REGNUM))])]
7501 "s390_offset_p (operands[0], operands[3], operands[2])
7502 && s390_offset_p (operands[1], operands[4], operands[2])
7503 && !s390_overlap_p (operands[0], operands[1],
7504 INTVAL (operands[2]) + INTVAL (operands[5]))
7505 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7507 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
7509 (clobber (reg:CC CC_REGNUM))])]
7510 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7511 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7512 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7516 ;;- Bit set (inclusive or) instructions.
7519 (define_expand "ior<mode>3"
7520 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7521 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
7522 (match_operand:INT 2 "general_operand" "")))
7523 (clobber (reg:CC CC_REGNUM))]
7525 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
7528 ; iordi3 instruction pattern(s).
7531 (define_insn "*iordi3_cc"
7532 [(set (reg CC_REGNUM)
7533 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7534 (match_operand:DI 2 "general_operand" " d,d,T"))
7536 (set (match_operand:DI 0 "register_operand" "=d,d,d")
7537 (ior:DI (match_dup 1) (match_dup 2)))]
7538 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7543 [(set_attr "op_type" "RRE,RRF,RXY")
7544 (set_attr "cpu_facility" "*,z196,*")
7545 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7547 (define_insn "*iordi3_cconly"
7548 [(set (reg CC_REGNUM)
7549 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7550 (match_operand:DI 2 "general_operand" " d,d,T"))
7552 (clobber (match_scratch:DI 0 "=d,d,d"))]
7553 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7558 [(set_attr "op_type" "RRE,RRF,RXY")
7559 (set_attr "cpu_facility" "*,z196,*")
7560 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7562 (define_insn "*iordi3"
7563 [(set (match_operand:DI 0 "nonimmediate_operand"
7564 "=d, d, d, d, d, d,d,d,d, AQ,Q")
7565 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
7566 " %0, 0, 0, 0, 0, 0,0,d,0, 0,0")
7567 (match_operand:DI 2 "general_operand"
7568 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q")))
7569 (clobber (reg:CC CC_REGNUM))]
7570 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7583 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
7584 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
7585 (set_attr "z10prop" "z10_super_E1,
7598 [(set (match_operand:DI 0 "s_operand" "")
7599 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7600 (clobber (reg:CC CC_REGNUM))]
7603 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7604 (clobber (reg:CC CC_REGNUM))])]
7605 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7608 ; iorsi3 instruction pattern(s).
7611 (define_insn "*iorsi3_cc"
7612 [(set (reg CC_REGNUM)
7613 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7614 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7616 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
7617 (ior:SI (match_dup 1) (match_dup 2)))]
7618 "s390_match_ccmode(insn, CCTmode)"
7625 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7626 (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7627 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7629 (define_insn "*iorsi3_cconly"
7630 [(set (reg CC_REGNUM)
7631 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7632 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7634 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
7635 "s390_match_ccmode(insn, CCTmode)"
7642 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7643 (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7644 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7646 (define_insn "*iorsi3_zarch"
7647 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
7648 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
7649 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
7650 (clobber (reg:CC CC_REGNUM))]
7651 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7662 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
7663 (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*")
7664 (set_attr "z10prop" "z10_super_E1,
7674 (define_insn "*iorsi3_esa"
7675 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
7676 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
7677 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
7678 (clobber (reg:CC CC_REGNUM))]
7679 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7685 [(set_attr "op_type" "RR,RX,SI,SS")
7686 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7689 [(set (match_operand:SI 0 "s_operand" "")
7690 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7691 (clobber (reg:CC CC_REGNUM))]
7694 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7695 (clobber (reg:CC CC_REGNUM))])]
7696 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7699 ; iorhi3 instruction pattern(s).
7702 (define_insn "*iorhi3_zarch"
7703 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7704 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
7705 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
7706 (clobber (reg:CC CC_REGNUM))]
7707 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7714 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
7715 (set_attr "cpu_facility" "*,z196,*,*,*")
7716 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
7718 (define_insn "*iorhi3_esa"
7719 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7720 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7721 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
7722 (clobber (reg:CC CC_REGNUM))]
7723 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7728 [(set_attr "op_type" "RR,SI,SS")
7729 (set_attr "z10prop" "z10_super_E1,*,*")])
7732 [(set (match_operand:HI 0 "s_operand" "")
7733 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7734 (clobber (reg:CC CC_REGNUM))]
7737 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7738 (clobber (reg:CC CC_REGNUM))])]
7739 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7742 ; iorqi3 instruction pattern(s).
7745 (define_insn "*iorqi3_zarch"
7746 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7747 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7748 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
7749 (clobber (reg:CC CC_REGNUM))]
7750 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7758 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7759 (set_attr "cpu_facility" "*,z196,*,*,longdisp,*")
7760 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
7761 z10_super,z10_super,*")])
7763 (define_insn "*iorqi3_esa"
7764 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7765 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7766 (match_operand:QI 2 "general_operand" "d,n,Q")))
7767 (clobber (reg:CC CC_REGNUM))]
7768 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7773 [(set_attr "op_type" "RR,SI,SS")
7774 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7777 ; Block inclusive or (OC) patterns.
7781 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7782 (ior:BLK (match_dup 0)
7783 (match_operand:BLK 1 "memory_operand" "Q")))
7784 (use (match_operand 2 "const_int_operand" "n"))
7785 (clobber (reg:CC CC_REGNUM))]
7786 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7787 "oc\t%O0(%2,%R0),%S1"
7788 [(set_attr "op_type" "SS")
7789 (set_attr "z196prop" "z196_cracked")])
7792 [(set (match_operand 0 "memory_operand" "")
7794 (match_operand 1 "memory_operand" "")))
7795 (clobber (reg:CC CC_REGNUM))]
7797 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7798 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7800 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
7802 (clobber (reg:CC CC_REGNUM))])]
7804 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7805 operands[0] = adjust_address (operands[0], BLKmode, 0);
7806 operands[1] = adjust_address (operands[1], BLKmode, 0);
7811 [(set (match_operand:BLK 0 "memory_operand" "")
7812 (ior:BLK (match_dup 0)
7813 (match_operand:BLK 1 "memory_operand" "")))
7814 (use (match_operand 2 "const_int_operand" ""))
7815 (clobber (reg:CC CC_REGNUM))])
7817 [(set (match_operand:BLK 3 "memory_operand" "")
7818 (ior:BLK (match_dup 3)
7819 (match_operand:BLK 4 "memory_operand" "")))
7820 (use (match_operand 5 "const_int_operand" ""))
7821 (clobber (reg:CC CC_REGNUM))])]
7822 "s390_offset_p (operands[0], operands[3], operands[2])
7823 && s390_offset_p (operands[1], operands[4], operands[2])
7824 && !s390_overlap_p (operands[0], operands[1],
7825 INTVAL (operands[2]) + INTVAL (operands[5]))
7826 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7828 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
7830 (clobber (reg:CC CC_REGNUM))])]
7831 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7832 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7833 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7837 ;;- Xor instructions.
7840 (define_expand "xor<mode>3"
7841 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7842 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
7843 (match_operand:INT 2 "general_operand" "")))
7844 (clobber (reg:CC CC_REGNUM))]
7846 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
7848 ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing
7849 ; simplifications. So its better to have something matching.
7851 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7852 (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))]
7855 [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2)))
7856 (clobber (reg:CC CC_REGNUM))])]
7858 operands[2] = constm1_rtx;
7859 if (!s390_logical_operator_ok_p (operands))
7864 ; xordi3 instruction pattern(s).
7867 (define_insn "*xordi3_cc"
7868 [(set (reg CC_REGNUM)
7869 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7870 (match_operand:DI 2 "general_operand" " d,d,T"))
7872 (set (match_operand:DI 0 "register_operand" "=d,d,d")
7873 (xor:DI (match_dup 1) (match_dup 2)))]
7874 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7879 [(set_attr "op_type" "RRE,RRF,RXY")
7880 (set_attr "cpu_facility" "*,z196,*")
7881 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7883 (define_insn "*xordi3_cconly"
7884 [(set (reg CC_REGNUM)
7885 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7886 (match_operand:DI 2 "general_operand" " d,d,T"))
7888 (clobber (match_scratch:DI 0 "=d,d,d"))]
7889 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7894 [(set_attr "op_type" "RRE,RRF,RXY")
7895 (set_attr "cpu_facility" "*,z196,*")
7896 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7898 (define_insn "*xordi3"
7899 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d,d, AQ,Q")
7900 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0")
7901 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q")))
7902 (clobber (reg:CC CC_REGNUM))]
7903 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7912 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
7913 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
7914 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
7915 *,z10_super_E1,*,*")])
7918 [(set (match_operand:DI 0 "s_operand" "")
7919 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7920 (clobber (reg:CC CC_REGNUM))]
7923 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7924 (clobber (reg:CC CC_REGNUM))])]
7925 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7928 ; xorsi3 instruction pattern(s).
7931 (define_insn "*xorsi3_cc"
7932 [(set (reg CC_REGNUM)
7933 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7934 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7936 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
7937 (xor:SI (match_dup 1) (match_dup 2)))]
7938 "s390_match_ccmode(insn, CCTmode)"
7945 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7946 (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7947 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7948 z10_super_E1,z10_super_E1")])
7950 (define_insn "*xorsi3_cconly"
7951 [(set (reg CC_REGNUM)
7952 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7953 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7955 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
7956 "s390_match_ccmode(insn, CCTmode)"
7963 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7964 (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7965 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7966 z10_super_E1,z10_super_E1")])
7968 (define_insn "*xorsi3"
7969 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
7970 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
7971 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
7972 (clobber (reg:CC CC_REGNUM))]
7973 "s390_logical_operator_ok_p (operands)"
7982 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
7983 (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*")
7984 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7985 z10_super_E1,z10_super_E1,*,*")])
7988 [(set (match_operand:SI 0 "s_operand" "")
7989 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7990 (clobber (reg:CC CC_REGNUM))]
7993 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7994 (clobber (reg:CC CC_REGNUM))])]
7995 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7998 ; xorhi3 instruction pattern(s).
8001 (define_insn "*xorhi3"
8002 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
8003 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
8004 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
8005 (clobber (reg:CC CC_REGNUM))]
8006 "s390_logical_operator_ok_p (operands)"
8013 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
8014 (set_attr "cpu_facility" "*,*,z196,*,*")
8015 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
8018 [(set (match_operand:HI 0 "s_operand" "")
8019 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
8020 (clobber (reg:CC CC_REGNUM))]
8023 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
8024 (clobber (reg:CC CC_REGNUM))])]
8025 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
8028 ; xorqi3 instruction pattern(s).
8031 (define_insn "*xorqi3"
8032 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
8033 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
8034 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
8035 (clobber (reg:CC CC_REGNUM))]
8036 "s390_logical_operator_ok_p (operands)"
8044 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
8045 (set_attr "cpu_facility" "*,*,z196,*,longdisp,*")
8046 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
8050 ; Block exclusive or (XC) patterns.
8054 [(set (match_operand:BLK 0 "memory_operand" "=Q")
8055 (xor:BLK (match_dup 0)
8056 (match_operand:BLK 1 "memory_operand" "Q")))
8057 (use (match_operand 2 "const_int_operand" "n"))
8058 (clobber (reg:CC CC_REGNUM))]
8059 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
8060 "xc\t%O0(%2,%R0),%S1"
8061 [(set_attr "op_type" "SS")])
8064 [(set (match_operand 0 "memory_operand" "")
8066 (match_operand 1 "memory_operand" "")))
8067 (clobber (reg:CC CC_REGNUM))]
8069 && GET_MODE (operands[0]) == GET_MODE (operands[1])
8070 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
8072 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
8074 (clobber (reg:CC CC_REGNUM))])]
8076 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
8077 operands[0] = adjust_address (operands[0], BLKmode, 0);
8078 operands[1] = adjust_address (operands[1], BLKmode, 0);
8083 [(set (match_operand:BLK 0 "memory_operand" "")
8084 (xor:BLK (match_dup 0)
8085 (match_operand:BLK 1 "memory_operand" "")))
8086 (use (match_operand 2 "const_int_operand" ""))
8087 (clobber (reg:CC CC_REGNUM))])
8089 [(set (match_operand:BLK 3 "memory_operand" "")
8090 (xor:BLK (match_dup 3)
8091 (match_operand:BLK 4 "memory_operand" "")))
8092 (use (match_operand 5 "const_int_operand" ""))
8093 (clobber (reg:CC CC_REGNUM))])]
8094 "s390_offset_p (operands[0], operands[3], operands[2])
8095 && s390_offset_p (operands[1], operands[4], operands[2])
8096 && !s390_overlap_p (operands[0], operands[1],
8097 INTVAL (operands[2]) + INTVAL (operands[5]))
8098 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
8100 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
8102 (clobber (reg:CC CC_REGNUM))])]
8103 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
8104 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
8105 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
8108 ; Block xor (XC) patterns with src == dest.
8111 (define_insn "*xc_zero"
8112 [(set (match_operand:BLK 0 "memory_operand" "=Q")
8114 (use (match_operand 1 "const_int_operand" "n"))
8115 (clobber (reg:CC CC_REGNUM))]
8116 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
8117 "xc\t%O0(%1,%R0),%S0"
8118 [(set_attr "op_type" "SS")
8119 (set_attr "z196prop" "z196_cracked")])
8123 [(set (match_operand:BLK 0 "memory_operand" "")
8125 (use (match_operand 1 "const_int_operand" ""))
8126 (clobber (reg:CC CC_REGNUM))])
8128 [(set (match_operand:BLK 2 "memory_operand" "")
8130 (use (match_operand 3 "const_int_operand" ""))
8131 (clobber (reg:CC CC_REGNUM))])]
8132 "s390_offset_p (operands[0], operands[2], operands[1])
8133 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
8135 [(set (match_dup 4) (const_int 0))
8137 (clobber (reg:CC CC_REGNUM))])]
8138 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
8139 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
8143 ;;- Negate instructions.
8147 ; neg(di|si)2 instruction pattern(s).
8150 (define_expand "neg<mode>2"
8152 [(set (match_operand:DSI 0 "register_operand" "=d")
8153 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
8154 (clobber (reg:CC CC_REGNUM))])]
8158 (define_insn "*negdi2_sign_cc"
8159 [(set (reg CC_REGNUM)
8160 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
8161 (match_operand:SI 1 "register_operand" "d") 0)
8162 (const_int 32)) (const_int 32)))
8164 (set (match_operand:DI 0 "register_operand" "=d")
8165 (neg:DI (sign_extend:DI (match_dup 1))))]
8166 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8168 [(set_attr "op_type" "RRE")
8169 (set_attr "z10prop" "z10_c")])
8171 (define_insn "*negdi2_sign"
8172 [(set (match_operand:DI 0 "register_operand" "=d")
8173 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
8174 (clobber (reg:CC CC_REGNUM))]
8177 [(set_attr "op_type" "RRE")
8178 (set_attr "z10prop" "z10_c")])
8181 (define_insn "*neg<mode>2_cc"
8182 [(set (reg CC_REGNUM)
8183 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
8185 (set (match_operand:GPR 0 "register_operand" "=d")
8186 (neg:GPR (match_dup 1)))]
8187 "s390_match_ccmode (insn, CCAmode)"
8189 [(set_attr "op_type" "RR<E>")
8190 (set_attr "z10prop" "z10_super_c_E1")])
8193 (define_insn "*neg<mode>2_cconly"
8194 [(set (reg CC_REGNUM)
8195 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
8197 (clobber (match_scratch:GPR 0 "=d"))]
8198 "s390_match_ccmode (insn, CCAmode)"
8200 [(set_attr "op_type" "RR<E>")
8201 (set_attr "z10prop" "z10_super_c_E1")])
8204 (define_insn "*neg<mode>2"
8205 [(set (match_operand:GPR 0 "register_operand" "=d")
8206 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
8207 (clobber (reg:CC CC_REGNUM))]
8210 [(set_attr "op_type" "RR<E>")
8211 (set_attr "z10prop" "z10_super_c_E1")])
8213 (define_insn "*negdi2_31"
8214 [(set (match_operand:DI 0 "register_operand" "=d")
8215 (neg:DI (match_operand:DI 1 "register_operand" "d")))
8216 (clobber (reg:CC CC_REGNUM))]
8220 ; Split a DImode NEG on 31bit into 2 SImode NEGs
8222 ; Doing the twos complement separately on the SImode parts does an
8223 ; unwanted +1 on the high part which needs to be subtracted afterwards
8224 ; ... unless the +1 on the low part created an overflow.
8227 [(set (match_operand:DI 0 "register_operand" "")
8228 (neg:DI (match_operand:DI 1 "register_operand" "")))
8229 (clobber (reg:CC CC_REGNUM))]
8231 && (REGNO (operands[0]) == REGNO (operands[1])
8232 || s390_split_ok_p (operands[0], operands[1], DImode, 0))
8233 && reload_completed"
8235 [(set (match_dup 2) (neg:SI (match_dup 3)))
8236 (clobber (reg:CC CC_REGNUM))])
8238 [(set (reg:CCAP CC_REGNUM)
8239 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
8240 (set (match_dup 4) (neg:SI (match_dup 5)))])
8242 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
8244 (label_ref (match_dup 6))))
8246 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
8247 (clobber (reg:CC CC_REGNUM))])
8249 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
8250 operands[3] = operand_subword (operands[1], 0, 0, DImode);
8251 operands[4] = operand_subword (operands[0], 1, 0, DImode);
8252 operands[5] = operand_subword (operands[1], 1, 0, DImode);
8253 operands[6] = gen_label_rtx ();")
8255 ; Like above but first make a copy of the low part of the src operand
8256 ; since it might overlap with the high part of the destination.
8259 [(set (match_operand:DI 0 "register_operand" "")
8260 (neg:DI (match_operand:DI 1 "register_operand" "")))
8261 (clobber (reg:CC CC_REGNUM))]
8263 && s390_split_ok_p (operands[0], operands[1], DImode, 1)
8264 && reload_completed"
8265 [; Make a backup of op5 first
8266 (set (match_dup 4) (match_dup 5))
8267 ; Setting op2 here might clobber op5
8269 [(set (match_dup 2) (neg:SI (match_dup 3)))
8270 (clobber (reg:CC CC_REGNUM))])
8272 [(set (reg:CCAP CC_REGNUM)
8273 (compare:CCAP (neg:SI (match_dup 4)) (const_int 0)))
8274 (set (match_dup 4) (neg:SI (match_dup 4)))])
8276 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
8278 (label_ref (match_dup 6))))
8280 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
8281 (clobber (reg:CC CC_REGNUM))])
8283 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
8284 operands[3] = operand_subword (operands[1], 0, 0, DImode);
8285 operands[4] = operand_subword (operands[0], 1, 0, DImode);
8286 operands[5] = operand_subword (operands[1], 1, 0, DImode);
8287 operands[6] = gen_label_rtx ();")
8290 ; neg(df|sf)2 instruction pattern(s).
8293 (define_expand "neg<mode>2"
8295 [(set (match_operand:BFP 0 "register_operand")
8296 (neg:BFP (match_operand:BFP 1 "register_operand")))
8297 (clobber (reg:CC CC_REGNUM))])]
8298 "TARGET_HARD_FLOAT")
8300 ; lcxbr, lcdbr, lcebr
8301 (define_insn "*neg<mode>2_cc"
8302 [(set (reg CC_REGNUM)
8303 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
8304 (match_operand:BFP 2 "const0_operand" "")))
8305 (set (match_operand:BFP 0 "register_operand" "=f")
8306 (neg:BFP (match_dup 1)))]
8307 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8309 [(set_attr "op_type" "RRE")
8310 (set_attr "type" "fsimp<mode>")])
8312 ; lcxbr, lcdbr, lcebr
8313 (define_insn "*neg<mode>2_cconly"
8314 [(set (reg CC_REGNUM)
8315 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
8316 (match_operand:BFP 2 "const0_operand" "")))
8317 (clobber (match_scratch:BFP 0 "=f"))]
8318 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8320 [(set_attr "op_type" "RRE")
8321 (set_attr "type" "fsimp<mode>")])
8324 (define_insn "*neg<mode>2_nocc"
8325 [(set (match_operand:FP 0 "register_operand" "=f")
8326 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8329 [(set_attr "op_type" "RRE")
8330 (set_attr "type" "fsimp<mode>")])
8332 ; lcxbr, lcdbr, lcebr
8333 ; FIXME: wflcdb does not clobber cc
8334 ; FIXME: Does wflcdb ever match here?
8335 (define_insn "*neg<mode>2"
8336 [(set (match_operand:BFP 0 "register_operand" "=f,v,v")
8337 (neg:BFP (match_operand:BFP 1 "register_operand" "f,v,v")))
8338 (clobber (reg:CC CC_REGNUM))]
8344 [(set_attr "op_type" "RRE,VRR,VRR")
8345 (set_attr "cpu_facility" "*,vx,vxe")
8346 (set_attr "type" "fsimp<mode>,*,*")
8347 (set_attr "enabled" "*,<DF>,<SF>")])
8351 ;;- Absolute value instructions.
8355 ; abs(di|si)2 instruction pattern(s).
8358 (define_insn "*absdi2_sign_cc"
8359 [(set (reg CC_REGNUM)
8360 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8361 (match_operand:SI 1 "register_operand" "d") 0)
8362 (const_int 32)) (const_int 32)))
8364 (set (match_operand:DI 0 "register_operand" "=d")
8365 (abs:DI (sign_extend:DI (match_dup 1))))]
8366 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8368 [(set_attr "op_type" "RRE")
8369 (set_attr "z10prop" "z10_c")])
8371 (define_insn "*absdi2_sign"
8372 [(set (match_operand:DI 0 "register_operand" "=d")
8373 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
8374 (clobber (reg:CC CC_REGNUM))]
8377 [(set_attr "op_type" "RRE")
8378 (set_attr "z10prop" "z10_c")])
8381 (define_insn "*abs<mode>2_cc"
8382 [(set (reg CC_REGNUM)
8383 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
8385 (set (match_operand:GPR 0 "register_operand" "=d")
8386 (abs:GPR (match_dup 1)))]
8387 "s390_match_ccmode (insn, CCAmode)"
8389 [(set_attr "op_type" "RR<E>")
8390 (set_attr "z10prop" "z10_c")])
8393 (define_insn "*abs<mode>2_cconly"
8394 [(set (reg CC_REGNUM)
8395 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
8397 (clobber (match_scratch:GPR 0 "=d"))]
8398 "s390_match_ccmode (insn, CCAmode)"
8400 [(set_attr "op_type" "RR<E>")
8401 (set_attr "z10prop" "z10_c")])
8404 (define_insn "abs<mode>2"
8405 [(set (match_operand:GPR 0 "register_operand" "=d")
8406 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8407 (clobber (reg:CC CC_REGNUM))]
8410 [(set_attr "op_type" "RR<E>")
8411 (set_attr "z10prop" "z10_c")])
8414 ; abs(df|sf)2 instruction pattern(s).
8417 (define_expand "abs<mode>2"
8419 [(set (match_operand:BFP 0 "register_operand" "=f")
8420 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8421 (clobber (reg:CC CC_REGNUM))])]
8425 ; lpxbr, lpdbr, lpebr
8426 (define_insn "*abs<mode>2_cc"
8427 [(set (reg CC_REGNUM)
8428 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8429 (match_operand:BFP 2 "const0_operand" "")))
8430 (set (match_operand:BFP 0 "register_operand" "=f")
8431 (abs:BFP (match_dup 1)))]
8432 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8434 [(set_attr "op_type" "RRE")
8435 (set_attr "type" "fsimp<mode>")])
8437 ; lpxbr, lpdbr, lpebr
8438 (define_insn "*abs<mode>2_cconly"
8439 [(set (reg CC_REGNUM)
8440 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8441 (match_operand:BFP 2 "const0_operand" "")))
8442 (clobber (match_scratch:BFP 0 "=f"))]
8443 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8445 [(set_attr "op_type" "RRE")
8446 (set_attr "type" "fsimp<mode>")])
8449 (define_insn "*abs<mode>2_nocc"
8450 [(set (match_operand:FP 0 "register_operand" "=f")
8451 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8454 [(set_attr "op_type" "RRE")
8455 (set_attr "type" "fsimp<mode>")])
8457 ; lpxbr, lpdbr, lpebr
8458 ; FIXME: wflpdb does not clobber cc
8459 (define_insn "*abs<mode>2"
8460 [(set (match_operand:BFP 0 "register_operand" "=f,v")
8461 (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))
8462 (clobber (reg:CC CC_REGNUM))]
8467 [(set_attr "op_type" "RRE,VRR")
8468 (set_attr "cpu_facility" "*,vx")
8469 (set_attr "type" "fsimp<mode>,*")
8470 (set_attr "enabled" "*,<DFDI>")])
8474 ;;- Negated absolute value instructions
8481 (define_insn "*negabsdi2_sign_cc"
8482 [(set (reg CC_REGNUM)
8483 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8484 (match_operand:SI 1 "register_operand" "d") 0)
8485 (const_int 32)) (const_int 32))))
8487 (set (match_operand:DI 0 "register_operand" "=d")
8488 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
8489 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8491 [(set_attr "op_type" "RRE")
8492 (set_attr "z10prop" "z10_c")])
8494 (define_insn "*negabsdi2_sign"
8495 [(set (match_operand:DI 0 "register_operand" "=d")
8496 (neg:DI (abs:DI (sign_extend:DI
8497 (match_operand:SI 1 "register_operand" "d")))))
8498 (clobber (reg:CC CC_REGNUM))]
8501 [(set_attr "op_type" "RRE")
8502 (set_attr "z10prop" "z10_c")])
8505 (define_insn "*negabs<mode>2_cc"
8506 [(set (reg CC_REGNUM)
8507 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8509 (set (match_operand:GPR 0 "register_operand" "=d")
8510 (neg:GPR (abs:GPR (match_dup 1))))]
8511 "s390_match_ccmode (insn, CCAmode)"
8513 [(set_attr "op_type" "RR<E>")
8514 (set_attr "z10prop" "z10_c")])
8517 (define_insn "*negabs<mode>2_cconly"
8518 [(set (reg CC_REGNUM)
8519 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8521 (clobber (match_scratch:GPR 0 "=d"))]
8522 "s390_match_ccmode (insn, CCAmode)"
8524 [(set_attr "op_type" "RR<E>")
8525 (set_attr "z10prop" "z10_c")])
8528 (define_insn "*negabs<mode>2"
8529 [(set (match_operand:GPR 0 "register_operand" "=d")
8530 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
8531 (clobber (reg:CC CC_REGNUM))]
8534 [(set_attr "op_type" "RR<E>")
8535 (set_attr "z10prop" "z10_c")])
8541 ; lnxbr, lndbr, lnebr
8542 (define_insn "*negabs<mode>2_cc"
8543 [(set (reg CC_REGNUM)
8544 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8545 (match_operand:BFP 2 "const0_operand" "")))
8546 (set (match_operand:BFP 0 "register_operand" "=f")
8547 (neg:BFP (abs:BFP (match_dup 1))))]
8548 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8550 [(set_attr "op_type" "RRE")
8551 (set_attr "type" "fsimp<mode>")])
8553 ; lnxbr, lndbr, lnebr
8554 (define_insn "*negabs<mode>2_cconly"
8555 [(set (reg CC_REGNUM)
8556 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8557 (match_operand:BFP 2 "const0_operand" "")))
8558 (clobber (match_scratch:BFP 0 "=f"))]
8559 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8561 [(set_attr "op_type" "RRE")
8562 (set_attr "type" "fsimp<mode>")])
8565 (define_insn "*negabs<mode>2_nocc"
8566 [(set (match_operand:FP 0 "register_operand" "=f")
8567 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
8570 [(set_attr "op_type" "RRE")
8571 (set_attr "type" "fsimp<mode>")])
8573 ; lnxbr, lndbr, lnebr
8574 ; FIXME: wflndb does not clobber cc
8575 (define_insn "*negabs<mode>2"
8576 [(set (match_operand:BFP 0 "register_operand" "=f,v")
8577 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))))
8578 (clobber (reg:CC CC_REGNUM))]
8583 [(set_attr "op_type" "RRE,VRR")
8584 (set_attr "cpu_facility" "*,vx")
8585 (set_attr "type" "fsimp<mode>,*")
8586 (set_attr "enabled" "*,<DFDI>")])
8589 ;;- Square root instructions.
8593 ; sqrt(df|sf)2 instruction pattern(s).
8596 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
8597 (define_insn "sqrt<mode>2"
8598 [(set (match_operand:BFP 0 "register_operand" "=f,f,v")
8599 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))]
8605 [(set_attr "op_type" "RRE,RXE,VRR")
8606 (set_attr "type" "fsqrt<mode>")
8607 (set_attr "cpu_facility" "*,*,vx")
8608 (set_attr "enabled" "*,<DSF>,<DFDI>")])
8612 ;;- One complement instructions.
8616 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
8619 (define_expand "one_cmpl<mode>2"
8621 [(set (match_operand:INT 0 "register_operand" "")
8622 (xor:INT (match_operand:INT 1 "register_operand" "")
8624 (clobber (reg:CC CC_REGNUM))])]
8630 ;; Find leftmost bit instructions.
8633 (define_expand "clzdi2"
8634 [(set (match_operand:DI 0 "register_operand" "=d")
8635 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
8636 "TARGET_EXTIMM && TARGET_ZARCH"
8640 rtx wide_reg = gen_reg_rtx (TImode);
8641 rtx msb = gen_rtx_CONST_INT (DImode, HOST_WIDE_INT_1U << 63);
8643 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
8645 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
8647 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
8648 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
8653 (define_insn "clztidi2"
8654 [(set (match_operand:TI 0 "register_operand" "=d")
8658 (xor:DI (match_operand:DI 1 "register_operand" "d")
8659 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
8660 (subreg:SI (clz:DI (match_dup 1)) 4))))
8663 (zero_extend:TI (clz:DI (match_dup 1)))))
8664 (clobber (reg:CC CC_REGNUM))]
8665 "UINTVAL (operands[2]) == HOST_WIDE_INT_1U << 63
8666 && TARGET_EXTIMM && TARGET_ZARCH"
8668 [(set_attr "op_type" "RRE")])
8672 ;;- Rotate instructions.
8676 ; rotl(di|si)3 instruction pattern(s).
8679 (define_expand "rotl<mode>3"
8680 [(set (match_operand:GPR 0 "register_operand" "")
8681 (rotate:GPR (match_operand:GPR 1 "register_operand" "")
8682 (match_operand:SI 2 "nonmemory_operand" "")))]
8687 (define_insn "*rotl<mode>3<addr_style_op><masked_op>"
8688 [(set (match_operand:GPR 0 "register_operand" "=d")
8689 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
8690 (match_operand:SI 2 "nonmemory_operand" "an")))]
8692 "rll<g>\t%0,%1,<addr_style_op_ops>"
8693 [(set_attr "op_type" "RSE")
8694 (set_attr "atype" "reg")
8695 (set_attr "z10prop" "z10_super_E1")])
8699 ;;- Shift instructions.
8703 ; (ashl|lshr)(di|si)3 instruction pattern(s).
8704 ; Left shifts and logical right shifts
8706 (define_expand "<shift><mode>3"
8707 [(set (match_operand:DSI 0 "register_operand" "")
8708 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
8709 (match_operand:SI 2 "nonmemory_operand" "")))]
8713 ; ESA 64 bit register pair shift with reg or imm shift count
8715 (define_insn "*<shift>di3_31<addr_style_op><masked_op>"
8716 [(set (match_operand:DI 0 "register_operand" "=d")
8717 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
8718 (match_operand:SI 2 "nonmemory_operand" "an")))]
8720 "s<lr>dl\t%0,<addr_style_op_ops>"
8721 [(set_attr "op_type" "RS")
8722 (set_attr "atype" "reg")
8723 (set_attr "z196prop" "z196_cracked")])
8726 ; 64 bit register shift with reg or imm shift count
8727 ; sll, srl, sllg, srlg, sllk, srlk
8728 (define_insn "*<shift><mode>3<addr_style_op><masked_op>"
8729 [(set (match_operand:GPR 0 "register_operand" "=d, d")
8730 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
8731 (match_operand:SI 2 "nonmemory_operand" "an,an")))]
8734 s<lr>l<g>\t%0,<1><addr_style_op_ops>
8735 s<lr>l<gk>\t%0,%1,<addr_style_op_ops>"
8736 [(set_attr "op_type" "RS<E>,RSY")
8737 (set_attr "atype" "reg,reg")
8738 (set_attr "cpu_facility" "*,z196")
8739 (set_attr "z10prop" "z10_super_E1,*")])
8742 ; ashr(di|si)3 instruction pattern(s).
8743 ; Arithmetic right shifts
8745 (define_expand "ashr<mode>3"
8747 [(set (match_operand:DSI 0 "register_operand" "")
8748 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
8749 (match_operand:SI 2 "nonmemory_operand" "")))
8750 (clobber (reg:CC CC_REGNUM))])]
8754 ; FIXME: The number of alternatives is doubled here to match the fix
8755 ; number of 2 in the subst pattern for the (clobber (match_scratch...
8756 ; The right fix should be to support match_scratch in the output
8757 ; pattern of a define_subst.
8758 (define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>"
8759 [(set (match_operand:DI 0 "register_operand" "=d, d")
8760 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0, 0")
8761 (match_operand:SI 2 "nonmemory_operand" "an,an")))
8762 (clobber (reg:CC CC_REGNUM))]
8765 srda\t%0,<addr_style_op_cc_ops>
8766 srda\t%0,<addr_style_op_cc_ops>"
8767 [(set_attr "op_type" "RS")
8768 (set_attr "atype" "reg")])
8772 (define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>"
8773 [(set (match_operand:GPR 0 "register_operand" "=d, d")
8774 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
8775 (match_operand:SI 2 "nonmemory_operand" "an,an")))
8776 (clobber (reg:CC CC_REGNUM))]
8779 sra<g>\t%0,<1><addr_style_op_cc_ops>
8780 sra<gk>\t%0,%1,<addr_style_op_cc_ops>"
8781 [(set_attr "op_type" "RS<E>,RSY")
8782 (set_attr "atype" "reg")
8783 (set_attr "cpu_facility" "*,z196")
8784 (set_attr "z10prop" "z10_super_E1,*")])
8788 ;; Branch instruction patterns.
8791 (define_expand "cbranch<mode>4"
8793 (if_then_else (match_operator 0 "comparison_operator"
8794 [(match_operand:GPR 1 "register_operand" "")
8795 (match_operand:GPR 2 "general_operand" "")])
8796 (label_ref (match_operand 3 "" ""))
8799 "s390_emit_jump (operands[3],
8800 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8803 (define_expand "cbranch<mode>4"
8805 (if_then_else (match_operator 0 "comparison_operator"
8806 [(match_operand:FP 1 "register_operand" "")
8807 (match_operand:FP 2 "general_operand" "")])
8808 (label_ref (match_operand 3 "" ""))
8811 "s390_emit_jump (operands[3],
8812 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8815 (define_expand "cbranchcc4"
8817 (if_then_else (match_operator 0 "s390_comparison"
8818 [(match_operand 1 "cc_reg_operand" "")
8819 (match_operand 2 "const_int_operand" "")])
8820 (label_ref (match_operand 3 "" ""))
8827 ;;- Conditional jump instructions.
8830 (define_insn "*cjump_64"
8833 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8834 (match_operand 2 "const_int_operand" "")])
8835 (label_ref (match_operand 0 "" ""))
8839 if (get_attr_length (insn) == 4)
8842 return "jg%C1\t%l0";
8844 [(set_attr "op_type" "RI")
8845 (set_attr "type" "branch")
8846 (set (attr "length")
8847 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8848 (const_int 4) (const_int 6)))])
8850 (define_insn "*cjump_long"
8853 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8854 (match_operand 0 "address_operand" "ZQZR")
8856 "!TARGET_INDIRECT_BRANCH_NOBP_JUMP"
8858 if (get_attr_op_type (insn) == OP_TYPE_RR)
8863 [(set (attr "op_type")
8864 (if_then_else (match_operand 0 "register_operand" "")
8865 (const_string "RR") (const_string "RX")))
8866 (set (attr "mnemonic")
8867 (if_then_else (match_operand 0 "register_operand" "")
8868 (const_string "bcr") (const_string "bc")))
8869 (set_attr "type" "branch")
8870 (set_attr "atype" "agen")])
8872 ;; A conditional return instruction.
8873 (define_insn "*c<code>"
8876 (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8879 "s390_can_use_<code>_insn ()"
8881 if (TARGET_INDIRECT_BRANCH_NOBP_RET)
8883 s390_indirect_branch_via_thunk (RETURN_REGNUM,
8886 s390_indirect_branch_type_return);
8890 return "b%C0r\t%%r14";
8892 [(set (attr "op_type")
8893 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
8894 (const_string "RIL")
8895 (const_string "RR")))
8896 (set (attr "mnemonic")
8897 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
8898 (const_string "brcl")
8899 (const_string "bcr")))
8900 (set_attr "type" "jsr")
8901 (set_attr "atype" "agen")])
8904 ;;- Negated conditional jump instructions.
8907 (define_insn "*icjump_64"
8910 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8912 (label_ref (match_operand 0 "" ""))))]
8915 if (get_attr_length (insn) == 4)
8918 return "jg%D1\t%l0";
8920 [(set_attr "op_type" "RI")
8921 (set_attr "type" "branch")
8922 (set (attr "length")
8923 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8924 (const_int 4) (const_int 6)))])
8926 (define_insn "*icjump_long"
8929 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8931 (match_operand 0 "address_operand" "ZQZR")))]
8932 "!TARGET_INDIRECT_BRANCH_NOBP_JUMP"
8934 if (get_attr_op_type (insn) == OP_TYPE_RR)
8939 [(set (attr "op_type")
8940 (if_then_else (match_operand 0 "register_operand" "")
8941 (const_string "RR") (const_string "RX")))
8942 (set (attr "mnemonic")
8943 (if_then_else (match_operand 0 "register_operand" "")
8944 (const_string "bcr") (const_string "bc")))
8945 (set_attr "type" "branch")
8946 (set_attr "atype" "agen")])
8949 ;;- Trap instructions.
8953 [(trap_if (const_int 1) (const_int 0))]
8956 [(set_attr "op_type" "RI")
8957 (set_attr "type" "branch")])
8959 (define_expand "ctrap<mode>4"
8960 [(trap_if (match_operator 0 "comparison_operator"
8961 [(match_operand:GPR 1 "register_operand" "")
8962 (match_operand:GPR 2 "general_operand" "")])
8963 (match_operand 3 "const0_operand" ""))]
8966 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8967 operands[1], operands[2]);
8968 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8972 (define_expand "ctrap<mode>4"
8973 [(trap_if (match_operator 0 "comparison_operator"
8974 [(match_operand:FP 1 "register_operand" "")
8975 (match_operand:FP 2 "general_operand" "")])
8976 (match_operand 3 "const0_operand" ""))]
8979 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8980 operands[1], operands[2]);
8981 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8985 (define_insn "condtrap"
8986 [(trap_if (match_operator 0 "s390_comparison"
8987 [(match_operand 1 "cc_reg_operand" "c")
8992 [(set_attr "op_type" "RI")
8993 (set_attr "type" "branch")])
8995 ; crt, cgrt, cit, cgit
8996 (define_insn "*cmp_and_trap_signed_int<mode>"
8997 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8998 [(match_operand:GPR 1 "register_operand" "d,d")
8999 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
9005 [(set_attr "op_type" "RRF,RIE")
9006 (set_attr "type" "branch")
9007 (set_attr "z10prop" "z10_super_c,z10_super")])
9009 ; clrt, clgrt, clfit, clgit, clt, clgt
9010 (define_insn "*cmp_and_trap_unsigned_int<mode>"
9011 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
9012 [(match_operand:GPR 1 "register_operand" "d,d,d")
9013 (match_operand:GPR 2 "general_operand" "d,D,T")])
9020 [(set_attr "op_type" "RRF,RIE,RSY")
9021 (set_attr "type" "branch")
9022 (set_attr "z10prop" "z10_super_c,z10_super,*")
9023 (set_attr "cpu_facility" "z10,z10,zEC12")])
9026 (define_insn "*load_and_trap<mode>"
9027 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T")
9030 (set (match_operand:GPR 1 "register_operand" "=d")
9034 [(set_attr "op_type" "RXY")])
9038 ;;- Loop instructions.
9040 ;; This is all complicated by the fact that since this is a jump insn
9041 ;; we must handle our own output reloads.
9045 ; This splitter will be matched by combine and has to add the 2 moves
9046 ; necessary to load the compare and the increment values into a
9047 ; register pair as needed by brxle.
9049 (define_insn_and_split "*brx_stage1_<GPR:mode>"
9052 (match_operator 6 "s390_brx_operator"
9053 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
9054 (match_operand:GPR 2 "general_operand" ""))
9055 (match_operand:GPR 3 "register_operand" "")])
9056 (label_ref (match_operand 0 "" ""))
9058 (set (match_operand:GPR 4 "nonimmediate_operand" "")
9059 (plus:GPR (match_dup 1) (match_dup 2)))
9060 (clobber (match_scratch:GPR 5 ""))]
9063 "!reload_completed && !reload_in_progress"
9064 [(set (match_dup 7) (match_dup 2)) ; the increment
9065 (set (match_dup 8) (match_dup 3)) ; the comparison value
9066 (parallel [(set (pc)
9069 [(plus:GPR (match_dup 1) (match_dup 7))
9071 (label_ref (match_dup 0))
9074 (plus:GPR (match_dup 1) (match_dup 7)))
9075 (clobber (match_dup 5))
9076 (clobber (reg:CC CC_REGNUM))])]
9078 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
9079 operands[7] = gen_lowpart (<GPR:MODE>mode,
9080 gen_highpart (word_mode, dreg));
9081 operands[8] = gen_lowpart (<GPR:MODE>mode,
9082 gen_lowpart (word_mode, dreg));
9087 (define_insn_and_split "*brxg_64bit"
9090 (match_operator 5 "s390_brx_operator"
9091 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
9092 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
9093 (subreg:DI (match_dup 2) 8)])
9094 (label_ref (match_operand 0 "" ""))
9096 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
9097 (plus:DI (match_dup 1)
9098 (subreg:DI (match_dup 2) 0)))
9099 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
9100 (clobber (reg:CC CC_REGNUM))]
9103 if (which_alternative != 0)
9105 else if (get_attr_length (insn) == 6)
9106 return "brx%E5g\t%1,%2,%l0";
9108 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
9110 "&& reload_completed
9111 && (!REG_P (operands[3])
9112 || !rtx_equal_p (operands[1], operands[3]))"
9113 [(set (match_dup 4) (match_dup 1))
9114 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
9115 (clobber (reg:CC CC_REGNUM))])
9116 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
9117 (set (match_dup 3) (match_dup 4))
9118 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9119 (label_ref (match_dup 0))
9122 [(set_attr "op_type" "RIE")
9123 (set_attr "type" "branch")
9124 (set (attr "length")
9125 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9126 (const_int 6) (const_int 16)))])
9130 (define_insn_and_split "*brx_64bit"
9133 (match_operator 5 "s390_brx_operator"
9134 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
9135 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
9136 (subreg:SI (match_dup 2) 12)])
9137 (label_ref (match_operand 0 "" ""))
9139 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
9140 (plus:SI (match_dup 1)
9141 (subreg:SI (match_dup 2) 4)))
9142 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
9143 (clobber (reg:CC CC_REGNUM))]
9146 if (which_alternative != 0)
9148 else if (get_attr_length (insn) == 6)
9149 return "brx%C5\t%1,%2,%l0";
9151 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
9153 "&& reload_completed
9154 && (!REG_P (operands[3])
9155 || !rtx_equal_p (operands[1], operands[3]))"
9156 [(set (match_dup 4) (match_dup 1))
9157 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
9158 (clobber (reg:CC CC_REGNUM))])
9159 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
9160 (set (match_dup 3) (match_dup 4))
9161 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9162 (label_ref (match_dup 0))
9165 [(set_attr "op_type" "RSI")
9166 (set_attr "type" "branch")
9167 (set (attr "length")
9168 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9169 (const_int 6) (const_int 14)))])
9173 (define_insn_and_split "*brx_31bit"
9176 (match_operator 5 "s390_brx_operator"
9177 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
9178 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
9179 (subreg:SI (match_dup 2) 4)])
9180 (label_ref (match_operand 0 "" ""))
9182 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
9183 (plus:SI (match_dup 1)
9184 (subreg:SI (match_dup 2) 0)))
9185 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
9186 (clobber (reg:CC CC_REGNUM))]
9189 if (which_alternative != 0)
9191 else if (get_attr_length (insn) == 6)
9192 return "brx%C5\t%1,%2,%l0";
9194 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
9196 "&& reload_completed
9197 && (!REG_P (operands[3])
9198 || !rtx_equal_p (operands[1], operands[3]))"
9199 [(set (match_dup 4) (match_dup 1))
9200 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
9201 (clobber (reg:CC CC_REGNUM))])
9202 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
9203 (set (match_dup 3) (match_dup 4))
9204 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9205 (label_ref (match_dup 0))
9208 [(set_attr "op_type" "RSI")
9209 (set_attr "type" "branch")
9210 (set (attr "length")
9211 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9212 (const_int 6) (const_int 14)))])
9217 (define_expand "doloop_end"
9218 [(use (match_operand 0 "" "")) ; loop pseudo
9219 (use (match_operand 1 "" ""))] ; label
9222 if (GET_MODE (operands[0]) == SImode)
9223 emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
9224 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
9225 emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
9232 (define_insn_and_split "doloop_si64"
9235 (ne (match_operand:SI 1 "register_operand" "d,d,d")
9237 (label_ref (match_operand 0 "" ""))
9239 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9240 (plus:SI (match_dup 1) (const_int -1)))
9241 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9242 (clobber (reg:CC CC_REGNUM))]
9245 if (which_alternative != 0)
9247 else if (get_attr_length (insn) == 4)
9248 return "brct\t%1,%l0";
9250 return "ahi\t%1,-1\;jgne\t%l0";
9252 "&& reload_completed
9253 && (! REG_P (operands[2])
9254 || ! rtx_equal_p (operands[1], operands[2]))"
9255 [(set (match_dup 3) (match_dup 1))
9256 (parallel [(set (reg:CCAN CC_REGNUM)
9257 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9259 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9260 (set (match_dup 2) (match_dup 3))
9261 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9262 (label_ref (match_dup 0))
9265 [(set_attr "op_type" "RI")
9266 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9267 ; hurt us in the (rare) case of ahi.
9268 (set_attr "z10prop" "z10_super_E1")
9269 (set_attr "type" "branch")
9270 (set (attr "length")
9271 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9272 (const_int 4) (const_int 10)))])
9274 (define_insn_and_split "doloop_di"
9277 (ne (match_operand:DI 1 "register_operand" "d,d,d")
9279 (label_ref (match_operand 0 "" ""))
9281 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
9282 (plus:DI (match_dup 1) (const_int -1)))
9283 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
9284 (clobber (reg:CC CC_REGNUM))]
9287 if (which_alternative != 0)
9289 else if (get_attr_length (insn) == 4)
9290 return "brctg\t%1,%l0";
9292 return "aghi\t%1,-1\;jgne\t%l0";
9294 "&& reload_completed
9295 && (! REG_P (operands[2])
9296 || ! rtx_equal_p (operands[1], operands[2]))"
9297 [(set (match_dup 3) (match_dup 1))
9298 (parallel [(set (reg:CCAN CC_REGNUM)
9299 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
9301 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
9302 (set (match_dup 2) (match_dup 3))
9303 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9304 (label_ref (match_dup 0))
9307 [(set_attr "op_type" "RI")
9308 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9309 ; hurt us in the (rare) case of ahi.
9310 (set_attr "z10prop" "z10_super_E1")
9311 (set_attr "type" "branch")
9312 (set (attr "length")
9313 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9314 (const_int 4) (const_int 10)))])
9317 ;;- Unconditional jump instructions.
9321 ; jump instruction pattern(s).
9324 (define_expand "jump"
9325 [(match_operand 0 "" "")]
9327 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
9329 (define_insn "*jump64"
9330 [(set (pc) (label_ref (match_operand 0 "" "")))]
9333 if (get_attr_length (insn) == 4)
9338 [(set_attr "op_type" "RI")
9339 (set_attr "type" "branch")
9340 (set (attr "length")
9341 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9342 (const_int 4) (const_int 6)))])
9345 ; indirect-jump instruction pattern(s).
9348 (define_expand "indirect_jump"
9349 [(set (pc) (match_operand 0 "nonimmediate_operand" ""))]
9352 if (address_operand (operands[0], GET_MODE (operands[0])))
9355 && GET_MODE (operands[0]) == Pmode
9356 && memory_operand (operands[0], Pmode))
9359 operands[0] = force_reg (Pmode, operands[0]);
9361 if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK)
9363 operands[0] = force_reg (Pmode, operands[0]);
9367 emit_jump_insn (gen_indirect_jump_via_thunkdi_z10 (operands[0]));
9369 emit_jump_insn (gen_indirect_jump_via_thunksi_z10 (operands[0]));
9374 emit_jump_insn (gen_indirect_jump_via_thunkdi (operands[0]));
9376 emit_jump_insn (gen_indirect_jump_via_thunksi (operands[0]));
9381 if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK)
9383 operands[0] = force_reg (Pmode, operands[0]);
9384 rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
9388 emit_jump_insn (gen_indirect_jump_via_inlinethunkdi_z10 (operands[0],
9391 emit_jump_insn (gen_indirect_jump_via_inlinethunksi_z10 (operands[0],
9397 emit_jump_insn (gen_indirect_jump_via_inlinethunkdi (operands[0],
9399 force_reg (Pmode, label_ref)));
9401 emit_jump_insn (gen_indirect_jump_via_inlinethunksi (operands[0],
9403 force_reg (Pmode, label_ref)));
9409 (define_insn "*indirect_jump"
9411 (match_operand 0 "address_operand" "ZR"))]
9412 "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK"
9414 if (get_attr_op_type (insn) == OP_TYPE_RR)
9419 [(set (attr "op_type")
9420 (if_then_else (match_operand 0 "register_operand" "")
9421 (const_string "RR") (const_string "RX")))
9422 (set (attr "mnemonic")
9423 (if_then_else (match_operand 0 "register_operand" "")
9424 (const_string "br") (const_string "b")))
9425 (set_attr "type" "branch")
9426 (set_attr "atype" "agen")])
9428 (define_insn "indirect_jump_via_thunk<mode>_z10"
9430 (match_operand:P 0 "register_operand" "a"))]
9431 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK
9434 s390_indirect_branch_via_thunk (REGNO (operands[0]),
9437 s390_indirect_branch_type_jump);
9440 [(set_attr "op_type" "RIL")
9441 (set_attr "mnemonic" "jg")
9442 (set_attr "type" "branch")
9443 (set_attr "atype" "agen")])
9445 (define_insn "indirect_jump_via_thunk<mode>"
9447 (match_operand:P 0 "register_operand" " a"))
9448 (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))]
9449 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK
9452 s390_indirect_branch_via_thunk (REGNO (operands[0]),
9455 s390_indirect_branch_type_jump);
9458 [(set_attr "op_type" "RIL")
9459 (set_attr "mnemonic" "jg")
9460 (set_attr "type" "branch")
9461 (set_attr "atype" "agen")])
9464 ; The label_ref is wrapped into an if_then_else in order to hide it
9465 ; from mark_jump_label. Without this the label_ref would become the
9466 ; ONLY jump target of that jump breaking the control flow graph.
9467 (define_insn "indirect_jump_via_inlinethunk<mode>_z10"
9468 [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X")
9471 (const_int 0)] UNSPEC_EXECUTE_JUMP)
9472 (set (pc) (match_operand:P 0 "register_operand" "a"))]
9473 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK
9476 s390_indirect_branch_via_inline_thunk (operands[1]);
9479 [(set_attr "op_type" "RIL")
9480 (set_attr "type" "branch")
9481 (set_attr "length" "10")])
9483 (define_insn "indirect_jump_via_inlinethunk<mode>"
9484 [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X")
9487 (match_operand:P 2 "register_operand" "a")] UNSPEC_EXECUTE_JUMP)
9488 (set (pc) (match_operand:P 0 "register_operand" "a"))]
9489 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK
9492 s390_indirect_branch_via_inline_thunk (operands[2]);
9495 [(set_attr "op_type" "RX")
9496 (set_attr "type" "branch")
9497 (set_attr "length" "8")])
9499 ; FIXME: LRA does not appear to be able to deal with MEMs being
9500 ; checked against address constraints like ZR above. So make this a
9501 ; separate pattern for now.
9502 (define_insn "*indirect2_jump"
9504 (match_operand 0 "nonimmediate_operand" "a,T"))]
9505 "!TARGET_INDIRECT_BRANCH_NOBP_JUMP"
9509 [(set_attr "op_type" "RR,RXY")
9510 (set_attr "type" "branch")
9511 (set_attr "atype" "agen")
9512 (set_attr "cpu_facility" "*,z14")])
9515 ; casesi instruction pattern(s).
9518 (define_expand "casesi_jump"
9520 [(set (pc) (match_operand 0 "address_operand"))
9521 (use (label_ref (match_operand 1 "")))])]
9524 if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK)
9526 operands[0] = force_reg (GET_MODE (operands[0]), operands[0]);
9531 emit_jump_insn (gen_casesi_jump_via_thunkdi_z10 (operands[0],
9534 emit_jump_insn (gen_casesi_jump_via_thunksi_z10 (operands[0],
9540 emit_jump_insn (gen_casesi_jump_via_thunkdi (operands[0],
9543 emit_jump_insn (gen_casesi_jump_via_thunksi (operands[0],
9549 if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK)
9551 operands[0] = force_reg (Pmode, operands[0]);
9552 rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
9556 emit_jump_insn (gen_casesi_jump_via_inlinethunkdi_z10 (operands[0],
9560 emit_jump_insn (gen_casesi_jump_via_inlinethunksi_z10 (operands[0],
9567 emit_jump_insn (gen_casesi_jump_via_inlinethunkdi (operands[0],
9570 force_reg (Pmode, label_ref)));
9572 emit_jump_insn (gen_casesi_jump_via_inlinethunksi (operands[0],
9575 force_reg (Pmode, label_ref)));
9581 (define_insn "*casesi_jump"
9582 [(set (pc) (match_operand 0 "address_operand" "ZR"))
9583 (use (label_ref (match_operand 1 "" "")))]
9584 "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK"
9586 if (get_attr_op_type (insn) == OP_TYPE_RR)
9591 [(set (attr "op_type")
9592 (if_then_else (match_operand 0 "register_operand" "")
9593 (const_string "RR") (const_string "RX")))
9594 (set (attr "mnemonic")
9595 (if_then_else (match_operand 0 "register_operand" "")
9596 (const_string "br") (const_string "b")))
9597 (set_attr "type" "branch")
9598 (set_attr "atype" "agen")])
9600 (define_insn "casesi_jump_via_thunk<mode>_z10"
9601 [(set (pc) (match_operand:P 0 "register_operand" "a"))
9602 (use (label_ref (match_operand 1 "" "")))]
9603 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK
9606 s390_indirect_branch_via_thunk (REGNO (operands[0]),
9609 s390_indirect_branch_type_jump);
9612 [(set_attr "op_type" "RIL")
9613 (set_attr "mnemonic" "jg")
9614 (set_attr "type" "branch")
9615 (set_attr "atype" "agen")])
9617 (define_insn "casesi_jump_via_thunk<mode>"
9618 [(set (pc) (match_operand:P 0 "register_operand" "a"))
9619 (use (label_ref (match_operand 1 "" "")))
9620 (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))]
9621 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK
9624 s390_indirect_branch_via_thunk (REGNO (operands[0]),
9627 s390_indirect_branch_type_jump);
9630 [(set_attr "op_type" "RIL")
9631 (set_attr "mnemonic" "jg")
9632 (set_attr "type" "branch")
9633 (set_attr "atype" "agen")])
9636 ; The label_ref is wrapped into an if_then_else in order to hide it
9637 ; from mark_jump_label. Without this the label_ref would become the
9638 ; ONLY jump target of that jump breaking the control flow graph.
9639 (define_insn "casesi_jump_via_inlinethunk<mode>_z10"
9640 [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X")
9643 (const_int 0)] UNSPEC_EXECUTE_JUMP)
9644 (set (pc) (match_operand:P 0 "register_operand" "a"))
9645 (use (label_ref (match_operand 1 "" "")))]
9646 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK
9649 s390_indirect_branch_via_inline_thunk (operands[2]);
9652 [(set_attr "op_type" "RIL")
9653 (set_attr "type" "cs")
9654 (set_attr "length" "10")])
9656 (define_insn "casesi_jump_via_inlinethunk<mode>"
9657 [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X")
9660 (match_operand:P 3 "register_operand" "a")] UNSPEC_EXECUTE_JUMP)
9661 (set (pc) (match_operand:P 0 "register_operand" "a"))
9662 (use (label_ref (match_operand 1 "" "")))]
9663 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK
9666 s390_indirect_branch_via_inline_thunk (operands[3]);
9669 [(set_attr "op_type" "RX")
9670 (set_attr "type" "cs")
9671 (set_attr "length" "8")])
9673 (define_expand "casesi"
9674 [(match_operand:SI 0 "general_operand" "")
9675 (match_operand:SI 1 "general_operand" "")
9676 (match_operand:SI 2 "general_operand" "")
9677 (label_ref (match_operand 3 "" ""))
9678 (label_ref (match_operand 4 "" ""))]
9681 rtx index = gen_reg_rtx (SImode);
9682 rtx base = gen_reg_rtx (Pmode);
9683 rtx target = gen_reg_rtx (Pmode);
9685 emit_move_insn (index, operands[0]);
9686 emit_insn (gen_subsi3 (index, index, operands[1]));
9687 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
9690 if (Pmode != SImode)
9691 index = convert_to_mode (Pmode, index, 1);
9692 if (GET_CODE (index) != REG)
9693 index = copy_to_mode_reg (Pmode, index);
9696 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
9698 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
9700 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
9702 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
9703 emit_move_insn (target, index);
9706 target = gen_rtx_PLUS (Pmode, base, target);
9707 emit_jump_insn (gen_casesi_jump (target, operands[3]));
9714 ;;- Jump to subroutine.
9719 ; untyped call instruction pattern(s).
9722 ;; Call subroutine returning any type.
9723 (define_expand "untyped_call"
9724 [(parallel [(call (match_operand 0 "" "")
9726 (match_operand 1 "" "")
9727 (match_operand 2 "" "")])]
9732 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
9734 for (i = 0; i < XVECLEN (operands[2], 0); i++)
9736 rtx set = XVECEXP (operands[2], 0, i);
9737 emit_move_insn (SET_DEST (set), SET_SRC (set));
9740 /* The optimizer does not know that the call sets the function value
9741 registers we stored in the result block. We avoid problems by
9742 claiming that all hard registers are used and clobbered at this
9744 emit_insn (gen_blockage ());
9749 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
9750 ;; all of memory. This blocks insns from being moved across this point.
9752 (define_insn "blockage"
9753 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
9756 [(set_attr "type" "none")
9757 (set_attr "length" "0")])
9763 (define_expand "sibcall"
9764 [(call (match_operand 0 "" "")
9765 (match_operand 1 "" ""))]
9768 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
9772 (define_insn "*sibcall_br"
9773 [(call (mem:QI (reg SIBCALL_REGNUM))
9774 (match_operand 0 "const_int_operand" "n"))]
9775 "SIBLING_CALL_P (insn)
9776 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
9778 if (TARGET_INDIRECT_BRANCH_NOBP_CALL)
9780 gcc_assert (TARGET_CPU_Z10);
9781 s390_indirect_branch_via_thunk (SIBCALL_REGNUM,
9784 s390_indirect_branch_type_call);
9790 [(set (attr "op_type")
9791 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL")
9792 (const_string "RIL")
9793 (const_string "RR")))
9794 (set (attr "mnemonic")
9795 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL")
9797 (const_string "br")))
9798 (set_attr "type" "branch")
9799 (set_attr "atype" "agen")])
9801 (define_insn "*sibcall_brc"
9802 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9803 (match_operand 1 "const_int_operand" "n"))]
9804 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9806 [(set_attr "op_type" "RI")
9807 (set_attr "type" "branch")])
9809 (define_insn "*sibcall_brcl"
9810 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9811 (match_operand 1 "const_int_operand" "n"))]
9812 "SIBLING_CALL_P (insn)"
9814 [(set_attr "op_type" "RIL")
9815 (set_attr "type" "branch")])
9818 ; sibcall_value patterns
9821 (define_expand "sibcall_value"
9822 [(set (match_operand 0 "" "")
9823 (call (match_operand 1 "" "")
9824 (match_operand 2 "" "")))]
9827 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
9831 (define_insn "*sibcall_value_br"
9832 [(set (match_operand 0 "" "")
9833 (call (mem:QI (reg SIBCALL_REGNUM))
9834 (match_operand 1 "const_int_operand" "n")))]
9835 "SIBLING_CALL_P (insn)
9836 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
9838 if (TARGET_INDIRECT_BRANCH_NOBP_CALL)
9840 gcc_assert (TARGET_CPU_Z10);
9841 s390_indirect_branch_via_thunk (SIBCALL_REGNUM,
9844 s390_indirect_branch_type_call);
9850 [(set (attr "op_type")
9851 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL")
9852 (const_string "RIL")
9853 (const_string "RR")))
9854 (set (attr "mnemonic")
9855 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL")
9857 (const_string "br")))
9858 (set_attr "type" "branch")
9859 (set_attr "atype" "agen")])
9861 (define_insn "*sibcall_value_brc"
9862 [(set (match_operand 0 "" "")
9863 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9864 (match_operand 2 "const_int_operand" "n")))]
9865 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9867 [(set_attr "op_type" "RI")
9868 (set_attr "type" "branch")])
9870 (define_insn "*sibcall_value_brcl"
9871 [(set (match_operand 0 "" "")
9872 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9873 (match_operand 2 "const_int_operand" "n")))]
9874 "SIBLING_CALL_P (insn)"
9876 [(set_attr "op_type" "RIL")
9877 (set_attr "type" "branch")])
9881 ; call instruction pattern(s).
9884 (define_expand "call"
9885 [(call (match_operand 0 "" "")
9886 (match_operand 1 "" ""))
9887 (use (match_operand 2 "" ""))]
9890 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
9891 gen_rtx_REG (Pmode, RETURN_REGNUM));
9895 (define_insn "*bras"
9896 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9897 (match_operand 1 "const_int_operand" "n"))
9898 (clobber (match_operand 2 "register_operand" "=r"))]
9899 "!SIBLING_CALL_P (insn)
9900 && TARGET_SMALL_EXEC
9901 && GET_MODE (operands[2]) == Pmode"
9903 [(set_attr "op_type" "RI")
9904 (set_attr "type" "jsr")
9905 (set_attr "z196prop" "z196_cracked")])
9907 (define_insn "*brasl"
9908 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9909 (match_operand 1 "const_int_operand" "n"))
9910 (clobber (match_operand 2 "register_operand" "=r"))]
9911 "!SIBLING_CALL_P (insn)
9913 && GET_MODE (operands[2]) == Pmode"
9915 [(set_attr "op_type" "RIL")
9916 (set_attr "type" "jsr")
9917 (set_attr "z196prop" "z196_cracked")])
9919 (define_insn "*basr"
9920 [(call (mem:QI (match_operand 0 "address_operand" "ZR"))
9921 (match_operand 1 "const_int_operand" "n"))
9922 (clobber (match_operand 2 "register_operand" "=r"))]
9923 "!TARGET_INDIRECT_BRANCH_NOBP_CALL
9924 && !SIBLING_CALL_P (insn)
9925 && GET_MODE (operands[2]) == Pmode"
9927 if (get_attr_op_type (insn) == OP_TYPE_RR)
9928 return "basr\t%2,%0";
9930 return "bas\t%2,%a0";
9932 [(set (attr "op_type")
9933 (if_then_else (match_operand 0 "register_operand" "")
9934 (const_string "RR") (const_string "RX")))
9935 (set (attr "mnemonic")
9936 (if_then_else (match_operand 0 "register_operand" "")
9937 (const_string "basr") (const_string "bas")))
9938 (set_attr "type" "jsr")
9939 (set_attr "atype" "agen")
9940 (set_attr "z196prop" "z196_cracked")])
9942 (define_insn "*basr_via_thunk<mode>_z10"
9943 [(call (mem:QI (match_operand:P 0 "register_operand" "a"))
9944 (match_operand 1 "const_int_operand" "n"))
9945 (clobber (match_operand:P 2 "register_operand" "=&r"))]
9946 "TARGET_INDIRECT_BRANCH_NOBP_CALL
9948 && !SIBLING_CALL_P (insn)"
9950 s390_indirect_branch_via_thunk (REGNO (operands[0]),
9951 REGNO (operands[2]),
9953 s390_indirect_branch_type_call);
9956 [(set_attr "op_type" "RIL")
9957 (set_attr "mnemonic" "brasl")
9958 (set_attr "type" "jsr")
9959 (set_attr "atype" "agen")
9960 (set_attr "z196prop" "z196_cracked")])
9962 (define_insn "*basr_via_thunk<mode>"
9963 [(call (mem:QI (match_operand:P 0 "register_operand" "a"))
9964 (match_operand 1 "const_int_operand" "n"))
9965 (clobber (match_operand:P 2 "register_operand" "=&r"))
9966 (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))]
9967 "TARGET_INDIRECT_BRANCH_NOBP_CALL
9969 && !SIBLING_CALL_P (insn)"
9971 s390_indirect_branch_via_thunk (REGNO (operands[0]),
9972 REGNO (operands[2]),
9974 s390_indirect_branch_type_call);
9977 [(set_attr "op_type" "RIL")
9978 (set_attr "mnemonic" "brasl")
9979 (set_attr "type" "jsr")
9980 (set_attr "atype" "agen")
9981 (set_attr "z196prop" "z196_cracked")])
9984 ; call_value instruction pattern(s).
9987 (define_expand "call_value"
9988 [(set (match_operand 0 "" "")
9989 (call (match_operand 1 "" "")
9990 (match_operand 2 "" "")))
9991 (use (match_operand 3 "" ""))]
9994 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
9995 gen_rtx_REG (Pmode, RETURN_REGNUM));
9999 (define_insn "*bras_r"
10000 [(set (match_operand 0 "" "")
10001 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
10002 (match_operand:SI 2 "const_int_operand" "n")))
10003 (clobber (match_operand 3 "register_operand" "=r"))]
10004 "!SIBLING_CALL_P (insn)
10005 && TARGET_SMALL_EXEC
10006 && GET_MODE (operands[3]) == Pmode"
10008 [(set_attr "op_type" "RI")
10009 (set_attr "type" "jsr")
10010 (set_attr "z196prop" "z196_cracked")])
10012 (define_insn "*brasl_r"
10013 [(set (match_operand 0 "" "")
10014 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
10015 (match_operand 2 "const_int_operand" "n")))
10016 (clobber (match_operand 3 "register_operand" "=r"))]
10017 "!SIBLING_CALL_P (insn)
10019 && GET_MODE (operands[3]) == Pmode"
10021 [(set_attr "op_type" "RIL")
10022 (set_attr "type" "jsr")
10023 (set_attr "z196prop" "z196_cracked")])
10025 (define_insn "*basr_r"
10026 [(set (match_operand 0 "" "")
10027 (call (mem:QI (match_operand 1 "address_operand" "ZR"))
10028 (match_operand 2 "const_int_operand" "n")))
10029 (clobber (match_operand 3 "register_operand" "=r"))]
10030 "!TARGET_INDIRECT_BRANCH_NOBP_CALL
10031 && !SIBLING_CALL_P (insn)
10032 && GET_MODE (operands[3]) == Pmode"
10034 if (get_attr_op_type (insn) == OP_TYPE_RR)
10035 return "basr\t%3,%1";
10037 return "bas\t%3,%a1";
10039 [(set (attr "op_type")
10040 (if_then_else (match_operand 1 "register_operand" "")
10041 (const_string "RR") (const_string "RX")))
10042 (set (attr "mnemonic")
10043 (if_then_else (match_operand 1 "register_operand" "")
10044 (const_string "basr") (const_string "bas")))
10045 (set_attr "type" "jsr")
10046 (set_attr "atype" "agen")
10047 (set_attr "z196prop" "z196_cracked")])
10049 (define_insn "*basr_r_via_thunk_z10"
10050 [(set (match_operand 0 "" "")
10051 (call (mem:QI (match_operand 1 "register_operand" "a"))
10052 (match_operand 2 "const_int_operand" "n")))
10053 (clobber (match_operand 3 "register_operand" "=&r"))]
10054 "TARGET_INDIRECT_BRANCH_NOBP_CALL
10056 && !SIBLING_CALL_P (insn)
10057 && GET_MODE (operands[3]) == Pmode"
10059 s390_indirect_branch_via_thunk (REGNO (operands[1]),
10060 REGNO (operands[3]),
10062 s390_indirect_branch_type_call);
10065 [(set_attr "op_type" "RIL")
10066 (set_attr "mnemonic" "brasl")
10067 (set_attr "type" "jsr")
10068 (set_attr "atype" "agen")
10069 (set_attr "z196prop" "z196_cracked")])
10071 (define_insn "*basr_r_via_thunk"
10072 [(set (match_operand 0 "" "")
10073 (call (mem:QI (match_operand 1 "register_operand" "a"))
10074 (match_operand 2 "const_int_operand" "n")))
10075 (clobber (match_operand 3 "register_operand" "=&r"))
10076 (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))]
10077 "TARGET_INDIRECT_BRANCH_NOBP_CALL
10079 && !SIBLING_CALL_P (insn)
10080 && GET_MODE (operands[3]) == Pmode"
10082 s390_indirect_branch_via_thunk (REGNO (operands[1]),
10083 REGNO (operands[3]),
10085 s390_indirect_branch_type_call);
10088 [(set_attr "op_type" "RIL")
10089 (set_attr "mnemonic" "brasl")
10090 (set_attr "type" "jsr")
10091 (set_attr "atype" "agen")
10092 (set_attr "z196prop" "z196_cracked")])
10095 ;;- Thread-local storage support.
10098 (define_expand "get_thread_pointer<mode>"
10099 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
10103 (define_expand "set_thread_pointer<mode>"
10104 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
10105 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
10109 (define_insn "*set_tp"
10110 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
10113 [(set_attr "type" "none")
10114 (set_attr "length" "0")])
10116 (define_insn "*tls_load_64"
10117 [(set (match_operand:DI 0 "register_operand" "=d")
10118 (unspec:DI [(match_operand:DI 1 "memory_operand" "T")
10119 (match_operand:DI 2 "" "")]
10123 [(set_attr "op_type" "RXE")
10124 (set_attr "z10prop" "z10_fwd_A3")])
10126 (define_insn "*tls_load_31"
10127 [(set (match_operand:SI 0 "register_operand" "=d,d")
10128 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
10129 (match_operand:SI 2 "" "")]
10135 [(set_attr "op_type" "RX,RXY")
10136 (set_attr "type" "load")
10137 (set_attr "cpu_facility" "*,longdisp")
10138 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
10140 (define_insn "*bras_tls"
10141 [(set (match_operand 0 "" "")
10142 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
10143 (match_operand 2 "const_int_operand" "n")))
10144 (clobber (match_operand 3 "register_operand" "=r"))
10145 (use (match_operand 4 "" ""))]
10146 "!SIBLING_CALL_P (insn)
10147 && TARGET_SMALL_EXEC
10148 && GET_MODE (operands[3]) == Pmode"
10150 [(set_attr "op_type" "RI")
10151 (set_attr "type" "jsr")
10152 (set_attr "z196prop" "z196_cracked")])
10154 (define_insn "*brasl_tls"
10155 [(set (match_operand 0 "" "")
10156 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
10157 (match_operand 2 "const_int_operand" "n")))
10158 (clobber (match_operand 3 "register_operand" "=r"))
10159 (use (match_operand 4 "" ""))]
10160 "!SIBLING_CALL_P (insn)
10162 && GET_MODE (operands[3]) == Pmode"
10164 [(set_attr "op_type" "RIL")
10165 (set_attr "type" "jsr")
10166 (set_attr "z196prop" "z196_cracked")])
10168 (define_insn "*basr_tls"
10169 [(set (match_operand 0 "" "")
10170 (call (mem:QI (match_operand 1 "address_operand" "ZR"))
10171 (match_operand 2 "const_int_operand" "n")))
10172 (clobber (match_operand 3 "register_operand" "=r"))
10173 (use (match_operand 4 "" ""))]
10174 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
10176 if (get_attr_op_type (insn) == OP_TYPE_RR)
10177 return "basr\t%3,%1%J4";
10179 return "bas\t%3,%a1%J4";
10181 [(set (attr "op_type")
10182 (if_then_else (match_operand 1 "register_operand" "")
10183 (const_string "RR") (const_string "RX")))
10184 (set_attr "type" "jsr")
10185 (set_attr "atype" "agen")
10186 (set_attr "z196prop" "z196_cracked")])
10189 ;;- Atomic operations
10193 ; memory barrier patterns.
10196 (define_expand "mem_thread_fence"
10197 [(match_operand:SI 0 "const_int_operand")] ;; model
10200 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
10201 enough not to require barriers of any kind. */
10202 if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0]))))
10204 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
10205 MEM_VOLATILE_P (mem) = 1;
10206 emit_insn (gen_mem_thread_fence_1 (mem));
10211 ; Although bcr is superscalar on Z10, this variant will never
10212 ; become part of an execution group.
10213 ; With z196 we can make use of the fast-BCR-serialization facility.
10214 ; This allows for a slightly faster sync which is sufficient for our
10216 (define_insn "mem_thread_fence_1"
10217 [(set (match_operand:BLK 0 "" "")
10218 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
10222 return "bcr\t14,0";
10224 return "bcr\t15,0";
10226 [(set_attr "op_type" "RR")
10227 (set_attr "mnemonic" "bcr_flush")
10228 (set_attr "z196prop" "z196_alone")])
10231 ; atomic load/store operations
10234 ; Atomic loads need not examine the memory model at all.
10235 (define_expand "atomic_load<mode>"
10236 [(match_operand:DINT 0 "register_operand") ;; output
10237 (match_operand:DINT 1 "memory_operand") ;; memory
10238 (match_operand:SI 2 "const_int_operand")] ;; model
10241 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
10244 if (<MODE>mode == TImode)
10245 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
10246 else if (<MODE>mode == DImode && !TARGET_ZARCH)
10247 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
10249 emit_move_insn (operands[0], operands[1]);
10253 ; Different from movdi_31 in that we want no splitters.
10254 (define_insn "atomic_loaddi_1"
10255 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
10256 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
10264 [(set_attr "op_type" "RS,RSY,RS,RSY")
10265 (set_attr "cpu_facility" "*,longdisp,*,longdisp")
10266 (set_attr "type" "lm,lm,floaddf,floaddf")])
10268 (define_insn "atomic_loadti_1"
10269 [(set (match_operand:TI 0 "register_operand" "=r")
10270 (unspec:TI [(match_operand:TI 1 "memory_operand" "T")]
10274 [(set_attr "op_type" "RXY")
10275 (set_attr "type" "other")])
10277 ; Atomic stores must(?) enforce sequential consistency.
10278 (define_expand "atomic_store<mode>"
10279 [(match_operand:DINT 0 "memory_operand") ;; memory
10280 (match_operand:DINT 1 "register_operand") ;; input
10281 (match_operand:SI 2 "const_int_operand")] ;; model
10284 enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
10286 if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0])))
10289 if (<MODE>mode == TImode)
10290 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
10291 else if (<MODE>mode == DImode && !TARGET_ZARCH)
10292 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
10294 emit_move_insn (operands[0], operands[1]);
10295 if (is_mm_seq_cst (model))
10296 emit_insn (gen_mem_thread_fence (operands[2]));
10300 ; Different from movdi_31 in that we want no splitters.
10301 (define_insn "atomic_storedi_1"
10302 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
10303 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
10311 [(set_attr "op_type" "RS,RSY,RS,RSY")
10312 (set_attr "cpu_facility" "*,longdisp,*,longdisp")
10313 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
10315 (define_insn "atomic_storeti_1"
10316 [(set (match_operand:TI 0 "memory_operand" "=T")
10317 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
10321 [(set_attr "op_type" "RXY")
10322 (set_attr "type" "other")])
10325 ; compare and swap patterns.
10328 (define_expand "atomic_compare_and_swap<mode>"
10329 [(match_operand:SI 0 "register_operand") ;; bool success output
10330 (match_operand:DINT 1 "nonimmediate_operand");; oldval output
10331 (match_operand:DINT 2 "s_operand") ;; memory
10332 (match_operand:DINT 3 "general_operand") ;; expected intput
10333 (match_operand:DINT 4 "general_operand") ;; newval intput
10334 (match_operand:SI 5 "const_int_operand") ;; is_weak
10335 (match_operand:SI 6 "const_int_operand") ;; success model
10336 (match_operand:SI 7 "const_int_operand")] ;; failure model
10339 if (GET_MODE_BITSIZE (<MODE>mode) >= 16
10340 && GET_MODE_BITSIZE (<MODE>mode) > MEM_ALIGN (operands[2]))
10343 s390_expand_cs (<MODE>mode, operands[0], operands[1], operands[2],
10344 operands[3], operands[4], INTVAL (operands[5]));
10347 (define_expand "atomic_compare_and_swap<mode>_internal"
10349 [(set (match_operand:DGPR 0 "register_operand")
10350 (match_operand:DGPR 1 "s_operand"))
10352 (unspec_volatile:DGPR
10354 (match_operand:DGPR 2 "register_operand")
10355 (match_operand:DGPR 3 "register_operand")]
10357 (set (match_operand 4 "cc_reg_operand")
10359 "GET_MODE (operands[4]) == CCZmode
10360 || GET_MODE (operands[4]) == CCZ1mode"
10363 = gen_rtx_COMPARE (GET_MODE (operands[4]), operands[1], operands[2]);
10367 (define_insn "*atomic_compare_and_swap<mode>_1"
10368 [(set (match_operand:TDI 0 "register_operand" "=r")
10369 (match_operand:TDI 1 "nonsym_memory_operand" "+S"))
10371 (unspec_volatile:TDI
10373 (match_operand:TDI 2 "register_operand" "0")
10374 (match_operand:TDI 3 "register_operand" "r")]
10376 (set (reg CC_REGNUM)
10377 (compare (match_dup 1) (match_dup 2)))]
10379 && s390_match_ccmode (insn, CCZ1mode)"
10380 "c<td>sg\t%0,%3,%S1"
10381 [(set_attr "op_type" "RSY")
10382 (set_attr "type" "sem")])
10385 (define_insn "*atomic_compare_and_swapdi_2"
10386 [(set (match_operand:DI 0 "register_operand" "=r,r")
10387 (match_operand:DI 1 "nonsym_memory_operand" "+Q,S"))
10389 (unspec_volatile:DI
10391 (match_operand:DI 2 "register_operand" "0,0")
10392 (match_operand:DI 3 "register_operand" "r,r")]
10394 (set (reg CC_REGNUM)
10395 (compare (match_dup 1) (match_dup 2)))]
10397 && s390_match_ccmode (insn, CCZ1mode)"
10401 [(set_attr "op_type" "RS,RSY")
10402 (set_attr "cpu_facility" "*,longdisp")
10403 (set_attr "type" "sem")])
10406 (define_insn "*atomic_compare_and_swapsi_3"
10407 [(set (match_operand:SI 0 "register_operand" "=r,r")
10408 (match_operand:SI 1 "nonsym_memory_operand" "+Q,S"))
10410 (unspec_volatile:SI
10412 (match_operand:SI 2 "register_operand" "0,0")
10413 (match_operand:SI 3 "register_operand" "r,r")]
10415 (set (reg CC_REGNUM)
10416 (compare (match_dup 1) (match_dup 2)))]
10417 "s390_match_ccmode (insn, CCZ1mode)"
10421 [(set_attr "op_type" "RS,RSY")
10422 (set_attr "cpu_facility" "*,longdisp")
10423 (set_attr "type" "sem")])
10426 ; Other atomic instruction patterns.
10429 ; z196 load and add, xor, or and and instructions
10431 (define_expand "atomic_fetch_<atomic><mode>"
10432 [(match_operand:GPR 0 "register_operand") ;; val out
10434 (match_operand:GPR 1 "memory_operand") ;; memory
10435 (match_operand:GPR 2 "register_operand")) ;; val in
10436 (match_operand:SI 3 "const_int_operand")] ;; model
10439 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
10442 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
10443 (operands[0], operands[1], operands[2]));
10447 ; lan, lang, lao, laog, lax, laxg, laa, laag
10448 (define_insn "atomic_fetch_<atomic><mode>_iaf"
10449 [(set (match_operand:GPR 0 "register_operand" "=d")
10450 (match_operand:GPR 1 "memory_operand" "+S"))
10452 (unspec_volatile:GPR
10453 [(ATOMIC_Z196:GPR (match_dup 1)
10454 (match_operand:GPR 2 "general_operand" "d"))]
10455 UNSPECV_ATOMIC_OP))
10456 (clobber (reg:CC CC_REGNUM))]
10458 "la<noxa><g>\t%0,%2,%1"
10459 [(set_attr "op_type" "RSY")
10460 (set_attr "type" "sem")])
10462 ;; For SImode and larger, the optabs.c code will do just fine in
10463 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
10464 ;; better by expanding our own loop.
10466 (define_expand "atomic_<atomic><mode>"
10468 (match_operand:HQI 0 "memory_operand") ;; memory
10469 (match_operand:HQI 1 "general_operand")) ;; val in
10470 (match_operand:SI 2 "const_int_operand")] ;; model
10473 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
10474 operands[1], false);
10478 (define_expand "atomic_fetch_<atomic><mode>"
10479 [(match_operand:HQI 0 "register_operand") ;; val out
10481 (match_operand:HQI 1 "memory_operand") ;; memory
10482 (match_operand:HQI 2 "general_operand")) ;; val in
10483 (match_operand:SI 3 "const_int_operand")] ;; model
10486 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
10487 operands[2], false);
10491 (define_expand "atomic_<atomic>_fetch<mode>"
10492 [(match_operand:HQI 0 "register_operand") ;; val out
10494 (match_operand:HQI 1 "memory_operand") ;; memory
10495 (match_operand:HQI 2 "general_operand")) ;; val in
10496 (match_operand:SI 3 "const_int_operand")] ;; model
10499 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
10500 operands[2], true);
10504 ;; Pattern to implement atomic_exchange with a compare-and-swap loop. The code
10505 ;; generated by the middleend is not good.
10506 (define_expand "atomic_exchange<mode>"
10507 [(match_operand:DINT 0 "register_operand") ;; val out
10508 (match_operand:DINT 1 "s_operand") ;; memory
10509 (match_operand:DINT 2 "general_operand") ;; val in
10510 (match_operand:SI 3 "const_int_operand")] ;; model
10513 if (<MODE>mode != QImode
10514 && MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (<MODE>mode))
10516 if (<MODE>mode == HImode || <MODE>mode == QImode)
10517 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], operands[2],
10519 else if (<MODE>mode == SImode || TARGET_ZARCH)
10520 s390_expand_atomic_exchange_tdsi (operands[0], operands[1], operands[2]);
10527 ;;- Miscellaneous instructions.
10531 ; allocate stack instruction pattern(s).
10534 (define_expand "allocate_stack"
10535 [(match_operand 0 "general_operand" "")
10536 (match_operand 1 "general_operand" "")]
10539 rtx temp = gen_reg_rtx (Pmode);
10541 emit_move_insn (temp, s390_back_chain_rtx ());
10542 anti_adjust_stack (operands[1]);
10543 emit_move_insn (s390_back_chain_rtx (), temp);
10545 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10551 ; setjmp instruction pattern.
10554 (define_expand "builtin_setjmp_receiver"
10555 [(match_operand 0 "" "")]
10558 emit_insn (s390_load_got ());
10559 emit_use (pic_offset_table_rtx);
10563 ;; These patterns say how to save and restore the stack pointer. We need not
10564 ;; save the stack pointer at function level since we are careful to
10565 ;; preserve the backchain. At block level, we have to restore the backchain
10566 ;; when we restore the stack pointer.
10568 ;; For nonlocal gotos, we must save both the stack pointer and its
10569 ;; backchain and restore both. Note that in the nonlocal case, the
10570 ;; save area is a memory location.
10572 (define_expand "save_stack_function"
10573 [(match_operand 0 "general_operand" "")
10574 (match_operand 1 "general_operand" "")]
10578 (define_expand "restore_stack_function"
10579 [(match_operand 0 "general_operand" "")
10580 (match_operand 1 "general_operand" "")]
10584 (define_expand "restore_stack_block"
10585 [(match_operand 0 "register_operand" "")
10586 (match_operand 1 "register_operand" "")]
10589 rtx temp = gen_reg_rtx (Pmode);
10591 emit_move_insn (temp, s390_back_chain_rtx ());
10592 emit_move_insn (operands[0], operands[1]);
10593 emit_move_insn (s390_back_chain_rtx (), temp);
10598 (define_expand "save_stack_nonlocal"
10599 [(match_operand 0 "memory_operand" "")
10600 (match_operand 1 "register_operand" "")]
10603 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10605 /* Copy the backchain to the first word, sp to the second and the
10606 literal pool base to the third. */
10608 rtx save_bc = adjust_address (operands[0], Pmode, 0);
10609 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
10610 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
10612 if (TARGET_BACKCHAIN)
10613 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
10615 emit_move_insn (save_sp, operands[1]);
10616 emit_move_insn (save_bp, base);
10621 (define_expand "restore_stack_nonlocal"
10622 [(match_operand 0 "register_operand" "")
10623 (match_operand 1 "memory_operand" "")]
10626 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10627 rtx temp = NULL_RTX;
10629 /* Restore the backchain from the first word, sp from the second and the
10630 literal pool base from the third. */
10632 rtx save_bc = adjust_address (operands[1], Pmode, 0);
10633 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
10634 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
10636 if (TARGET_BACKCHAIN)
10637 temp = force_reg (Pmode, save_bc);
10639 emit_move_insn (base, save_bp);
10640 emit_move_insn (operands[0], save_sp);
10643 emit_move_insn (s390_back_chain_rtx (), temp);
10649 (define_expand "exception_receiver"
10653 s390_set_has_landing_pad_p (true);
10658 ; nop instruction pattern(s).
10665 [(set_attr "op_type" "RR")])
10667 ; non-branch NOPs required for optimizing compare-and-branch patterns
10670 (define_insn "nop_lr0"
10671 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_0)]
10674 [(set_attr "op_type" "RR")
10675 (set_attr "z10prop" "z10_fr_E1")])
10677 (define_insn "nop_lr1"
10678 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_1)]
10681 [(set_attr "op_type" "RR")])
10683 ;;- Undeletable nops (used for hotpatching)
10685 (define_insn "nop_2_byte"
10686 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)]
10689 [(set_attr "op_type" "RR")])
10691 (define_insn "nop_4_byte"
10692 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)]
10695 [(set_attr "op_type" "RX")])
10697 (define_insn "nop_6_byte"
10698 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)]
10701 [(set_attr "op_type" "RIL")])
10705 ; Special literal pool access instruction pattern(s).
10708 (define_insn "*pool_entry"
10709 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
10710 UNSPECV_POOL_ENTRY)]
10713 machine_mode mode = GET_MODE (PATTERN (insn));
10714 unsigned int align = GET_MODE_BITSIZE (mode);
10715 s390_output_pool_entry (operands[0], mode, align);
10718 [(set (attr "length")
10719 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
10721 (define_insn "pool_align"
10722 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
10723 UNSPECV_POOL_ALIGN)]
10726 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10728 (define_insn "pool_section_start"
10729 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
10732 switch_to_section (targetm.asm_out.function_rodata_section
10733 (current_function_decl));
10736 [(set_attr "length" "0")])
10738 (define_insn "pool_section_end"
10739 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
10742 switch_to_section (current_function_section ());
10745 [(set_attr "length" "0")])
10747 (define_insn "main_base_64"
10748 [(set (match_operand 0 "register_operand" "=a")
10749 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10750 "GET_MODE (operands[0]) == Pmode"
10752 [(set_attr "op_type" "RIL")
10753 (set_attr "type" "larl")
10754 (set_attr "z10prop" "z10_fwd_A1")])
10756 (define_insn "main_pool"
10757 [(set (match_operand 0 "register_operand" "=a")
10758 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
10759 "GET_MODE (operands[0]) == Pmode"
10761 gcc_unreachable ();
10763 [(set (attr "type")
10764 (const_string "larl"))])
10766 (define_insn "reload_base_64"
10767 [(set (match_operand 0 "register_operand" "=a")
10768 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10769 "GET_MODE (operands[0]) == Pmode"
10771 [(set_attr "op_type" "RIL")
10772 (set_attr "type" "larl")
10773 (set_attr "z10prop" "z10_fwd_A1")])
10775 (define_insn "pool"
10776 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
10779 gcc_unreachable ();
10781 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10784 ;; Insns related to generating the function prologue and epilogue.
10788 (define_expand "prologue"
10789 [(use (const_int 0))]
10791 "s390_emit_prologue (); DONE;")
10793 (define_expand "epilogue"
10794 [(use (const_int 1))]
10796 "s390_emit_epilogue (false); DONE;")
10798 (define_expand "sibcall_epilogue"
10799 [(use (const_int 0))]
10801 "s390_emit_epilogue (true); DONE;")
10803 ;; A direct return instruction, without using an epilogue.
10804 (define_insn "<code>"
10806 "s390_can_use_<code>_insn ()"
10808 if (TARGET_INDIRECT_BRANCH_NOBP_RET)
10810 /* The target is always r14 so there is no clobber
10811 of r1 needed for pre z10 targets. */
10812 s390_indirect_branch_via_thunk (RETURN_REGNUM,
10815 s390_indirect_branch_type_return);
10819 return "br\t%%r14";
10821 [(set (attr "op_type")
10822 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
10823 (const_string "RIL")
10824 (const_string "RR")))
10825 (set (attr "mnemonic")
10826 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
10827 (const_string "jg")
10828 (const_string "br")))
10829 (set_attr "type" "jsr")
10830 (set_attr "atype" "agen")])
10833 (define_expand "return_use"
10836 (use (match_operand 0 "register_operand" "a"))])]
10839 if (!TARGET_CPU_Z10
10840 && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION)
10843 emit_jump_insn (gen_returndi_prez10 (operands[0]));
10845 emit_jump_insn (gen_returnsi_prez10 (operands[0]));
10850 (define_insn "*return<mode>"
10852 (use (match_operand:P 0 "register_operand" "a"))]
10853 "TARGET_CPU_Z10 || !TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION"
10855 if (TARGET_INDIRECT_BRANCH_NOBP_RET)
10857 s390_indirect_branch_via_thunk (REGNO (operands[0]),
10860 s390_indirect_branch_type_return);
10866 [(set (attr "op_type")
10867 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
10868 (const_string "RIL")
10869 (const_string "RR")))
10870 (set (attr "mnemonic")
10871 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
10872 (const_string "jg")
10873 (const_string "br")))
10874 (set_attr "type" "jsr")
10875 (set_attr "atype" "agen")])
10877 (define_insn "return<mode>_prez10"
10879 (use (match_operand:P 0 "register_operand" "a"))
10880 (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))]
10881 "!TARGET_CPU_Z10 && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION"
10883 if (TARGET_INDIRECT_BRANCH_NOBP_RET)
10885 s390_indirect_branch_via_thunk (REGNO (operands[0]),
10888 s390_indirect_branch_type_return);
10894 [(set (attr "op_type")
10895 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
10896 (const_string "RIL")
10897 (const_string "RR")))
10898 (set (attr "mnemonic")
10899 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
10900 (const_string "jg")
10901 (const_string "br")))
10902 (set_attr "type" "jsr")
10903 (set_attr "atype" "agen")])
10906 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
10907 ;; pointer. This is used for compatibility.
10909 (define_expand "ptr_extend"
10910 [(set (match_operand:DI 0 "register_operand" "=r")
10911 (match_operand:SI 1 "register_operand" "r"))]
10914 emit_insn (gen_anddi3 (operands[0],
10915 gen_lowpart (DImode, operands[1]),
10916 GEN_INT (0x7fffffff)));
10920 ;; Instruction definition to expand eh_return macro to support
10921 ;; swapping in special linkage return addresses.
10923 (define_expand "eh_return"
10924 [(use (match_operand 0 "register_operand" ""))]
10927 s390_emit_tpf_eh_return (operands[0]);
10932 ; Stack Protector Patterns
10935 (define_expand "stack_protect_set"
10936 [(set (match_operand 0 "memory_operand" "")
10937 (match_operand 1 "memory_operand" ""))]
10940 #ifdef TARGET_THREAD_SSP_OFFSET
10942 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10943 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10946 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10948 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10953 (define_insn "stack_protect_set<mode>"
10954 [(set (match_operand:DSI 0 "memory_operand" "=Q")
10955 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
10957 "mvc\t%O0(%G0,%R0),%S1"
10958 [(set_attr "op_type" "SS")])
10960 (define_expand "stack_protect_test"
10961 [(set (reg:CC CC_REGNUM)
10962 (compare (match_operand 0 "memory_operand" "")
10963 (match_operand 1 "memory_operand" "")))
10964 (match_operand 2 "" "")]
10968 #ifdef TARGET_THREAD_SSP_OFFSET
10970 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10971 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10974 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
10976 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
10978 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
10979 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
10980 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
10984 (define_insn "stack_protect_test<mode>"
10985 [(set (reg:CCZ CC_REGNUM)
10986 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
10987 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
10989 "clc\t%O0(%G0,%R0),%S1"
10990 [(set_attr "op_type" "SS")])
10992 ; This is used in s390_emit_prologue in order to prevent insns
10993 ; adjusting the stack pointer to be moved over insns writing stack
10994 ; slots using a copy of the stack pointer in a different register.
10995 (define_insn "stack_tie"
10996 [(set (match_operand:BLK 0 "memory_operand" "+m")
10997 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
11000 [(set_attr "length" "0")])
11003 (define_insn "stack_restore_from_fpr"
11004 [(set (reg:DI STACK_REGNUM)
11005 (match_operand:DI 0 "register_operand" "f"))
11006 (clobber (mem:BLK (scratch)))]
11009 [(set_attr "op_type" "RRE")])
11012 ; Data prefetch patterns
11015 (define_insn "prefetch"
11016 [(prefetch (match_operand 0 "address_operand" "ZT,X")
11017 (match_operand:SI 1 "const_int_operand" " n,n")
11018 (match_operand:SI 2 "const_int_operand" " n,n"))]
11021 switch (which_alternative)
11024 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
11026 if (larl_operand (operands[0], Pmode))
11027 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
11031 /* This might be reached for symbolic operands with an odd
11032 addend. We simply omit the prefetch for such rare cases. */
11037 [(set_attr "type" "load,larl")
11038 (set_attr "op_type" "RXY,RIL")
11039 (set_attr "z10prop" "z10_super")
11040 (set_attr "z196prop" "z196_alone")])
11044 ; Byte swap instructions
11047 ; FIXME: There is also mvcin but we cannot use it since src and target
11049 ; lrvr, lrv, strv, lrvgr, lrvg, strvg
11050 (define_insn "bswap<mode>2"
11051 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T")
11052 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))]
11058 [(set_attr "type" "*,load,store")
11059 (set_attr "op_type" "RRE,RXY,RXY")
11060 (set_attr "z10prop" "z10_super")])
11062 (define_insn "bswaphi2"
11063 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T")
11064 (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))]
11070 [(set_attr "type" "*,load,store")
11071 (set_attr "op_type" "RRE,RXY,RXY")
11072 (set_attr "z10prop" "z10_super")])
11075 [(set (match_operand:HI 0 "register_operand" "")
11076 (bswap:HI (match_operand:HI 1 "register_operand" "")))]
11078 [(set (match_dup 2) (bswap:SI (match_dup 3)))
11079 (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))]
11081 operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
11082 operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
11087 ; Population count instruction
11090 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
11091 ; portions and stores the result in the corresponding bytes in op0.
11092 (define_insn "*popcount<mode>"
11093 [(set (match_operand:INT 0 "register_operand" "=d")
11094 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
11095 (clobber (reg:CC CC_REGNUM))]
11098 [(set_attr "op_type" "RRE")])
11100 (define_expand "popcountdi2"
11102 (parallel [(set (match_operand:DI 0 "register_operand" "")
11103 (unspec:DI [(match_operand:DI 1 "register_operand")]
11105 (clobber (reg:CC CC_REGNUM))])
11106 ; sllg op2, op0, 32
11107 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
11109 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
11110 (clobber (reg:CC CC_REGNUM))])
11111 ; sllg op2, op0, 16
11113 (ashift:DI (match_dup 0) (const_int 16)))
11115 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
11116 (clobber (reg:CC CC_REGNUM))])
11118 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
11120 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
11121 (clobber (reg:CC CC_REGNUM))])
11122 ; srlg op0, op0, 56
11123 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
11124 "TARGET_Z196 && TARGET_64BIT"
11125 "operands[2] = gen_reg_rtx (DImode);")
11127 (define_expand "popcountsi2"
11129 (parallel [(set (match_operand:SI 0 "register_operand" "")
11130 (unspec:SI [(match_operand:SI 1 "register_operand")]
11132 (clobber (reg:CC CC_REGNUM))])
11133 ; sllk op2, op0, 16
11135 (ashift:SI (match_dup 0) (const_int 16)))
11137 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
11138 (clobber (reg:CC CC_REGNUM))])
11140 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
11142 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
11143 (clobber (reg:CC CC_REGNUM))])
11145 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
11147 "operands[2] = gen_reg_rtx (SImode);")
11149 (define_expand "popcounthi2"
11151 (parallel [(set (match_operand:HI 0 "register_operand" "")
11152 (unspec:HI [(match_operand:HI 1 "register_operand")]
11154 (clobber (reg:CC CC_REGNUM))])
11157 (ashift:SI (match_dup 0) (const_int 8)))
11159 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
11160 (clobber (reg:CC CC_REGNUM))])
11162 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
11164 "operands[2] = gen_reg_rtx (SImode);")
11166 (define_expand "popcountqi2"
11168 (parallel [(set (match_operand:QI 0 "register_operand" "")
11169 (unspec:QI [(match_operand:QI 1 "register_operand")]
11171 (clobber (reg:CC CC_REGNUM))])]
11176 ;;- Copy sign instructions
11179 (define_insn "copysign<mode>3"
11180 [(set (match_operand:FP 0 "register_operand" "=f")
11181 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
11182 (match_operand:FP 2 "register_operand" "f")]
11186 [(set_attr "op_type" "RRF")
11187 (set_attr "type" "fsimp<mode>")])
11191 ;;- Transactional execution instructions
11194 ; This splitter helps combine to make use of CC directly when
11195 ; comparing the integer result of a tbegin builtin with a constant.
11196 ; The unspec is already removed by canonicalize_comparison. So this
11197 ; splitters only job is to turn the PARALLEL into separate insns
11198 ; again. Unfortunately this only works with the very first cc/int
11199 ; compare since combine is not able to deal with data flow across
11200 ; basic block boundaries.
11202 ; It needs to be an insn pattern as well since combine does not apply
11203 ; the splitter directly. Combine would only use it if it actually
11204 ; would reduce the number of instructions.
11205 (define_insn_and_split "*ccraw_to_int"
11208 (match_operator 0 "s390_eqne_operator"
11209 [(reg:CCRAW CC_REGNUM)
11210 (match_operand 1 "const_int_operand" "")])
11211 (label_ref (match_operand 2 "" ""))
11213 (set (match_operand:SI 3 "register_operand" "=d")
11214 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
11218 [(set (match_dup 3)
11219 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
11221 (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
11222 (label_ref (match_dup 2))
11226 ; Non-constrained transaction begin
11228 (define_expand "tbegin"
11229 [(match_operand:SI 0 "register_operand" "")
11230 (match_operand:BLK 1 "memory_operand" "")]
11233 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
11237 (define_expand "tbegin_nofloat"
11238 [(match_operand:SI 0 "register_operand" "")
11239 (match_operand:BLK 1 "memory_operand" "")]
11242 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
11246 (define_expand "tbegin_retry"
11247 [(match_operand:SI 0 "register_operand" "")
11248 (match_operand:BLK 1 "memory_operand" "")
11249 (match_operand:SI 2 "general_operand" "")]
11252 s390_expand_tbegin (operands[0], operands[1], operands[2], true);
11256 (define_expand "tbegin_retry_nofloat"
11257 [(match_operand:SI 0 "register_operand" "")
11258 (match_operand:BLK 1 "memory_operand" "")
11259 (match_operand:SI 2 "general_operand" "")]
11262 s390_expand_tbegin (operands[0], operands[1], operands[2], false);
11266 ; Clobber VRs since they don't get restored
11267 (define_insn "tbegin_1_z13"
11268 [(set (reg:CCRAW CC_REGNUM)
11269 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
11271 (set (match_operand:BLK 1 "memory_operand" "=Q")
11272 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
11273 (clobber (reg:TI 16)) (clobber (reg:TI 38))
11274 (clobber (reg:TI 17)) (clobber (reg:TI 39))
11275 (clobber (reg:TI 18)) (clobber (reg:TI 40))
11276 (clobber (reg:TI 19)) (clobber (reg:TI 41))
11277 (clobber (reg:TI 20)) (clobber (reg:TI 42))
11278 (clobber (reg:TI 21)) (clobber (reg:TI 43))
11279 (clobber (reg:TI 22)) (clobber (reg:TI 44))
11280 (clobber (reg:TI 23)) (clobber (reg:TI 45))
11281 (clobber (reg:TI 24)) (clobber (reg:TI 46))
11282 (clobber (reg:TI 25)) (clobber (reg:TI 47))
11283 (clobber (reg:TI 26)) (clobber (reg:TI 48))
11284 (clobber (reg:TI 27)) (clobber (reg:TI 49))
11285 (clobber (reg:TI 28)) (clobber (reg:TI 50))
11286 (clobber (reg:TI 29)) (clobber (reg:TI 51))
11287 (clobber (reg:TI 30)) (clobber (reg:TI 52))
11288 (clobber (reg:TI 31)) (clobber (reg:TI 53))]
11289 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
11290 ; not supposed to be used for immediates (see genpreds.c).
11291 "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
11293 [(set_attr "op_type" "SIL")])
11295 (define_insn "tbegin_1"
11296 [(set (reg:CCRAW CC_REGNUM)
11297 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
11299 (set (match_operand:BLK 1 "memory_operand" "=Q")
11300 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
11301 (clobber (reg:DF 16))
11302 (clobber (reg:DF 17))
11303 (clobber (reg:DF 18))
11304 (clobber (reg:DF 19))
11305 (clobber (reg:DF 20))
11306 (clobber (reg:DF 21))
11307 (clobber (reg:DF 22))
11308 (clobber (reg:DF 23))
11309 (clobber (reg:DF 24))
11310 (clobber (reg:DF 25))
11311 (clobber (reg:DF 26))
11312 (clobber (reg:DF 27))
11313 (clobber (reg:DF 28))
11314 (clobber (reg:DF 29))
11315 (clobber (reg:DF 30))
11316 (clobber (reg:DF 31))]
11317 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
11318 ; not supposed to be used for immediates (see genpreds.c).
11319 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
11321 [(set_attr "op_type" "SIL")])
11323 ; Same as above but without the FPR clobbers
11324 (define_insn "tbegin_nofloat_1"
11325 [(set (reg:CCRAW CC_REGNUM)
11326 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
11328 (set (match_operand:BLK 1 "memory_operand" "=Q")
11329 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
11330 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
11332 [(set_attr "op_type" "SIL")])
11335 ; Constrained transaction begin
11337 (define_expand "tbeginc"
11338 [(set (reg:CCRAW CC_REGNUM)
11339 (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
11344 (define_insn "*tbeginc_1"
11345 [(set (reg:CCRAW CC_REGNUM)
11346 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
11348 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
11350 [(set_attr "op_type" "SIL")])
11354 (define_expand "tend"
11355 [(set (reg:CCRAW CC_REGNUM)
11356 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
11357 (set (match_operand:SI 0 "register_operand" "")
11358 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
11362 (define_insn "*tend_1"
11363 [(set (reg:CCRAW CC_REGNUM)
11364 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
11367 [(set_attr "op_type" "S")])
11369 ; Transaction abort
11371 (define_expand "tabort"
11372 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")]
11374 "TARGET_HTM && operands != NULL"
11376 if (CONST_INT_P (operands[0])
11377 && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
11379 error ("invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
11380 ". Values in range 0 through 255 are reserved.",
11381 INTVAL (operands[0]));
11386 (define_insn "*tabort_1"
11387 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")]
11389 "TARGET_HTM && operands != NULL"
11391 [(set_attr "op_type" "S")])
11393 (define_insn "*tabort_1_plus"
11394 [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand" "a")
11395 (match_operand:SI 1 "const_int_operand" "J"))]
11397 "TARGET_HTM && operands != NULL
11398 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")"
11400 [(set_attr "op_type" "S")])
11402 ; Transaction extract nesting depth
11404 (define_insn "etnd"
11405 [(set (match_operand:SI 0 "register_operand" "=d")
11406 (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
11409 [(set_attr "op_type" "RRE")])
11411 ; Non-transactional store
11413 (define_insn "ntstg"
11414 [(set (match_operand:DI 0 "memory_operand" "=T")
11415 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
11419 [(set_attr "op_type" "RXY")])
11421 ; Transaction perform processor assist
11423 (define_expand "tx_assist"
11424 [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
11425 (reg:SI GPR0_REGNUM)
11426 (const_int PPA_TX_ABORT)]
11431 (define_insn "*ppa"
11432 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
11433 (match_operand:SI 1 "register_operand" "d")
11434 (match_operand 2 "const_int_operand" "I")]
11436 "(TARGET_ZEC12 || TARGET_HTM) && INTVAL (operands[2]) < 16"
11438 [(set_attr "op_type" "RRF")])
11441 ; Set and get floating point control register
11443 (define_insn "sfpc"
11444 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
11446 "TARGET_HARD_FLOAT"
11449 (define_insn "efpc"
11450 [(set (match_operand:SI 0 "register_operand" "=d")
11451 (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))]
11452 "TARGET_HARD_FLOAT"
11456 ; Load count to block boundary
11458 (define_insn "lcbb"
11459 [(set (match_operand:SI 0 "register_operand" "=d")
11460 (unspec:SI [(match_operand 1 "address_operand" "ZR")
11461 (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB))
11462 (clobber (reg:CC CC_REGNUM))]
11465 [(set_attr "op_type" "VRX")])
11467 ; Handle -fsplit-stack.
11469 (define_expand "split_stack_prologue"
11473 s390_expand_split_stack_prologue ();
11477 ;; If there are operand 0 bytes available on the stack, jump to
11480 (define_expand "split_stack_space_check"
11481 [(set (pc) (if_then_else
11482 (ltu (minus (reg 15)
11483 (match_operand 0 "register_operand"))
11484 (unspec [(const_int 0)] UNSPEC_STACK_CHECK))
11485 (label_ref (match_operand 1))
11489 /* Offset from thread pointer to __private_ss. */
11490 int psso = TARGET_64BIT ? 0x38 : 0x20;
11491 rtx tp = s390_get_thread_pointer ();
11492 rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso));
11493 rtx reg = gen_reg_rtx (Pmode);
11496 emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0]));
11498 emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0]));
11499 cc = s390_emit_compare (GT, reg, guard);
11500 s390_emit_jump (operands[1], cc);
11505 ;; __morestack parameter block for split stack prologue. Parameters are:
11506 ;; parameter block label, label to be called by __morestack, frame size,
11507 ;; stack parameter size.
11509 (define_insn "split_stack_data"
11510 [(unspec_volatile [(match_operand 0 "" "X")
11511 (match_operand 1 "" "X")
11512 (match_operand 2 "const_int_operand" "X")
11513 (match_operand 3 "const_int_operand" "X")]
11514 UNSPECV_SPLIT_STACK_DATA)]
11517 switch_to_section (targetm.asm_out.function_rodata_section
11518 (current_function_decl));
11521 output_asm_insn (".align\t8", operands);
11523 output_asm_insn (".align\t4", operands);
11524 (*targetm.asm_out.internal_label) (asm_out_file, "L",
11525 CODE_LABEL_NUMBER (operands[0]));
11528 output_asm_insn (".quad\t%2", operands);
11529 output_asm_insn (".quad\t%3", operands);
11530 output_asm_insn (".quad\t%1-%0", operands);
11534 output_asm_insn (".long\t%2", operands);
11535 output_asm_insn (".long\t%3", operands);
11536 output_asm_insn (".long\t%1-%0", operands);
11539 switch_to_section (current_function_section ());
11542 [(set_attr "length" "0")])
11545 ;; A jg with minimal fuss for use in split stack prologue.
11547 (define_expand "split_stack_call"
11548 [(match_operand 0 "bras_sym_operand" "X")
11549 (match_operand 1 "" "")]
11553 emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1]));
11555 emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1]));
11559 (define_insn "split_stack_call_<mode>"
11560 [(set (pc) (label_ref (match_operand 1 "" "")))
11561 (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
11563 UNSPECV_SPLIT_STACK_CALL))]
11566 [(set_attr "op_type" "RIL")
11567 (set_attr "type" "branch")])
11569 ;; Also a conditional one.
11571 (define_expand "split_stack_cond_call"
11572 [(match_operand 0 "bras_sym_operand" "X")
11573 (match_operand 1 "" "")
11574 (match_operand 2 "" "")]
11578 emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2]));
11580 emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2]));
11584 (define_insn "split_stack_cond_call_<mode>"
11587 (match_operand 1 "" "")
11588 (label_ref (match_operand 2 "" ""))
11590 (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
11592 UNSPECV_SPLIT_STACK_CALL))]
11595 [(set_attr "op_type" "RIL")
11596 (set_attr "type" "branch")])
11598 (define_insn "osc_break"
11599 [(unspec_volatile [(const_int 0)] UNSPECV_OSC_BREAK)]
11602 [(set_attr "op_type" "RR")])
11604 (define_expand "speculation_barrier"
11605 [(unspec_volatile [(reg:SI GPR0_REGNUM)
11606 (reg:SI GPR0_REGNUM)
11607 (const_int PPA_OOO_BARRIER)]