| blob | 49f86c2887a7269b205bc9bf789a0bca0a201563 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables.
27 Basic induction variables (BIVs) are a pseudo registers which are set within
28 a loop only by incrementing or decrementing its value. General induction
29 variables (GIVs) are pseudo registers with a value which is a linear function
30 of a basic induction variable. BIVs are recognized by `basic_induction_var';
31 GIVs by `general_induction_var'.
33 Once induction variables are identified, strength reduction is applied to the
34 general induction variables, and induction variable elimination is applied to
35 the basic induction variables.
37 It also finds cases where
38 a register is set within the loop by zero-extending a narrower value
39 and changes these to zero the entire register once before the loop
40 and merely copy the low part within the loop.
42 Most of the complexity is in heuristics to decide when it is worth
43 while to do these things. */
70 /* Not really meaningful values, but at least something. */
71 #ifndef SIMULTANEOUS_PREFETCHES
72 #define SIMULTANEOUS_PREFETCHES 3
73 #endif
74 #ifndef PREFETCH_BLOCK
75 #define PREFETCH_BLOCK 32
76 #endif
77 #ifndef HAVE_prefetch
78 #define HAVE_prefetch 0
79 #define CODE_FOR_prefetch 0
80 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
81 #endif
83 /* Give up the prefetch optimizations once we exceed a given threshold.
84 It is unlikely that we would be able to optimize something in a loop
85 with so many detected prefetches. */
86 #define MAX_PREFETCHES 100
87 /* The number of prefetch blocks that are beneficial to fetch at once before
88 a loop with a known (and low) iteration count. */
89 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
90 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
91 since it is likely that the data are already in the cache. */
92 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
94 /* Parameterize some prefetch heuristics so they can be turned on and off
95 easily for performance testing on new architectures. These can be
96 defined in target-dependent files. */
98 /* Prefetch is worthwhile only when loads/stores are dense. */
99 #ifndef PREFETCH_ONLY_DENSE_MEM
100 #define PREFETCH_ONLY_DENSE_MEM 1
101 #endif
103 /* Define what we mean by "dense" loads and stores; This value divided by 256
104 is the minimum percentage of memory references that worth prefetching. */
105 #ifndef PREFETCH_DENSE_MEM
106 #define PREFETCH_DENSE_MEM 220
107 #endif
109 /* Do not prefetch for a loop whose iteration count is known to be low. */
110 #ifndef PREFETCH_NO_LOW_LOOPCNT
111 #define PREFETCH_NO_LOW_LOOPCNT 1
112 #endif
114 /* Define what we mean by a "low" iteration count. */
115 #ifndef PREFETCH_LOW_LOOPCNT
116 #define PREFETCH_LOW_LOOPCNT 32
117 #endif
119 /* Do not prefetch for a loop that contains a function call; such a loop is
120 probably not an internal loop. */
121 #ifndef PREFETCH_NO_CALL
122 #define PREFETCH_NO_CALL 1
123 #endif
125 /* Do not prefetch accesses with an extreme stride. */
126 #ifndef PREFETCH_NO_EXTREME_STRIDE
127 #define PREFETCH_NO_EXTREME_STRIDE 1
128 #endif
130 /* Define what we mean by an "extreme" stride. */
131 #ifndef PREFETCH_EXTREME_STRIDE
132 #define PREFETCH_EXTREME_STRIDE 4096
133 #endif
135 /* Define a limit to how far apart indices can be and still be merged
136 into a single prefetch. */
137 #ifndef PREFETCH_EXTREME_DIFFERENCE
138 #define PREFETCH_EXTREME_DIFFERENCE 4096
139 #endif
141 /* Issue prefetch instructions before the loop to fetch data to be used
142 in the first few loop iterations. */
143 #ifndef PREFETCH_BEFORE_LOOP
144 #define PREFETCH_BEFORE_LOOP 1
145 #endif
147 /* Do not handle reversed order prefetches (negative stride). */
148 #ifndef PREFETCH_NO_REVERSE_ORDER
149 #define PREFETCH_NO_REVERSE_ORDER 1
150 #endif
152 /* Prefetch even if the GIV is in conditional code. */
153 #ifndef PREFETCH_CONDITIONAL
154 #define PREFETCH_CONDITIONAL 1
155 #endif
157 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
158 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
160 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
161 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
162 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
164 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
165 ((REGNO) < FIRST_PSEUDO_REGISTER \
166 ? (int) hard_regno_nregs[(REGNO)][GET_MODE (SET_DEST)] : 1)
169 /* Vector mapping INSN_UIDs to luids.
170 The luids are like uids but increase monotonically always.
171 We use them to see whether a jump comes from outside a given loop. */
175 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
176 number the insn is contained in. */
180 /* 1 + largest uid of any insn. */
184 /* Number of loops detected in current function. Used as index to the
185 next few tables. */
189 /* Bound on pseudo register number before loop optimization.
190 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
193 /* The value to pass to the next call of reg_scan_update. */
195 \f
196 /* During the analysis of a loop, a chain of `struct movable's
197 is made to record all the movable insns found.
198 Then the entire chain can be scanned to decide which to move. */
200 struct movable
201 {
206 of any registers used within the LIBCALL. */
208 that must be moved with this one. */
211 may be adjusted when matching movables
212 that load the same value are found. */
214 including other movables that force this
215 or match this one. */
217 a low part that we should avoid changing when
218 clearing the rest of the reg. */
222 /* If PARTIAL is 1, GLOBAL means something different:
223 that the reg is live outside the range from where it is set
224 to the following label. */
228 In particular, moving it does not make it
229 invariant. */
231 load SRC, rather than copying INSN. */
233 first insn of a consecutive sets group. */
236 the original insn with a copy from that
237 pseudo, rather than deleting it. */
241 };
246 /* Forward declarations. */
261 #if 0
263 #endif
306 rtx *);
367 {
368 rtx match;
369 rtx replacement;
370 rtx insn;
373 /* Nonzero iff INSN is between START and END, inclusive. */
374 #define INSN_IN_RANGE_P(INSN, START, END) \
375 (INSN_UID (INSN) < max_uid_for_loop \
376 && INSN_LUID (INSN) >= INSN_LUID (START) \
377 && INSN_LUID (INSN) <= INSN_LUID (END))
379 /* Indirect_jump_in_function is computed once per function. */
387 \f
388 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
389 copy the value of the strength reduced giv to its original register. */
392 /* Cost of using a register, to normalize the benefits of a giv. */
395 void
397 {
403 }
404 \f
405 /* Compute the mapping from uids to luids.
406 LUIDs are numbers assigned to insns, like uids,
407 except that luids increase monotonically through the code.
408 Start at insn START and stop just before END. Assign LUIDs
409 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
410 static int
412 {
414 rtx insn;
417 {
420 /* Don't assign luids to line-number NOTEs, so that the distance in
421 luids between two insns is not affected by -g. */
425 else
426 /* Give a line number note the same luid as preceding insn. */
428 }
430 }
431 \f
432 /* Entry point of this file. Perform loop optimization
433 on the current function. F is the first insn of the function
434 and DUMPFILE is a stream for output of a trace of actions taken
435 (or 0 if none should be output). */
437 void
439 {
440 rtx insn;
455 /* Count the number of loops. */
459 {
462 max_loop_num++;
463 }
465 /* Don't waste time if no loops. */
471 /* Get size to use for tables indexed by uids.
472 Leave some space for labels allocated by find_and_verify_loops. */
478 /* Allocate storage for array of loops. */
481 /* Find and process each loop.
482 First, find them, and record them in order of their beginnings. */
485 /* Allocate and initialize auxiliary loop information. */
490 /* Now find all register lifetimes. This must be done after
491 find_and_verify_loops, because it might reorder the insns in the
492 function. */
495 /* This must occur after reg_scan so that registers created by gcse
496 will have entries in the register tables.
498 We could have added a call to reg_scan after gcse_main in toplev.c,
499 but moving this call to init_alias_analysis is more efficient. */
502 /* See if we went too far. Note that get_max_uid already returns
503 one more that the maximum uid of all insn. */
506 /* Now reset it to the actual size we need. See above. */
509 /* find_and_verify_loops has already called compute_luids, but it
510 might have rearranged code afterwards, so we need to recompute
511 the luids now. */
514 /* Don't leave gaps in uid_luid for insns that have been
515 deleted. It is possible that the first or last insn
516 using some register has been deleted by cross-jumping.
517 Make sure that uid_luid for that former insn's uid
518 points to the general area where that insn used to be. */
520 {
524 }
529 /* Determine if the function has indirect jump. On some systems
530 this prevents low overhead loop instructions from being used. */
533 /* Now scan the loops, last ones first, since this means inner ones are done
534 before outer ones. */
536 {
540 {
543 }
544 }
548 /* Clean up. */
556 }
557 \f
558 /* Returns the next insn, in execution order, after INSN. START and
559 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
560 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
561 insn-stream; it is used with loops that are entered near the
562 bottom. */
564 static rtx
566 {
570 {
572 /* Go to the top of the loop, and continue there. */
574 else
575 /* We're done. */
577 }
580 /* We're done. */
584 }
586 /* Find any register references hidden inside X and add them to
587 the dependency list DEPS. This is used to look inside CLOBBER (MEM
588 when checking whether a PARALLEL can be pulled out of a loop. */
590 static rtx
592 {
596 else
597 {
601 {
607 }
608 }
610 }
612 /* Optimize one loop described by LOOP. */
614 /* ??? Could also move memory writes out of loops if the destination address
615 is invariant, the source is invariant, the memory write is not volatile,
616 and if we can prove that no read inside the loop can read this address
617 before the write occurs. If there is a read of this address after the
618 write, then we can also mark the memory read as invariant. */
620 static void
622 {
628 rtx p;
629 /* 1 if we are scanning insns that could be executed zero times. */
631 /* 1 if we are scanning insns that might never be executed
632 due to a subroutine call which might exit before they are reached. */
634 /* Number of insns in the loop. */
638 /* The SET from an insn, if it is the only SET in the insn. */
640 /* Chain describing insns movable in current loop. */
642 /* Ratio of extra register life span we can justify
643 for saving an instruction. More if loop doesn't call subroutines
644 since in that case saving an insn makes more difference
645 and more registers are available. */
647 /* Nonzero if we are scanning instructions in a sub-loop. */
656 /* Determine whether this loop starts with a jump down to a test at
657 the end. This will occur for a small number of loops with a test
658 that is too complex to duplicate in front of the loop.
660 We search for the first insn or label in the loop, skipping NOTEs.
661 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
662 (because we might have a loop executed only once that contains a
663 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
664 (in case we have a degenerate loop).
666 Note that if we mistakenly think that a loop is entered at the top
667 when, in fact, it is entered at the exit test, the only effect will be
668 slightly poorer optimization. Making the opposite error can generate
669 incorrect code. Since very few loops now start with a jump to the
670 exit test, the code here to detect that case is very conservative. */
673 p != loop_end
679 ;
683 /* If loop end is the end of the current function, then emit a
684 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
685 note insn. This is the position we use when sinking insns out of
686 the loop. */
689 else
692 /* Set up variables describing this loop. */
696 /* If loop has a jump before the first label,
697 the true entry is the target of that jump.
698 Start scan from there.
699 But record in LOOP->TOP the place where the end-test jumps
700 back to so we can scan that after the end of the loop. */
702 /* Loop entry must be unconditional jump (and not a RETURN) */
705 /* Check to see whether the jump actually
706 jumps out of the loop (meaning it's no loop).
707 This case can happen for things like
708 do {..} while (0). If this label was generated previously
709 by loop, we can't tell anything about it and have to reject
710 the loop. */
712 {
715 }
717 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
718 as required by loop_reg_used_before_p. So skip such loops. (This
719 test may never be true, but it's best to play it safe.)
721 Also, skip loops where we do not start scanning at a label. This
722 test also rejects loops starting with a JUMP_INSN that failed the
723 test above. */
727 {
732 }
734 /* Allocate extra space for REGs that might be created by load_mems.
735 We allocate a little extra slop as well, in the hopes that we
736 won't have to reallocate the regs array. */
741 {
747 }
749 /* Scan through the loop finding insns that are safe to move.
750 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
751 this reg will be considered invariant for subsequent insns.
752 We consider whether subsequent insns use the reg
753 in deciding whether it is worth actually moving.
755 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
756 and therefore it is possible that the insns we are scanning
757 would never be executed. At such times, we must make sure
758 that it is safe to execute the insn once instead of zero times.
759 When MAYBE_NEVER is 0, all insns will be executed at least once
760 so that is not a problem. */
765 {
767 in_libcall--;
769 {
772 in_libcall++;
776 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
778 #endif
780 {
788 /* Figure out what to use as a source of this insn. If a
789 REG_EQUIV note is given or if a REG_EQUAL note with a
790 constant operand is specified, use it as the source and
791 mark that we should move this insn by calling
792 emit_move_insn rather that duplicating the insn.
794 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL
795 note is present. */
799 else
800 {
805 {
807 /* A libcall block can use regs that don't appear in
808 the equivalent expression. To move the libcall,
809 we must move those regs too. */
811 }
812 }
814 /* For parallels, add any possible uses to the dependencies, as
815 we can't move the insn without resolving them first.
816 MEMs inside CLOBBERs may also reference registers; these
817 count as implicit uses. */
819 {
821 {
824 dependencies
826 dependencies);
831 }
832 }
835 than the one where it is set (meaning that
836 something after this point in the loop might
837 depend on its value before the set). */
839 /* And the set is not guaranteed to be executed once
840 the loop starts, or the value before the set is
841 needed before the set occurs...
843 ??? Note we have quadratic behavior here, mitigated
844 by the fact that the previous test will often fail for
845 large loops. Rather than re-scanning the entire loop
846 each time for register usage, we should build tables
847 of the register usage and use them here instead. */
848 && (maybe_never
850 /* It is unsafe to move the set. However, it may be OK to
851 move the source into a new pseudo, and substitute a
852 reg-to-reg copy for the original insn.
854 This code used to consider it OK to move a set of a variable
855 which was not created by the user and not used in an exit
856 test.
857 That behavior is incorrect and was removed. */
860 /* Don't try to optimize a MODE_CC set with a constant
861 source. It probably will be combined with a conditional
862 jump. */
865 ;
866 /* Don't try to optimize a register that was made
867 by loop-optimization for an inner loop.
868 We don't know its life-span, so we can't compute
869 the benefit. */
871 ;
872 /* Don't move the source and add a reg-to-reg copy:
873 - with -Os (this certainly increases size),
874 - if the mode doesn't support copy operations (obviously),
875 - if the source is already a reg (the motion will gain nothing),
876 - if the source is a legitimate constant (likewise). */
878 && (optimize_size
883 ;
886 || (tem2
889 || (tem1
890 = consec_sets_invariant_p
893 p)))
894 /* If the insn can cause a trap (such as divide by zero),
895 can't move it unless it's guaranteed to be executed
896 once loop is entered. Even a function call might
897 prevent the trap insn from being reached
898 (since it might exit!) */
901 {
905 /* A potential lossage is where we have a case where two insns
906 can be combined as long as they are both in the loop, but
907 we move one of them outside the loop. For large loops,
908 this can lose. The most common case of this is the address
909 of a function being called.
911 Therefore, if this register is marked as being used
912 exactly once if we are in a loop with calls
913 (a "large loop"), see if we can replace the usage of
914 this register with the source of this SET. If we can,
915 delete this insn.
917 Don't do this if P has a REG_RETVAL note or if we have
918 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
930 && (! SMALL_REGISTER_CLASSES
935 /* This test is not redundant; SET_SRC (set) might be
936 a call-clobbered register and the life of REGNO
937 might span a call. */
944 {
945 /* Replace any usage in a REG_EQUAL note. Must copy
946 the new source, so that we don't get rtx sharing
947 between the SET_SOURCE and REG_NOTES of insn p. */
949 = (replace_rtx
955 i++)
958 }
967 m->consec
978 /* Set M->cond if either loop_invariant_p
979 or consec_sets_invariant_p returned 2
980 (only conditionally invariant). */
990 /* Add M to the end of the chain MOVABLES. */
994 {
995 /* It is possible for the first instruction to have a
996 REG_EQUAL note but a non-invariant SET_SRC, so we must
997 remember the status of the first instruction in case
998 the last instruction doesn't have a REG_EQUAL note. */
1001 /* Skip this insn, not checking REG_LIBCALL notes. */
1003 /* Skip the consecutive insns, if there are any. */
1005 /* Back up to the last insn of the consecutive group. */
1008 /* We must now reset m->move_insn, m->is_equiv, and
1009 possibly m->set_src to correspond to the effects of
1010 all the insns. */
1014 else
1015 {
1019 else
1022 }
1023 m->is_equiv
1025 }
1026 }
1027 /* If this register is always set within a STRICT_LOW_PART
1028 or set to zero, then its high bytes are constant.
1029 So clear them outside the loop and within the loop
1030 just load the low bytes.
1031 We must check that the machine has an instruction to do so.
1032 Also, if the value loaded into the register
1033 depends on the same register, this cannot be done. */
1043 {
1046 {
1061 /* If the insn may not be executed on some cycles,
1062 we can't clear the whole reg; clear just high part.
1063 Not even if the reg is used only within this loop.
1064 Consider this:
1065 while (1)
1066 while (s != t) {
1067 if (foo ()) x = *s;
1068 use (x);
1069 }
1070 Clearing x before the inner loop could clobber a value
1071 being saved from the last time around the outer loop.
1072 However, if the reg is not used outside this loop
1073 and all uses of the register are in the same
1074 basic block as the store, there is no problem.
1076 If this insn was made by loop, we don't know its
1077 INSN_LUID and hence must make a conservative
1078 assumption. */
1081 || (labels_in_range_p
1085 else
1094 i++)
1096 /* Add M to the end of the chain MOVABLES. */
1098 }
1099 }
1100 }
1101 }
1102 /* Past a call insn, we get to insns which might not be executed
1103 because the call might exit. This matters for insns that trap.
1104 Constant and pure call insns always return, so they don't count. */
1107 /* Past a label or a jump, we get to insns for which we
1108 can't count on whether or how many times they will be
1109 executed during each iteration. Therefore, we can
1110 only move out sets of trivial variables
1111 (those not used after the loop). */
1112 /* Similar code appears twice in strength_reduce. */
1114 /* If we enter the loop in the middle, and scan around to the
1115 beginning, don't set maybe_never for that. This must be an
1116 unconditional jump, otherwise the code at the top of the
1117 loop might never be executed. Unconditional jumps are
1118 followed by a barrier then the loop_end. */
1124 {
1125 /* At the virtual top of a converted loop, insns are again known to
1126 be executed: logically, the loop begins here even though the exit
1127 code has been duplicated. */
1131 loop_depth++;
1133 loop_depth--;
1134 }
1135 }
1137 /* If one movable subsumes another, ignore that other. */
1141 /* For each movable insn, see if the reg that it loads
1142 leads when it dies right into another conditionally movable insn.
1143 If so, record that the second insn "forces" the first one,
1144 since the second can be moved only if the first is. */
1148 /* See if there are multiple movable insns that load the same value.
1149 If there are, make all but the first point at the first one
1150 through the `match' field, and add the priorities of them
1151 all together as the priority of the first. */
1155 /* Now consider each movable insn to decide whether it is worth moving.
1156 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1158 For machines with few registers this increases code size, so do not
1159 move moveables when optimizing for code size on such machines.
1160 (The 18 below is the value for i386.) */
1164 {
1167 /* Recalculate regs->array if move_movables has created new
1168 registers. */
1170 {
1176 ;
1181 }
1182 }
1184 /* Now candidates that still are negative are those not moved.
1185 Change regs->array[I].set_in_loop to indicate that those are not actually
1186 invariant. */
1191 /* Now that we've moved some things out of the loop, we might be able to
1192 hoist even more memory references. */
1195 /* Recalculate regs->array if load_mems has created new registers. */
1203 ;
1210 {
1212 /* Ensure our label doesn't go away. */
1223 }
1226 /* The movable information is required for strength reduction. */
1232 }
1233 \f
1234 /* Add elements to *OUTPUT to record all the pseudo-regs
1235 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1237 static void
1239 {
1247 {
1265 }
1269 {
1273 {
1282 }
1283 }
1284 }
1285 \f
1286 /* Check what regs are referred to in the libcall block ending with INSN,
1287 aside from those mentioned in the equivalent value.
1288 If there are none, return 0.
1289 If there are one or more, return an EXPR_LIST containing all of them. */
1291 static rtx
1293 {
1298 /* First, find all the regs used in the libcall block
1299 that are not mentioned as inputs to the result. */
1302 {
1306 }
1309 }
1310 \f
1311 /* Return 1 if all uses of REG
1312 are between INSN and the end of the basic block. */
1314 static int
1316 {
1318 rtx p;
1323 /* Search this basic block for the already recorded last use of the reg. */
1325 {
1327 {
1333 /* Ordinary insn: if this is the last use, we win. */
1339 /* Jump insn: if this is the last use, we win. */
1342 /* Otherwise, it's the end of the basic block, so we lose. */
1347 /* It's the end of the basic block, so we lose. */
1352 }
1353 }
1355 /* The "last use" that was recorded can't be found after the first
1356 use. This can happen when the last use was deleted while
1357 processing an inner loop, this inner loop was then completely
1358 unrolled, and the outer loop is always exited after the inner loop,
1359 so that everything after the first use becomes a single basic block. */
1361 }
1362 \f
1363 /* Compute the benefit of eliminating the insns in the block whose
1364 last insn is LAST. This may be a group of insns used to compute a
1365 value directly or can contain a library call. */
1367 static int
1369 {
1370 rtx insn;
1375 {
1378 routine. */
1382 benefit++;
1383 }
1386 }
1387 \f
1388 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1390 static rtx
1392 {
1394 {
1395 rtx temp;
1397 /* If first insn of libcall sequence, skip to end. */
1398 /* Do this at start of loop, since INSN is guaranteed to
1399 be an insn here. */
1404 do
1407 }
1410 }
1412 /* Ignore any movable whose insn falls within a libcall
1413 which is part of another movable.
1414 We make use of the fact that the movable for the libcall value
1415 was made later and so appears later on the chain. */
1417 static void
1419 {
1423 {
1424 /* Is this a movable for the value of a libcall? */
1427 {
1428 rtx insn;
1429 /* Check for earlier movables inside that range,
1430 and mark them invalid. We cannot use LUIDs here because
1431 insns created by loop.c for prior loops don't have LUIDs.
1432 Rather than reject all such insns from movables, we just
1433 explicitly check each insn in the libcall (since invariant
1434 libcalls aren't that common). */
1439 }
1440 }
1441 }
1443 /* For each movable insn, see if the reg that it loads
1444 leads when it dies right into another conditionally movable insn.
1445 If so, record that the second insn "forces" the first one,
1446 since the second can be moved only if the first is. */
1448 static void
1450 {
1454 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1456 {
1459 /* ??? Could this be a bug? What if CSE caused the
1460 register of M1 to be used after this insn?
1461 Since CSE does not update regno_last_uid,
1462 this insn M->insn might not be where it dies.
1463 But very likely this doesn't matter; what matters is
1464 that M's reg is computed from M1's reg. */
1469 /* If m->consec, m->set_src isn't valid. */
1473 /* Increase the priority of the moving the first insn
1474 since it permits the second to be moved as well.
1475 Likewise for insns already forced by the first insn. */
1477 {
1482 {
1485 }
1486 }
1487 }
1488 }
1489 \f
1490 /* Find invariant expressions that are equal and can be combined into
1491 one register. */
1493 static void
1495 {
1500 /* Regs that are set more than once are not allowed to match
1501 or be matched. I'm no longer sure why not. */
1502 /* Only pseudo registers are allowed to match or be matched,
1503 since move_movables does not validate the change. */
1504 /* Perhaps testing m->consec_sets would be more appropriate here? */
1511 {
1518 /* We want later insns to match the first one. Don't make the first
1519 one match any later ones. So start this loop at m->next. */
1525 /* A reg used outside the loop mustn't be eliminated. */
1527 /* A reg used for zero-extending mustn't be eliminated. */
1530 ||
1531 (
1532 /* Can combine regs with different modes loaded from the
1533 same constant only if the modes are the same or
1534 if both are integer modes with M wider or the same
1535 width as M1. The check for integer is redundant, but
1536 safe, since the only case of differing destination
1537 modes with equal sources is when both sources are
1538 VOIDmode, i.e., CONST_INT. */
1544 /* See if the source of M1 says it matches M. */
1551 {
1557 }
1558 }
1560 /* Now combine the regs used for zero-extension.
1561 This can be done for those not marked `global'
1562 provided their lives don't overlap. */
1566 {
1569 /* Combine all the registers for extension from mode MODE.
1570 Don't combine any that are used outside this loop. */
1574 {
1581 {
1582 /* First one: don't check for overlap, just record it. */
1585 }
1587 /* Make sure they extend to the same mode.
1588 (Almost always true.) */
1592 /* We already have one: check for overlap with those
1593 already combined together. */
1600 /* No overlap: we can combine this with the others. */
1606 overlap:
1607 ;
1608 }
1609 }
1611 /* Clean up. */
1613 }
1615 /* Returns the number of movable instructions in LOOP that were not
1616 moved outside the loop. */
1618 static int
1620 {
1629 }
1631 \f
1632 /* Return 1 if regs X and Y will become the same if moved. */
1634 static int
1636 {
1653 }
1655 /* Return 1 if X and Y are identical-looking rtx's.
1656 This is the Lisp function EQUAL for rtx arguments.
1658 If two registers are matching movables or a movable register and an
1659 equivalent constant, consider them equal. */
1661 static int
1664 {
1678 /* If we have a register and a constant, they may sometimes be
1679 equal. */
1682 {
1687 }
1690 {
1695 }
1697 /* Otherwise, rtx's of different codes cannot be equal. */
1701 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1702 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1707 /* These three types of rtx's can be compared nonrecursively. */
1716 /* Compare the elements. If any pair of corresponding elements
1717 fail to match, return 0 for the whole things. */
1721 {
1723 {
1735 /* Two vectors must have the same length. */
1739 /* And the corresponding elements must match. */
1758 /* These are just backpointers, so they don't matter. */
1764 /* It is believed that rtx's at this level will never
1765 contain anything but integers and other rtx's,
1766 except for within LABEL_REFs and SYMBOL_REFs. */
1769 }
1770 }
1772 }
1773 \f
1774 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1775 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1776 references is incremented once for each added note. */
1778 static void
1780 {
1784 rtx insn;
1787 {
1788 /* This code used to ignore labels that referred to dispatch tables to
1789 avoid flow generating (slightly) worse code.
1791 We no longer ignore such label references (see LABEL_REF handling in
1792 mark_jump_label for additional information). */
1795 {
1800 }
1801 }
1805 {
1811 }
1812 }
1813 \f
1814 /* Scan MOVABLES, and move the insns that deserve to be moved.
1815 If two matching movables are combined, replace one reg with the
1816 other throughout. */
1818 static void
1821 {
1826 rtx p;
1829 /* Map of pseudo-register replacements to handle combining
1830 when we move several insns that load the same value
1831 into different pseudo-registers. */
1836 {
1837 /* Describe this movable insn. */
1840 {
1861 }
1863 /* Ignore the insn if it's already done (it matched something else).
1864 Otherwise, see if it is now safe to move. */
1876 {
1878 rtx p;
1881 /* We have an insn that is safe to move.
1882 Compute its desirability. */
1893 /* An insn MUST be moved if we already moved something else
1894 which is safe only if this one is moved too: that is,
1895 if already_moved[REGNO] is nonzero. */
1897 /* An insn is desirable to move if the new lifetime of the
1898 register is no more than THRESHOLD times the old lifetime.
1899 If it's not desirable, it means the loop is so big
1900 that moving won't speed things up much,
1901 and it is liable to make register usage worse. */
1903 /* It is also desirable to move if it can be moved at no
1904 extra cost because something else was already moved. */
1907 || flag_move_all_movables
1912 {
1921 /* Now move the insns that set the reg. */
1924 {
1927 /* Find the end of this chain of matching regs.
1928 Thus, we load each reg in the chain from that one reg.
1929 And that reg is loaded with 0 directly,
1930 since it has ->match == 0. */
1936 /* Mark the moved, invariant reg as being allowed to
1937 share a hard reg with the other matching invariant. */
1941 regs_may_share
1944 regs_may_share));
1952 }
1953 /* If we are to re-generate the item being moved with a
1954 new move insn, first delete what we have and then emit
1955 the move insn before the loop. */
1957 {
1961 {
1962 /* If this is the first insn of a library call sequence,
1963 something is very wrong. */
1968 /* If this is the last insn of a libcall sequence, then
1969 delete every insn in the sequence except the last.
1970 The last insn is handled in the normal manner. */
1973 {
1977 }
1982 /* simplify_giv_expr expects that it can walk the insns
1983 at m->insn forwards and see this old sequence we are
1984 tossing here. delete_insn does preserve the next
1985 pointers, but when we skip over a NOTE we must fix
1986 it up. Otherwise that code walks into the non-deleted
1987 insn stream. */
1992 {
1993 /* Replace the original insn with a move from
1994 our newly created temp. */
2000 }
2001 }
2020 /* The more regs we move, the less we like moving them. */
2022 }
2023 else
2024 {
2026 {
2029 /* If first insn of libcall sequence, skip to end. */
2030 /* Do this at start of loop, since p is guaranteed to
2031 be an insn here. */
2036 /* If last insn of libcall sequence, move all
2037 insns except the last before the loop. The last
2038 insn is handled in the normal manner. */
2041 {
2049 {
2050 rtx body;
2051 rtx n;
2052 rtx next;
2059 /* Find the next insn after TEMP,
2060 not counting USE or NOTE insns. */
2068 /* If that is the call, this may be the insn
2069 that loads the function address.
2071 Extract the function address from the insn
2072 that loads it into a register.
2073 If this insn was cse'd, we get incorrect code.
2075 So emit a new move insn that copies the
2076 function address into the register that the
2077 call insn will use. flow.c will delete any
2078 redundant stores that we have created. */
2083 NULL_RTX)))
2084 {
2090 }
2091 /* We have the call insn.
2092 If it uses the register we suspect it might,
2093 load it with the correct address directly. */
2098 gen_move_insn
2102 {
2104 /* Because the USAGE information potentially
2105 contains objects other than hard registers
2106 we need to copy it. */
2110 }
2111 else
2120 }
2123 }
2125 {
2126 /* P sets REG to zero; but we should clear only
2127 the bits that are not covered by the mode
2128 m->savemode. */
2130 rtx sequence;
2131 rtx tem;
2134 tem = expand_simple_binop
2147 }
2149 {
2151 /* Because the USAGE information potentially
2152 contains objects other than hard registers
2153 we need to copy it. */
2157 }
2159 {
2160 rtx seq;
2161 /* The SET_SRC might not be invariant, so we must
2162 use the REG_EQUAL note. */
2175 }
2177 {
2185 }
2186 else
2190 {
2194 /* If there is a REG_EQUAL note present whose value
2195 is not loop invariant, then delete it, since it
2196 may cause problems with later optimization passes.
2197 It is possible for cse to create such notes
2198 like this as a result of record_jump_cond. */
2203 }
2212 /* If library call, now fix the REG_NOTES that contain
2213 insn pointers, namely REG_LIBCALL on FIRST
2214 and REG_RETVAL on I1. */
2216 {
2220 }
2226 /* simplify_giv_expr expects that it can walk the insns
2227 at m->insn forwards and see this old sequence we are
2228 tossing here. delete_insn does preserve the next
2229 pointers, but when we skip over a NOTE we must fix
2230 it up. Otherwise that code walks into the non-deleted
2231 insn stream. */
2236 {
2237 rtx seq;
2238 /* Replace the original insn with a move from
2239 our newly created temp. */
2245 }
2246 }
2248 /* The more regs we move, the less we like moving them. */
2250 }
2255 {
2256 /* Any other movable that loads the same register
2257 MUST be moved. */
2260 /* This reg has been moved out of one loop. */
2263 /* The reg set here is now invariant. */
2265 {
2269 }
2271 /* Change the length-of-life info for the register
2272 to say it lives at least the full length of this loop.
2273 This will help guide optimizations in outer loops. */
2276 /* This is the old insn before all the moved insns.
2277 We can't use the moved insn because it is out of range
2278 in uid_luid. Only the old insns have luids. */
2282 }
2284 /* Combine with this moved insn any other matching movables. */
2289 {
2290 rtx temp;
2292 /* Schedule the reg loaded by M1
2293 for replacement so that shares the reg of M.
2294 If the modes differ (only possible in restricted
2295 circumstances, make a SUBREG.
2297 Note this assumes that the target dependent files
2298 treat REG and SUBREG equally, including within
2299 GO_IF_LEGITIMATE_ADDRESS and in all the
2300 predicates since we never verify that replacing the
2301 original register with a SUBREG results in a
2302 recognizable insn. */
2305 else
2310 /* Get rid of the matching insn
2311 and prevent further processing of it. */
2314 /* If library call, delete all insns. */
2316 NULL_RTX)))
2318 else
2321 /* Any other movable that loads the same register
2322 MUST be moved. */
2325 /* The reg merged here is now invariant,
2326 if the reg it matches is invariant. */
2328 {
2332 i++)
2334 }
2335 }
2336 }
2339 }
2345 }
2350 /* Go through all the instructions in the loop, making
2351 all the register substitutions scheduled in REG_MAP. */
2354 {
2358 }
2360 /* Clean up. */
2363 }
2366 static void
2368 {
2371 else
2374 }
2377 static void
2379 {
2384 {
2387 }
2388 }
2389 \f
2390 #if 0
2391 /* Scan X and replace the address of any MEM in it with ADDR.
2392 REG is the address that MEM should have before the replacement. */
2394 static void
2396 {
2405 {
2417 /* Short cut for very common case. */
2422 /* Short cut for very common case. */
2427 /* If this MEM uses a reg other than the one we expected,
2428 something is wrong. */
2436 }
2440 {
2444 {
2448 }
2449 }
2450 }
2451 #endif
2452 \f
2453 /* Return the number of memory refs to addresses that vary
2454 in the rtx X. */
2456 static int
2458 {
2469 {
2486 }
2491 {
2495 {
2499 }
2500 }
2502 }
2503 \f
2504 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2505 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2506 `unknown_address_altered', `unknown_constant_address_altered', and
2507 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2508 list `store_mems' in LOOP. */
2510 static void
2512 {
2514 rtx insn;
2518 /* The label after END. Jumping here is just like falling off the
2519 end of the loop. We use next_nonnote_insn instead of next_label
2520 as a hedge against the (pathological) case where some actual insn
2521 might end up between the two. */
2540 /* If loop opts run twice, this was set on 1st pass for 2nd. */
2545 {
2547 {
2550 }
2551 }
2555 {
2557 {
2560 {
2562 /* Count number of loops contained in this one. */
2564 }
2571 {
2574 }
2584 {
2588 {
2593 {
2596 }
2597 else
2598 {
2601 }
2603 do
2604 {
2606 {
2608 {
2609 /* Something tricky. */
2612 }
2615 {
2616 /* A jump outside the current loop. */
2619 }
2620 }
2624 }
2626 }
2627 else
2628 {
2629 /* A return, or something tricky. */
2631 }
2632 }
2633 /* Fall through. */
2654 }
2655 }
2657 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2659 anywhere. */
2661 /* We don't want loads for MEMs moved to a location before the
2662 one at which their stack memory becomes allocated. (Note
2663 that this is not a problem for malloc, etc., since those
2664 require actual function calls. */
2665 && ! current_function_calls_alloca
2666 /* There are ways to leave the loop other than falling off the
2667 end. */
2673 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2674 that loop_invariant_p and load_mems can use true_dependence
2675 to determine what is really clobbered. */
2677 {
2680 loop_info->store_mems
2682 }
2684 {
2687 loop_info->store_mems
2689 }
2690 }
2691 \f
2692 /* Invalidate all loops containing LABEL. */
2694 static void
2696 {
2700 }
2702 /* Scan the function looking for loops. Record the start and end of each loop.
2703 Also mark as invalid loops any loops that contain a setjmp or are branched
2704 to from outside the loop. */
2706 static void
2708 {
2709 rtx insn;
2710 rtx label;
2720 /* If there are jumps to undefined labels,
2721 treat them as jumps out of any/all loops.
2722 This also avoids writing past end of tables when there are no loops. */
2725 /* Find boundaries of loops, mark which loops are contained within
2726 loops, and invalidate loops that have setjmp. */
2731 {
2734 {
2738 num_loops++;
2762 }
2766 {
2767 /* In this case, we must invalidate our current loop and any
2768 enclosing loop. */
2770 {
2776 }
2777 }
2779 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2780 enclosing loop, but this doesn't matter. */
2782 }
2784 /* Any loop containing a label used in an initializer must be invalidated,
2785 because it can be jumped into from anywhere. */
2789 /* Any loop containing a label used for an exception handler must be
2790 invalidated, because it can be jumped into from anywhere. */
2793 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2794 loop that it is not contained within, that loop is marked invalid.
2795 If any INSN or CALL_INSN uses a label's address, then the loop containing
2796 that label is marked invalid, because it could be jumped into from
2797 anywhere.
2799 Also look for blocks of code ending in an unconditional branch that
2800 exits the loop. If such a block is surrounded by a conditional
2801 branch around the block, move the block elsewhere (see below) and
2802 invert the jump to point to the code block. This may eliminate a
2803 label in our loop and will simplify processing by both us and a
2804 possible second cse pass. */
2808 {
2812 {
2816 }
2823 /* See if this is an unconditional branch outside the loop. */
2831 {
2832 rtx p;
2838 /* Go backwards until we reach the start of the loop, a label,
2839 or a JUMP_INSN. */
2846 ;
2848 /* Check for the case where we have a jump to an inner nested
2849 loop, and do not perform the optimization in that case. */
2852 {
2855 {
2860 }
2861 }
2863 /* Make sure that the target of P is within the current loop. */
2869 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2870 we have a block of code to try to move.
2872 We look backward and then forward from the target of INSN
2873 to find a BARRIER at the same loop depth as the target.
2874 If we find such a BARRIER, we make a new label for the start
2875 of the block, invert the jump in P and point it to that label,
2876 and move the block of code to the spot we found. */
2881 /* Just ignore jumps to labels that were never emitted.
2882 These always indicate compilation errors. */
2886 /* If it's not safe to move the sequence, then we
2887 mustn't try. */
2890 {
2891 rtx target
2895 rtx tmp;
2897 /* Search for possible garbage past the conditional jumps
2898 and look for the last barrier. */
2906 /* Don't move things inside a tablejump. */
2919 /* Don't move things inside a tablejump. */
2930 {
2934 /* Ensure our label doesn't go away. */
2937 /* Verify that uid_loop is large enough and that
2938 we can invert P. */
2940 {
2943 /* If no suitable BARRIER was found, create a suitable
2944 one before TARGET. Since TARGET is a fall through
2945 path, we'll need to insert a jump around our block
2946 and add a BARRIER before TARGET.
2948 This creates an extra unconditional jump outside
2949 the loop. However, the benefits of removing rarely
2950 executed instructions from inside the loop usually
2951 outweighs the cost of the extra unconditional jump
2952 outside the loop. */
2954 {
2955 rtx temp;
2962 }
2964 /* Include the BARRIER after INSN and copy the
2965 block after LOC. */
2970 /* All those insns are now in TARGET_LOOP. */
2976 /* The label jumped to by INSN is no longer a loop
2977 exit. Unless INSN does not have a label (e.g.,
2978 it is a RETURN insn), search loop->exit_labels
2979 to find its label_ref, and remove it. Also turn
2980 off LABEL_OUTSIDE_LOOP_P bit. */
2982 {
2984 r;
2987 {
2991 else
2994 }
3000 /* If we didn't find it, then something is
3001 wrong. */
3004 }
3006 /* P is now a jump outside the loop, so it must be put
3007 in loop->exit_labels, and marked as such.
3008 The easiest way to do this is to just call
3009 mark_loop_jump again for P. */
3012 /* If INSN now jumps to the insn after it,
3013 delete INSN. */
3018 }
3020 /* Continue the loop after where the conditional
3021 branch used to jump, since the only branch insn
3022 in the block (if it still remains) is an inter-loop
3023 branch and hence needs no processing. */
3029 /* This loop will be continued with NEXT_INSN (insn). */
3031 }
3032 }
3033 }
3034 }
3035 }
3037 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
3038 loops it is contained in, mark the target loop invalid.
3040 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
3042 static void
3044 {
3050 {
3062 /* There could be a label reference in here. */
3074 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3086 /* Link together all labels that branch outside the loop. This
3087 is used by final_[bg]iv_value and the loop unrolling code. Also
3088 mark this LABEL_REF so we know that this branch should predict
3089 false. */
3091 /* A check to make sure the label is not in an inner nested loop,
3092 since this does not count as a loop exit. */
3094 {
3099 }
3100 else
3104 {
3113 }
3115 /* If this is inside a loop, but not in the current loop or one enclosed
3116 by it, it invalidates at least one loop. */
3121 /* We must invalidate every nested loop containing the target of this
3122 label, except those that also contain the jump insn. */
3125 {
3126 /* Stop when we reach a loop that also contains the jump insn. */
3131 /* If we get here, we know we need to invalidate a loop. */
3138 }
3142 /* If this is not setting pc, ignore. */
3164 /* Strictly speaking this is not a jump into the loop, only a possible
3165 jump out of the loop. However, we have no way to link the destination
3166 of this jump onto the list of exit labels. To be safe we mark this
3167 loop and any containing loops as invalid. */
3169 {
3171 {
3177 }
3178 }
3180 }
3181 }
3182 \f
3183 /* Return nonzero if there is a label in the range from
3184 insn INSN to and including the insn whose luid is END
3185 INSN must have an assigned luid (i.e., it must not have
3186 been previously created by loop.c). */
3188 static int
3190 {
3192 {
3196 }
3199 }
3201 /* Record that a memory reference X is being set. */
3203 static void
3206 {
3212 /* Count number of memory writes.
3213 This affects heuristics in strength_reduce. */
3216 /* BLKmode MEM means all memory is clobbered. */
3218 {
3221 else
3225 }
3229 }
3231 /* X is a value modified by an INSN that references a biv inside a loop
3232 exit test (ie, X is somehow related to the value of the biv). If X
3233 is a pseudo that is used more than once, then the biv is (effectively)
3234 used more than once. DATA is a pointer to a loop_regs structure. */
3236 static void
3238 {
3253 /* If we do not have usage information, or if we know the register
3254 is used more than once, note that fact for check_dbra_loop. */
3259 }
3260 \f
3261 /* Return nonzero if the rtx X is invariant over the current loop.
3263 The value is 2 if we refer to something only conditionally invariant.
3265 A memory ref is invariant if it is not volatile and does not conflict
3266 with anything stored in `loop_info->store_mems'. */
3268 int
3270 {
3277 rtx mem_list_entry;
3283 {
3291 /* A LABEL_REF is normally invariant, however, if we are unrolling
3292 loops, and this label is inside the loop, then it isn't invariant.
3293 This is because each unrolled copy of the loop body will have
3294 a copy of this label. If this was invariant, then an insn loading
3295 the address of this label into a register might get moved outside
3296 the loop, and then each loop body would end up using the same label.
3298 We don't know the loop bounds here though, so just fail for all
3299 labels. */
3302 else
3320 /* Out-of-range regs can occur when we are called from unrolling.
3321 These registers created by the unroller are set in the loop,
3322 hence are never invariant.
3323 Other out-of-range regs can be generated by load_mems; those that
3324 are written to in the loop are not invariant, while those that are
3325 not written to are invariant. It would be easy for load_mems
3326 to set n_times_set correctly for these registers, however, there
3327 is no easy way to distinguish them from registers created by the
3328 unroller. */
3339 /* Volatile memory references must be rejected. Do this before
3340 checking for read-only items, so that volatile read-only items
3341 will be rejected also. */
3345 /* See if there is any dependence between a store and this load. */
3348 {
3354 }
3356 /* It's not invalidated by a store in memory
3357 but we must still verify the address is invariant. */
3361 /* Don't mess with insns declared volatile. */
3368 }
3372 {
3374 {
3380 }
3382 {
3385 {
3391 }
3393 }
3394 }
3397 }
3398 \f
3399 /* Return nonzero if all the insns in the loop that set REG
3400 are INSN and the immediately following insns,
3401 and if each of those insns sets REG in an invariant way
3402 (not counting uses of REG in them).
3404 The value is 2 if some of these insns are only conditionally invariant.
3406 We assume that INSN itself is the first set of REG
3407 and that its source is invariant. */
3409 static int
3411 rtx insn)
3412 {
3416 rtx temp;
3417 /* Number of sets we have to insist on finding after INSN. */
3423 /* If N_SETS hit the limit, we can't rely on its value. */
3430 {
3432 rtx set;
3437 /* If library call, skip to end of it. */
3446 {
3451 {
3452 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3453 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3454 notes are OK. */
3460 }
3461 }
3463 count--;
3465 {
3468 }
3469 }
3472 /* If loop_invariant_p ever returned 2, we return 2. */
3474 }
3475 \f
3476 /* Look at all uses (not sets) of registers in X. For each, if it is
3477 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3478 a different insn, set USAGE[REGNO] to const0_rtx. */
3480 static void
3482 {
3494 {
3495 /* Don't count SET_DEST if it is a REG; otherwise count things
3496 in SET_DEST because if a register is partially modified, it won't
3497 show up as a potential movable so we don't care how USAGE is set
3498 for it. */
3502 }
3503 else
3505 {
3511 }
3512 }
3513 \f
3514 /* Count and record any set in X which is contained in INSN. Update
3515 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3516 in X. */
3518 static void
3520 {
3522 /* Don't move a reg that has an explicit clobber.
3523 It's not worth the pain to try to do it correctly. */
3527 {
3535 {
3539 {
3540 /* If this is the first setting of this reg
3541 in current basic block, and it was set before,
3542 it must be set in two basic blocks, so it cannot
3543 be moved out of the loop. */
3547 /* If this is not first setting in current basic block,
3548 see if reg was used in between previous one and this.
3549 If so, neither one can be moved. */
3556 }
3557 }
3558 }
3559 }
3560 \f
3561 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3562 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3563 contained in insn INSN is used by any insn that precedes INSN in
3564 cyclic order starting from the loop entry point.
3566 We don't want to use INSN_LUID here because if we restrict INSN to those
3567 that have a valid INSN_LUID, it means we cannot move an invariant out
3568 from an inner loop past two loops. */
3570 static int
3572 {
3574 rtx p;
3576 /* Scan forward checking for register usage. If we hit INSN, we
3577 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3579 {
3585 }
3588 }
3589 \f
3591 /* Information we collect about arrays that we might want to prefetch. */
3592 struct prefetch_info
3593 {
3597 index. */
3598 HOST_WIDE_INT index;
3600 iteration. */
3602 prefetch area in one iteration. */
3604 This is set only for loops with known
3605 iteration counts and is 0xffffffff
3606 otherwise. */
3610 };
3612 /* Data used by check_store function. */
3613 struct check_store_data
3614 {
3615 rtx mem_address;
3617 };
3623 /* Set mem_write when mem_address is found. Used as callback to
3624 note_stores. */
3625 static void
3627 {
3632 }
3633 \f
3634 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3635 important to get some addresses combined. Later more sophisticated
3636 transformations can be added when necessary.
3638 ??? Same trick with swapping operand is done at several other places.
3639 It can be nice to develop some common way to handle this. */
3641 static int
3643 {
3655 {
3660 }
3662 /* Compare the elements. If any pair of corresponding elements fails to
3663 match, return 0 for the whole thing. */
3667 {
3669 {
3681 /* Two vectors must have the same length. */
3685 /* And the corresponding elements must match. */
3703 /* These are just backpointers, so they don't matter. */
3709 /* It is believed that rtx's at this level will never
3710 contain anything but integers and other rtx's,
3711 except for within LABEL_REFs and SYMBOL_REFs. */
3714 }
3715 }
3717 }
3718 \f
3719 /* Remove constant addition value from the expression X (when present)
3720 and return it. */
3722 static HOST_WIDE_INT
3724 {
3728 /* Avoid clobbering a shared CONST expression. */
3730 {
3734 {
3737 }
3739 }
3742 {
3745 }
3747 /* For plus expression recurse on ourself. */
3749 {
3753 /* In case our parameter was constant, remove extra zero from the
3754 expression. */
3759 }
3762 }
3764 /* Attempt to identify accesses to arrays that are most likely to cause cache
3765 misses, and emit prefetch instructions a few prefetch blocks forward.
3767 To detect the arrays we use the GIV information that was collected by the
3768 strength reduction pass.
3770 The prefetch instructions are generated after the GIV information is done
3771 and before the strength reduction process. The new GIVs are injected into
3772 the strength reduction tables, so the prefetch addresses are optimized as
3773 well.
3775 GIVs are split into base address, stride, and constant addition values.
3776 GIVs with the same address, stride and close addition values are combined
3777 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3778 for write instructions can be used for the block we write to, on machines
3779 that support write prefetches.
3781 Several heuristics are used to determine when to prefetch. They are
3782 controlled by defined symbols that can be overridden for each target. */
3784 static void
3786 {
3802 /* Consider only loops w/o calls. When a call is done, the loop is probably
3803 slow enough to read the memory. */
3805 {
3810 }
3812 /* Don't prefetch in loops known to have few iterations. */
3816 {
3821 }
3823 /* Search all induction variables and pick those interesting for the prefetch
3824 machinery. */
3826 {
3832 /* Expect all BIVs to be executed in each iteration. This makes our
3833 analysis more conservative. */
3835 {
3836 /* Discard non-constant additions that we can't handle well yet, and
3837 BIVs that are executed multiple times; such BIVs ought to be
3838 handled in the nested loop. We accept not_every_iteration BIVs,
3839 since these only result in larger strides and make our
3840 heuristics more conservative. */
3842 {
3844 {
3850 }
3852 }
3855 {
3857 {
3863 }
3865 }
3869 }
3875 {
3876 rtx address;
3877 rtx temp;
3886 /* See whether an induction variable is interesting to us and if
3887 not, report the reason. */
3891 /* We are interested only in constant stride memory references
3892 in order to be able to compute density easily. */
3896 else
3897 {
3900 {
3903 }
3905 /* On some targets, reversed order prefetches are not
3906 worthwhile. */
3910 /* Prefetch of accesses with an extreme stride might not be
3911 worthwhile, either. */
3916 /* Ignore GIVs with varying add values; we can't predict the
3917 value for the next iteration. */
3921 /* Ignore GIVs in the nested loops; they ought to have been
3922 handled already. */
3925 }
3928 {
3934 }
3936 /* Determine the pointer to the basic array we are examining. It is
3937 the sum of the BIV's initial value and the GIV's add_val. */
3947 /* When the GIV is not always executed, we might be better off by
3948 not dirtying the cache pages. */
3951 else
3952 {
3957 }
3959 /* Attempt to find another prefetch to the same array and see if we
3960 can merge this one. */
3964 {
3965 /* In case both access same array (same location
3966 just with small difference in constant indexes), merge
3967 the prefetches. Just do the later and the earlier will
3968 get prefetched from previous iteration.
3969 The artificial threshold should not be too small,
3970 but also not bigger than small portion of memory usually
3971 traversed by single loop. */
3974 {
3983 }
3987 {
3992 }
3993 }
3995 /* Merging failed. */
3997 {
4005 num_prefetches++;
4007 {
4012 }
4013 }
4014 }
4015 }
4018 {
4021 /* Attempt to calculate the total number of bytes fetched by all
4022 iterations of the loop. Avoid overflow. */
4027 else
4032 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4037 {
4042 }
4043 else
4044 {
4050 }
4051 else
4054 /* Find how many prefetch instructions we'll use within the loop. */
4056 {
4062 }
4063 }
4065 /* Determine how many iterations ahead to prefetch within the loop, based
4066 on how many prefetches we currently expect to do within the loop. */
4068 {
4070 {
4076 }
4077 }
4078 /* We'll also use AHEAD to determine how many prefetch instructions to
4079 emit before a loop, so don't leave it zero. */
4084 {
4085 /* Update if we've decided not to prefetch anything within the loop. */
4089 /* Find how many prefetch instructions we'll use before the loop. */
4091 {
4099 }
4102 {
4122 }
4123 }
4126 {
4127 /* Record that this loop uses prefetch instructions. */
4131 {
4136 }
4137 }
4140 {
4144 {
4146 rtx insn;
4150 rtx seq;
4152 /* We can save some effort by offsetting the address on
4153 architectures with offsettable memory references. */
4156 else
4157 {
4163 }
4166 /* Make sure the address operand is valid for prefetch. */
4176 /* Check all insns emitted and record the new GIV
4177 information. */
4180 {
4185 }
4186 }
4189 {
4190 /* Emit insns before the loop to fetch the first cache lines or,
4191 if we're not prefetching within the loop, everything we expect
4192 to need. */
4194 {
4202 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4203 non-constant INIT_VAL to have the same mode as REG, which
4204 in this case we know to be Pmode. */
4206 {
4207 rtx seq;
4214 }
4220 loop_start);
4221 }
4222 }
4223 }
4226 }
4227 \f
4228 /* Communication with routines called via `note_stores'. */
4232 /* Dummy register to have nonzero DEST_REG for DEST_ADDR type givs. */
4236 /* ??? Unfinished optimizations, and possible future optimizations,
4237 for the strength reduction code. */
4239 /* ??? The interaction of biv elimination, and recognition of 'constant'
4240 bivs, may cause problems. */
4242 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4243 performance problems.
4245 Perhaps don't eliminate things that can be combined with an addressing
4246 mode. Find all givs that have the same biv, mult_val, and add_val;
4247 then for each giv, check to see if its only use dies in a following
4248 memory address. If so, generate a new memory address and check to see
4249 if it is valid. If it is valid, then store the modified memory address,
4250 otherwise, mark the giv as not done so that it will get its own iv. */
4252 /* ??? Could try to optimize branches when it is known that a biv is always
4253 positive. */
4255 /* ??? When replace a biv in a compare insn, we should replace with closest
4256 giv so that an optimized branch can still be recognized by the combiner,
4257 e.g. the VAX acb insn. */
4259 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4260 was rerun in loop_optimize whenever a register was added or moved.
4261 Also, some of the optimizations could be a little less conservative. */
4262 \f
4263 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4264 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4265 callback.
4267 NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at
4268 least once for every loop iteration except for the last one.
4270 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4271 loop iteration.
4272 */
4273 void
4275 {
4280 rtx p;
4282 /* If loop_scan_start points to the loop exit test, we have to be wary of
4283 subversive use of gotos inside expression statements. */
4287 /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */
4291 {
4294 /* Past CODE_LABEL, we get to insns that may be executed multiple
4295 times. The only way we can be sure that they can't is if every
4296 jump insn between here and the end of the loop either
4297 returns, exits the loop, is a jump to a location that is still
4298 behind the label, or is a jump to the loop start. */
4301 {
4307 {
4312 {
4315 else
4319 }
4327 {
4330 }
4331 }
4332 }
4334 /* Past a jump, we get to insns for which we can't count
4335 on whether they will be executed during each iteration. */
4336 /* This code appears twice in strength_reduce. There is also similar
4337 code in scan_loop. */
4339 /* If we enter the loop in the middle, and scan around to the
4340 beginning, don't set not_every_iteration for that.
4341 This can be any kind of jump, since we want to know if insns
4342 will be executed if the loop is executed. */
4347 {
4350 /* If this is a jump outside the loop, then it also doesn't
4351 matter. Check to see if the target of this branch is on the
4352 loop->exits_labels list. */
4360 }
4363 {
4364 /* At the virtual top of a converted loop, insns are again known to
4365 be executed each iteration: logically, the loop begins here
4366 even though the exit code has been duplicated.
4368 Insns are also again known to be executed each iteration at
4369 the LOOP_CONT note. */
4375 loop_depth++;
4377 loop_depth--;
4378 }
4380 /* Note if we pass a loop latch. If we do, then we can not clear
4381 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4382 a loop since a jump before the last CODE_LABEL may have started
4383 a new loop iteration.
4385 Note that LOOP_TOP is only set for rotated loops and we need
4386 this check for all loops, so compare against the CODE_LABEL
4387 which immediately follows LOOP_START. */
4392 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4393 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4394 or not an insn is known to be executed each iteration of the
4395 loop, whether or not any iterations are known to occur.
4397 Therefore, if we have just passed a label and have no more labels
4398 between here and the test insn of the loop, and we have not passed
4399 a jump to the top of the loop, then we know these insns will be
4400 executed each iteration. */
4403 && !past_loop_latch
4408 }
4409 }
4410 \f
4411 static void
4413 {
4416 /* Temporary list pointers for traversing ivs->list. */
4423 /* Scan ivs->list to remove all regs that proved not to be bivs.
4424 Make a sanity check against regs->n_times_set. */
4426 {
4428 /* Above happens if register modified by subreg, etc. */
4429 /* Make sure it is not recognized as a basic induction var: */
4431 /* If never incremented, it is invariant that we decided not to
4432 move. So leave it alone. */
4434 {
4445 }
4446 else
4447 {
4452 }
4453 }
4454 }
4457 /* Determine how BIVS are initialized by looking through pre-header
4458 extended basic block. */
4459 static void
4461 {
4463 /* Temporary list pointers for traversing ivs->list. */
4466 rtx p;
4468 /* Find initial value for each biv by searching backwards from loop_start,
4469 halting at first label. Also record any test condition. */
4473 {
4474 rtx test;
4484 /* Record any test of a biv that branches around the loop if no store
4485 between it and the start of loop. We only care about tests with
4486 constants and registers and only certain of those. */
4496 {
4497 /* If an NE test, we have an initial value! */
4499 {
4503 }
4504 else
4506 }
4507 }
4508 }
4511 /* Look at the each biv and see if we can say anything better about its
4512 initial value from any initializing insns set up above. (This is done
4513 in two passes to avoid missing SETs in a PARALLEL.) */
4514 static void
4516 {
4518 /* Temporary list pointers for traversing ivs->list. */
4523 {
4524 rtx src;
4525 rtx note;
4530 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4531 is a constant, use the value of that. */
4537 else
4550 {
4554 {
4557 }
4558 }
4559 /* If we can't make it a giv,
4560 let biv keep initial value of "itself". */
4563 }
4564 }
4567 /* Search the loop for general induction variables. */
4569 static void
4571 {
4573 }
4576 /* For each giv for which we still don't know whether or not it is
4577 replaceable, check to see if it is replaceable because its final value
4578 can be calculated. */
4580 static void
4582 {
4587 {
4593 }
4594 }
4597 /* Return nonzero if it is possible to eliminate the biv BL provided
4598 all givs are reduced. This is possible if either the reg is not
4599 used outside the loop, or we can compute what its final value will
4600 be. */
4602 static int
4605 {
4606 /* For architectures with a decrement_and_branch_until_zero insn,
4607 don't do this if we put a REG_NONNEG note on the endtest for this
4608 biv. */
4610 #ifdef HAVE_decrement_and_branch_until_zero
4612 {
4617 }
4618 #endif
4620 /* Check that biv is used outside loop or if it has a final value.
4621 Compare against bl->init_insn rather than loop->start. We aren't
4622 concerned with any uses of the biv between init_insn and
4623 loop->start since these won't be affected by the value of the biv
4624 elsewhere in the function, so long as init_insn doesn't use the
4625 biv itself. */
4636 {
4644 }
4646 }
4649 /* Reduce each giv of BL that we have decided to reduce. */
4651 static void
4653 {
4657 {
4660 {
4663 /* If the code for derived givs immediately below has already
4664 allocated a new_reg, we must keep it. */
4668 #ifdef AUTO_INC_DEC
4669 /* If the target has auto-increment addressing modes, and
4670 this is an address giv, then try to put the increment
4671 immediately after its use, so that flow can create an
4672 auto-increment addressing mode. */
4673 /* Don't do this for loops entered at the bottom, to avoid
4674 this invalid transformation:
4675 jmp L; -> jmp L;
4676 TOP: TOP:
4677 use giv use giv
4678 L: inc giv
4679 inc biv L:
4680 test biv test giv
4681 cbr TOP cbr TOP
4682 */
4685 /* We don't handle reversed biv's because bl->biv->insn
4686 does not have a valid INSN_LUID. */
4691 {
4692 /* If other giv's have been combined with this one, then
4693 this will work only if all uses of the other giv's occur
4694 before this giv's insn. This is difficult to check.
4696 We simplify this by looking for the common case where
4697 there is one DEST_REG giv, and this giv's insn is the
4698 last use of the dest_reg of that DEST_REG giv. If the
4699 increment occurs after the address giv, then we can
4700 perform the optimization. (Otherwise, the increment
4701 would have to go before other_giv, and we would not be
4702 able to combine it with the address giv to get an
4703 auto-inc address.) */
4705 {
4710 {
4713 else
4715 }
4722 }
4723 /* Check for case where increment is before the address
4724 giv. Do this test in "loop order". */
4733 else
4736 #ifdef HAVE_cc0
4737 {
4738 rtx prev;
4740 /* We can't put an insn immediately after one setting
4741 cc0, or immediately before one using cc0. */
4748 }
4749 #endif
4753 }
4754 #endif
4756 /* For each place where the biv is incremented, add an insn
4757 to increment the new, reduced reg for the giv. */
4759 {
4760 rtx insert_before;
4762 /* Skip if location is the same as a previous one. */
4769 else
4777 /* A multiply is acceptable here
4778 since this is presumed to be seldom executed. */
4782 }
4784 /* Add code at loop start to initialize giv's reduced reg. */
4789 }
4790 }
4791 }
4794 /* Check for givs whose first use is their definition and whose
4795 last use is the definition of another giv. If so, it is likely
4796 dead and should not be used to derive another giv nor to
4797 eliminate a biv. */
4799 static void
4801 {
4805 {
4812 {
4818 }
4819 }
4820 }
4823 static void
4825 {
4829 {
4836 /* Update expression if this was combined, in case other giv was
4837 replaced. */
4842 /* See if this register is known to be a pointer to something. If
4843 so, see if we can find the alignment. First see if there is a
4844 destination register that is a pointer. If so, this shares the
4845 alignment too. Next see if we can deduce anything from the
4846 computational information. If not, and this is a DEST_ADDR
4847 giv, at least we know that it's a pointer, though we don't know
4848 the alignment. */
4856 {
4865 }
4869 {
4877 }
4882 /* Store reduced reg as the address in the memref where we found
4883 this giv. */
4886 {
4888 }
4889 else
4890 {
4892 rtx note;
4894 /* Not replaceable; emit an insn to set the original giv reg from
4895 the reduced giv, same as above. */
4900 /* The original insn may have a REG_EQUAL note. This note is
4901 now incorrect and may result in invalid substitutions later.
4902 The original insn is dead, but may be part of a libcall
4903 sequence, which doesn't seem worth the bother of handling. */
4907 }
4909 /* When a loop is reversed, givs which depend on the reversed
4910 biv, and which are live outside the loop, must be set to their
4911 correct final value. This insn is only needed if the giv is
4912 not replaceable. The correct final value is the same as the
4913 value that the giv starts the reversed loop with. */
4924 {
4929 }
4930 }
4931 }
4934 static int
4937 rtx test_reg)
4938 {
4947 /* Reduce benefit if not replaceable, since we will insert a
4948 move-insn to replace the insn that calculates this giv. Don't do
4949 this unless the giv is a user variable, since it will often be
4950 marked non-replaceable because of the duplication of the exit
4951 code outside the loop. In such a case, the copies we insert are
4952 dead and will be deleted. So they don't have a cost. Similar
4953 situations exist. */
4954 /* ??? The new final_[bg]iv_value code does a much better job of
4955 finding replaceable giv's, and hence this code may no longer be
4956 necessary. */
4961 /* Decrease the benefit to count the add-insns that we will insert
4962 to increment the reduced reg for the giv. ??? This can
4963 overestimate the run-time cost of the additional insns, e.g. if
4964 there are multiple basic blocks that increment the biv, but only
4965 one of these blocks is executed during each iteration. There is
4966 no good way to detect cases like this with the current structure
4967 of the loop optimizer. This code is more accurate for
4968 determining code size than run-time benefits. */
4971 /* Decide whether to strength-reduce this giv or to leave the code
4972 unchanged (recompute it from the biv each time it is used). This
4973 decision can be made independently for each giv. */
4975 #ifdef AUTO_INC_DEC
4976 /* Attempt to guess whether autoincrement will handle some of the
4977 new add insns; if so, increase BENEFIT (undo the subtraction of
4978 add_cost that was done above). */
4980 /* Increasing the benefit is risky, since this is only a guess.
4981 Avoid increasing register pressure in cases where there would
4982 be no other benefit from reducing this giv. */
4985 {
5000 }
5001 #endif
5004 }
5007 /* Free IV structures for LOOP. */
5009 static void
5011 {
5018 {
5024 {
5027 }
5029 {
5032 }
5036 }
5037 }
5040 /* Perform strength reduction and induction variable elimination.
5042 Pseudo registers created during this function will be beyond the
5043 last valid index in several tables including
5044 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5045 problem here, because the added registers cannot be givs outside of
5046 their loop, and hence will never be reconsidered. But scan_loop
5047 must check regnos to make sure they are in bounds. */
5049 static void
5051 {
5055 rtx p;
5056 /* Temporary list pointer for traversing ivs->list. */
5058 /* Ratio of extra register life span we can justify
5059 for saving an instruction. More if loop doesn't call subroutines
5060 since in that case saving an insn makes more difference
5061 and more registers are available. */
5062 /* ??? could set this to last value of threshold in move_movables */
5064 /* Map of pseudo-register replacements. */
5076 /* Find all BIVs in loop. */
5079 /* Exit if there are no bivs. */
5081 {
5082 /* Can still unroll the loop anyways, but indicate that there is no
5083 strength reduction info available. */
5089 }
5091 /* Determine how BIVS are initialized by looking through pre-header
5092 extended basic block. */
5095 /* Look at the each biv and see if we can say anything better about its
5096 initial value from any initializing insns set up above. */
5099 /* Search the loop for general induction variables. */
5102 /* Try to calculate and save the number of loop iterations. This is
5103 set to zero if the actual number can not be calculated. This must
5104 be called after all giv's have been identified, since otherwise it may
5105 fail if the iteration variable is a giv. */
5108 #ifdef HAVE_prefetch
5111 #endif
5113 /* Now for each giv for which we still don't know whether or not it is
5114 replaceable, check to see if it is replaceable because its final value
5115 can be calculated. This must be done after loop_iterations is called,
5116 so that final_giv_value will work correctly. */
5119 /* Try to prove that the loop counter variable (if any) is always
5120 nonnegative; if so, record that fact with a REG_NONNEG note
5121 so that "decrement and branch until zero" insn can be used. */
5124 /* Create reg_map to hold substitutions for replaceable giv regs.
5125 Some givs might have been made from biv increments, so look at
5126 ivs->reg_iv_type for a suitable size. */
5130 /* Examine each iv class for feasibility of strength reduction/induction
5131 variable elimination. */
5134 {
5138 /* Test whether it will be possible to eliminate this biv
5139 provided all givs are reduced. */
5142 /* This will be true at the end, if all givs which depend on this
5143 biv have been strength reduced.
5144 We can't (currently) eliminate the biv unless this is so. */
5147 /* Check each extension dependent giv in this class to see if its
5148 root biv is safe from wrapping in the interior mode. */
5151 /* Combine all giv's for this iv_class. */
5155 {
5163 /* If an insn is not to be strength reduced, then set its ignore
5164 flag, and clear bl->all_reduced. */
5166 /* A giv that depends on a reversed biv must be reduced if it is
5167 used after the loop exit, otherwise, it would have the wrong
5168 value after the loop exit. To make it simple, just reduce all
5169 of such giv's whether or not we know they are used after the loop
5170 exit. */
5175 {
5183 }
5184 else
5185 {
5186 /* Check that we can increment the reduced giv without a
5187 multiply insn. If not, reject it. */
5192 {
5200 }
5201 }
5202 }
5204 /* Check for givs whose first use is their definition and whose
5205 last use is the definition of another giv. If so, it is likely
5206 dead and should not be used to derive another giv nor to
5207 eliminate a biv. */
5210 /* Reduce each giv that we decided to reduce. */
5213 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5214 as not reduced.
5216 For each giv register that can be reduced now: if replaceable,
5217 substitute reduced reg wherever the old giv occurs;
5218 else add new move insn "giv_reg = reduced_reg". */
5221 /* All the givs based on the biv bl have been reduced if they
5222 merit it. */
5224 /* For each giv not marked as maybe dead that has been combined with a
5225 second giv, clear any "maybe dead" mark on that second giv.
5226 v->new_reg will either be or refer to the register of the giv it
5227 combined with.
5229 Doing this clearing avoids problems in biv elimination where
5230 a giv's new_reg is a complex value that can't be put in the
5231 insn but the giv combined with (with a reg as new_reg) is
5232 marked maybe_dead. Since the register will be used in either
5233 case, we'd prefer it be used from the simpler giv. */
5239 /* Try to eliminate the biv, if it is a candidate.
5240 This won't work if ! bl->all_reduced,
5241 since the givs we planned to use might not have been reduced.
5243 We have to be careful that we didn't initially think we could
5244 eliminate this biv because of a giv that we now think may be
5245 dead and shouldn't be used as a biv replacement.
5247 Also, there is the possibility that we may have a giv that looks
5248 like it can be used to eliminate a biv, but the resulting insn
5249 isn't valid. This can happen, for example, on the 88k, where a
5250 JUMP_INSN can compare a register only with zero. Attempts to
5251 replace it with a compare with a constant will fail.
5253 Note that in cases where this call fails, we may have replaced some
5254 of the occurrences of the biv with a giv, but no harm was done in
5255 doing so in the rare cases where it can occur. */
5259 {
5260 /* ?? If we created a new test to bypass the loop entirely,
5261 or otherwise drop straight in, based on this test, then
5262 we might want to rewrite it also. This way some later
5263 pass has more hope of removing the initialization of this
5264 biv entirely. */
5266 /* If final_value != 0, then the biv may be used after loop end
5267 and we must emit an insn to set it just in case.
5269 Reversed bivs already have an insn after the loop setting their
5270 value, so we don't need another one. We can't calculate the
5271 proper final value for such a biv here anyways. */
5280 }
5281 /* See above note wrt final_value. But since we couldn't eliminate
5282 the biv, we must set the value after the loop instead of before. */
5286 }
5288 /* Go through all the instructions in the loop, making all the
5289 register substitutions scheduled in REG_MAP. */
5293 {
5297 }
5300 {
5301 /* When we completely unroll a loop we will likely not need the increment
5302 of the loop BIV and we will not need the conditional branch at the
5303 end of the loop. */
5306 #ifdef HAVE_cc0
5307 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5308 need the comparison before the conditional branch at the end of the
5309 loop. */
5311 #endif
5313 /* We'll need one copy for each loop iteration. */
5316 /* A little slop to account for the ability to remove initialization
5317 code, better CSE, and other secondary benefits of completely
5318 unrolling some loops. */
5321 /* Clamp the value. */
5324 }
5326 /* Unroll loops from within strength reduction so that we can use the
5327 induction variable information that strength_reduce has already
5328 collected. Always unroll loops that would be as small or smaller
5329 unrolled than when rolled. */
5342 }
5343 \f
5344 /*Record all basic induction variables calculated in the insn. */
5345 static rtx
5348 {
5350 rtx set;
5351 rtx dest_reg;
5352 rtx inc_val;
5353 rtx mult_val;
5359 {
5364 {
5369 {
5370 /* It is a possible basic induction variable.
5371 Create and initialize an induction structure for it. */
5378 }
5381 }
5382 }
5384 }
5385 \f
5386 /* Record all givs calculated in the insn.
5387 A register is a giv if: it is only set once, it is a function of a
5388 biv and a constant (or invariant), and it is not a biv. */
5389 static rtx
5392 {
5395 rtx set;
5396 /* Look for a general induction variable in a register. */
5401 {
5402 rtx src_reg;
5403 rtx dest_reg;
5404 rtx add_val;
5405 rtx mult_val;
5406 rtx ext_val;
5409 rtx last_consec_insn;
5418 /* Equivalent expression is a giv. */
5423 /* Don't try to handle any regs made by loop optimization.
5424 We have nothing on them in regno_first_uid, etc. */
5426 /* Don't recognize a BASIC_INDUCT_VAR here. */
5428 /* This must be the only place where the register is set. */
5430 /* or all sets must be consecutive and make a giv. */
5435 {
5438 /* If this is a library call, increase benefit. */
5442 /* Skip the consecutive insns, if there are any. */
5450 }
5451 }
5453 /* Look for givs which are memory addresses. */
5456 maybe_multiple);
5458 /* Update the status of whether giv can derive other givs. This can
5459 change when we pass a label or an insn that updates a biv. */
5463 }
5464 \f
5465 /* Return 1 if X is a valid source for an initial value (or as value being
5466 compared against in an initial test).
5468 X must be either a register or constant and must not be clobbered between
5469 the current insn and the start of the loop.
5471 INSN is the insn containing X. */
5473 static int
5475 {
5479 /* Only consider pseudos we know about initialized in insns whose luids
5480 we know. */
5485 /* Don't use call-clobbered registers across a call which clobbers it. On
5486 some machines, don't use any hard registers at all. */
5488 && (SMALL_REGISTER_CLASSES
5492 /* Don't use registers that have been clobbered before the start of the
5493 loop. */
5498 }
5499 \f
5500 /* Scan X for memory refs and check each memory address
5501 as a possible giv. INSN is the insn whose pattern X comes from.
5502 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5503 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5504 more than once in each loop iteration. */
5506 static void
5509 {
5519 {
5535 {
5536 rtx src_reg;
5537 rtx add_val;
5538 rtx mult_val;
5539 rtx ext_val;
5542 /* This code used to disable creating GIVs with mult_val == 1 and
5543 add_val == 0. However, this leads to lost optimizations when
5544 it comes time to combine a set of related DEST_ADDR GIVs, since
5545 this one would not be seen. */
5550 {
5551 /* Found one; record it. */
5559 }
5560 }
5565 }
5567 /* Recursively scan the subexpressions for other mem refs. */
5573 maybe_multiple);
5577 maybe_multiple);
5578 }
5579 \f
5580 /* Fill in the data about one biv update.
5581 V is the `struct induction' in which we record the biv. (It is
5582 allocated by the caller, with alloca.)
5583 INSN is the insn that sets it.
5584 DEST_REG is the biv's reg.
5586 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5587 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5588 being set to INC_VAL.
5590 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5591 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5592 can be executed more than once per iteration. If MAYBE_MULTIPLE
5593 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5594 executed exactly once per iteration. */
5596 static void
5600 {
5617 /* Add this to the reg's iv_class, creating a class
5618 if this is the first incrementation of the reg. */
5622 {
5623 /* Create and initialize new iv_class. */
5633 /* Set initial value to the reg itself. */
5636 /* We haven't seen the initializing insn yet. */
5646 /* Add this class to ivs->list. */
5650 /* Put it in the array of biv register classes. */
5652 }
5653 else
5654 {
5655 /* Check if location is the same as a previous one. */
5659 {
5662 }
5663 }
5665 /* Update IV_CLASS entry for this biv. */
5674 }
5675 \f
5676 /* Fill in the data about one giv.
5677 V is the `struct induction' in which we record the giv. (It is
5678 allocated by the caller, with alloca.)
5679 INSN is the insn that sets it.
5680 BENEFIT estimates the savings from deleting this insn.
5681 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5682 into a register or is used as a memory address.
5684 SRC_REG is the biv reg which the giv is computed from.
5685 DEST_REG is the giv's reg (if the giv is stored in a reg).
5686 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5687 LOCATION points to the place where this giv's value appears in INSN. */
5689 static void
5694 {
5699 rtx temp;
5701 /* Attempt to prove constantness of the values. Don't let simplify_rtx
5702 undo the MULT canonicalization that we performed earlier. */
5732 /* The v->always_computable field is used in update_giv_derive, to
5733 determine whether a giv can be used to derive another giv. For a
5734 DEST_REG giv, INSN computes a new value for the giv, so its value
5735 isn't computable if INSN insn't executed every iteration.
5736 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5737 it does not compute a new value. Hence the value is always computable
5738 regardless of whether INSN is executed each iteration. */
5742 else
5748 {
5751 }
5753 {
5758 /* If the lifetime is zero, it means that this register is
5759 really a dead store. So mark this as a giv that can be
5760 ignored. This will not prevent the biv from being eliminated. */
5766 }
5768 /* Add the giv to the class of givs computed from one biv. */
5772 {
5775 /* Don't count DEST_ADDR. This is supposed to count the number of
5776 insns that calculate givs. */
5780 }
5781 else
5782 /* Fatal error, biv missing for this giv? */
5786 {
5789 }
5790 else
5791 {
5792 /* The giv can be replaced outright by the reduced register only if all
5793 of the following conditions are true:
5794 - the insn that sets the giv is always executed on any iteration
5795 on which the giv is used at all
5796 (there are two ways to deduce this:
5797 either the insn is executed on every iteration,
5798 or all uses follow that insn in the same basic block),
5799 - the giv is not used outside the loop
5800 - no assignments to the biv occur during the giv's lifetime. */
5803 /* Previous line always fails if INSN was moved by loop opt. */
5806 && (! not_every_iteration
5808 {
5809 /* Now check that there are no assignments to the biv within the
5810 giv's lifetime. This requires two separate checks. */
5812 /* Check each biv update, and fail if any are between the first
5813 and last use of the giv.
5815 If this loop contains an inner loop that was unrolled, then
5816 the insn modifying the biv may have been emitted by the loop
5817 unrolling code, and hence does not have a valid luid. Just
5818 mark the biv as not replaceable in this case. It is not very
5819 useful as a biv, because it is used in two different loops.
5820 It is very unlikely that we would be able to optimize the giv
5821 using this biv anyways. */
5826 {
5832 {
5836 }
5837 }
5839 /* If there are any backwards branches that go from after the
5840 biv update to before it, then this giv is not replaceable. */
5844 {
5848 }
5849 }
5850 else
5851 {
5852 /* May still be replaceable, we don't have enough info here to
5853 decide. */
5856 }
5857 }
5859 /* Record whether the add_val contains a const_int, for later use by
5860 combine_givs. */
5861 {
5866 ;
5870 {
5872 {
5877 else
5879 }
5882 }
5883 }
5887 }
5889 /* All this does is determine whether a giv can be made replaceable because
5890 its final value can be calculated. This code can not be part of record_giv
5891 above, because final_giv_value requires that the number of loop iterations
5892 be known, and that can not be accurately calculated until after all givs
5893 have been identified. */
5895 static void
5897 {
5900 /* DEST_ADDR givs will never reach here, because they are always marked
5901 replaceable above in record_giv. */
5903 /* The giv can be replaced outright by the reduced register only if all
5904 of the following conditions are true:
5905 - the insn that sets the giv is always executed on any iteration
5906 on which the giv is used at all
5907 (there are two ways to deduce this:
5908 either the insn is executed on every iteration,
5909 or all uses follow that insn in the same basic block),
5910 - its final value can be calculated (this condition is different
5911 than the one above in record_giv)
5912 - it's not used before the it's set
5913 - no assignments to the biv occur during the giv's lifetime. */
5915 #if 0
5916 /* This is only called now when replaceable is known to be false. */
5917 /* Clear replaceable, so that it won't confuse final_giv_value. */
5919 #endif
5924 {
5927 rtx last_giv_use;
5932 /* When trying to determine whether or not a biv increment occurs
5933 during the lifetime of the giv, we can ignore uses of the variable
5934 outside the loop because final_value is true. Hence we can not
5935 use regno_last_uid and regno_first_uid as above in record_giv. */
5937 /* Search the loop to determine whether any assignments to the
5938 biv occur during the giv's lifetime. Start with the insn
5939 that sets the giv, and search around the loop until we come
5940 back to that insn again.
5942 Also fail if there is a jump within the giv's lifetime that jumps
5943 to somewhere outside the lifetime but still within the loop. This
5944 catches spaghetti code where the execution order is not linear, and
5945 hence the above test fails. Here we assume that the giv lifetime
5946 does not extend from one iteration of the loop to the next, so as
5947 to make the test easier. Since the lifetime isn't known yet,
5948 this requires two loops. See also record_giv above. */
5953 {
5956 {
5959 }
5964 {
5965 /* It is possible for the BIV increment to use the GIV if we
5966 have a cycle. Thus we must be sure to check each insn for
5967 both BIV and GIV uses, and we must check for BIV uses
5968 first. */
5975 {
5977 {
5981 }
5983 }
5984 }
5985 }
5987 /* Now that the lifetime of the giv is known, check for branches
5988 from within the lifetime to outside the lifetime if it is still
5989 replaceable. */
5992 {
5995 {
6008 {
6017 }
6018 }
6019 }
6021 /* If it is replaceable, then save the final value. */
6024 }
6029 }
6030 \f
6031 /* Update the status of whether a giv can derive other givs.
6033 We need to do something special if there is or may be an update to the biv
6034 between the time the giv is defined and the time it is used to derive
6035 another giv.
6037 In addition, a giv that is only conditionally set is not allowed to
6038 derive another giv once a label has been passed.
6040 The cases we look at are when a label or an update to a biv is passed. */
6042 static void
6044 {
6048 rtx tem;
6051 /* Search all IV classes, then all bivs, and finally all givs.
6053 There are three cases we are concerned with. First we have the situation
6054 of a giv that is only updated conditionally. In that case, it may not
6055 derive any givs after a label is passed.
6057 The second case is when a biv update occurs, or may occur, after the
6058 definition of a giv. For certain biv updates (see below) that are
6059 known to occur between the giv definition and use, we can adjust the
6060 giv definition. For others, or when the biv update is conditional,
6061 we must prevent the giv from deriving any other givs. There are two
6062 sub-cases within this case.
6064 If this is a label, we are concerned with any biv update that is done
6065 conditionally, since it may be done after the giv is defined followed by
6066 a branch here (actually, we need to pass both a jump and a label, but
6067 this extra tracking doesn't seem worth it).
6069 If this is a jump, we are concerned about any biv update that may be
6070 executed multiple times. We are actually only concerned about
6071 backward jumps, but it is probably not worth performing the test
6072 on the jump again here.
6074 If this is a biv update, we must adjust the giv status to show that a
6075 subsequent biv update was performed. If this adjustment cannot be done,
6076 the giv cannot derive further givs. */
6082 {
6083 /* Skip if location is the same as a previous one. */
6088 {
6089 /* If cant_derive is already true, there is no point in
6090 checking all of these conditions again. */
6094 /* If this giv is conditionally set and we have passed a label,
6095 it cannot derive anything. */
6099 /* Skip givs that have mult_val == 0, since
6100 they are really invariants. Also skip those that are
6101 replaceable, since we know their lifetime doesn't contain
6102 any biv update. */
6106 /* The only way we can allow this giv to derive another
6107 is if this is a biv increment and we can form the product
6108 of biv->add_val and giv->mult_val. In this case, we will
6109 be able to compute a compensation. */
6111 {
6112 rtx ext_val_dummy;
6123 tem = simplify_giv_expr
6130 else
6132 }
6136 }
6137 }
6138 }
6139 \f
6140 /* Check whether an insn is an increment legitimate for a basic induction var.
6141 X is the source of insn P, or a part of it.
6142 MODE is the mode in which X should be interpreted.
6144 DEST_REG is the putative biv, also the destination of the insn.
6145 We accept patterns of these forms:
6146 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6147 REG = INVARIANT + REG
6149 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6150 store the additive term into *INC_VAL, and store the place where
6151 we found the additive term into *LOCATION.
6153 If X is an assignment of an invariant into DEST_REG, we set
6154 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6156 We also want to detect a BIV when it corresponds to a variable
6157 whose mode was promoted. In that case, an increment
6158 of the variable may be a PLUS that adds a SUBREG of that variable to
6159 an invariant and then sign- or zero-extends the result of the PLUS
6160 into the variable.
6162 Most GIVs in such cases will be in the promoted mode, since that is the
6163 probably the natural computation mode (and almost certainly the mode
6164 used for addresses) on the machine. So we view the pseudo-reg containing
6165 the variable as the BIV, as if it were simply incremented.
6167 Note that treating the entire pseudo as a BIV will result in making
6168 simple increments to any GIVs based on it. However, if the variable
6169 overflows in its declared mode but not its promoted mode, the result will
6170 be incorrect. This is acceptable if the variable is signed, since
6171 overflows in such cases are undefined, but not if it is unsigned, since
6172 those overflows are defined. So we only check for SIGN_EXTEND and
6173 not ZERO_EXTEND.
6175 If we cannot find a biv, we return 0. */
6177 static int
6181 {
6189 {
6195 {
6197 }
6202 {
6204 }
6205 else
6212 /* convert_modes can emit new instructions, e.g. when arg is a loop
6213 invariant MEM and dest_reg has a different mode.
6214 These instructions would be emitted after the end of the function
6215 and then *inc_val would be an uninitialized pseudo.
6216 Detect this and bail in this case.
6217 Other alternatives to solve this can be introducing a convert_modes
6218 variant which is allowed to fail but not allowed to emit new
6219 instructions, emit these instructions before loop start and let
6220 it be garbage collected if *inc_val is never used or saving the
6221 *inc_val initialization sequence generated here and when *inc_val
6222 is going to be actually used, emit it at some suitable place. */
6226 {
6229 }
6237 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6238 handle addition of promoted variables.
6239 ??? The comment at the start of this function is wrong: promoted
6240 variable increments don't look like it says they do. */
6246 /* If this register is assigned in a previous insn, look at its
6247 source, but don't go outside the loop or past a label. */
6249 /* If this sets a register to itself, we would repeat any previous
6250 biv increment if we applied this strategy blindly. */
6256 {
6257 rtx dest;
6258 do
6259 {
6261 }
6290 }
6291 /* Fall through. */
6293 /* Can accept constant setting of biv only when inside inner most loop.
6294 Otherwise, a biv of an inner loop may be incorrectly recognized
6295 as a biv of the outer loop,
6296 causing code to be moved INTO the inner loop. */
6303 /* convert_modes aborts if we try to convert to or from CCmode, so just
6304 exclude that case. It is very unlikely that a condition code value
6305 would be a useful iterator anyways. convert_modes aborts if we try to
6306 convert a float mode to non-float or vice versa too. */
6310 {
6311 /* Possible bug here? Perhaps we don't know the mode of X. */
6315 {
6318 }
6323 }
6324 else
6328 /* Ignore this BIV if signed arithmetic overflow is defined. */
6335 /* Similar, since this can be a sign extension. */
6340 ;
6354 location);
6359 }
6360 }
6361 \f
6362 /* A general induction variable (giv) is any quantity that is a linear
6363 function of a basic induction variable,
6364 i.e. giv = biv * mult_val + add_val.
6365 The coefficients can be any loop invariant quantity.
6366 A giv need not be computed directly from the biv;
6367 it can be computed by way of other givs. */
6369 /* Determine whether X computes a giv.
6370 If it does, return a nonzero value
6371 which is the benefit from eliminating the computation of X;
6372 set *SRC_REG to the register of the biv that it is computed from;
6373 set *ADD_VAL and *MULT_VAL to the coefficients,
6374 such that the value of X is biv * mult + add; */
6376 static int
6381 {
6385 /* If this is an invariant, forget it, it isn't a giv. */
6396 {
6399 /* Since this is now an invariant and wasn't before, it must be a giv
6400 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6401 with. */
6408 /* This is equivalent to a BIV. */
6415 /* Either (plus (biv) (invar)) or
6416 (plus (mult (biv) (invar_1)) (invar_2)). */
6418 {
6421 }
6422 else
6423 {
6426 }
6431 /* ADD_VAL is zero. */
6439 }
6441 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6442 unless they are CONST_INT). */
6450 else
6453 /* Always return true if this is a giv so it will be detected as such,
6454 even if the benefit is zero or negative. This allows elimination
6455 of bivs that might otherwise not be eliminated. */
6457 }
6458 \f
6459 /* Given an expression, X, try to form it as a linear function of a biv.
6460 We will canonicalize it to be of the form
6461 (plus (mult (BIV) (invar_1))
6462 (invar_2))
6463 with possible degeneracies.
6465 The invariant expressions must each be of a form that can be used as a
6466 machine operand. We surround then with a USE rtx (a hack, but localized
6467 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6468 routine; it is the caller's responsibility to strip them.
6470 If no such canonicalization is possible (i.e., two biv's are used or an
6471 expression that is neither invariant nor a biv or giv), this routine
6472 returns 0.
6474 For a nonzero return, the result will have a code of CONST_INT, USE,
6475 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6477 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6482 static rtx
6484 {
6489 rtx tem;
6491 /* If this is not an integer mode, or if we cannot do arithmetic in this
6492 mode, this can't be a giv. */
6499 {
6506 /* Put constant last, CONST_INT last if both constant. */
6514 /* Handle addition of zero, then addition of an invariant. */
6519 {
6522 /* Adding two invariants must result in an invariant, so enclose
6523 addition operation inside a USE and return it. */
6533 else
6542 /* biv + invar or mult + invar. Return sum. */
6546 /* (a + invar_1) + invar_2. Associate. */
6547 return
6553 arg1)),
6558 }
6560 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6561 MULT to reduce cases. */
6567 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6568 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6569 Recurse to associate the second PLUS. */
6574 return
6582 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6598 /* Handle "a - b" as "a + b * (-1)". */
6604 constm1_rtx)),
6613 /* Put constant last, CONST_INT last if both constant. */
6618 /* If second argument is not now constant, not giv. */
6622 /* Handle multiply by 0 or 1. */
6630 {
6632 /* biv * invar. Done. */
6636 /* Product of two constants. */
6640 /* invar * invar is a giv, but attempt to simplify it somehow. */
6646 {
6647 /* (invar_0 * invar_1) * invar_2. Associate. */
6654 arg1)),
6656 }
6657 /* Propagate the MULT expressions to the innermost nodes. */
6659 {
6660 /* (invar_0 + invar_1) * invar_2. Distribute. */
6666 arg1),
6670 arg1)),
6672 }
6676 /* (a * invar_1) * invar_2. Associate. */
6682 arg1)),
6686 /* (a + invar_1) * invar_2. Distribute. */
6691 arg1),
6694 arg1)),
6699 }
6702 /* Shift by constant is multiply by power of two. */
6706 return
6715 /* "-a" is "a * (-1)" */
6721 /* "~a" is "-a - 1". Silly, but easy. */
6725 const1_rtx),
6729 /* Already in proper form for invariant. */
6735 /* Conditionally recognize extensions of simple IVs. After we've
6736 computed loop traversal counts and verified the range of the
6737 source IV, we'll reevaluate this as a GIV. */
6739 {
6742 {
6745 }
6746 }
6750 /* If this is a new register, we can't deal with it. */
6754 /* Check for biv or giv. */
6756 {
6760 {
6763 /* Form expression from giv and add benefit. Ensure this giv
6764 can derive another and subtract any needed adjustment if so. */
6766 /* Increasing the benefit here is risky. The only case in which it
6767 is arguably correct is if this is the only use of V. In other
6768 cases, this will artificially inflate the benefit of the current
6769 giv, and lead to suboptimal code. Thus, it is disabled, since
6770 potentially not reducing an only marginally beneficial giv is
6771 less harmful than reducing many givs that are not really
6772 beneficial. */
6773 {
6777 }
6790 {
6793 }
6794 else
6795 {
6798 }
6800 }
6803 do_default:
6804 /* If it isn't an induction variable, and it is invariant, we
6805 may be able to simplify things further by looking through
6806 the bits we just moved outside the loop. */
6808 {
6814 {
6815 /* Ok, we found a match. Substitute and simplify. */
6817 /* If we match another movable, we must use that, as
6818 this one is going away. */
6823 /* If consec is nonzero, this is a member of a group of
6824 instructions that were moved together. We handle this
6825 case only to the point of seeking to the last insn and
6826 looking for a REG_EQUAL. Fail if we don't find one. */
6828 {
6831 do
6832 {
6834 }
6840 }
6841 else
6842 {
6846 }
6849 {
6850 /* What we are most interested in is pointer
6851 arithmetic on invariants -- only take
6852 patterns we may be able to do something with. */
6858 {
6860 benefit);
6863 }
6868 {
6873 }
6874 }
6876 }
6877 }
6879 }
6881 /* Fall through to general case. */
6883 /* If invariant, return as USE (unless CONST_INT).
6884 Otherwise, not giv. */
6889 {
6898 }
6899 else
6901 }
6902 }
6904 /* This routine folds invariants such that there is only ever one
6905 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6907 static rtx
6909 {
6915 {
6918 }
6921 {
6924 }
6925 else
6926 {
6929 }
6930 }
6932 static rtx
6934 {
6936 {
6940 else
6943 }
6946 else
6949 }
6950 \f
6951 /* Help detect a giv that is calculated by several consecutive insns;
6952 for example,
6953 giv = biv * M
6954 giv = giv + A
6955 The caller has already identified the first insn P as having a giv as dest;
6956 we check that all other insns that set the same register follow
6957 immediately after P, that they alter nothing else,
6958 and that the result of the last is still a giv.
6960 The value is 0 if the reg set in P is not really a giv.
6961 Otherwise, the value is the amount gained by eliminating
6962 all the consecutive insns that compute the value.
6964 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6965 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6967 The coefficients of the ultimate giv value are stored in
6968 *MULT_VAL and *ADD_VAL. */
6970 static int
6974 {
6980 rtx temp;
6981 rtx set;
6983 /* Indicate that this is a giv so that we can update the value produced in
6984 each insn of the multi-insn sequence.
6986 This induction structure will be used only by the call to
6987 general_induction_var below, so we can allocate it on our stack.
6988 If this is a giv, our caller will replace the induct var entry with
6989 a new induction structure. */
7010 {
7014 /* If libcall, skip to end of call sequence. */
7025 /* Giv created by equivalent expression. */
7031 {
7035 count--;
7039 }
7041 {
7042 /* Allow insns that set something other than this giv to a
7043 constant. Such insns are needed on machines which cannot
7044 include long constants and should not disqualify a giv. */
7053 }
7054 }
7059 }
7060 \f
7061 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7062 represented by G1. If no such expression can be found, or it is clear that
7063 it cannot possibly be a valid address, 0 is returned.
7065 To perform the computation, we note that
7066 G1 = x * v + a and
7067 G2 = y * v + b
7068 where `v' is the biv.
7070 So G2 = (y/b) * G1 + (b - a*y/x).
7072 Note that MULT = y/x.
7074 Update: A and B are now allowed to be additive expressions such that
7075 B contains all variables in A. That is, computing B-A will not require
7076 subtracting variables. */
7078 static rtx
7080 {
7081 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7086 /* If MULT is not 1, we cannot handle A with non-constants, since we
7087 would then be required to subtract multiples of the registers in A.
7088 This is theoretically possible, and may even apply to some Fortran
7089 constructs, but it is a lot of work and we do not attempt it here. */
7094 /* In general these structures are sorted top to bottom (down the PLUS
7095 chain), but not left to right across the PLUS. If B is a higher
7096 order giv than A, we can strip one level and recurse. If A is higher
7097 order, we'll eventually bail out, but won't know that until the end.
7098 If they are the same, we'll strip one level around this loop. */
7101 {
7113 /* We matched: remove one reg completely. */
7116 /* An alternate match. */
7119 /* An alternate match. */
7121 else
7122 {
7123 /* Indicates an extra register in B. Strip one level from B and
7124 recurse, hoping B was the higher order expression. */
7129 }
7130 }
7132 /* Here we are at the last level of A, go through the cases hoping to
7133 get rid of everything but a constant. */
7136 {
7149 }
7151 {
7153 }
7155 {
7160 }
7162 {
7167 else
7169 }
7174 }
7176 rtx
7178 {
7181 /* The value that G1 will be multiplied by must be a constant integer. Also,
7182 the only chance we have of getting a valid address is if b*c/a (see above
7183 for notation) is also an integer. */
7186 {
7194 }
7197 else
7198 {
7199 /* ??? Find out if the one is a multiple of the other? */
7201 }
7205 {
7206 /* Failed. If we've got a multiplication factor between G1 and G2,
7207 scale G1's addend and try again. */
7209 {
7213 {
7214 HOST_WIDE_INT m;
7218 }
7219 else
7220 {
7222 mult);
7223 }
7226 }
7227 }
7231 /* Form simplified final result. */
7236 else
7241 else
7242 {
7245 {
7249 }
7252 }
7253 }
7254 \f
7255 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7256 represented by G1. This indicates that G2 should be combined with G1 and
7257 that G2 can use (either directly or via an address expression) a register
7258 used to represent G1. */
7260 static rtx
7262 {
7265 /* With the introduction of ext dependent givs, we must care for modes.
7266 G2 must not use a wider mode than G1. */
7276 /* If these givs are identical, they can be combined. We use the results
7277 of express_from because the addends are not in a canonical form, so
7278 rtx_equal_p is a weaker test. */
7279 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7280 combination to be the other way round. */
7283 {
7285 }
7287 /* If G2 can be expressed as a function of G1 and that function is valid
7288 as an address and no more expensive than using a register for G2,
7289 the expression of G2 in terms of G1 can be used. */
7296 }
7297 \f
7298 /* Check each extension dependent giv in this class to see if its
7299 root biv is safe from wrapping in the interior mode, which would
7300 make the giv illegal. */
7302 static void
7304 {
7308 HOST_WIDE_INT start_val;
7314 /* Make sure the iteration data is available. We must have
7315 constants in order to be certain of no overflow. */
7321 /* Make sure the host can represent the arithmetic. */
7323 {
7325 HOST_WIDE_INT s_end_val;
7337 /* Check for host arithmetic overflow. */
7339 {
7341 HOST_WIDE_INT s_max;
7348 /* Check zero extension of biv ok. */
7350 /* Check for host arithmetic overflow. */
7351 && (neg_incr
7354 /* Check for target arithmetic overflow. */
7355 && (neg_incr
7358 {
7360 }
7362 /* Check sign extension of biv ok. */
7363 /* ??? While it is true that overflow with signed and pointer
7364 arithmetic is undefined, I fear too many programmers don't
7365 keep this fact in mind -- myself included on occasion.
7366 So leave alone with the signed overflow optimizations. */
7368 /* Check for host arithmetic overflow. */
7369 && (neg_incr
7372 /* Check for target arithmetic overflow. */
7373 && (neg_incr
7376 {
7378 }
7379 }
7380 }
7382 /* If we know the BIV is compared at run-time against an
7383 invariant value, and the increment is +/- 1, we may also
7384 be able to prove that the BIV cannot overflow. */
7390 {
7391 /* If the increment is +1, and the exit test is a <,
7392 the BIV cannot overflow. (For <=, we have the
7393 problematic case that the comparison value might
7394 be the maximum value of the range.) */
7396 {
7401 }
7403 /* Likewise for increment -1 and exit test >. */
7405 {
7410 }
7411 }
7413 /* Invalidate givs that fail the tests. */
7416 {
7421 {
7430 /* We don't know whether this value is being used as either
7431 signed or unsigned, so to safely truncate we must satisfy
7432 both. The initial check here verifies the BIV itself;
7433 once that is successful we may check its range wrt the
7434 derived GIV. This works only if we were able to determine
7435 constant start and end values above. */
7437 {
7441 /* We know from the above that both endpoints are nonnegative,
7442 and that there is no wrapping. Verify that both endpoints
7443 are within the (signed) range of the outer mode. */
7446 }
7451 }
7454 {
7456 {
7460 }
7461 }
7462 else
7463 {
7465 {
7470 else
7471 {
7476 else
7478 }
7483 }
7486 }
7487 }
7488 }
7490 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7492 rtx
7494 {
7500 /* Recall that check_ext_dependent_givs verified that the known bounds
7501 of a biv did not overflow or wrap with respect to the extension for
7502 the giv. Therefore, constants need no additional adjustment. */
7506 /* Otherwise, we must adjust the value to compensate for the
7507 differing modes of the biv and the giv. */
7509 }
7510 \f
7511 struct combine_givs_stats
7512 {
7515 };
7517 static int
7519 {
7526 /* Stabilize the sort. */
7530 }
7532 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7533 any other. If so, point SAME to the giv combined with and set NEW_REG to
7534 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7535 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7537 static void
7539 {
7540 /* Additional benefit to add for being combined multiple times. */
7548 /* Count givs, because bl->giv_count is incorrect here. */
7552 giv_count++;
7564 {
7566 rtx single_use;
7571 /* If a DEST_REG GIV is used only once, do not allow it to combine
7572 with anything, for in doing so we will gain nothing that cannot
7573 be had by simply letting the GIV with which we would have combined
7574 to be reduced on its own. The losage shows up in particular with
7575 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7576 be seen elsewhere as well. */
7583 /* Add an additional weight for zero addends. */
7588 {
7589 rtx this_combine;
7594 {
7597 }
7598 }
7600 }
7602 /* Iterate, combining until we can't. */
7603 restart:
7607 {
7610 {
7616 }
7618 }
7621 {
7627 /* If it has already been combined, skip. */
7632 {
7635 /* If it has already been combined, skip. */
7637 {
7642 /* For destination, we now may replace by mem expression instead
7643 of register. This changes the costs considerably, so add the
7644 compensation. */
7654 /* ??? The new final_[bg]iv_value code does a much better job
7655 of finding replaceable giv's, and hence this code may no
7656 longer be necessary. */
7660 /* To help optimize the next set of combinations, remove
7661 this giv from the benefits of other potential mates. */
7663 {
7667 }
7674 }
7675 }
7677 /* To help optimize the next set of combinations, remove
7678 this giv from the benefits of other potential mates. */
7680 {
7682 {
7686 }
7690 /* We've finished with this giv, and everything it touched.
7691 Restart the combination so that proper weights for the
7692 rest of the givs are properly taken into account. */
7693 /* ??? Ideally we would compact the arrays at this point, so
7694 as to not cover old ground. But sanely compacting
7695 can_combine is tricky. */
7697 }
7698 }
7700 /* Clean up. */
7703 }
7704 \f
7705 /* Generate sequence for REG = B * M + A. B is the initial value of
7706 the basic induction variable, M a multiplicative constant, A an
7707 additive constant and REG the destination register. */
7709 static rtx
7711 {
7712 rtx seq;
7713 rtx result;
7716 /* Use unsigned arithmetic. */
7724 }
7727 /* Update registers created in insn sequence SEQ. */
7729 static void
7731 {
7732 rtx insn;
7734 /* Update register info for alias analysis. */
7738 {
7745 }
7746 }
7749 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. B
7750 is the initial value of the basic induction variable, M a
7751 multiplicative constant, A an additive constant and REG the
7752 destination register. */
7754 void
7757 {
7758 rtx seq;
7761 {
7764 }
7766 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7769 /* Increase the lifetime of any invariants moved further in code. */
7774 /* It is possible that the expansion created lots of new registers.
7775 Iterate over the sequence we just created and record them all. We
7776 must do this before inserting the sequence. */
7780 }
7783 /* Emit insns in loop pre-header to set REG = B * M + A. B is the
7784 initial value of the basic induction variable, M a multiplicative
7785 constant, A an additive constant and REG the destination
7786 register. */
7788 void
7790 {
7791 rtx seq;
7793 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7796 /* Increase the lifetime of any invariants moved further in code.
7797 ???? Is this really necessary? */
7802 /* It is possible that the expansion created lots of new registers.
7803 Iterate over the sequence we just created and record them all. We
7804 must do this before inserting the sequence. */
7808 }
7811 /* Emit insns after loop to set REG = B * M + A. B is the initial
7812 value of the basic induction variable, M a multiplicative constant,
7813 A an additive constant and REG the destination register. */
7815 void
7817 {
7818 rtx seq;
7820 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7823 /* It is possible that the expansion created lots of new registers.
7824 Iterate over the sequence we just created and record them all. We
7825 must do this before inserting the sequence. */
7829 }
7833 /* Similar to gen_add_mult, but compute cost rather than generating
7834 sequence. */
7836 static int
7838 {
7848 {
7853 }
7856 }
7857 \f
7858 /* Test whether A * B can be computed without
7859 an actual multiply insn. Value is 1 if so.
7861 ??? This function stinks because it generates a ton of wasted RTL
7862 ??? and as a result fragments GC memory to no end. There are other
7863 ??? places in the compiler which are invoked a lot and do the same
7864 ??? thing, generate wasted RTL just to see if something is possible. */
7866 static int
7868 {
7869 rtx tmp;
7872 /* If only one is constant, make it B. */
7876 /* If first constant, both constant, so don't need multiply. */
7880 /* If second not constant, neither is constant, so would need multiply. */
7884 /* One operand is constant, so might not need multiply insn. Generate the
7885 code for the multiply and see if a call or multiply, or long sequence
7886 of insns is generated. */
7895 {
7898 {
7908 {
7911 }
7914 }
7915 }
7925 }
7926 \f
7927 /* Check to see if loop can be terminated by a "decrement and branch until
7928 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7929 Also try reversing an increment loop to a decrement loop
7930 to see if the optimization can be performed.
7931 Value is nonzero if optimization was performed. */
7933 /* This is useful even if the architecture doesn't have such an insn,
7934 because it might change a loops which increments from 0 to n to a loop
7935 which decrements from n to 0. A loop that decrements to zero is usually
7936 faster than one that increments from zero. */
7938 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7939 such as approx_final_value, biv_total_increment, loop_iterations, and
7940 final_[bg]iv_value. */
7942 static int
7944 {
7949 rtx reg;
7951 rtx jump_label;
7952 rtx final_value;
7953 rtx start_value;
7954 rtx new_add_val;
7955 rtx comparison;
7956 rtx before_comparison;
7957 rtx p;
7958 rtx jump;
7959 rtx first_compare;
7964 /* If last insn is a conditional branch, and the insn before tests a
7965 register value, try to optimize it. Otherwise, we can't do anything. */
7974 /* Try to compute whether the compare/branch at the loop end is one or
7975 two instructions. */
7981 else
7984 {
7985 /* If more than one condition is present to control the loop, then
7986 do not proceed, as this function does not know how to rewrite
7987 loop tests with more than one condition.
7989 Look backwards from the first insn in the last comparison
7990 sequence and see if we've got another comparison sequence. */
7992 rtx jump1;
7996 }
7998 /* Check all of the bivs to see if the compare uses one of them.
7999 Skip biv's set more than once because we can't guarantee that
8000 it will be zero on the last iteration. Also skip if the biv is
8001 used between its update and the test insn. */
8004 {
8009 first_compare))
8011 }
8013 /* Try swapping the comparison to identify a suitable biv. */
8020 first_compare))
8021 {
8023 VOIDmode,
8027 }
8032 /* Look for the case where the basic induction variable is always
8033 nonnegative, and equals zero on the last iteration.
8034 In this case, add a reg_note REG_NONNEG, which allows the
8035 m68k DBRA instruction to be used. */
8041 {
8042 /* Initial value must be greater than 0,
8043 init_val % -dec_value == 0 to ensure that it equals zero on
8044 the last iteration */
8050 {
8051 /* Register always nonnegative, add REG_NOTE to branch. */
8059 }
8061 /* If the decrement is 1 and the value was tested as >= 0 before
8062 the loop, then we can safely optimize. */
8064 {
8078 {
8086 }
8087 }
8088 }
8091 {
8092 /* Try to change inc to dec, so can apply above optimization. */
8093 /* Can do this if:
8094 all registers modified are induction variables or invariant,
8095 all memory references have non-overlapping addresses
8096 (obviously true if only one write)
8097 allow 2 insns for the compare/jump at the end of the loop. */
8098 /* Also, we must avoid any instructions which use both the reversed
8099 biv and another biv. Such instructions will fail if the loop is
8100 reversed. We meet this condition by requiring that either
8101 no_use_except_counting is true, or else that there is only
8102 one biv. */
8104 /* 1 if the iteration var is used only to count iterations. */
8106 /* 1 if the loop has no memory store, or it has a single memory store
8107 which is reversible. */
8113 {
8117 /* If there are no givs for this biv, and the only exit is the
8118 fall through at the end of the loop, then
8119 see if perhaps there are no uses except to count. */
8123 {
8128 /* An insn that sets the biv is okay. */
8129 ;
8131 /* An insn that doesn't mention the biv is okay. */
8132 ;
8135 {
8136 /* If either of these insns uses the biv and sets a pseudo
8137 that has more than one usage, then the biv has uses
8138 other than counting since it's used to derive a value
8139 that is used more than one time. */
8141 regs);
8143 {
8146 }
8147 }
8148 else
8149 {
8152 }
8153 }
8155 /* A biv has uses besides counting if it is used to set
8156 another biv. */
8160 {
8163 }
8164 }
8167 /* No need to worry about MEMs. */
8168 ;
8170 {
8175 /* If the loop has a single store, and the destination address is
8176 invariant, then we can't reverse the loop, because this address
8177 might then have the wrong value at loop exit.
8178 This would work if the source was invariant also, however, in that
8179 case, the insn should have been moved out of the loop. */
8182 {
8185 /* If we could prove that each of the memory locations
8186 written to was different, then we could reverse the
8187 store -- but we don't presently have any way of
8188 knowing that. */
8191 /* If the store depends on a register that is set after the
8192 store, it depends on the initial value, and is thus not
8193 reversible. */
8195 {
8202 }
8203 }
8204 }
8205 else
8208 /* This code only acts for innermost loops. Also it simplifies
8209 the memory address check by only reversing loops with
8210 zero or one memory access.
8211 Two memory accesses could involve parts of the same array,
8212 and that can't be reversed.
8213 If the biv is used only for counting, than we don't need to worry
8214 about all these things. */
8220 && reversible_mem_store
8225 {
8226 rtx tem;
8228 /* Loop can be reversed. */
8232 /* Now check other conditions:
8234 The increment must be a constant, as must the initial value,
8235 and the comparison code must be LT.
8237 This test can probably be improved since +/- 1 in the constant
8238 can be obtained by changing LT to LE and vice versa; this is
8239 confusing. */
8242 /* for constants, LE gets turned into LT */
8247 {
8259 comparison_const_width
8261 else
8262 comparison_const_width
8266 comparison_sign_mask
8269 /* If the comparison value is not a loop invariant, then we
8270 can not reverse this loop.
8272 ??? If the insns which initialize the comparison value as
8273 a whole compute an invariant result, then we could move
8274 them out of the loop and proceed with loop reversal. */
8282 /* Normalize the initial value if it is an integer and
8283 has no other use except as a counter. This will allow
8284 a few more loops to be reversed. */
8288 {
8290 /* The code below requires comparison_val to be a multiple
8291 of add_val in order to do the loop reversal, so
8292 round up comparison_val to a multiple of add_val.
8293 Since comparison_value is constant, we know that the
8294 current comparison code is LT. */
8296 comparison_val
8298 /* We postpone overflow checks for COMPARISON_VAL here;
8299 even if there is an overflow, we might still be able to
8300 reverse the loop, if converting the loop exit test to
8301 NE is possible. */
8303 }
8305 /* First check if we can do a vanilla loop reversal. */
8307 /* If we have a decrement_and_branch_on_count,
8308 prefer the NE test, since this will allow that
8309 instruction to be generated. Note that we must
8310 use a vanilla loop reversal if the biv is used to
8311 calculate a giv or has a non-counting use. */
8312 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8313 && defined (HAVE_decrement_and_branch_on_count)
8317 #endif
8319 /* Now do postponed overflow checks on COMPARISON_VAL. */
8322 {
8323 /* Register will always be nonnegative, with value
8324 0 on last iteration */
8328 }
8332 {
8335 }
8336 else
8342 /* If the initial value is not zero, or if the comparison
8343 value is not an exact multiple of the increment, then we
8344 can not reverse this loop. */
8347 {
8350 }
8351 else
8352 {
8355 }
8359 /* Reset these in case we normalized the initial value
8360 and comparison value above. */
8363 {
8365 final_value
8367 }
8370 /* Save some info needed to produce the new insns. */
8376 /* Set start_value; if this is not a CONST_INT, we need
8377 to generate a SUB.
8378 Initialize biv to start_value before loop start.
8379 The old initializing insn will be deleted as a
8380 dead store by flow.c. */
8383 {
8384 start_value
8387 }
8389 {
8396 start_value
8402 }
8404 {
8406 initial_value);
8410 start_value
8413 }
8414 else
8415 /* We could handle the other cases too, but it'll be
8416 better to have a testcase first. */
8419 /* We may not have a single insn which can increment a reg, so
8420 create a sequence to hold all the insns from expand_inc. */
8429 /* Update biv info to reflect its new status. */
8434 /* Update loop info. */
8443 /* Inc LABEL_NUSES so that delete_insn will
8444 not delete the label. */
8447 /* If we have a separate comparison insn that does more
8448 than just set cc0, the result of the comparison might
8449 be used outside the loop. */
8451 #ifdef HAVE_CC0
8453 #endif
8454 );
8456 /* Emit an insn after the end of the loop to set the biv's
8457 proper exit value if it is used anywhere outside the loop. */
8467 /* Delete compare/branch at end of loop. */
8472 /* Add new compare/branch insn at end of loop. */
8484 ;
8490 {
8492 {
8493 /* Increment of LABEL_NUSES done above. */
8494 /* Register is now always nonnegative,
8495 so add REG_NONNEG note to the branch. */
8498 }
8500 }
8502 /* No insn may reference both the reversed and another biv or it
8503 will fail (see comment near the top of the loop reversal
8504 code).
8505 Earlier on, we have verified that the biv has no use except
8506 counting, or it is the only biv in this function.
8507 However, the code that computes no_use_except_counting does
8508 not verify reg notes. It's possible to have an insn that
8509 references another biv, and has a REG_EQUAL note with an
8510 expression based on the reversed biv. To avoid this case,
8511 remove all REG_EQUAL notes based on the reversed biv
8512 here. */
8515 {
8518 /* If this is a set of a GIV based on the reversed biv, any
8519 REG_EQUAL notes should still be correct. */
8526 {
8531 else
8533 }
8534 }
8536 /* Mark that this biv has been reversed. Each giv which depends
8537 on this biv, and which is also live past the end of the loop
8538 will have to be fixed up. */
8543 {
8547 else
8549 }
8552 }
8553 }
8554 }
8557 }
8558 \f
8559 /* Verify whether the biv BL appears to be eliminable,
8560 based on the insns in the loop that refer to it.
8562 If ELIMINATE_P is nonzero, actually do the elimination.
8564 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8565 determine whether invariant insns should be placed inside or at the
8566 start of the loop. */
8568 static int
8571 {
8574 rtx p;
8576 /* Scan all insns in the loop, stopping if we find one that uses the
8577 biv in a way that we cannot eliminate. */
8580 {
8584 rtx note;
8586 /* If this is a libcall that sets a giv, skip ahead to its end. */
8588 {
8592 {
8597 {
8604 }
8605 }
8606 }
8608 /* Closely examine the insn if the biv is mentioned. */
8613 {
8619 }
8621 /* If we are eliminating, kill REG_EQUAL notes mentioning the biv. */
8626 }
8629 {
8634 }
8637 }
8638 \f
8639 /* INSN and REFERENCE are instructions in the same insn chain.
8640 Return nonzero if INSN is first. */
8642 int
8644 {
8648 {
8649 /* Start with test for not first so that INSN == REFERENCE yields not
8650 first. */
8656 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8657 previous insn, hence the <= comparison below does not work if
8658 P is a note. */
8669 }
8670 }
8672 /* We are trying to eliminate BIV in INSN using GIV. Return nonzero if
8673 the offset that we have to take into account due to auto-increment /
8674 div derivation is zero. */
8675 static int
8678 {
8679 /* If the giv V had the auto-inc address optimization applied
8680 to it, and INSN occurs between the giv insn and the biv
8681 insn, then we'd have to adjust the value used here.
8682 This is rare, so we don't bother to make this possible. */
8691 }
8693 /* If BL appears in X (part of the pattern of INSN), see if we can
8694 eliminate its use. If so, return 1. If not, return 0.
8696 If BIV does not appear in X, return 1.
8698 If ELIMINATE_P is nonzero, actually do the elimination.
8699 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8700 Depending on how many items have been moved out of the loop, it
8701 will either be before INSN (when WHERE_INSN is nonzero) or at the
8702 start of the loop (when WHERE_INSN is zero). */
8704 static int
8708 {
8714 #ifdef HAVE_cc0
8716 #endif
8722 {
8724 /* If we haven't already been able to do something with this BIV,
8725 we can't eliminate it. */
8731 /* If this sets the BIV, it is not a problem. */
8735 /* If this is an insn that defines a giv, it is also ok because
8736 it will go away when the giv is reduced. */
8741 #ifdef HAVE_cc0
8743 {
8744 /* Can replace with any giv that was reduced and
8745 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8746 Require a constant for MULT_VAL, so we know it's nonzero.
8747 ??? We disable this optimization to avoid potential
8748 overflows. */
8756 {
8763 /* If the giv has the opposite direction of change,
8764 then reverse the comparison. */
8768 else
8771 /* We can probably test that giv's reduced reg. */
8774 }
8776 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8777 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8778 Require a constant for MULT_VAL, so we know it's nonzero.
8779 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8780 overflow problem. */
8792 {
8799 /* If the giv has the opposite direction of change,
8800 then reverse the comparison. */
8804 else
8808 /* Replace biv with the giv's reduced register. */
8813 /* Insn doesn't support that constant or invariant. Copy it
8814 into a register (it will be a loop invariant.) */
8821 /* Substitute the new register for its invariant value in
8822 the compare expression. */
8826 }
8827 }
8828 #endif
8835 /* See if either argument is the biv. */
8840 else
8844 {
8845 /* First try to replace with any giv that has constant positive
8846 mult_val and constant add_val. We might be able to support
8847 negative mult_val, but it seems complex to do it in general. */
8859 {
8863 /* Don't eliminate if the linear combination that makes up
8864 the giv overflows when it is applied to ARG. */
8866 {
8867 rtx add_val;
8871 else
8877 }
8882 /* Replace biv with the giv's reduced reg. */
8885 /* If all constants are actually constant integers and
8886 the derived constant can be directly placed in the COMPARE,
8887 do so. */
8890 {
8893 }
8894 else
8895 {
8896 /* Otherwise, load it into a register. */
8901 }
8907 }
8909 /* Look for giv with positive constant mult_val and nonconst add_val.
8910 Insert insns to calculate new compare value.
8911 ??? Turn this off due to possible overflow. */
8919 {
8920 rtx tem;
8930 /* Replace biv with giv's reduced register. */
8934 /* Compute value to compare against. */
8938 /* Use it in this insn. */
8942 }
8943 }
8945 {
8947 {
8948 /* Look for giv with constant positive mult_val and nonconst
8949 add_val. Insert insns to compute new compare value.
8950 ??? Turn this off due to possible overflow. */
8957 {
8958 rtx tem;
8968 /* Replace biv with giv's reduced register. */
8972 /* Compute value to compare against. */
8979 }
8980 }
8982 /* This code has problems. Basically, you can't know when
8983 seeing if we will eliminate BL, whether a particular giv
8984 of ARG will be reduced. If it isn't going to be reduced,
8985 we can't eliminate BL. We can try forcing it to be reduced,
8986 but that can generate poor code.
8988 The problem is that the benefit of reducing TV, below should
8989 be increased if BL can actually be eliminated, but this means
8990 we might have to do a topological sort of the order in which
8991 we try to process biv. It doesn't seem worthwhile to do
8992 this sort of thing now. */
8994 #if 0
8995 /* Otherwise the reg compared with had better be a biv. */
9000 /* Look for a pair of givs, one for each biv,
9001 with identical coefficients. */
9003 {
9015 {
9022 /* Replace biv with its giv's reduced reg. */
9024 /* Replace other operand with the other giv's
9025 reduced reg. */
9028 }
9029 }
9030 #endif
9031 }
9033 /* If we get here, the biv can't be eliminated. */
9037 /* If this address is a DEST_ADDR giv, it doesn't matter if the
9038 biv is used in it, since it will be replaced. */
9046 }
9048 /* See if any subexpression fails elimination. */
9051 {
9053 {
9066 }
9067 }
9070 }
9071 \f
9072 /* Return nonzero if the last use of REG
9073 is in an insn following INSN in the same basic block. */
9075 static int
9077 {
9078 rtx n;
9082 {
9085 }
9087 }
9088 \f
9089 /* Called via `note_stores' to record the initial value of a biv. Here we
9090 just record the location of the set and process it later. */
9092 static void
9094 {
9105 /* If this is the first set found, record it. */
9107 {
9110 }
9111 }
9112 \f
9113 /* If any of the registers in X are "old" and currently have a last use earlier
9114 than INSN, update them to have a last use of INSN. Their actual last use
9115 will be the previous insn but it will not have a valid uid_luid so we can't
9116 use it. X must be a source expression only. */
9118 static void
9120 {
9121 /* Check for the case where INSN does not have a valid luid. In this case,
9122 there is no need to modify the regno_last_uid, as this can only happen
9123 when code is inserted after the loop_end to set a pseudo's final value,
9124 and hence this insn will never be the last use of x.
9125 ???? This comment is not correct. See for example loop_givs_reduce.
9126 This may insert an insn before another new insn. */
9130 {
9132 }
9133 else
9134 {
9138 {
9144 }
9145 }
9146 }
9147 \f
9148 /* Given an insn INSN and condition COND, return the condition in a
9149 canonical form to simplify testing by callers. Specifically:
9151 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9152 (2) Both operands will be machine operands; (cc0) will have been replaced.
9153 (3) If an operand is a constant, it will be the second operand.
9154 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9155 for GE, GEU, and LEU.
9157 If the condition cannot be understood, or is an inequality floating-point
9158 comparison which needs to be reversed, 0 will be returned.
9160 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
9162 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9163 insn used in locating the condition was found. If a replacement test
9164 of the condition is desired, it should be placed in front of that
9165 insn and we will be sure that the inputs are still valid.
9167 If WANT_REG is nonzero, we wish the condition to be relative to that
9168 register, if possible. Therefore, do not canonicalize the condition
9169 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
9170 to be a compare to a CC mode register.
9172 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST
9173 and at INSN. */
9175 rtx
9178 {
9181 rtx set;
9182 rtx tem;
9200 /* If we are comparing a register with zero, see if the register is set
9201 in the previous insn to a COMPARE or a comparison operation. Perform
9202 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9203 in cse.c */
9209 {
9210 /* Set nonzero when we find something of interest. */
9213 #ifdef HAVE_cc0
9214 /* If comparison with cc0, import actual comparison from compare
9215 insn. */
9217 {
9228 }
9229 #endif
9231 /* If this is a COMPARE, pick up the two things being compared. */
9233 {
9237 }
9241 /* Go back to the previous insn. Stop if it is not an INSN. We also
9242 stop if it isn't a single set or if it has a REG_INC note because
9243 we don't want to bother dealing with it. */
9257 /* If this is setting OP0, get what it sets it to if it looks
9258 relevant. */
9260 {
9262 #ifdef FLOAT_STORE_FLAG_VALUE
9263 REAL_VALUE_TYPE fsfv;
9264 #endif
9266 /* ??? We may not combine comparisons done in a CCmode with
9267 comparisons not done in a CCmode. This is to aid targets
9268 like Alpha that have an IEEE compliant EQ instruction, and
9269 a non-IEEE compliant BEQ instruction. The use of CCmode is
9270 actually artificial, simply to prevent the combination, but
9271 should not affect other platforms.
9273 However, we must allow VOIDmode comparisons to match either
9274 CCmode or non-CCmode comparison, because some ports have
9275 modeless comparisons inside branch patterns.
9277 ??? This mode check should perhaps look more like the mode check
9278 in simplify_comparison in combine. */
9286 && (STORE_FLAG_VALUE
9289 #ifdef FLOAT_STORE_FLAG_VALUE
9294 #endif
9295 ))
9306 && (STORE_FLAG_VALUE
9309 #ifdef FLOAT_STORE_FLAG_VALUE
9314 #endif
9315 ))
9321 {
9324 }
9325 else
9327 }
9330 /* If this sets OP0, but not directly, we have to give up. */
9334 {
9335 /* If the caller is expecting the condition to be valid at INSN,
9336 make sure X doesn't change before INSN. */
9343 {
9348 }
9353 }
9354 }
9356 /* If constant is first, put it last. */
9360 /* If OP0 is the result of a comparison, we weren't able to find what
9361 was really being compared, so fail. */
9366 /* Canonicalize any ordered comparison with integers involving equality
9367 if we can do computations in the relevant mode and we do not
9368 overflow. */
9374 {
9377 unsigned HOST_WIDE_INT max_val
9381 {
9387 /* When cross-compiling, const_val might be sign-extended from
9388 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9408 }
9409 }
9411 /* Never return CC0; return zero instead. */
9416 }
9418 /* Given a jump insn JUMP, return the condition that will cause it to branch
9419 to its JUMP_LABEL. If the condition cannot be understood, or is an
9420 inequality floating-point comparison which needs to be reversed, 0 will
9421 be returned.
9423 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9424 insn used in locating the condition was found. If a replacement test
9425 of the condition is desired, it should be placed in front of that
9426 insn and we will be sure that the inputs are still valid. If EARLIEST
9427 is null, the returned condition will be valid at INSN.
9429 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
9430 compare CC mode register.
9432 VALID_AT_INSN_P is the same as for canonicalize_condition. */
9434 rtx
9436 {
9437 rtx cond;
9439 rtx set;
9441 /* If this is not a standard conditional jump, we can't parse it. */
9449 /* If this branches to JUMP_LABEL when the condition is false, reverse
9450 the condition. */
9451 reverse
9457 }
9459 /* Similar to above routine, except that we also put an invariant last
9460 unless both operands are invariants. */
9462 rtx
9464 {
9474 }
9476 /* Scan the function and determine whether it has indirect (computed) jumps.
9478 This is taken mostly from flow.c; similar code exists elsewhere
9479 in the compiler. It may be useful to put this into rtlanal.c. */
9480 static int
9482 {
9483 rtx insn;
9490 }
9492 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9493 documentation for LOOP_MEMS for the definition of `appropriate'.
9494 This function is called from prescan_loop via for_each_rtx. */
9496 static int
9498 {
9507 {
9512 /* We're not interested in MEMs that are only clobbered. */
9516 /* We're not interested in the MEM associated with a
9517 CONST_DOUBLE, so there's no need to traverse into this. */
9521 /* We're not interested in any MEMs that only appear in notes. */
9525 /* This is not a MEM. */
9527 }
9529 /* See if we've already seen this MEM. */
9532 {
9536 /* The modes of the two memory accesses are different. If
9537 this happens, something tricky is going on, and we just
9538 don't optimize accesses to this MEM. */
9542 }
9544 /* Resize the array, if necessary. */
9546 {
9549 else
9554 }
9556 /* Actually insert the MEM. */
9558 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9559 because we can't put it in a register. We still store it in the
9560 table, though, so that if we see the same address later, but in a
9561 non-BLK mode, we'll not think we can optimize it at that point. */
9567 }
9570 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9572 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9573 register that is modified by an insn between FROM and TO. If the
9574 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9575 more, stop incrementing it, to avoid overflow.
9577 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9578 register I is used, if it is only used once. Otherwise, it is set
9579 to 0 (for no uses) or const0_rtx for more than one use. This
9580 parameter may be zero, in which case this processing is not done.
9582 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9583 optimize register I. */
9585 static void
9587 {
9590 /* last_set[n] is nonzero iff reg n has been set in the current
9591 basic block. In that case, it is the insn that last set reg n. */
9593 rtx insn;
9599 /* Grow the regs array if not allocated or too small. */
9601 {
9606 /* Zero the new elements. */
9609 }
9611 /* Clear previously scanned fields but do not clear n_times_set. */
9613 {
9617 }
9621 /* Scan the loop, recording register usage. */
9624 {
9626 {
9627 /* Record registers that have exactly one use. */
9630 /* Include uses in REG_EQUAL notes. */
9638 {
9642 last_set);
9643 }
9644 }
9649 /* Invalidate all registers used for function argument passing.
9650 We check rtx_varies_p for the same reason as below, to allow
9651 optimizing PIC calculations. */
9653 {
9654 rtx link;
9656 link;
9658 {
9665 }
9666 }
9667 }
9669 /* Invalidate all hard registers clobbered by calls. With one exception:
9670 a call-clobbered PIC register is still function-invariant for our
9671 purposes, since we can hoist any PIC calculations out of the loop.
9672 Thus the call to rtx_varies_p. */
9677 {
9680 }
9682 #ifdef AVOID_CCMODE_COPIES
9683 /* Don't try to move insns which set CC registers if we should not
9684 create CCmode register copies. */
9688 #endif
9690 /* Set regs->array[I].n_times_set for the new registers. */
9695 }
9697 /* Returns the number of real INSNs in the LOOP. */
9699 static int
9701 {
9703 rtx insn;
9711 }
9713 /* Move MEMs into registers for the duration of the loop. */
9715 static void
9717 {
9724 rtx end_label;
9725 /* Nonzero if the next instruction may never be executed. */
9732 /* We cannot use next_label here because it skips over normal insns. */
9737 /* Check to see if it's possible that some instructions in the loop are
9738 never executed. Also check if there is a goto out of the loop other
9739 than right after the end of the loop. */
9743 {
9747 /* If we enter the loop in the middle, and scan
9748 around to the beginning, don't set maybe_never
9749 for that. This must be an unconditional jump,
9750 otherwise the code at the top of the loop might
9751 never be executed. Unconditional jumps are
9752 followed a by barrier then loop end. */
9757 {
9758 /* If this is a jump outside of the loop but not right
9759 after the end of the loop, we would have to emit new fixup
9760 sequences for each such label. */
9762 JUMP_INSN is executed, we must be conservative. */
9771 /* Something complicated. */
9773 else
9774 /* If there are any more instructions in the loop, they
9775 might not be reached. */
9777 }
9780 }
9782 /* Find start of the extended basic block that enters the loop. */
9786 ;
9791 /* Build table of mems that get set to constant values before the
9792 loop. */
9796 /* Actually move the MEMs. */
9798 {
9799 regset_head load_copies;
9800 regset_head store_copies;
9802 rtx reg;
9804 rtx mem_list_entry;
9808 /* There's no telling whether or not MEM is modified. */
9811 /* Go through the MEMs written to in the loop to see if this
9812 one is aliased by one of them. */
9815 {
9820 {
9821 /* MEM is indeed aliased by this store. */
9824 }
9826 }
9832 /* If this MEM is written to, we must be sure that there
9833 are no reads from another MEM that aliases this one. */
9835 {
9839 {
9843 VOIDmode,
9845 rtx_varies_p))
9846 {
9847 /* It's not safe to hoist loop_info->mems[i] out of
9848 the loop because writes to it might not be
9849 seen by reads from loop_info->mems[j]. */
9852 }
9853 }
9854 }
9857 /* We can't access the MEM outside the loop; it might
9858 cause a trap that wouldn't have happened otherwise. */
9862 /* We thought we were going to lift this MEM out of the
9863 loop, but later discovered that we could not. */
9869 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9870 order to keep scan_loop from moving stores to this MEM
9871 out of the loop just because this REG is neither a
9872 user-variable nor used in the loop test. */
9877 /* Now, replace all references to the MEM with the
9878 corresponding pseudos. */
9883 {
9885 {
9886 rtx set;
9890 /* See if this copies the mem into a register that isn't
9891 modified afterwards. We'll try to do copy propagation
9892 a little further on. */
9894 /* @@@ This test is _way_ too conservative. */
9895 && ! maybe_never
9903 /* See if this copies the mem from a register that isn't
9904 modified afterwards. We'll try to remove the
9905 redundant copy later on by doing a little register
9906 renaming and copy propagation. This will help
9907 to untangle things for the BIV detection code. */
9909 && ! maybe_never
9917 /* If this is a call which uses / clobbers this memory
9918 location, we must not change the interface here. */
9922 {
9926 }
9927 else
9928 /* Replace the memory reference with the shadow register. */
9931 }
9936 }
9941 /* We couldn't replace all occurrences of the MEM. */
9943 else
9944 {
9945 /* Load the memory immediately before LOOP->START, which is
9946 the NOTE_LOOP_BEG. */
9948 rtx set;
9954 {
9958 {
9962 /* Extending hard register lifetimes causes crash
9963 on SRC targets. Doing so on non-SRC is
9964 probably also not good idea, since we most
9965 probably have pseudoregister equivalence as
9966 well. */
9969 }
9970 /* Use the constant equivalence if that is cheap enough. */
9976 {
9979 }
9981 /* If best_equiv is nonzero, we know that MEM is set to a
9982 constant or register before the loop. We will use this
9983 knowledge to initialize the shadow register with that
9984 constant or reg rather than by loading from MEM. */
9987 }
9992 {
9995 {
9998 }
9999 }
10005 {
10007 {
10010 }
10012 /* Store the memory immediately after END, which is
10013 the NOTE_LOOP_END. */
10016 }
10019 {
10024 }
10026 /* Attempt a bit of copy propagation. This helps untangle the
10027 data flow, and enables {basic,general}_induction_var to find
10028 more bivs/givs. */
10029 EXECUTE_IF_SET_IN_REG_SET
10031 {
10033 });
10036 EXECUTE_IF_SET_IN_REG_SET
10038 {
10040 });
10042 }
10043 }
10045 /* Now, we need to replace all references to the previous exit
10046 label with the new one. */
10053 }
10055 /* For communication between note_reg_stored and its caller. */
10056 struct note_reg_stored_arg
10057 {
10059 rtx reg;
10060 };
10062 /* Called via note_stores, record in SET_SEEN whether X, which is written,
10063 is equal to ARG. */
10064 static void
10066 {
10070 }
10072 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10073 There must be exactly one insn that sets this pseudo; it will be
10074 deleted if all replacements succeed and we can prove that the register
10075 is not used after the loop. */
10077 static void
10079 {
10080 /* This is the reg that we are copying from. */
10083 rtx insn;
10084 /* These help keep track of whether we replaced all uses of the reg. */
10091 {
10092 rtx set;
10094 /* Only substitute within one extended basic block from the initializing
10095 insn. */
10102 /* Is this the initializing insn? */
10107 {
10114 }
10116 /* Only substitute after seeing the initializing insn. */
10118 {
10125 /* Stop replacing when REPLACEMENT is modified. */
10130 {
10133 /* It is possible that we've turned previously valid REG_EQUAL to
10134 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10135 REPLACEMENT is modified, we get different meaning. */
10139 }
10140 }
10141 }
10145 {
10149 {
10150 rtx first;
10151 rtx retval_note;
10153 /* Assume we're just deleting INIT_INSN. */
10155 /* Look for REG_RETVAL note. If we're deleting the end of
10156 the libcall sequence, the whole sequence can go. */
10158 /* If we found a REG_RETVAL note, find the first instruction
10159 in the sequence. */
10163 /* Delete the instructions. */
10165 }
10168 }
10169 }
10171 /* Replace all the instructions from FIRST up to and including LAST
10172 with NOTE_INSN_DELETED notes. */
10174 static void
10176 {
10178 {
10184 /* If this was the LAST instructions we're supposed to delete,
10185 we're done. */
10190 }
10191 }
10193 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10194 loop LOOP if the order of the sets of these registers can be
10195 swapped. There must be exactly one insn within the loop that sets
10196 this pseudo followed immediately by a move insn that sets
10197 REPLACEMENT with REGNO. */
10198 static void
10201 {
10202 rtx insn;
10211 {
10212 /* Search for the insn that copies REGNO to NEW_REGNO? */
10220 }
10223 {
10224 rtx prev_insn;
10225 rtx prev_set;
10227 /* Some DEF-USE info would come in handy here to make this
10228 function more general. For now, just check the previous insn
10229 which is the most likely candidate for setting REGNO. */
10237 {
10238 /* We have:
10239 (set (reg regno) (expr))
10240 (set (reg new_regno) (reg regno))
10242 so try converting this to:
10243 (set (reg new_regno) (expr))
10244 (set (reg regno) (reg new_regno))
10246 The former construct is often generated when a global
10247 variable used for an induction variable is shadowed by a
10248 register (NEW_REGNO). The latter construct improves the
10249 chances of GIV replacement and BIV elimination. */
10259 {
10266 /* Update first use of REGNO. */
10270 /* Now perform copy propagation to hopefully
10271 remove all uses of REGNO within the loop. */
10273 }
10274 }
10275 }
10276 }
10278 /* Worker function for find_mem_in_note, called via for_each_rtx. */
10280 static int
10282 {
10284 {
10288 }
10290 }
10292 /* Returns the first MEM found in NOTE by depth-first search. */
10294 static rtx
10296 {
10300 }
10302 /* Replace MEM with its associated pseudo register. This function is
10303 called from load_mems via for_each_rtx. DATA is actually a pointer
10304 to a structure describing the instruction currently being scanned
10305 and the MEM we are currently replacing. */
10307 static int
10309 {
10317 {
10322 /* We're not interested in the MEM associated with a
10323 CONST_DOUBLE, so there's no need to traverse into one. */
10327 /* This is not a MEM. */
10329 }
10332 /* This is not the MEM we are currently replacing. */
10335 /* Actually replace the MEM. */
10339 }
10341 static void
10343 {
10344 loop_replace_args args;
10352 /* If we hoist a mem write out of the loop, then REG_EQUAL
10353 notes referring to the mem are no longer valid. */
10355 {
10360 {
10364 {
10365 /* Remove the note. */
10368 }
10369 }
10370 }
10371 }
10373 /* Replace one register with another. Called through for_each_rtx; PX points
10374 to the rtx being scanned. DATA is actually a pointer to
10375 a structure of arguments. */
10377 static int
10379 {
10390 }
10392 static void
10394 {
10395 loop_replace_args args;
10402 }
10403 \f
10404 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10405 (ignored in the interim). */
10407 static rtx
10410 rtx pattern)
10411 {
10413 }
10416 /* If WHERE_INSN is nonzero emit insn for PATTERN before WHERE_INSN
10417 in basic block WHERE_BB (ignored in the interim) within the loop
10418 otherwise hoist PATTERN into the loop pre-header. */
10420 rtx
10422 basic_block where_bb ATTRIBUTE_UNUSED,
10424 {
10428 }
10431 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10432 WHERE_BB (ignored in the interim) within the loop. */
10434 static rtx
10436 basic_block where_bb ATTRIBUTE_UNUSED,
10438 {
10440 }
10443 /* Hoist insn for PATTERN into the loop pre-header. */
10445 rtx
10447 {
10449 }
10452 /* Hoist call insn for PATTERN into the loop pre-header. */
10454 static rtx
10456 {
10458 }
10461 /* Sink insn for PATTERN after the loop end. */
10463 rtx
10465 {
10467 }
10469 /* bl->final_value can be either general_operand or PLUS of general_operand
10470 and constant. Emit sequence of instructions to load it into REG. */
10471 static rtx
10473 {
10474 rtx seq;
10482 }
10484 /* If the loop has multiple exits, emit insn for PATTERN before the
10485 loop to ensure that it will always be executed no matter how the
10486 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10487 since this is slightly more efficient. */
10489 static rtx
10491 {
10494 else
10496 }
10497 \f
10498 static void
10500 {
10508 iv_num++;
10513 {
10516 }
10517 }
10520 static void
10523 {
10525 rtx incr;
10536 {
10539 }
10541 {
10544 }
10548 {
10552 }
10555 {
10559 }
10561 /* List the increments. */
10563 {
10567 }
10569 /* List the givs. */
10571 {
10576 else
10579 }
10580 }
10583 static void
10585 {
10596 {
10600 }
10603 }
10606 static void
10608 {
10615 else
10631 {
10633 {
10645 }
10646 }
10657 {
10661 }
10664 }
10667 void
10669 {
10671 }
10674 void
10676 {
10678 }
10681 void
10683 {
10685 }
10688 void
10690 {
10692 }
10695 #define LOOP_BLOCK_NUM_1(INSN) \
10696 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10698 /* The notes do not have an assigned block, so look at the next insn. */
10699 #define LOOP_BLOCK_NUM(INSN) \
10700 ((INSN) ? (NOTE_P (INSN) \
10701 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10702 : LOOP_BLOCK_NUM_1 (INSN)) \
10703 : -1)
10705 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10707 static void
10710 {
10711 rtx label;
10716 /* Print diagnostics to compare our concept of a loop with
10717 what the loop notes say. */
10732 {
10752 {
10755 {
10758 }
10759 }
10762 /* This can happen when a marked loop appears as two nested loops,
10763 say from while (a || b) {}. The inner loop won't match
10764 the loop markers but the outer one will. */
10767 }
10768 }
10770 /* Call this function from the debugger to dump LOOP. */
10772 void
10774 {
10776 }
10778 /* Call this function from the debugger to dump LOOPS. */
10780 void
10782 {
10784 }