| blob | 165f8d1fa22432b96967c69a58dbb7b4bf18120d |
1 /* Expand the basic unary and binary arithmetic operations, for GNU compiler.
2 Copyright (C) 1987-2022 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
38 /* Include insn-config.h before expr.h so that HAVE_conditional_move
39 is properly defined. */
51 machine_mode *);
57 /* Debug facility for use in GDB. */
59 \f
60 /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to
61 the result of operation CODE applied to OP0 (and OP1 if it is a binary
62 operation). OP0_MODE is OP0's mode.
64 If the last insn does not set TARGET, don't do anything, but return 1.
66 If the last insn or a previous insn sets TARGET and TARGET is one of OP0
67 or OP1, don't add the REG_EQUAL note but return 0. Our caller can then
68 try again, ensuring that TARGET is not one of the operands. */
70 static int
73 {
75 rtx set;
76 rtx note;
93 ;
95 /* If TARGET is in OP0 or OP1, punt. We'd end up with a note referencing
96 a value changing in the insn, so the note would be invalid for CSE. */
99 {
103 {
104 /* For MEM target, with MEM = MEM op X, prefer no REG_EQUAL note
105 over expanding it as temp = MEM op X, MEM = temp. If the target
106 supports MEM = MEM op X instructions, it is sometimes too hard
107 to reconstruct that form later, especially if X is also a memory,
108 and due to multiple occurrences of addresses the address might
109 be forced into register unnecessarily.
110 Note that not emitting the REG_EQUIV note might inhibit
111 CSE in some cases. */
120 }
122 }
129 /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */
136 {
145 {
151 else
155 }
156 /* FALLTHRU */
160 }
161 else
167 }
168 \f
169 /* Given two input operands, OP0 and OP1, determine what the correct from_mode
170 for a widening operation would be. In most cases this would be OP0, but if
171 that's a constant it'll be VOIDmode, which isn't useful. */
173 static machine_mode
175 {
178 machine_mode result;
184 else
191 }
192 \f
193 /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP
194 says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need
195 not actually do a sign-extend or zero-extend, but can leave the
196 higher-order bits of the result rtx undefined, for example, in the case
197 of logical operations, but not right shifts. */
199 static rtx
202 {
203 rtx result;
204 scalar_int_mode int_mode;
206 /* If we don't have to extend and this is a constant, return it. */
210 /* If we must extend do so. If OP is a SUBREG for a promoted object, also
211 extend since it will be more efficient to do so unless the signedness of
212 a promoted object differs from our extension. */
219 /* If MODE is no wider than a single word, we return a lowpart or paradoxical
220 SUBREG. */
224 /* Otherwise, get an object of MODE, clobber it, and set the low-order
225 part to OP. */
231 }
232 \f
233 /* Expand vector widening operations.
235 There are two different classes of operations handled here:
236 1) Operations whose result is wider than all the arguments to the operation.
237 Examples: VEC_UNPACK_HI/LO_EXPR, VEC_WIDEN_MULT_HI/LO_EXPR
238 In this case OP0 and optionally OP1 would be initialized,
239 but WIDE_OP wouldn't (not relevant for this case).
240 2) Operations whose result is of the same size as the last argument to the
241 operation, but wider than all the other arguments to the operation.
242 Examples: WIDEN_SUM_EXPR, VEC_DOT_PROD_EXPR.
243 In the case WIDE_OP, OP0 and optionally OP1 would be initialized.
245 E.g, when called to expand the following operations, this is how
246 the arguments will be initialized:
247 nops OP0 OP1 WIDE_OP
248 widening-sum 2 oprnd0 - oprnd1
249 widening-dot-product 3 oprnd0 oprnd1 oprnd2
250 widening-mult 2 oprnd0 oprnd1 -
251 type-promotion (vec-unpack) 1 oprnd0 - - */
253 rtx
256 {
260 optab widen_pattern_optab;
273 /* The sign is from the result type rather than operand's type
274 for these ops. */
275 widen_pattern_optab
283 {
284 /* For VEC_UNPACK_{LO,HI}_EXPR if the mode of op0 and result is
285 the same scalar mode for VECTOR_BOOLEAN_TYPE_P vectors, use
286 vec_unpacks_sbool_{lo,hi}_optab, so that we can pass in
287 the pattern number of elements in the wider vector. */
288 widen_pattern_optab
292 }
294 {
299 ;
301 {
303 /* Same as optab_vector_mixed_sign but flip the operands. */
305 }
308 else
311 widen_pattern_optab
313 }
314 else
315 widen_pattern_optab
321 tmode0);
322 else
329 {
333 }
335 /* The last operand is of a wider mode than the rest of the operands. */
339 {
343 }
354 }
356 /* Generate code to perform an operation specified by TERNARY_OPTAB
357 on operands OP0, OP1 and OP2, with result having machine-mode MODE.
359 UNSIGNEDP is for the case where we have to widen the operands
360 to perform the operation. It says to use zero-extension.
362 If TARGET is nonzero, the value
363 is generated there, if it is convenient to do so.
364 In all cases an rtx is returned for the locus of the value;
365 this may or may not be TARGET. */
367 rtx
370 {
382 }
385 /* Like expand_binop, but return a constant rtx if the result can be
386 calculated at compile time. The arguments and return value are
387 otherwise the same as for expand_binop. */
389 rtx
393 {
395 {
400 }
403 }
405 /* Like simplify_expand_binop, but always put the result in TARGET.
406 Return true if the expansion succeeded. */
408 bool
412 {
420 }
422 /* Create a new vector value in VMODE with all elements set to OP. The
423 mode of OP must be the element mode of VMODE. If OP is a constant,
424 then the return value will be a constant. */
426 rtx
428 {
430 rtvec vec;
439 {
445 }
450 /* ??? If the target doesn't have a vec_init, then we have no easy way
451 of performing this operation. Most of this sort of generic support
452 is hidden away in the vector lowering support in gimple. */
465 }
467 /* This subroutine of expand_doubleword_shift handles the cases in which
468 the effective shift value is >= BITS_PER_WORD. The arguments and return
469 value are the same as for the parent routine, except that SUPERWORD_OP1
470 is the shift count to use when shifting OUTOF_INPUT into INTO_TARGET.
471 INTO_TARGET may be null if the caller has decided to calculate it. */
473 static bool
477 {
484 {
485 /* For a signed right shift, we must fill OUTOF_TARGET with copies
486 of the sign bit, otherwise we must fill it with zeros. */
489 else
495 }
497 }
499 /* This subroutine of expand_doubleword_shift handles the cases in which
500 the effective shift value is < BITS_PER_WORD. The arguments and return
501 value are the same as for the parent routine. */
503 static bool
509 {
516 /* The low OP1 bits of INTO_TARGET come from the high bits of OUTOF_INPUT.
517 We therefore need to shift OUTOF_INPUT by (BITS_PER_WORD - OP1) bits in
518 the opposite direction to BINOPTAB. */
520 {
526 }
527 else
528 {
529 /* We must avoid shifting by BITS_PER_WORD bits since that is either
530 the same as a zero shift (if shift_mask == BITS_PER_WORD - 1) or
531 has unknown behavior. Do a single shift first, then shift by the
532 remainder. It's OK to use ~OP1 as the remainder if shift counts
533 are truncated to the mode size. */
537 {
538 tmp = immed_wide_int_const
542 }
543 else
544 {
549 }
550 }
558 /* Shift INTO_INPUT logically by OP1. This is the last use of INTO_INPUT
559 so the result can go directly into INTO_TARGET if convenient. */
565 /* Now OR in the bits carried over from OUTOF_INPUT. */
570 /* Use a standard word_mode shift for the out-of half. */
577 }
580 /* Try implementing expand_doubleword_shift using conditional moves.
581 The shift is by < BITS_PER_WORD if (CMP_CODE CMP1 CMP2) is true,
582 otherwise it is by >= BITS_PER_WORD. SUBWORD_OP1 and SUPERWORD_OP1
583 are the shift counts to use in the former and latter case. All other
584 arguments are the same as the parent routine. */
586 static bool
594 {
597 /* Put the superword version of the output into OUTOF_SUPERWORD and
598 INTO_SUPERWORD. */
601 {
602 /* The value INTO_TARGET >> SUBWORD_OP1, which we later store in
603 OUTOF_TARGET, is the same as the value of INTO_SUPERWORD. */
608 }
609 else
610 {
616 }
618 /* Put the subword version directly in OUTOF_TARGET and INTO_TARGET. */
625 /* Select between them. Do the INTO half first because INTO_SUPERWORD
626 might be the current value of OUTOF_TARGET. */
639 }
641 /* Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts.
642 OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first
643 input operand; the shift moves bits in the direction OUTOF_INPUT->
644 INTO_TARGET. OUTOF_TARGET and INTO_TARGET are the equivalent words
645 of the target. OP1 is the shift count and OP1_MODE is its mode.
646 If OP1 is constant, it will have been truncated as appropriate
647 and is known to be nonzero.
649 If SHIFT_MASK is zero, the result of word shifts is undefined when the
650 shift count is outside the range [0, BITS_PER_WORD). This routine must
651 avoid generating such shifts for OP1s in the range [0, BITS_PER_WORD * 2).
653 If SHIFT_MASK is nonzero, all word-mode shift counts are effectively
654 masked by it and shifts in the range [BITS_PER_WORD, SHIFT_MASK) will
655 fill with zeros or sign bits as appropriate.
657 If SHIFT_MASK is BITS_PER_WORD - 1, this routine will synthesize
658 a doubleword shift whose equivalent mask is BITS_PER_WORD * 2 - 1.
659 Doing this preserves semantics required by SHIFT_COUNT_TRUNCATED.
660 In all other cases, shifts by values outside [0, BITS_PER_UNIT * 2)
661 are undefined.
663 BINOPTAB, UNSIGNEDP and METHODS are as for expand_binop. This function
664 may not use INTO_INPUT after modifying INTO_TARGET, and similarly for
665 OUTOF_INPUT and OUTOF_TARGET. OUTOF_TARGET can be null if the parent
666 function wants to calculate it itself.
668 Return true if the shift could be successfully synthesized. */
670 static bool
676 {
680 /* See if word-mode shifts by BITS_PER_WORD...BITS_PER_WORD * 2 - 1 will
681 fill the result with sign or zero bits as appropriate. If so, the value
682 of OUTOF_TARGET will always be (SHIFT OUTOF_INPUT OP1). Recursively call
683 this routine to calculate INTO_TARGET (which depends on both OUTOF_INPUT
684 and INTO_INPUT), then emit code to set up OUTOF_TARGET.
686 This isn't worthwhile for constant shifts since the optimizers will
687 cope better with in-range shift counts. */
691 {
701 }
703 /* Set CMP_CODE, CMP1 and CMP2 so that the rtx (CMP_CODE CMP1 CMP2)
704 is true when the effective shift value is less than BITS_PER_WORD.
705 Set SUPERWORD_OP1 to the shift count that should be used to shift
706 OUTOF_INPUT into INTO_TARGET when the condition is false. */
709 {
710 /* Set CMP1 to OP1 & BITS_PER_WORD. The result is zero iff OP1
711 is a subword shift count. */
717 }
718 else
719 {
720 /* Set CMP1 to OP1 - BITS_PER_WORD. */
726 }
730 /* If we can compute the condition at compile time, pick the
731 appropriate subroutine. */
734 {
739 else
744 }
746 /* Try using conditional moves to generate straight-line code. */
748 {
758 }
760 /* As a last resort, use branches to select the correct alternative. */
764 NO_DEFER_POP;
768 OK_DEFER_POP;
787 }
788 \f
789 /* Subroutine of expand_binop. Perform a double word multiplication of
790 operands OP0 and OP1 both of mode MODE, which is exactly twice as wide
791 as the target's word_mode. This function return NULL_RTX if anything
792 goes wrong, in which case it may have already emitted instructions
793 which need to be deleted.
795 If we want to multiply two two-word values and have normal and widening
796 multiplies of single-word values, we can do this with three smaller
797 multiplications.
799 The multiplication proceeds as follows:
800 _______________________
801 [__op0_high_|__op0_low__]
802 _______________________
803 * [__op1_high_|__op1_low__]
804 _______________________________________________
805 _______________________
806 (1) [__op0_low__*__op1_low__]
807 _______________________
808 (2a) [__op0_low__*__op1_high_]
809 _______________________
810 (2b) [__op0_high_*__op1_low__]
811 _______________________
812 (3) [__op0_high_*__op1_high_]
815 This gives a 4-word result. Since we are only interested in the
816 lower 2 words, partial result (3) and the upper words of (2a) and
817 (2b) don't need to be calculated. Hence (2a) and (2b) can be
818 calculated using non-widening multiplication.
820 (1), however, needs to be calculated with an unsigned widening
821 multiplication. If this operation is not directly supported we
822 try using a signed widening multiplication and adjust the result.
823 This adjustment works as follows:
825 If both operands are positive then no adjustment is needed.
827 If the operands have different signs, for example op0_low < 0 and
828 op1_low >= 0, the instruction treats the most significant bit of
829 op0_low as a sign bit instead of a bit with significance
830 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low
831 with 2**BITS_PER_WORD - op0_low, and two's complements the
832 result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to
833 the result.
835 Similarly, if both operands are negative, we need to add
836 (op0_low + op1_low) * 2**BITS_PER_WORD.
838 We use a trick to adjust quickly. We logically shift op0_low right
839 (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to
840 op0_high (op1_high) before it is used to calculate 2b (2a). If no
841 logical shift exists, we do an arithmetic right shift and subtract
842 the 0 or -1. */
844 static rtx
847 {
859 /* If we're using an unsigned multiply to directly compute the product
860 of the low-order words of the operands and perform any required
861 adjustments of the operands, we begin by trying two more multiplications
862 and then computing the appropriate sum.
864 We have checked above that the required addition is provided.
865 Full-word addition will normally always succeed, especially if
866 it is provided at all, so we don't worry about its failure. The
867 multiplication may well fail, however, so we do handle that. */
870 {
871 /* ??? This could be done with emit_store_flag where available. */
877 else
878 {
885 }
889 }
896 /* OP0_HIGH should now be dead. */
899 {
900 /* ??? This could be done with emit_store_flag where available. */
906 else
907 {
914 }
918 }
925 /* OP1_HIGH should now be dead. */
933 /* *_widen_optab needs to determine operand mode, make sure at least
934 one operand has non-VOID mode. */
941 else
953 }
955 /* Subroutine of expand_binop. Optimize unsigned double-word OP0 % OP1 for
956 constant OP1. If for some bit in [BITS_PER_WORD / 2, BITS_PER_WORD] range
957 (prefer higher bits) ((1w << bit) % OP1) == 1, then the modulo can be
958 computed in word-mode as ((OP0 & (bit - 1)) + ((OP0 >> bit) & (bit - 1))
959 + (OP0 >> (2 * bit))) % OP1. Whether we need to sum 2, 3 or 4 values
960 depends on the bit value, if 2, then carry from the addition needs to be
961 added too, i.e. like:
962 sum += __builtin_add_overflow (low, high, &sum)
964 Optimize signed double-word OP0 % OP1 similarly, just apply some correction
965 factor to the sum before doing unsigned remainder, in the form of
966 sum += (((signed) OP0 >> (2 * BITS_PER_WORD - 1)) & const);
967 then perform unsigned
968 remainder = sum % OP1;
969 and finally
970 remainder += ((signed) OP0 >> (2 * BITS_PER_WORD - 1)) & (1 - OP1); */
972 static rtx
974 {
980 {
986 {
987 /* For signed modulo we need to add correction to the sum
988 and that might again overflow. */
1011 OPTAB_DIRECT);
1014 }
1015 else
1016 {
1017 /* Code below uses GEN_INT, so we need the masks to be representable
1018 in HOST_WIDE_INTs. */
1021 /* If op0 is e.g. -1 or -2 unsigned, then the 2 additions might
1022 overflow. Consider 64-bit -1ULL for word size 32, if we add
1023 0x7fffffffU + 0x7fffffffU + 3U, it wraps around to 1. */
1031 {
1032 /* For signed modulo, compute it as unsigned modulo of
1033 sum with a correction added to it if OP0 is negative,
1034 such that the result can be computed as unsigned
1035 remainder + ((OP1 >> (2 * BITS_PER_WORD - 1)) & (1 - OP1). */
1039 /* wmod2 == -wmod1. */
1042 {
1046 /* Now verify if the count sums can't overflow, and punt
1047 if they could. */
1058 mode);
1067 OPTAB_DIRECT);
1070 }
1071 }
1074 {
1088 OPTAB_DIRECT);
1093 else
1098 }
1100 {
1105 }
1106 }
1114 {
1116 {
1118 mode);
1124 }
1127 word_mode),
1135 }
1138 /* Punt if we need any library calls. */
1141 else
1147 }
1149 }
1151 /* Similarly to the above function, but compute both quotient and remainder.
1152 Quotient can be computed from the remainder as:
1153 rem = op0 % op1; // Handled using expand_doubleword_mod
1154 quot = (op0 - rem) * inv; // inv is multiplicative inverse of op1 modulo
1155 // 2 * BITS_PER_WORD
1157 We can also handle cases where op1 is a multiple of power of two constant
1158 and constant handled by expand_doubleword_mod.
1159 op11 = 1 << __builtin_ctz (op1);
1160 op12 = op1 / op11;
1161 rem1 = op0 % op12; // Handled using expand_doubleword_mod
1162 quot1 = (op0 - rem1) * inv; // inv is multiplicative inverse of op12 modulo
1163 // 2 * BITS_PER_WORD
1164 rem = (quot1 % op11) * op12 + rem1;
1165 quot = quot1 / op11; */
1167 rtx
1170 {
1173 /* Negative dividend should have been optimized into positive,
1174 similarly modulo by 1 and modulo by power of two is optimized
1175 differently too. */
1182 {
1186 }
1210 {
1233 }
1235 /* Punt if we need any library calls. */
1238 else
1246 }
1247 \f
1248 /* Wrapper around expand_binop which takes an rtx code to specify
1249 the operation to perform, not an optab pointer. All other
1250 arguments are the same. */
1251 rtx
1255 {
1260 }
1262 /* Return whether OP0 and OP1 should be swapped when expanding a commutative
1263 binop. Order them according to commutative_operand_precedence and, if
1264 possible, try to put TARGET or a pseudo first. */
1265 static bool
1267 {
1277 /* With equal precedence, both orders are ok, but it is better if the
1278 first operand is TARGET, or if both TARGET and OP0 are pseudos. */
1281 else
1283 }
1285 /* Return true if BINOPTAB implements a shift operation. */
1287 static bool
1289 {
1291 {
1303 }
1304 }
1306 /* Return true if BINOPTAB implements a commutative binary operation. */
1308 static bool
1310 {
1316 }
1318 /* X is to be used in mode MODE as operand OPN to BINOPTAB. If we're
1319 optimizing, and if the operand is a constant that costs more than
1320 1 instruction, force the constant into a register and return that
1321 register. Return X otherwise. UNSIGNEDP says whether X is unsigned. */
1323 static rtx
1326 {
1330 && optimize
1334 {
1336 {
1340 }
1341 else
1344 }
1346 }
1348 /* Helper function for expand_binop: handle the case where there
1349 is an insn ICODE that directly implements the indicated operation.
1350 Returns null if this is not possible. */
1351 static rtx
1356 {
1366 /* If it is a commutative operator and the modes would match
1367 if we would swap the operands, we can save the conversions. */
1374 /* If we are optimizing, force expensive constants into a register. */
1378 else
1379 /* Shifts and rotates often use a different mode for op1 from op0;
1380 for VOIDmode constants we don't know the mode, so force it
1381 to be canonicalized using convert_modes. */
1384 /* In case the insn wants input operands in modes different from
1385 those of the actual operands, convert the operands. It would
1386 seem that we don't need to convert CONST_INTs, but we do, so
1387 that they're properly zero-extended, sign-extended or truncated
1388 for their mode. */
1392 {
1395 }
1400 {
1403 }
1405 /* If operation is commutative,
1406 try to make the first operand a register.
1407 Even better, try to make it the same as the target.
1408 Also try to make the last operand a constant. */
1413 /* Now, if insn's predicates don't allow our operands, put them into
1414 pseudo regs. */
1423 {
1424 /* The mode of the result is different then the mode of the
1425 arguments. */
1429 {
1432 }
1433 }
1434 else
1442 {
1443 /* If PAT is composed of more than one insn, try to add an appropriate
1444 REG_EQUAL note to it. If we can't because TEMP conflicts with an
1445 operand, call expand_binop again, this time without a target. */
1450 {
1454 }
1458 }
1461 }
1463 /* Generate code to perform an operation specified by BINOPTAB
1464 on operands OP0 and OP1, with result having machine-mode MODE.
1466 UNSIGNEDP is for the case where we have to widen the operands
1467 to perform the operation. It says to use zero-extension.
1469 If TARGET is nonzero, the value
1470 is generated there, if it is convenient to do so.
1471 In all cases an rtx is returned for the locus of the value;
1472 this may or may not be TARGET. */
1474 rtx
1477 {
1478 enum optab_methods next_methods
1483 machine_mode wider_mode;
1484 scalar_int_mode int_mode;
1485 rtx libfunc;
1486 rtx temp;
1492 /* If subtracting an integer constant, convert this into an addition of
1493 the negated constant. */
1496 {
1499 }
1500 /* For shifts, constant invalid op1 might be expanded from different
1501 mode than MODE. As those are invalid, force them to a register
1502 to avoid further problems during expansion. */
1506 {
1509 }
1511 /* Record where to delete back to if we backtrack. */
1514 /* If we can do it with a three-operand insn, do so. */
1517 {
1519 {
1522 }
1523 else
1526 {
1531 }
1532 }
1534 /* If we were trying to rotate, and that didn't work, try rotating
1535 the other direction before falling back to shifts and bitwise-or. */
1541 {
1543 rtx newop1;
1550 else
1559 }
1561 /* If this is a multiply, see if we can do a widening operation that
1562 takes operands of this mode and makes a wider mode. */
1567 ? umul_widen_optab
1570 {
1571 /* *_widen_optab needs to determine operand mode, make sure at least
1572 one operand has non-VOID mode. */
1580 {
1584 else
1586 }
1587 }
1589 /* If this is a vector shift by a scalar, see if we can do a vector
1590 shift by a vector. If so, broadcast the scalar into a vector. */
1592 {
1608 {
1609 /* The scalar may have been extended to be too wide. Truncate
1610 it back to the proper size to fit in the broadcast vector. */
1620 {
1625 }
1626 }
1627 }
1629 /* Look for a wider mode of the same class for which we think we
1630 can open-code the operation. Check for a widening multiply at the
1631 wider mode as well. */
1636 {
1637 machine_mode next_mode;
1642 ? umul_widen_optab
1646 {
1650 /* For certain integer operations, we need not actually extend
1651 the narrow operands, as long as we will truncate
1652 the results to the same narrowness. */
1659 {
1666 }
1670 /* The second operand of a shift must always be extended. */
1677 {
1680 {
1685 }
1686 else
1688 }
1689 else
1691 }
1692 }
1694 /* If operation is commutative,
1695 try to make the first operand a register.
1696 Even better, try to make it the same as the target.
1697 Also try to make the last operand a constant. */
1702 /* These can be done a word at a time. */
1707 {
1711 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1712 won't be accurate, so use a new target. */
1723 /* Do the actual arithmetic. */
1731 {
1743 }
1749 {
1752 }
1753 }
1755 /* Synthesize double word shifts from single word shifts. */
1765 {
1767 scalar_int_mode op1_mode;
1775 /* Apply the truncation to constant shifts. */
1782 /* Make sure that this is a combination that expand_doubleword_shift
1783 can handle. See the comments there for details. */
1787 {
1793 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1794 won't be accurate, so use a new target. */
1805 /* OUTOF_* is the word we are shifting bits away from, and
1806 INTO_* is the word that we are shifting bits towards, thus
1807 they differ depending on the direction of the shift and
1808 WORDS_BIG_ENDIAN. */
1823 {
1829 }
1831 }
1832 }
1834 /* Synthesize double word rotates from single word shifts. */
1841 {
1845 rtx inter;
1848 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1849 won't be accurate, so use a new target. Do this also if target is not
1850 a REG, first because having a register instead may open optimization
1851 opportunities, and second because if target and op0 happen to be MEMs
1852 designating the same location, we would risk clobbering it too early
1853 in the code sequence we generate below. */
1867 /* OUTOF_* is the word we are shifting bits away from, and
1868 INTO_* is the word that we are shifting bits towards, thus
1869 they differ depending on the direction of the shift and
1870 WORDS_BIG_ENDIAN. */
1882 {
1883 /* This is just a word swap. */
1887 }
1888 else
1889 {
1901 {
1904 }
1905 else
1906 {
1909 }
1910 rtx first_shift_count_rtx
1912 rtx second_shift_count_rtx
1925 else
1945 }
1951 {
1954 }
1955 }
1957 /* These can be done a word at a time by propagating carries. */
1962 {
1969 /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG
1970 value is one of those, use it. Otherwise, use 1 since it is the
1971 one easiest to get. */
1972 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
1974 #else
1976 #endif
1978 /* Prepare the operands. */
1987 /* Indicate for flow that the entire target reg is being set. */
1991 /* Do the actual arithmetic. */
1993 {
1998 rtx x;
2000 /* Main add/subtract of the input operands. */
2008 {
2009 /* Store carry from main add/subtract. */
2016 }
2019 {
2020 rtx newx;
2022 /* Add/subtract previous carry to main result. */
2029 {
2030 /* Get out carry from adding/subtracting carry in. */
2038 /* Logical-ior the two poss. carry together. */
2044 }
2046 }
2047 else
2048 {
2051 }
2054 }
2057 {
2060 {
2067 target);
2068 }
2069 else
2073 }
2075 else
2077 }
2079 /* Attempt to synthesize double word multiplies using a sequence of word
2080 mode multiplications. We first attempt to generate a sequence using a
2081 more efficient unsigned widening multiply, and if that fails we then
2082 try using a signed widening multiply. */
2089 {
2093 {
2098 }
2103 {
2108 }
2111 {
2113 {
2115 product);
2117 REG_EQUAL,
2122 }
2124 }
2125 }
2127 /* Attempt to synthetize double word modulo by constant divisor. */
2132 && optimize
2138 int_mode) == CODE_FOR_nothing
2142 {
2148 else
2149 {
2151 binoptab == umod_optab
2157 }
2159 {
2161 {
2163 res);
2168 }
2170 }
2171 else
2173 }
2175 /* It can't be open-coded in this mode.
2176 Use a library call if one is available and caller says that's ok. */
2181 {
2185 rtx value;
2190 {
2192 /* Specify unsigned here,
2193 since negative shift counts are meaningless. */
2195 }
2201 /* Pass 1 for NO_QUEUE so we don't lose any increments
2202 if the libcall is cse'd or moved. */
2213 trapv ? NULL_RTX
2218 }
2222 /* It can't be done in this mode. Can we do it in a wider mode? */
2226 {
2227 /* Caller says, don't even try. */
2230 }
2232 /* Compute the value of METHODS to pass to recursive calls.
2233 Don't allow widening to be tried recursively. */
2237 /* Look for a wider mode of the same class for which it appears we can do
2238 the operation. */
2241 {
2242 /* This code doesn't make sense for conversion optabs, since we
2243 wouldn't then want to extend the operands to be the same size
2244 as the result. */
2247 {
2251 {
2255 /* For certain integer operations, we need not actually extend
2256 the narrow operands, as long as we will truncate
2257 the results to the same narrowness. */
2269 /* The second operand of a shift must always be extended. */
2276 {
2279 {
2284 }
2285 else
2287 }
2288 else
2290 }
2291 }
2292 }
2296 }
2297 \f
2298 /* Expand a binary operator which has both signed and unsigned forms.
2299 UOPTAB is the optab for unsigned operations, and SOPTAB is for
2300 signed operations.
2302 If we widen unsigned operands, we may use a signed wider operation instead
2303 of an unsigned wider operation, since the result would be the same. */
2305 rtx
2309 {
2310 rtx temp;
2314 /* Do it without widening, if possible. */
2320 /* Try widening to a signed int. Disable any direct use of any
2321 signed insn in the current mode. */
2327 /* For unsigned operands, try widening to an unsigned int. */
2334 /* Use the right width libcall if that exists. */
2340 /* Must widen and use a libcall, use either signed or unsigned. */
2347 egress:
2348 /* Undo the fiddling above. */
2352 }
2353 \f
2354 /* Generate code to perform an operation specified by UNOPPTAB
2355 on operand OP0, with two results to TARG0 and TARG1.
2356 We assume that the order of the operands for the instruction
2357 is TARG0, TARG1, OP0.
2359 Either TARG0 or TARG1 may be zero, but what that means is that
2360 the result is not actually wanted. We will generate it into
2361 a dummy pseudo-reg and discard it. They may not both be zero.
2363 Returns 1 if this operation can be performed; 0 if not. */
2365 int
2368 {
2371 machine_mode wider_mode;
2382 /* Record where to go back to if we fail. */
2386 {
2395 }
2397 /* It can't be done in this mode. Can we do it in a wider mode? */
2400 {
2402 {
2404 {
2410 {
2414 }
2415 else
2417 }
2418 }
2419 }
2423 }
2424 \f
2425 /* Generate code to perform an operation specified by BINOPTAB
2426 on operands OP0 and OP1, with two results to TARG1 and TARG2.
2427 We assume that the order of the operands for the instruction
2428 is TARG0, OP0, OP1, TARG1, which would fit a pattern like
2429 [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))].
2431 Either TARG0 or TARG1 may be zero, but what that means is that
2432 the result is not actually wanted. We will generate it into
2433 a dummy pseudo-reg and discard it. They may not both be zero.
2435 Returns 1 if this operation can be performed; 0 if not. */
2437 int
2440 {
2443 machine_mode wider_mode;
2454 /* Record where to go back to if we fail. */
2458 {
2465 /* If we are optimizing, force expensive constants into a register. */
2476 }
2478 /* It can't be done in this mode. Can we do it in a wider mode? */
2481 {
2483 {
2485 {
2493 {
2497 }
2498 else
2500 }
2501 }
2502 }
2506 }
2508 /* Expand the two-valued library call indicated by BINOPTAB, but
2509 preserve only one of the values. If TARG0 is non-NULL, the first
2510 value is placed into TARG0; otherwise the second value is placed
2511 into TARG1. Exactly one of TARG0 and TARG1 must be non-NULL. The
2512 value stored into TARG0 or TARG1 is equivalent to (CODE OP0 OP1).
2513 This routine assumes that the value returned by the library call is
2514 as if the return value was of an integral mode twice as wide as the
2515 mode of OP0. Returns 1 if the call was successful. */
2517 bool
2520 {
2521 machine_mode mode;
2522 machine_mode libval_mode;
2523 rtx libval;
2525 rtx libfunc;
2527 /* Exactly one of TARG0 or TARG1 should be non-NULL. */
2535 /* The value returned by the library function will have twice as
2536 many bits as the nominal MODE. */
2540 libval_mode,
2543 /* Get the part of VAL containing the value that we want. */
2548 /* Move the into the desired location. */
2553 }
2555 \f
2556 /* Wrapper around expand_unop which takes an rtx code to specify
2557 the operation to perform, not an optab pointer. All other
2558 arguments are the same. */
2559 rtx
2562 {
2567 }
2569 /* Try calculating
2570 (clz:narrow x)
2571 as
2572 (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)).
2574 A similar operation can be used for clrsb. UNOPTAB says which operation
2575 we are trying to expand. */
2576 static rtx
2578 {
2579 opt_scalar_int_mode wider_mode_iter;
2581 {
2584 {
2597 temp = expand_binop
2601 wider_mode),
2607 }
2608 }
2610 }
2612 /* Attempt to emit (clrsb:mode op0) as
2613 (plus:mode (clz:mode (xor:mode op0 (ashr:mode op0 (const_int prec-1))))
2614 (const_int -1))
2615 if CLZ_DEFINED_VALUE_AT_ZERO (mode, val) is 2 and val is prec,
2616 or as
2617 (clz:mode (ior:mode (xor:mode (ashl:mode op0 (const_int 1))
2618 (ashr:mode op0 (const_int prec-1)))
2619 (const_int 1)))
2620 otherwise. */
2622 static rtx
2624 {
2634 else
2639 {
2643 {
2644 fail:
2647 }
2648 }
2657 OPTAB_DIRECT);
2662 {
2667 }
2673 {
2678 }
2686 }
2688 /* Try calculating clz of a double-word quantity as two clz's of word-sized
2689 quantities, choosing which based on whether the high word is nonzero. */
2690 static rtx
2692 {
2701 /* If we were not given a target, use a word_mode register, not a
2702 'mode' register. The result will fit, and nobody is expecting
2703 anything bigger (the return type of __builtin_clz* is int). */
2707 /* In any case, write to a word_mode scratch in both branches of the
2708 conditional, so we can ensure there is a single move insn setting
2709 'target' to tag a REG_EQUAL note on. */
2714 /* If the high word is not equal to zero,
2715 then clz of the full value is clz of the high word. */
2729 /* Else clz of the full value is clz of the low word plus the number
2730 of bits in the high word. */
2754 fail:
2757 }
2759 /* Try calculating popcount of a double-word quantity as two popcount's of
2760 word-sized quantities and summing up the results. */
2761 static rtx
2763 {
2776 {
2779 }
2781 /* If we were not given a target, use a word_mode register, not a
2782 'mode' register. The result will fit, and nobody is expecting
2783 anything bigger (the return type of __builtin_popcount* is int). */
2795 }
2797 /* Try calculating
2798 (parity:wide x)
2799 as
2800 (parity:narrow (low (x) ^ high (x))) */
2801 static rtx
2803 {
2809 }
2811 /* Try calculating
2812 (bswap:narrow x)
2813 as
2814 (lshiftrt:wide (bswap:wide x) ((width wide) - (width narrow))). */
2815 static rtx
2817 {
2818 rtx x;
2820 opt_scalar_int_mode wider_mode_iter;
2845 {
2849 }
2850 else
2854 }
2856 /* Try calculating bswap as two bswaps of two word-sized operands. */
2858 static rtx
2860 {
2876 }
2878 /* Try calculating (parity x) as (and (popcount x) 1), where
2879 popcount can also be done in a wider mode. */
2880 static rtx
2882 {
2884 opt_scalar_int_mode wider_mode_iter;
2886 {
2889 {
2906 {
2910 else
2912 }
2913 else
2915 }
2916 }
2918 }
2920 /* Try calculating ctz(x) as K - clz(x & -x) ,
2921 where K is GET_MODE_PRECISION(mode) - 1.
2923 Both __builtin_ctz and __builtin_clz are undefined at zero, so we
2924 don't have to worry about what the hardware does in that case. (If
2925 the clz instruction produces the usual value at 0, which is K, the
2926 result of this code sequence will be -1; expand_ffs, below, relies
2927 on this. It might be nice to have it be K instead, for consistency
2928 with the (very few) processors that provide a ctz with a defined
2929 value, but that would take one more instruction, and it would be
2930 less convenient for expand_ffs anyway. */
2932 static rtx
2934 {
2936 rtx temp;
2955 {
2958 }
2966 }
2969 /* Try calculating ffs(x) using ctz(x) if we have that instruction, or
2970 else with the sequence used by expand_clz.
2972 The ffs builtin promises to return zero for a zero value and ctz/clz
2973 may have an undefined value in that case. If they do not give us a
2974 convenient value, we have to generate a test and branch. */
2975 static rtx
2977 {
2980 rtx temp;
2984 {
2992 }
2994 {
3001 {
3004 }
3005 }
3006 else
3011 else
3012 {
3013 /* We don't try to do anything clever with the situation found
3014 on some processors (eg Alpha) where ctz(0:mode) ==
3015 bitsize(mode). If someone can think of a way to send N to -1
3016 and leave alone all values in the range 0..N-1 (where N is a
3017 power of two), cheaper than this test-and-branch, please add it.
3019 The test-and-branch is done after the operation itself, in case
3020 the operation sets condition codes that can be recycled for this.
3021 (This is true on i386, for instance.) */
3029 }
3031 /* temp now has a value in the range -1..bitsize-1. ffs is supposed
3032 to produce a value in the range 0..bitsize. */
3045 fail:
3048 }
3050 /* Extract the OMODE lowpart from VAL, which has IMODE. Under certain
3051 conditions, VAL may already be a SUBREG against which we cannot generate
3052 a further SUBREG. In this case, we expect forcing the value into a
3053 register will work around the situation. */
3055 static rtx
3057 machine_mode imode)
3058 {
3059 rtx ret;
3062 {
3066 }
3068 }
3070 /* Expand a floating point absolute value or negation operation via a
3071 logical operation on the sign bit. */
3073 static rtx
3076 {
3079 scalar_int_mode imode;
3080 rtx temp;
3083 /* The format has to have a simple sign bit. */
3092 /* Don't create negative zeros if the format doesn't support them. */
3097 {
3102 }
3103 else
3104 {
3109 else
3113 }
3126 {
3130 {
3135 {
3137 op0_piece,
3142 }
3143 else
3145 }
3151 }
3152 else
3153 {
3162 target);
3163 }
3166 }
3168 /* As expand_unop, but will fail rather than attempt the operation in a
3169 different mode or with a libcall. */
3170 static rtx
3173 {
3175 {
3185 {
3190 {
3193 }
3198 }
3199 }
3201 }
3203 /* Generate code to perform an operation specified by UNOPTAB
3204 on operand OP0, with result having machine-mode MODE.
3206 UNSIGNEDP is for the case where we have to widen the operands
3207 to perform the operation. It says to use zero-extension.
3209 If TARGET is nonzero, the value
3210 is generated there, if it is convenient to do so.
3211 In all cases an rtx is returned for the locus of the value;
3212 this may or may not be TARGET. */
3214 rtx
3217 {
3219 machine_mode wider_mode;
3220 scalar_int_mode int_mode;
3221 scalar_float_mode float_mode;
3222 rtx temp;
3223 rtx libfunc;
3229 /* It can't be done in this mode. Can we open-code it in a wider mode? */
3231 /* Widening (or narrowing) clz needs special treatment. */
3233 {
3235 {
3242 {
3246 }
3247 }
3250 }
3253 {
3255 {
3262 }
3264 }
3271 {
3275 }
3283 {
3287 }
3289 /* Widening (or narrowing) bswap needs special treatment. */
3291 {
3292 /* HImode is special because in this mode BSWAP is equivalent to ROTATE
3293 or ROTATERT. First try these directly; if this fails, then try the
3294 obvious pair of shifts with allowed widening, as this will probably
3295 be always more efficient than the other fallback methods. */
3297 {
3302 {
3308 }
3311 {
3317 }
3328 {
3333 }
3336 }
3339 {
3344 /* We do not provide a 128-bit bswap in libgcc so force the use of
3345 a double bswap for 64-bit targets. */
3349 {
3353 }
3354 }
3357 }
3361 {
3363 {
3367 /* For certain operations, we need not actually extend
3368 the narrow operand, as long as we will truncate the
3369 results to the same narrowness. */
3377 unsignedp);
3380 {
3383 {
3388 }
3389 else
3391 }
3392 else
3394 }
3395 }
3397 /* These can be done a word at a time. */
3402 {
3414 /* Do the actual arithmetic. */
3416 {
3424 }
3431 }
3433 /* Emit ~op0 as op0 ^ -1. */
3437 {
3442 }
3445 {
3446 /* Try negating floating point values by flipping the sign bit. */
3448 {
3452 }
3454 /* If there is no negation pattern, and we have no negative zero,
3455 try subtracting from zero. */
3457 {
3464 }
3465 }
3467 /* Try calculating parity (x) as popcount (x) % 2. */
3469 {
3473 }
3475 /* Try implementing ffs (x) in terms of clz (x). */
3477 {
3481 }
3483 /* Try implementing ctz (x) in terms of clz (x). */
3485 {
3489 }
3491 try_libcall:
3492 /* Now try a library call in this mode. */
3495 {
3497 rtx value;
3498 rtx eq_value;
3501 /* All of these functions return small values. Thus we choose to
3502 have them return something that isn't a double-word. */
3506 outmode
3512 /* Pass 1 for NO_QUEUE so we don't lose any increments
3513 if the libcall is cse'd or moved. */
3523 else
3524 {
3531 }
3535 }
3537 /* It can't be done in this mode. Can we do it in a wider mode? */
3540 {
3542 {
3545 {
3549 /* For certain operations, we need not actually extend
3550 the narrow operand, as long as we will truncate the
3551 results to the same narrowness. */
3559 unsignedp);
3561 /* If we are generating clz using wider mode, adjust the
3562 result. Similarly for clrsb. */
3565 {
3566 scalar_int_mode wider_int_mode
3569 temp = expand_binop
3573 wider_int_mode),
3575 }
3577 /* Likewise for bswap. */
3579 {
3580 scalar_int_mode wider_int_mode
3592 }
3595 {
3597 {
3602 }
3603 else
3605 }
3606 else
3608 }
3609 }
3610 }
3612 /* One final attempt at implementing negation via subtraction,
3613 this time allowing widening of the operand. */
3615 {
3616 rtx temp;
3623 }
3626 }
3627 \f
3628 /* Emit code to compute the absolute value of OP0, with result to
3629 TARGET if convenient. (TARGET may be 0.) The return value says
3630 where the result actually is to be found.
3632 MODE is the mode of the operand; the mode of the result is
3633 different but can be deduced from MODE.
3635 */
3637 rtx
3640 {
3641 rtx temp;
3647 /* First try to do it with a special abs instruction. */
3653 /* For floating point modes, try clearing the sign bit. */
3654 scalar_float_mode float_mode;
3656 {
3660 }
3662 /* If we have a MAX insn, we can do this as MAX (x, -x). */
3665 {
3672 OPTAB_WIDEN);
3678 }
3680 /* If this machine has expensive jumps, we can do integer absolute
3681 value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)),
3682 where W is the width of MODE. */
3684 scalar_int_mode int_mode;
3688 {
3694 OPTAB_LIB_WIDEN);
3702 }
3705 }
3707 rtx
3710 {
3711 rtx temp;
3722 /* If that does not win, use conditional jump and negate. */
3724 /* It is safe to use the target if it is the same
3725 as the source if this is also a pseudo register */
3739 NO_DEFER_POP;
3750 OK_DEFER_POP;
3752 }
3754 /* Emit code to compute the one's complement absolute value of OP0
3755 (if (OP0 < 0) OP0 = ~OP0), with result to TARGET if convenient.
3756 (TARGET may be NULL_RTX.) The return value says where the result
3757 actually is to be found.
3759 MODE is the mode of the operand; the mode of the result is
3760 different but can be deduced from MODE. */
3762 rtx
3764 {
3765 rtx temp;
3767 /* Not applicable for floating point modes. */
3771 /* If we have a MAX insn, we can do this as MAX (x, ~x). */
3773 {
3779 OPTAB_WIDEN);
3785 }
3787 /* If this machine has expensive jumps, we can do one's complement
3788 absolute value of X as (((signed) x >> (W-1)) ^ x). */
3790 scalar_int_mode int_mode;
3794 {
3800 OPTAB_LIB_WIDEN);
3804 }
3807 }
3809 /* A subroutine of expand_copysign, perform the copysign operation using the
3810 abs and neg primitives advertised to exist on the target. The assumption
3811 is that we have a split register file, and leaving op0 in fp registers,
3812 and not playing with subregs so much, will help the register allocator. */
3814 static rtx
3817 {
3818 scalar_int_mode imode;
3820 rtx sign;
3826 /* Check if the back end provides an insn that handles signbit for the
3827 argument's mode. */
3830 {
3834 }
3835 else
3836 {
3838 {
3842 }
3843 else
3844 {
3850 else
3854 }
3860 }
3863 {
3868 }
3869 else
3870 {
3873 else
3875 }
3882 else
3890 }
3893 /* A subroutine of expand_copysign, perform the entire copysign operation
3894 with integer bitmasks. BITPOS is the position of the sign bit; OP0_IS_ABS
3895 is true if op0 is known to have its sign bit clear. */
3897 static rtx
3900 {
3901 scalar_int_mode imode;
3903 rtx temp;
3907 {
3912 }
3913 else
3914 {
3919 else
3923 }
3936 {
3940 {
3945 {
3947 op0_piece
3960 }
3961 else
3963 }
3969 }
3970 else
3971 {
3985 }
3988 }
3990 /* Expand the C99 copysign operation. OP0 and OP1 must be the same
3991 scalar floating point mode. Return NULL if we do not know how to
3992 expand the operation inline. */
3994 rtx
3996 {
3997 scalar_float_mode mode;
4000 rtx temp;
4005 /* First try to do it with a special instruction. */
4017 {
4021 }
4027 {
4032 }
4038 }
4039 \f
4040 /* Generate an instruction whose insn-code is INSN_CODE,
4041 with two operands: an output TARGET and an input OP0.
4042 TARGET *must* be nonzero, and the output is always stored there.
4043 CODE is an rtx code such that (CODE OP0) is an rtx that describes
4044 the value that is stored into TARGET.
4046 Return false if expansion failed. */
4048 bool
4051 {
4071 }
4072 /* Generate an instruction whose insn-code is INSN_CODE,
4073 with two operands: an output TARGET and an input OP0.
4074 TARGET *must* be nonzero, and the output is always stored there.
4075 CODE is an rtx code such that (CODE OP0) is an rtx that describes
4076 the value that is stored into TARGET. */
4078 void
4080 {
4083 }
4084 \f
4085 struct no_conflict_data
4086 {
4087 rtx target;
4090 };
4092 /* Called via note_stores by emit_libcall_block. Set P->must_stay if
4093 the currently examined clobber / store has to stay in the list of
4094 insns that constitute the actual libcall block. */
4095 static void
4097 {
4100 /* If this inns directly contributes to setting the target, it must stay. */
4103 /* If we haven't committed to keeping any other insns in the list yet,
4104 there is nothing more to check. */
4107 /* If this insn sets / clobbers a register that feeds one of the insns
4108 already in the list, this insn has to stay too. */
4112 /* Likewise if this insn depends on a register set by a previous
4113 insn in the list, or if it sets a result (presumably a hard
4114 register) that is set or clobbered by a previous insn.
4115 N.B. the modified_*_p (SET_DEST...) tests applied to a MEM
4116 SET_DEST perform the former check on the address, and the latter
4117 check on the MEM. */
4124 }
4126 \f
4127 /* Emit code to make a call to a constant function or a library call.
4129 INSNS is a list containing all insns emitted in the call.
4130 These insns leave the result in RESULT. Our block is to copy RESULT
4131 to TARGET, which is logically equivalent to EQUIV.
4133 We first emit any insns that set a pseudo on the assumption that these are
4134 loading constants into registers; doing so allows them to be safely cse'ed
4135 between blocks. Then we emit all the other insns in the block, followed by
4136 an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL
4137 note with an operand of EQUIV. */
4139 static void
4142 {
4146 /* If this is a reg with REG_USERVAR_P set, then it could possibly turn
4147 into a MEM later. Protect the libcall block from this change. */
4151 /* If we're using non-call exceptions, a libcall corresponding to an
4152 operation that may trap may also trap. */
4153 /* ??? See the comment in front of make_reg_eh_region_note. */
4156 {
4159 {
4162 {
4166 }
4167 }
4168 }
4169 else
4170 {
4171 /* Look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION
4172 reg note to indicate that this call cannot throw or execute a nonlocal
4173 goto (unless there is already a REG_EH_REGION note, in which case
4174 we update it). */
4178 }
4180 /* First emit all insns that set pseudos. Remove them from the list as
4181 we go. Avoid insns that set pseudos which were referenced in previous
4182 insns. These can be generated by move_by_pieces, for example,
4183 to update an address. Similarly, avoid insns that reference things
4184 set in previous insns. */
4187 {
4194 {
4203 {
4206 else
4213 }
4214 }
4216 /* Some ports use a loop to copy large arguments onto the stack.
4217 Don't move anything outside such a loop. */
4220 }
4222 /* Write the remaining insns followed by the final copy. */
4224 {
4228 }
4236 }
4238 void
4240 {
4242 }
4243 \f
4244 /* Nonzero if we can perform a comparison of mode MODE straightforwardly.
4245 PURPOSE describes how this comparison will be used. CODE is the rtx
4246 comparison code we will be using.
4248 ??? Actually, CODE is slightly weaker than that. A target is still
4249 required to implement all of the normal bcc operations, but not
4250 required to implement all (or any) of the unordered bcc operations. */
4252 int
4255 {
4256 rtx test;
4258 do
4259 {
4276 }
4280 }
4282 /* Return whether RTL code CODE corresponds to an unsigned optab. */
4284 static bool
4286 {
4288 }
4290 /* Return whether the backend-emitted comparison for code CODE, comparing
4291 operands of mode VALUE_MODE and producing a result with MASK_MODE, matches
4292 operand OPNO of pattern ICODE. */
4294 static bool
4297 machine_mode value_mode)
4298 {
4303 }
4305 /* Return whether the backend can emit a vector comparison (vec_cmp/vec_cmpu)
4306 for code CODE, comparing operands of mode VALUE_MODE and producing a result
4307 with MASK_MODE. */
4309 bool
4311 machine_mode mask_mode)
4312 {
4313 enum insn_code icode
4319 }
4321 /* Return whether the backend can emit a vector comparison (vcond/vcondu) for
4322 code CODE, comparing operands of mode CMP_OP_MODE and producing a result
4323 with VALUE_MODE. */
4325 bool
4327 machine_mode cmp_op_mode)
4328 {
4329 enum insn_code icode
4335 }
4337 /* Return whether the backend can emit vector set instructions for inserting
4338 element into vector at variable index position. */
4340 bool
4342 {
4356 }
4358 /* This function is called when we are going to emit a compare instruction that
4359 compares the values found in X and Y, using the rtl operator COMPARISON.
4361 If they have mode BLKmode, then SIZE specifies the size of both operands.
4363 UNSIGNEDP nonzero says that the operands are unsigned;
4364 this matters if they need to be widened (as given by METHODS).
4366 *PTEST is where the resulting comparison RTX is returned or NULL_RTX
4367 if we failed to produce one.
4369 *PMODE is the mode of the inputs (in case they are const_int).
4371 This function performs all the setup necessary so that the caller only has
4372 to emit a single comparison insn. This setup can involve doing a BLKmode
4373 comparison or emitting a library call to perform the comparison if no insn
4374 is available to handle it.
4375 The values which are passed in through pointers can be modified; the caller
4376 should perform the comparison on the modified values. Constant
4377 comparisons must have already been folded. */
4379 static void
4383 {
4386 machine_mode cmp_mode;
4389 /* The other methods are not needed. */
4396 /* If we are optimizing, force expensive constants into a register. */
4409 /* Don't let both operands fail to indicate the mode. */
4415 /* Handle all BLKmode compares. */
4418 {
4419 machine_mode result_mode;
4421 rtx result;
4422 rtx opalign
4427 /* Try to use a memory block compare insn - either cmpstr
4428 or cmpmem will do. */
4429 opt_scalar_int_mode cmp_mode_iter;
4431 {
4441 /* Must make sure the size fits the insn's mode. */
4456 }
4461 /* Otherwise call a library function. */
4469 }
4471 /* Don't allow operands to the compare to trap, as that can put the
4472 compare and branch in different basic blocks. */
4474 {
4481 }
4484 {
4491 }
4496 {
4501 {
4508 {
4514 }
4516 }
4520 }
4526 {
4527 /* Small trick if UNORDERED isn't implemented by the hardware. */
4529 {
4534 }
4537 }
4538 else
4539 {
4540 rtx result;
4541 machine_mode ret_mode;
4543 /* Handle a libcall just for the mode we are using. */
4547 /* If we want unsigned, and this mode has a distinct unsigned
4548 comparison routine, use that. */
4550 {
4554 }
4560 /* There are two kinds of comparison routines. Biased routines
4561 return 0/1/2, and unbiased routines return -1/0/1. Other parts
4562 of gcc expect that the comparison operation is equivalent
4563 to the modified comparison. For signed comparisons compare the
4564 result against 1 in the biased case, and zero in the unbiased
4565 case. For unsigned comparisons always compare against 1 after
4566 biasing the unbiased result by adding 1. This gives us a way to
4567 represent LTU.
4568 The comparisons in the fixed-point helper library are always
4569 biased. */
4574 {
4577 else
4579 }
4584 }
4588 fail:
4590 }
4592 /* Before emitting an insn with code ICODE, make sure that X, which is going
4593 to be used for operand OPNUM of the insn, is converted from mode MODE to
4594 WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and
4595 that it is accepted by the operand predicate. Return the new value. */
4597 rtx
4600 {
4605 {
4612 }
4615 }
4617 /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know
4618 we can do the branch. */
4620 static void
4622 profile_probability prob)
4623 {
4624 machine_mode optab_mode;
4639 && insn
4644 }
4646 /* Generate code to compare X with Y so that the condition codes are
4647 set and to jump to LABEL if the condition is true. If X is a
4648 constant and Y is not a constant, then the comparison is swapped to
4649 ensure that the comparison RTL has the canonical form.
4651 UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they
4652 need to be widened. UNSIGNEDP is also used to select the proper
4653 branch condition code.
4655 If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y.
4657 MODE is the mode of the inputs (in case they are const_int).
4659 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
4660 It will be potentially converted into an unsigned variant based on
4661 UNSIGNEDP to select a proper jump instruction.
4663 PROB is the probability of jumping to LABEL. */
4665 void
4668 profile_probability prob)
4669 {
4671 rtx test;
4673 /* Swap operands and condition to ensure canonical RTL. */
4676 {
4679 }
4681 /* If OP0 is still a constant, then both X and Y must be constants
4682 or the opposite comparison is not supported. Force X into a register
4683 to create canonical RTL. */
4693 }
4695 \f
4696 /* Emit a library call comparison between floating point X and Y.
4697 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */
4699 static void
4702 {
4706 machine_mode mode;
4715 {
4722 {
4726 }
4730 {
4734 }
4735 }
4740 {
4743 }
4745 /* Attach a REG_EQUAL note describing the semantics of the libcall to
4746 the RTL. The allows the RTL optimizers to delete the libcall if the
4747 condition can be determined at compile-time. */
4750 {
4753 }
4754 else
4755 {
4757 {
4790 }
4791 }
4794 {
4799 }
4800 else
4801 {
4806 }
4821 else
4825 }
4826 \f
4827 /* Generate code to indirectly jump to a location given in the rtx LOC. */
4829 void
4831 {
4834 else
4835 {
4840 }
4841 }
4842 \f
4844 /* Emit a conditional move instruction if the machine supports one for that
4845 condition and machine mode.
4847 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4848 the mode to use should they be constants. If it is VOIDmode, they cannot
4849 both be constants.
4851 OP2 should be stored in TARGET if the comparison is true, otherwise OP3
4852 should be stored there. MODE is the mode to use should they be constants.
4853 If it is VOIDmode, they cannot both be constants.
4855 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4856 is not supported. */
4858 rtx
4862 {
4863 rtx comparison;
4868 /* If the two source operands are identical, that's just a move. */
4871 {
4877 }
4879 /* If one operand is constant, make it the second one. Only do this
4880 if the other operand is not constant as well. */
4883 {
4886 }
4888 /* get_condition will prefer to generate LT and GT even if the old
4889 comparison was against zero, so undo that canonicalization here since
4890 comparisons against zero are cheaper. */
4906 {
4910 }
4924 {
4926 comparison =
4930 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4931 punt and let the caller figure out how best to deal with this
4932 situation. */
4934 {
4935 saved_pending_stack_adjust save;
4944 {
4949 }
4952 }
4957 /* If the preferred op2/op3 order is not usable, retry with other
4958 operand order, perhaps it will expand successfully. */
4963 NULL))
4966 else
4969 }
4970 }
4972 /* Helper function that, in addition to COMPARISON, also tries
4973 the reversed REV_COMPARISON with swapped OP2 and OP3. As opposed
4974 to when we pass the specific constituents of a comparison, no
4975 additional insns are emitted for it. It might still be necessary
4976 to emit more than one insn for the final conditional move, though. */
4978 rtx
4981 {
4988 }
4990 /* Helper for emitting a conditional move. */
4992 static rtx
4995 {
5001 /* If the two source operands are identical, that's just a move.
5002 As the comparison comes in non-canonicalized, we must make
5003 sure not to discard any possible side effects. If there are
5004 side effects, just let the target handle it. */
5006 {
5012 }
5033 {
5037 }
5040 }
5043 /* Emit a conditional negate or bitwise complement using the
5044 negcc or notcc optabs if available. Return NULL_RTX if such operations
5045 are not available. Otherwise return the RTX holding the result.
5046 TARGET is the desired destination of the result. COMP is the comparison
5047 on which to negate. If COND is true move into TARGET the negation
5048 or bitwise complement of OP1. Otherwise move OP2 into TARGET.
5049 CODE is either NEG or NOT. MODE is the machine mode in which the
5050 operation is performed. */
5052 rtx
5055 rtx op2)
5056 {
5062 else
5082 {
5087 }
5090 }
5092 /* Emit a conditional addition instruction if the machine supports one for that
5093 condition and machine mode.
5095 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
5096 the mode to use should they be constants. If it is VOIDmode, they cannot
5097 both be constants.
5099 OP2 should be stored in TARGET if the comparison is false, otherwise OP2+OP3
5100 should be stored there. MODE is the mode to use should they be constants.
5101 If it is VOIDmode, they cannot both be constants.
5103 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
5104 is not supported. */
5106 rtx
5110 {
5111 rtx comparison;
5115 /* If one operand is constant, make it the second one. Only do this
5116 if the other operand is not constant as well. */
5119 {
5122 }
5124 /* get_condition will prefer to generate LT and GT even if the old
5125 comparison was against zero, so undo that canonicalization here since
5126 comparisons against zero are cheaper. */
5149 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
5150 return NULL and let the caller figure out how best to deal with this
5151 situation. */
5161 {
5169 {
5173 }
5174 }
5177 }
5178 \f
5179 /* These functions attempt to generate an insn body, rather than
5180 emitting the insn, but if the gen function already emits them, we
5181 make no attempt to turn them back into naked patterns. */
5183 /* Generate and return an insn body to add Y to X. */
5185 rtx_insn *
5187 {
5195 }
5197 /* Generate and return an insn body to add r1 and c,
5198 storing the result in r0. */
5200 rtx_insn *
5202 {
5212 }
5214 int
5216 {
5232 }
5234 /* Generate and return an insn body to add Y to X. */
5236 rtx_insn *
5238 {
5246 }
5248 /* Return true if the target implements an addptr pattern and X, Y,
5249 and Z are valid for the pattern predicates. */
5251 int
5253 {
5269 }
5271 /* Generate and return an insn body to subtract Y from X. */
5273 rtx_insn *
5275 {
5283 }
5285 /* Generate and return an insn body to subtract r1 and c,
5286 storing the result in r0. */
5288 rtx_insn *
5290 {
5300 }
5302 int
5304 {
5320 }
5321 \f
5322 /* Generate the body of an insn to extend Y (with mode MFROM)
5323 into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */
5325 rtx_insn *
5328 {
5331 }
5332 \f
5333 /* Generate code to convert FROM to floating point
5334 and store in TO. FROM must be fixed point and not VOIDmode.
5335 UNSIGNEDP nonzero means regard FROM as unsigned.
5336 Normally this is done by correcting the final value
5337 if it is negative. */
5339 void
5341 {
5348 /* Crash now, because we won't be able to decide which mode to use. */
5351 /* Look for an insn to do the conversion. Do it in the specified
5352 modes if possible; otherwise convert either input, output or both to
5353 wider mode. If the integer mode is wider than the mode of FROM,
5354 we can do the conversion signed even if the input is unsigned. */
5358 {
5368 {
5374 }
5377 {
5390 }
5391 }
5393 /* Unsigned integer, and no way to convert directly. Convert as signed,
5394 then unconditionally adjust the result. */
5396 && can_do_signed
5399 {
5400 opt_scalar_mode fmode_iter;
5402 rtx temp;
5403 REAL_VALUE_TYPE offset;
5405 /* Look for a usable floating mode FMODE wider than the source and at
5406 least as wide as the target. Using FMODE will avoid rounding woes
5407 with unsigned values greater than the signed maximum value. */
5410 {
5415 }
5418 {
5419 /* There is no such mode. Pretend the target is wide enough. */
5422 /* Avoid double-rounding when TO is narrower than FROM. */
5425 {
5426 rtx temp1;
5429 /* Don't use TARGET if it isn't a register, is a hard register,
5430 or is the wrong mode. */
5439 /* Test whether the sign bit is set. */
5443 /* The sign bit is not set. Convert as signed. */
5448 /* The sign bit is set.
5449 Convert to a usable (positive signed) value by shifting right
5450 one bit, while remembering if a nonzero bit was shifted
5451 out; i.e., compute (from & 1) | (from >> 1). */
5458 OPTAB_LIB_WIDEN);
5461 /* Multiply by 2 to undo the shift above. */
5470 }
5471 }
5473 /* If we are about to do some arithmetic to correct for an
5474 unsigned operand, do it in a pseudo-register. */
5480 /* Convert as signed integer to floating. */
5483 /* If FROM is negative (and therefore TO is negative),
5484 correct its value by 2**bitwidth. */
5501 }
5503 /* No hardware instruction available; call a library routine. */
5504 {
5505 rtx libfunc;
5507 rtx value;
5526 }
5528 done:
5530 /* Copy result to requested destination
5531 if we have been computing in a temp location. */
5534 {
5537 else
5539 }
5540 }
5541 \f
5542 /* Generate code to convert FROM to fixed point and store in TO. FROM
5543 must be floating point. */
5545 void
5547 {
5551 opt_scalar_mode fmode_iter;
5554 /* We first try to find a pair of modes, one real and one integer, at
5555 least as wide as FROM and TO, respectively, in which we can open-code
5556 this conversion. If the integer mode is wider than the mode of TO,
5557 we can do the conversion either signed or unsigned. */
5561 {
5569 {
5576 {
5580 }
5587 {
5591 }
5593 }
5594 }
5596 /* For an unsigned conversion, there is one more way to do it.
5597 If we have a signed conversion, we generate code that compares
5598 the real value to the largest representable positive number. If if
5599 is smaller, the conversion is done normally. Otherwise, subtract
5600 one plus the highest signed number, convert, and add it back.
5602 We only need to check all real modes, since we know we didn't find
5603 anything with a wider integer mode.
5605 This code used to extend FP value into mode wider than the destination.
5606 This is needed for decimal float modes which cannot accurately
5607 represent one plus the highest signed number of the same size, but
5608 not for binary modes. Consider, for instance conversion from SFmode
5609 into DImode.
5611 The hot path through the code is dealing with inputs smaller than 2^63
5612 and doing just the conversion, so there is no bits to lose.
5614 In the other path we know the value is positive in the range 2^63..2^64-1
5615 inclusive. (as for other input overflow happens and result is undefined)
5616 So we know that the most important bit set in mantissa corresponds to
5617 2^63. The subtraction of 2^63 should not generate any rounding as it
5618 simply clears out that bit. The rest is trivial. */
5620 scalar_int_mode to_mode;
5625 {
5631 {
5633 REAL_VALUE_TYPE offset;
5634 rtx limit;
5647 /* See if we need to do the subtraction. */
5652 /* If not, do the signed "fix" and branch around fixup code. */
5657 /* Otherwise, subtract 2**(N-1), convert to signed number,
5658 then add 2**(N-1). Do the addition using XOR since this
5659 will often generate better code. */
5665 gen_int_mode
5667 to_mode),
5676 {
5677 /* Make a place for a REG_NOTE and add it. */
5682 to);
5683 }
5686 }
5687 }
5689 /* We can't do it with an insn, so use a library call. But first ensure
5690 that the mode of TO is at least as wide as SImode, since those are the
5691 only library calls we know about. */
5694 {
5698 }
5699 else
5700 {
5702 rtx value;
5703 rtx libfunc;
5719 }
5722 {
5725 else
5727 }
5728 }
5731 /* Promote integer arguments for a libcall if necessary.
5732 emit_library_call_value cannot do the promotion because it does not
5733 know if it should do a signed or unsigned promotion. This is because
5734 there are no tree types defined for libcalls. */
5736 static rtx
5738 {
5739 scalar_int_mode mode;
5740 machine_mode arg_mode;
5742 {
5743 /* If we need to promote the integer function argument we need to do
5744 it here instead of inside emit_library_call_value because in
5745 emit_library_call_value we don't know if we should do a signed or
5746 unsigned promotion. */
5753 }
5755 }
5757 /* Generate code to convert FROM or TO a fixed-point.
5758 If UINTP is true, either TO or FROM is an unsigned integer.
5759 If SATP is true, we need to saturate the result. */
5761 void
5763 {
5766 convert_optab tab;
5770 rtx value;
5771 rtx libfunc;
5774 {
5777 }
5780 {
5783 }
5784 else
5785 {
5788 }
5791 {
5794 }
5810 }
5812 /* Generate code to convert FROM to fixed point and store in TO. FROM
5813 must be floating point, TO must be signed. Use the conversion optab
5814 TAB to do the conversion. */
5816 bool
5818 {
5823 /* We first try to find a pair of modes, one real and one integer, at
5824 least as wide as FROM and TO, respectively, in which we can open-code
5825 this conversion. If the integer mode is wider than the mode of TO,
5826 we can do the conversion either signed or unsigned. */
5830 {
5834 {
5843 {
5846 }
5850 }
5851 }
5854 }
5855 \f
5856 /* Report whether we have an instruction to perform the operation
5857 specified by CODE on operands of mode MODE. */
5858 int
5860 {
5864 }
5866 /* Print information about the current contents of the optabs on
5867 STDERR. */
5869 DEBUG_FUNCTION void
5871 {
5874 /* Dump the arithmetic optabs. */
5877 {
5880 {
5886 }
5887 }
5889 /* Dump the conversion optabs. */
5893 {
5897 {
5904 }
5905 }
5906 }
5908 /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition
5909 CODE. Return 0 on failure. */
5911 rtx_insn *
5913 {
5917 rtx trap_rtx;
5926 /* Some targets only accept a zero trap code. */
5936 else
5938 tcode);
5940 /* If that failed, then give up. */
5942 {
5945 }
5951 }
5953 /* Return rtx code for TCODE or UNKNOWN. Use UNSIGNEDP to select signed
5954 or unsigned operation code. */
5956 enum rtx_code
5958 {
5961 {
6017 }
6019 }
6021 /* Return rtx code for TCODE. Use UNSIGNEDP to select signed
6022 or unsigned operation code. */
6024 enum rtx_code
6026 {
6030 }
6032 /* Return a comparison rtx of mode CMP_MODE for COND. Use UNSIGNEDP to
6033 select signed or unsigned operators. OPNO holds the index of the
6034 first comparison operand for insn ICODE. Do not generate the
6035 compare instruction itself. */
6037 rtx
6041 {
6049 /* Expand operands. For vector types with scalar modes, e.g. where int64x1_t
6050 has mode DImode, this can produce a constant RTX of mode VOIDmode; in such
6051 cases, use the original mode. */
6053 EXPAND_STACK_PARM);
6059 EXPAND_STACK_PARM);
6069 }
6071 /* Check if vec_perm mask SEL is a constant equivalent to a shift of
6072 the first vec_perm operand, assuming the second operand (for left shift
6073 first operand) is a constant vector of zeros. Return the shift distance
6074 in bits if so, or NULL_RTX if the vec_perm is not a shift. MODE is the
6075 mode of the value being shifted. SHIFT_OPTAB is vec_shr_optab for right
6076 shift or vec_shl_optab for left shift. */
6077 static rtx
6079 optab shift_optab)
6080 {
6087 {
6093 {
6095 {
6099 }
6104 }
6109 }
6111 {
6116 {
6118 /* Indices into the second vector are all equivalent. */
6123 }
6124 }
6127 }
6129 /* A subroutine of expand_vec_perm_var for expanding one vec_perm insn. */
6131 static rtx
6134 {
6144 /* Make an effort to preserve v0 == v1. The target expander is able to
6145 rely on this to determine if we're permuting a single input operand. */
6147 {
6155 }
6156 else
6157 {
6160 }
6165 }
6167 /* Implement a permutation of vectors v0 and v1 using the permutation
6168 vector in SEL and return the result. Use TARGET to hold the result
6169 if nonnull and convenient.
6171 MODE is the mode of the vectors being permuted (V0 and V1). SEL_MODE
6172 is the TYPE_MODE associated with SEL, or BLKmode if SEL isn't known
6173 to have a particular mode. */
6175 rtx
6178 rtx target)
6179 {
6183 /* Set QIMODE to a different vector mode with byte elements.
6184 If no such mode, or if MODE already has byte elements, use VOIDmode. */
6185 machine_mode qimode;
6192 /* Always specify two input vectors here and leave the target to handle
6193 cases in which the inputs are equal. Not all backends can cope with
6194 the single-input representation when testing for a double-input
6195 target instruction. */
6198 /* See if this can be handled with a vec_shr or vec_shl. We only do this
6199 if the second (for vec_shr) or first (for vec_shl) vector is all
6200 zeroes. */
6208 {
6211 }
6213 {
6218 }
6220 {
6223 {
6228 {
6234 }
6236 {
6243 }
6244 }
6245 }
6248 {
6255 indices))
6257 }
6259 /* Fall back to a constant byte-based permutation. */
6260 vec_perm_indices qimode_indices;
6263 {
6272 }
6279 /* Otherwise expand as a fully variable permuation. */
6281 /* The optabs are only defined for selectors with the same width
6282 as the values being permuted. */
6283 machine_mode required_sel_mode;
6285 {
6288 }
6290 /* We know that it is semantically valid to treat SEL as having SEL_MODE.
6291 If that isn't the mode we want then we need to prove that using
6292 REQUIRED_SEL_MODE is OK. */
6294 {
6296 {
6299 }
6301 }
6305 {
6310 }
6314 {
6317 {
6322 }
6323 }
6327 }
6329 /* Implement a permutation of vectors v0 and v1 using the permutation
6330 vector in SEL and return the result. Use TARGET to hold the result
6331 if nonnull and convenient.
6333 MODE is the mode of the vectors being permuted (V0 and V1).
6334 SEL must have the integer equivalent of MODE and is known to be
6335 unsuitable for permutes with a constant permutation vector. */
6337 rtx
6339 {
6351 {
6355 }
6357 /* As a special case to aid several targets, lower the element-based
6358 permutation to a byte-based permutation and try again. */
6359 machine_mode qimode;
6367 /* Multiply each element by its byte size. */
6372 else
6378 /* Broadcast the low byte each element into each of its bytes.
6379 The encoding has U interleaved stepped patterns, one for each
6380 byte of an element. */
6390 /* Add the byte offset to each byte element. */
6391 /* Note that the definition of the indicies here is memory ordering,
6392 so there should be no difference between big and little endian. */
6407 }
6409 /* Generate VEC_SERIES_EXPR <OP0, OP1>, returning a value of mode VMODE.
6410 Use TARGET for the result if nonnull and convenient. */
6412 rtx
6414 {
6428 }
6430 /* Generate insns for a vector comparison into a mask. */
6432 rtx
6434 {
6437 rtx comparison;
6439 machine_mode vmode;
6453 {
6458 }
6468 }
6470 /* Expand a highpart multiply. */
6472 rtx
6475 {
6479 machine_mode wmode;
6485 {
6491 OPTAB_LIB_WIDEN);
6504 }
6524 vec_perm_builder sel;
6526 {
6527 /* The encoding has 2 interleaved stepped patterns. */
6532 }
6533 else
6534 {
6535 /* The encoding has a single interleaved stepped pattern. */
6539 }
6542 }
6543 \f
6544 /* Helper function to find the MODE_CC set in a sync_compare_and_swap
6545 pattern. */
6547 static void
6549 {
6552 {
6556 }
6557 }
6559 /* This is a helper function for the other atomic operations. This function
6560 emits a loop that contains SEQ that iterates until a compare-and-swap
6561 operation at the end succeeds. MEM is the memory to be modified. SEQ is
6562 a set of instructions that takes a value from OLD_REG as an input and
6563 produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be
6564 set to the current contents of MEM. After SEQ, a compare-and-swap will
6565 attempt to update MEM with NEW_REG. The function returns true when the
6566 loop was generated successfully. */
6568 static bool
6570 {
6575 /* The loop we want to generate looks like
6577 cmp_reg = mem;
6578 label:
6579 old_reg = cmp_reg;
6580 seq;
6581 (success, cmp_reg) = compare-and-swap(mem, old_reg, new_reg)
6582 if (success)
6583 goto label;
6585 Note that we only do the plain load from memory once. Subsequent
6586 iterations use the value loaded by the compare-and-swap pattern. */
6601 MEMMODEL_RELAXED))
6607 /* Mark this jump predicted not taken. */
6612 }
6615 /* This function tries to emit an atomic_exchange intruction. VAL is written
6616 to *MEM using memory model MODEL. The previous contents of *MEM are returned,
6617 using TARGET if possible. */
6619 static rtx
6621 {
6625 /* If the target supports the exchange directly, great. */
6628 {
6637 }
6640 }
6642 /* This function tries to implement an atomic exchange operation using
6643 __sync_lock_test_and_set. VAL is written to *MEM using memory model MODEL.
6644 The previous contents of *MEM are returned, using TARGET if possible.
6645 Since this instructionn is an acquire barrier only, stronger memory
6646 models may require additional barriers to be emitted. */
6648 static rtx
6651 {
6658 /* Legacy sync_lock_test_and_set is an acquire barrier. If the pattern
6659 exists, and the memory model is stronger than acquire, add a release
6660 barrier before the instruction. */
6666 {
6673 }
6675 /* If an external test-and-set libcall is provided, use that instead of
6676 any external compare-and-swap that we might get from the compare-and-
6677 swap-loop expansion later. */
6679 {
6682 {
6683 rtx addr;
6689 }
6690 }
6692 /* If the test_and_set can't be emitted, eliminate any barrier that might
6693 have been emitted. */
6696 }
6698 /* This function tries to implement an atomic exchange operation using a
6699 compare_and_swap loop. VAL is written to *MEM. The previous contents of
6700 *MEM are returned, using TARGET if possible. No memory model is required
6701 since a compare_and_swap loop is seq-cst. */
6703 static rtx
6705 {
6709 {
6714 }
6717 }
6719 /* This function tries to implement an atomic test-and-set operation
6720 using the atomic_test_and_set instruction pattern. A boolean value
6721 is returned from the operation, using TARGET if possible. */
6723 static rtx
6725 {
6726 machine_mode pat_bool_mode;
6732 /* While we always get QImode from __atomic_test_and_set, we get
6733 other memory modes from __sync_lock_test_and_set. Note that we
6734 use no endian adjustment here. This matches the 4.6 behavior
6735 in the Sparc backend. */
6749 }
6751 /* This function expands the legacy _sync_lock test_and_set operation which is
6752 generally an atomic exchange. Some limited targets only allow the
6753 constant 1 to be stored. This is an ACQUIRE operation.
6755 TARGET is an optional place to stick the return value.
6756 MEM is where VAL is stored. */
6758 rtx
6760 {
6761 rtx ret;
6763 /* Try an atomic_exchange first. */
6769 MEMMODEL_SYNC_ACQUIRE);
6777 /* If there are no other options, try atomic_test_and_set if the value
6778 being stored is 1. */
6783 }
6785 /* This function expands the atomic test_and_set operation:
6786 atomically store a boolean TRUE into MEM and return the previous value.
6788 MEMMODEL is the memory model variant to use.
6789 TARGET is an optional place to stick the return value. */
6791 rtx
6793 {
6801 /* Be binary compatible with non-default settings of trueval, and different
6802 cpu revisions. E.g. one revision may have atomic-test-and-set, but
6803 another only has atomic-exchange. */
6805 {
6808 }
6809 else
6810 {
6813 }
6815 /* Try the atomic-exchange optab... */
6818 /* ... then an atomic-compare-and-swap loop ... */
6822 /* ... before trying the vaguely defined legacy lock_test_and_set. */
6826 /* Recall that the legacy lock_test_and_set optab was allowed to do magic
6827 things with the value 1. Thus we try again without trueval. */
6831 /* Failing all else, assume a single threaded environment and simply
6832 perform the operation. */
6834 {
6835 /* If the result is ignored skip the move to target. */
6841 }
6843 /* Recall that have to return a boolean value; rectify if trueval
6844 is not exactly one. */
6849 }
6851 /* This function expands the atomic exchange operation:
6852 atomically store VAL in MEM and return the previous value in MEM.
6854 MEMMODEL is the memory model variant to use.
6855 TARGET is an optional place to stick the return value. */
6857 rtx
6859 {
6861 rtx ret;
6863 /* If loads are not atomic for the required size and we are not called to
6864 provide a __sync builtin, do not do anything so that we stay consistent
6865 with atomic loads of the same size. */
6871 /* Next try a compare-and-swap loop for the exchange. */
6876 }
6878 /* This function expands the atomic compare exchange operation:
6880 *PTARGET_BOOL is an optional place to store the boolean success/failure.
6881 *PTARGET_OVAL is an optional place to store the old value from memory.
6882 Both target parameters may be NULL or const0_rtx to indicate that we do
6883 not care about that return value. Both target parameters are updated on
6884 success to the actual location of the corresponding result.
6886 MEMMODEL is the memory model variant to use.
6888 The return value of the function is true for success. */
6890 bool
6895 {
6900 rtx libfunc;
6902 /* If loads are not atomic for the required size and we are not called to
6903 provide a __sync builtin, do not do anything so that we stay consistent
6904 with atomic loads of the same size. */
6908 /* Load expected into a register for the compare and swap. */
6912 /* Make sure we always have some place to put the return oldval.
6913 Further, make sure that place is distinct from the input expected,
6914 just in case we need that path down below. */
6925 {
6931 /* Make sure we always have a place for the bool operand. */
6937 /* Emit the compare_and_swap. */
6947 {
6948 /* Return success/failure. */
6952 }
6953 }
6955 /* Otherwise fall back to the original __sync_val_compare_and_swap
6956 which is always seq-cst. */
6959 {
6960 rtx cc_reg;
6971 /* If the caller isn't interested in the boolean return value,
6972 skip the computation of it. */
6976 /* Otherwise, work out if the compare-and-swap succeeded. */
6981 {
6985 }
6987 }
6989 /* Also check for library support for __sync_val_compare_and_swap. */
6992 {
6999 /* Compute the boolean return value only if requested. */
7002 else
7004 }
7006 /* Failure. */
7009 success_bool_from_val:
7012 success:
7013 /* Make sure that the oval output winds up where the caller asked. */
7019 }
7021 /* Generate asm volatile("" : : : "memory") as the memory blockage. */
7023 static void
7025 {
7038 }
7040 /* Do not propagate memory accesses across this point. */
7042 static void
7044 {
7047 else
7049 }
7051 /* Generate asm volatile("" : : : "memory") as a memory blockage, at the
7052 same time clobbering the register set specified by REGS. */
7054 void
7056 {
7062 num_of_regs++;
7079 {
7083 {
7085 j++;
7086 }
7088 }
7091 }
7093 /* This routine will either emit the mem_thread_fence pattern or issue a
7094 sync_synchronize to generate a fence for memory model MEMMODEL. */
7096 void
7098 {
7102 {
7105 }
7110 else
7112 }
7114 /* Emit a signal fence with given memory model. */
7116 void
7118 {
7119 /* No machine barrier is required to implement a signal fence, but
7120 a compiler memory barrier must be issued, except for relaxed MM. */
7123 }
7125 /* This function expands the atomic load operation:
7126 return the atomically loaded value in MEM.
7128 MEMMODEL is the memory model variant to use.
7129 TARGET is an option place to stick the return value. */
7131 rtx
7133 {
7137 /* If the target supports the load directly, great. */
7140 {
7150 {
7154 }
7156 }
7158 /* If the size of the object is greater than word size on this target,
7159 then we assume that a load will not be atomic. We could try to
7160 emulate a load with a compare-and-swap operation, but the store that
7161 doing this could result in would be incorrect if this is a volatile
7162 atomic load or targetting read-only-mapped memory. */
7164 /* If there is no atomic load, leave the library call. */
7167 /* Otherwise assume loads are atomic, and emit the proper barriers. */
7171 /* For SEQ_CST, emit a barrier before the load. */
7177 /* Emit the appropriate barrier after the load. */
7181 }
7183 /* This function expands the atomic store operation:
7184 Atomically store VAL in MEM.
7185 MEMMODEL is the memory model variant to use.
7186 USE_RELEASE is true if __sync_lock_release can be used as a fall back.
7187 function returns const0_rtx if a pattern was emitted. */
7189 rtx
7191 {
7196 /* If the target supports the store directly, great. */
7199 {
7207 {
7211 }
7213 }
7215 /* If using __sync_lock_release is a viable alternative, try it.
7216 Note that this will not be set to true if we are expanding a generic
7217 __atomic_store_n. */
7219 {
7222 {
7226 {
7227 /* lock_release is only a release barrier. */
7231 }
7232 }
7233 }
7235 /* If the size of the object is greater than word size on this target,
7236 a default store will not be atomic. */
7238 {
7239 /* If loads are atomic or we are called to provide a __sync builtin,
7240 we can try a atomic_exchange and throw away the result. Otherwise,
7241 don't do anything so that we do not create an inconsistency between
7242 loads and stores. */
7244 {
7248 val);
7251 }
7253 }
7255 /* Otherwise assume stores are atomic, and emit the proper barriers. */
7260 /* For SEQ_CST, also emit a barrier after the store. */
7265 }
7268 /* Structure containing the pointers and values required to process the
7269 various forms of the atomic_fetch_op and atomic_op_fetch builtins. */
7271 struct atomic_op_functions
7272 {
7273 direct_optab mem_fetch_before;
7274 direct_optab mem_fetch_after;
7275 direct_optab mem_no_result;
7276 optab fetch_before;
7277 optab fetch_after;
7278 direct_optab no_result;
7280 };
7283 /* Fill in structure pointed to by OP with the various optab entries for an
7284 operation of type CODE. */
7286 static void
7288 {
7291 /* If SWITCHABLE_TARGET is defined, then subtargets can be switched
7292 in the source code during compilation, and the optab entries are not
7293 computable until runtime. Fill in the values at runtime. */
7295 {
7352 }
7353 }
7355 /* See if there is a more optimal way to implement the operation "*MEM CODE VAL"
7356 using memory order MODEL. If AFTER is true the operation needs to return
7357 the value of *MEM after the operation, otherwise the previous value.
7358 TARGET is an optional place to place the result. The result is unused if
7359 it is const0_rtx.
7360 Return the result if there is a better sequence, otherwise NULL_RTX. */
7362 static rtx
7365 {
7366 /* If the value is prefetched, or not used, it may be possible to replace
7367 the sequence with a native exchange operation. */
7369 {
7370 /* fetch_and (&x, 0, m) can be replaced with exchange (&x, 0, m). */
7372 {
7376 }
7378 /* fetch_or (&x, -1, m) can be replaced with exchange (&x, -1, m). */
7380 {
7384 }
7385 }
7388 }
7390 /* Try to emit an instruction for a specific operation varaition.
7391 OPTAB contains the OP functions.
7392 TARGET is an optional place to return the result. const0_rtx means unused.
7393 MEM is the memory location to operate on.
7394 VAL is the value to use in the operation.
7395 USE_MEMMODEL is TRUE if the variation with a memory model should be tried.
7396 MODEL is the memory model, if used.
7397 AFTER is true if the returned result is the value after the operation. */
7399 static rtx
7402 {
7409 /* Check to see if there is a result returned. */
7411 {
7413 {
7417 }
7418 else
7419 {
7422 }
7423 }
7424 /* Otherwise, we need to generate a result. */
7425 else
7426 {
7428 {
7433 }
7434 else
7435 {
7439 }
7441 }
7446 /* VAL may have been promoted to a wider mode. Shrink it if so. */
7453 }
7456 /* This function expands an atomic fetch_OP or OP_fetch operation:
7457 TARGET is an option place to stick the return value. const0_rtx indicates
7458 the result is unused.
7459 atomically fetch MEM, perform the operation with VAL and return it to MEM.
7460 CODE is the operation being performed (OP)
7461 MEMMODEL is the memory model variant to use.
7462 AFTER is true to return the result of the operation (OP_fetch).
7463 AFTER is false to return the value before the operation (fetch_OP).
7465 This function will *only* generate instructions if there is a direct
7466 optab. No compare and swap loops or libcalls will be generated. */
7468 static rtx
7472 {
7475 rtx result;
7480 /* Check to see if there are any better instructions. */
7485 /* Check for the case where the result isn't used and try those patterns. */
7487 {
7488 /* Try the memory model variant first. */
7493 /* Next try the old style withuot a memory model. */
7498 /* There is no no-result pattern, so try patterns with a result. */
7500 }
7502 /* Try the __atomic version. */
7507 /* Try the older __sync version. */
7512 /* If the fetch value can be calculated from the other variation of fetch,
7513 try that operation. */
7515 {
7516 /* Try the __atomic version, then the older __sync version. */
7522 {
7523 /* If the result isn't used, no need to do compensation code. */
7527 /* Issue compensation code. Fetch_after == fetch_before OP val.
7528 Fetch_before == after REVERSE_OP val. */
7532 {
7536 }
7537 else
7541 }
7542 }
7544 /* No direct opcode can be generated. */
7546 }
7550 /* This function expands an atomic fetch_OP or OP_fetch operation:
7551 TARGET is an option place to stick the return value. const0_rtx indicates
7552 the result is unused.
7553 atomically fetch MEM, perform the operation with VAL and return it to MEM.
7554 CODE is the operation being performed (OP)
7555 MEMMODEL is the memory model variant to use.
7556 AFTER is true to return the result of the operation (OP_fetch).
7557 AFTER is false to return the value before the operation (fetch_OP). */
7558 rtx
7561 {
7563 rtx result;
7566 /* If loads are not atomic for the required size and we are not called to
7567 provide a __sync builtin, do not do anything so that we stay consistent
7568 with atomic loads of the same size. */
7573 after);
7578 /* Add/sub can be implemented by doing the reverse operation with -(val). */
7580 {
7581 rtx tmp;
7589 {
7590 /* PLUS worked so emit the insns and return. */
7595 }
7597 /* PLUS did not work, so throw away the negation code and continue. */
7599 }
7601 /* Try the __sync libcalls only if we can't do compare-and-swap inline. */
7603 {
7604 rtx libfunc;
7614 {
7620 }
7622 {
7631 }
7633 /* We need the original code for any further attempts. */
7635 }
7637 /* If nothing else has succeeded, default to a compare and swap loop. */
7639 {
7645 /* If the result is used, get a register for it. */
7647 {
7650 /* If fetch_before, copy the value now. */
7653 }
7654 else
7659 {
7663 }
7664 else
7666 OPTAB_LIB_WIDEN);
7668 /* For after, copy the value now. */
7676 }
7679 }
7680 \f
7681 /* Return true if OPERAND is suitable for operand number OPNO of
7682 instruction ICODE. */
7684 bool
7686 {
7690 }
7691 \f
7692 /* TARGET is a target of a multiword operation that we are going to
7693 implement as a series of word-mode operations. Return true if
7694 TARGET is suitable for this purpose. */
7696 bool
7698 {
7699 machine_mode mode;
7709 }
7711 /* Make OP describe an input operand that has value INTVAL and that has
7712 no inherent mode. This function should only be used for operands that
7713 are always expand-time constants. The backend may request that INTVAL
7714 be copied into a different kind of rtx, but it must specify the mode
7715 of that rtx if so. */
7717 void
7719 {
7723 }
7725 /* Like maybe_legitimize_operand, but do not change the code of the
7726 current rtx value. */
7728 static bool
7731 {
7732 /* See if the operand matches in its current form. */
7736 /* If the operand is a memory whose address has no side effects,
7737 try forcing the address into a non-virtual pseudo register.
7738 The check for side effects is important because copy_to_mode_reg
7739 cannot handle things like auto-modified addresses. */
7741 {
7748 {
7750 machine_mode mode;
7756 {
7759 }
7761 }
7762 }
7765 }
7767 /* Try to make OP match operand OPNO of instruction ICODE. Return true
7768 on success, storing the new operand value back in OP. */
7770 static bool
7773 {
7778 {
7780 {
7783 }
7798 input:
7816 else
7817 /* The caller must tell us what mode this value has. */
7824 {
7827 }
7829 {
7833 }
7846 {
7849 }
7851 }
7853 }
7855 /* Make OP describe an input operand that should have the same value
7856 as VALUE, after any mode conversion that the target might request.
7857 TYPE is the type of VALUE. */
7859 void
7862 {
7865 }
7867 /* Return true if the requirements on operands OP1 and OP2 of instruction
7868 ICODE are similar enough for the result of legitimizing OP1 to be
7869 reusable for OP2. OPNO1 and OPNO2 are the operand numbers associated
7870 with OP1 and OP2 respectively. */
7877 {
7878 /* Check requirements that are common to all types. */
7885 /* Check the requirements for specific types. */
7887 {
7889 /* Outputs must remain distinct. */
7901 }
7903 }
7905 /* Try to make operands [OPS, OPS + NOPS) match operands [OPNO, OPNO + NOPS)
7906 of instruction ICODE. Return true on success, leaving the new operand
7907 values in the OPS themselves. Emit no code on failure. */
7909 bool
7912 {
7916 {
7919 /* First try reusing the result of an earlier legitimization.
7920 This avoids duplicate rtl and ensures that tied operands
7921 remain tied.
7923 This search is linear, but NOPS is bounded at compile time
7924 to a small number (current a single digit). */
7931 {
7934 }
7936 /* Otherwise try legitimizing the operand on its own. */
7938 {
7941 }
7942 }
7944 }
7946 /* Try to generate instruction ICODE, using operands [OPS, OPS + NOPS)
7947 as its operands. Return the instruction pattern on success,
7948 and emit any necessary set-up code. Return null and emit no
7949 code on failure. */
7951 rtx_insn *
7954 {
7960 {
7988 }
7990 }
7992 /* Try to emit instruction ICODE, using operands [OPS, OPS + NOPS)
7993 as its operands. Return true on success and emit no code on failure. */
7995 bool
7998 {
8001 {
8004 }
8006 }
8008 /* Like maybe_expand_insn, but for jumps. */
8010 bool
8013 {
8016 {
8019 }
8021 }
8023 /* Emit instruction ICODE, using operands [OPS, OPS + NOPS)
8024 as its operands. */
8026 void
8029 {
8032 }
8034 /* Like expand_insn, but for jumps. */
8036 void
8039 {
8042 }