1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
56 #include "tree-flow.h"
59 #include "tm-constrs.h"
61 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
64 #include "gstab.h" /* for N_SLINE */
67 #ifndef TARGET_NO_PROTOTYPE
68 #define TARGET_NO_PROTOTYPE 0
71 #define min(A,B) ((A) < (B) ? (A) : (B))
72 #define max(A,B) ((A) > (B) ? (A) : (B))
74 /* Structure used to define the rs6000 stack */
75 typedef struct rs6000_stack
{
76 int first_gp_reg_save
; /* first callee saved GP register used */
77 int first_fp_reg_save
; /* first callee saved FP register used */
78 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
79 int lr_save_p
; /* true if the link reg needs to be saved */
80 int cr_save_p
; /* true if the CR reg needs to be saved */
81 unsigned int vrsave_mask
; /* mask of vec registers to save */
82 int push_p
; /* true if we need to allocate stack space */
83 int calls_p
; /* true if the function makes any calls */
84 int world_save_p
; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi
; /* which ABI to use */
87 int gp_save_offset
; /* offset to save GP regs from initial SP */
88 int fp_save_offset
; /* offset to save FP regs from initial SP */
89 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset
; /* offset to save LR from initial SP */
91 int cr_save_offset
; /* offset to save CR from initial SP */
92 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
94 int varargs_save_offset
; /* offset to save the varargs registers */
95 int ehrd_offset
; /* offset to EH return data */
96 int reg_size
; /* register size (4 or 8) */
97 HOST_WIDE_INT vars_size
; /* variable save area size */
98 int parm_size
; /* outgoing parameter size */
99 int save_size
; /* save area size */
100 int fixed_size
; /* fixed size of stack frame */
101 int gp_size
; /* size of saved GP registers */
102 int fp_size
; /* size of saved FP registers */
103 int altivec_size
; /* size of saved AltiVec registers */
104 int cr_size
; /* size to hold CR if not in save_size */
105 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size
; /* size of altivec alignment padding if
108 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size
;
110 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
111 int spe_64bit_regs_used
;
114 /* A C structure for machine-specific, per-function data.
115 This is added to the cfun structure. */
116 typedef struct GTY(()) machine_function
118 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
119 int ra_needs_full_frame
;
120 /* Some local-dynamic symbol. */
121 const char *some_ld_name
;
122 /* Whether the instruction chain has been scanned already. */
123 int insn_chain_scanned_p
;
124 /* Flags if __builtin_return_address (0) was used. */
126 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
127 varargs save area. */
128 HOST_WIDE_INT varargs_save_offset
;
129 /* Temporary stack slot to use for SDmode copies. This slot is
130 64-bits wide and is allocated early enough so that the offset
131 does not overflow the 16-bit load/store offset field. */
132 rtx sdmode_stack_slot
;
135 /* Target cpu type */
137 enum processor_type rs6000_cpu
;
138 struct rs6000_cpu_select rs6000_select
[3] =
140 /* switch name, tune arch */
141 { (const char *)0, "--with-cpu=", 1, 1 },
142 { (const char *)0, "-mcpu=", 1, 1 },
143 { (const char *)0, "-mtune=", 1, 0 },
146 /* Always emit branch hint bits. */
147 static GTY(()) bool rs6000_always_hint
;
149 /* Schedule instructions for group formation. */
150 static GTY(()) bool rs6000_sched_groups
;
152 /* Align branch targets. */
153 static GTY(()) bool rs6000_align_branch_targets
;
155 /* Support for -msched-costly-dep option. */
156 const char *rs6000_sched_costly_dep_str
;
157 enum rs6000_dependence_cost rs6000_sched_costly_dep
;
159 /* Support for -minsert-sched-nops option. */
160 const char *rs6000_sched_insert_nops_str
;
161 enum rs6000_nop_insertion rs6000_sched_insert_nops
;
163 /* Support targetm.vectorize.builtin_mask_for_load. */
164 static GTY(()) tree altivec_builtin_mask_for_load
;
166 /* Size of long double. */
167 int rs6000_long_double_type_size
;
169 /* IEEE quad extended precision long double. */
172 /* Nonzero to use AltiVec ABI. */
173 int rs6000_altivec_abi
;
175 /* Nonzero if we want SPE SIMD instructions. */
178 /* Nonzero if we want SPE ABI extensions. */
181 /* Nonzero to use isel instructions. */
184 /* Nonzero if floating point operations are done in the GPRs. */
185 int rs6000_float_gprs
= 0;
187 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
188 int rs6000_darwin64_abi
;
190 /* Set to nonzero once AIX common-mode calls have been defined. */
191 static GTY(()) int common_mode_defined
;
193 /* Label number of label created for -mrelocatable, to call to so we can
194 get the address of the GOT section */
195 int rs6000_pic_labelno
;
198 /* Which abi to adhere to */
199 const char *rs6000_abi_name
;
201 /* Semantics of the small data area */
202 enum rs6000_sdata_type rs6000_sdata
= SDATA_DATA
;
204 /* Which small data model to use */
205 const char *rs6000_sdata_name
= (char *)0;
207 /* Counter for labels which are to be placed in .fixup. */
208 int fixuplabelno
= 0;
211 /* Bit size of immediate TLS offsets and string from which it is decoded. */
212 int rs6000_tls_size
= 32;
213 const char *rs6000_tls_size_string
;
215 /* ABI enumeration available for subtarget to use. */
216 enum rs6000_abi rs6000_current_abi
;
218 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
222 const char *rs6000_debug_name
;
223 int rs6000_debug_stack
; /* debug stack applications */
224 int rs6000_debug_arg
; /* debug argument handling */
226 /* Value is TRUE if register/mode pair is acceptable. */
227 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
229 /* Built in types. */
231 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
232 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
234 const char *rs6000_traceback_name
;
236 traceback_default
= 0,
242 /* Flag to say the TOC is initialized */
244 char toc_label_name
[10];
246 /* Cached value of rs6000_variable_issue. This is cached in
247 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
248 static short cached_can_issue_more
;
250 static GTY(()) section
*read_only_data_section
;
251 static GTY(()) section
*private_data_section
;
252 static GTY(()) section
*read_only_private_data_section
;
253 static GTY(()) section
*sdata2_section
;
254 static GTY(()) section
*toc_section
;
256 /* Control alignment for fields within structures. */
257 /* String from -malign-XXXXX. */
258 int rs6000_alignment_flags
;
260 /* True for any options that were explicitly set. */
262 bool aix_struct_ret
; /* True if -maix-struct-ret was used. */
263 bool alignment
; /* True if -malign- was used. */
264 bool spe_abi
; /* True if -mabi=spe/no-spe was used. */
265 bool altivec_abi
; /* True if -mabi=altivec/no-altivec used. */
266 bool spe
; /* True if -mspe= was used. */
267 bool float_gprs
; /* True if -mfloat-gprs= was used. */
268 bool isel
; /* True if -misel was used. */
269 bool long_double
; /* True if -mlong-double- was used. */
270 bool ieee
; /* True if -mabi=ieee/ibmlongdouble used. */
271 bool vrsave
; /* True if -mvrsave was used. */
272 } rs6000_explicit_options
;
274 struct builtin_description
276 /* mask is not const because we're going to alter it below. This
277 nonsense will go away when we rewrite the -march infrastructure
278 to give us more target flag bits. */
280 const enum insn_code icode
;
281 const char *const name
;
282 const enum rs6000_builtins code
;
285 /* Target cpu costs. */
287 struct processor_costs
{
288 const int mulsi
; /* cost of SImode multiplication. */
289 const int mulsi_const
; /* cost of SImode multiplication by constant. */
290 const int mulsi_const9
; /* cost of SImode mult by short constant. */
291 const int muldi
; /* cost of DImode multiplication. */
292 const int divsi
; /* cost of SImode division. */
293 const int divdi
; /* cost of DImode division. */
294 const int fp
; /* cost of simple SFmode and DFmode insns. */
295 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
296 const int sdiv
; /* cost of SFmode division (fdivs). */
297 const int ddiv
; /* cost of DFmode division (fdiv). */
298 const int cache_line_size
; /* cache line size in bytes. */
299 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
300 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
301 const int simultaneous_prefetches
; /* number of parallel prefetch
305 const struct processor_costs
*rs6000_cost
;
307 /* Processor costs (relative to an add) */
309 /* Instruction size costs on 32bit processors. */
311 struct processor_costs size32_cost
= {
312 COSTS_N_INSNS (1), /* mulsi */
313 COSTS_N_INSNS (1), /* mulsi_const */
314 COSTS_N_INSNS (1), /* mulsi_const9 */
315 COSTS_N_INSNS (1), /* muldi */
316 COSTS_N_INSNS (1), /* divsi */
317 COSTS_N_INSNS (1), /* divdi */
318 COSTS_N_INSNS (1), /* fp */
319 COSTS_N_INSNS (1), /* dmul */
320 COSTS_N_INSNS (1), /* sdiv */
321 COSTS_N_INSNS (1), /* ddiv */
328 /* Instruction size costs on 64bit processors. */
330 struct processor_costs size64_cost
= {
331 COSTS_N_INSNS (1), /* mulsi */
332 COSTS_N_INSNS (1), /* mulsi_const */
333 COSTS_N_INSNS (1), /* mulsi_const9 */
334 COSTS_N_INSNS (1), /* muldi */
335 COSTS_N_INSNS (1), /* divsi */
336 COSTS_N_INSNS (1), /* divdi */
337 COSTS_N_INSNS (1), /* fp */
338 COSTS_N_INSNS (1), /* dmul */
339 COSTS_N_INSNS (1), /* sdiv */
340 COSTS_N_INSNS (1), /* ddiv */
347 /* Instruction costs on RIOS1 processors. */
349 struct processor_costs rios1_cost
= {
350 COSTS_N_INSNS (5), /* mulsi */
351 COSTS_N_INSNS (4), /* mulsi_const */
352 COSTS_N_INSNS (3), /* mulsi_const9 */
353 COSTS_N_INSNS (5), /* muldi */
354 COSTS_N_INSNS (19), /* divsi */
355 COSTS_N_INSNS (19), /* divdi */
356 COSTS_N_INSNS (2), /* fp */
357 COSTS_N_INSNS (2), /* dmul */
358 COSTS_N_INSNS (19), /* sdiv */
359 COSTS_N_INSNS (19), /* ddiv */
360 128, /* cache line size */
366 /* Instruction costs on RIOS2 processors. */
368 struct processor_costs rios2_cost
= {
369 COSTS_N_INSNS (2), /* mulsi */
370 COSTS_N_INSNS (2), /* mulsi_const */
371 COSTS_N_INSNS (2), /* mulsi_const9 */
372 COSTS_N_INSNS (2), /* muldi */
373 COSTS_N_INSNS (13), /* divsi */
374 COSTS_N_INSNS (13), /* divdi */
375 COSTS_N_INSNS (2), /* fp */
376 COSTS_N_INSNS (2), /* dmul */
377 COSTS_N_INSNS (17), /* sdiv */
378 COSTS_N_INSNS (17), /* ddiv */
379 256, /* cache line size */
385 /* Instruction costs on RS64A processors. */
387 struct processor_costs rs64a_cost
= {
388 COSTS_N_INSNS (20), /* mulsi */
389 COSTS_N_INSNS (12), /* mulsi_const */
390 COSTS_N_INSNS (8), /* mulsi_const9 */
391 COSTS_N_INSNS (34), /* muldi */
392 COSTS_N_INSNS (65), /* divsi */
393 COSTS_N_INSNS (67), /* divdi */
394 COSTS_N_INSNS (4), /* fp */
395 COSTS_N_INSNS (4), /* dmul */
396 COSTS_N_INSNS (31), /* sdiv */
397 COSTS_N_INSNS (31), /* ddiv */
398 128, /* cache line size */
404 /* Instruction costs on MPCCORE processors. */
406 struct processor_costs mpccore_cost
= {
407 COSTS_N_INSNS (2), /* mulsi */
408 COSTS_N_INSNS (2), /* mulsi_const */
409 COSTS_N_INSNS (2), /* mulsi_const9 */
410 COSTS_N_INSNS (2), /* muldi */
411 COSTS_N_INSNS (6), /* divsi */
412 COSTS_N_INSNS (6), /* divdi */
413 COSTS_N_INSNS (4), /* fp */
414 COSTS_N_INSNS (5), /* dmul */
415 COSTS_N_INSNS (10), /* sdiv */
416 COSTS_N_INSNS (17), /* ddiv */
417 32, /* cache line size */
423 /* Instruction costs on PPC403 processors. */
425 struct processor_costs ppc403_cost
= {
426 COSTS_N_INSNS (4), /* mulsi */
427 COSTS_N_INSNS (4), /* mulsi_const */
428 COSTS_N_INSNS (4), /* mulsi_const9 */
429 COSTS_N_INSNS (4), /* muldi */
430 COSTS_N_INSNS (33), /* divsi */
431 COSTS_N_INSNS (33), /* divdi */
432 COSTS_N_INSNS (11), /* fp */
433 COSTS_N_INSNS (11), /* dmul */
434 COSTS_N_INSNS (11), /* sdiv */
435 COSTS_N_INSNS (11), /* ddiv */
436 32, /* cache line size */
442 /* Instruction costs on PPC405 processors. */
444 struct processor_costs ppc405_cost
= {
445 COSTS_N_INSNS (5), /* mulsi */
446 COSTS_N_INSNS (4), /* mulsi_const */
447 COSTS_N_INSNS (3), /* mulsi_const9 */
448 COSTS_N_INSNS (5), /* muldi */
449 COSTS_N_INSNS (35), /* divsi */
450 COSTS_N_INSNS (35), /* divdi */
451 COSTS_N_INSNS (11), /* fp */
452 COSTS_N_INSNS (11), /* dmul */
453 COSTS_N_INSNS (11), /* sdiv */
454 COSTS_N_INSNS (11), /* ddiv */
455 32, /* cache line size */
461 /* Instruction costs on PPC440 processors. */
463 struct processor_costs ppc440_cost
= {
464 COSTS_N_INSNS (3), /* mulsi */
465 COSTS_N_INSNS (2), /* mulsi_const */
466 COSTS_N_INSNS (2), /* mulsi_const9 */
467 COSTS_N_INSNS (3), /* muldi */
468 COSTS_N_INSNS (34), /* divsi */
469 COSTS_N_INSNS (34), /* divdi */
470 COSTS_N_INSNS (5), /* fp */
471 COSTS_N_INSNS (5), /* dmul */
472 COSTS_N_INSNS (19), /* sdiv */
473 COSTS_N_INSNS (33), /* ddiv */
474 32, /* cache line size */
480 /* Instruction costs on PPC601 processors. */
482 struct processor_costs ppc601_cost
= {
483 COSTS_N_INSNS (5), /* mulsi */
484 COSTS_N_INSNS (5), /* mulsi_const */
485 COSTS_N_INSNS (5), /* mulsi_const9 */
486 COSTS_N_INSNS (5), /* muldi */
487 COSTS_N_INSNS (36), /* divsi */
488 COSTS_N_INSNS (36), /* divdi */
489 COSTS_N_INSNS (4), /* fp */
490 COSTS_N_INSNS (5), /* dmul */
491 COSTS_N_INSNS (17), /* sdiv */
492 COSTS_N_INSNS (31), /* ddiv */
493 32, /* cache line size */
499 /* Instruction costs on PPC603 processors. */
501 struct processor_costs ppc603_cost
= {
502 COSTS_N_INSNS (5), /* mulsi */
503 COSTS_N_INSNS (3), /* mulsi_const */
504 COSTS_N_INSNS (2), /* mulsi_const9 */
505 COSTS_N_INSNS (5), /* muldi */
506 COSTS_N_INSNS (37), /* divsi */
507 COSTS_N_INSNS (37), /* divdi */
508 COSTS_N_INSNS (3), /* fp */
509 COSTS_N_INSNS (4), /* dmul */
510 COSTS_N_INSNS (18), /* sdiv */
511 COSTS_N_INSNS (33), /* ddiv */
512 32, /* cache line size */
518 /* Instruction costs on PPC604 processors. */
520 struct processor_costs ppc604_cost
= {
521 COSTS_N_INSNS (4), /* mulsi */
522 COSTS_N_INSNS (4), /* mulsi_const */
523 COSTS_N_INSNS (4), /* mulsi_const9 */
524 COSTS_N_INSNS (4), /* muldi */
525 COSTS_N_INSNS (20), /* divsi */
526 COSTS_N_INSNS (20), /* divdi */
527 COSTS_N_INSNS (3), /* fp */
528 COSTS_N_INSNS (3), /* dmul */
529 COSTS_N_INSNS (18), /* sdiv */
530 COSTS_N_INSNS (32), /* ddiv */
531 32, /* cache line size */
537 /* Instruction costs on PPC604e processors. */
539 struct processor_costs ppc604e_cost
= {
540 COSTS_N_INSNS (2), /* mulsi */
541 COSTS_N_INSNS (2), /* mulsi_const */
542 COSTS_N_INSNS (2), /* mulsi_const9 */
543 COSTS_N_INSNS (2), /* muldi */
544 COSTS_N_INSNS (20), /* divsi */
545 COSTS_N_INSNS (20), /* divdi */
546 COSTS_N_INSNS (3), /* fp */
547 COSTS_N_INSNS (3), /* dmul */
548 COSTS_N_INSNS (18), /* sdiv */
549 COSTS_N_INSNS (32), /* ddiv */
550 32, /* cache line size */
556 /* Instruction costs on PPC620 processors. */
558 struct processor_costs ppc620_cost
= {
559 COSTS_N_INSNS (5), /* mulsi */
560 COSTS_N_INSNS (4), /* mulsi_const */
561 COSTS_N_INSNS (3), /* mulsi_const9 */
562 COSTS_N_INSNS (7), /* muldi */
563 COSTS_N_INSNS (21), /* divsi */
564 COSTS_N_INSNS (37), /* divdi */
565 COSTS_N_INSNS (3), /* fp */
566 COSTS_N_INSNS (3), /* dmul */
567 COSTS_N_INSNS (18), /* sdiv */
568 COSTS_N_INSNS (32), /* ddiv */
569 128, /* cache line size */
575 /* Instruction costs on PPC630 processors. */
577 struct processor_costs ppc630_cost
= {
578 COSTS_N_INSNS (5), /* mulsi */
579 COSTS_N_INSNS (4), /* mulsi_const */
580 COSTS_N_INSNS (3), /* mulsi_const9 */
581 COSTS_N_INSNS (7), /* muldi */
582 COSTS_N_INSNS (21), /* divsi */
583 COSTS_N_INSNS (37), /* divdi */
584 COSTS_N_INSNS (3), /* fp */
585 COSTS_N_INSNS (3), /* dmul */
586 COSTS_N_INSNS (17), /* sdiv */
587 COSTS_N_INSNS (21), /* ddiv */
588 128, /* cache line size */
594 /* Instruction costs on Cell processor. */
595 /* COSTS_N_INSNS (1) ~ one add. */
597 struct processor_costs ppccell_cost
= {
598 COSTS_N_INSNS (9/2)+2, /* mulsi */
599 COSTS_N_INSNS (6/2), /* mulsi_const */
600 COSTS_N_INSNS (6/2), /* mulsi_const9 */
601 COSTS_N_INSNS (15/2)+2, /* muldi */
602 COSTS_N_INSNS (38/2), /* divsi */
603 COSTS_N_INSNS (70/2), /* divdi */
604 COSTS_N_INSNS (10/2), /* fp */
605 COSTS_N_INSNS (10/2), /* dmul */
606 COSTS_N_INSNS (74/2), /* sdiv */
607 COSTS_N_INSNS (74/2), /* ddiv */
608 128, /* cache line size */
614 /* Instruction costs on PPC750 and PPC7400 processors. */
616 struct processor_costs ppc750_cost
= {
617 COSTS_N_INSNS (5), /* mulsi */
618 COSTS_N_INSNS (3), /* mulsi_const */
619 COSTS_N_INSNS (2), /* mulsi_const9 */
620 COSTS_N_INSNS (5), /* muldi */
621 COSTS_N_INSNS (17), /* divsi */
622 COSTS_N_INSNS (17), /* divdi */
623 COSTS_N_INSNS (3), /* fp */
624 COSTS_N_INSNS (3), /* dmul */
625 COSTS_N_INSNS (17), /* sdiv */
626 COSTS_N_INSNS (31), /* ddiv */
627 32, /* cache line size */
633 /* Instruction costs on PPC7450 processors. */
635 struct processor_costs ppc7450_cost
= {
636 COSTS_N_INSNS (4), /* mulsi */
637 COSTS_N_INSNS (3), /* mulsi_const */
638 COSTS_N_INSNS (3), /* mulsi_const9 */
639 COSTS_N_INSNS (4), /* muldi */
640 COSTS_N_INSNS (23), /* divsi */
641 COSTS_N_INSNS (23), /* divdi */
642 COSTS_N_INSNS (5), /* fp */
643 COSTS_N_INSNS (5), /* dmul */
644 COSTS_N_INSNS (21), /* sdiv */
645 COSTS_N_INSNS (35), /* ddiv */
646 32, /* cache line size */
652 /* Instruction costs on PPC8540 processors. */
654 struct processor_costs ppc8540_cost
= {
655 COSTS_N_INSNS (4), /* mulsi */
656 COSTS_N_INSNS (4), /* mulsi_const */
657 COSTS_N_INSNS (4), /* mulsi_const9 */
658 COSTS_N_INSNS (4), /* muldi */
659 COSTS_N_INSNS (19), /* divsi */
660 COSTS_N_INSNS (19), /* divdi */
661 COSTS_N_INSNS (4), /* fp */
662 COSTS_N_INSNS (4), /* dmul */
663 COSTS_N_INSNS (29), /* sdiv */
664 COSTS_N_INSNS (29), /* ddiv */
665 32, /* cache line size */
668 1, /* prefetch streams /*/
671 /* Instruction costs on E300C2 and E300C3 cores. */
673 struct processor_costs ppce300c2c3_cost
= {
674 COSTS_N_INSNS (4), /* mulsi */
675 COSTS_N_INSNS (4), /* mulsi_const */
676 COSTS_N_INSNS (4), /* mulsi_const9 */
677 COSTS_N_INSNS (4), /* muldi */
678 COSTS_N_INSNS (19), /* divsi */
679 COSTS_N_INSNS (19), /* divdi */
680 COSTS_N_INSNS (3), /* fp */
681 COSTS_N_INSNS (4), /* dmul */
682 COSTS_N_INSNS (18), /* sdiv */
683 COSTS_N_INSNS (33), /* ddiv */
687 1, /* prefetch streams /*/
690 /* Instruction costs on PPCE500MC processors. */
692 struct processor_costs ppce500mc_cost
= {
693 COSTS_N_INSNS (4), /* mulsi */
694 COSTS_N_INSNS (4), /* mulsi_const */
695 COSTS_N_INSNS (4), /* mulsi_const9 */
696 COSTS_N_INSNS (4), /* muldi */
697 COSTS_N_INSNS (14), /* divsi */
698 COSTS_N_INSNS (14), /* divdi */
699 COSTS_N_INSNS (8), /* fp */
700 COSTS_N_INSNS (10), /* dmul */
701 COSTS_N_INSNS (36), /* sdiv */
702 COSTS_N_INSNS (66), /* ddiv */
703 64, /* cache line size */
706 1, /* prefetch streams /*/
709 /* Instruction costs on POWER4 and POWER5 processors. */
711 struct processor_costs power4_cost
= {
712 COSTS_N_INSNS (3), /* mulsi */
713 COSTS_N_INSNS (2), /* mulsi_const */
714 COSTS_N_INSNS (2), /* mulsi_const9 */
715 COSTS_N_INSNS (4), /* muldi */
716 COSTS_N_INSNS (18), /* divsi */
717 COSTS_N_INSNS (34), /* divdi */
718 COSTS_N_INSNS (3), /* fp */
719 COSTS_N_INSNS (3), /* dmul */
720 COSTS_N_INSNS (17), /* sdiv */
721 COSTS_N_INSNS (17), /* ddiv */
722 128, /* cache line size */
725 8, /* prefetch streams /*/
728 /* Instruction costs on POWER6 processors. */
730 struct processor_costs power6_cost
= {
731 COSTS_N_INSNS (8), /* mulsi */
732 COSTS_N_INSNS (8), /* mulsi_const */
733 COSTS_N_INSNS (8), /* mulsi_const9 */
734 COSTS_N_INSNS (8), /* muldi */
735 COSTS_N_INSNS (22), /* divsi */
736 COSTS_N_INSNS (28), /* divdi */
737 COSTS_N_INSNS (3), /* fp */
738 COSTS_N_INSNS (3), /* dmul */
739 COSTS_N_INSNS (13), /* sdiv */
740 COSTS_N_INSNS (16), /* ddiv */
741 128, /* cache line size */
744 16, /* prefetch streams */
748 static bool rs6000_function_ok_for_sibcall (tree
, tree
);
749 static const char *rs6000_invalid_within_doloop (const_rtx
);
750 static rtx
rs6000_generate_compare (rtx
, enum machine_mode
);
751 static void rs6000_emit_stack_tie (void);
752 static void rs6000_frame_related (rtx
, rtx
, HOST_WIDE_INT
, rtx
, rtx
);
753 static bool spe_func_has_64bit_regs_p (void);
754 static void emit_frame_save (rtx
, rtx
, enum machine_mode
, unsigned int,
756 static rtx
gen_frame_mem_offset (enum machine_mode
, rtx
, int);
757 static void rs6000_emit_allocate_stack (HOST_WIDE_INT
, int, int);
758 static unsigned rs6000_hash_constant (rtx
);
759 static unsigned toc_hash_function (const void *);
760 static int toc_hash_eq (const void *, const void *);
761 static bool constant_pool_expr_p (rtx
);
762 static bool legitimate_small_data_p (enum machine_mode
, rtx
);
763 static bool legitimate_lo_sum_address_p (enum machine_mode
, rtx
, int);
764 static struct machine_function
* rs6000_init_machine_status (void);
765 static bool rs6000_assemble_integer (rtx
, unsigned int, int);
766 static bool no_global_regs_above (int, bool);
767 #ifdef HAVE_GAS_HIDDEN
768 static void rs6000_assemble_visibility (tree
, int);
770 static int rs6000_ra_ever_killed (void);
771 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
772 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
773 static bool rs6000_ms_bitfield_layout_p (const_tree
);
774 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
775 static void rs6000_eliminate_indexed_memrefs (rtx operands
[2]);
776 static const char *rs6000_mangle_type (const_tree
);
777 extern const struct attribute_spec rs6000_attribute_table
[];
778 static void rs6000_set_default_type_attributes (tree
);
779 static rtx
rs6000_savres_routine_sym (rs6000_stack_t
*, bool, bool, bool);
780 static void rs6000_emit_stack_reset (rs6000_stack_t
*, rtx
, rtx
, int, bool);
781 static rtx
rs6000_make_savres_rtx (rs6000_stack_t
*, rtx
, int,
782 enum machine_mode
, bool, bool, bool);
783 static bool rs6000_reg_live_or_pic_offset_p (int);
784 static int rs6000_savres_strategy (rs6000_stack_t
*, bool, int, int);
785 static void rs6000_restore_saved_cr (rtx
, int);
786 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT
);
787 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT
);
788 static void rs6000_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
790 static rtx
rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
791 static bool rs6000_return_in_memory (const_tree
, const_tree
);
792 static void rs6000_file_start (void);
794 static int rs6000_elf_reloc_rw_mask (void);
795 static void rs6000_elf_asm_out_constructor (rtx
, int);
796 static void rs6000_elf_asm_out_destructor (rtx
, int);
797 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED
;
798 static void rs6000_elf_asm_init_sections (void);
799 static section
*rs6000_elf_select_rtx_section (enum machine_mode
, rtx
,
800 unsigned HOST_WIDE_INT
);
801 static void rs6000_elf_encode_section_info (tree
, rtx
, int)
804 static bool rs6000_use_blocks_for_constant_p (enum machine_mode
, const_rtx
);
805 static void rs6000_alloc_sdmode_stack_slot (void);
806 static void rs6000_instantiate_decls (void);
808 static void rs6000_xcoff_asm_output_anchor (rtx
);
809 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
810 static void rs6000_xcoff_asm_init_sections (void);
811 static int rs6000_xcoff_reloc_rw_mask (void);
812 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree
);
813 static section
*rs6000_xcoff_select_section (tree
, int,
814 unsigned HOST_WIDE_INT
);
815 static void rs6000_xcoff_unique_section (tree
, int);
816 static section
*rs6000_xcoff_select_rtx_section
817 (enum machine_mode
, rtx
, unsigned HOST_WIDE_INT
);
818 static const char * rs6000_xcoff_strip_name_encoding (const char *);
819 static unsigned int rs6000_xcoff_section_type_flags (tree
, const char *, int);
820 static void rs6000_xcoff_file_start (void);
821 static void rs6000_xcoff_file_end (void);
823 static int rs6000_variable_issue (FILE *, int, rtx
, int);
824 static bool rs6000_rtx_costs (rtx
, int, int, int *, bool);
825 static int rs6000_adjust_cost (rtx
, rtx
, rtx
, int);
826 static void rs6000_sched_init (FILE *, int, int);
827 static bool is_microcoded_insn (rtx
);
828 static bool is_nonpipeline_insn (rtx
);
829 static bool is_cracked_insn (rtx
);
830 static bool is_branch_slot_insn (rtx
);
831 static bool is_load_insn (rtx
);
832 static rtx
get_store_dest (rtx pat
);
833 static bool is_store_insn (rtx
);
834 static bool set_to_load_agen (rtx
,rtx
);
835 static bool adjacent_mem_locations (rtx
,rtx
);
836 static int rs6000_adjust_priority (rtx
, int);
837 static int rs6000_issue_rate (void);
838 static bool rs6000_is_costly_dependence (dep_t
, int, int);
839 static rtx
get_next_active_insn (rtx
, rtx
);
840 static bool insn_terminates_group_p (rtx
, enum group_termination
);
841 static bool insn_must_be_first_in_group (rtx
);
842 static bool insn_must_be_last_in_group (rtx
);
843 static bool is_costly_group (rtx
*, rtx
);
844 static int force_new_group (int, FILE *, rtx
*, rtx
, bool *, int, int *);
845 static int redefine_groups (FILE *, int, rtx
, rtx
);
846 static int pad_groups (FILE *, int, rtx
, rtx
);
847 static void rs6000_sched_finish (FILE *, int);
848 static int rs6000_sched_reorder (FILE *, int, rtx
*, int *, int);
849 static int rs6000_sched_reorder2 (FILE *, int, rtx
*, int *, int);
850 static int rs6000_use_sched_lookahead (void);
851 static int rs6000_use_sched_lookahead_guard (rtx
);
852 static void * rs6000_alloc_sched_context (void);
853 static void rs6000_init_sched_context (void *, bool);
854 static void rs6000_set_sched_context (void *);
855 static void rs6000_free_sched_context (void *);
856 static tree
rs6000_builtin_reciprocal (unsigned int, bool, bool);
857 static tree
rs6000_builtin_mask_for_load (void);
858 static tree
rs6000_builtin_mul_widen_even (tree
);
859 static tree
rs6000_builtin_mul_widen_odd (tree
);
860 static tree
rs6000_builtin_conversion (enum tree_code
, tree
);
861 static tree
rs6000_builtin_vec_perm (tree
, tree
*);
863 static void def_builtin (int, const char *, tree
, int);
864 static bool rs6000_vector_alignment_reachable (const_tree
, bool);
865 static void rs6000_init_builtins (void);
866 static rtx
rs6000_expand_unop_builtin (enum insn_code
, tree
, rtx
);
867 static rtx
rs6000_expand_binop_builtin (enum insn_code
, tree
, rtx
);
868 static rtx
rs6000_expand_ternop_builtin (enum insn_code
, tree
, rtx
);
869 static rtx
rs6000_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
870 static void altivec_init_builtins (void);
871 static void rs6000_common_init_builtins (void);
872 static void rs6000_init_libfuncs (void);
874 static void paired_init_builtins (void);
875 static rtx
paired_expand_builtin (tree
, rtx
, bool *);
876 static rtx
paired_expand_lv_builtin (enum insn_code
, tree
, rtx
);
877 static rtx
paired_expand_stv_builtin (enum insn_code
, tree
);
878 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
880 static void enable_mask_for_builtins (struct builtin_description
*, int,
881 enum rs6000_builtins
,
882 enum rs6000_builtins
);
883 static void spe_init_builtins (void);
884 static rtx
spe_expand_builtin (tree
, rtx
, bool *);
885 static rtx
spe_expand_stv_builtin (enum insn_code
, tree
);
886 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
887 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
888 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
889 static rs6000_stack_t
*rs6000_stack_info (void);
890 static void debug_stack_info (rs6000_stack_t
*);
892 static rtx
altivec_expand_builtin (tree
, rtx
, bool *);
893 static rtx
altivec_expand_ld_builtin (tree
, rtx
, bool *);
894 static rtx
altivec_expand_st_builtin (tree
, rtx
, bool *);
895 static rtx
altivec_expand_dst_builtin (tree
, rtx
, bool *);
896 static rtx
altivec_expand_abs_builtin (enum insn_code
, tree
, rtx
);
897 static rtx
altivec_expand_predicate_builtin (enum insn_code
,
898 const char *, tree
, rtx
);
899 static rtx
altivec_expand_stv_builtin (enum insn_code
, tree
);
900 static rtx
altivec_expand_vec_init_builtin (tree
, tree
, rtx
);
901 static rtx
altivec_expand_vec_set_builtin (tree
);
902 static rtx
altivec_expand_vec_ext_builtin (tree
, rtx
);
903 static int get_element_number (tree
, tree
);
904 static bool rs6000_handle_option (size_t, const char *, int);
905 static void rs6000_parse_tls_size_option (void);
906 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
907 static int first_altivec_reg_to_save (void);
908 static unsigned int compute_vrsave_mask (void);
909 static void compute_save_world_info (rs6000_stack_t
*info_ptr
);
910 static void is_altivec_return_reg (rtx
, void *);
911 static rtx
generate_set_vrsave (rtx
, rs6000_stack_t
*, int);
912 int easy_vector_constant (rtx
, enum machine_mode
);
913 static rtx
rs6000_dwarf_register_span (rtx
);
914 static void rs6000_init_dwarf_reg_sizes_extra (tree
);
915 static rtx
rs6000_legitimize_address (rtx
, rtx
, enum machine_mode
);
916 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
917 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
918 static rtx
rs6000_tls_get_addr (void);
919 static rtx
rs6000_got_sym (void);
920 static int rs6000_tls_symbol_ref_1 (rtx
*, void *);
921 static const char *rs6000_get_some_local_dynamic_name (void);
922 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
923 static rtx
rs6000_complex_function_value (enum machine_mode
);
924 static rtx
rs6000_spe_function_arg (CUMULATIVE_ARGS
*,
925 enum machine_mode
, tree
);
926 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*,
928 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*,
929 tree
, HOST_WIDE_INT
);
930 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*,
933 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*,
934 const_tree
, HOST_WIDE_INT
,
936 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
, int, bool);
937 static rtx
rs6000_mixed_function_arg (enum machine_mode
, tree
, int);
938 static void rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
);
939 static void setup_incoming_varargs (CUMULATIVE_ARGS
*,
940 enum machine_mode
, tree
,
942 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode
,
944 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
946 static const char *invalid_arg_for_unprototyped_fn (const_tree
, const_tree
, const_tree
);
948 static void macho_branch_islands (void);
949 static int no_previous_def (tree function_name
);
950 static tree
get_prev_label (tree function_name
);
951 static void rs6000_darwin_file_start (void);
954 static tree
rs6000_build_builtin_va_list (void);
955 static void rs6000_va_start (tree
, rtx
);
956 static tree
rs6000_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
957 static bool rs6000_must_pass_in_stack (enum machine_mode
, const_tree
);
958 static bool rs6000_scalar_mode_supported_p (enum machine_mode
);
959 static bool rs6000_vector_mode_supported_p (enum machine_mode
);
960 static int get_vec_cmp_insn (enum rtx_code
, enum machine_mode
,
962 static rtx
rs6000_emit_vector_compare (enum rtx_code
, rtx
, rtx
,
964 static int get_vsel_insn (enum machine_mode
);
965 static void rs6000_emit_vector_select (rtx
, rtx
, rtx
, rtx
);
966 static tree
rs6000_stack_protect_fail (void);
968 const int INSN_NOT_AVAILABLE
= -1;
969 static enum machine_mode
rs6000_eh_return_filter_mode (void);
971 /* Hash table stuff for keeping track of TOC entries. */
973 struct GTY(()) toc_hash_struct
975 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
976 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
978 enum machine_mode key_mode
;
982 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
984 /* Default register names. */
985 char rs6000_reg_names
[][8] =
987 "0", "1", "2", "3", "4", "5", "6", "7",
988 "8", "9", "10", "11", "12", "13", "14", "15",
989 "16", "17", "18", "19", "20", "21", "22", "23",
990 "24", "25", "26", "27", "28", "29", "30", "31",
991 "0", "1", "2", "3", "4", "5", "6", "7",
992 "8", "9", "10", "11", "12", "13", "14", "15",
993 "16", "17", "18", "19", "20", "21", "22", "23",
994 "24", "25", "26", "27", "28", "29", "30", "31",
995 "mq", "lr", "ctr","ap",
996 "0", "1", "2", "3", "4", "5", "6", "7",
998 /* AltiVec registers. */
999 "0", "1", "2", "3", "4", "5", "6", "7",
1000 "8", "9", "10", "11", "12", "13", "14", "15",
1001 "16", "17", "18", "19", "20", "21", "22", "23",
1002 "24", "25", "26", "27", "28", "29", "30", "31",
1004 /* SPE registers. */
1005 "spe_acc", "spefscr",
1006 /* Soft frame pointer. */
1010 #ifdef TARGET_REGNAMES
1011 static const char alt_reg_names
[][8] =
1013 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1014 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1015 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1016 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1017 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1018 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1019 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1020 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1021 "mq", "lr", "ctr", "ap",
1022 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1024 /* AltiVec registers. */
1025 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1026 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1027 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1028 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1030 /* SPE registers. */
1031 "spe_acc", "spefscr",
1032 /* Soft frame pointer. */
1037 #ifndef MASK_STRICT_ALIGN
1038 #define MASK_STRICT_ALIGN 0
1040 #ifndef TARGET_PROFILE_KERNEL
1041 #define TARGET_PROFILE_KERNEL 0
1044 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1045 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1047 /* Initialize the GCC target structure. */
1048 #undef TARGET_ATTRIBUTE_TABLE
1049 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1050 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1051 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1053 #undef TARGET_ASM_ALIGNED_DI_OP
1054 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1056 /* Default unaligned ops are only provided for ELF. Find the ops needed
1057 for non-ELF systems. */
1058 #ifndef OBJECT_FORMAT_ELF
1060 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1062 #undef TARGET_ASM_UNALIGNED_HI_OP
1063 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1064 #undef TARGET_ASM_UNALIGNED_SI_OP
1065 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1066 #undef TARGET_ASM_UNALIGNED_DI_OP
1067 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1070 #undef TARGET_ASM_UNALIGNED_HI_OP
1071 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1072 #undef TARGET_ASM_UNALIGNED_SI_OP
1073 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1074 #undef TARGET_ASM_UNALIGNED_DI_OP
1075 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1076 #undef TARGET_ASM_ALIGNED_DI_OP
1077 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1081 /* This hook deals with fixups for relocatable code and DI-mode objects
1083 #undef TARGET_ASM_INTEGER
1084 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1086 #ifdef HAVE_GAS_HIDDEN
1087 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1088 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1091 #undef TARGET_HAVE_TLS
1092 #define TARGET_HAVE_TLS HAVE_AS_TLS
1094 #undef TARGET_CANNOT_FORCE_CONST_MEM
1095 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
1097 #undef TARGET_ASM_FUNCTION_PROLOGUE
1098 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1099 #undef TARGET_ASM_FUNCTION_EPILOGUE
1100 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1102 #undef TARGET_LEGITIMIZE_ADDRESS
1103 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1105 #undef TARGET_SCHED_VARIABLE_ISSUE
1106 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1108 #undef TARGET_SCHED_ISSUE_RATE
1109 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1110 #undef TARGET_SCHED_ADJUST_COST
1111 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1112 #undef TARGET_SCHED_ADJUST_PRIORITY
1113 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1114 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1115 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1116 #undef TARGET_SCHED_INIT
1117 #define TARGET_SCHED_INIT rs6000_sched_init
1118 #undef TARGET_SCHED_FINISH
1119 #define TARGET_SCHED_FINISH rs6000_sched_finish
1120 #undef TARGET_SCHED_REORDER
1121 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1122 #undef TARGET_SCHED_REORDER2
1123 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1125 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1126 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1128 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1129 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1131 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1132 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1133 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1134 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1135 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1136 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1137 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1138 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1140 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1141 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1142 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
1143 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
1144 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
1145 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
1146 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
1147 #define TARGET_VECTORIZE_BUILTIN_CONVERSION rs6000_builtin_conversion
1148 #undef TARGET_VECTORIZE_BUILTIN_VEC_PERM
1149 #define TARGET_VECTORIZE_BUILTIN_VEC_PERM rs6000_builtin_vec_perm
1151 #undef TARGET_VECTOR_ALIGNMENT_REACHABLE
1152 #define TARGET_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1154 #undef TARGET_INIT_BUILTINS
1155 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1157 #undef TARGET_EXPAND_BUILTIN
1158 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1160 #undef TARGET_MANGLE_TYPE
1161 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1163 #undef TARGET_INIT_LIBFUNCS
1164 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1167 #undef TARGET_BINDS_LOCAL_P
1168 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1171 #undef TARGET_MS_BITFIELD_LAYOUT_P
1172 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1174 #undef TARGET_ASM_OUTPUT_MI_THUNK
1175 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1177 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1178 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1180 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1181 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1183 #undef TARGET_INVALID_WITHIN_DOLOOP
1184 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1186 #undef TARGET_RTX_COSTS
1187 #define TARGET_RTX_COSTS rs6000_rtx_costs
1188 #undef TARGET_ADDRESS_COST
1189 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
1191 #undef TARGET_DWARF_REGISTER_SPAN
1192 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1194 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1195 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1197 /* On rs6000, function arguments are promoted, as are function return
1199 #undef TARGET_PROMOTE_FUNCTION_ARGS
1200 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
1201 #undef TARGET_PROMOTE_FUNCTION_RETURN
1202 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
1204 #undef TARGET_RETURN_IN_MEMORY
1205 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1207 #undef TARGET_SETUP_INCOMING_VARARGS
1208 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1210 /* Always strict argument naming on rs6000. */
1211 #undef TARGET_STRICT_ARGUMENT_NAMING
1212 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1213 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1214 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1215 #undef TARGET_SPLIT_COMPLEX_ARG
1216 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1217 #undef TARGET_MUST_PASS_IN_STACK
1218 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1219 #undef TARGET_PASS_BY_REFERENCE
1220 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1221 #undef TARGET_ARG_PARTIAL_BYTES
1222 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1224 #undef TARGET_BUILD_BUILTIN_VA_LIST
1225 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1227 #undef TARGET_EXPAND_BUILTIN_VA_START
1228 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1230 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1231 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1233 #undef TARGET_EH_RETURN_FILTER_MODE
1234 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1236 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1237 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1239 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1240 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1242 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1243 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1245 #undef TARGET_HANDLE_OPTION
1246 #define TARGET_HANDLE_OPTION rs6000_handle_option
1248 #undef TARGET_DEFAULT_TARGET_FLAGS
1249 #define TARGET_DEFAULT_TARGET_FLAGS \
1252 #undef TARGET_STACK_PROTECT_FAIL
1253 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1255 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1256 The PowerPC architecture requires only weak consistency among
1257 processors--that is, memory accesses between processors need not be
1258 sequentially consistent and memory accesses among processors can occur
1259 in any order. The ability to order memory accesses weakly provides
1260 opportunities for more efficient use of the system bus. Unless a
1261 dependency exists, the 604e allows read operations to precede store
1263 #undef TARGET_RELAXED_ORDERING
1264 #define TARGET_RELAXED_ORDERING true
1267 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1268 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1271 /* Use a 32-bit anchor range. This leads to sequences like:
1273 addis tmp,anchor,high
1276 where tmp itself acts as an anchor, and can be shared between
1277 accesses to the same 64k page. */
1278 #undef TARGET_MIN_ANCHOR_OFFSET
1279 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1280 #undef TARGET_MAX_ANCHOR_OFFSET
1281 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1282 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1283 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1285 #undef TARGET_BUILTIN_RECIPROCAL
1286 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1288 #undef TARGET_EXPAND_TO_RTL_HOOK
1289 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1291 #undef TARGET_INSTANTIATE_DECLS
1292 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1294 struct gcc_target targetm
= TARGET_INITIALIZER
;
1297 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1300 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1302 /* The GPRs can hold any mode, but values bigger than one register
1303 cannot go past R31. */
1304 if (INT_REGNO_P (regno
))
1305 return INT_REGNO_P (regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1);
1307 /* The float registers can only hold floating modes and DImode.
1308 This excludes the 32-bit decimal float mode for now. */
1309 if (FP_REGNO_P (regno
))
1311 ((SCALAR_FLOAT_MODE_P (mode
)
1312 && (mode
!= TDmode
|| (regno
% 2) == 0)
1313 && FP_REGNO_P (regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1))
1314 || (GET_MODE_CLASS (mode
) == MODE_INT
1315 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
1316 || (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
1317 && PAIRED_VECTOR_MODE (mode
)));
1319 /* The CR register can only hold CC modes. */
1320 if (CR_REGNO_P (regno
))
1321 return GET_MODE_CLASS (mode
) == MODE_CC
;
1323 if (XER_REGNO_P (regno
))
1324 return mode
== PSImode
;
1326 /* AltiVec only in AldyVec registers. */
1327 if (ALTIVEC_REGNO_P (regno
))
1328 return ALTIVEC_VECTOR_MODE (mode
);
1330 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1331 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1334 /* We cannot put TImode anywhere except general register and it must be
1335 able to fit within the register set. */
1337 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1340 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1342 rs6000_init_hard_regno_mode_ok (void)
1346 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
1347 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1348 if (rs6000_hard_regno_mode_ok (r
, (enum machine_mode
) m
))
1349 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
1353 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
1356 darwin_rs6000_override_options (void)
1358 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
1360 rs6000_altivec_abi
= 1;
1361 TARGET_ALTIVEC_VRSAVE
= 1;
1362 if (DEFAULT_ABI
== ABI_DARWIN
)
1364 if (MACHO_DYNAMIC_NO_PIC_P
)
1367 warning (0, "-mdynamic-no-pic overrides -fpic or -fPIC");
1370 else if (flag_pic
== 1)
1375 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
1377 target_flags
|= MASK_POWERPC64
;
1378 warning (0, "-m64 requires PowerPC64 architecture, enabling");
1382 rs6000_default_long_calls
= 1;
1383 target_flags
|= MASK_SOFT_FLOAT
;
1386 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
1388 if (!flag_mkernel
&& !flag_apple_kext
1390 && ! (target_flags_explicit
& MASK_ALTIVEC
))
1391 target_flags
|= MASK_ALTIVEC
;
1393 /* Unless the user (not the configurer) has explicitly overridden
1394 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
1395 G4 unless targetting the kernel. */
1398 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
1399 && ! (target_flags_explicit
& MASK_ALTIVEC
)
1400 && ! rs6000_select
[1].string
)
1402 target_flags
|= MASK_ALTIVEC
;
1407 /* If not otherwise specified by a target, make 'long double' equivalent to
1410 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1411 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1414 /* Override command line options. Mostly we process the processor
1415 type and sometimes adjust other TARGET_ options. */
1418 rs6000_override_options (const char *default_cpu
)
1421 struct rs6000_cpu_select
*ptr
;
1424 /* Simplifications for entries below. */
1427 POWERPC_BASE_MASK
= MASK_POWERPC
| MASK_NEW_MNEMONICS
,
1428 POWERPC_7400_MASK
= POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_ALTIVEC
1431 /* This table occasionally claims that a processor does not support
1432 a particular feature even though it does, but the feature is slower
1433 than the alternative. Thus, it shouldn't be relied on as a
1434 complete description of the processor's support.
1436 Please keep this list in order, and don't forget to update the
1437 documentation in invoke.texi when adding a new processor or
1441 const char *const name
; /* Canonical processor name. */
1442 const enum processor_type processor
; /* Processor type enum value. */
1443 const int target_enable
; /* Target flags to enable. */
1444 } const processor_target_table
[]
1445 = {{"401", PROCESSOR_PPC403
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1446 {"403", PROCESSOR_PPC403
,
1447 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_STRICT_ALIGN
},
1448 {"405", PROCESSOR_PPC405
,
1449 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_MULHW
| MASK_DLMZB
},
1450 {"405fp", PROCESSOR_PPC405
,
1451 POWERPC_BASE_MASK
| MASK_MULHW
| MASK_DLMZB
},
1452 {"440", PROCESSOR_PPC440
,
1453 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_MULHW
| MASK_DLMZB
},
1454 {"440fp", PROCESSOR_PPC440
,
1455 POWERPC_BASE_MASK
| MASK_MULHW
| MASK_DLMZB
},
1456 {"464", PROCESSOR_PPC440
,
1457 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_MULHW
| MASK_DLMZB
},
1458 {"464fp", PROCESSOR_PPC440
,
1459 POWERPC_BASE_MASK
| MASK_MULHW
| MASK_DLMZB
},
1460 {"505", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
},
1461 {"601", PROCESSOR_PPC601
,
1462 MASK_POWER
| POWERPC_BASE_MASK
| MASK_MULTIPLE
| MASK_STRING
},
1463 {"602", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1464 {"603", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1465 {"603e", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1466 {"604", PROCESSOR_PPC604
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1467 {"604e", PROCESSOR_PPC604e
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1468 {"620", PROCESSOR_PPC620
,
1469 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1470 {"630", PROCESSOR_PPC630
,
1471 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1472 {"740", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1473 {"7400", PROCESSOR_PPC7400
, POWERPC_7400_MASK
},
1474 {"7450", PROCESSOR_PPC7450
, POWERPC_7400_MASK
},
1475 {"750", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1476 {"801", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1477 {"821", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1478 {"823", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1479 {"8540", PROCESSOR_PPC8540
, POWERPC_BASE_MASK
| MASK_STRICT_ALIGN
},
1480 /* 8548 has a dummy entry for now. */
1481 {"8548", PROCESSOR_PPC8540
, POWERPC_BASE_MASK
| MASK_STRICT_ALIGN
},
1482 {"e300c2", PROCESSOR_PPCE300C2
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1483 {"e300c3", PROCESSOR_PPCE300C3
, POWERPC_BASE_MASK
},
1484 {"e500mc", PROCESSOR_PPCE500MC
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1485 {"860", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1486 {"970", PROCESSOR_POWER4
,
1487 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1488 {"cell", PROCESSOR_CELL
,
1489 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1490 {"common", PROCESSOR_COMMON
, MASK_NEW_MNEMONICS
},
1491 {"ec603e", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1492 {"G3", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1493 {"G4", PROCESSOR_PPC7450
, POWERPC_7400_MASK
},
1494 {"G5", PROCESSOR_POWER4
,
1495 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1496 {"power", PROCESSOR_POWER
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1497 {"power2", PROCESSOR_POWER
,
1498 MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
},
1499 {"power3", PROCESSOR_PPC630
,
1500 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1501 {"power4", PROCESSOR_POWER4
,
1502 POWERPC_BASE_MASK
| MASK_POWERPC64
| MASK_PPC_GPOPT
| MASK_PPC_GFXOPT
1504 {"power5", PROCESSOR_POWER5
,
1505 POWERPC_BASE_MASK
| MASK_POWERPC64
| MASK_PPC_GPOPT
| MASK_PPC_GFXOPT
1506 | MASK_MFCRF
| MASK_POPCNTB
},
1507 {"power5+", PROCESSOR_POWER5
,
1508 POWERPC_BASE_MASK
| MASK_POWERPC64
| MASK_PPC_GPOPT
| MASK_PPC_GFXOPT
1509 | MASK_MFCRF
| MASK_POPCNTB
| MASK_FPRND
},
1510 {"power6", PROCESSOR_POWER6
,
1511 POWERPC_BASE_MASK
| MASK_POWERPC64
| MASK_PPC_GPOPT
| MASK_PPC_GFXOPT
1512 | MASK_MFCRF
| MASK_POPCNTB
| MASK_FPRND
| MASK_CMPB
| MASK_DFP
},
1513 {"power6x", PROCESSOR_POWER6
,
1514 POWERPC_BASE_MASK
| MASK_POWERPC64
| MASK_PPC_GPOPT
| MASK_PPC_GFXOPT
1515 | MASK_MFCRF
| MASK_POPCNTB
| MASK_FPRND
| MASK_CMPB
| MASK_DFP
1517 {"power7", PROCESSOR_POWER5
,
1518 POWERPC_7400_MASK
| MASK_POWERPC64
| MASK_PPC_GPOPT
| MASK_MFCRF
1519 | MASK_POPCNTB
| MASK_FPRND
| MASK_CMPB
| MASK_DFP
},
1520 {"powerpc", PROCESSOR_POWERPC
, POWERPC_BASE_MASK
},
1521 {"powerpc64", PROCESSOR_POWERPC64
,
1522 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1523 {"rios", PROCESSOR_RIOS1
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1524 {"rios1", PROCESSOR_RIOS1
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1525 {"rios2", PROCESSOR_RIOS2
,
1526 MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
},
1527 {"rsc", PROCESSOR_PPC601
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1528 {"rsc1", PROCESSOR_PPC601
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1529 {"rs64", PROCESSOR_RS64A
,
1530 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
}
1533 const size_t ptt_size
= ARRAY_SIZE (processor_target_table
);
1535 /* Some OSs don't support saving the high part of 64-bit registers on
1536 context switch. Other OSs don't support saving Altivec registers.
1537 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1538 settings; if the user wants either, the user must explicitly specify
1539 them and we won't interfere with the user's specification. */
1542 POWER_MASKS
= MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
,
1543 POWERPC_MASKS
= (POWERPC_BASE_MASK
| MASK_PPC_GPOPT
| MASK_STRICT_ALIGN
1544 | MASK_PPC_GFXOPT
| MASK_POWERPC64
| MASK_ALTIVEC
1545 | MASK_MFCRF
| MASK_POPCNTB
| MASK_FPRND
| MASK_MULHW
1546 | MASK_DLMZB
| MASK_CMPB
| MASK_MFPGPR
| MASK_DFP
)
1549 set_masks
= POWER_MASKS
| POWERPC_MASKS
| MASK_SOFT_FLOAT
;
1550 #ifdef OS_MISSING_POWERPC64
1551 if (OS_MISSING_POWERPC64
)
1552 set_masks
&= ~MASK_POWERPC64
;
1554 #ifdef OS_MISSING_ALTIVEC
1555 if (OS_MISSING_ALTIVEC
)
1556 set_masks
&= ~MASK_ALTIVEC
;
1559 /* Don't override by the processor default if given explicitly. */
1560 set_masks
&= ~target_flags_explicit
;
1562 /* Identify the processor type. */
1563 rs6000_select
[0].string
= default_cpu
;
1564 rs6000_cpu
= TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
;
1566 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
1568 ptr
= &rs6000_select
[i
];
1569 if (ptr
->string
!= (char *)0 && ptr
->string
[0] != '\0')
1571 for (j
= 0; j
< ptt_size
; j
++)
1572 if (! strcmp (ptr
->string
, processor_target_table
[j
].name
))
1574 if (ptr
->set_tune_p
)
1575 rs6000_cpu
= processor_target_table
[j
].processor
;
1577 if (ptr
->set_arch_p
)
1579 target_flags
&= ~set_masks
;
1580 target_flags
|= (processor_target_table
[j
].target_enable
1587 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
1591 if ((TARGET_E500
|| rs6000_cpu
== PROCESSOR_PPCE500MC
)
1592 && !rs6000_explicit_options
.isel
)
1595 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
1596 || rs6000_cpu
== PROCESSOR_PPCE500MC
)
1599 error ("AltiVec not supported in this target");
1601 error ("Spe not supported in this target");
1604 /* Disable Cell microcode if we are optimizing for the Cell
1605 and not optimizing for size. */
1606 if (rs6000_gen_cell_microcode
== -1)
1607 rs6000_gen_cell_microcode
= !(rs6000_cpu
== PROCESSOR_CELL
1610 /* If we are optimizing big endian systems for space, use the load/store
1611 multiple and string instructions unless we are not generating
1613 if (BYTES_BIG_ENDIAN
&& optimize_size
&& !rs6000_gen_cell_microcode
)
1614 target_flags
|= ~target_flags_explicit
& (MASK_MULTIPLE
| MASK_STRING
);
1616 /* Don't allow -mmultiple or -mstring on little endian systems
1617 unless the cpu is a 750, because the hardware doesn't support the
1618 instructions used in little endian mode, and causes an alignment
1619 trap. The 750 does not cause an alignment trap (except when the
1620 target is unaligned). */
1622 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
1624 if (TARGET_MULTIPLE
)
1626 target_flags
&= ~MASK_MULTIPLE
;
1627 if ((target_flags_explicit
& MASK_MULTIPLE
) != 0)
1628 warning (0, "-mmultiple is not supported on little endian systems");
1633 target_flags
&= ~MASK_STRING
;
1634 if ((target_flags_explicit
& MASK_STRING
) != 0)
1635 warning (0, "-mstring is not supported on little endian systems");
1639 /* Set debug flags */
1640 if (rs6000_debug_name
)
1642 if (! strcmp (rs6000_debug_name
, "all"))
1643 rs6000_debug_stack
= rs6000_debug_arg
= 1;
1644 else if (! strcmp (rs6000_debug_name
, "stack"))
1645 rs6000_debug_stack
= 1;
1646 else if (! strcmp (rs6000_debug_name
, "arg"))
1647 rs6000_debug_arg
= 1;
1649 error ("unknown -mdebug-%s switch", rs6000_debug_name
);
1652 if (rs6000_traceback_name
)
1654 if (! strncmp (rs6000_traceback_name
, "full", 4))
1655 rs6000_traceback
= traceback_full
;
1656 else if (! strncmp (rs6000_traceback_name
, "part", 4))
1657 rs6000_traceback
= traceback_part
;
1658 else if (! strncmp (rs6000_traceback_name
, "no", 2))
1659 rs6000_traceback
= traceback_none
;
1661 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1662 rs6000_traceback_name
);
1665 if (!rs6000_explicit_options
.long_double
)
1666 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
1668 #ifndef POWERPC_LINUX
1669 if (!rs6000_explicit_options
.ieee
)
1670 rs6000_ieeequad
= 1;
1673 /* Enable Altivec ABI for AIX -maltivec. */
1674 if (TARGET_XCOFF
&& TARGET_ALTIVEC
)
1675 rs6000_altivec_abi
= 1;
1677 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
1678 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
1679 be explicitly overridden in either case. */
1682 if (!rs6000_explicit_options
.altivec_abi
1683 && (TARGET_64BIT
|| TARGET_ALTIVEC
))
1684 rs6000_altivec_abi
= 1;
1686 /* Enable VRSAVE for AltiVec ABI, unless explicitly overridden. */
1687 if (!rs6000_explicit_options
.vrsave
)
1688 TARGET_ALTIVEC_VRSAVE
= rs6000_altivec_abi
;
1691 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1692 if (DEFAULT_ABI
== ABI_DARWIN
&& TARGET_64BIT
)
1694 rs6000_darwin64_abi
= 1;
1696 darwin_one_byte_bool
= 1;
1698 /* Default to natural alignment, for better performance. */
1699 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
1702 /* Place FP constants in the constant pool instead of TOC
1703 if section anchors enabled. */
1704 if (flag_section_anchors
)
1705 TARGET_NO_FP_IN_TOC
= 1;
1707 /* Handle -mtls-size option. */
1708 rs6000_parse_tls_size_option ();
1710 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1711 SUBTARGET_OVERRIDE_OPTIONS
;
1713 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1714 SUBSUBTARGET_OVERRIDE_OPTIONS
;
1716 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1717 SUB3TARGET_OVERRIDE_OPTIONS
;
1720 if (TARGET_E500
|| rs6000_cpu
== PROCESSOR_PPCE500MC
)
1722 /* The e500 and e500mc do not have string instructions, and we set
1723 MASK_STRING above when optimizing for size. */
1724 if ((target_flags
& MASK_STRING
) != 0)
1725 target_flags
= target_flags
& ~MASK_STRING
;
1727 else if (rs6000_select
[1].string
!= NULL
)
1729 /* For the powerpc-eabispe configuration, we set all these by
1730 default, so let's unset them if we manually set another
1731 CPU that is not the E500. */
1732 if (!rs6000_explicit_options
.spe_abi
)
1734 if (!rs6000_explicit_options
.spe
)
1736 if (!rs6000_explicit_options
.float_gprs
)
1737 rs6000_float_gprs
= 0;
1738 if (!rs6000_explicit_options
.isel
)
1742 /* Detect invalid option combinations with E500. */
1745 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
1746 && rs6000_cpu
!= PROCESSOR_POWER5
1747 && rs6000_cpu
!= PROCESSOR_POWER6
1748 && rs6000_cpu
!= PROCESSOR_CELL
);
1749 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
1750 || rs6000_cpu
== PROCESSOR_POWER5
);
1751 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
1752 || rs6000_cpu
== PROCESSOR_POWER5
1753 || rs6000_cpu
== PROCESSOR_POWER6
);
1755 rs6000_sched_restricted_insns_priority
1756 = (rs6000_sched_groups
? 1 : 0);
1758 /* Handle -msched-costly-dep option. */
1759 rs6000_sched_costly_dep
1760 = (rs6000_sched_groups
? store_to_load_dep_costly
: no_dep_costly
);
1762 if (rs6000_sched_costly_dep_str
)
1764 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
1765 rs6000_sched_costly_dep
= no_dep_costly
;
1766 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
1767 rs6000_sched_costly_dep
= all_deps_costly
;
1768 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
1769 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
1770 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
1771 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
1773 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
1774 atoi (rs6000_sched_costly_dep_str
));
1777 /* Handle -minsert-sched-nops option. */
1778 rs6000_sched_insert_nops
1779 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
1781 if (rs6000_sched_insert_nops_str
)
1783 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
1784 rs6000_sched_insert_nops
= sched_finish_none
;
1785 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
1786 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
1787 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
1788 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
1790 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
1791 atoi (rs6000_sched_insert_nops_str
));
1794 #ifdef TARGET_REGNAMES
1795 /* If the user desires alternate register names, copy in the
1796 alternate names now. */
1797 if (TARGET_REGNAMES
)
1798 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
1801 /* Set aix_struct_return last, after the ABI is determined.
1802 If -maix-struct-return or -msvr4-struct-return was explicitly
1803 used, don't override with the ABI default. */
1804 if (!rs6000_explicit_options
.aix_struct_ret
)
1805 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
1807 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
1808 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
1811 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
1813 /* We can only guarantee the availability of DI pseudo-ops when
1814 assembling for 64-bit targets. */
1817 targetm
.asm_out
.aligned_op
.di
= NULL
;
1818 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1821 /* Set branch target alignment, if not optimizing for size. */
1824 /* Cell wants to be aligned 8byte for dual issue. */
1825 if (rs6000_cpu
== PROCESSOR_CELL
)
1827 if (align_functions
<= 0)
1828 align_functions
= 8;
1829 if (align_jumps
<= 0)
1831 if (align_loops
<= 0)
1834 if (rs6000_align_branch_targets
)
1836 if (align_functions
<= 0)
1837 align_functions
= 16;
1838 if (align_jumps
<= 0)
1840 if (align_loops
<= 0)
1843 if (align_jumps_max_skip
<= 0)
1844 align_jumps_max_skip
= 15;
1845 if (align_loops_max_skip
<= 0)
1846 align_loops_max_skip
= 15;
1849 /* Arrange to save and restore machine status around nested functions. */
1850 init_machine_status
= rs6000_init_machine_status
;
1852 /* We should always be splitting complex arguments, but we can't break
1853 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1854 if (DEFAULT_ABI
!= ABI_AIX
)
1855 targetm
.calls
.split_complex_arg
= NULL
;
1857 /* Initialize rs6000_cost with the appropriate target costs. */
1859 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
1863 case PROCESSOR_RIOS1
:
1864 rs6000_cost
= &rios1_cost
;
1867 case PROCESSOR_RIOS2
:
1868 rs6000_cost
= &rios2_cost
;
1871 case PROCESSOR_RS64A
:
1872 rs6000_cost
= &rs64a_cost
;
1875 case PROCESSOR_MPCCORE
:
1876 rs6000_cost
= &mpccore_cost
;
1879 case PROCESSOR_PPC403
:
1880 rs6000_cost
= &ppc403_cost
;
1883 case PROCESSOR_PPC405
:
1884 rs6000_cost
= &ppc405_cost
;
1887 case PROCESSOR_PPC440
:
1888 rs6000_cost
= &ppc440_cost
;
1891 case PROCESSOR_PPC601
:
1892 rs6000_cost
= &ppc601_cost
;
1895 case PROCESSOR_PPC603
:
1896 rs6000_cost
= &ppc603_cost
;
1899 case PROCESSOR_PPC604
:
1900 rs6000_cost
= &ppc604_cost
;
1903 case PROCESSOR_PPC604e
:
1904 rs6000_cost
= &ppc604e_cost
;
1907 case PROCESSOR_PPC620
:
1908 rs6000_cost
= &ppc620_cost
;
1911 case PROCESSOR_PPC630
:
1912 rs6000_cost
= &ppc630_cost
;
1915 case PROCESSOR_CELL
:
1916 rs6000_cost
= &ppccell_cost
;
1919 case PROCESSOR_PPC750
:
1920 case PROCESSOR_PPC7400
:
1921 rs6000_cost
= &ppc750_cost
;
1924 case PROCESSOR_PPC7450
:
1925 rs6000_cost
= &ppc7450_cost
;
1928 case PROCESSOR_PPC8540
:
1929 rs6000_cost
= &ppc8540_cost
;
1932 case PROCESSOR_PPCE300C2
:
1933 case PROCESSOR_PPCE300C3
:
1934 rs6000_cost
= &ppce300c2c3_cost
;
1937 case PROCESSOR_PPCE500MC
:
1938 rs6000_cost
= &ppce500mc_cost
;
1941 case PROCESSOR_POWER4
:
1942 case PROCESSOR_POWER5
:
1943 rs6000_cost
= &power4_cost
;
1946 case PROCESSOR_POWER6
:
1947 rs6000_cost
= &power6_cost
;
1954 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES
))
1955 set_param_value ("simultaneous-prefetches",
1956 rs6000_cost
->simultaneous_prefetches
);
1957 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE
))
1958 set_param_value ("l1-cache-size", rs6000_cost
->l1_cache_size
);
1959 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE
))
1960 set_param_value ("l1-cache-line-size", rs6000_cost
->cache_line_size
);
1961 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE
))
1962 set_param_value ("l2-cache-size", rs6000_cost
->l2_cache_size
);
1964 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
1965 can be optimized to ap = __builtin_next_arg (0). */
1966 if (DEFAULT_ABI
!= ABI_V4
)
1967 targetm
.expand_builtin_va_start
= NULL
;
1969 /* Set up single/double float flags.
1970 If TARGET_HARD_FLOAT is set, but neither single or double is set,
1971 then set both flags. */
1972 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
1973 && rs6000_single_float
== 0 && rs6000_double_float
== 0)
1974 rs6000_single_float
= rs6000_double_float
= 1;
1976 /* Reset single and double FP flags if target is E500. */
1979 rs6000_single_float
= rs6000_double_float
= 0;
1980 if (TARGET_E500_SINGLE
)
1981 rs6000_single_float
= 1;
1982 if (TARGET_E500_DOUBLE
)
1983 rs6000_single_float
= rs6000_double_float
= 1;
1986 /* If not explicitly specified via option, decide whether to generate indexed
1987 load/store instructions. */
1988 if (TARGET_AVOID_XFORM
== -1)
1989 /* Avoid indexed addressing when targeting Power6 in order to avoid
1990 the DERAT mispredict penalty. */
1991 TARGET_AVOID_XFORM
= (rs6000_cpu
== PROCESSOR_POWER6
&& TARGET_CMPB
);
1993 rs6000_init_hard_regno_mode_ok ();
1996 /* Implement targetm.vectorize.builtin_mask_for_load. */
1998 rs6000_builtin_mask_for_load (void)
2001 return altivec_builtin_mask_for_load
;
2006 /* Implement targetm.vectorize.builtin_conversion.
2007 Returns a decl of a function that implements conversion of an integer vector
2008 into a floating-point vector, or vice-versa. TYPE is the type of the integer
2009 side of the conversion.
2010 Return NULL_TREE if it is not available. */
2012 rs6000_builtin_conversion (enum tree_code code
, tree type
)
2014 if (!TARGET_ALTIVEC
)
2019 case FIX_TRUNC_EXPR
:
2020 switch (TYPE_MODE (type
))
2023 return TYPE_UNSIGNED (type
)
2024 ? rs6000_builtin_decls
[ALTIVEC_BUILTIN_VCTUXS
]
2025 : rs6000_builtin_decls
[ALTIVEC_BUILTIN_VCTSXS
];
2031 switch (TYPE_MODE (type
))
2034 return TYPE_UNSIGNED (type
)
2035 ? rs6000_builtin_decls
[ALTIVEC_BUILTIN_VCFUX
]
2036 : rs6000_builtin_decls
[ALTIVEC_BUILTIN_VCFSX
];
2046 /* Implement targetm.vectorize.builtin_mul_widen_even. */
2048 rs6000_builtin_mul_widen_even (tree type
)
2050 if (!TARGET_ALTIVEC
)
2053 switch (TYPE_MODE (type
))
2056 return TYPE_UNSIGNED (type
)
2057 ? rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULEUH
]
2058 : rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULESH
];
2061 return TYPE_UNSIGNED (type
)
2062 ? rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULEUB
]
2063 : rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULESB
];
2069 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
2071 rs6000_builtin_mul_widen_odd (tree type
)
2073 if (!TARGET_ALTIVEC
)
2076 switch (TYPE_MODE (type
))
2079 return TYPE_UNSIGNED (type
)
2080 ? rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOUH
]
2081 : rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOSH
];
2084 return TYPE_UNSIGNED (type
)
2085 ? rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOUB
]
2086 : rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOSB
];
2093 /* Return true iff, data reference of TYPE can reach vector alignment (16)
2094 after applying N number of iterations. This routine does not determine
2095 how may iterations are required to reach desired alignment. */
2098 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
2105 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
2108 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
2118 /* Assuming that all other types are naturally aligned. CHECKME! */
2123 /* Implement targetm.vectorize.builtin_vec_perm. */
2125 rs6000_builtin_vec_perm (tree type
, tree
*mask_element_type
)
2129 *mask_element_type
= unsigned_char_type_node
;
2131 switch (TYPE_MODE (type
))
2134 d
= rs6000_builtin_decls
[ALTIVEC_BUILTIN_VPERM_16QI
];
2138 d
= rs6000_builtin_decls
[ALTIVEC_BUILTIN_VPERM_8HI
];
2142 d
= rs6000_builtin_decls
[ALTIVEC_BUILTIN_VPERM_4SI
];
2146 d
= rs6000_builtin_decls
[ALTIVEC_BUILTIN_VPERM_4SF
];
2157 /* Handle generic options of the form -mfoo=yes/no.
2158 NAME is the option name.
2159 VALUE is the option value.
2160 FLAG is the pointer to the flag where to store a 1 or 0, depending on
2161 whether the option value is 'yes' or 'no' respectively. */
2163 rs6000_parse_yes_no_option (const char *name
, const char *value
, int *flag
)
2167 else if (!strcmp (value
, "yes"))
2169 else if (!strcmp (value
, "no"))
2172 error ("unknown -m%s= option specified: '%s'", name
, value
);
2175 /* Validate and record the size specified with the -mtls-size option. */
2178 rs6000_parse_tls_size_option (void)
2180 if (rs6000_tls_size_string
== 0)
2182 else if (strcmp (rs6000_tls_size_string
, "16") == 0)
2183 rs6000_tls_size
= 16;
2184 else if (strcmp (rs6000_tls_size_string
, "32") == 0)
2185 rs6000_tls_size
= 32;
2186 else if (strcmp (rs6000_tls_size_string
, "64") == 0)
2187 rs6000_tls_size
= 64;
2189 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string
);
2193 optimization_options (int level ATTRIBUTE_UNUSED
, int size ATTRIBUTE_UNUSED
)
2195 if (DEFAULT_ABI
== ABI_DARWIN
)
2196 /* The Darwin libraries never set errno, so we might as well
2197 avoid calling them when that's the only reason we would. */
2198 flag_errno_math
= 0;
2200 /* Double growth factor to counter reduced min jump length. */
2201 set_param_value ("max-grow-copy-bb-insns", 16);
2203 /* Enable section anchors by default.
2204 Skip section anchors for Objective C and Objective C++
2205 until front-ends fixed. */
2206 if (!TARGET_MACHO
&& lang_hooks
.name
[4] != 'O')
2207 flag_section_anchors
= 2;
2210 static enum fpu_type_t
2211 rs6000_parse_fpu_option (const char *option
)
2213 if (!strcmp("none", option
)) return FPU_NONE
;
2214 if (!strcmp("sp_lite", option
)) return FPU_SF_LITE
;
2215 if (!strcmp("dp_lite", option
)) return FPU_DF_LITE
;
2216 if (!strcmp("sp_full", option
)) return FPU_SF_FULL
;
2217 if (!strcmp("dp_full", option
)) return FPU_DF_FULL
;
2218 error("unknown value %s for -mfpu", option
);
2222 /* Implement TARGET_HANDLE_OPTION. */
2225 rs6000_handle_option (size_t code
, const char *arg
, int value
)
2227 enum fpu_type_t fpu_type
= FPU_NONE
;
2232 target_flags
&= ~(MASK_POWER
| MASK_POWER2
2233 | MASK_MULTIPLE
| MASK_STRING
);
2234 target_flags_explicit
|= (MASK_POWER
| MASK_POWER2
2235 | MASK_MULTIPLE
| MASK_STRING
);
2237 case OPT_mno_powerpc
:
2238 target_flags
&= ~(MASK_POWERPC
| MASK_PPC_GPOPT
2239 | MASK_PPC_GFXOPT
| MASK_POWERPC64
);
2240 target_flags_explicit
|= (MASK_POWERPC
| MASK_PPC_GPOPT
2241 | MASK_PPC_GFXOPT
| MASK_POWERPC64
);
2244 target_flags
&= ~MASK_MINIMAL_TOC
;
2245 TARGET_NO_FP_IN_TOC
= 0;
2246 TARGET_NO_SUM_IN_TOC
= 0;
2247 target_flags_explicit
|= MASK_MINIMAL_TOC
;
2248 #ifdef TARGET_USES_SYSV4_OPT
2249 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
2250 just the same as -mminimal-toc. */
2251 target_flags
|= MASK_MINIMAL_TOC
;
2252 target_flags_explicit
|= MASK_MINIMAL_TOC
;
2256 #ifdef TARGET_USES_SYSV4_OPT
2258 /* Make -mtoc behave like -mminimal-toc. */
2259 target_flags
|= MASK_MINIMAL_TOC
;
2260 target_flags_explicit
|= MASK_MINIMAL_TOC
;
2264 #ifdef TARGET_USES_AIX64_OPT
2269 target_flags
|= MASK_POWERPC64
| MASK_POWERPC
;
2270 target_flags
|= ~target_flags_explicit
& MASK_PPC_GFXOPT
;
2271 target_flags_explicit
|= MASK_POWERPC64
| MASK_POWERPC
;
2274 #ifdef TARGET_USES_AIX64_OPT
2279 target_flags
&= ~MASK_POWERPC64
;
2280 target_flags_explicit
|= MASK_POWERPC64
;
2283 case OPT_minsert_sched_nops_
:
2284 rs6000_sched_insert_nops_str
= arg
;
2287 case OPT_mminimal_toc
:
2290 TARGET_NO_FP_IN_TOC
= 0;
2291 TARGET_NO_SUM_IN_TOC
= 0;
2298 target_flags
|= (MASK_MULTIPLE
| MASK_STRING
);
2299 target_flags_explicit
|= (MASK_MULTIPLE
| MASK_STRING
);
2306 target_flags
|= (MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
);
2307 target_flags_explicit
|= (MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
);
2311 case OPT_mpowerpc_gpopt
:
2312 case OPT_mpowerpc_gfxopt
:
2315 target_flags
|= MASK_POWERPC
;
2316 target_flags_explicit
|= MASK_POWERPC
;
2320 case OPT_maix_struct_return
:
2321 case OPT_msvr4_struct_return
:
2322 rs6000_explicit_options
.aix_struct_ret
= true;
2326 rs6000_explicit_options
.vrsave
= true;
2327 TARGET_ALTIVEC_VRSAVE
= value
;
2331 rs6000_explicit_options
.vrsave
= true;
2332 rs6000_parse_yes_no_option ("vrsave", arg
, &(TARGET_ALTIVEC_VRSAVE
));
2336 rs6000_explicit_options
.isel
= true;
2337 rs6000_isel
= value
;
2341 rs6000_explicit_options
.isel
= true;
2342 rs6000_parse_yes_no_option ("isel", arg
, &(rs6000_isel
));
2346 rs6000_explicit_options
.spe
= true;
2351 rs6000_explicit_options
.spe
= true;
2352 rs6000_parse_yes_no_option ("spe", arg
, &(rs6000_spe
));
2356 rs6000_debug_name
= arg
;
2359 #ifdef TARGET_USES_SYSV4_OPT
2361 rs6000_abi_name
= arg
;
2365 rs6000_sdata_name
= arg
;
2368 case OPT_mtls_size_
:
2369 rs6000_tls_size_string
= arg
;
2372 case OPT_mrelocatable
:
2375 target_flags
|= MASK_MINIMAL_TOC
;
2376 target_flags_explicit
|= MASK_MINIMAL_TOC
;
2377 TARGET_NO_FP_IN_TOC
= 1;
2381 case OPT_mrelocatable_lib
:
2384 target_flags
|= MASK_RELOCATABLE
| MASK_MINIMAL_TOC
;
2385 target_flags_explicit
|= MASK_RELOCATABLE
| MASK_MINIMAL_TOC
;
2386 TARGET_NO_FP_IN_TOC
= 1;
2390 target_flags
&= ~MASK_RELOCATABLE
;
2391 target_flags_explicit
|= MASK_RELOCATABLE
;
2397 if (!strcmp (arg
, "altivec"))
2399 rs6000_explicit_options
.altivec_abi
= true;
2400 rs6000_altivec_abi
= 1;
2402 /* Enabling the AltiVec ABI turns off the SPE ABI. */
2405 else if (! strcmp (arg
, "no-altivec"))
2407 rs6000_explicit_options
.altivec_abi
= true;
2408 rs6000_altivec_abi
= 0;
2410 else if (! strcmp (arg
, "spe"))
2412 rs6000_explicit_options
.spe_abi
= true;
2414 rs6000_altivec_abi
= 0;
2415 if (!TARGET_SPE_ABI
)
2416 error ("not configured for ABI: '%s'", arg
);
2418 else if (! strcmp (arg
, "no-spe"))
2420 rs6000_explicit_options
.spe_abi
= true;
2424 /* These are here for testing during development only, do not
2425 document in the manual please. */
2426 else if (! strcmp (arg
, "d64"))
2428 rs6000_darwin64_abi
= 1;
2429 warning (0, "Using darwin64 ABI");
2431 else if (! strcmp (arg
, "d32"))
2433 rs6000_darwin64_abi
= 0;
2434 warning (0, "Using old darwin ABI");
2437 else if (! strcmp (arg
, "ibmlongdouble"))
2439 rs6000_explicit_options
.ieee
= true;
2440 rs6000_ieeequad
= 0;
2441 warning (0, "Using IBM extended precision long double");
2443 else if (! strcmp (arg
, "ieeelongdouble"))
2445 rs6000_explicit_options
.ieee
= true;
2446 rs6000_ieeequad
= 1;
2447 warning (0, "Using IEEE extended precision long double");
2452 error ("unknown ABI specified: '%s'", arg
);
2458 rs6000_select
[1].string
= arg
;
2462 rs6000_select
[2].string
= arg
;
2465 case OPT_mtraceback_
:
2466 rs6000_traceback_name
= arg
;
2469 case OPT_mfloat_gprs_
:
2470 rs6000_explicit_options
.float_gprs
= true;
2471 if (! strcmp (arg
, "yes") || ! strcmp (arg
, "single"))
2472 rs6000_float_gprs
= 1;
2473 else if (! strcmp (arg
, "double"))
2474 rs6000_float_gprs
= 2;
2475 else if (! strcmp (arg
, "no"))
2476 rs6000_float_gprs
= 0;
2479 error ("invalid option for -mfloat-gprs: '%s'", arg
);
2484 case OPT_mlong_double_
:
2485 rs6000_explicit_options
.long_double
= true;
2486 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
2487 if (value
!= 64 && value
!= 128)
2489 error ("Unknown switch -mlong-double-%s", arg
);
2490 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
2494 rs6000_long_double_type_size
= value
;
2497 case OPT_msched_costly_dep_
:
2498 rs6000_sched_costly_dep_str
= arg
;
2502 rs6000_explicit_options
.alignment
= true;
2503 if (! strcmp (arg
, "power"))
2505 /* On 64-bit Darwin, power alignment is ABI-incompatible with
2506 some C library functions, so warn about it. The flag may be
2507 useful for performance studies from time to time though, so
2508 don't disable it entirely. */
2509 if (DEFAULT_ABI
== ABI_DARWIN
&& TARGET_64BIT
)
2510 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2511 " it is incompatible with the installed C and C++ libraries");
2512 rs6000_alignment_flags
= MASK_ALIGN_POWER
;
2514 else if (! strcmp (arg
, "natural"))
2515 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
2518 error ("unknown -malign-XXXXX option specified: '%s'", arg
);
2523 case OPT_msingle_float
:
2524 if (!TARGET_SINGLE_FPU
)
2525 warning (0, "-msingle-float option equivalent to -mhard-float");
2526 /* -msingle-float implies -mno-double-float and TARGET_HARD_FLOAT. */
2527 rs6000_double_float
= 0;
2528 target_flags
&= ~MASK_SOFT_FLOAT
;
2529 target_flags_explicit
|= MASK_SOFT_FLOAT
;
2532 case OPT_mdouble_float
:
2533 /* -mdouble-float implies -msingle-float and TARGET_HARD_FLOAT. */
2534 rs6000_single_float
= 1;
2535 target_flags
&= ~MASK_SOFT_FLOAT
;
2536 target_flags_explicit
|= MASK_SOFT_FLOAT
;
2539 case OPT_msimple_fpu
:
2540 if (!TARGET_SINGLE_FPU
)
2541 warning (0, "-msimple-fpu option ignored");
2544 case OPT_mhard_float
:
2545 /* -mhard_float implies -msingle-float and -mdouble-float. */
2546 rs6000_single_float
= rs6000_double_float
= 1;
2549 case OPT_msoft_float
:
2550 /* -msoft_float implies -mnosingle-float and -mnodouble-float. */
2551 rs6000_single_float
= rs6000_double_float
= 0;
2555 fpu_type
= rs6000_parse_fpu_option(arg
);
2556 if (fpu_type
!= FPU_NONE
)
2557 /* If -mfpu is not none, then turn off SOFT_FLOAT, turn on HARD_FLOAT. */
2559 target_flags
&= ~MASK_SOFT_FLOAT
;
2560 target_flags_explicit
|= MASK_SOFT_FLOAT
;
2561 rs6000_xilinx_fpu
= 1;
2562 if (fpu_type
== FPU_SF_LITE
|| fpu_type
== FPU_SF_FULL
)
2563 rs6000_single_float
= 1;
2564 if (fpu_type
== FPU_DF_LITE
|| fpu_type
== FPU_DF_FULL
)
2565 rs6000_single_float
= rs6000_double_float
= 1;
2566 if (fpu_type
== FPU_SF_LITE
|| fpu_type
== FPU_DF_LITE
)
2567 rs6000_simple_fpu
= 1;
2571 /* -mfpu=none is equivalent to -msoft-float */
2572 target_flags
|= MASK_SOFT_FLOAT
;
2573 target_flags_explicit
|= MASK_SOFT_FLOAT
;
2574 rs6000_single_float
= rs6000_double_float
= 0;
2581 /* Do anything needed at the start of the asm file. */
2584 rs6000_file_start (void)
2588 const char *start
= buffer
;
2589 struct rs6000_cpu_select
*ptr
;
2590 const char *default_cpu
= TARGET_CPU_DEFAULT
;
2591 FILE *file
= asm_out_file
;
2593 default_file_start ();
2595 #ifdef TARGET_BI_ARCH
2596 if ((TARGET_DEFAULT
^ target_flags
) & MASK_64BIT
)
2600 if (flag_verbose_asm
)
2602 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
2603 rs6000_select
[0].string
= default_cpu
;
2605 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
2607 ptr
= &rs6000_select
[i
];
2608 if (ptr
->string
!= (char *)0 && ptr
->string
[0] != '\0')
2610 fprintf (file
, "%s %s%s", start
, ptr
->name
, ptr
->string
);
2615 if (PPC405_ERRATUM77
)
2617 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
2621 #ifdef USING_ELFOS_H
2622 switch (rs6000_sdata
)
2624 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
2625 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
2626 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
2627 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
2630 if (rs6000_sdata
&& g_switch_value
)
2632 fprintf (file
, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED
, start
,
2642 #ifdef HAVE_AS_GNU_ATTRIBUTE
2643 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
2645 fprintf (file
, "\t.gnu_attribute 4, %d\n",
2646 ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
) ? 1
2647 : (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_SINGLE_FLOAT
) ? 3
2649 fprintf (file
, "\t.gnu_attribute 8, %d\n",
2650 (TARGET_ALTIVEC_ABI
? 2
2651 : TARGET_SPE_ABI
? 3
2653 fprintf (file
, "\t.gnu_attribute 12, %d\n",
2654 aix_struct_return
? 2 : 1);
2659 if (DEFAULT_ABI
== ABI_AIX
|| (TARGET_ELF
&& flag_pic
== 2))
2661 switch_to_section (toc_section
);
2662 switch_to_section (text_section
);
2667 /* Return nonzero if this function is known to have a null epilogue. */
2670 direct_return (void)
2672 if (reload_completed
)
2674 rs6000_stack_t
*info
= rs6000_stack_info ();
2676 if (info
->first_gp_reg_save
== 32
2677 && info
->first_fp_reg_save
== 64
2678 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
2679 && ! info
->lr_save_p
2680 && ! info
->cr_save_p
2681 && info
->vrsave_mask
== 0
2689 /* Return the number of instructions it takes to form a constant in an
2690 integer register. */
2693 num_insns_constant_wide (HOST_WIDE_INT value
)
2695 /* signed constant loadable with {cal|addi} */
2696 if ((unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000)
2699 /* constant loadable with {cau|addis} */
2700 else if ((value
& 0xffff) == 0
2701 && (value
>> 31 == -1 || value
>> 31 == 0))
2704 #if HOST_BITS_PER_WIDE_INT == 64
2705 else if (TARGET_POWERPC64
)
2707 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2708 HOST_WIDE_INT high
= value
>> 31;
2710 if (high
== 0 || high
== -1)
2716 return num_insns_constant_wide (high
) + 1;
2718 return (num_insns_constant_wide (high
)
2719 + num_insns_constant_wide (low
) + 1);
2728 num_insns_constant (rtx op
, enum machine_mode mode
)
2730 HOST_WIDE_INT low
, high
;
2732 switch (GET_CODE (op
))
2735 #if HOST_BITS_PER_WIDE_INT == 64
2736 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
2737 && mask64_operand (op
, mode
))
2741 return num_insns_constant_wide (INTVAL (op
));
2744 if (mode
== SFmode
|| mode
== SDmode
)
2749 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2750 if (DECIMAL_FLOAT_MODE_P (mode
))
2751 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
2753 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2754 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
2757 if (mode
== VOIDmode
|| mode
== DImode
)
2759 high
= CONST_DOUBLE_HIGH (op
);
2760 low
= CONST_DOUBLE_LOW (op
);
2767 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2768 if (DECIMAL_FLOAT_MODE_P (mode
))
2769 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, l
);
2771 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
2772 high
= l
[WORDS_BIG_ENDIAN
== 0];
2773 low
= l
[WORDS_BIG_ENDIAN
!= 0];
2777 return (num_insns_constant_wide (low
)
2778 + num_insns_constant_wide (high
));
2781 if ((high
== 0 && low
>= 0)
2782 || (high
== -1 && low
< 0))
2783 return num_insns_constant_wide (low
);
2785 else if (mask64_operand (op
, mode
))
2789 return num_insns_constant_wide (high
) + 1;
2792 return (num_insns_constant_wide (high
)
2793 + num_insns_constant_wide (low
) + 1);
2801 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2802 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2803 corresponding element of the vector, but for V4SFmode and V2SFmode,
2804 the corresponding "float" is interpreted as an SImode integer. */
2807 const_vector_elt_as_int (rtx op
, unsigned int elt
)
2809 rtx tmp
= CONST_VECTOR_ELT (op
, elt
);
2810 if (GET_MODE (op
) == V4SFmode
2811 || GET_MODE (op
) == V2SFmode
)
2812 tmp
= gen_lowpart (SImode
, tmp
);
2813 return INTVAL (tmp
);
2816 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2817 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2818 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2819 all items are set to the same value and contain COPIES replicas of the
2820 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2821 operand and the others are set to the value of the operand's msb. */
2824 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
2826 enum machine_mode mode
= GET_MODE (op
);
2827 enum machine_mode inner
= GET_MODE_INNER (mode
);
2830 unsigned nunits
= GET_MODE_NUNITS (mode
);
2831 unsigned bitsize
= GET_MODE_BITSIZE (inner
);
2832 unsigned mask
= GET_MODE_MASK (inner
);
2834 HOST_WIDE_INT val
= const_vector_elt_as_int (op
, nunits
- 1);
2835 HOST_WIDE_INT splat_val
= val
;
2836 HOST_WIDE_INT msb_val
= val
> 0 ? 0 : -1;
2838 /* Construct the value to be splatted, if possible. If not, return 0. */
2839 for (i
= 2; i
<= copies
; i
*= 2)
2841 HOST_WIDE_INT small_val
;
2843 small_val
= splat_val
>> bitsize
;
2845 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
2847 splat_val
= small_val
;
2850 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2851 if (EASY_VECTOR_15 (splat_val
))
2854 /* Also check if we can splat, and then add the result to itself. Do so if
2855 the value is positive, of if the splat instruction is using OP's mode;
2856 for splat_val < 0, the splat and the add should use the same mode. */
2857 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
2858 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
2864 /* Check if VAL is present in every STEP-th element, and the
2865 other elements are filled with its most significant bit. */
2866 for (i
= 0; i
< nunits
- 1; ++i
)
2868 HOST_WIDE_INT desired_val
;
2869 if (((i
+ 1) & (step
- 1)) == 0)
2872 desired_val
= msb_val
;
2874 if (desired_val
!= const_vector_elt_as_int (op
, i
))
2882 /* Return true if OP is of the given MODE and can be synthesized
2883 with a vspltisb, vspltish or vspltisw. */
2886 easy_altivec_constant (rtx op
, enum machine_mode mode
)
2888 unsigned step
, copies
;
2890 if (mode
== VOIDmode
)
2891 mode
= GET_MODE (op
);
2892 else if (mode
!= GET_MODE (op
))
2895 /* Start with a vspltisw. */
2896 step
= GET_MODE_NUNITS (mode
) / 4;
2899 if (vspltis_constant (op
, step
, copies
))
2902 /* Then try with a vspltish. */
2908 if (vspltis_constant (op
, step
, copies
))
2911 /* And finally a vspltisb. */
2917 if (vspltis_constant (op
, step
, copies
))
2923 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2924 result is OP. Abort if it is not possible. */
2927 gen_easy_altivec_constant (rtx op
)
2929 enum machine_mode mode
= GET_MODE (op
);
2930 int nunits
= GET_MODE_NUNITS (mode
);
2931 rtx last
= CONST_VECTOR_ELT (op
, nunits
- 1);
2932 unsigned step
= nunits
/ 4;
2933 unsigned copies
= 1;
2935 /* Start with a vspltisw. */
2936 if (vspltis_constant (op
, step
, copies
))
2937 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, last
));
2939 /* Then try with a vspltish. */
2945 if (vspltis_constant (op
, step
, copies
))
2946 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, last
));
2948 /* And finally a vspltisb. */
2954 if (vspltis_constant (op
, step
, copies
))
2955 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, last
));
2961 output_vec_const_move (rtx
*operands
)
2964 enum machine_mode mode
;
2969 mode
= GET_MODE (dest
);
2974 if (zero_constant (vec
, mode
))
2975 return "vxor %0,%0,%0";
2977 splat_vec
= gen_easy_altivec_constant (vec
);
2978 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
2979 operands
[1] = XEXP (splat_vec
, 0);
2980 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
2983 switch (GET_MODE (splat_vec
))
2986 return "vspltisw %0,%1";
2989 return "vspltish %0,%1";
2992 return "vspltisb %0,%1";
2999 gcc_assert (TARGET_SPE
);
3001 /* Vector constant 0 is handled as a splitter of V2SI, and in the
3002 pattern of V1DI, V4HI, and V2SF.
3004 FIXME: We should probably return # and add post reload
3005 splitters for these, but this way is so easy ;-). */
3006 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
3007 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
3008 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
3009 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
3011 return "li %0,%1\n\tevmergelo %0,%0,%0";
3013 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
3016 /* Initialize TARGET of vector PAIRED to VALS. */
3019 paired_expand_vector_init (rtx target
, rtx vals
)
3021 enum machine_mode mode
= GET_MODE (target
);
3022 int n_elts
= GET_MODE_NUNITS (mode
);
3024 rtx x
, new_rtx
, tmp
, constant_op
, op1
, op2
;
3027 for (i
= 0; i
< n_elts
; ++i
)
3029 x
= XVECEXP (vals
, 0, i
);
3030 if (!CONSTANT_P (x
))
3035 /* Load from constant pool. */
3036 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
3042 /* The vector is initialized only with non-constants. */
3043 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
3044 XVECEXP (vals
, 0, 1));
3046 emit_move_insn (target
, new_rtx
);
3050 /* One field is non-constant and the other one is a constant. Load the
3051 constant from the constant pool and use ps_merge instruction to
3052 construct the whole vector. */
3053 op1
= XVECEXP (vals
, 0, 0);
3054 op2
= XVECEXP (vals
, 0, 1);
3056 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
3058 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
3059 emit_move_insn (tmp
, constant_op
);
3061 if (CONSTANT_P (op1
))
3062 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
3064 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
3066 emit_move_insn (target
, new_rtx
);
3070 paired_expand_vector_move (rtx operands
[])
3072 rtx op0
= operands
[0], op1
= operands
[1];
3074 emit_move_insn (op0
, op1
);
3077 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
3078 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
3079 operands for the relation operation COND. This is a recursive
3083 paired_emit_vector_compare (enum rtx_code rcode
,
3084 rtx dest
, rtx op0
, rtx op1
,
3085 rtx cc_op0
, rtx cc_op1
)
3087 rtx tmp
= gen_reg_rtx (V2SFmode
);
3088 rtx tmp1
, max
, min
, equal_zero
;
3090 gcc_assert (TARGET_PAIRED_FLOAT
);
3091 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
3097 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
3101 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
3102 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
3106 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
3109 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
3112 tmp1
= gen_reg_rtx (V2SFmode
);
3113 max
= gen_reg_rtx (V2SFmode
);
3114 min
= gen_reg_rtx (V2SFmode
);
3115 equal_zero
= gen_reg_rtx (V2SFmode
);
3117 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
3118 emit_insn (gen_selv2sf4
3119 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
3120 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
3121 emit_insn (gen_selv2sf4
3122 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
3123 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
3124 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
3127 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
3130 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
3133 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
3136 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
3139 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
3148 /* Emit vector conditional expression.
3149 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
3150 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
3153 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
3154 rtx cond
, rtx cc_op0
, rtx cc_op1
)
3156 enum rtx_code rcode
= GET_CODE (cond
);
3158 if (!TARGET_PAIRED_FLOAT
)
3161 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
3166 /* Initialize vector TARGET to VALS. */
3169 rs6000_expand_vector_init (rtx target
, rtx vals
)
3171 enum machine_mode mode
= GET_MODE (target
);
3172 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
3173 int n_elts
= GET_MODE_NUNITS (mode
);
3174 int n_var
= 0, one_var
= -1;
3175 bool all_same
= true, all_const_zero
= true;
3179 for (i
= 0; i
< n_elts
; ++i
)
3181 x
= XVECEXP (vals
, 0, i
);
3182 if (!CONSTANT_P (x
))
3183 ++n_var
, one_var
= i
;
3184 else if (x
!= CONST0_RTX (inner_mode
))
3185 all_const_zero
= false;
3187 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
3193 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
3194 if (mode
!= V4SFmode
&& all_const_zero
)
3196 /* Zero register. */
3197 emit_insn (gen_rtx_SET (VOIDmode
, target
,
3198 gen_rtx_XOR (mode
, target
, target
)));
3201 else if (mode
!= V4SFmode
&& easy_vector_constant (const_vec
, mode
))
3203 /* Splat immediate. */
3204 emit_insn (gen_rtx_SET (VOIDmode
, target
, const_vec
));
3208 ; /* Splat vector element. */
3211 /* Load from constant pool. */
3212 emit_move_insn (target
, const_vec
);
3217 /* Store value to stack temp. Load vector element. Splat. */
3220 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
), 0);
3221 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
3222 XVECEXP (vals
, 0, 0));
3223 x
= gen_rtx_UNSPEC (VOIDmode
,
3224 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
3225 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
3227 gen_rtx_SET (VOIDmode
,
3230 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
3231 gen_rtx_PARALLEL (VOIDmode
,
3232 gen_rtvec (1, const0_rtx
)));
3233 emit_insn (gen_rtx_SET (VOIDmode
, target
,
3234 gen_rtx_VEC_DUPLICATE (mode
, x
)));
3238 /* One field is non-constant. Load constant then overwrite
3242 rtx copy
= copy_rtx (vals
);
3244 /* Load constant part of vector, substitute neighboring value for
3246 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
3247 rs6000_expand_vector_init (target
, copy
);
3249 /* Insert variable. */
3250 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
3254 /* Construct the vector in memory one field at a time
3255 and load the whole vector. */
3256 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
3257 for (i
= 0; i
< n_elts
; i
++)
3258 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
3259 i
* GET_MODE_SIZE (inner_mode
)),
3260 XVECEXP (vals
, 0, i
));
3261 emit_move_insn (target
, mem
);
3264 /* Set field ELT of TARGET to VAL. */
3267 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
3269 enum machine_mode mode
= GET_MODE (target
);
3270 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
3271 rtx reg
= gen_reg_rtx (mode
);
3273 int width
= GET_MODE_SIZE (inner_mode
);
3276 /* Load single variable value. */
3277 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
), 0);
3278 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
3279 x
= gen_rtx_UNSPEC (VOIDmode
,
3280 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
3281 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
3283 gen_rtx_SET (VOIDmode
,
3287 /* Linear sequence. */
3288 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
3289 for (i
= 0; i
< 16; ++i
)
3290 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
3292 /* Set permute mask to insert element into target. */
3293 for (i
= 0; i
< width
; ++i
)
3294 XVECEXP (mask
, 0, elt
*width
+ i
)
3295 = GEN_INT (i
+ 0x10);
3296 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
3297 x
= gen_rtx_UNSPEC (mode
,
3298 gen_rtvec (3, target
, reg
,
3299 force_reg (V16QImode
, x
)),
3301 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
3304 /* Extract field ELT from VEC into TARGET. */
3307 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
3309 enum machine_mode mode
= GET_MODE (vec
);
3310 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
3313 /* Allocate mode-sized buffer. */
3314 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
3316 /* Add offset to field within buffer matching vector element. */
3317 mem
= adjust_address_nv (mem
, mode
, elt
* GET_MODE_SIZE (inner_mode
));
3319 /* Store single field into mode-sized buffer. */
3320 x
= gen_rtx_UNSPEC (VOIDmode
,
3321 gen_rtvec (1, const0_rtx
), UNSPEC_STVE
);
3322 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
3324 gen_rtx_SET (VOIDmode
,
3327 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
3330 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
3331 implement ANDing by the mask IN. */
3333 build_mask64_2_operands (rtx in
, rtx
*out
)
3335 #if HOST_BITS_PER_WIDE_INT >= 64
3336 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
3339 gcc_assert (GET_CODE (in
) == CONST_INT
);
3344 /* Assume c initially something like 0x00fff000000fffff. The idea
3345 is to rotate the word so that the middle ^^^^^^ group of zeros
3346 is at the MS end and can be cleared with an rldicl mask. We then
3347 rotate back and clear off the MS ^^ group of zeros with a
3349 c
= ~c
; /* c == 0xff000ffffff00000 */
3350 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
3351 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
3352 c
= ~c
; /* c == 0x00fff000000fffff */
3353 c
&= -lsb
; /* c == 0x00fff00000000000 */
3354 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
3355 c
= ~c
; /* c == 0xff000fffffffffff */
3356 c
&= -lsb
; /* c == 0xff00000000000000 */
3358 while ((lsb
>>= 1) != 0)
3359 shift
++; /* shift == 44 on exit from loop */
3360 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
3361 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
3362 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
3366 /* Assume c initially something like 0xff000f0000000000. The idea
3367 is to rotate the word so that the ^^^ middle group of zeros
3368 is at the LS end and can be cleared with an rldicr mask. We then
3369 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
3371 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
3372 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
3373 c
= ~c
; /* c == 0x00fff0ffffffffff */
3374 c
&= -lsb
; /* c == 0x00fff00000000000 */
3375 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
3376 c
= ~c
; /* c == 0xff000fffffffffff */
3377 c
&= -lsb
; /* c == 0xff00000000000000 */
3379 while ((lsb
>>= 1) != 0)
3380 shift
++; /* shift == 44 on exit from loop */
3381 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
3382 m1
>>= shift
; /* m1 == 0x0000000000000fff */
3383 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
3386 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
3387 masks will be all 1's. We are guaranteed more than one transition. */
3388 out
[0] = GEN_INT (64 - shift
);
3389 out
[1] = GEN_INT (m1
);
3390 out
[2] = GEN_INT (shift
);
3391 out
[3] = GEN_INT (m2
);
3399 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
3402 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
3404 if (TARGET_E500_DOUBLE
)
3406 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
3407 subreg:TI and reg:TF. Decimal float modes are like integer
3408 modes (only low part of each register used) for this
3410 if (GET_CODE (op
) == SUBREG
3411 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
3412 || mode
== DDmode
|| mode
== TDmode
)
3413 && REG_P (SUBREG_REG (op
))
3414 && (GET_MODE (SUBREG_REG (op
)) == DFmode
3415 || GET_MODE (SUBREG_REG (op
)) == TFmode
))
3418 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
3420 if (GET_CODE (op
) == SUBREG
3421 && (mode
== DFmode
|| mode
== TFmode
)
3422 && REG_P (SUBREG_REG (op
))
3423 && (GET_MODE (SUBREG_REG (op
)) == DImode
3424 || GET_MODE (SUBREG_REG (op
)) == TImode
3425 || GET_MODE (SUBREG_REG (op
)) == DDmode
3426 || GET_MODE (SUBREG_REG (op
)) == TDmode
))
3431 && GET_CODE (op
) == SUBREG
3433 && REG_P (SUBREG_REG (op
))
3434 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
3440 /* AIX increases natural record alignment to doubleword if the first
3441 field is an FP double while the FP fields remain word aligned. */
3444 rs6000_special_round_type_align (tree type
, unsigned int computed
,
3445 unsigned int specified
)
3447 unsigned int align
= MAX (computed
, specified
);
3448 tree field
= TYPE_FIELDS (type
);
3450 /* Skip all non field decls */
3451 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
3452 field
= TREE_CHAIN (field
);
3454 if (field
!= NULL
&& field
!= type
)
3456 type
= TREE_TYPE (field
);
3457 while (TREE_CODE (type
) == ARRAY_TYPE
)
3458 type
= TREE_TYPE (type
);
3460 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
3461 align
= MAX (align
, 64);
3467 /* Darwin increases record alignment to the natural alignment of
3471 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
3472 unsigned int specified
)
3474 unsigned int align
= MAX (computed
, specified
);
3476 if (TYPE_PACKED (type
))
3479 /* Find the first field, looking down into aggregates. */
3481 tree field
= TYPE_FIELDS (type
);
3482 /* Skip all non field decls */
3483 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
3484 field
= TREE_CHAIN (field
);
3487 type
= TREE_TYPE (field
);
3488 while (TREE_CODE (type
) == ARRAY_TYPE
)
3489 type
= TREE_TYPE (type
);
3490 } while (AGGREGATE_TYPE_P (type
));
3492 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
3493 align
= MAX (align
, TYPE_ALIGN (type
));
3498 /* Return 1 for an operand in small memory on V.4/eabi. */
3501 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
3502 enum machine_mode mode ATTRIBUTE_UNUSED
)
3507 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
3510 if (DEFAULT_ABI
!= ABI_V4
)
3513 /* Vector and float memory instructions have a limited offset on the
3514 SPE, so using a vector or float variable directly as an operand is
3517 && (SPE_VECTOR_MODE (mode
) || FLOAT_MODE_P (mode
)))
3520 if (GET_CODE (op
) == SYMBOL_REF
)
3523 else if (GET_CODE (op
) != CONST
3524 || GET_CODE (XEXP (op
, 0)) != PLUS
3525 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
3526 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
3531 rtx sum
= XEXP (op
, 0);
3532 HOST_WIDE_INT summand
;
3534 /* We have to be careful here, because it is the referenced address
3535 that must be 32k from _SDA_BASE_, not just the symbol. */
3536 summand
= INTVAL (XEXP (sum
, 1));
3537 if (summand
< 0 || (unsigned HOST_WIDE_INT
) summand
> g_switch_value
)
3540 sym_ref
= XEXP (sum
, 0);
3543 return SYMBOL_REF_SMALL_P (sym_ref
);
3549 /* Return true if either operand is a general purpose register. */
3552 gpr_or_gpr_p (rtx op0
, rtx op1
)
3554 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
3555 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
3559 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3562 constant_pool_expr_p (rtx op
)
3566 split_const (op
, &base
, &offset
);
3567 return (GET_CODE (base
) == SYMBOL_REF
3568 && CONSTANT_POOL_ADDRESS_P (base
)
3569 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
3573 toc_relative_expr_p (rtx op
)
3577 if (GET_CODE (op
) != CONST
)
3580 split_const (op
, &base
, &offset
);
3581 return (GET_CODE (base
) == UNSPEC
3582 && XINT (base
, 1) == UNSPEC_TOCREL
);
3586 legitimate_constant_pool_address_p (rtx x
)
3589 && GET_CODE (x
) == PLUS
3590 && GET_CODE (XEXP (x
, 0)) == REG
3591 && (TARGET_MINIMAL_TOC
|| REGNO (XEXP (x
, 0)) == TOC_REGISTER
)
3592 && toc_relative_expr_p (XEXP (x
, 1)));
3596 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
3598 return (DEFAULT_ABI
== ABI_V4
3599 && !flag_pic
&& !TARGET_TOC
3600 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
3601 && small_data_operand (x
, mode
));
3604 /* SPE offset addressing is limited to 5-bits worth of double words. */
3605 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3608 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
, int strict
)
3610 unsigned HOST_WIDE_INT offset
, extra
;
3612 if (GET_CODE (x
) != PLUS
)
3614 if (GET_CODE (XEXP (x
, 0)) != REG
)
3616 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
3618 if (legitimate_constant_pool_address_p (x
))
3620 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3623 offset
= INTVAL (XEXP (x
, 1));
3631 /* AltiVec vector modes. Only reg+reg addressing is valid and
3632 constant offset zero should not occur due to canonicalization. */
3639 /* Paired vector modes. Only reg+reg addressing is valid and
3640 constant offset zero should not occur due to canonicalization. */
3641 if (TARGET_PAIRED_FLOAT
)
3643 /* SPE vector modes. */
3644 return SPE_CONST_OFFSET_OK (offset
);
3647 if (TARGET_E500_DOUBLE
)
3648 return SPE_CONST_OFFSET_OK (offset
);
3652 /* On e500v2, we may have:
3654 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3656 Which gets addressed with evldd instructions. */
3657 if (TARGET_E500_DOUBLE
)
3658 return SPE_CONST_OFFSET_OK (offset
);
3660 if (mode
== DFmode
|| mode
== DDmode
|| !TARGET_POWERPC64
)
3662 else if (offset
& 3)
3667 if (TARGET_E500_DOUBLE
)
3668 return (SPE_CONST_OFFSET_OK (offset
)
3669 && SPE_CONST_OFFSET_OK (offset
+ 8));
3673 if (mode
== TFmode
|| mode
== TDmode
|| !TARGET_POWERPC64
)
3675 else if (offset
& 3)
3686 return (offset
< 0x10000) && (offset
+ extra
< 0x10000);
3690 legitimate_indexed_address_p (rtx x
, int strict
)
3694 if (GET_CODE (x
) != PLUS
)
3700 /* Recognize the rtl generated by reload which we know will later be
3701 replaced with proper base and index regs. */
3703 && reload_in_progress
3704 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
3708 return (REG_P (op0
) && REG_P (op1
)
3709 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
3710 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
3711 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
3712 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
3716 avoiding_indexed_address_p (enum machine_mode mode
)
3718 /* Avoid indexed addressing for modes that have non-indexed
3719 load/store instruction forms. */
3720 return TARGET_AVOID_XFORM
&& !ALTIVEC_VECTOR_MODE (mode
);
3724 legitimate_indirect_address_p (rtx x
, int strict
)
3726 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
3730 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
3732 if (!TARGET_MACHO
|| !flag_pic
3733 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
3737 if (GET_CODE (x
) != LO_SUM
)
3739 if (GET_CODE (XEXP (x
, 0)) != REG
)
3741 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
3745 return CONSTANT_P (x
);
3749 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
3751 if (GET_CODE (x
) != LO_SUM
)
3753 if (GET_CODE (XEXP (x
, 0)) != REG
)
3755 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
3757 /* Restrict addressing for DI because of our SUBREG hackery. */
3758 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
3759 || mode
== DDmode
|| mode
== TDmode
3764 if (TARGET_ELF
|| TARGET_MACHO
)
3766 if (DEFAULT_ABI
!= ABI_AIX
&& DEFAULT_ABI
!= ABI_DARWIN
&& flag_pic
)
3770 if (GET_MODE_NUNITS (mode
) != 1)
3772 if (GET_MODE_BITSIZE (mode
) > 64
3773 || (GET_MODE_BITSIZE (mode
) > 32 && !TARGET_POWERPC64
3774 && !(TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
3775 && (mode
== DFmode
|| mode
== DDmode
))))
3778 return CONSTANT_P (x
);
3785 /* Try machine-dependent ways of modifying an illegitimate address
3786 to be legitimate. If we find one, return the new, valid address.
3787 This is used from only one place: `memory_address' in explow.c.
3789 OLDX is the address as it was before break_out_memory_refs was
3790 called. In some cases it is useful to look at this to decide what
3793 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3795 It is always safe for this function to do nothing. It exists to
3796 recognize opportunities to optimize the output.
3798 On RS/6000, first check for the sum of a register with a constant
3799 integer that is out of range. If so, generate code to add the
3800 constant with the low-order 16 bits masked to the register and force
3801 this result into another register (this can be done with `cau').
3802 Then generate an address of REG+(CONST&0xffff), allowing for the
3803 possibility of bit 16 being a one.
3805 Then check for the sum of a register and something not constant, try to
3806 load the other things into a register and return the sum. */
3809 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3810 enum machine_mode mode
)
3812 if (GET_CODE (x
) == SYMBOL_REF
)
3814 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
3816 return rs6000_legitimize_tls_address (x
, model
);
3819 if (GET_CODE (x
) == PLUS
3820 && GET_CODE (XEXP (x
, 0)) == REG
3821 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3822 && (unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000) >= 0x10000
3823 && !((TARGET_POWERPC64
3824 && (mode
== DImode
|| mode
== TImode
)
3825 && (INTVAL (XEXP (x
, 1)) & 3) != 0)
3826 || SPE_VECTOR_MODE (mode
)
3827 || ALTIVEC_VECTOR_MODE (mode
)
3828 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
3829 || mode
== DImode
|| mode
== DDmode
3830 || mode
== TDmode
))))
3832 HOST_WIDE_INT high_int
, low_int
;
3834 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3835 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
3836 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3837 GEN_INT (high_int
)), 0);
3838 return gen_rtx_PLUS (Pmode
, sum
, GEN_INT (low_int
));
3840 else if (GET_CODE (x
) == PLUS
3841 && GET_CODE (XEXP (x
, 0)) == REG
3842 && GET_CODE (XEXP (x
, 1)) != CONST_INT
3843 && GET_MODE_NUNITS (mode
) == 1
3844 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
3846 || ((mode
!= DImode
&& mode
!= DFmode
&& mode
!= DDmode
)
3847 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
)))
3848 && (TARGET_POWERPC64
|| mode
!= DImode
)
3849 && !avoiding_indexed_address_p (mode
)
3854 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3855 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
3857 else if (ALTIVEC_VECTOR_MODE (mode
))
3861 /* Make sure both operands are registers. */
3862 if (GET_CODE (x
) == PLUS
)
3863 return gen_rtx_PLUS (Pmode
, force_reg (Pmode
, XEXP (x
, 0)),
3864 force_reg (Pmode
, XEXP (x
, 1)));
3866 reg
= force_reg (Pmode
, x
);
3869 else if (SPE_VECTOR_MODE (mode
)
3870 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
3871 || mode
== DDmode
|| mode
== TDmode
3872 || mode
== DImode
)))
3876 /* We accept [reg + reg] and [reg + OFFSET]. */
3878 if (GET_CODE (x
) == PLUS
)
3880 rtx op1
= XEXP (x
, 0);
3881 rtx op2
= XEXP (x
, 1);
3884 op1
= force_reg (Pmode
, op1
);
3886 if (GET_CODE (op2
) != REG
3887 && (GET_CODE (op2
) != CONST_INT
3888 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))
3889 || (GET_MODE_SIZE (mode
) > 8
3890 && !SPE_CONST_OFFSET_OK (INTVAL (op2
) + 8))))
3891 op2
= force_reg (Pmode
, op2
);
3893 /* We can't always do [reg + reg] for these, because [reg +
3894 reg + offset] is not a legitimate addressing mode. */
3895 y
= gen_rtx_PLUS (Pmode
, op1
, op2
);
3897 if ((GET_MODE_SIZE (mode
) > 8 || mode
== DDmode
) && REG_P (op2
))
3898 return force_reg (Pmode
, y
);
3903 return force_reg (Pmode
, x
);
3909 && GET_CODE (x
) != CONST_INT
3910 && GET_CODE (x
) != CONST_DOUBLE
3912 && GET_MODE_NUNITS (mode
) == 1
3913 && (GET_MODE_BITSIZE (mode
) <= 32
3914 || ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
3915 && (mode
== DFmode
|| mode
== DDmode
))))
3917 rtx reg
= gen_reg_rtx (Pmode
);
3918 emit_insn (gen_elf_high (reg
, x
));
3919 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
3921 else if (TARGET_MACHO
&& TARGET_32BIT
&& TARGET_NO_TOC
3924 && ! MACHO_DYNAMIC_NO_PIC_P
3926 && GET_CODE (x
) != CONST_INT
3927 && GET_CODE (x
) != CONST_DOUBLE
3929 && GET_MODE_NUNITS (mode
) == 1
3930 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
3931 || (mode
!= DFmode
&& mode
!= DDmode
))
3935 rtx reg
= gen_reg_rtx (Pmode
);
3936 emit_insn (gen_macho_high (reg
, x
));
3937 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
3940 && GET_CODE (x
) == SYMBOL_REF
3941 && constant_pool_expr_p (x
)
3942 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
3944 return create_TOC_reference (x
);
3950 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3951 We need to emit DTP-relative relocations. */
3954 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
3959 fputs ("\t.long\t", file
);
3962 fputs (DOUBLE_INT_ASM_OP
, file
);
3967 output_addr_const (file
, x
);
3968 fputs ("@dtprel+0x8000", file
);
3971 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3973 static GTY(()) rtx rs6000_tls_symbol
;
3975 rs6000_tls_get_addr (void)
3977 if (!rs6000_tls_symbol
)
3978 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3980 return rs6000_tls_symbol
;
3983 /* Construct the SYMBOL_REF for TLS GOT references. */
3985 static GTY(()) rtx rs6000_got_symbol
;
3987 rs6000_got_sym (void)
3989 if (!rs6000_got_symbol
)
3991 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3992 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
3993 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
3996 return rs6000_got_symbol
;
3999 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
4000 this (thread-local) address. */
4003 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
4007 dest
= gen_reg_rtx (Pmode
);
4008 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
4014 tlsreg
= gen_rtx_REG (Pmode
, 13);
4015 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
4019 tlsreg
= gen_rtx_REG (Pmode
, 2);
4020 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
4024 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
4028 tmp
= gen_reg_rtx (Pmode
);
4031 tlsreg
= gen_rtx_REG (Pmode
, 13);
4032 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
4036 tlsreg
= gen_rtx_REG (Pmode
, 2);
4037 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
4041 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
4043 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
4048 rtx r3
, got
, tga
, tmp1
, tmp2
, eqv
;
4050 /* We currently use relocations like @got@tlsgd for tls, which
4051 means the linker will handle allocation of tls entries, placing
4052 them in the .got section. So use a pointer to the .got section,
4053 not one to secondary TOC sections used by 64-bit -mminimal-toc,
4054 or to secondary GOT sections used by 32-bit -fPIC. */
4056 got
= gen_rtx_REG (Pmode
, 2);
4060 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
4063 rtx gsym
= rs6000_got_sym ();
4064 got
= gen_reg_rtx (Pmode
);
4066 rs6000_emit_move (got
, gsym
, Pmode
);
4072 tmp1
= gen_reg_rtx (Pmode
);
4073 tmp2
= gen_reg_rtx (Pmode
);
4074 tmp3
= gen_reg_rtx (Pmode
);
4075 mem
= gen_const_mem (Pmode
, tmp1
);
4077 first
= emit_insn (gen_load_toc_v4_PIC_1b (gsym
));
4078 emit_move_insn (tmp1
,
4079 gen_rtx_REG (Pmode
, LR_REGNO
));
4080 emit_move_insn (tmp2
, mem
);
4081 emit_insn (gen_addsi3 (tmp3
, tmp1
, tmp2
));
4082 last
= emit_move_insn (got
, tmp3
);
4083 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
4088 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
4090 r3
= gen_rtx_REG (Pmode
, 3);
4091 tga
= rs6000_tls_get_addr ();
4093 if (DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
4094 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
4095 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_64BIT
)
4096 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
4097 else if (DEFAULT_ABI
== ABI_V4
)
4098 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
4103 insn
= emit_call_insn (insn
);
4104 RTL_CONST_CALL_P (insn
) = 1;
4105 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r3
);
4106 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
4107 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
4108 insn
= get_insns ();
4110 emit_libcall_block (insn
, dest
, r3
, addr
);
4112 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
4114 r3
= gen_rtx_REG (Pmode
, 3);
4115 tga
= rs6000_tls_get_addr ();
4117 if (DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
4118 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
4119 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_64BIT
)
4120 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
4121 else if (DEFAULT_ABI
== ABI_V4
)
4122 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
4127 insn
= emit_call_insn (insn
);
4128 RTL_CONST_CALL_P (insn
) = 1;
4129 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r3
);
4130 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
4131 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
4132 insn
= get_insns ();
4134 tmp1
= gen_reg_rtx (Pmode
);
4135 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
4137 emit_libcall_block (insn
, tmp1
, r3
, eqv
);
4138 if (rs6000_tls_size
== 16)
4141 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
4143 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
4145 else if (rs6000_tls_size
== 32)
4147 tmp2
= gen_reg_rtx (Pmode
);
4149 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
4151 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
4154 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
4156 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
4160 tmp2
= gen_reg_rtx (Pmode
);
4162 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
4164 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
4166 insn
= gen_rtx_SET (Pmode
, dest
,
4167 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
4173 /* IE, or 64-bit offset LE. */
4174 tmp2
= gen_reg_rtx (Pmode
);
4176 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
4178 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
4181 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
4183 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
4191 /* Return 1 if X contains a thread-local symbol. */
4194 rs6000_tls_referenced_p (rtx x
)
4196 if (! TARGET_HAVE_TLS
)
4199 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
4202 /* Return 1 if *X is a thread-local symbol. This is the same as
4203 rs6000_tls_symbol_ref except for the type of the unused argument. */
4206 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
4208 return RS6000_SYMBOL_REF_TLS_P (*x
);
4211 /* The convention appears to be to define this wherever it is used.
4212 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
4213 is now used here. */
4214 #ifndef REG_MODE_OK_FOR_BASE_P
4215 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
4218 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
4219 replace the input X, or the original X if no replacement is called for.
4220 The output parameter *WIN is 1 if the calling macro should goto WIN,
4223 For RS/6000, we wish to handle large displacements off a base
4224 register by splitting the addend across an addiu/addis and the mem insn.
4225 This cuts number of extra insns needed from 3 to 1.
4227 On Darwin, we use this to generate code for floating point constants.
4228 A movsf_low is generated so we wind up with 2 instructions rather than 3.
4229 The Darwin code is inside #if TARGET_MACHO because only then are the
4230 machopic_* functions defined. */
4232 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
4233 int opnum
, int type
,
4234 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
4236 /* We must recognize output that we have already generated ourselves. */
4237 if (GET_CODE (x
) == PLUS
4238 && GET_CODE (XEXP (x
, 0)) == PLUS
4239 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
4240 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4241 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4243 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4244 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4245 opnum
, (enum reload_type
)type
);
4251 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
4252 && GET_CODE (x
) == LO_SUM
4253 && GET_CODE (XEXP (x
, 0)) == PLUS
4254 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
4255 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
4256 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
4257 && machopic_operand_p (XEXP (x
, 1)))
4259 /* Result of previous invocation of this function on Darwin
4260 floating point constant. */
4261 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4262 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
4263 opnum
, (enum reload_type
)type
);
4269 /* Force ld/std non-word aligned offset into base register by wrapping
4271 if (GET_CODE (x
) == PLUS
4272 && GET_CODE (XEXP (x
, 0)) == REG
4273 && REGNO (XEXP (x
, 0)) < 32
4274 && REG_MODE_OK_FOR_BASE_P (XEXP (x
, 0), mode
)
4275 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4276 && (INTVAL (XEXP (x
, 1)) & 3) != 0
4277 && !ALTIVEC_VECTOR_MODE (mode
)
4278 && GET_MODE_SIZE (mode
) >= UNITS_PER_WORD
4279 && TARGET_POWERPC64
)
4281 x
= gen_rtx_PLUS (GET_MODE (x
), x
, GEN_INT (0));
4282 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4283 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4284 opnum
, (enum reload_type
) type
);
4289 if (GET_CODE (x
) == PLUS
4290 && GET_CODE (XEXP (x
, 0)) == REG
4291 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
4292 && REG_MODE_OK_FOR_BASE_P (XEXP (x
, 0), mode
)
4293 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4294 && !SPE_VECTOR_MODE (mode
)
4295 && !(TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
4296 || mode
== DDmode
|| mode
== TDmode
4298 && !ALTIVEC_VECTOR_MODE (mode
))
4300 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
4301 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
4303 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
4305 /* Check for 32-bit overflow. */
4306 if (high
+ low
!= val
)
4312 /* Reload the high part into a base reg; leave the low part
4313 in the mem directly. */
4315 x
= gen_rtx_PLUS (GET_MODE (x
),
4316 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
4320 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4321 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4322 opnum
, (enum reload_type
)type
);
4327 if (GET_CODE (x
) == SYMBOL_REF
4328 && !ALTIVEC_VECTOR_MODE (mode
)
4329 && !SPE_VECTOR_MODE (mode
)
4331 && DEFAULT_ABI
== ABI_DARWIN
4332 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
4334 && DEFAULT_ABI
== ABI_V4
4337 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
4338 The same goes for DImode without 64-bit gprs and DFmode and DDmode
4342 && (mode
!= DImode
|| TARGET_POWERPC64
)
4343 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
4344 || (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)))
4349 rtx offset
= machopic_gen_offset (x
);
4350 x
= gen_rtx_LO_SUM (GET_MODE (x
),
4351 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
4352 gen_rtx_HIGH (Pmode
, offset
)), offset
);
4356 x
= gen_rtx_LO_SUM (GET_MODE (x
),
4357 gen_rtx_HIGH (Pmode
, x
), x
);
4359 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4360 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
4361 opnum
, (enum reload_type
)type
);
4366 /* Reload an offset address wrapped by an AND that represents the
4367 masking of the lower bits. Strip the outer AND and let reload
4368 convert the offset address into an indirect address. */
4370 && ALTIVEC_VECTOR_MODE (mode
)
4371 && GET_CODE (x
) == AND
4372 && GET_CODE (XEXP (x
, 0)) == PLUS
4373 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
4374 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4375 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4376 && INTVAL (XEXP (x
, 1)) == -16)
4384 && GET_CODE (x
) == SYMBOL_REF
4385 && constant_pool_expr_p (x
)
4386 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), mode
))
4388 x
= create_TOC_reference (x
);
4396 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
4397 that is a valid memory address for an instruction.
4398 The MODE argument is the machine mode for the MEM expression
4399 that wants to use this address.
4401 On the RS/6000, there are four valid address: a SYMBOL_REF that
4402 refers to a constant pool entry of an address (or the sum of it
4403 plus a constant), a short (16-bit signed) constant plus a register,
4404 the sum of two registers, or a register indirect, possibly with an
4405 auto-increment. For DFmode, DDmode and DImode with a constant plus
4406 register, we must ensure that both words are addressable or PowerPC64
4407 with offset word aligned.
4409 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
4410 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
4411 because adjacent memory cells are accessed by adding word-sized offsets
4412 during assembly output. */
4414 rs6000_legitimate_address (enum machine_mode mode
, rtx x
, int reg_ok_strict
)
4416 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
4418 && ALTIVEC_VECTOR_MODE (mode
)
4419 && GET_CODE (x
) == AND
4420 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4421 && INTVAL (XEXP (x
, 1)) == -16)
4424 if (RS6000_SYMBOL_REF_TLS_P (x
))
4426 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
4428 if ((GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
4429 && !ALTIVEC_VECTOR_MODE (mode
)
4430 && !SPE_VECTOR_MODE (mode
)
4433 /* Restrict addressing for DI because of our SUBREG hackery. */
4434 && !(TARGET_E500_DOUBLE
4435 && (mode
== DFmode
|| mode
== DDmode
|| mode
== DImode
))
4437 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
4439 if (legitimate_small_data_p (mode
, x
))
4441 if (legitimate_constant_pool_address_p (x
))
4443 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
4445 && GET_CODE (x
) == PLUS
4446 && GET_CODE (XEXP (x
, 0)) == REG
4447 && (XEXP (x
, 0) == virtual_stack_vars_rtx
4448 || XEXP (x
, 0) == arg_pointer_rtx
)
4449 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4451 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
))
4456 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
4458 || (mode
!= DFmode
&& mode
!= DDmode
)
4459 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
))
4460 && (TARGET_POWERPC64
|| mode
!= DImode
)
4461 && !avoiding_indexed_address_p (mode
)
4462 && legitimate_indexed_address_p (x
, reg_ok_strict
))
4464 if (GET_CODE (x
) == PRE_MODIFY
4468 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
4470 || ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_E500_DOUBLE
))
4471 && (TARGET_POWERPC64
|| mode
!= DImode
)
4472 && !ALTIVEC_VECTOR_MODE (mode
)
4473 && !SPE_VECTOR_MODE (mode
)
4474 /* Restrict addressing for DI because of our SUBREG hackery. */
4475 && !(TARGET_E500_DOUBLE
4476 && (mode
== DFmode
|| mode
== DDmode
|| mode
== DImode
))
4478 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
4479 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1), reg_ok_strict
)
4480 || (!avoiding_indexed_address_p (mode
)
4481 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
4482 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4484 if (legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
4489 /* Go to LABEL if ADDR (a legitimate address expression)
4490 has an effect that depends on the machine mode it is used for.
4492 On the RS/6000 this is true of all integral offsets (since AltiVec
4493 modes don't allow them) or is a pre-increment or decrement.
4495 ??? Except that due to conceptual problems in offsettable_address_p
4496 we can't really report the problems of integral offsets. So leave
4497 this assuming that the adjustable offset must be valid for the
4498 sub-words of a TFmode operand, which is what we had before. */
4501 rs6000_mode_dependent_address (rtx addr
)
4503 switch (GET_CODE (addr
))
4506 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
4508 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
4509 return val
+ 12 + 0x8000 >= 0x10000;
4516 /* Auto-increment cases are now treated generically in recog.c. */
4518 return TARGET_UPDATE
;
4527 /* Implement FIND_BASE_TERM. */
4530 rs6000_find_base_term (rtx op
)
4534 split_const (op
, &base
, &offset
);
4535 if (GET_CODE (base
) == UNSPEC
)
4536 switch (XINT (base
, 1))
4539 case UNSPEC_MACHOPIC_OFFSET
:
4540 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
4541 for aliasing purposes. */
4542 return XVECEXP (base
, 0, 0);
4548 /* More elaborate version of recog's offsettable_memref_p predicate
4549 that works around the ??? note of rs6000_mode_dependent_address.
4550 In particular it accepts
4552 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
4554 in 32-bit mode, that the recog predicate rejects. */
4557 rs6000_offsettable_memref_p (rtx op
)
4562 /* First mimic offsettable_memref_p. */
4563 if (offsettable_address_p (1, GET_MODE (op
), XEXP (op
, 0)))
4566 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
4567 the latter predicate knows nothing about the mode of the memory
4568 reference and, therefore, assumes that it is the largest supported
4569 mode (TFmode). As a consequence, legitimate offsettable memory
4570 references are rejected. rs6000_legitimate_offset_address_p contains
4571 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
4572 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0), 1);
4575 /* Return number of consecutive hard regs needed starting at reg REGNO
4576 to hold something of mode MODE.
4577 This is ordinarily the length in words of a value of mode MODE
4578 but can be less for certain modes in special long registers.
4580 For the SPE, GPRs are 64 bits but only 32 bits are visible in
4581 scalar instructions. The upper 32 bits are only available to the
4584 POWER and PowerPC GPRs hold 32 bits worth;
4585 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
4588 rs6000_hard_regno_nregs (int regno
, enum machine_mode mode
)
4590 if (FP_REGNO_P (regno
))
4591 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
4593 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
4594 return (GET_MODE_SIZE (mode
) + UNITS_PER_SPE_WORD
- 1) / UNITS_PER_SPE_WORD
;
4596 if (ALTIVEC_REGNO_P (regno
))
4598 (GET_MODE_SIZE (mode
) + UNITS_PER_ALTIVEC_WORD
- 1) / UNITS_PER_ALTIVEC_WORD
;
4600 /* The value returned for SCmode in the E500 double case is 2 for
4601 ABI compatibility; storing an SCmode value in a single register
4602 would require function_arg and rs6000_spe_function_arg to handle
4603 SCmode so as to pass the value correctly in a pair of
4605 if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
4606 && !DECIMAL_FLOAT_MODE_P (mode
))
4607 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
4609 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4612 /* Change register usage conditional on target flags. */
4614 rs6000_conditional_register_usage (void)
4618 /* Set MQ register fixed (already call_used) if not POWER
4619 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4624 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
4626 fixed_regs
[13] = call_used_regs
[13]
4627 = call_really_used_regs
[13] = 1;
4629 /* Conditionally disable FPRs. */
4630 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
4631 for (i
= 32; i
< 64; i
++)
4632 fixed_regs
[i
] = call_used_regs
[i
]
4633 = call_really_used_regs
[i
] = 1;
4635 /* The TOC register is not killed across calls in a way that is
4636 visible to the compiler. */
4637 if (DEFAULT_ABI
== ABI_AIX
)
4638 call_really_used_regs
[2] = 0;
4640 if (DEFAULT_ABI
== ABI_V4
4641 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
4643 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4645 if (DEFAULT_ABI
== ABI_V4
4646 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
4648 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4649 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4650 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4652 if (DEFAULT_ABI
== ABI_DARWIN
4653 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
4654 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4655 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4656 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4658 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
4659 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4660 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4664 global_regs
[SPEFSCR_REGNO
] = 1;
4665 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
4666 registers in prologues and epilogues. We no longer use r14
4667 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
4668 pool for link-compatibility with older versions of GCC. Once
4669 "old" code has died out, we can return r14 to the allocation
4672 = call_used_regs
[14]
4673 = call_really_used_regs
[14] = 1;
4676 if (!TARGET_ALTIVEC
)
4678 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
4679 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
4680 call_really_used_regs
[VRSAVE_REGNO
] = 1;
4684 global_regs
[VSCR_REGNO
] = 1;
4686 if (TARGET_ALTIVEC_ABI
)
4688 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
4689 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
4691 /* AIX reserves VR20:31 in non-extended ABI mode. */
4693 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
4694 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
4698 /* Try to output insns to set TARGET equal to the constant C if it can
4699 be done in less than N insns. Do all computations in MODE.
4700 Returns the place where the output has been placed if it can be
4701 done and the insns have been emitted. If it would take more than N
4702 insns, zero is returned and no insns and emitted. */
4705 rs6000_emit_set_const (rtx dest
, enum machine_mode mode
,
4706 rtx source
, int n ATTRIBUTE_UNUSED
)
4708 rtx result
, insn
, set
;
4709 HOST_WIDE_INT c0
, c1
;
4716 dest
= gen_reg_rtx (mode
);
4717 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
4721 result
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
4723 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (result
),
4724 GEN_INT (INTVAL (source
)
4725 & (~ (HOST_WIDE_INT
) 0xffff))));
4726 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
4727 gen_rtx_IOR (SImode
, copy_rtx (result
),
4728 GEN_INT (INTVAL (source
) & 0xffff))));
4733 switch (GET_CODE (source
))
4736 c0
= INTVAL (source
);
4741 #if HOST_BITS_PER_WIDE_INT >= 64
4742 c0
= CONST_DOUBLE_LOW (source
);
4745 c0
= CONST_DOUBLE_LOW (source
);
4746 c1
= CONST_DOUBLE_HIGH (source
);
4754 result
= rs6000_emit_set_long_const (dest
, c0
, c1
);
4761 insn
= get_last_insn ();
4762 set
= single_set (insn
);
4763 if (! CONSTANT_P (SET_SRC (set
)))
4764 set_unique_reg_note (insn
, REG_EQUAL
, source
);
4769 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4770 fall back to a straight forward decomposition. We do this to avoid
4771 exponential run times encountered when looking for longer sequences
4772 with rs6000_emit_set_const. */
4774 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
4776 if (!TARGET_POWERPC64
)
4778 rtx operand1
, operand2
;
4780 operand1
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
== 0,
4782 operand2
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
!= 0,
4784 emit_move_insn (operand1
, GEN_INT (c1
));
4785 emit_move_insn (operand2
, GEN_INT (c2
));
4789 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
4792 ud2
= (c1
& 0xffff0000) >> 16;
4793 #if HOST_BITS_PER_WIDE_INT >= 64
4797 ud4
= (c2
& 0xffff0000) >> 16;
4799 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
4800 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
4803 emit_move_insn (dest
, GEN_INT (((ud1
^ 0x8000) - 0x8000)));
4805 emit_move_insn (dest
, GEN_INT (ud1
));
4808 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
4809 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
4812 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
4815 emit_move_insn (dest
, GEN_INT (ud2
<< 16));
4817 emit_move_insn (copy_rtx (dest
),
4818 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4821 else if ((ud4
== 0xffff && (ud3
& 0x8000))
4822 || (ud4
== 0 && ! (ud3
& 0x8000)))
4825 emit_move_insn (dest
, GEN_INT (((ud3
<< 16) ^ 0x80000000)
4828 emit_move_insn (dest
, GEN_INT (ud3
<< 16));
4831 emit_move_insn (copy_rtx (dest
),
4832 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4834 emit_move_insn (copy_rtx (dest
),
4835 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
4838 emit_move_insn (copy_rtx (dest
),
4839 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4845 emit_move_insn (dest
, GEN_INT (((ud4
<< 16) ^ 0x80000000)
4848 emit_move_insn (dest
, GEN_INT (ud4
<< 16));
4851 emit_move_insn (copy_rtx (dest
),
4852 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4855 emit_move_insn (copy_rtx (dest
),
4856 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
4859 emit_move_insn (copy_rtx (dest
),
4860 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4861 GEN_INT (ud2
<< 16)));
4863 emit_move_insn (copy_rtx (dest
),
4864 gen_rtx_IOR (DImode
, copy_rtx (dest
), GEN_INT (ud1
)));
4870 /* Helper for the following. Get rid of [r+r] memory refs
4871 in cases where it won't work (TImode, TFmode, TDmode). */
4874 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
4876 if (GET_CODE (operands
[0]) == MEM
4877 && GET_CODE (XEXP (operands
[0], 0)) != REG
4878 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0))
4879 && ! reload_in_progress
)
4881 = replace_equiv_address (operands
[0],
4882 copy_addr_to_reg (XEXP (operands
[0], 0)));
4884 if (GET_CODE (operands
[1]) == MEM
4885 && GET_CODE (XEXP (operands
[1], 0)) != REG
4886 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0))
4887 && ! reload_in_progress
)
4889 = replace_equiv_address (operands
[1],
4890 copy_addr_to_reg (XEXP (operands
[1], 0)));
4893 /* Emit a move from SOURCE to DEST in mode MODE. */
4895 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
4899 operands
[1] = source
;
4901 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4902 if (GET_CODE (operands
[1]) == CONST_DOUBLE
4903 && ! FLOAT_MODE_P (mode
)
4904 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
4906 /* FIXME. This should never happen. */
4907 /* Since it seems that it does, do the safe thing and convert
4909 operands
[1] = gen_int_mode (CONST_DOUBLE_LOW (operands
[1]), mode
);
4911 gcc_assert (GET_CODE (operands
[1]) != CONST_DOUBLE
4912 || FLOAT_MODE_P (mode
)
4913 || ((CONST_DOUBLE_HIGH (operands
[1]) != 0
4914 || CONST_DOUBLE_LOW (operands
[1]) < 0)
4915 && (CONST_DOUBLE_HIGH (operands
[1]) != -1
4916 || CONST_DOUBLE_LOW (operands
[1]) >= 0)));
4918 /* Check if GCC is setting up a block move that will end up using FP
4919 registers as temporaries. We must make sure this is acceptable. */
4920 if (GET_CODE (operands
[0]) == MEM
4921 && GET_CODE (operands
[1]) == MEM
4923 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
4924 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
4925 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
4926 ? 32 : MEM_ALIGN (operands
[0])))
4927 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
4929 : MEM_ALIGN (operands
[1]))))
4930 && ! MEM_VOLATILE_P (operands
[0])
4931 && ! MEM_VOLATILE_P (operands
[1]))
4933 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
4934 adjust_address (operands
[1], SImode
, 0));
4935 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
4936 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
4940 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
4941 && !gpc_reg_operand (operands
[1], mode
))
4942 operands
[1] = force_reg (mode
, operands
[1]);
4944 if (mode
== SFmode
&& ! TARGET_POWERPC
4945 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
4946 && GET_CODE (operands
[0]) == MEM
)
4950 if (reload_in_progress
|| reload_completed
)
4951 regnum
= true_regnum (operands
[1]);
4952 else if (GET_CODE (operands
[1]) == REG
)
4953 regnum
= REGNO (operands
[1]);
4957 /* If operands[1] is a register, on POWER it may have
4958 double-precision data in it, so truncate it to single
4960 if (FP_REGNO_P (regnum
) || regnum
>= FIRST_PSEUDO_REGISTER
)
4963 newreg
= (!can_create_pseudo_p () ? copy_rtx (operands
[1])
4964 : gen_reg_rtx (mode
));
4965 emit_insn (gen_aux_truncdfsf2 (newreg
, operands
[1]));
4966 operands
[1] = newreg
;
4970 /* Recognize the case where operand[1] is a reference to thread-local
4971 data and load its address to a register. */
4972 if (rs6000_tls_referenced_p (operands
[1]))
4974 enum tls_model model
;
4975 rtx tmp
= operands
[1];
4978 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
4980 addend
= XEXP (XEXP (tmp
, 0), 1);
4981 tmp
= XEXP (XEXP (tmp
, 0), 0);
4984 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
4985 model
= SYMBOL_REF_TLS_MODEL (tmp
);
4986 gcc_assert (model
!= 0);
4988 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
4991 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
4992 tmp
= force_operand (tmp
, operands
[0]);
4997 /* Handle the case where reload calls us with an invalid address. */
4998 if (reload_in_progress
&& mode
== Pmode
4999 && (! general_operand (operands
[1], mode
)
5000 || ! nonimmediate_operand (operands
[0], mode
)))
5003 /* 128-bit constant floating-point values on Darwin should really be
5004 loaded as two parts. */
5005 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
5006 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
5008 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
5009 know how to get a DFmode SUBREG of a TFmode. */
5010 enum machine_mode imode
= (TARGET_E500_DOUBLE
? DFmode
: DImode
);
5011 rs6000_emit_move (simplify_gen_subreg (imode
, operands
[0], mode
, 0),
5012 simplify_gen_subreg (imode
, operands
[1], mode
, 0),
5014 rs6000_emit_move (simplify_gen_subreg (imode
, operands
[0], mode
,
5015 GET_MODE_SIZE (imode
)),
5016 simplify_gen_subreg (imode
, operands
[1], mode
,
5017 GET_MODE_SIZE (imode
)),
5022 if (reload_in_progress
&& cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
5023 cfun
->machine
->sdmode_stack_slot
=
5024 eliminate_regs (cfun
->machine
->sdmode_stack_slot
, VOIDmode
, NULL_RTX
);
5026 if (reload_in_progress
5028 && MEM_P (operands
[0])
5029 && rtx_equal_p (operands
[0], cfun
->machine
->sdmode_stack_slot
)
5030 && REG_P (operands
[1]))
5032 if (FP_REGNO_P (REGNO (operands
[1])))
5034 rtx mem
= adjust_address_nv (operands
[0], DDmode
, 0);
5035 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
5036 emit_insn (gen_movsd_store (mem
, operands
[1]));
5038 else if (INT_REGNO_P (REGNO (operands
[1])))
5040 rtx mem
= adjust_address_nv (operands
[0], mode
, 4);
5041 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
5042 emit_insn (gen_movsd_hardfloat (mem
, operands
[1]));
5048 if (reload_in_progress
5050 && REG_P (operands
[0])
5051 && MEM_P (operands
[1])
5052 && rtx_equal_p (operands
[1], cfun
->machine
->sdmode_stack_slot
))
5054 if (FP_REGNO_P (REGNO (operands
[0])))
5056 rtx mem
= adjust_address_nv (operands
[1], DDmode
, 0);
5057 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
5058 emit_insn (gen_movsd_load (operands
[0], mem
));
5060 else if (INT_REGNO_P (REGNO (operands
[0])))
5062 rtx mem
= adjust_address_nv (operands
[1], mode
, 4);
5063 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
5064 emit_insn (gen_movsd_hardfloat (operands
[0], mem
));
5071 /* FIXME: In the long term, this switch statement should go away
5072 and be replaced by a sequence of tests based on things like
5078 if (CONSTANT_P (operands
[1])
5079 && GET_CODE (operands
[1]) != CONST_INT
)
5080 operands
[1] = force_const_mem (mode
, operands
[1]);
5085 rs6000_eliminate_indexed_memrefs (operands
);
5092 if (CONSTANT_P (operands
[1])
5093 && ! easy_fp_constant (operands
[1], mode
))
5094 operands
[1] = force_const_mem (mode
, operands
[1]);
5105 if (CONSTANT_P (operands
[1])
5106 && !easy_vector_constant (operands
[1], mode
))
5107 operands
[1] = force_const_mem (mode
, operands
[1]);
5112 /* Use default pattern for address of ELF small data */
5115 && DEFAULT_ABI
== ABI_V4
5116 && (GET_CODE (operands
[1]) == SYMBOL_REF
5117 || GET_CODE (operands
[1]) == CONST
)
5118 && small_data_operand (operands
[1], mode
))
5120 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
5124 if (DEFAULT_ABI
== ABI_V4
5125 && mode
== Pmode
&& mode
== SImode
5126 && flag_pic
== 1 && got_operand (operands
[1], mode
))
5128 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
5132 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
5136 && CONSTANT_P (operands
[1])
5137 && GET_CODE (operands
[1]) != HIGH
5138 && GET_CODE (operands
[1]) != CONST_INT
)
5140 rtx target
= (!can_create_pseudo_p ()
5142 : gen_reg_rtx (mode
));
5144 /* If this is a function address on -mcall-aixdesc,
5145 convert it to the address of the descriptor. */
5146 if (DEFAULT_ABI
== ABI_AIX
5147 && GET_CODE (operands
[1]) == SYMBOL_REF
5148 && XSTR (operands
[1], 0)[0] == '.')
5150 const char *name
= XSTR (operands
[1], 0);
5152 while (*name
== '.')
5154 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
5155 CONSTANT_POOL_ADDRESS_P (new_ref
)
5156 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
5157 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
5158 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
5159 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
5160 operands
[1] = new_ref
;
5163 if (DEFAULT_ABI
== ABI_DARWIN
)
5166 if (MACHO_DYNAMIC_NO_PIC_P
)
5168 /* Take care of any required data indirection. */
5169 operands
[1] = rs6000_machopic_legitimize_pic_address (
5170 operands
[1], mode
, operands
[0]);
5171 if (operands
[0] != operands
[1])
5172 emit_insn (gen_rtx_SET (VOIDmode
,
5173 operands
[0], operands
[1]));
5177 emit_insn (gen_macho_high (target
, operands
[1]));
5178 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
5182 emit_insn (gen_elf_high (target
, operands
[1]));
5183 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
5187 /* If this is a SYMBOL_REF that refers to a constant pool entry,
5188 and we have put it in the TOC, we just need to make a TOC-relative
5191 && GET_CODE (operands
[1]) == SYMBOL_REF
5192 && constant_pool_expr_p (operands
[1])
5193 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands
[1]),
5194 get_pool_mode (operands
[1])))
5196 operands
[1] = create_TOC_reference (operands
[1]);
5198 else if (mode
== Pmode
5199 && CONSTANT_P (operands
[1])
5200 && ((GET_CODE (operands
[1]) != CONST_INT
5201 && ! easy_fp_constant (operands
[1], mode
))
5202 || (GET_CODE (operands
[1]) == CONST_INT
5203 && num_insns_constant (operands
[1], mode
) > 2)
5204 || (GET_CODE (operands
[0]) == REG
5205 && FP_REGNO_P (REGNO (operands
[0]))))
5206 && GET_CODE (operands
[1]) != HIGH
5207 && ! legitimate_constant_pool_address_p (operands
[1])
5208 && ! toc_relative_expr_p (operands
[1]))
5210 /* Emit a USE operation so that the constant isn't deleted if
5211 expensive optimizations are turned on because nobody
5212 references it. This should only be done for operands that
5213 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
5214 This should not be done for operands that contain LABEL_REFs.
5215 For now, we just handle the obvious case. */
5216 if (GET_CODE (operands
[1]) != LABEL_REF
)
5217 emit_use (operands
[1]);
5220 /* Darwin uses a special PIC legitimizer. */
5221 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
5224 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
5226 if (operands
[0] != operands
[1])
5227 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
5232 /* If we are to limit the number of things we put in the TOC and
5233 this is a symbol plus a constant we can add in one insn,
5234 just put the symbol in the TOC and add the constant. Don't do
5235 this if reload is in progress. */
5236 if (GET_CODE (operands
[1]) == CONST
5237 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
5238 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
5239 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
5240 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
5241 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
5242 && ! side_effects_p (operands
[0]))
5245 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
5246 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
5248 sym
= force_reg (mode
, sym
);
5250 emit_insn (gen_addsi3 (operands
[0], sym
, other
));
5252 emit_insn (gen_adddi3 (operands
[0], sym
, other
));
5256 operands
[1] = force_const_mem (mode
, operands
[1]);
5259 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
5260 && constant_pool_expr_p (XEXP (operands
[1], 0))
5261 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
5262 get_pool_constant (XEXP (operands
[1], 0)),
5263 get_pool_mode (XEXP (operands
[1], 0))))
5266 = gen_const_mem (mode
,
5267 create_TOC_reference (XEXP (operands
[1], 0)));
5268 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
5274 rs6000_eliminate_indexed_memrefs (operands
);
5278 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5280 gen_rtx_SET (VOIDmode
,
5281 operands
[0], operands
[1]),
5282 gen_rtx_CLOBBER (VOIDmode
,
5283 gen_rtx_SCRATCH (SImode
)))));
5292 /* Above, we may have called force_const_mem which may have returned
5293 an invalid address. If we can, fix this up; otherwise, reload will
5294 have to deal with it. */
5295 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
5296 operands
[1] = validize_mem (operands
[1]);
5299 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
5302 /* Nonzero if we can use a floating-point register to pass this arg. */
5303 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
5304 (SCALAR_FLOAT_MODE_P (MODE) \
5305 && (CUM)->fregno <= FP_ARG_MAX_REG \
5306 && TARGET_HARD_FLOAT && TARGET_FPRS)
5308 /* Nonzero if we can use an AltiVec register to pass this arg. */
5309 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
5310 (ALTIVEC_VECTOR_MODE (MODE) \
5311 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
5312 && TARGET_ALTIVEC_ABI \
5315 /* Return a nonzero value to say to return the function value in
5316 memory, just as large structures are always returned. TYPE will be
5317 the data type of the value, and FNTYPE will be the type of the
5318 function doing the returning, or @code{NULL} for libcalls.
5320 The AIX ABI for the RS/6000 specifies that all structures are
5321 returned in memory. The Darwin ABI does the same. The SVR4 ABI
5322 specifies that structures <= 8 bytes are returned in r3/r4, but a
5323 draft put them in memory, and GCC used to implement the draft
5324 instead of the final standard. Therefore, aix_struct_return
5325 controls this instead of DEFAULT_ABI; V.4 targets needing backward
5326 compatibility can change DRAFT_V4_STRUCT_RET to override the
5327 default, and -m switches get the final word. See
5328 rs6000_override_options for more details.
5330 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
5331 long double support is enabled. These values are returned in memory.
5333 int_size_in_bytes returns -1 for variable size objects, which go in
5334 memory always. The cast to unsigned makes -1 > 8. */
5337 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5339 /* In the darwin64 abi, try to use registers for larger structs
5341 if (rs6000_darwin64_abi
5342 && TREE_CODE (type
) == RECORD_TYPE
5343 && int_size_in_bytes (type
) > 0)
5345 CUMULATIVE_ARGS valcum
;
5349 valcum
.fregno
= FP_ARG_MIN_REG
;
5350 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
5351 /* Do a trial code generation as if this were going to be passed
5352 as an argument; if any part goes in memory, we return NULL. */
5353 valret
= rs6000_darwin64_record_arg (&valcum
, type
, 1, true);
5356 /* Otherwise fall through to more conventional ABI rules. */
5359 if (AGGREGATE_TYPE_P (type
)
5360 && (aix_struct_return
5361 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
5364 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5365 modes only exist for GCC vector types if -maltivec. */
5366 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
5367 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
5370 /* Return synthetic vectors in memory. */
5371 if (TREE_CODE (type
) == VECTOR_TYPE
5372 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
5374 static bool warned_for_return_big_vectors
= false;
5375 if (!warned_for_return_big_vectors
)
5377 warning (0, "GCC vector returned by reference: "
5378 "non-standard ABI extension with no compatibility guarantee");
5379 warned_for_return_big_vectors
= true;
5384 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& TYPE_MODE (type
) == TFmode
)
5390 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5391 for a call to a function whose data type is FNTYPE.
5392 For a library call, FNTYPE is 0.
5394 For incoming args we set the number of arguments in the prototype large
5395 so we never return a PARALLEL. */
5398 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
5399 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
5400 int libcall
, int n_named_args
)
5402 static CUMULATIVE_ARGS zero_cumulative
;
5404 *cum
= zero_cumulative
;
5406 cum
->fregno
= FP_ARG_MIN_REG
;
5407 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
5408 cum
->prototype
= (fntype
&& TYPE_ARG_TYPES (fntype
));
5409 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
5410 ? CALL_LIBCALL
: CALL_NORMAL
);
5411 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
5412 cum
->stdarg
= fntype
5413 && (TYPE_ARG_TYPES (fntype
) != 0
5414 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
5415 != void_type_node
));
5417 cum
->nargs_prototype
= 0;
5418 if (incoming
|| cum
->prototype
)
5419 cum
->nargs_prototype
= n_named_args
;
5421 /* Check for a longcall attribute. */
5422 if ((!fntype
&& rs6000_default_long_calls
)
5424 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
5425 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
5426 cum
->call_cookie
|= CALL_LONG
;
5428 if (TARGET_DEBUG_ARG
)
5430 fprintf (stderr
, "\ninit_cumulative_args:");
5433 tree ret_type
= TREE_TYPE (fntype
);
5434 fprintf (stderr
, " ret code = %s,",
5435 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
5438 if (cum
->call_cookie
& CALL_LONG
)
5439 fprintf (stderr
, " longcall,");
5441 fprintf (stderr
, " proto = %d, nargs = %d\n",
5442 cum
->prototype
, cum
->nargs_prototype
);
5447 && TARGET_ALTIVEC_ABI
5448 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
5450 error ("cannot return value in vector register because"
5451 " altivec instructions are disabled, use -maltivec"
5456 /* Return true if TYPE must be passed on the stack and not in registers. */
5459 rs6000_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
5461 if (DEFAULT_ABI
== ABI_AIX
|| TARGET_64BIT
)
5462 return must_pass_in_stack_var_size (mode
, type
);
5464 return must_pass_in_stack_var_size_or_pad (mode
, type
);
5467 /* If defined, a C expression which determines whether, and in which
5468 direction, to pad out an argument with extra space. The value
5469 should be of type `enum direction': either `upward' to pad above
5470 the argument, `downward' to pad below, or `none' to inhibit
5473 For the AIX ABI structs are always stored left shifted in their
5477 function_arg_padding (enum machine_mode mode
, const_tree type
)
5479 #ifndef AGGREGATE_PADDING_FIXED
5480 #define AGGREGATE_PADDING_FIXED 0
5482 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
5483 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
5486 if (!AGGREGATE_PADDING_FIXED
)
5488 /* GCC used to pass structures of the same size as integer types as
5489 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
5490 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
5491 passed padded downward, except that -mstrict-align further
5492 muddied the water in that multi-component structures of 2 and 4
5493 bytes in size were passed padded upward.
5495 The following arranges for best compatibility with previous
5496 versions of gcc, but removes the -mstrict-align dependency. */
5497 if (BYTES_BIG_ENDIAN
)
5499 HOST_WIDE_INT size
= 0;
5501 if (mode
== BLKmode
)
5503 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
5504 size
= int_size_in_bytes (type
);
5507 size
= GET_MODE_SIZE (mode
);
5509 if (size
== 1 || size
== 2 || size
== 4)
5515 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
5517 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
5521 /* Fall back to the default. */
5522 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
5525 /* If defined, a C expression that gives the alignment boundary, in bits,
5526 of an argument with the specified mode and type. If it is not defined,
5527 PARM_BOUNDARY is used for all arguments.
5529 V.4 wants long longs and doubles to be double word aligned. Just
5530 testing the mode size is a boneheaded way to do this as it means
5531 that other types such as complex int are also double word aligned.
5532 However, we're stuck with this because changing the ABI might break
5533 existing library interfaces.
5535 Doubleword align SPE vectors.
5536 Quadword align Altivec vectors.
5537 Quadword align large synthetic vector types. */
5540 function_arg_boundary (enum machine_mode mode
, tree type
)
5542 if (DEFAULT_ABI
== ABI_V4
5543 && (GET_MODE_SIZE (mode
) == 8
5544 || (TARGET_HARD_FLOAT
5546 && (mode
== TFmode
|| mode
== TDmode
))))
5548 else if (SPE_VECTOR_MODE (mode
)
5549 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
5550 && int_size_in_bytes (type
) >= 8
5551 && int_size_in_bytes (type
) < 16))
5553 else if (ALTIVEC_VECTOR_MODE (mode
)
5554 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
5555 && int_size_in_bytes (type
) >= 16))
5557 else if (rs6000_darwin64_abi
&& mode
== BLKmode
5558 && type
&& TYPE_ALIGN (type
) > 64)
5561 return PARM_BOUNDARY
;
5564 /* For a function parm of MODE and TYPE, return the starting word in
5565 the parameter area. NWORDS of the parameter area are already used. */
5568 rs6000_parm_start (enum machine_mode mode
, tree type
, unsigned int nwords
)
5571 unsigned int parm_offset
;
5573 align
= function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
5574 parm_offset
= DEFAULT_ABI
== ABI_V4
? 2 : 6;
5575 return nwords
+ (-(parm_offset
+ nwords
) & align
);
5578 /* Compute the size (in words) of a function argument. */
5580 static unsigned long
5581 rs6000_arg_size (enum machine_mode mode
, tree type
)
5585 if (mode
!= BLKmode
)
5586 size
= GET_MODE_SIZE (mode
);
5588 size
= int_size_in_bytes (type
);
5591 return (size
+ 3) >> 2;
5593 return (size
+ 7) >> 3;
5596 /* Use this to flush pending int fields. */
5599 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
5600 HOST_WIDE_INT bitpos
)
5602 unsigned int startbit
, endbit
;
5603 int intregs
, intoffset
;
5604 enum machine_mode mode
;
5606 if (cum
->intoffset
== -1)
5609 intoffset
= cum
->intoffset
;
5610 cum
->intoffset
= -1;
5612 if (intoffset
% BITS_PER_WORD
!= 0)
5614 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
5616 if (mode
== BLKmode
)
5618 /* We couldn't find an appropriate mode, which happens,
5619 e.g., in packed structs when there are 3 bytes to load.
5620 Back intoffset back to the beginning of the word in this
5622 intoffset
= intoffset
& -BITS_PER_WORD
;
5626 startbit
= intoffset
& -BITS_PER_WORD
;
5627 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5628 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
5629 cum
->words
+= intregs
;
5632 /* The darwin64 ABI calls for us to recurse down through structs,
5633 looking for elements passed in registers. Unfortunately, we have
5634 to track int register count here also because of misalignments
5635 in powerpc alignment mode. */
5638 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
5640 HOST_WIDE_INT startbitpos
)
5644 for (f
= TYPE_FIELDS (type
); f
; f
= TREE_CHAIN (f
))
5645 if (TREE_CODE (f
) == FIELD_DECL
)
5647 HOST_WIDE_INT bitpos
= startbitpos
;
5648 tree ftype
= TREE_TYPE (f
);
5649 enum machine_mode mode
;
5650 if (ftype
== error_mark_node
)
5652 mode
= TYPE_MODE (ftype
);
5654 if (DECL_SIZE (f
) != 0
5655 && host_integerp (bit_position (f
), 1))
5656 bitpos
+= int_bit_position (f
);
5658 /* ??? FIXME: else assume zero offset. */
5660 if (TREE_CODE (ftype
) == RECORD_TYPE
)
5661 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
5662 else if (USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
5664 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
);
5665 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5666 cum
->words
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5668 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, 1))
5670 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
);
5674 else if (cum
->intoffset
== -1)
5675 cum
->intoffset
= bitpos
;
5679 /* Update the data in CUM to advance over an argument
5680 of mode MODE and data type TYPE.
5681 (TYPE is null for libcalls where that information may not be available.)
5683 Note that for args passed by reference, function_arg will be called
5684 with MODE and TYPE set to that of the pointer to the arg, not the arg
5688 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5689 tree type
, int named
, int depth
)
5693 /* Only tick off an argument if we're not recursing. */
5695 cum
->nargs_prototype
--;
5697 if (TARGET_ALTIVEC_ABI
5698 && (ALTIVEC_VECTOR_MODE (mode
)
5699 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
5700 && int_size_in_bytes (type
) == 16)))
5704 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
5707 if (!TARGET_ALTIVEC
)
5708 error ("cannot pass argument in vector register because"
5709 " altivec instructions are disabled, use -maltivec"
5712 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
5713 even if it is going to be passed in a vector register.
5714 Darwin does the same for variable-argument functions. */
5715 if ((DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
5716 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
5726 /* Vector parameters must be 16-byte aligned. This places
5727 them at 2 mod 4 in terms of words in 32-bit mode, since
5728 the parameter save area starts at offset 24 from the
5729 stack. In 64-bit mode, they just have to start on an
5730 even word, since the parameter save area is 16-byte
5731 aligned. Space for GPRs is reserved even if the argument
5732 will be passed in memory. */
5734 align
= (2 - cum
->words
) & 3;
5736 align
= cum
->words
& 1;
5737 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
5739 if (TARGET_DEBUG_ARG
)
5741 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
5743 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
5744 cum
->nargs_prototype
, cum
->prototype
,
5745 GET_MODE_NAME (mode
));
5749 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
5751 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
5754 else if (rs6000_darwin64_abi
5756 && TREE_CODE (type
) == RECORD_TYPE
5757 && (size
= int_size_in_bytes (type
)) > 0)
5759 /* Variable sized types have size == -1 and are
5760 treated as if consisting entirely of ints.
5761 Pad to 16 byte boundary if needed. */
5762 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
5763 && (cum
->words
% 2) != 0)
5765 /* For varargs, we can just go up by the size of the struct. */
5767 cum
->words
+= (size
+ 7) / 8;
5770 /* It is tempting to say int register count just goes up by
5771 sizeof(type)/8, but this is wrong in a case such as
5772 { int; double; int; } [powerpc alignment]. We have to
5773 grovel through the fields for these too. */
5775 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
5776 rs6000_darwin64_record_arg_advance_flush (cum
,
5777 size
* BITS_PER_UNIT
);
5780 else if (DEFAULT_ABI
== ABI_V4
)
5782 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
5783 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
5784 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
5785 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
5786 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
5788 /* _Decimal128 must use an even/odd register pair. This assumes
5789 that the register number is odd when fregno is odd. */
5790 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
5793 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
5794 <= FP_ARG_V4_MAX_REG
)
5795 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5798 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
5799 if (mode
== DFmode
|| mode
== TFmode
5800 || mode
== DDmode
|| mode
== TDmode
)
5801 cum
->words
+= cum
->words
& 1;
5802 cum
->words
+= rs6000_arg_size (mode
, type
);
5807 int n_words
= rs6000_arg_size (mode
, type
);
5808 int gregno
= cum
->sysv_gregno
;
5810 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5811 (r7,r8) or (r9,r10). As does any other 2 word item such
5812 as complex int due to a historical mistake. */
5814 gregno
+= (1 - gregno
) & 1;
5816 /* Multi-reg args are not split between registers and stack. */
5817 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
5819 /* Long long and SPE vectors are aligned on the stack.
5820 So are other 2 word items such as complex int due to
5821 a historical mistake. */
5823 cum
->words
+= cum
->words
& 1;
5824 cum
->words
+= n_words
;
5827 /* Note: continuing to accumulate gregno past when we've started
5828 spilling to the stack indicates the fact that we've started
5829 spilling to the stack to expand_builtin_saveregs. */
5830 cum
->sysv_gregno
= gregno
+ n_words
;
5833 if (TARGET_DEBUG_ARG
)
5835 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
5836 cum
->words
, cum
->fregno
);
5837 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
5838 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
5839 fprintf (stderr
, "mode = %4s, named = %d\n",
5840 GET_MODE_NAME (mode
), named
);
5845 int n_words
= rs6000_arg_size (mode
, type
);
5846 int start_words
= cum
->words
;
5847 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
5849 cum
->words
= align_words
+ n_words
;
5851 if (SCALAR_FLOAT_MODE_P (mode
)
5852 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
5854 /* _Decimal128 must be passed in an even/odd float register pair.
5855 This assumes that the register number is odd when fregno is
5857 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
5859 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5862 if (TARGET_DEBUG_ARG
)
5864 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
5865 cum
->words
, cum
->fregno
);
5866 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
5867 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
5868 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
5869 named
, align_words
- start_words
, depth
);
5875 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
5882 r1
= gen_rtx_REG (DImode
, gregno
);
5883 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
5884 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
5888 r1
= gen_rtx_REG (DImode
, gregno
);
5889 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
5890 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
5891 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
5892 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
5895 r1
= gen_rtx_REG (DImode
, gregno
);
5896 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
5897 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
5898 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
5899 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
5900 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
5901 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
5902 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
5903 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
5910 /* Determine where to put a SIMD argument on the SPE. */
5912 rs6000_spe_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5915 int gregno
= cum
->sysv_gregno
;
5917 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5918 are passed and returned in a pair of GPRs for ABI compatibility. */
5919 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
5920 || mode
== DCmode
|| mode
== TCmode
))
5922 int n_words
= rs6000_arg_size (mode
, type
);
5924 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5926 gregno
+= (1 - gregno
) & 1;
5928 /* Multi-reg args are not split between registers and stack. */
5929 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
5932 return spe_build_register_parallel (mode
, gregno
);
5936 int n_words
= rs6000_arg_size (mode
, type
);
5938 /* SPE vectors are put in odd registers. */
5939 if (n_words
== 2 && (gregno
& 1) == 0)
5942 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
5945 enum machine_mode m
= SImode
;
5947 r1
= gen_rtx_REG (m
, gregno
);
5948 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
5949 r2
= gen_rtx_REG (m
, gregno
+ 1);
5950 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
5951 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
5958 if (gregno
<= GP_ARG_MAX_REG
)
5959 return gen_rtx_REG (mode
, gregno
);
5965 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
5966 structure between cum->intoffset and bitpos to integer registers. */
5969 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
5970 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
5972 enum machine_mode mode
;
5974 unsigned int startbit
, endbit
;
5975 int this_regno
, intregs
, intoffset
;
5978 if (cum
->intoffset
== -1)
5981 intoffset
= cum
->intoffset
;
5982 cum
->intoffset
= -1;
5984 /* If this is the trailing part of a word, try to only load that
5985 much into the register. Otherwise load the whole register. Note
5986 that in the latter case we may pick up unwanted bits. It's not a
5987 problem at the moment but may wish to revisit. */
5989 if (intoffset
% BITS_PER_WORD
!= 0)
5991 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
5993 if (mode
== BLKmode
)
5995 /* We couldn't find an appropriate mode, which happens,
5996 e.g., in packed structs when there are 3 bytes to load.
5997 Back intoffset back to the beginning of the word in this
5999 intoffset
= intoffset
& -BITS_PER_WORD
;
6006 startbit
= intoffset
& -BITS_PER_WORD
;
6007 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
6008 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
6009 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
6011 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
6014 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
6018 intoffset
/= BITS_PER_UNIT
;
6021 regno
= GP_ARG_MIN_REG
+ this_regno
;
6022 reg
= gen_rtx_REG (mode
, regno
);
6024 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
6027 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
6031 while (intregs
> 0);
6034 /* Recursive workhorse for the following. */
6037 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
6038 HOST_WIDE_INT startbitpos
, rtx rvec
[],
6043 for (f
= TYPE_FIELDS (type
); f
; f
= TREE_CHAIN (f
))
6044 if (TREE_CODE (f
) == FIELD_DECL
)
6046 HOST_WIDE_INT bitpos
= startbitpos
;
6047 tree ftype
= TREE_TYPE (f
);
6048 enum machine_mode mode
;
6049 if (ftype
== error_mark_node
)
6051 mode
= TYPE_MODE (ftype
);
6053 if (DECL_SIZE (f
) != 0
6054 && host_integerp (bit_position (f
), 1))
6055 bitpos
+= int_bit_position (f
);
6057 /* ??? FIXME: else assume zero offset. */
6059 if (TREE_CODE (ftype
) == RECORD_TYPE
)
6060 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
6061 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
6066 case SCmode
: mode
= SFmode
; break;
6067 case DCmode
: mode
= DFmode
; break;
6068 case TCmode
: mode
= TFmode
; break;
6072 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
6074 = gen_rtx_EXPR_LIST (VOIDmode
,
6075 gen_rtx_REG (mode
, cum
->fregno
++),
6076 GEN_INT (bitpos
/ BITS_PER_UNIT
));
6077 if (mode
== TFmode
|| mode
== TDmode
)
6080 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, ftype
, 1))
6082 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
6084 = gen_rtx_EXPR_LIST (VOIDmode
,
6085 gen_rtx_REG (mode
, cum
->vregno
++),
6086 GEN_INT (bitpos
/ BITS_PER_UNIT
));
6088 else if (cum
->intoffset
== -1)
6089 cum
->intoffset
= bitpos
;
6093 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
6094 the register(s) to be used for each field and subfield of a struct
6095 being passed by value, along with the offset of where the
6096 register's value may be found in the block. FP fields go in FP
6097 register, vector fields go in vector registers, and everything
6098 else goes in int registers, packed as in memory.
6100 This code is also used for function return values. RETVAL indicates
6101 whether this is the case.
6103 Much of this is taken from the SPARC V9 port, which has a similar
6104 calling convention. */
6107 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
6108 int named
, bool retval
)
6110 rtx rvec
[FIRST_PSEUDO_REGISTER
];
6111 int k
= 1, kbase
= 1;
6112 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
6113 /* This is a copy; modifications are not visible to our caller. */
6114 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
6115 CUMULATIVE_ARGS
*cum
= ©_cum
;
6117 /* Pad to 16 byte boundary if needed. */
6118 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
6119 && (cum
->words
% 2) != 0)
6126 /* Put entries into rvec[] for individual FP and vector fields, and
6127 for the chunks of memory that go in int regs. Note we start at
6128 element 1; 0 is reserved for an indication of using memory, and
6129 may or may not be filled in below. */
6130 rs6000_darwin64_record_arg_recurse (cum
, type
, 0, rvec
, &k
);
6131 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
6133 /* If any part of the struct went on the stack put all of it there.
6134 This hack is because the generic code for
6135 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
6136 parts of the struct are not at the beginning. */
6140 return NULL_RTX
; /* doesn't go in registers at all */
6142 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6144 if (k
> 1 || cum
->use_stack
)
6145 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
6150 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
6153 rs6000_mixed_function_arg (enum machine_mode mode
, tree type
, int align_words
)
6157 rtx rvec
[GP_ARG_NUM_REG
+ 1];
6159 if (align_words
>= GP_ARG_NUM_REG
)
6162 n_units
= rs6000_arg_size (mode
, type
);
6164 /* Optimize the simple case where the arg fits in one gpr, except in
6165 the case of BLKmode due to assign_parms assuming that registers are
6166 BITS_PER_WORD wide. */
6168 || (n_units
== 1 && mode
!= BLKmode
))
6169 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
6172 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
6173 /* Not all of the arg fits in gprs. Say that it goes in memory too,
6174 using a magic NULL_RTX component.
6175 This is not strictly correct. Only some of the arg belongs in
6176 memory, not all of it. However, the normal scheme using
6177 function_arg_partial_nregs can result in unusual subregs, eg.
6178 (subreg:SI (reg:DF) 4), which are not handled well. The code to
6179 store the whole arg to memory is often more efficient than code
6180 to store pieces, and we know that space is available in the right
6181 place for the whole arg. */
6182 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6187 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
6188 rtx off
= GEN_INT (i
++ * 4);
6189 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
6191 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
6193 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
6196 /* Determine where to put an argument to a function.
6197 Value is zero to push the argument on the stack,
6198 or a hard register in which to store the argument.
6200 MODE is the argument's machine mode.
6201 TYPE is the data type of the argument (as a tree).
6202 This is null for libcalls where that information may
6204 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6205 the preceding args and about the function being called. It is
6206 not modified in this routine.
6207 NAMED is nonzero if this argument is a named parameter
6208 (otherwise it is an extra parameter matching an ellipsis).
6210 On RS/6000 the first eight words of non-FP are normally in registers
6211 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
6212 Under V.4, the first 8 FP args are in registers.
6214 If this is floating-point and no prototype is specified, we use
6215 both an FP and integer register (or possibly FP reg and stack). Library
6216 functions (when CALL_LIBCALL is set) always have the proper types for args,
6217 so we can pass the FP value just in one register. emit_library_function
6218 doesn't support PARALLEL anyway.
6220 Note that for args passed by reference, function_arg will be called
6221 with MODE and TYPE set to that of the pointer to the arg, not the arg
6225 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
6226 tree type
, int named
)
6228 enum rs6000_abi abi
= DEFAULT_ABI
;
6230 /* Return a marker to indicate whether CR1 needs to set or clear the
6231 bit that V.4 uses to say fp args were passed in registers.
6232 Assume that we don't need the marker for software floating point,
6233 or compiler generated library calls. */
6234 if (mode
== VOIDmode
)
6237 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
6239 || (cum
->nargs_prototype
< 0
6240 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
6242 /* For the SPE, we need to crxor CR6 always. */
6244 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
6245 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
6246 return GEN_INT (cum
->call_cookie
6247 | ((cum
->fregno
== FP_ARG_MIN_REG
)
6248 ? CALL_V4_SET_FP_ARGS
6249 : CALL_V4_CLEAR_FP_ARGS
));
6252 return GEN_INT (cum
->call_cookie
);
6255 if (rs6000_darwin64_abi
&& mode
== BLKmode
6256 && TREE_CODE (type
) == RECORD_TYPE
)
6258 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, false);
6259 if (rslt
!= NULL_RTX
)
6261 /* Else fall through to usual handling. */
6264 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
6265 if (TARGET_64BIT
&& ! cum
->prototype
)
6267 /* Vector parameters get passed in vector register
6268 and also in GPRs or memory, in absence of prototype. */
6271 align_words
= (cum
->words
+ 1) & ~1;
6273 if (align_words
>= GP_ARG_NUM_REG
)
6279 slot
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
6281 return gen_rtx_PARALLEL (mode
,
6283 gen_rtx_EXPR_LIST (VOIDmode
,
6285 gen_rtx_EXPR_LIST (VOIDmode
,
6286 gen_rtx_REG (mode
, cum
->vregno
),
6290 return gen_rtx_REG (mode
, cum
->vregno
);
6291 else if (TARGET_ALTIVEC_ABI
6292 && (ALTIVEC_VECTOR_MODE (mode
)
6293 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
6294 && int_size_in_bytes (type
) == 16)))
6296 if (named
|| abi
== ABI_V4
)
6300 /* Vector parameters to varargs functions under AIX or Darwin
6301 get passed in memory and possibly also in GPRs. */
6302 int align
, align_words
, n_words
;
6303 enum machine_mode part_mode
;
6305 /* Vector parameters must be 16-byte aligned. This places them at
6306 2 mod 4 in terms of words in 32-bit mode, since the parameter
6307 save area starts at offset 24 from the stack. In 64-bit mode,
6308 they just have to start on an even word, since the parameter
6309 save area is 16-byte aligned. */
6311 align
= (2 - cum
->words
) & 3;
6313 align
= cum
->words
& 1;
6314 align_words
= cum
->words
+ align
;
6316 /* Out of registers? Memory, then. */
6317 if (align_words
>= GP_ARG_NUM_REG
)
6320 if (TARGET_32BIT
&& TARGET_POWERPC64
)
6321 return rs6000_mixed_function_arg (mode
, type
, align_words
);
6323 /* The vector value goes in GPRs. Only the part of the
6324 value in GPRs is reported here. */
6326 n_words
= rs6000_arg_size (mode
, type
);
6327 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
6328 /* Fortunately, there are only two possibilities, the value
6329 is either wholly in GPRs or half in GPRs and half not. */
6332 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
6335 else if (TARGET_SPE_ABI
&& TARGET_SPE
6336 && (SPE_VECTOR_MODE (mode
)
6337 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
6340 || mode
== TCmode
))))
6341 return rs6000_spe_function_arg (cum
, mode
, type
);
6343 else if (abi
== ABI_V4
)
6345 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
6346 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
6347 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
6348 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
6349 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
6351 /* _Decimal128 must use an even/odd register pair. This assumes
6352 that the register number is odd when fregno is odd. */
6353 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
6356 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
6357 <= FP_ARG_V4_MAX_REG
)
6358 return gen_rtx_REG (mode
, cum
->fregno
);
6364 int n_words
= rs6000_arg_size (mode
, type
);
6365 int gregno
= cum
->sysv_gregno
;
6367 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
6368 (r7,r8) or (r9,r10). As does any other 2 word item such
6369 as complex int due to a historical mistake. */
6371 gregno
+= (1 - gregno
) & 1;
6373 /* Multi-reg args are not split between registers and stack. */
6374 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
6377 if (TARGET_32BIT
&& TARGET_POWERPC64
)
6378 return rs6000_mixed_function_arg (mode
, type
,
6379 gregno
- GP_ARG_MIN_REG
);
6380 return gen_rtx_REG (mode
, gregno
);
6385 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
6387 /* _Decimal128 must be passed in an even/odd float register pair.
6388 This assumes that the register number is odd when fregno is odd. */
6389 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
6392 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
6394 rtx rvec
[GP_ARG_NUM_REG
+ 1];
6398 enum machine_mode fmode
= mode
;
6399 unsigned long n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
6401 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
6403 /* Currently, we only ever need one reg here because complex
6404 doubles are split. */
6405 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
6406 && (fmode
== TFmode
|| fmode
== TDmode
));
6408 /* Long double or _Decimal128 split over regs and memory. */
6409 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
6412 /* Do we also need to pass this arg in the parameter save
6415 && (cum
->nargs_prototype
<= 0
6416 || (DEFAULT_ABI
== ABI_AIX
6418 && align_words
>= GP_ARG_NUM_REG
)));
6420 if (!needs_psave
&& mode
== fmode
)
6421 return gen_rtx_REG (fmode
, cum
->fregno
);
6426 /* Describe the part that goes in gprs or the stack.
6427 This piece must come first, before the fprs. */
6428 if (align_words
< GP_ARG_NUM_REG
)
6430 unsigned long n_words
= rs6000_arg_size (mode
, type
);
6432 if (align_words
+ n_words
> GP_ARG_NUM_REG
6433 || (TARGET_32BIT
&& TARGET_POWERPC64
))
6435 /* If this is partially on the stack, then we only
6436 include the portion actually in registers here. */
6437 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
6440 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
6441 /* Not all of the arg fits in gprs. Say that it
6442 goes in memory too, using a magic NULL_RTX
6443 component. Also see comment in
6444 rs6000_mixed_function_arg for why the normal
6445 function_arg_partial_nregs scheme doesn't work
6447 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
,
6451 r
= gen_rtx_REG (rmode
,
6452 GP_ARG_MIN_REG
+ align_words
);
6453 off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
6454 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
6456 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
6460 /* The whole arg fits in gprs. */
6461 r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
6462 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
6466 /* It's entirely in memory. */
6467 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6470 /* Describe where this piece goes in the fprs. */
6471 r
= gen_rtx_REG (fmode
, cum
->fregno
);
6472 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
6474 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
6476 else if (align_words
< GP_ARG_NUM_REG
)
6478 if (TARGET_32BIT
&& TARGET_POWERPC64
)
6479 return rs6000_mixed_function_arg (mode
, type
, align_words
);
6481 if (mode
== BLKmode
)
6484 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
6491 /* For an arg passed partly in registers and partly in memory, this is
6492 the number of bytes passed in registers. For args passed entirely in
6493 registers or entirely in memory, zero. When an arg is described by a
6494 PARALLEL, perhaps using more than one register type, this function
6495 returns the number of bytes used by the first element of the PARALLEL. */
6498 rs6000_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
6499 tree type
, bool named
)
6504 if (DEFAULT_ABI
== ABI_V4
)
6507 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
)
6508 && cum
->nargs_prototype
>= 0)
6511 /* In this complicated case we just disable the partial_nregs code. */
6512 if (rs6000_darwin64_abi
&& mode
== BLKmode
6513 && TREE_CODE (type
) == RECORD_TYPE
6514 && int_size_in_bytes (type
) > 0)
6517 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
6519 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
6521 /* If we are passing this arg in the fixed parameter save area
6522 (gprs or memory) as well as fprs, then this function should
6523 return the number of partial bytes passed in the parameter
6524 save area rather than partial bytes passed in fprs. */
6526 && (cum
->nargs_prototype
<= 0
6527 || (DEFAULT_ABI
== ABI_AIX
6529 && align_words
>= GP_ARG_NUM_REG
)))
6531 else if (cum
->fregno
+ ((GET_MODE_SIZE (mode
) + 7) >> 3)
6532 > FP_ARG_MAX_REG
+ 1)
6533 ret
= (FP_ARG_MAX_REG
+ 1 - cum
->fregno
) * 8;
6534 else if (cum
->nargs_prototype
>= 0)
6538 if (align_words
< GP_ARG_NUM_REG
6539 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
6540 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
6542 if (ret
!= 0 && TARGET_DEBUG_ARG
)
6543 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
6548 /* A C expression that indicates when an argument must be passed by
6549 reference. If nonzero for an argument, a copy of that argument is
6550 made in memory and a pointer to the argument is passed instead of
6551 the argument itself. The pointer is passed in whatever way is
6552 appropriate for passing a pointer to that type.
6554 Under V.4, aggregates and long double are passed by reference.
6556 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
6557 reference unless the AltiVec vector extension ABI is in force.
6559 As an extension to all ABIs, variable sized types are passed by
6563 rs6000_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
6564 enum machine_mode mode
, const_tree type
,
6565 bool named ATTRIBUTE_UNUSED
)
6567 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& mode
== TFmode
)
6569 if (TARGET_DEBUG_ARG
)
6570 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
6577 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
6579 if (TARGET_DEBUG_ARG
)
6580 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
6584 if (int_size_in_bytes (type
) < 0)
6586 if (TARGET_DEBUG_ARG
)
6587 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
6591 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
6592 modes only exist for GCC vector types if -maltivec. */
6593 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
6595 if (TARGET_DEBUG_ARG
)
6596 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
6600 /* Pass synthetic vectors in memory. */
6601 if (TREE_CODE (type
) == VECTOR_TYPE
6602 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
6604 static bool warned_for_pass_big_vectors
= false;
6605 if (TARGET_DEBUG_ARG
)
6606 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
6607 if (!warned_for_pass_big_vectors
)
6609 warning (0, "GCC vector passed by reference: "
6610 "non-standard ABI extension with no compatibility guarantee");
6611 warned_for_pass_big_vectors
= true;
6620 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
6623 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
6628 for (i
= 0; i
< nregs
; i
++)
6630 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
6631 if (reload_completed
)
6633 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
6636 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
6637 i
* GET_MODE_SIZE (reg_mode
));
6640 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
6644 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
6648 /* Perform any needed actions needed for a function that is receiving a
6649 variable number of arguments.
6653 MODE and TYPE are the mode and type of the current parameter.
6655 PRETEND_SIZE is a variable that should be set to the amount of stack
6656 that must be pushed by the prolog to pretend that our caller pushed
6659 Normally, this macro will push all remaining incoming registers on the
6660 stack and set PRETEND_SIZE to the length of the registers pushed. */
6663 setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
6664 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
6667 CUMULATIVE_ARGS next_cum
;
6668 int reg_size
= TARGET_32BIT
? 4 : 8;
6669 rtx save_area
= NULL_RTX
, mem
;
6670 int first_reg_offset
;
6673 /* Skip the last named argument. */
6675 function_arg_advance (&next_cum
, mode
, type
, 1, 0);
6677 if (DEFAULT_ABI
== ABI_V4
)
6679 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
6683 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
6684 HOST_WIDE_INT offset
= 0;
6686 /* Try to optimize the size of the varargs save area.
6687 The ABI requires that ap.reg_save_area is doubleword
6688 aligned, but we don't need to allocate space for all
6689 the bytes, only those to which we actually will save
6691 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
6692 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
6693 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
6694 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
6695 && cfun
->va_list_fpr_size
)
6698 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
6699 * UNITS_PER_FP_WORD
;
6700 if (cfun
->va_list_fpr_size
6701 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
6702 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
6704 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
6705 * UNITS_PER_FP_WORD
;
6709 offset
= -((first_reg_offset
* reg_size
) & ~7);
6710 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
6712 gpr_reg_num
= cfun
->va_list_gpr_size
;
6713 if (reg_size
== 4 && (first_reg_offset
& 1))
6716 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
6719 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
6721 - (int) (GP_ARG_NUM_REG
* reg_size
);
6723 if (gpr_size
+ fpr_size
)
6726 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
6727 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
6728 reg_save_area
= XEXP (reg_save_area
, 0);
6729 if (GET_CODE (reg_save_area
) == PLUS
)
6731 gcc_assert (XEXP (reg_save_area
, 0)
6732 == virtual_stack_vars_rtx
);
6733 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
6734 offset
+= INTVAL (XEXP (reg_save_area
, 1));
6737 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
6740 cfun
->machine
->varargs_save_offset
= offset
;
6741 save_area
= plus_constant (virtual_stack_vars_rtx
, offset
);
6746 first_reg_offset
= next_cum
.words
;
6747 save_area
= virtual_incoming_args_rtx
;
6749 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
6750 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
6753 set
= get_varargs_alias_set ();
6754 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
6755 && cfun
->va_list_gpr_size
)
6757 int nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
6759 if (va_list_gpr_counter_field
)
6761 /* V4 va_list_gpr_size counts number of registers needed. */
6762 if (nregs
> cfun
->va_list_gpr_size
)
6763 nregs
= cfun
->va_list_gpr_size
;
6767 /* char * va_list instead counts number of bytes needed. */
6768 if (nregs
> cfun
->va_list_gpr_size
/ reg_size
)
6769 nregs
= cfun
->va_list_gpr_size
/ reg_size
;
6772 mem
= gen_rtx_MEM (BLKmode
,
6773 plus_constant (save_area
,
6774 first_reg_offset
* reg_size
));
6775 MEM_NOTRAP_P (mem
) = 1;
6776 set_mem_alias_set (mem
, set
);
6777 set_mem_align (mem
, BITS_PER_WORD
);
6779 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
6783 /* Save FP registers if needed. */
6784 if (DEFAULT_ABI
== ABI_V4
6785 && TARGET_HARD_FLOAT
&& TARGET_FPRS
6787 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
6788 && cfun
->va_list_fpr_size
)
6790 int fregno
= next_cum
.fregno
, nregs
;
6791 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
6792 rtx lab
= gen_label_rtx ();
6793 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
6794 * UNITS_PER_FP_WORD
);
6797 (gen_rtx_SET (VOIDmode
,
6799 gen_rtx_IF_THEN_ELSE (VOIDmode
,
6800 gen_rtx_NE (VOIDmode
, cr1
,
6802 gen_rtx_LABEL_REF (VOIDmode
, lab
),
6806 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
6807 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
6809 mem
= gen_rtx_MEM ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
6811 plus_constant (save_area
, off
));
6812 MEM_NOTRAP_P (mem
) = 1;
6813 set_mem_alias_set (mem
, set
);
6814 set_mem_align (mem
, GET_MODE_ALIGNMENT (
6815 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
6816 ? DFmode
: SFmode
));
6817 emit_move_insn (mem
, gen_rtx_REG (
6818 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
6819 ? DFmode
: SFmode
, fregno
));
6826 /* Create the va_list data type. */
6829 rs6000_build_builtin_va_list (void)
6831 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
6833 /* For AIX, prefer 'char *' because that's what the system
6834 header files like. */
6835 if (DEFAULT_ABI
!= ABI_V4
)
6836 return build_pointer_type (char_type_node
);
6838 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
6839 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
6841 f_gpr
= build_decl (FIELD_DECL
, get_identifier ("gpr"),
6842 unsigned_char_type_node
);
6843 f_fpr
= build_decl (FIELD_DECL
, get_identifier ("fpr"),
6844 unsigned_char_type_node
);
6845 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
6847 f_res
= build_decl (FIELD_DECL
, get_identifier ("reserved"),
6848 short_unsigned_type_node
);
6849 f_ovf
= build_decl (FIELD_DECL
, get_identifier ("overflow_arg_area"),
6851 f_sav
= build_decl (FIELD_DECL
, get_identifier ("reg_save_area"),
6854 va_list_gpr_counter_field
= f_gpr
;
6855 va_list_fpr_counter_field
= f_fpr
;
6857 DECL_FIELD_CONTEXT (f_gpr
) = record
;
6858 DECL_FIELD_CONTEXT (f_fpr
) = record
;
6859 DECL_FIELD_CONTEXT (f_res
) = record
;
6860 DECL_FIELD_CONTEXT (f_ovf
) = record
;
6861 DECL_FIELD_CONTEXT (f_sav
) = record
;
6863 TREE_CHAIN (record
) = type_decl
;
6864 TYPE_NAME (record
) = type_decl
;
6865 TYPE_FIELDS (record
) = f_gpr
;
6866 TREE_CHAIN (f_gpr
) = f_fpr
;
6867 TREE_CHAIN (f_fpr
) = f_res
;
6868 TREE_CHAIN (f_res
) = f_ovf
;
6869 TREE_CHAIN (f_ovf
) = f_sav
;
6871 layout_type (record
);
6873 /* The correct type is an array type of one element. */
6874 return build_array_type (record
, build_index_type (size_zero_node
));
6877 /* Implement va_start. */
6880 rs6000_va_start (tree valist
, rtx nextarg
)
6882 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
6883 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
6884 tree gpr
, fpr
, ovf
, sav
, t
;
6886 /* Only SVR4 needs something special. */
6887 if (DEFAULT_ABI
!= ABI_V4
)
6889 std_expand_builtin_va_start (valist
, nextarg
);
6893 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
6894 f_fpr
= TREE_CHAIN (f_gpr
);
6895 f_res
= TREE_CHAIN (f_fpr
);
6896 f_ovf
= TREE_CHAIN (f_res
);
6897 f_sav
= TREE_CHAIN (f_ovf
);
6899 valist
= build_va_arg_indirect_ref (valist
);
6900 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
6901 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
6903 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
6905 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
6908 /* Count number of gp and fp argument registers used. */
6909 words
= crtl
->args
.info
.words
;
6910 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
6912 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
6915 if (TARGET_DEBUG_ARG
)
6916 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
6917 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
6918 words
, n_gpr
, n_fpr
);
6920 if (cfun
->va_list_gpr_size
)
6922 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
6923 build_int_cst (NULL_TREE
, n_gpr
));
6924 TREE_SIDE_EFFECTS (t
) = 1;
6925 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6928 if (cfun
->va_list_fpr_size
)
6930 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
6931 build_int_cst (NULL_TREE
, n_fpr
));
6932 TREE_SIDE_EFFECTS (t
) = 1;
6933 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6936 /* Find the overflow area. */
6937 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
6939 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovf
), t
,
6940 size_int (words
* UNITS_PER_WORD
));
6941 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
6942 TREE_SIDE_EFFECTS (t
) = 1;
6943 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6945 /* If there were no va_arg invocations, don't set up the register
6947 if (!cfun
->va_list_gpr_size
6948 && !cfun
->va_list_fpr_size
6949 && n_gpr
< GP_ARG_NUM_REG
6950 && n_fpr
< FP_ARG_V4_MAX_REG
)
6953 /* Find the register save area. */
6954 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
6955 if (cfun
->machine
->varargs_save_offset
)
6956 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (sav
), t
,
6957 size_int (cfun
->machine
->varargs_save_offset
));
6958 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
6959 TREE_SIDE_EFFECTS (t
) = 1;
6960 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6963 /* Implement va_arg. */
6966 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
6969 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
6970 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
6971 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
6972 tree lab_false
, lab_over
, addr
;
6974 tree ptrtype
= build_pointer_type (type
);
6978 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
6980 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
6981 return build_va_arg_indirect_ref (t
);
6984 if (DEFAULT_ABI
!= ABI_V4
)
6986 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
6988 tree elem_type
= TREE_TYPE (type
);
6989 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
6990 int elem_size
= GET_MODE_SIZE (elem_mode
);
6992 if (elem_size
< UNITS_PER_WORD
)
6994 tree real_part
, imag_part
;
6995 gimple_seq post
= NULL
;
6997 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
6999 /* Copy the value into a temporary, lest the formal temporary
7000 be reused out from under us. */
7001 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
7002 gimple_seq_add_seq (pre_p
, post
);
7004 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
7007 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
7011 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
7014 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
7015 f_fpr
= TREE_CHAIN (f_gpr
);
7016 f_res
= TREE_CHAIN (f_fpr
);
7017 f_ovf
= TREE_CHAIN (f_res
);
7018 f_sav
= TREE_CHAIN (f_ovf
);
7020 valist
= build_va_arg_indirect_ref (valist
);
7021 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
7022 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
7024 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
7026 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
7029 size
= int_size_in_bytes (type
);
7030 rsize
= (size
+ 3) / 4;
7033 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
7034 && ((TARGET_SINGLE_FLOAT
&& TYPE_MODE (type
) == SFmode
)
7035 || (TARGET_DOUBLE_FLOAT
7036 && (TYPE_MODE (type
) == DFmode
7037 || TYPE_MODE (type
) == TFmode
7038 || TYPE_MODE (type
) == SDmode
7039 || TYPE_MODE (type
) == DDmode
7040 || TYPE_MODE (type
) == TDmode
))))
7042 /* FP args go in FP registers, if present. */
7044 n_reg
= (size
+ 7) / 8;
7045 sav_ofs
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4) * 4;
7046 sav_scale
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4);
7047 if (TYPE_MODE (type
) != SFmode
&& TYPE_MODE (type
) != SDmode
)
7052 /* Otherwise into GP registers. */
7061 /* Pull the value out of the saved registers.... */
7064 addr
= create_tmp_var (ptr_type_node
, "addr");
7065 DECL_POINTER_ALIAS_SET (addr
) = get_varargs_alias_set ();
7067 /* AltiVec vectors never go in registers when -mabi=altivec. */
7068 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
7072 lab_false
= create_artificial_label ();
7073 lab_over
= create_artificial_label ();
7075 /* Long long and SPE vectors are aligned in the registers.
7076 As are any other 2 gpr item such as complex int due to a
7077 historical mistake. */
7079 if (n_reg
== 2 && reg
== gpr
)
7082 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
7083 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
7084 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
7085 unshare_expr (reg
), u
);
7087 /* _Decimal128 is passed in even/odd fpr pairs; the stored
7088 reg number is 0 for f1, so we want to make it odd. */
7089 else if (reg
== fpr
&& TYPE_MODE (type
) == TDmode
)
7091 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
7092 build_int_cst (TREE_TYPE (reg
), 1));
7093 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
7096 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
7097 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
7098 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
7099 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
7100 gimplify_and_add (t
, pre_p
);
7104 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, sav
, size_int (sav_ofs
));
7106 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
7107 build_int_cst (TREE_TYPE (reg
), n_reg
));
7108 u
= fold_convert (sizetype
, u
);
7109 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
7110 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
, u
);
7112 /* _Decimal32 varargs are located in the second word of the 64-bit
7113 FP register for 32-bit binaries. */
7114 if (!TARGET_POWERPC64
7115 && TARGET_HARD_FLOAT
&& TARGET_FPRS
7116 && TYPE_MODE (type
) == SDmode
)
7117 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (size
));
7119 gimplify_assign (addr
, t
, pre_p
);
7121 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
7123 stmt
= gimple_build_label (lab_false
);
7124 gimple_seq_add_stmt (pre_p
, stmt
);
7126 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
7128 /* Ensure that we don't find any more args in regs.
7129 Alignment has taken care of for special cases. */
7130 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
7134 /* ... otherwise out of the overflow area. */
7136 /* Care for on-stack alignment if needed. */
7140 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (align
- 1));
7141 t
= fold_convert (sizetype
, t
);
7142 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
7144 t
= fold_convert (TREE_TYPE (ovf
), t
);
7146 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
7148 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
7150 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (size
));
7151 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
7155 stmt
= gimple_build_label (lab_over
);
7156 gimple_seq_add_stmt (pre_p
, stmt
);
7159 if (STRICT_ALIGNMENT
7160 && (TYPE_ALIGN (type
)
7161 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
7163 /* The value (of type complex double, for example) may not be
7164 aligned in memory in the saved registers, so copy via a
7165 temporary. (This is the same code as used for SPARC.) */
7166 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
7167 tree dest_addr
= build_fold_addr_expr (tmp
);
7169 tree copy
= build_call_expr (implicit_built_in_decls
[BUILT_IN_MEMCPY
],
7170 3, dest_addr
, addr
, size_int (rsize
* 4));
7172 gimplify_and_add (copy
, pre_p
);
7176 addr
= fold_convert (ptrtype
, addr
);
7177 return build_va_arg_indirect_ref (addr
);
7183 def_builtin (int mask
, const char *name
, tree type
, int code
)
7185 if ((mask
& target_flags
) || TARGET_PAIRED_FLOAT
)
7187 if (rs6000_builtin_decls
[code
])
7190 rs6000_builtin_decls
[code
] =
7191 add_builtin_function (name
, type
, code
, BUILT_IN_MD
,
7196 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
7198 static const struct builtin_description bdesc_3arg
[] =
7200 { MASK_ALTIVEC
, CODE_FOR_altivec_vmaddfp
, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP
},
7201 { MASK_ALTIVEC
, CODE_FOR_altivec_vmhaddshs
, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS
},
7202 { MASK_ALTIVEC
, CODE_FOR_altivec_vmhraddshs
, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS
},
7203 { MASK_ALTIVEC
, CODE_FOR_altivec_vmladduhm
, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM
},
7204 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumubm
, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM
},
7205 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsummbm
, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM
},
7206 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumuhm
, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM
},
7207 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumshm
, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM
},
7208 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumuhs
, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS
},
7209 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumshs
, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS
},
7210 { MASK_ALTIVEC
, CODE_FOR_altivec_vnmsubfp
, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP
},
7211 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v4sf
, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF
},
7212 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v4si
, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI
},
7213 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v8hi
, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI
},
7214 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v16qi
, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI
},
7215 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v4sf
, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF
},
7216 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v4si
, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI
},
7217 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v8hi
, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI
},
7218 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v16qi
, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI
},
7219 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v16qi
, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI
},
7220 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v8hi
, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI
},
7221 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v4si
, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI
},
7222 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v4sf
, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF
},
7224 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD
},
7225 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS
},
7226 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD
},
7227 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS
},
7228 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM
},
7229 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM
},
7230 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM
},
7231 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM
},
7232 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM
},
7233 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS
},
7234 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS
},
7235 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS
},
7236 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB
},
7237 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM
},
7238 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL
},
7240 { 0, CODE_FOR_paired_msub
, "__builtin_paired_msub", PAIRED_BUILTIN_MSUB
},
7241 { 0, CODE_FOR_paired_madd
, "__builtin_paired_madd", PAIRED_BUILTIN_MADD
},
7242 { 0, CODE_FOR_paired_madds0
, "__builtin_paired_madds0", PAIRED_BUILTIN_MADDS0
},
7243 { 0, CODE_FOR_paired_madds1
, "__builtin_paired_madds1", PAIRED_BUILTIN_MADDS1
},
7244 { 0, CODE_FOR_paired_nmsub
, "__builtin_paired_nmsub", PAIRED_BUILTIN_NMSUB
},
7245 { 0, CODE_FOR_paired_nmadd
, "__builtin_paired_nmadd", PAIRED_BUILTIN_NMADD
},
7246 { 0, CODE_FOR_paired_sum0
, "__builtin_paired_sum0", PAIRED_BUILTIN_SUM0
},
7247 { 0, CODE_FOR_paired_sum1
, "__builtin_paired_sum1", PAIRED_BUILTIN_SUM1
},
7248 { 0, CODE_FOR_selv2sf4
, "__builtin_paired_selv2sf4", PAIRED_BUILTIN_SELV2SF4
},
7251 /* DST operations: void foo (void *, const int, const char). */
7253 static const struct builtin_description bdesc_dst
[] =
7255 { MASK_ALTIVEC
, CODE_FOR_altivec_dst
, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST
},
7256 { MASK_ALTIVEC
, CODE_FOR_altivec_dstt
, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT
},
7257 { MASK_ALTIVEC
, CODE_FOR_altivec_dstst
, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST
},
7258 { MASK_ALTIVEC
, CODE_FOR_altivec_dststt
, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT
},
7260 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST
},
7261 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT
},
7262 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST
},
7263 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT
}
7266 /* Simple binary operations: VECc = foo (VECa, VECb). */
7268 static struct builtin_description bdesc_2arg
[] =
7270 { MASK_ALTIVEC
, CODE_FOR_addv16qi3
, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM
},
7271 { MASK_ALTIVEC
, CODE_FOR_addv8hi3
, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM
},
7272 { MASK_ALTIVEC
, CODE_FOR_addv4si3
, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM
},
7273 { MASK_ALTIVEC
, CODE_FOR_addv4sf3
, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP
},
7274 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddcuw
, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW
},
7275 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddubs
, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS
},
7276 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddsbs
, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS
},
7277 { MASK_ALTIVEC
, CODE_FOR_altivec_vadduhs
, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS
},
7278 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddshs
, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS
},
7279 { MASK_ALTIVEC
, CODE_FOR_altivec_vadduws
, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS
},
7280 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddsws
, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS
},
7281 { MASK_ALTIVEC
, CODE_FOR_andv4si3
, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND
},
7282 { MASK_ALTIVEC
, CODE_FOR_andcv4si3
, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC
},
7283 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgub
, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB
},
7284 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsb
, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB
},
7285 { MASK_ALTIVEC
, CODE_FOR_altivec_vavguh
, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH
},
7286 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsh
, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH
},
7287 { MASK_ALTIVEC
, CODE_FOR_altivec_vavguw
, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW
},
7288 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsw
, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW
},
7289 { MASK_ALTIVEC
, CODE_FOR_altivec_vcfux
, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX
},
7290 { MASK_ALTIVEC
, CODE_FOR_altivec_vcfsx
, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX
},
7291 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpbfp
, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP
},
7292 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequb
, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB
},
7293 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequh
, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH
},
7294 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequw
, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW
},
7295 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpeqfp
, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP
},
7296 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgefp
, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP
},
7297 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtub
, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB
},
7298 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsb
, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB
},
7299 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtuh
, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH
},
7300 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsh
, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH
},
7301 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtuw
, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW
},
7302 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsw
, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW
},
7303 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtfp
, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP
},
7304 { MASK_ALTIVEC
, CODE_FOR_altivec_vctsxs
, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS
},
7305 { MASK_ALTIVEC
, CODE_FOR_altivec_vctuxs
, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS
},
7306 { MASK_ALTIVEC
, CODE_FOR_umaxv16qi3
, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB
},
7307 { MASK_ALTIVEC
, CODE_FOR_smaxv16qi3
, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB
},
7308 { MASK_ALTIVEC
, CODE_FOR_umaxv8hi3
, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH
},
7309 { MASK_ALTIVEC
, CODE_FOR_smaxv8hi3
, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH
},
7310 { MASK_ALTIVEC
, CODE_FOR_umaxv4si3
, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW
},
7311 { MASK_ALTIVEC
, CODE_FOR_smaxv4si3
, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW
},
7312 { MASK_ALTIVEC
, CODE_FOR_smaxv4sf3
, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP
},
7313 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghb
, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB
},
7314 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghh
, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH
},
7315 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghw
, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW
},
7316 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglb
, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB
},
7317 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglh
, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH
},
7318 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglw
, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW
},
7319 { MASK_ALTIVEC
, CODE_FOR_uminv16qi3
, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB
},
7320 { MASK_ALTIVEC
, CODE_FOR_sminv16qi3
, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB
},
7321 { MASK_ALTIVEC
, CODE_FOR_uminv8hi3
, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH
},
7322 { MASK_ALTIVEC
, CODE_FOR_sminv8hi3
, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH
},
7323 { MASK_ALTIVEC
, CODE_FOR_uminv4si3
, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW
},
7324 { MASK_ALTIVEC
, CODE_FOR_sminv4si3
, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW
},
7325 { MASK_ALTIVEC
, CODE_FOR_sminv4sf3
, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP
},
7326 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuleub
, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB
},
7327 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulesb
, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB
},
7328 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuleuh
, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH
},
7329 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulesh
, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH
},
7330 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuloub
, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB
},
7331 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulosb
, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB
},
7332 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulouh
, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH
},
7333 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulosh
, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH
},
7334 { MASK_ALTIVEC
, CODE_FOR_altivec_norv4si3
, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR
},
7335 { MASK_ALTIVEC
, CODE_FOR_iorv4si3
, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR
},
7336 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum
, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM
},
7337 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum
, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM
},
7338 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkpx
, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX
},
7339 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkshss
, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS
},
7340 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkswss
, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS
},
7341 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhus
, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS
},
7342 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkshus
, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS
},
7343 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwus
, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS
},
7344 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkswus
, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS
},
7345 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlb
, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB
},
7346 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlh
, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH
},
7347 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlw
, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW
},
7348 { MASK_ALTIVEC
, CODE_FOR_vashlv16qi3
, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB
},
7349 { MASK_ALTIVEC
, CODE_FOR_vashlv8hi3
, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH
},
7350 { MASK_ALTIVEC
, CODE_FOR_vashlv4si3
, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW
},
7351 { MASK_ALTIVEC
, CODE_FOR_altivec_vsl
, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL
},
7352 { MASK_ALTIVEC
, CODE_FOR_altivec_vslo
, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO
},
7353 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltb
, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB
},
7354 { MASK_ALTIVEC
, CODE_FOR_altivec_vsplth
, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH
},
7355 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltw
, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW
},
7356 { MASK_ALTIVEC
, CODE_FOR_vlshrv16qi3
, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB
},
7357 { MASK_ALTIVEC
, CODE_FOR_vlshrv8hi3
, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH
},
7358 { MASK_ALTIVEC
, CODE_FOR_vlshrv4si3
, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW
},
7359 { MASK_ALTIVEC
, CODE_FOR_vashrv16qi3
, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB
},
7360 { MASK_ALTIVEC
, CODE_FOR_vashrv8hi3
, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH
},
7361 { MASK_ALTIVEC
, CODE_FOR_vashrv4si3
, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW
},
7362 { MASK_ALTIVEC
, CODE_FOR_altivec_vsr
, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR
},
7363 { MASK_ALTIVEC
, CODE_FOR_altivec_vsro
, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO
},
7364 { MASK_ALTIVEC
, CODE_FOR_subv16qi3
, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM
},
7365 { MASK_ALTIVEC
, CODE_FOR_subv8hi3
, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM
},
7366 { MASK_ALTIVEC
, CODE_FOR_subv4si3
, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM
},
7367 { MASK_ALTIVEC
, CODE_FOR_subv4sf3
, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP
},
7368 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubcuw
, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW
},
7369 { MASK_ALTIVEC
, CODE_FOR_altivec_vsububs
, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS
},
7370 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubsbs
, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS
},
7371 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubuhs
, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS
},
7372 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubshs
, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS
},
7373 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubuws
, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS
},
7374 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubsws
, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS
},
7375 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4ubs
, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS
},
7376 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4sbs
, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS
},
7377 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4shs
, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS
},
7378 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum2sws
, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS
},
7379 { MASK_ALTIVEC
, CODE_FOR_altivec_vsumsws
, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS
},
7380 { MASK_ALTIVEC
, CODE_FOR_xorv4si3
, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR
},
7382 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD
},
7383 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP
},
7384 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM
},
7385 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM
},
7386 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM
},
7387 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC
},
7388 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS
},
7389 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS
},
7390 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS
},
7391 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS
},
7392 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS
},
7393 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS
},
7394 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS
},
7395 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND
},
7396 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC
},
7397 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG
},
7398 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW
},
7399 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW
},
7400 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH
},
7401 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH
},
7402 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB
},
7403 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB
},
7404 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB
},
7405 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ
},
7406 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP
},
7407 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW
},
7408 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH
},
7409 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB
},
7410 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE
},
7411 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT
},
7412 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP
},
7413 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW
},
7414 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW
},
7415 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH
},
7416 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH
},
7417 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB
},
7418 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB
},
7419 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE
},
7420 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT
},
7421 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX
},
7422 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP
},
7423 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW
},
7424 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW
},
7425 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH
},
7426 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH
},
7427 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB
},
7428 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB
},
7429 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH
},
7430 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW
},
7431 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH
},
7432 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB
},
7433 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL
},
7434 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW
},
7435 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH
},
7436 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB
},
7437 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN
},
7438 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP
},
7439 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW
},
7440 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW
},
7441 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH
},
7442 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH
},
7443 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB
},
7444 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB
},
7445 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE
},
7446 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB
},
7447 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB
},
7448 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH
},
7449 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH
},
7450 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO
},
7451 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH
},
7452 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH
},
7453 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB
},
7454 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB
},
7455 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR
},
7456 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR
},
7457 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK
},
7458 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM
},
7459 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM
},
7460 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX
},
7461 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS
},
7462 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS
},
7463 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS
},
7464 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS
},
7465 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS
},
7466 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU
},
7467 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS
},
7468 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS
},
7469 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL
},
7470 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW
},
7471 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH
},
7472 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB
},
7473 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL
},
7474 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW
},
7475 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH
},
7476 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB
},
7477 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL
},
7478 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO
},
7479 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR
},
7480 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW
},
7481 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH
},
7482 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB
},
7483 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA
},
7484 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW
},
7485 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH
},
7486 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB
},
7487 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL
},
7488 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO
},
7489 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB
},
7490 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP
},
7491 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM
},
7492 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM
},
7493 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM
},
7494 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC
},
7495 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS
},
7496 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS
},
7497 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS
},
7498 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS
},
7499 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS
},
7500 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS
},
7501 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS
},
7502 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S
},
7503 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS
},
7504 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS
},
7505 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS
},
7506 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S
},
7507 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS
},
7508 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR
},
7510 { 0, CODE_FOR_divv2sf3
, "__builtin_paired_divv2sf3", PAIRED_BUILTIN_DIVV2SF3
},
7511 { 0, CODE_FOR_addv2sf3
, "__builtin_paired_addv2sf3", PAIRED_BUILTIN_ADDV2SF3
},
7512 { 0, CODE_FOR_subv2sf3
, "__builtin_paired_subv2sf3", PAIRED_BUILTIN_SUBV2SF3
},
7513 { 0, CODE_FOR_mulv2sf3
, "__builtin_paired_mulv2sf3", PAIRED_BUILTIN_MULV2SF3
},
7514 { 0, CODE_FOR_paired_muls0
, "__builtin_paired_muls0", PAIRED_BUILTIN_MULS0
},
7515 { 0, CODE_FOR_paired_muls1
, "__builtin_paired_muls1", PAIRED_BUILTIN_MULS1
},
7516 { 0, CODE_FOR_paired_merge00
, "__builtin_paired_merge00", PAIRED_BUILTIN_MERGE00
},
7517 { 0, CODE_FOR_paired_merge01
, "__builtin_paired_merge01", PAIRED_BUILTIN_MERGE01
},
7518 { 0, CODE_FOR_paired_merge10
, "__builtin_paired_merge10", PAIRED_BUILTIN_MERGE10
},
7519 { 0, CODE_FOR_paired_merge11
, "__builtin_paired_merge11", PAIRED_BUILTIN_MERGE11
},
7521 /* Place holder, leave as first spe builtin. */
7522 { 0, CODE_FOR_spe_evaddw
, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW
},
7523 { 0, CODE_FOR_spe_evand
, "__builtin_spe_evand", SPE_BUILTIN_EVAND
},
7524 { 0, CODE_FOR_spe_evandc
, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC
},
7525 { 0, CODE_FOR_spe_evdivws
, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS
},
7526 { 0, CODE_FOR_spe_evdivwu
, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU
},
7527 { 0, CODE_FOR_spe_eveqv
, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV
},
7528 { 0, CODE_FOR_spe_evfsadd
, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD
},
7529 { 0, CODE_FOR_spe_evfsdiv
, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV
},
7530 { 0, CODE_FOR_spe_evfsmul
, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL
},
7531 { 0, CODE_FOR_spe_evfssub
, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB
},
7532 { 0, CODE_FOR_spe_evmergehi
, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI
},
7533 { 0, CODE_FOR_spe_evmergehilo
, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO
},
7534 { 0, CODE_FOR_spe_evmergelo
, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO
},
7535 { 0, CODE_FOR_spe_evmergelohi
, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI
},
7536 { 0, CODE_FOR_spe_evmhegsmfaa
, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA
},
7537 { 0, CODE_FOR_spe_evmhegsmfan
, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN
},
7538 { 0, CODE_FOR_spe_evmhegsmiaa
, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA
},
7539 { 0, CODE_FOR_spe_evmhegsmian
, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN
},
7540 { 0, CODE_FOR_spe_evmhegumiaa
, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA
},
7541 { 0, CODE_FOR_spe_evmhegumian
, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN
},
7542 { 0, CODE_FOR_spe_evmhesmf
, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF
},
7543 { 0, CODE_FOR_spe_evmhesmfa
, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA
},
7544 { 0, CODE_FOR_spe_evmhesmfaaw
, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW
},
7545 { 0, CODE_FOR_spe_evmhesmfanw
, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW
},
7546 { 0, CODE_FOR_spe_evmhesmi
, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI
},
7547 { 0, CODE_FOR_spe_evmhesmia
, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA
},
7548 { 0, CODE_FOR_spe_evmhesmiaaw
, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW
},
7549 { 0, CODE_FOR_spe_evmhesmianw
, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW
},
7550 { 0, CODE_FOR_spe_evmhessf
, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF
},
7551 { 0, CODE_FOR_spe_evmhessfa
, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA
},
7552 { 0, CODE_FOR_spe_evmhessfaaw
, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW
},
7553 { 0, CODE_FOR_spe_evmhessfanw
, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW
},
7554 { 0, CODE_FOR_spe_evmhessiaaw
, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW
},
7555 { 0, CODE_FOR_spe_evmhessianw
, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW
},
7556 { 0, CODE_FOR_spe_evmheumi
, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI
},
7557 { 0, CODE_FOR_spe_evmheumia
, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA
},
7558 { 0, CODE_FOR_spe_evmheumiaaw
, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW
},
7559 { 0, CODE_FOR_spe_evmheumianw
, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW
},
7560 { 0, CODE_FOR_spe_evmheusiaaw
, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW
},
7561 { 0, CODE_FOR_spe_evmheusianw
, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW
},
7562 { 0, CODE_FOR_spe_evmhogsmfaa
, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA
},
7563 { 0, CODE_FOR_spe_evmhogsmfan
, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN
},
7564 { 0, CODE_FOR_spe_evmhogsmiaa
, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA
},
7565 { 0, CODE_FOR_spe_evmhogsmian
, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN
},
7566 { 0, CODE_FOR_spe_evmhogumiaa
, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA
},
7567 { 0, CODE_FOR_spe_evmhogumian
, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN
},
7568 { 0, CODE_FOR_spe_evmhosmf
, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF
},
7569 { 0, CODE_FOR_spe_evmhosmfa
, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA
},
7570 { 0, CODE_FOR_spe_evmhosmfaaw
, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW
},
7571 { 0, CODE_FOR_spe_evmhosmfanw
, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW
},
7572 { 0, CODE_FOR_spe_evmhosmi
, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI
},
7573 { 0, CODE_FOR_spe_evmhosmia
, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA
},
7574 { 0, CODE_FOR_spe_evmhosmiaaw
, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW
},
7575 { 0, CODE_FOR_spe_evmhosmianw
, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW
},
7576 { 0, CODE_FOR_spe_evmhossf
, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF
},
7577 { 0, CODE_FOR_spe_evmhossfa
, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA
},
7578 { 0, CODE_FOR_spe_evmhossfaaw
, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW
},
7579 { 0, CODE_FOR_spe_evmhossfanw
, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW
},
7580 { 0, CODE_FOR_spe_evmhossiaaw
, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW
},
7581 { 0, CODE_FOR_spe_evmhossianw
, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW
},
7582 { 0, CODE_FOR_spe_evmhoumi
, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI
},
7583 { 0, CODE_FOR_spe_evmhoumia
, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA
},
7584 { 0, CODE_FOR_spe_evmhoumiaaw
, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW
},
7585 { 0, CODE_FOR_spe_evmhoumianw
, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW
},
7586 { 0, CODE_FOR_spe_evmhousiaaw
, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW
},
7587 { 0, CODE_FOR_spe_evmhousianw
, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW
},
7588 { 0, CODE_FOR_spe_evmwhsmf
, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF
},
7589 { 0, CODE_FOR_spe_evmwhsmfa
, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA
},
7590 { 0, CODE_FOR_spe_evmwhsmi
, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI
},
7591 { 0, CODE_FOR_spe_evmwhsmia
, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA
},
7592 { 0, CODE_FOR_spe_evmwhssf
, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF
},
7593 { 0, CODE_FOR_spe_evmwhssfa
, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA
},
7594 { 0, CODE_FOR_spe_evmwhumi
, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI
},
7595 { 0, CODE_FOR_spe_evmwhumia
, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA
},
7596 { 0, CODE_FOR_spe_evmwlsmiaaw
, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW
},
7597 { 0, CODE_FOR_spe_evmwlsmianw
, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW
},
7598 { 0, CODE_FOR_spe_evmwlssiaaw
, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW
},
7599 { 0, CODE_FOR_spe_evmwlssianw
, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW
},
7600 { 0, CODE_FOR_spe_evmwlumi
, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI
},
7601 { 0, CODE_FOR_spe_evmwlumia
, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA
},
7602 { 0, CODE_FOR_spe_evmwlumiaaw
, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW
},
7603 { 0, CODE_FOR_spe_evmwlumianw
, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW
},
7604 { 0, CODE_FOR_spe_evmwlusiaaw
, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW
},
7605 { 0, CODE_FOR_spe_evmwlusianw
, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW
},
7606 { 0, CODE_FOR_spe_evmwsmf
, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF
},
7607 { 0, CODE_FOR_spe_evmwsmfa
, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA
},
7608 { 0, CODE_FOR_spe_evmwsmfaa
, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA
},
7609 { 0, CODE_FOR_spe_evmwsmfan
, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN
},
7610 { 0, CODE_FOR_spe_evmwsmi
, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI
},
7611 { 0, CODE_FOR_spe_evmwsmia
, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA
},
7612 { 0, CODE_FOR_spe_evmwsmiaa
, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA
},
7613 { 0, CODE_FOR_spe_evmwsmian
, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN
},
7614 { 0, CODE_FOR_spe_evmwssf
, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF
},
7615 { 0, CODE_FOR_spe_evmwssfa
, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA
},
7616 { 0, CODE_FOR_spe_evmwssfaa
, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA
},
7617 { 0, CODE_FOR_spe_evmwssfan
, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN
},
7618 { 0, CODE_FOR_spe_evmwumi
, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI
},
7619 { 0, CODE_FOR_spe_evmwumia
, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA
},
7620 { 0, CODE_FOR_spe_evmwumiaa
, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA
},
7621 { 0, CODE_FOR_spe_evmwumian
, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN
},
7622 { 0, CODE_FOR_spe_evnand
, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND
},
7623 { 0, CODE_FOR_spe_evnor
, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR
},
7624 { 0, CODE_FOR_spe_evor
, "__builtin_spe_evor", SPE_BUILTIN_EVOR
},
7625 { 0, CODE_FOR_spe_evorc
, "__builtin_spe_evorc", SPE_BUILTIN_EVORC
},
7626 { 0, CODE_FOR_spe_evrlw
, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW
},
7627 { 0, CODE_FOR_spe_evslw
, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW
},
7628 { 0, CODE_FOR_spe_evsrws
, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS
},
7629 { 0, CODE_FOR_spe_evsrwu
, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU
},
7630 { 0, CODE_FOR_spe_evsubfw
, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW
},
7632 /* SPE binary operations expecting a 5-bit unsigned literal. */
7633 { 0, CODE_FOR_spe_evaddiw
, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW
},
7635 { 0, CODE_FOR_spe_evrlwi
, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI
},
7636 { 0, CODE_FOR_spe_evslwi
, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI
},
7637 { 0, CODE_FOR_spe_evsrwis
, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS
},
7638 { 0, CODE_FOR_spe_evsrwiu
, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU
},
7639 { 0, CODE_FOR_spe_evsubifw
, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW
},
7640 { 0, CODE_FOR_spe_evmwhssfaa
, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA
},
7641 { 0, CODE_FOR_spe_evmwhssmaa
, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA
},
7642 { 0, CODE_FOR_spe_evmwhsmfaa
, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA
},
7643 { 0, CODE_FOR_spe_evmwhsmiaa
, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA
},
7644 { 0, CODE_FOR_spe_evmwhusiaa
, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA
},
7645 { 0, CODE_FOR_spe_evmwhumiaa
, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA
},
7646 { 0, CODE_FOR_spe_evmwhssfan
, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN
},
7647 { 0, CODE_FOR_spe_evmwhssian
, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN
},
7648 { 0, CODE_FOR_spe_evmwhsmfan
, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN
},
7649 { 0, CODE_FOR_spe_evmwhsmian
, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN
},
7650 { 0, CODE_FOR_spe_evmwhusian
, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN
},
7651 { 0, CODE_FOR_spe_evmwhumian
, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN
},
7652 { 0, CODE_FOR_spe_evmwhgssfaa
, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA
},
7653 { 0, CODE_FOR_spe_evmwhgsmfaa
, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA
},
7654 { 0, CODE_FOR_spe_evmwhgsmiaa
, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA
},
7655 { 0, CODE_FOR_spe_evmwhgumiaa
, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA
},
7656 { 0, CODE_FOR_spe_evmwhgssfan
, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN
},
7657 { 0, CODE_FOR_spe_evmwhgsmfan
, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN
},
7658 { 0, CODE_FOR_spe_evmwhgsmian
, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN
},
7659 { 0, CODE_FOR_spe_evmwhgumian
, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN
},
7660 { 0, CODE_FOR_spe_brinc
, "__builtin_spe_brinc", SPE_BUILTIN_BRINC
},
7662 /* Place-holder. Leave as last binary SPE builtin. */
7663 { 0, CODE_FOR_xorv2si3
, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR
}
7666 /* AltiVec predicates. */
7668 struct builtin_description_predicates
7670 const unsigned int mask
;
7671 const enum insn_code icode
;
7673 const char *const name
;
7674 const enum rs6000_builtins code
;
7677 static const struct builtin_description_predicates bdesc_altivec_preds
[] =
7679 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P
},
7680 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P
},
7681 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P
},
7682 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P
},
7683 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P
},
7684 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P
},
7685 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P
},
7686 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P
},
7687 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P
},
7688 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P
},
7689 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P
},
7690 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P
},
7691 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P
},
7693 { MASK_ALTIVEC
, CODE_FOR_nothing
, NULL
, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P
},
7694 { MASK_ALTIVEC
, CODE_FOR_nothing
, NULL
, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P
},
7695 { MASK_ALTIVEC
, CODE_FOR_nothing
, NULL
, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P
}
7698 /* SPE predicates. */
7699 static struct builtin_description bdesc_spe_predicates
[] =
7701 /* Place-holder. Leave as first. */
7702 { 0, CODE_FOR_spe_evcmpeq
, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ
},
7703 { 0, CODE_FOR_spe_evcmpgts
, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS
},
7704 { 0, CODE_FOR_spe_evcmpgtu
, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU
},
7705 { 0, CODE_FOR_spe_evcmplts
, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS
},
7706 { 0, CODE_FOR_spe_evcmpltu
, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU
},
7707 { 0, CODE_FOR_spe_evfscmpeq
, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ
},
7708 { 0, CODE_FOR_spe_evfscmpgt
, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT
},
7709 { 0, CODE_FOR_spe_evfscmplt
, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT
},
7710 { 0, CODE_FOR_spe_evfststeq
, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ
},
7711 { 0, CODE_FOR_spe_evfststgt
, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT
},
7712 /* Place-holder. Leave as last. */
7713 { 0, CODE_FOR_spe_evfststlt
, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT
},
7716 /* SPE evsel predicates. */
7717 static struct builtin_description bdesc_spe_evsel
[] =
7719 /* Place-holder. Leave as first. */
7720 { 0, CODE_FOR_spe_evcmpgts
, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS
},
7721 { 0, CODE_FOR_spe_evcmpgtu
, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU
},
7722 { 0, CODE_FOR_spe_evcmplts
, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS
},
7723 { 0, CODE_FOR_spe_evcmpltu
, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU
},
7724 { 0, CODE_FOR_spe_evcmpeq
, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ
},
7725 { 0, CODE_FOR_spe_evfscmpgt
, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT
},
7726 { 0, CODE_FOR_spe_evfscmplt
, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT
},
7727 { 0, CODE_FOR_spe_evfscmpeq
, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ
},
7728 { 0, CODE_FOR_spe_evfststgt
, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT
},
7729 { 0, CODE_FOR_spe_evfststlt
, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT
},
7730 /* Place-holder. Leave as last. */
7731 { 0, CODE_FOR_spe_evfststeq
, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ
},
7734 /* PAIRED predicates. */
7735 static const struct builtin_description bdesc_paired_preds
[] =
7737 /* Place-holder. Leave as first. */
7738 { 0, CODE_FOR_paired_cmpu0
, "__builtin_paired_cmpu0", PAIRED_BUILTIN_CMPU0
},
7739 /* Place-holder. Leave as last. */
7740 { 0, CODE_FOR_paired_cmpu1
, "__builtin_paired_cmpu1", PAIRED_BUILTIN_CMPU1
},
7743 /* ABS* operations. */
7745 static const struct builtin_description bdesc_abs
[] =
7747 { MASK_ALTIVEC
, CODE_FOR_absv4si2
, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI
},
7748 { MASK_ALTIVEC
, CODE_FOR_absv8hi2
, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI
},
7749 { MASK_ALTIVEC
, CODE_FOR_absv4sf2
, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF
},
7750 { MASK_ALTIVEC
, CODE_FOR_absv16qi2
, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI
},
7751 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v4si
, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI
},
7752 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v8hi
, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI
},
7753 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v16qi
, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI
}
7756 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
7759 static struct builtin_description bdesc_1arg
[] =
7761 { MASK_ALTIVEC
, CODE_FOR_altivec_vexptefp
, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP
},
7762 { MASK_ALTIVEC
, CODE_FOR_altivec_vlogefp
, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP
},
7763 { MASK_ALTIVEC
, CODE_FOR_altivec_vrefp
, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP
},
7764 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfim
, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM
},
7765 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfin
, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN
},
7766 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfip
, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP
},
7767 { MASK_ALTIVEC
, CODE_FOR_ftruncv4sf2
, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ
},
7768 { MASK_ALTIVEC
, CODE_FOR_altivec_vrsqrtefp
, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP
},
7769 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltisb
, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB
},
7770 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltish
, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH
},
7771 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltisw
, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW
},
7772 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhsb
, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB
},
7773 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhpx
, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX
},
7774 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhsh
, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH
},
7775 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklsb
, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB
},
7776 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklpx
, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX
},
7777 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklsh
, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH
},
7779 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS
},
7780 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS
},
7781 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL
},
7782 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE
},
7783 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR
},
7784 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE
},
7785 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR
},
7786 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE
},
7787 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND
},
7788 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE
},
7789 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC
},
7790 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH
},
7791 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH
},
7792 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX
},
7793 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB
},
7794 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL
},
7795 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX
},
7796 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH
},
7797 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB
},
7799 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
7800 end with SPE_BUILTIN_EVSUBFUSIAAW. */
7801 { 0, CODE_FOR_spe_evabs
, "__builtin_spe_evabs", SPE_BUILTIN_EVABS
},
7802 { 0, CODE_FOR_spe_evaddsmiaaw
, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW
},
7803 { 0, CODE_FOR_spe_evaddssiaaw
, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW
},
7804 { 0, CODE_FOR_spe_evaddumiaaw
, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW
},
7805 { 0, CODE_FOR_spe_evaddusiaaw
, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW
},
7806 { 0, CODE_FOR_spe_evcntlsw
, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW
},
7807 { 0, CODE_FOR_spe_evcntlzw
, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW
},
7808 { 0, CODE_FOR_spe_evextsb
, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB
},
7809 { 0, CODE_FOR_spe_evextsh
, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH
},
7810 { 0, CODE_FOR_spe_evfsabs
, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS
},
7811 { 0, CODE_FOR_spe_evfscfsf
, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF
},
7812 { 0, CODE_FOR_spe_evfscfsi
, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI
},
7813 { 0, CODE_FOR_spe_evfscfuf
, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF
},
7814 { 0, CODE_FOR_spe_evfscfui
, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI
},
7815 { 0, CODE_FOR_spe_evfsctsf
, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF
},
7816 { 0, CODE_FOR_spe_evfsctsi
, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI
},
7817 { 0, CODE_FOR_spe_evfsctsiz
, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ
},
7818 { 0, CODE_FOR_spe_evfsctuf
, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF
},
7819 { 0, CODE_FOR_spe_evfsctui
, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI
},
7820 { 0, CODE_FOR_spe_evfsctuiz
, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ
},
7821 { 0, CODE_FOR_spe_evfsnabs
, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS
},
7822 { 0, CODE_FOR_spe_evfsneg
, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG
},
7823 { 0, CODE_FOR_spe_evmra
, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA
},
7824 { 0, CODE_FOR_negv2si2
, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG
},
7825 { 0, CODE_FOR_spe_evrndw
, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW
},
7826 { 0, CODE_FOR_spe_evsubfsmiaaw
, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW
},
7827 { 0, CODE_FOR_spe_evsubfssiaaw
, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW
},
7828 { 0, CODE_FOR_spe_evsubfumiaaw
, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW
},
7830 /* Place-holder. Leave as last unary SPE builtin. */
7831 { 0, CODE_FOR_spe_evsubfusiaaw
, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW
},
7833 { 0, CODE_FOR_absv2sf2
, "__builtin_paired_absv2sf2", PAIRED_BUILTIN_ABSV2SF2
},
7834 { 0, CODE_FOR_nabsv2sf2
, "__builtin_paired_nabsv2sf2", PAIRED_BUILTIN_NABSV2SF2
},
7835 { 0, CODE_FOR_negv2sf2
, "__builtin_paired_negv2sf2", PAIRED_BUILTIN_NEGV2SF2
},
7836 { 0, CODE_FOR_sqrtv2sf2
, "__builtin_paired_sqrtv2sf2", PAIRED_BUILTIN_SQRTV2SF2
},
7837 { 0, CODE_FOR_resv2sf2
, "__builtin_paired_resv2sf2", PAIRED_BUILTIN_RESV2SF2
}
7841 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
7844 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7845 rtx op0
= expand_normal (arg0
);
7846 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7847 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7849 if (icode
== CODE_FOR_nothing
)
7850 /* Builtin not supported on this processor. */
7853 /* If we got invalid arguments bail out before generating bad rtl. */
7854 if (arg0
== error_mark_node
)
7857 if (icode
== CODE_FOR_altivec_vspltisb
7858 || icode
== CODE_FOR_altivec_vspltish
7859 || icode
== CODE_FOR_altivec_vspltisw
7860 || icode
== CODE_FOR_spe_evsplatfi
7861 || icode
== CODE_FOR_spe_evsplati
)
7863 /* Only allow 5-bit *signed* literals. */
7864 if (GET_CODE (op0
) != CONST_INT
7865 || INTVAL (op0
) > 15
7866 || INTVAL (op0
) < -16)
7868 error ("argument 1 must be a 5-bit signed literal");
7874 || GET_MODE (target
) != tmode
7875 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7876 target
= gen_reg_rtx (tmode
);
7878 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7879 op0
= copy_to_mode_reg (mode0
, op0
);
7881 pat
= GEN_FCN (icode
) (target
, op0
);
7890 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
7892 rtx pat
, scratch1
, scratch2
;
7893 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7894 rtx op0
= expand_normal (arg0
);
7895 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7896 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7898 /* If we have invalid arguments, bail out before generating bad rtl. */
7899 if (arg0
== error_mark_node
)
7903 || GET_MODE (target
) != tmode
7904 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7905 target
= gen_reg_rtx (tmode
);
7907 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7908 op0
= copy_to_mode_reg (mode0
, op0
);
7910 scratch1
= gen_reg_rtx (mode0
);
7911 scratch2
= gen_reg_rtx (mode0
);
7913 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
7922 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
7925 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7926 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7927 rtx op0
= expand_normal (arg0
);
7928 rtx op1
= expand_normal (arg1
);
7929 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7930 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7931 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
7933 if (icode
== CODE_FOR_nothing
)
7934 /* Builtin not supported on this processor. */
7937 /* If we got invalid arguments bail out before generating bad rtl. */
7938 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
7941 if (icode
== CODE_FOR_altivec_vcfux
7942 || icode
== CODE_FOR_altivec_vcfsx
7943 || icode
== CODE_FOR_altivec_vctsxs
7944 || icode
== CODE_FOR_altivec_vctuxs
7945 || icode
== CODE_FOR_altivec_vspltb
7946 || icode
== CODE_FOR_altivec_vsplth
7947 || icode
== CODE_FOR_altivec_vspltw
7948 || icode
== CODE_FOR_spe_evaddiw
7949 || icode
== CODE_FOR_spe_evldd
7950 || icode
== CODE_FOR_spe_evldh
7951 || icode
== CODE_FOR_spe_evldw
7952 || icode
== CODE_FOR_spe_evlhhesplat
7953 || icode
== CODE_FOR_spe_evlhhossplat
7954 || icode
== CODE_FOR_spe_evlhhousplat
7955 || icode
== CODE_FOR_spe_evlwhe
7956 || icode
== CODE_FOR_spe_evlwhos
7957 || icode
== CODE_FOR_spe_evlwhou
7958 || icode
== CODE_FOR_spe_evlwhsplat
7959 || icode
== CODE_FOR_spe_evlwwsplat
7960 || icode
== CODE_FOR_spe_evrlwi
7961 || icode
== CODE_FOR_spe_evslwi
7962 || icode
== CODE_FOR_spe_evsrwis
7963 || icode
== CODE_FOR_spe_evsubifw
7964 || icode
== CODE_FOR_spe_evsrwiu
)
7966 /* Only allow 5-bit unsigned literals. */
7968 if (TREE_CODE (arg1
) != INTEGER_CST
7969 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
7971 error ("argument 2 must be a 5-bit unsigned literal");
7977 || GET_MODE (target
) != tmode
7978 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7979 target
= gen_reg_rtx (tmode
);
7981 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7982 op0
= copy_to_mode_reg (mode0
, op0
);
7983 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
7984 op1
= copy_to_mode_reg (mode1
, op1
);
7986 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
7995 altivec_expand_predicate_builtin (enum insn_code icode
, const char *opcode
,
7996 tree exp
, rtx target
)
7999 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
8000 tree arg0
= CALL_EXPR_ARG (exp
, 1);
8001 tree arg1
= CALL_EXPR_ARG (exp
, 2);
8002 rtx op0
= expand_normal (arg0
);
8003 rtx op1
= expand_normal (arg1
);
8004 enum machine_mode tmode
= SImode
;
8005 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
8006 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
8009 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
8011 error ("argument 1 of __builtin_altivec_predicate must be a constant");
8015 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
8017 gcc_assert (mode0
== mode1
);
8019 /* If we have invalid arguments, bail out before generating bad rtl. */
8020 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
8024 || GET_MODE (target
) != tmode
8025 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8026 target
= gen_reg_rtx (tmode
);
8028 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8029 op0
= copy_to_mode_reg (mode0
, op0
);
8030 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
8031 op1
= copy_to_mode_reg (mode1
, op1
);
8033 scratch
= gen_reg_rtx (mode0
);
8035 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
,
8036 gen_rtx_SYMBOL_REF (Pmode
, opcode
));
8041 /* The vec_any* and vec_all* predicates use the same opcodes for two
8042 different operations, but the bits in CR6 will be different
8043 depending on what information we want. So we have to play tricks
8044 with CR6 to get the right bits out.
8046 If you think this is disgusting, look at the specs for the
8047 AltiVec predicates. */
8049 switch (cr6_form_int
)
8052 emit_insn (gen_cr6_test_for_zero (target
));
8055 emit_insn (gen_cr6_test_for_zero_reverse (target
));
8058 emit_insn (gen_cr6_test_for_lt (target
));
8061 emit_insn (gen_cr6_test_for_lt_reverse (target
));
8064 error ("argument 1 of __builtin_altivec_predicate is out of range");
8072 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
8075 tree arg0
= CALL_EXPR_ARG (exp
, 0);
8076 tree arg1
= CALL_EXPR_ARG (exp
, 1);
8077 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
8078 enum machine_mode mode0
= Pmode
;
8079 enum machine_mode mode1
= Pmode
;
8080 rtx op0
= expand_normal (arg0
);
8081 rtx op1
= expand_normal (arg1
);
8083 if (icode
== CODE_FOR_nothing
)
8084 /* Builtin not supported on this processor. */
8087 /* If we got invalid arguments bail out before generating bad rtl. */
8088 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
8092 || GET_MODE (target
) != tmode
8093 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8094 target
= gen_reg_rtx (tmode
);
8096 op1
= copy_to_mode_reg (mode1
, op1
);
8098 if (op0
== const0_rtx
)
8100 addr
= gen_rtx_MEM (tmode
, op1
);
8104 op0
= copy_to_mode_reg (mode0
, op0
);
8105 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
8108 pat
= GEN_FCN (icode
) (target
, addr
);
8118 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
8121 tree arg0
= CALL_EXPR_ARG (exp
, 0);
8122 tree arg1
= CALL_EXPR_ARG (exp
, 1);
8123 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
8124 enum machine_mode mode0
= Pmode
;
8125 enum machine_mode mode1
= Pmode
;
8126 rtx op0
= expand_normal (arg0
);
8127 rtx op1
= expand_normal (arg1
);
8129 if (icode
== CODE_FOR_nothing
)
8130 /* Builtin not supported on this processor. */
8133 /* If we got invalid arguments bail out before generating bad rtl. */
8134 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
8138 || GET_MODE (target
) != tmode
8139 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8140 target
= gen_reg_rtx (tmode
);
8142 op1
= copy_to_mode_reg (mode1
, op1
);
8144 if (op0
== const0_rtx
)
8146 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
8150 op0
= copy_to_mode_reg (mode0
, op0
);
8151 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
8154 pat
= GEN_FCN (icode
) (target
, addr
);
8164 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
8166 tree arg0
= CALL_EXPR_ARG (exp
, 0);
8167 tree arg1
= CALL_EXPR_ARG (exp
, 1);
8168 tree arg2
= CALL_EXPR_ARG (exp
, 2);
8169 rtx op0
= expand_normal (arg0
);
8170 rtx op1
= expand_normal (arg1
);
8171 rtx op2
= expand_normal (arg2
);
8173 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
8174 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
8175 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
8177 /* Invalid arguments. Bail before doing anything stoopid! */
8178 if (arg0
== error_mark_node
8179 || arg1
== error_mark_node
8180 || arg2
== error_mark_node
)
8183 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
8184 op0
= copy_to_mode_reg (mode2
, op0
);
8185 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
8186 op1
= copy_to_mode_reg (mode0
, op1
);
8187 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
8188 op2
= copy_to_mode_reg (mode1
, op2
);
8190 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
8197 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
8199 tree arg0
= CALL_EXPR_ARG (exp
, 0);
8200 tree arg1
= CALL_EXPR_ARG (exp
, 1);
8201 tree arg2
= CALL_EXPR_ARG (exp
, 2);
8202 rtx op0
= expand_normal (arg0
);
8203 rtx op1
= expand_normal (arg1
);
8204 rtx op2
= expand_normal (arg2
);
8206 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
8207 enum machine_mode mode1
= Pmode
;
8208 enum machine_mode mode2
= Pmode
;
8210 /* Invalid arguments. Bail before doing anything stoopid! */
8211 if (arg0
== error_mark_node
8212 || arg1
== error_mark_node
8213 || arg2
== error_mark_node
)
8216 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
8217 op0
= copy_to_mode_reg (tmode
, op0
);
8219 op2
= copy_to_mode_reg (mode2
, op2
);
8221 if (op1
== const0_rtx
)
8223 addr
= gen_rtx_MEM (tmode
, op2
);
8227 op1
= copy_to_mode_reg (mode1
, op1
);
8228 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
8231 pat
= GEN_FCN (icode
) (addr
, op0
);
8238 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
8240 tree arg0
= CALL_EXPR_ARG (exp
, 0);
8241 tree arg1
= CALL_EXPR_ARG (exp
, 1);
8242 tree arg2
= CALL_EXPR_ARG (exp
, 2);
8243 rtx op0
= expand_normal (arg0
);
8244 rtx op1
= expand_normal (arg1
);
8245 rtx op2
= expand_normal (arg2
);
8247 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
8248 enum machine_mode mode1
= Pmode
;
8249 enum machine_mode mode2
= Pmode
;
8251 /* Invalid arguments. Bail before doing anything stoopid! */
8252 if (arg0
== error_mark_node
8253 || arg1
== error_mark_node
8254 || arg2
== error_mark_node
)
8257 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
8258 op0
= copy_to_mode_reg (tmode
, op0
);
8260 op2
= copy_to_mode_reg (mode2
, op2
);
8262 if (op1
== const0_rtx
)
8264 addr
= gen_rtx_MEM (tmode
, op2
);
8268 op1
= copy_to_mode_reg (mode1
, op1
);
8269 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
8272 pat
= GEN_FCN (icode
) (addr
, op0
);
8279 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
8282 tree arg0
= CALL_EXPR_ARG (exp
, 0);
8283 tree arg1
= CALL_EXPR_ARG (exp
, 1);
8284 tree arg2
= CALL_EXPR_ARG (exp
, 2);
8285 rtx op0
= expand_normal (arg0
);
8286 rtx op1
= expand_normal (arg1
);
8287 rtx op2
= expand_normal (arg2
);
8288 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
8289 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
8290 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
8291 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
8293 if (icode
== CODE_FOR_nothing
)
8294 /* Builtin not supported on this processor. */
8297 /* If we got invalid arguments bail out before generating bad rtl. */
8298 if (arg0
== error_mark_node
8299 || arg1
== error_mark_node
8300 || arg2
== error_mark_node
)
8303 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
8304 || icode
== CODE_FOR_altivec_vsldoi_v4si
8305 || icode
== CODE_FOR_altivec_vsldoi_v8hi
8306 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
8308 /* Only allow 4-bit unsigned literals. */
8310 if (TREE_CODE (arg2
) != INTEGER_CST
8311 || TREE_INT_CST_LOW (arg2
) & ~0xf)
8313 error ("argument 3 must be a 4-bit unsigned literal");
8319 || GET_MODE (target
) != tmode
8320 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8321 target
= gen_reg_rtx (tmode
);
8323 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8324 op0
= copy_to_mode_reg (mode0
, op0
);
8325 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
8326 op1
= copy_to_mode_reg (mode1
, op1
);
8327 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
8328 op2
= copy_to_mode_reg (mode2
, op2
);
8330 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
8331 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
8333 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
8341 /* Expand the lvx builtins. */
8343 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
8345 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8346 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8348 enum machine_mode tmode
, mode0
;
8350 enum insn_code icode
;
8354 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
8355 icode
= CODE_FOR_altivec_lvx_v16qi
;
8357 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
8358 icode
= CODE_FOR_altivec_lvx_v8hi
;
8360 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
8361 icode
= CODE_FOR_altivec_lvx_v4si
;
8363 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
8364 icode
= CODE_FOR_altivec_lvx_v4sf
;
8373 arg0
= CALL_EXPR_ARG (exp
, 0);
8374 op0
= expand_normal (arg0
);
8375 tmode
= insn_data
[icode
].operand
[0].mode
;
8376 mode0
= insn_data
[icode
].operand
[1].mode
;
8379 || GET_MODE (target
) != tmode
8380 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8381 target
= gen_reg_rtx (tmode
);
8383 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8384 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
8386 pat
= GEN_FCN (icode
) (target
, op0
);
8393 /* Expand the stvx builtins. */
8395 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
8398 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8399 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8401 enum machine_mode mode0
, mode1
;
8403 enum insn_code icode
;
8407 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
8408 icode
= CODE_FOR_altivec_stvx_v16qi
;
8410 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
8411 icode
= CODE_FOR_altivec_stvx_v8hi
;
8413 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
8414 icode
= CODE_FOR_altivec_stvx_v4si
;
8416 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
8417 icode
= CODE_FOR_altivec_stvx_v4sf
;
8424 arg0
= CALL_EXPR_ARG (exp
, 0);
8425 arg1
= CALL_EXPR_ARG (exp
, 1);
8426 op0
= expand_normal (arg0
);
8427 op1
= expand_normal (arg1
);
8428 mode0
= insn_data
[icode
].operand
[0].mode
;
8429 mode1
= insn_data
[icode
].operand
[1].mode
;
8431 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
8432 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
8433 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
8434 op1
= copy_to_mode_reg (mode1
, op1
);
8436 pat
= GEN_FCN (icode
) (op0
, op1
);
8444 /* Expand the dst builtins. */
8446 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
8449 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8450 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8451 tree arg0
, arg1
, arg2
;
8452 enum machine_mode mode0
, mode1
, mode2
;
8453 rtx pat
, op0
, op1
, op2
;
8454 const struct builtin_description
*d
;
8459 /* Handle DST variants. */
8461 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
8462 if (d
->code
== fcode
)
8464 arg0
= CALL_EXPR_ARG (exp
, 0);
8465 arg1
= CALL_EXPR_ARG (exp
, 1);
8466 arg2
= CALL_EXPR_ARG (exp
, 2);
8467 op0
= expand_normal (arg0
);
8468 op1
= expand_normal (arg1
);
8469 op2
= expand_normal (arg2
);
8470 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
8471 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
8472 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
8474 /* Invalid arguments, bail out before generating bad rtl. */
8475 if (arg0
== error_mark_node
8476 || arg1
== error_mark_node
8477 || arg2
== error_mark_node
)
8482 if (TREE_CODE (arg2
) != INTEGER_CST
8483 || TREE_INT_CST_LOW (arg2
) & ~0x3)
8485 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
8489 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
8490 op0
= copy_to_mode_reg (Pmode
, op0
);
8491 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
8492 op1
= copy_to_mode_reg (mode1
, op1
);
8494 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
8504 /* Expand vec_init builtin. */
8506 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
8508 enum machine_mode tmode
= TYPE_MODE (type
);
8509 enum machine_mode inner_mode
= GET_MODE_INNER (tmode
);
8510 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
8511 rtvec v
= rtvec_alloc (n_elt
);
8513 gcc_assert (VECTOR_MODE_P (tmode
));
8514 gcc_assert (n_elt
== call_expr_nargs (exp
));
8516 for (i
= 0; i
< n_elt
; ++i
)
8518 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
8519 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
8522 if (!target
|| !register_operand (target
, tmode
))
8523 target
= gen_reg_rtx (tmode
);
8525 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
8529 /* Return the integer constant in ARG. Constrain it to be in the range
8530 of the subparts of VEC_TYPE; issue an error if not. */
8533 get_element_number (tree vec_type
, tree arg
)
8535 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
8537 if (!host_integerp (arg
, 1)
8538 || (elt
= tree_low_cst (arg
, 1), elt
> max
))
8540 error ("selector must be an integer constant in the range 0..%wi", max
);
8547 /* Expand vec_set builtin. */
8549 altivec_expand_vec_set_builtin (tree exp
)
8551 enum machine_mode tmode
, mode1
;
8552 tree arg0
, arg1
, arg2
;
8556 arg0
= CALL_EXPR_ARG (exp
, 0);
8557 arg1
= CALL_EXPR_ARG (exp
, 1);
8558 arg2
= CALL_EXPR_ARG (exp
, 2);
8560 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
8561 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
8562 gcc_assert (VECTOR_MODE_P (tmode
));
8564 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
8565 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
8566 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
8568 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
8569 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
8571 op0
= force_reg (tmode
, op0
);
8572 op1
= force_reg (mode1
, op1
);
8574 rs6000_expand_vector_set (op0
, op1
, elt
);
8579 /* Expand vec_ext builtin. */
8581 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
8583 enum machine_mode tmode
, mode0
;
8588 arg0
= CALL_EXPR_ARG (exp
, 0);
8589 arg1
= CALL_EXPR_ARG (exp
, 1);
8591 op0
= expand_normal (arg0
);
8592 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
8594 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
8595 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
8596 gcc_assert (VECTOR_MODE_P (mode0
));
8598 op0
= force_reg (mode0
, op0
);
8600 if (optimize
|| !target
|| !register_operand (target
, tmode
))
8601 target
= gen_reg_rtx (tmode
);
8603 rs6000_expand_vector_extract (target
, op0
, elt
);
8608 /* Expand the builtin in EXP and store the result in TARGET. Store
8609 true in *EXPANDEDP if we found a builtin to expand. */
8611 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
8613 const struct builtin_description
*d
;
8614 const struct builtin_description_predicates
*dp
;
8616 enum insn_code icode
;
8617 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8620 enum machine_mode tmode
, mode0
;
8621 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8623 if (fcode
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8624 && fcode
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
)
8627 error ("unresolved overload for Altivec builtin %qF", fndecl
);
8631 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
8635 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
8639 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
8647 case ALTIVEC_BUILTIN_STVX
:
8648 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx
, exp
);
8649 case ALTIVEC_BUILTIN_STVEBX
:
8650 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
8651 case ALTIVEC_BUILTIN_STVEHX
:
8652 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
8653 case ALTIVEC_BUILTIN_STVEWX
:
8654 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
8655 case ALTIVEC_BUILTIN_STVXL
:
8656 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl
, exp
);
8658 case ALTIVEC_BUILTIN_STVLX
:
8659 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
8660 case ALTIVEC_BUILTIN_STVLXL
:
8661 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
8662 case ALTIVEC_BUILTIN_STVRX
:
8663 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
8664 case ALTIVEC_BUILTIN_STVRXL
:
8665 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
8667 case ALTIVEC_BUILTIN_MFVSCR
:
8668 icode
= CODE_FOR_altivec_mfvscr
;
8669 tmode
= insn_data
[icode
].operand
[0].mode
;
8672 || GET_MODE (target
) != tmode
8673 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8674 target
= gen_reg_rtx (tmode
);
8676 pat
= GEN_FCN (icode
) (target
);
8682 case ALTIVEC_BUILTIN_MTVSCR
:
8683 icode
= CODE_FOR_altivec_mtvscr
;
8684 arg0
= CALL_EXPR_ARG (exp
, 0);
8685 op0
= expand_normal (arg0
);
8686 mode0
= insn_data
[icode
].operand
[0].mode
;
8688 /* If we got invalid arguments bail out before generating bad rtl. */
8689 if (arg0
== error_mark_node
)
8692 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
8693 op0
= copy_to_mode_reg (mode0
, op0
);
8695 pat
= GEN_FCN (icode
) (op0
);
8700 case ALTIVEC_BUILTIN_DSSALL
:
8701 emit_insn (gen_altivec_dssall ());
8704 case ALTIVEC_BUILTIN_DSS
:
8705 icode
= CODE_FOR_altivec_dss
;
8706 arg0
= CALL_EXPR_ARG (exp
, 0);
8708 op0
= expand_normal (arg0
);
8709 mode0
= insn_data
[icode
].operand
[0].mode
;
8711 /* If we got invalid arguments bail out before generating bad rtl. */
8712 if (arg0
== error_mark_node
)
8715 if (TREE_CODE (arg0
) != INTEGER_CST
8716 || TREE_INT_CST_LOW (arg0
) & ~0x3)
8718 error ("argument to dss must be a 2-bit unsigned literal");
8722 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
8723 op0
= copy_to_mode_reg (mode0
, op0
);
8725 emit_insn (gen_altivec_dss (op0
));
8728 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
8729 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
8730 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
8731 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
8732 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
8734 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
8735 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
8736 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
8737 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
8738 return altivec_expand_vec_set_builtin (exp
);
8740 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
8741 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
8742 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
8743 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
8744 return altivec_expand_vec_ext_builtin (exp
, target
);
8751 /* Expand abs* operations. */
8753 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
8754 if (d
->code
== fcode
)
8755 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
8757 /* Expand the AltiVec predicates. */
8758 dp
= bdesc_altivec_preds
;
8759 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, dp
++)
8760 if (dp
->code
== fcode
)
8761 return altivec_expand_predicate_builtin (dp
->icode
, dp
->opcode
,
8764 /* LV* are funky. We initialized them differently. */
8767 case ALTIVEC_BUILTIN_LVSL
:
8768 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
8769 exp
, target
, false);
8770 case ALTIVEC_BUILTIN_LVSR
:
8771 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
8772 exp
, target
, false);
8773 case ALTIVEC_BUILTIN_LVEBX
:
8774 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
8775 exp
, target
, false);
8776 case ALTIVEC_BUILTIN_LVEHX
:
8777 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
8778 exp
, target
, false);
8779 case ALTIVEC_BUILTIN_LVEWX
:
8780 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
8781 exp
, target
, false);
8782 case ALTIVEC_BUILTIN_LVXL
:
8783 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl
,
8784 exp
, target
, false);
8785 case ALTIVEC_BUILTIN_LVX
:
8786 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx
,
8787 exp
, target
, false);
8788 case ALTIVEC_BUILTIN_LVLX
:
8789 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
8791 case ALTIVEC_BUILTIN_LVLXL
:
8792 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
8794 case ALTIVEC_BUILTIN_LVRX
:
8795 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
8797 case ALTIVEC_BUILTIN_LVRXL
:
8798 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
8809 /* Expand the builtin in EXP and store the result in TARGET. Store
8810 true in *EXPANDEDP if we found a builtin to expand. */
8812 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
8814 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8815 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8816 const struct builtin_description
*d
;
8823 case PAIRED_BUILTIN_STX
:
8824 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
8825 case PAIRED_BUILTIN_LX
:
8826 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
8832 /* Expand the paired predicates. */
8833 d
= bdesc_paired_preds
;
8834 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
8835 if (d
->code
== fcode
)
8836 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
8842 /* Binops that need to be initialized manually, but can be expanded
8843 automagically by rs6000_expand_binop_builtin. */
8844 static struct builtin_description bdesc_2arg_spe
[] =
8846 { 0, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
8847 { 0, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
8848 { 0, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
8849 { 0, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
8850 { 0, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
8851 { 0, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
8852 { 0, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
8853 { 0, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
8854 { 0, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
8855 { 0, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
8856 { 0, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
8857 { 0, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
8858 { 0, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
8859 { 0, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
8860 { 0, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
8861 { 0, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
8862 { 0, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
8863 { 0, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
8864 { 0, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
8865 { 0, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
8866 { 0, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
8867 { 0, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
8870 /* Expand the builtin in EXP and store the result in TARGET. Store
8871 true in *EXPANDEDP if we found a builtin to expand.
8873 This expands the SPE builtins that are not simple unary and binary
8876 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
8878 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8880 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8881 enum insn_code icode
;
8882 enum machine_mode tmode
, mode0
;
8884 struct builtin_description
*d
;
8889 /* Syntax check for a 5-bit unsigned immediate. */
8892 case SPE_BUILTIN_EVSTDD
:
8893 case SPE_BUILTIN_EVSTDH
:
8894 case SPE_BUILTIN_EVSTDW
:
8895 case SPE_BUILTIN_EVSTWHE
:
8896 case SPE_BUILTIN_EVSTWHO
:
8897 case SPE_BUILTIN_EVSTWWE
:
8898 case SPE_BUILTIN_EVSTWWO
:
8899 arg1
= CALL_EXPR_ARG (exp
, 2);
8900 if (TREE_CODE (arg1
) != INTEGER_CST
8901 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
8903 error ("argument 2 must be a 5-bit unsigned literal");
8911 /* The evsplat*i instructions are not quite generic. */
8914 case SPE_BUILTIN_EVSPLATFI
:
8915 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
8917 case SPE_BUILTIN_EVSPLATI
:
8918 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
8924 d
= (struct builtin_description
*) bdesc_2arg_spe
;
8925 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
8926 if (d
->code
== fcode
)
8927 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
8929 d
= (struct builtin_description
*) bdesc_spe_predicates
;
8930 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
8931 if (d
->code
== fcode
)
8932 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
8934 d
= (struct builtin_description
*) bdesc_spe_evsel
;
8935 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
8936 if (d
->code
== fcode
)
8937 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
8941 case SPE_BUILTIN_EVSTDDX
:
8942 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
8943 case SPE_BUILTIN_EVSTDHX
:
8944 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
8945 case SPE_BUILTIN_EVSTDWX
:
8946 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
8947 case SPE_BUILTIN_EVSTWHEX
:
8948 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
8949 case SPE_BUILTIN_EVSTWHOX
:
8950 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
8951 case SPE_BUILTIN_EVSTWWEX
:
8952 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
8953 case SPE_BUILTIN_EVSTWWOX
:
8954 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
8955 case SPE_BUILTIN_EVSTDD
:
8956 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
8957 case SPE_BUILTIN_EVSTDH
:
8958 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
8959 case SPE_BUILTIN_EVSTDW
:
8960 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
8961 case SPE_BUILTIN_EVSTWHE
:
8962 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
8963 case SPE_BUILTIN_EVSTWHO
:
8964 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
8965 case SPE_BUILTIN_EVSTWWE
:
8966 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
8967 case SPE_BUILTIN_EVSTWWO
:
8968 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
8969 case SPE_BUILTIN_MFSPEFSCR
:
8970 icode
= CODE_FOR_spe_mfspefscr
;
8971 tmode
= insn_data
[icode
].operand
[0].mode
;
8974 || GET_MODE (target
) != tmode
8975 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8976 target
= gen_reg_rtx (tmode
);
8978 pat
= GEN_FCN (icode
) (target
);
8983 case SPE_BUILTIN_MTSPEFSCR
:
8984 icode
= CODE_FOR_spe_mtspefscr
;
8985 arg0
= CALL_EXPR_ARG (exp
, 0);
8986 op0
= expand_normal (arg0
);
8987 mode0
= insn_data
[icode
].operand
[0].mode
;
8989 if (arg0
== error_mark_node
)
8992 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
8993 op0
= copy_to_mode_reg (mode0
, op0
);
8995 pat
= GEN_FCN (icode
) (op0
);
9008 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
9010 rtx pat
, scratch
, tmp
;
9011 tree form
= CALL_EXPR_ARG (exp
, 0);
9012 tree arg0
= CALL_EXPR_ARG (exp
, 1);
9013 tree arg1
= CALL_EXPR_ARG (exp
, 2);
9014 rtx op0
= expand_normal (arg0
);
9015 rtx op1
= expand_normal (arg1
);
9016 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
9017 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
9021 if (TREE_CODE (form
) != INTEGER_CST
)
9023 error ("argument 1 of __builtin_paired_predicate must be a constant");
9027 form_int
= TREE_INT_CST_LOW (form
);
9029 gcc_assert (mode0
== mode1
);
9031 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
9035 || GET_MODE (target
) != SImode
9036 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
9037 target
= gen_reg_rtx (SImode
);
9038 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
9039 op0
= copy_to_mode_reg (mode0
, op0
);
9040 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
9041 op1
= copy_to_mode_reg (mode1
, op1
);
9043 scratch
= gen_reg_rtx (CCFPmode
);
9045 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
9067 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
9070 error ("argument 1 of __builtin_paired_predicate is out of range");
9074 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
9075 emit_move_insn (target
, tmp
);
9080 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
9082 rtx pat
, scratch
, tmp
;
9083 tree form
= CALL_EXPR_ARG (exp
, 0);
9084 tree arg0
= CALL_EXPR_ARG (exp
, 1);
9085 tree arg1
= CALL_EXPR_ARG (exp
, 2);
9086 rtx op0
= expand_normal (arg0
);
9087 rtx op1
= expand_normal (arg1
);
9088 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
9089 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
9093 if (TREE_CODE (form
) != INTEGER_CST
)
9095 error ("argument 1 of __builtin_spe_predicate must be a constant");
9099 form_int
= TREE_INT_CST_LOW (form
);
9101 gcc_assert (mode0
== mode1
);
9103 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
9107 || GET_MODE (target
) != SImode
9108 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
9109 target
= gen_reg_rtx (SImode
);
9111 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
9112 op0
= copy_to_mode_reg (mode0
, op0
);
9113 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
9114 op1
= copy_to_mode_reg (mode1
, op1
);
9116 scratch
= gen_reg_rtx (CCmode
);
9118 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
9123 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
9124 _lower_. We use one compare, but look in different bits of the
9125 CR for each variant.
9127 There are 2 elements in each SPE simd type (upper/lower). The CR
9128 bits are set as follows:
9130 BIT0 | BIT 1 | BIT 2 | BIT 3
9131 U | L | (U | L) | (U & L)
9133 So, for an "all" relationship, BIT 3 would be set.
9134 For an "any" relationship, BIT 2 would be set. Etc.
9136 Following traditional nomenclature, these bits map to:
9138 BIT0 | BIT 1 | BIT 2 | BIT 3
9141 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
9146 /* All variant. OV bit. */
9148 /* We need to get to the OV bit, which is the ORDERED bit. We
9149 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
9150 that's ugly and will make validate_condition_mode die.
9151 So let's just use another pattern. */
9152 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
9154 /* Any variant. EQ bit. */
9158 /* Upper variant. LT bit. */
9162 /* Lower variant. GT bit. */
9167 error ("argument 1 of __builtin_spe_predicate is out of range");
9171 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
9172 emit_move_insn (target
, tmp
);
9177 /* The evsel builtins look like this:
9179 e = __builtin_spe_evsel_OP (a, b, c, d);
9183 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
9184 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
9188 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
9191 tree arg0
= CALL_EXPR_ARG (exp
, 0);
9192 tree arg1
= CALL_EXPR_ARG (exp
, 1);
9193 tree arg2
= CALL_EXPR_ARG (exp
, 2);
9194 tree arg3
= CALL_EXPR_ARG (exp
, 3);
9195 rtx op0
= expand_normal (arg0
);
9196 rtx op1
= expand_normal (arg1
);
9197 rtx op2
= expand_normal (arg2
);
9198 rtx op3
= expand_normal (arg3
);
9199 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
9200 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
9202 gcc_assert (mode0
== mode1
);
9204 if (arg0
== error_mark_node
|| arg1
== error_mark_node
9205 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
9209 || GET_MODE (target
) != mode0
9210 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
9211 target
= gen_reg_rtx (mode0
);
9213 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
9214 op0
= copy_to_mode_reg (mode0
, op0
);
9215 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
9216 op1
= copy_to_mode_reg (mode0
, op1
);
9217 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
9218 op2
= copy_to_mode_reg (mode0
, op2
);
9219 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
9220 op3
= copy_to_mode_reg (mode0
, op3
);
9222 /* Generate the compare. */
9223 scratch
= gen_reg_rtx (CCmode
);
9224 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
9229 if (mode0
== V2SImode
)
9230 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
9232 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
9237 /* Expand an expression EXP that calls a built-in function,
9238 with result going to TARGET if that's convenient
9239 (and in mode MODE if that's convenient).
9240 SUBTARGET may be used as the target for computing one of EXP's operands.
9241 IGNORE is nonzero if the value is to be ignored. */
9244 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
9245 enum machine_mode mode ATTRIBUTE_UNUSED
,
9246 int ignore ATTRIBUTE_UNUSED
)
9248 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9249 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
9250 const struct builtin_description
*d
;
9255 if (fcode
== RS6000_BUILTIN_RECIP
)
9256 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
9258 if (fcode
== RS6000_BUILTIN_RECIPF
)
9259 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
9261 if (fcode
== RS6000_BUILTIN_RSQRTF
)
9262 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
9264 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_LOAD
9265 || fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
9267 int icode
= (int) CODE_FOR_altivec_lvsr
;
9268 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9269 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
9273 gcc_assert (TARGET_ALTIVEC
);
9275 arg
= CALL_EXPR_ARG (exp
, 0);
9276 gcc_assert (TREE_CODE (TREE_TYPE (arg
)) == POINTER_TYPE
);
9277 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
9278 addr
= memory_address (mode
, op
);
9279 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
9283 /* For the load case need to negate the address. */
9284 op
= gen_reg_rtx (GET_MODE (addr
));
9285 emit_insn (gen_rtx_SET (VOIDmode
, op
,
9286 gen_rtx_NEG (GET_MODE (addr
), addr
)));
9288 op
= gen_rtx_MEM (mode
, op
);
9291 || GET_MODE (target
) != tmode
9292 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9293 target
= gen_reg_rtx (tmode
);
9295 /*pat = gen_altivec_lvsr (target, op);*/
9296 pat
= GEN_FCN (icode
) (target
, op
);
9304 /* FIXME: There's got to be a nicer way to handle this case than
9305 constructing a new CALL_EXPR. */
9306 if (fcode
== ALTIVEC_BUILTIN_VCFUX
9307 || fcode
== ALTIVEC_BUILTIN_VCFSX
9308 || fcode
== ALTIVEC_BUILTIN_VCTUXS
9309 || fcode
== ALTIVEC_BUILTIN_VCTSXS
)
9311 if (call_expr_nargs (exp
) == 1)
9312 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
9313 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
9318 ret
= altivec_expand_builtin (exp
, target
, &success
);
9325 ret
= spe_expand_builtin (exp
, target
, &success
);
9330 if (TARGET_PAIRED_FLOAT
)
9332 ret
= paired_expand_builtin (exp
, target
, &success
);
9338 gcc_assert (TARGET_ALTIVEC
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
);
9340 /* Handle simple unary operations. */
9341 d
= (struct builtin_description
*) bdesc_1arg
;
9342 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
9343 if (d
->code
== fcode
)
9344 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
9346 /* Handle simple binary operations. */
9347 d
= (struct builtin_description
*) bdesc_2arg
;
9348 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
9349 if (d
->code
== fcode
)
9350 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
9352 /* Handle simple ternary operations. */
9354 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
9355 if (d
->code
== fcode
)
9356 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
9362 rs6000_init_builtins (void)
9366 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
9367 V2SF_type_node
= build_vector_type (float_type_node
, 2);
9368 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
9369 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
9370 V4SF_type_node
= build_vector_type (float_type_node
, 4);
9371 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
9372 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
9374 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
9375 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
9376 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
9378 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
9379 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
9380 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
9381 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
9383 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
9384 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
9385 'vector unsigned short'. */
9387 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
9388 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
9389 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
9390 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
9392 long_integer_type_internal_node
= long_integer_type_node
;
9393 long_unsigned_type_internal_node
= long_unsigned_type_node
;
9394 intQI_type_internal_node
= intQI_type_node
;
9395 uintQI_type_internal_node
= unsigned_intQI_type_node
;
9396 intHI_type_internal_node
= intHI_type_node
;
9397 uintHI_type_internal_node
= unsigned_intHI_type_node
;
9398 intSI_type_internal_node
= intSI_type_node
;
9399 uintSI_type_internal_node
= unsigned_intSI_type_node
;
9400 float_type_internal_node
= float_type_node
;
9401 void_type_internal_node
= void_type_node
;
9403 tdecl
= build_decl (TYPE_DECL
, get_identifier ("__bool char"),
9404 bool_char_type_node
);
9405 TYPE_NAME (bool_char_type_node
) = tdecl
;
9406 (*lang_hooks
.decls
.pushdecl
) (tdecl
);
9407 tdecl
= build_decl (TYPE_DECL
, get_identifier ("__bool short"),
9408 bool_short_type_node
);
9409 TYPE_NAME (bool_short_type_node
) = tdecl
;
9410 (*lang_hooks
.decls
.pushdecl
) (tdecl
);
9411 tdecl
= build_decl (TYPE_DECL
, get_identifier ("__bool int"),
9412 bool_int_type_node
);
9413 TYPE_NAME (bool_int_type_node
) = tdecl
;
9414 (*lang_hooks
.decls
.pushdecl
) (tdecl
);
9415 tdecl
= build_decl (TYPE_DECL
, get_identifier ("__pixel"),
9417 TYPE_NAME (pixel_type_node
) = tdecl
;
9418 (*lang_hooks
.decls
.pushdecl
) (tdecl
);
9420 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
9421 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
9422 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
9423 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
9425 tdecl
= build_decl (TYPE_DECL
, get_identifier ("__vector unsigned char"),
9426 unsigned_V16QI_type_node
);
9427 TYPE_NAME (unsigned_V16QI_type_node
) = tdecl
;
9428 (*lang_hooks
.decls
.pushdecl
) (tdecl
);
9429 tdecl
= build_decl (TYPE_DECL
, get_identifier ("__vector signed char"),
9431 TYPE_NAME (V16QI_type_node
) = tdecl
;
9432 (*lang_hooks
.decls
.pushdecl
) (tdecl
);
9433 tdecl
= build_decl (TYPE_DECL
, get_identifier ("__vector __bool char"),
9434 bool_V16QI_type_node
);
9435 TYPE_NAME ( bool_V16QI_type_node
) = tdecl
;
9436 (*lang_hooks
.decls
.pushdecl
) (tdecl
);
9438 tdecl
= build_decl (TYPE_DECL
, get_identifier ("__vector unsigned short"),
9439 unsigned_V8HI_type_node
);
9440 TYPE_NAME (unsigned_V8HI_type_node
) = tdecl
;
9441 (*lang_hooks
.decls
.pushdecl
) (tdecl
);
9442 tdecl
= build_decl (TYPE_DECL
, get_identifier ("__vector signed short"),
9444 TYPE_NAME (V8HI_type_node
) = tdecl
;
9445 (*lang_hooks
.decls
.pushdecl
) (tdecl
);
9446 tdecl
= build_decl (TYPE_DECL
, get_identifier ("__vector __bool short"),
9447 bool_V8HI_type_node
);
9448 TYPE_NAME (bool_V8HI_type_node
) = tdecl
;
9449 (*lang_hooks
.decls
.pushdecl
) (tdecl
);
9451 tdecl
= build_decl (TYPE_DECL
, get_identifier ("__vector unsigned int"),
9452 unsigned_V4SI_type_node
);
9453 TYPE_NAME (unsigned_V4SI_type_node
) = tdecl
;
9454 (*lang_hooks
.decls
.pushdecl
) (tdecl
);
9455 tdecl
= build_decl (TYPE_DECL
, get_identifier ("__vector signed int"),
9457 TYPE_NAME (V4SI_type_node
) = tdecl
;
9458 (*lang_hooks
.decls
.pushdecl
) (tdecl
);
9459 tdecl
= build_decl (TYPE_DECL
, get_identifier ("__vector __bool int"),
9460 bool_V4SI_type_node
);
9461 TYPE_NAME (bool_V4SI_type_node
) = tdecl
;
9462 (*lang_hooks
.decls
.pushdecl
) (tdecl
);
9464 tdecl
= build_decl (TYPE_DECL
, get_identifier ("__vector float"),
9466 TYPE_NAME (V4SF_type_node
) = tdecl
;
9467 (*lang_hooks
.decls
.pushdecl
) (tdecl
);
9468 tdecl
= build_decl (TYPE_DECL
, get_identifier ("__vector __pixel"),
9469 pixel_V8HI_type_node
);
9470 TYPE_NAME (pixel_V8HI_type_node
) = tdecl
;
9471 (*lang_hooks
.decls
.pushdecl
) (tdecl
);
9473 if (TARGET_PAIRED_FLOAT
)
9474 paired_init_builtins ();
9476 spe_init_builtins ();
9478 altivec_init_builtins ();
9479 if (TARGET_ALTIVEC
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
9480 rs6000_common_init_builtins ();
9481 if (TARGET_PPC_GFXOPT
)
9483 tree ftype
= build_function_type_list (float_type_node
,
9487 def_builtin (MASK_PPC_GFXOPT
, "__builtin_recipdivf", ftype
,
9488 RS6000_BUILTIN_RECIPF
);
9490 ftype
= build_function_type_list (float_type_node
,
9493 def_builtin (MASK_PPC_GFXOPT
, "__builtin_rsqrtf", ftype
,
9494 RS6000_BUILTIN_RSQRTF
);
9498 tree ftype
= build_function_type_list (double_type_node
,
9502 def_builtin (MASK_POPCNTB
, "__builtin_recipdiv", ftype
,
9503 RS6000_BUILTIN_RECIP
);
9508 /* AIX libm provides clog as __clog. */
9509 if (built_in_decls
[BUILT_IN_CLOG
])
9510 set_user_assembler_name (built_in_decls
[BUILT_IN_CLOG
], "__clog");
9513 #ifdef SUBTARGET_INIT_BUILTINS
9514 SUBTARGET_INIT_BUILTINS
;
9518 /* Search through a set of builtins and enable the mask bits.
9519 DESC is an array of builtins.
9520 SIZE is the total number of builtins.
9521 START is the builtin enum at which to start.
9522 END is the builtin enum at which to end. */
9524 enable_mask_for_builtins (struct builtin_description
*desc
, int size
,
9525 enum rs6000_builtins start
,
9526 enum rs6000_builtins end
)
9530 for (i
= 0; i
< size
; ++i
)
9531 if (desc
[i
].code
== start
)
9537 for (; i
< size
; ++i
)
9539 /* Flip all the bits on. */
9540 desc
[i
].mask
= target_flags
;
9541 if (desc
[i
].code
== end
)
9547 spe_init_builtins (void)
9549 tree endlink
= void_list_node
;
9550 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
9551 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
9552 struct builtin_description
*d
;
9555 tree v2si_ftype_4_v2si
9556 = build_function_type
9557 (opaque_V2SI_type_node
,
9558 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9559 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9560 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9561 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9564 tree v2sf_ftype_4_v2sf
9565 = build_function_type
9566 (opaque_V2SF_type_node
,
9567 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9568 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9569 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9570 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9573 tree int_ftype_int_v2si_v2si
9574 = build_function_type
9576 tree_cons (NULL_TREE
, integer_type_node
,
9577 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9578 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9581 tree int_ftype_int_v2sf_v2sf
9582 = build_function_type
9584 tree_cons (NULL_TREE
, integer_type_node
,
9585 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9586 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9589 tree void_ftype_v2si_puint_int
9590 = build_function_type (void_type_node
,
9591 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9592 tree_cons (NULL_TREE
, puint_type_node
,
9593 tree_cons (NULL_TREE
,
9597 tree void_ftype_v2si_puint_char
9598 = build_function_type (void_type_node
,
9599 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9600 tree_cons (NULL_TREE
, puint_type_node
,
9601 tree_cons (NULL_TREE
,
9605 tree void_ftype_v2si_pv2si_int
9606 = build_function_type (void_type_node
,
9607 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9608 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
9609 tree_cons (NULL_TREE
,
9613 tree void_ftype_v2si_pv2si_char
9614 = build_function_type (void_type_node
,
9615 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9616 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
9617 tree_cons (NULL_TREE
,
9622 = build_function_type (void_type_node
,
9623 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
9626 = build_function_type (integer_type_node
, endlink
);
9628 tree v2si_ftype_pv2si_int
9629 = build_function_type (opaque_V2SI_type_node
,
9630 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
9631 tree_cons (NULL_TREE
, integer_type_node
,
9634 tree v2si_ftype_puint_int
9635 = build_function_type (opaque_V2SI_type_node
,
9636 tree_cons (NULL_TREE
, puint_type_node
,
9637 tree_cons (NULL_TREE
, integer_type_node
,
9640 tree v2si_ftype_pushort_int
9641 = build_function_type (opaque_V2SI_type_node
,
9642 tree_cons (NULL_TREE
, pushort_type_node
,
9643 tree_cons (NULL_TREE
, integer_type_node
,
9646 tree v2si_ftype_signed_char
9647 = build_function_type (opaque_V2SI_type_node
,
9648 tree_cons (NULL_TREE
, signed_char_type_node
,
9651 /* The initialization of the simple binary and unary builtins is
9652 done in rs6000_common_init_builtins, but we have to enable the
9653 mask bits here manually because we have run out of `target_flags'
9654 bits. We really need to redesign this mask business. */
9656 enable_mask_for_builtins ((struct builtin_description
*) bdesc_2arg
,
9657 ARRAY_SIZE (bdesc_2arg
),
9660 enable_mask_for_builtins ((struct builtin_description
*) bdesc_1arg
,
9661 ARRAY_SIZE (bdesc_1arg
),
9663 SPE_BUILTIN_EVSUBFUSIAAW
);
9664 enable_mask_for_builtins ((struct builtin_description
*) bdesc_spe_predicates
,
9665 ARRAY_SIZE (bdesc_spe_predicates
),
9666 SPE_BUILTIN_EVCMPEQ
,
9667 SPE_BUILTIN_EVFSTSTLT
);
9668 enable_mask_for_builtins ((struct builtin_description
*) bdesc_spe_evsel
,
9669 ARRAY_SIZE (bdesc_spe_evsel
),
9670 SPE_BUILTIN_EVSEL_CMPGTS
,
9671 SPE_BUILTIN_EVSEL_FSTSTEQ
);
9673 (*lang_hooks
.decls
.pushdecl
)
9674 (build_decl (TYPE_DECL
, get_identifier ("__ev64_opaque__"),
9675 opaque_V2SI_type_node
));
9677 /* Initialize irregular SPE builtins. */
9679 def_builtin (target_flags
, "__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
9680 def_builtin (target_flags
, "__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
9681 def_builtin (target_flags
, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
9682 def_builtin (target_flags
, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
9683 def_builtin (target_flags
, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
9684 def_builtin (target_flags
, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
9685 def_builtin (target_flags
, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
9686 def_builtin (target_flags
, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
9687 def_builtin (target_flags
, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
9688 def_builtin (target_flags
, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
9689 def_builtin (target_flags
, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
9690 def_builtin (target_flags
, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
9691 def_builtin (target_flags
, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
9692 def_builtin (target_flags
, "__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
9693 def_builtin (target_flags
, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
9694 def_builtin (target_flags
, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
9695 def_builtin (target_flags
, "__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
9696 def_builtin (target_flags
, "__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
9699 def_builtin (target_flags
, "__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
9700 def_builtin (target_flags
, "__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
9701 def_builtin (target_flags
, "__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
9702 def_builtin (target_flags
, "__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
9703 def_builtin (target_flags
, "__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
9704 def_builtin (target_flags
, "__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
9705 def_builtin (target_flags
, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
9706 def_builtin (target_flags
, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
9707 def_builtin (target_flags
, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
9708 def_builtin (target_flags
, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
9709 def_builtin (target_flags
, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
9710 def_builtin (target_flags
, "__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
9711 def_builtin (target_flags
, "__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
9712 def_builtin (target_flags
, "__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
9713 def_builtin (target_flags
, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
9714 def_builtin (target_flags
, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
9715 def_builtin (target_flags
, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
9716 def_builtin (target_flags
, "__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
9717 def_builtin (target_flags
, "__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
9718 def_builtin (target_flags
, "__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
9719 def_builtin (target_flags
, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
9720 def_builtin (target_flags
, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
9723 d
= (struct builtin_description
*) bdesc_spe_predicates
;
9724 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
9728 switch (insn_data
[d
->icode
].operand
[1].mode
)
9731 type
= int_ftype_int_v2si_v2si
;
9734 type
= int_ftype_int_v2sf_v2sf
;
9740 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9743 /* Evsel predicates. */
9744 d
= (struct builtin_description
*) bdesc_spe_evsel
;
9745 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
9749 switch (insn_data
[d
->icode
].operand
[1].mode
)
9752 type
= v2si_ftype_4_v2si
;
9755 type
= v2sf_ftype_4_v2sf
;
9761 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9766 paired_init_builtins (void)
9768 const struct builtin_description
*d
;
9770 tree endlink
= void_list_node
;
9772 tree int_ftype_int_v2sf_v2sf
9773 = build_function_type
9775 tree_cons (NULL_TREE
, integer_type_node
,
9776 tree_cons (NULL_TREE
, V2SF_type_node
,
9777 tree_cons (NULL_TREE
, V2SF_type_node
,
9779 tree pcfloat_type_node
=
9780 build_pointer_type (build_qualified_type
9781 (float_type_node
, TYPE_QUAL_CONST
));
9783 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
9784 long_integer_type_node
,
9787 tree void_ftype_v2sf_long_pcfloat
=
9788 build_function_type_list (void_type_node
,
9790 long_integer_type_node
,
9795 def_builtin (0, "__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
9799 def_builtin (0, "__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
9800 PAIRED_BUILTIN_STX
);
9803 d
= bdesc_paired_preds
;
9804 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
9808 switch (insn_data
[d
->icode
].operand
[1].mode
)
9811 type
= int_ftype_int_v2sf_v2sf
;
9817 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9822 altivec_init_builtins (void)
9824 const struct builtin_description
*d
;
9825 const struct builtin_description_predicates
*dp
;
9829 tree pfloat_type_node
= build_pointer_type (float_type_node
);
9830 tree pint_type_node
= build_pointer_type (integer_type_node
);
9831 tree pshort_type_node
= build_pointer_type (short_integer_type_node
);
9832 tree pchar_type_node
= build_pointer_type (char_type_node
);
9834 tree pvoid_type_node
= build_pointer_type (void_type_node
);
9836 tree pcfloat_type_node
= build_pointer_type (build_qualified_type (float_type_node
, TYPE_QUAL_CONST
));
9837 tree pcint_type_node
= build_pointer_type (build_qualified_type (integer_type_node
, TYPE_QUAL_CONST
));
9838 tree pcshort_type_node
= build_pointer_type (build_qualified_type (short_integer_type_node
, TYPE_QUAL_CONST
));
9839 tree pcchar_type_node
= build_pointer_type (build_qualified_type (char_type_node
, TYPE_QUAL_CONST
));
9841 tree pcvoid_type_node
= build_pointer_type (build_qualified_type (void_type_node
, TYPE_QUAL_CONST
));
9843 tree int_ftype_opaque
9844 = build_function_type_list (integer_type_node
,
9845 opaque_V4SI_type_node
, NULL_TREE
);
9846 tree opaque_ftype_opaque
9847 = build_function_type (integer_type_node
,
9849 tree opaque_ftype_opaque_int
9850 = build_function_type_list (opaque_V4SI_type_node
,
9851 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
9852 tree opaque_ftype_opaque_opaque_int
9853 = build_function_type_list (opaque_V4SI_type_node
,
9854 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
9855 integer_type_node
, NULL_TREE
);
9856 tree int_ftype_int_opaque_opaque
9857 = build_function_type_list (integer_type_node
,
9858 integer_type_node
, opaque_V4SI_type_node
,
9859 opaque_V4SI_type_node
, NULL_TREE
);
9860 tree int_ftype_int_v4si_v4si
9861 = build_function_type_list (integer_type_node
,
9862 integer_type_node
, V4SI_type_node
,
9863 V4SI_type_node
, NULL_TREE
);
9864 tree v4sf_ftype_pcfloat
9865 = build_function_type_list (V4SF_type_node
, pcfloat_type_node
, NULL_TREE
);
9866 tree void_ftype_pfloat_v4sf
9867 = build_function_type_list (void_type_node
,
9868 pfloat_type_node
, V4SF_type_node
, NULL_TREE
);
9869 tree v4si_ftype_pcint
9870 = build_function_type_list (V4SI_type_node
, pcint_type_node
, NULL_TREE
);
9871 tree void_ftype_pint_v4si
9872 = build_function_type_list (void_type_node
,
9873 pint_type_node
, V4SI_type_node
, NULL_TREE
);
9874 tree v8hi_ftype_pcshort
9875 = build_function_type_list (V8HI_type_node
, pcshort_type_node
, NULL_TREE
);
9876 tree void_ftype_pshort_v8hi
9877 = build_function_type_list (void_type_node
,
9878 pshort_type_node
, V8HI_type_node
, NULL_TREE
);
9879 tree v16qi_ftype_pcchar
9880 = build_function_type_list (V16QI_type_node
, pcchar_type_node
, NULL_TREE
);
9881 tree void_ftype_pchar_v16qi
9882 = build_function_type_list (void_type_node
,
9883 pchar_type_node
, V16QI_type_node
, NULL_TREE
);
9884 tree void_ftype_v4si
9885 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
9886 tree v8hi_ftype_void
9887 = build_function_type (V8HI_type_node
, void_list_node
);
9888 tree void_ftype_void
9889 = build_function_type (void_type_node
, void_list_node
);
9891 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
9893 tree opaque_ftype_long_pcvoid
9894 = build_function_type_list (opaque_V4SI_type_node
,
9895 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
9896 tree v16qi_ftype_long_pcvoid
9897 = build_function_type_list (V16QI_type_node
,
9898 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
9899 tree v8hi_ftype_long_pcvoid
9900 = build_function_type_list (V8HI_type_node
,
9901 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
9902 tree v4si_ftype_long_pcvoid
9903 = build_function_type_list (V4SI_type_node
,
9904 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
9906 tree void_ftype_opaque_long_pvoid
9907 = build_function_type_list (void_type_node
,
9908 opaque_V4SI_type_node
, long_integer_type_node
,
9909 pvoid_type_node
, NULL_TREE
);
9910 tree void_ftype_v4si_long_pvoid
9911 = build_function_type_list (void_type_node
,
9912 V4SI_type_node
, long_integer_type_node
,
9913 pvoid_type_node
, NULL_TREE
);
9914 tree void_ftype_v16qi_long_pvoid
9915 = build_function_type_list (void_type_node
,
9916 V16QI_type_node
, long_integer_type_node
,
9917 pvoid_type_node
, NULL_TREE
);
9918 tree void_ftype_v8hi_long_pvoid
9919 = build_function_type_list (void_type_node
,
9920 V8HI_type_node
, long_integer_type_node
,
9921 pvoid_type_node
, NULL_TREE
);
9922 tree int_ftype_int_v8hi_v8hi
9923 = build_function_type_list (integer_type_node
,
9924 integer_type_node
, V8HI_type_node
,
9925 V8HI_type_node
, NULL_TREE
);
9926 tree int_ftype_int_v16qi_v16qi
9927 = build_function_type_list (integer_type_node
,
9928 integer_type_node
, V16QI_type_node
,
9929 V16QI_type_node
, NULL_TREE
);
9930 tree int_ftype_int_v4sf_v4sf
9931 = build_function_type_list (integer_type_node
,
9932 integer_type_node
, V4SF_type_node
,
9933 V4SF_type_node
, NULL_TREE
);
9934 tree v4si_ftype_v4si
9935 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
9936 tree v8hi_ftype_v8hi
9937 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
9938 tree v16qi_ftype_v16qi
9939 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
9940 tree v4sf_ftype_v4sf
9941 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
9942 tree void_ftype_pcvoid_int_int
9943 = build_function_type_list (void_type_node
,
9944 pcvoid_type_node
, integer_type_node
,
9945 integer_type_node
, NULL_TREE
);
9947 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat
,
9948 ALTIVEC_BUILTIN_LD_INTERNAL_4sf
);
9949 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf
,
9950 ALTIVEC_BUILTIN_ST_INTERNAL_4sf
);
9951 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint
,
9952 ALTIVEC_BUILTIN_LD_INTERNAL_4si
);
9953 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si
,
9954 ALTIVEC_BUILTIN_ST_INTERNAL_4si
);
9955 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort
,
9956 ALTIVEC_BUILTIN_LD_INTERNAL_8hi
);
9957 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi
,
9958 ALTIVEC_BUILTIN_ST_INTERNAL_8hi
);
9959 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar
,
9960 ALTIVEC_BUILTIN_LD_INTERNAL_16qi
);
9961 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi
,
9962 ALTIVEC_BUILTIN_ST_INTERNAL_16qi
);
9963 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
9964 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
9965 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
9966 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
9967 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
9968 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
9969 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
9970 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
9971 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
9972 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
9973 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
9974 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
9975 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
9976 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
9977 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
9978 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
9979 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
9980 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
9981 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
9982 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
9983 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
9984 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
9985 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
9986 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
9987 def_builtin (MASK_ALTIVEC
, "__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
9988 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
9989 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
9990 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
9991 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
9992 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
9994 if (rs6000_cpu
== PROCESSOR_CELL
)
9996 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
9997 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
9998 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
9999 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
10001 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
10002 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
10003 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
10004 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
10006 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
10007 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
10008 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
10009 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
10011 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
10012 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
10013 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
10014 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
10016 def_builtin (MASK_ALTIVEC
, "__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
10017 def_builtin (MASK_ALTIVEC
, "__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
10018 def_builtin (MASK_ALTIVEC
, "__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
10020 def_builtin (MASK_ALTIVEC
, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
10021 def_builtin (MASK_ALTIVEC
, "__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
10022 def_builtin (MASK_ALTIVEC
, "__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
10023 def_builtin (MASK_ALTIVEC
, "__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
10024 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
10025 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
10026 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
10027 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
10028 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
10029 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
10030 def_builtin (MASK_ALTIVEC
, "__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
10031 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
10033 /* Add the DST variants. */
10035 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
10036 def_builtin (d
->mask
, d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
10038 /* Initialize the predicates. */
10039 dp
= bdesc_altivec_preds
;
10040 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, dp
++)
10042 enum machine_mode mode1
;
10044 bool is_overloaded
= dp
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10045 && dp
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
10050 mode1
= insn_data
[dp
->icode
].operand
[1].mode
;
10055 type
= int_ftype_int_opaque_opaque
;
10058 type
= int_ftype_int_v4si_v4si
;
10061 type
= int_ftype_int_v8hi_v8hi
;
10064 type
= int_ftype_int_v16qi_v16qi
;
10067 type
= int_ftype_int_v4sf_v4sf
;
10070 gcc_unreachable ();
10073 def_builtin (dp
->mask
, dp
->name
, type
, dp
->code
);
10076 /* Initialize the abs* operators. */
10078 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
10080 enum machine_mode mode0
;
10083 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
10088 type
= v4si_ftype_v4si
;
10091 type
= v8hi_ftype_v8hi
;
10094 type
= v16qi_ftype_v16qi
;
10097 type
= v4sf_ftype_v4sf
;
10100 gcc_unreachable ();
10103 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
10106 if (TARGET_ALTIVEC
)
10110 /* Initialize target builtin that implements
10111 targetm.vectorize.builtin_mask_for_load. */
10113 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
10114 v16qi_ftype_long_pcvoid
,
10115 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
10116 BUILT_IN_MD
, NULL
, NULL_TREE
);
10117 TREE_READONLY (decl
) = 1;
10118 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
10119 altivec_builtin_mask_for_load
= decl
;
10122 /* Access to the vec_init patterns. */
10123 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
10124 integer_type_node
, integer_type_node
,
10125 integer_type_node
, NULL_TREE
);
10126 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v4si", ftype
,
10127 ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
10129 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
10130 short_integer_type_node
,
10131 short_integer_type_node
,
10132 short_integer_type_node
,
10133 short_integer_type_node
,
10134 short_integer_type_node
,
10135 short_integer_type_node
,
10136 short_integer_type_node
, NULL_TREE
);
10137 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v8hi", ftype
,
10138 ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
10140 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
10141 char_type_node
, char_type_node
,
10142 char_type_node
, char_type_node
,
10143 char_type_node
, char_type_node
,
10144 char_type_node
, char_type_node
,
10145 char_type_node
, char_type_node
,
10146 char_type_node
, char_type_node
,
10147 char_type_node
, char_type_node
,
10148 char_type_node
, NULL_TREE
);
10149 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v16qi", ftype
,
10150 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
10152 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
10153 float_type_node
, float_type_node
,
10154 float_type_node
, NULL_TREE
);
10155 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v4sf", ftype
,
10156 ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
10158 /* Access to the vec_set patterns. */
10159 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
10161 integer_type_node
, NULL_TREE
);
10162 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v4si", ftype
,
10163 ALTIVEC_BUILTIN_VEC_SET_V4SI
);
10165 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
10167 integer_type_node
, NULL_TREE
);
10168 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v8hi", ftype
,
10169 ALTIVEC_BUILTIN_VEC_SET_V8HI
);
10171 ftype
= build_function_type_list (V8HI_type_node
, V16QI_type_node
,
10173 integer_type_node
, NULL_TREE
);
10174 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v16qi", ftype
,
10175 ALTIVEC_BUILTIN_VEC_SET_V16QI
);
10177 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
10179 integer_type_node
, NULL_TREE
);
10180 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v4sf", ftype
,
10181 ALTIVEC_BUILTIN_VEC_SET_V4SF
);
10183 /* Access to the vec_extract patterns. */
10184 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
10185 integer_type_node
, NULL_TREE
);
10186 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v4si", ftype
,
10187 ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
10189 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
10190 integer_type_node
, NULL_TREE
);
10191 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v8hi", ftype
,
10192 ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
10194 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
10195 integer_type_node
, NULL_TREE
);
10196 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v16qi", ftype
,
10197 ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
10199 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
10200 integer_type_node
, NULL_TREE
);
10201 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v4sf", ftype
,
10202 ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
10206 rs6000_common_init_builtins (void)
10208 const struct builtin_description
*d
;
10211 tree v2sf_ftype_v2sf_v2sf_v2sf
10212 = build_function_type_list (V2SF_type_node
,
10213 V2SF_type_node
, V2SF_type_node
,
10214 V2SF_type_node
, NULL_TREE
);
10216 tree v4sf_ftype_v4sf_v4sf_v16qi
10217 = build_function_type_list (V4SF_type_node
,
10218 V4SF_type_node
, V4SF_type_node
,
10219 V16QI_type_node
, NULL_TREE
);
10220 tree v4si_ftype_v4si_v4si_v16qi
10221 = build_function_type_list (V4SI_type_node
,
10222 V4SI_type_node
, V4SI_type_node
,
10223 V16QI_type_node
, NULL_TREE
);
10224 tree v8hi_ftype_v8hi_v8hi_v16qi
10225 = build_function_type_list (V8HI_type_node
,
10226 V8HI_type_node
, V8HI_type_node
,
10227 V16QI_type_node
, NULL_TREE
);
10228 tree v16qi_ftype_v16qi_v16qi_v16qi
10229 = build_function_type_list (V16QI_type_node
,
10230 V16QI_type_node
, V16QI_type_node
,
10231 V16QI_type_node
, NULL_TREE
);
10232 tree v4si_ftype_int
10233 = build_function_type_list (V4SI_type_node
, integer_type_node
, NULL_TREE
);
10234 tree v8hi_ftype_int
10235 = build_function_type_list (V8HI_type_node
, integer_type_node
, NULL_TREE
);
10236 tree v16qi_ftype_int
10237 = build_function_type_list (V16QI_type_node
, integer_type_node
, NULL_TREE
);
10238 tree v8hi_ftype_v16qi
10239 = build_function_type_list (V8HI_type_node
, V16QI_type_node
, NULL_TREE
);
10240 tree v4sf_ftype_v4sf
10241 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
10243 tree v2si_ftype_v2si_v2si
10244 = build_function_type_list (opaque_V2SI_type_node
,
10245 opaque_V2SI_type_node
,
10246 opaque_V2SI_type_node
, NULL_TREE
);
10248 tree v2sf_ftype_v2sf_v2sf_spe
10249 = build_function_type_list (opaque_V2SF_type_node
,
10250 opaque_V2SF_type_node
,
10251 opaque_V2SF_type_node
, NULL_TREE
);
10253 tree v2sf_ftype_v2sf_v2sf
10254 = build_function_type_list (V2SF_type_node
,
10256 V2SF_type_node
, NULL_TREE
);
10259 tree v2si_ftype_int_int
10260 = build_function_type_list (opaque_V2SI_type_node
,
10261 integer_type_node
, integer_type_node
,
10264 tree opaque_ftype_opaque
10265 = build_function_type_list (opaque_V4SI_type_node
,
10266 opaque_V4SI_type_node
, NULL_TREE
);
10268 tree v2si_ftype_v2si
10269 = build_function_type_list (opaque_V2SI_type_node
,
10270 opaque_V2SI_type_node
, NULL_TREE
);
10272 tree v2sf_ftype_v2sf_spe
10273 = build_function_type_list (opaque_V2SF_type_node
,
10274 opaque_V2SF_type_node
, NULL_TREE
);
10276 tree v2sf_ftype_v2sf
10277 = build_function_type_list (V2SF_type_node
,
10278 V2SF_type_node
, NULL_TREE
);
10280 tree v2sf_ftype_v2si
10281 = build_function_type_list (opaque_V2SF_type_node
,
10282 opaque_V2SI_type_node
, NULL_TREE
);
10284 tree v2si_ftype_v2sf
10285 = build_function_type_list (opaque_V2SI_type_node
,
10286 opaque_V2SF_type_node
, NULL_TREE
);
10288 tree v2si_ftype_v2si_char
10289 = build_function_type_list (opaque_V2SI_type_node
,
10290 opaque_V2SI_type_node
,
10291 char_type_node
, NULL_TREE
);
10293 tree v2si_ftype_int_char
10294 = build_function_type_list (opaque_V2SI_type_node
,
10295 integer_type_node
, char_type_node
, NULL_TREE
);
10297 tree v2si_ftype_char
10298 = build_function_type_list (opaque_V2SI_type_node
,
10299 char_type_node
, NULL_TREE
);
10301 tree int_ftype_int_int
10302 = build_function_type_list (integer_type_node
,
10303 integer_type_node
, integer_type_node
,
10306 tree opaque_ftype_opaque_opaque
10307 = build_function_type_list (opaque_V4SI_type_node
,
10308 opaque_V4SI_type_node
, opaque_V4SI_type_node
, NULL_TREE
);
10309 tree v4si_ftype_v4si_v4si
10310 = build_function_type_list (V4SI_type_node
,
10311 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
10312 tree v4sf_ftype_v4si_int
10313 = build_function_type_list (V4SF_type_node
,
10314 V4SI_type_node
, integer_type_node
, NULL_TREE
);
10315 tree v4si_ftype_v4sf_int
10316 = build_function_type_list (V4SI_type_node
,
10317 V4SF_type_node
, integer_type_node
, NULL_TREE
);
10318 tree v4si_ftype_v4si_int
10319 = build_function_type_list (V4SI_type_node
,
10320 V4SI_type_node
, integer_type_node
, NULL_TREE
);
10321 tree v8hi_ftype_v8hi_int
10322 = build_function_type_list (V8HI_type_node
,
10323 V8HI_type_node
, integer_type_node
, NULL_TREE
);
10324 tree v16qi_ftype_v16qi_int
10325 = build_function_type_list (V16QI_type_node
,
10326 V16QI_type_node
, integer_type_node
, NULL_TREE
);
10327 tree v16qi_ftype_v16qi_v16qi_int
10328 = build_function_type_list (V16QI_type_node
,
10329 V16QI_type_node
, V16QI_type_node
,
10330 integer_type_node
, NULL_TREE
);
10331 tree v8hi_ftype_v8hi_v8hi_int
10332 = build_function_type_list (V8HI_type_node
,
10333 V8HI_type_node
, V8HI_type_node
,
10334 integer_type_node
, NULL_TREE
);
10335 tree v4si_ftype_v4si_v4si_int
10336 = build_function_type_list (V4SI_type_node
,
10337 V4SI_type_node
, V4SI_type_node
,
10338 integer_type_node
, NULL_TREE
);
10339 tree v4sf_ftype_v4sf_v4sf_int
10340 = build_function_type_list (V4SF_type_node
,
10341 V4SF_type_node
, V4SF_type_node
,
10342 integer_type_node
, NULL_TREE
);
10343 tree v4sf_ftype_v4sf_v4sf
10344 = build_function_type_list (V4SF_type_node
,
10345 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
10346 tree opaque_ftype_opaque_opaque_opaque
10347 = build_function_type_list (opaque_V4SI_type_node
,
10348 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
10349 opaque_V4SI_type_node
, NULL_TREE
);
10350 tree v4sf_ftype_v4sf_v4sf_v4si
10351 = build_function_type_list (V4SF_type_node
,
10352 V4SF_type_node
, V4SF_type_node
,
10353 V4SI_type_node
, NULL_TREE
);
10354 tree v4sf_ftype_v4sf_v4sf_v4sf
10355 = build_function_type_list (V4SF_type_node
,
10356 V4SF_type_node
, V4SF_type_node
,
10357 V4SF_type_node
, NULL_TREE
);
10358 tree v4si_ftype_v4si_v4si_v4si
10359 = build_function_type_list (V4SI_type_node
,
10360 V4SI_type_node
, V4SI_type_node
,
10361 V4SI_type_node
, NULL_TREE
);
10362 tree v8hi_ftype_v8hi_v8hi
10363 = build_function_type_list (V8HI_type_node
,
10364 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
10365 tree v8hi_ftype_v8hi_v8hi_v8hi
10366 = build_function_type_list (V8HI_type_node
,
10367 V8HI_type_node
, V8HI_type_node
,
10368 V8HI_type_node
, NULL_TREE
);
10369 tree v4si_ftype_v8hi_v8hi_v4si
10370 = build_function_type_list (V4SI_type_node
,
10371 V8HI_type_node
, V8HI_type_node
,
10372 V4SI_type_node
, NULL_TREE
);
10373 tree v4si_ftype_v16qi_v16qi_v4si
10374 = build_function_type_list (V4SI_type_node
,
10375 V16QI_type_node
, V16QI_type_node
,
10376 V4SI_type_node
, NULL_TREE
);
10377 tree v16qi_ftype_v16qi_v16qi
10378 = build_function_type_list (V16QI_type_node
,
10379 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
10380 tree v4si_ftype_v4sf_v4sf
10381 = build_function_type_list (V4SI_type_node
,
10382 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
10383 tree v8hi_ftype_v16qi_v16qi
10384 = build_function_type_list (V8HI_type_node
,
10385 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
10386 tree v4si_ftype_v8hi_v8hi
10387 = build_function_type_list (V4SI_type_node
,
10388 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
10389 tree v8hi_ftype_v4si_v4si
10390 = build_function_type_list (V8HI_type_node
,
10391 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
10392 tree v16qi_ftype_v8hi_v8hi
10393 = build_function_type_list (V16QI_type_node
,
10394 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
10395 tree v4si_ftype_v16qi_v4si
10396 = build_function_type_list (V4SI_type_node
,
10397 V16QI_type_node
, V4SI_type_node
, NULL_TREE
);
10398 tree v4si_ftype_v16qi_v16qi
10399 = build_function_type_list (V4SI_type_node
,
10400 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
10401 tree v4si_ftype_v8hi_v4si
10402 = build_function_type_list (V4SI_type_node
,
10403 V8HI_type_node
, V4SI_type_node
, NULL_TREE
);
10404 tree v4si_ftype_v8hi
10405 = build_function_type_list (V4SI_type_node
, V8HI_type_node
, NULL_TREE
);
10406 tree int_ftype_v4si_v4si
10407 = build_function_type_list (integer_type_node
,
10408 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
10409 tree int_ftype_v4sf_v4sf
10410 = build_function_type_list (integer_type_node
,
10411 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
10412 tree int_ftype_v16qi_v16qi
10413 = build_function_type_list (integer_type_node
,
10414 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
10415 tree int_ftype_v8hi_v8hi
10416 = build_function_type_list (integer_type_node
,
10417 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
10419 /* Add the simple ternary operators. */
10421 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
10423 enum machine_mode mode0
, mode1
, mode2
, mode3
;
10425 bool is_overloaded
= d
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10426 && d
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
10437 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
10440 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
10441 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
10442 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
10443 mode3
= insn_data
[d
->icode
].operand
[3].mode
;
10446 /* When all four are of the same mode. */
10447 if (mode0
== mode1
&& mode1
== mode2
&& mode2
== mode3
)
10452 type
= opaque_ftype_opaque_opaque_opaque
;
10455 type
= v4si_ftype_v4si_v4si_v4si
;
10458 type
= v4sf_ftype_v4sf_v4sf_v4sf
;
10461 type
= v8hi_ftype_v8hi_v8hi_v8hi
;
10464 type
= v16qi_ftype_v16qi_v16qi_v16qi
;
10467 type
= v2sf_ftype_v2sf_v2sf_v2sf
;
10470 gcc_unreachable ();
10473 else if (mode0
== mode1
&& mode1
== mode2
&& mode3
== V16QImode
)
10478 type
= v4si_ftype_v4si_v4si_v16qi
;
10481 type
= v4sf_ftype_v4sf_v4sf_v16qi
;
10484 type
= v8hi_ftype_v8hi_v8hi_v16qi
;
10487 type
= v16qi_ftype_v16qi_v16qi_v16qi
;
10490 gcc_unreachable ();
10493 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V16QImode
10494 && mode3
== V4SImode
)
10495 type
= v4si_ftype_v16qi_v16qi_v4si
;
10496 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V8HImode
10497 && mode3
== V4SImode
)
10498 type
= v4si_ftype_v8hi_v8hi_v4si
;
10499 else if (mode0
== V4SFmode
&& mode1
== V4SFmode
&& mode2
== V4SFmode
10500 && mode3
== V4SImode
)
10501 type
= v4sf_ftype_v4sf_v4sf_v4si
;
10503 /* vchar, vchar, vchar, 4-bit literal. */
10504 else if (mode0
== V16QImode
&& mode1
== mode0
&& mode2
== mode0
10505 && mode3
== QImode
)
10506 type
= v16qi_ftype_v16qi_v16qi_int
;
10508 /* vshort, vshort, vshort, 4-bit literal. */
10509 else if (mode0
== V8HImode
&& mode1
== mode0
&& mode2
== mode0
10510 && mode3
== QImode
)
10511 type
= v8hi_ftype_v8hi_v8hi_int
;
10513 /* vint, vint, vint, 4-bit literal. */
10514 else if (mode0
== V4SImode
&& mode1
== mode0
&& mode2
== mode0
10515 && mode3
== QImode
)
10516 type
= v4si_ftype_v4si_v4si_int
;
10518 /* vfloat, vfloat, vfloat, 4-bit literal. */
10519 else if (mode0
== V4SFmode
&& mode1
== mode0
&& mode2
== mode0
10520 && mode3
== QImode
)
10521 type
= v4sf_ftype_v4sf_v4sf_int
;
10524 gcc_unreachable ();
10526 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
10529 /* Add the simple binary operators. */
10530 d
= (struct builtin_description
*) bdesc_2arg
;
10531 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
10533 enum machine_mode mode0
, mode1
, mode2
;
10535 bool is_overloaded
= d
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10536 && d
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
10546 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
10549 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
10550 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
10551 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
10554 /* When all three operands are of the same mode. */
10555 if (mode0
== mode1
&& mode1
== mode2
)
10560 type
= opaque_ftype_opaque_opaque
;
10563 type
= v4sf_ftype_v4sf_v4sf
;
10566 type
= v4si_ftype_v4si_v4si
;
10569 type
= v16qi_ftype_v16qi_v16qi
;
10572 type
= v8hi_ftype_v8hi_v8hi
;
10575 type
= v2si_ftype_v2si_v2si
;
10578 if (TARGET_PAIRED_FLOAT
)
10579 type
= v2sf_ftype_v2sf_v2sf
;
10581 type
= v2sf_ftype_v2sf_v2sf_spe
;
10584 type
= int_ftype_int_int
;
10587 gcc_unreachable ();
10591 /* A few other combos we really don't want to do manually. */
10593 /* vint, vfloat, vfloat. */
10594 else if (mode0
== V4SImode
&& mode1
== V4SFmode
&& mode2
== V4SFmode
)
10595 type
= v4si_ftype_v4sf_v4sf
;
10597 /* vshort, vchar, vchar. */
10598 else if (mode0
== V8HImode
&& mode1
== V16QImode
&& mode2
== V16QImode
)
10599 type
= v8hi_ftype_v16qi_v16qi
;
10601 /* vint, vshort, vshort. */
10602 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V8HImode
)
10603 type
= v4si_ftype_v8hi_v8hi
;
10605 /* vshort, vint, vint. */
10606 else if (mode0
== V8HImode
&& mode1
== V4SImode
&& mode2
== V4SImode
)
10607 type
= v8hi_ftype_v4si_v4si
;
10609 /* vchar, vshort, vshort. */
10610 else if (mode0
== V16QImode
&& mode1
== V8HImode
&& mode2
== V8HImode
)
10611 type
= v16qi_ftype_v8hi_v8hi
;
10613 /* vint, vchar, vint. */
10614 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V4SImode
)
10615 type
= v4si_ftype_v16qi_v4si
;
10617 /* vint, vchar, vchar. */
10618 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V16QImode
)
10619 type
= v4si_ftype_v16qi_v16qi
;
10621 /* vint, vshort, vint. */
10622 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V4SImode
)
10623 type
= v4si_ftype_v8hi_v4si
;
10625 /* vint, vint, 5-bit literal. */
10626 else if (mode0
== V4SImode
&& mode1
== V4SImode
&& mode2
== QImode
)
10627 type
= v4si_ftype_v4si_int
;
10629 /* vshort, vshort, 5-bit literal. */
10630 else if (mode0
== V8HImode
&& mode1
== V8HImode
&& mode2
== QImode
)
10631 type
= v8hi_ftype_v8hi_int
;
10633 /* vchar, vchar, 5-bit literal. */
10634 else if (mode0
== V16QImode
&& mode1
== V16QImode
&& mode2
== QImode
)
10635 type
= v16qi_ftype_v16qi_int
;
10637 /* vfloat, vint, 5-bit literal. */
10638 else if (mode0
== V4SFmode
&& mode1
== V4SImode
&& mode2
== QImode
)
10639 type
= v4sf_ftype_v4si_int
;
10641 /* vint, vfloat, 5-bit literal. */
10642 else if (mode0
== V4SImode
&& mode1
== V4SFmode
&& mode2
== QImode
)
10643 type
= v4si_ftype_v4sf_int
;
10645 else if (mode0
== V2SImode
&& mode1
== SImode
&& mode2
== SImode
)
10646 type
= v2si_ftype_int_int
;
10648 else if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
10649 type
= v2si_ftype_v2si_char
;
10651 else if (mode0
== V2SImode
&& mode1
== SImode
&& mode2
== QImode
)
10652 type
= v2si_ftype_int_char
;
10657 gcc_assert (mode0
== SImode
);
10661 type
= int_ftype_v4si_v4si
;
10664 type
= int_ftype_v4sf_v4sf
;
10667 type
= int_ftype_v16qi_v16qi
;
10670 type
= int_ftype_v8hi_v8hi
;
10673 gcc_unreachable ();
10677 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
10680 /* Add the simple unary operators. */
10681 d
= (struct builtin_description
*) bdesc_1arg
;
10682 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
10684 enum machine_mode mode0
, mode1
;
10686 bool is_overloaded
= d
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10687 && d
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
10696 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
10699 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
10700 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
10703 if (mode0
== V4SImode
&& mode1
== QImode
)
10704 type
= v4si_ftype_int
;
10705 else if (mode0
== V8HImode
&& mode1
== QImode
)
10706 type
= v8hi_ftype_int
;
10707 else if (mode0
== V16QImode
&& mode1
== QImode
)
10708 type
= v16qi_ftype_int
;
10709 else if (mode0
== VOIDmode
&& mode1
== VOIDmode
)
10710 type
= opaque_ftype_opaque
;
10711 else if (mode0
== V4SFmode
&& mode1
== V4SFmode
)
10712 type
= v4sf_ftype_v4sf
;
10713 else if (mode0
== V8HImode
&& mode1
== V16QImode
)
10714 type
= v8hi_ftype_v16qi
;
10715 else if (mode0
== V4SImode
&& mode1
== V8HImode
)
10716 type
= v4si_ftype_v8hi
;
10717 else if (mode0
== V2SImode
&& mode1
== V2SImode
)
10718 type
= v2si_ftype_v2si
;
10719 else if (mode0
== V2SFmode
&& mode1
== V2SFmode
)
10721 if (TARGET_PAIRED_FLOAT
)
10722 type
= v2sf_ftype_v2sf
;
10724 type
= v2sf_ftype_v2sf_spe
;
10726 else if (mode0
== V2SFmode
&& mode1
== V2SImode
)
10727 type
= v2sf_ftype_v2si
;
10728 else if (mode0
== V2SImode
&& mode1
== V2SFmode
)
10729 type
= v2si_ftype_v2sf
;
10730 else if (mode0
== V2SImode
&& mode1
== QImode
)
10731 type
= v2si_ftype_char
;
10733 gcc_unreachable ();
10735 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
10740 rs6000_init_libfuncs (void)
10742 if (DEFAULT_ABI
!= ABI_V4
&& TARGET_XCOFF
10743 && !TARGET_POWER2
&& !TARGET_POWERPC
)
10745 /* AIX library routines for float->int conversion. */
10746 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__itrunc");
10747 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__uitrunc");
10748 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_qitrunc");
10749 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_quitrunc");
10752 if (!TARGET_IEEEQUAD
)
10753 /* AIX/Darwin/64-bit Linux quad floating point routines. */
10754 if (!TARGET_XL_COMPAT
)
10756 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
10757 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
10758 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
10759 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
10761 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
10763 set_optab_libfunc (neg_optab
, TFmode
, "__gcc_qneg");
10764 set_optab_libfunc (eq_optab
, TFmode
, "__gcc_qeq");
10765 set_optab_libfunc (ne_optab
, TFmode
, "__gcc_qne");
10766 set_optab_libfunc (gt_optab
, TFmode
, "__gcc_qgt");
10767 set_optab_libfunc (ge_optab
, TFmode
, "__gcc_qge");
10768 set_optab_libfunc (lt_optab
, TFmode
, "__gcc_qlt");
10769 set_optab_libfunc (le_optab
, TFmode
, "__gcc_qle");
10771 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "__gcc_stoq");
10772 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "__gcc_dtoq");
10773 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "__gcc_qtos");
10774 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "__gcc_qtod");
10775 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "__gcc_qtoi");
10776 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "__gcc_qtou");
10777 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "__gcc_itoq");
10778 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "__gcc_utoq");
10781 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
10782 set_optab_libfunc (unord_optab
, TFmode
, "__gcc_qunord");
10786 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
10787 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
10788 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
10789 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
10793 /* 32-bit SVR4 quad floating point routines. */
10795 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
10796 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
10797 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
10798 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
10799 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
10800 if (TARGET_PPC_GPOPT
|| TARGET_POWER2
)
10801 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
10803 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
10804 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
10805 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
10806 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
10807 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
10808 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
10810 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
10811 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
10812 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
10813 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
10814 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
10815 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
10816 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
10817 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_q_utoq");
10822 /* Expand a block clear operation, and return 1 if successful. Return 0
10823 if we should let the compiler generate normal code.
10825 operands[0] is the destination
10826 operands[1] is the length
10827 operands[3] is the alignment */
10830 expand_block_clear (rtx operands
[])
10832 rtx orig_dest
= operands
[0];
10833 rtx bytes_rtx
= operands
[1];
10834 rtx align_rtx
= operands
[3];
10835 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
10836 HOST_WIDE_INT align
;
10837 HOST_WIDE_INT bytes
;
10842 /* If this is not a fixed size move, just call memcpy */
10846 /* This must be a fixed size alignment */
10847 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
10848 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
10850 /* Anything to clear? */
10851 bytes
= INTVAL (bytes_rtx
);
10855 /* Use the builtin memset after a point, to avoid huge code bloat.
10856 When optimize_size, avoid any significant code bloat; calling
10857 memset is about 4 instructions, so allow for one instruction to
10858 load zero and three to do clearing. */
10859 if (TARGET_ALTIVEC
&& align
>= 128)
10861 else if (TARGET_POWERPC64
&& align
>= 32)
10863 else if (TARGET_SPE
&& align
>= 64)
10868 if (optimize_size
&& bytes
> 3 * clear_step
)
10870 if (! optimize_size
&& bytes
> 8 * clear_step
)
10873 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
10875 enum machine_mode mode
= BLKmode
;
10878 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
10883 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
10888 else if (bytes
>= 8 && TARGET_POWERPC64
10889 /* 64-bit loads and stores require word-aligned
10891 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
10896 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
10897 { /* move 4 bytes */
10901 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
10902 { /* move 2 bytes */
10906 else /* move 1 byte at a time */
10912 dest
= adjust_address (orig_dest
, mode
, offset
);
10914 emit_move_insn (dest
, CONST0_RTX (mode
));
10921 /* Expand a block move operation, and return 1 if successful. Return 0
10922 if we should let the compiler generate normal code.
10924 operands[0] is the destination
10925 operands[1] is the source
10926 operands[2] is the length
10927 operands[3] is the alignment */
10929 #define MAX_MOVE_REG 4
10932 expand_block_move (rtx operands
[])
10934 rtx orig_dest
= operands
[0];
10935 rtx orig_src
= operands
[1];
10936 rtx bytes_rtx
= operands
[2];
10937 rtx align_rtx
= operands
[3];
10938 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
10943 rtx stores
[MAX_MOVE_REG
];
10946 /* If this is not a fixed size move, just call memcpy */
10950 /* This must be a fixed size alignment */
10951 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
10952 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
10954 /* Anything to move? */
10955 bytes
= INTVAL (bytes_rtx
);
10959 /* store_one_arg depends on expand_block_move to handle at least the size of
10960 reg_parm_stack_space. */
10961 if (bytes
> (TARGET_POWERPC64
? 64 : 32))
10964 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
10967 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
10968 rtx (*mov
) (rtx
, rtx
);
10970 enum machine_mode mode
= BLKmode
;
10973 /* Altivec first, since it will be faster than a string move
10974 when it applies, and usually not significantly larger. */
10975 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
10979 gen_func
.mov
= gen_movv4si
;
10981 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
10985 gen_func
.mov
= gen_movv2si
;
10987 else if (TARGET_STRING
10988 && bytes
> 24 /* move up to 32 bytes at a time */
10994 && ! fixed_regs
[10]
10995 && ! fixed_regs
[11]
10996 && ! fixed_regs
[12])
10998 move_bytes
= (bytes
> 32) ? 32 : bytes
;
10999 gen_func
.movmemsi
= gen_movmemsi_8reg
;
11001 else if (TARGET_STRING
11002 && bytes
> 16 /* move up to 24 bytes at a time */
11008 && ! fixed_regs
[10])
11010 move_bytes
= (bytes
> 24) ? 24 : bytes
;
11011 gen_func
.movmemsi
= gen_movmemsi_6reg
;
11013 else if (TARGET_STRING
11014 && bytes
> 8 /* move up to 16 bytes at a time */
11018 && ! fixed_regs
[8])
11020 move_bytes
= (bytes
> 16) ? 16 : bytes
;
11021 gen_func
.movmemsi
= gen_movmemsi_4reg
;
11023 else if (bytes
>= 8 && TARGET_POWERPC64
11024 /* 64-bit loads and stores require word-aligned
11026 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
11030 gen_func
.mov
= gen_movdi
;
11032 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
11033 { /* move up to 8 bytes at a time */
11034 move_bytes
= (bytes
> 8) ? 8 : bytes
;
11035 gen_func
.movmemsi
= gen_movmemsi_2reg
;
11037 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
11038 { /* move 4 bytes */
11041 gen_func
.mov
= gen_movsi
;
11043 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
11044 { /* move 2 bytes */
11047 gen_func
.mov
= gen_movhi
;
11049 else if (TARGET_STRING
&& bytes
> 1)
11050 { /* move up to 4 bytes at a time */
11051 move_bytes
= (bytes
> 4) ? 4 : bytes
;
11052 gen_func
.movmemsi
= gen_movmemsi_1reg
;
11054 else /* move 1 byte at a time */
11058 gen_func
.mov
= gen_movqi
;
11061 src
= adjust_address (orig_src
, mode
, offset
);
11062 dest
= adjust_address (orig_dest
, mode
, offset
);
11064 if (mode
!= BLKmode
)
11066 rtx tmp_reg
= gen_reg_rtx (mode
);
11068 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
11069 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
11072 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
11075 for (i
= 0; i
< num_reg
; i
++)
11076 emit_insn (stores
[i
]);
11080 if (mode
== BLKmode
)
11082 /* Move the address into scratch registers. The movmemsi
11083 patterns require zero offset. */
11084 if (!REG_P (XEXP (src
, 0)))
11086 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
11087 src
= replace_equiv_address (src
, src_reg
);
11089 set_mem_size (src
, GEN_INT (move_bytes
));
11091 if (!REG_P (XEXP (dest
, 0)))
11093 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
11094 dest
= replace_equiv_address (dest
, dest_reg
);
11096 set_mem_size (dest
, GEN_INT (move_bytes
));
11098 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
11099 GEN_INT (move_bytes
& 31),
11108 /* Return a string to perform a load_multiple operation.
11109 operands[0] is the vector.
11110 operands[1] is the source address.
11111 operands[2] is the first destination register. */
11114 rs6000_output_load_multiple (rtx operands
[3])
11116 /* We have to handle the case where the pseudo used to contain the address
11117 is assigned to one of the output registers. */
11119 int words
= XVECLEN (operands
[0], 0);
11122 if (XVECLEN (operands
[0], 0) == 1)
11123 return "{l|lwz} %2,0(%1)";
11125 for (i
= 0; i
< words
; i
++)
11126 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
11127 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
11131 xop
[0] = GEN_INT (4 * (words
-1));
11132 xop
[1] = operands
[1];
11133 xop
[2] = operands
[2];
11134 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop
);
11139 xop
[0] = GEN_INT (4 * (words
-1));
11140 xop
[1] = operands
[1];
11141 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
11142 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop
);
11147 for (j
= 0; j
< words
; j
++)
11150 xop
[0] = GEN_INT (j
* 4);
11151 xop
[1] = operands
[1];
11152 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
11153 output_asm_insn ("{l|lwz} %2,%0(%1)", xop
);
11155 xop
[0] = GEN_INT (i
* 4);
11156 xop
[1] = operands
[1];
11157 output_asm_insn ("{l|lwz} %1,%0(%1)", xop
);
11162 return "{lsi|lswi} %2,%1,%N0";
11166 /* A validation routine: say whether CODE, a condition code, and MODE
11167 match. The other alternatives either don't make sense or should
11168 never be generated. */
11171 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
11173 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
11174 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
11175 && GET_MODE_CLASS (mode
) == MODE_CC
);
11177 /* These don't make sense. */
11178 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
11179 || mode
!= CCUNSmode
);
11181 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
11182 || mode
== CCUNSmode
);
11184 gcc_assert (mode
== CCFPmode
11185 || (code
!= ORDERED
&& code
!= UNORDERED
11186 && code
!= UNEQ
&& code
!= LTGT
11187 && code
!= UNGT
&& code
!= UNLT
11188 && code
!= UNGE
&& code
!= UNLE
));
11190 /* These should never be generated except for
11191 flag_finite_math_only. */
11192 gcc_assert (mode
!= CCFPmode
11193 || flag_finite_math_only
11194 || (code
!= LE
&& code
!= GE
11195 && code
!= UNEQ
&& code
!= LTGT
11196 && code
!= UNGT
&& code
!= UNLT
));
11198 /* These are invalid; the information is not there. */
11199 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
11203 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
11204 mask required to convert the result of a rotate insn into a shift
11205 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
11208 includes_lshift_p (rtx shiftop
, rtx andop
)
11210 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
11212 shift_mask
<<= INTVAL (shiftop
);
11214 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
11217 /* Similar, but for right shift. */
11220 includes_rshift_p (rtx shiftop
, rtx andop
)
11222 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
11224 shift_mask
>>= INTVAL (shiftop
);
11226 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
11229 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
11230 to perform a left shift. It must have exactly SHIFTOP least
11231 significant 0's, then one or more 1's, then zero or more 0's. */
11234 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
11236 if (GET_CODE (andop
) == CONST_INT
)
11238 HOST_WIDE_INT c
, lsb
, shift_mask
;
11240 c
= INTVAL (andop
);
11241 if (c
== 0 || c
== ~0)
11245 shift_mask
<<= INTVAL (shiftop
);
11247 /* Find the least significant one bit. */
11250 /* It must coincide with the LSB of the shift mask. */
11251 if (-lsb
!= shift_mask
)
11254 /* Invert to look for the next transition (if any). */
11257 /* Remove the low group of ones (originally low group of zeros). */
11260 /* Again find the lsb, and check we have all 1's above. */
11264 else if (GET_CODE (andop
) == CONST_DOUBLE
11265 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
11267 HOST_WIDE_INT low
, high
, lsb
;
11268 HOST_WIDE_INT shift_mask_low
, shift_mask_high
;
11270 low
= CONST_DOUBLE_LOW (andop
);
11271 if (HOST_BITS_PER_WIDE_INT
< 64)
11272 high
= CONST_DOUBLE_HIGH (andop
);
11274 if ((low
== 0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== 0))
11275 || (low
== ~0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0)))
11278 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
11280 shift_mask_high
= ~0;
11281 if (INTVAL (shiftop
) > 32)
11282 shift_mask_high
<<= INTVAL (shiftop
) - 32;
11284 lsb
= high
& -high
;
11286 if (-lsb
!= shift_mask_high
|| INTVAL (shiftop
) < 32)
11292 lsb
= high
& -high
;
11293 return high
== -lsb
;
11296 shift_mask_low
= ~0;
11297 shift_mask_low
<<= INTVAL (shiftop
);
11301 if (-lsb
!= shift_mask_low
)
11304 if (HOST_BITS_PER_WIDE_INT
< 64)
11309 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
11311 lsb
= high
& -high
;
11312 return high
== -lsb
;
11316 return low
== -lsb
&& (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0);
11322 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
11323 to perform a left shift. It must have SHIFTOP or more least
11324 significant 0's, with the remainder of the word 1's. */
11327 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
11329 if (GET_CODE (andop
) == CONST_INT
)
11331 HOST_WIDE_INT c
, lsb
, shift_mask
;
11334 shift_mask
<<= INTVAL (shiftop
);
11335 c
= INTVAL (andop
);
11337 /* Find the least significant one bit. */
11340 /* It must be covered by the shift mask.
11341 This test also rejects c == 0. */
11342 if ((lsb
& shift_mask
) == 0)
11345 /* Check we have all 1's above the transition, and reject all 1's. */
11346 return c
== -lsb
&& lsb
!= 1;
11348 else if (GET_CODE (andop
) == CONST_DOUBLE
11349 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
11351 HOST_WIDE_INT low
, lsb
, shift_mask_low
;
11353 low
= CONST_DOUBLE_LOW (andop
);
11355 if (HOST_BITS_PER_WIDE_INT
< 64)
11357 HOST_WIDE_INT high
, shift_mask_high
;
11359 high
= CONST_DOUBLE_HIGH (andop
);
11363 shift_mask_high
= ~0;
11364 if (INTVAL (shiftop
) > 32)
11365 shift_mask_high
<<= INTVAL (shiftop
) - 32;
11367 lsb
= high
& -high
;
11369 if ((lsb
& shift_mask_high
) == 0)
11372 return high
== -lsb
;
11378 shift_mask_low
= ~0;
11379 shift_mask_low
<<= INTVAL (shiftop
);
11383 if ((lsb
& shift_mask_low
) == 0)
11386 return low
== -lsb
&& lsb
!= 1;
11392 /* Return 1 if operands will generate a valid arguments to rlwimi
11393 instruction for insert with right shift in 64-bit mode. The mask may
11394 not start on the first bit or stop on the last bit because wrap-around
11395 effects of instruction do not correspond to semantics of RTL insn. */
11398 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
11400 if (INTVAL (startop
) > 32
11401 && INTVAL (startop
) < 64
11402 && INTVAL (sizeop
) > 1
11403 && INTVAL (sizeop
) + INTVAL (startop
) < 64
11404 && INTVAL (shiftop
) > 0
11405 && INTVAL (sizeop
) + INTVAL (shiftop
) < 32
11406 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
11412 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
11413 for lfq and stfq insns iff the registers are hard registers. */
11416 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
11418 /* We might have been passed a SUBREG. */
11419 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
11422 /* We might have been passed non floating point registers. */
11423 if (!FP_REGNO_P (REGNO (reg1
))
11424 || !FP_REGNO_P (REGNO (reg2
)))
11427 return (REGNO (reg1
) == REGNO (reg2
) - 1);
11430 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
11431 addr1 and addr2 must be in consecutive memory locations
11432 (addr2 == addr1 + 8). */
11435 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
11438 unsigned int reg1
, reg2
;
11439 int offset1
, offset2
;
11441 /* The mems cannot be volatile. */
11442 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
11445 addr1
= XEXP (mem1
, 0);
11446 addr2
= XEXP (mem2
, 0);
11448 /* Extract an offset (if used) from the first addr. */
11449 if (GET_CODE (addr1
) == PLUS
)
11451 /* If not a REG, return zero. */
11452 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
11456 reg1
= REGNO (XEXP (addr1
, 0));
11457 /* The offset must be constant! */
11458 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
11460 offset1
= INTVAL (XEXP (addr1
, 1));
11463 else if (GET_CODE (addr1
) != REG
)
11467 reg1
= REGNO (addr1
);
11468 /* This was a simple (mem (reg)) expression. Offset is 0. */
11472 /* And now for the second addr. */
11473 if (GET_CODE (addr2
) == PLUS
)
11475 /* If not a REG, return zero. */
11476 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
11480 reg2
= REGNO (XEXP (addr2
, 0));
11481 /* The offset must be constant. */
11482 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
11484 offset2
= INTVAL (XEXP (addr2
, 1));
11487 else if (GET_CODE (addr2
) != REG
)
11491 reg2
= REGNO (addr2
);
11492 /* This was a simple (mem (reg)) expression. Offset is 0. */
11496 /* Both of these must have the same base register. */
11500 /* The offset for the second addr must be 8 more than the first addr. */
11501 if (offset2
!= offset1
+ 8)
11504 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
11511 rs6000_secondary_memory_needed_rtx (enum machine_mode mode
)
11513 static bool eliminated
= false;
11514 if (mode
!= SDmode
)
11515 return assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
11518 rtx mem
= cfun
->machine
->sdmode_stack_slot
;
11519 gcc_assert (mem
!= NULL_RTX
);
11523 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
11524 cfun
->machine
->sdmode_stack_slot
= mem
;
11532 rs6000_check_sdmode (tree
*tp
, int *walk_subtrees
, void *data ATTRIBUTE_UNUSED
)
11534 /* Don't walk into types. */
11535 if (*tp
== NULL_TREE
|| *tp
== error_mark_node
|| TYPE_P (*tp
))
11537 *walk_subtrees
= 0;
11541 switch (TREE_CODE (*tp
))
11550 case ALIGN_INDIRECT_REF
:
11551 case MISALIGNED_INDIRECT_REF
:
11552 case VIEW_CONVERT_EXPR
:
11553 if (TYPE_MODE (TREE_TYPE (*tp
)) == SDmode
)
11564 /* Allocate a 64-bit stack slot to be used for copying SDmode
11565 values through if this function has any SDmode references. */
11568 rs6000_alloc_sdmode_stack_slot (void)
11572 gimple_stmt_iterator gsi
;
11574 gcc_assert (cfun
->machine
->sdmode_stack_slot
== NULL_RTX
);
11577 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
11579 tree ret
= walk_gimple_op (gsi_stmt (gsi
), rs6000_check_sdmode
, NULL
);
11582 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
11583 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
11589 /* Check for any SDmode parameters of the function. */
11590 for (t
= DECL_ARGUMENTS (cfun
->decl
); t
; t
= TREE_CHAIN (t
))
11592 if (TREE_TYPE (t
) == error_mark_node
)
11595 if (TYPE_MODE (TREE_TYPE (t
)) == SDmode
11596 || TYPE_MODE (DECL_ARG_TYPE (t
)) == SDmode
)
11598 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
11599 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
11607 rs6000_instantiate_decls (void)
11609 if (cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
11610 instantiate_decl_rtl (cfun
->machine
->sdmode_stack_slot
);
11613 /* Return the register class of a scratch register needed to copy IN into
11614 or out of a register in RCLASS in MODE. If it can be done directly,
11615 NO_REGS is returned. */
11618 rs6000_secondary_reload_class (enum reg_class rclass
,
11619 enum machine_mode mode ATTRIBUTE_UNUSED
,
11624 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
11626 && MACHOPIC_INDIRECT
11630 /* We cannot copy a symbolic operand directly into anything
11631 other than BASE_REGS for TARGET_ELF. So indicate that a
11632 register from BASE_REGS is needed as an intermediate
11635 On Darwin, pic addresses require a load from memory, which
11636 needs a base register. */
11637 if (rclass
!= BASE_REGS
11638 && (GET_CODE (in
) == SYMBOL_REF
11639 || GET_CODE (in
) == HIGH
11640 || GET_CODE (in
) == LABEL_REF
11641 || GET_CODE (in
) == CONST
))
11645 if (GET_CODE (in
) == REG
)
11647 regno
= REGNO (in
);
11648 if (regno
>= FIRST_PSEUDO_REGISTER
)
11650 regno
= true_regnum (in
);
11651 if (regno
>= FIRST_PSEUDO_REGISTER
)
11655 else if (GET_CODE (in
) == SUBREG
)
11657 regno
= true_regnum (in
);
11658 if (regno
>= FIRST_PSEUDO_REGISTER
)
11664 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
11666 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
11667 || (regno
>= 0 && INT_REGNO_P (regno
)))
11670 /* Constants, memory, and FP registers can go into FP registers. */
11671 if ((regno
== -1 || FP_REGNO_P (regno
))
11672 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
11673 return (mode
!= SDmode
) ? NO_REGS
: GENERAL_REGS
;
11675 /* Memory, and AltiVec registers can go into AltiVec registers. */
11676 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
11677 && rclass
== ALTIVEC_REGS
)
11680 /* We can copy among the CR registers. */
11681 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
11682 && regno
>= 0 && CR_REGNO_P (regno
))
11685 /* Otherwise, we need GENERAL_REGS. */
11686 return GENERAL_REGS
;
11689 /* Given a comparison operation, return the bit number in CCR to test. We
11690 know this is a valid comparison.
11692 SCC_P is 1 if this is for an scc. That means that %D will have been
11693 used instead of %C, so the bits will be in different places.
11695 Return -1 if OP isn't a valid comparison for some reason. */
11698 ccr_bit (rtx op
, int scc_p
)
11700 enum rtx_code code
= GET_CODE (op
);
11701 enum machine_mode cc_mode
;
11706 if (!COMPARISON_P (op
))
11709 reg
= XEXP (op
, 0);
11711 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
11713 cc_mode
= GET_MODE (reg
);
11714 cc_regnum
= REGNO (reg
);
11715 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
11717 validate_condition_mode (code
, cc_mode
);
11719 /* When generating a sCOND operation, only positive conditions are
11722 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
11723 || code
== GTU
|| code
== LTU
);
11728 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
11730 return base_bit
+ 2;
11731 case GT
: case GTU
: case UNLE
:
11732 return base_bit
+ 1;
11733 case LT
: case LTU
: case UNGE
:
11735 case ORDERED
: case UNORDERED
:
11736 return base_bit
+ 3;
11739 /* If scc, we will have done a cror to put the bit in the
11740 unordered position. So test that bit. For integer, this is ! LT
11741 unless this is an scc insn. */
11742 return scc_p
? base_bit
+ 3 : base_bit
;
11745 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
11748 gcc_unreachable ();
11752 /* Return the GOT register. */
11755 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
11757 /* The second flow pass currently (June 1999) can't update
11758 regs_ever_live without disturbing other parts of the compiler, so
11759 update it here to make the prolog/epilogue code happy. */
11760 if (!can_create_pseudo_p ()
11761 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
11762 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
11764 crtl
->uses_pic_offset_table
= 1;
11766 return pic_offset_table_rtx
;
11769 /* Function to init struct machine_function.
11770 This will be called, via a pointer variable,
11771 from push_function_context. */
11773 static struct machine_function
*
11774 rs6000_init_machine_status (void)
11776 return GGC_CNEW (machine_function
);
11779 /* These macros test for integers and extract the low-order bits. */
11781 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
11782 && GET_MODE (X) == VOIDmode)
11784 #define INT_LOWPART(X) \
11785 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
11788 extract_MB (rtx op
)
11791 unsigned long val
= INT_LOWPART (op
);
11793 /* If the high bit is zero, the value is the first 1 bit we find
11795 if ((val
& 0x80000000) == 0)
11797 gcc_assert (val
& 0xffffffff);
11800 while (((val
<<= 1) & 0x80000000) == 0)
11805 /* If the high bit is set and the low bit is not, or the mask is all
11806 1's, the value is zero. */
11807 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
11810 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11813 while (((val
>>= 1) & 1) != 0)
11820 extract_ME (rtx op
)
11823 unsigned long val
= INT_LOWPART (op
);
11825 /* If the low bit is zero, the value is the first 1 bit we find from
11827 if ((val
& 1) == 0)
11829 gcc_assert (val
& 0xffffffff);
11832 while (((val
>>= 1) & 1) == 0)
11838 /* If the low bit is set and the high bit is not, or the mask is all
11839 1's, the value is 31. */
11840 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
11843 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11846 while (((val
<<= 1) & 0x80000000) != 0)
11852 /* Locate some local-dynamic symbol still in use by this function
11853 so that we can print its name in some tls_ld pattern. */
11855 static const char *
11856 rs6000_get_some_local_dynamic_name (void)
11860 if (cfun
->machine
->some_ld_name
)
11861 return cfun
->machine
->some_ld_name
;
11863 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11865 && for_each_rtx (&PATTERN (insn
),
11866 rs6000_get_some_local_dynamic_name_1
, 0))
11867 return cfun
->machine
->some_ld_name
;
11869 gcc_unreachable ();
11872 /* Helper function for rs6000_get_some_local_dynamic_name. */
11875 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
11879 if (GET_CODE (x
) == SYMBOL_REF
)
11881 const char *str
= XSTR (x
, 0);
11882 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
11884 cfun
->machine
->some_ld_name
= str
;
11892 /* Write out a function code label. */
11895 rs6000_output_function_entry (FILE *file
, const char *fname
)
11897 if (fname
[0] != '.')
11899 switch (DEFAULT_ABI
)
11902 gcc_unreachable ();
11908 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
11917 RS6000_OUTPUT_BASENAME (file
, fname
);
11919 assemble_name (file
, fname
);
11922 /* Print an operand. Recognize special options, documented below. */
11925 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
11926 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
11928 #define SMALL_DATA_RELOC "sda21"
11929 #define SMALL_DATA_REG 0
11933 print_operand (FILE *file
, rtx x
, int code
)
11937 unsigned HOST_WIDE_INT uval
;
11942 /* Write out an instruction after the call which may be replaced
11943 with glue code by the loader. This depends on the AIX version. */
11944 asm_fprintf (file
, RS6000_CALL_GLUE
);
11947 /* %a is output_address. */
11950 /* If X is a constant integer whose low-order 5 bits are zero,
11951 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
11952 in the AIX assembler where "sri" with a zero shift count
11953 writes a trash instruction. */
11954 if (GET_CODE (x
) == CONST_INT
&& (INTVAL (x
) & 31) == 0)
11961 /* If constant, low-order 16 bits of constant, unsigned.
11962 Otherwise, write normally. */
11964 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 0xffff);
11966 print_operand (file
, x
, 0);
11970 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
11971 for 64-bit mask direction. */
11972 putc (((INT_LOWPART (x
) & 1) == 0 ? 'r' : 'l'), file
);
11975 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
11979 /* X is a CR register. Print the number of the GT bit of the CR. */
11980 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
11981 output_operand_lossage ("invalid %%E value");
11983 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 1);
11987 /* Like 'J' but get to the GT bit only. */
11988 gcc_assert (GET_CODE (x
) == REG
);
11990 /* Bit 1 is GT bit. */
11991 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
11993 /* Add one for shift count in rlinm for scc. */
11994 fprintf (file
, "%d", i
+ 1);
11998 /* X is a CR register. Print the number of the EQ bit of the CR */
11999 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
12000 output_operand_lossage ("invalid %%E value");
12002 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
12006 /* X is a CR register. Print the shift count needed to move it
12007 to the high-order four bits. */
12008 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
12009 output_operand_lossage ("invalid %%f value");
12011 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
12015 /* Similar, but print the count for the rotate in the opposite
12017 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
12018 output_operand_lossage ("invalid %%F value");
12020 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
12024 /* X is a constant integer. If it is negative, print "m",
12025 otherwise print "z". This is to make an aze or ame insn. */
12026 if (GET_CODE (x
) != CONST_INT
)
12027 output_operand_lossage ("invalid %%G value");
12028 else if (INTVAL (x
) >= 0)
12035 /* If constant, output low-order five bits. Otherwise, write
12038 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 31);
12040 print_operand (file
, x
, 0);
12044 /* If constant, output low-order six bits. Otherwise, write
12047 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 63);
12049 print_operand (file
, x
, 0);
12053 /* Print `i' if this is a constant, else nothing. */
12059 /* Write the bit number in CCR for jump. */
12060 i
= ccr_bit (x
, 0);
12062 output_operand_lossage ("invalid %%j code");
12064 fprintf (file
, "%d", i
);
12068 /* Similar, but add one for shift count in rlinm for scc and pass
12069 scc flag to `ccr_bit'. */
12070 i
= ccr_bit (x
, 1);
12072 output_operand_lossage ("invalid %%J code");
12074 /* If we want bit 31, write a shift count of zero, not 32. */
12075 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
12079 /* X must be a constant. Write the 1's complement of the
12082 output_operand_lossage ("invalid %%k value");
12084 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INT_LOWPART (x
));
12088 /* X must be a symbolic constant on ELF. Write an
12089 expression suitable for an 'addi' that adds in the low 16
12090 bits of the MEM. */
12091 if (GET_CODE (x
) != CONST
)
12093 print_operand_address (file
, x
);
12094 fputs ("@l", file
);
12098 if (GET_CODE (XEXP (x
, 0)) != PLUS
12099 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
12100 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
12101 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
12102 output_operand_lossage ("invalid %%K value");
12103 print_operand_address (file
, XEXP (XEXP (x
, 0), 0));
12104 fputs ("@l", file
);
12105 /* For GNU as, there must be a non-alphanumeric character
12106 between 'l' and the number. The '-' is added by
12107 print_operand() already. */
12108 if (INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0)
12110 print_operand (file
, XEXP (XEXP (x
, 0), 1), 0);
12114 /* %l is output_asm_label. */
12117 /* Write second word of DImode or DFmode reference. Works on register
12118 or non-indexed memory only. */
12119 if (GET_CODE (x
) == REG
)
12120 fputs (reg_names
[REGNO (x
) + 1], file
);
12121 else if (GET_CODE (x
) == MEM
)
12123 /* Handle possible auto-increment. Since it is pre-increment and
12124 we have already done it, we can just use an offset of word. */
12125 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
12126 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
12127 output_address (plus_constant (XEXP (XEXP (x
, 0), 0),
12129 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
12130 output_address (plus_constant (XEXP (XEXP (x
, 0), 0),
12133 output_address (XEXP (adjust_address_nv (x
, SImode
,
12137 if (small_data_operand (x
, GET_MODE (x
)))
12138 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
12139 reg_names
[SMALL_DATA_REG
]);
12144 /* MB value for a mask operand. */
12145 if (! mask_operand (x
, SImode
))
12146 output_operand_lossage ("invalid %%m value");
12148 fprintf (file
, "%d", extract_MB (x
));
12152 /* ME value for a mask operand. */
12153 if (! mask_operand (x
, SImode
))
12154 output_operand_lossage ("invalid %%M value");
12156 fprintf (file
, "%d", extract_ME (x
));
12159 /* %n outputs the negative of its operand. */
12162 /* Write the number of elements in the vector times 4. */
12163 if (GET_CODE (x
) != PARALLEL
)
12164 output_operand_lossage ("invalid %%N value");
12166 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
12170 /* Similar, but subtract 1 first. */
12171 if (GET_CODE (x
) != PARALLEL
)
12172 output_operand_lossage ("invalid %%O value");
12174 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
12178 /* X is a CONST_INT that is a power of two. Output the logarithm. */
12180 || INT_LOWPART (x
) < 0
12181 || (i
= exact_log2 (INT_LOWPART (x
))) < 0)
12182 output_operand_lossage ("invalid %%p value");
12184 fprintf (file
, "%d", i
);
12188 /* The operand must be an indirect memory reference. The result
12189 is the register name. */
12190 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
12191 || REGNO (XEXP (x
, 0)) >= 32)
12192 output_operand_lossage ("invalid %%P value");
12194 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
12198 /* This outputs the logical code corresponding to a boolean
12199 expression. The expression may have one or both operands
12200 negated (if one, only the first one). For condition register
12201 logical operations, it will also treat the negated
12202 CR codes as NOTs, but not handle NOTs of them. */
12204 const char *const *t
= 0;
12206 enum rtx_code code
= GET_CODE (x
);
12207 static const char * const tbl
[3][3] = {
12208 { "and", "andc", "nor" },
12209 { "or", "orc", "nand" },
12210 { "xor", "eqv", "xor" } };
12214 else if (code
== IOR
)
12216 else if (code
== XOR
)
12219 output_operand_lossage ("invalid %%q value");
12221 if (GET_CODE (XEXP (x
, 0)) != NOT
)
12225 if (GET_CODE (XEXP (x
, 1)) == NOT
)
12243 /* X is a CR register. Print the mask for `mtcrf'. */
12244 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
12245 output_operand_lossage ("invalid %%R value");
12247 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
12251 /* Low 5 bits of 32 - value */
12253 output_operand_lossage ("invalid %%s value");
12255 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INT_LOWPART (x
)) & 31);
12259 /* PowerPC64 mask position. All 0's is excluded.
12260 CONST_INT 32-bit mask is considered sign-extended so any
12261 transition must occur within the CONST_INT, not on the boundary. */
12262 if (! mask64_operand (x
, DImode
))
12263 output_operand_lossage ("invalid %%S value");
12265 uval
= INT_LOWPART (x
);
12267 if (uval
& 1) /* Clear Left */
12269 #if HOST_BITS_PER_WIDE_INT > 64
12270 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
12274 else /* Clear Right */
12277 #if HOST_BITS_PER_WIDE_INT > 64
12278 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
12284 gcc_assert (i
>= 0);
12285 fprintf (file
, "%d", i
);
12289 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
12290 gcc_assert (GET_CODE (x
) == REG
&& GET_MODE (x
) == CCmode
);
12292 /* Bit 3 is OV bit. */
12293 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
12295 /* If we want bit 31, write a shift count of zero, not 32. */
12296 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
12300 /* Print the symbolic name of a branch target register. */
12301 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
12302 && REGNO (x
) != CTR_REGNO
))
12303 output_operand_lossage ("invalid %%T value");
12304 else if (REGNO (x
) == LR_REGNO
)
12305 fputs (TARGET_NEW_MNEMONICS
? "lr" : "r", file
);
12307 fputs ("ctr", file
);
12311 /* High-order 16 bits of constant for use in unsigned operand. */
12313 output_operand_lossage ("invalid %%u value");
12315 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
12316 (INT_LOWPART (x
) >> 16) & 0xffff);
12320 /* High-order 16 bits of constant for use in signed operand. */
12322 output_operand_lossage ("invalid %%v value");
12324 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
12325 (INT_LOWPART (x
) >> 16) & 0xffff);
12329 /* Print `u' if this has an auto-increment or auto-decrement. */
12330 if (GET_CODE (x
) == MEM
12331 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
12332 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
12333 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
12338 /* Print the trap code for this operand. */
12339 switch (GET_CODE (x
))
12342 fputs ("eq", file
); /* 4 */
12345 fputs ("ne", file
); /* 24 */
12348 fputs ("lt", file
); /* 16 */
12351 fputs ("le", file
); /* 20 */
12354 fputs ("gt", file
); /* 8 */
12357 fputs ("ge", file
); /* 12 */
12360 fputs ("llt", file
); /* 2 */
12363 fputs ("lle", file
); /* 6 */
12366 fputs ("lgt", file
); /* 1 */
12369 fputs ("lge", file
); /* 5 */
12372 gcc_unreachable ();
12377 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
12380 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
12381 ((INT_LOWPART (x
) & 0xffff) ^ 0x8000) - 0x8000);
12383 print_operand (file
, x
, 0);
12387 /* MB value for a PowerPC64 rldic operand. */
12388 val
= (GET_CODE (x
) == CONST_INT
12389 ? INTVAL (x
) : CONST_DOUBLE_HIGH (x
));
12394 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
; i
++)
12395 if ((val
<<= 1) < 0)
12398 #if HOST_BITS_PER_WIDE_INT == 32
12399 if (GET_CODE (x
) == CONST_INT
&& i
>= 0)
12400 i
+= 32; /* zero-extend high-part was all 0's */
12401 else if (GET_CODE (x
) == CONST_DOUBLE
&& i
== 32)
12403 val
= CONST_DOUBLE_LOW (x
);
12409 for ( ; i
< 64; i
++)
12410 if ((val
<<= 1) < 0)
12415 fprintf (file
, "%d", i
+ 1);
12419 if (GET_CODE (x
) == MEM
12420 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
12421 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
12422 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
12427 /* Like 'L', for third word of TImode */
12428 if (GET_CODE (x
) == REG
)
12429 fputs (reg_names
[REGNO (x
) + 2], file
);
12430 else if (GET_CODE (x
) == MEM
)
12432 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
12433 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
12434 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 8));
12435 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
12436 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 8));
12438 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
12439 if (small_data_operand (x
, GET_MODE (x
)))
12440 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
12441 reg_names
[SMALL_DATA_REG
]);
12446 /* X is a SYMBOL_REF. Write out the name preceded by a
12447 period and without any trailing data in brackets. Used for function
12448 names. If we are configured for System V (or the embedded ABI) on
12449 the PowerPC, do not emit the period, since those systems do not use
12450 TOCs and the like. */
12451 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
12453 /* Mark the decl as referenced so that cgraph will output the
12455 if (SYMBOL_REF_DECL (x
))
12456 mark_decl_referenced (SYMBOL_REF_DECL (x
));
12458 /* For macho, check to see if we need a stub. */
12461 const char *name
= XSTR (x
, 0);
12463 if (MACHOPIC_INDIRECT
12464 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
12465 name
= machopic_indirection_name (x
, /*stub_p=*/true);
12467 assemble_name (file
, name
);
12469 else if (!DOT_SYMBOLS
)
12470 assemble_name (file
, XSTR (x
, 0));
12472 rs6000_output_function_entry (file
, XSTR (x
, 0));
12476 /* Like 'L', for last word of TImode. */
12477 if (GET_CODE (x
) == REG
)
12478 fputs (reg_names
[REGNO (x
) + 3], file
);
12479 else if (GET_CODE (x
) == MEM
)
12481 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
12482 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
12483 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 12));
12484 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
12485 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 12));
12487 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
12488 if (small_data_operand (x
, GET_MODE (x
)))
12489 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
12490 reg_names
[SMALL_DATA_REG
]);
12494 /* Print AltiVec or SPE memory operand. */
12499 gcc_assert (GET_CODE (x
) == MEM
);
12503 /* Ugly hack because %y is overloaded. */
12504 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
12505 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
12506 || GET_MODE (x
) == TFmode
12507 || GET_MODE (x
) == TImode
))
12509 /* Handle [reg]. */
12510 if (GET_CODE (tmp
) == REG
)
12512 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
12515 /* Handle [reg+UIMM]. */
12516 else if (GET_CODE (tmp
) == PLUS
&&
12517 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
12521 gcc_assert (GET_CODE (XEXP (tmp
, 0)) == REG
);
12523 x
= INTVAL (XEXP (tmp
, 1));
12524 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
12528 /* Fall through. Must be [reg+reg]. */
12531 && GET_CODE (tmp
) == AND
12532 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
12533 && INTVAL (XEXP (tmp
, 1)) == -16)
12534 tmp
= XEXP (tmp
, 0);
12535 if (GET_CODE (tmp
) == REG
)
12536 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
12539 if (!GET_CODE (tmp
) == PLUS
12540 || !REG_P (XEXP (tmp
, 0))
12541 || !REG_P (XEXP (tmp
, 1)))
12543 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
12547 if (REGNO (XEXP (tmp
, 0)) == 0)
12548 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
12549 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
12551 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
12552 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
12558 if (GET_CODE (x
) == REG
)
12559 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
12560 else if (GET_CODE (x
) == MEM
)
12562 /* We need to handle PRE_INC and PRE_DEC here, since we need to
12563 know the width from the mode. */
12564 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
12565 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
12566 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
12567 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
12568 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
12569 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
12570 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
12571 output_address (XEXP (XEXP (x
, 0), 1));
12573 output_address (XEXP (x
, 0));
12576 output_addr_const (file
, x
);
12580 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
12584 output_operand_lossage ("invalid %%xn code");
12588 /* Print the address of an operand. */
12591 print_operand_address (FILE *file
, rtx x
)
12593 if (GET_CODE (x
) == REG
)
12594 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
12595 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
12596 || GET_CODE (x
) == LABEL_REF
)
12598 output_addr_const (file
, x
);
12599 if (small_data_operand (x
, GET_MODE (x
)))
12600 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
12601 reg_names
[SMALL_DATA_REG
]);
12603 gcc_assert (!TARGET_TOC
);
12605 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == REG
)
12607 gcc_assert (REG_P (XEXP (x
, 0)));
12608 if (REGNO (XEXP (x
, 0)) == 0)
12609 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
12610 reg_names
[ REGNO (XEXP (x
, 0)) ]);
12612 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
12613 reg_names
[ REGNO (XEXP (x
, 1)) ]);
12615 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
12616 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
12617 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
12619 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
12620 && CONSTANT_P (XEXP (x
, 1)))
12622 output_addr_const (file
, XEXP (x
, 1));
12623 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
12627 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
12628 && CONSTANT_P (XEXP (x
, 1)))
12630 fprintf (file
, "lo16(");
12631 output_addr_const (file
, XEXP (x
, 1));
12632 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
12635 else if (legitimate_constant_pool_address_p (x
))
12637 output_addr_const (file
, XEXP (x
, 1));
12638 fprintf (file
, "(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
12641 gcc_unreachable ();
12644 /* Implement OUTPUT_ADDR_CONST_EXTRA for address X. */
12647 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
12649 if (GET_CODE (x
) == UNSPEC
)
12650 switch (XINT (x
, 1))
12652 case UNSPEC_TOCREL
:
12653 x
= XVECEXP (x
, 0, 0);
12654 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
12655 output_addr_const (file
, x
);
12656 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
12659 assemble_name (file
, toc_label_name
);
12661 else if (TARGET_ELF
)
12662 fputs ("@toc", file
);
12666 case UNSPEC_MACHOPIC_OFFSET
:
12667 output_addr_const (file
, XVECEXP (x
, 0, 0));
12669 machopic_output_function_base_name (file
);
12676 /* Target hook for assembling integer objects. The PowerPC version has
12677 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
12678 is defined. It also needs to handle DI-mode objects on 64-bit
12682 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
12684 #ifdef RELOCATABLE_NEEDS_FIXUP
12685 /* Special handling for SI values. */
12686 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
12688 static int recurse
= 0;
12690 /* For -mrelocatable, we mark all addresses that need to be fixed up
12691 in the .fixup section. */
12692 if (TARGET_RELOCATABLE
12693 && in_section
!= toc_section
12694 && in_section
!= text_section
12695 && !unlikely_text_section_p (in_section
)
12697 && GET_CODE (x
) != CONST_INT
12698 && GET_CODE (x
) != CONST_DOUBLE
12704 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
12706 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
12707 fprintf (asm_out_file
, "\t.long\t(");
12708 output_addr_const (asm_out_file
, x
);
12709 fprintf (asm_out_file
, ")@fixup\n");
12710 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
12711 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
12712 fprintf (asm_out_file
, "\t.long\t");
12713 assemble_name (asm_out_file
, buf
);
12714 fprintf (asm_out_file
, "\n\t.previous\n");
12718 /* Remove initial .'s to turn a -mcall-aixdesc function
12719 address into the address of the descriptor, not the function
12721 else if (GET_CODE (x
) == SYMBOL_REF
12722 && XSTR (x
, 0)[0] == '.'
12723 && DEFAULT_ABI
== ABI_AIX
)
12725 const char *name
= XSTR (x
, 0);
12726 while (*name
== '.')
12729 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
12733 #endif /* RELOCATABLE_NEEDS_FIXUP */
12734 return default_assemble_integer (x
, size
, aligned_p
);
12737 #ifdef HAVE_GAS_HIDDEN
12738 /* Emit an assembler directive to set symbol visibility for DECL to
12739 VISIBILITY_TYPE. */
12742 rs6000_assemble_visibility (tree decl
, int vis
)
12744 /* Functions need to have their entry point symbol visibility set as
12745 well as their descriptor symbol visibility. */
12746 if (DEFAULT_ABI
== ABI_AIX
12748 && TREE_CODE (decl
) == FUNCTION_DECL
)
12750 static const char * const visibility_types
[] = {
12751 NULL
, "internal", "hidden", "protected"
12754 const char *name
, *type
;
12756 name
= ((* targetm
.strip_name_encoding
)
12757 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
12758 type
= visibility_types
[vis
];
12760 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
12761 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
12764 default_assemble_visibility (decl
, vis
);
12769 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
12771 /* Reversal of FP compares takes care -- an ordered compare
12772 becomes an unordered compare and vice versa. */
12773 if (mode
== CCFPmode
12774 && (!flag_finite_math_only
12775 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
12776 || code
== UNEQ
|| code
== LTGT
))
12777 return reverse_condition_maybe_unordered (code
);
12779 return reverse_condition (code
);
12782 /* Generate a compare for CODE. Return a brand-new rtx that
12783 represents the result of the compare. */
12786 rs6000_generate_compare (rtx cmp
, enum machine_mode mode
)
12788 enum machine_mode comp_mode
;
12789 rtx compare_result
;
12790 enum rtx_code code
= GET_CODE (cmp
);
12791 rtx op0
= XEXP (cmp
, 0);
12792 rtx op1
= XEXP (cmp
, 1);
12794 if (FLOAT_MODE_P (mode
))
12795 comp_mode
= CCFPmode
;
12796 else if (code
== GTU
|| code
== LTU
12797 || code
== GEU
|| code
== LEU
)
12798 comp_mode
= CCUNSmode
;
12799 else if ((code
== EQ
|| code
== NE
)
12800 && GET_CODE (op0
) == SUBREG
12801 && GET_CODE (op1
) == SUBREG
12802 && SUBREG_PROMOTED_UNSIGNED_P (op0
)
12803 && SUBREG_PROMOTED_UNSIGNED_P (op1
))
12804 /* These are unsigned values, perhaps there will be a later
12805 ordering compare that can be shared with this one.
12806 Unfortunately we cannot detect the signedness of the operands
12807 for non-subregs. */
12808 comp_mode
= CCUNSmode
;
12810 comp_mode
= CCmode
;
12812 /* First, the compare. */
12813 compare_result
= gen_reg_rtx (comp_mode
);
12815 /* E500 FP compare instructions on the GPRs. Yuck! */
12816 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
12817 && FLOAT_MODE_P (mode
))
12819 rtx cmp
, or_result
, compare_result2
;
12820 enum machine_mode op_mode
= GET_MODE (op0
);
12822 if (op_mode
== VOIDmode
)
12823 op_mode
= GET_MODE (op1
);
12825 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
12826 This explains the following mess. */
12830 case EQ
: case UNEQ
: case NE
: case LTGT
:
12834 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
12835 ? gen_tstsfeq_gpr (compare_result
, op0
, op1
)
12836 : gen_cmpsfeq_gpr (compare_result
, op0
, op1
);
12840 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
12841 ? gen_tstdfeq_gpr (compare_result
, op0
, op1
)
12842 : gen_cmpdfeq_gpr (compare_result
, op0
, op1
);
12846 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
12847 ? gen_tsttfeq_gpr (compare_result
, op0
, op1
)
12848 : gen_cmptfeq_gpr (compare_result
, op0
, op1
);
12852 gcc_unreachable ();
12856 case GT
: case GTU
: case UNGT
: case UNGE
: case GE
: case GEU
:
12860 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
12861 ? gen_tstsfgt_gpr (compare_result
, op0
, op1
)
12862 : gen_cmpsfgt_gpr (compare_result
, op0
, op1
);
12866 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
12867 ? gen_tstdfgt_gpr (compare_result
, op0
, op1
)
12868 : gen_cmpdfgt_gpr (compare_result
, op0
, op1
);
12872 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
12873 ? gen_tsttfgt_gpr (compare_result
, op0
, op1
)
12874 : gen_cmptfgt_gpr (compare_result
, op0
, op1
);
12878 gcc_unreachable ();
12882 case LT
: case LTU
: case UNLT
: case UNLE
: case LE
: case LEU
:
12886 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
12887 ? gen_tstsflt_gpr (compare_result
, op0
, op1
)
12888 : gen_cmpsflt_gpr (compare_result
, op0
, op1
);
12892 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
12893 ? gen_tstdflt_gpr (compare_result
, op0
, op1
)
12894 : gen_cmpdflt_gpr (compare_result
, op0
, op1
);
12898 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
12899 ? gen_tsttflt_gpr (compare_result
, op0
, op1
)
12900 : gen_cmptflt_gpr (compare_result
, op0
, op1
);
12904 gcc_unreachable ();
12908 gcc_unreachable ();
12911 /* Synthesize LE and GE from LT/GT || EQ. */
12912 if (code
== LE
|| code
== GE
|| code
== LEU
|| code
== GEU
)
12918 case LE
: code
= LT
; break;
12919 case GE
: code
= GT
; break;
12920 case LEU
: code
= LT
; break;
12921 case GEU
: code
= GT
; break;
12922 default: gcc_unreachable ();
12925 compare_result2
= gen_reg_rtx (CCFPmode
);
12931 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
12932 ? gen_tstsfeq_gpr (compare_result2
, op0
, op1
)
12933 : gen_cmpsfeq_gpr (compare_result2
, op0
, op1
);
12937 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
12938 ? gen_tstdfeq_gpr (compare_result2
, op0
, op1
)
12939 : gen_cmpdfeq_gpr (compare_result2
, op0
, op1
);
12943 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
12944 ? gen_tsttfeq_gpr (compare_result2
, op0
, op1
)
12945 : gen_cmptfeq_gpr (compare_result2
, op0
, op1
);
12949 gcc_unreachable ();
12953 /* OR them together. */
12954 or_result
= gen_reg_rtx (CCFPmode
);
12955 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
12957 compare_result
= or_result
;
12962 if (code
== NE
|| code
== LTGT
)
12972 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
12973 CLOBBERs to match cmptf_internal2 pattern. */
12974 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
12975 && GET_MODE (op0
) == TFmode
12976 && !TARGET_IEEEQUAD
12977 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
12978 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
12980 gen_rtx_SET (VOIDmode
,
12982 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
12983 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12984 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12985 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12986 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12987 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12988 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12989 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12990 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)))));
12991 else if (GET_CODE (op1
) == UNSPEC
12992 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
12994 rtx op1
= XVECEXP (op1
, 0, 0);
12995 comp_mode
= CCEQmode
;
12996 compare_result
= gen_reg_rtx (CCEQmode
);
12998 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1
));
13000 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1
));
13003 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
13004 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
13007 /* Some kinds of FP comparisons need an OR operation;
13008 under flag_finite_math_only we don't bother. */
13009 if (FLOAT_MODE_P (mode
)
13010 && !flag_finite_math_only
13011 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
13012 && (code
== LE
|| code
== GE
13013 || code
== UNEQ
|| code
== LTGT
13014 || code
== UNGT
|| code
== UNLT
))
13016 enum rtx_code or1
, or2
;
13017 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
13018 rtx or_result
= gen_reg_rtx (CCEQmode
);
13022 case LE
: or1
= LT
; or2
= EQ
; break;
13023 case GE
: or1
= GT
; or2
= EQ
; break;
13024 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
13025 case LTGT
: or1
= LT
; or2
= GT
; break;
13026 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
13027 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
13028 default: gcc_unreachable ();
13030 validate_condition_mode (or1
, comp_mode
);
13031 validate_condition_mode (or2
, comp_mode
);
13032 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
13033 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
13034 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
13035 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
13037 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
13039 compare_result
= or_result
;
13043 validate_condition_mode (code
, GET_MODE (compare_result
));
13045 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
13049 /* Emit the RTL for an sCOND pattern. */
13052 rs6000_emit_sCOND (enum machine_mode mode
, rtx operands
[])
13055 enum machine_mode op_mode
;
13056 enum rtx_code cond_code
;
13057 rtx result
= operands
[0];
13059 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
13060 cond_code
= GET_CODE (condition_rtx
);
13062 if (FLOAT_MODE_P (mode
)
13063 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
13067 PUT_MODE (condition_rtx
, SImode
);
13068 t
= XEXP (condition_rtx
, 0);
13070 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
13072 if (cond_code
== NE
)
13073 emit_insn (gen_e500_flip_gt_bit (t
, t
));
13075 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
13079 if (cond_code
== NE
13080 || cond_code
== GE
|| cond_code
== LE
13081 || cond_code
== GEU
|| cond_code
== LEU
13082 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
13084 rtx not_result
= gen_reg_rtx (CCEQmode
);
13085 rtx not_op
, rev_cond_rtx
;
13086 enum machine_mode cc_mode
;
13088 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
13090 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
13091 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
13092 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
13093 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
13094 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
13097 op_mode
= GET_MODE (XEXP (operands
[1], 0));
13098 if (op_mode
== VOIDmode
)
13099 op_mode
= GET_MODE (XEXP (operands
[1], 1));
13101 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
13103 PUT_MODE (condition_rtx
, DImode
);
13104 convert_move (result
, condition_rtx
, 0);
13108 PUT_MODE (condition_rtx
, SImode
);
13109 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
13113 /* Emit a branch of kind CODE to location LOC. */
13116 rs6000_emit_cbranch (enum machine_mode mode
, rtx operands
[])
13118 rtx condition_rtx
, loc_ref
;
13120 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
13121 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
13122 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
13123 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
13124 loc_ref
, pc_rtx
)));
13127 /* Return the string to output a conditional branch to LABEL, which is
13128 the operand number of the label, or -1 if the branch is really a
13129 conditional return.
13131 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
13132 condition code register and its mode specifies what kind of
13133 comparison we made.
13135 REVERSED is nonzero if we should reverse the sense of the comparison.
13137 INSN is the insn. */
13140 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
13142 static char string
[64];
13143 enum rtx_code code
= GET_CODE (op
);
13144 rtx cc_reg
= XEXP (op
, 0);
13145 enum machine_mode mode
= GET_MODE (cc_reg
);
13146 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
13147 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
13148 int really_reversed
= reversed
^ need_longbranch
;
13154 validate_condition_mode (code
, mode
);
13156 /* Work out which way this really branches. We could use
13157 reverse_condition_maybe_unordered here always but this
13158 makes the resulting assembler clearer. */
13159 if (really_reversed
)
13161 /* Reversal of FP compares takes care -- an ordered compare
13162 becomes an unordered compare and vice versa. */
13163 if (mode
== CCFPmode
)
13164 code
= reverse_condition_maybe_unordered (code
);
13166 code
= reverse_condition (code
);
13169 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
13171 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
13176 /* Opposite of GT. */
13185 gcc_unreachable ();
13191 /* Not all of these are actually distinct opcodes, but
13192 we distinguish them for clarity of the resulting assembler. */
13193 case NE
: case LTGT
:
13194 ccode
= "ne"; break;
13195 case EQ
: case UNEQ
:
13196 ccode
= "eq"; break;
13198 ccode
= "ge"; break;
13199 case GT
: case GTU
: case UNGT
:
13200 ccode
= "gt"; break;
13202 ccode
= "le"; break;
13203 case LT
: case LTU
: case UNLT
:
13204 ccode
= "lt"; break;
13205 case UNORDERED
: ccode
= "un"; break;
13206 case ORDERED
: ccode
= "nu"; break;
13207 case UNGE
: ccode
= "nl"; break;
13208 case UNLE
: ccode
= "ng"; break;
13210 gcc_unreachable ();
13213 /* Maybe we have a guess as to how likely the branch is.
13214 The old mnemonics don't have a way to specify this information. */
13216 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
13217 if (note
!= NULL_RTX
)
13219 /* PROB is the difference from 50%. */
13220 int prob
= INTVAL (XEXP (note
, 0)) - REG_BR_PROB_BASE
/ 2;
13222 /* Only hint for highly probable/improbable branches on newer
13223 cpus as static prediction overrides processor dynamic
13224 prediction. For older cpus we may as well always hint, but
13225 assume not taken for branches that are very close to 50% as a
13226 mispredicted taken branch is more expensive than a
13227 mispredicted not-taken branch. */
13228 if (rs6000_always_hint
13229 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
13230 && br_prob_note_reliable_p (note
)))
13232 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
13233 && ((prob
> 0) ^ need_longbranch
))
13241 s
+= sprintf (s
, "{b%sr|b%slr%s} ", ccode
, ccode
, pred
);
13243 s
+= sprintf (s
, "{b%s|b%s%s} ", ccode
, ccode
, pred
);
13245 /* We need to escape any '%' characters in the reg_names string.
13246 Assume they'd only be the first character.... */
13247 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
13249 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
13253 /* If the branch distance was too far, we may have to use an
13254 unconditional branch to go the distance. */
13255 if (need_longbranch
)
13256 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
13258 s
+= sprintf (s
, ",%s", label
);
13264 /* Return the string to flip the GT bit on a CR. */
13266 output_e500_flip_gt_bit (rtx dst
, rtx src
)
13268 static char string
[64];
13271 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
13272 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
13275 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
13276 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
13278 sprintf (string
, "crnot %d,%d", a
, b
);
13282 /* Return insn index for the vector compare instruction for given CODE,
13283 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
13287 get_vec_cmp_insn (enum rtx_code code
,
13288 enum machine_mode dest_mode
,
13289 enum machine_mode op_mode
)
13291 if (!TARGET_ALTIVEC
)
13292 return INSN_NOT_AVAILABLE
;
13297 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
13298 return UNSPEC_VCMPEQUB
;
13299 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
13300 return UNSPEC_VCMPEQUH
;
13301 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
13302 return UNSPEC_VCMPEQUW
;
13303 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
13304 return UNSPEC_VCMPEQFP
;
13307 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
13308 return UNSPEC_VCMPGEFP
;
13310 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
13311 return UNSPEC_VCMPGTSB
;
13312 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
13313 return UNSPEC_VCMPGTSH
;
13314 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
13315 return UNSPEC_VCMPGTSW
;
13316 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
13317 return UNSPEC_VCMPGTFP
;
13320 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
13321 return UNSPEC_VCMPGTUB
;
13322 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
13323 return UNSPEC_VCMPGTUH
;
13324 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
13325 return UNSPEC_VCMPGTUW
;
13330 return INSN_NOT_AVAILABLE
;
13333 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
13334 DMODE is expected destination mode. This is a recursive function. */
13337 rs6000_emit_vector_compare (enum rtx_code rcode
,
13339 enum machine_mode dmode
)
13343 enum machine_mode dest_mode
;
13344 enum machine_mode op_mode
= GET_MODE (op1
);
13346 gcc_assert (TARGET_ALTIVEC
);
13347 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
13349 /* Floating point vector compare instructions uses destination V4SImode.
13350 Move destination to appropriate mode later. */
13351 if (dmode
== V4SFmode
)
13352 dest_mode
= V4SImode
;
13356 mask
= gen_reg_rtx (dest_mode
);
13357 vec_cmp_insn
= get_vec_cmp_insn (rcode
, dest_mode
, op_mode
);
13359 if (vec_cmp_insn
== INSN_NOT_AVAILABLE
)
13361 bool swap_operands
= false;
13362 bool try_again
= false;
13367 swap_operands
= true;
13372 swap_operands
= true;
13380 /* Invert condition and try again.
13381 e.g., A != B becomes ~(A==B). */
13383 enum rtx_code rev_code
;
13384 enum insn_code nor_code
;
13387 rev_code
= reverse_condition_maybe_unordered (rcode
);
13388 eq_rtx
= rs6000_emit_vector_compare (rev_code
, op0
, op1
,
13391 nor_code
= optab_handler (one_cmpl_optab
, (int)dest_mode
)->insn_code
;
13392 gcc_assert (nor_code
!= CODE_FOR_nothing
);
13393 emit_insn (GEN_FCN (nor_code
) (mask
, eq_rtx
));
13395 if (dmode
!= dest_mode
)
13397 rtx temp
= gen_reg_rtx (dest_mode
);
13398 convert_move (temp
, mask
, 0);
13408 /* Try GT/GTU/LT/LTU OR EQ */
13411 enum insn_code ior_code
;
13412 enum rtx_code new_code
;
13433 gcc_unreachable ();
13436 c_rtx
= rs6000_emit_vector_compare (new_code
,
13437 op0
, op1
, dest_mode
);
13438 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
,
13441 ior_code
= optab_handler (ior_optab
, (int)dest_mode
)->insn_code
;
13442 gcc_assert (ior_code
!= CODE_FOR_nothing
);
13443 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
13444 if (dmode
!= dest_mode
)
13446 rtx temp
= gen_reg_rtx (dest_mode
);
13447 convert_move (temp
, mask
, 0);
13454 gcc_unreachable ();
13459 vec_cmp_insn
= get_vec_cmp_insn (rcode
, dest_mode
, op_mode
);
13460 /* You only get two chances. */
13461 gcc_assert (vec_cmp_insn
!= INSN_NOT_AVAILABLE
);
13473 emit_insn (gen_rtx_SET (VOIDmode
, mask
,
13474 gen_rtx_UNSPEC (dest_mode
,
13475 gen_rtvec (2, op0
, op1
),
13477 if (dmode
!= dest_mode
)
13479 rtx temp
= gen_reg_rtx (dest_mode
);
13480 convert_move (temp
, mask
, 0);
13486 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
13487 valid insn doesn exist for given mode. */
13490 get_vsel_insn (enum machine_mode mode
)
13495 return UNSPEC_VSEL4SI
;
13498 return UNSPEC_VSEL4SF
;
13501 return UNSPEC_VSEL8HI
;
13504 return UNSPEC_VSEL16QI
;
13507 return INSN_NOT_AVAILABLE
;
13510 return INSN_NOT_AVAILABLE
;
13513 /* Emit vector select insn where DEST is destination using
13514 operands OP1, OP2 and MASK. */
13517 rs6000_emit_vector_select (rtx dest
, rtx op1
, rtx op2
, rtx mask
)
13520 enum machine_mode dest_mode
= GET_MODE (dest
);
13521 int vsel_insn_index
= get_vsel_insn (GET_MODE (dest
));
13523 temp
= gen_reg_rtx (dest_mode
);
13525 /* For each vector element, select op1 when mask is 1 otherwise
13527 t
= gen_rtx_SET (VOIDmode
, temp
,
13528 gen_rtx_UNSPEC (dest_mode
,
13529 gen_rtvec (3, op2
, op1
, mask
),
13532 emit_move_insn (dest
, temp
);
13536 /* Emit vector conditional expression.
13537 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
13538 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
13541 rs6000_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
13542 rtx cond
, rtx cc_op0
, rtx cc_op1
)
13544 enum machine_mode dest_mode
= GET_MODE (dest
);
13545 enum rtx_code rcode
= GET_CODE (cond
);
13548 if (!TARGET_ALTIVEC
)
13551 /* Get the vector mask for the given relational operations. */
13552 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, dest_mode
);
13554 rs6000_emit_vector_select (dest
, op1
, op2
, mask
);
13559 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
13560 operands of the last comparison is nonzero/true, FALSE_COND if it
13561 is zero/false. Return 0 if the hardware has no such operation. */
13564 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
13566 enum rtx_code code
= GET_CODE (op
);
13567 rtx op0
= XEXP (op
, 0);
13568 rtx op1
= XEXP (op
, 1);
13569 REAL_VALUE_TYPE c1
;
13570 enum machine_mode compare_mode
= GET_MODE (op0
);
13571 enum machine_mode result_mode
= GET_MODE (dest
);
13573 bool is_against_zero
;
13575 /* These modes should always match. */
13576 if (GET_MODE (op1
) != compare_mode
13577 /* In the isel case however, we can use a compare immediate, so
13578 op1 may be a small constant. */
13579 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
13581 if (GET_MODE (true_cond
) != result_mode
)
13583 if (GET_MODE (false_cond
) != result_mode
)
13586 /* First, work out if the hardware can do this at all, or
13587 if it's too slow.... */
13588 if (!FLOAT_MODE_P (compare_mode
))
13591 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
13594 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
13595 && SCALAR_FLOAT_MODE_P (compare_mode
))
13598 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
13600 /* A floating-point subtract might overflow, underflow, or produce
13601 an inexact result, thus changing the floating-point flags, so it
13602 can't be generated if we care about that. It's safe if one side
13603 of the construct is zero, since then no subtract will be
13605 if (SCALAR_FLOAT_MODE_P (compare_mode
)
13606 && flag_trapping_math
&& ! is_against_zero
)
13609 /* Eliminate half of the comparisons by switching operands, this
13610 makes the remaining code simpler. */
13611 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
13612 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
13614 code
= reverse_condition_maybe_unordered (code
);
13616 true_cond
= false_cond
;
13620 /* UNEQ and LTGT take four instructions for a comparison with zero,
13621 it'll probably be faster to use a branch here too. */
13622 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
13625 if (GET_CODE (op1
) == CONST_DOUBLE
)
13626 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
13628 /* We're going to try to implement comparisons by performing
13629 a subtract, then comparing against zero. Unfortunately,
13630 Inf - Inf is NaN which is not zero, and so if we don't
13631 know that the operand is finite and the comparison
13632 would treat EQ different to UNORDERED, we can't do it. */
13633 if (HONOR_INFINITIES (compare_mode
)
13634 && code
!= GT
&& code
!= UNGE
13635 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
13636 /* Constructs of the form (a OP b ? a : b) are safe. */
13637 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
13638 || (! rtx_equal_p (op0
, true_cond
)
13639 && ! rtx_equal_p (op1
, true_cond
))))
13642 /* At this point we know we can use fsel. */
13644 /* Reduce the comparison to a comparison against zero. */
13645 if (! is_against_zero
)
13647 temp
= gen_reg_rtx (compare_mode
);
13648 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
13649 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
13651 op1
= CONST0_RTX (compare_mode
);
13654 /* If we don't care about NaNs we can reduce some of the comparisons
13655 down to faster ones. */
13656 if (! HONOR_NANS (compare_mode
))
13662 true_cond
= false_cond
;
13675 /* Now, reduce everything down to a GE. */
13682 temp
= gen_reg_rtx (compare_mode
);
13683 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
13688 temp
= gen_reg_rtx (compare_mode
);
13689 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
13694 temp
= gen_reg_rtx (compare_mode
);
13695 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
13696 gen_rtx_NEG (compare_mode
,
13697 gen_rtx_ABS (compare_mode
, op0
))));
13702 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
13703 temp
= gen_reg_rtx (result_mode
);
13704 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
13705 gen_rtx_IF_THEN_ELSE (result_mode
,
13706 gen_rtx_GE (VOIDmode
,
13708 true_cond
, false_cond
)));
13709 false_cond
= true_cond
;
13712 temp
= gen_reg_rtx (compare_mode
);
13713 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
13718 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
13719 temp
= gen_reg_rtx (result_mode
);
13720 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
13721 gen_rtx_IF_THEN_ELSE (result_mode
,
13722 gen_rtx_GE (VOIDmode
,
13724 true_cond
, false_cond
)));
13725 true_cond
= false_cond
;
13728 temp
= gen_reg_rtx (compare_mode
);
13729 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
13734 gcc_unreachable ();
13737 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
13738 gen_rtx_IF_THEN_ELSE (result_mode
,
13739 gen_rtx_GE (VOIDmode
,
13741 true_cond
, false_cond
)));
13745 /* Same as above, but for ints (isel). */
13748 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
13750 rtx condition_rtx
, cr
;
13752 /* All isel implementations thus far are 32-bits. */
13753 if (GET_MODE (XEXP (op
, 0)) != SImode
)
13756 /* We still have to do the compare, because isel doesn't do a
13757 compare, it just looks at the CRx bits set by a previous compare
13759 condition_rtx
= rs6000_generate_compare (op
, SImode
);
13760 cr
= XEXP (condition_rtx
, 0);
13762 if (GET_MODE (cr
) == CCmode
)
13763 emit_insn (gen_isel_signed (dest
, condition_rtx
,
13764 true_cond
, false_cond
, cr
));
13766 emit_insn (gen_isel_unsigned (dest
, condition_rtx
,
13767 true_cond
, false_cond
, cr
));
13773 output_isel (rtx
*operands
)
13775 enum rtx_code code
;
13777 code
= GET_CODE (operands
[1]);
13778 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
13780 PUT_CODE (operands
[1], reverse_condition (code
));
13781 return "isel %0,%3,%2,%j1";
13784 return "isel %0,%2,%3,%j1";
13788 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
13790 enum machine_mode mode
= GET_MODE (op0
);
13794 if (code
== SMAX
|| code
== SMIN
)
13799 if (code
== SMAX
|| code
== UMAX
)
13800 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
13801 op0
, op1
, mode
, 0);
13803 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
13804 op1
, op0
, mode
, 0);
13805 gcc_assert (target
);
13806 if (target
!= dest
)
13807 emit_move_insn (dest
, target
);
13810 /* Emit instructions to perform a load-reserved/store-conditional operation.
13811 The operation performed is an atomic
13812 (set M (CODE:MODE M OP))
13813 If not NULL, BEFORE is atomically set to M before the operation, and
13814 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
13815 If SYNC_P then a memory barrier is emitted before the operation.
13816 Either OP or M may be wrapped in a NOT operation. */
13819 rs6000_emit_sync (enum rtx_code code
, enum machine_mode mode
,
13820 rtx m
, rtx op
, rtx before_param
, rtx after_param
,
13823 enum machine_mode used_mode
;
13824 rtx the_op
, set_before
, set_after
, set_atomic
, cc_scratch
, before
, after
;
13827 HOST_WIDE_INT imask
= GET_MODE_MASK (mode
);
13828 rtx shift
= NULL_RTX
;
13831 emit_insn (gen_lwsync ());
13835 /* If this is smaller than SImode, we'll have to use SImode with
13837 if (mode
== QImode
|| mode
== HImode
)
13841 if (MEM_ALIGN (used_m
) >= 32)
13844 if (BYTES_BIG_ENDIAN
)
13845 ishift
= GET_MODE_BITSIZE (SImode
) - GET_MODE_BITSIZE (mode
);
13847 shift
= GEN_INT (ishift
);
13848 used_m
= change_address (used_m
, SImode
, 0);
13852 rtx addrSI
, aligned_addr
;
13853 int shift_mask
= mode
== QImode
? 0x18 : 0x10;
13855 addrSI
= gen_lowpart_common (SImode
,
13856 force_reg (Pmode
, XEXP (used_m
, 0)));
13857 addrSI
= force_reg (SImode
, addrSI
);
13858 shift
= gen_reg_rtx (SImode
);
13860 emit_insn (gen_rlwinm (shift
, addrSI
, GEN_INT (3),
13861 GEN_INT (shift_mask
)));
13862 emit_insn (gen_xorsi3 (shift
, shift
, GEN_INT (shift_mask
)));
13864 aligned_addr
= expand_binop (Pmode
, and_optab
,
13866 GEN_INT (-4), NULL_RTX
,
13867 1, OPTAB_LIB_WIDEN
);
13868 used_m
= change_address (used_m
, SImode
, aligned_addr
);
13869 set_mem_align (used_m
, 32);
13871 /* It's safe to keep the old alias set of USED_M, because
13872 the operation is atomic and only affects the original
13876 if (GET_CODE (op
) == NOT
)
13878 oldop
= lowpart_subreg (SImode
, XEXP (op
, 0), mode
);
13879 oldop
= gen_rtx_NOT (SImode
, oldop
);
13882 oldop
= lowpart_subreg (SImode
, op
, mode
);
13888 newop
= expand_binop (SImode
, and_optab
,
13889 oldop
, GEN_INT (imask
), NULL_RTX
,
13890 1, OPTAB_LIB_WIDEN
);
13891 emit_insn (gen_ashlsi3 (newop
, newop
, shift
));
13894 case NOT
: /* NAND */
13895 newop
= expand_binop (SImode
, ior_optab
,
13896 oldop
, GEN_INT (~imask
), NULL_RTX
,
13897 1, OPTAB_LIB_WIDEN
);
13898 emit_insn (gen_rotlsi3 (newop
, newop
, shift
));
13902 newop
= expand_binop (SImode
, ior_optab
,
13903 oldop
, GEN_INT (~imask
), NULL_RTX
,
13904 1, OPTAB_LIB_WIDEN
);
13905 emit_insn (gen_rotlsi3 (newop
, newop
, shift
));
13913 newop
= expand_binop (SImode
, and_optab
,
13914 oldop
, GEN_INT (imask
), NULL_RTX
,
13915 1, OPTAB_LIB_WIDEN
);
13916 emit_insn (gen_ashlsi3 (newop
, newop
, shift
));
13918 mask
= gen_reg_rtx (SImode
);
13919 emit_move_insn (mask
, GEN_INT (imask
));
13920 emit_insn (gen_ashlsi3 (mask
, mask
, shift
));
13923 newop
= gen_rtx_PLUS (SImode
, m
, newop
);
13925 newop
= gen_rtx_MINUS (SImode
, m
, newop
);
13926 newop
= gen_rtx_AND (SImode
, newop
, mask
);
13927 newop
= gen_rtx_IOR (SImode
, newop
,
13928 gen_rtx_AND (SImode
,
13929 gen_rtx_NOT (SImode
, mask
),
13935 gcc_unreachable ();
13939 used_mode
= SImode
;
13940 before
= gen_reg_rtx (used_mode
);
13941 after
= gen_reg_rtx (used_mode
);
13946 before
= before_param
;
13947 after
= after_param
;
13949 if (before
== NULL_RTX
)
13950 before
= gen_reg_rtx (used_mode
);
13951 if (after
== NULL_RTX
)
13952 after
= gen_reg_rtx (used_mode
);
13955 if ((code
== PLUS
|| code
== MINUS
)
13956 && used_mode
!= mode
)
13957 the_op
= op
; /* Computed above. */
13958 else if (GET_CODE (op
) == NOT
&& GET_CODE (m
) != NOT
)
13959 the_op
= gen_rtx_fmt_ee (code
, used_mode
, op
, m
);
13960 else if (code
== NOT
)
13961 the_op
= gen_rtx_fmt_ee (IOR
, used_mode
,
13962 gen_rtx_NOT (used_mode
, m
),
13963 gen_rtx_NOT (used_mode
, op
));
13965 the_op
= gen_rtx_fmt_ee (code
, used_mode
, m
, op
);
13967 set_after
= gen_rtx_SET (VOIDmode
, after
, the_op
);
13968 set_before
= gen_rtx_SET (VOIDmode
, before
, used_m
);
13969 set_atomic
= gen_rtx_SET (VOIDmode
, used_m
,
13970 gen_rtx_UNSPEC (used_mode
,
13971 gen_rtvec (1, the_op
),
13973 cc_scratch
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (CCmode
));
13975 if ((code
== PLUS
|| code
== MINUS
) && used_mode
!= mode
)
13976 vec
= gen_rtvec (5, set_after
, set_before
, set_atomic
, cc_scratch
,
13977 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (SImode
)));
13979 vec
= gen_rtvec (4, set_after
, set_before
, set_atomic
, cc_scratch
);
13980 emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
13982 /* Shift and mask the return values properly. */
13983 if (used_mode
!= mode
&& before_param
)
13985 emit_insn (gen_lshrsi3 (before
, before
, shift
));
13986 convert_move (before_param
, before
, 1);
13989 if (used_mode
!= mode
&& after_param
)
13991 emit_insn (gen_lshrsi3 (after
, after
, shift
));
13992 convert_move (after_param
, after
, 1);
13995 /* The previous sequence will end with a branch that's dependent on
13996 the conditional store, so placing an isync will ensure that no
13997 other instructions (especially, no load or store instructions)
13998 can start before the atomic operation completes. */
14000 emit_insn (gen_isync ());
14003 /* A subroutine of the atomic operation splitters. Jump to LABEL if
14004 COND is true. Mark the jump as unlikely to be taken. */
14007 emit_unlikely_jump (rtx cond
, rtx label
)
14009 rtx very_unlikely
= GEN_INT (REG_BR_PROB_BASE
/ 100 - 1);
14012 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
14013 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
14014 add_reg_note (x
, REG_BR_PROB
, very_unlikely
);
14017 /* A subroutine of the atomic operation splitters. Emit a load-locked
14018 instruction in MODE. */
14021 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
14023 rtx (*fn
) (rtx
, rtx
) = NULL
;
14024 if (mode
== SImode
)
14025 fn
= gen_load_locked_si
;
14026 else if (mode
== DImode
)
14027 fn
= gen_load_locked_di
;
14028 emit_insn (fn (reg
, mem
));
14031 /* A subroutine of the atomic operation splitters. Emit a store-conditional
14032 instruction in MODE. */
14035 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
14037 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
14038 if (mode
== SImode
)
14039 fn
= gen_store_conditional_si
;
14040 else if (mode
== DImode
)
14041 fn
= gen_store_conditional_di
;
14043 /* Emit sync before stwcx. to address PPC405 Erratum. */
14044 if (PPC405_ERRATUM77
)
14045 emit_insn (gen_memory_barrier ());
14047 emit_insn (fn (res
, mem
, val
));
14050 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
14051 to perform. MEM is the memory on which to operate. VAL is the second
14052 operand of the binary operator. BEFORE and AFTER are optional locations to
14053 return the value of MEM either before of after the operation. SCRATCH is
14054 a scratch register. */
14057 rs6000_split_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
14058 rtx before
, rtx after
, rtx scratch
)
14060 enum machine_mode mode
= GET_MODE (mem
);
14061 rtx label
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
14063 emit_insn (gen_lwsync ());
14065 label
= gen_label_rtx ();
14066 emit_label (label
);
14067 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
14069 if (before
== NULL_RTX
)
14071 emit_load_locked (mode
, before
, mem
);
14074 x
= gen_rtx_IOR (mode
,
14075 gen_rtx_NOT (mode
, before
),
14076 gen_rtx_NOT (mode
, val
));
14077 else if (code
== AND
)
14078 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (2, before
, val
), UNSPEC_AND
);
14080 x
= gen_rtx_fmt_ee (code
, mode
, before
, val
);
14082 if (after
!= NULL_RTX
)
14083 emit_insn (gen_rtx_SET (VOIDmode
, after
, copy_rtx (x
)));
14084 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, x
));
14086 emit_store_conditional (mode
, cond
, mem
, scratch
);
14088 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
14089 emit_unlikely_jump (x
, label
);
14091 emit_insn (gen_isync ());
14094 /* Expand an atomic compare and swap operation. MEM is the memory on which
14095 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
14096 value to be stored. SCRATCH is a scratch GPR. */
14099 rs6000_split_compare_and_swap (rtx retval
, rtx mem
, rtx oldval
, rtx newval
,
14102 enum machine_mode mode
= GET_MODE (mem
);
14103 rtx label1
, label2
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
14105 emit_insn (gen_lwsync ());
14107 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
14108 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
14109 emit_label (XEXP (label1
, 0));
14111 emit_load_locked (mode
, retval
, mem
);
14113 x
= gen_rtx_COMPARE (CCmode
, retval
, oldval
);
14114 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
14116 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
14117 emit_unlikely_jump (x
, label2
);
14119 emit_move_insn (scratch
, newval
);
14120 emit_store_conditional (mode
, cond
, mem
, scratch
);
14122 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
14123 emit_unlikely_jump (x
, label1
);
14125 emit_insn (gen_isync ());
14126 emit_label (XEXP (label2
, 0));
14129 /* Expand an atomic test and set operation. MEM is the memory on which
14130 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
14133 rs6000_split_lock_test_and_set (rtx retval
, rtx mem
, rtx val
, rtx scratch
)
14135 enum machine_mode mode
= GET_MODE (mem
);
14136 rtx label
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
14138 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
14139 emit_label (XEXP (label
, 0));
14141 emit_load_locked (mode
, retval
, mem
);
14142 emit_move_insn (scratch
, val
);
14143 emit_store_conditional (mode
, cond
, mem
, scratch
);
14145 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
14146 emit_unlikely_jump (x
, label
);
14148 emit_insn (gen_isync ());
14152 rs6000_expand_compare_and_swapqhi (rtx dst
, rtx mem
, rtx oldval
, rtx newval
)
14154 enum machine_mode mode
= GET_MODE (mem
);
14155 rtx addrSI
, align
, wdst
, shift
, mask
;
14156 HOST_WIDE_INT shift_mask
= mode
== QImode
? 0x18 : 0x10;
14157 HOST_WIDE_INT imask
= GET_MODE_MASK (mode
);
14159 /* Shift amount for subword relative to aligned word. */
14160 addrSI
= force_reg (GET_MODE (XEXP (mem
, 0)), XEXP (mem
, 0));
14161 addrSI
= force_reg (SImode
, gen_lowpart_common (SImode
, addrSI
));
14162 shift
= gen_reg_rtx (SImode
);
14163 emit_insn (gen_rlwinm (shift
, addrSI
, GEN_INT (3),
14164 GEN_INT (shift_mask
)));
14165 emit_insn (gen_xorsi3 (shift
, shift
, GEN_INT (shift_mask
)));
14167 /* Shift and mask old value into position within word. */
14168 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
14169 oldval
= expand_binop (SImode
, and_optab
,
14170 oldval
, GEN_INT (imask
), NULL_RTX
,
14171 1, OPTAB_LIB_WIDEN
);
14172 emit_insn (gen_ashlsi3 (oldval
, oldval
, shift
));
14174 /* Shift and mask new value into position within word. */
14175 newval
= convert_modes (SImode
, mode
, newval
, 1);
14176 newval
= expand_binop (SImode
, and_optab
,
14177 newval
, GEN_INT (imask
), NULL_RTX
,
14178 1, OPTAB_LIB_WIDEN
);
14179 emit_insn (gen_ashlsi3 (newval
, newval
, shift
));
14181 /* Mask for insertion. */
14182 mask
= gen_reg_rtx (SImode
);
14183 emit_move_insn (mask
, GEN_INT (imask
));
14184 emit_insn (gen_ashlsi3 (mask
, mask
, shift
));
14186 /* Address of aligned word containing subword. */
14187 align
= expand_binop (Pmode
, and_optab
, XEXP (mem
, 0), GEN_INT (-4),
14188 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
14189 mem
= change_address (mem
, SImode
, align
);
14190 set_mem_align (mem
, 32);
14191 MEM_VOLATILE_P (mem
) = 1;
14193 wdst
= gen_reg_rtx (SImode
);
14194 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst
, mask
,
14195 oldval
, newval
, mem
));
14197 /* Shift the result back. */
14198 emit_insn (gen_lshrsi3 (wdst
, wdst
, shift
));
14200 emit_move_insn (dst
, gen_lowpart (mode
, wdst
));
14204 rs6000_split_compare_and_swapqhi (rtx dest
, rtx mask
,
14205 rtx oldval
, rtx newval
, rtx mem
,
14208 rtx label1
, label2
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
14210 emit_insn (gen_lwsync ());
14211 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
14212 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
14213 emit_label (XEXP (label1
, 0));
14215 emit_load_locked (SImode
, scratch
, mem
);
14217 /* Mask subword within loaded value for comparison with oldval.
14218 Use UNSPEC_AND to avoid clobber.*/
14219 emit_insn (gen_rtx_SET (SImode
, dest
,
14220 gen_rtx_UNSPEC (SImode
,
14221 gen_rtvec (2, scratch
, mask
),
14224 x
= gen_rtx_COMPARE (CCmode
, dest
, oldval
);
14225 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
14227 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
14228 emit_unlikely_jump (x
, label2
);
14230 /* Clear subword within loaded value for insertion of new value. */
14231 emit_insn (gen_rtx_SET (SImode
, scratch
,
14232 gen_rtx_AND (SImode
,
14233 gen_rtx_NOT (SImode
, mask
), scratch
)));
14234 emit_insn (gen_iorsi3 (scratch
, scratch
, newval
));
14235 emit_store_conditional (SImode
, cond
, mem
, scratch
);
14237 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
14238 emit_unlikely_jump (x
, label1
);
14240 emit_insn (gen_isync ());
14241 emit_label (XEXP (label2
, 0));
14245 /* Emit instructions to move SRC to DST. Called by splitters for
14246 multi-register moves. It will emit at most one instruction for
14247 each register that is accessed; that is, it won't emit li/lis pairs
14248 (or equivalent for 64-bit code). One of SRC or DST must be a hard
14252 rs6000_split_multireg_move (rtx dst
, rtx src
)
14254 /* The register number of the first register being moved. */
14256 /* The mode that is to be moved. */
14257 enum machine_mode mode
;
14258 /* The mode that the move is being done in, and its size. */
14259 enum machine_mode reg_mode
;
14261 /* The number of registers that will be moved. */
14264 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
14265 mode
= GET_MODE (dst
);
14266 nregs
= hard_regno_nregs
[reg
][mode
];
14267 if (FP_REGNO_P (reg
))
14268 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
14269 ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? DFmode
: SFmode
);
14270 else if (ALTIVEC_REGNO_P (reg
))
14271 reg_mode
= V16QImode
;
14272 else if (TARGET_E500_DOUBLE
&& mode
== TFmode
)
14275 reg_mode
= word_mode
;
14276 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
14278 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
14280 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
14282 /* Move register range backwards, if we might have destructive
14285 for (i
= nregs
- 1; i
>= 0; i
--)
14286 emit_insn (gen_rtx_SET (VOIDmode
,
14287 simplify_gen_subreg (reg_mode
, dst
, mode
,
14288 i
* reg_mode_size
),
14289 simplify_gen_subreg (reg_mode
, src
, mode
,
14290 i
* reg_mode_size
)));
14296 bool used_update
= false;
14298 if (MEM_P (src
) && INT_REGNO_P (reg
))
14302 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
14303 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
14306 breg
= XEXP (XEXP (src
, 0), 0);
14307 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
14308 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
14309 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
14310 emit_insn (TARGET_32BIT
14311 ? gen_addsi3 (breg
, breg
, delta_rtx
)
14312 : gen_adddi3 (breg
, breg
, delta_rtx
));
14313 src
= replace_equiv_address (src
, breg
);
14315 else if (! rs6000_offsettable_memref_p (src
))
14318 basereg
= gen_rtx_REG (Pmode
, reg
);
14319 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
14320 src
= replace_equiv_address (src
, basereg
);
14323 breg
= XEXP (src
, 0);
14324 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
14325 breg
= XEXP (breg
, 0);
14327 /* If the base register we are using to address memory is
14328 also a destination reg, then change that register last. */
14330 && REGNO (breg
) >= REGNO (dst
)
14331 && REGNO (breg
) < REGNO (dst
) + nregs
)
14332 j
= REGNO (breg
) - REGNO (dst
);
14335 if (GET_CODE (dst
) == MEM
&& INT_REGNO_P (reg
))
14339 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
14340 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
14343 breg
= XEXP (XEXP (dst
, 0), 0);
14344 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
14345 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
14346 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
14348 /* We have to update the breg before doing the store.
14349 Use store with update, if available. */
14353 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
14354 emit_insn (TARGET_32BIT
14355 ? (TARGET_POWERPC64
14356 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
14357 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
14358 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
14359 used_update
= true;
14362 emit_insn (TARGET_32BIT
14363 ? gen_addsi3 (breg
, breg
, delta_rtx
)
14364 : gen_adddi3 (breg
, breg
, delta_rtx
));
14365 dst
= replace_equiv_address (dst
, breg
);
14368 gcc_assert (rs6000_offsettable_memref_p (dst
));
14371 for (i
= 0; i
< nregs
; i
++)
14373 /* Calculate index to next subword. */
14378 /* If compiler already emitted move of first word by
14379 store with update, no need to do anything. */
14380 if (j
== 0 && used_update
)
14383 emit_insn (gen_rtx_SET (VOIDmode
,
14384 simplify_gen_subreg (reg_mode
, dst
, mode
,
14385 j
* reg_mode_size
),
14386 simplify_gen_subreg (reg_mode
, src
, mode
,
14387 j
* reg_mode_size
)));
14393 /* This page contains routines that are used to determine what the
14394 function prologue and epilogue code will do and write them out. */
14396 /* Return the first fixed-point register that is required to be
14397 saved. 32 if none. */
14400 first_reg_to_save (void)
14404 /* Find lowest numbered live register. */
14405 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
14406 if (df_regs_ever_live_p (first_reg
)
14407 && (! call_used_regs
[first_reg
]
14408 || (first_reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
14409 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
14410 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
14411 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
)))))
14416 && crtl
->uses_pic_offset_table
14417 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
14418 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
14424 /* Similar, for FP regs. */
14427 first_fp_reg_to_save (void)
14431 /* Find lowest numbered live register. */
14432 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
14433 if (df_regs_ever_live_p (first_reg
))
14439 /* Similar, for AltiVec regs. */
14442 first_altivec_reg_to_save (void)
14446 /* Stack frame remains as is unless we are in AltiVec ABI. */
14447 if (! TARGET_ALTIVEC_ABI
)
14448 return LAST_ALTIVEC_REGNO
+ 1;
14450 /* On Darwin, the unwind routines are compiled without
14451 TARGET_ALTIVEC, and use save_world to save/restore the
14452 altivec registers when necessary. */
14453 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
14454 && ! TARGET_ALTIVEC
)
14455 return FIRST_ALTIVEC_REGNO
+ 20;
14457 /* Find lowest numbered live register. */
14458 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
14459 if (df_regs_ever_live_p (i
))
14465 /* Return a 32-bit mask of the AltiVec registers we need to set in
14466 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
14467 the 32-bit word is 0. */
14469 static unsigned int
14470 compute_vrsave_mask (void)
14472 unsigned int i
, mask
= 0;
14474 /* On Darwin, the unwind routines are compiled without
14475 TARGET_ALTIVEC, and use save_world to save/restore the
14476 call-saved altivec registers when necessary. */
14477 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
14478 && ! TARGET_ALTIVEC
)
14481 /* First, find out if we use _any_ altivec registers. */
14482 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
14483 if (df_regs_ever_live_p (i
))
14484 mask
|= ALTIVEC_REG_BIT (i
);
14489 /* Next, remove the argument registers from the set. These must
14490 be in the VRSAVE mask set by the caller, so we don't need to add
14491 them in again. More importantly, the mask we compute here is
14492 used to generate CLOBBERs in the set_vrsave insn, and we do not
14493 wish the argument registers to die. */
14494 for (i
= crtl
->args
.info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
14495 mask
&= ~ALTIVEC_REG_BIT (i
);
14497 /* Similarly, remove the return value from the set. */
14500 diddle_return_value (is_altivec_return_reg
, &yes
);
14502 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
14508 /* For a very restricted set of circumstances, we can cut down the
14509 size of prologues/epilogues by calling our own save/restore-the-world
14513 compute_save_world_info (rs6000_stack_t
*info_ptr
)
14515 info_ptr
->world_save_p
= 1;
14516 info_ptr
->world_save_p
14517 = (WORLD_SAVE_P (info_ptr
)
14518 && DEFAULT_ABI
== ABI_DARWIN
14519 && ! (cfun
->calls_setjmp
&& flag_exceptions
)
14520 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
14521 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
14522 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
14523 && info_ptr
->cr_save_p
);
14525 /* This will not work in conjunction with sibcalls. Make sure there
14526 are none. (This check is expensive, but seldom executed.) */
14527 if (WORLD_SAVE_P (info_ptr
))
14530 for ( insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
14531 if ( GET_CODE (insn
) == CALL_INSN
14532 && SIBLING_CALL_P (insn
))
14534 info_ptr
->world_save_p
= 0;
14539 if (WORLD_SAVE_P (info_ptr
))
14541 /* Even if we're not touching VRsave, make sure there's room on the
14542 stack for it, if it looks like we're calling SAVE_WORLD, which
14543 will attempt to save it. */
14544 info_ptr
->vrsave_size
= 4;
14546 /* If we are going to save the world, we need to save the link register too. */
14547 info_ptr
->lr_save_p
= 1;
14549 /* "Save" the VRsave register too if we're saving the world. */
14550 if (info_ptr
->vrsave_mask
== 0)
14551 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
14553 /* Because the Darwin register save/restore routines only handle
14554 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
14556 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
14557 && (info_ptr
->first_altivec_reg_save
14558 >= FIRST_SAVED_ALTIVEC_REGNO
));
14565 is_altivec_return_reg (rtx reg
, void *xyes
)
14567 bool *yes
= (bool *) xyes
;
14568 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
14573 /* Calculate the stack information for the current function. This is
14574 complicated by having two separate calling sequences, the AIX calling
14575 sequence and the V.4 calling sequence.
14577 AIX (and Darwin/Mac OS X) stack frames look like:
14579 SP----> +---------------------------------------+
14580 | back chain to caller | 0 0
14581 +---------------------------------------+
14582 | saved CR | 4 8 (8-11)
14583 +---------------------------------------+
14585 +---------------------------------------+
14586 | reserved for compilers | 12 24
14587 +---------------------------------------+
14588 | reserved for binders | 16 32
14589 +---------------------------------------+
14590 | saved TOC pointer | 20 40
14591 +---------------------------------------+
14592 | Parameter save area (P) | 24 48
14593 +---------------------------------------+
14594 | Alloca space (A) | 24+P etc.
14595 +---------------------------------------+
14596 | Local variable space (L) | 24+P+A
14597 +---------------------------------------+
14598 | Float/int conversion temporary (X) | 24+P+A+L
14599 +---------------------------------------+
14600 | Save area for AltiVec registers (W) | 24+P+A+L+X
14601 +---------------------------------------+
14602 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
14603 +---------------------------------------+
14604 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
14605 +---------------------------------------+
14606 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
14607 +---------------------------------------+
14608 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
14609 +---------------------------------------+
14610 old SP->| back chain to caller's caller |
14611 +---------------------------------------+
14613 The required alignment for AIX configurations is two words (i.e., 8
14617 V.4 stack frames look like:
14619 SP----> +---------------------------------------+
14620 | back chain to caller | 0
14621 +---------------------------------------+
14622 | caller's saved LR | 4
14623 +---------------------------------------+
14624 | Parameter save area (P) | 8
14625 +---------------------------------------+
14626 | Alloca space (A) | 8+P
14627 +---------------------------------------+
14628 | Varargs save area (V) | 8+P+A
14629 +---------------------------------------+
14630 | Local variable space (L) | 8+P+A+V
14631 +---------------------------------------+
14632 | Float/int conversion temporary (X) | 8+P+A+V+L
14633 +---------------------------------------+
14634 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
14635 +---------------------------------------+
14636 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
14637 +---------------------------------------+
14638 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
14639 +---------------------------------------+
14640 | SPE: area for 64-bit GP registers |
14641 +---------------------------------------+
14642 | SPE alignment padding |
14643 +---------------------------------------+
14644 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
14645 +---------------------------------------+
14646 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
14647 +---------------------------------------+
14648 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
14649 +---------------------------------------+
14650 old SP->| back chain to caller's caller |
14651 +---------------------------------------+
14653 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
14654 given. (But note below and in sysv4.h that we require only 8 and
14655 may round up the size of our stack frame anyways. The historical
14656 reason is early versions of powerpc-linux which didn't properly
14657 align the stack at program startup. A happy side-effect is that
14658 -mno-eabi libraries can be used with -meabi programs.)
14660 The EABI configuration defaults to the V.4 layout. However,
14661 the stack alignment requirements may differ. If -mno-eabi is not
14662 given, the required stack alignment is 8 bytes; if -mno-eabi is
14663 given, the required alignment is 16 bytes. (But see V.4 comment
14666 #ifndef ABI_STACK_BOUNDARY
14667 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
14670 static rs6000_stack_t
*
14671 rs6000_stack_info (void)
14673 static rs6000_stack_t info
;
14674 rs6000_stack_t
*info_ptr
= &info
;
14675 int reg_size
= TARGET_32BIT
? 4 : 8;
14679 HOST_WIDE_INT non_fixed_size
;
14681 memset (&info
, 0, sizeof (info
));
14685 /* Cache value so we don't rescan instruction chain over and over. */
14686 if (cfun
->machine
->insn_chain_scanned_p
== 0)
14687 cfun
->machine
->insn_chain_scanned_p
14688 = spe_func_has_64bit_regs_p () + 1;
14689 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
14692 /* Select which calling sequence. */
14693 info_ptr
->abi
= DEFAULT_ABI
;
14695 /* Calculate which registers need to be saved & save area size. */
14696 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
14697 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
14698 even if it currently looks like we won't. Reload may need it to
14699 get at a constant; if so, it will have already created a constant
14700 pool entry for it. */
14701 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
14702 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
14703 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
14704 && crtl
->uses_const_pool
14705 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
14706 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
14708 first_gp
= info_ptr
->first_gp_reg_save
;
14710 info_ptr
->gp_size
= reg_size
* (32 - first_gp
);
14712 /* For the SPE, we have an additional upper 32-bits on each GPR.
14713 Ideally we should save the entire 64-bits only when the upper
14714 half is used in SIMD instructions. Since we only record
14715 registers live (not the size they are used in), this proves
14716 difficult because we'd have to traverse the instruction chain at
14717 the right time, taking reload into account. This is a real pain,
14718 so we opt to save the GPRs in 64-bits always if but one register
14719 gets used in 64-bits. Otherwise, all the registers in the frame
14720 get saved in 32-bits.
14722 So... since when we save all GPRs (except the SP) in 64-bits, the
14723 traditional GP save area will be empty. */
14724 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
14725 info_ptr
->gp_size
= 0;
14727 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
14728 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
14730 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
14731 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
14732 - info_ptr
->first_altivec_reg_save
);
14734 /* Does this function call anything? */
14735 info_ptr
->calls_p
= (! current_function_is_leaf
14736 || cfun
->machine
->ra_needs_full_frame
);
14738 /* Determine if we need to save the link register. */
14739 if ((DEFAULT_ABI
== ABI_AIX
14741 && !TARGET_PROFILE_KERNEL
)
14742 #ifdef TARGET_RELOCATABLE
14743 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
14745 || (info_ptr
->first_fp_reg_save
!= 64
14746 && !FP_SAVE_INLINE (info_ptr
->first_fp_reg_save
))
14747 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
14748 || info_ptr
->calls_p
14749 || rs6000_ra_ever_killed ())
14751 info_ptr
->lr_save_p
= 1;
14752 df_set_regs_ever_live (LR_REGNO
, true);
14755 /* Determine if we need to save the condition code registers. */
14756 if (df_regs_ever_live_p (CR2_REGNO
)
14757 || df_regs_ever_live_p (CR3_REGNO
)
14758 || df_regs_ever_live_p (CR4_REGNO
))
14760 info_ptr
->cr_save_p
= 1;
14761 if (DEFAULT_ABI
== ABI_V4
)
14762 info_ptr
->cr_size
= reg_size
;
14765 /* If the current function calls __builtin_eh_return, then we need
14766 to allocate stack space for registers that will hold data for
14767 the exception handler. */
14768 if (crtl
->calls_eh_return
)
14771 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
14774 /* SPE saves EH registers in 64-bits. */
14775 ehrd_size
= i
* (TARGET_SPE_ABI
14776 && info_ptr
->spe_64bit_regs_used
!= 0
14777 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
14782 /* Determine various sizes. */
14783 info_ptr
->reg_size
= reg_size
;
14784 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
14785 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
14786 info_ptr
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
14787 TARGET_ALTIVEC
? 16 : 8);
14788 if (FRAME_GROWS_DOWNWARD
)
14789 info_ptr
->vars_size
14790 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
14791 + info_ptr
->parm_size
,
14792 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
14793 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
14794 + info_ptr
->parm_size
);
14796 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
14797 info_ptr
->spe_gp_size
= 8 * (32 - first_gp
);
14799 info_ptr
->spe_gp_size
= 0;
14801 if (TARGET_ALTIVEC_ABI
)
14802 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
14804 info_ptr
->vrsave_mask
= 0;
14806 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
14807 info_ptr
->vrsave_size
= 4;
14809 info_ptr
->vrsave_size
= 0;
14811 compute_save_world_info (info_ptr
);
14813 /* Calculate the offsets. */
14814 switch (DEFAULT_ABI
)
14818 gcc_unreachable ();
14822 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
14823 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
14825 if (TARGET_ALTIVEC_ABI
)
14827 info_ptr
->vrsave_save_offset
14828 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
14830 /* Align stack so vector save area is on a quadword boundary.
14831 The padding goes above the vectors. */
14832 if (info_ptr
->altivec_size
!= 0)
14833 info_ptr
->altivec_padding_size
14834 = info_ptr
->vrsave_save_offset
& 0xF;
14836 info_ptr
->altivec_padding_size
= 0;
14838 info_ptr
->altivec_save_offset
14839 = info_ptr
->vrsave_save_offset
14840 - info_ptr
->altivec_padding_size
14841 - info_ptr
->altivec_size
;
14842 gcc_assert (info_ptr
->altivec_size
== 0
14843 || info_ptr
->altivec_save_offset
% 16 == 0);
14845 /* Adjust for AltiVec case. */
14846 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
14849 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
14850 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
14851 info_ptr
->lr_save_offset
= 2*reg_size
;
14855 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
14856 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
14857 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
14859 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
14861 /* Align stack so SPE GPR save area is aligned on a
14862 double-word boundary. */
14863 if (info_ptr
->spe_gp_size
!= 0 && info_ptr
->cr_save_offset
!= 0)
14864 info_ptr
->spe_padding_size
14865 = 8 - (-info_ptr
->cr_save_offset
% 8);
14867 info_ptr
->spe_padding_size
= 0;
14869 info_ptr
->spe_gp_save_offset
14870 = info_ptr
->cr_save_offset
14871 - info_ptr
->spe_padding_size
14872 - info_ptr
->spe_gp_size
;
14874 /* Adjust for SPE case. */
14875 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
14877 else if (TARGET_ALTIVEC_ABI
)
14879 info_ptr
->vrsave_save_offset
14880 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
14882 /* Align stack so vector save area is on a quadword boundary. */
14883 if (info_ptr
->altivec_size
!= 0)
14884 info_ptr
->altivec_padding_size
14885 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
14887 info_ptr
->altivec_padding_size
= 0;
14889 info_ptr
->altivec_save_offset
14890 = info_ptr
->vrsave_save_offset
14891 - info_ptr
->altivec_padding_size
14892 - info_ptr
->altivec_size
;
14894 /* Adjust for AltiVec case. */
14895 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
14898 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
14899 info_ptr
->ehrd_offset
-= ehrd_size
;
14900 info_ptr
->lr_save_offset
= reg_size
;
14904 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
14905 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
14906 + info_ptr
->gp_size
14907 + info_ptr
->altivec_size
14908 + info_ptr
->altivec_padding_size
14909 + info_ptr
->spe_gp_size
14910 + info_ptr
->spe_padding_size
14912 + info_ptr
->cr_size
14913 + info_ptr
->vrsave_size
,
14916 non_fixed_size
= (info_ptr
->vars_size
14917 + info_ptr
->parm_size
14918 + info_ptr
->save_size
);
14920 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
14921 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
14923 /* Determine if we need to allocate any stack frame:
14925 For AIX we need to push the stack if a frame pointer is needed
14926 (because the stack might be dynamically adjusted), if we are
14927 debugging, if we make calls, or if the sum of fp_save, gp_save,
14928 and local variables are more than the space needed to save all
14929 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
14930 + 18*8 = 288 (GPR13 reserved).
14932 For V.4 we don't have the stack cushion that AIX uses, but assume
14933 that the debugger can handle stackless frames. */
14935 if (info_ptr
->calls_p
)
14936 info_ptr
->push_p
= 1;
14938 else if (DEFAULT_ABI
== ABI_V4
)
14939 info_ptr
->push_p
= non_fixed_size
!= 0;
14941 else if (frame_pointer_needed
)
14942 info_ptr
->push_p
= 1;
14944 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
14945 info_ptr
->push_p
= 1;
14948 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
14950 /* Zero offsets if we're not saving those registers. */
14951 if (info_ptr
->fp_size
== 0)
14952 info_ptr
->fp_save_offset
= 0;
14954 if (info_ptr
->gp_size
== 0)
14955 info_ptr
->gp_save_offset
= 0;
14957 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
14958 info_ptr
->altivec_save_offset
= 0;
14960 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->vrsave_mask
== 0)
14961 info_ptr
->vrsave_save_offset
= 0;
14963 if (! TARGET_SPE_ABI
14964 || info_ptr
->spe_64bit_regs_used
== 0
14965 || info_ptr
->spe_gp_size
== 0)
14966 info_ptr
->spe_gp_save_offset
= 0;
14968 if (! info_ptr
->lr_save_p
)
14969 info_ptr
->lr_save_offset
= 0;
14971 if (! info_ptr
->cr_save_p
)
14972 info_ptr
->cr_save_offset
= 0;
14977 /* Return true if the current function uses any GPRs in 64-bit SIMD
14981 spe_func_has_64bit_regs_p (void)
14985 /* Functions that save and restore all the call-saved registers will
14986 need to save/restore the registers in 64-bits. */
14987 if (crtl
->calls_eh_return
14988 || cfun
->calls_setjmp
14989 || crtl
->has_nonlocal_goto
)
14992 insns
= get_insns ();
14994 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
15000 /* FIXME: This should be implemented with attributes...
15002 (set_attr "spe64" "true")....then,
15003 if (get_spe64(insn)) return true;
15005 It's the only reliable way to do the stuff below. */
15007 i
= PATTERN (insn
);
15008 if (GET_CODE (i
) == SET
)
15010 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
15012 if (SPE_VECTOR_MODE (mode
))
15014 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
))
15024 debug_stack_info (rs6000_stack_t
*info
)
15026 const char *abi_string
;
15029 info
= rs6000_stack_info ();
15031 fprintf (stderr
, "\nStack information for function %s:\n",
15032 ((current_function_decl
&& DECL_NAME (current_function_decl
))
15033 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
15038 default: abi_string
= "Unknown"; break;
15039 case ABI_NONE
: abi_string
= "NONE"; break;
15040 case ABI_AIX
: abi_string
= "AIX"; break;
15041 case ABI_DARWIN
: abi_string
= "Darwin"; break;
15042 case ABI_V4
: abi_string
= "V.4"; break;
15045 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
15047 if (TARGET_ALTIVEC_ABI
)
15048 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
15050 if (TARGET_SPE_ABI
)
15051 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
15053 if (info
->first_gp_reg_save
!= 32)
15054 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
15056 if (info
->first_fp_reg_save
!= 64)
15057 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
15059 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
15060 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
15061 info
->first_altivec_reg_save
);
15063 if (info
->lr_save_p
)
15064 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
15066 if (info
->cr_save_p
)
15067 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
15069 if (info
->vrsave_mask
)
15070 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
15073 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
15076 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
15078 if (info
->gp_save_offset
)
15079 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
15081 if (info
->fp_save_offset
)
15082 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
15084 if (info
->altivec_save_offset
)
15085 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
15086 info
->altivec_save_offset
);
15088 if (info
->spe_gp_save_offset
)
15089 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
15090 info
->spe_gp_save_offset
);
15092 if (info
->vrsave_save_offset
)
15093 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
15094 info
->vrsave_save_offset
);
15096 if (info
->lr_save_offset
)
15097 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
15099 if (info
->cr_save_offset
)
15100 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
15102 if (info
->varargs_save_offset
)
15103 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
15105 if (info
->total_size
)
15106 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
15109 if (info
->vars_size
)
15110 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
15113 if (info
->parm_size
)
15114 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
15116 if (info
->fixed_size
)
15117 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
15120 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
15122 if (info
->spe_gp_size
)
15123 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
15126 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
15128 if (info
->altivec_size
)
15129 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
15131 if (info
->vrsave_size
)
15132 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
15134 if (info
->altivec_padding_size
)
15135 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
15136 info
->altivec_padding_size
);
15138 if (info
->spe_padding_size
)
15139 fprintf (stderr
, "\tspe_padding_size = %5d\n",
15140 info
->spe_padding_size
);
15143 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
15145 if (info
->save_size
)
15146 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
15148 if (info
->reg_size
!= 4)
15149 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
15151 fprintf (stderr
, "\n");
15155 rs6000_return_addr (int count
, rtx frame
)
15157 /* Currently we don't optimize very well between prolog and body
15158 code and for PIC code the code can be actually quite bad, so
15159 don't try to be too clever here. */
15160 if (count
!= 0 || (DEFAULT_ABI
!= ABI_AIX
&& flag_pic
))
15162 cfun
->machine
->ra_needs_full_frame
= 1;
15169 plus_constant (copy_to_reg
15170 (gen_rtx_MEM (Pmode
,
15171 memory_address (Pmode
, frame
))),
15172 RETURN_ADDRESS_OFFSET
)));
15175 cfun
->machine
->ra_need_lr
= 1;
15176 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
15179 /* Say whether a function is a candidate for sibcall handling or not.
15180 We do not allow indirect calls to be optimized into sibling calls.
15181 Also, we can't do it if there are any vector parameters; there's
15182 nowhere to put the VRsave code so it works; note that functions with
15183 vector parameters are required to have a prototype, so the argument
15184 type info must be available here. (The tail recursion case can work
15185 with vector parameters, but there's no way to distinguish here.) */
15187 rs6000_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
15192 if (TARGET_ALTIVEC_VRSAVE
)
15194 for (type
= TYPE_ARG_TYPES (TREE_TYPE (decl
));
15195 type
; type
= TREE_CHAIN (type
))
15197 if (TREE_CODE (TREE_VALUE (type
)) == VECTOR_TYPE
)
15201 if (DEFAULT_ABI
== ABI_DARWIN
15202 || ((*targetm
.binds_local_p
) (decl
)
15203 && (DEFAULT_ABI
!= ABI_AIX
|| !DECL_EXTERNAL (decl
))))
15205 tree attr_list
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
15207 if (!lookup_attribute ("longcall", attr_list
)
15208 || lookup_attribute ("shortcall", attr_list
))
15215 /* NULL if INSN insn is valid within a low-overhead loop.
15216 Otherwise return why doloop cannot be applied.
15217 PowerPC uses the COUNT register for branch on table instructions. */
15219 static const char *
15220 rs6000_invalid_within_doloop (const_rtx insn
)
15223 return "Function call in the loop.";
15226 && (GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
15227 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
))
15228 return "Computed branch in the loop.";
15234 rs6000_ra_ever_killed (void)
15240 if (cfun
->is_thunk
)
15243 /* regs_ever_live has LR marked as used if any sibcalls are present,
15244 but this should not force saving and restoring in the
15245 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
15246 clobbers LR, so that is inappropriate. */
15248 /* Also, the prologue can generate a store into LR that
15249 doesn't really count, like this:
15252 bcl to set PIC register
15256 When we're called from the epilogue, we need to avoid counting
15257 this as a store. */
15259 push_topmost_sequence ();
15260 top
= get_insns ();
15261 pop_topmost_sequence ();
15262 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
15264 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
15270 if (!SIBLING_CALL_P (insn
))
15273 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
15275 else if (set_of (reg
, insn
) != NULL_RTX
15276 && !prologue_epilogue_contains (insn
))
15283 /* Emit instructions needed to load the TOC register.
15284 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
15285 a constant pool; or for SVR4 -fpic. */
15288 rs6000_emit_load_toc_table (int fromprolog
)
15291 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
15293 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
)
15296 rtx lab
, tmp1
, tmp2
, got
;
15298 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
15299 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
15301 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
15303 got
= rs6000_got_sym ();
15304 tmp1
= tmp2
= dest
;
15307 tmp1
= gen_reg_rtx (Pmode
);
15308 tmp2
= gen_reg_rtx (Pmode
);
15310 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
15311 emit_move_insn (tmp1
,
15312 gen_rtx_REG (Pmode
, LR_REGNO
));
15313 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
15314 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
15316 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
15318 emit_insn (gen_load_toc_v4_pic_si ());
15319 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
15321 else if (TARGET_ELF
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
== 2)
15324 rtx temp0
= (fromprolog
15325 ? gen_rtx_REG (Pmode
, 0)
15326 : gen_reg_rtx (Pmode
));
15332 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
15333 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
15335 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
15336 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
15338 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
15339 emit_move_insn (dest
,
15340 gen_rtx_REG (Pmode
, LR_REGNO
));
15341 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
15347 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
15348 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
));
15349 emit_move_insn (dest
,
15350 gen_rtx_REG (Pmode
, LR_REGNO
));
15351 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
15353 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
15355 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
15357 /* This is for AIX code running in non-PIC ELF32. */
15360 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
15361 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
15363 emit_insn (gen_elf_high (dest
, realsym
));
15364 emit_insn (gen_elf_low (dest
, dest
, realsym
));
15368 gcc_assert (DEFAULT_ABI
== ABI_AIX
);
15371 emit_insn (gen_load_toc_aix_si (dest
));
15373 emit_insn (gen_load_toc_aix_di (dest
));
15377 /* Emit instructions to restore the link register after determining where
15378 its value has been stored. */
15381 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
15383 rs6000_stack_t
*info
= rs6000_stack_info ();
15386 operands
[0] = source
;
15387 operands
[1] = scratch
;
15389 if (info
->lr_save_p
)
15391 rtx frame_rtx
= stack_pointer_rtx
;
15392 HOST_WIDE_INT sp_offset
= 0;
15395 if (frame_pointer_needed
15396 || cfun
->calls_alloca
15397 || info
->total_size
> 32767)
15399 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
15400 emit_move_insn (operands
[1], tmp
);
15401 frame_rtx
= operands
[1];
15403 else if (info
->push_p
)
15404 sp_offset
= info
->total_size
;
15406 tmp
= plus_constant (frame_rtx
, info
->lr_save_offset
+ sp_offset
);
15407 tmp
= gen_frame_mem (Pmode
, tmp
);
15408 emit_move_insn (tmp
, operands
[0]);
15411 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
15414 static GTY(()) alias_set_type set
= -1;
15417 get_TOC_alias_set (void)
15420 set
= new_alias_set ();
15424 /* This returns nonzero if the current function uses the TOC. This is
15425 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
15426 is generated by the ABI_V4 load_toc_* patterns. */
15433 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
15436 rtx pat
= PATTERN (insn
);
15439 if (GET_CODE (pat
) == PARALLEL
)
15440 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
15442 rtx sub
= XVECEXP (pat
, 0, i
);
15443 if (GET_CODE (sub
) == USE
)
15445 sub
= XEXP (sub
, 0);
15446 if (GET_CODE (sub
) == UNSPEC
15447 && XINT (sub
, 1) == UNSPEC_TOC
)
15457 create_TOC_reference (rtx symbol
)
15459 if (!can_create_pseudo_p ())
15460 df_set_regs_ever_live (TOC_REGISTER
, true);
15461 return gen_rtx_PLUS (Pmode
,
15462 gen_rtx_REG (Pmode
, TOC_REGISTER
),
15463 gen_rtx_CONST (Pmode
,
15464 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, symbol
), UNSPEC_TOCREL
)));
15467 /* If _Unwind_* has been called from within the same module,
15468 toc register is not guaranteed to be saved to 40(1) on function
15469 entry. Save it there in that case. */
15472 rs6000_aix_emit_builtin_unwind_init (void)
15475 rtx stack_top
= gen_reg_rtx (Pmode
);
15476 rtx opcode_addr
= gen_reg_rtx (Pmode
);
15477 rtx opcode
= gen_reg_rtx (SImode
);
15478 rtx tocompare
= gen_reg_rtx (SImode
);
15479 rtx no_toc_save_needed
= gen_label_rtx ();
15481 mem
= gen_frame_mem (Pmode
, hard_frame_pointer_rtx
);
15482 emit_move_insn (stack_top
, mem
);
15484 mem
= gen_frame_mem (Pmode
,
15485 gen_rtx_PLUS (Pmode
, stack_top
,
15486 GEN_INT (2 * GET_MODE_SIZE (Pmode
))));
15487 emit_move_insn (opcode_addr
, mem
);
15488 emit_move_insn (opcode
, gen_rtx_MEM (SImode
, opcode_addr
));
15489 emit_move_insn (tocompare
, gen_int_mode (TARGET_32BIT
? 0x80410014
15490 : 0xE8410028, SImode
));
15492 do_compare_rtx_and_jump (opcode
, tocompare
, EQ
, 1,
15493 SImode
, NULL_RTX
, NULL_RTX
,
15494 no_toc_save_needed
);
15496 mem
= gen_frame_mem (Pmode
,
15497 gen_rtx_PLUS (Pmode
, stack_top
,
15498 GEN_INT (5 * GET_MODE_SIZE (Pmode
))));
15499 emit_move_insn (mem
, gen_rtx_REG (Pmode
, 2));
15500 emit_label (no_toc_save_needed
);
15503 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
15504 and the change to the stack pointer. */
15507 rs6000_emit_stack_tie (void)
15509 rtx mem
= gen_frame_mem (BLKmode
,
15510 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
15512 emit_insn (gen_stack_tie (mem
));
15515 /* Emit the correct code for allocating stack space, as insns.
15516 If COPY_R12, make sure a copy of the old frame is left in r12.
15517 If COPY_R11, make sure a copy of the old frame is left in r11,
15518 in preference to r12 if COPY_R12.
15519 The generated code may use hard register 0 as a temporary. */
15522 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, int copy_r12
, int copy_r11
)
15525 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
15526 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
15527 rtx todec
= gen_int_mode (-size
, Pmode
);
15530 if (INTVAL (todec
) != -size
)
15532 warning (0, "stack frame too large");
15533 emit_insn (gen_trap ());
15537 if (crtl
->limit_stack
)
15539 if (REG_P (stack_limit_rtx
)
15540 && REGNO (stack_limit_rtx
) > 1
15541 && REGNO (stack_limit_rtx
) <= 31)
15543 emit_insn (TARGET_32BIT
15544 ? gen_addsi3 (tmp_reg
,
15547 : gen_adddi3 (tmp_reg
,
15551 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
15554 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
15556 && DEFAULT_ABI
== ABI_V4
)
15558 rtx toload
= gen_rtx_CONST (VOIDmode
,
15559 gen_rtx_PLUS (Pmode
,
15563 emit_insn (gen_elf_high (tmp_reg
, toload
));
15564 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
15565 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
15569 warning (0, "stack limit expression is not supported");
15572 if (copy_r12
|| copy_r11
)
15573 emit_move_insn (copy_r11
15574 ? gen_rtx_REG (Pmode
, 11)
15575 : gen_rtx_REG (Pmode
, 12),
15580 /* Need a note here so that try_split doesn't get confused. */
15581 if (get_last_insn () == NULL_RTX
)
15582 emit_note (NOTE_INSN_DELETED
);
15583 insn
= emit_move_insn (tmp_reg
, todec
);
15584 try_split (PATTERN (insn
), insn
, 0);
15588 insn
= emit_insn (TARGET_32BIT
15589 ? gen_movsi_update_stack (stack_reg
, stack_reg
,
15591 : gen_movdi_di_update_stack (stack_reg
, stack_reg
,
15592 todec
, stack_reg
));
15593 /* Since we didn't use gen_frame_mem to generate the MEM, grab
15594 it now and set the alias set/attributes. The above gen_*_update
15595 calls will generate a PARALLEL with the MEM set being the first
15597 par
= PATTERN (insn
);
15598 gcc_assert (GET_CODE (par
) == PARALLEL
);
15599 set
= XVECEXP (par
, 0, 0);
15600 gcc_assert (GET_CODE (set
) == SET
);
15601 mem
= SET_DEST (set
);
15602 gcc_assert (MEM_P (mem
));
15603 MEM_NOTRAP_P (mem
) = 1;
15604 set_mem_alias_set (mem
, get_frame_alias_set ());
15606 RTX_FRAME_RELATED_P (insn
) = 1;
15607 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
15608 gen_rtx_SET (VOIDmode
, stack_reg
,
15609 gen_rtx_PLUS (Pmode
, stack_reg
,
15610 GEN_INT (-size
))));
15613 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
15614 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
15615 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
15616 deduce these equivalences by itself so it wasn't necessary to hold
15617 its hand so much. */
15620 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
15621 rtx reg2
, rtx rreg
)
15625 /* copy_rtx will not make unique copies of registers, so we need to
15626 ensure we don't have unwanted sharing here. */
15628 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
15631 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
15633 real
= copy_rtx (PATTERN (insn
));
15635 if (reg2
!= NULL_RTX
)
15636 real
= replace_rtx (real
, reg2
, rreg
);
15638 real
= replace_rtx (real
, reg
,
15639 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
15640 STACK_POINTER_REGNUM
),
15643 /* We expect that 'real' is either a SET or a PARALLEL containing
15644 SETs (and possibly other stuff). In a PARALLEL, all the SETs
15645 are important so they all have to be marked RTX_FRAME_RELATED_P. */
15647 if (GET_CODE (real
) == SET
)
15651 temp
= simplify_rtx (SET_SRC (set
));
15653 SET_SRC (set
) = temp
;
15654 temp
= simplify_rtx (SET_DEST (set
));
15656 SET_DEST (set
) = temp
;
15657 if (GET_CODE (SET_DEST (set
)) == MEM
)
15659 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
15661 XEXP (SET_DEST (set
), 0) = temp
;
15668 gcc_assert (GET_CODE (real
) == PARALLEL
);
15669 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
15670 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
15672 rtx set
= XVECEXP (real
, 0, i
);
15674 temp
= simplify_rtx (SET_SRC (set
));
15676 SET_SRC (set
) = temp
;
15677 temp
= simplify_rtx (SET_DEST (set
));
15679 SET_DEST (set
) = temp
;
15680 if (GET_CODE (SET_DEST (set
)) == MEM
)
15682 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
15684 XEXP (SET_DEST (set
), 0) = temp
;
15686 RTX_FRAME_RELATED_P (set
) = 1;
15690 RTX_FRAME_RELATED_P (insn
) = 1;
15691 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, real
);
15694 /* Returns an insn that has a vrsave set operation with the
15695 appropriate CLOBBERs. */
15698 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
15701 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
15702 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
15705 = gen_rtx_SET (VOIDmode
,
15707 gen_rtx_UNSPEC_VOLATILE (SImode
,
15708 gen_rtvec (2, reg
, vrsave
),
15709 UNSPECV_SET_VRSAVE
));
15713 /* We need to clobber the registers in the mask so the scheduler
15714 does not move sets to VRSAVE before sets of AltiVec registers.
15716 However, if the function receives nonlocal gotos, reload will set
15717 all call saved registers live. We will end up with:
15719 (set (reg 999) (mem))
15720 (parallel [ (set (reg vrsave) (unspec blah))
15721 (clobber (reg 999))])
15723 The clobber will cause the store into reg 999 to be dead, and
15724 flow will attempt to delete an epilogue insn. In this case, we
15725 need an unspec use/set of the register. */
15727 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
15728 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
15730 if (!epiloguep
|| call_used_regs
[i
])
15731 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
15732 gen_rtx_REG (V4SImode
, i
));
15735 rtx reg
= gen_rtx_REG (V4SImode
, i
);
15738 = gen_rtx_SET (VOIDmode
,
15740 gen_rtx_UNSPEC (V4SImode
,
15741 gen_rtvec (1, reg
), 27));
15745 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
15747 for (i
= 0; i
< nclobs
; ++i
)
15748 XVECEXP (insn
, 0, i
) = clobs
[i
];
15753 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
15754 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
15757 emit_frame_save (rtx frame_reg
, rtx frame_ptr
, enum machine_mode mode
,
15758 unsigned int regno
, int offset
, HOST_WIDE_INT total_size
)
15760 rtx reg
, offset_rtx
, insn
, mem
, addr
, int_rtx
;
15761 rtx replacea
, replaceb
;
15763 int_rtx
= GEN_INT (offset
);
15765 /* Some cases that need register indexed addressing. */
15766 if ((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
15767 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
15769 && SPE_VECTOR_MODE (mode
)
15770 && !SPE_CONST_OFFSET_OK (offset
)))
15772 /* Whomever calls us must make sure r11 is available in the
15773 flow path of instructions in the prologue. */
15774 offset_rtx
= gen_rtx_REG (Pmode
, 11);
15775 emit_move_insn (offset_rtx
, int_rtx
);
15777 replacea
= offset_rtx
;
15778 replaceb
= int_rtx
;
15782 offset_rtx
= int_rtx
;
15783 replacea
= NULL_RTX
;
15784 replaceb
= NULL_RTX
;
15787 reg
= gen_rtx_REG (mode
, regno
);
15788 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, offset_rtx
);
15789 mem
= gen_frame_mem (mode
, addr
);
15791 insn
= emit_move_insn (mem
, reg
);
15793 rs6000_frame_related (insn
, frame_ptr
, total_size
, replacea
, replaceb
);
15796 /* Emit an offset memory reference suitable for a frame store, while
15797 converting to a valid addressing mode. */
15800 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
15802 rtx int_rtx
, offset_rtx
;
15804 int_rtx
= GEN_INT (offset
);
15806 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
))
15807 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
15809 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
15810 emit_move_insn (offset_rtx
, int_rtx
);
15813 offset_rtx
= int_rtx
;
15815 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
15818 /* Look for user-defined global regs. We should not save and restore these,
15819 and cannot use stmw/lmw if there are any in its range. */
15822 no_global_regs_above (int first
, bool gpr
)
15825 for (i
= first
; i
< gpr
? 32 : 64 ; i
++)
15826 if (global_regs
[i
])
15831 #ifndef TARGET_FIX_AND_CONTINUE
15832 #define TARGET_FIX_AND_CONTINUE 0
15835 /* It's really GPR 13 and FPR 14, but we need the smaller of the two. */
15836 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
15837 #define LAST_SAVRES_REGISTER 31
15838 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
15840 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][8];
15842 /* Return the symbol for an out-of-line register save/restore routine.
15843 We are saving/restoring GPRs if GPR is true. */
15846 rs6000_savres_routine_sym (rs6000_stack_t
*info
, bool savep
, bool gpr
, bool exitp
)
15848 int regno
= gpr
? info
->first_gp_reg_save
: (info
->first_fp_reg_save
- 32);
15850 int select
= ((savep
? 1 : 0) << 2
15852 /* On the SPE, we never have any FPRs, but we do have
15853 32/64-bit versions of the routines. */
15854 ? (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
? 1 : 0)
15858 /* Don't generate bogus routine names. */
15859 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
&& regno
<= LAST_SAVRES_REGISTER
);
15861 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
15866 const char *action
;
15867 const char *regkind
;
15868 const char *exit_suffix
;
15870 action
= savep
? "save" : "rest";
15872 /* SPE has slightly different names for its routines depending on
15873 whether we are saving 32-bit or 64-bit registers. */
15874 if (TARGET_SPE_ABI
)
15876 /* No floating point saves on the SPE. */
15879 regkind
= info
->spe_64bit_regs_used
? "64gpr" : "32gpr";
15882 regkind
= gpr
? "gpr" : "fpr";
15884 exit_suffix
= exitp
? "_x" : "";
15886 sprintf (name
, "_%s%s_%d%s", action
, regkind
, regno
, exit_suffix
);
15888 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
15889 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
15895 /* Emit a sequence of insns, including a stack tie if needed, for
15896 resetting the stack pointer. If SAVRES is true, then don't reset the
15897 stack pointer, but move the base of the frame into r11 for use by
15898 out-of-line register restore routines. */
15901 rs6000_emit_stack_reset (rs6000_stack_t
*info
,
15902 rtx sp_reg_rtx
, rtx frame_reg_rtx
,
15903 int sp_offset
, bool savres
)
15905 /* This blockage is needed so that sched doesn't decide to move
15906 the sp change before the register restores. */
15907 if (frame_reg_rtx
!= sp_reg_rtx
15909 && info
->spe_64bit_regs_used
!= 0
15910 && info
->first_gp_reg_save
!= 32))
15911 rs6000_emit_stack_tie ();
15913 if (frame_reg_rtx
!= sp_reg_rtx
)
15915 if (sp_offset
!= 0)
15916 emit_insn (gen_addsi3 (sp_reg_rtx
, frame_reg_rtx
,
15917 GEN_INT (sp_offset
)));
15919 emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
15921 else if (sp_offset
!= 0)
15923 /* If we are restoring registers out-of-line, we will be using the
15924 "exit" variants of the restore routines, which will reset the
15925 stack for us. But we do need to point r11 into the right place
15926 for those routines. */
15927 rtx dest_reg
= (savres
15928 ? gen_rtx_REG (Pmode
, 11)
15931 emit_insn (TARGET_32BIT
15932 ? gen_addsi3 (dest_reg
, sp_reg_rtx
,
15933 GEN_INT (sp_offset
))
15934 : gen_adddi3 (dest_reg
, sp_reg_rtx
,
15935 GEN_INT (sp_offset
)));
15939 /* Construct a parallel rtx describing the effect of a call to an
15940 out-of-line register save/restore routine. */
15943 rs6000_make_savres_rtx (rs6000_stack_t
*info
,
15944 rtx frame_reg_rtx
, int save_area_offset
,
15945 enum machine_mode reg_mode
,
15946 bool savep
, bool gpr
, bool exitp
)
15949 int offset
, start_reg
, end_reg
, n_regs
;
15950 int reg_size
= GET_MODE_SIZE (reg_mode
);
15956 ? info
->first_gp_reg_save
15957 : info
->first_fp_reg_save
);
15958 end_reg
= gpr
? 32 : 64;
15959 n_regs
= end_reg
- start_reg
;
15960 p
= rtvec_alloc ((exitp
? 4 : 3) + n_regs
);
15962 /* If we're saving registers, then we should never say we're exiting. */
15963 gcc_assert ((savep
&& !exitp
) || !savep
);
15966 RTVEC_ELT (p
, offset
++) = gen_rtx_RETURN (VOIDmode
);
15968 RTVEC_ELT (p
, offset
++)
15969 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 65));
15971 sym
= rs6000_savres_routine_sym (info
, savep
, gpr
, exitp
);
15972 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
15973 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 11));
15975 for (i
= 0; i
< end_reg
- start_reg
; i
++)
15977 rtx addr
, reg
, mem
;
15978 reg
= gen_rtx_REG (reg_mode
, start_reg
+ i
);
15979 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15980 GEN_INT (save_area_offset
+ reg_size
*i
));
15981 mem
= gen_frame_mem (reg_mode
, addr
);
15983 RTVEC_ELT (p
, i
+ offset
) = gen_rtx_SET (VOIDmode
,
15985 savep
? reg
: mem
);
15988 return gen_rtx_PARALLEL (VOIDmode
, p
);
15991 /* Determine whether the gp REG is really used. */
15994 rs6000_reg_live_or_pic_offset_p (int reg
)
15996 return ((df_regs_ever_live_p (reg
)
15997 && (!call_used_regs
[reg
]
15998 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
15999 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
16000 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
16001 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
16002 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))));
16006 SAVRES_MULTIPLE
= 0x1,
16007 SAVRES_INLINE_FPRS
= 0x2,
16008 SAVRES_INLINE_GPRS
= 0x4
16011 /* Determine the strategy for savings/restoring registers. */
16014 rs6000_savres_strategy (rs6000_stack_t
*info
, bool savep
,
16015 int using_static_chain_p
, int sibcall
)
16017 bool using_multiple_p
;
16019 bool savres_fprs_inline
;
16020 bool savres_gprs_inline
;
16021 bool noclobber_global_gprs
16022 = no_global_regs_above (info
->first_gp_reg_save
, /*gpr=*/true);
16024 using_multiple_p
= (TARGET_MULTIPLE
&& ! TARGET_POWERPC64
16025 && (!TARGET_SPE_ABI
16026 || info
->spe_64bit_regs_used
== 0)
16027 && info
->first_gp_reg_save
< 31
16028 && noclobber_global_gprs
);
16029 /* Don't bother to try to save things out-of-line if r11 is occupied
16030 by the static chain. It would require too much fiddling and the
16031 static chain is rarely used anyway. */
16032 common
= (using_static_chain_p
16034 || crtl
->calls_eh_return
16035 || !info
->lr_save_p
16036 || cfun
->machine
->ra_need_lr
16037 || info
->total_size
> 32767);
16038 savres_fprs_inline
= (common
16039 || info
->first_fp_reg_save
== 64
16040 || !no_global_regs_above (info
->first_fp_reg_save
,
16042 || FP_SAVE_INLINE (info
->first_fp_reg_save
));
16043 savres_gprs_inline
= (common
16044 /* Saving CR interferes with the exit routines
16045 used on the SPE, so just punt here. */
16048 && info
->spe_64bit_regs_used
!= 0
16049 && info
->cr_save_p
!= 0)
16050 || info
->first_gp_reg_save
== 32
16051 || !noclobber_global_gprs
16052 || GP_SAVE_INLINE (info
->first_gp_reg_save
));
16055 /* If we are going to use store multiple, then don't even bother
16056 with the out-of-line routines, since the store-multiple instruction
16057 will always be smaller. */
16058 savres_gprs_inline
= savres_gprs_inline
|| using_multiple_p
;
16061 /* The situation is more complicated with load multiple. We'd
16062 prefer to use the out-of-line routines for restores, since the
16063 "exit" out-of-line routines can handle the restore of LR and
16064 the frame teardown. But we can only use the out-of-line
16065 routines if we know that we've used store multiple or
16066 out-of-line routines in the prologue, i.e. if we've saved all
16067 the registers from first_gp_reg_save. Otherwise, we risk
16068 loading garbage from the stack. Furthermore, we can only use
16069 the "exit" out-of-line gpr restore if we haven't saved any
16071 bool saved_all
= !savres_gprs_inline
|| using_multiple_p
;
16073 if (saved_all
&& info
->first_fp_reg_save
!= 64)
16074 /* We can't use the exit routine; use load multiple if it's
16076 savres_gprs_inline
= savres_gprs_inline
|| using_multiple_p
;
16079 return (using_multiple_p
16080 | (savres_fprs_inline
<< 1)
16081 | (savres_gprs_inline
<< 2));
16084 /* Emit function prologue as insns. */
16087 rs6000_emit_prologue (void)
16089 rs6000_stack_t
*info
= rs6000_stack_info ();
16090 enum machine_mode reg_mode
= Pmode
;
16091 int reg_size
= TARGET_32BIT
? 4 : 8;
16092 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
16093 rtx frame_ptr_rtx
= gen_rtx_REG (Pmode
, 12);
16094 rtx frame_reg_rtx
= sp_reg_rtx
;
16095 rtx cr_save_rtx
= NULL_RTX
;
16098 int saving_FPRs_inline
;
16099 int saving_GPRs_inline
;
16100 int using_store_multiple
;
16101 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
16102 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
16103 && !call_used_regs
[STATIC_CHAIN_REGNUM
]);
16104 HOST_WIDE_INT sp_offset
= 0;
16106 if (TARGET_FIX_AND_CONTINUE
)
16108 /* gdb on darwin arranges to forward a function from the old
16109 address by modifying the first 5 instructions of the function
16110 to branch to the overriding function. This is necessary to
16111 permit function pointers that point to the old function to
16112 actually forward to the new function. */
16113 emit_insn (gen_nop ());
16114 emit_insn (gen_nop ());
16115 emit_insn (gen_nop ());
16116 emit_insn (gen_nop ());
16117 emit_insn (gen_nop ());
16120 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
16122 reg_mode
= V2SImode
;
16126 strategy
= rs6000_savres_strategy (info
, /*savep=*/true,
16127 /*static_chain_p=*/using_static_chain_p
,
16129 using_store_multiple
= strategy
& SAVRES_MULTIPLE
;
16130 saving_FPRs_inline
= strategy
& SAVRES_INLINE_FPRS
;
16131 saving_GPRs_inline
= strategy
& SAVRES_INLINE_GPRS
;
16133 /* For V.4, update stack before we do any saving and set back pointer. */
16134 if (! WORLD_SAVE_P (info
)
16136 && (DEFAULT_ABI
== ABI_V4
16137 || crtl
->calls_eh_return
))
16139 bool need_r11
= (TARGET_SPE
16140 ? (!saving_GPRs_inline
16141 && info
->spe_64bit_regs_used
== 0)
16142 : (!saving_FPRs_inline
|| !saving_GPRs_inline
));
16143 if (info
->total_size
< 32767)
16144 sp_offset
= info
->total_size
;
16146 frame_reg_rtx
= (need_r11
16147 ? gen_rtx_REG (Pmode
, 11)
16149 rs6000_emit_allocate_stack (info
->total_size
,
16150 (frame_reg_rtx
!= sp_reg_rtx
16151 && (info
->cr_save_p
16153 || info
->first_fp_reg_save
< 64
16154 || info
->first_gp_reg_save
< 32
16157 if (frame_reg_rtx
!= sp_reg_rtx
)
16158 rs6000_emit_stack_tie ();
16161 /* Handle world saves specially here. */
16162 if (WORLD_SAVE_P (info
))
16169 /* save_world expects lr in r0. */
16170 reg0
= gen_rtx_REG (Pmode
, 0);
16171 if (info
->lr_save_p
)
16173 insn
= emit_move_insn (reg0
,
16174 gen_rtx_REG (Pmode
, LR_REGNO
));
16175 RTX_FRAME_RELATED_P (insn
) = 1;
16178 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
16179 assumptions about the offsets of various bits of the stack
16181 gcc_assert (info
->gp_save_offset
== -220
16182 && info
->fp_save_offset
== -144
16183 && info
->lr_save_offset
== 8
16184 && info
->cr_save_offset
== 4
16187 && (!crtl
->calls_eh_return
16188 || info
->ehrd_offset
== -432)
16189 && info
->vrsave_save_offset
== -224
16190 && info
->altivec_save_offset
== -416);
16192 treg
= gen_rtx_REG (SImode
, 11);
16193 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
16195 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
16196 in R11. It also clobbers R12, so beware! */
16198 /* Preserve CR2 for save_world prologues */
16200 sz
+= 32 - info
->first_gp_reg_save
;
16201 sz
+= 64 - info
->first_fp_reg_save
;
16202 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
16203 p
= rtvec_alloc (sz
);
16205 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
16206 gen_rtx_REG (SImode
,
16208 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
16209 gen_rtx_SYMBOL_REF (Pmode
,
16211 /* We do floats first so that the instruction pattern matches
16213 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
16215 rtx reg
= gen_rtx_REG (((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
16216 ? DFmode
: SFmode
),
16217 info
->first_fp_reg_save
+ i
);
16218 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16219 GEN_INT (info
->fp_save_offset
16220 + sp_offset
+ 8 * i
));
16221 rtx mem
= gen_frame_mem (((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
16222 ? DFmode
: SFmode
), addr
);
16224 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
16226 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
16228 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
16229 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16230 GEN_INT (info
->altivec_save_offset
16231 + sp_offset
+ 16 * i
));
16232 rtx mem
= gen_frame_mem (V4SImode
, addr
);
16234 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
16236 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16238 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
16239 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16240 GEN_INT (info
->gp_save_offset
16241 + sp_offset
+ reg_size
* i
));
16242 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16244 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
16248 /* CR register traditionally saved as CR2. */
16249 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
16250 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16251 GEN_INT (info
->cr_save_offset
16253 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16255 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
16257 /* Explain about use of R0. */
16258 if (info
->lr_save_p
)
16260 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16261 GEN_INT (info
->lr_save_offset
16263 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16265 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg0
);
16267 /* Explain what happens to the stack pointer. */
16269 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
16270 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, sp_reg_rtx
, newval
);
16273 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
16274 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16275 treg
, GEN_INT (-info
->total_size
));
16276 sp_offset
= info
->total_size
;
16279 /* If we use the link register, get it into r0. */
16280 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
16282 rtx addr
, reg
, mem
;
16284 insn
= emit_move_insn (gen_rtx_REG (Pmode
, 0),
16285 gen_rtx_REG (Pmode
, LR_REGNO
));
16286 RTX_FRAME_RELATED_P (insn
) = 1;
16288 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16289 GEN_INT (info
->lr_save_offset
+ sp_offset
));
16290 reg
= gen_rtx_REG (Pmode
, 0);
16291 mem
= gen_rtx_MEM (Pmode
, addr
);
16292 /* This should not be of rs6000_sr_alias_set, because of
16293 __builtin_return_address. */
16295 insn
= emit_move_insn (mem
, reg
);
16296 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16297 NULL_RTX
, NULL_RTX
);
16300 /* If we need to save CR, put it into r12. */
16301 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
&& frame_reg_rtx
!= frame_ptr_rtx
)
16305 cr_save_rtx
= gen_rtx_REG (SImode
, 12);
16306 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
16307 RTX_FRAME_RELATED_P (insn
) = 1;
16308 /* Now, there's no way that dwarf2out_frame_debug_expr is going
16309 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
16310 But that's OK. All we have to do is specify that _one_ condition
16311 code register is saved in this stack slot. The thrower's epilogue
16312 will then restore all the call-saved registers.
16313 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
16314 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
,
16315 gen_rtx_REG (SImode
, CR2_REGNO
));
16316 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
16319 /* Do any required saving of fpr's. If only one or two to save, do
16320 it ourselves. Otherwise, call function. */
16321 if (!WORLD_SAVE_P (info
) && saving_FPRs_inline
)
16324 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
16325 if ((df_regs_ever_live_p (info
->first_fp_reg_save
+i
)
16326 && ! call_used_regs
[info
->first_fp_reg_save
+i
]))
16327 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
,
16328 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
16330 info
->first_fp_reg_save
+ i
,
16331 info
->fp_save_offset
+ sp_offset
+ 8 * i
,
16334 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
16338 par
= rs6000_make_savres_rtx (info
, frame_reg_rtx
,
16339 info
->fp_save_offset
+ sp_offset
,
16341 /*savep=*/true, /*gpr=*/false,
16343 insn
= emit_insn (par
);
16344 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16345 NULL_RTX
, NULL_RTX
);
16348 /* Save GPRs. This is done as a PARALLEL if we are using
16349 the store-multiple instructions. */
16350 if (!WORLD_SAVE_P (info
)
16352 && info
->spe_64bit_regs_used
!= 0
16353 && info
->first_gp_reg_save
!= 32)
16356 rtx spe_save_area_ptr
;
16358 /* Determine whether we can address all of the registers that need
16359 to be saved with an offset from the stack pointer that fits in
16360 the small const field for SPE memory instructions. */
16361 int spe_regs_addressable_via_sp
16362 = (SPE_CONST_OFFSET_OK(info
->spe_gp_save_offset
+ sp_offset
16363 + (32 - info
->first_gp_reg_save
- 1) * reg_size
)
16364 && saving_GPRs_inline
);
16367 if (spe_regs_addressable_via_sp
)
16369 spe_save_area_ptr
= frame_reg_rtx
;
16370 spe_offset
= info
->spe_gp_save_offset
+ sp_offset
;
16374 /* Make r11 point to the start of the SPE save area. We need
16375 to be careful here if r11 is holding the static chain. If
16376 it is, then temporarily save it in r0. We would use r0 as
16377 our base register here, but using r0 as a base register in
16378 loads and stores means something different from what we
16380 int ool_adjust
= (saving_GPRs_inline
16382 : (info
->first_gp_reg_save
16383 - (FIRST_SAVRES_REGISTER
+1))*8);
16384 HOST_WIDE_INT offset
= (info
->spe_gp_save_offset
16385 + sp_offset
- ool_adjust
);
16387 if (using_static_chain_p
)
16389 rtx r0
= gen_rtx_REG (Pmode
, 0);
16390 gcc_assert (info
->first_gp_reg_save
> 11);
16392 emit_move_insn (r0
, gen_rtx_REG (Pmode
, 11));
16395 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
16396 insn
= emit_insn (gen_addsi3 (spe_save_area_ptr
,
16398 GEN_INT (offset
)));
16399 /* We need to make sure the move to r11 gets noted for
16400 properly outputting unwind information. */
16401 if (!saving_GPRs_inline
)
16402 rs6000_frame_related (insn
, frame_reg_rtx
, offset
,
16403 NULL_RTX
, NULL_RTX
);
16407 if (saving_GPRs_inline
)
16409 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16410 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
16412 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
16413 rtx offset
, addr
, mem
;
16415 /* We're doing all this to ensure that the offset fits into
16416 the immediate offset of 'evstdd'. */
16417 gcc_assert (SPE_CONST_OFFSET_OK (reg_size
* i
+ spe_offset
));
16419 offset
= GEN_INT (reg_size
* i
+ spe_offset
);
16420 addr
= gen_rtx_PLUS (Pmode
, spe_save_area_ptr
, offset
);
16421 mem
= gen_rtx_MEM (V2SImode
, addr
);
16423 insn
= emit_move_insn (mem
, reg
);
16425 rs6000_frame_related (insn
, spe_save_area_ptr
,
16426 info
->spe_gp_save_offset
16427 + sp_offset
+ reg_size
* i
,
16428 offset
, const0_rtx
);
16435 par
= rs6000_make_savres_rtx (info
, gen_rtx_REG (Pmode
, 11),
16437 /*savep=*/true, /*gpr=*/true,
16439 insn
= emit_insn (par
);
16440 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16441 NULL_RTX
, NULL_RTX
);
16445 /* Move the static chain pointer back. */
16446 if (using_static_chain_p
&& !spe_regs_addressable_via_sp
)
16447 emit_move_insn (gen_rtx_REG (Pmode
, 11), gen_rtx_REG (Pmode
, 0));
16449 else if (!WORLD_SAVE_P (info
) && !saving_GPRs_inline
)
16453 /* Need to adjust r11 if we saved any FPRs. */
16454 if (info
->first_fp_reg_save
!= 64)
16456 rtx r11
= gen_rtx_REG (reg_mode
, 11);
16457 rtx offset
= GEN_INT (info
->total_size
16458 + (-8 * (64-info
->first_fp_reg_save
)));
16459 rtx ptr_reg
= (sp_reg_rtx
== frame_reg_rtx
16460 ? sp_reg_rtx
: r11
);
16462 emit_insn (TARGET_32BIT
16463 ? gen_addsi3 (r11
, ptr_reg
, offset
)
16464 : gen_adddi3 (r11
, ptr_reg
, offset
));
16467 par
= rs6000_make_savres_rtx (info
, frame_reg_rtx
,
16468 info
->gp_save_offset
+ sp_offset
,
16470 /*savep=*/true, /*gpr=*/true,
16472 insn
= emit_insn (par
);
16473 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16474 NULL_RTX
, NULL_RTX
);
16476 else if (!WORLD_SAVE_P (info
) && using_store_multiple
)
16480 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
16481 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16483 rtx addr
, reg
, mem
;
16484 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
16485 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16486 GEN_INT (info
->gp_save_offset
16489 mem
= gen_frame_mem (reg_mode
, addr
);
16491 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, reg
);
16493 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
16494 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16495 NULL_RTX
, NULL_RTX
);
16497 else if (!WORLD_SAVE_P (info
))
16500 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16501 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
16503 rtx addr
, reg
, mem
;
16504 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
16506 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16507 GEN_INT (info
->gp_save_offset
16510 mem
= gen_frame_mem (reg_mode
, addr
);
16512 insn
= emit_move_insn (mem
, reg
);
16513 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16514 NULL_RTX
, NULL_RTX
);
16518 /* ??? There's no need to emit actual instructions here, but it's the
16519 easiest way to get the frame unwind information emitted. */
16520 if (crtl
->calls_eh_return
)
16522 unsigned int i
, regno
;
16524 /* In AIX ABI we need to pretend we save r2 here. */
16527 rtx addr
, reg
, mem
;
16529 reg
= gen_rtx_REG (reg_mode
, 2);
16530 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16531 GEN_INT (sp_offset
+ 5 * reg_size
));
16532 mem
= gen_frame_mem (reg_mode
, addr
);
16534 insn
= emit_move_insn (mem
, reg
);
16535 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16536 NULL_RTX
, NULL_RTX
);
16537 PATTERN (insn
) = gen_blockage ();
16542 regno
= EH_RETURN_DATA_REGNO (i
);
16543 if (regno
== INVALID_REGNUM
)
16546 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, reg_mode
, regno
,
16547 info
->ehrd_offset
+ sp_offset
16548 + reg_size
* (int) i
,
16553 /* Save CR if we use any that must be preserved. */
16554 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
16556 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16557 GEN_INT (info
->cr_save_offset
+ sp_offset
));
16558 rtx mem
= gen_frame_mem (SImode
, addr
);
16559 /* See the large comment above about why CR2_REGNO is used. */
16560 rtx magic_eh_cr_reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
16562 /* If r12 was used to hold the original sp, copy cr into r0 now
16564 if (REGNO (frame_reg_rtx
) == 12)
16568 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
16569 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
16570 RTX_FRAME_RELATED_P (insn
) = 1;
16571 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
, magic_eh_cr_reg
);
16572 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
16574 insn
= emit_move_insn (mem
, cr_save_rtx
);
16576 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16577 NULL_RTX
, NULL_RTX
);
16580 /* Update stack and set back pointer unless this is V.4,
16581 for which it was done previously. */
16582 if (!WORLD_SAVE_P (info
) && info
->push_p
16583 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
16585 if (info
->total_size
< 32767)
16586 sp_offset
= info
->total_size
;
16588 frame_reg_rtx
= frame_ptr_rtx
;
16589 rs6000_emit_allocate_stack (info
->total_size
,
16590 (frame_reg_rtx
!= sp_reg_rtx
16591 && ((info
->altivec_size
!= 0)
16592 || (info
->vrsave_mask
!= 0)
16595 if (frame_reg_rtx
!= sp_reg_rtx
)
16596 rs6000_emit_stack_tie ();
16599 /* Set frame pointer, if needed. */
16600 if (frame_pointer_needed
)
16602 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
16604 RTX_FRAME_RELATED_P (insn
) = 1;
16607 /* Save AltiVec registers if needed. Save here because the red zone does
16608 not include AltiVec registers. */
16609 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
&& info
->altivec_size
!= 0)
16613 /* There should be a non inline version of this, for when we
16614 are saving lots of vector registers. */
16615 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
16616 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
16618 rtx areg
, savereg
, mem
;
16621 offset
= info
->altivec_save_offset
+ sp_offset
16622 + 16 * (i
- info
->first_altivec_reg_save
);
16624 savereg
= gen_rtx_REG (V4SImode
, i
);
16626 areg
= gen_rtx_REG (Pmode
, 0);
16627 emit_move_insn (areg
, GEN_INT (offset
));
16629 /* AltiVec addressing mode is [reg+reg]. */
16630 mem
= gen_frame_mem (V4SImode
,
16631 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
16633 insn
= emit_move_insn (mem
, savereg
);
16635 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16636 areg
, GEN_INT (offset
));
16640 /* VRSAVE is a bit vector representing which AltiVec registers
16641 are used. The OS uses this to determine which vector
16642 registers to save on a context switch. We need to save
16643 VRSAVE on the stack frame, add whatever AltiVec registers we
16644 used in this function, and do the corresponding magic in the
16647 if (TARGET_ALTIVEC
&& TARGET_ALTIVEC_VRSAVE
16648 && info
->vrsave_mask
!= 0)
16650 rtx reg
, mem
, vrsave
;
16653 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
16654 as frame_reg_rtx and r11 as the static chain pointer for
16655 nested functions. */
16656 reg
= gen_rtx_REG (SImode
, 0);
16657 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
16659 emit_insn (gen_get_vrsave_internal (reg
));
16661 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
16663 if (!WORLD_SAVE_P (info
))
16666 offset
= info
->vrsave_save_offset
+ sp_offset
;
16667 mem
= gen_frame_mem (SImode
,
16668 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16669 GEN_INT (offset
)));
16670 insn
= emit_move_insn (mem
, reg
);
16673 /* Include the registers in the mask. */
16674 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
16676 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
16679 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
16680 if ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
16681 || (DEFAULT_ABI
== ABI_V4
16682 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
16683 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
)))
16685 /* If emit_load_toc_table will use the link register, we need to save
16686 it. We use R12 for this purpose because emit_load_toc_table
16687 can use register 0. This allows us to use a plain 'blr' to return
16688 from the procedure more often. */
16689 int save_LR_around_toc_setup
= (TARGET_ELF
16690 && DEFAULT_ABI
!= ABI_AIX
16692 && ! info
->lr_save_p
16693 && EDGE_COUNT (EXIT_BLOCK_PTR
->preds
) > 0);
16694 if (save_LR_around_toc_setup
)
16696 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
16698 insn
= emit_move_insn (frame_ptr_rtx
, lr
);
16699 RTX_FRAME_RELATED_P (insn
) = 1;
16701 rs6000_emit_load_toc_table (TRUE
);
16703 insn
= emit_move_insn (lr
, frame_ptr_rtx
);
16704 RTX_FRAME_RELATED_P (insn
) = 1;
16707 rs6000_emit_load_toc_table (TRUE
);
16711 if (DEFAULT_ABI
== ABI_DARWIN
16712 && flag_pic
&& crtl
->uses_pic_offset_table
)
16714 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
16715 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
16717 /* Save and restore LR locally around this call (in R0). */
16718 if (!info
->lr_save_p
)
16719 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
16721 emit_insn (gen_load_macho_picbase (src
));
16723 emit_move_insn (gen_rtx_REG (Pmode
,
16724 RS6000_PIC_OFFSET_TABLE_REGNUM
),
16727 if (!info
->lr_save_p
)
16728 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
16733 /* Write function prologue. */
16736 rs6000_output_function_prologue (FILE *file
,
16737 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
16739 rs6000_stack_t
*info
= rs6000_stack_info ();
16741 if (TARGET_DEBUG_STACK
)
16742 debug_stack_info (info
);
16744 /* Write .extern for any function we will call to save and restore
16746 if (info
->first_fp_reg_save
< 64
16747 && !FP_SAVE_INLINE (info
->first_fp_reg_save
))
16748 fprintf (file
, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
16749 SAVE_FP_PREFIX
, info
->first_fp_reg_save
- 32, SAVE_FP_SUFFIX
,
16750 RESTORE_FP_PREFIX
, info
->first_fp_reg_save
- 32, RESTORE_FP_SUFFIX
);
16752 /* Write .extern for AIX common mode routines, if needed. */
16753 if (! TARGET_POWER
&& ! TARGET_POWERPC
&& ! common_mode_defined
)
16755 fputs ("\t.extern __mulh\n", file
);
16756 fputs ("\t.extern __mull\n", file
);
16757 fputs ("\t.extern __divss\n", file
);
16758 fputs ("\t.extern __divus\n", file
);
16759 fputs ("\t.extern __quoss\n", file
);
16760 fputs ("\t.extern __quous\n", file
);
16761 common_mode_defined
= 1;
16764 if (! HAVE_prologue
)
16768 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
16769 the "toplevel" insn chain. */
16770 emit_note (NOTE_INSN_DELETED
);
16771 rs6000_emit_prologue ();
16772 emit_note (NOTE_INSN_DELETED
);
16774 /* Expand INSN_ADDRESSES so final() doesn't crash. */
16778 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
16780 INSN_ADDRESSES_NEW (insn
, addr
);
16785 if (TARGET_DEBUG_STACK
)
16786 debug_rtx_list (get_insns (), 100);
16787 final (get_insns (), file
, FALSE
);
16791 rs6000_pic_labelno
++;
16794 /* Non-zero if vmx regs are restored before the frame pop, zero if
16795 we restore after the pop when possible. */
16796 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
16798 /* Reload CR from REG. */
16801 rs6000_restore_saved_cr (rtx reg
, int using_mfcr_multiple
)
16806 if (using_mfcr_multiple
)
16808 for (i
= 0; i
< 8; i
++)
16809 if (df_regs_ever_live_p (CR0_REGNO
+i
) && ! call_used_regs
[CR0_REGNO
+i
])
16811 gcc_assert (count
);
16814 if (using_mfcr_multiple
&& count
> 1)
16819 p
= rtvec_alloc (count
);
16822 for (i
= 0; i
< 8; i
++)
16823 if (df_regs_ever_live_p (CR0_REGNO
+i
) && ! call_used_regs
[CR0_REGNO
+i
])
16825 rtvec r
= rtvec_alloc (2);
16826 RTVEC_ELT (r
, 0) = reg
;
16827 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
16828 RTVEC_ELT (p
, ndx
) =
16829 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+i
),
16830 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
16833 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
16834 gcc_assert (ndx
== count
);
16837 for (i
= 0; i
< 8; i
++)
16838 if (df_regs_ever_live_p (CR0_REGNO
+i
) && ! call_used_regs
[CR0_REGNO
+i
])
16840 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode
,
16846 /* Emit function epilogue as insns.
16848 At present, dwarf2out_frame_debug_expr doesn't understand
16849 register restores, so we don't bother setting RTX_FRAME_RELATED_P
16850 anywhere in the epilogue. Most of the insns below would in any case
16851 need special notes to explain where r11 is in relation to the stack. */
16854 rs6000_emit_epilogue (int sibcall
)
16856 rs6000_stack_t
*info
;
16857 int restoring_GPRs_inline
;
16858 int restoring_FPRs_inline
;
16859 int using_load_multiple
;
16860 int using_mtcr_multiple
;
16861 int use_backchain_to_restore_sp
;
16865 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
16866 rtx frame_reg_rtx
= sp_reg_rtx
;
16867 enum machine_mode reg_mode
= Pmode
;
16868 int reg_size
= TARGET_32BIT
? 4 : 8;
16871 info
= rs6000_stack_info ();
16873 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
16875 reg_mode
= V2SImode
;
16879 strategy
= rs6000_savres_strategy (info
, /*savep=*/false,
16880 /*static_chain_p=*/0, sibcall
);
16881 using_load_multiple
= strategy
& SAVRES_MULTIPLE
;
16882 restoring_FPRs_inline
= strategy
& SAVRES_INLINE_FPRS
;
16883 restoring_GPRs_inline
= strategy
& SAVRES_INLINE_GPRS
;
16884 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
16885 || rs6000_cpu
== PROCESSOR_PPC603
16886 || rs6000_cpu
== PROCESSOR_PPC750
16888 /* Restore via the backchain when we have a large frame, since this
16889 is more efficient than an addis, addi pair. The second condition
16890 here will not trigger at the moment; We don't actually need a
16891 frame pointer for alloca, but the generic parts of the compiler
16892 give us one anyway. */
16893 use_backchain_to_restore_sp
= (info
->total_size
> 32767
16894 || info
->total_size
16895 + (info
->lr_save_p
? info
->lr_save_offset
: 0)
16897 || (cfun
->calls_alloca
16898 && !frame_pointer_needed
));
16899 restore_lr
= (info
->lr_save_p
16900 && restoring_GPRs_inline
16901 && restoring_FPRs_inline
);
16903 if (WORLD_SAVE_P (info
))
16907 const char *alloc_rname
;
16910 /* eh_rest_world_r10 will return to the location saved in the LR
16911 stack slot (which is not likely to be our caller.)
16912 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
16913 rest_world is similar, except any R10 parameter is ignored.
16914 The exception-handling stuff that was here in 2.95 is no
16915 longer necessary. */
16919 + 32 - info
->first_gp_reg_save
16920 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
16921 + 63 + 1 - info
->first_fp_reg_save
);
16923 strcpy (rname
, ((crtl
->calls_eh_return
) ?
16924 "*eh_rest_world_r10" : "*rest_world"));
16925 alloc_rname
= ggc_strdup (rname
);
16928 RTVEC_ELT (p
, j
++) = gen_rtx_RETURN (VOIDmode
);
16929 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
16930 gen_rtx_REG (Pmode
,
16933 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
16934 /* The instruction pattern requires a clobber here;
16935 it is shared with the restVEC helper. */
16937 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
16940 /* CR register traditionally saved as CR2. */
16941 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
16942 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16943 GEN_INT (info
->cr_save_offset
));
16944 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16946 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
16949 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16951 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
16952 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16953 GEN_INT (info
->gp_save_offset
16955 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16957 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
16959 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
16961 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
16962 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16963 GEN_INT (info
->altivec_save_offset
16965 rtx mem
= gen_frame_mem (V4SImode
, addr
);
16967 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
16969 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
16971 rtx reg
= gen_rtx_REG (((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
16972 ? DFmode
: SFmode
),
16973 info
->first_fp_reg_save
+ i
);
16974 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16975 GEN_INT (info
->fp_save_offset
16977 rtx mem
= gen_frame_mem (((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
16978 ? DFmode
: SFmode
), addr
);
16980 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
16983 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
16985 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
16987 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
16989 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
16991 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
16992 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
16997 /* frame_reg_rtx + sp_offset points to the top of this stack frame. */
16999 sp_offset
= info
->total_size
;
17001 /* Restore AltiVec registers if we must do so before adjusting the
17003 if (TARGET_ALTIVEC_ABI
17004 && info
->altivec_size
!= 0
17005 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
17006 || (DEFAULT_ABI
!= ABI_V4
17007 && info
->altivec_save_offset
< (TARGET_32BIT
? -220 : -288))))
17011 if (use_backchain_to_restore_sp
)
17013 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
17014 emit_move_insn (frame_reg_rtx
,
17015 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
17018 else if (frame_pointer_needed
)
17019 frame_reg_rtx
= hard_frame_pointer_rtx
;
17021 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
17022 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
17024 rtx addr
, areg
, mem
;
17026 areg
= gen_rtx_REG (Pmode
, 0);
17028 (areg
, GEN_INT (info
->altivec_save_offset
17030 + 16 * (i
- info
->first_altivec_reg_save
)));
17032 /* AltiVec addressing mode is [reg+reg]. */
17033 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
17034 mem
= gen_frame_mem (V4SImode
, addr
);
17036 emit_move_insn (gen_rtx_REG (V4SImode
, i
), mem
);
17040 /* Restore VRSAVE if we must do so before adjusting the stack. */
17042 && TARGET_ALTIVEC_VRSAVE
17043 && info
->vrsave_mask
!= 0
17044 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
17045 || (DEFAULT_ABI
!= ABI_V4
17046 && info
->vrsave_save_offset
< (TARGET_32BIT
? -220 : -288))))
17048 rtx addr
, mem
, reg
;
17050 if (frame_reg_rtx
== sp_reg_rtx
)
17052 if (use_backchain_to_restore_sp
)
17054 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
17055 emit_move_insn (frame_reg_rtx
,
17056 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
17059 else if (frame_pointer_needed
)
17060 frame_reg_rtx
= hard_frame_pointer_rtx
;
17063 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
17064 GEN_INT (info
->vrsave_save_offset
+ sp_offset
));
17065 mem
= gen_frame_mem (SImode
, addr
);
17066 reg
= gen_rtx_REG (SImode
, 12);
17067 emit_move_insn (reg
, mem
);
17069 emit_insn (generate_set_vrsave (reg
, info
, 1));
17072 /* If we have a large stack frame, restore the old stack pointer
17073 using the backchain. */
17074 if (use_backchain_to_restore_sp
)
17076 if (frame_reg_rtx
== sp_reg_rtx
)
17078 /* Under V.4, don't reset the stack pointer until after we're done
17079 loading the saved registers. */
17080 if (DEFAULT_ABI
== ABI_V4
)
17081 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
17083 emit_move_insn (frame_reg_rtx
,
17084 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
17087 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
17088 && DEFAULT_ABI
== ABI_V4
)
17089 /* frame_reg_rtx has been set up by the altivec restore. */
17093 emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
17094 frame_reg_rtx
= sp_reg_rtx
;
17097 /* If we have a frame pointer, we can restore the old stack pointer
17099 else if (frame_pointer_needed
)
17101 frame_reg_rtx
= sp_reg_rtx
;
17102 if (DEFAULT_ABI
== ABI_V4
)
17103 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
17105 emit_insn (TARGET_32BIT
17106 ? gen_addsi3 (frame_reg_rtx
, hard_frame_pointer_rtx
,
17107 GEN_INT (info
->total_size
))
17108 : gen_adddi3 (frame_reg_rtx
, hard_frame_pointer_rtx
,
17109 GEN_INT (info
->total_size
)));
17112 else if (info
->push_p
17113 && DEFAULT_ABI
!= ABI_V4
17114 && !crtl
->calls_eh_return
)
17116 emit_insn (TARGET_32BIT
17117 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
,
17118 GEN_INT (info
->total_size
))
17119 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
,
17120 GEN_INT (info
->total_size
)));
17124 /* Restore AltiVec registers if we have not done so already. */
17125 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
17126 && TARGET_ALTIVEC_ABI
17127 && info
->altivec_size
!= 0
17128 && (DEFAULT_ABI
== ABI_V4
17129 || info
->altivec_save_offset
>= (TARGET_32BIT
? -220 : -288)))
17133 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
17134 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
17136 rtx addr
, areg
, mem
;
17138 areg
= gen_rtx_REG (Pmode
, 0);
17140 (areg
, GEN_INT (info
->altivec_save_offset
17142 + 16 * (i
- info
->first_altivec_reg_save
)));
17144 /* AltiVec addressing mode is [reg+reg]. */
17145 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
17146 mem
= gen_frame_mem (V4SImode
, addr
);
17148 emit_move_insn (gen_rtx_REG (V4SImode
, i
), mem
);
17152 /* Restore VRSAVE if we have not done so already. */
17153 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
17155 && TARGET_ALTIVEC_VRSAVE
17156 && info
->vrsave_mask
!= 0
17157 && (DEFAULT_ABI
== ABI_V4
17158 || info
->vrsave_save_offset
>= (TARGET_32BIT
? -220 : -288)))
17160 rtx addr
, mem
, reg
;
17162 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
17163 GEN_INT (info
->vrsave_save_offset
+ sp_offset
));
17164 mem
= gen_frame_mem (SImode
, addr
);
17165 reg
= gen_rtx_REG (SImode
, 12);
17166 emit_move_insn (reg
, mem
);
17168 emit_insn (generate_set_vrsave (reg
, info
, 1));
17171 /* Get the old lr if we saved it. If we are restoring registers
17172 out-of-line, then the out-of-line routines can do this for us. */
17175 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
,
17176 info
->lr_save_offset
+ sp_offset
);
17178 emit_move_insn (gen_rtx_REG (Pmode
, 0), mem
);
17181 /* Get the old cr if we saved it. */
17182 if (info
->cr_save_p
)
17184 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
17185 GEN_INT (info
->cr_save_offset
+ sp_offset
));
17186 rtx mem
= gen_frame_mem (SImode
, addr
);
17188 emit_move_insn (gen_rtx_REG (SImode
, 12), mem
);
17191 /* Set LR here to try to overlap restores below. */
17193 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
),
17194 gen_rtx_REG (Pmode
, 0));
17196 /* Load exception handler data registers, if needed. */
17197 if (crtl
->calls_eh_return
)
17199 unsigned int i
, regno
;
17203 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
17204 GEN_INT (sp_offset
+ 5 * reg_size
));
17205 rtx mem
= gen_frame_mem (reg_mode
, addr
);
17207 emit_move_insn (gen_rtx_REG (reg_mode
, 2), mem
);
17214 regno
= EH_RETURN_DATA_REGNO (i
);
17215 if (regno
== INVALID_REGNUM
)
17218 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
17219 info
->ehrd_offset
+ sp_offset
17220 + reg_size
* (int) i
);
17222 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
17226 /* Restore GPRs. This is done as a PARALLEL if we are using
17227 the load-multiple instructions. */
17229 && info
->spe_64bit_regs_used
!= 0
17230 && info
->first_gp_reg_save
!= 32)
17232 /* Determine whether we can address all of the registers that need
17233 to be saved with an offset from the stack pointer that fits in
17234 the small const field for SPE memory instructions. */
17235 int spe_regs_addressable_via_sp
17236 = (SPE_CONST_OFFSET_OK(info
->spe_gp_save_offset
+ sp_offset
17237 + (32 - info
->first_gp_reg_save
- 1) * reg_size
)
17238 && restoring_GPRs_inline
);
17241 if (spe_regs_addressable_via_sp
)
17242 spe_offset
= info
->spe_gp_save_offset
+ sp_offset
;
17245 rtx old_frame_reg_rtx
= frame_reg_rtx
;
17246 /* Make r11 point to the start of the SPE save area. We worried about
17247 not clobbering it when we were saving registers in the prologue.
17248 There's no need to worry here because the static chain is passed
17249 anew to every function. */
17250 int ool_adjust
= (restoring_GPRs_inline
17252 : (info
->first_gp_reg_save
17253 - (FIRST_SAVRES_REGISTER
+1))*8);
17255 if (frame_reg_rtx
== sp_reg_rtx
)
17256 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
17257 emit_insn (gen_addsi3 (frame_reg_rtx
, old_frame_reg_rtx
,
17258 GEN_INT (info
->spe_gp_save_offset
17261 /* Keep the invariant that frame_reg_rtx + sp_offset points
17262 at the top of the stack frame. */
17263 sp_offset
= -info
->spe_gp_save_offset
;
17268 if (restoring_GPRs_inline
)
17270 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
17271 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
17273 rtx offset
, addr
, mem
;
17275 /* We're doing all this to ensure that the immediate offset
17276 fits into the immediate field of 'evldd'. */
17277 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
17279 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
17280 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, offset
);
17281 mem
= gen_rtx_MEM (V2SImode
, addr
);
17283 emit_move_insn (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
17291 par
= rs6000_make_savres_rtx (info
, gen_rtx_REG (Pmode
, 11),
17293 /*savep=*/false, /*gpr=*/true,
17295 emit_jump_insn (par
);
17297 /* We don't want anybody else emitting things after we jumped
17302 else if (!restoring_GPRs_inline
)
17304 /* We are jumping to an out-of-line function. */
17305 bool can_use_exit
= info
->first_fp_reg_save
== 64;
17308 /* Emit stack reset code if we need it. */
17310 rs6000_emit_stack_reset (info
, sp_reg_rtx
, frame_reg_rtx
,
17311 sp_offset
, can_use_exit
);
17313 emit_insn (gen_addsi3 (gen_rtx_REG (Pmode
, 11),
17315 GEN_INT (sp_offset
- info
->fp_size
)));
17317 par
= rs6000_make_savres_rtx (info
, frame_reg_rtx
,
17318 info
->gp_save_offset
, reg_mode
,
17319 /*savep=*/false, /*gpr=*/true,
17320 /*exitp=*/can_use_exit
);
17324 if (info
->cr_save_p
)
17325 rs6000_restore_saved_cr (gen_rtx_REG (SImode
, 12),
17326 using_mtcr_multiple
);
17328 emit_jump_insn (par
);
17330 /* We don't want anybody else emitting things after we jumped
17337 else if (using_load_multiple
)
17340 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
17341 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
17343 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
17344 GEN_INT (info
->gp_save_offset
17347 rtx mem
= gen_frame_mem (reg_mode
, addr
);
17350 gen_rtx_SET (VOIDmode
,
17351 gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
17354 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
17358 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
17359 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
17361 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
17362 GEN_INT (info
->gp_save_offset
17365 rtx mem
= gen_frame_mem (reg_mode
, addr
);
17367 emit_move_insn (gen_rtx_REG (reg_mode
,
17368 info
->first_gp_reg_save
+ i
), mem
);
17372 /* Restore fpr's if we need to do it without calling a function. */
17373 if (restoring_FPRs_inline
)
17374 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
17375 if ((df_regs_ever_live_p (info
->first_fp_reg_save
+i
)
17376 && ! call_used_regs
[info
->first_fp_reg_save
+i
]))
17379 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
17380 GEN_INT (info
->fp_save_offset
17383 mem
= gen_frame_mem (((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
17384 ? DFmode
: SFmode
), addr
);
17386 emit_move_insn (gen_rtx_REG (((TARGET_HARD_FLOAT
17387 && TARGET_DOUBLE_FLOAT
)
17388 ? DFmode
: SFmode
),
17389 info
->first_fp_reg_save
+ i
),
17393 /* If we saved cr, restore it here. Just those that were used. */
17394 if (info
->cr_save_p
)
17395 rs6000_restore_saved_cr (gen_rtx_REG (SImode
, 12), using_mtcr_multiple
);
17397 /* If this is V.4, unwind the stack pointer after all of the loads
17399 rs6000_emit_stack_reset (info
, sp_reg_rtx
, frame_reg_rtx
,
17400 sp_offset
, !restoring_FPRs_inline
);
17402 if (crtl
->calls_eh_return
)
17404 rtx sa
= EH_RETURN_STACKADJ_RTX
;
17405 emit_insn (TARGET_32BIT
17406 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
, sa
)
17407 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
, sa
));
17413 if (! restoring_FPRs_inline
)
17414 p
= rtvec_alloc (4 + 64 - info
->first_fp_reg_save
);
17416 p
= rtvec_alloc (2);
17418 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
17419 RTVEC_ELT (p
, 1) = (restoring_FPRs_inline
17420 ? gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 65))
17421 : gen_rtx_CLOBBER (VOIDmode
,
17422 gen_rtx_REG (Pmode
, 65)));
17424 /* If we have to restore more than two FP registers, branch to the
17425 restore function. It will return to our caller. */
17426 if (! restoring_FPRs_inline
)
17431 sym
= rs6000_savres_routine_sym (info
,
17435 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
, sym
);
17436 RTVEC_ELT (p
, 3) = gen_rtx_USE (VOIDmode
,
17437 gen_rtx_REG (Pmode
, 11));
17438 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
17441 addr
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
,
17442 GEN_INT (info
->fp_save_offset
+ 8*i
));
17443 mem
= gen_frame_mem (DFmode
, addr
);
17445 RTVEC_ELT (p
, i
+4) =
17446 gen_rtx_SET (VOIDmode
,
17447 gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
),
17452 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
17456 /* Write function epilogue. */
17459 rs6000_output_function_epilogue (FILE *file
,
17460 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
17462 if (! HAVE_epilogue
)
17464 rtx insn
= get_last_insn ();
17465 /* If the last insn was a BARRIER, we don't have to write anything except
17466 the trace table. */
17467 if (GET_CODE (insn
) == NOTE
)
17468 insn
= prev_nonnote_insn (insn
);
17469 if (insn
== 0 || GET_CODE (insn
) != BARRIER
)
17471 /* This is slightly ugly, but at least we don't have two
17472 copies of the epilogue-emitting code. */
17475 /* A NOTE_INSN_DELETED is supposed to be at the start
17476 and end of the "toplevel" insn chain. */
17477 emit_note (NOTE_INSN_DELETED
);
17478 rs6000_emit_epilogue (FALSE
);
17479 emit_note (NOTE_INSN_DELETED
);
17481 /* Expand INSN_ADDRESSES so final() doesn't crash. */
17485 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
17487 INSN_ADDRESSES_NEW (insn
, addr
);
17492 if (TARGET_DEBUG_STACK
)
17493 debug_rtx_list (get_insns (), 100);
17494 final (get_insns (), file
, FALSE
);
17500 macho_branch_islands ();
17501 /* Mach-O doesn't support labels at the end of objects, so if
17502 it looks like we might want one, insert a NOP. */
17504 rtx insn
= get_last_insn ();
17507 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
17508 insn
= PREV_INSN (insn
);
17512 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
17513 fputs ("\tnop\n", file
);
17517 /* Output a traceback table here. See /usr/include/sys/debug.h for info
17520 We don't output a traceback table if -finhibit-size-directive was
17521 used. The documentation for -finhibit-size-directive reads
17522 ``don't output a @code{.size} assembler directive, or anything
17523 else that would cause trouble if the function is split in the
17524 middle, and the two halves are placed at locations far apart in
17525 memory.'' The traceback table has this property, since it
17526 includes the offset from the start of the function to the
17527 traceback table itself.
17529 System V.4 Powerpc's (and the embedded ABI derived from it) use a
17530 different traceback table. */
17531 if (DEFAULT_ABI
== ABI_AIX
&& ! flag_inhibit_size_directive
17532 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
17534 const char *fname
= NULL
;
17535 const char *language_string
= lang_hooks
.name
;
17536 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
17538 int optional_tbtab
;
17539 rs6000_stack_t
*info
= rs6000_stack_info ();
17541 if (rs6000_traceback
== traceback_full
)
17542 optional_tbtab
= 1;
17543 else if (rs6000_traceback
== traceback_part
)
17544 optional_tbtab
= 0;
17546 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
17548 if (optional_tbtab
)
17550 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
17551 while (*fname
== '.') /* V.4 encodes . in the name */
17554 /* Need label immediately before tbtab, so we can compute
17555 its offset from the function start. */
17556 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
17557 ASM_OUTPUT_LABEL (file
, fname
);
17560 /* The .tbtab pseudo-op can only be used for the first eight
17561 expressions, since it can't handle the possibly variable
17562 length fields that follow. However, if you omit the optional
17563 fields, the assembler outputs zeros for all optional fields
17564 anyways, giving each variable length field is minimum length
17565 (as defined in sys/debug.h). Thus we can not use the .tbtab
17566 pseudo-op at all. */
17568 /* An all-zero word flags the start of the tbtab, for debuggers
17569 that have to find it by searching forward from the entry
17570 point or from the current pc. */
17571 fputs ("\t.long 0\n", file
);
17573 /* Tbtab format type. Use format type 0. */
17574 fputs ("\t.byte 0,", file
);
17576 /* Language type. Unfortunately, there does not seem to be any
17577 official way to discover the language being compiled, so we
17578 use language_string.
17579 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
17580 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
17581 a number, so for now use 9. */
17582 if (! strcmp (language_string
, "GNU C"))
17584 else if (! strcmp (language_string
, "GNU F77")
17585 || ! strcmp (language_string
, "GNU Fortran"))
17587 else if (! strcmp (language_string
, "GNU Pascal"))
17589 else if (! strcmp (language_string
, "GNU Ada"))
17591 else if (! strcmp (language_string
, "GNU C++")
17592 || ! strcmp (language_string
, "GNU Objective-C++"))
17594 else if (! strcmp (language_string
, "GNU Java"))
17596 else if (! strcmp (language_string
, "GNU Objective-C"))
17599 gcc_unreachable ();
17600 fprintf (file
, "%d,", i
);
17602 /* 8 single bit fields: global linkage (not set for C extern linkage,
17603 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
17604 from start of procedure stored in tbtab, internal function, function
17605 has controlled storage, function has no toc, function uses fp,
17606 function logs/aborts fp operations. */
17607 /* Assume that fp operations are used if any fp reg must be saved. */
17608 fprintf (file
, "%d,",
17609 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
17611 /* 6 bitfields: function is interrupt handler, name present in
17612 proc table, function calls alloca, on condition directives
17613 (controls stack walks, 3 bits), saves condition reg, saves
17615 /* The `function calls alloca' bit seems to be set whenever reg 31 is
17616 set up as a frame pointer, even when there is no alloca call. */
17617 fprintf (file
, "%d,",
17618 ((optional_tbtab
<< 6)
17619 | ((optional_tbtab
& frame_pointer_needed
) << 5)
17620 | (info
->cr_save_p
<< 1)
17621 | (info
->lr_save_p
)));
17623 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
17625 fprintf (file
, "%d,",
17626 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
17628 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
17629 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
17631 if (optional_tbtab
)
17633 /* Compute the parameter info from the function decl argument
17636 int next_parm_info_bit
= 31;
17638 for (decl
= DECL_ARGUMENTS (current_function_decl
);
17639 decl
; decl
= TREE_CHAIN (decl
))
17641 rtx parameter
= DECL_INCOMING_RTL (decl
);
17642 enum machine_mode mode
= GET_MODE (parameter
);
17644 if (GET_CODE (parameter
) == REG
)
17646 if (SCALAR_FLOAT_MODE_P (mode
))
17667 gcc_unreachable ();
17670 /* If only one bit will fit, don't or in this entry. */
17671 if (next_parm_info_bit
> 0)
17672 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
17673 next_parm_info_bit
-= 2;
17677 fixed_parms
+= ((GET_MODE_SIZE (mode
)
17678 + (UNITS_PER_WORD
- 1))
17680 next_parm_info_bit
-= 1;
17686 /* Number of fixed point parameters. */
17687 /* This is actually the number of words of fixed point parameters; thus
17688 an 8 byte struct counts as 2; and thus the maximum value is 8. */
17689 fprintf (file
, "%d,", fixed_parms
);
17691 /* 2 bitfields: number of floating point parameters (7 bits), parameters
17693 /* This is actually the number of fp registers that hold parameters;
17694 and thus the maximum value is 13. */
17695 /* Set parameters on stack bit if parameters are not in their original
17696 registers, regardless of whether they are on the stack? Xlc
17697 seems to set the bit when not optimizing. */
17698 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
17700 if (! optional_tbtab
)
17703 /* Optional fields follow. Some are variable length. */
17705 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
17706 11 double float. */
17707 /* There is an entry for each parameter in a register, in the order that
17708 they occur in the parameter list. Any intervening arguments on the
17709 stack are ignored. If the list overflows a long (max possible length
17710 34 bits) then completely leave off all elements that don't fit. */
17711 /* Only emit this long if there was at least one parameter. */
17712 if (fixed_parms
|| float_parms
)
17713 fprintf (file
, "\t.long %d\n", parm_info
);
17715 /* Offset from start of code to tb table. */
17716 fputs ("\t.long ", file
);
17717 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
17719 RS6000_OUTPUT_BASENAME (file
, fname
);
17721 assemble_name (file
, fname
);
17723 rs6000_output_function_entry (file
, fname
);
17726 /* Interrupt handler mask. */
17727 /* Omit this long, since we never set the interrupt handler bit
17730 /* Number of CTL (controlled storage) anchors. */
17731 /* Omit this long, since the has_ctl bit is never set above. */
17733 /* Displacement into stack of each CTL anchor. */
17734 /* Omit this list of longs, because there are no CTL anchors. */
17736 /* Length of function name. */
17739 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
17741 /* Function name. */
17742 assemble_string (fname
, strlen (fname
));
17744 /* Register for alloca automatic storage; this is always reg 31.
17745 Only emit this if the alloca bit was set above. */
17746 if (frame_pointer_needed
)
17747 fputs ("\t.byte 31\n", file
);
17749 fputs ("\t.align 2\n", file
);
17753 /* A C compound statement that outputs the assembler code for a thunk
17754 function, used to implement C++ virtual function calls with
17755 multiple inheritance. The thunk acts as a wrapper around a virtual
17756 function, adjusting the implicit object parameter before handing
17757 control off to the real function.
17759 First, emit code to add the integer DELTA to the location that
17760 contains the incoming first argument. Assume that this argument
17761 contains a pointer, and is the one used to pass the `this' pointer
17762 in C++. This is the incoming argument *before* the function
17763 prologue, e.g. `%o0' on a sparc. The addition must preserve the
17764 values of all other incoming arguments.
17766 After the addition, emit code to jump to FUNCTION, which is a
17767 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
17768 not touch the return address. Hence returning from FUNCTION will
17769 return to whoever called the current `thunk'.
17771 The effect must be as if FUNCTION had been called directly with the
17772 adjusted first argument. This macro is responsible for emitting
17773 all of the code for a thunk function; output_function_prologue()
17774 and output_function_epilogue() are not invoked.
17776 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
17777 been extracted from it.) It might possibly be useful on some
17778 targets, but probably not.
17780 If you do not define this macro, the target-independent code in the
17781 C++ frontend will generate a less efficient heavyweight thunk that
17782 calls FUNCTION instead of jumping to it. The generic approach does
17783 not support varargs. */
17786 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
17787 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
17790 rtx this_rtx
, insn
, funexp
;
17792 reload_completed
= 1;
17793 epilogue_completed
= 1;
17795 /* Mark the end of the (empty) prologue. */
17796 emit_note (NOTE_INSN_PROLOGUE_END
);
17798 /* Find the "this" pointer. If the function returns a structure,
17799 the structure return pointer is in r3. */
17800 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
17801 this_rtx
= gen_rtx_REG (Pmode
, 4);
17803 this_rtx
= gen_rtx_REG (Pmode
, 3);
17805 /* Apply the constant offset, if required. */
17808 rtx delta_rtx
= GEN_INT (delta
);
17809 emit_insn (TARGET_32BIT
17810 ? gen_addsi3 (this_rtx
, this_rtx
, delta_rtx
)
17811 : gen_adddi3 (this_rtx
, this_rtx
, delta_rtx
));
17814 /* Apply the offset from the vtable, if required. */
17817 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
17818 rtx tmp
= gen_rtx_REG (Pmode
, 12);
17820 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
17821 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
17823 emit_insn (TARGET_32BIT
17824 ? gen_addsi3 (tmp
, tmp
, vcall_offset_rtx
)
17825 : gen_adddi3 (tmp
, tmp
, vcall_offset_rtx
));
17826 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
17830 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
17832 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
17834 emit_insn (TARGET_32BIT
17835 ? gen_addsi3 (this_rtx
, this_rtx
, tmp
)
17836 : gen_adddi3 (this_rtx
, this_rtx
, tmp
));
17839 /* Generate a tail call to the target function. */
17840 if (!TREE_USED (function
))
17842 assemble_external (function
);
17843 TREE_USED (function
) = 1;
17845 funexp
= XEXP (DECL_RTL (function
), 0);
17846 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
17849 if (MACHOPIC_INDIRECT
)
17850 funexp
= machopic_indirect_call_target (funexp
);
17853 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
17854 generate sibcall RTL explicitly. */
17855 insn
= emit_call_insn (
17856 gen_rtx_PARALLEL (VOIDmode
,
17858 gen_rtx_CALL (VOIDmode
,
17859 funexp
, const0_rtx
),
17860 gen_rtx_USE (VOIDmode
, const0_rtx
),
17861 gen_rtx_USE (VOIDmode
,
17862 gen_rtx_REG (SImode
,
17864 gen_rtx_RETURN (VOIDmode
))));
17865 SIBLING_CALL_P (insn
) = 1;
17868 /* Run just enough of rest_of_compilation to get the insns emitted.
17869 There's not really enough bulk here to make other passes such as
17870 instruction scheduling worth while. Note that use_thunk calls
17871 assemble_start_function and assemble_end_function. */
17872 insn
= get_insns ();
17873 insn_locators_alloc ();
17874 shorten_branches (insn
);
17875 final_start_function (insn
, file
, 1);
17876 final (insn
, file
, 1);
17877 final_end_function ();
17878 free_after_compilation (cfun
);
17880 reload_completed
= 0;
17881 epilogue_completed
= 0;
17884 /* A quick summary of the various types of 'constant-pool tables'
17887 Target Flags Name One table per
17888 AIX (none) AIX TOC object file
17889 AIX -mfull-toc AIX TOC object file
17890 AIX -mminimal-toc AIX minimal TOC translation unit
17891 SVR4/EABI (none) SVR4 SDATA object file
17892 SVR4/EABI -fpic SVR4 pic object file
17893 SVR4/EABI -fPIC SVR4 PIC translation unit
17894 SVR4/EABI -mrelocatable EABI TOC function
17895 SVR4/EABI -maix AIX TOC object file
17896 SVR4/EABI -maix -mminimal-toc
17897 AIX minimal TOC translation unit
17899 Name Reg. Set by entries contains:
17900 made by addrs? fp? sum?
17902 AIX TOC 2 crt0 as Y option option
17903 AIX minimal TOC 30 prolog gcc Y Y option
17904 SVR4 SDATA 13 crt0 gcc N Y N
17905 SVR4 pic 30 prolog ld Y not yet N
17906 SVR4 PIC 30 prolog gcc Y option option
17907 EABI TOC 30 prolog gcc Y option option
17911 /* Hash functions for the hash table. */
17914 rs6000_hash_constant (rtx k
)
17916 enum rtx_code code
= GET_CODE (k
);
17917 enum machine_mode mode
= GET_MODE (k
);
17918 unsigned result
= (code
<< 3) ^ mode
;
17919 const char *format
;
17922 format
= GET_RTX_FORMAT (code
);
17923 flen
= strlen (format
);
17929 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
17932 if (mode
!= VOIDmode
)
17933 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
17945 for (; fidx
< flen
; fidx
++)
17946 switch (format
[fidx
])
17951 const char *str
= XSTR (k
, fidx
);
17952 len
= strlen (str
);
17953 result
= result
* 613 + len
;
17954 for (i
= 0; i
< len
; i
++)
17955 result
= result
* 613 + (unsigned) str
[i
];
17960 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
17964 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
17967 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
17968 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
17972 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
17973 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
17980 gcc_unreachable ();
17987 toc_hash_function (const void *hash_entry
)
17989 const struct toc_hash_struct
*thc
=
17990 (const struct toc_hash_struct
*) hash_entry
;
17991 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
17994 /* Compare H1 and H2 for equivalence. */
17997 toc_hash_eq (const void *h1
, const void *h2
)
17999 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
18000 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
18002 if (((const struct toc_hash_struct
*) h1
)->key_mode
18003 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
18006 return rtx_equal_p (r1
, r2
);
18009 /* These are the names given by the C++ front-end to vtables, and
18010 vtable-like objects. Ideally, this logic should not be here;
18011 instead, there should be some programmatic way of inquiring as
18012 to whether or not an object is a vtable. */
18014 #define VTABLE_NAME_P(NAME) \
18015 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
18016 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
18017 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
18018 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
18019 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
18021 #ifdef NO_DOLLAR_IN_LABEL
18022 /* Return a GGC-allocated character string translating dollar signs in
18023 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
18026 rs6000_xcoff_strip_dollar (const char *name
)
18031 p
= strchr (name
, '$');
18033 if (p
== 0 || p
== name
)
18036 len
= strlen (name
);
18037 strip
= (char *) alloca (len
+ 1);
18038 strcpy (strip
, name
);
18039 p
= strchr (strip
, '$');
18043 p
= strchr (p
+ 1, '$');
18046 return ggc_alloc_string (strip
, len
);
18051 rs6000_output_symbol_ref (FILE *file
, rtx x
)
18053 /* Currently C++ toc references to vtables can be emitted before it
18054 is decided whether the vtable is public or private. If this is
18055 the case, then the linker will eventually complain that there is
18056 a reference to an unknown section. Thus, for vtables only,
18057 we emit the TOC reference to reference the symbol and not the
18059 const char *name
= XSTR (x
, 0);
18061 if (VTABLE_NAME_P (name
))
18063 RS6000_OUTPUT_BASENAME (file
, name
);
18066 assemble_name (file
, name
);
18069 /* Output a TOC entry. We derive the entry name from what is being
18073 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
18076 const char *name
= buf
;
18078 HOST_WIDE_INT offset
= 0;
18080 gcc_assert (!TARGET_NO_TOC
);
18082 /* When the linker won't eliminate them, don't output duplicate
18083 TOC entries (this happens on AIX if there is any kind of TOC,
18084 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
18086 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
18088 struct toc_hash_struct
*h
;
18091 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
18092 time because GGC is not initialized at that point. */
18093 if (toc_hash_table
== NULL
)
18094 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
18095 toc_hash_eq
, NULL
);
18097 h
= GGC_NEW (struct toc_hash_struct
);
18099 h
->key_mode
= mode
;
18100 h
->labelno
= labelno
;
18102 found
= htab_find_slot (toc_hash_table
, h
, INSERT
);
18103 if (*found
== NULL
)
18105 else /* This is indeed a duplicate.
18106 Set this label equal to that label. */
18108 fputs ("\t.set ", file
);
18109 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
18110 fprintf (file
, "%d,", labelno
);
18111 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
18112 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
18118 /* If we're going to put a double constant in the TOC, make sure it's
18119 aligned properly when strict alignment is on. */
18120 if (GET_CODE (x
) == CONST_DOUBLE
18121 && STRICT_ALIGNMENT
18122 && GET_MODE_BITSIZE (mode
) >= 64
18123 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
18124 ASM_OUTPUT_ALIGN (file
, 3);
18127 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
18129 /* Handle FP constants specially. Note that if we have a minimal
18130 TOC, things we put here aren't actually in the TOC, so we can allow
18132 if (GET_CODE (x
) == CONST_DOUBLE
&&
18133 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
))
18135 REAL_VALUE_TYPE rv
;
18138 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
18139 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
18140 REAL_VALUE_TO_TARGET_DECIMAL128 (rv
, k
);
18142 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
18146 if (TARGET_MINIMAL_TOC
)
18147 fputs (DOUBLE_INT_ASM_OP
, file
);
18149 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
18150 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
18151 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
18152 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
18153 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
18154 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
18159 if (TARGET_MINIMAL_TOC
)
18160 fputs ("\t.long ", file
);
18162 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
18163 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
18164 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
18165 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
18166 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
18167 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
18171 else if (GET_CODE (x
) == CONST_DOUBLE
&&
18172 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
18174 REAL_VALUE_TYPE rv
;
18177 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
18179 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
18180 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, k
);
18182 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
18186 if (TARGET_MINIMAL_TOC
)
18187 fputs (DOUBLE_INT_ASM_OP
, file
);
18189 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
18190 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
18191 fprintf (file
, "0x%lx%08lx\n",
18192 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
18197 if (TARGET_MINIMAL_TOC
)
18198 fputs ("\t.long ", file
);
18200 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
18201 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
18202 fprintf (file
, "0x%lx,0x%lx\n",
18203 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
18207 else if (GET_CODE (x
) == CONST_DOUBLE
&&
18208 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
18210 REAL_VALUE_TYPE rv
;
18213 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
18214 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
18215 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
18217 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
18221 if (TARGET_MINIMAL_TOC
)
18222 fputs (DOUBLE_INT_ASM_OP
, file
);
18224 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
18225 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
18230 if (TARGET_MINIMAL_TOC
)
18231 fputs ("\t.long ", file
);
18233 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
18234 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
18238 else if (GET_MODE (x
) == VOIDmode
18239 && (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
))
18241 unsigned HOST_WIDE_INT low
;
18242 HOST_WIDE_INT high
;
18244 if (GET_CODE (x
) == CONST_DOUBLE
)
18246 low
= CONST_DOUBLE_LOW (x
);
18247 high
= CONST_DOUBLE_HIGH (x
);
18250 #if HOST_BITS_PER_WIDE_INT == 32
18253 high
= (low
& 0x80000000) ? ~0 : 0;
18257 low
= INTVAL (x
) & 0xffffffff;
18258 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
18262 /* TOC entries are always Pmode-sized, but since this
18263 is a bigendian machine then if we're putting smaller
18264 integer constants in the TOC we have to pad them.
18265 (This is still a win over putting the constants in
18266 a separate constant pool, because then we'd have
18267 to have both a TOC entry _and_ the actual constant.)
18269 For a 32-bit target, CONST_INT values are loaded and shifted
18270 entirely within `low' and can be stored in one TOC entry. */
18272 /* It would be easy to make this work, but it doesn't now. */
18273 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
18275 if (POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
18277 #if HOST_BITS_PER_WIDE_INT == 32
18278 lshift_double (low
, high
, POINTER_SIZE
- GET_MODE_BITSIZE (mode
),
18279 POINTER_SIZE
, &low
, &high
, 0);
18282 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
18283 high
= (HOST_WIDE_INT
) low
>> 32;
18290 if (TARGET_MINIMAL_TOC
)
18291 fputs (DOUBLE_INT_ASM_OP
, file
);
18293 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
18294 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
18295 fprintf (file
, "0x%lx%08lx\n",
18296 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
18301 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
18303 if (TARGET_MINIMAL_TOC
)
18304 fputs ("\t.long ", file
);
18306 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
18307 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
18308 fprintf (file
, "0x%lx,0x%lx\n",
18309 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
18313 if (TARGET_MINIMAL_TOC
)
18314 fputs ("\t.long ", file
);
18316 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
18317 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
18323 if (GET_CODE (x
) == CONST
)
18325 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
);
18327 base
= XEXP (XEXP (x
, 0), 0);
18328 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
18331 switch (GET_CODE (base
))
18334 name
= XSTR (base
, 0);
18338 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
18339 CODE_LABEL_NUMBER (XEXP (base
, 0)));
18343 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
18347 gcc_unreachable ();
18350 if (TARGET_MINIMAL_TOC
)
18351 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
18354 fputs ("\t.tc ", file
);
18355 RS6000_OUTPUT_BASENAME (file
, name
);
18358 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
18360 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
18362 fputs ("[TC],", file
);
18365 /* Currently C++ toc references to vtables can be emitted before it
18366 is decided whether the vtable is public or private. If this is
18367 the case, then the linker will eventually complain that there is
18368 a TOC reference to an unknown section. Thus, for vtables only,
18369 we emit the TOC reference to reference the symbol and not the
18371 if (VTABLE_NAME_P (name
))
18373 RS6000_OUTPUT_BASENAME (file
, name
);
18375 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
18376 else if (offset
> 0)
18377 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
18380 output_addr_const (file
, x
);
18384 /* Output an assembler pseudo-op to write an ASCII string of N characters
18385 starting at P to FILE.
18387 On the RS/6000, we have to do this using the .byte operation and
18388 write out special characters outside the quoted string.
18389 Also, the assembler is broken; very long strings are truncated,
18390 so we must artificially break them up early. */
18393 output_ascii (FILE *file
, const char *p
, int n
)
18396 int i
, count_string
;
18397 const char *for_string
= "\t.byte \"";
18398 const char *for_decimal
= "\t.byte ";
18399 const char *to_close
= NULL
;
18402 for (i
= 0; i
< n
; i
++)
18405 if (c
>= ' ' && c
< 0177)
18408 fputs (for_string
, file
);
18411 /* Write two quotes to get one. */
18419 for_decimal
= "\"\n\t.byte ";
18423 if (count_string
>= 512)
18425 fputs (to_close
, file
);
18427 for_string
= "\t.byte \"";
18428 for_decimal
= "\t.byte ";
18436 fputs (for_decimal
, file
);
18437 fprintf (file
, "%d", c
);
18439 for_string
= "\n\t.byte \"";
18440 for_decimal
= ", ";
18446 /* Now close the string if we have written one. Then end the line. */
18448 fputs (to_close
, file
);
18451 /* Generate a unique section name for FILENAME for a section type
18452 represented by SECTION_DESC. Output goes into BUF.
18454 SECTION_DESC can be any string, as long as it is different for each
18455 possible section type.
18457 We name the section in the same manner as xlc. The name begins with an
18458 underscore followed by the filename (after stripping any leading directory
18459 names) with the last period replaced by the string SECTION_DESC. If
18460 FILENAME does not contain a period, SECTION_DESC is appended to the end of
18464 rs6000_gen_section_name (char **buf
, const char *filename
,
18465 const char *section_desc
)
18467 const char *q
, *after_last_slash
, *last_period
= 0;
18471 after_last_slash
= filename
;
18472 for (q
= filename
; *q
; q
++)
18475 after_last_slash
= q
+ 1;
18476 else if (*q
== '.')
18480 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
18481 *buf
= (char *) xmalloc (len
);
18486 for (q
= after_last_slash
; *q
; q
++)
18488 if (q
== last_period
)
18490 strcpy (p
, section_desc
);
18491 p
+= strlen (section_desc
);
18495 else if (ISALNUM (*q
))
18499 if (last_period
== 0)
18500 strcpy (p
, section_desc
);
18505 /* Emit profile function. */
18508 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
18510 /* Non-standard profiling for kernels, which just saves LR then calls
18511 _mcount without worrying about arg saves. The idea is to change
18512 the function prologue as little as possible as it isn't easy to
18513 account for arg save/restore code added just for _mcount. */
18514 if (TARGET_PROFILE_KERNEL
)
18517 if (DEFAULT_ABI
== ABI_AIX
)
18519 #ifndef NO_PROFILE_COUNTERS
18520 # define NO_PROFILE_COUNTERS 0
18522 if (NO_PROFILE_COUNTERS
)
18523 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
18524 LCT_NORMAL
, VOIDmode
, 0);
18528 const char *label_name
;
18531 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
18532 label_name
= (*targetm
.strip_name_encoding
) (ggc_strdup (buf
));
18533 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
18535 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
18536 LCT_NORMAL
, VOIDmode
, 1, fun
, Pmode
);
18539 else if (DEFAULT_ABI
== ABI_DARWIN
)
18541 const char *mcount_name
= RS6000_MCOUNT
;
18542 int caller_addr_regno
= LR_REGNO
;
18544 /* Be conservative and always set this, at least for now. */
18545 crtl
->uses_pic_offset_table
= 1;
18548 /* For PIC code, set up a stub and collect the caller's address
18549 from r0, which is where the prologue puts it. */
18550 if (MACHOPIC_INDIRECT
18551 && crtl
->uses_pic_offset_table
)
18552 caller_addr_regno
= 0;
18554 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
18555 LCT_NORMAL
, VOIDmode
, 1,
18556 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
18560 /* Write function profiler code. */
18563 output_function_profiler (FILE *file
, int labelno
)
18567 switch (DEFAULT_ABI
)
18570 gcc_unreachable ();
18575 warning (0, "no profiling of 64-bit code for this ABI");
18578 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
18579 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
18580 if (NO_PROFILE_COUNTERS
)
18582 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
18583 reg_names
[0], reg_names
[1]);
18585 else if (TARGET_SECURE_PLT
&& flag_pic
)
18587 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
18588 reg_names
[0], reg_names
[1]);
18589 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
18590 asm_fprintf (file
, "\t{cau|addis} %s,%s,",
18591 reg_names
[12], reg_names
[12]);
18592 assemble_name (file
, buf
);
18593 asm_fprintf (file
, "-1b@ha\n\t{cal|la} %s,", reg_names
[0]);
18594 assemble_name (file
, buf
);
18595 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
18597 else if (flag_pic
== 1)
18599 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
18600 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
18601 reg_names
[0], reg_names
[1]);
18602 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
18603 asm_fprintf (file
, "\t{l|lwz} %s,", reg_names
[0]);
18604 assemble_name (file
, buf
);
18605 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
18607 else if (flag_pic
> 1)
18609 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
18610 reg_names
[0], reg_names
[1]);
18611 /* Now, we need to get the address of the label. */
18612 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
18613 assemble_name (file
, buf
);
18614 fputs ("-.\n1:", file
);
18615 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
18616 asm_fprintf (file
, "\t{l|lwz} %s,0(%s)\n",
18617 reg_names
[0], reg_names
[11]);
18618 asm_fprintf (file
, "\t{cax|add} %s,%s,%s\n",
18619 reg_names
[0], reg_names
[0], reg_names
[11]);
18623 asm_fprintf (file
, "\t{liu|lis} %s,", reg_names
[12]);
18624 assemble_name (file
, buf
);
18625 fputs ("@ha\n", file
);
18626 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
18627 reg_names
[0], reg_names
[1]);
18628 asm_fprintf (file
, "\t{cal|la} %s,", reg_names
[0]);
18629 assemble_name (file
, buf
);
18630 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
18633 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
18634 fprintf (file
, "\tbl %s%s\n",
18635 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
18640 if (!TARGET_PROFILE_KERNEL
)
18642 /* Don't do anything, done in output_profile_hook (). */
18646 gcc_assert (!TARGET_32BIT
);
18648 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
18649 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
18651 if (cfun
->static_chain_decl
!= NULL
)
18653 asm_fprintf (file
, "\tstd %s,24(%s)\n",
18654 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
18655 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
18656 asm_fprintf (file
, "\tld %s,24(%s)\n",
18657 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
18660 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
18668 /* The following variable value is the last issued insn. */
18670 static rtx last_scheduled_insn
;
18672 /* The following variable helps to balance issuing of load and
18673 store instructions */
18675 static int load_store_pendulum
;
18677 /* Power4 load update and store update instructions are cracked into a
18678 load or store and an integer insn which are executed in the same cycle.
18679 Branches have their own dispatch slot which does not count against the
18680 GCC issue rate, but it changes the program flow so there are no other
18681 instructions to issue in this cycle. */
18684 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED
,
18685 int verbose ATTRIBUTE_UNUSED
,
18686 rtx insn
, int more
)
18688 last_scheduled_insn
= insn
;
18689 if (GET_CODE (PATTERN (insn
)) == USE
18690 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
18692 cached_can_issue_more
= more
;
18693 return cached_can_issue_more
;
18696 if (insn_terminates_group_p (insn
, current_group
))
18698 cached_can_issue_more
= 0;
18699 return cached_can_issue_more
;
18702 /* If no reservation, but reach here */
18703 if (recog_memoized (insn
) < 0)
18706 if (rs6000_sched_groups
)
18708 if (is_microcoded_insn (insn
))
18709 cached_can_issue_more
= 0;
18710 else if (is_cracked_insn (insn
))
18711 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
18713 cached_can_issue_more
= more
- 1;
18715 return cached_can_issue_more
;
18718 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
18721 cached_can_issue_more
= more
- 1;
18722 return cached_can_issue_more
;
18725 /* Adjust the cost of a scheduling dependency. Return the new cost of
18726 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
18729 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
18731 enum attr_type attr_type
;
18733 if (! recog_memoized (insn
))
18736 switch (REG_NOTE_KIND (link
))
18740 /* Data dependency; DEP_INSN writes a register that INSN reads
18741 some cycles later. */
18743 /* Separate a load from a narrower, dependent store. */
18744 if (rs6000_sched_groups
18745 && GET_CODE (PATTERN (insn
)) == SET
18746 && GET_CODE (PATTERN (dep_insn
)) == SET
18747 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
18748 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
18749 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
18750 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
18753 attr_type
= get_attr_type (insn
);
18758 /* Tell the first scheduling pass about the latency between
18759 a mtctr and bctr (and mtlr and br/blr). The first
18760 scheduling pass will not know about this latency since
18761 the mtctr instruction, which has the latency associated
18762 to it, will be generated by reload. */
18763 return TARGET_POWER
? 5 : 4;
18765 /* Leave some extra cycles between a compare and its
18766 dependent branch, to inhibit expensive mispredicts. */
18767 if ((rs6000_cpu_attr
== CPU_PPC603
18768 || rs6000_cpu_attr
== CPU_PPC604
18769 || rs6000_cpu_attr
== CPU_PPC604E
18770 || rs6000_cpu_attr
== CPU_PPC620
18771 || rs6000_cpu_attr
== CPU_PPC630
18772 || rs6000_cpu_attr
== CPU_PPC750
18773 || rs6000_cpu_attr
== CPU_PPC7400
18774 || rs6000_cpu_attr
== CPU_PPC7450
18775 || rs6000_cpu_attr
== CPU_POWER4
18776 || rs6000_cpu_attr
== CPU_POWER5
18777 || rs6000_cpu_attr
== CPU_CELL
)
18778 && recog_memoized (dep_insn
)
18779 && (INSN_CODE (dep_insn
) >= 0))
18781 switch (get_attr_type (dep_insn
))
18785 case TYPE_DELAYED_COMPARE
:
18786 case TYPE_IMUL_COMPARE
:
18787 case TYPE_LMUL_COMPARE
:
18788 case TYPE_FPCOMPARE
:
18789 case TYPE_CR_LOGICAL
:
18790 case TYPE_DELAYED_CR
:
18799 case TYPE_STORE_UX
:
18801 case TYPE_FPSTORE_U
:
18802 case TYPE_FPSTORE_UX
:
18803 if ((rs6000_cpu
== PROCESSOR_POWER6
)
18804 && recog_memoized (dep_insn
)
18805 && (INSN_CODE (dep_insn
) >= 0))
18808 if (GET_CODE (PATTERN (insn
)) != SET
)
18809 /* If this happens, we have to extend this to schedule
18810 optimally. Return default for now. */
18813 /* Adjust the cost for the case where the value written
18814 by a fixed point operation is used as the address
18815 gen value on a store. */
18816 switch (get_attr_type (dep_insn
))
18823 if (! store_data_bypass_p (dep_insn
, insn
))
18827 case TYPE_LOAD_EXT
:
18828 case TYPE_LOAD_EXT_U
:
18829 case TYPE_LOAD_EXT_UX
:
18830 case TYPE_VAR_SHIFT_ROTATE
:
18831 case TYPE_VAR_DELAYED_COMPARE
:
18833 if (! store_data_bypass_p (dep_insn
, insn
))
18839 case TYPE_FAST_COMPARE
:
18842 case TYPE_INSERT_WORD
:
18843 case TYPE_INSERT_DWORD
:
18844 case TYPE_FPLOAD_U
:
18845 case TYPE_FPLOAD_UX
:
18847 case TYPE_STORE_UX
:
18848 case TYPE_FPSTORE_U
:
18849 case TYPE_FPSTORE_UX
:
18851 if (! store_data_bypass_p (dep_insn
, insn
))
18859 case TYPE_IMUL_COMPARE
:
18860 case TYPE_LMUL_COMPARE
:
18862 if (! store_data_bypass_p (dep_insn
, insn
))
18868 if (! store_data_bypass_p (dep_insn
, insn
))
18874 if (! store_data_bypass_p (dep_insn
, insn
))
18887 case TYPE_LOAD_EXT
:
18888 case TYPE_LOAD_EXT_U
:
18889 case TYPE_LOAD_EXT_UX
:
18890 if ((rs6000_cpu
== PROCESSOR_POWER6
)
18891 && recog_memoized (dep_insn
)
18892 && (INSN_CODE (dep_insn
) >= 0))
18895 /* Adjust the cost for the case where the value written
18896 by a fixed point instruction is used within the address
18897 gen portion of a subsequent load(u)(x) */
18898 switch (get_attr_type (dep_insn
))
18905 if (set_to_load_agen (dep_insn
, insn
))
18909 case TYPE_LOAD_EXT
:
18910 case TYPE_LOAD_EXT_U
:
18911 case TYPE_LOAD_EXT_UX
:
18912 case TYPE_VAR_SHIFT_ROTATE
:
18913 case TYPE_VAR_DELAYED_COMPARE
:
18915 if (set_to_load_agen (dep_insn
, insn
))
18921 case TYPE_FAST_COMPARE
:
18924 case TYPE_INSERT_WORD
:
18925 case TYPE_INSERT_DWORD
:
18926 case TYPE_FPLOAD_U
:
18927 case TYPE_FPLOAD_UX
:
18929 case TYPE_STORE_UX
:
18930 case TYPE_FPSTORE_U
:
18931 case TYPE_FPSTORE_UX
:
18933 if (set_to_load_agen (dep_insn
, insn
))
18941 case TYPE_IMUL_COMPARE
:
18942 case TYPE_LMUL_COMPARE
:
18944 if (set_to_load_agen (dep_insn
, insn
))
18950 if (set_to_load_agen (dep_insn
, insn
))
18956 if (set_to_load_agen (dep_insn
, insn
))
18967 if ((rs6000_cpu
== PROCESSOR_POWER6
)
18968 && recog_memoized (dep_insn
)
18969 && (INSN_CODE (dep_insn
) >= 0)
18970 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
18977 /* Fall out to return default cost. */
18981 case REG_DEP_OUTPUT
:
18982 /* Output dependency; DEP_INSN writes a register that INSN writes some
18984 if ((rs6000_cpu
== PROCESSOR_POWER6
)
18985 && recog_memoized (dep_insn
)
18986 && (INSN_CODE (dep_insn
) >= 0))
18988 attr_type
= get_attr_type (insn
);
18993 if (get_attr_type (dep_insn
) == TYPE_FP
)
18997 if (get_attr_type (dep_insn
) == TYPE_MFFGPR
)
19005 /* Anti dependency; DEP_INSN reads a register that INSN writes some
19010 gcc_unreachable ();
19016 /* The function returns a true if INSN is microcoded.
19017 Return false otherwise. */
19020 is_microcoded_insn (rtx insn
)
19022 if (!insn
|| !INSN_P (insn
)
19023 || GET_CODE (PATTERN (insn
)) == USE
19024 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
19027 if (rs6000_cpu_attr
== CPU_CELL
)
19028 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
19030 if (rs6000_sched_groups
)
19032 enum attr_type type
= get_attr_type (insn
);
19033 if (type
== TYPE_LOAD_EXT_U
19034 || type
== TYPE_LOAD_EXT_UX
19035 || type
== TYPE_LOAD_UX
19036 || type
== TYPE_STORE_UX
19037 || type
== TYPE_MFCR
)
19044 /* The function returns true if INSN is cracked into 2 instructions
19045 by the processor (and therefore occupies 2 issue slots). */
19048 is_cracked_insn (rtx insn
)
19050 if (!insn
|| !INSN_P (insn
)
19051 || GET_CODE (PATTERN (insn
)) == USE
19052 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
19055 if (rs6000_sched_groups
)
19057 enum attr_type type
= get_attr_type (insn
);
19058 if (type
== TYPE_LOAD_U
|| type
== TYPE_STORE_U
19059 || type
== TYPE_FPLOAD_U
|| type
== TYPE_FPSTORE_U
19060 || type
== TYPE_FPLOAD_UX
|| type
== TYPE_FPSTORE_UX
19061 || type
== TYPE_LOAD_EXT
|| type
== TYPE_DELAYED_CR
19062 || type
== TYPE_COMPARE
|| type
== TYPE_DELAYED_COMPARE
19063 || type
== TYPE_IMUL_COMPARE
|| type
== TYPE_LMUL_COMPARE
19064 || type
== TYPE_IDIV
|| type
== TYPE_LDIV
19065 || type
== TYPE_INSERT_WORD
)
19072 /* The function returns true if INSN can be issued only from
19073 the branch slot. */
19076 is_branch_slot_insn (rtx insn
)
19078 if (!insn
|| !INSN_P (insn
)
19079 || GET_CODE (PATTERN (insn
)) == USE
19080 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
19083 if (rs6000_sched_groups
)
19085 enum attr_type type
= get_attr_type (insn
);
19086 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
19094 /* The function returns true if out_inst sets a value that is
19095 used in the address generation computation of in_insn */
19097 set_to_load_agen (rtx out_insn
, rtx in_insn
)
19099 rtx out_set
, in_set
;
19101 /* For performance reasons, only handle the simple case where
19102 both loads are a single_set. */
19103 out_set
= single_set (out_insn
);
19106 in_set
= single_set (in_insn
);
19108 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
19114 /* The function returns true if the target storage location of
19115 out_insn is adjacent to the target storage location of in_insn */
19116 /* Return 1 if memory locations are adjacent. */
19119 adjacent_mem_locations (rtx insn1
, rtx insn2
)
19122 rtx a
= get_store_dest (PATTERN (insn1
));
19123 rtx b
= get_store_dest (PATTERN (insn2
));
19125 if ((GET_CODE (XEXP (a
, 0)) == REG
19126 || (GET_CODE (XEXP (a
, 0)) == PLUS
19127 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
19128 && (GET_CODE (XEXP (b
, 0)) == REG
19129 || (GET_CODE (XEXP (b
, 0)) == PLUS
19130 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
19132 HOST_WIDE_INT val0
= 0, val1
= 0, val_diff
;
19135 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
19137 reg0
= XEXP (XEXP (a
, 0), 0);
19138 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
19141 reg0
= XEXP (a
, 0);
19143 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
19145 reg1
= XEXP (XEXP (b
, 0), 0);
19146 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
19149 reg1
= XEXP (b
, 0);
19151 val_diff
= val1
- val0
;
19153 return ((REGNO (reg0
) == REGNO (reg1
))
19154 && ((MEM_SIZE (a
) && val_diff
== INTVAL (MEM_SIZE (a
)))
19155 || (MEM_SIZE (b
) && val_diff
== -INTVAL (MEM_SIZE (b
)))));
19161 /* A C statement (sans semicolon) to update the integer scheduling
19162 priority INSN_PRIORITY (INSN). Increase the priority to execute the
19163 INSN earlier, reduce the priority to execute INSN later. Do not
19164 define this macro if you do not need to adjust the scheduling
19165 priorities of insns. */
19168 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
19170 /* On machines (like the 750) which have asymmetric integer units,
19171 where one integer unit can do multiply and divides and the other
19172 can't, reduce the priority of multiply/divide so it is scheduled
19173 before other integer operations. */
19176 if (! INSN_P (insn
))
19179 if (GET_CODE (PATTERN (insn
)) == USE
)
19182 switch (rs6000_cpu_attr
) {
19184 switch (get_attr_type (insn
))
19191 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
19192 priority
, priority
);
19193 if (priority
>= 0 && priority
< 0x01000000)
19200 if (insn_must_be_first_in_group (insn
)
19201 && reload_completed
19202 && current_sched_info
->sched_max_insns_priority
19203 && rs6000_sched_restricted_insns_priority
)
19206 /* Prioritize insns that can be dispatched only in the first
19208 if (rs6000_sched_restricted_insns_priority
== 1)
19209 /* Attach highest priority to insn. This means that in
19210 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
19211 precede 'priority' (critical path) considerations. */
19212 return current_sched_info
->sched_max_insns_priority
;
19213 else if (rs6000_sched_restricted_insns_priority
== 2)
19214 /* Increase priority of insn by a minimal amount. This means that in
19215 haifa-sched.c:ready_sort(), only 'priority' (critical path)
19216 considerations precede dispatch-slot restriction considerations. */
19217 return (priority
+ 1);
19220 if (rs6000_cpu
== PROCESSOR_POWER6
19221 && ((load_store_pendulum
== -2 && is_load_insn (insn
))
19222 || (load_store_pendulum
== 2 && is_store_insn (insn
))))
19223 /* Attach highest priority to insn if the scheduler has just issued two
19224 stores and this instruction is a load, or two loads and this instruction
19225 is a store. Power6 wants loads and stores scheduled alternately
19227 return current_sched_info
->sched_max_insns_priority
;
19232 /* Return true if the instruction is nonpipelined on the Cell. */
19234 is_nonpipeline_insn (rtx insn
)
19236 enum attr_type type
;
19237 if (!insn
|| !INSN_P (insn
)
19238 || GET_CODE (PATTERN (insn
)) == USE
19239 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
19242 type
= get_attr_type (insn
);
19243 if (type
== TYPE_IMUL
19244 || type
== TYPE_IMUL2
19245 || type
== TYPE_IMUL3
19246 || type
== TYPE_LMUL
19247 || type
== TYPE_IDIV
19248 || type
== TYPE_LDIV
19249 || type
== TYPE_SDIV
19250 || type
== TYPE_DDIV
19251 || type
== TYPE_SSQRT
19252 || type
== TYPE_DSQRT
19253 || type
== TYPE_MFCR
19254 || type
== TYPE_MFCRF
19255 || type
== TYPE_MFJMPR
)
19263 /* Return how many instructions the machine can issue per cycle. */
19266 rs6000_issue_rate (void)
19268 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
19269 if (!reload_completed
)
19272 switch (rs6000_cpu_attr
) {
19273 case CPU_RIOS1
: /* ? */
19275 case CPU_PPC601
: /* ? */
19284 case CPU_PPCE300C2
:
19285 case CPU_PPCE300C3
:
19286 case CPU_PPCE500MC
:
19303 /* Return how many instructions to look ahead for better insn
19307 rs6000_use_sched_lookahead (void)
19309 if (rs6000_cpu_attr
== CPU_PPC8540
)
19311 if (rs6000_cpu_attr
== CPU_CELL
)
19312 return (reload_completed
? 8 : 0);
19316 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
19318 rs6000_use_sched_lookahead_guard (rtx insn
)
19320 if (rs6000_cpu_attr
!= CPU_CELL
)
19323 if (insn
== NULL_RTX
|| !INSN_P (insn
))
19326 if (!reload_completed
19327 || is_nonpipeline_insn (insn
)
19328 || is_microcoded_insn (insn
))
19334 /* Determine is PAT refers to memory. */
19337 is_mem_ref (rtx pat
)
19343 /* stack_tie does not produce any real memory traffic. */
19344 if (GET_CODE (pat
) == UNSPEC
19345 && XINT (pat
, 1) == UNSPEC_TIE
)
19348 if (GET_CODE (pat
) == MEM
)
19351 /* Recursively process the pattern. */
19352 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
19354 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0 && !ret
; i
--)
19357 ret
|= is_mem_ref (XEXP (pat
, i
));
19358 else if (fmt
[i
] == 'E')
19359 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
19360 ret
|= is_mem_ref (XVECEXP (pat
, i
, j
));
19366 /* Determine if PAT is a PATTERN of a load insn. */
19369 is_load_insn1 (rtx pat
)
19371 if (!pat
|| pat
== NULL_RTX
)
19374 if (GET_CODE (pat
) == SET
)
19375 return is_mem_ref (SET_SRC (pat
));
19377 if (GET_CODE (pat
) == PARALLEL
)
19381 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
19382 if (is_load_insn1 (XVECEXP (pat
, 0, i
)))
19389 /* Determine if INSN loads from memory. */
19392 is_load_insn (rtx insn
)
19394 if (!insn
|| !INSN_P (insn
))
19397 if (GET_CODE (insn
) == CALL_INSN
)
19400 return is_load_insn1 (PATTERN (insn
));
19403 /* Determine if PAT is a PATTERN of a store insn. */
19406 is_store_insn1 (rtx pat
)
19408 if (!pat
|| pat
== NULL_RTX
)
19411 if (GET_CODE (pat
) == SET
)
19412 return is_mem_ref (SET_DEST (pat
));
19414 if (GET_CODE (pat
) == PARALLEL
)
19418 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
19419 if (is_store_insn1 (XVECEXP (pat
, 0, i
)))
19426 /* Determine if INSN stores to memory. */
19429 is_store_insn (rtx insn
)
19431 if (!insn
|| !INSN_P (insn
))
19434 return is_store_insn1 (PATTERN (insn
));
19437 /* Return the dest of a store insn. */
19440 get_store_dest (rtx pat
)
19442 gcc_assert (is_store_insn1 (pat
));
19444 if (GET_CODE (pat
) == SET
)
19445 return SET_DEST (pat
);
19446 else if (GET_CODE (pat
) == PARALLEL
)
19450 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
19452 rtx inner_pat
= XVECEXP (pat
, 0, i
);
19453 if (GET_CODE (inner_pat
) == SET
19454 && is_mem_ref (SET_DEST (inner_pat
)))
19458 /* We shouldn't get here, because we should have either a simple
19459 store insn or a store with update which are covered above. */
19463 /* Returns whether the dependence between INSN and NEXT is considered
19464 costly by the given target. */
19467 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
19472 /* If the flag is not enabled - no dependence is considered costly;
19473 allow all dependent insns in the same group.
19474 This is the most aggressive option. */
19475 if (rs6000_sched_costly_dep
== no_dep_costly
)
19478 /* If the flag is set to 1 - a dependence is always considered costly;
19479 do not allow dependent instructions in the same group.
19480 This is the most conservative option. */
19481 if (rs6000_sched_costly_dep
== all_deps_costly
)
19484 insn
= DEP_PRO (dep
);
19485 next
= DEP_CON (dep
);
19487 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
19488 && is_load_insn (next
)
19489 && is_store_insn (insn
))
19490 /* Prevent load after store in the same group. */
19493 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
19494 && is_load_insn (next
)
19495 && is_store_insn (insn
)
19496 && DEP_TYPE (dep
) == REG_DEP_TRUE
)
19497 /* Prevent load after store in the same group if it is a true
19501 /* The flag is set to X; dependences with latency >= X are considered costly,
19502 and will not be scheduled in the same group. */
19503 if (rs6000_sched_costly_dep
<= max_dep_latency
19504 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
19510 /* Return the next insn after INSN that is found before TAIL is reached,
19511 skipping any "non-active" insns - insns that will not actually occupy
19512 an issue slot. Return NULL_RTX if such an insn is not found. */
19515 get_next_active_insn (rtx insn
, rtx tail
)
19517 if (insn
== NULL_RTX
|| insn
== tail
)
19522 insn
= NEXT_INSN (insn
);
19523 if (insn
== NULL_RTX
|| insn
== tail
)
19528 || (NONJUMP_INSN_P (insn
)
19529 && GET_CODE (PATTERN (insn
)) != USE
19530 && GET_CODE (PATTERN (insn
)) != CLOBBER
19531 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
19537 /* We are about to begin issuing insns for this clock cycle. */
19540 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
19541 rtx
*ready ATTRIBUTE_UNUSED
,
19542 int *pn_ready ATTRIBUTE_UNUSED
,
19543 int clock_var ATTRIBUTE_UNUSED
)
19545 int n_ready
= *pn_ready
;
19548 fprintf (dump
, "// rs6000_sched_reorder :\n");
19550 /* Reorder the ready list, if the second to last ready insn
19551 is a nonepipeline insn. */
19552 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
19554 if (is_nonpipeline_insn (ready
[n_ready
- 1])
19555 && (recog_memoized (ready
[n_ready
- 2]) > 0))
19556 /* Simply swap first two insns. */
19558 rtx tmp
= ready
[n_ready
- 1];
19559 ready
[n_ready
- 1] = ready
[n_ready
- 2];
19560 ready
[n_ready
- 2] = tmp
;
19564 if (rs6000_cpu
== PROCESSOR_POWER6
)
19565 load_store_pendulum
= 0;
19567 return rs6000_issue_rate ();
19570 /* Like rs6000_sched_reorder, but called after issuing each insn. */
19573 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx
*ready
,
19574 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
19577 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
19579 /* For Power6, we need to handle some special cases to try and keep the
19580 store queue from overflowing and triggering expensive flushes.
19582 This code monitors how load and store instructions are being issued
19583 and skews the ready list one way or the other to increase the likelihood
19584 that a desired instruction is issued at the proper time.
19586 A couple of things are done. First, we maintain a "load_store_pendulum"
19587 to track the current state of load/store issue.
19589 - If the pendulum is at zero, then no loads or stores have been
19590 issued in the current cycle so we do nothing.
19592 - If the pendulum is 1, then a single load has been issued in this
19593 cycle and we attempt to locate another load in the ready list to
19596 - If the pendulum is -2, then two stores have already been
19597 issued in this cycle, so we increase the priority of the first load
19598 in the ready list to increase it's likelihood of being chosen first
19601 - If the pendulum is -1, then a single store has been issued in this
19602 cycle and we attempt to locate another store in the ready list to
19603 issue with it, preferring a store to an adjacent memory location to
19604 facilitate store pairing in the store queue.
19606 - If the pendulum is 2, then two loads have already been
19607 issued in this cycle, so we increase the priority of the first store
19608 in the ready list to increase it's likelihood of being chosen first
19611 - If the pendulum < -2 or > 2, then do nothing.
19613 Note: This code covers the most common scenarios. There exist non
19614 load/store instructions which make use of the LSU and which
19615 would need to be accounted for to strictly model the behavior
19616 of the machine. Those instructions are currently unaccounted
19617 for to help minimize compile time overhead of this code.
19619 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
19625 if (is_store_insn (last_scheduled_insn
))
19626 /* Issuing a store, swing the load_store_pendulum to the left */
19627 load_store_pendulum
--;
19628 else if (is_load_insn (last_scheduled_insn
))
19629 /* Issuing a load, swing the load_store_pendulum to the right */
19630 load_store_pendulum
++;
19632 return cached_can_issue_more
;
19634 /* If the pendulum is balanced, or there is only one instruction on
19635 the ready list, then all is well, so return. */
19636 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
19637 return cached_can_issue_more
;
19639 if (load_store_pendulum
== 1)
19641 /* A load has been issued in this cycle. Scan the ready list
19642 for another load to issue with it */
19647 if (is_load_insn (ready
[pos
]))
19649 /* Found a load. Move it to the head of the ready list,
19650 and adjust it's priority so that it is more likely to
19653 for (i
=pos
; i
<*pn_ready
-1; i
++)
19654 ready
[i
] = ready
[i
+ 1];
19655 ready
[*pn_ready
-1] = tmp
;
19657 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
19658 INSN_PRIORITY (tmp
)++;
19664 else if (load_store_pendulum
== -2)
19666 /* Two stores have been issued in this cycle. Increase the
19667 priority of the first load in the ready list to favor it for
19668 issuing in the next cycle. */
19673 if (is_load_insn (ready
[pos
])
19675 && INSN_PRIORITY_KNOWN (ready
[pos
]))
19677 INSN_PRIORITY (ready
[pos
])++;
19679 /* Adjust the pendulum to account for the fact that a load
19680 was found and increased in priority. This is to prevent
19681 increasing the priority of multiple loads */
19682 load_store_pendulum
--;
19689 else if (load_store_pendulum
== -1)
19691 /* A store has been issued in this cycle. Scan the ready list for
19692 another store to issue with it, preferring a store to an adjacent
19694 int first_store_pos
= -1;
19700 if (is_store_insn (ready
[pos
]))
19702 /* Maintain the index of the first store found on the
19704 if (first_store_pos
== -1)
19705 first_store_pos
= pos
;
19707 if (is_store_insn (last_scheduled_insn
)
19708 && adjacent_mem_locations (last_scheduled_insn
,ready
[pos
]))
19710 /* Found an adjacent store. Move it to the head of the
19711 ready list, and adjust it's priority so that it is
19712 more likely to stay there */
19714 for (i
=pos
; i
<*pn_ready
-1; i
++)
19715 ready
[i
] = ready
[i
+ 1];
19716 ready
[*pn_ready
-1] = tmp
;
19718 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
19719 INSN_PRIORITY (tmp
)++;
19721 first_store_pos
= -1;
19729 if (first_store_pos
>= 0)
19731 /* An adjacent store wasn't found, but a non-adjacent store was,
19732 so move the non-adjacent store to the front of the ready
19733 list, and adjust its priority so that it is more likely to
19735 tmp
= ready
[first_store_pos
];
19736 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
19737 ready
[i
] = ready
[i
+ 1];
19738 ready
[*pn_ready
-1] = tmp
;
19739 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
19740 INSN_PRIORITY (tmp
)++;
19743 else if (load_store_pendulum
== 2)
19745 /* Two loads have been issued in this cycle. Increase the priority
19746 of the first store in the ready list to favor it for issuing in
19752 if (is_store_insn (ready
[pos
])
19754 && INSN_PRIORITY_KNOWN (ready
[pos
]))
19756 INSN_PRIORITY (ready
[pos
])++;
19758 /* Adjust the pendulum to account for the fact that a store
19759 was found and increased in priority. This is to prevent
19760 increasing the priority of multiple stores */
19761 load_store_pendulum
++;
19770 return cached_can_issue_more
;
19773 /* Return whether the presence of INSN causes a dispatch group termination
19774 of group WHICH_GROUP.
19776 If WHICH_GROUP == current_group, this function will return true if INSN
19777 causes the termination of the current group (i.e, the dispatch group to
19778 which INSN belongs). This means that INSN will be the last insn in the
19779 group it belongs to.
19781 If WHICH_GROUP == previous_group, this function will return true if INSN
19782 causes the termination of the previous group (i.e, the dispatch group that
19783 precedes the group to which INSN belongs). This means that INSN will be
19784 the first insn in the group it belongs to). */
19787 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
19794 first
= insn_must_be_first_in_group (insn
);
19795 last
= insn_must_be_last_in_group (insn
);
19800 if (which_group
== current_group
)
19802 else if (which_group
== previous_group
)
19810 insn_must_be_first_in_group (rtx insn
)
19812 enum attr_type type
;
19815 || insn
== NULL_RTX
19816 || GET_CODE (insn
) == NOTE
19817 || GET_CODE (PATTERN (insn
)) == USE
19818 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
19821 switch (rs6000_cpu
)
19823 case PROCESSOR_POWER5
:
19824 if (is_cracked_insn (insn
))
19826 case PROCESSOR_POWER4
:
19827 if (is_microcoded_insn (insn
))
19830 if (!rs6000_sched_groups
)
19833 type
= get_attr_type (insn
);
19840 case TYPE_DELAYED_CR
:
19841 case TYPE_CR_LOGICAL
:
19855 case PROCESSOR_POWER6
:
19856 type
= get_attr_type (insn
);
19860 case TYPE_INSERT_DWORD
:
19864 case TYPE_VAR_SHIFT_ROTATE
:
19871 case TYPE_INSERT_WORD
:
19872 case TYPE_DELAYED_COMPARE
:
19873 case TYPE_IMUL_COMPARE
:
19874 case TYPE_LMUL_COMPARE
:
19875 case TYPE_FPCOMPARE
:
19886 case TYPE_LOAD_EXT_UX
:
19888 case TYPE_STORE_UX
:
19889 case TYPE_FPLOAD_U
:
19890 case TYPE_FPLOAD_UX
:
19891 case TYPE_FPSTORE_U
:
19892 case TYPE_FPSTORE_UX
:
19906 insn_must_be_last_in_group (rtx insn
)
19908 enum attr_type type
;
19911 || insn
== NULL_RTX
19912 || GET_CODE (insn
) == NOTE
19913 || GET_CODE (PATTERN (insn
)) == USE
19914 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
19917 switch (rs6000_cpu
) {
19918 case PROCESSOR_POWER4
:
19919 case PROCESSOR_POWER5
:
19920 if (is_microcoded_insn (insn
))
19923 if (is_branch_slot_insn (insn
))
19927 case PROCESSOR_POWER6
:
19928 type
= get_attr_type (insn
);
19935 case TYPE_VAR_SHIFT_ROTATE
:
19942 case TYPE_DELAYED_COMPARE
:
19943 case TYPE_IMUL_COMPARE
:
19944 case TYPE_LMUL_COMPARE
:
19945 case TYPE_FPCOMPARE
:
19966 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
19967 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
19970 is_costly_group (rtx
*group_insns
, rtx next_insn
)
19973 int issue_rate
= rs6000_issue_rate ();
19975 for (i
= 0; i
< issue_rate
; i
++)
19977 sd_iterator_def sd_it
;
19979 rtx insn
= group_insns
[i
];
19984 FOR_EACH_DEP (insn
, SD_LIST_FORW
, sd_it
, dep
)
19986 rtx next
= DEP_CON (dep
);
19988 if (next
== next_insn
19989 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
19997 /* Utility of the function redefine_groups.
19998 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
19999 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
20000 to keep it "far" (in a separate group) from GROUP_INSNS, following
20001 one of the following schemes, depending on the value of the flag
20002 -minsert_sched_nops = X:
20003 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
20004 in order to force NEXT_INSN into a separate group.
20005 (2) X < sched_finish_regroup_exact: insert exactly X nops.
20006 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
20007 insertion (has a group just ended, how many vacant issue slots remain in the
20008 last group, and how many dispatch groups were encountered so far). */
20011 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
20012 rtx next_insn
, bool *group_end
, int can_issue_more
,
20017 int issue_rate
= rs6000_issue_rate ();
20018 bool end
= *group_end
;
20021 if (next_insn
== NULL_RTX
)
20022 return can_issue_more
;
20024 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
20025 return can_issue_more
;
20027 force
= is_costly_group (group_insns
, next_insn
);
20029 return can_issue_more
;
20031 if (sched_verbose
> 6)
20032 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
20033 *group_count
,can_issue_more
);
20035 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
20038 can_issue_more
= 0;
20040 /* Since only a branch can be issued in the last issue_slot, it is
20041 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
20042 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
20043 in this case the last nop will start a new group and the branch
20044 will be forced to the new group. */
20045 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
20048 while (can_issue_more
> 0)
20051 emit_insn_before (nop
, next_insn
);
20059 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
20061 int n_nops
= rs6000_sched_insert_nops
;
20063 /* Nops can't be issued from the branch slot, so the effective
20064 issue_rate for nops is 'issue_rate - 1'. */
20065 if (can_issue_more
== 0)
20066 can_issue_more
= issue_rate
;
20068 if (can_issue_more
== 0)
20070 can_issue_more
= issue_rate
- 1;
20073 for (i
= 0; i
< issue_rate
; i
++)
20075 group_insns
[i
] = 0;
20082 emit_insn_before (nop
, next_insn
);
20083 if (can_issue_more
== issue_rate
- 1) /* new group begins */
20086 if (can_issue_more
== 0)
20088 can_issue_more
= issue_rate
- 1;
20091 for (i
= 0; i
< issue_rate
; i
++)
20093 group_insns
[i
] = 0;
20099 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
20102 /* Is next_insn going to start a new group? */
20105 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
20106 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
20107 || (can_issue_more
< issue_rate
&&
20108 insn_terminates_group_p (next_insn
, previous_group
)));
20109 if (*group_end
&& end
)
20112 if (sched_verbose
> 6)
20113 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
20114 *group_count
, can_issue_more
);
20115 return can_issue_more
;
20118 return can_issue_more
;
20121 /* This function tries to synch the dispatch groups that the compiler "sees"
20122 with the dispatch groups that the processor dispatcher is expected to
20123 form in practice. It tries to achieve this synchronization by forcing the
20124 estimated processor grouping on the compiler (as opposed to the function
20125 'pad_goups' which tries to force the scheduler's grouping on the processor).
20127 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
20128 examines the (estimated) dispatch groups that will be formed by the processor
20129 dispatcher. It marks these group boundaries to reflect the estimated
20130 processor grouping, overriding the grouping that the scheduler had marked.
20131 Depending on the value of the flag '-minsert-sched-nops' this function can
20132 force certain insns into separate groups or force a certain distance between
20133 them by inserting nops, for example, if there exists a "costly dependence"
20136 The function estimates the group boundaries that the processor will form as
20137 follows: It keeps track of how many vacant issue slots are available after
20138 each insn. A subsequent insn will start a new group if one of the following
20140 - no more vacant issue slots remain in the current dispatch group.
20141 - only the last issue slot, which is the branch slot, is vacant, but the next
20142 insn is not a branch.
20143 - only the last 2 or less issue slots, including the branch slot, are vacant,
20144 which means that a cracked insn (which occupies two issue slots) can't be
20145 issued in this group.
20146 - less than 'issue_rate' slots are vacant, and the next insn always needs to
20147 start a new group. */
20150 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
20152 rtx insn
, next_insn
;
20154 int can_issue_more
;
20157 int group_count
= 0;
20161 issue_rate
= rs6000_issue_rate ();
20162 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
20163 for (i
= 0; i
< issue_rate
; i
++)
20165 group_insns
[i
] = 0;
20167 can_issue_more
= issue_rate
;
20169 insn
= get_next_active_insn (prev_head_insn
, tail
);
20172 while (insn
!= NULL_RTX
)
20174 slot
= (issue_rate
- can_issue_more
);
20175 group_insns
[slot
] = insn
;
20177 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
20178 if (insn_terminates_group_p (insn
, current_group
))
20179 can_issue_more
= 0;
20181 next_insn
= get_next_active_insn (insn
, tail
);
20182 if (next_insn
== NULL_RTX
)
20183 return group_count
+ 1;
20185 /* Is next_insn going to start a new group? */
20187 = (can_issue_more
== 0
20188 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
20189 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
20190 || (can_issue_more
< issue_rate
&&
20191 insn_terminates_group_p (next_insn
, previous_group
)));
20193 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
20194 next_insn
, &group_end
, can_issue_more
,
20200 can_issue_more
= 0;
20201 for (i
= 0; i
< issue_rate
; i
++)
20203 group_insns
[i
] = 0;
20207 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
20208 PUT_MODE (next_insn
, VOIDmode
);
20209 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
20210 PUT_MODE (next_insn
, TImode
);
20213 if (can_issue_more
== 0)
20214 can_issue_more
= issue_rate
;
20217 return group_count
;
20220 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
20221 dispatch group boundaries that the scheduler had marked. Pad with nops
20222 any dispatch groups which have vacant issue slots, in order to force the
20223 scheduler's grouping on the processor dispatcher. The function
20224 returns the number of dispatch groups found. */
20227 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
20229 rtx insn
, next_insn
;
20232 int can_issue_more
;
20234 int group_count
= 0;
20236 /* Initialize issue_rate. */
20237 issue_rate
= rs6000_issue_rate ();
20238 can_issue_more
= issue_rate
;
20240 insn
= get_next_active_insn (prev_head_insn
, tail
);
20241 next_insn
= get_next_active_insn (insn
, tail
);
20243 while (insn
!= NULL_RTX
)
20246 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
20248 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
20250 if (next_insn
== NULL_RTX
)
20255 /* If the scheduler had marked group termination at this location
20256 (between insn and next_insn), and neither insn nor next_insn will
20257 force group termination, pad the group with nops to force group
20260 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
20261 && !insn_terminates_group_p (insn
, current_group
)
20262 && !insn_terminates_group_p (next_insn
, previous_group
))
20264 if (!is_branch_slot_insn (next_insn
))
20267 while (can_issue_more
)
20270 emit_insn_before (nop
, next_insn
);
20275 can_issue_more
= issue_rate
;
20280 next_insn
= get_next_active_insn (insn
, tail
);
20283 return group_count
;
20286 /* We're beginning a new block. Initialize data structures as necessary. */
20289 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
20290 int sched_verbose ATTRIBUTE_UNUSED
,
20291 int max_ready ATTRIBUTE_UNUSED
)
20293 last_scheduled_insn
= NULL_RTX
;
20294 load_store_pendulum
= 0;
20297 /* The following function is called at the end of scheduling BB.
20298 After reload, it inserts nops at insn group bundling. */
20301 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
20306 fprintf (dump
, "=== Finishing schedule.\n");
20308 if (reload_completed
&& rs6000_sched_groups
)
20310 /* Do not run sched_finish hook when selective scheduling enabled. */
20311 if (sel_sched_p ())
20314 if (rs6000_sched_insert_nops
== sched_finish_none
)
20317 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
20318 n_groups
= pad_groups (dump
, sched_verbose
,
20319 current_sched_info
->prev_head
,
20320 current_sched_info
->next_tail
);
20322 n_groups
= redefine_groups (dump
, sched_verbose
,
20323 current_sched_info
->prev_head
,
20324 current_sched_info
->next_tail
);
20326 if (sched_verbose
>= 6)
20328 fprintf (dump
, "ngroups = %d\n", n_groups
);
20329 print_rtl (dump
, current_sched_info
->prev_head
);
20330 fprintf (dump
, "Done finish_sched\n");
20335 struct _rs6000_sched_context
20337 short cached_can_issue_more
;
20338 rtx last_scheduled_insn
;
20339 int load_store_pendulum
;
20342 typedef struct _rs6000_sched_context rs6000_sched_context_def
;
20343 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
20345 /* Allocate store for new scheduling context. */
20347 rs6000_alloc_sched_context (void)
20349 return xmalloc (sizeof (rs6000_sched_context_def
));
20352 /* If CLEAN_P is true then initializes _SC with clean data,
20353 and from the global context otherwise. */
20355 rs6000_init_sched_context (void *_sc
, bool clean_p
)
20357 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
20361 sc
->cached_can_issue_more
= 0;
20362 sc
->last_scheduled_insn
= NULL_RTX
;
20363 sc
->load_store_pendulum
= 0;
20367 sc
->cached_can_issue_more
= cached_can_issue_more
;
20368 sc
->last_scheduled_insn
= last_scheduled_insn
;
20369 sc
->load_store_pendulum
= load_store_pendulum
;
20373 /* Sets the global scheduling context to the one pointed to by _SC. */
20375 rs6000_set_sched_context (void *_sc
)
20377 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
20379 gcc_assert (sc
!= NULL
);
20381 cached_can_issue_more
= sc
->cached_can_issue_more
;
20382 last_scheduled_insn
= sc
->last_scheduled_insn
;
20383 load_store_pendulum
= sc
->load_store_pendulum
;
20388 rs6000_free_sched_context (void *_sc
)
20390 gcc_assert (_sc
!= NULL
);
20396 /* Length in units of the trampoline for entering a nested function. */
20399 rs6000_trampoline_size (void)
20403 switch (DEFAULT_ABI
)
20406 gcc_unreachable ();
20409 ret
= (TARGET_32BIT
) ? 12 : 24;
20414 ret
= (TARGET_32BIT
) ? 40 : 48;
20421 /* Emit RTL insns to initialize the variable parts of a trampoline.
20422 FNADDR is an RTX for the address of the function's pure code.
20423 CXT is an RTX for the static chain value for the function. */
20426 rs6000_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx cxt
)
20428 int regsize
= (TARGET_32BIT
) ? 4 : 8;
20429 rtx ctx_reg
= force_reg (Pmode
, cxt
);
20431 switch (DEFAULT_ABI
)
20434 gcc_unreachable ();
20436 /* Macros to shorten the code expansions below. */
20437 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
20438 #define MEM_PLUS(addr,offset) \
20439 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
20441 /* Under AIX, just build the 3 word function descriptor */
20444 rtx fn_reg
= gen_reg_rtx (Pmode
);
20445 rtx toc_reg
= gen_reg_rtx (Pmode
);
20446 emit_move_insn (fn_reg
, MEM_DEREF (fnaddr
));
20447 emit_move_insn (toc_reg
, MEM_PLUS (fnaddr
, regsize
));
20448 emit_move_insn (MEM_DEREF (addr
), fn_reg
);
20449 emit_move_insn (MEM_PLUS (addr
, regsize
), toc_reg
);
20450 emit_move_insn (MEM_PLUS (addr
, 2*regsize
), ctx_reg
);
20454 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
20457 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
20458 LCT_NORMAL
, VOIDmode
, 4,
20460 GEN_INT (rs6000_trampoline_size ()), SImode
,
20470 /* Table of valid machine attributes. */
20472 const struct attribute_spec rs6000_attribute_table
[] =
20474 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
20475 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
},
20476 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
},
20477 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
},
20478 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
},
20479 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
},
20480 #ifdef SUBTARGET_ATTRIBUTE_TABLE
20481 SUBTARGET_ATTRIBUTE_TABLE
,
20483 { NULL
, 0, 0, false, false, false, NULL
}
20486 /* Handle the "altivec" attribute. The attribute may have
20487 arguments as follows:
20489 __attribute__((altivec(vector__)))
20490 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
20491 __attribute__((altivec(bool__))) (always followed by 'unsigned')
20493 and may appear more than once (e.g., 'vector bool char') in a
20494 given declaration. */
20497 rs6000_handle_altivec_attribute (tree
*node
,
20498 tree name ATTRIBUTE_UNUSED
,
20500 int flags ATTRIBUTE_UNUSED
,
20501 bool *no_add_attrs
)
20503 tree type
= *node
, result
= NULL_TREE
;
20504 enum machine_mode mode
;
20507 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
20508 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
20509 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
20512 while (POINTER_TYPE_P (type
)
20513 || TREE_CODE (type
) == FUNCTION_TYPE
20514 || TREE_CODE (type
) == METHOD_TYPE
20515 || TREE_CODE (type
) == ARRAY_TYPE
)
20516 type
= TREE_TYPE (type
);
20518 mode
= TYPE_MODE (type
);
20520 /* Check for invalid AltiVec type qualifiers. */
20521 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
20524 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
20525 else if (rs6000_warn_altivec_long
)
20526 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
20528 else if (type
== long_long_unsigned_type_node
20529 || type
== long_long_integer_type_node
)
20530 error ("use of %<long long%> in AltiVec types is invalid");
20531 else if (type
== double_type_node
)
20532 error ("use of %<double%> in AltiVec types is invalid");
20533 else if (type
== long_double_type_node
)
20534 error ("use of %<long double%> in AltiVec types is invalid");
20535 else if (type
== boolean_type_node
)
20536 error ("use of boolean types in AltiVec types is invalid");
20537 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
20538 error ("use of %<complex%> in AltiVec types is invalid");
20539 else if (DECIMAL_FLOAT_MODE_P (mode
))
20540 error ("use of decimal floating point types in AltiVec types is invalid");
20542 switch (altivec_type
)
20545 unsigned_p
= TYPE_UNSIGNED (type
);
20549 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
20552 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
20555 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
20557 case SFmode
: result
= V4SF_type_node
; break;
20558 /* If the user says 'vector int bool', we may be handed the 'bool'
20559 attribute _before_ the 'vector' attribute, and so select the
20560 proper type in the 'b' case below. */
20561 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
20569 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
20570 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
20571 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
20578 case V8HImode
: result
= pixel_V8HI_type_node
;
20584 /* Propagate qualifiers attached to the element type
20585 onto the vector type. */
20586 if (result
&& result
!= type
&& TYPE_QUALS (type
))
20587 result
= build_qualified_type (result
, TYPE_QUALS (type
));
20589 *no_add_attrs
= true; /* No need to hang on to the attribute. */
20592 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
20597 /* AltiVec defines four built-in scalar types that serve as vector
20598 elements; we must teach the compiler how to mangle them. */
20600 static const char *
20601 rs6000_mangle_type (const_tree type
)
20603 type
= TYPE_MAIN_VARIANT (type
);
20605 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
20606 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
20609 if (type
== bool_char_type_node
) return "U6__boolc";
20610 if (type
== bool_short_type_node
) return "U6__bools";
20611 if (type
== pixel_type_node
) return "u7__pixel";
20612 if (type
== bool_int_type_node
) return "U6__booli";
20614 /* Mangle IBM extended float long double as `g' (__float128) on
20615 powerpc*-linux where long-double-64 previously was the default. */
20616 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
20618 && TARGET_LONG_DOUBLE_128
20619 && !TARGET_IEEEQUAD
)
20622 /* For all other types, use normal C++ mangling. */
20626 /* Handle a "longcall" or "shortcall" attribute; arguments as in
20627 struct attribute_spec.handler. */
20630 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
20631 tree args ATTRIBUTE_UNUSED
,
20632 int flags ATTRIBUTE_UNUSED
,
20633 bool *no_add_attrs
)
20635 if (TREE_CODE (*node
) != FUNCTION_TYPE
20636 && TREE_CODE (*node
) != FIELD_DECL
20637 && TREE_CODE (*node
) != TYPE_DECL
)
20639 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
20641 *no_add_attrs
= true;
20647 /* Set longcall attributes on all functions declared when
20648 rs6000_default_long_calls is true. */
20650 rs6000_set_default_type_attributes (tree type
)
20652 if (rs6000_default_long_calls
20653 && (TREE_CODE (type
) == FUNCTION_TYPE
20654 || TREE_CODE (type
) == METHOD_TYPE
))
20655 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
20657 TYPE_ATTRIBUTES (type
));
20660 darwin_set_default_type_attributes (type
);
20664 /* Return a reference suitable for calling a function with the
20665 longcall attribute. */
20668 rs6000_longcall_ref (rtx call_ref
)
20670 const char *call_name
;
20673 if (GET_CODE (call_ref
) != SYMBOL_REF
)
20676 /* System V adds '.' to the internal name, so skip them. */
20677 call_name
= XSTR (call_ref
, 0);
20678 if (*call_name
== '.')
20680 while (*call_name
== '.')
20683 node
= get_identifier (call_name
);
20684 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
20687 return force_reg (Pmode
, call_ref
);
20690 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
20691 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
20694 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
20695 struct attribute_spec.handler. */
20697 rs6000_handle_struct_attribute (tree
*node
, tree name
,
20698 tree args ATTRIBUTE_UNUSED
,
20699 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
20702 if (DECL_P (*node
))
20704 if (TREE_CODE (*node
) == TYPE_DECL
)
20705 type
= &TREE_TYPE (*node
);
20710 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
20711 || TREE_CODE (*type
) == UNION_TYPE
)))
20713 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
20714 *no_add_attrs
= true;
20717 else if ((is_attribute_p ("ms_struct", name
)
20718 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
20719 || ((is_attribute_p ("gcc_struct", name
)
20720 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
20722 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
20724 *no_add_attrs
= true;
20731 rs6000_ms_bitfield_layout_p (const_tree record_type
)
20733 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
20734 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
20735 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
20738 #ifdef USING_ELFOS_H
20740 /* A get_unnamed_section callback, used for switching to toc_section. */
20743 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
20745 if (DEFAULT_ABI
== ABI_AIX
20746 && TARGET_MINIMAL_TOC
20747 && !TARGET_RELOCATABLE
)
20749 if (!toc_initialized
)
20751 toc_initialized
= 1;
20752 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
20753 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
20754 fprintf (asm_out_file
, "\t.tc ");
20755 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
20756 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
20757 fprintf (asm_out_file
, "\n");
20759 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
20760 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
20761 fprintf (asm_out_file
, " = .+32768\n");
20764 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
20766 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_RELOCATABLE
)
20767 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
20770 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
20771 if (!toc_initialized
)
20773 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
20774 fprintf (asm_out_file
, " = .+32768\n");
20775 toc_initialized
= 1;
20780 /* Implement TARGET_ASM_INIT_SECTIONS. */
20783 rs6000_elf_asm_init_sections (void)
20786 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
20789 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
20790 SDATA2_SECTION_ASM_OP
);
20793 /* Implement TARGET_SELECT_RTX_SECTION. */
20796 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
20797 unsigned HOST_WIDE_INT align
)
20799 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
20800 return toc_section
;
20802 return default_elf_select_rtx_section (mode
, x
, align
);
20805 /* For a SYMBOL_REF, set generic flags and then perform some
20806 target-specific processing.
20808 When the AIX ABI is requested on a non-AIX system, replace the
20809 function name with the real name (with a leading .) rather than the
20810 function descriptor name. This saves a lot of overriding code to
20811 read the prefixes. */
20814 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
20816 default_encode_section_info (decl
, rtl
, first
);
20819 && TREE_CODE (decl
) == FUNCTION_DECL
20821 && DEFAULT_ABI
== ABI_AIX
)
20823 rtx sym_ref
= XEXP (rtl
, 0);
20824 size_t len
= strlen (XSTR (sym_ref
, 0));
20825 char *str
= XALLOCAVEC (char, len
+ 2);
20827 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
20828 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
20833 compare_section_name (const char *section
, const char *templ
)
20837 len
= strlen (templ
);
20838 return (strncmp (section
, templ
, len
) == 0
20839 && (section
[len
] == 0 || section
[len
] == '.'));
20843 rs6000_elf_in_small_data_p (const_tree decl
)
20845 if (rs6000_sdata
== SDATA_NONE
)
20848 /* We want to merge strings, so we never consider them small data. */
20849 if (TREE_CODE (decl
) == STRING_CST
)
20852 /* Functions are never in the small data area. */
20853 if (TREE_CODE (decl
) == FUNCTION_DECL
)
20856 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
20858 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
20859 if (compare_section_name (section
, ".sdata")
20860 || compare_section_name (section
, ".sdata2")
20861 || compare_section_name (section
, ".gnu.linkonce.s")
20862 || compare_section_name (section
, ".sbss")
20863 || compare_section_name (section
, ".sbss2")
20864 || compare_section_name (section
, ".gnu.linkonce.sb")
20865 || strcmp (section
, ".PPC.EMB.sdata0") == 0
20866 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
20871 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
20874 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
20875 /* If it's not public, and we're not going to reference it there,
20876 there's no need to put it in the small data section. */
20877 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
20884 #endif /* USING_ELFOS_H */
20886 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
20889 rs6000_use_blocks_for_constant_p (enum machine_mode mode
, const_rtx x
)
20891 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
20894 /* Return a REG that occurs in ADDR with coefficient 1.
20895 ADDR can be effectively incremented by incrementing REG.
20897 r0 is special and we must not select it as an address
20898 register by this routine since our caller will try to
20899 increment the returned register via an "la" instruction. */
20902 find_addr_reg (rtx addr
)
20904 while (GET_CODE (addr
) == PLUS
)
20906 if (GET_CODE (XEXP (addr
, 0)) == REG
20907 && REGNO (XEXP (addr
, 0)) != 0)
20908 addr
= XEXP (addr
, 0);
20909 else if (GET_CODE (XEXP (addr
, 1)) == REG
20910 && REGNO (XEXP (addr
, 1)) != 0)
20911 addr
= XEXP (addr
, 1);
20912 else if (CONSTANT_P (XEXP (addr
, 0)))
20913 addr
= XEXP (addr
, 1);
20914 else if (CONSTANT_P (XEXP (addr
, 1)))
20915 addr
= XEXP (addr
, 0);
20917 gcc_unreachable ();
20919 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
20924 rs6000_fatal_bad_address (rtx op
)
20926 fatal_insn ("bad address", op
);
20931 static tree branch_island_list
= 0;
20933 /* Remember to generate a branch island for far calls to the given
20937 add_compiler_branch_island (tree label_name
, tree function_name
,
20940 tree branch_island
= build_tree_list (function_name
, label_name
);
20941 TREE_TYPE (branch_island
) = build_int_cst (NULL_TREE
, line_number
);
20942 TREE_CHAIN (branch_island
) = branch_island_list
;
20943 branch_island_list
= branch_island
;
20946 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
20947 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
20948 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
20949 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
20951 /* Generate far-jump branch islands for everything on the
20952 branch_island_list. Invoked immediately after the last instruction
20953 of the epilogue has been emitted; the branch-islands must be
20954 appended to, and contiguous with, the function body. Mach-O stubs
20955 are generated in machopic_output_stub(). */
20958 macho_branch_islands (void)
20961 tree branch_island
;
20963 for (branch_island
= branch_island_list
;
20965 branch_island
= TREE_CHAIN (branch_island
))
20967 const char *label
=
20968 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island
));
20970 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island
));
20971 char name_buf
[512];
20972 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
20973 if (name
[0] == '*' || name
[0] == '&')
20974 strcpy (name_buf
, name
+1);
20978 strcpy (name_buf
+1, name
);
20980 strcpy (tmp_buf
, "\n");
20981 strcat (tmp_buf
, label
);
20982 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
20983 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
20984 dbxout_stabd (N_SLINE
, BRANCH_ISLAND_LINE_NUMBER (branch_island
));
20985 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
20988 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
20989 strcat (tmp_buf
, label
);
20990 strcat (tmp_buf
, "_pic\n");
20991 strcat (tmp_buf
, label
);
20992 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
20994 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
20995 strcat (tmp_buf
, name_buf
);
20996 strcat (tmp_buf
, " - ");
20997 strcat (tmp_buf
, label
);
20998 strcat (tmp_buf
, "_pic)\n");
21000 strcat (tmp_buf
, "\tmtlr r0\n");
21002 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
21003 strcat (tmp_buf
, name_buf
);
21004 strcat (tmp_buf
, " - ");
21005 strcat (tmp_buf
, label
);
21006 strcat (tmp_buf
, "_pic)\n");
21008 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
21012 strcat (tmp_buf
, ":\nlis r12,hi16(");
21013 strcat (tmp_buf
, name_buf
);
21014 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
21015 strcat (tmp_buf
, name_buf
);
21016 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
21018 output_asm_insn (tmp_buf
, 0);
21019 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
21020 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
21021 dbxout_stabd (N_SLINE
, BRANCH_ISLAND_LINE_NUMBER (branch_island
));
21022 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
21025 branch_island_list
= 0;
21028 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
21029 already there or not. */
21032 no_previous_def (tree function_name
)
21034 tree branch_island
;
21035 for (branch_island
= branch_island_list
;
21037 branch_island
= TREE_CHAIN (branch_island
))
21038 if (function_name
== BRANCH_ISLAND_FUNCTION_NAME (branch_island
))
21043 /* GET_PREV_LABEL gets the label name from the previous definition of
21047 get_prev_label (tree function_name
)
21049 tree branch_island
;
21050 for (branch_island
= branch_island_list
;
21052 branch_island
= TREE_CHAIN (branch_island
))
21053 if (function_name
== BRANCH_ISLAND_FUNCTION_NAME (branch_island
))
21054 return BRANCH_ISLAND_LABEL_NAME (branch_island
);
21058 #ifndef DARWIN_LINKER_GENERATES_ISLANDS
21059 #define DARWIN_LINKER_GENERATES_ISLANDS 0
21062 /* KEXTs still need branch islands. */
21063 #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \
21064 || flag_mkernel || flag_apple_kext)
21066 /* INSN is either a function call or a millicode call. It may have an
21067 unconditional jump in its delay slot.
21069 CALL_DEST is the routine we are calling. */
21072 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
,
21073 int cookie_operand_number
)
21075 static char buf
[256];
21076 if (DARWIN_GENERATE_ISLANDS
21077 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
21078 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
21081 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
21083 if (no_previous_def (funname
))
21085 rtx label_rtx
= gen_label_rtx ();
21086 char *label_buf
, temp_buf
[256];
21087 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
21088 CODE_LABEL_NUMBER (label_rtx
));
21089 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
21090 labelname
= get_identifier (label_buf
);
21091 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
21094 labelname
= get_prev_label (funname
);
21096 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
21097 instruction will reach 'foo', otherwise link as 'bl L42'".
21098 "L42" should be a 'branch island', that will do a far jump to
21099 'foo'. Branch islands are generated in
21100 macho_branch_islands(). */
21101 sprintf (buf
, "jbsr %%z%d,%.246s",
21102 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
21105 sprintf (buf
, "bl %%z%d", dest_operand_number
);
21109 /* Generate PIC and indirect symbol stubs. */
21112 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
21114 unsigned int length
;
21115 char *symbol_name
, *lazy_ptr_name
;
21116 char *local_label_0
;
21117 static int label
= 0;
21119 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
21120 symb
= (*targetm
.strip_name_encoding
) (symb
);
21123 length
= strlen (symb
);
21124 symbol_name
= XALLOCAVEC (char, length
+ 32);
21125 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
21127 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
21128 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
21131 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
21133 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
21137 fprintf (file
, "\t.align 5\n");
21139 fprintf (file
, "%s:\n", stub
);
21140 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
21143 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
21144 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
21146 fprintf (file
, "\tmflr r0\n");
21147 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
21148 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
21149 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
21150 lazy_ptr_name
, local_label_0
);
21151 fprintf (file
, "\tmtlr r0\n");
21152 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
21153 (TARGET_64BIT
? "ldu" : "lwzu"),
21154 lazy_ptr_name
, local_label_0
);
21155 fprintf (file
, "\tmtctr r12\n");
21156 fprintf (file
, "\tbctr\n");
21160 fprintf (file
, "\t.align 4\n");
21162 fprintf (file
, "%s:\n", stub
);
21163 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
21165 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
21166 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
21167 (TARGET_64BIT
? "ldu" : "lwzu"),
21169 fprintf (file
, "\tmtctr r12\n");
21170 fprintf (file
, "\tbctr\n");
21173 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
21174 fprintf (file
, "%s:\n", lazy_ptr_name
);
21175 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
21176 fprintf (file
, "%sdyld_stub_binding_helper\n",
21177 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
21180 /* Legitimize PIC addresses. If the address is already
21181 position-independent, we return ORIG. Newly generated
21182 position-independent addresses go into a reg. This is REG if non
21183 zero, otherwise we allocate register(s) as necessary. */
21185 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
21188 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
21193 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
21194 reg
= gen_reg_rtx (Pmode
);
21196 if (GET_CODE (orig
) == CONST
)
21200 if (GET_CODE (XEXP (orig
, 0)) == PLUS
21201 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
21204 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
21206 /* Use a different reg for the intermediate value, as
21207 it will be marked UNCHANGING. */
21208 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
21209 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
21212 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
21215 if (GET_CODE (offset
) == CONST_INT
)
21217 if (SMALL_INT (offset
))
21218 return plus_constant (base
, INTVAL (offset
));
21219 else if (! reload_in_progress
&& ! reload_completed
)
21220 offset
= force_reg (Pmode
, offset
);
21223 rtx mem
= force_const_mem (Pmode
, orig
);
21224 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
21227 return gen_rtx_PLUS (Pmode
, base
, offset
);
21230 /* Fall back on generic machopic code. */
21231 return machopic_legitimize_pic_address (orig
, mode
, reg
);
21234 /* Output a .machine directive for the Darwin assembler, and call
21235 the generic start_file routine. */
21238 rs6000_darwin_file_start (void)
21240 static const struct
21246 { "ppc64", "ppc64", MASK_64BIT
},
21247 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
21248 { "power4", "ppc970", 0 },
21249 { "G5", "ppc970", 0 },
21250 { "7450", "ppc7450", 0 },
21251 { "7400", "ppc7400", MASK_ALTIVEC
},
21252 { "G4", "ppc7400", 0 },
21253 { "750", "ppc750", 0 },
21254 { "740", "ppc750", 0 },
21255 { "G3", "ppc750", 0 },
21256 { "604e", "ppc604e", 0 },
21257 { "604", "ppc604", 0 },
21258 { "603e", "ppc603", 0 },
21259 { "603", "ppc603", 0 },
21260 { "601", "ppc601", 0 },
21261 { NULL
, "ppc", 0 } };
21262 const char *cpu_id
= "";
21265 rs6000_file_start ();
21266 darwin_file_start ();
21268 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
21269 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
21270 if (rs6000_select
[i
].set_arch_p
&& rs6000_select
[i
].string
21271 && rs6000_select
[i
].string
[0] != '\0')
21272 cpu_id
= rs6000_select
[i
].string
;
21274 /* Look through the mapping array. Pick the first name that either
21275 matches the argument, has a bit set in IF_SET that is also set
21276 in the target flags, or has a NULL name. */
21279 while (mapping
[i
].arg
!= NULL
21280 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
21281 && (mapping
[i
].if_set
& target_flags
) == 0)
21284 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
21287 #endif /* TARGET_MACHO */
21291 rs6000_elf_reloc_rw_mask (void)
21295 else if (DEFAULT_ABI
== ABI_AIX
)
21301 /* Record an element in the table of global constructors. SYMBOL is
21302 a SYMBOL_REF of the function to be called; PRIORITY is a number
21303 between 0 and MAX_INIT_PRIORITY.
21305 This differs from default_named_section_asm_out_constructor in
21306 that we have special handling for -mrelocatable. */
21309 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
21311 const char *section
= ".ctors";
21314 if (priority
!= DEFAULT_INIT_PRIORITY
)
21316 sprintf (buf
, ".ctors.%.5u",
21317 /* Invert the numbering so the linker puts us in the proper
21318 order; constructors are run from right to left, and the
21319 linker sorts in increasing order. */
21320 MAX_INIT_PRIORITY
- priority
);
21324 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
21325 assemble_align (POINTER_SIZE
);
21327 if (TARGET_RELOCATABLE
)
21329 fputs ("\t.long (", asm_out_file
);
21330 output_addr_const (asm_out_file
, symbol
);
21331 fputs (")@fixup\n", asm_out_file
);
21334 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
21338 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
21340 const char *section
= ".dtors";
21343 if (priority
!= DEFAULT_INIT_PRIORITY
)
21345 sprintf (buf
, ".dtors.%.5u",
21346 /* Invert the numbering so the linker puts us in the proper
21347 order; constructors are run from right to left, and the
21348 linker sorts in increasing order. */
21349 MAX_INIT_PRIORITY
- priority
);
21353 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
21354 assemble_align (POINTER_SIZE
);
21356 if (TARGET_RELOCATABLE
)
21358 fputs ("\t.long (", asm_out_file
);
21359 output_addr_const (asm_out_file
, symbol
);
21360 fputs (")@fixup\n", asm_out_file
);
21363 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
21367 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
21371 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
21372 ASM_OUTPUT_LABEL (file
, name
);
21373 fputs (DOUBLE_INT_ASM_OP
, file
);
21374 rs6000_output_function_entry (file
, name
);
21375 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
21378 fputs ("\t.size\t", file
);
21379 assemble_name (file
, name
);
21380 fputs (",24\n\t.type\t.", file
);
21381 assemble_name (file
, name
);
21382 fputs (",@function\n", file
);
21383 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
21385 fputs ("\t.globl\t.", file
);
21386 assemble_name (file
, name
);
21391 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
21392 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
21393 rs6000_output_function_entry (file
, name
);
21394 fputs (":\n", file
);
21398 if (TARGET_RELOCATABLE
21399 && !TARGET_SECURE_PLT
21400 && (get_pool_size () != 0 || crtl
->profile
)
21405 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
21407 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
21408 fprintf (file
, "\t.long ");
21409 assemble_name (file
, buf
);
21411 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
21412 assemble_name (file
, buf
);
21416 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
21417 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
21419 if (DEFAULT_ABI
== ABI_AIX
)
21421 const char *desc_name
, *orig_name
;
21423 orig_name
= (*targetm
.strip_name_encoding
) (name
);
21424 desc_name
= orig_name
;
21425 while (*desc_name
== '.')
21428 if (TREE_PUBLIC (decl
))
21429 fprintf (file
, "\t.globl %s\n", desc_name
);
21431 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
21432 fprintf (file
, "%s:\n", desc_name
);
21433 fprintf (file
, "\t.long %s\n", orig_name
);
21434 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
21435 if (DEFAULT_ABI
== ABI_AIX
)
21436 fputs ("\t.long 0\n", file
);
21437 fprintf (file
, "\t.previous\n");
21439 ASM_OUTPUT_LABEL (file
, name
);
21443 rs6000_elf_end_indicate_exec_stack (void)
21446 file_end_indicate_exec_stack ();
21452 rs6000_xcoff_asm_output_anchor (rtx symbol
)
21456 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
21457 SYMBOL_REF_BLOCK_OFFSET (symbol
));
21458 ASM_OUTPUT_DEF (asm_out_file
, XSTR (symbol
, 0), buffer
);
21462 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
21464 fputs (GLOBAL_ASM_OP
, stream
);
21465 RS6000_OUTPUT_BASENAME (stream
, name
);
21466 putc ('\n', stream
);
21469 /* A get_unnamed_decl callback, used for read-only sections. PTR
21470 points to the section string variable. */
21473 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
21475 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
21476 *(const char *const *) directive
,
21477 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
21480 /* Likewise for read-write sections. */
21483 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
21485 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
21486 *(const char *const *) directive
,
21487 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
21490 /* A get_unnamed_section callback, used for switching to toc_section. */
21493 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
21495 if (TARGET_MINIMAL_TOC
)
21497 /* toc_section is always selected at least once from
21498 rs6000_xcoff_file_start, so this is guaranteed to
21499 always be defined once and only once in each file. */
21500 if (!toc_initialized
)
21502 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
21503 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
21504 toc_initialized
= 1;
21506 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
21507 (TARGET_32BIT
? "" : ",3"));
21510 fputs ("\t.toc\n", asm_out_file
);
21513 /* Implement TARGET_ASM_INIT_SECTIONS. */
21516 rs6000_xcoff_asm_init_sections (void)
21518 read_only_data_section
21519 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
21520 &xcoff_read_only_section_name
);
21522 private_data_section
21523 = get_unnamed_section (SECTION_WRITE
,
21524 rs6000_xcoff_output_readwrite_section_asm_op
,
21525 &xcoff_private_data_section_name
);
21527 read_only_private_data_section
21528 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
21529 &xcoff_private_data_section_name
);
21532 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
21534 readonly_data_section
= read_only_data_section
;
21535 exception_section
= data_section
;
21539 rs6000_xcoff_reloc_rw_mask (void)
21545 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
21546 tree decl ATTRIBUTE_UNUSED
)
21549 static const char * const suffix
[3] = { "PR", "RO", "RW" };
21551 if (flags
& SECTION_CODE
)
21553 else if (flags
& SECTION_WRITE
)
21558 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
21559 (flags
& SECTION_CODE
) ? "." : "",
21560 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
21564 rs6000_xcoff_select_section (tree decl
, int reloc
,
21565 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
21567 if (decl_readonly_section (decl
, reloc
))
21569 if (TREE_PUBLIC (decl
))
21570 return read_only_data_section
;
21572 return read_only_private_data_section
;
21576 if (TREE_PUBLIC (decl
))
21577 return data_section
;
21579 return private_data_section
;
21584 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
21588 /* Use select_section for private and uninitialized data. */
21589 if (!TREE_PUBLIC (decl
)
21590 || DECL_COMMON (decl
)
21591 || DECL_INITIAL (decl
) == NULL_TREE
21592 || DECL_INITIAL (decl
) == error_mark_node
21593 || (flag_zero_initialized_in_bss
21594 && initializer_zerop (DECL_INITIAL (decl
))))
21597 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
21598 name
= (*targetm
.strip_name_encoding
) (name
);
21599 DECL_SECTION_NAME (decl
) = build_string (strlen (name
), name
);
21602 /* Select section for constant in constant pool.
21604 On RS/6000, all constants are in the private read-only data area.
21605 However, if this is being placed in the TOC it must be output as a
21609 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
21610 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
21612 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
21613 return toc_section
;
21615 return read_only_private_data_section
;
21618 /* Remove any trailing [DS] or the like from the symbol name. */
21620 static const char *
21621 rs6000_xcoff_strip_name_encoding (const char *name
)
21626 len
= strlen (name
);
21627 if (name
[len
- 1] == ']')
21628 return ggc_alloc_string (name
, len
- 4);
21633 /* Section attributes. AIX is always PIC. */
21635 static unsigned int
21636 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
21638 unsigned int align
;
21639 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
21641 /* Align to at least UNIT size. */
21642 if (flags
& SECTION_CODE
)
21643 align
= MIN_UNITS_PER_WORD
;
21645 /* Increase alignment of large objects if not already stricter. */
21646 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
21647 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
21648 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
21650 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
21653 /* Output at beginning of assembler file.
21655 Initialize the section names for the RS/6000 at this point.
21657 Specify filename, including full path, to assembler.
21659 We want to go into the TOC section so at least one .toc will be emitted.
21660 Also, in order to output proper .bs/.es pairs, we need at least one static
21661 [RW] section emitted.
21663 Finally, declare mcount when profiling to make the assembler happy. */
21666 rs6000_xcoff_file_start (void)
21668 rs6000_gen_section_name (&xcoff_bss_section_name
,
21669 main_input_filename
, ".bss_");
21670 rs6000_gen_section_name (&xcoff_private_data_section_name
,
21671 main_input_filename
, ".rw_");
21672 rs6000_gen_section_name (&xcoff_read_only_section_name
,
21673 main_input_filename
, ".ro_");
21675 fputs ("\t.file\t", asm_out_file
);
21676 output_quoted_string (asm_out_file
, main_input_filename
);
21677 fputc ('\n', asm_out_file
);
21678 if (write_symbols
!= NO_DEBUG
)
21679 switch_to_section (private_data_section
);
21680 switch_to_section (text_section
);
21682 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
21683 rs6000_file_start ();
21686 /* Output at end of assembler file.
21687 On the RS/6000, referencing data should automatically pull in text. */
21690 rs6000_xcoff_file_end (void)
21692 switch_to_section (text_section
);
21693 fputs ("_section_.text:\n", asm_out_file
);
21694 switch_to_section (data_section
);
21695 fputs (TARGET_32BIT
21696 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
21699 #endif /* TARGET_XCOFF */
21701 /* Compute a (partial) cost for rtx X. Return true if the complete
21702 cost has been computed, and false if subexpressions should be
21703 scanned. In either case, *TOTAL contains the cost result. */
21706 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
21709 enum machine_mode mode
= GET_MODE (x
);
21713 /* On the RS/6000, if it is valid in the insn, it is free. */
21715 if (((outer_code
== SET
21716 || outer_code
== PLUS
21717 || outer_code
== MINUS
)
21718 && (satisfies_constraint_I (x
)
21719 || satisfies_constraint_L (x
)))
21720 || (outer_code
== AND
21721 && (satisfies_constraint_K (x
)
21723 ? satisfies_constraint_L (x
)
21724 : satisfies_constraint_J (x
))
21725 || mask_operand (x
, mode
)
21727 && mask64_operand (x
, DImode
))))
21728 || ((outer_code
== IOR
|| outer_code
== XOR
)
21729 && (satisfies_constraint_K (x
)
21731 ? satisfies_constraint_L (x
)
21732 : satisfies_constraint_J (x
))))
21733 || outer_code
== ASHIFT
21734 || outer_code
== ASHIFTRT
21735 || outer_code
== LSHIFTRT
21736 || outer_code
== ROTATE
21737 || outer_code
== ROTATERT
21738 || outer_code
== ZERO_EXTRACT
21739 || (outer_code
== MULT
21740 && satisfies_constraint_I (x
))
21741 || ((outer_code
== DIV
|| outer_code
== UDIV
21742 || outer_code
== MOD
|| outer_code
== UMOD
)
21743 && exact_log2 (INTVAL (x
)) >= 0)
21744 || (outer_code
== COMPARE
21745 && (satisfies_constraint_I (x
)
21746 || satisfies_constraint_K (x
)))
21747 || (outer_code
== EQ
21748 && (satisfies_constraint_I (x
)
21749 || satisfies_constraint_K (x
)
21751 ? satisfies_constraint_L (x
)
21752 : satisfies_constraint_J (x
))))
21753 || (outer_code
== GTU
21754 && satisfies_constraint_I (x
))
21755 || (outer_code
== LTU
21756 && satisfies_constraint_P (x
)))
21761 else if ((outer_code
== PLUS
21762 && reg_or_add_cint_operand (x
, VOIDmode
))
21763 || (outer_code
== MINUS
21764 && reg_or_sub_cint_operand (x
, VOIDmode
))
21765 || ((outer_code
== SET
21766 || outer_code
== IOR
21767 || outer_code
== XOR
)
21769 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
21771 *total
= COSTS_N_INSNS (1);
21777 if (mode
== DImode
&& code
== CONST_DOUBLE
)
21779 if ((outer_code
== IOR
|| outer_code
== XOR
)
21780 && CONST_DOUBLE_HIGH (x
) == 0
21781 && (CONST_DOUBLE_LOW (x
)
21782 & ~ (unsigned HOST_WIDE_INT
) 0xffff) == 0)
21787 else if ((outer_code
== AND
&& and64_2_operand (x
, DImode
))
21788 || ((outer_code
== SET
21789 || outer_code
== IOR
21790 || outer_code
== XOR
)
21791 && CONST_DOUBLE_HIGH (x
) == 0))
21793 *total
= COSTS_N_INSNS (1);
21803 /* When optimizing for size, MEM should be slightly more expensive
21804 than generating address, e.g., (plus (reg) (const)).
21805 L1 cache latency is about two instructions. */
21806 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
21814 if (mode
== DFmode
)
21816 if (GET_CODE (XEXP (x
, 0)) == MULT
)
21818 /* FNMA accounted in outer NEG. */
21819 if (outer_code
== NEG
)
21820 *total
= rs6000_cost
->dmul
- rs6000_cost
->fp
;
21822 *total
= rs6000_cost
->dmul
;
21825 *total
= rs6000_cost
->fp
;
21827 else if (mode
== SFmode
)
21829 /* FNMA accounted in outer NEG. */
21830 if (outer_code
== NEG
&& GET_CODE (XEXP (x
, 0)) == MULT
)
21833 *total
= rs6000_cost
->fp
;
21836 *total
= COSTS_N_INSNS (1);
21840 if (mode
== DFmode
)
21842 if (GET_CODE (XEXP (x
, 0)) == MULT
21843 || GET_CODE (XEXP (x
, 1)) == MULT
)
21845 /* FNMA accounted in outer NEG. */
21846 if (outer_code
== NEG
)
21847 *total
= rs6000_cost
->dmul
- rs6000_cost
->fp
;
21849 *total
= rs6000_cost
->dmul
;
21852 *total
= rs6000_cost
->fp
;
21854 else if (mode
== SFmode
)
21856 /* FNMA accounted in outer NEG. */
21857 if (outer_code
== NEG
&& GET_CODE (XEXP (x
, 0)) == MULT
)
21860 *total
= rs6000_cost
->fp
;
21863 *total
= COSTS_N_INSNS (1);
21867 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
21868 && satisfies_constraint_I (XEXP (x
, 1)))
21870 if (INTVAL (XEXP (x
, 1)) >= -256
21871 && INTVAL (XEXP (x
, 1)) <= 255)
21872 *total
= rs6000_cost
->mulsi_const9
;
21874 *total
= rs6000_cost
->mulsi_const
;
21876 /* FMA accounted in outer PLUS/MINUS. */
21877 else if ((mode
== DFmode
|| mode
== SFmode
)
21878 && (outer_code
== PLUS
|| outer_code
== MINUS
))
21880 else if (mode
== DFmode
)
21881 *total
= rs6000_cost
->dmul
;
21882 else if (mode
== SFmode
)
21883 *total
= rs6000_cost
->fp
;
21884 else if (mode
== DImode
)
21885 *total
= rs6000_cost
->muldi
;
21887 *total
= rs6000_cost
->mulsi
;
21892 if (FLOAT_MODE_P (mode
))
21894 *total
= mode
== DFmode
? rs6000_cost
->ddiv
21895 : rs6000_cost
->sdiv
;
21902 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
21903 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
21905 if (code
== DIV
|| code
== MOD
)
21907 *total
= COSTS_N_INSNS (2);
21910 *total
= COSTS_N_INSNS (1);
21914 if (GET_MODE (XEXP (x
, 1)) == DImode
)
21915 *total
= rs6000_cost
->divdi
;
21917 *total
= rs6000_cost
->divsi
;
21919 /* Add in shift and subtract for MOD. */
21920 if (code
== MOD
|| code
== UMOD
)
21921 *total
+= COSTS_N_INSNS (2);
21926 *total
= COSTS_N_INSNS (4);
21930 *total
= COSTS_N_INSNS (6);
21934 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
21946 *total
= COSTS_N_INSNS (1);
21954 /* Handle mul_highpart. */
21955 if (outer_code
== TRUNCATE
21956 && GET_CODE (XEXP (x
, 0)) == MULT
)
21958 if (mode
== DImode
)
21959 *total
= rs6000_cost
->muldi
;
21961 *total
= rs6000_cost
->mulsi
;
21964 else if (outer_code
== AND
)
21967 *total
= COSTS_N_INSNS (1);
21972 if (GET_CODE (XEXP (x
, 0)) == MEM
)
21975 *total
= COSTS_N_INSNS (1);
21981 if (!FLOAT_MODE_P (mode
))
21983 *total
= COSTS_N_INSNS (1);
21989 case UNSIGNED_FLOAT
:
21992 case FLOAT_TRUNCATE
:
21993 *total
= rs6000_cost
->fp
;
21997 if (mode
== DFmode
)
22000 *total
= rs6000_cost
->fp
;
22004 switch (XINT (x
, 1))
22007 *total
= rs6000_cost
->fp
;
22019 *total
= COSTS_N_INSNS (1);
22022 else if (FLOAT_MODE_P (mode
)
22023 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
22025 *total
= rs6000_cost
->fp
;
22033 /* Carry bit requires mode == Pmode.
22034 NEG or PLUS already counted so only add one. */
22036 && (outer_code
== NEG
|| outer_code
== PLUS
))
22038 *total
= COSTS_N_INSNS (1);
22041 if (outer_code
== SET
)
22043 if (XEXP (x
, 1) == const0_rtx
)
22045 *total
= COSTS_N_INSNS (2);
22048 else if (mode
== Pmode
)
22050 *total
= COSTS_N_INSNS (3);
22059 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
22061 *total
= COSTS_N_INSNS (2);
22065 if (outer_code
== COMPARE
)
22079 /* A C expression returning the cost of moving data from a register of class
22080 CLASS1 to one of CLASS2. */
22083 rs6000_register_move_cost (enum machine_mode mode
,
22084 enum reg_class from
, enum reg_class to
)
22086 /* Moves from/to GENERAL_REGS. */
22087 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
22088 || reg_classes_intersect_p (from
, GENERAL_REGS
))
22090 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
22093 if (from
== FLOAT_REGS
|| from
== ALTIVEC_REGS
)
22094 return (rs6000_memory_move_cost (mode
, from
, 0)
22095 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, 0));
22097 /* It's more expensive to move CR_REGS than CR0_REGS because of the
22099 else if (from
== CR_REGS
)
22102 /* Power6 has slower LR/CTR moves so make them more expensive than
22103 memory in order to bias spills to memory .*/
22104 else if (rs6000_cpu
== PROCESSOR_POWER6
22105 && reg_classes_intersect_p (from
, LINK_OR_CTR_REGS
))
22106 return 6 * hard_regno_nregs
[0][mode
];
22109 /* A move will cost one instruction per GPR moved. */
22110 return 2 * hard_regno_nregs
[0][mode
];
22113 /* Moving between two similar registers is just one instruction. */
22114 else if (reg_classes_intersect_p (to
, from
))
22115 return (mode
== TFmode
|| mode
== TDmode
) ? 4 : 2;
22117 /* Everything else has to go through GENERAL_REGS. */
22119 return (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
22120 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
22123 /* A C expressions returning the cost of moving data of MODE from a register to
22127 rs6000_memory_move_cost (enum machine_mode mode
, enum reg_class rclass
,
22128 int in ATTRIBUTE_UNUSED
)
22130 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
22131 return 4 * hard_regno_nregs
[0][mode
];
22132 else if (reg_classes_intersect_p (rclass
, FLOAT_REGS
))
22133 return 4 * hard_regno_nregs
[32][mode
];
22134 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
22135 return 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
22137 return 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
22140 /* Returns a code for a target-specific builtin that implements
22141 reciprocal of the function, or NULL_TREE if not available. */
22144 rs6000_builtin_reciprocal (unsigned int fn
, bool md_fn
,
22145 bool sqrt ATTRIBUTE_UNUSED
)
22147 if (! (TARGET_RECIP
&& TARGET_PPC_GFXOPT
&& !optimize_size
22148 && flag_finite_math_only
&& !flag_trapping_math
22149 && flag_unsafe_math_optimizations
))
22157 case BUILT_IN_SQRTF
:
22158 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRTF
];
22165 /* Newton-Raphson approximation of single-precision floating point divide n/d.
22166 Assumes no trapping math and finite arguments. */
22169 rs6000_emit_swdivsf (rtx dst
, rtx n
, rtx d
)
22171 rtx x0
, e0
, e1
, y1
, u0
, v0
, one
;
22173 x0
= gen_reg_rtx (SFmode
);
22174 e0
= gen_reg_rtx (SFmode
);
22175 e1
= gen_reg_rtx (SFmode
);
22176 y1
= gen_reg_rtx (SFmode
);
22177 u0
= gen_reg_rtx (SFmode
);
22178 v0
= gen_reg_rtx (SFmode
);
22179 one
= force_reg (SFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconst1
, SFmode
));
22181 /* x0 = 1./d estimate */
22182 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
22183 gen_rtx_UNSPEC (SFmode
, gen_rtvec (1, d
),
22185 /* e0 = 1. - d * x0 */
22186 emit_insn (gen_rtx_SET (VOIDmode
, e0
,
22187 gen_rtx_MINUS (SFmode
, one
,
22188 gen_rtx_MULT (SFmode
, d
, x0
))));
22189 /* e1 = e0 + e0 * e0 */
22190 emit_insn (gen_rtx_SET (VOIDmode
, e1
,
22191 gen_rtx_PLUS (SFmode
,
22192 gen_rtx_MULT (SFmode
, e0
, e0
), e0
)));
22193 /* y1 = x0 + e1 * x0 */
22194 emit_insn (gen_rtx_SET (VOIDmode
, y1
,
22195 gen_rtx_PLUS (SFmode
,
22196 gen_rtx_MULT (SFmode
, e1
, x0
), x0
)));
22198 emit_insn (gen_rtx_SET (VOIDmode
, u0
,
22199 gen_rtx_MULT (SFmode
, n
, y1
)));
22200 /* v0 = n - d * u0 */
22201 emit_insn (gen_rtx_SET (VOIDmode
, v0
,
22202 gen_rtx_MINUS (SFmode
, n
,
22203 gen_rtx_MULT (SFmode
, d
, u0
))));
22204 /* dst = u0 + v0 * y1 */
22205 emit_insn (gen_rtx_SET (VOIDmode
, dst
,
22206 gen_rtx_PLUS (SFmode
,
22207 gen_rtx_MULT (SFmode
, v0
, y1
), u0
)));
22210 /* Newton-Raphson approximation of double-precision floating point divide n/d.
22211 Assumes no trapping math and finite arguments. */
22214 rs6000_emit_swdivdf (rtx dst
, rtx n
, rtx d
)
22216 rtx x0
, e0
, e1
, e2
, y1
, y2
, y3
, u0
, v0
, one
;
22218 x0
= gen_reg_rtx (DFmode
);
22219 e0
= gen_reg_rtx (DFmode
);
22220 e1
= gen_reg_rtx (DFmode
);
22221 e2
= gen_reg_rtx (DFmode
);
22222 y1
= gen_reg_rtx (DFmode
);
22223 y2
= gen_reg_rtx (DFmode
);
22224 y3
= gen_reg_rtx (DFmode
);
22225 u0
= gen_reg_rtx (DFmode
);
22226 v0
= gen_reg_rtx (DFmode
);
22227 one
= force_reg (DFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconst1
, DFmode
));
22229 /* x0 = 1./d estimate */
22230 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
22231 gen_rtx_UNSPEC (DFmode
, gen_rtvec (1, d
),
22233 /* e0 = 1. - d * x0 */
22234 emit_insn (gen_rtx_SET (VOIDmode
, e0
,
22235 gen_rtx_MINUS (DFmode
, one
,
22236 gen_rtx_MULT (SFmode
, d
, x0
))));
22237 /* y1 = x0 + e0 * x0 */
22238 emit_insn (gen_rtx_SET (VOIDmode
, y1
,
22239 gen_rtx_PLUS (DFmode
,
22240 gen_rtx_MULT (DFmode
, e0
, x0
), x0
)));
22242 emit_insn (gen_rtx_SET (VOIDmode
, e1
,
22243 gen_rtx_MULT (DFmode
, e0
, e0
)));
22244 /* y2 = y1 + e1 * y1 */
22245 emit_insn (gen_rtx_SET (VOIDmode
, y2
,
22246 gen_rtx_PLUS (DFmode
,
22247 gen_rtx_MULT (DFmode
, e1
, y1
), y1
)));
22249 emit_insn (gen_rtx_SET (VOIDmode
, e2
,
22250 gen_rtx_MULT (DFmode
, e1
, e1
)));
22251 /* y3 = y2 + e2 * y2 */
22252 emit_insn (gen_rtx_SET (VOIDmode
, y3
,
22253 gen_rtx_PLUS (DFmode
,
22254 gen_rtx_MULT (DFmode
, e2
, y2
), y2
)));
22256 emit_insn (gen_rtx_SET (VOIDmode
, u0
,
22257 gen_rtx_MULT (DFmode
, n
, y3
)));
22258 /* v0 = n - d * u0 */
22259 emit_insn (gen_rtx_SET (VOIDmode
, v0
,
22260 gen_rtx_MINUS (DFmode
, n
,
22261 gen_rtx_MULT (DFmode
, d
, u0
))));
22262 /* dst = u0 + v0 * y3 */
22263 emit_insn (gen_rtx_SET (VOIDmode
, dst
,
22264 gen_rtx_PLUS (DFmode
,
22265 gen_rtx_MULT (DFmode
, v0
, y3
), u0
)));
22269 /* Newton-Raphson approximation of single-precision floating point rsqrt.
22270 Assumes no trapping math and finite arguments. */
22273 rs6000_emit_swrsqrtsf (rtx dst
, rtx src
)
22275 rtx x0
, x1
, x2
, y1
, u0
, u1
, u2
, v0
, v1
, v2
, t0
,
22276 half
, one
, halfthree
, c1
, cond
, label
;
22278 x0
= gen_reg_rtx (SFmode
);
22279 x1
= gen_reg_rtx (SFmode
);
22280 x2
= gen_reg_rtx (SFmode
);
22281 y1
= gen_reg_rtx (SFmode
);
22282 u0
= gen_reg_rtx (SFmode
);
22283 u1
= gen_reg_rtx (SFmode
);
22284 u2
= gen_reg_rtx (SFmode
);
22285 v0
= gen_reg_rtx (SFmode
);
22286 v1
= gen_reg_rtx (SFmode
);
22287 v2
= gen_reg_rtx (SFmode
);
22288 t0
= gen_reg_rtx (SFmode
);
22289 halfthree
= gen_reg_rtx (SFmode
);
22290 cond
= gen_rtx_REG (CCFPmode
, CR1_REGNO
);
22291 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
22293 /* check 0.0, 1.0, NaN, Inf by testing src * src = src */
22294 emit_insn (gen_rtx_SET (VOIDmode
, t0
,
22295 gen_rtx_MULT (SFmode
, src
, src
)));
22297 emit_insn (gen_rtx_SET (VOIDmode
, cond
,
22298 gen_rtx_COMPARE (CCFPmode
, t0
, src
)));
22299 c1
= gen_rtx_EQ (VOIDmode
, cond
, const0_rtx
);
22300 emit_unlikely_jump (c1
, label
);
22302 half
= force_reg (SFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconsthalf
, SFmode
));
22303 one
= force_reg (SFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconst1
, SFmode
));
22305 /* halfthree = 1.5 = 1.0 + 0.5 */
22306 emit_insn (gen_rtx_SET (VOIDmode
, halfthree
,
22307 gen_rtx_PLUS (SFmode
, one
, half
)));
22309 /* x0 = rsqrt estimate */
22310 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
22311 gen_rtx_UNSPEC (SFmode
, gen_rtvec (1, src
),
22314 /* y1 = 0.5 * src = 1.5 * src - src -> fewer constants */
22315 emit_insn (gen_rtx_SET (VOIDmode
, y1
,
22316 gen_rtx_MINUS (SFmode
,
22317 gen_rtx_MULT (SFmode
, src
, halfthree
),
22320 /* x1 = x0 * (1.5 - y1 * (x0 * x0)) */
22321 emit_insn (gen_rtx_SET (VOIDmode
, u0
,
22322 gen_rtx_MULT (SFmode
, x0
, x0
)));
22323 emit_insn (gen_rtx_SET (VOIDmode
, v0
,
22324 gen_rtx_MINUS (SFmode
,
22326 gen_rtx_MULT (SFmode
, y1
, u0
))));
22327 emit_insn (gen_rtx_SET (VOIDmode
, x1
,
22328 gen_rtx_MULT (SFmode
, x0
, v0
)));
22330 /* x2 = x1 * (1.5 - y1 * (x1 * x1)) */
22331 emit_insn (gen_rtx_SET (VOIDmode
, u1
,
22332 gen_rtx_MULT (SFmode
, x1
, x1
)));
22333 emit_insn (gen_rtx_SET (VOIDmode
, v1
,
22334 gen_rtx_MINUS (SFmode
,
22336 gen_rtx_MULT (SFmode
, y1
, u1
))));
22337 emit_insn (gen_rtx_SET (VOIDmode
, x2
,
22338 gen_rtx_MULT (SFmode
, x1
, v1
)));
22340 /* dst = x2 * (1.5 - y1 * (x2 * x2)) */
22341 emit_insn (gen_rtx_SET (VOIDmode
, u2
,
22342 gen_rtx_MULT (SFmode
, x2
, x2
)));
22343 emit_insn (gen_rtx_SET (VOIDmode
, v2
,
22344 gen_rtx_MINUS (SFmode
,
22346 gen_rtx_MULT (SFmode
, y1
, u2
))));
22347 emit_insn (gen_rtx_SET (VOIDmode
, dst
,
22348 gen_rtx_MULT (SFmode
, x2
, v2
)));
22350 emit_label (XEXP (label
, 0));
22353 /* Emit popcount intrinsic on TARGET_POPCNTB targets. DST is the
22354 target, and SRC is the argument operand. */
22357 rs6000_emit_popcount (rtx dst
, rtx src
)
22359 enum machine_mode mode
= GET_MODE (dst
);
22362 tmp1
= gen_reg_rtx (mode
);
22364 if (mode
== SImode
)
22366 emit_insn (gen_popcntbsi2 (tmp1
, src
));
22367 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
22369 tmp2
= force_reg (SImode
, tmp2
);
22370 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
22374 emit_insn (gen_popcntbdi2 (tmp1
, src
));
22375 tmp2
= expand_mult (DImode
, tmp1
,
22376 GEN_INT ((HOST_WIDE_INT
)
22377 0x01010101 << 32 | 0x01010101),
22379 tmp2
= force_reg (DImode
, tmp2
);
22380 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
22385 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
22386 target, and SRC is the argument operand. */
22389 rs6000_emit_parity (rtx dst
, rtx src
)
22391 enum machine_mode mode
= GET_MODE (dst
);
22394 tmp
= gen_reg_rtx (mode
);
22395 if (mode
== SImode
)
22397 /* Is mult+shift >= shift+xor+shift+xor? */
22398 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
22400 rtx tmp1
, tmp2
, tmp3
, tmp4
;
22402 tmp1
= gen_reg_rtx (SImode
);
22403 emit_insn (gen_popcntbsi2 (tmp1
, src
));
22405 tmp2
= gen_reg_rtx (SImode
);
22406 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
22407 tmp3
= gen_reg_rtx (SImode
);
22408 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
22410 tmp4
= gen_reg_rtx (SImode
);
22411 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
22412 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
22415 rs6000_emit_popcount (tmp
, src
);
22416 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
22420 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
22421 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
22423 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
22425 tmp1
= gen_reg_rtx (DImode
);
22426 emit_insn (gen_popcntbdi2 (tmp1
, src
));
22428 tmp2
= gen_reg_rtx (DImode
);
22429 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
22430 tmp3
= gen_reg_rtx (DImode
);
22431 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
22433 tmp4
= gen_reg_rtx (DImode
);
22434 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
22435 tmp5
= gen_reg_rtx (DImode
);
22436 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
22438 tmp6
= gen_reg_rtx (DImode
);
22439 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
22440 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
22443 rs6000_emit_popcount (tmp
, src
);
22444 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
22448 /* Return an RTX representing where to find the function value of a
22449 function returning MODE. */
22451 rs6000_complex_function_value (enum machine_mode mode
)
22453 unsigned int regno
;
22455 enum machine_mode inner
= GET_MODE_INNER (mode
);
22456 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
22458 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
22459 regno
= FP_ARG_RETURN
;
22462 regno
= GP_ARG_RETURN
;
22464 /* 32-bit is OK since it'll go in r3/r4. */
22465 if (TARGET_32BIT
&& inner_bytes
>= 4)
22466 return gen_rtx_REG (mode
, regno
);
22469 if (inner_bytes
>= 8)
22470 return gen_rtx_REG (mode
, regno
);
22472 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
22474 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
22475 GEN_INT (inner_bytes
));
22476 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
22479 /* Define how to find the value returned by a function.
22480 VALTYPE is the data type of the value (as a tree).
22481 If the precise function being called is known, FUNC is its FUNCTION_DECL;
22482 otherwise, FUNC is 0.
22484 On the SPE, both FPs and vectors are returned in r3.
22486 On RS/6000 an integer value is in r3 and a floating-point value is in
22487 fp1, unless -msoft-float. */
22490 rs6000_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
22492 enum machine_mode mode
;
22493 unsigned int regno
;
22495 /* Special handling for structs in darwin64. */
22496 if (rs6000_darwin64_abi
22497 && TYPE_MODE (valtype
) == BLKmode
22498 && TREE_CODE (valtype
) == RECORD_TYPE
22499 && int_size_in_bytes (valtype
) > 0)
22501 CUMULATIVE_ARGS valcum
;
22505 valcum
.fregno
= FP_ARG_MIN_REG
;
22506 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
22507 /* Do a trial code generation as if this were going to be passed as
22508 an argument; if any part goes in memory, we return NULL. */
22509 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, 1, true);
22512 /* Otherwise fall through to standard ABI rules. */
22515 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
22517 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
22518 return gen_rtx_PARALLEL (DImode
,
22520 gen_rtx_EXPR_LIST (VOIDmode
,
22521 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
22523 gen_rtx_EXPR_LIST (VOIDmode
,
22524 gen_rtx_REG (SImode
,
22525 GP_ARG_RETURN
+ 1),
22528 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DCmode
)
22530 return gen_rtx_PARALLEL (DCmode
,
22532 gen_rtx_EXPR_LIST (VOIDmode
,
22533 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
22535 gen_rtx_EXPR_LIST (VOIDmode
,
22536 gen_rtx_REG (SImode
,
22537 GP_ARG_RETURN
+ 1),
22539 gen_rtx_EXPR_LIST (VOIDmode
,
22540 gen_rtx_REG (SImode
,
22541 GP_ARG_RETURN
+ 2),
22543 gen_rtx_EXPR_LIST (VOIDmode
,
22544 gen_rtx_REG (SImode
,
22545 GP_ARG_RETURN
+ 3),
22549 mode
= TYPE_MODE (valtype
);
22550 if ((INTEGRAL_TYPE_P (valtype
) && GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
22551 || POINTER_TYPE_P (valtype
))
22552 mode
= TARGET_32BIT
? SImode
: DImode
;
22554 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
22555 /* _Decimal128 must use an even/odd register pair. */
22556 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
22557 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
22558 && ((TARGET_SINGLE_FLOAT
&& (mode
== SFmode
)) || TARGET_DOUBLE_FLOAT
))
22559 regno
= FP_ARG_RETURN
;
22560 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
22561 && targetm
.calls
.split_complex_arg
)
22562 return rs6000_complex_function_value (mode
);
22563 else if (TREE_CODE (valtype
) == VECTOR_TYPE
22564 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
22565 && ALTIVEC_VECTOR_MODE (mode
))
22566 regno
= ALTIVEC_ARG_RETURN
;
22567 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
22568 && (mode
== DFmode
|| mode
== DCmode
22569 || mode
== TFmode
|| mode
== TCmode
))
22570 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
22572 regno
= GP_ARG_RETURN
;
22574 return gen_rtx_REG (mode
, regno
);
22577 /* Define how to find the value returned by a library function
22578 assuming the value has mode MODE. */
22580 rs6000_libcall_value (enum machine_mode mode
)
22582 unsigned int regno
;
22584 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
22586 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
22587 return gen_rtx_PARALLEL (DImode
,
22589 gen_rtx_EXPR_LIST (VOIDmode
,
22590 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
22592 gen_rtx_EXPR_LIST (VOIDmode
,
22593 gen_rtx_REG (SImode
,
22594 GP_ARG_RETURN
+ 1),
22598 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
22599 /* _Decimal128 must use an even/odd register pair. */
22600 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
22601 else if (SCALAR_FLOAT_MODE_P (mode
)
22602 && TARGET_HARD_FLOAT
&& TARGET_FPRS
22603 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
) || TARGET_DOUBLE_FLOAT
))
22604 regno
= FP_ARG_RETURN
;
22605 else if (ALTIVEC_VECTOR_MODE (mode
)
22606 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
22607 regno
= ALTIVEC_ARG_RETURN
;
22608 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
22609 return rs6000_complex_function_value (mode
);
22610 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
22611 && (mode
== DFmode
|| mode
== DCmode
22612 || mode
== TFmode
|| mode
== TCmode
))
22613 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
22615 regno
= GP_ARG_RETURN
;
22617 return gen_rtx_REG (mode
, regno
);
22620 /* Define the offset between two registers, FROM to be eliminated and its
22621 replacement TO, at the start of a routine. */
22623 rs6000_initial_elimination_offset (int from
, int to
)
22625 rs6000_stack_t
*info
= rs6000_stack_info ();
22626 HOST_WIDE_INT offset
;
22628 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
22629 offset
= info
->push_p
? 0 : -info
->total_size
;
22630 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
22632 offset
= info
->push_p
? 0 : -info
->total_size
;
22633 if (FRAME_GROWS_DOWNWARD
)
22634 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
22636 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
22637 offset
= FRAME_GROWS_DOWNWARD
22638 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
22640 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
22641 offset
= info
->total_size
;
22642 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
22643 offset
= info
->push_p
? info
->total_size
: 0;
22644 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
22647 gcc_unreachable ();
22653 rs6000_dwarf_register_span (rtx reg
)
22657 unsigned regno
= REGNO (reg
);
22658 enum machine_mode mode
= GET_MODE (reg
);
22662 && (SPE_VECTOR_MODE (GET_MODE (reg
))
22663 || (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
)
22664 && mode
!= SFmode
&& mode
!= SDmode
&& mode
!= SCmode
)))
22669 regno
= REGNO (reg
);
22671 /* The duality of the SPE register size wreaks all kinds of havoc.
22672 This is a way of distinguishing r0 in 32-bits from r0 in
22674 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
22675 gcc_assert (words
<= 4);
22676 for (i
= 0; i
< words
; i
++, regno
++)
22678 if (BYTES_BIG_ENDIAN
)
22680 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
+ 1200);
22681 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
);
22685 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
);
22686 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
+ 1200);
22690 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (words
* 2, parts
));
22693 /* Fill in sizes for SPE register high parts in table used by unwinder. */
22696 rs6000_init_dwarf_reg_sizes_extra (tree address
)
22701 enum machine_mode mode
= TYPE_MODE (char_type_node
);
22702 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
22703 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
22704 rtx value
= gen_int_mode (4, mode
);
22706 for (i
= 1201; i
< 1232; i
++)
22708 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
22709 HOST_WIDE_INT offset
22710 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
22712 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
22717 /* Map internal gcc register numbers to DWARF2 register numbers. */
22720 rs6000_dbx_register_number (unsigned int regno
)
22722 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
22724 if (regno
== MQ_REGNO
)
22726 if (regno
== LR_REGNO
)
22728 if (regno
== CTR_REGNO
)
22730 if (CR_REGNO_P (regno
))
22731 return regno
- CR0_REGNO
+ 86;
22732 if (regno
== XER_REGNO
)
22734 if (ALTIVEC_REGNO_P (regno
))
22735 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
22736 if (regno
== VRSAVE_REGNO
)
22738 if (regno
== VSCR_REGNO
)
22740 if (regno
== SPE_ACC_REGNO
)
22742 if (regno
== SPEFSCR_REGNO
)
22744 /* SPE high reg number. We get these values of regno from
22745 rs6000_dwarf_register_span. */
22746 gcc_assert (regno
>= 1200 && regno
< 1232);
22750 /* target hook eh_return_filter_mode */
22751 static enum machine_mode
22752 rs6000_eh_return_filter_mode (void)
22754 return TARGET_32BIT
? SImode
: word_mode
;
22757 /* Target hook for scalar_mode_supported_p. */
22759 rs6000_scalar_mode_supported_p (enum machine_mode mode
)
22761 if (DECIMAL_FLOAT_MODE_P (mode
))
22764 return default_scalar_mode_supported_p (mode
);
22767 /* Target hook for vector_mode_supported_p. */
22769 rs6000_vector_mode_supported_p (enum machine_mode mode
)
22772 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
22775 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
22778 else if (TARGET_ALTIVEC
&& ALTIVEC_VECTOR_MODE (mode
))
22785 /* Target hook for invalid_arg_for_unprototyped_fn. */
22786 static const char *
22787 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
22789 return (!rs6000_darwin64_abi
22791 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
22792 && (funcdecl
== NULL_TREE
22793 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
22794 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
22795 ? N_("AltiVec argument passed to unprototyped function")
22799 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
22800 setup by using __stack_chk_fail_local hidden function instead of
22801 calling __stack_chk_fail directly. Otherwise it is better to call
22802 __stack_chk_fail directly. */
22805 rs6000_stack_protect_fail (void)
22807 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
22808 ? default_hidden_stack_protect_fail ()
22809 : default_external_stack_protect_fail ();
22813 rs6000_final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
22814 int num_operands ATTRIBUTE_UNUSED
)
22816 if (rs6000_warn_cell_microcode
)
22819 int insn_code_number
= recog_memoized (insn
);
22820 location_t location
= locator_location (INSN_LOCATOR (insn
));
22822 /* Punt on insns we cannot recognize. */
22823 if (insn_code_number
< 0)
22826 temp
= get_insn_template (insn_code_number
, insn
);
22828 if (get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
)
22829 warning_at (location
, OPT_mwarn_cell_microcode
,
22830 "emitting microcode insn %s\t[%s] #%d",
22831 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
22832 else if (get_attr_cell_micro (insn
) == CELL_MICRO_CONDITIONAL
)
22833 warning_at (location
, OPT_mwarn_cell_microcode
,
22834 "emitting conditional microcode insn %s\t[%s] #%d",
22835 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
22839 #include "gt-rs6000.h"