1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 #include "insn-codes.h"
95 #include "rtlhooks-def.h"
96 /* Include output.h for dump_file. */
100 /* Number of attempts to combine instructions in this function. */
102 static int combine_attempts
;
104 /* Number of attempts that got as far as substitution in this function. */
106 static int combine_merges
;
108 /* Number of instructions combined with added SETs in this function. */
110 static int combine_extras
;
112 /* Number of instructions combined in this function. */
114 static int combine_successes
;
116 /* Totals over entire compilation. */
118 static int total_attempts
, total_merges
, total_extras
, total_successes
;
121 /* Vector mapping INSN_UIDs to cuids.
122 The cuids are like uids but increase monotonically always.
123 Combine always uses cuids so that it can compare them.
124 But actually renumbering the uids, which we used to do,
125 proves to be a bad idea because it makes it hard to compare
126 the dumps produced by earlier passes with those from later passes. */
128 static int *uid_cuid
;
129 static int max_uid_cuid
;
131 /* Get the cuid of an insn. */
133 #define INSN_CUID(INSN) \
134 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
136 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
137 BITS_PER_WORD would invoke undefined behavior. Work around it. */
139 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
140 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
142 /* Maximum register number, which is the size of the tables below. */
144 static unsigned int combine_max_regno
;
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick
;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
216 char last_set_sign_bit_copies
;
217 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid
;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies
;
239 unsigned HOST_WIDE_INT nonzero_bits
;
242 static struct reg_stat
*reg_stat
;
244 /* Record the cuid of the last insn that invalidated memory
245 (anything that writes memory, and subroutine calls, but not pushes). */
247 static int mem_last_set
;
249 /* Record the cuid of the last CALL_INSN
250 so we can tell whether a potential combination crosses any calls. */
252 static int last_call_cuid
;
254 /* When `subst' is called, this is the insn that is being modified
255 (by combining in a previous insn). The PATTERN of this insn
256 is still the old pattern partially modified and it should not be
257 looked at, but this may be used to examine the successors of the insn
258 to judge whether a simplification is valid. */
260 static rtx subst_insn
;
262 /* This is the lowest CUID that `subst' is currently dealing with.
263 get_last_value will not return a value if the register was set at or
264 after this CUID. If not for this mechanism, we could get confused if
265 I2 or I1 in try_combine were an insn that used the old value of a register
266 to obtain a new value. In that case, we might erroneously get the
267 new value of the register when we wanted the old one. */
269 static int subst_low_cuid
;
271 /* This contains any hard registers that are used in newpat; reg_dead_at_p
272 must consider all these registers to be always live. */
274 static HARD_REG_SET newpat_used_regs
;
276 /* This is an insn to which a LOG_LINKS entry has been added. If this
277 insn is the earlier than I2 or I3, combine should rescan starting at
280 static rtx added_links_insn
;
282 /* Basic block in which we are performing combines. */
283 static basic_block this_basic_block
;
285 /* A bitmap indicating which blocks had registers go dead at entry.
286 After combine, we'll need to re-do global life analysis with
287 those blocks as starting points. */
288 static sbitmap refresh_blocks
;
290 /* The following array records the insn_rtx_cost for every insn
291 in the instruction stream. */
293 static int *uid_insn_cost
;
295 /* Length of the currently allocated uid_insn_cost array. */
297 static int last_insn_cost
;
299 /* Incremented for each label. */
301 static int label_tick
;
303 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
304 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
306 static enum machine_mode nonzero_bits_mode
;
308 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
309 be safely used. It is zero while computing them and after combine has
310 completed. This former test prevents propagating values based on
311 previously set values, which can be incorrect if a variable is modified
314 static int nonzero_sign_valid
;
317 /* Record one modification to rtl structure
318 to be undone by storing old_contents into *where.
319 is_int is 1 if the contents are an int. */
325 union {rtx r
; int i
;} old_contents
;
326 union {rtx
*r
; int *i
;} where
;
329 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
330 num_undo says how many are currently recorded.
332 other_insn is nonzero if we have modified some other insn in the process
333 of working on subst_insn. It must be verified too. */
342 static struct undobuf undobuf
;
344 /* Number of times the pseudo being substituted for
345 was found and replaced. */
347 static int n_occurrences
;
349 static rtx
reg_nonzero_bits_for_combine (rtx
, enum machine_mode
, rtx
,
351 unsigned HOST_WIDE_INT
,
352 unsigned HOST_WIDE_INT
*);
353 static rtx
reg_num_sign_bit_copies_for_combine (rtx
, enum machine_mode
, rtx
,
355 unsigned int, unsigned int *);
356 static void do_SUBST (rtx
*, rtx
);
357 static void do_SUBST_INT (int *, int);
358 static void init_reg_last (void);
359 static void setup_incoming_promotions (void);
360 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
361 static int cant_combine_insn_p (rtx
);
362 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
363 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
364 static int contains_muldiv (rtx
);
365 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
366 static void undo_all (void);
367 static void undo_commit (void);
368 static rtx
*find_split_point (rtx
*, rtx
);
369 static rtx
subst (rtx
, rtx
, rtx
, int, int);
370 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int);
371 static rtx
simplify_if_then_else (rtx
);
372 static rtx
simplify_set (rtx
);
373 static rtx
simplify_logical (rtx
);
374 static rtx
expand_compound_operation (rtx
);
375 static rtx
expand_field_assignment (rtx
);
376 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
377 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
378 static rtx
extract_left_shift (rtx
, int);
379 static rtx
make_compound_operation (rtx
, enum rtx_code
);
380 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
381 unsigned HOST_WIDE_INT
*);
382 static rtx
force_to_mode (rtx
, enum machine_mode
,
383 unsigned HOST_WIDE_INT
, rtx
, int);
384 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
385 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
386 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
387 static rtx
make_field_assignment (rtx
);
388 static rtx
apply_distributive_law (rtx
);
389 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
390 unsigned HOST_WIDE_INT
);
391 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
392 HOST_WIDE_INT
, enum machine_mode
, int *);
393 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
395 static int recog_for_combine (rtx
*, rtx
, rtx
*);
396 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
397 static rtx
gen_binary (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
398 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
399 static void update_table_tick (rtx
);
400 static void record_value_for_reg (rtx
, rtx
, rtx
);
401 static void check_promoted_subreg (rtx
, rtx
);
402 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
403 static void record_dead_and_set_regs (rtx
);
404 static int get_last_value_validate (rtx
*, rtx
, int, int);
405 static rtx
get_last_value (rtx
);
406 static int use_crosses_set_p (rtx
, int);
407 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
408 static int reg_dead_at_p (rtx
, rtx
);
409 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
410 static int reg_bitfield_target_p (rtx
, rtx
);
411 static void distribute_notes (rtx
, rtx
, rtx
, rtx
);
412 static void distribute_links (rtx
);
413 static void mark_used_regs_combine (rtx
);
414 static int insn_cuid (rtx
);
415 static void record_promoted_value (rtx
, rtx
);
416 static rtx
reversed_comparison (rtx
, enum machine_mode
, rtx
, rtx
);
417 static enum rtx_code
combine_reversed_comparison_code (rtx
);
418 static int unmentioned_reg_p_1 (rtx
*, void *);
419 static bool unmentioned_reg_p (rtx
, rtx
);
422 /* It is not safe to use ordinary gen_lowpart in combine.
423 See comments in gen_lowpart_for_combine. */
424 #undef RTL_HOOKS_GEN_LOWPART
425 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
427 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
428 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
430 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
431 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
433 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
436 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
437 insn. The substitution can be undone by undo_all. If INTO is already
438 set to NEWVAL, do not record this change. Because computing NEWVAL might
439 also call SUBST, we have to compute it before we put anything into
443 do_SUBST (rtx
*into
, rtx newval
)
448 if (oldval
== newval
)
451 /* We'd like to catch as many invalid transformations here as
452 possible. Unfortunately, there are way too many mode changes
453 that are perfectly valid, so we'd waste too much effort for
454 little gain doing the checks here. Focus on catching invalid
455 transformations involving integer constants. */
456 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
457 && GET_CODE (newval
) == CONST_INT
)
459 /* Sanity check that we're replacing oldval with a CONST_INT
460 that is a valid sign-extension for the original mode. */
461 gcc_assert (INTVAL (newval
)
462 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
464 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
465 CONST_INT is not valid, because after the replacement, the
466 original mode would be gone. Unfortunately, we can't tell
467 when do_SUBST is called to replace the operand thereof, so we
468 perform this test on oldval instead, checking whether an
469 invalid replacement took place before we got here. */
470 gcc_assert (!(GET_CODE (oldval
) == SUBREG
471 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
));
472 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
473 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
));
477 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
479 buf
= xmalloc (sizeof (struct undo
));
483 buf
->old_contents
.r
= oldval
;
486 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
489 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
491 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
492 for the value of a HOST_WIDE_INT value (including CONST_INT) is
496 do_SUBST_INT (int *into
, int newval
)
501 if (oldval
== newval
)
505 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
507 buf
= xmalloc (sizeof (struct undo
));
511 buf
->old_contents
.i
= oldval
;
514 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
517 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
519 /* Subroutine of try_combine. Determine whether the combine replacement
520 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
521 that the original instruction sequence I1, I2 and I3. Note that I1
522 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
523 costs of all instructions can be estimated, and the replacements are
524 more expensive than the original sequence. */
527 combine_validate_cost (rtx i1
, rtx i2
, rtx i3
, rtx newpat
, rtx newi2pat
)
529 int i1_cost
, i2_cost
, i3_cost
;
530 int new_i2_cost
, new_i3_cost
;
531 int old_cost
, new_cost
;
533 /* Lookup the original insn_rtx_costs. */
534 i2_cost
= INSN_UID (i2
) <= last_insn_cost
535 ? uid_insn_cost
[INSN_UID (i2
)] : 0;
536 i3_cost
= INSN_UID (i3
) <= last_insn_cost
537 ? uid_insn_cost
[INSN_UID (i3
)] : 0;
541 i1_cost
= INSN_UID (i1
) <= last_insn_cost
542 ? uid_insn_cost
[INSN_UID (i1
)] : 0;
543 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0)
544 ? i1_cost
+ i2_cost
+ i3_cost
: 0;
548 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
552 /* Calculate the replacement insn_rtx_costs. */
553 new_i3_cost
= insn_rtx_cost (newpat
);
556 new_i2_cost
= insn_rtx_cost (newi2pat
);
557 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
558 ? new_i2_cost
+ new_i3_cost
: 0;
562 new_cost
= new_i3_cost
;
566 if (undobuf
.other_insn
)
568 int old_other_cost
, new_other_cost
;
570 old_other_cost
= (INSN_UID (undobuf
.other_insn
) <= last_insn_cost
571 ? uid_insn_cost
[INSN_UID (undobuf
.other_insn
)] : 0);
572 new_other_cost
= insn_rtx_cost (PATTERN (undobuf
.other_insn
));
573 if (old_other_cost
> 0 && new_other_cost
> 0)
575 old_cost
+= old_other_cost
;
576 new_cost
+= new_other_cost
;
582 /* Disallow this recombination if both new_cost and old_cost are
583 greater than zero, and new_cost is greater than old cost. */
585 && new_cost
> old_cost
)
592 "rejecting combination of insns %d, %d and %d\n",
593 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
594 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
595 i1_cost
, i2_cost
, i3_cost
, old_cost
);
600 "rejecting combination of insns %d and %d\n",
601 INSN_UID (i2
), INSN_UID (i3
));
602 fprintf (dump_file
, "original costs %d + %d = %d\n",
603 i2_cost
, i3_cost
, old_cost
);
608 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
609 new_i2_cost
, new_i3_cost
, new_cost
);
612 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
618 /* Update the uid_insn_cost array with the replacement costs. */
619 uid_insn_cost
[INSN_UID (i2
)] = new_i2_cost
;
620 uid_insn_cost
[INSN_UID (i3
)] = new_i3_cost
;
622 uid_insn_cost
[INSN_UID (i1
)] = 0;
627 /* Main entry point for combiner. F is the first insn of the function.
628 NREGS is the first unused pseudo-reg number.
630 Return nonzero if the combiner has turned an indirect jump
631 instruction into a direct jump. */
633 combine_instructions (rtx f
, unsigned int nregs
)
640 rtx links
, nextlinks
;
642 int new_direct_jump_p
= 0;
644 combine_attempts
= 0;
647 combine_successes
= 0;
649 combine_max_regno
= nregs
;
651 rtl_hooks
= combine_rtl_hooks
;
653 reg_stat
= xcalloc (nregs
, sizeof (struct reg_stat
));
655 init_recog_no_volatile ();
657 /* Compute maximum uid value so uid_cuid can be allocated. */
659 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
660 if (INSN_UID (insn
) > i
)
663 uid_cuid
= xmalloc ((i
+ 1) * sizeof (int));
666 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
668 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
669 problems when, for example, we have j <<= 1 in a loop. */
671 nonzero_sign_valid
= 0;
673 /* Compute the mapping from uids to cuids.
674 Cuids are numbers assigned to insns, like uids,
675 except that cuids increase monotonically through the code.
677 Scan all SETs and see if we can deduce anything about what
678 bits are known to be zero for some registers and how many copies
679 of the sign bit are known to exist for those registers.
681 Also set any known values so that we can use it while searching
682 for what bits are known to be set. */
686 setup_incoming_promotions ();
688 refresh_blocks
= sbitmap_alloc (last_basic_block
);
689 sbitmap_zero (refresh_blocks
);
691 /* Allocate array of current insn_rtx_costs. */
692 uid_insn_cost
= xcalloc (max_uid_cuid
+ 1, sizeof (int));
693 last_insn_cost
= max_uid_cuid
;
695 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
697 uid_cuid
[INSN_UID (insn
)] = ++i
;
703 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
705 record_dead_and_set_regs (insn
);
708 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
709 if (REG_NOTE_KIND (links
) == REG_INC
)
710 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
714 /* Record the current insn_rtx_cost of this instruction. */
715 if (NONJUMP_INSN_P (insn
))
716 uid_insn_cost
[INSN_UID (insn
)] = insn_rtx_cost (PATTERN (insn
));
718 fprintf(dump_file
, "insn_cost %d: %d\n",
719 INSN_UID (insn
), uid_insn_cost
[INSN_UID (insn
)]);
726 nonzero_sign_valid
= 1;
728 /* Now scan all the insns in forward order. */
734 setup_incoming_promotions ();
736 FOR_EACH_BB (this_basic_block
)
738 for (insn
= BB_HEAD (this_basic_block
);
739 insn
!= NEXT_INSN (BB_END (this_basic_block
));
740 insn
= next
? next
: NEXT_INSN (insn
))
747 else if (INSN_P (insn
))
749 /* See if we know about function return values before this
750 insn based upon SUBREG flags. */
751 check_promoted_subreg (insn
, PATTERN (insn
));
753 /* Try this insn with each insn it links back to. */
755 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
756 if ((next
= try_combine (insn
, XEXP (links
, 0),
757 NULL_RTX
, &new_direct_jump_p
)) != 0)
760 /* Try each sequence of three linked insns ending with this one. */
762 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
764 rtx link
= XEXP (links
, 0);
766 /* If the linked insn has been replaced by a note, then there
767 is no point in pursuing this chain any further. */
771 for (nextlinks
= LOG_LINKS (link
);
773 nextlinks
= XEXP (nextlinks
, 1))
774 if ((next
= try_combine (insn
, link
,
776 &new_direct_jump_p
)) != 0)
781 /* Try to combine a jump insn that uses CC0
782 with a preceding insn that sets CC0, and maybe with its
783 logical predecessor as well.
784 This is how we make decrement-and-branch insns.
785 We need this special code because data flow connections
786 via CC0 do not get entered in LOG_LINKS. */
789 && (prev
= prev_nonnote_insn (insn
)) != 0
790 && NONJUMP_INSN_P (prev
)
791 && sets_cc0_p (PATTERN (prev
)))
793 if ((next
= try_combine (insn
, prev
,
794 NULL_RTX
, &new_direct_jump_p
)) != 0)
797 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
798 nextlinks
= XEXP (nextlinks
, 1))
799 if ((next
= try_combine (insn
, prev
,
801 &new_direct_jump_p
)) != 0)
805 /* Do the same for an insn that explicitly references CC0. */
806 if (NONJUMP_INSN_P (insn
)
807 && (prev
= prev_nonnote_insn (insn
)) != 0
808 && NONJUMP_INSN_P (prev
)
809 && sets_cc0_p (PATTERN (prev
))
810 && GET_CODE (PATTERN (insn
)) == SET
811 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
813 if ((next
= try_combine (insn
, prev
,
814 NULL_RTX
, &new_direct_jump_p
)) != 0)
817 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
818 nextlinks
= XEXP (nextlinks
, 1))
819 if ((next
= try_combine (insn
, prev
,
821 &new_direct_jump_p
)) != 0)
825 /* Finally, see if any of the insns that this insn links to
826 explicitly references CC0. If so, try this insn, that insn,
827 and its predecessor if it sets CC0. */
828 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
829 if (NONJUMP_INSN_P (XEXP (links
, 0))
830 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
831 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
832 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
833 && NONJUMP_INSN_P (prev
)
834 && sets_cc0_p (PATTERN (prev
))
835 && (next
= try_combine (insn
, XEXP (links
, 0),
836 prev
, &new_direct_jump_p
)) != 0)
840 /* Try combining an insn with two different insns whose results it
842 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
843 for (nextlinks
= XEXP (links
, 1); nextlinks
;
844 nextlinks
= XEXP (nextlinks
, 1))
845 if ((next
= try_combine (insn
, XEXP (links
, 0),
847 &new_direct_jump_p
)) != 0)
850 /* Try this insn with each REG_EQUAL note it links back to. */
851 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
854 rtx temp
= XEXP (links
, 0);
855 if ((set
= single_set (temp
)) != 0
856 && (note
= find_reg_equal_equiv_note (temp
)) != 0
857 && GET_CODE (XEXP (note
, 0)) != EXPR_LIST
858 /* Avoid using a register that may already been marked
859 dead by an earlier instruction. */
860 && ! unmentioned_reg_p (XEXP (note
, 0), SET_SRC (set
)))
862 /* Temporarily replace the set's source with the
863 contents of the REG_EQUAL note. The insn will
864 be deleted or recognized by try_combine. */
865 rtx orig
= SET_SRC (set
);
866 SET_SRC (set
) = XEXP (note
, 0);
867 next
= try_combine (insn
, temp
, NULL_RTX
,
871 SET_SRC (set
) = orig
;
876 record_dead_and_set_regs (insn
);
885 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, i
,
886 BASIC_BLOCK (i
)->flags
|= BB_DIRTY
);
887 new_direct_jump_p
|= purge_all_dead_edges (0);
888 delete_noop_moves ();
890 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
891 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
892 | PROP_KILL_DEAD_CODE
);
895 sbitmap_free (refresh_blocks
);
896 free (uid_insn_cost
);
901 struct undo
*undo
, *next
;
902 for (undo
= undobuf
.frees
; undo
; undo
= next
)
910 total_attempts
+= combine_attempts
;
911 total_merges
+= combine_merges
;
912 total_extras
+= combine_extras
;
913 total_successes
+= combine_successes
;
915 nonzero_sign_valid
= 0;
916 rtl_hooks
= general_rtl_hooks
;
918 /* Make recognizer allow volatile MEMs again. */
921 return new_direct_jump_p
;
924 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
930 for (i
= 0; i
< combine_max_regno
; i
++)
931 memset (reg_stat
+ i
, 0, offsetof (struct reg_stat
, sign_bit_copies
));
934 /* Set up any promoted values for incoming argument registers. */
937 setup_incoming_promotions (void)
941 enum machine_mode mode
;
943 rtx first
= get_insns ();
945 if (targetm
.calls
.promote_function_args (TREE_TYPE (cfun
->decl
)))
947 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
948 /* Check whether this register can hold an incoming pointer
949 argument. FUNCTION_ARG_REGNO_P tests outgoing register
950 numbers, so translate if necessary due to register windows. */
951 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
952 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
955 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
958 gen_rtx_CLOBBER (mode
, const0_rtx
)));
963 /* Called via note_stores. If X is a pseudo that is narrower than
964 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
966 If we are setting only a portion of X and we can't figure out what
967 portion, assume all bits will be used since we don't know what will
970 Similarly, set how many bits of X are known to be copies of the sign bit
971 at all locations in the function. This is the smallest number implied
975 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
,
976 void *data ATTRIBUTE_UNUSED
)
981 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
982 /* If this register is undefined at the start of the file, we can't
983 say what its contents were. */
984 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, REGNO (x
))
985 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
987 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
989 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
990 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
994 /* If this is a complex assignment, see if we can convert it into a
995 simple assignment. */
996 set
= expand_field_assignment (set
);
998 /* If this is a simple assignment, or we have a paradoxical SUBREG,
999 set what we know about X. */
1001 if (SET_DEST (set
) == x
1002 || (GET_CODE (SET_DEST (set
)) == SUBREG
1003 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
1004 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
1005 && SUBREG_REG (SET_DEST (set
)) == x
))
1007 rtx src
= SET_SRC (set
);
1009 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1010 /* If X is narrower than a word and SRC is a non-negative
1011 constant that would appear negative in the mode of X,
1012 sign-extend it for use in reg_stat[].nonzero_bits because some
1013 machines (maybe most) will actually do the sign-extension
1014 and this is the conservative approach.
1016 ??? For 2.5, try to tighten up the MD files in this regard
1017 instead of this kludge. */
1019 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
1020 && GET_CODE (src
) == CONST_INT
1022 && 0 != (INTVAL (src
)
1023 & ((HOST_WIDE_INT
) 1
1024 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
1025 src
= GEN_INT (INTVAL (src
)
1026 | ((HOST_WIDE_INT
) (-1)
1027 << GET_MODE_BITSIZE (GET_MODE (x
))));
1030 /* Don't call nonzero_bits if it cannot change anything. */
1031 if (reg_stat
[REGNO (x
)].nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1032 reg_stat
[REGNO (x
)].nonzero_bits
1033 |= nonzero_bits (src
, nonzero_bits_mode
);
1034 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1035 if (reg_stat
[REGNO (x
)].sign_bit_copies
== 0
1036 || reg_stat
[REGNO (x
)].sign_bit_copies
> num
)
1037 reg_stat
[REGNO (x
)].sign_bit_copies
= num
;
1041 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1042 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
1047 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1048 insns that were previously combined into I3 or that will be combined
1049 into the merger of INSN and I3.
1051 Return 0 if the combination is not allowed for any reason.
1053 If the combination is allowed, *PDEST will be set to the single
1054 destination of INSN and *PSRC to the single source, and this function
1058 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
1059 rtx
*pdest
, rtx
*psrc
)
1062 rtx set
= 0, src
, dest
;
1067 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
1068 && next_active_insn (succ
) == i3
)
1069 : next_active_insn (insn
) == i3
);
1071 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1072 or a PARALLEL consisting of such a SET and CLOBBERs.
1074 If INSN has CLOBBER parallel parts, ignore them for our processing.
1075 By definition, these happen during the execution of the insn. When it
1076 is merged with another insn, all bets are off. If they are, in fact,
1077 needed and aren't also supplied in I3, they may be added by
1078 recog_for_combine. Otherwise, it won't match.
1080 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1083 Get the source and destination of INSN. If more than one, can't
1086 if (GET_CODE (PATTERN (insn
)) == SET
)
1087 set
= PATTERN (insn
);
1088 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1089 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1091 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1093 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1096 switch (GET_CODE (elt
))
1098 /* This is important to combine floating point insns
1099 for the SH4 port. */
1101 /* Combining an isolated USE doesn't make sense.
1102 We depend here on combinable_i3pat to reject them. */
1103 /* The code below this loop only verifies that the inputs of
1104 the SET in INSN do not change. We call reg_set_between_p
1105 to verify that the REG in the USE does not change between
1107 If the USE in INSN was for a pseudo register, the matching
1108 insn pattern will likely match any register; combining this
1109 with any other USE would only be safe if we knew that the
1110 used registers have identical values, or if there was
1111 something to tell them apart, e.g. different modes. For
1112 now, we forgo such complicated tests and simply disallow
1113 combining of USES of pseudo registers with any other USE. */
1114 if (REG_P (XEXP (elt
, 0))
1115 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1117 rtx i3pat
= PATTERN (i3
);
1118 int i
= XVECLEN (i3pat
, 0) - 1;
1119 unsigned int regno
= REGNO (XEXP (elt
, 0));
1123 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1125 if (GET_CODE (i3elt
) == USE
1126 && REG_P (XEXP (i3elt
, 0))
1127 && (REGNO (XEXP (i3elt
, 0)) == regno
1128 ? reg_set_between_p (XEXP (elt
, 0),
1129 PREV_INSN (insn
), i3
)
1130 : regno
>= FIRST_PSEUDO_REGISTER
))
1137 /* We can ignore CLOBBERs. */
1142 /* Ignore SETs whose result isn't used but not those that
1143 have side-effects. */
1144 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1145 && (!(note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
))
1146 || INTVAL (XEXP (note
, 0)) <= 0)
1147 && ! side_effects_p (elt
))
1150 /* If we have already found a SET, this is a second one and
1151 so we cannot combine with this insn. */
1159 /* Anything else means we can't combine. */
1165 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1166 so don't do anything with it. */
1167 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1176 set
= expand_field_assignment (set
);
1177 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1179 /* Don't eliminate a store in the stack pointer. */
1180 if (dest
== stack_pointer_rtx
1181 /* Don't combine with an insn that sets a register to itself if it has
1182 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1183 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1184 /* Can't merge an ASM_OPERANDS. */
1185 || GET_CODE (src
) == ASM_OPERANDS
1186 /* Can't merge a function call. */
1187 || GET_CODE (src
) == CALL
1188 /* Don't eliminate a function call argument. */
1190 && (find_reg_fusage (i3
, USE
, dest
)
1192 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1193 && global_regs
[REGNO (dest
)])))
1194 /* Don't substitute into an incremented register. */
1195 || FIND_REG_INC_NOTE (i3
, dest
)
1196 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1197 /* Don't substitute into a non-local goto, this confuses CFG. */
1198 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1200 /* Don't combine the end of a libcall into anything. */
1201 /* ??? This gives worse code, and appears to be unnecessary, since no
1202 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1203 use REG_RETVAL notes for noconflict blocks, but other code here
1204 makes sure that those insns don't disappear. */
1205 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1207 /* Make sure that DEST is not used after SUCC but before I3. */
1208 || (succ
&& ! all_adjacent
1209 && reg_used_between_p (dest
, succ
, i3
))
1210 /* Make sure that the value that is to be substituted for the register
1211 does not use any registers whose values alter in between. However,
1212 If the insns are adjacent, a use can't cross a set even though we
1213 think it might (this can happen for a sequence of insns each setting
1214 the same destination; last_set of that register might point to
1215 a NOTE). If INSN has a REG_EQUIV note, the register is always
1216 equivalent to the memory so the substitution is valid even if there
1217 are intervening stores. Also, don't move a volatile asm or
1218 UNSPEC_VOLATILE across any other insns. */
1221 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1222 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1223 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1224 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1225 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1226 better register allocation by not doing the combine. */
1227 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1228 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1229 /* Don't combine across a CALL_INSN, because that would possibly
1230 change whether the life span of some REGs crosses calls or not,
1231 and it is a pain to update that information.
1232 Exception: if source is a constant, moving it later can't hurt.
1233 Accept that special case, because it helps -fforce-addr a lot. */
1234 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1237 /* DEST must either be a REG or CC0. */
1240 /* If register alignment is being enforced for multi-word items in all
1241 cases except for parameters, it is possible to have a register copy
1242 insn referencing a hard register that is not allowed to contain the
1243 mode being copied and which would not be valid as an operand of most
1244 insns. Eliminate this problem by not combining with such an insn.
1246 Also, on some machines we don't want to extend the life of a hard
1250 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1251 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1252 /* Don't extend the life of a hard register unless it is
1253 user variable (if we have few registers) or it can't
1254 fit into the desired register (meaning something special
1256 Also avoid substituting a return register into I3, because
1257 reload can't handle a conflict with constraints of other
1259 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1260 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1263 else if (GET_CODE (dest
) != CC0
)
1267 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1268 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1269 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1271 /* Don't substitute for a register intended as a clobberable
1273 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1274 if (rtx_equal_p (reg
, dest
))
1277 /* If the clobber represents an earlyclobber operand, we must not
1278 substitute an expression containing the clobbered register.
1279 As we do not analyze the constraint strings here, we have to
1280 make the conservative assumption. However, if the register is
1281 a fixed hard reg, the clobber cannot represent any operand;
1282 we leave it up to the machine description to either accept or
1283 reject use-and-clobber patterns. */
1285 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1286 || !fixed_regs
[REGNO (reg
)])
1287 if (reg_overlap_mentioned_p (reg
, src
))
1291 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1292 or not), reject, unless nothing volatile comes between it and I3 */
1294 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1296 /* Make sure succ doesn't contain a volatile reference. */
1297 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1300 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1301 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1305 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1306 to be an explicit register variable, and was chosen for a reason. */
1308 if (GET_CODE (src
) == ASM_OPERANDS
1309 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1312 /* If there are any volatile insns between INSN and I3, reject, because
1313 they might affect machine state. */
1315 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1316 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1319 /* If INSN or I2 contains an autoincrement or autodecrement,
1320 make sure that register is not used between there and I3,
1321 and not already used in I3 either.
1322 Also insist that I3 not be a jump; if it were one
1323 and the incremented register were spilled, we would lose. */
1326 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1327 if (REG_NOTE_KIND (link
) == REG_INC
1329 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1330 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1335 /* Don't combine an insn that follows a CC0-setting insn.
1336 An insn that uses CC0 must not be separated from the one that sets it.
1337 We do, however, allow I2 to follow a CC0-setting insn if that insn
1338 is passed as I1; in that case it will be deleted also.
1339 We also allow combining in this case if all the insns are adjacent
1340 because that would leave the two CC0 insns adjacent as well.
1341 It would be more logical to test whether CC0 occurs inside I1 or I2,
1342 but that would be much slower, and this ought to be equivalent. */
1344 p
= prev_nonnote_insn (insn
);
1345 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
1350 /* If we get here, we have passed all the tests and the combination is
1359 /* LOC is the location within I3 that contains its pattern or the component
1360 of a PARALLEL of the pattern. We validate that it is valid for combining.
1362 One problem is if I3 modifies its output, as opposed to replacing it
1363 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1364 so would produce an insn that is not equivalent to the original insns.
1368 (set (reg:DI 101) (reg:DI 100))
1369 (set (subreg:SI (reg:DI 101) 0) <foo>)
1371 This is NOT equivalent to:
1373 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1374 (set (reg:DI 101) (reg:DI 100))])
1376 Not only does this modify 100 (in which case it might still be valid
1377 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1379 We can also run into a problem if I2 sets a register that I1
1380 uses and I1 gets directly substituted into I3 (not via I2). In that
1381 case, we would be getting the wrong value of I2DEST into I3, so we
1382 must reject the combination. This case occurs when I2 and I1 both
1383 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1384 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1385 of a SET must prevent combination from occurring.
1387 Before doing the above check, we first try to expand a field assignment
1388 into a set of logical operations.
1390 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1391 we place a register that is both set and used within I3. If more than one
1392 such register is detected, we fail.
1394 Return 1 if the combination is valid, zero otherwise. */
1397 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1398 int i1_not_in_src
, rtx
*pi3dest_killed
)
1402 if (GET_CODE (x
) == SET
)
1405 rtx dest
= SET_DEST (set
);
1406 rtx src
= SET_SRC (set
);
1407 rtx inner_dest
= dest
;
1409 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1410 || GET_CODE (inner_dest
) == SUBREG
1411 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1412 inner_dest
= XEXP (inner_dest
, 0);
1414 /* Check for the case where I3 modifies its output, as discussed
1415 above. We don't want to prevent pseudos from being combined
1416 into the address of a MEM, so only prevent the combination if
1417 i1 or i2 set the same MEM. */
1418 if ((inner_dest
!= dest
&&
1419 (!MEM_P (inner_dest
)
1420 || rtx_equal_p (i2dest
, inner_dest
)
1421 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1422 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1423 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1425 /* This is the same test done in can_combine_p except we can't test
1426 all_adjacent; we don't have to, since this instruction will stay
1427 in place, thus we are not considering increasing the lifetime of
1430 Also, if this insn sets a function argument, combining it with
1431 something that might need a spill could clobber a previous
1432 function argument; the all_adjacent test in can_combine_p also
1433 checks this; here, we do a more specific test for this case. */
1435 || (REG_P (inner_dest
)
1436 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1437 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1438 GET_MODE (inner_dest
))))
1439 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1442 /* If DEST is used in I3, it is being killed in this insn,
1443 so record that for later.
1444 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1445 STACK_POINTER_REGNUM, since these are always considered to be
1446 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1447 if (pi3dest_killed
&& REG_P (dest
)
1448 && reg_referenced_p (dest
, PATTERN (i3
))
1449 && REGNO (dest
) != FRAME_POINTER_REGNUM
1450 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1451 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1453 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1454 && (REGNO (dest
) != ARG_POINTER_REGNUM
1455 || ! fixed_regs
[REGNO (dest
)])
1457 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1459 if (*pi3dest_killed
)
1462 *pi3dest_killed
= dest
;
1466 else if (GET_CODE (x
) == PARALLEL
)
1470 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1471 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1472 i1_not_in_src
, pi3dest_killed
))
1479 /* Return 1 if X is an arithmetic expression that contains a multiplication
1480 and division. We don't count multiplications by powers of two here. */
1483 contains_muldiv (rtx x
)
1485 switch (GET_CODE (x
))
1487 case MOD
: case DIV
: case UMOD
: case UDIV
:
1491 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1492 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1495 return contains_muldiv (XEXP (x
, 0))
1496 || contains_muldiv (XEXP (x
, 1));
1499 return contains_muldiv (XEXP (x
, 0));
1505 /* Determine whether INSN can be used in a combination. Return nonzero if
1506 not. This is used in try_combine to detect early some cases where we
1507 can't perform combinations. */
1510 cant_combine_insn_p (rtx insn
)
1515 /* If this isn't really an insn, we can't do anything.
1516 This can occur when flow deletes an insn that it has merged into an
1517 auto-increment address. */
1518 if (! INSN_P (insn
))
1521 /* Never combine loads and stores involving hard regs that are likely
1522 to be spilled. The register allocator can usually handle such
1523 reg-reg moves by tying. If we allow the combiner to make
1524 substitutions of likely-spilled regs, we may abort in reload.
1525 As an exception, we allow combinations involving fixed regs; these are
1526 not available to the register allocator so there's no risk involved. */
1528 set
= single_set (insn
);
1531 src
= SET_SRC (set
);
1532 dest
= SET_DEST (set
);
1533 if (GET_CODE (src
) == SUBREG
)
1534 src
= SUBREG_REG (src
);
1535 if (GET_CODE (dest
) == SUBREG
)
1536 dest
= SUBREG_REG (dest
);
1537 if (REG_P (src
) && REG_P (dest
)
1538 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1539 && ! fixed_regs
[REGNO (src
)]
1540 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1541 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1542 && ! fixed_regs
[REGNO (dest
)]
1543 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1549 /* Adjust INSN after we made a change to its destination.
1551 Changing the destination can invalidate notes that say something about
1552 the results of the insn and a LOG_LINK pointing to the insn. */
1555 adjust_for_new_dest (rtx insn
)
1559 /* For notes, be conservative and simply remove them. */
1560 loc
= ®_NOTES (insn
);
1563 enum reg_note kind
= REG_NOTE_KIND (*loc
);
1564 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
1565 *loc
= XEXP (*loc
, 1);
1567 loc
= &XEXP (*loc
, 1);
1570 /* The new insn will have a destination that was previously the destination
1571 of an insn just above it. Call distribute_links to make a LOG_LINK from
1572 the next use of that destination. */
1573 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
1576 /* Try to combine the insns I1 and I2 into I3.
1577 Here I1 and I2 appear earlier than I3.
1578 I1 can be zero; then we combine just I2 into I3.
1580 If we are combining three insns and the resulting insn is not recognized,
1581 try splitting it into two insns. If that happens, I2 and I3 are retained
1582 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1585 Return 0 if the combination does not work. Then nothing is changed.
1586 If we did the combination, return the insn at which combine should
1589 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1590 new direct jump instruction. */
1593 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
1595 /* New patterns for I3 and I2, respectively. */
1596 rtx newpat
, newi2pat
= 0;
1597 int substed_i2
= 0, substed_i1
= 0;
1598 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1599 int added_sets_1
, added_sets_2
;
1600 /* Total number of SETs to put into I3. */
1602 /* Nonzero if I2's body now appears in I3. */
1604 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1605 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1606 /* Contains I3 if the destination of I3 is used in its source, which means
1607 that the old life of I3 is being killed. If that usage is placed into
1608 I2 and not in I3, a REG_DEAD note must be made. */
1609 rtx i3dest_killed
= 0;
1610 /* SET_DEST and SET_SRC of I2 and I1. */
1611 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1612 /* PATTERN (I2), or a copy of it in certain cases. */
1614 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1615 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1616 int i1_feeds_i3
= 0;
1617 /* Notes that must be added to REG_NOTES in I3 and I2. */
1618 rtx new_i3_notes
, new_i2_notes
;
1619 /* Notes that we substituted I3 into I2 instead of the normal case. */
1620 int i3_subst_into_i2
= 0;
1621 /* Notes that I1, I2 or I3 is a MULT operation. */
1630 /* Exit early if one of the insns involved can't be used for
1632 if (cant_combine_insn_p (i3
)
1633 || cant_combine_insn_p (i2
)
1634 || (i1
&& cant_combine_insn_p (i1
))
1635 /* We also can't do anything if I3 has a
1636 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1639 /* ??? This gives worse code, and appears to be unnecessary, since no
1640 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1641 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1647 undobuf
.other_insn
= 0;
1649 /* Reset the hard register usage information. */
1650 CLEAR_HARD_REG_SET (newpat_used_regs
);
1652 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1653 code below, set I1 to be the earlier of the two insns. */
1654 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1655 temp
= i1
, i1
= i2
, i2
= temp
;
1657 added_links_insn
= 0;
1659 /* First check for one important special-case that the code below will
1660 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1661 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1662 we may be able to replace that destination with the destination of I3.
1663 This occurs in the common code where we compute both a quotient and
1664 remainder into a structure, in which case we want to do the computation
1665 directly into the structure to avoid register-register copies.
1667 Note that this case handles both multiple sets in I2 and also
1668 cases where I2 has a number of CLOBBER or PARALLELs.
1670 We make very conservative checks below and only try to handle the
1671 most common cases of this. For example, we only handle the case
1672 where I2 and I3 are adjacent to avoid making difficult register
1675 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
1676 && REG_P (SET_SRC (PATTERN (i3
)))
1677 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1678 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1679 && GET_CODE (PATTERN (i2
)) == PARALLEL
1680 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1681 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1682 below would need to check what is inside (and reg_overlap_mentioned_p
1683 doesn't support those codes anyway). Don't allow those destinations;
1684 the resulting insn isn't likely to be recognized anyway. */
1685 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1686 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1687 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1688 SET_DEST (PATTERN (i3
)))
1689 && next_real_insn (i2
) == i3
)
1691 rtx p2
= PATTERN (i2
);
1693 /* Make sure that the destination of I3,
1694 which we are going to substitute into one output of I2,
1695 is not used within another output of I2. We must avoid making this:
1696 (parallel [(set (mem (reg 69)) ...)
1697 (set (reg 69) ...)])
1698 which is not well-defined as to order of actions.
1699 (Besides, reload can't handle output reloads for this.)
1701 The problem can also happen if the dest of I3 is a memory ref,
1702 if another dest in I2 is an indirect memory ref. */
1703 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1704 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1705 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1706 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1707 SET_DEST (XVECEXP (p2
, 0, i
))))
1710 if (i
== XVECLEN (p2
, 0))
1711 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1712 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1713 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1714 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1719 subst_low_cuid
= INSN_CUID (i2
);
1721 added_sets_2
= added_sets_1
= 0;
1722 i2dest
= SET_SRC (PATTERN (i3
));
1724 /* Replace the dest in I2 with our dest and make the resulting
1725 insn the new pattern for I3. Then skip to where we
1726 validate the pattern. Everything was set up above. */
1727 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1728 SET_DEST (PATTERN (i3
)));
1731 i3_subst_into_i2
= 1;
1732 goto validate_replacement
;
1736 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1737 one of those words to another constant, merge them by making a new
1740 && (temp
= single_set (i2
)) != 0
1741 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1742 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1743 && REG_P (SET_DEST (temp
))
1744 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1745 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1746 && GET_CODE (PATTERN (i3
)) == SET
1747 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1748 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1749 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1750 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1751 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1753 HOST_WIDE_INT lo
, hi
;
1755 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1756 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1759 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1760 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1763 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1765 /* We don't handle the case of the target word being wider
1766 than a host wide int. */
1767 gcc_assert (HOST_BITS_PER_WIDE_INT
>= BITS_PER_WORD
);
1769 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1770 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1771 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1773 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1774 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1775 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1777 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1778 >> (HOST_BITS_PER_WIDE_INT
- 1));
1780 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1781 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1782 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1783 (INTVAL (SET_SRC (PATTERN (i3
)))));
1785 hi
= lo
< 0 ? -1 : 0;
1788 /* We don't handle the case of the higher word not fitting
1789 entirely in either hi or lo. */
1794 subst_low_cuid
= INSN_CUID (i2
);
1795 added_sets_2
= added_sets_1
= 0;
1796 i2dest
= SET_DEST (temp
);
1798 SUBST (SET_SRC (temp
),
1799 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1801 newpat
= PATTERN (i2
);
1802 goto validate_replacement
;
1806 /* If we have no I1 and I2 looks like:
1807 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1809 make up a dummy I1 that is
1812 (set (reg:CC X) (compare:CC Y (const_int 0)))
1814 (We can ignore any trailing CLOBBERs.)
1816 This undoes a previous combination and allows us to match a branch-and-
1819 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1820 && XVECLEN (PATTERN (i2
), 0) >= 2
1821 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1822 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1824 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1825 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1826 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1827 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
1828 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1829 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1831 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1832 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1837 /* We make I1 with the same INSN_UID as I2. This gives it
1838 the same INSN_CUID for value tracking. Our fake I1 will
1839 never appear in the insn stream so giving it the same INSN_UID
1840 as I2 will not cause a problem. */
1842 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1843 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
1844 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1847 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1848 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1849 SET_DEST (PATTERN (i1
)));
1854 /* Verify that I2 and I1 are valid for combining. */
1855 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1856 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1862 /* Record whether I2DEST is used in I2SRC and similarly for the other
1863 cases. Knowing this will help in register status updating below. */
1864 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1865 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1866 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1868 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1870 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1872 /* Ensure that I3's pattern can be the destination of combines. */
1873 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1874 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1881 /* See if any of the insns is a MULT operation. Unless one is, we will
1882 reject a combination that is, since it must be slower. Be conservative
1884 if (GET_CODE (i2src
) == MULT
1885 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1886 || (GET_CODE (PATTERN (i3
)) == SET
1887 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1890 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1891 We used to do this EXCEPT in one case: I3 has a post-inc in an
1892 output operand. However, that exception can give rise to insns like
1894 which is a famous insn on the PDP-11 where the value of r3 used as the
1895 source was model-dependent. Avoid this sort of thing. */
1898 if (!(GET_CODE (PATTERN (i3
)) == SET
1899 && REG_P (SET_SRC (PATTERN (i3
)))
1900 && MEM_P (SET_DEST (PATTERN (i3
)))
1901 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1902 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1903 /* It's not the exception. */
1906 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1907 if (REG_NOTE_KIND (link
) == REG_INC
1908 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1910 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1917 /* See if the SETs in I1 or I2 need to be kept around in the merged
1918 instruction: whenever the value set there is still needed past I3.
1919 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1921 For the SET in I1, we have two cases: If I1 and I2 independently
1922 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1923 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1924 in I1 needs to be kept around unless I1DEST dies or is set in either
1925 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1926 I1DEST. If so, we know I1 feeds into I2. */
1928 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1931 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1932 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1934 /* If the set in I2 needs to be kept around, we must make a copy of
1935 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1936 PATTERN (I2), we are only substituting for the original I1DEST, not into
1937 an already-substituted copy. This also prevents making self-referential
1938 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1941 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1942 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1946 i2pat
= copy_rtx (i2pat
);
1950 /* Substitute in the latest insn for the regs set by the earlier ones. */
1952 maxreg
= max_reg_num ();
1956 /* It is possible that the source of I2 or I1 may be performing an
1957 unneeded operation, such as a ZERO_EXTEND of something that is known
1958 to have the high part zero. Handle that case by letting subst look at
1959 the innermost one of them.
1961 Another way to do this would be to have a function that tries to
1962 simplify a single insn instead of merging two or more insns. We don't
1963 do this because of the potential of infinite loops and because
1964 of the potential extra memory required. However, doing it the way
1965 we are is a bit of a kludge and doesn't catch all cases.
1967 But only do this if -fexpensive-optimizations since it slows things down
1968 and doesn't usually win. */
1970 if (flag_expensive_optimizations
)
1972 /* Pass pc_rtx so no substitutions are done, just simplifications. */
1975 subst_low_cuid
= INSN_CUID (i1
);
1976 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1980 subst_low_cuid
= INSN_CUID (i2
);
1981 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1986 /* Many machines that don't use CC0 have insns that can both perform an
1987 arithmetic operation and set the condition code. These operations will
1988 be represented as a PARALLEL with the first element of the vector
1989 being a COMPARE of an arithmetic operation with the constant zero.
1990 The second element of the vector will set some pseudo to the result
1991 of the same arithmetic operation. If we simplify the COMPARE, we won't
1992 match such a pattern and so will generate an extra insn. Here we test
1993 for this case, where both the comparison and the operation result are
1994 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1995 I2SRC. Later we will make the PARALLEL that contains I2. */
1997 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1998 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1999 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
2000 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2002 #ifdef SELECT_CC_MODE
2004 enum machine_mode compare_mode
;
2007 newpat
= PATTERN (i3
);
2008 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
2012 #ifdef SELECT_CC_MODE
2013 /* See if a COMPARE with the operand we substituted in should be done
2014 with the mode that is currently being used. If not, do the same
2015 processing we do in `subst' for a SET; namely, if the destination
2016 is used only once, try to replace it with a register of the proper
2017 mode and also replace the COMPARE. */
2018 if (undobuf
.other_insn
== 0
2019 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
2020 &undobuf
.other_insn
))
2021 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
2023 != GET_MODE (SET_DEST (newpat
))))
2025 unsigned int regno
= REGNO (SET_DEST (newpat
));
2026 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
2028 if (regno
< FIRST_PSEUDO_REGISTER
2029 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
2030 && ! REG_USERVAR_P (SET_DEST (newpat
))))
2032 if (regno
>= FIRST_PSEUDO_REGISTER
)
2033 SUBST (regno_reg_rtx
[regno
], new_dest
);
2035 SUBST (SET_DEST (newpat
), new_dest
);
2036 SUBST (XEXP (*cc_use
, 0), new_dest
);
2037 SUBST (SET_SRC (newpat
),
2038 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
2041 undobuf
.other_insn
= 0;
2048 n_occurrences
= 0; /* `subst' counts here */
2050 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2051 need to make a unique copy of I2SRC each time we substitute it
2052 to avoid self-referential rtl. */
2054 subst_low_cuid
= INSN_CUID (i2
);
2055 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
2056 ! i1_feeds_i3
&& i1dest_in_i1src
);
2059 /* Record whether i2's body now appears within i3's body. */
2060 i2_is_used
= n_occurrences
;
2063 /* If we already got a failure, don't try to do more. Otherwise,
2064 try to substitute in I1 if we have it. */
2066 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
2068 /* Before we can do this substitution, we must redo the test done
2069 above (see detailed comments there) that ensures that I1DEST
2070 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2072 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
2080 subst_low_cuid
= INSN_CUID (i1
);
2081 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
2085 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2086 to count all the ways that I2SRC and I1SRC can be used. */
2087 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
2088 && i2_is_used
+ added_sets_2
> 1)
2089 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
2090 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
2092 /* Fail if we tried to make a new register (we used to abort, but there's
2093 really no reason to). */
2094 || max_reg_num () != maxreg
2095 /* Fail if we couldn't do something and have a CLOBBER. */
2096 || GET_CODE (newpat
) == CLOBBER
2097 /* Fail if this new pattern is a MULT and we didn't have one before
2098 at the outer level. */
2099 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
2106 /* If the actions of the earlier insns must be kept
2107 in addition to substituting them into the latest one,
2108 we must make a new PARALLEL for the latest insn
2109 to hold additional the SETs. */
2111 if (added_sets_1
|| added_sets_2
)
2115 if (GET_CODE (newpat
) == PARALLEL
)
2117 rtvec old
= XVEC (newpat
, 0);
2118 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2119 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2120 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2121 sizeof (old
->elem
[0]) * old
->num_elem
);
2126 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2127 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2128 XVECEXP (newpat
, 0, 0) = old
;
2132 XVECEXP (newpat
, 0, --total_sets
)
2133 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2134 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2138 /* If there is no I1, use I2's body as is. We used to also not do
2139 the subst call below if I2 was substituted into I3,
2140 but that could lose a simplification. */
2142 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2144 /* See comment where i2pat is assigned. */
2145 XVECEXP (newpat
, 0, --total_sets
)
2146 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2150 /* We come here when we are replacing a destination in I2 with the
2151 destination of I3. */
2152 validate_replacement
:
2154 /* Note which hard regs this insn has as inputs. */
2155 mark_used_regs_combine (newpat
);
2157 /* Is the result of combination a valid instruction? */
2158 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2160 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2161 the second SET's destination is a register that is unused and isn't
2162 marked as an instruction that might trap in an EH region. In that case,
2163 we just need the first SET. This can occur when simplifying a divmod
2164 insn. We *must* test for this case here because the code below that
2165 splits two independent SETs doesn't handle this case correctly when it
2166 updates the register status.
2168 It's pointless doing this if we originally had two sets, one from
2169 i3, and one from i2. Combining then splitting the parallel results
2170 in the original i2 again plus an invalid insn (which we delete).
2171 The net effect is only to move instructions around, which makes
2172 debug info less accurate.
2174 Also check the case where the first SET's destination is unused.
2175 That would not cause incorrect code, but does cause an unneeded
2178 if (insn_code_number
< 0
2179 && !(added_sets_2
&& i1
== 0)
2180 && GET_CODE (newpat
) == PARALLEL
2181 && XVECLEN (newpat
, 0) == 2
2182 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2183 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2184 && asm_noperands (newpat
) < 0)
2186 rtx set0
= XVECEXP (newpat
, 0, 0);
2187 rtx set1
= XVECEXP (newpat
, 0, 1);
2190 if (((REG_P (SET_DEST (set1
))
2191 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
2192 || (GET_CODE (SET_DEST (set1
)) == SUBREG
2193 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
2194 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2195 || INTVAL (XEXP (note
, 0)) <= 0)
2196 && ! side_effects_p (SET_SRC (set1
)))
2199 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2202 else if (((REG_P (SET_DEST (set0
))
2203 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
2204 || (GET_CODE (SET_DEST (set0
)) == SUBREG
2205 && find_reg_note (i3
, REG_UNUSED
,
2206 SUBREG_REG (SET_DEST (set0
)))))
2207 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2208 || INTVAL (XEXP (note
, 0)) <= 0)
2209 && ! side_effects_p (SET_SRC (set0
)))
2212 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2214 if (insn_code_number
>= 0)
2216 /* If we will be able to accept this, we have made a
2217 change to the destination of I3. This requires us to
2218 do a few adjustments. */
2220 PATTERN (i3
) = newpat
;
2221 adjust_for_new_dest (i3
);
2226 /* If we were combining three insns and the result is a simple SET
2227 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2228 insns. There are two ways to do this. It can be split using a
2229 machine-specific method (like when you have an addition of a large
2230 constant) or by combine in the function find_split_point. */
2232 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2233 && asm_noperands (newpat
) < 0)
2235 rtx m_split
, *split
;
2236 rtx ni2dest
= i2dest
;
2238 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2239 use I2DEST as a scratch register will help. In the latter case,
2240 convert I2DEST to the mode of the source of NEWPAT if we can. */
2242 m_split
= split_insns (newpat
, i3
);
2244 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2245 inputs of NEWPAT. */
2247 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2248 possible to try that as a scratch reg. This would require adding
2249 more code to make it work though. */
2251 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2253 /* If I2DEST is a hard register or the only use of a pseudo,
2254 we can change its mode. */
2255 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2256 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2258 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2259 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2260 && ! REG_USERVAR_P (i2dest
))))
2261 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2264 m_split
= split_insns (gen_rtx_PARALLEL
2266 gen_rtvec (2, newpat
,
2267 gen_rtx_CLOBBER (VOIDmode
,
2270 /* If the split with the mode-changed register didn't work, try
2271 the original register. */
2272 if (! m_split
&& ni2dest
!= i2dest
)
2275 m_split
= split_insns (gen_rtx_PARALLEL
2277 gen_rtvec (2, newpat
,
2278 gen_rtx_CLOBBER (VOIDmode
,
2284 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2286 m_split
= PATTERN (m_split
);
2287 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2288 if (insn_code_number
>= 0)
2291 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2292 && (next_real_insn (i2
) == i3
2293 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2296 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2297 newi2pat
= PATTERN (m_split
);
2299 i3set
= single_set (NEXT_INSN (m_split
));
2300 i2set
= single_set (m_split
);
2302 /* In case we changed the mode of I2DEST, replace it in the
2303 pseudo-register table here. We can't do it above in case this
2304 code doesn't get executed and we do a split the other way. */
2306 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2307 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2309 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2311 /* If I2 or I3 has multiple SETs, we won't know how to track
2312 register status, so don't use these insns. If I2's destination
2313 is used between I2 and I3, we also can't use these insns. */
2315 if (i2_code_number
>= 0 && i2set
&& i3set
2316 && (next_real_insn (i2
) == i3
2317 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2318 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2320 if (insn_code_number
>= 0)
2323 /* It is possible that both insns now set the destination of I3.
2324 If so, we must show an extra use of it. */
2326 if (insn_code_number
>= 0)
2328 rtx new_i3_dest
= SET_DEST (i3set
);
2329 rtx new_i2_dest
= SET_DEST (i2set
);
2331 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2332 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2333 || GET_CODE (new_i3_dest
) == SUBREG
)
2334 new_i3_dest
= XEXP (new_i3_dest
, 0);
2336 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2337 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2338 || GET_CODE (new_i2_dest
) == SUBREG
)
2339 new_i2_dest
= XEXP (new_i2_dest
, 0);
2341 if (REG_P (new_i3_dest
)
2342 && REG_P (new_i2_dest
)
2343 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2344 REG_N_SETS (REGNO (new_i2_dest
))++;
2348 /* If we can split it and use I2DEST, go ahead and see if that
2349 helps things be recognized. Verify that none of the registers
2350 are set between I2 and I3. */
2351 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2355 /* We need I2DEST in the proper mode. If it is a hard register
2356 or the only use of a pseudo, we can change its mode. */
2357 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2358 || GET_MODE (*split
) == VOIDmode
2359 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2360 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2361 && ! REG_USERVAR_P (i2dest
)))
2362 && (next_real_insn (i2
) == i3
2363 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2364 /* We can't overwrite I2DEST if its value is still used by
2366 && ! reg_referenced_p (i2dest
, newpat
))
2368 rtx newdest
= i2dest
;
2369 enum rtx_code split_code
= GET_CODE (*split
);
2370 enum machine_mode split_mode
= GET_MODE (*split
);
2372 /* Get NEWDEST as a register in the proper mode. We have already
2373 validated that we can do this. */
2374 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2376 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2378 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2379 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2382 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2383 an ASHIFT. This can occur if it was inside a PLUS and hence
2384 appeared to be a memory address. This is a kludge. */
2385 if (split_code
== MULT
2386 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2387 && INTVAL (XEXP (*split
, 1)) > 0
2388 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2390 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2391 XEXP (*split
, 0), GEN_INT (i
)));
2392 /* Update split_code because we may not have a multiply
2394 split_code
= GET_CODE (*split
);
2397 #ifdef INSN_SCHEDULING
2398 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2399 be written as a ZERO_EXTEND. */
2400 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
2402 #ifdef LOAD_EXTEND_OP
2403 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2404 what it really is. */
2405 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2407 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2408 SUBREG_REG (*split
)));
2411 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2412 SUBREG_REG (*split
)));
2416 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2417 SUBST (*split
, newdest
);
2418 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2420 /* recog_for_combine might have added CLOBBERs to newi2pat.
2421 Make sure NEWPAT does not depend on the clobbered regs. */
2422 if (GET_CODE (newi2pat
) == PARALLEL
)
2423 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
2424 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
2426 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
2427 if (reg_overlap_mentioned_p (reg
, newpat
))
2434 /* If the split point was a MULT and we didn't have one before,
2435 don't use one now. */
2436 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2437 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2441 /* Check for a case where we loaded from memory in a narrow mode and
2442 then sign extended it, but we need both registers. In that case,
2443 we have a PARALLEL with both loads from the same memory location.
2444 We can split this into a load from memory followed by a register-register
2445 copy. This saves at least one insn, more if register allocation can
2448 We cannot do this if the destination of the first assignment is a
2449 condition code register or cc0. We eliminate this case by making sure
2450 the SET_DEST and SET_SRC have the same mode.
2452 We cannot do this if the destination of the second assignment is
2453 a register that we have already assumed is zero-extended. Similarly
2454 for a SUBREG of such a register. */
2456 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2457 && GET_CODE (newpat
) == PARALLEL
2458 && XVECLEN (newpat
, 0) == 2
2459 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2460 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2461 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2462 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2463 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2464 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2465 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2466 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2468 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2469 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2470 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2472 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
2473 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2474 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2475 && (reg_stat
[REGNO (temp
)].nonzero_bits
2476 != GET_MODE_MASK (word_mode
))))
2477 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2478 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2480 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
2481 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2482 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2483 && (reg_stat
[REGNO (temp
)].nonzero_bits
2484 != GET_MODE_MASK (word_mode
)))))
2485 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2486 SET_SRC (XVECEXP (newpat
, 0, 1)))
2487 && ! find_reg_note (i3
, REG_UNUSED
,
2488 SET_DEST (XVECEXP (newpat
, 0, 0))))
2492 newi2pat
= XVECEXP (newpat
, 0, 0);
2493 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2494 newpat
= XVECEXP (newpat
, 0, 1);
2495 SUBST (SET_SRC (newpat
),
2496 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2497 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2499 if (i2_code_number
>= 0)
2500 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2502 if (insn_code_number
>= 0)
2506 /* Similarly, check for a case where we have a PARALLEL of two independent
2507 SETs but we started with three insns. In this case, we can do the sets
2508 as two separate insns. This case occurs when some SET allows two
2509 other insns to combine, but the destination of that SET is still live. */
2511 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2512 && GET_CODE (newpat
) == PARALLEL
2513 && XVECLEN (newpat
, 0) == 2
2514 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2515 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2516 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2517 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2518 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2519 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2520 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2522 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2523 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2524 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2525 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2526 XVECEXP (newpat
, 0, 0))
2527 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2528 XVECEXP (newpat
, 0, 1))
2529 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2530 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2532 /* Normally, it doesn't matter which of the two is done first,
2533 but it does if one references cc0. In that case, it has to
2536 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2538 newi2pat
= XVECEXP (newpat
, 0, 0);
2539 newpat
= XVECEXP (newpat
, 0, 1);
2544 newi2pat
= XVECEXP (newpat
, 0, 1);
2545 newpat
= XVECEXP (newpat
, 0, 0);
2548 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2550 if (i2_code_number
>= 0)
2551 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2554 /* If it still isn't recognized, fail and change things back the way they
2556 if ((insn_code_number
< 0
2557 /* Is the result a reasonable ASM_OPERANDS? */
2558 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2564 /* If we had to change another insn, make sure it is valid also. */
2565 if (undobuf
.other_insn
)
2567 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2568 rtx new_other_notes
;
2571 CLEAR_HARD_REG_SET (newpat_used_regs
);
2573 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2576 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2582 PATTERN (undobuf
.other_insn
) = other_pat
;
2584 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2585 are still valid. Then add any non-duplicate notes added by
2586 recog_for_combine. */
2587 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2589 next
= XEXP (note
, 1);
2591 if (REG_NOTE_KIND (note
) == REG_UNUSED
2592 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2594 if (REG_P (XEXP (note
, 0)))
2595 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2597 remove_note (undobuf
.other_insn
, note
);
2601 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2602 if (REG_P (XEXP (note
, 0)))
2603 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2605 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2606 undobuf
.other_insn
, NULL_RTX
);
2609 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2610 they are adjacent to each other or not. */
2612 rtx p
= prev_nonnote_insn (i3
);
2613 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
2614 && sets_cc0_p (newi2pat
))
2622 /* Only allow this combination if insn_rtx_costs reports that the
2623 replacement instructions are cheaper than the originals. */
2624 if (!combine_validate_cost (i1
, i2
, i3
, newpat
, newi2pat
))
2630 /* We now know that we can do this combination. Merge the insns and
2631 update the status of registers and LOG_LINKS. */
2639 /* I3 now uses what used to be its destination and which is now
2640 I2's destination. This requires us to do a few adjustments. */
2641 PATTERN (i3
) = newpat
;
2642 adjust_for_new_dest (i3
);
2644 /* We need a LOG_LINK from I3 to I2. But we used to have one,
2647 However, some later insn might be using I2's dest and have
2648 a LOG_LINK pointing at I3. We must remove this link.
2649 The simplest way to remove the link is to point it at I1,
2650 which we know will be a NOTE. */
2652 /* newi2pat is usually a SET here; however, recog_for_combine might
2653 have added some clobbers. */
2654 if (GET_CODE (newi2pat
) == PARALLEL
)
2655 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
2657 ni2dest
= SET_DEST (newi2pat
);
2659 for (insn
= NEXT_INSN (i3
);
2660 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2661 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
2662 insn
= NEXT_INSN (insn
))
2664 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2666 for (link
= LOG_LINKS (insn
); link
;
2667 link
= XEXP (link
, 1))
2668 if (XEXP (link
, 0) == i3
)
2669 XEXP (link
, 0) = i1
;
2677 rtx i3notes
, i2notes
, i1notes
= 0;
2678 rtx i3links
, i2links
, i1links
= 0;
2682 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2684 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2685 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2687 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2689 /* Ensure that we do not have something that should not be shared but
2690 occurs multiple times in the new insns. Check this by first
2691 resetting all the `used' flags and then copying anything is shared. */
2693 reset_used_flags (i3notes
);
2694 reset_used_flags (i2notes
);
2695 reset_used_flags (i1notes
);
2696 reset_used_flags (newpat
);
2697 reset_used_flags (newi2pat
);
2698 if (undobuf
.other_insn
)
2699 reset_used_flags (PATTERN (undobuf
.other_insn
));
2701 i3notes
= copy_rtx_if_shared (i3notes
);
2702 i2notes
= copy_rtx_if_shared (i2notes
);
2703 i1notes
= copy_rtx_if_shared (i1notes
);
2704 newpat
= copy_rtx_if_shared (newpat
);
2705 newi2pat
= copy_rtx_if_shared (newi2pat
);
2706 if (undobuf
.other_insn
)
2707 reset_used_flags (PATTERN (undobuf
.other_insn
));
2709 INSN_CODE (i3
) = insn_code_number
;
2710 PATTERN (i3
) = newpat
;
2712 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
2714 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2716 reset_used_flags (call_usage
);
2717 call_usage
= copy_rtx (call_usage
);
2720 replace_rtx (call_usage
, i2dest
, i2src
);
2723 replace_rtx (call_usage
, i1dest
, i1src
);
2725 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2728 if (undobuf
.other_insn
)
2729 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2731 /* We had one special case above where I2 had more than one set and
2732 we replaced a destination of one of those sets with the destination
2733 of I3. In that case, we have to update LOG_LINKS of insns later
2734 in this basic block. Note that this (expensive) case is rare.
2736 Also, in this case, we must pretend that all REG_NOTEs for I2
2737 actually came from I3, so that REG_UNUSED notes from I2 will be
2738 properly handled. */
2740 if (i3_subst_into_i2
)
2742 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2743 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2744 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
2745 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2746 && ! find_reg_note (i2
, REG_UNUSED
,
2747 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2748 for (temp
= NEXT_INSN (i2
);
2749 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2750 || BB_HEAD (this_basic_block
) != temp
);
2751 temp
= NEXT_INSN (temp
))
2752 if (temp
!= i3
&& INSN_P (temp
))
2753 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2754 if (XEXP (link
, 0) == i2
)
2755 XEXP (link
, 0) = i3
;
2760 while (XEXP (link
, 1))
2761 link
= XEXP (link
, 1);
2762 XEXP (link
, 1) = i2notes
;
2776 INSN_CODE (i2
) = i2_code_number
;
2777 PATTERN (i2
) = newi2pat
;
2780 SET_INSN_DELETED (i2
);
2786 SET_INSN_DELETED (i1
);
2789 /* Get death notes for everything that is now used in either I3 or
2790 I2 and used to die in a previous insn. If we built two new
2791 patterns, move from I1 to I2 then I2 to I3 so that we get the
2792 proper movement on registers that I2 modifies. */
2796 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2797 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2800 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2803 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2805 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
);
2807 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
);
2809 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
);
2811 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2813 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2814 know these are REG_UNUSED and want them to go to the desired insn,
2815 so we always pass it as i3. We have not counted the notes in
2816 reg_n_deaths yet, so we need to do so now. */
2818 if (newi2pat
&& new_i2_notes
)
2820 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2821 if (REG_P (XEXP (temp
, 0)))
2822 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2824 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
);
2829 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2830 if (REG_P (XEXP (temp
, 0)))
2831 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2833 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
);
2836 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2837 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2838 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2839 in that case, it might delete I2. Similarly for I2 and I1.
2840 Show an additional death due to the REG_DEAD note we make here. If
2841 we discard it in distribute_notes, we will decrement it again. */
2845 if (REG_P (i3dest_killed
))
2846 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2848 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2849 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2851 NULL_RTX
, i2
, NULL_RTX
);
2853 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2855 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2858 if (i2dest_in_i2src
)
2861 REG_N_DEATHS (REGNO (i2dest
))++;
2863 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2864 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2865 NULL_RTX
, i2
, NULL_RTX
);
2867 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2868 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2871 if (i1dest_in_i1src
)
2874 REG_N_DEATHS (REGNO (i1dest
))++;
2876 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2877 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2878 NULL_RTX
, i2
, NULL_RTX
);
2880 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2881 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2884 distribute_links (i3links
);
2885 distribute_links (i2links
);
2886 distribute_links (i1links
);
2891 rtx i2_insn
= 0, i2_val
= 0, set
;
2893 /* The insn that used to set this register doesn't exist, and
2894 this life of the register may not exist either. See if one of
2895 I3's links points to an insn that sets I2DEST. If it does,
2896 that is now the last known value for I2DEST. If we don't update
2897 this and I2 set the register to a value that depended on its old
2898 contents, we will get confused. If this insn is used, thing
2899 will be set correctly in combine_instructions. */
2901 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2902 if ((set
= single_set (XEXP (link
, 0))) != 0
2903 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2904 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2906 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2908 /* If the reg formerly set in I2 died only once and that was in I3,
2909 zero its use count so it won't make `reload' do any work. */
2911 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2912 && ! i2dest_in_i2src
)
2914 regno
= REGNO (i2dest
);
2915 REG_N_SETS (regno
)--;
2919 if (i1
&& REG_P (i1dest
))
2922 rtx i1_insn
= 0, i1_val
= 0, set
;
2924 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2925 if ((set
= single_set (XEXP (link
, 0))) != 0
2926 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2927 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2929 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2931 regno
= REGNO (i1dest
);
2932 if (! added_sets_1
&& ! i1dest_in_i1src
)
2933 REG_N_SETS (regno
)--;
2936 /* Update reg_stat[].nonzero_bits et al for any changes that may have
2937 been made to this insn. The order of
2938 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
2939 can affect nonzero_bits of newpat */
2941 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2942 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2944 /* Set new_direct_jump_p if a new return or simple jump instruction
2947 If I3 is now an unconditional jump, ensure that it has a
2948 BARRIER following it since it may have initially been a
2949 conditional jump. It may also be the last nonnote insn. */
2951 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2953 *new_direct_jump_p
= 1;
2954 mark_jump_label (PATTERN (i3
), i3
, 0);
2956 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2957 || !BARRIER_P (temp
))
2958 emit_barrier_after (i3
);
2961 if (undobuf
.other_insn
!= NULL_RTX
2962 && (returnjump_p (undobuf
.other_insn
)
2963 || any_uncondjump_p (undobuf
.other_insn
)))
2965 *new_direct_jump_p
= 1;
2967 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
2968 || !BARRIER_P (temp
))
2969 emit_barrier_after (undobuf
.other_insn
);
2972 /* An NOOP jump does not need barrier, but it does need cleaning up
2974 if (GET_CODE (newpat
) == SET
2975 && SET_SRC (newpat
) == pc_rtx
2976 && SET_DEST (newpat
) == pc_rtx
)
2977 *new_direct_jump_p
= 1;
2980 combine_successes
++;
2983 if (added_links_insn
2984 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2985 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2986 return added_links_insn
;
2988 return newi2pat
? i2
: i3
;
2991 /* Undo all the modifications recorded in undobuf. */
2996 struct undo
*undo
, *next
;
2998 for (undo
= undobuf
.undos
; undo
; undo
= next
)
3002 *undo
->where
.i
= undo
->old_contents
.i
;
3004 *undo
->where
.r
= undo
->old_contents
.r
;
3006 undo
->next
= undobuf
.frees
;
3007 undobuf
.frees
= undo
;
3013 /* We've committed to accepting the changes we made. Move all
3014 of the undos to the free list. */
3019 struct undo
*undo
, *next
;
3021 for (undo
= undobuf
.undos
; undo
; undo
= next
)
3024 undo
->next
= undobuf
.frees
;
3025 undobuf
.frees
= undo
;
3031 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3032 where we have an arithmetic expression and return that point. LOC will
3035 try_combine will call this function to see if an insn can be split into
3039 find_split_point (rtx
*loc
, rtx insn
)
3042 enum rtx_code code
= GET_CODE (x
);
3044 unsigned HOST_WIDE_INT len
= 0;
3045 HOST_WIDE_INT pos
= 0;
3047 rtx inner
= NULL_RTX
;
3049 /* First special-case some codes. */
3053 #ifdef INSN_SCHEDULING
3054 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3056 if (MEM_P (SUBREG_REG (x
)))
3059 return find_split_point (&SUBREG_REG (x
), insn
);
3063 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3064 using LO_SUM and HIGH. */
3065 if (GET_CODE (XEXP (x
, 0)) == CONST
3066 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
3069 gen_rtx_LO_SUM (Pmode
,
3070 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
3072 return &XEXP (XEXP (x
, 0), 0);
3076 /* If we have a PLUS whose second operand is a constant and the
3077 address is not valid, perhaps will can split it up using
3078 the machine-specific way to split large constants. We use
3079 the first pseudo-reg (one of the virtual regs) as a placeholder;
3080 it will not remain in the result. */
3081 if (GET_CODE (XEXP (x
, 0)) == PLUS
3082 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3083 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
3085 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
3086 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
3089 /* This should have produced two insns, each of which sets our
3090 placeholder. If the source of the second is a valid address,
3091 we can make put both sources together and make a split point
3095 && NEXT_INSN (seq
) != NULL_RTX
3096 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
3097 && NONJUMP_INSN_P (seq
)
3098 && GET_CODE (PATTERN (seq
)) == SET
3099 && SET_DEST (PATTERN (seq
)) == reg
3100 && ! reg_mentioned_p (reg
,
3101 SET_SRC (PATTERN (seq
)))
3102 && NONJUMP_INSN_P (NEXT_INSN (seq
))
3103 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
3104 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
3105 && memory_address_p (GET_MODE (x
),
3106 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
3108 rtx src1
= SET_SRC (PATTERN (seq
));
3109 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
3111 /* Replace the placeholder in SRC2 with SRC1. If we can
3112 find where in SRC2 it was placed, that can become our
3113 split point and we can replace this address with SRC2.
3114 Just try two obvious places. */
3116 src2
= replace_rtx (src2
, reg
, src1
);
3118 if (XEXP (src2
, 0) == src1
)
3119 split
= &XEXP (src2
, 0);
3120 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
3121 && XEXP (XEXP (src2
, 0), 0) == src1
)
3122 split
= &XEXP (XEXP (src2
, 0), 0);
3126 SUBST (XEXP (x
, 0), src2
);
3131 /* If that didn't work, perhaps the first operand is complex and
3132 needs to be computed separately, so make a split point there.
3133 This will occur on machines that just support REG + CONST
3134 and have a constant moved through some previous computation. */
3136 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
3137 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
3138 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
3139 return &XEXP (XEXP (x
, 0), 0);
3145 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3146 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3147 we need to put the operand into a register. So split at that
3150 if (SET_DEST (x
) == cc0_rtx
3151 && GET_CODE (SET_SRC (x
)) != COMPARE
3152 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
3153 && !OBJECT_P (SET_SRC (x
))
3154 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
3155 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
3156 return &SET_SRC (x
);
3159 /* See if we can split SET_SRC as it stands. */
3160 split
= find_split_point (&SET_SRC (x
), insn
);
3161 if (split
&& split
!= &SET_SRC (x
))
3164 /* See if we can split SET_DEST as it stands. */
3165 split
= find_split_point (&SET_DEST (x
), insn
);
3166 if (split
&& split
!= &SET_DEST (x
))
3169 /* See if this is a bitfield assignment with everything constant. If
3170 so, this is an IOR of an AND, so split it into that. */
3171 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
3172 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
3173 <= HOST_BITS_PER_WIDE_INT
)
3174 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
3175 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
3176 && GET_CODE (SET_SRC (x
)) == CONST_INT
3177 && ((INTVAL (XEXP (SET_DEST (x
), 1))
3178 + INTVAL (XEXP (SET_DEST (x
), 2)))
3179 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
3180 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
3182 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3183 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3184 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3185 rtx dest
= XEXP (SET_DEST (x
), 0);
3186 enum machine_mode mode
= GET_MODE (dest
);
3187 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3189 if (BITS_BIG_ENDIAN
)
3190 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3194 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3197 gen_binary (IOR
, mode
,
3198 gen_binary (AND
, mode
, dest
,
3199 gen_int_mode (~(mask
<< pos
),
3201 GEN_INT (src
<< pos
)));
3203 SUBST (SET_DEST (x
), dest
);
3205 split
= find_split_point (&SET_SRC (x
), insn
);
3206 if (split
&& split
!= &SET_SRC (x
))
3210 /* Otherwise, see if this is an operation that we can split into two.
3211 If so, try to split that. */
3212 code
= GET_CODE (SET_SRC (x
));
3217 /* If we are AND'ing with a large constant that is only a single
3218 bit and the result is only being used in a context where we
3219 need to know if it is zero or nonzero, replace it with a bit
3220 extraction. This will avoid the large constant, which might
3221 have taken more than one insn to make. If the constant were
3222 not a valid argument to the AND but took only one insn to make,
3223 this is no worse, but if it took more than one insn, it will
3226 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3227 && REG_P (XEXP (SET_SRC (x
), 0))
3228 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3229 && REG_P (SET_DEST (x
))
3230 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3231 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3232 && XEXP (*split
, 0) == SET_DEST (x
)
3233 && XEXP (*split
, 1) == const0_rtx
)
3235 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3236 XEXP (SET_SRC (x
), 0),
3237 pos
, NULL_RTX
, 1, 1, 0, 0);
3238 if (extraction
!= 0)
3240 SUBST (SET_SRC (x
), extraction
);
3241 return find_split_point (loc
, insn
);
3247 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3248 is known to be on, this can be converted into a NEG of a shift. */
3249 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3250 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3251 && 1 <= (pos
= exact_log2
3252 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3253 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3255 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3259 gen_rtx_LSHIFTRT (mode
,
3260 XEXP (SET_SRC (x
), 0),
3263 split
= find_split_point (&SET_SRC (x
), insn
);
3264 if (split
&& split
!= &SET_SRC (x
))
3270 inner
= XEXP (SET_SRC (x
), 0);
3272 /* We can't optimize if either mode is a partial integer
3273 mode as we don't know how many bits are significant
3275 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3276 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3280 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3286 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3287 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3289 inner
= XEXP (SET_SRC (x
), 0);
3290 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3291 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3293 if (BITS_BIG_ENDIAN
)
3294 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3295 unsignedp
= (code
== ZERO_EXTRACT
);
3303 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3305 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3307 /* For unsigned, we have a choice of a shift followed by an
3308 AND or two shifts. Use two shifts for field sizes where the
3309 constant might be too large. We assume here that we can
3310 always at least get 8-bit constants in an AND insn, which is
3311 true for every current RISC. */
3313 if (unsignedp
&& len
<= 8)
3318 (mode
, gen_lowpart (mode
, inner
),
3320 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3322 split
= find_split_point (&SET_SRC (x
), insn
);
3323 if (split
&& split
!= &SET_SRC (x
))
3330 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3331 gen_rtx_ASHIFT (mode
,
3332 gen_lowpart (mode
, inner
),
3333 GEN_INT (GET_MODE_BITSIZE (mode
)
3335 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3337 split
= find_split_point (&SET_SRC (x
), insn
);
3338 if (split
&& split
!= &SET_SRC (x
))
3343 /* See if this is a simple operation with a constant as the second
3344 operand. It might be that this constant is out of range and hence
3345 could be used as a split point. */
3346 if (BINARY_P (SET_SRC (x
))
3347 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3348 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
3349 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3350 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
3351 return &XEXP (SET_SRC (x
), 1);
3353 /* Finally, see if this is a simple operation with its first operand
3354 not in a register. The operation might require this operand in a
3355 register, so return it as a split point. We can always do this
3356 because if the first operand were another operation, we would have
3357 already found it as a split point. */
3358 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
3359 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3360 return &XEXP (SET_SRC (x
), 0);
3366 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3367 it is better to write this as (not (ior A B)) so we can split it.
3368 Similarly for IOR. */
3369 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3372 gen_rtx_NOT (GET_MODE (x
),
3373 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3375 XEXP (XEXP (x
, 0), 0),
3376 XEXP (XEXP (x
, 1), 0))));
3377 return find_split_point (loc
, insn
);
3380 /* Many RISC machines have a large set of logical insns. If the
3381 second operand is a NOT, put it first so we will try to split the
3382 other operand first. */
3383 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3385 rtx tem
= XEXP (x
, 0);
3386 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3387 SUBST (XEXP (x
, 1), tem
);
3395 /* Otherwise, select our actions depending on our rtx class. */
3396 switch (GET_RTX_CLASS (code
))
3398 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3400 split
= find_split_point (&XEXP (x
, 2), insn
);
3403 /* ... fall through ... */
3405 case RTX_COMM_ARITH
:
3407 case RTX_COMM_COMPARE
:
3408 split
= find_split_point (&XEXP (x
, 1), insn
);
3411 /* ... fall through ... */
3413 /* Some machines have (and (shift ...) ...) insns. If X is not
3414 an AND, but XEXP (X, 0) is, use it as our split point. */
3415 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3416 return &XEXP (x
, 0);
3418 split
= find_split_point (&XEXP (x
, 0), insn
);
3424 /* Otherwise, we don't have a split point. */
3429 /* Throughout X, replace FROM with TO, and return the result.
3430 The result is TO if X is FROM;
3431 otherwise the result is X, but its contents may have been modified.
3432 If they were modified, a record was made in undobuf so that
3433 undo_all will (among other things) return X to its original state.
3435 If the number of changes necessary is too much to record to undo,
3436 the excess changes are not made, so the result is invalid.
3437 The changes already made can still be undone.
3438 undobuf.num_undo is incremented for such changes, so by testing that
3439 the caller can tell whether the result is valid.
3441 `n_occurrences' is incremented each time FROM is replaced.
3443 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3445 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3446 by copying if `n_occurrences' is nonzero. */
3449 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
3451 enum rtx_code code
= GET_CODE (x
);
3452 enum machine_mode op0_mode
= VOIDmode
;
3457 /* Two expressions are equal if they are identical copies of a shared
3458 RTX or if they are both registers with the same register number
3461 #define COMBINE_RTX_EQUAL_P(X,Y) \
3463 || (REG_P (X) && REG_P (Y) \
3464 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3466 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3469 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3472 /* If X and FROM are the same register but different modes, they will
3473 not have been seen as equal above. However, flow.c will make a
3474 LOG_LINKS entry for that case. If we do nothing, we will try to
3475 rerecognize our original insn and, when it succeeds, we will
3476 delete the feeding insn, which is incorrect.
3478 So force this insn not to match in this (rare) case. */
3479 if (! in_dest
&& code
== REG
&& REG_P (from
)
3480 && REGNO (x
) == REGNO (from
))
3481 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3483 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3484 of which may contain things that can be combined. */
3485 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
3488 /* It is possible to have a subexpression appear twice in the insn.
3489 Suppose that FROM is a register that appears within TO.
3490 Then, after that subexpression has been scanned once by `subst',
3491 the second time it is scanned, TO may be found. If we were
3492 to scan TO here, we would find FROM within it and create a
3493 self-referent rtl structure which is completely wrong. */
3494 if (COMBINE_RTX_EQUAL_P (x
, to
))
3497 /* Parallel asm_operands need special attention because all of the
3498 inputs are shared across the arms. Furthermore, unsharing the
3499 rtl results in recognition failures. Failure to handle this case
3500 specially can result in circular rtl.
3502 Solve this by doing a normal pass across the first entry of the
3503 parallel, and only processing the SET_DESTs of the subsequent
3506 if (code
== PARALLEL
3507 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3508 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3510 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3512 /* If this substitution failed, this whole thing fails. */
3513 if (GET_CODE (new) == CLOBBER
3514 && XEXP (new, 0) == const0_rtx
)
3517 SUBST (XVECEXP (x
, 0, 0), new);
3519 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3521 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3524 && GET_CODE (dest
) != CC0
3525 && GET_CODE (dest
) != PC
)
3527 new = subst (dest
, from
, to
, 0, unique_copy
);
3529 /* If this substitution failed, this whole thing fails. */
3530 if (GET_CODE (new) == CLOBBER
3531 && XEXP (new, 0) == const0_rtx
)
3534 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3540 len
= GET_RTX_LENGTH (code
);
3541 fmt
= GET_RTX_FORMAT (code
);
3543 /* We don't need to process a SET_DEST that is a register, CC0,
3544 or PC, so set up to skip this common case. All other cases
3545 where we want to suppress replacing something inside a
3546 SET_SRC are handled via the IN_DEST operand. */
3548 && (REG_P (SET_DEST (x
))
3549 || GET_CODE (SET_DEST (x
)) == CC0
3550 || GET_CODE (SET_DEST (x
)) == PC
))
3553 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3556 op0_mode
= GET_MODE (XEXP (x
, 0));
3558 for (i
= 0; i
< len
; i
++)
3563 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3565 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3567 new = (unique_copy
&& n_occurrences
3568 ? copy_rtx (to
) : to
);
3573 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3576 /* If this substitution failed, this whole thing
3578 if (GET_CODE (new) == CLOBBER
3579 && XEXP (new, 0) == const0_rtx
)
3583 SUBST (XVECEXP (x
, i
, j
), new);
3586 else if (fmt
[i
] == 'e')
3588 /* If this is a register being set, ignore it. */
3592 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
3594 || code
== STRICT_LOW_PART
))
3597 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3599 /* In general, don't install a subreg involving two
3600 modes not tieable. It can worsen register
3601 allocation, and can even make invalid reload
3602 insns, since the reg inside may need to be copied
3603 from in the outside mode, and that may be invalid
3604 if it is an fp reg copied in integer mode.
3606 We allow two exceptions to this: It is valid if
3607 it is inside another SUBREG and the mode of that
3608 SUBREG and the mode of the inside of TO is
3609 tieable and it is valid if X is a SET that copies
3612 if (GET_CODE (to
) == SUBREG
3613 && ! MODES_TIEABLE_P (GET_MODE (to
),
3614 GET_MODE (SUBREG_REG (to
)))
3615 && ! (code
== SUBREG
3616 && MODES_TIEABLE_P (GET_MODE (x
),
3617 GET_MODE (SUBREG_REG (to
))))
3619 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3622 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3624 #ifdef CANNOT_CHANGE_MODE_CLASS
3627 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3628 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3631 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3634 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3638 /* If we are in a SET_DEST, suppress most cases unless we
3639 have gone inside a MEM, in which case we want to
3640 simplify the address. We assume here that things that
3641 are actually part of the destination have their inner
3642 parts in the first expression. This is true for SUBREG,
3643 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3644 things aside from REG and MEM that should appear in a
3646 new = subst (XEXP (x
, i
), from
, to
,
3648 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3649 || code
== ZERO_EXTRACT
))
3651 && i
== 0), unique_copy
);
3653 /* If we found that we will have to reject this combination,
3654 indicate that by returning the CLOBBER ourselves, rather than
3655 an expression containing it. This will speed things up as
3656 well as prevent accidents where two CLOBBERs are considered
3657 to be equal, thus producing an incorrect simplification. */
3659 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3662 if (GET_CODE (x
) == SUBREG
3663 && (GET_CODE (new) == CONST_INT
3664 || GET_CODE (new) == CONST_DOUBLE
))
3666 enum machine_mode mode
= GET_MODE (x
);
3668 x
= simplify_subreg (GET_MODE (x
), new,
3669 GET_MODE (SUBREG_REG (x
)),
3672 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3674 else if (GET_CODE (new) == CONST_INT
3675 && GET_CODE (x
) == ZERO_EXTEND
)
3677 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3678 new, GET_MODE (XEXP (x
, 0)));
3682 SUBST (XEXP (x
, i
), new);
3687 /* Try to simplify X. If the simplification changed the code, it is likely
3688 that further simplification will help, so loop, but limit the number
3689 of repetitions that will be performed. */
3691 for (i
= 0; i
< 4; i
++)
3693 /* If X is sufficiently simple, don't bother trying to do anything
3695 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3696 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
);
3698 if (GET_CODE (x
) == code
)
3701 code
= GET_CODE (x
);
3703 /* We no longer know the original mode of operand 0 since we
3704 have changed the form of X) */
3705 op0_mode
= VOIDmode
;
3711 /* Simplify X, a piece of RTL. We just operate on the expression at the
3712 outer level; call `subst' to simplify recursively. Return the new
3715 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3716 if we are inside a SET_DEST. */
3719 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
)
3721 enum rtx_code code
= GET_CODE (x
);
3722 enum machine_mode mode
= GET_MODE (x
);
3727 /* If this is a commutative operation, put a constant last and a complex
3728 expression first. We don't need to do this for comparisons here. */
3729 if (COMMUTATIVE_ARITH_P (x
)
3730 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3733 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3734 SUBST (XEXP (x
, 1), temp
);
3737 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3738 sign extension of a PLUS with a constant, reverse the order of the sign
3739 extension and the addition. Note that this not the same as the original
3740 code, but overflow is undefined for signed values. Also note that the
3741 PLUS will have been partially moved "inside" the sign-extension, so that
3742 the first operand of X will really look like:
3743 (ashiftrt (plus (ashift A C4) C5) C4).
3745 (plus (ashiftrt (ashift A C4) C2) C4)
3746 and replace the first operand of X with that expression. Later parts
3747 of this function may simplify the expression further.
3749 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3750 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3751 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3753 We do this to simplify address expressions. */
3755 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3756 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3757 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3758 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3759 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3760 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3761 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3762 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3763 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3764 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3765 XEXP (XEXP (x
, 0), 1))) != 0)
3768 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3769 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3770 INTVAL (XEXP (XEXP (x
, 0), 1)));
3772 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3773 INTVAL (XEXP (XEXP (x
, 0), 1)));
3775 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3778 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3779 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3780 things. Check for cases where both arms are testing the same
3783 Don't do anything if all operands are very simple. */
3786 && ((!OBJECT_P (XEXP (x
, 0))
3787 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3788 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
3789 || (!OBJECT_P (XEXP (x
, 1))
3790 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3791 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
3793 && (!OBJECT_P (XEXP (x
, 0))
3794 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3795 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
3797 rtx cond
, true_rtx
, false_rtx
;
3799 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3801 /* If everything is a comparison, what we have is highly unlikely
3802 to be simpler, so don't use it. */
3803 && ! (COMPARISON_P (x
)
3804 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
3806 rtx cop1
= const0_rtx
;
3807 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3809 if (cond_code
== NE
&& COMPARISON_P (cond
))
3812 /* Simplify the alternative arms; this may collapse the true and
3813 false arms to store-flag values. Be careful to use copy_rtx
3814 here since true_rtx or false_rtx might share RTL with x as a
3815 result of the if_then_else_cond call above. */
3816 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3817 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3819 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3820 is unlikely to be simpler. */
3821 if (general_operand (true_rtx
, VOIDmode
)
3822 && general_operand (false_rtx
, VOIDmode
))
3824 enum rtx_code reversed
;
3826 /* Restarting if we generate a store-flag expression will cause
3827 us to loop. Just drop through in this case. */
3829 /* If the result values are STORE_FLAG_VALUE and zero, we can
3830 just make the comparison operation. */
3831 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3832 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3833 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3834 && ((reversed
= reversed_comparison_code_parts
3835 (cond_code
, cond
, cop1
, NULL
))
3837 x
= gen_binary (reversed
, mode
, cond
, cop1
);
3839 /* Likewise, we can make the negate of a comparison operation
3840 if the result values are - STORE_FLAG_VALUE and zero. */
3841 else if (GET_CODE (true_rtx
) == CONST_INT
3842 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3843 && false_rtx
== const0_rtx
)
3844 x
= simplify_gen_unary (NEG
, mode
,
3845 gen_binary (cond_code
, mode
, cond
,
3848 else if (GET_CODE (false_rtx
) == CONST_INT
3849 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3850 && true_rtx
== const0_rtx
3851 && ((reversed
= reversed_comparison_code_parts
3852 (cond_code
, cond
, cop1
, NULL
))
3854 x
= simplify_gen_unary (NEG
, mode
,
3855 gen_binary (reversed
, mode
,
3859 return gen_rtx_IF_THEN_ELSE (mode
,
3860 gen_binary (cond_code
, VOIDmode
,
3862 true_rtx
, false_rtx
);
3864 code
= GET_CODE (x
);
3865 op0_mode
= VOIDmode
;
3870 /* Try to fold this expression in case we have constants that weren't
3873 switch (GET_RTX_CLASS (code
))
3876 if (op0_mode
== VOIDmode
)
3877 op0_mode
= GET_MODE (XEXP (x
, 0));
3878 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3881 case RTX_COMM_COMPARE
:
3883 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3884 if (cmp_mode
== VOIDmode
)
3886 cmp_mode
= GET_MODE (XEXP (x
, 1));
3887 if (cmp_mode
== VOIDmode
)
3888 cmp_mode
= op0_mode
;
3890 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
3891 XEXP (x
, 0), XEXP (x
, 1));
3894 case RTX_COMM_ARITH
:
3896 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3898 case RTX_BITFIELD_OPS
:
3900 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3901 XEXP (x
, 1), XEXP (x
, 2));
3910 code
= GET_CODE (temp
);
3911 op0_mode
= VOIDmode
;
3912 mode
= GET_MODE (temp
);
3915 /* First see if we can apply the inverse distributive law. */
3916 if (code
== PLUS
|| code
== MINUS
3917 || code
== AND
|| code
== IOR
|| code
== XOR
)
3919 x
= apply_distributive_law (x
);
3920 code
= GET_CODE (x
);
3921 op0_mode
= VOIDmode
;
3924 /* If CODE is an associative operation not otherwise handled, see if we
3925 can associate some operands. This can win if they are constants or
3926 if they are logically related (i.e. (a & b) & a). */
3927 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3928 || code
== AND
|| code
== IOR
|| code
== XOR
3929 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3930 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3931 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3933 if (GET_CODE (XEXP (x
, 0)) == code
)
3935 rtx other
= XEXP (XEXP (x
, 0), 0);
3936 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3937 rtx inner_op1
= XEXP (x
, 1);
3940 /* Make sure we pass the constant operand if any as the second
3941 one if this is a commutative operation. */
3942 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
3944 rtx tem
= inner_op0
;
3945 inner_op0
= inner_op1
;
3948 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3949 : code
== DIV
? MULT
3951 mode
, inner_op0
, inner_op1
);
3953 /* For commutative operations, try the other pair if that one
3955 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
3957 other
= XEXP (XEXP (x
, 0), 1);
3958 inner
= simplify_binary_operation (code
, mode
,
3959 XEXP (XEXP (x
, 0), 0),
3964 return gen_binary (code
, mode
, other
, inner
);
3968 /* A little bit of algebraic simplification here. */
3972 /* Ensure that our address has any ASHIFTs converted to MULT in case
3973 address-recognizing predicates are called later. */
3974 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3975 SUBST (XEXP (x
, 0), temp
);
3979 if (op0_mode
== VOIDmode
)
3980 op0_mode
= GET_MODE (SUBREG_REG (x
));
3982 /* See if this can be moved to simplify_subreg. */
3983 if (CONSTANT_P (SUBREG_REG (x
))
3984 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3985 /* Don't call gen_lowpart if the inner mode
3986 is VOIDmode and we cannot simplify it, as SUBREG without
3987 inner mode is invalid. */
3988 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3989 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3990 return gen_lowpart (mode
, SUBREG_REG (x
));
3992 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3996 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
4002 /* Don't change the mode of the MEM if that would change the meaning
4004 if (MEM_P (SUBREG_REG (x
))
4005 && (MEM_VOLATILE_P (SUBREG_REG (x
))
4006 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
4007 return gen_rtx_CLOBBER (mode
, const0_rtx
);
4009 /* Note that we cannot do any narrowing for non-constants since
4010 we might have been counting on using the fact that some bits were
4011 zero. We now do this in the SET. */
4016 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4017 && subreg_lowpart_p (XEXP (x
, 0))
4018 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
4019 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
4020 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
4021 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
4023 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
4025 x
= gen_rtx_ROTATE (inner_mode
,
4026 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
4028 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
4029 return gen_lowpart (mode
, x
);
4032 /* Apply De Morgan's laws to reduce number of patterns for machines
4033 with negating logical insns (and-not, nand, etc.). If result has
4034 only one NOT, put it first, since that is how the patterns are
4037 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
4039 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
4040 enum machine_mode op_mode
;
4042 op_mode
= GET_MODE (in1
);
4043 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
4045 op_mode
= GET_MODE (in2
);
4046 if (op_mode
== VOIDmode
)
4048 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
4050 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
4053 in2
= in1
; in1
= tem
;
4056 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
4062 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4063 if (GET_CODE (XEXP (x
, 0)) == XOR
4064 && XEXP (XEXP (x
, 0), 1) == const1_rtx
4065 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
4066 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
4068 temp
= expand_compound_operation (XEXP (x
, 0));
4070 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4071 replaced by (lshiftrt X C). This will convert
4072 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4074 if (GET_CODE (temp
) == ASHIFTRT
4075 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
4076 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4077 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4078 INTVAL (XEXP (temp
, 1)));
4080 /* If X has only a single bit that might be nonzero, say, bit I, convert
4081 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4082 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4083 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4084 or a SUBREG of one since we'd be making the expression more
4085 complex if it was just a register. */
4088 && ! (GET_CODE (temp
) == SUBREG
4089 && REG_P (SUBREG_REG (temp
)))
4090 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4092 rtx temp1
= simplify_shift_const
4093 (NULL_RTX
, ASHIFTRT
, mode
,
4094 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4095 GET_MODE_BITSIZE (mode
) - 1 - i
),
4096 GET_MODE_BITSIZE (mode
) - 1 - i
);
4098 /* If all we did was surround TEMP with the two shifts, we
4099 haven't improved anything, so don't use it. Otherwise,
4100 we are better off with TEMP1. */
4101 if (GET_CODE (temp1
) != ASHIFTRT
4102 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4103 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4109 /* We can't handle truncation to a partial integer mode here
4110 because we don't know the real bitsize of the partial
4112 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4115 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4116 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4117 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
4119 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4120 GET_MODE_MASK (mode
), NULL_RTX
, 0));
4122 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4123 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4124 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4125 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4126 return XEXP (XEXP (x
, 0), 0);
4128 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4129 (OP:SI foo:SI) if OP is NEG or ABS. */
4130 if ((GET_CODE (XEXP (x
, 0)) == ABS
4131 || GET_CODE (XEXP (x
, 0)) == NEG
)
4132 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
4133 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4134 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4135 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4136 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4138 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4140 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4141 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4142 && subreg_lowpart_p (XEXP (x
, 0)))
4143 return SUBREG_REG (XEXP (x
, 0));
4145 /* If we know that the value is already truncated, we can
4146 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4147 is nonzero for the corresponding modes. But don't do this
4148 for an (LSHIFTRT (MULT ...)) since this will cause problems
4149 with the umulXi3_highpart patterns. */
4150 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4151 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4152 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4153 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
4154 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4155 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4156 return gen_lowpart (mode
, XEXP (x
, 0));
4158 /* A truncate of a comparison can be replaced with a subreg if
4159 STORE_FLAG_VALUE permits. This is like the previous test,
4160 but it works even if the comparison is done in a mode larger
4161 than HOST_BITS_PER_WIDE_INT. */
4162 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4163 && COMPARISON_P (XEXP (x
, 0))
4164 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4165 return gen_lowpart (mode
, XEXP (x
, 0));
4167 /* Similarly, a truncate of a register whose value is a
4168 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4170 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4171 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4172 && (temp
= get_last_value (XEXP (x
, 0)))
4173 && COMPARISON_P (temp
))
4174 return gen_lowpart (mode
, XEXP (x
, 0));
4178 case FLOAT_TRUNCATE
:
4179 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4180 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4181 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4182 return XEXP (XEXP (x
, 0), 0);
4184 /* (float_truncate:SF (float_truncate:DF foo:XF))
4185 = (float_truncate:SF foo:XF).
4186 This may eliminate double rounding, so it is unsafe.
4188 (float_truncate:SF (float_extend:XF foo:DF))
4189 = (float_truncate:SF foo:DF).
4191 (float_truncate:DF (float_extend:XF foo:SF))
4192 = (float_extend:SF foo:DF). */
4193 if ((GET_CODE (XEXP (x
, 0)) == FLOAT_TRUNCATE
4194 && flag_unsafe_math_optimizations
)
4195 || GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
)
4196 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0),
4198 > GET_MODE_SIZE (mode
)
4199 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
4201 XEXP (XEXP (x
, 0), 0), mode
);
4203 /* (float_truncate (float x)) is (float x) */
4204 if (GET_CODE (XEXP (x
, 0)) == FLOAT
4205 && (flag_unsafe_math_optimizations
4206 || ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4207 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4208 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4209 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4210 return simplify_gen_unary (FLOAT
, mode
,
4211 XEXP (XEXP (x
, 0), 0),
4212 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4214 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4215 (OP:SF foo:SF) if OP is NEG or ABS. */
4216 if ((GET_CODE (XEXP (x
, 0)) == ABS
4217 || GET_CODE (XEXP (x
, 0)) == NEG
)
4218 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4219 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4220 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4221 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4223 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4224 is (float_truncate:SF x). */
4225 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4226 && subreg_lowpart_p (XEXP (x
, 0))
4227 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4228 return SUBREG_REG (XEXP (x
, 0));
4231 /* (float_extend (float_extend x)) is (float_extend x)
4233 (float_extend (float x)) is (float x) assuming that double
4234 rounding can't happen.
4236 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4237 || (GET_CODE (XEXP (x
, 0)) == FLOAT
4238 && ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4239 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4240 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4241 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4242 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4243 XEXP (XEXP (x
, 0), 0),
4244 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4249 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4250 using cc0, in which case we want to leave it as a COMPARE
4251 so we can distinguish it from a register-register-copy. */
4252 if (XEXP (x
, 1) == const0_rtx
)
4255 /* x - 0 is the same as x unless x's mode has signed zeros and
4256 allows rounding towards -infinity. Under those conditions,
4258 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4259 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4260 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4266 /* (const (const X)) can become (const X). Do it this way rather than
4267 returning the inner CONST since CONST can be shared with a
4269 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4270 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4275 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4276 can add in an offset. find_split_point will split this address up
4277 again if it doesn't match. */
4278 if (GET_CODE (XEXP (x
, 0)) == HIGH
4279 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4285 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4287 if (GET_CODE (XEXP (x
, 0)) == MULT
4288 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == NEG
)
4292 in1
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4293 in2
= XEXP (XEXP (x
, 0), 1);
4294 return gen_binary (MINUS
, mode
, XEXP (x
, 1),
4295 gen_binary (MULT
, mode
, in1
, in2
));
4298 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4299 outermost. That's because that's the way indexed addresses are
4300 supposed to appear. This code used to check many more cases, but
4301 they are now checked elsewhere. */
4302 if (GET_CODE (XEXP (x
, 0)) == PLUS
4303 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4304 return gen_binary (PLUS
, mode
,
4305 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4307 XEXP (XEXP (x
, 0), 1));
4309 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4310 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4311 bit-field and can be replaced by either a sign_extend or a
4312 sign_extract. The `and' may be a zero_extend and the two
4313 <c>, -<c> constants may be reversed. */
4314 if (GET_CODE (XEXP (x
, 0)) == XOR
4315 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4316 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4317 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4318 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4319 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4320 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4321 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4322 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4323 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4324 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4325 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4326 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4327 == (unsigned int) i
+ 1))))
4328 return simplify_shift_const
4329 (NULL_RTX
, ASHIFTRT
, mode
,
4330 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4331 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4332 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4333 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4335 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4336 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4337 is 1. This produces better code than the alternative immediately
4339 if (COMPARISON_P (XEXP (x
, 0))
4340 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4341 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4342 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4343 XEXP (XEXP (x
, 0), 0),
4344 XEXP (XEXP (x
, 0), 1))))
4346 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4348 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4349 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4350 the bitsize of the mode - 1. This allows simplification of
4351 "a = (b & 8) == 0;" */
4352 if (XEXP (x
, 1) == constm1_rtx
4353 && !REG_P (XEXP (x
, 0))
4354 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4355 && REG_P (SUBREG_REG (XEXP (x
, 0))))
4356 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4357 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4358 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4359 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4360 GET_MODE_BITSIZE (mode
) - 1),
4361 GET_MODE_BITSIZE (mode
) - 1);
4363 /* If we are adding two things that have no bits in common, convert
4364 the addition into an IOR. This will often be further simplified,
4365 for example in cases like ((a & 1) + (a & 2)), which can
4368 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4369 && (nonzero_bits (XEXP (x
, 0), mode
)
4370 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4372 /* Try to simplify the expression further. */
4373 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4374 temp
= combine_simplify_rtx (tor
, mode
, in_dest
);
4376 /* If we could, great. If not, do not go ahead with the IOR
4377 replacement, since PLUS appears in many special purpose
4378 address arithmetic instructions. */
4379 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4385 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4386 by reversing the comparison code if valid. */
4387 if (STORE_FLAG_VALUE
== 1
4388 && XEXP (x
, 0) == const1_rtx
4389 && COMPARISON_P (XEXP (x
, 1))
4390 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4391 XEXP (XEXP (x
, 1), 0),
4392 XEXP (XEXP (x
, 1), 1))))
4395 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4396 (and <foo> (const_int pow2-1)) */
4397 if (GET_CODE (XEXP (x
, 1)) == AND
4398 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4399 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4400 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4401 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4402 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4404 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4406 if (GET_CODE (XEXP (x
, 1)) == MULT
4407 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == NEG
)
4411 in1
= XEXP (XEXP (XEXP (x
, 1), 0), 0);
4412 in2
= XEXP (XEXP (x
, 1), 1);
4413 return gen_binary (PLUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4417 /* Canonicalize (minus (neg A) (mult B C)) to
4418 (minus (mult (neg B) C) A). */
4419 if (GET_CODE (XEXP (x
, 1)) == MULT
4420 && GET_CODE (XEXP (x
, 0)) == NEG
)
4424 in1
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 1), 0), mode
);
4425 in2
= XEXP (XEXP (x
, 1), 1);
4426 return gen_binary (MINUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4427 XEXP (XEXP (x
, 0), 0));
4430 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4432 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4433 return gen_binary (MINUS
, mode
,
4434 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4435 XEXP (XEXP (x
, 1), 0)),
4436 XEXP (XEXP (x
, 1), 1));
4440 /* If we have (mult (plus A B) C), apply the distributive law and then
4441 the inverse distributive law to see if things simplify. This
4442 occurs mostly in addresses, often when unrolling loops. */
4444 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4446 x
= apply_distributive_law
4447 (gen_binary (PLUS
, mode
,
4448 gen_binary (MULT
, mode
,
4449 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4450 gen_binary (MULT
, mode
,
4451 XEXP (XEXP (x
, 0), 1),
4452 copy_rtx (XEXP (x
, 1)))));
4454 if (GET_CODE (x
) != MULT
)
4457 /* Try simplify a*(b/c) as (a*b)/c. */
4458 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4459 && GET_CODE (XEXP (x
, 0)) == DIV
)
4461 rtx tem
= simplify_binary_operation (MULT
, mode
,
4462 XEXP (XEXP (x
, 0), 0),
4465 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4470 /* If this is a divide by a power of two, treat it as a shift if
4471 its first operand is a shift. */
4472 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4473 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4474 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4475 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4476 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4477 || GET_CODE (XEXP (x
, 0)) == ROTATE
4478 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4479 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4483 case GT
: case GTU
: case GE
: case GEU
:
4484 case LT
: case LTU
: case LE
: case LEU
:
4485 case UNEQ
: case LTGT
:
4486 case UNGT
: case UNGE
:
4487 case UNLT
: case UNLE
:
4488 case UNORDERED
: case ORDERED
:
4489 /* If the first operand is a condition code, we can't do anything
4491 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4492 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4493 && ! CC0_P (XEXP (x
, 0))))
4495 rtx op0
= XEXP (x
, 0);
4496 rtx op1
= XEXP (x
, 1);
4497 enum rtx_code new_code
;
4499 if (GET_CODE (op0
) == COMPARE
)
4500 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4502 /* Simplify our comparison, if possible. */
4503 new_code
= simplify_comparison (code
, &op0
, &op1
);
4505 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4506 if only the low-order bit is possibly nonzero in X (such as when
4507 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4508 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4509 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4512 Remove any ZERO_EXTRACT we made when thinking this was a
4513 comparison. It may now be simpler to use, e.g., an AND. If a
4514 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4515 the call to make_compound_operation in the SET case. */
4517 if (STORE_FLAG_VALUE
== 1
4518 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4519 && op1
== const0_rtx
4520 && mode
== GET_MODE (op0
)
4521 && nonzero_bits (op0
, mode
) == 1)
4522 return gen_lowpart (mode
,
4523 expand_compound_operation (op0
));
4525 else if (STORE_FLAG_VALUE
== 1
4526 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4527 && op1
== const0_rtx
4528 && mode
== GET_MODE (op0
)
4529 && (num_sign_bit_copies (op0
, mode
)
4530 == GET_MODE_BITSIZE (mode
)))
4532 op0
= expand_compound_operation (op0
);
4533 return simplify_gen_unary (NEG
, mode
,
4534 gen_lowpart (mode
, op0
),
4538 else if (STORE_FLAG_VALUE
== 1
4539 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4540 && op1
== const0_rtx
4541 && mode
== GET_MODE (op0
)
4542 && nonzero_bits (op0
, mode
) == 1)
4544 op0
= expand_compound_operation (op0
);
4545 return gen_binary (XOR
, mode
,
4546 gen_lowpart (mode
, op0
),
4550 else if (STORE_FLAG_VALUE
== 1
4551 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4552 && op1
== const0_rtx
4553 && mode
== GET_MODE (op0
)
4554 && (num_sign_bit_copies (op0
, mode
)
4555 == GET_MODE_BITSIZE (mode
)))
4557 op0
= expand_compound_operation (op0
);
4558 return plus_constant (gen_lowpart (mode
, op0
), 1);
4561 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4563 if (STORE_FLAG_VALUE
== -1
4564 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4565 && op1
== const0_rtx
4566 && (num_sign_bit_copies (op0
, mode
)
4567 == GET_MODE_BITSIZE (mode
)))
4568 return gen_lowpart (mode
,
4569 expand_compound_operation (op0
));
4571 else if (STORE_FLAG_VALUE
== -1
4572 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4573 && op1
== const0_rtx
4574 && mode
== GET_MODE (op0
)
4575 && nonzero_bits (op0
, mode
) == 1)
4577 op0
= expand_compound_operation (op0
);
4578 return simplify_gen_unary (NEG
, mode
,
4579 gen_lowpart (mode
, op0
),
4583 else if (STORE_FLAG_VALUE
== -1
4584 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4585 && op1
== const0_rtx
4586 && mode
== GET_MODE (op0
)
4587 && (num_sign_bit_copies (op0
, mode
)
4588 == GET_MODE_BITSIZE (mode
)))
4590 op0
= expand_compound_operation (op0
);
4591 return simplify_gen_unary (NOT
, mode
,
4592 gen_lowpart (mode
, op0
),
4596 /* If X is 0/1, (eq X 0) is X-1. */
4597 else if (STORE_FLAG_VALUE
== -1
4598 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4599 && op1
== const0_rtx
4600 && mode
== GET_MODE (op0
)
4601 && nonzero_bits (op0
, mode
) == 1)
4603 op0
= expand_compound_operation (op0
);
4604 return plus_constant (gen_lowpart (mode
, op0
), -1);
4607 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4608 one bit that might be nonzero, we can convert (ne x 0) to
4609 (ashift x c) where C puts the bit in the sign bit. Remove any
4610 AND with STORE_FLAG_VALUE when we are done, since we are only
4611 going to test the sign bit. */
4612 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4613 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4614 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4615 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4616 && op1
== const0_rtx
4617 && mode
== GET_MODE (op0
)
4618 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4620 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4621 expand_compound_operation (op0
),
4622 GET_MODE_BITSIZE (mode
) - 1 - i
);
4623 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4629 /* If the code changed, return a whole new comparison. */
4630 if (new_code
!= code
)
4631 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4633 /* Otherwise, keep this operation, but maybe change its operands.
4634 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4635 SUBST (XEXP (x
, 0), op0
);
4636 SUBST (XEXP (x
, 1), op1
);
4641 return simplify_if_then_else (x
);
4647 /* If we are processing SET_DEST, we are done. */
4651 return expand_compound_operation (x
);
4654 return simplify_set (x
);
4659 return simplify_logical (x
);
4662 /* (abs (neg <foo>)) -> (abs <foo>) */
4663 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4664 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4666 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4668 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4671 /* If operand is something known to be positive, ignore the ABS. */
4672 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4673 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4674 <= HOST_BITS_PER_WIDE_INT
)
4675 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4676 & ((HOST_WIDE_INT
) 1
4677 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4681 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4682 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4683 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4688 /* (ffs (*_extend <X>)) = (ffs <X>) */
4689 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4690 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4691 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4696 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4697 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4698 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4702 /* (float (sign_extend <X>)) = (float <X>). */
4703 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4704 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4712 /* If this is a shift by a constant amount, simplify it. */
4713 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4714 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4715 INTVAL (XEXP (x
, 1)));
4717 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
4719 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4721 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4728 rtx op0
= XEXP (x
, 0);
4729 rtx op1
= XEXP (x
, 1);
4732 gcc_assert (GET_CODE (op1
) == PARALLEL
);
4733 len
= XVECLEN (op1
, 0);
4735 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4736 && GET_CODE (op0
) == VEC_CONCAT
)
4738 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4740 /* Try to find the element in the VEC_CONCAT. */
4743 if (GET_MODE (op0
) == GET_MODE (x
))
4745 if (GET_CODE (op0
) == VEC_CONCAT
)
4747 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4748 if (op0_size
< offset
)
4749 op0
= XEXP (op0
, 0);
4753 op0
= XEXP (op0
, 1);
4771 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4774 simplify_if_then_else (rtx x
)
4776 enum machine_mode mode
= GET_MODE (x
);
4777 rtx cond
= XEXP (x
, 0);
4778 rtx true_rtx
= XEXP (x
, 1);
4779 rtx false_rtx
= XEXP (x
, 2);
4780 enum rtx_code true_code
= GET_CODE (cond
);
4781 int comparison_p
= COMPARISON_P (cond
);
4784 enum rtx_code false_code
;
4787 /* Simplify storing of the truth value. */
4788 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4789 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4791 /* Also when the truth value has to be reversed. */
4793 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4794 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4798 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4799 in it is being compared against certain values. Get the true and false
4800 comparisons and see if that says anything about the value of each arm. */
4803 && ((false_code
= combine_reversed_comparison_code (cond
))
4805 && REG_P (XEXP (cond
, 0)))
4808 rtx from
= XEXP (cond
, 0);
4809 rtx true_val
= XEXP (cond
, 1);
4810 rtx false_val
= true_val
;
4813 /* If FALSE_CODE is EQ, swap the codes and arms. */
4815 if (false_code
== EQ
)
4817 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4818 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4821 /* If we are comparing against zero and the expression being tested has
4822 only a single bit that might be nonzero, that is its value when it is
4823 not equal to zero. Similarly if it is known to be -1 or 0. */
4825 if (true_code
== EQ
&& true_val
== const0_rtx
4826 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4827 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4828 else if (true_code
== EQ
&& true_val
== const0_rtx
4829 && (num_sign_bit_copies (from
, GET_MODE (from
))
4830 == GET_MODE_BITSIZE (GET_MODE (from
))))
4831 false_code
= EQ
, false_val
= constm1_rtx
;
4833 /* Now simplify an arm if we know the value of the register in the
4834 branch and it is used in the arm. Be careful due to the potential
4835 of locally-shared RTL. */
4837 if (reg_mentioned_p (from
, true_rtx
))
4838 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4840 pc_rtx
, pc_rtx
, 0, 0);
4841 if (reg_mentioned_p (from
, false_rtx
))
4842 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4844 pc_rtx
, pc_rtx
, 0, 0);
4846 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4847 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4849 true_rtx
= XEXP (x
, 1);
4850 false_rtx
= XEXP (x
, 2);
4851 true_code
= GET_CODE (cond
);
4854 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4855 reversed, do so to avoid needing two sets of patterns for
4856 subtract-and-branch insns. Similarly if we have a constant in the true
4857 arm, the false arm is the same as the first operand of the comparison, or
4858 the false arm is more complicated than the true arm. */
4861 && combine_reversed_comparison_code (cond
) != UNKNOWN
4862 && (true_rtx
== pc_rtx
4863 || (CONSTANT_P (true_rtx
)
4864 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4865 || true_rtx
== const0_rtx
4866 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
4867 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
4868 && !OBJECT_P (false_rtx
))
4869 || reg_mentioned_p (true_rtx
, false_rtx
)
4870 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4872 true_code
= reversed_comparison_code (cond
, NULL
);
4874 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4877 SUBST (XEXP (x
, 1), false_rtx
);
4878 SUBST (XEXP (x
, 2), true_rtx
);
4880 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4883 /* It is possible that the conditional has been simplified out. */
4884 true_code
= GET_CODE (cond
);
4885 comparison_p
= COMPARISON_P (cond
);
4888 /* If the two arms are identical, we don't need the comparison. */
4890 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4893 /* Convert a == b ? b : a to "a". */
4894 if (true_code
== EQ
&& ! side_effects_p (cond
)
4895 && !HONOR_NANS (mode
)
4896 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4897 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4899 else if (true_code
== NE
&& ! side_effects_p (cond
)
4900 && !HONOR_NANS (mode
)
4901 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4902 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4905 /* Look for cases where we have (abs x) or (neg (abs X)). */
4907 if (GET_MODE_CLASS (mode
) == MODE_INT
4908 && GET_CODE (false_rtx
) == NEG
4909 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4911 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4912 && ! side_effects_p (true_rtx
))
4917 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4921 simplify_gen_unary (NEG
, mode
,
4922 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4928 /* Look for MIN or MAX. */
4930 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4932 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4933 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4934 && ! side_effects_p (cond
))
4939 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4942 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4945 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4948 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4953 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4954 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4955 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4956 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4957 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4958 neither 1 or -1, but it isn't worth checking for. */
4960 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4962 && GET_MODE_CLASS (mode
) == MODE_INT
4963 && ! side_effects_p (x
))
4965 rtx t
= make_compound_operation (true_rtx
, SET
);
4966 rtx f
= make_compound_operation (false_rtx
, SET
);
4967 rtx cond_op0
= XEXP (cond
, 0);
4968 rtx cond_op1
= XEXP (cond
, 1);
4969 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
4970 enum machine_mode m
= mode
;
4971 rtx z
= 0, c1
= NULL_RTX
;
4973 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4974 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4975 || GET_CODE (t
) == ASHIFT
4976 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4977 && rtx_equal_p (XEXP (t
, 0), f
))
4978 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4980 /* If an identity-zero op is commutative, check whether there
4981 would be a match if we swapped the operands. */
4982 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4983 || GET_CODE (t
) == XOR
)
4984 && rtx_equal_p (XEXP (t
, 1), f
))
4985 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4986 else if (GET_CODE (t
) == SIGN_EXTEND
4987 && (GET_CODE (XEXP (t
, 0)) == PLUS
4988 || GET_CODE (XEXP (t
, 0)) == MINUS
4989 || GET_CODE (XEXP (t
, 0)) == IOR
4990 || GET_CODE (XEXP (t
, 0)) == XOR
4991 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4992 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4993 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4994 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4995 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4996 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4997 && (num_sign_bit_copies (f
, GET_MODE (f
))
4999 (GET_MODE_BITSIZE (mode
)
5000 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
5002 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5003 extend_op
= SIGN_EXTEND
;
5004 m
= GET_MODE (XEXP (t
, 0));
5006 else if (GET_CODE (t
) == SIGN_EXTEND
5007 && (GET_CODE (XEXP (t
, 0)) == PLUS
5008 || GET_CODE (XEXP (t
, 0)) == IOR
5009 || GET_CODE (XEXP (t
, 0)) == XOR
)
5010 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5011 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5012 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5013 && (num_sign_bit_copies (f
, GET_MODE (f
))
5015 (GET_MODE_BITSIZE (mode
)
5016 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
5018 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5019 extend_op
= SIGN_EXTEND
;
5020 m
= GET_MODE (XEXP (t
, 0));
5022 else if (GET_CODE (t
) == ZERO_EXTEND
5023 && (GET_CODE (XEXP (t
, 0)) == PLUS
5024 || GET_CODE (XEXP (t
, 0)) == MINUS
5025 || GET_CODE (XEXP (t
, 0)) == IOR
5026 || GET_CODE (XEXP (t
, 0)) == XOR
5027 || GET_CODE (XEXP (t
, 0)) == ASHIFT
5028 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
5029 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
5030 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
5031 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5032 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
5033 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
5034 && ((nonzero_bits (f
, GET_MODE (f
))
5035 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
5038 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5039 extend_op
= ZERO_EXTEND
;
5040 m
= GET_MODE (XEXP (t
, 0));
5042 else if (GET_CODE (t
) == ZERO_EXTEND
5043 && (GET_CODE (XEXP (t
, 0)) == PLUS
5044 || GET_CODE (XEXP (t
, 0)) == IOR
5045 || GET_CODE (XEXP (t
, 0)) == XOR
)
5046 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5047 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5048 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5049 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5050 && ((nonzero_bits (f
, GET_MODE (f
))
5051 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
5054 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5055 extend_op
= ZERO_EXTEND
;
5056 m
= GET_MODE (XEXP (t
, 0));
5061 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
5062 pc_rtx
, pc_rtx
, 0, 0);
5063 temp
= gen_binary (MULT
, m
, temp
,
5064 gen_binary (MULT
, m
, c1
, const_true_rtx
));
5065 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
5066 temp
= gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
5068 if (extend_op
!= UNKNOWN
)
5069 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
5075 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5076 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5077 negation of a single bit, we can convert this operation to a shift. We
5078 can actually do this more generally, but it doesn't seem worth it. */
5080 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5081 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5082 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
5083 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
5084 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
5085 == GET_MODE_BITSIZE (mode
))
5086 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
5088 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5089 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
5091 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5092 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5093 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5094 && GET_MODE (XEXP (cond
, 0)) == mode
5095 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
5096 == nonzero_bits (XEXP (cond
, 0), mode
)
5097 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
5098 return XEXP (cond
, 0);
5103 /* Simplify X, a SET expression. Return the new expression. */
5106 simplify_set (rtx x
)
5108 rtx src
= SET_SRC (x
);
5109 rtx dest
= SET_DEST (x
);
5110 enum machine_mode mode
5111 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
5115 /* (set (pc) (return)) gets written as (return). */
5116 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
5119 /* Now that we know for sure which bits of SRC we are using, see if we can
5120 simplify the expression for the object knowing that we only need the
5123 if (GET_MODE_CLASS (mode
) == MODE_INT
5124 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5126 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
5127 SUBST (SET_SRC (x
), src
);
5130 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5131 the comparison result and try to simplify it unless we already have used
5132 undobuf.other_insn. */
5133 if ((GET_MODE_CLASS (mode
) == MODE_CC
5134 || GET_CODE (src
) == COMPARE
5136 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
5137 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
5138 && COMPARISON_P (*cc_use
)
5139 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
5141 enum rtx_code old_code
= GET_CODE (*cc_use
);
5142 enum rtx_code new_code
;
5144 int other_changed
= 0;
5145 enum machine_mode compare_mode
= GET_MODE (dest
);
5147 if (GET_CODE (src
) == COMPARE
)
5148 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5150 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
5152 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
5155 new_code
= old_code
;
5156 else if (!CONSTANT_P (tmp
))
5158 new_code
= GET_CODE (tmp
);
5159 op0
= XEXP (tmp
, 0);
5160 op1
= XEXP (tmp
, 1);
5164 rtx pat
= PATTERN (other_insn
);
5165 undobuf
.other_insn
= other_insn
;
5166 SUBST (*cc_use
, tmp
);
5168 /* Attempt to simplify CC user. */
5169 if (GET_CODE (pat
) == SET
)
5171 rtx
new = simplify_rtx (SET_SRC (pat
));
5172 if (new != NULL_RTX
)
5173 SUBST (SET_SRC (pat
), new);
5176 /* Convert X into a no-op move. */
5177 SUBST (SET_DEST (x
), pc_rtx
);
5178 SUBST (SET_SRC (x
), pc_rtx
);
5182 /* Simplify our comparison, if possible. */
5183 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
5185 #ifdef SELECT_CC_MODE
5186 /* If this machine has CC modes other than CCmode, check to see if we
5187 need to use a different CC mode here. */
5188 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5189 compare_mode
= GET_MODE (op0
);
5191 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5194 /* If the mode changed, we have to change SET_DEST, the mode in the
5195 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5196 a hard register, just build new versions with the proper mode. If it
5197 is a pseudo, we lose unless it is only time we set the pseudo, in
5198 which case we can safely change its mode. */
5199 if (compare_mode
!= GET_MODE (dest
))
5201 unsigned int regno
= REGNO (dest
);
5202 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5204 if (regno
< FIRST_PSEUDO_REGISTER
5205 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5207 if (regno
>= FIRST_PSEUDO_REGISTER
)
5208 SUBST (regno_reg_rtx
[regno
], new_dest
);
5210 SUBST (SET_DEST (x
), new_dest
);
5211 SUBST (XEXP (*cc_use
, 0), new_dest
);
5218 #endif /* SELECT_CC_MODE */
5220 /* If the code changed, we have to build a new comparison in
5221 undobuf.other_insn. */
5222 if (new_code
!= old_code
)
5224 int other_changed_previously
= other_changed
;
5225 unsigned HOST_WIDE_INT mask
;
5227 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5231 /* If the only change we made was to change an EQ into an NE or
5232 vice versa, OP0 has only one bit that might be nonzero, and OP1
5233 is zero, check if changing the user of the condition code will
5234 produce a valid insn. If it won't, we can keep the original code
5235 in that insn by surrounding our operation with an XOR. */
5237 if (((old_code
== NE
&& new_code
== EQ
)
5238 || (old_code
== EQ
&& new_code
== NE
))
5239 && ! other_changed_previously
&& op1
== const0_rtx
5240 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5241 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5243 rtx pat
= PATTERN (other_insn
), note
= 0;
5245 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5246 && ! check_asm_operands (pat
)))
5248 PUT_CODE (*cc_use
, old_code
);
5251 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5257 undobuf
.other_insn
= other_insn
;
5260 /* If we are now comparing against zero, change our source if
5261 needed. If we do not use cc0, we always have a COMPARE. */
5262 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5264 SUBST (SET_SRC (x
), op0
);
5270 /* Otherwise, if we didn't previously have a COMPARE in the
5271 correct mode, we need one. */
5272 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5274 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5279 /* Otherwise, update the COMPARE if needed. */
5280 SUBST (XEXP (src
, 0), op0
);
5281 SUBST (XEXP (src
, 1), op1
);
5286 /* Get SET_SRC in a form where we have placed back any
5287 compound expressions. Then do the checks below. */
5288 src
= make_compound_operation (src
, SET
);
5289 SUBST (SET_SRC (x
), src
);
5292 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5293 and X being a REG or (subreg (reg)), we may be able to convert this to
5294 (set (subreg:m2 x) (op)).
5296 We can always do this if M1 is narrower than M2 because that means that
5297 we only care about the low bits of the result.
5299 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5300 perform a narrower operation than requested since the high-order bits will
5301 be undefined. On machine where it is defined, this transformation is safe
5302 as long as M1 and M2 have the same number of words. */
5304 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5305 && !OBJECT_P (SUBREG_REG (src
))
5306 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5308 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5309 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5310 #ifndef WORD_REGISTER_OPERATIONS
5311 && (GET_MODE_SIZE (GET_MODE (src
))
5312 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5314 #ifdef CANNOT_CHANGE_MODE_CLASS
5315 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
5316 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5317 GET_MODE (SUBREG_REG (src
)),
5321 || (GET_CODE (dest
) == SUBREG
5322 && REG_P (SUBREG_REG (dest
)))))
5324 SUBST (SET_DEST (x
),
5325 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
5327 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5329 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5333 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5336 && GET_CODE (src
) == SUBREG
5337 && subreg_lowpart_p (src
)
5338 && (GET_MODE_BITSIZE (GET_MODE (src
))
5339 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5341 rtx inner
= SUBREG_REG (src
);
5342 enum machine_mode inner_mode
= GET_MODE (inner
);
5344 /* Here we make sure that we don't have a sign bit on. */
5345 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5346 && (nonzero_bits (inner
, inner_mode
)
5347 < ((unsigned HOST_WIDE_INT
) 1
5348 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5350 SUBST (SET_SRC (x
), inner
);
5356 #ifdef LOAD_EXTEND_OP
5357 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5358 would require a paradoxical subreg. Replace the subreg with a
5359 zero_extend to avoid the reload that would otherwise be required. */
5361 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5362 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
5363 && SUBREG_BYTE (src
) == 0
5364 && (GET_MODE_SIZE (GET_MODE (src
))
5365 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5366 && MEM_P (SUBREG_REG (src
)))
5369 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5370 GET_MODE (src
), SUBREG_REG (src
)));
5376 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5377 are comparing an item known to be 0 or -1 against 0, use a logical
5378 operation instead. Check for one of the arms being an IOR of the other
5379 arm with some value. We compute three terms to be IOR'ed together. In
5380 practice, at most two will be nonzero. Then we do the IOR's. */
5382 if (GET_CODE (dest
) != PC
5383 && GET_CODE (src
) == IF_THEN_ELSE
5384 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5385 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5386 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5387 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5388 #ifdef HAVE_conditional_move
5389 && ! can_conditionally_move_p (GET_MODE (src
))
5391 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5392 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5393 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5394 && ! side_effects_p (src
))
5396 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5397 ? XEXP (src
, 1) : XEXP (src
, 2));
5398 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5399 ? XEXP (src
, 2) : XEXP (src
, 1));
5400 rtx term1
= const0_rtx
, term2
, term3
;
5402 if (GET_CODE (true_rtx
) == IOR
5403 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5404 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5405 else if (GET_CODE (true_rtx
) == IOR
5406 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5407 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5408 else if (GET_CODE (false_rtx
) == IOR
5409 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5410 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5411 else if (GET_CODE (false_rtx
) == IOR
5412 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5413 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5415 term2
= gen_binary (AND
, GET_MODE (src
),
5416 XEXP (XEXP (src
, 0), 0), true_rtx
);
5417 term3
= gen_binary (AND
, GET_MODE (src
),
5418 simplify_gen_unary (NOT
, GET_MODE (src
),
5419 XEXP (XEXP (src
, 0), 0),
5424 gen_binary (IOR
, GET_MODE (src
),
5425 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5431 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5432 whole thing fail. */
5433 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5435 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5438 /* Convert this into a field assignment operation, if possible. */
5439 return make_field_assignment (x
);
5442 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5446 simplify_logical (rtx x
)
5448 enum machine_mode mode
= GET_MODE (x
);
5449 rtx op0
= XEXP (x
, 0);
5450 rtx op1
= XEXP (x
, 1);
5453 switch (GET_CODE (x
))
5456 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5457 insn (and may simplify more). */
5458 if (GET_CODE (op0
) == XOR
5459 && rtx_equal_p (XEXP (op0
, 0), op1
)
5460 && ! side_effects_p (op1
))
5461 x
= gen_binary (AND
, mode
,
5462 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5465 if (GET_CODE (op0
) == XOR
5466 && rtx_equal_p (XEXP (op0
, 1), op1
)
5467 && ! side_effects_p (op1
))
5468 x
= gen_binary (AND
, mode
,
5469 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5472 /* Similarly for (~(A ^ B)) & A. */
5473 if (GET_CODE (op0
) == NOT
5474 && GET_CODE (XEXP (op0
, 0)) == XOR
5475 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5476 && ! side_effects_p (op1
))
5477 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5479 if (GET_CODE (op0
) == NOT
5480 && GET_CODE (XEXP (op0
, 0)) == XOR
5481 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5482 && ! side_effects_p (op1
))
5483 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5485 /* We can call simplify_and_const_int only if we don't lose
5486 any (sign) bits when converting INTVAL (op1) to
5487 "unsigned HOST_WIDE_INT". */
5488 if (GET_CODE (op1
) == CONST_INT
5489 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5490 || INTVAL (op1
) > 0))
5492 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5494 /* If we have (ior (and (X C1) C2)) and the next restart would be
5495 the last, simplify this by making C1 as small as possible
5496 and then exit. Only do this if C1 actually changes: for now
5497 this only saves memory but, should this transformation be
5498 moved to simplify-rtx.c, we'd risk unbounded recursion there. */
5499 if (GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5500 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5501 && GET_CODE (op1
) == CONST_INT
5502 && (INTVAL (XEXP (op0
, 1)) & INTVAL (op1
)) != 0)
5503 return gen_binary (IOR
, mode
,
5504 gen_binary (AND
, mode
, XEXP (op0
, 0),
5505 GEN_INT (INTVAL (XEXP (op0
, 1))
5506 & ~INTVAL (op1
))), op1
);
5508 if (GET_CODE (x
) != AND
)
5515 /* Convert (A | B) & A to A. */
5516 if (GET_CODE (op0
) == IOR
5517 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5518 || rtx_equal_p (XEXP (op0
, 1), op1
))
5519 && ! side_effects_p (XEXP (op0
, 0))
5520 && ! side_effects_p (XEXP (op0
, 1)))
5523 /* In the following group of tests (and those in case IOR below),
5524 we start with some combination of logical operations and apply
5525 the distributive law followed by the inverse distributive law.
5526 Most of the time, this results in no change. However, if some of
5527 the operands are the same or inverses of each other, simplifications
5530 For example, (and (ior A B) (not B)) can occur as the result of
5531 expanding a bit field assignment. When we apply the distributive
5532 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5533 which then simplifies to (and (A (not B))).
5535 If we have (and (ior A B) C), apply the distributive law and then
5536 the inverse distributive law to see if things simplify. */
5538 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5540 x
= apply_distributive_law
5541 (gen_binary (GET_CODE (op0
), mode
,
5542 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5543 gen_binary (AND
, mode
, XEXP (op0
, 1),
5545 if (GET_CODE (x
) != AND
)
5549 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5550 return apply_distributive_law
5551 (gen_binary (GET_CODE (op1
), mode
,
5552 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5553 gen_binary (AND
, mode
, XEXP (op1
, 1),
5556 /* Similarly, taking advantage of the fact that
5557 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5559 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5560 return apply_distributive_law
5561 (gen_binary (XOR
, mode
,
5562 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5563 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5566 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5567 return apply_distributive_law
5568 (gen_binary (XOR
, mode
,
5569 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5570 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5574 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5575 if (GET_CODE (op1
) == CONST_INT
5576 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5577 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5580 /* Convert (A & B) | A to A. */
5581 if (GET_CODE (op0
) == AND
5582 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5583 || rtx_equal_p (XEXP (op0
, 1), op1
))
5584 && ! side_effects_p (XEXP (op0
, 0))
5585 && ! side_effects_p (XEXP (op0
, 1)))
5588 /* If we have (ior (and A B) C), apply the distributive law and then
5589 the inverse distributive law to see if things simplify. */
5591 if (GET_CODE (op0
) == AND
)
5593 rtx tmp
= apply_distributive_law
5594 (gen_binary (AND
, mode
,
5595 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5596 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5599 if (GET_CODE (tmp
) != IOR
5600 && rtx_cost (tmp
, SET
) < rtx_cost (x
, SET
))
5604 if (GET_CODE (op1
) == AND
)
5606 rtx tmp
= apply_distributive_law
5607 (gen_binary (AND
, mode
,
5608 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5609 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5612 if (GET_CODE (tmp
) != IOR
5613 && rtx_cost (tmp
, SET
) < rtx_cost (x
, SET
))
5617 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5618 mode size to (rotate A CX). */
5620 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5621 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5622 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5623 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5624 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5625 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5626 == GET_MODE_BITSIZE (mode
)))
5627 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5628 (GET_CODE (op0
) == ASHIFT
5629 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5631 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5632 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5633 does not affect any of the bits in OP1, it can really be done
5634 as a PLUS and we can associate. We do this by seeing if OP1
5635 can be safely shifted left C bits. */
5636 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5637 && GET_CODE (XEXP (op0
, 0)) == PLUS
5638 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5639 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5640 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5642 int count
= INTVAL (XEXP (op0
, 1));
5643 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5645 if (mask
>> count
== INTVAL (op1
)
5646 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5648 SUBST (XEXP (XEXP (op0
, 0), 1),
5649 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5656 /* If we are XORing two things that have no bits in common,
5657 convert them into an IOR. This helps to detect rotation encoded
5658 using those methods and possibly other simplifications. */
5660 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5661 && (nonzero_bits (op0
, mode
)
5662 & nonzero_bits (op1
, mode
)) == 0)
5663 return (gen_binary (IOR
, mode
, op0
, op1
));
5665 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5666 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5669 int num_negated
= 0;
5671 if (GET_CODE (op0
) == NOT
)
5672 num_negated
++, op0
= XEXP (op0
, 0);
5673 if (GET_CODE (op1
) == NOT
)
5674 num_negated
++, op1
= XEXP (op1
, 0);
5676 if (num_negated
== 2)
5678 SUBST (XEXP (x
, 0), op0
);
5679 SUBST (XEXP (x
, 1), op1
);
5681 else if (num_negated
== 1)
5683 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5687 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5688 correspond to a machine insn or result in further simplifications
5689 if B is a constant. */
5691 if (GET_CODE (op0
) == AND
5692 && rtx_equal_p (XEXP (op0
, 1), op1
)
5693 && ! side_effects_p (op1
))
5694 return gen_binary (AND
, mode
,
5695 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5698 else if (GET_CODE (op0
) == AND
5699 && rtx_equal_p (XEXP (op0
, 0), op1
)
5700 && ! side_effects_p (op1
))
5701 return gen_binary (AND
, mode
,
5702 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5705 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5706 comparison if STORE_FLAG_VALUE is 1. */
5707 if (STORE_FLAG_VALUE
== 1
5708 && op1
== const1_rtx
5709 && COMPARISON_P (op0
)
5710 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5714 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5715 is (lt foo (const_int 0)), so we can perform the above
5716 simplification if STORE_FLAG_VALUE is 1. */
5718 if (STORE_FLAG_VALUE
== 1
5719 && op1
== const1_rtx
5720 && GET_CODE (op0
) == LSHIFTRT
5721 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5722 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5723 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5725 /* (xor (comparison foo bar) (const_int sign-bit))
5726 when STORE_FLAG_VALUE is the sign bit. */
5727 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5728 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5729 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5730 && op1
== const_true_rtx
5731 && COMPARISON_P (op0
)
5732 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5745 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5746 operations" because they can be replaced with two more basic operations.
5747 ZERO_EXTEND is also considered "compound" because it can be replaced with
5748 an AND operation, which is simpler, though only one operation.
5750 The function expand_compound_operation is called with an rtx expression
5751 and will convert it to the appropriate shifts and AND operations,
5752 simplifying at each stage.
5754 The function make_compound_operation is called to convert an expression
5755 consisting of shifts and ANDs into the equivalent compound expression.
5756 It is the inverse of this function, loosely speaking. */
5759 expand_compound_operation (rtx x
)
5761 unsigned HOST_WIDE_INT pos
= 0, len
;
5763 unsigned int modewidth
;
5766 switch (GET_CODE (x
))
5771 /* We can't necessarily use a const_int for a multiword mode;
5772 it depends on implicitly extending the value.
5773 Since we don't know the right way to extend it,
5774 we can't tell whether the implicit way is right.
5776 Even for a mode that is no wider than a const_int,
5777 we can't win, because we need to sign extend one of its bits through
5778 the rest of it, and we don't know which bit. */
5779 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5782 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5783 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5784 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5785 reloaded. If not for that, MEM's would very rarely be safe.
5787 Reject MODEs bigger than a word, because we might not be able
5788 to reference a two-register group starting with an arbitrary register
5789 (and currently gen_lowpart might crash for a SUBREG). */
5791 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5794 /* Reject MODEs that aren't scalar integers because turning vector
5795 or complex modes into shifts causes problems. */
5797 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5800 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5801 /* If the inner object has VOIDmode (the only way this can happen
5802 is if it is an ASM_OPERANDS), we can't do anything since we don't
5803 know how much masking to do. */
5812 /* ... fall through ... */
5815 /* If the operand is a CLOBBER, just return it. */
5816 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5819 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5820 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5821 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5824 /* Reject MODEs that aren't scalar integers because turning vector
5825 or complex modes into shifts causes problems. */
5827 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5830 len
= INTVAL (XEXP (x
, 1));
5831 pos
= INTVAL (XEXP (x
, 2));
5833 /* If this goes outside the object being extracted, replace the object
5834 with a (use (mem ...)) construct that only combine understands
5835 and is used only for this purpose. */
5836 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5837 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5839 if (BITS_BIG_ENDIAN
)
5840 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5847 /* Convert sign extension to zero extension, if we know that the high
5848 bit is not set, as this is easier to optimize. It will be converted
5849 back to cheaper alternative in make_extraction. */
5850 if (GET_CODE (x
) == SIGN_EXTEND
5851 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5852 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5853 & ~(((unsigned HOST_WIDE_INT
)
5854 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5858 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5859 rtx temp2
= expand_compound_operation (temp
);
5861 /* Make sure this is a profitable operation. */
5862 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
5864 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
5870 /* We can optimize some special cases of ZERO_EXTEND. */
5871 if (GET_CODE (x
) == ZERO_EXTEND
)
5873 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5874 know that the last value didn't have any inappropriate bits
5876 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5877 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5878 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5879 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5880 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5881 return XEXP (XEXP (x
, 0), 0);
5883 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5884 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5885 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5886 && subreg_lowpart_p (XEXP (x
, 0))
5887 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5888 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5889 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5890 return SUBREG_REG (XEXP (x
, 0));
5892 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5893 is a comparison and STORE_FLAG_VALUE permits. This is like
5894 the first case, but it works even when GET_MODE (x) is larger
5895 than HOST_WIDE_INT. */
5896 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5897 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5898 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
5899 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5900 <= HOST_BITS_PER_WIDE_INT
)
5901 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5902 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5903 return XEXP (XEXP (x
, 0), 0);
5905 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5906 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5907 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5908 && subreg_lowpart_p (XEXP (x
, 0))
5909 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
5910 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5911 <= HOST_BITS_PER_WIDE_INT
)
5912 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5913 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5914 return SUBREG_REG (XEXP (x
, 0));
5918 /* If we reach here, we want to return a pair of shifts. The inner
5919 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5920 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5921 logical depending on the value of UNSIGNEDP.
5923 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5924 converted into an AND of a shift.
5926 We must check for the case where the left shift would have a negative
5927 count. This can happen in a case like (x >> 31) & 255 on machines
5928 that can't shift by a constant. On those machines, we would first
5929 combine the shift with the AND to produce a variable-position
5930 extraction. Then the constant of 31 would be substituted in to produce
5931 a such a position. */
5933 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5934 if (modewidth
+ len
>= pos
)
5935 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5937 simplify_shift_const (NULL_RTX
, ASHIFT
,
5940 modewidth
- pos
- len
),
5943 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5944 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5945 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5948 ((HOST_WIDE_INT
) 1 << len
) - 1);
5950 /* Any other cases we can't handle. */
5953 /* If we couldn't do this for some reason, return the original
5955 if (GET_CODE (tem
) == CLOBBER
)
5961 /* X is a SET which contains an assignment of one object into
5962 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5963 or certain SUBREGS). If possible, convert it into a series of
5966 We half-heartedly support variable positions, but do not at all
5967 support variable lengths. */
5970 expand_field_assignment (rtx x
)
5973 rtx pos
; /* Always counts from low bit. */
5976 enum machine_mode compute_mode
;
5978 /* Loop until we find something we can't simplify. */
5981 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5982 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5984 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5985 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5986 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5988 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5989 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5991 inner
= XEXP (SET_DEST (x
), 0);
5992 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5993 pos
= XEXP (SET_DEST (x
), 2);
5995 /* If the position is constant and spans the width of INNER,
5996 surround INNER with a USE to indicate this. */
5997 if (GET_CODE (pos
) == CONST_INT
5998 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5999 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
6001 if (BITS_BIG_ENDIAN
)
6003 if (GET_CODE (pos
) == CONST_INT
)
6004 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
6006 else if (GET_CODE (pos
) == MINUS
6007 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
6008 && (INTVAL (XEXP (pos
, 1))
6009 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
6010 /* If position is ADJUST - X, new position is X. */
6011 pos
= XEXP (pos
, 0);
6013 pos
= gen_binary (MINUS
, GET_MODE (pos
),
6014 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
6020 /* A SUBREG between two modes that occupy the same numbers of words
6021 can be done by moving the SUBREG to the source. */
6022 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6023 /* We need SUBREGs to compute nonzero_bits properly. */
6024 && nonzero_sign_valid
6025 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6026 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6027 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6028 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6030 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6032 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6039 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6040 inner
= SUBREG_REG (inner
);
6042 compute_mode
= GET_MODE (inner
);
6044 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6045 if (! SCALAR_INT_MODE_P (compute_mode
))
6047 enum machine_mode imode
;
6049 /* Don't do anything for vector or complex integral types. */
6050 if (! FLOAT_MODE_P (compute_mode
))
6053 /* Try to find an integral mode to pun with. */
6054 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6055 if (imode
== BLKmode
)
6058 compute_mode
= imode
;
6059 inner
= gen_lowpart (imode
, inner
);
6062 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6063 if (len
< HOST_BITS_PER_WIDE_INT
)
6064 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
6068 /* Now compute the equivalent expression. Make a copy of INNER
6069 for the SET_DEST in case it is a MEM into which we will substitute;
6070 we don't want shared RTL in that case. */
6072 (VOIDmode
, copy_rtx (inner
),
6073 gen_binary (IOR
, compute_mode
,
6074 gen_binary (AND
, compute_mode
,
6075 simplify_gen_unary (NOT
, compute_mode
,
6081 gen_binary (ASHIFT
, compute_mode
,
6082 gen_binary (AND
, compute_mode
,
6084 (compute_mode
, SET_SRC (x
)),
6092 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6093 it is an RTX that represents a variable starting position; otherwise,
6094 POS is the (constant) starting bit position (counted from the LSB).
6096 INNER may be a USE. This will occur when we started with a bitfield
6097 that went outside the boundary of the object in memory, which is
6098 allowed on most machines. To isolate this case, we produce a USE
6099 whose mode is wide enough and surround the MEM with it. The only
6100 code that understands the USE is this routine. If it is not removed,
6101 it will cause the resulting insn not to match.
6103 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6106 IN_DEST is nonzero if this is a reference in the destination of a
6107 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6108 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6111 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6112 ZERO_EXTRACT should be built even for bits starting at bit 0.
6114 MODE is the desired mode of the result (if IN_DEST == 0).
6116 The result is an RTX for the extraction or NULL_RTX if the target
6120 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
6121 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
6122 int in_dest
, int in_compare
)
6124 /* This mode describes the size of the storage area
6125 to fetch the overall value from. Within that, we
6126 ignore the POS lowest bits, etc. */
6127 enum machine_mode is_mode
= GET_MODE (inner
);
6128 enum machine_mode inner_mode
;
6129 enum machine_mode wanted_inner_mode
= byte_mode
;
6130 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6131 enum machine_mode pos_mode
= word_mode
;
6132 enum machine_mode extraction_mode
= word_mode
;
6133 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6136 rtx orig_pos_rtx
= pos_rtx
;
6137 HOST_WIDE_INT orig_pos
;
6139 /* Get some information about INNER and get the innermost object. */
6140 if (GET_CODE (inner
) == USE
)
6141 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6142 /* We don't need to adjust the position because we set up the USE
6143 to pretend that it was a full-word object. */
6144 spans_byte
= 1, inner
= XEXP (inner
, 0);
6145 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6147 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6148 consider just the QI as the memory to extract from.
6149 The subreg adds or removes high bits; its mode is
6150 irrelevant to the meaning of this extraction,
6151 since POS and LEN count from the lsb. */
6152 if (MEM_P (SUBREG_REG (inner
)))
6153 is_mode
= GET_MODE (SUBREG_REG (inner
));
6154 inner
= SUBREG_REG (inner
);
6156 else if (GET_CODE (inner
) == ASHIFT
6157 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
6158 && pos_rtx
== 0 && pos
== 0
6159 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6161 /* We're extracting the least significant bits of an rtx
6162 (ashift X (const_int C)), where LEN > C. Extract the
6163 least significant (LEN - C) bits of X, giving an rtx
6164 whose mode is MODE, then shift it left C times. */
6165 new = make_extraction (mode
, XEXP (inner
, 0),
6166 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6167 unsignedp
, in_dest
, in_compare
);
6169 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
6172 inner_mode
= GET_MODE (inner
);
6174 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6175 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6177 /* See if this can be done without an extraction. We never can if the
6178 width of the field is not the same as that of some integer mode. For
6179 registers, we can only avoid the extraction if the position is at the
6180 low-order bit and this is either not in the destination or we have the
6181 appropriate STRICT_LOW_PART operation available.
6183 For MEM, we can avoid an extract if the field starts on an appropriate
6184 boundary and we can change the mode of the memory reference. However,
6185 we cannot directly access the MEM if we have a USE and the underlying
6186 MEM is not TMODE. This combination means that MEM was being used in a
6187 context where bits outside its mode were being referenced; that is only
6188 valid in bit-field insns. */
6190 if (tmode
!= BLKmode
6191 && ! (spans_byte
&& inner_mode
!= tmode
)
6192 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6196 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6197 || (MEM_P (inner
) && pos_rtx
== 0
6199 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6200 : BITS_PER_UNIT
)) == 0
6201 /* We can't do this if we are widening INNER_MODE (it
6202 may not be aligned, for one thing). */
6203 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6204 && (inner_mode
== tmode
6205 || (! mode_dependent_address_p (XEXP (inner
, 0))
6206 && ! MEM_VOLATILE_P (inner
))))))
6208 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6209 field. If the original and current mode are the same, we need not
6210 adjust the offset. Otherwise, we do if bytes big endian.
6212 If INNER is not a MEM, get a piece consisting of just the field
6213 of interest (in this case POS % BITS_PER_WORD must be 0). */
6217 HOST_WIDE_INT offset
;
6219 /* POS counts from lsb, but make OFFSET count in memory order. */
6220 if (BYTES_BIG_ENDIAN
)
6221 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6223 offset
= pos
/ BITS_PER_UNIT
;
6225 new = adjust_address_nv (inner
, tmode
, offset
);
6227 else if (REG_P (inner
))
6229 if (tmode
!= inner_mode
)
6231 /* We can't call gen_lowpart in a DEST since we
6232 always want a SUBREG (see below) and it would sometimes
6233 return a new hard register. */
6236 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6238 if (WORDS_BIG_ENDIAN
6239 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6240 final_word
= ((GET_MODE_SIZE (inner_mode
)
6241 - GET_MODE_SIZE (tmode
))
6242 / UNITS_PER_WORD
) - final_word
;
6244 final_word
*= UNITS_PER_WORD
;
6245 if (BYTES_BIG_ENDIAN
&&
6246 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6247 final_word
+= (GET_MODE_SIZE (inner_mode
)
6248 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6250 /* Avoid creating invalid subregs, for example when
6251 simplifying (x>>32)&255. */
6252 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6255 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6258 new = gen_lowpart (tmode
, inner
);
6264 new = force_to_mode (inner
, tmode
,
6265 len
>= HOST_BITS_PER_WIDE_INT
6266 ? ~(unsigned HOST_WIDE_INT
) 0
6267 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6270 /* If this extraction is going into the destination of a SET,
6271 make a STRICT_LOW_PART unless we made a MEM. */
6274 return (MEM_P (new) ? new
6275 : (GET_CODE (new) != SUBREG
6276 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6277 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6282 if (GET_CODE (new) == CONST_INT
)
6283 return gen_int_mode (INTVAL (new), mode
);
6285 /* If we know that no extraneous bits are set, and that the high
6286 bit is not set, convert the extraction to the cheaper of
6287 sign and zero extension, that are equivalent in these cases. */
6288 if (flag_expensive_optimizations
6289 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6290 && ((nonzero_bits (new, tmode
)
6291 & ~(((unsigned HOST_WIDE_INT
)
6292 GET_MODE_MASK (tmode
))
6296 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6297 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6299 /* Prefer ZERO_EXTENSION, since it gives more information to
6301 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6306 /* Otherwise, sign- or zero-extend unless we already are in the
6309 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6313 /* Unless this is a COMPARE or we have a funny memory reference,
6314 don't do anything with zero-extending field extracts starting at
6315 the low-order bit since they are simple AND operations. */
6316 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6317 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6320 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6321 we would be spanning bytes or if the position is not a constant and the
6322 length is not 1. In all other cases, we would only be going outside
6323 our object in cases when an original shift would have been
6325 if (! spans_byte
&& MEM_P (inner
)
6326 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6327 || (pos_rtx
!= 0 && len
!= 1)))
6330 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6331 and the mode for the result. */
6332 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6334 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6335 pos_mode
= mode_for_extraction (EP_insv
, 2);
6336 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6339 if (! in_dest
&& unsignedp
6340 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6342 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6343 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6344 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6347 if (! in_dest
&& ! unsignedp
6348 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6350 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6351 pos_mode
= mode_for_extraction (EP_extv
, 3);
6352 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6355 /* Never narrow an object, since that might not be safe. */
6357 if (mode
!= VOIDmode
6358 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6359 extraction_mode
= mode
;
6361 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6362 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6363 pos_mode
= GET_MODE (pos_rtx
);
6365 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6366 if we have to change the mode of memory and cannot, the desired mode is
6369 wanted_inner_mode
= wanted_inner_reg_mode
;
6370 else if (inner_mode
!= wanted_inner_mode
6371 && (mode_dependent_address_p (XEXP (inner
, 0))
6372 || MEM_VOLATILE_P (inner
)))
6373 wanted_inner_mode
= extraction_mode
;
6377 if (BITS_BIG_ENDIAN
)
6379 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6380 BITS_BIG_ENDIAN style. If position is constant, compute new
6381 position. Otherwise, build subtraction.
6382 Note that POS is relative to the mode of the original argument.
6383 If it's a MEM we need to recompute POS relative to that.
6384 However, if we're extracting from (or inserting into) a register,
6385 we want to recompute POS relative to wanted_inner_mode. */
6386 int width
= (MEM_P (inner
)
6387 ? GET_MODE_BITSIZE (is_mode
)
6388 : GET_MODE_BITSIZE (wanted_inner_mode
));
6391 pos
= width
- len
- pos
;
6394 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6395 /* POS may be less than 0 now, but we check for that below.
6396 Note that it can only be less than 0 if !MEM_P (inner). */
6399 /* If INNER has a wider mode, make it smaller. If this is a constant
6400 extract, try to adjust the byte to point to the byte containing
6402 if (wanted_inner_mode
!= VOIDmode
6403 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6405 && (inner_mode
== wanted_inner_mode
6406 || (! mode_dependent_address_p (XEXP (inner
, 0))
6407 && ! MEM_VOLATILE_P (inner
))))))
6411 /* The computations below will be correct if the machine is big
6412 endian in both bits and bytes or little endian in bits and bytes.
6413 If it is mixed, we must adjust. */
6415 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6416 adjust OFFSET to compensate. */
6417 if (BYTES_BIG_ENDIAN
6419 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6420 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6422 /* If this is a constant position, we can move to the desired byte. */
6425 offset
+= pos
/ BITS_PER_UNIT
;
6426 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6429 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6431 && is_mode
!= wanted_inner_mode
)
6432 offset
= (GET_MODE_SIZE (is_mode
)
6433 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6435 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6436 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6439 /* If INNER is not memory, we can always get it into the proper mode. If we
6440 are changing its mode, POS must be a constant and smaller than the size
6442 else if (!MEM_P (inner
))
6444 if (GET_MODE (inner
) != wanted_inner_mode
6446 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6449 inner
= force_to_mode (inner
, wanted_inner_mode
,
6451 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6452 ? ~(unsigned HOST_WIDE_INT
) 0
6453 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6458 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6459 have to zero extend. Otherwise, we can just use a SUBREG. */
6461 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6463 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6465 /* If we know that no extraneous bits are set, and that the high
6466 bit is not set, convert extraction to cheaper one - either
6467 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6469 if (flag_expensive_optimizations
6470 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6471 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6472 & ~(((unsigned HOST_WIDE_INT
)
6473 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6477 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6479 /* Prefer ZERO_EXTENSION, since it gives more information to
6481 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6486 else if (pos_rtx
!= 0
6487 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6488 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
6490 /* Make POS_RTX unless we already have it and it is correct. If we don't
6491 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6493 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6494 pos_rtx
= orig_pos_rtx
;
6496 else if (pos_rtx
== 0)
6497 pos_rtx
= GEN_INT (pos
);
6499 /* Make the required operation. See if we can use existing rtx. */
6500 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6501 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6503 new = gen_lowpart (mode
, new);
6508 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6509 with any other operations in X. Return X without that shift if so. */
6512 extract_left_shift (rtx x
, int count
)
6514 enum rtx_code code
= GET_CODE (x
);
6515 enum machine_mode mode
= GET_MODE (x
);
6521 /* This is the shift itself. If it is wide enough, we will return
6522 either the value being shifted if the shift count is equal to
6523 COUNT or a shift for the difference. */
6524 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6525 && INTVAL (XEXP (x
, 1)) >= count
)
6526 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6527 INTVAL (XEXP (x
, 1)) - count
);
6531 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6532 return simplify_gen_unary (code
, mode
, tem
, mode
);
6536 case PLUS
: case IOR
: case XOR
: case AND
:
6537 /* If we can safely shift this constant and we find the inner shift,
6538 make a new operation. */
6539 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6540 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6541 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6542 return gen_binary (code
, mode
, tem
,
6543 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6554 /* Look at the expression rooted at X. Look for expressions
6555 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6556 Form these expressions.
6558 Return the new rtx, usually just X.
6560 Also, for machines like the VAX that don't have logical shift insns,
6561 try to convert logical to arithmetic shift operations in cases where
6562 they are equivalent. This undoes the canonicalizations to logical
6563 shifts done elsewhere.
6565 We try, as much as possible, to re-use rtl expressions to save memory.
6567 IN_CODE says what kind of expression we are processing. Normally, it is
6568 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6569 being kludges), it is MEM. When processing the arguments of a comparison
6570 or a COMPARE against zero, it is COMPARE. */
6573 make_compound_operation (rtx x
, enum rtx_code in_code
)
6575 enum rtx_code code
= GET_CODE (x
);
6576 enum machine_mode mode
= GET_MODE (x
);
6577 int mode_width
= GET_MODE_BITSIZE (mode
);
6579 enum rtx_code next_code
;
6585 /* Select the code to be used in recursive calls. Once we are inside an
6586 address, we stay there. If we have a comparison, set to COMPARE,
6587 but once inside, go back to our default of SET. */
6589 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6590 : ((code
== COMPARE
|| COMPARISON_P (x
))
6591 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6592 : in_code
== COMPARE
? SET
: in_code
);
6594 /* Process depending on the code of this operation. If NEW is set
6595 nonzero, it will be returned. */
6600 /* Convert shifts by constants into multiplications if inside
6602 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6603 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6604 && INTVAL (XEXP (x
, 1)) >= 0)
6606 new = make_compound_operation (XEXP (x
, 0), next_code
);
6607 new = gen_rtx_MULT (mode
, new,
6608 GEN_INT ((HOST_WIDE_INT
) 1
6609 << INTVAL (XEXP (x
, 1))));
6614 /* If the second operand is not a constant, we can't do anything
6616 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6619 /* If the constant is a power of two minus one and the first operand
6620 is a logical right shift, make an extraction. */
6621 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6622 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6624 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6625 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6626 0, in_code
== COMPARE
);
6629 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6630 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6631 && subreg_lowpart_p (XEXP (x
, 0))
6632 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6633 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6635 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6637 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6638 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6639 0, in_code
== COMPARE
);
6641 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6642 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6643 || GET_CODE (XEXP (x
, 0)) == IOR
)
6644 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6645 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6646 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6648 /* Apply the distributive law, and then try to make extractions. */
6649 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6650 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6652 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6654 new = make_compound_operation (new, in_code
);
6657 /* If we are have (and (rotate X C) M) and C is larger than the number
6658 of bits in M, this is an extraction. */
6660 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6661 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6662 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6663 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6665 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6666 new = make_extraction (mode
, new,
6667 (GET_MODE_BITSIZE (mode
)
6668 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6669 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6672 /* On machines without logical shifts, if the operand of the AND is
6673 a logical shift and our mask turns off all the propagated sign
6674 bits, we can replace the logical shift with an arithmetic shift. */
6675 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6676 && !have_insn_for (LSHIFTRT
, mode
)
6677 && have_insn_for (ASHIFTRT
, mode
)
6678 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6679 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6680 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6681 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6683 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6685 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6686 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6688 gen_rtx_ASHIFTRT (mode
,
6689 make_compound_operation
6690 (XEXP (XEXP (x
, 0), 0), next_code
),
6691 XEXP (XEXP (x
, 0), 1)));
6694 /* If the constant is one less than a power of two, this might be
6695 representable by an extraction even if no shift is present.
6696 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6697 we are in a COMPARE. */
6698 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6699 new = make_extraction (mode
,
6700 make_compound_operation (XEXP (x
, 0),
6702 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6704 /* If we are in a comparison and this is an AND with a power of two,
6705 convert this into the appropriate bit extract. */
6706 else if (in_code
== COMPARE
6707 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6708 new = make_extraction (mode
,
6709 make_compound_operation (XEXP (x
, 0),
6711 i
, NULL_RTX
, 1, 1, 0, 1);
6716 /* If the sign bit is known to be zero, replace this with an
6717 arithmetic shift. */
6718 if (have_insn_for (ASHIFTRT
, mode
)
6719 && ! have_insn_for (LSHIFTRT
, mode
)
6720 && mode_width
<= HOST_BITS_PER_WIDE_INT
6721 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6723 new = gen_rtx_ASHIFTRT (mode
,
6724 make_compound_operation (XEXP (x
, 0),
6730 /* ... fall through ... */
6736 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6737 this is a SIGN_EXTRACT. */
6738 if (GET_CODE (rhs
) == CONST_INT
6739 && GET_CODE (lhs
) == ASHIFT
6740 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6741 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6743 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6744 new = make_extraction (mode
, new,
6745 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6746 NULL_RTX
, mode_width
- INTVAL (rhs
),
6747 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6751 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6752 If so, try to merge the shifts into a SIGN_EXTEND. We could
6753 also do this for some cases of SIGN_EXTRACT, but it doesn't
6754 seem worth the effort; the case checked for occurs on Alpha. */
6757 && ! (GET_CODE (lhs
) == SUBREG
6758 && (OBJECT_P (SUBREG_REG (lhs
))))
6759 && GET_CODE (rhs
) == CONST_INT
6760 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6761 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6762 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6763 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6764 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6769 /* Call ourselves recursively on the inner expression. If we are
6770 narrowing the object and it has a different RTL code from
6771 what it originally did, do this SUBREG as a force_to_mode. */
6773 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6774 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6775 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6776 && subreg_lowpart_p (x
))
6778 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6781 /* If we have something other than a SUBREG, we might have
6782 done an expansion, so rerun ourselves. */
6783 if (GET_CODE (newer
) != SUBREG
)
6784 newer
= make_compound_operation (newer
, in_code
);
6789 /* If this is a paradoxical subreg, and the new code is a sign or
6790 zero extension, omit the subreg and widen the extension. If it
6791 is a regular subreg, we can still get rid of the subreg by not
6792 widening so much, or in fact removing the extension entirely. */
6793 if ((GET_CODE (tem
) == SIGN_EXTEND
6794 || GET_CODE (tem
) == ZERO_EXTEND
)
6795 && subreg_lowpart_p (x
))
6797 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6798 || (GET_MODE_SIZE (mode
) >
6799 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6801 if (! SCALAR_INT_MODE_P (mode
))
6803 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6806 tem
= gen_lowpart (mode
, XEXP (tem
, 0));
6817 x
= gen_lowpart (mode
, new);
6818 code
= GET_CODE (x
);
6821 /* Now recursively process each operand of this operation. */
6822 fmt
= GET_RTX_FORMAT (code
);
6823 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6826 new = make_compound_operation (XEXP (x
, i
), next_code
);
6827 SUBST (XEXP (x
, i
), new);
6833 /* Given M see if it is a value that would select a field of bits
6834 within an item, but not the entire word. Return -1 if not.
6835 Otherwise, return the starting position of the field, where 0 is the
6838 *PLEN is set to the length of the field. */
6841 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
6843 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6844 int pos
= exact_log2 (m
& -m
);
6848 /* Now shift off the low-order zero bits and see if we have a
6849 power of two minus 1. */
6850 len
= exact_log2 ((m
>> pos
) + 1);
6859 /* See if X can be simplified knowing that we will only refer to it in
6860 MODE and will only refer to those bits that are nonzero in MASK.
6861 If other bits are being computed or if masking operations are done
6862 that select a superset of the bits in MASK, they can sometimes be
6865 Return a possibly simplified expression, but always convert X to
6866 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6868 Also, if REG is nonzero and X is a register equal in value to REG,
6871 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6872 are all off in X. This is used when X will be complemented, by either
6873 NOT, NEG, or XOR. */
6876 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
6877 rtx reg
, int just_select
)
6879 enum rtx_code code
= GET_CODE (x
);
6880 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6881 enum machine_mode op_mode
;
6882 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6885 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6886 code below will do the wrong thing since the mode of such an
6887 expression is VOIDmode.
6889 Also do nothing if X is a CLOBBER; this can happen if X was
6890 the return value from a call to gen_lowpart. */
6891 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6894 /* We want to perform the operation is its present mode unless we know
6895 that the operation is valid in MODE, in which case we do the operation
6897 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6898 && have_insn_for (code
, mode
))
6899 ? mode
: GET_MODE (x
));
6901 /* It is not valid to do a right-shift in a narrower mode
6902 than the one it came in with. */
6903 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6904 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6905 op_mode
= GET_MODE (x
);
6907 /* Truncate MASK to fit OP_MODE. */
6909 mask
&= GET_MODE_MASK (op_mode
);
6911 /* When we have an arithmetic operation, or a shift whose count we
6912 do not know, we need to assume that all bits up to the highest-order
6913 bit in MASK will be needed. This is how we form such a mask. */
6914 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
6915 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
6917 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6920 /* Determine what bits of X are guaranteed to be (non)zero. */
6921 nonzero
= nonzero_bits (x
, mode
);
6923 /* If none of the bits in X are needed, return a zero. */
6924 if (! just_select
&& (nonzero
& mask
) == 0)
6927 /* If X is a CONST_INT, return a new one. Do this here since the
6928 test below will fail. */
6929 if (GET_CODE (x
) == CONST_INT
)
6931 if (SCALAR_INT_MODE_P (mode
))
6932 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6935 x
= GEN_INT (INTVAL (x
) & mask
);
6936 return gen_lowpart_common (mode
, x
);
6940 /* If X is narrower than MODE and we want all the bits in X's mode, just
6941 get X in the proper mode. */
6942 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6943 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6944 return gen_lowpart (mode
, x
);
6949 /* If X is a (clobber (const_int)), return it since we know we are
6950 generating something that won't match. */
6954 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6955 spanned the boundary of the MEM. If we are now masking so it is
6956 within that boundary, we don't need the USE any more. */
6957 if (! BITS_BIG_ENDIAN
6958 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6959 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6966 x
= expand_compound_operation (x
);
6967 if (GET_CODE (x
) != code
)
6968 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6972 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6973 || rtx_equal_p (reg
, get_last_value (x
))))
6978 if (subreg_lowpart_p (x
)
6979 /* We can ignore the effect of this SUBREG if it narrows the mode or
6980 if the constant masks to zero all the bits the mode doesn't
6982 && ((GET_MODE_SIZE (GET_MODE (x
))
6983 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6985 & GET_MODE_MASK (GET_MODE (x
))
6986 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6987 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6991 /* If this is an AND with a constant, convert it into an AND
6992 whose constant is the AND of that constant with MASK. If it
6993 remains an AND of MASK, delete it since it is redundant. */
6995 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6997 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6998 mask
& INTVAL (XEXP (x
, 1)));
7000 /* If X is still an AND, see if it is an AND with a mask that
7001 is just some low-order bits. If so, and it is MASK, we don't
7004 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
7005 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
7009 /* If it remains an AND, try making another AND with the bits
7010 in the mode mask that aren't in MASK turned on. If the
7011 constant in the AND is wide enough, this might make a
7012 cheaper constant. */
7014 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
7015 && GET_MODE_MASK (GET_MODE (x
)) != mask
7016 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
7018 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
7019 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
7020 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
7023 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7024 number, sign extend it. */
7025 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
7026 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
7027 cval
|= (HOST_WIDE_INT
) -1 << width
;
7029 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
7030 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
7040 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7041 low-order bits (as in an alignment operation) and FOO is already
7042 aligned to that boundary, mask C1 to that boundary as well.
7043 This may eliminate that PLUS and, later, the AND. */
7046 unsigned int width
= GET_MODE_BITSIZE (mode
);
7047 unsigned HOST_WIDE_INT smask
= mask
;
7049 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7050 number, sign extend it. */
7052 if (width
< HOST_BITS_PER_WIDE_INT
7053 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
7054 smask
|= (HOST_WIDE_INT
) -1 << width
;
7056 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7057 && exact_log2 (- smask
) >= 0
7058 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
7059 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
7060 return force_to_mode (plus_constant (XEXP (x
, 0),
7061 (INTVAL (XEXP (x
, 1)) & smask
)),
7062 mode
, smask
, reg
, next_select
);
7065 /* ... fall through ... */
7068 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7069 most significant bit in MASK since carries from those bits will
7070 affect the bits we are interested in. */
7075 /* If X is (minus C Y) where C's least set bit is larger than any bit
7076 in the mask, then we may replace with (neg Y). */
7077 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7078 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
7079 & -INTVAL (XEXP (x
, 0))))
7082 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
7084 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7087 /* Similarly, if C contains every bit in the fuller_mask, then we may
7088 replace with (not Y). */
7089 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7090 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
7091 == INTVAL (XEXP (x
, 0))))
7093 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
7094 XEXP (x
, 1), GET_MODE (x
));
7095 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7103 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7104 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7105 operation which may be a bitfield extraction. Ensure that the
7106 constant we form is not wider than the mode of X. */
7108 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7109 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7110 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7111 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7112 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7113 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
7114 + floor_log2 (INTVAL (XEXP (x
, 1))))
7115 < GET_MODE_BITSIZE (GET_MODE (x
)))
7116 && (INTVAL (XEXP (x
, 1))
7117 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
7119 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
7120 << INTVAL (XEXP (XEXP (x
, 0), 1)));
7121 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
7122 XEXP (XEXP (x
, 0), 0), temp
);
7123 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
7124 XEXP (XEXP (x
, 0), 1));
7125 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7129 /* For most binary operations, just propagate into the operation and
7130 change the mode if we have an operation of that mode. */
7132 op0
= gen_lowpart (op_mode
,
7133 force_to_mode (XEXP (x
, 0), mode
, mask
,
7135 op1
= gen_lowpart (op_mode
,
7136 force_to_mode (XEXP (x
, 1), mode
, mask
,
7139 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7140 x
= gen_binary (code
, op_mode
, op0
, op1
);
7144 /* For left shifts, do the same, but just for the first operand.
7145 However, we cannot do anything with shifts where we cannot
7146 guarantee that the counts are smaller than the size of the mode
7147 because such a count will have a different meaning in a
7150 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7151 && INTVAL (XEXP (x
, 1)) >= 0
7152 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7153 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7154 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7155 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7158 /* If the shift count is a constant and we can do arithmetic in
7159 the mode of the shift, refine which bits we need. Otherwise, use the
7160 conservative form of the mask. */
7161 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7162 && INTVAL (XEXP (x
, 1)) >= 0
7163 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7164 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7165 mask
>>= INTVAL (XEXP (x
, 1));
7169 op0
= gen_lowpart (op_mode
,
7170 force_to_mode (XEXP (x
, 0), op_mode
,
7171 mask
, reg
, next_select
));
7173 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7174 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7178 /* Here we can only do something if the shift count is a constant,
7179 this shift constant is valid for the host, and we can do arithmetic
7182 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7183 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7184 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7186 rtx inner
= XEXP (x
, 0);
7187 unsigned HOST_WIDE_INT inner_mask
;
7189 /* Select the mask of the bits we need for the shift operand. */
7190 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7192 /* We can only change the mode of the shift if we can do arithmetic
7193 in the mode of the shift and INNER_MASK is no wider than the
7194 width of X's mode. */
7195 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
7196 op_mode
= GET_MODE (x
);
7198 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7200 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7201 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7204 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7205 shift and AND produces only copies of the sign bit (C2 is one less
7206 than a power of two), we can do this with just a shift. */
7208 if (GET_CODE (x
) == LSHIFTRT
7209 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7210 /* The shift puts one of the sign bit copies in the least significant
7212 && ((INTVAL (XEXP (x
, 1))
7213 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7214 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7215 && exact_log2 (mask
+ 1) >= 0
7216 /* Number of bits left after the shift must be more than the mask
7218 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7219 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7220 /* Must be more sign bit copies than the mask needs. */
7221 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7222 >= exact_log2 (mask
+ 1)))
7223 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7224 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7225 - exact_log2 (mask
+ 1)));
7230 /* If we are just looking for the sign bit, we don't need this shift at
7231 all, even if it has a variable count. */
7232 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7233 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7234 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7235 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7237 /* If this is a shift by a constant, get a mask that contains those bits
7238 that are not copies of the sign bit. We then have two cases: If
7239 MASK only includes those bits, this can be a logical shift, which may
7240 allow simplifications. If MASK is a single-bit field not within
7241 those bits, we are requesting a copy of the sign bit and hence can
7242 shift the sign bit to the appropriate location. */
7244 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7245 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7249 /* If the considered data is wider than HOST_WIDE_INT, we can't
7250 represent a mask for all its bits in a single scalar.
7251 But we only care about the lower bits, so calculate these. */
7253 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7255 nonzero
= ~(HOST_WIDE_INT
) 0;
7257 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7258 is the number of bits a full-width mask would have set.
7259 We need only shift if these are fewer than nonzero can
7260 hold. If not, we must keep all bits set in nonzero. */
7262 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7263 < HOST_BITS_PER_WIDE_INT
)
7264 nonzero
>>= INTVAL (XEXP (x
, 1))
7265 + HOST_BITS_PER_WIDE_INT
7266 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7270 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7271 nonzero
>>= INTVAL (XEXP (x
, 1));
7274 if ((mask
& ~nonzero
) == 0
7275 || (i
= exact_log2 (mask
)) >= 0)
7277 x
= simplify_shift_const
7278 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7279 i
< 0 ? INTVAL (XEXP (x
, 1))
7280 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7282 if (GET_CODE (x
) != ASHIFTRT
)
7283 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7287 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7288 even if the shift count isn't a constant. */
7290 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7294 /* If this is a zero- or sign-extension operation that just affects bits
7295 we don't care about, remove it. Be sure the call above returned
7296 something that is still a shift. */
7298 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7299 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7300 && INTVAL (XEXP (x
, 1)) >= 0
7301 && (INTVAL (XEXP (x
, 1))
7302 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7303 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7304 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7305 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7312 /* If the shift count is constant and we can do computations
7313 in the mode of X, compute where the bits we care about are.
7314 Otherwise, we can't do anything. Don't change the mode of
7315 the shift or propagate MODE into the shift, though. */
7316 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7317 && INTVAL (XEXP (x
, 1)) >= 0)
7319 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7320 GET_MODE (x
), GEN_INT (mask
),
7322 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7324 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7325 INTVAL (temp
), reg
, next_select
));
7330 /* If we just want the low-order bit, the NEG isn't needed since it
7331 won't change the low-order bit. */
7333 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7335 /* We need any bits less significant than the most significant bit in
7336 MASK since carries from those bits will affect the bits we are
7342 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7343 same as the XOR case above. Ensure that the constant we form is not
7344 wider than the mode of X. */
7346 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7347 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7348 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7349 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7350 < GET_MODE_BITSIZE (GET_MODE (x
)))
7351 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7353 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7355 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7356 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7358 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7361 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7362 use the full mask inside the NOT. */
7366 op0
= gen_lowpart (op_mode
,
7367 force_to_mode (XEXP (x
, 0), mode
, mask
,
7369 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7370 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7374 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7375 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7376 which is equal to STORE_FLAG_VALUE. */
7377 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7378 && GET_MODE (XEXP (x
, 0)) == mode
7379 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7380 && (nonzero_bits (XEXP (x
, 0), mode
)
7381 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7382 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7387 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7388 written in a narrower mode. We play it safe and do not do so. */
7391 gen_lowpart (GET_MODE (x
),
7392 force_to_mode (XEXP (x
, 1), mode
,
7393 mask
, reg
, next_select
)));
7395 gen_lowpart (GET_MODE (x
),
7396 force_to_mode (XEXP (x
, 2), mode
,
7397 mask
, reg
, next_select
)));
7404 /* Ensure we return a value of the proper mode. */
7405 return gen_lowpart (mode
, x
);
7408 /* Return nonzero if X is an expression that has one of two values depending on
7409 whether some other value is zero or nonzero. In that case, we return the
7410 value that is being tested, *PTRUE is set to the value if the rtx being
7411 returned has a nonzero value, and *PFALSE is set to the other alternative.
7413 If we return zero, we set *PTRUE and *PFALSE to X. */
7416 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7418 enum machine_mode mode
= GET_MODE (x
);
7419 enum rtx_code code
= GET_CODE (x
);
7420 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7421 unsigned HOST_WIDE_INT nz
;
7423 /* If we are comparing a value against zero, we are done. */
7424 if ((code
== NE
|| code
== EQ
)
7425 && XEXP (x
, 1) == const0_rtx
)
7427 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7428 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7432 /* If this is a unary operation whose operand has one of two values, apply
7433 our opcode to compute those values. */
7434 else if (UNARY_P (x
)
7435 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7437 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7438 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7439 GET_MODE (XEXP (x
, 0)));
7443 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7444 make can't possibly match and would suppress other optimizations. */
7445 else if (code
== COMPARE
)
7448 /* If this is a binary operation, see if either side has only one of two
7449 values. If either one does or if both do and they are conditional on
7450 the same value, compute the new true and false values. */
7451 else if (BINARY_P (x
))
7453 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7454 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7456 if ((cond0
!= 0 || cond1
!= 0)
7457 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7459 /* If if_then_else_cond returned zero, then true/false are the
7460 same rtl. We must copy one of them to prevent invalid rtl
7463 true0
= copy_rtx (true0
);
7464 else if (cond1
== 0)
7465 true1
= copy_rtx (true1
);
7467 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7468 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7469 return cond0
? cond0
: cond1
;
7472 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7473 operands is zero when the other is nonzero, and vice-versa,
7474 and STORE_FLAG_VALUE is 1 or -1. */
7476 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7477 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7479 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7481 rtx op0
= XEXP (XEXP (x
, 0), 1);
7482 rtx op1
= XEXP (XEXP (x
, 1), 1);
7484 cond0
= XEXP (XEXP (x
, 0), 0);
7485 cond1
= XEXP (XEXP (x
, 1), 0);
7487 if (COMPARISON_P (cond0
)
7488 && COMPARISON_P (cond1
)
7489 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7490 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7491 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7492 || ((swap_condition (GET_CODE (cond0
))
7493 == combine_reversed_comparison_code (cond1
))
7494 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7495 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7496 && ! side_effects_p (x
))
7498 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7499 *pfalse
= gen_binary (MULT
, mode
,
7501 ? simplify_gen_unary (NEG
, mode
, op1
,
7509 /* Similarly for MULT, AND and UMIN, except that for these the result
7511 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7512 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7513 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7515 cond0
= XEXP (XEXP (x
, 0), 0);
7516 cond1
= XEXP (XEXP (x
, 1), 0);
7518 if (COMPARISON_P (cond0
)
7519 && COMPARISON_P (cond1
)
7520 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7521 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7522 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7523 || ((swap_condition (GET_CODE (cond0
))
7524 == combine_reversed_comparison_code (cond1
))
7525 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7526 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7527 && ! side_effects_p (x
))
7529 *ptrue
= *pfalse
= const0_rtx
;
7535 else if (code
== IF_THEN_ELSE
)
7537 /* If we have IF_THEN_ELSE already, extract the condition and
7538 canonicalize it if it is NE or EQ. */
7539 cond0
= XEXP (x
, 0);
7540 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7541 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7542 return XEXP (cond0
, 0);
7543 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7545 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7546 return XEXP (cond0
, 0);
7552 /* If X is a SUBREG, we can narrow both the true and false values
7553 if the inner expression, if there is a condition. */
7554 else if (code
== SUBREG
7555 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7558 true0
= simplify_gen_subreg (mode
, true0
,
7559 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7560 false0
= simplify_gen_subreg (mode
, false0
,
7561 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7562 if (true0
&& false0
)
7570 /* If X is a constant, this isn't special and will cause confusions
7571 if we treat it as such. Likewise if it is equivalent to a constant. */
7572 else if (CONSTANT_P (x
)
7573 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7576 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7577 will be least confusing to the rest of the compiler. */
7578 else if (mode
== BImode
)
7580 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7584 /* If X is known to be either 0 or -1, those are the true and
7585 false values when testing X. */
7586 else if (x
== constm1_rtx
|| x
== const0_rtx
7587 || (mode
!= VOIDmode
7588 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7590 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7594 /* Likewise for 0 or a single bit. */
7595 else if (SCALAR_INT_MODE_P (mode
)
7596 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7597 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7599 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7603 /* Otherwise fail; show no condition with true and false values the same. */
7604 *ptrue
= *pfalse
= x
;
7608 /* Return the value of expression X given the fact that condition COND
7609 is known to be true when applied to REG as its first operand and VAL
7610 as its second. X is known to not be shared and so can be modified in
7613 We only handle the simplest cases, and specifically those cases that
7614 arise with IF_THEN_ELSE expressions. */
7617 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7619 enum rtx_code code
= GET_CODE (x
);
7624 if (side_effects_p (x
))
7627 /* If either operand of the condition is a floating point value,
7628 then we have to avoid collapsing an EQ comparison. */
7630 && rtx_equal_p (x
, reg
)
7631 && ! FLOAT_MODE_P (GET_MODE (x
))
7632 && ! FLOAT_MODE_P (GET_MODE (val
)))
7635 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7638 /* If X is (abs REG) and we know something about REG's relationship
7639 with zero, we may be able to simplify this. */
7641 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7644 case GE
: case GT
: case EQ
:
7647 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7649 GET_MODE (XEXP (x
, 0)));
7654 /* The only other cases we handle are MIN, MAX, and comparisons if the
7655 operands are the same as REG and VAL. */
7657 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
7659 if (rtx_equal_p (XEXP (x
, 0), val
))
7660 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7662 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7664 if (COMPARISON_P (x
))
7666 if (comparison_dominates_p (cond
, code
))
7667 return const_true_rtx
;
7669 code
= combine_reversed_comparison_code (x
);
7671 && comparison_dominates_p (cond
, code
))
7676 else if (code
== SMAX
|| code
== SMIN
7677 || code
== UMIN
|| code
== UMAX
)
7679 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7681 /* Do not reverse the condition when it is NE or EQ.
7682 This is because we cannot conclude anything about
7683 the value of 'SMAX (x, y)' when x is not equal to y,
7684 but we can when x equals y. */
7685 if ((code
== SMAX
|| code
== UMAX
)
7686 && ! (cond
== EQ
|| cond
== NE
))
7687 cond
= reverse_condition (cond
);
7692 return unsignedp
? x
: XEXP (x
, 1);
7694 return unsignedp
? x
: XEXP (x
, 0);
7696 return unsignedp
? XEXP (x
, 1) : x
;
7698 return unsignedp
? XEXP (x
, 0) : x
;
7705 else if (code
== SUBREG
)
7707 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7708 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7710 if (SUBREG_REG (x
) != r
)
7712 /* We must simplify subreg here, before we lose track of the
7713 original inner_mode. */
7714 new = simplify_subreg (GET_MODE (x
), r
,
7715 inner_mode
, SUBREG_BYTE (x
));
7719 SUBST (SUBREG_REG (x
), r
);
7724 /* We don't have to handle SIGN_EXTEND here, because even in the
7725 case of replacing something with a modeless CONST_INT, a
7726 CONST_INT is already (supposed to be) a valid sign extension for
7727 its narrower mode, which implies it's already properly
7728 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7729 story is different. */
7730 else if (code
== ZERO_EXTEND
)
7732 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7733 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7735 if (XEXP (x
, 0) != r
)
7737 /* We must simplify the zero_extend here, before we lose
7738 track of the original inner_mode. */
7739 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7744 SUBST (XEXP (x
, 0), r
);
7750 fmt
= GET_RTX_FORMAT (code
);
7751 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7754 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7755 else if (fmt
[i
] == 'E')
7756 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7757 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7764 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7765 assignment as a field assignment. */
7768 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
7770 if (x
== y
|| rtx_equal_p (x
, y
))
7773 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7776 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7777 Note that all SUBREGs of MEM are paradoxical; otherwise they
7778 would have been rewritten. */
7779 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
7780 && MEM_P (SUBREG_REG (y
))
7781 && rtx_equal_p (SUBREG_REG (y
),
7782 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
7785 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
7786 && MEM_P (SUBREG_REG (x
))
7787 && rtx_equal_p (SUBREG_REG (x
),
7788 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
7791 /* We used to see if get_last_value of X and Y were the same but that's
7792 not correct. In one direction, we'll cause the assignment to have
7793 the wrong destination and in the case, we'll import a register into this
7794 insn that might have already have been dead. So fail if none of the
7795 above cases are true. */
7799 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7800 Return that assignment if so.
7802 We only handle the most common cases. */
7805 make_field_assignment (rtx x
)
7807 rtx dest
= SET_DEST (x
);
7808 rtx src
= SET_SRC (x
);
7813 unsigned HOST_WIDE_INT len
;
7815 enum machine_mode mode
;
7817 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7818 a clear of a one-bit field. We will have changed it to
7819 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7822 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7823 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7824 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7825 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7827 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7830 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7834 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7835 && subreg_lowpart_p (XEXP (src
, 0))
7836 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7837 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7838 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7839 && GET_CODE (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == CONST_INT
7840 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7841 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7843 assign
= make_extraction (VOIDmode
, dest
, 0,
7844 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7847 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7851 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7853 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7854 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7855 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7857 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7860 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7864 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7865 SRC is an AND with all bits of that field set, then we can discard
7867 if (GET_CODE (dest
) == ZERO_EXTRACT
7868 && GET_CODE (XEXP (dest
, 1)) == CONST_INT
7869 && GET_CODE (src
) == AND
7870 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
7872 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
7873 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
7874 unsigned HOST_WIDE_INT ze_mask
;
7876 if (width
>= HOST_BITS_PER_WIDE_INT
)
7879 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
7881 /* Complete overlap. We can remove the source AND. */
7882 if ((and_mask
& ze_mask
) == ze_mask
)
7883 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
7885 /* Partial overlap. We can reduce the source AND. */
7886 if ((and_mask
& ze_mask
) != and_mask
)
7888 mode
= GET_MODE (src
);
7889 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
7890 gen_int_mode (and_mask
& ze_mask
, mode
));
7891 return gen_rtx_SET (VOIDmode
, dest
, src
);
7895 /* The other case we handle is assignments into a constant-position
7896 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7897 a mask that has all one bits except for a group of zero bits and
7898 OTHER is known to have zeros where C1 has ones, this is such an
7899 assignment. Compute the position and length from C1. Shift OTHER
7900 to the appropriate position, force it to the required mode, and
7901 make the extraction. Check for the AND in both operands. */
7903 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7906 rhs
= expand_compound_operation (XEXP (src
, 0));
7907 lhs
= expand_compound_operation (XEXP (src
, 1));
7909 if (GET_CODE (rhs
) == AND
7910 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7911 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7912 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7913 else if (GET_CODE (lhs
) == AND
7914 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7915 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7916 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7920 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7921 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7922 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7923 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7926 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7930 /* The mode to use for the source is the mode of the assignment, or of
7931 what is inside a possible STRICT_LOW_PART. */
7932 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7933 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7935 /* Shift OTHER right POS places and make it the source, restricting it
7936 to the proper length and mode. */
7938 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7939 GET_MODE (src
), other
, pos
),
7941 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7942 ? ~(unsigned HOST_WIDE_INT
) 0
7943 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7946 /* If SRC is masked by an AND that does not make a difference in
7947 the value being stored, strip it. */
7948 if (GET_CODE (assign
) == ZERO_EXTRACT
7949 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
7950 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
7951 && GET_CODE (src
) == AND
7952 && GET_CODE (XEXP (src
, 1)) == CONST_INT
7953 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
7954 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
7955 src
= XEXP (src
, 0);
7957 return gen_rtx_SET (VOIDmode
, assign
, src
);
7960 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7964 apply_distributive_law (rtx x
)
7966 enum rtx_code code
= GET_CODE (x
);
7967 enum rtx_code inner_code
;
7968 rtx lhs
, rhs
, other
;
7971 /* Distributivity is not true for floating point as it can change the
7972 value. So we don't do it unless -funsafe-math-optimizations. */
7973 if (FLOAT_MODE_P (GET_MODE (x
))
7974 && ! flag_unsafe_math_optimizations
)
7977 /* The outer operation can only be one of the following: */
7978 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7979 && code
!= PLUS
&& code
!= MINUS
)
7985 /* If either operand is a primitive we can't do anything, so get out
7987 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
7990 lhs
= expand_compound_operation (lhs
);
7991 rhs
= expand_compound_operation (rhs
);
7992 inner_code
= GET_CODE (lhs
);
7993 if (inner_code
!= GET_CODE (rhs
))
7996 /* See if the inner and outer operations distribute. */
8003 /* These all distribute except over PLUS. */
8004 if (code
== PLUS
|| code
== MINUS
)
8009 if (code
!= PLUS
&& code
!= MINUS
)
8014 /* This is also a multiply, so it distributes over everything. */
8018 /* Non-paradoxical SUBREGs distributes over all operations, provided
8019 the inner modes and byte offsets are the same, this is an extraction
8020 of a low-order part, we don't convert an fp operation to int or
8021 vice versa, and we would not be converting a single-word
8022 operation into a multi-word operation. The latter test is not
8023 required, but it prevents generating unneeded multi-word operations.
8024 Some of the previous tests are redundant given the latter test, but
8025 are retained because they are required for correctness.
8027 We produce the result slightly differently in this case. */
8029 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
8030 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
8031 || ! subreg_lowpart_p (lhs
)
8032 || (GET_MODE_CLASS (GET_MODE (lhs
))
8033 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
8034 || (GET_MODE_SIZE (GET_MODE (lhs
))
8035 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
8036 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
8039 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
8040 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
8041 return gen_lowpart (GET_MODE (x
), tem
);
8047 /* Set LHS and RHS to the inner operands (A and B in the example
8048 above) and set OTHER to the common operand (C in the example).
8049 There is only one way to do this unless the inner operation is
8051 if (COMMUTATIVE_ARITH_P (lhs
)
8052 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
8053 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
8054 else if (COMMUTATIVE_ARITH_P (lhs
)
8055 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
8056 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
8057 else if (COMMUTATIVE_ARITH_P (lhs
)
8058 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
8059 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
8060 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
8061 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
8065 /* Form the new inner operation, seeing if it simplifies first. */
8066 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
8068 /* There is one exception to the general way of distributing:
8069 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8070 if (code
== XOR
&& inner_code
== IOR
)
8073 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
8076 /* We may be able to continuing distributing the result, so call
8077 ourselves recursively on the inner operation before forming the
8078 outer operation, which we return. */
8079 return gen_binary (inner_code
, GET_MODE (x
),
8080 apply_distributive_law (tem
), other
);
8083 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8086 Return an equivalent form, if different from X. Otherwise, return X. If
8087 X is zero, we are to always construct the equivalent form. */
8090 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
8091 unsigned HOST_WIDE_INT constop
)
8093 unsigned HOST_WIDE_INT nonzero
;
8096 /* Simplify VAROP knowing that we will be only looking at some of the
8099 Note by passing in CONSTOP, we guarantee that the bits not set in
8100 CONSTOP are not significant and will never be examined. We must
8101 ensure that is the case by explicitly masking out those bits
8102 before returning. */
8103 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
8105 /* If VAROP is a CLOBBER, we will fail so return it. */
8106 if (GET_CODE (varop
) == CLOBBER
)
8109 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8110 to VAROP and return the new constant. */
8111 if (GET_CODE (varop
) == CONST_INT
)
8112 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
8114 /* See what bits may be nonzero in VAROP. Unlike the general case of
8115 a call to nonzero_bits, here we don't care about bits outside
8118 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
8120 /* Turn off all bits in the constant that are known to already be zero.
8121 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8122 which is tested below. */
8126 /* If we don't have any bits left, return zero. */
8130 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8131 a power of two, we can replace this with an ASHIFT. */
8132 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
8133 && (i
= exact_log2 (constop
)) >= 0)
8134 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
8136 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8137 or XOR, then try to apply the distributive law. This may eliminate
8138 operations if either branch can be simplified because of the AND.
8139 It may also make some cases more complex, but those cases probably
8140 won't match a pattern either with or without this. */
8142 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
8146 apply_distributive_law
8147 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
8148 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
8149 XEXP (varop
, 0), constop
),
8150 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
8151 XEXP (varop
, 1), constop
))));
8153 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8154 the AND and see if one of the operands simplifies to zero. If so, we
8155 may eliminate it. */
8157 if (GET_CODE (varop
) == PLUS
8158 && exact_log2 (constop
+ 1) >= 0)
8162 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
8163 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
8164 if (o0
== const0_rtx
)
8166 if (o1
== const0_rtx
)
8170 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8171 if we already had one (just check for the simplest cases). */
8172 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
8173 && GET_MODE (XEXP (x
, 0)) == mode
8174 && SUBREG_REG (XEXP (x
, 0)) == varop
)
8175 varop
= XEXP (x
, 0);
8177 varop
= gen_lowpart (mode
, varop
);
8179 /* If we can't make the SUBREG, try to return what we were given. */
8180 if (GET_CODE (varop
) == CLOBBER
)
8181 return x
? x
: varop
;
8183 /* If we are only masking insignificant bits, return VAROP. */
8184 if (constop
== nonzero
)
8188 /* Otherwise, return an AND. */
8189 constop
= trunc_int_for_mode (constop
, mode
);
8190 /* See how much, if any, of X we can use. */
8191 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
8192 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
8196 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8197 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
8198 SUBST (XEXP (x
, 1), GEN_INT (constop
));
8200 SUBST (XEXP (x
, 0), varop
);
8207 /* Given a REG, X, compute which bits in X can be nonzero.
8208 We don't care about bits outside of those defined in MODE.
8210 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8211 a shift, AND, or zero_extract, we can do better. */
8214 reg_nonzero_bits_for_combine (rtx x
, enum machine_mode mode
,
8215 rtx known_x ATTRIBUTE_UNUSED
,
8216 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
8217 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
8218 unsigned HOST_WIDE_INT
*nonzero
)
8222 /* If X is a register whose nonzero bits value is current, use it.
8223 Otherwise, if X is a register whose value we can find, use that
8224 value. Otherwise, use the previously-computed global nonzero bits
8225 for this register. */
8227 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8228 && (reg_stat
[REGNO (x
)].last_set_mode
== mode
8229 || (GET_MODE_CLASS (reg_stat
[REGNO (x
)].last_set_mode
) == MODE_INT
8230 && GET_MODE_CLASS (mode
) == MODE_INT
))
8231 && (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8232 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8233 && REG_N_SETS (REGNO (x
)) == 1
8234 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8236 && INSN_CUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_cuid
)
8238 *nonzero
&= reg_stat
[REGNO (x
)].last_set_nonzero_bits
;
8242 tem
= get_last_value (x
);
8246 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8247 /* If X is narrower than MODE and TEM is a non-negative
8248 constant that would appear negative in the mode of X,
8249 sign-extend it for use in reg_nonzero_bits because some
8250 machines (maybe most) will actually do the sign-extension
8251 and this is the conservative approach.
8253 ??? For 2.5, try to tighten up the MD files in this regard
8254 instead of this kludge. */
8256 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
)
8257 && GET_CODE (tem
) == CONST_INT
8259 && 0 != (INTVAL (tem
)
8260 & ((HOST_WIDE_INT
) 1
8261 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8262 tem
= GEN_INT (INTVAL (tem
)
8263 | ((HOST_WIDE_INT
) (-1)
8264 << GET_MODE_BITSIZE (GET_MODE (x
))));
8268 else if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].nonzero_bits
)
8270 unsigned HOST_WIDE_INT mask
= reg_stat
[REGNO (x
)].nonzero_bits
;
8272 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
))
8273 /* We don't know anything about the upper bits. */
8274 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8281 /* Return the number of bits at the high-order end of X that are known to
8282 be equal to the sign bit. X will be used in mode MODE; if MODE is
8283 VOIDmode, X will be used in its own mode. The returned value will always
8284 be between 1 and the number of bits in MODE. */
8287 reg_num_sign_bit_copies_for_combine (rtx x
, enum machine_mode mode
,
8288 rtx known_x ATTRIBUTE_UNUSED
,
8289 enum machine_mode known_mode
8291 unsigned int known_ret ATTRIBUTE_UNUSED
,
8292 unsigned int *result
)
8296 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8297 && reg_stat
[REGNO (x
)].last_set_mode
== mode
8298 && (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8299 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8300 && REG_N_SETS (REGNO (x
)) == 1
8301 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8303 && INSN_CUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_cuid
)
8305 *result
= reg_stat
[REGNO (x
)].last_set_sign_bit_copies
;
8309 tem
= get_last_value (x
);
8313 if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].sign_bit_copies
!= 0
8314 && GET_MODE_BITSIZE (GET_MODE (x
)) == GET_MODE_BITSIZE (mode
))
8315 *result
= reg_stat
[REGNO (x
)].sign_bit_copies
;
8320 /* Return the number of "extended" bits there are in X, when interpreted
8321 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8322 unsigned quantities, this is the number of high-order zero bits.
8323 For signed quantities, this is the number of copies of the sign bit
8324 minus 1. In both case, this function returns the number of "spare"
8325 bits. For example, if two quantities for which this function returns
8326 at least 1 are added, the addition is known not to overflow.
8328 This function will always return 0 unless called during combine, which
8329 implies that it must be called from a define_split. */
8332 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
8334 if (nonzero_sign_valid
== 0)
8338 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8339 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8340 - floor_log2 (nonzero_bits (x
, mode
)))
8342 : num_sign_bit_copies (x
, mode
) - 1);
8345 /* This function is called from `simplify_shift_const' to merge two
8346 outer operations. Specifically, we have already found that we need
8347 to perform operation *POP0 with constant *PCONST0 at the outermost
8348 position. We would now like to also perform OP1 with constant CONST1
8349 (with *POP0 being done last).
8351 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8352 the resulting operation. *PCOMP_P is set to 1 if we would need to
8353 complement the innermost operand, otherwise it is unchanged.
8355 MODE is the mode in which the operation will be done. No bits outside
8356 the width of this mode matter. It is assumed that the width of this mode
8357 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8359 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8360 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8361 result is simply *PCONST0.
8363 If the resulting operation cannot be expressed as one operation, we
8364 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8367 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
8369 enum rtx_code op0
= *pop0
;
8370 HOST_WIDE_INT const0
= *pconst0
;
8372 const0
&= GET_MODE_MASK (mode
);
8373 const1
&= GET_MODE_MASK (mode
);
8375 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8379 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8382 if (op1
== UNKNOWN
|| op0
== SET
)
8385 else if (op0
== UNKNOWN
)
8386 op0
= op1
, const0
= const1
;
8388 else if (op0
== op1
)
8412 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8413 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8416 /* If the two constants aren't the same, we can't do anything. The
8417 remaining six cases can all be done. */
8418 else if (const0
!= const1
)
8426 /* (a & b) | b == b */
8428 else /* op1 == XOR */
8429 /* (a ^ b) | b == a | b */
8435 /* (a & b) ^ b == (~a) & b */
8436 op0
= AND
, *pcomp_p
= 1;
8437 else /* op1 == IOR */
8438 /* (a | b) ^ b == a & ~b */
8439 op0
= AND
, const0
= ~const0
;
8444 /* (a | b) & b == b */
8446 else /* op1 == XOR */
8447 /* (a ^ b) & b) == (~a) & b */
8454 /* Check for NO-OP cases. */
8455 const0
&= GET_MODE_MASK (mode
);
8457 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8459 else if (const0
== 0 && op0
== AND
)
8461 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8465 /* ??? Slightly redundant with the above mask, but not entirely.
8466 Moving this above means we'd have to sign-extend the mode mask
8467 for the final test. */
8468 const0
= trunc_int_for_mode (const0
, mode
);
8476 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8477 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
8478 that we started with.
8480 The shift is normally computed in the widest mode we find in VAROP, as
8481 long as it isn't a different number of words than RESULT_MODE. Exceptions
8482 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8485 simplify_shift_const (rtx x
, enum rtx_code code
,
8486 enum machine_mode result_mode
, rtx varop
,
8489 enum rtx_code orig_code
= code
;
8492 enum machine_mode mode
= result_mode
;
8493 enum machine_mode shift_mode
, tmode
;
8494 unsigned int mode_words
8495 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8496 /* We form (outer_op (code varop count) (outer_const)). */
8497 enum rtx_code outer_op
= UNKNOWN
;
8498 HOST_WIDE_INT outer_const
= 0;
8500 int complement_p
= 0;
8503 /* Make sure and truncate the "natural" shift on the way in. We don't
8504 want to do this inside the loop as it makes it more difficult to
8506 if (SHIFT_COUNT_TRUNCATED
)
8507 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
8509 /* If we were given an invalid count, don't do anything except exactly
8510 what was requested. */
8512 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
8517 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
8522 /* Unless one of the branches of the `if' in this loop does a `continue',
8523 we will `break' the loop after the `if'. */
8527 /* If we have an operand of (clobber (const_int 0)), just return that
8529 if (GET_CODE (varop
) == CLOBBER
)
8532 /* If we discovered we had to complement VAROP, leave. Making a NOT
8533 here would cause an infinite loop. */
8537 /* Convert ROTATERT to ROTATE. */
8538 if (code
== ROTATERT
)
8540 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
8542 if (VECTOR_MODE_P (result_mode
))
8543 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
8545 count
= bitsize
- count
;
8548 /* We need to determine what mode we will do the shift in. If the
8549 shift is a right shift or a ROTATE, we must always do it in the mode
8550 it was originally done in. Otherwise, we can do it in MODE, the
8551 widest mode encountered. */
8553 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8554 ? result_mode
: mode
);
8556 /* Handle cases where the count is greater than the size of the mode
8557 minus 1. For ASHIFT, use the size minus one as the count (this can
8558 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8559 take the count modulo the size. For other shifts, the result is
8562 Since these shifts are being produced by the compiler by combining
8563 multiple operations, each of which are defined, we know what the
8564 result is supposed to be. */
8566 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
8568 if (code
== ASHIFTRT
)
8569 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8570 else if (code
== ROTATE
|| code
== ROTATERT
)
8571 count
%= GET_MODE_BITSIZE (shift_mode
);
8574 /* We can't simply return zero because there may be an
8582 /* An arithmetic right shift of a quantity known to be -1 or 0
8584 if (code
== ASHIFTRT
8585 && (num_sign_bit_copies (varop
, shift_mode
)
8586 == GET_MODE_BITSIZE (shift_mode
)))
8592 /* If we are doing an arithmetic right shift and discarding all but
8593 the sign bit copies, this is equivalent to doing a shift by the
8594 bitsize minus one. Convert it into that shift because it will often
8595 allow other simplifications. */
8597 if (code
== ASHIFTRT
8598 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
8599 >= GET_MODE_BITSIZE (shift_mode
)))
8600 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8602 /* We simplify the tests below and elsewhere by converting
8603 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8604 `make_compound_operation' will convert it to an ASHIFTRT for
8605 those machines (such as VAX) that don't have an LSHIFTRT. */
8606 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8608 && ((nonzero_bits (varop
, shift_mode
)
8609 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
8613 if (code
== LSHIFTRT
8614 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8615 && !(nonzero_bits (varop
, shift_mode
) >> count
))
8618 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8619 && !((nonzero_bits (varop
, shift_mode
) << count
)
8620 & GET_MODE_MASK (shift_mode
)))
8623 switch (GET_CODE (varop
))
8629 new = expand_compound_operation (varop
);
8638 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8639 minus the width of a smaller mode, we can do this with a
8640 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8641 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8642 && ! mode_dependent_address_p (XEXP (varop
, 0))
8643 && ! MEM_VOLATILE_P (varop
)
8644 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8645 MODE_INT
, 1)) != BLKmode
)
8647 new = adjust_address_nv (varop
, tmode
,
8648 BYTES_BIG_ENDIAN
? 0
8649 : count
/ BITS_PER_UNIT
);
8651 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8652 : ZERO_EXTEND
, mode
, new);
8659 /* Similar to the case above, except that we can only do this if
8660 the resulting mode is the same as that of the underlying
8661 MEM and adjust the address depending on the *bits* endianness
8662 because of the way that bit-field extract insns are defined. */
8663 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8664 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8665 MODE_INT
, 1)) != BLKmode
8666 && tmode
== GET_MODE (XEXP (varop
, 0)))
8668 if (BITS_BIG_ENDIAN
)
8669 new = XEXP (varop
, 0);
8672 new = copy_rtx (XEXP (varop
, 0));
8673 SUBST (XEXP (new, 0),
8674 plus_constant (XEXP (new, 0),
8675 count
/ BITS_PER_UNIT
));
8678 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8679 : ZERO_EXTEND
, mode
, new);
8686 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8687 the same number of words as what we've seen so far. Then store
8688 the widest mode in MODE. */
8689 if (subreg_lowpart_p (varop
)
8690 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8691 > GET_MODE_SIZE (GET_MODE (varop
)))
8692 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8693 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
8696 varop
= SUBREG_REG (varop
);
8697 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
8698 mode
= GET_MODE (varop
);
8704 /* Some machines use MULT instead of ASHIFT because MULT
8705 is cheaper. But it is still better on those machines to
8706 merge two shifts into one. */
8707 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8708 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8711 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
8712 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
8718 /* Similar, for when divides are cheaper. */
8719 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8720 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8723 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
8724 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
8730 /* If we are extracting just the sign bit of an arithmetic
8731 right shift, that shift is not needed. However, the sign
8732 bit of a wider mode may be different from what would be
8733 interpreted as the sign bit in a narrower mode, so, if
8734 the result is narrower, don't discard the shift. */
8735 if (code
== LSHIFTRT
8736 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
8737 && (GET_MODE_BITSIZE (result_mode
)
8738 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
8740 varop
= XEXP (varop
, 0);
8744 /* ... fall through ... */
8749 /* Here we have two nested shifts. The result is usually the
8750 AND of a new shift with a mask. We compute the result below. */
8751 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8752 && INTVAL (XEXP (varop
, 1)) >= 0
8753 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
8754 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8755 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8757 enum rtx_code first_code
= GET_CODE (varop
);
8758 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
8759 unsigned HOST_WIDE_INT mask
;
8762 /* We have one common special case. We can't do any merging if
8763 the inner code is an ASHIFTRT of a smaller mode. However, if
8764 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8765 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8766 we can convert it to
8767 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8768 This simplifies certain SIGN_EXTEND operations. */
8769 if (code
== ASHIFT
&& first_code
== ASHIFTRT
8770 && count
== (unsigned int)
8771 (GET_MODE_BITSIZE (result_mode
)
8772 - GET_MODE_BITSIZE (GET_MODE (varop
))))
8774 /* C3 has the low-order C1 bits zero. */
8776 mask
= (GET_MODE_MASK (mode
)
8777 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
8779 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
8780 XEXP (varop
, 0), mask
);
8781 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
8783 count
= first_count
;
8788 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8789 than C1 high-order bits equal to the sign bit, we can convert
8790 this to either an ASHIFT or an ASHIFTRT depending on the
8793 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8795 if (code
== ASHIFTRT
&& first_code
== ASHIFT
8796 && GET_MODE (varop
) == shift_mode
8797 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
8800 varop
= XEXP (varop
, 0);
8802 signed_count
= count
- first_count
;
8803 if (signed_count
< 0)
8804 count
= -signed_count
, code
= ASHIFT
;
8806 count
= signed_count
;
8811 /* There are some cases we can't do. If CODE is ASHIFTRT,
8812 we can only do this if FIRST_CODE is also ASHIFTRT.
8814 We can't do the case when CODE is ROTATE and FIRST_CODE is
8817 If the mode of this shift is not the mode of the outer shift,
8818 we can't do this if either shift is a right shift or ROTATE.
8820 Finally, we can't do any of these if the mode is too wide
8821 unless the codes are the same.
8823 Handle the case where the shift codes are the same
8826 if (code
== first_code
)
8828 if (GET_MODE (varop
) != result_mode
8829 && (code
== ASHIFTRT
|| code
== LSHIFTRT
8833 count
+= first_count
;
8834 varop
= XEXP (varop
, 0);
8838 if (code
== ASHIFTRT
8839 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
8840 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
8841 || (GET_MODE (varop
) != result_mode
8842 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
8843 || first_code
== ROTATE
8844 || code
== ROTATE
)))
8847 /* To compute the mask to apply after the shift, shift the
8848 nonzero bits of the inner shift the same way the
8849 outer shift will. */
8851 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
8854 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
8857 /* Give up if we can't compute an outer operation to use. */
8859 || GET_CODE (mask_rtx
) != CONST_INT
8860 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
8862 result_mode
, &complement_p
))
8865 /* If the shifts are in the same direction, we add the
8866 counts. Otherwise, we subtract them. */
8867 signed_count
= count
;
8868 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8869 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
8870 signed_count
+= first_count
;
8872 signed_count
-= first_count
;
8874 /* If COUNT is positive, the new shift is usually CODE,
8875 except for the two exceptions below, in which case it is
8876 FIRST_CODE. If the count is negative, FIRST_CODE should
8878 if (signed_count
> 0
8879 && ((first_code
== ROTATE
&& code
== ASHIFT
)
8880 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
8881 code
= first_code
, count
= signed_count
;
8882 else if (signed_count
< 0)
8883 code
= first_code
, count
= -signed_count
;
8885 count
= signed_count
;
8887 varop
= XEXP (varop
, 0);
8891 /* If we have (A << B << C) for any shift, we can convert this to
8892 (A << C << B). This wins if A is a constant. Only try this if
8893 B is not a constant. */
8895 else if (GET_CODE (varop
) == code
8896 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
8898 = simplify_binary_operation (code
, mode
,
8902 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
8909 /* Make this fit the case below. */
8910 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
8911 GEN_INT (GET_MODE_MASK (mode
)));
8917 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8918 with C the size of VAROP - 1 and the shift is logical if
8919 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8920 we have an (le X 0) operation. If we have an arithmetic shift
8921 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8922 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8924 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
8925 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
8926 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8927 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
8928 && count
== (unsigned int)
8929 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
8930 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
8933 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
8936 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
8937 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
8942 /* If we have (shift (logical)), move the logical to the outside
8943 to allow it to possibly combine with another logical and the
8944 shift to combine with another shift. This also canonicalizes to
8945 what a ZERO_EXTRACT looks like. Also, some machines have
8946 (and (shift)) insns. */
8948 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8949 /* We can't do this if we have (ashiftrt (xor)) and the
8950 constant has its sign bit set in shift_mode. */
8951 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
8952 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
8954 && (new = simplify_binary_operation (code
, result_mode
,
8956 GEN_INT (count
))) != 0
8957 && GET_CODE (new) == CONST_INT
8958 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
8959 INTVAL (new), result_mode
, &complement_p
))
8961 varop
= XEXP (varop
, 0);
8965 /* If we can't do that, try to simplify the shift in each arm of the
8966 logical expression, make a new logical expression, and apply
8967 the inverse distributive law. This also can't be done
8968 for some (ashiftrt (xor)). */
8969 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8970 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
8971 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
8974 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
8975 XEXP (varop
, 0), count
);
8976 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
8977 XEXP (varop
, 1), count
);
8979 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
8980 varop
= apply_distributive_law (varop
);
8988 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8989 says that the sign bit can be tested, FOO has mode MODE, C is
8990 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8991 that may be nonzero. */
8992 if (code
== LSHIFTRT
8993 && XEXP (varop
, 1) == const0_rtx
8994 && GET_MODE (XEXP (varop
, 0)) == result_mode
8995 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
8996 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8997 && ((STORE_FLAG_VALUE
8998 & ((HOST_WIDE_INT
) 1
8999 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9000 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9001 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9002 (HOST_WIDE_INT
) 1, result_mode
,
9005 varop
= XEXP (varop
, 0);
9012 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9013 than the number of bits in the mode is equivalent to A. */
9014 if (code
== LSHIFTRT
9015 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9016 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9018 varop
= XEXP (varop
, 0);
9023 /* NEG commutes with ASHIFT since it is multiplication. Move the
9024 NEG outside to allow shifts to combine. */
9026 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9027 (HOST_WIDE_INT
) 0, result_mode
,
9030 varop
= XEXP (varop
, 0);
9036 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9037 is one less than the number of bits in the mode is
9038 equivalent to (xor A 1). */
9039 if (code
== LSHIFTRT
9040 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9041 && XEXP (varop
, 1) == constm1_rtx
9042 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9043 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9044 (HOST_WIDE_INT
) 1, result_mode
,
9048 varop
= XEXP (varop
, 0);
9052 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9053 that might be nonzero in BAR are those being shifted out and those
9054 bits are known zero in FOO, we can replace the PLUS with FOO.
9055 Similarly in the other operand order. This code occurs when
9056 we are computing the size of a variable-size array. */
9058 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9059 && count
< HOST_BITS_PER_WIDE_INT
9060 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9061 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9062 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9064 varop
= XEXP (varop
, 0);
9067 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9068 && count
< HOST_BITS_PER_WIDE_INT
9069 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9070 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9072 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9073 & nonzero_bits (XEXP (varop
, 1),
9076 varop
= XEXP (varop
, 1);
9080 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9082 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9083 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9085 GEN_INT (count
))) != 0
9086 && GET_CODE (new) == CONST_INT
9087 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9088 INTVAL (new), result_mode
, &complement_p
))
9090 varop
= XEXP (varop
, 0);
9094 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9095 signbit', and attempt to change the PLUS to an XOR and move it to
9096 the outer operation as is done above in the AND/IOR/XOR case
9097 leg for shift(logical). See details in logical handling above
9098 for reasoning in doing so. */
9099 if (code
== LSHIFTRT
9100 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9101 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
9102 && (new = simplify_binary_operation (code
, result_mode
,
9104 GEN_INT (count
))) != 0
9105 && GET_CODE (new) == CONST_INT
9106 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9107 INTVAL (new), result_mode
, &complement_p
))
9109 varop
= XEXP (varop
, 0);
9116 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9117 with C the size of VAROP - 1 and the shift is logical if
9118 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9119 we have a (gt X 0) operation. If the shift is arithmetic with
9120 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9121 we have a (neg (gt X 0)) operation. */
9123 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9124 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9125 && count
== (unsigned int)
9126 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9127 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9128 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9129 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9131 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9134 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9137 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9138 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9145 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9146 if the truncate does not affect the value. */
9147 if (code
== LSHIFTRT
9148 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9149 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9150 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9151 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9152 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9154 rtx varop_inner
= XEXP (varop
, 0);
9157 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9158 XEXP (varop_inner
, 0),
9160 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9161 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9174 /* We need to determine what mode to do the shift in. If the shift is
9175 a right shift or ROTATE, we must always do it in the mode it was
9176 originally done in. Otherwise, we can do it in MODE, the widest mode
9177 encountered. The code we care about is that of the shift that will
9178 actually be done, not the shift that was originally requested. */
9180 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9181 ? result_mode
: mode
);
9183 /* We have now finished analyzing the shift. The result should be
9184 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9185 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9186 to the result of the shift. OUTER_CONST is the relevant constant,
9187 but we must turn off all bits turned off in the shift.
9189 If we were passed a value for X, see if we can use any pieces of
9190 it. If not, make new rtx. */
9192 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == RTX_BIN_ARITH
9193 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9194 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9195 const_rtx
= XEXP (x
, 1);
9197 const_rtx
= GEN_INT (count
);
9199 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9200 && GET_MODE (XEXP (x
, 0)) == shift_mode
9201 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9202 varop
= XEXP (x
, 0);
9203 else if (GET_MODE (varop
) != shift_mode
)
9204 varop
= gen_lowpart (shift_mode
, varop
);
9206 /* If we can't make the SUBREG, try to return what we were given. */
9207 if (GET_CODE (varop
) == CLOBBER
)
9208 return x
? x
: varop
;
9210 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9214 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9216 /* If we have an outer operation and we just made a shift, it is
9217 possible that we could have simplified the shift were it not
9218 for the outer operation. So try to do the simplification
9221 if (outer_op
!= UNKNOWN
&& GET_CODE (x
) == code
9222 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9223 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9224 INTVAL (XEXP (x
, 1)));
9226 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9227 turn off all the bits that the shift would have turned off. */
9228 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9229 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9230 GET_MODE_MASK (result_mode
) >> orig_count
);
9232 /* Do the remainder of the processing in RESULT_MODE. */
9233 x
= gen_lowpart (result_mode
, x
);
9235 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9238 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9240 if (outer_op
!= UNKNOWN
)
9242 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9243 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9245 if (outer_op
== AND
)
9246 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9247 else if (outer_op
== SET
)
9248 /* This means that we have determined that the result is
9249 equivalent to a constant. This should be rare. */
9250 x
= GEN_INT (outer_const
);
9251 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
9252 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9254 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9260 /* Like recog, but we receive the address of a pointer to a new pattern.
9261 We try to match the rtx that the pointer points to.
9262 If that fails, we may try to modify or replace the pattern,
9263 storing the replacement into the same pointer object.
9265 Modifications include deletion or addition of CLOBBERs.
9267 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9268 the CLOBBERs are placed.
9270 The value is the final insn code from the pattern ultimately matched,
9274 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9277 int insn_code_number
;
9278 int num_clobbers_to_add
= 0;
9281 rtx old_notes
, old_pat
;
9283 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9284 we use to indicate that something didn't match. If we find such a
9285 thing, force rejection. */
9286 if (GET_CODE (pat
) == PARALLEL
)
9287 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9288 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9289 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9292 old_pat
= PATTERN (insn
);
9293 old_notes
= REG_NOTES (insn
);
9294 PATTERN (insn
) = pat
;
9295 REG_NOTES (insn
) = 0;
9297 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9299 /* If it isn't, there is the possibility that we previously had an insn
9300 that clobbered some register as a side effect, but the combined
9301 insn doesn't need to do that. So try once more without the clobbers
9302 unless this represents an ASM insn. */
9304 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9305 && GET_CODE (pat
) == PARALLEL
)
9309 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9310 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9313 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9317 SUBST_INT (XVECLEN (pat
, 0), pos
);
9320 pat
= XVECEXP (pat
, 0, 0);
9322 PATTERN (insn
) = pat
;
9323 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9325 PATTERN (insn
) = old_pat
;
9326 REG_NOTES (insn
) = old_notes
;
9328 /* Recognize all noop sets, these will be killed by followup pass. */
9329 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9330 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9332 /* If we had any clobbers to add, make a new pattern than contains
9333 them. Then check to make sure that all of them are dead. */
9334 if (num_clobbers_to_add
)
9336 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9337 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9339 + num_clobbers_to_add
)
9340 : num_clobbers_to_add
+ 1));
9342 if (GET_CODE (pat
) == PARALLEL
)
9343 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9344 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9346 XVECEXP (newpat
, 0, 0) = pat
;
9348 add_clobbers (newpat
, insn_code_number
);
9350 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9351 i
< XVECLEN (newpat
, 0); i
++)
9353 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
9354 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9356 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9357 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9365 return insn_code_number
;
9368 /* Like gen_lowpart_general but for use by combine. In combine it
9369 is not possible to create any new pseudoregs. However, it is
9370 safe to create invalid memory addresses, because combine will
9371 try to recognize them and all they will do is make the combine
9374 If for some reason this cannot do its job, an rtx
9375 (clobber (const_int 0)) is returned.
9376 An insn containing that will not be recognized. */
9379 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
9381 enum machine_mode imode
= GET_MODE (x
);
9382 unsigned int osize
= GET_MODE_SIZE (omode
);
9383 unsigned int isize
= GET_MODE_SIZE (imode
);
9389 /* Return identity if this is a CONST or symbolic reference. */
9391 && (GET_CODE (x
) == CONST
9392 || GET_CODE (x
) == SYMBOL_REF
9393 || GET_CODE (x
) == LABEL_REF
))
9396 /* We can only support MODE being wider than a word if X is a
9397 constant integer or has a mode the same size. */
9398 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
9399 && ! ((imode
== VOIDmode
9400 && (GET_CODE (x
) == CONST_INT
9401 || GET_CODE (x
) == CONST_DOUBLE
))
9405 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9406 won't know what to do. So we will strip off the SUBREG here and
9407 process normally. */
9408 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
9412 /* For use in case we fall down into the address adjustments
9413 further below, we need to adjust the known mode and size of
9414 x; imode and isize, since we just adjusted x. */
9415 imode
= GET_MODE (x
);
9420 isize
= GET_MODE_SIZE (imode
);
9423 result
= gen_lowpart_common (omode
, x
);
9425 #ifdef CANNOT_CHANGE_MODE_CLASS
9426 if (result
!= 0 && GET_CODE (result
) == SUBREG
)
9427 record_subregs_of_mode (result
);
9437 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9439 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9442 /* If we want to refer to something bigger than the original memref,
9443 generate a paradoxical subreg instead. That will force a reload
9444 of the original memref X. */
9446 return gen_rtx_SUBREG (omode
, x
, 0);
9448 if (WORDS_BIG_ENDIAN
)
9449 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
9451 /* Adjust the address so that the address-after-the-data is
9453 if (BYTES_BIG_ENDIAN
)
9454 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
9456 return adjust_address_nv (x
, omode
, offset
);
9459 /* If X is a comparison operator, rewrite it in a new mode. This
9460 probably won't match, but may allow further simplifications. */
9461 else if (COMPARISON_P (x
))
9462 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
9464 /* If we couldn't simplify X any other way, just enclose it in a
9465 SUBREG. Normally, this SUBREG won't match, but some patterns may
9466 include an explicit SUBREG or we may simplify it further in combine. */
9472 offset
= subreg_lowpart_offset (omode
, imode
);
9473 if (imode
== VOIDmode
)
9475 imode
= int_mode_for_mode (omode
);
9476 x
= gen_lowpart_common (imode
, x
);
9480 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
9486 return gen_rtx_CLOBBER (imode
, const0_rtx
);
9489 /* These routines make binary and unary operations by first seeing if they
9490 fold; if not, a new expression is allocated. */
9493 gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
, rtx op1
)
9498 if (GET_CODE (op0
) == CLOBBER
)
9500 else if (GET_CODE (op1
) == CLOBBER
)
9503 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
9504 && swap_commutative_operands_p (op0
, op1
))
9505 tem
= op0
, op0
= op1
, op1
= tem
;
9507 if (GET_RTX_CLASS (code
) == RTX_COMPARE
9508 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
9510 enum machine_mode op_mode
= GET_MODE (op0
);
9512 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9513 just (REL_OP X Y). */
9514 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
9516 op1
= XEXP (op0
, 1);
9517 op0
= XEXP (op0
, 0);
9518 op_mode
= GET_MODE (op0
);
9521 if (op_mode
== VOIDmode
)
9522 op_mode
= GET_MODE (op1
);
9523 result
= simplify_relational_operation (code
, mode
, op_mode
, op0
, op1
);
9526 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
9531 /* Put complex operands first and constants second. */
9532 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
9533 && swap_commutative_operands_p (op0
, op1
))
9534 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
9536 /* If we are turning off bits already known off in OP0, we need not do
9538 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
9539 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9540 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
9543 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
9546 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9547 comparison code that will be tested.
9549 The result is a possibly different comparison code to use. *POP0 and
9550 *POP1 may be updated.
9552 It is possible that we might detect that a comparison is either always
9553 true or always false. However, we do not perform general constant
9554 folding in combine, so this knowledge isn't useful. Such tautologies
9555 should have been detected earlier. Hence we ignore all such cases. */
9557 static enum rtx_code
9558 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
9564 enum machine_mode mode
, tmode
;
9566 /* Try a few ways of applying the same transformation to both operands. */
9569 #ifndef WORD_REGISTER_OPERATIONS
9570 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9571 so check specially. */
9572 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
9573 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
9574 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9575 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
9576 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
9577 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
9578 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
9579 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
9580 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9581 && XEXP (op0
, 1) == XEXP (op1
, 1)
9582 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
9583 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
9584 && (INTVAL (XEXP (op0
, 1))
9585 == (GET_MODE_BITSIZE (GET_MODE (op0
))
9587 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
9589 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
9590 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
9594 /* If both operands are the same constant shift, see if we can ignore the
9595 shift. We can if the shift is a rotate or if the bits shifted out of
9596 this shift are known to be zero for both inputs and if the type of
9597 comparison is compatible with the shift. */
9598 if (GET_CODE (op0
) == GET_CODE (op1
)
9599 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
9600 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
9601 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
9602 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
9603 || (GET_CODE (op0
) == ASHIFTRT
9604 && (code
!= GTU
&& code
!= LTU
9605 && code
!= GEU
&& code
!= LEU
)))
9606 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9607 && INTVAL (XEXP (op0
, 1)) >= 0
9608 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
9609 && XEXP (op0
, 1) == XEXP (op1
, 1))
9611 enum machine_mode mode
= GET_MODE (op0
);
9612 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9613 int shift_count
= INTVAL (XEXP (op0
, 1));
9615 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
9616 mask
&= (mask
>> shift_count
) << shift_count
;
9617 else if (GET_CODE (op0
) == ASHIFT
)
9618 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
9620 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
9621 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
9622 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
9627 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9628 SUBREGs are of the same mode, and, in both cases, the AND would
9629 be redundant if the comparison was done in the narrower mode,
9630 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9631 and the operand's possibly nonzero bits are 0xffffff01; in that case
9632 if we only care about QImode, we don't need the AND). This case
9633 occurs if the output mode of an scc insn is not SImode and
9634 STORE_FLAG_VALUE == 1 (e.g., the 386).
9636 Similarly, check for a case where the AND's are ZERO_EXTEND
9637 operations from some narrower mode even though a SUBREG is not
9640 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
9641 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9642 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
9644 rtx inner_op0
= XEXP (op0
, 0);
9645 rtx inner_op1
= XEXP (op1
, 0);
9646 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
9647 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
9650 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
9651 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
9652 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
9653 && (GET_MODE (SUBREG_REG (inner_op0
))
9654 == GET_MODE (SUBREG_REG (inner_op1
)))
9655 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
9656 <= HOST_BITS_PER_WIDE_INT
)
9657 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
9658 GET_MODE (SUBREG_REG (inner_op0
)))))
9659 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
9660 GET_MODE (SUBREG_REG (inner_op1
))))))
9662 op0
= SUBREG_REG (inner_op0
);
9663 op1
= SUBREG_REG (inner_op1
);
9665 /* The resulting comparison is always unsigned since we masked
9666 off the original sign bit. */
9667 code
= unsigned_condition (code
);
9673 for (tmode
= GET_CLASS_NARROWEST_MODE
9674 (GET_MODE_CLASS (GET_MODE (op0
)));
9675 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
9676 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
9678 op0
= gen_lowpart (tmode
, inner_op0
);
9679 op1
= gen_lowpart (tmode
, inner_op1
);
9680 code
= unsigned_condition (code
);
9689 /* If both operands are NOT, we can strip off the outer operation
9690 and adjust the comparison code for swapped operands; similarly for
9691 NEG, except that this must be an equality comparison. */
9692 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
9693 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
9694 && (code
== EQ
|| code
== NE
)))
9695 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
9701 /* If the first operand is a constant, swap the operands and adjust the
9702 comparison code appropriately, but don't do this if the second operand
9703 is already a constant integer. */
9704 if (swap_commutative_operands_p (op0
, op1
))
9706 tem
= op0
, op0
= op1
, op1
= tem
;
9707 code
= swap_condition (code
);
9710 /* We now enter a loop during which we will try to simplify the comparison.
9711 For the most part, we only are concerned with comparisons with zero,
9712 but some things may really be comparisons with zero but not start
9713 out looking that way. */
9715 while (GET_CODE (op1
) == CONST_INT
)
9717 enum machine_mode mode
= GET_MODE (op0
);
9718 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
9719 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9720 int equality_comparison_p
;
9721 int sign_bit_comparison_p
;
9722 int unsigned_comparison_p
;
9723 HOST_WIDE_INT const_op
;
9725 /* We only want to handle integral modes. This catches VOIDmode,
9726 CCmode, and the floating-point modes. An exception is that we
9727 can handle VOIDmode if OP0 is a COMPARE or a comparison
9730 if (GET_MODE_CLASS (mode
) != MODE_INT
9731 && ! (mode
== VOIDmode
9732 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
9735 /* Get the constant we are comparing against and turn off all bits
9736 not on in our mode. */
9737 const_op
= INTVAL (op1
);
9738 if (mode
!= VOIDmode
)
9739 const_op
= trunc_int_for_mode (const_op
, mode
);
9740 op1
= GEN_INT (const_op
);
9742 /* If we are comparing against a constant power of two and the value
9743 being compared can only have that single bit nonzero (e.g., it was
9744 `and'ed with that bit), we can replace this with a comparison
9747 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
9748 || code
== LT
|| code
== LTU
)
9749 && mode_width
<= HOST_BITS_PER_WIDE_INT
9750 && exact_log2 (const_op
) >= 0
9751 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
9753 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
9754 op1
= const0_rtx
, const_op
= 0;
9757 /* Similarly, if we are comparing a value known to be either -1 or
9758 0 with -1, change it to the opposite comparison against zero. */
9761 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
9762 || code
== GEU
|| code
== LTU
)
9763 && num_sign_bit_copies (op0
, mode
) == mode_width
)
9765 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
9766 op1
= const0_rtx
, const_op
= 0;
9769 /* Do some canonicalizations based on the comparison code. We prefer
9770 comparisons against zero and then prefer equality comparisons.
9771 If we can reduce the size of a constant, we will do that too. */
9776 /* < C is equivalent to <= (C - 1) */
9780 op1
= GEN_INT (const_op
);
9782 /* ... fall through to LE case below. */
9788 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9792 op1
= GEN_INT (const_op
);
9796 /* If we are doing a <= 0 comparison on a value known to have
9797 a zero sign bit, we can replace this with == 0. */
9798 else if (const_op
== 0
9799 && mode_width
<= HOST_BITS_PER_WIDE_INT
9800 && (nonzero_bits (op0
, mode
)
9801 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9806 /* >= C is equivalent to > (C - 1). */
9810 op1
= GEN_INT (const_op
);
9812 /* ... fall through to GT below. */
9818 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9822 op1
= GEN_INT (const_op
);
9826 /* If we are doing a > 0 comparison on a value known to have
9827 a zero sign bit, we can replace this with != 0. */
9828 else if (const_op
== 0
9829 && mode_width
<= HOST_BITS_PER_WIDE_INT
9830 && (nonzero_bits (op0
, mode
)
9831 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9836 /* < C is equivalent to <= (C - 1). */
9840 op1
= GEN_INT (const_op
);
9842 /* ... fall through ... */
9845 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9846 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9847 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9849 const_op
= 0, op1
= const0_rtx
;
9857 /* unsigned <= 0 is equivalent to == 0 */
9861 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9862 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9863 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9865 const_op
= 0, op1
= const0_rtx
;
9871 /* >= C is equivalent to > (C - 1). */
9875 op1
= GEN_INT (const_op
);
9877 /* ... fall through ... */
9880 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9881 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9882 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9884 const_op
= 0, op1
= const0_rtx
;
9892 /* unsigned > 0 is equivalent to != 0 */
9896 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9897 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9898 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9900 const_op
= 0, op1
= const0_rtx
;
9909 /* Compute some predicates to simplify code below. */
9911 equality_comparison_p
= (code
== EQ
|| code
== NE
);
9912 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
9913 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
9916 /* If this is a sign bit comparison and we can do arithmetic in
9917 MODE, say that we will only be needing the sign bit of OP0. */
9918 if (sign_bit_comparison_p
9919 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9920 op0
= force_to_mode (op0
, mode
,
9922 << (GET_MODE_BITSIZE (mode
) - 1)),
9925 /* Now try cases based on the opcode of OP0. If none of the cases
9926 does a "continue", we exit this loop immediately after the
9929 switch (GET_CODE (op0
))
9932 /* If we are extracting a single bit from a variable position in
9933 a constant that has only a single bit set and are comparing it
9934 with zero, we can convert this into an equality comparison
9935 between the position and the location of the single bit. */
9936 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9937 have already reduced the shift count modulo the word size. */
9938 if (!SHIFT_COUNT_TRUNCATED
9939 && GET_CODE (XEXP (op0
, 0)) == CONST_INT
9940 && XEXP (op0
, 1) == const1_rtx
9941 && equality_comparison_p
&& const_op
== 0
9942 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
9944 if (BITS_BIG_ENDIAN
)
9946 enum machine_mode new_mode
9947 = mode_for_extraction (EP_extzv
, 1);
9948 if (new_mode
== MAX_MACHINE_MODE
)
9949 i
= BITS_PER_WORD
- 1 - i
;
9953 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
9957 op0
= XEXP (op0
, 2);
9961 /* Result is nonzero iff shift count is equal to I. */
9962 code
= reverse_condition (code
);
9966 /* ... fall through ... */
9969 tem
= expand_compound_operation (op0
);
9978 /* If testing for equality, we can take the NOT of the constant. */
9979 if (equality_comparison_p
9980 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
9982 op0
= XEXP (op0
, 0);
9987 /* If just looking at the sign bit, reverse the sense of the
9989 if (sign_bit_comparison_p
)
9991 op0
= XEXP (op0
, 0);
9992 code
= (code
== GE
? LT
: GE
);
9998 /* If testing for equality, we can take the NEG of the constant. */
9999 if (equality_comparison_p
10000 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10002 op0
= XEXP (op0
, 0);
10007 /* The remaining cases only apply to comparisons with zero. */
10011 /* When X is ABS or is known positive,
10012 (neg X) is < 0 if and only if X != 0. */
10014 if (sign_bit_comparison_p
10015 && (GET_CODE (XEXP (op0
, 0)) == ABS
10016 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10017 && (nonzero_bits (XEXP (op0
, 0), mode
)
10018 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10020 op0
= XEXP (op0
, 0);
10021 code
= (code
== LT
? NE
: EQ
);
10025 /* If we have NEG of something whose two high-order bits are the
10026 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10027 if (num_sign_bit_copies (op0
, mode
) >= 2)
10029 op0
= XEXP (op0
, 0);
10030 code
= swap_condition (code
);
10036 /* If we are testing equality and our count is a constant, we
10037 can perform the inverse operation on our RHS. */
10038 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10039 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10040 op1
, XEXP (op0
, 1))) != 0)
10042 op0
= XEXP (op0
, 0);
10047 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10048 a particular bit. Convert it to an AND of a constant of that
10049 bit. This will be converted into a ZERO_EXTRACT. */
10050 if (const_op
== 0 && sign_bit_comparison_p
10051 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10052 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10054 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10057 - INTVAL (XEXP (op0
, 1)))));
10058 code
= (code
== LT
? NE
: EQ
);
10062 /* Fall through. */
10065 /* ABS is ignorable inside an equality comparison with zero. */
10066 if (const_op
== 0 && equality_comparison_p
)
10068 op0
= XEXP (op0
, 0);
10074 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10075 (compare FOO CONST) if CONST fits in FOO's mode and we
10076 are either testing inequality or have an unsigned
10077 comparison with ZERO_EXTEND or a signed comparison with
10078 SIGN_EXTEND. But don't do it if we don't have a compare
10079 insn of the given mode, since we'd have to revert it
10080 later on, and then we wouldn't know whether to sign- or
10082 mode
= GET_MODE (XEXP (op0
, 0));
10083 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10084 && ! unsigned_comparison_p
10085 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10086 && ((unsigned HOST_WIDE_INT
) const_op
10087 < (((unsigned HOST_WIDE_INT
) 1
10088 << (GET_MODE_BITSIZE (mode
) - 1))))
10089 && cmp_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
10091 op0
= XEXP (op0
, 0);
10097 /* Check for the case where we are comparing A - C1 with C2, that is
10099 (subreg:MODE (plus (A) (-C1))) op (C2)
10101 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10102 comparison in the wider mode. One of the following two conditions
10103 must be true in order for this to be valid:
10105 1. The mode extension results in the same bit pattern being added
10106 on both sides and the comparison is equality or unsigned. As
10107 C2 has been truncated to fit in MODE, the pattern can only be
10110 2. The mode extension results in the sign bit being copied on
10113 The difficulty here is that we have predicates for A but not for
10114 (A - C1) so we need to check that C1 is within proper bounds so
10115 as to perturbate A as little as possible. */
10117 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10118 && subreg_lowpart_p (op0
)
10119 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) > mode_width
10120 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10121 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
)
10123 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
10124 rtx a
= XEXP (SUBREG_REG (op0
), 0);
10125 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
10128 && (unsigned HOST_WIDE_INT
) c1
10129 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
10130 && (equality_comparison_p
|| unsigned_comparison_p
)
10131 /* (A - C1) zero-extends if it is positive and sign-extends
10132 if it is negative, C2 both zero- and sign-extends. */
10133 && ((0 == (nonzero_bits (a
, inner_mode
)
10134 & ~GET_MODE_MASK (mode
))
10136 /* (A - C1) sign-extends if it is positive and 1-extends
10137 if it is negative, C2 both sign- and 1-extends. */
10138 || (num_sign_bit_copies (a
, inner_mode
)
10139 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10142 || ((unsigned HOST_WIDE_INT
) c1
10143 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
10144 /* (A - C1) always sign-extends, like C2. */
10145 && num_sign_bit_copies (a
, inner_mode
)
10146 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10147 - mode_width
- 1)))
10149 op0
= SUBREG_REG (op0
);
10154 /* If the inner mode is narrower and we are extracting the low part,
10155 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10156 if (subreg_lowpart_p (op0
)
10157 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10158 /* Fall through */ ;
10162 /* ... fall through ... */
10165 mode
= GET_MODE (XEXP (op0
, 0));
10166 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10167 && (unsigned_comparison_p
|| equality_comparison_p
)
10168 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10169 && ((unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
))
10170 && cmp_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
10172 op0
= XEXP (op0
, 0);
10178 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10179 this for equality comparisons due to pathological cases involving
10181 if (equality_comparison_p
10182 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10183 op1
, XEXP (op0
, 1))))
10185 op0
= XEXP (op0
, 0);
10190 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10191 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10192 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10194 op0
= XEXP (XEXP (op0
, 0), 0);
10195 code
= (code
== LT
? EQ
: NE
);
10201 /* We used to optimize signed comparisons against zero, but that
10202 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10203 arrive here as equality comparisons, or (GEU, LTU) are
10204 optimized away. No need to special-case them. */
10206 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10207 (eq B (minus A C)), whichever simplifies. We can only do
10208 this for equality comparisons due to pathological cases involving
10210 if (equality_comparison_p
10211 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10212 XEXP (op0
, 1), op1
)))
10214 op0
= XEXP (op0
, 0);
10219 if (equality_comparison_p
10220 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10221 XEXP (op0
, 0), op1
)))
10223 op0
= XEXP (op0
, 1);
10228 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10229 of bits in X minus 1, is one iff X > 0. */
10230 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10231 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10232 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10234 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10236 op0
= XEXP (op0
, 1);
10237 code
= (code
== GE
? LE
: GT
);
10243 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10244 if C is zero or B is a constant. */
10245 if (equality_comparison_p
10246 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10247 XEXP (op0
, 1), op1
)))
10249 op0
= XEXP (op0
, 0);
10256 case UNEQ
: case LTGT
:
10257 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10258 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10259 case UNORDERED
: case ORDERED
:
10260 /* We can't do anything if OP0 is a condition code value, rather
10261 than an actual data value. */
10263 || CC0_P (XEXP (op0
, 0))
10264 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10267 /* Get the two operands being compared. */
10268 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10269 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10271 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10273 /* Check for the cases where we simply want the result of the
10274 earlier test or the opposite of that result. */
10275 if (code
== NE
|| code
== EQ
10276 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10277 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10278 && (STORE_FLAG_VALUE
10279 & (((HOST_WIDE_INT
) 1
10280 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10281 && (code
== LT
|| code
== GE
)))
10283 enum rtx_code new_code
;
10284 if (code
== LT
|| code
== NE
)
10285 new_code
= GET_CODE (op0
);
10287 new_code
= combine_reversed_comparison_code (op0
);
10289 if (new_code
!= UNKNOWN
)
10300 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10302 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10303 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10304 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10306 op0
= XEXP (op0
, 1);
10307 code
= (code
== GE
? GT
: LE
);
10313 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10314 will be converted to a ZERO_EXTRACT later. */
10315 if (const_op
== 0 && equality_comparison_p
10316 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10317 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10319 op0
= simplify_and_const_int
10320 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10322 XEXP (XEXP (op0
, 0), 1)),
10323 (HOST_WIDE_INT
) 1);
10327 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10328 zero and X is a comparison and C1 and C2 describe only bits set
10329 in STORE_FLAG_VALUE, we can compare with X. */
10330 if (const_op
== 0 && equality_comparison_p
10331 && mode_width
<= HOST_BITS_PER_WIDE_INT
10332 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10333 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10334 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10335 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10336 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10338 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10339 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10340 if ((~STORE_FLAG_VALUE
& mask
) == 0
10341 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
10342 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10343 && COMPARISON_P (tem
))))
10345 op0
= XEXP (XEXP (op0
, 0), 0);
10350 /* If we are doing an equality comparison of an AND of a bit equal
10351 to the sign bit, replace this with a LT or GE comparison of
10352 the underlying value. */
10353 if (equality_comparison_p
10355 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10356 && mode_width
<= HOST_BITS_PER_WIDE_INT
10357 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10358 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10360 op0
= XEXP (op0
, 0);
10361 code
= (code
== EQ
? GE
: LT
);
10365 /* If this AND operation is really a ZERO_EXTEND from a narrower
10366 mode, the constant fits within that mode, and this is either an
10367 equality or unsigned comparison, try to do this comparison in
10368 the narrower mode. */
10369 if ((equality_comparison_p
|| unsigned_comparison_p
)
10370 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10371 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10372 & GET_MODE_MASK (mode
))
10374 && const_op
>> i
== 0
10375 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10377 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
10381 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10382 fits in both M1 and M2 and the SUBREG is either paradoxical
10383 or represents the low part, permute the SUBREG and the AND
10385 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10387 unsigned HOST_WIDE_INT c1
;
10388 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10389 /* Require an integral mode, to avoid creating something like
10391 if (SCALAR_INT_MODE_P (tmode
)
10392 /* It is unsafe to commute the AND into the SUBREG if the
10393 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10394 not defined. As originally written the upper bits
10395 have a defined value due to the AND operation.
10396 However, if we commute the AND inside the SUBREG then
10397 they no longer have defined values and the meaning of
10398 the code has been changed. */
10400 #ifdef WORD_REGISTER_OPERATIONS
10401 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10402 && mode_width
<= BITS_PER_WORD
)
10404 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10405 && subreg_lowpart_p (XEXP (op0
, 0))))
10406 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10407 && mode_width
<= HOST_BITS_PER_WIDE_INT
10408 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10409 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10410 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10412 && c1
!= GET_MODE_MASK (tmode
))
10414 op0
= gen_binary (AND
, tmode
,
10415 SUBREG_REG (XEXP (op0
, 0)),
10416 gen_int_mode (c1
, tmode
));
10417 op0
= gen_lowpart (mode
, op0
);
10422 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10423 if (const_op
== 0 && equality_comparison_p
10424 && XEXP (op0
, 1) == const1_rtx
10425 && GET_CODE (XEXP (op0
, 0)) == NOT
)
10427 op0
= simplify_and_const_int
10428 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
10429 code
= (code
== NE
? EQ
: NE
);
10433 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10434 (eq (and (lshiftrt X) 1) 0).
10435 Also handle the case where (not X) is expressed using xor. */
10436 if (const_op
== 0 && equality_comparison_p
10437 && XEXP (op0
, 1) == const1_rtx
10438 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
10440 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
10441 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
10443 if (GET_CODE (shift_op
) == NOT
10444 || (GET_CODE (shift_op
) == XOR
10445 && GET_CODE (XEXP (shift_op
, 1)) == CONST_INT
10446 && GET_CODE (shift_count
) == CONST_INT
10447 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10448 && (INTVAL (XEXP (shift_op
, 1))
10449 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
10451 op0
= simplify_and_const_int
10453 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
10454 (HOST_WIDE_INT
) 1);
10455 code
= (code
== NE
? EQ
: NE
);
10462 /* If we have (compare (ashift FOO N) (const_int C)) and
10463 the high order N bits of FOO (N+1 if an inequality comparison)
10464 are known to be zero, we can do this by comparing FOO with C
10465 shifted right N bits so long as the low-order N bits of C are
10467 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10468 && INTVAL (XEXP (op0
, 1)) >= 0
10469 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10470 < HOST_BITS_PER_WIDE_INT
)
10472 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10473 && mode_width
<= HOST_BITS_PER_WIDE_INT
10474 && (nonzero_bits (XEXP (op0
, 0), mode
)
10475 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10476 + ! equality_comparison_p
))) == 0)
10478 /* We must perform a logical shift, not an arithmetic one,
10479 as we want the top N bits of C to be zero. */
10480 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10482 temp
>>= INTVAL (XEXP (op0
, 1));
10483 op1
= gen_int_mode (temp
, mode
);
10484 op0
= XEXP (op0
, 0);
10488 /* If we are doing a sign bit comparison, it means we are testing
10489 a particular bit. Convert it to the appropriate AND. */
10490 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10491 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10493 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10496 - INTVAL (XEXP (op0
, 1)))));
10497 code
= (code
== LT
? NE
: EQ
);
10501 /* If this an equality comparison with zero and we are shifting
10502 the low bit to the sign bit, we can convert this to an AND of the
10504 if (const_op
== 0 && equality_comparison_p
10505 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10506 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10509 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10510 (HOST_WIDE_INT
) 1);
10516 /* If this is an equality comparison with zero, we can do this
10517 as a logical shift, which might be much simpler. */
10518 if (equality_comparison_p
&& const_op
== 0
10519 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10521 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10523 INTVAL (XEXP (op0
, 1)));
10527 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10528 do the comparison in a narrower mode. */
10529 if (! unsigned_comparison_p
10530 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10531 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10532 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10533 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10534 MODE_INT
, 1)) != BLKmode
10535 && (((unsigned HOST_WIDE_INT
) const_op
10536 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10537 <= GET_MODE_MASK (tmode
)))
10539 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
10543 /* Likewise if OP0 is a PLUS of a sign extension with a
10544 constant, which is usually represented with the PLUS
10545 between the shifts. */
10546 if (! unsigned_comparison_p
10547 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10548 && GET_CODE (XEXP (op0
, 0)) == PLUS
10549 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10550 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10551 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10552 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10553 MODE_INT
, 1)) != BLKmode
10554 && (((unsigned HOST_WIDE_INT
) const_op
10555 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10556 <= GET_MODE_MASK (tmode
)))
10558 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
10559 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
10560 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
10563 op0
= gen_binary (PLUS
, tmode
,
10564 gen_lowpart (tmode
, inner
),
10569 /* ... fall through ... */
10571 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10572 the low order N bits of FOO are known to be zero, we can do this
10573 by comparing FOO with C shifted left N bits so long as no
10574 overflow occurs. */
10575 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10576 && INTVAL (XEXP (op0
, 1)) >= 0
10577 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10578 && mode_width
<= HOST_BITS_PER_WIDE_INT
10579 && (nonzero_bits (XEXP (op0
, 0), mode
)
10580 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
10581 && (((unsigned HOST_WIDE_INT
) const_op
10582 + (GET_CODE (op0
) != LSHIFTRT
10583 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
10586 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
10588 /* If the shift was logical, then we must make the condition
10590 if (GET_CODE (op0
) == LSHIFTRT
)
10591 code
= unsigned_condition (code
);
10593 const_op
<<= INTVAL (XEXP (op0
, 1));
10594 op1
= GEN_INT (const_op
);
10595 op0
= XEXP (op0
, 0);
10599 /* If we are using this shift to extract just the sign bit, we
10600 can replace this with an LT or GE comparison. */
10602 && (equality_comparison_p
|| sign_bit_comparison_p
)
10603 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10604 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10607 op0
= XEXP (op0
, 0);
10608 code
= (code
== NE
|| code
== GT
? LT
: GE
);
10620 /* Now make any compound operations involved in this comparison. Then,
10621 check for an outmost SUBREG on OP0 that is not doing anything or is
10622 paradoxical. The latter transformation must only be performed when
10623 it is known that the "extra" bits will be the same in op0 and op1 or
10624 that they don't matter. There are three cases to consider:
10626 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10627 care bits and we can assume they have any convenient value. So
10628 making the transformation is safe.
10630 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10631 In this case the upper bits of op0 are undefined. We should not make
10632 the simplification in that case as we do not know the contents of
10635 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10636 UNKNOWN. In that case we know those bits are zeros or ones. We must
10637 also be sure that they are the same as the upper bits of op1.
10639 We can never remove a SUBREG for a non-equality comparison because
10640 the sign bit is in a different place in the underlying object. */
10642 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
10643 op1
= make_compound_operation (op1
, SET
);
10645 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10646 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10647 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
10648 && (code
== NE
|| code
== EQ
))
10650 if (GET_MODE_SIZE (GET_MODE (op0
))
10651 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
10653 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10655 if (REG_P (SUBREG_REG (op0
)))
10657 op0
= SUBREG_REG (op0
);
10658 op1
= gen_lowpart (GET_MODE (op0
), op1
);
10661 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10662 <= HOST_BITS_PER_WIDE_INT
)
10663 && (nonzero_bits (SUBREG_REG (op0
),
10664 GET_MODE (SUBREG_REG (op0
)))
10665 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
10667 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
10669 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
10670 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
10671 op0
= SUBREG_REG (op0
), op1
= tem
;
10675 /* We now do the opposite procedure: Some machines don't have compare
10676 insns in all modes. If OP0's mode is an integer mode smaller than a
10677 word and we can't do a compare in that mode, see if there is a larger
10678 mode for which we can do the compare. There are a number of cases in
10679 which we can use the wider mode. */
10681 mode
= GET_MODE (op0
);
10682 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10683 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
10684 && ! have_insn_for (COMPARE
, mode
))
10685 for (tmode
= GET_MODE_WIDER_MODE (mode
);
10687 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
10688 tmode
= GET_MODE_WIDER_MODE (tmode
))
10689 if (have_insn_for (COMPARE
, tmode
))
10693 /* If the only nonzero bits in OP0 and OP1 are those in the
10694 narrower mode and this is an equality or unsigned comparison,
10695 we can use the wider mode. Similarly for sign-extended
10696 values, in which case it is true for all comparisons. */
10697 zero_extended
= ((code
== EQ
|| code
== NE
10698 || code
== GEU
|| code
== GTU
10699 || code
== LEU
|| code
== LTU
)
10700 && (nonzero_bits (op0
, tmode
)
10701 & ~GET_MODE_MASK (mode
)) == 0
10702 && ((GET_CODE (op1
) == CONST_INT
10703 || (nonzero_bits (op1
, tmode
)
10704 & ~GET_MODE_MASK (mode
)) == 0)));
10707 || ((num_sign_bit_copies (op0
, tmode
)
10708 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
10709 - GET_MODE_BITSIZE (mode
)))
10710 && (num_sign_bit_copies (op1
, tmode
)
10711 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
10712 - GET_MODE_BITSIZE (mode
)))))
10714 /* If OP0 is an AND and we don't have an AND in MODE either,
10715 make a new AND in the proper mode. */
10716 if (GET_CODE (op0
) == AND
10717 && !have_insn_for (AND
, mode
))
10718 op0
= gen_binary (AND
, tmode
,
10719 gen_lowpart (tmode
,
10721 gen_lowpart (tmode
,
10724 op0
= gen_lowpart (tmode
, op0
);
10725 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
10726 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
10727 op1
= gen_lowpart (tmode
, op1
);
10731 /* If this is a test for negative, we can make an explicit
10732 test of the sign bit. */
10734 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
10735 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10737 op0
= gen_binary (AND
, tmode
,
10738 gen_lowpart (tmode
, op0
),
10739 GEN_INT ((HOST_WIDE_INT
) 1
10740 << (GET_MODE_BITSIZE (mode
) - 1)));
10741 code
= (code
== LT
) ? NE
: EQ
;
10746 #ifdef CANONICALIZE_COMPARISON
10747 /* If this machine only supports a subset of valid comparisons, see if we
10748 can convert an unsupported one into a supported one. */
10749 CANONICALIZE_COMPARISON (code
, op0
, op1
);
10758 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
10759 searching backward. */
10760 static enum rtx_code
10761 combine_reversed_comparison_code (rtx exp
)
10763 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
10766 if (code1
!= UNKNOWN
10767 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
10769 /* Otherwise try and find where the condition codes were last set and
10771 x
= get_last_value (XEXP (exp
, 0));
10772 if (!x
|| GET_CODE (x
) != COMPARE
)
10774 return reversed_comparison_code_parts (GET_CODE (exp
),
10775 XEXP (x
, 0), XEXP (x
, 1), NULL
);
10778 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
10779 Return NULL_RTX in case we fail to do the reversal. */
10781 reversed_comparison (rtx exp
, enum machine_mode mode
, rtx op0
, rtx op1
)
10783 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
10784 if (reversed_code
== UNKNOWN
)
10787 return gen_binary (reversed_code
, mode
, op0
, op1
);
10790 /* Utility function for record_value_for_reg. Count number of
10795 enum rtx_code code
= GET_CODE (x
);
10799 if (GET_RTX_CLASS (code
) == '2'
10800 || GET_RTX_CLASS (code
) == 'c')
10802 rtx x0
= XEXP (x
, 0);
10803 rtx x1
= XEXP (x
, 1);
10806 return 1 + 2 * count_rtxs (x0
);
10808 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
10809 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
10810 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
10811 return 2 + 2 * count_rtxs (x0
)
10812 + count_rtxs (x
== XEXP (x1
, 0)
10813 ? XEXP (x1
, 1) : XEXP (x1
, 0));
10815 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
10816 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
10817 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
10818 return 2 + 2 * count_rtxs (x1
)
10819 + count_rtxs (x
== XEXP (x0
, 0)
10820 ? XEXP (x0
, 1) : XEXP (x0
, 0));
10823 fmt
= GET_RTX_FORMAT (code
);
10824 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10826 ret
+= count_rtxs (XEXP (x
, i
));
10831 /* Utility function for following routine. Called when X is part of a value
10832 being stored into last_set_value. Sets last_set_table_tick
10833 for each register mentioned. Similar to mention_regs in cse.c */
10836 update_table_tick (rtx x
)
10838 enum rtx_code code
= GET_CODE (x
);
10839 const char *fmt
= GET_RTX_FORMAT (code
);
10844 unsigned int regno
= REGNO (x
);
10845 unsigned int endregno
10846 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10847 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
10850 for (r
= regno
; r
< endregno
; r
++)
10851 reg_stat
[r
].last_set_table_tick
= label_tick
;
10856 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10857 /* Note that we can't have an "E" in values stored; see
10858 get_last_value_validate. */
10861 /* Check for identical subexpressions. If x contains
10862 identical subexpression we only have to traverse one of
10864 if (i
== 0 && ARITHMETIC_P (x
))
10866 /* Note that at this point x1 has already been
10868 rtx x0
= XEXP (x
, 0);
10869 rtx x1
= XEXP (x
, 1);
10871 /* If x0 and x1 are identical then there is no need to
10876 /* If x0 is identical to a subexpression of x1 then while
10877 processing x1, x0 has already been processed. Thus we
10878 are done with x. */
10879 if (ARITHMETIC_P (x1
)
10880 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
10883 /* If x1 is identical to a subexpression of x0 then we
10884 still have to process the rest of x0. */
10885 if (ARITHMETIC_P (x0
)
10886 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
10888 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
10893 update_table_tick (XEXP (x
, i
));
10897 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10898 are saying that the register is clobbered and we no longer know its
10899 value. If INSN is zero, don't update reg_stat[].last_set; this is
10900 only permitted with VALUE also zero and is used to invalidate the
10904 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
10906 unsigned int regno
= REGNO (reg
);
10907 unsigned int endregno
10908 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10909 ? hard_regno_nregs
[regno
][GET_MODE (reg
)] : 1);
10912 /* If VALUE contains REG and we have a previous value for REG, substitute
10913 the previous value. */
10914 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
10918 /* Set things up so get_last_value is allowed to see anything set up to
10920 subst_low_cuid
= INSN_CUID (insn
);
10921 tem
= get_last_value (reg
);
10923 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10924 it isn't going to be useful and will take a lot of time to process,
10925 so just use the CLOBBER. */
10929 if (ARITHMETIC_P (tem
)
10930 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
10931 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
10932 tem
= XEXP (tem
, 0);
10933 else if (count_occurrences (value
, reg
, 1) >= 2)
10935 /* If there are two or more occurrences of REG in VALUE,
10936 prevent the value from growing too much. */
10937 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
10938 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
10941 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
10945 /* For each register modified, show we don't know its value, that
10946 we don't know about its bitwise content, that its value has been
10947 updated, and that we don't know the location of the death of the
10949 for (i
= regno
; i
< endregno
; i
++)
10952 reg_stat
[i
].last_set
= insn
;
10954 reg_stat
[i
].last_set_value
= 0;
10955 reg_stat
[i
].last_set_mode
= 0;
10956 reg_stat
[i
].last_set_nonzero_bits
= 0;
10957 reg_stat
[i
].last_set_sign_bit_copies
= 0;
10958 reg_stat
[i
].last_death
= 0;
10961 /* Mark registers that are being referenced in this value. */
10963 update_table_tick (value
);
10965 /* Now update the status of each register being set.
10966 If someone is using this register in this block, set this register
10967 to invalid since we will get confused between the two lives in this
10968 basic block. This makes using this register always invalid. In cse, we
10969 scan the table to invalidate all entries using this register, but this
10970 is too much work for us. */
10972 for (i
= regno
; i
< endregno
; i
++)
10974 reg_stat
[i
].last_set_label
= label_tick
;
10975 if (value
&& reg_stat
[i
].last_set_table_tick
== label_tick
)
10976 reg_stat
[i
].last_set_invalid
= 1;
10978 reg_stat
[i
].last_set_invalid
= 0;
10981 /* The value being assigned might refer to X (like in "x++;"). In that
10982 case, we must replace it with (clobber (const_int 0)) to prevent
10984 if (value
&& ! get_last_value_validate (&value
, insn
,
10985 reg_stat
[regno
].last_set_label
, 0))
10987 value
= copy_rtx (value
);
10988 if (! get_last_value_validate (&value
, insn
,
10989 reg_stat
[regno
].last_set_label
, 1))
10993 /* For the main register being modified, update the value, the mode, the
10994 nonzero bits, and the number of sign bit copies. */
10996 reg_stat
[regno
].last_set_value
= value
;
11000 enum machine_mode mode
= GET_MODE (reg
);
11001 subst_low_cuid
= INSN_CUID (insn
);
11002 reg_stat
[regno
].last_set_mode
= mode
;
11003 if (GET_MODE_CLASS (mode
) == MODE_INT
11004 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11005 mode
= nonzero_bits_mode
;
11006 reg_stat
[regno
].last_set_nonzero_bits
= nonzero_bits (value
, mode
);
11007 reg_stat
[regno
].last_set_sign_bit_copies
11008 = num_sign_bit_copies (value
, GET_MODE (reg
));
11012 /* Called via note_stores from record_dead_and_set_regs to handle one
11013 SET or CLOBBER in an insn. DATA is the instruction in which the
11014 set is occurring. */
11017 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
11019 rtx record_dead_insn
= (rtx
) data
;
11021 if (GET_CODE (dest
) == SUBREG
)
11022 dest
= SUBREG_REG (dest
);
11026 /* If we are setting the whole register, we know its value. Otherwise
11027 show that we don't know the value. We can handle SUBREG in
11029 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11030 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11031 else if (GET_CODE (setter
) == SET
11032 && GET_CODE (SET_DEST (setter
)) == SUBREG
11033 && SUBREG_REG (SET_DEST (setter
)) == dest
11034 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11035 && subreg_lowpart_p (SET_DEST (setter
)))
11036 record_value_for_reg (dest
, record_dead_insn
,
11037 gen_lowpart (GET_MODE (dest
),
11038 SET_SRC (setter
)));
11040 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11042 else if (MEM_P (dest
)
11043 /* Ignore pushes, they clobber nothing. */
11044 && ! push_operand (dest
, GET_MODE (dest
)))
11045 mem_last_set
= INSN_CUID (record_dead_insn
);
11048 /* Update the records of when each REG was most recently set or killed
11049 for the things done by INSN. This is the last thing done in processing
11050 INSN in the combiner loop.
11052 We update reg_stat[], in particular fields last_set, last_set_value,
11053 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11054 last_death, and also the similar information mem_last_set (which insn
11055 most recently modified memory) and last_call_cuid (which insn was the
11056 most recent subroutine call). */
11059 record_dead_and_set_regs (rtx insn
)
11064 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11066 if (REG_NOTE_KIND (link
) == REG_DEAD
11067 && REG_P (XEXP (link
, 0)))
11069 unsigned int regno
= REGNO (XEXP (link
, 0));
11070 unsigned int endregno
11071 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11072 ? hard_regno_nregs
[regno
][GET_MODE (XEXP (link
, 0))]
11075 for (i
= regno
; i
< endregno
; i
++)
11076 reg_stat
[i
].last_death
= insn
;
11078 else if (REG_NOTE_KIND (link
) == REG_INC
)
11079 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11084 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11085 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11087 reg_stat
[i
].last_set_value
= 0;
11088 reg_stat
[i
].last_set_mode
= 0;
11089 reg_stat
[i
].last_set_nonzero_bits
= 0;
11090 reg_stat
[i
].last_set_sign_bit_copies
= 0;
11091 reg_stat
[i
].last_death
= 0;
11094 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11096 /* Don't bother recording what this insn does. It might set the
11097 return value register, but we can't combine into a call
11098 pattern anyway, so there's no point trying (and it may cause
11099 a crash, if e.g. we wind up asking for last_set_value of a
11100 SUBREG of the return value register). */
11104 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11107 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11108 register present in the SUBREG, so for each such SUBREG go back and
11109 adjust nonzero and sign bit information of the registers that are
11110 known to have some zero/sign bits set.
11112 This is needed because when combine blows the SUBREGs away, the
11113 information on zero/sign bits is lost and further combines can be
11114 missed because of that. */
11117 record_promoted_value (rtx insn
, rtx subreg
)
11120 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11121 enum machine_mode mode
= GET_MODE (subreg
);
11123 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11126 for (links
= LOG_LINKS (insn
); links
;)
11128 insn
= XEXP (links
, 0);
11129 set
= single_set (insn
);
11131 if (! set
|| !REG_P (SET_DEST (set
))
11132 || REGNO (SET_DEST (set
)) != regno
11133 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11135 links
= XEXP (links
, 1);
11139 if (reg_stat
[regno
].last_set
== insn
)
11141 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11142 reg_stat
[regno
].last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
11145 if (REG_P (SET_SRC (set
)))
11147 regno
= REGNO (SET_SRC (set
));
11148 links
= LOG_LINKS (insn
);
11155 /* Scan X for promoted SUBREGs. For each one found,
11156 note what it implies to the registers used in it. */
11159 check_promoted_subreg (rtx insn
, rtx x
)
11161 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11162 && REG_P (SUBREG_REG (x
)))
11163 record_promoted_value (insn
, x
);
11166 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11169 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11173 check_promoted_subreg (insn
, XEXP (x
, i
));
11177 if (XVEC (x
, i
) != 0)
11178 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11179 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11185 /* Utility routine for the following function. Verify that all the registers
11186 mentioned in *LOC are valid when *LOC was part of a value set when
11187 label_tick == TICK. Return 0 if some are not.
11189 If REPLACE is nonzero, replace the invalid reference with
11190 (clobber (const_int 0)) and return 1. This replacement is useful because
11191 we often can get useful information about the form of a value (e.g., if
11192 it was produced by a shift that always produces -1 or 0) even though
11193 we don't know exactly what registers it was produced from. */
11196 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11199 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11200 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11205 unsigned int regno
= REGNO (x
);
11206 unsigned int endregno
11207 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11208 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11211 for (j
= regno
; j
< endregno
; j
++)
11212 if (reg_stat
[j
].last_set_invalid
11213 /* If this is a pseudo-register that was only set once and not
11214 live at the beginning of the function, it is always valid. */
11215 || (! (regno
>= FIRST_PSEUDO_REGISTER
11216 && REG_N_SETS (regno
) == 1
11217 && (! REGNO_REG_SET_P
11218 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))
11219 && reg_stat
[j
].last_set_label
> tick
))
11222 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11228 /* If this is a memory reference, make sure that there were
11229 no stores after it that might have clobbered the value. We don't
11230 have alias info, so we assume any store invalidates it. */
11231 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
11232 && INSN_CUID (insn
) <= mem_last_set
)
11235 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11239 for (i
= 0; i
< len
; i
++)
11243 /* Check for identical subexpressions. If x contains
11244 identical subexpression we only have to traverse one of
11246 if (i
== 1 && ARITHMETIC_P (x
))
11248 /* Note that at this point x0 has already been checked
11249 and found valid. */
11250 rtx x0
= XEXP (x
, 0);
11251 rtx x1
= XEXP (x
, 1);
11253 /* If x0 and x1 are identical then x is also valid. */
11257 /* If x1 is identical to a subexpression of x0 then
11258 while checking x0, x1 has already been checked. Thus
11259 it is valid and so as x. */
11260 if (ARITHMETIC_P (x0
)
11261 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11264 /* If x0 is identical to a subexpression of x1 then x is
11265 valid iff the rest of x1 is valid. */
11266 if (ARITHMETIC_P (x1
)
11267 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11269 get_last_value_validate (&XEXP (x1
,
11270 x0
== XEXP (x1
, 0) ? 1 : 0),
11271 insn
, tick
, replace
);
11274 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11278 /* Don't bother with these. They shouldn't occur anyway. */
11279 else if (fmt
[i
] == 'E')
11283 /* If we haven't found a reason for it to be invalid, it is valid. */
11287 /* Get the last value assigned to X, if known. Some registers
11288 in the value may be replaced with (clobber (const_int 0)) if their value
11289 is known longer known reliably. */
11292 get_last_value (rtx x
)
11294 unsigned int regno
;
11297 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11298 then convert it to the desired mode. If this is a paradoxical SUBREG,
11299 we cannot predict what values the "extra" bits might have. */
11300 if (GET_CODE (x
) == SUBREG
11301 && subreg_lowpart_p (x
)
11302 && (GET_MODE_SIZE (GET_MODE (x
))
11303 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11304 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11305 return gen_lowpart (GET_MODE (x
), value
);
11311 value
= reg_stat
[regno
].last_set_value
;
11313 /* If we don't have a value, or if it isn't for this basic block and
11314 it's either a hard register, set more than once, or it's a live
11315 at the beginning of the function, return 0.
11317 Because if it's not live at the beginning of the function then the reg
11318 is always set before being used (is never used without being set).
11319 And, if it's set only once, and it's always set before use, then all
11320 uses must have the same last value, even if it's not from this basic
11324 || (reg_stat
[regno
].last_set_label
!= label_tick
11325 && (regno
< FIRST_PSEUDO_REGISTER
11326 || REG_N_SETS (regno
) != 1
11327 || (REGNO_REG_SET_P
11328 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))))
11331 /* If the value was set in a later insn than the ones we are processing,
11332 we can't use it even if the register was only set once. */
11333 if (INSN_CUID (reg_stat
[regno
].last_set
) >= subst_low_cuid
)
11336 /* If the value has all its registers valid, return it. */
11337 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11338 reg_stat
[regno
].last_set_label
, 0))
11341 /* Otherwise, make a copy and replace any invalid register with
11342 (clobber (const_int 0)). If that fails for some reason, return 0. */
11344 value
= copy_rtx (value
);
11345 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11346 reg_stat
[regno
].last_set_label
, 1))
11352 /* Return nonzero if expression X refers to a REG or to memory
11353 that is set in an instruction more recent than FROM_CUID. */
11356 use_crosses_set_p (rtx x
, int from_cuid
)
11360 enum rtx_code code
= GET_CODE (x
);
11364 unsigned int regno
= REGNO (x
);
11365 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11366 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11368 #ifdef PUSH_ROUNDING
11369 /* Don't allow uses of the stack pointer to be moved,
11370 because we don't know whether the move crosses a push insn. */
11371 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11374 for (; regno
< endreg
; regno
++)
11375 if (reg_stat
[regno
].last_set
11376 && INSN_CUID (reg_stat
[regno
].last_set
) > from_cuid
)
11381 if (code
== MEM
&& mem_last_set
> from_cuid
)
11384 fmt
= GET_RTX_FORMAT (code
);
11386 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11391 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11392 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11395 else if (fmt
[i
] == 'e'
11396 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11402 /* Define three variables used for communication between the following
11405 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11406 static int reg_dead_flag
;
11408 /* Function called via note_stores from reg_dead_at_p.
11410 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11411 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11414 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
11416 unsigned int regno
, endregno
;
11421 regno
= REGNO (dest
);
11422 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11423 ? hard_regno_nregs
[regno
][GET_MODE (dest
)] : 1);
11425 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11426 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11429 /* Return nonzero if REG is known to be dead at INSN.
11431 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11432 referencing REG, it is dead. If we hit a SET referencing REG, it is
11433 live. Otherwise, see if it is live or dead at the start of the basic
11434 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11435 must be assumed to be always live. */
11438 reg_dead_at_p (rtx reg
, rtx insn
)
11443 /* Set variables for reg_dead_at_p_1. */
11444 reg_dead_regno
= REGNO (reg
);
11445 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11446 ? hard_regno_nregs
[reg_dead_regno
]
11452 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11453 we allow the machine description to decide whether use-and-clobber
11454 patterns are OK. */
11455 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11457 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11458 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11462 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11463 beginning of function. */
11464 for (; insn
&& !LABEL_P (insn
) && !BARRIER_P (insn
);
11465 insn
= prev_nonnote_insn (insn
))
11467 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11469 return reg_dead_flag
== 1 ? 1 : 0;
11471 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11475 /* Get the basic block that we were in. */
11477 block
= ENTRY_BLOCK_PTR
->next_bb
;
11480 FOR_EACH_BB (block
)
11481 if (insn
== BB_HEAD (block
))
11484 if (block
== EXIT_BLOCK_PTR
)
11488 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11489 if (REGNO_REG_SET_P (block
->global_live_at_start
, i
))
11495 /* Note hard registers in X that are used. This code is similar to
11496 that in flow.c, but much simpler since we don't care about pseudos. */
11499 mark_used_regs_combine (rtx x
)
11501 RTX_CODE code
= GET_CODE (x
);
11502 unsigned int regno
;
11515 case ADDR_DIFF_VEC
:
11518 /* CC0 must die in the insn after it is set, so we don't need to take
11519 special note of it here. */
11525 /* If we are clobbering a MEM, mark any hard registers inside the
11526 address as used. */
11527 if (MEM_P (XEXP (x
, 0)))
11528 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11533 /* A hard reg in a wide mode may really be multiple registers.
11534 If so, mark all of them just like the first. */
11535 if (regno
< FIRST_PSEUDO_REGISTER
)
11537 unsigned int endregno
, r
;
11539 /* None of this applies to the stack, frame or arg pointers. */
11540 if (regno
== STACK_POINTER_REGNUM
11541 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11542 || regno
== HARD_FRAME_POINTER_REGNUM
11544 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11545 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11547 || regno
== FRAME_POINTER_REGNUM
)
11550 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11551 for (r
= regno
; r
< endregno
; r
++)
11552 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11558 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11560 rtx testreg
= SET_DEST (x
);
11562 while (GET_CODE (testreg
) == SUBREG
11563 || GET_CODE (testreg
) == ZERO_EXTRACT
11564 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11565 testreg
= XEXP (testreg
, 0);
11567 if (MEM_P (testreg
))
11568 mark_used_regs_combine (XEXP (testreg
, 0));
11570 mark_used_regs_combine (SET_SRC (x
));
11578 /* Recursively scan the operands of this expression. */
11581 const char *fmt
= GET_RTX_FORMAT (code
);
11583 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11586 mark_used_regs_combine (XEXP (x
, i
));
11587 else if (fmt
[i
] == 'E')
11591 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11592 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11598 /* Remove register number REGNO from the dead registers list of INSN.
11600 Return the note used to record the death, if there was one. */
11603 remove_death (unsigned int regno
, rtx insn
)
11605 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11609 REG_N_DEATHS (regno
)--;
11610 remove_note (insn
, note
);
11616 /* For each register (hardware or pseudo) used within expression X, if its
11617 death is in an instruction with cuid between FROM_CUID (inclusive) and
11618 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11619 list headed by PNOTES.
11621 That said, don't move registers killed by maybe_kill_insn.
11623 This is done when X is being merged by combination into TO_INSN. These
11624 notes will then be distributed as needed. */
11627 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_cuid
, rtx to_insn
,
11632 enum rtx_code code
= GET_CODE (x
);
11636 unsigned int regno
= REGNO (x
);
11637 rtx where_dead
= reg_stat
[regno
].last_death
;
11638 rtx before_dead
, after_dead
;
11640 /* Don't move the register if it gets killed in between from and to. */
11641 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11642 && ! reg_referenced_p (x
, maybe_kill_insn
))
11645 /* WHERE_DEAD could be a USE insn made by combine, so first we
11646 make sure that we have insns with valid INSN_CUID values. */
11647 before_dead
= where_dead
;
11648 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11649 before_dead
= PREV_INSN (before_dead
);
11651 after_dead
= where_dead
;
11652 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11653 after_dead
= NEXT_INSN (after_dead
);
11655 if (before_dead
&& after_dead
11656 && INSN_CUID (before_dead
) >= from_cuid
11657 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11658 || (where_dead
!= after_dead
11659 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11661 rtx note
= remove_death (regno
, where_dead
);
11663 /* It is possible for the call above to return 0. This can occur
11664 when last_death points to I2 or I1 that we combined with.
11665 In that case make a new note.
11667 We must also check for the case where X is a hard register
11668 and NOTE is a death note for a range of hard registers
11669 including X. In that case, we must put REG_DEAD notes for
11670 the remaining registers in place of NOTE. */
11672 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11673 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11674 > GET_MODE_SIZE (GET_MODE (x
))))
11676 unsigned int deadregno
= REGNO (XEXP (note
, 0));
11677 unsigned int deadend
11678 = (deadregno
+ hard_regno_nregs
[deadregno
]
11679 [GET_MODE (XEXP (note
, 0))]);
11680 unsigned int ourend
11681 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11684 for (i
= deadregno
; i
< deadend
; i
++)
11685 if (i
< regno
|| i
>= ourend
)
11686 REG_NOTES (where_dead
)
11687 = gen_rtx_EXPR_LIST (REG_DEAD
,
11689 REG_NOTES (where_dead
));
11692 /* If we didn't find any note, or if we found a REG_DEAD note that
11693 covers only part of the given reg, and we have a multi-reg hard
11694 register, then to be safe we must check for REG_DEAD notes
11695 for each register other than the first. They could have
11696 their own REG_DEAD notes lying around. */
11697 else if ((note
== 0
11699 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11700 < GET_MODE_SIZE (GET_MODE (x
)))))
11701 && regno
< FIRST_PSEUDO_REGISTER
11702 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
11704 unsigned int ourend
11705 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11706 unsigned int i
, offset
;
11710 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
11714 for (i
= regno
+ offset
; i
< ourend
; i
++)
11715 move_deaths (regno_reg_rtx
[i
],
11716 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
11719 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
11721 XEXP (note
, 1) = *pnotes
;
11725 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
11727 REG_N_DEATHS (regno
)++;
11733 else if (GET_CODE (x
) == SET
)
11735 rtx dest
= SET_DEST (x
);
11737 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11739 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11740 that accesses one word of a multi-word item, some
11741 piece of everything register in the expression is used by
11742 this insn, so remove any old death. */
11743 /* ??? So why do we test for equality of the sizes? */
11745 if (GET_CODE (dest
) == ZERO_EXTRACT
11746 || GET_CODE (dest
) == STRICT_LOW_PART
11747 || (GET_CODE (dest
) == SUBREG
11748 && (((GET_MODE_SIZE (GET_MODE (dest
))
11749 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
11750 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
11751 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
11753 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11757 /* If this is some other SUBREG, we know it replaces the entire
11758 value, so use that as the destination. */
11759 if (GET_CODE (dest
) == SUBREG
)
11760 dest
= SUBREG_REG (dest
);
11762 /* If this is a MEM, adjust deaths of anything used in the address.
11763 For a REG (the only other possibility), the entire value is
11764 being replaced so the old value is not used in this insn. */
11767 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
11772 else if (GET_CODE (x
) == CLOBBER
)
11775 len
= GET_RTX_LENGTH (code
);
11776 fmt
= GET_RTX_FORMAT (code
);
11778 for (i
= 0; i
< len
; i
++)
11783 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11784 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
11787 else if (fmt
[i
] == 'e')
11788 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11792 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11793 pattern of an insn. X must be a REG. */
11796 reg_bitfield_target_p (rtx x
, rtx body
)
11800 if (GET_CODE (body
) == SET
)
11802 rtx dest
= SET_DEST (body
);
11804 unsigned int regno
, tregno
, endregno
, endtregno
;
11806 if (GET_CODE (dest
) == ZERO_EXTRACT
)
11807 target
= XEXP (dest
, 0);
11808 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
11809 target
= SUBREG_REG (XEXP (dest
, 0));
11813 if (GET_CODE (target
) == SUBREG
)
11814 target
= SUBREG_REG (target
);
11816 if (!REG_P (target
))
11819 tregno
= REGNO (target
), regno
= REGNO (x
);
11820 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
11821 return target
== x
;
11823 endtregno
= tregno
+ hard_regno_nregs
[tregno
][GET_MODE (target
)];
11824 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11826 return endregno
> tregno
&& regno
< endtregno
;
11829 else if (GET_CODE (body
) == PARALLEL
)
11830 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
11831 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
11837 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11838 as appropriate. I3 and I2 are the insns resulting from the combination
11839 insns including FROM (I2 may be zero).
11841 Each note in the list is either ignored or placed on some insns, depending
11842 on the type of note. */
11845 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
)
11847 rtx note
, next_note
;
11850 for (note
= notes
; note
; note
= next_note
)
11852 rtx place
= 0, place2
= 0;
11854 /* If this NOTE references a pseudo register, ensure it references
11855 the latest copy of that register. */
11856 if (XEXP (note
, 0) && REG_P (XEXP (note
, 0))
11857 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
11858 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
11860 next_note
= XEXP (note
, 1);
11861 switch (REG_NOTE_KIND (note
))
11865 /* Doesn't matter much where we put this, as long as it's somewhere.
11866 It is preferable to keep these notes on branches, which is most
11867 likely to be i3. */
11871 case REG_VALUE_PROFILE
:
11872 /* Just get rid of this note, as it is unused later anyway. */
11875 case REG_NON_LOCAL_GOTO
:
11880 gcc_assert (i2
&& JUMP_P (i2
));
11885 case REG_EH_REGION
:
11886 /* These notes must remain with the call or trapping instruction. */
11889 else if (i2
&& CALL_P (i2
))
11893 gcc_assert (flag_non_call_exceptions
);
11894 if (may_trap_p (i3
))
11896 else if (i2
&& may_trap_p (i2
))
11898 /* ??? Otherwise assume we've combined things such that we
11899 can now prove that the instructions can't trap. Drop the
11900 note in this case. */
11906 /* These notes must remain with the call. It should not be
11907 possible for both I2 and I3 to be a call. */
11912 gcc_assert (i2
&& CALL_P (i2
));
11918 /* Any clobbers for i3 may still exist, and so we must process
11919 REG_UNUSED notes from that insn.
11921 Any clobbers from i2 or i1 can only exist if they were added by
11922 recog_for_combine. In that case, recog_for_combine created the
11923 necessary REG_UNUSED notes. Trying to keep any original
11924 REG_UNUSED notes from these insns can cause incorrect output
11925 if it is for the same register as the original i3 dest.
11926 In that case, we will notice that the register is set in i3,
11927 and then add a REG_UNUSED note for the destination of i3, which
11928 is wrong. However, it is possible to have REG_UNUSED notes from
11929 i2 or i1 for register which were both used and clobbered, so
11930 we keep notes from i2 or i1 if they will turn into REG_DEAD
11933 /* If this register is set or clobbered in I3, put the note there
11934 unless there is one already. */
11935 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
11937 if (from_insn
!= i3
)
11940 if (! (REG_P (XEXP (note
, 0))
11941 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
11942 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
11945 /* Otherwise, if this register is used by I3, then this register
11946 now dies here, so we must put a REG_DEAD note here unless there
11948 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
11949 && ! (REG_P (XEXP (note
, 0))
11950 ? find_regno_note (i3
, REG_DEAD
,
11951 REGNO (XEXP (note
, 0)))
11952 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
11954 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
11962 /* These notes say something about results of an insn. We can
11963 only support them if they used to be on I3 in which case they
11964 remain on I3. Otherwise they are ignored.
11966 If the note refers to an expression that is not a constant, we
11967 must also ignore the note since we cannot tell whether the
11968 equivalence is still true. It might be possible to do
11969 slightly better than this (we only have a problem if I2DEST
11970 or I1DEST is present in the expression), but it doesn't
11971 seem worth the trouble. */
11973 if (from_insn
== i3
11974 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
11979 case REG_NO_CONFLICT
:
11980 /* These notes say something about how a register is used. They must
11981 be present on any use of the register in I2 or I3. */
11982 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
11985 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
11995 /* This can show up in several ways -- either directly in the
11996 pattern, or hidden off in the constant pool with (or without?)
11997 a REG_EQUAL note. */
11998 /* ??? Ignore the without-reg_equal-note problem for now. */
11999 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12000 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12001 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12002 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12006 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12007 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12008 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12009 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12017 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
12018 a JUMP_LABEL instead or decrement LABEL_NUSES. */
12019 if (place
&& JUMP_P (place
))
12021 rtx label
= JUMP_LABEL (place
);
12024 JUMP_LABEL (place
) = XEXP (note
, 0);
12027 gcc_assert (label
== XEXP (note
, 0));
12028 if (LABEL_P (label
))
12029 LABEL_NUSES (label
)--;
12033 if (place2
&& JUMP_P (place2
))
12035 rtx label
= JUMP_LABEL (place2
);
12038 JUMP_LABEL (place2
) = XEXP (note
, 0);
12041 gcc_assert (label
== XEXP (note
, 0));
12042 if (LABEL_P (label
))
12043 LABEL_NUSES (label
)--;
12050 /* This note says something about the value of a register prior
12051 to the execution of an insn. It is too much trouble to see
12052 if the note is still correct in all situations. It is better
12053 to simply delete it. */
12057 /* If the insn previously containing this note still exists,
12058 put it back where it was. Otherwise move it to the previous
12059 insn. Adjust the corresponding REG_LIBCALL note. */
12060 if (!NOTE_P (from_insn
))
12064 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12065 place
= prev_real_insn (from_insn
);
12067 XEXP (tem
, 0) = place
;
12068 /* If we're deleting the last remaining instruction of a
12069 libcall sequence, don't add the notes. */
12070 else if (XEXP (note
, 0) == from_insn
)
12072 /* Don't add the dangling REG_RETVAL note. */
12079 /* This is handled similarly to REG_RETVAL. */
12080 if (!NOTE_P (from_insn
))
12084 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12085 place
= next_real_insn (from_insn
);
12087 XEXP (tem
, 0) = place
;
12088 /* If we're deleting the last remaining instruction of a
12089 libcall sequence, don't add the notes. */
12090 else if (XEXP (note
, 0) == from_insn
)
12092 /* Don't add the dangling REG_LIBCALL note. */
12099 /* If the register is used as an input in I3, it dies there.
12100 Similarly for I2, if it is nonzero and adjacent to I3.
12102 If the register is not used as an input in either I3 or I2
12103 and it is not one of the registers we were supposed to eliminate,
12104 there are two possibilities. We might have a non-adjacent I2
12105 or we might have somehow eliminated an additional register
12106 from a computation. For example, we might have had A & B where
12107 we discover that B will always be zero. In this case we will
12108 eliminate the reference to A.
12110 In both cases, we must search to see if we can find a previous
12111 use of A and put the death note there. */
12114 && CALL_P (from_insn
)
12115 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12117 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12119 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12120 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12125 basic_block bb
= this_basic_block
;
12127 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12129 if (! INSN_P (tem
))
12131 if (tem
== BB_HEAD (bb
))
12136 /* If the register is being set at TEM, see if that is all
12137 TEM is doing. If so, delete TEM. Otherwise, make this
12138 into a REG_UNUSED note instead. Don't delete sets to
12139 global register vars. */
12140 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
12141 || !global_regs
[REGNO (XEXP (note
, 0))])
12142 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12144 rtx set
= single_set (tem
);
12145 rtx inner_dest
= 0;
12147 rtx cc0_setter
= NULL_RTX
;
12151 for (inner_dest
= SET_DEST (set
);
12152 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12153 || GET_CODE (inner_dest
) == SUBREG
12154 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12155 inner_dest
= XEXP (inner_dest
, 0))
12158 /* Verify that it was the set, and not a clobber that
12159 modified the register.
12161 CC0 targets must be careful to maintain setter/user
12162 pairs. If we cannot delete the setter due to side
12163 effects, mark the user with an UNUSED note instead
12166 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12167 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12169 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12170 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12171 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12175 /* Move the notes and links of TEM elsewhere.
12176 This might delete other dead insns recursively.
12177 First set the pattern to something that won't use
12179 rtx old_notes
= REG_NOTES (tem
);
12181 PATTERN (tem
) = pc_rtx
;
12182 REG_NOTES (tem
) = NULL
;
12184 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
);
12185 distribute_links (LOG_LINKS (tem
));
12187 SET_INSN_DELETED (tem
);
12190 /* Delete the setter too. */
12193 PATTERN (cc0_setter
) = pc_rtx
;
12194 old_notes
= REG_NOTES (cc0_setter
);
12195 REG_NOTES (cc0_setter
) = NULL
;
12197 distribute_notes (old_notes
, cc0_setter
,
12198 cc0_setter
, NULL_RTX
);
12199 distribute_links (LOG_LINKS (cc0_setter
));
12201 SET_INSN_DELETED (cc0_setter
);
12207 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12209 /* If there isn't already a REG_UNUSED note, put one
12210 here. Do not place a REG_DEAD note, even if
12211 the register is also used here; that would not
12212 match the algorithm used in lifetime analysis
12213 and can cause the consistency check in the
12214 scheduler to fail. */
12215 if (! find_regno_note (tem
, REG_UNUSED
,
12216 REGNO (XEXP (note
, 0))))
12221 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12223 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12227 /* If we are doing a 3->2 combination, and we have a
12228 register which formerly died in i3 and was not used
12229 by i2, which now no longer dies in i3 and is used in
12230 i2 but does not die in i2, and place is between i2
12231 and i3, then we may need to move a link from place to
12233 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12234 && INSN_CUID (place
) > INSN_CUID (i2
)
12236 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12237 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12239 rtx links
= LOG_LINKS (place
);
12240 LOG_LINKS (place
) = 0;
12241 distribute_links (links
);
12246 if (tem
== BB_HEAD (bb
))
12250 /* We haven't found an insn for the death note and it
12251 is still a REG_DEAD note, but we have hit the beginning
12252 of the block. If the existing life info says the reg
12253 was dead, there's nothing left to do. Otherwise, we'll
12254 need to do a global life update after combine. */
12255 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12256 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12257 REGNO (XEXP (note
, 0))))
12258 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12261 /* If the register is set or already dead at PLACE, we needn't do
12262 anything with this note if it is still a REG_DEAD note.
12263 We check here if it is set at all, not if is it totally replaced,
12264 which is what `dead_or_set_p' checks, so also check for it being
12267 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12269 unsigned int regno
= REGNO (XEXP (note
, 0));
12271 /* Similarly, if the instruction on which we want to place
12272 the note is a noop, we'll need do a global live update
12273 after we remove them in delete_noop_moves. */
12274 if (noop_move_p (place
))
12275 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12277 if (dead_or_set_p (place
, XEXP (note
, 0))
12278 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12280 /* Unless the register previously died in PLACE, clear
12281 last_death. [I no longer understand why this is
12283 if (reg_stat
[regno
].last_death
!= place
)
12284 reg_stat
[regno
].last_death
= 0;
12288 reg_stat
[regno
].last_death
= place
;
12290 /* If this is a death note for a hard reg that is occupying
12291 multiple registers, ensure that we are still using all
12292 parts of the object. If we find a piece of the object
12293 that is unused, we must arrange for an appropriate REG_DEAD
12294 note to be added for it. However, we can't just emit a USE
12295 and tag the note to it, since the register might actually
12296 be dead; so we recourse, and the recursive call then finds
12297 the previous insn that used this register. */
12299 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12300 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
12302 unsigned int endregno
12303 = regno
+ hard_regno_nregs
[regno
]
12304 [GET_MODE (XEXP (note
, 0))];
12308 for (i
= regno
; i
< endregno
; i
++)
12309 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12310 && ! find_regno_fusage (place
, USE
, i
))
12311 || dead_or_set_regno_p (place
, i
))
12316 /* Put only REG_DEAD notes for pieces that are
12317 not already dead or set. */
12319 for (i
= regno
; i
< endregno
;
12320 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
12322 rtx piece
= regno_reg_rtx
[i
];
12323 basic_block bb
= this_basic_block
;
12325 if (! dead_or_set_p (place
, piece
)
12326 && ! reg_bitfield_target_p (piece
,
12330 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12332 distribute_notes (new_note
, place
, place
,
12335 else if (! refers_to_regno_p (i
, i
+ 1,
12336 PATTERN (place
), 0)
12337 && ! find_regno_fusage (place
, USE
, i
))
12338 for (tem
= PREV_INSN (place
); ;
12339 tem
= PREV_INSN (tem
))
12341 if (! INSN_P (tem
))
12343 if (tem
== BB_HEAD (bb
))
12345 SET_BIT (refresh_blocks
,
12346 this_basic_block
->index
);
12351 if (dead_or_set_p (tem
, piece
)
12352 || reg_bitfield_target_p (piece
,
12356 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12371 /* Any other notes should not be present at this point in the
12373 gcc_unreachable ();
12378 XEXP (note
, 1) = REG_NOTES (place
);
12379 REG_NOTES (place
) = note
;
12381 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12382 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12383 && REG_P (XEXP (note
, 0)))
12384 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12388 if ((REG_NOTE_KIND (note
) == REG_DEAD
12389 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12390 && REG_P (XEXP (note
, 0)))
12391 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12393 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12394 REG_NOTE_KIND (note
),
12396 REG_NOTES (place2
));
12401 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12402 I3, I2, and I1 to new locations. This is also called to add a link
12403 pointing at I3 when I3's destination is changed. */
12406 distribute_links (rtx links
)
12408 rtx link
, next_link
;
12410 for (link
= links
; link
; link
= next_link
)
12416 next_link
= XEXP (link
, 1);
12418 /* If the insn that this link points to is a NOTE or isn't a single
12419 set, ignore it. In the latter case, it isn't clear what we
12420 can do other than ignore the link, since we can't tell which
12421 register it was for. Such links wouldn't be used by combine
12424 It is not possible for the destination of the target of the link to
12425 have been changed by combine. The only potential of this is if we
12426 replace I3, I2, and I1 by I3 and I2. But in that case the
12427 destination of I2 also remains unchanged. */
12429 if (NOTE_P (XEXP (link
, 0))
12430 || (set
= single_set (XEXP (link
, 0))) == 0)
12433 reg
= SET_DEST (set
);
12434 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12435 || GET_CODE (reg
) == STRICT_LOW_PART
)
12436 reg
= XEXP (reg
, 0);
12438 /* A LOG_LINK is defined as being placed on the first insn that uses
12439 a register and points to the insn that sets the register. Start
12440 searching at the next insn after the target of the link and stop
12441 when we reach a set of the register or the end of the basic block.
12443 Note that this correctly handles the link that used to point from
12444 I3 to I2. Also note that not much searching is typically done here
12445 since most links don't point very far away. */
12447 for (insn
= NEXT_INSN (XEXP (link
, 0));
12448 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12449 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
12450 insn
= NEXT_INSN (insn
))
12451 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12453 if (reg_referenced_p (reg
, PATTERN (insn
)))
12457 else if (CALL_P (insn
)
12458 && find_reg_fusage (insn
, USE
, reg
))
12463 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
12466 /* If we found a place to put the link, place it there unless there
12467 is already a link to the same insn as LINK at that point. */
12473 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12474 if (XEXP (link2
, 0) == XEXP (link
, 0))
12479 XEXP (link
, 1) = LOG_LINKS (place
);
12480 LOG_LINKS (place
) = link
;
12482 /* Set added_links_insn to the earliest insn we added a
12484 if (added_links_insn
== 0
12485 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12486 added_links_insn
= place
;
12492 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12493 Check whether the expression pointer to by LOC is a register or
12494 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12495 Otherwise return zero. */
12498 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
12503 && (REG_P (x
) || MEM_P (x
))
12504 && ! reg_mentioned_p (x
, (rtx
) expr
))
12509 /* Check for any register or memory mentioned in EQUIV that is not
12510 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12511 of EXPR where some registers may have been replaced by constants. */
12514 unmentioned_reg_p (rtx equiv
, rtx expr
)
12516 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
12519 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12522 insn_cuid (rtx insn
)
12524 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12525 && NONJUMP_INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
)
12526 insn
= NEXT_INSN (insn
);
12528 gcc_assert (INSN_UID (insn
) <= max_uid_cuid
);
12530 return INSN_CUID (insn
);
12534 dump_combine_stats (FILE *file
)
12538 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12539 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12543 dump_combine_total_stats (FILE *file
)
12547 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12548 total_attempts
, total_merges
, total_extras
, total_successes
);