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PR c++/14032
[official-gcc.git] / gcc / longlong.h
blobedb9bfd5f3550b4ca56ef0522df350c1d9511cd0
1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2 Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2004,
3 2005, 2007 Free Software Foundation, Inc.
4
5 This definition file is free software; you can redistribute it
6 and/or modify it under the terms of the GNU General Public
7 License as published by the Free Software Foundation; either
8 version 3, or (at your option) any later version.
9
10 This definition file is distributed in the hope that it will be
11 useful, but WITHOUT ANY WARRANTY; without even the implied
12 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 See the GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; see the file COPYING3. If not see
17 <http://www.gnu.org/licenses/>. */
18
19 /* You have to define the following before including this file:
20
21 UWtype -- An unsigned type, default type for operations (typically a "word")
22 UHWtype -- An unsigned type, at least half the size of UWtype.
23 UDWtype -- An unsigned type, at least twice as large a UWtype
24 W_TYPE_SIZE -- size in bits of UWtype
25
26 UQItype -- Unsigned 8 bit type.
27 SItype, USItype -- Signed and unsigned 32 bit types.
28 DItype, UDItype -- Signed and unsigned 64 bit types.
29
30 On a 32 bit machine UWtype should typically be USItype;
31 on a 64 bit machine, UWtype should typically be UDItype. */
32
33 #define __BITS4 (W_TYPE_SIZE / 4)
34 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
35 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
36 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
37
38 #ifndef W_TYPE_SIZE
39 #define W_TYPE_SIZE 32
40 #define UWtype USItype
41 #define UHWtype USItype
42 #define UDWtype UDItype
43 #endif
44
45 extern const UQItype __clz_tab[256];
46
47 /* Define auxiliary asm macros.
48
49 1) umul_ppmm(high_prod, low_prod, multiplier, multiplicand) multiplies two
50 UWtype integers MULTIPLIER and MULTIPLICAND, and generates a two UWtype
51 word product in HIGH_PROD and LOW_PROD.
52
53 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
54 UDWtype product. This is just a variant of umul_ppmm.
55
56 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
57 denominator) divides a UDWtype, composed by the UWtype integers
58 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
59 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
60 than DENOMINATOR for correct operation. If, in addition, the most
61 significant bit of DENOMINATOR must be 1, then the pre-processor symbol
62 UDIV_NEEDS_NORMALIZATION is defined to 1.
63
64 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
65 denominator). Like udiv_qrnnd but the numbers are signed. The quotient
66 is rounded towards 0.
67
68 5) count_leading_zeros(count, x) counts the number of zero-bits from the
69 msb to the first nonzero bit in the UWtype X. This is the number of
70 steps X needs to be shifted left to set the msb. Undefined for X == 0,
71 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
72
73 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
74 from the least significant end.
75
76 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
77 high_addend_2, low_addend_2) adds two UWtype integers, composed by
78 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
79 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
80 (i.e. carry out) is not stored anywhere, and is lost.
81
82 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
83 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
84 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
85 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
86 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
87 and is lost.
88
89 If any of these macros are left undefined for a particular CPU,
90 C macros are used. */
91
92 /* The CPUs come in alphabetical order below.
93
94 Please add support for more CPUs here, or improve the current support
95 for the CPUs below!
96 (E.g. WE32100, IBM360.) */
97
98 #if defined (__GNUC__) && !defined (NO_ASM)
99
100 /* We sometimes need to clobber "cc" with gcc2, but that would not be
101 understood by gcc1. Use cpp to avoid major code duplication. */
102 #if __GNUC__ < 2
103 #define __CLOBBER_CC
104 #define __AND_CLOBBER_CC
105 #else /* __GNUC__ >= 2 */
106 #define __CLOBBER_CC : "cc"
107 #define __AND_CLOBBER_CC , "cc"
108 #endif /* __GNUC__ < 2 */
109
110 #if defined (__alpha) && W_TYPE_SIZE == 64
111 #define umul_ppmm(ph, pl, m0, m1) \
112 do { \
113 UDItype __m0 = (m0), __m1 = (m1); \
114 (ph) = __builtin_alpha_umulh (__m0, __m1); \
115 (pl) = __m0 * __m1; \
116 } while (0)
117 #define UMUL_TIME 46
118 #ifndef LONGLONG_STANDALONE
119 #define udiv_qrnnd(q, r, n1, n0, d) \
120 do { UDItype __r; \
121 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
122 (r) = __r; \
123 } while (0)
124 extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
125 #define UDIV_TIME 220
126 #endif /* LONGLONG_STANDALONE */
127 #ifdef __alpha_cix__
128 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X))
129 #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X))
130 #define COUNT_LEADING_ZEROS_0 64
131 #else
132 #define count_leading_zeros(COUNT,X) \
133 do { \
134 UDItype __xr = (X), __t, __a; \
135 __t = __builtin_alpha_cmpbge (0, __xr); \
136 __a = __clz_tab[__t ^ 0xff] - 1; \
137 __t = __builtin_alpha_extbl (__xr, __a); \
138 (COUNT) = 64 - (__clz_tab[__t] + __a*8); \
139 } while (0)
140 #define count_trailing_zeros(COUNT,X) \
141 do { \
142 UDItype __xr = (X), __t, __a; \
143 __t = __builtin_alpha_cmpbge (0, __xr); \
144 __t = ~__t & -~__t; \
145 __a = ((__t & 0xCC) != 0) * 2; \
146 __a += ((__t & 0xF0) != 0) * 4; \
147 __a += ((__t & 0xAA) != 0); \
148 __t = __builtin_alpha_extbl (__xr, __a); \
149 __a <<= 3; \
150 __t &= -__t; \
151 __a += ((__t & 0xCC) != 0) * 2; \
152 __a += ((__t & 0xF0) != 0) * 4; \
153 __a += ((__t & 0xAA) != 0); \
154 (COUNT) = __a; \
155 } while (0)
156 #endif /* __alpha_cix__ */
157 #endif /* __alpha */
158
159 #if defined (__arc__) && W_TYPE_SIZE == 32
160 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
161 __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
162 : "=r" ((USItype) (sh)), \
163 "=&r" ((USItype) (sl)) \
164 : "%r" ((USItype) (ah)), \
165 "rIJ" ((USItype) (bh)), \
166 "%r" ((USItype) (al)), \
167 "rIJ" ((USItype) (bl)))
168 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
169 __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
170 : "=r" ((USItype) (sh)), \
171 "=&r" ((USItype) (sl)) \
172 : "r" ((USItype) (ah)), \
173 "rIJ" ((USItype) (bh)), \
174 "r" ((USItype) (al)), \
175 "rIJ" ((USItype) (bl)))
176 /* Call libgcc routine. */
177 #define umul_ppmm(w1, w0, u, v) \
178 do { \
179 DWunion __w; \
180 __w.ll = __umulsidi3 (u, v); \
181 w1 = __w.s.high; \
182 w0 = __w.s.low; \
183 } while (0)
184 #define __umulsidi3 __umulsidi3
185 UDItype __umulsidi3 (USItype, USItype);
186 #endif
187
188 #if defined (__arm__) && !defined (__thumb__) && W_TYPE_SIZE == 32
189 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
190 __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
191 : "=r" ((USItype) (sh)), \
192 "=&r" ((USItype) (sl)) \
193 : "%r" ((USItype) (ah)), \
194 "rI" ((USItype) (bh)), \
195 "%r" ((USItype) (al)), \
196 "rI" ((USItype) (bl)) __CLOBBER_CC)
197 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
198 __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
199 : "=r" ((USItype) (sh)), \
200 "=&r" ((USItype) (sl)) \
201 : "r" ((USItype) (ah)), \
202 "rI" ((USItype) (bh)), \
203 "r" ((USItype) (al)), \
204 "rI" ((USItype) (bl)) __CLOBBER_CC)
205 #define umul_ppmm(xh, xl, a, b) \
206 {register USItype __t0, __t1, __t2; \
207 __asm__ ("%@ Inlined umul_ppmm\n" \
208 " mov %2, %5, lsr #16\n" \
209 " mov %0, %6, lsr #16\n" \
210 " bic %3, %5, %2, lsl #16\n" \
211 " bic %4, %6, %0, lsl #16\n" \
212 " mul %1, %3, %4\n" \
213 " mul %4, %2, %4\n" \
214 " mul %3, %0, %3\n" \
215 " mul %0, %2, %0\n" \
216 " adds %3, %4, %3\n" \
217 " addcs %0, %0, #65536\n" \
218 " adds %1, %1, %3, lsl #16\n" \
219 " adc %0, %0, %3, lsr #16" \
220 : "=&r" ((USItype) (xh)), \
221 "=r" ((USItype) (xl)), \
222 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
223 : "r" ((USItype) (a)), \
224 "r" ((USItype) (b)) __CLOBBER_CC );}
225 #define UMUL_TIME 20
226 #define UDIV_TIME 100
227 #endif /* __arm__ */
228
229 #if defined (__CRIS__) && __CRIS_arch_version >= 3
230 #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
231 #endif /* __CRIS__ */
232
233 #if defined (__hppa) && W_TYPE_SIZE == 32
234 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
235 __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
236 : "=r" ((USItype) (sh)), \
237 "=&r" ((USItype) (sl)) \
238 : "%rM" ((USItype) (ah)), \
239 "rM" ((USItype) (bh)), \
240 "%rM" ((USItype) (al)), \
241 "rM" ((USItype) (bl)))
242 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
243 __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
244 : "=r" ((USItype) (sh)), \
245 "=&r" ((USItype) (sl)) \
246 : "rM" ((USItype) (ah)), \
247 "rM" ((USItype) (bh)), \
248 "rM" ((USItype) (al)), \
249 "rM" ((USItype) (bl)))
250 #if defined (_PA_RISC1_1)
251 #define umul_ppmm(w1, w0, u, v) \
252 do { \
253 union \
254 { \
255 UDItype __f; \
256 struct {USItype __w1, __w0;} __w1w0; \
257 } __t; \
258 __asm__ ("xmpyu %1,%2,%0" \
259 : "=x" (__t.__f) \
260 : "x" ((USItype) (u)), \
261 "x" ((USItype) (v))); \
262 (w1) = __t.__w1w0.__w1; \
263 (w0) = __t.__w1w0.__w0; \
264 } while (0)
265 #define UMUL_TIME 8
266 #else
267 #define UMUL_TIME 30
268 #endif
269 #define UDIV_TIME 40
270 #define count_leading_zeros(count, x) \
271 do { \
272 USItype __tmp; \
273 __asm__ ( \
274 "ldi 1,%0\n" \
275 " extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
276 " extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\
277 " ldo 16(%0),%0 ; Yes. Perform add.\n" \
278 " extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
279 " extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\
280 " ldo 8(%0),%0 ; Yes. Perform add.\n" \
281 " extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
282 " extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\
283 " ldo 4(%0),%0 ; Yes. Perform add.\n" \
284 " extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
285 " extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\
286 " ldo 2(%0),%0 ; Yes. Perform add.\n" \
287 " extru %1,30,1,%1 ; Extract bit 1.\n" \
288 " sub %0,%1,%0 ; Subtract it.\n" \
289 : "=r" (count), "=r" (__tmp) : "1" (x)); \
290 } while (0)
291 #endif
292
293 #if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
294 #define smul_ppmm(xh, xl, m0, m1) \
295 do { \
296 union {DItype __ll; \
297 struct {USItype __h, __l;} __i; \
298 } __x; \
299 __asm__ ("lr %N0,%1\n\tmr %0,%2" \
300 : "=&r" (__x.__ll) \
301 : "r" (m0), "r" (m1)); \
302 (xh) = __x.__i.__h; (xl) = __x.__i.__l; \
303 } while (0)
304 #define sdiv_qrnnd(q, r, n1, n0, d) \
305 do { \
306 union {DItype __ll; \
307 struct {USItype __h, __l;} __i; \
308 } __x; \
309 __x.__i.__h = n1; __x.__i.__l = n0; \
310 __asm__ ("dr %0,%2" \
311 : "=r" (__x.__ll) \
312 : "0" (__x.__ll), "r" (d)); \
313 (q) = __x.__i.__l; (r) = __x.__i.__h; \
314 } while (0)
315 #endif
316
317 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
318 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
319 __asm__ ("addl %5,%1\n\tadcl %3,%0" \
320 : "=r" ((USItype) (sh)), \
321 "=&r" ((USItype) (sl)) \
322 : "%0" ((USItype) (ah)), \
323 "g" ((USItype) (bh)), \
324 "%1" ((USItype) (al)), \
325 "g" ((USItype) (bl)))
326 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
327 __asm__ ("subl %5,%1\n\tsbbl %3,%0" \
328 : "=r" ((USItype) (sh)), \
329 "=&r" ((USItype) (sl)) \
330 : "0" ((USItype) (ah)), \
331 "g" ((USItype) (bh)), \
332 "1" ((USItype) (al)), \
333 "g" ((USItype) (bl)))
334 #define umul_ppmm(w1, w0, u, v) \
335 __asm__ ("mull %3" \
336 : "=a" ((USItype) (w0)), \
337 "=d" ((USItype) (w1)) \
338 : "%0" ((USItype) (u)), \
339 "rm" ((USItype) (v)))
340 #define udiv_qrnnd(q, r, n1, n0, dv) \
341 __asm__ ("divl %4" \
342 : "=a" ((USItype) (q)), \
343 "=d" ((USItype) (r)) \
344 : "0" ((USItype) (n0)), \
345 "1" ((USItype) (n1)), \
346 "rm" ((USItype) (dv)))
347 #define count_leading_zeros(count, x) ((count) = __builtin_clz (x))
348 #define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x))
349 #define UMUL_TIME 40
350 #define UDIV_TIME 40
351 #endif /* 80x86 */
352
353 #if (defined (__x86_64__) || defined (__i386__)) && W_TYPE_SIZE == 64
354 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
355 __asm__ ("addq %5,%1\n\tadcq %3,%0" \
356 : "=r" ((UDItype) (sh)), \
357 "=&r" ((UDItype) (sl)) \
358 : "%0" ((UDItype) (ah)), \
359 "rme" ((UDItype) (bh)), \
360 "%1" ((UDItype) (al)), \
361 "rme" ((UDItype) (bl)))
362 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
363 __asm__ ("subq %5,%1\n\tsbbq %3,%0" \
364 : "=r" ((UDItype) (sh)), \
365 "=&r" ((UDItype) (sl)) \
366 : "0" ((UDItype) (ah)), \
367 "rme" ((UDItype) (bh)), \
368 "1" ((UDItype) (al)), \
369 "rme" ((UDItype) (bl)))
370 #define umul_ppmm(w1, w0, u, v) \
371 __asm__ ("mulq %3" \
372 : "=a" ((UDItype) (w0)), \
373 "=d" ((UDItype) (w1)) \
374 : "%0" ((UDItype) (u)), \
375 "rm" ((UDItype) (v)))
376 #define udiv_qrnnd(q, r, n1, n0, dv) \
377 __asm__ ("divq %4" \
378 : "=a" ((UDItype) (q)), \
379 "=d" ((UDItype) (r)) \
380 : "0" ((UDItype) (n0)), \
381 "1" ((UDItype) (n1)), \
382 "rm" ((UDItype) (dv)))
383 #define count_leading_zeros(count, x) ((count) = __builtin_clzl (x))
384 #define count_trailing_zeros(count, x) ((count) = __builtin_ctzl (x))
385 #define UMUL_TIME 40
386 #define UDIV_TIME 40
387 #endif /* x86_64 */
388
389 #if defined (__i960__) && W_TYPE_SIZE == 32
390 #define umul_ppmm(w1, w0, u, v) \
391 ({union {UDItype __ll; \
392 struct {USItype __l, __h;} __i; \
393 } __xx; \
394 __asm__ ("emul %2,%1,%0" \
395 : "=d" (__xx.__ll) \
396 : "%dI" ((USItype) (u)), \
397 "dI" ((USItype) (v))); \
398 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
399 #define __umulsidi3(u, v) \
400 ({UDItype __w; \
401 __asm__ ("emul %2,%1,%0" \
402 : "=d" (__w) \
403 : "%dI" ((USItype) (u)), \
404 "dI" ((USItype) (v))); \
405 __w; })
406 #endif /* __i960__ */
407
408 #if defined (__M32R__) && W_TYPE_SIZE == 32
409 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
410 /* The cmp clears the condition bit. */ \
411 __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \
412 : "=r" ((USItype) (sh)), \
413 "=&r" ((USItype) (sl)) \
414 : "0" ((USItype) (ah)), \
415 "r" ((USItype) (bh)), \
416 "1" ((USItype) (al)), \
417 "r" ((USItype) (bl)) \
418 : "cbit")
419 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
420 /* The cmp clears the condition bit. */ \
421 __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \
422 : "=r" ((USItype) (sh)), \
423 "=&r" ((USItype) (sl)) \
424 : "0" ((USItype) (ah)), \
425 "r" ((USItype) (bh)), \
426 "1" ((USItype) (al)), \
427 "r" ((USItype) (bl)) \
428 : "cbit")
429 #endif /* __M32R__ */
430
431 #if defined (__mc68000__) && W_TYPE_SIZE == 32
432 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
433 __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
434 : "=d" ((USItype) (sh)), \
435 "=&d" ((USItype) (sl)) \
436 : "%0" ((USItype) (ah)), \
437 "d" ((USItype) (bh)), \
438 "%1" ((USItype) (al)), \
439 "g" ((USItype) (bl)))
440 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
441 __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
442 : "=d" ((USItype) (sh)), \
443 "=&d" ((USItype) (sl)) \
444 : "0" ((USItype) (ah)), \
445 "d" ((USItype) (bh)), \
446 "1" ((USItype) (al)), \
447 "g" ((USItype) (bl)))
448
449 /* The '020, '030, '040, '060 and CPU32 have 32x32->64 and 64/32->32q-32r. */
450 #if (defined (__mc68020__) && !defined (__mc68060__))
451 #define umul_ppmm(w1, w0, u, v) \
452 __asm__ ("mulu%.l %3,%1:%0" \
453 : "=d" ((USItype) (w0)), \
454 "=d" ((USItype) (w1)) \
455 : "%0" ((USItype) (u)), \
456 "dmi" ((USItype) (v)))
457 #define UMUL_TIME 45
458 #define udiv_qrnnd(q, r, n1, n0, d) \
459 __asm__ ("divu%.l %4,%1:%0" \
460 : "=d" ((USItype) (q)), \
461 "=d" ((USItype) (r)) \
462 : "0" ((USItype) (n0)), \
463 "1" ((USItype) (n1)), \
464 "dmi" ((USItype) (d)))
465 #define UDIV_TIME 90
466 #define sdiv_qrnnd(q, r, n1, n0, d) \
467 __asm__ ("divs%.l %4,%1:%0" \
468 : "=d" ((USItype) (q)), \
469 "=d" ((USItype) (r)) \
470 : "0" ((USItype) (n0)), \
471 "1" ((USItype) (n1)), \
472 "dmi" ((USItype) (d)))
473
474 #elif defined (__mcoldfire__) /* not mc68020 */
475
476 #define umul_ppmm(xh, xl, a, b) \
477 __asm__ ("| Inlined umul_ppmm\n" \
478 " move%.l %2,%/d0\n" \
479 " move%.l %3,%/d1\n" \
480 " move%.l %/d0,%/d2\n" \
481 " swap %/d0\n" \
482 " move%.l %/d1,%/d3\n" \
483 " swap %/d1\n" \
484 " move%.w %/d2,%/d4\n" \
485 " mulu %/d3,%/d4\n" \
486 " mulu %/d1,%/d2\n" \
487 " mulu %/d0,%/d3\n" \
488 " mulu %/d0,%/d1\n" \
489 " move%.l %/d4,%/d0\n" \
490 " clr%.w %/d0\n" \
491 " swap %/d0\n" \
492 " add%.l %/d0,%/d2\n" \
493 " add%.l %/d3,%/d2\n" \
494 " jcc 1f\n" \
495 " add%.l %#65536,%/d1\n" \
496 "1: swap %/d2\n" \
497 " moveq %#0,%/d0\n" \
498 " move%.w %/d2,%/d0\n" \
499 " move%.w %/d4,%/d2\n" \
500 " move%.l %/d2,%1\n" \
501 " add%.l %/d1,%/d0\n" \
502 " move%.l %/d0,%0" \
503 : "=g" ((USItype) (xh)), \
504 "=g" ((USItype) (xl)) \
505 : "g" ((USItype) (a)), \
506 "g" ((USItype) (b)) \
507 : "d0", "d1", "d2", "d3", "d4")
508 #define UMUL_TIME 100
509 #define UDIV_TIME 400
510 #else /* not ColdFire */
511 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
512 #define umul_ppmm(xh, xl, a, b) \
513 __asm__ ("| Inlined umul_ppmm\n" \
514 " move%.l %2,%/d0\n" \
515 " move%.l %3,%/d1\n" \
516 " move%.l %/d0,%/d2\n" \
517 " swap %/d0\n" \
518 " move%.l %/d1,%/d3\n" \
519 " swap %/d1\n" \
520 " move%.w %/d2,%/d4\n" \
521 " mulu %/d3,%/d4\n" \
522 " mulu %/d1,%/d2\n" \
523 " mulu %/d0,%/d3\n" \
524 " mulu %/d0,%/d1\n" \
525 " move%.l %/d4,%/d0\n" \
526 " eor%.w %/d0,%/d0\n" \
527 " swap %/d0\n" \
528 " add%.l %/d0,%/d2\n" \
529 " add%.l %/d3,%/d2\n" \
530 " jcc 1f\n" \
531 " add%.l %#65536,%/d1\n" \
532 "1: swap %/d2\n" \
533 " moveq %#0,%/d0\n" \
534 " move%.w %/d2,%/d0\n" \
535 " move%.w %/d4,%/d2\n" \
536 " move%.l %/d2,%1\n" \
537 " add%.l %/d1,%/d0\n" \
538 " move%.l %/d0,%0" \
539 : "=g" ((USItype) (xh)), \
540 "=g" ((USItype) (xl)) \
541 : "g" ((USItype) (a)), \
542 "g" ((USItype) (b)) \
543 : "d0", "d1", "d2", "d3", "d4")
544 #define UMUL_TIME 100
545 #define UDIV_TIME 400
546
547 #endif /* not mc68020 */
548
549 /* The '020, '030, '040 and '060 have bitfield insns.
550 cpu32 disguises as a 68020, but lacks them. */
551 #if defined (__mc68020__) && !defined (__mcpu32__)
552 #define count_leading_zeros(count, x) \
553 __asm__ ("bfffo %1{%b2:%b2},%0" \
554 : "=d" ((USItype) (count)) \
555 : "od" ((USItype) (x)), "n" (0))
556 /* Some ColdFire architectures have a ff1 instruction supported via
557 __builtin_clz. */
558 #elif defined (__mcfisaaplus__) || defined (__mcfisac__)
559 #define count_leading_zeros(count,x) ((count) = __builtin_clz (x))
560 #define COUNT_LEADING_ZEROS_0 32
561 #endif
562 #endif /* mc68000 */
563
564 #if defined (__m88000__) && W_TYPE_SIZE == 32
565 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
566 __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
567 : "=r" ((USItype) (sh)), \
568 "=&r" ((USItype) (sl)) \
569 : "%rJ" ((USItype) (ah)), \
570 "rJ" ((USItype) (bh)), \
571 "%rJ" ((USItype) (al)), \
572 "rJ" ((USItype) (bl)))
573 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
574 __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
575 : "=r" ((USItype) (sh)), \
576 "=&r" ((USItype) (sl)) \
577 : "rJ" ((USItype) (ah)), \
578 "rJ" ((USItype) (bh)), \
579 "rJ" ((USItype) (al)), \
580 "rJ" ((USItype) (bl)))
581 #define count_leading_zeros(count, x) \
582 do { \
583 USItype __cbtmp; \
584 __asm__ ("ff1 %0,%1" \
585 : "=r" (__cbtmp) \
586 : "r" ((USItype) (x))); \
587 (count) = __cbtmp ^ 31; \
588 } while (0)
589 #define COUNT_LEADING_ZEROS_0 63 /* sic */
590 #if defined (__mc88110__)
591 #define umul_ppmm(wh, wl, u, v) \
592 do { \
593 union {UDItype __ll; \
594 struct {USItype __h, __l;} __i; \
595 } __xx; \
596 __asm__ ("mulu.d %0,%1,%2" \
597 : "=r" (__xx.__ll) \
598 : "r" ((USItype) (u)), \
599 "r" ((USItype) (v))); \
600 (wh) = __xx.__i.__h; \
601 (wl) = __xx.__i.__l; \
602 } while (0)
603 #define udiv_qrnnd(q, r, n1, n0, d) \
604 ({union {UDItype __ll; \
605 struct {USItype __h, __l;} __i; \
606 } __xx; \
607 USItype __q; \
608 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
609 __asm__ ("divu.d %0,%1,%2" \
610 : "=r" (__q) \
611 : "r" (__xx.__ll), \
612 "r" ((USItype) (d))); \
613 (r) = (n0) - __q * (d); (q) = __q; })
614 #define UMUL_TIME 5
615 #define UDIV_TIME 25
616 #else
617 #define UMUL_TIME 17
618 #define UDIV_TIME 150
619 #endif /* __mc88110__ */
620 #endif /* __m88000__ */
621
622 #if defined (__mips__) && W_TYPE_SIZE == 32
623 #define umul_ppmm(w1, w0, u, v) \
624 __asm__ ("multu %2,%3" \
625 : "=l" ((USItype) (w0)), \
626 "=h" ((USItype) (w1)) \
627 : "d" ((USItype) (u)), \
628 "d" ((USItype) (v)))
629 #define UMUL_TIME 10
630 #define UDIV_TIME 100
631
632 #if (__mips == 32 || __mips == 64) && ! __mips16
633 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
634 #define COUNT_LEADING_ZEROS_0 32
635 #endif
636 #endif /* __mips__ */
637
638 #if defined (__ns32000__) && W_TYPE_SIZE == 32
639 #define umul_ppmm(w1, w0, u, v) \
640 ({union {UDItype __ll; \
641 struct {USItype __l, __h;} __i; \
642 } __xx; \
643 __asm__ ("meid %2,%0" \
644 : "=g" (__xx.__ll) \
645 : "%0" ((USItype) (u)), \
646 "g" ((USItype) (v))); \
647 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
648 #define __umulsidi3(u, v) \
649 ({UDItype __w; \
650 __asm__ ("meid %2,%0" \
651 : "=g" (__w) \
652 : "%0" ((USItype) (u)), \
653 "g" ((USItype) (v))); \
654 __w; })
655 #define udiv_qrnnd(q, r, n1, n0, d) \
656 ({union {UDItype __ll; \
657 struct {USItype __l, __h;} __i; \
658 } __xx; \
659 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
660 __asm__ ("deid %2,%0" \
661 : "=g" (__xx.__ll) \
662 : "0" (__xx.__ll), \
663 "g" ((USItype) (d))); \
664 (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
665 #define count_trailing_zeros(count,x) \
666 do { \
667 __asm__ ("ffsd %2,%0" \
668 : "=r" ((USItype) (count)) \
669 : "0" ((USItype) 0), \
670 "r" ((USItype) (x))); \
671 } while (0)
672 #endif /* __ns32000__ */
673
674 /* FIXME: We should test _IBMR2 here when we add assembly support for the
675 system vendor compilers.
676 FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good
677 enough, since that hits ARM and m68k too. */
678 #if (defined (_ARCH_PPC) /* AIX */ \
679 || defined (_ARCH_PWR) /* AIX */ \
680 || defined (_ARCH_COM) /* AIX */ \
681 || defined (__powerpc__) /* gcc */ \
682 || defined (__POWERPC__) /* BEOS */ \
683 || defined (__ppc__) /* Darwin */ \
684 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
685 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
686 && CPU_FAMILY == PPC) \
687 ) && W_TYPE_SIZE == 32
688 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
689 do { \
690 if (__builtin_constant_p (bh) && (bh) == 0) \
691 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
692 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
693 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
694 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
695 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
696 else \
697 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
698 : "=r" (sh), "=&r" (sl) \
699 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
700 } while (0)
701 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
702 do { \
703 if (__builtin_constant_p (ah) && (ah) == 0) \
704 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
705 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
706 else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
707 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
708 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
709 else if (__builtin_constant_p (bh) && (bh) == 0) \
710 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
711 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
712 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
713 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
714 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
715 else \
716 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
717 : "=r" (sh), "=&r" (sl) \
718 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
719 } while (0)
720 #define count_leading_zeros(count, x) \
721 __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
722 #define COUNT_LEADING_ZEROS_0 32
723 #if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
724 || defined (__ppc__) \
725 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
726 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
727 && CPU_FAMILY == PPC)
728 #define umul_ppmm(ph, pl, m0, m1) \
729 do { \
730 USItype __m0 = (m0), __m1 = (m1); \
731 __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
732 (pl) = __m0 * __m1; \
733 } while (0)
734 #define UMUL_TIME 15
735 #define smul_ppmm(ph, pl, m0, m1) \
736 do { \
737 SItype __m0 = (m0), __m1 = (m1); \
738 __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
739 (pl) = __m0 * __m1; \
740 } while (0)
741 #define SMUL_TIME 14
742 #define UDIV_TIME 120
743 #elif defined (_ARCH_PWR)
744 #define UMUL_TIME 8
745 #define smul_ppmm(xh, xl, m0, m1) \
746 __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
747 #define SMUL_TIME 4
748 #define sdiv_qrnnd(q, r, nh, nl, d) \
749 __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
750 #define UDIV_TIME 100
751 #endif
752 #endif /* 32-bit POWER architecture variants. */
753
754 /* We should test _IBMR2 here when we add assembly support for the system
755 vendor compilers. */
756 #if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
757 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
758 do { \
759 if (__builtin_constant_p (bh) && (bh) == 0) \
760 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
761 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
762 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
763 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
764 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
765 else \
766 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
767 : "=r" (sh), "=&r" (sl) \
768 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
769 } while (0)
770 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
771 do { \
772 if (__builtin_constant_p (ah) && (ah) == 0) \
773 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
774 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
775 else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
776 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
777 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
778 else if (__builtin_constant_p (bh) && (bh) == 0) \
779 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
780 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
781 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
782 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
783 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
784 else \
785 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
786 : "=r" (sh), "=&r" (sl) \
787 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
788 } while (0)
789 #define count_leading_zeros(count, x) \
790 __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
791 #define COUNT_LEADING_ZEROS_0 64
792 #define umul_ppmm(ph, pl, m0, m1) \
793 do { \
794 UDItype __m0 = (m0), __m1 = (m1); \
795 __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
796 (pl) = __m0 * __m1; \
797 } while (0)
798 #define UMUL_TIME 15
799 #define smul_ppmm(ph, pl, m0, m1) \
800 do { \
801 DItype __m0 = (m0), __m1 = (m1); \
802 __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
803 (pl) = __m0 * __m1; \
804 } while (0)
805 #define SMUL_TIME 14 /* ??? */
806 #define UDIV_TIME 120 /* ??? */
807 #endif /* 64-bit PowerPC. */
808
809 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
810 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
811 __asm__ ("a %1,%5\n\tae %0,%3" \
812 : "=r" ((USItype) (sh)), \
813 "=&r" ((USItype) (sl)) \
814 : "%0" ((USItype) (ah)), \
815 "r" ((USItype) (bh)), \
816 "%1" ((USItype) (al)), \
817 "r" ((USItype) (bl)))
818 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
819 __asm__ ("s %1,%5\n\tse %0,%3" \
820 : "=r" ((USItype) (sh)), \
821 "=&r" ((USItype) (sl)) \
822 : "0" ((USItype) (ah)), \
823 "r" ((USItype) (bh)), \
824 "1" ((USItype) (al)), \
825 "r" ((USItype) (bl)))
826 #define umul_ppmm(ph, pl, m0, m1) \
827 do { \
828 USItype __m0 = (m0), __m1 = (m1); \
829 __asm__ ( \
830 "s r2,r2\n" \
831 " mts r10,%2\n" \
832 " m r2,%3\n" \
833 " m r2,%3\n" \
834 " m r2,%3\n" \
835 " m r2,%3\n" \
836 " m r2,%3\n" \
837 " m r2,%3\n" \
838 " m r2,%3\n" \
839 " m r2,%3\n" \
840 " m r2,%3\n" \
841 " m r2,%3\n" \
842 " m r2,%3\n" \
843 " m r2,%3\n" \
844 " m r2,%3\n" \
845 " m r2,%3\n" \
846 " m r2,%3\n" \
847 " m r2,%3\n" \
848 " cas %0,r2,r0\n" \
849 " mfs r10,%1" \
850 : "=r" ((USItype) (ph)), \
851 "=r" ((USItype) (pl)) \
852 : "%r" (__m0), \
853 "r" (__m1) \
854 : "r2"); \
855 (ph) += ((((SItype) __m0 >> 31) & __m1) \
856 + (((SItype) __m1 >> 31) & __m0)); \
857 } while (0)
858 #define UMUL_TIME 20
859 #define UDIV_TIME 200
860 #define count_leading_zeros(count, x) \
861 do { \
862 if ((x) >= 0x10000) \
863 __asm__ ("clz %0,%1" \
864 : "=r" ((USItype) (count)) \
865 : "r" ((USItype) (x) >> 16)); \
866 else \
867 { \
868 __asm__ ("clz %0,%1" \
869 : "=r" ((USItype) (count)) \
870 : "r" ((USItype) (x))); \
871 (count) += 16; \
872 } \
873 } while (0)
874 #endif
875
876 #if defined(__sh__) && !__SHMEDIA__ && W_TYPE_SIZE == 32
877 #ifndef __sh1__
878 #define umul_ppmm(w1, w0, u, v) \
879 __asm__ ( \
880 "dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \
881 : "=r<" ((USItype)(w1)), \
882 "=r<" ((USItype)(w0)) \
883 : "r" ((USItype)(u)), \
884 "r" ((USItype)(v)) \
885 : "macl", "mach")
886 #define UMUL_TIME 5
887 #endif
888
889 /* This is the same algorithm as __udiv_qrnnd_c. */
890 #define UDIV_NEEDS_NORMALIZATION 1
891
892 #define udiv_qrnnd(q, r, n1, n0, d) \
893 do { \
894 extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
895 __attribute__ ((visibility ("hidden"))); \
896 /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \
897 __asm__ ( \
898 "mov%M4 %4,r5\n" \
899 " swap.w %3,r4\n" \
900 " swap.w r5,r6\n" \
901 " jsr @%5\n" \
902 " shll16 r6\n" \
903 " swap.w r4,r4\n" \
904 " jsr @%5\n" \
905 " swap.w r1,%0\n" \
906 " or r1,%0" \
907 : "=r" (q), "=&z" (r) \
908 : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
909 : "r1", "r2", "r4", "r5", "r6", "pr"); \
910 } while (0)
911
912 #define UDIV_TIME 80
913
914 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
915 __asm__ ("clrt;subc %5,%1; subc %4,%0" \
916 : "=r" (sh), "=r" (sl) \
917 : "0" (ah), "1" (al), "r" (bh), "r" (bl))
918
919 #endif /* __sh__ */
920
921 #if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
922 #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
923 #define count_leading_zeros(count, x) \
924 do \
925 { \
926 UDItype x_ = (USItype)(x); \
927 SItype c_; \
928 \
929 __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
930 (count) = c_ - 31; \
931 } \
932 while (0)
933 #define COUNT_LEADING_ZEROS_0 32
934 #endif
935
936 #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
937 && W_TYPE_SIZE == 32
938 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
939 __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
940 : "=r" ((USItype) (sh)), \
941 "=&r" ((USItype) (sl)) \
942 : "%rJ" ((USItype) (ah)), \
943 "rI" ((USItype) (bh)), \
944 "%rJ" ((USItype) (al)), \
945 "rI" ((USItype) (bl)) \
946 __CLOBBER_CC)
947 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
948 __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
949 : "=r" ((USItype) (sh)), \
950 "=&r" ((USItype) (sl)) \
951 : "rJ" ((USItype) (ah)), \
952 "rI" ((USItype) (bh)), \
953 "rJ" ((USItype) (al)), \
954 "rI" ((USItype) (bl)) \
955 __CLOBBER_CC)
956 #if defined (__sparc_v8__)
957 #define umul_ppmm(w1, w0, u, v) \
958 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
959 : "=r" ((USItype) (w1)), \
960 "=r" ((USItype) (w0)) \
961 : "r" ((USItype) (u)), \
962 "r" ((USItype) (v)))
963 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
964 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
965 : "=&r" ((USItype) (__q)), \
966 "=&r" ((USItype) (__r)) \
967 : "r" ((USItype) (__n1)), \
968 "r" ((USItype) (__n0)), \
969 "r" ((USItype) (__d)))
970 #else
971 #if defined (__sparclite__)
972 /* This has hardware multiply but not divide. It also has two additional
973 instructions scan (ffs from high bit) and divscc. */
974 #define umul_ppmm(w1, w0, u, v) \
975 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
976 : "=r" ((USItype) (w1)), \
977 "=r" ((USItype) (w0)) \
978 : "r" ((USItype) (u)), \
979 "r" ((USItype) (v)))
980 #define udiv_qrnnd(q, r, n1, n0, d) \
981 __asm__ ("! Inlined udiv_qrnnd\n" \
982 " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
983 " tst %%g0\n" \
984 " divscc %3,%4,%%g1\n" \
985 " divscc %%g1,%4,%%g1\n" \
986 " divscc %%g1,%4,%%g1\n" \
987 " divscc %%g1,%4,%%g1\n" \
988 " divscc %%g1,%4,%%g1\n" \
989 " divscc %%g1,%4,%%g1\n" \
990 " divscc %%g1,%4,%%g1\n" \
991 " divscc %%g1,%4,%%g1\n" \
992 " divscc %%g1,%4,%%g1\n" \
993 " divscc %%g1,%4,%%g1\n" \
994 " divscc %%g1,%4,%%g1\n" \
995 " divscc %%g1,%4,%%g1\n" \
996 " divscc %%g1,%4,%%g1\n" \
997 " divscc %%g1,%4,%%g1\n" \
998 " divscc %%g1,%4,%%g1\n" \
999 " divscc %%g1,%4,%%g1\n" \
1000 " divscc %%g1,%4,%%g1\n" \
1001 " divscc %%g1,%4,%%g1\n" \
1002 " divscc %%g1,%4,%%g1\n" \
1003 " divscc %%g1,%4,%%g1\n" \
1004 " divscc %%g1,%4,%%g1\n" \
1005 " divscc %%g1,%4,%%g1\n" \
1006 " divscc %%g1,%4,%%g1\n" \
1007 " divscc %%g1,%4,%%g1\n" \
1008 " divscc %%g1,%4,%%g1\n" \
1009 " divscc %%g1,%4,%%g1\n" \
1010 " divscc %%g1,%4,%%g1\n" \
1011 " divscc %%g1,%4,%%g1\n" \
1012 " divscc %%g1,%4,%%g1\n" \
1013 " divscc %%g1,%4,%%g1\n" \
1014 " divscc %%g1,%4,%%g1\n" \
1015 " divscc %%g1,%4,%0\n" \
1016 " rd %%y,%1\n" \
1017 " bl,a 1f\n" \
1018 " add %1,%4,%1\n" \
1019 "1: ! End of inline udiv_qrnnd" \
1020 : "=r" ((USItype) (q)), \
1021 "=r" ((USItype) (r)) \
1022 : "r" ((USItype) (n1)), \
1023 "r" ((USItype) (n0)), \
1024 "rI" ((USItype) (d)) \
1025 : "g1" __AND_CLOBBER_CC)
1026 #define UDIV_TIME 37
1027 #define count_leading_zeros(count, x) \
1028 do { \
1029 __asm__ ("scan %1,1,%0" \
1030 : "=r" ((USItype) (count)) \
1031 : "r" ((USItype) (x))); \
1032 } while (0)
1033 /* Early sparclites return 63 for an argument of 0, but they warn that future
1034 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
1035 undefined. */
1036 #else
1037 /* SPARC without integer multiplication and divide instructions.
1038 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
1039 #define umul_ppmm(w1, w0, u, v) \
1040 __asm__ ("! Inlined umul_ppmm\n" \
1041 " wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
1042 " sra %3,31,%%o5 ! Don't move this insn\n" \
1043 " and %2,%%o5,%%o5 ! Don't move this insn\n" \
1044 " andcc %%g0,0,%%g1 ! Don't move this insn\n" \
1045 " mulscc %%g1,%3,%%g1\n" \
1046 " mulscc %%g1,%3,%%g1\n" \
1047 " mulscc %%g1,%3,%%g1\n" \
1048 " mulscc %%g1,%3,%%g1\n" \
1049 " mulscc %%g1,%3,%%g1\n" \
1050 " mulscc %%g1,%3,%%g1\n" \
1051 " mulscc %%g1,%3,%%g1\n" \
1052 " mulscc %%g1,%3,%%g1\n" \
1053 " mulscc %%g1,%3,%%g1\n" \
1054 " mulscc %%g1,%3,%%g1\n" \
1055 " mulscc %%g1,%3,%%g1\n" \
1056 " mulscc %%g1,%3,%%g1\n" \
1057 " mulscc %%g1,%3,%%g1\n" \
1058 " mulscc %%g1,%3,%%g1\n" \
1059 " mulscc %%g1,%3,%%g1\n" \
1060 " mulscc %%g1,%3,%%g1\n" \
1061 " mulscc %%g1,%3,%%g1\n" \
1062 " mulscc %%g1,%3,%%g1\n" \
1063 " mulscc %%g1,%3,%%g1\n" \
1064 " mulscc %%g1,%3,%%g1\n" \
1065 " mulscc %%g1,%3,%%g1\n" \
1066 " mulscc %%g1,%3,%%g1\n" \
1067 " mulscc %%g1,%3,%%g1\n" \
1068 " mulscc %%g1,%3,%%g1\n" \
1069 " mulscc %%g1,%3,%%g1\n" \
1070 " mulscc %%g1,%3,%%g1\n" \
1071 " mulscc %%g1,%3,%%g1\n" \
1072 " mulscc %%g1,%3,%%g1\n" \
1073 " mulscc %%g1,%3,%%g1\n" \
1074 " mulscc %%g1,%3,%%g1\n" \
1075 " mulscc %%g1,%3,%%g1\n" \
1076 " mulscc %%g1,%3,%%g1\n" \
1077 " mulscc %%g1,0,%%g1\n" \
1078 " add %%g1,%%o5,%0\n" \
1079 " rd %%y,%1" \
1080 : "=r" ((USItype) (w1)), \
1081 "=r" ((USItype) (w0)) \
1082 : "%rI" ((USItype) (u)), \
1083 "r" ((USItype) (v)) \
1084 : "g1", "o5" __AND_CLOBBER_CC)
1085 #define UMUL_TIME 39 /* 39 instructions */
1086 /* It's quite necessary to add this much assembler for the sparc.
1087 The default udiv_qrnnd (in C) is more than 10 times slower! */
1088 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
1089 __asm__ ("! Inlined udiv_qrnnd\n" \
1090 " mov 32,%%g1\n" \
1091 " subcc %1,%2,%%g0\n" \
1092 "1: bcs 5f\n" \
1093 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1094 " sub %1,%2,%1 ! this kills msb of n\n" \
1095 " addx %1,%1,%1 ! so this can't give carry\n" \
1096 " subcc %%g1,1,%%g1\n" \
1097 "2: bne 1b\n" \
1098 " subcc %1,%2,%%g0\n" \
1099 " bcs 3f\n" \
1100 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1101 " b 3f\n" \
1102 " sub %1,%2,%1 ! this kills msb of n\n" \
1103 "4: sub %1,%2,%1\n" \
1104 "5: addxcc %1,%1,%1\n" \
1105 " bcc 2b\n" \
1106 " subcc %%g1,1,%%g1\n" \
1107 "! Got carry from n. Subtract next step to cancel this carry.\n" \
1108 " bne 4b\n" \
1109 " addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
1110 " sub %1,%2,%1\n" \
1111 "3: xnor %0,0,%0\n" \
1112 " ! End of inline udiv_qrnnd" \
1113 : "=&r" ((USItype) (__q)), \
1114 "=&r" ((USItype) (__r)) \
1115 : "r" ((USItype) (__d)), \
1116 "1" ((USItype) (__n1)), \
1117 "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
1118 #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
1119 #endif /* __sparclite__ */
1120 #endif /* __sparc_v8__ */
1121 #endif /* sparc32 */
1122
1123 #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
1124 && W_TYPE_SIZE == 64
1125 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1126 __asm__ ("addcc %r4,%5,%1\n\t" \
1127 "add %r2,%3,%0\n\t" \
1128 "bcs,a,pn %%xcc, 1f\n\t" \
1129 "add %0, 1, %0\n" \
1130 "1:" \
1131 : "=r" ((UDItype)(sh)), \
1132 "=&r" ((UDItype)(sl)) \
1133 : "%rJ" ((UDItype)(ah)), \
1134 "rI" ((UDItype)(bh)), \
1135 "%rJ" ((UDItype)(al)), \
1136 "rI" ((UDItype)(bl)) \
1137 __CLOBBER_CC)
1138
1139 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1140 __asm__ ("subcc %r4,%5,%1\n\t" \
1141 "sub %r2,%3,%0\n\t" \
1142 "bcs,a,pn %%xcc, 1f\n\t" \
1143 "sub %0, 1, %0\n\t" \
1144 "1:" \
1145 : "=r" ((UDItype)(sh)), \
1146 "=&r" ((UDItype)(sl)) \
1147 : "rJ" ((UDItype)(ah)), \
1148 "rI" ((UDItype)(bh)), \
1149 "rJ" ((UDItype)(al)), \
1150 "rI" ((UDItype)(bl)) \
1151 __CLOBBER_CC)
1152
1153 #define umul_ppmm(wh, wl, u, v) \
1154 do { \
1155 UDItype tmp1, tmp2, tmp3, tmp4; \
1156 __asm__ __volatile__ ( \
1157 "srl %7,0,%3\n\t" \
1158 "mulx %3,%6,%1\n\t" \
1159 "srlx %6,32,%2\n\t" \
1160 "mulx %2,%3,%4\n\t" \
1161 "sllx %4,32,%5\n\t" \
1162 "srl %6,0,%3\n\t" \
1163 "sub %1,%5,%5\n\t" \
1164 "srlx %5,32,%5\n\t" \
1165 "addcc %4,%5,%4\n\t" \
1166 "srlx %7,32,%5\n\t" \
1167 "mulx %3,%5,%3\n\t" \
1168 "mulx %2,%5,%5\n\t" \
1169 "sethi %%hi(0x80000000),%2\n\t" \
1170 "addcc %4,%3,%4\n\t" \
1171 "srlx %4,32,%4\n\t" \
1172 "add %2,%2,%2\n\t" \
1173 "movcc %%xcc,%%g0,%2\n\t" \
1174 "addcc %5,%4,%5\n\t" \
1175 "sllx %3,32,%3\n\t" \
1176 "add %1,%3,%1\n\t" \
1177 "add %5,%2,%0" \
1178 : "=r" ((UDItype)(wh)), \
1179 "=&r" ((UDItype)(wl)), \
1180 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
1181 : "r" ((UDItype)(u)), \
1182 "r" ((UDItype)(v)) \
1183 __CLOBBER_CC); \
1184 } while (0)
1185 #define UMUL_TIME 96
1186 #define UDIV_TIME 230
1187 #endif /* sparc64 */
1188
1189 #if defined (__vax__) && W_TYPE_SIZE == 32
1190 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1191 __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
1192 : "=g" ((USItype) (sh)), \
1193 "=&g" ((USItype) (sl)) \
1194 : "%0" ((USItype) (ah)), \
1195 "g" ((USItype) (bh)), \
1196 "%1" ((USItype) (al)), \
1197 "g" ((USItype) (bl)))
1198 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1199 __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
1200 : "=g" ((USItype) (sh)), \
1201 "=&g" ((USItype) (sl)) \
1202 : "0" ((USItype) (ah)), \
1203 "g" ((USItype) (bh)), \
1204 "1" ((USItype) (al)), \
1205 "g" ((USItype) (bl)))
1206 #define umul_ppmm(xh, xl, m0, m1) \
1207 do { \
1208 union { \
1209 UDItype __ll; \
1210 struct {USItype __l, __h;} __i; \
1211 } __xx; \
1212 USItype __m0 = (m0), __m1 = (m1); \
1213 __asm__ ("emul %1,%2,$0,%0" \
1214 : "=r" (__xx.__ll) \
1215 : "g" (__m0), \
1216 "g" (__m1)); \
1217 (xh) = __xx.__i.__h; \
1218 (xl) = __xx.__i.__l; \
1219 (xh) += ((((SItype) __m0 >> 31) & __m1) \
1220 + (((SItype) __m1 >> 31) & __m0)); \
1221 } while (0)
1222 #define sdiv_qrnnd(q, r, n1, n0, d) \
1223 do { \
1224 union {DItype __ll; \
1225 struct {SItype __l, __h;} __i; \
1226 } __xx; \
1227 __xx.__i.__h = n1; __xx.__i.__l = n0; \
1228 __asm__ ("ediv %3,%2,%0,%1" \
1229 : "=g" (q), "=g" (r) \
1230 : "g" (__xx.__ll), "g" (d)); \
1231 } while (0)
1232 #endif /* __vax__ */
1233
1234 #if defined (__xtensa__) && W_TYPE_SIZE == 32
1235 /* This code is not Xtensa-configuration-specific, so rely on the compiler
1236 to expand builtin functions depending on what configuration features
1237 are available. This avoids library calls when the operation can be
1238 performed in-line. */
1239 #define umul_ppmm(w1, w0, u, v) \
1240 do { \
1241 DWunion __w; \
1242 __w.ll = __builtin_umulsidi3 (u, v); \
1243 w1 = __w.s.high; \
1244 w0 = __w.s.low; \
1245 } while (0)
1246 #define __umulsidi3(u, v) __builtin_umulsidi3 (u, v)
1247 #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
1248 #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
1249 #endif /* __xtensa__ */
1250
1251 #if defined (__z8000__) && W_TYPE_SIZE == 16
1252 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1253 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
1254 : "=r" ((unsigned int)(sh)), \
1255 "=&r" ((unsigned int)(sl)) \
1256 : "%0" ((unsigned int)(ah)), \
1257 "r" ((unsigned int)(bh)), \
1258 "%1" ((unsigned int)(al)), \
1259 "rQR" ((unsigned int)(bl)))
1260 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1261 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
1262 : "=r" ((unsigned int)(sh)), \
1263 "=&r" ((unsigned int)(sl)) \
1264 : "0" ((unsigned int)(ah)), \
1265 "r" ((unsigned int)(bh)), \
1266 "1" ((unsigned int)(al)), \
1267 "rQR" ((unsigned int)(bl)))
1268 #define umul_ppmm(xh, xl, m0, m1) \
1269 do { \
1270 union {long int __ll; \
1271 struct {unsigned int __h, __l;} __i; \
1272 } __xx; \
1273 unsigned int __m0 = (m0), __m1 = (m1); \
1274 __asm__ ("mult %S0,%H3" \
1275 : "=r" (__xx.__i.__h), \
1276 "=r" (__xx.__i.__l) \
1277 : "%1" (__m0), \
1278 "rQR" (__m1)); \
1279 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1280 (xh) += ((((signed int) __m0 >> 15) & __m1) \
1281 + (((signed int) __m1 >> 15) & __m0)); \
1282 } while (0)
1283 #endif /* __z8000__ */
1284
1285 #endif /* __GNUC__ */
1286
1287 /* If this machine has no inline assembler, use C macros. */
1288
1289 #if !defined (add_ssaaaa)
1290 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1291 do { \
1292 UWtype __x; \
1293 __x = (al) + (bl); \
1294 (sh) = (ah) + (bh) + (__x < (al)); \
1295 (sl) = __x; \
1296 } while (0)
1297 #endif
1298
1299 #if !defined (sub_ddmmss)
1300 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1301 do { \
1302 UWtype __x; \
1303 __x = (al) - (bl); \
1304 (sh) = (ah) - (bh) - (__x > (al)); \
1305 (sl) = __x; \
1306 } while (0)
1307 #endif
1308
1309 /* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
1310 smul_ppmm. */
1311 #if !defined (umul_ppmm) && defined (smul_ppmm)
1312 #define umul_ppmm(w1, w0, u, v) \
1313 do { \
1314 UWtype __w1; \
1315 UWtype __xm0 = (u), __xm1 = (v); \
1316 smul_ppmm (__w1, w0, __xm0, __xm1); \
1317 (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \
1318 + (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \
1319 } while (0)
1320 #endif
1321
1322 /* If we still don't have umul_ppmm, define it using plain C. */
1323 #if !defined (umul_ppmm)
1324 #define umul_ppmm(w1, w0, u, v) \
1325 do { \
1326 UWtype __x0, __x1, __x2, __x3; \
1327 UHWtype __ul, __vl, __uh, __vh; \
1328 \
1329 __ul = __ll_lowpart (u); \
1330 __uh = __ll_highpart (u); \
1331 __vl = __ll_lowpart (v); \
1332 __vh = __ll_highpart (v); \
1333 \
1334 __x0 = (UWtype) __ul * __vl; \
1335 __x1 = (UWtype) __ul * __vh; \
1336 __x2 = (UWtype) __uh * __vl; \
1337 __x3 = (UWtype) __uh * __vh; \
1338 \
1339 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1340 __x1 += __x2; /* but this indeed can */ \
1341 if (__x1 < __x2) /* did we get it? */ \
1342 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1343 \
1344 (w1) = __x3 + __ll_highpart (__x1); \
1345 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
1346 } while (0)
1347 #endif
1348
1349 #if !defined (__umulsidi3)
1350 #define __umulsidi3(u, v) \
1351 ({DWunion __w; \
1352 umul_ppmm (__w.s.high, __w.s.low, u, v); \
1353 __w.ll; })
1354 #endif
1355
1356 /* Define this unconditionally, so it can be used for debugging. */
1357 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1358 do { \
1359 UWtype __d1, __d0, __q1, __q0; \
1360 UWtype __r1, __r0, __m; \
1361 __d1 = __ll_highpart (d); \
1362 __d0 = __ll_lowpart (d); \
1363 \
1364 __r1 = (n1) % __d1; \
1365 __q1 = (n1) / __d1; \
1366 __m = (UWtype) __q1 * __d0; \
1367 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
1368 if (__r1 < __m) \
1369 { \
1370 __q1--, __r1 += (d); \
1371 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
1372 if (__r1 < __m) \
1373 __q1--, __r1 += (d); \
1374 } \
1375 __r1 -= __m; \
1376 \
1377 __r0 = __r1 % __d1; \
1378 __q0 = __r1 / __d1; \
1379 __m = (UWtype) __q0 * __d0; \
1380 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
1381 if (__r0 < __m) \
1382 { \
1383 __q0--, __r0 += (d); \
1384 if (__r0 >= (d)) \
1385 if (__r0 < __m) \
1386 __q0--, __r0 += (d); \
1387 } \
1388 __r0 -= __m; \
1389 \
1390 (q) = (UWtype) __q1 * __ll_B | __q0; \
1391 (r) = __r0; \
1392 } while (0)
1393
1394 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1395 __udiv_w_sdiv (defined in libgcc or elsewhere). */
1396 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
1397 #define udiv_qrnnd(q, r, nh, nl, d) \
1398 do { \
1399 USItype __r; \
1400 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
1401 (r) = __r; \
1402 } while (0)
1403 #endif
1404
1405 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1406 #if !defined (udiv_qrnnd)
1407 #define UDIV_NEEDS_NORMALIZATION 1
1408 #define udiv_qrnnd __udiv_qrnnd_c
1409 #endif
1410
1411 #if !defined (count_leading_zeros)
1412 #define count_leading_zeros(count, x) \
1413 do { \
1414 UWtype __xr = (x); \
1415 UWtype __a; \
1416 \
1417 if (W_TYPE_SIZE <= 32) \
1418 { \
1419 __a = __xr < ((UWtype)1<<2*__BITS4) \
1420 ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \
1421 : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
1422 } \
1423 else \
1424 { \
1425 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
1426 if (((__xr >> __a) & 0xff) != 0) \
1427 break; \
1428 } \
1429 \
1430 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
1431 } while (0)
1432 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
1433 #endif
1434
1435 #if !defined (count_trailing_zeros)
1436 /* Define count_trailing_zeros using count_leading_zeros. The latter might be
1437 defined in asm, but if it is not, the C version above is good enough. */
1438 #define count_trailing_zeros(count, x) \
1439 do { \
1440 UWtype __ctz_x = (x); \
1441 UWtype __ctz_c; \
1442 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
1443 (count) = W_TYPE_SIZE - 1 - __ctz_c; \
1444 } while (0)
1445 #endif
1446
1447 #ifndef UDIV_NEEDS_NORMALIZATION
1448 #define UDIV_NEEDS_NORMALIZATION 0
1449 #endif
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