gcc/config/cr16/cr16.h

   1 /* Definitions of target machine for GNU compiler, for CR16.
   2    Copyright (C) 2012-2021 Free Software Foundation, Inc.
   3    Contributed by KPIT Cummins Infosystems Limited.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef GCC_CR16_H
  22 #define GCC_CR16_H
  23
  24 #define OBJECT_FORMAT_ELF
  25
  26 /* Controlling the driver.  */
  27
  28 /* The GNU C++ standard library requires that these macros be defined.  */
  29 #undef CPLUSPLUS_CPP_SPEC
  30 #define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)"
  31
  32 #undef  STARTFILE_SPEC
  33 #define STARTFILE_SPEC "crt1.o%s crti.o%s crtbegin.o%s crtlibid.o%s"
  34
  35 #undef  ENDFILE_SPEC
  36 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
  37
  38 #undef  MATH_LIBRARY
  39 #define MATH_LIBRARY ""
  40
  41 #undef  LIB_SPEC
  42 #define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) \
  43 %{msim*:%{!T*:-Tsim.ld}} \
  44 %{!T*:%{!msim*: %{-Telf32cr16.x}}}"
  45
  46 /* Run-time target specification.  */
  47 #ifndef TARGET_CPU_CPP_BUILTINS
  48 #define TARGET_CPU_CPP_BUILTINS()          \
  49 do                                         \
  50   {                                        \
  51     builtin_define ("__CR__");             \
  52     builtin_define ("__CR16__");           \
  53     builtin_define ("__CR16C__");          \
  54     if (TARGET_CR16CP)                     \
  55       builtin_define ("__CR16CP__");       \
  56     else                                   \
  57       builtin_define ("__CR16CSTD__");     \
  58     if (CR16_TARGET_DATA_NEAR)             \
  59       builtin_define ("__DATA_NEAR__");    \
  60     if (CR16_TARGET_DATA_MEDIUM)           \
  61       builtin_define ("__DATA_MEDIUM__");  \
  62     if (CR16_TARGET_DATA_FAR)              \
  63       builtin_define ("__DATA_FAR__");     \
  64     if (TARGET_INT32)                      \
  65       builtin_define ("__INT32__");        \
  66   }                                        \
  67 while (0)
  68 #endif
  69
  70 /* Force the generation of dwarf .debug_frame sections even if not
  71    compiling -g.  This guarantees that we can unwind the stack.  */
  72 #define DWARF2_FRAME_INFO 1
  73
  74 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
  75
  76 /* Generate .file/.loc directives, so that the assembler generates the
  77    line table.  */
  78 #define DWARF2_ASM_LINE_DEBUG_INFO 1
  79
  80 #define CR16_TARGET_DATA_NEAR   cr16_is_data_model (DM_NEAR)
  81 #define CR16_TARGET_DATA_MEDIUM cr16_is_data_model (DM_DEFAULT)
  82 #define CR16_TARGET_DATA_FAR    cr16_is_data_model (DM_FAR)
  83
  84 /* Storage layout.  */
  85 #define BITS_BIG_ENDIAN     0
  86
  87 #define BYTES_BIG_ENDIAN    0
  88
  89 #define WORDS_BIG_ENDIAN    0
  90
  91 #define UNITS_PER_WORD      2
  92
  93 /* Units per 32-bit (DWORD).  */
  94 #define CR16_UNITS_PER_DWORD 4
  95
  96 #define POINTER_SIZE        32
  97
  98 #define PARM_BOUNDARY       16
  99
 100 #define STACK_BOUNDARY      (MAX (BIGGEST_ALIGNMENT, PARM_BOUNDARY))
 101
 102 #define FUNCTION_BOUNDARY   BIGGEST_ALIGNMENT
 103
 104 /* Biggest alignment on CR16C+ is 32-bit as internal bus is AMBA based
 105    where as CR16C is proprietary internal bus architecture.  */
 106 #define BIGGEST_ALIGNMENT   ((TARGET_CR16CP) ? 32 : 16)
 107
 108 #define MAX_FIXED_MODE_SIZE 64
 109
 110 /* In CR16 arrays of chars are word-aligned, so strcpy () will be faster.  */
 111 #define DATA_ALIGNMENT(TYPE, ALIGN)              \
 112   (((TREE_CODE (TYPE) == ARRAY_TYPE)             \
 113      && (TYPE_MODE (TREE_TYPE (TYPE)) == QImode) \
 114      && ((ALIGN) < BITS_PER_WORD))               \
 115      ? (BITS_PER_WORD) : (ALIGN))
 116
 117 #define STRICT_ALIGNMENT 0
 118
 119 #define PCC_BITFIELD_TYPE_MATTERS 1
 120
 121 /* Layout of source language data types.  */
 122 #define INT_TYPE_SIZE       (TARGET_INT32 ? 32 : 16)
 123
 124 #define SHORT_TYPE_SIZE     16
 125
 126 #define LONG_TYPE_SIZE      32
 127
 128 #define LONG_LONG_TYPE_SIZE 64
 129
 130 #define FLOAT_TYPE_SIZE     32
 131
 132 #define DOUBLE_TYPE_SIZE    64
 133
 134 #define LONG_DOUBLE_TYPE_SIZE 64
 135
 136 #define DEFAULT_SIGNED_CHAR 1
 137
 138 #define SIZE_TYPE           "long unsigned int"
 139
 140 #define PTRDIFF_TYPE        "long int"
 141
 142 #define WCHAR_TYPE          "short unsigned int"
 143
 144 #define WCHAR_TYPE_SIZE     16
 145
 146 /* By default, the C++ compiler will use the lowest bit of the pointer
 147    to function to indicate a pointer-to-member-function points to a
 148    virtual member function.  However, in CR architecture FUNCTION_BOUNDARY
 149    indicates function addresses are always even, but function pointers can be
 150    odd (after right-shifting them when loading them into a register), and the
 151    default doesn't work.  In that case, the lowest bit of the delta
 152    field will be used (the remainder of the field is shifted to the left).  */
 153 #define TARGET_PTRMEMFUNC_VBIT_LOCATION     ptrmemfunc_vbit_in_delta
 154
 155 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
 156    values must be in memory.  */
 157 #define DEFAULT_PCC_STRUCT_RETURN 0
 158
 159 /* Register usage.  */
 160
 161 /* First 32-bit register is R12.  */
 162 #define CR16_FIRST_DWORD_REGISTER   12
 163
 164 #define FIRST_PSEUDO_REGISTER       16
 165
 166 /* 1 for registers that have pervasive standard uses
 167    and are not available for the register allocator.
 168    On the CR16, only the stack pointer (r15) is such.  */
 169 #define FIXED_REGISTERS                               \
 170   {                                                   \
 171   /* r0  r1  r2  r3  r4  r5  r6  r7  r8  r9  r10.  */ \
 172     0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,        \
 173   /* r11 r12 r13 ra  sp.  */                          \
 174     0,  0,  0,  0,  1                                 \
 175   }
 176
 177 /* 1 for registers not available across function calls.
 178    These must include the FIXED_REGISTERS and also any
 179    registers that can be used without being saved.
 180    The latter must include the registers where values are returned
 181    and the register where structure-value addresses are passed.
 182
 183    On the CR16, calls clobbers r0-r6 (scratch registers),
 184    ra (the return address) and sp (the stack pointer).  */
 185 #define CALL_USED_REGISTERS                           \
 186   {                                                   \
 187   /* r0  r1  r2  r3  r4  r5  r6  r7  r8  r9  r10.  */ \
 188     1,  1,  1,  1,  1,  1,  1,  0,  0,  0,  0,        \
 189   /* r11 r12 r13 ra  sp.  */                          \
 190     0,  0,  0,  1,  1                                 \
 191   }
 192
 193 /* Returns 1 if the register is longer than word size, 0 otherwise.  */
 194 #define LONG_REG_P(REGNO)                                                    \
 195   (targetm.hard_regno_nregs (REGNO,                                          \
 196                              GET_MODE_WIDER_MODE (word_mode).require ()) == 1)
 197
 198 /* Interrupt functions can only use registers that have already been
 199    saved by the prologue, even if they would normally be call-clobbered
 200    Check if sizes are same and then check if it is possible to rename.  */
 201 #define HARD_REGNO_RENAME_OK(SRC, DEST)                 \
 202   (!cr16_interrupt_function_p () || (df_regs_ever_live_p (DEST)))
 203
 204 /* Exception handling stuff.  */
 205
 206 /*To ensure correct dwarf unwinding.  */
 207 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((optimize ("no-gcse","no-dse")))
 208
 209 #define gen_rtx_RA      gen_rtx_REG (Pmode, RETURN_ADDRESS_REGNUM)
 210
 211 /* Use (r8,r7) and (r10,r9) to pass exception handling information.  */
 212 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? (N*2 + 7) : INVALID_REGNUM)
 213
 214 #define DWARF2_UNWIND_INFO 1
 215
 216 /* (r5,r4) holds a stack adjustment for returning to a handler.  */
 217 #define EH_RETURN_STACKADJ_RTX          gen_rtx_REG (Pmode, 4)
 218
 219 #define EH_RETURN_HANDLER_RTX \
 220   gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, -4))
 221
 222 #define INCOMING_RETURN_ADDR_RTX        gen_rtx_RA
 223
 224 #define DWARF_FRAME_RETURN_COLUMN       \
 225   DWARF_FRAME_REGNUM (RETURN_ADDRESS_REGNUM)
 226
 227 #define INCOMING_FRAME_SP_OFFSET                0
 228 #define FRAME_POINTER_CFA_OFFSET(FNDECL)        0
 229
 230 /* A C expression whose value is RTL representing the value of the return
 231    address for the frame COUNT steps up from the current frame.  */
 232 #define RETURN_ADDR_RTX(COUNT, FRAME)                                   \
 233   (COUNT == 0)  ?  gen_rtx_PLUS (Pmode, gen_rtx_RA, gen_rtx_RA)         \
 234                 :  const0_rtx
 235
 236 enum reg_class
 237 {
 238   NO_REGS,
 239   SHORT_REGS,
 240   LONG_REGS,
 241   NOSP_REGS,
 242   DOUBLE_BASE_REGS,
 243   GENERAL_REGS,
 244   ALL_REGS,
 245   LIM_REG_CLASSES
 246 };
 247
 248 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 249
 250 #define REG_CLASS_NAMES \
 251   {                     \
 252     "NO_REGS",          \
 253     "SHORT_REGS",       \
 254     "LONG_REGS",        \
 255     "NOSP_REGS",        \
 256     "DOUBLE_BASE_REGS", \
 257     "GENERAL_REGS",     \
 258     "ALL_REGS"          \
 259   }
 260
 261 #define REG_CLASS_CONTENTS                                      \
 262   {                                                             \
 263     {0x00000000}, /* NO_REGS                         */         \
 264     {0x00000FFF}, /* SHORT_REGS         : 0 - 11     */         \
 265     {0x0000F000}, /* LONG_REGS          : 12 - 15    */         \
 266     {0x00007FFF}, /* NOSP_REGS          : 0 - 14     */         \
 267     {0x0000F555}, /* DOUBLE_BASE_REGS   : 2,4,6,8,10 */         \
 268     {0x0000FFFF}, /* GENERAL_REGS       : 0 - 15     */         \
 269     {0x0000FFFF}  /* ALL_REGS           : 0 - 15     */         \
 270   }
 271
 272 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P  hook_bool_mode_true
 273
 274 #define REGNO_REG_CLASS(REGNO)  cr16_regno_reg_class (REGNO)
 275
 276 #define BASE_REG_CLASS      GENERAL_REGS
 277
 278 #define MODE_BASE_REG_CLASS(MODE) \
 279   (GET_MODE_SIZE (MODE) <= 4 ?  (BASE_REG_CLASS) :  (DOUBLE_BASE_REGS))
 280
 281 #define INDEX_REG_CLASS      LONG_REGS
 282
 283 #define CR16_REGNO_OK_FOR_BASE_P(REGNO)                  \
 284   (((REGNO) < FIRST_PSEUDO_REGISTER)                     \
 285      || (reg_renumber && ((unsigned) reg_renumber[REGNO] \
 286                         < FIRST_PSEUDO_REGISTER)))
 287
 288 /* Use even-numbered reg for 64-bit accesses.  */
 289 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE)     \
 290         (CR16_REGNO_OK_FOR_BASE_P(REGNO)  &&      \
 291           ((GET_MODE_SIZE (MODE) > 4  &&          \
 292              (REGNO) < CR16_FIRST_DWORD_REGISTER) \
 293              ? (((REGNO) & 1) == 0)               \
 294              : 1))
 295
 296 /* TODO: For now lets not support index addressing mode.  */
 297 #define REGNO_OK_FOR_INDEX_P(REGNO)        \
 298   (((REGNO >= CR16_FIRST_DWORD_REGISTER)   \
 299      && ((REGNO) < FIRST_PSEUDO_REGISTER)) \
 300    || (reg_renumber                        \
 301        && (((unsigned) reg_renumber[REGNO] >= CR16_FIRST_DWORD_REGISTER)  \
 302             && ((unsigned) reg_renumber[REGNO] < FIRST_PSEUDO_REGISTER))) \
 303   )
 304
 305 #define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
 306
 307 /* The maximum number of consecutive registers of class CLASS needed to
 308    hold a value of mode MODE.
 309    On the CompactRISC architecture, the size of MODE in words.
 310    The size of MODE in double words for the class LONG_REGS.
 311
 312    The following check assumes if the class is not LONG_REGS, then
 313    all (NO_REGS, SHORT_REGS, NOSP_REGS and GENERAL_REGS) other classes are
 314    short.  We may have to check if this can cause any degradation in
 315    performance.  */
 316 #define CLASS_MAX_NREGS(CLASS, MODE) \
 317   (CLASS == LONG_REGS \
 318    ? (GET_MODE_SIZE (MODE) + CR16_UNITS_PER_DWORD - 1) / CR16_UNITS_PER_DWORD\
 319    : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 320
 321 /* Macros to check the range of integers . These macros were used across
 322    the port, majorly in constraints.md, predicates.md files. */
 323 #define SIGNED_INT_FITS_N_BITS(imm, N)           \
 324   ((((imm) < ((HOST_WIDE_INT) 1 << ((N) - 1)))       \
 325       && ((imm) >= -((HOST_WIDE_INT) 1 << ((N) - 1)))) ? 1 : 0)
 326
 327 #define UNSIGNED_INT_FITS_N_BITS(imm, N) \
 328   (((imm) < ((HOST_WIDE_INT) 1 << (N)) && (imm) >= (HOST_WIDE_INT) 0) ? 1 : 0)
 329
 330 #define IN_RANGE_P(VALUE, LOW, HIGH)                            \
 331   ((((HOST_WIDE_INT)(VALUE)) >= (HOST_WIDE_INT)(LOW))           \
 332    && (((HOST_WIDE_INT)(VALUE)) <= ((HOST_WIDE_INT)(HIGH))))
 333
 334 #define IN_RAN(VALUE, LOW, HIGH)                             \
 335   (((((HOST_WIDE_INT)(VALUE)) >= (HOST_WIDE_INT)(LOW))       \
 336    && (((HOST_WIDE_INT)(VALUE)) <= ((HOST_WIDE_INT)(HIGH)))) ? 1 : 0)
 337
 338 /* This check is for sbit/cbit instruction.  */
 339 #define OK_FOR_Z(OP) \
 340   ((GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == CONST_INT) \
 341    || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG) \
 342    || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == PLUS \
 343        && GET_CODE (XEXP ((XEXP (OP, 0)), 0)) == REG \
 344        && GET_CODE (XEXP ((XEXP (OP, 0)), 1)) == CONST_INT))
 345
 346 /* Stack layout and calling conventions.  */
 347 #define STACK_GROWS_DOWNWARD 1
 348
 349 #define STACK_POINTER_REGNUM    15
 350
 351 #define FRAME_POINTER_REGNUM    13
 352
 353 #define ARG_POINTER_REGNUM      12
 354
 355 #define STATIC_CHAIN_REGNUM     1
 356
 357 #define RETURN_ADDRESS_REGNUM   14
 358
 359 #define FIRST_PARM_OFFSET(FNDECL) 0
 360
 361 #define ELIMINABLE_REGS                            \
 362   {                                                \
 363     { ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM}, \
 364     { ARG_POINTER_REGNUM,   FRAME_POINTER_REGNUM}, \
 365     { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}  \
 366   }
 367
 368 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)              \
 369   do                                                              \
 370     {                                                             \
 371       (OFFSET) = cr16_initial_elimination_offset ((FROM), (TO));  \
 372     }                                                             \
 373   while (0)
 374
 375 /* Passing function arguments.  */
 376
 377 #define ACCUMULATE_OUTGOING_ARGS 0
 378
 379 #define PUSH_ROUNDING(BYTES) cr16_push_rounding (BYTES)
 380
 381 #ifndef CUMULATIVE_ARGS
 382 struct cumulative_args
 383 {
 384   int ints;
 385   int last_parm_in_reg;
 386 };
 387
 388 #define CUMULATIVE_ARGS struct cumulative_args
 389 #endif
 390
 391 /* On the CR16 architecture, Varargs routines should receive their parameters
 392    on the stack.  */
 393
 394 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
 395   cr16_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME))
 396
 397 #define FUNCTION_ARG_REGNO_P(REGNO)  cr16_function_arg_regno_p (REGNO)
 398
 399 /* Generating code for profiling - NOT IMPLEMENTED.  */
 400 #undef  FUNCTION_PROFILER
 401 #define FUNCTION_PROFILER(STREAM, LABELNO)      \
 402 {                                               \
 403   sorry ("profiler support for CR16");          \
 404 }
 405
 406 /* Trampolines for nested functions - NOT SUPPORTED.  */
 407 #define TRAMPOLINE_SIZE    16
 408
 409 /* ADDRESSING MODES.  */
 410
 411 #define CONSTANT_ADDRESS_P(X)       \
 412   (GET_CODE (X) == LABEL_REF        \
 413    || GET_CODE (X) == SYMBOL_REF    \
 414    || GET_CODE (X) == CONST         \
 415    || GET_CODE (X) == CONST_INT)
 416
 417 #define MAX_REGS_PER_ADDRESS    2
 418
 419 #define HAVE_POST_INCREMENT     0
 420 #define HAVE_POST_DECREMENT     0
 421 #define HAVE_POST_MODIFY_DISP   0
 422 #define HAVE_POST_MODIFY_REG    0
 423
 424 #ifdef REG_OK_STRICT
 425 #define CR16_REG_OK_FOR_BASE_P(X)       CR16_REGNO_OK_FOR_BASE_P (REGNO (X))
 426 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 427   REGNO_MODE_OK_FOR_BASE_P (REGNO(X), MODE)
 428 #define REG_OK_FOR_INDEX_P(X)   REGNO_OK_FOR_INDEX_P (REGNO (X))
 429 #else /* not REG_OK_STRICT.  */
 430 #define CR16_REG_OK_FOR_BASE_P(X)       1
 431 #define REG_MODE_OK_FOR_BASE_P(X, MODE) 1
 432 #define REG_OK_FOR_INDEX_P(X)   1
 433 #endif /* not REG_OK_STRICT.  */
 434
 435 /* Assume best case (branch predicted).  */
 436 #define BRANCH_COST(speed_p, predictable_p)       2
 437
 438 #define SLOW_BYTE_ACCESS  1
 439
 440 /* It is as good or better to call a constant function address than to
 441    call an address kept in a register.  */
 442 #define NO_FUNCTION_CSE 1
 443
 444 /* Dividing the output into sections.  */
 445
 446 #define TEXT_SECTION_ASM_OP "\t.section\t.text"
 447
 448 #define DATA_SECTION_ASM_OP "\t.section\t.data"
 449
 450 #define BSS_SECTION_ASM_OP  "\t.section\t.bss"
 451
 452 /* Position independent code (PIC).  */
 453 /* NEAR_PIC for -fpic option.  */
 454
 455 #define NEAR_PIC 1
 456
 457 /* FAR_PIC for -fPIC option.  */
 458
 459 #define FAR_PIC  2
 460
 461 #define PIC_OFFSET_TABLE_REGNUM  12
 462
 463 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
 464
 465 /* Assembler format.  */
 466
 467 /* Character to start a comment.  */
 468 #define ASM_COMMENT_START "#"
 469
 470 #define GLOBAL_ASM_OP "\t.globl\t"
 471
 472 #undef USER_LABEL_PREFIX
 473 #define USER_LABEL_PREFIX "_"
 474
 475 #undef ASM_OUTPUT_LABELREF
 476 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
 477   asm_fprintf (STREAM, "%U%s", (*targetm.strip_name_encoding) (NAME))
 478
 479 #define ASM_OUTPUT_SYMBOL_REF(STREAM, SYMBOL)   \
 480   do                                            \
 481     {                                           \
 482       const char *rn = XSTR (SYMBOL, 0);        \
 483       assemble_name (STREAM, rn);               \
 484       if (SYMBOL_REF_FUNCTION_P (SYMBOL))       \
 485       {                                         \
 486         fprintf ((STREAM), "@c");               \
 487       }                                         \
 488     }                                           \
 489   while (0)
 490
 491 #undef ASM_APP_ON
 492 #define ASM_APP_ON   "#APP\n"
 493
 494 #undef ASM_APP_OFF
 495 #define ASM_APP_OFF  "#NO_APP\n"
 496
 497 /* Switch into a generic section.  */
 498 #define TARGET_ASM_NAMED_SECTION        default_elf_asm_named_section
 499
 500 #undef INIT_SECTION_ASM_OP
 501 #define INIT_SECTION_ASM_OP             "\t.section\t.init"
 502
 503 #undef FINI_SECTION_ASM_OP
 504 #define FINI_SECTION_ASM_OP             "\t.section\t.fini"
 505
 506 /* Instruction output.  */
 507
 508 #define REGISTER_NAMES                                     \
 509   {                                                        \
 510     "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7", \
 511     "r8",  "r9",  "r10", "r11", "r12", "r13", "ra",  "sp"  \
 512   }
 513
 514 /* Output of dispatch tables.  */
 515
 516 /* Revisit. No PC relative case as label expressions are not
 517    properly supported in binutils else we could have done this:
 518    #define CASE_VECTOR_PC_RELATIVE (optimize_size ? 1 : 0).  */
 519 #define CASE_VECTOR_PC_RELATIVE 0
 520
 521 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)    \
 522   ((GET_MODE (BODY) == QImode)                              \
 523    ? fprintf ((FILE), "\t.byte (.L%d-.L%d) >> 1\n",         \
 524               VALUE, REL)                                   \
 525    : fprintf ((FILE), "\t.word (.L%d-.L%d) >> 1\n",         \
 526               VALUE, REL))
 527
 528 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
 529   asm_fprintf ((STREAM), "\t.long\t.L%d@c\n", (VALUE))
 530
 531 /* Alignment in assembler file.  */
 532
 533 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
 534   asm_fprintf ((STREAM), "\t.align\t%d\n", 1 << (POWER))
 535
 536 /* Miscellaneous parameters.  */
 537
 538 #define CASE_VECTOR_MODE  Pmode
 539
 540 #define MOVE_MAX 4
 541
 542 #define STORE_FLAG_VALUE  1
 543
 544 #define Pmode SImode
 545
 546 #define FUNCTION_MODE QImode
 547
 548 /* Define this boolean macro(s) to indicate whether or not your architecture
 549    has (un)conditional branches that can span all of memory.  It is used in
 550    conjunction with an optimization that partitions hot and cold basic blocks
 551    into separate sections of the executable.
 552    CR16 contains branch instructions that span whole address space.  */
 553 #define HAS_LONG_COND_BRANCH    1
 554 #define HAS_LONG_UNCOND_BRANCH  1
 555
 556 #endif /* End of GCC_CR16_H.  */