Daily bump.
[official-gcc.git] / libgcc / config / aarch64 / linux-unwind.h
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1 /* Copyright (C) 2009-2015 Free Software Foundation, Inc.
2 Contributed by ARM Ltd.
4 This file is free software; you can redistribute it and/or modify it
5 under the terms of the GNU General Public License as published by the
6 Free Software Foundation; either version 3, or (at your option) any
7 later version.
9 This file is distributed in the hope that it will be useful, but
10 WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 General Public License for more details.
14 Under Section 7 of GPL version 3, you are granted additional
15 permissions described in the GCC Runtime Library Exception, version
16 3.1, as published by the Free Software Foundation.
18 You should have received a copy of the GNU General Public License and
19 a copy of the GCC Runtime Library Exception along with this program;
20 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
21 <http://www.gnu.org/licenses/>. */
23 #ifndef inhibit_libc
25 #include <signal.h>
26 #include <sys/ucontext.h>
29 /* Since insns are always stored LE, on a BE system the opcodes will
30 be loaded byte-reversed. Therefore, define two sets of opcodes,
31 one for LE and one for BE. */
33 #if __AARCH64EB__
34 #define MOVZ_X8_8B 0x681180d2
35 #define SVC_0 0x010000d4
36 #else
37 #define MOVZ_X8_8B 0xd2801168
38 #define SVC_0 0xd4000001
39 #endif
41 #define MD_FALLBACK_FRAME_STATE_FOR aarch64_fallback_frame_state
43 static _Unwind_Reason_Code
44 aarch64_fallback_frame_state (struct _Unwind_Context *context,
45 _Unwind_FrameState * fs)
47 /* The kernel creates an rt_sigframe on the stack immediately prior
48 to delivering a signal.
50 This structure must have the same shape as the linux kernel
51 equivalent. */
52 struct rt_sigframe
54 siginfo_t info;
55 struct ucontext uc;
58 struct rt_sigframe *rt_;
59 _Unwind_Ptr new_cfa;
60 unsigned *pc = context->ra;
61 struct sigcontext *sc;
62 struct _aarch64_ctx *extension_marker;
63 int i;
65 /* A signal frame will have a return address pointing to
66 __default_sa_restorer. This code is hardwired as:
68 0xd2801168 movz x8, #0x8b
69 0xd4000001 svc 0x0
71 if (pc[0] != MOVZ_X8_8B || pc[1] != SVC_0)
73 return _URC_END_OF_STACK;
76 rt_ = context->cfa;
77 sc = &rt_->uc.uc_mcontext;
79 /* This define duplicates the definition in aarch64.md */
80 #define SP_REGNUM 31
82 new_cfa = (_Unwind_Ptr) sc;
83 fs->regs.cfa_how = CFA_REG_OFFSET;
84 fs->regs.cfa_reg = __LIBGCC_STACK_POINTER_REGNUM__;
85 fs->regs.cfa_offset = new_cfa - (_Unwind_Ptr) context->cfa;
87 for (i = 0; i < AARCH64_DWARF_NUMBER_R; i++)
89 fs->regs.reg[AARCH64_DWARF_R0 + i].how = REG_SAVED_OFFSET;
90 fs->regs.reg[AARCH64_DWARF_R0 + i].loc.offset =
91 (_Unwind_Ptr) & (sc->regs[i]) - new_cfa;
94 /* The core context may be extended with an arbitrary set of
95 additional contexts appended sequentially. Each additional
96 context contains a magic identifier and size in bytes. The size
97 field can be used to skip over unrecognized context extensions.
98 The end of the context sequence is marked by a context with magic
99 0 or size 0. */
100 for (extension_marker = (struct _aarch64_ctx *) &sc->__reserved;
101 extension_marker->magic;
102 extension_marker = (struct _aarch64_ctx *)
103 ((unsigned char *) extension_marker + extension_marker->size))
105 if (extension_marker->magic == FPSIMD_MAGIC)
107 struct fpsimd_context *ctx =
108 (struct fpsimd_context *) extension_marker;
109 int i;
111 for (i = 0; i < AARCH64_DWARF_NUMBER_V; i++)
113 _Unwind_Sword offset;
115 fs->regs.reg[AARCH64_DWARF_V0 + i].how = REG_SAVED_OFFSET;
117 /* sigcontext contains 32 128bit registers for V0 to
118 V31. The kernel will have saved the contents of the
119 V registers. We want to unwind the callee save D
120 registers. Each D register comprises the least
121 significant half of the corresponding V register. We
122 need to offset into the saved V register dependent on
123 our endianness to find the saved D register. */
125 offset = (_Unwind_Ptr) & (ctx->vregs[i]) - new_cfa;
127 /* The endianness adjustment code below expects that a
128 saved V register is 16 bytes. */
129 gcc_assert (sizeof (ctx->vregs[0]) == 16);
130 #if defined (__AARCH64EB__)
131 offset = offset + 8;
132 #endif
133 fs->regs.reg[AARCH64_DWARF_V0 + i].loc.offset = offset;
136 else
138 /* There is context provided that we do not recognize! */
142 fs->regs.reg[31].how = REG_SAVED_OFFSET;
143 fs->regs.reg[31].loc.offset = (_Unwind_Ptr) & (sc->sp) - new_cfa;
145 fs->signal_frame = 1;
147 fs->regs.reg[__LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__].how =
148 REG_SAVED_VAL_OFFSET;
149 fs->regs.reg[__LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__].loc.offset =
150 (_Unwind_Ptr) (sc->pc) - new_cfa;
152 fs->retaddr_column = __LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__;
154 return _URC_NO_REASON;
157 #endif