1 /* Copyright (C) 1997-2013 Free Software Foundation, Inc.
2 Contributed by Red Hat, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
32 #include "insn-attr.h"
41 #include "diagnostic-core.h"
42 #include "basic-block.h"
46 #include "target-def.h"
47 #include "targhooks.h"
48 #include "langhooks.h"
53 #define FRV_INLINE inline
56 /* The maximum number of distinct NOP patterns. There are three:
57 nop, fnop and mnop. */
58 #define NUM_NOP_PATTERNS 3
60 /* Classification of instructions and units: integer, floating-point/media,
61 branch and control. */
62 enum frv_insn_group
{ GROUP_I
, GROUP_FM
, GROUP_B
, GROUP_C
, NUM_GROUPS
};
64 /* The DFA names of the units, in packet order. */
65 static const char *const frv_unit_names
[] =
75 /* The classification of each unit in frv_unit_names[]. */
76 static const enum frv_insn_group frv_unit_groups
[ARRAY_SIZE (frv_unit_names
)] =
86 /* Return the DFA unit code associated with the Nth unit of integer
87 or floating-point group GROUP, */
88 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
90 /* Return the number of integer or floating-point unit UNIT
91 (1 for I1, 2 for F2, etc.). */
92 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
94 /* The DFA unit number for each unit in frv_unit_names[]. */
95 static int frv_unit_codes
[ARRAY_SIZE (frv_unit_names
)];
97 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
98 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
99 no instruction of type T has been seen. */
100 static unsigned int frv_type_to_unit
[TYPE_UNKNOWN
+ 1];
102 /* An array of dummy nop INSNs, one for each type of nop that the
104 static GTY(()) rtx frv_nops
[NUM_NOP_PATTERNS
];
106 /* The number of nop instructions in frv_nops[]. */
107 static unsigned int frv_num_nops
;
109 /* The type of access. FRV_IO_UNKNOWN means the access can be either
110 a read or a write. */
111 enum frv_io_type
{ FRV_IO_UNKNOWN
, FRV_IO_READ
, FRV_IO_WRITE
};
113 /* Information about one __builtin_read or __builtin_write access, or
114 the combination of several such accesses. The most general value
115 is all-zeros (an unknown access to an unknown address). */
117 enum frv_io_type type
;
119 /* The constant address being accessed, or zero if not known. */
120 HOST_WIDE_INT const_address
;
122 /* The run-time address, as used in operand 0 of the membar pattern. */
126 /* Return true if instruction INSN should be packed with the following
128 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
130 /* Set the value of PACKING_FLAG_P(INSN). */
131 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
132 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
134 /* Loop with REG set to each hard register in rtx X. */
135 #define FOR_EACH_REGNO(REG, X) \
136 for (REG = REGNO (X); \
137 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
140 /* This structure contains machine specific function data. */
141 struct GTY(()) machine_function
143 /* True if we have created an rtx that relies on the stack frame. */
146 /* True if this function contains at least one __builtin_{read,write}*. */
150 /* Temporary register allocation support structure. */
151 typedef struct frv_tmp_reg_struct
153 HARD_REG_SET regs
; /* possible registers to allocate */
154 int next_reg
[N_REG_CLASSES
]; /* next register to allocate per class */
158 /* Register state information for VLIW re-packing phase. */
159 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
160 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
161 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
162 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
164 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
166 typedef unsigned char regstate_t
;
168 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
176 /* Information required by frv_frame_access. */
179 /* This field is FRV_LOAD if registers are to be loaded from the stack and
180 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
181 the move is being done by the prologue code while FRV_LOAD implies it
182 is being done by the epilogue. */
183 enum frv_stack_op op
;
185 /* The base register to use when accessing the stack. This may be the
186 frame pointer, stack pointer, or a temporary. The choice of register
187 depends on which part of the frame is being accessed and how big the
191 /* The offset of BASE from the bottom of the current frame, in bytes. */
193 } frv_frame_accessor_t
;
195 /* Conditional execution support gathered together in one structure. */
198 /* Linked list of insns to add if the conditional execution conversion was
199 successful. Each link points to an EXPR_LIST which points to the pattern
200 of the insn to add, and the insn to be inserted before. */
201 rtx added_insns_list
;
203 /* Identify which registers are safe to allocate for if conversions to
204 conditional execution. We keep the last allocated register in the
205 register classes between COND_EXEC statements. This will mean we allocate
206 different registers for each different COND_EXEC group if we can. This
207 might allow the scheduler to intermix two different COND_EXEC sections. */
208 frv_tmp_reg_t tmp_reg
;
210 /* For nested IFs, identify which CC registers are used outside of setting
211 via a compare isnsn, and using via a check insn. This will allow us to
212 know if we can rewrite the register to use a different register that will
213 be paired with the CR register controlling the nested IF-THEN blocks. */
214 HARD_REG_SET nested_cc_ok_rewrite
;
216 /* Temporary registers allocated to hold constants during conditional
218 rtx scratch_regs
[FIRST_PSEUDO_REGISTER
];
220 /* Current number of temp registers available. */
221 int cur_scratch_regs
;
223 /* Number of nested conditional execution blocks. */
224 int num_nested_cond_exec
;
226 /* Map of insns that set up constants in scratch registers. */
227 bitmap scratch_insns_bitmap
;
229 /* Conditional execution test register (CC0..CC7). */
232 /* Conditional execution compare register that is paired with cr_reg, so that
233 nested compares can be done. The csubcc and caddcc instructions don't
234 have enough bits to specify both a CC register to be set and a CR register
235 to do the test on, so the same bit number is used for both. Needless to
236 say, this is rather inconvenient for GCC. */
239 /* Extra CR registers used for &&, ||. */
243 /* Previous CR used in nested if, to make sure we are dealing with the same
244 nested if as the previous statement. */
245 rtx last_nested_if_cr
;
249 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt
;
251 /* Map register number to smallest register class. */
252 enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
];
254 /* Cached value of frv_stack_info. */
255 static frv_stack_t
*frv_stack_cache
= (frv_stack_t
*)0;
257 /* Forward references */
259 static void frv_option_override (void);
260 static bool frv_legitimate_address_p (enum machine_mode
, rtx
, bool);
261 static int frv_default_flags_for_cpu (void);
262 static int frv_string_begins_with (const_tree
, const char *);
263 static FRV_INLINE
bool frv_small_data_reloc_p (rtx
, int);
264 static void frv_print_operand (FILE *, rtx
, int);
265 static void frv_print_operand_address (FILE *, rtx
);
266 static bool frv_print_operand_punct_valid_p (unsigned char code
);
267 static void frv_print_operand_memory_reference_reg
269 static void frv_print_operand_memory_reference (FILE *, rtx
, int);
270 static int frv_print_operand_jump_hint (rtx
);
271 static const char *comparison_string (enum rtx_code
, rtx
);
272 static rtx
frv_function_value (const_tree
, const_tree
,
274 static rtx
frv_libcall_value (enum machine_mode
,
276 static FRV_INLINE
int frv_regno_ok_for_base_p (int, int);
277 static rtx
single_set_pattern (rtx
);
278 static int frv_function_contains_far_jump (void);
279 static rtx
frv_alloc_temp_reg (frv_tmp_reg_t
*,
283 static rtx
frv_frame_offset_rtx (int);
284 static rtx
frv_frame_mem (enum machine_mode
, rtx
, int);
285 static rtx
frv_dwarf_store (rtx
, int);
286 static void frv_frame_insn (rtx
, rtx
);
287 static void frv_frame_access (frv_frame_accessor_t
*,
289 static void frv_frame_access_multi (frv_frame_accessor_t
*,
291 static void frv_frame_access_standard_regs (enum frv_stack_op
,
293 static struct machine_function
*frv_init_machine_status (void);
294 static rtx
frv_int_to_acc (enum insn_code
, int, rtx
);
295 static enum machine_mode
frv_matching_accg_mode (enum machine_mode
);
296 static rtx
frv_read_argument (tree
, unsigned int);
297 static rtx
frv_read_iacc_argument (enum machine_mode
, tree
, unsigned int);
298 static int frv_check_constant_argument (enum insn_code
, int, rtx
);
299 static rtx
frv_legitimize_target (enum insn_code
, rtx
);
300 static rtx
frv_legitimize_argument (enum insn_code
, int, rtx
);
301 static rtx
frv_legitimize_tls_address (rtx
, enum tls_model
);
302 static rtx
frv_legitimize_address (rtx
, rtx
, enum machine_mode
);
303 static rtx
frv_expand_set_builtin (enum insn_code
, tree
, rtx
);
304 static rtx
frv_expand_unop_builtin (enum insn_code
, tree
, rtx
);
305 static rtx
frv_expand_binop_builtin (enum insn_code
, tree
, rtx
);
306 static rtx
frv_expand_cut_builtin (enum insn_code
, tree
, rtx
);
307 static rtx
frv_expand_binopimm_builtin (enum insn_code
, tree
, rtx
);
308 static rtx
frv_expand_voidbinop_builtin (enum insn_code
, tree
);
309 static rtx
frv_expand_int_void2arg (enum insn_code
, tree
);
310 static rtx
frv_expand_prefetches (enum insn_code
, tree
);
311 static rtx
frv_expand_voidtriop_builtin (enum insn_code
, tree
);
312 static rtx
frv_expand_voidaccop_builtin (enum insn_code
, tree
);
313 static rtx
frv_expand_mclracc_builtin (tree
);
314 static rtx
frv_expand_mrdacc_builtin (enum insn_code
, tree
);
315 static rtx
frv_expand_mwtacc_builtin (enum insn_code
, tree
);
316 static rtx
frv_expand_noargs_builtin (enum insn_code
);
317 static void frv_split_iacc_move (rtx
, rtx
);
318 static rtx
frv_emit_comparison (enum rtx_code
, rtx
, rtx
);
319 static int frv_clear_registers_used (rtx
*, void *);
320 static void frv_ifcvt_add_insn (rtx
, rtx
, int);
321 static rtx
frv_ifcvt_rewrite_mem (rtx
, enum machine_mode
, rtx
);
322 static rtx
frv_ifcvt_load_value (rtx
, rtx
);
323 static int frv_acc_group_1 (rtx
*, void *);
324 static unsigned int frv_insn_unit (rtx
);
325 static bool frv_issues_to_branch_unit_p (rtx
);
326 static int frv_cond_flags (rtx
);
327 static bool frv_regstate_conflict_p (regstate_t
, regstate_t
);
328 static int frv_registers_conflict_p_1 (rtx
*, void *);
329 static bool frv_registers_conflict_p (rtx
);
330 static void frv_registers_update_1 (rtx
, const_rtx
, void *);
331 static void frv_registers_update (rtx
);
332 static void frv_start_packet (void);
333 static void frv_start_packet_block (void);
334 static void frv_finish_packet (void (*) (void));
335 static bool frv_pack_insn_p (rtx
);
336 static void frv_add_insn_to_packet (rtx
);
337 static void frv_insert_nop_in_packet (rtx
);
338 static bool frv_for_each_packet (void (*) (void));
339 static bool frv_sort_insn_group_1 (enum frv_insn_group
,
340 unsigned int, unsigned int,
341 unsigned int, unsigned int,
343 static int frv_compare_insns (const void *, const void *);
344 static void frv_sort_insn_group (enum frv_insn_group
);
345 static void frv_reorder_packet (void);
346 static void frv_fill_unused_units (enum frv_insn_group
);
347 static void frv_align_label (void);
348 static void frv_reorg_packet (void);
349 static void frv_register_nop (rtx
);
350 static void frv_reorg (void);
351 static void frv_pack_insns (void);
352 static void frv_function_prologue (FILE *, HOST_WIDE_INT
);
353 static void frv_function_epilogue (FILE *, HOST_WIDE_INT
);
354 static bool frv_assemble_integer (rtx
, unsigned, int);
355 static void frv_init_builtins (void);
356 static rtx
frv_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
357 static void frv_init_libfuncs (void);
358 static bool frv_in_small_data_p (const_tree
);
359 static void frv_asm_output_mi_thunk
360 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
361 static void frv_setup_incoming_varargs (cumulative_args_t
,
364 static rtx
frv_expand_builtin_saveregs (void);
365 static void frv_expand_builtin_va_start (tree
, rtx
);
366 static bool frv_rtx_costs (rtx
, int, int, int, int*,
368 static int frv_register_move_cost (enum machine_mode
,
369 reg_class_t
, reg_class_t
);
370 static int frv_memory_move_cost (enum machine_mode
,
372 static void frv_asm_out_constructor (rtx
, int);
373 static void frv_asm_out_destructor (rtx
, int);
374 static bool frv_function_symbol_referenced_p (rtx
);
375 static bool frv_legitimate_constant_p (enum machine_mode
, rtx
);
376 static bool frv_cannot_force_const_mem (enum machine_mode
, rtx
);
377 static const char *unspec_got_name (int);
378 static void frv_output_const_unspec (FILE *,
379 const struct frv_unspec
*);
380 static bool frv_function_ok_for_sibcall (tree
, tree
);
381 static rtx
frv_struct_value_rtx (tree
, int);
382 static bool frv_must_pass_in_stack (enum machine_mode mode
, const_tree type
);
383 static int frv_arg_partial_bytes (cumulative_args_t
, enum machine_mode
,
385 static rtx
frv_function_arg (cumulative_args_t
, enum machine_mode
,
387 static rtx
frv_function_incoming_arg (cumulative_args_t
, enum machine_mode
,
389 static void frv_function_arg_advance (cumulative_args_t
, enum machine_mode
,
391 static unsigned int frv_function_arg_boundary (enum machine_mode
,
393 static void frv_output_dwarf_dtprel (FILE *, int, rtx
)
395 static reg_class_t
frv_secondary_reload (bool, rtx
, reg_class_t
,
397 secondary_reload_info
*);
398 static bool frv_frame_pointer_required (void);
399 static bool frv_can_eliminate (const int, const int);
400 static void frv_conditional_register_usage (void);
401 static void frv_trampoline_init (rtx
, tree
, rtx
);
402 static bool frv_class_likely_spilled_p (reg_class_t
);
404 /* Initialize the GCC target structure. */
405 #undef TARGET_PRINT_OPERAND
406 #define TARGET_PRINT_OPERAND frv_print_operand
407 #undef TARGET_PRINT_OPERAND_ADDRESS
408 #define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address
409 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
410 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p
411 #undef TARGET_ASM_FUNCTION_PROLOGUE
412 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
413 #undef TARGET_ASM_FUNCTION_EPILOGUE
414 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
415 #undef TARGET_ASM_INTEGER
416 #define TARGET_ASM_INTEGER frv_assemble_integer
417 #undef TARGET_OPTION_OVERRIDE
418 #define TARGET_OPTION_OVERRIDE frv_option_override
419 #undef TARGET_INIT_BUILTINS
420 #define TARGET_INIT_BUILTINS frv_init_builtins
421 #undef TARGET_EXPAND_BUILTIN
422 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
423 #undef TARGET_INIT_LIBFUNCS
424 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
425 #undef TARGET_IN_SMALL_DATA_P
426 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
427 #undef TARGET_REGISTER_MOVE_COST
428 #define TARGET_REGISTER_MOVE_COST frv_register_move_cost
429 #undef TARGET_MEMORY_MOVE_COST
430 #define TARGET_MEMORY_MOVE_COST frv_memory_move_cost
431 #undef TARGET_RTX_COSTS
432 #define TARGET_RTX_COSTS frv_rtx_costs
433 #undef TARGET_ASM_CONSTRUCTOR
434 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
435 #undef TARGET_ASM_DESTRUCTOR
436 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
438 #undef TARGET_ASM_OUTPUT_MI_THUNK
439 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
440 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
441 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
443 #undef TARGET_SCHED_ISSUE_RATE
444 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
446 #undef TARGET_LEGITIMIZE_ADDRESS
447 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
449 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
450 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
451 #undef TARGET_LEGITIMATE_CONSTANT_P
452 #define TARGET_LEGITIMATE_CONSTANT_P frv_legitimate_constant_p
453 #undef TARGET_CANNOT_FORCE_CONST_MEM
454 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
456 #undef TARGET_HAVE_TLS
457 #define TARGET_HAVE_TLS HAVE_AS_TLS
459 #undef TARGET_STRUCT_VALUE_RTX
460 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
461 #undef TARGET_MUST_PASS_IN_STACK
462 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
463 #undef TARGET_PASS_BY_REFERENCE
464 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
465 #undef TARGET_ARG_PARTIAL_BYTES
466 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
467 #undef TARGET_FUNCTION_ARG
468 #define TARGET_FUNCTION_ARG frv_function_arg
469 #undef TARGET_FUNCTION_INCOMING_ARG
470 #define TARGET_FUNCTION_INCOMING_ARG frv_function_incoming_arg
471 #undef TARGET_FUNCTION_ARG_ADVANCE
472 #define TARGET_FUNCTION_ARG_ADVANCE frv_function_arg_advance
473 #undef TARGET_FUNCTION_ARG_BOUNDARY
474 #define TARGET_FUNCTION_ARG_BOUNDARY frv_function_arg_boundary
476 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
477 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
478 #undef TARGET_SETUP_INCOMING_VARARGS
479 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
480 #undef TARGET_MACHINE_DEPENDENT_REORG
481 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
483 #undef TARGET_EXPAND_BUILTIN_VA_START
484 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
487 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
488 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
491 #undef TARGET_CLASS_LIKELY_SPILLED_P
492 #define TARGET_CLASS_LIKELY_SPILLED_P frv_class_likely_spilled_p
494 #undef TARGET_SECONDARY_RELOAD
495 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
497 #undef TARGET_LEGITIMATE_ADDRESS_P
498 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
500 #undef TARGET_FRAME_POINTER_REQUIRED
501 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
503 #undef TARGET_CAN_ELIMINATE
504 #define TARGET_CAN_ELIMINATE frv_can_eliminate
506 #undef TARGET_CONDITIONAL_REGISTER_USAGE
507 #define TARGET_CONDITIONAL_REGISTER_USAGE frv_conditional_register_usage
509 #undef TARGET_TRAMPOLINE_INIT
510 #define TARGET_TRAMPOLINE_INIT frv_trampoline_init
512 #undef TARGET_FUNCTION_VALUE
513 #define TARGET_FUNCTION_VALUE frv_function_value
514 #undef TARGET_LIBCALL_VALUE
515 #define TARGET_LIBCALL_VALUE frv_libcall_value
517 struct gcc_target targetm
= TARGET_INITIALIZER
;
519 #define FRV_SYMBOL_REF_TLS_P(RTX) \
520 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
523 /* Any function call that satisfies the machine-independent
524 requirements is eligible on FR-V. */
527 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
528 tree exp ATTRIBUTE_UNUSED
)
533 /* Return true if SYMBOL is a small data symbol and relocation RELOC
534 can be used to access it directly in a load or store. */
536 static FRV_INLINE
bool
537 frv_small_data_reloc_p (rtx symbol
, int reloc
)
539 return (GET_CODE (symbol
) == SYMBOL_REF
540 && SYMBOL_REF_SMALL_P (symbol
)
541 && (!TARGET_FDPIC
|| flag_pic
== 1)
542 && (reloc
== R_FRV_GOTOFF12
|| reloc
== R_FRV_GPREL12
));
545 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
549 frv_const_unspec_p (rtx x
, struct frv_unspec
*unspec
)
551 if (GET_CODE (x
) == CONST
)
555 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
557 unspec
->offset
+= INTVAL (XEXP (x
, 1));
560 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_GOT
)
562 unspec
->symbol
= XVECEXP (x
, 0, 0);
563 unspec
->reloc
= INTVAL (XVECEXP (x
, 0, 1));
565 if (unspec
->offset
== 0)
568 if (frv_small_data_reloc_p (unspec
->symbol
, unspec
->reloc
)
569 && unspec
->offset
> 0
570 && unspec
->offset
< g_switch_value
)
577 /* Decide whether we can force certain constants to memory. If we
578 decide we can't, the caller should be able to cope with it in
581 We never allow constants to be forced into memory for TARGET_FDPIC.
582 This is necessary for several reasons:
584 1. Since frv_legitimate_constant_p rejects constant pool addresses, the
585 target-independent code will try to force them into the constant
586 pool, thus leading to infinite recursion.
588 2. We can never introduce new constant pool references during reload.
589 Any such reference would require use of the pseudo FDPIC register.
591 3. We can't represent a constant added to a function pointer (which is
592 not the same as a pointer to a function+constant).
594 4. In many cases, it's more efficient to calculate the constant in-line. */
597 frv_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
,
598 rtx x ATTRIBUTE_UNUSED
)
604 frv_default_flags_for_cpu (void)
606 switch (frv_cpu_type
)
608 case FRV_CPU_GENERIC
:
609 return MASK_DEFAULT_FRV
;
612 return MASK_DEFAULT_FR550
;
616 return MASK_DEFAULT_FR500
;
619 return MASK_DEFAULT_FR450
;
623 return MASK_DEFAULT_FR400
;
627 return MASK_DEFAULT_SIMPLE
;
634 /* Implement TARGET_OPTION_OVERRIDE. */
637 frv_option_override (void)
642 target_flags
|= (frv_default_flags_for_cpu () & ~target_flags_explicit
);
644 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
645 linker about linking pic and non-pic code. */
648 if (!flag_pic
) /* -fPIC */
651 if (!global_options_set
.x_g_switch_value
) /* -G0 */
657 /* A C expression whose value is a register class containing hard
658 register REGNO. In general there is more than one such class;
659 choose a class which is "minimal", meaning that no smaller class
660 also contains the register. */
662 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
664 enum reg_class rclass
;
668 int gpr_reg
= regno
- GPR_FIRST
;
670 if (gpr_reg
== GR8_REG
)
673 else if (gpr_reg
== GR9_REG
)
676 else if (gpr_reg
== GR14_REG
)
677 rclass
= FDPIC_FPTR_REGS
;
679 else if (gpr_reg
== FDPIC_REGNO
)
682 else if ((gpr_reg
& 3) == 0)
685 else if ((gpr_reg
& 1) == 0)
692 else if (FPR_P (regno
))
694 int fpr_reg
= regno
- GPR_FIRST
;
695 if ((fpr_reg
& 3) == 0)
696 rclass
= QUAD_FPR_REGS
;
698 else if ((fpr_reg
& 1) == 0)
705 else if (regno
== LR_REGNO
)
708 else if (regno
== LCR_REGNO
)
711 else if (ICC_P (regno
))
714 else if (FCC_P (regno
))
717 else if (ICR_P (regno
))
720 else if (FCR_P (regno
))
723 else if (ACC_P (regno
))
725 int r
= regno
- ACC_FIRST
;
727 rclass
= QUAD_ACC_REGS
;
728 else if ((r
& 1) == 0)
729 rclass
= EVEN_ACC_REGS
;
734 else if (ACCG_P (regno
))
740 regno_reg_class
[regno
] = rclass
;
743 /* Check for small data option */
744 if (!global_options_set
.x_g_switch_value
&& !TARGET_LIBPIC
)
745 g_switch_value
= SDATA_DEFAULT_SIZE
;
747 /* There is no single unaligned SI op for PIC code. Sometimes we
748 need to use ".4byte" and sometimes we need to use ".picptr".
749 See frv_assemble_integer for details. */
750 if (flag_pic
|| TARGET_FDPIC
)
751 targetm
.asm_out
.unaligned_op
.si
= 0;
753 if ((target_flags_explicit
& MASK_LINKED_FP
) == 0)
754 target_flags
|= MASK_LINKED_FP
;
756 if ((target_flags_explicit
& MASK_OPTIMIZE_MEMBAR
) == 0)
757 target_flags
|= MASK_OPTIMIZE_MEMBAR
;
759 for (i
= 0; i
< ARRAY_SIZE (frv_unit_names
); i
++)
760 frv_unit_codes
[i
] = get_cpu_unit_code (frv_unit_names
[i
]);
762 for (i
= 0; i
< ARRAY_SIZE (frv_type_to_unit
); i
++)
763 frv_type_to_unit
[i
] = ARRAY_SIZE (frv_unit_codes
);
765 init_machine_status
= frv_init_machine_status
;
769 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
772 frv_string_begins_with (const_tree name
, const char *prefix
)
774 const int prefix_len
= strlen (prefix
);
776 /* Remember: NAME's length includes the null terminator. */
777 return (TREE_STRING_LENGTH (name
) > prefix_len
778 && strncmp (TREE_STRING_POINTER (name
), prefix
, prefix_len
) == 0);
781 /* Zero or more C statements that may conditionally modify two variables
782 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
783 been initialized from the two preceding macros.
785 This is necessary in case the fixed or call-clobbered registers depend on
788 You need not define this macro if it has no work to do.
790 If the usage of an entire class of registers depends on the target flags,
791 you may indicate this to GCC by using this macro to modify `fixed_regs' and
792 `call_used_regs' to 1 for each of the registers in the classes which should
793 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
794 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
796 (However, if this class is not included in `GENERAL_REGS' and all of the
797 insn patterns whose constraints permit this class are controlled by target
798 switches, then GCC will automatically avoid using these registers when the
799 target switches are opposed to them.) */
802 frv_conditional_register_usage (void)
806 for (i
= GPR_FIRST
+ NUM_GPRS
; i
<= GPR_LAST
; i
++)
807 fixed_regs
[i
] = call_used_regs
[i
] = 1;
809 for (i
= FPR_FIRST
+ NUM_FPRS
; i
<= FPR_LAST
; i
++)
810 fixed_regs
[i
] = call_used_regs
[i
] = 1;
812 /* Reserve the registers used for conditional execution. At present, we need
813 1 ICC and 1 ICR register. */
814 fixed_regs
[ICC_TEMP
] = call_used_regs
[ICC_TEMP
] = 1;
815 fixed_regs
[ICR_TEMP
] = call_used_regs
[ICR_TEMP
] = 1;
819 fixed_regs
[ICC_FIRST
] = call_used_regs
[ICC_FIRST
] = 1;
820 fixed_regs
[FCC_FIRST
] = call_used_regs
[FCC_FIRST
] = 1;
821 fixed_regs
[ICR_FIRST
] = call_used_regs
[ICR_FIRST
] = 1;
822 fixed_regs
[FCR_FIRST
] = call_used_regs
[FCR_FIRST
] = 1;
826 fixed_regs
[GPR_FIRST
+ 16] = fixed_regs
[GPR_FIRST
+ 17] =
827 call_used_regs
[GPR_FIRST
+ 16] = call_used_regs
[GPR_FIRST
+ 17] = 0;
830 /* If -fpic, SDA_BASE_REG is the PIC register. */
831 if (g_switch_value
== 0 && !flag_pic
)
832 fixed_regs
[SDA_BASE_REG
] = call_used_regs
[SDA_BASE_REG
] = 0;
835 fixed_regs
[PIC_REGNO
] = call_used_regs
[PIC_REGNO
] = 0;
841 * Compute the stack frame layout
844 * +---------------+-----------------------+-----------------------+
845 * |Register |type |caller-save/callee-save|
846 * +---------------+-----------------------+-----------------------+
847 * |GR0 |Zero register | - |
848 * |GR1 |Stack pointer(SP) | - |
849 * |GR2 |Frame pointer(FP) | - |
850 * |GR3 |Hidden parameter | caller save |
851 * |GR4-GR7 | - | caller save |
852 * |GR8-GR13 |Argument register | caller save |
853 * |GR14-GR15 | - | caller save |
854 * |GR16-GR31 | - | callee save |
855 * |GR32-GR47 | - | caller save |
856 * |GR48-GR63 | - | callee save |
857 * |FR0-FR15 | - | caller save |
858 * |FR16-FR31 | - | callee save |
859 * |FR32-FR47 | - | caller save |
860 * |FR48-FR63 | - | callee save |
861 * +---------------+-----------------------+-----------------------+
865 * SP-> |-----------------------------------|
867 * |-----------------------------------|
868 * | Register save area |
869 * |-----------------------------------|
870 * | Local variable save area |
871 * FP-> |-----------------------------------|
873 * |-----------------------------------|
874 * | Hidden parameter save area |
875 * |-----------------------------------|
876 * | Return address(LR) storage area |
877 * |-----------------------------------|
878 * | Padding for alignment |
879 * |-----------------------------------|
880 * | Register argument area |
881 * OLD SP-> |-----------------------------------|
883 * |-----------------------------------|
886 * Argument area/Parameter area:
888 * When a function is called, this area is used for argument transfer. When
889 * the argument is set up by the caller function, this area is referred to as
890 * the argument area. When the argument is referenced by the callee function,
891 * this area is referred to as the parameter area. The area is allocated when
892 * all arguments cannot be placed on the argument register at the time of
895 * Register save area:
897 * This is a register save area that must be guaranteed for the caller
898 * function. This area is not secured when the register save operation is not
901 * Local variable save area:
903 * This is the area for local variables and temporary variables.
907 * This area stores the FP value of the caller function.
909 * Hidden parameter save area:
911 * This area stores the start address of the return value storage
912 * area for a struct/union return function.
913 * When a struct/union is used as the return value, the caller
914 * function stores the return value storage area start address in
915 * register GR3 and passes it to the caller function.
916 * The callee function interprets the address stored in the GR3
917 * as the return value storage area start address.
918 * When register GR3 needs to be saved into memory, the callee
919 * function saves it in the hidden parameter save area. This
920 * area is not secured when the save operation is not needed.
922 * Return address(LR) storage area:
924 * This area saves the LR. The LR stores the address of a return to the caller
925 * function for the purpose of function calling.
927 * Argument register area:
929 * This area saves the argument register. This area is not secured when the
930 * save operation is not needed.
934 * Arguments, the count of which equals the count of argument registers (6
935 * words), are positioned in registers GR8 to GR13 and delivered to the callee
936 * function. When a struct/union return function is called, the return value
937 * area address is stored in register GR3. Arguments not placed in the
938 * argument registers will be stored in the stack argument area for transfer
939 * purposes. When an 8-byte type argument is to be delivered using registers,
940 * it is divided into two and placed in two registers for transfer. When
941 * argument registers must be saved to memory, the callee function secures an
942 * argument register save area in the stack. In this case, a continuous
943 * argument register save area must be established in the parameter area. The
944 * argument register save area must be allocated as needed to cover the size of
945 * the argument register to be saved. If the function has a variable count of
946 * arguments, it saves all argument registers in the argument register save
949 * Argument Extension Format:
951 * When an argument is to be stored in the stack, its type is converted to an
952 * extended type in accordance with the individual argument type. The argument
953 * is freed by the caller function after the return from the callee function is
956 * +-----------------------+---------------+------------------------+
957 * | Argument Type |Extended Type |Stack Storage Size(byte)|
958 * +-----------------------+---------------+------------------------+
960 * |signed char |int | 4 |
961 * |unsigned char |int | 4 |
962 * |[signed] short int |int | 4 |
963 * |unsigned short int |int | 4 |
964 * |[signed] int |No extension | 4 |
965 * |unsigned int |No extension | 4 |
966 * |[signed] long int |No extension | 4 |
967 * |unsigned long int |No extension | 4 |
968 * |[signed] long long int |No extension | 8 |
969 * |unsigned long long int |No extension | 8 |
970 * |float |double | 8 |
971 * |double |No extension | 8 |
972 * |long double |No extension | 8 |
973 * |pointer |No extension | 4 |
974 * |struct/union |- | 4 (*1) |
975 * +-----------------------+---------------+------------------------+
977 * When a struct/union is to be delivered as an argument, the caller copies it
978 * to the local variable area and delivers the address of that area.
982 * +-------------------------------+----------------------+
983 * |Return Value Type |Return Value Interface|
984 * +-------------------------------+----------------------+
986 * |[signed|unsigned] char |GR8 |
987 * |[signed|unsigned] short int |GR8 |
988 * |[signed|unsigned] int |GR8 |
989 * |[signed|unsigned] long int |GR8 |
991 * |[signed|unsigned] long long int|GR8 & GR9 |
993 * |double |GR8 & GR9 |
994 * |long double |GR8 & GR9 |
995 * |struct/union |(*1) |
996 * +-------------------------------+----------------------+
998 * When a struct/union is used as the return value, the caller function stores
999 * the start address of the return value storage area into GR3 and then passes
1000 * it to the callee function. The callee function interprets GR3 as the start
1001 * address of the return value storage area. When this address needs to be
1002 * saved in memory, the callee function secures the hidden parameter save area
1003 * and saves the address in that area.
1007 frv_stack_info (void)
1009 static frv_stack_t info
, zero_info
;
1010 frv_stack_t
*info_ptr
= &info
;
1011 tree fndecl
= current_function_decl
;
1019 /* If we've already calculated the values and reload is complete,
1021 if (frv_stack_cache
)
1022 return frv_stack_cache
;
1024 /* Zero all fields. */
1027 /* Set up the register range information. */
1028 info_ptr
->regs
[STACK_REGS_GPR
].name
= "gpr";
1029 info_ptr
->regs
[STACK_REGS_GPR
].first
= LAST_ARG_REGNUM
+ 1;
1030 info_ptr
->regs
[STACK_REGS_GPR
].last
= GPR_LAST
;
1031 info_ptr
->regs
[STACK_REGS_GPR
].dword_p
= TRUE
;
1033 info_ptr
->regs
[STACK_REGS_FPR
].name
= "fpr";
1034 info_ptr
->regs
[STACK_REGS_FPR
].first
= FPR_FIRST
;
1035 info_ptr
->regs
[STACK_REGS_FPR
].last
= FPR_LAST
;
1036 info_ptr
->regs
[STACK_REGS_FPR
].dword_p
= TRUE
;
1038 info_ptr
->regs
[STACK_REGS_LR
].name
= "lr";
1039 info_ptr
->regs
[STACK_REGS_LR
].first
= LR_REGNO
;
1040 info_ptr
->regs
[STACK_REGS_LR
].last
= LR_REGNO
;
1041 info_ptr
->regs
[STACK_REGS_LR
].special_p
= 1;
1043 info_ptr
->regs
[STACK_REGS_CC
].name
= "cc";
1044 info_ptr
->regs
[STACK_REGS_CC
].first
= CC_FIRST
;
1045 info_ptr
->regs
[STACK_REGS_CC
].last
= CC_LAST
;
1046 info_ptr
->regs
[STACK_REGS_CC
].field_p
= TRUE
;
1048 info_ptr
->regs
[STACK_REGS_LCR
].name
= "lcr";
1049 info_ptr
->regs
[STACK_REGS_LCR
].first
= LCR_REGNO
;
1050 info_ptr
->regs
[STACK_REGS_LCR
].last
= LCR_REGNO
;
1052 info_ptr
->regs
[STACK_REGS_STDARG
].name
= "stdarg";
1053 info_ptr
->regs
[STACK_REGS_STDARG
].first
= FIRST_ARG_REGNUM
;
1054 info_ptr
->regs
[STACK_REGS_STDARG
].last
= LAST_ARG_REGNUM
;
1055 info_ptr
->regs
[STACK_REGS_STDARG
].dword_p
= 1;
1056 info_ptr
->regs
[STACK_REGS_STDARG
].special_p
= 1;
1058 info_ptr
->regs
[STACK_REGS_STRUCT
].name
= "struct";
1059 info_ptr
->regs
[STACK_REGS_STRUCT
].first
= FRV_STRUCT_VALUE_REGNUM
;
1060 info_ptr
->regs
[STACK_REGS_STRUCT
].last
= FRV_STRUCT_VALUE_REGNUM
;
1061 info_ptr
->regs
[STACK_REGS_STRUCT
].special_p
= 1;
1063 info_ptr
->regs
[STACK_REGS_FP
].name
= "fp";
1064 info_ptr
->regs
[STACK_REGS_FP
].first
= FRAME_POINTER_REGNUM
;
1065 info_ptr
->regs
[STACK_REGS_FP
].last
= FRAME_POINTER_REGNUM
;
1066 info_ptr
->regs
[STACK_REGS_FP
].special_p
= 1;
1068 /* Determine if this is a stdarg function. If so, allocate space to store
1075 /* Find the last argument, and see if it is __builtin_va_alist. */
1076 for (cur_arg
= DECL_ARGUMENTS (fndecl
); cur_arg
!= (tree
)0; cur_arg
= next_arg
)
1078 next_arg
= DECL_CHAIN (cur_arg
);
1079 if (next_arg
== (tree
)0)
1081 if (DECL_NAME (cur_arg
)
1082 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)), "__builtin_va_alist"))
1090 /* Iterate over all of the register ranges. */
1091 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1093 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1094 int first
= reg_ptr
->first
;
1095 int last
= reg_ptr
->last
;
1097 int size_2words
= 0;
1100 /* Calculate which registers need to be saved & save area size. */
1104 for (regno
= first
; regno
<= last
; regno
++)
1106 if ((df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
1107 || (crtl
->calls_eh_return
1108 && (regno
>= FIRST_EH_REGNUM
&& regno
<= LAST_EH_REGNUM
))
1109 || (!TARGET_FDPIC
&& flag_pic
1110 && crtl
->uses_pic_offset_table
&& regno
== PIC_REGNO
))
1112 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1113 size_1word
+= UNITS_PER_WORD
;
1118 /* Calculate whether we need to create a frame after everything else
1119 has been processed. */
1124 if (df_regs_ever_live_p (LR_REGNO
)
1126 /* This is set for __builtin_return_address, etc. */
1127 || cfun
->machine
->frame_needed
1128 || (TARGET_LINKED_FP
&& frame_pointer_needed
)
1129 || (!TARGET_FDPIC
&& flag_pic
1130 && crtl
->uses_pic_offset_table
))
1132 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1133 size_1word
+= UNITS_PER_WORD
;
1137 case STACK_REGS_STDARG
:
1140 /* If this is a stdarg function with a non varardic
1141 argument split between registers and the stack,
1142 adjust the saved registers downward. */
1143 last
-= (ADDR_ALIGN (crtl
->args
.pretend_args_size
, UNITS_PER_WORD
)
1146 for (regno
= first
; regno
<= last
; regno
++)
1148 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1149 size_1word
+= UNITS_PER_WORD
;
1152 info_ptr
->stdarg_size
= size_1word
;
1156 case STACK_REGS_STRUCT
:
1157 if (cfun
->returns_struct
)
1159 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1160 size_1word
+= UNITS_PER_WORD
;
1168 /* If this is a field, it only takes one word. */
1169 if (reg_ptr
->field_p
)
1170 size_1word
= UNITS_PER_WORD
;
1172 /* Determine which register pairs can be saved together. */
1173 else if (reg_ptr
->dword_p
&& TARGET_DWORD
)
1175 for (regno
= first
; regno
< last
; regno
+= 2)
1177 if (info_ptr
->save_p
[regno
] && info_ptr
->save_p
[regno
+1])
1179 size_2words
+= 2 * UNITS_PER_WORD
;
1180 size_1word
-= 2 * UNITS_PER_WORD
;
1181 info_ptr
->save_p
[regno
] = REG_SAVE_2WORDS
;
1182 info_ptr
->save_p
[regno
+1] = REG_SAVE_NO_SAVE
;
1187 reg_ptr
->size_1word
= size_1word
;
1188 reg_ptr
->size_2words
= size_2words
;
1190 if (! reg_ptr
->special_p
)
1192 info_ptr
->regs_size_1word
+= size_1word
;
1193 info_ptr
->regs_size_2words
+= size_2words
;
1198 /* Set up the sizes of each each field in the frame body, making the sizes
1199 of each be divisible by the size of a dword if dword operations might
1200 be used, or the size of a word otherwise. */
1201 alignment
= (TARGET_DWORD
? 2 * UNITS_PER_WORD
: UNITS_PER_WORD
);
1203 info_ptr
->parameter_size
= ADDR_ALIGN (crtl
->outgoing_args_size
, alignment
);
1204 info_ptr
->regs_size
= ADDR_ALIGN (info_ptr
->regs_size_2words
1205 + info_ptr
->regs_size_1word
,
1207 info_ptr
->vars_size
= ADDR_ALIGN (get_frame_size (), alignment
);
1209 info_ptr
->pretend_size
= crtl
->args
.pretend_args_size
;
1211 /* Work out the size of the frame, excluding the header. Both the frame
1212 body and register parameter area will be dword-aligned. */
1213 info_ptr
->total_size
1214 = (ADDR_ALIGN (info_ptr
->parameter_size
1215 + info_ptr
->regs_size
1216 + info_ptr
->vars_size
,
1218 + ADDR_ALIGN (info_ptr
->pretend_size
1219 + info_ptr
->stdarg_size
,
1220 2 * UNITS_PER_WORD
));
1222 /* See if we need to create a frame at all, if so add header area. */
1223 if (info_ptr
->total_size
> 0
1224 || frame_pointer_needed
1225 || info_ptr
->regs
[STACK_REGS_LR
].size_1word
> 0
1226 || info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
> 0)
1228 offset
= info_ptr
->parameter_size
;
1229 info_ptr
->header_size
= 4 * UNITS_PER_WORD
;
1230 info_ptr
->total_size
+= 4 * UNITS_PER_WORD
;
1232 /* Calculate the offsets to save normal register pairs. */
1233 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1235 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1236 if (! reg_ptr
->special_p
)
1238 int first
= reg_ptr
->first
;
1239 int last
= reg_ptr
->last
;
1242 for (regno
= first
; regno
<= last
; regno
++)
1243 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
1244 && regno
!= FRAME_POINTER_REGNUM
1245 && (regno
< FIRST_ARG_REGNUM
1246 || regno
> LAST_ARG_REGNUM
))
1248 info_ptr
->reg_offset
[regno
] = offset
;
1249 offset
+= 2 * UNITS_PER_WORD
;
1254 /* Calculate the offsets to save normal single registers. */
1255 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1257 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1258 if (! reg_ptr
->special_p
)
1260 int first
= reg_ptr
->first
;
1261 int last
= reg_ptr
->last
;
1264 for (regno
= first
; regno
<= last
; regno
++)
1265 if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
1266 && regno
!= FRAME_POINTER_REGNUM
1267 && (regno
< FIRST_ARG_REGNUM
1268 || regno
> LAST_ARG_REGNUM
))
1270 info_ptr
->reg_offset
[regno
] = offset
;
1271 offset
+= UNITS_PER_WORD
;
1276 /* Calculate the offset to save the local variables at. */
1277 offset
= ADDR_ALIGN (offset
, alignment
);
1278 if (info_ptr
->vars_size
)
1280 info_ptr
->vars_offset
= offset
;
1281 offset
+= info_ptr
->vars_size
;
1284 /* Align header to a dword-boundary. */
1285 offset
= ADDR_ALIGN (offset
, 2 * UNITS_PER_WORD
);
1287 /* Calculate the offsets in the fixed frame. */
1288 info_ptr
->save_p
[FRAME_POINTER_REGNUM
] = REG_SAVE_1WORD
;
1289 info_ptr
->reg_offset
[FRAME_POINTER_REGNUM
] = offset
;
1290 info_ptr
->regs
[STACK_REGS_FP
].size_1word
= UNITS_PER_WORD
;
1292 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1293 info_ptr
->reg_offset
[LR_REGNO
] = offset
+ 2*UNITS_PER_WORD
;
1294 info_ptr
->regs
[STACK_REGS_LR
].size_1word
= UNITS_PER_WORD
;
1296 if (cfun
->returns_struct
)
1298 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1299 info_ptr
->reg_offset
[FRV_STRUCT_VALUE_REGNUM
] = offset
+ UNITS_PER_WORD
;
1300 info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
= UNITS_PER_WORD
;
1303 /* Calculate the offsets to store the arguments passed in registers
1304 for stdarg functions. The register pairs are first and the single
1305 register if any is last. The register save area starts on a
1307 if (info_ptr
->stdarg_size
)
1309 int first
= info_ptr
->regs
[STACK_REGS_STDARG
].first
;
1310 int last
= info_ptr
->regs
[STACK_REGS_STDARG
].last
;
1313 /* Skip the header. */
1314 offset
+= 4 * UNITS_PER_WORD
;
1315 for (regno
= first
; regno
<= last
; regno
++)
1317 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
)
1319 info_ptr
->reg_offset
[regno
] = offset
;
1320 offset
+= 2 * UNITS_PER_WORD
;
1322 else if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
)
1324 info_ptr
->reg_offset
[regno
] = offset
;
1325 offset
+= UNITS_PER_WORD
;
1331 if (reload_completed
)
1332 frv_stack_cache
= info_ptr
;
1338 /* Print the information about the frv stack offsets, etc. when debugging. */
1341 frv_debug_stack (frv_stack_t
*info
)
1346 info
= frv_stack_info ();
1348 fprintf (stderr
, "\nStack information for function %s:\n",
1349 ((current_function_decl
&& DECL_NAME (current_function_decl
))
1350 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
1353 fprintf (stderr
, "\ttotal_size\t= %6d\n", info
->total_size
);
1354 fprintf (stderr
, "\tvars_size\t= %6d\n", info
->vars_size
);
1355 fprintf (stderr
, "\tparam_size\t= %6d\n", info
->parameter_size
);
1356 fprintf (stderr
, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1357 info
->regs_size
, info
->regs_size_1word
, info
->regs_size_2words
);
1359 fprintf (stderr
, "\theader_size\t= %6d\n", info
->header_size
);
1360 fprintf (stderr
, "\tpretend_size\t= %6d\n", info
->pretend_size
);
1361 fprintf (stderr
, "\tvars_offset\t= %6d\n", info
->vars_offset
);
1362 fprintf (stderr
, "\tregs_offset\t= %6d\n", info
->regs_offset
);
1364 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1366 frv_stack_regs_t
*regs
= &(info
->regs
[range
]);
1367 if ((regs
->size_1word
+ regs
->size_2words
) > 0)
1369 int first
= regs
->first
;
1370 int last
= regs
->last
;
1373 fprintf (stderr
, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1374 regs
->name
, regs
->size_1word
+ regs
->size_2words
,
1375 regs
->size_1word
, regs
->size_2words
);
1377 for (regno
= first
; regno
<= last
; regno
++)
1379 if (info
->save_p
[regno
] == REG_SAVE_1WORD
)
1380 fprintf (stderr
, " %s (%d)", reg_names
[regno
],
1381 info
->reg_offset
[regno
]);
1383 else if (info
->save_p
[regno
] == REG_SAVE_2WORDS
)
1384 fprintf (stderr
, " %s-%s (%d)", reg_names
[regno
],
1385 reg_names
[regno
+1], info
->reg_offset
[regno
]);
1388 fputc ('\n', stderr
);
1398 /* Used during final to control the packing of insns. The value is
1399 1 if the current instruction should be packed with the next one,
1400 0 if it shouldn't or -1 if packing is disabled altogether. */
1402 static int frv_insn_packing_flag
;
1404 /* True if the current function contains a far jump. */
1407 frv_function_contains_far_jump (void)
1409 rtx insn
= get_insns ();
1412 && get_attr_far_jump (insn
) == FAR_JUMP_YES
))
1413 insn
= NEXT_INSN (insn
);
1414 return (insn
!= NULL
);
1417 /* For the FRV, this function makes sure that a function with far jumps
1418 will return correctly. It also does the VLIW packing. */
1421 frv_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1423 rtx insn
, next
, last_call
;
1425 /* If no frame was created, check whether the function uses a call
1426 instruction to implement a far jump. If so, save the link in gr3 and
1427 replace all returns to LR with returns to GR3. GR3 is used because it
1428 is call-clobbered, because is not available to the register allocator,
1429 and because all functions that take a hidden argument pointer will have
1431 if (frv_stack_info ()->total_size
== 0 && frv_function_contains_far_jump ())
1435 /* Just to check that the above comment is true. */
1436 gcc_assert (!df_regs_ever_live_p (GPR_FIRST
+ 3));
1438 /* Generate the instruction that saves the link register. */
1439 fprintf (file
, "\tmovsg lr,gr3\n");
1441 /* Replace the LR with GR3 in *return_internal patterns. The insn
1442 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1443 simply emit a different assembly directive because bralr and jmpl
1444 execute in different units. */
1445 for (insn
= get_insns(); insn
!= NULL
; insn
= NEXT_INSN (insn
))
1448 rtx pattern
= PATTERN (insn
);
1449 if (GET_CODE (pattern
) == PARALLEL
1450 && XVECLEN (pattern
, 0) >= 2
1451 && GET_CODE (XVECEXP (pattern
, 0, 0)) == RETURN
1452 && GET_CODE (XVECEXP (pattern
, 0, 1)) == USE
)
1454 rtx address
= XEXP (XVECEXP (pattern
, 0, 1), 0);
1455 if (GET_CODE (address
) == REG
&& REGNO (address
) == LR_REGNO
)
1456 SET_REGNO (address
, GPR_FIRST
+ 3);
1463 /* Allow the garbage collector to free the nops created by frv_reorg. */
1464 memset (frv_nops
, 0, sizeof (frv_nops
));
1466 /* Locate CALL_ARG_LOCATION notes that have been misplaced
1467 and move them back to where they should be located. */
1468 last_call
= NULL_RTX
;
1469 for (insn
= get_insns (); insn
; insn
= next
)
1471 next
= NEXT_INSN (insn
);
1473 || (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
1474 && CALL_P (XVECEXP (PATTERN (insn
), 0, 0))))
1477 if (!NOTE_P (insn
) || NOTE_KIND (insn
) != NOTE_INSN_CALL_ARG_LOCATION
)
1480 if (NEXT_INSN (last_call
) == insn
)
1483 NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
1484 PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
1485 PREV_INSN (insn
) = last_call
;
1486 NEXT_INSN (insn
) = NEXT_INSN (last_call
);
1487 PREV_INSN (NEXT_INSN (insn
)) = insn
;
1488 NEXT_INSN (PREV_INSN (insn
)) = insn
;
1494 /* Return the next available temporary register in a given class. */
1497 frv_alloc_temp_reg (
1498 frv_tmp_reg_t
*info
, /* which registers are available */
1499 enum reg_class rclass
, /* register class desired */
1500 enum machine_mode mode
, /* mode to allocate register with */
1501 int mark_as_used
, /* register not available after allocation */
1502 int no_abort
) /* return NULL instead of aborting */
1504 int regno
= info
->next_reg
[ (int)rclass
];
1505 int orig_regno
= regno
;
1506 HARD_REG_SET
*reg_in_class
= ®_class_contents
[ (int)rclass
];
1511 if (TEST_HARD_REG_BIT (*reg_in_class
, regno
)
1512 && TEST_HARD_REG_BIT (info
->regs
, regno
))
1515 if (++regno
>= FIRST_PSEUDO_REGISTER
)
1517 if (regno
== orig_regno
)
1519 gcc_assert (no_abort
);
1524 nr
= HARD_REGNO_NREGS (regno
, mode
);
1525 info
->next_reg
[ (int)rclass
] = regno
+ nr
;
1528 for (i
= 0; i
< nr
; i
++)
1529 CLEAR_HARD_REG_BIT (info
->regs
, regno
+i
);
1531 return gen_rtx_REG (mode
, regno
);
1535 /* Return an rtx with the value OFFSET, which will either be a register or a
1536 signed 12-bit integer. It can be used as the second operand in an "add"
1537 instruction, or as the index in a load or store.
1539 The function returns a constant rtx if OFFSET is small enough, otherwise
1540 it loads the constant into register OFFSET_REGNO and returns that. */
1542 frv_frame_offset_rtx (int offset
)
1544 rtx offset_rtx
= GEN_INT (offset
);
1545 if (IN_RANGE (offset
, -2048, 2047))
1549 rtx reg_rtx
= gen_rtx_REG (SImode
, OFFSET_REGNO
);
1550 if (IN_RANGE (offset
, -32768, 32767))
1551 emit_insn (gen_movsi (reg_rtx
, offset_rtx
));
1554 emit_insn (gen_movsi_high (reg_rtx
, offset_rtx
));
1555 emit_insn (gen_movsi_lo_sum (reg_rtx
, offset_rtx
));
1561 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1562 prologue and epilogue uses such expressions to access the stack. */
1564 frv_frame_mem (enum machine_mode mode
, rtx base
, int offset
)
1566 return gen_rtx_MEM (mode
, gen_rtx_PLUS (Pmode
,
1568 frv_frame_offset_rtx (offset
)));
1571 /* Generate a frame-related expression:
1573 (set REG (mem (plus (sp) (const_int OFFSET)))).
1575 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1576 instructions. Marking the expressions as frame-related is superfluous if
1577 the note contains just a single set. But if the note contains a PARALLEL
1578 or SEQUENCE that has several sets, each set must be individually marked
1579 as frame-related. */
1581 frv_dwarf_store (rtx reg
, int offset
)
1583 rtx set
= gen_rtx_SET (VOIDmode
,
1584 gen_rtx_MEM (GET_MODE (reg
),
1585 plus_constant (Pmode
, stack_pointer_rtx
,
1588 RTX_FRAME_RELATED_P (set
) = 1;
1592 /* Emit a frame-related instruction whose pattern is PATTERN. The
1593 instruction is the last in a sequence that cumulatively performs the
1594 operation described by DWARF_PATTERN. The instruction is marked as
1595 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1598 frv_frame_insn (rtx pattern
, rtx dwarf_pattern
)
1600 rtx insn
= emit_insn (pattern
);
1601 RTX_FRAME_RELATED_P (insn
) = 1;
1602 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
1607 /* Emit instructions that transfer REG to or from the memory location (sp +
1608 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1609 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1610 function to store registers and only the epilogue uses it to load them.
1612 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1613 The generated instruction will use BASE as its base register. BASE may
1614 simply be the stack pointer, but if several accesses are being made to a
1615 region far away from the stack pointer, it may be more efficient to set
1616 up a temporary instead.
1618 Store instructions will be frame-related and will be annotated with the
1619 overall effect of the store. Load instructions will be followed by a
1620 (use) to prevent later optimizations from zapping them.
1622 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1623 as a temporary in such cases. */
1625 frv_frame_access (frv_frame_accessor_t
*accessor
, rtx reg
, int stack_offset
)
1627 enum machine_mode mode
= GET_MODE (reg
);
1628 rtx mem
= frv_frame_mem (mode
,
1630 stack_offset
- accessor
->base_offset
);
1632 if (accessor
->op
== FRV_LOAD
)
1634 if (SPR_P (REGNO (reg
)))
1636 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1637 emit_insn (gen_rtx_SET (VOIDmode
, temp
, mem
));
1638 emit_insn (gen_rtx_SET (VOIDmode
, reg
, temp
));
1642 /* We cannot use reg+reg addressing for DImode access. */
1644 && GET_CODE (XEXP (mem
, 0)) == PLUS
1645 && GET_CODE (XEXP (XEXP (mem
, 0), 0)) == REG
1646 && GET_CODE (XEXP (XEXP (mem
, 0), 1)) == REG
)
1648 rtx temp
= gen_rtx_REG (SImode
, TEMP_REGNO
);
1650 emit_move_insn (temp
,
1651 gen_rtx_PLUS (SImode
, XEXP (XEXP (mem
, 0), 0),
1652 XEXP (XEXP (mem
, 0), 1)));
1653 mem
= gen_rtx_MEM (DImode
, temp
);
1655 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
1661 if (SPR_P (REGNO (reg
)))
1663 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1664 emit_insn (gen_rtx_SET (VOIDmode
, temp
, reg
));
1665 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, temp
),
1666 frv_dwarf_store (reg
, stack_offset
));
1668 else if (mode
== DImode
)
1670 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1671 with a separate save for each register. */
1672 rtx reg1
= gen_rtx_REG (SImode
, REGNO (reg
));
1673 rtx reg2
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
1674 rtx set1
= frv_dwarf_store (reg1
, stack_offset
);
1675 rtx set2
= frv_dwarf_store (reg2
, stack_offset
+ 4);
1677 /* Also we cannot use reg+reg addressing. */
1678 if (GET_CODE (XEXP (mem
, 0)) == PLUS
1679 && GET_CODE (XEXP (XEXP (mem
, 0), 0)) == REG
1680 && GET_CODE (XEXP (XEXP (mem
, 0), 1)) == REG
)
1682 rtx temp
= gen_rtx_REG (SImode
, TEMP_REGNO
);
1683 emit_move_insn (temp
,
1684 gen_rtx_PLUS (SImode
, XEXP (XEXP (mem
, 0), 0),
1685 XEXP (XEXP (mem
, 0), 1)));
1686 mem
= gen_rtx_MEM (DImode
, temp
);
1689 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1690 gen_rtx_PARALLEL (VOIDmode
,
1691 gen_rtvec (2, set1
, set2
)));
1694 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1695 frv_dwarf_store (reg
, stack_offset
));
1699 /* A function that uses frv_frame_access to transfer a group of registers to
1700 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1701 is the stack information generated by frv_stack_info, and REG_SET is the
1702 number of the register set to transfer. */
1704 frv_frame_access_multi (frv_frame_accessor_t
*accessor
,
1708 frv_stack_regs_t
*regs_info
;
1711 regs_info
= &info
->regs
[reg_set
];
1712 for (regno
= regs_info
->first
; regno
<= regs_info
->last
; regno
++)
1713 if (info
->save_p
[regno
])
1714 frv_frame_access (accessor
,
1715 info
->save_p
[regno
] == REG_SAVE_2WORDS
1716 ? gen_rtx_REG (DImode
, regno
)
1717 : gen_rtx_REG (SImode
, regno
),
1718 info
->reg_offset
[regno
]);
1721 /* Save or restore callee-saved registers that are kept outside the frame
1722 header. The function saves the registers if OP is FRV_STORE and restores
1723 them if OP is FRV_LOAD. INFO is the stack information generated by
1726 frv_frame_access_standard_regs (enum frv_stack_op op
, frv_stack_t
*info
)
1728 frv_frame_accessor_t accessor
;
1731 accessor
.base
= stack_pointer_rtx
;
1732 accessor
.base_offset
= 0;
1733 frv_frame_access_multi (&accessor
, info
, STACK_REGS_GPR
);
1734 frv_frame_access_multi (&accessor
, info
, STACK_REGS_FPR
);
1735 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LCR
);
1739 /* Called after register allocation to add any instructions needed for the
1740 prologue. Using a prologue insn is favored compared to putting all of the
1741 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1742 it allows the scheduler to intermix instructions with the saves of
1743 the caller saved registers. In some cases, it might be necessary
1744 to emit a barrier instruction as the last insn to prevent such
1747 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1748 so that the debug info generation code can handle them properly. */
1750 frv_expand_prologue (void)
1752 frv_stack_t
*info
= frv_stack_info ();
1753 rtx sp
= stack_pointer_rtx
;
1754 rtx fp
= frame_pointer_rtx
;
1755 frv_frame_accessor_t accessor
;
1757 if (TARGET_DEBUG_STACK
)
1758 frv_debug_stack (info
);
1760 if (flag_stack_usage_info
)
1761 current_function_static_stack_size
= info
->total_size
;
1763 if (info
->total_size
== 0)
1766 /* We're interested in three areas of the frame here:
1768 A: the register save area
1770 C: the header after B
1772 If the frame pointer isn't used, we'll have to set up A, B and C
1773 using the stack pointer. If the frame pointer is used, we'll access
1777 B: set up using sp or a temporary (see below)
1780 We set up B using the stack pointer if the frame is small enough.
1781 Otherwise, it's more efficient to copy the old stack pointer into a
1782 temporary and use that.
1784 Note that it's important to make sure the prologue and epilogue use the
1785 same registers to access A and C, since doing otherwise will confuse
1786 the aliasing code. */
1788 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1789 isn't used, the same method will serve for C. */
1790 accessor
.op
= FRV_STORE
;
1791 if (frame_pointer_needed
&& info
->total_size
> 2048)
1793 accessor
.base
= gen_rtx_REG (Pmode
, OLD_SP_REGNO
);
1794 accessor
.base_offset
= info
->total_size
;
1795 emit_insn (gen_movsi (accessor
.base
, sp
));
1799 accessor
.base
= stack_pointer_rtx
;
1800 accessor
.base_offset
= 0;
1803 /* Allocate the stack space. */
1805 rtx asm_offset
= frv_frame_offset_rtx (-info
->total_size
);
1806 rtx dwarf_offset
= GEN_INT (-info
->total_size
);
1808 frv_frame_insn (gen_stack_adjust (sp
, sp
, asm_offset
),
1811 gen_rtx_PLUS (Pmode
, sp
, dwarf_offset
)));
1814 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1815 and point the new one to that location. */
1816 if (frame_pointer_needed
)
1818 int fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1820 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1821 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1823 rtx asm_src
= plus_constant (Pmode
, accessor
.base
,
1824 fp_offset
- accessor
.base_offset
);
1825 rtx dwarf_src
= plus_constant (Pmode
, sp
, fp_offset
);
1827 /* Store the old frame pointer at (sp + FP_OFFSET). */
1828 frv_frame_access (&accessor
, fp
, fp_offset
);
1830 /* Set up the new frame pointer. */
1831 frv_frame_insn (gen_rtx_SET (VOIDmode
, fp
, asm_src
),
1832 gen_rtx_SET (VOIDmode
, fp
, dwarf_src
));
1834 /* Access region C from the frame pointer. */
1836 accessor
.base_offset
= fp_offset
;
1839 /* Set up region C. */
1840 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STRUCT
);
1841 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LR
);
1842 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STDARG
);
1844 /* Set up region A. */
1845 frv_frame_access_standard_regs (FRV_STORE
, info
);
1847 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1848 scheduler from moving loads before the stores saving the registers. */
1849 if (info
->stdarg_size
> 0)
1850 emit_insn (gen_blockage ());
1852 /* Set up pic register/small data register for this function. */
1853 if (!TARGET_FDPIC
&& flag_pic
&& crtl
->uses_pic_offset_table
)
1854 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode
, PIC_REGNO
),
1855 gen_rtx_REG (Pmode
, LR_REGNO
),
1856 gen_rtx_REG (SImode
, OFFSET_REGNO
)));
1860 /* Under frv, all of the work is done via frv_expand_epilogue, but
1861 this function provides a convenient place to do cleanup. */
1864 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
1865 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1867 frv_stack_cache
= (frv_stack_t
*)0;
1869 /* Zap last used registers for conditional execution. */
1870 memset (&frv_ifcvt
.tmp_reg
, 0, sizeof (frv_ifcvt
.tmp_reg
));
1872 /* Release the bitmap of created insns. */
1873 BITMAP_FREE (frv_ifcvt
.scratch_insns_bitmap
);
1877 /* Called after register allocation to add any instructions needed for the
1878 epilogue. Using an epilogue insn is favored compared to putting all of the
1879 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1880 it allows the scheduler to intermix instructions with the saves of
1881 the caller saved registers. In some cases, it might be necessary
1882 to emit a barrier instruction as the last insn to prevent such
1886 frv_expand_epilogue (bool emit_return
)
1888 frv_stack_t
*info
= frv_stack_info ();
1889 rtx fp
= frame_pointer_rtx
;
1890 rtx sp
= stack_pointer_rtx
;
1894 fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1896 /* Restore the stack pointer to its original value if alloca or the like
1898 if (! crtl
->sp_is_unchanging
)
1899 emit_insn (gen_addsi3 (sp
, fp
, frv_frame_offset_rtx (-fp_offset
)));
1901 /* Restore the callee-saved registers that were used in this function. */
1902 frv_frame_access_standard_regs (FRV_LOAD
, info
);
1904 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1905 no return instruction should be emitted. */
1906 if (info
->save_p
[LR_REGNO
])
1911 /* Use the same method to access the link register's slot as we did in
1912 the prologue. In other words, use the frame pointer if available,
1913 otherwise use the stack pointer.
1915 LR_OFFSET is the offset of the link register's slot from the start
1916 of the frame and MEM is a memory rtx for it. */
1917 lr_offset
= info
->reg_offset
[LR_REGNO
];
1918 if (frame_pointer_needed
)
1919 mem
= frv_frame_mem (Pmode
, fp
, lr_offset
- fp_offset
);
1921 mem
= frv_frame_mem (Pmode
, sp
, lr_offset
);
1923 /* Load the old link register into a GPR. */
1924 return_addr
= gen_rtx_REG (Pmode
, TEMP_REGNO
);
1925 emit_insn (gen_rtx_SET (VOIDmode
, return_addr
, mem
));
1928 return_addr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1930 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1931 the load is preserved. */
1932 if (frame_pointer_needed
)
1934 emit_insn (gen_rtx_SET (VOIDmode
, fp
, gen_rtx_MEM (Pmode
, fp
)));
1938 /* Deallocate the stack frame. */
1939 if (info
->total_size
!= 0)
1941 rtx offset
= frv_frame_offset_rtx (info
->total_size
);
1942 emit_insn (gen_stack_adjust (sp
, sp
, offset
));
1945 /* If this function uses eh_return, add the final stack adjustment now. */
1946 if (crtl
->calls_eh_return
)
1947 emit_insn (gen_stack_adjust (sp
, sp
, EH_RETURN_STACKADJ_RTX
));
1950 emit_jump_insn (gen_epilogue_return (return_addr
));
1953 rtx lr
= return_addr
;
1955 if (REGNO (return_addr
) != LR_REGNO
)
1957 lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1958 emit_move_insn (lr
, return_addr
);
1966 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1969 frv_asm_output_mi_thunk (FILE *file
,
1970 tree thunk_fndecl ATTRIBUTE_UNUSED
,
1971 HOST_WIDE_INT delta
,
1972 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
1975 const char *name_func
= XSTR (XEXP (DECL_RTL (function
), 0), 0);
1976 const char *name_arg0
= reg_names
[FIRST_ARG_REGNUM
];
1977 const char *name_jmp
= reg_names
[JUMP_REGNO
];
1978 const char *parallel
= (frv_issue_rate () > 1 ? ".p" : "");
1980 /* Do the add using an addi if possible. */
1981 if (IN_RANGE (delta
, -2048, 2047))
1982 fprintf (file
, "\taddi %s,#%d,%s\n", name_arg0
, (int) delta
, name_arg0
);
1985 const char *const name_add
= reg_names
[TEMP_REGNO
];
1986 fprintf (file
, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1987 parallel
, delta
, name_add
);
1988 fprintf (file
, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1990 fprintf (file
, "\tadd %s,%s,%s\n", name_add
, name_arg0
, name_arg0
);
1995 const char *name_pic
= reg_names
[FDPIC_REGNO
];
1996 name_jmp
= reg_names
[FDPIC_FPTR_REGNO
];
2000 fprintf (file
, "\tsethi%s #gotofffuncdeschi(", parallel
);
2001 assemble_name (file
, name_func
);
2002 fprintf (file
, "),%s\n", name_jmp
);
2004 fprintf (file
, "\tsetlo #gotofffuncdesclo(");
2005 assemble_name (file
, name_func
);
2006 fprintf (file
, "),%s\n", name_jmp
);
2008 fprintf (file
, "\tldd @(%s,%s), %s\n", name_jmp
, name_pic
, name_jmp
);
2012 fprintf (file
, "\tlddo @(%s,#gotofffuncdesc12(", name_pic
);
2013 assemble_name (file
, name_func
);
2014 fprintf (file
, "\t)), %s\n", name_jmp
);
2019 fprintf (file
, "\tsethi%s #hi(", parallel
);
2020 assemble_name (file
, name_func
);
2021 fprintf (file
, "),%s\n", name_jmp
);
2023 fprintf (file
, "\tsetlo #lo(");
2024 assemble_name (file
, name_func
);
2025 fprintf (file
, "),%s\n", name_jmp
);
2029 /* Use JUMP_REGNO as a temporary PIC register. */
2030 const char *name_lr
= reg_names
[LR_REGNO
];
2031 const char *name_gppic
= name_jmp
;
2032 const char *name_tmp
= reg_names
[TEMP_REGNO
];
2034 fprintf (file
, "\tmovsg %s,%s\n", name_lr
, name_tmp
);
2035 fprintf (file
, "\tcall 1f\n");
2036 fprintf (file
, "1:\tmovsg %s,%s\n", name_lr
, name_gppic
);
2037 fprintf (file
, "\tmovgs %s,%s\n", name_tmp
, name_lr
);
2038 fprintf (file
, "\tsethi%s #gprelhi(1b),%s\n", parallel
, name_tmp
);
2039 fprintf (file
, "\tsetlo #gprello(1b),%s\n", name_tmp
);
2040 fprintf (file
, "\tsub %s,%s,%s\n", name_gppic
, name_tmp
, name_gppic
);
2042 fprintf (file
, "\tsethi%s #gprelhi(", parallel
);
2043 assemble_name (file
, name_func
);
2044 fprintf (file
, "),%s\n", name_tmp
);
2046 fprintf (file
, "\tsetlo #gprello(");
2047 assemble_name (file
, name_func
);
2048 fprintf (file
, "),%s\n", name_tmp
);
2050 fprintf (file
, "\tadd %s,%s,%s\n", name_gppic
, name_tmp
, name_jmp
);
2053 /* Jump to the function address. */
2054 fprintf (file
, "\tjmpl @(%s,%s)\n", name_jmp
, reg_names
[GPR_FIRST
+0]);
2059 /* On frv, create a frame whenever we need to create stack. */
2062 frv_frame_pointer_required (void)
2064 /* If we forgoing the usual linkage requirements, we only need
2065 a frame pointer if the stack pointer might change. */
2066 if (!TARGET_LINKED_FP
)
2067 return !crtl
->sp_is_unchanging
;
2069 if (! crtl
->is_leaf
)
2072 if (get_frame_size () != 0)
2078 if (!crtl
->sp_is_unchanging
)
2081 if (!TARGET_FDPIC
&& flag_pic
&& crtl
->uses_pic_offset_table
)
2087 if (cfun
->machine
->frame_needed
)
2094 /* Worker function for TARGET_CAN_ELIMINATE. */
2097 frv_can_eliminate (const int from
, const int to
)
2099 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
2100 ? ! frame_pointer_needed
2104 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2105 initial difference between the specified pair of registers. This macro must
2106 be defined if `ELIMINABLE_REGS' is defined. */
2108 /* See frv_stack_info for more details on the frv stack frame. */
2111 frv_initial_elimination_offset (int from
, int to
)
2113 frv_stack_t
*info
= frv_stack_info ();
2116 if (to
== STACK_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2117 ret
= info
->total_size
- info
->pretend_size
;
2119 else if (to
== STACK_POINTER_REGNUM
&& from
== FRAME_POINTER_REGNUM
)
2120 ret
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
2122 else if (to
== FRAME_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2123 ret
= (info
->total_size
2124 - info
->reg_offset
[FRAME_POINTER_REGNUM
]
2125 - info
->pretend_size
);
2130 if (TARGET_DEBUG_STACK
)
2131 fprintf (stderr
, "Eliminate %s to %s by adding %d\n",
2132 reg_names
[from
], reg_names
[to
], ret
);
2138 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2141 frv_setup_incoming_varargs (cumulative_args_t cum_v
,
2142 enum machine_mode mode
,
2143 tree type ATTRIBUTE_UNUSED
,
2147 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2149 if (TARGET_DEBUG_ARG
)
2151 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2152 *cum
, GET_MODE_NAME (mode
), *pretend_size
, second_time
);
2156 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2159 frv_expand_builtin_saveregs (void)
2161 int offset
= UNITS_PER_WORD
* FRV_NUM_ARG_REGS
;
2163 if (TARGET_DEBUG_ARG
)
2164 fprintf (stderr
, "expand_builtin_saveregs: offset from ap = %d\n",
2167 return gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
, GEN_INT (- offset
));
2171 /* Expand __builtin_va_start to do the va_start macro. */
2174 frv_expand_builtin_va_start (tree valist
, rtx nextarg
)
2177 int num
= crtl
->args
.info
- FIRST_ARG_REGNUM
- FRV_NUM_ARG_REGS
;
2179 nextarg
= gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
,
2180 GEN_INT (UNITS_PER_WORD
* num
));
2182 if (TARGET_DEBUG_ARG
)
2184 fprintf (stderr
, "va_start: args_info = %d, num = %d\n",
2185 crtl
->args
.info
, num
);
2187 debug_rtx (nextarg
);
2190 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
2191 fold_convert (TREE_TYPE (valist
),
2192 make_tree (sizetype
, nextarg
)));
2193 TREE_SIDE_EFFECTS (t
) = 1;
2195 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2199 /* Expand a block move operation, and return 1 if successful. Return 0
2200 if we should let the compiler generate normal code.
2202 operands[0] is the destination
2203 operands[1] is the source
2204 operands[2] is the length
2205 operands[3] is the alignment */
2207 /* Maximum number of loads to do before doing the stores */
2208 #ifndef MAX_MOVE_REG
2209 #define MAX_MOVE_REG 4
2212 /* Maximum number of total loads to do. */
2213 #ifndef TOTAL_MOVE_REG
2214 #define TOTAL_MOVE_REG 8
2218 frv_expand_block_move (rtx operands
[])
2220 rtx orig_dest
= operands
[0];
2221 rtx orig_src
= operands
[1];
2222 rtx bytes_rtx
= operands
[2];
2223 rtx align_rtx
= operands
[3];
2224 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2237 rtx stores
[MAX_MOVE_REG
];
2239 enum machine_mode mode
;
2241 /* If this is not a fixed size move, just call memcpy. */
2245 /* This should be a fixed size alignment. */
2246 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
2248 align
= INTVAL (align_rtx
);
2250 /* Anything to move? */
2251 bytes
= INTVAL (bytes_rtx
);
2255 /* Don't support real large moves. */
2256 if (bytes
> TOTAL_MOVE_REG
*align
)
2259 /* Move the address into scratch registers. */
2260 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2261 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2263 num_reg
= offset
= 0;
2264 for ( ; bytes
> 0; (bytes
-= move_bytes
), (offset
+= move_bytes
))
2266 /* Calculate the correct offset for src/dest. */
2270 dest_addr
= dest_reg
;
2274 src_addr
= plus_constant (Pmode
, src_reg
, offset
);
2275 dest_addr
= plus_constant (Pmode
, dest_reg
, offset
);
2278 /* Generate the appropriate load and store, saving the stores
2280 if (bytes
>= 4 && align
>= 4)
2282 else if (bytes
>= 2 && align
>= 2)
2287 move_bytes
= GET_MODE_SIZE (mode
);
2288 tmp_reg
= gen_reg_rtx (mode
);
2289 src_mem
= change_address (orig_src
, mode
, src_addr
);
2290 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2291 emit_insn (gen_rtx_SET (VOIDmode
, tmp_reg
, src_mem
));
2292 stores
[num_reg
++] = gen_rtx_SET (VOIDmode
, dest_mem
, tmp_reg
);
2294 if (num_reg
>= MAX_MOVE_REG
)
2296 for (i
= 0; i
< num_reg
; i
++)
2297 emit_insn (stores
[i
]);
2302 for (i
= 0; i
< num_reg
; i
++)
2303 emit_insn (stores
[i
]);
2309 /* Expand a block clear operation, and return 1 if successful. Return 0
2310 if we should let the compiler generate normal code.
2312 operands[0] is the destination
2313 operands[1] is the length
2314 operands[3] is the alignment */
2317 frv_expand_block_clear (rtx operands
[])
2319 rtx orig_dest
= operands
[0];
2320 rtx bytes_rtx
= operands
[1];
2321 rtx align_rtx
= operands
[3];
2322 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2330 enum machine_mode mode
;
2332 /* If this is not a fixed size move, just call memcpy. */
2336 /* This should be a fixed size alignment. */
2337 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
2339 align
= INTVAL (align_rtx
);
2341 /* Anything to move? */
2342 bytes
= INTVAL (bytes_rtx
);
2346 /* Don't support real large clears. */
2347 if (bytes
> TOTAL_MOVE_REG
*align
)
2350 /* Move the address into a scratch register. */
2351 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2354 for ( ; bytes
> 0; (bytes
-= clear_bytes
), (offset
+= clear_bytes
))
2356 /* Calculate the correct offset for src/dest. */
2357 dest_addr
= ((offset
== 0)
2359 : plus_constant (Pmode
, dest_reg
, offset
));
2361 /* Generate the appropriate store of gr0. */
2362 if (bytes
>= 4 && align
>= 4)
2364 else if (bytes
>= 2 && align
>= 2)
2369 clear_bytes
= GET_MODE_SIZE (mode
);
2370 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2371 emit_insn (gen_rtx_SET (VOIDmode
, dest_mem
, const0_rtx
));
2378 /* The following variable is used to output modifiers of assembler
2379 code of the current output insn. */
2381 static rtx
*frv_insn_operands
;
2383 /* The following function is used to add assembler insn code suffix .p
2384 if it is necessary. */
2387 frv_asm_output_opcode (FILE *f
, const char *ptr
)
2391 if (frv_insn_packing_flag
<= 0)
2394 for (; *ptr
&& *ptr
!= ' ' && *ptr
!= '\t';)
2397 if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
2398 || (*ptr
>= 'A' && *ptr
<= 'Z')))
2400 int letter
= *ptr
++;
2403 frv_print_operand (f
, frv_insn_operands
[c
], letter
);
2404 while ((c
= *ptr
) >= '0' && c
<= '9')
2416 /* Set up the packing bit for the current output insn. Note that this
2417 function is not called for asm insns. */
2420 frv_final_prescan_insn (rtx insn
, rtx
*opvec
,
2421 int noperands ATTRIBUTE_UNUSED
)
2425 if (frv_insn_packing_flag
>= 0)
2427 frv_insn_operands
= opvec
;
2428 frv_insn_packing_flag
= PACKING_FLAG_P (insn
);
2430 else if (recog_memoized (insn
) >= 0
2431 && get_attr_acc_group (insn
) == ACC_GROUP_ODD
)
2432 /* Packing optimizations have been disabled, but INSN can only
2433 be issued in M1. Insert an mnop in M0. */
2434 fprintf (asm_out_file
, "\tmnop.p\n");
2440 /* A C expression whose value is RTL representing the address in a stack frame
2441 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2442 an RTL expression for the address of the stack frame itself.
2444 If you don't define this macro, the default is to return the value of
2445 FRAMEADDR--that is, the stack frame address is also the address of the stack
2446 word that points to the previous frame. */
2448 /* The default is correct, but we need to make sure the frame gets created. */
2450 frv_dynamic_chain_address (rtx frame
)
2452 cfun
->machine
->frame_needed
= 1;
2457 /* A C expression whose value is RTL representing the value of the return
2458 address for the frame COUNT steps up from the current frame, after the
2459 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2460 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2463 The value of the expression must always be the correct address when COUNT is
2464 zero, but may be `NULL_RTX' if there is not way to determine the return
2465 address of other frames. */
2468 frv_return_addr_rtx (int count
, rtx frame
)
2472 cfun
->machine
->frame_needed
= 1;
2473 return gen_rtx_MEM (Pmode
, plus_constant (Pmode
, frame
, 8));
2476 /* Given a memory reference MEMREF, interpret the referenced memory as
2477 an array of MODE values, and return a reference to the element
2478 specified by INDEX. Assume that any pre-modification implicit in
2479 MEMREF has already happened.
2481 MEMREF must be a legitimate operand for modes larger than SImode.
2482 frv_legitimate_address_p forbids register+register addresses, which
2483 this function cannot handle. */
2485 frv_index_memory (rtx memref
, enum machine_mode mode
, int index
)
2487 rtx base
= XEXP (memref
, 0);
2488 if (GET_CODE (base
) == PRE_MODIFY
)
2489 base
= XEXP (base
, 0);
2490 return change_address (memref
, mode
,
2491 plus_constant (Pmode
, base
,
2492 index
* GET_MODE_SIZE (mode
)));
2496 /* Print a memory address as an operand to reference that memory location. */
2498 frv_print_operand_address (FILE * stream
, rtx x
)
2500 if (GET_CODE (x
) == MEM
)
2503 switch (GET_CODE (x
))
2506 fputs (reg_names
[ REGNO (x
)], stream
);
2510 fprintf (stream
, "%ld", (long) INTVAL (x
));
2514 assemble_name (stream
, XSTR (x
, 0));
2519 output_addr_const (stream
, x
);
2523 /* Poorly constructed asm statements can trigger this alternative.
2524 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2525 frv_print_operand_memory_reference (stream
, x
, 0);
2532 fatal_insn ("bad insn to frv_print_operand_address:", x
);
2537 frv_print_operand_memory_reference_reg (FILE * stream
, rtx x
)
2539 int regno
= true_regnum (x
);
2541 fputs (reg_names
[regno
], stream
);
2543 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x
);
2546 /* Print a memory reference suitable for the ld/st instructions. */
2549 frv_print_operand_memory_reference (FILE * stream
, rtx x
, int addr_offset
)
2551 struct frv_unspec unspec
;
2555 switch (GET_CODE (x
))
2562 case PRE_MODIFY
: /* (pre_modify (reg) (plus (reg) (reg))) */
2564 x1
= XEXP (XEXP (x
, 1), 1);
2574 if (GET_CODE (x0
) == CONST_INT
)
2582 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2591 else if (GET_CODE (x1
) != CONST_INT
)
2592 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2595 fputs ("@(", stream
);
2597 fputs (reg_names
[GPR_R0
], stream
);
2598 else if (GET_CODE (x0
) == REG
|| GET_CODE (x0
) == SUBREG
)
2599 frv_print_operand_memory_reference_reg (stream
, x0
);
2601 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2603 fputs (",", stream
);
2605 fputs (reg_names
[GPR_R0
], stream
);
2609 switch (GET_CODE (x1
))
2613 frv_print_operand_memory_reference_reg (stream
, x1
);
2617 fprintf (stream
, "%ld", (long) (INTVAL (x1
) + addr_offset
));
2621 if (!frv_const_unspec_p (x1
, &unspec
))
2622 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1
);
2623 frv_output_const_unspec (stream
, &unspec
);
2627 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2631 fputs (")", stream
);
2635 /* Return 2 for likely branches and 0 for non-likely branches */
2637 #define FRV_JUMP_LIKELY 2
2638 #define FRV_JUMP_NOT_LIKELY 0
2641 frv_print_operand_jump_hint (rtx insn
)
2647 enum { UNKNOWN
, BACKWARD
, FORWARD
} jump_type
= UNKNOWN
;
2649 gcc_assert (JUMP_P (insn
));
2651 /* Assume any non-conditional jump is likely. */
2652 if (! any_condjump_p (insn
))
2653 ret
= FRV_JUMP_LIKELY
;
2657 labelref
= condjump_label (insn
);
2660 rtx label
= XEXP (labelref
, 0);
2661 jump_type
= (insn_current_address
> INSN_ADDRESSES (INSN_UID (label
))
2666 note
= find_reg_note (insn
, REG_BR_PROB
, 0);
2668 ret
= ((jump_type
== BACKWARD
) ? FRV_JUMP_LIKELY
: FRV_JUMP_NOT_LIKELY
);
2672 prob
= XINT (note
, 0);
2673 ret
= ((prob
>= (REG_BR_PROB_BASE
/ 2))
2675 : FRV_JUMP_NOT_LIKELY
);
2687 case UNKNOWN
: direction
= "unknown jump direction"; break;
2688 case BACKWARD
: direction
= "jump backward"; break;
2689 case FORWARD
: direction
= "jump forward"; break;
2693 "%s: uid %ld, %s, probability = %d, max prob. = %d, hint = %d\n",
2694 IDENTIFIER_POINTER (DECL_NAME (current_function_decl
)),
2695 (long)INSN_UID (insn
), direction
, prob
,
2696 REG_BR_PROB_BASE
, ret
);
2704 /* Return the comparison operator to use for CODE given that the ICC
2708 comparison_string (enum rtx_code code
, rtx op0
)
2710 bool is_nz_p
= GET_MODE (op0
) == CC_NZmode
;
2713 default: output_operand_lossage ("bad condition code");
2714 case EQ
: return "eq";
2715 case NE
: return "ne";
2716 case LT
: return is_nz_p
? "n" : "lt";
2717 case LE
: return "le";
2718 case GT
: return "gt";
2719 case GE
: return is_nz_p
? "p" : "ge";
2720 case LTU
: return is_nz_p
? "no" : "c";
2721 case LEU
: return is_nz_p
? "eq" : "ls";
2722 case GTU
: return is_nz_p
? "ne" : "hi";
2723 case GEU
: return is_nz_p
? "ra" : "nc";
2727 /* Print an operand to an assembler instruction.
2729 `%' followed by a letter and a digit says to output an operand in an
2730 alternate fashion. Four letters have standard, built-in meanings
2731 described below. The hook `TARGET_PRINT_OPERAND' can define
2732 additional letters with nonstandard meanings.
2734 `%cDIGIT' can be used to substitute an operand that is a constant value
2735 without the syntax that normally indicates an immediate operand.
2737 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2740 `%aDIGIT' can be used to substitute an operand as if it were a memory
2741 reference, with the actual operand treated as the address. This may be
2742 useful when outputting a "load address" instruction, because often the
2743 assembler syntax for such an instruction requires you to write the operand
2744 as if it were a memory reference.
2746 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2748 `%=' outputs a number which is unique to each instruction in the entire
2749 compilation. This is useful for making local labels to be referred to more
2750 than once in a single template that generates multiple assembler
2753 `%' followed by a punctuation character specifies a substitution that
2754 does not use an operand. Only one case is standard: `%%' outputs a
2755 `%' into the assembler code. Other nonstandard cases can be defined
2756 in the `TARGET_PRINT_OPERAND' hook. You must also define which
2757 punctuation characters are valid with the
2758 `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook. */
2761 frv_print_operand (FILE * file
, rtx x
, int code
)
2763 struct frv_unspec unspec
;
2764 HOST_WIDE_INT value
;
2767 if (code
!= 0 && !ISALPHA (code
))
2770 else if (GET_CODE (x
) == CONST_INT
)
2773 else if (GET_CODE (x
) == CONST_DOUBLE
)
2775 if (GET_MODE (x
) == SFmode
)
2780 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
2781 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2785 else if (GET_MODE (x
) == VOIDmode
)
2786 value
= CONST_DOUBLE_LOW (x
);
2789 fatal_insn ("bad insn in frv_print_operand, bad const_double", x
);
2800 fputs (reg_names
[GPR_R0
], file
);
2804 fprintf (file
, "%d", frv_print_operand_jump_hint (current_output_insn
));
2808 /* Output small data area base register (gr16). */
2809 fputs (reg_names
[SDA_BASE_REG
], file
);
2813 /* Output pic register (gr17). */
2814 fputs (reg_names
[PIC_REGNO
], file
);
2818 /* Output the temporary integer CCR register. */
2819 fputs (reg_names
[ICR_TEMP
], file
);
2823 /* Output the temporary integer CC register. */
2824 fputs (reg_names
[ICC_TEMP
], file
);
2827 /* case 'a': print an address. */
2830 /* Print appropriate test for integer branch false operation. */
2831 fputs (comparison_string (reverse_condition (GET_CODE (x
)),
2832 XEXP (x
, 0)), file
);
2836 /* Print appropriate test for integer branch true operation. */
2837 fputs (comparison_string (GET_CODE (x
), XEXP (x
, 0)), file
);
2841 /* Print 1 for a NE and 0 for an EQ to give the final argument
2842 for a conditional instruction. */
2843 if (GET_CODE (x
) == NE
)
2846 else if (GET_CODE (x
) == EQ
)
2850 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x
);
2854 /* Print appropriate test for floating point branch false operation. */
2855 switch (GET_CODE (x
))
2858 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x
);
2860 case EQ
: fputs ("ne", file
); break;
2861 case NE
: fputs ("eq", file
); break;
2862 case LT
: fputs ("uge", file
); break;
2863 case LE
: fputs ("ug", file
); break;
2864 case GT
: fputs ("ule", file
); break;
2865 case GE
: fputs ("ul", file
); break;
2870 /* Print appropriate test for floating point branch true operation. */
2871 switch (GET_CODE (x
))
2874 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x
);
2876 case EQ
: fputs ("eq", file
); break;
2877 case NE
: fputs ("ne", file
); break;
2878 case LT
: fputs ("lt", file
); break;
2879 case LE
: fputs ("le", file
); break;
2880 case GT
: fputs ("gt", file
); break;
2881 case GE
: fputs ("ge", file
); break;
2886 /* Print appropriate GOT function. */
2887 if (GET_CODE (x
) != CONST_INT
)
2888 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x
);
2889 fputs (unspec_got_name (INTVAL (x
)), file
);
2893 /* Print 'i' if the operand is a constant, or is a memory reference that
2895 if (GET_CODE (x
) == MEM
)
2896 x
= ((GET_CODE (XEXP (x
, 0)) == PLUS
)
2897 ? XEXP (XEXP (x
, 0), 1)
2899 else if (GET_CODE (x
) == PLUS
)
2902 switch (GET_CODE (x
))
2916 /* For jump instructions, print 'i' if the operand is a constant or
2917 is an expression that adds a constant. */
2918 if (GET_CODE (x
) == CONST_INT
)
2923 if (GET_CODE (x
) == CONST_INT
2924 || (GET_CODE (x
) == PLUS
2925 && (GET_CODE (XEXP (x
, 1)) == CONST_INT
2926 || GET_CODE (XEXP (x
, 0)) == CONST_INT
)))
2932 /* Print the lower register of a double word register pair */
2933 if (GET_CODE (x
) == REG
)
2934 fputs (reg_names
[ REGNO (x
)+1 ], file
);
2936 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x
);
2939 /* case 'l': print a LABEL_REF. */
2943 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2944 for the second word of double memory operations. */
2945 offset
= (code
== 'M') ? 0 : UNITS_PER_WORD
;
2946 switch (GET_CODE (x
))
2949 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x
);
2952 frv_print_operand_memory_reference (file
, XEXP (x
, 0), offset
);
2960 frv_print_operand_memory_reference (file
, x
, offset
);
2966 /* Print the opcode of a command. */
2967 switch (GET_CODE (x
))
2970 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x
);
2972 case PLUS
: fputs ("add", file
); break;
2973 case MINUS
: fputs ("sub", file
); break;
2974 case AND
: fputs ("and", file
); break;
2975 case IOR
: fputs ("or", file
); break;
2976 case XOR
: fputs ("xor", file
); break;
2977 case ASHIFT
: fputs ("sll", file
); break;
2978 case ASHIFTRT
: fputs ("sra", file
); break;
2979 case LSHIFTRT
: fputs ("srl", file
); break;
2983 /* case 'n': negate and print a constant int. */
2986 /* Print PIC label using operand as the number. */
2987 if (GET_CODE (x
) != CONST_INT
)
2988 fatal_insn ("bad insn to frv_print_operand, P modifier:", x
);
2990 fprintf (file
, ".LCF%ld", (long)INTVAL (x
));
2994 /* Print 'u' if the operand is a update load/store. */
2995 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
3000 /* If value is 0, print gr0, otherwise it must be a register. */
3001 if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0)
3002 fputs (reg_names
[GPR_R0
], file
);
3004 else if (GET_CODE (x
) == REG
)
3005 fputs (reg_names
[REGNO (x
)], file
);
3008 fatal_insn ("bad insn in frv_print_operand, z case", x
);
3012 /* Print constant in hex. */
3013 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
3015 fprintf (file
, "%s0x%.4lx", IMMEDIATE_PREFIX
, (long) value
);
3022 if (GET_CODE (x
) == REG
)
3023 fputs (reg_names
[REGNO (x
)], file
);
3025 else if (GET_CODE (x
) == CONST_INT
3026 || GET_CODE (x
) == CONST_DOUBLE
)
3027 fprintf (file
, "%s%ld", IMMEDIATE_PREFIX
, (long) value
);
3029 else if (frv_const_unspec_p (x
, &unspec
))
3030 frv_output_const_unspec (file
, &unspec
);
3032 else if (GET_CODE (x
) == MEM
)
3033 frv_print_operand_address (file
, XEXP (x
, 0));
3035 else if (CONSTANT_ADDRESS_P (x
))
3036 frv_print_operand_address (file
, x
);
3039 fatal_insn ("bad insn in frv_print_operand, 0 case", x
);
3044 fatal_insn ("frv_print_operand: unknown code", x
);
3052 frv_print_operand_punct_valid_p (unsigned char code
)
3054 return (code
== '.' || code
== '#' || code
== '@' || code
== '~'
3055 || code
== '*' || code
== '&');
3059 /* A C statement (sans semicolon) for initializing the variable CUM for the
3060 state at the beginning of the argument list. The variable has type
3061 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3062 of the function which will receive the args, or 0 if the args are to a
3063 compiler support library function. The value of INDIRECT is nonzero when
3064 processing an indirect call, for example a call through a function pointer.
3065 The value of INDIRECT is zero for a call to an explicitly named function, a
3066 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3067 arguments for the function being compiled.
3069 When processing a call to a compiler support library function, LIBNAME
3070 identifies which one. It is a `symbol_ref' rtx which contains the name of
3071 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3072 being processed. Thus, each time this macro is called, either LIBNAME or
3073 FNTYPE is nonzero, but never both of them at once. */
3076 frv_init_cumulative_args (CUMULATIVE_ARGS
*cum
,
3082 *cum
= FIRST_ARG_REGNUM
;
3084 if (TARGET_DEBUG_ARG
)
3086 fprintf (stderr
, "\ninit_cumulative_args:");
3087 if (!fndecl
&& fntype
)
3088 fputs (" indirect", stderr
);
3091 fputs (" incoming", stderr
);
3095 tree ret_type
= TREE_TYPE (fntype
);
3096 fprintf (stderr
, " return=%s,",
3097 get_tree_code_name (TREE_CODE (ret_type
)));
3100 if (libname
&& GET_CODE (libname
) == SYMBOL_REF
)
3101 fprintf (stderr
, " libname=%s", XSTR (libname
, 0));
3103 if (cfun
->returns_struct
)
3104 fprintf (stderr
, " return-struct");
3106 putc ('\n', stderr
);
3111 /* Return true if we should pass an argument on the stack rather than
3115 frv_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
3117 if (mode
== BLKmode
)
3121 return AGGREGATE_TYPE_P (type
);
3124 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3125 argument with the specified mode and type. If it is not defined,
3126 `PARM_BOUNDARY' is used for all arguments. */
3129 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED
,
3130 const_tree type ATTRIBUTE_UNUSED
)
3132 return BITS_PER_WORD
;
3136 frv_function_arg_1 (cumulative_args_t cum_v
, enum machine_mode mode
,
3137 const_tree type ATTRIBUTE_UNUSED
, bool named
,
3138 bool incoming ATTRIBUTE_UNUSED
)
3140 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
3142 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3147 /* Return a marker for use in the call instruction. */
3148 if (xmode
== VOIDmode
)
3154 else if (arg_num
<= LAST_ARG_REGNUM
)
3156 ret
= gen_rtx_REG (xmode
, arg_num
);
3157 debstr
= reg_names
[arg_num
];
3166 if (TARGET_DEBUG_ARG
)
3168 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3169 arg_num
, GET_MODE_NAME (mode
), named
, GET_MODE_SIZE (mode
), debstr
);
3175 frv_function_arg (cumulative_args_t cum
, enum machine_mode mode
,
3176 const_tree type
, bool named
)
3178 return frv_function_arg_1 (cum
, mode
, type
, named
, false);
3182 frv_function_incoming_arg (cumulative_args_t cum
, enum machine_mode mode
,
3183 const_tree type
, bool named
)
3185 return frv_function_arg_1 (cum
, mode
, type
, named
, true);
3189 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3190 advance past an argument in the argument list. The values MODE, TYPE and
3191 NAMED describe that argument. Once this is done, the variable CUM is
3192 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3194 This macro need not do anything if the argument in question was passed on
3195 the stack. The compiler knows how to track the amount of stack space used
3196 for arguments without any special help. */
3199 frv_function_arg_advance (cumulative_args_t cum_v
,
3200 enum machine_mode mode
,
3201 const_tree type ATTRIBUTE_UNUSED
,
3204 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
3206 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3207 int bytes
= GET_MODE_SIZE (xmode
);
3208 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3211 *cum
= arg_num
+ words
;
3213 if (TARGET_DEBUG_ARG
)
3215 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3216 arg_num
, GET_MODE_NAME (mode
), named
, words
* UNITS_PER_WORD
);
3220 /* A C expression for the number of words, at the beginning of an argument,
3221 must be put in registers. The value must be zero for arguments that are
3222 passed entirely in registers or that are entirely pushed on the stack.
3224 On some machines, certain arguments must be passed partially in registers
3225 and partially in memory. On these machines, typically the first N words of
3226 arguments are passed in registers, and the rest on the stack. If a
3227 multi-word argument (a `double' or a structure) crosses that boundary, its
3228 first few words must be passed in registers and the rest must be pushed.
3229 This macro tells the compiler when this occurs, and how many of the words
3230 should go in registers.
3232 `FUNCTION_ARG' for these arguments should return the first register to be
3233 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3234 the called function. */
3237 frv_arg_partial_bytes (cumulative_args_t cum
, enum machine_mode mode
,
3238 tree type ATTRIBUTE_UNUSED
, bool named ATTRIBUTE_UNUSED
)
3241 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3242 int bytes
= GET_MODE_SIZE (xmode
);
3243 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3244 int arg_num
= *get_cumulative_args (cum
);
3247 ret
= ((arg_num
<= LAST_ARG_REGNUM
&& arg_num
+ words
> LAST_ARG_REGNUM
+1)
3248 ? LAST_ARG_REGNUM
- arg_num
+ 1
3250 ret
*= UNITS_PER_WORD
;
3252 if (TARGET_DEBUG_ARG
&& ret
)
3253 fprintf (stderr
, "frv_arg_partial_bytes: %d\n", ret
);
3259 /* Implements TARGET_FUNCTION_VALUE. */
3262 frv_function_value (const_tree valtype
,
3263 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
3264 bool outgoing ATTRIBUTE_UNUSED
)
3266 return gen_rtx_REG (TYPE_MODE (valtype
), RETURN_VALUE_REGNUM
);
3270 /* Implements TARGET_LIBCALL_VALUE. */
3273 frv_libcall_value (enum machine_mode mode
,
3274 const_rtx fun ATTRIBUTE_UNUSED
)
3276 return gen_rtx_REG (mode
, RETURN_VALUE_REGNUM
);
3280 /* Implements FUNCTION_VALUE_REGNO_P. */
3283 frv_function_value_regno_p (const unsigned int regno
)
3285 return (regno
== RETURN_VALUE_REGNUM
);
3288 /* Return true if a register is ok to use as a base or index register. */
3290 static FRV_INLINE
int
3291 frv_regno_ok_for_base_p (int regno
, int strict_p
)
3297 return (reg_renumber
[regno
] >= 0 && GPR_P (reg_renumber
[regno
]));
3299 if (regno
== ARG_POINTER_REGNUM
)
3302 return (regno
>= FIRST_PSEUDO_REGISTER
);
3306 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3307 RTX) is a legitimate memory address on the target machine for a memory
3308 operand of mode MODE.
3310 It usually pays to define several simpler macros to serve as subroutines for
3311 this one. Otherwise it may be too complicated to understand.
3313 This macro must exist in two variants: a strict variant and a non-strict
3314 one. The strict variant is used in the reload pass. It must be defined so
3315 that any pseudo-register that has not been allocated a hard register is
3316 considered a memory reference. In contexts where some kind of register is
3317 required, a pseudo-register with no hard register must be rejected.
3319 The non-strict variant is used in other passes. It must be defined to
3320 accept all pseudo-registers in every context where some kind of register is
3323 Compiler source files that want to use the strict variant of this macro
3324 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3325 conditional to define the strict variant in that case and the non-strict
3328 Normally, constant addresses which are the sum of a `symbol_ref' and an
3329 integer are stored inside a `const' RTX to mark them as constant.
3330 Therefore, there is no need to recognize such sums specifically as
3331 legitimate addresses. Normally you would simply recognize any `const' as
3334 Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle
3335 constant sums that are not marked with `const'. It assumes that a
3336 naked `plus' indicates indexing. If so, then you *must* reject such
3337 naked constant sums as illegitimate addresses, so that none of them
3338 will be given to `TARGET_PRINT_OPERAND_ADDRESS'. */
3341 frv_legitimate_address_p_1 (enum machine_mode mode
,
3345 int allow_double_reg_p
)
3349 HOST_WIDE_INT value
;
3352 if (FRV_SYMBOL_REF_TLS_P (x
))
3355 switch (GET_CODE (x
))
3362 if (GET_CODE (x
) != REG
)
3368 ret
= frv_regno_ok_for_base_p (REGNO (x
), strict_p
);
3374 if (GET_CODE (x0
) != REG
3375 || ! frv_regno_ok_for_base_p (REGNO (x0
), strict_p
)
3376 || GET_CODE (x1
) != PLUS
3377 || ! rtx_equal_p (x0
, XEXP (x1
, 0))
3378 || GET_CODE (XEXP (x1
, 1)) != REG
3379 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1
, 1)), strict_p
))
3386 /* 12-bit immediate */
3391 ret
= IN_RANGE (INTVAL (x
), -2048, 2047);
3393 /* If we can't use load/store double operations, make sure we can
3394 address the second word. */
3395 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3396 ret
= IN_RANGE (INTVAL (x
) + GET_MODE_SIZE (mode
) - 1,
3405 if (GET_CODE (x0
) == SUBREG
)
3406 x0
= SUBREG_REG (x0
);
3408 if (GET_CODE (x0
) != REG
)
3411 regno0
= REGNO (x0
);
3412 if (!frv_regno_ok_for_base_p (regno0
, strict_p
))
3415 switch (GET_CODE (x1
))
3421 x1
= SUBREG_REG (x1
);
3422 if (GET_CODE (x1
) != REG
)
3428 /* Do not allow reg+reg addressing for modes > 1 word if we
3429 can't depend on having move double instructions. */
3430 if (!allow_double_reg_p
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3433 ret
= frv_regno_ok_for_base_p (REGNO (x1
), strict_p
);
3437 /* 12-bit immediate */
3442 value
= INTVAL (x1
);
3443 ret
= IN_RANGE (value
, -2048, 2047);
3445 /* If we can't use load/store double operations, make sure we can
3446 address the second word. */
3447 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3448 ret
= IN_RANGE (value
+ GET_MODE_SIZE (mode
) - 1, -2048, 2047);
3453 if (!condexec_p
&& got12_operand (x1
, VOIDmode
))
3461 if (TARGET_DEBUG_ADDR
)
3463 fprintf (stderr
, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3464 GET_MODE_NAME (mode
), ret
, (strict_p
) ? "" : "not ",
3465 (condexec_p
) ? ", inside conditional code" : "");
3473 frv_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
3475 return frv_legitimate_address_p_1 (mode
, x
, strict_p
, FALSE
, FALSE
);
3478 /* Given an ADDR, generate code to inline the PLT. */
3480 gen_inlined_tls_plt (rtx addr
)
3483 rtx picreg
= get_hard_reg_initial_val (Pmode
, FDPIC_REG
);
3486 dest
= gen_reg_rtx (DImode
);
3493 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3494 calll #gettlsoff(ADDR)@(gr8, gr0)
3496 emit_insn (gen_tls_lddi (dest
, addr
, picreg
));
3503 sethi.p #gottlsdeschi(ADDR), gr8
3504 setlo #gottlsdesclo(ADDR), gr8
3505 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3506 calll #gettlsoff(ADDR)@(gr8, gr0)
3508 rtx reguse
= gen_reg_rtx (Pmode
);
3509 emit_insn (gen_tlsoff_hilo (reguse
, addr
, GEN_INT (R_FRV_GOTTLSDESCHI
)));
3510 emit_insn (gen_tls_tlsdesc_ldd (dest
, picreg
, reguse
, addr
));
3513 retval
= gen_reg_rtx (Pmode
);
3514 emit_insn (gen_tls_indirect_call (retval
, addr
, dest
, picreg
));
3518 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3519 the destination address. */
3521 gen_tlsmoff (rtx addr
, rtx reg
)
3523 rtx dest
= gen_reg_rtx (Pmode
);
3527 /* sethi.p #tlsmoffhi(x), grA
3528 setlo #tlsmofflo(x), grA
3530 dest
= gen_reg_rtx (Pmode
);
3531 emit_insn (gen_tlsoff_hilo (dest
, addr
,
3532 GEN_INT (R_FRV_TLSMOFFHI
)));
3533 dest
= gen_rtx_PLUS (Pmode
, dest
, reg
);
3537 /* addi grB, #tlsmoff12(x), grC
3539 ld/st @(grB, #tlsmoff12(x)), grC
3541 dest
= gen_reg_rtx (Pmode
);
3542 emit_insn (gen_symGOTOFF2reg_i (dest
, addr
, reg
,
3543 GEN_INT (R_FRV_TLSMOFF12
)));
3548 /* Generate code for a TLS address. */
3550 frv_legitimize_tls_address (rtx addr
, enum tls_model model
)
3552 rtx dest
, tp
= gen_rtx_REG (Pmode
, 29);
3553 rtx picreg
= get_hard_reg_initial_val (Pmode
, 15);
3557 case TLS_MODEL_INITIAL_EXEC
:
3561 ldi @(gr15, #gottlsoff12(x)), gr5
3563 dest
= gen_reg_rtx (Pmode
);
3564 emit_insn (gen_tls_load_gottlsoff12 (dest
, addr
, picreg
));
3565 dest
= gen_rtx_PLUS (Pmode
, tp
, dest
);
3569 /* -fPIC or anything else.
3571 sethi.p #gottlsoffhi(x), gr14
3572 setlo #gottlsofflo(x), gr14
3573 ld #tlsoff(x)@(gr15, gr14), gr9
3575 rtx tmp
= gen_reg_rtx (Pmode
);
3576 dest
= gen_reg_rtx (Pmode
);
3577 emit_insn (gen_tlsoff_hilo (tmp
, addr
,
3578 GEN_INT (R_FRV_GOTTLSOFF_HI
)));
3580 emit_insn (gen_tls_tlsoff_ld (dest
, picreg
, tmp
, addr
));
3581 dest
= gen_rtx_PLUS (Pmode
, tp
, dest
);
3584 case TLS_MODEL_LOCAL_DYNAMIC
:
3588 if (TARGET_INLINE_PLT
)
3589 retval
= gen_inlined_tls_plt (GEN_INT (0));
3592 /* call #gettlsoff(0) */
3593 retval
= gen_reg_rtx (Pmode
);
3594 emit_insn (gen_call_gettlsoff (retval
, GEN_INT (0), picreg
));
3597 reg
= gen_reg_rtx (Pmode
);
3598 emit_insn (gen_rtx_SET (VOIDmode
, reg
,
3599 gen_rtx_PLUS (Pmode
,
3602 dest
= gen_tlsmoff (addr
, reg
);
3605 dest = gen_reg_rtx (Pmode);
3606 emit_insn (gen_tlsoff_hilo (dest, addr,
3607 GEN_INT (R_FRV_TLSMOFFHI)));
3608 dest = gen_rtx_PLUS (Pmode, dest, reg);
3612 case TLS_MODEL_LOCAL_EXEC
:
3613 dest
= gen_tlsmoff (addr
, gen_rtx_REG (Pmode
, 29));
3615 case TLS_MODEL_GLOBAL_DYNAMIC
:
3619 if (TARGET_INLINE_PLT
)
3620 retval
= gen_inlined_tls_plt (addr
);
3623 /* call #gettlsoff(x) */
3624 retval
= gen_reg_rtx (Pmode
);
3625 emit_insn (gen_call_gettlsoff (retval
, addr
, picreg
));
3627 dest
= gen_rtx_PLUS (Pmode
, retval
, tp
);
3638 frv_legitimize_address (rtx x
,
3639 rtx oldx ATTRIBUTE_UNUSED
,
3640 enum machine_mode mode ATTRIBUTE_UNUSED
)
3642 if (GET_CODE (x
) == SYMBOL_REF
)
3644 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
3646 return frv_legitimize_tls_address (x
, model
);
3652 /* Test whether a local function descriptor is canonical, i.e.,
3653 whether we can use FUNCDESC_GOTOFF to compute the address of the
3657 frv_local_funcdesc_p (rtx fnx
)
3660 enum symbol_visibility vis
;
3663 if (! SYMBOL_REF_LOCAL_P (fnx
))
3666 fn
= SYMBOL_REF_DECL (fnx
);
3671 vis
= DECL_VISIBILITY (fn
);
3673 if (vis
== VISIBILITY_PROTECTED
)
3674 /* Private function descriptors for protected functions are not
3675 canonical. Temporarily change the visibility to global. */
3676 vis
= VISIBILITY_DEFAULT
;
3677 else if (flag_shlib
)
3678 /* If we're already compiling for a shared library (that, unlike
3679 executables, can't assume that the existence of a definition
3680 implies local binding), we can skip the re-testing. */
3683 ret
= default_binds_local_p_1 (fn
, flag_pic
);
3685 DECL_VISIBILITY (fn
) = vis
;
3690 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3694 frv_gen_GPsym2reg (rtx dest
, rtx src
)
3696 tree gp
= get_identifier ("_gp");
3697 rtx gp_sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (gp
));
3699 return gen_symGOT2reg (dest
, gp_sym
, src
, GEN_INT (R_FRV_GOT12
));
3703 unspec_got_name (int i
)
3707 case R_FRV_GOT12
: return "got12";
3708 case R_FRV_GOTHI
: return "gothi";
3709 case R_FRV_GOTLO
: return "gotlo";
3710 case R_FRV_FUNCDESC
: return "funcdesc";
3711 case R_FRV_FUNCDESC_GOT12
: return "gotfuncdesc12";
3712 case R_FRV_FUNCDESC_GOTHI
: return "gotfuncdeschi";
3713 case R_FRV_FUNCDESC_GOTLO
: return "gotfuncdesclo";
3714 case R_FRV_FUNCDESC_VALUE
: return "funcdescvalue";
3715 case R_FRV_FUNCDESC_GOTOFF12
: return "gotofffuncdesc12";
3716 case R_FRV_FUNCDESC_GOTOFFHI
: return "gotofffuncdeschi";
3717 case R_FRV_FUNCDESC_GOTOFFLO
: return "gotofffuncdesclo";
3718 case R_FRV_GOTOFF12
: return "gotoff12";
3719 case R_FRV_GOTOFFHI
: return "gotoffhi";
3720 case R_FRV_GOTOFFLO
: return "gotofflo";
3721 case R_FRV_GPREL12
: return "gprel12";
3722 case R_FRV_GPRELHI
: return "gprelhi";
3723 case R_FRV_GPRELLO
: return "gprello";
3724 case R_FRV_GOTTLSOFF_HI
: return "gottlsoffhi";
3725 case R_FRV_GOTTLSOFF_LO
: return "gottlsofflo";
3726 case R_FRV_TLSMOFFHI
: return "tlsmoffhi";
3727 case R_FRV_TLSMOFFLO
: return "tlsmofflo";
3728 case R_FRV_TLSMOFF12
: return "tlsmoff12";
3729 case R_FRV_TLSDESCHI
: return "tlsdeschi";
3730 case R_FRV_TLSDESCLO
: return "tlsdesclo";
3731 case R_FRV_GOTTLSDESCHI
: return "gottlsdeschi";
3732 case R_FRV_GOTTLSDESCLO
: return "gottlsdesclo";
3733 default: gcc_unreachable ();
3737 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3738 is added inside the relocation operator. */
3741 frv_output_const_unspec (FILE *stream
, const struct frv_unspec
*unspec
)
3743 fprintf (stream
, "#%s(", unspec_got_name (unspec
->reloc
));
3744 output_addr_const (stream
, plus_constant (Pmode
, unspec
->symbol
,
3746 fputs (")", stream
);
3749 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3750 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3751 otherwise return ORIG_X. */
3754 frv_find_base_term (rtx x
)
3756 struct frv_unspec unspec
;
3758 if (frv_const_unspec_p (x
, &unspec
)
3759 && frv_small_data_reloc_p (unspec
.symbol
, unspec
.reloc
))
3760 return plus_constant (Pmode
, unspec
.symbol
, unspec
.offset
);
3765 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3766 the operand is used by a predicated instruction. */
3769 frv_legitimate_memory_operand (rtx op
, enum machine_mode mode
, int condexec_p
)
3771 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
3772 && GET_CODE (op
) == MEM
3773 && frv_legitimate_address_p_1 (mode
, XEXP (op
, 0),
3774 reload_completed
, condexec_p
, FALSE
));
3778 frv_expand_fdpic_call (rtx
*operands
, bool ret_value
, bool sibcall
)
3780 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
3781 rtx picreg
= get_hard_reg_initial_val (SImode
, FDPIC_REG
);
3787 rvrtx
= operands
[0];
3791 addr
= XEXP (operands
[0], 0);
3793 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3794 any calls that would involve a PLT, but can't tell, since we
3795 don't know whether an extern function is going to be provided by
3796 a separate translation unit or imported from a separate module.
3797 When compiling for shared libraries, if the function has default
3798 visibility, we assume it's overridable, so we inline the PLT, but
3799 for executables, we don't really have a way to make a good
3800 decision: a function is as likely to be imported from a shared
3801 library as it is to be defined in the executable itself. We
3802 assume executables will get global functions defined locally,
3803 whereas shared libraries will have them potentially overridden,
3804 so we only inline PLTs when compiling for shared libraries.
3806 In order to mark a function as local to a shared library, any
3807 non-default visibility attribute suffices. Unfortunately,
3808 there's no simple way to tag a function declaration as ``in a
3809 different module'', which we could then use to trigger PLT
3810 inlining on executables. There's -minline-plt, but it affects
3811 all external functions, so one would have to also mark function
3812 declarations available in the same module with non-default
3813 visibility, which is advantageous in itself. */
3814 if (GET_CODE (addr
) == SYMBOL_REF
3815 && ((!SYMBOL_REF_LOCAL_P (addr
) && TARGET_INLINE_PLT
)
3819 dest
= gen_reg_rtx (SImode
);
3821 x
= gen_symGOTOFF2reg_hilo (dest
, addr
, OUR_FDPIC_REG
,
3822 GEN_INT (R_FRV_FUNCDESC_GOTOFF12
));
3824 x
= gen_symGOTOFF2reg (dest
, addr
, OUR_FDPIC_REG
,
3825 GEN_INT (R_FRV_FUNCDESC_GOTOFF12
));
3827 crtl
->uses_pic_offset_table
= TRUE
;
3830 else if (GET_CODE (addr
) == SYMBOL_REF
)
3832 /* These are always either local, or handled through a local
3835 c
= gen_call_value_fdpicsi (rvrtx
, addr
, operands
[1],
3836 operands
[2], picreg
, lr
);
3838 c
= gen_call_fdpicsi (addr
, operands
[1], operands
[2], picreg
, lr
);
3842 else if (! ldd_address_operand (addr
, Pmode
))
3843 addr
= force_reg (Pmode
, addr
);
3845 picreg
= gen_reg_rtx (DImode
);
3846 emit_insn (gen_movdi_ldd (picreg
, addr
));
3848 if (sibcall
&& ret_value
)
3849 c
= gen_sibcall_value_fdpicdi (rvrtx
, picreg
, const0_rtx
);
3851 c
= gen_sibcall_fdpicdi (picreg
, const0_rtx
);
3853 c
= gen_call_value_fdpicdi (rvrtx
, picreg
, const0_rtx
, lr
);
3855 c
= gen_call_fdpicdi (picreg
, const0_rtx
, lr
);
3859 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3860 process these separately from any offsets, such that we add any
3861 offsets to the function descriptor (the actual pointer), not to the
3862 function address. */
3865 frv_function_symbol_referenced_p (rtx x
)
3871 if (GET_CODE (x
) == SYMBOL_REF
)
3872 return SYMBOL_REF_FUNCTION_P (x
);
3874 length
= GET_RTX_LENGTH (GET_CODE (x
));
3875 format
= GET_RTX_FORMAT (GET_CODE (x
));
3877 for (j
= 0; j
< length
; ++j
)
3882 if (frv_function_symbol_referenced_p (XEXP (x
, j
)))
3888 if (XVEC (x
, j
) != 0)
3891 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
3892 if (frv_function_symbol_referenced_p (XVECEXP (x
, j
, k
)))
3898 /* Nothing to do. */
3906 /* Return true if the memory operand is one that can be conditionally
3910 condexec_memory_operand (rtx op
, enum machine_mode mode
)
3912 enum machine_mode op_mode
= GET_MODE (op
);
3915 if (mode
!= VOIDmode
&& op_mode
!= mode
)
3930 if (GET_CODE (op
) != MEM
)
3933 addr
= XEXP (op
, 0);
3934 return frv_legitimate_address_p_1 (mode
, addr
, reload_completed
, TRUE
, FALSE
);
3937 /* Return true if the bare return instruction can be used outside of the
3938 epilog code. For frv, we only do it if there was no stack allocation. */
3941 direct_return_p (void)
3945 if (!reload_completed
)
3948 info
= frv_stack_info ();
3949 return (info
->total_size
== 0);
3954 frv_emit_move (enum machine_mode mode
, rtx dest
, rtx src
)
3956 if (GET_CODE (src
) == SYMBOL_REF
)
3958 enum tls_model model
= SYMBOL_REF_TLS_MODEL (src
);
3960 src
= frv_legitimize_tls_address (src
, model
);
3966 if (frv_emit_movsi (dest
, src
))
3975 if (!reload_in_progress
3976 && !reload_completed
3977 && !register_operand (dest
, mode
)
3978 && !reg_or_0_operand (src
, mode
))
3979 src
= copy_to_mode_reg (mode
, src
);
3986 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
3989 /* Emit code to handle a MOVSI, adding in the small data register or pic
3990 register if needed to load up addresses. Return TRUE if the appropriate
3991 instructions are emitted. */
3994 frv_emit_movsi (rtx dest
, rtx src
)
3996 int base_regno
= -1;
3999 struct frv_unspec old_unspec
;
4001 if (!reload_in_progress
4002 && !reload_completed
4003 && !register_operand (dest
, SImode
)
4004 && (!reg_or_0_operand (src
, SImode
)
4005 /* Virtual registers will almost always be replaced by an
4006 add instruction, so expose this to CSE by copying to
4007 an intermediate register. */
4008 || (GET_CODE (src
) == REG
4009 && IN_RANGE (REGNO (src
),
4010 FIRST_VIRTUAL_REGISTER
,
4011 LAST_VIRTUAL_POINTER_REGISTER
))))
4013 emit_insn (gen_rtx_SET (VOIDmode
, dest
, copy_to_mode_reg (SImode
, src
)));
4017 /* Explicitly add in the PIC or small data register if needed. */
4018 switch (GET_CODE (src
))
4027 /* Using GPREL12, we use a single GOT entry for all symbols
4028 in read-only sections, but trade sequences such as:
4030 sethi #gothi(label), gr#
4031 setlo #gotlo(label), gr#
4036 ld @(gr15,#got12(_gp)), gr#
4037 sethi #gprelhi(label), gr##
4038 setlo #gprello(label), gr##
4041 We may often be able to share gr# for multiple
4042 computations of GPREL addresses, and we may often fold
4043 the final add into the pair of registers of a load or
4044 store instruction, so it's often profitable. Even when
4045 optimizing for size, we're trading a GOT entry for an
4046 additional instruction, which trades GOT space
4047 (read-write) for code size (read-only, shareable), as
4048 long as the symbol is not used in more than two different
4051 With -fpie/-fpic, we'd be trading a single load for a
4052 sequence of 4 instructions, because the offset of the
4053 label can't be assumed to be addressable with 12 bits, so
4054 we don't do this. */
4055 if (TARGET_GPREL_RO
)
4056 unspec
= R_FRV_GPREL12
;
4058 unspec
= R_FRV_GOT12
;
4061 base_regno
= PIC_REGNO
;
4066 if (frv_const_unspec_p (src
, &old_unspec
))
4069 if (TARGET_FDPIC
&& frv_function_symbol_referenced_p (XEXP (src
, 0)))
4072 src
= force_reg (GET_MODE (XEXP (src
, 0)), XEXP (src
, 0));
4073 emit_move_insn (dest
, src
);
4078 sym
= XEXP (sym
, 0);
4079 if (GET_CODE (sym
) == PLUS
4080 && GET_CODE (XEXP (sym
, 0)) == SYMBOL_REF
4081 && GET_CODE (XEXP (sym
, 1)) == CONST_INT
)
4082 sym
= XEXP (sym
, 0);
4083 if (GET_CODE (sym
) == SYMBOL_REF
)
4085 else if (GET_CODE (sym
) == LABEL_REF
)
4088 goto handle_whatever
;
4096 enum tls_model model
= SYMBOL_REF_TLS_MODEL (sym
);
4100 src
= frv_legitimize_tls_address (src
, model
);
4101 emit_move_insn (dest
, src
);
4105 if (SYMBOL_REF_FUNCTION_P (sym
))
4107 if (frv_local_funcdesc_p (sym
))
4108 unspec
= R_FRV_FUNCDESC_GOTOFF12
;
4110 unspec
= R_FRV_FUNCDESC_GOT12
;
4114 if (CONSTANT_POOL_ADDRESS_P (sym
))
4115 switch (GET_CODE (get_pool_constant (sym
)))
4122 unspec
= R_FRV_GOTOFF12
;
4127 if (TARGET_GPREL_RO
)
4128 unspec
= R_FRV_GPREL12
;
4130 unspec
= R_FRV_GOT12
;
4133 else if (SYMBOL_REF_LOCAL_P (sym
)
4134 && !SYMBOL_REF_EXTERNAL_P (sym
)
4135 && SYMBOL_REF_DECL (sym
)
4136 && (!DECL_P (SYMBOL_REF_DECL (sym
))
4137 || !DECL_COMMON (SYMBOL_REF_DECL (sym
))))
4139 tree decl
= SYMBOL_REF_DECL (sym
);
4140 tree init
= TREE_CODE (decl
) == VAR_DECL
4141 ? DECL_INITIAL (decl
)
4142 : TREE_CODE (decl
) == CONSTRUCTOR
4145 bool named_section
, readonly
;
4147 if (init
&& init
!= error_mark_node
)
4148 reloc
= compute_reloc_for_constant (init
);
4150 named_section
= TREE_CODE (decl
) == VAR_DECL
4151 && lookup_attribute ("section", DECL_ATTRIBUTES (decl
));
4152 readonly
= decl_readonly_section (decl
, reloc
);
4155 unspec
= R_FRV_GOT12
;
4157 unspec
= R_FRV_GOTOFF12
;
4158 else if (readonly
&& TARGET_GPREL_RO
)
4159 unspec
= R_FRV_GPREL12
;
4161 unspec
= R_FRV_GOT12
;
4164 unspec
= R_FRV_GOT12
;
4168 else if (SYMBOL_REF_SMALL_P (sym
))
4169 base_regno
= SDA_BASE_REG
;
4172 base_regno
= PIC_REGNO
;
4177 if (base_regno
>= 0)
4179 if (GET_CODE (sym
) == SYMBOL_REF
&& SYMBOL_REF_SMALL_P (sym
))
4180 emit_insn (gen_symGOTOFF2reg (dest
, src
,
4181 gen_rtx_REG (Pmode
, base_regno
),
4182 GEN_INT (R_FRV_GPREL12
)));
4184 emit_insn (gen_symGOTOFF2reg_hilo (dest
, src
,
4185 gen_rtx_REG (Pmode
, base_regno
),
4186 GEN_INT (R_FRV_GPREL12
)));
4187 if (base_regno
== PIC_REGNO
)
4188 crtl
->uses_pic_offset_table
= TRUE
;
4196 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4197 new uses of it once reload has begun. */
4198 gcc_assert (!reload_in_progress
&& !reload_completed
);
4202 case R_FRV_GOTOFF12
:
4203 if (!frv_small_data_reloc_p (sym
, unspec
))
4204 x
= gen_symGOTOFF2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4207 x
= gen_symGOTOFF2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4210 if (!frv_small_data_reloc_p (sym
, unspec
))
4211 x
= gen_symGPREL2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4214 x
= gen_symGPREL2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4216 case R_FRV_FUNCDESC_GOTOFF12
:
4218 x
= gen_symGOTOFF2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4221 x
= gen_symGOTOFF2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4225 x
= gen_symGOT2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4228 x
= gen_symGOT2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4232 crtl
->uses_pic_offset_table
= TRUE
;
4241 /* Return a string to output a single word move. */
4244 output_move_single (rtx operands
[], rtx insn
)
4246 rtx dest
= operands
[0];
4247 rtx src
= operands
[1];
4249 if (GET_CODE (dest
) == REG
)
4251 int dest_regno
= REGNO (dest
);
4252 enum machine_mode mode
= GET_MODE (dest
);
4254 if (GPR_P (dest_regno
))
4256 if (GET_CODE (src
) == REG
)
4258 /* gpr <- some sort of register */
4259 int src_regno
= REGNO (src
);
4261 if (GPR_P (src_regno
))
4262 return "mov %1, %0";
4264 else if (FPR_P (src_regno
))
4265 return "movfg %1, %0";
4267 else if (SPR_P (src_regno
))
4268 return "movsg %1, %0";
4271 else if (GET_CODE (src
) == MEM
)
4280 return "ldsb%I1%U1 %M1,%0";
4283 return "ldsh%I1%U1 %M1,%0";
4287 return "ld%I1%U1 %M1, %0";
4291 else if (GET_CODE (src
) == CONST_INT
4292 || GET_CODE (src
) == CONST_DOUBLE
)
4294 /* gpr <- integer/floating constant */
4295 HOST_WIDE_INT value
;
4297 if (GET_CODE (src
) == CONST_INT
)
4298 value
= INTVAL (src
);
4300 else if (mode
== SFmode
)
4305 REAL_VALUE_FROM_CONST_DOUBLE (rv
, src
);
4306 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
4311 value
= CONST_DOUBLE_LOW (src
);
4313 if (IN_RANGE (value
, -32768, 32767))
4314 return "setlos %1, %0";
4319 else if (GET_CODE (src
) == SYMBOL_REF
4320 || GET_CODE (src
) == LABEL_REF
4321 || GET_CODE (src
) == CONST
)
4327 else if (FPR_P (dest_regno
))
4329 if (GET_CODE (src
) == REG
)
4331 /* fpr <- some sort of register */
4332 int src_regno
= REGNO (src
);
4334 if (GPR_P (src_regno
))
4335 return "movgf %1, %0";
4337 else if (FPR_P (src_regno
))
4339 if (TARGET_HARD_FLOAT
)
4340 return "fmovs %1, %0";
4342 return "mor %1, %1, %0";
4346 else if (GET_CODE (src
) == MEM
)
4355 return "ldbf%I1%U1 %M1,%0";
4358 return "ldhf%I1%U1 %M1,%0";
4362 return "ldf%I1%U1 %M1, %0";
4366 else if (ZERO_P (src
))
4367 return "movgf %., %0";
4370 else if (SPR_P (dest_regno
))
4372 if (GET_CODE (src
) == REG
)
4374 /* spr <- some sort of register */
4375 int src_regno
= REGNO (src
);
4377 if (GPR_P (src_regno
))
4378 return "movgs %1, %0";
4380 else if (ZERO_P (src
))
4381 return "movgs %., %0";
4385 else if (GET_CODE (dest
) == MEM
)
4387 if (GET_CODE (src
) == REG
)
4389 int src_regno
= REGNO (src
);
4390 enum machine_mode mode
= GET_MODE (dest
);
4392 if (GPR_P (src_regno
))
4400 return "stb%I0%U0 %1, %M0";
4403 return "sth%I0%U0 %1, %M0";
4407 return "st%I0%U0 %1, %M0";
4411 else if (FPR_P (src_regno
))
4419 return "stbf%I0%U0 %1, %M0";
4422 return "sthf%I0%U0 %1, %M0";
4426 return "stf%I0%U0 %1, %M0";
4431 else if (ZERO_P (src
))
4433 switch (GET_MODE (dest
))
4439 return "stb%I0%U0 %., %M0";
4442 return "sth%I0%U0 %., %M0";
4446 return "st%I0%U0 %., %M0";
4451 fatal_insn ("bad output_move_single operand", insn
);
4456 /* Return a string to output a double word move. */
4459 output_move_double (rtx operands
[], rtx insn
)
4461 rtx dest
= operands
[0];
4462 rtx src
= operands
[1];
4463 enum machine_mode mode
= GET_MODE (dest
);
4465 if (GET_CODE (dest
) == REG
)
4467 int dest_regno
= REGNO (dest
);
4469 if (GPR_P (dest_regno
))
4471 if (GET_CODE (src
) == REG
)
4473 /* gpr <- some sort of register */
4474 int src_regno
= REGNO (src
);
4476 if (GPR_P (src_regno
))
4479 else if (FPR_P (src_regno
))
4481 if (((dest_regno
- GPR_FIRST
) & 1) == 0
4482 && ((src_regno
- FPR_FIRST
) & 1) == 0)
4483 return "movfgd %1, %0";
4489 else if (GET_CODE (src
) == MEM
)
4492 if (dbl_memory_one_insn_operand (src
, mode
))
4493 return "ldd%I1%U1 %M1, %0";
4498 else if (GET_CODE (src
) == CONST_INT
4499 || GET_CODE (src
) == CONST_DOUBLE
)
4503 else if (FPR_P (dest_regno
))
4505 if (GET_CODE (src
) == REG
)
4507 /* fpr <- some sort of register */
4508 int src_regno
= REGNO (src
);
4510 if (GPR_P (src_regno
))
4512 if (((dest_regno
- FPR_FIRST
) & 1) == 0
4513 && ((src_regno
- GPR_FIRST
) & 1) == 0)
4514 return "movgfd %1, %0";
4519 else if (FPR_P (src_regno
))
4522 && ((dest_regno
- FPR_FIRST
) & 1) == 0
4523 && ((src_regno
- FPR_FIRST
) & 1) == 0)
4524 return "fmovd %1, %0";
4530 else if (GET_CODE (src
) == MEM
)
4533 if (dbl_memory_one_insn_operand (src
, mode
))
4534 return "lddf%I1%U1 %M1, %0";
4539 else if (ZERO_P (src
))
4544 else if (GET_CODE (dest
) == MEM
)
4546 if (GET_CODE (src
) == REG
)
4548 int src_regno
= REGNO (src
);
4550 if (GPR_P (src_regno
))
4552 if (((src_regno
- GPR_FIRST
) & 1) == 0
4553 && dbl_memory_one_insn_operand (dest
, mode
))
4554 return "std%I0%U0 %1, %M0";
4559 if (FPR_P (src_regno
))
4561 if (((src_regno
- FPR_FIRST
) & 1) == 0
4562 && dbl_memory_one_insn_operand (dest
, mode
))
4563 return "stdf%I0%U0 %1, %M0";
4569 else if (ZERO_P (src
))
4571 if (dbl_memory_one_insn_operand (dest
, mode
))
4572 return "std%I0%U0 %., %M0";
4578 fatal_insn ("bad output_move_double operand", insn
);
4583 /* Return a string to output a single word conditional move.
4584 Operand0 -- EQ/NE of ccr register and 0
4585 Operand1 -- CCR register
4586 Operand2 -- destination
4587 Operand3 -- source */
4590 output_condmove_single (rtx operands
[], rtx insn
)
4592 rtx dest
= operands
[2];
4593 rtx src
= operands
[3];
4595 if (GET_CODE (dest
) == REG
)
4597 int dest_regno
= REGNO (dest
);
4598 enum machine_mode mode
= GET_MODE (dest
);
4600 if (GPR_P (dest_regno
))
4602 if (GET_CODE (src
) == REG
)
4604 /* gpr <- some sort of register */
4605 int src_regno
= REGNO (src
);
4607 if (GPR_P (src_regno
))
4608 return "cmov %z3, %2, %1, %e0";
4610 else if (FPR_P (src_regno
))
4611 return "cmovfg %3, %2, %1, %e0";
4614 else if (GET_CODE (src
) == MEM
)
4623 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4626 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4630 return "cld%I3%U3 %M3, %2, %1, %e0";
4634 else if (ZERO_P (src
))
4635 return "cmov %., %2, %1, %e0";
4638 else if (FPR_P (dest_regno
))
4640 if (GET_CODE (src
) == REG
)
4642 /* fpr <- some sort of register */
4643 int src_regno
= REGNO (src
);
4645 if (GPR_P (src_regno
))
4646 return "cmovgf %3, %2, %1, %e0";
4648 else if (FPR_P (src_regno
))
4650 if (TARGET_HARD_FLOAT
)
4651 return "cfmovs %3,%2,%1,%e0";
4653 return "cmor %3, %3, %2, %1, %e0";
4657 else if (GET_CODE (src
) == MEM
)
4660 if (mode
== SImode
|| mode
== SFmode
)
4661 return "cldf%I3%U3 %M3, %2, %1, %e0";
4664 else if (ZERO_P (src
))
4665 return "cmovgf %., %2, %1, %e0";
4669 else if (GET_CODE (dest
) == MEM
)
4671 if (GET_CODE (src
) == REG
)
4673 int src_regno
= REGNO (src
);
4674 enum machine_mode mode
= GET_MODE (dest
);
4676 if (GPR_P (src_regno
))
4684 return "cstb%I2%U2 %3, %M2, %1, %e0";
4687 return "csth%I2%U2 %3, %M2, %1, %e0";
4691 return "cst%I2%U2 %3, %M2, %1, %e0";
4695 else if (FPR_P (src_regno
) && (mode
== SImode
|| mode
== SFmode
))
4696 return "cstf%I2%U2 %3, %M2, %1, %e0";
4699 else if (ZERO_P (src
))
4701 enum machine_mode mode
= GET_MODE (dest
);
4708 return "cstb%I2%U2 %., %M2, %1, %e0";
4711 return "csth%I2%U2 %., %M2, %1, %e0";
4715 return "cst%I2%U2 %., %M2, %1, %e0";
4720 fatal_insn ("bad output_condmove_single operand", insn
);
4725 /* Emit the appropriate code to do a comparison, returning the register the
4726 comparison was done it. */
4729 frv_emit_comparison (enum rtx_code test
, rtx op0
, rtx op1
)
4731 enum machine_mode cc_mode
;
4734 /* Floating point doesn't have comparison against a constant. */
4735 if (GET_MODE (op0
) == CC_FPmode
&& GET_CODE (op1
) != REG
)
4736 op1
= force_reg (GET_MODE (op0
), op1
);
4738 /* Possibly disable using anything but a fixed register in order to work
4739 around cse moving comparisons past function calls. */
4740 cc_mode
= SELECT_CC_MODE (test
, op0
, op1
);
4741 cc_reg
= ((TARGET_ALLOC_CC
)
4742 ? gen_reg_rtx (cc_mode
)
4743 : gen_rtx_REG (cc_mode
,
4744 (cc_mode
== CC_FPmode
) ? FCC_FIRST
: ICC_FIRST
));
4746 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
4747 gen_rtx_COMPARE (cc_mode
, op0
, op1
)));
4753 /* Emit code for a conditional branch.
4754 XXX: I originally wanted to add a clobber of a CCR register to use in
4755 conditional execution, but that confuses the rest of the compiler. */
4758 frv_emit_cond_branch (rtx operands
[])
4763 enum rtx_code test
= GET_CODE (operands
[0]);
4764 rtx cc_reg
= frv_emit_comparison (test
, operands
[1], operands
[2]);
4765 enum machine_mode cc_mode
= GET_MODE (cc_reg
);
4767 /* Branches generate:
4769 (if_then_else (<test>, <cc_reg>, (const_int 0))
4770 (label_ref <branch_label>)
4772 label_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
4773 test_rtx
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
4774 if_else
= gen_rtx_IF_THEN_ELSE (cc_mode
, test_rtx
, label_ref
, pc_rtx
);
4775 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, if_else
));
4780 /* Emit code to set a gpr to 1/0 based on a comparison. */
4783 frv_emit_scc (rtx operands
[])
4789 enum rtx_code test
= GET_CODE (operands
[1]);
4790 rtx cc_reg
= frv_emit_comparison (test
, operands
[2], operands
[3]);
4792 /* SCC instructions generate:
4793 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4794 (clobber (<ccr_reg>))]) */
4795 test_rtx
= gen_rtx_fmt_ee (test
, SImode
, cc_reg
, const0_rtx
);
4796 set
= gen_rtx_SET (VOIDmode
, operands
[0], test_rtx
);
4798 cr_reg
= ((TARGET_ALLOC_CC
)
4799 ? gen_reg_rtx (CC_CCRmode
)
4800 : gen_rtx_REG (CC_CCRmode
,
4801 ((GET_MODE (cc_reg
) == CC_FPmode
)
4805 clobber
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
4806 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
4811 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4812 the separate insns. */
4815 frv_split_scc (rtx dest
, rtx test
, rtx cc_reg
, rtx cr_reg
, HOST_WIDE_INT value
)
4821 /* Set the appropriate CCR bit. */
4822 emit_insn (gen_rtx_SET (VOIDmode
,
4824 gen_rtx_fmt_ee (GET_CODE (test
),
4829 /* Move the value into the destination. */
4830 emit_move_insn (dest
, GEN_INT (value
));
4832 /* Move 0 into the destination if the test failed */
4833 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4834 gen_rtx_EQ (GET_MODE (cr_reg
),
4837 gen_rtx_SET (VOIDmode
, dest
, const0_rtx
)));
4839 /* Finish up, return sequence. */
4846 /* Emit the code for a conditional move, return TRUE if we could do the
4850 frv_emit_cond_move (rtx dest
, rtx test_rtx
, rtx src1
, rtx src2
)
4857 enum rtx_code test
= GET_CODE (test_rtx
);
4858 rtx cc_reg
= frv_emit_comparison (test
,
4859 XEXP (test_rtx
, 0), XEXP (test_rtx
, 1));
4860 enum machine_mode cc_mode
= GET_MODE (cc_reg
);
4862 /* Conditional move instructions generate:
4863 (parallel [(set <target>
4864 (if_then_else (<test> <cc_reg> (const_int 0))
4867 (clobber (<ccr_reg>))]) */
4869 /* Handle various cases of conditional move involving two constants. */
4870 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
4872 HOST_WIDE_INT value1
= INTVAL (src1
);
4873 HOST_WIDE_INT value2
= INTVAL (src2
);
4875 /* Having 0 as one of the constants can be done by loading the other
4876 constant, and optionally moving in gr0. */
4877 if (value1
== 0 || value2
== 0)
4880 /* If the first value is within an addi range and also the difference
4881 between the two fits in an addi's range, load up the difference, then
4882 conditionally move in 0, and then unconditionally add the first
4884 else if (IN_RANGE (value1
, -2048, 2047)
4885 && IN_RANGE (value2
- value1
, -2048, 2047))
4888 /* If neither condition holds, just force the constant into a
4892 src1
= force_reg (GET_MODE (dest
), src1
);
4893 src2
= force_reg (GET_MODE (dest
), src2
);
4897 /* If one value is a register, insure the other value is either 0 or a
4901 if (GET_CODE (src1
) == CONST_INT
&& INTVAL (src1
) != 0)
4902 src1
= force_reg (GET_MODE (dest
), src1
);
4904 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
4905 src2
= force_reg (GET_MODE (dest
), src2
);
4908 test2
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
4909 if_rtx
= gen_rtx_IF_THEN_ELSE (GET_MODE (dest
), test2
, src1
, src2
);
4911 set
= gen_rtx_SET (VOIDmode
, dest
, if_rtx
);
4913 cr_reg
= ((TARGET_ALLOC_CC
)
4914 ? gen_reg_rtx (CC_CCRmode
)
4915 : gen_rtx_REG (CC_CCRmode
,
4916 (cc_mode
== CC_FPmode
) ? FCR_FIRST
: ICR_FIRST
));
4918 clobber_cc
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
4919 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber_cc
)));
4924 /* Split a conditional move into constituent parts, returning a SEQUENCE
4925 containing all of the insns. */
4928 frv_split_cond_move (rtx operands
[])
4930 rtx dest
= operands
[0];
4931 rtx test
= operands
[1];
4932 rtx cc_reg
= operands
[2];
4933 rtx src1
= operands
[3];
4934 rtx src2
= operands
[4];
4935 rtx cr_reg
= operands
[5];
4937 enum machine_mode cr_mode
= GET_MODE (cr_reg
);
4941 /* Set the appropriate CCR bit. */
4942 emit_insn (gen_rtx_SET (VOIDmode
,
4944 gen_rtx_fmt_ee (GET_CODE (test
),
4949 /* Handle various cases of conditional move involving two constants. */
4950 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
4952 HOST_WIDE_INT value1
= INTVAL (src1
);
4953 HOST_WIDE_INT value2
= INTVAL (src2
);
4955 /* Having 0 as one of the constants can be done by loading the other
4956 constant, and optionally moving in gr0. */
4959 emit_move_insn (dest
, src2
);
4960 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4961 gen_rtx_NE (cr_mode
, cr_reg
,
4963 gen_rtx_SET (VOIDmode
, dest
, src1
)));
4966 else if (value2
== 0)
4968 emit_move_insn (dest
, src1
);
4969 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4970 gen_rtx_EQ (cr_mode
, cr_reg
,
4972 gen_rtx_SET (VOIDmode
, dest
, src2
)));
4975 /* If the first value is within an addi range and also the difference
4976 between the two fits in an addi's range, load up the difference, then
4977 conditionally move in 0, and then unconditionally add the first
4979 else if (IN_RANGE (value1
, -2048, 2047)
4980 && IN_RANGE (value2
- value1
, -2048, 2047))
4982 rtx dest_si
= ((GET_MODE (dest
) == SImode
)
4984 : gen_rtx_SUBREG (SImode
, dest
, 0));
4986 emit_move_insn (dest_si
, GEN_INT (value2
- value1
));
4987 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4988 gen_rtx_NE (cr_mode
, cr_reg
,
4990 gen_rtx_SET (VOIDmode
, dest_si
,
4992 emit_insn (gen_addsi3 (dest_si
, dest_si
, src1
));
5000 /* Emit the conditional move for the test being true if needed. */
5001 if (! rtx_equal_p (dest
, src1
))
5002 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5003 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5004 gen_rtx_SET (VOIDmode
, dest
, src1
)));
5006 /* Emit the conditional move for the test being false if needed. */
5007 if (! rtx_equal_p (dest
, src2
))
5008 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5009 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
5010 gen_rtx_SET (VOIDmode
, dest
, src2
)));
5013 /* Finish up, return sequence. */
5020 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5021 memory location that is not known to be dword-aligned. */
5023 frv_split_double_load (rtx dest
, rtx source
)
5025 int regno
= REGNO (dest
);
5026 rtx dest1
= gen_highpart (SImode
, dest
);
5027 rtx dest2
= gen_lowpart (SImode
, dest
);
5028 rtx address
= XEXP (source
, 0);
5030 /* If the address is pre-modified, load the lower-numbered register
5031 first, then load the other register using an integer offset from
5032 the modified base register. This order should always be safe,
5033 since the pre-modification cannot affect the same registers as the
5036 The situation for other loads is more complicated. Loading one
5037 of the registers could affect the value of ADDRESS, so we must
5038 be careful which order we do them in. */
5039 if (GET_CODE (address
) == PRE_MODIFY
5040 || ! refers_to_regno_p (regno
, regno
+ 1, address
, NULL
))
5042 /* It is safe to load the lower-numbered register first. */
5043 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
5044 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
5048 /* ADDRESS is not pre-modified and the address depends on the
5049 lower-numbered register. Load the higher-numbered register
5051 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
5052 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
5056 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5057 and SOURCE is either a double register or the constant zero. */
5059 frv_split_double_store (rtx dest
, rtx source
)
5061 rtx dest1
= change_address (dest
, SImode
, NULL
);
5062 rtx dest2
= frv_index_memory (dest
, SImode
, 1);
5063 if (ZERO_P (source
))
5065 emit_move_insn (dest1
, CONST0_RTX (SImode
));
5066 emit_move_insn (dest2
, CONST0_RTX (SImode
));
5070 emit_move_insn (dest1
, gen_highpart (SImode
, source
));
5071 emit_move_insn (dest2
, gen_lowpart (SImode
, source
));
5076 /* Split a min/max operation returning a SEQUENCE containing all of the
5080 frv_split_minmax (rtx operands
[])
5082 rtx dest
= operands
[0];
5083 rtx minmax
= operands
[1];
5084 rtx src1
= operands
[2];
5085 rtx src2
= operands
[3];
5086 rtx cc_reg
= operands
[4];
5087 rtx cr_reg
= operands
[5];
5089 enum rtx_code test_code
;
5090 enum machine_mode cr_mode
= GET_MODE (cr_reg
);
5094 /* Figure out which test to use. */
5095 switch (GET_CODE (minmax
))
5100 case SMIN
: test_code
= LT
; break;
5101 case SMAX
: test_code
= GT
; break;
5102 case UMIN
: test_code
= LTU
; break;
5103 case UMAX
: test_code
= GTU
; break;
5106 /* Issue the compare instruction. */
5107 emit_insn (gen_rtx_SET (VOIDmode
,
5109 gen_rtx_COMPARE (GET_MODE (cc_reg
),
5112 /* Set the appropriate CCR bit. */
5113 emit_insn (gen_rtx_SET (VOIDmode
,
5115 gen_rtx_fmt_ee (test_code
,
5120 /* If are taking the min/max of a nonzero constant, load that first, and
5121 then do a conditional move of the other value. */
5122 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
5124 gcc_assert (!rtx_equal_p (dest
, src1
));
5126 emit_move_insn (dest
, src2
);
5127 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5128 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5129 gen_rtx_SET (VOIDmode
, dest
, src1
)));
5132 /* Otherwise, do each half of the move. */
5135 /* Emit the conditional move for the test being true if needed. */
5136 if (! rtx_equal_p (dest
, src1
))
5137 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5138 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5139 gen_rtx_SET (VOIDmode
, dest
, src1
)));
5141 /* Emit the conditional move for the test being false if needed. */
5142 if (! rtx_equal_p (dest
, src2
))
5143 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5144 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
5145 gen_rtx_SET (VOIDmode
, dest
, src2
)));
5148 /* Finish up, return sequence. */
5155 /* Split an integer abs operation returning a SEQUENCE containing all of the
5159 frv_split_abs (rtx operands
[])
5161 rtx dest
= operands
[0];
5162 rtx src
= operands
[1];
5163 rtx cc_reg
= operands
[2];
5164 rtx cr_reg
= operands
[3];
5169 /* Issue the compare < 0 instruction. */
5170 emit_insn (gen_rtx_SET (VOIDmode
,
5172 gen_rtx_COMPARE (CCmode
, src
, const0_rtx
)));
5174 /* Set the appropriate CCR bit. */
5175 emit_insn (gen_rtx_SET (VOIDmode
,
5177 gen_rtx_fmt_ee (LT
, CC_CCRmode
, cc_reg
, const0_rtx
)));
5179 /* Emit the conditional negate if the value is negative. */
5180 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5181 gen_rtx_NE (CC_CCRmode
, cr_reg
, const0_rtx
),
5182 gen_negsi2 (dest
, src
)));
5184 /* Emit the conditional move for the test being false if needed. */
5185 if (! rtx_equal_p (dest
, src
))
5186 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5187 gen_rtx_EQ (CC_CCRmode
, cr_reg
, const0_rtx
),
5188 gen_rtx_SET (VOIDmode
, dest
, src
)));
5190 /* Finish up, return sequence. */
5197 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5198 register used in an insn. */
5201 frv_clear_registers_used (rtx
*ptr
, void *data
)
5203 if (GET_CODE (*ptr
) == REG
)
5205 int regno
= REGNO (*ptr
);
5206 HARD_REG_SET
*p_regs
= (HARD_REG_SET
*)data
;
5208 if (regno
< FIRST_PSEUDO_REGISTER
)
5210 int reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (*ptr
));
5212 while (regno
< reg_max
)
5214 CLEAR_HARD_REG_BIT (*p_regs
, regno
);
5224 /* Initialize machine-specific if-conversion data.
5225 On the FR-V, we don't have any extra fields per se, but it is useful hook to
5226 initialize the static storage. */
5228 frv_ifcvt_machdep_init (void *ce_info ATTRIBUTE_UNUSED
)
5230 frv_ifcvt
.added_insns_list
= NULL_RTX
;
5231 frv_ifcvt
.cur_scratch_regs
= 0;
5232 frv_ifcvt
.num_nested_cond_exec
= 0;
5233 frv_ifcvt
.cr_reg
= NULL_RTX
;
5234 frv_ifcvt
.nested_cc_reg
= NULL_RTX
;
5235 frv_ifcvt
.extra_int_cr
= NULL_RTX
;
5236 frv_ifcvt
.extra_fp_cr
= NULL_RTX
;
5237 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
5241 /* Internal function to add a potential insn to the list of insns to be inserted
5242 if the conditional execution conversion is successful. */
5245 frv_ifcvt_add_insn (rtx pattern
, rtx insn
, int before_p
)
5247 rtx link
= alloc_EXPR_LIST (VOIDmode
, pattern
, insn
);
5249 link
->jump
= before_p
; /* Mark to add this before or after insn. */
5250 frv_ifcvt
.added_insns_list
= alloc_EXPR_LIST (VOIDmode
, link
,
5251 frv_ifcvt
.added_insns_list
);
5253 if (TARGET_DEBUG_COND_EXEC
)
5256 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5257 (before_p
) ? "before" : "after",
5258 (int)INSN_UID (insn
));
5260 debug_rtx (pattern
);
5265 /* A C expression to modify the code described by the conditional if
5266 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5267 FALSE_EXPR for converting if-then and if-then-else code to conditional
5268 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5269 tests cannot be converted. */
5272 frv_ifcvt_modify_tests (ce_if_block_t
*ce_info
, rtx
*p_true
, rtx
*p_false
)
5274 basic_block test_bb
= ce_info
->test_bb
; /* test basic block */
5275 basic_block then_bb
= ce_info
->then_bb
; /* THEN */
5276 basic_block else_bb
= ce_info
->else_bb
; /* ELSE or NULL */
5277 basic_block join_bb
= ce_info
->join_bb
; /* join block or NULL */
5278 rtx true_expr
= *p_true
;
5282 enum machine_mode mode
= GET_MODE (true_expr
);
5286 frv_tmp_reg_t
*tmp_reg
= &frv_ifcvt
.tmp_reg
;
5288 rtx sub_cond_exec_reg
;
5290 enum rtx_code code_true
;
5291 enum rtx_code code_false
;
5292 enum reg_class cc_class
;
5293 enum reg_class cr_class
;
5296 reg_set_iterator rsi
;
5298 /* Make sure we are only dealing with hard registers. Also honor the
5299 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5301 if (!reload_completed
|| !TARGET_COND_EXEC
5302 || (!TARGET_NESTED_CE
&& ce_info
->pass
> 1))
5305 /* Figure out which registers we can allocate for our own purposes. Only
5306 consider registers that are not preserved across function calls and are
5307 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5308 if we did not need to use them in reloading other registers. */
5309 memset (&tmp_reg
->regs
, 0, sizeof (tmp_reg
->regs
));
5310 COPY_HARD_REG_SET (tmp_reg
->regs
, call_used_reg_set
);
5311 AND_COMPL_HARD_REG_SET (tmp_reg
->regs
, fixed_reg_set
);
5312 SET_HARD_REG_BIT (tmp_reg
->regs
, ICC_TEMP
);
5313 SET_HARD_REG_BIT (tmp_reg
->regs
, ICR_TEMP
);
5315 /* If this is a nested IF, we need to discover whether the CC registers that
5316 are set/used inside of the block are used anywhere else. If not, we can
5317 change them to be the CC register that is paired with the CR register that
5318 controls the outermost IF block. */
5319 if (ce_info
->pass
> 1)
5321 CLEAR_HARD_REG_SET (frv_ifcvt
.nested_cc_ok_rewrite
);
5322 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5323 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5325 if (REGNO_REG_SET_P (df_get_live_in (then_bb
), j
))
5329 && REGNO_REG_SET_P (df_get_live_in (else_bb
), j
))
5333 && REGNO_REG_SET_P (df_get_live_in (join_bb
), j
))
5336 SET_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
);
5340 for (j
= 0; j
< frv_ifcvt
.cur_scratch_regs
; j
++)
5341 frv_ifcvt
.scratch_regs
[j
] = NULL_RTX
;
5343 frv_ifcvt
.added_insns_list
= NULL_RTX
;
5344 frv_ifcvt
.cur_scratch_regs
= 0;
5346 bb
= (basic_block
*) alloca ((2 + ce_info
->num_multiple_test_blocks
)
5347 * sizeof (basic_block
));
5353 /* Remove anything live at the beginning of the join block from being
5354 available for allocation. */
5355 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb
), 0, regno
, rsi
)
5357 if (regno
< FIRST_PSEUDO_REGISTER
)
5358 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
5362 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5364 if (ce_info
->num_multiple_test_blocks
)
5366 basic_block multiple_test_bb
= ce_info
->last_test_bb
;
5368 while (multiple_test_bb
!= test_bb
)
5370 bb
[num_bb
++] = multiple_test_bb
;
5371 multiple_test_bb
= EDGE_PRED (multiple_test_bb
, 0)->src
;
5375 /* Add in the THEN and ELSE blocks to be scanned. */
5376 bb
[num_bb
++] = then_bb
;
5378 bb
[num_bb
++] = else_bb
;
5380 sub_cond_exec_reg
= NULL_RTX
;
5381 frv_ifcvt
.num_nested_cond_exec
= 0;
5383 /* Scan all of the blocks for registers that must not be allocated. */
5384 for (j
= 0; j
< num_bb
; j
++)
5386 rtx last_insn
= BB_END (bb
[j
]);
5387 rtx insn
= BB_HEAD (bb
[j
]);
5391 fprintf (dump_file
, "Scanning %s block %d, start %d, end %d\n",
5392 (bb
[j
] == else_bb
) ? "else" : ((bb
[j
] == then_bb
) ? "then" : "test"),
5394 (int) INSN_UID (BB_HEAD (bb
[j
])),
5395 (int) INSN_UID (BB_END (bb
[j
])));
5397 /* Anything live at the beginning of the block is obviously unavailable
5399 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb
[j
]), 0, regno
, rsi
)
5401 if (regno
< FIRST_PSEUDO_REGISTER
)
5402 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
5405 /* Loop through the insns in the block. */
5408 /* Mark any new registers that are created as being unavailable for
5409 allocation. Also see if the CC register used in nested IFs can be
5415 int skip_nested_if
= FALSE
;
5417 for_each_rtx (&PATTERN (insn
), frv_clear_registers_used
,
5418 (void *)&tmp_reg
->regs
);
5420 pattern
= PATTERN (insn
);
5421 if (GET_CODE (pattern
) == COND_EXEC
)
5423 rtx reg
= XEXP (COND_EXEC_TEST (pattern
), 0);
5425 if (reg
!= sub_cond_exec_reg
)
5427 sub_cond_exec_reg
= reg
;
5428 frv_ifcvt
.num_nested_cond_exec
++;
5432 set
= single_set_pattern (pattern
);
5435 rtx dest
= SET_DEST (set
);
5436 rtx src
= SET_SRC (set
);
5438 if (GET_CODE (dest
) == REG
)
5440 int regno
= REGNO (dest
);
5441 enum rtx_code src_code
= GET_CODE (src
);
5443 if (CC_P (regno
) && src_code
== COMPARE
)
5444 skip_nested_if
= TRUE
;
5446 else if (CR_P (regno
)
5447 && (src_code
== IF_THEN_ELSE
5448 || COMPARISON_P (src
)))
5449 skip_nested_if
= TRUE
;
5453 if (! skip_nested_if
)
5454 for_each_rtx (&PATTERN (insn
), frv_clear_registers_used
,
5455 (void *)&frv_ifcvt
.nested_cc_ok_rewrite
);
5458 if (insn
== last_insn
)
5461 insn
= NEXT_INSN (insn
);
5465 /* If this is a nested if, rewrite the CC registers that are available to
5466 include the ones that can be rewritten, to increase the chance of being
5467 able to allocate a paired CC/CR register combination. */
5468 if (ce_info
->pass
> 1)
5470 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5471 if (TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
))
5472 SET_HARD_REG_BIT (tmp_reg
->regs
, j
);
5474 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, j
);
5480 fprintf (dump_file
, "Available GPRs: ");
5482 for (j
= GPR_FIRST
; j
<= GPR_LAST
; j
++)
5483 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5485 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5486 if (++num_gprs
> GPR_TEMP_NUM
+2)
5490 fprintf (dump_file
, "%s\nAvailable CRs: ",
5491 (num_gprs
> GPR_TEMP_NUM
+2) ? " ..." : "");
5493 for (j
= CR_FIRST
; j
<= CR_LAST
; j
++)
5494 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5495 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5497 fputs ("\n", dump_file
);
5499 if (ce_info
->pass
> 1)
5501 fprintf (dump_file
, "Modifiable CCs: ");
5502 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5503 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5504 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5506 fprintf (dump_file
, "\n%d nested COND_EXEC statements\n",
5507 frv_ifcvt
.num_nested_cond_exec
);
5511 /* Allocate the appropriate temporary condition code register. Try to
5512 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5513 that conditional cmp's can be done. */
5514 if (mode
== CCmode
|| mode
== CC_UNSmode
|| mode
== CC_NZmode
)
5516 cr_class
= ICR_REGS
;
5517 cc_class
= ICC_REGS
;
5518 cc_first
= ICC_FIRST
;
5521 else if (mode
== CC_FPmode
)
5523 cr_class
= FCR_REGS
;
5524 cc_class
= FCC_REGS
;
5525 cc_first
= FCC_FIRST
;
5530 cc_first
= cc_last
= 0;
5531 cr_class
= cc_class
= NO_REGS
;
5534 cc
= XEXP (true_expr
, 0);
5535 nested_cc
= cr
= NULL_RTX
;
5536 if (cc_class
!= NO_REGS
)
5538 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5539 so we can execute a csubcc/caddcc/cfcmps instruction. */
5542 for (cc_regno
= cc_first
; cc_regno
<= cc_last
; cc_regno
++)
5544 int cr_regno
= cc_regno
- CC_FIRST
+ CR_FIRST
;
5546 if (TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cc_regno
)
5547 && TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cr_regno
))
5549 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cr_class
] = cr_regno
;
5550 cr
= frv_alloc_temp_reg (tmp_reg
, cr_class
, CC_CCRmode
, TRUE
,
5553 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cc_class
] = cc_regno
;
5554 nested_cc
= frv_alloc_temp_reg (tmp_reg
, cc_class
, CCmode
,
5564 fprintf (dump_file
, "Could not allocate a CR temporary register\n");
5571 "Will use %s for conditional execution, %s for nested comparisons\n",
5572 reg_names
[ REGNO (cr
)],
5573 (nested_cc
) ? reg_names
[ REGNO (nested_cc
) ] : "<none>");
5575 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5576 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5577 bit being true. We don't do this for floating point, because of NaNs. */
5578 code
= GET_CODE (true_expr
);
5579 if (GET_MODE (cc
) != CC_FPmode
)
5581 code
= reverse_condition (code
);
5591 check_insn
= gen_rtx_SET (VOIDmode
, cr
,
5592 gen_rtx_fmt_ee (code
, CC_CCRmode
, cc
, const0_rtx
));
5594 /* Record the check insn to be inserted later. */
5595 frv_ifcvt_add_insn (check_insn
, BB_END (test_bb
), TRUE
);
5597 /* Update the tests. */
5598 frv_ifcvt
.cr_reg
= cr
;
5599 frv_ifcvt
.nested_cc_reg
= nested_cc
;
5600 *p_true
= gen_rtx_fmt_ee (code_true
, CC_CCRmode
, cr
, const0_rtx
);
5601 *p_false
= gen_rtx_fmt_ee (code_false
, CC_CCRmode
, cr
, const0_rtx
);
5604 /* Fail, don't do this conditional execution. */
5607 *p_false
= NULL_RTX
;
5609 fprintf (dump_file
, "Disabling this conditional execution.\n");
5615 /* A C expression to modify the code described by the conditional if
5616 information CE_INFO, for the basic block BB, possibly updating the tests in
5617 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5618 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5619 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5621 /* p_true and p_false are given expressions of the form:
5623 (and (eq:CC_CCR (reg:CC_CCR)
5629 frv_ifcvt_modify_multiple_tests (ce_if_block_t
*ce_info
,
5634 rtx old_true
= XEXP (*p_true
, 0);
5635 rtx old_false
= XEXP (*p_false
, 0);
5636 rtx true_expr
= XEXP (*p_true
, 1);
5637 rtx false_expr
= XEXP (*p_false
, 1);
5640 rtx cr
= XEXP (old_true
, 0);
5642 rtx new_cr
= NULL_RTX
;
5643 rtx
*p_new_cr
= (rtx
*)0;
5647 enum reg_class cr_class
;
5648 enum machine_mode mode
= GET_MODE (true_expr
);
5649 rtx (*logical_func
)(rtx
, rtx
, rtx
);
5651 if (TARGET_DEBUG_COND_EXEC
)
5654 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5655 ce_info
->and_and_p
? "&&" : "||");
5657 debug_rtx (*p_true
);
5659 fputs ("\nfalse insn:\n", stderr
);
5660 debug_rtx (*p_false
);
5663 if (!TARGET_MULTI_CE
)
5666 if (GET_CODE (cr
) != REG
)
5669 if (mode
== CCmode
|| mode
== CC_UNSmode
|| mode
== CC_NZmode
)
5671 cr_class
= ICR_REGS
;
5672 p_new_cr
= &frv_ifcvt
.extra_int_cr
;
5674 else if (mode
== CC_FPmode
)
5676 cr_class
= FCR_REGS
;
5677 p_new_cr
= &frv_ifcvt
.extra_fp_cr
;
5682 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5683 more &&/|| tests. */
5687 new_cr
= *p_new_cr
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, cr_class
,
5688 CC_CCRmode
, TRUE
, TRUE
);
5693 if (ce_info
->and_and_p
)
5695 old_test
= old_false
;
5696 test_expr
= true_expr
;
5697 logical_func
= (GET_CODE (old_true
) == EQ
) ? gen_andcr
: gen_andncr
;
5698 *p_true
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
5699 *p_false
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
5703 old_test
= old_false
;
5704 test_expr
= false_expr
;
5705 logical_func
= (GET_CODE (old_false
) == EQ
) ? gen_orcr
: gen_orncr
;
5706 *p_true
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
5707 *p_false
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
5710 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5711 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5713 frv_ifcvt_add_insn ((*logical_func
) (cr
, cr
, new_cr
), BB_END (bb
), TRUE
);
5715 /* Now add the conditional check insn. */
5716 cc
= XEXP (test_expr
, 0);
5717 compare
= gen_rtx_fmt_ee (GET_CODE (test_expr
), CC_CCRmode
, cc
, const0_rtx
);
5718 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, old_test
, compare
, const0_rtx
);
5720 check_insn
= gen_rtx_SET (VOIDmode
, new_cr
, if_else
);
5722 /* Add the new check insn to the list of check insns that need to be
5724 frv_ifcvt_add_insn (check_insn
, BB_END (bb
), TRUE
);
5726 if (TARGET_DEBUG_COND_EXEC
)
5728 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5731 debug_rtx (*p_true
);
5733 fputs ("\nfalse insn:\n", stderr
);
5734 debug_rtx (*p_false
);
5740 *p_true
= *p_false
= NULL_RTX
;
5742 /* If we allocated a CR register, release it. */
5745 CLEAR_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, REGNO (new_cr
));
5746 *p_new_cr
= NULL_RTX
;
5749 if (TARGET_DEBUG_COND_EXEC
)
5750 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr
);
5756 /* Return a register which will be loaded with a value if an IF block is
5757 converted to conditional execution. This is used to rewrite instructions
5758 that use constants to ones that just use registers. */
5761 frv_ifcvt_load_value (rtx value
, rtx insn ATTRIBUTE_UNUSED
)
5763 int num_alloc
= frv_ifcvt
.cur_scratch_regs
;
5767 /* We know gr0 == 0, so replace any errant uses. */
5768 if (value
== const0_rtx
)
5769 return gen_rtx_REG (SImode
, GPR_FIRST
);
5771 /* First search all registers currently loaded to see if we have an
5772 applicable constant. */
5773 if (CONSTANT_P (value
)
5774 || (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
))
5776 for (i
= 0; i
< num_alloc
; i
++)
5778 if (rtx_equal_p (SET_SRC (frv_ifcvt
.scratch_regs
[i
]), value
))
5779 return SET_DEST (frv_ifcvt
.scratch_regs
[i
]);
5783 /* Have we exhausted the number of registers available? */
5784 if (num_alloc
>= GPR_TEMP_NUM
)
5787 fprintf (dump_file
, "Too many temporary registers allocated\n");
5792 /* Allocate the new register. */
5793 reg
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, GPR_REGS
, SImode
, TRUE
, TRUE
);
5797 fputs ("Could not find a scratch register\n", dump_file
);
5802 frv_ifcvt
.cur_scratch_regs
++;
5803 frv_ifcvt
.scratch_regs
[num_alloc
] = gen_rtx_SET (VOIDmode
, reg
, value
);
5807 if (GET_CODE (value
) == CONST_INT
)
5808 fprintf (dump_file
, "Register %s will hold %ld\n",
5809 reg_names
[ REGNO (reg
)], (long)INTVAL (value
));
5811 else if (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
)
5812 fprintf (dump_file
, "Register %s will hold LR\n",
5813 reg_names
[ REGNO (reg
)]);
5816 fprintf (dump_file
, "Register %s will hold a saved value\n",
5817 reg_names
[ REGNO (reg
)]);
5824 /* Update a MEM used in conditional code that might contain an offset to put
5825 the offset into a scratch register, so that the conditional load/store
5826 operations can be used. This function returns the original pointer if the
5827 MEM is valid to use in conditional code, NULL if we can't load up the offset
5828 into a temporary register, or the new MEM if we were successful. */
5831 frv_ifcvt_rewrite_mem (rtx mem
, enum machine_mode mode
, rtx insn
)
5833 rtx addr
= XEXP (mem
, 0);
5835 if (!frv_legitimate_address_p_1 (mode
, addr
, reload_completed
, TRUE
, FALSE
))
5837 if (GET_CODE (addr
) == PLUS
)
5839 rtx addr_op0
= XEXP (addr
, 0);
5840 rtx addr_op1
= XEXP (addr
, 1);
5842 if (GET_CODE (addr_op0
) == REG
&& CONSTANT_P (addr_op1
))
5844 rtx reg
= frv_ifcvt_load_value (addr_op1
, insn
);
5848 addr
= gen_rtx_PLUS (Pmode
, addr_op0
, reg
);
5855 else if (CONSTANT_P (addr
))
5856 addr
= frv_ifcvt_load_value (addr
, insn
);
5861 if (addr
== NULL_RTX
)
5864 else if (XEXP (mem
, 0) != addr
)
5865 return change_address (mem
, mode
, addr
);
5872 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5873 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5876 single_set_pattern (rtx pattern
)
5881 if (GET_CODE (pattern
) == COND_EXEC
)
5882 pattern
= COND_EXEC_CODE (pattern
);
5884 if (GET_CODE (pattern
) == SET
)
5887 else if (GET_CODE (pattern
) == PARALLEL
)
5889 for (i
= 0, set
= 0; i
< XVECLEN (pattern
, 0); i
++)
5891 rtx sub
= XVECEXP (pattern
, 0, i
);
5893 switch (GET_CODE (sub
))
5917 /* A C expression to modify the code described by the conditional if
5918 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5919 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5920 insn cannot be converted to be executed conditionally. */
5923 frv_ifcvt_modify_insn (ce_if_block_t
*ce_info
,
5927 rtx orig_ce_pattern
= pattern
;
5933 gcc_assert (GET_CODE (pattern
) == COND_EXEC
);
5935 test
= COND_EXEC_TEST (pattern
);
5936 if (GET_CODE (test
) == AND
)
5938 rtx cr
= frv_ifcvt
.cr_reg
;
5941 op0
= XEXP (test
, 0);
5942 if (! rtx_equal_p (cr
, XEXP (op0
, 0)))
5945 op1
= XEXP (test
, 1);
5946 test_reg
= XEXP (op1
, 0);
5947 if (GET_CODE (test_reg
) != REG
)
5950 /* Is this the first nested if block in this sequence? If so, generate
5951 an andcr or andncr. */
5952 if (! frv_ifcvt
.last_nested_if_cr
)
5956 frv_ifcvt
.last_nested_if_cr
= test_reg
;
5957 if (GET_CODE (op0
) == NE
)
5958 and_op
= gen_andcr (test_reg
, cr
, test_reg
);
5960 and_op
= gen_andncr (test_reg
, cr
, test_reg
);
5962 frv_ifcvt_add_insn (and_op
, insn
, TRUE
);
5965 /* If this isn't the first statement in the nested if sequence, see if we
5966 are dealing with the same register. */
5967 else if (! rtx_equal_p (test_reg
, frv_ifcvt
.last_nested_if_cr
))
5970 COND_EXEC_TEST (pattern
) = test
= op1
;
5973 /* If this isn't a nested if, reset state variables. */
5976 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
5979 set
= single_set_pattern (pattern
);
5982 rtx dest
= SET_DEST (set
);
5983 rtx src
= SET_SRC (set
);
5984 enum machine_mode mode
= GET_MODE (dest
);
5986 /* Check for normal binary operators. */
5987 if (mode
== SImode
&& ARITHMETIC_P (src
))
5989 op0
= XEXP (src
, 0);
5990 op1
= XEXP (src
, 1);
5992 if (integer_register_operand (op0
, SImode
) && CONSTANT_P (op1
))
5994 op1
= frv_ifcvt_load_value (op1
, insn
);
5996 COND_EXEC_CODE (pattern
)
5997 = gen_rtx_SET (VOIDmode
, dest
, gen_rtx_fmt_ee (GET_CODE (src
),
6005 /* For multiply by a constant, we need to handle the sign extending
6006 correctly. Add a USE of the value after the multiply to prevent flow
6007 from cratering because only one register out of the two were used. */
6008 else if (mode
== DImode
&& GET_CODE (src
) == MULT
)
6010 op0
= XEXP (src
, 0);
6011 op1
= XEXP (src
, 1);
6012 if (GET_CODE (op0
) == SIGN_EXTEND
&& GET_CODE (op1
) == CONST_INT
)
6014 op1
= frv_ifcvt_load_value (op1
, insn
);
6017 op1
= gen_rtx_SIGN_EXTEND (DImode
, op1
);
6018 COND_EXEC_CODE (pattern
)
6019 = gen_rtx_SET (VOIDmode
, dest
,
6020 gen_rtx_MULT (DImode
, op0
, op1
));
6026 frv_ifcvt_add_insn (gen_use (dest
), insn
, FALSE
);
6029 /* If we are just loading a constant created for a nested conditional
6030 execution statement, just load the constant without any conditional
6031 execution, since we know that the constant will not interfere with any
6033 else if (frv_ifcvt
.scratch_insns_bitmap
6034 && bitmap_bit_p (frv_ifcvt
.scratch_insns_bitmap
,
6036 && REG_P (SET_DEST (set
))
6037 /* We must not unconditionally set a scratch reg chosen
6038 for a nested if-converted block if its incoming
6039 value from the TEST block (or the result of the THEN
6040 branch) could/should propagate to the JOIN block.
6041 It suffices to test whether the register is live at
6042 the JOIN point: if it's live there, we can infer
6043 that we set it in the former JOIN block of the
6044 nested if-converted block (otherwise it wouldn't
6045 have been available as a scratch register), and it
6046 is either propagated through or set in the other
6047 conditional block. It's probably not worth trying
6048 to catch the latter case, and it could actually
6049 limit scheduling of the combined block quite
6052 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info
->join_bb
),
6053 REGNO (SET_DEST (set
))))
6054 /* Similarly, we must not unconditionally set a reg
6055 used as scratch in the THEN branch if the same reg
6056 is live in the ELSE branch. */
6057 && (! ce_info
->else_bb
6058 || BLOCK_FOR_INSN (insn
) == ce_info
->else_bb
6059 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info
->else_bb
),
6060 REGNO (SET_DEST (set
))))))
6063 else if (mode
== QImode
|| mode
== HImode
|| mode
== SImode
6066 int changed_p
= FALSE
;
6068 /* Check for just loading up a constant */
6069 if (CONSTANT_P (src
) && integer_register_operand (dest
, mode
))
6071 src
= frv_ifcvt_load_value (src
, insn
);
6078 /* See if we need to fix up stores */
6079 if (GET_CODE (dest
) == MEM
)
6081 rtx new_mem
= frv_ifcvt_rewrite_mem (dest
, mode
, insn
);
6086 else if (new_mem
!= dest
)
6093 /* See if we need to fix up loads */
6094 if (GET_CODE (src
) == MEM
)
6096 rtx new_mem
= frv_ifcvt_rewrite_mem (src
, mode
, insn
);
6101 else if (new_mem
!= src
)
6108 /* If either src or destination changed, redo SET. */
6110 COND_EXEC_CODE (pattern
) = gen_rtx_SET (VOIDmode
, dest
, src
);
6113 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6114 rewriting the CC register to be the same as the paired CC/CR register
6116 else if (mode
== CC_CCRmode
&& COMPARISON_P (src
))
6118 int regno
= REGNO (XEXP (src
, 0));
6121 if (ce_info
->pass
> 1
6122 && regno
!= (int)REGNO (frv_ifcvt
.nested_cc_reg
)
6123 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, regno
))
6125 src
= gen_rtx_fmt_ee (GET_CODE (src
),
6127 frv_ifcvt
.nested_cc_reg
,
6131 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, test
, src
, const0_rtx
);
6132 pattern
= gen_rtx_SET (VOIDmode
, dest
, if_else
);
6135 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6136 else if (ce_info
->pass
> 1
6137 && GET_CODE (dest
) == REG
6138 && CC_P (REGNO (dest
))
6139 && REGNO (dest
) != REGNO (frv_ifcvt
.nested_cc_reg
)
6140 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
,
6142 && GET_CODE (src
) == COMPARE
)
6144 PUT_MODE (frv_ifcvt
.nested_cc_reg
, GET_MODE (dest
));
6145 COND_EXEC_CODE (pattern
)
6146 = gen_rtx_SET (VOIDmode
, frv_ifcvt
.nested_cc_reg
, copy_rtx (src
));
6150 if (TARGET_DEBUG_COND_EXEC
)
6152 rtx orig_pattern
= PATTERN (insn
);
6154 PATTERN (insn
) = pattern
;
6156 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6160 PATTERN (insn
) = orig_pattern
;
6166 if (TARGET_DEBUG_COND_EXEC
)
6168 rtx orig_pattern
= PATTERN (insn
);
6170 PATTERN (insn
) = orig_ce_pattern
;
6172 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6176 PATTERN (insn
) = orig_pattern
;
6183 /* A C expression to perform any final machine dependent modifications in
6184 converting code to conditional execution in the code described by the
6185 conditional if information CE_INFO. */
6188 frv_ifcvt_modify_final (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
6192 rtx p
= frv_ifcvt
.added_insns_list
;
6195 /* Loop inserting the check insns. The last check insn is the first test,
6196 and is the appropriate place to insert constants. */
6201 rtx check_and_insert_insns
= XEXP (p
, 0);
6204 check_insn
= XEXP (check_and_insert_insns
, 0);
6205 existing_insn
= XEXP (check_and_insert_insns
, 1);
6208 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6209 the existing insn, otherwise it is to be inserted AFTER. */
6210 if (check_and_insert_insns
->jump
)
6212 emit_insn_before (check_insn
, existing_insn
);
6213 check_and_insert_insns
->jump
= 0;
6216 emit_insn_after (check_insn
, existing_insn
);
6218 free_EXPR_LIST_node (check_and_insert_insns
);
6219 free_EXPR_LIST_node (old_p
);
6221 while (p
!= NULL_RTX
);
6223 /* Load up any constants needed into temp gprs */
6224 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
6226 rtx insn
= emit_insn_before (frv_ifcvt
.scratch_regs
[i
], existing_insn
);
6227 if (! frv_ifcvt
.scratch_insns_bitmap
)
6228 frv_ifcvt
.scratch_insns_bitmap
= BITMAP_ALLOC (NULL
);
6229 bitmap_set_bit (frv_ifcvt
.scratch_insns_bitmap
, INSN_UID (insn
));
6230 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
6233 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6234 frv_ifcvt
.cur_scratch_regs
= 0;
6238 /* A C expression to cancel any machine dependent modifications in converting
6239 code to conditional execution in the code described by the conditional if
6240 information CE_INFO. */
6243 frv_ifcvt_modify_cancel (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
6246 rtx p
= frv_ifcvt
.added_insns_list
;
6248 /* Loop freeing up the EXPR_LIST's allocated. */
6249 while (p
!= NULL_RTX
)
6251 rtx check_and_jump
= XEXP (p
, 0);
6255 free_EXPR_LIST_node (check_and_jump
);
6256 free_EXPR_LIST_node (old_p
);
6259 /* Release any temporary gprs allocated. */
6260 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
6261 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
6263 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6264 frv_ifcvt
.cur_scratch_regs
= 0;
6268 /* A C expression for the size in bytes of the trampoline, as an integer.
6272 setlo #0, <static_chain>
6274 sethi #0, <static_chain>
6275 jmpl @(gr0,<jmp_reg>) */
6278 frv_trampoline_size (void)
6281 /* Allocate room for the function descriptor and the lddi
6284 return 5 /* instructions */ * 4 /* instruction size. */;
6288 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6289 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6290 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6291 should be passed to the function when it is called.
6296 setlo #0, <static_chain>
6298 sethi #0, <static_chain>
6299 jmpl @(gr0,<jmp_reg>) */
6302 frv_trampoline_init (rtx m_tramp
, tree fndecl
, rtx static_chain
)
6304 rtx addr
= XEXP (m_tramp
, 0);
6305 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6306 rtx sc_reg
= force_reg (Pmode
, static_chain
);
6308 emit_library_call (gen_rtx_SYMBOL_REF (SImode
, "__trampoline_setup"),
6309 LCT_NORMAL
, VOIDmode
, 4,
6311 GEN_INT (frv_trampoline_size ()), SImode
,
6317 /* Many machines have some registers that cannot be copied directly to or from
6318 memory or even from other types of registers. An example is the `MQ'
6319 register, which on most machines, can only be copied to or from general
6320 registers, but not memory. Some machines allow copying all registers to and
6321 from memory, but require a scratch register for stores to some memory
6322 locations (e.g., those with symbolic address on the RT, and those with
6323 certain symbolic address on the SPARC when compiling PIC). In some cases,
6324 both an intermediate and a scratch register are required.
6326 You should define these macros to indicate to the reload phase that it may
6327 need to allocate at least one register for a reload in addition to the
6328 register to contain the data. Specifically, if copying X to a register
6329 RCLASS in MODE requires an intermediate register, you should define
6330 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6331 whose registers can be used as intermediate registers or scratch registers.
6333 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6334 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6335 largest register class required. If the requirements for input and output
6336 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6337 instead of defining both macros identically.
6339 The values returned by these macros are often `GENERAL_REGS'. Return
6340 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6341 to or from a register of RCLASS in MODE without requiring a scratch register.
6342 Do not define this macro if it would always return `NO_REGS'.
6344 If a scratch register is required (either with or without an intermediate
6345 register), you should define patterns for `reload_inM' or `reload_outM', as
6346 required.. These patterns, which will normally be implemented with a
6347 `define_expand', should be similar to the `movM' patterns, except that
6348 operand 2 is the scratch register.
6350 Define constraints for the reload register and scratch register that contain
6351 a single register class. If the original reload register (whose class is
6352 RCLASS) can meet the constraint given in the pattern, the value returned by
6353 these macros is used for the class of the scratch register. Otherwise, two
6354 additional reload registers are required. Their classes are obtained from
6355 the constraints in the insn pattern.
6357 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6358 either be in a hard register or in memory. Use `true_regnum' to find out;
6359 it will return -1 if the pseudo is in memory and the hard register number if
6360 it is in a register.
6362 These macros should not be used in the case where a particular class of
6363 registers can only be copied to memory and not to another class of
6364 registers. In that case, secondary reload registers are not needed and
6365 would not be helpful. Instead, a stack location must be used to perform the
6366 copy and the `movM' pattern should use memory as an intermediate storage.
6367 This case often occurs between floating-point and general registers. */
6370 frv_secondary_reload_class (enum reg_class rclass
,
6371 enum machine_mode mode ATTRIBUTE_UNUSED
,
6382 /* Accumulators/Accumulator guard registers need to go through floating
6387 if (x
&& GET_CODE (x
) == REG
)
6389 int regno
= REGNO (x
);
6391 if (ACC_P (regno
) || ACCG_P (regno
))
6396 /* Nonzero constants should be loaded into an FPR through a GPR. */
6398 if (x
&& CONSTANT_P (x
) && !ZERO_P (x
))
6404 /* All of these types need gpr registers. */
6416 /* The accumulators need fpr registers. */
6426 /* This hook exists to catch the case where secondary_reload_class() is
6427 called from init_reg_autoinc() in regclass.c - before the reload optabs
6428 have been initialised. */
6431 frv_secondary_reload (bool in_p
, rtx x
, reg_class_t reload_class_i
,
6432 enum machine_mode reload_mode
,
6433 secondary_reload_info
* sri
)
6435 enum reg_class rclass
= NO_REGS
;
6436 enum reg_class reload_class
= (enum reg_class
) reload_class_i
;
6438 if (sri
->prev_sri
&& sri
->prev_sri
->t_icode
!= CODE_FOR_nothing
)
6440 sri
->icode
= sri
->prev_sri
->t_icode
;
6444 rclass
= frv_secondary_reload_class (reload_class
, reload_mode
, x
);
6446 if (rclass
!= NO_REGS
)
6448 enum insn_code icode
6449 = direct_optab_handler (in_p
? reload_in_optab
: reload_out_optab
,
6453 /* This happens when then the reload_[in|out]_optabs have
6454 not been initialised. */
6455 sri
->t_icode
= CODE_FOR_nothing
;
6460 /* Fall back to the default secondary reload handler. */
6461 return default_secondary_reload (in_p
, x
, reload_class
, reload_mode
, sri
);
6465 /* Worker function for TARGET_CLASS_LIKELY_SPILLED_P. */
6468 frv_class_likely_spilled_p (reg_class_t rclass
)
6478 case FDPIC_FPTR_REGS
:
6498 /* An expression for the alignment of a structure field FIELD if the
6499 alignment computed in the usual way is COMPUTED. GCC uses this
6500 value instead of the value in `BIGGEST_ALIGNMENT' or
6501 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6503 /* The definition type of the bit field data is either char, short, long or
6504 long long. The maximum bit size is the number of bits of its own type.
6506 The bit field data is assigned to a storage unit that has an adequate size
6507 for bit field data retention and is located at the smallest address.
6509 Consecutive bit field data are packed at consecutive bits having the same
6510 storage unit, with regard to the type, beginning with the MSB and continuing
6513 If a field to be assigned lies over a bit field type boundary, its
6514 assignment is completed by aligning it with a boundary suitable for the
6517 When a bit field having a bit length of 0 is declared, it is forcibly
6518 assigned to the next storage unit.
6531 &x 00000000 00000000 00000000 00000000
6534 &x+4 00000000 00000000 00000000 00000000
6537 &x+8 00000000 00000000 00000000 00000000
6540 &x+12 00000000 00000000 00000000 00000000
6546 frv_adjust_field_align (tree field
, int computed
)
6548 /* Make sure that the bitfield is not wider than the type. */
6549 if (DECL_BIT_FIELD (field
)
6550 && !DECL_ARTIFICIAL (field
))
6552 tree parent
= DECL_CONTEXT (field
);
6553 tree prev
= NULL_TREE
;
6556 for (cur
= TYPE_FIELDS (parent
); cur
&& cur
!= field
; cur
= DECL_CHAIN (cur
))
6558 if (TREE_CODE (cur
) != FIELD_DECL
)
6566 /* If this isn't a :0 field and if the previous element is a bitfield
6567 also, see if the type is different, if so, we will need to align the
6568 bit-field to the next boundary. */
6570 && ! DECL_PACKED (field
)
6571 && ! integer_zerop (DECL_SIZE (field
))
6572 && DECL_BIT_FIELD_TYPE (field
) != DECL_BIT_FIELD_TYPE (prev
))
6574 int prev_align
= TYPE_ALIGN (TREE_TYPE (prev
));
6575 int cur_align
= TYPE_ALIGN (TREE_TYPE (field
));
6576 computed
= (prev_align
> cur_align
) ? prev_align
: cur_align
;
6584 /* A C expression that is nonzero if it is permissible to store a value of mode
6585 MODE in hard register number REGNO (or in several registers starting with
6586 that one). For a machine where all registers are equivalent, a suitable
6589 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6591 It is not necessary for this macro to check for the numbers of fixed
6592 registers, because the allocation mechanism considers them to be always
6595 On some machines, double-precision values must be kept in even/odd register
6596 pairs. The way to implement that is to define this macro to reject odd
6597 register numbers for such modes.
6599 The minimum requirement for a mode to be OK in a register is that the
6600 `movMODE' instruction pattern support moves between the register and any
6601 other hard register for which the mode is OK; and that moving a value into
6602 the register and back out not alter it.
6604 Since the same instruction used to move `SImode' will work for all narrower
6605 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6606 to distinguish between these modes, provided you define patterns `movhi',
6607 etc., to take advantage of this. This is useful because of the interaction
6608 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6609 all integer modes to be tieable.
6611 Many machines have special registers for floating point arithmetic. Often
6612 people assume that floating point machine modes are allowed only in floating
6613 point registers. This is not true. Any registers that can hold integers
6614 can safely *hold* a floating point machine mode, whether or not floating
6615 arithmetic can be done on it in those registers. Integer move instructions
6616 can be used to move the values.
6618 On some machines, though, the converse is true: fixed-point machine modes
6619 may not go in floating registers. This is true if the floating registers
6620 normalize any value stored in them, because storing a non-floating value
6621 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6622 fixed-point machine modes in floating registers. But if the floating
6623 registers do not automatically normalize, if you can store any bit pattern
6624 in one and retrieve it unchanged without a trap, then any machine mode may
6625 go in a floating register, so you can define this macro to say so.
6627 The primary significance of special floating registers is rather that they
6628 are the registers acceptable in floating point arithmetic instructions.
6629 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6630 writing the proper constraints for those instructions.
6632 On some machines, the floating registers are especially slow to access, so
6633 that it is better to store a value in a stack frame than in such a register
6634 if floating point arithmetic is not being done. As long as the floating
6635 registers are not in class `GENERAL_REGS', they will not be used unless some
6636 pattern's constraint asks for one. */
6639 frv_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
6649 return ICC_P (regno
) || GPR_P (regno
);
6652 return CR_P (regno
) || GPR_P (regno
);
6655 return FCC_P (regno
) || GPR_P (regno
);
6661 /* Set BASE to the first register in REGNO's class. Set MASK to the
6662 bits that must be clear in (REGNO - BASE) for the register to be
6664 if (INTEGRAL_MODE_P (mode
) || FLOAT_MODE_P (mode
) || VECTOR_MODE_P (mode
))
6668 /* ACCGs store one byte. Two-byte quantities must start in
6669 even-numbered registers, four-byte ones in registers whose
6670 numbers are divisible by four, and so on. */
6672 mask
= GET_MODE_SIZE (mode
) - 1;
6676 /* The other registers store one word. */
6677 if (GPR_P (regno
) || regno
== AP_FIRST
)
6680 else if (FPR_P (regno
))
6683 else if (ACC_P (regno
))
6686 else if (SPR_P (regno
))
6687 return mode
== SImode
;
6689 /* Fill in the table. */
6693 /* Anything smaller than an SI is OK in any word-sized register. */
6694 if (GET_MODE_SIZE (mode
) < 4)
6697 mask
= (GET_MODE_SIZE (mode
) / 4) - 1;
6699 return (((regno
- base
) & mask
) == 0);
6706 /* A C expression for the number of consecutive hard registers, starting at
6707 register number REGNO, required to hold a value of mode MODE.
6709 On a machine where all registers are exactly one word, a suitable definition
6712 #define HARD_REGNO_NREGS(REGNO, MODE) \
6713 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6714 / UNITS_PER_WORD)) */
6716 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6717 that we can build the appropriate instructions to properly reload the
6718 values. Also, make the byte-sized accumulator guards use one guard
6722 frv_hard_regno_nregs (int regno
, enum machine_mode mode
)
6725 return GET_MODE_SIZE (mode
);
6727 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6731 /* A C expression for the maximum number of consecutive registers of
6732 class RCLASS needed to hold a value of mode MODE.
6734 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6735 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6736 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6738 This macro helps control the handling of multiple-word values in
6741 This declaration is required. */
6744 frv_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
6746 if (rclass
== ACCG_REGS
)
6747 /* An N-byte value requires N accumulator guards. */
6748 return GET_MODE_SIZE (mode
);
6750 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6754 /* A C expression that is nonzero if X is a legitimate constant for an
6755 immediate operand on the target machine. You can assume that X satisfies
6756 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6757 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6760 frv_legitimate_constant_p (enum machine_mode mode
, rtx x
)
6762 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6763 means that the move expanders will be expected to deal with most
6764 kinds of constant, regardless of what we return here.
6766 However, among its other duties, frv_legitimate_constant_p decides whether
6767 a constant can be entered into reg_equiv_constant[]. If we return true,
6768 reload can create new instances of the constant whenever it likes.
6770 The idea is therefore to accept as many constants as possible (to give
6771 reload more freedom) while rejecting constants that can only be created
6772 at certain times. In particular, anything with a symbolic component will
6773 require use of the pseudo FDPIC register, which is only available before
6776 return LEGITIMATE_PIC_OPERAND_P (x
);
6778 /* All of the integer constants are ok. */
6779 if (GET_CODE (x
) != CONST_DOUBLE
)
6782 /* double integer constants are ok. */
6783 if (GET_MODE (x
) == VOIDmode
|| mode
== DImode
)
6786 /* 0 is always ok. */
6787 if (x
== CONST0_RTX (mode
))
6790 /* If floating point is just emulated, allow any constant, since it will be
6791 constructed in the GPRs. */
6792 if (!TARGET_HAS_FPRS
)
6795 if (mode
== DFmode
&& !TARGET_DOUBLE
)
6798 /* Otherwise store the constant away and do a load. */
6802 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6803 CC_NZ for comparisons against zero in which a single Z or N flag test
6804 is enough, CC_UNS for other unsigned comparisons, and CC for other
6805 signed comparisons. */
6808 frv_select_cc_mode (enum rtx_code code
, rtx x
, rtx y
)
6810 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6819 return y
== const0_rtx
? CC_NZmode
: CCmode
;
6825 return y
== const0_rtx
? CC_NZmode
: CC_UNSmode
;
6833 /* Worker function for TARGET_REGISTER_MOVE_COST. */
6835 #define HIGH_COST 40
6836 #define MEDIUM_COST 3
6840 frv_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
6841 reg_class_t from
, reg_class_t to
)
6854 case FDPIC_FPTR_REGS
:
6855 case FDPIC_CALL_REGS
:
6868 case FDPIC_FPTR_REGS
:
6869 case FDPIC_CALL_REGS
:
6894 case FDPIC_FPTR_REGS
:
6895 case FDPIC_CALL_REGS
:
6919 case FDPIC_FPTR_REGS
:
6920 case FDPIC_CALL_REGS
:
6941 /* Worker function for TARGET_MEMORY_MOVE_COST. */
6944 frv_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
6945 reg_class_t rclass ATTRIBUTE_UNUSED
,
6946 bool in ATTRIBUTE_UNUSED
)
6952 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
6953 use ".picptr" to generate safe relocations for PIC code. We also
6954 need a fixup entry for aligned (non-debugging) code. */
6957 frv_assemble_integer (rtx value
, unsigned int size
, int aligned_p
)
6959 if ((flag_pic
|| TARGET_FDPIC
) && size
== UNITS_PER_WORD
)
6961 if (GET_CODE (value
) == CONST
6962 || GET_CODE (value
) == SYMBOL_REF
6963 || GET_CODE (value
) == LABEL_REF
)
6965 if (TARGET_FDPIC
&& GET_CODE (value
) == SYMBOL_REF
6966 && SYMBOL_REF_FUNCTION_P (value
))
6968 fputs ("\t.picptr\tfuncdesc(", asm_out_file
);
6969 output_addr_const (asm_out_file
, value
);
6970 fputs (")\n", asm_out_file
);
6973 else if (TARGET_FDPIC
&& GET_CODE (value
) == CONST
6974 && frv_function_symbol_referenced_p (value
))
6976 if (aligned_p
&& !TARGET_FDPIC
)
6978 static int label_num
= 0;
6982 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", label_num
++);
6983 p
= (* targetm
.strip_name_encoding
) (buf
);
6985 fprintf (asm_out_file
, "%s:\n", p
);
6986 fprintf (asm_out_file
, "%s\n", FIXUP_SECTION_ASM_OP
);
6987 fprintf (asm_out_file
, "\t.picptr\t%s\n", p
);
6988 fprintf (asm_out_file
, "\t.previous\n");
6990 assemble_integer_with_op ("\t.picptr\t", value
);
6995 /* We've set the unaligned SI op to NULL, so we always have to
6996 handle the unaligned case here. */
6997 assemble_integer_with_op ("\t.4byte\t", value
);
7001 return default_assemble_integer (value
, size
, aligned_p
);
7004 /* Function to set up the backend function structure. */
7006 static struct machine_function
*
7007 frv_init_machine_status (void)
7009 return ggc_alloc_cleared_machine_function ();
7012 /* Implement TARGET_SCHED_ISSUE_RATE. */
7015 frv_issue_rate (void)
7020 switch (frv_cpu_type
)
7024 case FRV_CPU_SIMPLE
:
7032 case FRV_CPU_GENERIC
:
7034 case FRV_CPU_TOMCAT
:
7042 /* A for_each_rtx callback. If X refers to an accumulator, return
7043 ACC_GROUP_ODD if the bit 2 of the register number is set and
7044 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
7048 frv_acc_group_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
7052 if (ACC_P (REGNO (*x
)))
7053 return (REGNO (*x
) - ACC_FIRST
) & 4 ? ACC_GROUP_ODD
: ACC_GROUP_EVEN
;
7054 if (ACCG_P (REGNO (*x
)))
7055 return (REGNO (*x
) - ACCG_FIRST
) & 4 ? ACC_GROUP_ODD
: ACC_GROUP_EVEN
;
7060 /* Return the value of INSN's acc_group attribute. */
7063 frv_acc_group (rtx insn
)
7065 /* This distinction only applies to the FR550 packing constraints. */
7066 if (frv_cpu_type
!= FRV_CPU_FR550
)
7067 return ACC_GROUP_NONE
;
7068 return for_each_rtx (&PATTERN (insn
), frv_acc_group_1
, 0);
7071 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7072 INSN will try to claim first. Since this value depends only on the
7073 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7076 frv_insn_unit (rtx insn
)
7078 enum attr_type type
;
7080 type
= get_attr_type (insn
);
7081 if (frv_type_to_unit
[type
] == ARRAY_SIZE (frv_unit_codes
))
7083 /* We haven't seen this type of instruction before. */
7087 /* Issue the instruction on its own to see which unit it prefers. */
7088 state
= alloca (state_size ());
7089 state_reset (state
);
7090 state_transition (state
, insn
);
7092 /* Find out which unit was taken. */
7093 for (unit
= 0; unit
< ARRAY_SIZE (frv_unit_codes
); unit
++)
7094 if (cpu_unit_reservation_p (state
, frv_unit_codes
[unit
]))
7097 gcc_assert (unit
!= ARRAY_SIZE (frv_unit_codes
));
7099 frv_type_to_unit
[type
] = unit
;
7101 return frv_type_to_unit
[type
];
7104 /* Return true if INSN issues to a branch unit. */
7107 frv_issues_to_branch_unit_p (rtx insn
)
7109 return frv_unit_groups
[frv_insn_unit (insn
)] == GROUP_B
;
7112 /* The instructions in the packet, partitioned into groups. */
7113 struct frv_packet_group
{
7114 /* How many instructions in the packet belong to this group. */
7115 unsigned int num_insns
;
7117 /* A list of the instructions that belong to this group, in the order
7118 they appear in the rtl stream. */
7119 rtx insns
[ARRAY_SIZE (frv_unit_codes
)];
7121 /* The contents of INSNS after they have been sorted into the correct
7122 assembly-language order. Element X issues to unit X. The list may
7123 contain extra nops. */
7124 rtx sorted
[ARRAY_SIZE (frv_unit_codes
)];
7126 /* The member of frv_nops[] to use in sorted[]. */
7130 /* The current state of the packing pass, implemented by frv_pack_insns. */
7132 /* The state of the pipeline DFA. */
7135 /* Which hardware registers are set within the current packet,
7136 and the conditions under which they are set. */
7137 regstate_t regstate
[FIRST_PSEUDO_REGISTER
];
7139 /* The memory locations that have been modified so far in this
7140 packet. MEM is the memref and COND is the regstate_t condition
7141 under which it is set. */
7147 /* The number of valid entries in MEMS. The value is larger than
7148 ARRAY_SIZE (mems) if there were too many mems to record. */
7149 unsigned int num_mems
;
7151 /* The maximum number of instructions that can be packed together. */
7152 unsigned int issue_rate
;
7154 /* The instructions in the packet, partitioned into groups. */
7155 struct frv_packet_group groups
[NUM_GROUPS
];
7157 /* The instructions that make up the current packet. */
7158 rtx insns
[ARRAY_SIZE (frv_unit_codes
)];
7159 unsigned int num_insns
;
7162 /* Return the regstate_t flags for the given COND_EXEC condition.
7163 Abort if the condition isn't in the right form. */
7166 frv_cond_flags (rtx cond
)
7168 gcc_assert ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
7169 && GET_CODE (XEXP (cond
, 0)) == REG
7170 && CR_P (REGNO (XEXP (cond
, 0)))
7171 && XEXP (cond
, 1) == const0_rtx
);
7172 return ((REGNO (XEXP (cond
, 0)) - CR_FIRST
)
7173 | (GET_CODE (cond
) == NE
7175 : REGSTATE_IF_FALSE
));
7179 /* Return true if something accessed under condition COND2 can
7180 conflict with something written under condition COND1. */
7183 frv_regstate_conflict_p (regstate_t cond1
, regstate_t cond2
)
7185 /* If either reference was unconditional, we have a conflict. */
7186 if ((cond1
& REGSTATE_IF_EITHER
) == 0
7187 || (cond2
& REGSTATE_IF_EITHER
) == 0)
7190 /* The references might conflict if they were controlled by
7192 if ((cond1
& REGSTATE_CC_MASK
) != (cond2
& REGSTATE_CC_MASK
))
7195 /* They definitely conflict if they are controlled by the
7197 if ((cond1
& cond2
& REGSTATE_IF_EITHER
) != 0)
7204 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7205 the current packet. DATA points to a regstate_t that describes the
7206 condition under which *X might be set or used. */
7209 frv_registers_conflict_p_1 (rtx
*x
, void *data
)
7211 unsigned int regno
, i
;
7214 cond
= *(regstate_t
*) data
;
7216 if (GET_CODE (*x
) == REG
)
7217 FOR_EACH_REGNO (regno
, *x
)
7218 if ((frv_packet
.regstate
[regno
] & REGSTATE_MODIFIED
) != 0)
7219 if (frv_regstate_conflict_p (frv_packet
.regstate
[regno
], cond
))
7222 if (GET_CODE (*x
) == MEM
)
7224 /* If we ran out of memory slots, assume a conflict. */
7225 if (frv_packet
.num_mems
> ARRAY_SIZE (frv_packet
.mems
))
7228 /* Check for output or true dependencies with earlier MEMs. */
7229 for (i
= 0; i
< frv_packet
.num_mems
; i
++)
7230 if (frv_regstate_conflict_p (frv_packet
.mems
[i
].cond
, cond
))
7232 if (true_dependence (frv_packet
.mems
[i
].mem
, VOIDmode
, *x
))
7235 if (output_dependence (frv_packet
.mems
[i
].mem
, *x
))
7240 /* The return values of calls aren't significant: they describe
7241 the effect of the call as a whole, not of the insn itself. */
7242 if (GET_CODE (*x
) == SET
&& GET_CODE (SET_SRC (*x
)) == CALL
)
7244 if (for_each_rtx (&SET_SRC (*x
), frv_registers_conflict_p_1
, data
))
7249 /* Check subexpressions. */
7254 /* Return true if something in X might depend on an instruction
7255 in the current packet. */
7258 frv_registers_conflict_p (rtx x
)
7263 if (GET_CODE (x
) == COND_EXEC
)
7265 if (for_each_rtx (&XEXP (x
, 0), frv_registers_conflict_p_1
, &flags
))
7268 flags
|= frv_cond_flags (XEXP (x
, 0));
7271 return for_each_rtx (&x
, frv_registers_conflict_p_1
, &flags
);
7275 /* A note_stores callback. DATA points to the regstate_t condition
7276 under which X is modified. Update FRV_PACKET accordingly. */
7279 frv_registers_update_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7283 if (GET_CODE (x
) == REG
)
7284 FOR_EACH_REGNO (regno
, x
)
7285 frv_packet
.regstate
[regno
] |= *(regstate_t
*) data
;
7287 if (GET_CODE (x
) == MEM
)
7289 if (frv_packet
.num_mems
< ARRAY_SIZE (frv_packet
.mems
))
7291 frv_packet
.mems
[frv_packet
.num_mems
].mem
= x
;
7292 frv_packet
.mems
[frv_packet
.num_mems
].cond
= *(regstate_t
*) data
;
7294 frv_packet
.num_mems
++;
7299 /* Update the register state information for an instruction whose
7303 frv_registers_update (rtx x
)
7307 flags
= REGSTATE_MODIFIED
;
7308 if (GET_CODE (x
) == COND_EXEC
)
7310 flags
|= frv_cond_flags (XEXP (x
, 0));
7313 note_stores (x
, frv_registers_update_1
, &flags
);
7317 /* Initialize frv_packet for the start of a new packet. */
7320 frv_start_packet (void)
7322 enum frv_insn_group group
;
7324 memset (frv_packet
.regstate
, 0, sizeof (frv_packet
.regstate
));
7325 frv_packet
.num_mems
= 0;
7326 frv_packet
.num_insns
= 0;
7327 for (group
= GROUP_I
; group
< NUM_GROUPS
;
7328 group
= (enum frv_insn_group
) (group
+ 1))
7329 frv_packet
.groups
[group
].num_insns
= 0;
7333 /* Likewise for the start of a new basic block. */
7336 frv_start_packet_block (void)
7338 state_reset (frv_packet
.dfa_state
);
7339 frv_start_packet ();
7343 /* Finish the current packet, if any, and start a new one. Call
7344 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7347 frv_finish_packet (void (*handle_packet
) (void))
7349 if (frv_packet
.num_insns
> 0)
7352 state_transition (frv_packet
.dfa_state
, 0);
7353 frv_start_packet ();
7358 /* Return true if INSN can be added to the current packet. Update
7359 the DFA state on success. */
7362 frv_pack_insn_p (rtx insn
)
7364 /* See if the packet is already as long as it can be. */
7365 if (frv_packet
.num_insns
== frv_packet
.issue_rate
)
7368 /* If the scheduler thought that an instruction should start a packet,
7369 it's usually a good idea to believe it. It knows much more about
7370 the latencies than we do.
7372 There are some exceptions though:
7374 - Conditional instructions are scheduled on the assumption that
7375 they will be executed. This is usually a good thing, since it
7376 tends to avoid unnecessary stalls in the conditional code.
7377 But we want to pack conditional instructions as tightly as
7378 possible, in order to optimize the case where they aren't
7381 - The scheduler will always put branches on their own, even
7382 if there's no real dependency.
7384 - There's no point putting a call in its own packet unless
7386 if (frv_packet
.num_insns
> 0
7387 && NONJUMP_INSN_P (insn
)
7388 && GET_MODE (insn
) == TImode
7389 && GET_CODE (PATTERN (insn
)) != COND_EXEC
)
7392 /* Check for register conflicts. Don't do this for setlo since any
7393 conflict will be with the partnering sethi, with which it can
7395 if (get_attr_type (insn
) != TYPE_SETLO
)
7396 if (frv_registers_conflict_p (PATTERN (insn
)))
7399 return state_transition (frv_packet
.dfa_state
, insn
) < 0;
7403 /* Add instruction INSN to the current packet. */
7406 frv_add_insn_to_packet (rtx insn
)
7408 struct frv_packet_group
*packet_group
;
7410 packet_group
= &frv_packet
.groups
[frv_unit_groups
[frv_insn_unit (insn
)]];
7411 packet_group
->insns
[packet_group
->num_insns
++] = insn
;
7412 frv_packet
.insns
[frv_packet
.num_insns
++] = insn
;
7414 frv_registers_update (PATTERN (insn
));
7418 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7419 packet ends in a branch or call, insert the nop before it, otherwise
7423 frv_insert_nop_in_packet (rtx insn
)
7425 struct frv_packet_group
*packet_group
;
7428 packet_group
= &frv_packet
.groups
[frv_unit_groups
[frv_insn_unit (insn
)]];
7429 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
7430 if (! NONJUMP_INSN_P (last
))
7432 insn
= emit_insn_before (PATTERN (insn
), last
);
7433 frv_packet
.insns
[frv_packet
.num_insns
- 1] = insn
;
7434 frv_packet
.insns
[frv_packet
.num_insns
++] = last
;
7438 insn
= emit_insn_after (PATTERN (insn
), last
);
7439 frv_packet
.insns
[frv_packet
.num_insns
++] = insn
;
7441 packet_group
->insns
[packet_group
->num_insns
++] = insn
;
7445 /* If packing is enabled, divide the instructions into packets and
7446 return true. Call HANDLE_PACKET for each complete packet. */
7449 frv_for_each_packet (void (*handle_packet
) (void))
7451 rtx insn
, next_insn
;
7453 frv_packet
.issue_rate
= frv_issue_rate ();
7455 /* Early exit if we don't want to pack insns. */
7457 || !flag_schedule_insns_after_reload
7458 || !TARGET_VLIW_BRANCH
7459 || frv_packet
.issue_rate
== 1)
7462 /* Set up the initial packing state. */
7464 frv_packet
.dfa_state
= alloca (state_size ());
7466 frv_start_packet_block ();
7467 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
7472 code
= GET_CODE (insn
);
7473 next_insn
= NEXT_INSN (insn
);
7475 if (code
== CODE_LABEL
)
7477 frv_finish_packet (handle_packet
);
7478 frv_start_packet_block ();
7482 switch (GET_CODE (PATTERN (insn
)))
7489 /* Calls mustn't be packed on a TOMCAT. */
7490 if (CALL_P (insn
) && frv_cpu_type
== FRV_CPU_TOMCAT
)
7491 frv_finish_packet (handle_packet
);
7493 /* Since the last instruction in a packet determines the EH
7494 region, any exception-throwing instruction must come at
7495 the end of reordered packet. Insns that issue to a
7496 branch unit are bound to come last; for others it's
7497 too hard to predict. */
7498 eh_insn_p
= (find_reg_note (insn
, REG_EH_REGION
, NULL
) != NULL
);
7499 if (eh_insn_p
&& !frv_issues_to_branch_unit_p (insn
))
7500 frv_finish_packet (handle_packet
);
7502 /* Finish the current packet if we can't add INSN to it.
7503 Simulate cycles until INSN is ready to issue. */
7504 if (!frv_pack_insn_p (insn
))
7506 frv_finish_packet (handle_packet
);
7507 while (!frv_pack_insn_p (insn
))
7508 state_transition (frv_packet
.dfa_state
, 0);
7511 /* Add the instruction to the packet. */
7512 frv_add_insn_to_packet (insn
);
7514 /* Calls and jumps end a packet, as do insns that throw
7516 if (code
== CALL_INSN
|| code
== JUMP_INSN
|| eh_insn_p
)
7517 frv_finish_packet (handle_packet
);
7521 frv_finish_packet (handle_packet
);
7526 /* Subroutine of frv_sort_insn_group. We are trying to sort
7527 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7528 language order. We have already picked a new position for
7529 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7530 These instructions will occupy elements [0, LOWER_SLOT) and
7531 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7532 the DFA state after issuing these instructions.
7534 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7535 of the unused instructions. Return true if one such permutation gives
7536 a valid ordering, leaving the successful permutation in sorted[].
7537 Do not modify sorted[] until a valid permutation is found. */
7540 frv_sort_insn_group_1 (enum frv_insn_group group
,
7541 unsigned int lower_slot
, unsigned int upper_slot
,
7542 unsigned int issued
, unsigned int num_insns
,
7545 struct frv_packet_group
*packet_group
;
7551 /* Early success if we've filled all the slots. */
7552 if (lower_slot
== upper_slot
)
7555 packet_group
= &frv_packet
.groups
[group
];
7556 dfa_size
= state_size ();
7557 test_state
= alloca (dfa_size
);
7559 /* Try issuing each unused instruction. */
7560 for (i
= num_insns
- 1; i
+ 1 != 0; i
--)
7561 if (~issued
& (1 << i
))
7563 insn
= packet_group
->sorted
[i
];
7564 memcpy (test_state
, state
, dfa_size
);
7565 if (state_transition (test_state
, insn
) < 0
7566 && cpu_unit_reservation_p (test_state
,
7567 NTH_UNIT (group
, upper_slot
- 1))
7568 && frv_sort_insn_group_1 (group
, lower_slot
, upper_slot
- 1,
7569 issued
| (1 << i
), num_insns
,
7572 packet_group
->sorted
[upper_slot
- 1] = insn
;
7580 /* Compare two instructions by their frv_insn_unit. */
7583 frv_compare_insns (const void *first
, const void *second
)
7585 const rtx
*const insn1
= (rtx
const *) first
,
7586 *const insn2
= (rtx
const *) second
;
7587 return frv_insn_unit (*insn1
) - frv_insn_unit (*insn2
);
7590 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7591 and sort it into assembly language order. See frv.md for a description of
7595 frv_sort_insn_group (enum frv_insn_group group
)
7597 struct frv_packet_group
*packet_group
;
7598 unsigned int first
, i
, nop
, max_unit
, num_slots
;
7599 state_t state
, test_state
;
7602 packet_group
= &frv_packet
.groups
[group
];
7604 /* Assume no nop is needed. */
7605 packet_group
->nop
= 0;
7607 if (packet_group
->num_insns
== 0)
7610 /* Copy insns[] to sorted[]. */
7611 memcpy (packet_group
->sorted
, packet_group
->insns
,
7612 sizeof (rtx
) * packet_group
->num_insns
);
7614 /* Sort sorted[] by the unit that each insn tries to take first. */
7615 if (packet_group
->num_insns
> 1)
7616 qsort (packet_group
->sorted
, packet_group
->num_insns
,
7617 sizeof (rtx
), frv_compare_insns
);
7619 /* That's always enough for branch and control insns. */
7620 if (group
== GROUP_B
|| group
== GROUP_C
)
7623 dfa_size
= state_size ();
7624 state
= alloca (dfa_size
);
7625 test_state
= alloca (dfa_size
);
7627 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7628 consecutively and such that the DFA takes unit X when sorted[X]
7629 is added. Set STATE to the new DFA state. */
7630 state_reset (test_state
);
7631 for (first
= 0; first
< packet_group
->num_insns
; first
++)
7633 memcpy (state
, test_state
, dfa_size
);
7634 if (state_transition (test_state
, packet_group
->sorted
[first
]) >= 0
7635 || !cpu_unit_reservation_p (test_state
, NTH_UNIT (group
, first
)))
7639 /* If all the instructions issued in ascending order, we're done. */
7640 if (first
== packet_group
->num_insns
)
7643 /* Add nops to the end of sorted[] and try each permutation until
7644 we find one that works. */
7645 for (nop
= 0; nop
< frv_num_nops
; nop
++)
7647 max_unit
= frv_insn_unit (frv_nops
[nop
]);
7648 if (frv_unit_groups
[max_unit
] == group
)
7650 packet_group
->nop
= frv_nops
[nop
];
7651 num_slots
= UNIT_NUMBER (max_unit
) + 1;
7652 for (i
= packet_group
->num_insns
; i
< num_slots
; i
++)
7653 packet_group
->sorted
[i
] = frv_nops
[nop
];
7654 if (frv_sort_insn_group_1 (group
, first
, num_slots
,
7655 (1 << first
) - 1, num_slots
, state
))
7662 /* Sort the current packet into assembly-language order. Set packing
7663 flags as appropriate. */
7666 frv_reorder_packet (void)
7668 unsigned int cursor
[NUM_GROUPS
];
7669 rtx insns
[ARRAY_SIZE (frv_unit_groups
)];
7670 unsigned int unit
, to
, from
;
7671 enum frv_insn_group group
;
7672 struct frv_packet_group
*packet_group
;
7674 /* First sort each group individually. */
7675 for (group
= GROUP_I
; group
< NUM_GROUPS
;
7676 group
= (enum frv_insn_group
) (group
+ 1))
7679 frv_sort_insn_group (group
);
7682 /* Go through the unit template and try add an instruction from
7683 that unit's group. */
7685 for (unit
= 0; unit
< ARRAY_SIZE (frv_unit_groups
); unit
++)
7687 group
= frv_unit_groups
[unit
];
7688 packet_group
= &frv_packet
.groups
[group
];
7689 if (cursor
[group
] < packet_group
->num_insns
)
7691 /* frv_reorg should have added nops for us. */
7692 gcc_assert (packet_group
->sorted
[cursor
[group
]]
7693 != packet_group
->nop
);
7694 insns
[to
++] = packet_group
->sorted
[cursor
[group
]++];
7698 gcc_assert (to
== frv_packet
.num_insns
);
7700 /* Clear the last instruction's packing flag, thus marking the end of
7701 a packet. Reorder the other instructions relative to it. */
7702 CLEAR_PACKING_FLAG (insns
[to
- 1]);
7703 for (from
= 0; from
< to
- 1; from
++)
7705 remove_insn (insns
[from
]);
7706 add_insn_before (insns
[from
], insns
[to
- 1], NULL
);
7707 SET_PACKING_FLAG (insns
[from
]);
7712 /* Divide instructions into packets. Reorder the contents of each
7713 packet so that they are in the correct assembly-language order.
7715 Since this pass can change the raw meaning of the rtl stream, it must
7716 only be called at the last minute, just before the instructions are
7720 frv_pack_insns (void)
7722 if (frv_for_each_packet (frv_reorder_packet
))
7723 frv_insn_packing_flag
= 0;
7725 frv_insn_packing_flag
= -1;
7728 /* See whether we need to add nops to group GROUP in order to
7729 make a valid packet. */
7732 frv_fill_unused_units (enum frv_insn_group group
)
7734 unsigned int non_nops
, nops
, i
;
7735 struct frv_packet_group
*packet_group
;
7737 packet_group
= &frv_packet
.groups
[group
];
7739 /* Sort the instructions into assembly-language order.
7740 Use nops to fill slots that are otherwise unused. */
7741 frv_sort_insn_group (group
);
7743 /* See how many nops are needed before the final useful instruction. */
7745 for (non_nops
= 0; non_nops
< packet_group
->num_insns
; non_nops
++)
7746 while (packet_group
->sorted
[i
++] == packet_group
->nop
)
7749 /* Insert that many nops into the instruction stream. */
7751 frv_insert_nop_in_packet (packet_group
->nop
);
7754 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7757 frv_same_doubleword_p (const struct frv_io
*io1
, const struct frv_io
*io2
)
7759 if (io1
->const_address
!= 0 && io2
->const_address
!= 0)
7760 return io1
->const_address
== io2
->const_address
;
7762 if (io1
->var_address
!= 0 && io2
->var_address
!= 0)
7763 return rtx_equal_p (io1
->var_address
, io2
->var_address
);
7768 /* Return true if operations IO1 and IO2 are guaranteed to complete
7772 frv_io_fixed_order_p (const struct frv_io
*io1
, const struct frv_io
*io2
)
7774 /* The order of writes is always preserved. */
7775 if (io1
->type
== FRV_IO_WRITE
&& io2
->type
== FRV_IO_WRITE
)
7778 /* The order of reads isn't preserved. */
7779 if (io1
->type
!= FRV_IO_WRITE
&& io2
->type
!= FRV_IO_WRITE
)
7782 /* One operation is a write and the other is (or could be) a read.
7783 The order is only guaranteed if the accesses are to the same
7785 return frv_same_doubleword_p (io1
, io2
);
7788 /* Generalize I/O operation X so that it covers both X and Y. */
7791 frv_io_union (struct frv_io
*x
, const struct frv_io
*y
)
7793 if (x
->type
!= y
->type
)
7794 x
->type
= FRV_IO_UNKNOWN
;
7795 if (!frv_same_doubleword_p (x
, y
))
7797 x
->const_address
= 0;
7802 /* Fill IO with information about the load or store associated with
7803 membar instruction INSN. */
7806 frv_extract_membar (struct frv_io
*io
, rtx insn
)
7808 extract_insn (insn
);
7809 io
->type
= (enum frv_io_type
) INTVAL (recog_data
.operand
[2]);
7810 io
->const_address
= INTVAL (recog_data
.operand
[1]);
7811 io
->var_address
= XEXP (recog_data
.operand
[0], 0);
7814 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7815 if X is a register and *DATA depends on X. */
7818 frv_io_check_address (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7820 rtx
*other
= (rtx
*) data
;
7822 if (REG_P (x
) && *other
!= 0 && reg_overlap_mentioned_p (x
, *other
))
7826 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7827 Remove every modified register from the set. */
7830 frv_io_handle_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7832 HARD_REG_SET
*set
= (HARD_REG_SET
*) data
;
7836 FOR_EACH_REGNO (regno
, x
)
7837 CLEAR_HARD_REG_BIT (*set
, regno
);
7840 /* A for_each_rtx callback for which DATA points to a HARD_REG_SET.
7841 Add every register in *X to the set. */
7844 frv_io_handle_use_1 (rtx
*x
, void *data
)
7846 HARD_REG_SET
*set
= (HARD_REG_SET
*) data
;
7850 FOR_EACH_REGNO (regno
, *x
)
7851 SET_HARD_REG_BIT (*set
, regno
);
7856 /* A note_stores callback that applies frv_io_handle_use_1 to an
7857 entire rhs value. */
7860 frv_io_handle_use (rtx
*x
, void *data
)
7862 for_each_rtx (x
, frv_io_handle_use_1
, data
);
7865 /* Go through block BB looking for membars to remove. There are two
7866 cases where intra-block analysis is enough:
7868 - a membar is redundant if it occurs between two consecutive I/O
7869 operations and if those operations are guaranteed to complete
7872 - a membar for a __builtin_read is redundant if the result is
7873 used before the next I/O operation is issued.
7875 If the last membar in the block could not be removed, and there
7876 are guaranteed to be no I/O operations between that membar and
7877 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7880 Describe the block's first I/O operation in *NEXT_IO. Describe
7881 an unknown operation if the block doesn't do any I/O. */
7884 frv_optimize_membar_local (basic_block bb
, struct frv_io
*next_io
,
7887 HARD_REG_SET used_regs
;
7888 rtx next_membar
, set
, insn
;
7891 /* NEXT_IO is the next I/O operation to be performed after the current
7892 instruction. It starts off as being an unknown operation. */
7893 memset (next_io
, 0, sizeof (*next_io
));
7895 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7896 next_is_end_p
= true;
7898 /* If the current instruction is a __builtin_read or __builtin_write,
7899 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7900 is null if the membar has already been deleted.
7902 Note that the initialization here should only be needed to
7903 suppress warnings. */
7906 /* USED_REGS is the set of registers that are used before the
7907 next I/O instruction. */
7908 CLEAR_HARD_REG_SET (used_regs
);
7910 for (insn
= BB_END (bb
); insn
!= BB_HEAD (bb
); insn
= PREV_INSN (insn
))
7913 /* We can't predict what a call will do to volatile memory. */
7914 memset (next_io
, 0, sizeof (struct frv_io
));
7915 next_is_end_p
= false;
7916 CLEAR_HARD_REG_SET (used_regs
);
7918 else if (INSN_P (insn
))
7919 switch (recog_memoized (insn
))
7921 case CODE_FOR_optional_membar_qi
:
7922 case CODE_FOR_optional_membar_hi
:
7923 case CODE_FOR_optional_membar_si
:
7924 case CODE_FOR_optional_membar_di
:
7928 /* Local information isn't enough to decide whether this
7929 membar is needed. Stash it away for later. */
7930 *last_membar
= insn
;
7931 frv_extract_membar (next_io
, insn
);
7932 next_is_end_p
= false;
7936 /* Check whether the I/O operation before INSN could be
7937 reordered with one described by NEXT_IO. If it can't,
7938 INSN will not be needed. */
7939 struct frv_io prev_io
;
7941 frv_extract_membar (&prev_io
, insn
);
7942 if (frv_io_fixed_order_p (&prev_io
, next_io
))
7946 ";; [Local] Removing membar %d since order"
7947 " of accesses is guaranteed\n",
7948 INSN_UID (next_membar
));
7950 insn
= NEXT_INSN (insn
);
7951 delete_insn (next_membar
);
7959 /* Invalidate NEXT_IO's address if it depends on something that
7960 is clobbered by INSN. */
7961 if (next_io
->var_address
)
7962 note_stores (PATTERN (insn
), frv_io_check_address
,
7963 &next_io
->var_address
);
7965 /* If the next membar is associated with a __builtin_read,
7966 see if INSN reads from that address. If it does, and if
7967 the destination register is used before the next I/O access,
7968 there is no need for the membar. */
7969 set
= PATTERN (insn
);
7970 if (next_io
->type
== FRV_IO_READ
7971 && next_io
->var_address
!= 0
7973 && GET_CODE (set
) == SET
7974 && GET_CODE (SET_DEST (set
)) == REG
7975 && TEST_HARD_REG_BIT (used_regs
, REGNO (SET_DEST (set
))))
7979 src
= SET_SRC (set
);
7980 if (GET_CODE (src
) == ZERO_EXTEND
)
7981 src
= XEXP (src
, 0);
7983 if (GET_CODE (src
) == MEM
7984 && rtx_equal_p (XEXP (src
, 0), next_io
->var_address
))
7988 ";; [Local] Removing membar %d since the target"
7989 " of %d is used before the I/O operation\n",
7990 INSN_UID (next_membar
), INSN_UID (insn
));
7992 if (next_membar
== *last_membar
)
7995 delete_insn (next_membar
);
8000 /* If INSN has volatile references, forget about any registers
8001 that are used after it. Otherwise forget about uses that
8002 are (or might be) defined by INSN. */
8003 if (volatile_refs_p (PATTERN (insn
)))
8004 CLEAR_HARD_REG_SET (used_regs
);
8006 note_stores (PATTERN (insn
), frv_io_handle_set
, &used_regs
);
8008 note_uses (&PATTERN (insn
), frv_io_handle_use
, &used_regs
);
8013 /* See if MEMBAR, the last membar instruction in BB, can be removed.
8014 FIRST_IO[X] describes the first operation performed by basic block X. */
8017 frv_optimize_membar_global (basic_block bb
, struct frv_io
*first_io
,
8020 struct frv_io this_io
, next_io
;
8024 /* We need to keep the membar if there is an edge to the exit block. */
8025 FOR_EACH_EDGE (succ
, ei
, bb
->succs
)
8026 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
8027 if (succ
->dest
== EXIT_BLOCK_PTR
)
8030 /* Work out the union of all successor blocks. */
8031 ei
= ei_start (bb
->succs
);
8032 ei_cond (ei
, &succ
);
8033 /* next_io = first_io[bb->succ->dest->index]; */
8034 next_io
= first_io
[succ
->dest
->index
];
8035 ei
= ei_start (bb
->succs
);
8036 if (ei_cond (ei
, &succ
))
8038 for (ei_next (&ei
); ei_cond (ei
, &succ
); ei_next (&ei
))
8039 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
8040 frv_io_union (&next_io
, &first_io
[succ
->dest
->index
]);
8045 frv_extract_membar (&this_io
, membar
);
8046 if (frv_io_fixed_order_p (&this_io
, &next_io
))
8050 ";; [Global] Removing membar %d since order of accesses"
8051 " is guaranteed\n", INSN_UID (membar
));
8053 delete_insn (membar
);
8057 /* Remove redundant membars from the current function. */
8060 frv_optimize_membar (void)
8063 struct frv_io
*first_io
;
8066 compute_bb_for_insn ();
8067 first_io
= XCNEWVEC (struct frv_io
, last_basic_block
);
8068 last_membar
= XCNEWVEC (rtx
, last_basic_block
);
8071 frv_optimize_membar_local (bb
, &first_io
[bb
->index
],
8072 &last_membar
[bb
->index
]);
8075 if (last_membar
[bb
->index
] != 0)
8076 frv_optimize_membar_global (bb
, first_io
, last_membar
[bb
->index
]);
8082 /* Used by frv_reorg to keep track of the current packet's address. */
8083 static unsigned int frv_packet_address
;
8085 /* If the current packet falls through to a label, try to pad the packet
8086 with nops in order to fit the label's alignment requirements. */
8089 frv_align_label (void)
8091 unsigned int alignment
, target
, nop
;
8092 rtx x
, last
, barrier
, label
;
8094 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8095 maximum alignment of that packet, LABEL to the last label between
8096 the packets, and BARRIER to the last barrier. */
8097 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
8098 label
= barrier
= 0;
8100 for (x
= NEXT_INSN (last
); x
!= 0 && !INSN_P (x
); x
= NEXT_INSN (x
))
8104 unsigned int subalign
= 1 << label_to_alignment (x
);
8105 alignment
= MAX (alignment
, subalign
);
8112 /* If -malign-labels, and the packet falls through to an unaligned
8113 label, try introducing a nop to align that label to 8 bytes. */
8114 if (TARGET_ALIGN_LABELS
8117 && frv_packet
.num_insns
< frv_packet
.issue_rate
)
8118 alignment
= MAX (alignment
, 8);
8120 /* Advance the address to the end of the current packet. */
8121 frv_packet_address
+= frv_packet
.num_insns
* 4;
8123 /* Work out the target address, after alignment. */
8124 target
= (frv_packet_address
+ alignment
- 1) & -alignment
;
8126 /* If the packet falls through to the label, try to find an efficient
8127 padding sequence. */
8130 /* First try adding nops to the current packet. */
8131 for (nop
= 0; nop
< frv_num_nops
; nop
++)
8132 while (frv_packet_address
< target
&& frv_pack_insn_p (frv_nops
[nop
]))
8134 frv_insert_nop_in_packet (frv_nops
[nop
]);
8135 frv_packet_address
+= 4;
8138 /* If we still haven't reached the target, add some new packets that
8139 contain only nops. If there are two types of nop, insert an
8140 alternating sequence of frv_nops[0] and frv_nops[1], which will
8141 lead to packets like:
8148 etc. Just emit frv_nops[0] if that's the only nop we have. */
8149 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
8151 while (frv_packet_address
< target
)
8153 last
= emit_insn_after (PATTERN (frv_nops
[nop
]), last
);
8154 frv_packet_address
+= 4;
8155 if (frv_num_nops
> 1)
8160 frv_packet_address
= target
;
8163 /* Subroutine of frv_reorg, called after each packet has been constructed
8167 frv_reorg_packet (void)
8169 frv_fill_unused_units (GROUP_I
);
8170 frv_fill_unused_units (GROUP_FM
);
8174 /* Add an instruction with pattern NOP to frv_nops[]. */
8177 frv_register_nop (rtx nop
)
8179 nop
= make_insn_raw (nop
);
8180 NEXT_INSN (nop
) = 0;
8181 PREV_INSN (nop
) = 0;
8182 frv_nops
[frv_num_nops
++] = nop
;
8185 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8186 into packets and check whether we need to insert nops in order to
8187 fulfill the processor's issue requirements. Also, if the user has
8188 requested a certain alignment for a label, try to meet that alignment
8189 by inserting nops in the previous packet. */
8194 if (optimize
> 0 && TARGET_OPTIMIZE_MEMBAR
&& cfun
->machine
->has_membar_p
)
8195 frv_optimize_membar ();
8198 frv_register_nop (gen_nop ());
8200 frv_register_nop (gen_mnop ());
8201 if (TARGET_HARD_FLOAT
)
8202 frv_register_nop (gen_fnop ());
8204 /* Estimate the length of each branch. Although this may change after
8205 we've inserted nops, it will only do so in big functions. */
8206 shorten_branches (get_insns ());
8208 frv_packet_address
= 0;
8209 frv_for_each_packet (frv_reorg_packet
);
8212 #define def_builtin(name, type, code) \
8213 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8215 struct builtin_description
8217 enum insn_code icode
;
8219 enum frv_builtins code
;
8220 enum rtx_code comparison
;
8224 /* Media intrinsics that take a single, constant argument. */
8226 static struct builtin_description bdesc_set
[] =
8228 { CODE_FOR_mhdsets
, "__MHDSETS", FRV_BUILTIN_MHDSETS
, UNKNOWN
, 0 }
8231 /* Media intrinsics that take just one argument. */
8233 static struct builtin_description bdesc_1arg
[] =
8235 { CODE_FOR_mnot
, "__MNOT", FRV_BUILTIN_MNOT
, UNKNOWN
, 0 },
8236 { CODE_FOR_munpackh
, "__MUNPACKH", FRV_BUILTIN_MUNPACKH
, UNKNOWN
, 0 },
8237 { CODE_FOR_mbtoh
, "__MBTOH", FRV_BUILTIN_MBTOH
, UNKNOWN
, 0 },
8238 { CODE_FOR_mhtob
, "__MHTOB", FRV_BUILTIN_MHTOB
, UNKNOWN
, 0},
8239 { CODE_FOR_mabshs
, "__MABSHS", FRV_BUILTIN_MABSHS
, UNKNOWN
, 0 },
8240 { CODE_FOR_scutss
, "__SCUTSS", FRV_BUILTIN_SCUTSS
, UNKNOWN
, 0 }
8243 /* Media intrinsics that take two arguments. */
8245 static struct builtin_description bdesc_2arg
[] =
8247 { CODE_FOR_mand
, "__MAND", FRV_BUILTIN_MAND
, UNKNOWN
, 0},
8248 { CODE_FOR_mor
, "__MOR", FRV_BUILTIN_MOR
, UNKNOWN
, 0},
8249 { CODE_FOR_mxor
, "__MXOR", FRV_BUILTIN_MXOR
, UNKNOWN
, 0},
8250 { CODE_FOR_maveh
, "__MAVEH", FRV_BUILTIN_MAVEH
, UNKNOWN
, 0},
8251 { CODE_FOR_msaths
, "__MSATHS", FRV_BUILTIN_MSATHS
, UNKNOWN
, 0},
8252 { CODE_FOR_msathu
, "__MSATHU", FRV_BUILTIN_MSATHU
, UNKNOWN
, 0},
8253 { CODE_FOR_maddhss
, "__MADDHSS", FRV_BUILTIN_MADDHSS
, UNKNOWN
, 0},
8254 { CODE_FOR_maddhus
, "__MADDHUS", FRV_BUILTIN_MADDHUS
, UNKNOWN
, 0},
8255 { CODE_FOR_msubhss
, "__MSUBHSS", FRV_BUILTIN_MSUBHSS
, UNKNOWN
, 0},
8256 { CODE_FOR_msubhus
, "__MSUBHUS", FRV_BUILTIN_MSUBHUS
, UNKNOWN
, 0},
8257 { CODE_FOR_mqaddhss
, "__MQADDHSS", FRV_BUILTIN_MQADDHSS
, UNKNOWN
, 0},
8258 { CODE_FOR_mqaddhus
, "__MQADDHUS", FRV_BUILTIN_MQADDHUS
, UNKNOWN
, 0},
8259 { CODE_FOR_mqsubhss
, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS
, UNKNOWN
, 0},
8260 { CODE_FOR_mqsubhus
, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS
, UNKNOWN
, 0},
8261 { CODE_FOR_mpackh
, "__MPACKH", FRV_BUILTIN_MPACKH
, UNKNOWN
, 0},
8262 { CODE_FOR_mcop1
, "__Mcop1", FRV_BUILTIN_MCOP1
, UNKNOWN
, 0},
8263 { CODE_FOR_mcop2
, "__Mcop2", FRV_BUILTIN_MCOP2
, UNKNOWN
, 0},
8264 { CODE_FOR_mwcut
, "__MWCUT", FRV_BUILTIN_MWCUT
, UNKNOWN
, 0},
8265 { CODE_FOR_mqsaths
, "__MQSATHS", FRV_BUILTIN_MQSATHS
, UNKNOWN
, 0},
8266 { CODE_FOR_mqlclrhs
, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS
, UNKNOWN
, 0},
8267 { CODE_FOR_mqlmths
, "__MQLMTHS", FRV_BUILTIN_MQLMTHS
, UNKNOWN
, 0},
8268 { CODE_FOR_smul
, "__SMUL", FRV_BUILTIN_SMUL
, UNKNOWN
, 0},
8269 { CODE_FOR_umul
, "__UMUL", FRV_BUILTIN_UMUL
, UNKNOWN
, 0},
8270 { CODE_FOR_addss
, "__ADDSS", FRV_BUILTIN_ADDSS
, UNKNOWN
, 0},
8271 { CODE_FOR_subss
, "__SUBSS", FRV_BUILTIN_SUBSS
, UNKNOWN
, 0},
8272 { CODE_FOR_slass
, "__SLASS", FRV_BUILTIN_SLASS
, UNKNOWN
, 0},
8273 { CODE_FOR_scan
, "__SCAN", FRV_BUILTIN_SCAN
, UNKNOWN
, 0}
8276 /* Integer intrinsics that take two arguments and have no return value. */
8278 static struct builtin_description bdesc_int_void2arg
[] =
8280 { CODE_FOR_smass
, "__SMASS", FRV_BUILTIN_SMASS
, UNKNOWN
, 0},
8281 { CODE_FOR_smsss
, "__SMSSS", FRV_BUILTIN_SMSSS
, UNKNOWN
, 0},
8282 { CODE_FOR_smu
, "__SMU", FRV_BUILTIN_SMU
, UNKNOWN
, 0}
8285 static struct builtin_description bdesc_prefetches
[] =
8287 { CODE_FOR_frv_prefetch0
, "__data_prefetch0", FRV_BUILTIN_PREFETCH0
, UNKNOWN
,
8289 { CODE_FOR_frv_prefetch
, "__data_prefetch", FRV_BUILTIN_PREFETCH
, UNKNOWN
, 0}
8292 /* Media intrinsics that take two arguments, the first being an ACC number. */
8294 static struct builtin_description bdesc_cut
[] =
8296 { CODE_FOR_mcut
, "__MCUT", FRV_BUILTIN_MCUT
, UNKNOWN
, 0},
8297 { CODE_FOR_mcutss
, "__MCUTSS", FRV_BUILTIN_MCUTSS
, UNKNOWN
, 0},
8298 { CODE_FOR_mdcutssi
, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI
, UNKNOWN
, 0}
8301 /* Two-argument media intrinsics with an immediate second argument. */
8303 static struct builtin_description bdesc_2argimm
[] =
8305 { CODE_FOR_mrotli
, "__MROTLI", FRV_BUILTIN_MROTLI
, UNKNOWN
, 0},
8306 { CODE_FOR_mrotri
, "__MROTRI", FRV_BUILTIN_MROTRI
, UNKNOWN
, 0},
8307 { CODE_FOR_msllhi
, "__MSLLHI", FRV_BUILTIN_MSLLHI
, UNKNOWN
, 0},
8308 { CODE_FOR_msrlhi
, "__MSRLHI", FRV_BUILTIN_MSRLHI
, UNKNOWN
, 0},
8309 { CODE_FOR_msrahi
, "__MSRAHI", FRV_BUILTIN_MSRAHI
, UNKNOWN
, 0},
8310 { CODE_FOR_mexpdhw
, "__MEXPDHW", FRV_BUILTIN_MEXPDHW
, UNKNOWN
, 0},
8311 { CODE_FOR_mexpdhd
, "__MEXPDHD", FRV_BUILTIN_MEXPDHD
, UNKNOWN
, 0},
8312 { CODE_FOR_mdrotli
, "__MDROTLI", FRV_BUILTIN_MDROTLI
, UNKNOWN
, 0},
8313 { CODE_FOR_mcplhi
, "__MCPLHI", FRV_BUILTIN_MCPLHI
, UNKNOWN
, 0},
8314 { CODE_FOR_mcpli
, "__MCPLI", FRV_BUILTIN_MCPLI
, UNKNOWN
, 0},
8315 { CODE_FOR_mhsetlos
, "__MHSETLOS", FRV_BUILTIN_MHSETLOS
, UNKNOWN
, 0},
8316 { CODE_FOR_mhsetloh
, "__MHSETLOH", FRV_BUILTIN_MHSETLOH
, UNKNOWN
, 0},
8317 { CODE_FOR_mhsethis
, "__MHSETHIS", FRV_BUILTIN_MHSETHIS
, UNKNOWN
, 0},
8318 { CODE_FOR_mhsethih
, "__MHSETHIH", FRV_BUILTIN_MHSETHIH
, UNKNOWN
, 0},
8319 { CODE_FOR_mhdseth
, "__MHDSETH", FRV_BUILTIN_MHDSETH
, UNKNOWN
, 0},
8320 { CODE_FOR_mqsllhi
, "__MQSLLHI", FRV_BUILTIN_MQSLLHI
, UNKNOWN
, 0},
8321 { CODE_FOR_mqsrahi
, "__MQSRAHI", FRV_BUILTIN_MQSRAHI
, UNKNOWN
, 0}
8324 /* Media intrinsics that take two arguments and return void, the first argument
8325 being a pointer to 4 words in memory. */
8327 static struct builtin_description bdesc_void2arg
[] =
8329 { CODE_FOR_mdunpackh
, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH
, UNKNOWN
, 0},
8330 { CODE_FOR_mbtohe
, "__MBTOHE", FRV_BUILTIN_MBTOHE
, UNKNOWN
, 0},
8333 /* Media intrinsics that take three arguments, the first being a const_int that
8334 denotes an accumulator, and that return void. */
8336 static struct builtin_description bdesc_void3arg
[] =
8338 { CODE_FOR_mcpxrs
, "__MCPXRS", FRV_BUILTIN_MCPXRS
, UNKNOWN
, 0},
8339 { CODE_FOR_mcpxru
, "__MCPXRU", FRV_BUILTIN_MCPXRU
, UNKNOWN
, 0},
8340 { CODE_FOR_mcpxis
, "__MCPXIS", FRV_BUILTIN_MCPXIS
, UNKNOWN
, 0},
8341 { CODE_FOR_mcpxiu
, "__MCPXIU", FRV_BUILTIN_MCPXIU
, UNKNOWN
, 0},
8342 { CODE_FOR_mmulhs
, "__MMULHS", FRV_BUILTIN_MMULHS
, UNKNOWN
, 0},
8343 { CODE_FOR_mmulhu
, "__MMULHU", FRV_BUILTIN_MMULHU
, UNKNOWN
, 0},
8344 { CODE_FOR_mmulxhs
, "__MMULXHS", FRV_BUILTIN_MMULXHS
, UNKNOWN
, 0},
8345 { CODE_FOR_mmulxhu
, "__MMULXHU", FRV_BUILTIN_MMULXHU
, UNKNOWN
, 0},
8346 { CODE_FOR_mmachs
, "__MMACHS", FRV_BUILTIN_MMACHS
, UNKNOWN
, 0},
8347 { CODE_FOR_mmachu
, "__MMACHU", FRV_BUILTIN_MMACHU
, UNKNOWN
, 0},
8348 { CODE_FOR_mmrdhs
, "__MMRDHS", FRV_BUILTIN_MMRDHS
, UNKNOWN
, 0},
8349 { CODE_FOR_mmrdhu
, "__MMRDHU", FRV_BUILTIN_MMRDHU
, UNKNOWN
, 0},
8350 { CODE_FOR_mqcpxrs
, "__MQCPXRS", FRV_BUILTIN_MQCPXRS
, UNKNOWN
, 0},
8351 { CODE_FOR_mqcpxru
, "__MQCPXRU", FRV_BUILTIN_MQCPXRU
, UNKNOWN
, 0},
8352 { CODE_FOR_mqcpxis
, "__MQCPXIS", FRV_BUILTIN_MQCPXIS
, UNKNOWN
, 0},
8353 { CODE_FOR_mqcpxiu
, "__MQCPXIU", FRV_BUILTIN_MQCPXIU
, UNKNOWN
, 0},
8354 { CODE_FOR_mqmulhs
, "__MQMULHS", FRV_BUILTIN_MQMULHS
, UNKNOWN
, 0},
8355 { CODE_FOR_mqmulhu
, "__MQMULHU", FRV_BUILTIN_MQMULHU
, UNKNOWN
, 0},
8356 { CODE_FOR_mqmulxhs
, "__MQMULXHS", FRV_BUILTIN_MQMULXHS
, UNKNOWN
, 0},
8357 { CODE_FOR_mqmulxhu
, "__MQMULXHU", FRV_BUILTIN_MQMULXHU
, UNKNOWN
, 0},
8358 { CODE_FOR_mqmachs
, "__MQMACHS", FRV_BUILTIN_MQMACHS
, UNKNOWN
, 0},
8359 { CODE_FOR_mqmachu
, "__MQMACHU", FRV_BUILTIN_MQMACHU
, UNKNOWN
, 0},
8360 { CODE_FOR_mqxmachs
, "__MQXMACHS", FRV_BUILTIN_MQXMACHS
, UNKNOWN
, 0},
8361 { CODE_FOR_mqxmacxhs
, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS
, UNKNOWN
, 0},
8362 { CODE_FOR_mqmacxhs
, "__MQMACXHS", FRV_BUILTIN_MQMACXHS
, UNKNOWN
, 0}
8365 /* Media intrinsics that take two accumulator numbers as argument and
8368 static struct builtin_description bdesc_voidacc
[] =
8370 { CODE_FOR_maddaccs
, "__MADDACCS", FRV_BUILTIN_MADDACCS
, UNKNOWN
, 0},
8371 { CODE_FOR_msubaccs
, "__MSUBACCS", FRV_BUILTIN_MSUBACCS
, UNKNOWN
, 0},
8372 { CODE_FOR_masaccs
, "__MASACCS", FRV_BUILTIN_MASACCS
, UNKNOWN
, 0},
8373 { CODE_FOR_mdaddaccs
, "__MDADDACCS", FRV_BUILTIN_MDADDACCS
, UNKNOWN
, 0},
8374 { CODE_FOR_mdsubaccs
, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS
, UNKNOWN
, 0},
8375 { CODE_FOR_mdasaccs
, "__MDASACCS", FRV_BUILTIN_MDASACCS
, UNKNOWN
, 0}
8378 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8379 a normal move and the ICODE is for the membar. */
8381 static struct builtin_description bdesc_loads
[] =
8383 { CODE_FOR_optional_membar_qi
, "__builtin_read8",
8384 FRV_BUILTIN_READ8
, UNKNOWN
, 0},
8385 { CODE_FOR_optional_membar_hi
, "__builtin_read16",
8386 FRV_BUILTIN_READ16
, UNKNOWN
, 0},
8387 { CODE_FOR_optional_membar_si
, "__builtin_read32",
8388 FRV_BUILTIN_READ32
, UNKNOWN
, 0},
8389 { CODE_FOR_optional_membar_di
, "__builtin_read64",
8390 FRV_BUILTIN_READ64
, UNKNOWN
, 0}
8393 /* Likewise stores. */
8395 static struct builtin_description bdesc_stores
[] =
8397 { CODE_FOR_optional_membar_qi
, "__builtin_write8",
8398 FRV_BUILTIN_WRITE8
, UNKNOWN
, 0},
8399 { CODE_FOR_optional_membar_hi
, "__builtin_write16",
8400 FRV_BUILTIN_WRITE16
, UNKNOWN
, 0},
8401 { CODE_FOR_optional_membar_si
, "__builtin_write32",
8402 FRV_BUILTIN_WRITE32
, UNKNOWN
, 0},
8403 { CODE_FOR_optional_membar_di
, "__builtin_write64",
8404 FRV_BUILTIN_WRITE64
, UNKNOWN
, 0},
8407 /* Initialize media builtins. */
8410 frv_init_builtins (void)
8412 tree accumulator
= integer_type_node
;
8413 tree integer
= integer_type_node
;
8414 tree voidt
= void_type_node
;
8415 tree uhalf
= short_unsigned_type_node
;
8416 tree sword1
= long_integer_type_node
;
8417 tree uword1
= long_unsigned_type_node
;
8418 tree sword2
= long_long_integer_type_node
;
8419 tree uword2
= long_long_unsigned_type_node
;
8420 tree uword4
= build_pointer_type (uword1
);
8421 tree vptr
= build_pointer_type (build_type_variant (void_type_node
, 0, 1));
8422 tree ubyte
= unsigned_char_type_node
;
8423 tree iacc
= integer_type_node
;
8425 #define UNARY(RET, T1) \
8426 build_function_type_list (RET, T1, NULL_TREE)
8428 #define BINARY(RET, T1, T2) \
8429 build_function_type_list (RET, T1, T2, NULL_TREE)
8431 #define TRINARY(RET, T1, T2, T3) \
8432 build_function_type_list (RET, T1, T2, T3, NULL_TREE)
8434 #define QUAD(RET, T1, T2, T3, T4) \
8435 build_function_type_list (RET, T1, T2, T3, T4, NULL_TREE)
8437 tree void_ftype_void
= build_function_type_list (voidt
, NULL_TREE
);
8439 tree void_ftype_acc
= UNARY (voidt
, accumulator
);
8440 tree void_ftype_uw4_uw1
= BINARY (voidt
, uword4
, uword1
);
8441 tree void_ftype_uw4_uw2
= BINARY (voidt
, uword4
, uword2
);
8442 tree void_ftype_acc_uw1
= BINARY (voidt
, accumulator
, uword1
);
8443 tree void_ftype_acc_acc
= BINARY (voidt
, accumulator
, accumulator
);
8444 tree void_ftype_acc_uw1_uw1
= TRINARY (voidt
, accumulator
, uword1
, uword1
);
8445 tree void_ftype_acc_sw1_sw1
= TRINARY (voidt
, accumulator
, sword1
, sword1
);
8446 tree void_ftype_acc_uw2_uw2
= TRINARY (voidt
, accumulator
, uword2
, uword2
);
8447 tree void_ftype_acc_sw2_sw2
= TRINARY (voidt
, accumulator
, sword2
, sword2
);
8449 tree uw1_ftype_uw1
= UNARY (uword1
, uword1
);
8450 tree uw1_ftype_sw1
= UNARY (uword1
, sword1
);
8451 tree uw1_ftype_uw2
= UNARY (uword1
, uword2
);
8452 tree uw1_ftype_acc
= UNARY (uword1
, accumulator
);
8453 tree uw1_ftype_uh_uh
= BINARY (uword1
, uhalf
, uhalf
);
8454 tree uw1_ftype_uw1_uw1
= BINARY (uword1
, uword1
, uword1
);
8455 tree uw1_ftype_uw1_int
= BINARY (uword1
, uword1
, integer
);
8456 tree uw1_ftype_acc_uw1
= BINARY (uword1
, accumulator
, uword1
);
8457 tree uw1_ftype_acc_sw1
= BINARY (uword1
, accumulator
, sword1
);
8458 tree uw1_ftype_uw2_uw1
= BINARY (uword1
, uword2
, uword1
);
8459 tree uw1_ftype_uw2_int
= BINARY (uword1
, uword2
, integer
);
8461 tree sw1_ftype_int
= UNARY (sword1
, integer
);
8462 tree sw1_ftype_sw1_sw1
= BINARY (sword1
, sword1
, sword1
);
8463 tree sw1_ftype_sw1_int
= BINARY (sword1
, sword1
, integer
);
8465 tree uw2_ftype_uw1
= UNARY (uword2
, uword1
);
8466 tree uw2_ftype_uw1_int
= BINARY (uword2
, uword1
, integer
);
8467 tree uw2_ftype_uw2_uw2
= BINARY (uword2
, uword2
, uword2
);
8468 tree uw2_ftype_uw2_int
= BINARY (uword2
, uword2
, integer
);
8469 tree uw2_ftype_acc_int
= BINARY (uword2
, accumulator
, integer
);
8470 tree uw2_ftype_uh_uh_uh_uh
= QUAD (uword2
, uhalf
, uhalf
, uhalf
, uhalf
);
8472 tree sw2_ftype_sw2_sw2
= BINARY (sword2
, sword2
, sword2
);
8473 tree sw2_ftype_sw2_int
= BINARY (sword2
, sword2
, integer
);
8474 tree uw2_ftype_uw1_uw1
= BINARY (uword2
, uword1
, uword1
);
8475 tree sw2_ftype_sw1_sw1
= BINARY (sword2
, sword1
, sword1
);
8476 tree void_ftype_sw1_sw1
= BINARY (voidt
, sword1
, sword1
);
8477 tree void_ftype_iacc_sw2
= BINARY (voidt
, iacc
, sword2
);
8478 tree void_ftype_iacc_sw1
= BINARY (voidt
, iacc
, sword1
);
8479 tree sw1_ftype_sw1
= UNARY (sword1
, sword1
);
8480 tree sw2_ftype_iacc
= UNARY (sword2
, iacc
);
8481 tree sw1_ftype_iacc
= UNARY (sword1
, iacc
);
8482 tree void_ftype_ptr
= UNARY (voidt
, const_ptr_type_node
);
8483 tree uw1_ftype_vptr
= UNARY (uword1
, vptr
);
8484 tree uw2_ftype_vptr
= UNARY (uword2
, vptr
);
8485 tree void_ftype_vptr_ub
= BINARY (voidt
, vptr
, ubyte
);
8486 tree void_ftype_vptr_uh
= BINARY (voidt
, vptr
, uhalf
);
8487 tree void_ftype_vptr_uw1
= BINARY (voidt
, vptr
, uword1
);
8488 tree void_ftype_vptr_uw2
= BINARY (voidt
, vptr
, uword2
);
8490 def_builtin ("__MAND", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAND
);
8491 def_builtin ("__MOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MOR
);
8492 def_builtin ("__MXOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MXOR
);
8493 def_builtin ("__MNOT", uw1_ftype_uw1
, FRV_BUILTIN_MNOT
);
8494 def_builtin ("__MROTLI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTLI
);
8495 def_builtin ("__MROTRI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTRI
);
8496 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1
, FRV_BUILTIN_MWCUT
);
8497 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAVEH
);
8498 def_builtin ("__MSLLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSLLHI
);
8499 def_builtin ("__MSRLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSRLHI
);
8500 def_builtin ("__MSRAHI", sw1_ftype_sw1_int
, FRV_BUILTIN_MSRAHI
);
8501 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSATHS
);
8502 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSATHU
);
8503 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MADDHSS
);
8504 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MADDHUS
);
8505 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSUBHSS
);
8506 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSUBHUS
);
8507 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULHS
);
8508 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULHU
);
8509 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULXHS
);
8510 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULXHU
);
8511 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMACHS
);
8512 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMACHU
);
8513 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMRDHS
);
8514 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMRDHU
);
8515 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQADDHSS
);
8516 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQADDHUS
);
8517 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSUBHSS
);
8518 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQSUBHUS
);
8519 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULHS
);
8520 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULHU
);
8521 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULXHS
);
8522 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULXHU
);
8523 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACHS
);
8524 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMACHU
);
8525 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXRS
);
8526 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXRU
);
8527 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXIS
);
8528 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXIU
);
8529 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXRS
);
8530 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXRU
);
8531 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXIS
);
8532 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXIU
);
8533 def_builtin ("__MCUT", uw1_ftype_acc_uw1
, FRV_BUILTIN_MCUT
);
8534 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1
, FRV_BUILTIN_MCUTSS
);
8535 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int
, FRV_BUILTIN_MEXPDHW
);
8536 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int
, FRV_BUILTIN_MEXPDHD
);
8537 def_builtin ("__MPACKH", uw1_ftype_uh_uh
, FRV_BUILTIN_MPACKH
);
8538 def_builtin ("__MUNPACKH", uw2_ftype_uw1
, FRV_BUILTIN_MUNPACKH
);
8539 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh
, FRV_BUILTIN_MDPACKH
);
8540 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2
, FRV_BUILTIN_MDUNPACKH
);
8541 def_builtin ("__MBTOH", uw2_ftype_uw1
, FRV_BUILTIN_MBTOH
);
8542 def_builtin ("__MHTOB", uw1_ftype_uw2
, FRV_BUILTIN_MHTOB
);
8543 def_builtin ("__MBTOHE", void_ftype_uw4_uw1
, FRV_BUILTIN_MBTOHE
);
8544 def_builtin ("__MCLRACC", void_ftype_acc
, FRV_BUILTIN_MCLRACC
);
8545 def_builtin ("__MCLRACCA", void_ftype_void
, FRV_BUILTIN_MCLRACCA
);
8546 def_builtin ("__MRDACC", uw1_ftype_acc
, FRV_BUILTIN_MRDACC
);
8547 def_builtin ("__MRDACCG", uw1_ftype_acc
, FRV_BUILTIN_MRDACCG
);
8548 def_builtin ("__MWTACC", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACC
);
8549 def_builtin ("__MWTACCG", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACCG
);
8550 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP1
);
8551 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP2
);
8552 def_builtin ("__MTRAP", void_ftype_void
, FRV_BUILTIN_MTRAP
);
8553 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACHS
);
8554 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACXHS
);
8555 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACXHS
);
8556 def_builtin ("__MADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MADDACCS
);
8557 def_builtin ("__MSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MSUBACCS
);
8558 def_builtin ("__MASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MASACCS
);
8559 def_builtin ("__MDADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDADDACCS
);
8560 def_builtin ("__MDSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDSUBACCS
);
8561 def_builtin ("__MDASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDASACCS
);
8562 def_builtin ("__MABSHS", uw1_ftype_sw1
, FRV_BUILTIN_MABSHS
);
8563 def_builtin ("__MDROTLI", uw2_ftype_uw2_int
, FRV_BUILTIN_MDROTLI
);
8564 def_builtin ("__MCPLHI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLHI
);
8565 def_builtin ("__MCPLI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLI
);
8566 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int
, FRV_BUILTIN_MDCUTSSI
);
8567 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSATHS
);
8568 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETLOS
);
8569 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETHIS
);
8570 def_builtin ("__MHDSETS", sw1_ftype_int
, FRV_BUILTIN_MHDSETS
);
8571 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETLOH
);
8572 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETHIH
);
8573 def_builtin ("__MHDSETH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHDSETH
);
8574 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQLCLRHS
);
8575 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQLMTHS
);
8576 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int
, FRV_BUILTIN_MQSLLHI
);
8577 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int
, FRV_BUILTIN_MQSRAHI
);
8578 def_builtin ("__SMUL", sw2_ftype_sw1_sw1
, FRV_BUILTIN_SMUL
);
8579 def_builtin ("__UMUL", uw2_ftype_uw1_uw1
, FRV_BUILTIN_UMUL
);
8580 def_builtin ("__SMASS", void_ftype_sw1_sw1
, FRV_BUILTIN_SMASS
);
8581 def_builtin ("__SMSSS", void_ftype_sw1_sw1
, FRV_BUILTIN_SMSSS
);
8582 def_builtin ("__SMU", void_ftype_sw1_sw1
, FRV_BUILTIN_SMU
);
8583 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_ADDSS
);
8584 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SUBSS
);
8585 def_builtin ("__SLASS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SLASS
);
8586 def_builtin ("__SCAN", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SCAN
);
8587 def_builtin ("__SCUTSS", sw1_ftype_sw1
, FRV_BUILTIN_SCUTSS
);
8588 def_builtin ("__IACCreadll", sw2_ftype_iacc
, FRV_BUILTIN_IACCreadll
);
8589 def_builtin ("__IACCreadl", sw1_ftype_iacc
, FRV_BUILTIN_IACCreadl
);
8590 def_builtin ("__IACCsetll", void_ftype_iacc_sw2
, FRV_BUILTIN_IACCsetll
);
8591 def_builtin ("__IACCsetl", void_ftype_iacc_sw1
, FRV_BUILTIN_IACCsetl
);
8592 def_builtin ("__data_prefetch0", void_ftype_ptr
, FRV_BUILTIN_PREFETCH0
);
8593 def_builtin ("__data_prefetch", void_ftype_ptr
, FRV_BUILTIN_PREFETCH
);
8594 def_builtin ("__builtin_read8", uw1_ftype_vptr
, FRV_BUILTIN_READ8
);
8595 def_builtin ("__builtin_read16", uw1_ftype_vptr
, FRV_BUILTIN_READ16
);
8596 def_builtin ("__builtin_read32", uw1_ftype_vptr
, FRV_BUILTIN_READ32
);
8597 def_builtin ("__builtin_read64", uw2_ftype_vptr
, FRV_BUILTIN_READ64
);
8599 def_builtin ("__builtin_write8", void_ftype_vptr_ub
, FRV_BUILTIN_WRITE8
);
8600 def_builtin ("__builtin_write16", void_ftype_vptr_uh
, FRV_BUILTIN_WRITE16
);
8601 def_builtin ("__builtin_write32", void_ftype_vptr_uw1
, FRV_BUILTIN_WRITE32
);
8602 def_builtin ("__builtin_write64", void_ftype_vptr_uw2
, FRV_BUILTIN_WRITE64
);
8610 /* Set the names for various arithmetic operations according to the
8613 frv_init_libfuncs (void)
8615 set_optab_libfunc (smod_optab
, SImode
, "__modi");
8616 set_optab_libfunc (umod_optab
, SImode
, "__umodi");
8618 set_optab_libfunc (add_optab
, DImode
, "__addll");
8619 set_optab_libfunc (sub_optab
, DImode
, "__subll");
8620 set_optab_libfunc (smul_optab
, DImode
, "__mulll");
8621 set_optab_libfunc (sdiv_optab
, DImode
, "__divll");
8622 set_optab_libfunc (smod_optab
, DImode
, "__modll");
8623 set_optab_libfunc (umod_optab
, DImode
, "__umodll");
8624 set_optab_libfunc (and_optab
, DImode
, "__andll");
8625 set_optab_libfunc (ior_optab
, DImode
, "__orll");
8626 set_optab_libfunc (xor_optab
, DImode
, "__xorll");
8627 set_optab_libfunc (one_cmpl_optab
, DImode
, "__notll");
8629 set_optab_libfunc (add_optab
, SFmode
, "__addf");
8630 set_optab_libfunc (sub_optab
, SFmode
, "__subf");
8631 set_optab_libfunc (smul_optab
, SFmode
, "__mulf");
8632 set_optab_libfunc (sdiv_optab
, SFmode
, "__divf");
8634 set_optab_libfunc (add_optab
, DFmode
, "__addd");
8635 set_optab_libfunc (sub_optab
, DFmode
, "__subd");
8636 set_optab_libfunc (smul_optab
, DFmode
, "__muld");
8637 set_optab_libfunc (sdiv_optab
, DFmode
, "__divd");
8639 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__ftod");
8640 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__dtof");
8642 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__ftoi");
8643 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
8644 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__dtoi");
8645 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
8647 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__ftoui");
8648 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
8649 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__dtoui");
8650 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
8652 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__itof");
8653 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__lltof");
8654 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__itod");
8655 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__lltod");
8658 /* Convert an integer constant to an accumulator register. ICODE is the
8659 code of the target instruction, OPNUM is the number of the
8660 accumulator operand and OPVAL is the constant integer. Try both
8661 ACC and ACCG registers; only report an error if neither fit the
8665 frv_int_to_acc (enum insn_code icode
, int opnum
, rtx opval
)
8670 /* ACCs and ACCGs are implicit global registers if media intrinsics
8671 are being used. We set up this lazily to avoid creating lots of
8672 unnecessary call_insn rtl in non-media code. */
8673 for (i
= 0; i
<= ACC_MASK
; i
++)
8674 if ((i
& ACC_MASK
) == i
)
8675 global_regs
[i
+ ACC_FIRST
] = global_regs
[i
+ ACCG_FIRST
] = 1;
8677 if (GET_CODE (opval
) != CONST_INT
)
8679 error ("accumulator is not a constant integer");
8682 if ((INTVAL (opval
) & ~ACC_MASK
) != 0)
8684 error ("accumulator number is out of bounds");
8688 reg
= gen_rtx_REG (insn_data
[icode
].operand
[opnum
].mode
,
8689 ACC_FIRST
+ INTVAL (opval
));
8690 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8691 SET_REGNO (reg
, ACCG_FIRST
+ INTVAL (opval
));
8693 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8695 error ("inappropriate accumulator for %qs", insn_data
[icode
].name
);
8701 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8704 static enum machine_mode
8705 frv_matching_accg_mode (enum machine_mode mode
)
8723 /* Given that a __builtin_read or __builtin_write function is accessing
8724 address ADDRESS, return the value that should be used as operand 1
8728 frv_io_address_cookie (rtx address
)
8730 return (GET_CODE (address
) == CONST_INT
8731 ? GEN_INT (INTVAL (address
) / 8 * 8)
8735 /* Return the accumulator guard that should be paired with accumulator
8736 register ACC. The mode of the returned register is in the same
8737 class as ACC, but is four times smaller. */
8740 frv_matching_accg_for_acc (rtx acc
)
8742 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc
)),
8743 REGNO (acc
) - ACC_FIRST
+ ACCG_FIRST
);
8746 /* Read the requested argument from the call EXP given by INDEX.
8747 Return the value as an rtx. */
8750 frv_read_argument (tree exp
, unsigned int index
)
8752 return expand_normal (CALL_EXPR_ARG (exp
, index
));
8755 /* Like frv_read_argument, but interpret the argument as the number
8756 of an IACC register and return a (reg:MODE ...) rtx for it. */
8759 frv_read_iacc_argument (enum machine_mode mode
, tree call
,
8765 op
= frv_read_argument (call
, index
);
8766 if (GET_CODE (op
) != CONST_INT
8768 || INTVAL (op
) > IACC_LAST
- IACC_FIRST
8769 || ((INTVAL (op
) * 4) & (GET_MODE_SIZE (mode
) - 1)) != 0)
8771 error ("invalid IACC argument");
8775 /* IACCs are implicit global registers. We set up this lazily to
8776 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8778 regno
= INTVAL (op
) + IACC_FIRST
;
8779 for (i
= 0; i
< HARD_REGNO_NREGS (regno
, mode
); i
++)
8780 global_regs
[regno
+ i
] = 1;
8782 return gen_rtx_REG (mode
, regno
);
8785 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8786 The instruction should require a constant operand of some sort. The
8787 function prints an error if OPVAL is not valid. */
8790 frv_check_constant_argument (enum insn_code icode
, int opnum
, rtx opval
)
8792 if (GET_CODE (opval
) != CONST_INT
)
8794 error ("%qs expects a constant argument", insn_data
[icode
].name
);
8797 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (opval
, VOIDmode
))
8799 error ("constant argument out of range for %qs", insn_data
[icode
].name
);
8805 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8806 if it's not null, has the right mode, and satisfies operand 0's
8810 frv_legitimize_target (enum insn_code icode
, rtx target
)
8812 enum machine_mode mode
= insn_data
[icode
].operand
[0].mode
;
8815 || GET_MODE (target
) != mode
8816 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode
))
8817 return gen_reg_rtx (mode
);
8822 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8823 check whether ARG satisfies the operand's constraints. If it doesn't,
8824 copy ARG to a temporary register and return that. Otherwise return ARG
8828 frv_legitimize_argument (enum insn_code icode
, int opnum
, rtx arg
)
8830 enum machine_mode mode
= insn_data
[icode
].operand
[opnum
].mode
;
8832 if ((*insn_data
[icode
].operand
[opnum
].predicate
) (arg
, mode
))
8835 return copy_to_mode_reg (mode
, arg
);
8838 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8841 frv_volatile_memref (enum machine_mode mode
, rtx arg
)
8845 mem
= gen_rtx_MEM (mode
, memory_address (mode
, arg
));
8846 MEM_VOLATILE_P (mem
) = 1;
8850 /* Expand builtins that take a single, constant argument. At the moment,
8851 only MHDSETS falls into this category. */
8854 frv_expand_set_builtin (enum insn_code icode
, tree call
, rtx target
)
8857 rtx op0
= frv_read_argument (call
, 0);
8859 if (! frv_check_constant_argument (icode
, 1, op0
))
8862 target
= frv_legitimize_target (icode
, target
);
8863 pat
= GEN_FCN (icode
) (target
, op0
);
8871 /* Expand builtins that take one operand. */
8874 frv_expand_unop_builtin (enum insn_code icode
, tree call
, rtx target
)
8877 rtx op0
= frv_read_argument (call
, 0);
8879 target
= frv_legitimize_target (icode
, target
);
8880 op0
= frv_legitimize_argument (icode
, 1, op0
);
8881 pat
= GEN_FCN (icode
) (target
, op0
);
8889 /* Expand builtins that take two operands. */
8892 frv_expand_binop_builtin (enum insn_code icode
, tree call
, rtx target
)
8895 rtx op0
= frv_read_argument (call
, 0);
8896 rtx op1
= frv_read_argument (call
, 1);
8898 target
= frv_legitimize_target (icode
, target
);
8899 op0
= frv_legitimize_argument (icode
, 1, op0
);
8900 op1
= frv_legitimize_argument (icode
, 2, op1
);
8901 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
8909 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8913 frv_expand_cut_builtin (enum insn_code icode
, tree call
, rtx target
)
8916 rtx op0
= frv_read_argument (call
, 0);
8917 rtx op1
= frv_read_argument (call
, 1);
8920 target
= frv_legitimize_target (icode
, target
);
8921 op0
= frv_int_to_acc (icode
, 1, op0
);
8925 if (icode
== CODE_FOR_mdcutssi
|| GET_CODE (op1
) == CONST_INT
)
8927 if (! frv_check_constant_argument (icode
, 2, op1
))
8931 op1
= frv_legitimize_argument (icode
, 2, op1
);
8933 op2
= frv_matching_accg_for_acc (op0
);
8934 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
8942 /* Expand builtins that take two operands and the second is immediate. */
8945 frv_expand_binopimm_builtin (enum insn_code icode
, tree call
, rtx target
)
8948 rtx op0
= frv_read_argument (call
, 0);
8949 rtx op1
= frv_read_argument (call
, 1);
8951 if (! frv_check_constant_argument (icode
, 2, op1
))
8954 target
= frv_legitimize_target (icode
, target
);
8955 op0
= frv_legitimize_argument (icode
, 1, op0
);
8956 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
8964 /* Expand builtins that take two operands, the first operand being a pointer to
8965 ints and return void. */
8968 frv_expand_voidbinop_builtin (enum insn_code icode
, tree call
)
8971 rtx op0
= frv_read_argument (call
, 0);
8972 rtx op1
= frv_read_argument (call
, 1);
8973 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
8976 if (GET_CODE (op0
) != MEM
)
8980 if (! offsettable_address_p (0, mode0
, op0
))
8982 reg
= gen_reg_rtx (Pmode
);
8983 emit_insn (gen_rtx_SET (VOIDmode
, reg
, op0
));
8986 op0
= gen_rtx_MEM (SImode
, reg
);
8989 addr
= XEXP (op0
, 0);
8990 if (! offsettable_address_p (0, mode0
, addr
))
8991 addr
= copy_to_mode_reg (Pmode
, op0
);
8993 op0
= change_address (op0
, V4SImode
, addr
);
8994 op1
= frv_legitimize_argument (icode
, 1, op1
);
8995 pat
= GEN_FCN (icode
) (op0
, op1
);
9003 /* Expand builtins that take two long operands and return void. */
9006 frv_expand_int_void2arg (enum insn_code icode
, tree call
)
9009 rtx op0
= frv_read_argument (call
, 0);
9010 rtx op1
= frv_read_argument (call
, 1);
9012 op0
= frv_legitimize_argument (icode
, 1, op0
);
9013 op1
= frv_legitimize_argument (icode
, 1, op1
);
9014 pat
= GEN_FCN (icode
) (op0
, op1
);
9022 /* Expand prefetch builtins. These take a single address as argument. */
9025 frv_expand_prefetches (enum insn_code icode
, tree call
)
9028 rtx op0
= frv_read_argument (call
, 0);
9030 pat
= GEN_FCN (icode
) (force_reg (Pmode
, op0
));
9038 /* Expand builtins that take three operands and return void. The first
9039 argument must be a constant that describes a pair or quad accumulators. A
9040 fourth argument is created that is the accumulator guard register that
9041 corresponds to the accumulator. */
9044 frv_expand_voidtriop_builtin (enum insn_code icode
, tree call
)
9047 rtx op0
= frv_read_argument (call
, 0);
9048 rtx op1
= frv_read_argument (call
, 1);
9049 rtx op2
= frv_read_argument (call
, 2);
9052 op0
= frv_int_to_acc (icode
, 0, op0
);
9056 op1
= frv_legitimize_argument (icode
, 1, op1
);
9057 op2
= frv_legitimize_argument (icode
, 2, op2
);
9058 op3
= frv_matching_accg_for_acc (op0
);
9059 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9067 /* Expand builtins that perform accumulator-to-accumulator operations.
9068 These builtins take two accumulator numbers as argument and return
9072 frv_expand_voidaccop_builtin (enum insn_code icode
, tree call
)
9075 rtx op0
= frv_read_argument (call
, 0);
9076 rtx op1
= frv_read_argument (call
, 1);
9080 op0
= frv_int_to_acc (icode
, 0, op0
);
9084 op1
= frv_int_to_acc (icode
, 1, op1
);
9088 op2
= frv_matching_accg_for_acc (op0
);
9089 op3
= frv_matching_accg_for_acc (op1
);
9090 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9098 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9099 membar and TARGET_MODE is the mode that the loaded value should have. */
9102 frv_expand_load_builtin (enum insn_code icode
, enum machine_mode target_mode
,
9103 tree call
, rtx target
)
9105 rtx op0
= frv_read_argument (call
, 0);
9106 rtx cookie
= frv_io_address_cookie (op0
);
9108 if (target
== 0 || !REG_P (target
))
9109 target
= gen_reg_rtx (target_mode
);
9110 op0
= frv_volatile_memref (insn_data
[icode
].operand
[0].mode
, op0
);
9111 convert_move (target
, op0
, 1);
9112 emit_insn (GEN_FCN (icode
) (copy_rtx (op0
), cookie
, GEN_INT (FRV_IO_READ
)));
9113 cfun
->machine
->has_membar_p
= 1;
9117 /* Likewise __builtin_write* functions. */
9120 frv_expand_store_builtin (enum insn_code icode
, tree call
)
9122 rtx op0
= frv_read_argument (call
, 0);
9123 rtx op1
= frv_read_argument (call
, 1);
9124 rtx cookie
= frv_io_address_cookie (op0
);
9126 op0
= frv_volatile_memref (insn_data
[icode
].operand
[0].mode
, op0
);
9127 convert_move (op0
, force_reg (insn_data
[icode
].operand
[0].mode
, op1
), 1);
9128 emit_insn (GEN_FCN (icode
) (copy_rtx (op0
), cookie
, GEN_INT (FRV_IO_WRITE
)));
9129 cfun
->machine
->has_membar_p
= 1;
9133 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9134 each argument forms one word of the two double-word input registers.
9135 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9136 to put the return value. */
9139 frv_expand_mdpackh_builtin (tree call
, rtx target
)
9141 enum insn_code icode
= CODE_FOR_mdpackh
;
9143 rtx arg1
= frv_read_argument (call
, 0);
9144 rtx arg2
= frv_read_argument (call
, 1);
9145 rtx arg3
= frv_read_argument (call
, 2);
9146 rtx arg4
= frv_read_argument (call
, 3);
9148 target
= frv_legitimize_target (icode
, target
);
9149 op0
= gen_reg_rtx (DImode
);
9150 op1
= gen_reg_rtx (DImode
);
9152 /* The high half of each word is not explicitly initialized, so indicate
9153 that the input operands are not live before this point. */
9157 /* Move each argument into the low half of its associated input word. */
9158 emit_move_insn (simplify_gen_subreg (HImode
, op0
, DImode
, 2), arg1
);
9159 emit_move_insn (simplify_gen_subreg (HImode
, op0
, DImode
, 6), arg2
);
9160 emit_move_insn (simplify_gen_subreg (HImode
, op1
, DImode
, 2), arg3
);
9161 emit_move_insn (simplify_gen_subreg (HImode
, op1
, DImode
, 6), arg4
);
9163 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
9171 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9172 number as argument. */
9175 frv_expand_mclracc_builtin (tree call
)
9177 enum insn_code icode
= CODE_FOR_mclracc
;
9179 rtx op0
= frv_read_argument (call
, 0);
9181 op0
= frv_int_to_acc (icode
, 0, op0
);
9185 pat
= GEN_FCN (icode
) (op0
);
9192 /* Expand builtins that take no arguments. */
9195 frv_expand_noargs_builtin (enum insn_code icode
)
9197 rtx pat
= GEN_FCN (icode
) (const0_rtx
);
9204 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9205 number or accumulator guard number as argument and return an SI integer. */
9208 frv_expand_mrdacc_builtin (enum insn_code icode
, tree call
)
9211 rtx target
= gen_reg_rtx (SImode
);
9212 rtx op0
= frv_read_argument (call
, 0);
9214 op0
= frv_int_to_acc (icode
, 1, op0
);
9218 pat
= GEN_FCN (icode
) (target
, op0
);
9226 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9227 accumulator guard as their first argument and an SImode value as their
9231 frv_expand_mwtacc_builtin (enum insn_code icode
, tree call
)
9234 rtx op0
= frv_read_argument (call
, 0);
9235 rtx op1
= frv_read_argument (call
, 1);
9237 op0
= frv_int_to_acc (icode
, 0, op0
);
9241 op1
= frv_legitimize_argument (icode
, 1, op1
);
9242 pat
= GEN_FCN (icode
) (op0
, op1
);
9249 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9250 to move DImode values into and out of IACC0. */
9253 frv_split_iacc_move (rtx dest
, rtx src
)
9255 enum machine_mode inner
;
9258 inner
= GET_MODE (dest
);
9259 for (i
= 0; i
< GET_MODE_SIZE (inner
); i
+= GET_MODE_SIZE (SImode
))
9260 emit_move_insn (simplify_gen_subreg (SImode
, dest
, inner
, i
),
9261 simplify_gen_subreg (SImode
, src
, inner
, i
));
9264 /* Expand builtins. */
9267 frv_expand_builtin (tree exp
,
9269 rtx subtarget ATTRIBUTE_UNUSED
,
9270 enum machine_mode mode ATTRIBUTE_UNUSED
,
9271 int ignore ATTRIBUTE_UNUSED
)
9273 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9274 unsigned fcode
= (unsigned)DECL_FUNCTION_CODE (fndecl
);
9276 struct builtin_description
*d
;
9278 if (fcode
< FRV_BUILTIN_FIRST_NONMEDIA
&& !TARGET_MEDIA
)
9280 error ("media functions are not available unless -mmedia is used");
9286 case FRV_BUILTIN_MCOP1
:
9287 case FRV_BUILTIN_MCOP2
:
9288 case FRV_BUILTIN_MDUNPACKH
:
9289 case FRV_BUILTIN_MBTOHE
:
9290 if (! TARGET_MEDIA_REV1
)
9292 error ("this media function is only available on the fr500");
9297 case FRV_BUILTIN_MQXMACHS
:
9298 case FRV_BUILTIN_MQXMACXHS
:
9299 case FRV_BUILTIN_MQMACXHS
:
9300 case FRV_BUILTIN_MADDACCS
:
9301 case FRV_BUILTIN_MSUBACCS
:
9302 case FRV_BUILTIN_MASACCS
:
9303 case FRV_BUILTIN_MDADDACCS
:
9304 case FRV_BUILTIN_MDSUBACCS
:
9305 case FRV_BUILTIN_MDASACCS
:
9306 case FRV_BUILTIN_MABSHS
:
9307 case FRV_BUILTIN_MDROTLI
:
9308 case FRV_BUILTIN_MCPLHI
:
9309 case FRV_BUILTIN_MCPLI
:
9310 case FRV_BUILTIN_MDCUTSSI
:
9311 case FRV_BUILTIN_MQSATHS
:
9312 case FRV_BUILTIN_MHSETLOS
:
9313 case FRV_BUILTIN_MHSETLOH
:
9314 case FRV_BUILTIN_MHSETHIS
:
9315 case FRV_BUILTIN_MHSETHIH
:
9316 case FRV_BUILTIN_MHDSETS
:
9317 case FRV_BUILTIN_MHDSETH
:
9318 if (! TARGET_MEDIA_REV2
)
9320 error ("this media function is only available on the fr400"
9326 case FRV_BUILTIN_SMASS
:
9327 case FRV_BUILTIN_SMSSS
:
9328 case FRV_BUILTIN_SMU
:
9329 case FRV_BUILTIN_ADDSS
:
9330 case FRV_BUILTIN_SUBSS
:
9331 case FRV_BUILTIN_SLASS
:
9332 case FRV_BUILTIN_SCUTSS
:
9333 case FRV_BUILTIN_IACCreadll
:
9334 case FRV_BUILTIN_IACCreadl
:
9335 case FRV_BUILTIN_IACCsetll
:
9336 case FRV_BUILTIN_IACCsetl
:
9337 if (!TARGET_FR405_BUILTINS
)
9339 error ("this builtin function is only available"
9340 " on the fr405 and fr450");
9345 case FRV_BUILTIN_PREFETCH
:
9346 if (!TARGET_FR500_FR550_BUILTINS
)
9348 error ("this builtin function is only available on the fr500"
9354 case FRV_BUILTIN_MQLCLRHS
:
9355 case FRV_BUILTIN_MQLMTHS
:
9356 case FRV_BUILTIN_MQSLLHI
:
9357 case FRV_BUILTIN_MQSRAHI
:
9358 if (!TARGET_MEDIA_FR450
)
9360 error ("this builtin function is only available on the fr450");
9369 /* Expand unique builtins. */
9373 case FRV_BUILTIN_MTRAP
:
9374 return frv_expand_noargs_builtin (CODE_FOR_mtrap
);
9376 case FRV_BUILTIN_MCLRACC
:
9377 return frv_expand_mclracc_builtin (exp
);
9379 case FRV_BUILTIN_MCLRACCA
:
9381 return frv_expand_noargs_builtin (CODE_FOR_mclracca8
);
9383 return frv_expand_noargs_builtin (CODE_FOR_mclracca4
);
9385 case FRV_BUILTIN_MRDACC
:
9386 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc
, exp
);
9388 case FRV_BUILTIN_MRDACCG
:
9389 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg
, exp
);
9391 case FRV_BUILTIN_MWTACC
:
9392 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc
, exp
);
9394 case FRV_BUILTIN_MWTACCG
:
9395 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg
, exp
);
9397 case FRV_BUILTIN_MDPACKH
:
9398 return frv_expand_mdpackh_builtin (exp
, target
);
9400 case FRV_BUILTIN_IACCreadll
:
9402 rtx src
= frv_read_iacc_argument (DImode
, exp
, 0);
9403 if (target
== 0 || !REG_P (target
))
9404 target
= gen_reg_rtx (DImode
);
9405 frv_split_iacc_move (target
, src
);
9409 case FRV_BUILTIN_IACCreadl
:
9410 return frv_read_iacc_argument (SImode
, exp
, 0);
9412 case FRV_BUILTIN_IACCsetll
:
9414 rtx dest
= frv_read_iacc_argument (DImode
, exp
, 0);
9415 rtx src
= frv_read_argument (exp
, 1);
9416 frv_split_iacc_move (dest
, force_reg (DImode
, src
));
9420 case FRV_BUILTIN_IACCsetl
:
9422 rtx dest
= frv_read_iacc_argument (SImode
, exp
, 0);
9423 rtx src
= frv_read_argument (exp
, 1);
9424 emit_move_insn (dest
, force_reg (SImode
, src
));
9432 /* Expand groups of builtins. */
9434 for (i
= 0, d
= bdesc_set
; i
< ARRAY_SIZE (bdesc_set
); i
++, d
++)
9435 if (d
->code
== fcode
)
9436 return frv_expand_set_builtin (d
->icode
, exp
, target
);
9438 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
9439 if (d
->code
== fcode
)
9440 return frv_expand_unop_builtin (d
->icode
, exp
, target
);
9442 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
9443 if (d
->code
== fcode
)
9444 return frv_expand_binop_builtin (d
->icode
, exp
, target
);
9446 for (i
= 0, d
= bdesc_cut
; i
< ARRAY_SIZE (bdesc_cut
); i
++, d
++)
9447 if (d
->code
== fcode
)
9448 return frv_expand_cut_builtin (d
->icode
, exp
, target
);
9450 for (i
= 0, d
= bdesc_2argimm
; i
< ARRAY_SIZE (bdesc_2argimm
); i
++, d
++)
9451 if (d
->code
== fcode
)
9452 return frv_expand_binopimm_builtin (d
->icode
, exp
, target
);
9454 for (i
= 0, d
= bdesc_void2arg
; i
< ARRAY_SIZE (bdesc_void2arg
); i
++, d
++)
9455 if (d
->code
== fcode
)
9456 return frv_expand_voidbinop_builtin (d
->icode
, exp
);
9458 for (i
= 0, d
= bdesc_void3arg
; i
< ARRAY_SIZE (bdesc_void3arg
); i
++, d
++)
9459 if (d
->code
== fcode
)
9460 return frv_expand_voidtriop_builtin (d
->icode
, exp
);
9462 for (i
= 0, d
= bdesc_voidacc
; i
< ARRAY_SIZE (bdesc_voidacc
); i
++, d
++)
9463 if (d
->code
== fcode
)
9464 return frv_expand_voidaccop_builtin (d
->icode
, exp
);
9466 for (i
= 0, d
= bdesc_int_void2arg
;
9467 i
< ARRAY_SIZE (bdesc_int_void2arg
); i
++, d
++)
9468 if (d
->code
== fcode
)
9469 return frv_expand_int_void2arg (d
->icode
, exp
);
9471 for (i
= 0, d
= bdesc_prefetches
;
9472 i
< ARRAY_SIZE (bdesc_prefetches
); i
++, d
++)
9473 if (d
->code
== fcode
)
9474 return frv_expand_prefetches (d
->icode
, exp
);
9476 for (i
= 0, d
= bdesc_loads
; i
< ARRAY_SIZE (bdesc_loads
); i
++, d
++)
9477 if (d
->code
== fcode
)
9478 return frv_expand_load_builtin (d
->icode
, TYPE_MODE (TREE_TYPE (exp
)),
9481 for (i
= 0, d
= bdesc_stores
; i
< ARRAY_SIZE (bdesc_stores
); i
++, d
++)
9482 if (d
->code
== fcode
)
9483 return frv_expand_store_builtin (d
->icode
, exp
);
9489 frv_in_small_data_p (const_tree decl
)
9492 const_tree section_name
;
9494 /* Don't apply the -G flag to internal compiler structures. We
9495 should leave such structures in the main data section, partly
9496 for efficiency and partly because the size of some of them
9497 (such as C++ typeinfos) is not known until later. */
9498 if (TREE_CODE (decl
) != VAR_DECL
|| DECL_ARTIFICIAL (decl
))
9501 /* If we already know which section the decl should be in, see if
9502 it's a small data section. */
9503 section_name
= DECL_SECTION_NAME (decl
);
9506 gcc_assert (TREE_CODE (section_name
) == STRING_CST
);
9507 if (frv_string_begins_with (section_name
, ".sdata"))
9509 if (frv_string_begins_with (section_name
, ".sbss"))
9514 size
= int_size_in_bytes (TREE_TYPE (decl
));
9515 if (size
> 0 && size
<= g_switch_value
)
9522 frv_rtx_costs (rtx x
,
9523 int code ATTRIBUTE_UNUSED
,
9524 int outer_code ATTRIBUTE_UNUSED
,
9525 int opno ATTRIBUTE_UNUSED
,
9527 bool speed ATTRIBUTE_UNUSED
)
9529 if (outer_code
== MEM
)
9531 /* Don't differentiate between memory addresses. All the ones
9532 we accept have equal cost. */
9533 *total
= COSTS_N_INSNS (0);
9540 /* Make 12-bit integers really cheap. */
9541 if (IN_RANGE (INTVAL (x
), -2048, 2047))
9552 *total
= COSTS_N_INSNS (2);
9566 if (GET_MODE (x
) == SImode
)
9567 *total
= COSTS_N_INSNS (1);
9568 else if (GET_MODE (x
) == DImode
)
9569 *total
= COSTS_N_INSNS (2);
9571 *total
= COSTS_N_INSNS (3);
9575 if (GET_MODE (x
) == SImode
)
9576 *total
= COSTS_N_INSNS (2);
9578 *total
= COSTS_N_INSNS (6); /* guess */
9585 *total
= COSTS_N_INSNS (18);
9589 *total
= COSTS_N_INSNS (3);
9598 frv_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9600 switch_to_section (ctors_section
);
9601 assemble_align (POINTER_SIZE
);
9604 int ok
= frv_assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, 1);
9609 assemble_integer_with_op ("\t.picptr\t", symbol
);
9613 frv_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9615 switch_to_section (dtors_section
);
9616 assemble_align (POINTER_SIZE
);
9619 int ok
= frv_assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, 1);
9624 assemble_integer_with_op ("\t.picptr\t", symbol
);
9627 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9630 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
9631 int incoming ATTRIBUTE_UNUSED
)
9633 return gen_rtx_REG (Pmode
, FRV_STRUCT_VALUE_REGNUM
);
9636 #define TLS_BIAS (2048 - 16)
9638 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9639 We need to emit DTP-relative relocations. */
9642 frv_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
9644 gcc_assert (size
== 4);
9645 fputs ("\t.picptr\ttlsmoff(", file
);
9646 /* We want the unbiased TLS offset, so add the bias to the
9647 expression, such that the implicit biasing cancels out. */
9648 output_addr_const (file
, plus_constant (Pmode
, x
, TLS_BIAS
));