1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
2 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
42 #include "diagnostic-core.h"
43 #include "basic-block.h"
47 #include "target-def.h"
48 #include "targhooks.h"
49 #include "langhooks.h"
54 #define FRV_INLINE inline
57 /* The maximum number of distinct NOP patterns. There are three:
58 nop, fnop and mnop. */
59 #define NUM_NOP_PATTERNS 3
61 /* Classification of instructions and units: integer, floating-point/media,
62 branch and control. */
63 enum frv_insn_group
{ GROUP_I
, GROUP_FM
, GROUP_B
, GROUP_C
, NUM_GROUPS
};
65 /* The DFA names of the units, in packet order. */
66 static const char *const frv_unit_names
[] =
76 /* The classification of each unit in frv_unit_names[]. */
77 static const enum frv_insn_group frv_unit_groups
[ARRAY_SIZE (frv_unit_names
)] =
87 /* Return the DFA unit code associated with the Nth unit of integer
88 or floating-point group GROUP, */
89 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
91 /* Return the number of integer or floating-point unit UNIT
92 (1 for I1, 2 for F2, etc.). */
93 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
95 /* The DFA unit number for each unit in frv_unit_names[]. */
96 static int frv_unit_codes
[ARRAY_SIZE (frv_unit_names
)];
98 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
99 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
100 no instruction of type T has been seen. */
101 static unsigned int frv_type_to_unit
[TYPE_UNKNOWN
+ 1];
103 /* An array of dummy nop INSNs, one for each type of nop that the
105 static GTY(()) rtx frv_nops
[NUM_NOP_PATTERNS
];
107 /* The number of nop instructions in frv_nops[]. */
108 static unsigned int frv_num_nops
;
110 /* The type of access. FRV_IO_UNKNOWN means the access can be either
111 a read or a write. */
112 enum frv_io_type
{ FRV_IO_UNKNOWN
, FRV_IO_READ
, FRV_IO_WRITE
};
114 /* Information about one __builtin_read or __builtin_write access, or
115 the combination of several such accesses. The most general value
116 is all-zeros (an unknown access to an unknown address). */
118 enum frv_io_type type
;
120 /* The constant address being accessed, or zero if not known. */
121 HOST_WIDE_INT const_address
;
123 /* The run-time address, as used in operand 0 of the membar pattern. */
127 /* Return true if instruction INSN should be packed with the following
129 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
131 /* Set the value of PACKING_FLAG_P(INSN). */
132 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
133 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
135 /* Loop with REG set to each hard register in rtx X. */
136 #define FOR_EACH_REGNO(REG, X) \
137 for (REG = REGNO (X); \
138 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
141 /* This structure contains machine specific function data. */
142 struct GTY(()) machine_function
144 /* True if we have created an rtx that relies on the stack frame. */
147 /* True if this function contains at least one __builtin_{read,write}*. */
151 /* Temporary register allocation support structure. */
152 typedef struct frv_tmp_reg_struct
154 HARD_REG_SET regs
; /* possible registers to allocate */
155 int next_reg
[N_REG_CLASSES
]; /* next register to allocate per class */
159 /* Register state information for VLIW re-packing phase. */
160 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
161 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
162 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
163 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
165 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
167 typedef unsigned char regstate_t
;
169 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
177 /* Information required by frv_frame_access. */
180 /* This field is FRV_LOAD if registers are to be loaded from the stack and
181 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
182 the move is being done by the prologue code while FRV_LOAD implies it
183 is being done by the epilogue. */
184 enum frv_stack_op op
;
186 /* The base register to use when accessing the stack. This may be the
187 frame pointer, stack pointer, or a temporary. The choice of register
188 depends on which part of the frame is being accessed and how big the
192 /* The offset of BASE from the bottom of the current frame, in bytes. */
194 } frv_frame_accessor_t
;
196 /* Conditional execution support gathered together in one structure. */
199 /* Linked list of insns to add if the conditional execution conversion was
200 successful. Each link points to an EXPR_LIST which points to the pattern
201 of the insn to add, and the insn to be inserted before. */
202 rtx added_insns_list
;
204 /* Identify which registers are safe to allocate for if conversions to
205 conditional execution. We keep the last allocated register in the
206 register classes between COND_EXEC statements. This will mean we allocate
207 different registers for each different COND_EXEC group if we can. This
208 might allow the scheduler to intermix two different COND_EXEC sections. */
209 frv_tmp_reg_t tmp_reg
;
211 /* For nested IFs, identify which CC registers are used outside of setting
212 via a compare isnsn, and using via a check insn. This will allow us to
213 know if we can rewrite the register to use a different register that will
214 be paired with the CR register controlling the nested IF-THEN blocks. */
215 HARD_REG_SET nested_cc_ok_rewrite
;
217 /* Temporary registers allocated to hold constants during conditional
219 rtx scratch_regs
[FIRST_PSEUDO_REGISTER
];
221 /* Current number of temp registers available. */
222 int cur_scratch_regs
;
224 /* Number of nested conditional execution blocks. */
225 int num_nested_cond_exec
;
227 /* Map of insns that set up constants in scratch registers. */
228 bitmap scratch_insns_bitmap
;
230 /* Conditional execution test register (CC0..CC7). */
233 /* Conditional execution compare register that is paired with cr_reg, so that
234 nested compares can be done. The csubcc and caddcc instructions don't
235 have enough bits to specify both a CC register to be set and a CR register
236 to do the test on, so the same bit number is used for both. Needless to
237 say, this is rather inconvenient for GCC. */
240 /* Extra CR registers used for &&, ||. */
244 /* Previous CR used in nested if, to make sure we are dealing with the same
245 nested if as the previous statement. */
246 rtx last_nested_if_cr
;
250 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt
;
252 /* Map register number to smallest register class. */
253 enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
];
255 /* Cached value of frv_stack_info. */
256 static frv_stack_t
*frv_stack_cache
= (frv_stack_t
*)0;
258 /* Forward references */
260 static void frv_option_override (void);
261 static bool frv_legitimate_address_p (enum machine_mode
, rtx
, bool);
262 static int frv_default_flags_for_cpu (void);
263 static int frv_string_begins_with (const_tree
, const char *);
264 static FRV_INLINE
bool frv_small_data_reloc_p (rtx
, int);
265 static void frv_print_operand (FILE *, rtx
, int);
266 static void frv_print_operand_address (FILE *, rtx
);
267 static bool frv_print_operand_punct_valid_p (unsigned char code
);
268 static void frv_print_operand_memory_reference_reg
270 static void frv_print_operand_memory_reference (FILE *, rtx
, int);
271 static int frv_print_operand_jump_hint (rtx
);
272 static const char *comparison_string (enum rtx_code
, rtx
);
273 static rtx
frv_function_value (const_tree
, const_tree
,
275 static rtx
frv_libcall_value (enum machine_mode
,
277 static FRV_INLINE
int frv_regno_ok_for_base_p (int, int);
278 static rtx
single_set_pattern (rtx
);
279 static int frv_function_contains_far_jump (void);
280 static rtx
frv_alloc_temp_reg (frv_tmp_reg_t
*,
284 static rtx
frv_frame_offset_rtx (int);
285 static rtx
frv_frame_mem (enum machine_mode
, rtx
, int);
286 static rtx
frv_dwarf_store (rtx
, int);
287 static void frv_frame_insn (rtx
, rtx
);
288 static void frv_frame_access (frv_frame_accessor_t
*,
290 static void frv_frame_access_multi (frv_frame_accessor_t
*,
292 static void frv_frame_access_standard_regs (enum frv_stack_op
,
294 static struct machine_function
*frv_init_machine_status (void);
295 static rtx
frv_int_to_acc (enum insn_code
, int, rtx
);
296 static enum machine_mode
frv_matching_accg_mode (enum machine_mode
);
297 static rtx
frv_read_argument (tree
, unsigned int);
298 static rtx
frv_read_iacc_argument (enum machine_mode
, tree
, unsigned int);
299 static int frv_check_constant_argument (enum insn_code
, int, rtx
);
300 static rtx
frv_legitimize_target (enum insn_code
, rtx
);
301 static rtx
frv_legitimize_argument (enum insn_code
, int, rtx
);
302 static rtx
frv_legitimize_tls_address (rtx
, enum tls_model
);
303 static rtx
frv_legitimize_address (rtx
, rtx
, enum machine_mode
);
304 static rtx
frv_expand_set_builtin (enum insn_code
, tree
, rtx
);
305 static rtx
frv_expand_unop_builtin (enum insn_code
, tree
, rtx
);
306 static rtx
frv_expand_binop_builtin (enum insn_code
, tree
, rtx
);
307 static rtx
frv_expand_cut_builtin (enum insn_code
, tree
, rtx
);
308 static rtx
frv_expand_binopimm_builtin (enum insn_code
, tree
, rtx
);
309 static rtx
frv_expand_voidbinop_builtin (enum insn_code
, tree
);
310 static rtx
frv_expand_int_void2arg (enum insn_code
, tree
);
311 static rtx
frv_expand_prefetches (enum insn_code
, tree
);
312 static rtx
frv_expand_voidtriop_builtin (enum insn_code
, tree
);
313 static rtx
frv_expand_voidaccop_builtin (enum insn_code
, tree
);
314 static rtx
frv_expand_mclracc_builtin (tree
);
315 static rtx
frv_expand_mrdacc_builtin (enum insn_code
, tree
);
316 static rtx
frv_expand_mwtacc_builtin (enum insn_code
, tree
);
317 static rtx
frv_expand_noargs_builtin (enum insn_code
);
318 static void frv_split_iacc_move (rtx
, rtx
);
319 static rtx
frv_emit_comparison (enum rtx_code
, rtx
, rtx
);
320 static int frv_clear_registers_used (rtx
*, void *);
321 static void frv_ifcvt_add_insn (rtx
, rtx
, int);
322 static rtx
frv_ifcvt_rewrite_mem (rtx
, enum machine_mode
, rtx
);
323 static rtx
frv_ifcvt_load_value (rtx
, rtx
);
324 static int frv_acc_group_1 (rtx
*, void *);
325 static unsigned int frv_insn_unit (rtx
);
326 static bool frv_issues_to_branch_unit_p (rtx
);
327 static int frv_cond_flags (rtx
);
328 static bool frv_regstate_conflict_p (regstate_t
, regstate_t
);
329 static int frv_registers_conflict_p_1 (rtx
*, void *);
330 static bool frv_registers_conflict_p (rtx
);
331 static void frv_registers_update_1 (rtx
, const_rtx
, void *);
332 static void frv_registers_update (rtx
);
333 static void frv_start_packet (void);
334 static void frv_start_packet_block (void);
335 static void frv_finish_packet (void (*) (void));
336 static bool frv_pack_insn_p (rtx
);
337 static void frv_add_insn_to_packet (rtx
);
338 static void frv_insert_nop_in_packet (rtx
);
339 static bool frv_for_each_packet (void (*) (void));
340 static bool frv_sort_insn_group_1 (enum frv_insn_group
,
341 unsigned int, unsigned int,
342 unsigned int, unsigned int,
344 static int frv_compare_insns (const void *, const void *);
345 static void frv_sort_insn_group (enum frv_insn_group
);
346 static void frv_reorder_packet (void);
347 static void frv_fill_unused_units (enum frv_insn_group
);
348 static void frv_align_label (void);
349 static void frv_reorg_packet (void);
350 static void frv_register_nop (rtx
);
351 static void frv_reorg (void);
352 static void frv_pack_insns (void);
353 static void frv_function_prologue (FILE *, HOST_WIDE_INT
);
354 static void frv_function_epilogue (FILE *, HOST_WIDE_INT
);
355 static bool frv_assemble_integer (rtx
, unsigned, int);
356 static void frv_init_builtins (void);
357 static rtx
frv_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
358 static void frv_init_libfuncs (void);
359 static bool frv_in_small_data_p (const_tree
);
360 static void frv_asm_output_mi_thunk
361 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
362 static void frv_setup_incoming_varargs (cumulative_args_t
,
365 static rtx
frv_expand_builtin_saveregs (void);
366 static void frv_expand_builtin_va_start (tree
, rtx
);
367 static bool frv_rtx_costs (rtx
, int, int, int, int*,
369 static int frv_register_move_cost (enum machine_mode
,
370 reg_class_t
, reg_class_t
);
371 static int frv_memory_move_cost (enum machine_mode
,
373 static void frv_asm_out_constructor (rtx
, int);
374 static void frv_asm_out_destructor (rtx
, int);
375 static bool frv_function_symbol_referenced_p (rtx
);
376 static bool frv_legitimate_constant_p (enum machine_mode
, rtx
);
377 static bool frv_cannot_force_const_mem (enum machine_mode
, rtx
);
378 static const char *unspec_got_name (int);
379 static void frv_output_const_unspec (FILE *,
380 const struct frv_unspec
*);
381 static bool frv_function_ok_for_sibcall (tree
, tree
);
382 static rtx
frv_struct_value_rtx (tree
, int);
383 static bool frv_must_pass_in_stack (enum machine_mode mode
, const_tree type
);
384 static int frv_arg_partial_bytes (cumulative_args_t
, enum machine_mode
,
386 static rtx
frv_function_arg (cumulative_args_t
, enum machine_mode
,
388 static rtx
frv_function_incoming_arg (cumulative_args_t
, enum machine_mode
,
390 static void frv_function_arg_advance (cumulative_args_t
, enum machine_mode
,
392 static unsigned int frv_function_arg_boundary (enum machine_mode
,
394 static void frv_output_dwarf_dtprel (FILE *, int, rtx
)
396 static reg_class_t
frv_secondary_reload (bool, rtx
, reg_class_t
,
398 secondary_reload_info
*);
399 static bool frv_frame_pointer_required (void);
400 static bool frv_can_eliminate (const int, const int);
401 static void frv_conditional_register_usage (void);
402 static void frv_trampoline_init (rtx
, tree
, rtx
);
403 static bool frv_class_likely_spilled_p (reg_class_t
);
405 /* Initialize the GCC target structure. */
406 #undef TARGET_PRINT_OPERAND
407 #define TARGET_PRINT_OPERAND frv_print_operand
408 #undef TARGET_PRINT_OPERAND_ADDRESS
409 #define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address
410 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
411 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p
412 #undef TARGET_ASM_FUNCTION_PROLOGUE
413 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
414 #undef TARGET_ASM_FUNCTION_EPILOGUE
415 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
416 #undef TARGET_ASM_INTEGER
417 #define TARGET_ASM_INTEGER frv_assemble_integer
418 #undef TARGET_OPTION_OVERRIDE
419 #define TARGET_OPTION_OVERRIDE frv_option_override
420 #undef TARGET_INIT_BUILTINS
421 #define TARGET_INIT_BUILTINS frv_init_builtins
422 #undef TARGET_EXPAND_BUILTIN
423 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
424 #undef TARGET_INIT_LIBFUNCS
425 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
426 #undef TARGET_IN_SMALL_DATA_P
427 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
428 #undef TARGET_REGISTER_MOVE_COST
429 #define TARGET_REGISTER_MOVE_COST frv_register_move_cost
430 #undef TARGET_MEMORY_MOVE_COST
431 #define TARGET_MEMORY_MOVE_COST frv_memory_move_cost
432 #undef TARGET_RTX_COSTS
433 #define TARGET_RTX_COSTS frv_rtx_costs
434 #undef TARGET_ASM_CONSTRUCTOR
435 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
436 #undef TARGET_ASM_DESTRUCTOR
437 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
439 #undef TARGET_ASM_OUTPUT_MI_THUNK
440 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
441 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
442 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
444 #undef TARGET_SCHED_ISSUE_RATE
445 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
447 #undef TARGET_LEGITIMIZE_ADDRESS
448 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
450 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
451 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
452 #undef TARGET_LEGITIMATE_CONSTANT_P
453 #define TARGET_LEGITIMATE_CONSTANT_P frv_legitimate_constant_p
454 #undef TARGET_CANNOT_FORCE_CONST_MEM
455 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
457 #undef TARGET_HAVE_TLS
458 #define TARGET_HAVE_TLS HAVE_AS_TLS
460 #undef TARGET_STRUCT_VALUE_RTX
461 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
462 #undef TARGET_MUST_PASS_IN_STACK
463 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
464 #undef TARGET_PASS_BY_REFERENCE
465 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
466 #undef TARGET_ARG_PARTIAL_BYTES
467 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
468 #undef TARGET_FUNCTION_ARG
469 #define TARGET_FUNCTION_ARG frv_function_arg
470 #undef TARGET_FUNCTION_INCOMING_ARG
471 #define TARGET_FUNCTION_INCOMING_ARG frv_function_incoming_arg
472 #undef TARGET_FUNCTION_ARG_ADVANCE
473 #define TARGET_FUNCTION_ARG_ADVANCE frv_function_arg_advance
474 #undef TARGET_FUNCTION_ARG_BOUNDARY
475 #define TARGET_FUNCTION_ARG_BOUNDARY frv_function_arg_boundary
477 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
478 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
479 #undef TARGET_SETUP_INCOMING_VARARGS
480 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
481 #undef TARGET_MACHINE_DEPENDENT_REORG
482 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
484 #undef TARGET_EXPAND_BUILTIN_VA_START
485 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
488 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
489 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
492 #undef TARGET_CLASS_LIKELY_SPILLED_P
493 #define TARGET_CLASS_LIKELY_SPILLED_P frv_class_likely_spilled_p
495 #undef TARGET_SECONDARY_RELOAD
496 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
498 #undef TARGET_LEGITIMATE_ADDRESS_P
499 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
501 #undef TARGET_FRAME_POINTER_REQUIRED
502 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
504 #undef TARGET_CAN_ELIMINATE
505 #define TARGET_CAN_ELIMINATE frv_can_eliminate
507 #undef TARGET_CONDITIONAL_REGISTER_USAGE
508 #define TARGET_CONDITIONAL_REGISTER_USAGE frv_conditional_register_usage
510 #undef TARGET_TRAMPOLINE_INIT
511 #define TARGET_TRAMPOLINE_INIT frv_trampoline_init
513 #undef TARGET_FUNCTION_VALUE
514 #define TARGET_FUNCTION_VALUE frv_function_value
515 #undef TARGET_LIBCALL_VALUE
516 #define TARGET_LIBCALL_VALUE frv_libcall_value
518 struct gcc_target targetm
= TARGET_INITIALIZER
;
520 #define FRV_SYMBOL_REF_TLS_P(RTX) \
521 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
524 /* Any function call that satisfies the machine-independent
525 requirements is eligible on FR-V. */
528 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
529 tree exp ATTRIBUTE_UNUSED
)
534 /* Return true if SYMBOL is a small data symbol and relocation RELOC
535 can be used to access it directly in a load or store. */
537 static FRV_INLINE
bool
538 frv_small_data_reloc_p (rtx symbol
, int reloc
)
540 return (GET_CODE (symbol
) == SYMBOL_REF
541 && SYMBOL_REF_SMALL_P (symbol
)
542 && (!TARGET_FDPIC
|| flag_pic
== 1)
543 && (reloc
== R_FRV_GOTOFF12
|| reloc
== R_FRV_GPREL12
));
546 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
550 frv_const_unspec_p (rtx x
, struct frv_unspec
*unspec
)
552 if (GET_CODE (x
) == CONST
)
556 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
558 unspec
->offset
+= INTVAL (XEXP (x
, 1));
561 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_GOT
)
563 unspec
->symbol
= XVECEXP (x
, 0, 0);
564 unspec
->reloc
= INTVAL (XVECEXP (x
, 0, 1));
566 if (unspec
->offset
== 0)
569 if (frv_small_data_reloc_p (unspec
->symbol
, unspec
->reloc
)
570 && unspec
->offset
> 0
571 && unspec
->offset
< g_switch_value
)
578 /* Decide whether we can force certain constants to memory. If we
579 decide we can't, the caller should be able to cope with it in
582 We never allow constants to be forced into memory for TARGET_FDPIC.
583 This is necessary for several reasons:
585 1. Since frv_legitimate_constant_p rejects constant pool addresses, the
586 target-independent code will try to force them into the constant
587 pool, thus leading to infinite recursion.
589 2. We can never introduce new constant pool references during reload.
590 Any such reference would require use of the pseudo FDPIC register.
592 3. We can't represent a constant added to a function pointer (which is
593 not the same as a pointer to a function+constant).
595 4. In many cases, it's more efficient to calculate the constant in-line. */
598 frv_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
,
599 rtx x ATTRIBUTE_UNUSED
)
605 frv_default_flags_for_cpu (void)
607 switch (frv_cpu_type
)
609 case FRV_CPU_GENERIC
:
610 return MASK_DEFAULT_FRV
;
613 return MASK_DEFAULT_FR550
;
617 return MASK_DEFAULT_FR500
;
620 return MASK_DEFAULT_FR450
;
624 return MASK_DEFAULT_FR400
;
628 return MASK_DEFAULT_SIMPLE
;
635 /* Implement TARGET_OPTION_OVERRIDE. */
638 frv_option_override (void)
643 target_flags
|= (frv_default_flags_for_cpu () & ~target_flags_explicit
);
645 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
646 linker about linking pic and non-pic code. */
649 if (!flag_pic
) /* -fPIC */
652 if (!global_options_set
.x_g_switch_value
) /* -G0 */
658 /* A C expression whose value is a register class containing hard
659 register REGNO. In general there is more than one such class;
660 choose a class which is "minimal", meaning that no smaller class
661 also contains the register. */
663 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
665 enum reg_class rclass
;
669 int gpr_reg
= regno
- GPR_FIRST
;
671 if (gpr_reg
== GR8_REG
)
674 else if (gpr_reg
== GR9_REG
)
677 else if (gpr_reg
== GR14_REG
)
678 rclass
= FDPIC_FPTR_REGS
;
680 else if (gpr_reg
== FDPIC_REGNO
)
683 else if ((gpr_reg
& 3) == 0)
686 else if ((gpr_reg
& 1) == 0)
693 else if (FPR_P (regno
))
695 int fpr_reg
= regno
- GPR_FIRST
;
696 if ((fpr_reg
& 3) == 0)
697 rclass
= QUAD_FPR_REGS
;
699 else if ((fpr_reg
& 1) == 0)
706 else if (regno
== LR_REGNO
)
709 else if (regno
== LCR_REGNO
)
712 else if (ICC_P (regno
))
715 else if (FCC_P (regno
))
718 else if (ICR_P (regno
))
721 else if (FCR_P (regno
))
724 else if (ACC_P (regno
))
726 int r
= regno
- ACC_FIRST
;
728 rclass
= QUAD_ACC_REGS
;
729 else if ((r
& 1) == 0)
730 rclass
= EVEN_ACC_REGS
;
735 else if (ACCG_P (regno
))
741 regno_reg_class
[regno
] = rclass
;
744 /* Check for small data option */
745 if (!global_options_set
.x_g_switch_value
&& !TARGET_LIBPIC
)
746 g_switch_value
= SDATA_DEFAULT_SIZE
;
748 /* There is no single unaligned SI op for PIC code. Sometimes we
749 need to use ".4byte" and sometimes we need to use ".picptr".
750 See frv_assemble_integer for details. */
751 if (flag_pic
|| TARGET_FDPIC
)
752 targetm
.asm_out
.unaligned_op
.si
= 0;
754 if ((target_flags_explicit
& MASK_LINKED_FP
) == 0)
755 target_flags
|= MASK_LINKED_FP
;
757 if ((target_flags_explicit
& MASK_OPTIMIZE_MEMBAR
) == 0)
758 target_flags
|= MASK_OPTIMIZE_MEMBAR
;
760 for (i
= 0; i
< ARRAY_SIZE (frv_unit_names
); i
++)
761 frv_unit_codes
[i
] = get_cpu_unit_code (frv_unit_names
[i
]);
763 for (i
= 0; i
< ARRAY_SIZE (frv_type_to_unit
); i
++)
764 frv_type_to_unit
[i
] = ARRAY_SIZE (frv_unit_codes
);
766 init_machine_status
= frv_init_machine_status
;
770 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
773 frv_string_begins_with (const_tree name
, const char *prefix
)
775 const int prefix_len
= strlen (prefix
);
777 /* Remember: NAME's length includes the null terminator. */
778 return (TREE_STRING_LENGTH (name
) > prefix_len
779 && strncmp (TREE_STRING_POINTER (name
), prefix
, prefix_len
) == 0);
782 /* Zero or more C statements that may conditionally modify two variables
783 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
784 been initialized from the two preceding macros.
786 This is necessary in case the fixed or call-clobbered registers depend on
789 You need not define this macro if it has no work to do.
791 If the usage of an entire class of registers depends on the target flags,
792 you may indicate this to GCC by using this macro to modify `fixed_regs' and
793 `call_used_regs' to 1 for each of the registers in the classes which should
794 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
795 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
797 (However, if this class is not included in `GENERAL_REGS' and all of the
798 insn patterns whose constraints permit this class are controlled by target
799 switches, then GCC will automatically avoid using these registers when the
800 target switches are opposed to them.) */
803 frv_conditional_register_usage (void)
807 for (i
= GPR_FIRST
+ NUM_GPRS
; i
<= GPR_LAST
; i
++)
808 fixed_regs
[i
] = call_used_regs
[i
] = 1;
810 for (i
= FPR_FIRST
+ NUM_FPRS
; i
<= FPR_LAST
; i
++)
811 fixed_regs
[i
] = call_used_regs
[i
] = 1;
813 /* Reserve the registers used for conditional execution. At present, we need
814 1 ICC and 1 ICR register. */
815 fixed_regs
[ICC_TEMP
] = call_used_regs
[ICC_TEMP
] = 1;
816 fixed_regs
[ICR_TEMP
] = call_used_regs
[ICR_TEMP
] = 1;
820 fixed_regs
[ICC_FIRST
] = call_used_regs
[ICC_FIRST
] = 1;
821 fixed_regs
[FCC_FIRST
] = call_used_regs
[FCC_FIRST
] = 1;
822 fixed_regs
[ICR_FIRST
] = call_used_regs
[ICR_FIRST
] = 1;
823 fixed_regs
[FCR_FIRST
] = call_used_regs
[FCR_FIRST
] = 1;
827 fixed_regs
[GPR_FIRST
+ 16] = fixed_regs
[GPR_FIRST
+ 17] =
828 call_used_regs
[GPR_FIRST
+ 16] = call_used_regs
[GPR_FIRST
+ 17] = 0;
831 /* If -fpic, SDA_BASE_REG is the PIC register. */
832 if (g_switch_value
== 0 && !flag_pic
)
833 fixed_regs
[SDA_BASE_REG
] = call_used_regs
[SDA_BASE_REG
] = 0;
836 fixed_regs
[PIC_REGNO
] = call_used_regs
[PIC_REGNO
] = 0;
842 * Compute the stack frame layout
845 * +---------------+-----------------------+-----------------------+
846 * |Register |type |caller-save/callee-save|
847 * +---------------+-----------------------+-----------------------+
848 * |GR0 |Zero register | - |
849 * |GR1 |Stack pointer(SP) | - |
850 * |GR2 |Frame pointer(FP) | - |
851 * |GR3 |Hidden parameter | caller save |
852 * |GR4-GR7 | - | caller save |
853 * |GR8-GR13 |Argument register | caller save |
854 * |GR14-GR15 | - | caller save |
855 * |GR16-GR31 | - | callee save |
856 * |GR32-GR47 | - | caller save |
857 * |GR48-GR63 | - | callee save |
858 * |FR0-FR15 | - | caller save |
859 * |FR16-FR31 | - | callee save |
860 * |FR32-FR47 | - | caller save |
861 * |FR48-FR63 | - | callee save |
862 * +---------------+-----------------------+-----------------------+
866 * SP-> |-----------------------------------|
868 * |-----------------------------------|
869 * | Register save area |
870 * |-----------------------------------|
871 * | Local variable save area |
872 * FP-> |-----------------------------------|
874 * |-----------------------------------|
875 * | Hidden parameter save area |
876 * |-----------------------------------|
877 * | Return address(LR) storage area |
878 * |-----------------------------------|
879 * | Padding for alignment |
880 * |-----------------------------------|
881 * | Register argument area |
882 * OLD SP-> |-----------------------------------|
884 * |-----------------------------------|
887 * Argument area/Parameter area:
889 * When a function is called, this area is used for argument transfer. When
890 * the argument is set up by the caller function, this area is referred to as
891 * the argument area. When the argument is referenced by the callee function,
892 * this area is referred to as the parameter area. The area is allocated when
893 * all arguments cannot be placed on the argument register at the time of
896 * Register save area:
898 * This is a register save area that must be guaranteed for the caller
899 * function. This area is not secured when the register save operation is not
902 * Local variable save area:
904 * This is the area for local variables and temporary variables.
908 * This area stores the FP value of the caller function.
910 * Hidden parameter save area:
912 * This area stores the start address of the return value storage
913 * area for a struct/union return function.
914 * When a struct/union is used as the return value, the caller
915 * function stores the return value storage area start address in
916 * register GR3 and passes it to the caller function.
917 * The callee function interprets the address stored in the GR3
918 * as the return value storage area start address.
919 * When register GR3 needs to be saved into memory, the callee
920 * function saves it in the hidden parameter save area. This
921 * area is not secured when the save operation is not needed.
923 * Return address(LR) storage area:
925 * This area saves the LR. The LR stores the address of a return to the caller
926 * function for the purpose of function calling.
928 * Argument register area:
930 * This area saves the argument register. This area is not secured when the
931 * save operation is not needed.
935 * Arguments, the count of which equals the count of argument registers (6
936 * words), are positioned in registers GR8 to GR13 and delivered to the callee
937 * function. When a struct/union return function is called, the return value
938 * area address is stored in register GR3. Arguments not placed in the
939 * argument registers will be stored in the stack argument area for transfer
940 * purposes. When an 8-byte type argument is to be delivered using registers,
941 * it is divided into two and placed in two registers for transfer. When
942 * argument registers must be saved to memory, the callee function secures an
943 * argument register save area in the stack. In this case, a continuous
944 * argument register save area must be established in the parameter area. The
945 * argument register save area must be allocated as needed to cover the size of
946 * the argument register to be saved. If the function has a variable count of
947 * arguments, it saves all argument registers in the argument register save
950 * Argument Extension Format:
952 * When an argument is to be stored in the stack, its type is converted to an
953 * extended type in accordance with the individual argument type. The argument
954 * is freed by the caller function after the return from the callee function is
957 * +-----------------------+---------------+------------------------+
958 * | Argument Type |Extended Type |Stack Storage Size(byte)|
959 * +-----------------------+---------------+------------------------+
961 * |signed char |int | 4 |
962 * |unsigned char |int | 4 |
963 * |[signed] short int |int | 4 |
964 * |unsigned short int |int | 4 |
965 * |[signed] int |No extension | 4 |
966 * |unsigned int |No extension | 4 |
967 * |[signed] long int |No extension | 4 |
968 * |unsigned long int |No extension | 4 |
969 * |[signed] long long int |No extension | 8 |
970 * |unsigned long long int |No extension | 8 |
971 * |float |double | 8 |
972 * |double |No extension | 8 |
973 * |long double |No extension | 8 |
974 * |pointer |No extension | 4 |
975 * |struct/union |- | 4 (*1) |
976 * +-----------------------+---------------+------------------------+
978 * When a struct/union is to be delivered as an argument, the caller copies it
979 * to the local variable area and delivers the address of that area.
983 * +-------------------------------+----------------------+
984 * |Return Value Type |Return Value Interface|
985 * +-------------------------------+----------------------+
987 * |[signed|unsigned] char |GR8 |
988 * |[signed|unsigned] short int |GR8 |
989 * |[signed|unsigned] int |GR8 |
990 * |[signed|unsigned] long int |GR8 |
992 * |[signed|unsigned] long long int|GR8 & GR9 |
994 * |double |GR8 & GR9 |
995 * |long double |GR8 & GR9 |
996 * |struct/union |(*1) |
997 * +-------------------------------+----------------------+
999 * When a struct/union is used as the return value, the caller function stores
1000 * the start address of the return value storage area into GR3 and then passes
1001 * it to the callee function. The callee function interprets GR3 as the start
1002 * address of the return value storage area. When this address needs to be
1003 * saved in memory, the callee function secures the hidden parameter save area
1004 * and saves the address in that area.
1008 frv_stack_info (void)
1010 static frv_stack_t info
, zero_info
;
1011 frv_stack_t
*info_ptr
= &info
;
1012 tree fndecl
= current_function_decl
;
1020 /* If we've already calculated the values and reload is complete,
1022 if (frv_stack_cache
)
1023 return frv_stack_cache
;
1025 /* Zero all fields. */
1028 /* Set up the register range information. */
1029 info_ptr
->regs
[STACK_REGS_GPR
].name
= "gpr";
1030 info_ptr
->regs
[STACK_REGS_GPR
].first
= LAST_ARG_REGNUM
+ 1;
1031 info_ptr
->regs
[STACK_REGS_GPR
].last
= GPR_LAST
;
1032 info_ptr
->regs
[STACK_REGS_GPR
].dword_p
= TRUE
;
1034 info_ptr
->regs
[STACK_REGS_FPR
].name
= "fpr";
1035 info_ptr
->regs
[STACK_REGS_FPR
].first
= FPR_FIRST
;
1036 info_ptr
->regs
[STACK_REGS_FPR
].last
= FPR_LAST
;
1037 info_ptr
->regs
[STACK_REGS_FPR
].dword_p
= TRUE
;
1039 info_ptr
->regs
[STACK_REGS_LR
].name
= "lr";
1040 info_ptr
->regs
[STACK_REGS_LR
].first
= LR_REGNO
;
1041 info_ptr
->regs
[STACK_REGS_LR
].last
= LR_REGNO
;
1042 info_ptr
->regs
[STACK_REGS_LR
].special_p
= 1;
1044 info_ptr
->regs
[STACK_REGS_CC
].name
= "cc";
1045 info_ptr
->regs
[STACK_REGS_CC
].first
= CC_FIRST
;
1046 info_ptr
->regs
[STACK_REGS_CC
].last
= CC_LAST
;
1047 info_ptr
->regs
[STACK_REGS_CC
].field_p
= TRUE
;
1049 info_ptr
->regs
[STACK_REGS_LCR
].name
= "lcr";
1050 info_ptr
->regs
[STACK_REGS_LCR
].first
= LCR_REGNO
;
1051 info_ptr
->regs
[STACK_REGS_LCR
].last
= LCR_REGNO
;
1053 info_ptr
->regs
[STACK_REGS_STDARG
].name
= "stdarg";
1054 info_ptr
->regs
[STACK_REGS_STDARG
].first
= FIRST_ARG_REGNUM
;
1055 info_ptr
->regs
[STACK_REGS_STDARG
].last
= LAST_ARG_REGNUM
;
1056 info_ptr
->regs
[STACK_REGS_STDARG
].dword_p
= 1;
1057 info_ptr
->regs
[STACK_REGS_STDARG
].special_p
= 1;
1059 info_ptr
->regs
[STACK_REGS_STRUCT
].name
= "struct";
1060 info_ptr
->regs
[STACK_REGS_STRUCT
].first
= FRV_STRUCT_VALUE_REGNUM
;
1061 info_ptr
->regs
[STACK_REGS_STRUCT
].last
= FRV_STRUCT_VALUE_REGNUM
;
1062 info_ptr
->regs
[STACK_REGS_STRUCT
].special_p
= 1;
1064 info_ptr
->regs
[STACK_REGS_FP
].name
= "fp";
1065 info_ptr
->regs
[STACK_REGS_FP
].first
= FRAME_POINTER_REGNUM
;
1066 info_ptr
->regs
[STACK_REGS_FP
].last
= FRAME_POINTER_REGNUM
;
1067 info_ptr
->regs
[STACK_REGS_FP
].special_p
= 1;
1069 /* Determine if this is a stdarg function. If so, allocate space to store
1076 /* Find the last argument, and see if it is __builtin_va_alist. */
1077 for (cur_arg
= DECL_ARGUMENTS (fndecl
); cur_arg
!= (tree
)0; cur_arg
= next_arg
)
1079 next_arg
= DECL_CHAIN (cur_arg
);
1080 if (next_arg
== (tree
)0)
1082 if (DECL_NAME (cur_arg
)
1083 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)), "__builtin_va_alist"))
1091 /* Iterate over all of the register ranges. */
1092 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1094 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1095 int first
= reg_ptr
->first
;
1096 int last
= reg_ptr
->last
;
1098 int size_2words
= 0;
1101 /* Calculate which registers need to be saved & save area size. */
1105 for (regno
= first
; regno
<= last
; regno
++)
1107 if ((df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
1108 || (crtl
->calls_eh_return
1109 && (regno
>= FIRST_EH_REGNUM
&& regno
<= LAST_EH_REGNUM
))
1110 || (!TARGET_FDPIC
&& flag_pic
1111 && crtl
->uses_pic_offset_table
&& regno
== PIC_REGNO
))
1113 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1114 size_1word
+= UNITS_PER_WORD
;
1119 /* Calculate whether we need to create a frame after everything else
1120 has been processed. */
1125 if (df_regs_ever_live_p (LR_REGNO
)
1127 /* This is set for __builtin_return_address, etc. */
1128 || cfun
->machine
->frame_needed
1129 || (TARGET_LINKED_FP
&& frame_pointer_needed
)
1130 || (!TARGET_FDPIC
&& flag_pic
1131 && crtl
->uses_pic_offset_table
))
1133 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1134 size_1word
+= UNITS_PER_WORD
;
1138 case STACK_REGS_STDARG
:
1141 /* If this is a stdarg function with a non varardic
1142 argument split between registers and the stack,
1143 adjust the saved registers downward. */
1144 last
-= (ADDR_ALIGN (crtl
->args
.pretend_args_size
, UNITS_PER_WORD
)
1147 for (regno
= first
; regno
<= last
; regno
++)
1149 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1150 size_1word
+= UNITS_PER_WORD
;
1153 info_ptr
->stdarg_size
= size_1word
;
1157 case STACK_REGS_STRUCT
:
1158 if (cfun
->returns_struct
)
1160 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1161 size_1word
+= UNITS_PER_WORD
;
1169 /* If this is a field, it only takes one word. */
1170 if (reg_ptr
->field_p
)
1171 size_1word
= UNITS_PER_WORD
;
1173 /* Determine which register pairs can be saved together. */
1174 else if (reg_ptr
->dword_p
&& TARGET_DWORD
)
1176 for (regno
= first
; regno
< last
; regno
+= 2)
1178 if (info_ptr
->save_p
[regno
] && info_ptr
->save_p
[regno
+1])
1180 size_2words
+= 2 * UNITS_PER_WORD
;
1181 size_1word
-= 2 * UNITS_PER_WORD
;
1182 info_ptr
->save_p
[regno
] = REG_SAVE_2WORDS
;
1183 info_ptr
->save_p
[regno
+1] = REG_SAVE_NO_SAVE
;
1188 reg_ptr
->size_1word
= size_1word
;
1189 reg_ptr
->size_2words
= size_2words
;
1191 if (! reg_ptr
->special_p
)
1193 info_ptr
->regs_size_1word
+= size_1word
;
1194 info_ptr
->regs_size_2words
+= size_2words
;
1199 /* Set up the sizes of each each field in the frame body, making the sizes
1200 of each be divisible by the size of a dword if dword operations might
1201 be used, or the size of a word otherwise. */
1202 alignment
= (TARGET_DWORD
? 2 * UNITS_PER_WORD
: UNITS_PER_WORD
);
1204 info_ptr
->parameter_size
= ADDR_ALIGN (crtl
->outgoing_args_size
, alignment
);
1205 info_ptr
->regs_size
= ADDR_ALIGN (info_ptr
->regs_size_2words
1206 + info_ptr
->regs_size_1word
,
1208 info_ptr
->vars_size
= ADDR_ALIGN (get_frame_size (), alignment
);
1210 info_ptr
->pretend_size
= crtl
->args
.pretend_args_size
;
1212 /* Work out the size of the frame, excluding the header. Both the frame
1213 body and register parameter area will be dword-aligned. */
1214 info_ptr
->total_size
1215 = (ADDR_ALIGN (info_ptr
->parameter_size
1216 + info_ptr
->regs_size
1217 + info_ptr
->vars_size
,
1219 + ADDR_ALIGN (info_ptr
->pretend_size
1220 + info_ptr
->stdarg_size
,
1221 2 * UNITS_PER_WORD
));
1223 /* See if we need to create a frame at all, if so add header area. */
1224 if (info_ptr
->total_size
> 0
1225 || frame_pointer_needed
1226 || info_ptr
->regs
[STACK_REGS_LR
].size_1word
> 0
1227 || info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
> 0)
1229 offset
= info_ptr
->parameter_size
;
1230 info_ptr
->header_size
= 4 * UNITS_PER_WORD
;
1231 info_ptr
->total_size
+= 4 * UNITS_PER_WORD
;
1233 /* Calculate the offsets to save normal register pairs. */
1234 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1236 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1237 if (! reg_ptr
->special_p
)
1239 int first
= reg_ptr
->first
;
1240 int last
= reg_ptr
->last
;
1243 for (regno
= first
; regno
<= last
; regno
++)
1244 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
1245 && regno
!= FRAME_POINTER_REGNUM
1246 && (regno
< FIRST_ARG_REGNUM
1247 || regno
> LAST_ARG_REGNUM
))
1249 info_ptr
->reg_offset
[regno
] = offset
;
1250 offset
+= 2 * UNITS_PER_WORD
;
1255 /* Calculate the offsets to save normal single registers. */
1256 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1258 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1259 if (! reg_ptr
->special_p
)
1261 int first
= reg_ptr
->first
;
1262 int last
= reg_ptr
->last
;
1265 for (regno
= first
; regno
<= last
; regno
++)
1266 if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
1267 && regno
!= FRAME_POINTER_REGNUM
1268 && (regno
< FIRST_ARG_REGNUM
1269 || regno
> LAST_ARG_REGNUM
))
1271 info_ptr
->reg_offset
[regno
] = offset
;
1272 offset
+= UNITS_PER_WORD
;
1277 /* Calculate the offset to save the local variables at. */
1278 offset
= ADDR_ALIGN (offset
, alignment
);
1279 if (info_ptr
->vars_size
)
1281 info_ptr
->vars_offset
= offset
;
1282 offset
+= info_ptr
->vars_size
;
1285 /* Align header to a dword-boundary. */
1286 offset
= ADDR_ALIGN (offset
, 2 * UNITS_PER_WORD
);
1288 /* Calculate the offsets in the fixed frame. */
1289 info_ptr
->save_p
[FRAME_POINTER_REGNUM
] = REG_SAVE_1WORD
;
1290 info_ptr
->reg_offset
[FRAME_POINTER_REGNUM
] = offset
;
1291 info_ptr
->regs
[STACK_REGS_FP
].size_1word
= UNITS_PER_WORD
;
1293 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1294 info_ptr
->reg_offset
[LR_REGNO
] = offset
+ 2*UNITS_PER_WORD
;
1295 info_ptr
->regs
[STACK_REGS_LR
].size_1word
= UNITS_PER_WORD
;
1297 if (cfun
->returns_struct
)
1299 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1300 info_ptr
->reg_offset
[FRV_STRUCT_VALUE_REGNUM
] = offset
+ UNITS_PER_WORD
;
1301 info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
= UNITS_PER_WORD
;
1304 /* Calculate the offsets to store the arguments passed in registers
1305 for stdarg functions. The register pairs are first and the single
1306 register if any is last. The register save area starts on a
1308 if (info_ptr
->stdarg_size
)
1310 int first
= info_ptr
->regs
[STACK_REGS_STDARG
].first
;
1311 int last
= info_ptr
->regs
[STACK_REGS_STDARG
].last
;
1314 /* Skip the header. */
1315 offset
+= 4 * UNITS_PER_WORD
;
1316 for (regno
= first
; regno
<= last
; regno
++)
1318 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
)
1320 info_ptr
->reg_offset
[regno
] = offset
;
1321 offset
+= 2 * UNITS_PER_WORD
;
1323 else if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
)
1325 info_ptr
->reg_offset
[regno
] = offset
;
1326 offset
+= UNITS_PER_WORD
;
1332 if (reload_completed
)
1333 frv_stack_cache
= info_ptr
;
1339 /* Print the information about the frv stack offsets, etc. when debugging. */
1342 frv_debug_stack (frv_stack_t
*info
)
1347 info
= frv_stack_info ();
1349 fprintf (stderr
, "\nStack information for function %s:\n",
1350 ((current_function_decl
&& DECL_NAME (current_function_decl
))
1351 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
1354 fprintf (stderr
, "\ttotal_size\t= %6d\n", info
->total_size
);
1355 fprintf (stderr
, "\tvars_size\t= %6d\n", info
->vars_size
);
1356 fprintf (stderr
, "\tparam_size\t= %6d\n", info
->parameter_size
);
1357 fprintf (stderr
, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1358 info
->regs_size
, info
->regs_size_1word
, info
->regs_size_2words
);
1360 fprintf (stderr
, "\theader_size\t= %6d\n", info
->header_size
);
1361 fprintf (stderr
, "\tpretend_size\t= %6d\n", info
->pretend_size
);
1362 fprintf (stderr
, "\tvars_offset\t= %6d\n", info
->vars_offset
);
1363 fprintf (stderr
, "\tregs_offset\t= %6d\n", info
->regs_offset
);
1365 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1367 frv_stack_regs_t
*regs
= &(info
->regs
[range
]);
1368 if ((regs
->size_1word
+ regs
->size_2words
) > 0)
1370 int first
= regs
->first
;
1371 int last
= regs
->last
;
1374 fprintf (stderr
, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1375 regs
->name
, regs
->size_1word
+ regs
->size_2words
,
1376 regs
->size_1word
, regs
->size_2words
);
1378 for (regno
= first
; regno
<= last
; regno
++)
1380 if (info
->save_p
[regno
] == REG_SAVE_1WORD
)
1381 fprintf (stderr
, " %s (%d)", reg_names
[regno
],
1382 info
->reg_offset
[regno
]);
1384 else if (info
->save_p
[regno
] == REG_SAVE_2WORDS
)
1385 fprintf (stderr
, " %s-%s (%d)", reg_names
[regno
],
1386 reg_names
[regno
+1], info
->reg_offset
[regno
]);
1389 fputc ('\n', stderr
);
1399 /* Used during final to control the packing of insns. The value is
1400 1 if the current instruction should be packed with the next one,
1401 0 if it shouldn't or -1 if packing is disabled altogether. */
1403 static int frv_insn_packing_flag
;
1405 /* True if the current function contains a far jump. */
1408 frv_function_contains_far_jump (void)
1410 rtx insn
= get_insns ();
1412 && !(GET_CODE (insn
) == JUMP_INSN
1413 /* Ignore tablejump patterns. */
1414 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
1415 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
1416 && get_attr_far_jump (insn
) == FAR_JUMP_YES
))
1417 insn
= NEXT_INSN (insn
);
1418 return (insn
!= NULL
);
1421 /* For the FRV, this function makes sure that a function with far jumps
1422 will return correctly. It also does the VLIW packing. */
1425 frv_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1427 rtx insn
, next
, last_call
;
1429 /* If no frame was created, check whether the function uses a call
1430 instruction to implement a far jump. If so, save the link in gr3 and
1431 replace all returns to LR with returns to GR3. GR3 is used because it
1432 is call-clobbered, because is not available to the register allocator,
1433 and because all functions that take a hidden argument pointer will have
1435 if (frv_stack_info ()->total_size
== 0 && frv_function_contains_far_jump ())
1439 /* Just to check that the above comment is true. */
1440 gcc_assert (!df_regs_ever_live_p (GPR_FIRST
+ 3));
1442 /* Generate the instruction that saves the link register. */
1443 fprintf (file
, "\tmovsg lr,gr3\n");
1445 /* Replace the LR with GR3 in *return_internal patterns. The insn
1446 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1447 simply emit a different assembly directive because bralr and jmpl
1448 execute in different units. */
1449 for (insn
= get_insns(); insn
!= NULL
; insn
= NEXT_INSN (insn
))
1450 if (GET_CODE (insn
) == JUMP_INSN
)
1452 rtx pattern
= PATTERN (insn
);
1453 if (GET_CODE (pattern
) == PARALLEL
1454 && XVECLEN (pattern
, 0) >= 2
1455 && GET_CODE (XVECEXP (pattern
, 0, 0)) == RETURN
1456 && GET_CODE (XVECEXP (pattern
, 0, 1)) == USE
)
1458 rtx address
= XEXP (XVECEXP (pattern
, 0, 1), 0);
1459 if (GET_CODE (address
) == REG
&& REGNO (address
) == LR_REGNO
)
1460 SET_REGNO (address
, GPR_FIRST
+ 3);
1467 /* Allow the garbage collector to free the nops created by frv_reorg. */
1468 memset (frv_nops
, 0, sizeof (frv_nops
));
1470 /* Locate CALL_ARG_LOCATION notes that have been misplaced
1471 and move them back to where they should be located. */
1472 last_call
= NULL_RTX
;
1473 for (insn
= get_insns (); insn
; insn
= next
)
1475 next
= NEXT_INSN (insn
);
1477 || (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
1478 && CALL_P (XVECEXP (PATTERN (insn
), 0, 0))))
1481 if (!NOTE_P (insn
) || NOTE_KIND (insn
) != NOTE_INSN_CALL_ARG_LOCATION
)
1484 if (NEXT_INSN (last_call
) == insn
)
1487 NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
1488 PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
1489 PREV_INSN (insn
) = last_call
;
1490 NEXT_INSN (insn
) = NEXT_INSN (last_call
);
1491 PREV_INSN (NEXT_INSN (insn
)) = insn
;
1492 NEXT_INSN (PREV_INSN (insn
)) = insn
;
1498 /* Return the next available temporary register in a given class. */
1501 frv_alloc_temp_reg (
1502 frv_tmp_reg_t
*info
, /* which registers are available */
1503 enum reg_class rclass
, /* register class desired */
1504 enum machine_mode mode
, /* mode to allocate register with */
1505 int mark_as_used
, /* register not available after allocation */
1506 int no_abort
) /* return NULL instead of aborting */
1508 int regno
= info
->next_reg
[ (int)rclass
];
1509 int orig_regno
= regno
;
1510 HARD_REG_SET
*reg_in_class
= ®_class_contents
[ (int)rclass
];
1515 if (TEST_HARD_REG_BIT (*reg_in_class
, regno
)
1516 && TEST_HARD_REG_BIT (info
->regs
, regno
))
1519 if (++regno
>= FIRST_PSEUDO_REGISTER
)
1521 if (regno
== orig_regno
)
1523 gcc_assert (no_abort
);
1528 nr
= HARD_REGNO_NREGS (regno
, mode
);
1529 info
->next_reg
[ (int)rclass
] = regno
+ nr
;
1532 for (i
= 0; i
< nr
; i
++)
1533 CLEAR_HARD_REG_BIT (info
->regs
, regno
+i
);
1535 return gen_rtx_REG (mode
, regno
);
1539 /* Return an rtx with the value OFFSET, which will either be a register or a
1540 signed 12-bit integer. It can be used as the second operand in an "add"
1541 instruction, or as the index in a load or store.
1543 The function returns a constant rtx if OFFSET is small enough, otherwise
1544 it loads the constant into register OFFSET_REGNO and returns that. */
1546 frv_frame_offset_rtx (int offset
)
1548 rtx offset_rtx
= GEN_INT (offset
);
1549 if (IN_RANGE (offset
, -2048, 2047))
1553 rtx reg_rtx
= gen_rtx_REG (SImode
, OFFSET_REGNO
);
1554 if (IN_RANGE (offset
, -32768, 32767))
1555 emit_insn (gen_movsi (reg_rtx
, offset_rtx
));
1558 emit_insn (gen_movsi_high (reg_rtx
, offset_rtx
));
1559 emit_insn (gen_movsi_lo_sum (reg_rtx
, offset_rtx
));
1565 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1566 prologue and epilogue uses such expressions to access the stack. */
1568 frv_frame_mem (enum machine_mode mode
, rtx base
, int offset
)
1570 return gen_rtx_MEM (mode
, gen_rtx_PLUS (Pmode
,
1572 frv_frame_offset_rtx (offset
)));
1575 /* Generate a frame-related expression:
1577 (set REG (mem (plus (sp) (const_int OFFSET)))).
1579 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1580 instructions. Marking the expressions as frame-related is superfluous if
1581 the note contains just a single set. But if the note contains a PARALLEL
1582 or SEQUENCE that has several sets, each set must be individually marked
1583 as frame-related. */
1585 frv_dwarf_store (rtx reg
, int offset
)
1587 rtx set
= gen_rtx_SET (VOIDmode
,
1588 gen_rtx_MEM (GET_MODE (reg
),
1589 plus_constant (Pmode
, stack_pointer_rtx
,
1592 RTX_FRAME_RELATED_P (set
) = 1;
1596 /* Emit a frame-related instruction whose pattern is PATTERN. The
1597 instruction is the last in a sequence that cumulatively performs the
1598 operation described by DWARF_PATTERN. The instruction is marked as
1599 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1602 frv_frame_insn (rtx pattern
, rtx dwarf_pattern
)
1604 rtx insn
= emit_insn (pattern
);
1605 RTX_FRAME_RELATED_P (insn
) = 1;
1606 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
1611 /* Emit instructions that transfer REG to or from the memory location (sp +
1612 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1613 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1614 function to store registers and only the epilogue uses it to load them.
1616 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1617 The generated instruction will use BASE as its base register. BASE may
1618 simply be the stack pointer, but if several accesses are being made to a
1619 region far away from the stack pointer, it may be more efficient to set
1620 up a temporary instead.
1622 Store instructions will be frame-related and will be annotated with the
1623 overall effect of the store. Load instructions will be followed by a
1624 (use) to prevent later optimizations from zapping them.
1626 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1627 as a temporary in such cases. */
1629 frv_frame_access (frv_frame_accessor_t
*accessor
, rtx reg
, int stack_offset
)
1631 enum machine_mode mode
= GET_MODE (reg
);
1632 rtx mem
= frv_frame_mem (mode
,
1634 stack_offset
- accessor
->base_offset
);
1636 if (accessor
->op
== FRV_LOAD
)
1638 if (SPR_P (REGNO (reg
)))
1640 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1641 emit_insn (gen_rtx_SET (VOIDmode
, temp
, mem
));
1642 emit_insn (gen_rtx_SET (VOIDmode
, reg
, temp
));
1646 /* We cannot use reg+reg addressing for DImode access. */
1648 && GET_CODE (XEXP (mem
, 0)) == PLUS
1649 && GET_CODE (XEXP (XEXP (mem
, 0), 0)) == REG
1650 && GET_CODE (XEXP (XEXP (mem
, 0), 1)) == REG
)
1652 rtx temp
= gen_rtx_REG (SImode
, TEMP_REGNO
);
1654 emit_move_insn (temp
,
1655 gen_rtx_PLUS (SImode
, XEXP (XEXP (mem
, 0), 0),
1656 XEXP (XEXP (mem
, 0), 1)));
1657 mem
= gen_rtx_MEM (DImode
, temp
);
1659 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
1665 if (SPR_P (REGNO (reg
)))
1667 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1668 emit_insn (gen_rtx_SET (VOIDmode
, temp
, reg
));
1669 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, temp
),
1670 frv_dwarf_store (reg
, stack_offset
));
1672 else if (mode
== DImode
)
1674 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1675 with a separate save for each register. */
1676 rtx reg1
= gen_rtx_REG (SImode
, REGNO (reg
));
1677 rtx reg2
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
1678 rtx set1
= frv_dwarf_store (reg1
, stack_offset
);
1679 rtx set2
= frv_dwarf_store (reg2
, stack_offset
+ 4);
1681 /* Also we cannot use reg+reg addressing. */
1682 if (GET_CODE (XEXP (mem
, 0)) == PLUS
1683 && GET_CODE (XEXP (XEXP (mem
, 0), 0)) == REG
1684 && GET_CODE (XEXP (XEXP (mem
, 0), 1)) == REG
)
1686 rtx temp
= gen_rtx_REG (SImode
, TEMP_REGNO
);
1687 emit_move_insn (temp
,
1688 gen_rtx_PLUS (SImode
, XEXP (XEXP (mem
, 0), 0),
1689 XEXP (XEXP (mem
, 0), 1)));
1690 mem
= gen_rtx_MEM (DImode
, temp
);
1693 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1694 gen_rtx_PARALLEL (VOIDmode
,
1695 gen_rtvec (2, set1
, set2
)));
1698 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1699 frv_dwarf_store (reg
, stack_offset
));
1703 /* A function that uses frv_frame_access to transfer a group of registers to
1704 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1705 is the stack information generated by frv_stack_info, and REG_SET is the
1706 number of the register set to transfer. */
1708 frv_frame_access_multi (frv_frame_accessor_t
*accessor
,
1712 frv_stack_regs_t
*regs_info
;
1715 regs_info
= &info
->regs
[reg_set
];
1716 for (regno
= regs_info
->first
; regno
<= regs_info
->last
; regno
++)
1717 if (info
->save_p
[regno
])
1718 frv_frame_access (accessor
,
1719 info
->save_p
[regno
] == REG_SAVE_2WORDS
1720 ? gen_rtx_REG (DImode
, regno
)
1721 : gen_rtx_REG (SImode
, regno
),
1722 info
->reg_offset
[regno
]);
1725 /* Save or restore callee-saved registers that are kept outside the frame
1726 header. The function saves the registers if OP is FRV_STORE and restores
1727 them if OP is FRV_LOAD. INFO is the stack information generated by
1730 frv_frame_access_standard_regs (enum frv_stack_op op
, frv_stack_t
*info
)
1732 frv_frame_accessor_t accessor
;
1735 accessor
.base
= stack_pointer_rtx
;
1736 accessor
.base_offset
= 0;
1737 frv_frame_access_multi (&accessor
, info
, STACK_REGS_GPR
);
1738 frv_frame_access_multi (&accessor
, info
, STACK_REGS_FPR
);
1739 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LCR
);
1743 /* Called after register allocation to add any instructions needed for the
1744 prologue. Using a prologue insn is favored compared to putting all of the
1745 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1746 it allows the scheduler to intermix instructions with the saves of
1747 the caller saved registers. In some cases, it might be necessary
1748 to emit a barrier instruction as the last insn to prevent such
1751 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1752 so that the debug info generation code can handle them properly. */
1754 frv_expand_prologue (void)
1756 frv_stack_t
*info
= frv_stack_info ();
1757 rtx sp
= stack_pointer_rtx
;
1758 rtx fp
= frame_pointer_rtx
;
1759 frv_frame_accessor_t accessor
;
1761 if (TARGET_DEBUG_STACK
)
1762 frv_debug_stack (info
);
1764 if (flag_stack_usage_info
)
1765 current_function_static_stack_size
= info
->total_size
;
1767 if (info
->total_size
== 0)
1770 /* We're interested in three areas of the frame here:
1772 A: the register save area
1774 C: the header after B
1776 If the frame pointer isn't used, we'll have to set up A, B and C
1777 using the stack pointer. If the frame pointer is used, we'll access
1781 B: set up using sp or a temporary (see below)
1784 We set up B using the stack pointer if the frame is small enough.
1785 Otherwise, it's more efficient to copy the old stack pointer into a
1786 temporary and use that.
1788 Note that it's important to make sure the prologue and epilogue use the
1789 same registers to access A and C, since doing otherwise will confuse
1790 the aliasing code. */
1792 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1793 isn't used, the same method will serve for C. */
1794 accessor
.op
= FRV_STORE
;
1795 if (frame_pointer_needed
&& info
->total_size
> 2048)
1797 accessor
.base
= gen_rtx_REG (Pmode
, OLD_SP_REGNO
);
1798 accessor
.base_offset
= info
->total_size
;
1799 emit_insn (gen_movsi (accessor
.base
, sp
));
1803 accessor
.base
= stack_pointer_rtx
;
1804 accessor
.base_offset
= 0;
1807 /* Allocate the stack space. */
1809 rtx asm_offset
= frv_frame_offset_rtx (-info
->total_size
);
1810 rtx dwarf_offset
= GEN_INT (-info
->total_size
);
1812 frv_frame_insn (gen_stack_adjust (sp
, sp
, asm_offset
),
1815 gen_rtx_PLUS (Pmode
, sp
, dwarf_offset
)));
1818 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1819 and point the new one to that location. */
1820 if (frame_pointer_needed
)
1822 int fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1824 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1825 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1827 rtx asm_src
= plus_constant (Pmode
, accessor
.base
,
1828 fp_offset
- accessor
.base_offset
);
1829 rtx dwarf_src
= plus_constant (Pmode
, sp
, fp_offset
);
1831 /* Store the old frame pointer at (sp + FP_OFFSET). */
1832 frv_frame_access (&accessor
, fp
, fp_offset
);
1834 /* Set up the new frame pointer. */
1835 frv_frame_insn (gen_rtx_SET (VOIDmode
, fp
, asm_src
),
1836 gen_rtx_SET (VOIDmode
, fp
, dwarf_src
));
1838 /* Access region C from the frame pointer. */
1840 accessor
.base_offset
= fp_offset
;
1843 /* Set up region C. */
1844 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STRUCT
);
1845 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LR
);
1846 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STDARG
);
1848 /* Set up region A. */
1849 frv_frame_access_standard_regs (FRV_STORE
, info
);
1851 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1852 scheduler from moving loads before the stores saving the registers. */
1853 if (info
->stdarg_size
> 0)
1854 emit_insn (gen_blockage ());
1856 /* Set up pic register/small data register for this function. */
1857 if (!TARGET_FDPIC
&& flag_pic
&& crtl
->uses_pic_offset_table
)
1858 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode
, PIC_REGNO
),
1859 gen_rtx_REG (Pmode
, LR_REGNO
),
1860 gen_rtx_REG (SImode
, OFFSET_REGNO
)));
1864 /* Under frv, all of the work is done via frv_expand_epilogue, but
1865 this function provides a convenient place to do cleanup. */
1868 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
1869 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1871 frv_stack_cache
= (frv_stack_t
*)0;
1873 /* Zap last used registers for conditional execution. */
1874 memset (&frv_ifcvt
.tmp_reg
, 0, sizeof (frv_ifcvt
.tmp_reg
));
1876 /* Release the bitmap of created insns. */
1877 BITMAP_FREE (frv_ifcvt
.scratch_insns_bitmap
);
1881 /* Called after register allocation to add any instructions needed for the
1882 epilogue. Using an epilogue insn is favored compared to putting all of the
1883 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1884 it allows the scheduler to intermix instructions with the saves of
1885 the caller saved registers. In some cases, it might be necessary
1886 to emit a barrier instruction as the last insn to prevent such
1890 frv_expand_epilogue (bool emit_return
)
1892 frv_stack_t
*info
= frv_stack_info ();
1893 rtx fp
= frame_pointer_rtx
;
1894 rtx sp
= stack_pointer_rtx
;
1898 fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1900 /* Restore the stack pointer to its original value if alloca or the like
1902 if (! crtl
->sp_is_unchanging
)
1903 emit_insn (gen_addsi3 (sp
, fp
, frv_frame_offset_rtx (-fp_offset
)));
1905 /* Restore the callee-saved registers that were used in this function. */
1906 frv_frame_access_standard_regs (FRV_LOAD
, info
);
1908 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1909 no return instruction should be emitted. */
1910 if (info
->save_p
[LR_REGNO
])
1915 /* Use the same method to access the link register's slot as we did in
1916 the prologue. In other words, use the frame pointer if available,
1917 otherwise use the stack pointer.
1919 LR_OFFSET is the offset of the link register's slot from the start
1920 of the frame and MEM is a memory rtx for it. */
1921 lr_offset
= info
->reg_offset
[LR_REGNO
];
1922 if (frame_pointer_needed
)
1923 mem
= frv_frame_mem (Pmode
, fp
, lr_offset
- fp_offset
);
1925 mem
= frv_frame_mem (Pmode
, sp
, lr_offset
);
1927 /* Load the old link register into a GPR. */
1928 return_addr
= gen_rtx_REG (Pmode
, TEMP_REGNO
);
1929 emit_insn (gen_rtx_SET (VOIDmode
, return_addr
, mem
));
1932 return_addr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1934 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1935 the load is preserved. */
1936 if (frame_pointer_needed
)
1938 emit_insn (gen_rtx_SET (VOIDmode
, fp
, gen_rtx_MEM (Pmode
, fp
)));
1942 /* Deallocate the stack frame. */
1943 if (info
->total_size
!= 0)
1945 rtx offset
= frv_frame_offset_rtx (info
->total_size
);
1946 emit_insn (gen_stack_adjust (sp
, sp
, offset
));
1949 /* If this function uses eh_return, add the final stack adjustment now. */
1950 if (crtl
->calls_eh_return
)
1951 emit_insn (gen_stack_adjust (sp
, sp
, EH_RETURN_STACKADJ_RTX
));
1954 emit_jump_insn (gen_epilogue_return (return_addr
));
1957 rtx lr
= return_addr
;
1959 if (REGNO (return_addr
) != LR_REGNO
)
1961 lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1962 emit_move_insn (lr
, return_addr
);
1970 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1973 frv_asm_output_mi_thunk (FILE *file
,
1974 tree thunk_fndecl ATTRIBUTE_UNUSED
,
1975 HOST_WIDE_INT delta
,
1976 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
1979 const char *name_func
= XSTR (XEXP (DECL_RTL (function
), 0), 0);
1980 const char *name_arg0
= reg_names
[FIRST_ARG_REGNUM
];
1981 const char *name_jmp
= reg_names
[JUMP_REGNO
];
1982 const char *parallel
= (frv_issue_rate () > 1 ? ".p" : "");
1984 /* Do the add using an addi if possible. */
1985 if (IN_RANGE (delta
, -2048, 2047))
1986 fprintf (file
, "\taddi %s,#%d,%s\n", name_arg0
, (int) delta
, name_arg0
);
1989 const char *const name_add
= reg_names
[TEMP_REGNO
];
1990 fprintf (file
, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1991 parallel
, delta
, name_add
);
1992 fprintf (file
, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1994 fprintf (file
, "\tadd %s,%s,%s\n", name_add
, name_arg0
, name_arg0
);
1999 const char *name_pic
= reg_names
[FDPIC_REGNO
];
2000 name_jmp
= reg_names
[FDPIC_FPTR_REGNO
];
2004 fprintf (file
, "\tsethi%s #gotofffuncdeschi(", parallel
);
2005 assemble_name (file
, name_func
);
2006 fprintf (file
, "),%s\n", name_jmp
);
2008 fprintf (file
, "\tsetlo #gotofffuncdesclo(");
2009 assemble_name (file
, name_func
);
2010 fprintf (file
, "),%s\n", name_jmp
);
2012 fprintf (file
, "\tldd @(%s,%s), %s\n", name_jmp
, name_pic
, name_jmp
);
2016 fprintf (file
, "\tlddo @(%s,#gotofffuncdesc12(", name_pic
);
2017 assemble_name (file
, name_func
);
2018 fprintf (file
, "\t)), %s\n", name_jmp
);
2023 fprintf (file
, "\tsethi%s #hi(", parallel
);
2024 assemble_name (file
, name_func
);
2025 fprintf (file
, "),%s\n", name_jmp
);
2027 fprintf (file
, "\tsetlo #lo(");
2028 assemble_name (file
, name_func
);
2029 fprintf (file
, "),%s\n", name_jmp
);
2033 /* Use JUMP_REGNO as a temporary PIC register. */
2034 const char *name_lr
= reg_names
[LR_REGNO
];
2035 const char *name_gppic
= name_jmp
;
2036 const char *name_tmp
= reg_names
[TEMP_REGNO
];
2038 fprintf (file
, "\tmovsg %s,%s\n", name_lr
, name_tmp
);
2039 fprintf (file
, "\tcall 1f\n");
2040 fprintf (file
, "1:\tmovsg %s,%s\n", name_lr
, name_gppic
);
2041 fprintf (file
, "\tmovgs %s,%s\n", name_tmp
, name_lr
);
2042 fprintf (file
, "\tsethi%s #gprelhi(1b),%s\n", parallel
, name_tmp
);
2043 fprintf (file
, "\tsetlo #gprello(1b),%s\n", name_tmp
);
2044 fprintf (file
, "\tsub %s,%s,%s\n", name_gppic
, name_tmp
, name_gppic
);
2046 fprintf (file
, "\tsethi%s #gprelhi(", parallel
);
2047 assemble_name (file
, name_func
);
2048 fprintf (file
, "),%s\n", name_tmp
);
2050 fprintf (file
, "\tsetlo #gprello(");
2051 assemble_name (file
, name_func
);
2052 fprintf (file
, "),%s\n", name_tmp
);
2054 fprintf (file
, "\tadd %s,%s,%s\n", name_gppic
, name_tmp
, name_jmp
);
2057 /* Jump to the function address. */
2058 fprintf (file
, "\tjmpl @(%s,%s)\n", name_jmp
, reg_names
[GPR_FIRST
+0]);
2063 /* On frv, create a frame whenever we need to create stack. */
2066 frv_frame_pointer_required (void)
2068 /* If we forgoing the usual linkage requirements, we only need
2069 a frame pointer if the stack pointer might change. */
2070 if (!TARGET_LINKED_FP
)
2071 return !crtl
->sp_is_unchanging
;
2073 if (! crtl
->is_leaf
)
2076 if (get_frame_size () != 0)
2082 if (!crtl
->sp_is_unchanging
)
2085 if (!TARGET_FDPIC
&& flag_pic
&& crtl
->uses_pic_offset_table
)
2091 if (cfun
->machine
->frame_needed
)
2098 /* Worker function for TARGET_CAN_ELIMINATE. */
2101 frv_can_eliminate (const int from
, const int to
)
2103 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
2104 ? ! frame_pointer_needed
2108 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2109 initial difference between the specified pair of registers. This macro must
2110 be defined if `ELIMINABLE_REGS' is defined. */
2112 /* See frv_stack_info for more details on the frv stack frame. */
2115 frv_initial_elimination_offset (int from
, int to
)
2117 frv_stack_t
*info
= frv_stack_info ();
2120 if (to
== STACK_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2121 ret
= info
->total_size
- info
->pretend_size
;
2123 else if (to
== STACK_POINTER_REGNUM
&& from
== FRAME_POINTER_REGNUM
)
2124 ret
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
2126 else if (to
== FRAME_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2127 ret
= (info
->total_size
2128 - info
->reg_offset
[FRAME_POINTER_REGNUM
]
2129 - info
->pretend_size
);
2134 if (TARGET_DEBUG_STACK
)
2135 fprintf (stderr
, "Eliminate %s to %s by adding %d\n",
2136 reg_names
[from
], reg_names
[to
], ret
);
2142 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2145 frv_setup_incoming_varargs (cumulative_args_t cum_v
,
2146 enum machine_mode mode
,
2147 tree type ATTRIBUTE_UNUSED
,
2151 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2153 if (TARGET_DEBUG_ARG
)
2155 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2156 *cum
, GET_MODE_NAME (mode
), *pretend_size
, second_time
);
2160 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2163 frv_expand_builtin_saveregs (void)
2165 int offset
= UNITS_PER_WORD
* FRV_NUM_ARG_REGS
;
2167 if (TARGET_DEBUG_ARG
)
2168 fprintf (stderr
, "expand_builtin_saveregs: offset from ap = %d\n",
2171 return gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
, GEN_INT (- offset
));
2175 /* Expand __builtin_va_start to do the va_start macro. */
2178 frv_expand_builtin_va_start (tree valist
, rtx nextarg
)
2181 int num
= crtl
->args
.info
- FIRST_ARG_REGNUM
- FRV_NUM_ARG_REGS
;
2183 nextarg
= gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
,
2184 GEN_INT (UNITS_PER_WORD
* num
));
2186 if (TARGET_DEBUG_ARG
)
2188 fprintf (stderr
, "va_start: args_info = %d, num = %d\n",
2189 crtl
->args
.info
, num
);
2191 debug_rtx (nextarg
);
2194 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
2195 fold_convert (TREE_TYPE (valist
),
2196 make_tree (sizetype
, nextarg
)));
2197 TREE_SIDE_EFFECTS (t
) = 1;
2199 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2203 /* Expand a block move operation, and return 1 if successful. Return 0
2204 if we should let the compiler generate normal code.
2206 operands[0] is the destination
2207 operands[1] is the source
2208 operands[2] is the length
2209 operands[3] is the alignment */
2211 /* Maximum number of loads to do before doing the stores */
2212 #ifndef MAX_MOVE_REG
2213 #define MAX_MOVE_REG 4
2216 /* Maximum number of total loads to do. */
2217 #ifndef TOTAL_MOVE_REG
2218 #define TOTAL_MOVE_REG 8
2222 frv_expand_block_move (rtx operands
[])
2224 rtx orig_dest
= operands
[0];
2225 rtx orig_src
= operands
[1];
2226 rtx bytes_rtx
= operands
[2];
2227 rtx align_rtx
= operands
[3];
2228 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2241 rtx stores
[MAX_MOVE_REG
];
2243 enum machine_mode mode
;
2245 /* If this is not a fixed size move, just call memcpy. */
2249 /* This should be a fixed size alignment. */
2250 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
2252 align
= INTVAL (align_rtx
);
2254 /* Anything to move? */
2255 bytes
= INTVAL (bytes_rtx
);
2259 /* Don't support real large moves. */
2260 if (bytes
> TOTAL_MOVE_REG
*align
)
2263 /* Move the address into scratch registers. */
2264 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2265 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2267 num_reg
= offset
= 0;
2268 for ( ; bytes
> 0; (bytes
-= move_bytes
), (offset
+= move_bytes
))
2270 /* Calculate the correct offset for src/dest. */
2274 dest_addr
= dest_reg
;
2278 src_addr
= plus_constant (Pmode
, src_reg
, offset
);
2279 dest_addr
= plus_constant (Pmode
, dest_reg
, offset
);
2282 /* Generate the appropriate load and store, saving the stores
2284 if (bytes
>= 4 && align
>= 4)
2286 else if (bytes
>= 2 && align
>= 2)
2291 move_bytes
= GET_MODE_SIZE (mode
);
2292 tmp_reg
= gen_reg_rtx (mode
);
2293 src_mem
= change_address (orig_src
, mode
, src_addr
);
2294 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2295 emit_insn (gen_rtx_SET (VOIDmode
, tmp_reg
, src_mem
));
2296 stores
[num_reg
++] = gen_rtx_SET (VOIDmode
, dest_mem
, tmp_reg
);
2298 if (num_reg
>= MAX_MOVE_REG
)
2300 for (i
= 0; i
< num_reg
; i
++)
2301 emit_insn (stores
[i
]);
2306 for (i
= 0; i
< num_reg
; i
++)
2307 emit_insn (stores
[i
]);
2313 /* Expand a block clear operation, and return 1 if successful. Return 0
2314 if we should let the compiler generate normal code.
2316 operands[0] is the destination
2317 operands[1] is the length
2318 operands[3] is the alignment */
2321 frv_expand_block_clear (rtx operands
[])
2323 rtx orig_dest
= operands
[0];
2324 rtx bytes_rtx
= operands
[1];
2325 rtx align_rtx
= operands
[3];
2326 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2334 enum machine_mode mode
;
2336 /* If this is not a fixed size move, just call memcpy. */
2340 /* This should be a fixed size alignment. */
2341 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
2343 align
= INTVAL (align_rtx
);
2345 /* Anything to move? */
2346 bytes
= INTVAL (bytes_rtx
);
2350 /* Don't support real large clears. */
2351 if (bytes
> TOTAL_MOVE_REG
*align
)
2354 /* Move the address into a scratch register. */
2355 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2358 for ( ; bytes
> 0; (bytes
-= clear_bytes
), (offset
+= clear_bytes
))
2360 /* Calculate the correct offset for src/dest. */
2361 dest_addr
= ((offset
== 0)
2363 : plus_constant (Pmode
, dest_reg
, offset
));
2365 /* Generate the appropriate store of gr0. */
2366 if (bytes
>= 4 && align
>= 4)
2368 else if (bytes
>= 2 && align
>= 2)
2373 clear_bytes
= GET_MODE_SIZE (mode
);
2374 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2375 emit_insn (gen_rtx_SET (VOIDmode
, dest_mem
, const0_rtx
));
2382 /* The following variable is used to output modifiers of assembler
2383 code of the current output insn. */
2385 static rtx
*frv_insn_operands
;
2387 /* The following function is used to add assembler insn code suffix .p
2388 if it is necessary. */
2391 frv_asm_output_opcode (FILE *f
, const char *ptr
)
2395 if (frv_insn_packing_flag
<= 0)
2398 for (; *ptr
&& *ptr
!= ' ' && *ptr
!= '\t';)
2401 if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
2402 || (*ptr
>= 'A' && *ptr
<= 'Z')))
2404 int letter
= *ptr
++;
2407 frv_print_operand (f
, frv_insn_operands
[c
], letter
);
2408 while ((c
= *ptr
) >= '0' && c
<= '9')
2420 /* Set up the packing bit for the current output insn. Note that this
2421 function is not called for asm insns. */
2424 frv_final_prescan_insn (rtx insn
, rtx
*opvec
,
2425 int noperands ATTRIBUTE_UNUSED
)
2429 if (frv_insn_packing_flag
>= 0)
2431 frv_insn_operands
= opvec
;
2432 frv_insn_packing_flag
= PACKING_FLAG_P (insn
);
2434 else if (recog_memoized (insn
) >= 0
2435 && get_attr_acc_group (insn
) == ACC_GROUP_ODD
)
2436 /* Packing optimizations have been disabled, but INSN can only
2437 be issued in M1. Insert an mnop in M0. */
2438 fprintf (asm_out_file
, "\tmnop.p\n");
2444 /* A C expression whose value is RTL representing the address in a stack frame
2445 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2446 an RTL expression for the address of the stack frame itself.
2448 If you don't define this macro, the default is to return the value of
2449 FRAMEADDR--that is, the stack frame address is also the address of the stack
2450 word that points to the previous frame. */
2452 /* The default is correct, but we need to make sure the frame gets created. */
2454 frv_dynamic_chain_address (rtx frame
)
2456 cfun
->machine
->frame_needed
= 1;
2461 /* A C expression whose value is RTL representing the value of the return
2462 address for the frame COUNT steps up from the current frame, after the
2463 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2464 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2467 The value of the expression must always be the correct address when COUNT is
2468 zero, but may be `NULL_RTX' if there is not way to determine the return
2469 address of other frames. */
2472 frv_return_addr_rtx (int count
, rtx frame
)
2476 cfun
->machine
->frame_needed
= 1;
2477 return gen_rtx_MEM (Pmode
, plus_constant (Pmode
, frame
, 8));
2480 /* Given a memory reference MEMREF, interpret the referenced memory as
2481 an array of MODE values, and return a reference to the element
2482 specified by INDEX. Assume that any pre-modification implicit in
2483 MEMREF has already happened.
2485 MEMREF must be a legitimate operand for modes larger than SImode.
2486 frv_legitimate_address_p forbids register+register addresses, which
2487 this function cannot handle. */
2489 frv_index_memory (rtx memref
, enum machine_mode mode
, int index
)
2491 rtx base
= XEXP (memref
, 0);
2492 if (GET_CODE (base
) == PRE_MODIFY
)
2493 base
= XEXP (base
, 0);
2494 return change_address (memref
, mode
,
2495 plus_constant (Pmode
, base
,
2496 index
* GET_MODE_SIZE (mode
)));
2500 /* Print a memory address as an operand to reference that memory location. */
2502 frv_print_operand_address (FILE * stream
, rtx x
)
2504 if (GET_CODE (x
) == MEM
)
2507 switch (GET_CODE (x
))
2510 fputs (reg_names
[ REGNO (x
)], stream
);
2514 fprintf (stream
, "%ld", (long) INTVAL (x
));
2518 assemble_name (stream
, XSTR (x
, 0));
2523 output_addr_const (stream
, x
);
2527 /* Poorly constructed asm statements can trigger this alternative.
2528 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2529 frv_print_operand_memory_reference (stream
, x
, 0);
2536 fatal_insn ("bad insn to frv_print_operand_address:", x
);
2541 frv_print_operand_memory_reference_reg (FILE * stream
, rtx x
)
2543 int regno
= true_regnum (x
);
2545 fputs (reg_names
[regno
], stream
);
2547 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x
);
2550 /* Print a memory reference suitable for the ld/st instructions. */
2553 frv_print_operand_memory_reference (FILE * stream
, rtx x
, int addr_offset
)
2555 struct frv_unspec unspec
;
2559 switch (GET_CODE (x
))
2566 case PRE_MODIFY
: /* (pre_modify (reg) (plus (reg) (reg))) */
2568 x1
= XEXP (XEXP (x
, 1), 1);
2578 if (GET_CODE (x0
) == CONST_INT
)
2586 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2595 else if (GET_CODE (x1
) != CONST_INT
)
2596 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2599 fputs ("@(", stream
);
2601 fputs (reg_names
[GPR_R0
], stream
);
2602 else if (GET_CODE (x0
) == REG
|| GET_CODE (x0
) == SUBREG
)
2603 frv_print_operand_memory_reference_reg (stream
, x0
);
2605 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2607 fputs (",", stream
);
2609 fputs (reg_names
[GPR_R0
], stream
);
2613 switch (GET_CODE (x1
))
2617 frv_print_operand_memory_reference_reg (stream
, x1
);
2621 fprintf (stream
, "%ld", (long) (INTVAL (x1
) + addr_offset
));
2625 if (!frv_const_unspec_p (x1
, &unspec
))
2626 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1
);
2627 frv_output_const_unspec (stream
, &unspec
);
2631 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2635 fputs (")", stream
);
2639 /* Return 2 for likely branches and 0 for non-likely branches */
2641 #define FRV_JUMP_LIKELY 2
2642 #define FRV_JUMP_NOT_LIKELY 0
2645 frv_print_operand_jump_hint (rtx insn
)
2650 HOST_WIDE_INT prob
= -1;
2651 enum { UNKNOWN
, BACKWARD
, FORWARD
} jump_type
= UNKNOWN
;
2653 gcc_assert (GET_CODE (insn
) == JUMP_INSN
);
2655 /* Assume any non-conditional jump is likely. */
2656 if (! any_condjump_p (insn
))
2657 ret
= FRV_JUMP_LIKELY
;
2661 labelref
= condjump_label (insn
);
2664 rtx label
= XEXP (labelref
, 0);
2665 jump_type
= (insn_current_address
> INSN_ADDRESSES (INSN_UID (label
))
2670 note
= find_reg_note (insn
, REG_BR_PROB
, 0);
2672 ret
= ((jump_type
== BACKWARD
) ? FRV_JUMP_LIKELY
: FRV_JUMP_NOT_LIKELY
);
2676 prob
= INTVAL (XEXP (note
, 0));
2677 ret
= ((prob
>= (REG_BR_PROB_BASE
/ 2))
2679 : FRV_JUMP_NOT_LIKELY
);
2691 case UNKNOWN
: direction
= "unknown jump direction"; break;
2692 case BACKWARD
: direction
= "jump backward"; break;
2693 case FORWARD
: direction
= "jump forward"; break;
2697 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2698 IDENTIFIER_POINTER (DECL_NAME (current_function_decl
)),
2699 (long)INSN_UID (insn
), direction
, (long)prob
,
2700 (long)REG_BR_PROB_BASE
, ret
);
2708 /* Return the comparison operator to use for CODE given that the ICC
2712 comparison_string (enum rtx_code code
, rtx op0
)
2714 bool is_nz_p
= GET_MODE (op0
) == CC_NZmode
;
2717 default: output_operand_lossage ("bad condition code");
2718 case EQ
: return "eq";
2719 case NE
: return "ne";
2720 case LT
: return is_nz_p
? "n" : "lt";
2721 case LE
: return "le";
2722 case GT
: return "gt";
2723 case GE
: return is_nz_p
? "p" : "ge";
2724 case LTU
: return is_nz_p
? "no" : "c";
2725 case LEU
: return is_nz_p
? "eq" : "ls";
2726 case GTU
: return is_nz_p
? "ne" : "hi";
2727 case GEU
: return is_nz_p
? "ra" : "nc";
2731 /* Print an operand to an assembler instruction.
2733 `%' followed by a letter and a digit says to output an operand in an
2734 alternate fashion. Four letters have standard, built-in meanings
2735 described below. The hook `TARGET_PRINT_OPERAND' can define
2736 additional letters with nonstandard meanings.
2738 `%cDIGIT' can be used to substitute an operand that is a constant value
2739 without the syntax that normally indicates an immediate operand.
2741 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2744 `%aDIGIT' can be used to substitute an operand as if it were a memory
2745 reference, with the actual operand treated as the address. This may be
2746 useful when outputting a "load address" instruction, because often the
2747 assembler syntax for such an instruction requires you to write the operand
2748 as if it were a memory reference.
2750 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2752 `%=' outputs a number which is unique to each instruction in the entire
2753 compilation. This is useful for making local labels to be referred to more
2754 than once in a single template that generates multiple assembler
2757 `%' followed by a punctuation character specifies a substitution that
2758 does not use an operand. Only one case is standard: `%%' outputs a
2759 `%' into the assembler code. Other nonstandard cases can be defined
2760 in the `TARGET_PRINT_OPERAND' hook. You must also define which
2761 punctuation characters are valid with the
2762 `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook. */
2765 frv_print_operand (FILE * file
, rtx x
, int code
)
2767 struct frv_unspec unspec
;
2768 HOST_WIDE_INT value
;
2771 if (code
!= 0 && !ISALPHA (code
))
2774 else if (GET_CODE (x
) == CONST_INT
)
2777 else if (GET_CODE (x
) == CONST_DOUBLE
)
2779 if (GET_MODE (x
) == SFmode
)
2784 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
2785 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2789 else if (GET_MODE (x
) == VOIDmode
)
2790 value
= CONST_DOUBLE_LOW (x
);
2793 fatal_insn ("bad insn in frv_print_operand, bad const_double", x
);
2804 fputs (reg_names
[GPR_R0
], file
);
2808 fprintf (file
, "%d", frv_print_operand_jump_hint (current_output_insn
));
2812 /* Output small data area base register (gr16). */
2813 fputs (reg_names
[SDA_BASE_REG
], file
);
2817 /* Output pic register (gr17). */
2818 fputs (reg_names
[PIC_REGNO
], file
);
2822 /* Output the temporary integer CCR register. */
2823 fputs (reg_names
[ICR_TEMP
], file
);
2827 /* Output the temporary integer CC register. */
2828 fputs (reg_names
[ICC_TEMP
], file
);
2831 /* case 'a': print an address. */
2834 /* Print appropriate test for integer branch false operation. */
2835 fputs (comparison_string (reverse_condition (GET_CODE (x
)),
2836 XEXP (x
, 0)), file
);
2840 /* Print appropriate test for integer branch true operation. */
2841 fputs (comparison_string (GET_CODE (x
), XEXP (x
, 0)), file
);
2845 /* Print 1 for a NE and 0 for an EQ to give the final argument
2846 for a conditional instruction. */
2847 if (GET_CODE (x
) == NE
)
2850 else if (GET_CODE (x
) == EQ
)
2854 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x
);
2858 /* Print appropriate test for floating point branch false operation. */
2859 switch (GET_CODE (x
))
2862 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x
);
2864 case EQ
: fputs ("ne", file
); break;
2865 case NE
: fputs ("eq", file
); break;
2866 case LT
: fputs ("uge", file
); break;
2867 case LE
: fputs ("ug", file
); break;
2868 case GT
: fputs ("ule", file
); break;
2869 case GE
: fputs ("ul", file
); break;
2874 /* Print appropriate test for floating point branch true operation. */
2875 switch (GET_CODE (x
))
2878 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x
);
2880 case EQ
: fputs ("eq", file
); break;
2881 case NE
: fputs ("ne", file
); break;
2882 case LT
: fputs ("lt", file
); break;
2883 case LE
: fputs ("le", file
); break;
2884 case GT
: fputs ("gt", file
); break;
2885 case GE
: fputs ("ge", file
); break;
2890 /* Print appropriate GOT function. */
2891 if (GET_CODE (x
) != CONST_INT
)
2892 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x
);
2893 fputs (unspec_got_name (INTVAL (x
)), file
);
2897 /* Print 'i' if the operand is a constant, or is a memory reference that
2899 if (GET_CODE (x
) == MEM
)
2900 x
= ((GET_CODE (XEXP (x
, 0)) == PLUS
)
2901 ? XEXP (XEXP (x
, 0), 1)
2903 else if (GET_CODE (x
) == PLUS
)
2906 switch (GET_CODE (x
))
2920 /* For jump instructions, print 'i' if the operand is a constant or
2921 is an expression that adds a constant. */
2922 if (GET_CODE (x
) == CONST_INT
)
2927 if (GET_CODE (x
) == CONST_INT
2928 || (GET_CODE (x
) == PLUS
2929 && (GET_CODE (XEXP (x
, 1)) == CONST_INT
2930 || GET_CODE (XEXP (x
, 0)) == CONST_INT
)))
2936 /* Print the lower register of a double word register pair */
2937 if (GET_CODE (x
) == REG
)
2938 fputs (reg_names
[ REGNO (x
)+1 ], file
);
2940 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x
);
2943 /* case 'l': print a LABEL_REF. */
2947 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2948 for the second word of double memory operations. */
2949 offset
= (code
== 'M') ? 0 : UNITS_PER_WORD
;
2950 switch (GET_CODE (x
))
2953 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x
);
2956 frv_print_operand_memory_reference (file
, XEXP (x
, 0), offset
);
2964 frv_print_operand_memory_reference (file
, x
, offset
);
2970 /* Print the opcode of a command. */
2971 switch (GET_CODE (x
))
2974 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x
);
2976 case PLUS
: fputs ("add", file
); break;
2977 case MINUS
: fputs ("sub", file
); break;
2978 case AND
: fputs ("and", file
); break;
2979 case IOR
: fputs ("or", file
); break;
2980 case XOR
: fputs ("xor", file
); break;
2981 case ASHIFT
: fputs ("sll", file
); break;
2982 case ASHIFTRT
: fputs ("sra", file
); break;
2983 case LSHIFTRT
: fputs ("srl", file
); break;
2987 /* case 'n': negate and print a constant int. */
2990 /* Print PIC label using operand as the number. */
2991 if (GET_CODE (x
) != CONST_INT
)
2992 fatal_insn ("bad insn to frv_print_operand, P modifier:", x
);
2994 fprintf (file
, ".LCF%ld", (long)INTVAL (x
));
2998 /* Print 'u' if the operand is a update load/store. */
2999 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
3004 /* If value is 0, print gr0, otherwise it must be a register. */
3005 if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0)
3006 fputs (reg_names
[GPR_R0
], file
);
3008 else if (GET_CODE (x
) == REG
)
3009 fputs (reg_names
[REGNO (x
)], file
);
3012 fatal_insn ("bad insn in frv_print_operand, z case", x
);
3016 /* Print constant in hex. */
3017 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
3019 fprintf (file
, "%s0x%.4lx", IMMEDIATE_PREFIX
, (long) value
);
3026 if (GET_CODE (x
) == REG
)
3027 fputs (reg_names
[REGNO (x
)], file
);
3029 else if (GET_CODE (x
) == CONST_INT
3030 || GET_CODE (x
) == CONST_DOUBLE
)
3031 fprintf (file
, "%s%ld", IMMEDIATE_PREFIX
, (long) value
);
3033 else if (frv_const_unspec_p (x
, &unspec
))
3034 frv_output_const_unspec (file
, &unspec
);
3036 else if (GET_CODE (x
) == MEM
)
3037 frv_print_operand_address (file
, XEXP (x
, 0));
3039 else if (CONSTANT_ADDRESS_P (x
))
3040 frv_print_operand_address (file
, x
);
3043 fatal_insn ("bad insn in frv_print_operand, 0 case", x
);
3048 fatal_insn ("frv_print_operand: unknown code", x
);
3056 frv_print_operand_punct_valid_p (unsigned char code
)
3058 return (code
== '.' || code
== '#' || code
== '@' || code
== '~'
3059 || code
== '*' || code
== '&');
3063 /* A C statement (sans semicolon) for initializing the variable CUM for the
3064 state at the beginning of the argument list. The variable has type
3065 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3066 of the function which will receive the args, or 0 if the args are to a
3067 compiler support library function. The value of INDIRECT is nonzero when
3068 processing an indirect call, for example a call through a function pointer.
3069 The value of INDIRECT is zero for a call to an explicitly named function, a
3070 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3071 arguments for the function being compiled.
3073 When processing a call to a compiler support library function, LIBNAME
3074 identifies which one. It is a `symbol_ref' rtx which contains the name of
3075 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3076 being processed. Thus, each time this macro is called, either LIBNAME or
3077 FNTYPE is nonzero, but never both of them at once. */
3080 frv_init_cumulative_args (CUMULATIVE_ARGS
*cum
,
3086 *cum
= FIRST_ARG_REGNUM
;
3088 if (TARGET_DEBUG_ARG
)
3090 fprintf (stderr
, "\ninit_cumulative_args:");
3091 if (!fndecl
&& fntype
)
3092 fputs (" indirect", stderr
);
3095 fputs (" incoming", stderr
);
3099 tree ret_type
= TREE_TYPE (fntype
);
3100 fprintf (stderr
, " return=%s,",
3101 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
3104 if (libname
&& GET_CODE (libname
) == SYMBOL_REF
)
3105 fprintf (stderr
, " libname=%s", XSTR (libname
, 0));
3107 if (cfun
->returns_struct
)
3108 fprintf (stderr
, " return-struct");
3110 putc ('\n', stderr
);
3115 /* Return true if we should pass an argument on the stack rather than
3119 frv_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
3121 if (mode
== BLKmode
)
3125 return AGGREGATE_TYPE_P (type
);
3128 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3129 argument with the specified mode and type. If it is not defined,
3130 `PARM_BOUNDARY' is used for all arguments. */
3133 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED
,
3134 const_tree type ATTRIBUTE_UNUSED
)
3136 return BITS_PER_WORD
;
3140 frv_function_arg_1 (cumulative_args_t cum_v
, enum machine_mode mode
,
3141 const_tree type ATTRIBUTE_UNUSED
, bool named
,
3142 bool incoming ATTRIBUTE_UNUSED
)
3144 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
3146 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3151 /* Return a marker for use in the call instruction. */
3152 if (xmode
== VOIDmode
)
3158 else if (arg_num
<= LAST_ARG_REGNUM
)
3160 ret
= gen_rtx_REG (xmode
, arg_num
);
3161 debstr
= reg_names
[arg_num
];
3170 if (TARGET_DEBUG_ARG
)
3172 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3173 arg_num
, GET_MODE_NAME (mode
), named
, GET_MODE_SIZE (mode
), debstr
);
3179 frv_function_arg (cumulative_args_t cum
, enum machine_mode mode
,
3180 const_tree type
, bool named
)
3182 return frv_function_arg_1 (cum
, mode
, type
, named
, false);
3186 frv_function_incoming_arg (cumulative_args_t cum
, enum machine_mode mode
,
3187 const_tree type
, bool named
)
3189 return frv_function_arg_1 (cum
, mode
, type
, named
, true);
3193 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3194 advance past an argument in the argument list. The values MODE, TYPE and
3195 NAMED describe that argument. Once this is done, the variable CUM is
3196 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3198 This macro need not do anything if the argument in question was passed on
3199 the stack. The compiler knows how to track the amount of stack space used
3200 for arguments without any special help. */
3203 frv_function_arg_advance (cumulative_args_t cum_v
,
3204 enum machine_mode mode
,
3205 const_tree type ATTRIBUTE_UNUSED
,
3208 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
3210 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3211 int bytes
= GET_MODE_SIZE (xmode
);
3212 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3215 *cum
= arg_num
+ words
;
3217 if (TARGET_DEBUG_ARG
)
3219 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3220 arg_num
, GET_MODE_NAME (mode
), named
, words
* UNITS_PER_WORD
);
3224 /* A C expression for the number of words, at the beginning of an argument,
3225 must be put in registers. The value must be zero for arguments that are
3226 passed entirely in registers or that are entirely pushed on the stack.
3228 On some machines, certain arguments must be passed partially in registers
3229 and partially in memory. On these machines, typically the first N words of
3230 arguments are passed in registers, and the rest on the stack. If a
3231 multi-word argument (a `double' or a structure) crosses that boundary, its
3232 first few words must be passed in registers and the rest must be pushed.
3233 This macro tells the compiler when this occurs, and how many of the words
3234 should go in registers.
3236 `FUNCTION_ARG' for these arguments should return the first register to be
3237 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3238 the called function. */
3241 frv_arg_partial_bytes (cumulative_args_t cum
, enum machine_mode mode
,
3242 tree type ATTRIBUTE_UNUSED
, bool named ATTRIBUTE_UNUSED
)
3245 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3246 int bytes
= GET_MODE_SIZE (xmode
);
3247 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3248 int arg_num
= *get_cumulative_args (cum
);
3251 ret
= ((arg_num
<= LAST_ARG_REGNUM
&& arg_num
+ words
> LAST_ARG_REGNUM
+1)
3252 ? LAST_ARG_REGNUM
- arg_num
+ 1
3254 ret
*= UNITS_PER_WORD
;
3256 if (TARGET_DEBUG_ARG
&& ret
)
3257 fprintf (stderr
, "frv_arg_partial_bytes: %d\n", ret
);
3263 /* Implements TARGET_FUNCTION_VALUE. */
3266 frv_function_value (const_tree valtype
,
3267 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
3268 bool outgoing ATTRIBUTE_UNUSED
)
3270 return gen_rtx_REG (TYPE_MODE (valtype
), RETURN_VALUE_REGNUM
);
3274 /* Implements TARGET_LIBCALL_VALUE. */
3277 frv_libcall_value (enum machine_mode mode
,
3278 const_rtx fun ATTRIBUTE_UNUSED
)
3280 return gen_rtx_REG (mode
, RETURN_VALUE_REGNUM
);
3284 /* Implements FUNCTION_VALUE_REGNO_P. */
3287 frv_function_value_regno_p (const unsigned int regno
)
3289 return (regno
== RETURN_VALUE_REGNUM
);
3292 /* Return true if a register is ok to use as a base or index register. */
3294 static FRV_INLINE
int
3295 frv_regno_ok_for_base_p (int regno
, int strict_p
)
3301 return (reg_renumber
[regno
] >= 0 && GPR_P (reg_renumber
[regno
]));
3303 if (regno
== ARG_POINTER_REGNUM
)
3306 return (regno
>= FIRST_PSEUDO_REGISTER
);
3310 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3311 RTX) is a legitimate memory address on the target machine for a memory
3312 operand of mode MODE.
3314 It usually pays to define several simpler macros to serve as subroutines for
3315 this one. Otherwise it may be too complicated to understand.
3317 This macro must exist in two variants: a strict variant and a non-strict
3318 one. The strict variant is used in the reload pass. It must be defined so
3319 that any pseudo-register that has not been allocated a hard register is
3320 considered a memory reference. In contexts where some kind of register is
3321 required, a pseudo-register with no hard register must be rejected.
3323 The non-strict variant is used in other passes. It must be defined to
3324 accept all pseudo-registers in every context where some kind of register is
3327 Compiler source files that want to use the strict variant of this macro
3328 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3329 conditional to define the strict variant in that case and the non-strict
3332 Normally, constant addresses which are the sum of a `symbol_ref' and an
3333 integer are stored inside a `const' RTX to mark them as constant.
3334 Therefore, there is no need to recognize such sums specifically as
3335 legitimate addresses. Normally you would simply recognize any `const' as
3338 Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle
3339 constant sums that are not marked with `const'. It assumes that a
3340 naked `plus' indicates indexing. If so, then you *must* reject such
3341 naked constant sums as illegitimate addresses, so that none of them
3342 will be given to `TARGET_PRINT_OPERAND_ADDRESS'. */
3345 frv_legitimate_address_p_1 (enum machine_mode mode
,
3349 int allow_double_reg_p
)
3353 HOST_WIDE_INT value
;
3356 if (FRV_SYMBOL_REF_TLS_P (x
))
3359 switch (GET_CODE (x
))
3366 if (GET_CODE (x
) != REG
)
3372 ret
= frv_regno_ok_for_base_p (REGNO (x
), strict_p
);
3378 if (GET_CODE (x0
) != REG
3379 || ! frv_regno_ok_for_base_p (REGNO (x0
), strict_p
)
3380 || GET_CODE (x1
) != PLUS
3381 || ! rtx_equal_p (x0
, XEXP (x1
, 0))
3382 || GET_CODE (XEXP (x1
, 1)) != REG
3383 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1
, 1)), strict_p
))
3390 /* 12-bit immediate */
3395 ret
= IN_RANGE (INTVAL (x
), -2048, 2047);
3397 /* If we can't use load/store double operations, make sure we can
3398 address the second word. */
3399 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3400 ret
= IN_RANGE (INTVAL (x
) + GET_MODE_SIZE (mode
) - 1,
3409 if (GET_CODE (x0
) == SUBREG
)
3410 x0
= SUBREG_REG (x0
);
3412 if (GET_CODE (x0
) != REG
)
3415 regno0
= REGNO (x0
);
3416 if (!frv_regno_ok_for_base_p (regno0
, strict_p
))
3419 switch (GET_CODE (x1
))
3425 x1
= SUBREG_REG (x1
);
3426 if (GET_CODE (x1
) != REG
)
3432 /* Do not allow reg+reg addressing for modes > 1 word if we
3433 can't depend on having move double instructions. */
3434 if (!allow_double_reg_p
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3437 ret
= frv_regno_ok_for_base_p (REGNO (x1
), strict_p
);
3441 /* 12-bit immediate */
3446 value
= INTVAL (x1
);
3447 ret
= IN_RANGE (value
, -2048, 2047);
3449 /* If we can't use load/store double operations, make sure we can
3450 address the second word. */
3451 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3452 ret
= IN_RANGE (value
+ GET_MODE_SIZE (mode
) - 1, -2048, 2047);
3457 if (!condexec_p
&& got12_operand (x1
, VOIDmode
))
3465 if (TARGET_DEBUG_ADDR
)
3467 fprintf (stderr
, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3468 GET_MODE_NAME (mode
), ret
, (strict_p
) ? "" : "not ",
3469 (condexec_p
) ? ", inside conditional code" : "");
3477 frv_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
3479 return frv_legitimate_address_p_1 (mode
, x
, strict_p
, FALSE
, FALSE
);
3482 /* Given an ADDR, generate code to inline the PLT. */
3484 gen_inlined_tls_plt (rtx addr
)
3487 rtx picreg
= get_hard_reg_initial_val (Pmode
, FDPIC_REG
);
3490 dest
= gen_reg_rtx (DImode
);
3497 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3498 calll #gettlsoff(ADDR)@(gr8, gr0)
3500 emit_insn (gen_tls_lddi (dest
, addr
, picreg
));
3507 sethi.p #gottlsdeschi(ADDR), gr8
3508 setlo #gottlsdesclo(ADDR), gr8
3509 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3510 calll #gettlsoff(ADDR)@(gr8, gr0)
3512 rtx reguse
= gen_reg_rtx (Pmode
);
3513 emit_insn (gen_tlsoff_hilo (reguse
, addr
, GEN_INT (R_FRV_GOTTLSDESCHI
)));
3514 emit_insn (gen_tls_tlsdesc_ldd (dest
, picreg
, reguse
, addr
));
3517 retval
= gen_reg_rtx (Pmode
);
3518 emit_insn (gen_tls_indirect_call (retval
, addr
, dest
, picreg
));
3522 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3523 the destination address. */
3525 gen_tlsmoff (rtx addr
, rtx reg
)
3527 rtx dest
= gen_reg_rtx (Pmode
);
3531 /* sethi.p #tlsmoffhi(x), grA
3532 setlo #tlsmofflo(x), grA
3534 dest
= gen_reg_rtx (Pmode
);
3535 emit_insn (gen_tlsoff_hilo (dest
, addr
,
3536 GEN_INT (R_FRV_TLSMOFFHI
)));
3537 dest
= gen_rtx_PLUS (Pmode
, dest
, reg
);
3541 /* addi grB, #tlsmoff12(x), grC
3543 ld/st @(grB, #tlsmoff12(x)), grC
3545 dest
= gen_reg_rtx (Pmode
);
3546 emit_insn (gen_symGOTOFF2reg_i (dest
, addr
, reg
,
3547 GEN_INT (R_FRV_TLSMOFF12
)));
3552 /* Generate code for a TLS address. */
3554 frv_legitimize_tls_address (rtx addr
, enum tls_model model
)
3556 rtx dest
, tp
= gen_rtx_REG (Pmode
, 29);
3557 rtx picreg
= get_hard_reg_initial_val (Pmode
, 15);
3561 case TLS_MODEL_INITIAL_EXEC
:
3565 ldi @(gr15, #gottlsoff12(x)), gr5
3567 dest
= gen_reg_rtx (Pmode
);
3568 emit_insn (gen_tls_load_gottlsoff12 (dest
, addr
, picreg
));
3569 dest
= gen_rtx_PLUS (Pmode
, tp
, dest
);
3573 /* -fPIC or anything else.
3575 sethi.p #gottlsoffhi(x), gr14
3576 setlo #gottlsofflo(x), gr14
3577 ld #tlsoff(x)@(gr15, gr14), gr9
3579 rtx tmp
= gen_reg_rtx (Pmode
);
3580 dest
= gen_reg_rtx (Pmode
);
3581 emit_insn (gen_tlsoff_hilo (tmp
, addr
,
3582 GEN_INT (R_FRV_GOTTLSOFF_HI
)));
3584 emit_insn (gen_tls_tlsoff_ld (dest
, picreg
, tmp
, addr
));
3585 dest
= gen_rtx_PLUS (Pmode
, tp
, dest
);
3588 case TLS_MODEL_LOCAL_DYNAMIC
:
3592 if (TARGET_INLINE_PLT
)
3593 retval
= gen_inlined_tls_plt (GEN_INT (0));
3596 /* call #gettlsoff(0) */
3597 retval
= gen_reg_rtx (Pmode
);
3598 emit_insn (gen_call_gettlsoff (retval
, GEN_INT (0), picreg
));
3601 reg
= gen_reg_rtx (Pmode
);
3602 emit_insn (gen_rtx_SET (VOIDmode
, reg
,
3603 gen_rtx_PLUS (Pmode
,
3606 dest
= gen_tlsmoff (addr
, reg
);
3609 dest = gen_reg_rtx (Pmode);
3610 emit_insn (gen_tlsoff_hilo (dest, addr,
3611 GEN_INT (R_FRV_TLSMOFFHI)));
3612 dest = gen_rtx_PLUS (Pmode, dest, reg);
3616 case TLS_MODEL_LOCAL_EXEC
:
3617 dest
= gen_tlsmoff (addr
, gen_rtx_REG (Pmode
, 29));
3619 case TLS_MODEL_GLOBAL_DYNAMIC
:
3623 if (TARGET_INLINE_PLT
)
3624 retval
= gen_inlined_tls_plt (addr
);
3627 /* call #gettlsoff(x) */
3628 retval
= gen_reg_rtx (Pmode
);
3629 emit_insn (gen_call_gettlsoff (retval
, addr
, picreg
));
3631 dest
= gen_rtx_PLUS (Pmode
, retval
, tp
);
3642 frv_legitimize_address (rtx x
,
3643 rtx oldx ATTRIBUTE_UNUSED
,
3644 enum machine_mode mode ATTRIBUTE_UNUSED
)
3646 if (GET_CODE (x
) == SYMBOL_REF
)
3648 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
3650 return frv_legitimize_tls_address (x
, model
);
3656 /* Test whether a local function descriptor is canonical, i.e.,
3657 whether we can use FUNCDESC_GOTOFF to compute the address of the
3661 frv_local_funcdesc_p (rtx fnx
)
3664 enum symbol_visibility vis
;
3667 if (! SYMBOL_REF_LOCAL_P (fnx
))
3670 fn
= SYMBOL_REF_DECL (fnx
);
3675 vis
= DECL_VISIBILITY (fn
);
3677 if (vis
== VISIBILITY_PROTECTED
)
3678 /* Private function descriptors for protected functions are not
3679 canonical. Temporarily change the visibility to global. */
3680 vis
= VISIBILITY_DEFAULT
;
3681 else if (flag_shlib
)
3682 /* If we're already compiling for a shared library (that, unlike
3683 executables, can't assume that the existence of a definition
3684 implies local binding), we can skip the re-testing. */
3687 ret
= default_binds_local_p_1 (fn
, flag_pic
);
3689 DECL_VISIBILITY (fn
) = vis
;
3694 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3698 frv_gen_GPsym2reg (rtx dest
, rtx src
)
3700 tree gp
= get_identifier ("_gp");
3701 rtx gp_sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (gp
));
3703 return gen_symGOT2reg (dest
, gp_sym
, src
, GEN_INT (R_FRV_GOT12
));
3707 unspec_got_name (int i
)
3711 case R_FRV_GOT12
: return "got12";
3712 case R_FRV_GOTHI
: return "gothi";
3713 case R_FRV_GOTLO
: return "gotlo";
3714 case R_FRV_FUNCDESC
: return "funcdesc";
3715 case R_FRV_FUNCDESC_GOT12
: return "gotfuncdesc12";
3716 case R_FRV_FUNCDESC_GOTHI
: return "gotfuncdeschi";
3717 case R_FRV_FUNCDESC_GOTLO
: return "gotfuncdesclo";
3718 case R_FRV_FUNCDESC_VALUE
: return "funcdescvalue";
3719 case R_FRV_FUNCDESC_GOTOFF12
: return "gotofffuncdesc12";
3720 case R_FRV_FUNCDESC_GOTOFFHI
: return "gotofffuncdeschi";
3721 case R_FRV_FUNCDESC_GOTOFFLO
: return "gotofffuncdesclo";
3722 case R_FRV_GOTOFF12
: return "gotoff12";
3723 case R_FRV_GOTOFFHI
: return "gotoffhi";
3724 case R_FRV_GOTOFFLO
: return "gotofflo";
3725 case R_FRV_GPREL12
: return "gprel12";
3726 case R_FRV_GPRELHI
: return "gprelhi";
3727 case R_FRV_GPRELLO
: return "gprello";
3728 case R_FRV_GOTTLSOFF_HI
: return "gottlsoffhi";
3729 case R_FRV_GOTTLSOFF_LO
: return "gottlsofflo";
3730 case R_FRV_TLSMOFFHI
: return "tlsmoffhi";
3731 case R_FRV_TLSMOFFLO
: return "tlsmofflo";
3732 case R_FRV_TLSMOFF12
: return "tlsmoff12";
3733 case R_FRV_TLSDESCHI
: return "tlsdeschi";
3734 case R_FRV_TLSDESCLO
: return "tlsdesclo";
3735 case R_FRV_GOTTLSDESCHI
: return "gottlsdeschi";
3736 case R_FRV_GOTTLSDESCLO
: return "gottlsdesclo";
3737 default: gcc_unreachable ();
3741 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3742 is added inside the relocation operator. */
3745 frv_output_const_unspec (FILE *stream
, const struct frv_unspec
*unspec
)
3747 fprintf (stream
, "#%s(", unspec_got_name (unspec
->reloc
));
3748 output_addr_const (stream
, plus_constant (Pmode
, unspec
->symbol
,
3750 fputs (")", stream
);
3753 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3754 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3755 otherwise return ORIG_X. */
3758 frv_find_base_term (rtx x
)
3760 struct frv_unspec unspec
;
3762 if (frv_const_unspec_p (x
, &unspec
)
3763 && frv_small_data_reloc_p (unspec
.symbol
, unspec
.reloc
))
3764 return plus_constant (Pmode
, unspec
.symbol
, unspec
.offset
);
3769 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3770 the operand is used by a predicated instruction. */
3773 frv_legitimate_memory_operand (rtx op
, enum machine_mode mode
, int condexec_p
)
3775 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
3776 && GET_CODE (op
) == MEM
3777 && frv_legitimate_address_p_1 (mode
, XEXP (op
, 0),
3778 reload_completed
, condexec_p
, FALSE
));
3782 frv_expand_fdpic_call (rtx
*operands
, bool ret_value
, bool sibcall
)
3784 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
3785 rtx picreg
= get_hard_reg_initial_val (SImode
, FDPIC_REG
);
3791 rvrtx
= operands
[0];
3795 addr
= XEXP (operands
[0], 0);
3797 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3798 any calls that would involve a PLT, but can't tell, since we
3799 don't know whether an extern function is going to be provided by
3800 a separate translation unit or imported from a separate module.
3801 When compiling for shared libraries, if the function has default
3802 visibility, we assume it's overridable, so we inline the PLT, but
3803 for executables, we don't really have a way to make a good
3804 decision: a function is as likely to be imported from a shared
3805 library as it is to be defined in the executable itself. We
3806 assume executables will get global functions defined locally,
3807 whereas shared libraries will have them potentially overridden,
3808 so we only inline PLTs when compiling for shared libraries.
3810 In order to mark a function as local to a shared library, any
3811 non-default visibility attribute suffices. Unfortunately,
3812 there's no simple way to tag a function declaration as ``in a
3813 different module'', which we could then use to trigger PLT
3814 inlining on executables. There's -minline-plt, but it affects
3815 all external functions, so one would have to also mark function
3816 declarations available in the same module with non-default
3817 visibility, which is advantageous in itself. */
3818 if (GET_CODE (addr
) == SYMBOL_REF
3819 && ((!SYMBOL_REF_LOCAL_P (addr
) && TARGET_INLINE_PLT
)
3823 dest
= gen_reg_rtx (SImode
);
3825 x
= gen_symGOTOFF2reg_hilo (dest
, addr
, OUR_FDPIC_REG
,
3826 GEN_INT (R_FRV_FUNCDESC_GOTOFF12
));
3828 x
= gen_symGOTOFF2reg (dest
, addr
, OUR_FDPIC_REG
,
3829 GEN_INT (R_FRV_FUNCDESC_GOTOFF12
));
3831 crtl
->uses_pic_offset_table
= TRUE
;
3834 else if (GET_CODE (addr
) == SYMBOL_REF
)
3836 /* These are always either local, or handled through a local
3839 c
= gen_call_value_fdpicsi (rvrtx
, addr
, operands
[1],
3840 operands
[2], picreg
, lr
);
3842 c
= gen_call_fdpicsi (addr
, operands
[1], operands
[2], picreg
, lr
);
3846 else if (! ldd_address_operand (addr
, Pmode
))
3847 addr
= force_reg (Pmode
, addr
);
3849 picreg
= gen_reg_rtx (DImode
);
3850 emit_insn (gen_movdi_ldd (picreg
, addr
));
3852 if (sibcall
&& ret_value
)
3853 c
= gen_sibcall_value_fdpicdi (rvrtx
, picreg
, const0_rtx
);
3855 c
= gen_sibcall_fdpicdi (picreg
, const0_rtx
);
3857 c
= gen_call_value_fdpicdi (rvrtx
, picreg
, const0_rtx
, lr
);
3859 c
= gen_call_fdpicdi (picreg
, const0_rtx
, lr
);
3863 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3864 process these separately from any offsets, such that we add any
3865 offsets to the function descriptor (the actual pointer), not to the
3866 function address. */
3869 frv_function_symbol_referenced_p (rtx x
)
3875 if (GET_CODE (x
) == SYMBOL_REF
)
3876 return SYMBOL_REF_FUNCTION_P (x
);
3878 length
= GET_RTX_LENGTH (GET_CODE (x
));
3879 format
= GET_RTX_FORMAT (GET_CODE (x
));
3881 for (j
= 0; j
< length
; ++j
)
3886 if (frv_function_symbol_referenced_p (XEXP (x
, j
)))
3892 if (XVEC (x
, j
) != 0)
3895 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
3896 if (frv_function_symbol_referenced_p (XVECEXP (x
, j
, k
)))
3902 /* Nothing to do. */
3910 /* Return true if the memory operand is one that can be conditionally
3914 condexec_memory_operand (rtx op
, enum machine_mode mode
)
3916 enum machine_mode op_mode
= GET_MODE (op
);
3919 if (mode
!= VOIDmode
&& op_mode
!= mode
)
3934 if (GET_CODE (op
) != MEM
)
3937 addr
= XEXP (op
, 0);
3938 return frv_legitimate_address_p_1 (mode
, addr
, reload_completed
, TRUE
, FALSE
);
3941 /* Return true if the bare return instruction can be used outside of the
3942 epilog code. For frv, we only do it if there was no stack allocation. */
3945 direct_return_p (void)
3949 if (!reload_completed
)
3952 info
= frv_stack_info ();
3953 return (info
->total_size
== 0);
3958 frv_emit_move (enum machine_mode mode
, rtx dest
, rtx src
)
3960 if (GET_CODE (src
) == SYMBOL_REF
)
3962 enum tls_model model
= SYMBOL_REF_TLS_MODEL (src
);
3964 src
= frv_legitimize_tls_address (src
, model
);
3970 if (frv_emit_movsi (dest
, src
))
3979 if (!reload_in_progress
3980 && !reload_completed
3981 && !register_operand (dest
, mode
)
3982 && !reg_or_0_operand (src
, mode
))
3983 src
= copy_to_mode_reg (mode
, src
);
3990 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
3993 /* Emit code to handle a MOVSI, adding in the small data register or pic
3994 register if needed to load up addresses. Return TRUE if the appropriate
3995 instructions are emitted. */
3998 frv_emit_movsi (rtx dest
, rtx src
)
4000 int base_regno
= -1;
4003 struct frv_unspec old_unspec
;
4005 if (!reload_in_progress
4006 && !reload_completed
4007 && !register_operand (dest
, SImode
)
4008 && (!reg_or_0_operand (src
, SImode
)
4009 /* Virtual registers will almost always be replaced by an
4010 add instruction, so expose this to CSE by copying to
4011 an intermediate register. */
4012 || (GET_CODE (src
) == REG
4013 && IN_RANGE (REGNO (src
),
4014 FIRST_VIRTUAL_REGISTER
,
4015 LAST_VIRTUAL_POINTER_REGISTER
))))
4017 emit_insn (gen_rtx_SET (VOIDmode
, dest
, copy_to_mode_reg (SImode
, src
)));
4021 /* Explicitly add in the PIC or small data register if needed. */
4022 switch (GET_CODE (src
))
4031 /* Using GPREL12, we use a single GOT entry for all symbols
4032 in read-only sections, but trade sequences such as:
4034 sethi #gothi(label), gr#
4035 setlo #gotlo(label), gr#
4040 ld @(gr15,#got12(_gp)), gr#
4041 sethi #gprelhi(label), gr##
4042 setlo #gprello(label), gr##
4045 We may often be able to share gr# for multiple
4046 computations of GPREL addresses, and we may often fold
4047 the final add into the pair of registers of a load or
4048 store instruction, so it's often profitable. Even when
4049 optimizing for size, we're trading a GOT entry for an
4050 additional instruction, which trades GOT space
4051 (read-write) for code size (read-only, shareable), as
4052 long as the symbol is not used in more than two different
4055 With -fpie/-fpic, we'd be trading a single load for a
4056 sequence of 4 instructions, because the offset of the
4057 label can't be assumed to be addressable with 12 bits, so
4058 we don't do this. */
4059 if (TARGET_GPREL_RO
)
4060 unspec
= R_FRV_GPREL12
;
4062 unspec
= R_FRV_GOT12
;
4065 base_regno
= PIC_REGNO
;
4070 if (frv_const_unspec_p (src
, &old_unspec
))
4073 if (TARGET_FDPIC
&& frv_function_symbol_referenced_p (XEXP (src
, 0)))
4076 src
= force_reg (GET_MODE (XEXP (src
, 0)), XEXP (src
, 0));
4077 emit_move_insn (dest
, src
);
4082 sym
= XEXP (sym
, 0);
4083 if (GET_CODE (sym
) == PLUS
4084 && GET_CODE (XEXP (sym
, 0)) == SYMBOL_REF
4085 && GET_CODE (XEXP (sym
, 1)) == CONST_INT
)
4086 sym
= XEXP (sym
, 0);
4087 if (GET_CODE (sym
) == SYMBOL_REF
)
4089 else if (GET_CODE (sym
) == LABEL_REF
)
4092 goto handle_whatever
;
4100 enum tls_model model
= SYMBOL_REF_TLS_MODEL (sym
);
4104 src
= frv_legitimize_tls_address (src
, model
);
4105 emit_move_insn (dest
, src
);
4109 if (SYMBOL_REF_FUNCTION_P (sym
))
4111 if (frv_local_funcdesc_p (sym
))
4112 unspec
= R_FRV_FUNCDESC_GOTOFF12
;
4114 unspec
= R_FRV_FUNCDESC_GOT12
;
4118 if (CONSTANT_POOL_ADDRESS_P (sym
))
4119 switch (GET_CODE (get_pool_constant (sym
)))
4126 unspec
= R_FRV_GOTOFF12
;
4131 if (TARGET_GPREL_RO
)
4132 unspec
= R_FRV_GPREL12
;
4134 unspec
= R_FRV_GOT12
;
4137 else if (SYMBOL_REF_LOCAL_P (sym
)
4138 && !SYMBOL_REF_EXTERNAL_P (sym
)
4139 && SYMBOL_REF_DECL (sym
)
4140 && (!DECL_P (SYMBOL_REF_DECL (sym
))
4141 || !DECL_COMMON (SYMBOL_REF_DECL (sym
))))
4143 tree decl
= SYMBOL_REF_DECL (sym
);
4144 tree init
= TREE_CODE (decl
) == VAR_DECL
4145 ? DECL_INITIAL (decl
)
4146 : TREE_CODE (decl
) == CONSTRUCTOR
4149 bool named_section
, readonly
;
4151 if (init
&& init
!= error_mark_node
)
4152 reloc
= compute_reloc_for_constant (init
);
4154 named_section
= TREE_CODE (decl
) == VAR_DECL
4155 && lookup_attribute ("section", DECL_ATTRIBUTES (decl
));
4156 readonly
= decl_readonly_section (decl
, reloc
);
4159 unspec
= R_FRV_GOT12
;
4161 unspec
= R_FRV_GOTOFF12
;
4162 else if (readonly
&& TARGET_GPREL_RO
)
4163 unspec
= R_FRV_GPREL12
;
4165 unspec
= R_FRV_GOT12
;
4168 unspec
= R_FRV_GOT12
;
4172 else if (SYMBOL_REF_SMALL_P (sym
))
4173 base_regno
= SDA_BASE_REG
;
4176 base_regno
= PIC_REGNO
;
4181 if (base_regno
>= 0)
4183 if (GET_CODE (sym
) == SYMBOL_REF
&& SYMBOL_REF_SMALL_P (sym
))
4184 emit_insn (gen_symGOTOFF2reg (dest
, src
,
4185 gen_rtx_REG (Pmode
, base_regno
),
4186 GEN_INT (R_FRV_GPREL12
)));
4188 emit_insn (gen_symGOTOFF2reg_hilo (dest
, src
,
4189 gen_rtx_REG (Pmode
, base_regno
),
4190 GEN_INT (R_FRV_GPREL12
)));
4191 if (base_regno
== PIC_REGNO
)
4192 crtl
->uses_pic_offset_table
= TRUE
;
4200 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4201 new uses of it once reload has begun. */
4202 gcc_assert (!reload_in_progress
&& !reload_completed
);
4206 case R_FRV_GOTOFF12
:
4207 if (!frv_small_data_reloc_p (sym
, unspec
))
4208 x
= gen_symGOTOFF2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4211 x
= gen_symGOTOFF2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4214 if (!frv_small_data_reloc_p (sym
, unspec
))
4215 x
= gen_symGPREL2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4218 x
= gen_symGPREL2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4220 case R_FRV_FUNCDESC_GOTOFF12
:
4222 x
= gen_symGOTOFF2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4225 x
= gen_symGOTOFF2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4229 x
= gen_symGOT2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4232 x
= gen_symGOT2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4236 crtl
->uses_pic_offset_table
= TRUE
;
4245 /* Return a string to output a single word move. */
4248 output_move_single (rtx operands
[], rtx insn
)
4250 rtx dest
= operands
[0];
4251 rtx src
= operands
[1];
4253 if (GET_CODE (dest
) == REG
)
4255 int dest_regno
= REGNO (dest
);
4256 enum machine_mode mode
= GET_MODE (dest
);
4258 if (GPR_P (dest_regno
))
4260 if (GET_CODE (src
) == REG
)
4262 /* gpr <- some sort of register */
4263 int src_regno
= REGNO (src
);
4265 if (GPR_P (src_regno
))
4266 return "mov %1, %0";
4268 else if (FPR_P (src_regno
))
4269 return "movfg %1, %0";
4271 else if (SPR_P (src_regno
))
4272 return "movsg %1, %0";
4275 else if (GET_CODE (src
) == MEM
)
4284 return "ldsb%I1%U1 %M1,%0";
4287 return "ldsh%I1%U1 %M1,%0";
4291 return "ld%I1%U1 %M1, %0";
4295 else if (GET_CODE (src
) == CONST_INT
4296 || GET_CODE (src
) == CONST_DOUBLE
)
4298 /* gpr <- integer/floating constant */
4299 HOST_WIDE_INT value
;
4301 if (GET_CODE (src
) == CONST_INT
)
4302 value
= INTVAL (src
);
4304 else if (mode
== SFmode
)
4309 REAL_VALUE_FROM_CONST_DOUBLE (rv
, src
);
4310 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
4315 value
= CONST_DOUBLE_LOW (src
);
4317 if (IN_RANGE (value
, -32768, 32767))
4318 return "setlos %1, %0";
4323 else if (GET_CODE (src
) == SYMBOL_REF
4324 || GET_CODE (src
) == LABEL_REF
4325 || GET_CODE (src
) == CONST
)
4331 else if (FPR_P (dest_regno
))
4333 if (GET_CODE (src
) == REG
)
4335 /* fpr <- some sort of register */
4336 int src_regno
= REGNO (src
);
4338 if (GPR_P (src_regno
))
4339 return "movgf %1, %0";
4341 else if (FPR_P (src_regno
))
4343 if (TARGET_HARD_FLOAT
)
4344 return "fmovs %1, %0";
4346 return "mor %1, %1, %0";
4350 else if (GET_CODE (src
) == MEM
)
4359 return "ldbf%I1%U1 %M1,%0";
4362 return "ldhf%I1%U1 %M1,%0";
4366 return "ldf%I1%U1 %M1, %0";
4370 else if (ZERO_P (src
))
4371 return "movgf %., %0";
4374 else if (SPR_P (dest_regno
))
4376 if (GET_CODE (src
) == REG
)
4378 /* spr <- some sort of register */
4379 int src_regno
= REGNO (src
);
4381 if (GPR_P (src_regno
))
4382 return "movgs %1, %0";
4384 else if (ZERO_P (src
))
4385 return "movgs %., %0";
4389 else if (GET_CODE (dest
) == MEM
)
4391 if (GET_CODE (src
) == REG
)
4393 int src_regno
= REGNO (src
);
4394 enum machine_mode mode
= GET_MODE (dest
);
4396 if (GPR_P (src_regno
))
4404 return "stb%I0%U0 %1, %M0";
4407 return "sth%I0%U0 %1, %M0";
4411 return "st%I0%U0 %1, %M0";
4415 else if (FPR_P (src_regno
))
4423 return "stbf%I0%U0 %1, %M0";
4426 return "sthf%I0%U0 %1, %M0";
4430 return "stf%I0%U0 %1, %M0";
4435 else if (ZERO_P (src
))
4437 switch (GET_MODE (dest
))
4443 return "stb%I0%U0 %., %M0";
4446 return "sth%I0%U0 %., %M0";
4450 return "st%I0%U0 %., %M0";
4455 fatal_insn ("bad output_move_single operand", insn
);
4460 /* Return a string to output a double word move. */
4463 output_move_double (rtx operands
[], rtx insn
)
4465 rtx dest
= operands
[0];
4466 rtx src
= operands
[1];
4467 enum machine_mode mode
= GET_MODE (dest
);
4469 if (GET_CODE (dest
) == REG
)
4471 int dest_regno
= REGNO (dest
);
4473 if (GPR_P (dest_regno
))
4475 if (GET_CODE (src
) == REG
)
4477 /* gpr <- some sort of register */
4478 int src_regno
= REGNO (src
);
4480 if (GPR_P (src_regno
))
4483 else if (FPR_P (src_regno
))
4485 if (((dest_regno
- GPR_FIRST
) & 1) == 0
4486 && ((src_regno
- FPR_FIRST
) & 1) == 0)
4487 return "movfgd %1, %0";
4493 else if (GET_CODE (src
) == MEM
)
4496 if (dbl_memory_one_insn_operand (src
, mode
))
4497 return "ldd%I1%U1 %M1, %0";
4502 else if (GET_CODE (src
) == CONST_INT
4503 || GET_CODE (src
) == CONST_DOUBLE
)
4507 else if (FPR_P (dest_regno
))
4509 if (GET_CODE (src
) == REG
)
4511 /* fpr <- some sort of register */
4512 int src_regno
= REGNO (src
);
4514 if (GPR_P (src_regno
))
4516 if (((dest_regno
- FPR_FIRST
) & 1) == 0
4517 && ((src_regno
- GPR_FIRST
) & 1) == 0)
4518 return "movgfd %1, %0";
4523 else if (FPR_P (src_regno
))
4526 && ((dest_regno
- FPR_FIRST
) & 1) == 0
4527 && ((src_regno
- FPR_FIRST
) & 1) == 0)
4528 return "fmovd %1, %0";
4534 else if (GET_CODE (src
) == MEM
)
4537 if (dbl_memory_one_insn_operand (src
, mode
))
4538 return "lddf%I1%U1 %M1, %0";
4543 else if (ZERO_P (src
))
4548 else if (GET_CODE (dest
) == MEM
)
4550 if (GET_CODE (src
) == REG
)
4552 int src_regno
= REGNO (src
);
4554 if (GPR_P (src_regno
))
4556 if (((src_regno
- GPR_FIRST
) & 1) == 0
4557 && dbl_memory_one_insn_operand (dest
, mode
))
4558 return "std%I0%U0 %1, %M0";
4563 if (FPR_P (src_regno
))
4565 if (((src_regno
- FPR_FIRST
) & 1) == 0
4566 && dbl_memory_one_insn_operand (dest
, mode
))
4567 return "stdf%I0%U0 %1, %M0";
4573 else if (ZERO_P (src
))
4575 if (dbl_memory_one_insn_operand (dest
, mode
))
4576 return "std%I0%U0 %., %M0";
4582 fatal_insn ("bad output_move_double operand", insn
);
4587 /* Return a string to output a single word conditional move.
4588 Operand0 -- EQ/NE of ccr register and 0
4589 Operand1 -- CCR register
4590 Operand2 -- destination
4591 Operand3 -- source */
4594 output_condmove_single (rtx operands
[], rtx insn
)
4596 rtx dest
= operands
[2];
4597 rtx src
= operands
[3];
4599 if (GET_CODE (dest
) == REG
)
4601 int dest_regno
= REGNO (dest
);
4602 enum machine_mode mode
= GET_MODE (dest
);
4604 if (GPR_P (dest_regno
))
4606 if (GET_CODE (src
) == REG
)
4608 /* gpr <- some sort of register */
4609 int src_regno
= REGNO (src
);
4611 if (GPR_P (src_regno
))
4612 return "cmov %z3, %2, %1, %e0";
4614 else if (FPR_P (src_regno
))
4615 return "cmovfg %3, %2, %1, %e0";
4618 else if (GET_CODE (src
) == MEM
)
4627 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4630 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4634 return "cld%I3%U3 %M3, %2, %1, %e0";
4638 else if (ZERO_P (src
))
4639 return "cmov %., %2, %1, %e0";
4642 else if (FPR_P (dest_regno
))
4644 if (GET_CODE (src
) == REG
)
4646 /* fpr <- some sort of register */
4647 int src_regno
= REGNO (src
);
4649 if (GPR_P (src_regno
))
4650 return "cmovgf %3, %2, %1, %e0";
4652 else if (FPR_P (src_regno
))
4654 if (TARGET_HARD_FLOAT
)
4655 return "cfmovs %3,%2,%1,%e0";
4657 return "cmor %3, %3, %2, %1, %e0";
4661 else if (GET_CODE (src
) == MEM
)
4664 if (mode
== SImode
|| mode
== SFmode
)
4665 return "cldf%I3%U3 %M3, %2, %1, %e0";
4668 else if (ZERO_P (src
))
4669 return "cmovgf %., %2, %1, %e0";
4673 else if (GET_CODE (dest
) == MEM
)
4675 if (GET_CODE (src
) == REG
)
4677 int src_regno
= REGNO (src
);
4678 enum machine_mode mode
= GET_MODE (dest
);
4680 if (GPR_P (src_regno
))
4688 return "cstb%I2%U2 %3, %M2, %1, %e0";
4691 return "csth%I2%U2 %3, %M2, %1, %e0";
4695 return "cst%I2%U2 %3, %M2, %1, %e0";
4699 else if (FPR_P (src_regno
) && (mode
== SImode
|| mode
== SFmode
))
4700 return "cstf%I2%U2 %3, %M2, %1, %e0";
4703 else if (ZERO_P (src
))
4705 enum machine_mode mode
= GET_MODE (dest
);
4712 return "cstb%I2%U2 %., %M2, %1, %e0";
4715 return "csth%I2%U2 %., %M2, %1, %e0";
4719 return "cst%I2%U2 %., %M2, %1, %e0";
4724 fatal_insn ("bad output_condmove_single operand", insn
);
4729 /* Emit the appropriate code to do a comparison, returning the register the
4730 comparison was done it. */
4733 frv_emit_comparison (enum rtx_code test
, rtx op0
, rtx op1
)
4735 enum machine_mode cc_mode
;
4738 /* Floating point doesn't have comparison against a constant. */
4739 if (GET_MODE (op0
) == CC_FPmode
&& GET_CODE (op1
) != REG
)
4740 op1
= force_reg (GET_MODE (op0
), op1
);
4742 /* Possibly disable using anything but a fixed register in order to work
4743 around cse moving comparisons past function calls. */
4744 cc_mode
= SELECT_CC_MODE (test
, op0
, op1
);
4745 cc_reg
= ((TARGET_ALLOC_CC
)
4746 ? gen_reg_rtx (cc_mode
)
4747 : gen_rtx_REG (cc_mode
,
4748 (cc_mode
== CC_FPmode
) ? FCC_FIRST
: ICC_FIRST
));
4750 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
4751 gen_rtx_COMPARE (cc_mode
, op0
, op1
)));
4757 /* Emit code for a conditional branch.
4758 XXX: I originally wanted to add a clobber of a CCR register to use in
4759 conditional execution, but that confuses the rest of the compiler. */
4762 frv_emit_cond_branch (rtx operands
[])
4767 enum rtx_code test
= GET_CODE (operands
[0]);
4768 rtx cc_reg
= frv_emit_comparison (test
, operands
[1], operands
[2]);
4769 enum machine_mode cc_mode
= GET_MODE (cc_reg
);
4771 /* Branches generate:
4773 (if_then_else (<test>, <cc_reg>, (const_int 0))
4774 (label_ref <branch_label>)
4776 label_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
4777 test_rtx
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
4778 if_else
= gen_rtx_IF_THEN_ELSE (cc_mode
, test_rtx
, label_ref
, pc_rtx
);
4779 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, if_else
));
4784 /* Emit code to set a gpr to 1/0 based on a comparison. */
4787 frv_emit_scc (rtx operands
[])
4793 enum rtx_code test
= GET_CODE (operands
[1]);
4794 rtx cc_reg
= frv_emit_comparison (test
, operands
[2], operands
[3]);
4796 /* SCC instructions generate:
4797 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4798 (clobber (<ccr_reg>))]) */
4799 test_rtx
= gen_rtx_fmt_ee (test
, SImode
, cc_reg
, const0_rtx
);
4800 set
= gen_rtx_SET (VOIDmode
, operands
[0], test_rtx
);
4802 cr_reg
= ((TARGET_ALLOC_CC
)
4803 ? gen_reg_rtx (CC_CCRmode
)
4804 : gen_rtx_REG (CC_CCRmode
,
4805 ((GET_MODE (cc_reg
) == CC_FPmode
)
4809 clobber
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
4810 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
4815 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4816 the separate insns. */
4819 frv_split_scc (rtx dest
, rtx test
, rtx cc_reg
, rtx cr_reg
, HOST_WIDE_INT value
)
4825 /* Set the appropriate CCR bit. */
4826 emit_insn (gen_rtx_SET (VOIDmode
,
4828 gen_rtx_fmt_ee (GET_CODE (test
),
4833 /* Move the value into the destination. */
4834 emit_move_insn (dest
, GEN_INT (value
));
4836 /* Move 0 into the destination if the test failed */
4837 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4838 gen_rtx_EQ (GET_MODE (cr_reg
),
4841 gen_rtx_SET (VOIDmode
, dest
, const0_rtx
)));
4843 /* Finish up, return sequence. */
4850 /* Emit the code for a conditional move, return TRUE if we could do the
4854 frv_emit_cond_move (rtx dest
, rtx test_rtx
, rtx src1
, rtx src2
)
4861 enum rtx_code test
= GET_CODE (test_rtx
);
4862 rtx cc_reg
= frv_emit_comparison (test
,
4863 XEXP (test_rtx
, 0), XEXP (test_rtx
, 1));
4864 enum machine_mode cc_mode
= GET_MODE (cc_reg
);
4866 /* Conditional move instructions generate:
4867 (parallel [(set <target>
4868 (if_then_else (<test> <cc_reg> (const_int 0))
4871 (clobber (<ccr_reg>))]) */
4873 /* Handle various cases of conditional move involving two constants. */
4874 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
4876 HOST_WIDE_INT value1
= INTVAL (src1
);
4877 HOST_WIDE_INT value2
= INTVAL (src2
);
4879 /* Having 0 as one of the constants can be done by loading the other
4880 constant, and optionally moving in gr0. */
4881 if (value1
== 0 || value2
== 0)
4884 /* If the first value is within an addi range and also the difference
4885 between the two fits in an addi's range, load up the difference, then
4886 conditionally move in 0, and then unconditionally add the first
4888 else if (IN_RANGE (value1
, -2048, 2047)
4889 && IN_RANGE (value2
- value1
, -2048, 2047))
4892 /* If neither condition holds, just force the constant into a
4896 src1
= force_reg (GET_MODE (dest
), src1
);
4897 src2
= force_reg (GET_MODE (dest
), src2
);
4901 /* If one value is a register, insure the other value is either 0 or a
4905 if (GET_CODE (src1
) == CONST_INT
&& INTVAL (src1
) != 0)
4906 src1
= force_reg (GET_MODE (dest
), src1
);
4908 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
4909 src2
= force_reg (GET_MODE (dest
), src2
);
4912 test2
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
4913 if_rtx
= gen_rtx_IF_THEN_ELSE (GET_MODE (dest
), test2
, src1
, src2
);
4915 set
= gen_rtx_SET (VOIDmode
, dest
, if_rtx
);
4917 cr_reg
= ((TARGET_ALLOC_CC
)
4918 ? gen_reg_rtx (CC_CCRmode
)
4919 : gen_rtx_REG (CC_CCRmode
,
4920 (cc_mode
== CC_FPmode
) ? FCR_FIRST
: ICR_FIRST
));
4922 clobber_cc
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
4923 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber_cc
)));
4928 /* Split a conditional move into constituent parts, returning a SEQUENCE
4929 containing all of the insns. */
4932 frv_split_cond_move (rtx operands
[])
4934 rtx dest
= operands
[0];
4935 rtx test
= operands
[1];
4936 rtx cc_reg
= operands
[2];
4937 rtx src1
= operands
[3];
4938 rtx src2
= operands
[4];
4939 rtx cr_reg
= operands
[5];
4941 enum machine_mode cr_mode
= GET_MODE (cr_reg
);
4945 /* Set the appropriate CCR bit. */
4946 emit_insn (gen_rtx_SET (VOIDmode
,
4948 gen_rtx_fmt_ee (GET_CODE (test
),
4953 /* Handle various cases of conditional move involving two constants. */
4954 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
4956 HOST_WIDE_INT value1
= INTVAL (src1
);
4957 HOST_WIDE_INT value2
= INTVAL (src2
);
4959 /* Having 0 as one of the constants can be done by loading the other
4960 constant, and optionally moving in gr0. */
4963 emit_move_insn (dest
, src2
);
4964 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4965 gen_rtx_NE (cr_mode
, cr_reg
,
4967 gen_rtx_SET (VOIDmode
, dest
, src1
)));
4970 else if (value2
== 0)
4972 emit_move_insn (dest
, src1
);
4973 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4974 gen_rtx_EQ (cr_mode
, cr_reg
,
4976 gen_rtx_SET (VOIDmode
, dest
, src2
)));
4979 /* If the first value is within an addi range and also the difference
4980 between the two fits in an addi's range, load up the difference, then
4981 conditionally move in 0, and then unconditionally add the first
4983 else if (IN_RANGE (value1
, -2048, 2047)
4984 && IN_RANGE (value2
- value1
, -2048, 2047))
4986 rtx dest_si
= ((GET_MODE (dest
) == SImode
)
4988 : gen_rtx_SUBREG (SImode
, dest
, 0));
4990 emit_move_insn (dest_si
, GEN_INT (value2
- value1
));
4991 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4992 gen_rtx_NE (cr_mode
, cr_reg
,
4994 gen_rtx_SET (VOIDmode
, dest_si
,
4996 emit_insn (gen_addsi3 (dest_si
, dest_si
, src1
));
5004 /* Emit the conditional move for the test being true if needed. */
5005 if (! rtx_equal_p (dest
, src1
))
5006 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5007 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5008 gen_rtx_SET (VOIDmode
, dest
, src1
)));
5010 /* Emit the conditional move for the test being false if needed. */
5011 if (! rtx_equal_p (dest
, src2
))
5012 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5013 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
5014 gen_rtx_SET (VOIDmode
, dest
, src2
)));
5017 /* Finish up, return sequence. */
5024 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5025 memory location that is not known to be dword-aligned. */
5027 frv_split_double_load (rtx dest
, rtx source
)
5029 int regno
= REGNO (dest
);
5030 rtx dest1
= gen_highpart (SImode
, dest
);
5031 rtx dest2
= gen_lowpart (SImode
, dest
);
5032 rtx address
= XEXP (source
, 0);
5034 /* If the address is pre-modified, load the lower-numbered register
5035 first, then load the other register using an integer offset from
5036 the modified base register. This order should always be safe,
5037 since the pre-modification cannot affect the same registers as the
5040 The situation for other loads is more complicated. Loading one
5041 of the registers could affect the value of ADDRESS, so we must
5042 be careful which order we do them in. */
5043 if (GET_CODE (address
) == PRE_MODIFY
5044 || ! refers_to_regno_p (regno
, regno
+ 1, address
, NULL
))
5046 /* It is safe to load the lower-numbered register first. */
5047 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
5048 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
5052 /* ADDRESS is not pre-modified and the address depends on the
5053 lower-numbered register. Load the higher-numbered register
5055 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
5056 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
5060 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5061 and SOURCE is either a double register or the constant zero. */
5063 frv_split_double_store (rtx dest
, rtx source
)
5065 rtx dest1
= change_address (dest
, SImode
, NULL
);
5066 rtx dest2
= frv_index_memory (dest
, SImode
, 1);
5067 if (ZERO_P (source
))
5069 emit_move_insn (dest1
, CONST0_RTX (SImode
));
5070 emit_move_insn (dest2
, CONST0_RTX (SImode
));
5074 emit_move_insn (dest1
, gen_highpart (SImode
, source
));
5075 emit_move_insn (dest2
, gen_lowpart (SImode
, source
));
5080 /* Split a min/max operation returning a SEQUENCE containing all of the
5084 frv_split_minmax (rtx operands
[])
5086 rtx dest
= operands
[0];
5087 rtx minmax
= operands
[1];
5088 rtx src1
= operands
[2];
5089 rtx src2
= operands
[3];
5090 rtx cc_reg
= operands
[4];
5091 rtx cr_reg
= operands
[5];
5093 enum rtx_code test_code
;
5094 enum machine_mode cr_mode
= GET_MODE (cr_reg
);
5098 /* Figure out which test to use. */
5099 switch (GET_CODE (minmax
))
5104 case SMIN
: test_code
= LT
; break;
5105 case SMAX
: test_code
= GT
; break;
5106 case UMIN
: test_code
= LTU
; break;
5107 case UMAX
: test_code
= GTU
; break;
5110 /* Issue the compare instruction. */
5111 emit_insn (gen_rtx_SET (VOIDmode
,
5113 gen_rtx_COMPARE (GET_MODE (cc_reg
),
5116 /* Set the appropriate CCR bit. */
5117 emit_insn (gen_rtx_SET (VOIDmode
,
5119 gen_rtx_fmt_ee (test_code
,
5124 /* If are taking the min/max of a nonzero constant, load that first, and
5125 then do a conditional move of the other value. */
5126 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
5128 gcc_assert (!rtx_equal_p (dest
, src1
));
5130 emit_move_insn (dest
, src2
);
5131 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5132 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5133 gen_rtx_SET (VOIDmode
, dest
, src1
)));
5136 /* Otherwise, do each half of the move. */
5139 /* Emit the conditional move for the test being true if needed. */
5140 if (! rtx_equal_p (dest
, src1
))
5141 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5142 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5143 gen_rtx_SET (VOIDmode
, dest
, src1
)));
5145 /* Emit the conditional move for the test being false if needed. */
5146 if (! rtx_equal_p (dest
, src2
))
5147 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5148 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
5149 gen_rtx_SET (VOIDmode
, dest
, src2
)));
5152 /* Finish up, return sequence. */
5159 /* Split an integer abs operation returning a SEQUENCE containing all of the
5163 frv_split_abs (rtx operands
[])
5165 rtx dest
= operands
[0];
5166 rtx src
= operands
[1];
5167 rtx cc_reg
= operands
[2];
5168 rtx cr_reg
= operands
[3];
5173 /* Issue the compare < 0 instruction. */
5174 emit_insn (gen_rtx_SET (VOIDmode
,
5176 gen_rtx_COMPARE (CCmode
, src
, const0_rtx
)));
5178 /* Set the appropriate CCR bit. */
5179 emit_insn (gen_rtx_SET (VOIDmode
,
5181 gen_rtx_fmt_ee (LT
, CC_CCRmode
, cc_reg
, const0_rtx
)));
5183 /* Emit the conditional negate if the value is negative. */
5184 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5185 gen_rtx_NE (CC_CCRmode
, cr_reg
, const0_rtx
),
5186 gen_negsi2 (dest
, src
)));
5188 /* Emit the conditional move for the test being false if needed. */
5189 if (! rtx_equal_p (dest
, src
))
5190 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5191 gen_rtx_EQ (CC_CCRmode
, cr_reg
, const0_rtx
),
5192 gen_rtx_SET (VOIDmode
, dest
, src
)));
5194 /* Finish up, return sequence. */
5201 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5202 register used in an insn. */
5205 frv_clear_registers_used (rtx
*ptr
, void *data
)
5207 if (GET_CODE (*ptr
) == REG
)
5209 int regno
= REGNO (*ptr
);
5210 HARD_REG_SET
*p_regs
= (HARD_REG_SET
*)data
;
5212 if (regno
< FIRST_PSEUDO_REGISTER
)
5214 int reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (*ptr
));
5216 while (regno
< reg_max
)
5218 CLEAR_HARD_REG_BIT (*p_regs
, regno
);
5228 /* Initialize machine-specific if-conversion data.
5229 On the FR-V, we don't have any extra fields per se, but it is useful hook to
5230 initialize the static storage. */
5232 frv_ifcvt_machdep_init (void *ce_info ATTRIBUTE_UNUSED
)
5234 frv_ifcvt
.added_insns_list
= NULL_RTX
;
5235 frv_ifcvt
.cur_scratch_regs
= 0;
5236 frv_ifcvt
.num_nested_cond_exec
= 0;
5237 frv_ifcvt
.cr_reg
= NULL_RTX
;
5238 frv_ifcvt
.nested_cc_reg
= NULL_RTX
;
5239 frv_ifcvt
.extra_int_cr
= NULL_RTX
;
5240 frv_ifcvt
.extra_fp_cr
= NULL_RTX
;
5241 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
5245 /* Internal function to add a potential insn to the list of insns to be inserted
5246 if the conditional execution conversion is successful. */
5249 frv_ifcvt_add_insn (rtx pattern
, rtx insn
, int before_p
)
5251 rtx link
= alloc_EXPR_LIST (VOIDmode
, pattern
, insn
);
5253 link
->jump
= before_p
; /* Mark to add this before or after insn. */
5254 frv_ifcvt
.added_insns_list
= alloc_EXPR_LIST (VOIDmode
, link
,
5255 frv_ifcvt
.added_insns_list
);
5257 if (TARGET_DEBUG_COND_EXEC
)
5260 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5261 (before_p
) ? "before" : "after",
5262 (int)INSN_UID (insn
));
5264 debug_rtx (pattern
);
5269 /* A C expression to modify the code described by the conditional if
5270 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5271 FALSE_EXPR for converting if-then and if-then-else code to conditional
5272 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5273 tests cannot be converted. */
5276 frv_ifcvt_modify_tests (ce_if_block_t
*ce_info
, rtx
*p_true
, rtx
*p_false
)
5278 basic_block test_bb
= ce_info
->test_bb
; /* test basic block */
5279 basic_block then_bb
= ce_info
->then_bb
; /* THEN */
5280 basic_block else_bb
= ce_info
->else_bb
; /* ELSE or NULL */
5281 basic_block join_bb
= ce_info
->join_bb
; /* join block or NULL */
5282 rtx true_expr
= *p_true
;
5286 enum machine_mode mode
= GET_MODE (true_expr
);
5290 frv_tmp_reg_t
*tmp_reg
= &frv_ifcvt
.tmp_reg
;
5292 rtx sub_cond_exec_reg
;
5294 enum rtx_code code_true
;
5295 enum rtx_code code_false
;
5296 enum reg_class cc_class
;
5297 enum reg_class cr_class
;
5300 reg_set_iterator rsi
;
5302 /* Make sure we are only dealing with hard registers. Also honor the
5303 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5305 if (!reload_completed
|| !TARGET_COND_EXEC
5306 || (!TARGET_NESTED_CE
&& ce_info
->pass
> 1))
5309 /* Figure out which registers we can allocate for our own purposes. Only
5310 consider registers that are not preserved across function calls and are
5311 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5312 if we did not need to use them in reloading other registers. */
5313 memset (&tmp_reg
->regs
, 0, sizeof (tmp_reg
->regs
));
5314 COPY_HARD_REG_SET (tmp_reg
->regs
, call_used_reg_set
);
5315 AND_COMPL_HARD_REG_SET (tmp_reg
->regs
, fixed_reg_set
);
5316 SET_HARD_REG_BIT (tmp_reg
->regs
, ICC_TEMP
);
5317 SET_HARD_REG_BIT (tmp_reg
->regs
, ICR_TEMP
);
5319 /* If this is a nested IF, we need to discover whether the CC registers that
5320 are set/used inside of the block are used anywhere else. If not, we can
5321 change them to be the CC register that is paired with the CR register that
5322 controls the outermost IF block. */
5323 if (ce_info
->pass
> 1)
5325 CLEAR_HARD_REG_SET (frv_ifcvt
.nested_cc_ok_rewrite
);
5326 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5327 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5329 if (REGNO_REG_SET_P (df_get_live_in (then_bb
), j
))
5333 && REGNO_REG_SET_P (df_get_live_in (else_bb
), j
))
5337 && REGNO_REG_SET_P (df_get_live_in (join_bb
), j
))
5340 SET_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
);
5344 for (j
= 0; j
< frv_ifcvt
.cur_scratch_regs
; j
++)
5345 frv_ifcvt
.scratch_regs
[j
] = NULL_RTX
;
5347 frv_ifcvt
.added_insns_list
= NULL_RTX
;
5348 frv_ifcvt
.cur_scratch_regs
= 0;
5350 bb
= (basic_block
*) alloca ((2 + ce_info
->num_multiple_test_blocks
)
5351 * sizeof (basic_block
));
5357 /* Remove anything live at the beginning of the join block from being
5358 available for allocation. */
5359 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb
), 0, regno
, rsi
)
5361 if (regno
< FIRST_PSEUDO_REGISTER
)
5362 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
5366 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5368 if (ce_info
->num_multiple_test_blocks
)
5370 basic_block multiple_test_bb
= ce_info
->last_test_bb
;
5372 while (multiple_test_bb
!= test_bb
)
5374 bb
[num_bb
++] = multiple_test_bb
;
5375 multiple_test_bb
= EDGE_PRED (multiple_test_bb
, 0)->src
;
5379 /* Add in the THEN and ELSE blocks to be scanned. */
5380 bb
[num_bb
++] = then_bb
;
5382 bb
[num_bb
++] = else_bb
;
5384 sub_cond_exec_reg
= NULL_RTX
;
5385 frv_ifcvt
.num_nested_cond_exec
= 0;
5387 /* Scan all of the blocks for registers that must not be allocated. */
5388 for (j
= 0; j
< num_bb
; j
++)
5390 rtx last_insn
= BB_END (bb
[j
]);
5391 rtx insn
= BB_HEAD (bb
[j
]);
5395 fprintf (dump_file
, "Scanning %s block %d, start %d, end %d\n",
5396 (bb
[j
] == else_bb
) ? "else" : ((bb
[j
] == then_bb
) ? "then" : "test"),
5398 (int) INSN_UID (BB_HEAD (bb
[j
])),
5399 (int) INSN_UID (BB_END (bb
[j
])));
5401 /* Anything live at the beginning of the block is obviously unavailable
5403 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb
[j
]), 0, regno
, rsi
)
5405 if (regno
< FIRST_PSEUDO_REGISTER
)
5406 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
5409 /* Loop through the insns in the block. */
5412 /* Mark any new registers that are created as being unavailable for
5413 allocation. Also see if the CC register used in nested IFs can be
5419 int skip_nested_if
= FALSE
;
5421 for_each_rtx (&PATTERN (insn
), frv_clear_registers_used
,
5422 (void *)&tmp_reg
->regs
);
5424 pattern
= PATTERN (insn
);
5425 if (GET_CODE (pattern
) == COND_EXEC
)
5427 rtx reg
= XEXP (COND_EXEC_TEST (pattern
), 0);
5429 if (reg
!= sub_cond_exec_reg
)
5431 sub_cond_exec_reg
= reg
;
5432 frv_ifcvt
.num_nested_cond_exec
++;
5436 set
= single_set_pattern (pattern
);
5439 rtx dest
= SET_DEST (set
);
5440 rtx src
= SET_SRC (set
);
5442 if (GET_CODE (dest
) == REG
)
5444 int regno
= REGNO (dest
);
5445 enum rtx_code src_code
= GET_CODE (src
);
5447 if (CC_P (regno
) && src_code
== COMPARE
)
5448 skip_nested_if
= TRUE
;
5450 else if (CR_P (regno
)
5451 && (src_code
== IF_THEN_ELSE
5452 || COMPARISON_P (src
)))
5453 skip_nested_if
= TRUE
;
5457 if (! skip_nested_if
)
5458 for_each_rtx (&PATTERN (insn
), frv_clear_registers_used
,
5459 (void *)&frv_ifcvt
.nested_cc_ok_rewrite
);
5462 if (insn
== last_insn
)
5465 insn
= NEXT_INSN (insn
);
5469 /* If this is a nested if, rewrite the CC registers that are available to
5470 include the ones that can be rewritten, to increase the chance of being
5471 able to allocate a paired CC/CR register combination. */
5472 if (ce_info
->pass
> 1)
5474 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5475 if (TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
))
5476 SET_HARD_REG_BIT (tmp_reg
->regs
, j
);
5478 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, j
);
5484 fprintf (dump_file
, "Available GPRs: ");
5486 for (j
= GPR_FIRST
; j
<= GPR_LAST
; j
++)
5487 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5489 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5490 if (++num_gprs
> GPR_TEMP_NUM
+2)
5494 fprintf (dump_file
, "%s\nAvailable CRs: ",
5495 (num_gprs
> GPR_TEMP_NUM
+2) ? " ..." : "");
5497 for (j
= CR_FIRST
; j
<= CR_LAST
; j
++)
5498 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5499 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5501 fputs ("\n", dump_file
);
5503 if (ce_info
->pass
> 1)
5505 fprintf (dump_file
, "Modifiable CCs: ");
5506 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5507 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5508 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5510 fprintf (dump_file
, "\n%d nested COND_EXEC statements\n",
5511 frv_ifcvt
.num_nested_cond_exec
);
5515 /* Allocate the appropriate temporary condition code register. Try to
5516 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5517 that conditional cmp's can be done. */
5518 if (mode
== CCmode
|| mode
== CC_UNSmode
|| mode
== CC_NZmode
)
5520 cr_class
= ICR_REGS
;
5521 cc_class
= ICC_REGS
;
5522 cc_first
= ICC_FIRST
;
5525 else if (mode
== CC_FPmode
)
5527 cr_class
= FCR_REGS
;
5528 cc_class
= FCC_REGS
;
5529 cc_first
= FCC_FIRST
;
5534 cc_first
= cc_last
= 0;
5535 cr_class
= cc_class
= NO_REGS
;
5538 cc
= XEXP (true_expr
, 0);
5539 nested_cc
= cr
= NULL_RTX
;
5540 if (cc_class
!= NO_REGS
)
5542 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5543 so we can execute a csubcc/caddcc/cfcmps instruction. */
5546 for (cc_regno
= cc_first
; cc_regno
<= cc_last
; cc_regno
++)
5548 int cr_regno
= cc_regno
- CC_FIRST
+ CR_FIRST
;
5550 if (TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cc_regno
)
5551 && TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cr_regno
))
5553 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cr_class
] = cr_regno
;
5554 cr
= frv_alloc_temp_reg (tmp_reg
, cr_class
, CC_CCRmode
, TRUE
,
5557 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cc_class
] = cc_regno
;
5558 nested_cc
= frv_alloc_temp_reg (tmp_reg
, cc_class
, CCmode
,
5568 fprintf (dump_file
, "Could not allocate a CR temporary register\n");
5575 "Will use %s for conditional execution, %s for nested comparisons\n",
5576 reg_names
[ REGNO (cr
)],
5577 (nested_cc
) ? reg_names
[ REGNO (nested_cc
) ] : "<none>");
5579 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5580 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5581 bit being true. We don't do this for floating point, because of NaNs. */
5582 code
= GET_CODE (true_expr
);
5583 if (GET_MODE (cc
) != CC_FPmode
)
5585 code
= reverse_condition (code
);
5595 check_insn
= gen_rtx_SET (VOIDmode
, cr
,
5596 gen_rtx_fmt_ee (code
, CC_CCRmode
, cc
, const0_rtx
));
5598 /* Record the check insn to be inserted later. */
5599 frv_ifcvt_add_insn (check_insn
, BB_END (test_bb
), TRUE
);
5601 /* Update the tests. */
5602 frv_ifcvt
.cr_reg
= cr
;
5603 frv_ifcvt
.nested_cc_reg
= nested_cc
;
5604 *p_true
= gen_rtx_fmt_ee (code_true
, CC_CCRmode
, cr
, const0_rtx
);
5605 *p_false
= gen_rtx_fmt_ee (code_false
, CC_CCRmode
, cr
, const0_rtx
);
5608 /* Fail, don't do this conditional execution. */
5611 *p_false
= NULL_RTX
;
5613 fprintf (dump_file
, "Disabling this conditional execution.\n");
5619 /* A C expression to modify the code described by the conditional if
5620 information CE_INFO, for the basic block BB, possibly updating the tests in
5621 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5622 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5623 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5625 /* p_true and p_false are given expressions of the form:
5627 (and (eq:CC_CCR (reg:CC_CCR)
5633 frv_ifcvt_modify_multiple_tests (ce_if_block_t
*ce_info
,
5638 rtx old_true
= XEXP (*p_true
, 0);
5639 rtx old_false
= XEXP (*p_false
, 0);
5640 rtx true_expr
= XEXP (*p_true
, 1);
5641 rtx false_expr
= XEXP (*p_false
, 1);
5644 rtx cr
= XEXP (old_true
, 0);
5646 rtx new_cr
= NULL_RTX
;
5647 rtx
*p_new_cr
= (rtx
*)0;
5651 enum reg_class cr_class
;
5652 enum machine_mode mode
= GET_MODE (true_expr
);
5653 rtx (*logical_func
)(rtx
, rtx
, rtx
);
5655 if (TARGET_DEBUG_COND_EXEC
)
5658 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5659 ce_info
->and_and_p
? "&&" : "||");
5661 debug_rtx (*p_true
);
5663 fputs ("\nfalse insn:\n", stderr
);
5664 debug_rtx (*p_false
);
5667 if (!TARGET_MULTI_CE
)
5670 if (GET_CODE (cr
) != REG
)
5673 if (mode
== CCmode
|| mode
== CC_UNSmode
|| mode
== CC_NZmode
)
5675 cr_class
= ICR_REGS
;
5676 p_new_cr
= &frv_ifcvt
.extra_int_cr
;
5678 else if (mode
== CC_FPmode
)
5680 cr_class
= FCR_REGS
;
5681 p_new_cr
= &frv_ifcvt
.extra_fp_cr
;
5686 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5687 more &&/|| tests. */
5691 new_cr
= *p_new_cr
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, cr_class
,
5692 CC_CCRmode
, TRUE
, TRUE
);
5697 if (ce_info
->and_and_p
)
5699 old_test
= old_false
;
5700 test_expr
= true_expr
;
5701 logical_func
= (GET_CODE (old_true
) == EQ
) ? gen_andcr
: gen_andncr
;
5702 *p_true
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
5703 *p_false
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
5707 old_test
= old_false
;
5708 test_expr
= false_expr
;
5709 logical_func
= (GET_CODE (old_false
) == EQ
) ? gen_orcr
: gen_orncr
;
5710 *p_true
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
5711 *p_false
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
5714 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5715 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5717 frv_ifcvt_add_insn ((*logical_func
) (cr
, cr
, new_cr
), BB_END (bb
), TRUE
);
5719 /* Now add the conditional check insn. */
5720 cc
= XEXP (test_expr
, 0);
5721 compare
= gen_rtx_fmt_ee (GET_CODE (test_expr
), CC_CCRmode
, cc
, const0_rtx
);
5722 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, old_test
, compare
, const0_rtx
);
5724 check_insn
= gen_rtx_SET (VOIDmode
, new_cr
, if_else
);
5726 /* Add the new check insn to the list of check insns that need to be
5728 frv_ifcvt_add_insn (check_insn
, BB_END (bb
), TRUE
);
5730 if (TARGET_DEBUG_COND_EXEC
)
5732 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5735 debug_rtx (*p_true
);
5737 fputs ("\nfalse insn:\n", stderr
);
5738 debug_rtx (*p_false
);
5744 *p_true
= *p_false
= NULL_RTX
;
5746 /* If we allocated a CR register, release it. */
5749 CLEAR_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, REGNO (new_cr
));
5750 *p_new_cr
= NULL_RTX
;
5753 if (TARGET_DEBUG_COND_EXEC
)
5754 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr
);
5760 /* Return a register which will be loaded with a value if an IF block is
5761 converted to conditional execution. This is used to rewrite instructions
5762 that use constants to ones that just use registers. */
5765 frv_ifcvt_load_value (rtx value
, rtx insn ATTRIBUTE_UNUSED
)
5767 int num_alloc
= frv_ifcvt
.cur_scratch_regs
;
5771 /* We know gr0 == 0, so replace any errant uses. */
5772 if (value
== const0_rtx
)
5773 return gen_rtx_REG (SImode
, GPR_FIRST
);
5775 /* First search all registers currently loaded to see if we have an
5776 applicable constant. */
5777 if (CONSTANT_P (value
)
5778 || (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
))
5780 for (i
= 0; i
< num_alloc
; i
++)
5782 if (rtx_equal_p (SET_SRC (frv_ifcvt
.scratch_regs
[i
]), value
))
5783 return SET_DEST (frv_ifcvt
.scratch_regs
[i
]);
5787 /* Have we exhausted the number of registers available? */
5788 if (num_alloc
>= GPR_TEMP_NUM
)
5791 fprintf (dump_file
, "Too many temporary registers allocated\n");
5796 /* Allocate the new register. */
5797 reg
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, GPR_REGS
, SImode
, TRUE
, TRUE
);
5801 fputs ("Could not find a scratch register\n", dump_file
);
5806 frv_ifcvt
.cur_scratch_regs
++;
5807 frv_ifcvt
.scratch_regs
[num_alloc
] = gen_rtx_SET (VOIDmode
, reg
, value
);
5811 if (GET_CODE (value
) == CONST_INT
)
5812 fprintf (dump_file
, "Register %s will hold %ld\n",
5813 reg_names
[ REGNO (reg
)], (long)INTVAL (value
));
5815 else if (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
)
5816 fprintf (dump_file
, "Register %s will hold LR\n",
5817 reg_names
[ REGNO (reg
)]);
5820 fprintf (dump_file
, "Register %s will hold a saved value\n",
5821 reg_names
[ REGNO (reg
)]);
5828 /* Update a MEM used in conditional code that might contain an offset to put
5829 the offset into a scratch register, so that the conditional load/store
5830 operations can be used. This function returns the original pointer if the
5831 MEM is valid to use in conditional code, NULL if we can't load up the offset
5832 into a temporary register, or the new MEM if we were successful. */
5835 frv_ifcvt_rewrite_mem (rtx mem
, enum machine_mode mode
, rtx insn
)
5837 rtx addr
= XEXP (mem
, 0);
5839 if (!frv_legitimate_address_p_1 (mode
, addr
, reload_completed
, TRUE
, FALSE
))
5841 if (GET_CODE (addr
) == PLUS
)
5843 rtx addr_op0
= XEXP (addr
, 0);
5844 rtx addr_op1
= XEXP (addr
, 1);
5846 if (GET_CODE (addr_op0
) == REG
&& CONSTANT_P (addr_op1
))
5848 rtx reg
= frv_ifcvt_load_value (addr_op1
, insn
);
5852 addr
= gen_rtx_PLUS (Pmode
, addr_op0
, reg
);
5859 else if (CONSTANT_P (addr
))
5860 addr
= frv_ifcvt_load_value (addr
, insn
);
5865 if (addr
== NULL_RTX
)
5868 else if (XEXP (mem
, 0) != addr
)
5869 return change_address (mem
, mode
, addr
);
5876 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5877 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5880 single_set_pattern (rtx pattern
)
5885 if (GET_CODE (pattern
) == COND_EXEC
)
5886 pattern
= COND_EXEC_CODE (pattern
);
5888 if (GET_CODE (pattern
) == SET
)
5891 else if (GET_CODE (pattern
) == PARALLEL
)
5893 for (i
= 0, set
= 0; i
< XVECLEN (pattern
, 0); i
++)
5895 rtx sub
= XVECEXP (pattern
, 0, i
);
5897 switch (GET_CODE (sub
))
5921 /* A C expression to modify the code described by the conditional if
5922 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5923 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5924 insn cannot be converted to be executed conditionally. */
5927 frv_ifcvt_modify_insn (ce_if_block_t
*ce_info
,
5931 rtx orig_ce_pattern
= pattern
;
5937 gcc_assert (GET_CODE (pattern
) == COND_EXEC
);
5939 test
= COND_EXEC_TEST (pattern
);
5940 if (GET_CODE (test
) == AND
)
5942 rtx cr
= frv_ifcvt
.cr_reg
;
5945 op0
= XEXP (test
, 0);
5946 if (! rtx_equal_p (cr
, XEXP (op0
, 0)))
5949 op1
= XEXP (test
, 1);
5950 test_reg
= XEXP (op1
, 0);
5951 if (GET_CODE (test_reg
) != REG
)
5954 /* Is this the first nested if block in this sequence? If so, generate
5955 an andcr or andncr. */
5956 if (! frv_ifcvt
.last_nested_if_cr
)
5960 frv_ifcvt
.last_nested_if_cr
= test_reg
;
5961 if (GET_CODE (op0
) == NE
)
5962 and_op
= gen_andcr (test_reg
, cr
, test_reg
);
5964 and_op
= gen_andncr (test_reg
, cr
, test_reg
);
5966 frv_ifcvt_add_insn (and_op
, insn
, TRUE
);
5969 /* If this isn't the first statement in the nested if sequence, see if we
5970 are dealing with the same register. */
5971 else if (! rtx_equal_p (test_reg
, frv_ifcvt
.last_nested_if_cr
))
5974 COND_EXEC_TEST (pattern
) = test
= op1
;
5977 /* If this isn't a nested if, reset state variables. */
5980 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
5983 set
= single_set_pattern (pattern
);
5986 rtx dest
= SET_DEST (set
);
5987 rtx src
= SET_SRC (set
);
5988 enum machine_mode mode
= GET_MODE (dest
);
5990 /* Check for normal binary operators. */
5991 if (mode
== SImode
&& ARITHMETIC_P (src
))
5993 op0
= XEXP (src
, 0);
5994 op1
= XEXP (src
, 1);
5996 if (integer_register_operand (op0
, SImode
) && CONSTANT_P (op1
))
5998 op1
= frv_ifcvt_load_value (op1
, insn
);
6000 COND_EXEC_CODE (pattern
)
6001 = gen_rtx_SET (VOIDmode
, dest
, gen_rtx_fmt_ee (GET_CODE (src
),
6009 /* For multiply by a constant, we need to handle the sign extending
6010 correctly. Add a USE of the value after the multiply to prevent flow
6011 from cratering because only one register out of the two were used. */
6012 else if (mode
== DImode
&& GET_CODE (src
) == MULT
)
6014 op0
= XEXP (src
, 0);
6015 op1
= XEXP (src
, 1);
6016 if (GET_CODE (op0
) == SIGN_EXTEND
&& GET_CODE (op1
) == CONST_INT
)
6018 op1
= frv_ifcvt_load_value (op1
, insn
);
6021 op1
= gen_rtx_SIGN_EXTEND (DImode
, op1
);
6022 COND_EXEC_CODE (pattern
)
6023 = gen_rtx_SET (VOIDmode
, dest
,
6024 gen_rtx_MULT (DImode
, op0
, op1
));
6030 frv_ifcvt_add_insn (gen_use (dest
), insn
, FALSE
);
6033 /* If we are just loading a constant created for a nested conditional
6034 execution statement, just load the constant without any conditional
6035 execution, since we know that the constant will not interfere with any
6037 else if (frv_ifcvt
.scratch_insns_bitmap
6038 && bitmap_bit_p (frv_ifcvt
.scratch_insns_bitmap
,
6040 && REG_P (SET_DEST (set
))
6041 /* We must not unconditionally set a scratch reg chosen
6042 for a nested if-converted block if its incoming
6043 value from the TEST block (or the result of the THEN
6044 branch) could/should propagate to the JOIN block.
6045 It suffices to test whether the register is live at
6046 the JOIN point: if it's live there, we can infer
6047 that we set it in the former JOIN block of the
6048 nested if-converted block (otherwise it wouldn't
6049 have been available as a scratch register), and it
6050 is either propagated through or set in the other
6051 conditional block. It's probably not worth trying
6052 to catch the latter case, and it could actually
6053 limit scheduling of the combined block quite
6056 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info
->join_bb
),
6057 REGNO (SET_DEST (set
))))
6058 /* Similarly, we must not unconditionally set a reg
6059 used as scratch in the THEN branch if the same reg
6060 is live in the ELSE branch. */
6061 && (! ce_info
->else_bb
6062 || BLOCK_FOR_INSN (insn
) == ce_info
->else_bb
6063 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info
->else_bb
),
6064 REGNO (SET_DEST (set
))))))
6067 else if (mode
== QImode
|| mode
== HImode
|| mode
== SImode
6070 int changed_p
= FALSE
;
6072 /* Check for just loading up a constant */
6073 if (CONSTANT_P (src
) && integer_register_operand (dest
, mode
))
6075 src
= frv_ifcvt_load_value (src
, insn
);
6082 /* See if we need to fix up stores */
6083 if (GET_CODE (dest
) == MEM
)
6085 rtx new_mem
= frv_ifcvt_rewrite_mem (dest
, mode
, insn
);
6090 else if (new_mem
!= dest
)
6097 /* See if we need to fix up loads */
6098 if (GET_CODE (src
) == MEM
)
6100 rtx new_mem
= frv_ifcvt_rewrite_mem (src
, mode
, insn
);
6105 else if (new_mem
!= src
)
6112 /* If either src or destination changed, redo SET. */
6114 COND_EXEC_CODE (pattern
) = gen_rtx_SET (VOIDmode
, dest
, src
);
6117 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6118 rewriting the CC register to be the same as the paired CC/CR register
6120 else if (mode
== CC_CCRmode
&& COMPARISON_P (src
))
6122 int regno
= REGNO (XEXP (src
, 0));
6125 if (ce_info
->pass
> 1
6126 && regno
!= (int)REGNO (frv_ifcvt
.nested_cc_reg
)
6127 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, regno
))
6129 src
= gen_rtx_fmt_ee (GET_CODE (src
),
6131 frv_ifcvt
.nested_cc_reg
,
6135 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, test
, src
, const0_rtx
);
6136 pattern
= gen_rtx_SET (VOIDmode
, dest
, if_else
);
6139 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6140 else if (ce_info
->pass
> 1
6141 && GET_CODE (dest
) == REG
6142 && CC_P (REGNO (dest
))
6143 && REGNO (dest
) != REGNO (frv_ifcvt
.nested_cc_reg
)
6144 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
,
6146 && GET_CODE (src
) == COMPARE
)
6148 PUT_MODE (frv_ifcvt
.nested_cc_reg
, GET_MODE (dest
));
6149 COND_EXEC_CODE (pattern
)
6150 = gen_rtx_SET (VOIDmode
, frv_ifcvt
.nested_cc_reg
, copy_rtx (src
));
6154 if (TARGET_DEBUG_COND_EXEC
)
6156 rtx orig_pattern
= PATTERN (insn
);
6158 PATTERN (insn
) = pattern
;
6160 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6164 PATTERN (insn
) = orig_pattern
;
6170 if (TARGET_DEBUG_COND_EXEC
)
6172 rtx orig_pattern
= PATTERN (insn
);
6174 PATTERN (insn
) = orig_ce_pattern
;
6176 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6180 PATTERN (insn
) = orig_pattern
;
6187 /* A C expression to perform any final machine dependent modifications in
6188 converting code to conditional execution in the code described by the
6189 conditional if information CE_INFO. */
6192 frv_ifcvt_modify_final (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
6196 rtx p
= frv_ifcvt
.added_insns_list
;
6199 /* Loop inserting the check insns. The last check insn is the first test,
6200 and is the appropriate place to insert constants. */
6205 rtx check_and_insert_insns
= XEXP (p
, 0);
6208 check_insn
= XEXP (check_and_insert_insns
, 0);
6209 existing_insn
= XEXP (check_and_insert_insns
, 1);
6212 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6213 the existing insn, otherwise it is to be inserted AFTER. */
6214 if (check_and_insert_insns
->jump
)
6216 emit_insn_before (check_insn
, existing_insn
);
6217 check_and_insert_insns
->jump
= 0;
6220 emit_insn_after (check_insn
, existing_insn
);
6222 free_EXPR_LIST_node (check_and_insert_insns
);
6223 free_EXPR_LIST_node (old_p
);
6225 while (p
!= NULL_RTX
);
6227 /* Load up any constants needed into temp gprs */
6228 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
6230 rtx insn
= emit_insn_before (frv_ifcvt
.scratch_regs
[i
], existing_insn
);
6231 if (! frv_ifcvt
.scratch_insns_bitmap
)
6232 frv_ifcvt
.scratch_insns_bitmap
= BITMAP_ALLOC (NULL
);
6233 bitmap_set_bit (frv_ifcvt
.scratch_insns_bitmap
, INSN_UID (insn
));
6234 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
6237 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6238 frv_ifcvt
.cur_scratch_regs
= 0;
6242 /* A C expression to cancel any machine dependent modifications in converting
6243 code to conditional execution in the code described by the conditional if
6244 information CE_INFO. */
6247 frv_ifcvt_modify_cancel (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
6250 rtx p
= frv_ifcvt
.added_insns_list
;
6252 /* Loop freeing up the EXPR_LIST's allocated. */
6253 while (p
!= NULL_RTX
)
6255 rtx check_and_jump
= XEXP (p
, 0);
6259 free_EXPR_LIST_node (check_and_jump
);
6260 free_EXPR_LIST_node (old_p
);
6263 /* Release any temporary gprs allocated. */
6264 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
6265 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
6267 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6268 frv_ifcvt
.cur_scratch_regs
= 0;
6272 /* A C expression for the size in bytes of the trampoline, as an integer.
6276 setlo #0, <static_chain>
6278 sethi #0, <static_chain>
6279 jmpl @(gr0,<jmp_reg>) */
6282 frv_trampoline_size (void)
6285 /* Allocate room for the function descriptor and the lddi
6288 return 5 /* instructions */ * 4 /* instruction size. */;
6292 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6293 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6294 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6295 should be passed to the function when it is called.
6300 setlo #0, <static_chain>
6302 sethi #0, <static_chain>
6303 jmpl @(gr0,<jmp_reg>) */
6306 frv_trampoline_init (rtx m_tramp
, tree fndecl
, rtx static_chain
)
6308 rtx addr
= XEXP (m_tramp
, 0);
6309 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6310 rtx sc_reg
= force_reg (Pmode
, static_chain
);
6312 emit_library_call (gen_rtx_SYMBOL_REF (SImode
, "__trampoline_setup"),
6313 LCT_NORMAL
, VOIDmode
, 4,
6315 GEN_INT (frv_trampoline_size ()), SImode
,
6321 /* Many machines have some registers that cannot be copied directly to or from
6322 memory or even from other types of registers. An example is the `MQ'
6323 register, which on most machines, can only be copied to or from general
6324 registers, but not memory. Some machines allow copying all registers to and
6325 from memory, but require a scratch register for stores to some memory
6326 locations (e.g., those with symbolic address on the RT, and those with
6327 certain symbolic address on the SPARC when compiling PIC). In some cases,
6328 both an intermediate and a scratch register are required.
6330 You should define these macros to indicate to the reload phase that it may
6331 need to allocate at least one register for a reload in addition to the
6332 register to contain the data. Specifically, if copying X to a register
6333 RCLASS in MODE requires an intermediate register, you should define
6334 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6335 whose registers can be used as intermediate registers or scratch registers.
6337 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6338 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6339 largest register class required. If the requirements for input and output
6340 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6341 instead of defining both macros identically.
6343 The values returned by these macros are often `GENERAL_REGS'. Return
6344 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6345 to or from a register of RCLASS in MODE without requiring a scratch register.
6346 Do not define this macro if it would always return `NO_REGS'.
6348 If a scratch register is required (either with or without an intermediate
6349 register), you should define patterns for `reload_inM' or `reload_outM', as
6350 required.. These patterns, which will normally be implemented with a
6351 `define_expand', should be similar to the `movM' patterns, except that
6352 operand 2 is the scratch register.
6354 Define constraints for the reload register and scratch register that contain
6355 a single register class. If the original reload register (whose class is
6356 RCLASS) can meet the constraint given in the pattern, the value returned by
6357 these macros is used for the class of the scratch register. Otherwise, two
6358 additional reload registers are required. Their classes are obtained from
6359 the constraints in the insn pattern.
6361 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6362 either be in a hard register or in memory. Use `true_regnum' to find out;
6363 it will return -1 if the pseudo is in memory and the hard register number if
6364 it is in a register.
6366 These macros should not be used in the case where a particular class of
6367 registers can only be copied to memory and not to another class of
6368 registers. In that case, secondary reload registers are not needed and
6369 would not be helpful. Instead, a stack location must be used to perform the
6370 copy and the `movM' pattern should use memory as an intermediate storage.
6371 This case often occurs between floating-point and general registers. */
6374 frv_secondary_reload_class (enum reg_class rclass
,
6375 enum machine_mode mode ATTRIBUTE_UNUSED
,
6386 /* Accumulators/Accumulator guard registers need to go through floating
6391 if (x
&& GET_CODE (x
) == REG
)
6393 int regno
= REGNO (x
);
6395 if (ACC_P (regno
) || ACCG_P (regno
))
6400 /* Nonzero constants should be loaded into an FPR through a GPR. */
6402 if (x
&& CONSTANT_P (x
) && !ZERO_P (x
))
6408 /* All of these types need gpr registers. */
6420 /* The accumulators need fpr registers. */
6430 /* This hook exists to catch the case where secondary_reload_class() is
6431 called from init_reg_autoinc() in regclass.c - before the reload optabs
6432 have been initialised. */
6435 frv_secondary_reload (bool in_p
, rtx x
, reg_class_t reload_class_i
,
6436 enum machine_mode reload_mode
,
6437 secondary_reload_info
* sri
)
6439 enum reg_class rclass
= NO_REGS
;
6440 enum reg_class reload_class
= (enum reg_class
) reload_class_i
;
6442 if (sri
->prev_sri
&& sri
->prev_sri
->t_icode
!= CODE_FOR_nothing
)
6444 sri
->icode
= sri
->prev_sri
->t_icode
;
6448 rclass
= frv_secondary_reload_class (reload_class
, reload_mode
, x
);
6450 if (rclass
!= NO_REGS
)
6452 enum insn_code icode
6453 = direct_optab_handler (in_p
? reload_in_optab
: reload_out_optab
,
6457 /* This happens when then the reload_[in|out]_optabs have
6458 not been initialised. */
6459 sri
->t_icode
= CODE_FOR_nothing
;
6464 /* Fall back to the default secondary reload handler. */
6465 return default_secondary_reload (in_p
, x
, reload_class
, reload_mode
, sri
);
6469 /* Worker function for TARGET_CLASS_LIKELY_SPILLED_P. */
6472 frv_class_likely_spilled_p (reg_class_t rclass
)
6482 case FDPIC_FPTR_REGS
:
6502 /* An expression for the alignment of a structure field FIELD if the
6503 alignment computed in the usual way is COMPUTED. GCC uses this
6504 value instead of the value in `BIGGEST_ALIGNMENT' or
6505 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6507 /* The definition type of the bit field data is either char, short, long or
6508 long long. The maximum bit size is the number of bits of its own type.
6510 The bit field data is assigned to a storage unit that has an adequate size
6511 for bit field data retention and is located at the smallest address.
6513 Consecutive bit field data are packed at consecutive bits having the same
6514 storage unit, with regard to the type, beginning with the MSB and continuing
6517 If a field to be assigned lies over a bit field type boundary, its
6518 assignment is completed by aligning it with a boundary suitable for the
6521 When a bit field having a bit length of 0 is declared, it is forcibly
6522 assigned to the next storage unit.
6535 &x 00000000 00000000 00000000 00000000
6538 &x+4 00000000 00000000 00000000 00000000
6541 &x+8 00000000 00000000 00000000 00000000
6544 &x+12 00000000 00000000 00000000 00000000
6550 frv_adjust_field_align (tree field
, int computed
)
6552 /* Make sure that the bitfield is not wider than the type. */
6553 if (DECL_BIT_FIELD (field
)
6554 && !DECL_ARTIFICIAL (field
))
6556 tree parent
= DECL_CONTEXT (field
);
6557 tree prev
= NULL_TREE
;
6560 for (cur
= TYPE_FIELDS (parent
); cur
&& cur
!= field
; cur
= DECL_CHAIN (cur
))
6562 if (TREE_CODE (cur
) != FIELD_DECL
)
6570 /* If this isn't a :0 field and if the previous element is a bitfield
6571 also, see if the type is different, if so, we will need to align the
6572 bit-field to the next boundary. */
6574 && ! DECL_PACKED (field
)
6575 && ! integer_zerop (DECL_SIZE (field
))
6576 && DECL_BIT_FIELD_TYPE (field
) != DECL_BIT_FIELD_TYPE (prev
))
6578 int prev_align
= TYPE_ALIGN (TREE_TYPE (prev
));
6579 int cur_align
= TYPE_ALIGN (TREE_TYPE (field
));
6580 computed
= (prev_align
> cur_align
) ? prev_align
: cur_align
;
6588 /* A C expression that is nonzero if it is permissible to store a value of mode
6589 MODE in hard register number REGNO (or in several registers starting with
6590 that one). For a machine where all registers are equivalent, a suitable
6593 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6595 It is not necessary for this macro to check for the numbers of fixed
6596 registers, because the allocation mechanism considers them to be always
6599 On some machines, double-precision values must be kept in even/odd register
6600 pairs. The way to implement that is to define this macro to reject odd
6601 register numbers for such modes.
6603 The minimum requirement for a mode to be OK in a register is that the
6604 `movMODE' instruction pattern support moves between the register and any
6605 other hard register for which the mode is OK; and that moving a value into
6606 the register and back out not alter it.
6608 Since the same instruction used to move `SImode' will work for all narrower
6609 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6610 to distinguish between these modes, provided you define patterns `movhi',
6611 etc., to take advantage of this. This is useful because of the interaction
6612 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6613 all integer modes to be tieable.
6615 Many machines have special registers for floating point arithmetic. Often
6616 people assume that floating point machine modes are allowed only in floating
6617 point registers. This is not true. Any registers that can hold integers
6618 can safely *hold* a floating point machine mode, whether or not floating
6619 arithmetic can be done on it in those registers. Integer move instructions
6620 can be used to move the values.
6622 On some machines, though, the converse is true: fixed-point machine modes
6623 may not go in floating registers. This is true if the floating registers
6624 normalize any value stored in them, because storing a non-floating value
6625 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6626 fixed-point machine modes in floating registers. But if the floating
6627 registers do not automatically normalize, if you can store any bit pattern
6628 in one and retrieve it unchanged without a trap, then any machine mode may
6629 go in a floating register, so you can define this macro to say so.
6631 The primary significance of special floating registers is rather that they
6632 are the registers acceptable in floating point arithmetic instructions.
6633 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6634 writing the proper constraints for those instructions.
6636 On some machines, the floating registers are especially slow to access, so
6637 that it is better to store a value in a stack frame than in such a register
6638 if floating point arithmetic is not being done. As long as the floating
6639 registers are not in class `GENERAL_REGS', they will not be used unless some
6640 pattern's constraint asks for one. */
6643 frv_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
6653 return ICC_P (regno
) || GPR_P (regno
);
6656 return CR_P (regno
) || GPR_P (regno
);
6659 return FCC_P (regno
) || GPR_P (regno
);
6665 /* Set BASE to the first register in REGNO's class. Set MASK to the
6666 bits that must be clear in (REGNO - BASE) for the register to be
6668 if (INTEGRAL_MODE_P (mode
) || FLOAT_MODE_P (mode
) || VECTOR_MODE_P (mode
))
6672 /* ACCGs store one byte. Two-byte quantities must start in
6673 even-numbered registers, four-byte ones in registers whose
6674 numbers are divisible by four, and so on. */
6676 mask
= GET_MODE_SIZE (mode
) - 1;
6680 /* The other registers store one word. */
6681 if (GPR_P (regno
) || regno
== AP_FIRST
)
6684 else if (FPR_P (regno
))
6687 else if (ACC_P (regno
))
6690 else if (SPR_P (regno
))
6691 return mode
== SImode
;
6693 /* Fill in the table. */
6697 /* Anything smaller than an SI is OK in any word-sized register. */
6698 if (GET_MODE_SIZE (mode
) < 4)
6701 mask
= (GET_MODE_SIZE (mode
) / 4) - 1;
6703 return (((regno
- base
) & mask
) == 0);
6710 /* A C expression for the number of consecutive hard registers, starting at
6711 register number REGNO, required to hold a value of mode MODE.
6713 On a machine where all registers are exactly one word, a suitable definition
6716 #define HARD_REGNO_NREGS(REGNO, MODE) \
6717 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6718 / UNITS_PER_WORD)) */
6720 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6721 that we can build the appropriate instructions to properly reload the
6722 values. Also, make the byte-sized accumulator guards use one guard
6726 frv_hard_regno_nregs (int regno
, enum machine_mode mode
)
6729 return GET_MODE_SIZE (mode
);
6731 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6735 /* A C expression for the maximum number of consecutive registers of
6736 class RCLASS needed to hold a value of mode MODE.
6738 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6739 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6740 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6742 This macro helps control the handling of multiple-word values in
6745 This declaration is required. */
6748 frv_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
6750 if (rclass
== ACCG_REGS
)
6751 /* An N-byte value requires N accumulator guards. */
6752 return GET_MODE_SIZE (mode
);
6754 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6758 /* A C expression that is nonzero if X is a legitimate constant for an
6759 immediate operand on the target machine. You can assume that X satisfies
6760 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6761 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6764 frv_legitimate_constant_p (enum machine_mode mode
, rtx x
)
6766 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6767 means that the move expanders will be expected to deal with most
6768 kinds of constant, regardless of what we return here.
6770 However, among its other duties, frv_legitimate_constant_p decides whether
6771 a constant can be entered into reg_equiv_constant[]. If we return true,
6772 reload can create new instances of the constant whenever it likes.
6774 The idea is therefore to accept as many constants as possible (to give
6775 reload more freedom) while rejecting constants that can only be created
6776 at certain times. In particular, anything with a symbolic component will
6777 require use of the pseudo FDPIC register, which is only available before
6780 return LEGITIMATE_PIC_OPERAND_P (x
);
6782 /* All of the integer constants are ok. */
6783 if (GET_CODE (x
) != CONST_DOUBLE
)
6786 /* double integer constants are ok. */
6787 if (GET_MODE (x
) == VOIDmode
|| mode
== DImode
)
6790 /* 0 is always ok. */
6791 if (x
== CONST0_RTX (mode
))
6794 /* If floating point is just emulated, allow any constant, since it will be
6795 constructed in the GPRs. */
6796 if (!TARGET_HAS_FPRS
)
6799 if (mode
== DFmode
&& !TARGET_DOUBLE
)
6802 /* Otherwise store the constant away and do a load. */
6806 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6807 CC_NZ for comparisons against zero in which a single Z or N flag test
6808 is enough, CC_UNS for other unsigned comparisons, and CC for other
6809 signed comparisons. */
6812 frv_select_cc_mode (enum rtx_code code
, rtx x
, rtx y
)
6814 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6823 return y
== const0_rtx
? CC_NZmode
: CCmode
;
6829 return y
== const0_rtx
? CC_NZmode
: CC_UNSmode
;
6837 /* Worker function for TARGET_REGISTER_MOVE_COST. */
6839 #define HIGH_COST 40
6840 #define MEDIUM_COST 3
6844 frv_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
6845 reg_class_t from
, reg_class_t to
)
6858 case FDPIC_FPTR_REGS
:
6859 case FDPIC_CALL_REGS
:
6872 case FDPIC_FPTR_REGS
:
6873 case FDPIC_CALL_REGS
:
6898 case FDPIC_FPTR_REGS
:
6899 case FDPIC_CALL_REGS
:
6923 case FDPIC_FPTR_REGS
:
6924 case FDPIC_CALL_REGS
:
6945 /* Worker function for TARGET_MEMORY_MOVE_COST. */
6948 frv_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
6949 reg_class_t rclass ATTRIBUTE_UNUSED
,
6950 bool in ATTRIBUTE_UNUSED
)
6956 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
6957 use ".picptr" to generate safe relocations for PIC code. We also
6958 need a fixup entry for aligned (non-debugging) code. */
6961 frv_assemble_integer (rtx value
, unsigned int size
, int aligned_p
)
6963 if ((flag_pic
|| TARGET_FDPIC
) && size
== UNITS_PER_WORD
)
6965 if (GET_CODE (value
) == CONST
6966 || GET_CODE (value
) == SYMBOL_REF
6967 || GET_CODE (value
) == LABEL_REF
)
6969 if (TARGET_FDPIC
&& GET_CODE (value
) == SYMBOL_REF
6970 && SYMBOL_REF_FUNCTION_P (value
))
6972 fputs ("\t.picptr\tfuncdesc(", asm_out_file
);
6973 output_addr_const (asm_out_file
, value
);
6974 fputs (")\n", asm_out_file
);
6977 else if (TARGET_FDPIC
&& GET_CODE (value
) == CONST
6978 && frv_function_symbol_referenced_p (value
))
6980 if (aligned_p
&& !TARGET_FDPIC
)
6982 static int label_num
= 0;
6986 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", label_num
++);
6987 p
= (* targetm
.strip_name_encoding
) (buf
);
6989 fprintf (asm_out_file
, "%s:\n", p
);
6990 fprintf (asm_out_file
, "%s\n", FIXUP_SECTION_ASM_OP
);
6991 fprintf (asm_out_file
, "\t.picptr\t%s\n", p
);
6992 fprintf (asm_out_file
, "\t.previous\n");
6994 assemble_integer_with_op ("\t.picptr\t", value
);
6999 /* We've set the unaligned SI op to NULL, so we always have to
7000 handle the unaligned case here. */
7001 assemble_integer_with_op ("\t.4byte\t", value
);
7005 return default_assemble_integer (value
, size
, aligned_p
);
7008 /* Function to set up the backend function structure. */
7010 static struct machine_function
*
7011 frv_init_machine_status (void)
7013 return ggc_alloc_cleared_machine_function ();
7016 /* Implement TARGET_SCHED_ISSUE_RATE. */
7019 frv_issue_rate (void)
7024 switch (frv_cpu_type
)
7028 case FRV_CPU_SIMPLE
:
7036 case FRV_CPU_GENERIC
:
7038 case FRV_CPU_TOMCAT
:
7046 /* A for_each_rtx callback. If X refers to an accumulator, return
7047 ACC_GROUP_ODD if the bit 2 of the register number is set and
7048 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
7052 frv_acc_group_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
7056 if (ACC_P (REGNO (*x
)))
7057 return (REGNO (*x
) - ACC_FIRST
) & 4 ? ACC_GROUP_ODD
: ACC_GROUP_EVEN
;
7058 if (ACCG_P (REGNO (*x
)))
7059 return (REGNO (*x
) - ACCG_FIRST
) & 4 ? ACC_GROUP_ODD
: ACC_GROUP_EVEN
;
7064 /* Return the value of INSN's acc_group attribute. */
7067 frv_acc_group (rtx insn
)
7069 /* This distinction only applies to the FR550 packing constraints. */
7070 if (frv_cpu_type
!= FRV_CPU_FR550
)
7071 return ACC_GROUP_NONE
;
7072 return for_each_rtx (&PATTERN (insn
), frv_acc_group_1
, 0);
7075 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7076 INSN will try to claim first. Since this value depends only on the
7077 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7080 frv_insn_unit (rtx insn
)
7082 enum attr_type type
;
7084 type
= get_attr_type (insn
);
7085 if (frv_type_to_unit
[type
] == ARRAY_SIZE (frv_unit_codes
))
7087 /* We haven't seen this type of instruction before. */
7091 /* Issue the instruction on its own to see which unit it prefers. */
7092 state
= alloca (state_size ());
7093 state_reset (state
);
7094 state_transition (state
, insn
);
7096 /* Find out which unit was taken. */
7097 for (unit
= 0; unit
< ARRAY_SIZE (frv_unit_codes
); unit
++)
7098 if (cpu_unit_reservation_p (state
, frv_unit_codes
[unit
]))
7101 gcc_assert (unit
!= ARRAY_SIZE (frv_unit_codes
));
7103 frv_type_to_unit
[type
] = unit
;
7105 return frv_type_to_unit
[type
];
7108 /* Return true if INSN issues to a branch unit. */
7111 frv_issues_to_branch_unit_p (rtx insn
)
7113 return frv_unit_groups
[frv_insn_unit (insn
)] == GROUP_B
;
7116 /* The instructions in the packet, partitioned into groups. */
7117 struct frv_packet_group
{
7118 /* How many instructions in the packet belong to this group. */
7119 unsigned int num_insns
;
7121 /* A list of the instructions that belong to this group, in the order
7122 they appear in the rtl stream. */
7123 rtx insns
[ARRAY_SIZE (frv_unit_codes
)];
7125 /* The contents of INSNS after they have been sorted into the correct
7126 assembly-language order. Element X issues to unit X. The list may
7127 contain extra nops. */
7128 rtx sorted
[ARRAY_SIZE (frv_unit_codes
)];
7130 /* The member of frv_nops[] to use in sorted[]. */
7134 /* The current state of the packing pass, implemented by frv_pack_insns. */
7136 /* The state of the pipeline DFA. */
7139 /* Which hardware registers are set within the current packet,
7140 and the conditions under which they are set. */
7141 regstate_t regstate
[FIRST_PSEUDO_REGISTER
];
7143 /* The memory locations that have been modified so far in this
7144 packet. MEM is the memref and COND is the regstate_t condition
7145 under which it is set. */
7151 /* The number of valid entries in MEMS. The value is larger than
7152 ARRAY_SIZE (mems) if there were too many mems to record. */
7153 unsigned int num_mems
;
7155 /* The maximum number of instructions that can be packed together. */
7156 unsigned int issue_rate
;
7158 /* The instructions in the packet, partitioned into groups. */
7159 struct frv_packet_group groups
[NUM_GROUPS
];
7161 /* The instructions that make up the current packet. */
7162 rtx insns
[ARRAY_SIZE (frv_unit_codes
)];
7163 unsigned int num_insns
;
7166 /* Return the regstate_t flags for the given COND_EXEC condition.
7167 Abort if the condition isn't in the right form. */
7170 frv_cond_flags (rtx cond
)
7172 gcc_assert ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
7173 && GET_CODE (XEXP (cond
, 0)) == REG
7174 && CR_P (REGNO (XEXP (cond
, 0)))
7175 && XEXP (cond
, 1) == const0_rtx
);
7176 return ((REGNO (XEXP (cond
, 0)) - CR_FIRST
)
7177 | (GET_CODE (cond
) == NE
7179 : REGSTATE_IF_FALSE
));
7183 /* Return true if something accessed under condition COND2 can
7184 conflict with something written under condition COND1. */
7187 frv_regstate_conflict_p (regstate_t cond1
, regstate_t cond2
)
7189 /* If either reference was unconditional, we have a conflict. */
7190 if ((cond1
& REGSTATE_IF_EITHER
) == 0
7191 || (cond2
& REGSTATE_IF_EITHER
) == 0)
7194 /* The references might conflict if they were controlled by
7196 if ((cond1
& REGSTATE_CC_MASK
) != (cond2
& REGSTATE_CC_MASK
))
7199 /* They definitely conflict if they are controlled by the
7201 if ((cond1
& cond2
& REGSTATE_IF_EITHER
) != 0)
7208 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7209 the current packet. DATA points to a regstate_t that describes the
7210 condition under which *X might be set or used. */
7213 frv_registers_conflict_p_1 (rtx
*x
, void *data
)
7215 unsigned int regno
, i
;
7218 cond
= *(regstate_t
*) data
;
7220 if (GET_CODE (*x
) == REG
)
7221 FOR_EACH_REGNO (regno
, *x
)
7222 if ((frv_packet
.regstate
[regno
] & REGSTATE_MODIFIED
) != 0)
7223 if (frv_regstate_conflict_p (frv_packet
.regstate
[regno
], cond
))
7226 if (GET_CODE (*x
) == MEM
)
7228 /* If we ran out of memory slots, assume a conflict. */
7229 if (frv_packet
.num_mems
> ARRAY_SIZE (frv_packet
.mems
))
7232 /* Check for output or true dependencies with earlier MEMs. */
7233 for (i
= 0; i
< frv_packet
.num_mems
; i
++)
7234 if (frv_regstate_conflict_p (frv_packet
.mems
[i
].cond
, cond
))
7236 if (true_dependence (frv_packet
.mems
[i
].mem
, VOIDmode
, *x
))
7239 if (output_dependence (frv_packet
.mems
[i
].mem
, *x
))
7244 /* The return values of calls aren't significant: they describe
7245 the effect of the call as a whole, not of the insn itself. */
7246 if (GET_CODE (*x
) == SET
&& GET_CODE (SET_SRC (*x
)) == CALL
)
7248 if (for_each_rtx (&SET_SRC (*x
), frv_registers_conflict_p_1
, data
))
7253 /* Check subexpressions. */
7258 /* Return true if something in X might depend on an instruction
7259 in the current packet. */
7262 frv_registers_conflict_p (rtx x
)
7267 if (GET_CODE (x
) == COND_EXEC
)
7269 if (for_each_rtx (&XEXP (x
, 0), frv_registers_conflict_p_1
, &flags
))
7272 flags
|= frv_cond_flags (XEXP (x
, 0));
7275 return for_each_rtx (&x
, frv_registers_conflict_p_1
, &flags
);
7279 /* A note_stores callback. DATA points to the regstate_t condition
7280 under which X is modified. Update FRV_PACKET accordingly. */
7283 frv_registers_update_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7287 if (GET_CODE (x
) == REG
)
7288 FOR_EACH_REGNO (regno
, x
)
7289 frv_packet
.regstate
[regno
] |= *(regstate_t
*) data
;
7291 if (GET_CODE (x
) == MEM
)
7293 if (frv_packet
.num_mems
< ARRAY_SIZE (frv_packet
.mems
))
7295 frv_packet
.mems
[frv_packet
.num_mems
].mem
= x
;
7296 frv_packet
.mems
[frv_packet
.num_mems
].cond
= *(regstate_t
*) data
;
7298 frv_packet
.num_mems
++;
7303 /* Update the register state information for an instruction whose
7307 frv_registers_update (rtx x
)
7311 flags
= REGSTATE_MODIFIED
;
7312 if (GET_CODE (x
) == COND_EXEC
)
7314 flags
|= frv_cond_flags (XEXP (x
, 0));
7317 note_stores (x
, frv_registers_update_1
, &flags
);
7321 /* Initialize frv_packet for the start of a new packet. */
7324 frv_start_packet (void)
7326 enum frv_insn_group group
;
7328 memset (frv_packet
.regstate
, 0, sizeof (frv_packet
.regstate
));
7329 frv_packet
.num_mems
= 0;
7330 frv_packet
.num_insns
= 0;
7331 for (group
= GROUP_I
; group
< NUM_GROUPS
;
7332 group
= (enum frv_insn_group
) (group
+ 1))
7333 frv_packet
.groups
[group
].num_insns
= 0;
7337 /* Likewise for the start of a new basic block. */
7340 frv_start_packet_block (void)
7342 state_reset (frv_packet
.dfa_state
);
7343 frv_start_packet ();
7347 /* Finish the current packet, if any, and start a new one. Call
7348 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7351 frv_finish_packet (void (*handle_packet
) (void))
7353 if (frv_packet
.num_insns
> 0)
7356 state_transition (frv_packet
.dfa_state
, 0);
7357 frv_start_packet ();
7362 /* Return true if INSN can be added to the current packet. Update
7363 the DFA state on success. */
7366 frv_pack_insn_p (rtx insn
)
7368 /* See if the packet is already as long as it can be. */
7369 if (frv_packet
.num_insns
== frv_packet
.issue_rate
)
7372 /* If the scheduler thought that an instruction should start a packet,
7373 it's usually a good idea to believe it. It knows much more about
7374 the latencies than we do.
7376 There are some exceptions though:
7378 - Conditional instructions are scheduled on the assumption that
7379 they will be executed. This is usually a good thing, since it
7380 tends to avoid unnecessary stalls in the conditional code.
7381 But we want to pack conditional instructions as tightly as
7382 possible, in order to optimize the case where they aren't
7385 - The scheduler will always put branches on their own, even
7386 if there's no real dependency.
7388 - There's no point putting a call in its own packet unless
7390 if (frv_packet
.num_insns
> 0
7391 && GET_CODE (insn
) == INSN
7392 && GET_MODE (insn
) == TImode
7393 && GET_CODE (PATTERN (insn
)) != COND_EXEC
)
7396 /* Check for register conflicts. Don't do this for setlo since any
7397 conflict will be with the partnering sethi, with which it can
7399 if (get_attr_type (insn
) != TYPE_SETLO
)
7400 if (frv_registers_conflict_p (PATTERN (insn
)))
7403 return state_transition (frv_packet
.dfa_state
, insn
) < 0;
7407 /* Add instruction INSN to the current packet. */
7410 frv_add_insn_to_packet (rtx insn
)
7412 struct frv_packet_group
*packet_group
;
7414 packet_group
= &frv_packet
.groups
[frv_unit_groups
[frv_insn_unit (insn
)]];
7415 packet_group
->insns
[packet_group
->num_insns
++] = insn
;
7416 frv_packet
.insns
[frv_packet
.num_insns
++] = insn
;
7418 frv_registers_update (PATTERN (insn
));
7422 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7423 packet ends in a branch or call, insert the nop before it, otherwise
7427 frv_insert_nop_in_packet (rtx insn
)
7429 struct frv_packet_group
*packet_group
;
7432 packet_group
= &frv_packet
.groups
[frv_unit_groups
[frv_insn_unit (insn
)]];
7433 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
7434 if (GET_CODE (last
) != INSN
)
7436 insn
= emit_insn_before (PATTERN (insn
), last
);
7437 frv_packet
.insns
[frv_packet
.num_insns
- 1] = insn
;
7438 frv_packet
.insns
[frv_packet
.num_insns
++] = last
;
7442 insn
= emit_insn_after (PATTERN (insn
), last
);
7443 frv_packet
.insns
[frv_packet
.num_insns
++] = insn
;
7445 packet_group
->insns
[packet_group
->num_insns
++] = insn
;
7449 /* If packing is enabled, divide the instructions into packets and
7450 return true. Call HANDLE_PACKET for each complete packet. */
7453 frv_for_each_packet (void (*handle_packet
) (void))
7455 rtx insn
, next_insn
;
7457 frv_packet
.issue_rate
= frv_issue_rate ();
7459 /* Early exit if we don't want to pack insns. */
7461 || !flag_schedule_insns_after_reload
7462 || !TARGET_VLIW_BRANCH
7463 || frv_packet
.issue_rate
== 1)
7466 /* Set up the initial packing state. */
7468 frv_packet
.dfa_state
= alloca (state_size ());
7470 frv_start_packet_block ();
7471 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
7476 code
= GET_CODE (insn
);
7477 next_insn
= NEXT_INSN (insn
);
7479 if (code
== CODE_LABEL
)
7481 frv_finish_packet (handle_packet
);
7482 frv_start_packet_block ();
7486 switch (GET_CODE (PATTERN (insn
)))
7495 /* Calls mustn't be packed on a TOMCAT. */
7496 if (GET_CODE (insn
) == CALL_INSN
&& frv_cpu_type
== FRV_CPU_TOMCAT
)
7497 frv_finish_packet (handle_packet
);
7499 /* Since the last instruction in a packet determines the EH
7500 region, any exception-throwing instruction must come at
7501 the end of reordered packet. Insns that issue to a
7502 branch unit are bound to come last; for others it's
7503 too hard to predict. */
7504 eh_insn_p
= (find_reg_note (insn
, REG_EH_REGION
, NULL
) != NULL
);
7505 if (eh_insn_p
&& !frv_issues_to_branch_unit_p (insn
))
7506 frv_finish_packet (handle_packet
);
7508 /* Finish the current packet if we can't add INSN to it.
7509 Simulate cycles until INSN is ready to issue. */
7510 if (!frv_pack_insn_p (insn
))
7512 frv_finish_packet (handle_packet
);
7513 while (!frv_pack_insn_p (insn
))
7514 state_transition (frv_packet
.dfa_state
, 0);
7517 /* Add the instruction to the packet. */
7518 frv_add_insn_to_packet (insn
);
7520 /* Calls and jumps end a packet, as do insns that throw
7522 if (code
== CALL_INSN
|| code
== JUMP_INSN
|| eh_insn_p
)
7523 frv_finish_packet (handle_packet
);
7527 frv_finish_packet (handle_packet
);
7532 /* Subroutine of frv_sort_insn_group. We are trying to sort
7533 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7534 language order. We have already picked a new position for
7535 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7536 These instructions will occupy elements [0, LOWER_SLOT) and
7537 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7538 the DFA state after issuing these instructions.
7540 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7541 of the unused instructions. Return true if one such permutation gives
7542 a valid ordering, leaving the successful permutation in sorted[].
7543 Do not modify sorted[] until a valid permutation is found. */
7546 frv_sort_insn_group_1 (enum frv_insn_group group
,
7547 unsigned int lower_slot
, unsigned int upper_slot
,
7548 unsigned int issued
, unsigned int num_insns
,
7551 struct frv_packet_group
*packet_group
;
7557 /* Early success if we've filled all the slots. */
7558 if (lower_slot
== upper_slot
)
7561 packet_group
= &frv_packet
.groups
[group
];
7562 dfa_size
= state_size ();
7563 test_state
= alloca (dfa_size
);
7565 /* Try issuing each unused instruction. */
7566 for (i
= num_insns
- 1; i
+ 1 != 0; i
--)
7567 if (~issued
& (1 << i
))
7569 insn
= packet_group
->sorted
[i
];
7570 memcpy (test_state
, state
, dfa_size
);
7571 if (state_transition (test_state
, insn
) < 0
7572 && cpu_unit_reservation_p (test_state
,
7573 NTH_UNIT (group
, upper_slot
- 1))
7574 && frv_sort_insn_group_1 (group
, lower_slot
, upper_slot
- 1,
7575 issued
| (1 << i
), num_insns
,
7578 packet_group
->sorted
[upper_slot
- 1] = insn
;
7586 /* Compare two instructions by their frv_insn_unit. */
7589 frv_compare_insns (const void *first
, const void *second
)
7591 const rtx
*const insn1
= (rtx
const *) first
,
7592 *const insn2
= (rtx
const *) second
;
7593 return frv_insn_unit (*insn1
) - frv_insn_unit (*insn2
);
7596 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7597 and sort it into assembly language order. See frv.md for a description of
7601 frv_sort_insn_group (enum frv_insn_group group
)
7603 struct frv_packet_group
*packet_group
;
7604 unsigned int first
, i
, nop
, max_unit
, num_slots
;
7605 state_t state
, test_state
;
7608 packet_group
= &frv_packet
.groups
[group
];
7610 /* Assume no nop is needed. */
7611 packet_group
->nop
= 0;
7613 if (packet_group
->num_insns
== 0)
7616 /* Copy insns[] to sorted[]. */
7617 memcpy (packet_group
->sorted
, packet_group
->insns
,
7618 sizeof (rtx
) * packet_group
->num_insns
);
7620 /* Sort sorted[] by the unit that each insn tries to take first. */
7621 if (packet_group
->num_insns
> 1)
7622 qsort (packet_group
->sorted
, packet_group
->num_insns
,
7623 sizeof (rtx
), frv_compare_insns
);
7625 /* That's always enough for branch and control insns. */
7626 if (group
== GROUP_B
|| group
== GROUP_C
)
7629 dfa_size
= state_size ();
7630 state
= alloca (dfa_size
);
7631 test_state
= alloca (dfa_size
);
7633 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7634 consecutively and such that the DFA takes unit X when sorted[X]
7635 is added. Set STATE to the new DFA state. */
7636 state_reset (test_state
);
7637 for (first
= 0; first
< packet_group
->num_insns
; first
++)
7639 memcpy (state
, test_state
, dfa_size
);
7640 if (state_transition (test_state
, packet_group
->sorted
[first
]) >= 0
7641 || !cpu_unit_reservation_p (test_state
, NTH_UNIT (group
, first
)))
7645 /* If all the instructions issued in ascending order, we're done. */
7646 if (first
== packet_group
->num_insns
)
7649 /* Add nops to the end of sorted[] and try each permutation until
7650 we find one that works. */
7651 for (nop
= 0; nop
< frv_num_nops
; nop
++)
7653 max_unit
= frv_insn_unit (frv_nops
[nop
]);
7654 if (frv_unit_groups
[max_unit
] == group
)
7656 packet_group
->nop
= frv_nops
[nop
];
7657 num_slots
= UNIT_NUMBER (max_unit
) + 1;
7658 for (i
= packet_group
->num_insns
; i
< num_slots
; i
++)
7659 packet_group
->sorted
[i
] = frv_nops
[nop
];
7660 if (frv_sort_insn_group_1 (group
, first
, num_slots
,
7661 (1 << first
) - 1, num_slots
, state
))
7668 /* Sort the current packet into assembly-language order. Set packing
7669 flags as appropriate. */
7672 frv_reorder_packet (void)
7674 unsigned int cursor
[NUM_GROUPS
];
7675 rtx insns
[ARRAY_SIZE (frv_unit_groups
)];
7676 unsigned int unit
, to
, from
;
7677 enum frv_insn_group group
;
7678 struct frv_packet_group
*packet_group
;
7680 /* First sort each group individually. */
7681 for (group
= GROUP_I
; group
< NUM_GROUPS
;
7682 group
= (enum frv_insn_group
) (group
+ 1))
7685 frv_sort_insn_group (group
);
7688 /* Go through the unit template and try add an instruction from
7689 that unit's group. */
7691 for (unit
= 0; unit
< ARRAY_SIZE (frv_unit_groups
); unit
++)
7693 group
= frv_unit_groups
[unit
];
7694 packet_group
= &frv_packet
.groups
[group
];
7695 if (cursor
[group
] < packet_group
->num_insns
)
7697 /* frv_reorg should have added nops for us. */
7698 gcc_assert (packet_group
->sorted
[cursor
[group
]]
7699 != packet_group
->nop
);
7700 insns
[to
++] = packet_group
->sorted
[cursor
[group
]++];
7704 gcc_assert (to
== frv_packet
.num_insns
);
7706 /* Clear the last instruction's packing flag, thus marking the end of
7707 a packet. Reorder the other instructions relative to it. */
7708 CLEAR_PACKING_FLAG (insns
[to
- 1]);
7709 for (from
= 0; from
< to
- 1; from
++)
7711 remove_insn (insns
[from
]);
7712 add_insn_before (insns
[from
], insns
[to
- 1], NULL
);
7713 SET_PACKING_FLAG (insns
[from
]);
7718 /* Divide instructions into packets. Reorder the contents of each
7719 packet so that they are in the correct assembly-language order.
7721 Since this pass can change the raw meaning of the rtl stream, it must
7722 only be called at the last minute, just before the instructions are
7726 frv_pack_insns (void)
7728 if (frv_for_each_packet (frv_reorder_packet
))
7729 frv_insn_packing_flag
= 0;
7731 frv_insn_packing_flag
= -1;
7734 /* See whether we need to add nops to group GROUP in order to
7735 make a valid packet. */
7738 frv_fill_unused_units (enum frv_insn_group group
)
7740 unsigned int non_nops
, nops
, i
;
7741 struct frv_packet_group
*packet_group
;
7743 packet_group
= &frv_packet
.groups
[group
];
7745 /* Sort the instructions into assembly-language order.
7746 Use nops to fill slots that are otherwise unused. */
7747 frv_sort_insn_group (group
);
7749 /* See how many nops are needed before the final useful instruction. */
7751 for (non_nops
= 0; non_nops
< packet_group
->num_insns
; non_nops
++)
7752 while (packet_group
->sorted
[i
++] == packet_group
->nop
)
7755 /* Insert that many nops into the instruction stream. */
7757 frv_insert_nop_in_packet (packet_group
->nop
);
7760 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7763 frv_same_doubleword_p (const struct frv_io
*io1
, const struct frv_io
*io2
)
7765 if (io1
->const_address
!= 0 && io2
->const_address
!= 0)
7766 return io1
->const_address
== io2
->const_address
;
7768 if (io1
->var_address
!= 0 && io2
->var_address
!= 0)
7769 return rtx_equal_p (io1
->var_address
, io2
->var_address
);
7774 /* Return true if operations IO1 and IO2 are guaranteed to complete
7778 frv_io_fixed_order_p (const struct frv_io
*io1
, const struct frv_io
*io2
)
7780 /* The order of writes is always preserved. */
7781 if (io1
->type
== FRV_IO_WRITE
&& io2
->type
== FRV_IO_WRITE
)
7784 /* The order of reads isn't preserved. */
7785 if (io1
->type
!= FRV_IO_WRITE
&& io2
->type
!= FRV_IO_WRITE
)
7788 /* One operation is a write and the other is (or could be) a read.
7789 The order is only guaranteed if the accesses are to the same
7791 return frv_same_doubleword_p (io1
, io2
);
7794 /* Generalize I/O operation X so that it covers both X and Y. */
7797 frv_io_union (struct frv_io
*x
, const struct frv_io
*y
)
7799 if (x
->type
!= y
->type
)
7800 x
->type
= FRV_IO_UNKNOWN
;
7801 if (!frv_same_doubleword_p (x
, y
))
7803 x
->const_address
= 0;
7808 /* Fill IO with information about the load or store associated with
7809 membar instruction INSN. */
7812 frv_extract_membar (struct frv_io
*io
, rtx insn
)
7814 extract_insn (insn
);
7815 io
->type
= (enum frv_io_type
) INTVAL (recog_data
.operand
[2]);
7816 io
->const_address
= INTVAL (recog_data
.operand
[1]);
7817 io
->var_address
= XEXP (recog_data
.operand
[0], 0);
7820 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7821 if X is a register and *DATA depends on X. */
7824 frv_io_check_address (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7826 rtx
*other
= (rtx
*) data
;
7828 if (REG_P (x
) && *other
!= 0 && reg_overlap_mentioned_p (x
, *other
))
7832 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7833 Remove every modified register from the set. */
7836 frv_io_handle_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7838 HARD_REG_SET
*set
= (HARD_REG_SET
*) data
;
7842 FOR_EACH_REGNO (regno
, x
)
7843 CLEAR_HARD_REG_BIT (*set
, regno
);
7846 /* A for_each_rtx callback for which DATA points to a HARD_REG_SET.
7847 Add every register in *X to the set. */
7850 frv_io_handle_use_1 (rtx
*x
, void *data
)
7852 HARD_REG_SET
*set
= (HARD_REG_SET
*) data
;
7856 FOR_EACH_REGNO (regno
, *x
)
7857 SET_HARD_REG_BIT (*set
, regno
);
7862 /* A note_stores callback that applies frv_io_handle_use_1 to an
7863 entire rhs value. */
7866 frv_io_handle_use (rtx
*x
, void *data
)
7868 for_each_rtx (x
, frv_io_handle_use_1
, data
);
7871 /* Go through block BB looking for membars to remove. There are two
7872 cases where intra-block analysis is enough:
7874 - a membar is redundant if it occurs between two consecutive I/O
7875 operations and if those operations are guaranteed to complete
7878 - a membar for a __builtin_read is redundant if the result is
7879 used before the next I/O operation is issued.
7881 If the last membar in the block could not be removed, and there
7882 are guaranteed to be no I/O operations between that membar and
7883 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7886 Describe the block's first I/O operation in *NEXT_IO. Describe
7887 an unknown operation if the block doesn't do any I/O. */
7890 frv_optimize_membar_local (basic_block bb
, struct frv_io
*next_io
,
7893 HARD_REG_SET used_regs
;
7894 rtx next_membar
, set
, insn
;
7897 /* NEXT_IO is the next I/O operation to be performed after the current
7898 instruction. It starts off as being an unknown operation. */
7899 memset (next_io
, 0, sizeof (*next_io
));
7901 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7902 next_is_end_p
= true;
7904 /* If the current instruction is a __builtin_read or __builtin_write,
7905 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7906 is null if the membar has already been deleted.
7908 Note that the initialization here should only be needed to
7909 suppress warnings. */
7912 /* USED_REGS is the set of registers that are used before the
7913 next I/O instruction. */
7914 CLEAR_HARD_REG_SET (used_regs
);
7916 for (insn
= BB_END (bb
); insn
!= BB_HEAD (bb
); insn
= PREV_INSN (insn
))
7917 if (GET_CODE (insn
) == CALL_INSN
)
7919 /* We can't predict what a call will do to volatile memory. */
7920 memset (next_io
, 0, sizeof (struct frv_io
));
7921 next_is_end_p
= false;
7922 CLEAR_HARD_REG_SET (used_regs
);
7924 else if (INSN_P (insn
))
7925 switch (recog_memoized (insn
))
7927 case CODE_FOR_optional_membar_qi
:
7928 case CODE_FOR_optional_membar_hi
:
7929 case CODE_FOR_optional_membar_si
:
7930 case CODE_FOR_optional_membar_di
:
7934 /* Local information isn't enough to decide whether this
7935 membar is needed. Stash it away for later. */
7936 *last_membar
= insn
;
7937 frv_extract_membar (next_io
, insn
);
7938 next_is_end_p
= false;
7942 /* Check whether the I/O operation before INSN could be
7943 reordered with one described by NEXT_IO. If it can't,
7944 INSN will not be needed. */
7945 struct frv_io prev_io
;
7947 frv_extract_membar (&prev_io
, insn
);
7948 if (frv_io_fixed_order_p (&prev_io
, next_io
))
7952 ";; [Local] Removing membar %d since order"
7953 " of accesses is guaranteed\n",
7954 INSN_UID (next_membar
));
7956 insn
= NEXT_INSN (insn
);
7957 delete_insn (next_membar
);
7965 /* Invalidate NEXT_IO's address if it depends on something that
7966 is clobbered by INSN. */
7967 if (next_io
->var_address
)
7968 note_stores (PATTERN (insn
), frv_io_check_address
,
7969 &next_io
->var_address
);
7971 /* If the next membar is associated with a __builtin_read,
7972 see if INSN reads from that address. If it does, and if
7973 the destination register is used before the next I/O access,
7974 there is no need for the membar. */
7975 set
= PATTERN (insn
);
7976 if (next_io
->type
== FRV_IO_READ
7977 && next_io
->var_address
!= 0
7979 && GET_CODE (set
) == SET
7980 && GET_CODE (SET_DEST (set
)) == REG
7981 && TEST_HARD_REG_BIT (used_regs
, REGNO (SET_DEST (set
))))
7985 src
= SET_SRC (set
);
7986 if (GET_CODE (src
) == ZERO_EXTEND
)
7987 src
= XEXP (src
, 0);
7989 if (GET_CODE (src
) == MEM
7990 && rtx_equal_p (XEXP (src
, 0), next_io
->var_address
))
7994 ";; [Local] Removing membar %d since the target"
7995 " of %d is used before the I/O operation\n",
7996 INSN_UID (next_membar
), INSN_UID (insn
));
7998 if (next_membar
== *last_membar
)
8001 delete_insn (next_membar
);
8006 /* If INSN has volatile references, forget about any registers
8007 that are used after it. Otherwise forget about uses that
8008 are (or might be) defined by INSN. */
8009 if (volatile_refs_p (PATTERN (insn
)))
8010 CLEAR_HARD_REG_SET (used_regs
);
8012 note_stores (PATTERN (insn
), frv_io_handle_set
, &used_regs
);
8014 note_uses (&PATTERN (insn
), frv_io_handle_use
, &used_regs
);
8019 /* See if MEMBAR, the last membar instruction in BB, can be removed.
8020 FIRST_IO[X] describes the first operation performed by basic block X. */
8023 frv_optimize_membar_global (basic_block bb
, struct frv_io
*first_io
,
8026 struct frv_io this_io
, next_io
;
8030 /* We need to keep the membar if there is an edge to the exit block. */
8031 FOR_EACH_EDGE (succ
, ei
, bb
->succs
)
8032 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
8033 if (succ
->dest
== EXIT_BLOCK_PTR
)
8036 /* Work out the union of all successor blocks. */
8037 ei
= ei_start (bb
->succs
);
8038 ei_cond (ei
, &succ
);
8039 /* next_io = first_io[bb->succ->dest->index]; */
8040 next_io
= first_io
[succ
->dest
->index
];
8041 ei
= ei_start (bb
->succs
);
8042 if (ei_cond (ei
, &succ
))
8044 for (ei_next (&ei
); ei_cond (ei
, &succ
); ei_next (&ei
))
8045 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
8046 frv_io_union (&next_io
, &first_io
[succ
->dest
->index
]);
8051 frv_extract_membar (&this_io
, membar
);
8052 if (frv_io_fixed_order_p (&this_io
, &next_io
))
8056 ";; [Global] Removing membar %d since order of accesses"
8057 " is guaranteed\n", INSN_UID (membar
));
8059 delete_insn (membar
);
8063 /* Remove redundant membars from the current function. */
8066 frv_optimize_membar (void)
8069 struct frv_io
*first_io
;
8072 compute_bb_for_insn ();
8073 first_io
= XCNEWVEC (struct frv_io
, last_basic_block
);
8074 last_membar
= XCNEWVEC (rtx
, last_basic_block
);
8077 frv_optimize_membar_local (bb
, &first_io
[bb
->index
],
8078 &last_membar
[bb
->index
]);
8081 if (last_membar
[bb
->index
] != 0)
8082 frv_optimize_membar_global (bb
, first_io
, last_membar
[bb
->index
]);
8088 /* Used by frv_reorg to keep track of the current packet's address. */
8089 static unsigned int frv_packet_address
;
8091 /* If the current packet falls through to a label, try to pad the packet
8092 with nops in order to fit the label's alignment requirements. */
8095 frv_align_label (void)
8097 unsigned int alignment
, target
, nop
;
8098 rtx x
, last
, barrier
, label
;
8100 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8101 maximum alignment of that packet, LABEL to the last label between
8102 the packets, and BARRIER to the last barrier. */
8103 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
8104 label
= barrier
= 0;
8106 for (x
= NEXT_INSN (last
); x
!= 0 && !INSN_P (x
); x
= NEXT_INSN (x
))
8110 unsigned int subalign
= 1 << label_to_alignment (x
);
8111 alignment
= MAX (alignment
, subalign
);
8118 /* If -malign-labels, and the packet falls through to an unaligned
8119 label, try introducing a nop to align that label to 8 bytes. */
8120 if (TARGET_ALIGN_LABELS
8123 && frv_packet
.num_insns
< frv_packet
.issue_rate
)
8124 alignment
= MAX (alignment
, 8);
8126 /* Advance the address to the end of the current packet. */
8127 frv_packet_address
+= frv_packet
.num_insns
* 4;
8129 /* Work out the target address, after alignment. */
8130 target
= (frv_packet_address
+ alignment
- 1) & -alignment
;
8132 /* If the packet falls through to the label, try to find an efficient
8133 padding sequence. */
8136 /* First try adding nops to the current packet. */
8137 for (nop
= 0; nop
< frv_num_nops
; nop
++)
8138 while (frv_packet_address
< target
&& frv_pack_insn_p (frv_nops
[nop
]))
8140 frv_insert_nop_in_packet (frv_nops
[nop
]);
8141 frv_packet_address
+= 4;
8144 /* If we still haven't reached the target, add some new packets that
8145 contain only nops. If there are two types of nop, insert an
8146 alternating sequence of frv_nops[0] and frv_nops[1], which will
8147 lead to packets like:
8154 etc. Just emit frv_nops[0] if that's the only nop we have. */
8155 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
8157 while (frv_packet_address
< target
)
8159 last
= emit_insn_after (PATTERN (frv_nops
[nop
]), last
);
8160 frv_packet_address
+= 4;
8161 if (frv_num_nops
> 1)
8166 frv_packet_address
= target
;
8169 /* Subroutine of frv_reorg, called after each packet has been constructed
8173 frv_reorg_packet (void)
8175 frv_fill_unused_units (GROUP_I
);
8176 frv_fill_unused_units (GROUP_FM
);
8180 /* Add an instruction with pattern NOP to frv_nops[]. */
8183 frv_register_nop (rtx nop
)
8185 nop
= make_insn_raw (nop
);
8186 NEXT_INSN (nop
) = 0;
8187 PREV_INSN (nop
) = 0;
8188 frv_nops
[frv_num_nops
++] = nop
;
8191 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8192 into packets and check whether we need to insert nops in order to
8193 fulfill the processor's issue requirements. Also, if the user has
8194 requested a certain alignment for a label, try to meet that alignment
8195 by inserting nops in the previous packet. */
8200 if (optimize
> 0 && TARGET_OPTIMIZE_MEMBAR
&& cfun
->machine
->has_membar_p
)
8201 frv_optimize_membar ();
8204 frv_register_nop (gen_nop ());
8206 frv_register_nop (gen_mnop ());
8207 if (TARGET_HARD_FLOAT
)
8208 frv_register_nop (gen_fnop ());
8210 /* Estimate the length of each branch. Although this may change after
8211 we've inserted nops, it will only do so in big functions. */
8212 shorten_branches (get_insns ());
8214 frv_packet_address
= 0;
8215 frv_for_each_packet (frv_reorg_packet
);
8218 #define def_builtin(name, type, code) \
8219 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8221 struct builtin_description
8223 enum insn_code icode
;
8225 enum frv_builtins code
;
8226 enum rtx_code comparison
;
8230 /* Media intrinsics that take a single, constant argument. */
8232 static struct builtin_description bdesc_set
[] =
8234 { CODE_FOR_mhdsets
, "__MHDSETS", FRV_BUILTIN_MHDSETS
, UNKNOWN
, 0 }
8237 /* Media intrinsics that take just one argument. */
8239 static struct builtin_description bdesc_1arg
[] =
8241 { CODE_FOR_mnot
, "__MNOT", FRV_BUILTIN_MNOT
, UNKNOWN
, 0 },
8242 { CODE_FOR_munpackh
, "__MUNPACKH", FRV_BUILTIN_MUNPACKH
, UNKNOWN
, 0 },
8243 { CODE_FOR_mbtoh
, "__MBTOH", FRV_BUILTIN_MBTOH
, UNKNOWN
, 0 },
8244 { CODE_FOR_mhtob
, "__MHTOB", FRV_BUILTIN_MHTOB
, UNKNOWN
, 0},
8245 { CODE_FOR_mabshs
, "__MABSHS", FRV_BUILTIN_MABSHS
, UNKNOWN
, 0 },
8246 { CODE_FOR_scutss
, "__SCUTSS", FRV_BUILTIN_SCUTSS
, UNKNOWN
, 0 }
8249 /* Media intrinsics that take two arguments. */
8251 static struct builtin_description bdesc_2arg
[] =
8253 { CODE_FOR_mand
, "__MAND", FRV_BUILTIN_MAND
, UNKNOWN
, 0},
8254 { CODE_FOR_mor
, "__MOR", FRV_BUILTIN_MOR
, UNKNOWN
, 0},
8255 { CODE_FOR_mxor
, "__MXOR", FRV_BUILTIN_MXOR
, UNKNOWN
, 0},
8256 { CODE_FOR_maveh
, "__MAVEH", FRV_BUILTIN_MAVEH
, UNKNOWN
, 0},
8257 { CODE_FOR_msaths
, "__MSATHS", FRV_BUILTIN_MSATHS
, UNKNOWN
, 0},
8258 { CODE_FOR_msathu
, "__MSATHU", FRV_BUILTIN_MSATHU
, UNKNOWN
, 0},
8259 { CODE_FOR_maddhss
, "__MADDHSS", FRV_BUILTIN_MADDHSS
, UNKNOWN
, 0},
8260 { CODE_FOR_maddhus
, "__MADDHUS", FRV_BUILTIN_MADDHUS
, UNKNOWN
, 0},
8261 { CODE_FOR_msubhss
, "__MSUBHSS", FRV_BUILTIN_MSUBHSS
, UNKNOWN
, 0},
8262 { CODE_FOR_msubhus
, "__MSUBHUS", FRV_BUILTIN_MSUBHUS
, UNKNOWN
, 0},
8263 { CODE_FOR_mqaddhss
, "__MQADDHSS", FRV_BUILTIN_MQADDHSS
, UNKNOWN
, 0},
8264 { CODE_FOR_mqaddhus
, "__MQADDHUS", FRV_BUILTIN_MQADDHUS
, UNKNOWN
, 0},
8265 { CODE_FOR_mqsubhss
, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS
, UNKNOWN
, 0},
8266 { CODE_FOR_mqsubhus
, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS
, UNKNOWN
, 0},
8267 { CODE_FOR_mpackh
, "__MPACKH", FRV_BUILTIN_MPACKH
, UNKNOWN
, 0},
8268 { CODE_FOR_mcop1
, "__Mcop1", FRV_BUILTIN_MCOP1
, UNKNOWN
, 0},
8269 { CODE_FOR_mcop2
, "__Mcop2", FRV_BUILTIN_MCOP2
, UNKNOWN
, 0},
8270 { CODE_FOR_mwcut
, "__MWCUT", FRV_BUILTIN_MWCUT
, UNKNOWN
, 0},
8271 { CODE_FOR_mqsaths
, "__MQSATHS", FRV_BUILTIN_MQSATHS
, UNKNOWN
, 0},
8272 { CODE_FOR_mqlclrhs
, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS
, UNKNOWN
, 0},
8273 { CODE_FOR_mqlmths
, "__MQLMTHS", FRV_BUILTIN_MQLMTHS
, UNKNOWN
, 0},
8274 { CODE_FOR_smul
, "__SMUL", FRV_BUILTIN_SMUL
, UNKNOWN
, 0},
8275 { CODE_FOR_umul
, "__UMUL", FRV_BUILTIN_UMUL
, UNKNOWN
, 0},
8276 { CODE_FOR_addss
, "__ADDSS", FRV_BUILTIN_ADDSS
, UNKNOWN
, 0},
8277 { CODE_FOR_subss
, "__SUBSS", FRV_BUILTIN_SUBSS
, UNKNOWN
, 0},
8278 { CODE_FOR_slass
, "__SLASS", FRV_BUILTIN_SLASS
, UNKNOWN
, 0},
8279 { CODE_FOR_scan
, "__SCAN", FRV_BUILTIN_SCAN
, UNKNOWN
, 0}
8282 /* Integer intrinsics that take two arguments and have no return value. */
8284 static struct builtin_description bdesc_int_void2arg
[] =
8286 { CODE_FOR_smass
, "__SMASS", FRV_BUILTIN_SMASS
, UNKNOWN
, 0},
8287 { CODE_FOR_smsss
, "__SMSSS", FRV_BUILTIN_SMSSS
, UNKNOWN
, 0},
8288 { CODE_FOR_smu
, "__SMU", FRV_BUILTIN_SMU
, UNKNOWN
, 0}
8291 static struct builtin_description bdesc_prefetches
[] =
8293 { CODE_FOR_frv_prefetch0
, "__data_prefetch0", FRV_BUILTIN_PREFETCH0
, UNKNOWN
,
8295 { CODE_FOR_frv_prefetch
, "__data_prefetch", FRV_BUILTIN_PREFETCH
, UNKNOWN
, 0}
8298 /* Media intrinsics that take two arguments, the first being an ACC number. */
8300 static struct builtin_description bdesc_cut
[] =
8302 { CODE_FOR_mcut
, "__MCUT", FRV_BUILTIN_MCUT
, UNKNOWN
, 0},
8303 { CODE_FOR_mcutss
, "__MCUTSS", FRV_BUILTIN_MCUTSS
, UNKNOWN
, 0},
8304 { CODE_FOR_mdcutssi
, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI
, UNKNOWN
, 0}
8307 /* Two-argument media intrinsics with an immediate second argument. */
8309 static struct builtin_description bdesc_2argimm
[] =
8311 { CODE_FOR_mrotli
, "__MROTLI", FRV_BUILTIN_MROTLI
, UNKNOWN
, 0},
8312 { CODE_FOR_mrotri
, "__MROTRI", FRV_BUILTIN_MROTRI
, UNKNOWN
, 0},
8313 { CODE_FOR_msllhi
, "__MSLLHI", FRV_BUILTIN_MSLLHI
, UNKNOWN
, 0},
8314 { CODE_FOR_msrlhi
, "__MSRLHI", FRV_BUILTIN_MSRLHI
, UNKNOWN
, 0},
8315 { CODE_FOR_msrahi
, "__MSRAHI", FRV_BUILTIN_MSRAHI
, UNKNOWN
, 0},
8316 { CODE_FOR_mexpdhw
, "__MEXPDHW", FRV_BUILTIN_MEXPDHW
, UNKNOWN
, 0},
8317 { CODE_FOR_mexpdhd
, "__MEXPDHD", FRV_BUILTIN_MEXPDHD
, UNKNOWN
, 0},
8318 { CODE_FOR_mdrotli
, "__MDROTLI", FRV_BUILTIN_MDROTLI
, UNKNOWN
, 0},
8319 { CODE_FOR_mcplhi
, "__MCPLHI", FRV_BUILTIN_MCPLHI
, UNKNOWN
, 0},
8320 { CODE_FOR_mcpli
, "__MCPLI", FRV_BUILTIN_MCPLI
, UNKNOWN
, 0},
8321 { CODE_FOR_mhsetlos
, "__MHSETLOS", FRV_BUILTIN_MHSETLOS
, UNKNOWN
, 0},
8322 { CODE_FOR_mhsetloh
, "__MHSETLOH", FRV_BUILTIN_MHSETLOH
, UNKNOWN
, 0},
8323 { CODE_FOR_mhsethis
, "__MHSETHIS", FRV_BUILTIN_MHSETHIS
, UNKNOWN
, 0},
8324 { CODE_FOR_mhsethih
, "__MHSETHIH", FRV_BUILTIN_MHSETHIH
, UNKNOWN
, 0},
8325 { CODE_FOR_mhdseth
, "__MHDSETH", FRV_BUILTIN_MHDSETH
, UNKNOWN
, 0},
8326 { CODE_FOR_mqsllhi
, "__MQSLLHI", FRV_BUILTIN_MQSLLHI
, UNKNOWN
, 0},
8327 { CODE_FOR_mqsrahi
, "__MQSRAHI", FRV_BUILTIN_MQSRAHI
, UNKNOWN
, 0}
8330 /* Media intrinsics that take two arguments and return void, the first argument
8331 being a pointer to 4 words in memory. */
8333 static struct builtin_description bdesc_void2arg
[] =
8335 { CODE_FOR_mdunpackh
, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH
, UNKNOWN
, 0},
8336 { CODE_FOR_mbtohe
, "__MBTOHE", FRV_BUILTIN_MBTOHE
, UNKNOWN
, 0},
8339 /* Media intrinsics that take three arguments, the first being a const_int that
8340 denotes an accumulator, and that return void. */
8342 static struct builtin_description bdesc_void3arg
[] =
8344 { CODE_FOR_mcpxrs
, "__MCPXRS", FRV_BUILTIN_MCPXRS
, UNKNOWN
, 0},
8345 { CODE_FOR_mcpxru
, "__MCPXRU", FRV_BUILTIN_MCPXRU
, UNKNOWN
, 0},
8346 { CODE_FOR_mcpxis
, "__MCPXIS", FRV_BUILTIN_MCPXIS
, UNKNOWN
, 0},
8347 { CODE_FOR_mcpxiu
, "__MCPXIU", FRV_BUILTIN_MCPXIU
, UNKNOWN
, 0},
8348 { CODE_FOR_mmulhs
, "__MMULHS", FRV_BUILTIN_MMULHS
, UNKNOWN
, 0},
8349 { CODE_FOR_mmulhu
, "__MMULHU", FRV_BUILTIN_MMULHU
, UNKNOWN
, 0},
8350 { CODE_FOR_mmulxhs
, "__MMULXHS", FRV_BUILTIN_MMULXHS
, UNKNOWN
, 0},
8351 { CODE_FOR_mmulxhu
, "__MMULXHU", FRV_BUILTIN_MMULXHU
, UNKNOWN
, 0},
8352 { CODE_FOR_mmachs
, "__MMACHS", FRV_BUILTIN_MMACHS
, UNKNOWN
, 0},
8353 { CODE_FOR_mmachu
, "__MMACHU", FRV_BUILTIN_MMACHU
, UNKNOWN
, 0},
8354 { CODE_FOR_mmrdhs
, "__MMRDHS", FRV_BUILTIN_MMRDHS
, UNKNOWN
, 0},
8355 { CODE_FOR_mmrdhu
, "__MMRDHU", FRV_BUILTIN_MMRDHU
, UNKNOWN
, 0},
8356 { CODE_FOR_mqcpxrs
, "__MQCPXRS", FRV_BUILTIN_MQCPXRS
, UNKNOWN
, 0},
8357 { CODE_FOR_mqcpxru
, "__MQCPXRU", FRV_BUILTIN_MQCPXRU
, UNKNOWN
, 0},
8358 { CODE_FOR_mqcpxis
, "__MQCPXIS", FRV_BUILTIN_MQCPXIS
, UNKNOWN
, 0},
8359 { CODE_FOR_mqcpxiu
, "__MQCPXIU", FRV_BUILTIN_MQCPXIU
, UNKNOWN
, 0},
8360 { CODE_FOR_mqmulhs
, "__MQMULHS", FRV_BUILTIN_MQMULHS
, UNKNOWN
, 0},
8361 { CODE_FOR_mqmulhu
, "__MQMULHU", FRV_BUILTIN_MQMULHU
, UNKNOWN
, 0},
8362 { CODE_FOR_mqmulxhs
, "__MQMULXHS", FRV_BUILTIN_MQMULXHS
, UNKNOWN
, 0},
8363 { CODE_FOR_mqmulxhu
, "__MQMULXHU", FRV_BUILTIN_MQMULXHU
, UNKNOWN
, 0},
8364 { CODE_FOR_mqmachs
, "__MQMACHS", FRV_BUILTIN_MQMACHS
, UNKNOWN
, 0},
8365 { CODE_FOR_mqmachu
, "__MQMACHU", FRV_BUILTIN_MQMACHU
, UNKNOWN
, 0},
8366 { CODE_FOR_mqxmachs
, "__MQXMACHS", FRV_BUILTIN_MQXMACHS
, UNKNOWN
, 0},
8367 { CODE_FOR_mqxmacxhs
, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS
, UNKNOWN
, 0},
8368 { CODE_FOR_mqmacxhs
, "__MQMACXHS", FRV_BUILTIN_MQMACXHS
, UNKNOWN
, 0}
8371 /* Media intrinsics that take two accumulator numbers as argument and
8374 static struct builtin_description bdesc_voidacc
[] =
8376 { CODE_FOR_maddaccs
, "__MADDACCS", FRV_BUILTIN_MADDACCS
, UNKNOWN
, 0},
8377 { CODE_FOR_msubaccs
, "__MSUBACCS", FRV_BUILTIN_MSUBACCS
, UNKNOWN
, 0},
8378 { CODE_FOR_masaccs
, "__MASACCS", FRV_BUILTIN_MASACCS
, UNKNOWN
, 0},
8379 { CODE_FOR_mdaddaccs
, "__MDADDACCS", FRV_BUILTIN_MDADDACCS
, UNKNOWN
, 0},
8380 { CODE_FOR_mdsubaccs
, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS
, UNKNOWN
, 0},
8381 { CODE_FOR_mdasaccs
, "__MDASACCS", FRV_BUILTIN_MDASACCS
, UNKNOWN
, 0}
8384 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8385 a normal move and the ICODE is for the membar. */
8387 static struct builtin_description bdesc_loads
[] =
8389 { CODE_FOR_optional_membar_qi
, "__builtin_read8",
8390 FRV_BUILTIN_READ8
, UNKNOWN
, 0},
8391 { CODE_FOR_optional_membar_hi
, "__builtin_read16",
8392 FRV_BUILTIN_READ16
, UNKNOWN
, 0},
8393 { CODE_FOR_optional_membar_si
, "__builtin_read32",
8394 FRV_BUILTIN_READ32
, UNKNOWN
, 0},
8395 { CODE_FOR_optional_membar_di
, "__builtin_read64",
8396 FRV_BUILTIN_READ64
, UNKNOWN
, 0}
8399 /* Likewise stores. */
8401 static struct builtin_description bdesc_stores
[] =
8403 { CODE_FOR_optional_membar_qi
, "__builtin_write8",
8404 FRV_BUILTIN_WRITE8
, UNKNOWN
, 0},
8405 { CODE_FOR_optional_membar_hi
, "__builtin_write16",
8406 FRV_BUILTIN_WRITE16
, UNKNOWN
, 0},
8407 { CODE_FOR_optional_membar_si
, "__builtin_write32",
8408 FRV_BUILTIN_WRITE32
, UNKNOWN
, 0},
8409 { CODE_FOR_optional_membar_di
, "__builtin_write64",
8410 FRV_BUILTIN_WRITE64
, UNKNOWN
, 0},
8413 /* Initialize media builtins. */
8416 frv_init_builtins (void)
8418 tree accumulator
= integer_type_node
;
8419 tree integer
= integer_type_node
;
8420 tree voidt
= void_type_node
;
8421 tree uhalf
= short_unsigned_type_node
;
8422 tree sword1
= long_integer_type_node
;
8423 tree uword1
= long_unsigned_type_node
;
8424 tree sword2
= long_long_integer_type_node
;
8425 tree uword2
= long_long_unsigned_type_node
;
8426 tree uword4
= build_pointer_type (uword1
);
8427 tree vptr
= build_pointer_type (build_type_variant (void_type_node
, 0, 1));
8428 tree ubyte
= unsigned_char_type_node
;
8429 tree iacc
= integer_type_node
;
8431 #define UNARY(RET, T1) \
8432 build_function_type_list (RET, T1, NULL_TREE)
8434 #define BINARY(RET, T1, T2) \
8435 build_function_type_list (RET, T1, T2, NULL_TREE)
8437 #define TRINARY(RET, T1, T2, T3) \
8438 build_function_type_list (RET, T1, T2, T3, NULL_TREE)
8440 #define QUAD(RET, T1, T2, T3, T4) \
8441 build_function_type_list (RET, T1, T2, T3, T4, NULL_TREE)
8443 tree void_ftype_void
= build_function_type_list (voidt
, NULL_TREE
);
8445 tree void_ftype_acc
= UNARY (voidt
, accumulator
);
8446 tree void_ftype_uw4_uw1
= BINARY (voidt
, uword4
, uword1
);
8447 tree void_ftype_uw4_uw2
= BINARY (voidt
, uword4
, uword2
);
8448 tree void_ftype_acc_uw1
= BINARY (voidt
, accumulator
, uword1
);
8449 tree void_ftype_acc_acc
= BINARY (voidt
, accumulator
, accumulator
);
8450 tree void_ftype_acc_uw1_uw1
= TRINARY (voidt
, accumulator
, uword1
, uword1
);
8451 tree void_ftype_acc_sw1_sw1
= TRINARY (voidt
, accumulator
, sword1
, sword1
);
8452 tree void_ftype_acc_uw2_uw2
= TRINARY (voidt
, accumulator
, uword2
, uword2
);
8453 tree void_ftype_acc_sw2_sw2
= TRINARY (voidt
, accumulator
, sword2
, sword2
);
8455 tree uw1_ftype_uw1
= UNARY (uword1
, uword1
);
8456 tree uw1_ftype_sw1
= UNARY (uword1
, sword1
);
8457 tree uw1_ftype_uw2
= UNARY (uword1
, uword2
);
8458 tree uw1_ftype_acc
= UNARY (uword1
, accumulator
);
8459 tree uw1_ftype_uh_uh
= BINARY (uword1
, uhalf
, uhalf
);
8460 tree uw1_ftype_uw1_uw1
= BINARY (uword1
, uword1
, uword1
);
8461 tree uw1_ftype_uw1_int
= BINARY (uword1
, uword1
, integer
);
8462 tree uw1_ftype_acc_uw1
= BINARY (uword1
, accumulator
, uword1
);
8463 tree uw1_ftype_acc_sw1
= BINARY (uword1
, accumulator
, sword1
);
8464 tree uw1_ftype_uw2_uw1
= BINARY (uword1
, uword2
, uword1
);
8465 tree uw1_ftype_uw2_int
= BINARY (uword1
, uword2
, integer
);
8467 tree sw1_ftype_int
= UNARY (sword1
, integer
);
8468 tree sw1_ftype_sw1_sw1
= BINARY (sword1
, sword1
, sword1
);
8469 tree sw1_ftype_sw1_int
= BINARY (sword1
, sword1
, integer
);
8471 tree uw2_ftype_uw1
= UNARY (uword2
, uword1
);
8472 tree uw2_ftype_uw1_int
= BINARY (uword2
, uword1
, integer
);
8473 tree uw2_ftype_uw2_uw2
= BINARY (uword2
, uword2
, uword2
);
8474 tree uw2_ftype_uw2_int
= BINARY (uword2
, uword2
, integer
);
8475 tree uw2_ftype_acc_int
= BINARY (uword2
, accumulator
, integer
);
8476 tree uw2_ftype_uh_uh_uh_uh
= QUAD (uword2
, uhalf
, uhalf
, uhalf
, uhalf
);
8478 tree sw2_ftype_sw2_sw2
= BINARY (sword2
, sword2
, sword2
);
8479 tree sw2_ftype_sw2_int
= BINARY (sword2
, sword2
, integer
);
8480 tree uw2_ftype_uw1_uw1
= BINARY (uword2
, uword1
, uword1
);
8481 tree sw2_ftype_sw1_sw1
= BINARY (sword2
, sword1
, sword1
);
8482 tree void_ftype_sw1_sw1
= BINARY (voidt
, sword1
, sword1
);
8483 tree void_ftype_iacc_sw2
= BINARY (voidt
, iacc
, sword2
);
8484 tree void_ftype_iacc_sw1
= BINARY (voidt
, iacc
, sword1
);
8485 tree sw1_ftype_sw1
= UNARY (sword1
, sword1
);
8486 tree sw2_ftype_iacc
= UNARY (sword2
, iacc
);
8487 tree sw1_ftype_iacc
= UNARY (sword1
, iacc
);
8488 tree void_ftype_ptr
= UNARY (voidt
, const_ptr_type_node
);
8489 tree uw1_ftype_vptr
= UNARY (uword1
, vptr
);
8490 tree uw2_ftype_vptr
= UNARY (uword2
, vptr
);
8491 tree void_ftype_vptr_ub
= BINARY (voidt
, vptr
, ubyte
);
8492 tree void_ftype_vptr_uh
= BINARY (voidt
, vptr
, uhalf
);
8493 tree void_ftype_vptr_uw1
= BINARY (voidt
, vptr
, uword1
);
8494 tree void_ftype_vptr_uw2
= BINARY (voidt
, vptr
, uword2
);
8496 def_builtin ("__MAND", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAND
);
8497 def_builtin ("__MOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MOR
);
8498 def_builtin ("__MXOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MXOR
);
8499 def_builtin ("__MNOT", uw1_ftype_uw1
, FRV_BUILTIN_MNOT
);
8500 def_builtin ("__MROTLI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTLI
);
8501 def_builtin ("__MROTRI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTRI
);
8502 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1
, FRV_BUILTIN_MWCUT
);
8503 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAVEH
);
8504 def_builtin ("__MSLLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSLLHI
);
8505 def_builtin ("__MSRLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSRLHI
);
8506 def_builtin ("__MSRAHI", sw1_ftype_sw1_int
, FRV_BUILTIN_MSRAHI
);
8507 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSATHS
);
8508 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSATHU
);
8509 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MADDHSS
);
8510 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MADDHUS
);
8511 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSUBHSS
);
8512 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSUBHUS
);
8513 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULHS
);
8514 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULHU
);
8515 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULXHS
);
8516 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULXHU
);
8517 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMACHS
);
8518 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMACHU
);
8519 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMRDHS
);
8520 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMRDHU
);
8521 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQADDHSS
);
8522 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQADDHUS
);
8523 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSUBHSS
);
8524 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQSUBHUS
);
8525 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULHS
);
8526 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULHU
);
8527 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULXHS
);
8528 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULXHU
);
8529 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACHS
);
8530 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMACHU
);
8531 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXRS
);
8532 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXRU
);
8533 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXIS
);
8534 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXIU
);
8535 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXRS
);
8536 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXRU
);
8537 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXIS
);
8538 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXIU
);
8539 def_builtin ("__MCUT", uw1_ftype_acc_uw1
, FRV_BUILTIN_MCUT
);
8540 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1
, FRV_BUILTIN_MCUTSS
);
8541 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int
, FRV_BUILTIN_MEXPDHW
);
8542 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int
, FRV_BUILTIN_MEXPDHD
);
8543 def_builtin ("__MPACKH", uw1_ftype_uh_uh
, FRV_BUILTIN_MPACKH
);
8544 def_builtin ("__MUNPACKH", uw2_ftype_uw1
, FRV_BUILTIN_MUNPACKH
);
8545 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh
, FRV_BUILTIN_MDPACKH
);
8546 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2
, FRV_BUILTIN_MDUNPACKH
);
8547 def_builtin ("__MBTOH", uw2_ftype_uw1
, FRV_BUILTIN_MBTOH
);
8548 def_builtin ("__MHTOB", uw1_ftype_uw2
, FRV_BUILTIN_MHTOB
);
8549 def_builtin ("__MBTOHE", void_ftype_uw4_uw1
, FRV_BUILTIN_MBTOHE
);
8550 def_builtin ("__MCLRACC", void_ftype_acc
, FRV_BUILTIN_MCLRACC
);
8551 def_builtin ("__MCLRACCA", void_ftype_void
, FRV_BUILTIN_MCLRACCA
);
8552 def_builtin ("__MRDACC", uw1_ftype_acc
, FRV_BUILTIN_MRDACC
);
8553 def_builtin ("__MRDACCG", uw1_ftype_acc
, FRV_BUILTIN_MRDACCG
);
8554 def_builtin ("__MWTACC", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACC
);
8555 def_builtin ("__MWTACCG", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACCG
);
8556 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP1
);
8557 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP2
);
8558 def_builtin ("__MTRAP", void_ftype_void
, FRV_BUILTIN_MTRAP
);
8559 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACHS
);
8560 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACXHS
);
8561 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACXHS
);
8562 def_builtin ("__MADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MADDACCS
);
8563 def_builtin ("__MSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MSUBACCS
);
8564 def_builtin ("__MASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MASACCS
);
8565 def_builtin ("__MDADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDADDACCS
);
8566 def_builtin ("__MDSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDSUBACCS
);
8567 def_builtin ("__MDASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDASACCS
);
8568 def_builtin ("__MABSHS", uw1_ftype_sw1
, FRV_BUILTIN_MABSHS
);
8569 def_builtin ("__MDROTLI", uw2_ftype_uw2_int
, FRV_BUILTIN_MDROTLI
);
8570 def_builtin ("__MCPLHI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLHI
);
8571 def_builtin ("__MCPLI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLI
);
8572 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int
, FRV_BUILTIN_MDCUTSSI
);
8573 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSATHS
);
8574 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETLOS
);
8575 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETHIS
);
8576 def_builtin ("__MHDSETS", sw1_ftype_int
, FRV_BUILTIN_MHDSETS
);
8577 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETLOH
);
8578 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETHIH
);
8579 def_builtin ("__MHDSETH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHDSETH
);
8580 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQLCLRHS
);
8581 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQLMTHS
);
8582 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int
, FRV_BUILTIN_MQSLLHI
);
8583 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int
, FRV_BUILTIN_MQSRAHI
);
8584 def_builtin ("__SMUL", sw2_ftype_sw1_sw1
, FRV_BUILTIN_SMUL
);
8585 def_builtin ("__UMUL", uw2_ftype_uw1_uw1
, FRV_BUILTIN_UMUL
);
8586 def_builtin ("__SMASS", void_ftype_sw1_sw1
, FRV_BUILTIN_SMASS
);
8587 def_builtin ("__SMSSS", void_ftype_sw1_sw1
, FRV_BUILTIN_SMSSS
);
8588 def_builtin ("__SMU", void_ftype_sw1_sw1
, FRV_BUILTIN_SMU
);
8589 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_ADDSS
);
8590 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SUBSS
);
8591 def_builtin ("__SLASS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SLASS
);
8592 def_builtin ("__SCAN", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SCAN
);
8593 def_builtin ("__SCUTSS", sw1_ftype_sw1
, FRV_BUILTIN_SCUTSS
);
8594 def_builtin ("__IACCreadll", sw2_ftype_iacc
, FRV_BUILTIN_IACCreadll
);
8595 def_builtin ("__IACCreadl", sw1_ftype_iacc
, FRV_BUILTIN_IACCreadl
);
8596 def_builtin ("__IACCsetll", void_ftype_iacc_sw2
, FRV_BUILTIN_IACCsetll
);
8597 def_builtin ("__IACCsetl", void_ftype_iacc_sw1
, FRV_BUILTIN_IACCsetl
);
8598 def_builtin ("__data_prefetch0", void_ftype_ptr
, FRV_BUILTIN_PREFETCH0
);
8599 def_builtin ("__data_prefetch", void_ftype_ptr
, FRV_BUILTIN_PREFETCH
);
8600 def_builtin ("__builtin_read8", uw1_ftype_vptr
, FRV_BUILTIN_READ8
);
8601 def_builtin ("__builtin_read16", uw1_ftype_vptr
, FRV_BUILTIN_READ16
);
8602 def_builtin ("__builtin_read32", uw1_ftype_vptr
, FRV_BUILTIN_READ32
);
8603 def_builtin ("__builtin_read64", uw2_ftype_vptr
, FRV_BUILTIN_READ64
);
8605 def_builtin ("__builtin_write8", void_ftype_vptr_ub
, FRV_BUILTIN_WRITE8
);
8606 def_builtin ("__builtin_write16", void_ftype_vptr_uh
, FRV_BUILTIN_WRITE16
);
8607 def_builtin ("__builtin_write32", void_ftype_vptr_uw1
, FRV_BUILTIN_WRITE32
);
8608 def_builtin ("__builtin_write64", void_ftype_vptr_uw2
, FRV_BUILTIN_WRITE64
);
8616 /* Set the names for various arithmetic operations according to the
8619 frv_init_libfuncs (void)
8621 set_optab_libfunc (smod_optab
, SImode
, "__modi");
8622 set_optab_libfunc (umod_optab
, SImode
, "__umodi");
8624 set_optab_libfunc (add_optab
, DImode
, "__addll");
8625 set_optab_libfunc (sub_optab
, DImode
, "__subll");
8626 set_optab_libfunc (smul_optab
, DImode
, "__mulll");
8627 set_optab_libfunc (sdiv_optab
, DImode
, "__divll");
8628 set_optab_libfunc (smod_optab
, DImode
, "__modll");
8629 set_optab_libfunc (umod_optab
, DImode
, "__umodll");
8630 set_optab_libfunc (and_optab
, DImode
, "__andll");
8631 set_optab_libfunc (ior_optab
, DImode
, "__orll");
8632 set_optab_libfunc (xor_optab
, DImode
, "__xorll");
8633 set_optab_libfunc (one_cmpl_optab
, DImode
, "__notll");
8635 set_optab_libfunc (add_optab
, SFmode
, "__addf");
8636 set_optab_libfunc (sub_optab
, SFmode
, "__subf");
8637 set_optab_libfunc (smul_optab
, SFmode
, "__mulf");
8638 set_optab_libfunc (sdiv_optab
, SFmode
, "__divf");
8640 set_optab_libfunc (add_optab
, DFmode
, "__addd");
8641 set_optab_libfunc (sub_optab
, DFmode
, "__subd");
8642 set_optab_libfunc (smul_optab
, DFmode
, "__muld");
8643 set_optab_libfunc (sdiv_optab
, DFmode
, "__divd");
8645 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__ftod");
8646 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__dtof");
8648 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__ftoi");
8649 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
8650 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__dtoi");
8651 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
8653 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__ftoui");
8654 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
8655 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__dtoui");
8656 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
8658 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__itof");
8659 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__lltof");
8660 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__itod");
8661 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__lltod");
8664 /* Convert an integer constant to an accumulator register. ICODE is the
8665 code of the target instruction, OPNUM is the number of the
8666 accumulator operand and OPVAL is the constant integer. Try both
8667 ACC and ACCG registers; only report an error if neither fit the
8671 frv_int_to_acc (enum insn_code icode
, int opnum
, rtx opval
)
8676 /* ACCs and ACCGs are implicit global registers if media intrinsics
8677 are being used. We set up this lazily to avoid creating lots of
8678 unnecessary call_insn rtl in non-media code. */
8679 for (i
= 0; i
<= ACC_MASK
; i
++)
8680 if ((i
& ACC_MASK
) == i
)
8681 global_regs
[i
+ ACC_FIRST
] = global_regs
[i
+ ACCG_FIRST
] = 1;
8683 if (GET_CODE (opval
) != CONST_INT
)
8685 error ("accumulator is not a constant integer");
8688 if ((INTVAL (opval
) & ~ACC_MASK
) != 0)
8690 error ("accumulator number is out of bounds");
8694 reg
= gen_rtx_REG (insn_data
[icode
].operand
[opnum
].mode
,
8695 ACC_FIRST
+ INTVAL (opval
));
8696 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8697 SET_REGNO (reg
, ACCG_FIRST
+ INTVAL (opval
));
8699 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8701 error ("inappropriate accumulator for %qs", insn_data
[icode
].name
);
8707 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8710 static enum machine_mode
8711 frv_matching_accg_mode (enum machine_mode mode
)
8729 /* Given that a __builtin_read or __builtin_write function is accessing
8730 address ADDRESS, return the value that should be used as operand 1
8734 frv_io_address_cookie (rtx address
)
8736 return (GET_CODE (address
) == CONST_INT
8737 ? GEN_INT (INTVAL (address
) / 8 * 8)
8741 /* Return the accumulator guard that should be paired with accumulator
8742 register ACC. The mode of the returned register is in the same
8743 class as ACC, but is four times smaller. */
8746 frv_matching_accg_for_acc (rtx acc
)
8748 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc
)),
8749 REGNO (acc
) - ACC_FIRST
+ ACCG_FIRST
);
8752 /* Read the requested argument from the call EXP given by INDEX.
8753 Return the value as an rtx. */
8756 frv_read_argument (tree exp
, unsigned int index
)
8758 return expand_normal (CALL_EXPR_ARG (exp
, index
));
8761 /* Like frv_read_argument, but interpret the argument as the number
8762 of an IACC register and return a (reg:MODE ...) rtx for it. */
8765 frv_read_iacc_argument (enum machine_mode mode
, tree call
,
8771 op
= frv_read_argument (call
, index
);
8772 if (GET_CODE (op
) != CONST_INT
8774 || INTVAL (op
) > IACC_LAST
- IACC_FIRST
8775 || ((INTVAL (op
) * 4) & (GET_MODE_SIZE (mode
) - 1)) != 0)
8777 error ("invalid IACC argument");
8781 /* IACCs are implicit global registers. We set up this lazily to
8782 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8784 regno
= INTVAL (op
) + IACC_FIRST
;
8785 for (i
= 0; i
< HARD_REGNO_NREGS (regno
, mode
); i
++)
8786 global_regs
[regno
+ i
] = 1;
8788 return gen_rtx_REG (mode
, regno
);
8791 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8792 The instruction should require a constant operand of some sort. The
8793 function prints an error if OPVAL is not valid. */
8796 frv_check_constant_argument (enum insn_code icode
, int opnum
, rtx opval
)
8798 if (GET_CODE (opval
) != CONST_INT
)
8800 error ("%qs expects a constant argument", insn_data
[icode
].name
);
8803 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (opval
, VOIDmode
))
8805 error ("constant argument out of range for %qs", insn_data
[icode
].name
);
8811 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8812 if it's not null, has the right mode, and satisfies operand 0's
8816 frv_legitimize_target (enum insn_code icode
, rtx target
)
8818 enum machine_mode mode
= insn_data
[icode
].operand
[0].mode
;
8821 || GET_MODE (target
) != mode
8822 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode
))
8823 return gen_reg_rtx (mode
);
8828 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8829 check whether ARG satisfies the operand's constraints. If it doesn't,
8830 copy ARG to a temporary register and return that. Otherwise return ARG
8834 frv_legitimize_argument (enum insn_code icode
, int opnum
, rtx arg
)
8836 enum machine_mode mode
= insn_data
[icode
].operand
[opnum
].mode
;
8838 if ((*insn_data
[icode
].operand
[opnum
].predicate
) (arg
, mode
))
8841 return copy_to_mode_reg (mode
, arg
);
8844 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8847 frv_volatile_memref (enum machine_mode mode
, rtx arg
)
8851 mem
= gen_rtx_MEM (mode
, memory_address (mode
, arg
));
8852 MEM_VOLATILE_P (mem
) = 1;
8856 /* Expand builtins that take a single, constant argument. At the moment,
8857 only MHDSETS falls into this category. */
8860 frv_expand_set_builtin (enum insn_code icode
, tree call
, rtx target
)
8863 rtx op0
= frv_read_argument (call
, 0);
8865 if (! frv_check_constant_argument (icode
, 1, op0
))
8868 target
= frv_legitimize_target (icode
, target
);
8869 pat
= GEN_FCN (icode
) (target
, op0
);
8877 /* Expand builtins that take one operand. */
8880 frv_expand_unop_builtin (enum insn_code icode
, tree call
, rtx target
)
8883 rtx op0
= frv_read_argument (call
, 0);
8885 target
= frv_legitimize_target (icode
, target
);
8886 op0
= frv_legitimize_argument (icode
, 1, op0
);
8887 pat
= GEN_FCN (icode
) (target
, op0
);
8895 /* Expand builtins that take two operands. */
8898 frv_expand_binop_builtin (enum insn_code icode
, tree call
, rtx target
)
8901 rtx op0
= frv_read_argument (call
, 0);
8902 rtx op1
= frv_read_argument (call
, 1);
8904 target
= frv_legitimize_target (icode
, target
);
8905 op0
= frv_legitimize_argument (icode
, 1, op0
);
8906 op1
= frv_legitimize_argument (icode
, 2, op1
);
8907 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
8915 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8919 frv_expand_cut_builtin (enum insn_code icode
, tree call
, rtx target
)
8922 rtx op0
= frv_read_argument (call
, 0);
8923 rtx op1
= frv_read_argument (call
, 1);
8926 target
= frv_legitimize_target (icode
, target
);
8927 op0
= frv_int_to_acc (icode
, 1, op0
);
8931 if (icode
== CODE_FOR_mdcutssi
|| GET_CODE (op1
) == CONST_INT
)
8933 if (! frv_check_constant_argument (icode
, 2, op1
))
8937 op1
= frv_legitimize_argument (icode
, 2, op1
);
8939 op2
= frv_matching_accg_for_acc (op0
);
8940 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
8948 /* Expand builtins that take two operands and the second is immediate. */
8951 frv_expand_binopimm_builtin (enum insn_code icode
, tree call
, rtx target
)
8954 rtx op0
= frv_read_argument (call
, 0);
8955 rtx op1
= frv_read_argument (call
, 1);
8957 if (! frv_check_constant_argument (icode
, 2, op1
))
8960 target
= frv_legitimize_target (icode
, target
);
8961 op0
= frv_legitimize_argument (icode
, 1, op0
);
8962 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
8970 /* Expand builtins that take two operands, the first operand being a pointer to
8971 ints and return void. */
8974 frv_expand_voidbinop_builtin (enum insn_code icode
, tree call
)
8977 rtx op0
= frv_read_argument (call
, 0);
8978 rtx op1
= frv_read_argument (call
, 1);
8979 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
8982 if (GET_CODE (op0
) != MEM
)
8986 if (! offsettable_address_p (0, mode0
, op0
))
8988 reg
= gen_reg_rtx (Pmode
);
8989 emit_insn (gen_rtx_SET (VOIDmode
, reg
, op0
));
8992 op0
= gen_rtx_MEM (SImode
, reg
);
8995 addr
= XEXP (op0
, 0);
8996 if (! offsettable_address_p (0, mode0
, addr
))
8997 addr
= copy_to_mode_reg (Pmode
, op0
);
8999 op0
= change_address (op0
, V4SImode
, addr
);
9000 op1
= frv_legitimize_argument (icode
, 1, op1
);
9001 pat
= GEN_FCN (icode
) (op0
, op1
);
9009 /* Expand builtins that take two long operands and return void. */
9012 frv_expand_int_void2arg (enum insn_code icode
, tree call
)
9015 rtx op0
= frv_read_argument (call
, 0);
9016 rtx op1
= frv_read_argument (call
, 1);
9018 op0
= frv_legitimize_argument (icode
, 1, op0
);
9019 op1
= frv_legitimize_argument (icode
, 1, op1
);
9020 pat
= GEN_FCN (icode
) (op0
, op1
);
9028 /* Expand prefetch builtins. These take a single address as argument. */
9031 frv_expand_prefetches (enum insn_code icode
, tree call
)
9034 rtx op0
= frv_read_argument (call
, 0);
9036 pat
= GEN_FCN (icode
) (force_reg (Pmode
, op0
));
9044 /* Expand builtins that take three operands and return void. The first
9045 argument must be a constant that describes a pair or quad accumulators. A
9046 fourth argument is created that is the accumulator guard register that
9047 corresponds to the accumulator. */
9050 frv_expand_voidtriop_builtin (enum insn_code icode
, tree call
)
9053 rtx op0
= frv_read_argument (call
, 0);
9054 rtx op1
= frv_read_argument (call
, 1);
9055 rtx op2
= frv_read_argument (call
, 2);
9058 op0
= frv_int_to_acc (icode
, 0, op0
);
9062 op1
= frv_legitimize_argument (icode
, 1, op1
);
9063 op2
= frv_legitimize_argument (icode
, 2, op2
);
9064 op3
= frv_matching_accg_for_acc (op0
);
9065 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9073 /* Expand builtins that perform accumulator-to-accumulator operations.
9074 These builtins take two accumulator numbers as argument and return
9078 frv_expand_voidaccop_builtin (enum insn_code icode
, tree call
)
9081 rtx op0
= frv_read_argument (call
, 0);
9082 rtx op1
= frv_read_argument (call
, 1);
9086 op0
= frv_int_to_acc (icode
, 0, op0
);
9090 op1
= frv_int_to_acc (icode
, 1, op1
);
9094 op2
= frv_matching_accg_for_acc (op0
);
9095 op3
= frv_matching_accg_for_acc (op1
);
9096 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9104 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9105 membar and TARGET_MODE is the mode that the loaded value should have. */
9108 frv_expand_load_builtin (enum insn_code icode
, enum machine_mode target_mode
,
9109 tree call
, rtx target
)
9111 rtx op0
= frv_read_argument (call
, 0);
9112 rtx cookie
= frv_io_address_cookie (op0
);
9114 if (target
== 0 || !REG_P (target
))
9115 target
= gen_reg_rtx (target_mode
);
9116 op0
= frv_volatile_memref (insn_data
[icode
].operand
[0].mode
, op0
);
9117 convert_move (target
, op0
, 1);
9118 emit_insn (GEN_FCN (icode
) (copy_rtx (op0
), cookie
, GEN_INT (FRV_IO_READ
)));
9119 cfun
->machine
->has_membar_p
= 1;
9123 /* Likewise __builtin_write* functions. */
9126 frv_expand_store_builtin (enum insn_code icode
, tree call
)
9128 rtx op0
= frv_read_argument (call
, 0);
9129 rtx op1
= frv_read_argument (call
, 1);
9130 rtx cookie
= frv_io_address_cookie (op0
);
9132 op0
= frv_volatile_memref (insn_data
[icode
].operand
[0].mode
, op0
);
9133 convert_move (op0
, force_reg (insn_data
[icode
].operand
[0].mode
, op1
), 1);
9134 emit_insn (GEN_FCN (icode
) (copy_rtx (op0
), cookie
, GEN_INT (FRV_IO_WRITE
)));
9135 cfun
->machine
->has_membar_p
= 1;
9139 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9140 each argument forms one word of the two double-word input registers.
9141 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9142 to put the return value. */
9145 frv_expand_mdpackh_builtin (tree call
, rtx target
)
9147 enum insn_code icode
= CODE_FOR_mdpackh
;
9149 rtx arg1
= frv_read_argument (call
, 0);
9150 rtx arg2
= frv_read_argument (call
, 1);
9151 rtx arg3
= frv_read_argument (call
, 2);
9152 rtx arg4
= frv_read_argument (call
, 3);
9154 target
= frv_legitimize_target (icode
, target
);
9155 op0
= gen_reg_rtx (DImode
);
9156 op1
= gen_reg_rtx (DImode
);
9158 /* The high half of each word is not explicitly initialized, so indicate
9159 that the input operands are not live before this point. */
9163 /* Move each argument into the low half of its associated input word. */
9164 emit_move_insn (simplify_gen_subreg (HImode
, op0
, DImode
, 2), arg1
);
9165 emit_move_insn (simplify_gen_subreg (HImode
, op0
, DImode
, 6), arg2
);
9166 emit_move_insn (simplify_gen_subreg (HImode
, op1
, DImode
, 2), arg3
);
9167 emit_move_insn (simplify_gen_subreg (HImode
, op1
, DImode
, 6), arg4
);
9169 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
9177 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9178 number as argument. */
9181 frv_expand_mclracc_builtin (tree call
)
9183 enum insn_code icode
= CODE_FOR_mclracc
;
9185 rtx op0
= frv_read_argument (call
, 0);
9187 op0
= frv_int_to_acc (icode
, 0, op0
);
9191 pat
= GEN_FCN (icode
) (op0
);
9198 /* Expand builtins that take no arguments. */
9201 frv_expand_noargs_builtin (enum insn_code icode
)
9203 rtx pat
= GEN_FCN (icode
) (const0_rtx
);
9210 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9211 number or accumulator guard number as argument and return an SI integer. */
9214 frv_expand_mrdacc_builtin (enum insn_code icode
, tree call
)
9217 rtx target
= gen_reg_rtx (SImode
);
9218 rtx op0
= frv_read_argument (call
, 0);
9220 op0
= frv_int_to_acc (icode
, 1, op0
);
9224 pat
= GEN_FCN (icode
) (target
, op0
);
9232 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9233 accumulator guard as their first argument and an SImode value as their
9237 frv_expand_mwtacc_builtin (enum insn_code icode
, tree call
)
9240 rtx op0
= frv_read_argument (call
, 0);
9241 rtx op1
= frv_read_argument (call
, 1);
9243 op0
= frv_int_to_acc (icode
, 0, op0
);
9247 op1
= frv_legitimize_argument (icode
, 1, op1
);
9248 pat
= GEN_FCN (icode
) (op0
, op1
);
9255 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9256 to move DImode values into and out of IACC0. */
9259 frv_split_iacc_move (rtx dest
, rtx src
)
9261 enum machine_mode inner
;
9264 inner
= GET_MODE (dest
);
9265 for (i
= 0; i
< GET_MODE_SIZE (inner
); i
+= GET_MODE_SIZE (SImode
))
9266 emit_move_insn (simplify_gen_subreg (SImode
, dest
, inner
, i
),
9267 simplify_gen_subreg (SImode
, src
, inner
, i
));
9270 /* Expand builtins. */
9273 frv_expand_builtin (tree exp
,
9275 rtx subtarget ATTRIBUTE_UNUSED
,
9276 enum machine_mode mode ATTRIBUTE_UNUSED
,
9277 int ignore ATTRIBUTE_UNUSED
)
9279 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9280 unsigned fcode
= (unsigned)DECL_FUNCTION_CODE (fndecl
);
9282 struct builtin_description
*d
;
9284 if (fcode
< FRV_BUILTIN_FIRST_NONMEDIA
&& !TARGET_MEDIA
)
9286 error ("media functions are not available unless -mmedia is used");
9292 case FRV_BUILTIN_MCOP1
:
9293 case FRV_BUILTIN_MCOP2
:
9294 case FRV_BUILTIN_MDUNPACKH
:
9295 case FRV_BUILTIN_MBTOHE
:
9296 if (! TARGET_MEDIA_REV1
)
9298 error ("this media function is only available on the fr500");
9303 case FRV_BUILTIN_MQXMACHS
:
9304 case FRV_BUILTIN_MQXMACXHS
:
9305 case FRV_BUILTIN_MQMACXHS
:
9306 case FRV_BUILTIN_MADDACCS
:
9307 case FRV_BUILTIN_MSUBACCS
:
9308 case FRV_BUILTIN_MASACCS
:
9309 case FRV_BUILTIN_MDADDACCS
:
9310 case FRV_BUILTIN_MDSUBACCS
:
9311 case FRV_BUILTIN_MDASACCS
:
9312 case FRV_BUILTIN_MABSHS
:
9313 case FRV_BUILTIN_MDROTLI
:
9314 case FRV_BUILTIN_MCPLHI
:
9315 case FRV_BUILTIN_MCPLI
:
9316 case FRV_BUILTIN_MDCUTSSI
:
9317 case FRV_BUILTIN_MQSATHS
:
9318 case FRV_BUILTIN_MHSETLOS
:
9319 case FRV_BUILTIN_MHSETLOH
:
9320 case FRV_BUILTIN_MHSETHIS
:
9321 case FRV_BUILTIN_MHSETHIH
:
9322 case FRV_BUILTIN_MHDSETS
:
9323 case FRV_BUILTIN_MHDSETH
:
9324 if (! TARGET_MEDIA_REV2
)
9326 error ("this media function is only available on the fr400"
9332 case FRV_BUILTIN_SMASS
:
9333 case FRV_BUILTIN_SMSSS
:
9334 case FRV_BUILTIN_SMU
:
9335 case FRV_BUILTIN_ADDSS
:
9336 case FRV_BUILTIN_SUBSS
:
9337 case FRV_BUILTIN_SLASS
:
9338 case FRV_BUILTIN_SCUTSS
:
9339 case FRV_BUILTIN_IACCreadll
:
9340 case FRV_BUILTIN_IACCreadl
:
9341 case FRV_BUILTIN_IACCsetll
:
9342 case FRV_BUILTIN_IACCsetl
:
9343 if (!TARGET_FR405_BUILTINS
)
9345 error ("this builtin function is only available"
9346 " on the fr405 and fr450");
9351 case FRV_BUILTIN_PREFETCH
:
9352 if (!TARGET_FR500_FR550_BUILTINS
)
9354 error ("this builtin function is only available on the fr500"
9360 case FRV_BUILTIN_MQLCLRHS
:
9361 case FRV_BUILTIN_MQLMTHS
:
9362 case FRV_BUILTIN_MQSLLHI
:
9363 case FRV_BUILTIN_MQSRAHI
:
9364 if (!TARGET_MEDIA_FR450
)
9366 error ("this builtin function is only available on the fr450");
9375 /* Expand unique builtins. */
9379 case FRV_BUILTIN_MTRAP
:
9380 return frv_expand_noargs_builtin (CODE_FOR_mtrap
);
9382 case FRV_BUILTIN_MCLRACC
:
9383 return frv_expand_mclracc_builtin (exp
);
9385 case FRV_BUILTIN_MCLRACCA
:
9387 return frv_expand_noargs_builtin (CODE_FOR_mclracca8
);
9389 return frv_expand_noargs_builtin (CODE_FOR_mclracca4
);
9391 case FRV_BUILTIN_MRDACC
:
9392 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc
, exp
);
9394 case FRV_BUILTIN_MRDACCG
:
9395 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg
, exp
);
9397 case FRV_BUILTIN_MWTACC
:
9398 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc
, exp
);
9400 case FRV_BUILTIN_MWTACCG
:
9401 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg
, exp
);
9403 case FRV_BUILTIN_MDPACKH
:
9404 return frv_expand_mdpackh_builtin (exp
, target
);
9406 case FRV_BUILTIN_IACCreadll
:
9408 rtx src
= frv_read_iacc_argument (DImode
, exp
, 0);
9409 if (target
== 0 || !REG_P (target
))
9410 target
= gen_reg_rtx (DImode
);
9411 frv_split_iacc_move (target
, src
);
9415 case FRV_BUILTIN_IACCreadl
:
9416 return frv_read_iacc_argument (SImode
, exp
, 0);
9418 case FRV_BUILTIN_IACCsetll
:
9420 rtx dest
= frv_read_iacc_argument (DImode
, exp
, 0);
9421 rtx src
= frv_read_argument (exp
, 1);
9422 frv_split_iacc_move (dest
, force_reg (DImode
, src
));
9426 case FRV_BUILTIN_IACCsetl
:
9428 rtx dest
= frv_read_iacc_argument (SImode
, exp
, 0);
9429 rtx src
= frv_read_argument (exp
, 1);
9430 emit_move_insn (dest
, force_reg (SImode
, src
));
9438 /* Expand groups of builtins. */
9440 for (i
= 0, d
= bdesc_set
; i
< ARRAY_SIZE (bdesc_set
); i
++, d
++)
9441 if (d
->code
== fcode
)
9442 return frv_expand_set_builtin (d
->icode
, exp
, target
);
9444 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
9445 if (d
->code
== fcode
)
9446 return frv_expand_unop_builtin (d
->icode
, exp
, target
);
9448 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
9449 if (d
->code
== fcode
)
9450 return frv_expand_binop_builtin (d
->icode
, exp
, target
);
9452 for (i
= 0, d
= bdesc_cut
; i
< ARRAY_SIZE (bdesc_cut
); i
++, d
++)
9453 if (d
->code
== fcode
)
9454 return frv_expand_cut_builtin (d
->icode
, exp
, target
);
9456 for (i
= 0, d
= bdesc_2argimm
; i
< ARRAY_SIZE (bdesc_2argimm
); i
++, d
++)
9457 if (d
->code
== fcode
)
9458 return frv_expand_binopimm_builtin (d
->icode
, exp
, target
);
9460 for (i
= 0, d
= bdesc_void2arg
; i
< ARRAY_SIZE (bdesc_void2arg
); i
++, d
++)
9461 if (d
->code
== fcode
)
9462 return frv_expand_voidbinop_builtin (d
->icode
, exp
);
9464 for (i
= 0, d
= bdesc_void3arg
; i
< ARRAY_SIZE (bdesc_void3arg
); i
++, d
++)
9465 if (d
->code
== fcode
)
9466 return frv_expand_voidtriop_builtin (d
->icode
, exp
);
9468 for (i
= 0, d
= bdesc_voidacc
; i
< ARRAY_SIZE (bdesc_voidacc
); i
++, d
++)
9469 if (d
->code
== fcode
)
9470 return frv_expand_voidaccop_builtin (d
->icode
, exp
);
9472 for (i
= 0, d
= bdesc_int_void2arg
;
9473 i
< ARRAY_SIZE (bdesc_int_void2arg
); i
++, d
++)
9474 if (d
->code
== fcode
)
9475 return frv_expand_int_void2arg (d
->icode
, exp
);
9477 for (i
= 0, d
= bdesc_prefetches
;
9478 i
< ARRAY_SIZE (bdesc_prefetches
); i
++, d
++)
9479 if (d
->code
== fcode
)
9480 return frv_expand_prefetches (d
->icode
, exp
);
9482 for (i
= 0, d
= bdesc_loads
; i
< ARRAY_SIZE (bdesc_loads
); i
++, d
++)
9483 if (d
->code
== fcode
)
9484 return frv_expand_load_builtin (d
->icode
, TYPE_MODE (TREE_TYPE (exp
)),
9487 for (i
= 0, d
= bdesc_stores
; i
< ARRAY_SIZE (bdesc_stores
); i
++, d
++)
9488 if (d
->code
== fcode
)
9489 return frv_expand_store_builtin (d
->icode
, exp
);
9495 frv_in_small_data_p (const_tree decl
)
9498 const_tree section_name
;
9500 /* Don't apply the -G flag to internal compiler structures. We
9501 should leave such structures in the main data section, partly
9502 for efficiency and partly because the size of some of them
9503 (such as C++ typeinfos) is not known until later. */
9504 if (TREE_CODE (decl
) != VAR_DECL
|| DECL_ARTIFICIAL (decl
))
9507 /* If we already know which section the decl should be in, see if
9508 it's a small data section. */
9509 section_name
= DECL_SECTION_NAME (decl
);
9512 gcc_assert (TREE_CODE (section_name
) == STRING_CST
);
9513 if (frv_string_begins_with (section_name
, ".sdata"))
9515 if (frv_string_begins_with (section_name
, ".sbss"))
9520 size
= int_size_in_bytes (TREE_TYPE (decl
));
9521 if (size
> 0 && size
<= g_switch_value
)
9528 frv_rtx_costs (rtx x
,
9529 int code ATTRIBUTE_UNUSED
,
9530 int outer_code ATTRIBUTE_UNUSED
,
9531 int opno ATTRIBUTE_UNUSED
,
9533 bool speed ATTRIBUTE_UNUSED
)
9535 if (outer_code
== MEM
)
9537 /* Don't differentiate between memory addresses. All the ones
9538 we accept have equal cost. */
9539 *total
= COSTS_N_INSNS (0);
9546 /* Make 12-bit integers really cheap. */
9547 if (IN_RANGE (INTVAL (x
), -2048, 2047))
9558 *total
= COSTS_N_INSNS (2);
9572 if (GET_MODE (x
) == SImode
)
9573 *total
= COSTS_N_INSNS (1);
9574 else if (GET_MODE (x
) == DImode
)
9575 *total
= COSTS_N_INSNS (2);
9577 *total
= COSTS_N_INSNS (3);
9581 if (GET_MODE (x
) == SImode
)
9582 *total
= COSTS_N_INSNS (2);
9584 *total
= COSTS_N_INSNS (6); /* guess */
9591 *total
= COSTS_N_INSNS (18);
9595 *total
= COSTS_N_INSNS (3);
9604 frv_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9606 switch_to_section (ctors_section
);
9607 assemble_align (POINTER_SIZE
);
9610 int ok
= frv_assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, 1);
9615 assemble_integer_with_op ("\t.picptr\t", symbol
);
9619 frv_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9621 switch_to_section (dtors_section
);
9622 assemble_align (POINTER_SIZE
);
9625 int ok
= frv_assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, 1);
9630 assemble_integer_with_op ("\t.picptr\t", symbol
);
9633 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9636 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
9637 int incoming ATTRIBUTE_UNUSED
)
9639 return gen_rtx_REG (Pmode
, FRV_STRUCT_VALUE_REGNUM
);
9642 #define TLS_BIAS (2048 - 16)
9644 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9645 We need to emit DTP-relative relocations. */
9648 frv_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
9650 gcc_assert (size
== 4);
9651 fputs ("\t.picptr\ttlsmoff(", file
);
9652 /* We want the unbiased TLS offset, so add the bias to the
9653 expression, such that the implicit biasing cancels out. */
9654 output_addr_const (file
, plus_constant (Pmode
, x
, TLS_BIAS
));