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Update Copyright years for files modified in 2011 and/or 2012.
[official-gcc.git] / gcc / config / bfin / bfin.h
blob14472fb0cc397e757af953c037c5bbeb5b9167a0
1 /* Definitions for the Blackfin port.
2 Copyright (C) 2005, 2007, 2008, 2009, 2010, 2011, 2012
3 Free Software Foundation, Inc.
4 Contributed by Analog Devices.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 3, or (at your
11 option) any later version.
12
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #ifndef _BFIN_CONFIG
23 #define _BFIN_CONFIG
24
25 #ifndef BFIN_OPTS_H
26 #include "config/bfin/bfin-opts.h"
27 #endif
28
29 #define OBJECT_FORMAT_ELF
30
31 #define BRT 1
32 #define BRF 0
33
34 /* Predefinition in the preprocessor for this target machine */
35 #ifndef TARGET_CPU_CPP_BUILTINS
36 #define TARGET_CPU_CPP_BUILTINS() \
37 do \
38 { \
39 builtin_define_std ("bfin"); \
40 builtin_define_std ("BFIN"); \
41 builtin_define ("__ADSPBLACKFIN__"); \
42 builtin_define ("__ADSPLPBLACKFIN__"); \
43 \
44 switch (bfin_cpu_type) \
45 { \
46 case BFIN_CPU_BF512: \
47 builtin_define ("__ADSPBF512__"); \
48 builtin_define ("__ADSPBF51x__"); \
49 break; \
50 case BFIN_CPU_BF514: \
51 builtin_define ("__ADSPBF514__"); \
52 builtin_define ("__ADSPBF51x__"); \
53 break; \
54 case BFIN_CPU_BF516: \
55 builtin_define ("__ADSPBF516__"); \
56 builtin_define ("__ADSPBF51x__"); \
57 break; \
58 case BFIN_CPU_BF518: \
59 builtin_define ("__ADSPBF518__"); \
60 builtin_define ("__ADSPBF51x__"); \
61 break; \
62 case BFIN_CPU_BF522: \
63 builtin_define ("__ADSPBF522__"); \
64 builtin_define ("__ADSPBF52x__"); \
65 break; \
66 case BFIN_CPU_BF523: \
67 builtin_define ("__ADSPBF523__"); \
68 builtin_define ("__ADSPBF52x__"); \
69 break; \
70 case BFIN_CPU_BF524: \
71 builtin_define ("__ADSPBF524__"); \
72 builtin_define ("__ADSPBF52x__"); \
73 break; \
74 case BFIN_CPU_BF525: \
75 builtin_define ("__ADSPBF525__"); \
76 builtin_define ("__ADSPBF52x__"); \
77 break; \
78 case BFIN_CPU_BF526: \
79 builtin_define ("__ADSPBF526__"); \
80 builtin_define ("__ADSPBF52x__"); \
81 break; \
82 case BFIN_CPU_BF527: \
83 builtin_define ("__ADSPBF527__"); \
84 builtin_define ("__ADSPBF52x__"); \
85 break; \
86 case BFIN_CPU_BF531: \
87 builtin_define ("__ADSPBF531__"); \
88 break; \
89 case BFIN_CPU_BF532: \
90 builtin_define ("__ADSPBF532__"); \
91 break; \
92 case BFIN_CPU_BF533: \
93 builtin_define ("__ADSPBF533__"); \
94 break; \
95 case BFIN_CPU_BF534: \
96 builtin_define ("__ADSPBF534__"); \
97 break; \
98 case BFIN_CPU_BF536: \
99 builtin_define ("__ADSPBF536__"); \
100 break; \
101 case BFIN_CPU_BF537: \
102 builtin_define ("__ADSPBF537__"); \
103 break; \
104 case BFIN_CPU_BF538: \
105 builtin_define ("__ADSPBF538__"); \
106 break; \
107 case BFIN_CPU_BF539: \
108 builtin_define ("__ADSPBF539__"); \
109 break; \
110 case BFIN_CPU_BF542M: \
111 builtin_define ("__ADSPBF542M__"); \
112 case BFIN_CPU_BF542: \
113 builtin_define ("__ADSPBF542__"); \
114 builtin_define ("__ADSPBF54x__"); \
115 break; \
116 case BFIN_CPU_BF544M: \
117 builtin_define ("__ADSPBF544M__"); \
118 case BFIN_CPU_BF544: \
119 builtin_define ("__ADSPBF544__"); \
120 builtin_define ("__ADSPBF54x__"); \
121 break; \
122 case BFIN_CPU_BF547M: \
123 builtin_define ("__ADSPBF547M__"); \
124 case BFIN_CPU_BF547: \
125 builtin_define ("__ADSPBF547__"); \
126 builtin_define ("__ADSPBF54x__"); \
127 break; \
128 case BFIN_CPU_BF548M: \
129 builtin_define ("__ADSPBF548M__"); \
130 case BFIN_CPU_BF548: \
131 builtin_define ("__ADSPBF548__"); \
132 builtin_define ("__ADSPBF54x__"); \
133 break; \
134 case BFIN_CPU_BF549M: \
135 builtin_define ("__ADSPBF549M__"); \
136 case BFIN_CPU_BF549: \
137 builtin_define ("__ADSPBF549__"); \
138 builtin_define ("__ADSPBF54x__"); \
139 break; \
140 case BFIN_CPU_BF561: \
141 builtin_define ("__ADSPBF561__"); \
142 break; \
143 case BFIN_CPU_BF592: \
144 builtin_define ("__ADSPBF592__"); \
145 builtin_define ("__ADSPBF59x__"); \
146 break; \
147 } \
148 \
149 if (bfin_si_revision != -1) \
150 { \
151 /* space of 0xnnnn and a NUL */ \
152 char *buf = XALLOCAVEC (char, 7); \
153 \
154 sprintf (buf, "0x%04x", bfin_si_revision); \
155 builtin_define_with_value ("__SILICON_REVISION__", buf, 0); \
156 } \
157 \
158 if (bfin_workarounds) \
159 builtin_define ("__WORKAROUNDS_ENABLED"); \
160 if (ENABLE_WA_SPECULATIVE_LOADS) \
161 builtin_define ("__WORKAROUND_SPECULATIVE_LOADS"); \
162 if (ENABLE_WA_SPECULATIVE_SYNCS) \
163 builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS"); \
164 if (ENABLE_WA_INDIRECT_CALLS) \
165 builtin_define ("__WORKAROUND_INDIRECT_CALLS"); \
166 if (ENABLE_WA_RETS) \
167 builtin_define ("__WORKAROUND_RETS"); \
168 \
169 if (TARGET_FDPIC) \
170 { \
171 builtin_define ("__BFIN_FDPIC__"); \
172 builtin_define ("__FDPIC__"); \
173 } \
174 if (TARGET_ID_SHARED_LIBRARY \
175 && !TARGET_SEP_DATA) \
176 builtin_define ("__ID_SHARED_LIB__"); \
177 if (flag_no_builtin) \
178 builtin_define ("__NO_BUILTIN"); \
179 if (TARGET_MULTICORE) \
180 builtin_define ("__BFIN_MULTICORE"); \
181 if (TARGET_COREA) \
182 builtin_define ("__BFIN_COREA"); \
183 if (TARGET_COREB) \
184 builtin_define ("__BFIN_COREB"); \
185 if (TARGET_SDRAM) \
186 builtin_define ("__BFIN_SDRAM"); \
187 } \
188 while (0)
189 #endif
190
191 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\
192 %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \
193 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
194 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \
195 "
196 #ifndef SUBTARGET_DRIVER_SELF_SPECS
197 # define SUBTARGET_DRIVER_SELF_SPECS
198 #endif
199
200 #define LINK_GCC_C_SEQUENCE_SPEC "\
201 %{mfast-fp:-lbffastfp} %G %L %{mfast-fp:-lbffastfp} %G \
202 "
203
204 #undef ASM_SPEC
205 #define ASM_SPEC "\
206 %{mno-fdpic:-mnopic} %{mfdpic}"
207
208 #define LINK_SPEC "\
209 %{h*} %{v:-V} \
210 %{mfdpic:-melf32bfinfd -z text} \
211 %{static:-dn -Bstatic} \
212 %{shared:-G -Bdynamic} \
213 %{symbolic:-Bsymbolic} \
214 -init __init -fini __fini "
215
216 /* Generate DSP instructions, like DSP halfword loads */
217 #define TARGET_DSP (1)
218
219 #define TARGET_DEFAULT 0
220
221 /* Maximum number of library ids we permit */
222 #define MAX_LIBRARY_ID 255
223
224 extern const char *bfin_library_id_string;
225
226 #define FUNCTION_MODE SImode
227 #define Pmode SImode
228
229 /* store-condition-codes instructions store 0 for false
230 This is the value stored for true. */
231 #define STORE_FLAG_VALUE 1
232
233 /* Define this if pushing a word on the stack
234 makes the stack pointer a smaller address. */
235 #define STACK_GROWS_DOWNWARD
236
237 #define STACK_PUSH_CODE PRE_DEC
238
239 /* Define this to nonzero if the nominal address of the stack frame
240 is at the high-address end of the local variables;
241 that is, each additional local variable allocated
242 goes at a more negative offset in the frame. */
243 #define FRAME_GROWS_DOWNWARD 1
244
245 /* We define a dummy ARGP register; the parameters start at offset 0 from
246 it. */
247 #define FIRST_PARM_OFFSET(DECL) 0
248
249 /* Offset within stack frame to start allocating local variables at.
250 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
251 first local allocated. Otherwise, it is the offset to the BEGINNING
252 of the first local allocated. */
253 #define STARTING_FRAME_OFFSET 0
254
255 /* Register to use for pushing function arguments. */
256 #define STACK_POINTER_REGNUM REG_P6
257
258 /* Base register for access to local variables of the function. */
259 #define FRAME_POINTER_REGNUM REG_P7
260
261 /* A dummy register that will be eliminated to either FP or SP. */
262 #define ARG_POINTER_REGNUM REG_ARGP
263
264 /* `PIC_OFFSET_TABLE_REGNUM'
265 The register number of the register used to address a table of
266 static data addresses in memory. In some cases this register is
267 defined by a processor's "application binary interface" (ABI).
268 When this macro is defined, RTL is generated for this register
269 once, as with the stack pointer and frame pointer registers. If
270 this macro is not defined, it is up to the machine-dependent files
271 to allocate such a register (if necessary). */
272 #define PIC_OFFSET_TABLE_REGNUM (REG_P5)
273
274 #define FDPIC_FPTR_REGNO REG_P1
275 #define FDPIC_REGNO REG_P3
276 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
277
278 /* A static chain register for nested functions. We need to use a
279 call-clobbered register for this. */
280 #define STATIC_CHAIN_REGNUM REG_P2
281
282 /* Define this if functions should assume that stack space has been
283 allocated for arguments even when their values are passed in
284 registers.
285
286 The value of this macro is the size, in bytes, of the area reserved for
287 arguments passed in registers.
288
289 This space can either be allocated by the caller or be a part of the
290 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
291 says which. */
292 #define FIXED_STACK_AREA 12
293 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA
294
295 /* Define this if the above stack space is to be considered part of the
296 * space allocated by the caller. */
297 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
298
299 /* Define this if the maximum size of all the outgoing args is to be
300 accumulated and pushed during the prologue. The amount can be
301 found in the variable crtl->outgoing_args_size. */
302 #define ACCUMULATE_OUTGOING_ARGS 1
303
304 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */
305
306 /* If defined, a C expression to compute the alignment for a local
307 variable. TYPE is the data type, and ALIGN is the alignment that
308 the object would ordinarily have. The value of this macro is used
309 instead of that alignment to align the object.
310
311 If this macro is not defined, then ALIGN is used.
312
313 One use of this macro is to increase alignment of medium-size
314 data to make it all fit in fewer cache lines. */
315
316 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN))
317
318 /* Make strings word-aligned so strcpy from constants will be faster. */
319 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
320 (TREE_CODE (EXP) == STRING_CST \
321 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
322
323 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18)
324 \f
325 /* Definitions for register eliminations.
326
327 This is an array of structures. Each structure initializes one pair
328 of eliminable registers. The "from" register number is given first,
329 followed by "to". Eliminations of the same "from" register are listed
330 in order of preference.
331
332 There are two registers that can always be eliminated on the i386.
333 The frame pointer and the arg pointer can be replaced by either the
334 hard frame pointer or to the stack pointer, depending upon the
335 circumstances. The hard frame pointer is not used before reload and
336 so it is not eligible for elimination. */
337
338 #define ELIMINABLE_REGS \
339 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
340 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
341 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \
342
343 /* Define the offset between two registers, one to be eliminated, and the other
344 its replacement, at the start of a routine. */
345
346 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
347 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO)))
348 \f
349 /* This processor has
350 8 data register for doing arithmetic
351 8 pointer register for doing addressing, including
352 1 stack pointer P6
353 1 frame pointer P7
354 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3)
355 1 condition code flag register CC
356 5 return address registers RETS/I/X/N/E
357 1 arithmetic status register (ASTAT). */
358
359 #define FIRST_PSEUDO_REGISTER 50
360
361 #define D_REGNO_P(X) ((X) <= REG_R7)
362 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7)
363 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3)
364 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X))
365 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3)
366 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
367 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X)))
368 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
369 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X)))
370
371 #define REGISTER_NAMES { \
372 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
373 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \
374 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \
375 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \
376 "A0", "A1", \
377 "CC", \
378 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \
379 "ARGP", \
380 "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \
381 }
382
383 #define SHORT_REGISTER_NAMES { \
384 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \
385 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \
386 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \
387 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", }
388
389 #define HIGH_REGISTER_NAMES { \
390 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \
391 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \
392 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \
393 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", }
394
395 #define DREGS_PAIR_NAMES { \
396 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, }
397
398 #define BYTE_REGISTER_NAMES { \
399 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", }
400
401
402 /* 1 for registers that have pervasive standard uses
403 and are not available for the register allocator. */
404
405 #define FIXED_REGISTERS \
406 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
407 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
408 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
409 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
410 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
411 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
412 /*lb0/1 */ \
413 1, 1 \
414 }
415
416 /* 1 for registers not available across function calls.
417 These must include the FIXED_REGISTERS and also any
418 registers that can be used without being saved.
419 The latter must include the registers where values are returned
420 and the register where structure-value addresses are passed.
421 Aside from that, you can include as many other registers as you like. */
422
423 #define CALL_USED_REGISTERS \
424 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
425 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \
426 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
427 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
428 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
429 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
430 /*lb0/1 */ \
431 1, 1 \
432 }
433
434 /* Order in which to allocate registers. Each register must be
435 listed once, even those in FIXED_REGISTERS. List frame pointer
436 late and fixed registers last. Note that, in general, we prefer
437 registers listed in CALL_USED_REGISTERS, keeping the others
438 available for storage of persistent values. */
439
440 #define REG_ALLOC_ORDER \
441 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \
442 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \
443 REG_A0, REG_A1, \
444 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \
445 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \
446 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \
447 REG_ASTAT, REG_SEQSTAT, REG_USP, \
448 REG_CC, REG_ARGP, \
449 REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \
450 }
451
452 /* Define the classes of registers for register constraints in the
453 machine description. Also define ranges of constants.
454
455 One of the classes must always be named ALL_REGS and include all hard regs.
456 If there is more than one class, another class must be named NO_REGS
457 and contain no registers.
458
459 The name GENERAL_REGS must be the name of a class (or an alias for
460 another name such as ALL_REGS). This is the class of registers
461 that is allowed by "g" or "r" in a register constraint.
462 Also, registers outside this class are allocated only when
463 instructions express preferences for them.
464
465 The classes must be numbered in nondecreasing order; that is,
466 a larger-numbered class must never be contained completely
467 in a smaller-numbered class.
468
469 For any two classes, it is very desirable that there be another
470 class that represents their union. */
471
472
473 enum reg_class
474 {
475 NO_REGS,
476 IREGS,
477 BREGS,
478 LREGS,
479 MREGS,
480 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */
481 DAGREGS,
482 EVEN_AREGS,
483 ODD_AREGS,
484 AREGS,
485 CCREGS,
486 EVEN_DREGS,
487 ODD_DREGS,
488 D0REGS,
489 D1REGS,
490 D2REGS,
491 D3REGS,
492 D4REGS,
493 D5REGS,
494 D6REGS,
495 D7REGS,
496 DREGS,
497 P0REGS,
498 FDPIC_REGS,
499 FDPIC_FPTR_REGS,
500 PREGS_CLOBBERED,
501 PREGS,
502 IPREGS,
503 DPREGS,
504 MOST_REGS,
505 LT_REGS,
506 LC_REGS,
507 LB_REGS,
508 PROLOGUE_REGS,
509 NON_A_CC_REGS,
510 ALL_REGS, LIM_REG_CLASSES
511 };
512
513 #define N_REG_CLASSES ((int)LIM_REG_CLASSES)
514
515 #define GENERAL_REGS DPREGS
516
517 /* Give names of register classes as strings for dump file. */
518
519 #define REG_CLASS_NAMES \
520 { "NO_REGS", \
521 "IREGS", \
522 "BREGS", \
523 "LREGS", \
524 "MREGS", \
525 "CIRCREGS", \
526 "DAGREGS", \
527 "EVEN_AREGS", \
528 "ODD_AREGS", \
529 "AREGS", \
530 "CCREGS", \
531 "EVEN_DREGS", \
532 "ODD_DREGS", \
533 "D0REGS", \
534 "D1REGS", \
535 "D2REGS", \
536 "D3REGS", \
537 "D4REGS", \
538 "D5REGS", \
539 "D6REGS", \
540 "D7REGS", \
541 "DREGS", \
542 "P0REGS", \
543 "FDPIC_REGS", \
544 "FDPIC_FPTR_REGS", \
545 "PREGS_CLOBBERED", \
546 "PREGS", \
547 "IPREGS", \
548 "DPREGS", \
549 "MOST_REGS", \
550 "LT_REGS", \
551 "LC_REGS", \
552 "LB_REGS", \
553 "PROLOGUE_REGS", \
554 "NON_A_CC_REGS", \
555 "ALL_REGS" }
556
557 /* An initializer containing the contents of the register classes, as integers
558 which are bit masks. The Nth integer specifies the contents of class N.
559 The way the integer MASK is interpreted is that register R is in the class
560 if `MASK & (1 << R)' is 1.
561
562 When the machine has more than 32 registers, an integer does not suffice.
563 Then the integers are replaced by sub-initializers, braced groupings
564 containing several integers. Each sub-initializer must be suitable as an
565 initializer for the type `HARD_REG_SET' which is defined in
566 `hard-reg-set.h'. */
567
568 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use
569 MOST_REGS as the union of DPREGS and DAGREGS. */
570
571 #define REG_CLASS_CONTENTS \
572 /* 31 - 0 63-32 */ \
573 { { 0x00000000, 0 }, /* NO_REGS */ \
574 { 0x000f0000, 0 }, /* IREGS */ \
575 { 0x00f00000, 0 }, /* BREGS */ \
576 { 0x0f000000, 0 }, /* LREGS */ \
577 { 0xf0000000, 0 }, /* MREGS */ \
578 { 0x0fff0000, 0 }, /* CIRCREGS */ \
579 { 0xffff0000, 0 }, /* DAGREGS */ \
580 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \
581 { 0x00000000, 0x2 }, /* ODD_AREGS */ \
582 { 0x00000000, 0x3 }, /* AREGS */ \
583 { 0x00000000, 0x4 }, /* CCREGS */ \
584 { 0x00000055, 0 }, /* EVEN_DREGS */ \
585 { 0x000000aa, 0 }, /* ODD_DREGS */ \
586 { 0x00000001, 0 }, /* D0REGS */ \
587 { 0x00000002, 0 }, /* D1REGS */ \
588 { 0x00000004, 0 }, /* D2REGS */ \
589 { 0x00000008, 0 }, /* D3REGS */ \
590 { 0x00000010, 0 }, /* D4REGS */ \
591 { 0x00000020, 0 }, /* D5REGS */ \
592 { 0x00000040, 0 }, /* D6REGS */ \
593 { 0x00000080, 0 }, /* D7REGS */ \
594 { 0x000000ff, 0 }, /* DREGS */ \
595 { 0x00000100, 0x000 }, /* P0REGS */ \
596 { 0x00000800, 0x000 }, /* FDPIC_REGS */ \
597 { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \
598 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \
599 { 0x0000ff00, 0x800 }, /* PREGS */ \
600 { 0x000fff00, 0x800 }, /* IPREGS */ \
601 { 0x0000ffff, 0x800 }, /* DPREGS */ \
602 { 0xffffffff, 0x800 }, /* MOST_REGS */\
603 { 0x00000000, 0x3000 }, /* LT_REGS */\
604 { 0x00000000, 0xc000 }, /* LC_REGS */\
605 { 0x00000000, 0x30000 }, /* LB_REGS */\
606 { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\
607 { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\
608 { 0xffffffff, 0x3ffff }} /* ALL_REGS */
609
610 #define IREG_POSSIBLE_P(OUTER) \
611 ((OUTER) == POST_INC || (OUTER) == PRE_INC \
612 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \
613 || (OUTER) == MEM || (OUTER) == ADDRESS)
614
615 #define MODE_CODE_BASE_REG_CLASS(MODE, AS, OUTER, INDEX) \
616 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS)
617
618 #define INDEX_REG_CLASS PREGS
619
620 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \
621 (P_REGNO_P (X) || (X) == REG_ARGP \
622 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \
623 && I_REGNO_P (X)))
624
625 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \
626 ((X) >= FIRST_PSEUDO_REGISTER \
627 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX))
628
629 #ifdef REG_OK_STRICT
630 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \
631 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)
632 #else
633 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \
634 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX)
635 #endif
636
637 #define REGNO_OK_FOR_INDEX_P(X) 0
638
639 /* The same information, inverted:
640 Return the class number of the smallest class containing
641 reg number REGNO. This could be a conditional expression
642 or could index an array. */
643
644 #define REGNO_REG_CLASS(REGNO) \
645 ((REGNO) == REG_R0 ? D0REGS \
646 : (REGNO) == REG_R1 ? D1REGS \
647 : (REGNO) == REG_R2 ? D2REGS \
648 : (REGNO) == REG_R3 ? D3REGS \
649 : (REGNO) == REG_R4 ? D4REGS \
650 : (REGNO) == REG_R5 ? D5REGS \
651 : (REGNO) == REG_R6 ? D6REGS \
652 : (REGNO) == REG_R7 ? D7REGS \
653 : (REGNO) == REG_P0 ? P0REGS \
654 : (REGNO) < REG_I0 ? PREGS \
655 : (REGNO) == REG_ARGP ? PREGS \
656 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \
657 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \
658 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \
659 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \
660 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \
661 : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \
662 : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \
663 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \
664 : (REGNO) == REG_CC ? CCREGS \
665 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \
666 : NO_REGS)
667
668 /* When this hook returns true for MODE, the compiler allows
669 registers explicitly used in the rtl to be used as spill registers
670 but prevents the compiler from extending the lifetime of these
671 registers. */
672 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
673
674 /* Do not allow to store a value in REG_CC for any mode */
675 /* Do not allow to store value in pregs if mode is not SI*/
676 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
677
678 /* Return the maximum number of consecutive registers
679 needed to represent mode MODE in a register of class CLASS. */
680 #define CLASS_MAX_NREGS(CLASS, MODE) \
681 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \
682 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
683
684 #define HARD_REGNO_NREGS(REGNO, MODE) \
685 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \
686 : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \
687 : CLASS_MAX_NREGS (GENERAL_REGS, MODE))
688
689 /* A C expression that is nonzero if hard register TO can be
690 considered for use as a rename register for FROM register */
691 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO)
692
693 /* A C expression that is nonzero if it is desirable to choose
694 register allocation so as to avoid move instructions between a
695 value of mode MODE1 and a value of mode MODE2.
696
697 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
698 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
699 MODE2)' must be zero. */
700 #define MODES_TIEABLE_P(MODE1, MODE2) \
701 ((MODE1) == (MODE2) \
702 || ((GET_MODE_CLASS (MODE1) == MODE_INT \
703 || GET_MODE_CLASS (MODE1) == MODE_FLOAT) \
704 && (GET_MODE_CLASS (MODE2) == MODE_INT \
705 || GET_MODE_CLASS (MODE2) == MODE_FLOAT) \
706 && (MODE1) != BImode && (MODE2) != BImode \
707 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
708 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD))
709
710 /* `PREFERRED_RELOAD_CLASS (X, CLASS)'
711 A C expression that places additional restrictions on the register
712 class to use when it is necessary to copy value X into a register
713 in class CLASS. The value is a register class; perhaps CLASS, or
714 perhaps another, smaller class. */
715 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
716 (GET_CODE (X) == POST_INC \
717 || GET_CODE (X) == POST_DEC \
718 || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS))
719
720 /* Function Calling Conventions. */
721
722 /* The type of the current function; normal functions are of type
723 SUBROUTINE. */
724 typedef enum {
725 SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER
726 } e_funkind;
727 #define FUNCTION_RETURN_REGISTERS { REG_RETS, REG_RETI, REG_RETX, REG_RETN }
728
729 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 }
730
731 /* Flags for the call/call_value rtl operations set up by function_arg */
732 #define CALL_NORMAL 0x00000000 /* no special processing */
733 #define CALL_LONG 0x00000001 /* always call indirect */
734 #define CALL_SHORT 0x00000002 /* always call by symbol */
735
736 typedef struct {
737 int words; /* # words passed so far */
738 int nregs; /* # registers available for passing */
739 int *arg_regs; /* array of register -1 terminated */
740 int call_cookie; /* Do special things for this call */
741 } CUMULATIVE_ARGS;
742
743 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO)
744
745
746 /* Initialize a variable CUM of type CUMULATIVE_ARGS
747 for a call to a function whose data type is FNTYPE.
748 For a library call, FNTYPE is 0. */
749 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \
750 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
751
752 /* Define how to find the value returned by a function.
753 VALTYPE is the data type of the value (as a tree).
754 If the precise function being called is known, FUNC is its FUNCTION_DECL;
755 otherwise, FUNC is 0.
756 */
757
758 #define VALUE_REGNO(MODE) (REG_R0)
759
760 #define FUNCTION_VALUE(VALTYPE, FUNC) \
761 gen_rtx_REG (TYPE_MODE (VALTYPE), \
762 VALUE_REGNO(TYPE_MODE(VALTYPE)))
763
764 /* Define how to find the value returned by a library function
765 assuming the value has mode MODE. */
766
767 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE))
768
769 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0)
770
771 #define DEFAULT_PCC_STRUCT_RETURN 0
772
773 /* Before the prologue, the return address is in the RETS register. */
774 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS)
775
776 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT)
777
778 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS)
779
780 /* Call instructions don't modify the stack pointer on the Blackfin. */
781 #define INCOMING_FRAME_SP_OFFSET 0
782
783 /* Describe how we implement __builtin_eh_return. */
784 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
785 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2)
786 #define EH_RETURN_HANDLER_RTX \
787 gen_frame_mem (Pmode, plus_constant (Pmode, frame_pointer_rtx, \
788 UNITS_PER_WORD))
789
790 /* Addressing Modes */
791
792 /* A number, the maximum number of registers that can appear in a
793 valid memory address. Note that it is up to you to specify a
794 value equal to the maximum number that `TARGET_LEGITIMATE_ADDRESS_P'
795 would ever accept. */
796 #define MAX_REGS_PER_ADDRESS 1
797
798 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \
799 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode)
800
801 #define HAVE_POST_INCREMENT 1
802 #define HAVE_POST_DECREMENT 1
803 #define HAVE_PRE_DECREMENT 1
804
805 /* `LEGITIMATE_PIC_OPERAND_P (X)'
806 A C expression that is nonzero if X is a legitimate immediate
807 operand on the target machine when generating position independent
808 code. You can assume that X satisfies `CONSTANT_P', so you need
809 not check this. You can also assume FLAG_PIC is true, so you need
810 not check it either. You need not define this macro if all
811 constants (including `SYMBOL_REF') can be immediate operands when
812 generating position independent code. */
813 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X)
814
815 #define SYMBOLIC_CONST(X) \
816 (GET_CODE (X) == SYMBOL_REF \
817 || GET_CODE (X) == LABEL_REF \
818 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
819
820 #define NOTICE_UPDATE_CC(EXPR, INSN) 0
821
822 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
823 is done just by pretending it is already truncated. */
824 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
825
826 /* Max number of bytes we can move from memory to memory
827 in one reasonably fast instruction. */
828 #define MOVE_MAX UNITS_PER_WORD
829
830 /* If a memory-to-memory move would take MOVE_RATIO or more simple
831 move-instruction pairs, we will do a movmem or libcall instead. */
832
833 #define MOVE_RATIO(speed) 5
834
835 /* STORAGE LAYOUT: target machine storage layout
836 Define this macro as a C expression which is nonzero if accessing
837 less than a word of memory (i.e. a `char' or a `short') is no
838 faster than accessing a word of memory, i.e., if such access
839 require more than one instruction or if there is no difference in
840 cost between byte and (aligned) word loads.
841
842 When this macro is not defined, the compiler will access a field by
843 finding the smallest containing object; when it is defined, a
844 fullword load will be used if alignment permits. Unless bytes
845 accesses are faster than word accesses, using word accesses is
846 preferable since it may eliminate subsequent memory access if
847 subsequent accesses occur to other fields in the same word of the
848 structure, but to different bytes. */
849 #define SLOW_BYTE_ACCESS 0
850 #define SLOW_SHORT_ACCESS 0
851
852 /* Define this if most significant bit is lowest numbered
853 in instructions that operate on numbered bit-fields. */
854 #define BITS_BIG_ENDIAN 0
855
856 /* Define this if most significant byte of a word is the lowest numbered.
857 We can't access bytes but if we could we would in the Big Endian order. */
858 #define BYTES_BIG_ENDIAN 0
859
860 /* Define this if most significant word of a multiword number is numbered. */
861 #define WORDS_BIG_ENDIAN 0
862
863 /* number of bits in an addressable storage unit */
864 #define BITS_PER_UNIT 8
865
866 /* Width in bits of a "word", which is the contents of a machine register.
867 Note that this is not necessarily the width of data type `int';
868 if using 16-bit ints on a 68000, this would still be 32.
869 But on a machine with 16-bit registers, this would be 16. */
870 #define BITS_PER_WORD 32
871
872 /* Width of a word, in units (bytes). */
873 #define UNITS_PER_WORD 4
874
875 /* Width in bits of a pointer.
876 See also the macro `Pmode1' defined below. */
877 #define POINTER_SIZE 32
878
879 /* Allocation boundary (in *bits*) for storing pointers in memory. */
880 #define POINTER_BOUNDARY 32
881
882 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
883 #define PARM_BOUNDARY 32
884
885 /* Boundary (in *bits*) on which stack pointer should be aligned. */
886 #define STACK_BOUNDARY 32
887
888 /* Allocation boundary (in *bits*) for the code of a function. */
889 #define FUNCTION_BOUNDARY 32
890
891 /* Alignment of field after `int : 0' in a structure. */
892 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
893
894 /* No data type wants to be aligned rounder than this. */
895 #define BIGGEST_ALIGNMENT 32
896
897 /* Define this if move instructions will actually fail to work
898 when given unaligned data. */
899 #define STRICT_ALIGNMENT 1
900
901 /* (shell-command "rm c-decl.o stor-layout.o")
902 * never define PCC_BITFIELD_TYPE_MATTERS
903 * really cause some alignment problem
904 */
905
906 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \
907 BITS_PER_UNIT)
908
909 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \
910 BITS_PER_UNIT)
911
912
913 /* what is the 'type' of size_t */
914 #define SIZE_TYPE "long unsigned int"
915
916 /* Define this as 1 if `char' should by default be signed; else as 0. */
917 #define DEFAULT_SIGNED_CHAR 1
918 #define FLOAT_TYPE_SIZE BITS_PER_WORD
919 #define SHORT_TYPE_SIZE 16
920 #define CHAR_TYPE_SIZE 8
921 #define INT_TYPE_SIZE 32
922 #define LONG_TYPE_SIZE 32
923 #define LONG_LONG_TYPE_SIZE 64
924
925 /* Note: Fix this to depend on target switch. -- lev */
926
927 /* Note: Try to implement double and force long double. -- tonyko
928 * #define __DOUBLES_ARE_FLOATS__
929 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE
930 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
931 * #define DOUBLES_ARE_FLOATS 1
932 */
933
934 #define DOUBLE_TYPE_SIZE 64
935 #define LONG_DOUBLE_TYPE_SIZE 64
936
937 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)'
938 A macro to update M and UNSIGNEDP when an object whose type is
939 TYPE and which has the specified mode and signedness is to be
940 stored in a register. This macro is only called when TYPE is a
941 scalar type.
942
943 On most RISC machines, which only have operations that operate on
944 a full register, define this macro to set M to `word_mode' if M is
945 an integer mode narrower than `BITS_PER_WORD'. In most cases,
946 only integer modes should be widened because wider-precision
947 floating-point operations are usually more expensive than their
948 narrower counterparts.
949
950 For most machines, the macro definition does not change UNSIGNEDP.
951 However, some machines, have instructions that preferentially
952 handle either signed or unsigned quantities of certain modes. For
953 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add
954 instructions sign-extend the result to 64 bits. On such machines,
955 set UNSIGNEDP according to which kind of extension is more
956 efficient.
957
958 Do not define this macro if it would never modify M.*/
959
960 #define BFIN_PROMOTE_MODE_P(MODE) \
961 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \
962 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)
963
964 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
965 if (BFIN_PROMOTE_MODE_P(MODE)) \
966 { \
967 if (MODE == QImode) \
968 UNSIGNEDP = 1; \
969 else if (MODE == HImode) \
970 UNSIGNEDP = 0; \
971 (MODE) = SImode; \
972 }
973
974 /* Describing Relative Costs of Operations */
975
976 /* Do not put function addr into constant pool */
977 #define NO_FUNCTION_CSE 1
978
979 /* Specify the machine mode that this machine uses
980 for the index in the tablejump instruction. */
981 #define CASE_VECTOR_MODE SImode
982
983 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
984
985 /* Define if operations between registers always perform the operation
986 on the full register even if a narrower mode is specified.
987 #define WORD_REGISTER_OPERATIONS
988 */
989
990 /* Evaluates to true if A and B are mac flags that can be used
991 together in a single multiply insn. That is the case if they are
992 both the same flag not involving M, or if one is a combination of
993 the other with M. */
994 #define MACFLAGS_MATCH_P(A, B) \
995 ((A) == (B) \
996 || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \
997 || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \
998 || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \
999 || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS))
1000
1001 /* Switch into a generic section. */
1002 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
1003
1004 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE)
1005 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX)
1006
1007 typedef enum sections {
1008 CODE_DIR,
1009 DATA_DIR,
1010 LAST_SECT_NM
1011 } SECT_ENUM_T;
1012
1013 typedef enum directives {
1014 LONG_CONST_DIR,
1015 SHORT_CONST_DIR,
1016 BYTE_CONST_DIR,
1017 SPACE_DIR,
1018 INIT_DIR,
1019 LAST_DIR_NM
1020 } DIR_ENUM_T;
1021
1022 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \
1023 ((C) == ';' \
1024 || ((C) == '|' && (STR)[1] == '|'))
1025
1026 #define TEXT_SECTION_ASM_OP ".text;"
1027 #define DATA_SECTION_ASM_OP ".data;"
1028
1029 #define ASM_APP_ON ""
1030 #define ASM_APP_OFF ""
1031
1032 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \
1033 do { fputs (".global ", FILE); \
1034 assemble_name (FILE, NAME); \
1035 fputc (';',FILE); \
1036 fputc ('\n',FILE); \
1037 } while (0)
1038
1039 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1040 do { \
1041 fputs (".type ", FILE); \
1042 assemble_name (FILE, NAME); \
1043 fputs (", STT_FUNC", FILE); \
1044 fputc (';',FILE); \
1045 fputc ('\n',FILE); \
1046 ASM_OUTPUT_LABEL(FILE, NAME); \
1047 } while (0)
1048
1049 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1050 do { assemble_name (FILE, NAME); \
1051 fputs (":\n",FILE); \
1052 } while (0)
1053
1054 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1055 do { fprintf (FILE, "_%s", NAME); \
1056 } while (0)
1057
1058 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1059 do { char __buf[256]; \
1060 fprintf (FILE, "\t.dd\t"); \
1061 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1062 assemble_name (FILE, __buf); \
1063 fputc (';', FILE); \
1064 fputc ('\n', FILE); \
1065 } while (0)
1066
1067 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1068 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)
1069
1070 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1071 do { \
1072 char __buf[256]; \
1073 fprintf (FILE, "\t.dd\t"); \
1074 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1075 assemble_name (FILE, __buf); \
1076 fputs (" - ", FILE); \
1077 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \
1078 assemble_name (FILE, __buf); \
1079 fputc (';', FILE); \
1080 fputc ('\n', FILE); \
1081 } while (0)
1082
1083 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1084 do { \
1085 if ((LOG) != 0) \
1086 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
1087 } while (0)
1088
1089 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1090 do { \
1091 asm_output_skip (FILE, SIZE); \
1092 } while (0)
1093
1094 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1095 do { \
1096 switch_to_section (data_section); \
1097 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \
1098 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
1099 ASM_OUTPUT_LABEL (FILE, NAME); \
1100 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \
1101 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \
1102 } while (0)
1103
1104 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1105 do { \
1106 ASM_GLOBALIZE_LABEL1(FILE,NAME); \
1107 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0)
1108
1109 #define ASM_COMMENT_START "//"
1110
1111 #define PROFILE_BEFORE_PROLOGUE
1112 #define FUNCTION_PROFILER(FILE, LABELNO) \
1113 do { \
1114 fprintf (FILE, "\t[--SP] = RETS;\n"); \
1115 if (TARGET_LONG_CALLS) \
1116 { \
1117 fprintf (FILE, "\tP2.h = __mcount;\n"); \
1118 fprintf (FILE, "\tP2.l = __mcount;\n"); \
1119 fprintf (FILE, "\tCALL (P2);\n"); \
1120 } \
1121 else \
1122 fprintf (FILE, "\tCALL __mcount;\n"); \
1123 fprintf (FILE, "\tRETS = [SP++];\n"); \
1124 } while(0)
1125
1126 #undef NO_PROFILE_COUNTERS
1127 #define NO_PROFILE_COUNTERS 1
1128
1129 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "\t[--SP] = %s;\n", reg_names[REGNO])
1130 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "\t%s = [SP++];\n", reg_names[REGNO])
1131
1132 extern rtx bfin_cc_rtx, bfin_rets_rtx;
1133
1134 /* This works for GAS and some other assemblers. */
1135 #define SET_ASM_OP ".set "
1136
1137 /* DBX register number for a given compiler register number */
1138 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1139
1140 #define SIZE_ASM_OP "\t.size\t"
1141
1142 extern int splitting_for_sched, splitting_loops;
1143
1144 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!')
1145
1146 #ifndef TARGET_SUPPORTS_SYNC_CALLS
1147 #define TARGET_SUPPORTS_SYNC_CALLS 0
1148 #endif
1149
1150 struct bfin_cpu
1151 {
1152 const char *name;
1153 bfin_cpu_t type;
1154 int si_revision;
1155 unsigned int workarounds;
1156 };
1157
1158 extern const struct bfin_cpu bfin_cpus[];
1159
1160 #endif /* _BFIN_CONFIG */
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