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Replace current_function_anonymous_args with cfun->machine->uses_anonymous_args
[official-gcc.git] / gcc / config / arm / arm.h
blob9b60d7bda594fd2dbc522e04cf590a22fcd6115f
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GNU CC.
10
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 #define TARGET_CPU_arm2 0x0000
30 #define TARGET_CPU_arm250 0x0000
31 #define TARGET_CPU_arm3 0x0000
32 #define TARGET_CPU_arm6 0x0001
33 #define TARGET_CPU_arm600 0x0001
34 #define TARGET_CPU_arm610 0x0002
35 #define TARGET_CPU_arm7 0x0001
36 #define TARGET_CPU_arm7m 0x0004
37 #define TARGET_CPU_arm7dm 0x0004
38 #define TARGET_CPU_arm7dmi 0x0004
39 #define TARGET_CPU_arm700 0x0001
40 #define TARGET_CPU_arm710 0x0002
41 #define TARGET_CPU_arm7100 0x0002
42 #define TARGET_CPU_arm7500 0x0002
43 #define TARGET_CPU_arm7500fe 0x1001
44 #define TARGET_CPU_arm7tdmi 0x0008
45 #define TARGET_CPU_arm8 0x0010
46 #define TARGET_CPU_arm810 0x0020
47 #define TARGET_CPU_strongarm 0x0040
48 #define TARGET_CPU_strongarm110 0x0040
49 #define TARGET_CPU_strongarm1100 0x0040
50 #define TARGET_CPU_arm9 0x0080
51 #define TARGET_CPU_arm9tdmi 0x0080
52 #define TARGET_CPU_xscale 0x0100
53 /* Configure didn't specify. */
54 #define TARGET_CPU_generic 0x8000
55
56 typedef enum arm_cond_code
57 {
58 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
59 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
60 }
61 arm_cc;
62
63 extern arm_cc arm_current_cc;
64
65 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
66
67 extern int arm_target_label;
68 extern int arm_ccfsm_state;
69 extern struct rtx_def * arm_target_insn;
70 /* Run-time compilation parameters selecting different hardware subsets. */
71 extern int target_flags;
72 /* The floating point instruction architecture, can be 2 or 3 */
73 extern const char * target_fp_name;
74 /* Define the information needed to generate branch insns. This is
75 stored from the compare operation. Note that we can't use "rtx" here
76 since it hasn't been defined! */
77 extern struct rtx_def * arm_compare_op0;
78 extern struct rtx_def * arm_compare_op1;
79 /* The label of the current constant pool. */
80 extern struct rtx_def * pool_vector_label;
81 /* Set to 1 when a return insn is output, this means that the epilogue
82 is not needed. */
83 extern int return_used_this_function;
84 \f
85 /* Just in case configure has failed to define anything. */
86 #ifndef TARGET_CPU_DEFAULT
87 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
88 #endif
89
90 /* If the configuration file doesn't specify the cpu, the subtarget may
91 override it. If it doesn't, then default to an ARM6. */
92 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
93 #undef TARGET_CPU_DEFAULT
94
95 #ifdef SUBTARGET_CPU_DEFAULT
96 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
97 #else
98 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
99 #endif
100 #endif
101
102 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
103 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
104 #else
105 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
106 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
107 #else
108 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
109 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
110 #else
111 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi
112 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
113 #else
114 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
115 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
116 #else
117 #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale
118 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__"
119 #else
120 Unrecognized value in TARGET_CPU_DEFAULT.
121 #endif
122 #endif
123 #endif
124 #endif
125 #endif
126 #endif
127
128 #undef CPP_SPEC
129 #define CPP_SPEC "\
130 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
131 %(cpp_endian) %(subtarget_cpp_spec) %(cpp_isa) %(cpp_interwork)"
132
133 #define CPP_ISA_SPEC "%{mthumb:-D__thumb__} %{!mthumb:-D__arm__}"
134
135 /* Set the architecture define -- if -march= is set, then it overrides
136 the -mcpu= setting. */
137 #define CPP_CPU_ARCH_SPEC "\
138 -Acpu=arm -Amachine=arm \
139 %{march=arm2:-D__ARM_ARCH_2__} \
140 %{march=arm250:-D__ARM_ARCH_2__} \
141 %{march=arm3:-D__ARM_ARCH_2__} \
142 %{march=arm6:-D__ARM_ARCH_3__} \
143 %{march=arm600:-D__ARM_ARCH_3__} \
144 %{march=arm610:-D__ARM_ARCH_3__} \
145 %{march=arm7:-D__ARM_ARCH_3__} \
146 %{march=arm700:-D__ARM_ARCH_3__} \
147 %{march=arm710:-D__ARM_ARCH_3__} \
148 %{march=arm720:-D__ARM_ARCH_3__} \
149 %{march=arm7100:-D__ARM_ARCH_3__} \
150 %{march=arm7500:-D__ARM_ARCH_3__} \
151 %{march=arm7500fe:-D__ARM_ARCH_3__} \
152 %{march=arm7m:-D__ARM_ARCH_3M__} \
153 %{march=arm7dm:-D__ARM_ARCH_3M__} \
154 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
155 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
156 %{march=arm8:-D__ARM_ARCH_4__} \
157 %{march=arm810:-D__ARM_ARCH_4__} \
158 %{march=arm9:-D__ARM_ARCH_4T__} \
159 %{march=arm920:-D__ARM_ARCH_4__} \
160 %{march=arm920t:-D__ARM_ARCH_4T__} \
161 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
162 %{march=strongarm:-D__ARM_ARCH_4__} \
163 %{march=strongarm110:-D__ARM_ARCH_4__} \
164 %{march=strongarm1100:-D__ARM_ARCH_4__} \
165 %{march=xscale:-D__ARM_ARCH_5TE__} \
166 %{march=xscale:-D__XSCALE__} \
167 %{march=armv2:-D__ARM_ARCH_2__} \
168 %{march=armv2a:-D__ARM_ARCH_2__} \
169 %{march=armv3:-D__ARM_ARCH_3__} \
170 %{march=armv3m:-D__ARM_ARCH_3M__} \
171 %{march=armv4:-D__ARM_ARCH_4__} \
172 %{march=armv4t:-D__ARM_ARCH_4T__} \
173 %{march=armv5:-D__ARM_ARCH_5__} \
174 %{march=armv5t:-D__ARM_ARCH_5T__} \
175 %{march=armv5e:-D__ARM_ARCH_5E__} \
176 %{march=armv5te:-D__ARM_ARCH_5TE__} \
177 %{!march=*: \
178 %{mcpu=arm2:-D__ARM_ARCH_2__} \
179 %{mcpu=arm250:-D__ARM_ARCH_2__} \
180 %{mcpu=arm3:-D__ARM_ARCH_2__} \
181 %{mcpu=arm6:-D__ARM_ARCH_3__} \
182 %{mcpu=arm600:-D__ARM_ARCH_3__} \
183 %{mcpu=arm610:-D__ARM_ARCH_3__} \
184 %{mcpu=arm7:-D__ARM_ARCH_3__} \
185 %{mcpu=arm700:-D__ARM_ARCH_3__} \
186 %{mcpu=arm710:-D__ARM_ARCH_3__} \
187 %{mcpu=arm720:-D__ARM_ARCH_3__} \
188 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
189 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
190 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
191 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
192 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
193 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
194 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
195 %{mcpu=arm8:-D__ARM_ARCH_4__} \
196 %{mcpu=arm810:-D__ARM_ARCH_4__} \
197 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
198 %{mcpu=arm920:-D__ARM_ARCH_4__} \
199 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
200 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
201 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
202 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
203 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
204 %{mcpu=xscale:-D__ARM_ARCH_5TE__} \
205 %{mcpu=xscale:-D__XSCALE__} \
206 %{!mcpu*:%(cpp_cpu_arch_default)}} \
207 "
208
209 /* Define __APCS_26__ if the PC also contains the PSR */
210 #define CPP_APCS_PC_SPEC "\
211 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
212 -D__APCS_32__} \
213 %{mapcs-26:-D__APCS_26__} \
214 %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \
215 "
216
217 #ifndef CPP_APCS_PC_DEFAULT_SPEC
218 #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"
219 #endif
220
221 #define CPP_FLOAT_SPEC "\
222 %{msoft-float:\
223 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
224 -D__SOFTFP__} \
225 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
226 "
227
228 /* Default is hard float, which doesn't define anything */
229 #define CPP_FLOAT_DEFAULT_SPEC ""
230
231 #define CPP_ENDIAN_SPEC "\
232 %{mbig-endian: \
233 %{mlittle-endian: \
234 %e-mbig-endian and -mlittle-endian may not be used together} \
235 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__} %{mthumb:-D__THUMBEB__}}\
236 %{mlittle-endian:-D__ARMEL__ %{mthumb:-D__THUMBEL__}} \
237 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
238 "
239
240 /* Default is little endian. */
241 #define CPP_ENDIAN_DEFAULT_SPEC "-D__ARMEL__ %{mthumb:-D__THUMBEL__}"
242
243 /* Add a define for interworking. Needed when building libgcc.a.
244 This must define __THUMB_INTERWORK__ to the pre-processor if
245 interworking is enabled by default. */
246 #ifndef CPP_INTERWORK_DEFAULT_SPEC
247 #define CPP_INTERWORK_DEFAULT_SPEC ""
248 #endif
249
250 #define CPP_INTERWORK_SPEC " \
251 %{mthumb-interwork: \
252 %{mno-thumb-interwork: %eincompatible interworking options} \
253 -D__THUMB_INTERWORK__} \
254 %{!mthumb-interwork:%{!mno-thumb-interwork:%(cpp_interwork_default)}} \
255 "
256
257 #ifndef CPP_PREDEFINES
258 #define CPP_PREDEFINES ""
259 #endif
260
261 #ifndef CC1_SPEC
262 #define CC1_SPEC ""
263 #endif
264
265 /* This macro defines names of additional specifications to put in the specs
266 that can be used in various specifications like CC1_SPEC. Its definition
267 is an initializer with a subgrouping for each command option.
268
269 Each subgrouping contains a string constant, that defines the
270 specification name, and a string constant that used by the GNU CC driver
271 program.
272
273 Do not define this macro if it does not need to do anything. */
274 #define EXTRA_SPECS \
275 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
276 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
277 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \
278 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \
279 { "cpp_float", CPP_FLOAT_SPEC }, \
280 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \
281 { "cpp_endian", CPP_ENDIAN_SPEC }, \
282 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \
283 { "cpp_isa", CPP_ISA_SPEC }, \
284 { "cpp_interwork", CPP_INTERWORK_SPEC }, \
285 { "cpp_interwork_default", CPP_INTERWORK_DEFAULT_SPEC }, \
286 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
287 SUBTARGET_EXTRA_SPECS
288
289 #ifndef SUBTARGET_EXTRA_SPECS
290 #define SUBTARGET_EXTRA_SPECS
291 #endif
292
293 #ifndef SUBTARGET_CPP_SPEC
294 #define SUBTARGET_CPP_SPEC ""
295 #endif
296 \f
297 /* Run-time Target Specification. */
298 #ifndef TARGET_VERSION
299 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
300 #endif
301
302 /* Nonzero if the function prologue (and epilogue) should obey
303 the ARM Procedure Call Standard. */
304 #define ARM_FLAG_APCS_FRAME (1 << 0)
305
306 /* Nonzero if the function prologue should output the function name to enable
307 the post mortem debugger to print a backtrace (very useful on RISCOS,
308 unused on RISCiX). Specifying this flag also enables
309 -fno-omit-frame-pointer.
310 XXX Must still be implemented in the prologue. */
311 #define ARM_FLAG_POKE (1 << 1)
312
313 /* Nonzero if floating point instructions are emulated by the FPE, in which
314 case instruction scheduling becomes very uninteresting. */
315 #define ARM_FLAG_FPE (1 << 2)
316
317 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
318 that assume restoration of the condition flags when returning from a
319 branch and link (ie a function). */
320 #define ARM_FLAG_APCS_32 (1 << 3)
321
322 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
323
324 /* Nonzero if stack checking should be performed on entry to each function
325 which allocates temporary variables on the stack. */
326 #define ARM_FLAG_APCS_STACK (1 << 4)
327
328 /* Nonzero if floating point parameters should be passed to functions in
329 floating point registers. */
330 #define ARM_FLAG_APCS_FLOAT (1 << 5)
331
332 /* Nonzero if re-entrant, position independent code should be generated.
333 This is equivalent to -fpic. */
334 #define ARM_FLAG_APCS_REENT (1 << 6)
335
336 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
337 be loaded using either LDRH or LDRB instructions. */
338 #define ARM_FLAG_MMU_TRAPS (1 << 7)
339
340 /* Nonzero if all floating point instructions are missing (and there is no
341 emulator either). Generate function calls for all ops in this case. */
342 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
343
344 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
345 #define ARM_FLAG_BIG_END (1 << 9)
346
347 /* Nonzero if we should compile for Thumb interworking. */
348 #define ARM_FLAG_INTERWORK (1 << 10)
349
350 /* Nonzero if we should have little-endian words even when compiling for
351 big-endian (for backwards compatibility with older versions of GCC). */
352 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
353
354 /* Nonzero if we need to protect the prolog from scheduling */
355 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
356
357 /* Nonzero if a call to abort should be generated if a noreturn
358 function tries to return. */
359 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
360
361 /* Nonzero if function prologues should not load the PIC register. */
362 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
363
364 /* Nonzero if all call instructions should be indirect. */
365 #define ARM_FLAG_LONG_CALLS (1 << 15)
366
367 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
368 #define ARM_FLAG_THUMB (1 << 16)
369
370 /* Set if a TPCS style stack frame should be generated, for non-leaf
371 functions, even if they do not need one. */
372 #define THUMB_FLAG_BACKTRACE (1 << 17)
373
374 /* Set if a TPCS style stack frame should be generated, for leaf
375 functions, even if they do not need one. */
376 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
377
378 /* Set if externally visible functions should assume that they
379 might be called in ARM mode, from a non-thumb aware code. */
380 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
381
382 /* Set if calls via function pointers should assume that their
383 destination is non-Thumb aware. */
384 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
385
386 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
387 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
388 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
389 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
390 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
391 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
392 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
393 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
394 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
395 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
396 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
397 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
398 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
399 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
400 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
401 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
402 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
403 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
404 #define TARGET_ARM (! TARGET_THUMB)
405 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
406 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
407 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
408 #define TARGET_BACKTRACE (leaf_function_p () \
409 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
410 : (target_flags & THUMB_FLAG_BACKTRACE))
411
412 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
413 Bit 31 is reserved. See riscix.h. */
414 #ifndef SUBTARGET_SWITCHES
415 #define SUBTARGET_SWITCHES
416 #endif
417
418 #define TARGET_SWITCHES \
419 { \
420 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
421 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
422 N_("Generate APCS conformant stack frames") }, \
423 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
424 {"poke-function-name", ARM_FLAG_POKE, \
425 N_("Store function names in object code") }, \
426 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
427 {"fpe", ARM_FLAG_FPE, "" }, \
428 {"apcs-32", ARM_FLAG_APCS_32, \
429 N_("Use the 32-bit version of the APCS") }, \
430 {"apcs-26", -ARM_FLAG_APCS_32, \
431 N_("Use the 26-bit version of the APCS") }, \
432 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
433 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
434 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
435 N_("Pass FP arguments in FP registers") }, \
436 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
437 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
438 N_("Generate re-entrant, PIC code") }, \
439 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
440 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
441 N_("The MMU will trap on unaligned accesses") }, \
442 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
443 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
444 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
445 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
446 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
447 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
448 N_("Use library calls to perform FP operations") }, \
449 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
450 N_("Use hardware floating point instructions") }, \
451 {"big-endian", ARM_FLAG_BIG_END, \
452 N_("Assume target CPU is configured as big endian") }, \
453 {"little-endian", -ARM_FLAG_BIG_END, \
454 N_("Assume target CPU is configured as little endian") }, \
455 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
456 N_("Assume big endian bytes, little endian words") }, \
457 {"thumb-interwork", ARM_FLAG_INTERWORK, \
458 N_("Support calls between Thumb and ARM instruction sets") }, \
459 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
460 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
461 N_("Generate a call to abort if a noreturn function returns")}, \
462 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
463 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
464 N_("Do not move instructions into a function's prologue") }, \
465 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
466 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
467 N_("Do not load the PIC register in function prologues") }, \
468 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
469 {"long-calls", ARM_FLAG_LONG_CALLS, \
470 N_("Generate call insns as indirect calls, if necessary") }, \
471 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
472 {"thumb", ARM_FLAG_THUMB, \
473 N_("Compile for the Thumb not the ARM") }, \
474 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
475 {"arm", -ARM_FLAG_THUMB, "" }, \
476 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
477 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
478 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
479 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
480 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
481 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
482 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
483 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
484 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
485 "" }, \
486 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
487 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
488 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
489 "" }, \
490 SUBTARGET_SWITCHES \
491 {"", TARGET_DEFAULT, "" } \
492 }
493
494 #define TARGET_OPTIONS \
495 { \
496 {"cpu=", & arm_select[0].string, \
497 N_("Specify the name of the target CPU") }, \
498 {"arch=", & arm_select[1].string, \
499 N_("Specify the name of the target architecture") }, \
500 {"tune=", & arm_select[2].string, "" }, \
501 {"fpe=", & target_fp_name, "" }, \
502 {"fp=", & target_fp_name, \
503 N_("Specify the version of the floating point emulator") }, \
504 {"structure-size-boundary=", & structure_size_string, \
505 N_("Specify the minimum bit alignment of structures") }, \
506 {"pic-register=", & arm_pic_register_string, \
507 N_("Specify the register to be used for PIC addressing") } \
508 }
509
510 struct arm_cpu_select
511 {
512 const char * string;
513 const char * name;
514 const struct processors * processors;
515 };
516
517 /* This is a magic array. If the user specifies a command line switch
518 which matches one of the entries in TARGET_OPTIONS then the corresponding
519 string pointer will be set to the value specified by the user. */
520 extern struct arm_cpu_select arm_select[];
521
522 enum prog_mode_type
523 {
524 prog_mode26,
525 prog_mode32
526 };
527
528 /* Recast the program mode class to be the prog_mode attribute */
529 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
530
531 extern enum prog_mode_type arm_prgmode;
532
533 /* What sort of floating point unit do we have? Hardware or software.
534 If software, is it issue 2 or issue 3? */
535 enum floating_point_type
536 {
537 FP_HARD,
538 FP_SOFT2,
539 FP_SOFT3
540 };
541
542 /* Recast the floating point class to be the floating point attribute. */
543 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
544
545 /* What type of floating point to tune for */
546 extern enum floating_point_type arm_fpu;
547
548 /* What type of floating point instructions are available */
549 extern enum floating_point_type arm_fpu_arch;
550
551 /* Default floating point architecture. Override in sub-target if
552 necessary. */
553 #ifndef FP_DEFAULT
554 #define FP_DEFAULT FP_SOFT2
555 #endif
556
557 /* Nonzero if the processor has a fast multiply insn, and one that does
558 a 64-bit multiply of two 32-bit values. */
559 extern int arm_fast_multiply;
560
561 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
562 extern int arm_arch4;
563
564 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
565 extern int arm_arch5;
566
567 /* Nonzero if this chip supports the ARM Architecture 5E extensions */
568 extern int arm_arch5e;
569
570 /* Nonzero if this chip can benefit from load scheduling. */
571 extern int arm_ld_sched;
572
573 /* Nonzero if generating thumb code. */
574 extern int thumb_code;
575
576 /* Nonzero if this chip is a StrongARM. */
577 extern int arm_is_strong;
578
579 /* Nonzero if this chip is an XScale. */
580 extern int arm_is_xscale;
581
582 /* Nonzero if this chip is an ARM6 or an ARM7. */
583 extern int arm_is_6_or_7;
584
585 #ifndef TARGET_DEFAULT
586 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
587 #endif
588
589 /* The frame pointer register used in gcc has nothing to do with debugging;
590 that is controlled by the APCS-FRAME option. */
591 #define CAN_DEBUG_WITHOUT_FP
592
593 #undef TARGET_MEM_FUNCTIONS
594 #define TARGET_MEM_FUNCTIONS 1
595
596 #define OVERRIDE_OPTIONS arm_override_options ()
597
598 /* Nonzero if PIC code requires explicit qualifiers to generate
599 PLT and GOT relocs rather than the assembler doing so implicitly.
600 Subtargets can override these if required. */
601 #ifndef NEED_GOT_RELOC
602 #define NEED_GOT_RELOC 0
603 #endif
604 #ifndef NEED_PLT_RELOC
605 #define NEED_PLT_RELOC 0
606 #endif
607
608 /* Nonzero if we need to refer to the GOT with a PC-relative
609 offset. In other words, generate
610
611 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
612
613 rather than
614
615 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
616
617 The default is true, which matches NetBSD. Subtargets can
618 override this if required. */
619 #ifndef GOT_PCREL
620 #define GOT_PCREL 1
621 #endif
622 \f
623 /* Target machine storage Layout. */
624
625
626 /* Define this macro if it is advisable to hold scalars in registers
627 in a wider mode than that declared by the program. In such cases,
628 the value is constrained to be within the bounds of the declared
629 type, but kept valid in the wider mode. The signedness of the
630 extension may differ from that of the type. */
631
632 /* It is far faster to zero extend chars than to sign extend them */
633
634 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
635 if (GET_MODE_CLASS (MODE) == MODE_INT \
636 && GET_MODE_SIZE (MODE) < 4) \
637 { \
638 if (MODE == QImode) \
639 UNSIGNEDP = 1; \
640 else if (MODE == HImode) \
641 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
642 (MODE) = SImode; \
643 }
644
645 /* Define this macro if the promotion described by `PROMOTE_MODE'
646 should also be done for outgoing function arguments. */
647 /* This is required to ensure that push insns always push a word. */
648 #define PROMOTE_FUNCTION_ARGS
649
650 /* Define for XFmode extended real floating point support.
651 This will automatically cause REAL_ARITHMETIC to be defined. */
652 /* For the ARM:
653 I think I have added all the code to make this work. Unfortunately,
654 early releases of the floating point emulation code on RISCiX used a
655 different format for extended precision numbers. On my RISCiX box there
656 is a bug somewhere which causes the machine to lock up when running enquire
657 with long doubles. There is the additional aspect that Norcroft C
658 treats long doubles as doubles and we ought to remain compatible.
659 Perhaps someone with an FPA coprocessor and not running RISCiX would like
660 to try this someday. */
661 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
662
663 /* Disable XFmode patterns in md file */
664 #define ENABLE_XF_PATTERNS 0
665
666 /* Define if you don't want extended real, but do want to use the
667 software floating point emulator for REAL_ARITHMETIC and
668 decimal <-> binary conversion. */
669 /* See comment above */
670 #define REAL_ARITHMETIC
671
672 /* Define this if most significant bit is lowest numbered
673 in instructions that operate on numbered bit-fields. */
674 #define BITS_BIG_ENDIAN 0
675
676 /* Define this if most significant byte of a word is the lowest numbered.
677 Most ARM processors are run in little endian mode, so that is the default.
678 If you want to have it run-time selectable, change the definition in a
679 cover file to be TARGET_BIG_ENDIAN. */
680 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
681
682 /* Define this if most significant word of a multiword number is the lowest
683 numbered.
684 This is always false, even when in big-endian mode. */
685 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
686
687 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
688 on processor pre-defineds when compiling libgcc2.c. */
689 #if defined(__ARMEB__) && !defined(__ARMWEL__)
690 #define LIBGCC2_WORDS_BIG_ENDIAN 1
691 #else
692 #define LIBGCC2_WORDS_BIG_ENDIAN 0
693 #endif
694
695 /* Define this if most significant word of doubles is the lowest numbered.
696 This is always true, even when in little-endian mode. */
697 #define FLOAT_WORDS_BIG_ENDIAN 1
698
699 /* Number of bits in an addressable storage unit */
700 #define BITS_PER_UNIT 8
701
702 #define BITS_PER_WORD 32
703
704 #define UNITS_PER_WORD 4
705
706 #define POINTER_SIZE 32
707
708 #define PARM_BOUNDARY 32
709
710 #define STACK_BOUNDARY 32
711
712 #define FUNCTION_BOUNDARY 32
713
714 /* The lowest bit is used to indicate Thumb-mode functions, so the
715 vbit must go into the delta field of pointers to member
716 functions. */
717 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
718
719 #define EMPTY_FIELD_BOUNDARY 32
720
721 #define BIGGEST_ALIGNMENT 32
722
723 /* Make strings word-aligned so strcpy from constants will be faster. */
724 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2)
725
726 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
727 ((TREE_CODE (EXP) == STRING_CST \
728 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
729 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
730
731 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
732 value set in previous versions of this toolchain was 8, which produces more
733 compact structures. The command line option -mstructure_size_boundary=<n>
734 can be used to change this value. For compatibility with the ARM SDK
735 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
736 0020D) page 2-20 says "Structures are aligned on word boundaries". */
737 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
738 extern int arm_structure_size_boundary;
739
740 /* This is the value used to initialise arm_structure_size_boundary. If a
741 particular arm target wants to change the default value it should change
742 the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h
743 for an example of this. */
744 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
745 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
746 #endif
747
748 /* Used when parsing command line option -mstructure_size_boundary. */
749 extern const char * structure_size_string;
750
751 /* Non-zero if move instructions will actually fail to work
752 when given unaligned data. */
753 #define STRICT_ALIGNMENT 1
754
755 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
756
757 \f
758 /* Standard register usage. */
759
760 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
761 (S - saved over call).
762
763 r0 * argument word/integer result
764 r1-r3 argument word
765
766 r4-r8 S register variable
767 r9 S (rfp) register variable (real frame pointer)
768
769 r10 F S (sl) stack limit (used by -mapcs-stack-check)
770 r11 F S (fp) argument pointer
771 r12 (ip) temp workspace
772 r13 F S (sp) lower end of current stack frame
773 r14 (lr) link address/workspace
774 r15 F (pc) program counter
775
776 f0 floating point result
777 f1-f3 floating point scratch
778
779 f4-f7 S floating point variable
780
781 cc This is NOT a real register, but is used internally
782 to represent things that use or set the condition
783 codes.
784 sfp This isn't either. It is used during rtl generation
785 since the offset between the frame pointer and the
786 auto's isn't known until after register allocation.
787 afp Nor this, we only need this because of non-local
788 goto. Without it fp appears to be used and the
789 elimination code won't get rid of sfp. It tracks
790 fp exactly at all times.
791
792 *: See CONDITIONAL_REGISTER_USAGE */
793
794 /* The stack backtrace structure is as follows:
795 fp points to here: | save code pointer | [fp]
796 | return link value | [fp, #-4]
797 | return sp value | [fp, #-8]
798 | return fp value | [fp, #-12]
799 [| saved r10 value |]
800 [| saved r9 value |]
801 [| saved r8 value |]
802 [| saved r7 value |]
803 [| saved r6 value |]
804 [| saved r5 value |]
805 [| saved r4 value |]
806 [| saved r3 value |]
807 [| saved r2 value |]
808 [| saved r1 value |]
809 [| saved r0 value |]
810 [| saved f7 value |] three words
811 [| saved f6 value |] three words
812 [| saved f5 value |] three words
813 [| saved f4 value |] three words
814 r0-r3 are not normally saved in a C function. */
815
816 /* 1 for registers that have pervasive standard uses
817 and are not available for the register allocator. */
818 #define FIXED_REGISTERS \
819 { \
820 0,0,0,0,0,0,0,0, \
821 0,0,0,0,0,1,0,1, \
822 0,0,0,0,0,0,0,0, \
823 1,1,1 \
824 }
825
826 /* 1 for registers not available across function calls.
827 These must include the FIXED_REGISTERS and also any
828 registers that can be used without being saved.
829 The latter must include the registers where values are returned
830 and the register where structure-value addresses are passed.
831 Aside from that, you can include as many other registers as you like.
832 The CC is not preserved over function calls on the ARM 6, so it is
833 easier to assume this for all. SFP is preserved, since FP is. */
834 #define CALL_USED_REGISTERS \
835 { \
836 1,1,1,1,0,0,0,0, \
837 0,0,0,0,1,1,1,1, \
838 1,1,1,1,0,0,0,0, \
839 1,1,1 \
840 }
841
842 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
843 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
844 #endif
845
846 #define CONDITIONAL_REGISTER_USAGE \
847 { \
848 int regno; \
849 \
850 if (TARGET_SOFT_FLOAT || TARGET_THUMB) \
851 { \
852 for (regno = FIRST_ARM_FP_REGNUM; \
853 regno <= LAST_ARM_FP_REGNUM; ++regno) \
854 fixed_regs[regno] = call_used_regs[regno] = 1; \
855 } \
856 if (flag_pic) \
857 { \
858 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
859 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
860 } \
861 else if (TARGET_APCS_STACK) \
862 { \
863 fixed_regs[10] = 1; \
864 call_used_regs[10] = 1; \
865 } \
866 if (TARGET_APCS_FRAME) \
867 { \
868 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
869 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
870 } \
871 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
872 }
873
874 /* These are a couple of extensions to the formats accecpted
875 by asm_fprintf:
876 %@ prints out ASM_COMMENT_START
877 %r prints out REGISTER_PREFIX reg_names[arg] */
878 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
879 case '@': \
880 fputs (ASM_COMMENT_START, FILE); \
881 break; \
882 \
883 case 'r': \
884 fputs (REGISTER_PREFIX, FILE); \
885 fputs (reg_names [va_arg (ARGS, int)], FILE); \
886 break;
887
888 /* Round X up to the nearest word. */
889 #define ROUND_UP(X) (((X) + 3) & ~3)
890
891 /* Convert fron bytes to ints. */
892 #define NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
893
894 /* The number of (integer) registers required to hold a quantity of type MODE. */
895 #define NUM_REGS(MODE) \
896 NUM_INTS (GET_MODE_SIZE (MODE))
897
898 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
899 #define NUM_REGS2(MODE, TYPE) \
900 NUM_INTS ((MODE) == BLKmode ? \
901 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
902
903 /* The number of (integer) argument register available. */
904 #define NUM_ARG_REGS 4
905
906 /* Return the regiser number of the N'th (integer) argument. */
907 #define ARG_REGISTER(N) (N - 1)
908
909 #if 0 /* FIXME: The ARM backend has special code to handle structure
910 returns, and will reserve its own hidden first argument. So
911 if this macro is enabled a *second* hidden argument will be
912 reserved, which will break binary compatibility with old
913 toolchains and also thunk handling. One day this should be
914 fixed. */
915 /* RTX for structure returns. NULL means use a hidden first argument. */
916 #define STRUCT_VALUE 0
917 #else
918 /* Register in which address to store a structure value
919 is passed to a function. */
920 #define STRUCT_VALUE_REGNUM ARG_REGISTER (1)
921 #endif
922
923 /* Specify the registers used for certain standard purposes.
924 The values of these macros are register numbers. */
925
926 /* The number of the last argument register. */
927 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
928
929 /* The number of the last "lo" register (thumb). */
930 #define LAST_LO_REGNUM 7
931
932 /* The register that holds the return address in exception handlers. */
933 #define EXCEPTION_LR_REGNUM 2
934
935 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
936 as an invisible last argument (possible since varargs don't exist in
937 Pascal), so the following is not true. */
938 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
939
940 /* Define this to be where the real frame pointer is if it is not possible to
941 work out the offset between the frame pointer and the automatic variables
942 until after register allocation has taken place. FRAME_POINTER_REGNUM
943 should point to a special register that we will make sure is eliminated.
944
945 For the Thumb we have another problem. The TPCS defines the frame pointer
946 as r11, and GCC belives that it is always possible to use the frame pointer
947 as base register for addressing purposes. (See comments in
948 find_reloads_address()). But - the Thumb does not allow high registers,
949 including r11, to be used as base address registers. Hence our problem.
950
951 The solution used here, and in the old thumb port is to use r7 instead of
952 r11 as the hard frame pointer and to have special code to generate
953 backtrace structures on the stack (if required to do so via a command line
954 option) using r11. This is the only 'user visable' use of r11 as a frame
955 pointer. */
956 #define ARM_HARD_FRAME_POINTER_REGNUM 11
957 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
958
959 #define HARD_FRAME_POINTER_REGNUM \
960 (TARGET_ARM \
961 ? ARM_HARD_FRAME_POINTER_REGNUM \
962 : THUMB_HARD_FRAME_POINTER_REGNUM)
963
964 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
965
966 /* Register to use for pushing function arguments. */
967 #define STACK_POINTER_REGNUM SP_REGNUM
968
969 /* ARM floating pointer registers. */
970 #define FIRST_ARM_FP_REGNUM 16
971 #define LAST_ARM_FP_REGNUM 23
972
973 /* Base register for access to local variables of the function. */
974 #define FRAME_POINTER_REGNUM 25
975
976 /* Base register for access to arguments of the function. */
977 #define ARG_POINTER_REGNUM 26
978
979 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
980 #define FIRST_PSEUDO_REGISTER 27
981
982 /* Value should be nonzero if functions must have frame pointers.
983 Zero means the frame pointer need not be set up (and parms may be accessed
984 via the stack pointer) in functions that seem suitable.
985 If we have to have a frame pointer we might as well make use of it.
986 APCS says that the frame pointer does not need to be pushed in leaf
987 functions, or simple tail call functions. */
988 #define FRAME_POINTER_REQUIRED \
989 (current_function_has_nonlocal_label \
990 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
991
992 /* Return number of consecutive hard regs needed starting at reg REGNO
993 to hold something of mode MODE.
994 This is ordinarily the length in words of a value of mode MODE
995 but can be less for certain modes in special long registers.
996
997 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
998 mode. */
999 #define HARD_REGNO_NREGS(REGNO, MODE) \
1000 ((TARGET_ARM \
1001 && REGNO >= FIRST_ARM_FP_REGNUM \
1002 && REGNO != FRAME_POINTER_REGNUM \
1003 && REGNO != ARG_POINTER_REGNUM) \
1004 ? 1 : NUM_REGS (MODE))
1005
1006 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1007 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1008 arm_hard_regno_mode_ok ((REGNO), (MODE))
1009
1010 /* Value is 1 if it is a good idea to tie two pseudo registers
1011 when one has mode MODE1 and one has mode MODE2.
1012 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1013 for any hard reg, then this must be 0 for correct output. */
1014 #define MODES_TIEABLE_P(MODE1, MODE2) \
1015 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1016
1017 /* The order in which register should be allocated. It is good to use ip
1018 since no saving is required (though calls clobber it) and it never contains
1019 function parameters. It is quite good to use lr since other calls may
1020 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1021 least likely to contain a function parameter; in addition results are
1022 returned in r0. */
1023 #define REG_ALLOC_ORDER \
1024 { \
1025 3, 2, 1, 0, 12, 14, 4, 5, \
1026 6, 7, 8, 10, 9, 11, 13, 15, \
1027 16, 17, 18, 19, 20, 21, 22, 23, \
1028 24, 25, 26 \
1029 }
1030 \f
1031 /* Register and constant classes. */
1032
1033 /* Register classes: used to be simple, just all ARM regs or all FPU regs
1034 Now that the Thumb is involved it has become more complicated. */
1035 enum reg_class
1036 {
1037 NO_REGS,
1038 FPU_REGS,
1039 LO_REGS,
1040 STACK_REG,
1041 BASE_REGS,
1042 HI_REGS,
1043 CC_REG,
1044 GENERAL_REGS,
1045 ALL_REGS,
1046 LIM_REG_CLASSES
1047 };
1048
1049 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1050
1051 /* Give names of register classes as strings for dump file. */
1052 #define REG_CLASS_NAMES \
1053 { \
1054 "NO_REGS", \
1055 "FPU_REGS", \
1056 "LO_REGS", \
1057 "STACK_REG", \
1058 "BASE_REGS", \
1059 "HI_REGS", \
1060 "CC_REG", \
1061 "GENERAL_REGS", \
1062 "ALL_REGS", \
1063 }
1064
1065 /* Define which registers fit in which classes.
1066 This is an initializer for a vector of HARD_REG_SET
1067 of length N_REG_CLASSES. */
1068 #define REG_CLASS_CONTENTS \
1069 { \
1070 { 0x0000000 }, /* NO_REGS */ \
1071 { 0x0FF0000 }, /* FPU_REGS */ \
1072 { 0x00000FF }, /* LO_REGS */ \
1073 { 0x0002000 }, /* STACK_REG */ \
1074 { 0x00020FF }, /* BASE_REGS */ \
1075 { 0x000FF00 }, /* HI_REGS */ \
1076 { 0x1000000 }, /* CC_REG */ \
1077 { 0x200FFFF }, /* GENERAL_REGS */ \
1078 { 0x2FFFFFF } /* ALL_REGS */ \
1079 }
1080
1081 /* The same information, inverted:
1082 Return the class number of the smallest class containing
1083 reg number REGNO. This could be a conditional expression
1084 or could index an array. */
1085 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1086
1087 /* The class value for index registers, and the one for base regs. */
1088 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1089 #define BASE_REG_CLASS (TARGET_THUMB ? BASE_REGS : GENERAL_REGS)
1090
1091 /* For the Thumb the high registers cannot be used as base
1092 registers when addressing quanitities in QI or HI mode. */
1093 #define MODE_BASE_REG_CLASS(MODE) \
1094 (TARGET_ARM ? BASE_REGS : \
1095 (((MODE) == QImode || (MODE) == HImode || (MODE) == VOIDmode) \
1096 ? LO_REGS : BASE_REGS))
1097
1098 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1099 registers explicitly used in the rtl to be used as spill registers
1100 but prevents the compiler from extending the lifetime of these
1101 registers. */
1102 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1103
1104 /* Get reg_class from a letter such as appears in the machine description.
1105 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS) for the
1106 ARM, but several more letters for the Thumb. */
1107 #define REG_CLASS_FROM_LETTER(C) \
1108 ( (C) == 'f' ? FPU_REGS \
1109 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1110 : TARGET_ARM ? NO_REGS \
1111 : (C) == 'h' ? HI_REGS \
1112 : (C) == 'b' ? BASE_REGS \
1113 : (C) == 'k' ? STACK_REG \
1114 : (C) == 'c' ? CC_REG \
1115 : NO_REGS)
1116
1117 /* The letters I, J, K, L and M in a register constraint string
1118 can be used to stand for particular ranges of immediate operands.
1119 This macro defines what the ranges are.
1120 C is the letter, and VALUE is a constant value.
1121 Return 1 if VALUE is in the range specified by C.
1122 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1123 J: valid indexing constants.
1124 K: ~value ok in rhs argument of data operand.
1125 L: -value ok in rhs argument of data operand.
1126 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1127 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1128 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1129 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1130 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1131 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1132 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1133 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1134 : 0)
1135
1136 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1137 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1138 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1139 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1140 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1141 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1142 && ((VAL) & 3) == 0) : \
1143 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1144 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1145 : 0)
1146
1147 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1148 (TARGET_ARM ? \
1149 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1150
1151 /* Constant letter 'G' for the FPU immediate constants.
1152 'H' means the same constant negated. */
1153 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1154 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : \
1155 (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
1156
1157 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1158 (TARGET_ARM ? \
1159 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1160
1161 /* For the ARM, `Q' means that this is a memory operand that is just
1162 an offset from a register.
1163 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1164 address. This means that the symbol is in the text segment and can be
1165 accessed without using a load. */
1166
1167 #define EXTRA_CONSTRAINT_ARM(OP, C) \
1168 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \
1169 (C) == 'R' ? (GET_CODE (OP) == MEM \
1170 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1171 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1172 (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
1173 : 0)
1174
1175 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1176 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1177 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1178
1179 #define EXTRA_CONSTRAINT(X, C) \
1180 (TARGET_ARM ? \
1181 EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C))
1182
1183 /* Given an rtx X being reloaded into a reg required to be
1184 in class CLASS, return the class of reg to actually use.
1185 In general this is just CLASS, but for the Thumb we prefer
1186 a LO_REGS class or a subset. */
1187 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1188 (TARGET_ARM ? (CLASS) : \
1189 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1190
1191 /* Must leave BASE_REGS reloads alone */
1192 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1193 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1194 ? ((true_regnum (X) == -1 ? LO_REGS \
1195 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1196 : NO_REGS)) \
1197 : NO_REGS)
1198
1199 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1200 ((CLASS) != LO_REGS \
1201 ? ((true_regnum (X) == -1 ? LO_REGS \
1202 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1203 : NO_REGS)) \
1204 : NO_REGS)
1205
1206 /* Return the register class of a scratch register needed to copy IN into
1207 or out of a register in CLASS in MODE. If it can be done directly,
1208 NO_REGS is returned. */
1209 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1210 (TARGET_ARM ? \
1211 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1212 ? GENERAL_REGS : NO_REGS) \
1213 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1214
1215 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1216 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1217 (TARGET_ARM ? \
1218 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1219 && (GET_CODE (X) == MEM \
1220 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1221 && true_regnum (X) == -1))) \
1222 ? GENERAL_REGS : NO_REGS) \
1223 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))
1224
1225 /* Try a machine-dependent way of reloading an illegitimate address
1226 operand. If we find one, push the reload and jump to WIN. This
1227 macro is used in only one place: `find_reloads_address' in reload.c.
1228
1229 For the ARM, we wish to handle large displacements off a base
1230 register by splitting the addend across a MOV and the mem insn.
1231 This can cut the number of reloads needed. */
1232 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1233 do \
1234 { \
1235 if (GET_CODE (X) == PLUS \
1236 && GET_CODE (XEXP (X, 0)) == REG \
1237 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1238 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1239 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1240 { \
1241 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1242 HOST_WIDE_INT low, high; \
1243 \
1244 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1245 low = ((val & 0xf) ^ 0x8) - 0x8; \
1246 else if (MODE == SImode \
1247 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1248 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1249 /* Need to be careful, -4096 is not a valid offset. */ \
1250 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1251 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1252 /* Need to be careful, -256 is not a valid offset. */ \
1253 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1254 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1255 && TARGET_HARD_FLOAT) \
1256 /* Need to be careful, -1024 is not a valid offset. */ \
1257 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1258 else \
1259 break; \
1260 \
1261 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1262 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1263 - (unsigned HOST_WIDE_INT) 0x80000000); \
1264 /* Check for overflow or zero */ \
1265 if (low == 0 || high == 0 || (high + low != val)) \
1266 break; \
1267 \
1268 /* Reload the high part into a base reg; leave the low part \
1269 in the mem. */ \
1270 X = gen_rtx_PLUS (GET_MODE (X), \
1271 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1272 GEN_INT (high)), \
1273 GEN_INT (low)); \
1274 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1275 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1276 VOIDmode, 0, 0, OPNUM, TYPE); \
1277 goto WIN; \
1278 } \
1279 } \
1280 while (0)
1281
1282 /* ??? If an HImode FP+large_offset address is converted to an HImode
1283 SP+large_offset address, then reload won't know how to fix it. It sees
1284 only that SP isn't valid for HImode, and so reloads the SP into an index
1285 register, but the resulting address is still invalid because the offset
1286 is too big. We fix it here instead by reloading the entire address. */
1287 /* We could probably achieve better results by defining PROMOTE_MODE to help
1288 cope with the variances between the Thumb's signed and unsigned byte and
1289 halfword load instructions. */
1290 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1291 { \
1292 if (GET_CODE (X) == PLUS \
1293 && GET_MODE_SIZE (MODE) < 4 \
1294 && GET_CODE (XEXP (X, 0)) == REG \
1295 && XEXP (X, 0) == stack_pointer_rtx \
1296 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1297 && ! THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
1298 { \
1299 rtx orig_X = X; \
1300 X = copy_rtx (X); \
1301 push_reload (orig_X, NULL_RTX, &X, NULL, \
1302 MODE_BASE_REG_CLASS (MODE), \
1303 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1304 goto WIN; \
1305 } \
1306 }
1307
1308 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1309 if (TARGET_ARM) \
1310 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1311 else \
1312 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1313
1314 /* Return the maximum number of consecutive registers
1315 needed to represent mode MODE in a register of class CLASS.
1316 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
1317 #define CLASS_MAX_NREGS(CLASS, MODE) \
1318 ((CLASS) == FPU_REGS ? 1 : NUM_REGS (MODE))
1319
1320 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
1321 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1322 (TARGET_ARM ? \
1323 ((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \
1324 (FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : 2) \
1325 : \
1326 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1327 \f
1328 /* Stack layout; function entry, exit and calling. */
1329
1330 /* Define this if pushing a word on the stack
1331 makes the stack pointer a smaller address. */
1332 #define STACK_GROWS_DOWNWARD 1
1333
1334 /* Define this if the nominal address of the stack frame
1335 is at the high-address end of the local variables;
1336 that is, each additional local variable allocated
1337 goes at a more negative offset in the frame. */
1338 #define FRAME_GROWS_DOWNWARD 1
1339
1340 /* Offset within stack frame to start allocating local variables at.
1341 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1342 first local allocated. Otherwise, it is the offset to the BEGINNING
1343 of the first local allocated. */
1344 #define STARTING_FRAME_OFFSET 0
1345
1346 /* If we generate an insn to push BYTES bytes,
1347 this says how many the stack pointer really advances by. */
1348 /* The push insns do not do this rounding implicitly.
1349 So don't define this. */
1350 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP (NPUSHED) */
1351
1352 /* Define this if the maximum size of all the outgoing args is to be
1353 accumulated and pushed during the prologue. The amount can be
1354 found in the variable current_function_outgoing_args_size. */
1355 #define ACCUMULATE_OUTGOING_ARGS 1
1356
1357 /* Offset of first parameter from the argument pointer register value. */
1358 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1359
1360 /* Value is the number of byte of arguments automatically
1361 popped when returning from a subroutine call.
1362 FUNDECL is the declaration node of the function (as a tree),
1363 FUNTYPE is the data type of the function (as a tree),
1364 or for a library call it is an identifier node for the subroutine name.
1365 SIZE is the number of bytes of arguments passed on the stack.
1366
1367 On the ARM, the caller does not pop any of its arguments that were passed
1368 on the stack. */
1369 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1370
1371 /* Define how to find the value returned by a library function
1372 assuming the value has mode MODE. */
1373 #define LIBCALL_VALUE(MODE) \
1374 (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1375 ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \
1376 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1377
1378 /* Define how to find the value returned by a function.
1379 VALTYPE is the data type of the value (as a tree).
1380 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1381 otherwise, FUNC is 0. */
1382 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1383 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1384
1385 /* 1 if N is a possible register number for a function value.
1386 On the ARM, only r0 and f0 can return results. */
1387 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1388 ((REGNO) == ARG_REGISTER (1) \
1389 || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT))
1390
1391 /* How large values are returned */
1392 /* A C expression which can inhibit the returning of certain function values
1393 in registers, based on the type of value. */
1394 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1395
1396 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1397 values must be in memory. On the ARM, they need only do so if larger
1398 than a word, or if they contain elements offset from zero in the struct. */
1399 #define DEFAULT_PCC_STRUCT_RETURN 0
1400
1401 /* Flags for the call/call_value rtl operations set up by function_arg. */
1402 #define CALL_NORMAL 0x00000000 /* No special processing. */
1403 #define CALL_LONG 0x00000001 /* Always call indirect. */
1404 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1405
1406 /* These bits describe the different types of function supported
1407 by the ARM backend. They are exclusive. ie a function cannot be both a
1408 normal function and an interworked function, for example. Knowing the
1409 type of a function is important for determining its prologue and
1410 epilogue sequences.
1411 Note value 7 is currently unassigned. Also note that the interrupt
1412 function types all have bit 2 set, so that they can be tested for easily.
1413 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1414 machine_function structure is initialised (to zero) func_type will
1415 default to unknown. This will force the first use of arm_current_func_type
1416 to call arm_compute_func_type. */
1417 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1418 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1419 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1420 #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */
1421 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1422 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1423 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1424
1425 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1426
1427 /* In addition functions can have several type modifiers,
1428 outlined by these bit masks: */
1429 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1430 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1431 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1432 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1433
1434 /* Some macros to test these flags. */
1435 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1436 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1437 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1438 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1439 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1440
1441 /* A C structure for machine-specific, per-function data.
1442 This is added to the cfun structure. */
1443 typedef struct machine_function
1444 {
1445 /* Additionsl stack adjustment in __builtin_eh_throw. */
1446 struct rtx_def *eh_epilogue_sp_ofs;
1447 /* Records if LR has to be saved for far jumps. */
1448 int far_jump_used;
1449 /* Records if ARG_POINTER was ever live. */
1450 int arg_pointer_live;
1451 /* Records if the save of LR has been eliminated. */
1452 int lr_save_eliminated;
1453 /* Records the type of the current function. */
1454 unsigned long func_type;
1455 /* Record if the function has a variable argument list. */
1456 int uses_anonymous_args;
1457 }
1458 machine_function;
1459
1460 /* A C type for declaring a variable that is used as the first argument of
1461 `FUNCTION_ARG' and other related values. For some target machines, the
1462 type `int' suffices and can hold the number of bytes of argument so far. */
1463 typedef struct
1464 {
1465 /* This is the number of registers of arguments scanned so far. */
1466 int nregs;
1467 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */
1468 int call_cookie;
1469 } CUMULATIVE_ARGS;
1470
1471 /* Define where to put the arguments to a function.
1472 Value is zero to push the argument on the stack,
1473 or a hard register in which to store the argument.
1474
1475 MODE is the argument's machine mode.
1476 TYPE is the data type of the argument (as a tree).
1477 This is null for libcalls where that information may
1478 not be available.
1479 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1480 the preceding args and about the function being called.
1481 NAMED is nonzero if this argument is a named parameter
1482 (otherwise it is an extra parameter matching an ellipsis).
1483
1484 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1485 other arguments are passed on the stack. If (NAMED == 0) (which happens
1486 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1487 passed in the stack (function_prologue will indeed make it pass in the
1488 stack if necessary). */
1489 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1490 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1491
1492 /* For an arg passed partly in registers and partly in memory,
1493 this is the number of registers used.
1494 For args passed entirely in registers or entirely in memory, zero. */
1495 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1496 ( NUM_ARG_REGS > (CUM).nregs \
1497 && (NUM_ARG_REGS < ((CUM).nregs + NUM_REGS2 (MODE, TYPE))) \
1498 ? NUM_ARG_REGS - (CUM).nregs : 0)
1499
1500 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1501 for a call to a function whose data type is FNTYPE.
1502 For a library call, FNTYPE is 0.
1503 On the ARM, the offset starts at 0. */
1504 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1505 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT))
1506
1507 /* Update the data in CUM to advance over an argument
1508 of mode MODE and data type TYPE.
1509 (TYPE is null for libcalls where that information may not be available.) */
1510 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1511 (CUM).nregs += NUM_REGS2 (MODE, TYPE)
1512
1513 /* 1 if N is a possible register number for function argument passing.
1514 On the ARM, r0-r3 are used to pass args. */
1515 #define FUNCTION_ARG_REGNO_P(REGNO) (IN_RANGE ((REGNO), 0, 3))
1516
1517 \f
1518 /* Tail calling. */
1519
1520 /* A C expression that evaluates to true if it is ok to perform a sibling
1521 call to DECL. */
1522 #define FUNCTION_OK_FOR_SIBCALL(DECL) arm_function_ok_for_sibcall ((DECL))
1523
1524 /* Perform any actions needed for a function that is receiving a variable
1525 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1526 of the current parameter. PRETEND_SIZE is a variable that should be set to
1527 the amount of stack that must be pushed by the prolog to pretend that our
1528 caller pushed it.
1529
1530 Normally, this macro will push all remaining incoming registers on the
1531 stack and set PRETEND_SIZE to the length of the registers pushed.
1532
1533 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1534 named arg and all anonymous args onto the stack.
1535 XXX I know the prologue shouldn't be pushing registers, but it is faster
1536 that way. */
1537 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1538 { \
1539 cfun->machine->uses_anonymous_args = 1; \
1540 if ((CUM).nregs < NUM_ARG_REGS) \
1541 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \
1542 }
1543
1544 /* If your target environment doesn't prefix user functions with an
1545 underscore, you may wish to re-define this to prevent any conflicts.
1546 e.g. AOF may prefix mcount with an underscore. */
1547 #ifndef ARM_MCOUNT_NAME
1548 #define ARM_MCOUNT_NAME "*mcount"
1549 #endif
1550
1551 /* Call the function profiler with a given profile label. The Acorn
1552 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1553 On the ARM the full profile code will look like:
1554 .data
1555 LP1
1556 .word 0
1557 .text
1558 mov ip, lr
1559 bl mcount
1560 .word LP1
1561
1562 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1563 will output the .text section.
1564
1565 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1566 ``prof'' doesn't seem to mind about this! */
1567 #ifndef ARM_FUNCTION_PROFILER
1568 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1569 { \
1570 char temp[20]; \
1571 rtx sym; \
1572 \
1573 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1574 IP_REGNUM, LR_REGNUM); \
1575 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1576 fputc ('\n', STREAM); \
1577 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1578 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1579 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1580 }
1581 #endif
1582
1583 #ifndef THUMB_FUNCTION_PROFILER
1584 #define THUMB_FUNCTION_PROFILER(STREAM, LABELNO) \
1585 { \
1586 fprintf (STREAM, "\tmov\tip, lr\n"); \
1587 fprintf (STREAM, "\tbl\tmcount\n"); \
1588 fprintf (STREAM, "\t.word\tLP%d\n", LABELNO); \
1589 }
1590 #endif
1591
1592 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1593 if (TARGET_ARM) \
1594 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1595 else \
1596 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1597
1598 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1599 the stack pointer does not matter. The value is tested only in
1600 functions that have frame pointers.
1601 No definition is equivalent to always zero.
1602
1603 On the ARM, the function epilogue recovers the stack pointer from the
1604 frame. */
1605 #define EXIT_IGNORE_STACK 1
1606
1607 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1608
1609 /* Determine if the epilogue should be output as RTL.
1610 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1611 #define USE_RETURN_INSN(ISCOND) \
1612 (TARGET_ARM ? use_return_insn (ISCOND) : 0)
1613
1614 /* Definitions for register eliminations.
1615
1616 This is an array of structures. Each structure initializes one pair
1617 of eliminable registers. The "from" register number is given first,
1618 followed by "to". Eliminations of the same "from" register are listed
1619 in order of preference.
1620
1621 We have two registers that can be eliminated on the ARM. First, the
1622 arg pointer register can often be eliminated in favor of the stack
1623 pointer register. Secondly, the pseudo frame pointer register can always
1624 be eliminated; it is replaced with either the stack or the real frame
1625 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1626 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1627
1628 #define ELIMINABLE_REGS \
1629 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1630 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1631 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1632 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1633 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1634 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1635 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1636
1637 /* Given FROM and TO register numbers, say whether this elimination is
1638 allowed. Frame pointer elimination is automatically handled.
1639
1640 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1641 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1642 pointer, we must eliminate FRAME_POINTER_REGNUM into
1643 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1644 ARG_POINTER_REGNUM. */
1645 #define CAN_ELIMINATE(FROM, TO) \
1646 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1647 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1648 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1649 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1650 1)
1651
1652 /* Define the offset between two registers, one to be eliminated, and the
1653 other its replacement, at the start of a routine. */
1654 #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1655 do \
1656 { \
1657 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1658 } \
1659 while (0)
1660
1661 /* Note: This macro must match the code in thumb_function_prologue(). */
1662 #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1663 { \
1664 (OFFSET) = 0; \
1665 if ((FROM) == ARG_POINTER_REGNUM) \
1666 { \
1667 int count_regs = 0; \
1668 int regno; \
1669 for (regno = 8; regno < 13; regno ++) \
1670 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1671 count_regs ++; \
1672 if (count_regs) \
1673 (OFFSET) += 4 * count_regs; \
1674 count_regs = 0; \
1675 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \
1676 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1677 count_regs ++; \
1678 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\
1679 (OFFSET) += 4 * (count_regs + 1); \
1680 if (TARGET_BACKTRACE) \
1681 { \
1682 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
1683 (OFFSET) += 20; \
1684 else \
1685 (OFFSET) += 16; \
1686 } \
1687 } \
1688 if ((TO) == STACK_POINTER_REGNUM) \
1689 { \
1690 (OFFSET) += current_function_outgoing_args_size; \
1691 (OFFSET) += ROUND_UP (get_frame_size ()); \
1692 } \
1693 }
1694
1695 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1696 if (TARGET_ARM) \
1697 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET); \
1698 else \
1699 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET)
1700
1701 /* Special case handling of the location of arguments passed on the stack. */
1702 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1703
1704 /* Initialize data used by insn expanders. This is called from insn_emit,
1705 once for every function before code is generated. */
1706 #define INIT_EXPANDERS arm_init_expanders ()
1707
1708 /* Output assembler code for a block containing the constant parts
1709 of a trampoline, leaving space for the variable parts.
1710
1711 On the ARM, (if r8 is the static chain regnum, and remembering that
1712 referencing pc adds an offset of 8) the trampoline looks like:
1713 ldr r8, [pc, #0]
1714 ldr pc, [pc]
1715 .word static chain value
1716 .word function's address
1717 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1718 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1719 { \
1720 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1721 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1722 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1723 PC_REGNUM, PC_REGNUM); \
1724 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1725 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1726 }
1727
1728 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1729 Why - because it is easier. This code will always be branched to via
1730 a BX instruction and since the compiler magically generates the address
1731 of the function the linker has no opportunity to ensure that the
1732 bottom bit is set. Thus the processor will be in ARM mode when it
1733 reaches this code. So we duplicate the ARM trampoline code and add
1734 a switch into Thumb mode as well. */
1735 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1736 { \
1737 fprintf (FILE, "\t.code 32\n"); \
1738 fprintf (FILE, ".Ltrampoline_start:\n"); \
1739 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1740 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1741 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1742 IP_REGNUM, PC_REGNUM); \
1743 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1744 IP_REGNUM, IP_REGNUM); \
1745 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1746 fprintf (FILE, "\t.word\t0\n"); \
1747 fprintf (FILE, "\t.word\t0\n"); \
1748 fprintf (FILE, "\t.code 16\n"); \
1749 }
1750
1751 #define TRAMPOLINE_TEMPLATE(FILE) \
1752 if (TARGET_ARM) \
1753 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1754 else \
1755 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1756
1757 /* Length in units of the trampoline for entering a nested function. */
1758 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1759
1760 /* Alignment required for a trampoline in bits. */
1761 #define TRAMPOLINE_ALIGNMENT 32
1762
1763 /* Emit RTL insns to initialize the variable parts of a trampoline.
1764 FNADDR is an RTX for the address of the function's pure code.
1765 CXT is an RTX for the static chain value for the function. */
1766 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1767 { \
1768 emit_move_insn \
1769 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \
1770 emit_move_insn \
1771 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \
1772 }
1773
1774 \f
1775 /* Addressing modes, and classification of registers for them. */
1776 #define HAVE_POST_INCREMENT 1
1777 #define HAVE_PRE_INCREMENT TARGET_ARM
1778 #define HAVE_POST_DECREMENT TARGET_ARM
1779 #define HAVE_PRE_DECREMENT TARGET_ARM
1780
1781 /* Macros to check register numbers against specific register classes. */
1782
1783 /* These assume that REGNO is a hard or pseudo reg number.
1784 They give nonzero only if REGNO is a hard reg of the suitable class
1785 or a pseudo reg currently allocated to a suitable hard reg.
1786 Since they use reg_renumber, they are safe only once reg_renumber
1787 has been allocated, which happens in local-alloc.c. */
1788 #define TEST_REGNO(R, TEST, VALUE) \
1789 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1790
1791 /* On the ARM, don't allow the pc to be used. */
1792 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1793 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1794 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1795 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1796
1797 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1798 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1799 || (GET_MODE_SIZE (MODE) >= 4 \
1800 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1801
1802 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1803 (TARGET_THUMB \
1804 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1805 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1806
1807 /* For ARM code, we don't care about the mode, but for Thumb, the index
1808 must be suitable for use in a QImode load. */
1809 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1810 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1811
1812 /* Maximum number of registers that can appear in a valid memory address.
1813 Shifts in addresses can't be by a register. */
1814 #define MAX_REGS_PER_ADDRESS 2
1815
1816 /* Recognize any constant value that is a valid address. */
1817 /* XXX We can address any constant, eventually... */
1818
1819 #ifdef AOF_ASSEMBLER
1820
1821 #define CONSTANT_ADDRESS_P(X) \
1822 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1823
1824 #else
1825
1826 #define CONSTANT_ADDRESS_P(X) \
1827 (GET_CODE (X) == SYMBOL_REF \
1828 && (CONSTANT_POOL_ADDRESS_P (X) \
1829 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1830
1831 #endif /* AOF_ASSEMBLER */
1832
1833 /* Nonzero if the constant value X is a legitimate general operand.
1834 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1835
1836 On the ARM, allow any integer (invalid ones are removed later by insn
1837 patterns), nice doubles and symbol_refs which refer to the function's
1838 constant pool XXX.
1839
1840 When generating pic allow anything. */
1841 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1842
1843 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1844 ( GET_CODE (X) == CONST_INT \
1845 || GET_CODE (X) == CONST_DOUBLE \
1846 || CONSTANT_ADDRESS_P (X))
1847
1848 #define LEGITIMATE_CONSTANT_P(X) \
1849 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
1850
1851 /* Special characters prefixed to function names
1852 in order to encode attribute like information.
1853 Note, '@' and '*' have already been taken. */
1854 #define SHORT_CALL_FLAG_CHAR '^'
1855 #define LONG_CALL_FLAG_CHAR '#'
1856
1857 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1858 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1859
1860 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1861 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1862
1863 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1864 #define SUBTARGET_NAME_ENCODING_LENGTHS
1865 #endif
1866
1867 /* This is a C fragement for the inside of a switch statement.
1868 Each case label should return the number of characters to
1869 be stripped from the start of a function's name, if that
1870 name starts with the indicated character. */
1871 #define ARM_NAME_ENCODING_LENGTHS \
1872 case SHORT_CALL_FLAG_CHAR: return 1; \
1873 case LONG_CALL_FLAG_CHAR: return 1; \
1874 case '*': return 1; \
1875 SUBTARGET_NAME_ENCODING_LENGTHS
1876
1877 /* This has to be handled by a function because more than part of the
1878 ARM backend uses function name prefixes to encode attributes. */
1879 #undef STRIP_NAME_ENCODING
1880 #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
1881 (VAR) = arm_strip_name_encoding (SYMBOL_NAME)
1882
1883 /* This is how to output a reference to a user-level label named NAME.
1884 `assemble_name' uses this. */
1885 #undef ASM_OUTPUT_LABELREF
1886 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1887 asm_fprintf (FILE, "%U%s", arm_strip_name_encoding (NAME))
1888
1889 /* If we are referencing a function that is weak then encode a long call
1890 flag in the function name, otherwise if the function is static or
1891 or known to be defined in this file then encode a short call flag.
1892 This macro is used inside the ENCODE_SECTION macro. */
1893 #define ARM_ENCODE_CALL_TYPE(decl) \
1894 if (TREE_CODE (decl) == FUNCTION_DECL) \
1895 { \
1896 if (DECL_WEAK (decl)) \
1897 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR); \
1898 else if (! TREE_PUBLIC (decl)) \
1899 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR); \
1900 }
1901
1902 /* Symbols in the text segment can be accessed without indirecting via the
1903 constant pool; it may take an extra binary operation, but this is still
1904 faster than indirecting via memory. Don't do this when not optimizing,
1905 since we won't be calculating al of the offsets necessary to do this
1906 simplification. */
1907 /* This doesn't work with AOF syntax, since the string table may be in
1908 a different AREA. */
1909 #ifndef AOF_ASSEMBLER
1910 #define ENCODE_SECTION_INFO(decl) \
1911 { \
1912 if (optimize > 0 && TREE_CONSTANT (decl) \
1913 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1914 { \
1915 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1916 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1917 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1918 } \
1919 ARM_ENCODE_CALL_TYPE (decl) \
1920 }
1921 #else
1922 #define ENCODE_SECTION_INFO(decl) \
1923 { \
1924 ARM_ENCODE_CALL_TYPE (decl) \
1925 }
1926 #endif
1927
1928 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1929 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1930
1931 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1932 and check its validity for a certain class.
1933 We have two alternate definitions for each of them.
1934 The usual definition accepts all pseudo regs; the other rejects
1935 them unless they have been allocated suitable hard regs.
1936 The symbol REG_OK_STRICT causes the latter definition to be used. */
1937 #ifndef REG_OK_STRICT
1938
1939 #define ARM_REG_OK_FOR_BASE_P(X) \
1940 (REGNO (X) <= LAST_ARM_REGNUM \
1941 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1942 || REGNO (X) == FRAME_POINTER_REGNUM \
1943 || REGNO (X) == ARG_POINTER_REGNUM)
1944
1945 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1946 (REGNO (X) <= LAST_LO_REGNUM \
1947 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1948 || (GET_MODE_SIZE (MODE) >= 4 \
1949 && (REGNO (X) == STACK_POINTER_REGNUM \
1950 || (X) == hard_frame_pointer_rtx \
1951 || (X) == arg_pointer_rtx)))
1952
1953 #else /* REG_OK_STRICT */
1954
1955 #define ARM_REG_OK_FOR_BASE_P(X) \
1956 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
1957
1958 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1959 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
1960
1961 #endif /* REG_OK_STRICT */
1962
1963 /* Now define some helpers in terms of the above. */
1964
1965 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1966 (TARGET_THUMB \
1967 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
1968 : ARM_REG_OK_FOR_BASE_P (X))
1969
1970 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
1971
1972 /* For Thumb, a valid index register is anything that can be used in
1973 a byte load instruction. */
1974 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
1975
1976 /* Nonzero if X is a hard reg that can be used as an index
1977 or if it is a pseudo reg. On the Thumb, the stack pointer
1978 is not suitable. */
1979 #define REG_OK_FOR_INDEX_P(X) \
1980 (TARGET_THUMB \
1981 ? THUMB_REG_OK_FOR_INDEX_P (X) \
1982 : ARM_REG_OK_FOR_INDEX_P (X))
1983
1984 \f
1985 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1986 that is a valid memory address for an instruction.
1987 The MODE argument is the machine mode for the MEM expression
1988 that wants to use this address.
1989
1990 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1991
1992 /* --------------------------------arm version----------------------------- */
1993 #define ARM_BASE_REGISTER_RTX_P(X) \
1994 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
1995
1996 #define ARM_INDEX_REGISTER_RTX_P(X) \
1997 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
1998
1999 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
2000 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
2001 only be small constants. */
2002 #define ARM_GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
2003 do \
2004 { \
2005 HOST_WIDE_INT range; \
2006 enum rtx_code code = GET_CODE (INDEX); \
2007 \
2008 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
2009 { \
2010 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
2011 && INTVAL (INDEX) > -1024 \
2012 && (INTVAL (INDEX) & 3) == 0) \
2013 goto LABEL; \
2014 } \
2015 else \
2016 { \
2017 if (ARM_INDEX_REGISTER_RTX_P (INDEX) \
2018 && GET_MODE_SIZE (MODE) <= 4) \
2019 goto LABEL; \
2020 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
2021 && (! arm_arch4 || (MODE) != HImode)) \
2022 { \
2023 rtx xiop0 = XEXP (INDEX, 0); \
2024 rtx xiop1 = XEXP (INDEX, 1); \
2025 if (ARM_INDEX_REGISTER_RTX_P (xiop0) \
2026 && power_of_two_operand (xiop1, SImode)) \
2027 goto LABEL; \
2028 if (ARM_INDEX_REGISTER_RTX_P (xiop1) \
2029 && power_of_two_operand (xiop0, SImode)) \
2030 goto LABEL; \
2031 } \
2032 if (GET_MODE_SIZE (MODE) <= 4 \
2033 && (code == LSHIFTRT || code == ASHIFTRT \
2034 || code == ASHIFT || code == ROTATERT) \
2035 && (! arm_arch4 || (MODE) != HImode)) \
2036 { \
2037 rtx op = XEXP (INDEX, 1); \
2038 if (ARM_INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
2039 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
2040 && INTVAL (op) <= 31) \
2041 goto LABEL; \
2042 } \
2043 /* NASTY: Since this limits the addressing of unsigned \
2044 byte loads. */ \
2045 range = ((MODE) == HImode || (MODE) == QImode) \
2046 ? (arm_arch4 ? 256 : 4095) : 4096; \
2047 if (code == CONST_INT && INTVAL (INDEX) < range \
2048 && INTVAL (INDEX) > -range) \
2049 goto LABEL; \
2050 } \
2051 } \
2052 while (0)
2053
2054 /* Jump to LABEL if X is a valid address RTX. This must take
2055 REG_OK_STRICT into account when deciding about valid registers.
2056
2057 Allow REG, REG+REG, REG+INDEX, INDEX+REG, REG-INDEX, and non
2058 floating SYMBOL_REF to the constant pool. Allow REG-only and
2059 AUTINC-REG if handling TImode or HImode. Other symbol refs must be
2060 forced though a static cell to ensure addressability. */
2061 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2062 { \
2063 if (ARM_BASE_REGISTER_RTX_P (X)) \
2064 goto LABEL; \
2065 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2066 && GET_CODE (XEXP (X, 0)) == REG \
2067 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
2068 goto LABEL; \
2069 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2070 && (GET_CODE (X) == LABEL_REF \
2071 || (GET_CODE (X) == CONST \
2072 && GET_CODE (XEXP ((X), 0)) == PLUS \
2073 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
2074 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
2075 goto LABEL; \
2076 else if ((MODE) == TImode) \
2077 ; \
2078 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
2079 { \
2080 if (GET_CODE (X) == PLUS && ARM_BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2081 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2082 { \
2083 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
2084 if (val == 4 || val == -4 || val == -8) \
2085 goto LABEL; \
2086 } \
2087 } \
2088 else if (GET_CODE (X) == PLUS) \
2089 { \
2090 rtx xop0 = XEXP (X, 0); \
2091 rtx xop1 = XEXP (X, 1); \
2092 \
2093 if (ARM_BASE_REGISTER_RTX_P (xop0)) \
2094 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
2095 else if (ARM_BASE_REGISTER_RTX_P (xop1)) \
2096 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
2097 } \
2098 /* Reload currently can't handle MINUS, so disable this for now */ \
2099 /* else if (GET_CODE (X) == MINUS) \
2100 { \
2101 rtx xop0 = XEXP (X,0); \
2102 rtx xop1 = XEXP (X,1); \
2103 \
2104 if (ARM_BASE_REGISTER_RTX_P (xop0)) \
2105 ARM_GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
2106 } */ \
2107 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2108 && GET_CODE (X) == SYMBOL_REF \
2109 && CONSTANT_POOL_ADDRESS_P (X) \
2110 && ! (flag_pic \
2111 && symbol_mentioned_p (get_pool_constant (X)))) \
2112 goto LABEL; \
2113 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
2114 && (GET_MODE_SIZE (MODE) <= 4) \
2115 && GET_CODE (XEXP (X, 0)) == REG \
2116 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
2117 goto LABEL; \
2118 }
2119
2120 /* ---------------------thumb version----------------------------------*/
2121 #define THUMB_LEGITIMATE_OFFSET(MODE, VAL) \
2122 (GET_MODE_SIZE (MODE) == 1 ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \
2123 : GET_MODE_SIZE (MODE) == 2 ? ((unsigned HOST_WIDE_INT) (VAL) < 64 \
2124 && ((VAL) & 1) == 0) \
2125 : ((VAL) >= 0 && ((VAL) + GET_MODE_SIZE (MODE)) <= 128 \
2126 && ((VAL) & 3) == 0))
2127
2128 /* The AP may be eliminated to either the SP or the FP, so we use the
2129 least common denominator, e.g. SImode, and offsets from 0 to 64. */
2130
2131 /* ??? Verify whether the above is the right approach. */
2132
2133 /* ??? Also, the FP may be eliminated to the SP, so perhaps that
2134 needs special handling also. */
2135
2136 /* ??? Look at how the mips16 port solves this problem. It probably uses
2137 better ways to solve some of these problems. */
2138
2139 /* Although it is not incorrect, we don't accept QImode and HImode
2140 addresses based on the frame pointer or arg pointer until the
2141 reload pass starts. This is so that eliminating such addresses
2142 into stack based ones won't produce impossible code. */
2143 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2144 { \
2145 /* ??? Not clear if this is right. Experiment. */ \
2146 if (GET_MODE_SIZE (MODE) < 4 \
2147 && ! (reload_in_progress || reload_completed) \
2148 && ( reg_mentioned_p (frame_pointer_rtx, X) \
2149 || reg_mentioned_p (arg_pointer_rtx, X) \
2150 || reg_mentioned_p (virtual_incoming_args_rtx, X) \
2151 || reg_mentioned_p (virtual_outgoing_args_rtx, X) \
2152 || reg_mentioned_p (virtual_stack_dynamic_rtx, X) \
2153 || reg_mentioned_p (virtual_stack_vars_rtx, X))) \
2154 ; \
2155 /* Accept any base register. SP only in SImode or larger. */ \
2156 else if (GET_CODE (X) == REG \
2157 && THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE)) \
2158 goto WIN; \
2159 /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */ \
2160 else if (GET_MODE_SIZE (MODE) >= 4 && CONSTANT_P (X) \
2161 && CONSTANT_POOL_ADDRESS_P (X) && ! flag_pic) \
2162 goto WIN; \
2163 /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */ \
2164 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2165 && (GET_CODE (X) == LABEL_REF \
2166 || (GET_CODE (X) == CONST \
2167 && GET_CODE (XEXP (X, 0)) == PLUS \
2168 && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF \
2169 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))) \
2170 goto WIN; \
2171 /* Post-inc indexing only supported for SImode and larger. */ \
2172 else if (GET_CODE (X) == POST_INC && GET_MODE_SIZE (MODE) >= 4 \
2173 && GET_CODE (XEXP (X, 0)) == REG \
2174 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
2175 goto WIN; \
2176 else if (GET_CODE (X) == PLUS) \
2177 { \
2178 /* REG+REG address can be any two index registers. */ \
2179 /* We disallow FRAME+REG addressing since we know that FRAME \
2180 will be replaced with STACK, and SP relative addressing only \
2181 permits SP+OFFSET. */ \
2182 if (GET_MODE_SIZE (MODE) <= 4 \
2183 && GET_CODE (XEXP (X, 0)) == REG \
2184 && GET_CODE (XEXP (X, 1)) == REG \
2185 && XEXP (X, 0) != frame_pointer_rtx \
2186 && XEXP (X, 1) != frame_pointer_rtx \
2187 && XEXP (X, 0) != virtual_stack_vars_rtx \
2188 && XEXP (X, 1) != virtual_stack_vars_rtx \
2189 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2190 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 1))) \
2191 goto WIN; \
2192 /* REG+const has 5-7 bit offset for non-SP registers. */ \
2193 else if (GET_CODE (XEXP (X, 0)) == REG \
2194 && (THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2195 || XEXP (X, 0) == arg_pointer_rtx) \
2196 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2197 && THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
2198 goto WIN; \
2199 /* REG+const has 10 bit offset for SP, but only SImode and \
2200 larger is supported. */ \
2201 /* ??? Should probably check for DI/DFmode overflow here \
2202 just like GO_IF_LEGITIMATE_OFFSET does. */ \
2203 else if (GET_CODE (XEXP (X, 0)) == REG \
2204 && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \
2205 && GET_MODE_SIZE (MODE) >= 4 \
2206 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2207 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (X, 1)) \
2208 + GET_MODE_SIZE (MODE)) <= 1024 \
2209 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2210 goto WIN; \
2211 else if (GET_CODE (XEXP (X, 0)) == REG \
2212 && REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \
2213 && GET_MODE_SIZE (MODE) >= 4 \
2214 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2215 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2216 goto WIN; \
2217 } \
2218 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2219 && GET_CODE (X) == SYMBOL_REF \
2220 && CONSTANT_POOL_ADDRESS_P (X) \
2221 && ! (flag_pic \
2222 && symbol_mentioned_p (get_pool_constant (X)))) \
2223 goto WIN; \
2224 }
2225
2226 /* ------------------------------------------------------------------- */
2227 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2228 if (TARGET_ARM) \
2229 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2230 else /* if (TARGET_THUMB) */ \
2231 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2232 /* ------------------------------------------------------------------- */
2233 \f
2234 /* Try machine-dependent ways of modifying an illegitimate address
2235 to be legitimate. If we find one, return the new, valid address.
2236 This macro is used in only one place: `memory_address' in explow.c.
2237
2238 OLDX is the address as it was before break_out_memory_refs was called.
2239 In some cases it is useful to look at this to decide what needs to be done.
2240
2241 MODE and WIN are passed so that this macro can use
2242 GO_IF_LEGITIMATE_ADDRESS.
2243
2244 It is always safe for this macro to do nothing. It exists to recognize
2245 opportunities to optimize the output.
2246
2247 On the ARM, try to convert [REG, #BIGCONST]
2248 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
2249 where VALIDCONST == 0 in case of TImode. */
2250 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2251 { \
2252 if (GET_CODE (X) == PLUS) \
2253 { \
2254 rtx xop0 = XEXP (X, 0); \
2255 rtx xop1 = XEXP (X, 1); \
2256 \
2257 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
2258 xop0 = force_reg (SImode, xop0); \
2259 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2260 xop1 = force_reg (SImode, xop1); \
2261 if (ARM_BASE_REGISTER_RTX_P (xop0) \
2262 && GET_CODE (xop1) == CONST_INT) \
2263 { \
2264 HOST_WIDE_INT n, low_n; \
2265 rtx base_reg, val; \
2266 n = INTVAL (xop1); \
2267 \
2268 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
2269 { \
2270 low_n = n & 0x0f; \
2271 n &= ~0x0f; \
2272 if (low_n > 4) \
2273 { \
2274 n += 16; \
2275 low_n -= 16; \
2276 } \
2277 } \
2278 else \
2279 { \
2280 low_n = ((MODE) == TImode ? 0 \
2281 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
2282 n -= low_n; \
2283 } \
2284 base_reg = gen_reg_rtx (SImode); \
2285 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
2286 GEN_INT (n)), NULL_RTX); \
2287 emit_move_insn (base_reg, val); \
2288 (X) = (low_n == 0 ? base_reg \
2289 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
2290 } \
2291 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
2292 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
2293 } \
2294 else if (GET_CODE (X) == MINUS) \
2295 { \
2296 rtx xop0 = XEXP (X, 0); \
2297 rtx xop1 = XEXP (X, 1); \
2298 \
2299 if (CONSTANT_P (xop0)) \
2300 xop0 = force_reg (SImode, xop0); \
2301 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2302 xop1 = force_reg (SImode, xop1); \
2303 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
2304 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
2305 } \
2306 if (flag_pic) \
2307 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2308 if (memory_address_p (MODE, X)) \
2309 goto WIN; \
2310 }
2311
2312 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2313 if (flag_pic) \
2314 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX);
2315
2316 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2317 if (TARGET_ARM) \
2318 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) \
2319 else \
2320 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN)
2321
2322 /* Go to LABEL if ADDR (a legitimate address expression)
2323 has an effect that depends on the machine mode it is used for. */
2324 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2325 { \
2326 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2327 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2328 goto LABEL; \
2329 }
2330
2331 /* Nothing helpful to do for the Thumb */
2332 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2333 if (TARGET_ARM) \
2334 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2335 \f
2336
2337 /* Specify the machine mode that this machine uses
2338 for the index in the tablejump instruction. */
2339 #define CASE_VECTOR_MODE Pmode
2340
2341 /* Define as C expression which evaluates to nonzero if the tablejump
2342 instruction expects the table to contain offsets from the address of the
2343 table.
2344 Do not define this if the table should contain absolute addresses. */
2345 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2346
2347 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2348 unsigned is probably best, but may break some code. */
2349 #ifndef DEFAULT_SIGNED_CHAR
2350 #define DEFAULT_SIGNED_CHAR 0
2351 #endif
2352
2353 /* Don't cse the address of the function being compiled. */
2354 #define NO_RECURSIVE_FUNCTION_CSE 1
2355
2356 /* Max number of bytes we can move from memory to memory
2357 in one reasonably fast instruction. */
2358 #define MOVE_MAX 4
2359
2360 #undef MOVE_RATIO
2361 #define MOVE_RATIO (arm_is_xscale ? 4 : 2)
2362
2363 /* Define if operations between registers always perform the operation
2364 on the full register even if a narrower mode is specified. */
2365 #define WORD_REGISTER_OPERATIONS
2366
2367 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2368 will either zero-extend or sign-extend. The value of this macro should
2369 be the code that says which one of the two operations is implicitly
2370 done, NIL if none. */
2371 #define LOAD_EXTEND_OP(MODE) \
2372 (TARGET_THUMB ? ZERO_EXTEND : \
2373 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2374 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2375
2376 /* Nonzero if access to memory by bytes is slow and undesirable. */
2377 #define SLOW_BYTE_ACCESS 0
2378
2379 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2380
2381 /* Immediate shift counts are truncated by the output routines (or was it
2382 the assembler?). Shift counts in a register are truncated by ARM. Note
2383 that the native compiler puts too large (> 32) immediate shift counts
2384 into a register and shifts by the register, letting the ARM decide what
2385 to do instead of doing that itself. */
2386 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2387 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2388 On the arm, Y in a register is used modulo 256 for the shift. Only for
2389 rotates is modulo 32 used. */
2390 /* #define SHIFT_COUNT_TRUNCATED 1 */
2391
2392 /* All integers have the same format so truncation is easy. */
2393 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2394
2395 /* Calling from registers is a massive pain. */
2396 #define NO_FUNCTION_CSE 1
2397
2398 /* Chars and shorts should be passed as ints. */
2399 #define PROMOTE_PROTOTYPES 1
2400
2401 /* The machine modes of pointers and functions */
2402 #define Pmode SImode
2403 #define FUNCTION_MODE Pmode
2404
2405 #define ARM_FRAME_RTX(X) \
2406 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2407 || (X) == arg_pointer_rtx)
2408
2409 #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \
2410 return arm_rtx_costs (X, CODE, OUTER_CODE);
2411
2412 /* Moves to and from memory are quite expensive */
2413 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2414 (TARGET_ARM ? 10 : \
2415 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2416 * (CLASS == LO_REGS ? 1 : 2)))
2417
2418 /* All address computations that can be done are free, but rtx cost returns
2419 the same for practically all of them. So we weight the different types
2420 of address here in the order (most pref first):
2421 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
2422 #define ARM_ADDRESS_COST(X) \
2423 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
2424 || GET_CODE (X) == SYMBOL_REF) \
2425 ? 0 \
2426 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
2427 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
2428 ? 10 \
2429 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
2430 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
2431 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
2432 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
2433 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
2434 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
2435 ? 1 : 0)) \
2436 : 4)))))
2437
2438 #define THUMB_ADDRESS_COST(X) \
2439 ((GET_CODE (X) == REG \
2440 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
2441 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \
2442 ? 1 : 2)
2443
2444 #define ADDRESS_COST(X) \
2445 (TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X))
2446
2447 /* Try to generate sequences that don't involve branches, we can then use
2448 conditional instructions */
2449 #define BRANCH_COST \
2450 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2451 \f
2452 /* Position Independent Code. */
2453 /* We decide which register to use based on the compilation options and
2454 the assembler in use; this is more general than the APCS restriction of
2455 using sb (r9) all the time. */
2456 extern int arm_pic_register;
2457
2458 /* Used when parsing command line option -mpic-register=. */
2459 extern const char * arm_pic_register_string;
2460
2461 /* The register number of the register used to address a table of static
2462 data addresses in memory. */
2463 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2464
2465 #define FINALIZE_PIC arm_finalize_pic (1)
2466
2467 /* We can't directly access anything that contains a symbol,
2468 nor can we indirect via the constant pool. */
2469 #define LEGITIMATE_PIC_OPERAND_P(X) \
2470 ( ! symbol_mentioned_p (X) \
2471 && ! label_mentioned_p (X) \
2472 && (! CONSTANT_POOL_ADDRESS_P (X) \
2473 || ( ! symbol_mentioned_p (get_pool_constant (X)) \
2474 && ! label_mentioned_p (get_pool_constant (X)))))
2475
2476 /* We need to know when we are making a constant pool; this determines
2477 whether data needs to be in the GOT or can be referenced via a GOT
2478 offset. */
2479 extern int making_const_table;
2480 \f
2481 /* Handle pragmas for compatibility with Intel's compilers. */
2482 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
2483 cpp_register_pragma (PFILE, 0, "long_calls", arm_pr_long_calls); \
2484 cpp_register_pragma (PFILE, 0, "no_long_calls", arm_pr_no_long_calls); \
2485 cpp_register_pragma (PFILE, 0, "long_calls_off", arm_pr_long_calls_off); \
2486 } while (0)
2487
2488 /* Condition code information. */
2489 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2490 return the mode to be used for the comparison.
2491 CCFPEmode should be used with floating inequalities,
2492 CCFPmode should be used with floating equalities.
2493 CC_NOOVmode should be used with SImode integer equalities.
2494 CC_Zmode should be used if only the Z flag is set correctly
2495 CCmode should be used otherwise. */
2496
2497 #define EXTRA_CC_MODES \
2498 CC(CC_NOOVmode, "CC_NOOV") \
2499 CC(CC_Zmode, "CC_Z") \
2500 CC(CC_SWPmode, "CC_SWP") \
2501 CC(CCFPmode, "CCFP") \
2502 CC(CCFPEmode, "CCFPE") \
2503 CC(CC_DNEmode, "CC_DNE") \
2504 CC(CC_DEQmode, "CC_DEQ") \
2505 CC(CC_DLEmode, "CC_DLE") \
2506 CC(CC_DLTmode, "CC_DLT") \
2507 CC(CC_DGEmode, "CC_DGE") \
2508 CC(CC_DGTmode, "CC_DGT") \
2509 CC(CC_DLEUmode, "CC_DLEU") \
2510 CC(CC_DLTUmode, "CC_DLTU") \
2511 CC(CC_DGEUmode, "CC_DGEU") \
2512 CC(CC_DGTUmode, "CC_DGTU") \
2513 CC(CC_Cmode, "CC_C")
2514
2515 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2516
2517 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2518
2519 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2520 do \
2521 { \
2522 if (GET_CODE (OP1) == CONST_INT \
2523 && ! (const_ok_for_arm (INTVAL (OP1)) \
2524 || (const_ok_for_arm (- INTVAL (OP1))))) \
2525 { \
2526 rtx const_op = OP1; \
2527 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2528 OP1 = const_op; \
2529 } \
2530 } \
2531 while (0)
2532
2533 #define STORE_FLAG_VALUE 1
2534
2535 \f
2536
2537 /* Gcc puts the pool in the wrong place for ARM, since we can only
2538 load addresses a limited distance around the pc. We do some
2539 special munging to move the constant pool values to the correct
2540 point in the code. */
2541 #define MACHINE_DEPENDENT_REORG(INSN) \
2542 arm_reorg (INSN); \
2543
2544 #undef ASM_APP_OFF
2545 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2546
2547 /* Output an internal label definition. */
2548 #ifndef ASM_OUTPUT_INTERNAL_LABEL
2549 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
2550 do \
2551 { \
2552 char * s = (char *) alloca (40 + strlen (PREFIX)); \
2553 \
2554 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
2555 && !strcmp (PREFIX, "L")) \
2556 { \
2557 arm_ccfsm_state = 0; \
2558 arm_target_insn = NULL; \
2559 } \
2560 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
2561 ASM_OUTPUT_LABEL (STREAM, s); \
2562 } \
2563 while (0)
2564 #endif
2565
2566 /* Output a push or a pop instruction (only used when profiling). */
2567 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2568 if (TARGET_ARM) \
2569 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2570 STACK_POINTER_REGNUM, REGNO); \
2571 else \
2572 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO)
2573
2574
2575 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2576 if (TARGET_ARM) \
2577 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2578 STACK_POINTER_REGNUM, REGNO); \
2579 else \
2580 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO)
2581
2582 /* This is how to output a label which precedes a jumptable. Since
2583 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2584 #undef ASM_OUTPUT_CASE_LABEL
2585 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2586 do \
2587 { \
2588 if (TARGET_THUMB) \
2589 ASM_OUTPUT_ALIGN (FILE, 2); \
2590 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
2591 } \
2592 while (0)
2593
2594 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2595 do \
2596 { \
2597 if (TARGET_THUMB) \
2598 { \
2599 if (is_called_in_ARM_mode (DECL)) \
2600 fprintf (STREAM, "\t.code 32\n") ; \
2601 else \
2602 fprintf (STREAM, "\t.thumb_func\n") ; \
2603 } \
2604 if (TARGET_POKE_FUNCTION_NAME) \
2605 arm_poke_function_name (STREAM, (char *) NAME); \
2606 } \
2607 while (0)
2608
2609 /* For aliases of functions we use .thumb_set instead. */
2610 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2611 do \
2612 { \
2613 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2614 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2615 \
2616 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2617 { \
2618 fprintf (FILE, "\t.thumb_set "); \
2619 assemble_name (FILE, LABEL1); \
2620 fprintf (FILE, ","); \
2621 assemble_name (FILE, LABEL2); \
2622 fprintf (FILE, "\n"); \
2623 } \
2624 else \
2625 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2626 } \
2627 while (0)
2628
2629 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2630 /* To support -falign-* switches we need to use .p2align so
2631 that alignment directives in code sections will be padded
2632 with no-op instructions, rather than zeroes. */
2633 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
2634 if ((LOG) != 0) \
2635 { \
2636 if ((MAX_SKIP) == 0) \
2637 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
2638 else \
2639 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2640 (LOG), (MAX_SKIP)); \
2641 }
2642 #endif
2643 \f
2644 /* Only perform branch elimination (by making instructions conditional) if
2645 we're optimising. Otherwise it's of no use anyway. */
2646 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2647 if (TARGET_ARM && optimize) \
2648 arm_final_prescan_insn (INSN); \
2649 else if (TARGET_THUMB) \
2650 thumb_final_prescan_insn (INSN)
2651
2652 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2653 (CODE == '@' || CODE == '|' \
2654 || (TARGET_ARM && (CODE == '?')) \
2655 || (TARGET_THUMB && (CODE == '_')))
2656
2657 /* Output an operand of an instruction. */
2658 #define PRINT_OPERAND(STREAM, X, CODE) \
2659 arm_print_operand (STREAM, X, CODE)
2660
2661 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2662 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2663 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2664 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2665 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2666 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2667 : 0))))
2668
2669 /* Output the address of an operand. */
2670 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2671 { \
2672 int is_minus = GET_CODE (X) == MINUS; \
2673 \
2674 if (GET_CODE (X) == REG) \
2675 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2676 else if (GET_CODE (X) == PLUS || is_minus) \
2677 { \
2678 rtx base = XEXP (X, 0); \
2679 rtx index = XEXP (X, 1); \
2680 HOST_WIDE_INT offset = 0; \
2681 if (GET_CODE (base) != REG) \
2682 { \
2683 /* Ensure that BASE is a register */ \
2684 /* (one of them must be). */ \
2685 rtx temp = base; \
2686 base = index; \
2687 index = temp; \
2688 } \
2689 switch (GET_CODE (index)) \
2690 { \
2691 case CONST_INT: \
2692 offset = INTVAL (index); \
2693 if (is_minus) \
2694 offset = -offset; \
2695 asm_fprintf (STREAM, "[%r, #%d]", \
2696 REGNO (base), offset); \
2697 break; \
2698 \
2699 case REG: \
2700 asm_fprintf (STREAM, "[%r, %s%r]", \
2701 REGNO (base), is_minus ? "-" : "", \
2702 REGNO (index)); \
2703 break; \
2704 \
2705 case MULT: \
2706 case ASHIFTRT: \
2707 case LSHIFTRT: \
2708 case ASHIFT: \
2709 case ROTATERT: \
2710 { \
2711 asm_fprintf (STREAM, "[%r, %s%r", \
2712 REGNO (base), is_minus ? "-" : "", \
2713 REGNO (XEXP (index, 0))); \
2714 arm_print_operand (STREAM, index, 'S'); \
2715 fputs ("]", STREAM); \
2716 break; \
2717 } \
2718 \
2719 default: \
2720 abort(); \
2721 } \
2722 } \
2723 else if ( GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC\
2724 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC)\
2725 { \
2726 extern int output_memory_reference_mode; \
2727 \
2728 if (GET_CODE (XEXP (X, 0)) != REG) \
2729 abort (); \
2730 \
2731 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2732 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2733 REGNO (XEXP (X, 0)), \
2734 GET_CODE (X) == PRE_DEC ? "-" : "", \
2735 GET_MODE_SIZE (output_memory_reference_mode));\
2736 else \
2737 asm_fprintf (STREAM, "[%r], #%s%d", \
2738 REGNO (XEXP (X, 0)), \
2739 GET_CODE (X) == POST_DEC ? "-" : "", \
2740 GET_MODE_SIZE (output_memory_reference_mode));\
2741 } \
2742 else output_addr_const (STREAM, X); \
2743 }
2744
2745 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2746 { \
2747 if (GET_CODE (X) == REG) \
2748 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2749 else if (GET_CODE (X) == POST_INC) \
2750 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2751 else if (GET_CODE (X) == PLUS) \
2752 { \
2753 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2754 asm_fprintf (STREAM, "[%r, #%d]", \
2755 REGNO (XEXP (X, 0)), \
2756 (int) INTVAL (XEXP (X, 1))); \
2757 else \
2758 asm_fprintf (STREAM, "[%r, %r]", \
2759 REGNO (XEXP (X, 0)), \
2760 REGNO (XEXP (X, 1))); \
2761 } \
2762 else \
2763 output_addr_const (STREAM, X); \
2764 }
2765
2766 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2767 if (TARGET_ARM) \
2768 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2769 else \
2770 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2771
2772 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2773 Used for C++ multiple inheritance. */
2774 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2775 do \
2776 { \
2777 int mi_delta = (DELTA); \
2778 const char *const mi_op = mi_delta < 0 ? "sub" : "add"; \
2779 int shift = 0; \
2780 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
2781 ? 1 : 0); \
2782 if (mi_delta < 0) \
2783 mi_delta = - mi_delta; \
2784 while (mi_delta != 0) \
2785 { \
2786 if ((mi_delta & (3 << shift)) == 0) \
2787 shift += 2; \
2788 else \
2789 { \
2790 asm_fprintf (FILE, "\t%s\t%r, %r, #%d\n", \
2791 mi_op, this_regno, this_regno, \
2792 mi_delta & (0xff << shift)); \
2793 mi_delta &= ~(0xff << shift); \
2794 shift += 8; \
2795 } \
2796 } \
2797 fputs ("\tb\t", FILE); \
2798 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2799 if (NEED_PLT_RELOC) \
2800 fputs ("(PLT)", FILE); \
2801 fputc ('\n', FILE); \
2802 } \
2803 while (0)
2804
2805 /* A C expression whose value is RTL representing the value of the return
2806 address for the frame COUNT steps up from the current frame. */
2807
2808 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2809 arm_return_addr (COUNT, FRAME)
2810
2811 /* Mask of the bits in the PC that contain the real return address
2812 when running in 26-bit mode. */
2813 #define RETURN_ADDR_MASK26 (0x03fffffc)
2814
2815 /* Pick up the return address upon entry to a procedure. Used for
2816 dwarf2 unwind information. This also enables the table driven
2817 mechanism. */
2818 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2819 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2820
2821 /* Used to mask out junk bits from the return address, such as
2822 processor state, interrupt status, condition codes and the like. */
2823 #define MASK_RETURN_ADDR \
2824 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2825 in 26 bit mode, the condition codes must be masked out of the \
2826 return address. This does not apply to ARM6 and later processors \
2827 when running in 32 bit mode. */ \
2828 ((!TARGET_APCS_32) ? (GEN_INT (RETURN_ADDR_MASK26)) \
2829 : (GEN_INT ((unsigned long)0xffffffff)))
2830
2831 \f
2832 /* Define the codes that are matched by predicates in arm.c */
2833 #define PREDICATE_CODES \
2834 {"s_register_operand", {SUBREG, REG}}, \
2835 {"arm_hard_register_operand", {REG}}, \
2836 {"f_register_operand", {SUBREG, REG}}, \
2837 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2838 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2839 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2840 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2841 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2842 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2843 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2844 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2845 {"offsettable_memory_operand", {MEM}}, \
2846 {"bad_signed_byte_operand", {MEM}}, \
2847 {"alignable_memory_operand", {MEM}}, \
2848 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2849 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2850 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2851 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2852 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2853 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2854 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2855 {"load_multiple_operation", {PARALLEL}}, \
2856 {"store_multiple_operation", {PARALLEL}}, \
2857 {"equality_operator", {EQ, NE}}, \
2858 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2859 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2860 UNGE, UNGT}}, \
2861 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2862 {"const_shift_operand", {CONST_INT}}, \
2863 {"multi_register_push", {PARALLEL}}, \
2864 {"cc_register", {REG}}, \
2865 {"logical_binary_operator", {AND, IOR, XOR}}, \
2866 {"dominant_cc_register", {REG}},
2867
2868 /* Define this if you have special predicates that know special things
2869 about modes. Genrecog will warn about certain forms of
2870 match_operand without a mode; if the operand predicate is listed in
2871 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2872 #define SPECIAL_MODE_PREDICATES \
2873 "cc_register", "dominant_cc_register",
2874
2875 enum arm_builtins
2876 {
2877 ARM_BUILTIN_CLZ,
2878 ARM_BUILTIN_MAX
2879 };
2880 #endif /* ! GCC_ARM_H */
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