1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
47 #include "target-def.h"
49 /* 1 if the caller has placed an "unimp" insn immediately after the call.
50 This is used in v8 code when calling a function that returns a structure.
51 v9 doesn't have this. Be careful to have this test be the same as that
54 #define SKIP_CALLERS_UNIMP_P \
55 (!TARGET_ARCH64 && current_function_returns_struct \
56 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
57 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
60 /* Global variables for machine-dependent things. */
62 /* Size of frame. Need to know this to emit return insns from leaf procedures.
63 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
64 reload pass. This is important as the value is later used in insn
65 scheduling (to see what can go in a delay slot).
66 APPARENT_FSIZE is the size of the stack less the register save area and less
67 the outgoing argument area. It is used when saving call preserved regs. */
68 static int apparent_fsize
;
69 static int actual_fsize
;
71 /* Number of live general or floating point registers needed to be
72 saved (as 4-byte quantities). */
73 static int num_gfregs
;
75 /* Save the operands last given to a compare for use when we
76 generate a scc or bcc insn. */
77 rtx sparc_compare_op0
, sparc_compare_op1
;
79 /* Coordinate with the md file wrt special insns created by
80 sparc_nonflat_function_epilogue. */
81 bool sparc_emitting_epilogue
;
83 /* Vector to say how input registers are mapped to output registers.
84 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
85 eliminate it. You must use -fomit-frame-pointer to get that. */
86 char leaf_reg_remap
[] =
87 { 0, 1, 2, 3, 4, 5, 6, 7,
88 -1, -1, -1, -1, -1, -1, 14, -1,
89 -1, -1, -1, -1, -1, -1, -1, -1,
90 8, 9, 10, 11, 12, 13, -1, 15,
92 32, 33, 34, 35, 36, 37, 38, 39,
93 40, 41, 42, 43, 44, 45, 46, 47,
94 48, 49, 50, 51, 52, 53, 54, 55,
95 56, 57, 58, 59, 60, 61, 62, 63,
96 64, 65, 66, 67, 68, 69, 70, 71,
97 72, 73, 74, 75, 76, 77, 78, 79,
98 80, 81, 82, 83, 84, 85, 86, 87,
99 88, 89, 90, 91, 92, 93, 94, 95,
100 96, 97, 98, 99, 100};
102 /* Vector, indexed by hard register number, which contains 1
103 for a register that is allowable in a candidate for leaf
104 function treatment. */
105 char sparc_leaf_regs
[] =
106 { 1, 1, 1, 1, 1, 1, 1, 1,
107 0, 0, 0, 0, 0, 0, 1, 0,
108 0, 0, 0, 0, 0, 0, 0, 0,
109 1, 1, 1, 1, 1, 1, 0, 1,
110 1, 1, 1, 1, 1, 1, 1, 1,
111 1, 1, 1, 1, 1, 1, 1, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
120 /* Name of where we pretend to think the frame pointer points.
121 Normally, this is "%fp", but if we are in a leaf procedure,
122 this is "%sp+something". We record "something" separately as it may be
123 too big for reg+constant addressing. */
125 static const char *frame_base_name
;
126 static int frame_base_offset
;
128 static void sparc_init_modes
PARAMS ((void));
129 static int save_regs
PARAMS ((FILE *, int, int, const char *,
131 static int restore_regs
PARAMS ((FILE *, int, int, const char *, int, int));
132 static void build_big_number
PARAMS ((FILE *, int, const char *));
133 static int function_arg_slotno
PARAMS ((const CUMULATIVE_ARGS
*,
134 enum machine_mode
, tree
, int, int,
137 static int supersparc_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
138 static int hypersparc_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
140 static void sparc_output_addr_vec
PARAMS ((rtx
));
141 static void sparc_output_addr_diff_vec
PARAMS ((rtx
));
142 static void sparc_output_deferred_case_vectors
PARAMS ((void));
143 static void sparc_add_gc_roots
PARAMS ((void));
144 static int check_return_regs
PARAMS ((rtx
));
145 static int epilogue_renumber
PARAMS ((rtx
*, int));
146 static bool sparc_assemble_integer
PARAMS ((rtx
, unsigned int, int));
147 static int set_extends
PARAMS ((rtx
));
148 static void output_restore_regs
PARAMS ((FILE *, int));
149 static void sparc_output_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
150 static void sparc_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
151 static void sparc_flat_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
152 static void sparc_flat_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
153 static void sparc_nonflat_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
,
155 static void sparc_nonflat_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
,
157 #ifdef OBJECT_FORMAT_ELF
158 static void sparc_elf_asm_named_section
PARAMS ((const char *, unsigned int));
161 static int sparc_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
162 static int sparc_issue_rate
PARAMS ((void));
163 static void sparc_sched_init
PARAMS ((FILE *, int, int));
164 static int sparc_use_dfa_pipeline_interface
PARAMS ((void));
165 static int sparc_use_sched_lookahead
PARAMS ((void));
167 static void emit_soft_tfmode_libcall
PARAMS ((const char *, int, rtx
*));
168 static void emit_soft_tfmode_binop
PARAMS ((enum rtx_code
, rtx
*));
169 static void emit_soft_tfmode_unop
PARAMS ((enum rtx_code
, rtx
*));
170 static void emit_soft_tfmode_cvt
PARAMS ((enum rtx_code
, rtx
*));
171 static void emit_hard_tfmode_operation
PARAMS ((enum rtx_code
, rtx
*));
173 /* Option handling. */
175 /* Code model option as passed by user. */
176 const char *sparc_cmodel_string
;
178 enum cmodel sparc_cmodel
;
180 char sparc_hard_reg_printed
[8];
182 struct sparc_cpu_select sparc_select
[] =
184 /* switch name, tune arch */
185 { (char *)0, "default", 1, 1 },
186 { (char *)0, "-mcpu=", 1, 1 },
187 { (char *)0, "-mtune=", 1, 0 },
191 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
192 enum processor_type sparc_cpu
;
194 /* Initialize the GCC target structure. */
196 /* The sparc default is to use .half rather than .short for aligned
197 HI objects. Use .word instead of .long on non-ELF systems. */
198 #undef TARGET_ASM_ALIGNED_HI_OP
199 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
200 #ifndef OBJECT_FORMAT_ELF
201 #undef TARGET_ASM_ALIGNED_SI_OP
202 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
205 #undef TARGET_ASM_UNALIGNED_HI_OP
206 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
207 #undef TARGET_ASM_UNALIGNED_SI_OP
208 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
209 #undef TARGET_ASM_UNALIGNED_DI_OP
210 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
212 /* The target hook has to handle DI-mode values. */
213 #undef TARGET_ASM_INTEGER
214 #define TARGET_ASM_INTEGER sparc_assemble_integer
216 #undef TARGET_ASM_FUNCTION_PROLOGUE
217 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
218 #undef TARGET_ASM_FUNCTION_EPILOGUE
219 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
221 #undef TARGET_SCHED_ADJUST_COST
222 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
223 #undef TARGET_SCHED_ISSUE_RATE
224 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
225 #undef TARGET_SCHED_INIT
226 #define TARGET_SCHED_INIT sparc_sched_init
227 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
228 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
229 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
230 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
232 struct gcc_target targetm
= TARGET_INITIALIZER
;
234 /* Validate and override various options, and do some machine dependent
238 sparc_override_options ()
240 static struct code_model
{
241 const char *const name
;
243 } const cmodels
[] = {
245 { "medlow", CM_MEDLOW
},
246 { "medmid", CM_MEDMID
},
247 { "medany", CM_MEDANY
},
248 { "embmedany", CM_EMBMEDANY
},
251 const struct code_model
*cmodel
;
252 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
253 static struct cpu_default
{
255 const char *const name
;
256 } const cpu_default
[] = {
257 /* There must be one entry here for each TARGET_CPU value. */
258 { TARGET_CPU_sparc
, "cypress" },
259 { TARGET_CPU_sparclet
, "tsc701" },
260 { TARGET_CPU_sparclite
, "f930" },
261 { TARGET_CPU_v8
, "v8" },
262 { TARGET_CPU_hypersparc
, "hypersparc" },
263 { TARGET_CPU_sparclite86x
, "sparclite86x" },
264 { TARGET_CPU_supersparc
, "supersparc" },
265 { TARGET_CPU_v9
, "v9" },
266 { TARGET_CPU_ultrasparc
, "ultrasparc" },
267 { TARGET_CPU_ultrasparc3
, "ultrasparc3" },
270 const struct cpu_default
*def
;
271 /* Table of values for -m{cpu,tune}=. */
272 static struct cpu_table
{
273 const char *const name
;
274 const enum processor_type processor
;
277 } const cpu_table
[] = {
278 { "v7", PROCESSOR_V7
, MASK_ISA
, 0 },
279 { "cypress", PROCESSOR_CYPRESS
, MASK_ISA
, 0 },
280 { "v8", PROCESSOR_V8
, MASK_ISA
, MASK_V8
},
281 /* TI TMS390Z55 supersparc */
282 { "supersparc", PROCESSOR_SUPERSPARC
, MASK_ISA
, MASK_V8
},
283 { "sparclite", PROCESSOR_SPARCLITE
, MASK_ISA
, MASK_SPARCLITE
},
284 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
285 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
286 { "f930", PROCESSOR_F930
, MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
287 { "f934", PROCESSOR_F934
, MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
288 { "hypersparc", PROCESSOR_HYPERSPARC
, MASK_ISA
, MASK_V8
|MASK_FPU
},
289 { "sparclite86x", PROCESSOR_SPARCLITE86X
, MASK_ISA
|MASK_FPU
,
291 { "sparclet", PROCESSOR_SPARCLET
, MASK_ISA
, MASK_SPARCLET
},
293 { "tsc701", PROCESSOR_TSC701
, MASK_ISA
, MASK_SPARCLET
},
294 { "v9", PROCESSOR_V9
, MASK_ISA
, MASK_V9
},
295 /* TI ultrasparc I, II, IIi */
296 { "ultrasparc", PROCESSOR_ULTRASPARC
, MASK_ISA
, MASK_V9
297 /* Although insns using %y are deprecated, it is a clear win on current
299 |MASK_DEPRECATED_V8_INSNS
},
300 /* TI ultrasparc III */
301 /* ??? Check if %y issue still holds true in ultra3. */
302 { "ultrasparc3", PROCESSOR_ULTRASPARC3
, MASK_ISA
, MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
305 const struct cpu_table
*cpu
;
306 const struct sparc_cpu_select
*sel
;
309 #ifndef SPARC_BI_ARCH
310 /* Check for unsupported architecture size. */
311 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
312 error ("%s is not supported by this configuration",
313 DEFAULT_ARCH32_P
? "-m64" : "-m32");
316 /* We force all 64bit archs to use 128 bit long double */
317 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
319 error ("-mlong-double-64 not allowed with -m64");
320 target_flags
|= MASK_LONG_DOUBLE_128
;
323 /* Code model selection. */
324 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
328 sparc_cmodel
= CM_32
;
331 if (sparc_cmodel_string
!= NULL
)
335 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
336 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
338 if (cmodel
->name
== NULL
)
339 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
341 sparc_cmodel
= cmodel
->value
;
344 error ("-mcmodel= is not supported on 32 bit systems");
347 fpu
= TARGET_FPU
; /* save current -mfpu status */
349 /* Set the default CPU. */
350 for (def
= &cpu_default
[0]; def
->name
; ++def
)
351 if (def
->cpu
== TARGET_CPU_DEFAULT
)
355 sparc_select
[0].string
= def
->name
;
357 for (sel
= &sparc_select
[0]; sel
->name
; ++sel
)
361 for (cpu
= &cpu_table
[0]; cpu
->name
; ++cpu
)
362 if (! strcmp (sel
->string
, cpu
->name
))
365 sparc_cpu
= cpu
->processor
;
369 target_flags
&= ~cpu
->disable
;
370 target_flags
|= cpu
->enable
;
376 error ("bad value (%s) for %s switch", sel
->string
, sel
->name
);
380 /* If -mfpu or -mno-fpu was explicitly used, don't override with
381 the processor default. Clear MASK_FPU_SET to avoid confusing
382 the reverse mapping from switch values to names. */
385 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
386 target_flags
&= ~MASK_FPU_SET
;
389 /* Don't allow -mvis if FPU is disabled. */
391 target_flags
&= ~MASK_VIS
;
393 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
395 -m64 also implies v9. */
396 if (TARGET_VIS
|| TARGET_ARCH64
)
398 target_flags
|= MASK_V9
;
399 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
402 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
403 if (TARGET_V9
&& TARGET_ARCH32
)
404 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
406 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
407 if (! TARGET_V9
|| TARGET_ARCH64
)
408 target_flags
&= ~MASK_V8PLUS
;
410 /* Don't use stack biasing in 32 bit mode. */
412 target_flags
&= ~MASK_STACK_BIAS
;
414 /* Supply a default value for align_functions. */
415 if (align_functions
== 0
416 && (sparc_cpu
== PROCESSOR_ULTRASPARC
417 || sparc_cpu
== PROCESSOR_ULTRASPARC3
))
418 align_functions
= 32;
420 /* Validate PCC_STRUCT_RETURN. */
421 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
422 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
424 /* Only use .uaxword when compiling for a 64-bit target. */
426 targetm
.asm_out
.unaligned_op
.di
= NULL
;
428 /* Do various machine dependent initializations. */
431 /* Register global variables with the garbage collector. */
432 sparc_add_gc_roots ();
435 /* Miscellaneous utilities. */
437 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
438 or branch on register contents instructions. */
444 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
445 || code
== LE
|| code
== GT
);
449 /* Operand constraints. */
451 /* Return non-zero only if OP is a register of mode MODE,
455 reg_or_0_operand (op
, mode
)
457 enum machine_mode mode
;
459 if (register_operand (op
, mode
))
461 if (op
== const0_rtx
)
463 if (GET_MODE (op
) == VOIDmode
&& GET_CODE (op
) == CONST_DOUBLE
464 && CONST_DOUBLE_HIGH (op
) == 0
465 && CONST_DOUBLE_LOW (op
) == 0)
467 if (fp_zero_operand (op
, mode
))
472 /* Nonzero if OP is a floating point value with value 0.0. */
475 fp_zero_operand (op
, mode
)
477 enum machine_mode mode
;
479 if (GET_MODE_CLASS (GET_MODE (op
)) != MODE_FLOAT
)
481 return op
== CONST0_RTX (mode
);
484 /* Nonzero if OP is a register operand in floating point register. */
487 fp_register_operand (op
, mode
)
489 enum machine_mode mode
;
491 if (! register_operand (op
, mode
))
493 if (GET_CODE (op
) == SUBREG
)
494 op
= SUBREG_REG (op
);
495 return GET_CODE (op
) == REG
&& SPARC_FP_REG_P (REGNO (op
));
498 /* Nonzero if OP is a floating point constant which can
499 be loaded into an integer register using a single
500 sethi instruction. */
506 if (GET_CODE (op
) == CONST_DOUBLE
)
511 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
512 if (REAL_VALUES_EQUAL (r
, dconst0
) &&
513 ! REAL_VALUE_MINUS_ZERO (r
))
515 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
516 if (SPARC_SETHI_P (i
))
523 /* Nonzero if OP is a floating point constant which can
524 be loaded into an integer register using a single
531 if (GET_CODE (op
) == CONST_DOUBLE
)
536 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
537 if (REAL_VALUES_EQUAL (r
, dconst0
) &&
538 ! REAL_VALUE_MINUS_ZERO (r
))
540 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
541 if (SPARC_SIMM13_P (i
))
548 /* Nonzero if OP is a floating point constant which can
549 be loaded into an integer register using a high/losum
550 instruction sequence. */
556 /* The constraints calling this should only be in
557 SFmode move insns, so any constant which cannot
558 be moved using a single insn will do. */
559 if (GET_CODE (op
) == CONST_DOUBLE
)
564 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
565 if (REAL_VALUES_EQUAL (r
, dconst0
) &&
566 ! REAL_VALUE_MINUS_ZERO (r
))
568 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
569 if (! SPARC_SETHI_P (i
)
570 && ! SPARC_SIMM13_P (i
))
577 /* Nonzero if OP is an integer register. */
580 intreg_operand (op
, mode
)
582 enum machine_mode mode ATTRIBUTE_UNUSED
;
584 return (register_operand (op
, SImode
)
585 || (TARGET_ARCH64
&& register_operand (op
, DImode
)));
588 /* Nonzero if OP is a floating point condition code register. */
591 fcc_reg_operand (op
, mode
)
593 enum machine_mode mode
;
595 /* This can happen when recog is called from combine. Op may be a MEM.
596 Fail instead of calling abort in this case. */
597 if (GET_CODE (op
) != REG
)
600 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
603 && (GET_MODE (op
) != CCFPmode
&& GET_MODE (op
) != CCFPEmode
))
606 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
607 if (reg_renumber
== 0)
608 return REGNO (op
) >= FIRST_PSEUDO_REGISTER
;
609 return REGNO_OK_FOR_CCFP_P (REGNO (op
));
611 return (unsigned) REGNO (op
) - SPARC_FIRST_V9_FCC_REG
< 4;
615 /* Nonzero if OP is a floating point condition code fcc0 register. */
618 fcc0_reg_operand (op
, mode
)
620 enum machine_mode mode
;
622 /* This can happen when recog is called from combine. Op may be a MEM.
623 Fail instead of calling abort in this case. */
624 if (GET_CODE (op
) != REG
)
627 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
630 && (GET_MODE (op
) != CCFPmode
&& GET_MODE (op
) != CCFPEmode
))
633 return REGNO (op
) == SPARC_FCC_REG
;
636 /* Nonzero if OP is an integer or floating point condition code register. */
639 icc_or_fcc_reg_operand (op
, mode
)
641 enum machine_mode mode
;
643 if (GET_CODE (op
) == REG
&& REGNO (op
) == SPARC_ICC_REG
)
645 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
648 && GET_MODE (op
) != CCmode
&& GET_MODE (op
) != CCXmode
)
653 return fcc_reg_operand (op
, mode
);
656 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
658 restore_operand (op
, mode
)
660 enum machine_mode mode
;
662 return (GET_CODE (op
) == REG
&& GET_MODE (op
) == mode
663 && (REGNO (op
) < 8 || (REGNO (op
) >= 24 && REGNO (op
) < 32)));
666 /* Call insn on SPARC can take a PC-relative constant address, or any regular
670 call_operand (op
, mode
)
672 enum machine_mode mode
;
674 if (GET_CODE (op
) != MEM
)
677 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
681 call_operand_address (op
, mode
)
683 enum machine_mode mode
;
685 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
688 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
689 reference and a constant. */
692 symbolic_operand (op
, mode
)
694 enum machine_mode mode
;
696 enum machine_mode omode
= GET_MODE (op
);
698 if (omode
!= mode
&& omode
!= VOIDmode
&& mode
!= VOIDmode
)
701 switch (GET_CODE (op
))
709 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
710 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
711 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
718 /* Return truth value of statement that OP is a symbolic memory
719 operand of mode MODE. */
722 symbolic_memory_operand (op
, mode
)
724 enum machine_mode mode ATTRIBUTE_UNUSED
;
726 if (GET_CODE (op
) == SUBREG
)
727 op
= SUBREG_REG (op
);
728 if (GET_CODE (op
) != MEM
)
731 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
732 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
735 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
738 label_ref_operand (op
, mode
)
740 enum machine_mode mode
;
742 if (GET_CODE (op
) != LABEL_REF
)
744 if (GET_MODE (op
) != mode
)
749 /* Return 1 if the operand is an argument used in generating pic references
750 in either the medium/low or medium/anywhere code models of sparc64. */
753 sp64_medium_pic_operand (op
, mode
)
755 enum machine_mode mode ATTRIBUTE_UNUSED
;
757 /* Check for (const (minus (symbol_ref:GOT)
758 (const (minus (label) (pc))))). */
759 if (GET_CODE (op
) != CONST
)
762 if (GET_CODE (op
) != MINUS
)
764 if (GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
)
766 /* ??? Ensure symbol is GOT. */
767 if (GET_CODE (XEXP (op
, 1)) != CONST
)
769 if (GET_CODE (XEXP (XEXP (op
, 1), 0)) != MINUS
)
774 /* Return 1 if the operand is a data segment reference. This includes
775 the readonly data segment, or in other words anything but the text segment.
776 This is needed in the medium/anywhere code model on v9. These values
777 are accessed with EMBMEDANY_BASE_REG. */
780 data_segment_operand (op
, mode
)
782 enum machine_mode mode ATTRIBUTE_UNUSED
;
784 switch (GET_CODE (op
))
787 return ! SYMBOL_REF_FLAG (op
);
789 /* Assume canonical format of symbol + constant.
792 return data_segment_operand (XEXP (op
, 0), VOIDmode
);
798 /* Return 1 if the operand is a text segment reference.
799 This is needed in the medium/anywhere code model on v9. */
802 text_segment_operand (op
, mode
)
804 enum machine_mode mode ATTRIBUTE_UNUSED
;
806 switch (GET_CODE (op
))
811 return SYMBOL_REF_FLAG (op
);
813 /* Assume canonical format of symbol + constant.
816 return text_segment_operand (XEXP (op
, 0), VOIDmode
);
822 /* Return 1 if the operand is either a register or a memory operand that is
826 reg_or_nonsymb_mem_operand (op
, mode
)
828 enum machine_mode mode
;
830 if (register_operand (op
, mode
))
833 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
840 splittable_symbolic_memory_operand (op
, mode
)
842 enum machine_mode mode ATTRIBUTE_UNUSED
;
844 if (GET_CODE (op
) != MEM
)
846 if (! symbolic_operand (XEXP (op
, 0), Pmode
))
852 splittable_immediate_memory_operand (op
, mode
)
854 enum machine_mode mode ATTRIBUTE_UNUSED
;
856 if (GET_CODE (op
) != MEM
)
858 if (! immediate_operand (XEXP (op
, 0), Pmode
))
863 /* Return truth value of whether OP is EQ or NE. */
868 enum machine_mode mode ATTRIBUTE_UNUSED
;
870 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
873 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
874 or LTU for non-floating-point. We handle those specially. */
877 normal_comp_operator (op
, mode
)
879 enum machine_mode mode ATTRIBUTE_UNUSED
;
881 enum rtx_code code
= GET_CODE (op
);
883 if (GET_RTX_CLASS (code
) != '<')
886 if (GET_MODE (XEXP (op
, 0)) == CCFPmode
887 || GET_MODE (XEXP (op
, 0)) == CCFPEmode
)
890 return (code
!= NE
&& code
!= EQ
&& code
!= GEU
&& code
!= LTU
);
893 /* Return 1 if this is a comparison operator. This allows the use of
894 MATCH_OPERATOR to recognize all the branch insns. */
897 noov_compare_op (op
, mode
)
899 enum machine_mode mode ATTRIBUTE_UNUSED
;
901 enum rtx_code code
= GET_CODE (op
);
903 if (GET_RTX_CLASS (code
) != '<')
906 if (GET_MODE (XEXP (op
, 0)) == CC_NOOVmode
907 || GET_MODE (XEXP (op
, 0)) == CCX_NOOVmode
)
908 /* These are the only branches which work with CC_NOOVmode. */
909 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
);
913 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
914 MATCH_OPERATOR to recognize all the branch insns. */
917 noov_compare64_op (op
, mode
)
919 enum machine_mode mode ATTRIBUTE_UNUSED
;
921 enum rtx_code code
= GET_CODE (op
);
926 if (GET_RTX_CLASS (code
) != '<')
929 if (GET_MODE (XEXP (op
, 0)) == CCX_NOOVmode
)
930 /* These are the only branches which work with CCX_NOOVmode. */
931 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
);
932 return (GET_MODE (XEXP (op
, 0)) == CCXmode
);
935 /* Nonzero if OP is a comparison operator suitable for use in v9
936 conditional move or branch on register contents instructions. */
939 v9_regcmp_op (op
, mode
)
941 enum machine_mode mode ATTRIBUTE_UNUSED
;
943 enum rtx_code code
= GET_CODE (op
);
945 if (GET_RTX_CLASS (code
) != '<')
948 return v9_regcmp_p (code
);
951 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
956 enum machine_mode mode ATTRIBUTE_UNUSED
;
958 return GET_CODE (op
) == SIGN_EXTEND
|| GET_CODE (op
) == ZERO_EXTEND
;
961 /* Return nonzero if OP is an operator of mode MODE which can set
962 the condition codes explicitly. We do not include PLUS and MINUS
963 because these require CC_NOOVmode, which we handle explicitly. */
966 cc_arithop (op
, mode
)
968 enum machine_mode mode ATTRIBUTE_UNUSED
;
970 if (GET_CODE (op
) == AND
971 || GET_CODE (op
) == IOR
972 || GET_CODE (op
) == XOR
)
978 /* Return nonzero if OP is an operator of mode MODE which can bitwise
979 complement its second operand and set the condition codes explicitly. */
982 cc_arithopn (op
, mode
)
984 enum machine_mode mode ATTRIBUTE_UNUSED
;
986 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
987 and (xor ... (not ...)) to (not (xor ...)). */
988 return (GET_CODE (op
) == AND
989 || GET_CODE (op
) == IOR
);
992 /* Return true if OP is a register, or is a CONST_INT that can fit in a
993 signed 13 bit immediate field. This is an acceptable SImode operand for
994 most 3 address instructions. */
997 arith_operand (op
, mode
)
999 enum machine_mode mode
;
1001 if (register_operand (op
, mode
))
1003 if (GET_CODE (op
) != CONST_INT
)
1005 return SMALL_INT32 (op
);
1008 /* Return true if OP is a constant 4096 */
1011 arith_4096_operand (op
, mode
)
1013 enum machine_mode mode ATTRIBUTE_UNUSED
;
1015 if (GET_CODE (op
) != CONST_INT
)
1018 return INTVAL (op
) == 4096;
1021 /* Return true if OP is suitable as second operand for add/sub */
1024 arith_add_operand (op
, mode
)
1026 enum machine_mode mode
;
1028 return arith_operand (op
, mode
) || arith_4096_operand (op
, mode
);
1031 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1032 immediate field of OR and XOR instructions. Used for 64-bit
1033 constant formation patterns. */
1035 const64_operand (op
, mode
)
1037 enum machine_mode mode ATTRIBUTE_UNUSED
;
1039 return ((GET_CODE (op
) == CONST_INT
1040 && SPARC_SIMM13_P (INTVAL (op
)))
1041 #if HOST_BITS_PER_WIDE_INT != 64
1042 || (GET_CODE (op
) == CONST_DOUBLE
1043 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))
1044 && (CONST_DOUBLE_HIGH (op
) ==
1045 ((CONST_DOUBLE_LOW (op
) & 0x80000000) != 0 ?
1046 (HOST_WIDE_INT
)-1 : 0)))
1051 /* The same, but only for sethi instructions. */
1053 const64_high_operand (op
, mode
)
1055 enum machine_mode mode
;
1057 return ((GET_CODE (op
) == CONST_INT
1058 && (INTVAL (op
) & ~(HOST_WIDE_INT
)0x3ff) != 0
1059 && SPARC_SETHI_P (INTVAL (op
) & GET_MODE_MASK (mode
))
1061 || (GET_CODE (op
) == CONST_DOUBLE
1062 && CONST_DOUBLE_HIGH (op
) == 0
1063 && (CONST_DOUBLE_LOW (op
) & ~(HOST_WIDE_INT
)0x3ff) != 0
1064 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op
))));
1067 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1068 signed 11 bit immediate field. This is an acceptable SImode operand for
1069 the movcc instructions. */
1072 arith11_operand (op
, mode
)
1074 enum machine_mode mode
;
1076 return (register_operand (op
, mode
)
1077 || (GET_CODE (op
) == CONST_INT
&& SPARC_SIMM11_P (INTVAL (op
))));
1080 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1081 signed 10 bit immediate field. This is an acceptable SImode operand for
1082 the movrcc instructions. */
1085 arith10_operand (op
, mode
)
1087 enum machine_mode mode
;
1089 return (register_operand (op
, mode
)
1090 || (GET_CODE (op
) == CONST_INT
&& SPARC_SIMM10_P (INTVAL (op
))));
1093 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1094 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1096 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1097 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1098 for most 3 address instructions. */
1101 arith_double_operand (op
, mode
)
1103 enum machine_mode mode
;
1105 return (register_operand (op
, mode
)
1106 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
1108 && GET_CODE (op
) == CONST_DOUBLE
1109 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
1110 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_HIGH (op
) + 0x1000) < 0x2000)
1112 && GET_CODE (op
) == CONST_DOUBLE
1113 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
1114 && ((CONST_DOUBLE_HIGH (op
) == -1
1115 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0x1000)
1116 || (CONST_DOUBLE_HIGH (op
) == 0
1117 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0))));
1120 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1123 arith_double_4096_operand (op
, mode
)
1125 enum machine_mode mode ATTRIBUTE_UNUSED
;
1127 return (TARGET_ARCH64
&&
1128 ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 4096) ||
1129 (GET_CODE (op
) == CONST_DOUBLE
&&
1130 CONST_DOUBLE_LOW (op
) == 4096 &&
1131 CONST_DOUBLE_HIGH (op
) == 0)));
1134 /* Return true if OP is suitable as second operand for add/sub in DImode */
1137 arith_double_add_operand (op
, mode
)
1139 enum machine_mode mode
;
1141 return arith_double_operand (op
, mode
) || arith_double_4096_operand (op
, mode
);
1144 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1145 can fit in an 11 bit immediate field. This is an acceptable DImode
1146 operand for the movcc instructions. */
1147 /* ??? Replace with arith11_operand? */
1150 arith11_double_operand (op
, mode
)
1152 enum machine_mode mode
;
1154 return (register_operand (op
, mode
)
1155 || (GET_CODE (op
) == CONST_DOUBLE
1156 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1157 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x400) < 0x800
1158 && ((CONST_DOUBLE_HIGH (op
) == -1
1159 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0x400)
1160 || (CONST_DOUBLE_HIGH (op
) == 0
1161 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0)))
1162 || (GET_CODE (op
) == CONST_INT
1163 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1164 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x400) < 0x800));
1167 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1168 can fit in an 10 bit immediate field. This is an acceptable DImode
1169 operand for the movrcc instructions. */
1170 /* ??? Replace with arith10_operand? */
1173 arith10_double_operand (op
, mode
)
1175 enum machine_mode mode
;
1177 return (register_operand (op
, mode
)
1178 || (GET_CODE (op
) == CONST_DOUBLE
1179 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1180 && (unsigned) (CONST_DOUBLE_LOW (op
) + 0x200) < 0x400
1181 && ((CONST_DOUBLE_HIGH (op
) == -1
1182 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0x200)
1183 || (CONST_DOUBLE_HIGH (op
) == 0
1184 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0)))
1185 || (GET_CODE (op
) == CONST_INT
1186 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1187 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x200) < 0x400));
1190 /* Return truth value of whether OP is an integer which fits the
1191 range constraining immediate operands in most three-address insns,
1192 which have a 13 bit immediate field. */
1195 small_int (op
, mode
)
1197 enum machine_mode mode ATTRIBUTE_UNUSED
;
1199 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
1203 small_int_or_double (op
, mode
)
1205 enum machine_mode mode ATTRIBUTE_UNUSED
;
1207 return ((GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
1208 || (GET_CODE (op
) == CONST_DOUBLE
1209 && CONST_DOUBLE_HIGH (op
) == 0
1210 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))));
1213 /* Recognize operand values for the umul instruction. That instruction sign
1214 extends immediate values just like all other sparc instructions, but
1215 interprets the extended result as an unsigned number. */
1218 uns_small_int (op
, mode
)
1220 enum machine_mode mode ATTRIBUTE_UNUSED
;
1222 #if HOST_BITS_PER_WIDE_INT > 32
1223 /* All allowed constants will fit a CONST_INT. */
1224 return (GET_CODE (op
) == CONST_INT
1225 && ((INTVAL (op
) >= 0 && INTVAL (op
) < 0x1000)
1226 || (INTVAL (op
) >= 0xFFFFF000
1227 && INTVAL (op
) <= 0xFFFFFFFF)));
1229 return ((GET_CODE (op
) == CONST_INT
&& (unsigned) INTVAL (op
) < 0x1000)
1230 || (GET_CODE (op
) == CONST_DOUBLE
1231 && CONST_DOUBLE_HIGH (op
) == 0
1232 && (unsigned) CONST_DOUBLE_LOW (op
) - 0xFFFFF000 < 0x1000));
1237 uns_arith_operand (op
, mode
)
1239 enum machine_mode mode
;
1241 return register_operand (op
, mode
) || uns_small_int (op
, mode
);
1244 /* Return truth value of statement that OP is a call-clobbered register. */
1246 clobbered_register (op
, mode
)
1248 enum machine_mode mode ATTRIBUTE_UNUSED
;
1250 return (GET_CODE (op
) == REG
&& call_used_regs
[REGNO (op
)]);
1253 /* Return 1 if OP is a valid operand for the source of a move insn. */
1256 input_operand (op
, mode
)
1258 enum machine_mode mode
;
1260 /* If both modes are non-void they must be the same. */
1261 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1264 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
1265 if (GET_CODE (op
) == CONST
&& GET_CODE (XEXP (op
, 0)) == CONSTANT_P_RTX
)
1268 /* Allow any one instruction integer constant, and all CONST_INT
1269 variants when we are working in DImode and !arch64. */
1270 if (GET_MODE_CLASS (mode
) == MODE_INT
1271 && ((GET_CODE (op
) == CONST_INT
1272 && (SPARC_SETHI_P (INTVAL (op
) & GET_MODE_MASK (mode
))
1273 || SPARC_SIMM13_P (INTVAL (op
))
1275 && ! TARGET_ARCH64
)))
1277 && GET_CODE (op
) == CONST_DOUBLE
1278 && ((CONST_DOUBLE_HIGH (op
) == 0
1279 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op
)))
1281 #if HOST_BITS_PER_WIDE_INT == 64
1282 (CONST_DOUBLE_HIGH (op
) == 0
1283 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
)))
1285 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))
1286 && (((CONST_DOUBLE_LOW (op
) & 0x80000000) == 0
1287 && CONST_DOUBLE_HIGH (op
) == 0)
1288 || (CONST_DOUBLE_HIGH (op
) == -1
1289 && CONST_DOUBLE_LOW (op
) & 0x80000000) != 0))
1294 /* If !arch64 and this is a DImode const, allow it so that
1295 the splits can be generated. */
1298 && GET_CODE (op
) == CONST_DOUBLE
)
1301 if (register_operand (op
, mode
))
1304 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
1305 && GET_CODE (op
) == CONST_DOUBLE
)
1308 /* If this is a SUBREG, look inside so that we handle
1309 paradoxical ones. */
1310 if (GET_CODE (op
) == SUBREG
)
1311 op
= SUBREG_REG (op
);
1313 /* Check for valid MEM forms. */
1314 if (GET_CODE (op
) == MEM
)
1316 rtx inside
= XEXP (op
, 0);
1318 if (GET_CODE (inside
) == LO_SUM
)
1320 /* We can't allow these because all of the splits
1321 (eventually as they trickle down into DFmode
1322 splits) require offsettable memory references. */
1324 && GET_MODE (op
) == TFmode
)
1327 return (register_operand (XEXP (inside
, 0), Pmode
)
1328 && CONSTANT_P (XEXP (inside
, 1)));
1330 return memory_address_p (mode
, inside
);
1337 /* We know it can't be done in one insn when we get here,
1338 the movsi expander guarentees this. */
1340 sparc_emit_set_const32 (op0
, op1
)
1344 enum machine_mode mode
= GET_MODE (op0
);
1347 if (GET_CODE (op1
) == CONST_INT
)
1349 HOST_WIDE_INT value
= INTVAL (op1
);
1351 if (SPARC_SETHI_P (value
& GET_MODE_MASK (mode
))
1352 || SPARC_SIMM13_P (value
))
1356 /* Full 2-insn decomposition is needed. */
1357 if (reload_in_progress
|| reload_completed
)
1360 temp
= gen_reg_rtx (mode
);
1362 if (GET_CODE (op1
) == CONST_INT
)
1364 /* Emit them as real moves instead of a HIGH/LO_SUM,
1365 this way CSE can see everything and reuse intermediate
1366 values if it wants. */
1368 && HOST_BITS_PER_WIDE_INT
!= 64
1369 && (INTVAL (op1
) & 0x80000000) != 0)
1370 emit_insn (gen_rtx_SET
1372 gen_rtx_CONST_DOUBLE (VOIDmode
,
1373 INTVAL (op1
) & ~(HOST_WIDE_INT
)0x3ff,
1376 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1377 GEN_INT (INTVAL (op1
)
1378 & ~(HOST_WIDE_INT
)0x3ff)));
1380 emit_insn (gen_rtx_SET (VOIDmode
,
1382 gen_rtx_IOR (mode
, temp
,
1383 GEN_INT (INTVAL (op1
) & 0x3ff))));
1387 /* A symbol, emit in the traditional way. */
1388 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1389 gen_rtx_HIGH (mode
, op1
)));
1390 emit_insn (gen_rtx_SET (VOIDmode
,
1391 op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1397 /* Sparc-v9 code-model support. */
1399 sparc_emit_set_symbolic_const64 (op0
, op1
, temp1
)
1406 if (temp1
&& GET_MODE (temp1
) == TImode
)
1409 temp1
= gen_rtx_REG (DImode
, REGNO (temp1
));
1412 switch (sparc_cmodel
)
1415 /* The range spanned by all instructions in the object is less
1416 than 2^31 bytes (2GB) and the distance from any instruction
1417 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1418 than 2^31 bytes (2GB).
1420 The executable must be in the low 4TB of the virtual address
1423 sethi %hi(symbol), %temp
1424 or %temp, %lo(symbol), %reg */
1425 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1426 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1430 /* The range spanned by all instructions in the object is less
1431 than 2^31 bytes (2GB) and the distance from any instruction
1432 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1433 than 2^31 bytes (2GB).
1435 The executable must be in the low 16TB of the virtual address
1438 sethi %h44(symbol), %temp1
1439 or %temp1, %m44(symbol), %temp2
1440 sllx %temp2, 12, %temp3
1441 or %temp3, %l44(symbol), %reg */
1442 emit_insn (gen_seth44 (op0
, op1
));
1443 emit_insn (gen_setm44 (op0
, op0
, op1
));
1444 emit_insn (gen_rtx_SET (VOIDmode
, temp1
,
1445 gen_rtx_ASHIFT (DImode
, op0
, GEN_INT (12))));
1446 emit_insn (gen_setl44 (op0
, temp1
, op1
));
1450 /* The range spanned by all instructions in the object is less
1451 than 2^31 bytes (2GB) and the distance from any instruction
1452 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1453 than 2^31 bytes (2GB).
1455 The executable can be placed anywhere in the virtual address
1458 sethi %hh(symbol), %temp1
1459 sethi %lm(symbol), %temp2
1460 or %temp1, %hm(symbol), %temp3
1461 or %temp2, %lo(symbol), %temp4
1462 sllx %temp3, 32, %temp5
1463 or %temp4, %temp5, %reg */
1465 /* It is possible that one of the registers we got for operands[2]
1466 might coincide with that of operands[0] (which is why we made
1467 it TImode). Pick the other one to use as our scratch. */
1468 if (rtx_equal_p (temp1
, op0
))
1471 temp1
= gen_rtx_REG (DImode
, REGNO (temp1
) + 1);
1476 emit_insn (gen_sethh (op0
, op1
));
1477 emit_insn (gen_setlm (temp1
, op1
));
1478 emit_insn (gen_sethm (op0
, op0
, op1
));
1479 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1480 gen_rtx_ASHIFT (DImode
, op0
, GEN_INT (32))));
1481 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1482 gen_rtx_PLUS (DImode
, op0
, temp1
)));
1483 emit_insn (gen_setlo (op0
, op0
, op1
));
1487 /* Old old old backwards compatibility kruft here.
1488 Essentially it is MEDLOW with a fixed 64-bit
1489 virtual base added to all data segment addresses.
1490 Text-segment stuff is computed like MEDANY, we can't
1491 reuse the code above because the relocation knobs
1494 Data segment: sethi %hi(symbol), %temp1
1495 or %temp1, %lo(symbol), %temp2
1496 add %temp2, EMBMEDANY_BASE_REG, %reg
1498 Text segment: sethi %uhi(symbol), %temp1
1499 sethi %hi(symbol), %temp2
1500 or %temp1, %ulo(symbol), %temp3
1501 or %temp2, %lo(symbol), %temp4
1502 sllx %temp3, 32, %temp5
1503 or %temp4, %temp5, %reg */
1504 if (data_segment_operand (op1
, GET_MODE (op1
)))
1506 emit_insn (gen_embmedany_sethi (temp1
, op1
));
1507 emit_insn (gen_embmedany_brsum (op0
, temp1
));
1508 emit_insn (gen_embmedany_losum (op0
, op0
, op1
));
1512 /* It is possible that one of the registers we got for operands[2]
1513 might coincide with that of operands[0] (which is why we made
1514 it TImode). Pick the other one to use as our scratch. */
1515 if (rtx_equal_p (temp1
, op0
))
1518 temp1
= gen_rtx_REG (DImode
, REGNO (temp1
) + 1);
1523 emit_insn (gen_embmedany_textuhi (op0
, op1
));
1524 emit_insn (gen_embmedany_texthi (temp1
, op1
));
1525 emit_insn (gen_embmedany_textulo (op0
, op0
, op1
));
1526 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1527 gen_rtx_ASHIFT (DImode
, op0
, GEN_INT (32))));
1528 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1529 gen_rtx_PLUS (DImode
, op0
, temp1
)));
1530 emit_insn (gen_embmedany_textlo (op0
, op0
, op1
));
1539 /* These avoid problems when cross compiling. If we do not
1540 go through all this hair then the optimizer will see
1541 invalid REG_EQUAL notes or in some cases none at all. */
1542 static void sparc_emit_set_safe_HIGH64
PARAMS ((rtx
, HOST_WIDE_INT
));
1543 static rtx gen_safe_SET64
PARAMS ((rtx
, HOST_WIDE_INT
));
1544 static rtx gen_safe_OR64
PARAMS ((rtx
, HOST_WIDE_INT
));
1545 static rtx gen_safe_XOR64
PARAMS ((rtx
, HOST_WIDE_INT
));
1547 #if HOST_BITS_PER_WIDE_INT == 64
1548 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1549 #define GEN_INT64(__x) GEN_INT (__x)
1551 #define GEN_HIGHINT64(__x) \
1552 gen_rtx_CONST_DOUBLE (VOIDmode, (__x) & ~(HOST_WIDE_INT)0x3ff, 0)
1553 #define GEN_INT64(__x) \
1554 gen_rtx_CONST_DOUBLE (VOIDmode, (__x) & 0xffffffff, \
1555 ((__x) & 0x80000000 \
1559 /* The optimizer is not to assume anything about exactly
1560 which bits are set for a HIGH, they are unspecified.
1561 Unfortunately this leads to many missed optimizations
1562 during CSE. We mask out the non-HIGH bits, and matches
1563 a plain movdi, to alleviate this problem. */
1565 sparc_emit_set_safe_HIGH64 (dest
, val
)
1569 emit_insn (gen_rtx_SET (VOIDmode
, dest
, GEN_HIGHINT64 (val
)));
1573 gen_safe_SET64 (dest
, val
)
1577 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT64 (val
));
1581 gen_safe_OR64 (src
, val
)
1585 return gen_rtx_IOR (DImode
, src
, GEN_INT64 (val
));
1589 gen_safe_XOR64 (src
, val
)
1593 return gen_rtx_XOR (DImode
, src
, GEN_INT64 (val
));
1596 /* Worker routines for 64-bit constant formation on arch64.
1597 One of the key things to be doing in these emissions is
1598 to create as many temp REGs as possible. This makes it
1599 possible for half-built constants to be used later when
1600 such values are similar to something required later on.
1601 Without doing this, the optimizer cannot see such
1604 static void sparc_emit_set_const64_quick1
1605 PARAMS ((rtx
, rtx
, unsigned HOST_WIDE_INT
, int));
1608 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
, is_neg
)
1611 unsigned HOST_WIDE_INT low_bits
;
1614 unsigned HOST_WIDE_INT high_bits
;
1617 high_bits
= (~low_bits
) & 0xffffffff;
1619 high_bits
= low_bits
;
1621 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1624 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1625 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1629 /* If we are XOR'ing with -1, then we should emit a one's complement
1630 instead. This way the combiner will notice logical operations
1631 such as ANDN later on and substitute. */
1632 if ((low_bits
& 0x3ff) == 0x3ff)
1634 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1635 gen_rtx_NOT (DImode
, temp
)));
1639 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1640 gen_safe_XOR64 (temp
,
1641 (-(HOST_WIDE_INT
)0x400
1642 | (low_bits
& 0x3ff)))));
1647 static void sparc_emit_set_const64_quick2
1648 PARAMS ((rtx
, rtx
, unsigned HOST_WIDE_INT
,
1649 unsigned HOST_WIDE_INT
, int));
1652 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_immediate
, shift_count
)
1655 unsigned HOST_WIDE_INT high_bits
;
1656 unsigned HOST_WIDE_INT low_immediate
;
1661 if ((high_bits
& 0xfffffc00) != 0)
1663 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1664 if ((high_bits
& ~0xfffffc00) != 0)
1665 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1666 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1672 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1676 /* Now shift it up into place. */
1677 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1678 gen_rtx_ASHIFT (DImode
, temp2
,
1679 GEN_INT (shift_count
))));
1681 /* If there is a low immediate part piece, finish up by
1682 putting that in as well. */
1683 if (low_immediate
!= 0)
1684 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1685 gen_safe_OR64 (op0
, low_immediate
)));
1688 static void sparc_emit_set_const64_longway
1689 PARAMS ((rtx
, rtx
, unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
));
1691 /* Full 64-bit constant decomposition. Even though this is the
1692 'worst' case, we still optimize a few things away. */
1694 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
)
1697 unsigned HOST_WIDE_INT high_bits
;
1698 unsigned HOST_WIDE_INT low_bits
;
1702 if (reload_in_progress
|| reload_completed
)
1705 sub_temp
= gen_reg_rtx (DImode
);
1707 if ((high_bits
& 0xfffffc00) != 0)
1709 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1710 if ((high_bits
& ~0xfffffc00) != 0)
1711 emit_insn (gen_rtx_SET (VOIDmode
,
1713 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1719 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1723 if (!reload_in_progress
&& !reload_completed
)
1725 rtx temp2
= gen_reg_rtx (DImode
);
1726 rtx temp3
= gen_reg_rtx (DImode
);
1727 rtx temp4
= gen_reg_rtx (DImode
);
1729 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1730 gen_rtx_ASHIFT (DImode
, sub_temp
,
1733 sparc_emit_set_safe_HIGH64 (temp2
, low_bits
);
1734 if ((low_bits
& ~0xfffffc00) != 0)
1736 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1737 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
1738 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1739 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
1743 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1744 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1749 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
1750 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
1751 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
1754 /* We are in the middle of reload, so this is really
1755 painful. However we do still make an attempt to
1756 avoid emitting truly stupid code. */
1757 if (low1
!= const0_rtx
)
1759 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1760 gen_rtx_ASHIFT (DImode
, sub_temp
,
1761 GEN_INT (to_shift
))));
1762 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1763 gen_rtx_IOR (DImode
, op0
, low1
)));
1771 if (low2
!= const0_rtx
)
1773 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1774 gen_rtx_ASHIFT (DImode
, sub_temp
,
1775 GEN_INT (to_shift
))));
1776 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1777 gen_rtx_IOR (DImode
, op0
, low2
)));
1785 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1786 gen_rtx_ASHIFT (DImode
, sub_temp
,
1787 GEN_INT (to_shift
))));
1788 if (low3
!= const0_rtx
)
1789 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1790 gen_rtx_IOR (DImode
, op0
, low3
)));
1795 /* Analyze a 64-bit constant for certain properties. */
1796 static void analyze_64bit_constant
1797 PARAMS ((unsigned HOST_WIDE_INT
,
1798 unsigned HOST_WIDE_INT
,
1799 int *, int *, int *));
1802 analyze_64bit_constant (high_bits
, low_bits
, hbsp
, lbsp
, abbasp
)
1803 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1804 int *hbsp
, *lbsp
, *abbasp
;
1806 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
1809 lowest_bit_set
= highest_bit_set
= -1;
1813 if ((lowest_bit_set
== -1)
1814 && ((low_bits
>> i
) & 1))
1816 if ((highest_bit_set
== -1)
1817 && ((high_bits
>> (32 - i
- 1)) & 1))
1818 highest_bit_set
= (64 - i
- 1);
1821 && ((highest_bit_set
== -1)
1822 || (lowest_bit_set
== -1)));
1828 if ((lowest_bit_set
== -1)
1829 && ((high_bits
>> i
) & 1))
1830 lowest_bit_set
= i
+ 32;
1831 if ((highest_bit_set
== -1)
1832 && ((low_bits
>> (32 - i
- 1)) & 1))
1833 highest_bit_set
= 32 - i
- 1;
1836 && ((highest_bit_set
== -1)
1837 || (lowest_bit_set
== -1)));
1839 /* If there are no bits set this should have gone out
1840 as one instruction! */
1841 if (lowest_bit_set
== -1
1842 || highest_bit_set
== -1)
1844 all_bits_between_are_set
= 1;
1845 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
1849 if ((low_bits
& (1 << i
)) != 0)
1854 if ((high_bits
& (1 << (i
- 32))) != 0)
1857 all_bits_between_are_set
= 0;
1860 *hbsp
= highest_bit_set
;
1861 *lbsp
= lowest_bit_set
;
1862 *abbasp
= all_bits_between_are_set
;
1865 static int const64_is_2insns
1866 PARAMS ((unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
));
1869 const64_is_2insns (high_bits
, low_bits
)
1870 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1872 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
1875 || high_bits
== 0xffffffff)
1878 analyze_64bit_constant (high_bits
, low_bits
,
1879 &highest_bit_set
, &lowest_bit_set
,
1880 &all_bits_between_are_set
);
1882 if ((highest_bit_set
== 63
1883 || lowest_bit_set
== 0)
1884 && all_bits_between_are_set
!= 0)
1887 if ((highest_bit_set
- lowest_bit_set
) < 21)
1893 static unsigned HOST_WIDE_INT create_simple_focus_bits
1894 PARAMS ((unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
,
1897 static unsigned HOST_WIDE_INT
1898 create_simple_focus_bits (high_bits
, low_bits
, lowest_bit_set
, shift
)
1899 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1900 int lowest_bit_set
, shift
;
1902 HOST_WIDE_INT hi
, lo
;
1904 if (lowest_bit_set
< 32)
1906 lo
= (low_bits
>> lowest_bit_set
) << shift
;
1907 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
1912 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
1919 /* Here we are sure to be arch64 and this is an integer constant
1920 being loaded into a register. Emit the most efficient
1921 insn sequence possible. Detection of all the 1-insn cases
1922 has been done already. */
1924 sparc_emit_set_const64 (op0
, op1
)
1928 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1929 int lowest_bit_set
, highest_bit_set
;
1930 int all_bits_between_are_set
;
1933 /* Sanity check that we know what we are working with. */
1934 if (! TARGET_ARCH64
)
1937 if (GET_CODE (op0
) != SUBREG
)
1939 if (GET_CODE (op0
) != REG
1940 || (REGNO (op0
) >= SPARC_FIRST_FP_REG
1941 && REGNO (op0
) <= SPARC_LAST_V9_FP_REG
))
1945 if (reload_in_progress
|| reload_completed
)
1948 temp
= gen_reg_rtx (DImode
);
1950 if (GET_CODE (op1
) != CONST_DOUBLE
1951 && GET_CODE (op1
) != CONST_INT
)
1953 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
1957 if (GET_CODE (op1
) == CONST_DOUBLE
)
1959 #if HOST_BITS_PER_WIDE_INT == 64
1960 high_bits
= (CONST_DOUBLE_LOW (op1
) >> 32) & 0xffffffff;
1961 low_bits
= CONST_DOUBLE_LOW (op1
) & 0xffffffff;
1963 high_bits
= CONST_DOUBLE_HIGH (op1
);
1964 low_bits
= CONST_DOUBLE_LOW (op1
);
1969 #if HOST_BITS_PER_WIDE_INT == 64
1970 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
1971 low_bits
= (INTVAL (op1
) & 0xffffffff);
1973 high_bits
= ((INTVAL (op1
) < 0) ?
1976 low_bits
= INTVAL (op1
);
1980 /* low_bits bits 0 --> 31
1981 high_bits bits 32 --> 63 */
1983 analyze_64bit_constant (high_bits
, low_bits
,
1984 &highest_bit_set
, &lowest_bit_set
,
1985 &all_bits_between_are_set
);
1987 /* First try for a 2-insn sequence. */
1989 /* These situations are preferred because the optimizer can
1990 * do more things with them:
1992 * sllx %reg, shift, %reg
1994 * srlx %reg, shift, %reg
1995 * 3) mov some_small_const, %reg
1996 * sllx %reg, shift, %reg
1998 if (((highest_bit_set
== 63
1999 || lowest_bit_set
== 0)
2000 && all_bits_between_are_set
!= 0)
2001 || ((highest_bit_set
- lowest_bit_set
) < 12))
2003 HOST_WIDE_INT the_const
= -1;
2004 int shift
= lowest_bit_set
;
2006 if ((highest_bit_set
!= 63
2007 && lowest_bit_set
!= 0)
2008 || all_bits_between_are_set
== 0)
2011 create_simple_focus_bits (high_bits
, low_bits
,
2014 else if (lowest_bit_set
== 0)
2015 shift
= -(63 - highest_bit_set
);
2017 if (! SPARC_SIMM13_P (the_const
))
2020 emit_insn (gen_safe_SET64 (temp
, the_const
));
2022 emit_insn (gen_rtx_SET (VOIDmode
,
2024 gen_rtx_ASHIFT (DImode
,
2028 emit_insn (gen_rtx_SET (VOIDmode
,
2030 gen_rtx_LSHIFTRT (DImode
,
2032 GEN_INT (-shift
))));
2038 /* Now a range of 22 or less bits set somewhere.
2039 * 1) sethi %hi(focus_bits), %reg
2040 * sllx %reg, shift, %reg
2041 * 2) sethi %hi(focus_bits), %reg
2042 * srlx %reg, shift, %reg
2044 if ((highest_bit_set
- lowest_bit_set
) < 21)
2046 unsigned HOST_WIDE_INT focus_bits
=
2047 create_simple_focus_bits (high_bits
, low_bits
,
2048 lowest_bit_set
, 10);
2050 if (! SPARC_SETHI_P (focus_bits
))
2053 sparc_emit_set_safe_HIGH64 (temp
, focus_bits
);
2055 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2056 if (lowest_bit_set
< 10)
2057 emit_insn (gen_rtx_SET (VOIDmode
,
2059 gen_rtx_LSHIFTRT (DImode
, temp
,
2060 GEN_INT (10 - lowest_bit_set
))));
2061 else if (lowest_bit_set
> 10)
2062 emit_insn (gen_rtx_SET (VOIDmode
,
2064 gen_rtx_ASHIFT (DImode
, temp
,
2065 GEN_INT (lowest_bit_set
- 10))));
2071 /* 1) sethi %hi(low_bits), %reg
2072 * or %reg, %lo(low_bits), %reg
2073 * 2) sethi %hi(~low_bits), %reg
2074 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2077 || high_bits
== 0xffffffff)
2079 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
2080 (high_bits
== 0xffffffff));
2084 /* Now, try 3-insn sequences. */
2086 /* 1) sethi %hi(high_bits), %reg
2087 * or %reg, %lo(high_bits), %reg
2088 * sllx %reg, 32, %reg
2092 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
2096 /* We may be able to do something quick
2097 when the constant is negated, so try that. */
2098 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
2099 (~low_bits
) & 0xfffffc00))
2101 /* NOTE: The trailing bits get XOR'd so we need the
2102 non-negated bits, not the negated ones. */
2103 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
2105 if ((((~high_bits
) & 0xffffffff) == 0
2106 && ((~low_bits
) & 0x80000000) == 0)
2107 || (((~high_bits
) & 0xffffffff) == 0xffffffff
2108 && ((~low_bits
) & 0x80000000) != 0))
2110 int fast_int
= (~low_bits
& 0xffffffff);
2112 if ((SPARC_SETHI_P (fast_int
)
2113 && (~high_bits
& 0xffffffff) == 0)
2114 || SPARC_SIMM13_P (fast_int
))
2115 emit_insn (gen_safe_SET64 (temp
, fast_int
));
2117 sparc_emit_set_const64 (temp
, GEN_INT64 (fast_int
));
2122 #if HOST_BITS_PER_WIDE_INT == 64
2123 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
2124 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
2126 negated_const
= gen_rtx_CONST_DOUBLE (DImode
,
2127 (~low_bits
) & 0xfffffc00,
2128 (~high_bits
) & 0xffffffff);
2130 sparc_emit_set_const64 (temp
, negated_const
);
2133 /* If we are XOR'ing with -1, then we should emit a one's complement
2134 instead. This way the combiner will notice logical operations
2135 such as ANDN later on and substitute. */
2136 if (trailing_bits
== 0x3ff)
2138 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2139 gen_rtx_NOT (DImode
, temp
)));
2143 emit_insn (gen_rtx_SET (VOIDmode
,
2145 gen_safe_XOR64 (temp
,
2146 (-0x400 | trailing_bits
))));
2151 /* 1) sethi %hi(xxx), %reg
2152 * or %reg, %lo(xxx), %reg
2153 * sllx %reg, yyy, %reg
2155 * ??? This is just a generalized version of the low_bits==0
2156 * thing above, FIXME...
2158 if ((highest_bit_set
- lowest_bit_set
) < 32)
2160 unsigned HOST_WIDE_INT focus_bits
=
2161 create_simple_focus_bits (high_bits
, low_bits
,
2164 /* We can't get here in this state. */
2165 if (highest_bit_set
< 32
2166 || lowest_bit_set
>= 32)
2169 /* So what we know is that the set bits straddle the
2170 middle of the 64-bit word. */
2171 sparc_emit_set_const64_quick2 (op0
, temp
,
2177 /* 1) sethi %hi(high_bits), %reg
2178 * or %reg, %lo(high_bits), %reg
2179 * sllx %reg, 32, %reg
2180 * or %reg, low_bits, %reg
2182 if (SPARC_SIMM13_P(low_bits
)
2183 && ((int)low_bits
> 0))
2185 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2189 /* The easiest way when all else fails, is full decomposition. */
2191 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2192 high_bits
, low_bits
, ~high_bits
, ~low_bits
);
2194 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2197 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2198 return the mode to be used for the comparison. For floating-point,
2199 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2200 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2201 processing is needed. */
2204 select_cc_mode (op
, x
, y
)
2207 rtx y ATTRIBUTE_UNUSED
;
2209 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2235 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2236 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2238 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2239 return CCX_NOOVmode
;
2245 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2252 /* X and Y are two things to compare using CODE. Emit the compare insn and
2253 return the rtx for the cc reg in the proper mode. */
2256 gen_compare_reg (code
, x
, y
)
2260 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
2263 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2264 fcc regs (cse can't tell they're really call clobbered regs and will
2265 remove a duplicate comparison even if there is an intervening function
2266 call - it will then try to reload the cc reg via an int reg which is why
2267 we need the movcc patterns). It is possible to provide the movcc
2268 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2269 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2270 to tell cse that CCFPE mode registers (even pseudos) are call
2273 /* ??? This is an experiment. Rather than making changes to cse which may
2274 or may not be easy/clean, we do our own cse. This is possible because
2275 we will generate hard registers. Cse knows they're call clobbered (it
2276 doesn't know the same thing about pseudos). If we guess wrong, no big
2277 deal, but if we win, great! */
2279 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2280 #if 1 /* experiment */
2283 /* We cycle through the registers to ensure they're all exercised. */
2284 static int next_fcc_reg
= 0;
2285 /* Previous x,y for each fcc reg. */
2286 static rtx prev_args
[4][2];
2288 /* Scan prev_args for x,y. */
2289 for (reg
= 0; reg
< 4; reg
++)
2290 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2295 prev_args
[reg
][0] = x
;
2296 prev_args
[reg
][1] = y
;
2297 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2299 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2302 cc_reg
= gen_reg_rtx (mode
);
2303 #endif /* ! experiment */
2304 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2305 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2307 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2309 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
2310 gen_rtx_COMPARE (mode
, x
, y
)));
2315 /* This function is used for v9 only.
2316 CODE is the code for an Scc's comparison.
2317 OPERANDS[0] is the target of the Scc insn.
2318 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2319 been generated yet).
2321 This function is needed to turn
2324 (gt (reg:CCX 100 %icc)
2328 (gt:DI (reg:CCX 100 %icc)
2331 IE: The instruction recognizer needs to see the mode of the comparison to
2332 find the right instruction. We could use "gt:DI" right in the
2333 define_expand, but leaving it out allows us to handle DI, SI, etc.
2335 We refer to the global sparc compare operands sparc_compare_op0 and
2336 sparc_compare_op1. */
2339 gen_v9_scc (compare_code
, operands
)
2340 enum rtx_code compare_code
;
2341 register rtx
*operands
;
2346 && (GET_MODE (sparc_compare_op0
) == DImode
2347 || GET_MODE (operands
[0]) == DImode
))
2350 op0
= sparc_compare_op0
;
2351 op1
= sparc_compare_op1
;
2353 /* Try to use the movrCC insns. */
2355 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
2356 && op1
== const0_rtx
2357 && v9_regcmp_p (compare_code
))
2359 /* Special case for op0 != 0. This can be done with one instruction if
2360 operands[0] == sparc_compare_op0. */
2362 if (compare_code
== NE
2363 && GET_MODE (operands
[0]) == DImode
2364 && rtx_equal_p (op0
, operands
[0]))
2366 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2367 gen_rtx_IF_THEN_ELSE (DImode
,
2368 gen_rtx_fmt_ee (compare_code
, DImode
,
2375 if (reg_overlap_mentioned_p (operands
[0], op0
))
2377 /* Handle the case where operands[0] == sparc_compare_op0.
2378 We "early clobber" the result. */
2379 op0
= gen_reg_rtx (GET_MODE (sparc_compare_op0
));
2380 emit_move_insn (op0
, sparc_compare_op0
);
2383 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
2384 if (GET_MODE (op0
) != DImode
)
2386 temp
= gen_reg_rtx (DImode
);
2387 convert_move (temp
, op0
, 0);
2391 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2392 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
2393 gen_rtx_fmt_ee (compare_code
, DImode
,
2401 operands
[1] = gen_compare_reg (compare_code
, op0
, op1
);
2403 switch (GET_MODE (operands
[1]))
2413 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
2414 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2415 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
2416 gen_rtx_fmt_ee (compare_code
,
2417 GET_MODE (operands
[1]),
2418 operands
[1], const0_rtx
),
2419 const1_rtx
, operands
[0])));
2424 /* Emit a conditional jump insn for the v9 architecture using comparison code
2425 CODE and jump target LABEL.
2426 This function exists to take advantage of the v9 brxx insns. */
2429 emit_v9_brxx_insn (code
, op0
, label
)
2433 emit_jump_insn (gen_rtx_SET (VOIDmode
,
2435 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2436 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
2438 gen_rtx_LABEL_REF (VOIDmode
, label
),
2442 /* Generate a DFmode part of a hard TFmode register.
2443 REG is the TFmode hard register, LOW is 1 for the
2444 low 64bit of the register and 0 otherwise.
2447 gen_df_reg (reg
, low
)
2451 int regno
= REGNO (reg
);
2453 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
2454 regno
+= (TARGET_ARCH64
&& regno
< 32) ? 1 : 2;
2455 return gen_rtx_REG (DFmode
, regno
);
2458 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2459 Unlike normal calls, TFmode operands are passed by reference. It is
2460 assumed that no more than 3 operands are required. */
2463 emit_soft_tfmode_libcall (func_name
, nargs
, operands
)
2464 const char *func_name
;
2468 rtx ret_slot
= NULL
, arg
[3], func_sym
;
2471 /* We only expect to be called for conversions, unary, and binary ops. */
2472 if (nargs
< 2 || nargs
> 3)
2475 for (i
= 0; i
< nargs
; ++i
)
2477 rtx this_arg
= operands
[i
];
2480 /* TFmode arguments and return values are passed by reference. */
2481 if (GET_MODE (this_arg
) == TFmode
)
2483 if (GET_CODE (this_arg
) == MEM
)
2484 this_arg
= XEXP (this_arg
, 0);
2485 else if (CONSTANT_P (this_arg
))
2487 this_slot
= force_const_mem (TFmode
, this_arg
);
2488 this_arg
= XEXP (this_slot
, 0);
2492 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
), 0);
2494 /* Operand 0 is the return value. We'll copy it out later. */
2496 emit_move_insn (this_slot
, this_arg
);
2498 ret_slot
= this_slot
;
2500 this_arg
= XEXP (this_slot
, 0);
2507 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
2509 if (GET_MODE (operands
[0]) == TFmode
)
2512 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
2513 arg
[0], GET_MODE (arg
[0]),
2514 arg
[1], GET_MODE (arg
[1]));
2516 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
2517 arg
[0], GET_MODE (arg
[0]),
2518 arg
[1], GET_MODE (arg
[1]),
2519 arg
[2], GET_MODE (arg
[2]));
2522 emit_move_insn (operands
[0], ret_slot
);
2531 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
2532 GET_MODE (operands
[0]), 1,
2533 arg
[1], GET_MODE (arg
[1]));
2535 if (ret
!= operands
[0])
2536 emit_move_insn (operands
[0], ret
);
2540 /* Expand soft-float TFmode calls to sparc abi routines. */
2543 emit_soft_tfmode_binop (code
, operands
)
2567 emit_soft_tfmode_libcall (func
, 3, operands
);
2571 emit_soft_tfmode_unop (code
, operands
)
2586 emit_soft_tfmode_libcall (func
, 2, operands
);
2590 emit_soft_tfmode_cvt (code
, operands
)
2599 switch (GET_MODE (operands
[1]))
2612 case FLOAT_TRUNCATE
:
2613 switch (GET_MODE (operands
[0]))
2627 switch (GET_MODE (operands
[1]))
2640 case UNSIGNED_FLOAT
:
2641 switch (GET_MODE (operands
[1]))
2655 switch (GET_MODE (operands
[0]))
2669 switch (GET_MODE (operands
[0]))
2686 emit_soft_tfmode_libcall (func
, 2, operands
);
2689 /* Expand a hard-float tfmode operation. All arguments must be in
2693 emit_hard_tfmode_operation (code
, operands
)
2699 if (GET_RTX_CLASS (code
) == '1')
2701 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2702 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
2706 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2707 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
2708 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
2709 operands
[1], operands
[2]);
2712 if (register_operand (operands
[0], VOIDmode
))
2715 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
2717 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op
));
2719 if (dest
!= operands
[0])
2720 emit_move_insn (operands
[0], dest
);
2724 emit_tfmode_binop (code
, operands
)
2728 if (TARGET_HARD_QUAD
)
2729 emit_hard_tfmode_operation (code
, operands
);
2731 emit_soft_tfmode_binop (code
, operands
);
2735 emit_tfmode_unop (code
, operands
)
2739 if (TARGET_HARD_QUAD
)
2740 emit_hard_tfmode_operation (code
, operands
);
2742 emit_soft_tfmode_unop (code
, operands
);
2746 emit_tfmode_cvt (code
, operands
)
2750 if (TARGET_HARD_QUAD
)
2751 emit_hard_tfmode_operation (code
, operands
);
2753 emit_soft_tfmode_cvt (code
, operands
);
2756 /* Return nonzero if a return peephole merging return with
2757 setting of output register is ok. */
2759 leaf_return_peephole_ok ()
2761 return (actual_fsize
== 0);
2764 /* Return nonzero if a branch/jump/call instruction will be emitting
2765 nop into its delay slot. */
2768 empty_delay_slot (insn
)
2773 /* If no previous instruction (should not happen), return true. */
2774 if (PREV_INSN (insn
) == NULL
)
2777 seq
= NEXT_INSN (PREV_INSN (insn
));
2778 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
2784 /* Return nonzero if TRIAL can go into the function epilogue's
2785 delay slot. SLOT is the slot we are trying to fill. */
2788 eligible_for_epilogue_delay (trial
, slot
)
2797 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2800 if (get_attr_length (trial
) != 1)
2803 /* If there are any call-saved registers, we should scan TRIAL if it
2804 does not reference them. For now just make it easy. */
2808 /* If the function uses __builtin_eh_return, the eh_return machinery
2809 occupies the delay slot. */
2810 if (current_function_calls_eh_return
)
2813 /* In the case of a true leaf function, anything can go into the delay slot.
2814 A delay slot only exists however if the frame size is zero, otherwise
2815 we will put an insn to adjust the stack after the return. */
2816 if (current_function_uses_only_leaf_regs
)
2818 if (leaf_return_peephole_ok ())
2819 return ((get_attr_in_uncond_branch_delay (trial
)
2820 == IN_BRANCH_DELAY_TRUE
));
2824 pat
= PATTERN (trial
);
2826 /* Otherwise, only operations which can be done in tandem with
2827 a `restore' or `return' insn can go into the delay slot. */
2828 if (GET_CODE (SET_DEST (pat
)) != REG
2829 || REGNO (SET_DEST (pat
)) < 24)
2832 /* If this instruction sets up floating point register and we have a return
2833 instruction, it can probably go in. But restore will not work
2835 if (REGNO (SET_DEST (pat
)) >= 32)
2837 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1)
2838 && (get_attr_in_uncond_branch_delay (trial
) == IN_BRANCH_DELAY_TRUE
))
2843 /* The set of insns matched here must agree precisely with the set of
2844 patterns paired with a RETURN in sparc.md. */
2846 src
= SET_SRC (pat
);
2848 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2849 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2850 && arith_operand (src
, GET_MODE (src
)))
2853 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2855 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2858 /* This matches "*return_di". */
2859 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2860 && arith_double_operand (src
, GET_MODE (src
)))
2861 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2863 /* This matches "*return_sf_no_fpu". */
2864 else if (! TARGET_FPU
&& restore_operand (SET_DEST (pat
), SFmode
)
2865 && register_operand (src
, SFmode
))
2868 /* If we have return instruction, anything that does not use
2869 local or output registers and can go into a delay slot wins. */
2870 else if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1)
2871 && (get_attr_in_uncond_branch_delay (trial
) == IN_BRANCH_DELAY_TRUE
))
2874 /* This matches "*return_addsi". */
2875 else if (GET_CODE (src
) == PLUS
2876 && arith_operand (XEXP (src
, 0), SImode
)
2877 && arith_operand (XEXP (src
, 1), SImode
)
2878 && (register_operand (XEXP (src
, 0), SImode
)
2879 || register_operand (XEXP (src
, 1), SImode
)))
2882 /* This matches "*return_adddi". */
2883 else if (GET_CODE (src
) == PLUS
2884 && arith_double_operand (XEXP (src
, 0), DImode
)
2885 && arith_double_operand (XEXP (src
, 1), DImode
)
2886 && (register_operand (XEXP (src
, 0), DImode
)
2887 || register_operand (XEXP (src
, 1), DImode
)))
2890 /* This can match "*return_losum_[sd]i".
2891 Catch only some cases, so that return_losum* don't have
2893 else if (GET_CODE (src
) == LO_SUM
2894 && ! TARGET_CM_MEDMID
2895 && ((register_operand (XEXP (src
, 0), SImode
)
2896 && immediate_operand (XEXP (src
, 1), SImode
))
2898 && register_operand (XEXP (src
, 0), DImode
)
2899 && immediate_operand (XEXP (src
, 1), DImode
))))
2902 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2903 else if (GET_CODE (src
) == ASHIFT
2904 && (register_operand (XEXP (src
, 0), SImode
)
2905 || register_operand (XEXP (src
, 0), DImode
))
2906 && XEXP (src
, 1) == const1_rtx
)
2912 /* Return nonzero if TRIAL can go into the sibling call
2916 eligible_for_sibcall_delay (trial
)
2921 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2924 if (get_attr_length (trial
) != 1)
2927 pat
= PATTERN (trial
);
2929 if (current_function_uses_only_leaf_regs
)
2931 /* If the tail call is done using the call instruction,
2932 we have to restore %o7 in the delay slot. */
2933 if ((TARGET_ARCH64
&& ! TARGET_CM_MEDLOW
) || flag_pic
)
2936 /* %g1 is used to build the function address */
2937 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
2943 /* Otherwise, only operations which can be done in tandem with
2944 a `restore' insn can go into the delay slot. */
2945 if (GET_CODE (SET_DEST (pat
)) != REG
2946 || REGNO (SET_DEST (pat
)) < 24
2947 || REGNO (SET_DEST (pat
)) >= 32)
2950 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2952 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
2955 src
= SET_SRC (pat
);
2957 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2958 && arith_operand (src
, GET_MODE (src
)))
2961 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2963 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2966 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2967 && arith_double_operand (src
, GET_MODE (src
)))
2968 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2970 else if (! TARGET_FPU
&& restore_operand (SET_DEST (pat
), SFmode
)
2971 && register_operand (src
, SFmode
))
2974 else if (GET_CODE (src
) == PLUS
2975 && arith_operand (XEXP (src
, 0), SImode
)
2976 && arith_operand (XEXP (src
, 1), SImode
)
2977 && (register_operand (XEXP (src
, 0), SImode
)
2978 || register_operand (XEXP (src
, 1), SImode
)))
2981 else if (GET_CODE (src
) == PLUS
2982 && arith_double_operand (XEXP (src
, 0), DImode
)
2983 && arith_double_operand (XEXP (src
, 1), DImode
)
2984 && (register_operand (XEXP (src
, 0), DImode
)
2985 || register_operand (XEXP (src
, 1), DImode
)))
2988 else if (GET_CODE (src
) == LO_SUM
2989 && ! TARGET_CM_MEDMID
2990 && ((register_operand (XEXP (src
, 0), SImode
)
2991 && immediate_operand (XEXP (src
, 1), SImode
))
2993 && register_operand (XEXP (src
, 0), DImode
)
2994 && immediate_operand (XEXP (src
, 1), DImode
))))
2997 else if (GET_CODE (src
) == ASHIFT
2998 && (register_operand (XEXP (src
, 0), SImode
)
2999 || register_operand (XEXP (src
, 0), DImode
))
3000 && XEXP (src
, 1) == const1_rtx
)
3007 check_return_regs (x
)
3010 switch (GET_CODE (x
))
3013 return IN_OR_GLOBAL_P (x
);
3028 if (check_return_regs (XEXP (x
, 1)) == 0)
3033 return check_return_regs (XEXP (x
, 0));
3041 /* Return 1 if TRIAL references only in and global registers. */
3043 eligible_for_return_delay (trial
)
3046 if (GET_CODE (PATTERN (trial
)) != SET
)
3049 return check_return_regs (PATTERN (trial
));
3053 short_branch (uid1
, uid2
)
3056 int delta
= INSN_ADDRESSES (uid1
) - INSN_ADDRESSES (uid2
);
3058 /* Leave a few words of "slop". */
3059 if (delta
>= -1023 && delta
<= 1022)
3065 /* Return non-zero if REG is not used after INSN.
3066 We assume REG is a reload reg, and therefore does
3067 not live past labels or calls or jumps. */
3069 reg_unused_after (reg
, insn
)
3073 enum rtx_code code
, prev_code
= UNKNOWN
;
3075 while ((insn
= NEXT_INSN (insn
)))
3077 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
3080 code
= GET_CODE (insn
);
3081 if (GET_CODE (insn
) == CODE_LABEL
)
3084 if (GET_RTX_CLASS (code
) == 'i')
3086 rtx set
= single_set (insn
);
3087 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
3090 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
3092 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
3100 /* The table we use to reference PIC data. */
3101 static rtx global_offset_table
;
3103 /* The function we use to get at it. */
3104 static rtx get_pc_symbol
;
3105 static char get_pc_symbol_name
[256];
3107 /* Ensure that we are not using patterns that are not OK with PIC. */
3116 if (GET_CODE (recog_data
.operand
[i
]) == SYMBOL_REF
3117 || (GET_CODE (recog_data
.operand
[i
]) == CONST
3118 && ! (GET_CODE (XEXP (recog_data
.operand
[i
], 0)) == MINUS
3119 && (XEXP (XEXP (recog_data
.operand
[i
], 0), 0)
3120 == global_offset_table
)
3121 && (GET_CODE (XEXP (XEXP (recog_data
.operand
[i
], 0), 1))
3130 /* Return true if X is an address which needs a temporary register when
3131 reloaded while generating PIC code. */
3134 pic_address_needs_scratch (x
)
3137 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3138 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3139 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3140 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3141 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3147 /* Legitimize PIC addresses. If the address is already position-independent,
3148 we return ORIG. Newly generated position-independent addresses go into a
3149 reg. This is REG if non zero, otherwise we allocate register(s) as
3153 legitimize_pic_address (orig
, mode
, reg
)
3155 enum machine_mode mode ATTRIBUTE_UNUSED
;
3158 if (GET_CODE (orig
) == SYMBOL_REF
)
3160 rtx pic_ref
, address
;
3165 if (reload_in_progress
|| reload_completed
)
3168 reg
= gen_reg_rtx (Pmode
);
3173 /* If not during reload, allocate another temp reg here for loading
3174 in the address, so that these instructions can be optimized
3176 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
3177 ? reg
: gen_reg_rtx (Pmode
));
3179 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3180 won't get confused into thinking that these two instructions
3181 are loading in the true address of the symbol. If in the
3182 future a PIC rtx exists, that should be used instead. */
3183 if (Pmode
== SImode
)
3185 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
3186 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3190 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
3191 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3198 pic_ref
= gen_rtx_MEM (Pmode
,
3199 gen_rtx_PLUS (Pmode
,
3200 pic_offset_table_rtx
, address
));
3201 current_function_uses_pic_offset_table
= 1;
3202 RTX_UNCHANGING_P (pic_ref
) = 1;
3203 insn
= emit_move_insn (reg
, pic_ref
);
3204 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3206 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
3210 else if (GET_CODE (orig
) == CONST
)
3214 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3215 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3220 if (reload_in_progress
|| reload_completed
)
3223 reg
= gen_reg_rtx (Pmode
);
3226 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
3228 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
3229 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
3230 base
== reg
? 0 : reg
);
3235 if (GET_CODE (offset
) == CONST_INT
)
3237 if (SMALL_INT (offset
))
3238 return plus_constant (base
, INTVAL (offset
));
3239 else if (! reload_in_progress
&& ! reload_completed
)
3240 offset
= force_reg (Pmode
, offset
);
3242 /* If we reach here, then something is seriously wrong. */
3245 return gen_rtx_PLUS (Pmode
, base
, offset
);
3247 else if (GET_CODE (orig
) == LABEL_REF
)
3248 /* ??? Why do we do this? */
3249 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3250 the register is live instead, in case it is eliminated. */
3251 current_function_uses_pic_offset_table
= 1;
3256 /* Emit special PIC prologues. */
3259 load_pic_register ()
3261 /* Labels to get the PC in the prologue of this function. */
3262 int orig_flag_pic
= flag_pic
;
3267 /* If we haven't emitted the special get_pc helper function, do so now. */
3268 if (get_pc_symbol_name
[0] == 0)
3272 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name
, "LGETPC", 0);
3275 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
3277 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
3278 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "LGETPC", 0);
3279 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file
);
3282 /* Initialize every time through, since we can't easily
3283 know this to be permanent. */
3284 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3285 get_pc_symbol
= gen_rtx_SYMBOL_REF (Pmode
, get_pc_symbol_name
);
3288 emit_insn (gen_get_pc (pic_offset_table_rtx
, global_offset_table
,
3291 flag_pic
= orig_flag_pic
;
3293 /* Need to emit this whether or not we obey regdecls,
3294 since setjmp/longjmp can cause life info to screw up.
3295 ??? In the case where we don't obey regdecls, this is not sufficient
3296 since we may not fall out the bottom. */
3297 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
3300 /* Return 1 if RTX is a MEM which is known to be aligned to at
3301 least a DESIRED byte boundary. */
3304 mem_min_alignment (mem
, desired
)
3308 rtx addr
, base
, offset
;
3310 /* If it's not a MEM we can't accept it. */
3311 if (GET_CODE (mem
) != MEM
)
3314 addr
= XEXP (mem
, 0);
3315 base
= offset
= NULL_RTX
;
3316 if (GET_CODE (addr
) == PLUS
)
3318 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3320 base
= XEXP (addr
, 0);
3322 /* What we are saying here is that if the base
3323 REG is aligned properly, the compiler will make
3324 sure any REG based index upon it will be so
3326 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
3327 offset
= XEXP (addr
, 1);
3329 offset
= const0_rtx
;
3332 else if (GET_CODE (addr
) == REG
)
3335 offset
= const0_rtx
;
3338 if (base
!= NULL_RTX
)
3340 int regno
= REGNO (base
);
3342 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
3344 /* Check if the compiler has recorded some information
3345 about the alignment of the base REG. If reload has
3346 completed, we already matched with proper alignments.
3347 If not running global_alloc, reload might give us
3348 unaligned pointer to local stack though. */
3350 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
3351 || (optimize
&& reload_completed
))
3352 && (INTVAL (offset
) & (desired
- 1)) == 0)
3357 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
3361 else if (! TARGET_UNALIGNED_DOUBLES
3362 || CONSTANT_P (addr
)
3363 || GET_CODE (addr
) == LO_SUM
)
3365 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3366 is true, in which case we can only assume that an access is aligned if
3367 it is to a constant address, or the address involves a LO_SUM. */
3371 /* An obviously unaligned address. */
3376 /* Vectors to keep interesting information about registers where it can easily
3377 be got. We use to use the actual mode value as the bit number, but there
3378 are more than 32 modes now. Instead we use two tables: one indexed by
3379 hard register number, and one indexed by mode. */
3381 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3382 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3383 mapped into one sparc_mode_class mode. */
3385 enum sparc_mode_class
{
3386 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
3387 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
3391 /* Modes for single-word and smaller quantities. */
3392 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3394 /* Modes for double-word and smaller quantities. */
3395 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3397 /* Modes for quad-word and smaller quantities. */
3398 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3400 /* Modes for 8-word and smaller quantities. */
3401 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3403 /* Modes for single-float quantities. We must allow any single word or
3404 smaller quantity. This is because the fix/float conversion instructions
3405 take integer inputs/outputs from the float registers. */
3406 #define SF_MODES (S_MODES)
3408 /* Modes for double-float and smaller quantities. */
3409 #define DF_MODES (S_MODES | D_MODES)
3411 /* Modes for double-float only quantities. */
3412 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3414 /* Modes for quad-float only quantities. */
3415 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3417 /* Modes for quad-float and smaller quantities. */
3418 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3420 /* Modes for quad-float and double-float quantities. */
3421 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3423 /* Modes for quad-float pair only quantities. */
3424 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3426 /* Modes for quad-float pairs and smaller quantities. */
3427 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3429 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3431 /* Modes for condition codes. */
3432 #define CC_MODES (1 << (int) CC_MODE)
3433 #define CCFP_MODES (1 << (int) CCFP_MODE)
3435 /* Value is 1 if register/mode pair is acceptable on sparc.
3436 The funny mixture of D and T modes is because integer operations
3437 do not specially operate on tetra quantities, so non-quad-aligned
3438 registers can hold quadword quantities (except %o4 and %i4 because
3439 they cross fixed registers). */
3441 /* This points to either the 32 bit or the 64 bit version. */
3442 const int *hard_regno_mode_classes
;
3444 static const int hard_32bit_mode_classes
[] = {
3445 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
3446 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
3447 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
3448 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
3450 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3451 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3452 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3453 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3455 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3456 and none can hold SFmode/SImode values. */
3457 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3458 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3459 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3460 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3463 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3469 static const int hard_64bit_mode_classes
[] = {
3470 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3471 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3472 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3473 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3475 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3476 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3477 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3478 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3480 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3481 and none can hold SFmode/SImode values. */
3482 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3483 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3484 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3485 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3488 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3494 int sparc_mode_class
[NUM_MACHINE_MODES
];
3496 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
3503 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
3505 switch (GET_MODE_CLASS (i
))
3508 case MODE_PARTIAL_INT
:
3509 case MODE_COMPLEX_INT
:
3510 if (GET_MODE_SIZE (i
) <= 4)
3511 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
3512 else if (GET_MODE_SIZE (i
) == 8)
3513 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
3514 else if (GET_MODE_SIZE (i
) == 16)
3515 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
3516 else if (GET_MODE_SIZE (i
) == 32)
3517 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
3519 sparc_mode_class
[i
] = 0;
3522 case MODE_COMPLEX_FLOAT
:
3523 if (GET_MODE_SIZE (i
) <= 4)
3524 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
3525 else if (GET_MODE_SIZE (i
) == 8)
3526 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
3527 else if (GET_MODE_SIZE (i
) == 16)
3528 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
3529 else if (GET_MODE_SIZE (i
) == 32)
3530 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
3532 sparc_mode_class
[i
] = 0;
3536 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3537 we must explicitly check for them here. */
3538 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
3539 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
3540 else if (i
== (int) CCmode
|| i
== (int) CC_NOOVmode
3541 || i
== (int) CCXmode
|| i
== (int) CCX_NOOVmode
)
3542 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
3544 sparc_mode_class
[i
] = 0;
3550 hard_regno_mode_classes
= hard_64bit_mode_classes
;
3552 hard_regno_mode_classes
= hard_32bit_mode_classes
;
3554 /* Initialize the array used by REGNO_REG_CLASS. */
3555 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3557 if (i
< 16 && TARGET_V8PLUS
)
3558 sparc_regno_reg_class
[i
] = I64_REGS
;
3559 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
3560 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
3562 sparc_regno_reg_class
[i
] = FP_REGS
;
3564 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
3566 sparc_regno_reg_class
[i
] = FPCC_REGS
;
3568 sparc_regno_reg_class
[i
] = NO_REGS
;
3572 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3573 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3574 v9 int regs as it simplifies the code. */
3577 save_regs (file
, low
, high
, base
, offset
, n_regs
, real_offset
)
3587 if (TARGET_ARCH64
&& high
<= 32)
3589 for (i
= low
; i
< high
; i
++)
3591 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3593 fprintf (file
, "\tstx\t%s, [%s+%d]\n",
3594 reg_names
[i
], base
, offset
+ 4 * n_regs
);
3595 if (dwarf2out_do_frame ())
3596 dwarf2out_reg_save ("", i
, real_offset
+ 4 * n_regs
);
3603 for (i
= low
; i
< high
; i
+= 2)
3605 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3607 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3609 fprintf (file
, "\tstd\t%s, [%s+%d]\n",
3610 reg_names
[i
], base
, offset
+ 4 * n_regs
);
3611 if (dwarf2out_do_frame ())
3613 char *l
= dwarf2out_cfi_label ();
3614 dwarf2out_reg_save (l
, i
, real_offset
+ 4 * n_regs
);
3615 dwarf2out_reg_save (l
, i
+1, real_offset
+ 4 * n_regs
+ 4);
3621 fprintf (file
, "\tst\t%s, [%s+%d]\n",
3622 reg_names
[i
], base
, offset
+ 4 * n_regs
);
3623 if (dwarf2out_do_frame ())
3624 dwarf2out_reg_save ("", i
, real_offset
+ 4 * n_regs
);
3630 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3632 fprintf (file
, "\tst\t%s, [%s+%d]\n",
3633 reg_names
[i
+1], base
, offset
+ 4 * n_regs
+ 4);
3634 if (dwarf2out_do_frame ())
3635 dwarf2out_reg_save ("", i
+ 1, real_offset
+ 4 * n_regs
+ 4);
3644 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
3646 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3647 v9 int regs as it simplifies the code. */
3650 restore_regs (file
, low
, high
, base
, offset
, n_regs
)
3659 if (TARGET_ARCH64
&& high
<= 32)
3661 for (i
= low
; i
< high
; i
++)
3663 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3664 fprintf (file
, "\tldx\t[%s+%d], %s\n",
3665 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3671 for (i
= low
; i
< high
; i
+= 2)
3673 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3674 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3675 fprintf (file
, "\tldd\t[%s+%d], %s\n",
3676 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3679 fprintf (file
, "\tld\t[%s+%d], %s\n",
3680 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3682 else if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3683 fprintf (file
, "\tld\t[%s+%d], %s\n",
3684 base
, offset
+ 4 * n_regs
+ 4, reg_names
[i
+1]),
3691 /* Compute the frame size required by the function. This function is called
3692 during the reload pass and also by output_function_prologue(). */
3695 compute_frame_size (size
, leaf_function
)
3700 int outgoing_args_size
= (current_function_outgoing_args_size
3701 + REG_PARM_STACK_SPACE (current_function_decl
));
3703 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3704 even to v9 int regs to be consistent with save_regs/restore_regs. */
3708 for (i
= 0; i
< 8; i
++)
3709 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3714 for (i
= 0; i
< 8; i
+= 2)
3715 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
3716 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
3720 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
3721 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
3722 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
3725 /* Set up values for use in `function_epilogue'. */
3726 num_gfregs
= n_regs
;
3728 if (leaf_function
&& n_regs
== 0
3729 && size
== 0 && current_function_outgoing_args_size
== 0)
3731 actual_fsize
= apparent_fsize
= 0;
3735 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
3736 apparent_fsize
= (size
- STARTING_FRAME_OFFSET
+ 7) & -8;
3737 apparent_fsize
+= n_regs
* 4;
3738 actual_fsize
= apparent_fsize
+ ((outgoing_args_size
+ 7) & -8);
3741 /* Make sure nothing can clobber our register windows.
3742 If a SAVE must be done, or there is a stack-local variable,
3743 the register window area must be allocated.
3744 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3745 if (leaf_function
== 0 || size
> 0)
3746 actual_fsize
+= (16 * UNITS_PER_WORD
) + (TARGET_ARCH64
? 0 : 8);
3748 return SPARC_STACK_ALIGN (actual_fsize
);
3751 /* Build a (32 bit) big number in a register. */
3752 /* ??? We may be able to use the set macro here too. */
3755 build_big_number (file
, num
, reg
)
3760 if (num
>= 0 || ! TARGET_ARCH64
)
3762 fprintf (file
, "\tsethi\t%%hi(%d), %s\n", num
, reg
);
3763 if ((num
& 0x3ff) != 0)
3764 fprintf (file
, "\tor\t%s, %%lo(%d), %s\n", reg
, num
, reg
);
3766 else /* num < 0 && TARGET_ARCH64 */
3768 /* Sethi does not sign extend, so we must use a little trickery
3769 to use it for negative numbers. Invert the constant before
3770 loading it in, then use xor immediate to invert the loaded bits
3771 (along with the upper 32 bits) to the desired constant. This
3772 works because the sethi and immediate fields overlap. */
3775 int low
= -0x400 + (asize
& 0x3FF);
3777 fprintf (file
, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
3778 inv
, reg
, reg
, low
, reg
);
3782 /* Output any necessary .register pseudo-ops. */
3784 sparc_output_scratch_registers (file
)
3785 FILE *file ATTRIBUTE_UNUSED
;
3787 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
3793 /* Check if %g[2367] were used without
3794 .register being printed for them already. */
3795 for (i
= 2; i
< 8; i
++)
3797 if (regs_ever_live
[i
]
3798 && ! sparc_hard_reg_printed
[i
])
3800 sparc_hard_reg_printed
[i
] = 1;
3801 fprintf (file
, "\t.register\t%%g%d, #scratch\n", i
);
3808 /* This function generates the assembly code for function entry.
3809 FILE is a stdio stream to output the code to.
3810 SIZE is an int: how many units of temporary storage to allocate.
3811 Refer to the array `regs_ever_live' to determine which registers
3812 to save; `regs_ever_live[I]' is nonzero if register number I
3813 is ever used in the function. This macro is responsible for
3814 knowing which registers should not be saved even if used. */
3816 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
3817 of memory. If any fpu reg is used in the function, we allocate
3818 such a block here, at the bottom of the frame, just in case it's needed.
3820 If this function is a leaf procedure, then we may choose not
3821 to do a "save" insn. The decision about whether or not
3822 to do this is made in regclass.c. */
3825 sparc_output_function_prologue (file
, size
)
3830 sparc_flat_function_prologue (file
, size
);
3832 sparc_nonflat_function_prologue (file
, size
,
3833 current_function_uses_only_leaf_regs
);
3836 /* Output code for the function prologue. */
3839 sparc_nonflat_function_prologue (file
, size
, leaf_function
)
3844 sparc_output_scratch_registers (file
);
3846 /* Need to use actual_fsize, since we are also allocating
3847 space for our callee (and our own register save area). */
3848 actual_fsize
= compute_frame_size (size
, leaf_function
);
3852 frame_base_name
= "%sp";
3853 frame_base_offset
= actual_fsize
+ SPARC_STACK_BIAS
;
3857 frame_base_name
= "%fp";
3858 frame_base_offset
= SPARC_STACK_BIAS
;
3861 /* This is only for the human reader. */
3862 fprintf (file
, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START
);
3864 if (actual_fsize
== 0)
3866 else if (! leaf_function
)
3868 if (actual_fsize
<= 4096)
3869 fprintf (file
, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize
);
3870 else if (actual_fsize
<= 8192)
3872 fprintf (file
, "\tsave\t%%sp, -4096, %%sp\n");
3873 fprintf (file
, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize
- 4096);
3877 build_big_number (file
, -actual_fsize
, "%g1");
3878 fprintf (file
, "\tsave\t%%sp, %%g1, %%sp\n");
3881 else /* leaf function */
3883 if (actual_fsize
<= 4096)
3884 fprintf (file
, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize
);
3885 else if (actual_fsize
<= 8192)
3887 fprintf (file
, "\tadd\t%%sp, -4096, %%sp\n");
3888 fprintf (file
, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize
- 4096);
3892 build_big_number (file
, -actual_fsize
, "%g1");
3893 fprintf (file
, "\tadd\t%%sp, %%g1, %%sp\n");
3897 if (dwarf2out_do_frame () && actual_fsize
)
3899 char *label
= dwarf2out_cfi_label ();
3901 /* The canonical frame address refers to the top of the frame. */
3902 dwarf2out_def_cfa (label
, (leaf_function
? STACK_POINTER_REGNUM
3903 : HARD_FRAME_POINTER_REGNUM
),
3906 if (! leaf_function
)
3908 /* Note the register window save. This tells the unwinder that
3909 it needs to restore the window registers from the previous
3910 frame's window save area at 0(cfa). */
3911 dwarf2out_window_save (label
);
3913 /* The return address (-8) is now in %i7. */
3914 dwarf2out_return_reg (label
, 31);
3918 /* If doing anything with PIC, do it now. */
3920 fprintf (file
, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START
);
3922 /* Call saved registers are saved just above the outgoing argument area. */
3925 int offset
, real_offset
, n_regs
;
3928 real_offset
= -apparent_fsize
;
3929 offset
= -apparent_fsize
+ frame_base_offset
;
3930 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096)
3932 /* ??? This might be optimized a little as %g1 might already have a
3933 value close enough that a single add insn will do. */
3934 /* ??? Although, all of this is probably only a temporary fix
3935 because if %g1 can hold a function result, then
3936 output_function_epilogue will lose (the result will get
3938 build_big_number (file
, offset
, "%g1");
3939 fprintf (file
, "\tadd\t%s, %%g1, %%g1\n", frame_base_name
);
3945 base
= frame_base_name
;
3948 n_regs
= save_regs (file
, 0, 8, base
, offset
, 0, real_offset
);
3949 save_regs (file
, 32, TARGET_V9
? 96 : 64, base
, offset
, n_regs
,
3954 /* Output code to restore any call saved registers. */
3957 output_restore_regs (file
, leaf_function
)
3959 int leaf_function ATTRIBUTE_UNUSED
;
3964 offset
= -apparent_fsize
+ frame_base_offset
;
3965 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096 - 8 /*double*/)
3967 build_big_number (file
, offset
, "%g1");
3968 fprintf (file
, "\tadd\t%s, %%g1, %%g1\n", frame_base_name
);
3974 base
= frame_base_name
;
3977 n_regs
= restore_regs (file
, 0, 8, base
, offset
, 0);
3978 restore_regs (file
, 32, TARGET_V9
? 96 : 64, base
, offset
, n_regs
);
3981 /* This function generates the assembly code for function exit,
3982 on machines that need it.
3984 The function epilogue should not depend on the current stack pointer!
3985 It should use the frame pointer only. This is mandatory because
3986 of alloca; we also take advantage of it to omit stack adjustments
3987 before returning. */
3990 sparc_output_function_epilogue (file
, size
)
3995 sparc_flat_function_epilogue (file
, size
);
3997 sparc_nonflat_function_epilogue (file
, size
,
3998 current_function_uses_only_leaf_regs
);
4001 /* Output code for the function epilogue. */
4004 sparc_nonflat_function_epilogue (file
, size
, leaf_function
)
4006 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
4011 if (current_function_epilogue_delay_list
== 0)
4013 /* If code does not drop into the epilogue, we need
4014 do nothing except output pending case vectors.
4016 We have to still output a dummy nop for the sake of
4017 sane backtraces. Otherwise, if the last two instructions
4018 of a function were call foo; dslot; this can make the return
4019 PC of foo (ie. address of call instruction plus 8) point to
4020 the first instruction in the next function. */
4023 fputs("\tnop\n", file
);
4025 insn
= get_last_insn ();
4026 if (GET_CODE (insn
) == NOTE
)
4027 insn
= prev_nonnote_insn (insn
);
4028 if (insn
&& GET_CODE (insn
) == BARRIER
)
4029 goto output_vectors
;
4033 output_restore_regs (file
, leaf_function
);
4035 /* Work out how to skip the caller's unimp instruction if required. */
4037 ret
= (SKIP_CALLERS_UNIMP_P
? "jmp\t%o7+12" : "retl");
4039 ret
= (SKIP_CALLERS_UNIMP_P
? "jmp\t%i7+12" : "ret");
4041 if (! leaf_function
)
4043 if (current_function_calls_eh_return
)
4045 if (current_function_epilogue_delay_list
)
4047 if (SKIP_CALLERS_UNIMP_P
)
4050 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file
);
4052 /* If we wound up with things in our delay slot, flush them here. */
4053 else if (current_function_epilogue_delay_list
)
4055 rtx delay
= PATTERN (XEXP (current_function_epilogue_delay_list
, 0));
4057 if (TARGET_V9
&& ! epilogue_renumber (&delay
, 1))
4059 epilogue_renumber (&delay
, 0);
4060 fputs (SKIP_CALLERS_UNIMP_P
4061 ? "\treturn\t%i7+12\n"
4062 : "\treturn\t%i7+8\n", file
);
4063 final_scan_insn (XEXP (current_function_epilogue_delay_list
, 0),
4070 if (GET_CODE (delay
) != SET
)
4073 src
= SET_SRC (delay
);
4074 if (GET_CODE (src
) == ASHIFT
)
4076 if (XEXP (src
, 1) != const1_rtx
)
4079 = gen_rtx_PLUS (GET_MODE (src
), XEXP (src
, 0),
4083 insn
= gen_rtx_PARALLEL (VOIDmode
,
4084 gen_rtvec (2, delay
,
4085 gen_rtx_RETURN (VOIDmode
)));
4086 insn
= emit_jump_insn (insn
);
4088 sparc_emitting_epilogue
= true;
4089 final_scan_insn (insn
, file
, 1, 0, 1);
4090 sparc_emitting_epilogue
= false;
4093 else if (TARGET_V9
&& ! SKIP_CALLERS_UNIMP_P
)
4094 fputs ("\treturn\t%i7+8\n\tnop\n", file
);
4096 fprintf (file
, "\t%s\n\trestore\n", ret
);
4098 /* All of the following cases are for leaf functions. */
4099 else if (current_function_calls_eh_return
)
4101 else if (current_function_epilogue_delay_list
)
4103 /* eligible_for_epilogue_delay_slot ensures that if this is a
4104 leaf function, then we will only have insn in the delay slot
4105 if the frame size is zero, thus no adjust for the stack is
4107 if (actual_fsize
!= 0)
4109 fprintf (file
, "\t%s\n", ret
);
4110 final_scan_insn (XEXP (current_function_epilogue_delay_list
, 0),
4113 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4114 avoid generating confusing assembly language output. */
4115 else if (actual_fsize
== 0)
4116 fprintf (file
, "\t%s\n\tnop\n", ret
);
4117 else if (actual_fsize
<= 4096)
4118 fprintf (file
, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret
, actual_fsize
);
4119 else if (actual_fsize
<= 8192)
4120 fprintf (file
, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
4121 ret
, actual_fsize
- 4096);
4122 else if ((actual_fsize
& 0x3ff) == 0)
4123 fprintf (file
, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4126 fprintf (file
, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4127 actual_fsize
, actual_fsize
, ret
);
4130 sparc_output_deferred_case_vectors ();
4133 /* Output a sibling call. */
4136 output_sibcall (insn
, call_operand
)
4137 rtx insn
, call_operand
;
4139 int leaf_regs
= current_function_uses_only_leaf_regs
;
4141 int delay_slot
= dbr_sequence_length () > 0;
4145 /* Call to restore global regs might clobber
4146 the delay slot. Instead of checking for this
4147 output the delay slot now. */
4150 rtx delay
= NEXT_INSN (insn
);
4155 final_scan_insn (delay
, asm_out_file
, 1, 0, 1);
4156 PATTERN (delay
) = gen_blockage ();
4157 INSN_CODE (delay
) = -1;
4160 output_restore_regs (asm_out_file
, leaf_regs
);
4163 operands
[0] = call_operand
;
4167 #ifdef HAVE_AS_RELAX_OPTION
4168 /* If as and ld are relaxing tail call insns into branch always,
4169 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4170 be optimized. With sethi/jmpl as nor ld has no easy way how to
4171 find out if somebody does not branch between the sethi and jmpl. */
4174 int spare_slot
= ((TARGET_ARCH32
|| TARGET_CM_MEDLOW
) && ! flag_pic
);
4178 if ((actual_fsize
|| ! spare_slot
) && delay_slot
)
4180 rtx delay
= NEXT_INSN (insn
);
4185 final_scan_insn (delay
, asm_out_file
, 1, 0, 1);
4186 PATTERN (delay
) = gen_blockage ();
4187 INSN_CODE (delay
) = -1;
4192 if (actual_fsize
<= 4096)
4193 size
= actual_fsize
;
4194 else if (actual_fsize
<= 8192)
4196 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file
);
4197 size
= actual_fsize
- 4096;
4199 else if ((actual_fsize
& 0x3ff) == 0)
4200 fprintf (asm_out_file
,
4201 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n",
4205 fprintf (asm_out_file
,
4206 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n",
4207 actual_fsize
, actual_fsize
);
4208 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file
);
4213 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands
);
4214 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands
);
4216 fprintf (asm_out_file
, "\t sub\t%%sp, -%d, %%sp\n", size
);
4217 else if (! delay_slot
)
4218 fputs ("\t nop\n", asm_out_file
);
4223 fprintf (asm_out_file
, "\tsub\t%%sp, -%d, %%sp\n", size
);
4224 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4225 it into branch if possible. */
4226 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands
);
4227 output_asm_insn ("call\t%a0, 0", operands
);
4228 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands
);
4233 output_asm_insn ("call\t%a0, 0", operands
);
4236 rtx delay
= NEXT_INSN (insn
), pat
;
4241 pat
= PATTERN (delay
);
4242 if (GET_CODE (pat
) != SET
)
4245 operands
[0] = SET_DEST (pat
);
4246 pat
= SET_SRC (pat
);
4247 switch (GET_CODE (pat
))
4250 operands
[1] = XEXP (pat
, 0);
4251 operands
[2] = XEXP (pat
, 1);
4252 output_asm_insn (" restore %r1, %2, %Y0", operands
);
4255 operands
[1] = XEXP (pat
, 0);
4256 operands
[2] = XEXP (pat
, 1);
4257 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
4260 operands
[1] = XEXP (pat
, 0);
4261 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
4265 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
4268 PATTERN (delay
) = gen_blockage ();
4269 INSN_CODE (delay
) = -1;
4272 fputs ("\t restore\n", asm_out_file
);
4276 /* Functions for handling argument passing.
4278 For v8 the first six args are normally in registers and the rest are
4279 pushed. Any arg that starts within the first 6 words is at least
4280 partially passed in a register unless its data type forbids.
4282 For v9, the argument registers are laid out as an array of 16 elements
4283 and arguments are added sequentially. The first 6 int args and up to the
4284 first 16 fp args (depending on size) are passed in regs.
4286 Slot Stack Integral Float Float in structure Double Long Double
4287 ---- ----- -------- ----- ------------------ ------ -----------
4288 15 [SP+248] %f31 %f30,%f31 %d30
4289 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4290 13 [SP+232] %f27 %f26,%f27 %d26
4291 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4292 11 [SP+216] %f23 %f22,%f23 %d22
4293 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4294 9 [SP+200] %f19 %f18,%f19 %d18
4295 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4296 7 [SP+184] %f15 %f14,%f15 %d14
4297 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4298 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4299 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4300 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4301 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4302 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4303 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4305 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4307 Integral arguments are always passed as 64 bit quantities appropriately
4310 Passing of floating point values is handled as follows.
4311 If a prototype is in scope:
4312 If the value is in a named argument (i.e. not a stdarg function or a
4313 value not part of the `...') then the value is passed in the appropriate
4315 If the value is part of the `...' and is passed in one of the first 6
4316 slots then the value is passed in the appropriate int reg.
4317 If the value is part of the `...' and is not passed in one of the first 6
4318 slots then the value is passed in memory.
4319 If a prototype is not in scope:
4320 If the value is one of the first 6 arguments the value is passed in the
4321 appropriate integer reg and the appropriate fp reg.
4322 If the value is not one of the first 6 arguments the value is passed in
4323 the appropriate fp reg and in memory.
4326 /* Maximum number of int regs for args. */
4327 #define SPARC_INT_ARG_MAX 6
4328 /* Maximum number of fp regs for args. */
4329 #define SPARC_FP_ARG_MAX 16
4331 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4333 /* Handle the INIT_CUMULATIVE_ARGS macro.
4334 Initialize a variable CUM of type CUMULATIVE_ARGS
4335 for a call to a function whose data type is FNTYPE.
4336 For a library call, FNTYPE is 0. */
4339 init_cumulative_args (cum
, fntype
, libname
, indirect
)
4340 CUMULATIVE_ARGS
*cum
;
4342 rtx libname ATTRIBUTE_UNUSED
;
4343 int indirect ATTRIBUTE_UNUSED
;
4346 cum
->prototype_p
= fntype
&& TYPE_ARG_TYPES (fntype
);
4347 cum
->libcall_p
= fntype
== 0;
4350 /* Compute the slot number to pass an argument in.
4351 Returns the slot number or -1 if passing on the stack.
4353 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4354 the preceding args and about the function being called.
4355 MODE is the argument's machine mode.
4356 TYPE is the data type of the argument (as a tree).
4357 This is null for libcalls where that information may
4359 NAMED is nonzero if this argument is a named parameter
4360 (otherwise it is an extra parameter matching an ellipsis).
4361 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4362 *PREGNO records the register number to use if scalar type.
4363 *PPADDING records the amount of padding needed in words. */
4366 function_arg_slotno (cum
, mode
, type
, named
, incoming_p
, pregno
, ppadding
)
4367 const CUMULATIVE_ARGS
*cum
;
4368 enum machine_mode mode
;
4375 int regbase
= (incoming_p
4376 ? SPARC_INCOMING_INT_ARG_FIRST
4377 : SPARC_OUTGOING_INT_ARG_FIRST
);
4378 int slotno
= cum
->words
;
4383 if (type
!= 0 && TREE_ADDRESSABLE (type
))
4386 && type
!= 0 && mode
== BLKmode
4387 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
4393 /* MODE is VOIDmode when generating the actual call.
4397 case QImode
: case CQImode
:
4398 case HImode
: case CHImode
:
4399 case SImode
: case CSImode
:
4400 case DImode
: case CDImode
:
4401 case TImode
: case CTImode
:
4402 if (slotno
>= SPARC_INT_ARG_MAX
)
4404 regno
= regbase
+ slotno
;
4407 case SFmode
: case SCmode
:
4408 case DFmode
: case DCmode
:
4409 case TFmode
: case TCmode
:
4412 if (slotno
>= SPARC_INT_ARG_MAX
)
4414 regno
= regbase
+ slotno
;
4418 if ((mode
== TFmode
|| mode
== TCmode
)
4419 && (slotno
& 1) != 0)
4420 slotno
++, *ppadding
= 1;
4421 if (TARGET_FPU
&& named
)
4423 if (slotno
>= SPARC_FP_ARG_MAX
)
4425 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
4431 if (slotno
>= SPARC_INT_ARG_MAX
)
4433 regno
= regbase
+ slotno
;
4439 /* For sparc64, objects requiring 16 byte alignment get it. */
4442 if (type
&& TYPE_ALIGN (type
) == 128 && (slotno
& 1) != 0)
4443 slotno
++, *ppadding
= 1;
4447 || (type
&& TREE_CODE (type
) == UNION_TYPE
))
4449 if (slotno
>= SPARC_INT_ARG_MAX
)
4451 regno
= regbase
+ slotno
;
4456 int intregs_p
= 0, fpregs_p
= 0;
4457 /* The ABI obviously doesn't specify how packed
4458 structures are passed. These are defined to be passed
4459 in int regs if possible, otherwise memory. */
4462 /* First see what kinds of registers we need. */
4463 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4465 if (TREE_CODE (field
) == FIELD_DECL
)
4467 if (TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4472 if (DECL_PACKED (field
))
4476 if (packed_p
|| !named
)
4477 fpregs_p
= 0, intregs_p
= 1;
4479 /* If all arg slots are filled, then must pass on stack. */
4480 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
4482 /* If there are only int args and all int arg slots are filled,
4483 then must pass on stack. */
4484 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
4486 /* Note that even if all int arg slots are filled, fp members may
4487 still be passed in regs if such regs are available.
4488 *PREGNO isn't set because there may be more than one, it's up
4489 to the caller to compute them. */
4502 /* Handle recursive register counting for structure field layout. */
4504 struct function_arg_record_value_parms
4507 int slotno
, named
, regbase
;
4512 static void function_arg_record_value_3
4513 PARAMS ((HOST_WIDE_INT
, struct function_arg_record_value_parms
*));
4514 static void function_arg_record_value_2
4515 PARAMS ((tree
, HOST_WIDE_INT
,
4516 struct function_arg_record_value_parms
*));
4517 static void function_arg_record_value_1
4518 PARAMS ((tree
, HOST_WIDE_INT
,
4519 struct function_arg_record_value_parms
*));
4520 static rtx function_arg_record_value
4521 PARAMS ((tree
, enum machine_mode
, int, int, int));
4523 /* A subroutine of function_arg_record_value. Traverse the structure
4524 recusively and determine how many registers will be required. */
4527 function_arg_record_value_1 (type
, startbitpos
, parms
)
4529 HOST_WIDE_INT startbitpos
;
4530 struct function_arg_record_value_parms
*parms
;
4534 /* The ABI obviously doesn't specify how packed structures are
4535 passed. These are defined to be passed in int regs if possible,
4536 otherwise memory. */
4539 /* We need to compute how many registers are needed so we can
4540 allocate the PARALLEL but before we can do that we need to know
4541 whether there are any packed fields. If there are, int regs are
4542 used regardless of whether there are fp values present. */
4543 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4545 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
4552 /* Compute how many registers we need. */
4553 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4555 if (TREE_CODE (field
) == FIELD_DECL
)
4557 HOST_WIDE_INT bitpos
= startbitpos
;
4559 if (DECL_SIZE (field
) != 0
4560 && host_integerp (bit_position (field
), 1))
4561 bitpos
+= int_bit_position (field
);
4563 /* ??? FIXME: else assume zero offset. */
4565 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
4566 function_arg_record_value_1 (TREE_TYPE (field
), bitpos
, parms
);
4567 else if ((TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4568 || (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
4569 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field
)))
4575 if (parms
->intoffset
!= -1)
4577 int intslots
, this_slotno
;
4579 intslots
= (bitpos
- parms
->intoffset
+ BITS_PER_WORD
- 1)
4581 this_slotno
= parms
->slotno
+ parms
->intoffset
4584 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
4585 intslots
= MAX (intslots
, 0);
4586 parms
->nregs
+= intslots
;
4587 parms
->intoffset
= -1;
4590 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4591 If it wasn't true we wouldn't be here. */
4593 if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
4598 if (parms
->intoffset
== -1)
4599 parms
->intoffset
= bitpos
;
4605 /* A subroutine of function_arg_record_value. Assign the bits of the
4606 structure between parms->intoffset and bitpos to integer registers. */
4609 function_arg_record_value_3 (bitpos
, parms
)
4610 HOST_WIDE_INT bitpos
;
4611 struct function_arg_record_value_parms
*parms
;
4613 enum machine_mode mode
;
4615 unsigned int startbit
, endbit
;
4616 int this_slotno
, intslots
, intoffset
;
4619 if (parms
->intoffset
== -1)
4622 intoffset
= parms
->intoffset
;
4623 parms
->intoffset
= -1;
4625 startbit
= intoffset
& -BITS_PER_WORD
;
4626 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
4627 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
4628 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
4630 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
4634 /* If this is the trailing part of a word, only load that much into
4635 the register. Otherwise load the whole register. Note that in
4636 the latter case we may pick up unwanted bits. It's not a problem
4637 at the moment but may wish to revisit. */
4639 if (intoffset
% BITS_PER_WORD
!= 0)
4640 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
4645 intoffset
/= BITS_PER_UNIT
;
4648 regno
= parms
->regbase
+ this_slotno
;
4649 reg
= gen_rtx_REG (mode
, regno
);
4650 XVECEXP (parms
->ret
, 0, parms
->nregs
)
4651 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
4654 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
4658 while (intslots
> 0);
4661 /* A subroutine of function_arg_record_value. Traverse the structure
4662 recursively and assign bits to floating point registers. Track which
4663 bits in between need integer registers; invoke function_arg_record_value_3
4664 to make that happen. */
4667 function_arg_record_value_2 (type
, startbitpos
, parms
)
4669 HOST_WIDE_INT startbitpos
;
4670 struct function_arg_record_value_parms
*parms
;
4675 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4677 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
4684 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4686 if (TREE_CODE (field
) == FIELD_DECL
)
4688 HOST_WIDE_INT bitpos
= startbitpos
;
4690 if (DECL_SIZE (field
) != 0
4691 && host_integerp (bit_position (field
), 1))
4692 bitpos
+= int_bit_position (field
);
4694 /* ??? FIXME: else assume zero offset. */
4696 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
4697 function_arg_record_value_2 (TREE_TYPE (field
), bitpos
, parms
);
4698 else if ((TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4699 || (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
4700 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field
)))
4706 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
4708 enum machine_mode mode
= DECL_MODE (field
);
4711 function_arg_record_value_3 (bitpos
, parms
);
4712 regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2
4713 + ((mode
== SFmode
|| mode
== SCmode
)
4714 && (bitpos
& 32) != 0);
4717 case SCmode
: mode
= SFmode
; break;
4718 case DCmode
: mode
= DFmode
; break;
4719 case TCmode
: mode
= TFmode
; break;
4722 reg
= gen_rtx_REG (mode
, regno
);
4723 XVECEXP (parms
->ret
, 0, parms
->nregs
)
4724 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4725 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4727 if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
4729 regno
+= GET_MODE_SIZE (mode
) / 4;
4730 reg
= gen_rtx_REG (mode
, regno
);
4731 XVECEXP (parms
->ret
, 0, parms
->nregs
)
4732 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4733 GEN_INT ((bitpos
+ GET_MODE_BITSIZE (mode
))
4740 if (parms
->intoffset
== -1)
4741 parms
->intoffset
= bitpos
;
4747 /* Used by function_arg and function_value to implement the complex
4748 Sparc64 structure calling conventions. */
4751 function_arg_record_value (type
, mode
, slotno
, named
, regbase
)
4753 enum machine_mode mode
;
4754 int slotno
, named
, regbase
;
4756 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
4757 struct function_arg_record_value_parms parms
;
4760 parms
.ret
= NULL_RTX
;
4761 parms
.slotno
= slotno
;
4762 parms
.named
= named
;
4763 parms
.regbase
= regbase
;
4765 /* Compute how many registers we need. */
4767 parms
.intoffset
= 0;
4768 function_arg_record_value_1 (type
, 0, &parms
);
4770 if (parms
.intoffset
!= -1)
4772 unsigned int startbit
, endbit
;
4773 int intslots
, this_slotno
;
4775 startbit
= parms
.intoffset
& -BITS_PER_WORD
;
4776 endbit
= (typesize
*BITS_PER_UNIT
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
4777 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
4778 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
4780 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
4781 intslots
= MAX (intslots
, 0);
4783 parms
.nregs
+= intslots
;
4785 nregs
= parms
.nregs
;
4787 /* Allocate the vector and handle some annoying special cases. */
4790 /* ??? Empty structure has no value? Duh? */
4793 /* Though there's nothing really to store, return a word register
4794 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
4795 leads to breakage due to the fact that there are zero bytes to
4797 return gen_rtx_REG (mode
, regbase
);
4801 /* ??? C++ has structures with no fields, and yet a size. Give up
4802 for now and pass everything back in integer registers. */
4803 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4805 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
4806 nregs
= SPARC_INT_ARG_MAX
- slotno
;
4811 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nregs
));
4813 /* Fill in the entries. */
4815 parms
.intoffset
= 0;
4816 function_arg_record_value_2 (type
, 0, &parms
);
4817 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
4819 if (parms
.nregs
!= nregs
)
4825 /* Handle the FUNCTION_ARG macro.
4826 Determine where to put an argument to a function.
4827 Value is zero to push the argument on the stack,
4828 or a hard register in which to store the argument.
4830 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4831 the preceding args and about the function being called.
4832 MODE is the argument's machine mode.
4833 TYPE is the data type of the argument (as a tree).
4834 This is null for libcalls where that information may
4836 NAMED is nonzero if this argument is a named parameter
4837 (otherwise it is an extra parameter matching an ellipsis).
4838 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
4841 function_arg (cum
, mode
, type
, named
, incoming_p
)
4842 const CUMULATIVE_ARGS
*cum
;
4843 enum machine_mode mode
;
4848 int regbase
= (incoming_p
4849 ? SPARC_INCOMING_INT_ARG_FIRST
4850 : SPARC_OUTGOING_INT_ARG_FIRST
);
4851 int slotno
, regno
, padding
;
4854 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
4862 reg
= gen_rtx_REG (mode
, regno
);
4866 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
4867 but also have the slot allocated for them.
4868 If no prototype is in scope fp values in register slots get passed
4869 in two places, either fp regs and int regs or fp regs and memory. */
4870 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4871 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4872 && SPARC_FP_REG_P (regno
))
4874 reg
= gen_rtx_REG (mode
, regno
);
4875 if (cum
->prototype_p
|| cum
->libcall_p
)
4877 /* "* 2" because fp reg numbers are recorded in 4 byte
4880 /* ??? This will cause the value to be passed in the fp reg and
4881 in the stack. When a prototype exists we want to pass the
4882 value in the reg but reserve space on the stack. That's an
4883 optimization, and is deferred [for a bit]. */
4884 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
4885 return gen_rtx_PARALLEL (mode
,
4887 gen_rtx_EXPR_LIST (VOIDmode
,
4888 NULL_RTX
, const0_rtx
),
4889 gen_rtx_EXPR_LIST (VOIDmode
,
4893 /* ??? It seems that passing back a register even when past
4894 the area declared by REG_PARM_STACK_SPACE will allocate
4895 space appropriately, and will not copy the data onto the
4896 stack, exactly as we desire.
4898 This is due to locate_and_pad_parm being called in
4899 expand_call whenever reg_parm_stack_space > 0, which
4900 while benefical to our example here, would seem to be
4901 in error from what had been intended. Ho hum... -- r~ */
4909 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
4913 /* On incoming, we don't need to know that the value
4914 is passed in %f0 and %i0, and it confuses other parts
4915 causing needless spillage even on the simplest cases. */
4919 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
4920 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
4922 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
4923 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
4925 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
4929 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
4930 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
4931 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
4935 else if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
4937 /* Structures up to 16 bytes in size are passed in arg slots on the
4938 stack and are promoted to registers where possible. */
4940 if (int_size_in_bytes (type
) > 16)
4941 abort (); /* shouldn't get here */
4943 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
4945 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
4947 enum machine_mode mode
;
4948 int bytes
= int_size_in_bytes (type
);
4953 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 0);
4954 reg
= gen_rtx_REG (mode
, regno
);
4958 /* Scalar or complex int. */
4959 reg
= gen_rtx_REG (mode
, regno
);
4965 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
4966 For an arg passed partly in registers and partly in memory,
4967 this is the number of registers used.
4968 For args passed entirely in registers or entirely in memory, zero.
4970 Any arg that starts in the first 6 regs but won't entirely fit in them
4971 needs partial registers on v8. On v9, structures with integer
4972 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
4973 values that begin in the last fp reg [where "last fp reg" varies with the
4974 mode] will be split between that reg and memory. */
4977 function_arg_partial_nregs (cum
, mode
, type
, named
)
4978 const CUMULATIVE_ARGS
*cum
;
4979 enum machine_mode mode
;
4983 int slotno
, regno
, padding
;
4985 /* We pass 0 for incoming_p here, it doesn't matter. */
4986 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
4993 if ((slotno
+ (mode
== BLKmode
4994 ? ROUND_ADVANCE (int_size_in_bytes (type
))
4995 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
4996 > NPARM_REGS (SImode
))
4997 return NPARM_REGS (SImode
) - slotno
;
5002 if (type
&& AGGREGATE_TYPE_P (type
))
5004 int size
= int_size_in_bytes (type
);
5005 int align
= TYPE_ALIGN (type
);
5008 slotno
+= slotno
& 1;
5009 if (size
> 8 && size
<= 16
5010 && slotno
== SPARC_INT_ARG_MAX
- 1)
5013 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
5014 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5017 if (GET_MODE_ALIGNMENT (mode
) == 128)
5019 slotno
+= slotno
& 1;
5020 if (slotno
== SPARC_INT_ARG_MAX
- 2)
5025 if (slotno
== SPARC_INT_ARG_MAX
- 1)
5029 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5031 if (GET_MODE_ALIGNMENT (mode
) == 128)
5032 slotno
+= slotno
& 1;
5033 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
5041 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5042 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5043 quad-precision floats by invisible reference.
5044 v9: Aggregates greater than 16 bytes are passed by reference.
5045 For Pascal, also pass arrays by reference. */
5048 function_arg_pass_by_reference (cum
, mode
, type
, named
)
5049 const CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
;
5050 enum machine_mode mode
;
5052 int named ATTRIBUTE_UNUSED
;
5056 return ((type
&& AGGREGATE_TYPE_P (type
))
5057 || mode
== TFmode
|| mode
== TCmode
);
5061 return ((type
&& TREE_CODE (type
) == ARRAY_TYPE
)
5062 /* Consider complex values as aggregates, so care for TCmode. */
5063 || GET_MODE_SIZE (mode
) > 16
5065 && AGGREGATE_TYPE_P (type
)
5066 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16));
5070 /* Handle the FUNCTION_ARG_ADVANCE macro.
5071 Update the data in CUM to advance over an argument
5072 of mode MODE and data type TYPE.
5073 TYPE is null for libcalls where that information may not be available. */
5076 function_arg_advance (cum
, mode
, type
, named
)
5077 CUMULATIVE_ARGS
*cum
;
5078 enum machine_mode mode
;
5082 int slotno
, regno
, padding
;
5084 /* We pass 0 for incoming_p here, it doesn't matter. */
5085 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
5087 /* If register required leading padding, add it. */
5089 cum
->words
+= padding
;
5093 cum
->words
+= (mode
!= BLKmode
5094 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
5095 : ROUND_ADVANCE (int_size_in_bytes (type
)));
5099 if (type
&& AGGREGATE_TYPE_P (type
))
5101 int size
= int_size_in_bytes (type
);
5105 else if (size
<= 16)
5107 else /* passed by reference */
5110 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
)
5114 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5116 cum
->words
+= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
5120 cum
->words
+= (mode
!= BLKmode
5121 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
5122 : ROUND_ADVANCE (int_size_in_bytes (type
)));
5127 /* Handle the FUNCTION_ARG_PADDING macro.
5128 For the 64 bit ABI structs are always stored left shifted in their
5132 function_arg_padding (mode
, type
)
5133 enum machine_mode mode
;
5136 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
5139 /* This is the default definition. */
5140 return (! BYTES_BIG_ENDIAN
5143 ? (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
5144 && int_size_in_bytes (type
) < (PARM_BOUNDARY
/ BITS_PER_UNIT
))
5145 : GET_MODE_BITSIZE (mode
) < PARM_BOUNDARY
)
5146 ? downward
: upward
));
5149 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5150 For v9, function return values are subject to the same rules as arguments,
5151 except that up to 32-bytes may be returned in registers. */
5154 function_value (type
, mode
, incoming_p
)
5156 enum machine_mode mode
;
5160 int regbase
= (incoming_p
5161 ? SPARC_OUTGOING_INT_ARG_FIRST
5162 : SPARC_INCOMING_INT_ARG_FIRST
);
5164 if (TARGET_ARCH64
&& type
)
5166 if (TREE_CODE (type
) == RECORD_TYPE
)
5168 /* Structures up to 32 bytes in size are passed in registers,
5169 promoted to fp registers where possible. */
5171 if (int_size_in_bytes (type
) > 32)
5172 abort (); /* shouldn't get here */
5174 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
5176 else if (AGGREGATE_TYPE_P (type
))
5178 /* All other aggregate types are passed in an integer register
5179 in a mode corresponding to the size of the type. */
5180 HOST_WIDE_INT bytes
= int_size_in_bytes (type
);
5185 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 0);
5190 && GET_MODE_CLASS (mode
) == MODE_INT
5191 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
5192 && type
&& ! AGGREGATE_TYPE_P (type
))
5196 regno
= BASE_RETURN_VALUE_REG (mode
);
5198 regno
= BASE_OUTGOING_VALUE_REG (mode
);
5200 return gen_rtx_REG (mode
, regno
);
5203 /* Do what is necessary for `va_start'. We look at the current function
5204 to determine if stdarg or varargs is used and return the address of
5205 the first unnamed parameter. */
5208 sparc_builtin_saveregs ()
5210 int first_reg
= current_function_args_info
.words
;
5214 for (regno
= first_reg
; regno
< NPARM_REGS (word_mode
); regno
++)
5215 emit_move_insn (gen_rtx_MEM (word_mode
,
5216 gen_rtx_PLUS (Pmode
,
5218 GEN_INT (FIRST_PARM_OFFSET (0)
5221 gen_rtx_REG (word_mode
,
5222 BASE_INCOMING_ARG_REG (word_mode
) + regno
));
5224 address
= gen_rtx_PLUS (Pmode
,
5226 GEN_INT (FIRST_PARM_OFFSET (0)
5227 + UNITS_PER_WORD
* first_reg
));
5232 /* Implement `va_start' for varargs and stdarg. */
5235 sparc_va_start (stdarg_p
, valist
, nextarg
)
5236 int stdarg_p ATTRIBUTE_UNUSED
;
5240 nextarg
= expand_builtin_saveregs ();
5241 std_expand_builtin_va_start (1, valist
, nextarg
);
5244 /* Implement `va_arg'. */
5247 sparc_va_arg (valist
, type
)
5250 HOST_WIDE_INT size
, rsize
, align
;
5255 /* Round up sizeof(type) to a word. */
5256 size
= int_size_in_bytes (type
);
5257 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
5262 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
5263 align
= 2 * UNITS_PER_WORD
;
5265 if (AGGREGATE_TYPE_P (type
))
5267 if ((unsigned HOST_WIDE_INT
) size
> 16)
5270 size
= rsize
= UNITS_PER_WORD
;
5272 /* SPARC v9 ABI states that structures up to 8 bytes in size are
5273 given one 8 byte slot. */
5275 size
= rsize
= UNITS_PER_WORD
;
5282 if (AGGREGATE_TYPE_P (type
)
5283 || TYPE_MODE (type
) == TFmode
5284 || TYPE_MODE (type
) == TCmode
)
5287 size
= rsize
= UNITS_PER_WORD
;
5294 incr
= fold (build (PLUS_EXPR
, ptr_type_node
, incr
,
5295 build_int_2 (align
- 1, 0)));
5296 incr
= fold (build (BIT_AND_EXPR
, ptr_type_node
, incr
,
5297 build_int_2 (-align
, -1)));
5300 addr
= incr
= save_expr (incr
);
5301 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
5303 addr
= fold (build (PLUS_EXPR
, ptr_type_node
, incr
,
5304 build_int_2 (rsize
- size
, 0)));
5306 incr
= fold (build (PLUS_EXPR
, ptr_type_node
, incr
,
5307 build_int_2 (rsize
, 0)));
5309 incr
= build (MODIFY_EXPR
, ptr_type_node
, valist
, incr
);
5310 TREE_SIDE_EFFECTS (incr
) = 1;
5311 expand_expr (incr
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5313 addr_rtx
= expand_expr (addr
, NULL
, Pmode
, EXPAND_NORMAL
);
5315 /* If the address isn't aligned properly for the type,
5316 we may need to copy to a temporary.
5317 FIXME: This is inefficient. Usually we can do this
5320 && TYPE_ALIGN (type
) > BITS_PER_WORD
5323 /* FIXME: We really need to specify that the temporary is live
5324 for the whole function because expand_builtin_va_arg wants
5325 the alias set to be get_varargs_alias_set (), but in this
5326 case the alias set is that for TYPE and if the memory gets
5327 reused it will be reused with alias set TYPE. */
5328 rtx tmp
= assign_temp (type
, 0, 1, 0);
5331 addr_rtx
= force_reg (Pmode
, addr_rtx
);
5332 addr_rtx
= gen_rtx_MEM (BLKmode
, addr_rtx
);
5333 set_mem_alias_set (addr_rtx
, get_varargs_alias_set ());
5334 set_mem_align (addr_rtx
, BITS_PER_WORD
);
5335 tmp
= shallow_copy_rtx (tmp
);
5336 PUT_MODE (tmp
, BLKmode
);
5337 set_mem_alias_set (tmp
, 0);
5339 dest_addr
= emit_block_move (tmp
, addr_rtx
, GEN_INT (rsize
));
5340 if (dest_addr
!= NULL_RTX
)
5341 addr_rtx
= dest_addr
;
5343 addr_rtx
= XCEXP (tmp
, 0, MEM
);
5348 addr_rtx
= force_reg (Pmode
, addr_rtx
);
5349 addr_rtx
= gen_rtx_MEM (Pmode
, addr_rtx
);
5350 set_mem_alias_set (addr_rtx
, get_varargs_alias_set ());
5356 /* Return the string to output a conditional branch to LABEL, which is
5357 the operand number of the label. OP is the conditional expression.
5358 XEXP (OP, 0) is assumed to be a condition code register (integer or
5359 floating point) and its mode specifies what kind of comparison we made.
5361 REVERSED is non-zero if we should reverse the sense of the comparison.
5363 ANNUL is non-zero if we should generate an annulling branch.
5365 NOOP is non-zero if we have to follow this branch by a noop.
5367 INSN, if set, is the insn. */
5370 output_cbranch (op
, dest
, label
, reversed
, annul
, noop
, insn
)
5373 int reversed
, annul
, noop
;
5376 static char string
[50];
5377 enum rtx_code code
= GET_CODE (op
);
5378 rtx cc_reg
= XEXP (op
, 0);
5379 enum machine_mode mode
= GET_MODE (cc_reg
);
5380 const char *labelno
, *branch
;
5381 int spaces
= 8, far
;
5384 /* v9 branches are limited to +-1MB. If it is too far away,
5397 fbne,a,pn %fcc2, .LC29
5405 far
= get_attr_length (insn
) >= 3;
5408 /* Reversal of FP compares takes care -- an ordered compare
5409 becomes an unordered compare and vice versa. */
5410 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
5411 code
= reverse_condition_maybe_unordered (code
);
5413 code
= reverse_condition (code
);
5416 /* Start by writing the branch condition. */
5417 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
5468 /* ??? !v9: FP branches cannot be preceded by another floating point
5469 insn. Because there is currently no concept of pre-delay slots,
5470 we can fix this only by always emitting a nop before a floating
5475 strcpy (string
, "nop\n\t");
5476 strcat (string
, branch
);
5489 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
5501 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
5522 strcpy (string
, branch
);
5524 spaces
-= strlen (branch
);
5525 p
= strchr (string
, '\0');
5527 /* Now add the annulling, the label, and a possible noop. */
5542 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
5544 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
5545 - INSN_ADDRESSES (INSN_UID (insn
)));
5546 /* Leave some instructions for "slop". */
5547 if (delta
< -260000 || delta
>= 260000)
5551 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
5553 static char v9_fcc_labelno
[] = "%%fccX, ";
5554 /* Set the char indicating the number of the fcc reg to use. */
5555 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
5556 labelno
= v9_fcc_labelno
;
5559 if (REGNO (cc_reg
) == SPARC_FCC_REG
)
5565 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
5567 labelno
= "%%xcc, ";
5573 labelno
= "%%icc, ";
5578 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
5581 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
5591 strcpy (p
, labelno
);
5592 p
= strchr (p
, '\0');
5595 strcpy (p
, ".+12\n\tnop\n\tb\t");
5602 /* Set the char indicating the number of the operand containing the
5607 strcpy (p
, "\n\tnop");
5612 /* Emit a library call comparison between floating point X and Y.
5613 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
5614 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
5615 values as arguments instead of the TFmode registers themselves,
5616 that's why we cannot call emit_float_lib_cmp. */
5618 sparc_emit_float_lib_cmp (x
, y
, comparison
)
5620 enum rtx_code comparison
;
5623 rtx slot0
, slot1
, result
, tem
, tem2
;
5624 enum machine_mode mode
;
5629 qpfunc
= (TARGET_ARCH64
) ? "_Qp_feq" : "_Q_feq";
5633 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fne" : "_Q_fne";
5637 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fgt" : "_Q_fgt";
5641 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fge" : "_Q_fge";
5645 qpfunc
= (TARGET_ARCH64
) ? "_Qp_flt" : "_Q_flt";
5649 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fle" : "_Q_fle";
5660 qpfunc
= (TARGET_ARCH64
) ? "_Qp_cmp" : "_Q_cmp";
5670 if (GET_CODE (x
) != MEM
)
5672 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
5673 emit_insn (gen_rtx_SET (VOIDmode
, slot0
, x
));
5678 if (GET_CODE (y
) != MEM
)
5680 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
5681 emit_insn (gen_rtx_SET (VOIDmode
, slot1
, y
));
5686 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, qpfunc
), LCT_NORMAL
,
5688 XEXP (slot0
, 0), Pmode
,
5689 XEXP (slot1
, 0), Pmode
);
5695 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, qpfunc
), LCT_NORMAL
,
5697 x
, TFmode
, y
, TFmode
);
5703 /* Immediately move the result of the libcall into a pseudo
5704 register so reload doesn't clobber the value if it needs
5705 the return register for a spill reg. */
5706 result
= gen_reg_rtx (mode
);
5707 emit_move_insn (result
, hard_libcall_value (mode
));
5712 emit_cmp_insn (result
, const0_rtx
, NE
, NULL_RTX
, mode
, 0);
5716 emit_cmp_insn (result
, GEN_INT(3), comparison
== UNORDERED
? EQ
: NE
,
5721 emit_cmp_insn (result
, const1_rtx
,
5722 comparison
== UNGT
? GT
: NE
, NULL_RTX
, mode
, 0);
5725 emit_cmp_insn (result
, const2_rtx
, NE
, NULL_RTX
, mode
, 0);
5728 tem
= gen_reg_rtx (mode
);
5730 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
5732 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
5733 emit_cmp_insn (tem
, const0_rtx
, NE
, NULL_RTX
, mode
, 0);
5737 tem
= gen_reg_rtx (mode
);
5739 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
5741 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
5742 tem2
= gen_reg_rtx (mode
);
5744 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
5746 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
5747 emit_cmp_insn (tem2
, const0_rtx
, comparison
== UNEQ
? EQ
: NE
,
5753 /* Generate an unsigned DImode to FP conversion. This is the same code
5754 optabs would emit if we didn't have TFmode patterns. */
5757 sparc_emit_floatunsdi (operands
)
5760 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
5761 enum machine_mode mode
;
5764 in
= force_reg (DImode
, operands
[1]);
5765 mode
= GET_MODE (out
);
5766 neglab
= gen_label_rtx ();
5767 donelab
= gen_label_rtx ();
5768 i0
= gen_reg_rtx (DImode
);
5769 i1
= gen_reg_rtx (DImode
);
5770 f0
= gen_reg_rtx (mode
);
5772 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
5774 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
5775 emit_jump_insn (gen_jump (donelab
));
5778 emit_label (neglab
);
5780 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
5781 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
5782 emit_insn (gen_iordi3 (i0
, i0
, i1
));
5783 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
5784 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
5786 emit_label (donelab
);
5789 /* Return the string to output a conditional branch to LABEL, testing
5790 register REG. LABEL is the operand number of the label; REG is the
5791 operand number of the reg. OP is the conditional expression. The mode
5792 of REG says what kind of comparison we made.
5794 REVERSED is non-zero if we should reverse the sense of the comparison.
5796 ANNUL is non-zero if we should generate an annulling branch.
5798 NOOP is non-zero if we have to follow this branch by a noop. */
5801 output_v9branch (op
, dest
, reg
, label
, reversed
, annul
, noop
, insn
)
5804 int reversed
, annul
, noop
;
5807 static char string
[50];
5808 enum rtx_code code
= GET_CODE (op
);
5809 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
5814 /* branch on register are limited to +-128KB. If it is too far away,
5827 brgez,a,pn %o1, .LC29
5833 ba,pt %xcc, .LC29 */
5835 far
= get_attr_length (insn
) >= 3;
5837 /* If not floating-point or if EQ or NE, we can just reverse the code. */
5839 code
= reverse_condition (code
);
5841 /* Only 64 bit versions of these instructions exist. */
5845 /* Start by writing the branch condition. */
5850 strcpy (string
, "brnz");
5854 strcpy (string
, "brz");
5858 strcpy (string
, "brgez");
5862 strcpy (string
, "brlz");
5866 strcpy (string
, "brlez");
5870 strcpy (string
, "brgz");
5877 p
= strchr (string
, '\0');
5879 /* Now add the annulling, reg, label, and nop. */
5886 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
5889 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
5894 *p
= p
< string
+ 8 ? '\t' : ' ';
5902 int veryfar
= 1, delta
;
5904 if (INSN_ADDRESSES_SET_P ())
5906 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
5907 - INSN_ADDRESSES (INSN_UID (insn
)));
5908 /* Leave some instructions for "slop". */
5909 if (delta
>= -260000 && delta
< 260000)
5913 strcpy (p
, ".+12\n\tnop\n\t");
5924 strcpy (p
, "ba,pt\t%%xcc, ");
5934 strcpy (p
, "\n\tnop");
5939 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
5940 Such instructions cannot be used in the delay slot of return insn on v9.
5941 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
5945 epilogue_renumber (where
, test
)
5946 register rtx
*where
;
5949 register const char *fmt
;
5951 register enum rtx_code code
;
5956 code
= GET_CODE (*where
);
5961 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
5963 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
5964 *where
= gen_rtx (REG
, GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
5972 /* Do not replace the frame pointer with the stack pointer because
5973 it can cause the delayed instruction to load below the stack.
5974 This occurs when instructions like:
5976 (set (reg/i:SI 24 %i0)
5977 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
5978 (const_int -20 [0xffffffec])) 0))
5980 are in the return delayed slot. */
5982 if (GET_CODE (XEXP (*where
, 0)) == REG
5983 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
5984 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
5985 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
5990 if (SPARC_STACK_BIAS
5991 && GET_CODE (XEXP (*where
, 0)) == REG
5992 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
6000 fmt
= GET_RTX_FORMAT (code
);
6002 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6007 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
6008 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
6011 else if (fmt
[i
] == 'e'
6012 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
6018 /* Leaf functions and non-leaf functions have different needs. */
6021 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
6024 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
6026 static const int *const reg_alloc_orders
[] = {
6027 reg_leaf_alloc_order
,
6028 reg_nonleaf_alloc_order
};
6031 order_regs_for_local_alloc ()
6033 static int last_order_nonleaf
= 1;
6035 if (regs_ever_live
[15] != last_order_nonleaf
)
6037 last_order_nonleaf
= !last_order_nonleaf
;
6038 memcpy ((char *) reg_alloc_order
,
6039 (const char *) reg_alloc_orders
[last_order_nonleaf
],
6040 FIRST_PSEUDO_REGISTER
* sizeof (int));
6044 /* Return 1 if REG and MEM are legitimate enough to allow the various
6045 mem<-->reg splits to be run. */
6048 sparc_splitdi_legitimate (reg
, mem
)
6052 /* Punt if we are here by mistake. */
6053 if (! reload_completed
)
6056 /* We must have an offsettable memory reference. */
6057 if (! offsettable_memref_p (mem
))
6060 /* If we have legitimate args for ldd/std, we do not want
6061 the split to happen. */
6062 if ((REGNO (reg
) % 2) == 0
6063 && mem_min_alignment (mem
, 8))
6070 /* Return 1 if x and y are some kind of REG and they refer to
6071 different hard registers. This test is guarenteed to be
6072 run after reload. */
6075 sparc_absnegfloat_split_legitimate (x
, y
)
6078 if (GET_CODE (x
) != REG
)
6080 if (GET_CODE (y
) != REG
)
6082 if (REGNO (x
) == REGNO (y
))
6087 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6088 This makes them candidates for using ldd and std insns.
6090 Note reg1 and reg2 *must* be hard registers. */
6093 registers_ok_for_ldd_peep (reg1
, reg2
)
6096 /* We might have been passed a SUBREG. */
6097 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
6100 if (REGNO (reg1
) % 2 != 0)
6103 /* Integer ldd is deprecated in SPARC V9 */
6104 if (TARGET_V9
&& REGNO (reg1
) < 32)
6107 return (REGNO (reg1
) == REGNO (reg2
) - 1);
6110 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6113 This can only happen when addr1 and addr2, the addresses in mem1
6114 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6115 addr1 must also be aligned on a 64-bit boundary.
6117 Also iff dependent_reg_rtx is not null it should not be used to
6118 compute the address for mem1, i.e. we cannot optimize a sequence
6130 But, note that the transformation from:
6135 is perfectly fine. Thus, the peephole2 patterns always pass us
6136 the destination register of the first load, never the second one.
6138 For stores we don't have a similar problem, so dependent_reg_rtx is
6142 mems_ok_for_ldd_peep (mem1
, mem2
, dependent_reg_rtx
)
6143 rtx mem1
, mem2
, dependent_reg_rtx
;
6149 /* The mems cannot be volatile. */
6150 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
6153 /* MEM1 should be aligned on a 64-bit boundary. */
6154 if (MEM_ALIGN (mem1
) < 64)
6157 addr1
= XEXP (mem1
, 0);
6158 addr2
= XEXP (mem2
, 0);
6160 /* Extract a register number and offset (if used) from the first addr. */
6161 if (GET_CODE (addr1
) == PLUS
)
6163 /* If not a REG, return zero. */
6164 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
6168 reg1
= REGNO (XEXP (addr1
, 0));
6169 /* The offset must be constant! */
6170 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
6172 offset1
= INTVAL (XEXP (addr1
, 1));
6175 else if (GET_CODE (addr1
) != REG
)
6179 reg1
= REGNO (addr1
);
6180 /* This was a simple (mem (reg)) expression. Offset is 0. */
6184 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6185 if (GET_CODE (addr2
) != PLUS
)
6188 if (GET_CODE (XEXP (addr2
, 0)) != REG
6189 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
6192 if (reg1
!= REGNO (XEXP (addr2
, 0)))
6195 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
6198 /* The first offset must be evenly divisible by 8 to ensure the
6199 address is 64 bit aligned. */
6200 if (offset1
% 8 != 0)
6203 /* The offset for the second addr must be 4 more than the first addr. */
6204 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
6207 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6212 /* Return 1 if reg is a pseudo, or is the first register in
6213 a hard register pair. This makes it a candidate for use in
6214 ldd and std insns. */
6217 register_ok_for_ldd (reg
)
6220 /* We might have been passed a SUBREG. */
6221 if (GET_CODE (reg
) != REG
)
6224 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
6225 return (REGNO (reg
) % 2 == 0);
6230 /* Print operand X (an rtx) in assembler syntax to file FILE.
6231 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6232 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6235 print_operand (file
, x
, code
)
6243 /* Output a 'nop' if there's nothing for the delay slot. */
6244 if (dbr_sequence_length () == 0)
6245 fputs ("\n\t nop", file
);
6248 /* Output an annul flag if there's nothing for the delay slot and we
6249 are optimizing. This is always used with '(' below. */
6250 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6251 this is a dbx bug. So, we only do this when optimizing. */
6252 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6253 Always emit a nop in case the next instruction is a branch. */
6254 if (dbr_sequence_length () == 0
6255 && (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
6259 /* Output a 'nop' if there's nothing for the delay slot and we are
6260 not optimizing. This is always used with '*' above. */
6261 if (dbr_sequence_length () == 0
6262 && ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
6263 fputs ("\n\t nop", file
);
6266 /* Output the Embedded Medium/Anywhere code model base register. */
6267 fputs (EMBMEDANY_BASE_REG
, file
);
6270 /* Print out what we are using as the frame pointer. This might
6271 be %fp, or might be %sp+offset. */
6272 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6273 fprintf (file
, "%s+%d", frame_base_name
, frame_base_offset
);
6276 /* Adjust the operand to take into account a RESTORE operation. */
6277 if (GET_CODE (x
) == CONST_INT
)
6279 else if (GET_CODE (x
) != REG
)
6280 output_operand_lossage ("invalid %%Y operand");
6281 else if (REGNO (x
) < 8)
6282 fputs (reg_names
[REGNO (x
)], file
);
6283 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
6284 fputs (reg_names
[REGNO (x
)-16], file
);
6286 output_operand_lossage ("invalid %%Y operand");
6289 /* Print out the low order register name of a register pair. */
6290 if (WORDS_BIG_ENDIAN
)
6291 fputs (reg_names
[REGNO (x
)+1], file
);
6293 fputs (reg_names
[REGNO (x
)], file
);
6296 /* Print out the high order register name of a register pair. */
6297 if (WORDS_BIG_ENDIAN
)
6298 fputs (reg_names
[REGNO (x
)], file
);
6300 fputs (reg_names
[REGNO (x
)+1], file
);
6303 /* Print out the second register name of a register pair or quad.
6304 I.e., R (%o0) => %o1. */
6305 fputs (reg_names
[REGNO (x
)+1], file
);
6308 /* Print out the third register name of a register quad.
6309 I.e., S (%o0) => %o2. */
6310 fputs (reg_names
[REGNO (x
)+2], file
);
6313 /* Print out the fourth register name of a register quad.
6314 I.e., T (%o0) => %o3. */
6315 fputs (reg_names
[REGNO (x
)+3], file
);
6318 /* Print a condition code register. */
6319 if (REGNO (x
) == SPARC_ICC_REG
)
6321 /* We don't handle CC[X]_NOOVmode because they're not supposed
6323 if (GET_MODE (x
) == CCmode
)
6324 fputs ("%icc", file
);
6325 else if (GET_MODE (x
) == CCXmode
)
6326 fputs ("%xcc", file
);
6331 /* %fccN register */
6332 fputs (reg_names
[REGNO (x
)], file
);
6335 /* Print the operand's address only. */
6336 output_address (XEXP (x
, 0));
6339 /* In this case we need a register. Use %g0 if the
6340 operand is const0_rtx. */
6342 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
6344 fputs ("%g0", file
);
6351 switch (GET_CODE (x
))
6353 case IOR
: fputs ("or", file
); break;
6354 case AND
: fputs ("and", file
); break;
6355 case XOR
: fputs ("xor", file
); break;
6356 default: output_operand_lossage ("invalid %%A operand");
6361 switch (GET_CODE (x
))
6363 case IOR
: fputs ("orn", file
); break;
6364 case AND
: fputs ("andn", file
); break;
6365 case XOR
: fputs ("xnor", file
); break;
6366 default: output_operand_lossage ("invalid %%B operand");
6370 /* These are used by the conditional move instructions. */
6374 enum rtx_code rc
= GET_CODE (x
);
6378 enum machine_mode mode
= GET_MODE (XEXP (x
, 0));
6379 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6380 rc
= reverse_condition_maybe_unordered (GET_CODE (x
));
6382 rc
= reverse_condition (GET_CODE (x
));
6386 case NE
: fputs ("ne", file
); break;
6387 case EQ
: fputs ("e", file
); break;
6388 case GE
: fputs ("ge", file
); break;
6389 case GT
: fputs ("g", file
); break;
6390 case LE
: fputs ("le", file
); break;
6391 case LT
: fputs ("l", file
); break;
6392 case GEU
: fputs ("geu", file
); break;
6393 case GTU
: fputs ("gu", file
); break;
6394 case LEU
: fputs ("leu", file
); break;
6395 case LTU
: fputs ("lu", file
); break;
6396 case LTGT
: fputs ("lg", file
); break;
6397 case UNORDERED
: fputs ("u", file
); break;
6398 case ORDERED
: fputs ("o", file
); break;
6399 case UNLT
: fputs ("ul", file
); break;
6400 case UNLE
: fputs ("ule", file
); break;
6401 case UNGT
: fputs ("ug", file
); break;
6402 case UNGE
: fputs ("uge", file
); break;
6403 case UNEQ
: fputs ("ue", file
); break;
6404 default: output_operand_lossage (code
== 'c'
6405 ? "invalid %%c operand"
6406 : "invalid %%C operand");
6411 /* These are used by the movr instruction pattern. */
6415 enum rtx_code rc
= (code
== 'd'
6416 ? reverse_condition (GET_CODE (x
))
6420 case NE
: fputs ("ne", file
); break;
6421 case EQ
: fputs ("e", file
); break;
6422 case GE
: fputs ("gez", file
); break;
6423 case LT
: fputs ("lz", file
); break;
6424 case LE
: fputs ("lez", file
); break;
6425 case GT
: fputs ("gz", file
); break;
6426 default: output_operand_lossage (code
== 'd'
6427 ? "invalid %%d operand"
6428 : "invalid %%D operand");
6435 /* Print a sign-extended character. */
6436 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
6437 fprintf (file
, "%d", i
);
6442 /* Operand must be a MEM; write its address. */
6443 if (GET_CODE (x
) != MEM
)
6444 output_operand_lossage ("invalid %%f operand");
6445 output_address (XEXP (x
, 0));
6449 /* Do nothing special. */
6453 /* Undocumented flag. */
6454 output_operand_lossage ("invalid operand output code");
6457 if (GET_CODE (x
) == REG
)
6458 fputs (reg_names
[REGNO (x
)], file
);
6459 else if (GET_CODE (x
) == MEM
)
6462 /* Poor Sun assembler doesn't understand absolute addressing. */
6463 if (CONSTANT_P (XEXP (x
, 0)))
6464 fputs ("%g0+", file
);
6465 output_address (XEXP (x
, 0));
6468 else if (GET_CODE (x
) == HIGH
)
6470 fputs ("%hi(", file
);
6471 output_addr_const (file
, XEXP (x
, 0));
6474 else if (GET_CODE (x
) == LO_SUM
)
6476 print_operand (file
, XEXP (x
, 0), 0);
6477 if (TARGET_CM_MEDMID
)
6478 fputs ("+%l44(", file
);
6480 fputs ("+%lo(", file
);
6481 output_addr_const (file
, XEXP (x
, 1));
6484 else if (GET_CODE (x
) == CONST_DOUBLE
6485 && (GET_MODE (x
) == VOIDmode
6486 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
6488 if (CONST_DOUBLE_HIGH (x
) == 0)
6489 fprintf (file
, "%u", (unsigned int) CONST_DOUBLE_LOW (x
));
6490 else if (CONST_DOUBLE_HIGH (x
) == -1
6491 && CONST_DOUBLE_LOW (x
) < 0)
6492 fprintf (file
, "%d", (int) CONST_DOUBLE_LOW (x
));
6494 output_operand_lossage ("long long constant not a valid immediate operand");
6496 else if (GET_CODE (x
) == CONST_DOUBLE
)
6497 output_operand_lossage ("floating point constant not a valid immediate operand");
6498 else { output_addr_const (file
, x
); }
6501 /* Target hook for assembling integer objects. The sparc version has
6502 special handling for aligned DI-mode objects. */
6505 sparc_assemble_integer (x
, size
, aligned_p
)
6510 /* ??? We only output .xword's for symbols and only then in environments
6511 where the assembler can handle them. */
6512 if (aligned_p
&& size
== 8
6513 && (GET_CODE (x
) != CONST_INT
&& GET_CODE (x
) != CONST_DOUBLE
))
6517 assemble_integer_with_op ("\t.xword\t", x
);
6522 assemble_aligned_integer (4, const0_rtx
);
6523 assemble_aligned_integer (4, x
);
6527 return default_assemble_integer (x
, size
, aligned_p
);
6530 /* Return the value of a code used in the .proc pseudo-op that says
6531 what kind of result this function returns. For non-C types, we pick
6532 the closest C type. */
6534 #ifndef SHORT_TYPE_SIZE
6535 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
6538 #ifndef INT_TYPE_SIZE
6539 #define INT_TYPE_SIZE BITS_PER_WORD
6542 #ifndef LONG_TYPE_SIZE
6543 #define LONG_TYPE_SIZE BITS_PER_WORD
6546 #ifndef LONG_LONG_TYPE_SIZE
6547 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
6550 #ifndef FLOAT_TYPE_SIZE
6551 #define FLOAT_TYPE_SIZE BITS_PER_WORD
6554 #ifndef DOUBLE_TYPE_SIZE
6555 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6558 #ifndef LONG_DOUBLE_TYPE_SIZE
6559 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6563 sparc_type_code (type
)
6566 register unsigned long qualifiers
= 0;
6567 register unsigned shift
;
6569 /* Only the first 30 bits of the qualifier are valid. We must refrain from
6570 setting more, since some assemblers will give an error for this. Also,
6571 we must be careful to avoid shifts of 32 bits or more to avoid getting
6572 unpredictable results. */
6574 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
6576 switch (TREE_CODE (type
))
6582 qualifiers
|= (3 << shift
);
6587 qualifiers
|= (2 << shift
);
6591 case REFERENCE_TYPE
:
6593 qualifiers
|= (1 << shift
);
6597 return (qualifiers
| 8);
6600 case QUAL_UNION_TYPE
:
6601 return (qualifiers
| 9);
6604 return (qualifiers
| 10);
6607 return (qualifiers
| 16);
6610 /* If this is a range type, consider it to be the underlying
6612 if (TREE_TYPE (type
) != 0)
6615 /* Carefully distinguish all the standard types of C,
6616 without messing up if the language is not C. We do this by
6617 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
6618 look at both the names and the above fields, but that's redundant.
6619 Any type whose size is between two C types will be considered
6620 to be the wider of the two types. Also, we do not have a
6621 special code to use for "long long", so anything wider than
6622 long is treated the same. Note that we can't distinguish
6623 between "int" and "long" in this code if they are the same
6624 size, but that's fine, since neither can the assembler. */
6626 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
6627 return (qualifiers
| (TREE_UNSIGNED (type
) ? 12 : 2));
6629 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
6630 return (qualifiers
| (TREE_UNSIGNED (type
) ? 13 : 3));
6632 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
6633 return (qualifiers
| (TREE_UNSIGNED (type
) ? 14 : 4));
6636 return (qualifiers
| (TREE_UNSIGNED (type
) ? 15 : 5));
6639 /* If this is a range type, consider it to be the underlying
6641 if (TREE_TYPE (type
) != 0)
6644 /* Carefully distinguish all the standard types of C,
6645 without messing up if the language is not C. */
6647 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
6648 return (qualifiers
| 6);
6651 return (qualifiers
| 7);
6653 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
6654 /* ??? We need to distinguish between double and float complex types,
6655 but I don't know how yet because I can't reach this code from
6656 existing front-ends. */
6657 return (qualifiers
| 7); /* Who knows? */
6659 case CHAR_TYPE
: /* GNU Pascal CHAR type. Not used in C. */
6660 case BOOLEAN_TYPE
: /* GNU Fortran BOOLEAN type. */
6661 case FILE_TYPE
: /* GNU Pascal FILE type. */
6662 case SET_TYPE
: /* GNU Pascal SET type. */
6663 case LANG_TYPE
: /* ? */
6667 abort (); /* Not a type! */
6674 /* Nested function support. */
6676 /* Emit RTL insns to initialize the variable parts of a trampoline.
6677 FNADDR is an RTX for the address of the function's pure code.
6678 CXT is an RTX for the static chain value for the function.
6680 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
6681 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
6682 (to store insns). This is a bit excessive. Perhaps a different
6683 mechanism would be better here.
6685 Emit enough FLUSH insns to synchronize the data and instruction caches. */
6688 sparc_initialize_trampoline (tramp
, fnaddr
, cxt
)
6689 rtx tramp
, fnaddr
, cxt
;
6691 /* SPARC 32 bit trampoline:
6694 sethi %hi(static), %g2
6696 or %g2, %lo(static), %g2
6698 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
6699 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
6701 #ifdef TRANSFER_FROM_TRAMPOLINE
6702 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "__enable_execute_stack"),
6703 LCT_NORMAL
, VOIDmode
, 1, tramp
, Pmode
);
6707 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 0)),
6708 expand_binop (SImode
, ior_optab
,
6709 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
,
6710 size_int (10), 0, 1),
6711 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
6712 NULL_RTX
, 1, OPTAB_DIRECT
));
6715 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
6716 expand_binop (SImode
, ior_optab
,
6717 expand_shift (RSHIFT_EXPR
, SImode
, cxt
,
6718 size_int (10), 0, 1),
6719 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
6720 NULL_RTX
, 1, OPTAB_DIRECT
));
6723 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
6724 expand_binop (SImode
, ior_optab
,
6725 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
6726 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
6727 NULL_RTX
, 1, OPTAB_DIRECT
));
6730 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
6731 expand_binop (SImode
, ior_optab
,
6732 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
6733 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
6734 NULL_RTX
, 1, OPTAB_DIRECT
));
6736 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
6737 aligned on a 16 byte boundary so one flush clears it all. */
6738 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode
, tramp
))));
6739 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
6740 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
)
6741 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode
,
6742 plus_constant (tramp
, 8)))));
6745 /* The 64 bit version is simpler because it makes more sense to load the
6746 values as "immediate" data out of the trampoline. It's also easier since
6747 we can read the PC without clobbering a register. */
6750 sparc64_initialize_trampoline (tramp
, fnaddr
, cxt
)
6751 rtx tramp
, fnaddr
, cxt
;
6753 #ifdef TRANSFER_FROM_TRAMPOLINE
6754 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "__enable_execute_stack"),
6755 LCT_NORMAL
, VOIDmode
, 1, tramp
, Pmode
);
6766 emit_move_insn (gen_rtx_MEM (SImode
, tramp
),
6767 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
6768 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
6769 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
6770 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
6771 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
6772 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
6773 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
6774 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 16)), cxt
);
6775 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 24)), fnaddr
);
6776 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode
, tramp
))));
6778 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
6779 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
)
6780 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode
, plus_constant (tramp
, 8)))));
6783 /* Subroutines to support a flat (single) register window calling
6786 /* Single-register window sparc stack frames look like:
6788 Before call After call
6789 +-----------------------+ +-----------------------+
6791 mem | caller's temps. | | caller's temps. |
6793 +-----------------------+ +-----------------------+
6795 | arguments on stack. | | arguments on stack. |
6797 +-----------------------+FP+92->+-----------------------+
6798 | 6 words to save | | 6 words to save |
6799 | arguments passed | | arguments passed |
6800 | in registers, even | | in registers, even |
6801 | if not passed. | | if not passed. |
6802 SP+68->+-----------------------+FP+68->+-----------------------+
6803 | 1 word struct addr | | 1 word struct addr |
6804 +-----------------------+FP+64->+-----------------------+
6806 | 16 word reg save area | | 16 word reg save area |
6808 SP->+-----------------------+ FP->+-----------------------+
6810 | fp/alu reg moves |
6811 FP-16->+-----------------------+
6815 +-----------------------+
6817 | fp register save |
6819 +-----------------------+
6821 | gp register save |
6823 +-----------------------+
6825 | alloca allocations |
6827 +-----------------------+
6829 | arguments on stack |
6831 SP+92->+-----------------------+
6833 | arguments passed |
6834 | in registers, even |
6835 low | if not passed. |
6836 memory SP+68->+-----------------------+
6837 | 1 word struct addr |
6838 SP+64->+-----------------------+
6840 I 16 word reg save area |
6842 SP->+-----------------------+ */
6844 /* Structure to be filled in by sparc_flat_compute_frame_size with register
6845 save masks, and offsets for the current function. */
6847 struct sparc_frame_info
6849 unsigned long total_size
; /* # bytes that the entire frame takes up. */
6850 unsigned long var_size
; /* # bytes that variables take up. */
6851 unsigned long args_size
; /* # bytes that outgoing arguments take up. */
6852 unsigned long extra_size
; /* # bytes of extra gunk. */
6853 unsigned int gp_reg_size
; /* # bytes needed to store gp regs. */
6854 unsigned int fp_reg_size
; /* # bytes needed to store fp regs. */
6855 unsigned long gmask
; /* Mask of saved gp registers. */
6856 unsigned long fmask
; /* Mask of saved fp registers. */
6857 unsigned long reg_offset
; /* Offset from new sp to store regs. */
6858 int initialized
; /* Nonzero if frame size already calculated. */
6861 /* Current frame information calculated by sparc_flat_compute_frame_size. */
6862 struct sparc_frame_info current_frame_info
;
6864 /* Zero structure to initialize current_frame_info. */
6865 struct sparc_frame_info zero_frame_info
;
6867 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
6869 #define RETURN_ADDR_REGNUM 15
6870 #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM))
6871 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
6873 #define MUST_SAVE_REGISTER(regno) \
6874 ((regs_ever_live[regno] && !call_used_regs[regno]) \
6875 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
6876 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
6878 /* Return the bytes needed to compute the frame pointer from the current
6882 sparc_flat_compute_frame_size (size
)
6883 int size
; /* # of var. bytes allocated. */
6886 unsigned long total_size
; /* # bytes that the entire frame takes up. */
6887 unsigned long var_size
; /* # bytes that variables take up. */
6888 unsigned long args_size
; /* # bytes that outgoing arguments take up. */
6889 unsigned long extra_size
; /* # extra bytes. */
6890 unsigned int gp_reg_size
; /* # bytes needed to store gp regs. */
6891 unsigned int fp_reg_size
; /* # bytes needed to store fp regs. */
6892 unsigned long gmask
; /* Mask of saved gp registers. */
6893 unsigned long fmask
; /* Mask of saved fp registers. */
6894 unsigned long reg_offset
; /* Offset to register save area. */
6895 int need_aligned_p
; /* 1 if need the save area 8 byte aligned. */
6897 /* This is the size of the 16 word reg save area, 1 word struct addr
6898 area, and 4 word fp/alu register copy area. */
6899 extra_size
= -STARTING_FRAME_OFFSET
+ FIRST_PARM_OFFSET(0);
6909 if (!leaf_function_p ())
6911 /* Also include the size needed for the 6 parameter registers. */
6912 args_size
= current_function_outgoing_args_size
+ 24;
6914 total_size
= var_size
+ args_size
;
6916 /* Calculate space needed for gp registers. */
6917 for (regno
= 1; regno
<= 31; regno
++)
6919 if (MUST_SAVE_REGISTER (regno
))
6921 /* If we need to save two regs in a row, ensure there's room to bump
6922 up the address to align it to a doubleword boundary. */
6923 if ((regno
& 0x1) == 0 && MUST_SAVE_REGISTER (regno
+1))
6925 if (gp_reg_size
% 8 != 0)
6927 gp_reg_size
+= 2 * UNITS_PER_WORD
;
6928 gmask
|= 3 << regno
;
6934 gp_reg_size
+= UNITS_PER_WORD
;
6935 gmask
|= 1 << regno
;
6940 /* Calculate space needed for fp registers. */
6941 for (regno
= 32; regno
<= 63; regno
++)
6943 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
6945 fp_reg_size
+= UNITS_PER_WORD
;
6946 fmask
|= 1 << (regno
- 32);
6953 reg_offset
= FIRST_PARM_OFFSET(0) + args_size
;
6954 /* Ensure save area is 8 byte aligned if we need it. */
6956 if (need_aligned_p
&& n
!= 0)
6958 total_size
+= 8 - n
;
6959 reg_offset
+= 8 - n
;
6961 total_size
+= gp_reg_size
+ fp_reg_size
;
6964 /* If we must allocate a stack frame at all, we must also allocate
6965 room for register window spillage, so as to be binary compatible
6966 with libraries and operating systems that do not use -mflat. */
6968 total_size
+= extra_size
;
6972 total_size
= SPARC_STACK_ALIGN (total_size
);
6974 /* Save other computed information. */
6975 current_frame_info
.total_size
= total_size
;
6976 current_frame_info
.var_size
= var_size
;
6977 current_frame_info
.args_size
= args_size
;
6978 current_frame_info
.extra_size
= extra_size
;
6979 current_frame_info
.gp_reg_size
= gp_reg_size
;
6980 current_frame_info
.fp_reg_size
= fp_reg_size
;
6981 current_frame_info
.gmask
= gmask
;
6982 current_frame_info
.fmask
= fmask
;
6983 current_frame_info
.reg_offset
= reg_offset
;
6984 current_frame_info
.initialized
= reload_completed
;
6986 /* Ok, we're done. */
6990 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
6993 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
6994 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
6995 [BASE_REG+OFFSET] will always be a valid address.
6997 WORD_OP is either "st" for save, "ld" for restore.
6998 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
7001 sparc_flat_save_restore (file
, base_reg
, offset
, gmask
, fmask
, word_op
,
7002 doubleword_op
, base_offset
)
7004 const char *base_reg
;
7005 unsigned int offset
;
7006 unsigned long gmask
;
7007 unsigned long fmask
;
7008 const char *word_op
;
7009 const char *doubleword_op
;
7010 unsigned long base_offset
;
7014 if (gmask
== 0 && fmask
== 0)
7017 /* Save registers starting from high to low. We've already saved the
7018 previous frame pointer and previous return address for the debugger's
7019 sake. The debugger allows us to not need a nop in the epilog if at least
7020 one register is reloaded in addition to return address. */
7024 for (regno
= 1; regno
<= 31; regno
++)
7026 if ((gmask
& (1L << regno
)) != 0)
7028 if ((regno
& 0x1) == 0 && ((gmask
& (1L << (regno
+1))) != 0))
7030 /* We can save two registers in a row. If we're not at a
7031 double word boundary, move to one.
7032 sparc_flat_compute_frame_size ensures there's room to do
7034 if (offset
% 8 != 0)
7035 offset
+= UNITS_PER_WORD
;
7037 if (word_op
[0] == 's')
7039 fprintf (file
, "\t%s\t%s, [%s+%d]\n",
7040 doubleword_op
, reg_names
[regno
],
7042 if (dwarf2out_do_frame ())
7044 char *l
= dwarf2out_cfi_label ();
7045 dwarf2out_reg_save (l
, regno
, offset
+ base_offset
);
7047 (l
, regno
+1, offset
+base_offset
+ UNITS_PER_WORD
);
7051 fprintf (file
, "\t%s\t[%s+%d], %s\n",
7052 doubleword_op
, base_reg
, offset
,
7055 offset
+= 2 * UNITS_PER_WORD
;
7060 if (word_op
[0] == 's')
7062 fprintf (file
, "\t%s\t%s, [%s+%d]\n",
7063 word_op
, reg_names
[regno
],
7065 if (dwarf2out_do_frame ())
7066 dwarf2out_reg_save ("", regno
, offset
+ base_offset
);
7069 fprintf (file
, "\t%s\t[%s+%d], %s\n",
7070 word_op
, base_reg
, offset
, reg_names
[regno
]);
7072 offset
+= UNITS_PER_WORD
;
7080 for (regno
= 32; regno
<= 63; regno
++)
7082 if ((fmask
& (1L << (regno
- 32))) != 0)
7084 if (word_op
[0] == 's')
7086 fprintf (file
, "\t%s\t%s, [%s+%d]\n",
7087 word_op
, reg_names
[regno
],
7089 if (dwarf2out_do_frame ())
7090 dwarf2out_reg_save ("", regno
, offset
+ base_offset
);
7093 fprintf (file
, "\t%s\t[%s+%d], %s\n",
7094 word_op
, base_reg
, offset
, reg_names
[regno
]);
7096 offset
+= UNITS_PER_WORD
;
7102 /* Set up the stack and frame (if desired) for the function. */
7105 sparc_flat_function_prologue (file
, size
)
7109 const char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
7110 unsigned long gmask
= current_frame_info
.gmask
;
7112 sparc_output_scratch_registers (file
);
7114 /* This is only for the human reader. */
7115 fprintf (file
, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START
);
7116 fprintf (file
, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7118 current_frame_info
.var_size
,
7119 current_frame_info
.gp_reg_size
/ 4,
7120 current_frame_info
.fp_reg_size
/ 4,
7121 current_function_outgoing_args_size
,
7122 current_frame_info
.extra_size
);
7124 size
= SPARC_STACK_ALIGN (size
);
7125 size
= (! current_frame_info
.initialized
7126 ? sparc_flat_compute_frame_size (size
)
7127 : current_frame_info
.total_size
);
7129 /* These cases shouldn't happen. Catch them now. */
7130 if (size
== 0 && (gmask
|| current_frame_info
.fmask
))
7133 /* Allocate our stack frame by decrementing %sp.
7134 At present, the only algorithm gdb can use to determine if this is a
7135 flat frame is if we always set %i7 if we set %sp. This can be optimized
7136 in the future by putting in some sort of debugging information that says
7137 this is a `flat' function. However, there is still the case of debugging
7138 code without such debugging information (including cases where most fns
7139 have such info, but there is one that doesn't). So, always do this now
7140 so we don't get a lot of code out there that gdb can't handle.
7141 If the frame pointer isn't needn't then that's ok - gdb won't be able to
7142 distinguish us from a non-flat function but there won't (and shouldn't)
7143 be any differences anyway. The return pc is saved (if necessary) right
7144 after %i7 so gdb won't have to look too far to find it. */
7147 unsigned int reg_offset
= current_frame_info
.reg_offset
;
7148 const char *const fp_str
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
7149 static const char *const t1_str
= "%g1";
7151 /* Things get a little tricky if local variables take up more than ~4096
7152 bytes and outgoing arguments take up more than ~4096 bytes. When that
7153 happens, the register save area can't be accessed from either end of
7154 the frame. Handle this by decrementing %sp to the start of the gp
7155 register save area, save the regs, update %i7, and then set %sp to its
7156 final value. Given that we only have one scratch register to play
7157 with it is the cheapest solution, and it helps gdb out as it won't
7158 slow down recognition of flat functions.
7159 Don't change the order of insns emitted here without checking with
7160 the gdb folk first. */
7162 /* Is the entire register save area offsettable from %sp? */
7163 if (reg_offset
< 4096 - 64 * (unsigned) UNITS_PER_WORD
)
7167 fprintf (file
, "\tadd\t%s, %d, %s\n",
7168 sp_str
, (int) -size
, sp_str
);
7169 if (gmask
& HARD_FRAME_POINTER_MASK
)
7171 fprintf (file
, "\tst\t%s, [%s+%d]\n",
7172 fp_str
, sp_str
, reg_offset
);
7173 fprintf (file
, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7174 sp_str
, (int) -size
, fp_str
, ASM_COMMENT_START
);
7180 fprintf (file
, "\tset\t");
7181 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, size
);
7182 fprintf (file
, ", %s\n\tsub\t%s, %s, %s\n",
7183 t1_str
, sp_str
, t1_str
, sp_str
);
7184 if (gmask
& HARD_FRAME_POINTER_MASK
)
7186 fprintf (file
, "\tst\t%s, [%s+%d]\n",
7187 fp_str
, sp_str
, reg_offset
);
7188 fprintf (file
, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7189 sp_str
, t1_str
, fp_str
, ASM_COMMENT_START
);
7193 if (dwarf2out_do_frame ())
7195 char *l
= dwarf2out_cfi_label ();
7196 if (gmask
& HARD_FRAME_POINTER_MASK
)
7198 dwarf2out_reg_save (l
, HARD_FRAME_POINTER_REGNUM
,
7199 reg_offset
- 4 - size
);
7200 dwarf2out_def_cfa (l
, HARD_FRAME_POINTER_REGNUM
, 0);
7203 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, size
);
7205 if (gmask
& RETURN_ADDR_MASK
)
7207 fprintf (file
, "\tst\t%s, [%s+%d]\n",
7208 reg_names
[RETURN_ADDR_REGNUM
], sp_str
, reg_offset
);
7209 if (dwarf2out_do_frame ())
7210 dwarf2out_return_save ("", reg_offset
- size
);
7213 sparc_flat_save_restore (file
, sp_str
, reg_offset
,
7214 gmask
& ~(HARD_FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
7215 current_frame_info
.fmask
,
7216 "st", "std", -size
);
7220 /* Subtract %sp in two steps, but make sure there is always a
7221 64 byte register save area, and %sp is properly aligned. */
7222 /* Amount to decrement %sp by, the first time. */
7223 unsigned HOST_WIDE_INT size1
= ((size
- reg_offset
+ 64) + 15) & -16;
7224 /* Offset to register save area from %sp. */
7225 unsigned HOST_WIDE_INT offset
= size1
- (size
- reg_offset
);
7229 fprintf (file
, "\tadd\t%s, %d, %s\n",
7230 sp_str
, (int) -size1
, sp_str
);
7231 if (gmask
& HARD_FRAME_POINTER_MASK
)
7233 fprintf (file
, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7234 fp_str
, sp_str
, (int) offset
, sp_str
, (int) -size1
,
7235 fp_str
, ASM_COMMENT_START
);
7241 fprintf (file
, "\tset\t");
7242 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, size1
);
7243 fprintf (file
, ", %s\n\tsub\t%s, %s, %s\n",
7244 t1_str
, sp_str
, t1_str
, sp_str
);
7245 if (gmask
& HARD_FRAME_POINTER_MASK
)
7247 fprintf (file
, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7248 fp_str
, sp_str
, (int) offset
, sp_str
, t1_str
,
7249 fp_str
, ASM_COMMENT_START
);
7253 if (dwarf2out_do_frame ())
7255 char *l
= dwarf2out_cfi_label ();
7256 if (gmask
& HARD_FRAME_POINTER_MASK
)
7258 dwarf2out_reg_save (l
, HARD_FRAME_POINTER_REGNUM
,
7259 offset
- 4 - size1
);
7260 dwarf2out_def_cfa (l
, HARD_FRAME_POINTER_REGNUM
, 0);
7263 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, size1
);
7265 if (gmask
& RETURN_ADDR_MASK
)
7267 fprintf (file
, "\tst\t%s, [%s+%d]\n",
7268 reg_names
[RETURN_ADDR_REGNUM
], sp_str
, (int) offset
);
7269 if (dwarf2out_do_frame ())
7270 /* offset - size1 == reg_offset - size
7271 if reg_offset were updated above like offset. */
7272 dwarf2out_return_save ("", offset
- size1
);
7275 sparc_flat_save_restore (file
, sp_str
, offset
,
7276 gmask
& ~(HARD_FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
7277 current_frame_info
.fmask
,
7278 "st", "std", -size1
);
7279 fprintf (file
, "\tset\t");
7280 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, size
- size1
);
7281 fprintf (file
, ", %s\n\tsub\t%s, %s, %s\n",
7282 t1_str
, sp_str
, t1_str
, sp_str
);
7283 if (dwarf2out_do_frame ())
7284 if (! (gmask
& HARD_FRAME_POINTER_MASK
))
7285 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, size
);
7289 fprintf (file
, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START
);
7292 /* Do any necessary cleanup after a function to restore stack, frame,
7296 sparc_flat_function_epilogue (file
, size
)
7300 rtx epilogue_delay
= current_function_epilogue_delay_list
;
7301 int noepilogue
= FALSE
;
7303 /* This is only for the human reader. */
7304 fprintf (file
, "\t%s#EPILOGUE#\n", ASM_COMMENT_START
);
7306 /* The epilogue does not depend on any registers, but the stack
7307 registers, so we assume that if we have 1 pending nop, it can be
7308 ignored, and 2 it must be filled (2 nops occur for integer
7309 multiply and divide). */
7311 size
= SPARC_STACK_ALIGN (size
);
7312 size
= (!current_frame_info
.initialized
7313 ? sparc_flat_compute_frame_size (size
)
7314 : current_frame_info
.total_size
);
7316 if (size
== 0 && epilogue_delay
== 0)
7318 rtx insn
= get_last_insn ();
7320 /* If the last insn was a BARRIER, we don't have to write any code
7321 because a jump (aka return) was put there. */
7322 if (GET_CODE (insn
) == NOTE
)
7323 insn
= prev_nonnote_insn (insn
);
7324 if (insn
&& GET_CODE (insn
) == BARRIER
)
7330 unsigned HOST_WIDE_INT reg_offset
= current_frame_info
.reg_offset
;
7331 unsigned HOST_WIDE_INT size1
;
7332 const char *const sp_str
= reg_names
[STACK_POINTER_REGNUM
];
7333 const char *const fp_str
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
7334 static const char *const t1_str
= "%g1";
7336 /* In the reload sequence, we don't need to fill the load delay
7337 slots for most of the loads, also see if we can fill the final
7338 delay slot if not otherwise filled by the reload sequence. */
7342 fprintf (file
, "\tset\t");
7343 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, size
);
7344 fprintf (file
, ", %s\n", t1_str
);
7347 if (frame_pointer_needed
)
7350 fprintf (file
,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
7351 fp_str
, t1_str
, sp_str
, ASM_COMMENT_START
);
7353 fprintf (file
,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
7354 fp_str
, (int) size
, sp_str
, ASM_COMMENT_START
);
7357 /* Is the entire register save area offsettable from %sp? */
7358 if (reg_offset
< 4096 - 64 * (unsigned) UNITS_PER_WORD
)
7364 /* Restore %sp in two steps, but make sure there is always a
7365 64 byte register save area, and %sp is properly aligned. */
7366 /* Amount to increment %sp by, the first time. */
7367 size1
= ((reg_offset
- 64 - 16) + 15) & -16;
7368 /* Offset to register save area from %sp. */
7369 reg_offset
= size1
- reg_offset
;
7371 fprintf (file
, "\tset\t");
7372 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, size1
);
7373 fprintf (file
, ", %s\n\tadd\t%s, %s, %s\n",
7374 t1_str
, sp_str
, t1_str
, sp_str
);
7377 /* We must restore the frame pointer and return address reg first
7378 because they are treated specially by the prologue output code. */
7379 if (current_frame_info
.gmask
& HARD_FRAME_POINTER_MASK
)
7381 fprintf (file
, "\tld\t[%s+%d], %s\n",
7382 sp_str
, (int) reg_offset
, fp_str
);
7385 if (current_frame_info
.gmask
& RETURN_ADDR_MASK
)
7387 fprintf (file
, "\tld\t[%s+%d], %s\n",
7388 sp_str
, (int) reg_offset
, reg_names
[RETURN_ADDR_REGNUM
]);
7392 /* Restore any remaining saved registers. */
7393 sparc_flat_save_restore (file
, sp_str
, reg_offset
,
7394 current_frame_info
.gmask
& ~(HARD_FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
7395 current_frame_info
.fmask
,
7398 /* If we had to increment %sp in two steps, record it so the second
7399 restoration in the epilogue finishes up. */
7405 fprintf (file
, "\tset\t");
7406 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, size
);
7407 fprintf (file
, ", %s\n", t1_str
);
7411 if (current_function_returns_struct
)
7412 fprintf (file
, "\tjmp\t%%o7+12\n");
7414 fprintf (file
, "\tretl\n");
7416 /* If the only register saved is the return address, we need a
7417 nop, unless we have an instruction to put into it. Otherwise
7418 we don't since reloading multiple registers doesn't reference
7419 the register being loaded. */
7425 final_scan_insn (XEXP (epilogue_delay
, 0), file
, 1, -2, 1);
7428 else if (size
> 4095)
7429 fprintf (file
, "\tadd\t%s, %s, %s\n", sp_str
, t1_str
, sp_str
);
7432 fprintf (file
, "\tadd\t%s, %d, %s\n", sp_str
, (int) size
, sp_str
);
7435 fprintf (file
, "\tnop\n");
7438 /* Reset state info for each function. */
7439 current_frame_info
= zero_frame_info
;
7441 sparc_output_deferred_case_vectors ();
7444 /* Define the number of delay slots needed for the function epilogue.
7446 On the sparc, we need a slot if either no stack has been allocated,
7447 or the only register saved is the return register. */
7450 sparc_flat_epilogue_delay_slots ()
7452 if (!current_frame_info
.initialized
)
7453 (void) sparc_flat_compute_frame_size (get_frame_size ());
7455 if (current_frame_info
.total_size
== 0)
7461 /* Return true if TRIAL is a valid insn for the epilogue delay slot.
7462 Any single length instruction which doesn't reference the stack or frame
7466 sparc_flat_eligible_for_epilogue_delay (trial
, slot
)
7468 int slot ATTRIBUTE_UNUSED
;
7470 rtx pat
= PATTERN (trial
);
7472 if (get_attr_length (trial
) != 1)
7475 if (! reg_mentioned_p (stack_pointer_rtx
, pat
)
7476 && ! reg_mentioned_p (frame_pointer_rtx
, pat
))
7482 /* Adjust the cost of a scheduling dependency. Return the new cost of
7483 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7486 supersparc_adjust_cost (insn
, link
, dep_insn
, cost
)
7492 enum attr_type insn_type
;
7494 if (! recog_memoized (insn
))
7497 insn_type
= get_attr_type (insn
);
7499 if (REG_NOTE_KIND (link
) == 0)
7501 /* Data dependency; DEP_INSN writes a register that INSN reads some
7504 /* if a load, then the dependence must be on the memory address;
7505 add an extra "cycle". Note that the cost could be two cycles
7506 if the reg was written late in an instruction group; we ca not tell
7508 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
7511 /* Get the delay only if the address of the store is the dependence. */
7512 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
7514 rtx pat
= PATTERN(insn
);
7515 rtx dep_pat
= PATTERN (dep_insn
);
7517 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
7518 return cost
; /* This should not happen! */
7520 /* The dependency between the two instructions was on the data that
7521 is being stored. Assume that this implies that the address of the
7522 store is not dependent. */
7523 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
7526 return cost
+ 3; /* An approximation. */
7529 /* A shift instruction cannot receive its data from an instruction
7530 in the same cycle; add a one cycle penalty. */
7531 if (insn_type
== TYPE_SHIFT
)
7532 return cost
+ 3; /* Split before cascade into shift. */
7536 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7537 INSN writes some cycles later. */
7539 /* These are only significant for the fpu unit; writing a fp reg before
7540 the fpu has finished with it stalls the processor. */
7542 /* Reusing an integer register causes no problems. */
7543 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
7551 hypersparc_adjust_cost (insn
, link
, dep_insn
, cost
)
7557 enum attr_type insn_type
, dep_type
;
7558 rtx pat
= PATTERN(insn
);
7559 rtx dep_pat
= PATTERN (dep_insn
);
7561 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
7564 insn_type
= get_attr_type (insn
);
7565 dep_type
= get_attr_type (dep_insn
);
7567 switch (REG_NOTE_KIND (link
))
7570 /* Data dependency; DEP_INSN writes a register that INSN reads some
7577 /* Get the delay iff the address of the store is the dependence. */
7578 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
7581 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
7588 /* If a load, then the dependence must be on the memory address. If
7589 the addresses aren't equal, then it might be a false dependency */
7590 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
7592 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
7593 || GET_CODE (SET_DEST (dep_pat
)) != MEM
7594 || GET_CODE (SET_SRC (pat
)) != MEM
7595 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
7596 XEXP (SET_SRC (pat
), 0)))
7604 /* Compare to branch latency is 0. There is no benefit from
7605 separating compare and branch. */
7606 if (dep_type
== TYPE_COMPARE
)
7608 /* Floating point compare to branch latency is less than
7609 compare to conditional move. */
7610 if (dep_type
== TYPE_FPCMP
)
7619 /* Anti-dependencies only penalize the fpu unit. */
7620 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
7632 sparc_adjust_cost(insn
, link
, dep
, cost
)
7640 case PROCESSOR_SUPERSPARC
:
7641 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
7643 case PROCESSOR_HYPERSPARC
:
7644 case PROCESSOR_SPARCLITE86X
:
7645 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
7654 sparc_sched_init (dump
, sched_verbose
, max_ready
)
7655 FILE *dump ATTRIBUTE_UNUSED
;
7656 int sched_verbose ATTRIBUTE_UNUSED
;
7657 int max_ready ATTRIBUTE_UNUSED
;
7662 sparc_use_dfa_pipeline_interface ()
7664 if ((1 << sparc_cpu
) &
7665 ((1 << PROCESSOR_ULTRASPARC
) | (1 << PROCESSOR_CYPRESS
) |
7666 (1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
7667 (1 << PROCESSOR_SPARCLITE86X
) | (1 << PROCESSOR_TSC701
) |
7668 (1 << PROCESSOR_ULTRASPARC3
)))
7674 sparc_use_sched_lookahead ()
7676 if (sparc_cpu
== PROCESSOR_ULTRASPARC
7677 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
7679 if ((1 << sparc_cpu
) &
7680 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
7681 (1 << PROCESSOR_SPARCLITE86X
)))
7694 /* Assume V9 processors are capable of at least dual-issue. */
7696 case PROCESSOR_SUPERSPARC
:
7698 case PROCESSOR_HYPERSPARC
:
7699 case PROCESSOR_SPARCLITE86X
:
7701 case PROCESSOR_ULTRASPARC
:
7702 case PROCESSOR_ULTRASPARC3
:
7711 register rtx pat
= PATTERN (insn
);
7713 switch (GET_CODE (SET_SRC (pat
)))
7715 /* Load and some shift instructions zero extend. */
7718 /* sethi clears the high bits */
7720 /* LO_SUM is used with sethi. sethi cleared the high
7721 bits and the values used with lo_sum are positive */
7723 /* Store flag stores 0 or 1 */
7733 rtx op0
= XEXP (SET_SRC (pat
), 0);
7734 rtx op1
= XEXP (SET_SRC (pat
), 1);
7735 if (GET_CODE (op1
) == CONST_INT
)
7736 return INTVAL (op1
) >= 0;
7737 if (GET_CODE (op0
) != REG
)
7739 if (sparc_check_64 (op0
, insn
) == 1)
7741 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
7746 rtx op0
= XEXP (SET_SRC (pat
), 0);
7747 rtx op1
= XEXP (SET_SRC (pat
), 1);
7748 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
7750 if (GET_CODE (op1
) == CONST_INT
)
7751 return INTVAL (op1
) >= 0;
7752 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
7756 return GET_MODE (SET_SRC (pat
)) == SImode
;
7757 /* Positive integers leave the high bits zero. */
7759 return ! (CONST_DOUBLE_LOW (SET_SRC (pat
)) & 0x80000000);
7761 return ! (INTVAL (SET_SRC (pat
)) & 0x80000000);
7764 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
7766 return sparc_check_64 (SET_SRC (pat
), insn
);
7772 /* We _ought_ to have only one kind per function, but... */
7773 static rtx sparc_addr_diff_list
;
7774 static rtx sparc_addr_list
;
7777 sparc_defer_case_vector (lab
, vec
, diff
)
7781 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
7783 sparc_addr_diff_list
7784 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
7786 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
7790 sparc_output_addr_vec (vec
)
7793 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
7794 int idx
, vlen
= XVECLEN (body
, 0);
7796 #ifdef ASM_OUTPUT_ADDR_VEC_START
7797 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
7800 #ifdef ASM_OUTPUT_CASE_LABEL
7801 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
7804 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
7807 for (idx
= 0; idx
< vlen
; idx
++)
7809 ASM_OUTPUT_ADDR_VEC_ELT
7810 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
7813 #ifdef ASM_OUTPUT_ADDR_VEC_END
7814 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
7819 sparc_output_addr_diff_vec (vec
)
7822 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
7823 rtx base
= XEXP (XEXP (body
, 0), 0);
7824 int idx
, vlen
= XVECLEN (body
, 1);
7826 #ifdef ASM_OUTPUT_ADDR_VEC_START
7827 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
7830 #ifdef ASM_OUTPUT_CASE_LABEL
7831 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
7834 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
7837 for (idx
= 0; idx
< vlen
; idx
++)
7839 ASM_OUTPUT_ADDR_DIFF_ELT
7842 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
7843 CODE_LABEL_NUMBER (base
));
7846 #ifdef ASM_OUTPUT_ADDR_VEC_END
7847 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
7852 sparc_output_deferred_case_vectors ()
7857 if (sparc_addr_list
== NULL_RTX
7858 && sparc_addr_diff_list
== NULL_RTX
)
7861 /* Align to cache line in the function's code section. */
7862 function_section (current_function_decl
);
7864 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
7866 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
7868 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
7869 sparc_output_addr_vec (XEXP (t
, 0));
7870 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
7871 sparc_output_addr_diff_vec (XEXP (t
, 0));
7873 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
7876 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7877 unknown. Return 1 if the high bits are zero, -1 if the register is
7880 sparc_check_64 (x
, insn
)
7883 /* If a register is set only once it is safe to ignore insns this
7884 code does not know how to handle. The loop will either recognize
7885 the single set and return the correct value or fail to recognize
7890 if (GET_CODE (x
) != REG
)
7893 if (GET_MODE (x
) == DImode
)
7894 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
7896 if (flag_expensive_optimizations
7897 && REG_N_SETS (REGNO (y
)) == 1)
7903 insn
= get_last_insn_anywhere ();
7908 while ((insn
= PREV_INSN (insn
)))
7910 switch (GET_CODE (insn
))
7923 rtx pat
= PATTERN (insn
);
7924 if (GET_CODE (pat
) != SET
)
7926 if (rtx_equal_p (x
, SET_DEST (pat
)))
7927 return set_extends (insn
);
7928 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
7929 return set_extends (insn
);
7930 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
7939 sparc_v8plus_shift (operands
, insn
, opcode
)
7944 static char asm_code
[60];
7946 if (GET_CODE (operands
[3]) == SCRATCH
)
7947 operands
[3] = operands
[0];
7948 if (GET_CODE (operands
[1]) == CONST_INT
)
7950 output_asm_insn ("mov\t%1, %3", operands
);
7954 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
7955 if (sparc_check_64 (operands
[1], insn
) <= 0)
7956 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
7957 output_asm_insn ("or\t%L1, %3, %3", operands
);
7960 strcpy(asm_code
, opcode
);
7961 if (which_alternative
!= 2)
7962 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
7964 return strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
7967 /* Output rtl to increment the profiler label LABELNO
7968 for profiling a function entry. */
7971 sparc_profile_hook (labelno
)
7977 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
7978 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
7979 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
7981 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
7984 /* Called to register all of our global variables with the garbage
7988 sparc_add_gc_roots ()
7990 ggc_add_rtx_root (&sparc_compare_op0
, 1);
7991 ggc_add_rtx_root (&sparc_compare_op1
, 1);
7992 ggc_add_rtx_root (&global_offset_table
, 1);
7993 ggc_add_rtx_root (&get_pc_symbol
, 1);
7994 ggc_add_rtx_root (&sparc_addr_diff_list
, 1);
7995 ggc_add_rtx_root (&sparc_addr_list
, 1);
7998 #ifdef OBJECT_FORMAT_ELF
8000 sparc_elf_asm_named_section (name
, flags
)
8004 if (flags
& SECTION_MERGE
)
8006 /* entsize cannot be expressed in this section attributes
8008 default_elf_asm_named_section (name
, flags
);
8012 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
8014 if (!(flags
& SECTION_DEBUG
))
8015 fputs (",#alloc", asm_out_file
);
8016 if (flags
& SECTION_WRITE
)
8017 fputs (",#write", asm_out_file
);
8018 if (flags
& SECTION_CODE
)
8019 fputs (",#execinstr", asm_out_file
);
8021 /* ??? Handle SECTION_BSS. */
8023 fputc ('\n', asm_out_file
);
8025 #endif /* OBJECT_FORMAT_ELF */
8028 sparc_extra_constraint_check (op
, c
, strict
)
8036 && (c
== 'T' || c
== 'U'))
8042 return fp_sethi_p (op
);
8045 return fp_mov_p (op
);
8048 return fp_high_losum_p (op
);
8052 || (GET_CODE (op
) == REG
8053 && (REGNO (op
) < FIRST_PSEUDO_REGISTER
8054 || reg_renumber
[REGNO (op
)] >= 0)))
8055 return register_ok_for_ldd (op
);
8067 /* Our memory extra constraints have to emulate the
8068 behavior of 'm' and 'o' in order for reload to work
8070 if (GET_CODE (op
) == MEM
)
8073 if ((TARGET_ARCH64
|| mem_min_alignment (op
, 8))
8075 || strict_memory_address_p (Pmode
, XEXP (op
, 0))))
8080 reload_ok_mem
= (reload_in_progress
8081 && GET_CODE (op
) == REG
8082 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
8083 && reg_renumber
[REGNO (op
)] < 0);
8086 return reload_ok_mem
;