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mips.c (compute_frame_size): Restore the original gp_sp_offset for !GENERATE_MIPS16E_...
[official-gcc.git] / gcc / config / mips / mips.c
blob980c928a10f8d36911966a21426af3ffbc336ba9
1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING. If not, write to
24 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
25 Boston, MA 02110-1301, USA. */
26
27 #include "config.h"
28 #include "system.h"
29 #include "coretypes.h"
30 #include "tm.h"
31 #include <signal.h>
32 #include "rtl.h"
33 #include "regs.h"
34 #include "hard-reg-set.h"
35 #include "real.h"
36 #include "insn-config.h"
37 #include "conditions.h"
38 #include "insn-attr.h"
39 #include "recog.h"
40 #include "toplev.h"
41 #include "output.h"
42 #include "tree.h"
43 #include "function.h"
44 #include "expr.h"
45 #include "optabs.h"
46 #include "flags.h"
47 #include "reload.h"
48 #include "tm_p.h"
49 #include "ggc.h"
50 #include "gstab.h"
51 #include "hashtab.h"
52 #include "debug.h"
53 #include "target.h"
54 #include "target-def.h"
55 #include "integrate.h"
56 #include "langhooks.h"
57 #include "cfglayout.h"
58 #include "sched-int.h"
59 #include "tree-gimple.h"
60 #include "bitmap.h"
61
62 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
63 #define UNSPEC_ADDRESS_P(X) \
64 (GET_CODE (X) == UNSPEC \
65 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
66 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67
68 /* Extract the symbol or label from UNSPEC wrapper X. */
69 #define UNSPEC_ADDRESS(X) \
70 XVECEXP (X, 0, 0)
71
72 /* Extract the symbol type from UNSPEC wrapper X. */
73 #define UNSPEC_ADDRESS_TYPE(X) \
74 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75
76 /* The maximum distance between the top of the stack frame and the
77 value $sp has when we save and restore registers.
78
79 The value for normal-mode code must be a SMALL_OPERAND and must
80 preserve the maximum stack alignment. We therefore use a value
81 of 0x7ff0 in this case.
82
83 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
84 up to 0x7f8 bytes and can usually save or restore all the registers
85 that we need to save or restore. (Note that we can only use these
86 instructions for o32, for which the stack alignment is 8 bytes.)
87
88 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
89 RESTORE are not available. We can then use unextended instructions
90 to save and restore registers, and to allocate and deallocate the top
91 part of the frame. */
92 #define MIPS_MAX_FIRST_STACK_STEP \
93 (!TARGET_MIPS16 ? 0x7ff0 \
94 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
95 : TARGET_64BIT ? 0x100 : 0x400)
96
97 /* True if INSN is a mips.md pattern or asm statement. */
98 #define USEFUL_INSN_P(INSN) \
99 (INSN_P (INSN) \
100 && GET_CODE (PATTERN (INSN)) != USE \
101 && GET_CODE (PATTERN (INSN)) != CLOBBER \
102 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
103 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
104
105 /* If INSN is a delayed branch sequence, return the first instruction
106 in the sequence, otherwise return INSN itself. */
107 #define SEQ_BEGIN(INSN) \
108 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
109 ? XVECEXP (PATTERN (INSN), 0, 0) \
110 : (INSN))
111
112 /* Likewise for the last instruction in a delayed branch sequence. */
113 #define SEQ_END(INSN) \
114 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
115 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
116 : (INSN))
117
118 /* Execute the following loop body with SUBINSN set to each instruction
119 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
120 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
121 for ((SUBINSN) = SEQ_BEGIN (INSN); \
122 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
123 (SUBINSN) = NEXT_INSN (SUBINSN))
124
125 /* True if bit BIT is set in VALUE. */
126 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
127
128 /* Classifies an address.
129
130 ADDRESS_REG
131 A natural register + offset address. The register satisfies
132 mips_valid_base_register_p and the offset is a const_arith_operand.
133
134 ADDRESS_LO_SUM
135 A LO_SUM rtx. The first operand is a valid base register and
136 the second operand is a symbolic address.
137
138 ADDRESS_CONST_INT
139 A signed 16-bit constant address.
140
141 ADDRESS_SYMBOLIC:
142 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
143 enum mips_address_type {
144 ADDRESS_REG,
145 ADDRESS_LO_SUM,
146 ADDRESS_CONST_INT,
147 ADDRESS_SYMBOLIC
148 };
149
150 /* Classifies the prototype of a builtin function. */
151 enum mips_function_type
152 {
153 MIPS_V2SF_FTYPE_V2SF,
154 MIPS_V2SF_FTYPE_V2SF_V2SF,
155 MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
156 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
157 MIPS_V2SF_FTYPE_SF_SF,
158 MIPS_INT_FTYPE_V2SF_V2SF,
159 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
160 MIPS_INT_FTYPE_SF_SF,
161 MIPS_INT_FTYPE_DF_DF,
162 MIPS_SF_FTYPE_V2SF,
163 MIPS_SF_FTYPE_SF,
164 MIPS_SF_FTYPE_SF_SF,
165 MIPS_DF_FTYPE_DF,
166 MIPS_DF_FTYPE_DF_DF,
167
168 /* For MIPS DSP ASE */
169 MIPS_DI_FTYPE_DI_SI,
170 MIPS_DI_FTYPE_DI_SI_SI,
171 MIPS_DI_FTYPE_DI_V2HI_V2HI,
172 MIPS_DI_FTYPE_DI_V4QI_V4QI,
173 MIPS_SI_FTYPE_DI_SI,
174 MIPS_SI_FTYPE_PTR_SI,
175 MIPS_SI_FTYPE_SI,
176 MIPS_SI_FTYPE_SI_SI,
177 MIPS_SI_FTYPE_V2HI,
178 MIPS_SI_FTYPE_V2HI_V2HI,
179 MIPS_SI_FTYPE_V4QI,
180 MIPS_SI_FTYPE_V4QI_V4QI,
181 MIPS_SI_FTYPE_VOID,
182 MIPS_V2HI_FTYPE_SI,
183 MIPS_V2HI_FTYPE_SI_SI,
184 MIPS_V2HI_FTYPE_V2HI,
185 MIPS_V2HI_FTYPE_V2HI_SI,
186 MIPS_V2HI_FTYPE_V2HI_V2HI,
187 MIPS_V2HI_FTYPE_V4QI,
188 MIPS_V2HI_FTYPE_V4QI_V2HI,
189 MIPS_V4QI_FTYPE_SI,
190 MIPS_V4QI_FTYPE_V2HI_V2HI,
191 MIPS_V4QI_FTYPE_V4QI_SI,
192 MIPS_V4QI_FTYPE_V4QI_V4QI,
193 MIPS_VOID_FTYPE_SI_SI,
194 MIPS_VOID_FTYPE_V2HI_V2HI,
195 MIPS_VOID_FTYPE_V4QI_V4QI,
196
197 /* For MIPS DSP REV 2 ASE. */
198 MIPS_V4QI_FTYPE_V4QI,
199 MIPS_SI_FTYPE_SI_SI_SI,
200 MIPS_DI_FTYPE_DI_USI_USI,
201 MIPS_DI_FTYPE_SI_SI,
202 MIPS_DI_FTYPE_USI_USI,
203 MIPS_V2HI_FTYPE_SI_SI_SI,
204
205 /* The last type. */
206 MIPS_MAX_FTYPE_MAX
207 };
208
209 /* Specifies how a builtin function should be converted into rtl. */
210 enum mips_builtin_type
211 {
212 /* The builtin corresponds directly to an .md pattern. The return
213 value is mapped to operand 0 and the arguments are mapped to
214 operands 1 and above. */
215 MIPS_BUILTIN_DIRECT,
216
217 /* The builtin corresponds directly to an .md pattern. There is no return
218 value and the arguments are mapped to operands 0 and above. */
219 MIPS_BUILTIN_DIRECT_NO_TARGET,
220
221 /* The builtin corresponds to a comparison instruction followed by
222 a mips_cond_move_tf_ps pattern. The first two arguments are the
223 values to compare and the second two arguments are the vector
224 operands for the movt.ps or movf.ps instruction (in assembly order). */
225 MIPS_BUILTIN_MOVF,
226 MIPS_BUILTIN_MOVT,
227
228 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
229 of this instruction is the result of the comparison, which has mode
230 CCV2 or CCV4. The function arguments are mapped to operands 1 and
231 above. The function's return value is an SImode boolean that is
232 true under the following conditions:
233
234 MIPS_BUILTIN_CMP_ANY: one of the registers is true
235 MIPS_BUILTIN_CMP_ALL: all of the registers are true
236 MIPS_BUILTIN_CMP_LOWER: the first register is true
237 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
238 MIPS_BUILTIN_CMP_ANY,
239 MIPS_BUILTIN_CMP_ALL,
240 MIPS_BUILTIN_CMP_UPPER,
241 MIPS_BUILTIN_CMP_LOWER,
242
243 /* As above, but the instruction only sets a single $fcc register. */
244 MIPS_BUILTIN_CMP_SINGLE,
245
246 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
247 MIPS_BUILTIN_BPOSGE32
248 };
249
250 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
251 #define MIPS_FP_CONDITIONS(MACRO) \
252 MACRO (f), \
253 MACRO (un), \
254 MACRO (eq), \
255 MACRO (ueq), \
256 MACRO (olt), \
257 MACRO (ult), \
258 MACRO (ole), \
259 MACRO (ule), \
260 MACRO (sf), \
261 MACRO (ngle), \
262 MACRO (seq), \
263 MACRO (ngl), \
264 MACRO (lt), \
265 MACRO (nge), \
266 MACRO (le), \
267 MACRO (ngt)
268
269 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
270 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
271 enum mips_fp_condition {
272 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
273 };
274
275 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
276 #define STRINGIFY(X) #X
277 static const char *const mips_fp_conditions[] = {
278 MIPS_FP_CONDITIONS (STRINGIFY)
279 };
280
281 /* A function to save or store a register. The first argument is the
282 register and the second is the stack slot. */
283 typedef void (*mips_save_restore_fn) (rtx, rtx);
284
285 struct mips16_constant;
286 struct mips_arg_info;
287 struct mips_address_info;
288 struct mips_integer_op;
289 struct mips_sim;
290
291 static enum mips_symbol_type mips_classify_symbol (rtx);
292 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
293 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
294 static bool mips_classify_address (struct mips_address_info *, rtx,
295 enum machine_mode, int);
296 static bool mips_cannot_force_const_mem (rtx);
297 static bool mips_use_blocks_for_constant_p (enum machine_mode, rtx);
298 static int mips_symbol_insns (enum mips_symbol_type);
299 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
300 static rtx mips_force_temporary (rtx, rtx);
301 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
302 static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
303 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
304 static unsigned int mips_build_lower (struct mips_integer_op *,
305 unsigned HOST_WIDE_INT);
306 static unsigned int mips_build_integer (struct mips_integer_op *,
307 unsigned HOST_WIDE_INT);
308 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
309 static int m16_check_op (rtx, int, int, int);
310 static bool mips_rtx_costs (rtx, int, int, int *);
311 static int mips_address_cost (rtx);
312 static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
313 static void mips_load_call_address (rtx, rtx, int);
314 static bool mips_function_ok_for_sibcall (tree, tree);
315 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
316 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
317 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
318 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
319 tree, int, struct mips_arg_info *);
320 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
321 static void mips_set_architecture (const struct mips_cpu_info *);
322 static void mips_set_tune (const struct mips_cpu_info *);
323 static bool mips_handle_option (size_t, const char *, int);
324 static struct machine_function *mips_init_machine_status (void);
325 static void print_operand_reloc (FILE *, rtx, const char **);
326 static void mips_file_start (void);
327 static bool mips_rewrite_small_data_p (rtx);
328 static int mips_small_data_pattern_1 (rtx *, void *);
329 static int mips_rewrite_small_data_1 (rtx *, void *);
330 static bool mips_function_has_gp_insn (void);
331 static unsigned int mips_global_pointer (void);
332 static bool mips_save_reg_p (unsigned int);
333 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
334 mips_save_restore_fn);
335 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
336 static void mips_output_cplocal (void);
337 static void mips_emit_loadgp (void);
338 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
339 static void mips_set_frame_expr (rtx);
340 static rtx mips_frame_set (rtx, rtx);
341 static void mips_save_reg (rtx, rtx);
342 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
343 static void mips_restore_reg (rtx, rtx);
344 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
345 HOST_WIDE_INT, tree);
346 static int symbolic_expression_p (rtx);
347 static section *mips_select_rtx_section (enum machine_mode, rtx,
348 unsigned HOST_WIDE_INT);
349 static section *mips_function_rodata_section (tree);
350 static bool mips_in_small_data_p (tree);
351 static bool mips_use_anchors_for_symbol_p (rtx);
352 static int mips_fpr_return_fields (tree, tree *);
353 static bool mips_return_in_msb (tree);
354 static rtx mips_return_fpr_pair (enum machine_mode mode,
355 enum machine_mode mode1, HOST_WIDE_INT,
356 enum machine_mode mode2, HOST_WIDE_INT);
357 static rtx mips16_gp_pseudo_reg (void);
358 static void mips16_fp_args (FILE *, int, int);
359 static void build_mips16_function_stub (FILE *);
360 static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
361 static void dump_constants (struct mips16_constant *, rtx);
362 static int mips16_insn_length (rtx);
363 static int mips16_rewrite_pool_refs (rtx *, void *);
364 static void mips16_lay_out_constants (void);
365 static void mips_sim_reset (struct mips_sim *);
366 static void mips_sim_init (struct mips_sim *, state_t);
367 static void mips_sim_next_cycle (struct mips_sim *);
368 static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
369 static int mips_sim_wait_regs_2 (rtx *, void *);
370 static void mips_sim_wait_regs_1 (rtx *, void *);
371 static void mips_sim_wait_regs (struct mips_sim *, rtx);
372 static void mips_sim_wait_units (struct mips_sim *, rtx);
373 static void mips_sim_wait_insn (struct mips_sim *, rtx);
374 static void mips_sim_record_set (rtx, rtx, void *);
375 static void mips_sim_issue_insn (struct mips_sim *, rtx);
376 static void mips_sim_issue_nop (struct mips_sim *);
377 static void mips_sim_finish_insn (struct mips_sim *, rtx);
378 static void vr4130_avoid_branch_rt_conflict (rtx);
379 static void vr4130_align_insns (void);
380 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
381 static void mips_avoid_hazards (void);
382 static void mips_reorg (void);
383 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
384 static bool mips_matching_cpu_name_p (const char *, const char *);
385 static const struct mips_cpu_info *mips_parse_cpu (const char *);
386 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
387 static bool mips_return_in_memory (tree, tree);
388 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
389 static void mips_macc_chains_record (rtx);
390 static void mips_macc_chains_reorder (rtx *, int);
391 static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
392 static bool vr4130_true_reg_dependence_p (rtx);
393 static bool vr4130_swap_insns_p (rtx, rtx);
394 static void vr4130_reorder (rtx *, int);
395 static void mips_promote_ready (rtx *, int, int);
396 static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
397 static int mips_variable_issue (FILE *, int, rtx, int);
398 static int mips_adjust_cost (rtx, rtx, rtx, int);
399 static int mips_issue_rate (void);
400 static int mips_multipass_dfa_lookahead (void);
401 static void mips_init_libfuncs (void);
402 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
403 tree, int *, int);
404 static tree mips_build_builtin_va_list (void);
405 static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
406 static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
407 tree, bool);
408 static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,
409 tree, bool);
410 static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,
411 tree, bool);
412 static bool mips_valid_pointer_mode (enum machine_mode);
413 static bool mips_vector_mode_supported_p (enum machine_mode);
414 static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree, unsigned int);
415 static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
416 static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
417 static void mips_init_builtins (void);
418 static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree, bool);
419 static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
420 enum insn_code, enum mips_fp_condition,
421 rtx, tree);
422 static rtx mips_expand_builtin_compare (enum mips_builtin_type,
423 enum insn_code, enum mips_fp_condition,
424 rtx, tree);
425 static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx);
426 static void mips_encode_section_info (tree, rtx, int);
427 static void mips_extra_live_on_entry (bitmap);
428 static int mips_comp_type_attributes (tree, tree);
429 static int mips_mode_rep_extended (enum machine_mode, enum machine_mode);
430 static bool mips_offset_within_alignment_p (rtx, HOST_WIDE_INT);
431 static void mips_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
432
433 /* Structure to be filled in by compute_frame_size with register
434 save masks, and offsets for the current function. */
435
436 struct mips_frame_info GTY(())
437 {
438 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
439 HOST_WIDE_INT var_size; /* # bytes that variables take up */
440 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
441 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
442 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
443 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
444 unsigned int mask; /* mask of saved gp registers */
445 unsigned int fmask; /* mask of saved fp registers */
446 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
447 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
448 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
449 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
450 bool initialized; /* true if frame size already calculated */
451 int num_gp; /* number of gp registers saved */
452 int num_fp; /* number of fp registers saved */
453 };
454
455 struct machine_function GTY(()) {
456 /* Pseudo-reg holding the value of $28 in a mips16 function which
457 refers to GP relative global variables. */
458 rtx mips16_gp_pseudo_rtx;
459
460 /* The number of extra stack bytes taken up by register varargs.
461 This area is allocated by the callee at the very top of the frame. */
462 int varargs_size;
463
464 /* Current frame information, calculated by compute_frame_size. */
465 struct mips_frame_info frame;
466
467 /* The register to use as the global pointer within this function. */
468 unsigned int global_pointer;
469
470 /* True if mips_adjust_insn_length should ignore an instruction's
471 hazard attribute. */
472 bool ignore_hazard_length_p;
473
474 /* True if the whole function is suitable for .set noreorder and
475 .set nomacro. */
476 bool all_noreorder_p;
477
478 /* True if the function is known to have an instruction that needs $gp. */
479 bool has_gp_insn_p;
480 };
481
482 /* Information about a single argument. */
483 struct mips_arg_info
484 {
485 /* True if the argument is passed in a floating-point register, or
486 would have been if we hadn't run out of registers. */
487 bool fpr_p;
488
489 /* The number of words passed in registers, rounded up. */
490 unsigned int reg_words;
491
492 /* For EABI, the offset of the first register from GP_ARG_FIRST or
493 FP_ARG_FIRST. For other ABIs, the offset of the first register from
494 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
495 comment for details).
496
497 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
498 on the stack. */
499 unsigned int reg_offset;
500
501 /* The number of words that must be passed on the stack, rounded up. */
502 unsigned int stack_words;
503
504 /* The offset from the start of the stack overflow area of the argument's
505 first stack word. Only meaningful when STACK_WORDS is nonzero. */
506 unsigned int stack_offset;
507 };
508
509
510 /* Information about an address described by mips_address_type.
511
512 ADDRESS_CONST_INT
513 No fields are used.
514
515 ADDRESS_REG
516 REG is the base register and OFFSET is the constant offset.
517
518 ADDRESS_LO_SUM
519 REG is the register that contains the high part of the address,
520 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
521 is the type of OFFSET's symbol.
522
523 ADDRESS_SYMBOLIC
524 SYMBOL_TYPE is the type of symbol being referenced. */
525
526 struct mips_address_info
527 {
528 enum mips_address_type type;
529 rtx reg;
530 rtx offset;
531 enum mips_symbol_type symbol_type;
532 };
533
534
535 /* One stage in a constant building sequence. These sequences have
536 the form:
537
538 A = VALUE[0]
539 A = A CODE[1] VALUE[1]
540 A = A CODE[2] VALUE[2]
541 ...
542
543 where A is an accumulator, each CODE[i] is a binary rtl operation
544 and each VALUE[i] is a constant integer. */
545 struct mips_integer_op {
546 enum rtx_code code;
547 unsigned HOST_WIDE_INT value;
548 };
549
550
551 /* The largest number of operations needed to load an integer constant.
552 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
553 When the lowest bit is clear, we can try, but reject a sequence with
554 an extra SLL at the end. */
555 #define MIPS_MAX_INTEGER_OPS 7
556
557 /* Information about a MIPS16e SAVE or RESTORE instruction. */
558 struct mips16e_save_restore_info {
559 /* The number of argument registers saved by a SAVE instruction.
560 0 for RESTORE instructions. */
561 unsigned int nargs;
562
563 /* Bit X is set if the instruction saves or restores GPR X. */
564 unsigned int mask;
565
566 /* The total number of bytes to allocate. */
567 HOST_WIDE_INT size;
568 };
569
570 /* Global variables for machine-dependent things. */
571
572 /* Threshold for data being put into the small data/bss area, instead
573 of the normal data area. */
574 int mips_section_threshold = -1;
575
576 /* Count the number of .file directives, so that .loc is up to date. */
577 int num_source_filenames = 0;
578
579 /* Count the number of sdb related labels are generated (to find block
580 start and end boundaries). */
581 int sdb_label_count = 0;
582
583 /* Next label # for each statement for Silicon Graphics IRIS systems. */
584 int sym_lineno = 0;
585
586 /* Name of the file containing the current function. */
587 const char *current_function_file = "";
588
589 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
590 int set_noreorder;
591 int set_noat;
592 int set_nomacro;
593 int set_volatile;
594
595 /* The next branch instruction is a branch likely, not branch normal. */
596 int mips_branch_likely;
597
598 /* The operands passed to the last cmpMM expander. */
599 rtx cmp_operands[2];
600
601 /* The target cpu for code generation. */
602 enum processor_type mips_arch;
603 const struct mips_cpu_info *mips_arch_info;
604
605 /* The target cpu for optimization and scheduling. */
606 enum processor_type mips_tune;
607 const struct mips_cpu_info *mips_tune_info;
608
609 /* Which instruction set architecture to use. */
610 int mips_isa;
611
612 /* Which ABI to use. */
613 int mips_abi = MIPS_ABI_DEFAULT;
614
615 /* Cost information to use. */
616 const struct mips_rtx_cost_data *mips_cost;
617
618 /* Whether we are generating mips16 hard float code. In mips16 mode
619 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
620 -msoft-float was not specified by the user, which means that we
621 should arrange to call mips32 hard floating point code. */
622 int mips16_hard_float;
623
624 /* The architecture selected by -mipsN. */
625 static const struct mips_cpu_info *mips_isa_info;
626
627 /* If TRUE, we split addresses into their high and low parts in the RTL. */
628 int mips_split_addresses;
629
630 /* Mode used for saving/restoring general purpose registers. */
631 static enum machine_mode gpr_mode;
632
633 /* Array giving truth value on whether or not a given hard register
634 can support a given mode. */
635 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
636
637 /* List of all MIPS punctuation characters used by print_operand. */
638 char mips_print_operand_punct[256];
639
640 /* Map GCC register number to debugger register number. */
641 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
642
643 /* A copy of the original flag_delayed_branch: see override_options. */
644 static int mips_flag_delayed_branch;
645
646 static GTY (()) int mips_output_filename_first_time = 1;
647
648 /* mips_split_p[X] is true if symbols of type X can be split by
649 mips_split_symbol(). */
650 bool mips_split_p[NUM_SYMBOL_TYPES];
651
652 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
653 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
654 if they are matched by a special .md file pattern. */
655 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
656
657 /* Likewise for HIGHs. */
658 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
659
660 /* Map hard register number to register class */
661 const enum reg_class mips_regno_to_class[] =
662 {
663 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
664 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
665 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
666 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
667 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
668 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
669 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
670 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
671 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
672 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
673 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
674 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
675 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
676 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
677 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
678 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
679 HI_REG, LO_REG, NO_REGS, ST_REGS,
680 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
681 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
682 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
683 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
684 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
685 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
686 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
687 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
688 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
689 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
690 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
691 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
692 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
693 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
694 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
695 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
696 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
697 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
698 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
699 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
700 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
701 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
702 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
703 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
704 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
705 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
706 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
707 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
708 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
709 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
710 };
711
712 /* Table of machine dependent attributes. */
713 const struct attribute_spec mips_attribute_table[] =
714 {
715 { "long_call", 0, 0, false, true, true, NULL },
716 { "far", 0, 0, false, true, true, NULL },
717 { "near", 0, 0, false, true, true, NULL },
718 { NULL, 0, 0, false, false, false, NULL }
719 };
720 \f
721 /* A table describing all the processors gcc knows about. Names are
722 matched in the order listed. The first mention of an ISA level is
723 taken as the canonical name for that ISA.
724
725 To ease comparison, please keep this table in the same order as
726 gas's mips_cpu_info_table[]. */
727 const struct mips_cpu_info mips_cpu_info_table[] = {
728 /* Entries for generic ISAs */
729 { "mips1", PROCESSOR_R3000, 1 },
730 { "mips2", PROCESSOR_R6000, 2 },
731 { "mips3", PROCESSOR_R4000, 3 },
732 { "mips4", PROCESSOR_R8000, 4 },
733 { "mips32", PROCESSOR_4KC, 32 },
734 { "mips32r2", PROCESSOR_M4K, 33 },
735 { "mips64", PROCESSOR_5KC, 64 },
736
737 /* MIPS I */
738 { "r3000", PROCESSOR_R3000, 1 },
739 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
740 { "r3900", PROCESSOR_R3900, 1 },
741
742 /* MIPS II */
743 { "r6000", PROCESSOR_R6000, 2 },
744
745 /* MIPS III */
746 { "r4000", PROCESSOR_R4000, 3 },
747 { "vr4100", PROCESSOR_R4100, 3 },
748 { "vr4111", PROCESSOR_R4111, 3 },
749 { "vr4120", PROCESSOR_R4120, 3 },
750 { "vr4130", PROCESSOR_R4130, 3 },
751 { "vr4300", PROCESSOR_R4300, 3 },
752 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
753 { "r4600", PROCESSOR_R4600, 3 },
754 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
755 { "r4650", PROCESSOR_R4650, 3 },
756
757 /* MIPS IV */
758 { "r8000", PROCESSOR_R8000, 4 },
759 { "vr5000", PROCESSOR_R5000, 4 },
760 { "vr5400", PROCESSOR_R5400, 4 },
761 { "vr5500", PROCESSOR_R5500, 4 },
762 { "rm7000", PROCESSOR_R7000, 4 },
763 { "rm9000", PROCESSOR_R9000, 4 },
764
765 /* MIPS32 */
766 { "4kc", PROCESSOR_4KC, 32 },
767 { "4km", PROCESSOR_4KC, 32 }, /* = 4kc */
768 { "4kp", PROCESSOR_4KP, 32 },
769 { "4ksc", PROCESSOR_4KC, 32 },
770
771 /* MIPS32 Release 2 */
772 { "m4k", PROCESSOR_M4K, 33 },
773 { "4kec", PROCESSOR_4KC, 33 },
774 { "4kem", PROCESSOR_4KC, 33 },
775 { "4kep", PROCESSOR_4KP, 33 },
776 { "4ksd", PROCESSOR_4KC, 33 },
777
778 { "24kc", PROCESSOR_24KC, 33 },
779 { "24kf2_1", PROCESSOR_24KF2_1, 33 },
780 { "24kf", PROCESSOR_24KF2_1, 33 },
781 { "24kf1_1", PROCESSOR_24KF1_1, 33 },
782 { "24kfx", PROCESSOR_24KF1_1, 33 },
783 { "24kx", PROCESSOR_24KF1_1, 33 },
784
785 { "24kec", PROCESSOR_24KC, 33 }, /* 24K with DSP */
786 { "24kef2_1", PROCESSOR_24KF2_1, 33 },
787 { "24kef", PROCESSOR_24KF2_1, 33 },
788 { "24kef1_1", PROCESSOR_24KF1_1, 33 },
789 { "24kefx", PROCESSOR_24KF1_1, 33 },
790 { "24kex", PROCESSOR_24KF1_1, 33 },
791
792 { "34kc", PROCESSOR_24KC, 33 }, /* 34K with MT/DSP */
793 { "34kf2_1", PROCESSOR_24KF2_1, 33 },
794 { "34kf", PROCESSOR_24KF2_1, 33 },
795 { "34kf1_1", PROCESSOR_24KF1_1, 33 },
796 { "34kfx", PROCESSOR_24KF1_1, 33 },
797 { "34kx", PROCESSOR_24KF1_1, 33 },
798
799 { "74kc", PROCESSOR_74KC, 33 }, /* 74K with DSPr2 */
800 { "74kf2_1", PROCESSOR_74KF2_1, 33 },
801 { "74kf", PROCESSOR_74KF2_1, 33 },
802 { "74kf1_1", PROCESSOR_74KF1_1, 33 },
803 { "74kfx", PROCESSOR_74KF1_1, 33 },
804 { "74kx", PROCESSOR_74KF1_1, 33 },
805 { "74kf3_2", PROCESSOR_74KF3_2, 33 },
806
807 /* MIPS64 */
808 { "5kc", PROCESSOR_5KC, 64 },
809 { "5kf", PROCESSOR_5KF, 64 },
810 { "20kc", PROCESSOR_20KC, 64 },
811 { "sb1", PROCESSOR_SB1, 64 },
812 { "sb1a", PROCESSOR_SB1A, 64 },
813 { "sr71000", PROCESSOR_SR71000, 64 },
814
815 /* End marker */
816 { 0, 0, 0 }
817 };
818
819 /* Default costs. If these are used for a processor we should look
820 up the actual costs. */
821 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
822 COSTS_N_INSNS (7), /* fp_mult_sf */ \
823 COSTS_N_INSNS (8), /* fp_mult_df */ \
824 COSTS_N_INSNS (23), /* fp_div_sf */ \
825 COSTS_N_INSNS (36), /* fp_div_df */ \
826 COSTS_N_INSNS (10), /* int_mult_si */ \
827 COSTS_N_INSNS (10), /* int_mult_di */ \
828 COSTS_N_INSNS (69), /* int_div_si */ \
829 COSTS_N_INSNS (69), /* int_div_di */ \
830 2, /* branch_cost */ \
831 4 /* memory_latency */
832
833 /* Need to replace these with the costs of calling the appropriate
834 libgcc routine. */
835 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
836 COSTS_N_INSNS (256), /* fp_mult_sf */ \
837 COSTS_N_INSNS (256), /* fp_mult_df */ \
838 COSTS_N_INSNS (256), /* fp_div_sf */ \
839 COSTS_N_INSNS (256) /* fp_div_df */
840
841 static struct mips_rtx_cost_data const mips_rtx_cost_optimize_size =
842 {
843 COSTS_N_INSNS (1), /* fp_add */
844 COSTS_N_INSNS (1), /* fp_mult_sf */
845 COSTS_N_INSNS (1), /* fp_mult_df */
846 COSTS_N_INSNS (1), /* fp_div_sf */
847 COSTS_N_INSNS (1), /* fp_div_df */
848 COSTS_N_INSNS (1), /* int_mult_si */
849 COSTS_N_INSNS (1), /* int_mult_di */
850 COSTS_N_INSNS (1), /* int_div_si */
851 COSTS_N_INSNS (1), /* int_div_di */
852 2, /* branch_cost */
853 4 /* memory_latency */
854 };
855
856 static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
857 {
858 { /* R3000 */
859 COSTS_N_INSNS (2), /* fp_add */
860 COSTS_N_INSNS (4), /* fp_mult_sf */
861 COSTS_N_INSNS (5), /* fp_mult_df */
862 COSTS_N_INSNS (12), /* fp_div_sf */
863 COSTS_N_INSNS (19), /* fp_div_df */
864 COSTS_N_INSNS (12), /* int_mult_si */
865 COSTS_N_INSNS (12), /* int_mult_di */
866 COSTS_N_INSNS (35), /* int_div_si */
867 COSTS_N_INSNS (35), /* int_div_di */
868 1, /* branch_cost */
869 4 /* memory_latency */
870
871 },
872 { /* 4KC */
873 SOFT_FP_COSTS,
874 COSTS_N_INSNS (6), /* int_mult_si */
875 COSTS_N_INSNS (6), /* int_mult_di */
876 COSTS_N_INSNS (36), /* int_div_si */
877 COSTS_N_INSNS (36), /* int_div_di */
878 1, /* branch_cost */
879 4 /* memory_latency */
880 },
881 { /* 4KP */
882 SOFT_FP_COSTS,
883 COSTS_N_INSNS (36), /* int_mult_si */
884 COSTS_N_INSNS (36), /* int_mult_di */
885 COSTS_N_INSNS (37), /* int_div_si */
886 COSTS_N_INSNS (37), /* int_div_di */
887 1, /* branch_cost */
888 4 /* memory_latency */
889 },
890 { /* 5KC */
891 SOFT_FP_COSTS,
892 COSTS_N_INSNS (4), /* int_mult_si */
893 COSTS_N_INSNS (11), /* int_mult_di */
894 COSTS_N_INSNS (36), /* int_div_si */
895 COSTS_N_INSNS (68), /* int_div_di */
896 1, /* branch_cost */
897 4 /* memory_latency */
898 },
899 { /* 5KF */
900 COSTS_N_INSNS (4), /* fp_add */
901 COSTS_N_INSNS (4), /* fp_mult_sf */
902 COSTS_N_INSNS (5), /* fp_mult_df */
903 COSTS_N_INSNS (17), /* fp_div_sf */
904 COSTS_N_INSNS (32), /* fp_div_df */
905 COSTS_N_INSNS (4), /* int_mult_si */
906 COSTS_N_INSNS (11), /* int_mult_di */
907 COSTS_N_INSNS (36), /* int_div_si */
908 COSTS_N_INSNS (68), /* int_div_di */
909 1, /* branch_cost */
910 4 /* memory_latency */
911 },
912 { /* 20KC */
913 DEFAULT_COSTS
914 },
915 { /* 24KC */
916 SOFT_FP_COSTS,
917 COSTS_N_INSNS (5), /* int_mult_si */
918 COSTS_N_INSNS (5), /* int_mult_di */
919 COSTS_N_INSNS (41), /* int_div_si */
920 COSTS_N_INSNS (41), /* int_div_di */
921 1, /* branch_cost */
922 4 /* memory_latency */
923 },
924 { /* 24KF2_1 */
925 COSTS_N_INSNS (8), /* fp_add */
926 COSTS_N_INSNS (8), /* fp_mult_sf */
927 COSTS_N_INSNS (10), /* fp_mult_df */
928 COSTS_N_INSNS (34), /* fp_div_sf */
929 COSTS_N_INSNS (64), /* fp_div_df */
930 COSTS_N_INSNS (5), /* int_mult_si */
931 COSTS_N_INSNS (5), /* int_mult_di */
932 COSTS_N_INSNS (41), /* int_div_si */
933 COSTS_N_INSNS (41), /* int_div_di */
934 1, /* branch_cost */
935 4 /* memory_latency */
936 },
937 { /* 24KF1_1 */
938 COSTS_N_INSNS (4), /* fp_add */
939 COSTS_N_INSNS (4), /* fp_mult_sf */
940 COSTS_N_INSNS (5), /* fp_mult_df */
941 COSTS_N_INSNS (17), /* fp_div_sf */
942 COSTS_N_INSNS (32), /* fp_div_df */
943 COSTS_N_INSNS (5), /* int_mult_si */
944 COSTS_N_INSNS (5), /* int_mult_di */
945 COSTS_N_INSNS (41), /* int_div_si */
946 COSTS_N_INSNS (41), /* int_div_di */
947 1, /* branch_cost */
948 4 /* memory_latency */
949 },
950 { /* 74KC */
951 SOFT_FP_COSTS,
952 COSTS_N_INSNS (5), /* int_mult_si */
953 COSTS_N_INSNS (5), /* int_mult_di */
954 COSTS_N_INSNS (41), /* int_div_si */
955 COSTS_N_INSNS (41), /* int_div_di */
956 1, /* branch_cost */
957 4 /* memory_latency */
958 },
959 { /* 74KF2_1 */
960 COSTS_N_INSNS (8), /* fp_add */
961 COSTS_N_INSNS (8), /* fp_mult_sf */
962 COSTS_N_INSNS (10), /* fp_mult_df */
963 COSTS_N_INSNS (34), /* fp_div_sf */
964 COSTS_N_INSNS (64), /* fp_div_df */
965 COSTS_N_INSNS (5), /* int_mult_si */
966 COSTS_N_INSNS (5), /* int_mult_di */
967 COSTS_N_INSNS (41), /* int_div_si */
968 COSTS_N_INSNS (41), /* int_div_di */
969 1, /* branch_cost */
970 4 /* memory_latency */
971 },
972 { /* 74KF1_1 */
973 COSTS_N_INSNS (4), /* fp_add */
974 COSTS_N_INSNS (4), /* fp_mult_sf */
975 COSTS_N_INSNS (5), /* fp_mult_df */
976 COSTS_N_INSNS (17), /* fp_div_sf */
977 COSTS_N_INSNS (32), /* fp_div_df */
978 COSTS_N_INSNS (5), /* int_mult_si */
979 COSTS_N_INSNS (5), /* int_mult_di */
980 COSTS_N_INSNS (41), /* int_div_si */
981 COSTS_N_INSNS (41), /* int_div_di */
982 1, /* branch_cost */
983 4 /* memory_latency */
984 },
985 { /* 74KF3_2 */
986 COSTS_N_INSNS (6), /* fp_add */
987 COSTS_N_INSNS (6), /* fp_mult_sf */
988 COSTS_N_INSNS (7), /* fp_mult_df */
989 COSTS_N_INSNS (25), /* fp_div_sf */
990 COSTS_N_INSNS (48), /* fp_div_df */
991 COSTS_N_INSNS (5), /* int_mult_si */
992 COSTS_N_INSNS (5), /* int_mult_di */
993 COSTS_N_INSNS (41), /* int_div_si */
994 COSTS_N_INSNS (41), /* int_div_di */
995 1, /* branch_cost */
996 4 /* memory_latency */
997 },
998 { /* M4k */
999 DEFAULT_COSTS
1000 },
1001 { /* R3900 */
1002 COSTS_N_INSNS (2), /* fp_add */
1003 COSTS_N_INSNS (4), /* fp_mult_sf */
1004 COSTS_N_INSNS (5), /* fp_mult_df */
1005 COSTS_N_INSNS (12), /* fp_div_sf */
1006 COSTS_N_INSNS (19), /* fp_div_df */
1007 COSTS_N_INSNS (2), /* int_mult_si */
1008 COSTS_N_INSNS (2), /* int_mult_di */
1009 COSTS_N_INSNS (35), /* int_div_si */
1010 COSTS_N_INSNS (35), /* int_div_di */
1011 1, /* branch_cost */
1012 4 /* memory_latency */
1013 },
1014 { /* R6000 */
1015 COSTS_N_INSNS (3), /* fp_add */
1016 COSTS_N_INSNS (5), /* fp_mult_sf */
1017 COSTS_N_INSNS (6), /* fp_mult_df */
1018 COSTS_N_INSNS (15), /* fp_div_sf */
1019 COSTS_N_INSNS (16), /* fp_div_df */
1020 COSTS_N_INSNS (17), /* int_mult_si */
1021 COSTS_N_INSNS (17), /* int_mult_di */
1022 COSTS_N_INSNS (38), /* int_div_si */
1023 COSTS_N_INSNS (38), /* int_div_di */
1024 2, /* branch_cost */
1025 6 /* memory_latency */
1026 },
1027 { /* R4000 */
1028 COSTS_N_INSNS (6), /* fp_add */
1029 COSTS_N_INSNS (7), /* fp_mult_sf */
1030 COSTS_N_INSNS (8), /* fp_mult_df */
1031 COSTS_N_INSNS (23), /* fp_div_sf */
1032 COSTS_N_INSNS (36), /* fp_div_df */
1033 COSTS_N_INSNS (10), /* int_mult_si */
1034 COSTS_N_INSNS (10), /* int_mult_di */
1035 COSTS_N_INSNS (69), /* int_div_si */
1036 COSTS_N_INSNS (69), /* int_div_di */
1037 2, /* branch_cost */
1038 6 /* memory_latency */
1039 },
1040 { /* R4100 */
1041 DEFAULT_COSTS
1042 },
1043 { /* R4111 */
1044 DEFAULT_COSTS
1045 },
1046 { /* R4120 */
1047 DEFAULT_COSTS
1048 },
1049 { /* R4130 */
1050 /* The only costs that appear to be updated here are
1051 integer multiplication. */
1052 SOFT_FP_COSTS,
1053 COSTS_N_INSNS (4), /* int_mult_si */
1054 COSTS_N_INSNS (6), /* int_mult_di */
1055 COSTS_N_INSNS (69), /* int_div_si */
1056 COSTS_N_INSNS (69), /* int_div_di */
1057 1, /* branch_cost */
1058 4 /* memory_latency */
1059 },
1060 { /* R4300 */
1061 DEFAULT_COSTS
1062 },
1063 { /* R4600 */
1064 DEFAULT_COSTS
1065 },
1066 { /* R4650 */
1067 DEFAULT_COSTS
1068 },
1069 { /* R5000 */
1070 COSTS_N_INSNS (6), /* fp_add */
1071 COSTS_N_INSNS (4), /* fp_mult_sf */
1072 COSTS_N_INSNS (5), /* fp_mult_df */
1073 COSTS_N_INSNS (23), /* fp_div_sf */
1074 COSTS_N_INSNS (36), /* fp_div_df */
1075 COSTS_N_INSNS (5), /* int_mult_si */
1076 COSTS_N_INSNS (5), /* int_mult_di */
1077 COSTS_N_INSNS (36), /* int_div_si */
1078 COSTS_N_INSNS (36), /* int_div_di */
1079 1, /* branch_cost */
1080 4 /* memory_latency */
1081 },
1082 { /* R5400 */
1083 COSTS_N_INSNS (6), /* fp_add */
1084 COSTS_N_INSNS (5), /* fp_mult_sf */
1085 COSTS_N_INSNS (6), /* fp_mult_df */
1086 COSTS_N_INSNS (30), /* fp_div_sf */
1087 COSTS_N_INSNS (59), /* fp_div_df */
1088 COSTS_N_INSNS (3), /* int_mult_si */
1089 COSTS_N_INSNS (4), /* int_mult_di */
1090 COSTS_N_INSNS (42), /* int_div_si */
1091 COSTS_N_INSNS (74), /* int_div_di */
1092 1, /* branch_cost */
1093 4 /* memory_latency */
1094 },
1095 { /* R5500 */
1096 COSTS_N_INSNS (6), /* fp_add */
1097 COSTS_N_INSNS (5), /* fp_mult_sf */
1098 COSTS_N_INSNS (6), /* fp_mult_df */
1099 COSTS_N_INSNS (30), /* fp_div_sf */
1100 COSTS_N_INSNS (59), /* fp_div_df */
1101 COSTS_N_INSNS (5), /* int_mult_si */
1102 COSTS_N_INSNS (9), /* int_mult_di */
1103 COSTS_N_INSNS (42), /* int_div_si */
1104 COSTS_N_INSNS (74), /* int_div_di */
1105 1, /* branch_cost */
1106 4 /* memory_latency */
1107 },
1108 { /* R7000 */
1109 /* The only costs that are changed here are
1110 integer multiplication. */
1111 COSTS_N_INSNS (6), /* fp_add */
1112 COSTS_N_INSNS (7), /* fp_mult_sf */
1113 COSTS_N_INSNS (8), /* fp_mult_df */
1114 COSTS_N_INSNS (23), /* fp_div_sf */
1115 COSTS_N_INSNS (36), /* fp_div_df */
1116 COSTS_N_INSNS (5), /* int_mult_si */
1117 COSTS_N_INSNS (9), /* int_mult_di */
1118 COSTS_N_INSNS (69), /* int_div_si */
1119 COSTS_N_INSNS (69), /* int_div_di */
1120 1, /* branch_cost */
1121 4 /* memory_latency */
1122 },
1123 { /* R8000 */
1124 DEFAULT_COSTS
1125 },
1126 { /* R9000 */
1127 /* The only costs that are changed here are
1128 integer multiplication. */
1129 COSTS_N_INSNS (6), /* fp_add */
1130 COSTS_N_INSNS (7), /* fp_mult_sf */
1131 COSTS_N_INSNS (8), /* fp_mult_df */
1132 COSTS_N_INSNS (23), /* fp_div_sf */
1133 COSTS_N_INSNS (36), /* fp_div_df */
1134 COSTS_N_INSNS (3), /* int_mult_si */
1135 COSTS_N_INSNS (8), /* int_mult_di */
1136 COSTS_N_INSNS (69), /* int_div_si */
1137 COSTS_N_INSNS (69), /* int_div_di */
1138 1, /* branch_cost */
1139 4 /* memory_latency */
1140 },
1141 { /* SB1 */
1142 /* These costs are the same as the SB-1A below. */
1143 COSTS_N_INSNS (4), /* fp_add */
1144 COSTS_N_INSNS (4), /* fp_mult_sf */
1145 COSTS_N_INSNS (4), /* fp_mult_df */
1146 COSTS_N_INSNS (24), /* fp_div_sf */
1147 COSTS_N_INSNS (32), /* fp_div_df */
1148 COSTS_N_INSNS (3), /* int_mult_si */
1149 COSTS_N_INSNS (4), /* int_mult_di */
1150 COSTS_N_INSNS (36), /* int_div_si */
1151 COSTS_N_INSNS (68), /* int_div_di */
1152 1, /* branch_cost */
1153 4 /* memory_latency */
1154 },
1155 { /* SB1-A */
1156 /* These costs are the same as the SB-1 above. */
1157 COSTS_N_INSNS (4), /* fp_add */
1158 COSTS_N_INSNS (4), /* fp_mult_sf */
1159 COSTS_N_INSNS (4), /* fp_mult_df */
1160 COSTS_N_INSNS (24), /* fp_div_sf */
1161 COSTS_N_INSNS (32), /* fp_div_df */
1162 COSTS_N_INSNS (3), /* int_mult_si */
1163 COSTS_N_INSNS (4), /* int_mult_di */
1164 COSTS_N_INSNS (36), /* int_div_si */
1165 COSTS_N_INSNS (68), /* int_div_di */
1166 1, /* branch_cost */
1167 4 /* memory_latency */
1168 },
1169 { /* SR71000 */
1170 DEFAULT_COSTS
1171 },
1172 };
1173
1174 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
1175 mips16e_s2_s8_regs[X], it must also save the registers in indexes
1176 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
1177 static const unsigned char mips16e_s2_s8_regs[] = {
1178 30, 23, 22, 21, 20, 19, 18
1179 };
1180 static const unsigned char mips16e_a0_a3_regs[] = {
1181 4, 5, 6, 7
1182 };
1183
1184 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
1185 ordered from the uppermost in memory to the lowest in memory. */
1186 static const unsigned char mips16e_save_restore_regs[] = {
1187 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
1188 };
1189 \f
1190 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
1191 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
1192 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
1193 #endif
1194 \f
1195 /* Initialize the GCC target structure. */
1196 #undef TARGET_ASM_ALIGNED_HI_OP
1197 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
1198 #undef TARGET_ASM_ALIGNED_SI_OP
1199 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
1200 #undef TARGET_ASM_ALIGNED_DI_OP
1201 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
1202
1203 #undef TARGET_ASM_FUNCTION_PROLOGUE
1204 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
1205 #undef TARGET_ASM_FUNCTION_EPILOGUE
1206 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
1207 #undef TARGET_ASM_SELECT_RTX_SECTION
1208 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
1209 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
1210 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
1211
1212 #undef TARGET_SCHED_REORDER
1213 #define TARGET_SCHED_REORDER mips_sched_reorder
1214 #undef TARGET_SCHED_VARIABLE_ISSUE
1215 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
1216 #undef TARGET_SCHED_ADJUST_COST
1217 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
1218 #undef TARGET_SCHED_ISSUE_RATE
1219 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
1220 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1221 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1222 mips_multipass_dfa_lookahead
1223
1224 #undef TARGET_DEFAULT_TARGET_FLAGS
1225 #define TARGET_DEFAULT_TARGET_FLAGS \
1226 (TARGET_DEFAULT \
1227 | TARGET_CPU_DEFAULT \
1228 | TARGET_ENDIAN_DEFAULT \
1229 | TARGET_FP_EXCEPTIONS_DEFAULT \
1230 | MASK_CHECK_ZERO_DIV \
1231 | MASK_FUSED_MADD)
1232 #undef TARGET_HANDLE_OPTION
1233 #define TARGET_HANDLE_OPTION mips_handle_option
1234
1235 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1236 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
1237
1238 #undef TARGET_VALID_POINTER_MODE
1239 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
1240 #undef TARGET_RTX_COSTS
1241 #define TARGET_RTX_COSTS mips_rtx_costs
1242 #undef TARGET_ADDRESS_COST
1243 #define TARGET_ADDRESS_COST mips_address_cost
1244
1245 #undef TARGET_IN_SMALL_DATA_P
1246 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
1247
1248 #undef TARGET_MACHINE_DEPENDENT_REORG
1249 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
1250
1251 #undef TARGET_ASM_FILE_START
1252 #define TARGET_ASM_FILE_START mips_file_start
1253 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
1254 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
1255
1256 #undef TARGET_INIT_LIBFUNCS
1257 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
1258
1259 #undef TARGET_BUILD_BUILTIN_VA_LIST
1260 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
1261 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1262 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
1263
1264 #undef TARGET_PROMOTE_FUNCTION_ARGS
1265 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1266 #undef TARGET_PROMOTE_FUNCTION_RETURN
1267 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1268 #undef TARGET_PROMOTE_PROTOTYPES
1269 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1270
1271 #undef TARGET_RETURN_IN_MEMORY
1272 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
1273 #undef TARGET_RETURN_IN_MSB
1274 #define TARGET_RETURN_IN_MSB mips_return_in_msb
1275
1276 #undef TARGET_ASM_OUTPUT_MI_THUNK
1277 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
1278 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1279 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1280
1281 #undef TARGET_SETUP_INCOMING_VARARGS
1282 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
1283 #undef TARGET_STRICT_ARGUMENT_NAMING
1284 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
1285 #undef TARGET_MUST_PASS_IN_STACK
1286 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
1287 #undef TARGET_PASS_BY_REFERENCE
1288 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
1289 #undef TARGET_CALLEE_COPIES
1290 #define TARGET_CALLEE_COPIES mips_callee_copies
1291 #undef TARGET_ARG_PARTIAL_BYTES
1292 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
1293
1294 #undef TARGET_MODE_REP_EXTENDED
1295 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
1296
1297 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1298 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
1299
1300 #undef TARGET_INIT_BUILTINS
1301 #define TARGET_INIT_BUILTINS mips_init_builtins
1302 #undef TARGET_EXPAND_BUILTIN
1303 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
1304
1305 #undef TARGET_HAVE_TLS
1306 #define TARGET_HAVE_TLS HAVE_AS_TLS
1307
1308 #undef TARGET_CANNOT_FORCE_CONST_MEM
1309 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
1310
1311 #undef TARGET_ENCODE_SECTION_INFO
1312 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
1313
1314 #undef TARGET_ATTRIBUTE_TABLE
1315 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
1316
1317 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1318 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
1319
1320 #undef TARGET_MIN_ANCHOR_OFFSET
1321 #define TARGET_MIN_ANCHOR_OFFSET -32768
1322 #undef TARGET_MAX_ANCHOR_OFFSET
1323 #define TARGET_MAX_ANCHOR_OFFSET 32767
1324 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1325 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
1326 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
1327 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
1328
1329 #undef TARGET_COMP_TYPE_ATTRIBUTES
1330 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
1331
1332 #ifdef HAVE_AS_DTPRELWORD
1333 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1334 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
1335 #endif
1336
1337 struct gcc_target targetm = TARGET_INITIALIZER;
1338
1339
1340 /* Predicates to test for presence of "near" and "far"/"long_call"
1341 attributes on the given TYPE. */
1342
1343 static bool
1344 mips_near_type_p (tree type)
1345 {
1346 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1347 }
1348
1349 static bool
1350 mips_far_type_p (tree type)
1351 {
1352 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1353 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1354 }
1355
1356
1357 /* Return 0 if the attributes for two types are incompatible, 1 if they
1358 are compatible, and 2 if they are nearly compatible (which causes a
1359 warning to be generated). */
1360
1361 static int
1362 mips_comp_type_attributes (tree type1, tree type2)
1363 {
1364 /* Check for mismatch of non-default calling convention. */
1365 if (TREE_CODE (type1) != FUNCTION_TYPE)
1366 return 1;
1367
1368 /* Disallow mixed near/far attributes. */
1369 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1370 return 0;
1371 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1372 return 0;
1373
1374 return 1;
1375 }
1376 \f
1377 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1378 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1379
1380 static void
1381 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1382 {
1383 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1384 {
1385 *base_ptr = XEXP (x, 0);
1386 *offset_ptr = INTVAL (XEXP (x, 1));
1387 }
1388 else
1389 {
1390 *base_ptr = x;
1391 *offset_ptr = 0;
1392 }
1393 }
1394 \f
1395 /* Return true if SYMBOL_REF X is associated with a global symbol
1396 (in the STB_GLOBAL sense). */
1397
1398 static bool
1399 mips_global_symbol_p (rtx x)
1400 {
1401 tree decl;
1402
1403 decl = SYMBOL_REF_DECL (x);
1404 if (!decl)
1405 return !SYMBOL_REF_LOCAL_P (x);
1406
1407 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1408 or weak symbols. Relocations in the object file will be against
1409 the target symbol, so it's that symbol's binding that matters here. */
1410 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1411 }
1412
1413 /* Return true if SYMBOL_REF X binds locally. */
1414
1415 static bool
1416 mips_symbol_binds_local_p (rtx x)
1417 {
1418 return (SYMBOL_REF_DECL (x)
1419 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1420 : SYMBOL_REF_LOCAL_P (x));
1421 }
1422
1423 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
1424
1425 static enum mips_symbol_type
1426 mips_classify_symbol (rtx x)
1427 {
1428 if (TARGET_RTP_PIC)
1429 return SYMBOL_GOT_DISP;
1430
1431 if (GET_CODE (x) == LABEL_REF)
1432 {
1433 if (TARGET_MIPS16)
1434 return SYMBOL_CONSTANT_POOL;
1435 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1436 return SYMBOL_GOT_PAGE_OFST;
1437 return SYMBOL_GENERAL;
1438 }
1439
1440 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1441
1442 if (SYMBOL_REF_TLS_MODEL (x))
1443 return SYMBOL_TLS;
1444
1445 if (CONSTANT_POOL_ADDRESS_P (x))
1446 {
1447 if (TARGET_MIPS16)
1448 return SYMBOL_CONSTANT_POOL;
1449
1450 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
1451 return SYMBOL_SMALL_DATA;
1452 }
1453
1454 /* Do not use small-data accesses for weak symbols; they may end up
1455 being zero. */
1456 if (SYMBOL_REF_SMALL_P (x)
1457 && !SYMBOL_REF_WEAK (x))
1458 return SYMBOL_SMALL_DATA;
1459
1460 if (TARGET_ABICALLS)
1461 {
1462 /* Don't use GOT accesses for locally-binding symbols; we can use
1463 %hi and %lo instead. */
1464 if (TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x))
1465 return SYMBOL_GENERAL;
1466
1467 /* There are three cases to consider:
1468
1469 - o32 PIC (either with or without explicit relocs)
1470 - n32/n64 PIC without explicit relocs
1471 - n32/n64 PIC with explicit relocs
1472
1473 In the first case, both local and global accesses will use an
1474 R_MIPS_GOT16 relocation. We must correctly predict which of
1475 the two semantics (local or global) the assembler and linker
1476 will apply. The choice depends on the symbol's binding rather
1477 than its visibility.
1478
1479 In the second case, the assembler will not use R_MIPS_GOT16
1480 relocations, but it chooses between local and global accesses
1481 in the same way as for o32 PIC.
1482
1483 In the third case we have more freedom since both forms of
1484 access will work for any kind of symbol. However, there seems
1485 little point in doing things differently. */
1486 if (mips_global_symbol_p (x))
1487 return SYMBOL_GOT_DISP;
1488
1489 return SYMBOL_GOT_PAGE_OFST;
1490 }
1491
1492 return SYMBOL_GENERAL;
1493 }
1494
1495 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1496 is the alignment (in bytes) of SYMBOL_REF X. */
1497
1498 static bool
1499 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1500 {
1501 /* If for some reason we can't get the alignment for the
1502 symbol, initializing this to one means we will only accept
1503 a zero offset. */
1504 HOST_WIDE_INT align = 1;
1505 tree t;
1506
1507 /* Get the alignment of the symbol we're referring to. */
1508 t = SYMBOL_REF_DECL (x);
1509 if (t)
1510 align = DECL_ALIGN_UNIT (t);
1511
1512 return offset >= 0 && offset < align;
1513 }
1514
1515 /* Return true if X is a symbolic constant that can be calculated in
1516 the same way as a bare symbol. If it is, store the type of the
1517 symbol in *SYMBOL_TYPE. */
1518
1519 bool
1520 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
1521 {
1522 rtx offset;
1523
1524 split_const (x, &x, &offset);
1525 if (UNSPEC_ADDRESS_P (x))
1526 {
1527 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1528 x = UNSPEC_ADDRESS (x);
1529 }
1530 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1531 {
1532 *symbol_type = mips_classify_symbol (x);
1533 if (*symbol_type == SYMBOL_TLS)
1534 return false;
1535 }
1536 else
1537 return false;
1538
1539 if (offset == const0_rtx)
1540 return true;
1541
1542 /* Check whether a nonzero offset is valid for the underlying
1543 relocations. */
1544 switch (*symbol_type)
1545 {
1546 case SYMBOL_GENERAL:
1547 case SYMBOL_64_HIGH:
1548 case SYMBOL_64_MID:
1549 case SYMBOL_64_LOW:
1550 /* If the target has 64-bit pointers and the object file only
1551 supports 32-bit symbols, the values of those symbols will be
1552 sign-extended. In this case we can't allow an arbitrary offset
1553 in case the 32-bit value X + OFFSET has a different sign from X. */
1554 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1555 return offset_within_block_p (x, INTVAL (offset));
1556
1557 /* In other cases the relocations can handle any offset. */
1558 return true;
1559
1560 case SYMBOL_CONSTANT_POOL:
1561 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1562 In this case, we no longer have access to the underlying constant,
1563 but the original symbol-based access was known to be valid. */
1564 if (GET_CODE (x) == LABEL_REF)
1565 return true;
1566
1567 /* Fall through. */
1568
1569 case SYMBOL_SMALL_DATA:
1570 /* Make sure that the offset refers to something within the
1571 same object block. This should guarantee that the final
1572 PC- or GP-relative offset is within the 16-bit limit. */
1573 return offset_within_block_p (x, INTVAL (offset));
1574
1575 case SYMBOL_GOT_PAGE_OFST:
1576 case SYMBOL_GOTOFF_PAGE:
1577 /* If the symbol is global, the GOT entry will contain the symbol's
1578 address, and we will apply a 16-bit offset after loading it.
1579 If the symbol is local, the linker should provide enough local
1580 GOT entries for a 16-bit offset, but larger offsets may lead
1581 to GOT overflow. */
1582 return SMALL_INT (offset);
1583
1584 case SYMBOL_TPREL:
1585 case SYMBOL_DTPREL:
1586 /* There is no carry between the HI and LO REL relocations, so the
1587 offset is only valid if we know it won't lead to such a carry. */
1588 return mips_offset_within_alignment_p (x, INTVAL (offset));
1589
1590 case SYMBOL_GOT_DISP:
1591 case SYMBOL_GOTOFF_DISP:
1592 case SYMBOL_GOTOFF_CALL:
1593 case SYMBOL_GOTOFF_LOADGP:
1594 case SYMBOL_TLSGD:
1595 case SYMBOL_TLSLDM:
1596 case SYMBOL_GOTTPREL:
1597 case SYMBOL_TLS:
1598 case SYMBOL_HALF:
1599 return false;
1600 }
1601 gcc_unreachable ();
1602 }
1603
1604
1605 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1606
1607 int
1608 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
1609 {
1610 if (!HARD_REGISTER_NUM_P (regno))
1611 {
1612 if (!strict)
1613 return true;
1614 regno = reg_renumber[regno];
1615 }
1616
1617 /* These fake registers will be eliminated to either the stack or
1618 hard frame pointer, both of which are usually valid base registers.
1619 Reload deals with the cases where the eliminated form isn't valid. */
1620 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1621 return true;
1622
1623 /* In mips16 mode, the stack pointer can only address word and doubleword
1624 values, nothing smaller. There are two problems here:
1625
1626 (a) Instantiating virtual registers can introduce new uses of the
1627 stack pointer. If these virtual registers are valid addresses,
1628 the stack pointer should be too.
1629
1630 (b) Most uses of the stack pointer are not made explicit until
1631 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1632 We don't know until that stage whether we'll be eliminating to the
1633 stack pointer (which needs the restriction) or the hard frame
1634 pointer (which doesn't).
1635
1636 All in all, it seems more consistent to only enforce this restriction
1637 during and after reload. */
1638 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1639 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1640
1641 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1642 }
1643
1644
1645 /* Return true if X is a valid base register for the given mode.
1646 Allow only hard registers if STRICT. */
1647
1648 static bool
1649 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1650 {
1651 if (!strict && GET_CODE (x) == SUBREG)
1652 x = SUBREG_REG (x);
1653
1654 return (REG_P (x)
1655 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1656 }
1657
1658
1659 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1660 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1661
1662 static bool
1663 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1664 enum machine_mode mode)
1665 {
1666 switch (symbol_type)
1667 {
1668 case SYMBOL_GENERAL:
1669 return !TARGET_MIPS16;
1670
1671 case SYMBOL_SMALL_DATA:
1672 return true;
1673
1674 case SYMBOL_CONSTANT_POOL:
1675 /* PC-relative addressing is only available for lw and ld. */
1676 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1677
1678 case SYMBOL_GOT_PAGE_OFST:
1679 return true;
1680
1681 case SYMBOL_GOT_DISP:
1682 /* The address will have to be loaded from the GOT first. */
1683 return false;
1684
1685 case SYMBOL_GOTOFF_PAGE:
1686 case SYMBOL_GOTOFF_DISP:
1687 case SYMBOL_GOTOFF_CALL:
1688 case SYMBOL_GOTOFF_LOADGP:
1689 case SYMBOL_TLS:
1690 case SYMBOL_TLSGD:
1691 case SYMBOL_TLSLDM:
1692 case SYMBOL_DTPREL:
1693 case SYMBOL_GOTTPREL:
1694 case SYMBOL_TPREL:
1695 case SYMBOL_64_HIGH:
1696 case SYMBOL_64_MID:
1697 case SYMBOL_64_LOW:
1698 case SYMBOL_HALF:
1699 return true;
1700 }
1701 gcc_unreachable ();
1702 }
1703
1704
1705 /* Return true if X is a valid address for machine mode MODE. If it is,
1706 fill in INFO appropriately. STRICT is true if we should only accept
1707 hard base registers. */
1708
1709 static bool
1710 mips_classify_address (struct mips_address_info *info, rtx x,
1711 enum machine_mode mode, int strict)
1712 {
1713 switch (GET_CODE (x))
1714 {
1715 case REG:
1716 case SUBREG:
1717 info->type = ADDRESS_REG;
1718 info->reg = x;
1719 info->offset = const0_rtx;
1720 return mips_valid_base_register_p (info->reg, mode, strict);
1721
1722 case PLUS:
1723 info->type = ADDRESS_REG;
1724 info->reg = XEXP (x, 0);
1725 info->offset = XEXP (x, 1);
1726 return (mips_valid_base_register_p (info->reg, mode, strict)
1727 && const_arith_operand (info->offset, VOIDmode));
1728
1729 case LO_SUM:
1730 info->type = ADDRESS_LO_SUM;
1731 info->reg = XEXP (x, 0);
1732 info->offset = XEXP (x, 1);
1733 return (mips_valid_base_register_p (info->reg, mode, strict)
1734 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1735 && mips_symbolic_address_p (info->symbol_type, mode)
1736 && mips_lo_relocs[info->symbol_type] != 0);
1737
1738 case CONST_INT:
1739 /* Small-integer addresses don't occur very often, but they
1740 are legitimate if $0 is a valid base register. */
1741 info->type = ADDRESS_CONST_INT;
1742 return !TARGET_MIPS16 && SMALL_INT (x);
1743
1744 case CONST:
1745 case LABEL_REF:
1746 case SYMBOL_REF:
1747 info->type = ADDRESS_SYMBOLIC;
1748 return (mips_symbolic_constant_p (x, &info->symbol_type)
1749 && mips_symbolic_address_p (info->symbol_type, mode)
1750 && !mips_split_p[info->symbol_type]);
1751
1752 default:
1753 return false;
1754 }
1755 }
1756
1757 /* Return true if X is a thread-local symbol. */
1758
1759 static bool
1760 mips_tls_operand_p (rtx x)
1761 {
1762 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1763 }
1764
1765 /* Return true if X can not be forced into a constant pool. */
1766
1767 static int
1768 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1769 {
1770 return mips_tls_operand_p (*x);
1771 }
1772
1773 /* Return true if X can not be forced into a constant pool. */
1774
1775 static bool
1776 mips_cannot_force_const_mem (rtx x)
1777 {
1778 rtx base, offset;
1779
1780 if (!TARGET_MIPS16)
1781 {
1782 /* As an optimization, reject constants that mips_legitimize_move
1783 can expand inline.
1784
1785 Suppose we have a multi-instruction sequence that loads constant C
1786 into register R. If R does not get allocated a hard register, and
1787 R is used in an operand that allows both registers and memory
1788 references, reload will consider forcing C into memory and using
1789 one of the instruction's memory alternatives. Returning false
1790 here will force it to use an input reload instead. */
1791 if (GET_CODE (x) == CONST_INT)
1792 return true;
1793
1794 split_const (x, &base, &offset);
1795 if (symbolic_operand (base, VOIDmode) && SMALL_INT (offset))
1796 return true;
1797 }
1798
1799 if (TARGET_HAVE_TLS && for_each_rtx (&x, &mips_tls_symbol_ref_1, 0))
1800 return true;
1801
1802 return false;
1803 }
1804
1805 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. MIPS16 uses per-function
1806 constant pools, but normal-mode code doesn't need to. */
1807
1808 static bool
1809 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1810 rtx x ATTRIBUTE_UNUSED)
1811 {
1812 return !TARGET_MIPS16;
1813 }
1814 \f
1815 /* Return the number of instructions needed to load a symbol of the
1816 given type into a register. If valid in an address, the same number
1817 of instructions are needed for loads and stores. Treat extended
1818 mips16 instructions as two instructions. */
1819
1820 static int
1821 mips_symbol_insns (enum mips_symbol_type type)
1822 {
1823 switch (type)
1824 {
1825 case SYMBOL_GENERAL:
1826 /* In mips16 code, general symbols must be fetched from the
1827 constant pool. */
1828 if (TARGET_MIPS16)
1829 return 0;
1830
1831 /* When using 64-bit symbols, we need 5 preparatory instructions,
1832 such as:
1833
1834 lui $at,%highest(symbol)
1835 daddiu $at,$at,%higher(symbol)
1836 dsll $at,$at,16
1837 daddiu $at,$at,%hi(symbol)
1838 dsll $at,$at,16
1839
1840 The final address is then $at + %lo(symbol). With 32-bit
1841 symbols we just need a preparatory lui. */
1842 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1843
1844 case SYMBOL_SMALL_DATA:
1845 case SYMBOL_HALF:
1846 return 1;
1847
1848 case SYMBOL_CONSTANT_POOL:
1849 /* This case is for mips16 only. Assume we'll need an
1850 extended instruction. */
1851 return 2;
1852
1853 case SYMBOL_GOT_PAGE_OFST:
1854 case SYMBOL_GOT_DISP:
1855 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1856 the local/global classification is accurate. See override_options
1857 for details.
1858
1859 The worst cases are:
1860
1861 (1) For local symbols when generating o32 or o64 code. The assembler
1862 will use:
1863
1864 lw $at,%got(symbol)
1865 nop
1866
1867 ...and the final address will be $at + %lo(symbol).
1868
1869 (2) For global symbols when -mxgot. The assembler will use:
1870
1871 lui $at,%got_hi(symbol)
1872 (d)addu $at,$at,$gp
1873
1874 ...and the final address will be $at + %got_lo(symbol). */
1875 return 3;
1876
1877 case SYMBOL_GOTOFF_PAGE:
1878 case SYMBOL_GOTOFF_DISP:
1879 case SYMBOL_GOTOFF_CALL:
1880 case SYMBOL_GOTOFF_LOADGP:
1881 case SYMBOL_64_HIGH:
1882 case SYMBOL_64_MID:
1883 case SYMBOL_64_LOW:
1884 case SYMBOL_TLSGD:
1885 case SYMBOL_TLSLDM:
1886 case SYMBOL_DTPREL:
1887 case SYMBOL_GOTTPREL:
1888 case SYMBOL_TPREL:
1889 /* Check whether the offset is a 16- or 32-bit value. */
1890 return mips_split_p[type] ? 2 : 1;
1891
1892 case SYMBOL_TLS:
1893 /* We don't treat a bare TLS symbol as a constant. */
1894 return 0;
1895 }
1896 gcc_unreachable ();
1897 }
1898
1899 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1900
1901 bool
1902 mips_stack_address_p (rtx x, enum machine_mode mode)
1903 {
1904 struct mips_address_info addr;
1905
1906 return (mips_classify_address (&addr, x, mode, false)
1907 && addr.type == ADDRESS_REG
1908 && addr.reg == stack_pointer_rtx);
1909 }
1910
1911 /* Return true if a value at OFFSET bytes from BASE can be accessed
1912 using an unextended mips16 instruction. MODE is the mode of the
1913 value.
1914
1915 Usually the offset in an unextended instruction is a 5-bit field.
1916 The offset is unsigned and shifted left once for HIs, twice
1917 for SIs, and so on. An exception is SImode accesses off the
1918 stack pointer, which have an 8-bit immediate field. */
1919
1920 static bool
1921 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1922 {
1923 if (TARGET_MIPS16
1924 && GET_CODE (offset) == CONST_INT
1925 && INTVAL (offset) >= 0
1926 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1927 {
1928 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1929 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1930 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1931 }
1932 return false;
1933 }
1934
1935
1936 /* Return the number of instructions needed to load or store a value
1937 of mode MODE at X. Return 0 if X isn't valid for MODE.
1938
1939 For mips16 code, count extended instructions as two instructions. */
1940
1941 int
1942 mips_address_insns (rtx x, enum machine_mode mode)
1943 {
1944 struct mips_address_info addr;
1945 int factor;
1946
1947 if (mode == BLKmode)
1948 /* BLKmode is used for single unaligned loads and stores. */
1949 factor = 1;
1950 else
1951 /* Each word of a multi-word value will be accessed individually. */
1952 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1953
1954 if (mips_classify_address (&addr, x, mode, false))
1955 switch (addr.type)
1956 {
1957 case ADDRESS_REG:
1958 if (TARGET_MIPS16
1959 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1960 return factor * 2;
1961 return factor;
1962
1963 case ADDRESS_LO_SUM:
1964 return (TARGET_MIPS16 ? factor * 2 : factor);
1965
1966 case ADDRESS_CONST_INT:
1967 return factor;
1968
1969 case ADDRESS_SYMBOLIC:
1970 return factor * mips_symbol_insns (addr.symbol_type);
1971 }
1972 return 0;
1973 }
1974
1975
1976 /* Likewise for constant X. */
1977
1978 int
1979 mips_const_insns (rtx x)
1980 {
1981 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1982 enum mips_symbol_type symbol_type;
1983 rtx offset;
1984
1985 switch (GET_CODE (x))
1986 {
1987 case HIGH:
1988 if (TARGET_MIPS16
1989 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1990 || !mips_split_p[symbol_type])
1991 return 0;
1992
1993 return 1;
1994
1995 case CONST_INT:
1996 if (TARGET_MIPS16)
1997 /* Unsigned 8-bit constants can be loaded using an unextended
1998 LI instruction. Unsigned 16-bit constants can be loaded
1999 using an extended LI. Negative constants must be loaded
2000 using LI and then negated. */
2001 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
2002 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2003 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
2004 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2005 : 0);
2006
2007 return mips_build_integer (codes, INTVAL (x));
2008
2009 case CONST_DOUBLE:
2010 case CONST_VECTOR:
2011 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
2012
2013 case CONST:
2014 if (CONST_GP_P (x))
2015 return 1;
2016
2017 /* See if we can refer to X directly. */
2018 if (mips_symbolic_constant_p (x, &symbol_type))
2019 return mips_symbol_insns (symbol_type);
2020
2021 /* Otherwise try splitting the constant into a base and offset.
2022 16-bit offsets can be added using an extra addiu. Larger offsets
2023 must be calculated separately and then added to the base. */
2024 split_const (x, &x, &offset);
2025 if (offset != 0)
2026 {
2027 int n = mips_const_insns (x);
2028 if (n != 0)
2029 {
2030 if (SMALL_INT (offset))
2031 return n + 1;
2032 else
2033 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2034 }
2035 }
2036 return 0;
2037
2038 case SYMBOL_REF:
2039 case LABEL_REF:
2040 return mips_symbol_insns (mips_classify_symbol (x));
2041
2042 default:
2043 return 0;
2044 }
2045 }
2046
2047
2048 /* Return the number of instructions needed for memory reference X.
2049 Count extended mips16 instructions as two instructions. */
2050
2051 int
2052 mips_fetch_insns (rtx x)
2053 {
2054 gcc_assert (MEM_P (x));
2055 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
2056 }
2057
2058
2059 /* Return the number of instructions needed for an integer division. */
2060
2061 int
2062 mips_idiv_insns (void)
2063 {
2064 int count;
2065
2066 count = 1;
2067 if (TARGET_CHECK_ZERO_DIV)
2068 {
2069 if (GENERATE_DIVIDE_TRAPS)
2070 count++;
2071 else
2072 count += 2;
2073 }
2074
2075 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2076 count++;
2077 return count;
2078 }
2079 \f
2080 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
2081 returns a nonzero value if X is a legitimate address for a memory
2082 operand of the indicated MODE. STRICT is nonzero if this function
2083 is called during reload. */
2084
2085 bool
2086 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
2087 {
2088 struct mips_address_info addr;
2089
2090 return mips_classify_address (&addr, x, mode, strict);
2091 }
2092
2093
2094 /* Copy VALUE to a register and return that register. If new psuedos
2095 are allowed, copy it into a new register, otherwise use DEST. */
2096
2097 static rtx
2098 mips_force_temporary (rtx dest, rtx value)
2099 {
2100 if (!no_new_pseudos)
2101 return force_reg (Pmode, value);
2102 else
2103 {
2104 emit_move_insn (copy_rtx (dest), value);
2105 return dest;
2106 }
2107 }
2108
2109
2110 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
2111 and is used to load the high part into a register. */
2112
2113 rtx
2114 mips_split_symbol (rtx temp, rtx addr)
2115 {
2116 rtx high;
2117
2118 if (!TARGET_MIPS16)
2119 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
2120 else if (no_new_pseudos)
2121 {
2122 emit_insn (gen_load_const_gp (copy_rtx (temp)));
2123 high = temp;
2124 }
2125 else
2126 high = mips16_gp_pseudo_reg ();
2127 return gen_rtx_LO_SUM (Pmode, high, addr);
2128 }
2129
2130
2131 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2132 type SYMBOL_TYPE. */
2133
2134 rtx
2135 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2136 {
2137 rtx base, offset;
2138
2139 split_const (address, &base, &offset);
2140 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2141 UNSPEC_ADDRESS_FIRST + symbol_type);
2142 if (offset != const0_rtx)
2143 base = gen_rtx_PLUS (Pmode, base, offset);
2144 return gen_rtx_CONST (Pmode, base);
2145 }
2146
2147
2148 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2149 high part to BASE and return the result. Just return BASE otherwise.
2150 TEMP is available as a temporary register if needed.
2151
2152 The returned expression can be used as the first operand to a LO_SUM. */
2153
2154 static rtx
2155 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2156 enum mips_symbol_type symbol_type)
2157 {
2158 if (mips_split_p[symbol_type])
2159 {
2160 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2161 addr = mips_force_temporary (temp, addr);
2162 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2163 }
2164 return base;
2165 }
2166
2167
2168 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2169 mips_force_temporary; it is only needed when OFFSET is not a
2170 SMALL_OPERAND. */
2171
2172 static rtx
2173 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2174 {
2175 if (!SMALL_OPERAND (offset))
2176 {
2177 rtx high;
2178 if (TARGET_MIPS16)
2179 {
2180 /* Load the full offset into a register so that we can use
2181 an unextended instruction for the address itself. */
2182 high = GEN_INT (offset);
2183 offset = 0;
2184 }
2185 else
2186 {
2187 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
2188 high = GEN_INT (CONST_HIGH_PART (offset));
2189 offset = CONST_LOW_PART (offset);
2190 }
2191 high = mips_force_temporary (temp, high);
2192 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2193 }
2194 return plus_constant (reg, offset);
2195 }
2196
2197 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
2198 referencing, and TYPE is the symbol type to use (either global
2199 dynamic or local dynamic). V0 is an RTX for the return value
2200 location. The entire insn sequence is returned. */
2201
2202 static GTY(()) rtx mips_tls_symbol;
2203
2204 static rtx
2205 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2206 {
2207 rtx insn, loc, tga, a0;
2208
2209 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2210
2211 if (!mips_tls_symbol)
2212 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2213
2214 loc = mips_unspec_address (sym, type);
2215
2216 start_sequence ();
2217
2218 emit_insn (gen_rtx_SET (Pmode, a0,
2219 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2220 tga = gen_rtx_MEM (Pmode, mips_tls_symbol);
2221 insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
2222 CONST_OR_PURE_CALL_P (insn) = 1;
2223 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), v0);
2224 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2225 insn = get_insns ();
2226
2227 end_sequence ();
2228
2229 return insn;
2230 }
2231
2232 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
2233 return value will be a valid address and move_operand (either a REG
2234 or a LO_SUM). */
2235
2236 static rtx
2237 mips_legitimize_tls_address (rtx loc)
2238 {
2239 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
2240 enum tls_model model;
2241
2242 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2243 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
2244
2245 model = SYMBOL_REF_TLS_MODEL (loc);
2246 /* Only TARGET_ABICALLS code can have more than one module; other
2247 code must be be static and should not use a GOT. All TLS models
2248 reduce to local exec in this situation. */
2249 if (!TARGET_ABICALLS)
2250 model = TLS_MODEL_LOCAL_EXEC;
2251
2252 switch (model)
2253 {
2254 case TLS_MODEL_GLOBAL_DYNAMIC:
2255 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2256 dest = gen_reg_rtx (Pmode);
2257 emit_libcall_block (insn, dest, v0, loc);
2258 break;
2259
2260 case TLS_MODEL_LOCAL_DYNAMIC:
2261 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2262 tmp1 = gen_reg_rtx (Pmode);
2263
2264 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2265 share the LDM result with other LD model accesses. */
2266 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2267 UNSPEC_TLS_LDM);
2268 emit_libcall_block (insn, tmp1, v0, eqv);
2269
2270 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2271 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2272 mips_unspec_address (loc, SYMBOL_DTPREL));
2273 break;
2274
2275 case TLS_MODEL_INITIAL_EXEC:
2276 tmp1 = gen_reg_rtx (Pmode);
2277 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2278 if (Pmode == DImode)
2279 {
2280 emit_insn (gen_tls_get_tp_di (v1));
2281 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2282 }
2283 else
2284 {
2285 emit_insn (gen_tls_get_tp_si (v1));
2286 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2287 }
2288 dest = gen_reg_rtx (Pmode);
2289 emit_insn (gen_add3_insn (dest, tmp1, v1));
2290 break;
2291
2292 case TLS_MODEL_LOCAL_EXEC:
2293 if (Pmode == DImode)
2294 emit_insn (gen_tls_get_tp_di (v1));
2295 else
2296 emit_insn (gen_tls_get_tp_si (v1));
2297
2298 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
2299 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2300 mips_unspec_address (loc, SYMBOL_TPREL));
2301 break;
2302
2303 default:
2304 gcc_unreachable ();
2305 }
2306
2307 return dest;
2308 }
2309
2310 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2311 be legitimized in a way that the generic machinery might not expect,
2312 put the new address in *XLOC and return true. MODE is the mode of
2313 the memory being accessed. */
2314
2315 bool
2316 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2317 {
2318 enum mips_symbol_type symbol_type;
2319
2320 if (mips_tls_operand_p (*xloc))
2321 {
2322 *xloc = mips_legitimize_tls_address (*xloc);
2323 return true;
2324 }
2325
2326 /* See if the address can split into a high part and a LO_SUM. */
2327 if (mips_symbolic_constant_p (*xloc, &symbol_type)
2328 && mips_symbolic_address_p (symbol_type, mode)
2329 && mips_split_p[symbol_type])
2330 {
2331 *xloc = mips_split_symbol (0, *xloc);
2332 return true;
2333 }
2334
2335 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
2336 {
2337 /* Handle REG + CONSTANT using mips_add_offset. */
2338 rtx reg;
2339
2340 reg = XEXP (*xloc, 0);
2341 if (!mips_valid_base_register_p (reg, mode, 0))
2342 reg = copy_to_mode_reg (Pmode, reg);
2343 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
2344 return true;
2345 }
2346
2347 return false;
2348 }
2349
2350
2351 /* Subroutine of mips_build_integer (with the same interface).
2352 Assume that the final action in the sequence should be a left shift. */
2353
2354 static unsigned int
2355 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
2356 {
2357 unsigned int i, shift;
2358
2359 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
2360 since signed numbers are easier to load than unsigned ones. */
2361 shift = 0;
2362 while ((value & 1) == 0)
2363 value /= 2, shift++;
2364
2365 i = mips_build_integer (codes, value);
2366 codes[i].code = ASHIFT;
2367 codes[i].value = shift;
2368 return i + 1;
2369 }
2370
2371
2372 /* As for mips_build_shift, but assume that the final action will be
2373 an IOR or PLUS operation. */
2374
2375 static unsigned int
2376 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
2377 {
2378 unsigned HOST_WIDE_INT high;
2379 unsigned int i;
2380
2381 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
2382 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
2383 {
2384 /* The constant is too complex to load with a simple lui/ori pair
2385 so our goal is to clear as many trailing zeros as possible.
2386 In this case, we know bit 16 is set and that the low 16 bits
2387 form a negative number. If we subtract that number from VALUE,
2388 we will clear at least the lowest 17 bits, maybe more. */
2389 i = mips_build_integer (codes, CONST_HIGH_PART (value));
2390 codes[i].code = PLUS;
2391 codes[i].value = CONST_LOW_PART (value);
2392 }
2393 else
2394 {
2395 i = mips_build_integer (codes, high);
2396 codes[i].code = IOR;
2397 codes[i].value = value & 0xffff;
2398 }
2399 return i + 1;
2400 }
2401
2402
2403 /* Fill CODES with a sequence of rtl operations to load VALUE.
2404 Return the number of operations needed. */
2405
2406 static unsigned int
2407 mips_build_integer (struct mips_integer_op *codes,
2408 unsigned HOST_WIDE_INT value)
2409 {
2410 if (SMALL_OPERAND (value)
2411 || SMALL_OPERAND_UNSIGNED (value)
2412 || LUI_OPERAND (value))
2413 {
2414 /* The value can be loaded with a single instruction. */
2415 codes[0].code = UNKNOWN;
2416 codes[0].value = value;
2417 return 1;
2418 }
2419 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
2420 {
2421 /* Either the constant is a simple LUI/ORI combination or its
2422 lowest bit is set. We don't want to shift in this case. */
2423 return mips_build_lower (codes, value);
2424 }
2425 else if ((value & 0xffff) == 0)
2426 {
2427 /* The constant will need at least three actions. The lowest
2428 16 bits are clear, so the final action will be a shift. */
2429 return mips_build_shift (codes, value);
2430 }
2431 else
2432 {
2433 /* The final action could be a shift, add or inclusive OR.
2434 Rather than use a complex condition to select the best
2435 approach, try both mips_build_shift and mips_build_lower
2436 and pick the one that gives the shortest sequence.
2437 Note that this case is only used once per constant. */
2438 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
2439 unsigned int cost, alt_cost;
2440
2441 cost = mips_build_shift (codes, value);
2442 alt_cost = mips_build_lower (alt_codes, value);
2443 if (alt_cost < cost)
2444 {
2445 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
2446 cost = alt_cost;
2447 }
2448 return cost;
2449 }
2450 }
2451
2452
2453 /* Load VALUE into DEST, using TEMP as a temporary register if need be. */
2454
2455 void
2456 mips_move_integer (rtx dest, rtx temp, unsigned HOST_WIDE_INT value)
2457 {
2458 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2459 enum machine_mode mode;
2460 unsigned int i, cost;
2461 rtx x;
2462
2463 mode = GET_MODE (dest);
2464 cost = mips_build_integer (codes, value);
2465
2466 /* Apply each binary operation to X. Invariant: X is a legitimate
2467 source operand for a SET pattern. */
2468 x = GEN_INT (codes[0].value);
2469 for (i = 1; i < cost; i++)
2470 {
2471 if (no_new_pseudos)
2472 {
2473 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2474 x = temp;
2475 }
2476 else
2477 x = force_reg (mode, x);
2478 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2479 }
2480
2481 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2482 }
2483
2484
2485 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2486 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2487 move_operand. */
2488
2489 static void
2490 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2491 {
2492 rtx base, offset;
2493
2494 /* Split moves of big integers into smaller pieces. */
2495 if (splittable_const_int_operand (src, mode))
2496 {
2497 mips_move_integer (dest, dest, INTVAL (src));
2498 return;
2499 }
2500
2501 /* Split moves of symbolic constants into high/low pairs. */
2502 if (splittable_symbolic_operand (src, mode))
2503 {
2504 emit_insn (gen_rtx_SET (VOIDmode, dest, mips_split_symbol (dest, src)));
2505 return;
2506 }
2507
2508 if (mips_tls_operand_p (src))
2509 {
2510 emit_move_insn (dest, mips_legitimize_tls_address (src));
2511 return;
2512 }
2513
2514 /* If we have (const (plus symbol offset)), load the symbol first
2515 and then add in the offset. This is usually better than forcing
2516 the constant into memory, at least in non-mips16 code. */
2517 split_const (src, &base, &offset);
2518 if (!TARGET_MIPS16
2519 && offset != const0_rtx
2520 && (!no_new_pseudos || SMALL_INT (offset)))
2521 {
2522 base = mips_force_temporary (dest, base);
2523 emit_move_insn (dest, mips_add_offset (0, base, INTVAL (offset)));
2524 return;
2525 }
2526
2527 src = force_const_mem (mode, src);
2528
2529 /* When using explicit relocs, constant pool references are sometimes
2530 not legitimate addresses. */
2531 if (!memory_operand (src, VOIDmode))
2532 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
2533 emit_move_insn (dest, src);
2534 }
2535
2536
2537 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2538 sequence that is valid. */
2539
2540 bool
2541 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2542 {
2543 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2544 {
2545 emit_move_insn (dest, force_reg (mode, src));
2546 return true;
2547 }
2548
2549 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2550 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2551 && REG_P (src) && MD_REG_P (REGNO (src))
2552 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2553 {
2554 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2555 if (GET_MODE_SIZE (mode) <= 4)
2556 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2557 gen_rtx_REG (SImode, REGNO (src)),
2558 gen_rtx_REG (SImode, other_regno)));
2559 else
2560 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2561 gen_rtx_REG (DImode, REGNO (src)),
2562 gen_rtx_REG (DImode, other_regno)));
2563 return true;
2564 }
2565
2566 /* We need to deal with constants that would be legitimate
2567 immediate_operands but not legitimate move_operands. */
2568 if (CONSTANT_P (src) && !move_operand (src, mode))
2569 {
2570 mips_legitimize_const_move (mode, dest, src);
2571 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2572 return true;
2573 }
2574 return false;
2575 }
2576 \f
2577 /* We need a lot of little routines to check constant values on the
2578 mips16. These are used to figure out how long the instruction will
2579 be. It would be much better to do this using constraints, but
2580 there aren't nearly enough letters available. */
2581
2582 static int
2583 m16_check_op (rtx op, int low, int high, int mask)
2584 {
2585 return (GET_CODE (op) == CONST_INT
2586 && INTVAL (op) >= low
2587 && INTVAL (op) <= high
2588 && (INTVAL (op) & mask) == 0);
2589 }
2590
2591 int
2592 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2593 {
2594 return m16_check_op (op, 0x1, 0x8, 0);
2595 }
2596
2597 int
2598 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2599 {
2600 return m16_check_op (op, - 0x8, 0x7, 0);
2601 }
2602
2603 int
2604 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2605 {
2606 return m16_check_op (op, - 0x7, 0x8, 0);
2607 }
2608
2609 int
2610 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2611 {
2612 return m16_check_op (op, - 0x10, 0xf, 0);
2613 }
2614
2615 int
2616 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2617 {
2618 return m16_check_op (op, - 0xf, 0x10, 0);
2619 }
2620
2621 int
2622 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2623 {
2624 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2625 }
2626
2627 int
2628 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2629 {
2630 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2631 }
2632
2633 int
2634 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2635 {
2636 return m16_check_op (op, - 0x80, 0x7f, 0);
2637 }
2638
2639 int
2640 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2641 {
2642 return m16_check_op (op, - 0x7f, 0x80, 0);
2643 }
2644
2645 int
2646 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2647 {
2648 return m16_check_op (op, 0x0, 0xff, 0);
2649 }
2650
2651 int
2652 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2653 {
2654 return m16_check_op (op, - 0xff, 0x0, 0);
2655 }
2656
2657 int
2658 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2659 {
2660 return m16_check_op (op, - 0x1, 0xfe, 0);
2661 }
2662
2663 int
2664 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2665 {
2666 return m16_check_op (op, 0x0, 0xff << 2, 3);
2667 }
2668
2669 int
2670 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2671 {
2672 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2673 }
2674
2675 int
2676 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2677 {
2678 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2679 }
2680
2681 int
2682 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2683 {
2684 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2685 }
2686 \f
2687 /* Return true if ADDR matches the pattern for the lwxs load scaled indexed
2688 address instruction. */
2689
2690 static bool
2691 mips_lwxs_address_p (rtx addr)
2692 {
2693 if (ISA_HAS_LWXS
2694 && GET_CODE (addr) == PLUS
2695 && REG_P (XEXP (addr, 1)))
2696 {
2697 rtx offset = XEXP (addr, 0);
2698 if (GET_CODE (offset) == MULT
2699 && REG_P (XEXP (offset, 0))
2700 && GET_CODE (XEXP (offset, 1)) == CONST_INT
2701 && INTVAL (XEXP (offset, 1)) == 4)
2702 return true;
2703 }
2704 return false;
2705 }
2706
2707 static bool
2708 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2709 {
2710 enum machine_mode mode = GET_MODE (x);
2711 bool float_mode_p = FLOAT_MODE_P (mode);
2712
2713 switch (code)
2714 {
2715 case CONST_INT:
2716 if (TARGET_MIPS16)
2717 {
2718 /* A number between 1 and 8 inclusive is efficient for a shift.
2719 Otherwise, we will need an extended instruction. */
2720 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2721 || (outer_code) == LSHIFTRT)
2722 {
2723 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2724 *total = 0;
2725 else
2726 *total = COSTS_N_INSNS (1);
2727 return true;
2728 }
2729
2730 /* We can use cmpi for an xor with an unsigned 16-bit value. */
2731 if ((outer_code) == XOR
2732 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2733 {
2734 *total = 0;
2735 return true;
2736 }
2737
2738 /* We may be able to use slt or sltu for a comparison with a
2739 signed 16-bit value. (The boundary conditions aren't quite
2740 right, but this is just a heuristic anyhow.) */
2741 if (((outer_code) == LT || (outer_code) == LE
2742 || (outer_code) == GE || (outer_code) == GT
2743 || (outer_code) == LTU || (outer_code) == LEU
2744 || (outer_code) == GEU || (outer_code) == GTU)
2745 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2746 {
2747 *total = 0;
2748 return true;
2749 }
2750
2751 /* Equality comparisons with 0 are cheap. */
2752 if (((outer_code) == EQ || (outer_code) == NE)
2753 && INTVAL (x) == 0)
2754 {
2755 *total = 0;
2756 return true;
2757 }
2758
2759 /* Constants in the range 0...255 can be loaded with an unextended
2760 instruction. They are therefore as cheap as a register move.
2761
2762 Given the choice between "li R1,0...255" and "move R1,R2"
2763 (where R2 is a known constant), it is usually better to use "li",
2764 since we do not want to unnecessarily extend the lifetime
2765 of R2. */
2766 if (outer_code == SET
2767 && INTVAL (x) >= 0
2768 && INTVAL (x) < 256)
2769 {
2770 *total = 0;
2771 return true;
2772 }
2773 }
2774 else
2775 {
2776 /* These can be used anywhere. */
2777 *total = 0;
2778 return true;
2779 }
2780
2781 /* Otherwise fall through to the handling below because
2782 we'll need to construct the constant. */
2783
2784 case CONST:
2785 case SYMBOL_REF:
2786 case LABEL_REF:
2787 case CONST_DOUBLE:
2788 if (LEGITIMATE_CONSTANT_P (x))
2789 {
2790 *total = COSTS_N_INSNS (1);
2791 return true;
2792 }
2793 else
2794 {
2795 /* The value will need to be fetched from the constant pool. */
2796 *total = CONSTANT_POOL_COST;
2797 return true;
2798 }
2799
2800 case MEM:
2801 {
2802 /* If the address is legitimate, return the number of
2803 instructions it needs. */
2804 rtx addr = XEXP (x, 0);
2805 int n = mips_address_insns (addr, GET_MODE (x));
2806 if (n > 0)
2807 {
2808 *total = COSTS_N_INSNS (n + 1);
2809 return true;
2810 }
2811 /* Check for scaled indexed address. */
2812 if (mips_lwxs_address_p (addr))
2813 {
2814 *total = COSTS_N_INSNS (2);
2815 return true;
2816 }
2817 /* Otherwise use the default handling. */
2818 return false;
2819 }
2820
2821 case FFS:
2822 *total = COSTS_N_INSNS (6);
2823 return true;
2824
2825 case NOT:
2826 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2827 return true;
2828
2829 case AND:
2830 case IOR:
2831 case XOR:
2832 if (mode == DImode && !TARGET_64BIT)
2833 {
2834 *total = COSTS_N_INSNS (2);
2835 return true;
2836 }
2837 return false;
2838
2839 case ASHIFT:
2840 case ASHIFTRT:
2841 case LSHIFTRT:
2842 if (mode == DImode && !TARGET_64BIT)
2843 {
2844 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2845 ? 4 : 12);
2846 return true;
2847 }
2848 return false;
2849
2850 case ABS:
2851 if (float_mode_p)
2852 *total = COSTS_N_INSNS (1);
2853 else
2854 *total = COSTS_N_INSNS (4);
2855 return true;
2856
2857 case LO_SUM:
2858 *total = COSTS_N_INSNS (1);
2859 return true;
2860
2861 case PLUS:
2862 case MINUS:
2863 if (float_mode_p)
2864 {
2865 *total = mips_cost->fp_add;
2866 return true;
2867 }
2868
2869 else if (mode == DImode && !TARGET_64BIT)
2870 {
2871 *total = COSTS_N_INSNS (4);
2872 return true;
2873 }
2874 return false;
2875
2876 case NEG:
2877 if (mode == DImode && !TARGET_64BIT)
2878 {
2879 *total = COSTS_N_INSNS (4);
2880 return true;
2881 }
2882 return false;
2883
2884 case MULT:
2885 if (mode == SFmode)
2886 *total = mips_cost->fp_mult_sf;
2887
2888 else if (mode == DFmode)
2889 *total = mips_cost->fp_mult_df;
2890
2891 else if (mode == SImode)
2892 *total = mips_cost->int_mult_si;
2893
2894 else
2895 *total = mips_cost->int_mult_di;
2896
2897 return true;
2898
2899 case DIV:
2900 case MOD:
2901 if (float_mode_p)
2902 {
2903 if (mode == SFmode)
2904 *total = mips_cost->fp_div_sf;
2905 else
2906 *total = mips_cost->fp_div_df;
2907
2908 return true;
2909 }
2910 /* Fall through. */
2911
2912 case UDIV:
2913 case UMOD:
2914 if (mode == DImode)
2915 *total = mips_cost->int_div_di;
2916 else
2917 *total = mips_cost->int_div_si;
2918
2919 return true;
2920
2921 case SIGN_EXTEND:
2922 /* A sign extend from SImode to DImode in 64-bit mode is often
2923 zero instructions, because the result can often be used
2924 directly by another instruction; we'll call it one. */
2925 if (TARGET_64BIT && mode == DImode
2926 && GET_MODE (XEXP (x, 0)) == SImode)
2927 *total = COSTS_N_INSNS (1);
2928 else
2929 *total = COSTS_N_INSNS (2);
2930 return true;
2931
2932 case ZERO_EXTEND:
2933 if (TARGET_64BIT && mode == DImode
2934 && GET_MODE (XEXP (x, 0)) == SImode)
2935 *total = COSTS_N_INSNS (2);
2936 else
2937 *total = COSTS_N_INSNS (1);
2938 return true;
2939
2940 case FLOAT:
2941 case UNSIGNED_FLOAT:
2942 case FIX:
2943 case FLOAT_EXTEND:
2944 case FLOAT_TRUNCATE:
2945 case SQRT:
2946 *total = mips_cost->fp_add;
2947 return true;
2948
2949 default:
2950 return false;
2951 }
2952 }
2953
2954 /* Provide the costs of an addressing mode that contains ADDR.
2955 If ADDR is not a valid address, its cost is irrelevant. */
2956
2957 static int
2958 mips_address_cost (rtx addr)
2959 {
2960 return mips_address_insns (addr, SImode);
2961 }
2962 \f
2963 /* Return one word of double-word value OP, taking into account the fixed
2964 endianness of certain registers. HIGH_P is true to select the high part,
2965 false to select the low part. */
2966
2967 rtx
2968 mips_subword (rtx op, int high_p)
2969 {
2970 unsigned int byte;
2971 enum machine_mode mode;
2972
2973 mode = GET_MODE (op);
2974 if (mode == VOIDmode)
2975 mode = DImode;
2976
2977 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2978 byte = UNITS_PER_WORD;
2979 else
2980 byte = 0;
2981
2982 if (REG_P (op))
2983 {
2984 if (FP_REG_P (REGNO (op)))
2985 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2986 if (ACC_HI_REG_P (REGNO (op)))
2987 return gen_rtx_REG (word_mode, high_p ? REGNO (op) : REGNO (op) + 1);
2988 }
2989
2990 if (MEM_P (op))
2991 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2992
2993 return simplify_gen_subreg (word_mode, op, mode, byte);
2994 }
2995
2996
2997 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2998
2999 bool
3000 mips_split_64bit_move_p (rtx dest, rtx src)
3001 {
3002 if (TARGET_64BIT)
3003 return false;
3004
3005 /* FP->FP moves can be done in a single instruction. */
3006 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
3007 return false;
3008
3009 /* Check for floating-point loads and stores. They can be done using
3010 ldc1 and sdc1 on MIPS II and above. */
3011 if (mips_isa > 1)
3012 {
3013 if (FP_REG_RTX_P (dest) && MEM_P (src))
3014 return false;
3015 if (FP_REG_RTX_P (src) && MEM_P (dest))
3016 return false;
3017 }
3018 return true;
3019 }
3020
3021
3022 /* Split a 64-bit move from SRC to DEST assuming that
3023 mips_split_64bit_move_p holds.
3024
3025 Moves into and out of FPRs cause some difficulty here. Such moves
3026 will always be DFmode, since paired FPRs are not allowed to store
3027 DImode values. The most natural representation would be two separate
3028 32-bit moves, such as:
3029
3030 (set (reg:SI $f0) (mem:SI ...))
3031 (set (reg:SI $f1) (mem:SI ...))
3032
3033 However, the second insn is invalid because odd-numbered FPRs are
3034 not allowed to store independent values. Use the patterns load_df_low,
3035 load_df_high and store_df_high instead. */
3036
3037 void
3038 mips_split_64bit_move (rtx dest, rtx src)
3039 {
3040 if (FP_REG_RTX_P (dest))
3041 {
3042 /* Loading an FPR from memory or from GPRs. */
3043 if (ISA_HAS_MXHC1)
3044 {
3045 dest = gen_lowpart (DFmode, dest);
3046 emit_insn (gen_load_df_low (dest, mips_subword (src, 0)));
3047 emit_insn (gen_mthc1 (dest, mips_subword (src, 1),
3048 copy_rtx (dest)));
3049 }
3050 else
3051 {
3052 emit_insn (gen_load_df_low (copy_rtx (dest),
3053 mips_subword (src, 0)));
3054 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
3055 copy_rtx (dest)));
3056 }
3057 }
3058 else if (FP_REG_RTX_P (src))
3059 {
3060 /* Storing an FPR into memory or GPRs. */
3061 if (ISA_HAS_MXHC1)
3062 {
3063 src = gen_lowpart (DFmode, src);
3064 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
3065 emit_insn (gen_mfhc1 (mips_subword (dest, 1), src));
3066 }
3067 else
3068 {
3069 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
3070 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
3071 }
3072 }
3073 else
3074 {
3075 /* The operation can be split into two normal moves. Decide in
3076 which order to do them. */
3077 rtx low_dest;
3078
3079 low_dest = mips_subword (dest, 0);
3080 if (REG_P (low_dest)
3081 && reg_overlap_mentioned_p (low_dest, src))
3082 {
3083 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
3084 emit_move_insn (low_dest, mips_subword (src, 0));
3085 }
3086 else
3087 {
3088 emit_move_insn (low_dest, mips_subword (src, 0));
3089 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
3090 }
3091 }
3092 }
3093 \f
3094 /* Return the appropriate instructions to move SRC into DEST. Assume
3095 that SRC is operand 1 and DEST is operand 0. */
3096
3097 const char *
3098 mips_output_move (rtx dest, rtx src)
3099 {
3100 enum rtx_code dest_code, src_code;
3101 bool dbl_p;
3102
3103 dest_code = GET_CODE (dest);
3104 src_code = GET_CODE (src);
3105 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
3106
3107 if (dbl_p && mips_split_64bit_move_p (dest, src))
3108 return "#";
3109
3110 if ((src_code == REG && GP_REG_P (REGNO (src)))
3111 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
3112 {
3113 if (dest_code == REG)
3114 {
3115 if (GP_REG_P (REGNO (dest)))
3116 return "move\t%0,%z1";
3117
3118 if (MD_REG_P (REGNO (dest)))
3119 return "mt%0\t%z1";
3120
3121 if (DSP_ACC_REG_P (REGNO (dest)))
3122 {
3123 static char retval[] = "mt__\t%z1,%q0";
3124 retval[2] = reg_names[REGNO (dest)][4];
3125 retval[3] = reg_names[REGNO (dest)][5];
3126 return retval;
3127 }
3128
3129 if (FP_REG_P (REGNO (dest)))
3130 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
3131
3132 if (ALL_COP_REG_P (REGNO (dest)))
3133 {
3134 static char retval[] = "dmtc_\t%z1,%0";
3135
3136 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3137 return (dbl_p ? retval : retval + 1);
3138 }
3139 }
3140 if (dest_code == MEM)
3141 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
3142 }
3143 if (dest_code == REG && GP_REG_P (REGNO (dest)))
3144 {
3145 if (src_code == REG)
3146 {
3147 if (DSP_ACC_REG_P (REGNO (src)))
3148 {
3149 static char retval[] = "mf__\t%0,%q1";
3150 retval[2] = reg_names[REGNO (src)][4];
3151 retval[3] = reg_names[REGNO (src)][5];
3152 return retval;
3153 }
3154
3155 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
3156 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
3157
3158 if (FP_REG_P (REGNO (src)))
3159 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
3160
3161 if (ALL_COP_REG_P (REGNO (src)))
3162 {
3163 static char retval[] = "dmfc_\t%0,%1";
3164
3165 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3166 return (dbl_p ? retval : retval + 1);
3167 }
3168 }
3169
3170 if (src_code == MEM)
3171 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
3172
3173 if (src_code == CONST_INT)
3174 {
3175 /* Don't use the X format, because that will give out of
3176 range numbers for 64-bit hosts and 32-bit targets. */
3177 if (!TARGET_MIPS16)
3178 return "li\t%0,%1\t\t\t# %X1";
3179
3180 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
3181 return "li\t%0,%1";
3182
3183 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
3184 return "#";
3185 }
3186
3187 if (src_code == HIGH)
3188 return "lui\t%0,%h1";
3189
3190 if (CONST_GP_P (src))
3191 return "move\t%0,%1";
3192
3193 if (symbolic_operand (src, VOIDmode))
3194 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
3195 }
3196 if (src_code == REG && FP_REG_P (REGNO (src)))
3197 {
3198 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3199 {
3200 if (GET_MODE (dest) == V2SFmode)
3201 return "mov.ps\t%0,%1";
3202 else
3203 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
3204 }
3205
3206 if (dest_code == MEM)
3207 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
3208 }
3209 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3210 {
3211 if (src_code == MEM)
3212 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
3213 }
3214 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
3215 {
3216 static char retval[] = "l_c_\t%0,%1";
3217
3218 retval[1] = (dbl_p ? 'd' : 'w');
3219 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3220 return retval;
3221 }
3222 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
3223 {
3224 static char retval[] = "s_c_\t%1,%0";
3225
3226 retval[1] = (dbl_p ? 'd' : 'w');
3227 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3228 return retval;
3229 }
3230 gcc_unreachable ();
3231 }
3232 \f
3233 /* Restore $gp from its save slot. Valid only when using o32 or
3234 o64 abicalls. */
3235
3236 void
3237 mips_restore_gp (void)
3238 {
3239 rtx address, slot;
3240
3241 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
3242
3243 address = mips_add_offset (pic_offset_table_rtx,
3244 frame_pointer_needed
3245 ? hard_frame_pointer_rtx
3246 : stack_pointer_rtx,
3247 current_function_outgoing_args_size);
3248 slot = gen_rtx_MEM (Pmode, address);
3249
3250 emit_move_insn (pic_offset_table_rtx, slot);
3251 if (!TARGET_EXPLICIT_RELOCS)
3252 emit_insn (gen_blockage ());
3253 }
3254 \f
3255 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
3256
3257 static void
3258 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
3259 {
3260 emit_insn (gen_rtx_SET (VOIDmode, target,
3261 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
3262 }
3263
3264 /* Return true if CMP1 is a suitable second operand for relational
3265 operator CODE. See also the *sCC patterns in mips.md. */
3266
3267 static bool
3268 mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
3269 {
3270 switch (code)
3271 {
3272 case GT:
3273 case GTU:
3274 return reg_or_0_operand (cmp1, VOIDmode);
3275
3276 case GE:
3277 case GEU:
3278 return !TARGET_MIPS16 && cmp1 == const1_rtx;
3279
3280 case LT:
3281 case LTU:
3282 return arith_operand (cmp1, VOIDmode);
3283
3284 case LE:
3285 return sle_operand (cmp1, VOIDmode);
3286
3287 case LEU:
3288 return sleu_operand (cmp1, VOIDmode);
3289
3290 default:
3291 gcc_unreachable ();
3292 }
3293 }
3294
3295 /* Canonicalize LE or LEU comparisons into LT comparisons when
3296 possible to avoid extra instructions or inverting the
3297 comparison. */
3298
3299 static bool
3300 mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1,
3301 enum machine_mode mode)
3302 {
3303 HOST_WIDE_INT original, plus_one;
3304
3305 if (GET_CODE (*cmp1) != CONST_INT)
3306 return false;
3307
3308 original = INTVAL (*cmp1);
3309 plus_one = trunc_int_for_mode ((unsigned HOST_WIDE_INT) original + 1, mode);
3310
3311 switch (*code)
3312 {
3313 case LE:
3314 if (original < plus_one)
3315 {
3316 *code = LT;
3317 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3318 return true;
3319 }
3320 break;
3321
3322 case LEU:
3323 if (plus_one != 0)
3324 {
3325 *code = LTU;
3326 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3327 return true;
3328 }
3329 break;
3330
3331 default:
3332 return false;
3333 }
3334
3335 return false;
3336
3337 }
3338
3339 /* Compare CMP0 and CMP1 using relational operator CODE and store the
3340 result in TARGET. CMP0 and TARGET are register_operands that have
3341 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
3342 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
3343
3344 static void
3345 mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
3346 rtx target, rtx cmp0, rtx cmp1)
3347 {
3348 /* First see if there is a MIPS instruction that can do this operation
3349 with CMP1 in its current form. If not, try to canonicalize the
3350 comparison to LT. If that fails, try doing the same for the
3351 inverse operation. If that also fails, force CMP1 into a register
3352 and try again. */
3353 if (mips_relational_operand_ok_p (code, cmp1))
3354 mips_emit_binary (code, target, cmp0, cmp1);
3355 else if (mips_canonicalize_comparison (&code, &cmp1, GET_MODE (target)))
3356 mips_emit_binary (code, target, cmp0, cmp1);
3357 else
3358 {
3359 enum rtx_code inv_code = reverse_condition (code);
3360 if (!mips_relational_operand_ok_p (inv_code, cmp1))
3361 {
3362 cmp1 = force_reg (GET_MODE (cmp0), cmp1);
3363 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
3364 }
3365 else if (invert_ptr == 0)
3366 {
3367 rtx inv_target = gen_reg_rtx (GET_MODE (target));
3368 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
3369 mips_emit_binary (XOR, target, inv_target, const1_rtx);
3370 }
3371 else
3372 {
3373 *invert_ptr = !*invert_ptr;
3374 mips_emit_binary (inv_code, target, cmp0, cmp1);
3375 }
3376 }
3377 }
3378
3379 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3380 The register will have the same mode as CMP0. */
3381
3382 static rtx
3383 mips_zero_if_equal (rtx cmp0, rtx cmp1)
3384 {
3385 if (cmp1 == const0_rtx)
3386 return cmp0;
3387
3388 if (uns_arith_operand (cmp1, VOIDmode))
3389 return expand_binop (GET_MODE (cmp0), xor_optab,
3390 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3391
3392 return expand_binop (GET_MODE (cmp0), sub_optab,
3393 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3394 }
3395
3396 /* Convert *CODE into a code that can be used in a floating-point
3397 scc instruction (c.<cond>.<fmt>). Return true if the values of
3398 the condition code registers will be inverted, with 0 indicating
3399 that the condition holds. */
3400
3401 static bool
3402 mips_reverse_fp_cond_p (enum rtx_code *code)
3403 {
3404 switch (*code)
3405 {
3406 case NE:
3407 case LTGT:
3408 case ORDERED:
3409 *code = reverse_condition_maybe_unordered (*code);
3410 return true;
3411
3412 default:
3413 return false;
3414 }
3415 }
3416
3417 /* Convert a comparison into something that can be used in a branch or
3418 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3419 being compared and *CODE is the code used to compare them.
3420
3421 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3422 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3423 otherwise any standard branch condition can be used. The standard branch
3424 conditions are:
3425
3426 - EQ/NE between two registers.
3427 - any comparison between a register and zero. */
3428
3429 static void
3430 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3431 {
3432 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3433 {
3434 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3435 {
3436 *op0 = cmp_operands[0];
3437 *op1 = cmp_operands[1];
3438 }
3439 else if (*code == EQ || *code == NE)
3440 {
3441 if (need_eq_ne_p)
3442 {
3443 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3444 *op1 = const0_rtx;
3445 }
3446 else
3447 {
3448 *op0 = cmp_operands[0];
3449 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3450 }
3451 }
3452 else
3453 {
3454 /* The comparison needs a separate scc instruction. Store the
3455 result of the scc in *OP0 and compare it against zero. */
3456 bool invert = false;
3457 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3458 *op1 = const0_rtx;
3459 mips_emit_int_relational (*code, &invert, *op0,
3460 cmp_operands[0], cmp_operands[1]);
3461 *code = (invert ? EQ : NE);
3462 }
3463 }
3464 else
3465 {
3466 enum rtx_code cmp_code;
3467
3468 /* Floating-point tests use a separate c.cond.fmt comparison to
3469 set a condition code register. The branch or conditional move
3470 will then compare that register against zero.
3471
3472 Set CMP_CODE to the code of the comparison instruction and
3473 *CODE to the code that the branch or move should use. */
3474 cmp_code = *code;
3475 *code = mips_reverse_fp_cond_p (&cmp_code) ? EQ : NE;
3476 *op0 = (ISA_HAS_8CC
3477 ? gen_reg_rtx (CCmode)
3478 : gen_rtx_REG (CCmode, FPSW_REGNUM));
3479 *op1 = const0_rtx;
3480 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
3481 }
3482 }
3483 \f
3484 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3485 Store the result in TARGET and return true if successful.
3486
3487 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3488
3489 bool
3490 mips_emit_scc (enum rtx_code code, rtx target)
3491 {
3492 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
3493 return false;
3494
3495 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
3496 if (code == EQ || code == NE)
3497 {
3498 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3499 mips_emit_binary (code, target, zie, const0_rtx);
3500 }
3501 else
3502 mips_emit_int_relational (code, 0, target,
3503 cmp_operands[0], cmp_operands[1]);
3504 return true;
3505 }
3506
3507 /* Emit the common code for doing conditional branches.
3508 operand[0] is the label to jump to.
3509 The comparison operands are saved away by cmp{si,di,sf,df}. */
3510
3511 void
3512 gen_conditional_branch (rtx *operands, enum rtx_code code)
3513 {
3514 rtx op0, op1, condition;
3515
3516 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
3517 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3518 emit_jump_insn (gen_condjump (condition, operands[0]));
3519 }
3520
3521 /* Implement:
3522
3523 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
3524 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
3525
3526 void
3527 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
3528 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
3529 {
3530 rtx cmp_result;
3531 bool reversed_p;
3532
3533 reversed_p = mips_reverse_fp_cond_p (&cond);
3534 cmp_result = gen_reg_rtx (CCV2mode);
3535 emit_insn (gen_scc_ps (cmp_result,
3536 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
3537 if (reversed_p)
3538 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
3539 cmp_result));
3540 else
3541 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
3542 cmp_result));
3543 }
3544
3545 /* Emit the common code for conditional moves. OPERANDS is the array
3546 of operands passed to the conditional move define_expand. */
3547
3548 void
3549 gen_conditional_move (rtx *operands)
3550 {
3551 enum rtx_code code;
3552 rtx op0, op1;
3553
3554 code = GET_CODE (operands[1]);
3555 mips_emit_compare (&code, &op0, &op1, true);
3556 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3557 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3558 gen_rtx_fmt_ee (code,
3559 GET_MODE (op0),
3560 op0, op1),
3561 operands[2], operands[3])));
3562 }
3563
3564 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3565 the conditional_trap expander. */
3566
3567 void
3568 mips_gen_conditional_trap (rtx *operands)
3569 {
3570 rtx op0, op1;
3571 enum rtx_code cmp_code = GET_CODE (operands[0]);
3572 enum machine_mode mode = GET_MODE (cmp_operands[0]);
3573
3574 /* MIPS conditional trap machine instructions don't have GT or LE
3575 flavors, so we must invert the comparison and convert to LT and
3576 GE, respectively. */
3577 switch (cmp_code)
3578 {
3579 case GT: cmp_code = LT; break;
3580 case LE: cmp_code = GE; break;
3581 case GTU: cmp_code = LTU; break;
3582 case LEU: cmp_code = GEU; break;
3583 default: break;
3584 }
3585 if (cmp_code == GET_CODE (operands[0]))
3586 {
3587 op0 = cmp_operands[0];
3588 op1 = cmp_operands[1];
3589 }
3590 else
3591 {
3592 op0 = cmp_operands[1];
3593 op1 = cmp_operands[0];
3594 }
3595 op0 = force_reg (mode, op0);
3596 if (!arith_operand (op1, mode))
3597 op1 = force_reg (mode, op1);
3598
3599 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3600 gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
3601 operands[1]));
3602 }
3603 \f
3604 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
3605
3606 static bool
3607 mips_ok_for_lazy_binding_p (rtx x)
3608 {
3609 return (TARGET_USE_GOT
3610 && GET_CODE (x) == SYMBOL_REF
3611 && !mips_symbol_binds_local_p (x));
3612 }
3613
3614 /* Load function address ADDR into register DEST. SIBCALL_P is true
3615 if the address is needed for a sibling call. */
3616
3617 static void
3618 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3619 {
3620 /* If we're generating PIC, and this call is to a global function,
3621 try to allow its address to be resolved lazily. This isn't
3622 possible if TARGET_CALL_SAVED_GP since the value of $gp on entry
3623 to the stub would be our caller's gp, not ours. */
3624 if (TARGET_EXPLICIT_RELOCS
3625 && !(sibcall_p && TARGET_CALL_SAVED_GP)
3626 && mips_ok_for_lazy_binding_p (addr))
3627 {
3628 rtx high, lo_sum_symbol;
3629
3630 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3631 addr, SYMBOL_GOTOFF_CALL);
3632 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3633 if (Pmode == SImode)
3634 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3635 else
3636 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3637 }
3638 else
3639 emit_move_insn (dest, addr);
3640 }
3641
3642
3643 /* Expand a call or call_value instruction. RESULT is where the
3644 result will go (null for calls), ADDR is the address of the
3645 function, ARGS_SIZE is the size of the arguments and AUX is
3646 the value passed to us by mips_function_arg. SIBCALL_P is true
3647 if we are expanding a sibling call, false if we're expanding
3648 a normal call. */
3649
3650 void
3651 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3652 {
3653 rtx orig_addr, pattern, insn;
3654
3655 orig_addr = addr;
3656 if (!call_insn_operand (addr, VOIDmode))
3657 {
3658 addr = gen_reg_rtx (Pmode);
3659 mips_load_call_address (addr, orig_addr, sibcall_p);
3660 }
3661
3662 if (mips16_hard_float
3663 && build_mips16_call_stub (result, addr, args_size,
3664 aux == 0 ? 0 : (int) GET_MODE (aux)))
3665 return;
3666
3667 if (result == 0)
3668 pattern = (sibcall_p
3669 ? gen_sibcall_internal (addr, args_size)
3670 : gen_call_internal (addr, args_size));
3671 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3672 {
3673 rtx reg1, reg2;
3674
3675 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3676 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3677 pattern =
3678 (sibcall_p
3679 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3680 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3681 }
3682 else
3683 pattern = (sibcall_p
3684 ? gen_sibcall_value_internal (result, addr, args_size)
3685 : gen_call_value_internal (result, addr, args_size));
3686
3687 insn = emit_call_insn (pattern);
3688
3689 /* Lazy-binding stubs require $gp to be valid on entry. */
3690 if (mips_ok_for_lazy_binding_p (orig_addr))
3691 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3692 }
3693
3694
3695 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3696
3697 static bool
3698 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3699 tree exp ATTRIBUTE_UNUSED)
3700 {
3701 return TARGET_SIBCALLS;
3702 }
3703 \f
3704 /* Emit code to move general operand SRC into condition-code
3705 register DEST. SCRATCH is a scratch TFmode float register.
3706 The sequence is:
3707
3708 FP1 = SRC
3709 FP2 = 0.0f
3710 DEST = FP2 < FP1
3711
3712 where FP1 and FP2 are single-precision float registers
3713 taken from SCRATCH. */
3714
3715 void
3716 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3717 {
3718 rtx fp1, fp2;
3719
3720 /* Change the source to SFmode. */
3721 if (MEM_P (src))
3722 src = adjust_address (src, SFmode, 0);
3723 else if (REG_P (src) || GET_CODE (src) == SUBREG)
3724 src = gen_rtx_REG (SFmode, true_regnum (src));
3725
3726 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3727 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
3728
3729 emit_move_insn (copy_rtx (fp1), src);
3730 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3731 emit_insn (gen_slt_sf (dest, fp2, fp1));
3732 }
3733 \f
3734 /* Emit code to change the current function's return address to
3735 ADDRESS. SCRATCH is available as a scratch register, if needed.
3736 ADDRESS and SCRATCH are both word-mode GPRs. */
3737
3738 void
3739 mips_set_return_address (rtx address, rtx scratch)
3740 {
3741 rtx slot_address;
3742
3743 compute_frame_size (get_frame_size ());
3744 gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
3745 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
3746 cfun->machine->frame.gp_sp_offset);
3747
3748 emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address);
3749 }
3750 \f
3751 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3752 Assume that the areas do not overlap. */
3753
3754 static void
3755 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3756 {
3757 HOST_WIDE_INT offset, delta;
3758 unsigned HOST_WIDE_INT bits;
3759 int i;
3760 enum machine_mode mode;
3761 rtx *regs;
3762
3763 /* Work out how many bits to move at a time. If both operands have
3764 half-word alignment, it is usually better to move in half words.
3765 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3766 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3767 Otherwise move word-sized chunks. */
3768 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3769 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3770 bits = BITS_PER_WORD / 2;
3771 else
3772 bits = BITS_PER_WORD;
3773
3774 mode = mode_for_size (bits, MODE_INT, 0);
3775 delta = bits / BITS_PER_UNIT;
3776
3777 /* Allocate a buffer for the temporary registers. */
3778 regs = alloca (sizeof (rtx) * length / delta);
3779
3780 /* Load as many BITS-sized chunks as possible. Use a normal load if
3781 the source has enough alignment, otherwise use left/right pairs. */
3782 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3783 {
3784 regs[i] = gen_reg_rtx (mode);
3785 if (MEM_ALIGN (src) >= bits)
3786 emit_move_insn (regs[i], adjust_address (src, mode, offset));
3787 else
3788 {
3789 rtx part = adjust_address (src, BLKmode, offset);
3790 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3791 gcc_unreachable ();
3792 }
3793 }
3794
3795 /* Copy the chunks to the destination. */
3796 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3797 if (MEM_ALIGN (dest) >= bits)
3798 emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
3799 else
3800 {
3801 rtx part = adjust_address (dest, BLKmode, offset);
3802 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3803 gcc_unreachable ();
3804 }
3805
3806 /* Mop up any left-over bytes. */
3807 if (offset < length)
3808 {
3809 src = adjust_address (src, BLKmode, offset);
3810 dest = adjust_address (dest, BLKmode, offset);
3811 move_by_pieces (dest, src, length - offset,
3812 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3813 }
3814 }
3815 \f
3816 #define MAX_MOVE_REGS 4
3817 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3818
3819
3820 /* Helper function for doing a loop-based block operation on memory
3821 reference MEM. Each iteration of the loop will operate on LENGTH
3822 bytes of MEM.
3823
3824 Create a new base register for use within the loop and point it to
3825 the start of MEM. Create a new memory reference that uses this
3826 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3827
3828 static void
3829 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3830 rtx *loop_reg, rtx *loop_mem)
3831 {
3832 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3833
3834 /* Although the new mem does not refer to a known location,
3835 it does keep up to LENGTH bytes of alignment. */
3836 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3837 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3838 }
3839
3840
3841 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3842 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3843 memory regions do not overlap. */
3844
3845 static void
3846 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3847 {
3848 rtx label, src_reg, dest_reg, final_src;
3849 HOST_WIDE_INT leftover;
3850
3851 leftover = length % MAX_MOVE_BYTES;
3852 length -= leftover;
3853
3854 /* Create registers and memory references for use within the loop. */
3855 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3856 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3857
3858 /* Calculate the value that SRC_REG should have after the last iteration
3859 of the loop. */
3860 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3861 0, 0, OPTAB_WIDEN);
3862
3863 /* Emit the start of the loop. */
3864 label = gen_label_rtx ();
3865 emit_label (label);
3866
3867 /* Emit the loop body. */
3868 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3869
3870 /* Move on to the next block. */
3871 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3872 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3873
3874 /* Emit the loop condition. */
3875 if (Pmode == DImode)
3876 emit_insn (gen_cmpdi (src_reg, final_src));
3877 else
3878 emit_insn (gen_cmpsi (src_reg, final_src));
3879 emit_jump_insn (gen_bne (label));
3880
3881 /* Mop up any left-over bytes. */
3882 if (leftover)
3883 mips_block_move_straight (dest, src, leftover);
3884 }
3885 \f
3886 /* Expand a movmemsi instruction. */
3887
3888 bool
3889 mips_expand_block_move (rtx dest, rtx src, rtx length)
3890 {
3891 if (GET_CODE (length) == CONST_INT)
3892 {
3893 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3894 {
3895 mips_block_move_straight (dest, src, INTVAL (length));
3896 return true;
3897 }
3898 else if (optimize)
3899 {
3900 mips_block_move_loop (dest, src, INTVAL (length));
3901 return true;
3902 }
3903 }
3904 return false;
3905 }
3906 \f
3907 /* Argument support functions. */
3908
3909 /* Initialize CUMULATIVE_ARGS for a function. */
3910
3911 void
3912 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3913 rtx libname ATTRIBUTE_UNUSED)
3914 {
3915 static CUMULATIVE_ARGS zero_cum;
3916 tree param, next_param;
3917
3918 *cum = zero_cum;
3919 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3920
3921 /* Determine if this function has variable arguments. This is
3922 indicated by the last argument being 'void_type_mode' if there
3923 are no variable arguments. The standard MIPS calling sequence
3924 passes all arguments in the general purpose registers in this case. */
3925
3926 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3927 param != 0; param = next_param)
3928 {
3929 next_param = TREE_CHAIN (param);
3930 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3931 cum->gp_reg_found = 1;
3932 }
3933 }
3934
3935
3936 /* Fill INFO with information about a single argument. CUM is the
3937 cumulative state for earlier arguments. MODE is the mode of this
3938 argument and TYPE is its type (if known). NAMED is true if this
3939 is a named (fixed) argument rather than a variable one. */
3940
3941 static void
3942 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3943 tree type, int named, struct mips_arg_info *info)
3944 {
3945 bool doubleword_aligned_p;
3946 unsigned int num_bytes, num_words, max_regs;
3947
3948 /* Work out the size of the argument. */
3949 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3950 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3951
3952 /* Decide whether it should go in a floating-point register, assuming
3953 one is free. Later code checks for availability.
3954
3955 The checks against UNITS_PER_FPVALUE handle the soft-float and
3956 single-float cases. */
3957 switch (mips_abi)
3958 {
3959 case ABI_EABI:
3960 /* The EABI conventions have traditionally been defined in terms
3961 of TYPE_MODE, regardless of the actual type. */
3962 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
3963 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3964 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3965 break;
3966
3967 case ABI_32:
3968 case ABI_O64:
3969 /* Only leading floating-point scalars are passed in
3970 floating-point registers. We also handle vector floats the same
3971 say, which is OK because they are not covered by the standard ABI. */
3972 info->fpr_p = (!cum->gp_reg_found
3973 && cum->arg_number < 2
3974 && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
3975 || VECTOR_FLOAT_TYPE_P (type))
3976 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3977 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3978 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3979 break;
3980
3981 case ABI_N32:
3982 case ABI_64:
3983 /* Scalar and complex floating-point types are passed in
3984 floating-point registers. */
3985 info->fpr_p = (named
3986 && (type == 0 || FLOAT_TYPE_P (type))
3987 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3988 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3989 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3990 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
3991
3992 /* ??? According to the ABI documentation, the real and imaginary
3993 parts of complex floats should be passed in individual registers.
3994 The real and imaginary parts of stack arguments are supposed
3995 to be contiguous and there should be an extra word of padding
3996 at the end.
3997
3998 This has two problems. First, it makes it impossible to use a
3999 single "void *" va_list type, since register and stack arguments
4000 are passed differently. (At the time of writing, MIPSpro cannot
4001 handle complex float varargs correctly.) Second, it's unclear
4002 what should happen when there is only one register free.
4003
4004 For now, we assume that named complex floats should go into FPRs
4005 if there are two FPRs free, otherwise they should be passed in the
4006 same way as a struct containing two floats. */
4007 if (info->fpr_p
4008 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4009 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4010 {
4011 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4012 info->fpr_p = false;
4013 else
4014 num_words = 2;
4015 }
4016 break;
4017
4018 default:
4019 gcc_unreachable ();
4020 }
4021
4022 /* See whether the argument has doubleword alignment. */
4023 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
4024
4025 /* Set REG_OFFSET to the register count we're interested in.
4026 The EABI allocates the floating-point registers separately,
4027 but the other ABIs allocate them like integer registers. */
4028 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4029 ? cum->num_fprs
4030 : cum->num_gprs);
4031
4032 /* Advance to an even register if the argument is doubleword-aligned. */
4033 if (doubleword_aligned_p)
4034 info->reg_offset += info->reg_offset & 1;
4035
4036 /* Work out the offset of a stack argument. */
4037 info->stack_offset = cum->stack_words;
4038 if (doubleword_aligned_p)
4039 info->stack_offset += info->stack_offset & 1;
4040
4041 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4042
4043 /* Partition the argument between registers and stack. */
4044 info->reg_words = MIN (num_words, max_regs);
4045 info->stack_words = num_words - info->reg_words;
4046 }
4047
4048
4049 /* INFO describes an argument that is passed in a single-register value.
4050 Return the register it uses, assuming that FPRs are available if
4051 HARD_FLOAT_P. */
4052
4053 static unsigned int
4054 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4055 {
4056 if (!info->fpr_p || !hard_float_p)
4057 return GP_ARG_FIRST + info->reg_offset;
4058 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4059 /* In o32, the second argument is always passed in $f14
4060 for TARGET_DOUBLE_FLOAT, regardless of whether the
4061 first argument was a word or doubleword. */
4062 return FP_ARG_FIRST + 2;
4063 else
4064 return FP_ARG_FIRST + info->reg_offset;
4065 }
4066
4067 /* Implement FUNCTION_ARG_ADVANCE. */
4068
4069 void
4070 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4071 tree type, int named)
4072 {
4073 struct mips_arg_info info;
4074
4075 mips_arg_info (cum, mode, type, named, &info);
4076
4077 if (!info.fpr_p)
4078 cum->gp_reg_found = true;
4079
4080 /* See the comment above the cumulative args structure in mips.h
4081 for an explanation of what this code does. It assumes the O32
4082 ABI, which passes at most 2 arguments in float registers. */
4083 if (cum->arg_number < 2 && info.fpr_p)
4084 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4085
4086 if (mips_abi != ABI_EABI || !info.fpr_p)
4087 cum->num_gprs = info.reg_offset + info.reg_words;
4088 else if (info.reg_words > 0)
4089 cum->num_fprs += MAX_FPRS_PER_FMT;
4090
4091 if (info.stack_words > 0)
4092 cum->stack_words = info.stack_offset + info.stack_words;
4093
4094 cum->arg_number++;
4095 }
4096
4097 /* Implement FUNCTION_ARG. */
4098
4099 struct rtx_def *
4100 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4101 tree type, int named)
4102 {
4103 struct mips_arg_info info;
4104
4105 /* We will be called with a mode of VOIDmode after the last argument
4106 has been seen. Whatever we return will be passed to the call
4107 insn. If we need a mips16 fp_code, return a REG with the code
4108 stored as the mode. */
4109 if (mode == VOIDmode)
4110 {
4111 if (TARGET_MIPS16 && cum->fp_code != 0)
4112 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4113
4114 else
4115 return 0;
4116 }
4117
4118 mips_arg_info (cum, mode, type, named, &info);
4119
4120 /* Return straight away if the whole argument is passed on the stack. */
4121 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4122 return 0;
4123
4124 if (type != 0
4125 && TREE_CODE (type) == RECORD_TYPE
4126 && TARGET_NEWABI
4127 && TYPE_SIZE_UNIT (type)
4128 && host_integerp (TYPE_SIZE_UNIT (type), 1)
4129 && named)
4130 {
4131 /* The Irix 6 n32/n64 ABIs say that if any 64-bit chunk of the
4132 structure contains a double in its entirety, then that 64-bit
4133 chunk is passed in a floating point register. */
4134 tree field;
4135
4136 /* First check to see if there is any such field. */
4137 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4138 if (TREE_CODE (field) == FIELD_DECL
4139 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4140 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4141 && host_integerp (bit_position (field), 0)
4142 && int_bit_position (field) % BITS_PER_WORD == 0)
4143 break;
4144
4145 if (field != 0)
4146 {
4147 /* Now handle the special case by returning a PARALLEL
4148 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4149 chunks are passed in registers. */
4150 unsigned int i;
4151 HOST_WIDE_INT bitpos;
4152 rtx ret;
4153
4154 /* assign_parms checks the mode of ENTRY_PARM, so we must
4155 use the actual mode here. */
4156 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4157
4158 bitpos = 0;
4159 field = TYPE_FIELDS (type);
4160 for (i = 0; i < info.reg_words; i++)
4161 {
4162 rtx reg;
4163
4164 for (; field; field = TREE_CHAIN (field))
4165 if (TREE_CODE (field) == FIELD_DECL
4166 && int_bit_position (field) >= bitpos)
4167 break;
4168
4169 if (field
4170 && int_bit_position (field) == bitpos
4171 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4172 && !TARGET_SOFT_FLOAT
4173 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4174 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4175 else
4176 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4177
4178 XVECEXP (ret, 0, i)
4179 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4180 GEN_INT (bitpos / BITS_PER_UNIT));
4181
4182 bitpos += BITS_PER_WORD;
4183 }
4184 return ret;
4185 }
4186 }
4187
4188 /* Handle the n32/n64 conventions for passing complex floating-point
4189 arguments in FPR pairs. The real part goes in the lower register
4190 and the imaginary part goes in the upper register. */
4191 if (TARGET_NEWABI
4192 && info.fpr_p
4193 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4194 {
4195 rtx real, imag;
4196 enum machine_mode inner;
4197 int reg;
4198
4199 inner = GET_MODE_INNER (mode);
4200 reg = FP_ARG_FIRST + info.reg_offset;
4201 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4202 {
4203 /* Real part in registers, imaginary part on stack. */
4204 gcc_assert (info.stack_words == info.reg_words);
4205 return gen_rtx_REG (inner, reg);
4206 }
4207 else
4208 {
4209 gcc_assert (info.stack_words == 0);
4210 real = gen_rtx_EXPR_LIST (VOIDmode,
4211 gen_rtx_REG (inner, reg),
4212 const0_rtx);
4213 imag = gen_rtx_EXPR_LIST (VOIDmode,
4214 gen_rtx_REG (inner,
4215 reg + info.reg_words / 2),
4216 GEN_INT (GET_MODE_SIZE (inner)));
4217 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4218 }
4219 }
4220
4221 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4222 }
4223
4224
4225 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4226
4227 static int
4228 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
4229 enum machine_mode mode, tree type, bool named)
4230 {
4231 struct mips_arg_info info;
4232
4233 mips_arg_info (cum, mode, type, named, &info);
4234 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4235 }
4236
4237
4238 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4239 PARM_BOUNDARY bits of alignment, but will be given anything up
4240 to STACK_BOUNDARY bits if the type requires it. */
4241
4242 int
4243 function_arg_boundary (enum machine_mode mode, tree type)
4244 {
4245 unsigned int alignment;
4246
4247 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4248 if (alignment < PARM_BOUNDARY)
4249 alignment = PARM_BOUNDARY;
4250 if (alignment > STACK_BOUNDARY)
4251 alignment = STACK_BOUNDARY;
4252 return alignment;
4253 }
4254
4255 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4256 upward rather than downward. In other words, return true if the
4257 first byte of the stack slot has useful data, false if the last
4258 byte does. */
4259
4260 bool
4261 mips_pad_arg_upward (enum machine_mode mode, tree type)
4262 {
4263 /* On little-endian targets, the first byte of every stack argument
4264 is passed in the first byte of the stack slot. */
4265 if (!BYTES_BIG_ENDIAN)
4266 return true;
4267
4268 /* Otherwise, integral types are padded downward: the last byte of a
4269 stack argument is passed in the last byte of the stack slot. */
4270 if (type != 0
4271 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
4272 : GET_MODE_CLASS (mode) == MODE_INT)
4273 return false;
4274
4275 /* Big-endian o64 pads floating-point arguments downward. */
4276 if (mips_abi == ABI_O64)
4277 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4278 return false;
4279
4280 /* Other types are padded upward for o32, o64, n32 and n64. */
4281 if (mips_abi != ABI_EABI)
4282 return true;
4283
4284 /* Arguments smaller than a stack slot are padded downward. */
4285 if (mode != BLKmode)
4286 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
4287 else
4288 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
4289 }
4290
4291
4292 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4293 if the least significant byte of the register has useful data. Return
4294 the opposite if the most significant byte does. */
4295
4296 bool
4297 mips_pad_reg_upward (enum machine_mode mode, tree type)
4298 {
4299 /* No shifting is required for floating-point arguments. */
4300 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4301 return !BYTES_BIG_ENDIAN;
4302
4303 /* Otherwise, apply the same padding to register arguments as we do
4304 to stack arguments. */
4305 return mips_pad_arg_upward (mode, type);
4306 }
4307 \f
4308 static void
4309 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4310 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4311 int no_rtl)
4312 {
4313 CUMULATIVE_ARGS local_cum;
4314 int gp_saved, fp_saved;
4315
4316 /* The caller has advanced CUM up to, but not beyond, the last named
4317 argument. Advance a local copy of CUM past the last "real" named
4318 argument, to find out how many registers are left over. */
4319
4320 local_cum = *cum;
4321 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
4322
4323 /* Found out how many registers we need to save. */
4324 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4325 fp_saved = (EABI_FLOAT_VARARGS_P
4326 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4327 : 0);
4328
4329 if (!no_rtl)
4330 {
4331 if (gp_saved > 0)
4332 {
4333 rtx ptr, mem;
4334
4335 ptr = plus_constant (virtual_incoming_args_rtx,
4336 REG_PARM_STACK_SPACE (cfun->decl)
4337 - gp_saved * UNITS_PER_WORD);
4338 mem = gen_rtx_MEM (BLKmode, ptr);
4339 set_mem_alias_set (mem, get_varargs_alias_set ());
4340
4341 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
4342 mem, gp_saved);
4343 }
4344 if (fp_saved > 0)
4345 {
4346 /* We can't use move_block_from_reg, because it will use
4347 the wrong mode. */
4348 enum machine_mode mode;
4349 int off, i;
4350
4351 /* Set OFF to the offset from virtual_incoming_args_rtx of
4352 the first float register. The FP save area lies below
4353 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4354 off = -gp_saved * UNITS_PER_WORD;
4355 off &= ~(UNITS_PER_FPVALUE - 1);
4356 off -= fp_saved * UNITS_PER_FPREG;
4357
4358 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4359
4360 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
4361 i += MAX_FPRS_PER_FMT)
4362 {
4363 rtx ptr, mem;
4364
4365 ptr = plus_constant (virtual_incoming_args_rtx, off);
4366 mem = gen_rtx_MEM (mode, ptr);
4367 set_mem_alias_set (mem, get_varargs_alias_set ());
4368 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
4369 off += UNITS_PER_HWFPVALUE;
4370 }
4371 }
4372 }
4373 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
4374 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
4375 + fp_saved * UNITS_PER_FPREG);
4376 }
4377
4378 /* Create the va_list data type.
4379 We keep 3 pointers, and two offsets.
4380 Two pointers are to the overflow area, which starts at the CFA.
4381 One of these is constant, for addressing into the GPR save area below it.
4382 The other is advanced up the stack through the overflow region.
4383 The third pointer is to the GPR save area. Since the FPR save area
4384 is just below it, we can address FPR slots off this pointer.
4385 We also keep two one-byte offsets, which are to be subtracted from the
4386 constant pointers to yield addresses in the GPR and FPR save areas.
4387 These are downcounted as float or non-float arguments are used,
4388 and when they get to zero, the argument must be obtained from the
4389 overflow region.
4390 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4391 pointer is enough. It's started at the GPR save area, and is
4392 advanced, period.
4393 Note that the GPR save area is not constant size, due to optimization
4394 in the prologue. Hence, we can't use a design with two pointers
4395 and two offsets, although we could have designed this with two pointers
4396 and three offsets. */
4397
4398 static tree
4399 mips_build_builtin_va_list (void)
4400 {
4401 if (EABI_FLOAT_VARARGS_P)
4402 {
4403 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4404 tree array, index;
4405
4406 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4407
4408 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4409 ptr_type_node);
4410 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4411 ptr_type_node);
4412 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4413 ptr_type_node);
4414 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4415 unsigned_char_type_node);
4416 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4417 unsigned_char_type_node);
4418 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4419 warn on every user file. */
4420 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4421 array = build_array_type (unsigned_char_type_node,
4422 build_index_type (index));
4423 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4424
4425 DECL_FIELD_CONTEXT (f_ovfl) = record;
4426 DECL_FIELD_CONTEXT (f_gtop) = record;
4427 DECL_FIELD_CONTEXT (f_ftop) = record;
4428 DECL_FIELD_CONTEXT (f_goff) = record;
4429 DECL_FIELD_CONTEXT (f_foff) = record;
4430 DECL_FIELD_CONTEXT (f_res) = record;
4431
4432 TYPE_FIELDS (record) = f_ovfl;
4433 TREE_CHAIN (f_ovfl) = f_gtop;
4434 TREE_CHAIN (f_gtop) = f_ftop;
4435 TREE_CHAIN (f_ftop) = f_goff;
4436 TREE_CHAIN (f_goff) = f_foff;
4437 TREE_CHAIN (f_foff) = f_res;
4438
4439 layout_type (record);
4440 return record;
4441 }
4442 else if (TARGET_IRIX && TARGET_IRIX6)
4443 /* On IRIX 6, this type is 'char *'. */
4444 return build_pointer_type (char_type_node);
4445 else
4446 /* Otherwise, we use 'void *'. */
4447 return ptr_type_node;
4448 }
4449
4450 /* Implement va_start. */
4451
4452 void
4453 mips_va_start (tree valist, rtx nextarg)
4454 {
4455 if (EABI_FLOAT_VARARGS_P)
4456 {
4457 const CUMULATIVE_ARGS *cum;
4458 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4459 tree ovfl, gtop, ftop, goff, foff;
4460 tree t;
4461 int gpr_save_area_size;
4462 int fpr_save_area_size;
4463 int fpr_offset;
4464
4465 cum = &current_function_args_info;
4466 gpr_save_area_size
4467 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4468 fpr_save_area_size
4469 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4470
4471 f_ovfl = TYPE_FIELDS (va_list_type_node);
4472 f_gtop = TREE_CHAIN (f_ovfl);
4473 f_ftop = TREE_CHAIN (f_gtop);
4474 f_goff = TREE_CHAIN (f_ftop);
4475 f_foff = TREE_CHAIN (f_goff);
4476
4477 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4478 NULL_TREE);
4479 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4480 NULL_TREE);
4481 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4482 NULL_TREE);
4483 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4484 NULL_TREE);
4485 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4486 NULL_TREE);
4487
4488 /* Emit code to initialize OVFL, which points to the next varargs
4489 stack argument. CUM->STACK_WORDS gives the number of stack
4490 words used by named arguments. */
4491 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4492 if (cum->stack_words > 0)
4493 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
4494 size_int (cum->stack_words * UNITS_PER_WORD));
4495 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
4496 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4497
4498 /* Emit code to initialize GTOP, the top of the GPR save area. */
4499 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4500 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gtop), gtop, t);
4501 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4502
4503 /* Emit code to initialize FTOP, the top of the FPR save area.
4504 This address is gpr_save_area_bytes below GTOP, rounded
4505 down to the next fp-aligned boundary. */
4506 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4507 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4508 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4509 if (fpr_offset)
4510 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
4511 size_int (-fpr_offset));
4512 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ftop), ftop, t);
4513 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4514
4515 /* Emit code to initialize GOFF, the offset from GTOP of the
4516 next GPR argument. */
4517 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (goff), goff,
4518 build_int_cst (NULL_TREE, gpr_save_area_size));
4519 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4520
4521 /* Likewise emit code to initialize FOFF, the offset from FTOP
4522 of the next FPR argument. */
4523 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (foff), foff,
4524 build_int_cst (NULL_TREE, fpr_save_area_size));
4525 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4526 }
4527 else
4528 {
4529 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4530 std_expand_builtin_va_start (valist, nextarg);
4531 }
4532 }
4533 \f
4534 /* Implement va_arg. */
4535
4536 static tree
4537 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
4538 {
4539 HOST_WIDE_INT size, rsize;
4540 tree addr;
4541 bool indirect;
4542
4543 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4544
4545 if (indirect)
4546 type = build_pointer_type (type);
4547
4548 size = int_size_in_bytes (type);
4549 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4550
4551 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
4552 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4553 else
4554 {
4555 /* Not a simple merged stack. */
4556
4557 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4558 tree ovfl, top, off, align;
4559 HOST_WIDE_INT osize;
4560 tree t, u;
4561
4562 f_ovfl = TYPE_FIELDS (va_list_type_node);
4563 f_gtop = TREE_CHAIN (f_ovfl);
4564 f_ftop = TREE_CHAIN (f_gtop);
4565 f_goff = TREE_CHAIN (f_ftop);
4566 f_foff = TREE_CHAIN (f_goff);
4567
4568 /* We maintain separate pointers and offsets for floating-point
4569 and integer arguments, but we need similar code in both cases.
4570 Let:
4571
4572 TOP be the top of the register save area;
4573 OFF be the offset from TOP of the next register;
4574 ADDR_RTX be the address of the argument;
4575 RSIZE be the number of bytes used to store the argument
4576 when it's in the register save area;
4577 OSIZE be the number of bytes used to store it when it's
4578 in the stack overflow area; and
4579 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4580
4581 The code we want is:
4582
4583 1: off &= -rsize; // round down
4584 2: if (off != 0)
4585 3: {
4586 4: addr_rtx = top - off;
4587 5: off -= rsize;
4588 6: }
4589 7: else
4590 8: {
4591 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4592 10: addr_rtx = ovfl + PADDING;
4593 11: ovfl += osize;
4594 14: }
4595
4596 [1] and [9] can sometimes be optimized away. */
4597
4598 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4599 NULL_TREE);
4600
4601 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4602 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4603 {
4604 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4605 NULL_TREE);
4606 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4607 NULL_TREE);
4608
4609 /* When floating-point registers are saved to the stack,
4610 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4611 of the float's precision. */
4612 rsize = UNITS_PER_HWFPVALUE;
4613
4614 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4615 (= PARM_BOUNDARY bits). This can be different from RSIZE
4616 in two cases:
4617
4618 (1) On 32-bit targets when TYPE is a structure such as:
4619
4620 struct s { float f; };
4621
4622 Such structures are passed in paired FPRs, so RSIZE
4623 will be 8 bytes. However, the structure only takes
4624 up 4 bytes of memory, so OSIZE will only be 4.
4625
4626 (2) In combinations such as -mgp64 -msingle-float
4627 -fshort-double. Doubles passed in registers
4628 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4629 but those passed on the stack take up
4630 UNITS_PER_WORD bytes. */
4631 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4632 }
4633 else
4634 {
4635 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4636 NULL_TREE);
4637 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4638 NULL_TREE);
4639 if (rsize > UNITS_PER_WORD)
4640 {
4641 /* [1] Emit code for: off &= -rsize. */
4642 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
4643 build_int_cst (NULL_TREE, -rsize));
4644 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (off), off, t);
4645 gimplify_and_add (t, pre_p);
4646 }
4647 osize = rsize;
4648 }
4649
4650 /* [2] Emit code to branch if off == 0. */
4651 t = build2 (NE_EXPR, boolean_type_node, off,
4652 build_int_cst (TREE_TYPE (off), 0));
4653 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
4654
4655 /* [5] Emit code for: off -= rsize. We do this as a form of
4656 post-increment not available to C. Also widen for the
4657 coming pointer arithmetic. */
4658 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
4659 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4660 t = fold_convert (sizetype, t);
4661 t = fold_build1 (NEGATE_EXPR, sizetype, t);
4662
4663 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4664 the argument has RSIZE - SIZE bytes of leading padding. */
4665 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
4666 if (BYTES_BIG_ENDIAN && rsize > size)
4667 {
4668 u = size_int (rsize - size);
4669 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
4670 }
4671 COND_EXPR_THEN (addr) = t;
4672
4673 if (osize > UNITS_PER_WORD)
4674 {
4675 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4676 u = size_int (osize - 1);
4677 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4678 t = fold_convert (sizetype, t);
4679 u = size_int (-osize);
4680 t = build2 (BIT_AND_EXPR, sizetype, t, u);
4681 t = fold_convert (TREE_TYPE (ovfl), t);
4682 align = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
4683 }
4684 else
4685 align = NULL;
4686
4687 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4688 post-increment ovfl by osize. On big-endian machines,
4689 the argument has OSIZE - SIZE bytes of leading padding. */
4690 u = fold_convert (TREE_TYPE (ovfl),
4691 build_int_cst (NULL_TREE, osize));
4692 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
4693 if (BYTES_BIG_ENDIAN && osize > size)
4694 {
4695 u = size_int (osize - size);
4696 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
4697 }
4698
4699 /* String [9] and [10,11] together. */
4700 if (align)
4701 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
4702 COND_EXPR_ELSE (addr) = t;
4703
4704 addr = fold_convert (build_pointer_type (type), addr);
4705 addr = build_va_arg_indirect_ref (addr);
4706 }
4707
4708 if (indirect)
4709 addr = build_va_arg_indirect_ref (addr);
4710
4711 return addr;
4712 }
4713 \f
4714 /* Return true if it is possible to use left/right accesses for a
4715 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4716 returning true, update *OP, *LEFT and *RIGHT as follows:
4717
4718 *OP is a BLKmode reference to the whole field.
4719
4720 *LEFT is a QImode reference to the first byte if big endian or
4721 the last byte if little endian. This address can be used in the
4722 left-side instructions (lwl, swl, ldl, sdl).
4723
4724 *RIGHT is a QImode reference to the opposite end of the field and
4725 can be used in the patterning right-side instruction. */
4726
4727 static bool
4728 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4729 rtx *left, rtx *right)
4730 {
4731 rtx first, last;
4732
4733 /* Check that the operand really is a MEM. Not all the extv and
4734 extzv predicates are checked. */
4735 if (!MEM_P (*op))
4736 return false;
4737
4738 /* Check that the size is valid. */
4739 if (width != 32 && (!TARGET_64BIT || width != 64))
4740 return false;
4741
4742 /* We can only access byte-aligned values. Since we are always passed
4743 a reference to the first byte of the field, it is not necessary to
4744 do anything with BITPOS after this check. */
4745 if (bitpos % BITS_PER_UNIT != 0)
4746 return false;
4747
4748 /* Reject aligned bitfields: we want to use a normal load or store
4749 instead of a left/right pair. */
4750 if (MEM_ALIGN (*op) >= width)
4751 return false;
4752
4753 /* Adjust *OP to refer to the whole field. This also has the effect
4754 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4755 *op = adjust_address (*op, BLKmode, 0);
4756 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4757
4758 /* Get references to both ends of the field. We deliberately don't
4759 use the original QImode *OP for FIRST since the new BLKmode one
4760 might have a simpler address. */
4761 first = adjust_address (*op, QImode, 0);
4762 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4763
4764 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4765 be the upper word and RIGHT the lower word. */
4766 if (TARGET_BIG_ENDIAN)
4767 *left = first, *right = last;
4768 else
4769 *left = last, *right = first;
4770
4771 return true;
4772 }
4773
4774
4775 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4776 Return true on success. We only handle cases where zero_extract is
4777 equivalent to sign_extract. */
4778
4779 bool
4780 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4781 {
4782 rtx left, right, temp;
4783
4784 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4785 paradoxical word_mode subreg. This is the only case in which
4786 we allow the destination to be larger than the source. */
4787 if (GET_CODE (dest) == SUBREG
4788 && GET_MODE (dest) == DImode
4789 && SUBREG_BYTE (dest) == 0
4790 && GET_MODE (SUBREG_REG (dest)) == SImode)
4791 dest = SUBREG_REG (dest);
4792
4793 /* After the above adjustment, the destination must be the same
4794 width as the source. */
4795 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4796 return false;
4797
4798 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4799 return false;
4800
4801 temp = gen_reg_rtx (GET_MODE (dest));
4802 if (GET_MODE (dest) == DImode)
4803 {
4804 emit_insn (gen_mov_ldl (temp, src, left));
4805 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
4806 }
4807 else
4808 {
4809 emit_insn (gen_mov_lwl (temp, src, left));
4810 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
4811 }
4812 return true;
4813 }
4814
4815
4816 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4817 true on success. */
4818
4819 bool
4820 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4821 {
4822 rtx left, right;
4823 enum machine_mode mode;
4824
4825 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4826 return false;
4827
4828 mode = mode_for_size (width, MODE_INT, 0);
4829 src = gen_lowpart (mode, src);
4830
4831 if (mode == DImode)
4832 {
4833 emit_insn (gen_mov_sdl (dest, src, left));
4834 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4835 }
4836 else
4837 {
4838 emit_insn (gen_mov_swl (dest, src, left));
4839 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4840 }
4841 return true;
4842 }
4843
4844 /* Return true if X is a MEM with the same size as MODE. */
4845
4846 bool
4847 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
4848 {
4849 rtx size;
4850
4851 if (!MEM_P (x))
4852 return false;
4853
4854 size = MEM_SIZE (x);
4855 return size && INTVAL (size) == GET_MODE_SIZE (mode);
4856 }
4857
4858 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
4859 source of an "ext" instruction or the destination of an "ins"
4860 instruction. OP must be a register operand and the following
4861 conditions must hold:
4862
4863 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
4864 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4865 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4866
4867 Also reject lengths equal to a word as they are better handled
4868 by the move patterns. */
4869
4870 bool
4871 mips_use_ins_ext_p (rtx op, rtx size, rtx position)
4872 {
4873 HOST_WIDE_INT len, pos;
4874
4875 if (!ISA_HAS_EXT_INS
4876 || !register_operand (op, VOIDmode)
4877 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
4878 return false;
4879
4880 len = INTVAL (size);
4881 pos = INTVAL (position);
4882
4883 if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
4884 || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op)))
4885 return false;
4886
4887 return true;
4888 }
4889
4890 /* Set up globals to generate code for the ISA or processor
4891 described by INFO. */
4892
4893 static void
4894 mips_set_architecture (const struct mips_cpu_info *info)
4895 {
4896 if (info != 0)
4897 {
4898 mips_arch_info = info;
4899 mips_arch = info->cpu;
4900 mips_isa = info->isa;
4901 }
4902 }
4903
4904
4905 /* Likewise for tuning. */
4906
4907 static void
4908 mips_set_tune (const struct mips_cpu_info *info)
4909 {
4910 if (info != 0)
4911 {
4912 mips_tune_info = info;
4913 mips_tune = info->cpu;
4914 }
4915 }
4916
4917 /* Implement TARGET_HANDLE_OPTION. */
4918
4919 static bool
4920 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
4921 {
4922 switch (code)
4923 {
4924 case OPT_mabi_:
4925 if (strcmp (arg, "32") == 0)
4926 mips_abi = ABI_32;
4927 else if (strcmp (arg, "o64") == 0)
4928 mips_abi = ABI_O64;
4929 else if (strcmp (arg, "n32") == 0)
4930 mips_abi = ABI_N32;
4931 else if (strcmp (arg, "64") == 0)
4932 mips_abi = ABI_64;
4933 else if (strcmp (arg, "eabi") == 0)
4934 mips_abi = ABI_EABI;
4935 else
4936 return false;
4937 return true;
4938
4939 case OPT_march_:
4940 case OPT_mtune_:
4941 return mips_parse_cpu (arg) != 0;
4942
4943 case OPT_mips:
4944 mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
4945 return mips_isa_info != 0;
4946
4947 case OPT_mno_flush_func:
4948 mips_cache_flush_func = NULL;
4949 return true;
4950
4951 default:
4952 return true;
4953 }
4954 }
4955
4956 /* Set up the threshold for data to go into the small data area, instead
4957 of the normal data area, and detect any conflicts in the switches. */
4958
4959 void
4960 override_options (void)
4961 {
4962 int i, start, regno;
4963 enum machine_mode mode;
4964
4965 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4966 SUBTARGET_OVERRIDE_OPTIONS;
4967 #endif
4968
4969 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4970
4971 /* The following code determines the architecture and register size.
4972 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4973 The GAS and GCC code should be kept in sync as much as possible. */
4974
4975 if (mips_arch_string != 0)
4976 mips_set_architecture (mips_parse_cpu (mips_arch_string));
4977
4978 if (mips_isa_info != 0)
4979 {
4980 if (mips_arch_info == 0)
4981 mips_set_architecture (mips_isa_info);
4982 else if (mips_arch_info->isa != mips_isa_info->isa)
4983 error ("-%s conflicts with the other architecture options, "
4984 "which specify a %s processor",
4985 mips_isa_info->name,
4986 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
4987 }
4988
4989 if (mips_arch_info == 0)
4990 {
4991 #ifdef MIPS_CPU_STRING_DEFAULT
4992 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
4993 #else
4994 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4995 #endif
4996 }
4997
4998 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4999 error ("-march=%s is not compatible with the selected ABI",
5000 mips_arch_info->name);
5001
5002 /* Optimize for mips_arch, unless -mtune selects a different processor. */
5003 if (mips_tune_string != 0)
5004 mips_set_tune (mips_parse_cpu (mips_tune_string));
5005
5006 if (mips_tune_info == 0)
5007 mips_set_tune (mips_arch_info);
5008
5009 /* Set cost structure for the processor. */
5010 if (optimize_size)
5011 mips_cost = &mips_rtx_cost_optimize_size;
5012 else
5013 mips_cost = &mips_rtx_cost_data[mips_tune];
5014
5015 if ((target_flags_explicit & MASK_64BIT) != 0)
5016 {
5017 /* The user specified the size of the integer registers. Make sure
5018 it agrees with the ABI and ISA. */
5019 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
5020 error ("-mgp64 used with a 32-bit processor");
5021 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
5022 error ("-mgp32 used with a 64-bit ABI");
5023 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
5024 error ("-mgp64 used with a 32-bit ABI");
5025 }
5026 else
5027 {
5028 /* Infer the integer register size from the ABI and processor.
5029 Restrict ourselves to 32-bit registers if that's all the
5030 processor has, or if the ABI cannot handle 64-bit registers. */
5031 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
5032 target_flags &= ~MASK_64BIT;
5033 else
5034 target_flags |= MASK_64BIT;
5035 }
5036
5037 if ((target_flags_explicit & MASK_FLOAT64) != 0)
5038 {
5039 /* Really, -mfp32 and -mfp64 are ornamental options. There's
5040 only one right answer here. */
5041 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
5042 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
5043 else if (!TARGET_64BIT && TARGET_FLOAT64
5044 && !(ISA_HAS_MXHC1 && mips_abi == ABI_32))
5045 error ("-mgp32 and -mfp64 can only be combined if the target"
5046 " supports the mfhc1 and mthc1 instructions");
5047 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
5048 error ("unsupported combination: %s", "-mfp64 -msingle-float");
5049 }
5050 else
5051 {
5052 /* -msingle-float selects 32-bit float registers. Otherwise the
5053 float registers should be the same size as the integer ones. */
5054 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
5055 target_flags |= MASK_FLOAT64;
5056 else
5057 target_flags &= ~MASK_FLOAT64;
5058 }
5059
5060 /* End of code shared with GAS. */
5061
5062 if ((target_flags_explicit & MASK_LONG64) == 0)
5063 {
5064 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
5065 target_flags |= MASK_LONG64;
5066 else
5067 target_flags &= ~MASK_LONG64;
5068 }
5069
5070 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
5071 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
5072 {
5073 /* For some configurations, it is useful to have -march control
5074 the default setting of MASK_SOFT_FLOAT. */
5075 switch ((int) mips_arch)
5076 {
5077 case PROCESSOR_R4100:
5078 case PROCESSOR_R4111:
5079 case PROCESSOR_R4120:
5080 case PROCESSOR_R4130:
5081 target_flags |= MASK_SOFT_FLOAT;
5082 break;
5083
5084 default:
5085 target_flags &= ~MASK_SOFT_FLOAT;
5086 break;
5087 }
5088 }
5089
5090 if (!TARGET_OLDABI)
5091 flag_pcc_struct_return = 0;
5092
5093 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
5094 {
5095 /* If neither -mbranch-likely nor -mno-branch-likely was given
5096 on the command line, set MASK_BRANCHLIKELY based on the target
5097 architecture.
5098
5099 By default, we enable use of Branch Likely instructions on
5100 all architectures which support them with the following
5101 exceptions: when creating MIPS32 or MIPS64 code, and when
5102 tuning for architectures where their use tends to hurt
5103 performance.
5104
5105 The MIPS32 and MIPS64 architecture specifications say "Software
5106 is strongly encouraged to avoid use of Branch Likely
5107 instructions, as they will be removed from a future revision
5108 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
5109 issue those instructions unless instructed to do so by
5110 -mbranch-likely. */
5111 if (ISA_HAS_BRANCHLIKELY
5112 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
5113 && !(TUNE_MIPS5500 || TUNE_SB1))
5114 target_flags |= MASK_BRANCHLIKELY;
5115 else
5116 target_flags &= ~MASK_BRANCHLIKELY;
5117 }
5118 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
5119 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
5120
5121 /* The effect of -mabicalls isn't defined for the EABI. */
5122 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
5123 {
5124 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
5125 target_flags &= ~MASK_ABICALLS;
5126 }
5127
5128 if (TARGET_ABICALLS)
5129 {
5130 /* We need to set flag_pic for executables as well as DSOs
5131 because we may reference symbols that are not defined in
5132 the final executable. (MIPS does not use things like
5133 copy relocs, for example.)
5134
5135 Also, there is a body of code that uses __PIC__ to distinguish
5136 between -mabicalls and -mno-abicalls code. */
5137 flag_pic = 1;
5138 if (mips_section_threshold > 0)
5139 warning (0, "%<-G%> is incompatible with %<-mabicalls%>");
5140 }
5141
5142 if (TARGET_VXWORKS_RTP && mips_section_threshold > 0)
5143 warning (0, "-G and -mrtp are incompatible");
5144
5145 /* mips_split_addresses is a half-way house between explicit
5146 relocations and the traditional assembler macros. It can
5147 split absolute 32-bit symbolic constants into a high/lo_sum
5148 pair but uses macros for other sorts of access.
5149
5150 Like explicit relocation support for REL targets, it relies
5151 on GNU extensions in the assembler and the linker.
5152
5153 Although this code should work for -O0, it has traditionally
5154 been treated as an optimization. */
5155 if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
5156 && optimize && !flag_pic
5157 && !ABI_HAS_64BIT_SYMBOLS)
5158 mips_split_addresses = 1;
5159 else
5160 mips_split_addresses = 0;
5161
5162 /* -mvr4130-align is a "speed over size" optimization: it usually produces
5163 faster code, but at the expense of more nops. Enable it at -O3 and
5164 above. */
5165 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
5166 target_flags |= MASK_VR4130_ALIGN;
5167
5168 /* When compiling for the mips16, we cannot use floating point. We
5169 record the original hard float value in mips16_hard_float. */
5170 if (TARGET_MIPS16)
5171 {
5172 if (TARGET_SOFT_FLOAT)
5173 mips16_hard_float = 0;
5174 else
5175 mips16_hard_float = 1;
5176 target_flags |= MASK_SOFT_FLOAT;
5177
5178 /* Don't run the scheduler before reload, since it tends to
5179 increase register pressure. */
5180 flag_schedule_insns = 0;
5181
5182 /* Don't do hot/cold partitioning. The constant layout code expects
5183 the whole function to be in a single section. */
5184 flag_reorder_blocks_and_partition = 0;
5185
5186 /* Silently disable -mexplicit-relocs since it doesn't apply
5187 to mips16 code. Even so, it would overly pedantic to warn
5188 about "-mips16 -mexplicit-relocs", especially given that
5189 we use a %gprel() operator. */
5190 target_flags &= ~MASK_EXPLICIT_RELOCS;
5191 }
5192
5193 /* When using explicit relocs, we call dbr_schedule from within
5194 mips_reorg. */
5195 if (TARGET_EXPLICIT_RELOCS)
5196 {
5197 mips_flag_delayed_branch = flag_delayed_branch;
5198 flag_delayed_branch = 0;
5199 }
5200
5201 #ifdef MIPS_TFMODE_FORMAT
5202 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
5203 #endif
5204
5205 /* Make sure that the user didn't turn off paired single support when
5206 MIPS-3D support is requested. */
5207 if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
5208 && !TARGET_PAIRED_SINGLE_FLOAT)
5209 error ("-mips3d requires -mpaired-single");
5210
5211 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
5212 if (TARGET_MIPS3D)
5213 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
5214
5215 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
5216 and TARGET_HARD_FLOAT are both true. */
5217 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
5218 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
5219
5220 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
5221 enabled. */
5222 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
5223 error ("-mips3d/-mpaired-single must be used with -mips64");
5224
5225 /* If TARGET_DSPR2, enable MASK_DSP. */
5226 if (TARGET_DSPR2)
5227 target_flags |= MASK_DSP;
5228
5229 if (TARGET_MIPS16 && TARGET_DSP)
5230 error ("-mips16 and -mdsp cannot be used together");
5231
5232 mips_print_operand_punct['?'] = 1;
5233 mips_print_operand_punct['#'] = 1;
5234 mips_print_operand_punct['/'] = 1;
5235 mips_print_operand_punct['&'] = 1;
5236 mips_print_operand_punct['!'] = 1;
5237 mips_print_operand_punct['*'] = 1;
5238 mips_print_operand_punct['@'] = 1;
5239 mips_print_operand_punct['.'] = 1;
5240 mips_print_operand_punct['('] = 1;
5241 mips_print_operand_punct[')'] = 1;
5242 mips_print_operand_punct['['] = 1;
5243 mips_print_operand_punct[']'] = 1;
5244 mips_print_operand_punct['<'] = 1;
5245 mips_print_operand_punct['>'] = 1;
5246 mips_print_operand_punct['{'] = 1;
5247 mips_print_operand_punct['}'] = 1;
5248 mips_print_operand_punct['^'] = 1;
5249 mips_print_operand_punct['$'] = 1;
5250 mips_print_operand_punct['+'] = 1;
5251 mips_print_operand_punct['~'] = 1;
5252
5253 /* Set up array to map GCC register number to debug register number.
5254 Ignore the special purpose register numbers. */
5255
5256 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5257 mips_dbx_regno[i] = -1;
5258
5259 start = GP_DBX_FIRST - GP_REG_FIRST;
5260 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
5261 mips_dbx_regno[i] = i + start;
5262
5263 start = FP_DBX_FIRST - FP_REG_FIRST;
5264 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
5265 mips_dbx_regno[i] = i + start;
5266
5267 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
5268 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
5269
5270 /* Set up array giving whether a given register can hold a given mode. */
5271
5272 for (mode = VOIDmode;
5273 mode != MAX_MACHINE_MODE;
5274 mode = (enum machine_mode) ((int)mode + 1))
5275 {
5276 register int size = GET_MODE_SIZE (mode);
5277 register enum mode_class class = GET_MODE_CLASS (mode);
5278
5279 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5280 {
5281 register int temp;
5282
5283 if (mode == CCV2mode)
5284 temp = (ISA_HAS_8CC
5285 && ST_REG_P (regno)
5286 && (regno - ST_REG_FIRST) % 2 == 0);
5287
5288 else if (mode == CCV4mode)
5289 temp = (ISA_HAS_8CC
5290 && ST_REG_P (regno)
5291 && (regno - ST_REG_FIRST) % 4 == 0);
5292
5293 else if (mode == CCmode)
5294 {
5295 if (! ISA_HAS_8CC)
5296 temp = (regno == FPSW_REGNUM);
5297 else
5298 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5299 || FP_REG_P (regno));
5300 }
5301
5302 else if (GP_REG_P (regno))
5303 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5304
5305 else if (FP_REG_P (regno))
5306 temp = ((((regno % MAX_FPRS_PER_FMT) == 0)
5307 || (MIN_FPRS_PER_FMT == 1
5308 && size <= UNITS_PER_FPREG))
5309 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT
5310 || class == MODE_VECTOR_FLOAT)
5311 && size <= UNITS_PER_FPVALUE)
5312 /* Allow integer modes that fit into a single
5313 register. We need to put integers into FPRs
5314 when using instructions like cvt and trunc.
5315 We can't allow sizes smaller than a word,
5316 the FPU has no appropriate load/store
5317 instructions for those. */
5318 || (class == MODE_INT
5319 && size >= MIN_UNITS_PER_WORD
5320 && size <= UNITS_PER_FPREG)
5321 /* Allow TFmode for CCmode reloads. */
5322 || (ISA_HAS_8CC && mode == TFmode)));
5323
5324 else if (ACC_REG_P (regno))
5325 temp = (INTEGRAL_MODE_P (mode)
5326 && (size <= UNITS_PER_WORD
5327 || (ACC_HI_REG_P (regno)
5328 && size == 2 * UNITS_PER_WORD)));
5329
5330 else if (ALL_COP_REG_P (regno))
5331 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
5332 else
5333 temp = 0;
5334
5335 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5336 }
5337 }
5338
5339 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5340 initialized yet, so we can't use that here. */
5341 gpr_mode = TARGET_64BIT ? DImode : SImode;
5342
5343 /* Provide default values for align_* for 64-bit targets. */
5344 if (TARGET_64BIT && !TARGET_MIPS16)
5345 {
5346 if (align_loops == 0)
5347 align_loops = 8;
5348 if (align_jumps == 0)
5349 align_jumps = 8;
5350 if (align_functions == 0)
5351 align_functions = 8;
5352 }
5353
5354 /* Function to allocate machine-dependent function status. */
5355 init_machine_status = &mips_init_machine_status;
5356
5357 if (ABI_HAS_64BIT_SYMBOLS)
5358 {
5359 if (TARGET_EXPLICIT_RELOCS)
5360 {
5361 mips_split_p[SYMBOL_64_HIGH] = true;
5362 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
5363 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
5364
5365 mips_split_p[SYMBOL_64_MID] = true;
5366 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
5367 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
5368
5369 mips_split_p[SYMBOL_64_LOW] = true;
5370 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
5371 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
5372
5373 mips_split_p[SYMBOL_GENERAL] = true;
5374 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5375 }
5376 }
5377 else
5378 {
5379 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
5380 {
5381 mips_split_p[SYMBOL_GENERAL] = true;
5382 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
5383 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5384 }
5385 }
5386
5387 if (TARGET_MIPS16)
5388 {
5389 /* The high part is provided by a pseudo copy of $gp. */
5390 mips_split_p[SYMBOL_SMALL_DATA] = true;
5391 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
5392 }
5393
5394 if (TARGET_EXPLICIT_RELOCS)
5395 {
5396 /* Small data constants are kept whole until after reload,
5397 then lowered by mips_rewrite_small_data. */
5398 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
5399
5400 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
5401 if (TARGET_NEWABI)
5402 {
5403 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
5404 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
5405 }
5406 else
5407 {
5408 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
5409 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
5410 }
5411
5412 if (TARGET_XGOT)
5413 {
5414 /* The HIGH and LO_SUM are matched by special .md patterns. */
5415 mips_split_p[SYMBOL_GOT_DISP] = true;
5416
5417 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
5418 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
5419 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
5420
5421 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
5422 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
5423 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
5424 }
5425 else
5426 {
5427 if (TARGET_NEWABI)
5428 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
5429 else
5430 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
5431 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
5432 }
5433 }
5434
5435 if (TARGET_NEWABI)
5436 {
5437 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
5438 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
5439 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
5440 }
5441
5442 /* Thread-local relocation operators. */
5443 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
5444 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
5445 mips_split_p[SYMBOL_DTPREL] = 1;
5446 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
5447 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
5448 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
5449 mips_split_p[SYMBOL_TPREL] = 1;
5450 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
5451 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
5452
5453 mips_lo_relocs[SYMBOL_HALF] = "%half(";
5454
5455 /* We don't have a thread pointer access instruction on MIPS16, or
5456 appropriate TLS relocations. */
5457 if (TARGET_MIPS16)
5458 targetm.have_tls = false;
5459
5460 /* Default to working around R4000 errata only if the processor
5461 was selected explicitly. */
5462 if ((target_flags_explicit & MASK_FIX_R4000) == 0
5463 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
5464 target_flags |= MASK_FIX_R4000;
5465
5466 /* Default to working around R4400 errata only if the processor
5467 was selected explicitly. */
5468 if ((target_flags_explicit & MASK_FIX_R4400) == 0
5469 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
5470 target_flags |= MASK_FIX_R4400;
5471 }
5472
5473 /* Implement CONDITIONAL_REGISTER_USAGE. */
5474
5475 void
5476 mips_conditional_register_usage (void)
5477 {
5478 if (!TARGET_DSP)
5479 {
5480 int regno;
5481
5482 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
5483 fixed_regs[regno] = call_used_regs[regno] = 1;
5484 }
5485 if (!TARGET_HARD_FLOAT)
5486 {
5487 int regno;
5488
5489 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5490 fixed_regs[regno] = call_used_regs[regno] = 1;
5491 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5492 fixed_regs[regno] = call_used_regs[regno] = 1;
5493 }
5494 else if (! ISA_HAS_8CC)
5495 {
5496 int regno;
5497
5498 /* We only have a single condition code register. We
5499 implement this by hiding all the condition code registers,
5500 and generating RTL that refers directly to ST_REG_FIRST. */
5501 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5502 fixed_regs[regno] = call_used_regs[regno] = 1;
5503 }
5504 /* In mips16 mode, we permit the $t temporary registers to be used
5505 for reload. We prohibit the unused $s registers, since they
5506 are caller saved, and saving them via a mips16 register would
5507 probably waste more time than just reloading the value. */
5508 if (TARGET_MIPS16)
5509 {
5510 fixed_regs[18] = call_used_regs[18] = 1;
5511 fixed_regs[19] = call_used_regs[19] = 1;
5512 fixed_regs[20] = call_used_regs[20] = 1;
5513 fixed_regs[21] = call_used_regs[21] = 1;
5514 fixed_regs[22] = call_used_regs[22] = 1;
5515 fixed_regs[23] = call_used_regs[23] = 1;
5516 fixed_regs[26] = call_used_regs[26] = 1;
5517 fixed_regs[27] = call_used_regs[27] = 1;
5518 fixed_regs[30] = call_used_regs[30] = 1;
5519 }
5520 /* fp20-23 are now caller saved. */
5521 if (mips_abi == ABI_64)
5522 {
5523 int regno;
5524 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5525 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5526 }
5527 /* Odd registers from fp21 to fp31 are now caller saved. */
5528 if (mips_abi == ABI_N32)
5529 {
5530 int regno;
5531 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5532 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5533 }
5534 }
5535
5536 /* Allocate a chunk of memory for per-function machine-dependent data. */
5537 static struct machine_function *
5538 mips_init_machine_status (void)
5539 {
5540 return ((struct machine_function *)
5541 ggc_alloc_cleared (sizeof (struct machine_function)));
5542 }
5543
5544 /* On the mips16, we want to allocate $24 (T_REG) before other
5545 registers for instructions for which it is possible. This helps
5546 avoid shuffling registers around in order to set up for an xor,
5547 encouraging the compiler to use a cmp instead. */
5548
5549 void
5550 mips_order_regs_for_local_alloc (void)
5551 {
5552 register int i;
5553
5554 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5555 reg_alloc_order[i] = i;
5556
5557 if (TARGET_MIPS16)
5558 {
5559 /* It really doesn't matter where we put register 0, since it is
5560 a fixed register anyhow. */
5561 reg_alloc_order[0] = 24;
5562 reg_alloc_order[24] = 0;
5563 }
5564 }
5565
5566 \f
5567 /* The MIPS debug format wants all automatic variables and arguments
5568 to be in terms of the virtual frame pointer (stack pointer before
5569 any adjustment in the function), while the MIPS 3.0 linker wants
5570 the frame pointer to be the stack pointer after the initial
5571 adjustment. So, we do the adjustment here. The arg pointer (which
5572 is eliminated) points to the virtual frame pointer, while the frame
5573 pointer (which may be eliminated) points to the stack pointer after
5574 the initial adjustments. */
5575
5576 HOST_WIDE_INT
5577 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5578 {
5579 rtx offset2 = const0_rtx;
5580 rtx reg = eliminate_constant_term (addr, &offset2);
5581
5582 if (offset == 0)
5583 offset = INTVAL (offset2);
5584
5585 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5586 || reg == hard_frame_pointer_rtx)
5587 {
5588 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5589 ? compute_frame_size (get_frame_size ())
5590 : cfun->machine->frame.total_size;
5591
5592 /* MIPS16 frame is smaller */
5593 if (frame_pointer_needed && TARGET_MIPS16)
5594 frame_size -= cfun->machine->frame.args_size;
5595
5596 offset = offset - frame_size;
5597 }
5598
5599 /* sdbout_parms does not want this to crash for unrecognized cases. */
5600 #if 0
5601 else if (reg != arg_pointer_rtx)
5602 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5603 addr);
5604 #endif
5605
5606 return offset;
5607 }
5608 \f
5609 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5610
5611 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5612 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5613 'h' OP is HIGH, prints %hi(X),
5614 'd' output integer constant in decimal,
5615 'z' if the operand is 0, use $0 instead of normal operand.
5616 'D' print second part of double-word register or memory operand.
5617 'L' print low-order register of double-word register operand.
5618 'M' print high-order register of double-word register operand.
5619 'C' print part of opcode for a branch condition.
5620 'F' print part of opcode for a floating-point branch condition.
5621 'N' print part of opcode for a branch condition, inverted.
5622 'W' print part of opcode for a floating-point branch condition, inverted.
5623 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
5624 'z' for (eq:?I ...), 'n' for (ne:?I ...).
5625 't' like 'T', but with the EQ/NE cases reversed
5626 'Y' for a CONST_INT X, print mips_fp_conditions[X]
5627 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
5628 'R' print the reloc associated with LO_SUM
5629 'q' print DSP accumulator registers
5630
5631 The punctuation characters are:
5632
5633 '(' Turn on .set noreorder
5634 ')' Turn on .set reorder
5635 '[' Turn on .set noat
5636 ']' Turn on .set at
5637 '<' Turn on .set nomacro
5638 '>' Turn on .set macro
5639 '{' Turn on .set volatile (not GAS)
5640 '}' Turn on .set novolatile (not GAS)
5641 '&' Turn on .set noreorder if filling delay slots
5642 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5643 '!' Turn on .set nomacro if filling delay slots
5644 '#' Print nop if in a .set noreorder section.
5645 '/' Like '#', but does nothing within a delayed branch sequence
5646 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5647 '@' Print the name of the assembler temporary register (at or $1).
5648 '.' Print the name of the register with a hard-wired zero (zero or $0).
5649 '^' Print the name of the pic call-through register (t9 or $25).
5650 '$' Print the name of the stack pointer register (sp or $29).
5651 '+' Print the name of the gp register (usually gp or $28).
5652 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5653
5654 void
5655 print_operand (FILE *file, rtx op, int letter)
5656 {
5657 register enum rtx_code code;
5658
5659 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5660 {
5661 switch (letter)
5662 {
5663 case '?':
5664 if (mips_branch_likely)
5665 putc ('l', file);
5666 break;
5667
5668 case '@':
5669 fputs (reg_names [GP_REG_FIRST + 1], file);
5670 break;
5671
5672 case '^':
5673 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5674 break;
5675
5676 case '.':
5677 fputs (reg_names [GP_REG_FIRST + 0], file);
5678 break;
5679
5680 case '$':
5681 fputs (reg_names[STACK_POINTER_REGNUM], file);
5682 break;
5683
5684 case '+':
5685 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5686 break;
5687
5688 case '&':
5689 if (final_sequence != 0 && set_noreorder++ == 0)
5690 fputs (".set\tnoreorder\n\t", file);
5691 break;
5692
5693 case '*':
5694 if (final_sequence != 0)
5695 {
5696 if (set_noreorder++ == 0)
5697 fputs (".set\tnoreorder\n\t", file);
5698
5699 if (set_nomacro++ == 0)
5700 fputs (".set\tnomacro\n\t", file);
5701 }
5702 break;
5703
5704 case '!':
5705 if (final_sequence != 0 && set_nomacro++ == 0)
5706 fputs ("\n\t.set\tnomacro", file);
5707 break;
5708
5709 case '#':
5710 if (set_noreorder != 0)
5711 fputs ("\n\tnop", file);
5712 break;
5713
5714 case '/':
5715 /* Print an extra newline so that the delayed insn is separated
5716 from the following ones. This looks neater and is consistent
5717 with non-nop delayed sequences. */
5718 if (set_noreorder != 0 && final_sequence == 0)
5719 fputs ("\n\tnop\n", file);
5720 break;
5721
5722 case '(':
5723 if (set_noreorder++ == 0)
5724 fputs (".set\tnoreorder\n\t", file);
5725 break;
5726
5727 case ')':
5728 if (set_noreorder == 0)
5729 error ("internal error: %%) found without a %%( in assembler pattern");
5730
5731 else if (--set_noreorder == 0)
5732 fputs ("\n\t.set\treorder", file);
5733
5734 break;
5735
5736 case '[':
5737 if (set_noat++ == 0)
5738 fputs (".set\tnoat\n\t", file);
5739 break;
5740
5741 case ']':
5742 if (set_noat == 0)
5743 error ("internal error: %%] found without a %%[ in assembler pattern");
5744 else if (--set_noat == 0)
5745 fputs ("\n\t.set\tat", file);
5746
5747 break;
5748
5749 case '<':
5750 if (set_nomacro++ == 0)
5751 fputs (".set\tnomacro\n\t", file);
5752 break;
5753
5754 case '>':
5755 if (set_nomacro == 0)
5756 error ("internal error: %%> found without a %%< in assembler pattern");
5757 else if (--set_nomacro == 0)
5758 fputs ("\n\t.set\tmacro", file);
5759
5760 break;
5761
5762 case '{':
5763 if (set_volatile++ == 0)
5764 fputs ("#.set\tvolatile\n\t", file);
5765 break;
5766
5767 case '}':
5768 if (set_volatile == 0)
5769 error ("internal error: %%} found without a %%{ in assembler pattern");
5770 else if (--set_volatile == 0)
5771 fputs ("\n\t#.set\tnovolatile", file);
5772
5773 break;
5774
5775 case '~':
5776 {
5777 if (align_labels_log > 0)
5778 ASM_OUTPUT_ALIGN (file, align_labels_log);
5779 }
5780 break;
5781
5782 default:
5783 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5784 break;
5785 }
5786
5787 return;
5788 }
5789
5790 if (! op)
5791 {
5792 error ("PRINT_OPERAND null pointer");
5793 return;
5794 }
5795
5796 code = GET_CODE (op);
5797
5798 if (letter == 'C')
5799 switch (code)
5800 {
5801 case EQ: fputs ("eq", file); break;
5802 case NE: fputs ("ne", file); break;
5803 case GT: fputs ("gt", file); break;
5804 case GE: fputs ("ge", file); break;
5805 case LT: fputs ("lt", file); break;
5806 case LE: fputs ("le", file); break;
5807 case GTU: fputs ("gtu", file); break;
5808 case GEU: fputs ("geu", file); break;
5809 case LTU: fputs ("ltu", file); break;
5810 case LEU: fputs ("leu", file); break;
5811 default:
5812 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5813 }
5814
5815 else if (letter == 'N')
5816 switch (code)
5817 {
5818 case EQ: fputs ("ne", file); break;
5819 case NE: fputs ("eq", file); break;
5820 case GT: fputs ("le", file); break;
5821 case GE: fputs ("lt", file); break;
5822 case LT: fputs ("ge", file); break;
5823 case LE: fputs ("gt", file); break;
5824 case GTU: fputs ("leu", file); break;
5825 case GEU: fputs ("ltu", file); break;
5826 case LTU: fputs ("geu", file); break;
5827 case LEU: fputs ("gtu", file); break;
5828 default:
5829 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5830 }
5831
5832 else if (letter == 'F')
5833 switch (code)
5834 {
5835 case EQ: fputs ("c1f", file); break;
5836 case NE: fputs ("c1t", file); break;
5837 default:
5838 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5839 }
5840
5841 else if (letter == 'W')
5842 switch (code)
5843 {
5844 case EQ: fputs ("c1t", file); break;
5845 case NE: fputs ("c1f", file); break;
5846 default:
5847 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5848 }
5849
5850 else if (letter == 'h')
5851 {
5852 if (GET_CODE (op) == HIGH)
5853 op = XEXP (op, 0);
5854
5855 print_operand_reloc (file, op, mips_hi_relocs);
5856 }
5857
5858 else if (letter == 'R')
5859 print_operand_reloc (file, op, mips_lo_relocs);
5860
5861 else if (letter == 'Y')
5862 {
5863 if (GET_CODE (op) == CONST_INT
5864 && ((unsigned HOST_WIDE_INT) INTVAL (op)
5865 < ARRAY_SIZE (mips_fp_conditions)))
5866 fputs (mips_fp_conditions[INTVAL (op)], file);
5867 else
5868 output_operand_lossage ("invalid %%Y value");
5869 }
5870
5871 else if (letter == 'Z')
5872 {
5873 if (ISA_HAS_8CC)
5874 {
5875 print_operand (file, op, 0);
5876 fputc (',', file);
5877 }
5878 }
5879
5880 else if (letter == 'q')
5881 {
5882 int regnum;
5883
5884 if (code != REG)
5885 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5886
5887 regnum = REGNO (op);
5888 if (MD_REG_P (regnum))
5889 fprintf (file, "$ac0");
5890 else if (DSP_ACC_REG_P (regnum))
5891 fprintf (file, "$ac%c", reg_names[regnum][3]);
5892 else
5893 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5894 }
5895
5896 else if (code == REG || code == SUBREG)
5897 {
5898 register int regnum;
5899
5900 if (code == REG)
5901 regnum = REGNO (op);
5902 else
5903 regnum = true_regnum (op);
5904
5905 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5906 || (letter == 'L' && WORDS_BIG_ENDIAN)
5907 || letter == 'D')
5908 regnum++;
5909
5910 fprintf (file, "%s", reg_names[regnum]);
5911 }
5912
5913 else if (code == MEM)
5914 {
5915 if (letter == 'D')
5916 output_address (plus_constant (XEXP (op, 0), 4));
5917 else
5918 output_address (XEXP (op, 0));
5919 }
5920
5921 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5922 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5923
5924 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5925 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5926
5927 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5928 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5929
5930 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5931 fputs (reg_names[GP_REG_FIRST], file);
5932
5933 else if (letter == 'd' || letter == 'x' || letter == 'X')
5934 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5935
5936 else if (letter == 'T' || letter == 't')
5937 {
5938 int truth = (code == NE) == (letter == 'T');
5939 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
5940 }
5941
5942 else if (CONST_GP_P (op))
5943 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5944
5945 else
5946 output_addr_const (file, op);
5947 }
5948
5949
5950 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5951 RELOCS is the array of relocations to use. */
5952
5953 static void
5954 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5955 {
5956 enum mips_symbol_type symbol_type;
5957 const char *p;
5958 rtx base, offset;
5959
5960 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5961 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5962
5963 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5964 split_const (op, &base, &offset);
5965 if (UNSPEC_ADDRESS_P (base))
5966 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
5967
5968 fputs (relocs[symbol_type], file);
5969 output_addr_const (file, op);
5970 for (p = relocs[symbol_type]; *p != 0; p++)
5971 if (*p == '(')
5972 fputc (')', file);
5973 }
5974 \f
5975 /* Output address operand X to FILE. */
5976
5977 void
5978 print_operand_address (FILE *file, rtx x)
5979 {
5980 struct mips_address_info addr;
5981
5982 if (mips_classify_address (&addr, x, word_mode, true))
5983 switch (addr.type)
5984 {
5985 case ADDRESS_REG:
5986 print_operand (file, addr.offset, 0);
5987 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5988 return;
5989
5990 case ADDRESS_LO_SUM:
5991 print_operand (file, addr.offset, 'R');
5992 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5993 return;
5994
5995 case ADDRESS_CONST_INT:
5996 output_addr_const (file, x);
5997 fprintf (file, "(%s)", reg_names[0]);
5998 return;
5999
6000 case ADDRESS_SYMBOLIC:
6001 output_addr_const (file, x);
6002 return;
6003 }
6004 gcc_unreachable ();
6005 }
6006 \f
6007 /* When using assembler macros, keep track of all of small-data externs
6008 so that mips_file_end can emit the appropriate declarations for them.
6009
6010 In most cases it would be safe (though pointless) to emit .externs
6011 for other symbols too. One exception is when an object is within
6012 the -G limit but declared by the user to be in a section other
6013 than .sbss or .sdata. */
6014
6015 void
6016 mips_output_external (FILE *file, tree decl, const char *name)
6017 {
6018 default_elf_asm_output_external (file, decl, name);
6019
6020 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
6021 set in order to avoid putting out names that are never really
6022 used. */
6023 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
6024 {
6025 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
6026 {
6027 fputs ("\t.extern\t", file);
6028 assemble_name (file, name);
6029 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
6030 int_size_in_bytes (TREE_TYPE (decl)));
6031 }
6032 else if (TARGET_IRIX
6033 && mips_abi == ABI_32
6034 && TREE_CODE (decl) == FUNCTION_DECL)
6035 {
6036 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
6037 `.global name .text' directive for every used but
6038 undefined function. If we don't, the linker may perform
6039 an optimization (skipping over the insns that set $gp)
6040 when it is unsafe. */
6041 fputs ("\t.globl ", file);
6042 assemble_name (file, name);
6043 fputs (" .text\n", file);
6044 }
6045 }
6046 }
6047 \f
6048 /* Emit a new filename to a stream. If we are smuggling stabs, try to
6049 put out a MIPS ECOFF file and a stab. */
6050
6051 void
6052 mips_output_filename (FILE *stream, const char *name)
6053 {
6054
6055 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
6056 directives. */
6057 if (write_symbols == DWARF2_DEBUG)
6058 return;
6059 else if (mips_output_filename_first_time)
6060 {
6061 mips_output_filename_first_time = 0;
6062 num_source_filenames += 1;
6063 current_function_file = name;
6064 fprintf (stream, "\t.file\t%d ", num_source_filenames);
6065 output_quoted_string (stream, name);
6066 putc ('\n', stream);
6067 }
6068
6069 /* If we are emitting stabs, let dbxout.c handle this (except for
6070 the mips_output_filename_first_time case). */
6071 else if (write_symbols == DBX_DEBUG)
6072 return;
6073
6074 else if (name != current_function_file
6075 && strcmp (name, current_function_file) != 0)
6076 {
6077 num_source_filenames += 1;
6078 current_function_file = name;
6079 fprintf (stream, "\t.file\t%d ", num_source_filenames);
6080 output_quoted_string (stream, name);
6081 putc ('\n', stream);
6082 }
6083 }
6084 \f
6085 /* Output an ASCII string, in a space-saving way. PREFIX is the string
6086 that should be written before the opening quote, such as "\t.ascii\t"
6087 for real string data or "\t# " for a comment. */
6088
6089 void
6090 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
6091 const char *prefix)
6092 {
6093 size_t i;
6094 int cur_pos = 17;
6095 register const unsigned char *string =
6096 (const unsigned char *)string_param;
6097
6098 fprintf (stream, "%s\"", prefix);
6099 for (i = 0; i < len; i++)
6100 {
6101 register int c = string[i];
6102
6103 if (ISPRINT (c))
6104 {
6105 if (c == '\\' || c == '\"')
6106 {
6107 putc ('\\', stream);
6108 cur_pos++;
6109 }
6110 putc (c, stream);
6111 cur_pos++;
6112 }
6113 else
6114 {
6115 fprintf (stream, "\\%03o", c);
6116 cur_pos += 4;
6117 }
6118
6119 if (cur_pos > 72 && i+1 < len)
6120 {
6121 cur_pos = 17;
6122 fprintf (stream, "\"\n%s\"", prefix);
6123 }
6124 }
6125 fprintf (stream, "\"\n");
6126 }
6127 \f
6128 /* Implement TARGET_ASM_FILE_START. */
6129
6130 static void
6131 mips_file_start (void)
6132 {
6133 default_file_start ();
6134
6135 if (!TARGET_IRIX)
6136 {
6137 /* Generate a special section to describe the ABI switches used to
6138 produce the resultant binary. This used to be done by the assembler
6139 setting bits in the ELF header's flags field, but we have run out of
6140 bits. GDB needs this information in order to be able to correctly
6141 debug these binaries. See the function mips_gdbarch_init() in
6142 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
6143 causes unnecessary IRIX 6 ld warnings. */
6144 const char * abi_string = NULL;
6145
6146 switch (mips_abi)
6147 {
6148 case ABI_32: abi_string = "abi32"; break;
6149 case ABI_N32: abi_string = "abiN32"; break;
6150 case ABI_64: abi_string = "abi64"; break;
6151 case ABI_O64: abi_string = "abiO64"; break;
6152 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
6153 default:
6154 gcc_unreachable ();
6155 }
6156 /* Note - we use fprintf directly rather than calling switch_to_section
6157 because in this way we can avoid creating an allocated section. We
6158 do not want this section to take up any space in the running
6159 executable. */
6160 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
6161
6162 /* There is no ELF header flag to distinguish long32 forms of the
6163 EABI from long64 forms. Emit a special section to help tools
6164 such as GDB. Do the same for o64, which is sometimes used with
6165 -mlong64. */
6166 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
6167 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
6168 TARGET_LONG64 ? 64 : 32);
6169
6170 /* Restore the default section. */
6171 fprintf (asm_out_file, "\t.previous\n");
6172
6173 #ifdef HAVE_AS_GNU_ATTRIBUTE
6174 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
6175 TARGET_HARD_FLOAT_ABI ? (TARGET_DOUBLE_FLOAT ? 1 : 2) : 3);
6176 #endif
6177 }
6178
6179 /* Generate the pseudo ops that System V.4 wants. */
6180 if (TARGET_ABICALLS)
6181 fprintf (asm_out_file, "\t.abicalls\n");
6182
6183 if (TARGET_MIPS16)
6184 fprintf (asm_out_file, "\t.set\tmips16\n");
6185
6186 if (flag_verbose_asm)
6187 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
6188 ASM_COMMENT_START,
6189 mips_section_threshold, mips_arch_info->name, mips_isa);
6190 }
6191
6192 #ifdef BSS_SECTION_ASM_OP
6193 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
6194 in the use of sbss. */
6195
6196 void
6197 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
6198 unsigned HOST_WIDE_INT size, int align)
6199 {
6200 extern tree last_assemble_variable_decl;
6201
6202 if (mips_in_small_data_p (decl))
6203 switch_to_section (get_named_section (NULL, ".sbss", 0));
6204 else
6205 switch_to_section (bss_section);
6206 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
6207 last_assemble_variable_decl = decl;
6208 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
6209 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
6210 }
6211 #endif
6212 \f
6213 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
6214 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
6215
6216 void
6217 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
6218 unsigned HOST_WIDE_INT size,
6219 unsigned int align)
6220 {
6221 /* If the target wants uninitialized const declarations in
6222 .rdata then don't put them in .comm. */
6223 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
6224 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
6225 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
6226 {
6227 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
6228 targetm.asm_out.globalize_label (stream, name);
6229
6230 switch_to_section (readonly_data_section);
6231 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
6232 mips_declare_object (stream, name, "",
6233 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
6234 size);
6235 }
6236 else
6237 mips_declare_common_object (stream, name, "\n\t.comm\t",
6238 size, align, true);
6239 }
6240
6241 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
6242 NAME is the name of the object and ALIGN is the required alignment
6243 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
6244 alignment argument. */
6245
6246 void
6247 mips_declare_common_object (FILE *stream, const char *name,
6248 const char *init_string,
6249 unsigned HOST_WIDE_INT size,
6250 unsigned int align, bool takes_alignment_p)
6251 {
6252 if (!takes_alignment_p)
6253 {
6254 size += (align / BITS_PER_UNIT) - 1;
6255 size -= size % (align / BITS_PER_UNIT);
6256 mips_declare_object (stream, name, init_string,
6257 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
6258 }
6259 else
6260 mips_declare_object (stream, name, init_string,
6261 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
6262 size, align / BITS_PER_UNIT);
6263 }
6264
6265 /* Emit either a label, .comm, or .lcomm directive. When using assembler
6266 macros, mark the symbol as written so that mips_file_end won't emit an
6267 .extern for it. STREAM is the output file, NAME is the name of the
6268 symbol, INIT_STRING is the string that should be written before the
6269 symbol and FINAL_STRING is the string that should be written after it.
6270 FINAL_STRING is a printf() format that consumes the remaining arguments. */
6271
6272 void
6273 mips_declare_object (FILE *stream, const char *name, const char *init_string,
6274 const char *final_string, ...)
6275 {
6276 va_list ap;
6277
6278 fputs (init_string, stream);
6279 assemble_name (stream, name);
6280 va_start (ap, final_string);
6281 vfprintf (stream, final_string, ap);
6282 va_end (ap);
6283
6284 if (!TARGET_EXPLICIT_RELOCS)
6285 {
6286 tree name_tree = get_identifier (name);
6287 TREE_ASM_WRITTEN (name_tree) = 1;
6288 }
6289 }
6290
6291 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
6292 extern int size_directive_output;
6293
6294 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
6295 definitions except that it uses mips_declare_object() to emit the label. */
6296
6297 void
6298 mips_declare_object_name (FILE *stream, const char *name,
6299 tree decl ATTRIBUTE_UNUSED)
6300 {
6301 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
6302 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
6303 #endif
6304
6305 size_directive_output = 0;
6306 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
6307 {
6308 HOST_WIDE_INT size;
6309
6310 size_directive_output = 1;
6311 size = int_size_in_bytes (TREE_TYPE (decl));
6312 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6313 }
6314
6315 mips_declare_object (stream, name, "", ":\n");
6316 }
6317
6318 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
6319
6320 void
6321 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
6322 {
6323 const char *name;
6324
6325 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
6326 if (!flag_inhibit_size_directive
6327 && DECL_SIZE (decl) != 0
6328 && !at_end && top_level
6329 && DECL_INITIAL (decl) == error_mark_node
6330 && !size_directive_output)
6331 {
6332 HOST_WIDE_INT size;
6333
6334 size_directive_output = 1;
6335 size = int_size_in_bytes (TREE_TYPE (decl));
6336 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6337 }
6338 }
6339 #endif
6340 \f
6341 /* Return true if X is a small data address that can be rewritten
6342 as a LO_SUM. */
6343
6344 static bool
6345 mips_rewrite_small_data_p (rtx x)
6346 {
6347 enum mips_symbol_type symbol_type;
6348
6349 return (TARGET_EXPLICIT_RELOCS
6350 && mips_symbolic_constant_p (x, &symbol_type)
6351 && symbol_type == SYMBOL_SMALL_DATA);
6352 }
6353
6354
6355 /* A for_each_rtx callback for mips_small_data_pattern_p. */
6356
6357 static int
6358 mips_small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6359 {
6360 if (GET_CODE (*loc) == LO_SUM)
6361 return -1;
6362
6363 return mips_rewrite_small_data_p (*loc);
6364 }
6365
6366 /* Return true if OP refers to small data symbols directly, not through
6367 a LO_SUM. */
6368
6369 bool
6370 mips_small_data_pattern_p (rtx op)
6371 {
6372 return for_each_rtx (&op, mips_small_data_pattern_1, 0);
6373 }
6374 \f
6375 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
6376
6377 static int
6378 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6379 {
6380 if (mips_rewrite_small_data_p (*loc))
6381 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
6382
6383 if (GET_CODE (*loc) == LO_SUM)
6384 return -1;
6385
6386 return 0;
6387 }
6388
6389 /* If possible, rewrite OP so that it refers to small data using
6390 explicit relocations. */
6391
6392 rtx
6393 mips_rewrite_small_data (rtx op)
6394 {
6395 op = copy_insn (op);
6396 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
6397 return op;
6398 }
6399 \f
6400 /* Return true if the current function has an insn that implicitly
6401 refers to $gp. */
6402
6403 static bool
6404 mips_function_has_gp_insn (void)
6405 {
6406 /* Don't bother rechecking if we found one last time. */
6407 if (!cfun->machine->has_gp_insn_p)
6408 {
6409 rtx insn;
6410
6411 push_topmost_sequence ();
6412 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6413 if (INSN_P (insn)
6414 && GET_CODE (PATTERN (insn)) != USE
6415 && GET_CODE (PATTERN (insn)) != CLOBBER
6416 && (get_attr_got (insn) != GOT_UNSET
6417 || small_data_pattern (PATTERN (insn), VOIDmode)))
6418 break;
6419 pop_topmost_sequence ();
6420
6421 cfun->machine->has_gp_insn_p = (insn != 0);
6422 }
6423 return cfun->machine->has_gp_insn_p;
6424 }
6425
6426
6427 /* Return the register that should be used as the global pointer
6428 within this function. Return 0 if the function doesn't need
6429 a global pointer. */
6430
6431 static unsigned int
6432 mips_global_pointer (void)
6433 {
6434 unsigned int regno;
6435
6436 /* $gp is always available unless we're using a GOT. */
6437 if (!TARGET_USE_GOT)
6438 return GLOBAL_POINTER_REGNUM;
6439
6440 /* We must always provide $gp when it is used implicitly. */
6441 if (!TARGET_EXPLICIT_RELOCS)
6442 return GLOBAL_POINTER_REGNUM;
6443
6444 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6445 a valid gp. */
6446 if (current_function_profile)
6447 return GLOBAL_POINTER_REGNUM;
6448
6449 /* If the function has a nonlocal goto, $gp must hold the correct
6450 global pointer for the target function. */
6451 if (current_function_has_nonlocal_goto)
6452 return GLOBAL_POINTER_REGNUM;
6453
6454 /* If the gp is never referenced, there's no need to initialize it.
6455 Note that reload can sometimes introduce constant pool references
6456 into a function that otherwise didn't need them. For example,
6457 suppose we have an instruction like:
6458
6459 (set (reg:DF R1) (float:DF (reg:SI R2)))
6460
6461 If R2 turns out to be constant such as 1, the instruction may have a
6462 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6463 using this constant if R2 doesn't get allocated to a register.
6464
6465 In cases like these, reload will have added the constant to the pool
6466 but no instruction will yet refer to it. */
6467 if (!df_regs_ever_live_p (GLOBAL_POINTER_REGNUM)
6468 && !current_function_uses_const_pool
6469 && !mips_function_has_gp_insn ())
6470 return 0;
6471
6472 /* We need a global pointer, but perhaps we can use a call-clobbered
6473 register instead of $gp. */
6474 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
6475 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6476 if (!df_regs_ever_live_p (regno)
6477 && call_used_regs[regno]
6478 && !fixed_regs[regno]
6479 && regno != PIC_FUNCTION_ADDR_REGNUM)
6480 return regno;
6481
6482 return GLOBAL_POINTER_REGNUM;
6483 }
6484
6485
6486 /* Return true if the function return value MODE will get returned in a
6487 floating-point register. */
6488
6489 static bool
6490 mips_return_mode_in_fpr_p (enum machine_mode mode)
6491 {
6492 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
6493 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
6494 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
6495 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
6496 }
6497
6498 /* Return a two-character string representing a function floating-point
6499 return mode, used to name MIPS16 function stubs. */
6500
6501 static const char *
6502 mips16_call_stub_mode_suffix (enum machine_mode mode)
6503 {
6504 if (mode == SFmode)
6505 return "sf";
6506 else if (mode == DFmode)
6507 return "df";
6508 else if (mode == SCmode)
6509 return "sc";
6510 else if (mode == DCmode)
6511 return "dc";
6512 else if (mode == V2SFmode)
6513 return "df";
6514 else
6515 gcc_unreachable ();
6516 }
6517
6518 /* Return true if the current function returns its value in a floating-point
6519 register in MIPS16 mode. */
6520
6521 static bool
6522 mips16_cfun_returns_in_fpr_p (void)
6523 {
6524 tree return_type = DECL_RESULT (current_function_decl);
6525 return (mips16_hard_float
6526 && !aggregate_value_p (return_type, current_function_decl)
6527 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
6528 }
6529
6530
6531 /* Return true if the current function must save REGNO. */
6532
6533 static bool
6534 mips_save_reg_p (unsigned int regno)
6535 {
6536 /* We only need to save $gp if TARGET_CALL_SAVED_GP and only then
6537 if we have not chosen a call-clobbered substitute. */
6538 if (regno == GLOBAL_POINTER_REGNUM)
6539 return TARGET_CALL_SAVED_GP && cfun->machine->global_pointer == regno;
6540
6541 /* Check call-saved registers. */
6542 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
6543 return true;
6544
6545 /* Save both registers in an FPR pair if either one is used. This is
6546 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
6547 register to be used without the even register. */
6548 if (FP_REG_P (regno)
6549 && MAX_FPRS_PER_FMT == 2
6550 && df_regs_ever_live_p (regno + 1)
6551 && !call_used_regs[regno + 1])
6552 return true;
6553
6554 /* We need to save the old frame pointer before setting up a new one. */
6555 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6556 return true;
6557
6558 /* We need to save the incoming return address if it is ever clobbered
6559 within the function. */
6560 if (regno == GP_REG_FIRST + 31 && df_regs_ever_live_p (regno))
6561 return true;
6562
6563 if (TARGET_MIPS16)
6564 {
6565 /* $18 is a special case in mips16 code. It may be used to call
6566 a function which returns a floating point value, but it is
6567 marked in call_used_regs. */
6568 if (regno == GP_REG_FIRST + 18 && df_regs_ever_live_p (regno))
6569 return true;
6570
6571 /* $31 is also a special case. It will be used to copy a return
6572 value into the floating point registers if the return value is
6573 floating point. */
6574 if (regno == GP_REG_FIRST + 31
6575 && mips16_cfun_returns_in_fpr_p ())
6576 return true;
6577 }
6578
6579 return false;
6580 }
6581
6582 /* Return the index of the lowest X in the range [0, SIZE) for which
6583 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
6584
6585 static unsigned int
6586 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
6587 unsigned int size)
6588 {
6589 unsigned int i;
6590
6591 for (i = 0; i < size; i++)
6592 if (BITSET_P (mask, regs[i]))
6593 break;
6594
6595 return i;
6596 }
6597
6598 /* *MASK_PTR is a mask of general purpose registers and *GP_REG_SIZE_PTR
6599 is the number of bytes that they occupy. If *MASK_PTR contains REGS[X]
6600 for some X in [0, SIZE), adjust *MASK_PTR and *GP_REG_SIZE_PTR so that
6601 the same is true for all indexes (X, SIZE). */
6602
6603 static void
6604 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
6605 unsigned int size, HOST_WIDE_INT *gp_reg_size_ptr)
6606 {
6607 unsigned int i;
6608
6609 i = mips16e_find_first_register (*mask_ptr, regs, size);
6610 for (i++; i < size; i++)
6611 if (!BITSET_P (*mask_ptr, regs[i]))
6612 {
6613 *gp_reg_size_ptr += GET_MODE_SIZE (gpr_mode);
6614 *mask_ptr |= 1 << regs[i];
6615 }
6616 }
6617
6618 /* Return the bytes needed to compute the frame pointer from the current
6619 stack pointer. SIZE is the size (in bytes) of the local variables.
6620
6621 MIPS stack frames look like:
6622
6623 Before call After call
6624 high +-----------------------+ +-----------------------+
6625 mem. | | | |
6626 | caller's temps. | | caller's temps. |
6627 | | | |
6628 +-----------------------+ +-----------------------+
6629 | | | |
6630 | arguments on stack. | | arguments on stack. |
6631 | | | |
6632 +-----------------------+ +-----------------------+
6633 | 4 words to save | | 4 words to save |
6634 | arguments passed | | arguments passed |
6635 | in registers, even | | in registers, even |
6636 | if not passed. | | if not passed. |
6637 SP->+-----------------------+ VFP->+-----------------------+
6638 (VFP = SP+fp_sp_offset) | |\
6639 | fp register save | | fp_reg_size
6640 | |/
6641 SP+gp_sp_offset->+-----------------------+
6642 /| |\
6643 | | gp register save | | gp_reg_size
6644 gp_reg_rounded | | |/
6645 | +-----------------------+
6646 \| alignment padding |
6647 +-----------------------+
6648 | |\
6649 | local variables | | var_size
6650 | |/
6651 +-----------------------+
6652 | |
6653 | alloca allocations |
6654 | |
6655 +-----------------------+
6656 /| |
6657 cprestore_size | | GP save for V.4 abi |
6658 \| |
6659 +-----------------------+
6660 | |\
6661 | arguments on stack | |
6662 | | |
6663 +-----------------------+ |
6664 | 4 words to save | | args_size
6665 | arguments passed | |
6666 | in registers, even | |
6667 | if not passed. | |
6668 low | (TARGET_OLDABI only) |/
6669 memory SP->+-----------------------+
6670
6671 */
6672
6673 HOST_WIDE_INT
6674 compute_frame_size (HOST_WIDE_INT size)
6675 {
6676 unsigned int regno;
6677 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6678 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6679 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6680 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6681 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6682 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6683 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6684 unsigned int mask; /* mask of saved gp registers */
6685 unsigned int fmask; /* mask of saved fp registers */
6686
6687 cfun->machine->global_pointer = mips_global_pointer ();
6688
6689 gp_reg_size = 0;
6690 fp_reg_size = 0;
6691 mask = 0;
6692 fmask = 0;
6693 var_size = MIPS_STACK_ALIGN (size);
6694 args_size = current_function_outgoing_args_size;
6695 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6696
6697 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6698 functions. If the function has local variables, we're committed
6699 to allocating it anyway. Otherwise reclaim it here. */
6700 if (var_size == 0 && current_function_is_leaf)
6701 cprestore_size = args_size = 0;
6702
6703 /* The MIPS 3.0 linker does not like functions that dynamically
6704 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6705 looks like we are trying to create a second frame pointer to the
6706 function, so allocate some stack space to make it happy. */
6707
6708 if (args_size == 0 && current_function_calls_alloca)
6709 args_size = 4 * UNITS_PER_WORD;
6710
6711 total_size = var_size + args_size + cprestore_size;
6712
6713 /* Calculate space needed for gp registers. */
6714 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6715 if (mips_save_reg_p (regno))
6716 {
6717 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6718 mask |= 1 << (regno - GP_REG_FIRST);
6719 }
6720
6721 /* We need to restore these for the handler. */
6722 if (current_function_calls_eh_return)
6723 {
6724 unsigned int i;
6725 for (i = 0; ; ++i)
6726 {
6727 regno = EH_RETURN_DATA_REGNO (i);
6728 if (regno == INVALID_REGNUM)
6729 break;
6730 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6731 mask |= 1 << (regno - GP_REG_FIRST);
6732 }
6733 }
6734
6735 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
6736 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
6737 save all later registers too. */
6738 if (GENERATE_MIPS16E_SAVE_RESTORE)
6739 {
6740 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
6741 ARRAY_SIZE (mips16e_s2_s8_regs), &gp_reg_size);
6742 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
6743 ARRAY_SIZE (mips16e_a0_a3_regs), &gp_reg_size);
6744 }
6745
6746 /* This loop must iterate over the same space as its companion in
6747 mips_for_each_saved_reg. */
6748 for (regno = (FP_REG_LAST - MAX_FPRS_PER_FMT + 1);
6749 regno >= FP_REG_FIRST;
6750 regno -= MAX_FPRS_PER_FMT)
6751 {
6752 if (mips_save_reg_p (regno))
6753 {
6754 fp_reg_size += MAX_FPRS_PER_FMT * UNITS_PER_FPREG;
6755 fmask |= ((1 << MAX_FPRS_PER_FMT) - 1) << (regno - FP_REG_FIRST);
6756 }
6757 }
6758
6759 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6760 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6761
6762 /* Add in the space required for saving incoming register arguments. */
6763 total_size += current_function_pretend_args_size;
6764 total_size += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
6765
6766 /* Save other computed information. */
6767 cfun->machine->frame.total_size = total_size;
6768 cfun->machine->frame.var_size = var_size;
6769 cfun->machine->frame.args_size = args_size;
6770 cfun->machine->frame.cprestore_size = cprestore_size;
6771 cfun->machine->frame.gp_reg_size = gp_reg_size;
6772 cfun->machine->frame.fp_reg_size = fp_reg_size;
6773 cfun->machine->frame.mask = mask;
6774 cfun->machine->frame.fmask = fmask;
6775 cfun->machine->frame.initialized = reload_completed;
6776 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6777 cfun->machine->frame.num_fp = (fp_reg_size
6778 / (MAX_FPRS_PER_FMT * UNITS_PER_FPREG));
6779
6780 if (mask)
6781 {
6782 HOST_WIDE_INT offset;
6783
6784 if (GENERATE_MIPS16E_SAVE_RESTORE)
6785 /* MIPS16e SAVE and RESTORE instructions require the GP save area
6786 to be aligned at the high end with any padding at the low end.
6787 It is only safe to use this calculation for o32, where we never
6788 have pretend arguments, and where any varargs will be saved in
6789 the caller-allocated area rather than at the top of the frame. */
6790 offset = (total_size - GET_MODE_SIZE (gpr_mode));
6791 else
6792 offset = (args_size + cprestore_size + var_size
6793 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6794 cfun->machine->frame.gp_sp_offset = offset;
6795 cfun->machine->frame.gp_save_offset = offset - total_size;
6796 }
6797 else
6798 {
6799 cfun->machine->frame.gp_sp_offset = 0;
6800 cfun->machine->frame.gp_save_offset = 0;
6801 }
6802
6803 if (fmask)
6804 {
6805 HOST_WIDE_INT offset;
6806
6807 offset = (args_size + cprestore_size + var_size
6808 + gp_reg_rounded + fp_reg_size
6809 - MAX_FPRS_PER_FMT * UNITS_PER_FPREG);
6810 cfun->machine->frame.fp_sp_offset = offset;
6811 cfun->machine->frame.fp_save_offset = offset - total_size;
6812 }
6813 else
6814 {
6815 cfun->machine->frame.fp_sp_offset = 0;
6816 cfun->machine->frame.fp_save_offset = 0;
6817 }
6818
6819 /* Ok, we're done. */
6820 return total_size;
6821 }
6822 \f
6823 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6824 pointer or argument pointer. TO is either the stack pointer or
6825 hard frame pointer. */
6826
6827 HOST_WIDE_INT
6828 mips_initial_elimination_offset (int from, int to)
6829 {
6830 HOST_WIDE_INT offset;
6831
6832 compute_frame_size (get_frame_size ());
6833
6834 /* Set OFFSET to the offset from the stack pointer. */
6835 switch (from)
6836 {
6837 case FRAME_POINTER_REGNUM:
6838 offset = 0;
6839 break;
6840
6841 case ARG_POINTER_REGNUM:
6842 offset = (cfun->machine->frame.total_size
6843 - current_function_pretend_args_size);
6844 break;
6845
6846 default:
6847 gcc_unreachable ();
6848 }
6849
6850 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6851 offset -= cfun->machine->frame.args_size;
6852
6853 return offset;
6854 }
6855 \f
6856 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6857 back to a previous frame. */
6858 rtx
6859 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6860 {
6861 if (count != 0)
6862 return const0_rtx;
6863
6864 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6865 }
6866 \f
6867 /* Use FN to save or restore register REGNO. MODE is the register's
6868 mode and OFFSET is the offset of its save slot from the current
6869 stack pointer. */
6870
6871 static void
6872 mips_save_restore_reg (enum machine_mode mode, int regno,
6873 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6874 {
6875 rtx mem;
6876
6877 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
6878
6879 fn (gen_rtx_REG (mode, regno), mem);
6880 }
6881
6882
6883 /* Call FN for each register that is saved by the current function.
6884 SP_OFFSET is the offset of the current stack pointer from the start
6885 of the frame. */
6886
6887 static void
6888 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6889 {
6890 enum machine_mode fpr_mode;
6891 HOST_WIDE_INT offset;
6892 int regno;
6893
6894 /* Save registers starting from high to low. The debuggers prefer at least
6895 the return register be stored at func+4, and also it allows us not to
6896 need a nop in the epilogue if at least one register is reloaded in
6897 addition to return address. */
6898 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6899 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6900 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6901 {
6902 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6903 offset -= GET_MODE_SIZE (gpr_mode);
6904 }
6905
6906 /* This loop must iterate over the same space as its companion in
6907 compute_frame_size. */
6908 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6909 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6910 for (regno = (FP_REG_LAST - MAX_FPRS_PER_FMT + 1);
6911 regno >= FP_REG_FIRST;
6912 regno -= MAX_FPRS_PER_FMT)
6913 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6914 {
6915 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6916 offset -= GET_MODE_SIZE (fpr_mode);
6917 }
6918 }
6919 \f
6920 /* If we're generating n32 or n64 abicalls, and the current function
6921 does not use $28 as its global pointer, emit a cplocal directive.
6922 Use pic_offset_table_rtx as the argument to the directive. */
6923
6924 static void
6925 mips_output_cplocal (void)
6926 {
6927 if (!TARGET_EXPLICIT_RELOCS
6928 && cfun->machine->global_pointer > 0
6929 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6930 output_asm_insn (".cplocal %+", 0);
6931 }
6932
6933 /* Return the style of GP load sequence that is being used for the
6934 current function. */
6935
6936 enum mips_loadgp_style
6937 mips_current_loadgp_style (void)
6938 {
6939 if (!TARGET_USE_GOT || cfun->machine->global_pointer == 0)
6940 return LOADGP_NONE;
6941
6942 if (TARGET_RTP_PIC)
6943 return LOADGP_RTP;
6944
6945 if (TARGET_ABSOLUTE_ABICALLS)
6946 return LOADGP_ABSOLUTE;
6947
6948 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
6949 }
6950
6951 /* The __gnu_local_gp symbol. */
6952
6953 static GTY(()) rtx mips_gnu_local_gp;
6954
6955 /* If we're generating n32 or n64 abicalls, emit instructions
6956 to set up the global pointer. */
6957
6958 static void
6959 mips_emit_loadgp (void)
6960 {
6961 rtx addr, offset, incoming_address, base, index;
6962
6963 switch (mips_current_loadgp_style ())
6964 {
6965 case LOADGP_ABSOLUTE:
6966 if (mips_gnu_local_gp == NULL)
6967 {
6968 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
6969 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
6970 }
6971 emit_insn (gen_loadgp_absolute (mips_gnu_local_gp));
6972 break;
6973
6974 case LOADGP_NEWABI:
6975 addr = XEXP (DECL_RTL (current_function_decl), 0);
6976 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6977 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6978 emit_insn (gen_loadgp_newabi (offset, incoming_address));
6979 if (!TARGET_EXPLICIT_RELOCS)
6980 emit_insn (gen_loadgp_blockage ());
6981 break;
6982
6983 case LOADGP_RTP:
6984 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
6985 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
6986 emit_insn (gen_loadgp_rtp (base, index));
6987 if (!TARGET_EXPLICIT_RELOCS)
6988 emit_insn (gen_loadgp_blockage ());
6989 break;
6990
6991 default:
6992 break;
6993 }
6994 }
6995
6996 /* Set up the stack and frame (if desired) for the function. */
6997
6998 static void
6999 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7000 {
7001 const char *fnname;
7002 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
7003
7004 #ifdef SDB_DEBUGGING_INFO
7005 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
7006 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
7007 #endif
7008
7009 /* In mips16 mode, we may need to generate a 32 bit to handle
7010 floating point arguments. The linker will arrange for any 32-bit
7011 functions to call this stub, which will then jump to the 16-bit
7012 function proper. */
7013 if (mips16_hard_float
7014 && current_function_args_info.fp_code != 0)
7015 build_mips16_function_stub (file);
7016
7017 if (!FUNCTION_NAME_ALREADY_DECLARED)
7018 {
7019 /* Get the function name the same way that toplev.c does before calling
7020 assemble_start_function. This is needed so that the name used here
7021 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7022 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7023
7024 if (!flag_inhibit_size_directive)
7025 {
7026 fputs ("\t.ent\t", file);
7027 assemble_name (file, fnname);
7028 fputs ("\n", file);
7029 }
7030
7031 assemble_name (file, fnname);
7032 fputs (":\n", file);
7033 }
7034
7035 /* Stop mips_file_end from treating this function as external. */
7036 if (TARGET_IRIX && mips_abi == ABI_32)
7037 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
7038
7039 if (!flag_inhibit_size_directive)
7040 {
7041 /* .frame FRAMEREG, FRAMESIZE, RETREG */
7042 fprintf (file,
7043 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
7044 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
7045 ", args= " HOST_WIDE_INT_PRINT_DEC
7046 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
7047 (reg_names[(frame_pointer_needed)
7048 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
7049 ((frame_pointer_needed && TARGET_MIPS16)
7050 ? tsize - cfun->machine->frame.args_size
7051 : tsize),
7052 reg_names[GP_REG_FIRST + 31],
7053 cfun->machine->frame.var_size,
7054 cfun->machine->frame.num_gp,
7055 cfun->machine->frame.num_fp,
7056 cfun->machine->frame.args_size,
7057 cfun->machine->frame.cprestore_size);
7058
7059 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
7060 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
7061 cfun->machine->frame.mask,
7062 cfun->machine->frame.gp_save_offset);
7063 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
7064 cfun->machine->frame.fmask,
7065 cfun->machine->frame.fp_save_offset);
7066
7067 /* Require:
7068 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
7069 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
7070 }
7071
7072 if (mips_current_loadgp_style () == LOADGP_OLDABI)
7073 {
7074 /* Handle the initialization of $gp for SVR4 PIC. */
7075 if (!cfun->machine->all_noreorder_p)
7076 output_asm_insn ("%(.cpload\t%^%)", 0);
7077 else
7078 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
7079 }
7080 else if (cfun->machine->all_noreorder_p)
7081 output_asm_insn ("%(%<", 0);
7082
7083 /* Tell the assembler which register we're using as the global
7084 pointer. This is needed for thunks, since they can use either
7085 explicit relocs or assembler macros. */
7086 mips_output_cplocal ();
7087 }
7088 \f
7089 /* Make the last instruction frame related and note that it performs
7090 the operation described by FRAME_PATTERN. */
7091
7092 static void
7093 mips_set_frame_expr (rtx frame_pattern)
7094 {
7095 rtx insn;
7096
7097 insn = get_last_insn ();
7098 RTX_FRAME_RELATED_P (insn) = 1;
7099 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7100 frame_pattern,
7101 REG_NOTES (insn));
7102 }
7103
7104
7105 /* Return a frame-related rtx that stores REG at MEM.
7106 REG must be a single register. */
7107
7108 static rtx
7109 mips_frame_set (rtx mem, rtx reg)
7110 {
7111 rtx set;
7112
7113 /* If we're saving the return address register and the dwarf return
7114 address column differs from the hard register number, adjust the
7115 note reg to refer to the former. */
7116 if (REGNO (reg) == GP_REG_FIRST + 31
7117 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
7118 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
7119
7120 set = gen_rtx_SET (VOIDmode, mem, reg);
7121 RTX_FRAME_RELATED_P (set) = 1;
7122
7123 return set;
7124 }
7125
7126
7127 /* Save register REG to MEM. Make the instruction frame-related. */
7128
7129 static void
7130 mips_save_reg (rtx reg, rtx mem)
7131 {
7132 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
7133 {
7134 rtx x1, x2;
7135
7136 if (mips_split_64bit_move_p (mem, reg))
7137 mips_split_64bit_move (mem, reg);
7138 else
7139 emit_move_insn (mem, reg);
7140
7141 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
7142 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
7143 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
7144 }
7145 else
7146 {
7147 if (TARGET_MIPS16
7148 && REGNO (reg) != GP_REG_FIRST + 31
7149 && !M16_REG_P (REGNO (reg)))
7150 {
7151 /* Save a non-mips16 register by moving it through a temporary.
7152 We don't need to do this for $31 since there's a special
7153 instruction for it. */
7154 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
7155 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
7156 }
7157 else
7158 emit_move_insn (mem, reg);
7159
7160 mips_set_frame_expr (mips_frame_set (mem, reg));
7161 }
7162 }
7163
7164 /* Return a move between register REGNO and memory location SP + OFFSET.
7165 Make the move a load if RESTORE_P, otherwise make it a frame-related
7166 store. */
7167
7168 static rtx
7169 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
7170 unsigned int regno)
7171 {
7172 rtx reg, mem;
7173
7174 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
7175 reg = gen_rtx_REG (SImode, regno);
7176 return (restore_p
7177 ? gen_rtx_SET (VOIDmode, reg, mem)
7178 : mips_frame_set (mem, reg));
7179 }
7180
7181 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
7182 The instruction must:
7183
7184 - Allocate or deallocate SIZE bytes in total; SIZE is known
7185 to be nonzero.
7186
7187 - Save or restore as many registers in *MASK_PTR as possible.
7188 The instruction saves the first registers at the top of the
7189 allocated area, with the other registers below it.
7190
7191 - Save NARGS argument registers above the allocated area.
7192
7193 (NARGS is always zero if RESTORE_P.)
7194
7195 The SAVE and RESTORE instructions cannot save and restore all general
7196 registers, so there may be some registers left over for the caller to
7197 handle. Destructively modify *MASK_PTR so that it contains the registers
7198 that still need to be saved or restored. The caller can save these
7199 registers in the memory immediately below *OFFSET_PTR, which is a
7200 byte offset from the bottom of the allocated stack area. */
7201
7202 static rtx
7203 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
7204 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
7205 HOST_WIDE_INT size)
7206 {
7207 rtx pattern, set;
7208 HOST_WIDE_INT offset, top_offset;
7209 unsigned int i, regno;
7210 int n;
7211
7212 gcc_assert (cfun->machine->frame.fp_reg_size == 0);
7213
7214 /* Calculate the number of elements in the PARALLEL. We need one element
7215 for the stack adjustment, one for each argument register save, and one
7216 for each additional register move. */
7217 n = 1 + nargs;
7218 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
7219 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
7220 n++;
7221
7222 /* Create the final PARALLEL. */
7223 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
7224 n = 0;
7225
7226 /* Add the stack pointer adjustment. */
7227 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7228 plus_constant (stack_pointer_rtx,
7229 restore_p ? size : -size));
7230 RTX_FRAME_RELATED_P (set) = 1;
7231 XVECEXP (pattern, 0, n++) = set;
7232
7233 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7234 top_offset = restore_p ? size : 0;
7235
7236 /* Save the arguments. */
7237 for (i = 0; i < nargs; i++)
7238 {
7239 offset = top_offset + i * GET_MODE_SIZE (gpr_mode);
7240 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
7241 XVECEXP (pattern, 0, n++) = set;
7242 }
7243
7244 /* Then fill in the other register moves. */
7245 offset = top_offset;
7246 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
7247 {
7248 regno = mips16e_save_restore_regs[i];
7249 if (BITSET_P (*mask_ptr, regno))
7250 {
7251 offset -= UNITS_PER_WORD;
7252 set = mips16e_save_restore_reg (restore_p, offset, regno);
7253 XVECEXP (pattern, 0, n++) = set;
7254 *mask_ptr &= ~(1 << regno);
7255 }
7256 }
7257
7258 /* Tell the caller what offset it should use for the remaining registers. */
7259 *offset_ptr = size + (offset - top_offset) + size;
7260
7261 gcc_assert (n == XVECLEN (pattern, 0));
7262
7263 return pattern;
7264 }
7265
7266 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
7267 pointer. Return true if PATTERN matches the kind of instruction
7268 generated by mips16e_build_save_restore. If INFO is nonnull,
7269 initialize it when returning true. */
7270
7271 bool
7272 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
7273 struct mips16e_save_restore_info *info)
7274 {
7275 unsigned int i, nargs, mask;
7276 HOST_WIDE_INT top_offset, save_offset, offset, extra;
7277 rtx set, reg, mem, base;
7278 int n;
7279
7280 if (!GENERATE_MIPS16E_SAVE_RESTORE)
7281 return false;
7282
7283 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7284 top_offset = adjust > 0 ? adjust : 0;
7285
7286 /* Interpret all other members of the PARALLEL. */
7287 save_offset = top_offset - GET_MODE_SIZE (gpr_mode);
7288 mask = 0;
7289 nargs = 0;
7290 i = 0;
7291 for (n = 1; n < XVECLEN (pattern, 0); n++)
7292 {
7293 /* Check that we have a SET. */
7294 set = XVECEXP (pattern, 0, n);
7295 if (GET_CODE (set) != SET)
7296 return false;
7297
7298 /* Check that the SET is a load (if restoring) or a store
7299 (if saving). */
7300 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
7301 if (!MEM_P (mem))
7302 return false;
7303
7304 /* Check that the address is the sum of the stack pointer and a
7305 possibly-zero constant offset. */
7306 mips_split_plus (XEXP (mem, 0), &base, &offset);
7307 if (base != stack_pointer_rtx)
7308 return false;
7309
7310 /* Check that SET's other operand is a register. */
7311 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
7312 if (!REG_P (reg))
7313 return false;
7314
7315 /* Check for argument saves. */
7316 if (offset == top_offset + nargs * GET_MODE_SIZE (gpr_mode)
7317 && REGNO (reg) == GP_ARG_FIRST + nargs)
7318 nargs++;
7319 else if (offset == save_offset)
7320 {
7321 while (mips16e_save_restore_regs[i++] != REGNO (reg))
7322 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
7323 return false;
7324
7325 mask |= 1 << REGNO (reg);
7326 save_offset -= GET_MODE_SIZE (gpr_mode);
7327 }
7328 else
7329 return false;
7330 }
7331
7332 /* Check that the restrictions on register ranges are met. */
7333 extra = 0;
7334 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
7335 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
7336 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
7337 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
7338 if (extra != 0)
7339 return false;
7340
7341 /* Make sure that the topmost argument register is not saved twice.
7342 The checks above ensure that the same is then true for the other
7343 argument registers. */
7344 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
7345 return false;
7346
7347 /* Pass back information, if requested. */
7348 if (info)
7349 {
7350 info->nargs = nargs;
7351 info->mask = mask;
7352 info->size = (adjust > 0 ? adjust : -adjust);
7353 }
7354
7355 return true;
7356 }
7357
7358 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
7359 for the register range [MIN_REG, MAX_REG]. Return a pointer to
7360 the null terminator. */
7361
7362 static char *
7363 mips16e_add_register_range (char *s, unsigned int min_reg,
7364 unsigned int max_reg)
7365 {
7366 if (min_reg != max_reg)
7367 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
7368 else
7369 s += sprintf (s, ",%s", reg_names[min_reg]);
7370 return s;
7371 }
7372
7373 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
7374 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
7375
7376 const char *
7377 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
7378 {
7379 static char buffer[300];
7380
7381 struct mips16e_save_restore_info info;
7382 unsigned int i, end;
7383 char *s;
7384
7385 /* Parse the pattern. */
7386 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
7387 gcc_unreachable ();
7388
7389 /* Add the mnemonic. */
7390 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
7391 s += strlen (s);
7392
7393 /* Save the arguments. */
7394 if (info.nargs > 1)
7395 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
7396 reg_names[GP_ARG_FIRST + info.nargs - 1]);
7397 else if (info.nargs == 1)
7398 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
7399
7400 /* Emit the amount of stack space to allocate or deallocate. */
7401 s += sprintf (s, "%d", (int) info.size);
7402
7403 /* Save or restore $16. */
7404 if (BITSET_P (info.mask, 16))
7405 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
7406
7407 /* Save or restore $17. */
7408 if (BITSET_P (info.mask, 17))
7409 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
7410
7411 /* Save or restore registers in the range $s2...$s8, which
7412 mips16e_s2_s8_regs lists in decreasing order. Note that this
7413 is a software register range; the hardware registers are not
7414 numbered consecutively. */
7415 end = ARRAY_SIZE (mips16e_s2_s8_regs);
7416 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
7417 if (i < end)
7418 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
7419 mips16e_s2_s8_regs[i]);
7420
7421 /* Save or restore registers in the range $a0...$a3. */
7422 end = ARRAY_SIZE (mips16e_a0_a3_regs);
7423 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
7424 if (i < end)
7425 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
7426 mips16e_a0_a3_regs[end - 1]);
7427
7428 /* Save or restore $31. */
7429 if (BITSET_P (info.mask, 31))
7430 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 31]);
7431
7432 return buffer;
7433 }
7434
7435 /* Return a simplified form of X using the register values in REG_VALUES.
7436 REG_VALUES[R] is the last value assigned to hard register R, or null
7437 if R has not been modified.
7438
7439 This function is rather limited, but is good enough for our purposes. */
7440
7441 static rtx
7442 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
7443 {
7444 rtx x0, x1;
7445
7446 x = avoid_constant_pool_reference (x);
7447
7448 if (UNARY_P (x))
7449 {
7450 x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7451 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
7452 x0, GET_MODE (XEXP (x, 0)));
7453 }
7454
7455 if (ARITHMETIC_P (x))
7456 {
7457 x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7458 x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
7459 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
7460 }
7461
7462 if (REG_P (x)
7463 && reg_values[REGNO (x)]
7464 && !rtx_unstable_p (reg_values[REGNO (x)]))
7465 return reg_values[REGNO (x)];
7466
7467 return x;
7468 }
7469
7470 /* Return true if (set DEST SRC) stores an argument register into its
7471 caller-allocated save slot, storing the number of that argument
7472 register in *REGNO_PTR if so. REG_VALUES is as for
7473 mips16e_collect_propagate_value. */
7474
7475 static bool
7476 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
7477 unsigned int *regno_ptr)
7478 {
7479 unsigned int argno, regno;
7480 HOST_WIDE_INT offset, required_offset;
7481 rtx addr, base;
7482
7483 /* Check that this is a word-mode store. */
7484 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
7485 return false;
7486
7487 /* Check that the register being saved is an unmodified argument
7488 register. */
7489 regno = REGNO (src);
7490 if (regno < GP_ARG_FIRST || regno > GP_ARG_LAST || reg_values[regno])
7491 return false;
7492 argno = regno - GP_ARG_FIRST;
7493
7494 /* Check whether the address is an appropriate stack pointer or
7495 frame pointer access. The frame pointer is offset from the
7496 stack pointer by the size of the outgoing arguments. */
7497 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
7498 mips_split_plus (addr, &base, &offset);
7499 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
7500 if (base == hard_frame_pointer_rtx)
7501 required_offset -= cfun->machine->frame.args_size;
7502 else if (base != stack_pointer_rtx)
7503 return false;
7504 if (offset != required_offset)
7505 return false;
7506
7507 *regno_ptr = regno;
7508 return true;
7509 }
7510
7511 /* A subroutine of mips_expand_prologue, called only when generating
7512 MIPS16e SAVE instructions. Search the start of the function for any
7513 instructions that save argument registers into their caller-allocated
7514 save slots. Delete such instructions and return a value N such that
7515 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
7516 instructions redundant. */
7517
7518 static unsigned int
7519 mips16e_collect_argument_saves (void)
7520 {
7521 rtx reg_values[FIRST_PSEUDO_REGISTER];
7522 rtx insn, next, set, dest, src;
7523 unsigned int nargs, regno;
7524
7525 push_topmost_sequence ();
7526 nargs = 0;
7527 memset (reg_values, 0, sizeof (reg_values));
7528 for (insn = get_insns (); insn; insn = next)
7529 {
7530 next = NEXT_INSN (insn);
7531 if (NOTE_P (insn))
7532 continue;
7533
7534 if (!INSN_P (insn))
7535 break;
7536
7537 set = PATTERN (insn);
7538 if (GET_CODE (set) != SET)
7539 break;
7540
7541 dest = SET_DEST (set);
7542 src = SET_SRC (set);
7543 if (mips16e_collect_argument_save_p (dest, src, reg_values, &regno))
7544 {
7545 if (!BITSET_P (cfun->machine->frame.mask, regno))
7546 {
7547 delete_insn (insn);
7548 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
7549 }
7550 }
7551 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
7552 reg_values[REGNO (dest)]
7553 = mips16e_collect_propagate_value (src, reg_values);
7554 else
7555 break;
7556 }
7557 pop_topmost_sequence ();
7558
7559 return nargs;
7560 }
7561
7562 /* Expand the prologue into a bunch of separate insns. */
7563
7564 void
7565 mips_expand_prologue (void)
7566 {
7567 HOST_WIDE_INT size;
7568 unsigned int nargs;
7569 rtx insn;
7570
7571 if (cfun->machine->global_pointer > 0)
7572 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
7573
7574 size = compute_frame_size (get_frame_size ());
7575
7576 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
7577 bytes beforehand; this is enough to cover the register save area
7578 without going out of range. */
7579 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
7580 {
7581 HOST_WIDE_INT step1;
7582
7583 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
7584
7585 if (GENERATE_MIPS16E_SAVE_RESTORE)
7586 {
7587 HOST_WIDE_INT offset;
7588 unsigned int mask, regno;
7589
7590 /* Try to merge argument stores into the save instruction. */
7591 nargs = mips16e_collect_argument_saves ();
7592
7593 /* Build the save instruction. */
7594 mask = cfun->machine->frame.mask;
7595 insn = mips16e_build_save_restore (false, &mask, &offset,
7596 nargs, step1);
7597 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
7598 size -= step1;
7599
7600 /* Check if we need to save other registers. */
7601 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
7602 if (BITSET_P (mask, regno - GP_REG_FIRST))
7603 {
7604 offset -= GET_MODE_SIZE (gpr_mode);
7605 mips_save_restore_reg (gpr_mode, regno, offset, mips_save_reg);
7606 }
7607 }
7608 else
7609 {
7610 insn = gen_add3_insn (stack_pointer_rtx,
7611 stack_pointer_rtx,
7612 GEN_INT (-step1));
7613 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
7614 size -= step1;
7615 mips_for_each_saved_reg (size, mips_save_reg);
7616 }
7617 }
7618
7619 /* Allocate the rest of the frame. */
7620 if (size > 0)
7621 {
7622 if (SMALL_OPERAND (-size))
7623 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
7624 stack_pointer_rtx,
7625 GEN_INT (-size)))) = 1;
7626 else
7627 {
7628 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
7629 if (TARGET_MIPS16)
7630 {
7631 /* There are no instructions to add or subtract registers
7632 from the stack pointer, so use the frame pointer as a
7633 temporary. We should always be using a frame pointer
7634 in this case anyway. */
7635 gcc_assert (frame_pointer_needed);
7636 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7637 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
7638 hard_frame_pointer_rtx,
7639 MIPS_PROLOGUE_TEMP (Pmode)));
7640 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
7641 }
7642 else
7643 emit_insn (gen_sub3_insn (stack_pointer_rtx,
7644 stack_pointer_rtx,
7645 MIPS_PROLOGUE_TEMP (Pmode)));
7646
7647 /* Describe the combined effect of the previous instructions. */
7648 mips_set_frame_expr
7649 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7650 plus_constant (stack_pointer_rtx, -size)));
7651 }
7652 }
7653
7654 /* Set up the frame pointer, if we're using one. In mips16 code,
7655 we point the frame pointer ahead of the outgoing argument area.
7656 This should allow more variables & incoming arguments to be
7657 accessed with unextended instructions. */
7658 if (frame_pointer_needed)
7659 {
7660 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
7661 {
7662 rtx offset = GEN_INT (cfun->machine->frame.args_size);
7663 if (SMALL_OPERAND (cfun->machine->frame.args_size))
7664 RTX_FRAME_RELATED_P
7665 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
7666 stack_pointer_rtx,
7667 offset))) = 1;
7668 else
7669 {
7670 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), offset);
7671 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7672 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
7673 hard_frame_pointer_rtx,
7674 MIPS_PROLOGUE_TEMP (Pmode)));
7675 mips_set_frame_expr
7676 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
7677 plus_constant (stack_pointer_rtx,
7678 cfun->machine->frame.args_size)));
7679 }
7680 }
7681 else
7682 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
7683 stack_pointer_rtx)) = 1;
7684 }
7685
7686 mips_emit_loadgp ();
7687
7688 /* If generating o32/o64 abicalls, save $gp on the stack. */
7689 if (TARGET_ABICALLS && TARGET_OLDABI && !current_function_is_leaf)
7690 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
7691
7692 /* If we are profiling, make sure no instructions are scheduled before
7693 the call to mcount. */
7694
7695 if (current_function_profile)
7696 emit_insn (gen_blockage ());
7697 }
7698 \f
7699 /* Do any necessary cleanup after a function to restore stack, frame,
7700 and regs. */
7701
7702 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
7703
7704 static void
7705 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
7706 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7707 {
7708 /* Reinstate the normal $gp. */
7709 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
7710 mips_output_cplocal ();
7711
7712 if (cfun->machine->all_noreorder_p)
7713 {
7714 /* Avoid using %>%) since it adds excess whitespace. */
7715 output_asm_insn (".set\tmacro", 0);
7716 output_asm_insn (".set\treorder", 0);
7717 set_noreorder = set_nomacro = 0;
7718 }
7719
7720 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
7721 {
7722 const char *fnname;
7723
7724 /* Get the function name the same way that toplev.c does before calling
7725 assemble_start_function. This is needed so that the name used here
7726 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7727 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7728 fputs ("\t.end\t", file);
7729 assemble_name (file, fnname);
7730 fputs ("\n", file);
7731 }
7732 }
7733 \f
7734 /* Emit instructions to restore register REG from slot MEM. */
7735
7736 static void
7737 mips_restore_reg (rtx reg, rtx mem)
7738 {
7739 /* There's no mips16 instruction to load $31 directly. Load into
7740 $7 instead and adjust the return insn appropriately. */
7741 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
7742 reg = gen_rtx_REG (GET_MODE (reg), 7);
7743
7744 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
7745 {
7746 /* Can't restore directly; move through a temporary. */
7747 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
7748 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
7749 }
7750 else
7751 emit_move_insn (reg, mem);
7752 }
7753
7754
7755 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
7756 if this epilogue precedes a sibling call, false if it is for a normal
7757 "epilogue" pattern. */
7758
7759 void
7760 mips_expand_epilogue (int sibcall_p)
7761 {
7762 HOST_WIDE_INT step1, step2;
7763 rtx base, target;
7764
7765 if (!sibcall_p && mips_can_use_return_insn ())
7766 {
7767 emit_jump_insn (gen_return ());
7768 return;
7769 }
7770
7771 /* In mips16 mode, if the return value should go into a floating-point
7772 register, we need to call a helper routine to copy it over. */
7773 if (mips16_cfun_returns_in_fpr_p ())
7774 {
7775 char *name;
7776 rtx func;
7777 rtx insn;
7778 rtx retval;
7779 rtx call;
7780 tree id;
7781 tree return_type;
7782 enum machine_mode return_mode;
7783
7784 return_type = DECL_RESULT (current_function_decl);
7785 return_mode = DECL_MODE (return_type);
7786
7787 name = ACONCAT (("__mips16_ret_",
7788 mips16_call_stub_mode_suffix (return_mode),
7789 NULL));
7790 id = get_identifier (name);
7791 func = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
7792 retval = gen_rtx_REG (return_mode, GP_RETURN);
7793 call = gen_call_value_internal (retval, func, const0_rtx);
7794 insn = emit_call_insn (call);
7795 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
7796 }
7797
7798 /* Split the frame into two. STEP1 is the amount of stack we should
7799 deallocate before restoring the registers. STEP2 is the amount we
7800 should deallocate afterwards.
7801
7802 Start off by assuming that no registers need to be restored. */
7803 step1 = cfun->machine->frame.total_size;
7804 step2 = 0;
7805
7806 /* Work out which register holds the frame address. Account for the
7807 frame pointer offset used by mips16 code. */
7808 if (!frame_pointer_needed)
7809 base = stack_pointer_rtx;
7810 else
7811 {
7812 base = hard_frame_pointer_rtx;
7813 if (TARGET_MIPS16)
7814 step1 -= cfun->machine->frame.args_size;
7815 }
7816
7817 /* If we need to restore registers, deallocate as much stack as
7818 possible in the second step without going out of range. */
7819 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
7820 {
7821 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
7822 step1 -= step2;
7823 }
7824
7825 /* Set TARGET to BASE + STEP1. */
7826 target = base;
7827 if (step1 > 0)
7828 {
7829 rtx adjust;
7830
7831 /* Get an rtx for STEP1 that we can add to BASE. */
7832 adjust = GEN_INT (step1);
7833 if (!SMALL_OPERAND (step1))
7834 {
7835 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
7836 adjust = MIPS_EPILOGUE_TEMP (Pmode);
7837 }
7838
7839 /* Normal mode code can copy the result straight into $sp. */
7840 if (!TARGET_MIPS16)
7841 target = stack_pointer_rtx;
7842
7843 emit_insn (gen_add3_insn (target, base, adjust));
7844 }
7845
7846 /* Copy TARGET into the stack pointer. */
7847 if (target != stack_pointer_rtx)
7848 emit_move_insn (stack_pointer_rtx, target);
7849
7850 /* If we're using addressing macros, $gp is implicitly used by all
7851 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
7852 from the stack. */
7853 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
7854 emit_insn (gen_blockage ());
7855
7856 if (GENERATE_MIPS16E_SAVE_RESTORE && cfun->machine->frame.mask != 0)
7857 {
7858 unsigned int regno, mask;
7859 HOST_WIDE_INT offset;
7860 rtx restore;
7861
7862 /* Generate the restore instruction. */
7863 mask = cfun->machine->frame.mask;
7864 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
7865
7866 /* Restore any other registers manually. */
7867 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
7868 if (BITSET_P (mask, regno - GP_REG_FIRST))
7869 {
7870 offset -= GET_MODE_SIZE (gpr_mode);
7871 mips_save_restore_reg (gpr_mode, regno, offset, mips_restore_reg);
7872 }
7873
7874 /* Restore the remaining registers and deallocate the final bit
7875 of the frame. */
7876 emit_insn (restore);
7877 }
7878 else
7879 {
7880 /* Restore the registers. */
7881 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
7882 mips_restore_reg);
7883
7884 /* Deallocate the final bit of the frame. */
7885 if (step2 > 0)
7886 emit_insn (gen_add3_insn (stack_pointer_rtx,
7887 stack_pointer_rtx,
7888 GEN_INT (step2)));
7889 }
7890
7891 /* Add in the __builtin_eh_return stack adjustment. We need to
7892 use a temporary in mips16 code. */
7893 if (current_function_calls_eh_return)
7894 {
7895 if (TARGET_MIPS16)
7896 {
7897 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
7898 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
7899 MIPS_EPILOGUE_TEMP (Pmode),
7900 EH_RETURN_STACKADJ_RTX));
7901 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
7902 }
7903 else
7904 emit_insn (gen_add3_insn (stack_pointer_rtx,
7905 stack_pointer_rtx,
7906 EH_RETURN_STACKADJ_RTX));
7907 }
7908
7909 if (!sibcall_p)
7910 {
7911 /* When generating MIPS16 code, the normal mips_for_each_saved_reg
7912 path will restore the return address into $7 rather than $31. */
7913 if (TARGET_MIPS16
7914 && !GENERATE_MIPS16E_SAVE_RESTORE
7915 && (cfun->machine->frame.mask & RA_MASK) != 0)
7916 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7917 GP_REG_FIRST + 7)));
7918 else
7919 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7920 GP_REG_FIRST + 31)));
7921 }
7922 }
7923 \f
7924 /* Return nonzero if this function is known to have a null epilogue.
7925 This allows the optimizer to omit jumps to jumps if no stack
7926 was created. */
7927
7928 int
7929 mips_can_use_return_insn (void)
7930 {
7931 if (! reload_completed)
7932 return 0;
7933
7934 if (df_regs_ever_live_p (31) || current_function_profile)
7935 return 0;
7936
7937 /* In mips16 mode, a function that returns a floating point value
7938 needs to arrange to copy the return value into the floating point
7939 registers. */
7940 if (mips16_cfun_returns_in_fpr_p ())
7941 return 0;
7942
7943 if (cfun->machine->frame.initialized)
7944 return cfun->machine->frame.total_size == 0;
7945
7946 return compute_frame_size (get_frame_size ()) == 0;
7947 }
7948 \f
7949 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
7950 in order to avoid duplicating too much logic from elsewhere. */
7951
7952 static void
7953 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7954 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7955 tree function)
7956 {
7957 rtx this, temp1, temp2, insn, fnaddr;
7958
7959 /* Pretend to be a post-reload pass while generating rtl. */
7960 no_new_pseudos = 1;
7961 reload_completed = 1;
7962
7963 /* Mark the end of the (empty) prologue. */
7964 emit_note (NOTE_INSN_PROLOGUE_END);
7965
7966 /* Pick a global pointer. Use a call-clobbered register if
7967 TARGET_CALL_SAVED_GP, so that we can use a sibcall. */
7968 if (TARGET_USE_GOT)
7969 {
7970 cfun->machine->global_pointer =
7971 TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
7972
7973 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
7974
7975 }
7976
7977 /* Set up the global pointer for n32 or n64 abicalls. If
7978 LOADGP_ABSOLUTE then the thunk does not use the gp and there is
7979 no need to load it.*/
7980 if (mips_current_loadgp_style () != LOADGP_ABSOLUTE
7981 || !targetm.binds_local_p (function))
7982 mips_emit_loadgp ();
7983
7984 /* We need two temporary registers in some cases. */
7985 temp1 = gen_rtx_REG (Pmode, 2);
7986 temp2 = gen_rtx_REG (Pmode, 3);
7987
7988 /* Find out which register contains the "this" pointer. */
7989 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7990 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
7991 else
7992 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
7993
7994 /* Add DELTA to THIS. */
7995 if (delta != 0)
7996 {
7997 rtx offset = GEN_INT (delta);
7998 if (!SMALL_OPERAND (delta))
7999 {
8000 emit_move_insn (temp1, offset);
8001 offset = temp1;
8002 }
8003 emit_insn (gen_add3_insn (this, this, offset));
8004 }
8005
8006 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
8007 if (vcall_offset != 0)
8008 {
8009 rtx addr;
8010
8011 /* Set TEMP1 to *THIS. */
8012 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
8013
8014 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
8015 addr = mips_add_offset (temp2, temp1, vcall_offset);
8016
8017 /* Load the offset and add it to THIS. */
8018 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
8019 emit_insn (gen_add3_insn (this, this, temp1));
8020 }
8021
8022 /* Jump to the target function. Use a sibcall if direct jumps are
8023 allowed, otherwise load the address into a register first. */
8024 fnaddr = XEXP (DECL_RTL (function), 0);
8025 if (TARGET_MIPS16 || TARGET_USE_GOT || SYMBOL_REF_LONG_CALL_P (fnaddr))
8026 {
8027 /* This is messy. gas treats "la $25,foo" as part of a call
8028 sequence and may allow a global "foo" to be lazily bound.
8029 The general move patterns therefore reject this combination.
8030
8031 In this context, lazy binding would actually be OK
8032 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
8033 TARGET_CALL_SAVED_GP; see mips_load_call_address.
8034 We must therefore load the address via a temporary
8035 register if mips_dangerous_for_la25_p.
8036
8037 If we jump to the temporary register rather than $25, the assembler
8038 can use the move insn to fill the jump's delay slot. */
8039 if (TARGET_USE_PIC_FN_ADDR_REG
8040 && !mips_dangerous_for_la25_p (fnaddr))
8041 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
8042 mips_load_call_address (temp1, fnaddr, true);
8043
8044 if (TARGET_USE_PIC_FN_ADDR_REG
8045 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
8046 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
8047 emit_jump_insn (gen_indirect_jump (temp1));
8048 }
8049 else
8050 {
8051 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
8052 SIBLING_CALL_P (insn) = 1;
8053 }
8054
8055 /* Run just enough of rest_of_compilation. This sequence was
8056 "borrowed" from alpha.c. */
8057 insn = get_insns ();
8058 insn_locators_alloc ();
8059 split_all_insns_noflow ();
8060 if (TARGET_MIPS16)
8061 mips16_lay_out_constants ();
8062 shorten_branches (insn);
8063 final_start_function (insn, file, 1);
8064 final (insn, file, 1);
8065 final_end_function ();
8066
8067 /* Clean up the vars set above. Note that final_end_function resets
8068 the global pointer for us. */
8069 reload_completed = 0;
8070 no_new_pseudos = 0;
8071 }
8072 \f
8073 /* Returns nonzero if X contains a SYMBOL_REF. */
8074
8075 static int
8076 symbolic_expression_p (rtx x)
8077 {
8078 if (GET_CODE (x) == SYMBOL_REF)
8079 return 1;
8080
8081 if (GET_CODE (x) == CONST)
8082 return symbolic_expression_p (XEXP (x, 0));
8083
8084 if (UNARY_P (x))
8085 return symbolic_expression_p (XEXP (x, 0));
8086
8087 if (ARITHMETIC_P (x))
8088 return (symbolic_expression_p (XEXP (x, 0))
8089 || symbolic_expression_p (XEXP (x, 1)));
8090
8091 return 0;
8092 }
8093
8094 /* Choose the section to use for the constant rtx expression X that has
8095 mode MODE. */
8096
8097 static section *
8098 mips_select_rtx_section (enum machine_mode mode, rtx x,
8099 unsigned HOST_WIDE_INT align)
8100 {
8101 if (TARGET_MIPS16)
8102 {
8103 /* In mips16 mode, the constant table always goes in the same section
8104 as the function, so that constants can be loaded using PC relative
8105 addressing. */
8106 return function_section (current_function_decl);
8107 }
8108 else if (TARGET_EMBEDDED_DATA)
8109 {
8110 /* For embedded applications, always put constants in read-only data,
8111 in order to reduce RAM usage. */
8112 return mergeable_constant_section (mode, align, 0);
8113 }
8114 else
8115 {
8116 /* For hosted applications, always put constants in small data if
8117 possible, as this gives the best performance. */
8118 /* ??? Consider using mergeable small data sections. */
8119
8120 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
8121 && mips_section_threshold > 0)
8122 return get_named_section (NULL, ".sdata", 0);
8123 else if (flag_pic && symbolic_expression_p (x))
8124 return get_named_section (NULL, ".data.rel.ro", 3);
8125 else
8126 return mergeable_constant_section (mode, align, 0);
8127 }
8128 }
8129
8130 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8131
8132 The complication here is that, with the combination TARGET_ABICALLS
8133 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
8134 therefore not be included in the read-only part of a DSO. Handle such
8135 cases by selecting a normal data section instead of a read-only one.
8136 The logic apes that in default_function_rodata_section. */
8137
8138 static section *
8139 mips_function_rodata_section (tree decl)
8140 {
8141 if (!TARGET_ABICALLS || TARGET_GPWORD)
8142 return default_function_rodata_section (decl);
8143
8144 if (decl && DECL_SECTION_NAME (decl))
8145 {
8146 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8147 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
8148 {
8149 char *rname = ASTRDUP (name);
8150 rname[14] = 'd';
8151 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
8152 }
8153 else if (flag_function_sections && flag_data_sections
8154 && strncmp (name, ".text.", 6) == 0)
8155 {
8156 char *rname = ASTRDUP (name);
8157 memcpy (rname + 1, "data", 4);
8158 return get_section (rname, SECTION_WRITE, decl);
8159 }
8160 }
8161 return data_section;
8162 }
8163
8164 /* Implement TARGET_IN_SMALL_DATA_P. This function controls whether
8165 locally-defined objects go in a small data section. It also controls
8166 the setting of the SYMBOL_REF_SMALL_P flag, which in turn helps
8167 mips_classify_symbol decide when to use %gp_rel(...)($gp) accesses. */
8168
8169 static bool
8170 mips_in_small_data_p (tree decl)
8171 {
8172 HOST_WIDE_INT size;
8173
8174 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
8175 return false;
8176
8177 /* We don't yet generate small-data references for -mabicalls or
8178 VxWorks RTP code. See the related -G handling in override_options. */
8179 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
8180 return false;
8181
8182 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
8183 {
8184 const char *name;
8185
8186 /* Reject anything that isn't in a known small-data section. */
8187 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8188 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
8189 return false;
8190
8191 /* If a symbol is defined externally, the assembler will use the
8192 usual -G rules when deciding how to implement macros. */
8193 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
8194 return true;
8195 }
8196 else if (TARGET_EMBEDDED_DATA)
8197 {
8198 /* Don't put constants into the small data section: we want them
8199 to be in ROM rather than RAM. */
8200 if (TREE_CODE (decl) != VAR_DECL)
8201 return false;
8202
8203 if (TREE_READONLY (decl)
8204 && !TREE_SIDE_EFFECTS (decl)
8205 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
8206 return false;
8207 }
8208
8209 size = int_size_in_bytes (TREE_TYPE (decl));
8210 return (size > 0 && size <= mips_section_threshold);
8211 }
8212
8213 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8214 anchors for small data: the GP register acts as an anchor in that
8215 case. We also don't want to use them for PC-relative accesses,
8216 where the PC acts as an anchor. */
8217
8218 static bool
8219 mips_use_anchors_for_symbol_p (rtx symbol)
8220 {
8221 switch (mips_classify_symbol (symbol))
8222 {
8223 case SYMBOL_CONSTANT_POOL:
8224 case SYMBOL_SMALL_DATA:
8225 return false;
8226
8227 default:
8228 return true;
8229 }
8230 }
8231 \f
8232 /* See whether VALTYPE is a record whose fields should be returned in
8233 floating-point registers. If so, return the number of fields and
8234 list them in FIELDS (which should have two elements). Return 0
8235 otherwise.
8236
8237 For n32 & n64, a structure with one or two fields is returned in
8238 floating-point registers as long as every field has a floating-point
8239 type. */
8240
8241 static int
8242 mips_fpr_return_fields (tree valtype, tree *fields)
8243 {
8244 tree field;
8245 int i;
8246
8247 if (!TARGET_NEWABI)
8248 return 0;
8249
8250 if (TREE_CODE (valtype) != RECORD_TYPE)
8251 return 0;
8252
8253 i = 0;
8254 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
8255 {
8256 if (TREE_CODE (field) != FIELD_DECL)
8257 continue;
8258
8259 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
8260 return 0;
8261
8262 if (i == 2)
8263 return 0;
8264
8265 fields[i++] = field;
8266 }
8267 return i;
8268 }
8269
8270
8271 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
8272 a value in the most significant part of $2/$3 if:
8273
8274 - the target is big-endian;
8275
8276 - the value has a structure or union type (we generalize this to
8277 cover aggregates from other languages too); and
8278
8279 - the structure is not returned in floating-point registers. */
8280
8281 static bool
8282 mips_return_in_msb (tree valtype)
8283 {
8284 tree fields[2];
8285
8286 return (TARGET_NEWABI
8287 && TARGET_BIG_ENDIAN
8288 && AGGREGATE_TYPE_P (valtype)
8289 && mips_fpr_return_fields (valtype, fields) == 0);
8290 }
8291
8292
8293 /* Return a composite value in a pair of floating-point registers.
8294 MODE1 and OFFSET1 are the mode and byte offset for the first value,
8295 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
8296 complete value.
8297
8298 For n32 & n64, $f0 always holds the first value and $f2 the second.
8299 Otherwise the values are packed together as closely as possible. */
8300
8301 static rtx
8302 mips_return_fpr_pair (enum machine_mode mode,
8303 enum machine_mode mode1, HOST_WIDE_INT offset1,
8304 enum machine_mode mode2, HOST_WIDE_INT offset2)
8305 {
8306 int inc;
8307
8308 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
8309 return gen_rtx_PARALLEL
8310 (mode,
8311 gen_rtvec (2,
8312 gen_rtx_EXPR_LIST (VOIDmode,
8313 gen_rtx_REG (mode1, FP_RETURN),
8314 GEN_INT (offset1)),
8315 gen_rtx_EXPR_LIST (VOIDmode,
8316 gen_rtx_REG (mode2, FP_RETURN + inc),
8317 GEN_INT (offset2))));
8318
8319 }
8320
8321
8322 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
8323 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
8324 VALTYPE is null and MODE is the mode of the return value. */
8325
8326 rtx
8327 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
8328 enum machine_mode mode)
8329 {
8330 if (valtype)
8331 {
8332 tree fields[2];
8333 int unsignedp;
8334
8335 mode = TYPE_MODE (valtype);
8336 unsignedp = TYPE_UNSIGNED (valtype);
8337
8338 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
8339 true, we must promote the mode just as PROMOTE_MODE does. */
8340 mode = promote_mode (valtype, mode, &unsignedp, 1);
8341
8342 /* Handle structures whose fields are returned in $f0/$f2. */
8343 switch (mips_fpr_return_fields (valtype, fields))
8344 {
8345 case 1:
8346 return gen_rtx_REG (mode, FP_RETURN);
8347
8348 case 2:
8349 return mips_return_fpr_pair (mode,
8350 TYPE_MODE (TREE_TYPE (fields[0])),
8351 int_byte_position (fields[0]),
8352 TYPE_MODE (TREE_TYPE (fields[1])),
8353 int_byte_position (fields[1]));
8354 }
8355
8356 /* If a value is passed in the most significant part of a register, see
8357 whether we have to round the mode up to a whole number of words. */
8358 if (mips_return_in_msb (valtype))
8359 {
8360 HOST_WIDE_INT size = int_size_in_bytes (valtype);
8361 if (size % UNITS_PER_WORD != 0)
8362 {
8363 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
8364 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
8365 }
8366 }
8367
8368 /* For EABI, the class of return register depends entirely on MODE.
8369 For example, "struct { some_type x; }" and "union { some_type x; }"
8370 are returned in the same way as a bare "some_type" would be.
8371 Other ABIs only use FPRs for scalar, complex or vector types. */
8372 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
8373 return gen_rtx_REG (mode, GP_RETURN);
8374 }
8375
8376 if (!TARGET_MIPS16)
8377 {
8378 /* Handle long doubles for n32 & n64. */
8379 if (mode == TFmode)
8380 return mips_return_fpr_pair (mode,
8381 DImode, 0,
8382 DImode, GET_MODE_SIZE (mode) / 2);
8383
8384 if (mips_return_mode_in_fpr_p (mode))
8385 {
8386 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
8387 return mips_return_fpr_pair (mode,
8388 GET_MODE_INNER (mode), 0,
8389 GET_MODE_INNER (mode),
8390 GET_MODE_SIZE (mode) / 2);
8391 else
8392 return gen_rtx_REG (mode, FP_RETURN);
8393 }
8394 }
8395
8396 return gen_rtx_REG (mode, GP_RETURN);
8397 }
8398
8399 /* Return nonzero when an argument must be passed by reference. */
8400
8401 static bool
8402 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
8403 enum machine_mode mode, tree type,
8404 bool named ATTRIBUTE_UNUSED)
8405 {
8406 if (mips_abi == ABI_EABI)
8407 {
8408 int size;
8409
8410 /* ??? How should SCmode be handled? */
8411 if (mode == DImode || mode == DFmode)
8412 return 0;
8413
8414 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
8415 return size == -1 || size > UNITS_PER_WORD;
8416 }
8417 else
8418 {
8419 /* If we have a variable-sized parameter, we have no choice. */
8420 return targetm.calls.must_pass_in_stack (mode, type);
8421 }
8422 }
8423
8424 static bool
8425 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
8426 enum machine_mode mode ATTRIBUTE_UNUSED,
8427 tree type ATTRIBUTE_UNUSED, bool named)
8428 {
8429 return mips_abi == ABI_EABI && named;
8430 }
8431
8432 /* Return true if registers of class CLASS cannot change from mode FROM
8433 to mode TO. */
8434
8435 bool
8436 mips_cannot_change_mode_class (enum machine_mode from,
8437 enum machine_mode to, enum reg_class class)
8438 {
8439 if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
8440 && MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
8441 {
8442 if (TARGET_BIG_ENDIAN)
8443 {
8444 /* When a multi-word value is stored in paired floating-point
8445 registers, the first register always holds the low word.
8446 We therefore can't allow FPRs to change between single-word
8447 and multi-word modes. */
8448 if (MAX_FPRS_PER_FMT > 1 && reg_classes_intersect_p (FP_REGS, class))
8449 return true;
8450 }
8451 else
8452 {
8453 /* LO_REGNO == HI_REGNO + 1, so if a multi-word value is stored
8454 in LO and HI, the high word always comes first. We therefore
8455 can't allow values stored in HI to change between single-word
8456 and multi-word modes.
8457 This rule applies to both the original HI/LO pair and the new
8458 DSP accumulators. */
8459 if (reg_classes_intersect_p (ACC_REGS, class))
8460 return true;
8461 }
8462 }
8463
8464 /* gcc assumes that each word of a multiword register can be accessed
8465 individually using SUBREGs. This is not true for floating-point
8466 registers if they are bigger than a word. */
8467 if (UNITS_PER_FPREG > UNITS_PER_WORD
8468 && GET_MODE_SIZE (from) > UNITS_PER_WORD
8469 && GET_MODE_SIZE (to) < UNITS_PER_FPREG
8470 && reg_classes_intersect_p (FP_REGS, class))
8471 return true;
8472
8473 /* Loading a 32-bit value into a 64-bit floating-point register
8474 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
8475 We can't allow 64-bit float registers to change from SImode to
8476 to a wider mode. */
8477 if (TARGET_64BIT
8478 && TARGET_FLOAT64
8479 && from == SImode
8480 && GET_MODE_SIZE (to) >= UNITS_PER_WORD
8481 && reg_classes_intersect_p (FP_REGS, class))
8482 return true;
8483
8484 return false;
8485 }
8486
8487 /* Return true if X should not be moved directly into register $25.
8488 We need this because many versions of GAS will treat "la $25,foo" as
8489 part of a call sequence and so allow a global "foo" to be lazily bound. */
8490
8491 bool
8492 mips_dangerous_for_la25_p (rtx x)
8493 {
8494 return (!TARGET_EXPLICIT_RELOCS
8495 && TARGET_USE_GOT
8496 && GET_CODE (x) == SYMBOL_REF
8497 && mips_global_symbol_p (x));
8498 }
8499
8500 /* Implement PREFERRED_RELOAD_CLASS. */
8501
8502 enum reg_class
8503 mips_preferred_reload_class (rtx x, enum reg_class class)
8504 {
8505 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
8506 return LEA_REGS;
8507
8508 if (TARGET_HARD_FLOAT
8509 && FLOAT_MODE_P (GET_MODE (x))
8510 && reg_class_subset_p (FP_REGS, class))
8511 return FP_REGS;
8512
8513 if (reg_class_subset_p (GR_REGS, class))
8514 class = GR_REGS;
8515
8516 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
8517 class = M16_REGS;
8518
8519 return class;
8520 }
8521
8522 /* This function returns the register class required for a secondary
8523 register when copying between one of the registers in CLASS, and X,
8524 using MODE. If IN_P is nonzero, the copy is going from X to the
8525 register, otherwise the register is the source. A return value of
8526 NO_REGS means that no secondary register is required. */
8527
8528 enum reg_class
8529 mips_secondary_reload_class (enum reg_class class,
8530 enum machine_mode mode, rtx x, int in_p)
8531 {
8532 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
8533 int regno = -1;
8534 int gp_reg_p;
8535
8536 if (REG_P (x)|| GET_CODE (x) == SUBREG)
8537 regno = true_regnum (x);
8538
8539 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
8540
8541 if (mips_dangerous_for_la25_p (x))
8542 {
8543 gr_regs = LEA_REGS;
8544 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
8545 return gr_regs;
8546 }
8547
8548 /* Copying from HI or LO to anywhere other than a general register
8549 requires a general register.
8550 This rule applies to both the original HI/LO pair and the new
8551 DSP accumulators. */
8552 if (reg_class_subset_p (class, ACC_REGS))
8553 {
8554 if (TARGET_MIPS16 && in_p)
8555 {
8556 /* We can't really copy to HI or LO at all in mips16 mode. */
8557 return M16_REGS;
8558 }
8559 return gp_reg_p ? NO_REGS : gr_regs;
8560 }
8561 if (ACC_REG_P (regno))
8562 {
8563 if (TARGET_MIPS16 && ! in_p)
8564 {
8565 /* We can't really copy to HI or LO at all in mips16 mode. */
8566 return M16_REGS;
8567 }
8568 return class == gr_regs ? NO_REGS : gr_regs;
8569 }
8570
8571 /* We can only copy a value to a condition code register from a
8572 floating point register, and even then we require a scratch
8573 floating point register. We can only copy a value out of a
8574 condition code register into a general register. */
8575 if (class == ST_REGS)
8576 {
8577 if (in_p)
8578 return FP_REGS;
8579 return gp_reg_p ? NO_REGS : gr_regs;
8580 }
8581 if (ST_REG_P (regno))
8582 {
8583 if (! in_p)
8584 return FP_REGS;
8585 return class == gr_regs ? NO_REGS : gr_regs;
8586 }
8587
8588 if (class == FP_REGS)
8589 {
8590 if (MEM_P (x))
8591 {
8592 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
8593 return NO_REGS;
8594 }
8595 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
8596 {
8597 /* We can use the l.s and l.d macros to load floating-point
8598 constants. ??? For l.s, we could probably get better
8599 code by returning GR_REGS here. */
8600 return NO_REGS;
8601 }
8602 else if (gp_reg_p || x == CONST0_RTX (mode))
8603 {
8604 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
8605 return NO_REGS;
8606 }
8607 else if (FP_REG_P (regno))
8608 {
8609 /* In this case we can use mov.s or mov.d. */
8610 return NO_REGS;
8611 }
8612 else
8613 {
8614 /* Otherwise, we need to reload through an integer register. */
8615 return gr_regs;
8616 }
8617 }
8618
8619 /* In mips16 mode, going between memory and anything but M16_REGS
8620 requires an M16_REG. */
8621 if (TARGET_MIPS16)
8622 {
8623 if (class != M16_REGS && class != M16_NA_REGS)
8624 {
8625 if (gp_reg_p)
8626 return NO_REGS;
8627 return M16_REGS;
8628 }
8629 if (! gp_reg_p)
8630 {
8631 if (class == M16_REGS || class == M16_NA_REGS)
8632 return NO_REGS;
8633 return M16_REGS;
8634 }
8635 }
8636
8637 return NO_REGS;
8638 }
8639
8640 /* Implement CLASS_MAX_NREGS.
8641
8642 - UNITS_PER_FPREG controls the number of registers needed by FP_REGS.
8643
8644 - ST_REGS are always hold CCmode values, and CCmode values are
8645 considered to be 4 bytes wide.
8646
8647 All other register classes are covered by UNITS_PER_WORD. Note that
8648 this is true even for unions of integer and float registers when the
8649 latter are smaller than the former. The only supported combination
8650 in which case this occurs is -mgp64 -msingle-float, which has 64-bit
8651 words but 32-bit float registers. A word-based calculation is correct
8652 in that case since -msingle-float disallows multi-FPR values. */
8653
8654 int
8655 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
8656 enum machine_mode mode)
8657 {
8658 if (class == ST_REGS)
8659 return (GET_MODE_SIZE (mode) + 3) / 4;
8660 else if (class == FP_REGS)
8661 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
8662 else
8663 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8664 }
8665
8666 static bool
8667 mips_valid_pointer_mode (enum machine_mode mode)
8668 {
8669 return (mode == SImode || (TARGET_64BIT && mode == DImode));
8670 }
8671
8672 /* Target hook for vector_mode_supported_p. */
8673
8674 static bool
8675 mips_vector_mode_supported_p (enum machine_mode mode)
8676 {
8677 switch (mode)
8678 {
8679 case V2SFmode:
8680 return TARGET_PAIRED_SINGLE_FLOAT;
8681
8682 case V2HImode:
8683 case V4QImode:
8684 return TARGET_DSP;
8685
8686 default:
8687 return false;
8688 }
8689 }
8690 \f
8691 /* If we can access small data directly (using gp-relative relocation
8692 operators) return the small data pointer, otherwise return null.
8693
8694 For each mips16 function which refers to GP relative symbols, we
8695 use a pseudo register, initialized at the start of the function, to
8696 hold the $gp value. */
8697
8698 static rtx
8699 mips16_gp_pseudo_reg (void)
8700 {
8701 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
8702 {
8703 rtx insn, scan;
8704
8705 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
8706
8707 /* We want to initialize this to a value which gcc will believe
8708 is constant. */
8709 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
8710
8711 push_topmost_sequence ();
8712 /* We need to emit the initialization after the FUNCTION_BEG
8713 note, so that it will be integrated. */
8714 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
8715 if (NOTE_P (scan)
8716 && NOTE_KIND (scan) == NOTE_INSN_FUNCTION_BEG)
8717 break;
8718 if (scan == NULL_RTX)
8719 scan = get_insns ();
8720 insn = emit_insn_after (insn, scan);
8721 pop_topmost_sequence ();
8722 }
8723
8724 return cfun->machine->mips16_gp_pseudo_rtx;
8725 }
8726
8727 /* Write out code to move floating point arguments in or out of
8728 general registers. Output the instructions to FILE. FP_CODE is
8729 the code describing which arguments are present (see the comment at
8730 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
8731 we are copying from the floating point registers. */
8732
8733 static void
8734 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
8735 {
8736 const char *s;
8737 int gparg, fparg;
8738 unsigned int f;
8739 CUMULATIVE_ARGS cum;
8740
8741 /* This code only works for the original 32-bit ABI and the O64 ABI. */
8742 gcc_assert (TARGET_OLDABI);
8743
8744 if (from_fp_p)
8745 s = "mfc1";
8746 else
8747 s = "mtc1";
8748
8749 init_cumulative_args (&cum, NULL, NULL);
8750
8751 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8752 {
8753 enum machine_mode mode;
8754 struct mips_arg_info info;
8755
8756 if ((f & 3) == 1)
8757 mode = SFmode;
8758 else if ((f & 3) == 2)
8759 mode = DFmode;
8760 else
8761 gcc_unreachable ();
8762
8763 mips_arg_info (&cum, mode, NULL, true, &info);
8764 gparg = mips_arg_regno (&info, false);
8765 fparg = mips_arg_regno (&info, true);
8766
8767 if (mode == SFmode)
8768 fprintf (file, "\t%s\t%s,%s\n", s,
8769 reg_names[gparg], reg_names[fparg]);
8770 else if (TARGET_64BIT)
8771 fprintf (file, "\td%s\t%s,%s\n", s,
8772 reg_names[gparg], reg_names[fparg]);
8773 else if (ISA_HAS_MXHC1)
8774 /* -mips32r2 -mfp64 */
8775 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n",
8776 s,
8777 reg_names[gparg + (WORDS_BIG_ENDIAN ? 1 : 0)],
8778 reg_names[fparg],
8779 from_fp_p ? "mfhc1" : "mthc1",
8780 reg_names[gparg + (WORDS_BIG_ENDIAN ? 0 : 1)],
8781 reg_names[fparg]);
8782 else if (TARGET_BIG_ENDIAN)
8783 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8784 reg_names[gparg], reg_names[fparg + 1], s,
8785 reg_names[gparg + 1], reg_names[fparg]);
8786 else
8787 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8788 reg_names[gparg], reg_names[fparg], s,
8789 reg_names[gparg + 1], reg_names[fparg + 1]);
8790
8791 function_arg_advance (&cum, mode, NULL, true);
8792 }
8793 }
8794
8795 /* Build a mips16 function stub. This is used for functions which
8796 take arguments in the floating point registers. It is 32-bit code
8797 that moves the floating point args into the general registers, and
8798 then jumps to the 16-bit code. */
8799
8800 static void
8801 build_mips16_function_stub (FILE *file)
8802 {
8803 const char *fnname;
8804 char *secname, *stubname;
8805 tree stubid, stubdecl;
8806 int need_comma;
8807 unsigned int f;
8808
8809 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8810 secname = (char *) alloca (strlen (fnname) + 20);
8811 sprintf (secname, ".mips16.fn.%s", fnname);
8812 stubname = (char *) alloca (strlen (fnname) + 20);
8813 sprintf (stubname, "__fn_stub_%s", fnname);
8814 stubid = get_identifier (stubname);
8815 stubdecl = build_decl (FUNCTION_DECL, stubid,
8816 build_function_type (void_type_node, NULL_TREE));
8817 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8818 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
8819
8820 fprintf (file, "\t# Stub function for %s (", current_function_name ());
8821 need_comma = 0;
8822 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
8823 {
8824 fprintf (file, "%s%s",
8825 need_comma ? ", " : "",
8826 (f & 3) == 1 ? "float" : "double");
8827 need_comma = 1;
8828 }
8829 fprintf (file, ")\n");
8830
8831 fprintf (file, "\t.set\tnomips16\n");
8832 switch_to_section (function_section (stubdecl));
8833 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
8834
8835 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
8836 within a .ent, and we cannot emit another .ent. */
8837 if (!FUNCTION_NAME_ALREADY_DECLARED)
8838 {
8839 fputs ("\t.ent\t", file);
8840 assemble_name (file, stubname);
8841 fputs ("\n", file);
8842 }
8843
8844 assemble_name (file, stubname);
8845 fputs (":\n", file);
8846
8847 /* We don't want the assembler to insert any nops here. */
8848 fprintf (file, "\t.set\tnoreorder\n");
8849
8850 mips16_fp_args (file, current_function_args_info.fp_code, 1);
8851
8852 fprintf (asm_out_file, "\t.set\tnoat\n");
8853 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
8854 assemble_name (file, fnname);
8855 fprintf (file, "\n");
8856 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8857 fprintf (asm_out_file, "\t.set\tat\n");
8858
8859 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8860 with one of the mfc1 instructions, because the result is not
8861 available for one instruction, so if the very first instruction
8862 in the function refers to the register, it will see the wrong
8863 value. */
8864 fprintf (file, "\tnop\n");
8865
8866 fprintf (file, "\t.set\treorder\n");
8867
8868 if (!FUNCTION_NAME_ALREADY_DECLARED)
8869 {
8870 fputs ("\t.end\t", file);
8871 assemble_name (file, stubname);
8872 fputs ("\n", file);
8873 }
8874
8875 fprintf (file, "\t.set\tmips16\n");
8876
8877 switch_to_section (function_section (current_function_decl));
8878 }
8879
8880 /* We keep a list of functions for which we have already built stubs
8881 in build_mips16_call_stub. */
8882
8883 struct mips16_stub
8884 {
8885 struct mips16_stub *next;
8886 char *name;
8887 int fpret;
8888 };
8889
8890 static struct mips16_stub *mips16_stubs;
8891
8892 /* Emit code to return a double value from a mips16 stub. GPREG is the
8893 first GP reg to use, FPREG is the first FP reg to use. */
8894
8895 static void
8896 mips16_fpret_double (int gpreg, int fpreg)
8897 {
8898 if (TARGET_64BIT)
8899 fprintf (asm_out_file, "\tdmfc1\t%s,%s\n",
8900 reg_names[gpreg], reg_names[fpreg]);
8901 else if (TARGET_FLOAT64)
8902 {
8903 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8904 reg_names[gpreg + WORDS_BIG_ENDIAN],
8905 reg_names[fpreg]);
8906 fprintf (asm_out_file, "\tmfhc1\t%s,%s\n",
8907 reg_names[gpreg + !WORDS_BIG_ENDIAN],
8908 reg_names[fpreg]);
8909 }
8910 else
8911 {
8912 if (TARGET_BIG_ENDIAN)
8913 {
8914 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8915 reg_names[gpreg + 0],
8916 reg_names[fpreg + 1]);
8917 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8918 reg_names[gpreg + 1],
8919 reg_names[fpreg + 0]);
8920 }
8921 else
8922 {
8923 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8924 reg_names[gpreg + 0],
8925 reg_names[fpreg + 0]);
8926 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8927 reg_names[gpreg + 1],
8928 reg_names[fpreg + 1]);
8929 }
8930 }
8931 }
8932
8933 /* Build a call stub for a mips16 call. A stub is needed if we are
8934 passing any floating point values which should go into the floating
8935 point registers. If we are, and the call turns out to be to a
8936 32-bit function, the stub will be used to move the values into the
8937 floating point registers before calling the 32-bit function. The
8938 linker will magically adjust the function call to either the 16-bit
8939 function or the 32-bit stub, depending upon where the function call
8940 is actually defined.
8941
8942 Similarly, we need a stub if the return value might come back in a
8943 floating point register.
8944
8945 RETVAL is the location of the return value, or null if this is
8946 a call rather than a call_value. FN is the address of the
8947 function and ARG_SIZE is the size of the arguments. FP_CODE
8948 is the code built by function_arg. This function returns a nonzero
8949 value if it builds the call instruction itself. */
8950
8951 int
8952 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
8953 {
8954 int fpret = 0;
8955 const char *fnname;
8956 char *secname, *stubname;
8957 struct mips16_stub *l;
8958 tree stubid, stubdecl;
8959 int need_comma;
8960 unsigned int f;
8961
8962 /* We don't need to do anything if we aren't in mips16 mode, or if
8963 we were invoked with the -msoft-float option. */
8964 if (!mips16_hard_float)
8965 return 0;
8966
8967 /* Figure out whether the value might come back in a floating point
8968 register. */
8969 if (retval)
8970 fpret = mips_return_mode_in_fpr_p (GET_MODE (retval));
8971
8972 /* We don't need to do anything if there were no floating point
8973 arguments and the value will not be returned in a floating point
8974 register. */
8975 if (fp_code == 0 && ! fpret)
8976 return 0;
8977
8978 /* We don't need to do anything if this is a call to a special
8979 mips16 support function. */
8980 if (GET_CODE (fn) == SYMBOL_REF
8981 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8982 return 0;
8983
8984 /* This code will only work for o32 and o64 abis. The other ABI's
8985 require more sophisticated support. */
8986 gcc_assert (TARGET_OLDABI);
8987
8988 /* If we're calling via a function pointer, then we must always call
8989 via a stub. There are magic stubs provided in libgcc.a for each
8990 of the required cases. Each of them expects the function address
8991 to arrive in register $2. */
8992
8993 if (GET_CODE (fn) != SYMBOL_REF)
8994 {
8995 char buf[30];
8996 tree id;
8997 rtx stub_fn, insn;
8998
8999 /* ??? If this code is modified to support other ABI's, we need
9000 to handle PARALLEL return values here. */
9001
9002 if (fpret)
9003 sprintf (buf, "__mips16_call_stub_%s_%d",
9004 mips16_call_stub_mode_suffix (GET_MODE (retval)),
9005 fp_code);
9006 else
9007 sprintf (buf, "__mips16_call_stub_%d",
9008 fp_code);
9009
9010 id = get_identifier (buf);
9011 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
9012
9013 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
9014
9015 if (retval == NULL_RTX)
9016 insn = gen_call_internal (stub_fn, arg_size);
9017 else
9018 insn = gen_call_value_internal (retval, stub_fn, arg_size);
9019 insn = emit_call_insn (insn);
9020
9021 /* Put the register usage information on the CALL. */
9022 CALL_INSN_FUNCTION_USAGE (insn) =
9023 gen_rtx_EXPR_LIST (VOIDmode,
9024 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
9025 CALL_INSN_FUNCTION_USAGE (insn));
9026
9027 /* If we are handling a floating point return value, we need to
9028 save $18 in the function prologue. Putting a note on the
9029 call will mean that df_regs_ever_live_p ($18) will be true if the
9030 call is not eliminated, and we can check that in the prologue
9031 code. */
9032 if (fpret)
9033 CALL_INSN_FUNCTION_USAGE (insn) =
9034 gen_rtx_EXPR_LIST (VOIDmode,
9035 gen_rtx_USE (VOIDmode,
9036 gen_rtx_REG (word_mode, 18)),
9037 CALL_INSN_FUNCTION_USAGE (insn));
9038
9039 /* Return 1 to tell the caller that we've generated the call
9040 insn. */
9041 return 1;
9042 }
9043
9044 /* We know the function we are going to call. If we have already
9045 built a stub, we don't need to do anything further. */
9046
9047 fnname = XSTR (fn, 0);
9048 for (l = mips16_stubs; l != NULL; l = l->next)
9049 if (strcmp (l->name, fnname) == 0)
9050 break;
9051
9052 if (l == NULL)
9053 {
9054 /* Build a special purpose stub. When the linker sees a
9055 function call in mips16 code, it will check where the target
9056 is defined. If the target is a 32-bit call, the linker will
9057 search for the section defined here. It can tell which
9058 symbol this section is associated with by looking at the
9059 relocation information (the name is unreliable, since this
9060 might be a static function). If such a section is found, the
9061 linker will redirect the call to the start of the magic
9062 section.
9063
9064 If the function does not return a floating point value, the
9065 special stub section is named
9066 .mips16.call.FNNAME
9067
9068 If the function does return a floating point value, the stub
9069 section is named
9070 .mips16.call.fp.FNNAME
9071 */
9072
9073 secname = (char *) alloca (strlen (fnname) + 40);
9074 sprintf (secname, ".mips16.call.%s%s",
9075 fpret ? "fp." : "",
9076 fnname);
9077 stubname = (char *) alloca (strlen (fnname) + 20);
9078 sprintf (stubname, "__call_stub_%s%s",
9079 fpret ? "fp_" : "",
9080 fnname);
9081 stubid = get_identifier (stubname);
9082 stubdecl = build_decl (FUNCTION_DECL, stubid,
9083 build_function_type (void_type_node, NULL_TREE));
9084 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
9085 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
9086
9087 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
9088 (fpret
9089 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
9090 : ""),
9091 fnname);
9092 need_comma = 0;
9093 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
9094 {
9095 fprintf (asm_out_file, "%s%s",
9096 need_comma ? ", " : "",
9097 (f & 3) == 1 ? "float" : "double");
9098 need_comma = 1;
9099 }
9100 fprintf (asm_out_file, ")\n");
9101
9102 fprintf (asm_out_file, "\t.set\tnomips16\n");
9103 assemble_start_function (stubdecl, stubname);
9104
9105 if (!FUNCTION_NAME_ALREADY_DECLARED)
9106 {
9107 fputs ("\t.ent\t", asm_out_file);
9108 assemble_name (asm_out_file, stubname);
9109 fputs ("\n", asm_out_file);
9110
9111 assemble_name (asm_out_file, stubname);
9112 fputs (":\n", asm_out_file);
9113 }
9114
9115 /* We build the stub code by hand. That's the only way we can
9116 do it, since we can't generate 32-bit code during a 16-bit
9117 compilation. */
9118
9119 /* We don't want the assembler to insert any nops here. */
9120 fprintf (asm_out_file, "\t.set\tnoreorder\n");
9121
9122 mips16_fp_args (asm_out_file, fp_code, 0);
9123
9124 if (! fpret)
9125 {
9126 fprintf (asm_out_file, "\t.set\tnoat\n");
9127 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
9128 fnname);
9129 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
9130 fprintf (asm_out_file, "\t.set\tat\n");
9131 /* Unfortunately, we can't fill the jump delay slot. We
9132 can't fill with one of the mtc1 instructions, because the
9133 result is not available for one instruction, so if the
9134 very first instruction in the function refers to the
9135 register, it will see the wrong value. */
9136 fprintf (asm_out_file, "\tnop\n");
9137 }
9138 else
9139 {
9140 fprintf (asm_out_file, "\tmove\t%s,%s\n",
9141 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
9142 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
9143 /* As above, we can't fill the delay slot. */
9144 fprintf (asm_out_file, "\tnop\n");
9145 if (GET_MODE (retval) == SFmode)
9146 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9147 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
9148 else if (GET_MODE (retval) == SCmode)
9149 {
9150 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9151 reg_names[GP_REG_FIRST + 2],
9152 reg_names[FP_REG_FIRST + 0]);
9153 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9154 reg_names[GP_REG_FIRST + 3],
9155 reg_names[FP_REG_FIRST + MAX_FPRS_PER_FMT]);
9156 }
9157 else if (GET_MODE (retval) == DFmode
9158 || GET_MODE (retval) == V2SFmode)
9159 {
9160 mips16_fpret_double (GP_REG_FIRST + 2, FP_REG_FIRST + 0);
9161 }
9162 else if (GET_MODE (retval) == DCmode)
9163 {
9164 mips16_fpret_double (GP_REG_FIRST + 2,
9165 FP_REG_FIRST + 0);
9166 mips16_fpret_double (GP_REG_FIRST + 4,
9167 FP_REG_FIRST + MAX_FPRS_PER_FMT);
9168 }
9169 else
9170 {
9171 if (TARGET_BIG_ENDIAN)
9172 {
9173 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9174 reg_names[GP_REG_FIRST + 2],
9175 reg_names[FP_REG_FIRST + 1]);
9176 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9177 reg_names[GP_REG_FIRST + 3],
9178 reg_names[FP_REG_FIRST + 0]);
9179 }
9180 else
9181 {
9182 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9183 reg_names[GP_REG_FIRST + 2],
9184 reg_names[FP_REG_FIRST + 0]);
9185 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9186 reg_names[GP_REG_FIRST + 3],
9187 reg_names[FP_REG_FIRST + 1]);
9188 }
9189 }
9190 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
9191 /* As above, we can't fill the delay slot. */
9192 fprintf (asm_out_file, "\tnop\n");
9193 }
9194
9195 fprintf (asm_out_file, "\t.set\treorder\n");
9196
9197 #ifdef ASM_DECLARE_FUNCTION_SIZE
9198 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
9199 #endif
9200
9201 if (!FUNCTION_NAME_ALREADY_DECLARED)
9202 {
9203 fputs ("\t.end\t", asm_out_file);
9204 assemble_name (asm_out_file, stubname);
9205 fputs ("\n", asm_out_file);
9206 }
9207
9208 fprintf (asm_out_file, "\t.set\tmips16\n");
9209
9210 /* Record this stub. */
9211 l = (struct mips16_stub *) xmalloc (sizeof *l);
9212 l->name = xstrdup (fnname);
9213 l->fpret = fpret;
9214 l->next = mips16_stubs;
9215 mips16_stubs = l;
9216 }
9217
9218 /* If we expect a floating point return value, but we've built a
9219 stub which does not expect one, then we're in trouble. We can't
9220 use the existing stub, because it won't handle the floating point
9221 value. We can't build a new stub, because the linker won't know
9222 which stub to use for the various calls in this object file.
9223 Fortunately, this case is illegal, since it means that a function
9224 was declared in two different ways in a single compilation. */
9225 if (fpret && ! l->fpret)
9226 error ("cannot handle inconsistent calls to %qs", fnname);
9227
9228 /* If we are calling a stub which handles a floating point return
9229 value, we need to arrange to save $18 in the prologue. We do
9230 this by marking the function call as using the register. The
9231 prologue will later see that it is used, and emit code to save
9232 it. */
9233
9234 if (l->fpret)
9235 {
9236 rtx insn;
9237
9238 if (retval == NULL_RTX)
9239 insn = gen_call_internal (fn, arg_size);
9240 else
9241 insn = gen_call_value_internal (retval, fn, arg_size);
9242 insn = emit_call_insn (insn);
9243
9244 CALL_INSN_FUNCTION_USAGE (insn) =
9245 gen_rtx_EXPR_LIST (VOIDmode,
9246 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
9247 CALL_INSN_FUNCTION_USAGE (insn));
9248
9249 /* Return 1 to tell the caller that we've generated the call
9250 insn. */
9251 return 1;
9252 }
9253
9254 /* Return 0 to let the caller generate the call insn. */
9255 return 0;
9256 }
9257
9258 /* An entry in the mips16 constant pool. VALUE is the pool constant,
9259 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
9260
9261 struct mips16_constant {
9262 struct mips16_constant *next;
9263 rtx value;
9264 rtx label;
9265 enum machine_mode mode;
9266 };
9267
9268 /* Information about an incomplete mips16 constant pool. FIRST is the
9269 first constant, HIGHEST_ADDRESS is the highest address that the first
9270 byte of the pool can have, and INSN_ADDRESS is the current instruction
9271 address. */
9272
9273 struct mips16_constant_pool {
9274 struct mips16_constant *first;
9275 int highest_address;
9276 int insn_address;
9277 };
9278
9279 /* Add constant VALUE to POOL and return its label. MODE is the
9280 value's mode (used for CONST_INTs, etc.). */
9281
9282 static rtx
9283 add_constant (struct mips16_constant_pool *pool,
9284 rtx value, enum machine_mode mode)
9285 {
9286 struct mips16_constant **p, *c;
9287 bool first_of_size_p;
9288
9289 /* See whether the constant is already in the pool. If so, return the
9290 existing label, otherwise leave P pointing to the place where the
9291 constant should be added.
9292
9293 Keep the pool sorted in increasing order of mode size so that we can
9294 reduce the number of alignments needed. */
9295 first_of_size_p = true;
9296 for (p = &pool->first; *p != 0; p = &(*p)->next)
9297 {
9298 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
9299 return (*p)->label;
9300 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
9301 break;
9302 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
9303 first_of_size_p = false;
9304 }
9305
9306 /* In the worst case, the constant needed by the earliest instruction
9307 will end up at the end of the pool. The entire pool must then be
9308 accessible from that instruction.
9309
9310 When adding the first constant, set the pool's highest address to
9311 the address of the first out-of-range byte. Adjust this address
9312 downwards each time a new constant is added. */
9313 if (pool->first == 0)
9314 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
9315 is the address of the instruction with the lowest two bits clear.
9316 The base PC value for ld has the lowest three bits clear. Assume
9317 the worst case here. */
9318 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
9319 pool->highest_address -= GET_MODE_SIZE (mode);
9320 if (first_of_size_p)
9321 /* Take into account the worst possible padding due to alignment. */
9322 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
9323
9324 /* Create a new entry. */
9325 c = (struct mips16_constant *) xmalloc (sizeof *c);
9326 c->value = value;
9327 c->mode = mode;
9328 c->label = gen_label_rtx ();
9329 c->next = *p;
9330 *p = c;
9331
9332 return c->label;
9333 }
9334
9335 /* Output constant VALUE after instruction INSN and return the last
9336 instruction emitted. MODE is the mode of the constant. */
9337
9338 static rtx
9339 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
9340 {
9341 switch (GET_MODE_CLASS (mode))
9342 {
9343 case MODE_INT:
9344 {
9345 rtx size = GEN_INT (GET_MODE_SIZE (mode));
9346 return emit_insn_after (gen_consttable_int (value, size), insn);
9347 }
9348
9349 case MODE_FLOAT:
9350 return emit_insn_after (gen_consttable_float (value), insn);
9351
9352 case MODE_VECTOR_FLOAT:
9353 case MODE_VECTOR_INT:
9354 {
9355 int i;
9356 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
9357 insn = dump_constants_1 (GET_MODE_INNER (mode),
9358 CONST_VECTOR_ELT (value, i), insn);
9359 return insn;
9360 }
9361
9362 default:
9363 gcc_unreachable ();
9364 }
9365 }
9366
9367
9368 /* Dump out the constants in CONSTANTS after INSN. */
9369
9370 static void
9371 dump_constants (struct mips16_constant *constants, rtx insn)
9372 {
9373 struct mips16_constant *c, *next;
9374 int align;
9375
9376 align = 0;
9377 for (c = constants; c != NULL; c = next)
9378 {
9379 /* If necessary, increase the alignment of PC. */
9380 if (align < GET_MODE_SIZE (c->mode))
9381 {
9382 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
9383 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
9384 }
9385 align = GET_MODE_SIZE (c->mode);
9386
9387 insn = emit_label_after (c->label, insn);
9388 insn = dump_constants_1 (c->mode, c->value, insn);
9389
9390 next = c->next;
9391 free (c);
9392 }
9393
9394 emit_barrier_after (insn);
9395 }
9396
9397 /* Return the length of instruction INSN. */
9398
9399 static int
9400 mips16_insn_length (rtx insn)
9401 {
9402 if (JUMP_P (insn))
9403 {
9404 rtx body = PATTERN (insn);
9405 if (GET_CODE (body) == ADDR_VEC)
9406 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
9407 if (GET_CODE (body) == ADDR_DIFF_VEC)
9408 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
9409 }
9410 return get_attr_length (insn);
9411 }
9412
9413 /* Rewrite *X so that constant pool references refer to the constant's
9414 label instead. DATA points to the constant pool structure. */
9415
9416 static int
9417 mips16_rewrite_pool_refs (rtx *x, void *data)
9418 {
9419 struct mips16_constant_pool *pool = data;
9420 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
9421 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
9422 get_pool_constant (*x),
9423 get_pool_mode (*x)));
9424 return 0;
9425 }
9426
9427 /* Build MIPS16 constant pools. */
9428
9429 static void
9430 mips16_lay_out_constants (void)
9431 {
9432 struct mips16_constant_pool pool;
9433 rtx insn, barrier;
9434
9435 barrier = 0;
9436 memset (&pool, 0, sizeof (pool));
9437 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9438 {
9439 /* Rewrite constant pool references in INSN. */
9440 if (INSN_P (insn))
9441 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
9442
9443 pool.insn_address += mips16_insn_length (insn);
9444
9445 if (pool.first != NULL)
9446 {
9447 /* If there are no natural barriers between the first user of
9448 the pool and the highest acceptable address, we'll need to
9449 create a new instruction to jump around the constant pool.
9450 In the worst case, this instruction will be 4 bytes long.
9451
9452 If it's too late to do this transformation after INSN,
9453 do it immediately before INSN. */
9454 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
9455 {
9456 rtx label, jump;
9457
9458 label = gen_label_rtx ();
9459
9460 jump = emit_jump_insn_before (gen_jump (label), insn);
9461 JUMP_LABEL (jump) = label;
9462 LABEL_NUSES (label) = 1;
9463 barrier = emit_barrier_after (jump);
9464
9465 emit_label_after (label, barrier);
9466 pool.insn_address += 4;
9467 }
9468
9469 /* See whether the constant pool is now out of range of the first
9470 user. If so, output the constants after the previous barrier.
9471 Note that any instructions between BARRIER and INSN (inclusive)
9472 will use negative offsets to refer to the pool. */
9473 if (pool.insn_address > pool.highest_address)
9474 {
9475 dump_constants (pool.first, barrier);
9476 pool.first = NULL;
9477 barrier = 0;
9478 }
9479 else if (BARRIER_P (insn))
9480 barrier = insn;
9481 }
9482 }
9483 dump_constants (pool.first, get_last_insn ());
9484 }
9485 \f
9486 /* A temporary variable used by for_each_rtx callbacks, etc. */
9487 static rtx mips_sim_insn;
9488
9489 /* A structure representing the state of the processor pipeline.
9490 Used by the mips_sim_* family of functions. */
9491 struct mips_sim {
9492 /* The maximum number of instructions that can be issued in a cycle.
9493 (Caches mips_issue_rate.) */
9494 unsigned int issue_rate;
9495
9496 /* The current simulation time. */
9497 unsigned int time;
9498
9499 /* How many more instructions can be issued in the current cycle. */
9500 unsigned int insns_left;
9501
9502 /* LAST_SET[X].INSN is the last instruction to set register X.
9503 LAST_SET[X].TIME is the time at which that instruction was issued.
9504 INSN is null if no instruction has yet set register X. */
9505 struct {
9506 rtx insn;
9507 unsigned int time;
9508 } last_set[FIRST_PSEUDO_REGISTER];
9509
9510 /* The pipeline's current DFA state. */
9511 state_t dfa_state;
9512 };
9513
9514 /* Reset STATE to the initial simulation state. */
9515
9516 static void
9517 mips_sim_reset (struct mips_sim *state)
9518 {
9519 state->time = 0;
9520 state->insns_left = state->issue_rate;
9521 memset (&state->last_set, 0, sizeof (state->last_set));
9522 state_reset (state->dfa_state);
9523 }
9524
9525 /* Initialize STATE before its first use. DFA_STATE points to an
9526 allocated but uninitialized DFA state. */
9527
9528 static void
9529 mips_sim_init (struct mips_sim *state, state_t dfa_state)
9530 {
9531 state->issue_rate = mips_issue_rate ();
9532 state->dfa_state = dfa_state;
9533 mips_sim_reset (state);
9534 }
9535
9536 /* Advance STATE by one clock cycle. */
9537
9538 static void
9539 mips_sim_next_cycle (struct mips_sim *state)
9540 {
9541 state->time++;
9542 state->insns_left = state->issue_rate;
9543 state_transition (state->dfa_state, 0);
9544 }
9545
9546 /* Advance simulation state STATE until instruction INSN can read
9547 register REG. */
9548
9549 static void
9550 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
9551 {
9552 unsigned int i;
9553
9554 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
9555 if (state->last_set[REGNO (reg) + i].insn != 0)
9556 {
9557 unsigned int t;
9558
9559 t = state->last_set[REGNO (reg) + i].time;
9560 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
9561 while (state->time < t)
9562 mips_sim_next_cycle (state);
9563 }
9564 }
9565
9566 /* A for_each_rtx callback. If *X is a register, advance simulation state
9567 DATA until mips_sim_insn can read the register's value. */
9568
9569 static int
9570 mips_sim_wait_regs_2 (rtx *x, void *data)
9571 {
9572 if (REG_P (*x))
9573 mips_sim_wait_reg (data, mips_sim_insn, *x);
9574 return 0;
9575 }
9576
9577 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
9578
9579 static void
9580 mips_sim_wait_regs_1 (rtx *x, void *data)
9581 {
9582 for_each_rtx (x, mips_sim_wait_regs_2, data);
9583 }
9584
9585 /* Advance simulation state STATE until all of INSN's register
9586 dependencies are satisfied. */
9587
9588 static void
9589 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
9590 {
9591 mips_sim_insn = insn;
9592 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
9593 }
9594
9595 /* Advance simulation state STATE until the units required by
9596 instruction INSN are available. */
9597
9598 static void
9599 mips_sim_wait_units (struct mips_sim *state, rtx insn)
9600 {
9601 state_t tmp_state;
9602
9603 tmp_state = alloca (state_size ());
9604 while (state->insns_left == 0
9605 || (memcpy (tmp_state, state->dfa_state, state_size ()),
9606 state_transition (tmp_state, insn) >= 0))
9607 mips_sim_next_cycle (state);
9608 }
9609
9610 /* Advance simulation state STATE until INSN is ready to issue. */
9611
9612 static void
9613 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
9614 {
9615 mips_sim_wait_regs (state, insn);
9616 mips_sim_wait_units (state, insn);
9617 }
9618
9619 /* mips_sim_insn has just set X. Update the LAST_SET array
9620 in simulation state DATA. */
9621
9622 static void
9623 mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
9624 {
9625 struct mips_sim *state;
9626 unsigned int i;
9627
9628 state = data;
9629 if (REG_P (x))
9630 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
9631 {
9632 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
9633 state->last_set[REGNO (x) + i].time = state->time;
9634 }
9635 }
9636
9637 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
9638 can issue immediately (i.e., that mips_sim_wait_insn has already
9639 been called). */
9640
9641 static void
9642 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
9643 {
9644 state_transition (state->dfa_state, insn);
9645 state->insns_left--;
9646
9647 mips_sim_insn = insn;
9648 note_stores (PATTERN (insn), mips_sim_record_set, state);
9649 }
9650
9651 /* Simulate issuing a NOP in state STATE. */
9652
9653 static void
9654 mips_sim_issue_nop (struct mips_sim *state)
9655 {
9656 if (state->insns_left == 0)
9657 mips_sim_next_cycle (state);
9658 state->insns_left--;
9659 }
9660
9661 /* Update simulation state STATE so that it's ready to accept the instruction
9662 after INSN. INSN should be part of the main rtl chain, not a member of a
9663 SEQUENCE. */
9664
9665 static void
9666 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
9667 {
9668 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
9669 if (JUMP_P (insn))
9670 mips_sim_issue_nop (state);
9671
9672 switch (GET_CODE (SEQ_BEGIN (insn)))
9673 {
9674 case CODE_LABEL:
9675 case CALL_INSN:
9676 /* We can't predict the processor state after a call or label. */
9677 mips_sim_reset (state);
9678 break;
9679
9680 case JUMP_INSN:
9681 /* The delay slots of branch likely instructions are only executed
9682 when the branch is taken. Therefore, if the caller has simulated
9683 the delay slot instruction, STATE does not really reflect the state
9684 of the pipeline for the instruction after the delay slot. Also,
9685 branch likely instructions tend to incur a penalty when not taken,
9686 so there will probably be an extra delay between the branch and
9687 the instruction after the delay slot. */
9688 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
9689 mips_sim_reset (state);
9690 break;
9691
9692 default:
9693 break;
9694 }
9695 }
9696 \f
9697 /* The VR4130 pipeline issues aligned pairs of instructions together,
9698 but it stalls the second instruction if it depends on the first.
9699 In order to cut down the amount of logic required, this dependence
9700 check is not based on a full instruction decode. Instead, any non-SPECIAL
9701 instruction is assumed to modify the register specified by bits 20-16
9702 (which is usually the "rt" field).
9703
9704 In beq, beql, bne and bnel instructions, the rt field is actually an
9705 input, so we can end up with a false dependence between the branch
9706 and its delay slot. If this situation occurs in instruction INSN,
9707 try to avoid it by swapping rs and rt. */
9708
9709 static void
9710 vr4130_avoid_branch_rt_conflict (rtx insn)
9711 {
9712 rtx first, second;
9713
9714 first = SEQ_BEGIN (insn);
9715 second = SEQ_END (insn);
9716 if (JUMP_P (first)
9717 && NONJUMP_INSN_P (second)
9718 && GET_CODE (PATTERN (first)) == SET
9719 && GET_CODE (SET_DEST (PATTERN (first))) == PC
9720 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
9721 {
9722 /* Check for the right kind of condition. */
9723 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
9724 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
9725 && REG_P (XEXP (cond, 0))
9726 && REG_P (XEXP (cond, 1))
9727 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
9728 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
9729 {
9730 /* SECOND mentions the rt register but not the rs register. */
9731 rtx tmp = XEXP (cond, 0);
9732 XEXP (cond, 0) = XEXP (cond, 1);
9733 XEXP (cond, 1) = tmp;
9734 }
9735 }
9736 }
9737
9738 /* Implement -mvr4130-align. Go through each basic block and simulate the
9739 processor pipeline. If we find that a pair of instructions could execute
9740 in parallel, and the first of those instruction is not 8-byte aligned,
9741 insert a nop to make it aligned. */
9742
9743 static void
9744 vr4130_align_insns (void)
9745 {
9746 struct mips_sim state;
9747 rtx insn, subinsn, last, last2, next;
9748 bool aligned_p;
9749
9750 dfa_start ();
9751
9752 /* LAST is the last instruction before INSN to have a nonzero length.
9753 LAST2 is the last such instruction before LAST. */
9754 last = 0;
9755 last2 = 0;
9756
9757 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
9758 aligned_p = true;
9759
9760 mips_sim_init (&state, alloca (state_size ()));
9761 for (insn = get_insns (); insn != 0; insn = next)
9762 {
9763 unsigned int length;
9764
9765 next = NEXT_INSN (insn);
9766
9767 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
9768 This isn't really related to the alignment pass, but we do it on
9769 the fly to avoid a separate instruction walk. */
9770 vr4130_avoid_branch_rt_conflict (insn);
9771
9772 if (USEFUL_INSN_P (insn))
9773 FOR_EACH_SUBINSN (subinsn, insn)
9774 {
9775 mips_sim_wait_insn (&state, subinsn);
9776
9777 /* If we want this instruction to issue in parallel with the
9778 previous one, make sure that the previous instruction is
9779 aligned. There are several reasons why this isn't worthwhile
9780 when the second instruction is a call:
9781
9782 - Calls are less likely to be performance critical,
9783 - There's a good chance that the delay slot can execute
9784 in parallel with the call.
9785 - The return address would then be unaligned.
9786
9787 In general, if we're going to insert a nop between instructions
9788 X and Y, it's better to insert it immediately after X. That
9789 way, if the nop makes Y aligned, it will also align any labels
9790 between X and Y. */
9791 if (state.insns_left != state.issue_rate
9792 && !CALL_P (subinsn))
9793 {
9794 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
9795 {
9796 /* SUBINSN is the first instruction in INSN and INSN is
9797 aligned. We want to align the previous instruction
9798 instead, so insert a nop between LAST2 and LAST.
9799
9800 Note that LAST could be either a single instruction
9801 or a branch with a delay slot. In the latter case,
9802 LAST, like INSN, is already aligned, but the delay
9803 slot must have some extra delay that stops it from
9804 issuing at the same time as the branch. We therefore
9805 insert a nop before the branch in order to align its
9806 delay slot. */
9807 emit_insn_after (gen_nop (), last2);
9808 aligned_p = false;
9809 }
9810 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
9811 {
9812 /* SUBINSN is the delay slot of INSN, but INSN is
9813 currently unaligned. Insert a nop between
9814 LAST and INSN to align it. */
9815 emit_insn_after (gen_nop (), last);
9816 aligned_p = true;
9817 }
9818 }
9819 mips_sim_issue_insn (&state, subinsn);
9820 }
9821 mips_sim_finish_insn (&state, insn);
9822
9823 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
9824 length = get_attr_length (insn);
9825 if (length > 0)
9826 {
9827 /* If the instruction is an asm statement or multi-instruction
9828 mips.md patern, the length is only an estimate. Insert an
9829 8 byte alignment after it so that the following instructions
9830 can be handled correctly. */
9831 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
9832 && (recog_memoized (insn) < 0 || length >= 8))
9833 {
9834 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
9835 next = NEXT_INSN (next);
9836 mips_sim_next_cycle (&state);
9837 aligned_p = true;
9838 }
9839 else if (length & 4)
9840 aligned_p = !aligned_p;
9841 last2 = last;
9842 last = insn;
9843 }
9844
9845 /* See whether INSN is an aligned label. */
9846 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
9847 aligned_p = true;
9848 }
9849 dfa_finish ();
9850 }
9851 \f
9852 /* Subroutine of mips_reorg. If there is a hazard between INSN
9853 and a previous instruction, avoid it by inserting nops after
9854 instruction AFTER.
9855
9856 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
9857 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
9858 before using the value of that register. *HILO_DELAY counts the
9859 number of instructions since the last hilo hazard (that is,
9860 the number of instructions since the last mflo or mfhi).
9861
9862 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
9863 for the next instruction.
9864
9865 LO_REG is an rtx for the LO register, used in dependence checking. */
9866
9867 static void
9868 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
9869 rtx *delayed_reg, rtx lo_reg)
9870 {
9871 rtx pattern, set;
9872 int nops, ninsns;
9873
9874 if (!INSN_P (insn))
9875 return;
9876
9877 pattern = PATTERN (insn);
9878
9879 /* Do not put the whole function in .set noreorder if it contains
9880 an asm statement. We don't know whether there will be hazards
9881 between the asm statement and the gcc-generated code. */
9882 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
9883 cfun->machine->all_noreorder_p = false;
9884
9885 /* Ignore zero-length instructions (barriers and the like). */
9886 ninsns = get_attr_length (insn) / 4;
9887 if (ninsns == 0)
9888 return;
9889
9890 /* Work out how many nops are needed. Note that we only care about
9891 registers that are explicitly mentioned in the instruction's pattern.
9892 It doesn't matter that calls use the argument registers or that they
9893 clobber hi and lo. */
9894 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
9895 nops = 2 - *hilo_delay;
9896 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
9897 nops = 1;
9898 else
9899 nops = 0;
9900
9901 /* Insert the nops between this instruction and the previous one.
9902 Each new nop takes us further from the last hilo hazard. */
9903 *hilo_delay += nops;
9904 while (nops-- > 0)
9905 emit_insn_after (gen_hazard_nop (), after);
9906
9907 /* Set up the state for the next instruction. */
9908 *hilo_delay += ninsns;
9909 *delayed_reg = 0;
9910 if (INSN_CODE (insn) >= 0)
9911 switch (get_attr_hazard (insn))
9912 {
9913 case HAZARD_NONE:
9914 break;
9915
9916 case HAZARD_HILO:
9917 *hilo_delay = 0;
9918 break;
9919
9920 case HAZARD_DELAY:
9921 set = single_set (insn);
9922 gcc_assert (set != 0);
9923 *delayed_reg = SET_DEST (set);
9924 break;
9925 }
9926 }
9927
9928
9929 /* Go through the instruction stream and insert nops where necessary.
9930 See if the whole function can then be put into .set noreorder &
9931 .set nomacro. */
9932
9933 static void
9934 mips_avoid_hazards (void)
9935 {
9936 rtx insn, last_insn, lo_reg, delayed_reg;
9937 int hilo_delay, i;
9938
9939 /* Force all instructions to be split into their final form. */
9940 split_all_insns_noflow ();
9941
9942 /* Recalculate instruction lengths without taking nops into account. */
9943 cfun->machine->ignore_hazard_length_p = true;
9944 shorten_branches (get_insns ());
9945
9946 cfun->machine->all_noreorder_p = true;
9947
9948 /* Profiled functions can't be all noreorder because the profiler
9949 support uses assembler macros. */
9950 if (current_function_profile)
9951 cfun->machine->all_noreorder_p = false;
9952
9953 /* Code compiled with -mfix-vr4120 can't be all noreorder because
9954 we rely on the assembler to work around some errata. */
9955 if (TARGET_FIX_VR4120)
9956 cfun->machine->all_noreorder_p = false;
9957
9958 /* The same is true for -mfix-vr4130 if we might generate mflo or
9959 mfhi instructions. Note that we avoid using mflo and mfhi if
9960 the VR4130 macc and dmacc instructions are available instead;
9961 see the *mfhilo_{si,di}_macc patterns. */
9962 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
9963 cfun->machine->all_noreorder_p = false;
9964
9965 last_insn = 0;
9966 hilo_delay = 2;
9967 delayed_reg = 0;
9968 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
9969
9970 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
9971 if (INSN_P (insn))
9972 {
9973 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
9974 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
9975 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
9976 &hilo_delay, &delayed_reg, lo_reg);
9977 else
9978 mips_avoid_hazard (last_insn, insn, &hilo_delay,
9979 &delayed_reg, lo_reg);
9980
9981 last_insn = insn;
9982 }
9983 }
9984
9985
9986 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
9987
9988 static void
9989 mips_reorg (void)
9990 {
9991 if (TARGET_MIPS16)
9992 mips16_lay_out_constants ();
9993 else if (TARGET_EXPLICIT_RELOCS)
9994 {
9995 if (mips_flag_delayed_branch)
9996 dbr_schedule (get_insns ());
9997 mips_avoid_hazards ();
9998 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
9999 vr4130_align_insns ();
10000 }
10001 }
10002
10003 /* This function does three things:
10004
10005 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
10006 - Register the mips16 hardware floating point stubs.
10007 - Register the gofast functions if selected using --enable-gofast. */
10008
10009 #include "config/gofast.h"
10010
10011 static void
10012 mips_init_libfuncs (void)
10013 {
10014 if (TARGET_FIX_VR4120)
10015 {
10016 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
10017 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
10018 }
10019
10020 if (mips16_hard_float)
10021 {
10022 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
10023 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
10024 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
10025 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
10026
10027 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
10028 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
10029 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
10030 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
10031 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
10032 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
10033
10034 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
10035 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
10036
10037 if (TARGET_DOUBLE_FLOAT)
10038 {
10039 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
10040 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
10041 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
10042 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
10043
10044 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
10045 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
10046 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
10047 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
10048 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
10049 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
10050
10051 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
10052 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
10053
10054 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
10055 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
10056 }
10057 }
10058 else
10059 gofast_maybe_init_libfuncs ();
10060 }
10061
10062 /* Return a number assessing the cost of moving a register in class
10063 FROM to class TO. The classes are expressed using the enumeration
10064 values such as `GENERAL_REGS'. A value of 2 is the default; other
10065 values are interpreted relative to that.
10066
10067 It is not required that the cost always equal 2 when FROM is the
10068 same as TO; on some machines it is expensive to move between
10069 registers if they are not general registers.
10070
10071 If reload sees an insn consisting of a single `set' between two
10072 hard registers, and if `REGISTER_MOVE_COST' applied to their
10073 classes returns a value of 2, reload does not check to ensure that
10074 the constraints of the insn are met. Setting a cost of other than
10075 2 will allow reload to verify that the constraints are met. You
10076 should do this if the `movM' pattern's constraints do not allow
10077 such copying.
10078
10079 ??? We make the cost of moving from HI/LO into general
10080 registers the same as for one of moving general registers to
10081 HI/LO for TARGET_MIPS16 in order to prevent allocating a
10082 pseudo to HI/LO. This might hurt optimizations though, it
10083 isn't clear if it is wise. And it might not work in all cases. We
10084 could solve the DImode LO reg problem by using a multiply, just
10085 like reload_{in,out}si. We could solve the SImode/HImode HI reg
10086 problem by using divide instructions. divu puts the remainder in
10087 the HI reg, so doing a divide by -1 will move the value in the HI
10088 reg for all values except -1. We could handle that case by using a
10089 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
10090 a compare/branch to test the input value to see which instruction
10091 we need to use. This gets pretty messy, but it is feasible. */
10092
10093 int
10094 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
10095 enum reg_class to, enum reg_class from)
10096 {
10097 if (from == M16_REGS && GR_REG_CLASS_P (to))
10098 return 2;
10099 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
10100 return 2;
10101 else if (GR_REG_CLASS_P (from))
10102 {
10103 if (to == M16_REGS)
10104 return 2;
10105 else if (to == M16_NA_REGS)
10106 return 2;
10107 else if (GR_REG_CLASS_P (to))
10108 {
10109 if (TARGET_MIPS16)
10110 return 4;
10111 else
10112 return 2;
10113 }
10114 else if (to == FP_REGS)
10115 return 4;
10116 else if (reg_class_subset_p (to, ACC_REGS))
10117 {
10118 if (TARGET_MIPS16)
10119 return 12;
10120 else
10121 return 6;
10122 }
10123 else if (COP_REG_CLASS_P (to))
10124 {
10125 return 5;
10126 }
10127 }
10128 else if (from == FP_REGS)
10129 {
10130 if (GR_REG_CLASS_P (to))
10131 return 4;
10132 else if (to == FP_REGS)
10133 return 2;
10134 else if (to == ST_REGS)
10135 return 8;
10136 }
10137 else if (reg_class_subset_p (from, ACC_REGS))
10138 {
10139 if (GR_REG_CLASS_P (to))
10140 {
10141 if (TARGET_MIPS16)
10142 return 12;
10143 else
10144 return 6;
10145 }
10146 }
10147 else if (from == ST_REGS && GR_REG_CLASS_P (to))
10148 return 4;
10149 else if (COP_REG_CLASS_P (from))
10150 {
10151 return 5;
10152 }
10153
10154 /* Fall through.
10155 ??? What cases are these? Shouldn't we return 2 here? */
10156
10157 return 12;
10158 }
10159
10160 /* Return the length of INSN. LENGTH is the initial length computed by
10161 attributes in the machine-description file. */
10162
10163 int
10164 mips_adjust_insn_length (rtx insn, int length)
10165 {
10166 /* A unconditional jump has an unfilled delay slot if it is not part
10167 of a sequence. A conditional jump normally has a delay slot, but
10168 does not on MIPS16. */
10169 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
10170 length += 4;
10171
10172 /* See how many nops might be needed to avoid hardware hazards. */
10173 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
10174 switch (get_attr_hazard (insn))
10175 {
10176 case HAZARD_NONE:
10177 break;
10178
10179 case HAZARD_DELAY:
10180 length += 4;
10181 break;
10182
10183 case HAZARD_HILO:
10184 length += 8;
10185 break;
10186 }
10187
10188 /* All MIPS16 instructions are a measly two bytes. */
10189 if (TARGET_MIPS16)
10190 length /= 2;
10191
10192 return length;
10193 }
10194
10195
10196 /* Return an asm sequence to start a noat block and load the address
10197 of a label into $1. */
10198
10199 const char *
10200 mips_output_load_label (void)
10201 {
10202 if (TARGET_EXPLICIT_RELOCS)
10203 switch (mips_abi)
10204 {
10205 case ABI_N32:
10206 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
10207
10208 case ABI_64:
10209 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
10210
10211 default:
10212 if (ISA_HAS_LOAD_DELAY)
10213 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
10214 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
10215 }
10216 else
10217 {
10218 if (Pmode == DImode)
10219 return "%[dla\t%@,%0";
10220 else
10221 return "%[la\t%@,%0";
10222 }
10223 }
10224
10225 /* Return the assembly code for INSN, which has the operands given by
10226 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
10227 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
10228 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
10229 version of BRANCH_IF_TRUE. */
10230
10231 const char *
10232 mips_output_conditional_branch (rtx insn, rtx *operands,
10233 const char *branch_if_true,
10234 const char *branch_if_false)
10235 {
10236 unsigned int length;
10237 rtx taken, not_taken;
10238
10239 length = get_attr_length (insn);
10240 if (length <= 8)
10241 {
10242 /* Just a simple conditional branch. */
10243 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
10244 return branch_if_true;
10245 }
10246
10247 /* Generate a reversed branch around a direct jump. This fallback does
10248 not use branch-likely instructions. */
10249 mips_branch_likely = false;
10250 not_taken = gen_label_rtx ();
10251 taken = operands[1];
10252
10253 /* Generate the reversed branch to NOT_TAKEN. */
10254 operands[1] = not_taken;
10255 output_asm_insn (branch_if_false, operands);
10256
10257 /* If INSN has a delay slot, we must provide delay slots for both the
10258 branch to NOT_TAKEN and the conditional jump. We must also ensure
10259 that INSN's delay slot is executed in the appropriate cases. */
10260 if (final_sequence)
10261 {
10262 /* This first delay slot will always be executed, so use INSN's
10263 delay slot if is not annulled. */
10264 if (!INSN_ANNULLED_BRANCH_P (insn))
10265 {
10266 final_scan_insn (XVECEXP (final_sequence, 0, 1),
10267 asm_out_file, optimize, 1, NULL);
10268 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
10269 }
10270 else
10271 output_asm_insn ("nop", 0);
10272 fprintf (asm_out_file, "\n");
10273 }
10274
10275 /* Output the unconditional branch to TAKEN. */
10276 if (length <= 16)
10277 output_asm_insn ("j\t%0%/", &taken);
10278 else
10279 {
10280 output_asm_insn (mips_output_load_label (), &taken);
10281 output_asm_insn ("jr\t%@%]%/", 0);
10282 }
10283
10284 /* Now deal with its delay slot; see above. */
10285 if (final_sequence)
10286 {
10287 /* This delay slot will only be executed if the branch is taken.
10288 Use INSN's delay slot if is annulled. */
10289 if (INSN_ANNULLED_BRANCH_P (insn))
10290 {
10291 final_scan_insn (XVECEXP (final_sequence, 0, 1),
10292 asm_out_file, optimize, 1, NULL);
10293 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
10294 }
10295 else
10296 output_asm_insn ("nop", 0);
10297 fprintf (asm_out_file, "\n");
10298 }
10299
10300 /* Output NOT_TAKEN. */
10301 (*targetm.asm_out.internal_label) (asm_out_file, "L",
10302 CODE_LABEL_NUMBER (not_taken));
10303 return "";
10304 }
10305
10306 /* Return the assembly code for INSN, which branches to OPERANDS[1]
10307 if some ordered condition is true. The condition is given by
10308 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
10309 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
10310 its second is always zero. */
10311
10312 const char *
10313 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
10314 {
10315 const char *branch[2];
10316
10317 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
10318 Make BRANCH[0] branch on the inverse condition. */
10319 switch (GET_CODE (operands[0]))
10320 {
10321 /* These cases are equivalent to comparisons against zero. */
10322 case LEU:
10323 inverted_p = !inverted_p;
10324 /* Fall through. */
10325 case GTU:
10326 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
10327 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
10328 break;
10329
10330 /* These cases are always true or always false. */
10331 case LTU:
10332 inverted_p = !inverted_p;
10333 /* Fall through. */
10334 case GEU:
10335 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
10336 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
10337 break;
10338
10339 default:
10340 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
10341 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
10342 break;
10343 }
10344 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
10345 }
10346 \f
10347 /* Used to output div or ddiv instruction DIVISION, which has the operands
10348 given by OPERANDS. Add in a divide-by-zero check if needed.
10349
10350 When working around R4000 and R4400 errata, we need to make sure that
10351 the division is not immediately followed by a shift[1][2]. We also
10352 need to stop the division from being put into a branch delay slot[3].
10353 The easiest way to avoid both problems is to add a nop after the
10354 division. When a divide-by-zero check is needed, this nop can be
10355 used to fill the branch delay slot.
10356
10357 [1] If a double-word or a variable shift executes immediately
10358 after starting an integer division, the shift may give an
10359 incorrect result. See quotations of errata #16 and #28 from
10360 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
10361 in mips.md for details.
10362
10363 [2] A similar bug to [1] exists for all revisions of the
10364 R4000 and the R4400 when run in an MC configuration.
10365 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
10366
10367 "19. In this following sequence:
10368
10369 ddiv (or ddivu or div or divu)
10370 dsll32 (or dsrl32, dsra32)
10371
10372 if an MPT stall occurs, while the divide is slipping the cpu
10373 pipeline, then the following double shift would end up with an
10374 incorrect result.
10375
10376 Workaround: The compiler needs to avoid generating any
10377 sequence with divide followed by extended double shift."
10378
10379 This erratum is also present in "MIPS R4400MC Errata, Processor
10380 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
10381 & 3.0" as errata #10 and #4, respectively.
10382
10383 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
10384 (also valid for MIPS R4000MC processors):
10385
10386 "52. R4000SC: This bug does not apply for the R4000PC.
10387
10388 There are two flavors of this bug:
10389
10390 1) If the instruction just after divide takes an RF exception
10391 (tlb-refill, tlb-invalid) and gets an instruction cache
10392 miss (both primary and secondary) and the line which is
10393 currently in secondary cache at this index had the first
10394 data word, where the bits 5..2 are set, then R4000 would
10395 get a wrong result for the div.
10396
10397 ##1
10398 nop
10399 div r8, r9
10400 ------------------- # end-of page. -tlb-refill
10401 nop
10402 ##2
10403 nop
10404 div r8, r9
10405 ------------------- # end-of page. -tlb-invalid
10406 nop
10407
10408 2) If the divide is in the taken branch delay slot, where the
10409 target takes RF exception and gets an I-cache miss for the
10410 exception vector or where I-cache miss occurs for the
10411 target address, under the above mentioned scenarios, the
10412 div would get wrong results.
10413
10414 ##1
10415 j r2 # to next page mapped or unmapped
10416 div r8,r9 # this bug would be there as long
10417 # as there is an ICache miss and
10418 nop # the "data pattern" is present
10419
10420 ##2
10421 beq r0, r0, NextPage # to Next page
10422 div r8,r9
10423 nop
10424
10425 This bug is present for div, divu, ddiv, and ddivu
10426 instructions.
10427
10428 Workaround: For item 1), OS could make sure that the next page
10429 after the divide instruction is also mapped. For item 2), the
10430 compiler could make sure that the divide instruction is not in
10431 the branch delay slot."
10432
10433 These processors have PRId values of 0x00004220 and 0x00004300 for
10434 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
10435
10436 const char *
10437 mips_output_division (const char *division, rtx *operands)
10438 {
10439 const char *s;
10440
10441 s = division;
10442 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
10443 {
10444 output_asm_insn (s, operands);
10445 s = "nop";
10446 }
10447 if (TARGET_CHECK_ZERO_DIV)
10448 {
10449 if (TARGET_MIPS16)
10450 {
10451 output_asm_insn (s, operands);
10452 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
10453 }
10454 else if (GENERATE_DIVIDE_TRAPS)
10455 {
10456 output_asm_insn (s, operands);
10457 s = "teq\t%2,%.,7";
10458 }
10459 else
10460 {
10461 output_asm_insn ("%(bne\t%2,%.,1f", operands);
10462 output_asm_insn (s, operands);
10463 s = "break\t7%)\n1:";
10464 }
10465 }
10466 return s;
10467 }
10468 \f
10469 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
10470 with a final "000" replaced by "k". Ignore case.
10471
10472 Note: this function is shared between GCC and GAS. */
10473
10474 static bool
10475 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
10476 {
10477 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
10478 given++, canonical++;
10479
10480 return ((*given == 0 && *canonical == 0)
10481 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
10482 }
10483
10484
10485 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
10486 CPU name. We've traditionally allowed a lot of variation here.
10487
10488 Note: this function is shared between GCC and GAS. */
10489
10490 static bool
10491 mips_matching_cpu_name_p (const char *canonical, const char *given)
10492 {
10493 /* First see if the name matches exactly, or with a final "000"
10494 turned into "k". */
10495 if (mips_strict_matching_cpu_name_p (canonical, given))
10496 return true;
10497
10498 /* If not, try comparing based on numerical designation alone.
10499 See if GIVEN is an unadorned number, or 'r' followed by a number. */
10500 if (TOLOWER (*given) == 'r')
10501 given++;
10502 if (!ISDIGIT (*given))
10503 return false;
10504
10505 /* Skip over some well-known prefixes in the canonical name,
10506 hoping to find a number there too. */
10507 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
10508 canonical += 2;
10509 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
10510 canonical += 2;
10511 else if (TOLOWER (canonical[0]) == 'r')
10512 canonical += 1;
10513
10514 return mips_strict_matching_cpu_name_p (canonical, given);
10515 }
10516
10517
10518 /* Return the mips_cpu_info entry for the processor or ISA given
10519 by CPU_STRING. Return null if the string isn't recognized.
10520
10521 A similar function exists in GAS. */
10522
10523 static const struct mips_cpu_info *
10524 mips_parse_cpu (const char *cpu_string)
10525 {
10526 const struct mips_cpu_info *p;
10527 const char *s;
10528
10529 /* In the past, we allowed upper-case CPU names, but it doesn't
10530 work well with the multilib machinery. */
10531 for (s = cpu_string; *s != 0; s++)
10532 if (ISUPPER (*s))
10533 {
10534 warning (0, "the cpu name must be lower case");
10535 break;
10536 }
10537
10538 /* 'from-abi' selects the most compatible architecture for the given
10539 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
10540 EABIs, we have to decide whether we're using the 32-bit or 64-bit
10541 version. Look first at the -mgp options, if given, otherwise base
10542 the choice on MASK_64BIT in TARGET_DEFAULT. */
10543 if (strcasecmp (cpu_string, "from-abi") == 0)
10544 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
10545 : ABI_NEEDS_64BIT_REGS ? 3
10546 : (TARGET_64BIT ? 3 : 1));
10547
10548 /* 'default' has traditionally been a no-op. Probably not very useful. */
10549 if (strcasecmp (cpu_string, "default") == 0)
10550 return 0;
10551
10552 for (p = mips_cpu_info_table; p->name != 0; p++)
10553 if (mips_matching_cpu_name_p (p->name, cpu_string))
10554 return p;
10555
10556 return 0;
10557 }
10558
10559
10560 /* Return the processor associated with the given ISA level, or null
10561 if the ISA isn't valid. */
10562
10563 static const struct mips_cpu_info *
10564 mips_cpu_info_from_isa (int isa)
10565 {
10566 const struct mips_cpu_info *p;
10567
10568 for (p = mips_cpu_info_table; p->name != 0; p++)
10569 if (p->isa == isa)
10570 return p;
10571
10572 return 0;
10573 }
10574 \f
10575 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
10576 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
10577 they only hold condition code modes, and CCmode is always considered to
10578 be 4 bytes wide. All other registers are word sized. */
10579
10580 unsigned int
10581 mips_hard_regno_nregs (int regno, enum machine_mode mode)
10582 {
10583 if (ST_REG_P (regno))
10584 return ((GET_MODE_SIZE (mode) + 3) / 4);
10585 else if (! FP_REG_P (regno))
10586 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
10587 else
10588 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
10589 }
10590
10591 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
10592 all BLKmode objects are returned in memory. Under the new (N32 and
10593 64-bit MIPS ABIs) small structures are returned in a register.
10594 Objects with varying size must still be returned in memory, of
10595 course. */
10596
10597 static bool
10598 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
10599 {
10600 if (TARGET_OLDABI)
10601 return (TYPE_MODE (type) == BLKmode);
10602 else
10603 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
10604 || (int_size_in_bytes (type) == -1));
10605 }
10606
10607 static bool
10608 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
10609 {
10610 return !TARGET_OLDABI;
10611 }
10612 \f
10613 /* Return true if INSN is a multiply-add or multiply-subtract
10614 instruction and PREV assigns to the accumulator operand. */
10615
10616 bool
10617 mips_linked_madd_p (rtx prev, rtx insn)
10618 {
10619 rtx x;
10620
10621 x = single_set (insn);
10622 if (x == 0)
10623 return false;
10624
10625 x = SET_SRC (x);
10626
10627 if (GET_CODE (x) == PLUS
10628 && GET_CODE (XEXP (x, 0)) == MULT
10629 && reg_set_p (XEXP (x, 1), prev))
10630 return true;
10631
10632 if (GET_CODE (x) == MINUS
10633 && GET_CODE (XEXP (x, 1)) == MULT
10634 && reg_set_p (XEXP (x, 0), prev))
10635 return true;
10636
10637 return false;
10638 }
10639 \f
10640 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
10641 that may clobber hi or lo. */
10642
10643 static rtx mips_macc_chains_last_hilo;
10644
10645 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
10646 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
10647
10648 static void
10649 mips_macc_chains_record (rtx insn)
10650 {
10651 if (get_attr_may_clobber_hilo (insn))
10652 mips_macc_chains_last_hilo = insn;
10653 }
10654
10655 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
10656 has NREADY elements, looking for a multiply-add or multiply-subtract
10657 instruction that is cumulative with mips_macc_chains_last_hilo.
10658 If there is one, promote it ahead of anything else that might
10659 clobber hi or lo. */
10660
10661 static void
10662 mips_macc_chains_reorder (rtx *ready, int nready)
10663 {
10664 int i, j;
10665
10666 if (mips_macc_chains_last_hilo != 0)
10667 for (i = nready - 1; i >= 0; i--)
10668 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
10669 {
10670 for (j = nready - 1; j > i; j--)
10671 if (recog_memoized (ready[j]) >= 0
10672 && get_attr_may_clobber_hilo (ready[j]))
10673 {
10674 mips_promote_ready (ready, i, j);
10675 break;
10676 }
10677 break;
10678 }
10679 }
10680 \f
10681 /* The last instruction to be scheduled. */
10682
10683 static rtx vr4130_last_insn;
10684
10685 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
10686 points to an rtx that is initially an instruction. Nullify the rtx
10687 if the instruction uses the value of register X. */
10688
10689 static void
10690 vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
10691 {
10692 rtx *insn_ptr = data;
10693 if (REG_P (x)
10694 && *insn_ptr != 0
10695 && reg_referenced_p (x, PATTERN (*insn_ptr)))
10696 *insn_ptr = 0;
10697 }
10698
10699 /* Return true if there is true register dependence between vr4130_last_insn
10700 and INSN. */
10701
10702 static bool
10703 vr4130_true_reg_dependence_p (rtx insn)
10704 {
10705 note_stores (PATTERN (vr4130_last_insn),
10706 vr4130_true_reg_dependence_p_1, &insn);
10707 return insn == 0;
10708 }
10709
10710 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
10711 the ready queue and that INSN2 is the instruction after it, return
10712 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
10713 in which INSN1 and INSN2 can probably issue in parallel, but for
10714 which (INSN2, INSN1) should be less sensitive to instruction
10715 alignment than (INSN1, INSN2). See 4130.md for more details. */
10716
10717 static bool
10718 vr4130_swap_insns_p (rtx insn1, rtx insn2)
10719 {
10720 dep_link_t dep;
10721
10722 /* Check for the following case:
10723
10724 1) there is some other instruction X with an anti dependence on INSN1;
10725 2) X has a higher priority than INSN2; and
10726 3) X is an arithmetic instruction (and thus has no unit restrictions).
10727
10728 If INSN1 is the last instruction blocking X, it would better to
10729 choose (INSN1, X) over (INSN2, INSN1). */
10730 FOR_EACH_DEP_LINK (dep, INSN_FORW_DEPS (insn1))
10731 if (DEP_LINK_KIND (dep) == REG_DEP_ANTI
10732 && INSN_PRIORITY (DEP_LINK_CON (dep)) > INSN_PRIORITY (insn2)
10733 && recog_memoized (DEP_LINK_CON (dep)) >= 0
10734 && get_attr_vr4130_class (DEP_LINK_CON (dep)) == VR4130_CLASS_ALU)
10735 return false;
10736
10737 if (vr4130_last_insn != 0
10738 && recog_memoized (insn1) >= 0
10739 && recog_memoized (insn2) >= 0)
10740 {
10741 /* See whether INSN1 and INSN2 use different execution units,
10742 or if they are both ALU-type instructions. If so, they can
10743 probably execute in parallel. */
10744 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
10745 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
10746 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
10747 {
10748 /* If only one of the instructions has a dependence on
10749 vr4130_last_insn, prefer to schedule the other one first. */
10750 bool dep1 = vr4130_true_reg_dependence_p (insn1);
10751 bool dep2 = vr4130_true_reg_dependence_p (insn2);
10752 if (dep1 != dep2)
10753 return dep1;
10754
10755 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
10756 is not an ALU-type instruction and if INSN1 uses the same
10757 execution unit. (Note that if this condition holds, we already
10758 know that INSN2 uses a different execution unit.) */
10759 if (class1 != VR4130_CLASS_ALU
10760 && recog_memoized (vr4130_last_insn) >= 0
10761 && class1 == get_attr_vr4130_class (vr4130_last_insn))
10762 return true;
10763 }
10764 }
10765 return false;
10766 }
10767
10768 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
10769 queue with at least two instructions. Swap the first two if
10770 vr4130_swap_insns_p says that it could be worthwhile. */
10771
10772 static void
10773 vr4130_reorder (rtx *ready, int nready)
10774 {
10775 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
10776 mips_promote_ready (ready, nready - 2, nready - 1);
10777 }
10778 \f
10779 /* Remove the instruction at index LOWER from ready queue READY and
10780 reinsert it in front of the instruction at index HIGHER. LOWER must
10781 be <= HIGHER. */
10782
10783 static void
10784 mips_promote_ready (rtx *ready, int lower, int higher)
10785 {
10786 rtx new_head;
10787 int i;
10788
10789 new_head = ready[lower];
10790 for (i = lower; i < higher; i++)
10791 ready[i] = ready[i + 1];
10792 ready[i] = new_head;
10793 }
10794
10795 /* Implement TARGET_SCHED_REORDER. */
10796
10797 static int
10798 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10799 rtx *ready, int *nreadyp, int cycle)
10800 {
10801 if (!reload_completed && TUNE_MACC_CHAINS)
10802 {
10803 if (cycle == 0)
10804 mips_macc_chains_last_hilo = 0;
10805 if (*nreadyp > 0)
10806 mips_macc_chains_reorder (ready, *nreadyp);
10807 }
10808 if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
10809 {
10810 if (cycle == 0)
10811 vr4130_last_insn = 0;
10812 if (*nreadyp > 1)
10813 vr4130_reorder (ready, *nreadyp);
10814 }
10815 return mips_issue_rate ();
10816 }
10817
10818 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
10819
10820 static int
10821 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10822 rtx insn, int more)
10823 {
10824 switch (GET_CODE (PATTERN (insn)))
10825 {
10826 case USE:
10827 case CLOBBER:
10828 /* Don't count USEs and CLOBBERs against the issue rate. */
10829 break;
10830
10831 default:
10832 more--;
10833 if (!reload_completed && TUNE_MACC_CHAINS)
10834 mips_macc_chains_record (insn);
10835 vr4130_last_insn = insn;
10836 break;
10837 }
10838 return more;
10839 }
10840 \f
10841 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
10842 dependencies have no cost. */
10843
10844 static int
10845 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
10846 rtx dep ATTRIBUTE_UNUSED, int cost)
10847 {
10848 if (REG_NOTE_KIND (link) != 0)
10849 return 0;
10850 return cost;
10851 }
10852
10853 /* Return the number of instructions that can be issued per cycle. */
10854
10855 static int
10856 mips_issue_rate (void)
10857 {
10858 switch (mips_tune)
10859 {
10860 case PROCESSOR_74KC:
10861 case PROCESSOR_74KF2_1:
10862 case PROCESSOR_74KF1_1:
10863 case PROCESSOR_74KF3_2:
10864 /* The 74k is not strictly quad-issue cpu, but can be seen as one
10865 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
10866 but in reality only a maximum of 3 insns can be issued as the
10867 floating point load/stores also require a slot in the AGEN pipe. */
10868 return 4;
10869
10870 case PROCESSOR_R4130:
10871 case PROCESSOR_R5400:
10872 case PROCESSOR_R5500:
10873 case PROCESSOR_R7000:
10874 case PROCESSOR_R9000:
10875 return 2;
10876
10877 case PROCESSOR_SB1:
10878 case PROCESSOR_SB1A:
10879 /* This is actually 4, but we get better performance if we claim 3.
10880 This is partly because of unwanted speculative code motion with the
10881 larger number, and partly because in most common cases we can't
10882 reach the theoretical max of 4. */
10883 return 3;
10884
10885 default:
10886 return 1;
10887 }
10888 }
10889
10890 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
10891 be as wide as the scheduling freedom in the DFA. */
10892
10893 static int
10894 mips_multipass_dfa_lookahead (void)
10895 {
10896 /* Can schedule up to 4 of the 6 function units in any one cycle. */
10897 if (TUNE_SB1)
10898 return 4;
10899
10900 return 0;
10901 }
10902
10903 /* Implements a store data bypass check. We need this because the cprestore
10904 pattern is type store, but defined using an UNSPEC. This UNSPEC causes the
10905 default routine to abort. We just return false for that case. */
10906 /* ??? Should try to give a better result here than assuming false. */
10907
10908 int
10909 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
10910 {
10911 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
10912 return false;
10913
10914 return ! store_data_bypass_p (out_insn, in_insn);
10915 }
10916 \f
10917 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
10918 return the first operand of the associated "pref" or "prefx" insn. */
10919
10920 rtx
10921 mips_prefetch_cookie (rtx write, rtx locality)
10922 {
10923 /* store_streamed / load_streamed. */
10924 if (INTVAL (locality) <= 0)
10925 return GEN_INT (INTVAL (write) + 4);
10926
10927 /* store / load. */
10928 if (INTVAL (locality) <= 2)
10929 return write;
10930
10931 /* store_retained / load_retained. */
10932 return GEN_INT (INTVAL (write) + 6);
10933 }
10934 \f
10935 /* MIPS builtin function support. */
10936
10937 struct builtin_description
10938 {
10939 /* The code of the main .md file instruction. See mips_builtin_type
10940 for more information. */
10941 enum insn_code icode;
10942
10943 /* The floating-point comparison code to use with ICODE, if any. */
10944 enum mips_fp_condition cond;
10945
10946 /* The name of the builtin function. */
10947 const char *name;
10948
10949 /* Specifies how the function should be expanded. */
10950 enum mips_builtin_type builtin_type;
10951
10952 /* The function's prototype. */
10953 enum mips_function_type function_type;
10954
10955 /* The target flags required for this function. */
10956 int target_flags;
10957 };
10958
10959 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
10960 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
10961 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10962 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10963 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
10964
10965 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
10966 TARGET_FLAGS. */
10967 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
10968 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
10969 "__builtin_mips_" #INSN "_" #COND "_s", \
10970 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
10971 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
10972 "__builtin_mips_" #INSN "_" #COND "_d", \
10973 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
10974
10975 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
10976 The lower and upper forms require TARGET_FLAGS while the any and all
10977 forms require MASK_MIPS3D. */
10978 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
10979 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10980 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
10981 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10982 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10983 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
10984 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10985 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10986 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
10987 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
10988 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10989 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
10990 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
10991
10992 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
10993 require MASK_MIPS3D. */
10994 #define CMP_4S_BUILTINS(INSN, COND) \
10995 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10996 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
10997 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10998 MASK_MIPS3D }, \
10999 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
11000 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
11001 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11002 MASK_MIPS3D }
11003
11004 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
11005 instruction requires TARGET_FLAGS. */
11006 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
11007 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
11008 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
11009 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11010 TARGET_FLAGS }, \
11011 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
11012 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
11013 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11014 TARGET_FLAGS }
11015
11016 /* Define all the builtins related to c.cond.fmt condition COND. */
11017 #define CMP_BUILTINS(COND) \
11018 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
11019 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
11020 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
11021 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
11022 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
11023 CMP_4S_BUILTINS (c, COND), \
11024 CMP_4S_BUILTINS (cabs, COND)
11025
11026 static const struct builtin_description mips_bdesc[] =
11027 {
11028 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11029 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11030 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11031 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11032 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
11033 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11034 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11035 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11036
11037 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
11038 MASK_PAIRED_SINGLE_FLOAT),
11039 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
11040 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
11041 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
11042 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
11043
11044 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
11045 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
11046 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
11047 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
11048 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
11049 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
11050
11051 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
11052 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
11053 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
11054 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
11055 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
11056 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
11057
11058 MIPS_FP_CONDITIONS (CMP_BUILTINS)
11059 };
11060
11061 /* Builtin functions for the SB-1 processor. */
11062
11063 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
11064
11065 static const struct builtin_description sb1_bdesc[] =
11066 {
11067 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
11068 };
11069
11070 /* Builtin functions for DSP ASE. */
11071
11072 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
11073 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
11074 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
11075 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
11076 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
11077
11078 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
11079 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
11080 builtin_description fields. */
11081 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
11082 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
11083 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
11084
11085 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
11086 branch instruction. TARGET_FLAGS is a builtin_description field. */
11087 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
11088 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
11089 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
11090
11091 static const struct builtin_description dsp_bdesc[] =
11092 {
11093 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11094 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11095 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11096 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
11097 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
11098 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11099 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11100 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11101 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
11102 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
11103 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11104 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11105 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11106 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
11107 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
11108 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
11109 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
11110 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
11111 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
11112 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
11113 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
11114 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
11115 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11116 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11117 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11118 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11119 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11120 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11121 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11122 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11123 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
11124 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
11125 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
11126 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11127 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
11128 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
11129 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
11130 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11131 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
11132 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
11133 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11134 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
11135 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
11136 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
11137 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11138 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
11139 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
11140 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
11141 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
11142 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
11143 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
11144 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
11145 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
11146 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
11147 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
11148 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
11149 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
11150 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11151 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11152 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
11153 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
11154 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
11155 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
11156 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
11157 BPOSGE_BUILTIN (32, MASK_DSP),
11158
11159 /* The following are for the MIPS DSP ASE REV 2. */
11160 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, MASK_DSPR2),
11161 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11162 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11163 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11164 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11165 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
11166 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
11167 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11168 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11169 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11170 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11171 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11172 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
11173 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11174 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
11175 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11176 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
11177 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
11178 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
11179 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
11180 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
11181 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSPR2),
11182 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11183 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11184 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11185 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11186 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11187 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11188 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
11189 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
11190 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11191 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11192 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
11193 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2)
11194 };
11195
11196 static const struct builtin_description dsp_32only_bdesc[] =
11197 {
11198 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
11199 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
11200 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
11201 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
11202 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11203 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11204 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11205 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
11206 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
11207 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11208 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11209 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11210 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11211 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11212 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11213 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11214 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11215 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11216 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11217 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
11218 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
11219
11220 /* The following are for the MIPS DSP ASE REV 2. */
11221 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11222 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11223 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
11224 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
11225 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
11226 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
11227 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11228 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, MASK_DSPR2),
11229 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, MASK_DSPR2),
11230 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11231 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11232 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11233 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11234 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11235 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2)
11236 };
11237
11238 /* This helps provide a mapping from builtin function codes to bdesc
11239 arrays. */
11240
11241 struct bdesc_map
11242 {
11243 /* The builtin function table that this entry describes. */
11244 const struct builtin_description *bdesc;
11245
11246 /* The number of entries in the builtin function table. */
11247 unsigned int size;
11248
11249 /* The target processor that supports these builtin functions.
11250 PROCESSOR_MAX means we enable them for all processors. */
11251 enum processor_type proc;
11252
11253 /* If the target has these flags, this builtin function table
11254 will not be supported. */
11255 int unsupported_target_flags;
11256 };
11257
11258 static const struct bdesc_map bdesc_arrays[] =
11259 {
11260 { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX, 0 },
11261 { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1, 0 },
11262 { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX, 0 },
11263 { dsp_32only_bdesc, ARRAY_SIZE (dsp_32only_bdesc), PROCESSOR_MAX,
11264 MASK_64BIT }
11265 };
11266
11267 /* Take the argument ARGNUM of the arglist of EXP and convert it into a form
11268 suitable for input operand OP of instruction ICODE. Return the value. */
11269
11270 static rtx
11271 mips_prepare_builtin_arg (enum insn_code icode,
11272 unsigned int op, tree exp, unsigned int argnum)
11273 {
11274 rtx value;
11275 enum machine_mode mode;
11276
11277 value = expand_normal (CALL_EXPR_ARG (exp, argnum));
11278 mode = insn_data[icode].operand[op].mode;
11279 if (!insn_data[icode].operand[op].predicate (value, mode))
11280 {
11281 value = copy_to_mode_reg (mode, value);
11282 /* Check the predicate again. */
11283 if (!insn_data[icode].operand[op].predicate (value, mode))
11284 {
11285 error ("invalid argument to builtin function");
11286 return const0_rtx;
11287 }
11288 }
11289
11290 return value;
11291 }
11292
11293 /* Return an rtx suitable for output operand OP of instruction ICODE.
11294 If TARGET is non-null, try to use it where possible. */
11295
11296 static rtx
11297 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
11298 {
11299 enum machine_mode mode;
11300
11301 mode = insn_data[icode].operand[op].mode;
11302 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
11303 target = gen_reg_rtx (mode);
11304
11305 return target;
11306 }
11307
11308 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
11309
11310 rtx
11311 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11312 enum machine_mode mode ATTRIBUTE_UNUSED,
11313 int ignore ATTRIBUTE_UNUSED)
11314 {
11315 enum insn_code icode;
11316 enum mips_builtin_type type;
11317 tree fndecl;
11318 unsigned int fcode;
11319 const struct builtin_description *bdesc;
11320 const struct bdesc_map *m;
11321
11322 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11323 fcode = DECL_FUNCTION_CODE (fndecl);
11324
11325 bdesc = NULL;
11326 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
11327 {
11328 if (fcode < m->size)
11329 {
11330 bdesc = m->bdesc;
11331 icode = bdesc[fcode].icode;
11332 type = bdesc[fcode].builtin_type;
11333 break;
11334 }
11335 fcode -= m->size;
11336 }
11337 if (bdesc == NULL)
11338 return 0;
11339
11340 switch (type)
11341 {
11342 case MIPS_BUILTIN_DIRECT:
11343 return mips_expand_builtin_direct (icode, target, exp, true);
11344
11345 case MIPS_BUILTIN_DIRECT_NO_TARGET:
11346 return mips_expand_builtin_direct (icode, target, exp, false);
11347
11348 case MIPS_BUILTIN_MOVT:
11349 case MIPS_BUILTIN_MOVF:
11350 return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
11351 target, exp);
11352
11353 case MIPS_BUILTIN_CMP_ANY:
11354 case MIPS_BUILTIN_CMP_ALL:
11355 case MIPS_BUILTIN_CMP_UPPER:
11356 case MIPS_BUILTIN_CMP_LOWER:
11357 case MIPS_BUILTIN_CMP_SINGLE:
11358 return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
11359 target, exp);
11360
11361 case MIPS_BUILTIN_BPOSGE32:
11362 return mips_expand_builtin_bposge (type, target);
11363
11364 default:
11365 return 0;
11366 }
11367 }
11368
11369 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
11370
11371 void
11372 mips_init_builtins (void)
11373 {
11374 const struct builtin_description *d;
11375 const struct bdesc_map *m;
11376 tree types[(int) MIPS_MAX_FTYPE_MAX];
11377 tree V2SF_type_node;
11378 tree V2HI_type_node;
11379 tree V4QI_type_node;
11380 unsigned int offset;
11381
11382 /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */
11383 if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP)
11384 return;
11385
11386 if (TARGET_PAIRED_SINGLE_FLOAT)
11387 {
11388 V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
11389
11390 types[MIPS_V2SF_FTYPE_V2SF]
11391 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
11392
11393 types[MIPS_V2SF_FTYPE_V2SF_V2SF]
11394 = build_function_type_list (V2SF_type_node,
11395 V2SF_type_node, V2SF_type_node, NULL_TREE);
11396
11397 types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT]
11398 = build_function_type_list (V2SF_type_node,
11399 V2SF_type_node, V2SF_type_node,
11400 integer_type_node, NULL_TREE);
11401
11402 types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF]
11403 = build_function_type_list (V2SF_type_node,
11404 V2SF_type_node, V2SF_type_node,
11405 V2SF_type_node, V2SF_type_node, NULL_TREE);
11406
11407 types[MIPS_V2SF_FTYPE_SF_SF]
11408 = build_function_type_list (V2SF_type_node,
11409 float_type_node, float_type_node, NULL_TREE);
11410
11411 types[MIPS_INT_FTYPE_V2SF_V2SF]
11412 = build_function_type_list (integer_type_node,
11413 V2SF_type_node, V2SF_type_node, NULL_TREE);
11414
11415 types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF]
11416 = build_function_type_list (integer_type_node,
11417 V2SF_type_node, V2SF_type_node,
11418 V2SF_type_node, V2SF_type_node, NULL_TREE);
11419
11420 types[MIPS_INT_FTYPE_SF_SF]
11421 = build_function_type_list (integer_type_node,
11422 float_type_node, float_type_node, NULL_TREE);
11423
11424 types[MIPS_INT_FTYPE_DF_DF]
11425 = build_function_type_list (integer_type_node,
11426 double_type_node, double_type_node, NULL_TREE);
11427
11428 types[MIPS_SF_FTYPE_V2SF]
11429 = build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE);
11430
11431 types[MIPS_SF_FTYPE_SF]
11432 = build_function_type_list (float_type_node,
11433 float_type_node, NULL_TREE);
11434
11435 types[MIPS_SF_FTYPE_SF_SF]
11436 = build_function_type_list (float_type_node,
11437 float_type_node, float_type_node, NULL_TREE);
11438
11439 types[MIPS_DF_FTYPE_DF]
11440 = build_function_type_list (double_type_node,
11441 double_type_node, NULL_TREE);
11442
11443 types[MIPS_DF_FTYPE_DF_DF]
11444 = build_function_type_list (double_type_node,
11445 double_type_node, double_type_node, NULL_TREE);
11446 }
11447
11448 if (TARGET_DSP)
11449 {
11450 V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
11451 V4QI_type_node = build_vector_type_for_mode (intQI_type_node, V4QImode);
11452
11453 types[MIPS_V2HI_FTYPE_V2HI_V2HI]
11454 = build_function_type_list (V2HI_type_node,
11455 V2HI_type_node, V2HI_type_node,
11456 NULL_TREE);
11457
11458 types[MIPS_SI_FTYPE_SI_SI]
11459 = build_function_type_list (intSI_type_node,
11460 intSI_type_node, intSI_type_node,
11461 NULL_TREE);
11462
11463 types[MIPS_V4QI_FTYPE_V4QI_V4QI]
11464 = build_function_type_list (V4QI_type_node,
11465 V4QI_type_node, V4QI_type_node,
11466 NULL_TREE);
11467
11468 types[MIPS_SI_FTYPE_V4QI]
11469 = build_function_type_list (intSI_type_node,
11470 V4QI_type_node,
11471 NULL_TREE);
11472
11473 types[MIPS_V2HI_FTYPE_V2HI]
11474 = build_function_type_list (V2HI_type_node,
11475 V2HI_type_node,
11476 NULL_TREE);
11477
11478 types[MIPS_SI_FTYPE_SI]
11479 = build_function_type_list (intSI_type_node,
11480 intSI_type_node,
11481 NULL_TREE);
11482
11483 types[MIPS_V4QI_FTYPE_V2HI_V2HI]
11484 = build_function_type_list (V4QI_type_node,
11485 V2HI_type_node, V2HI_type_node,
11486 NULL_TREE);
11487
11488 types[MIPS_V2HI_FTYPE_SI_SI]
11489 = build_function_type_list (V2HI_type_node,
11490 intSI_type_node, intSI_type_node,
11491 NULL_TREE);
11492
11493 types[MIPS_SI_FTYPE_V2HI]
11494 = build_function_type_list (intSI_type_node,
11495 V2HI_type_node,
11496 NULL_TREE);
11497
11498 types[MIPS_V2HI_FTYPE_V4QI]
11499 = build_function_type_list (V2HI_type_node,
11500 V4QI_type_node,
11501 NULL_TREE);
11502
11503 types[MIPS_V4QI_FTYPE_V4QI_SI]
11504 = build_function_type_list (V4QI_type_node,
11505 V4QI_type_node, intSI_type_node,
11506 NULL_TREE);
11507
11508 types[MIPS_V2HI_FTYPE_V2HI_SI]
11509 = build_function_type_list (V2HI_type_node,
11510 V2HI_type_node, intSI_type_node,
11511 NULL_TREE);
11512
11513 types[MIPS_V2HI_FTYPE_V4QI_V2HI]
11514 = build_function_type_list (V2HI_type_node,
11515 V4QI_type_node, V2HI_type_node,
11516 NULL_TREE);
11517
11518 types[MIPS_SI_FTYPE_V2HI_V2HI]
11519 = build_function_type_list (intSI_type_node,
11520 V2HI_type_node, V2HI_type_node,
11521 NULL_TREE);
11522
11523 types[MIPS_DI_FTYPE_DI_V4QI_V4QI]
11524 = build_function_type_list (intDI_type_node,
11525 intDI_type_node, V4QI_type_node, V4QI_type_node,
11526 NULL_TREE);
11527
11528 types[MIPS_DI_FTYPE_DI_V2HI_V2HI]
11529 = build_function_type_list (intDI_type_node,
11530 intDI_type_node, V2HI_type_node, V2HI_type_node,
11531 NULL_TREE);
11532
11533 types[MIPS_DI_FTYPE_DI_SI_SI]
11534 = build_function_type_list (intDI_type_node,
11535 intDI_type_node, intSI_type_node, intSI_type_node,
11536 NULL_TREE);
11537
11538 types[MIPS_V4QI_FTYPE_SI]
11539 = build_function_type_list (V4QI_type_node,
11540 intSI_type_node,
11541 NULL_TREE);
11542
11543 types[MIPS_V2HI_FTYPE_SI]
11544 = build_function_type_list (V2HI_type_node,
11545 intSI_type_node,
11546 NULL_TREE);
11547
11548 types[MIPS_VOID_FTYPE_V4QI_V4QI]
11549 = build_function_type_list (void_type_node,
11550 V4QI_type_node, V4QI_type_node,
11551 NULL_TREE);
11552
11553 types[MIPS_SI_FTYPE_V4QI_V4QI]
11554 = build_function_type_list (intSI_type_node,
11555 V4QI_type_node, V4QI_type_node,
11556 NULL_TREE);
11557
11558 types[MIPS_VOID_FTYPE_V2HI_V2HI]
11559 = build_function_type_list (void_type_node,
11560 V2HI_type_node, V2HI_type_node,
11561 NULL_TREE);
11562
11563 types[MIPS_SI_FTYPE_DI_SI]
11564 = build_function_type_list (intSI_type_node,
11565 intDI_type_node, intSI_type_node,
11566 NULL_TREE);
11567
11568 types[MIPS_DI_FTYPE_DI_SI]
11569 = build_function_type_list (intDI_type_node,
11570 intDI_type_node, intSI_type_node,
11571 NULL_TREE);
11572
11573 types[MIPS_VOID_FTYPE_SI_SI]
11574 = build_function_type_list (void_type_node,
11575 intSI_type_node, intSI_type_node,
11576 NULL_TREE);
11577
11578 types[MIPS_SI_FTYPE_PTR_SI]
11579 = build_function_type_list (intSI_type_node,
11580 ptr_type_node, intSI_type_node,
11581 NULL_TREE);
11582
11583 types[MIPS_SI_FTYPE_VOID]
11584 = build_function_type (intSI_type_node, void_list_node);
11585
11586 if (TARGET_DSPR2)
11587 {
11588 types[MIPS_V4QI_FTYPE_V4QI]
11589 = build_function_type_list (V4QI_type_node,
11590 V4QI_type_node,
11591 NULL_TREE);
11592
11593 types[MIPS_SI_FTYPE_SI_SI_SI]
11594 = build_function_type_list (intSI_type_node,
11595 intSI_type_node, intSI_type_node,
11596 intSI_type_node, NULL_TREE);
11597
11598 types[MIPS_DI_FTYPE_DI_USI_USI]
11599 = build_function_type_list (intDI_type_node,
11600 intDI_type_node,
11601 unsigned_intSI_type_node,
11602 unsigned_intSI_type_node, NULL_TREE);
11603
11604 types[MIPS_DI_FTYPE_SI_SI]
11605 = build_function_type_list (intDI_type_node,
11606 intSI_type_node, intSI_type_node,
11607 NULL_TREE);
11608
11609 types[MIPS_DI_FTYPE_USI_USI]
11610 = build_function_type_list (intDI_type_node,
11611 unsigned_intSI_type_node,
11612 unsigned_intSI_type_node, NULL_TREE);
11613
11614 types[MIPS_V2HI_FTYPE_SI_SI_SI]
11615 = build_function_type_list (V2HI_type_node,
11616 intSI_type_node, intSI_type_node,
11617 intSI_type_node, NULL_TREE);
11618
11619 }
11620 }
11621
11622 /* Iterate through all of the bdesc arrays, initializing all of the
11623 builtin functions. */
11624
11625 offset = 0;
11626 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
11627 {
11628 if ((m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
11629 && (m->unsupported_target_flags & target_flags) == 0)
11630 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
11631 if ((d->target_flags & target_flags) == d->target_flags)
11632 add_builtin_function (d->name, types[d->function_type],
11633 d - m->bdesc + offset,
11634 BUILT_IN_MD, NULL, NULL);
11635 offset += m->size;
11636 }
11637 }
11638
11639 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
11640 .md pattern and CALL is the function expr with arguments. TARGET,
11641 if nonnull, suggests a good place to put the result.
11642 HAS_TARGET indicates the function must return something. */
11643
11644 static rtx
11645 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
11646 bool has_target)
11647 {
11648 rtx ops[MAX_RECOG_OPERANDS];
11649 int i = 0;
11650 int j = 0;
11651
11652 if (has_target)
11653 {
11654 /* We save target to ops[0]. */
11655 ops[0] = mips_prepare_builtin_target (icode, 0, target);
11656 i = 1;
11657 }
11658
11659 /* We need to test if the arglist is not zero. Some instructions have extra
11660 clobber registers. */
11661 for (; i < insn_data[icode].n_operands && i <= call_expr_nargs (exp); i++, j++)
11662 ops[i] = mips_prepare_builtin_arg (icode, i, exp, j);
11663
11664 switch (i)
11665 {
11666 case 2:
11667 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
11668 break;
11669
11670 case 3:
11671 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
11672 break;
11673
11674 case 4:
11675 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
11676 break;
11677
11678 default:
11679 gcc_unreachable ();
11680 }
11681 return target;
11682 }
11683
11684 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
11685 function (TYPE says which). EXP is the tree for the function
11686 function, ICODE is the instruction that should be used to compare
11687 the first two arguments, and COND is the condition it should test.
11688 TARGET, if nonnull, suggests a good place to put the result. */
11689
11690 static rtx
11691 mips_expand_builtin_movtf (enum mips_builtin_type type,
11692 enum insn_code icode, enum mips_fp_condition cond,
11693 rtx target, tree exp)
11694 {
11695 rtx cmp_result, op0, op1;
11696
11697 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
11698 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
11699 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
11700 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
11701
11702 icode = CODE_FOR_mips_cond_move_tf_ps;
11703 target = mips_prepare_builtin_target (icode, 0, target);
11704 if (type == MIPS_BUILTIN_MOVT)
11705 {
11706 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
11707 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
11708 }
11709 else
11710 {
11711 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
11712 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
11713 }
11714 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
11715 return target;
11716 }
11717
11718 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
11719 into TARGET otherwise. Return TARGET. */
11720
11721 static rtx
11722 mips_builtin_branch_and_move (rtx condition, rtx target,
11723 rtx value_if_true, rtx value_if_false)
11724 {
11725 rtx true_label, done_label;
11726
11727 true_label = gen_label_rtx ();
11728 done_label = gen_label_rtx ();
11729
11730 /* First assume that CONDITION is false. */
11731 emit_move_insn (target, value_if_false);
11732
11733 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
11734 emit_jump_insn (gen_condjump (condition, true_label));
11735 emit_jump_insn (gen_jump (done_label));
11736 emit_barrier ();
11737
11738 /* Fix TARGET if CONDITION is true. */
11739 emit_label (true_label);
11740 emit_move_insn (target, value_if_true);
11741
11742 emit_label (done_label);
11743 return target;
11744 }
11745
11746 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
11747 of the comparison instruction and COND is the condition it should test.
11748 EXP is the function call and arguments and TARGET, if nonnull,
11749 suggests a good place to put the boolean result. */
11750
11751 static rtx
11752 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
11753 enum insn_code icode, enum mips_fp_condition cond,
11754 rtx target, tree exp)
11755 {
11756 rtx offset, condition, cmp_result, ops[MAX_RECOG_OPERANDS];
11757 int i;
11758 int j = 0;
11759
11760 if (target == 0 || GET_MODE (target) != SImode)
11761 target = gen_reg_rtx (SImode);
11762
11763 /* Prepare the operands to the comparison. */
11764 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
11765 for (i = 1; i < insn_data[icode].n_operands - 1; i++, j++)
11766 ops[i] = mips_prepare_builtin_arg (icode, i, exp, j);
11767
11768 switch (insn_data[icode].n_operands)
11769 {
11770 case 4:
11771 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond)));
11772 break;
11773
11774 case 6:
11775 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2],
11776 ops[3], ops[4], GEN_INT (cond)));
11777 break;
11778
11779 default:
11780 gcc_unreachable ();
11781 }
11782
11783 /* If the comparison sets more than one register, we define the result
11784 to be 0 if all registers are false and -1 if all registers are true.
11785 The value of the complete result is indeterminate otherwise. */
11786 switch (builtin_type)
11787 {
11788 case MIPS_BUILTIN_CMP_ALL:
11789 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
11790 return mips_builtin_branch_and_move (condition, target,
11791 const0_rtx, const1_rtx);
11792
11793 case MIPS_BUILTIN_CMP_UPPER:
11794 case MIPS_BUILTIN_CMP_LOWER:
11795 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
11796 condition = gen_single_cc (cmp_result, offset);
11797 return mips_builtin_branch_and_move (condition, target,
11798 const1_rtx, const0_rtx);
11799
11800 default:
11801 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
11802 return mips_builtin_branch_and_move (condition, target,
11803 const1_rtx, const0_rtx);
11804 }
11805 }
11806
11807 /* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
11808 suggests a good place to put the boolean result. */
11809
11810 static rtx
11811 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
11812 {
11813 rtx condition, cmp_result;
11814 int cmp_value;
11815
11816 if (target == 0 || GET_MODE (target) != SImode)
11817 target = gen_reg_rtx (SImode);
11818
11819 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
11820
11821 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
11822 cmp_value = 32;
11823 else
11824 gcc_assert (0);
11825
11826 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
11827 return mips_builtin_branch_and_move (condition, target,
11828 const1_rtx, const0_rtx);
11829 }
11830 \f
11831 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
11832 FIRST is true if this is the first time handling this decl. */
11833
11834 static void
11835 mips_encode_section_info (tree decl, rtx rtl, int first)
11836 {
11837 default_encode_section_info (decl, rtl, first);
11838
11839 if (TREE_CODE (decl) == FUNCTION_DECL)
11840 {
11841 rtx symbol = XEXP (rtl, 0);
11842
11843 if ((TARGET_LONG_CALLS && !mips_near_type_p (TREE_TYPE (decl)))
11844 || mips_far_type_p (TREE_TYPE (decl)))
11845 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
11846 }
11847 }
11848
11849 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. Some code models use the incoming
11850 value of PIC_FUNCTION_ADDR_REGNUM to set up the global pointer. */
11851
11852 static void
11853 mips_extra_live_on_entry (bitmap regs)
11854 {
11855 if (TARGET_USE_GOT && !TARGET_ABSOLUTE_ABICALLS)
11856 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
11857 }
11858
11859 /* SImode values are represented as sign-extended to DImode. */
11860
11861 int
11862 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
11863 {
11864 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
11865 return SIGN_EXTEND;
11866
11867 return UNKNOWN;
11868 }
11869 \f
11870 /* MIPS implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
11871
11872 static void
11873 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
11874 {
11875 switch (size)
11876 {
11877 case 4:
11878 fputs ("\t.dtprelword\t", file);
11879 break;
11880
11881 case 8:
11882 fputs ("\t.dtpreldword\t", file);
11883 break;
11884
11885 default:
11886 gcc_unreachable ();
11887 }
11888 output_addr_const (file, x);
11889 fputs ("+0x8000", file);
11890 }
11891 \f
11892 #include "gt-mips.h"
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