1 /* Expand the basic unary and binary arithmetic operations, for GNU compiler.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
25 #include "diagnostic-core.h"
27 /* Include insn-config.h before expr.h so that HAVE_conditional_move
28 is properly defined. */
29 #include "insn-config.h"
32 #include "stor-layout.h"
33 #include "stringpool.h"
45 #include "basic-block.h"
48 struct target_optabs default_target_optabs
;
49 struct target_libfuncs default_target_libfuncs
;
50 struct target_optabs
*this_fn_optabs
= &default_target_optabs
;
52 struct target_optabs
*this_target_optabs
= &default_target_optabs
;
53 struct target_libfuncs
*this_target_libfuncs
= &default_target_libfuncs
;
56 #define libfunc_hash \
57 (this_target_libfuncs->x_libfunc_hash)
59 static void prepare_float_lib_cmp (rtx
, rtx
, enum rtx_code
, rtx
*,
61 static rtx
expand_unop_direct (enum machine_mode
, optab
, rtx
, rtx
, int);
62 static void emit_libcall_block_1 (rtx
, rtx
, rtx
, rtx
, bool);
64 /* Debug facility for use in GDB. */
65 void debug_optab_libfuncs (void);
67 /* Prefixes for the current version of decimal floating point (BID vs. DPD) */
68 #if ENABLE_DECIMAL_BID_FORMAT
69 #define DECIMAL_PREFIX "bid_"
71 #define DECIMAL_PREFIX "dpd_"
74 /* Used for libfunc_hash. */
77 hash_libfunc (const void *p
)
79 const struct libfunc_entry
*const e
= (const struct libfunc_entry
*) p
;
80 return ((e
->mode1
+ e
->mode2
* NUM_MACHINE_MODES
) ^ e
->op
);
83 /* Used for libfunc_hash. */
86 eq_libfunc (const void *p
, const void *q
)
88 const struct libfunc_entry
*const e1
= (const struct libfunc_entry
*) p
;
89 const struct libfunc_entry
*const e2
= (const struct libfunc_entry
*) q
;
90 return e1
->op
== e2
->op
&& e1
->mode1
== e2
->mode1
&& e1
->mode2
== e2
->mode2
;
93 /* Return libfunc corresponding operation defined by OPTAB converting
94 from MODE2 to MODE1. Trigger lazy initialization if needed, return NULL
95 if no libfunc is available. */
97 convert_optab_libfunc (convert_optab optab
, enum machine_mode mode1
,
98 enum machine_mode mode2
)
100 struct libfunc_entry e
;
101 struct libfunc_entry
**slot
;
103 /* ??? This ought to be an assert, but not all of the places
104 that we expand optabs know about the optabs that got moved
106 if (!(optab
>= FIRST_CONV_OPTAB
&& optab
<= LAST_CONVLIB_OPTAB
))
112 slot
= (struct libfunc_entry
**)
113 htab_find_slot (libfunc_hash
, &e
, NO_INSERT
);
116 const struct convert_optab_libcall_d
*d
117 = &convlib_def
[optab
- FIRST_CONV_OPTAB
];
119 if (d
->libcall_gen
== NULL
)
122 d
->libcall_gen (optab
, d
->libcall_basename
, mode1
, mode2
);
123 slot
= (struct libfunc_entry
**)
124 htab_find_slot (libfunc_hash
, &e
, NO_INSERT
);
128 return (*slot
)->libfunc
;
131 /* Return libfunc corresponding operation defined by OPTAB in MODE.
132 Trigger lazy initialization if needed, return NULL if no libfunc is
135 optab_libfunc (optab optab
, enum machine_mode mode
)
137 struct libfunc_entry e
;
138 struct libfunc_entry
**slot
;
140 /* ??? This ought to be an assert, but not all of the places
141 that we expand optabs know about the optabs that got moved
143 if (!(optab
>= FIRST_NORM_OPTAB
&& optab
<= LAST_NORMLIB_OPTAB
))
149 slot
= (struct libfunc_entry
**)
150 htab_find_slot (libfunc_hash
, &e
, NO_INSERT
);
153 const struct optab_libcall_d
*d
154 = &normlib_def
[optab
- FIRST_NORM_OPTAB
];
156 if (d
->libcall_gen
== NULL
)
159 d
->libcall_gen (optab
, d
->libcall_basename
, d
->libcall_suffix
, mode
);
160 slot
= (struct libfunc_entry
**)
161 htab_find_slot (libfunc_hash
, &e
, NO_INSERT
);
165 return (*slot
)->libfunc
;
169 /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to
170 the result of operation CODE applied to OP0 (and OP1 if it is a binary
173 If the last insn does not set TARGET, don't do anything, but return 1.
175 If the last insn or a previous insn sets TARGET and TARGET is one of OP0
176 or OP1, don't add the REG_EQUAL note but return 0. Our caller can then
177 try again, ensuring that TARGET is not one of the operands. */
180 add_equal_note (rtx insns
, rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
185 gcc_assert (insns
&& INSN_P (insns
) && NEXT_INSN (insns
));
187 if (GET_RTX_CLASS (code
) != RTX_COMM_ARITH
188 && GET_RTX_CLASS (code
) != RTX_BIN_ARITH
189 && GET_RTX_CLASS (code
) != RTX_COMM_COMPARE
190 && GET_RTX_CLASS (code
) != RTX_COMPARE
191 && GET_RTX_CLASS (code
) != RTX_UNARY
)
194 if (GET_CODE (target
) == ZERO_EXTRACT
)
197 for (last_insn
= insns
;
198 NEXT_INSN (last_insn
) != NULL_RTX
;
199 last_insn
= NEXT_INSN (last_insn
))
202 /* If TARGET is in OP0 or OP1, punt. We'd end up with a note referencing
203 a value changing in the insn, so the note would be invalid for CSE. */
204 if (reg_overlap_mentioned_p (target
, op0
)
205 || (op1
&& reg_overlap_mentioned_p (target
, op1
)))
208 && (rtx_equal_p (target
, op0
)
209 || (op1
&& rtx_equal_p (target
, op1
))))
211 /* For MEM target, with MEM = MEM op X, prefer no REG_EQUAL note
212 over expanding it as temp = MEM op X, MEM = temp. If the target
213 supports MEM = MEM op X instructions, it is sometimes too hard
214 to reconstruct that form later, especially if X is also a memory,
215 and due to multiple occurrences of addresses the address might
216 be forced into register unnecessarily.
217 Note that not emitting the REG_EQUIV note might inhibit
218 CSE in some cases. */
219 set
= single_set (last_insn
);
221 && GET_CODE (SET_SRC (set
)) == code
222 && MEM_P (SET_DEST (set
))
223 && (rtx_equal_p (SET_DEST (set
), XEXP (SET_SRC (set
), 0))
224 || (op1
&& rtx_equal_p (SET_DEST (set
),
225 XEXP (SET_SRC (set
), 1)))))
231 set
= single_set (last_insn
);
235 if (! rtx_equal_p (SET_DEST (set
), target
)
236 /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */
237 && (GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
238 || ! rtx_equal_p (XEXP (SET_DEST (set
), 0), target
)))
241 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
251 if (GET_MODE (op0
) != VOIDmode
&& GET_MODE (target
) != GET_MODE (op0
))
253 note
= gen_rtx_fmt_e (code
, GET_MODE (op0
), copy_rtx (op0
));
254 if (GET_MODE_SIZE (GET_MODE (op0
))
255 > GET_MODE_SIZE (GET_MODE (target
)))
256 note
= simplify_gen_unary (TRUNCATE
, GET_MODE (target
),
257 note
, GET_MODE (op0
));
259 note
= simplify_gen_unary (ZERO_EXTEND
, GET_MODE (target
),
260 note
, GET_MODE (op0
));
265 note
= gen_rtx_fmt_e (code
, GET_MODE (target
), copy_rtx (op0
));
269 note
= gen_rtx_fmt_ee (code
, GET_MODE (target
), copy_rtx (op0
), copy_rtx (op1
));
271 set_unique_reg_note (last_insn
, REG_EQUAL
, note
);
276 /* Given two input operands, OP0 and OP1, determine what the correct from_mode
277 for a widening operation would be. In most cases this would be OP0, but if
278 that's a constant it'll be VOIDmode, which isn't useful. */
280 static enum machine_mode
281 widened_mode (enum machine_mode to_mode
, rtx op0
, rtx op1
)
283 enum machine_mode m0
= GET_MODE (op0
);
284 enum machine_mode m1
= GET_MODE (op1
);
285 enum machine_mode result
;
287 if (m0
== VOIDmode
&& m1
== VOIDmode
)
289 else if (m0
== VOIDmode
|| GET_MODE_SIZE (m0
) < GET_MODE_SIZE (m1
))
294 if (GET_MODE_SIZE (result
) > GET_MODE_SIZE (to_mode
))
300 /* Find a widening optab even if it doesn't widen as much as we want.
301 E.g. if from_mode is HImode, and to_mode is DImode, and there is no
302 direct HI->SI insn, then return SI->DI, if that exists.
303 If PERMIT_NON_WIDENING is non-zero then this can be used with
304 non-widening optabs also. */
307 find_widening_optab_handler_and_mode (optab op
, enum machine_mode to_mode
,
308 enum machine_mode from_mode
,
309 int permit_non_widening
,
310 enum machine_mode
*found_mode
)
312 for (; (permit_non_widening
|| from_mode
!= to_mode
)
313 && GET_MODE_SIZE (from_mode
) <= GET_MODE_SIZE (to_mode
)
314 && from_mode
!= VOIDmode
;
315 from_mode
= GET_MODE_WIDER_MODE (from_mode
))
317 enum insn_code handler
= widening_optab_handler (op
, to_mode
,
320 if (handler
!= CODE_FOR_nothing
)
323 *found_mode
= from_mode
;
328 return CODE_FOR_nothing
;
331 /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP
332 says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need
333 not actually do a sign-extend or zero-extend, but can leave the
334 higher-order bits of the result rtx undefined, for example, in the case
335 of logical operations, but not right shifts. */
338 widen_operand (rtx op
, enum machine_mode mode
, enum machine_mode oldmode
,
339 int unsignedp
, int no_extend
)
343 /* If we don't have to extend and this is a constant, return it. */
344 if (no_extend
&& GET_MODE (op
) == VOIDmode
)
347 /* If we must extend do so. If OP is a SUBREG for a promoted object, also
348 extend since it will be more efficient to do so unless the signedness of
349 a promoted object differs from our extension. */
351 || (GET_CODE (op
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (op
)
352 && SUBREG_PROMOTED_UNSIGNED_P (op
) == unsignedp
))
353 return convert_modes (mode
, oldmode
, op
, unsignedp
);
355 /* If MODE is no wider than a single word, we return a lowpart or paradoxical
357 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
358 return gen_lowpart (mode
, force_reg (GET_MODE (op
), op
));
360 /* Otherwise, get an object of MODE, clobber it, and set the low-order
363 result
= gen_reg_rtx (mode
);
364 emit_clobber (result
);
365 emit_move_insn (gen_lowpart (GET_MODE (op
), result
), op
);
369 /* Return the optab used for computing the operation given by the tree code,
370 CODE and the tree EXP. This function is not always usable (for example, it
371 cannot give complete results for multiplication or division) but probably
372 ought to be relied on more widely throughout the expander. */
374 optab_for_tree_code (enum tree_code code
, const_tree type
,
375 enum optab_subtype subtype
)
387 return one_cmpl_optab
;
392 case MULT_HIGHPART_EXPR
:
393 return TYPE_UNSIGNED (type
) ? umul_highpart_optab
: smul_highpart_optab
;
399 return TYPE_UNSIGNED (type
) ? umod_optab
: smod_optab
;
407 if (TYPE_SATURATING (type
))
408 return TYPE_UNSIGNED (type
) ? usdiv_optab
: ssdiv_optab
;
409 return TYPE_UNSIGNED (type
) ? udiv_optab
: sdiv_optab
;
412 if (TREE_CODE (type
) == VECTOR_TYPE
)
414 if (subtype
== optab_vector
)
415 return TYPE_SATURATING (type
) ? unknown_optab
: vashl_optab
;
417 gcc_assert (subtype
== optab_scalar
);
419 if (TYPE_SATURATING (type
))
420 return TYPE_UNSIGNED (type
) ? usashl_optab
: ssashl_optab
;
424 if (TREE_CODE (type
) == VECTOR_TYPE
)
426 if (subtype
== optab_vector
)
427 return TYPE_UNSIGNED (type
) ? vlshr_optab
: vashr_optab
;
429 gcc_assert (subtype
== optab_scalar
);
431 return TYPE_UNSIGNED (type
) ? lshr_optab
: ashr_optab
;
434 if (TREE_CODE (type
) == VECTOR_TYPE
)
436 if (subtype
== optab_vector
)
439 gcc_assert (subtype
== optab_scalar
);
444 if (TREE_CODE (type
) == VECTOR_TYPE
)
446 if (subtype
== optab_vector
)
449 gcc_assert (subtype
== optab_scalar
);
454 return TYPE_UNSIGNED (type
) ? umax_optab
: smax_optab
;
457 return TYPE_UNSIGNED (type
) ? umin_optab
: smin_optab
;
459 case REALIGN_LOAD_EXPR
:
460 return vec_realign_load_optab
;
463 return TYPE_UNSIGNED (type
) ? usum_widen_optab
: ssum_widen_optab
;
466 return TYPE_UNSIGNED (type
) ? udot_prod_optab
: sdot_prod_optab
;
468 case WIDEN_MULT_PLUS_EXPR
:
469 return (TYPE_UNSIGNED (type
)
470 ? (TYPE_SATURATING (type
)
471 ? usmadd_widen_optab
: umadd_widen_optab
)
472 : (TYPE_SATURATING (type
)
473 ? ssmadd_widen_optab
: smadd_widen_optab
));
475 case WIDEN_MULT_MINUS_EXPR
:
476 return (TYPE_UNSIGNED (type
)
477 ? (TYPE_SATURATING (type
)
478 ? usmsub_widen_optab
: umsub_widen_optab
)
479 : (TYPE_SATURATING (type
)
480 ? ssmsub_widen_optab
: smsub_widen_optab
));
486 return TYPE_UNSIGNED (type
) ? reduc_umax_optab
: reduc_smax_optab
;
489 return TYPE_UNSIGNED (type
) ? reduc_umin_optab
: reduc_smin_optab
;
491 case REDUC_PLUS_EXPR
:
492 return TYPE_UNSIGNED (type
) ? reduc_uplus_optab
: reduc_splus_optab
;
494 case VEC_LSHIFT_EXPR
:
495 return vec_shl_optab
;
497 case VEC_RSHIFT_EXPR
:
498 return vec_shr_optab
;
500 case VEC_WIDEN_MULT_HI_EXPR
:
501 return TYPE_UNSIGNED (type
) ?
502 vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
504 case VEC_WIDEN_MULT_LO_EXPR
:
505 return TYPE_UNSIGNED (type
) ?
506 vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
508 case VEC_WIDEN_MULT_EVEN_EXPR
:
509 return TYPE_UNSIGNED (type
) ?
510 vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
512 case VEC_WIDEN_MULT_ODD_EXPR
:
513 return TYPE_UNSIGNED (type
) ?
514 vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
516 case VEC_WIDEN_LSHIFT_HI_EXPR
:
517 return TYPE_UNSIGNED (type
) ?
518 vec_widen_ushiftl_hi_optab
: vec_widen_sshiftl_hi_optab
;
520 case VEC_WIDEN_LSHIFT_LO_EXPR
:
521 return TYPE_UNSIGNED (type
) ?
522 vec_widen_ushiftl_lo_optab
: vec_widen_sshiftl_lo_optab
;
524 case VEC_UNPACK_HI_EXPR
:
525 return TYPE_UNSIGNED (type
) ?
526 vec_unpacku_hi_optab
: vec_unpacks_hi_optab
;
528 case VEC_UNPACK_LO_EXPR
:
529 return TYPE_UNSIGNED (type
) ?
530 vec_unpacku_lo_optab
: vec_unpacks_lo_optab
;
532 case VEC_UNPACK_FLOAT_HI_EXPR
:
533 /* The signedness is determined from input operand. */
534 return TYPE_UNSIGNED (type
) ?
535 vec_unpacku_float_hi_optab
: vec_unpacks_float_hi_optab
;
537 case VEC_UNPACK_FLOAT_LO_EXPR
:
538 /* The signedness is determined from input operand. */
539 return TYPE_UNSIGNED (type
) ?
540 vec_unpacku_float_lo_optab
: vec_unpacks_float_lo_optab
;
542 case VEC_PACK_TRUNC_EXPR
:
543 return vec_pack_trunc_optab
;
545 case VEC_PACK_SAT_EXPR
:
546 return TYPE_UNSIGNED (type
) ? vec_pack_usat_optab
: vec_pack_ssat_optab
;
548 case VEC_PACK_FIX_TRUNC_EXPR
:
549 /* The signedness is determined from output operand. */
550 return TYPE_UNSIGNED (type
) ?
551 vec_pack_ufix_trunc_optab
: vec_pack_sfix_trunc_optab
;
557 trapv
= INTEGRAL_TYPE_P (type
) && TYPE_OVERFLOW_TRAPS (type
);
560 case POINTER_PLUS_EXPR
:
562 if (TYPE_SATURATING (type
))
563 return TYPE_UNSIGNED (type
) ? usadd_optab
: ssadd_optab
;
564 return trapv
? addv_optab
: add_optab
;
567 if (TYPE_SATURATING (type
))
568 return TYPE_UNSIGNED (type
) ? ussub_optab
: sssub_optab
;
569 return trapv
? subv_optab
: sub_optab
;
572 if (TYPE_SATURATING (type
))
573 return TYPE_UNSIGNED (type
) ? usmul_optab
: ssmul_optab
;
574 return trapv
? smulv_optab
: smul_optab
;
577 if (TYPE_SATURATING (type
))
578 return TYPE_UNSIGNED (type
) ? usneg_optab
: ssneg_optab
;
579 return trapv
? negv_optab
: neg_optab
;
582 return trapv
? absv_optab
: abs_optab
;
585 return unknown_optab
;
590 /* Expand vector widening operations.
592 There are two different classes of operations handled here:
593 1) Operations whose result is wider than all the arguments to the operation.
594 Examples: VEC_UNPACK_HI/LO_EXPR, VEC_WIDEN_MULT_HI/LO_EXPR
595 In this case OP0 and optionally OP1 would be initialized,
596 but WIDE_OP wouldn't (not relevant for this case).
597 2) Operations whose result is of the same size as the last argument to the
598 operation, but wider than all the other arguments to the operation.
599 Examples: WIDEN_SUM_EXPR, VEC_DOT_PROD_EXPR.
600 In the case WIDE_OP, OP0 and optionally OP1 would be initialized.
602 E.g, when called to expand the following operations, this is how
603 the arguments will be initialized:
605 widening-sum 2 oprnd0 - oprnd1
606 widening-dot-product 3 oprnd0 oprnd1 oprnd2
607 widening-mult 2 oprnd0 oprnd1 -
608 type-promotion (vec-unpack) 1 oprnd0 - - */
611 expand_widen_pattern_expr (sepops ops
, rtx op0
, rtx op1
, rtx wide_op
,
612 rtx target
, int unsignedp
)
614 struct expand_operand eops
[4];
615 tree oprnd0
, oprnd1
, oprnd2
;
616 enum machine_mode wmode
= VOIDmode
, tmode0
, tmode1
= VOIDmode
;
617 optab widen_pattern_optab
;
618 enum insn_code icode
;
619 int nops
= TREE_CODE_LENGTH (ops
->code
);
623 tmode0
= TYPE_MODE (TREE_TYPE (oprnd0
));
624 widen_pattern_optab
=
625 optab_for_tree_code (ops
->code
, TREE_TYPE (oprnd0
), optab_default
);
626 if (ops
->code
== WIDEN_MULT_PLUS_EXPR
627 || ops
->code
== WIDEN_MULT_MINUS_EXPR
)
628 icode
= find_widening_optab_handler (widen_pattern_optab
,
629 TYPE_MODE (TREE_TYPE (ops
->op2
)),
632 icode
= optab_handler (widen_pattern_optab
, tmode0
);
633 gcc_assert (icode
!= CODE_FOR_nothing
);
638 tmode1
= TYPE_MODE (TREE_TYPE (oprnd1
));
641 /* The last operand is of a wider mode than the rest of the operands. */
646 gcc_assert (tmode1
== tmode0
);
649 wmode
= TYPE_MODE (TREE_TYPE (oprnd2
));
653 create_output_operand (&eops
[op
++], target
, TYPE_MODE (ops
->type
));
654 create_convert_operand_from (&eops
[op
++], op0
, tmode0
, unsignedp
);
656 create_convert_operand_from (&eops
[op
++], op1
, tmode1
, unsignedp
);
658 create_convert_operand_from (&eops
[op
++], wide_op
, wmode
, unsignedp
);
659 expand_insn (icode
, op
, eops
);
660 return eops
[0].value
;
663 /* Generate code to perform an operation specified by TERNARY_OPTAB
664 on operands OP0, OP1 and OP2, with result having machine-mode MODE.
666 UNSIGNEDP is for the case where we have to widen the operands
667 to perform the operation. It says to use zero-extension.
669 If TARGET is nonzero, the value
670 is generated there, if it is convenient to do so.
671 In all cases an rtx is returned for the locus of the value;
672 this may or may not be TARGET. */
675 expand_ternary_op (enum machine_mode mode
, optab ternary_optab
, rtx op0
,
676 rtx op1
, rtx op2
, rtx target
, int unsignedp
)
678 struct expand_operand ops
[4];
679 enum insn_code icode
= optab_handler (ternary_optab
, mode
);
681 gcc_assert (optab_handler (ternary_optab
, mode
) != CODE_FOR_nothing
);
683 create_output_operand (&ops
[0], target
, mode
);
684 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
685 create_convert_operand_from (&ops
[2], op1
, mode
, unsignedp
);
686 create_convert_operand_from (&ops
[3], op2
, mode
, unsignedp
);
687 expand_insn (icode
, 4, ops
);
692 /* Like expand_binop, but return a constant rtx if the result can be
693 calculated at compile time. The arguments and return value are
694 otherwise the same as for expand_binop. */
697 simplify_expand_binop (enum machine_mode mode
, optab binoptab
,
698 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
699 enum optab_methods methods
)
701 if (CONSTANT_P (op0
) && CONSTANT_P (op1
))
703 rtx x
= simplify_binary_operation (optab_to_code (binoptab
),
709 return expand_binop (mode
, binoptab
, op0
, op1
, target
, unsignedp
, methods
);
712 /* Like simplify_expand_binop, but always put the result in TARGET.
713 Return true if the expansion succeeded. */
716 force_expand_binop (enum machine_mode mode
, optab binoptab
,
717 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
718 enum optab_methods methods
)
720 rtx x
= simplify_expand_binop (mode
, binoptab
, op0
, op1
,
721 target
, unsignedp
, methods
);
725 emit_move_insn (target
, x
);
729 /* Generate insns for VEC_LSHIFT_EXPR, VEC_RSHIFT_EXPR. */
732 expand_vec_shift_expr (sepops ops
, rtx target
)
734 struct expand_operand eops
[3];
735 enum insn_code icode
;
736 rtx rtx_op1
, rtx_op2
;
737 enum machine_mode mode
= TYPE_MODE (ops
->type
);
738 tree vec_oprnd
= ops
->op0
;
739 tree shift_oprnd
= ops
->op1
;
744 case VEC_RSHIFT_EXPR
:
745 shift_optab
= vec_shr_optab
;
747 case VEC_LSHIFT_EXPR
:
748 shift_optab
= vec_shl_optab
;
754 icode
= optab_handler (shift_optab
, mode
);
755 gcc_assert (icode
!= CODE_FOR_nothing
);
757 rtx_op1
= expand_normal (vec_oprnd
);
758 rtx_op2
= expand_normal (shift_oprnd
);
760 create_output_operand (&eops
[0], target
, mode
);
761 create_input_operand (&eops
[1], rtx_op1
, GET_MODE (rtx_op1
));
762 create_convert_operand_from_type (&eops
[2], rtx_op2
, TREE_TYPE (shift_oprnd
));
763 expand_insn (icode
, 3, eops
);
765 return eops
[0].value
;
768 /* Create a new vector value in VMODE with all elements set to OP. The
769 mode of OP must be the element mode of VMODE. If OP is a constant,
770 then the return value will be a constant. */
773 expand_vector_broadcast (enum machine_mode vmode
, rtx op
)
775 enum insn_code icode
;
780 gcc_checking_assert (VECTOR_MODE_P (vmode
));
782 n
= GET_MODE_NUNITS (vmode
);
783 vec
= rtvec_alloc (n
);
784 for (i
= 0; i
< n
; ++i
)
785 RTVEC_ELT (vec
, i
) = op
;
788 return gen_rtx_CONST_VECTOR (vmode
, vec
);
790 /* ??? If the target doesn't have a vec_init, then we have no easy way
791 of performing this operation. Most of this sort of generic support
792 is hidden away in the vector lowering support in gimple. */
793 icode
= optab_handler (vec_init_optab
, vmode
);
794 if (icode
== CODE_FOR_nothing
)
797 ret
= gen_reg_rtx (vmode
);
798 emit_insn (GEN_FCN (icode
) (ret
, gen_rtx_PARALLEL (vmode
, vec
)));
803 /* This subroutine of expand_doubleword_shift handles the cases in which
804 the effective shift value is >= BITS_PER_WORD. The arguments and return
805 value are the same as for the parent routine, except that SUPERWORD_OP1
806 is the shift count to use when shifting OUTOF_INPUT into INTO_TARGET.
807 INTO_TARGET may be null if the caller has decided to calculate it. */
810 expand_superword_shift (optab binoptab
, rtx outof_input
, rtx superword_op1
,
811 rtx outof_target
, rtx into_target
,
812 int unsignedp
, enum optab_methods methods
)
814 if (into_target
!= 0)
815 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, superword_op1
,
816 into_target
, unsignedp
, methods
))
819 if (outof_target
!= 0)
821 /* For a signed right shift, we must fill OUTOF_TARGET with copies
822 of the sign bit, otherwise we must fill it with zeros. */
823 if (binoptab
!= ashr_optab
)
824 emit_move_insn (outof_target
, CONST0_RTX (word_mode
));
826 if (!force_expand_binop (word_mode
, binoptab
,
827 outof_input
, GEN_INT (BITS_PER_WORD
- 1),
828 outof_target
, unsignedp
, methods
))
834 /* This subroutine of expand_doubleword_shift handles the cases in which
835 the effective shift value is < BITS_PER_WORD. The arguments and return
836 value are the same as for the parent routine. */
839 expand_subword_shift (enum machine_mode op1_mode
, optab binoptab
,
840 rtx outof_input
, rtx into_input
, rtx op1
,
841 rtx outof_target
, rtx into_target
,
842 int unsignedp
, enum optab_methods methods
,
843 unsigned HOST_WIDE_INT shift_mask
)
845 optab reverse_unsigned_shift
, unsigned_shift
;
848 reverse_unsigned_shift
= (binoptab
== ashl_optab
? lshr_optab
: ashl_optab
);
849 unsigned_shift
= (binoptab
== ashl_optab
? ashl_optab
: lshr_optab
);
851 /* The low OP1 bits of INTO_TARGET come from the high bits of OUTOF_INPUT.
852 We therefore need to shift OUTOF_INPUT by (BITS_PER_WORD - OP1) bits in
853 the opposite direction to BINOPTAB. */
854 if (CONSTANT_P (op1
) || shift_mask
>= BITS_PER_WORD
)
856 carries
= outof_input
;
857 tmp
= immed_double_const (BITS_PER_WORD
, 0, op1_mode
);
858 tmp
= simplify_expand_binop (op1_mode
, sub_optab
, tmp
, op1
,
863 /* We must avoid shifting by BITS_PER_WORD bits since that is either
864 the same as a zero shift (if shift_mask == BITS_PER_WORD - 1) or
865 has unknown behavior. Do a single shift first, then shift by the
866 remainder. It's OK to use ~OP1 as the remainder if shift counts
867 are truncated to the mode size. */
868 carries
= expand_binop (word_mode
, reverse_unsigned_shift
,
869 outof_input
, const1_rtx
, 0, unsignedp
, methods
);
870 if (shift_mask
== BITS_PER_WORD
- 1)
872 tmp
= immed_double_const (-1, -1, op1_mode
);
873 tmp
= simplify_expand_binop (op1_mode
, xor_optab
, op1
, tmp
,
878 tmp
= immed_double_const (BITS_PER_WORD
- 1, 0, op1_mode
);
879 tmp
= simplify_expand_binop (op1_mode
, sub_optab
, tmp
, op1
,
883 if (tmp
== 0 || carries
== 0)
885 carries
= expand_binop (word_mode
, reverse_unsigned_shift
,
886 carries
, tmp
, 0, unsignedp
, methods
);
890 /* Shift INTO_INPUT logically by OP1. This is the last use of INTO_INPUT
891 so the result can go directly into INTO_TARGET if convenient. */
892 tmp
= expand_binop (word_mode
, unsigned_shift
, into_input
, op1
,
893 into_target
, unsignedp
, methods
);
897 /* Now OR in the bits carried over from OUTOF_INPUT. */
898 if (!force_expand_binop (word_mode
, ior_optab
, tmp
, carries
,
899 into_target
, unsignedp
, methods
))
902 /* Use a standard word_mode shift for the out-of half. */
903 if (outof_target
!= 0)
904 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, op1
,
905 outof_target
, unsignedp
, methods
))
912 #ifdef HAVE_conditional_move
913 /* Try implementing expand_doubleword_shift using conditional moves.
914 The shift is by < BITS_PER_WORD if (CMP_CODE CMP1 CMP2) is true,
915 otherwise it is by >= BITS_PER_WORD. SUBWORD_OP1 and SUPERWORD_OP1
916 are the shift counts to use in the former and latter case. All other
917 arguments are the same as the parent routine. */
920 expand_doubleword_shift_condmove (enum machine_mode op1_mode
, optab binoptab
,
921 enum rtx_code cmp_code
, rtx cmp1
, rtx cmp2
,
922 rtx outof_input
, rtx into_input
,
923 rtx subword_op1
, rtx superword_op1
,
924 rtx outof_target
, rtx into_target
,
925 int unsignedp
, enum optab_methods methods
,
926 unsigned HOST_WIDE_INT shift_mask
)
928 rtx outof_superword
, into_superword
;
930 /* Put the superword version of the output into OUTOF_SUPERWORD and
932 outof_superword
= outof_target
!= 0 ? gen_reg_rtx (word_mode
) : 0;
933 if (outof_target
!= 0 && subword_op1
== superword_op1
)
935 /* The value INTO_TARGET >> SUBWORD_OP1, which we later store in
936 OUTOF_TARGET, is the same as the value of INTO_SUPERWORD. */
937 into_superword
= outof_target
;
938 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
939 outof_superword
, 0, unsignedp
, methods
))
944 into_superword
= gen_reg_rtx (word_mode
);
945 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
946 outof_superword
, into_superword
,
951 /* Put the subword version directly in OUTOF_TARGET and INTO_TARGET. */
952 if (!expand_subword_shift (op1_mode
, binoptab
,
953 outof_input
, into_input
, subword_op1
,
954 outof_target
, into_target
,
955 unsignedp
, methods
, shift_mask
))
958 /* Select between them. Do the INTO half first because INTO_SUPERWORD
959 might be the current value of OUTOF_TARGET. */
960 if (!emit_conditional_move (into_target
, cmp_code
, cmp1
, cmp2
, op1_mode
,
961 into_target
, into_superword
, word_mode
, false))
964 if (outof_target
!= 0)
965 if (!emit_conditional_move (outof_target
, cmp_code
, cmp1
, cmp2
, op1_mode
,
966 outof_target
, outof_superword
,
974 /* Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts.
975 OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first
976 input operand; the shift moves bits in the direction OUTOF_INPUT->
977 INTO_TARGET. OUTOF_TARGET and INTO_TARGET are the equivalent words
978 of the target. OP1 is the shift count and OP1_MODE is its mode.
979 If OP1 is constant, it will have been truncated as appropriate
980 and is known to be nonzero.
982 If SHIFT_MASK is zero, the result of word shifts is undefined when the
983 shift count is outside the range [0, BITS_PER_WORD). This routine must
984 avoid generating such shifts for OP1s in the range [0, BITS_PER_WORD * 2).
986 If SHIFT_MASK is nonzero, all word-mode shift counts are effectively
987 masked by it and shifts in the range [BITS_PER_WORD, SHIFT_MASK) will
988 fill with zeros or sign bits as appropriate.
990 If SHIFT_MASK is BITS_PER_WORD - 1, this routine will synthesize
991 a doubleword shift whose equivalent mask is BITS_PER_WORD * 2 - 1.
992 Doing this preserves semantics required by SHIFT_COUNT_TRUNCATED.
993 In all other cases, shifts by values outside [0, BITS_PER_UNIT * 2)
996 BINOPTAB, UNSIGNEDP and METHODS are as for expand_binop. This function
997 may not use INTO_INPUT after modifying INTO_TARGET, and similarly for
998 OUTOF_INPUT and OUTOF_TARGET. OUTOF_TARGET can be null if the parent
999 function wants to calculate it itself.
1001 Return true if the shift could be successfully synthesized. */
1004 expand_doubleword_shift (enum machine_mode op1_mode
, optab binoptab
,
1005 rtx outof_input
, rtx into_input
, rtx op1
,
1006 rtx outof_target
, rtx into_target
,
1007 int unsignedp
, enum optab_methods methods
,
1008 unsigned HOST_WIDE_INT shift_mask
)
1010 rtx superword_op1
, tmp
, cmp1
, cmp2
;
1011 rtx subword_label
, done_label
;
1012 enum rtx_code cmp_code
;
1014 /* See if word-mode shifts by BITS_PER_WORD...BITS_PER_WORD * 2 - 1 will
1015 fill the result with sign or zero bits as appropriate. If so, the value
1016 of OUTOF_TARGET will always be (SHIFT OUTOF_INPUT OP1). Recursively call
1017 this routine to calculate INTO_TARGET (which depends on both OUTOF_INPUT
1018 and INTO_INPUT), then emit code to set up OUTOF_TARGET.
1020 This isn't worthwhile for constant shifts since the optimizers will
1021 cope better with in-range shift counts. */
1022 if (shift_mask
>= BITS_PER_WORD
1023 && outof_target
!= 0
1024 && !CONSTANT_P (op1
))
1026 if (!expand_doubleword_shift (op1_mode
, binoptab
,
1027 outof_input
, into_input
, op1
,
1029 unsignedp
, methods
, shift_mask
))
1031 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, op1
,
1032 outof_target
, unsignedp
, methods
))
1037 /* Set CMP_CODE, CMP1 and CMP2 so that the rtx (CMP_CODE CMP1 CMP2)
1038 is true when the effective shift value is less than BITS_PER_WORD.
1039 Set SUPERWORD_OP1 to the shift count that should be used to shift
1040 OUTOF_INPUT into INTO_TARGET when the condition is false. */
1041 tmp
= immed_double_const (BITS_PER_WORD
, 0, op1_mode
);
1042 if (!CONSTANT_P (op1
) && shift_mask
== BITS_PER_WORD
- 1)
1044 /* Set CMP1 to OP1 & BITS_PER_WORD. The result is zero iff OP1
1045 is a subword shift count. */
1046 cmp1
= simplify_expand_binop (op1_mode
, and_optab
, op1
, tmp
,
1048 cmp2
= CONST0_RTX (op1_mode
);
1050 superword_op1
= op1
;
1054 /* Set CMP1 to OP1 - BITS_PER_WORD. */
1055 cmp1
= simplify_expand_binop (op1_mode
, sub_optab
, op1
, tmp
,
1057 cmp2
= CONST0_RTX (op1_mode
);
1059 superword_op1
= cmp1
;
1064 /* If we can compute the condition at compile time, pick the
1065 appropriate subroutine. */
1066 tmp
= simplify_relational_operation (cmp_code
, SImode
, op1_mode
, cmp1
, cmp2
);
1067 if (tmp
!= 0 && CONST_INT_P (tmp
))
1069 if (tmp
== const0_rtx
)
1070 return expand_superword_shift (binoptab
, outof_input
, superword_op1
,
1071 outof_target
, into_target
,
1072 unsignedp
, methods
);
1074 return expand_subword_shift (op1_mode
, binoptab
,
1075 outof_input
, into_input
, op1
,
1076 outof_target
, into_target
,
1077 unsignedp
, methods
, shift_mask
);
1080 #ifdef HAVE_conditional_move
1081 /* Try using conditional moves to generate straight-line code. */
1083 rtx start
= get_last_insn ();
1084 if (expand_doubleword_shift_condmove (op1_mode
, binoptab
,
1085 cmp_code
, cmp1
, cmp2
,
1086 outof_input
, into_input
,
1088 outof_target
, into_target
,
1089 unsignedp
, methods
, shift_mask
))
1091 delete_insns_since (start
);
1095 /* As a last resort, use branches to select the correct alternative. */
1096 subword_label
= gen_label_rtx ();
1097 done_label
= gen_label_rtx ();
1100 do_compare_rtx_and_jump (cmp1
, cmp2
, cmp_code
, false, op1_mode
,
1101 0, 0, subword_label
, -1);
1104 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
1105 outof_target
, into_target
,
1106 unsignedp
, methods
))
1109 emit_jump_insn (gen_jump (done_label
));
1111 emit_label (subword_label
);
1113 if (!expand_subword_shift (op1_mode
, binoptab
,
1114 outof_input
, into_input
, op1
,
1115 outof_target
, into_target
,
1116 unsignedp
, methods
, shift_mask
))
1119 emit_label (done_label
);
1123 /* Subroutine of expand_binop. Perform a double word multiplication of
1124 operands OP0 and OP1 both of mode MODE, which is exactly twice as wide
1125 as the target's word_mode. This function return NULL_RTX if anything
1126 goes wrong, in which case it may have already emitted instructions
1127 which need to be deleted.
1129 If we want to multiply two two-word values and have normal and widening
1130 multiplies of single-word values, we can do this with three smaller
1133 The multiplication proceeds as follows:
1134 _______________________
1135 [__op0_high_|__op0_low__]
1136 _______________________
1137 * [__op1_high_|__op1_low__]
1138 _______________________________________________
1139 _______________________
1140 (1) [__op0_low__*__op1_low__]
1141 _______________________
1142 (2a) [__op0_low__*__op1_high_]
1143 _______________________
1144 (2b) [__op0_high_*__op1_low__]
1145 _______________________
1146 (3) [__op0_high_*__op1_high_]
1149 This gives a 4-word result. Since we are only interested in the
1150 lower 2 words, partial result (3) and the upper words of (2a) and
1151 (2b) don't need to be calculated. Hence (2a) and (2b) can be
1152 calculated using non-widening multiplication.
1154 (1), however, needs to be calculated with an unsigned widening
1155 multiplication. If this operation is not directly supported we
1156 try using a signed widening multiplication and adjust the result.
1157 This adjustment works as follows:
1159 If both operands are positive then no adjustment is needed.
1161 If the operands have different signs, for example op0_low < 0 and
1162 op1_low >= 0, the instruction treats the most significant bit of
1163 op0_low as a sign bit instead of a bit with significance
1164 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low
1165 with 2**BITS_PER_WORD - op0_low, and two's complements the
1166 result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to
1169 Similarly, if both operands are negative, we need to add
1170 (op0_low + op1_low) * 2**BITS_PER_WORD.
1172 We use a trick to adjust quickly. We logically shift op0_low right
1173 (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to
1174 op0_high (op1_high) before it is used to calculate 2b (2a). If no
1175 logical shift exists, we do an arithmetic right shift and subtract
1179 expand_doubleword_mult (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
1180 bool umulp
, enum optab_methods methods
)
1182 int low
= (WORDS_BIG_ENDIAN
? 1 : 0);
1183 int high
= (WORDS_BIG_ENDIAN
? 0 : 1);
1184 rtx wordm1
= umulp
? NULL_RTX
: GEN_INT (BITS_PER_WORD
- 1);
1185 rtx product
, adjust
, product_high
, temp
;
1187 rtx op0_high
= operand_subword_force (op0
, high
, mode
);
1188 rtx op0_low
= operand_subword_force (op0
, low
, mode
);
1189 rtx op1_high
= operand_subword_force (op1
, high
, mode
);
1190 rtx op1_low
= operand_subword_force (op1
, low
, mode
);
1192 /* If we're using an unsigned multiply to directly compute the product
1193 of the low-order words of the operands and perform any required
1194 adjustments of the operands, we begin by trying two more multiplications
1195 and then computing the appropriate sum.
1197 We have checked above that the required addition is provided.
1198 Full-word addition will normally always succeed, especially if
1199 it is provided at all, so we don't worry about its failure. The
1200 multiplication may well fail, however, so we do handle that. */
1204 /* ??? This could be done with emit_store_flag where available. */
1205 temp
= expand_binop (word_mode
, lshr_optab
, op0_low
, wordm1
,
1206 NULL_RTX
, 1, methods
);
1208 op0_high
= expand_binop (word_mode
, add_optab
, op0_high
, temp
,
1209 NULL_RTX
, 0, OPTAB_DIRECT
);
1212 temp
= expand_binop (word_mode
, ashr_optab
, op0_low
, wordm1
,
1213 NULL_RTX
, 0, methods
);
1216 op0_high
= expand_binop (word_mode
, sub_optab
, op0_high
, temp
,
1217 NULL_RTX
, 0, OPTAB_DIRECT
);
1224 adjust
= expand_binop (word_mode
, smul_optab
, op0_high
, op1_low
,
1225 NULL_RTX
, 0, OPTAB_DIRECT
);
1229 /* OP0_HIGH should now be dead. */
1233 /* ??? This could be done with emit_store_flag where available. */
1234 temp
= expand_binop (word_mode
, lshr_optab
, op1_low
, wordm1
,
1235 NULL_RTX
, 1, methods
);
1237 op1_high
= expand_binop (word_mode
, add_optab
, op1_high
, temp
,
1238 NULL_RTX
, 0, OPTAB_DIRECT
);
1241 temp
= expand_binop (word_mode
, ashr_optab
, op1_low
, wordm1
,
1242 NULL_RTX
, 0, methods
);
1245 op1_high
= expand_binop (word_mode
, sub_optab
, op1_high
, temp
,
1246 NULL_RTX
, 0, OPTAB_DIRECT
);
1253 temp
= expand_binop (word_mode
, smul_optab
, op1_high
, op0_low
,
1254 NULL_RTX
, 0, OPTAB_DIRECT
);
1258 /* OP1_HIGH should now be dead. */
1260 adjust
= expand_binop (word_mode
, add_optab
, adjust
, temp
,
1261 NULL_RTX
, 0, OPTAB_DIRECT
);
1263 if (target
&& !REG_P (target
))
1267 product
= expand_binop (mode
, umul_widen_optab
, op0_low
, op1_low
,
1268 target
, 1, OPTAB_DIRECT
);
1270 product
= expand_binop (mode
, smul_widen_optab
, op0_low
, op1_low
,
1271 target
, 1, OPTAB_DIRECT
);
1276 product_high
= operand_subword (product
, high
, 1, mode
);
1277 adjust
= expand_binop (word_mode
, add_optab
, product_high
, adjust
,
1278 NULL_RTX
, 0, OPTAB_DIRECT
);
1279 emit_move_insn (product_high
, adjust
);
1283 /* Wrapper around expand_binop which takes an rtx code to specify
1284 the operation to perform, not an optab pointer. All other
1285 arguments are the same. */
1287 expand_simple_binop (enum machine_mode mode
, enum rtx_code code
, rtx op0
,
1288 rtx op1
, rtx target
, int unsignedp
,
1289 enum optab_methods methods
)
1291 optab binop
= code_to_optab (code
);
1294 return expand_binop (mode
, binop
, op0
, op1
, target
, unsignedp
, methods
);
1297 /* Return whether OP0 and OP1 should be swapped when expanding a commutative
1298 binop. Order them according to commutative_operand_precedence and, if
1299 possible, try to put TARGET or a pseudo first. */
1301 swap_commutative_operands_with_target (rtx target
, rtx op0
, rtx op1
)
1303 int op0_prec
= commutative_operand_precedence (op0
);
1304 int op1_prec
= commutative_operand_precedence (op1
);
1306 if (op0_prec
< op1_prec
)
1309 if (op0_prec
> op1_prec
)
1312 /* With equal precedence, both orders are ok, but it is better if the
1313 first operand is TARGET, or if both TARGET and OP0 are pseudos. */
1314 if (target
== 0 || REG_P (target
))
1315 return (REG_P (op1
) && !REG_P (op0
)) || target
== op1
;
1317 return rtx_equal_p (op1
, target
);
1320 /* Return true if BINOPTAB implements a shift operation. */
1323 shift_optab_p (optab binoptab
)
1325 switch (optab_to_code (binoptab
))
1341 /* Return true if BINOPTAB implements a commutative binary operation. */
1344 commutative_optab_p (optab binoptab
)
1346 return (GET_RTX_CLASS (optab_to_code (binoptab
)) == RTX_COMM_ARITH
1347 || binoptab
== smul_widen_optab
1348 || binoptab
== umul_widen_optab
1349 || binoptab
== smul_highpart_optab
1350 || binoptab
== umul_highpart_optab
);
1353 /* X is to be used in mode MODE as operand OPN to BINOPTAB. If we're
1354 optimizing, and if the operand is a constant that costs more than
1355 1 instruction, force the constant into a register and return that
1356 register. Return X otherwise. UNSIGNEDP says whether X is unsigned. */
1359 avoid_expensive_constant (enum machine_mode mode
, optab binoptab
,
1360 int opn
, rtx x
, bool unsignedp
)
1362 bool speed
= optimize_insn_for_speed_p ();
1364 if (mode
!= VOIDmode
1367 && (rtx_cost (x
, optab_to_code (binoptab
), opn
, speed
)
1368 > set_src_cost (x
, speed
)))
1370 if (CONST_INT_P (x
))
1372 HOST_WIDE_INT intval
= trunc_int_for_mode (INTVAL (x
), mode
);
1373 if (intval
!= INTVAL (x
))
1374 x
= GEN_INT (intval
);
1377 x
= convert_modes (mode
, VOIDmode
, x
, unsignedp
);
1378 x
= force_reg (mode
, x
);
1383 /* Helper function for expand_binop: handle the case where there
1384 is an insn that directly implements the indicated operation.
1385 Returns null if this is not possible. */
1387 expand_binop_directly (enum machine_mode mode
, optab binoptab
,
1389 rtx target
, int unsignedp
, enum optab_methods methods
,
1392 enum machine_mode from_mode
= widened_mode (mode
, op0
, op1
);
1393 enum insn_code icode
= find_widening_optab_handler (binoptab
, mode
,
1395 enum machine_mode xmode0
= insn_data
[(int) icode
].operand
[1].mode
;
1396 enum machine_mode xmode1
= insn_data
[(int) icode
].operand
[2].mode
;
1397 enum machine_mode mode0
, mode1
, tmp_mode
;
1398 struct expand_operand ops
[3];
1401 rtx xop0
= op0
, xop1
= op1
;
1404 /* If it is a commutative operator and the modes would match
1405 if we would swap the operands, we can save the conversions. */
1406 commutative_p
= commutative_optab_p (binoptab
);
1408 && GET_MODE (xop0
) != xmode0
&& GET_MODE (xop1
) != xmode1
1409 && GET_MODE (xop0
) == xmode1
&& GET_MODE (xop1
) == xmode1
)
1416 /* If we are optimizing, force expensive constants into a register. */
1417 xop0
= avoid_expensive_constant (xmode0
, binoptab
, 0, xop0
, unsignedp
);
1418 if (!shift_optab_p (binoptab
))
1419 xop1
= avoid_expensive_constant (xmode1
, binoptab
, 1, xop1
, unsignedp
);
1421 /* In case the insn wants input operands in modes different from
1422 those of the actual operands, convert the operands. It would
1423 seem that we don't need to convert CONST_INTs, but we do, so
1424 that they're properly zero-extended, sign-extended or truncated
1427 mode0
= GET_MODE (xop0
) != VOIDmode
? GET_MODE (xop0
) : mode
;
1428 if (xmode0
!= VOIDmode
&& xmode0
!= mode0
)
1430 xop0
= convert_modes (xmode0
, mode0
, xop0
, unsignedp
);
1434 mode1
= GET_MODE (xop1
) != VOIDmode
? GET_MODE (xop1
) : mode
;
1435 if (xmode1
!= VOIDmode
&& xmode1
!= mode1
)
1437 xop1
= convert_modes (xmode1
, mode1
, xop1
, unsignedp
);
1441 /* If operation is commutative,
1442 try to make the first operand a register.
1443 Even better, try to make it the same as the target.
1444 Also try to make the last operand a constant. */
1446 && swap_commutative_operands_with_target (target
, xop0
, xop1
))
1453 /* Now, if insn's predicates don't allow our operands, put them into
1456 if (binoptab
== vec_pack_trunc_optab
1457 || binoptab
== vec_pack_usat_optab
1458 || binoptab
== vec_pack_ssat_optab
1459 || binoptab
== vec_pack_ufix_trunc_optab
1460 || binoptab
== vec_pack_sfix_trunc_optab
)
1462 /* The mode of the result is different then the mode of the
1464 tmp_mode
= insn_data
[(int) icode
].operand
[0].mode
;
1465 if (GET_MODE_NUNITS (tmp_mode
) != 2 * GET_MODE_NUNITS (mode
))
1467 delete_insns_since (last
);
1474 create_output_operand (&ops
[0], target
, tmp_mode
);
1475 create_input_operand (&ops
[1], xop0
, mode0
);
1476 create_input_operand (&ops
[2], xop1
, mode1
);
1477 pat
= maybe_gen_insn (icode
, 3, ops
);
1480 /* If PAT is composed of more than one insn, try to add an appropriate
1481 REG_EQUAL note to it. If we can't because TEMP conflicts with an
1482 operand, call expand_binop again, this time without a target. */
1483 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
1484 && ! add_equal_note (pat
, ops
[0].value
, optab_to_code (binoptab
),
1485 ops
[1].value
, ops
[2].value
))
1487 delete_insns_since (last
);
1488 return expand_binop (mode
, binoptab
, op0
, op1
, NULL_RTX
,
1489 unsignedp
, methods
);
1493 return ops
[0].value
;
1495 delete_insns_since (last
);
1499 /* Generate code to perform an operation specified by BINOPTAB
1500 on operands OP0 and OP1, with result having machine-mode MODE.
1502 UNSIGNEDP is for the case where we have to widen the operands
1503 to perform the operation. It says to use zero-extension.
1505 If TARGET is nonzero, the value
1506 is generated there, if it is convenient to do so.
1507 In all cases an rtx is returned for the locus of the value;
1508 this may or may not be TARGET. */
1511 expand_binop (enum machine_mode mode
, optab binoptab
, rtx op0
, rtx op1
,
1512 rtx target
, int unsignedp
, enum optab_methods methods
)
1514 enum optab_methods next_methods
1515 = (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
1516 ? OPTAB_WIDEN
: methods
);
1517 enum mode_class mclass
;
1518 enum machine_mode wider_mode
;
1521 rtx entry_last
= get_last_insn ();
1524 mclass
= GET_MODE_CLASS (mode
);
1526 /* If subtracting an integer constant, convert this into an addition of
1527 the negated constant. */
1529 if (binoptab
== sub_optab
&& CONST_INT_P (op1
))
1531 op1
= negate_rtx (mode
, op1
);
1532 binoptab
= add_optab
;
1535 /* Record where to delete back to if we backtrack. */
1536 last
= get_last_insn ();
1538 /* If we can do it with a three-operand insn, do so. */
1540 if (methods
!= OPTAB_MUST_WIDEN
1541 && find_widening_optab_handler (binoptab
, mode
,
1542 widened_mode (mode
, op0
, op1
), 1)
1543 != CODE_FOR_nothing
)
1545 temp
= expand_binop_directly (mode
, binoptab
, op0
, op1
, target
,
1546 unsignedp
, methods
, last
);
1551 /* If we were trying to rotate, and that didn't work, try rotating
1552 the other direction before falling back to shifts and bitwise-or. */
1553 if (((binoptab
== rotl_optab
1554 && optab_handler (rotr_optab
, mode
) != CODE_FOR_nothing
)
1555 || (binoptab
== rotr_optab
1556 && optab_handler (rotl_optab
, mode
) != CODE_FOR_nothing
))
1557 && mclass
== MODE_INT
)
1559 optab otheroptab
= (binoptab
== rotl_optab
? rotr_optab
: rotl_optab
);
1561 unsigned int bits
= GET_MODE_PRECISION (mode
);
1563 if (CONST_INT_P (op1
))
1564 newop1
= GEN_INT (bits
- INTVAL (op1
));
1565 else if (targetm
.shift_truncation_mask (mode
) == bits
- 1)
1566 newop1
= negate_rtx (GET_MODE (op1
), op1
);
1568 newop1
= expand_binop (GET_MODE (op1
), sub_optab
,
1569 gen_int_mode (bits
, GET_MODE (op1
)), op1
,
1570 NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
1572 temp
= expand_binop_directly (mode
, otheroptab
, op0
, newop1
,
1573 target
, unsignedp
, methods
, last
);
1578 /* If this is a multiply, see if we can do a widening operation that
1579 takes operands of this mode and makes a wider mode. */
1581 if (binoptab
== smul_optab
1582 && GET_MODE_2XWIDER_MODE (mode
) != VOIDmode
1583 && (widening_optab_handler ((unsignedp
? umul_widen_optab
1584 : smul_widen_optab
),
1585 GET_MODE_2XWIDER_MODE (mode
), mode
)
1586 != CODE_FOR_nothing
))
1588 temp
= expand_binop (GET_MODE_2XWIDER_MODE (mode
),
1589 unsignedp
? umul_widen_optab
: smul_widen_optab
,
1590 op0
, op1
, NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
1594 if (GET_MODE_CLASS (mode
) == MODE_INT
1595 && TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (temp
)))
1596 return gen_lowpart (mode
, temp
);
1598 return convert_to_mode (mode
, temp
, unsignedp
);
1602 /* If this is a vector shift by a scalar, see if we can do a vector
1603 shift by a vector. If so, broadcast the scalar into a vector. */
1604 if (mclass
== MODE_VECTOR_INT
)
1606 optab otheroptab
= unknown_optab
;
1608 if (binoptab
== ashl_optab
)
1609 otheroptab
= vashl_optab
;
1610 else if (binoptab
== ashr_optab
)
1611 otheroptab
= vashr_optab
;
1612 else if (binoptab
== lshr_optab
)
1613 otheroptab
= vlshr_optab
;
1614 else if (binoptab
== rotl_optab
)
1615 otheroptab
= vrotl_optab
;
1616 else if (binoptab
== rotr_optab
)
1617 otheroptab
= vrotr_optab
;
1619 if (otheroptab
&& optab_handler (otheroptab
, mode
) != CODE_FOR_nothing
)
1621 rtx vop1
= expand_vector_broadcast (mode
, op1
);
1624 temp
= expand_binop_directly (mode
, otheroptab
, op0
, vop1
,
1625 target
, unsignedp
, methods
, last
);
1632 /* Look for a wider mode of the same class for which we think we
1633 can open-code the operation. Check for a widening multiply at the
1634 wider mode as well. */
1636 if (CLASS_HAS_WIDER_MODES_P (mclass
)
1637 && methods
!= OPTAB_DIRECT
&& methods
!= OPTAB_LIB
)
1638 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
1639 wider_mode
!= VOIDmode
;
1640 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
1642 if (optab_handler (binoptab
, wider_mode
) != CODE_FOR_nothing
1643 || (binoptab
== smul_optab
1644 && GET_MODE_WIDER_MODE (wider_mode
) != VOIDmode
1645 && (find_widening_optab_handler ((unsignedp
1647 : smul_widen_optab
),
1648 GET_MODE_WIDER_MODE (wider_mode
),
1650 != CODE_FOR_nothing
)))
1652 rtx xop0
= op0
, xop1
= op1
;
1655 /* For certain integer operations, we need not actually extend
1656 the narrow operands, as long as we will truncate
1657 the results to the same narrowness. */
1659 if ((binoptab
== ior_optab
|| binoptab
== and_optab
1660 || binoptab
== xor_optab
1661 || binoptab
== add_optab
|| binoptab
== sub_optab
1662 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
1663 && mclass
== MODE_INT
)
1666 xop0
= avoid_expensive_constant (mode
, binoptab
, 0,
1668 if (binoptab
!= ashl_optab
)
1669 xop1
= avoid_expensive_constant (mode
, binoptab
, 1,
1673 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
, no_extend
);
1675 /* The second operand of a shift must always be extended. */
1676 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
1677 no_extend
&& binoptab
!= ashl_optab
);
1679 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
1680 unsignedp
, OPTAB_DIRECT
);
1683 if (mclass
!= MODE_INT
1684 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
1687 target
= gen_reg_rtx (mode
);
1688 convert_move (target
, temp
, 0);
1692 return gen_lowpart (mode
, temp
);
1695 delete_insns_since (last
);
1699 /* If operation is commutative,
1700 try to make the first operand a register.
1701 Even better, try to make it the same as the target.
1702 Also try to make the last operand a constant. */
1703 if (commutative_optab_p (binoptab
)
1704 && swap_commutative_operands_with_target (target
, op0
, op1
))
1711 /* These can be done a word at a time. */
1712 if ((binoptab
== and_optab
|| binoptab
== ior_optab
|| binoptab
== xor_optab
)
1713 && mclass
== MODE_INT
1714 && GET_MODE_SIZE (mode
) > UNITS_PER_WORD
1715 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
)
1720 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1721 won't be accurate, so use a new target. */
1725 || !valid_multiword_target_p (target
))
1726 target
= gen_reg_rtx (mode
);
1730 /* Do the actual arithmetic. */
1731 for (i
= 0; i
< GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
; i
++)
1733 rtx target_piece
= operand_subword (target
, i
, 1, mode
);
1734 rtx x
= expand_binop (word_mode
, binoptab
,
1735 operand_subword_force (op0
, i
, mode
),
1736 operand_subword_force (op1
, i
, mode
),
1737 target_piece
, unsignedp
, next_methods
);
1742 if (target_piece
!= x
)
1743 emit_move_insn (target_piece
, x
);
1746 insns
= get_insns ();
1749 if (i
== GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
)
1756 /* Synthesize double word shifts from single word shifts. */
1757 if ((binoptab
== lshr_optab
|| binoptab
== ashl_optab
1758 || binoptab
== ashr_optab
)
1759 && mclass
== MODE_INT
1760 && (CONST_INT_P (op1
) || optimize_insn_for_speed_p ())
1761 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
1762 && GET_MODE_PRECISION (mode
) == GET_MODE_BITSIZE (mode
)
1763 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
1764 && optab_handler (ashl_optab
, word_mode
) != CODE_FOR_nothing
1765 && optab_handler (lshr_optab
, word_mode
) != CODE_FOR_nothing
)
1767 unsigned HOST_WIDE_INT shift_mask
, double_shift_mask
;
1768 enum machine_mode op1_mode
;
1770 double_shift_mask
= targetm
.shift_truncation_mask (mode
);
1771 shift_mask
= targetm
.shift_truncation_mask (word_mode
);
1772 op1_mode
= GET_MODE (op1
) != VOIDmode
? GET_MODE (op1
) : word_mode
;
1774 /* Apply the truncation to constant shifts. */
1775 if (double_shift_mask
> 0 && CONST_INT_P (op1
))
1776 op1
= GEN_INT (INTVAL (op1
) & double_shift_mask
);
1778 if (op1
== CONST0_RTX (op1_mode
))
1781 /* Make sure that this is a combination that expand_doubleword_shift
1782 can handle. See the comments there for details. */
1783 if (double_shift_mask
== 0
1784 || (shift_mask
== BITS_PER_WORD
- 1
1785 && double_shift_mask
== BITS_PER_WORD
* 2 - 1))
1788 rtx into_target
, outof_target
;
1789 rtx into_input
, outof_input
;
1790 int left_shift
, outof_word
;
1792 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1793 won't be accurate, so use a new target. */
1797 || !valid_multiword_target_p (target
))
1798 target
= gen_reg_rtx (mode
);
1802 /* OUTOF_* is the word we are shifting bits away from, and
1803 INTO_* is the word that we are shifting bits towards, thus
1804 they differ depending on the direction of the shift and
1805 WORDS_BIG_ENDIAN. */
1807 left_shift
= binoptab
== ashl_optab
;
1808 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
1810 outof_target
= operand_subword (target
, outof_word
, 1, mode
);
1811 into_target
= operand_subword (target
, 1 - outof_word
, 1, mode
);
1813 outof_input
= operand_subword_force (op0
, outof_word
, mode
);
1814 into_input
= operand_subword_force (op0
, 1 - outof_word
, mode
);
1816 if (expand_doubleword_shift (op1_mode
, binoptab
,
1817 outof_input
, into_input
, op1
,
1818 outof_target
, into_target
,
1819 unsignedp
, next_methods
, shift_mask
))
1821 insns
= get_insns ();
1831 /* Synthesize double word rotates from single word shifts. */
1832 if ((binoptab
== rotl_optab
|| binoptab
== rotr_optab
)
1833 && mclass
== MODE_INT
1834 && CONST_INT_P (op1
)
1835 && GET_MODE_PRECISION (mode
) == 2 * BITS_PER_WORD
1836 && optab_handler (ashl_optab
, word_mode
) != CODE_FOR_nothing
1837 && optab_handler (lshr_optab
, word_mode
) != CODE_FOR_nothing
)
1840 rtx into_target
, outof_target
;
1841 rtx into_input
, outof_input
;
1843 int shift_count
, left_shift
, outof_word
;
1845 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1846 won't be accurate, so use a new target. Do this also if target is not
1847 a REG, first because having a register instead may open optimization
1848 opportunities, and second because if target and op0 happen to be MEMs
1849 designating the same location, we would risk clobbering it too early
1850 in the code sequence we generate below. */
1855 || !valid_multiword_target_p (target
))
1856 target
= gen_reg_rtx (mode
);
1860 shift_count
= INTVAL (op1
);
1862 /* OUTOF_* is the word we are shifting bits away from, and
1863 INTO_* is the word that we are shifting bits towards, thus
1864 they differ depending on the direction of the shift and
1865 WORDS_BIG_ENDIAN. */
1867 left_shift
= (binoptab
== rotl_optab
);
1868 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
1870 outof_target
= operand_subword (target
, outof_word
, 1, mode
);
1871 into_target
= operand_subword (target
, 1 - outof_word
, 1, mode
);
1873 outof_input
= operand_subword_force (op0
, outof_word
, mode
);
1874 into_input
= operand_subword_force (op0
, 1 - outof_word
, mode
);
1876 if (shift_count
== BITS_PER_WORD
)
1878 /* This is just a word swap. */
1879 emit_move_insn (outof_target
, into_input
);
1880 emit_move_insn (into_target
, outof_input
);
1885 rtx into_temp1
, into_temp2
, outof_temp1
, outof_temp2
;
1886 rtx first_shift_count
, second_shift_count
;
1887 optab reverse_unsigned_shift
, unsigned_shift
;
1889 reverse_unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
1890 ? lshr_optab
: ashl_optab
);
1892 unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
1893 ? ashl_optab
: lshr_optab
);
1895 if (shift_count
> BITS_PER_WORD
)
1897 first_shift_count
= GEN_INT (shift_count
- BITS_PER_WORD
);
1898 second_shift_count
= GEN_INT (2 * BITS_PER_WORD
- shift_count
);
1902 first_shift_count
= GEN_INT (BITS_PER_WORD
- shift_count
);
1903 second_shift_count
= GEN_INT (shift_count
);
1906 into_temp1
= expand_binop (word_mode
, unsigned_shift
,
1907 outof_input
, first_shift_count
,
1908 NULL_RTX
, unsignedp
, next_methods
);
1909 into_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
1910 into_input
, second_shift_count
,
1911 NULL_RTX
, unsignedp
, next_methods
);
1913 if (into_temp1
!= 0 && into_temp2
!= 0)
1914 inter
= expand_binop (word_mode
, ior_optab
, into_temp1
, into_temp2
,
1915 into_target
, unsignedp
, next_methods
);
1919 if (inter
!= 0 && inter
!= into_target
)
1920 emit_move_insn (into_target
, inter
);
1922 outof_temp1
= expand_binop (word_mode
, unsigned_shift
,
1923 into_input
, first_shift_count
,
1924 NULL_RTX
, unsignedp
, next_methods
);
1925 outof_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
1926 outof_input
, second_shift_count
,
1927 NULL_RTX
, unsignedp
, next_methods
);
1929 if (inter
!= 0 && outof_temp1
!= 0 && outof_temp2
!= 0)
1930 inter
= expand_binop (word_mode
, ior_optab
,
1931 outof_temp1
, outof_temp2
,
1932 outof_target
, unsignedp
, next_methods
);
1934 if (inter
!= 0 && inter
!= outof_target
)
1935 emit_move_insn (outof_target
, inter
);
1938 insns
= get_insns ();
1948 /* These can be done a word at a time by propagating carries. */
1949 if ((binoptab
== add_optab
|| binoptab
== sub_optab
)
1950 && mclass
== MODE_INT
1951 && GET_MODE_SIZE (mode
) >= 2 * UNITS_PER_WORD
1952 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
)
1955 optab otheroptab
= binoptab
== add_optab
? sub_optab
: add_optab
;
1956 const unsigned int nwords
= GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
;
1957 rtx carry_in
= NULL_RTX
, carry_out
= NULL_RTX
;
1958 rtx xop0
, xop1
, xtarget
;
1960 /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG
1961 value is one of those, use it. Otherwise, use 1 since it is the
1962 one easiest to get. */
1963 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
1964 int normalizep
= STORE_FLAG_VALUE
;
1969 /* Prepare the operands. */
1970 xop0
= force_reg (mode
, op0
);
1971 xop1
= force_reg (mode
, op1
);
1973 xtarget
= gen_reg_rtx (mode
);
1975 if (target
== 0 || !REG_P (target
) || !valid_multiword_target_p (target
))
1978 /* Indicate for flow that the entire target reg is being set. */
1980 emit_clobber (xtarget
);
1982 /* Do the actual arithmetic. */
1983 for (i
= 0; i
< nwords
; i
++)
1985 int index
= (WORDS_BIG_ENDIAN
? nwords
- i
- 1 : i
);
1986 rtx target_piece
= operand_subword (xtarget
, index
, 1, mode
);
1987 rtx op0_piece
= operand_subword_force (xop0
, index
, mode
);
1988 rtx op1_piece
= operand_subword_force (xop1
, index
, mode
);
1991 /* Main add/subtract of the input operands. */
1992 x
= expand_binop (word_mode
, binoptab
,
1993 op0_piece
, op1_piece
,
1994 target_piece
, unsignedp
, next_methods
);
2000 /* Store carry from main add/subtract. */
2001 carry_out
= gen_reg_rtx (word_mode
);
2002 carry_out
= emit_store_flag_force (carry_out
,
2003 (binoptab
== add_optab
2006 word_mode
, 1, normalizep
);
2013 /* Add/subtract previous carry to main result. */
2014 newx
= expand_binop (word_mode
,
2015 normalizep
== 1 ? binoptab
: otheroptab
,
2017 NULL_RTX
, 1, next_methods
);
2021 /* Get out carry from adding/subtracting carry in. */
2022 rtx carry_tmp
= gen_reg_rtx (word_mode
);
2023 carry_tmp
= emit_store_flag_force (carry_tmp
,
2024 (binoptab
== add_optab
2027 word_mode
, 1, normalizep
);
2029 /* Logical-ior the two poss. carry together. */
2030 carry_out
= expand_binop (word_mode
, ior_optab
,
2031 carry_out
, carry_tmp
,
2032 carry_out
, 0, next_methods
);
2036 emit_move_insn (target_piece
, newx
);
2040 if (x
!= target_piece
)
2041 emit_move_insn (target_piece
, x
);
2044 carry_in
= carry_out
;
2047 if (i
== GET_MODE_BITSIZE (mode
) / (unsigned) BITS_PER_WORD
)
2049 if (optab_handler (mov_optab
, mode
) != CODE_FOR_nothing
2050 || ! rtx_equal_p (target
, xtarget
))
2052 rtx temp
= emit_move_insn (target
, xtarget
);
2054 set_dst_reg_note (temp
, REG_EQUAL
,
2055 gen_rtx_fmt_ee (optab_to_code (binoptab
),
2056 mode
, copy_rtx (xop0
),
2067 delete_insns_since (last
);
2070 /* Attempt to synthesize double word multiplies using a sequence of word
2071 mode multiplications. We first attempt to generate a sequence using a
2072 more efficient unsigned widening multiply, and if that fails we then
2073 try using a signed widening multiply. */
2075 if (binoptab
== smul_optab
2076 && mclass
== MODE_INT
2077 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
2078 && optab_handler (smul_optab
, word_mode
) != CODE_FOR_nothing
2079 && optab_handler (add_optab
, word_mode
) != CODE_FOR_nothing
)
2081 rtx product
= NULL_RTX
;
2082 if (widening_optab_handler (umul_widen_optab
, mode
, word_mode
)
2083 != CODE_FOR_nothing
)
2085 product
= expand_doubleword_mult (mode
, op0
, op1
, target
,
2088 delete_insns_since (last
);
2091 if (product
== NULL_RTX
2092 && widening_optab_handler (smul_widen_optab
, mode
, word_mode
)
2093 != CODE_FOR_nothing
)
2095 product
= expand_doubleword_mult (mode
, op0
, op1
, target
,
2098 delete_insns_since (last
);
2101 if (product
!= NULL_RTX
)
2103 if (optab_handler (mov_optab
, mode
) != CODE_FOR_nothing
)
2105 temp
= emit_move_insn (target
? target
: product
, product
);
2106 set_dst_reg_note (temp
,
2108 gen_rtx_fmt_ee (MULT
, mode
,
2111 target
? target
: product
);
2117 /* It can't be open-coded in this mode.
2118 Use a library call if one is available and caller says that's ok. */
2120 libfunc
= optab_libfunc (binoptab
, mode
);
2122 && (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
))
2126 enum machine_mode op1_mode
= mode
;
2131 if (shift_optab_p (binoptab
))
2133 op1_mode
= targetm
.libgcc_shift_count_mode ();
2134 /* Specify unsigned here,
2135 since negative shift counts are meaningless. */
2136 op1x
= convert_to_mode (op1_mode
, op1
, 1);
2139 if (GET_MODE (op0
) != VOIDmode
2140 && GET_MODE (op0
) != mode
)
2141 op0
= convert_to_mode (mode
, op0
, unsignedp
);
2143 /* Pass 1 for NO_QUEUE so we don't lose any increments
2144 if the libcall is cse'd or moved. */
2145 value
= emit_library_call_value (libfunc
,
2146 NULL_RTX
, LCT_CONST
, mode
, 2,
2147 op0
, mode
, op1x
, op1_mode
);
2149 insns
= get_insns ();
2152 target
= gen_reg_rtx (mode
);
2153 emit_libcall_block_1 (insns
, target
, value
,
2154 gen_rtx_fmt_ee (optab_to_code (binoptab
),
2156 trapv_binoptab_p (binoptab
));
2161 delete_insns_since (last
);
2163 /* It can't be done in this mode. Can we do it in a wider mode? */
2165 if (! (methods
== OPTAB_WIDEN
|| methods
== OPTAB_LIB_WIDEN
2166 || methods
== OPTAB_MUST_WIDEN
))
2168 /* Caller says, don't even try. */
2169 delete_insns_since (entry_last
);
2173 /* Compute the value of METHODS to pass to recursive calls.
2174 Don't allow widening to be tried recursively. */
2176 methods
= (methods
== OPTAB_LIB_WIDEN
? OPTAB_LIB
: OPTAB_DIRECT
);
2178 /* Look for a wider mode of the same class for which it appears we can do
2181 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2183 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2184 wider_mode
!= VOIDmode
;
2185 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2187 if (find_widening_optab_handler (binoptab
, wider_mode
, mode
, 1)
2189 || (methods
== OPTAB_LIB
2190 && optab_libfunc (binoptab
, wider_mode
)))
2192 rtx xop0
= op0
, xop1
= op1
;
2195 /* For certain integer operations, we need not actually extend
2196 the narrow operands, as long as we will truncate
2197 the results to the same narrowness. */
2199 if ((binoptab
== ior_optab
|| binoptab
== and_optab
2200 || binoptab
== xor_optab
2201 || binoptab
== add_optab
|| binoptab
== sub_optab
2202 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
2203 && mclass
== MODE_INT
)
2206 xop0
= widen_operand (xop0
, wider_mode
, mode
,
2207 unsignedp
, no_extend
);
2209 /* The second operand of a shift must always be extended. */
2210 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
2211 no_extend
&& binoptab
!= ashl_optab
);
2213 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
2214 unsignedp
, methods
);
2217 if (mclass
!= MODE_INT
2218 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
2221 target
= gen_reg_rtx (mode
);
2222 convert_move (target
, temp
, 0);
2226 return gen_lowpart (mode
, temp
);
2229 delete_insns_since (last
);
2234 delete_insns_since (entry_last
);
2238 /* Expand a binary operator which has both signed and unsigned forms.
2239 UOPTAB is the optab for unsigned operations, and SOPTAB is for
2242 If we widen unsigned operands, we may use a signed wider operation instead
2243 of an unsigned wider operation, since the result would be the same. */
2246 sign_expand_binop (enum machine_mode mode
, optab uoptab
, optab soptab
,
2247 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
2248 enum optab_methods methods
)
2251 optab direct_optab
= unsignedp
? uoptab
: soptab
;
2254 /* Do it without widening, if possible. */
2255 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
,
2256 unsignedp
, OPTAB_DIRECT
);
2257 if (temp
|| methods
== OPTAB_DIRECT
)
2260 /* Try widening to a signed int. Disable any direct use of any
2261 signed insn in the current mode. */
2262 save_enable
= swap_optab_enable (soptab
, mode
, false);
2264 temp
= expand_binop (mode
, soptab
, op0
, op1
, target
,
2265 unsignedp
, OPTAB_WIDEN
);
2267 /* For unsigned operands, try widening to an unsigned int. */
2268 if (!temp
&& unsignedp
)
2269 temp
= expand_binop (mode
, uoptab
, op0
, op1
, target
,
2270 unsignedp
, OPTAB_WIDEN
);
2271 if (temp
|| methods
== OPTAB_WIDEN
)
2274 /* Use the right width libcall if that exists. */
2275 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
,
2276 unsignedp
, OPTAB_LIB
);
2277 if (temp
|| methods
== OPTAB_LIB
)
2280 /* Must widen and use a libcall, use either signed or unsigned. */
2281 temp
= expand_binop (mode
, soptab
, op0
, op1
, target
,
2282 unsignedp
, methods
);
2283 if (!temp
&& unsignedp
)
2284 temp
= expand_binop (mode
, uoptab
, op0
, op1
, target
,
2285 unsignedp
, methods
);
2288 /* Undo the fiddling above. */
2290 swap_optab_enable (soptab
, mode
, true);
2294 /* Generate code to perform an operation specified by UNOPPTAB
2295 on operand OP0, with two results to TARG0 and TARG1.
2296 We assume that the order of the operands for the instruction
2297 is TARG0, TARG1, OP0.
2299 Either TARG0 or TARG1 may be zero, but what that means is that
2300 the result is not actually wanted. We will generate it into
2301 a dummy pseudo-reg and discard it. They may not both be zero.
2303 Returns 1 if this operation can be performed; 0 if not. */
2306 expand_twoval_unop (optab unoptab
, rtx op0
, rtx targ0
, rtx targ1
,
2309 enum machine_mode mode
= GET_MODE (targ0
? targ0
: targ1
);
2310 enum mode_class mclass
;
2311 enum machine_mode wider_mode
;
2312 rtx entry_last
= get_last_insn ();
2315 mclass
= GET_MODE_CLASS (mode
);
2318 targ0
= gen_reg_rtx (mode
);
2320 targ1
= gen_reg_rtx (mode
);
2322 /* Record where to go back to if we fail. */
2323 last
= get_last_insn ();
2325 if (optab_handler (unoptab
, mode
) != CODE_FOR_nothing
)
2327 struct expand_operand ops
[3];
2328 enum insn_code icode
= optab_handler (unoptab
, mode
);
2330 create_fixed_operand (&ops
[0], targ0
);
2331 create_fixed_operand (&ops
[1], targ1
);
2332 create_convert_operand_from (&ops
[2], op0
, mode
, unsignedp
);
2333 if (maybe_expand_insn (icode
, 3, ops
))
2337 /* It can't be done in this mode. Can we do it in a wider mode? */
2339 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2341 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2342 wider_mode
!= VOIDmode
;
2343 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2345 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
2347 rtx t0
= gen_reg_rtx (wider_mode
);
2348 rtx t1
= gen_reg_rtx (wider_mode
);
2349 rtx cop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
2351 if (expand_twoval_unop (unoptab
, cop0
, t0
, t1
, unsignedp
))
2353 convert_move (targ0
, t0
, unsignedp
);
2354 convert_move (targ1
, t1
, unsignedp
);
2358 delete_insns_since (last
);
2363 delete_insns_since (entry_last
);
2367 /* Generate code to perform an operation specified by BINOPTAB
2368 on operands OP0 and OP1, with two results to TARG1 and TARG2.
2369 We assume that the order of the operands for the instruction
2370 is TARG0, OP0, OP1, TARG1, which would fit a pattern like
2371 [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))].
2373 Either TARG0 or TARG1 may be zero, but what that means is that
2374 the result is not actually wanted. We will generate it into
2375 a dummy pseudo-reg and discard it. They may not both be zero.
2377 Returns 1 if this operation can be performed; 0 if not. */
2380 expand_twoval_binop (optab binoptab
, rtx op0
, rtx op1
, rtx targ0
, rtx targ1
,
2383 enum machine_mode mode
= GET_MODE (targ0
? targ0
: targ1
);
2384 enum mode_class mclass
;
2385 enum machine_mode wider_mode
;
2386 rtx entry_last
= get_last_insn ();
2389 mclass
= GET_MODE_CLASS (mode
);
2392 targ0
= gen_reg_rtx (mode
);
2394 targ1
= gen_reg_rtx (mode
);
2396 /* Record where to go back to if we fail. */
2397 last
= get_last_insn ();
2399 if (optab_handler (binoptab
, mode
) != CODE_FOR_nothing
)
2401 struct expand_operand ops
[4];
2402 enum insn_code icode
= optab_handler (binoptab
, mode
);
2403 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
2404 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
2405 rtx xop0
= op0
, xop1
= op1
;
2407 /* If we are optimizing, force expensive constants into a register. */
2408 xop0
= avoid_expensive_constant (mode0
, binoptab
, 0, xop0
, unsignedp
);
2409 xop1
= avoid_expensive_constant (mode1
, binoptab
, 1, xop1
, unsignedp
);
2411 create_fixed_operand (&ops
[0], targ0
);
2412 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
2413 create_convert_operand_from (&ops
[2], op1
, mode
, unsignedp
);
2414 create_fixed_operand (&ops
[3], targ1
);
2415 if (maybe_expand_insn (icode
, 4, ops
))
2417 delete_insns_since (last
);
2420 /* It can't be done in this mode. Can we do it in a wider mode? */
2422 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2424 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2425 wider_mode
!= VOIDmode
;
2426 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2428 if (optab_handler (binoptab
, wider_mode
) != CODE_FOR_nothing
)
2430 rtx t0
= gen_reg_rtx (wider_mode
);
2431 rtx t1
= gen_reg_rtx (wider_mode
);
2432 rtx cop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
2433 rtx cop1
= convert_modes (wider_mode
, mode
, op1
, unsignedp
);
2435 if (expand_twoval_binop (binoptab
, cop0
, cop1
,
2438 convert_move (targ0
, t0
, unsignedp
);
2439 convert_move (targ1
, t1
, unsignedp
);
2443 delete_insns_since (last
);
2448 delete_insns_since (entry_last
);
2452 /* Expand the two-valued library call indicated by BINOPTAB, but
2453 preserve only one of the values. If TARG0 is non-NULL, the first
2454 value is placed into TARG0; otherwise the second value is placed
2455 into TARG1. Exactly one of TARG0 and TARG1 must be non-NULL. The
2456 value stored into TARG0 or TARG1 is equivalent to (CODE OP0 OP1).
2457 This routine assumes that the value returned by the library call is
2458 as if the return value was of an integral mode twice as wide as the
2459 mode of OP0. Returns 1 if the call was successful. */
2462 expand_twoval_binop_libfunc (optab binoptab
, rtx op0
, rtx op1
,
2463 rtx targ0
, rtx targ1
, enum rtx_code code
)
2465 enum machine_mode mode
;
2466 enum machine_mode libval_mode
;
2471 /* Exactly one of TARG0 or TARG1 should be non-NULL. */
2472 gcc_assert (!targ0
!= !targ1
);
2474 mode
= GET_MODE (op0
);
2475 libfunc
= optab_libfunc (binoptab
, mode
);
2479 /* The value returned by the library function will have twice as
2480 many bits as the nominal MODE. */
2481 libval_mode
= smallest_mode_for_size (2 * GET_MODE_BITSIZE (mode
),
2484 libval
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
2488 /* Get the part of VAL containing the value that we want. */
2489 libval
= simplify_gen_subreg (mode
, libval
, libval_mode
,
2490 targ0
? 0 : GET_MODE_SIZE (mode
));
2491 insns
= get_insns ();
2493 /* Move the into the desired location. */
2494 emit_libcall_block (insns
, targ0
? targ0
: targ1
, libval
,
2495 gen_rtx_fmt_ee (code
, mode
, op0
, op1
));
2501 /* Wrapper around expand_unop which takes an rtx code to specify
2502 the operation to perform, not an optab pointer. All other
2503 arguments are the same. */
2505 expand_simple_unop (enum machine_mode mode
, enum rtx_code code
, rtx op0
,
2506 rtx target
, int unsignedp
)
2508 optab unop
= code_to_optab (code
);
2511 return expand_unop (mode
, unop
, op0
, target
, unsignedp
);
2517 (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)).
2519 A similar operation can be used for clrsb. UNOPTAB says which operation
2520 we are trying to expand. */
2522 widen_leading (enum machine_mode mode
, rtx op0
, rtx target
, optab unoptab
)
2524 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2525 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2527 enum machine_mode wider_mode
;
2528 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2529 wider_mode
!= VOIDmode
;
2530 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2532 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
2534 rtx xop0
, temp
, last
;
2536 last
= get_last_insn ();
2539 target
= gen_reg_rtx (mode
);
2540 xop0
= widen_operand (op0
, wider_mode
, mode
,
2541 unoptab
!= clrsb_optab
, false);
2542 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
2543 unoptab
!= clrsb_optab
);
2546 (wider_mode
, sub_optab
, temp
,
2547 gen_int_mode (GET_MODE_PRECISION (wider_mode
)
2548 - GET_MODE_PRECISION (mode
),
2550 target
, true, OPTAB_DIRECT
);
2552 delete_insns_since (last
);
2561 /* Try calculating clz of a double-word quantity as two clz's of word-sized
2562 quantities, choosing which based on whether the high word is nonzero. */
2564 expand_doubleword_clz (enum machine_mode mode
, rtx op0
, rtx target
)
2566 rtx xop0
= force_reg (mode
, op0
);
2567 rtx subhi
= gen_highpart (word_mode
, xop0
);
2568 rtx sublo
= gen_lowpart (word_mode
, xop0
);
2569 rtx hi0_label
= gen_label_rtx ();
2570 rtx after_label
= gen_label_rtx ();
2571 rtx seq
, temp
, result
;
2573 /* If we were not given a target, use a word_mode register, not a
2574 'mode' register. The result will fit, and nobody is expecting
2575 anything bigger (the return type of __builtin_clz* is int). */
2577 target
= gen_reg_rtx (word_mode
);
2579 /* In any case, write to a word_mode scratch in both branches of the
2580 conditional, so we can ensure there is a single move insn setting
2581 'target' to tag a REG_EQUAL note on. */
2582 result
= gen_reg_rtx (word_mode
);
2586 /* If the high word is not equal to zero,
2587 then clz of the full value is clz of the high word. */
2588 emit_cmp_and_jump_insns (subhi
, CONST0_RTX (word_mode
), EQ
, 0,
2589 word_mode
, true, hi0_label
);
2591 temp
= expand_unop_direct (word_mode
, clz_optab
, subhi
, result
, true);
2596 convert_move (result
, temp
, true);
2598 emit_jump_insn (gen_jump (after_label
));
2601 /* Else clz of the full value is clz of the low word plus the number
2602 of bits in the high word. */
2603 emit_label (hi0_label
);
2605 temp
= expand_unop_direct (word_mode
, clz_optab
, sublo
, 0, true);
2608 temp
= expand_binop (word_mode
, add_optab
, temp
,
2609 gen_int_mode (GET_MODE_BITSIZE (word_mode
), word_mode
),
2610 result
, true, OPTAB_DIRECT
);
2614 convert_move (result
, temp
, true);
2616 emit_label (after_label
);
2617 convert_move (target
, result
, true);
2622 add_equal_note (seq
, target
, CLZ
, xop0
, 0);
2634 (lshiftrt:wide (bswap:wide x) ((width wide) - (width narrow))). */
2636 widen_bswap (enum machine_mode mode
, rtx op0
, rtx target
)
2638 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2639 enum machine_mode wider_mode
;
2642 if (!CLASS_HAS_WIDER_MODES_P (mclass
))
2645 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2646 wider_mode
!= VOIDmode
;
2647 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2648 if (optab_handler (bswap_optab
, wider_mode
) != CODE_FOR_nothing
)
2653 last
= get_last_insn ();
2655 x
= widen_operand (op0
, wider_mode
, mode
, true, true);
2656 x
= expand_unop (wider_mode
, bswap_optab
, x
, NULL_RTX
, true);
2658 gcc_assert (GET_MODE_PRECISION (wider_mode
) == GET_MODE_BITSIZE (wider_mode
)
2659 && GET_MODE_PRECISION (mode
) == GET_MODE_BITSIZE (mode
));
2661 x
= expand_shift (RSHIFT_EXPR
, wider_mode
, x
,
2662 GET_MODE_BITSIZE (wider_mode
)
2663 - GET_MODE_BITSIZE (mode
),
2669 target
= gen_reg_rtx (mode
);
2670 emit_move_insn (target
, gen_lowpart (mode
, x
));
2673 delete_insns_since (last
);
2678 /* Try calculating bswap as two bswaps of two word-sized operands. */
2681 expand_doubleword_bswap (enum machine_mode mode
, rtx op
, rtx target
)
2685 t1
= expand_unop (word_mode
, bswap_optab
,
2686 operand_subword_force (op
, 0, mode
), NULL_RTX
, true);
2687 t0
= expand_unop (word_mode
, bswap_optab
,
2688 operand_subword_force (op
, 1, mode
), NULL_RTX
, true);
2690 if (target
== 0 || !valid_multiword_target_p (target
))
2691 target
= gen_reg_rtx (mode
);
2693 emit_clobber (target
);
2694 emit_move_insn (operand_subword (target
, 0, 1, mode
), t0
);
2695 emit_move_insn (operand_subword (target
, 1, 1, mode
), t1
);
2700 /* Try calculating (parity x) as (and (popcount x) 1), where
2701 popcount can also be done in a wider mode. */
2703 expand_parity (enum machine_mode mode
, rtx op0
, rtx target
)
2705 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2706 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2708 enum machine_mode wider_mode
;
2709 for (wider_mode
= mode
; wider_mode
!= VOIDmode
;
2710 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2712 if (optab_handler (popcount_optab
, wider_mode
) != CODE_FOR_nothing
)
2714 rtx xop0
, temp
, last
;
2716 last
= get_last_insn ();
2719 target
= gen_reg_rtx (mode
);
2720 xop0
= widen_operand (op0
, wider_mode
, mode
, true, false);
2721 temp
= expand_unop (wider_mode
, popcount_optab
, xop0
, NULL_RTX
,
2724 temp
= expand_binop (wider_mode
, and_optab
, temp
, const1_rtx
,
2725 target
, true, OPTAB_DIRECT
);
2727 delete_insns_since (last
);
2736 /* Try calculating ctz(x) as K - clz(x & -x) ,
2737 where K is GET_MODE_PRECISION(mode) - 1.
2739 Both __builtin_ctz and __builtin_clz are undefined at zero, so we
2740 don't have to worry about what the hardware does in that case. (If
2741 the clz instruction produces the usual value at 0, which is K, the
2742 result of this code sequence will be -1; expand_ffs, below, relies
2743 on this. It might be nice to have it be K instead, for consistency
2744 with the (very few) processors that provide a ctz with a defined
2745 value, but that would take one more instruction, and it would be
2746 less convenient for expand_ffs anyway. */
2749 expand_ctz (enum machine_mode mode
, rtx op0
, rtx target
)
2753 if (optab_handler (clz_optab
, mode
) == CODE_FOR_nothing
)
2758 temp
= expand_unop_direct (mode
, neg_optab
, op0
, NULL_RTX
, true);
2760 temp
= expand_binop (mode
, and_optab
, op0
, temp
, NULL_RTX
,
2761 true, OPTAB_DIRECT
);
2763 temp
= expand_unop_direct (mode
, clz_optab
, temp
, NULL_RTX
, true);
2765 temp
= expand_binop (mode
, sub_optab
,
2766 gen_int_mode (GET_MODE_PRECISION (mode
) - 1, mode
),
2768 true, OPTAB_DIRECT
);
2778 add_equal_note (seq
, temp
, CTZ
, op0
, 0);
2784 /* Try calculating ffs(x) using ctz(x) if we have that instruction, or
2785 else with the sequence used by expand_clz.
2787 The ffs builtin promises to return zero for a zero value and ctz/clz
2788 may have an undefined value in that case. If they do not give us a
2789 convenient value, we have to generate a test and branch. */
2791 expand_ffs (enum machine_mode mode
, rtx op0
, rtx target
)
2793 HOST_WIDE_INT val
= 0;
2794 bool defined_at_zero
= false;
2797 if (optab_handler (ctz_optab
, mode
) != CODE_FOR_nothing
)
2801 temp
= expand_unop_direct (mode
, ctz_optab
, op0
, 0, true);
2805 defined_at_zero
= (CTZ_DEFINED_VALUE_AT_ZERO (mode
, val
) == 2);
2807 else if (optab_handler (clz_optab
, mode
) != CODE_FOR_nothing
)
2810 temp
= expand_ctz (mode
, op0
, 0);
2814 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, val
) == 2)
2816 defined_at_zero
= true;
2817 val
= (GET_MODE_PRECISION (mode
) - 1) - val
;
2823 if (defined_at_zero
&& val
== -1)
2824 /* No correction needed at zero. */;
2827 /* We don't try to do anything clever with the situation found
2828 on some processors (eg Alpha) where ctz(0:mode) ==
2829 bitsize(mode). If someone can think of a way to send N to -1
2830 and leave alone all values in the range 0..N-1 (where N is a
2831 power of two), cheaper than this test-and-branch, please add it.
2833 The test-and-branch is done after the operation itself, in case
2834 the operation sets condition codes that can be recycled for this.
2835 (This is true on i386, for instance.) */
2837 rtx nonzero_label
= gen_label_rtx ();
2838 emit_cmp_and_jump_insns (op0
, CONST0_RTX (mode
), NE
, 0,
2839 mode
, true, nonzero_label
);
2841 convert_move (temp
, GEN_INT (-1), false);
2842 emit_label (nonzero_label
);
2845 /* temp now has a value in the range -1..bitsize-1. ffs is supposed
2846 to produce a value in the range 0..bitsize. */
2847 temp
= expand_binop (mode
, add_optab
, temp
, gen_int_mode (1, mode
),
2848 target
, false, OPTAB_DIRECT
);
2855 add_equal_note (seq
, temp
, FFS
, op0
, 0);
2864 /* Extract the OMODE lowpart from VAL, which has IMODE. Under certain
2865 conditions, VAL may already be a SUBREG against which we cannot generate
2866 a further SUBREG. In this case, we expect forcing the value into a
2867 register will work around the situation. */
2870 lowpart_subreg_maybe_copy (enum machine_mode omode
, rtx val
,
2871 enum machine_mode imode
)
2874 ret
= lowpart_subreg (omode
, val
, imode
);
2877 val
= force_reg (imode
, val
);
2878 ret
= lowpart_subreg (omode
, val
, imode
);
2879 gcc_assert (ret
!= NULL
);
2884 /* Expand a floating point absolute value or negation operation via a
2885 logical operation on the sign bit. */
2888 expand_absneg_bit (enum rtx_code code
, enum machine_mode mode
,
2889 rtx op0
, rtx target
)
2891 const struct real_format
*fmt
;
2892 int bitpos
, word
, nwords
, i
;
2893 enum machine_mode imode
;
2897 /* The format has to have a simple sign bit. */
2898 fmt
= REAL_MODE_FORMAT (mode
);
2902 bitpos
= fmt
->signbit_rw
;
2906 /* Don't create negative zeros if the format doesn't support them. */
2907 if (code
== NEG
&& !fmt
->has_signed_zero
)
2910 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
2912 imode
= int_mode_for_mode (mode
);
2913 if (imode
== BLKmode
)
2922 if (FLOAT_WORDS_BIG_ENDIAN
)
2923 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
2925 word
= bitpos
/ BITS_PER_WORD
;
2926 bitpos
= bitpos
% BITS_PER_WORD
;
2927 nwords
= (GET_MODE_BITSIZE (mode
) + BITS_PER_WORD
- 1) / BITS_PER_WORD
;
2930 mask
= double_int_zero
.set_bit (bitpos
);
2936 || (nwords
> 1 && !valid_multiword_target_p (target
)))
2937 target
= gen_reg_rtx (mode
);
2943 for (i
= 0; i
< nwords
; ++i
)
2945 rtx targ_piece
= operand_subword (target
, i
, 1, mode
);
2946 rtx op0_piece
= operand_subword_force (op0
, i
, mode
);
2950 temp
= expand_binop (imode
, code
== ABS
? and_optab
: xor_optab
,
2952 immed_double_int_const (mask
, imode
),
2953 targ_piece
, 1, OPTAB_LIB_WIDEN
);
2954 if (temp
!= targ_piece
)
2955 emit_move_insn (targ_piece
, temp
);
2958 emit_move_insn (targ_piece
, op0_piece
);
2961 insns
= get_insns ();
2968 temp
= expand_binop (imode
, code
== ABS
? and_optab
: xor_optab
,
2969 gen_lowpart (imode
, op0
),
2970 immed_double_int_const (mask
, imode
),
2971 gen_lowpart (imode
, target
), 1, OPTAB_LIB_WIDEN
);
2972 target
= lowpart_subreg_maybe_copy (mode
, temp
, imode
);
2974 set_dst_reg_note (get_last_insn (), REG_EQUAL
,
2975 gen_rtx_fmt_e (code
, mode
, copy_rtx (op0
)),
2982 /* As expand_unop, but will fail rather than attempt the operation in a
2983 different mode or with a libcall. */
2985 expand_unop_direct (enum machine_mode mode
, optab unoptab
, rtx op0
, rtx target
,
2988 if (optab_handler (unoptab
, mode
) != CODE_FOR_nothing
)
2990 struct expand_operand ops
[2];
2991 enum insn_code icode
= optab_handler (unoptab
, mode
);
2992 rtx last
= get_last_insn ();
2995 create_output_operand (&ops
[0], target
, mode
);
2996 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
2997 pat
= maybe_gen_insn (icode
, 2, ops
);
3000 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
3001 && ! add_equal_note (pat
, ops
[0].value
, optab_to_code (unoptab
),
3002 ops
[1].value
, NULL_RTX
))
3004 delete_insns_since (last
);
3005 return expand_unop (mode
, unoptab
, op0
, NULL_RTX
, unsignedp
);
3010 return ops
[0].value
;
3016 /* Generate code to perform an operation specified by UNOPTAB
3017 on operand OP0, with result having machine-mode MODE.
3019 UNSIGNEDP is for the case where we have to widen the operands
3020 to perform the operation. It says to use zero-extension.
3022 If TARGET is nonzero, the value
3023 is generated there, if it is convenient to do so.
3024 In all cases an rtx is returned for the locus of the value;
3025 this may or may not be TARGET. */
3028 expand_unop (enum machine_mode mode
, optab unoptab
, rtx op0
, rtx target
,
3031 enum mode_class mclass
= GET_MODE_CLASS (mode
);
3032 enum machine_mode wider_mode
;
3036 temp
= expand_unop_direct (mode
, unoptab
, op0
, target
, unsignedp
);
3040 /* It can't be done in this mode. Can we open-code it in a wider mode? */
3042 /* Widening (or narrowing) clz needs special treatment. */
3043 if (unoptab
== clz_optab
)
3045 temp
= widen_leading (mode
, op0
, target
, unoptab
);
3049 if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
3050 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
3052 temp
= expand_doubleword_clz (mode
, op0
, target
);
3060 if (unoptab
== clrsb_optab
)
3062 temp
= widen_leading (mode
, op0
, target
, unoptab
);
3068 /* Widening (or narrowing) bswap needs special treatment. */
3069 if (unoptab
== bswap_optab
)
3071 /* HImode is special because in this mode BSWAP is equivalent to ROTATE
3072 or ROTATERT. First try these directly; if this fails, then try the
3073 obvious pair of shifts with allowed widening, as this will probably
3074 be always more efficient than the other fallback methods. */
3077 rtx last
, temp1
, temp2
;
3079 if (optab_handler (rotl_optab
, mode
) != CODE_FOR_nothing
)
3081 temp
= expand_binop (mode
, rotl_optab
, op0
, GEN_INT (8), target
,
3082 unsignedp
, OPTAB_DIRECT
);
3087 if (optab_handler (rotr_optab
, mode
) != CODE_FOR_nothing
)
3089 temp
= expand_binop (mode
, rotr_optab
, op0
, GEN_INT (8), target
,
3090 unsignedp
, OPTAB_DIRECT
);
3095 last
= get_last_insn ();
3097 temp1
= expand_binop (mode
, ashl_optab
, op0
, GEN_INT (8), NULL_RTX
,
3098 unsignedp
, OPTAB_WIDEN
);
3099 temp2
= expand_binop (mode
, lshr_optab
, op0
, GEN_INT (8), NULL_RTX
,
3100 unsignedp
, OPTAB_WIDEN
);
3103 temp
= expand_binop (mode
, ior_optab
, temp1
, temp2
, target
,
3104 unsignedp
, OPTAB_WIDEN
);
3109 delete_insns_since (last
);
3112 temp
= widen_bswap (mode
, op0
, target
);
3116 if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
3117 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
3119 temp
= expand_doubleword_bswap (mode
, op0
, target
);
3127 if (CLASS_HAS_WIDER_MODES_P (mclass
))
3128 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
3129 wider_mode
!= VOIDmode
;
3130 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
3132 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
3135 rtx last
= get_last_insn ();
3137 /* For certain operations, we need not actually extend
3138 the narrow operand, as long as we will truncate the
3139 results to the same narrowness. */
3141 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
3142 (unoptab
== neg_optab
3143 || unoptab
== one_cmpl_optab
)
3144 && mclass
== MODE_INT
);
3146 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
3151 if (mclass
!= MODE_INT
3152 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
3155 target
= gen_reg_rtx (mode
);
3156 convert_move (target
, temp
, 0);
3160 return gen_lowpart (mode
, temp
);
3163 delete_insns_since (last
);
3167 /* These can be done a word at a time. */
3168 if (unoptab
== one_cmpl_optab
3169 && mclass
== MODE_INT
3170 && GET_MODE_SIZE (mode
) > UNITS_PER_WORD
3171 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
3176 if (target
== 0 || target
== op0
|| !valid_multiword_target_p (target
))
3177 target
= gen_reg_rtx (mode
);
3181 /* Do the actual arithmetic. */
3182 for (i
= 0; i
< GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
; i
++)
3184 rtx target_piece
= operand_subword (target
, i
, 1, mode
);
3185 rtx x
= expand_unop (word_mode
, unoptab
,
3186 operand_subword_force (op0
, i
, mode
),
3187 target_piece
, unsignedp
);
3189 if (target_piece
!= x
)
3190 emit_move_insn (target_piece
, x
);
3193 insns
= get_insns ();
3200 if (optab_to_code (unoptab
) == NEG
)
3202 /* Try negating floating point values by flipping the sign bit. */
3203 if (SCALAR_FLOAT_MODE_P (mode
))
3205 temp
= expand_absneg_bit (NEG
, mode
, op0
, target
);
3210 /* If there is no negation pattern, and we have no negative zero,
3211 try subtracting from zero. */
3212 if (!HONOR_SIGNED_ZEROS (mode
))
3214 temp
= expand_binop (mode
, (unoptab
== negv_optab
3215 ? subv_optab
: sub_optab
),
3216 CONST0_RTX (mode
), op0
, target
,
3217 unsignedp
, OPTAB_DIRECT
);
3223 /* Try calculating parity (x) as popcount (x) % 2. */
3224 if (unoptab
== parity_optab
)
3226 temp
= expand_parity (mode
, op0
, target
);
3231 /* Try implementing ffs (x) in terms of clz (x). */
3232 if (unoptab
== ffs_optab
)
3234 temp
= expand_ffs (mode
, op0
, target
);
3239 /* Try implementing ctz (x) in terms of clz (x). */
3240 if (unoptab
== ctz_optab
)
3242 temp
= expand_ctz (mode
, op0
, target
);
3248 /* Now try a library call in this mode. */
3249 libfunc
= optab_libfunc (unoptab
, mode
);
3255 enum machine_mode outmode
= mode
;
3257 /* All of these functions return small values. Thus we choose to
3258 have them return something that isn't a double-word. */
3259 if (unoptab
== ffs_optab
|| unoptab
== clz_optab
|| unoptab
== ctz_optab
3260 || unoptab
== clrsb_optab
|| unoptab
== popcount_optab
3261 || unoptab
== parity_optab
)
3263 = GET_MODE (hard_libcall_value (TYPE_MODE (integer_type_node
),
3264 optab_libfunc (unoptab
, mode
)));
3268 /* Pass 1 for NO_QUEUE so we don't lose any increments
3269 if the libcall is cse'd or moved. */
3270 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
, outmode
,
3272 insns
= get_insns ();
3275 target
= gen_reg_rtx (outmode
);
3276 eq_value
= gen_rtx_fmt_e (optab_to_code (unoptab
), mode
, op0
);
3277 if (GET_MODE_SIZE (outmode
) < GET_MODE_SIZE (mode
))
3278 eq_value
= simplify_gen_unary (TRUNCATE
, outmode
, eq_value
, mode
);
3279 else if (GET_MODE_SIZE (outmode
) > GET_MODE_SIZE (mode
))
3280 eq_value
= simplify_gen_unary (ZERO_EXTEND
, outmode
, eq_value
, mode
);
3281 emit_libcall_block_1 (insns
, target
, value
, eq_value
,
3282 trapv_unoptab_p (unoptab
));
3287 /* It can't be done in this mode. Can we do it in a wider mode? */
3289 if (CLASS_HAS_WIDER_MODES_P (mclass
))
3291 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
3292 wider_mode
!= VOIDmode
;
3293 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
3295 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
3296 || optab_libfunc (unoptab
, wider_mode
))
3299 rtx last
= get_last_insn ();
3301 /* For certain operations, we need not actually extend
3302 the narrow operand, as long as we will truncate the
3303 results to the same narrowness. */
3304 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
3305 (unoptab
== neg_optab
3306 || unoptab
== one_cmpl_optab
3307 || unoptab
== bswap_optab
)
3308 && mclass
== MODE_INT
);
3310 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
3313 /* If we are generating clz using wider mode, adjust the
3314 result. Similarly for clrsb. */
3315 if ((unoptab
== clz_optab
|| unoptab
== clrsb_optab
)
3318 (wider_mode
, sub_optab
, temp
,
3319 gen_int_mode (GET_MODE_PRECISION (wider_mode
)
3320 - GET_MODE_PRECISION (mode
),
3322 target
, true, OPTAB_DIRECT
);
3324 /* Likewise for bswap. */
3325 if (unoptab
== bswap_optab
&& temp
!= 0)
3327 gcc_assert (GET_MODE_PRECISION (wider_mode
)
3328 == GET_MODE_BITSIZE (wider_mode
)
3329 && GET_MODE_PRECISION (mode
)
3330 == GET_MODE_BITSIZE (mode
));
3332 temp
= expand_shift (RSHIFT_EXPR
, wider_mode
, temp
,
3333 GET_MODE_BITSIZE (wider_mode
)
3334 - GET_MODE_BITSIZE (mode
),
3340 if (mclass
!= MODE_INT
)
3343 target
= gen_reg_rtx (mode
);
3344 convert_move (target
, temp
, 0);
3348 return gen_lowpart (mode
, temp
);
3351 delete_insns_since (last
);
3356 /* One final attempt at implementing negation via subtraction,
3357 this time allowing widening of the operand. */
3358 if (optab_to_code (unoptab
) == NEG
&& !HONOR_SIGNED_ZEROS (mode
))
3361 temp
= expand_binop (mode
,
3362 unoptab
== negv_optab
? subv_optab
: sub_optab
,
3363 CONST0_RTX (mode
), op0
,
3364 target
, unsignedp
, OPTAB_LIB_WIDEN
);
3372 /* Emit code to compute the absolute value of OP0, with result to
3373 TARGET if convenient. (TARGET may be 0.) The return value says
3374 where the result actually is to be found.
3376 MODE is the mode of the operand; the mode of the result is
3377 different but can be deduced from MODE.
3382 expand_abs_nojump (enum machine_mode mode
, rtx op0
, rtx target
,
3383 int result_unsignedp
)
3388 result_unsignedp
= 1;
3390 /* First try to do it with a special abs instruction. */
3391 temp
= expand_unop (mode
, result_unsignedp
? abs_optab
: absv_optab
,
3396 /* For floating point modes, try clearing the sign bit. */
3397 if (SCALAR_FLOAT_MODE_P (mode
))
3399 temp
= expand_absneg_bit (ABS
, mode
, op0
, target
);
3404 /* If we have a MAX insn, we can do this as MAX (x, -x). */
3405 if (optab_handler (smax_optab
, mode
) != CODE_FOR_nothing
3406 && !HONOR_SIGNED_ZEROS (mode
))
3408 rtx last
= get_last_insn ();
3410 temp
= expand_unop (mode
, neg_optab
, op0
, NULL_RTX
, 0);
3412 temp
= expand_binop (mode
, smax_optab
, op0
, temp
, target
, 0,
3418 delete_insns_since (last
);
3421 /* If this machine has expensive jumps, we can do integer absolute
3422 value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)),
3423 where W is the width of MODE. */
3425 if (GET_MODE_CLASS (mode
) == MODE_INT
3426 && BRANCH_COST (optimize_insn_for_speed_p (),
3429 rtx extended
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3430 GET_MODE_PRECISION (mode
) - 1,
3433 temp
= expand_binop (mode
, xor_optab
, extended
, op0
, target
, 0,
3436 temp
= expand_binop (mode
, result_unsignedp
? sub_optab
: subv_optab
,
3437 temp
, extended
, target
, 0, OPTAB_LIB_WIDEN
);
3447 expand_abs (enum machine_mode mode
, rtx op0
, rtx target
,
3448 int result_unsignedp
, int safe
)
3453 result_unsignedp
= 1;
3455 temp
= expand_abs_nojump (mode
, op0
, target
, result_unsignedp
);
3459 /* If that does not win, use conditional jump and negate. */
3461 /* It is safe to use the target if it is the same
3462 as the source if this is also a pseudo register */
3463 if (op0
== target
&& REG_P (op0
)
3464 && REGNO (op0
) >= FIRST_PSEUDO_REGISTER
)
3467 op1
= gen_label_rtx ();
3468 if (target
== 0 || ! safe
3469 || GET_MODE (target
) != mode
3470 || (MEM_P (target
) && MEM_VOLATILE_P (target
))
3472 && REGNO (target
) < FIRST_PSEUDO_REGISTER
))
3473 target
= gen_reg_rtx (mode
);
3475 emit_move_insn (target
, op0
);
3478 do_compare_rtx_and_jump (target
, CONST0_RTX (mode
), GE
, 0, mode
,
3479 NULL_RTX
, NULL_RTX
, op1
, -1);
3481 op0
= expand_unop (mode
, result_unsignedp
? neg_optab
: negv_optab
,
3484 emit_move_insn (target
, op0
);
3490 /* Emit code to compute the one's complement absolute value of OP0
3491 (if (OP0 < 0) OP0 = ~OP0), with result to TARGET if convenient.
3492 (TARGET may be NULL_RTX.) The return value says where the result
3493 actually is to be found.
3495 MODE is the mode of the operand; the mode of the result is
3496 different but can be deduced from MODE. */
3499 expand_one_cmpl_abs_nojump (enum machine_mode mode
, rtx op0
, rtx target
)
3503 /* Not applicable for floating point modes. */
3504 if (FLOAT_MODE_P (mode
))
3507 /* If we have a MAX insn, we can do this as MAX (x, ~x). */
3508 if (optab_handler (smax_optab
, mode
) != CODE_FOR_nothing
)
3510 rtx last
= get_last_insn ();
3512 temp
= expand_unop (mode
, one_cmpl_optab
, op0
, NULL_RTX
, 0);
3514 temp
= expand_binop (mode
, smax_optab
, op0
, temp
, target
, 0,
3520 delete_insns_since (last
);
3523 /* If this machine has expensive jumps, we can do one's complement
3524 absolute value of X as (((signed) x >> (W-1)) ^ x). */
3526 if (GET_MODE_CLASS (mode
) == MODE_INT
3527 && BRANCH_COST (optimize_insn_for_speed_p (),
3530 rtx extended
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3531 GET_MODE_PRECISION (mode
) - 1,
3534 temp
= expand_binop (mode
, xor_optab
, extended
, op0
, target
, 0,
3544 /* A subroutine of expand_copysign, perform the copysign operation using the
3545 abs and neg primitives advertised to exist on the target. The assumption
3546 is that we have a split register file, and leaving op0 in fp registers,
3547 and not playing with subregs so much, will help the register allocator. */
3550 expand_copysign_absneg (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3551 int bitpos
, bool op0_is_abs
)
3553 enum machine_mode imode
;
3554 enum insn_code icode
;
3560 /* Check if the back end provides an insn that handles signbit for the
3562 icode
= optab_handler (signbit_optab
, mode
);
3563 if (icode
!= CODE_FOR_nothing
)
3565 imode
= insn_data
[(int) icode
].operand
[0].mode
;
3566 sign
= gen_reg_rtx (imode
);
3567 emit_unop_insn (icode
, sign
, op1
, UNKNOWN
);
3573 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
3575 imode
= int_mode_for_mode (mode
);
3576 if (imode
== BLKmode
)
3578 op1
= gen_lowpart (imode
, op1
);
3585 if (FLOAT_WORDS_BIG_ENDIAN
)
3586 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
3588 word
= bitpos
/ BITS_PER_WORD
;
3589 bitpos
= bitpos
% BITS_PER_WORD
;
3590 op1
= operand_subword_force (op1
, word
, mode
);
3593 mask
= double_int_zero
.set_bit (bitpos
);
3595 sign
= expand_binop (imode
, and_optab
, op1
,
3596 immed_double_int_const (mask
, imode
),
3597 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3602 op0
= expand_unop (mode
, abs_optab
, op0
, target
, 0);
3609 if (target
== NULL_RTX
)
3610 target
= copy_to_reg (op0
);
3612 emit_move_insn (target
, op0
);
3615 label
= gen_label_rtx ();
3616 emit_cmp_and_jump_insns (sign
, const0_rtx
, EQ
, NULL_RTX
, imode
, 1, label
);
3618 if (CONST_DOUBLE_AS_FLOAT_P (op0
))
3619 op0
= simplify_unary_operation (NEG
, mode
, op0
, mode
);
3621 op0
= expand_unop (mode
, neg_optab
, op0
, target
, 0);
3623 emit_move_insn (target
, op0
);
3631 /* A subroutine of expand_copysign, perform the entire copysign operation
3632 with integer bitmasks. BITPOS is the position of the sign bit; OP0_IS_ABS
3633 is true if op0 is known to have its sign bit clear. */
3636 expand_copysign_bit (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3637 int bitpos
, bool op0_is_abs
)
3639 enum machine_mode imode
;
3641 int word
, nwords
, i
;
3644 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
3646 imode
= int_mode_for_mode (mode
);
3647 if (imode
== BLKmode
)
3656 if (FLOAT_WORDS_BIG_ENDIAN
)
3657 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
3659 word
= bitpos
/ BITS_PER_WORD
;
3660 bitpos
= bitpos
% BITS_PER_WORD
;
3661 nwords
= (GET_MODE_BITSIZE (mode
) + BITS_PER_WORD
- 1) / BITS_PER_WORD
;
3664 mask
= double_int_zero
.set_bit (bitpos
);
3669 || (nwords
> 1 && !valid_multiword_target_p (target
)))
3670 target
= gen_reg_rtx (mode
);
3676 for (i
= 0; i
< nwords
; ++i
)
3678 rtx targ_piece
= operand_subword (target
, i
, 1, mode
);
3679 rtx op0_piece
= operand_subword_force (op0
, i
, mode
);
3685 = expand_binop (imode
, and_optab
, op0_piece
,
3686 immed_double_int_const (~mask
, imode
),
3687 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3689 op1
= expand_binop (imode
, and_optab
,
3690 operand_subword_force (op1
, i
, mode
),
3691 immed_double_int_const (mask
, imode
),
3692 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3694 temp
= expand_binop (imode
, ior_optab
, op0_piece
, op1
,
3695 targ_piece
, 1, OPTAB_LIB_WIDEN
);
3696 if (temp
!= targ_piece
)
3697 emit_move_insn (targ_piece
, temp
);
3700 emit_move_insn (targ_piece
, op0_piece
);
3703 insns
= get_insns ();
3710 op1
= expand_binop (imode
, and_optab
, gen_lowpart (imode
, op1
),
3711 immed_double_int_const (mask
, imode
),
3712 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3714 op0
= gen_lowpart (imode
, op0
);
3716 op0
= expand_binop (imode
, and_optab
, op0
,
3717 immed_double_int_const (~mask
, imode
),
3718 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3720 temp
= expand_binop (imode
, ior_optab
, op0
, op1
,
3721 gen_lowpart (imode
, target
), 1, OPTAB_LIB_WIDEN
);
3722 target
= lowpart_subreg_maybe_copy (mode
, temp
, imode
);
3728 /* Expand the C99 copysign operation. OP0 and OP1 must be the same
3729 scalar floating point mode. Return NULL if we do not know how to
3730 expand the operation inline. */
3733 expand_copysign (rtx op0
, rtx op1
, rtx target
)
3735 enum machine_mode mode
= GET_MODE (op0
);
3736 const struct real_format
*fmt
;
3740 gcc_assert (SCALAR_FLOAT_MODE_P (mode
));
3741 gcc_assert (GET_MODE (op1
) == mode
);
3743 /* First try to do it with a special instruction. */
3744 temp
= expand_binop (mode
, copysign_optab
, op0
, op1
,
3745 target
, 0, OPTAB_DIRECT
);
3749 fmt
= REAL_MODE_FORMAT (mode
);
3750 if (fmt
== NULL
|| !fmt
->has_signed_zero
)
3754 if (CONST_DOUBLE_AS_FLOAT_P (op0
))
3756 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0
)))
3757 op0
= simplify_unary_operation (ABS
, mode
, op0
, mode
);
3761 if (fmt
->signbit_ro
>= 0
3762 && (CONST_DOUBLE_AS_FLOAT_P (op0
)
3763 || (optab_handler (neg_optab
, mode
) != CODE_FOR_nothing
3764 && optab_handler (abs_optab
, mode
) != CODE_FOR_nothing
)))
3766 temp
= expand_copysign_absneg (mode
, op0
, op1
, target
,
3767 fmt
->signbit_ro
, op0_is_abs
);
3772 if (fmt
->signbit_rw
< 0)
3774 return expand_copysign_bit (mode
, op0
, op1
, target
,
3775 fmt
->signbit_rw
, op0_is_abs
);
3778 /* Generate an instruction whose insn-code is INSN_CODE,
3779 with two operands: an output TARGET and an input OP0.
3780 TARGET *must* be nonzero, and the output is always stored there.
3781 CODE is an rtx code such that (CODE OP0) is an rtx that describes
3782 the value that is stored into TARGET.
3784 Return false if expansion failed. */
3787 maybe_emit_unop_insn (enum insn_code icode
, rtx target
, rtx op0
,
3790 struct expand_operand ops
[2];
3793 create_output_operand (&ops
[0], target
, GET_MODE (target
));
3794 create_input_operand (&ops
[1], op0
, GET_MODE (op0
));
3795 pat
= maybe_gen_insn (icode
, 2, ops
);
3799 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
&& code
!= UNKNOWN
)
3800 add_equal_note (pat
, ops
[0].value
, code
, ops
[1].value
, NULL_RTX
);
3804 if (ops
[0].value
!= target
)
3805 emit_move_insn (target
, ops
[0].value
);
3808 /* Generate an instruction whose insn-code is INSN_CODE,
3809 with two operands: an output TARGET and an input OP0.
3810 TARGET *must* be nonzero, and the output is always stored there.
3811 CODE is an rtx code such that (CODE OP0) is an rtx that describes
3812 the value that is stored into TARGET. */
3815 emit_unop_insn (enum insn_code icode
, rtx target
, rtx op0
, enum rtx_code code
)
3817 bool ok
= maybe_emit_unop_insn (icode
, target
, op0
, code
);
3821 struct no_conflict_data
3823 rtx target
, first
, insn
;
3827 /* Called via note_stores by emit_libcall_block. Set P->must_stay if
3828 the currently examined clobber / store has to stay in the list of
3829 insns that constitute the actual libcall block. */
3831 no_conflict_move_test (rtx dest
, const_rtx set
, void *p0
)
3833 struct no_conflict_data
*p
= (struct no_conflict_data
*) p0
;
3835 /* If this inns directly contributes to setting the target, it must stay. */
3836 if (reg_overlap_mentioned_p (p
->target
, dest
))
3837 p
->must_stay
= true;
3838 /* If we haven't committed to keeping any other insns in the list yet,
3839 there is nothing more to check. */
3840 else if (p
->insn
== p
->first
)
3842 /* If this insn sets / clobbers a register that feeds one of the insns
3843 already in the list, this insn has to stay too. */
3844 else if (reg_overlap_mentioned_p (dest
, PATTERN (p
->first
))
3845 || (CALL_P (p
->first
) && (find_reg_fusage (p
->first
, USE
, dest
)))
3846 || reg_used_between_p (dest
, p
->first
, p
->insn
)
3847 /* Likewise if this insn depends on a register set by a previous
3848 insn in the list, or if it sets a result (presumably a hard
3849 register) that is set or clobbered by a previous insn.
3850 N.B. the modified_*_p (SET_DEST...) tests applied to a MEM
3851 SET_DEST perform the former check on the address, and the latter
3852 check on the MEM. */
3853 || (GET_CODE (set
) == SET
3854 && (modified_in_p (SET_SRC (set
), p
->first
)
3855 || modified_in_p (SET_DEST (set
), p
->first
)
3856 || modified_between_p (SET_SRC (set
), p
->first
, p
->insn
)
3857 || modified_between_p (SET_DEST (set
), p
->first
, p
->insn
))))
3858 p
->must_stay
= true;
3862 /* Emit code to make a call to a constant function or a library call.
3864 INSNS is a list containing all insns emitted in the call.
3865 These insns leave the result in RESULT. Our block is to copy RESULT
3866 to TARGET, which is logically equivalent to EQUIV.
3868 We first emit any insns that set a pseudo on the assumption that these are
3869 loading constants into registers; doing so allows them to be safely cse'ed
3870 between blocks. Then we emit all the other insns in the block, followed by
3871 an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL
3872 note with an operand of EQUIV. */
3875 emit_libcall_block_1 (rtx insns
, rtx target
, rtx result
, rtx equiv
,
3876 bool equiv_may_trap
)
3878 rtx final_dest
= target
;
3879 rtx next
, last
, insn
;
3881 /* If this is a reg with REG_USERVAR_P set, then it could possibly turn
3882 into a MEM later. Protect the libcall block from this change. */
3883 if (! REG_P (target
) || REG_USERVAR_P (target
))
3884 target
= gen_reg_rtx (GET_MODE (target
));
3886 /* If we're using non-call exceptions, a libcall corresponding to an
3887 operation that may trap may also trap. */
3888 /* ??? See the comment in front of make_reg_eh_region_note. */
3889 if (cfun
->can_throw_non_call_exceptions
3890 && (equiv_may_trap
|| may_trap_p (equiv
)))
3892 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3895 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
3898 int lp_nr
= INTVAL (XEXP (note
, 0));
3899 if (lp_nr
== 0 || lp_nr
== INT_MIN
)
3900 remove_note (insn
, note
);
3906 /* Look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION
3907 reg note to indicate that this call cannot throw or execute a nonlocal
3908 goto (unless there is already a REG_EH_REGION note, in which case
3910 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3912 make_reg_eh_region_note_nothrow_nononlocal (insn
);
3915 /* First emit all insns that set pseudos. Remove them from the list as
3916 we go. Avoid insns that set pseudos which were referenced in previous
3917 insns. These can be generated by move_by_pieces, for example,
3918 to update an address. Similarly, avoid insns that reference things
3919 set in previous insns. */
3921 for (insn
= insns
; insn
; insn
= next
)
3923 rtx set
= single_set (insn
);
3925 next
= NEXT_INSN (insn
);
3927 if (set
!= 0 && REG_P (SET_DEST (set
))
3928 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
3930 struct no_conflict_data data
;
3932 data
.target
= const0_rtx
;
3936 note_stores (PATTERN (insn
), no_conflict_move_test
, &data
);
3937 if (! data
.must_stay
)
3939 if (PREV_INSN (insn
))
3940 NEXT_INSN (PREV_INSN (insn
)) = next
;
3945 PREV_INSN (next
) = PREV_INSN (insn
);
3951 /* Some ports use a loop to copy large arguments onto the stack.
3952 Don't move anything outside such a loop. */
3957 /* Write the remaining insns followed by the final copy. */
3958 for (insn
= insns
; insn
; insn
= next
)
3960 next
= NEXT_INSN (insn
);
3965 last
= emit_move_insn (target
, result
);
3966 set_dst_reg_note (last
, REG_EQUAL
, copy_rtx (equiv
), target
);
3968 if (final_dest
!= target
)
3969 emit_move_insn (final_dest
, target
);
3973 emit_libcall_block (rtx insns
, rtx target
, rtx result
, rtx equiv
)
3975 emit_libcall_block_1 (insns
, target
, result
, equiv
, false);
3978 /* Nonzero if we can perform a comparison of mode MODE straightforwardly.
3979 PURPOSE describes how this comparison will be used. CODE is the rtx
3980 comparison code we will be using.
3982 ??? Actually, CODE is slightly weaker than that. A target is still
3983 required to implement all of the normal bcc operations, but not
3984 required to implement all (or any) of the unordered bcc operations. */
3987 can_compare_p (enum rtx_code code
, enum machine_mode mode
,
3988 enum can_compare_purpose purpose
)
3991 test
= gen_rtx_fmt_ee (code
, mode
, const0_rtx
, const0_rtx
);
3994 enum insn_code icode
;
3996 if (purpose
== ccp_jump
3997 && (icode
= optab_handler (cbranch_optab
, mode
)) != CODE_FOR_nothing
3998 && insn_operand_matches (icode
, 0, test
))
4000 if (purpose
== ccp_store_flag
4001 && (icode
= optab_handler (cstore_optab
, mode
)) != CODE_FOR_nothing
4002 && insn_operand_matches (icode
, 1, test
))
4004 if (purpose
== ccp_cmov
4005 && optab_handler (cmov_optab
, mode
) != CODE_FOR_nothing
)
4008 mode
= GET_MODE_WIDER_MODE (mode
);
4009 PUT_MODE (test
, mode
);
4011 while (mode
!= VOIDmode
);
4016 /* This function is called when we are going to emit a compare instruction that
4017 compares the values found in *PX and *PY, using the rtl operator COMPARISON.
4019 *PMODE is the mode of the inputs (in case they are const_int).
4020 *PUNSIGNEDP nonzero says that the operands are unsigned;
4021 this matters if they need to be widened (as given by METHODS).
4023 If they have mode BLKmode, then SIZE specifies the size of both operands.
4025 This function performs all the setup necessary so that the caller only has
4026 to emit a single comparison insn. This setup can involve doing a BLKmode
4027 comparison or emitting a library call to perform the comparison if no insn
4028 is available to handle it.
4029 The values which are passed in through pointers can be modified; the caller
4030 should perform the comparison on the modified values. Constant
4031 comparisons must have already been folded. */
4034 prepare_cmp_insn (rtx x
, rtx y
, enum rtx_code comparison
, rtx size
,
4035 int unsignedp
, enum optab_methods methods
,
4036 rtx
*ptest
, enum machine_mode
*pmode
)
4038 enum machine_mode mode
= *pmode
;
4040 enum machine_mode cmp_mode
;
4041 enum mode_class mclass
;
4043 /* The other methods are not needed. */
4044 gcc_assert (methods
== OPTAB_DIRECT
|| methods
== OPTAB_WIDEN
4045 || methods
== OPTAB_LIB_WIDEN
);
4047 /* If we are optimizing, force expensive constants into a register. */
4048 if (CONSTANT_P (x
) && optimize
4049 && (rtx_cost (x
, COMPARE
, 0, optimize_insn_for_speed_p ())
4050 > COSTS_N_INSNS (1)))
4051 x
= force_reg (mode
, x
);
4053 if (CONSTANT_P (y
) && optimize
4054 && (rtx_cost (y
, COMPARE
, 1, optimize_insn_for_speed_p ())
4055 > COSTS_N_INSNS (1)))
4056 y
= force_reg (mode
, y
);
4059 /* Make sure if we have a canonical comparison. The RTL
4060 documentation states that canonical comparisons are required only
4061 for targets which have cc0. */
4062 gcc_assert (!CONSTANT_P (x
) || CONSTANT_P (y
));
4065 /* Don't let both operands fail to indicate the mode. */
4066 if (GET_MODE (x
) == VOIDmode
&& GET_MODE (y
) == VOIDmode
)
4067 x
= force_reg (mode
, x
);
4068 if (mode
== VOIDmode
)
4069 mode
= GET_MODE (x
) != VOIDmode
? GET_MODE (x
) : GET_MODE (y
);
4071 /* Handle all BLKmode compares. */
4073 if (mode
== BLKmode
)
4075 enum machine_mode result_mode
;
4076 enum insn_code cmp_code
;
4081 = GEN_INT (MIN (MEM_ALIGN (x
), MEM_ALIGN (y
)) / BITS_PER_UNIT
);
4085 /* Try to use a memory block compare insn - either cmpstr
4086 or cmpmem will do. */
4087 for (cmp_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
4088 cmp_mode
!= VOIDmode
;
4089 cmp_mode
= GET_MODE_WIDER_MODE (cmp_mode
))
4091 cmp_code
= direct_optab_handler (cmpmem_optab
, cmp_mode
);
4092 if (cmp_code
== CODE_FOR_nothing
)
4093 cmp_code
= direct_optab_handler (cmpstr_optab
, cmp_mode
);
4094 if (cmp_code
== CODE_FOR_nothing
)
4095 cmp_code
= direct_optab_handler (cmpstrn_optab
, cmp_mode
);
4096 if (cmp_code
== CODE_FOR_nothing
)
4099 /* Must make sure the size fits the insn's mode. */
4100 if ((CONST_INT_P (size
)
4101 && INTVAL (size
) >= (1 << GET_MODE_BITSIZE (cmp_mode
)))
4102 || (GET_MODE_BITSIZE (GET_MODE (size
))
4103 > GET_MODE_BITSIZE (cmp_mode
)))
4106 result_mode
= insn_data
[cmp_code
].operand
[0].mode
;
4107 result
= gen_reg_rtx (result_mode
);
4108 size
= convert_to_mode (cmp_mode
, size
, 1);
4109 emit_insn (GEN_FCN (cmp_code
) (result
, x
, y
, size
, opalign
));
4111 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, result
, const0_rtx
);
4112 *pmode
= result_mode
;
4116 if (methods
!= OPTAB_LIB
&& methods
!= OPTAB_LIB_WIDEN
)
4119 /* Otherwise call a library function, memcmp. */
4120 libfunc
= memcmp_libfunc
;
4121 length_type
= sizetype
;
4122 result_mode
= TYPE_MODE (integer_type_node
);
4123 cmp_mode
= TYPE_MODE (length_type
);
4124 size
= convert_to_mode (TYPE_MODE (length_type
), size
,
4125 TYPE_UNSIGNED (length_type
));
4127 result
= emit_library_call_value (libfunc
, 0, LCT_PURE
,
4135 methods
= OPTAB_LIB_WIDEN
;
4139 /* Don't allow operands to the compare to trap, as that can put the
4140 compare and branch in different basic blocks. */
4141 if (cfun
->can_throw_non_call_exceptions
)
4144 x
= force_reg (mode
, x
);
4146 y
= force_reg (mode
, y
);
4149 if (GET_MODE_CLASS (mode
) == MODE_CC
)
4151 gcc_assert (can_compare_p (comparison
, CCmode
, ccp_jump
));
4152 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, x
, y
);
4156 mclass
= GET_MODE_CLASS (mode
);
4157 test
= gen_rtx_fmt_ee (comparison
, VOIDmode
, x
, y
);
4161 enum insn_code icode
;
4162 icode
= optab_handler (cbranch_optab
, cmp_mode
);
4163 if (icode
!= CODE_FOR_nothing
4164 && insn_operand_matches (icode
, 0, test
))
4166 rtx last
= get_last_insn ();
4167 rtx op0
= prepare_operand (icode
, x
, 1, mode
, cmp_mode
, unsignedp
);
4168 rtx op1
= prepare_operand (icode
, y
, 2, mode
, cmp_mode
, unsignedp
);
4170 && insn_operand_matches (icode
, 1, op0
)
4171 && insn_operand_matches (icode
, 2, op1
))
4173 XEXP (test
, 0) = op0
;
4174 XEXP (test
, 1) = op1
;
4179 delete_insns_since (last
);
4182 if (methods
== OPTAB_DIRECT
|| !CLASS_HAS_WIDER_MODES_P (mclass
))
4184 cmp_mode
= GET_MODE_WIDER_MODE (cmp_mode
);
4186 while (cmp_mode
!= VOIDmode
);
4188 if (methods
!= OPTAB_LIB_WIDEN
)
4191 if (!SCALAR_FLOAT_MODE_P (mode
))
4194 enum machine_mode ret_mode
;
4196 /* Handle a libcall just for the mode we are using. */
4197 libfunc
= optab_libfunc (cmp_optab
, mode
);
4198 gcc_assert (libfunc
);
4200 /* If we want unsigned, and this mode has a distinct unsigned
4201 comparison routine, use that. */
4204 rtx ulibfunc
= optab_libfunc (ucmp_optab
, mode
);
4209 ret_mode
= targetm
.libgcc_cmp_return_mode ();
4210 result
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
4211 ret_mode
, 2, x
, mode
, y
, mode
);
4213 /* There are two kinds of comparison routines. Biased routines
4214 return 0/1/2, and unbiased routines return -1/0/1. Other parts
4215 of gcc expect that the comparison operation is equivalent
4216 to the modified comparison. For signed comparisons compare the
4217 result against 1 in the biased case, and zero in the unbiased
4218 case. For unsigned comparisons always compare against 1 after
4219 biasing the unbiased result by adding 1. This gives us a way to
4221 The comparisons in the fixed-point helper library are always
4226 if (!TARGET_LIB_INT_CMP_BIASED
&& !ALL_FIXED_POINT_MODE_P (mode
))
4229 x
= plus_constant (ret_mode
, result
, 1);
4235 prepare_cmp_insn (x
, y
, comparison
, NULL_RTX
, unsignedp
, methods
,
4239 prepare_float_lib_cmp (x
, y
, comparison
, ptest
, pmode
);
4247 /* Before emitting an insn with code ICODE, make sure that X, which is going
4248 to be used for operand OPNUM of the insn, is converted from mode MODE to
4249 WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and
4250 that it is accepted by the operand predicate. Return the new value. */
4253 prepare_operand (enum insn_code icode
, rtx x
, int opnum
, enum machine_mode mode
,
4254 enum machine_mode wider_mode
, int unsignedp
)
4256 if (mode
!= wider_mode
)
4257 x
= convert_modes (wider_mode
, mode
, x
, unsignedp
);
4259 if (!insn_operand_matches (icode
, opnum
, x
))
4261 if (reload_completed
)
4263 x
= copy_to_mode_reg (insn_data
[(int) icode
].operand
[opnum
].mode
, x
);
4269 /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know
4270 we can do the branch. */
4273 emit_cmp_and_jump_insn_1 (rtx test
, enum machine_mode mode
, rtx label
, int prob
)
4275 enum machine_mode optab_mode
;
4276 enum mode_class mclass
;
4277 enum insn_code icode
;
4280 mclass
= GET_MODE_CLASS (mode
);
4281 optab_mode
= (mclass
== MODE_CC
) ? CCmode
: mode
;
4282 icode
= optab_handler (cbranch_optab
, optab_mode
);
4284 gcc_assert (icode
!= CODE_FOR_nothing
);
4285 gcc_assert (insn_operand_matches (icode
, 0, test
));
4286 insn
= emit_jump_insn (GEN_FCN (icode
) (test
, XEXP (test
, 0),
4287 XEXP (test
, 1), label
));
4289 && profile_status_for_fn (cfun
) != PROFILE_ABSENT
4292 && any_condjump_p (insn
)
4293 && !find_reg_note (insn
, REG_BR_PROB
, 0))
4294 add_int_reg_note (insn
, REG_BR_PROB
, prob
);
4297 /* Generate code to compare X with Y so that the condition codes are
4298 set and to jump to LABEL if the condition is true. If X is a
4299 constant and Y is not a constant, then the comparison is swapped to
4300 ensure that the comparison RTL has the canonical form.
4302 UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they
4303 need to be widened. UNSIGNEDP is also used to select the proper
4304 branch condition code.
4306 If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y.
4308 MODE is the mode of the inputs (in case they are const_int).
4310 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
4311 It will be potentially converted into an unsigned variant based on
4312 UNSIGNEDP to select a proper jump instruction.
4314 PROB is the probability of jumping to LABEL. */
4317 emit_cmp_and_jump_insns (rtx x
, rtx y
, enum rtx_code comparison
, rtx size
,
4318 enum machine_mode mode
, int unsignedp
, rtx label
,
4321 rtx op0
= x
, op1
= y
;
4324 /* Swap operands and condition to ensure canonical RTL. */
4325 if (swap_commutative_operands_p (x
, y
)
4326 && can_compare_p (swap_condition (comparison
), mode
, ccp_jump
))
4329 comparison
= swap_condition (comparison
);
4332 /* If OP0 is still a constant, then both X and Y must be constants
4333 or the opposite comparison is not supported. Force X into a register
4334 to create canonical RTL. */
4335 if (CONSTANT_P (op0
))
4336 op0
= force_reg (mode
, op0
);
4339 comparison
= unsigned_condition (comparison
);
4341 prepare_cmp_insn (op0
, op1
, comparison
, size
, unsignedp
, OPTAB_LIB_WIDEN
,
4343 emit_cmp_and_jump_insn_1 (test
, mode
, label
, prob
);
4347 /* Emit a library call comparison between floating point X and Y.
4348 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */
4351 prepare_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
,
4352 rtx
*ptest
, enum machine_mode
*pmode
)
4354 enum rtx_code swapped
= swap_condition (comparison
);
4355 enum rtx_code reversed
= reverse_condition_maybe_unordered (comparison
);
4356 enum machine_mode orig_mode
= GET_MODE (x
);
4357 enum machine_mode mode
, cmp_mode
;
4358 rtx true_rtx
, false_rtx
;
4359 rtx value
, target
, insns
, equiv
;
4361 bool reversed_p
= false;
4362 cmp_mode
= targetm
.libgcc_cmp_return_mode ();
4364 for (mode
= orig_mode
;
4366 mode
= GET_MODE_WIDER_MODE (mode
))
4368 if (code_to_optab (comparison
)
4369 && (libfunc
= optab_libfunc (code_to_optab (comparison
), mode
)))
4372 if (code_to_optab (swapped
)
4373 && (libfunc
= optab_libfunc (code_to_optab (swapped
), mode
)))
4376 tmp
= x
; x
= y
; y
= tmp
;
4377 comparison
= swapped
;
4381 if (code_to_optab (reversed
)
4382 && (libfunc
= optab_libfunc (code_to_optab (reversed
), mode
)))
4384 comparison
= reversed
;
4390 gcc_assert (mode
!= VOIDmode
);
4392 if (mode
!= orig_mode
)
4394 x
= convert_to_mode (mode
, x
, 0);
4395 y
= convert_to_mode (mode
, y
, 0);
4398 /* Attach a REG_EQUAL note describing the semantics of the libcall to
4399 the RTL. The allows the RTL optimizers to delete the libcall if the
4400 condition can be determined at compile-time. */
4401 if (comparison
== UNORDERED
4402 || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
))
4404 true_rtx
= const_true_rtx
;
4405 false_rtx
= const0_rtx
;
4412 true_rtx
= const0_rtx
;
4413 false_rtx
= const_true_rtx
;
4417 true_rtx
= const_true_rtx
;
4418 false_rtx
= const0_rtx
;
4422 true_rtx
= const1_rtx
;
4423 false_rtx
= const0_rtx
;
4427 true_rtx
= const0_rtx
;
4428 false_rtx
= constm1_rtx
;
4432 true_rtx
= constm1_rtx
;
4433 false_rtx
= const0_rtx
;
4437 true_rtx
= const0_rtx
;
4438 false_rtx
= const1_rtx
;
4446 if (comparison
== UNORDERED
)
4448 rtx temp
= simplify_gen_relational (NE
, cmp_mode
, mode
, x
, x
);
4449 equiv
= simplify_gen_relational (NE
, cmp_mode
, mode
, y
, y
);
4450 equiv
= simplify_gen_ternary (IF_THEN_ELSE
, cmp_mode
, cmp_mode
,
4451 temp
, const_true_rtx
, equiv
);
4455 equiv
= simplify_gen_relational (comparison
, cmp_mode
, mode
, x
, y
);
4456 if (! FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
))
4457 equiv
= simplify_gen_ternary (IF_THEN_ELSE
, cmp_mode
, cmp_mode
,
4458 equiv
, true_rtx
, false_rtx
);
4462 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
4463 cmp_mode
, 2, x
, mode
, y
, mode
);
4464 insns
= get_insns ();
4467 target
= gen_reg_rtx (cmp_mode
);
4468 emit_libcall_block (insns
, target
, value
, equiv
);
4470 if (comparison
== UNORDERED
4471 || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
)
4473 *ptest
= gen_rtx_fmt_ee (reversed_p
? EQ
: NE
, VOIDmode
, target
, false_rtx
);
4475 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, target
, const0_rtx
);
4480 /* Generate code to indirectly jump to a location given in the rtx LOC. */
4483 emit_indirect_jump (rtx loc
)
4485 struct expand_operand ops
[1];
4487 create_address_operand (&ops
[0], loc
);
4488 expand_jump_insn (CODE_FOR_indirect_jump
, 1, ops
);
4492 #ifdef HAVE_conditional_move
4494 /* Emit a conditional move instruction if the machine supports one for that
4495 condition and machine mode.
4497 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4498 the mode to use should they be constants. If it is VOIDmode, they cannot
4501 OP2 should be stored in TARGET if the comparison is true, otherwise OP3
4502 should be stored there. MODE is the mode to use should they be constants.
4503 If it is VOIDmode, they cannot both be constants.
4505 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4506 is not supported. */
4509 emit_conditional_move (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
4510 enum machine_mode cmode
, rtx op2
, rtx op3
,
4511 enum machine_mode mode
, int unsignedp
)
4513 rtx tem
, comparison
, last
;
4514 enum insn_code icode
;
4515 enum rtx_code reversed
;
4517 /* If one operand is constant, make it the second one. Only do this
4518 if the other operand is not constant as well. */
4520 if (swap_commutative_operands_p (op0
, op1
))
4525 code
= swap_condition (code
);
4528 /* get_condition will prefer to generate LT and GT even if the old
4529 comparison was against zero, so undo that canonicalization here since
4530 comparisons against zero are cheaper. */
4531 if (code
== LT
&& op1
== const1_rtx
)
4532 code
= LE
, op1
= const0_rtx
;
4533 else if (code
== GT
&& op1
== constm1_rtx
)
4534 code
= GE
, op1
= const0_rtx
;
4536 if (cmode
== VOIDmode
)
4537 cmode
= GET_MODE (op0
);
4539 if (swap_commutative_operands_p (op2
, op3
)
4540 && ((reversed
= reversed_comparison_code_parts (code
, op0
, op1
, NULL
))
4549 if (mode
== VOIDmode
)
4550 mode
= GET_MODE (op2
);
4552 icode
= direct_optab_handler (movcc_optab
, mode
);
4554 if (icode
== CODE_FOR_nothing
)
4558 target
= gen_reg_rtx (mode
);
4560 code
= unsignedp
? unsigned_condition (code
) : code
;
4561 comparison
= simplify_gen_relational (code
, VOIDmode
, cmode
, op0
, op1
);
4563 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4564 return NULL and let the caller figure out how best to deal with this
4566 if (!COMPARISON_P (comparison
))
4569 saved_pending_stack_adjust save
;
4570 save_pending_stack_adjust (&save
);
4571 last
= get_last_insn ();
4572 do_pending_stack_adjust ();
4573 prepare_cmp_insn (XEXP (comparison
, 0), XEXP (comparison
, 1),
4574 GET_CODE (comparison
), NULL_RTX
, unsignedp
, OPTAB_WIDEN
,
4575 &comparison
, &cmode
);
4578 struct expand_operand ops
[4];
4580 create_output_operand (&ops
[0], target
, mode
);
4581 create_fixed_operand (&ops
[1], comparison
);
4582 create_input_operand (&ops
[2], op2
, mode
);
4583 create_input_operand (&ops
[3], op3
, mode
);
4584 if (maybe_expand_insn (icode
, 4, ops
))
4586 if (ops
[0].value
!= target
)
4587 convert_move (target
, ops
[0].value
, false);
4591 delete_insns_since (last
);
4592 restore_pending_stack_adjust (&save
);
4596 /* Return nonzero if a conditional move of mode MODE is supported.
4598 This function is for combine so it can tell whether an insn that looks
4599 like a conditional move is actually supported by the hardware. If we
4600 guess wrong we lose a bit on optimization, but that's it. */
4601 /* ??? sparc64 supports conditionally moving integers values based on fp
4602 comparisons, and vice versa. How do we handle them? */
4605 can_conditionally_move_p (enum machine_mode mode
)
4607 if (direct_optab_handler (movcc_optab
, mode
) != CODE_FOR_nothing
)
4613 #endif /* HAVE_conditional_move */
4615 /* Emit a conditional addition instruction if the machine supports one for that
4616 condition and machine mode.
4618 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4619 the mode to use should they be constants. If it is VOIDmode, they cannot
4622 OP2 should be stored in TARGET if the comparison is false, otherwise OP2+OP3
4623 should be stored there. MODE is the mode to use should they be constants.
4624 If it is VOIDmode, they cannot both be constants.
4626 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4627 is not supported. */
4630 emit_conditional_add (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
4631 enum machine_mode cmode
, rtx op2
, rtx op3
,
4632 enum machine_mode mode
, int unsignedp
)
4634 rtx tem
, comparison
, last
;
4635 enum insn_code icode
;
4637 /* If one operand is constant, make it the second one. Only do this
4638 if the other operand is not constant as well. */
4640 if (swap_commutative_operands_p (op0
, op1
))
4645 code
= swap_condition (code
);
4648 /* get_condition will prefer to generate LT and GT even if the old
4649 comparison was against zero, so undo that canonicalization here since
4650 comparisons against zero are cheaper. */
4651 if (code
== LT
&& op1
== const1_rtx
)
4652 code
= LE
, op1
= const0_rtx
;
4653 else if (code
== GT
&& op1
== constm1_rtx
)
4654 code
= GE
, op1
= const0_rtx
;
4656 if (cmode
== VOIDmode
)
4657 cmode
= GET_MODE (op0
);
4659 if (mode
== VOIDmode
)
4660 mode
= GET_MODE (op2
);
4662 icode
= optab_handler (addcc_optab
, mode
);
4664 if (icode
== CODE_FOR_nothing
)
4668 target
= gen_reg_rtx (mode
);
4670 code
= unsignedp
? unsigned_condition (code
) : code
;
4671 comparison
= simplify_gen_relational (code
, VOIDmode
, cmode
, op0
, op1
);
4673 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4674 return NULL and let the caller figure out how best to deal with this
4676 if (!COMPARISON_P (comparison
))
4679 do_pending_stack_adjust ();
4680 last
= get_last_insn ();
4681 prepare_cmp_insn (XEXP (comparison
, 0), XEXP (comparison
, 1),
4682 GET_CODE (comparison
), NULL_RTX
, unsignedp
, OPTAB_WIDEN
,
4683 &comparison
, &cmode
);
4686 struct expand_operand ops
[4];
4688 create_output_operand (&ops
[0], target
, mode
);
4689 create_fixed_operand (&ops
[1], comparison
);
4690 create_input_operand (&ops
[2], op2
, mode
);
4691 create_input_operand (&ops
[3], op3
, mode
);
4692 if (maybe_expand_insn (icode
, 4, ops
))
4694 if (ops
[0].value
!= target
)
4695 convert_move (target
, ops
[0].value
, false);
4699 delete_insns_since (last
);
4703 /* These functions attempt to generate an insn body, rather than
4704 emitting the insn, but if the gen function already emits them, we
4705 make no attempt to turn them back into naked patterns. */
4707 /* Generate and return an insn body to add Y to X. */
4710 gen_add2_insn (rtx x
, rtx y
)
4712 enum insn_code icode
= optab_handler (add_optab
, GET_MODE (x
));
4714 gcc_assert (insn_operand_matches (icode
, 0, x
));
4715 gcc_assert (insn_operand_matches (icode
, 1, x
));
4716 gcc_assert (insn_operand_matches (icode
, 2, y
));
4718 return GEN_FCN (icode
) (x
, x
, y
);
4721 /* Generate and return an insn body to add r1 and c,
4722 storing the result in r0. */
4725 gen_add3_insn (rtx r0
, rtx r1
, rtx c
)
4727 enum insn_code icode
= optab_handler (add_optab
, GET_MODE (r0
));
4729 if (icode
== CODE_FOR_nothing
4730 || !insn_operand_matches (icode
, 0, r0
)
4731 || !insn_operand_matches (icode
, 1, r1
)
4732 || !insn_operand_matches (icode
, 2, c
))
4735 return GEN_FCN (icode
) (r0
, r1
, c
);
4739 have_add2_insn (rtx x
, rtx y
)
4741 enum insn_code icode
;
4743 gcc_assert (GET_MODE (x
) != VOIDmode
);
4745 icode
= optab_handler (add_optab
, GET_MODE (x
));
4747 if (icode
== CODE_FOR_nothing
)
4750 if (!insn_operand_matches (icode
, 0, x
)
4751 || !insn_operand_matches (icode
, 1, x
)
4752 || !insn_operand_matches (icode
, 2, y
))
4758 /* Generate and return an insn body to add Y to X. */
4761 gen_addptr3_insn (rtx x
, rtx y
, rtx z
)
4763 enum insn_code icode
= optab_handler (addptr3_optab
, GET_MODE (x
));
4765 gcc_assert (insn_operand_matches (icode
, 0, x
));
4766 gcc_assert (insn_operand_matches (icode
, 1, y
));
4767 gcc_assert (insn_operand_matches (icode
, 2, z
));
4769 return GEN_FCN (icode
) (x
, y
, z
);
4772 /* Return true if the target implements an addptr pattern and X, Y,
4773 and Z are valid for the pattern predicates. */
4776 have_addptr3_insn (rtx x
, rtx y
, rtx z
)
4778 enum insn_code icode
;
4780 gcc_assert (GET_MODE (x
) != VOIDmode
);
4782 icode
= optab_handler (addptr3_optab
, GET_MODE (x
));
4784 if (icode
== CODE_FOR_nothing
)
4787 if (!insn_operand_matches (icode
, 0, x
)
4788 || !insn_operand_matches (icode
, 1, y
)
4789 || !insn_operand_matches (icode
, 2, z
))
4795 /* Generate and return an insn body to subtract Y from X. */
4798 gen_sub2_insn (rtx x
, rtx y
)
4800 enum insn_code icode
= optab_handler (sub_optab
, GET_MODE (x
));
4802 gcc_assert (insn_operand_matches (icode
, 0, x
));
4803 gcc_assert (insn_operand_matches (icode
, 1, x
));
4804 gcc_assert (insn_operand_matches (icode
, 2, y
));
4806 return GEN_FCN (icode
) (x
, x
, y
);
4809 /* Generate and return an insn body to subtract r1 and c,
4810 storing the result in r0. */
4813 gen_sub3_insn (rtx r0
, rtx r1
, rtx c
)
4815 enum insn_code icode
= optab_handler (sub_optab
, GET_MODE (r0
));
4817 if (icode
== CODE_FOR_nothing
4818 || !insn_operand_matches (icode
, 0, r0
)
4819 || !insn_operand_matches (icode
, 1, r1
)
4820 || !insn_operand_matches (icode
, 2, c
))
4823 return GEN_FCN (icode
) (r0
, r1
, c
);
4827 have_sub2_insn (rtx x
, rtx y
)
4829 enum insn_code icode
;
4831 gcc_assert (GET_MODE (x
) != VOIDmode
);
4833 icode
= optab_handler (sub_optab
, GET_MODE (x
));
4835 if (icode
== CODE_FOR_nothing
)
4838 if (!insn_operand_matches (icode
, 0, x
)
4839 || !insn_operand_matches (icode
, 1, x
)
4840 || !insn_operand_matches (icode
, 2, y
))
4846 /* Generate the body of an instruction to copy Y into X.
4847 It may be a list of insns, if one insn isn't enough. */
4850 gen_move_insn (rtx x
, rtx y
)
4855 emit_move_insn_1 (x
, y
);
4861 /* Return the insn code used to extend FROM_MODE to TO_MODE.
4862 UNSIGNEDP specifies zero-extension instead of sign-extension. If
4863 no such operation exists, CODE_FOR_nothing will be returned. */
4866 can_extend_p (enum machine_mode to_mode
, enum machine_mode from_mode
,
4870 #ifdef HAVE_ptr_extend
4872 return CODE_FOR_ptr_extend
;
4875 tab
= unsignedp
? zext_optab
: sext_optab
;
4876 return convert_optab_handler (tab
, to_mode
, from_mode
);
4879 /* Generate the body of an insn to extend Y (with mode MFROM)
4880 into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */
4883 gen_extend_insn (rtx x
, rtx y
, enum machine_mode mto
,
4884 enum machine_mode mfrom
, int unsignedp
)
4886 enum insn_code icode
= can_extend_p (mto
, mfrom
, unsignedp
);
4887 return GEN_FCN (icode
) (x
, y
);
4890 /* can_fix_p and can_float_p say whether the target machine
4891 can directly convert a given fixed point type to
4892 a given floating point type, or vice versa.
4893 The returned value is the CODE_FOR_... value to use,
4894 or CODE_FOR_nothing if these modes cannot be directly converted.
4896 *TRUNCP_PTR is set to 1 if it is necessary to output
4897 an explicit FTRUNC insn before the fix insn; otherwise 0. */
4899 static enum insn_code
4900 can_fix_p (enum machine_mode fixmode
, enum machine_mode fltmode
,
4901 int unsignedp
, int *truncp_ptr
)
4904 enum insn_code icode
;
4906 tab
= unsignedp
? ufixtrunc_optab
: sfixtrunc_optab
;
4907 icode
= convert_optab_handler (tab
, fixmode
, fltmode
);
4908 if (icode
!= CODE_FOR_nothing
)
4914 /* FIXME: This requires a port to define both FIX and FTRUNC pattern
4915 for this to work. We need to rework the fix* and ftrunc* patterns
4916 and documentation. */
4917 tab
= unsignedp
? ufix_optab
: sfix_optab
;
4918 icode
= convert_optab_handler (tab
, fixmode
, fltmode
);
4919 if (icode
!= CODE_FOR_nothing
4920 && optab_handler (ftrunc_optab
, fltmode
) != CODE_FOR_nothing
)
4927 return CODE_FOR_nothing
;
4931 can_float_p (enum machine_mode fltmode
, enum machine_mode fixmode
,
4936 tab
= unsignedp
? ufloat_optab
: sfloat_optab
;
4937 return convert_optab_handler (tab
, fltmode
, fixmode
);
4940 /* Function supportable_convert_operation
4942 Check whether an operation represented by the code CODE is a
4943 convert operation that is supported by the target platform in
4944 vector form (i.e., when operating on arguments of type VECTYPE_IN
4945 producing a result of type VECTYPE_OUT).
4947 Convert operations we currently support directly are FIX_TRUNC and FLOAT.
4948 This function checks if these operations are supported
4949 by the target platform either directly (via vector tree-codes), or via
4953 - CODE1 is code of vector operation to be used when
4954 vectorizing the operation, if available.
4955 - DECL is decl of target builtin functions to be used
4956 when vectorizing the operation, if available. In this case,
4957 CODE1 is CALL_EXPR. */
4960 supportable_convert_operation (enum tree_code code
,
4961 tree vectype_out
, tree vectype_in
,
4962 tree
*decl
, enum tree_code
*code1
)
4964 enum machine_mode m1
,m2
;
4967 m1
= TYPE_MODE (vectype_out
);
4968 m2
= TYPE_MODE (vectype_in
);
4970 /* First check if we can done conversion directly. */
4971 if ((code
== FIX_TRUNC_EXPR
4972 && can_fix_p (m1
,m2
,TYPE_UNSIGNED (vectype_out
), &truncp
)
4973 != CODE_FOR_nothing
)
4974 || (code
== FLOAT_EXPR
4975 && can_float_p (m1
,m2
,TYPE_UNSIGNED (vectype_in
))
4976 != CODE_FOR_nothing
))
4982 /* Now check for builtin. */
4983 if (targetm
.vectorize
.builtin_conversion
4984 && targetm
.vectorize
.builtin_conversion (code
, vectype_out
, vectype_in
))
4987 *decl
= targetm
.vectorize
.builtin_conversion (code
, vectype_out
, vectype_in
);
4994 /* Generate code to convert FROM to floating point
4995 and store in TO. FROM must be fixed point and not VOIDmode.
4996 UNSIGNEDP nonzero means regard FROM as unsigned.
4997 Normally this is done by correcting the final value
4998 if it is negative. */
5001 expand_float (rtx to
, rtx from
, int unsignedp
)
5003 enum insn_code icode
;
5005 enum machine_mode fmode
, imode
;
5006 bool can_do_signed
= false;
5008 /* Crash now, because we won't be able to decide which mode to use. */
5009 gcc_assert (GET_MODE (from
) != VOIDmode
);
5011 /* Look for an insn to do the conversion. Do it in the specified
5012 modes if possible; otherwise convert either input, output or both to
5013 wider mode. If the integer mode is wider than the mode of FROM,
5014 we can do the conversion signed even if the input is unsigned. */
5016 for (fmode
= GET_MODE (to
); fmode
!= VOIDmode
;
5017 fmode
= GET_MODE_WIDER_MODE (fmode
))
5018 for (imode
= GET_MODE (from
); imode
!= VOIDmode
;
5019 imode
= GET_MODE_WIDER_MODE (imode
))
5021 int doing_unsigned
= unsignedp
;
5023 if (fmode
!= GET_MODE (to
)
5024 && significand_size (fmode
) < GET_MODE_PRECISION (GET_MODE (from
)))
5027 icode
= can_float_p (fmode
, imode
, unsignedp
);
5028 if (icode
== CODE_FOR_nothing
&& unsignedp
)
5030 enum insn_code scode
= can_float_p (fmode
, imode
, 0);
5031 if (scode
!= CODE_FOR_nothing
)
5032 can_do_signed
= true;
5033 if (imode
!= GET_MODE (from
))
5034 icode
= scode
, doing_unsigned
= 0;
5037 if (icode
!= CODE_FOR_nothing
)
5039 if (imode
!= GET_MODE (from
))
5040 from
= convert_to_mode (imode
, from
, unsignedp
);
5042 if (fmode
!= GET_MODE (to
))
5043 target
= gen_reg_rtx (fmode
);
5045 emit_unop_insn (icode
, target
, from
,
5046 doing_unsigned
? UNSIGNED_FLOAT
: FLOAT
);
5049 convert_move (to
, target
, 0);
5054 /* Unsigned integer, and no way to convert directly. Convert as signed,
5055 then unconditionally adjust the result. */
5056 if (unsignedp
&& can_do_signed
)
5058 rtx label
= gen_label_rtx ();
5060 REAL_VALUE_TYPE offset
;
5062 /* Look for a usable floating mode FMODE wider than the source and at
5063 least as wide as the target. Using FMODE will avoid rounding woes
5064 with unsigned values greater than the signed maximum value. */
5066 for (fmode
= GET_MODE (to
); fmode
!= VOIDmode
;
5067 fmode
= GET_MODE_WIDER_MODE (fmode
))
5068 if (GET_MODE_PRECISION (GET_MODE (from
)) < GET_MODE_BITSIZE (fmode
)
5069 && can_float_p (fmode
, GET_MODE (from
), 0) != CODE_FOR_nothing
)
5072 if (fmode
== VOIDmode
)
5074 /* There is no such mode. Pretend the target is wide enough. */
5075 fmode
= GET_MODE (to
);
5077 /* Avoid double-rounding when TO is narrower than FROM. */
5078 if ((significand_size (fmode
) + 1)
5079 < GET_MODE_PRECISION (GET_MODE (from
)))
5082 rtx neglabel
= gen_label_rtx ();
5084 /* Don't use TARGET if it isn't a register, is a hard register,
5085 or is the wrong mode. */
5087 || REGNO (target
) < FIRST_PSEUDO_REGISTER
5088 || GET_MODE (target
) != fmode
)
5089 target
= gen_reg_rtx (fmode
);
5091 imode
= GET_MODE (from
);
5092 do_pending_stack_adjust ();
5094 /* Test whether the sign bit is set. */
5095 emit_cmp_and_jump_insns (from
, const0_rtx
, LT
, NULL_RTX
, imode
,
5098 /* The sign bit is not set. Convert as signed. */
5099 expand_float (target
, from
, 0);
5100 emit_jump_insn (gen_jump (label
));
5103 /* The sign bit is set.
5104 Convert to a usable (positive signed) value by shifting right
5105 one bit, while remembering if a nonzero bit was shifted
5106 out; i.e., compute (from & 1) | (from >> 1). */
5108 emit_label (neglabel
);
5109 temp
= expand_binop (imode
, and_optab
, from
, const1_rtx
,
5110 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
5111 temp1
= expand_shift (RSHIFT_EXPR
, imode
, from
, 1, NULL_RTX
, 1);
5112 temp
= expand_binop (imode
, ior_optab
, temp
, temp1
, temp
, 1,
5114 expand_float (target
, temp
, 0);
5116 /* Multiply by 2 to undo the shift above. */
5117 temp
= expand_binop (fmode
, add_optab
, target
, target
,
5118 target
, 0, OPTAB_LIB_WIDEN
);
5120 emit_move_insn (target
, temp
);
5122 do_pending_stack_adjust ();
5128 /* If we are about to do some arithmetic to correct for an
5129 unsigned operand, do it in a pseudo-register. */
5131 if (GET_MODE (to
) != fmode
5132 || !REG_P (to
) || REGNO (to
) < FIRST_PSEUDO_REGISTER
)
5133 target
= gen_reg_rtx (fmode
);
5135 /* Convert as signed integer to floating. */
5136 expand_float (target
, from
, 0);
5138 /* If FROM is negative (and therefore TO is negative),
5139 correct its value by 2**bitwidth. */
5141 do_pending_stack_adjust ();
5142 emit_cmp_and_jump_insns (from
, const0_rtx
, GE
, NULL_RTX
, GET_MODE (from
),
5146 real_2expN (&offset
, GET_MODE_PRECISION (GET_MODE (from
)), fmode
);
5147 temp
= expand_binop (fmode
, add_optab
, target
,
5148 CONST_DOUBLE_FROM_REAL_VALUE (offset
, fmode
),
5149 target
, 0, OPTAB_LIB_WIDEN
);
5151 emit_move_insn (target
, temp
);
5153 do_pending_stack_adjust ();
5158 /* No hardware instruction available; call a library routine. */
5163 convert_optab tab
= unsignedp
? ufloat_optab
: sfloat_optab
;
5165 if (GET_MODE_SIZE (GET_MODE (from
)) < GET_MODE_SIZE (SImode
))
5166 from
= convert_to_mode (SImode
, from
, unsignedp
);
5168 libfunc
= convert_optab_libfunc (tab
, GET_MODE (to
), GET_MODE (from
));
5169 gcc_assert (libfunc
);
5173 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
5174 GET_MODE (to
), 1, from
,
5176 insns
= get_insns ();
5179 emit_libcall_block (insns
, target
, value
,
5180 gen_rtx_fmt_e (unsignedp
? UNSIGNED_FLOAT
: FLOAT
,
5181 GET_MODE (to
), from
));
5186 /* Copy result to requested destination
5187 if we have been computing in a temp location. */
5191 if (GET_MODE (target
) == GET_MODE (to
))
5192 emit_move_insn (to
, target
);
5194 convert_move (to
, target
, 0);
5198 /* Generate code to convert FROM to fixed point and store in TO. FROM
5199 must be floating point. */
5202 expand_fix (rtx to
, rtx from
, int unsignedp
)
5204 enum insn_code icode
;
5206 enum machine_mode fmode
, imode
;
5209 /* We first try to find a pair of modes, one real and one integer, at
5210 least as wide as FROM and TO, respectively, in which we can open-code
5211 this conversion. If the integer mode is wider than the mode of TO,
5212 we can do the conversion either signed or unsigned. */
5214 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5215 fmode
= GET_MODE_WIDER_MODE (fmode
))
5216 for (imode
= GET_MODE (to
); imode
!= VOIDmode
;
5217 imode
= GET_MODE_WIDER_MODE (imode
))
5219 int doing_unsigned
= unsignedp
;
5221 icode
= can_fix_p (imode
, fmode
, unsignedp
, &must_trunc
);
5222 if (icode
== CODE_FOR_nothing
&& imode
!= GET_MODE (to
) && unsignedp
)
5223 icode
= can_fix_p (imode
, fmode
, 0, &must_trunc
), doing_unsigned
= 0;
5225 if (icode
!= CODE_FOR_nothing
)
5227 rtx last
= get_last_insn ();
5228 if (fmode
!= GET_MODE (from
))
5229 from
= convert_to_mode (fmode
, from
, 0);
5233 rtx temp
= gen_reg_rtx (GET_MODE (from
));
5234 from
= expand_unop (GET_MODE (from
), ftrunc_optab
, from
,
5238 if (imode
!= GET_MODE (to
))
5239 target
= gen_reg_rtx (imode
);
5241 if (maybe_emit_unop_insn (icode
, target
, from
,
5242 doing_unsigned
? UNSIGNED_FIX
: FIX
))
5245 convert_move (to
, target
, unsignedp
);
5248 delete_insns_since (last
);
5252 /* For an unsigned conversion, there is one more way to do it.
5253 If we have a signed conversion, we generate code that compares
5254 the real value to the largest representable positive number. If if
5255 is smaller, the conversion is done normally. Otherwise, subtract
5256 one plus the highest signed number, convert, and add it back.
5258 We only need to check all real modes, since we know we didn't find
5259 anything with a wider integer mode.
5261 This code used to extend FP value into mode wider than the destination.
5262 This is needed for decimal float modes which cannot accurately
5263 represent one plus the highest signed number of the same size, but
5264 not for binary modes. Consider, for instance conversion from SFmode
5267 The hot path through the code is dealing with inputs smaller than 2^63
5268 and doing just the conversion, so there is no bits to lose.
5270 In the other path we know the value is positive in the range 2^63..2^64-1
5271 inclusive. (as for other input overflow happens and result is undefined)
5272 So we know that the most important bit set in mantissa corresponds to
5273 2^63. The subtraction of 2^63 should not generate any rounding as it
5274 simply clears out that bit. The rest is trivial. */
5276 if (unsignedp
&& GET_MODE_PRECISION (GET_MODE (to
)) <= HOST_BITS_PER_WIDE_INT
)
5277 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5278 fmode
= GET_MODE_WIDER_MODE (fmode
))
5279 if (CODE_FOR_nothing
!= can_fix_p (GET_MODE (to
), fmode
, 0, &must_trunc
)
5280 && (!DECIMAL_FLOAT_MODE_P (fmode
)
5281 || GET_MODE_BITSIZE (fmode
) > GET_MODE_PRECISION (GET_MODE (to
))))
5284 REAL_VALUE_TYPE offset
;
5285 rtx limit
, lab1
, lab2
, insn
;
5287 bitsize
= GET_MODE_PRECISION (GET_MODE (to
));
5288 real_2expN (&offset
, bitsize
- 1, fmode
);
5289 limit
= CONST_DOUBLE_FROM_REAL_VALUE (offset
, fmode
);
5290 lab1
= gen_label_rtx ();
5291 lab2
= gen_label_rtx ();
5293 if (fmode
!= GET_MODE (from
))
5294 from
= convert_to_mode (fmode
, from
, 0);
5296 /* See if we need to do the subtraction. */
5297 do_pending_stack_adjust ();
5298 emit_cmp_and_jump_insns (from
, limit
, GE
, NULL_RTX
, GET_MODE (from
),
5301 /* If not, do the signed "fix" and branch around fixup code. */
5302 expand_fix (to
, from
, 0);
5303 emit_jump_insn (gen_jump (lab2
));
5306 /* Otherwise, subtract 2**(N-1), convert to signed number,
5307 then add 2**(N-1). Do the addition using XOR since this
5308 will often generate better code. */
5310 target
= expand_binop (GET_MODE (from
), sub_optab
, from
, limit
,
5311 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
5312 expand_fix (to
, target
, 0);
5313 target
= expand_binop (GET_MODE (to
), xor_optab
, to
,
5315 ((HOST_WIDE_INT
) 1 << (bitsize
- 1),
5317 to
, 1, OPTAB_LIB_WIDEN
);
5320 emit_move_insn (to
, target
);
5324 if (optab_handler (mov_optab
, GET_MODE (to
)) != CODE_FOR_nothing
)
5326 /* Make a place for a REG_NOTE and add it. */
5327 insn
= emit_move_insn (to
, to
);
5328 set_dst_reg_note (insn
, REG_EQUAL
,
5329 gen_rtx_fmt_e (UNSIGNED_FIX
, GET_MODE (to
),
5337 /* We can't do it with an insn, so use a library call. But first ensure
5338 that the mode of TO is at least as wide as SImode, since those are the
5339 only library calls we know about. */
5341 if (GET_MODE_SIZE (GET_MODE (to
)) < GET_MODE_SIZE (SImode
))
5343 target
= gen_reg_rtx (SImode
);
5345 expand_fix (target
, from
, unsignedp
);
5353 convert_optab tab
= unsignedp
? ufix_optab
: sfix_optab
;
5354 libfunc
= convert_optab_libfunc (tab
, GET_MODE (to
), GET_MODE (from
));
5355 gcc_assert (libfunc
);
5359 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
5360 GET_MODE (to
), 1, from
,
5362 insns
= get_insns ();
5365 emit_libcall_block (insns
, target
, value
,
5366 gen_rtx_fmt_e (unsignedp
? UNSIGNED_FIX
: FIX
,
5367 GET_MODE (to
), from
));
5372 if (GET_MODE (to
) == GET_MODE (target
))
5373 emit_move_insn (to
, target
);
5375 convert_move (to
, target
, 0);
5379 /* Generate code to convert FROM or TO a fixed-point.
5380 If UINTP is true, either TO or FROM is an unsigned integer.
5381 If SATP is true, we need to saturate the result. */
5384 expand_fixed_convert (rtx to
, rtx from
, int uintp
, int satp
)
5386 enum machine_mode to_mode
= GET_MODE (to
);
5387 enum machine_mode from_mode
= GET_MODE (from
);
5389 enum rtx_code this_code
;
5390 enum insn_code code
;
5394 if (to_mode
== from_mode
)
5396 emit_move_insn (to
, from
);
5402 tab
= satp
? satfractuns_optab
: fractuns_optab
;
5403 this_code
= satp
? UNSIGNED_SAT_FRACT
: UNSIGNED_FRACT_CONVERT
;
5407 tab
= satp
? satfract_optab
: fract_optab
;
5408 this_code
= satp
? SAT_FRACT
: FRACT_CONVERT
;
5410 code
= convert_optab_handler (tab
, to_mode
, from_mode
);
5411 if (code
!= CODE_FOR_nothing
)
5413 emit_unop_insn (code
, to
, from
, this_code
);
5417 libfunc
= convert_optab_libfunc (tab
, to_mode
, from_mode
);
5418 gcc_assert (libfunc
);
5421 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
, to_mode
,
5422 1, from
, from_mode
);
5423 insns
= get_insns ();
5426 emit_libcall_block (insns
, to
, value
,
5427 gen_rtx_fmt_e (optab_to_code (tab
), to_mode
, from
));
5430 /* Generate code to convert FROM to fixed point and store in TO. FROM
5431 must be floating point, TO must be signed. Use the conversion optab
5432 TAB to do the conversion. */
5435 expand_sfix_optab (rtx to
, rtx from
, convert_optab tab
)
5437 enum insn_code icode
;
5439 enum machine_mode fmode
, imode
;
5441 /* We first try to find a pair of modes, one real and one integer, at
5442 least as wide as FROM and TO, respectively, in which we can open-code
5443 this conversion. If the integer mode is wider than the mode of TO,
5444 we can do the conversion either signed or unsigned. */
5446 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5447 fmode
= GET_MODE_WIDER_MODE (fmode
))
5448 for (imode
= GET_MODE (to
); imode
!= VOIDmode
;
5449 imode
= GET_MODE_WIDER_MODE (imode
))
5451 icode
= convert_optab_handler (tab
, imode
, fmode
);
5452 if (icode
!= CODE_FOR_nothing
)
5454 rtx last
= get_last_insn ();
5455 if (fmode
!= GET_MODE (from
))
5456 from
= convert_to_mode (fmode
, from
, 0);
5458 if (imode
!= GET_MODE (to
))
5459 target
= gen_reg_rtx (imode
);
5461 if (!maybe_emit_unop_insn (icode
, target
, from
, UNKNOWN
))
5463 delete_insns_since (last
);
5467 convert_move (to
, target
, 0);
5475 /* Report whether we have an instruction to perform the operation
5476 specified by CODE on operands of mode MODE. */
5478 have_insn_for (enum rtx_code code
, enum machine_mode mode
)
5480 return (code_to_optab (code
)
5481 && (optab_handler (code_to_optab (code
), mode
)
5482 != CODE_FOR_nothing
));
5485 /* Initialize the libfunc fields of an entire group of entries in some
5486 optab. Each entry is set equal to a string consisting of a leading
5487 pair of underscores followed by a generic operation name followed by
5488 a mode name (downshifted to lowercase) followed by a single character
5489 representing the number of operands for the given operation (which is
5490 usually one of the characters '2', '3', or '4').
5492 OPTABLE is the table in which libfunc fields are to be initialized.
5493 OPNAME is the generic (string) name of the operation.
5494 SUFFIX is the character which specifies the number of operands for
5495 the given generic operation.
5496 MODE is the mode to generate for.
5500 gen_libfunc (optab optable
, const char *opname
, int suffix
,
5501 enum machine_mode mode
)
5503 unsigned opname_len
= strlen (opname
);
5504 const char *mname
= GET_MODE_NAME (mode
);
5505 unsigned mname_len
= strlen (mname
);
5506 int prefix_len
= targetm
.libfunc_gnu_prefix
? 6 : 2;
5507 int len
= prefix_len
+ opname_len
+ mname_len
+ 1 + 1;
5508 char *libfunc_name
= XALLOCAVEC (char, len
);
5515 if (targetm
.libfunc_gnu_prefix
)
5522 for (q
= opname
; *q
; )
5524 for (q
= mname
; *q
; q
++)
5525 *p
++ = TOLOWER (*q
);
5529 set_optab_libfunc (optable
, mode
,
5530 ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5533 /* Like gen_libfunc, but verify that integer operation is involved. */
5536 gen_int_libfunc (optab optable
, const char *opname
, char suffix
,
5537 enum machine_mode mode
)
5539 int maxsize
= 2 * BITS_PER_WORD
;
5541 if (GET_MODE_CLASS (mode
) != MODE_INT
)
5543 if (maxsize
< LONG_LONG_TYPE_SIZE
)
5544 maxsize
= LONG_LONG_TYPE_SIZE
;
5545 if (GET_MODE_CLASS (mode
) != MODE_INT
5546 || GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
5547 || GET_MODE_BITSIZE (mode
) > maxsize
)
5549 gen_libfunc (optable
, opname
, suffix
, mode
);
5552 /* Like gen_libfunc, but verify that FP and set decimal prefix if needed. */
5555 gen_fp_libfunc (optab optable
, const char *opname
, char suffix
,
5556 enum machine_mode mode
)
5560 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5561 gen_libfunc (optable
, opname
, suffix
, mode
);
5562 if (DECIMAL_FLOAT_MODE_P (mode
))
5564 dec_opname
= XALLOCAVEC (char, sizeof (DECIMAL_PREFIX
) + strlen (opname
));
5565 /* For BID support, change the name to have either a bid_ or dpd_ prefix
5566 depending on the low level floating format used. */
5567 memcpy (dec_opname
, DECIMAL_PREFIX
, sizeof (DECIMAL_PREFIX
) - 1);
5568 strcpy (dec_opname
+ sizeof (DECIMAL_PREFIX
) - 1, opname
);
5569 gen_libfunc (optable
, dec_opname
, suffix
, mode
);
5573 /* Like gen_libfunc, but verify that fixed-point operation is involved. */
5576 gen_fixed_libfunc (optab optable
, const char *opname
, char suffix
,
5577 enum machine_mode mode
)
5579 if (!ALL_FIXED_POINT_MODE_P (mode
))
5581 gen_libfunc (optable
, opname
, suffix
, mode
);
5584 /* Like gen_libfunc, but verify that signed fixed-point operation is
5588 gen_signed_fixed_libfunc (optab optable
, const char *opname
, char suffix
,
5589 enum machine_mode mode
)
5591 if (!SIGNED_FIXED_POINT_MODE_P (mode
))
5593 gen_libfunc (optable
, opname
, suffix
, mode
);
5596 /* Like gen_libfunc, but verify that unsigned fixed-point operation is
5600 gen_unsigned_fixed_libfunc (optab optable
, const char *opname
, char suffix
,
5601 enum machine_mode mode
)
5603 if (!UNSIGNED_FIXED_POINT_MODE_P (mode
))
5605 gen_libfunc (optable
, opname
, suffix
, mode
);
5608 /* Like gen_libfunc, but verify that FP or INT operation is involved. */
5611 gen_int_fp_libfunc (optab optable
, const char *name
, char suffix
,
5612 enum machine_mode mode
)
5614 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5615 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5616 if (INTEGRAL_MODE_P (mode
))
5617 gen_int_libfunc (optable
, name
, suffix
, mode
);
5620 /* Like gen_libfunc, but verify that FP or INT operation is involved
5621 and add 'v' suffix for integer operation. */
5624 gen_intv_fp_libfunc (optab optable
, const char *name
, char suffix
,
5625 enum machine_mode mode
)
5627 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5628 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5629 if (GET_MODE_CLASS (mode
) == MODE_INT
)
5631 int len
= strlen (name
);
5632 char *v_name
= XALLOCAVEC (char, len
+ 2);
5633 strcpy (v_name
, name
);
5635 v_name
[len
+ 1] = 0;
5636 gen_int_libfunc (optable
, v_name
, suffix
, mode
);
5640 /* Like gen_libfunc, but verify that FP or INT or FIXED operation is
5644 gen_int_fp_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5645 enum machine_mode mode
)
5647 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5648 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5649 if (INTEGRAL_MODE_P (mode
))
5650 gen_int_libfunc (optable
, name
, suffix
, mode
);
5651 if (ALL_FIXED_POINT_MODE_P (mode
))
5652 gen_fixed_libfunc (optable
, name
, suffix
, mode
);
5655 /* Like gen_libfunc, but verify that FP or INT or signed FIXED operation is
5659 gen_int_fp_signed_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5660 enum machine_mode mode
)
5662 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5663 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5664 if (INTEGRAL_MODE_P (mode
))
5665 gen_int_libfunc (optable
, name
, suffix
, mode
);
5666 if (SIGNED_FIXED_POINT_MODE_P (mode
))
5667 gen_signed_fixed_libfunc (optable
, name
, suffix
, mode
);
5670 /* Like gen_libfunc, but verify that INT or FIXED operation is
5674 gen_int_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5675 enum machine_mode mode
)
5677 if (INTEGRAL_MODE_P (mode
))
5678 gen_int_libfunc (optable
, name
, suffix
, mode
);
5679 if (ALL_FIXED_POINT_MODE_P (mode
))
5680 gen_fixed_libfunc (optable
, name
, suffix
, mode
);
5683 /* Like gen_libfunc, but verify that INT or signed FIXED operation is
5687 gen_int_signed_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5688 enum machine_mode mode
)
5690 if (INTEGRAL_MODE_P (mode
))
5691 gen_int_libfunc (optable
, name
, suffix
, mode
);
5692 if (SIGNED_FIXED_POINT_MODE_P (mode
))
5693 gen_signed_fixed_libfunc (optable
, name
, suffix
, mode
);
5696 /* Like gen_libfunc, but verify that INT or unsigned FIXED operation is
5700 gen_int_unsigned_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5701 enum machine_mode mode
)
5703 if (INTEGRAL_MODE_P (mode
))
5704 gen_int_libfunc (optable
, name
, suffix
, mode
);
5705 if (UNSIGNED_FIXED_POINT_MODE_P (mode
))
5706 gen_unsigned_fixed_libfunc (optable
, name
, suffix
, mode
);
5709 /* Initialize the libfunc fields of an entire group of entries of an
5710 inter-mode-class conversion optab. The string formation rules are
5711 similar to the ones for init_libfuncs, above, but instead of having
5712 a mode name and an operand count these functions have two mode names
5713 and no operand count. */
5716 gen_interclass_conv_libfunc (convert_optab tab
,
5718 enum machine_mode tmode
,
5719 enum machine_mode fmode
)
5721 size_t opname_len
= strlen (opname
);
5722 size_t mname_len
= 0;
5724 const char *fname
, *tname
;
5726 int prefix_len
= targetm
.libfunc_gnu_prefix
? 6 : 2;
5727 char *libfunc_name
, *suffix
;
5728 char *nondec_name
, *dec_name
, *nondec_suffix
, *dec_suffix
;
5731 /* If this is a decimal conversion, add the current BID vs. DPD prefix that
5732 depends on which underlying decimal floating point format is used. */
5733 const size_t dec_len
= sizeof (DECIMAL_PREFIX
) - 1;
5735 mname_len
= strlen (GET_MODE_NAME (tmode
)) + strlen (GET_MODE_NAME (fmode
));
5737 nondec_name
= XALLOCAVEC (char, prefix_len
+ opname_len
+ mname_len
+ 1 + 1);
5738 nondec_name
[0] = '_';
5739 nondec_name
[1] = '_';
5740 if (targetm
.libfunc_gnu_prefix
)
5742 nondec_name
[2] = 'g';
5743 nondec_name
[3] = 'n';
5744 nondec_name
[4] = 'u';
5745 nondec_name
[5] = '_';
5748 memcpy (&nondec_name
[prefix_len
], opname
, opname_len
);
5749 nondec_suffix
= nondec_name
+ opname_len
+ prefix_len
;
5751 dec_name
= XALLOCAVEC (char, 2 + dec_len
+ opname_len
+ mname_len
+ 1 + 1);
5754 memcpy (&dec_name
[2], DECIMAL_PREFIX
, dec_len
);
5755 memcpy (&dec_name
[2+dec_len
], opname
, opname_len
);
5756 dec_suffix
= dec_name
+ dec_len
+ opname_len
+ 2;
5758 fname
= GET_MODE_NAME (fmode
);
5759 tname
= GET_MODE_NAME (tmode
);
5761 if (DECIMAL_FLOAT_MODE_P (fmode
) || DECIMAL_FLOAT_MODE_P (tmode
))
5763 libfunc_name
= dec_name
;
5764 suffix
= dec_suffix
;
5768 libfunc_name
= nondec_name
;
5769 suffix
= nondec_suffix
;
5773 for (q
= fname
; *q
; p
++, q
++)
5775 for (q
= tname
; *q
; p
++, q
++)
5780 set_conv_libfunc (tab
, tmode
, fmode
,
5781 ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5784 /* Same as gen_interclass_conv_libfunc but verify that we are producing
5785 int->fp conversion. */
5788 gen_int_to_fp_conv_libfunc (convert_optab tab
,
5790 enum machine_mode tmode
,
5791 enum machine_mode fmode
)
5793 if (GET_MODE_CLASS (fmode
) != MODE_INT
)
5795 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (tmode
))
5797 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5800 /* ufloat_optab is special by using floatun for FP and floatuns decimal fp
5804 gen_ufloat_conv_libfunc (convert_optab tab
,
5805 const char *opname ATTRIBUTE_UNUSED
,
5806 enum machine_mode tmode
,
5807 enum machine_mode fmode
)
5809 if (DECIMAL_FLOAT_MODE_P (tmode
))
5810 gen_int_to_fp_conv_libfunc (tab
, "floatuns", tmode
, fmode
);
5812 gen_int_to_fp_conv_libfunc (tab
, "floatun", tmode
, fmode
);
5815 /* Same as gen_interclass_conv_libfunc but verify that we are producing
5816 fp->int conversion. */
5819 gen_int_to_fp_nondecimal_conv_libfunc (convert_optab tab
,
5821 enum machine_mode tmode
,
5822 enum machine_mode fmode
)
5824 if (GET_MODE_CLASS (fmode
) != MODE_INT
)
5826 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
)
5828 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5831 /* Same as gen_interclass_conv_libfunc but verify that we are producing
5832 fp->int conversion with no decimal floating point involved. */
5835 gen_fp_to_int_conv_libfunc (convert_optab tab
,
5837 enum machine_mode tmode
,
5838 enum machine_mode fmode
)
5840 if (GET_MODE_CLASS (fmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (fmode
))
5842 if (GET_MODE_CLASS (tmode
) != MODE_INT
)
5844 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5847 /* Initialize the libfunc fields of an of an intra-mode-class conversion optab.
5848 The string formation rules are
5849 similar to the ones for init_libfunc, above. */
5852 gen_intraclass_conv_libfunc (convert_optab tab
, const char *opname
,
5853 enum machine_mode tmode
, enum machine_mode fmode
)
5855 size_t opname_len
= strlen (opname
);
5856 size_t mname_len
= 0;
5858 const char *fname
, *tname
;
5860 int prefix_len
= targetm
.libfunc_gnu_prefix
? 6 : 2;
5861 char *nondec_name
, *dec_name
, *nondec_suffix
, *dec_suffix
;
5862 char *libfunc_name
, *suffix
;
5865 /* If this is a decimal conversion, add the current BID vs. DPD prefix that
5866 depends on which underlying decimal floating point format is used. */
5867 const size_t dec_len
= sizeof (DECIMAL_PREFIX
) - 1;
5869 mname_len
= strlen (GET_MODE_NAME (tmode
)) + strlen (GET_MODE_NAME (fmode
));
5871 nondec_name
= XALLOCAVEC (char, 2 + opname_len
+ mname_len
+ 1 + 1);
5872 nondec_name
[0] = '_';
5873 nondec_name
[1] = '_';
5874 if (targetm
.libfunc_gnu_prefix
)
5876 nondec_name
[2] = 'g';
5877 nondec_name
[3] = 'n';
5878 nondec_name
[4] = 'u';
5879 nondec_name
[5] = '_';
5881 memcpy (&nondec_name
[prefix_len
], opname
, opname_len
);
5882 nondec_suffix
= nondec_name
+ opname_len
+ prefix_len
;
5884 dec_name
= XALLOCAVEC (char, 2 + dec_len
+ opname_len
+ mname_len
+ 1 + 1);
5887 memcpy (&dec_name
[2], DECIMAL_PREFIX
, dec_len
);
5888 memcpy (&dec_name
[2 + dec_len
], opname
, opname_len
);
5889 dec_suffix
= dec_name
+ dec_len
+ opname_len
+ 2;
5891 fname
= GET_MODE_NAME (fmode
);
5892 tname
= GET_MODE_NAME (tmode
);
5894 if (DECIMAL_FLOAT_MODE_P (fmode
) || DECIMAL_FLOAT_MODE_P (tmode
))
5896 libfunc_name
= dec_name
;
5897 suffix
= dec_suffix
;
5901 libfunc_name
= nondec_name
;
5902 suffix
= nondec_suffix
;
5906 for (q
= fname
; *q
; p
++, q
++)
5908 for (q
= tname
; *q
; p
++, q
++)
5914 set_conv_libfunc (tab
, tmode
, fmode
,
5915 ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5918 /* Pick proper libcall for trunc_optab. We need to chose if we do
5919 truncation or extension and interclass or intraclass. */
5922 gen_trunc_conv_libfunc (convert_optab tab
,
5924 enum machine_mode tmode
,
5925 enum machine_mode fmode
)
5927 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (tmode
))
5929 if (GET_MODE_CLASS (fmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (fmode
))
5934 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (fmode
))
5935 || (GET_MODE_CLASS (fmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (tmode
)))
5936 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5938 if (GET_MODE_PRECISION (fmode
) <= GET_MODE_PRECISION (tmode
))
5941 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
5942 && GET_MODE_CLASS (fmode
) == MODE_FLOAT
)
5943 || (DECIMAL_FLOAT_MODE_P (fmode
) && DECIMAL_FLOAT_MODE_P (tmode
)))
5944 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5947 /* Pick proper libcall for extend_optab. We need to chose if we do
5948 truncation or extension and interclass or intraclass. */
5951 gen_extend_conv_libfunc (convert_optab tab
,
5952 const char *opname ATTRIBUTE_UNUSED
,
5953 enum machine_mode tmode
,
5954 enum machine_mode fmode
)
5956 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (tmode
))
5958 if (GET_MODE_CLASS (fmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (fmode
))
5963 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (fmode
))
5964 || (GET_MODE_CLASS (fmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (tmode
)))
5965 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5967 if (GET_MODE_PRECISION (fmode
) > GET_MODE_PRECISION (tmode
))
5970 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
5971 && GET_MODE_CLASS (fmode
) == MODE_FLOAT
)
5972 || (DECIMAL_FLOAT_MODE_P (fmode
) && DECIMAL_FLOAT_MODE_P (tmode
)))
5973 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5976 /* Pick proper libcall for fract_optab. We need to chose if we do
5977 interclass or intraclass. */
5980 gen_fract_conv_libfunc (convert_optab tab
,
5982 enum machine_mode tmode
,
5983 enum machine_mode fmode
)
5987 if (!(ALL_FIXED_POINT_MODE_P (tmode
) || ALL_FIXED_POINT_MODE_P (fmode
)))
5990 if (GET_MODE_CLASS (tmode
) == GET_MODE_CLASS (fmode
))
5991 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5993 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5996 /* Pick proper libcall for fractuns_optab. */
5999 gen_fractuns_conv_libfunc (convert_optab tab
,
6001 enum machine_mode tmode
,
6002 enum machine_mode fmode
)
6006 /* One mode must be a fixed-point mode, and the other must be an integer
6008 if (!((ALL_FIXED_POINT_MODE_P (tmode
) && GET_MODE_CLASS (fmode
) == MODE_INT
)
6009 || (ALL_FIXED_POINT_MODE_P (fmode
)
6010 && GET_MODE_CLASS (tmode
) == MODE_INT
)))
6013 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6016 /* Pick proper libcall for satfract_optab. We need to chose if we do
6017 interclass or intraclass. */
6020 gen_satfract_conv_libfunc (convert_optab tab
,
6022 enum machine_mode tmode
,
6023 enum machine_mode fmode
)
6027 /* TMODE must be a fixed-point mode. */
6028 if (!ALL_FIXED_POINT_MODE_P (tmode
))
6031 if (GET_MODE_CLASS (tmode
) == GET_MODE_CLASS (fmode
))
6032 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6034 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6037 /* Pick proper libcall for satfractuns_optab. */
6040 gen_satfractuns_conv_libfunc (convert_optab tab
,
6042 enum machine_mode tmode
,
6043 enum machine_mode fmode
)
6047 /* TMODE must be a fixed-point mode, and FMODE must be an integer mode. */
6048 if (!(ALL_FIXED_POINT_MODE_P (tmode
) && GET_MODE_CLASS (fmode
) == MODE_INT
))
6051 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6054 /* A table of previously-created libfuncs, hashed by name. */
6055 static GTY ((param_is (union tree_node
))) htab_t libfunc_decls
;
6057 /* Hashtable callbacks for libfunc_decls. */
6060 libfunc_decl_hash (const void *entry
)
6062 return IDENTIFIER_HASH_VALUE (DECL_NAME ((const_tree
) entry
));
6066 libfunc_decl_eq (const void *entry1
, const void *entry2
)
6068 return DECL_NAME ((const_tree
) entry1
) == (const_tree
) entry2
;
6071 /* Build a decl for a libfunc named NAME. */
6074 build_libfunc_function (const char *name
)
6076 tree decl
= build_decl (UNKNOWN_LOCATION
, FUNCTION_DECL
,
6077 get_identifier (name
),
6078 build_function_type (integer_type_node
, NULL_TREE
));
6079 /* ??? We don't have any type information except for this is
6080 a function. Pretend this is "int foo()". */
6081 DECL_ARTIFICIAL (decl
) = 1;
6082 DECL_EXTERNAL (decl
) = 1;
6083 TREE_PUBLIC (decl
) = 1;
6084 gcc_assert (DECL_ASSEMBLER_NAME (decl
));
6086 /* Zap the nonsensical SYMBOL_REF_DECL for this. What we're left with
6087 are the flags assigned by targetm.encode_section_info. */
6088 SET_SYMBOL_REF_DECL (XEXP (DECL_RTL (decl
), 0), NULL
);
6094 init_one_libfunc (const char *name
)
6100 if (libfunc_decls
== NULL
)
6101 libfunc_decls
= htab_create_ggc (37, libfunc_decl_hash
,
6102 libfunc_decl_eq
, NULL
);
6104 /* See if we have already created a libfunc decl for this function. */
6105 id
= get_identifier (name
);
6106 hash
= IDENTIFIER_HASH_VALUE (id
);
6107 slot
= htab_find_slot_with_hash (libfunc_decls
, id
, hash
, INSERT
);
6108 decl
= (tree
) *slot
;
6111 /* Create a new decl, so that it can be passed to
6112 targetm.encode_section_info. */
6113 decl
= build_libfunc_function (name
);
6116 return XEXP (DECL_RTL (decl
), 0);
6119 /* Adjust the assembler name of libfunc NAME to ASMSPEC. */
6122 set_user_assembler_libfunc (const char *name
, const char *asmspec
)
6128 id
= get_identifier (name
);
6129 hash
= IDENTIFIER_HASH_VALUE (id
);
6130 slot
= htab_find_slot_with_hash (libfunc_decls
, id
, hash
, NO_INSERT
);
6132 decl
= (tree
) *slot
;
6133 set_user_assembler_name (decl
, asmspec
);
6134 return XEXP (DECL_RTL (decl
), 0);
6137 /* Call this to reset the function entry for one optab (OPTABLE) in mode
6138 MODE to NAME, which should be either 0 or a string constant. */
6140 set_optab_libfunc (optab op
, enum machine_mode mode
, const char *name
)
6143 struct libfunc_entry e
;
6144 struct libfunc_entry
**slot
;
6151 val
= init_one_libfunc (name
);
6154 slot
= (struct libfunc_entry
**) htab_find_slot (libfunc_hash
, &e
, INSERT
);
6156 *slot
= ggc_alloc_libfunc_entry ();
6158 (*slot
)->mode1
= mode
;
6159 (*slot
)->mode2
= VOIDmode
;
6160 (*slot
)->libfunc
= val
;
6163 /* Call this to reset the function entry for one conversion optab
6164 (OPTABLE) from mode FMODE to mode TMODE to NAME, which should be
6165 either 0 or a string constant. */
6167 set_conv_libfunc (convert_optab optab
, enum machine_mode tmode
,
6168 enum machine_mode fmode
, const char *name
)
6171 struct libfunc_entry e
;
6172 struct libfunc_entry
**slot
;
6179 val
= init_one_libfunc (name
);
6182 slot
= (struct libfunc_entry
**) htab_find_slot (libfunc_hash
, &e
, INSERT
);
6184 *slot
= ggc_alloc_libfunc_entry ();
6185 (*slot
)->op
= optab
;
6186 (*slot
)->mode1
= tmode
;
6187 (*slot
)->mode2
= fmode
;
6188 (*slot
)->libfunc
= val
;
6191 /* Call this to initialize the contents of the optabs
6192 appropriately for the current target machine. */
6198 htab_empty (libfunc_hash
);
6200 libfunc_hash
= htab_create_ggc (10, hash_libfunc
, eq_libfunc
, NULL
);
6202 /* Fill in the optabs with the insns we support. */
6203 init_all_optabs (this_fn_optabs
);
6205 /* The ffs function operates on `int'. Fall back on it if we do not
6206 have a libgcc2 function for that width. */
6207 if (INT_TYPE_SIZE
< BITS_PER_WORD
)
6208 set_optab_libfunc (ffs_optab
, mode_for_size (INT_TYPE_SIZE
, MODE_INT
, 0),
6211 /* Explicitly initialize the bswap libfuncs since we need them to be
6212 valid for things other than word_mode. */
6213 if (targetm
.libfunc_gnu_prefix
)
6215 set_optab_libfunc (bswap_optab
, SImode
, "__gnu_bswapsi2");
6216 set_optab_libfunc (bswap_optab
, DImode
, "__gnu_bswapdi2");
6220 set_optab_libfunc (bswap_optab
, SImode
, "__bswapsi2");
6221 set_optab_libfunc (bswap_optab
, DImode
, "__bswapdi2");
6224 /* Use cabs for double complex abs, since systems generally have cabs.
6225 Don't define any libcall for float complex, so that cabs will be used. */
6226 if (complex_double_type_node
)
6227 set_optab_libfunc (abs_optab
, TYPE_MODE (complex_double_type_node
),
6230 abort_libfunc
= init_one_libfunc ("abort");
6231 memcpy_libfunc
= init_one_libfunc ("memcpy");
6232 memmove_libfunc
= init_one_libfunc ("memmove");
6233 memcmp_libfunc
= init_one_libfunc ("memcmp");
6234 memset_libfunc
= init_one_libfunc ("memset");
6235 setbits_libfunc
= init_one_libfunc ("__setbits");
6237 #ifndef DONT_USE_BUILTIN_SETJMP
6238 setjmp_libfunc
= init_one_libfunc ("__builtin_setjmp");
6239 longjmp_libfunc
= init_one_libfunc ("__builtin_longjmp");
6241 setjmp_libfunc
= init_one_libfunc ("setjmp");
6242 longjmp_libfunc
= init_one_libfunc ("longjmp");
6244 unwind_sjlj_register_libfunc
= init_one_libfunc ("_Unwind_SjLj_Register");
6245 unwind_sjlj_unregister_libfunc
6246 = init_one_libfunc ("_Unwind_SjLj_Unregister");
6248 /* For function entry/exit instrumentation. */
6249 profile_function_entry_libfunc
6250 = init_one_libfunc ("__cyg_profile_func_enter");
6251 profile_function_exit_libfunc
6252 = init_one_libfunc ("__cyg_profile_func_exit");
6254 gcov_flush_libfunc
= init_one_libfunc ("__gcov_flush");
6256 /* Allow the target to add more libcalls or rename some, etc. */
6257 targetm
.init_libfuncs ();
6260 /* Use the current target and options to initialize
6261 TREE_OPTIMIZATION_OPTABS (OPTNODE). */
6264 init_tree_optimization_optabs (tree optnode
)
6266 /* Quick exit if we have already computed optabs for this target. */
6267 if (TREE_OPTIMIZATION_BASE_OPTABS (optnode
) == this_target_optabs
)
6270 /* Forget any previous information and set up for the current target. */
6271 TREE_OPTIMIZATION_BASE_OPTABS (optnode
) = this_target_optabs
;
6272 struct target_optabs
*tmp_optabs
= (struct target_optabs
*)
6273 TREE_OPTIMIZATION_OPTABS (optnode
);
6275 memset (tmp_optabs
, 0, sizeof (struct target_optabs
));
6277 tmp_optabs
= (struct target_optabs
*)
6278 ggc_alloc_atomic (sizeof (struct target_optabs
));
6280 /* Generate a new set of optabs into tmp_optabs. */
6281 init_all_optabs (tmp_optabs
);
6283 /* If the optabs changed, record it. */
6284 if (memcmp (tmp_optabs
, this_target_optabs
, sizeof (struct target_optabs
)))
6285 TREE_OPTIMIZATION_OPTABS (optnode
) = tmp_optabs
;
6288 TREE_OPTIMIZATION_OPTABS (optnode
) = NULL
;
6289 ggc_free (tmp_optabs
);
6293 /* A helper function for init_sync_libfuncs. Using the basename BASE,
6294 install libfuncs into TAB for BASE_N for 1 <= N <= MAX. */
6297 init_sync_libfuncs_1 (optab tab
, const char *base
, int max
)
6299 enum machine_mode mode
;
6301 size_t len
= strlen (base
);
6304 gcc_assert (max
<= 8);
6305 gcc_assert (len
+ 3 < sizeof (buf
));
6307 memcpy (buf
, base
, len
);
6310 buf
[len
+ 2] = '\0';
6313 for (i
= 1; i
<= max
; i
*= 2)
6315 buf
[len
+ 1] = '0' + i
;
6316 set_optab_libfunc (tab
, mode
, buf
);
6317 mode
= GET_MODE_2XWIDER_MODE (mode
);
6322 init_sync_libfuncs (int max
)
6324 if (!flag_sync_libcalls
)
6327 init_sync_libfuncs_1 (sync_compare_and_swap_optab
,
6328 "__sync_val_compare_and_swap", max
);
6329 init_sync_libfuncs_1 (sync_lock_test_and_set_optab
,
6330 "__sync_lock_test_and_set", max
);
6332 init_sync_libfuncs_1 (sync_old_add_optab
, "__sync_fetch_and_add", max
);
6333 init_sync_libfuncs_1 (sync_old_sub_optab
, "__sync_fetch_and_sub", max
);
6334 init_sync_libfuncs_1 (sync_old_ior_optab
, "__sync_fetch_and_or", max
);
6335 init_sync_libfuncs_1 (sync_old_and_optab
, "__sync_fetch_and_and", max
);
6336 init_sync_libfuncs_1 (sync_old_xor_optab
, "__sync_fetch_and_xor", max
);
6337 init_sync_libfuncs_1 (sync_old_nand_optab
, "__sync_fetch_and_nand", max
);
6339 init_sync_libfuncs_1 (sync_new_add_optab
, "__sync_add_and_fetch", max
);
6340 init_sync_libfuncs_1 (sync_new_sub_optab
, "__sync_sub_and_fetch", max
);
6341 init_sync_libfuncs_1 (sync_new_ior_optab
, "__sync_or_and_fetch", max
);
6342 init_sync_libfuncs_1 (sync_new_and_optab
, "__sync_and_and_fetch", max
);
6343 init_sync_libfuncs_1 (sync_new_xor_optab
, "__sync_xor_and_fetch", max
);
6344 init_sync_libfuncs_1 (sync_new_nand_optab
, "__sync_nand_and_fetch", max
);
6347 /* Print information about the current contents of the optabs on
6351 debug_optab_libfuncs (void)
6355 /* Dump the arithmetic optabs. */
6356 for (i
= FIRST_NORM_OPTAB
; i
<= LAST_NORMLIB_OPTAB
; ++i
)
6357 for (j
= 0; j
< NUM_MACHINE_MODES
; ++j
)
6359 rtx l
= optab_libfunc ((optab
) i
, (enum machine_mode
) j
);
6362 gcc_assert (GET_CODE (l
) == SYMBOL_REF
);
6363 fprintf (stderr
, "%s\t%s:\t%s\n",
6364 GET_RTX_NAME (optab_to_code ((optab
) i
)),
6370 /* Dump the conversion optabs. */
6371 for (i
= FIRST_CONV_OPTAB
; i
<= LAST_CONVLIB_OPTAB
; ++i
)
6372 for (j
= 0; j
< NUM_MACHINE_MODES
; ++j
)
6373 for (k
= 0; k
< NUM_MACHINE_MODES
; ++k
)
6375 rtx l
= convert_optab_libfunc ((optab
) i
, (enum machine_mode
) j
,
6376 (enum machine_mode
) k
);
6379 gcc_assert (GET_CODE (l
) == SYMBOL_REF
);
6380 fprintf (stderr
, "%s\t%s\t%s:\t%s\n",
6381 GET_RTX_NAME (optab_to_code ((optab
) i
)),
6390 /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition
6391 CODE. Return 0 on failure. */
6394 gen_cond_trap (enum rtx_code code
, rtx op1
, rtx op2
, rtx tcode
)
6396 enum machine_mode mode
= GET_MODE (op1
);
6397 enum insn_code icode
;
6401 if (mode
== VOIDmode
)
6404 icode
= optab_handler (ctrap_optab
, mode
);
6405 if (icode
== CODE_FOR_nothing
)
6408 /* Some targets only accept a zero trap code. */
6409 if (!insn_operand_matches (icode
, 3, tcode
))
6412 do_pending_stack_adjust ();
6414 prepare_cmp_insn (op1
, op2
, code
, NULL_RTX
, false, OPTAB_DIRECT
,
6419 insn
= GEN_FCN (icode
) (trap_rtx
, XEXP (trap_rtx
, 0), XEXP (trap_rtx
, 1),
6422 /* If that failed, then give up. */
6430 insn
= get_insns ();
6435 /* Return rtx code for TCODE. Use UNSIGNEDP to select signed
6436 or unsigned operation code. */
6438 static enum rtx_code
6439 get_rtx_code (enum tree_code tcode
, bool unsignedp
)
6451 code
= unsignedp
? LTU
: LT
;
6454 code
= unsignedp
? LEU
: LE
;
6457 code
= unsignedp
? GTU
: GT
;
6460 code
= unsignedp
? GEU
: GE
;
6463 case UNORDERED_EXPR
:
6494 /* Return comparison rtx for COND. Use UNSIGNEDP to select signed or
6495 unsigned operators. Do not generate compare instruction. */
6498 vector_compare_rtx (enum tree_code tcode
, tree t_op0
, tree t_op1
,
6499 bool unsignedp
, enum insn_code icode
)
6501 struct expand_operand ops
[2];
6502 rtx rtx_op0
, rtx_op1
;
6503 enum rtx_code rcode
= get_rtx_code (tcode
, unsignedp
);
6505 gcc_assert (TREE_CODE_CLASS (tcode
) == tcc_comparison
);
6507 /* Expand operands. */
6508 rtx_op0
= expand_expr (t_op0
, NULL_RTX
, TYPE_MODE (TREE_TYPE (t_op0
)),
6510 rtx_op1
= expand_expr (t_op1
, NULL_RTX
, TYPE_MODE (TREE_TYPE (t_op1
)),
6513 create_input_operand (&ops
[0], rtx_op0
, GET_MODE (rtx_op0
));
6514 create_input_operand (&ops
[1], rtx_op1
, GET_MODE (rtx_op1
));
6515 if (!maybe_legitimize_operands (icode
, 4, 2, ops
))
6517 return gen_rtx_fmt_ee (rcode
, VOIDmode
, ops
[0].value
, ops
[1].value
);
6520 /* Return true if VEC_PERM_EXPR can be expanded using SIMD extensions
6521 of the CPU. SEL may be NULL, which stands for an unknown constant. */
6524 can_vec_perm_p (enum machine_mode mode
, bool variable
,
6525 const unsigned char *sel
)
6527 enum machine_mode qimode
;
6529 /* If the target doesn't implement a vector mode for the vector type,
6530 then no operations are supported. */
6531 if (!VECTOR_MODE_P (mode
))
6536 if (direct_optab_handler (vec_perm_const_optab
, mode
) != CODE_FOR_nothing
6538 || targetm
.vectorize
.vec_perm_const_ok
== NULL
6539 || targetm
.vectorize
.vec_perm_const_ok (mode
, sel
)))
6543 if (direct_optab_handler (vec_perm_optab
, mode
) != CODE_FOR_nothing
)
6546 /* We allow fallback to a QI vector mode, and adjust the mask. */
6547 if (GET_MODE_INNER (mode
) == QImode
)
6549 qimode
= mode_for_vector (QImode
, GET_MODE_SIZE (mode
));
6550 if (!VECTOR_MODE_P (qimode
))
6553 /* ??? For completeness, we ought to check the QImode version of
6554 vec_perm_const_optab. But all users of this implicit lowering
6555 feature implement the variable vec_perm_optab. */
6556 if (direct_optab_handler (vec_perm_optab
, qimode
) == CODE_FOR_nothing
)
6559 /* In order to support the lowering of variable permutations,
6560 we need to support shifts and adds. */
6563 if (GET_MODE_UNIT_SIZE (mode
) > 2
6564 && optab_handler (ashl_optab
, mode
) == CODE_FOR_nothing
6565 && optab_handler (vashl_optab
, mode
) == CODE_FOR_nothing
)
6567 if (optab_handler (add_optab
, qimode
) == CODE_FOR_nothing
)
6574 /* A subroutine of expand_vec_perm for expanding one vec_perm insn. */
6577 expand_vec_perm_1 (enum insn_code icode
, rtx target
,
6578 rtx v0
, rtx v1
, rtx sel
)
6580 enum machine_mode tmode
= GET_MODE (target
);
6581 enum machine_mode smode
= GET_MODE (sel
);
6582 struct expand_operand ops
[4];
6584 create_output_operand (&ops
[0], target
, tmode
);
6585 create_input_operand (&ops
[3], sel
, smode
);
6587 /* Make an effort to preserve v0 == v1. The target expander is able to
6588 rely on this to determine if we're permuting a single input operand. */
6589 if (rtx_equal_p (v0
, v1
))
6591 if (!insn_operand_matches (icode
, 1, v0
))
6592 v0
= force_reg (tmode
, v0
);
6593 gcc_checking_assert (insn_operand_matches (icode
, 1, v0
));
6594 gcc_checking_assert (insn_operand_matches (icode
, 2, v0
));
6596 create_fixed_operand (&ops
[1], v0
);
6597 create_fixed_operand (&ops
[2], v0
);
6601 create_input_operand (&ops
[1], v0
, tmode
);
6602 create_input_operand (&ops
[2], v1
, tmode
);
6605 if (maybe_expand_insn (icode
, 4, ops
))
6606 return ops
[0].value
;
6610 /* Generate instructions for vec_perm optab given its mode
6611 and three operands. */
6614 expand_vec_perm (enum machine_mode mode
, rtx v0
, rtx v1
, rtx sel
, rtx target
)
6616 enum insn_code icode
;
6617 enum machine_mode qimode
;
6618 unsigned int i
, w
, e
, u
;
6619 rtx tmp
, sel_qi
= NULL
;
6622 if (!target
|| GET_MODE (target
) != mode
)
6623 target
= gen_reg_rtx (mode
);
6625 w
= GET_MODE_SIZE (mode
);
6626 e
= GET_MODE_NUNITS (mode
);
6627 u
= GET_MODE_UNIT_SIZE (mode
);
6629 /* Set QIMODE to a different vector mode with byte elements.
6630 If no such mode, or if MODE already has byte elements, use VOIDmode. */
6632 if (GET_MODE_INNER (mode
) != QImode
)
6634 qimode
= mode_for_vector (QImode
, w
);
6635 if (!VECTOR_MODE_P (qimode
))
6639 /* If the input is a constant, expand it specially. */
6640 gcc_assert (GET_MODE_CLASS (GET_MODE (sel
)) == MODE_VECTOR_INT
);
6641 if (GET_CODE (sel
) == CONST_VECTOR
)
6643 icode
= direct_optab_handler (vec_perm_const_optab
, mode
);
6644 if (icode
!= CODE_FOR_nothing
)
6646 tmp
= expand_vec_perm_1 (icode
, target
, v0
, v1
, sel
);
6651 /* Fall back to a constant byte-based permutation. */
6652 if (qimode
!= VOIDmode
)
6654 vec
= rtvec_alloc (w
);
6655 for (i
= 0; i
< e
; ++i
)
6657 unsigned int j
, this_e
;
6659 this_e
= INTVAL (CONST_VECTOR_ELT (sel
, i
));
6660 this_e
&= 2 * e
- 1;
6663 for (j
= 0; j
< u
; ++j
)
6664 RTVEC_ELT (vec
, i
* u
+ j
) = GEN_INT (this_e
+ j
);
6666 sel_qi
= gen_rtx_CONST_VECTOR (qimode
, vec
);
6668 icode
= direct_optab_handler (vec_perm_const_optab
, qimode
);
6669 if (icode
!= CODE_FOR_nothing
)
6671 tmp
= mode
!= qimode
? gen_reg_rtx (qimode
) : target
;
6672 tmp
= expand_vec_perm_1 (icode
, tmp
, gen_lowpart (qimode
, v0
),
6673 gen_lowpart (qimode
, v1
), sel_qi
);
6675 return gen_lowpart (mode
, tmp
);
6680 /* Otherwise expand as a fully variable permuation. */
6681 icode
= direct_optab_handler (vec_perm_optab
, mode
);
6682 if (icode
!= CODE_FOR_nothing
)
6684 tmp
= expand_vec_perm_1 (icode
, target
, v0
, v1
, sel
);
6689 /* As a special case to aid several targets, lower the element-based
6690 permutation to a byte-based permutation and try again. */
6691 if (qimode
== VOIDmode
)
6693 icode
= direct_optab_handler (vec_perm_optab
, qimode
);
6694 if (icode
== CODE_FOR_nothing
)
6699 /* Multiply each element by its byte size. */
6700 enum machine_mode selmode
= GET_MODE (sel
);
6702 sel
= expand_simple_binop (selmode
, PLUS
, sel
, sel
,
6703 sel
, 0, OPTAB_DIRECT
);
6705 sel
= expand_simple_binop (selmode
, ASHIFT
, sel
,
6706 GEN_INT (exact_log2 (u
)),
6707 sel
, 0, OPTAB_DIRECT
);
6708 gcc_assert (sel
!= NULL
);
6710 /* Broadcast the low byte each element into each of its bytes. */
6711 vec
= rtvec_alloc (w
);
6712 for (i
= 0; i
< w
; ++i
)
6714 int this_e
= i
/ u
* u
;
6715 if (BYTES_BIG_ENDIAN
)
6717 RTVEC_ELT (vec
, i
) = GEN_INT (this_e
);
6719 tmp
= gen_rtx_CONST_VECTOR (qimode
, vec
);
6720 sel
= gen_lowpart (qimode
, sel
);
6721 sel
= expand_vec_perm (qimode
, sel
, sel
, tmp
, NULL
);
6722 gcc_assert (sel
!= NULL
);
6724 /* Add the byte offset to each byte element. */
6725 /* Note that the definition of the indicies here is memory ordering,
6726 so there should be no difference between big and little endian. */
6727 vec
= rtvec_alloc (w
);
6728 for (i
= 0; i
< w
; ++i
)
6729 RTVEC_ELT (vec
, i
) = GEN_INT (i
% u
);
6730 tmp
= gen_rtx_CONST_VECTOR (qimode
, vec
);
6731 sel_qi
= expand_simple_binop (qimode
, PLUS
, sel
, tmp
,
6732 sel
, 0, OPTAB_DIRECT
);
6733 gcc_assert (sel_qi
!= NULL
);
6736 tmp
= mode
!= qimode
? gen_reg_rtx (qimode
) : target
;
6737 tmp
= expand_vec_perm_1 (icode
, tmp
, gen_lowpart (qimode
, v0
),
6738 gen_lowpart (qimode
, v1
), sel_qi
);
6740 tmp
= gen_lowpart (mode
, tmp
);
6744 /* Return insn code for a conditional operator with a comparison in
6745 mode CMODE, unsigned if UNS is true, resulting in a value of mode VMODE. */
6747 static inline enum insn_code
6748 get_vcond_icode (enum machine_mode vmode
, enum machine_mode cmode
, bool uns
)
6750 enum insn_code icode
= CODE_FOR_nothing
;
6752 icode
= convert_optab_handler (vcondu_optab
, vmode
, cmode
);
6754 icode
= convert_optab_handler (vcond_optab
, vmode
, cmode
);
6758 /* Return TRUE iff, appropriate vector insns are available
6759 for vector cond expr with vector type VALUE_TYPE and a comparison
6760 with operand vector types in CMP_OP_TYPE. */
6763 expand_vec_cond_expr_p (tree value_type
, tree cmp_op_type
)
6765 enum machine_mode value_mode
= TYPE_MODE (value_type
);
6766 enum machine_mode cmp_op_mode
= TYPE_MODE (cmp_op_type
);
6767 if (GET_MODE_SIZE (value_mode
) != GET_MODE_SIZE (cmp_op_mode
)
6768 || GET_MODE_NUNITS (value_mode
) != GET_MODE_NUNITS (cmp_op_mode
)
6769 || get_vcond_icode (TYPE_MODE (value_type
), TYPE_MODE (cmp_op_type
),
6770 TYPE_UNSIGNED (cmp_op_type
)) == CODE_FOR_nothing
)
6775 /* Generate insns for a VEC_COND_EXPR, given its TYPE and its
6779 expand_vec_cond_expr (tree vec_cond_type
, tree op0
, tree op1
, tree op2
,
6782 struct expand_operand ops
[6];
6783 enum insn_code icode
;
6784 rtx comparison
, rtx_op1
, rtx_op2
;
6785 enum machine_mode mode
= TYPE_MODE (vec_cond_type
);
6786 enum machine_mode cmp_op_mode
;
6789 enum tree_code tcode
;
6791 if (COMPARISON_CLASS_P (op0
))
6793 op0a
= TREE_OPERAND (op0
, 0);
6794 op0b
= TREE_OPERAND (op0
, 1);
6795 tcode
= TREE_CODE (op0
);
6800 gcc_assert (!TYPE_UNSIGNED (TREE_TYPE (op0
)));
6802 op0b
= build_zero_cst (TREE_TYPE (op0
));
6805 unsignedp
= TYPE_UNSIGNED (TREE_TYPE (op0a
));
6806 cmp_op_mode
= TYPE_MODE (TREE_TYPE (op0a
));
6809 gcc_assert (GET_MODE_SIZE (mode
) == GET_MODE_SIZE (cmp_op_mode
)
6810 && GET_MODE_NUNITS (mode
) == GET_MODE_NUNITS (cmp_op_mode
));
6812 icode
= get_vcond_icode (mode
, cmp_op_mode
, unsignedp
);
6813 if (icode
== CODE_FOR_nothing
)
6816 comparison
= vector_compare_rtx (tcode
, op0a
, op0b
, unsignedp
, icode
);
6817 rtx_op1
= expand_normal (op1
);
6818 rtx_op2
= expand_normal (op2
);
6820 create_output_operand (&ops
[0], target
, mode
);
6821 create_input_operand (&ops
[1], rtx_op1
, mode
);
6822 create_input_operand (&ops
[2], rtx_op2
, mode
);
6823 create_fixed_operand (&ops
[3], comparison
);
6824 create_fixed_operand (&ops
[4], XEXP (comparison
, 0));
6825 create_fixed_operand (&ops
[5], XEXP (comparison
, 1));
6826 expand_insn (icode
, 6, ops
);
6827 return ops
[0].value
;
6830 /* Return non-zero if a highpart multiply is supported of can be synthisized.
6831 For the benefit of expand_mult_highpart, the return value is 1 for direct,
6832 2 for even/odd widening, and 3 for hi/lo widening. */
6835 can_mult_highpart_p (enum machine_mode mode
, bool uns_p
)
6841 op
= uns_p
? umul_highpart_optab
: smul_highpart_optab
;
6842 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6845 /* If the mode is an integral vector, synth from widening operations. */
6846 if (GET_MODE_CLASS (mode
) != MODE_VECTOR_INT
)
6849 nunits
= GET_MODE_NUNITS (mode
);
6850 sel
= XALLOCAVEC (unsigned char, nunits
);
6852 op
= uns_p
? vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
6853 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6855 op
= uns_p
? vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
6856 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6858 for (i
= 0; i
< nunits
; ++i
)
6859 sel
[i
] = !BYTES_BIG_ENDIAN
+ (i
& ~1) + ((i
& 1) ? nunits
: 0);
6860 if (can_vec_perm_p (mode
, false, sel
))
6865 op
= uns_p
? vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
6866 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6868 op
= uns_p
? vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
6869 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6871 for (i
= 0; i
< nunits
; ++i
)
6872 sel
[i
] = 2 * i
+ (BYTES_BIG_ENDIAN
? 0 : 1);
6873 if (can_vec_perm_p (mode
, false, sel
))
6881 /* Expand a highpart multiply. */
6884 expand_mult_highpart (enum machine_mode mode
, rtx op0
, rtx op1
,
6885 rtx target
, bool uns_p
)
6887 struct expand_operand eops
[3];
6888 enum insn_code icode
;
6889 int method
, i
, nunits
;
6890 enum machine_mode wmode
;
6895 method
= can_mult_highpart_p (mode
, uns_p
);
6901 tab1
= uns_p
? umul_highpart_optab
: smul_highpart_optab
;
6902 return expand_binop (mode
, tab1
, op0
, op1
, target
, uns_p
,
6905 tab1
= uns_p
? vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
6906 tab2
= uns_p
? vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
6909 tab1
= uns_p
? vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
6910 tab2
= uns_p
? vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
6911 if (BYTES_BIG_ENDIAN
)
6922 icode
= optab_handler (tab1
, mode
);
6923 nunits
= GET_MODE_NUNITS (mode
);
6924 wmode
= insn_data
[icode
].operand
[0].mode
;
6925 gcc_checking_assert (2 * GET_MODE_NUNITS (wmode
) == nunits
);
6926 gcc_checking_assert (GET_MODE_SIZE (wmode
) == GET_MODE_SIZE (mode
));
6928 create_output_operand (&eops
[0], gen_reg_rtx (wmode
), wmode
);
6929 create_input_operand (&eops
[1], op0
, mode
);
6930 create_input_operand (&eops
[2], op1
, mode
);
6931 expand_insn (icode
, 3, eops
);
6932 m1
= gen_lowpart (mode
, eops
[0].value
);
6934 create_output_operand (&eops
[0], gen_reg_rtx (wmode
), wmode
);
6935 create_input_operand (&eops
[1], op0
, mode
);
6936 create_input_operand (&eops
[2], op1
, mode
);
6937 expand_insn (optab_handler (tab2
, mode
), 3, eops
);
6938 m2
= gen_lowpart (mode
, eops
[0].value
);
6940 v
= rtvec_alloc (nunits
);
6943 for (i
= 0; i
< nunits
; ++i
)
6944 RTVEC_ELT (v
, i
) = GEN_INT (!BYTES_BIG_ENDIAN
+ (i
& ~1)
6945 + ((i
& 1) ? nunits
: 0));
6949 for (i
= 0; i
< nunits
; ++i
)
6950 RTVEC_ELT (v
, i
) = GEN_INT (2 * i
+ (BYTES_BIG_ENDIAN
? 0 : 1));
6952 perm
= gen_rtx_CONST_VECTOR (mode
, v
);
6954 return expand_vec_perm (mode
, m1
, m2
, perm
, target
);
6957 /* Return true if target supports vector masked load/store for mode. */
6959 can_vec_mask_load_store_p (enum machine_mode mode
, bool is_load
)
6961 optab op
= is_load
? maskload_optab
: maskstore_optab
;
6962 enum machine_mode vmode
;
6963 unsigned int vector_sizes
;
6965 /* If mode is vector mode, check it directly. */
6966 if (VECTOR_MODE_P (mode
))
6967 return optab_handler (op
, mode
) != CODE_FOR_nothing
;
6969 /* Otherwise, return true if there is some vector mode with
6970 the mask load/store supported. */
6972 /* See if there is any chance the mask load or store might be
6973 vectorized. If not, punt. */
6974 vmode
= targetm
.vectorize
.preferred_simd_mode (mode
);
6975 if (!VECTOR_MODE_P (vmode
))
6978 if (optab_handler (op
, vmode
) != CODE_FOR_nothing
)
6981 vector_sizes
= targetm
.vectorize
.autovectorize_vector_sizes ();
6982 while (vector_sizes
!= 0)
6984 unsigned int cur
= 1 << floor_log2 (vector_sizes
);
6985 vector_sizes
&= ~cur
;
6986 if (cur
<= GET_MODE_SIZE (mode
))
6988 vmode
= mode_for_vector (mode
, cur
/ GET_MODE_SIZE (mode
));
6989 if (VECTOR_MODE_P (vmode
)
6990 && optab_handler (op
, vmode
) != CODE_FOR_nothing
)
6996 /* Return true if there is a compare_and_swap pattern. */
6999 can_compare_and_swap_p (enum machine_mode mode
, bool allow_libcall
)
7001 enum insn_code icode
;
7003 /* Check for __atomic_compare_and_swap. */
7004 icode
= direct_optab_handler (atomic_compare_and_swap_optab
, mode
);
7005 if (icode
!= CODE_FOR_nothing
)
7008 /* Check for __sync_compare_and_swap. */
7009 icode
= optab_handler (sync_compare_and_swap_optab
, mode
);
7010 if (icode
!= CODE_FOR_nothing
)
7012 if (allow_libcall
&& optab_libfunc (sync_compare_and_swap_optab
, mode
))
7015 /* No inline compare and swap. */
7019 /* Return true if an atomic exchange can be performed. */
7022 can_atomic_exchange_p (enum machine_mode mode
, bool allow_libcall
)
7024 enum insn_code icode
;
7026 /* Check for __atomic_exchange. */
7027 icode
= direct_optab_handler (atomic_exchange_optab
, mode
);
7028 if (icode
!= CODE_FOR_nothing
)
7031 /* Don't check __sync_test_and_set, as on some platforms that
7032 has reduced functionality. Targets that really do support
7033 a proper exchange should simply be updated to the __atomics. */
7035 return can_compare_and_swap_p (mode
, allow_libcall
);
7039 /* Helper function to find the MODE_CC set in a sync_compare_and_swap
7043 find_cc_set (rtx x
, const_rtx pat
, void *data
)
7045 if (REG_P (x
) && GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
7046 && GET_CODE (pat
) == SET
)
7048 rtx
*p_cc_reg
= (rtx
*) data
;
7049 gcc_assert (!*p_cc_reg
);
7054 /* This is a helper function for the other atomic operations. This function
7055 emits a loop that contains SEQ that iterates until a compare-and-swap
7056 operation at the end succeeds. MEM is the memory to be modified. SEQ is
7057 a set of instructions that takes a value from OLD_REG as an input and
7058 produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be
7059 set to the current contents of MEM. After SEQ, a compare-and-swap will
7060 attempt to update MEM with NEW_REG. The function returns true when the
7061 loop was generated successfully. */
7064 expand_compare_and_swap_loop (rtx mem
, rtx old_reg
, rtx new_reg
, rtx seq
)
7066 enum machine_mode mode
= GET_MODE (mem
);
7067 rtx label
, cmp_reg
, success
, oldval
;
7069 /* The loop we want to generate looks like
7075 (success, cmp_reg) = compare-and-swap(mem, old_reg, new_reg)
7079 Note that we only do the plain load from memory once. Subsequent
7080 iterations use the value loaded by the compare-and-swap pattern. */
7082 label
= gen_label_rtx ();
7083 cmp_reg
= gen_reg_rtx (mode
);
7085 emit_move_insn (cmp_reg
, mem
);
7087 emit_move_insn (old_reg
, cmp_reg
);
7093 if (!expand_atomic_compare_and_swap (&success
, &oldval
, mem
, old_reg
,
7094 new_reg
, false, MEMMODEL_SEQ_CST
,
7098 if (oldval
!= cmp_reg
)
7099 emit_move_insn (cmp_reg
, oldval
);
7101 /* Mark this jump predicted not taken. */
7102 emit_cmp_and_jump_insns (success
, const0_rtx
, EQ
, const0_rtx
,
7103 GET_MODE (success
), 1, label
, 0);
7108 /* This function tries to emit an atomic_exchange intruction. VAL is written
7109 to *MEM using memory model MODEL. The previous contents of *MEM are returned,
7110 using TARGET if possible. */
7113 maybe_emit_atomic_exchange (rtx target
, rtx mem
, rtx val
, enum memmodel model
)
7115 enum machine_mode mode
= GET_MODE (mem
);
7116 enum insn_code icode
;
7118 /* If the target supports the exchange directly, great. */
7119 icode
= direct_optab_handler (atomic_exchange_optab
, mode
);
7120 if (icode
!= CODE_FOR_nothing
)
7122 struct expand_operand ops
[4];
7124 create_output_operand (&ops
[0], target
, mode
);
7125 create_fixed_operand (&ops
[1], mem
);
7126 create_input_operand (&ops
[2], val
, mode
);
7127 create_integer_operand (&ops
[3], model
);
7128 if (maybe_expand_insn (icode
, 4, ops
))
7129 return ops
[0].value
;
7135 /* This function tries to implement an atomic exchange operation using
7136 __sync_lock_test_and_set. VAL is written to *MEM using memory model MODEL.
7137 The previous contents of *MEM are returned, using TARGET if possible.
7138 Since this instructionn is an acquire barrier only, stronger memory
7139 models may require additional barriers to be emitted. */
7142 maybe_emit_sync_lock_test_and_set (rtx target
, rtx mem
, rtx val
,
7143 enum memmodel model
)
7145 enum machine_mode mode
= GET_MODE (mem
);
7146 enum insn_code icode
;
7147 rtx last_insn
= get_last_insn ();
7149 icode
= optab_handler (sync_lock_test_and_set_optab
, mode
);
7151 /* Legacy sync_lock_test_and_set is an acquire barrier. If the pattern
7152 exists, and the memory model is stronger than acquire, add a release
7153 barrier before the instruction. */
7155 if ((model
& MEMMODEL_MASK
) == MEMMODEL_SEQ_CST
7156 || (model
& MEMMODEL_MASK
) == MEMMODEL_RELEASE
7157 || (model
& MEMMODEL_MASK
) == MEMMODEL_ACQ_REL
)
7158 expand_mem_thread_fence (model
);
7160 if (icode
!= CODE_FOR_nothing
)
7162 struct expand_operand ops
[3];
7163 create_output_operand (&ops
[0], target
, mode
);
7164 create_fixed_operand (&ops
[1], mem
);
7165 create_input_operand (&ops
[2], val
, mode
);
7166 if (maybe_expand_insn (icode
, 3, ops
))
7167 return ops
[0].value
;
7170 /* If an external test-and-set libcall is provided, use that instead of
7171 any external compare-and-swap that we might get from the compare-and-
7172 swap-loop expansion later. */
7173 if (!can_compare_and_swap_p (mode
, false))
7175 rtx libfunc
= optab_libfunc (sync_lock_test_and_set_optab
, mode
);
7176 if (libfunc
!= NULL
)
7180 addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
7181 return emit_library_call_value (libfunc
, NULL_RTX
, LCT_NORMAL
,
7182 mode
, 2, addr
, ptr_mode
,
7187 /* If the test_and_set can't be emitted, eliminate any barrier that might
7188 have been emitted. */
7189 delete_insns_since (last_insn
);
7193 /* This function tries to implement an atomic exchange operation using a
7194 compare_and_swap loop. VAL is written to *MEM. The previous contents of
7195 *MEM are returned, using TARGET if possible. No memory model is required
7196 since a compare_and_swap loop is seq-cst. */
7199 maybe_emit_compare_and_swap_exchange_loop (rtx target
, rtx mem
, rtx val
)
7201 enum machine_mode mode
= GET_MODE (mem
);
7203 if (can_compare_and_swap_p (mode
, true))
7205 if (!target
|| !register_operand (target
, mode
))
7206 target
= gen_reg_rtx (mode
);
7207 if (expand_compare_and_swap_loop (mem
, target
, val
, NULL_RTX
))
7214 /* This function tries to implement an atomic test-and-set operation
7215 using the atomic_test_and_set instruction pattern. A boolean value
7216 is returned from the operation, using TARGET if possible. */
7218 #ifndef HAVE_atomic_test_and_set
7219 #define HAVE_atomic_test_and_set 0
7220 #define CODE_FOR_atomic_test_and_set CODE_FOR_nothing
7224 maybe_emit_atomic_test_and_set (rtx target
, rtx mem
, enum memmodel model
)
7226 enum machine_mode pat_bool_mode
;
7227 struct expand_operand ops
[3];
7229 if (!HAVE_atomic_test_and_set
)
7232 /* While we always get QImode from __atomic_test_and_set, we get
7233 other memory modes from __sync_lock_test_and_set. Note that we
7234 use no endian adjustment here. This matches the 4.6 behavior
7235 in the Sparc backend. */
7237 (insn_data
[CODE_FOR_atomic_test_and_set
].operand
[1].mode
== QImode
);
7238 if (GET_MODE (mem
) != QImode
)
7239 mem
= adjust_address_nv (mem
, QImode
, 0);
7241 pat_bool_mode
= insn_data
[CODE_FOR_atomic_test_and_set
].operand
[0].mode
;
7242 create_output_operand (&ops
[0], target
, pat_bool_mode
);
7243 create_fixed_operand (&ops
[1], mem
);
7244 create_integer_operand (&ops
[2], model
);
7246 if (maybe_expand_insn (CODE_FOR_atomic_test_and_set
, 3, ops
))
7247 return ops
[0].value
;
7251 /* This function expands the legacy _sync_lock test_and_set operation which is
7252 generally an atomic exchange. Some limited targets only allow the
7253 constant 1 to be stored. This is an ACQUIRE operation.
7255 TARGET is an optional place to stick the return value.
7256 MEM is where VAL is stored. */
7259 expand_sync_lock_test_and_set (rtx target
, rtx mem
, rtx val
)
7263 /* Try an atomic_exchange first. */
7264 ret
= maybe_emit_atomic_exchange (target
, mem
, val
, MEMMODEL_ACQUIRE
);
7268 ret
= maybe_emit_sync_lock_test_and_set (target
, mem
, val
, MEMMODEL_ACQUIRE
);
7272 ret
= maybe_emit_compare_and_swap_exchange_loop (target
, mem
, val
);
7276 /* If there are no other options, try atomic_test_and_set if the value
7277 being stored is 1. */
7278 if (val
== const1_rtx
)
7279 ret
= maybe_emit_atomic_test_and_set (target
, mem
, MEMMODEL_ACQUIRE
);
7284 /* This function expands the atomic test_and_set operation:
7285 atomically store a boolean TRUE into MEM and return the previous value.
7287 MEMMODEL is the memory model variant to use.
7288 TARGET is an optional place to stick the return value. */
7291 expand_atomic_test_and_set (rtx target
, rtx mem
, enum memmodel model
)
7293 enum machine_mode mode
= GET_MODE (mem
);
7294 rtx ret
, trueval
, subtarget
;
7296 ret
= maybe_emit_atomic_test_and_set (target
, mem
, model
);
7300 /* Be binary compatible with non-default settings of trueval, and different
7301 cpu revisions. E.g. one revision may have atomic-test-and-set, but
7302 another only has atomic-exchange. */
7303 if (targetm
.atomic_test_and_set_trueval
== 1)
7305 trueval
= const1_rtx
;
7306 subtarget
= target
? target
: gen_reg_rtx (mode
);
7310 trueval
= gen_int_mode (targetm
.atomic_test_and_set_trueval
, mode
);
7311 subtarget
= gen_reg_rtx (mode
);
7314 /* Try the atomic-exchange optab... */
7315 ret
= maybe_emit_atomic_exchange (subtarget
, mem
, trueval
, model
);
7317 /* ... then an atomic-compare-and-swap loop ... */
7319 ret
= maybe_emit_compare_and_swap_exchange_loop (subtarget
, mem
, trueval
);
7321 /* ... before trying the vaguely defined legacy lock_test_and_set. */
7323 ret
= maybe_emit_sync_lock_test_and_set (subtarget
, mem
, trueval
, model
);
7325 /* Recall that the legacy lock_test_and_set optab was allowed to do magic
7326 things with the value 1. Thus we try again without trueval. */
7327 if (!ret
&& targetm
.atomic_test_and_set_trueval
!= 1)
7328 ret
= maybe_emit_sync_lock_test_and_set (subtarget
, mem
, const1_rtx
, model
);
7330 /* Failing all else, assume a single threaded environment and simply
7331 perform the operation. */
7334 emit_move_insn (subtarget
, mem
);
7335 emit_move_insn (mem
, trueval
);
7339 /* Recall that have to return a boolean value; rectify if trueval
7340 is not exactly one. */
7341 if (targetm
.atomic_test_and_set_trueval
!= 1)
7342 ret
= emit_store_flag_force (target
, NE
, ret
, const0_rtx
, mode
, 0, 1);
7347 /* This function expands the atomic exchange operation:
7348 atomically store VAL in MEM and return the previous value in MEM.
7350 MEMMODEL is the memory model variant to use.
7351 TARGET is an optional place to stick the return value. */
7354 expand_atomic_exchange (rtx target
, rtx mem
, rtx val
, enum memmodel model
)
7358 ret
= maybe_emit_atomic_exchange (target
, mem
, val
, model
);
7360 /* Next try a compare-and-swap loop for the exchange. */
7362 ret
= maybe_emit_compare_and_swap_exchange_loop (target
, mem
, val
);
7367 /* This function expands the atomic compare exchange operation:
7369 *PTARGET_BOOL is an optional place to store the boolean success/failure.
7370 *PTARGET_OVAL is an optional place to store the old value from memory.
7371 Both target parameters may be NULL to indicate that we do not care about
7372 that return value. Both target parameters are updated on success to
7373 the actual location of the corresponding result.
7375 MEMMODEL is the memory model variant to use.
7377 The return value of the function is true for success. */
7380 expand_atomic_compare_and_swap (rtx
*ptarget_bool
, rtx
*ptarget_oval
,
7381 rtx mem
, rtx expected
, rtx desired
,
7382 bool is_weak
, enum memmodel succ_model
,
7383 enum memmodel fail_model
)
7385 enum machine_mode mode
= GET_MODE (mem
);
7386 struct expand_operand ops
[8];
7387 enum insn_code icode
;
7388 rtx target_oval
, target_bool
= NULL_RTX
;
7391 /* Load expected into a register for the compare and swap. */
7392 if (MEM_P (expected
))
7393 expected
= copy_to_reg (expected
);
7395 /* Make sure we always have some place to put the return oldval.
7396 Further, make sure that place is distinct from the input expected,
7397 just in case we need that path down below. */
7398 if (ptarget_oval
== NULL
7399 || (target_oval
= *ptarget_oval
) == NULL
7400 || reg_overlap_mentioned_p (expected
, target_oval
))
7401 target_oval
= gen_reg_rtx (mode
);
7403 icode
= direct_optab_handler (atomic_compare_and_swap_optab
, mode
);
7404 if (icode
!= CODE_FOR_nothing
)
7406 enum machine_mode bool_mode
= insn_data
[icode
].operand
[0].mode
;
7408 /* Make sure we always have a place for the bool operand. */
7409 if (ptarget_bool
== NULL
7410 || (target_bool
= *ptarget_bool
) == NULL
7411 || GET_MODE (target_bool
) != bool_mode
)
7412 target_bool
= gen_reg_rtx (bool_mode
);
7414 /* Emit the compare_and_swap. */
7415 create_output_operand (&ops
[0], target_bool
, bool_mode
);
7416 create_output_operand (&ops
[1], target_oval
, mode
);
7417 create_fixed_operand (&ops
[2], mem
);
7418 create_input_operand (&ops
[3], expected
, mode
);
7419 create_input_operand (&ops
[4], desired
, mode
);
7420 create_integer_operand (&ops
[5], is_weak
);
7421 create_integer_operand (&ops
[6], succ_model
);
7422 create_integer_operand (&ops
[7], fail_model
);
7423 if (maybe_expand_insn (icode
, 8, ops
))
7425 /* Return success/failure. */
7426 target_bool
= ops
[0].value
;
7427 target_oval
= ops
[1].value
;
7432 /* Otherwise fall back to the original __sync_val_compare_and_swap
7433 which is always seq-cst. */
7434 icode
= optab_handler (sync_compare_and_swap_optab
, mode
);
7435 if (icode
!= CODE_FOR_nothing
)
7439 create_output_operand (&ops
[0], target_oval
, mode
);
7440 create_fixed_operand (&ops
[1], mem
);
7441 create_input_operand (&ops
[2], expected
, mode
);
7442 create_input_operand (&ops
[3], desired
, mode
);
7443 if (!maybe_expand_insn (icode
, 4, ops
))
7446 target_oval
= ops
[0].value
;
7448 /* If the caller isn't interested in the boolean return value,
7449 skip the computation of it. */
7450 if (ptarget_bool
== NULL
)
7453 /* Otherwise, work out if the compare-and-swap succeeded. */
7455 if (have_insn_for (COMPARE
, CCmode
))
7456 note_stores (PATTERN (get_last_insn ()), find_cc_set
, &cc_reg
);
7459 target_bool
= emit_store_flag_force (target_bool
, EQ
, cc_reg
,
7460 const0_rtx
, VOIDmode
, 0, 1);
7463 goto success_bool_from_val
;
7466 /* Also check for library support for __sync_val_compare_and_swap. */
7467 libfunc
= optab_libfunc (sync_compare_and_swap_optab
, mode
);
7468 if (libfunc
!= NULL
)
7470 rtx addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
7471 target_oval
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_NORMAL
,
7472 mode
, 3, addr
, ptr_mode
,
7473 expected
, mode
, desired
, mode
);
7475 /* Compute the boolean return value only if requested. */
7477 goto success_bool_from_val
;
7485 success_bool_from_val
:
7486 target_bool
= emit_store_flag_force (target_bool
, EQ
, target_oval
,
7487 expected
, VOIDmode
, 1, 1);
7489 /* Make sure that the oval output winds up where the caller asked. */
7491 *ptarget_oval
= target_oval
;
7493 *ptarget_bool
= target_bool
;
7497 /* Generate asm volatile("" : : : "memory") as the memory barrier. */
7500 expand_asm_memory_barrier (void)
7504 asm_op
= gen_rtx_ASM_OPERANDS (VOIDmode
, empty_string
, empty_string
, 0,
7505 rtvec_alloc (0), rtvec_alloc (0),
7506 rtvec_alloc (0), UNKNOWN_LOCATION
);
7507 MEM_VOLATILE_P (asm_op
) = 1;
7509 clob
= gen_rtx_SCRATCH (VOIDmode
);
7510 clob
= gen_rtx_MEM (BLKmode
, clob
);
7511 clob
= gen_rtx_CLOBBER (VOIDmode
, clob
);
7513 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, asm_op
, clob
)));
7516 /* This routine will either emit the mem_thread_fence pattern or issue a
7517 sync_synchronize to generate a fence for memory model MEMMODEL. */
7519 #ifndef HAVE_mem_thread_fence
7520 # define HAVE_mem_thread_fence 0
7521 # define gen_mem_thread_fence(x) (gcc_unreachable (), NULL_RTX)
7523 #ifndef HAVE_memory_barrier
7524 # define HAVE_memory_barrier 0
7525 # define gen_memory_barrier() (gcc_unreachable (), NULL_RTX)
7529 expand_mem_thread_fence (enum memmodel model
)
7531 if (HAVE_mem_thread_fence
)
7532 emit_insn (gen_mem_thread_fence (GEN_INT (model
)));
7533 else if ((model
& MEMMODEL_MASK
) != MEMMODEL_RELAXED
)
7535 if (HAVE_memory_barrier
)
7536 emit_insn (gen_memory_barrier ());
7537 else if (synchronize_libfunc
!= NULL_RTX
)
7538 emit_library_call (synchronize_libfunc
, LCT_NORMAL
, VOIDmode
, 0);
7540 expand_asm_memory_barrier ();
7544 /* This routine will either emit the mem_signal_fence pattern or issue a
7545 sync_synchronize to generate a fence for memory model MEMMODEL. */
7547 #ifndef HAVE_mem_signal_fence
7548 # define HAVE_mem_signal_fence 0
7549 # define gen_mem_signal_fence(x) (gcc_unreachable (), NULL_RTX)
7553 expand_mem_signal_fence (enum memmodel model
)
7555 if (HAVE_mem_signal_fence
)
7556 emit_insn (gen_mem_signal_fence (GEN_INT (model
)));
7557 else if ((model
& MEMMODEL_MASK
) != MEMMODEL_RELAXED
)
7559 /* By default targets are coherent between a thread and the signal
7560 handler running on the same thread. Thus this really becomes a
7561 compiler barrier, in that stores must not be sunk past
7562 (or raised above) a given point. */
7563 expand_asm_memory_barrier ();
7567 /* This function expands the atomic load operation:
7568 return the atomically loaded value in MEM.
7570 MEMMODEL is the memory model variant to use.
7571 TARGET is an option place to stick the return value. */
7574 expand_atomic_load (rtx target
, rtx mem
, enum memmodel model
)
7576 enum machine_mode mode
= GET_MODE (mem
);
7577 enum insn_code icode
;
7579 /* If the target supports the load directly, great. */
7580 icode
= direct_optab_handler (atomic_load_optab
, mode
);
7581 if (icode
!= CODE_FOR_nothing
)
7583 struct expand_operand ops
[3];
7585 create_output_operand (&ops
[0], target
, mode
);
7586 create_fixed_operand (&ops
[1], mem
);
7587 create_integer_operand (&ops
[2], model
);
7588 if (maybe_expand_insn (icode
, 3, ops
))
7589 return ops
[0].value
;
7592 /* If the size of the object is greater than word size on this target,
7593 then we assume that a load will not be atomic. */
7594 if (GET_MODE_PRECISION (mode
) > BITS_PER_WORD
)
7596 /* Issue val = compare_and_swap (mem, 0, 0).
7597 This may cause the occasional harmless store of 0 when the value is
7598 already 0, but it seems to be OK according to the standards guys. */
7599 if (expand_atomic_compare_and_swap (NULL
, &target
, mem
, const0_rtx
,
7600 const0_rtx
, false, model
, model
))
7603 /* Otherwise there is no atomic load, leave the library call. */
7607 /* Otherwise assume loads are atomic, and emit the proper barriers. */
7608 if (!target
|| target
== const0_rtx
)
7609 target
= gen_reg_rtx (mode
);
7611 /* For SEQ_CST, emit a barrier before the load. */
7612 if ((model
& MEMMODEL_MASK
) == MEMMODEL_SEQ_CST
)
7613 expand_mem_thread_fence (model
);
7615 emit_move_insn (target
, mem
);
7617 /* Emit the appropriate barrier after the load. */
7618 expand_mem_thread_fence (model
);
7623 /* This function expands the atomic store operation:
7624 Atomically store VAL in MEM.
7625 MEMMODEL is the memory model variant to use.
7626 USE_RELEASE is true if __sync_lock_release can be used as a fall back.
7627 function returns const0_rtx if a pattern was emitted. */
7630 expand_atomic_store (rtx mem
, rtx val
, enum memmodel model
, bool use_release
)
7632 enum machine_mode mode
= GET_MODE (mem
);
7633 enum insn_code icode
;
7634 struct expand_operand ops
[3];
7636 /* If the target supports the store directly, great. */
7637 icode
= direct_optab_handler (atomic_store_optab
, mode
);
7638 if (icode
!= CODE_FOR_nothing
)
7640 create_fixed_operand (&ops
[0], mem
);
7641 create_input_operand (&ops
[1], val
, mode
);
7642 create_integer_operand (&ops
[2], model
);
7643 if (maybe_expand_insn (icode
, 3, ops
))
7647 /* If using __sync_lock_release is a viable alternative, try it. */
7650 icode
= direct_optab_handler (sync_lock_release_optab
, mode
);
7651 if (icode
!= CODE_FOR_nothing
)
7653 create_fixed_operand (&ops
[0], mem
);
7654 create_input_operand (&ops
[1], const0_rtx
, mode
);
7655 if (maybe_expand_insn (icode
, 2, ops
))
7657 /* lock_release is only a release barrier. */
7658 if ((model
& MEMMODEL_MASK
) == MEMMODEL_SEQ_CST
)
7659 expand_mem_thread_fence (model
);
7665 /* If the size of the object is greater than word size on this target,
7666 a default store will not be atomic, Try a mem_exchange and throw away
7667 the result. If that doesn't work, don't do anything. */
7668 if (GET_MODE_PRECISION (mode
) > BITS_PER_WORD
)
7670 rtx target
= maybe_emit_atomic_exchange (NULL_RTX
, mem
, val
, model
);
7672 target
= maybe_emit_compare_and_swap_exchange_loop (NULL_RTX
, mem
, val
);
7679 /* Otherwise assume stores are atomic, and emit the proper barriers. */
7680 expand_mem_thread_fence (model
);
7682 emit_move_insn (mem
, val
);
7684 /* For SEQ_CST, also emit a barrier after the store. */
7685 if ((model
& MEMMODEL_MASK
) == MEMMODEL_SEQ_CST
)
7686 expand_mem_thread_fence (model
);
7692 /* Structure containing the pointers and values required to process the
7693 various forms of the atomic_fetch_op and atomic_op_fetch builtins. */
7695 struct atomic_op_functions
7697 direct_optab mem_fetch_before
;
7698 direct_optab mem_fetch_after
;
7699 direct_optab mem_no_result
;
7702 direct_optab no_result
;
7703 enum rtx_code reverse_code
;
7707 /* Fill in structure pointed to by OP with the various optab entries for an
7708 operation of type CODE. */
7711 get_atomic_op_for_code (struct atomic_op_functions
*op
, enum rtx_code code
)
7713 gcc_assert (op
!= NULL
);
7715 /* If SWITCHABLE_TARGET is defined, then subtargets can be switched
7716 in the source code during compilation, and the optab entries are not
7717 computable until runtime. Fill in the values at runtime. */
7721 op
->mem_fetch_before
= atomic_fetch_add_optab
;
7722 op
->mem_fetch_after
= atomic_add_fetch_optab
;
7723 op
->mem_no_result
= atomic_add_optab
;
7724 op
->fetch_before
= sync_old_add_optab
;
7725 op
->fetch_after
= sync_new_add_optab
;
7726 op
->no_result
= sync_add_optab
;
7727 op
->reverse_code
= MINUS
;
7730 op
->mem_fetch_before
= atomic_fetch_sub_optab
;
7731 op
->mem_fetch_after
= atomic_sub_fetch_optab
;
7732 op
->mem_no_result
= atomic_sub_optab
;
7733 op
->fetch_before
= sync_old_sub_optab
;
7734 op
->fetch_after
= sync_new_sub_optab
;
7735 op
->no_result
= sync_sub_optab
;
7736 op
->reverse_code
= PLUS
;
7739 op
->mem_fetch_before
= atomic_fetch_xor_optab
;
7740 op
->mem_fetch_after
= atomic_xor_fetch_optab
;
7741 op
->mem_no_result
= atomic_xor_optab
;
7742 op
->fetch_before
= sync_old_xor_optab
;
7743 op
->fetch_after
= sync_new_xor_optab
;
7744 op
->no_result
= sync_xor_optab
;
7745 op
->reverse_code
= XOR
;
7748 op
->mem_fetch_before
= atomic_fetch_and_optab
;
7749 op
->mem_fetch_after
= atomic_and_fetch_optab
;
7750 op
->mem_no_result
= atomic_and_optab
;
7751 op
->fetch_before
= sync_old_and_optab
;
7752 op
->fetch_after
= sync_new_and_optab
;
7753 op
->no_result
= sync_and_optab
;
7754 op
->reverse_code
= UNKNOWN
;
7757 op
->mem_fetch_before
= atomic_fetch_or_optab
;
7758 op
->mem_fetch_after
= atomic_or_fetch_optab
;
7759 op
->mem_no_result
= atomic_or_optab
;
7760 op
->fetch_before
= sync_old_ior_optab
;
7761 op
->fetch_after
= sync_new_ior_optab
;
7762 op
->no_result
= sync_ior_optab
;
7763 op
->reverse_code
= UNKNOWN
;
7766 op
->mem_fetch_before
= atomic_fetch_nand_optab
;
7767 op
->mem_fetch_after
= atomic_nand_fetch_optab
;
7768 op
->mem_no_result
= atomic_nand_optab
;
7769 op
->fetch_before
= sync_old_nand_optab
;
7770 op
->fetch_after
= sync_new_nand_optab
;
7771 op
->no_result
= sync_nand_optab
;
7772 op
->reverse_code
= UNKNOWN
;
7779 /* See if there is a more optimal way to implement the operation "*MEM CODE VAL"
7780 using memory order MODEL. If AFTER is true the operation needs to return
7781 the value of *MEM after the operation, otherwise the previous value.
7782 TARGET is an optional place to place the result. The result is unused if
7784 Return the result if there is a better sequence, otherwise NULL_RTX. */
7787 maybe_optimize_fetch_op (rtx target
, rtx mem
, rtx val
, enum rtx_code code
,
7788 enum memmodel model
, bool after
)
7790 /* If the value is prefetched, or not used, it may be possible to replace
7791 the sequence with a native exchange operation. */
7792 if (!after
|| target
== const0_rtx
)
7794 /* fetch_and (&x, 0, m) can be replaced with exchange (&x, 0, m). */
7795 if (code
== AND
&& val
== const0_rtx
)
7797 if (target
== const0_rtx
)
7798 target
= gen_reg_rtx (GET_MODE (mem
));
7799 return maybe_emit_atomic_exchange (target
, mem
, val
, model
);
7802 /* fetch_or (&x, -1, m) can be replaced with exchange (&x, -1, m). */
7803 if (code
== IOR
&& val
== constm1_rtx
)
7805 if (target
== const0_rtx
)
7806 target
= gen_reg_rtx (GET_MODE (mem
));
7807 return maybe_emit_atomic_exchange (target
, mem
, val
, model
);
7814 /* Try to emit an instruction for a specific operation varaition.
7815 OPTAB contains the OP functions.
7816 TARGET is an optional place to return the result. const0_rtx means unused.
7817 MEM is the memory location to operate on.
7818 VAL is the value to use in the operation.
7819 USE_MEMMODEL is TRUE if the variation with a memory model should be tried.
7820 MODEL is the memory model, if used.
7821 AFTER is true if the returned result is the value after the operation. */
7824 maybe_emit_op (const struct atomic_op_functions
*optab
, rtx target
, rtx mem
,
7825 rtx val
, bool use_memmodel
, enum memmodel model
, bool after
)
7827 enum machine_mode mode
= GET_MODE (mem
);
7828 struct expand_operand ops
[4];
7829 enum insn_code icode
;
7833 /* Check to see if there is a result returned. */
7834 if (target
== const0_rtx
)
7838 icode
= direct_optab_handler (optab
->mem_no_result
, mode
);
7839 create_integer_operand (&ops
[2], model
);
7844 icode
= direct_optab_handler (optab
->no_result
, mode
);
7848 /* Otherwise, we need to generate a result. */
7853 icode
= direct_optab_handler (after
? optab
->mem_fetch_after
7854 : optab
->mem_fetch_before
, mode
);
7855 create_integer_operand (&ops
[3], model
);
7860 icode
= optab_handler (after
? optab
->fetch_after
7861 : optab
->fetch_before
, mode
);
7864 create_output_operand (&ops
[op_counter
++], target
, mode
);
7866 if (icode
== CODE_FOR_nothing
)
7869 create_fixed_operand (&ops
[op_counter
++], mem
);
7870 /* VAL may have been promoted to a wider mode. Shrink it if so. */
7871 create_convert_operand_to (&ops
[op_counter
++], val
, mode
, true);
7873 if (maybe_expand_insn (icode
, num_ops
, ops
))
7874 return (target
== const0_rtx
? const0_rtx
: ops
[0].value
);
7880 /* This function expands an atomic fetch_OP or OP_fetch operation:
7881 TARGET is an option place to stick the return value. const0_rtx indicates
7882 the result is unused.
7883 atomically fetch MEM, perform the operation with VAL and return it to MEM.
7884 CODE is the operation being performed (OP)
7885 MEMMODEL is the memory model variant to use.
7886 AFTER is true to return the result of the operation (OP_fetch).
7887 AFTER is false to return the value before the operation (fetch_OP).
7889 This function will *only* generate instructions if there is a direct
7890 optab. No compare and swap loops or libcalls will be generated. */
7893 expand_atomic_fetch_op_no_fallback (rtx target
, rtx mem
, rtx val
,
7894 enum rtx_code code
, enum memmodel model
,
7897 enum machine_mode mode
= GET_MODE (mem
);
7898 struct atomic_op_functions optab
;
7900 bool unused_result
= (target
== const0_rtx
);
7902 get_atomic_op_for_code (&optab
, code
);
7904 /* Check to see if there are any better instructions. */
7905 result
= maybe_optimize_fetch_op (target
, mem
, val
, code
, model
, after
);
7909 /* Check for the case where the result isn't used and try those patterns. */
7912 /* Try the memory model variant first. */
7913 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, true);
7917 /* Next try the old style withuot a memory model. */
7918 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, true);
7922 /* There is no no-result pattern, so try patterns with a result. */
7926 /* Try the __atomic version. */
7927 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, after
);
7931 /* Try the older __sync version. */
7932 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, after
);
7936 /* If the fetch value can be calculated from the other variation of fetch,
7937 try that operation. */
7938 if (after
|| unused_result
|| optab
.reverse_code
!= UNKNOWN
)
7940 /* Try the __atomic version, then the older __sync version. */
7941 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, !after
);
7943 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, !after
);
7947 /* If the result isn't used, no need to do compensation code. */
7951 /* Issue compensation code. Fetch_after == fetch_before OP val.
7952 Fetch_before == after REVERSE_OP val. */
7954 code
= optab
.reverse_code
;
7957 result
= expand_simple_binop (mode
, AND
, result
, val
, NULL_RTX
,
7958 true, OPTAB_LIB_WIDEN
);
7959 result
= expand_simple_unop (mode
, NOT
, result
, target
, true);
7962 result
= expand_simple_binop (mode
, code
, result
, val
, target
,
7963 true, OPTAB_LIB_WIDEN
);
7968 /* No direct opcode can be generated. */
7974 /* This function expands an atomic fetch_OP or OP_fetch operation:
7975 TARGET is an option place to stick the return value. const0_rtx indicates
7976 the result is unused.
7977 atomically fetch MEM, perform the operation with VAL and return it to MEM.
7978 CODE is the operation being performed (OP)
7979 MEMMODEL is the memory model variant to use.
7980 AFTER is true to return the result of the operation (OP_fetch).
7981 AFTER is false to return the value before the operation (fetch_OP). */
7983 expand_atomic_fetch_op (rtx target
, rtx mem
, rtx val
, enum rtx_code code
,
7984 enum memmodel model
, bool after
)
7986 enum machine_mode mode
= GET_MODE (mem
);
7988 bool unused_result
= (target
== const0_rtx
);
7990 result
= expand_atomic_fetch_op_no_fallback (target
, mem
, val
, code
, model
,
7996 /* Add/sub can be implemented by doing the reverse operation with -(val). */
7997 if (code
== PLUS
|| code
== MINUS
)
8000 enum rtx_code reverse
= (code
== PLUS
? MINUS
: PLUS
);
8003 tmp
= expand_simple_unop (mode
, NEG
, val
, NULL_RTX
, true);
8004 result
= expand_atomic_fetch_op_no_fallback (target
, mem
, tmp
, reverse
,
8008 /* PLUS worked so emit the insns and return. */
8015 /* PLUS did not work, so throw away the negation code and continue. */
8019 /* Try the __sync libcalls only if we can't do compare-and-swap inline. */
8020 if (!can_compare_and_swap_p (mode
, false))
8024 enum rtx_code orig_code
= code
;
8025 struct atomic_op_functions optab
;
8027 get_atomic_op_for_code (&optab
, code
);
8028 libfunc
= optab_libfunc (after
? optab
.fetch_after
8029 : optab
.fetch_before
, mode
);
8031 && (after
|| unused_result
|| optab
.reverse_code
!= UNKNOWN
))
8035 code
= optab
.reverse_code
;
8036 libfunc
= optab_libfunc (after
? optab
.fetch_before
8037 : optab
.fetch_after
, mode
);
8039 if (libfunc
!= NULL
)
8041 rtx addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
8042 result
= emit_library_call_value (libfunc
, NULL
, LCT_NORMAL
, mode
,
8043 2, addr
, ptr_mode
, val
, mode
);
8045 if (!unused_result
&& fixup
)
8046 result
= expand_simple_binop (mode
, code
, result
, val
, target
,
8047 true, OPTAB_LIB_WIDEN
);
8051 /* We need the original code for any further attempts. */
8055 /* If nothing else has succeeded, default to a compare and swap loop. */
8056 if (can_compare_and_swap_p (mode
, true))
8059 rtx t0
= gen_reg_rtx (mode
), t1
;
8063 /* If the result is used, get a register for it. */
8066 if (!target
|| !register_operand (target
, mode
))
8067 target
= gen_reg_rtx (mode
);
8068 /* If fetch_before, copy the value now. */
8070 emit_move_insn (target
, t0
);
8073 target
= const0_rtx
;
8078 t1
= expand_simple_binop (mode
, AND
, t1
, val
, NULL_RTX
,
8079 true, OPTAB_LIB_WIDEN
);
8080 t1
= expand_simple_unop (mode
, code
, t1
, NULL_RTX
, true);
8083 t1
= expand_simple_binop (mode
, code
, t1
, val
, NULL_RTX
, true,
8086 /* For after, copy the value now. */
8087 if (!unused_result
&& after
)
8088 emit_move_insn (target
, t1
);
8089 insn
= get_insns ();
8092 if (t1
!= NULL
&& expand_compare_and_swap_loop (mem
, t0
, t1
, insn
))
8099 /* Return true if OPERAND is suitable for operand number OPNO of
8100 instruction ICODE. */
8103 insn_operand_matches (enum insn_code icode
, unsigned int opno
, rtx operand
)
8105 return (!insn_data
[(int) icode
].operand
[opno
].predicate
8106 || (insn_data
[(int) icode
].operand
[opno
].predicate
8107 (operand
, insn_data
[(int) icode
].operand
[opno
].mode
)));
8110 /* TARGET is a target of a multiword operation that we are going to
8111 implement as a series of word-mode operations. Return true if
8112 TARGET is suitable for this purpose. */
8115 valid_multiword_target_p (rtx target
)
8117 enum machine_mode mode
;
8120 mode
= GET_MODE (target
);
8121 for (i
= 0; i
< GET_MODE_SIZE (mode
); i
+= UNITS_PER_WORD
)
8122 if (!validate_subreg (word_mode
, mode
, target
, i
))
8127 /* Like maybe_legitimize_operand, but do not change the code of the
8128 current rtx value. */
8131 maybe_legitimize_operand_same_code (enum insn_code icode
, unsigned int opno
,
8132 struct expand_operand
*op
)
8134 /* See if the operand matches in its current form. */
8135 if (insn_operand_matches (icode
, opno
, op
->value
))
8138 /* If the operand is a memory whose address has no side effects,
8139 try forcing the address into a non-virtual pseudo register.
8140 The check for side effects is important because copy_to_mode_reg
8141 cannot handle things like auto-modified addresses. */
8142 if (insn_data
[(int) icode
].operand
[opno
].allows_mem
&& MEM_P (op
->value
))
8147 addr
= XEXP (mem
, 0);
8148 if (!(REG_P (addr
) && REGNO (addr
) > LAST_VIRTUAL_REGISTER
)
8149 && !side_effects_p (addr
))
8152 enum machine_mode mode
;
8154 last
= get_last_insn ();
8155 mode
= get_address_mode (mem
);
8156 mem
= replace_equiv_address (mem
, copy_to_mode_reg (mode
, addr
));
8157 if (insn_operand_matches (icode
, opno
, mem
))
8162 delete_insns_since (last
);
8169 /* Try to make OP match operand OPNO of instruction ICODE. Return true
8170 on success, storing the new operand value back in OP. */
8173 maybe_legitimize_operand (enum insn_code icode
, unsigned int opno
,
8174 struct expand_operand
*op
)
8176 enum machine_mode mode
, imode
;
8177 bool old_volatile_ok
, result
;
8183 old_volatile_ok
= volatile_ok
;
8185 result
= maybe_legitimize_operand_same_code (icode
, opno
, op
);
8186 volatile_ok
= old_volatile_ok
;
8190 gcc_assert (mode
!= VOIDmode
);
8192 && op
->value
!= const0_rtx
8193 && GET_MODE (op
->value
) == mode
8194 && maybe_legitimize_operand_same_code (icode
, opno
, op
))
8197 op
->value
= gen_reg_rtx (mode
);
8202 gcc_assert (mode
!= VOIDmode
);
8203 gcc_assert (GET_MODE (op
->value
) == VOIDmode
8204 || GET_MODE (op
->value
) == mode
);
8205 if (maybe_legitimize_operand_same_code (icode
, opno
, op
))
8208 op
->value
= copy_to_mode_reg (mode
, op
->value
);
8211 case EXPAND_CONVERT_TO
:
8212 gcc_assert (mode
!= VOIDmode
);
8213 op
->value
= convert_to_mode (mode
, op
->value
, op
->unsigned_p
);
8216 case EXPAND_CONVERT_FROM
:
8217 if (GET_MODE (op
->value
) != VOIDmode
)
8218 mode
= GET_MODE (op
->value
);
8220 /* The caller must tell us what mode this value has. */
8221 gcc_assert (mode
!= VOIDmode
);
8223 imode
= insn_data
[(int) icode
].operand
[opno
].mode
;
8224 if (imode
!= VOIDmode
&& imode
!= mode
)
8226 op
->value
= convert_modes (imode
, mode
, op
->value
, op
->unsigned_p
);
8231 case EXPAND_ADDRESS
:
8232 gcc_assert (mode
!= VOIDmode
);
8233 op
->value
= convert_memory_address (mode
, op
->value
);
8236 case EXPAND_INTEGER
:
8237 mode
= insn_data
[(int) icode
].operand
[opno
].mode
;
8238 if (mode
!= VOIDmode
&& const_int_operand (op
->value
, mode
))
8242 return insn_operand_matches (icode
, opno
, op
->value
);
8245 /* Make OP describe an input operand that should have the same value
8246 as VALUE, after any mode conversion that the target might request.
8247 TYPE is the type of VALUE. */
8250 create_convert_operand_from_type (struct expand_operand
*op
,
8251 rtx value
, tree type
)
8253 create_convert_operand_from (op
, value
, TYPE_MODE (type
),
8254 TYPE_UNSIGNED (type
));
8257 /* Try to make operands [OPS, OPS + NOPS) match operands [OPNO, OPNO + NOPS)
8258 of instruction ICODE. Return true on success, leaving the new operand
8259 values in the OPS themselves. Emit no code on failure. */
8262 maybe_legitimize_operands (enum insn_code icode
, unsigned int opno
,
8263 unsigned int nops
, struct expand_operand
*ops
)
8268 last
= get_last_insn ();
8269 for (i
= 0; i
< nops
; i
++)
8270 if (!maybe_legitimize_operand (icode
, opno
+ i
, &ops
[i
]))
8272 delete_insns_since (last
);
8278 /* Try to generate instruction ICODE, using operands [OPS, OPS + NOPS)
8279 as its operands. Return the instruction pattern on success,
8280 and emit any necessary set-up code. Return null and emit no
8284 maybe_gen_insn (enum insn_code icode
, unsigned int nops
,
8285 struct expand_operand
*ops
)
8287 gcc_assert (nops
== (unsigned int) insn_data
[(int) icode
].n_generator_args
);
8288 if (!maybe_legitimize_operands (icode
, 0, nops
, ops
))
8294 return GEN_FCN (icode
) (ops
[0].value
);
8296 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
);
8298 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
);
8300 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8303 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8304 ops
[3].value
, ops
[4].value
);
8306 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8307 ops
[3].value
, ops
[4].value
, ops
[5].value
);
8309 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8310 ops
[3].value
, ops
[4].value
, ops
[5].value
,
8313 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8314 ops
[3].value
, ops
[4].value
, ops
[5].value
,
8315 ops
[6].value
, ops
[7].value
);
8317 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8318 ops
[3].value
, ops
[4].value
, ops
[5].value
,
8319 ops
[6].value
, ops
[7].value
, ops
[8].value
);
8324 /* Try to emit instruction ICODE, using operands [OPS, OPS + NOPS)
8325 as its operands. Return true on success and emit no code on failure. */
8328 maybe_expand_insn (enum insn_code icode
, unsigned int nops
,
8329 struct expand_operand
*ops
)
8331 rtx pat
= maybe_gen_insn (icode
, nops
, ops
);
8340 /* Like maybe_expand_insn, but for jumps. */
8343 maybe_expand_jump_insn (enum insn_code icode
, unsigned int nops
,
8344 struct expand_operand
*ops
)
8346 rtx pat
= maybe_gen_insn (icode
, nops
, ops
);
8349 emit_jump_insn (pat
);
8355 /* Emit instruction ICODE, using operands [OPS, OPS + NOPS)
8359 expand_insn (enum insn_code icode
, unsigned int nops
,
8360 struct expand_operand
*ops
)
8362 if (!maybe_expand_insn (icode
, nops
, ops
))
8366 /* Like expand_insn, but for jumps. */
8369 expand_jump_insn (enum insn_code icode
, unsigned int nops
,
8370 struct expand_operand
*ops
)
8372 if (!maybe_expand_jump_insn (icode
, nops
, ops
))
8376 /* Reduce conditional compilation elsewhere. */
8379 #define CODE_FOR_insv CODE_FOR_nothing
8383 #define CODE_FOR_extv CODE_FOR_nothing
8386 #define HAVE_extzv 0
8387 #define CODE_FOR_extzv CODE_FOR_nothing
8390 /* Enumerates the possible types of structure operand to an
8392 enum extraction_type
{ ET_unaligned_mem
, ET_reg
};
8394 /* Check whether insv, extv or extzv pattern ICODE can be used for an
8395 insertion or extraction of type TYPE on a structure of mode MODE.
8396 Return true if so and fill in *INSN accordingly. STRUCT_OP is the
8397 operand number of the structure (the first sign_extract or zero_extract
8398 operand) and FIELD_OP is the operand number of the field (the other
8399 side of the set from the sign_extract or zero_extract). */
8402 get_traditional_extraction_insn (extraction_insn
*insn
,
8403 enum extraction_type type
,
8404 enum machine_mode mode
,
8405 enum insn_code icode
,
8406 int struct_op
, int field_op
)
8408 const struct insn_data_d
*data
= &insn_data
[icode
];
8410 enum machine_mode struct_mode
= data
->operand
[struct_op
].mode
;
8411 if (struct_mode
== VOIDmode
)
8412 struct_mode
= word_mode
;
8413 if (mode
!= struct_mode
)
8416 enum machine_mode field_mode
= data
->operand
[field_op
].mode
;
8417 if (field_mode
== VOIDmode
)
8418 field_mode
= word_mode
;
8420 enum machine_mode pos_mode
= data
->operand
[struct_op
+ 2].mode
;
8421 if (pos_mode
== VOIDmode
)
8422 pos_mode
= word_mode
;
8424 insn
->icode
= icode
;
8425 insn
->field_mode
= field_mode
;
8426 insn
->struct_mode
= (type
== ET_unaligned_mem
? byte_mode
: struct_mode
);
8427 insn
->pos_mode
= pos_mode
;
8431 /* Return true if an optab exists to perform an insertion or extraction
8432 of type TYPE in mode MODE. Describe the instruction in *INSN if so.
8434 REG_OPTAB is the optab to use for register structures and
8435 MISALIGN_OPTAB is the optab to use for misaligned memory structures.
8436 POS_OP is the operand number of the bit position. */
8439 get_optab_extraction_insn (struct extraction_insn
*insn
,
8440 enum extraction_type type
,
8441 enum machine_mode mode
, direct_optab reg_optab
,
8442 direct_optab misalign_optab
, int pos_op
)
8444 direct_optab optab
= (type
== ET_unaligned_mem
? misalign_optab
: reg_optab
);
8445 enum insn_code icode
= direct_optab_handler (optab
, mode
);
8446 if (icode
== CODE_FOR_nothing
)
8449 const struct insn_data_d
*data
= &insn_data
[icode
];
8451 insn
->icode
= icode
;
8452 insn
->field_mode
= mode
;
8453 insn
->struct_mode
= (type
== ET_unaligned_mem
? BLKmode
: mode
);
8454 insn
->pos_mode
= data
->operand
[pos_op
].mode
;
8455 if (insn
->pos_mode
== VOIDmode
)
8456 insn
->pos_mode
= word_mode
;
8460 /* Return true if an instruction exists to perform an insertion or
8461 extraction (PATTERN says which) of type TYPE in mode MODE.
8462 Describe the instruction in *INSN if so. */
8465 get_extraction_insn (extraction_insn
*insn
,
8466 enum extraction_pattern pattern
,
8467 enum extraction_type type
,
8468 enum machine_mode mode
)
8474 && get_traditional_extraction_insn (insn
, type
, mode
,
8475 CODE_FOR_insv
, 0, 3))
8477 return get_optab_extraction_insn (insn
, type
, mode
, insv_optab
,
8478 insvmisalign_optab
, 2);
8482 && get_traditional_extraction_insn (insn
, type
, mode
,
8483 CODE_FOR_extv
, 1, 0))
8485 return get_optab_extraction_insn (insn
, type
, mode
, extv_optab
,
8486 extvmisalign_optab
, 3);
8490 && get_traditional_extraction_insn (insn
, type
, mode
,
8491 CODE_FOR_extzv
, 1, 0))
8493 return get_optab_extraction_insn (insn
, type
, mode
, extzv_optab
,
8494 extzvmisalign_optab
, 3);
8501 /* Return true if an instruction exists to access a field of mode
8502 FIELDMODE in a structure that has STRUCT_BITS significant bits.
8503 Describe the "best" such instruction in *INSN if so. PATTERN and
8504 TYPE describe the type of insertion or extraction we want to perform.
8506 For an insertion, the number of significant structure bits includes
8507 all bits of the target. For an extraction, it need only include the
8508 most significant bit of the field. Larger widths are acceptable
8512 get_best_extraction_insn (extraction_insn
*insn
,
8513 enum extraction_pattern pattern
,
8514 enum extraction_type type
,
8515 unsigned HOST_WIDE_INT struct_bits
,
8516 enum machine_mode field_mode
)
8518 enum machine_mode mode
= smallest_mode_for_size (struct_bits
, MODE_INT
);
8519 while (mode
!= VOIDmode
)
8521 if (get_extraction_insn (insn
, pattern
, type
, mode
))
8523 while (mode
!= VOIDmode
8524 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (field_mode
)
8525 && !TRULY_NOOP_TRUNCATION_MODES_P (insn
->field_mode
,
8528 get_extraction_insn (insn
, pattern
, type
, mode
);
8529 mode
= GET_MODE_WIDER_MODE (mode
);
8533 mode
= GET_MODE_WIDER_MODE (mode
);
8538 /* Return true if an instruction exists to access a field of mode
8539 FIELDMODE in a register structure that has STRUCT_BITS significant bits.
8540 Describe the "best" such instruction in *INSN if so. PATTERN describes
8541 the type of insertion or extraction we want to perform.
8543 For an insertion, the number of significant structure bits includes
8544 all bits of the target. For an extraction, it need only include the
8545 most significant bit of the field. Larger widths are acceptable
8549 get_best_reg_extraction_insn (extraction_insn
*insn
,
8550 enum extraction_pattern pattern
,
8551 unsigned HOST_WIDE_INT struct_bits
,
8552 enum machine_mode field_mode
)
8554 return get_best_extraction_insn (insn
, pattern
, ET_reg
, struct_bits
,
8558 /* Return true if an instruction exists to access a field of BITSIZE
8559 bits starting BITNUM bits into a memory structure. Describe the
8560 "best" such instruction in *INSN if so. PATTERN describes the type
8561 of insertion or extraction we want to perform and FIELDMODE is the
8562 natural mode of the extracted field.
8564 The instructions considered here only access bytes that overlap
8565 the bitfield; they do not touch any surrounding bytes. */
8568 get_best_mem_extraction_insn (extraction_insn
*insn
,
8569 enum extraction_pattern pattern
,
8570 HOST_WIDE_INT bitsize
, HOST_WIDE_INT bitnum
,
8571 enum machine_mode field_mode
)
8573 unsigned HOST_WIDE_INT struct_bits
= (bitnum
% BITS_PER_UNIT
8575 + BITS_PER_UNIT
- 1);
8576 struct_bits
-= struct_bits
% BITS_PER_UNIT
;
8577 return get_best_extraction_insn (insn
, pattern
, ET_unaligned_mem
,
8578 struct_bits
, field_mode
);
8581 #include "gt-optabs.h"