1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "rtl-error.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
50 /* This file contains the reload pass of the compiler, which is
51 run after register allocation has been done. It checks that
52 each insn is valid (operands required to be in registers really
53 are in registers of the proper class) and fixes up invalid ones
54 by copying values temporarily into registers for the insns
57 The results of register allocation are described by the vector
58 reg_renumber; the insns still contain pseudo regs, but reg_renumber
59 can be used to find which hard reg, if any, a pseudo reg is in.
61 The technique we always use is to free up a few hard regs that are
62 called ``reload regs'', and for each place where a pseudo reg
63 must be in a hard reg, copy it temporarily into one of the reload regs.
65 Reload regs are allocated locally for every instruction that needs
66 reloads. When there are pseudos which are allocated to a register that
67 has been chosen as a reload reg, such pseudos must be ``spilled''.
68 This means that they go to other hard regs, or to stack slots if no other
69 available hard regs can be found. Spilling can invalidate more
70 insns, requiring additional need for reloads, so we must keep checking
71 until the process stabilizes.
73 For machines with different classes of registers, we must keep track
74 of the register class needed for each reload, and make sure that
75 we allocate enough reload registers of each class.
77 The file reload.c contains the code that checks one insn for
78 validity and reports the reloads that it needs. This file
79 is in charge of scanning the entire rtl code, accumulating the
80 reload needs, spilling, assigning reload registers to use for
81 fixing up each insn, and generating the new insns to copy values
82 into the reload registers. */
84 struct target_reload default_target_reload
;
86 struct target_reload
*this_target_reload
= &default_target_reload
;
89 #define spill_indirect_levels \
90 (this_target_reload->x_spill_indirect_levels)
92 /* During reload_as_needed, element N contains a REG rtx for the hard reg
93 into which reg N has been reloaded (perhaps for a previous insn). */
94 static rtx
*reg_last_reload_reg
;
96 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
97 for an output reload that stores into reg N. */
98 static regset_head reg_has_output_reload
;
100 /* Indicates which hard regs are reload-registers for an output reload
101 in the current insn. */
102 static HARD_REG_SET reg_is_output_reload
;
104 /* Element N is the constant value to which pseudo reg N is equivalent,
105 or zero if pseudo reg N is not equivalent to a constant.
106 find_reloads looks at this in order to replace pseudo reg N
107 with the constant it stands for. */
108 rtx
*reg_equiv_constant
;
110 /* Element N is an invariant value to which pseudo reg N is equivalent.
111 eliminate_regs_in_insn uses this to replace pseudos in particular
113 rtx
*reg_equiv_invariant
;
115 /* Element N is a memory location to which pseudo reg N is equivalent,
116 prior to any register elimination (such as frame pointer to stack
117 pointer). Depending on whether or not it is a valid address, this value
118 is transferred to either reg_equiv_address or reg_equiv_mem. */
119 rtx
*reg_equiv_memory_loc
;
121 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
122 collector can keep track of what is inside. */
123 VEC(rtx
,gc
) *reg_equiv_memory_loc_vec
;
125 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
126 This is used when the address is not valid as a memory address
127 (because its displacement is too big for the machine.) */
128 rtx
*reg_equiv_address
;
130 /* Element N is the memory slot to which pseudo reg N is equivalent,
131 or zero if pseudo reg N is not equivalent to a memory slot. */
134 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
135 alternate representations of the location of pseudo reg N. */
136 rtx
*reg_equiv_alt_mem_list
;
138 /* Widest width in which each pseudo reg is referred to (via subreg). */
139 static unsigned int *reg_max_ref_width
;
141 /* Element N is the list of insns that initialized reg N from its equivalent
142 constant or memory slot. */
144 int reg_equiv_init_size
;
146 /* Vector to remember old contents of reg_renumber before spilling. */
147 static short *reg_old_renumber
;
149 /* During reload_as_needed, element N contains the last pseudo regno reloaded
150 into hard register N. If that pseudo reg occupied more than one register,
151 reg_reloaded_contents points to that pseudo for each spill register in
152 use; all of these must remain set for an inheritance to occur. */
153 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
155 /* During reload_as_needed, element N contains the insn for which
156 hard register N was last used. Its contents are significant only
157 when reg_reloaded_valid is set for this register. */
158 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
160 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
161 static HARD_REG_SET reg_reloaded_valid
;
162 /* Indicate if the register was dead at the end of the reload.
163 This is only valid if reg_reloaded_contents is set and valid. */
164 static HARD_REG_SET reg_reloaded_dead
;
166 /* Indicate whether the register's current value is one that is not
167 safe to retain across a call, even for registers that are normally
168 call-saved. This is only meaningful for members of reg_reloaded_valid. */
169 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
171 /* Number of spill-regs so far; number of valid elements of spill_regs. */
174 /* In parallel with spill_regs, contains REG rtx's for those regs.
175 Holds the last rtx used for any given reg, or 0 if it has never
176 been used for spilling yet. This rtx is reused, provided it has
178 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
180 /* In parallel with spill_regs, contains nonzero for a spill reg
181 that was stored after the last time it was used.
182 The precise value is the insn generated to do the store. */
183 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
185 /* This is the register that was stored with spill_reg_store. This is a
186 copy of reload_out / reload_out_reg when the value was stored; if
187 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
188 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
190 /* This table is the inverse mapping of spill_regs:
191 indexed by hard reg number,
192 it contains the position of that reg in spill_regs,
193 or -1 for something that is not in spill_regs.
195 ?!? This is no longer accurate. */
196 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
198 /* This reg set indicates registers that can't be used as spill registers for
199 the currently processed insn. These are the hard registers which are live
200 during the insn, but not allocated to pseudos, as well as fixed
202 static HARD_REG_SET bad_spill_regs
;
204 /* These are the hard registers that can't be used as spill register for any
205 insn. This includes registers used for user variables and registers that
206 we can't eliminate. A register that appears in this set also can't be used
207 to retry register allocation. */
208 static HARD_REG_SET bad_spill_regs_global
;
210 /* Describes order of use of registers for reloading
211 of spilled pseudo-registers. `n_spills' is the number of
212 elements that are actually valid; new ones are added at the end.
214 Both spill_regs and spill_reg_order are used on two occasions:
215 once during find_reload_regs, where they keep track of the spill registers
216 for a single insn, but also during reload_as_needed where they show all
217 the registers ever used by reload. For the latter case, the information
218 is calculated during finish_spills. */
219 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
221 /* This vector of reg sets indicates, for each pseudo, which hard registers
222 may not be used for retrying global allocation because the register was
223 formerly spilled from one of them. If we allowed reallocating a pseudo to
224 a register that it was already allocated to, reload might not
226 static HARD_REG_SET
*pseudo_previous_regs
;
228 /* This vector of reg sets indicates, for each pseudo, which hard
229 registers may not be used for retrying global allocation because they
230 are used as spill registers during one of the insns in which the
232 static HARD_REG_SET
*pseudo_forbidden_regs
;
234 /* All hard regs that have been used as spill registers for any insn are
235 marked in this set. */
236 static HARD_REG_SET used_spill_regs
;
238 /* Index of last register assigned as a spill register. We allocate in
239 a round-robin fashion. */
240 static int last_spill_reg
;
242 /* Record the stack slot for each spilled hard register. */
243 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
245 /* Width allocated so far for that stack slot. */
246 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
248 /* Record which pseudos needed to be spilled. */
249 static regset_head spilled_pseudos
;
251 /* Record which pseudos changed their allocation in finish_spills. */
252 static regset_head changed_allocation_pseudos
;
254 /* Used for communication between order_regs_for_reload and count_pseudo.
255 Used to avoid counting one pseudo twice. */
256 static regset_head pseudos_counted
;
258 /* First uid used by insns created by reload in this function.
259 Used in find_equiv_reg. */
260 int reload_first_uid
;
262 /* Flag set by local-alloc or global-alloc if anything is live in
263 a call-clobbered reg across calls. */
264 int caller_save_needed
;
266 /* Set to 1 while reload_as_needed is operating.
267 Required by some machines to handle any generated moves differently. */
268 int reload_in_progress
= 0;
270 /* This obstack is used for allocation of rtl during register elimination.
271 The allocated storage can be freed once find_reloads has processed the
273 static struct obstack reload_obstack
;
275 /* Points to the beginning of the reload_obstack. All insn_chain structures
276 are allocated first. */
277 static char *reload_startobj
;
279 /* The point after all insn_chain structures. Used to quickly deallocate
280 memory allocated in copy_reloads during calculate_needs_all_insns. */
281 static char *reload_firstobj
;
283 /* This points before all local rtl generated by register elimination.
284 Used to quickly free all memory after processing one insn. */
285 static char *reload_insn_firstobj
;
287 /* List of insn_chain instructions, one for every insn that reload needs to
289 struct insn_chain
*reload_insn_chain
;
291 /* List of all insns needing reloads. */
292 static struct insn_chain
*insns_need_reload
;
294 /* This structure is used to record information about register eliminations.
295 Each array entry describes one possible way of eliminating a register
296 in favor of another. If there is more than one way of eliminating a
297 particular register, the most preferred should be specified first. */
301 int from
; /* Register number to be eliminated. */
302 int to
; /* Register number used as replacement. */
303 HOST_WIDE_INT initial_offset
; /* Initial difference between values. */
304 int can_eliminate
; /* Nonzero if this elimination can be done. */
305 int can_eliminate_previous
; /* Value returned by TARGET_CAN_ELIMINATE
306 target hook in previous scan over insns
308 HOST_WIDE_INT offset
; /* Current offset between the two regs. */
309 HOST_WIDE_INT previous_offset
;/* Offset at end of previous insn. */
310 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
311 rtx from_rtx
; /* REG rtx for the register to be eliminated.
312 We cannot simply compare the number since
313 we might then spuriously replace a hard
314 register corresponding to a pseudo
315 assigned to the reg to be eliminated. */
316 rtx to_rtx
; /* REG rtx for the replacement. */
319 static struct elim_table
*reg_eliminate
= 0;
321 /* This is an intermediate structure to initialize the table. It has
322 exactly the members provided by ELIMINABLE_REGS. */
323 static const struct elim_table_1
327 } reg_eliminate_1
[] =
329 /* If a set of eliminable registers was specified, define the table from it.
330 Otherwise, default to the normal case of the frame pointer being
331 replaced by the stack pointer. */
333 #ifdef ELIMINABLE_REGS
336 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
339 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
341 /* Record the number of pending eliminations that have an offset not equal
342 to their initial offset. If nonzero, we use a new copy of each
343 replacement result in any insns encountered. */
344 int num_not_at_initial_offset
;
346 /* Count the number of registers that we may be able to eliminate. */
347 static int num_eliminable
;
348 /* And the number of registers that are equivalent to a constant that
349 can be eliminated to frame_pointer / arg_pointer + constant. */
350 static int num_eliminable_invariants
;
352 /* For each label, we record the offset of each elimination. If we reach
353 a label by more than one path and an offset differs, we cannot do the
354 elimination. This information is indexed by the difference of the
355 number of the label and the first label number. We can't offset the
356 pointer itself as this can cause problems on machines with segmented
357 memory. The first table is an array of flags that records whether we
358 have yet encountered a label and the second table is an array of arrays,
359 one entry in the latter array for each elimination. */
361 static int first_label_num
;
362 static char *offsets_known_at
;
363 static HOST_WIDE_INT (*offsets_at
)[NUM_ELIMINABLE_REGS
];
365 /* Stack of addresses where an rtx has been changed. We can undo the
366 changes by popping items off the stack and restoring the original
367 value at each location.
369 We use this simplistic undo capability rather than copy_rtx as copy_rtx
370 will not make a deep copy of a normally sharable rtx, such as
371 (const (plus (symbol_ref) (const_int))). If such an expression appears
372 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
373 rtx expression would be changed. See PR 42431. */
377 DEF_VEC_ALLOC_P(rtx_p
,heap
);
378 static VEC(rtx_p
,heap
) *substitute_stack
;
380 /* Number of labels in the current function. */
382 static int num_labels
;
384 static void replace_pseudos_in (rtx
*, enum machine_mode
, rtx
);
385 static void maybe_fix_stack_asms (void);
386 static void copy_reloads (struct insn_chain
*);
387 static void calculate_needs_all_insns (int);
388 static int find_reg (struct insn_chain
*, int);
389 static void find_reload_regs (struct insn_chain
*);
390 static void select_reload_regs (void);
391 static void delete_caller_save_insns (void);
393 static void spill_failure (rtx
, enum reg_class
);
394 static void count_spilled_pseudo (int, int, int);
395 static void delete_dead_insn (rtx
);
396 static void alter_reg (int, int, bool);
397 static void set_label_offsets (rtx
, rtx
, int);
398 static void check_eliminable_occurrences (rtx
);
399 static void elimination_effects (rtx
, enum machine_mode
);
400 static rtx
eliminate_regs_1 (rtx
, enum machine_mode
, rtx
, bool, bool);
401 static int eliminate_regs_in_insn (rtx
, int);
402 static void update_eliminable_offsets (void);
403 static void mark_not_eliminable (rtx
, const_rtx
, void *);
404 static void set_initial_elim_offsets (void);
405 static bool verify_initial_elim_offsets (void);
406 static void set_initial_label_offsets (void);
407 static void set_offsets_for_label (rtx
);
408 static void init_eliminable_invariants (rtx
, bool);
409 static void init_elim_table (void);
410 static void free_reg_equiv (void);
411 static void update_eliminables (HARD_REG_SET
*);
412 static void elimination_costs_in_insn (rtx
);
413 static void spill_hard_reg (unsigned int, int);
414 static int finish_spills (int);
415 static void scan_paradoxical_subregs (rtx
);
416 static void count_pseudo (int);
417 static void order_regs_for_reload (struct insn_chain
*);
418 static void reload_as_needed (int);
419 static void forget_old_reloads_1 (rtx
, const_rtx
, void *);
420 static void forget_marked_reloads (regset
);
421 static int reload_reg_class_lower (const void *, const void *);
422 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
424 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
426 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
427 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
429 static int free_for_value_p (int, enum machine_mode
, int, enum reload_type
,
431 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type
);
432 static int allocate_reload_reg (struct insn_chain
*, int, int);
433 static int conflicts_with_override (rtx
);
434 static void failed_reload (rtx
, int);
435 static int set_reload_reg (int, int);
436 static void choose_reload_regs_init (struct insn_chain
*, rtx
*);
437 static void choose_reload_regs (struct insn_chain
*);
438 static void emit_input_reload_insns (struct insn_chain
*, struct reload
*,
440 static void emit_output_reload_insns (struct insn_chain
*, struct reload
*,
442 static void do_input_reload (struct insn_chain
*, struct reload
*, int);
443 static void do_output_reload (struct insn_chain
*, struct reload
*, int);
444 static void emit_reload_insns (struct insn_chain
*);
445 static void delete_output_reload (rtx
, int, int, rtx
);
446 static void delete_address_reloads (rtx
, rtx
);
447 static void delete_address_reloads_1 (rtx
, rtx
, rtx
);
448 static rtx
inc_for_reload (rtx
, rtx
, rtx
, int);
450 static void add_auto_inc_notes (rtx
, rtx
);
452 static void substitute (rtx
*, const_rtx
, rtx
);
453 static bool gen_reload_chain_without_interm_reg_p (int, int);
454 static int reloads_conflict (int, int);
455 static rtx
gen_reload (rtx
, rtx
, int, enum reload_type
);
456 static rtx
emit_insn_if_valid_for_reload (rtx
);
458 /* Initialize the reload pass. This is called at the beginning of compilation
459 and may be called again if the target is reinitialized. */
466 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
467 Set spill_indirect_levels to the number of levels such addressing is
468 permitted, zero if it is not permitted at all. */
471 = gen_rtx_MEM (Pmode
,
474 LAST_VIRTUAL_REGISTER
+ 1),
476 spill_indirect_levels
= 0;
478 while (memory_address_p (QImode
, tem
))
480 spill_indirect_levels
++;
481 tem
= gen_rtx_MEM (Pmode
, tem
);
484 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
486 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
487 indirect_symref_ok
= memory_address_p (QImode
, tem
);
489 /* See if reg+reg is a valid (and offsettable) address. */
491 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
493 tem
= gen_rtx_PLUS (Pmode
,
494 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
495 gen_rtx_REG (Pmode
, i
));
497 /* This way, we make sure that reg+reg is an offsettable address. */
498 tem
= plus_constant (tem
, 4);
500 if (memory_address_p (QImode
, tem
))
502 double_reg_address_ok
= 1;
507 /* Initialize obstack for our rtl allocation. */
508 gcc_obstack_init (&reload_obstack
);
509 reload_startobj
= XOBNEWVAR (&reload_obstack
, char, 0);
511 INIT_REG_SET (&spilled_pseudos
);
512 INIT_REG_SET (&changed_allocation_pseudos
);
513 INIT_REG_SET (&pseudos_counted
);
516 /* List of insn chains that are currently unused. */
517 static struct insn_chain
*unused_insn_chains
= 0;
519 /* Allocate an empty insn_chain structure. */
521 new_insn_chain (void)
523 struct insn_chain
*c
;
525 if (unused_insn_chains
== 0)
527 c
= XOBNEW (&reload_obstack
, struct insn_chain
);
528 INIT_REG_SET (&c
->live_throughout
);
529 INIT_REG_SET (&c
->dead_or_set
);
533 c
= unused_insn_chains
;
534 unused_insn_chains
= c
->next
;
536 c
->is_caller_save_insn
= 0;
537 c
->need_operand_change
= 0;
543 /* Small utility function to set all regs in hard reg set TO which are
544 allocated to pseudos in regset FROM. */
547 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
550 reg_set_iterator rsi
;
552 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
554 int r
= reg_renumber
[regno
];
558 /* reload_combine uses the information from DF_LIVE_IN,
559 which might still contain registers that have not
560 actually been allocated since they have an
562 gcc_assert (ira_conflicts_p
|| reload_completed
);
565 add_to_hard_reg_set (to
, PSEUDO_REGNO_MODE (regno
), r
);
569 /* Replace all pseudos found in LOC with their corresponding
573 replace_pseudos_in (rtx
*loc
, enum machine_mode mem_mode
, rtx usage
)
586 unsigned int regno
= REGNO (x
);
588 if (regno
< FIRST_PSEUDO_REGISTER
)
591 x
= eliminate_regs_1 (x
, mem_mode
, usage
, true, false);
595 replace_pseudos_in (loc
, mem_mode
, usage
);
599 if (reg_equiv_constant
[regno
])
600 *loc
= reg_equiv_constant
[regno
];
601 else if (reg_equiv_invariant
[regno
])
602 *loc
= reg_equiv_invariant
[regno
];
603 else if (reg_equiv_mem
[regno
])
604 *loc
= reg_equiv_mem
[regno
];
605 else if (reg_equiv_address
[regno
])
606 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address
[regno
]);
609 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
610 || REGNO (regno_reg_rtx
[regno
]) != regno
);
611 *loc
= regno_reg_rtx
[regno
];
616 else if (code
== MEM
)
618 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
622 /* Process each of our operands recursively. */
623 fmt
= GET_RTX_FORMAT (code
);
624 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
626 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
627 else if (*fmt
== 'E')
628 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
629 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
632 /* Determine if the current function has an exception receiver block
633 that reaches the exit block via non-exceptional edges */
636 has_nonexceptional_receiver (void)
640 basic_block
*tos
, *worklist
, bb
;
642 /* If we're not optimizing, then just err on the safe side. */
646 /* First determine which blocks can reach exit via normal paths. */
647 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks
+ 1);
650 bb
->flags
&= ~BB_REACHABLE
;
652 /* Place the exit block on our worklist. */
653 EXIT_BLOCK_PTR
->flags
|= BB_REACHABLE
;
654 *tos
++ = EXIT_BLOCK_PTR
;
656 /* Iterate: find everything reachable from what we've already seen. */
657 while (tos
!= worklist
)
661 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
662 if (!(e
->flags
& EDGE_ABNORMAL
))
664 basic_block src
= e
->src
;
666 if (!(src
->flags
& BB_REACHABLE
))
668 src
->flags
|= BB_REACHABLE
;
675 /* Now see if there's a reachable block with an exceptional incoming
678 if (bb
->flags
& BB_REACHABLE
)
679 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
680 if (e
->flags
& EDGE_ABNORMAL
)
683 /* No exceptional block reached exit unexceptionally. */
688 /* Global variables used by reload and its subroutines. */
690 /* The current basic block while in calculate_elim_costs_all_insns. */
691 static basic_block elim_bb
;
693 /* Set during calculate_needs if an insn needs register elimination. */
694 static int something_needs_elimination
;
695 /* Set during calculate_needs if an insn needs an operand changed. */
696 static int something_needs_operands_changed
;
697 /* Set by alter_regs if we spilled a register to the stack. */
698 static bool something_was_spilled
;
700 /* Nonzero means we couldn't get enough spill regs. */
703 /* Temporary array of pseudo-register number. */
704 static int *temp_pseudo_reg_arr
;
706 /* Main entry point for the reload pass.
708 FIRST is the first insn of the function being compiled.
710 GLOBAL nonzero means we were called from global_alloc
711 and should attempt to reallocate any pseudoregs that we
712 displace from hard regs we will use for reloads.
713 If GLOBAL is zero, we do not have enough information to do that,
714 so any pseudo reg that is spilled must go to the stack.
716 Return value is nonzero if reload failed
717 and we must not do any more for this function. */
720 reload (rtx first
, int global
)
724 struct elim_table
*ep
;
727 /* Make sure even insns with volatile mem refs are recognizable. */
732 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
734 /* Make sure that the last insn in the chain
735 is not something that needs reloading. */
736 emit_note (NOTE_INSN_DELETED
);
738 /* Enable find_equiv_reg to distinguish insns made by reload. */
739 reload_first_uid
= get_max_uid ();
741 #ifdef SECONDARY_MEMORY_NEEDED
742 /* Initialize the secondary memory table. */
743 clear_secondary_mem ();
746 /* We don't have a stack slot for any spill reg yet. */
747 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
748 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
750 /* Initialize the save area information for caller-save, in case some
754 /* Compute which hard registers are now in use
755 as homes for pseudo registers.
756 This is done here rather than (eg) in global_alloc
757 because this point is reached even if not optimizing. */
758 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
761 /* A function that has a nonlocal label that can reach the exit
762 block via non-exceptional paths must save all call-saved
764 if (cfun
->has_nonlocal_label
765 && has_nonexceptional_receiver ())
766 crtl
->saves_all_registers
= 1;
768 if (crtl
->saves_all_registers
)
769 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
770 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
771 df_set_regs_ever_live (i
, true);
773 reg_old_renumber
= XCNEWVEC (short, max_regno
);
774 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
775 pseudo_forbidden_regs
= XNEWVEC (HARD_REG_SET
, max_regno
);
776 pseudo_previous_regs
= XCNEWVEC (HARD_REG_SET
, max_regno
);
778 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
780 init_eliminable_invariants (first
, true);
783 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
784 stack slots to the pseudos that lack hard regs or equivalents.
785 Do not touch virtual registers. */
787 temp_pseudo_reg_arr
= XNEWVEC (int, max_regno
- LAST_VIRTUAL_REGISTER
- 1);
788 for (n
= 0, i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
789 temp_pseudo_reg_arr
[n
++] = i
;
792 /* Ask IRA to order pseudo-registers for better stack slot
794 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr
, n
, reg_max_ref_width
);
796 for (i
= 0; i
< n
; i
++)
797 alter_reg (temp_pseudo_reg_arr
[i
], -1, false);
799 /* If we have some registers we think can be eliminated, scan all insns to
800 see if there is an insn that sets one of these registers to something
801 other than itself plus a constant. If so, the register cannot be
802 eliminated. Doing this scan here eliminates an extra pass through the
803 main reload loop in the most common case where register elimination
805 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
807 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
809 maybe_fix_stack_asms ();
811 insns_need_reload
= 0;
812 something_needs_elimination
= 0;
814 /* Initialize to -1, which means take the first spill register. */
817 /* Spill any hard regs that we know we can't eliminate. */
818 CLEAR_HARD_REG_SET (used_spill_regs
);
819 /* There can be multiple ways to eliminate a register;
820 they should be listed adjacently.
821 Elimination for any register fails only if all possible ways fail. */
822 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
825 int can_eliminate
= 0;
828 can_eliminate
|= ep
->can_eliminate
;
831 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
833 spill_hard_reg (from
, 1);
836 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
837 if (frame_pointer_needed
)
838 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
840 finish_spills (global
);
842 /* From now on, we may need to generate moves differently. We may also
843 allow modifications of insns which cause them to not be recognized.
844 Any such modifications will be cleaned up during reload itself. */
845 reload_in_progress
= 1;
847 /* This loop scans the entire function each go-round
848 and repeats until one repetition spills no additional hard regs. */
851 int something_changed
;
853 HOST_WIDE_INT starting_frame_size
;
855 starting_frame_size
= get_frame_size ();
856 something_was_spilled
= false;
858 set_initial_elim_offsets ();
859 set_initial_label_offsets ();
861 /* For each pseudo register that has an equivalent location defined,
862 try to eliminate any eliminable registers (such as the frame pointer)
863 assuming initial offsets for the replacement register, which
866 If the resulting location is directly addressable, substitute
867 the MEM we just got directly for the old REG.
869 If it is not addressable but is a constant or the sum of a hard reg
870 and constant, it is probably not addressable because the constant is
871 out of range, in that case record the address; we will generate
872 hairy code to compute the address in a register each time it is
873 needed. Similarly if it is a hard register, but one that is not
874 valid as an address register.
876 If the location is not addressable, but does not have one of the
877 above forms, assign a stack slot. We have to do this to avoid the
878 potential of producing lots of reloads if, e.g., a location involves
879 a pseudo that didn't get a hard register and has an equivalent memory
880 location that also involves a pseudo that didn't get a hard register.
882 Perhaps at some point we will improve reload_when_needed handling
883 so this problem goes away. But that's very hairy. */
885 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
886 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc
[i
])
888 rtx x
= eliminate_regs (reg_equiv_memory_loc
[i
], VOIDmode
,
891 if (strict_memory_address_addr_space_p
892 (GET_MODE (regno_reg_rtx
[i
]), XEXP (x
, 0),
894 reg_equiv_mem
[i
] = x
, reg_equiv_address
[i
] = 0;
895 else if (CONSTANT_P (XEXP (x
, 0))
896 || (REG_P (XEXP (x
, 0))
897 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
898 || (GET_CODE (XEXP (x
, 0)) == PLUS
899 && REG_P (XEXP (XEXP (x
, 0), 0))
900 && (REGNO (XEXP (XEXP (x
, 0), 0))
901 < FIRST_PSEUDO_REGISTER
)
902 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
903 reg_equiv_address
[i
] = XEXP (x
, 0), reg_equiv_mem
[i
] = 0;
906 /* Make a new stack slot. Then indicate that something
907 changed so we go back and recompute offsets for
908 eliminable registers because the allocation of memory
909 below might change some offset. reg_equiv_{mem,address}
910 will be set up for this pseudo on the next pass around
912 reg_equiv_memory_loc
[i
] = 0;
913 reg_equiv_init
[i
] = 0;
914 alter_reg (i
, -1, true);
918 if (caller_save_needed
)
921 /* If we allocated another stack slot, redo elimination bookkeeping. */
922 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
924 if (starting_frame_size
&& crtl
->stack_alignment_needed
)
926 /* If we have a stack frame, we must align it now. The
927 stack size may be a part of the offset computation for
928 register elimination. So if this changes the stack size,
929 then repeat the elimination bookkeeping. We don't
930 realign when there is no stack, as that will cause a
931 stack frame when none is needed should
932 STARTING_FRAME_OFFSET not be already aligned to
934 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
935 if (starting_frame_size
!= get_frame_size ())
939 if (caller_save_needed
)
941 save_call_clobbered_regs ();
942 /* That might have allocated new insn_chain structures. */
943 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
946 calculate_needs_all_insns (global
);
948 if (! ira_conflicts_p
)
949 /* Don't do it for IRA. We need this info because we don't
950 change live_throughout and dead_or_set for chains when IRA
952 CLEAR_REG_SET (&spilled_pseudos
);
956 something_changed
= 0;
958 /* If we allocated any new memory locations, make another pass
959 since it might have changed elimination offsets. */
960 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
961 something_changed
= 1;
963 /* Even if the frame size remained the same, we might still have
964 changed elimination offsets, e.g. if find_reloads called
965 force_const_mem requiring the back end to allocate a constant
966 pool base register that needs to be saved on the stack. */
967 else if (!verify_initial_elim_offsets ())
968 something_changed
= 1;
971 HARD_REG_SET to_spill
;
972 CLEAR_HARD_REG_SET (to_spill
);
973 update_eliminables (&to_spill
);
974 AND_COMPL_HARD_REG_SET (used_spill_regs
, to_spill
);
976 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
977 if (TEST_HARD_REG_BIT (to_spill
, i
))
979 spill_hard_reg (i
, 1);
982 /* Regardless of the state of spills, if we previously had
983 a register that we thought we could eliminate, but now can
984 not eliminate, we must run another pass.
986 Consider pseudos which have an entry in reg_equiv_* which
987 reference an eliminable register. We must make another pass
988 to update reg_equiv_* so that we do not substitute in the
989 old value from when we thought the elimination could be
991 something_changed
= 1;
995 select_reload_regs ();
999 if (insns_need_reload
!= 0 || did_spill
)
1000 something_changed
|= finish_spills (global
);
1002 if (! something_changed
)
1005 if (caller_save_needed
)
1006 delete_caller_save_insns ();
1008 obstack_free (&reload_obstack
, reload_firstobj
);
1011 /* If global-alloc was run, notify it of any register eliminations we have
1014 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1015 if (ep
->can_eliminate
)
1016 mark_elimination (ep
->from
, ep
->to
);
1018 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1019 If that insn didn't set the register (i.e., it copied the register to
1020 memory), just delete that insn instead of the equivalencing insn plus
1021 anything now dead. If we call delete_dead_insn on that insn, we may
1022 delete the insn that actually sets the register if the register dies
1023 there and that is incorrect. */
1025 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1027 if (reg_renumber
[i
] < 0 && reg_equiv_init
[i
] != 0)
1030 for (list
= reg_equiv_init
[i
]; list
; list
= XEXP (list
, 1))
1032 rtx equiv_insn
= XEXP (list
, 0);
1034 /* If we already deleted the insn or if it may trap, we can't
1035 delete it. The latter case shouldn't happen, but can
1036 if an insn has a variable address, gets a REG_EH_REGION
1037 note added to it, and then gets converted into a load
1038 from a constant address. */
1039 if (NOTE_P (equiv_insn
)
1040 || can_throw_internal (equiv_insn
))
1042 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
1043 delete_dead_insn (equiv_insn
);
1045 SET_INSN_DELETED (equiv_insn
);
1050 /* Use the reload registers where necessary
1051 by generating move instructions to move the must-be-register
1052 values into or out of the reload registers. */
1054 if (insns_need_reload
!= 0 || something_needs_elimination
1055 || something_needs_operands_changed
)
1057 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1059 reload_as_needed (global
);
1061 gcc_assert (old_frame_size
== get_frame_size ());
1063 gcc_assert (verify_initial_elim_offsets ());
1066 /* If we were able to eliminate the frame pointer, show that it is no
1067 longer live at the start of any basic block. If it ls live by
1068 virtue of being in a pseudo, that pseudo will be marked live
1069 and hence the frame pointer will be known to be live via that
1072 if (! frame_pointer_needed
)
1074 bitmap_clear_bit (df_get_live_in (bb
), HARD_FRAME_POINTER_REGNUM
);
1076 /* Come here (with failure set nonzero) if we can't get enough spill
1080 CLEAR_REG_SET (&changed_allocation_pseudos
);
1081 CLEAR_REG_SET (&spilled_pseudos
);
1082 reload_in_progress
= 0;
1084 /* Now eliminate all pseudo regs by modifying them into
1085 their equivalent memory references.
1086 The REG-rtx's for the pseudos are modified in place,
1087 so all insns that used to refer to them now refer to memory.
1089 For a reg that has a reg_equiv_address, all those insns
1090 were changed by reloading so that no insns refer to it any longer;
1091 but the DECL_RTL of a variable decl may refer to it,
1092 and if so this causes the debugging info to mention the variable. */
1094 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1098 if (reg_equiv_mem
[i
])
1099 addr
= XEXP (reg_equiv_mem
[i
], 0);
1101 if (reg_equiv_address
[i
])
1102 addr
= reg_equiv_address
[i
];
1106 if (reg_renumber
[i
] < 0)
1108 rtx reg
= regno_reg_rtx
[i
];
1110 REG_USERVAR_P (reg
) = 0;
1111 PUT_CODE (reg
, MEM
);
1112 XEXP (reg
, 0) = addr
;
1113 if (reg_equiv_memory_loc
[i
])
1114 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc
[i
]);
1117 MEM_IN_STRUCT_P (reg
) = MEM_SCALAR_P (reg
) = 0;
1118 MEM_ATTRS (reg
) = 0;
1120 MEM_NOTRAP_P (reg
) = 1;
1122 else if (reg_equiv_mem
[i
])
1123 XEXP (reg_equiv_mem
[i
], 0) = addr
;
1126 /* We don't want complex addressing modes in debug insns
1127 if simpler ones will do, so delegitimize equivalences
1129 if (MAY_HAVE_DEBUG_INSNS
&& reg_renumber
[i
] < 0)
1131 rtx reg
= regno_reg_rtx
[i
];
1135 if (reg_equiv_constant
[i
])
1136 equiv
= reg_equiv_constant
[i
];
1137 else if (reg_equiv_invariant
[i
])
1138 equiv
= reg_equiv_invariant
[i
];
1139 else if (reg
&& MEM_P (reg
))
1140 equiv
= targetm
.delegitimize_address (reg
);
1141 else if (reg
&& REG_P (reg
) && (int)REGNO (reg
) != i
)
1147 for (use
= DF_REG_USE_CHAIN (i
); use
; use
= next
)
1149 insn
= DF_REF_INSN (use
);
1151 /* Make sure the next ref is for a different instruction,
1152 so that we're not affected by the rescan. */
1153 next
= DF_REF_NEXT_REG (use
);
1154 while (next
&& DF_REF_INSN (next
) == insn
)
1155 next
= DF_REF_NEXT_REG (next
);
1157 if (DEBUG_INSN_P (insn
))
1161 INSN_VAR_LOCATION_LOC (insn
) = gen_rtx_UNKNOWN_VAR_LOC ();
1162 df_insn_rescan_debug_internal (insn
);
1165 INSN_VAR_LOCATION_LOC (insn
)
1166 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn
),
1173 /* We must set reload_completed now since the cleanup_subreg_operands call
1174 below will re-recognize each insn and reload may have generated insns
1175 which are only valid during and after reload. */
1176 reload_completed
= 1;
1178 /* Make a pass over all the insns and delete all USEs which we inserted
1179 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1180 notes. Delete all CLOBBER insns, except those that refer to the return
1181 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1182 from misarranging variable-array code, and simplify (subreg (reg))
1183 operands. Strip and regenerate REG_INC notes that may have been moved
1186 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1192 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1193 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1195 if ((GET_CODE (PATTERN (insn
)) == USE
1196 /* We mark with QImode USEs introduced by reload itself. */
1197 && (GET_MODE (insn
) == QImode
1198 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1199 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1200 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1201 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1202 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1203 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1204 != stack_pointer_rtx
))
1205 && (!REG_P (XEXP (PATTERN (insn
), 0))
1206 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1212 /* Some CLOBBERs may survive until here and still reference unassigned
1213 pseudos with const equivalent, which may in turn cause ICE in later
1214 passes if the reference remains in place. */
1215 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1216 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1217 VOIDmode
, PATTERN (insn
));
1219 /* Discard obvious no-ops, even without -O. This optimization
1220 is fast and doesn't interfere with debugging. */
1221 if (NONJUMP_INSN_P (insn
)
1222 && GET_CODE (PATTERN (insn
)) == SET
1223 && REG_P (SET_SRC (PATTERN (insn
)))
1224 && REG_P (SET_DEST (PATTERN (insn
)))
1225 && (REGNO (SET_SRC (PATTERN (insn
)))
1226 == REGNO (SET_DEST (PATTERN (insn
)))))
1232 pnote
= ®_NOTES (insn
);
1235 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1236 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1237 || REG_NOTE_KIND (*pnote
) == REG_INC
)
1238 *pnote
= XEXP (*pnote
, 1);
1240 pnote
= &XEXP (*pnote
, 1);
1244 add_auto_inc_notes (insn
, PATTERN (insn
));
1247 /* Simplify (subreg (reg)) if it appears as an operand. */
1248 cleanup_subreg_operands (insn
);
1250 /* Clean up invalid ASMs so that they don't confuse later passes.
1252 if (asm_noperands (PATTERN (insn
)) >= 0)
1254 extract_insn (insn
);
1255 if (!constrain_operands (1))
1257 error_for_asm (insn
,
1258 "%<asm%> operand has impossible constraints");
1265 /* If we are doing generic stack checking, give a warning if this
1266 function's frame size is larger than we expect. */
1267 if (flag_stack_check
== GENERIC_STACK_CHECK
)
1269 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1270 static int verbose_warned
= 0;
1272 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1273 if (df_regs_ever_live_p (i
) && ! fixed_regs
[i
] && call_used_regs
[i
])
1274 size
+= UNITS_PER_WORD
;
1276 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1278 warning (0, "frame size too large for reliable stack checking");
1279 if (! verbose_warned
)
1281 warning (0, "try reducing the number of local variables");
1287 free (temp_pseudo_reg_arr
);
1289 /* Indicate that we no longer have known memory locations or constants. */
1292 free (reg_max_ref_width
);
1293 free (reg_old_renumber
);
1294 free (pseudo_previous_regs
);
1295 free (pseudo_forbidden_regs
);
1297 CLEAR_HARD_REG_SET (used_spill_regs
);
1298 for (i
= 0; i
< n_spills
; i
++)
1299 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1301 /* Free all the insn_chain structures at once. */
1302 obstack_free (&reload_obstack
, reload_startobj
);
1303 unused_insn_chains
= 0;
1304 fixup_abnormal_edges ();
1306 /* Replacing pseudos with their memory equivalents might have
1307 created shared rtx. Subsequent passes would get confused
1308 by this, so unshare everything here. */
1309 unshare_all_rtl_again (first
);
1311 #ifdef STACK_BOUNDARY
1312 /* init_emit has set the alignment of the hard frame pointer
1313 to STACK_BOUNDARY. It is very likely no longer valid if
1314 the hard frame pointer was used for register allocation. */
1315 if (!frame_pointer_needed
)
1316 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1319 VEC_free (rtx_p
, heap
, substitute_stack
);
1321 gcc_assert (bitmap_empty_p (&spilled_pseudos
));
1326 /* Yet another special case. Unfortunately, reg-stack forces people to
1327 write incorrect clobbers in asm statements. These clobbers must not
1328 cause the register to appear in bad_spill_regs, otherwise we'll call
1329 fatal_insn later. We clear the corresponding regnos in the live
1330 register sets to avoid this.
1331 The whole thing is rather sick, I'm afraid. */
1334 maybe_fix_stack_asms (void)
1337 const char *constraints
[MAX_RECOG_OPERANDS
];
1338 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1339 struct insn_chain
*chain
;
1341 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1344 HARD_REG_SET clobbered
, allowed
;
1347 if (! INSN_P (chain
->insn
)
1348 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1350 pat
= PATTERN (chain
->insn
);
1351 if (GET_CODE (pat
) != PARALLEL
)
1354 CLEAR_HARD_REG_SET (clobbered
);
1355 CLEAR_HARD_REG_SET (allowed
);
1357 /* First, make a mask of all stack regs that are clobbered. */
1358 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1360 rtx t
= XVECEXP (pat
, 0, i
);
1361 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1362 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1365 /* Get the operand values and constraints out of the insn. */
1366 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1367 constraints
, operand_mode
, NULL
);
1369 /* For every operand, see what registers are allowed. */
1370 for (i
= 0; i
< noperands
; i
++)
1372 const char *p
= constraints
[i
];
1373 /* For every alternative, we compute the class of registers allowed
1374 for reloading in CLS, and merge its contents into the reg set
1376 int cls
= (int) NO_REGS
;
1382 if (c
== '\0' || c
== ',' || c
== '#')
1384 /* End of one alternative - mark the regs in the current
1385 class, and reset the class. */
1386 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1392 } while (c
!= '\0' && c
!= ',');
1400 case '=': case '+': case '*': case '%': case '?': case '!':
1401 case '0': case '1': case '2': case '3': case '4': case '<':
1402 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1403 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1404 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1405 case TARGET_MEM_CONSTRAINT
:
1409 cls
= (int) reg_class_subunion
[cls
]
1410 [(int) base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
1415 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1419 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1420 cls
= (int) reg_class_subunion
[cls
]
1421 [(int) base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
1423 cls
= (int) reg_class_subunion
[cls
]
1424 [(int) REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1426 p
+= CONSTRAINT_LEN (c
, p
);
1429 /* Those of the registers which are clobbered, but allowed by the
1430 constraints, must be usable as reload registers. So clear them
1431 out of the life information. */
1432 AND_HARD_REG_SET (allowed
, clobbered
);
1433 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1434 if (TEST_HARD_REG_BIT (allowed
, i
))
1436 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1437 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1444 /* Copy the global variables n_reloads and rld into the corresponding elts
1447 copy_reloads (struct insn_chain
*chain
)
1449 chain
->n_reloads
= n_reloads
;
1450 chain
->rld
= XOBNEWVEC (&reload_obstack
, struct reload
, n_reloads
);
1451 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1452 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1455 /* Walk the chain of insns, and determine for each whether it needs reloads
1456 and/or eliminations. Build the corresponding insns_need_reload list, and
1457 set something_needs_elimination as appropriate. */
1459 calculate_needs_all_insns (int global
)
1461 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1462 struct insn_chain
*chain
, *next
= 0;
1464 something_needs_elimination
= 0;
1466 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1467 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1469 rtx insn
= chain
->insn
;
1473 /* Clear out the shortcuts. */
1474 chain
->n_reloads
= 0;
1475 chain
->need_elim
= 0;
1476 chain
->need_reload
= 0;
1477 chain
->need_operand_change
= 0;
1479 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1480 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1481 what effects this has on the known offsets at labels. */
1483 if (LABEL_P (insn
) || JUMP_P (insn
)
1484 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1485 set_label_offsets (insn
, insn
, 0);
1489 rtx old_body
= PATTERN (insn
);
1490 int old_code
= INSN_CODE (insn
);
1491 rtx old_notes
= REG_NOTES (insn
);
1492 int did_elimination
= 0;
1493 int operands_changed
= 0;
1494 rtx set
= single_set (insn
);
1496 /* Skip insns that only set an equivalence. */
1497 if (set
&& REG_P (SET_DEST (set
))
1498 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1499 && (reg_equiv_constant
[REGNO (SET_DEST (set
))]
1500 || (reg_equiv_invariant
[REGNO (SET_DEST (set
))]))
1501 && reg_equiv_init
[REGNO (SET_DEST (set
))])
1504 /* If needed, eliminate any eliminable registers. */
1505 if (num_eliminable
|| num_eliminable_invariants
)
1506 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1508 /* Analyze the instruction. */
1509 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1510 global
, spill_reg_order
);
1512 /* If a no-op set needs more than one reload, this is likely
1513 to be something that needs input address reloads. We
1514 can't get rid of this cleanly later, and it is of no use
1515 anyway, so discard it now.
1516 We only do this when expensive_optimizations is enabled,
1517 since this complements reload inheritance / output
1518 reload deletion, and it can make debugging harder. */
1519 if (flag_expensive_optimizations
&& n_reloads
> 1)
1521 rtx set
= single_set (insn
);
1524 ((SET_SRC (set
) == SET_DEST (set
)
1525 && REG_P (SET_SRC (set
))
1526 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1527 || (REG_P (SET_SRC (set
)) && REG_P (SET_DEST (set
))
1528 && reg_renumber
[REGNO (SET_SRC (set
))] < 0
1529 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1530 && reg_equiv_memory_loc
[REGNO (SET_SRC (set
))] != NULL
1531 && reg_equiv_memory_loc
[REGNO (SET_DEST (set
))] != NULL
1532 && rtx_equal_p (reg_equiv_memory_loc
1533 [REGNO (SET_SRC (set
))],
1534 reg_equiv_memory_loc
1535 [REGNO (SET_DEST (set
))]))))
1537 if (ira_conflicts_p
)
1538 /* Inform IRA about the insn deletion. */
1539 ira_mark_memory_move_deletion (REGNO (SET_DEST (set
)),
1540 REGNO (SET_SRC (set
)));
1542 /* Delete it from the reload chain. */
1544 chain
->prev
->next
= next
;
1546 reload_insn_chain
= next
;
1548 next
->prev
= chain
->prev
;
1549 chain
->next
= unused_insn_chains
;
1550 unused_insn_chains
= chain
;
1555 update_eliminable_offsets ();
1557 /* Remember for later shortcuts which insns had any reloads or
1558 register eliminations. */
1559 chain
->need_elim
= did_elimination
;
1560 chain
->need_reload
= n_reloads
> 0;
1561 chain
->need_operand_change
= operands_changed
;
1563 /* Discard any register replacements done. */
1564 if (did_elimination
)
1566 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1567 PATTERN (insn
) = old_body
;
1568 INSN_CODE (insn
) = old_code
;
1569 REG_NOTES (insn
) = old_notes
;
1570 something_needs_elimination
= 1;
1573 something_needs_operands_changed
|= operands_changed
;
1577 copy_reloads (chain
);
1578 *pprev_reload
= chain
;
1579 pprev_reload
= &chain
->next_need_reload
;
1586 /* This function is called from the register allocator to set up estimates
1587 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1588 an invariant. The structure is similar to calculate_needs_all_insns. */
1591 calculate_elim_costs_all_insns (void)
1593 int *reg_equiv_init_cost
;
1597 reg_equiv_init_cost
= XCNEWVEC (int, max_regno
);
1599 init_eliminable_invariants (get_insns (), false);
1601 set_initial_elim_offsets ();
1602 set_initial_label_offsets ();
1609 FOR_BB_INSNS (bb
, insn
)
1611 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1612 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1613 what effects this has on the known offsets at labels. */
1615 if (LABEL_P (insn
) || JUMP_P (insn
)
1616 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1617 set_label_offsets (insn
, insn
, 0);
1621 rtx set
= single_set (insn
);
1623 /* Skip insns that only set an equivalence. */
1624 if (set
&& REG_P (SET_DEST (set
))
1625 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1626 && (reg_equiv_constant
[REGNO (SET_DEST (set
))]
1627 || (reg_equiv_invariant
[REGNO (SET_DEST (set
))])))
1629 unsigned regno
= REGNO (SET_DEST (set
));
1630 rtx init
= reg_equiv_init
[regno
];
1633 rtx t
= eliminate_regs_1 (SET_SRC (set
), VOIDmode
, insn
,
1635 int cost
= rtx_cost (t
, SET
,
1636 optimize_bb_for_speed_p (bb
));
1637 int freq
= REG_FREQ_FROM_BB (bb
);
1639 reg_equiv_init_cost
[regno
] = cost
* freq
;
1643 /* If needed, eliminate any eliminable registers. */
1644 if (num_eliminable
|| num_eliminable_invariants
)
1645 elimination_costs_in_insn (insn
);
1648 update_eliminable_offsets ();
1652 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1654 if (reg_equiv_invariant
[i
])
1656 if (reg_equiv_init
[i
])
1658 int cost
= reg_equiv_init_cost
[i
];
1661 "Reg %d has equivalence, initial gains %d\n", i
, cost
);
1663 ira_adjust_equiv_reg_cost (i
, cost
);
1669 "Reg %d had equivalence, but can't be eliminated\n",
1671 ira_adjust_equiv_reg_cost (i
, 0);
1677 free (reg_equiv_init_cost
);
1680 /* Comparison function for qsort to decide which of two reloads
1681 should be handled first. *P1 and *P2 are the reload numbers. */
1684 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1686 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1689 /* Consider required reloads before optional ones. */
1690 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1694 /* Count all solitary classes before non-solitary ones. */
1695 t
= ((reg_class_size
[(int) rld
[r2
].rclass
] == 1)
1696 - (reg_class_size
[(int) rld
[r1
].rclass
] == 1));
1700 /* Aside from solitaires, consider all multi-reg groups first. */
1701 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1705 /* Consider reloads in order of increasing reg-class number. */
1706 t
= (int) rld
[r1
].rclass
- (int) rld
[r2
].rclass
;
1710 /* If reloads are equally urgent, sort by reload number,
1711 so that the results of qsort leave nothing to chance. */
1715 /* The cost of spilling each hard reg. */
1716 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1718 /* When spilling multiple hard registers, we use SPILL_COST for the first
1719 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1720 only the first hard reg for a multi-reg pseudo. */
1721 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1723 /* Map of hard regno to pseudo regno currently occupying the hard
1725 static int hard_regno_to_pseudo_regno
[FIRST_PSEUDO_REGISTER
];
1727 /* Update the spill cost arrays, considering that pseudo REG is live. */
1730 count_pseudo (int reg
)
1732 int freq
= REG_FREQ (reg
);
1733 int r
= reg_renumber
[reg
];
1736 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1737 || REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1738 /* Ignore spilled pseudo-registers which can be here only if IRA
1740 || (ira_conflicts_p
&& r
< 0))
1743 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1745 gcc_assert (r
>= 0);
1747 spill_add_cost
[r
] += freq
;
1748 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1751 hard_regno_to_pseudo_regno
[r
+ nregs
] = reg
;
1752 spill_cost
[r
+ nregs
] += freq
;
1756 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1757 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1760 order_regs_for_reload (struct insn_chain
*chain
)
1763 HARD_REG_SET used_by_pseudos
;
1764 HARD_REG_SET used_by_pseudos2
;
1765 reg_set_iterator rsi
;
1767 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1769 memset (spill_cost
, 0, sizeof spill_cost
);
1770 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1771 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1772 hard_regno_to_pseudo_regno
[i
] = -1;
1774 /* Count number of uses of each hard reg by pseudo regs allocated to it
1775 and then order them by decreasing use. First exclude hard registers
1776 that are live in or across this insn. */
1778 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1779 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1780 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1781 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1783 /* Now find out which pseudos are allocated to it, and update
1785 CLEAR_REG_SET (&pseudos_counted
);
1787 EXECUTE_IF_SET_IN_REG_SET
1788 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1792 EXECUTE_IF_SET_IN_REG_SET
1793 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1797 CLEAR_REG_SET (&pseudos_counted
);
1800 /* Vector of reload-numbers showing the order in which the reloads should
1802 static short reload_order
[MAX_RELOADS
];
1804 /* This is used to keep track of the spill regs used in one insn. */
1805 static HARD_REG_SET used_spill_regs_local
;
1807 /* We decided to spill hard register SPILLED, which has a size of
1808 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1809 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1810 update SPILL_COST/SPILL_ADD_COST. */
1813 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1815 int freq
= REG_FREQ (reg
);
1816 int r
= reg_renumber
[reg
];
1817 int nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1819 /* Ignore spilled pseudo-registers which can be here only if IRA is
1821 if ((ira_conflicts_p
&& r
< 0)
1822 || REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1823 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1826 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1828 spill_add_cost
[r
] -= freq
;
1831 hard_regno_to_pseudo_regno
[r
+ nregs
] = -1;
1832 spill_cost
[r
+ nregs
] -= freq
;
1836 /* Find reload register to use for reload number ORDER. */
1839 find_reg (struct insn_chain
*chain
, int order
)
1841 int rnum
= reload_order
[order
];
1842 struct reload
*rl
= rld
+ rnum
;
1843 int best_cost
= INT_MAX
;
1845 unsigned int i
, j
, n
;
1847 HARD_REG_SET not_usable
;
1848 HARD_REG_SET used_by_other_reload
;
1849 reg_set_iterator rsi
;
1850 static int regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1851 static int best_regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1853 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1854 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1855 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->rclass
]);
1857 CLEAR_HARD_REG_SET (used_by_other_reload
);
1858 for (k
= 0; k
< order
; k
++)
1860 int other
= reload_order
[k
];
1862 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1863 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1864 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1867 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1869 #ifdef REG_ALLOC_ORDER
1870 unsigned int regno
= reg_alloc_order
[i
];
1872 unsigned int regno
= i
;
1875 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1876 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1877 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1879 int this_cost
= spill_cost
[regno
];
1881 unsigned int this_nregs
= hard_regno_nregs
[regno
][rl
->mode
];
1883 for (j
= 1; j
< this_nregs
; j
++)
1885 this_cost
+= spill_add_cost
[regno
+ j
];
1886 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1887 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1893 if (ira_conflicts_p
)
1895 /* Ask IRA to find a better pseudo-register for
1897 for (n
= j
= 0; j
< this_nregs
; j
++)
1899 int r
= hard_regno_to_pseudo_regno
[regno
+ j
];
1903 if (n
== 0 || regno_pseudo_regs
[n
- 1] != r
)
1904 regno_pseudo_regs
[n
++] = r
;
1906 regno_pseudo_regs
[n
++] = -1;
1908 || ira_better_spill_reload_regno_p (regno_pseudo_regs
,
1909 best_regno_pseudo_regs
,
1916 best_regno_pseudo_regs
[j
] = regno_pseudo_regs
[j
];
1917 if (regno_pseudo_regs
[j
] < 0)
1924 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1926 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1928 if (this_cost
< best_cost
1929 /* Among registers with equal cost, prefer caller-saved ones, or
1930 use REG_ALLOC_ORDER if it is defined. */
1931 || (this_cost
== best_cost
1932 #ifdef REG_ALLOC_ORDER
1933 && (inv_reg_alloc_order
[regno
]
1934 < inv_reg_alloc_order
[best_reg
])
1936 && call_used_regs
[regno
]
1937 && ! call_used_regs
[best_reg
]
1942 best_cost
= this_cost
;
1950 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1952 rl
->nregs
= hard_regno_nregs
[best_reg
][rl
->mode
];
1953 rl
->regno
= best_reg
;
1955 EXECUTE_IF_SET_IN_REG_SET
1956 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1958 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1961 EXECUTE_IF_SET_IN_REG_SET
1962 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1964 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1967 for (i
= 0; i
< rl
->nregs
; i
++)
1969 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1970 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1971 gcc_assert (hard_regno_to_pseudo_regno
[best_reg
+ i
] == -1);
1972 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1977 /* Find more reload regs to satisfy the remaining need of an insn, which
1979 Do it by ascending class number, since otherwise a reg
1980 might be spilled for a big class and might fail to count
1981 for a smaller class even though it belongs to that class. */
1984 find_reload_regs (struct insn_chain
*chain
)
1988 /* In order to be certain of getting the registers we need,
1989 we must sort the reloads into order of increasing register class.
1990 Then our grabbing of reload registers will parallel the process
1991 that provided the reload registers. */
1992 for (i
= 0; i
< chain
->n_reloads
; i
++)
1994 /* Show whether this reload already has a hard reg. */
1995 if (chain
->rld
[i
].reg_rtx
)
1997 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
1998 chain
->rld
[i
].regno
= regno
;
2000 = hard_regno_nregs
[regno
][GET_MODE (chain
->rld
[i
].reg_rtx
)];
2003 chain
->rld
[i
].regno
= -1;
2004 reload_order
[i
] = i
;
2007 n_reloads
= chain
->n_reloads
;
2008 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
2010 CLEAR_HARD_REG_SET (used_spill_regs_local
);
2013 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
2015 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
2017 /* Compute the order of preference for hard registers to spill. */
2019 order_regs_for_reload (chain
);
2021 for (i
= 0; i
< n_reloads
; i
++)
2023 int r
= reload_order
[i
];
2025 /* Ignore reloads that got marked inoperative. */
2026 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
2027 && ! rld
[r
].optional
2028 && rld
[r
].regno
== -1)
2029 if (! find_reg (chain
, i
))
2032 fprintf (dump_file
, "reload failure for reload %d\n", r
);
2033 spill_failure (chain
->insn
, rld
[r
].rclass
);
2039 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
2040 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
2042 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
2046 select_reload_regs (void)
2048 struct insn_chain
*chain
;
2050 /* Try to satisfy the needs for each insn. */
2051 for (chain
= insns_need_reload
; chain
!= 0;
2052 chain
= chain
->next_need_reload
)
2053 find_reload_regs (chain
);
2056 /* Delete all insns that were inserted by emit_caller_save_insns during
2059 delete_caller_save_insns (void)
2061 struct insn_chain
*c
= reload_insn_chain
;
2065 while (c
!= 0 && c
->is_caller_save_insn
)
2067 struct insn_chain
*next
= c
->next
;
2070 if (c
== reload_insn_chain
)
2071 reload_insn_chain
= next
;
2075 next
->prev
= c
->prev
;
2077 c
->prev
->next
= next
;
2078 c
->next
= unused_insn_chains
;
2079 unused_insn_chains
= c
;
2087 /* Handle the failure to find a register to spill.
2088 INSN should be one of the insns which needed this particular spill reg. */
2091 spill_failure (rtx insn
, enum reg_class rclass
)
2093 if (asm_noperands (PATTERN (insn
)) >= 0)
2094 error_for_asm (insn
, "can't find a register in class %qs while "
2095 "reloading %<asm%>",
2096 reg_class_names
[rclass
]);
2099 error ("unable to find a register to spill in class %qs",
2100 reg_class_names
[rclass
]);
2104 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
2105 debug_reload_to_stream (dump_file
);
2107 fatal_insn ("this is the insn:", insn
);
2111 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2112 data that is dead in INSN. */
2115 delete_dead_insn (rtx insn
)
2117 rtx prev
= prev_real_insn (insn
);
2120 /* If the previous insn sets a register that dies in our insn, delete it
2122 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
2123 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
2124 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2125 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2126 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2127 delete_dead_insn (prev
);
2129 SET_INSN_DELETED (insn
);
2132 /* Modify the home of pseudo-reg I.
2133 The new home is present in reg_renumber[I].
2135 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2136 or it may be -1, meaning there is none or it is not relevant.
2137 This is used so that all pseudos spilled from a given hard reg
2138 can share one stack slot. */
2141 alter_reg (int i
, int from_reg
, bool dont_share_p
)
2143 /* When outputting an inline function, this can happen
2144 for a reg that isn't actually used. */
2145 if (regno_reg_rtx
[i
] == 0)
2148 /* If the reg got changed to a MEM at rtl-generation time,
2150 if (!REG_P (regno_reg_rtx
[i
]))
2153 /* Modify the reg-rtx to contain the new hard reg
2154 number or else to contain its pseudo reg number. */
2155 SET_REGNO (regno_reg_rtx
[i
],
2156 reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
);
2158 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2159 allocate a stack slot for it. */
2161 if (reg_renumber
[i
] < 0
2162 && REG_N_REFS (i
) > 0
2163 && reg_equiv_constant
[i
] == 0
2164 && (reg_equiv_invariant
[i
] == 0 || reg_equiv_init
[i
] == 0)
2165 && reg_equiv_memory_loc
[i
] == 0)
2168 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2169 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2170 unsigned int inherent_align
= GET_MODE_ALIGNMENT (mode
);
2171 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2172 unsigned int min_align
= reg_max_ref_width
[i
] * BITS_PER_UNIT
;
2175 something_was_spilled
= true;
2177 if (ira_conflicts_p
)
2179 /* Mark the spill for IRA. */
2180 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
2182 x
= ira_reuse_stack_slot (i
, inherent_size
, total_size
);
2188 /* Each pseudo reg has an inherent size which comes from its own mode,
2189 and a total size which provides room for paradoxical subregs
2190 which refer to the pseudo reg in wider modes.
2192 We can use a slot already allocated if it provides both
2193 enough inherent space and enough total space.
2194 Otherwise, we allocate a new slot, making sure that it has no less
2195 inherent space, and no less total space, then the previous slot. */
2196 else if (from_reg
== -1 || (!dont_share_p
&& ira_conflicts_p
))
2200 /* No known place to spill from => no slot to reuse. */
2201 x
= assign_stack_local (mode
, total_size
,
2202 min_align
> inherent_align
2203 || total_size
> inherent_size
? -1 : 0);
2207 /* Cancel the big-endian correction done in assign_stack_local.
2208 Get the address of the beginning of the slot. This is so we
2209 can do a big-endian correction unconditionally below. */
2210 if (BYTES_BIG_ENDIAN
)
2212 adjust
= inherent_size
- total_size
;
2215 = adjust_address_nv (x
, mode_for_size (total_size
2221 if (! dont_share_p
&& ira_conflicts_p
)
2222 /* Inform IRA about allocation a new stack slot. */
2223 ira_mark_new_stack_slot (stack_slot
, i
, total_size
);
2226 /* Reuse a stack slot if possible. */
2227 else if (spill_stack_slot
[from_reg
] != 0
2228 && spill_stack_slot_width
[from_reg
] >= total_size
2229 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2231 && MEM_ALIGN (spill_stack_slot
[from_reg
]) >= min_align
)
2232 x
= spill_stack_slot
[from_reg
];
2234 /* Allocate a bigger slot. */
2237 /* Compute maximum size needed, both for inherent size
2238 and for total size. */
2241 if (spill_stack_slot
[from_reg
])
2243 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2245 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2246 if (spill_stack_slot_width
[from_reg
] > total_size
)
2247 total_size
= spill_stack_slot_width
[from_reg
];
2248 if (MEM_ALIGN (spill_stack_slot
[from_reg
]) > min_align
)
2249 min_align
= MEM_ALIGN (spill_stack_slot
[from_reg
]);
2252 /* Make a slot with that size. */
2253 x
= assign_stack_local (mode
, total_size
,
2254 min_align
> inherent_align
2255 || total_size
> inherent_size
? -1 : 0);
2258 /* Cancel the big-endian correction done in assign_stack_local.
2259 Get the address of the beginning of the slot. This is so we
2260 can do a big-endian correction unconditionally below. */
2261 if (BYTES_BIG_ENDIAN
)
2263 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2266 = adjust_address_nv (x
, mode_for_size (total_size
2272 spill_stack_slot
[from_reg
] = stack_slot
;
2273 spill_stack_slot_width
[from_reg
] = total_size
;
2276 /* On a big endian machine, the "address" of the slot
2277 is the address of the low part that fits its inherent mode. */
2278 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2279 adjust
+= (total_size
- inherent_size
);
2281 /* If we have any adjustment to make, or if the stack slot is the
2282 wrong mode, make a new stack slot. */
2283 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2285 /* Set all of the memory attributes as appropriate for a spill. */
2286 set_mem_attrs_for_spill (x
);
2288 /* Save the stack slot for later. */
2289 reg_equiv_memory_loc
[i
] = x
;
2293 /* Mark the slots in regs_ever_live for the hard regs used by
2294 pseudo-reg number REGNO, accessed in MODE. */
2297 mark_home_live_1 (int regno
, enum machine_mode mode
)
2301 i
= reg_renumber
[regno
];
2304 lim
= end_hard_regno (mode
, i
);
2306 df_set_regs_ever_live(i
++, true);
2309 /* Mark the slots in regs_ever_live for the hard regs
2310 used by pseudo-reg number REGNO. */
2313 mark_home_live (int regno
)
2315 if (reg_renumber
[regno
] >= 0)
2316 mark_home_live_1 (regno
, PSEUDO_REGNO_MODE (regno
));
2319 /* This function handles the tracking of elimination offsets around branches.
2321 X is a piece of RTL being scanned.
2323 INSN is the insn that it came from, if any.
2325 INITIAL_P is nonzero if we are to set the offset to be the initial
2326 offset and zero if we are setting the offset of the label to be the
2330 set_label_offsets (rtx x
, rtx insn
, int initial_p
)
2332 enum rtx_code code
= GET_CODE (x
);
2335 struct elim_table
*p
;
2340 if (LABEL_REF_NONLOCAL_P (x
))
2345 /* ... fall through ... */
2348 /* If we know nothing about this label, set the desired offsets. Note
2349 that this sets the offset at a label to be the offset before a label
2350 if we don't know anything about the label. This is not correct for
2351 the label after a BARRIER, but is the best guess we can make. If
2352 we guessed wrong, we will suppress an elimination that might have
2353 been possible had we been able to guess correctly. */
2355 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2357 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2358 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2359 = (initial_p
? reg_eliminate
[i
].initial_offset
2360 : reg_eliminate
[i
].offset
);
2361 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2364 /* Otherwise, if this is the definition of a label and it is
2365 preceded by a BARRIER, set our offsets to the known offset of
2369 && (tem
= prev_nonnote_insn (insn
)) != 0
2371 set_offsets_for_label (insn
);
2373 /* If neither of the above cases is true, compare each offset
2374 with those previously recorded and suppress any eliminations
2375 where the offsets disagree. */
2377 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2378 if (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2379 != (initial_p
? reg_eliminate
[i
].initial_offset
2380 : reg_eliminate
[i
].offset
))
2381 reg_eliminate
[i
].can_eliminate
= 0;
2386 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2388 /* ... fall through ... */
2392 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2393 to indirectly and hence must have all eliminations at their
2395 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2396 if (REG_NOTE_KIND (tem
) == REG_LABEL_OPERAND
)
2397 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2403 /* Each of the labels in the parallel or address vector must be
2404 at their initial offsets. We want the first field for PARALLEL
2405 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2407 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2408 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2413 /* We only care about setting PC. If the source is not RETURN,
2414 IF_THEN_ELSE, or a label, disable any eliminations not at
2415 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2416 isn't one of those possibilities. For branches to a label,
2417 call ourselves recursively.
2419 Note that this can disable elimination unnecessarily when we have
2420 a non-local goto since it will look like a non-constant jump to
2421 someplace in the current function. This isn't a significant
2422 problem since such jumps will normally be when all elimination
2423 pairs are back to their initial offsets. */
2425 if (SET_DEST (x
) != pc_rtx
)
2428 switch (GET_CODE (SET_SRC (x
)))
2435 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2439 tem
= XEXP (SET_SRC (x
), 1);
2440 if (GET_CODE (tem
) == LABEL_REF
)
2441 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2442 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2445 tem
= XEXP (SET_SRC (x
), 2);
2446 if (GET_CODE (tem
) == LABEL_REF
)
2447 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2448 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2456 /* If we reach here, all eliminations must be at their initial
2457 offset because we are doing a jump to a variable address. */
2458 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2459 if (p
->offset
!= p
->initial_offset
)
2460 p
->can_eliminate
= 0;
2468 /* Called through for_each_rtx, this function examines every reg that occurs
2469 in PX and adjusts the costs for its elimination which are gathered by IRA.
2470 DATA is the insn in which PX occurs. We do not recurse into MEM
2474 note_reg_elim_costly (rtx
*px
, void *data
)
2476 rtx insn
= (rtx
)data
;
2483 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
2484 && reg_equiv_init
[REGNO (x
)]
2485 && reg_equiv_invariant
[REGNO (x
)])
2487 rtx t
= reg_equiv_invariant
[REGNO (x
)];
2488 rtx new_rtx
= eliminate_regs_1 (t
, Pmode
, insn
, true, true);
2489 int cost
= rtx_cost (new_rtx
, SET
, optimize_bb_for_speed_p (elim_bb
));
2490 int freq
= REG_FREQ_FROM_BB (elim_bb
);
2493 ira_adjust_equiv_reg_cost (REGNO (x
), -cost
* freq
);
2498 /* Scan X and replace any eliminable registers (such as fp) with a
2499 replacement (such as sp), plus an offset.
2501 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2502 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2503 MEM, we are allowed to replace a sum of a register and the constant zero
2504 with the register, which we cannot do outside a MEM. In addition, we need
2505 to record the fact that a register is referenced outside a MEM.
2507 If INSN is an insn, it is the insn containing X. If we replace a REG
2508 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2509 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2510 the REG is being modified.
2512 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2513 That's used when we eliminate in expressions stored in notes.
2514 This means, do not set ref_outside_mem even if the reference
2517 If FOR_COSTS is true, we are being called before reload in order to
2518 estimate the costs of keeping registers with an equivalence unallocated.
2520 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2521 replacements done assuming all offsets are at their initial values. If
2522 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2523 encounter, return the actual location so that find_reloads will do
2524 the proper thing. */
2527 eliminate_regs_1 (rtx x
, enum machine_mode mem_mode
, rtx insn
,
2528 bool may_use_invariant
, bool for_costs
)
2530 enum rtx_code code
= GET_CODE (x
);
2531 struct elim_table
*ep
;
2538 if (! current_function_decl
)
2561 /* First handle the case where we encounter a bare register that
2562 is eliminable. Replace it with a PLUS. */
2563 if (regno
< FIRST_PSEUDO_REGISTER
)
2565 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2567 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2568 return plus_constant (ep
->to_rtx
, ep
->previous_offset
);
2571 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2572 && reg_equiv_invariant
&& reg_equiv_invariant
[regno
])
2574 if (may_use_invariant
|| (insn
&& DEBUG_INSN_P (insn
)))
2575 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant
[regno
]),
2576 mem_mode
, insn
, true, for_costs
);
2577 /* There exists at least one use of REGNO that cannot be
2578 eliminated. Prevent the defining insn from being deleted. */
2579 reg_equiv_init
[regno
] = NULL_RTX
;
2581 alter_reg (regno
, -1, true);
2585 /* You might think handling MINUS in a manner similar to PLUS is a
2586 good idea. It is not. It has been tried multiple times and every
2587 time the change has had to have been reverted.
2589 Other parts of reload know a PLUS is special (gen_reload for example)
2590 and require special code to handle code a reloaded PLUS operand.
2592 Also consider backends where the flags register is clobbered by a
2593 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2594 lea instruction comes to mind). If we try to reload a MINUS, we
2595 may kill the flags register that was holding a useful value.
2597 So, please before trying to handle MINUS, consider reload as a
2598 whole instead of this little section as well as the backend issues. */
2600 /* If this is the sum of an eliminable register and a constant, rework
2602 if (REG_P (XEXP (x
, 0))
2603 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2604 && CONSTANT_P (XEXP (x
, 1)))
2606 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2608 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2610 /* The only time we want to replace a PLUS with a REG (this
2611 occurs when the constant operand of the PLUS is the negative
2612 of the offset) is when we are inside a MEM. We won't want
2613 to do so at other times because that would change the
2614 structure of the insn in a way that reload can't handle.
2615 We special-case the commonest situation in
2616 eliminate_regs_in_insn, so just replace a PLUS with a
2617 PLUS here, unless inside a MEM. */
2618 if (mem_mode
!= 0 && CONST_INT_P (XEXP (x
, 1))
2619 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2622 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2623 plus_constant (XEXP (x
, 1),
2624 ep
->previous_offset
));
2627 /* If the register is not eliminable, we are done since the other
2628 operand is a constant. */
2632 /* If this is part of an address, we want to bring any constant to the
2633 outermost PLUS. We will do this by doing register replacement in
2634 our operands and seeing if a constant shows up in one of them.
2636 Note that there is no risk of modifying the structure of the insn,
2637 since we only get called for its operands, thus we are either
2638 modifying the address inside a MEM, or something like an address
2639 operand of a load-address insn. */
2642 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2644 rtx new1
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2647 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2649 /* If one side is a PLUS and the other side is a pseudo that
2650 didn't get a hard register but has a reg_equiv_constant,
2651 we must replace the constant here since it may no longer
2652 be in the position of any operand. */
2653 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2654 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2655 && reg_renumber
[REGNO (new1
)] < 0
2656 && reg_equiv_constant
!= 0
2657 && reg_equiv_constant
[REGNO (new1
)] != 0)
2658 new1
= reg_equiv_constant
[REGNO (new1
)];
2659 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2660 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2661 && reg_renumber
[REGNO (new0
)] < 0
2662 && reg_equiv_constant
[REGNO (new0
)] != 0)
2663 new0
= reg_equiv_constant
[REGNO (new0
)];
2665 new_rtx
= form_sum (GET_MODE (x
), new0
, new1
);
2667 /* As above, if we are not inside a MEM we do not want to
2668 turn a PLUS into something else. We might try to do so here
2669 for an addition of 0 if we aren't optimizing. */
2670 if (! mem_mode
&& GET_CODE (new_rtx
) != PLUS
)
2671 return gen_rtx_PLUS (GET_MODE (x
), new_rtx
, const0_rtx
);
2679 /* If this is the product of an eliminable register and a
2680 constant, apply the distribute law and move the constant out
2681 so that we have (plus (mult ..) ..). This is needed in order
2682 to keep load-address insns valid. This case is pathological.
2683 We ignore the possibility of overflow here. */
2684 if (REG_P (XEXP (x
, 0))
2685 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2686 && CONST_INT_P (XEXP (x
, 1)))
2687 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2689 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2692 /* Refs inside notes or in DEBUG_INSNs don't count for
2694 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2695 || GET_CODE (insn
) == INSN_LIST
2696 || DEBUG_INSN_P (insn
))))
2697 ep
->ref_outside_mem
= 1;
2700 plus_constant (gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2701 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2704 /* ... fall through ... */
2708 /* See comments before PLUS about handling MINUS. */
2710 case DIV
: case UDIV
:
2711 case MOD
: case UMOD
:
2712 case AND
: case IOR
: case XOR
:
2713 case ROTATERT
: case ROTATE
:
2714 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2716 case GE
: case GT
: case GEU
: case GTU
:
2717 case LE
: case LT
: case LEU
: case LTU
:
2719 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2721 rtx new1
= XEXP (x
, 1)
2722 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, false,
2725 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2726 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2731 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2734 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2736 if (new_rtx
!= XEXP (x
, 0))
2738 /* If this is a REG_DEAD note, it is not valid anymore.
2739 Using the eliminated version could result in creating a
2740 REG_DEAD note for the stack or frame pointer. */
2741 if (REG_NOTE_KIND (x
) == REG_DEAD
)
2743 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2747 x
= alloc_reg_note (REG_NOTE_KIND (x
), new_rtx
, XEXP (x
, 1));
2751 /* ... fall through ... */
2754 /* Now do eliminations in the rest of the chain. If this was
2755 an EXPR_LIST, this might result in allocating more memory than is
2756 strictly needed, but it simplifies the code. */
2759 new_rtx
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2761 if (new_rtx
!= XEXP (x
, 1))
2763 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new_rtx
);
2771 /* We do not support elimination of a register that is modified.
2772 elimination_effects has already make sure that this does not
2778 /* We do not support elimination of a register that is modified.
2779 elimination_effects has already make sure that this does not
2780 happen. The only remaining case we need to consider here is
2781 that the increment value may be an eliminable register. */
2782 if (GET_CODE (XEXP (x
, 1)) == PLUS
2783 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2785 rtx new_rtx
= eliminate_regs_1 (XEXP (XEXP (x
, 1), 1), mem_mode
,
2786 insn
, true, for_costs
);
2788 if (new_rtx
!= XEXP (XEXP (x
, 1), 1))
2789 return gen_rtx_fmt_ee (code
, GET_MODE (x
), XEXP (x
, 0),
2790 gen_rtx_PLUS (GET_MODE (x
),
2791 XEXP (x
, 0), new_rtx
));
2795 case STRICT_LOW_PART
:
2797 case SIGN_EXTEND
: case ZERO_EXTEND
:
2798 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2799 case FLOAT
: case FIX
:
2800 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2809 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2811 if (new_rtx
!= XEXP (x
, 0))
2812 return gen_rtx_fmt_e (code
, GET_MODE (x
), new_rtx
);
2816 /* Similar to above processing, but preserve SUBREG_BYTE.
2817 Convert (subreg (mem)) to (mem) if not paradoxical.
2818 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2819 pseudo didn't get a hard reg, we must replace this with the
2820 eliminated version of the memory location because push_reload
2821 may do the replacement in certain circumstances. */
2822 if (REG_P (SUBREG_REG (x
))
2823 && (GET_MODE_SIZE (GET_MODE (x
))
2824 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2825 && reg_equiv_memory_loc
!= 0
2826 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2828 new_rtx
= SUBREG_REG (x
);
2831 new_rtx
= eliminate_regs_1 (SUBREG_REG (x
), mem_mode
, insn
, false,
2834 if (new_rtx
!= SUBREG_REG (x
))
2836 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2837 int new_size
= GET_MODE_SIZE (GET_MODE (new_rtx
));
2840 && ((x_size
< new_size
2841 #ifdef WORD_REGISTER_OPERATIONS
2842 /* On these machines, combine can create rtl of the form
2843 (set (subreg:m1 (reg:m2 R) 0) ...)
2844 where m1 < m2, and expects something interesting to
2845 happen to the entire word. Moreover, it will use the
2846 (reg:m2 R) later, expecting all bits to be preserved.
2847 So if the number of words is the same, preserve the
2848 subreg so that push_reload can see it. */
2849 && ! ((x_size
- 1) / UNITS_PER_WORD
2850 == (new_size
-1 ) / UNITS_PER_WORD
)
2853 || x_size
== new_size
)
2855 return adjust_address_nv (new_rtx
, GET_MODE (x
), SUBREG_BYTE (x
));
2857 return gen_rtx_SUBREG (GET_MODE (x
), new_rtx
, SUBREG_BYTE (x
));
2863 /* Our only special processing is to pass the mode of the MEM to our
2864 recursive call and copy the flags. While we are here, handle this
2865 case more efficiently. */
2867 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), GET_MODE (x
), insn
, true,
2870 && memory_address_p (GET_MODE (x
), XEXP (x
, 0))
2871 && !memory_address_p (GET_MODE (x
), new_rtx
))
2872 for_each_rtx (&XEXP (x
, 0), note_reg_elim_costly
, insn
);
2874 return replace_equiv_address_nv (x
, new_rtx
);
2877 /* Handle insn_list USE that a call to a pure function may generate. */
2878 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), VOIDmode
, insn
, false,
2880 if (new_rtx
!= XEXP (x
, 0))
2881 return gen_rtx_USE (GET_MODE (x
), new_rtx
);
2886 gcc_assert (insn
&& DEBUG_INSN_P (insn
));
2896 /* Process each of our operands recursively. If any have changed, make a
2898 fmt
= GET_RTX_FORMAT (code
);
2899 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2903 new_rtx
= eliminate_regs_1 (XEXP (x
, i
), mem_mode
, insn
, false,
2905 if (new_rtx
!= XEXP (x
, i
) && ! copied
)
2907 x
= shallow_copy_rtx (x
);
2910 XEXP (x
, i
) = new_rtx
;
2912 else if (*fmt
== 'E')
2915 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2917 new_rtx
= eliminate_regs_1 (XVECEXP (x
, i
, j
), mem_mode
, insn
, false,
2919 if (new_rtx
!= XVECEXP (x
, i
, j
) && ! copied_vec
)
2921 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2925 x
= shallow_copy_rtx (x
);
2928 XVEC (x
, i
) = new_v
;
2931 XVECEXP (x
, i
, j
) = new_rtx
;
2940 eliminate_regs (rtx x
, enum machine_mode mem_mode
, rtx insn
)
2942 return eliminate_regs_1 (x
, mem_mode
, insn
, false, false);
2945 /* Scan rtx X for modifications of elimination target registers. Update
2946 the table of eliminables to reflect the changed state. MEM_MODE is
2947 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2950 elimination_effects (rtx x
, enum machine_mode mem_mode
)
2952 enum rtx_code code
= GET_CODE (x
);
2953 struct elim_table
*ep
;
2978 /* First handle the case where we encounter a bare register that
2979 is eliminable. Replace it with a PLUS. */
2980 if (regno
< FIRST_PSEUDO_REGISTER
)
2982 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2984 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2987 ep
->ref_outside_mem
= 1;
2992 else if (reg_renumber
[regno
] < 0 && reg_equiv_constant
2993 && reg_equiv_constant
[regno
]
2994 && ! function_invariant_p (reg_equiv_constant
[regno
]))
2995 elimination_effects (reg_equiv_constant
[regno
], mem_mode
);
3004 /* If we modify the source of an elimination rule, disable it. */
3005 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3006 if (ep
->from_rtx
== XEXP (x
, 0))
3007 ep
->can_eliminate
= 0;
3009 /* If we modify the target of an elimination rule by adding a constant,
3010 update its offset. If we modify the target in any other way, we'll
3011 have to disable the rule as well. */
3012 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3013 if (ep
->to_rtx
== XEXP (x
, 0))
3015 int size
= GET_MODE_SIZE (mem_mode
);
3017 /* If more bytes than MEM_MODE are pushed, account for them. */
3018 #ifdef PUSH_ROUNDING
3019 if (ep
->to_rtx
== stack_pointer_rtx
)
3020 size
= PUSH_ROUNDING (size
);
3022 if (code
== PRE_DEC
|| code
== POST_DEC
)
3024 else if (code
== PRE_INC
|| code
== POST_INC
)
3026 else if (code
== PRE_MODIFY
|| code
== POST_MODIFY
)
3028 if (GET_CODE (XEXP (x
, 1)) == PLUS
3029 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
3030 && CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
3031 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
3033 ep
->can_eliminate
= 0;
3037 /* These two aren't unary operators. */
3038 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3041 /* Fall through to generic unary operation case. */
3042 case STRICT_LOW_PART
:
3044 case SIGN_EXTEND
: case ZERO_EXTEND
:
3045 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
3046 case FLOAT
: case FIX
:
3047 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
3056 elimination_effects (XEXP (x
, 0), mem_mode
);
3060 if (REG_P (SUBREG_REG (x
))
3061 && (GET_MODE_SIZE (GET_MODE (x
))
3062 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3063 && reg_equiv_memory_loc
!= 0
3064 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
3067 elimination_effects (SUBREG_REG (x
), mem_mode
);
3071 /* If using a register that is the source of an eliminate we still
3072 think can be performed, note it cannot be performed since we don't
3073 know how this register is used. */
3074 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3075 if (ep
->from_rtx
== XEXP (x
, 0))
3076 ep
->can_eliminate
= 0;
3078 elimination_effects (XEXP (x
, 0), mem_mode
);
3082 /* If clobbering a register that is the replacement register for an
3083 elimination we still think can be performed, note that it cannot
3084 be performed. Otherwise, we need not be concerned about it. */
3085 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3086 if (ep
->to_rtx
== XEXP (x
, 0))
3087 ep
->can_eliminate
= 0;
3089 elimination_effects (XEXP (x
, 0), mem_mode
);
3093 /* Check for setting a register that we know about. */
3094 if (REG_P (SET_DEST (x
)))
3096 /* See if this is setting the replacement register for an
3099 If DEST is the hard frame pointer, we do nothing because we
3100 assume that all assignments to the frame pointer are for
3101 non-local gotos and are being done at a time when they are valid
3102 and do not disturb anything else. Some machines want to
3103 eliminate a fake argument pointer (or even a fake frame pointer)
3104 with either the real frame or the stack pointer. Assignments to
3105 the hard frame pointer must not prevent this elimination. */
3107 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3109 if (ep
->to_rtx
== SET_DEST (x
)
3110 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3112 /* If it is being incremented, adjust the offset. Otherwise,
3113 this elimination can't be done. */
3114 rtx src
= SET_SRC (x
);
3116 if (GET_CODE (src
) == PLUS
3117 && XEXP (src
, 0) == SET_DEST (x
)
3118 && CONST_INT_P (XEXP (src
, 1)))
3119 ep
->offset
-= INTVAL (XEXP (src
, 1));
3121 ep
->can_eliminate
= 0;
3125 elimination_effects (SET_DEST (x
), VOIDmode
);
3126 elimination_effects (SET_SRC (x
), VOIDmode
);
3130 /* Our only special processing is to pass the mode of the MEM to our
3132 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
3139 fmt
= GET_RTX_FORMAT (code
);
3140 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3143 elimination_effects (XEXP (x
, i
), mem_mode
);
3144 else if (*fmt
== 'E')
3145 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3146 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
3150 /* Descend through rtx X and verify that no references to eliminable registers
3151 remain. If any do remain, mark the involved register as not
3155 check_eliminable_occurrences (rtx x
)
3164 code
= GET_CODE (x
);
3166 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
3168 struct elim_table
*ep
;
3170 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3171 if (ep
->from_rtx
== x
)
3172 ep
->can_eliminate
= 0;
3176 fmt
= GET_RTX_FORMAT (code
);
3177 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3180 check_eliminable_occurrences (XEXP (x
, i
));
3181 else if (*fmt
== 'E')
3184 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3185 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
3190 /* Scan INSN and eliminate all eliminable registers in it.
3192 If REPLACE is nonzero, do the replacement destructively. Also
3193 delete the insn as dead it if it is setting an eliminable register.
3195 If REPLACE is zero, do all our allocations in reload_obstack.
3197 If no eliminations were done and this insn doesn't require any elimination
3198 processing (these are not identical conditions: it might be updating sp,
3199 but not referencing fp; this needs to be seen during reload_as_needed so
3200 that the offset between fp and sp can be taken into consideration), zero
3201 is returned. Otherwise, 1 is returned. */
3204 eliminate_regs_in_insn (rtx insn
, int replace
)
3206 int icode
= recog_memoized (insn
);
3207 rtx old_body
= PATTERN (insn
);
3208 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3209 rtx old_set
= single_set (insn
);
3213 rtx substed_operand
[MAX_RECOG_OPERANDS
];
3214 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3215 struct elim_table
*ep
;
3216 rtx plus_src
, plus_cst_src
;
3218 if (! insn_is_asm
&& icode
< 0)
3220 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
3221 || GET_CODE (PATTERN (insn
)) == CLOBBER
3222 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
3223 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
3224 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
3225 || DEBUG_INSN_P (insn
));
3226 if (DEBUG_INSN_P (insn
))
3227 INSN_VAR_LOCATION_LOC (insn
)
3228 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn
), VOIDmode
, insn
);
3232 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3233 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3235 /* Check for setting an eliminable register. */
3236 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3237 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3239 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
3240 /* If this is setting the frame pointer register to the
3241 hardware frame pointer register and this is an elimination
3242 that will be done (tested above), this insn is really
3243 adjusting the frame pointer downward to compensate for
3244 the adjustment done before a nonlocal goto. */
3245 if (ep
->from
== FRAME_POINTER_REGNUM
3246 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
3248 rtx base
= SET_SRC (old_set
);
3249 rtx base_insn
= insn
;
3250 HOST_WIDE_INT offset
= 0;
3252 while (base
!= ep
->to_rtx
)
3254 rtx prev_insn
, prev_set
;
3256 if (GET_CODE (base
) == PLUS
3257 && CONST_INT_P (XEXP (base
, 1)))
3259 offset
+= INTVAL (XEXP (base
, 1));
3260 base
= XEXP (base
, 0);
3262 else if ((prev_insn
= prev_nonnote_insn (base_insn
)) != 0
3263 && (prev_set
= single_set (prev_insn
)) != 0
3264 && rtx_equal_p (SET_DEST (prev_set
), base
))
3266 base
= SET_SRC (prev_set
);
3267 base_insn
= prev_insn
;
3273 if (base
== ep
->to_rtx
)
3276 = plus_constant (ep
->to_rtx
, offset
- ep
->offset
);
3278 new_body
= old_body
;
3281 new_body
= copy_insn (old_body
);
3282 if (REG_NOTES (insn
))
3283 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3285 PATTERN (insn
) = new_body
;
3286 old_set
= single_set (insn
);
3288 /* First see if this insn remains valid when we
3289 make the change. If not, keep the INSN_CODE
3290 the same and let reload fit it up. */
3291 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3292 validate_change (insn
, &SET_DEST (old_set
),
3294 if (! apply_change_group ())
3296 SET_SRC (old_set
) = src
;
3297 SET_DEST (old_set
) = ep
->to_rtx
;
3306 /* In this case this insn isn't serving a useful purpose. We
3307 will delete it in reload_as_needed once we know that this
3308 elimination is, in fact, being done.
3310 If REPLACE isn't set, we can't delete this insn, but needn't
3311 process it since it won't be used unless something changes. */
3314 delete_dead_insn (insn
);
3322 /* We allow one special case which happens to work on all machines we
3323 currently support: a single set with the source or a REG_EQUAL
3324 note being a PLUS of an eliminable register and a constant. */
3325 plus_src
= plus_cst_src
= 0;
3326 if (old_set
&& REG_P (SET_DEST (old_set
)))
3328 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3329 plus_src
= SET_SRC (old_set
);
3330 /* First see if the source is of the form (plus (...) CST). */
3332 && CONST_INT_P (XEXP (plus_src
, 1)))
3333 plus_cst_src
= plus_src
;
3334 else if (REG_P (SET_SRC (old_set
))
3337 /* Otherwise, see if we have a REG_EQUAL note of the form
3338 (plus (...) CST). */
3340 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3342 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3343 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3344 && GET_CODE (XEXP (links
, 0)) == PLUS
3345 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3347 plus_cst_src
= XEXP (links
, 0);
3353 /* Check that the first operand of the PLUS is a hard reg or
3354 the lowpart subreg of one. */
3357 rtx reg
= XEXP (plus_cst_src
, 0);
3358 if (GET_CODE (reg
) == SUBREG
&& subreg_lowpart_p (reg
))
3359 reg
= SUBREG_REG (reg
);
3361 if (!REG_P (reg
) || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
3367 rtx reg
= XEXP (plus_cst_src
, 0);
3368 HOST_WIDE_INT offset
= INTVAL (XEXP (plus_cst_src
, 1));
3370 if (GET_CODE (reg
) == SUBREG
)
3371 reg
= SUBREG_REG (reg
);
3373 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3374 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3376 rtx to_rtx
= ep
->to_rtx
;
3377 offset
+= ep
->offset
;
3378 offset
= trunc_int_for_mode (offset
, GET_MODE (plus_cst_src
));
3380 if (GET_CODE (XEXP (plus_cst_src
, 0)) == SUBREG
)
3381 to_rtx
= gen_lowpart (GET_MODE (XEXP (plus_cst_src
, 0)),
3383 /* If we have a nonzero offset, and the source is already
3384 a simple REG, the following transformation would
3385 increase the cost of the insn by replacing a simple REG
3386 with (plus (reg sp) CST). So try only when we already
3387 had a PLUS before. */
3388 if (offset
== 0 || plus_src
)
3390 rtx new_src
= plus_constant (to_rtx
, offset
);
3392 new_body
= old_body
;
3395 new_body
= copy_insn (old_body
);
3396 if (REG_NOTES (insn
))
3397 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3399 PATTERN (insn
) = new_body
;
3400 old_set
= single_set (insn
);
3402 /* First see if this insn remains valid when we make the
3403 change. If not, try to replace the whole pattern with
3404 a simple set (this may help if the original insn was a
3405 PARALLEL that was only recognized as single_set due to
3406 REG_UNUSED notes). If this isn't valid either, keep
3407 the INSN_CODE the same and let reload fix it up. */
3408 if (!validate_change (insn
, &SET_SRC (old_set
), new_src
, 0))
3410 rtx new_pat
= gen_rtx_SET (VOIDmode
,
3411 SET_DEST (old_set
), new_src
);
3413 if (!validate_change (insn
, &PATTERN (insn
), new_pat
, 0))
3414 SET_SRC (old_set
) = new_src
;
3421 /* This can't have an effect on elimination offsets, so skip right
3427 /* Determine the effects of this insn on elimination offsets. */
3428 elimination_effects (old_body
, VOIDmode
);
3430 /* Eliminate all eliminable registers occurring in operands that
3431 can be handled by reload. */
3432 extract_insn (insn
);
3433 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3435 orig_operand
[i
] = recog_data
.operand
[i
];
3436 substed_operand
[i
] = recog_data
.operand
[i
];
3438 /* For an asm statement, every operand is eliminable. */
3439 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3441 bool is_set_src
, in_plus
;
3443 /* Check for setting a register that we know about. */
3444 if (recog_data
.operand_type
[i
] != OP_IN
3445 && REG_P (orig_operand
[i
]))
3447 /* If we are assigning to a register that can be eliminated, it
3448 must be as part of a PARALLEL, since the code above handles
3449 single SETs. We must indicate that we can no longer
3450 eliminate this reg. */
3451 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3453 if (ep
->from_rtx
== orig_operand
[i
])
3454 ep
->can_eliminate
= 0;
3457 /* Companion to the above plus substitution, we can allow
3458 invariants as the source of a plain move. */
3461 && recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3465 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3466 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3470 = eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3471 replace
? insn
: NULL_RTX
,
3472 is_set_src
|| in_plus
, false);
3473 if (substed_operand
[i
] != orig_operand
[i
])
3475 /* Terminate the search in check_eliminable_occurrences at
3477 *recog_data
.operand_loc
[i
] = 0;
3479 /* If an output operand changed from a REG to a MEM and INSN is an
3480 insn, write a CLOBBER insn. */
3481 if (recog_data
.operand_type
[i
] != OP_IN
3482 && REG_P (orig_operand
[i
])
3483 && MEM_P (substed_operand
[i
])
3485 emit_insn_after (gen_clobber (orig_operand
[i
]), insn
);
3489 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3490 *recog_data
.dup_loc
[i
]
3491 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3493 /* If any eliminable remain, they aren't eliminable anymore. */
3494 check_eliminable_occurrences (old_body
);
3496 /* Substitute the operands; the new values are in the substed_operand
3498 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3499 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3500 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3501 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3503 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3504 re-recognize the insn. We do this in case we had a simple addition
3505 but now can do this as a load-address. This saves an insn in this
3507 If re-recognition fails, the old insn code number will still be used,
3508 and some register operands may have changed into PLUS expressions.
3509 These will be handled by find_reloads by loading them into a register
3514 /* If we aren't replacing things permanently and we changed something,
3515 make another copy to ensure that all the RTL is new. Otherwise
3516 things can go wrong if find_reload swaps commutative operands
3517 and one is inside RTL that has been copied while the other is not. */
3518 new_body
= old_body
;
3521 new_body
= copy_insn (old_body
);
3522 if (REG_NOTES (insn
))
3523 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3525 PATTERN (insn
) = new_body
;
3527 /* If we had a move insn but now we don't, rerecognize it. This will
3528 cause spurious re-recognition if the old move had a PARALLEL since
3529 the new one still will, but we can't call single_set without
3530 having put NEW_BODY into the insn and the re-recognition won't
3531 hurt in this rare case. */
3532 /* ??? Why this huge if statement - why don't we just rerecognize the
3536 && ((REG_P (SET_SRC (old_set
))
3537 && (GET_CODE (new_body
) != SET
3538 || !REG_P (SET_SRC (new_body
))))
3539 /* If this was a load from or store to memory, compare
3540 the MEM in recog_data.operand to the one in the insn.
3541 If they are not equal, then rerecognize the insn. */
3543 && ((MEM_P (SET_SRC (old_set
))
3544 && SET_SRC (old_set
) != recog_data
.operand
[1])
3545 || (MEM_P (SET_DEST (old_set
))
3546 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3547 /* If this was an add insn before, rerecognize. */
3548 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3550 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3552 INSN_CODE (insn
) = new_icode
;
3556 /* Restore the old body. If there were any changes to it, we made a copy
3557 of it while the changes were still in place, so we'll correctly return
3558 a modified insn below. */
3561 /* Restore the old body. */
3562 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3563 /* Restoring a top-level match_parallel would clobber the new_body
3564 we installed in the insn. */
3565 if (recog_data
.operand_loc
[i
] != &PATTERN (insn
))
3566 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3567 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3568 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3571 /* Update all elimination pairs to reflect the status after the current
3572 insn. The changes we make were determined by the earlier call to
3573 elimination_effects.
3575 We also detect cases where register elimination cannot be done,
3576 namely, if a register would be both changed and referenced outside a MEM
3577 in the resulting insn since such an insn is often undefined and, even if
3578 not, we cannot know what meaning will be given to it. Note that it is
3579 valid to have a register used in an address in an insn that changes it
3580 (presumably with a pre- or post-increment or decrement).
3582 If anything changes, return nonzero. */
3584 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3586 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3587 ep
->can_eliminate
= 0;
3589 ep
->ref_outside_mem
= 0;
3591 if (ep
->previous_offset
!= ep
->offset
)
3596 /* If we changed something, perform elimination in REG_NOTES. This is
3597 needed even when REPLACE is zero because a REG_DEAD note might refer
3598 to a register that we eliminate and could cause a different number
3599 of spill registers to be needed in the final reload pass than in
3601 if (val
&& REG_NOTES (insn
) != 0)
3603 = eliminate_regs_1 (REG_NOTES (insn
), VOIDmode
, REG_NOTES (insn
), true,
3609 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3610 register allocator. INSN is the instruction we need to examine, we perform
3611 eliminations in its operands and record cases where eliminating a reg with
3612 an invariant equivalence would add extra cost. */
3615 elimination_costs_in_insn (rtx insn
)
3617 int icode
= recog_memoized (insn
);
3618 rtx old_body
= PATTERN (insn
);
3619 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3620 rtx old_set
= single_set (insn
);
3622 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3623 rtx orig_dup
[MAX_RECOG_OPERANDS
];
3624 struct elim_table
*ep
;
3625 rtx plus_src
, plus_cst_src
;
3628 if (! insn_is_asm
&& icode
< 0)
3630 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
3631 || GET_CODE (PATTERN (insn
)) == CLOBBER
3632 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
3633 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
3634 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
3635 || DEBUG_INSN_P (insn
));
3639 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3640 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3642 /* Check for setting an eliminable register. */
3643 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3644 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3648 /* We allow one special case which happens to work on all machines we
3649 currently support: a single set with the source or a REG_EQUAL
3650 note being a PLUS of an eliminable register and a constant. */
3651 plus_src
= plus_cst_src
= 0;
3653 if (old_set
&& REG_P (SET_DEST (old_set
)))
3656 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3657 plus_src
= SET_SRC (old_set
);
3658 /* First see if the source is of the form (plus (...) CST). */
3660 && CONST_INT_P (XEXP (plus_src
, 1)))
3661 plus_cst_src
= plus_src
;
3662 else if (REG_P (SET_SRC (old_set
))
3665 /* Otherwise, see if we have a REG_EQUAL note of the form
3666 (plus (...) CST). */
3668 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3670 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3671 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3672 && GET_CODE (XEXP (links
, 0)) == PLUS
3673 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3675 plus_cst_src
= XEXP (links
, 0);
3682 /* Determine the effects of this insn on elimination offsets. */
3683 elimination_effects (old_body
, VOIDmode
);
3685 /* Eliminate all eliminable registers occurring in operands that
3686 can be handled by reload. */
3687 extract_insn (insn
);
3688 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3689 orig_dup
[i
] = *recog_data
.dup_loc
[i
];
3691 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3693 orig_operand
[i
] = recog_data
.operand
[i
];
3695 /* For an asm statement, every operand is eliminable. */
3696 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3698 bool is_set_src
, in_plus
;
3700 /* Check for setting a register that we know about. */
3701 if (recog_data
.operand_type
[i
] != OP_IN
3702 && REG_P (orig_operand
[i
]))
3704 /* If we are assigning to a register that can be eliminated, it
3705 must be as part of a PARALLEL, since the code above handles
3706 single SETs. We must indicate that we can no longer
3707 eliminate this reg. */
3708 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3710 if (ep
->from_rtx
== orig_operand
[i
])
3711 ep
->can_eliminate
= 0;
3714 /* Companion to the above plus substitution, we can allow
3715 invariants as the source of a plain move. */
3717 if (old_set
&& recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3719 if (is_set_src
&& !sets_reg_p
)
3720 note_reg_elim_costly (&SET_SRC (old_set
), insn
);
3722 if (plus_src
&& sets_reg_p
3723 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3724 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3727 eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3729 is_set_src
|| in_plus
, true);
3730 /* Terminate the search in check_eliminable_occurrences at
3732 *recog_data
.operand_loc
[i
] = 0;
3736 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3737 *recog_data
.dup_loc
[i
]
3738 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3740 /* If any eliminable remain, they aren't eliminable anymore. */
3741 check_eliminable_occurrences (old_body
);
3743 /* Restore the old body. */
3744 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3745 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3746 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3747 *recog_data
.dup_loc
[i
] = orig_dup
[i
];
3749 /* Update all elimination pairs to reflect the status after the current
3750 insn. The changes we make were determined by the earlier call to
3751 elimination_effects. */
3753 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3755 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3756 ep
->can_eliminate
= 0;
3758 ep
->ref_outside_mem
= 0;
3764 /* Loop through all elimination pairs.
3765 Recalculate the number not at initial offset.
3767 Compute the maximum offset (minimum offset if the stack does not
3768 grow downward) for each elimination pair. */
3771 update_eliminable_offsets (void)
3773 struct elim_table
*ep
;
3775 num_not_at_initial_offset
= 0;
3776 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3778 ep
->previous_offset
= ep
->offset
;
3779 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3780 num_not_at_initial_offset
++;
3784 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3785 replacement we currently believe is valid, mark it as not eliminable if X
3786 modifies DEST in any way other than by adding a constant integer to it.
3788 If DEST is the frame pointer, we do nothing because we assume that
3789 all assignments to the hard frame pointer are nonlocal gotos and are being
3790 done at a time when they are valid and do not disturb anything else.
3791 Some machines want to eliminate a fake argument pointer with either the
3792 frame or stack pointer. Assignments to the hard frame pointer must not
3793 prevent this elimination.
3795 Called via note_stores from reload before starting its passes to scan
3796 the insns of the function. */
3799 mark_not_eliminable (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
3803 /* A SUBREG of a hard register here is just changing its mode. We should
3804 not see a SUBREG of an eliminable hard register, but check just in
3806 if (GET_CODE (dest
) == SUBREG
)
3807 dest
= SUBREG_REG (dest
);
3809 if (dest
== hard_frame_pointer_rtx
)
3812 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3813 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3814 && (GET_CODE (x
) != SET
3815 || GET_CODE (SET_SRC (x
)) != PLUS
3816 || XEXP (SET_SRC (x
), 0) != dest
3817 || !CONST_INT_P (XEXP (SET_SRC (x
), 1))))
3819 reg_eliminate
[i
].can_eliminate_previous
3820 = reg_eliminate
[i
].can_eliminate
= 0;
3825 /* Verify that the initial elimination offsets did not change since the
3826 last call to set_initial_elim_offsets. This is used to catch cases
3827 where something illegal happened during reload_as_needed that could
3828 cause incorrect code to be generated if we did not check for it. */
3831 verify_initial_elim_offsets (void)
3835 if (!num_eliminable
)
3838 #ifdef ELIMINABLE_REGS
3840 struct elim_table
*ep
;
3842 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3844 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3845 if (t
!= ep
->initial_offset
)
3850 INITIAL_FRAME_POINTER_OFFSET (t
);
3851 if (t
!= reg_eliminate
[0].initial_offset
)
3858 /* Reset all offsets on eliminable registers to their initial values. */
3861 set_initial_elim_offsets (void)
3863 struct elim_table
*ep
= reg_eliminate
;
3865 #ifdef ELIMINABLE_REGS
3866 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3868 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3869 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3872 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3873 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3876 num_not_at_initial_offset
= 0;
3879 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3882 set_initial_eh_label_offset (rtx label
)
3884 set_label_offsets (label
, NULL_RTX
, 1);
3887 /* Initialize the known label offsets.
3888 Set a known offset for each forced label to be at the initial offset
3889 of each elimination. We do this because we assume that all
3890 computed jumps occur from a location where each elimination is
3891 at its initial offset.
3892 For all other labels, show that we don't know the offsets. */
3895 set_initial_label_offsets (void)
3898 memset (offsets_known_at
, 0, num_labels
);
3900 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3902 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3904 for_each_eh_label (set_initial_eh_label_offset
);
3907 /* Set all elimination offsets to the known values for the code label given
3911 set_offsets_for_label (rtx insn
)
3914 int label_nr
= CODE_LABEL_NUMBER (insn
);
3915 struct elim_table
*ep
;
3917 num_not_at_initial_offset
= 0;
3918 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3920 ep
->offset
= ep
->previous_offset
3921 = offsets_at
[label_nr
- first_label_num
][i
];
3922 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3923 num_not_at_initial_offset
++;
3927 /* See if anything that happened changes which eliminations are valid.
3928 For example, on the SPARC, whether or not the frame pointer can
3929 be eliminated can depend on what registers have been used. We need
3930 not check some conditions again (such as flag_omit_frame_pointer)
3931 since they can't have changed. */
3934 update_eliminables (HARD_REG_SET
*pset
)
3936 int previous_frame_pointer_needed
= frame_pointer_needed
;
3937 struct elim_table
*ep
;
3939 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3940 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
3941 && targetm
.frame_pointer_required ())
3942 #ifdef ELIMINABLE_REGS
3943 || ! targetm
.can_eliminate (ep
->from
, ep
->to
)
3946 ep
->can_eliminate
= 0;
3948 /* Look for the case where we have discovered that we can't replace
3949 register A with register B and that means that we will now be
3950 trying to replace register A with register C. This means we can
3951 no longer replace register C with register B and we need to disable
3952 such an elimination, if it exists. This occurs often with A == ap,
3953 B == sp, and C == fp. */
3955 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3957 struct elim_table
*op
;
3960 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3962 /* Find the current elimination for ep->from, if there is a
3964 for (op
= reg_eliminate
;
3965 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3966 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3972 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3974 for (op
= reg_eliminate
;
3975 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3976 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3977 op
->can_eliminate
= 0;
3981 /* See if any registers that we thought we could eliminate the previous
3982 time are no longer eliminable. If so, something has changed and we
3983 must spill the register. Also, recompute the number of eliminable
3984 registers and see if the frame pointer is needed; it is if there is
3985 no elimination of the frame pointer that we can perform. */
3987 frame_pointer_needed
= 1;
3988 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3990 if (ep
->can_eliminate
3991 && ep
->from
== FRAME_POINTER_REGNUM
3992 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
3993 && (! SUPPORTS_STACK_ALIGNMENT
3994 || ! crtl
->stack_realign_needed
))
3995 frame_pointer_needed
= 0;
3997 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3999 ep
->can_eliminate_previous
= 0;
4000 SET_HARD_REG_BIT (*pset
, ep
->from
);
4005 /* If we didn't need a frame pointer last time, but we do now, spill
4006 the hard frame pointer. */
4007 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
4008 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
4011 /* Return true if X is used as the target register of an elimination. */
4014 elimination_target_reg_p (rtx x
)
4016 struct elim_table
*ep
;
4018 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4019 if (ep
->to_rtx
== x
&& ep
->can_eliminate
)
4025 /* Initialize the table of registers to eliminate.
4026 Pre-condition: global flag frame_pointer_needed has been set before
4027 calling this function. */
4030 init_elim_table (void)
4032 struct elim_table
*ep
;
4033 #ifdef ELIMINABLE_REGS
4034 const struct elim_table_1
*ep1
;
4038 reg_eliminate
= XCNEWVEC (struct elim_table
, NUM_ELIMINABLE_REGS
);
4042 #ifdef ELIMINABLE_REGS
4043 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
4044 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
4046 ep
->from
= ep1
->from
;
4048 ep
->can_eliminate
= ep
->can_eliminate_previous
4049 = (targetm
.can_eliminate (ep
->from
, ep
->to
)
4050 && ! (ep
->to
== STACK_POINTER_REGNUM
4051 && frame_pointer_needed
4052 && (! SUPPORTS_STACK_ALIGNMENT
4053 || ! stack_realign_fp
)));
4056 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
4057 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
4058 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
4059 = ! frame_pointer_needed
;
4062 /* Count the number of eliminable registers and build the FROM and TO
4063 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4064 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4065 We depend on this. */
4066 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4068 num_eliminable
+= ep
->can_eliminate
;
4069 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
4070 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
4074 /* Find all the pseudo registers that didn't get hard regs
4075 but do have known equivalent constants or memory slots.
4076 These include parameters (known equivalent to parameter slots)
4077 and cse'd or loop-moved constant memory addresses.
4079 Record constant equivalents in reg_equiv_constant
4080 so they will be substituted by find_reloads.
4081 Record memory equivalents in reg_mem_equiv so they can
4082 be substituted eventually by altering the REG-rtx's. */
4085 init_eliminable_invariants (rtx first
, bool do_subregs
)
4090 reg_equiv_constant
= XCNEWVEC (rtx
, max_regno
);
4091 reg_equiv_invariant
= XCNEWVEC (rtx
, max_regno
);
4092 reg_equiv_mem
= XCNEWVEC (rtx
, max_regno
);
4093 reg_equiv_alt_mem_list
= XCNEWVEC (rtx
, max_regno
);
4094 reg_equiv_address
= XCNEWVEC (rtx
, max_regno
);
4096 reg_max_ref_width
= XCNEWVEC (unsigned int, max_regno
);
4098 reg_max_ref_width
= NULL
;
4100 num_eliminable_invariants
= 0;
4102 first_label_num
= get_first_label_num ();
4103 num_labels
= max_label_num () - first_label_num
;
4105 /* Allocate the tables used to store offset information at labels. */
4106 offsets_known_at
= XNEWVEC (char, num_labels
);
4107 offsets_at
= (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS
]) xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (HOST_WIDE_INT
));
4109 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4110 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4111 find largest such for each pseudo. FIRST is the head of the insn
4114 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4116 rtx set
= single_set (insn
);
4118 /* We may introduce USEs that we want to remove at the end, so
4119 we'll mark them with QImode. Make sure there are no
4120 previously-marked insns left by say regmove. */
4121 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
4122 && GET_MODE (insn
) != VOIDmode
)
4123 PUT_MODE (insn
, VOIDmode
);
4125 if (do_subregs
&& NONDEBUG_INSN_P (insn
))
4126 scan_paradoxical_subregs (PATTERN (insn
));
4128 if (set
!= 0 && REG_P (SET_DEST (set
)))
4130 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
4136 i
= REGNO (SET_DEST (set
));
4139 if (i
<= LAST_VIRTUAL_REGISTER
)
4142 /* If flag_pic and we have constant, verify it's legitimate. */
4144 || !flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
))
4146 /* It can happen that a REG_EQUIV note contains a MEM
4147 that is not a legitimate memory operand. As later
4148 stages of reload assume that all addresses found
4149 in the reg_equiv_* arrays were originally legitimate,
4150 we ignore such REG_EQUIV notes. */
4151 if (memory_operand (x
, VOIDmode
))
4153 /* Always unshare the equivalence, so we can
4154 substitute into this insn without touching the
4156 reg_equiv_memory_loc
[i
] = copy_rtx (x
);
4158 else if (function_invariant_p (x
))
4160 if (GET_CODE (x
) == PLUS
)
4162 /* This is PLUS of frame pointer and a constant,
4163 and might be shared. Unshare it. */
4164 reg_equiv_invariant
[i
] = copy_rtx (x
);
4165 num_eliminable_invariants
++;
4167 else if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
4169 reg_equiv_invariant
[i
] = x
;
4170 num_eliminable_invariants
++;
4172 else if (LEGITIMATE_CONSTANT_P (x
))
4173 reg_equiv_constant
[i
] = x
;
4176 reg_equiv_memory_loc
[i
]
4177 = force_const_mem (GET_MODE (SET_DEST (set
)), x
);
4178 if (! reg_equiv_memory_loc
[i
])
4179 reg_equiv_init
[i
] = NULL_RTX
;
4184 reg_equiv_init
[i
] = NULL_RTX
;
4189 reg_equiv_init
[i
] = NULL_RTX
;
4194 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4195 if (reg_equiv_init
[i
])
4197 fprintf (dump_file
, "init_insns for %u: ", i
);
4198 print_inline_rtx (dump_file
, reg_equiv_init
[i
], 20);
4199 fprintf (dump_file
, "\n");
4203 /* Indicate that we no longer have known memory locations or constants.
4204 Free all data involved in tracking these. */
4207 free_reg_equiv (void)
4211 if (reg_equiv_constant
)
4212 free (reg_equiv_constant
);
4213 if (reg_equiv_invariant
)
4214 free (reg_equiv_invariant
);
4215 reg_equiv_constant
= 0;
4216 reg_equiv_invariant
= 0;
4217 VEC_free (rtx
, gc
, reg_equiv_memory_loc_vec
);
4218 reg_equiv_memory_loc
= 0;
4220 if (offsets_known_at
)
4221 free (offsets_known_at
);
4225 offsets_known_at
= 0;
4227 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4228 if (reg_equiv_alt_mem_list
[i
])
4229 free_EXPR_LIST_list (®_equiv_alt_mem_list
[i
]);
4230 free (reg_equiv_alt_mem_list
);
4232 free (reg_equiv_mem
);
4233 free (reg_equiv_address
);
4236 /* Kick all pseudos out of hard register REGNO.
4238 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4239 because we found we can't eliminate some register. In the case, no pseudos
4240 are allowed to be in the register, even if they are only in a block that
4241 doesn't require spill registers, unlike the case when we are spilling this
4242 hard reg to produce another spill register.
4244 Return nonzero if any pseudos needed to be kicked out. */
4247 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
4253 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
4254 df_set_regs_ever_live (regno
, true);
4257 /* Spill every pseudo reg that was allocated to this reg
4258 or to something that overlaps this reg. */
4260 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4261 if (reg_renumber
[i
] >= 0
4262 && (unsigned int) reg_renumber
[i
] <= regno
4263 && end_hard_regno (PSEUDO_REGNO_MODE (i
), reg_renumber
[i
]) > regno
)
4264 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
4267 /* After find_reload_regs has been run for all insn that need reloads,
4268 and/or spill_hard_regs was called, this function is used to actually
4269 spill pseudo registers and try to reallocate them. It also sets up the
4270 spill_regs array for use by choose_reload_regs. */
4273 finish_spills (int global
)
4275 struct insn_chain
*chain
;
4276 int something_changed
= 0;
4278 reg_set_iterator rsi
;
4280 /* Build the spill_regs array for the function. */
4281 /* If there are some registers still to eliminate and one of the spill regs
4282 wasn't ever used before, additional stack space may have to be
4283 allocated to store this register. Thus, we may have changed the offset
4284 between the stack and frame pointers, so mark that something has changed.
4286 One might think that we need only set VAL to 1 if this is a call-used
4287 register. However, the set of registers that must be saved by the
4288 prologue is not identical to the call-used set. For example, the
4289 register used by the call insn for the return PC is a call-used register,
4290 but must be saved by the prologue. */
4293 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4294 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
4296 spill_reg_order
[i
] = n_spills
;
4297 spill_regs
[n_spills
++] = i
;
4298 if (num_eliminable
&& ! df_regs_ever_live_p (i
))
4299 something_changed
= 1;
4300 df_set_regs_ever_live (i
, true);
4303 spill_reg_order
[i
] = -1;
4305 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4306 if (! ira_conflicts_p
|| reg_renumber
[i
] >= 0)
4308 /* Record the current hard register the pseudo is allocated to
4309 in pseudo_previous_regs so we avoid reallocating it to the
4310 same hard reg in a later pass. */
4311 gcc_assert (reg_renumber
[i
] >= 0);
4313 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
4314 /* Mark it as no longer having a hard register home. */
4315 reg_renumber
[i
] = -1;
4316 if (ira_conflicts_p
)
4317 /* Inform IRA about the change. */
4318 ira_mark_allocation_change (i
);
4319 /* We will need to scan everything again. */
4320 something_changed
= 1;
4323 /* Retry global register allocation if possible. */
4324 if (global
&& ira_conflicts_p
)
4328 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
4329 /* For every insn that needs reloads, set the registers used as spill
4330 regs in pseudo_forbidden_regs for every pseudo live across the
4332 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
4334 EXECUTE_IF_SET_IN_REG_SET
4335 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4337 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4338 chain
->used_spill_regs
);
4340 EXECUTE_IF_SET_IN_REG_SET
4341 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4343 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4344 chain
->used_spill_regs
);
4348 /* Retry allocating the pseudos spilled in IRA and the
4349 reload. For each reg, merge the various reg sets that
4350 indicate which hard regs can't be used, and call
4351 ira_reassign_pseudos. */
4352 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned) max_regno
; i
++)
4353 if (reg_old_renumber
[i
] != reg_renumber
[i
])
4355 if (reg_renumber
[i
] < 0)
4356 temp_pseudo_reg_arr
[n
++] = i
;
4358 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
4360 if (ira_reassign_pseudos (temp_pseudo_reg_arr
, n
,
4361 bad_spill_regs_global
,
4362 pseudo_forbidden_regs
, pseudo_previous_regs
,
4364 something_changed
= 1;
4366 /* Fix up the register information in the insn chain.
4367 This involves deleting those of the spilled pseudos which did not get
4368 a new hard register home from the live_{before,after} sets. */
4369 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4371 HARD_REG_SET used_by_pseudos
;
4372 HARD_REG_SET used_by_pseudos2
;
4374 if (! ira_conflicts_p
)
4376 /* Don't do it for IRA because IRA and the reload still can
4377 assign hard registers to the spilled pseudos on next
4378 reload iterations. */
4379 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
4380 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
4382 /* Mark any unallocated hard regs as available for spills. That
4383 makes inheritance work somewhat better. */
4384 if (chain
->need_reload
)
4386 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
4387 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
4388 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
4390 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
4391 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
4392 /* Value of chain->used_spill_regs from previous iteration
4393 may be not included in the value calculated here because
4394 of possible removing caller-saves insns (see function
4395 delete_caller_save_insns. */
4396 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
4397 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
4401 CLEAR_REG_SET (&changed_allocation_pseudos
);
4402 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4403 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
4405 int regno
= reg_renumber
[i
];
4406 if (reg_old_renumber
[i
] == regno
)
4409 SET_REGNO_REG_SET (&changed_allocation_pseudos
, i
);
4411 alter_reg (i
, reg_old_renumber
[i
], false);
4412 reg_old_renumber
[i
] = regno
;
4416 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
4418 fprintf (dump_file
, " Register %d now in %d.\n\n",
4419 i
, reg_renumber
[i
]);
4423 return something_changed
;
4426 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4429 scan_paradoxical_subregs (rtx x
)
4433 enum rtx_code code
= GET_CODE (x
);
4444 case CONST_VECTOR
: /* shouldn't happen, but just in case. */
4452 if (REG_P (SUBREG_REG (x
))
4453 && (GET_MODE_SIZE (GET_MODE (x
))
4454 > reg_max_ref_width
[REGNO (SUBREG_REG (x
))]))
4456 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
4457 = GET_MODE_SIZE (GET_MODE (x
));
4458 mark_home_live_1 (REGNO (SUBREG_REG (x
)), GET_MODE (x
));
4466 fmt
= GET_RTX_FORMAT (code
);
4467 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4470 scan_paradoxical_subregs (XEXP (x
, i
));
4471 else if (fmt
[i
] == 'E')
4474 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4475 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
4480 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4481 examine all of the reload insns between PREV and NEXT exclusive, and
4482 annotate all that may trap. */
4485 fixup_eh_region_note (rtx insn
, rtx prev
, rtx next
)
4487 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
4490 if (!insn_could_throw_p (insn
))
4491 remove_note (insn
, note
);
4492 copy_reg_eh_region_note_forward (note
, NEXT_INSN (prev
), next
);
4495 /* Reload pseudo-registers into hard regs around each insn as needed.
4496 Additional register load insns are output before the insn that needs it
4497 and perhaps store insns after insns that modify the reloaded pseudo reg.
4499 reg_last_reload_reg and reg_reloaded_contents keep track of
4500 which registers are already available in reload registers.
4501 We update these for the reloads that we perform,
4502 as the insns are scanned. */
4505 reload_as_needed (int live_known
)
4507 struct insn_chain
*chain
;
4508 #if defined (AUTO_INC_DEC)
4513 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
4514 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
4515 reg_last_reload_reg
= XCNEWVEC (rtx
, max_regno
);
4516 INIT_REG_SET (®_has_output_reload
);
4517 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4518 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
4520 set_initial_elim_offsets ();
4522 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4525 rtx insn
= chain
->insn
;
4526 rtx old_next
= NEXT_INSN (insn
);
4528 rtx old_prev
= PREV_INSN (insn
);
4531 /* If we pass a label, copy the offsets from the label information
4532 into the current offsets of each elimination. */
4534 set_offsets_for_label (insn
);
4536 else if (INSN_P (insn
))
4538 regset_head regs_to_forget
;
4539 INIT_REG_SET (®s_to_forget
);
4540 note_stores (PATTERN (insn
), forget_old_reloads_1
, ®s_to_forget
);
4542 /* If this is a USE and CLOBBER of a MEM, ensure that any
4543 references to eliminable registers have been removed. */
4545 if ((GET_CODE (PATTERN (insn
)) == USE
4546 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4547 && MEM_P (XEXP (PATTERN (insn
), 0)))
4548 XEXP (XEXP (PATTERN (insn
), 0), 0)
4549 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4550 GET_MODE (XEXP (PATTERN (insn
), 0)),
4553 /* If we need to do register elimination processing, do so.
4554 This might delete the insn, in which case we are done. */
4555 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
4557 eliminate_regs_in_insn (insn
, 1);
4560 update_eliminable_offsets ();
4561 CLEAR_REG_SET (®s_to_forget
);
4566 /* If need_elim is nonzero but need_reload is zero, one might think
4567 that we could simply set n_reloads to 0. However, find_reloads
4568 could have done some manipulation of the insn (such as swapping
4569 commutative operands), and these manipulations are lost during
4570 the first pass for every insn that needs register elimination.
4571 So the actions of find_reloads must be redone here. */
4573 if (! chain
->need_elim
&& ! chain
->need_reload
4574 && ! chain
->need_operand_change
)
4576 /* First find the pseudo regs that must be reloaded for this insn.
4577 This info is returned in the tables reload_... (see reload.h).
4578 Also modify the body of INSN by substituting RELOAD
4579 rtx's for those pseudo regs. */
4582 CLEAR_REG_SET (®_has_output_reload
);
4583 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4585 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4591 rtx next
= NEXT_INSN (insn
);
4594 prev
= PREV_INSN (insn
);
4596 /* Now compute which reload regs to reload them into. Perhaps
4597 reusing reload regs from previous insns, or else output
4598 load insns to reload them. Maybe output store insns too.
4599 Record the choices of reload reg in reload_reg_rtx. */
4600 choose_reload_regs (chain
);
4602 /* Generate the insns to reload operands into or out of
4603 their reload regs. */
4604 emit_reload_insns (chain
);
4606 /* Substitute the chosen reload regs from reload_reg_rtx
4607 into the insn's body (or perhaps into the bodies of other
4608 load and store insn that we just made for reloading
4609 and that we moved the structure into). */
4610 subst_reloads (insn
);
4612 /* Adjust the exception region notes for loads and stores. */
4613 if (cfun
->can_throw_non_call_exceptions
&& !CALL_P (insn
))
4614 fixup_eh_region_note (insn
, prev
, next
);
4616 /* If this was an ASM, make sure that all the reload insns
4617 we have generated are valid. If not, give an error
4619 if (asm_noperands (PATTERN (insn
)) >= 0)
4620 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
4621 if (p
!= insn
&& INSN_P (p
)
4622 && GET_CODE (PATTERN (p
)) != USE
4623 && (recog_memoized (p
) < 0
4624 || (extract_insn (p
), ! constrain_operands (1))))
4626 error_for_asm (insn
,
4627 "%<asm%> operand requires "
4628 "impossible reload");
4633 if (num_eliminable
&& chain
->need_elim
)
4634 update_eliminable_offsets ();
4636 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4637 is no longer validly lying around to save a future reload.
4638 Note that this does not detect pseudos that were reloaded
4639 for this insn in order to be stored in
4640 (obeying register constraints). That is correct; such reload
4641 registers ARE still valid. */
4642 forget_marked_reloads (®s_to_forget
);
4643 CLEAR_REG_SET (®s_to_forget
);
4645 /* There may have been CLOBBER insns placed after INSN. So scan
4646 between INSN and NEXT and use them to forget old reloads. */
4647 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4648 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
4649 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
4652 /* Likewise for regs altered by auto-increment in this insn.
4653 REG_INC notes have been changed by reloading:
4654 find_reloads_address_1 records substitutions for them,
4655 which have been performed by subst_reloads above. */
4656 for (i
= n_reloads
- 1; i
>= 0; i
--)
4658 rtx in_reg
= rld
[i
].in_reg
;
4661 enum rtx_code code
= GET_CODE (in_reg
);
4662 /* PRE_INC / PRE_DEC will have the reload register ending up
4663 with the same value as the stack slot, but that doesn't
4664 hold true for POST_INC / POST_DEC. Either we have to
4665 convert the memory access to a true POST_INC / POST_DEC,
4666 or we can't use the reload register for inheritance. */
4667 if ((code
== POST_INC
|| code
== POST_DEC
)
4668 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4669 REGNO (rld
[i
].reg_rtx
))
4670 /* Make sure it is the inc/dec pseudo, and not
4671 some other (e.g. output operand) pseudo. */
4672 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4673 == REGNO (XEXP (in_reg
, 0))))
4676 rtx reload_reg
= rld
[i
].reg_rtx
;
4677 enum machine_mode mode
= GET_MODE (reload_reg
);
4681 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4683 /* We really want to ignore REG_INC notes here, so
4684 use PATTERN (p) as argument to reg_set_p . */
4685 if (reg_set_p (reload_reg
, PATTERN (p
)))
4687 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4693 = gen_rtx_fmt_e (code
, mode
, reload_reg
);
4695 validate_replace_rtx_group (reload_reg
,
4697 n
= verify_changes (0);
4699 /* We must also verify that the constraints
4700 are met after the replacement. Make sure
4701 extract_insn is only called for an insn
4702 where the replacements were found to be
4707 n
= constrain_operands (1);
4710 /* If the constraints were not met, then
4711 undo the replacement, else confirm it. */
4715 confirm_change_group ();
4721 add_reg_note (p
, REG_INC
, reload_reg
);
4722 /* Mark this as having an output reload so that the
4723 REG_INC processing code below won't invalidate
4724 the reload for inheritance. */
4725 SET_HARD_REG_BIT (reg_is_output_reload
,
4726 REGNO (reload_reg
));
4727 SET_REGNO_REG_SET (®_has_output_reload
,
4728 REGNO (XEXP (in_reg
, 0)));
4731 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4734 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4735 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4736 REGNO (rld
[i
].reg_rtx
))
4737 /* Make sure it is the inc/dec pseudo, and not
4738 some other (e.g. output operand) pseudo. */
4739 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4740 == REGNO (XEXP (in_reg
, 0))))
4742 SET_HARD_REG_BIT (reg_is_output_reload
,
4743 REGNO (rld
[i
].reg_rtx
));
4744 SET_REGNO_REG_SET (®_has_output_reload
,
4745 REGNO (XEXP (in_reg
, 0)));
4747 else if (code
== PRE_INC
|| code
== PRE_DEC
4748 || code
== POST_INC
|| code
== POST_DEC
)
4750 int in_regno
= REGNO (XEXP (in_reg
, 0));
4752 if (reg_last_reload_reg
[in_regno
] != NULL_RTX
)
4755 bool forget_p
= true;
4757 in_hard_regno
= REGNO (reg_last_reload_reg
[in_regno
]);
4758 if (TEST_HARD_REG_BIT (reg_reloaded_valid
,
4761 for (x
= old_prev
? NEXT_INSN (old_prev
) : insn
;
4764 if (x
== reg_reloaded_insn
[in_hard_regno
])
4770 /* If for some reasons, we didn't set up
4771 reg_last_reload_reg in this insn,
4772 invalidate inheritance from previous
4773 insns for the incremented/decremented
4774 register. Such registers will be not in
4775 reg_has_output_reload. Invalidate it
4776 also if the corresponding element in
4777 reg_reloaded_insn is also
4780 forget_old_reloads_1 (XEXP (in_reg
, 0),
4786 /* If a pseudo that got a hard register is auto-incremented,
4787 we must purge records of copying it into pseudos without
4789 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4790 if (REG_NOTE_KIND (x
) == REG_INC
)
4792 /* See if this pseudo reg was reloaded in this insn.
4793 If so, its last-reload info is still valid
4794 because it is based on this insn's reload. */
4795 for (i
= 0; i
< n_reloads
; i
++)
4796 if (rld
[i
].out
== XEXP (x
, 0))
4800 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4804 /* A reload reg's contents are unknown after a label. */
4806 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4808 /* Don't assume a reload reg is still good after a call insn
4809 if it is a call-used reg, or if it contains a value that will
4810 be partially clobbered by the call. */
4811 else if (CALL_P (insn
))
4813 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4814 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, reg_reloaded_call_part_clobbered
);
4819 free (reg_last_reload_reg
);
4820 CLEAR_REG_SET (®_has_output_reload
);
4823 /* Discard all record of any value reloaded from X,
4824 or reloaded in X from someplace else;
4825 unless X is an output reload reg of the current insn.
4827 X may be a hard reg (the reload reg)
4828 or it may be a pseudo reg that was reloaded from.
4830 When DATA is non-NULL just mark the registers in regset
4831 to be forgotten later. */
4834 forget_old_reloads_1 (rtx x
, const_rtx ignored ATTRIBUTE_UNUSED
,
4839 regset regs
= (regset
) data
;
4841 /* note_stores does give us subregs of hard regs,
4842 subreg_regno_offset requires a hard reg. */
4843 while (GET_CODE (x
) == SUBREG
)
4845 /* We ignore the subreg offset when calculating the regno,
4846 because we are using the entire underlying hard register
4856 if (regno
>= FIRST_PSEUDO_REGISTER
)
4862 nr
= hard_regno_nregs
[regno
][GET_MODE (x
)];
4863 /* Storing into a spilled-reg invalidates its contents.
4864 This can happen if a block-local pseudo is allocated to that reg
4865 and it wasn't spilled because this block's total need is 0.
4866 Then some insn might have an optional reload and use this reg. */
4868 for (i
= 0; i
< nr
; i
++)
4869 /* But don't do this if the reg actually serves as an output
4870 reload reg in the current instruction. */
4872 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4874 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4875 spill_reg_store
[regno
+ i
] = 0;
4881 SET_REGNO_REG_SET (regs
, regno
+ nr
);
4884 /* Since value of X has changed,
4885 forget any value previously copied from it. */
4888 /* But don't forget a copy if this is the output reload
4889 that establishes the copy's validity. */
4891 || !REGNO_REG_SET_P (®_has_output_reload
, regno
+ nr
))
4892 reg_last_reload_reg
[regno
+ nr
] = 0;
4896 /* Forget the reloads marked in regset by previous function. */
4898 forget_marked_reloads (regset regs
)
4901 reg_set_iterator rsi
;
4902 EXECUTE_IF_SET_IN_REG_SET (regs
, 0, reg
, rsi
)
4904 if (reg
< FIRST_PSEUDO_REGISTER
4905 /* But don't do this if the reg actually serves as an output
4906 reload reg in the current instruction. */
4908 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, reg
)))
4910 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, reg
);
4911 spill_reg_store
[reg
] = 0;
4914 || !REGNO_REG_SET_P (®_has_output_reload
, reg
))
4915 reg_last_reload_reg
[reg
] = 0;
4919 /* The following HARD_REG_SETs indicate when each hard register is
4920 used for a reload of various parts of the current insn. */
4922 /* If reg is unavailable for all reloads. */
4923 static HARD_REG_SET reload_reg_unavailable
;
4924 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4925 static HARD_REG_SET reload_reg_used
;
4926 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4927 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4928 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4929 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4930 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4931 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4932 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4933 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4934 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4935 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4936 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4937 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4938 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4939 static HARD_REG_SET reload_reg_used_in_op_addr
;
4940 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4941 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4942 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4943 static HARD_REG_SET reload_reg_used_in_insn
;
4944 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4945 static HARD_REG_SET reload_reg_used_in_other_addr
;
4947 /* If reg is in use as a reload reg for any sort of reload. */
4948 static HARD_REG_SET reload_reg_used_at_all
;
4950 /* If reg is use as an inherited reload. We just mark the first register
4952 static HARD_REG_SET reload_reg_used_for_inherit
;
4954 /* Records which hard regs are used in any way, either as explicit use or
4955 by being allocated to a pseudo during any point of the current insn. */
4956 static HARD_REG_SET reg_used_in_insn
;
4958 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4959 TYPE. MODE is used to indicate how many consecutive regs are
4963 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
4964 enum machine_mode mode
)
4966 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
4969 for (i
= regno
; i
< nregs
+ regno
; i
++)
4974 SET_HARD_REG_BIT (reload_reg_used
, i
);
4977 case RELOAD_FOR_INPUT_ADDRESS
:
4978 SET_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4981 case RELOAD_FOR_INPADDR_ADDRESS
:
4982 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], i
);
4985 case RELOAD_FOR_OUTPUT_ADDRESS
:
4986 SET_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4989 case RELOAD_FOR_OUTADDR_ADDRESS
:
4990 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], i
);
4993 case RELOAD_FOR_OPERAND_ADDRESS
:
4994 SET_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
4997 case RELOAD_FOR_OPADDR_ADDR
:
4998 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, i
);
5001 case RELOAD_FOR_OTHER_ADDRESS
:
5002 SET_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
5005 case RELOAD_FOR_INPUT
:
5006 SET_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
5009 case RELOAD_FOR_OUTPUT
:
5010 SET_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
5013 case RELOAD_FOR_INSN
:
5014 SET_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
5018 SET_HARD_REG_BIT (reload_reg_used_at_all
, i
);
5022 /* Similarly, but show REGNO is no longer in use for a reload. */
5025 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
5026 enum reload_type type
, enum machine_mode mode
)
5028 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
5029 unsigned int start_regno
, end_regno
, r
;
5031 /* A complication is that for some reload types, inheritance might
5032 allow multiple reloads of the same types to share a reload register.
5033 We set check_opnum if we have to check only reloads with the same
5034 operand number, and check_any if we have to check all reloads. */
5035 int check_opnum
= 0;
5037 HARD_REG_SET
*used_in_set
;
5042 used_in_set
= &reload_reg_used
;
5045 case RELOAD_FOR_INPUT_ADDRESS
:
5046 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
5049 case RELOAD_FOR_INPADDR_ADDRESS
:
5051 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
5054 case RELOAD_FOR_OUTPUT_ADDRESS
:
5055 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
5058 case RELOAD_FOR_OUTADDR_ADDRESS
:
5060 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
5063 case RELOAD_FOR_OPERAND_ADDRESS
:
5064 used_in_set
= &reload_reg_used_in_op_addr
;
5067 case RELOAD_FOR_OPADDR_ADDR
:
5069 used_in_set
= &reload_reg_used_in_op_addr_reload
;
5072 case RELOAD_FOR_OTHER_ADDRESS
:
5073 used_in_set
= &reload_reg_used_in_other_addr
;
5077 case RELOAD_FOR_INPUT
:
5078 used_in_set
= &reload_reg_used_in_input
[opnum
];
5081 case RELOAD_FOR_OUTPUT
:
5082 used_in_set
= &reload_reg_used_in_output
[opnum
];
5085 case RELOAD_FOR_INSN
:
5086 used_in_set
= &reload_reg_used_in_insn
;
5091 /* We resolve conflicts with remaining reloads of the same type by
5092 excluding the intervals of reload registers by them from the
5093 interval of freed reload registers. Since we only keep track of
5094 one set of interval bounds, we might have to exclude somewhat
5095 more than what would be necessary if we used a HARD_REG_SET here.
5096 But this should only happen very infrequently, so there should
5097 be no reason to worry about it. */
5099 start_regno
= regno
;
5100 end_regno
= regno
+ nregs
;
5101 if (check_opnum
|| check_any
)
5103 for (i
= n_reloads
- 1; i
>= 0; i
--)
5105 if (rld
[i
].when_needed
== type
5106 && (check_any
|| rld
[i
].opnum
== opnum
)
5109 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
5110 unsigned int conflict_end
5111 = end_hard_regno (rld
[i
].mode
, conflict_start
);
5113 /* If there is an overlap with the first to-be-freed register,
5114 adjust the interval start. */
5115 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
5116 start_regno
= conflict_end
;
5117 /* Otherwise, if there is a conflict with one of the other
5118 to-be-freed registers, adjust the interval end. */
5119 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
5120 end_regno
= conflict_start
;
5125 for (r
= start_regno
; r
< end_regno
; r
++)
5126 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
5129 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5130 specified by OPNUM and TYPE. */
5133 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
5137 /* In use for a RELOAD_OTHER means it's not available for anything. */
5138 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
5139 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5145 /* In use for anything means we can't use it for RELOAD_OTHER. */
5146 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
5147 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5148 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5149 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5152 for (i
= 0; i
< reload_n_operands
; i
++)
5153 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5154 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5155 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5156 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5157 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5158 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5163 case RELOAD_FOR_INPUT
:
5164 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5165 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
5168 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5171 /* If it is used for some other input, can't use it. */
5172 for (i
= 0; i
< reload_n_operands
; i
++)
5173 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5176 /* If it is used in a later operand's address, can't use it. */
5177 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5178 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5179 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5184 case RELOAD_FOR_INPUT_ADDRESS
:
5185 /* Can't use a register if it is used for an input address for this
5186 operand or used as an input in an earlier one. */
5187 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
5188 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5191 for (i
= 0; i
< opnum
; i
++)
5192 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5197 case RELOAD_FOR_INPADDR_ADDRESS
:
5198 /* Can't use a register if it is used for an input address
5199 for this operand or used as an input in an earlier
5201 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5204 for (i
= 0; i
< opnum
; i
++)
5205 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5210 case RELOAD_FOR_OUTPUT_ADDRESS
:
5211 /* Can't use a register if it is used for an output address for this
5212 operand or used as an output in this or a later operand. Note
5213 that multiple output operands are emitted in reverse order, so
5214 the conflicting ones are those with lower indices. */
5215 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
5218 for (i
= 0; i
<= opnum
; i
++)
5219 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5224 case RELOAD_FOR_OUTADDR_ADDRESS
:
5225 /* Can't use a register if it is used for an output address
5226 for this operand or used as an output in this or a
5227 later operand. Note that multiple output operands are
5228 emitted in reverse order, so the conflicting ones are
5229 those with lower indices. */
5230 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5233 for (i
= 0; i
<= opnum
; i
++)
5234 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5239 case RELOAD_FOR_OPERAND_ADDRESS
:
5240 for (i
= 0; i
< reload_n_operands
; i
++)
5241 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5244 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5245 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5247 case RELOAD_FOR_OPADDR_ADDR
:
5248 for (i
= 0; i
< reload_n_operands
; i
++)
5249 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5252 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
5254 case RELOAD_FOR_OUTPUT
:
5255 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5256 outputs, or an operand address for this or an earlier output.
5257 Note that multiple output operands are emitted in reverse order,
5258 so the conflicting ones are those with higher indices. */
5259 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5262 for (i
= 0; i
< reload_n_operands
; i
++)
5263 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5266 for (i
= opnum
; i
< reload_n_operands
; i
++)
5267 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5268 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5273 case RELOAD_FOR_INSN
:
5274 for (i
= 0; i
< reload_n_operands
; i
++)
5275 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5276 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5279 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5280 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5282 case RELOAD_FOR_OTHER_ADDRESS
:
5283 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
5290 /* Return 1 if the value in reload reg REGNO, as used by a reload
5291 needed for the part of the insn specified by OPNUM and TYPE,
5292 is still available in REGNO at the end of the insn.
5294 We can assume that the reload reg was already tested for availability
5295 at the time it is needed, and we should not check this again,
5296 in case the reg has already been marked in use. */
5299 reload_reg_reaches_end_p (unsigned int regno
, int opnum
, enum reload_type type
)
5306 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5307 its value must reach the end. */
5310 /* If this use is for part of the insn,
5311 its value reaches if no subsequent part uses the same register.
5312 Just like the above function, don't try to do this with lots
5315 case RELOAD_FOR_OTHER_ADDRESS
:
5316 /* Here we check for everything else, since these don't conflict
5317 with anything else and everything comes later. */
5319 for (i
= 0; i
< reload_n_operands
; i
++)
5320 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5321 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5322 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
5323 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5324 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5325 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5328 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5329 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5330 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5331 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5333 case RELOAD_FOR_INPUT_ADDRESS
:
5334 case RELOAD_FOR_INPADDR_ADDRESS
:
5335 /* Similar, except that we check only for this and subsequent inputs
5336 and the address of only subsequent inputs and we do not need
5337 to check for RELOAD_OTHER objects since they are known not to
5340 for (i
= opnum
; i
< reload_n_operands
; i
++)
5341 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5344 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5345 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5346 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5349 for (i
= 0; i
< reload_n_operands
; i
++)
5350 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5351 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5352 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5355 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5358 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5359 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5360 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5362 case RELOAD_FOR_INPUT
:
5363 /* Similar to input address, except we start at the next operand for
5364 both input and input address and we do not check for
5365 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5368 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5369 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5370 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5371 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5374 /* ... fall through ... */
5376 case RELOAD_FOR_OPERAND_ADDRESS
:
5377 /* Check outputs and their addresses. */
5379 for (i
= 0; i
< reload_n_operands
; i
++)
5380 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5381 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5382 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5385 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5387 case RELOAD_FOR_OPADDR_ADDR
:
5388 for (i
= 0; i
< reload_n_operands
; i
++)
5389 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5390 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5391 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5394 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5395 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5396 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5398 case RELOAD_FOR_INSN
:
5399 /* These conflict with other outputs with RELOAD_OTHER. So
5400 we need only check for output addresses. */
5402 opnum
= reload_n_operands
;
5404 /* ... fall through ... */
5406 case RELOAD_FOR_OUTPUT
:
5407 case RELOAD_FOR_OUTPUT_ADDRESS
:
5408 case RELOAD_FOR_OUTADDR_ADDRESS
:
5409 /* We already know these can't conflict with a later output. So the
5410 only thing to check are later output addresses.
5411 Note that multiple output operands are emitted in reverse order,
5412 so the conflicting ones are those with lower indices. */
5413 for (i
= 0; i
< opnum
; i
++)
5414 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5415 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5425 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5426 every register in the range [REGNO, REGNO + NREGS). */
5429 reload_regs_reach_end_p (unsigned int regno
, int nregs
,
5430 int opnum
, enum reload_type type
)
5434 for (i
= 0; i
< nregs
; i
++)
5435 if (!reload_reg_reaches_end_p (regno
+ i
, opnum
, type
))
5441 /* Returns whether R1 and R2 are uniquely chained: the value of one
5442 is used by the other, and that value is not used by any other
5443 reload for this insn. This is used to partially undo the decision
5444 made in find_reloads when in the case of multiple
5445 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5446 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5447 reloads. This code tries to avoid the conflict created by that
5448 change. It might be cleaner to explicitly keep track of which
5449 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5450 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5451 this after the fact. */
5453 reloads_unique_chain_p (int r1
, int r2
)
5457 /* We only check input reloads. */
5458 if (! rld
[r1
].in
|| ! rld
[r2
].in
)
5461 /* Avoid anything with output reloads. */
5462 if (rld
[r1
].out
|| rld
[r2
].out
)
5465 /* "chained" means one reload is a component of the other reload,
5466 not the same as the other reload. */
5467 if (rld
[r1
].opnum
!= rld
[r2
].opnum
5468 || rtx_equal_p (rld
[r1
].in
, rld
[r2
].in
)
5469 || rld
[r1
].optional
|| rld
[r2
].optional
5470 || ! (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
)
5471 || reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
)))
5474 for (i
= 0; i
< n_reloads
; i
++)
5475 /* Look for input reloads that aren't our two */
5476 if (i
!= r1
&& i
!= r2
&& rld
[i
].in
)
5478 /* If our reload is mentioned at all, it isn't a simple chain. */
5479 if (reg_mentioned_p (rld
[r1
].in
, rld
[i
].in
))
5485 /* The recursive function change all occurrences of WHAT in *WHERE
5488 substitute (rtx
*where
, const_rtx what
, rtx repl
)
5497 if (*where
== what
|| rtx_equal_p (*where
, what
))
5499 /* Record the location of the changed rtx. */
5500 VEC_safe_push (rtx_p
, heap
, substitute_stack
, where
);
5505 code
= GET_CODE (*where
);
5506 fmt
= GET_RTX_FORMAT (code
);
5507 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5513 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
5514 substitute (&XVECEXP (*where
, i
, j
), what
, repl
);
5516 else if (fmt
[i
] == 'e')
5517 substitute (&XEXP (*where
, i
), what
, repl
);
5521 /* The function returns TRUE if chain of reload R1 and R2 (in any
5522 order) can be evaluated without usage of intermediate register for
5523 the reload containing another reload. It is important to see
5524 gen_reload to understand what the function is trying to do. As an
5525 example, let us have reload chain
5528 r1: <something> + const
5530 and reload R2 got reload reg HR. The function returns true if
5531 there is a correct insn HR = HR + <something>. Otherwise,
5532 gen_reload will use intermediate register (and this is the reload
5533 reg for R1) to reload <something>.
5535 We need this function to find a conflict for chain reloads. In our
5536 example, if HR = HR + <something> is incorrect insn, then we cannot
5537 use HR as a reload register for R2. If we do use it then we get a
5546 gen_reload_chain_without_interm_reg_p (int r1
, int r2
)
5548 /* Assume other cases in gen_reload are not possible for
5549 chain reloads or do need an intermediate hard registers. */
5552 rtx out
, in
, tem
, insn
;
5553 rtx last
= get_last_insn ();
5555 /* Make r2 a component of r1. */
5556 if (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
))
5562 gcc_assert (reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
));
5563 regno
= rld
[r1
].regno
>= 0 ? rld
[r1
].regno
: rld
[r2
].regno
;
5564 gcc_assert (regno
>= 0);
5565 out
= gen_rtx_REG (rld
[r1
].mode
, regno
);
5567 substitute (&in
, rld
[r2
].in
, gen_rtx_REG (rld
[r2
].mode
, regno
));
5569 /* If IN is a paradoxical SUBREG, remove it and try to put the
5570 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5571 if (GET_CODE (in
) == SUBREG
5572 && (GET_MODE_SIZE (GET_MODE (in
))
5573 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
5574 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
5575 in
= SUBREG_REG (in
), out
= tem
;
5577 if (GET_CODE (in
) == PLUS
5578 && (REG_P (XEXP (in
, 0))
5579 || GET_CODE (XEXP (in
, 0)) == SUBREG
5580 || MEM_P (XEXP (in
, 0)))
5581 && (REG_P (XEXP (in
, 1))
5582 || GET_CODE (XEXP (in
, 1)) == SUBREG
5583 || CONSTANT_P (XEXP (in
, 1))
5584 || MEM_P (XEXP (in
, 1))))
5586 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
5587 code
= recog_memoized (insn
);
5592 extract_insn (insn
);
5593 /* We want constrain operands to treat this insn strictly in
5594 its validity determination, i.e., the way it would after
5595 reload has completed. */
5596 result
= constrain_operands (1);
5599 delete_insns_since (last
);
5602 /* Restore the original value at each changed address within R1. */
5603 while (!VEC_empty (rtx_p
, substitute_stack
))
5605 rtx
*where
= VEC_pop (rtx_p
, substitute_stack
);
5606 *where
= rld
[r2
].in
;
5612 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5615 This function uses the same algorithm as reload_reg_free_p above. */
5618 reloads_conflict (int r1
, int r2
)
5620 enum reload_type r1_type
= rld
[r1
].when_needed
;
5621 enum reload_type r2_type
= rld
[r2
].when_needed
;
5622 int r1_opnum
= rld
[r1
].opnum
;
5623 int r2_opnum
= rld
[r2
].opnum
;
5625 /* RELOAD_OTHER conflicts with everything. */
5626 if (r2_type
== RELOAD_OTHER
)
5629 /* Otherwise, check conflicts differently for each type. */
5633 case RELOAD_FOR_INPUT
:
5634 return (r2_type
== RELOAD_FOR_INSN
5635 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5636 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5637 || r2_type
== RELOAD_FOR_INPUT
5638 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5639 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5640 && r2_opnum
> r1_opnum
));
5642 case RELOAD_FOR_INPUT_ADDRESS
:
5643 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5644 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5646 case RELOAD_FOR_INPADDR_ADDRESS
:
5647 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5648 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5650 case RELOAD_FOR_OUTPUT_ADDRESS
:
5651 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5652 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5654 case RELOAD_FOR_OUTADDR_ADDRESS
:
5655 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5656 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5658 case RELOAD_FOR_OPERAND_ADDRESS
:
5659 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5660 || (r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5661 && (!reloads_unique_chain_p (r1
, r2
)
5662 || !gen_reload_chain_without_interm_reg_p (r1
, r2
))));
5664 case RELOAD_FOR_OPADDR_ADDR
:
5665 return (r2_type
== RELOAD_FOR_INPUT
5666 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5668 case RELOAD_FOR_OUTPUT
:
5669 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5670 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5671 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5672 && r2_opnum
>= r1_opnum
));
5674 case RELOAD_FOR_INSN
:
5675 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5676 || r2_type
== RELOAD_FOR_INSN
5677 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5679 case RELOAD_FOR_OTHER_ADDRESS
:
5680 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5690 /* Indexed by reload number, 1 if incoming value
5691 inherited from previous insns. */
5692 static char reload_inherited
[MAX_RELOADS
];
5694 /* For an inherited reload, this is the insn the reload was inherited from,
5695 if we know it. Otherwise, this is 0. */
5696 static rtx reload_inheritance_insn
[MAX_RELOADS
];
5698 /* If nonzero, this is a place to get the value of the reload,
5699 rather than using reload_in. */
5700 static rtx reload_override_in
[MAX_RELOADS
];
5702 /* For each reload, the hard register number of the register used,
5703 or -1 if we did not need a register for this reload. */
5704 static int reload_spill_index
[MAX_RELOADS
];
5706 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5707 static rtx reload_reg_rtx_for_input
[MAX_RELOADS
];
5709 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5710 static rtx reload_reg_rtx_for_output
[MAX_RELOADS
];
5712 /* Subroutine of free_for_value_p, used to check a single register.
5713 START_REGNO is the starting regno of the full reload register
5714 (possibly comprising multiple hard registers) that we are considering. */
5717 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
5718 enum reload_type type
, rtx value
, rtx out
,
5719 int reloadnum
, int ignore_address_reloads
)
5722 /* Set if we see an input reload that must not share its reload register
5723 with any new earlyclobber, but might otherwise share the reload
5724 register with an output or input-output reload. */
5725 int check_earlyclobber
= 0;
5729 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5732 if (out
== const0_rtx
)
5738 /* We use some pseudo 'time' value to check if the lifetimes of the
5739 new register use would overlap with the one of a previous reload
5740 that is not read-only or uses a different value.
5741 The 'time' used doesn't have to be linear in any shape or form, just
5743 Some reload types use different 'buckets' for each operand.
5744 So there are MAX_RECOG_OPERANDS different time values for each
5746 We compute TIME1 as the time when the register for the prospective
5747 new reload ceases to be live, and TIME2 for each existing
5748 reload as the time when that the reload register of that reload
5750 Where there is little to be gained by exact lifetime calculations,
5751 we just make conservative assumptions, i.e. a longer lifetime;
5752 this is done in the 'default:' cases. */
5755 case RELOAD_FOR_OTHER_ADDRESS
:
5756 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5757 time1
= copy
? 0 : 1;
5760 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
5762 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5763 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5764 respectively, to the time values for these, we get distinct time
5765 values. To get distinct time values for each operand, we have to
5766 multiply opnum by at least three. We round that up to four because
5767 multiply by four is often cheaper. */
5768 case RELOAD_FOR_INPADDR_ADDRESS
:
5769 time1
= opnum
* 4 + 2;
5771 case RELOAD_FOR_INPUT_ADDRESS
:
5772 time1
= opnum
* 4 + 3;
5774 case RELOAD_FOR_INPUT
:
5775 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5776 executes (inclusive). */
5777 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
5779 case RELOAD_FOR_OPADDR_ADDR
:
5781 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5782 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5784 case RELOAD_FOR_OPERAND_ADDRESS
:
5785 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5787 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
5789 case RELOAD_FOR_OUTADDR_ADDRESS
:
5790 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
5792 case RELOAD_FOR_OUTPUT_ADDRESS
:
5793 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
5796 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
5799 for (i
= 0; i
< n_reloads
; i
++)
5801 rtx reg
= rld
[i
].reg_rtx
;
5802 if (reg
&& REG_P (reg
)
5803 && ((unsigned) regno
- true_regnum (reg
)
5804 <= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] - (unsigned) 1)
5807 rtx other_input
= rld
[i
].in
;
5809 /* If the other reload loads the same input value, that
5810 will not cause a conflict only if it's loading it into
5811 the same register. */
5812 if (true_regnum (reg
) != start_regno
)
5813 other_input
= NULL_RTX
;
5814 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
5815 || rld
[i
].out
|| out
)
5818 switch (rld
[i
].when_needed
)
5820 case RELOAD_FOR_OTHER_ADDRESS
:
5823 case RELOAD_FOR_INPADDR_ADDRESS
:
5824 /* find_reloads makes sure that a
5825 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5826 by at most one - the first -
5827 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5828 address reload is inherited, the address address reload
5829 goes away, so we can ignore this conflict. */
5830 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
5831 && ignore_address_reloads
5832 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5833 Then the address address is still needed to store
5834 back the new address. */
5835 && ! rld
[reloadnum
].out
)
5837 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5838 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5840 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5841 && ignore_address_reloads
5842 /* Unless we are reloading an auto_inc expression. */
5843 && ! rld
[reloadnum
].out
)
5845 time2
= rld
[i
].opnum
* 4 + 2;
5847 case RELOAD_FOR_INPUT_ADDRESS
:
5848 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5849 && ignore_address_reloads
5850 && ! rld
[reloadnum
].out
)
5852 time2
= rld
[i
].opnum
* 4 + 3;
5854 case RELOAD_FOR_INPUT
:
5855 time2
= rld
[i
].opnum
* 4 + 4;
5856 check_earlyclobber
= 1;
5858 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5859 == MAX_RECOG_OPERAND * 4 */
5860 case RELOAD_FOR_OPADDR_ADDR
:
5861 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
5862 && ignore_address_reloads
5863 && ! rld
[reloadnum
].out
)
5865 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5867 case RELOAD_FOR_OPERAND_ADDRESS
:
5868 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
5869 check_earlyclobber
= 1;
5871 case RELOAD_FOR_INSN
:
5872 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5874 case RELOAD_FOR_OUTPUT
:
5875 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5876 instruction is executed. */
5877 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5879 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5880 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5882 case RELOAD_FOR_OUTADDR_ADDRESS
:
5883 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
5884 && ignore_address_reloads
5885 && ! rld
[reloadnum
].out
)
5887 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
5889 case RELOAD_FOR_OUTPUT_ADDRESS
:
5890 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
5893 /* If there is no conflict in the input part, handle this
5894 like an output reload. */
5895 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
5897 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5898 /* Earlyclobbered outputs must conflict with inputs. */
5899 if (earlyclobber_operand_p (rld
[i
].out
))
5900 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5905 /* RELOAD_OTHER might be live beyond instruction execution,
5906 but this is not obvious when we set time2 = 1. So check
5907 here if there might be a problem with the new reload
5908 clobbering the register used by the RELOAD_OTHER. */
5916 && (! rld
[i
].in
|| rld
[i
].out
5917 || ! rtx_equal_p (other_input
, value
)))
5918 || (out
&& rld
[reloadnum
].out_reg
5919 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
5925 /* Earlyclobbered outputs must conflict with inputs. */
5926 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
5932 /* Return 1 if the value in reload reg REGNO, as used by a reload
5933 needed for the part of the insn specified by OPNUM and TYPE,
5934 may be used to load VALUE into it.
5936 MODE is the mode in which the register is used, this is needed to
5937 determine how many hard regs to test.
5939 Other read-only reloads with the same value do not conflict
5940 unless OUT is nonzero and these other reloads have to live while
5941 output reloads live.
5942 If OUT is CONST0_RTX, this is a special case: it means that the
5943 test should not be for using register REGNO as reload register, but
5944 for copying from register REGNO into the reload register.
5946 RELOADNUM is the number of the reload we want to load this value for;
5947 a reload does not conflict with itself.
5949 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5950 reloads that load an address for the very reload we are considering.
5952 The caller has to make sure that there is no conflict with the return
5956 free_for_value_p (int regno
, enum machine_mode mode
, int opnum
,
5957 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
5958 int ignore_address_reloads
)
5960 int nregs
= hard_regno_nregs
[regno
][mode
];
5962 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
5963 value
, out
, reloadnum
,
5964 ignore_address_reloads
))
5969 /* Return nonzero if the rtx X is invariant over the current function. */
5970 /* ??? Actually, the places where we use this expect exactly what is
5971 tested here, and not everything that is function invariant. In
5972 particular, the frame pointer and arg pointer are special cased;
5973 pic_offset_table_rtx is not, and we must not spill these things to
5977 function_invariant_p (const_rtx x
)
5981 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
5983 if (GET_CODE (x
) == PLUS
5984 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
5985 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5990 /* Determine whether the reload reg X overlaps any rtx'es used for
5991 overriding inheritance. Return nonzero if so. */
5994 conflicts_with_override (rtx x
)
5997 for (i
= 0; i
< n_reloads
; i
++)
5998 if (reload_override_in
[i
]
5999 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
6004 /* Give an error message saying we failed to find a reload for INSN,
6005 and clear out reload R. */
6007 failed_reload (rtx insn
, int r
)
6009 if (asm_noperands (PATTERN (insn
)) < 0)
6010 /* It's the compiler's fault. */
6011 fatal_insn ("could not find a spill register", insn
);
6013 /* It's the user's fault; the operand's mode and constraint
6014 don't match. Disable this reload so we don't crash in final. */
6015 error_for_asm (insn
,
6016 "%<asm%> operand constraint incompatible with operand size");
6020 rld
[r
].optional
= 1;
6021 rld
[r
].secondary_p
= 1;
6024 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6025 for reload R. If it's valid, get an rtx for it. Return nonzero if
6028 set_reload_reg (int i
, int r
)
6031 rtx reg
= spill_reg_rtx
[i
];
6033 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
6034 spill_reg_rtx
[i
] = reg
6035 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
6037 regno
= true_regnum (reg
);
6039 /* Detect when the reload reg can't hold the reload mode.
6040 This used to be one `if', but Sequent compiler can't handle that. */
6041 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6043 enum machine_mode test_mode
= VOIDmode
;
6045 test_mode
= GET_MODE (rld
[r
].in
);
6046 /* If rld[r].in has VOIDmode, it means we will load it
6047 in whatever mode the reload reg has: to wit, rld[r].mode.
6048 We have already tested that for validity. */
6049 /* Aside from that, we need to test that the expressions
6050 to reload from or into have modes which are valid for this
6051 reload register. Otherwise the reload insns would be invalid. */
6052 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
6053 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
6054 if (! (rld
[r
].out
!= 0
6055 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
6057 /* The reg is OK. */
6060 /* Mark as in use for this insn the reload regs we use
6062 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
6063 rld
[r
].when_needed
, rld
[r
].mode
);
6065 rld
[r
].reg_rtx
= reg
;
6066 reload_spill_index
[r
] = spill_regs
[i
];
6073 /* Find a spill register to use as a reload register for reload R.
6074 LAST_RELOAD is nonzero if this is the last reload for the insn being
6077 Set rld[R].reg_rtx to the register allocated.
6079 We return 1 if successful, or 0 if we couldn't find a spill reg and
6080 we didn't change anything. */
6083 allocate_reload_reg (struct insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
6088 /* If we put this reload ahead, thinking it is a group,
6089 then insist on finding a group. Otherwise we can grab a
6090 reg that some other reload needs.
6091 (That can happen when we have a 68000 DATA_OR_FP_REG
6092 which is a group of data regs or one fp reg.)
6093 We need not be so restrictive if there are no more reloads
6096 ??? Really it would be nicer to have smarter handling
6097 for that kind of reg class, where a problem like this is normal.
6098 Perhaps those classes should be avoided for reloading
6099 by use of more alternatives. */
6101 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
6103 /* If we want a single register and haven't yet found one,
6104 take any reg in the right class and not in use.
6105 If we want a consecutive group, here is where we look for it.
6107 We use three passes so we can first look for reload regs to
6108 reuse, which are already in use for other reloads in this insn,
6109 and only then use additional registers which are not "bad", then
6110 finally any register.
6112 I think that maximizing reuse is needed to make sure we don't
6113 run out of reload regs. Suppose we have three reloads, and
6114 reloads A and B can share regs. These need two regs.
6115 Suppose A and B are given different regs.
6116 That leaves none for C. */
6117 for (pass
= 0; pass
< 3; pass
++)
6119 /* I is the index in spill_regs.
6120 We advance it round-robin between insns to use all spill regs
6121 equally, so that inherited reloads have a chance
6122 of leapfrogging each other. */
6126 for (count
= 0; count
< n_spills
; count
++)
6128 int rclass
= (int) rld
[r
].rclass
;
6134 regnum
= spill_regs
[i
];
6136 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
6139 /* We check reload_reg_used to make sure we
6140 don't clobber the return register. */
6141 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
6142 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
6143 rld
[r
].when_needed
, rld
[r
].in
,
6145 && TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regnum
)
6146 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
6147 /* Look first for regs to share, then for unshared. But
6148 don't share regs used for inherited reloads; they are
6149 the ones we want to preserve. */
6151 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6153 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
6156 int nr
= hard_regno_nregs
[regnum
][rld
[r
].mode
];
6158 /* During the second pass we want to avoid reload registers
6159 which are "bad" for this reload. */
6161 && ira_bad_reload_regno (regnum
, rld
[r
].in
, rld
[r
].out
))
6164 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6165 (on 68000) got us two FP regs. If NR is 1,
6166 we would reject both of them. */
6169 /* If we need only one reg, we have already won. */
6172 /* But reject a single reg if we demand a group. */
6177 /* Otherwise check that as many consecutive regs as we need
6178 are available here. */
6181 int regno
= regnum
+ nr
- 1;
6182 if (!(TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
)
6183 && spill_reg_order
[regno
] >= 0
6184 && reload_reg_free_p (regno
, rld
[r
].opnum
,
6185 rld
[r
].when_needed
)))
6194 /* If we found something on the current pass, omit later passes. */
6195 if (count
< n_spills
)
6199 /* We should have found a spill register by now. */
6200 if (count
>= n_spills
)
6203 /* I is the index in SPILL_REG_RTX of the reload register we are to
6204 allocate. Get an rtx for it and find its register number. */
6206 return set_reload_reg (i
, r
);
6209 /* Initialize all the tables needed to allocate reload registers.
6210 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6211 is the array we use to restore the reg_rtx field for every reload. */
6214 choose_reload_regs_init (struct insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
6218 for (i
= 0; i
< n_reloads
; i
++)
6219 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
6221 memset (reload_inherited
, 0, MAX_RELOADS
);
6222 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
6223 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
6225 CLEAR_HARD_REG_SET (reload_reg_used
);
6226 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
6227 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
6228 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
6229 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
6230 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
6232 CLEAR_HARD_REG_SET (reg_used_in_insn
);
6235 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
6236 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6237 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
6238 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6239 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
6240 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
6243 for (i
= 0; i
< reload_n_operands
; i
++)
6245 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
6246 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
6247 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
6248 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
6249 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
6250 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
6253 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
6255 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
6257 for (i
= 0; i
< n_reloads
; i
++)
6258 /* If we have already decided to use a certain register,
6259 don't use it in another way. */
6261 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
6262 rld
[i
].when_needed
, rld
[i
].mode
);
6265 /* Assign hard reg targets for the pseudo-registers we must reload
6266 into hard regs for this insn.
6267 Also output the instructions to copy them in and out of the hard regs.
6269 For machines with register classes, we are responsible for
6270 finding a reload reg in the proper class. */
6273 choose_reload_regs (struct insn_chain
*chain
)
6275 rtx insn
= chain
->insn
;
6277 unsigned int max_group_size
= 1;
6278 enum reg_class group_class
= NO_REGS
;
6279 int pass
, win
, inheritance
;
6281 rtx save_reload_reg_rtx
[MAX_RELOADS
];
6283 /* In order to be certain of getting the registers we need,
6284 we must sort the reloads into order of increasing register class.
6285 Then our grabbing of reload registers will parallel the process
6286 that provided the reload registers.
6288 Also note whether any of the reloads wants a consecutive group of regs.
6289 If so, record the maximum size of the group desired and what
6290 register class contains all the groups needed by this insn. */
6292 for (j
= 0; j
< n_reloads
; j
++)
6294 reload_order
[j
] = j
;
6295 if (rld
[j
].reg_rtx
!= NULL_RTX
)
6297 gcc_assert (REG_P (rld
[j
].reg_rtx
)
6298 && HARD_REGISTER_P (rld
[j
].reg_rtx
));
6299 reload_spill_index
[j
] = REGNO (rld
[j
].reg_rtx
);
6302 reload_spill_index
[j
] = -1;
6304 if (rld
[j
].nregs
> 1)
6306 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
6308 = reg_class_superunion
[(int) rld
[j
].rclass
][(int) group_class
];
6311 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
6315 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
6317 /* If -O, try first with inheritance, then turning it off.
6318 If not -O, don't do inheritance.
6319 Using inheritance when not optimizing leads to paradoxes
6320 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6321 because one side of the comparison might be inherited. */
6323 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
6325 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6327 /* Process the reloads in order of preference just found.
6328 Beyond this point, subregs can be found in reload_reg_rtx.
6330 This used to look for an existing reloaded home for all of the
6331 reloads, and only then perform any new reloads. But that could lose
6332 if the reloads were done out of reg-class order because a later
6333 reload with a looser constraint might have an old home in a register
6334 needed by an earlier reload with a tighter constraint.
6336 To solve this, we make two passes over the reloads, in the order
6337 described above. In the first pass we try to inherit a reload
6338 from a previous insn. If there is a later reload that needs a
6339 class that is a proper subset of the class being processed, we must
6340 also allocate a spill register during the first pass.
6342 Then make a second pass over the reloads to allocate any reloads
6343 that haven't been given registers yet. */
6345 for (j
= 0; j
< n_reloads
; j
++)
6347 int r
= reload_order
[j
];
6348 rtx search_equiv
= NULL_RTX
;
6350 /* Ignore reloads that got marked inoperative. */
6351 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
6352 && ! rld
[r
].secondary_p
)
6355 /* If find_reloads chose to use reload_in or reload_out as a reload
6356 register, we don't need to chose one. Otherwise, try even if it
6357 found one since we might save an insn if we find the value lying
6359 Try also when reload_in is a pseudo without a hard reg. */
6360 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
6361 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
6362 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
6363 && !MEM_P (rld
[r
].in
)
6364 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
6367 #if 0 /* No longer needed for correct operation.
6368 It might give better code, or might not; worth an experiment? */
6369 /* If this is an optional reload, we can't inherit from earlier insns
6370 until we are sure that any non-optional reloads have been allocated.
6371 The following code takes advantage of the fact that optional reloads
6372 are at the end of reload_order. */
6373 if (rld
[r
].optional
!= 0)
6374 for (i
= 0; i
< j
; i
++)
6375 if ((rld
[reload_order
[i
]].out
!= 0
6376 || rld
[reload_order
[i
]].in
!= 0
6377 || rld
[reload_order
[i
]].secondary_p
)
6378 && ! rld
[reload_order
[i
]].optional
6379 && rld
[reload_order
[i
]].reg_rtx
== 0)
6380 allocate_reload_reg (chain
, reload_order
[i
], 0);
6383 /* First see if this pseudo is already available as reloaded
6384 for a previous insn. We cannot try to inherit for reloads
6385 that are smaller than the maximum number of registers needed
6386 for groups unless the register we would allocate cannot be used
6389 We could check here to see if this is a secondary reload for
6390 an object that is already in a register of the desired class.
6391 This would avoid the need for the secondary reload register.
6392 But this is complex because we can't easily determine what
6393 objects might want to be loaded via this reload. So let a
6394 register be allocated here. In `emit_reload_insns' we suppress
6395 one of the loads in the case described above. */
6401 enum machine_mode mode
= VOIDmode
;
6405 else if (REG_P (rld
[r
].in
))
6407 regno
= REGNO (rld
[r
].in
);
6408 mode
= GET_MODE (rld
[r
].in
);
6410 else if (REG_P (rld
[r
].in_reg
))
6412 regno
= REGNO (rld
[r
].in_reg
);
6413 mode
= GET_MODE (rld
[r
].in_reg
);
6415 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
6416 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
6418 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
6419 if (regno
< FIRST_PSEUDO_REGISTER
)
6420 regno
= subreg_regno (rld
[r
].in_reg
);
6422 byte
= SUBREG_BYTE (rld
[r
].in_reg
);
6423 mode
= GET_MODE (rld
[r
].in_reg
);
6426 else if (GET_RTX_CLASS (GET_CODE (rld
[r
].in_reg
)) == RTX_AUTOINC
6427 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
6429 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
6430 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
6431 rld
[r
].out
= rld
[r
].in
;
6435 /* This won't work, since REGNO can be a pseudo reg number.
6436 Also, it takes much more hair to keep track of all the things
6437 that can invalidate an inherited reload of part of a pseudoreg. */
6438 else if (GET_CODE (rld
[r
].in
) == SUBREG
6439 && REG_P (SUBREG_REG (rld
[r
].in
)))
6440 regno
= subreg_regno (rld
[r
].in
);
6444 && reg_last_reload_reg
[regno
] != 0
6445 #ifdef CANNOT_CHANGE_MODE_CLASS
6446 /* Verify that the register it's in can be used in
6448 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg
[regno
]),
6449 GET_MODE (reg_last_reload_reg
[regno
]),
6454 enum reg_class rclass
= rld
[r
].rclass
, last_class
;
6455 rtx last_reg
= reg_last_reload_reg
[regno
];
6456 enum machine_mode need_mode
;
6458 i
= REGNO (last_reg
);
6459 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
6460 last_class
= REGNO_REG_CLASS (i
);
6466 = smallest_mode_for_size
6467 (GET_MODE_BITSIZE (mode
) + byte
* BITS_PER_UNIT
,
6468 GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
6469 ? MODE_INT
: GET_MODE_CLASS (mode
));
6471 if ((GET_MODE_SIZE (GET_MODE (last_reg
))
6472 >= GET_MODE_SIZE (need_mode
))
6473 && reg_reloaded_contents
[i
] == regno
6474 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
6475 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
6476 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) rclass
], i
)
6477 /* Even if we can't use this register as a reload
6478 register, we might use it for reload_override_in,
6479 if copying it to the desired class is cheap
6481 || ((register_move_cost (mode
, last_class
, rclass
)
6482 < memory_move_cost (mode
, rclass
, true))
6483 && (secondary_reload_class (1, rclass
, mode
,
6486 #ifdef SECONDARY_MEMORY_NEEDED
6487 && ! SECONDARY_MEMORY_NEEDED (last_class
, rclass
,
6492 && (rld
[r
].nregs
== max_group_size
6493 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
6495 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
6496 rld
[r
].when_needed
, rld
[r
].in
,
6499 /* If a group is needed, verify that all the subsequent
6500 registers still have their values intact. */
6501 int nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
6504 for (k
= 1; k
< nr
; k
++)
6505 if (reg_reloaded_contents
[i
+ k
] != regno
6506 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
6514 last_reg
= (GET_MODE (last_reg
) == mode
6515 ? last_reg
: gen_rtx_REG (mode
, i
));
6518 for (k
= 0; k
< nr
; k
++)
6519 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6522 /* We found a register that contains the
6523 value we need. If this register is the
6524 same as an `earlyclobber' operand of the
6525 current insn, just mark it as a place to
6526 reload from since we can't use it as the
6527 reload register itself. */
6529 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
6530 if (reg_overlap_mentioned_for_reload_p
6531 (reg_last_reload_reg
[regno
],
6532 reload_earlyclobbers
[i1
]))
6535 if (i1
!= n_earlyclobbers
6536 || ! (free_for_value_p (i
, rld
[r
].mode
,
6538 rld
[r
].when_needed
, rld
[r
].in
,
6540 /* Don't use it if we'd clobber a pseudo reg. */
6541 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
6543 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
6544 /* Don't clobber the frame pointer. */
6545 || (i
== HARD_FRAME_POINTER_REGNUM
6546 && frame_pointer_needed
6548 /* Don't really use the inherited spill reg
6549 if we need it wider than we've got it. */
6550 || (GET_MODE_SIZE (rld
[r
].mode
)
6551 > GET_MODE_SIZE (mode
))
6554 /* If find_reloads chose reload_out as reload
6555 register, stay with it - that leaves the
6556 inherited register for subsequent reloads. */
6557 || (rld
[r
].out
&& rld
[r
].reg_rtx
6558 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
6560 if (! rld
[r
].optional
)
6562 reload_override_in
[r
] = last_reg
;
6563 reload_inheritance_insn
[r
]
6564 = reg_reloaded_insn
[i
];
6570 /* We can use this as a reload reg. */
6571 /* Mark the register as in use for this part of
6573 mark_reload_reg_in_use (i
,
6577 rld
[r
].reg_rtx
= last_reg
;
6578 reload_inherited
[r
] = 1;
6579 reload_inheritance_insn
[r
]
6580 = reg_reloaded_insn
[i
];
6581 reload_spill_index
[r
] = i
;
6582 for (k
= 0; k
< nr
; k
++)
6583 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6591 /* Here's another way to see if the value is already lying around. */
6594 && ! reload_inherited
[r
]
6596 && (CONSTANT_P (rld
[r
].in
)
6597 || GET_CODE (rld
[r
].in
) == PLUS
6598 || REG_P (rld
[r
].in
)
6599 || MEM_P (rld
[r
].in
))
6600 && (rld
[r
].nregs
== max_group_size
6601 || ! reg_classes_intersect_p (rld
[r
].rclass
, group_class
)))
6602 search_equiv
= rld
[r
].in
;
6603 /* If this is an output reload from a simple move insn, look
6604 if an equivalence for the input is available. */
6605 else if (inheritance
&& rld
[r
].in
== 0 && rld
[r
].out
!= 0)
6607 rtx set
= single_set (insn
);
6610 && rtx_equal_p (rld
[r
].out
, SET_DEST (set
))
6611 && CONSTANT_P (SET_SRC (set
)))
6612 search_equiv
= SET_SRC (set
);
6618 = find_equiv_reg (search_equiv
, insn
, rld
[r
].rclass
,
6619 -1, NULL
, 0, rld
[r
].mode
);
6625 regno
= REGNO (equiv
);
6628 /* This must be a SUBREG of a hard register.
6629 Make a new REG since this might be used in an
6630 address and not all machines support SUBREGs
6632 gcc_assert (GET_CODE (equiv
) == SUBREG
);
6633 regno
= subreg_regno (equiv
);
6634 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
6635 /* If we choose EQUIV as the reload register, but the
6636 loop below decides to cancel the inheritance, we'll
6637 end up reloading EQUIV in rld[r].mode, not the mode
6638 it had originally. That isn't safe when EQUIV isn't
6639 available as a spill register since its value might
6640 still be live at this point. */
6641 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
6642 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
6647 /* If we found a spill reg, reject it unless it is free
6648 and of the desired class. */
6652 int bad_for_class
= 0;
6653 int max_regno
= regno
+ rld
[r
].nregs
;
6655 for (i
= regno
; i
< max_regno
; i
++)
6657 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6659 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6664 && ! free_for_value_p (regno
, rld
[r
].mode
,
6665 rld
[r
].opnum
, rld
[r
].when_needed
,
6666 rld
[r
].in
, rld
[r
].out
, r
, 1))
6671 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6674 /* We found a register that contains the value we need.
6675 If this register is the same as an `earlyclobber' operand
6676 of the current insn, just mark it as a place to reload from
6677 since we can't use it as the reload register itself. */
6680 for (i
= 0; i
< n_earlyclobbers
; i
++)
6681 if (reg_overlap_mentioned_for_reload_p (equiv
,
6682 reload_earlyclobbers
[i
]))
6684 if (! rld
[r
].optional
)
6685 reload_override_in
[r
] = equiv
;
6690 /* If the equiv register we have found is explicitly clobbered
6691 in the current insn, it depends on the reload type if we
6692 can use it, use it for reload_override_in, or not at all.
6693 In particular, we then can't use EQUIV for a
6694 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6698 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 2))
6699 switch (rld
[r
].when_needed
)
6701 case RELOAD_FOR_OTHER_ADDRESS
:
6702 case RELOAD_FOR_INPADDR_ADDRESS
:
6703 case RELOAD_FOR_INPUT_ADDRESS
:
6704 case RELOAD_FOR_OPADDR_ADDR
:
6707 case RELOAD_FOR_INPUT
:
6708 case RELOAD_FOR_OPERAND_ADDRESS
:
6709 if (! rld
[r
].optional
)
6710 reload_override_in
[r
] = equiv
;
6716 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
6717 switch (rld
[r
].when_needed
)
6719 case RELOAD_FOR_OTHER_ADDRESS
:
6720 case RELOAD_FOR_INPADDR_ADDRESS
:
6721 case RELOAD_FOR_INPUT_ADDRESS
:
6722 case RELOAD_FOR_OPADDR_ADDR
:
6723 case RELOAD_FOR_OPERAND_ADDRESS
:
6724 case RELOAD_FOR_INPUT
:
6727 if (! rld
[r
].optional
)
6728 reload_override_in
[r
] = equiv
;
6736 /* If we found an equivalent reg, say no code need be generated
6737 to load it, and use it as our reload reg. */
6739 && (regno
!= HARD_FRAME_POINTER_REGNUM
6740 || !frame_pointer_needed
))
6742 int nr
= hard_regno_nregs
[regno
][rld
[r
].mode
];
6744 rld
[r
].reg_rtx
= equiv
;
6745 reload_spill_index
[r
] = regno
;
6746 reload_inherited
[r
] = 1;
6748 /* If reg_reloaded_valid is not set for this register,
6749 there might be a stale spill_reg_store lying around.
6750 We must clear it, since otherwise emit_reload_insns
6751 might delete the store. */
6752 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6753 spill_reg_store
[regno
] = NULL_RTX
;
6754 /* If any of the hard registers in EQUIV are spill
6755 registers, mark them as in use for this insn. */
6756 for (k
= 0; k
< nr
; k
++)
6758 i
= spill_reg_order
[regno
+ k
];
6761 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
6764 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6771 /* If we found a register to use already, or if this is an optional
6772 reload, we are done. */
6773 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
6777 /* No longer needed for correct operation. Might or might
6778 not give better code on the average. Want to experiment? */
6780 /* See if there is a later reload that has a class different from our
6781 class that intersects our class or that requires less register
6782 than our reload. If so, we must allocate a register to this
6783 reload now, since that reload might inherit a previous reload
6784 and take the only available register in our class. Don't do this
6785 for optional reloads since they will force all previous reloads
6786 to be allocated. Also don't do this for reloads that have been
6789 for (i
= j
+ 1; i
< n_reloads
; i
++)
6791 int s
= reload_order
[i
];
6793 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
6794 && ! rld
[s
].secondary_p
)
6798 if ((rld
[s
].rclass
!= rld
[r
].rclass
6799 && reg_classes_intersect_p (rld
[r
].rclass
,
6801 || rld
[s
].nregs
< rld
[r
].nregs
)
6808 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
6812 /* Now allocate reload registers for anything non-optional that
6813 didn't get one yet. */
6814 for (j
= 0; j
< n_reloads
; j
++)
6816 int r
= reload_order
[j
];
6818 /* Ignore reloads that got marked inoperative. */
6819 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
6822 /* Skip reloads that already have a register allocated or are
6824 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
6827 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
6831 /* If that loop got all the way, we have won. */
6838 /* Loop around and try without any inheritance. */
6843 /* First undo everything done by the failed attempt
6844 to allocate with inheritance. */
6845 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6847 /* Some sanity tests to verify that the reloads found in the first
6848 pass are identical to the ones we have now. */
6849 gcc_assert (chain
->n_reloads
== n_reloads
);
6851 for (i
= 0; i
< n_reloads
; i
++)
6853 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
6855 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
6856 for (j
= 0; j
< n_spills
; j
++)
6857 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
6858 if (! set_reload_reg (j
, i
))
6859 failed_reload (chain
->insn
, i
);
6863 /* If we thought we could inherit a reload, because it seemed that
6864 nothing else wanted the same reload register earlier in the insn,
6865 verify that assumption, now that all reloads have been assigned.
6866 Likewise for reloads where reload_override_in has been set. */
6868 /* If doing expensive optimizations, do one preliminary pass that doesn't
6869 cancel any inheritance, but removes reloads that have been needed only
6870 for reloads that we know can be inherited. */
6871 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
6873 for (j
= 0; j
< n_reloads
; j
++)
6875 int r
= reload_order
[j
];
6877 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
6878 check_reg
= rld
[r
].reg_rtx
;
6879 else if (reload_override_in
[r
]
6880 && (REG_P (reload_override_in
[r
])
6881 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
6882 check_reg
= reload_override_in
[r
];
6885 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
6886 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
6887 (reload_inherited
[r
]
6888 ? rld
[r
].out
: const0_rtx
),
6893 reload_inherited
[r
] = 0;
6894 reload_override_in
[r
] = 0;
6896 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6897 reload_override_in, then we do not need its related
6898 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6899 likewise for other reload types.
6900 We handle this by removing a reload when its only replacement
6901 is mentioned in reload_in of the reload we are going to inherit.
6902 A special case are auto_inc expressions; even if the input is
6903 inherited, we still need the address for the output. We can
6904 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6905 If we succeeded removing some reload and we are doing a preliminary
6906 pass just to remove such reloads, make another pass, since the
6907 removal of one reload might allow us to inherit another one. */
6909 && rld
[r
].out
!= rld
[r
].in
6910 && remove_address_replacements (rld
[r
].in
) && pass
)
6915 /* Now that reload_override_in is known valid,
6916 actually override reload_in. */
6917 for (j
= 0; j
< n_reloads
; j
++)
6918 if (reload_override_in
[j
])
6919 rld
[j
].in
= reload_override_in
[j
];
6921 /* If this reload won't be done because it has been canceled or is
6922 optional and not inherited, clear reload_reg_rtx so other
6923 routines (such as subst_reloads) don't get confused. */
6924 for (j
= 0; j
< n_reloads
; j
++)
6925 if (rld
[j
].reg_rtx
!= 0
6926 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
6927 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
6928 && ! rld
[j
].secondary_p
)))
6930 int regno
= true_regnum (rld
[j
].reg_rtx
);
6932 if (spill_reg_order
[regno
] >= 0)
6933 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
6934 rld
[j
].when_needed
, rld
[j
].mode
);
6936 reload_spill_index
[j
] = -1;
6939 /* Record which pseudos and which spill regs have output reloads. */
6940 for (j
= 0; j
< n_reloads
; j
++)
6942 int r
= reload_order
[j
];
6944 i
= reload_spill_index
[r
];
6946 /* I is nonneg if this reload uses a register.
6947 If rld[r].reg_rtx is 0, this is an optional reload
6948 that we opted to ignore. */
6949 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
6950 && rld
[r
].reg_rtx
!= 0)
6952 int nregno
= REGNO (rld
[r
].out_reg
);
6955 if (nregno
< FIRST_PSEUDO_REGISTER
)
6956 nr
= hard_regno_nregs
[nregno
][rld
[r
].mode
];
6959 SET_REGNO_REG_SET (®_has_output_reload
,
6964 nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
6966 SET_HARD_REG_BIT (reg_is_output_reload
, i
+ nr
);
6969 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
6970 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
6971 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
6976 /* Deallocate the reload register for reload R. This is called from
6977 remove_address_replacements. */
6980 deallocate_reload_reg (int r
)
6984 if (! rld
[r
].reg_rtx
)
6986 regno
= true_regnum (rld
[r
].reg_rtx
);
6988 if (spill_reg_order
[regno
] >= 0)
6989 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
6991 reload_spill_index
[r
] = -1;
6994 /* These arrays are filled by emit_reload_insns and its subroutines. */
6995 static rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
6996 static rtx other_input_address_reload_insns
= 0;
6997 static rtx other_input_reload_insns
= 0;
6998 static rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
6999 static rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7000 static rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
7001 static rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
7002 static rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7003 static rtx operand_reload_insns
= 0;
7004 static rtx other_operand_reload_insns
= 0;
7005 static rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
7007 /* Values to be put in spill_reg_store are put here first. */
7008 static rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
7009 static HARD_REG_SET reg_reloaded_died
;
7011 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7012 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7013 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7014 adjusted register, and return true. Otherwise, return false. */
7016 reload_adjust_reg_for_temp (rtx
*reload_reg
, rtx alt_reload_reg
,
7017 enum reg_class new_class
,
7018 enum machine_mode new_mode
)
7023 for (reg
= *reload_reg
; reg
; reg
= alt_reload_reg
, alt_reload_reg
= 0)
7025 unsigned regno
= REGNO (reg
);
7027 if (!TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
], regno
))
7029 if (GET_MODE (reg
) != new_mode
)
7031 if (!HARD_REGNO_MODE_OK (regno
, new_mode
))
7033 if (hard_regno_nregs
[regno
][new_mode
]
7034 > hard_regno_nregs
[regno
][GET_MODE (reg
)])
7036 reg
= reload_adjust_reg_for_mode (reg
, new_mode
);
7044 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7045 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7046 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7047 adjusted register, and return true. Otherwise, return false. */
7049 reload_adjust_reg_for_icode (rtx
*reload_reg
, rtx alt_reload_reg
,
7050 enum insn_code icode
)
7053 enum reg_class new_class
= scratch_reload_class (icode
);
7054 enum machine_mode new_mode
= insn_data
[(int) icode
].operand
[2].mode
;
7056 return reload_adjust_reg_for_temp (reload_reg
, alt_reload_reg
,
7057 new_class
, new_mode
);
7060 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7061 has the number J. OLD contains the value to be used as input. */
7064 emit_input_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7067 rtx insn
= chain
->insn
;
7069 rtx oldequiv_reg
= 0;
7072 enum machine_mode mode
;
7075 /* delete_output_reload is only invoked properly if old contains
7076 the original pseudo register. Since this is replaced with a
7077 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7078 find the pseudo in RELOAD_IN_REG. */
7079 if (reload_override_in
[j
]
7080 && REG_P (rl
->in_reg
))
7087 else if (REG_P (oldequiv
))
7088 oldequiv_reg
= oldequiv
;
7089 else if (GET_CODE (oldequiv
) == SUBREG
)
7090 oldequiv_reg
= SUBREG_REG (oldequiv
);
7092 reloadreg
= reload_reg_rtx_for_input
[j
];
7093 mode
= GET_MODE (reloadreg
);
7095 /* If we are reloading from a register that was recently stored in
7096 with an output-reload, see if we can prove there was
7097 actually no need to store the old value in it. */
7099 if (optimize
&& REG_P (oldequiv
)
7100 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
7101 && spill_reg_store
[REGNO (oldequiv
)]
7103 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
7104 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
7106 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
7108 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7111 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
7112 oldequiv
= SUBREG_REG (oldequiv
);
7113 if (GET_MODE (oldequiv
) != VOIDmode
7114 && mode
!= GET_MODE (oldequiv
))
7115 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
7117 /* Switch to the right place to emit the reload insns. */
7118 switch (rl
->when_needed
)
7121 where
= &other_input_reload_insns
;
7123 case RELOAD_FOR_INPUT
:
7124 where
= &input_reload_insns
[rl
->opnum
];
7126 case RELOAD_FOR_INPUT_ADDRESS
:
7127 where
= &input_address_reload_insns
[rl
->opnum
];
7129 case RELOAD_FOR_INPADDR_ADDRESS
:
7130 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
7132 case RELOAD_FOR_OUTPUT_ADDRESS
:
7133 where
= &output_address_reload_insns
[rl
->opnum
];
7135 case RELOAD_FOR_OUTADDR_ADDRESS
:
7136 where
= &outaddr_address_reload_insns
[rl
->opnum
];
7138 case RELOAD_FOR_OPERAND_ADDRESS
:
7139 where
= &operand_reload_insns
;
7141 case RELOAD_FOR_OPADDR_ADDR
:
7142 where
= &other_operand_reload_insns
;
7144 case RELOAD_FOR_OTHER_ADDRESS
:
7145 where
= &other_input_address_reload_insns
;
7151 push_to_sequence (*where
);
7153 /* Auto-increment addresses must be reloaded in a special way. */
7154 if (rl
->out
&& ! rl
->out_reg
)
7156 /* We are not going to bother supporting the case where a
7157 incremented register can't be copied directly from
7158 OLDEQUIV since this seems highly unlikely. */
7159 gcc_assert (rl
->secondary_in_reload
< 0);
7161 if (reload_inherited
[j
])
7162 oldequiv
= reloadreg
;
7164 old
= XEXP (rl
->in_reg
, 0);
7166 if (optimize
&& REG_P (oldequiv
)
7167 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
7168 && spill_reg_store
[REGNO (oldequiv
)]
7170 && (dead_or_set_p (insn
,
7171 spill_reg_stored_to
[REGNO (oldequiv
)])
7172 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
7174 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
7176 /* Prevent normal processing of this reload. */
7178 /* Output a special code sequence for this case. */
7179 new_spill_reg_store
[REGNO (reloadreg
)]
7180 = inc_for_reload (reloadreg
, oldequiv
, rl
->out
,
7184 /* If we are reloading a pseudo-register that was set by the previous
7185 insn, see if we can get rid of that pseudo-register entirely
7186 by redirecting the previous insn into our reload register. */
7188 else if (optimize
&& REG_P (old
)
7189 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7190 && dead_or_set_p (insn
, old
)
7191 /* This is unsafe if some other reload
7192 uses the same reg first. */
7193 && ! conflicts_with_override (reloadreg
)
7194 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
7195 rl
->when_needed
, old
, rl
->out
, j
, 0))
7197 rtx temp
= PREV_INSN (insn
);
7198 while (temp
&& (NOTE_P (temp
) || DEBUG_INSN_P (temp
)))
7199 temp
= PREV_INSN (temp
);
7201 && NONJUMP_INSN_P (temp
)
7202 && GET_CODE (PATTERN (temp
)) == SET
7203 && SET_DEST (PATTERN (temp
)) == old
7204 /* Make sure we can access insn_operand_constraint. */
7205 && asm_noperands (PATTERN (temp
)) < 0
7206 /* This is unsafe if operand occurs more than once in current
7207 insn. Perhaps some occurrences aren't reloaded. */
7208 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
7210 rtx old
= SET_DEST (PATTERN (temp
));
7211 /* Store into the reload register instead of the pseudo. */
7212 SET_DEST (PATTERN (temp
)) = reloadreg
;
7214 /* Verify that resulting insn is valid. */
7215 extract_insn (temp
);
7216 if (constrain_operands (1))
7218 /* If the previous insn is an output reload, the source is
7219 a reload register, and its spill_reg_store entry will
7220 contain the previous destination. This is now
7222 if (REG_P (SET_SRC (PATTERN (temp
)))
7223 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
7225 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7226 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7229 /* If these are the only uses of the pseudo reg,
7230 pretend for GDB it lives in the reload reg we used. */
7231 if (REG_N_DEATHS (REGNO (old
)) == 1
7232 && REG_N_SETS (REGNO (old
)) == 1)
7234 reg_renumber
[REGNO (old
)] = REGNO (reloadreg
);
7235 if (ira_conflicts_p
)
7236 /* Inform IRA about the change. */
7237 ira_mark_allocation_change (REGNO (old
));
7238 alter_reg (REGNO (old
), -1, false);
7242 /* Adjust any debug insns between temp and insn. */
7243 while ((temp
= NEXT_INSN (temp
)) != insn
)
7244 if (DEBUG_INSN_P (temp
))
7245 replace_rtx (PATTERN (temp
), old
, reloadreg
);
7247 gcc_assert (NOTE_P (temp
));
7251 SET_DEST (PATTERN (temp
)) = old
;
7256 /* We can't do that, so output an insn to load RELOADREG. */
7258 /* If we have a secondary reload, pick up the secondary register
7259 and icode, if any. If OLDEQUIV and OLD are different or
7260 if this is an in-out reload, recompute whether or not we
7261 still need a secondary register and what the icode should
7262 be. If we still need a secondary register and the class or
7263 icode is different, go back to reloading from OLD if using
7264 OLDEQUIV means that we got the wrong type of register. We
7265 cannot have different class or icode due to an in-out reload
7266 because we don't make such reloads when both the input and
7267 output need secondary reload registers. */
7269 if (! special
&& rl
->secondary_in_reload
>= 0)
7271 rtx second_reload_reg
= 0;
7272 rtx third_reload_reg
= 0;
7273 int secondary_reload
= rl
->secondary_in_reload
;
7274 rtx real_oldequiv
= oldequiv
;
7277 enum insn_code icode
;
7278 enum insn_code tertiary_icode
= CODE_FOR_nothing
;
7280 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7281 and similarly for OLD.
7282 See comments in get_secondary_reload in reload.c. */
7283 /* If it is a pseudo that cannot be replaced with its
7284 equivalent MEM, we must fall back to reload_in, which
7285 will have all the necessary substitutions registered.
7286 Likewise for a pseudo that can't be replaced with its
7287 equivalent constant.
7289 Take extra care for subregs of such pseudos. Note that
7290 we cannot use reg_equiv_mem in this case because it is
7291 not in the right mode. */
7294 if (GET_CODE (tmp
) == SUBREG
)
7295 tmp
= SUBREG_REG (tmp
);
7297 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7298 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
7299 || reg_equiv_constant
[REGNO (tmp
)] != 0))
7301 if (! reg_equiv_mem
[REGNO (tmp
)]
7302 || num_not_at_initial_offset
7303 || GET_CODE (oldequiv
) == SUBREG
)
7304 real_oldequiv
= rl
->in
;
7306 real_oldequiv
= reg_equiv_mem
[REGNO (tmp
)];
7310 if (GET_CODE (tmp
) == SUBREG
)
7311 tmp
= SUBREG_REG (tmp
);
7313 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7314 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
7315 || reg_equiv_constant
[REGNO (tmp
)] != 0))
7317 if (! reg_equiv_mem
[REGNO (tmp
)]
7318 || num_not_at_initial_offset
7319 || GET_CODE (old
) == SUBREG
)
7322 real_old
= reg_equiv_mem
[REGNO (tmp
)];
7325 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
7326 if (rld
[secondary_reload
].secondary_in_reload
>= 0)
7328 int tertiary_reload
= rld
[secondary_reload
].secondary_in_reload
;
7330 third_reload_reg
= rld
[tertiary_reload
].reg_rtx
;
7331 tertiary_icode
= rld
[secondary_reload
].secondary_in_icode
;
7332 /* We'd have to add more code for quartary reloads. */
7333 gcc_assert (rld
[tertiary_reload
].secondary_in_reload
< 0);
7335 icode
= rl
->secondary_in_icode
;
7337 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
7338 || (rl
->in
!= 0 && rl
->out
!= 0))
7340 secondary_reload_info sri
, sri2
;
7341 enum reg_class new_class
, new_t_class
;
7343 sri
.icode
= CODE_FOR_nothing
;
7344 sri
.prev_sri
= NULL
;
7346 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7350 if (new_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
7351 second_reload_reg
= 0;
7352 else if (new_class
== NO_REGS
)
7354 if (reload_adjust_reg_for_icode (&second_reload_reg
,
7356 (enum insn_code
) sri
.icode
))
7358 icode
= (enum insn_code
) sri
.icode
;
7359 third_reload_reg
= 0;
7364 real_oldequiv
= real_old
;
7367 else if (sri
.icode
!= CODE_FOR_nothing
)
7368 /* We currently lack a way to express this in reloads. */
7372 sri2
.icode
= CODE_FOR_nothing
;
7373 sri2
.prev_sri
= &sri
;
7375 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7378 if (new_t_class
== NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7380 if (reload_adjust_reg_for_temp (&second_reload_reg
,
7384 third_reload_reg
= 0;
7385 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7390 real_oldequiv
= real_old
;
7393 else if (new_t_class
== NO_REGS
&& sri2
.icode
!= CODE_FOR_nothing
)
7395 rtx intermediate
= second_reload_reg
;
7397 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7399 && reload_adjust_reg_for_icode (&third_reload_reg
, NULL
,
7403 second_reload_reg
= intermediate
;
7404 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7409 real_oldequiv
= real_old
;
7412 else if (new_t_class
!= NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7414 rtx intermediate
= second_reload_reg
;
7416 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7418 && reload_adjust_reg_for_temp (&third_reload_reg
, NULL
,
7421 second_reload_reg
= intermediate
;
7422 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7427 real_oldequiv
= real_old
;
7432 /* This could be handled more intelligently too. */
7434 real_oldequiv
= real_old
;
7439 /* If we still need a secondary reload register, check
7440 to see if it is being used as a scratch or intermediate
7441 register and generate code appropriately. If we need
7442 a scratch register, use REAL_OLDEQUIV since the form of
7443 the insn may depend on the actual address if it is
7446 if (second_reload_reg
)
7448 if (icode
!= CODE_FOR_nothing
)
7450 /* We'd have to add extra code to handle this case. */
7451 gcc_assert (!third_reload_reg
);
7453 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
7454 second_reload_reg
));
7459 /* See if we need a scratch register to load the
7460 intermediate register (a tertiary reload). */
7461 if (tertiary_icode
!= CODE_FOR_nothing
)
7463 emit_insn ((GEN_FCN (tertiary_icode
)
7464 (second_reload_reg
, real_oldequiv
,
7465 third_reload_reg
)));
7467 else if (third_reload_reg
)
7469 gen_reload (third_reload_reg
, real_oldequiv
,
7472 gen_reload (second_reload_reg
, third_reload_reg
,
7477 gen_reload (second_reload_reg
, real_oldequiv
,
7481 oldequiv
= second_reload_reg
;
7486 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
7488 rtx real_oldequiv
= oldequiv
;
7490 if ((REG_P (oldequiv
)
7491 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
7492 && (reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0
7493 || reg_equiv_constant
[REGNO (oldequiv
)] != 0))
7494 || (GET_CODE (oldequiv
) == SUBREG
7495 && REG_P (SUBREG_REG (oldequiv
))
7496 && (REGNO (SUBREG_REG (oldequiv
))
7497 >= FIRST_PSEUDO_REGISTER
)
7498 && ((reg_equiv_memory_loc
7499 [REGNO (SUBREG_REG (oldequiv
))] != 0)
7500 || (reg_equiv_constant
7501 [REGNO (SUBREG_REG (oldequiv
))] != 0)))
7502 || (CONSTANT_P (oldequiv
)
7503 && (targetm
.preferred_reload_class (oldequiv
,
7504 REGNO_REG_CLASS (REGNO (reloadreg
)))
7506 real_oldequiv
= rl
->in
;
7507 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
7511 if (cfun
->can_throw_non_call_exceptions
)
7512 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7514 /* End this sequence. */
7515 *where
= get_insns ();
7518 /* Update reload_override_in so that delete_address_reloads_1
7519 can see the actual register usage. */
7521 reload_override_in
[j
] = oldequiv
;
7524 /* Generate insns to for the output reload RL, which is for the insn described
7525 by CHAIN and has the number J. */
7527 emit_output_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7531 rtx insn
= chain
->insn
;
7534 enum machine_mode mode
;
7538 if (rl
->when_needed
== RELOAD_OTHER
)
7541 push_to_sequence (output_reload_insns
[rl
->opnum
]);
7543 rl_reg_rtx
= reload_reg_rtx_for_output
[j
];
7544 mode
= GET_MODE (rl_reg_rtx
);
7546 reloadreg
= rl_reg_rtx
;
7548 /* If we need two reload regs, set RELOADREG to the intermediate
7549 one, since it will be stored into OLD. We might need a secondary
7550 register only for an input reload, so check again here. */
7552 if (rl
->secondary_out_reload
>= 0)
7555 int secondary_reload
= rl
->secondary_out_reload
;
7556 int tertiary_reload
= rld
[secondary_reload
].secondary_out_reload
;
7558 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7559 && reg_equiv_mem
[REGNO (old
)] != 0)
7560 real_old
= reg_equiv_mem
[REGNO (old
)];
7562 if (secondary_reload_class (0, rl
->rclass
, mode
, real_old
) != NO_REGS
)
7564 rtx second_reloadreg
= reloadreg
;
7565 reloadreg
= rld
[secondary_reload
].reg_rtx
;
7567 /* See if RELOADREG is to be used as a scratch register
7568 or as an intermediate register. */
7569 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
7571 /* We'd have to add extra code to handle this case. */
7572 gcc_assert (tertiary_reload
< 0);
7574 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
7575 (real_old
, second_reloadreg
, reloadreg
)));
7580 /* See if we need both a scratch and intermediate reload
7583 enum insn_code tertiary_icode
7584 = rld
[secondary_reload
].secondary_out_icode
;
7586 /* We'd have to add more code for quartary reloads. */
7587 gcc_assert (tertiary_reload
< 0
7588 || rld
[tertiary_reload
].secondary_out_reload
< 0);
7590 if (GET_MODE (reloadreg
) != mode
)
7591 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
7593 if (tertiary_icode
!= CODE_FOR_nothing
)
7595 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7598 /* Copy primary reload reg to secondary reload reg.
7599 (Note that these have been swapped above, then
7600 secondary reload reg to OLD using our insn.) */
7602 /* If REAL_OLD is a paradoxical SUBREG, remove it
7603 and try to put the opposite SUBREG on
7605 if (GET_CODE (real_old
) == SUBREG
7606 && (GET_MODE_SIZE (GET_MODE (real_old
))
7607 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old
))))
7608 && 0 != (tem
= gen_lowpart_common
7609 (GET_MODE (SUBREG_REG (real_old
)),
7611 real_old
= SUBREG_REG (real_old
), reloadreg
= tem
;
7613 gen_reload (reloadreg
, second_reloadreg
,
7614 rl
->opnum
, rl
->when_needed
);
7615 emit_insn ((GEN_FCN (tertiary_icode
)
7616 (real_old
, reloadreg
, third_reloadreg
)));
7622 /* Copy between the reload regs here and then to
7625 gen_reload (reloadreg
, second_reloadreg
,
7626 rl
->opnum
, rl
->when_needed
);
7627 if (tertiary_reload
>= 0)
7629 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7631 gen_reload (third_reloadreg
, reloadreg
,
7632 rl
->opnum
, rl
->when_needed
);
7633 reloadreg
= third_reloadreg
;
7640 /* Output the last reload insn. */
7645 /* Don't output the last reload if OLD is not the dest of
7646 INSN and is in the src and is clobbered by INSN. */
7647 if (! flag_expensive_optimizations
7649 || !(set
= single_set (insn
))
7650 || rtx_equal_p (old
, SET_DEST (set
))
7651 || !reg_mentioned_p (old
, SET_SRC (set
))
7652 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
7653 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
7654 gen_reload (old
, reloadreg
, rl
->opnum
,
7658 /* Look at all insns we emitted, just to be safe. */
7659 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7662 rtx pat
= PATTERN (p
);
7664 /* If this output reload doesn't come from a spill reg,
7665 clear any memory of reloaded copies of the pseudo reg.
7666 If this output reload comes from a spill reg,
7667 reg_has_output_reload will make this do nothing. */
7668 note_stores (pat
, forget_old_reloads_1
, NULL
);
7670 if (reg_mentioned_p (rl_reg_rtx
, pat
))
7672 rtx set
= single_set (insn
);
7673 if (reload_spill_index
[j
] < 0
7675 && SET_SRC (set
) == rl_reg_rtx
)
7677 int src
= REGNO (SET_SRC (set
));
7679 reload_spill_index
[j
] = src
;
7680 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7681 if (find_regno_note (insn
, REG_DEAD
, src
))
7682 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7684 if (HARD_REGISTER_P (rl_reg_rtx
))
7686 int s
= rl
->secondary_out_reload
;
7687 set
= single_set (p
);
7688 /* If this reload copies only to the secondary reload
7689 register, the secondary reload does the actual
7691 if (s
>= 0 && set
== NULL_RTX
)
7692 /* We can't tell what function the secondary reload
7693 has and where the actual store to the pseudo is
7694 made; leave new_spill_reg_store alone. */
7697 && SET_SRC (set
) == rl_reg_rtx
7698 && SET_DEST (set
) == rld
[s
].reg_rtx
)
7700 /* Usually the next instruction will be the
7701 secondary reload insn; if we can confirm
7702 that it is, setting new_spill_reg_store to
7703 that insn will allow an extra optimization. */
7704 rtx s_reg
= rld
[s
].reg_rtx
;
7705 rtx next
= NEXT_INSN (p
);
7706 rld
[s
].out
= rl
->out
;
7707 rld
[s
].out_reg
= rl
->out_reg
;
7708 set
= single_set (next
);
7709 if (set
&& SET_SRC (set
) == s_reg
7710 && ! new_spill_reg_store
[REGNO (s_reg
)])
7712 SET_HARD_REG_BIT (reg_is_output_reload
,
7714 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7718 new_spill_reg_store
[REGNO (rl_reg_rtx
)] = p
;
7723 if (rl
->when_needed
== RELOAD_OTHER
)
7725 emit_insn (other_output_reload_insns
[rl
->opnum
]);
7726 other_output_reload_insns
[rl
->opnum
] = get_insns ();
7729 output_reload_insns
[rl
->opnum
] = get_insns ();
7731 if (cfun
->can_throw_non_call_exceptions
)
7732 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7737 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7738 and has the number J. */
7740 do_input_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7742 rtx insn
= chain
->insn
;
7743 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
7744 ? rl
->in_reg
: rl
->in
);
7745 rtx reg_rtx
= rl
->reg_rtx
;
7749 enum machine_mode mode
;
7751 /* Determine the mode to reload in.
7752 This is very tricky because we have three to choose from.
7753 There is the mode the insn operand wants (rl->inmode).
7754 There is the mode of the reload register RELOADREG.
7755 There is the intrinsic mode of the operand, which we could find
7756 by stripping some SUBREGs.
7757 It turns out that RELOADREG's mode is irrelevant:
7758 we can change that arbitrarily.
7760 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7761 then the reload reg may not support QImode moves, so use SImode.
7762 If foo is in memory due to spilling a pseudo reg, this is safe,
7763 because the QImode value is in the least significant part of a
7764 slot big enough for a SImode. If foo is some other sort of
7765 memory reference, then it is impossible to reload this case,
7766 so previous passes had better make sure this never happens.
7768 Then consider a one-word union which has SImode and one of its
7769 members is a float, being fetched as (SUBREG:SF union:SI).
7770 We must fetch that as SFmode because we could be loading into
7771 a float-only register. In this case OLD's mode is correct.
7773 Consider an immediate integer: it has VOIDmode. Here we need
7774 to get a mode from something else.
7776 In some cases, there is a fourth mode, the operand's
7777 containing mode. If the insn specifies a containing mode for
7778 this operand, it overrides all others.
7780 I am not sure whether the algorithm here is always right,
7781 but it does the right things in those cases. */
7783 mode
= GET_MODE (old
);
7784 if (mode
== VOIDmode
)
7787 /* We cannot use gen_lowpart_common since it can do the wrong thing
7788 when REG_RTX has a multi-word mode. Note that REG_RTX must
7789 always be a REG here. */
7790 if (GET_MODE (reg_rtx
) != mode
)
7791 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7793 reload_reg_rtx_for_input
[j
] = reg_rtx
;
7796 /* AUTO_INC reloads need to be handled even if inherited. We got an
7797 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7798 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
7799 && ! rtx_equal_p (reg_rtx
, old
)
7801 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
7803 /* When inheriting a wider reload, we have a MEM in rl->in,
7804 e.g. inheriting a SImode output reload for
7805 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7806 if (optimize
&& reload_inherited
[j
] && rl
->in
7808 && MEM_P (rl
->in_reg
)
7809 && reload_spill_index
[j
] >= 0
7810 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
7811 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
7813 /* If we are reloading a register that was recently stored in with an
7814 output-reload, see if we can prove there was
7815 actually no need to store the old value in it. */
7818 && (reload_inherited
[j
] || reload_override_in
[j
])
7821 && spill_reg_store
[REGNO (reg_rtx
)] != 0
7823 /* There doesn't seem to be any reason to restrict this to pseudos
7824 and doing so loses in the case where we are copying from a
7825 register of the wrong class. */
7826 && !HARD_REGISTER_P (spill_reg_stored_to
[REGNO (reg_rtx
)])
7828 /* The insn might have already some references to stackslots
7829 replaced by MEMs, while reload_out_reg still names the
7831 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (reg_rtx
)])
7832 || rtx_equal_p (spill_reg_stored_to
[REGNO (reg_rtx
)], rl
->out_reg
)))
7833 delete_output_reload (insn
, j
, REGNO (reg_rtx
), reg_rtx
);
7836 /* Do output reloading for reload RL, which is for the insn described by
7837 CHAIN and has the number J.
7838 ??? At some point we need to support handling output reloads of
7839 JUMP_INSNs or insns that set cc0. */
7841 do_output_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7844 rtx insn
= chain
->insn
;
7845 /* If this is an output reload that stores something that is
7846 not loaded in this same reload, see if we can eliminate a previous
7848 rtx pseudo
= rl
->out_reg
;
7849 rtx reg_rtx
= rl
->reg_rtx
;
7851 if (rl
->out
&& reg_rtx
)
7853 enum machine_mode mode
;
7855 /* Determine the mode to reload in.
7856 See comments above (for input reloading). */
7857 mode
= GET_MODE (rl
->out
);
7858 if (mode
== VOIDmode
)
7860 /* VOIDmode should never happen for an output. */
7861 if (asm_noperands (PATTERN (insn
)) < 0)
7862 /* It's the compiler's fault. */
7863 fatal_insn ("VOIDmode on an output", insn
);
7864 error_for_asm (insn
, "output operand is constant in %<asm%>");
7865 /* Prevent crash--use something we know is valid. */
7867 rl
->out
= gen_rtx_REG (mode
, REGNO (reg_rtx
));
7869 if (GET_MODE (reg_rtx
) != mode
)
7870 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7872 reload_reg_rtx_for_output
[j
] = reg_rtx
;
7877 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
7878 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
7879 && reg_last_reload_reg
[REGNO (pseudo
)])
7881 int pseudo_no
= REGNO (pseudo
);
7882 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
7884 /* We don't need to test full validity of last_regno for
7885 inherit here; we only want to know if the store actually
7886 matches the pseudo. */
7887 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
7888 && reg_reloaded_contents
[last_regno
] == pseudo_no
7889 && spill_reg_store
[last_regno
]
7890 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
7891 delete_output_reload (insn
, j
, last_regno
, reg_rtx
);
7897 || rtx_equal_p (old
, reg_rtx
))
7900 /* An output operand that dies right away does need a reload,
7901 but need not be copied from it. Show the new location in the
7903 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
7904 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
7906 XEXP (note
, 0) = reg_rtx
;
7909 /* Likewise for a SUBREG of an operand that dies. */
7910 else if (GET_CODE (old
) == SUBREG
7911 && REG_P (SUBREG_REG (old
))
7912 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
7915 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
), reg_rtx
);
7918 else if (GET_CODE (old
) == SCRATCH
)
7919 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7920 but we don't want to make an output reload. */
7923 /* If is a JUMP_INSN, we can't support output reloads yet. */
7924 gcc_assert (NONJUMP_INSN_P (insn
));
7926 emit_output_reload_insns (chain
, rld
+ j
, j
);
7929 /* A reload copies values of MODE from register SRC to register DEST.
7930 Return true if it can be treated for inheritance purposes like a
7931 group of reloads, each one reloading a single hard register. The
7932 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7933 occupy the same number of hard registers. */
7936 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED
,
7937 int src ATTRIBUTE_UNUSED
,
7938 enum machine_mode mode ATTRIBUTE_UNUSED
)
7940 #ifdef CANNOT_CHANGE_MODE_CLASS
7941 return (!REG_CANNOT_CHANGE_MODE_P (dest
, mode
, reg_raw_mode
[dest
])
7942 && !REG_CANNOT_CHANGE_MODE_P (src
, mode
, reg_raw_mode
[src
]));
7948 /* Output insns to reload values in and out of the chosen reload regs. */
7951 emit_reload_insns (struct insn_chain
*chain
)
7953 rtx insn
= chain
->insn
;
7957 CLEAR_HARD_REG_SET (reg_reloaded_died
);
7959 for (j
= 0; j
< reload_n_operands
; j
++)
7960 input_reload_insns
[j
] = input_address_reload_insns
[j
]
7961 = inpaddr_address_reload_insns
[j
]
7962 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
7963 = outaddr_address_reload_insns
[j
]
7964 = other_output_reload_insns
[j
] = 0;
7965 other_input_address_reload_insns
= 0;
7966 other_input_reload_insns
= 0;
7967 operand_reload_insns
= 0;
7968 other_operand_reload_insns
= 0;
7970 /* Dump reloads into the dump file. */
7973 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
7974 debug_reload_to_stream (dump_file
);
7977 /* Now output the instructions to copy the data into and out of the
7978 reload registers. Do these in the order that the reloads were reported,
7979 since reloads of base and index registers precede reloads of operands
7980 and the operands may need the base and index registers reloaded. */
7982 for (j
= 0; j
< n_reloads
; j
++)
7984 if (rld
[j
].reg_rtx
&& HARD_REGISTER_P (rld
[j
].reg_rtx
))
7988 for (i
= REGNO (rld
[j
].reg_rtx
); i
< END_REGNO (rld
[j
].reg_rtx
); i
++)
7989 new_spill_reg_store
[i
] = 0;
7992 do_input_reload (chain
, rld
+ j
, j
);
7993 do_output_reload (chain
, rld
+ j
, j
);
7996 /* Now write all the insns we made for reloads in the order expected by
7997 the allocation functions. Prior to the insn being reloaded, we write
7998 the following reloads:
8000 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8002 RELOAD_OTHER reloads.
8004 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8005 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8006 RELOAD_FOR_INPUT reload for the operand.
8008 RELOAD_FOR_OPADDR_ADDRS reloads.
8010 RELOAD_FOR_OPERAND_ADDRESS reloads.
8012 After the insn being reloaded, we write the following:
8014 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8015 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8016 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8017 reloads for the operand. The RELOAD_OTHER output reloads are
8018 output in descending order by reload number. */
8020 emit_insn_before (other_input_address_reload_insns
, insn
);
8021 emit_insn_before (other_input_reload_insns
, insn
);
8023 for (j
= 0; j
< reload_n_operands
; j
++)
8025 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
8026 emit_insn_before (input_address_reload_insns
[j
], insn
);
8027 emit_insn_before (input_reload_insns
[j
], insn
);
8030 emit_insn_before (other_operand_reload_insns
, insn
);
8031 emit_insn_before (operand_reload_insns
, insn
);
8033 for (j
= 0; j
< reload_n_operands
; j
++)
8035 rtx x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
8036 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
8037 x
= emit_insn_after (output_reload_insns
[j
], x
);
8038 emit_insn_after (other_output_reload_insns
[j
], x
);
8041 /* For all the spill regs newly reloaded in this instruction,
8042 record what they were reloaded from, so subsequent instructions
8043 can inherit the reloads.
8045 Update spill_reg_store for the reloads of this insn.
8046 Copy the elements that were updated in the loop above. */
8048 for (j
= 0; j
< n_reloads
; j
++)
8050 int r
= reload_order
[j
];
8051 int i
= reload_spill_index
[r
];
8053 /* If this is a non-inherited input reload from a pseudo, we must
8054 clear any memory of a previous store to the same pseudo. Only do
8055 something if there will not be an output reload for the pseudo
8057 if (rld
[r
].in_reg
!= 0
8058 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
8060 rtx reg
= rld
[r
].in_reg
;
8062 if (GET_CODE (reg
) == SUBREG
)
8063 reg
= SUBREG_REG (reg
);
8066 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
8067 && !REGNO_REG_SET_P (®_has_output_reload
, REGNO (reg
)))
8069 int nregno
= REGNO (reg
);
8071 if (reg_last_reload_reg
[nregno
])
8073 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
8075 if (reg_reloaded_contents
[last_regno
] == nregno
)
8076 spill_reg_store
[last_regno
] = 0;
8081 /* I is nonneg if this reload used a register.
8082 If rld[r].reg_rtx is 0, this is an optional reload
8083 that we opted to ignore. */
8085 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
8087 int nr
= hard_regno_nregs
[i
][GET_MODE (rld
[r
].reg_rtx
)];
8090 /* For a multi register reload, we need to check if all or part
8091 of the value lives to the end. */
8092 for (k
= 0; k
< nr
; k
++)
8093 if (reload_reg_reaches_end_p (i
+ k
, rld
[r
].opnum
,
8094 rld
[r
].when_needed
))
8095 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
8097 /* Maybe the spill reg contains a copy of reload_out. */
8099 && (REG_P (rld
[r
].out
)
8103 || REG_P (rld
[r
].out_reg
)))
8106 enum machine_mode mode
;
8109 reg
= reload_reg_rtx_for_output
[r
];
8110 mode
= GET_MODE (reg
);
8111 regno
= REGNO (reg
);
8112 nregs
= hard_regno_nregs
[regno
][mode
];
8113 if (reload_regs_reach_end_p (regno
, nregs
, rld
[r
].opnum
,
8114 rld
[r
].when_needed
))
8116 rtx out
= (REG_P (rld
[r
].out
)
8120 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
8121 int out_regno
= REGNO (out
);
8122 int out_nregs
= (!HARD_REGISTER_NUM_P (out_regno
) ? 1
8123 : hard_regno_nregs
[out_regno
][mode
]);
8126 spill_reg_store
[regno
] = new_spill_reg_store
[regno
];
8127 spill_reg_stored_to
[regno
] = out
;
8128 reg_last_reload_reg
[out_regno
] = reg
;
8130 piecemeal
= (HARD_REGISTER_NUM_P (out_regno
)
8131 && nregs
== out_nregs
8132 && inherit_piecemeal_p (out_regno
, regno
, mode
));
8134 /* If OUT_REGNO is a hard register, it may occupy more than
8135 one register. If it does, say what is in the
8136 rest of the registers assuming that both registers
8137 agree on how many words the object takes. If not,
8138 invalidate the subsequent registers. */
8140 if (HARD_REGISTER_NUM_P (out_regno
))
8141 for (k
= 1; k
< out_nregs
; k
++)
8142 reg_last_reload_reg
[out_regno
+ k
]
8143 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8145 /* Now do the inverse operation. */
8146 for (k
= 0; k
< nregs
; k
++)
8148 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8149 reg_reloaded_contents
[regno
+ k
]
8150 = (!HARD_REGISTER_NUM_P (out_regno
) || !piecemeal
8153 reg_reloaded_insn
[regno
+ k
] = insn
;
8154 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8155 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8156 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8159 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8164 /* Maybe the spill reg contains a copy of reload_in. Only do
8165 something if there will not be an output reload for
8166 the register being reloaded. */
8167 else if (rld
[r
].out_reg
== 0
8169 && ((REG_P (rld
[r
].in
)
8170 && !HARD_REGISTER_P (rld
[r
].in
)
8171 && !REGNO_REG_SET_P (®_has_output_reload
,
8173 || (REG_P (rld
[r
].in_reg
)
8174 && !REGNO_REG_SET_P (®_has_output_reload
,
8175 REGNO (rld
[r
].in_reg
))))
8176 && !reg_set_p (reload_reg_rtx_for_input
[r
], PATTERN (insn
)))
8179 enum machine_mode mode
;
8182 reg
= reload_reg_rtx_for_input
[r
];
8183 mode
= GET_MODE (reg
);
8184 regno
= REGNO (reg
);
8185 nregs
= hard_regno_nregs
[regno
][mode
];
8186 if (reload_regs_reach_end_p (regno
, nregs
, rld
[r
].opnum
,
8187 rld
[r
].when_needed
))
8194 if (REG_P (rld
[r
].in
)
8195 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
8197 else if (REG_P (rld
[r
].in_reg
))
8200 in
= XEXP (rld
[r
].in_reg
, 0);
8201 in_regno
= REGNO (in
);
8203 in_nregs
= (!HARD_REGISTER_NUM_P (in_regno
) ? 1
8204 : hard_regno_nregs
[in_regno
][mode
]);
8206 reg_last_reload_reg
[in_regno
] = reg
;
8208 piecemeal
= (HARD_REGISTER_NUM_P (in_regno
)
8209 && nregs
== in_nregs
8210 && inherit_piecemeal_p (regno
, in_regno
, mode
));
8212 if (HARD_REGISTER_NUM_P (in_regno
))
8213 for (k
= 1; k
< in_nregs
; k
++)
8214 reg_last_reload_reg
[in_regno
+ k
]
8215 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8217 /* Unless we inherited this reload, show we haven't
8218 recently done a store.
8219 Previous stores of inherited auto_inc expressions
8220 also have to be discarded. */
8221 if (! reload_inherited
[r
]
8222 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
8223 spill_reg_store
[regno
] = 0;
8225 for (k
= 0; k
< nregs
; k
++)
8227 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8228 reg_reloaded_contents
[regno
+ k
]
8229 = (!HARD_REGISTER_NUM_P (in_regno
) || !piecemeal
8232 reg_reloaded_insn
[regno
+ k
] = insn
;
8233 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8234 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8235 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8238 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8245 /* The following if-statement was #if 0'd in 1.34 (or before...).
8246 It's reenabled in 1.35 because supposedly nothing else
8247 deals with this problem. */
8249 /* If a register gets output-reloaded from a non-spill register,
8250 that invalidates any previous reloaded copy of it.
8251 But forget_old_reloads_1 won't get to see it, because
8252 it thinks only about the original insn. So invalidate it here.
8253 Also do the same thing for RELOAD_OTHER constraints where the
8254 output is discarded. */
8256 && ((rld
[r
].out
!= 0
8257 && (REG_P (rld
[r
].out
)
8258 || (MEM_P (rld
[r
].out
)
8259 && REG_P (rld
[r
].out_reg
))))
8260 || (rld
[r
].out
== 0 && rld
[r
].out_reg
8261 && REG_P (rld
[r
].out_reg
))))
8263 rtx out
= ((rld
[r
].out
&& REG_P (rld
[r
].out
))
8264 ? rld
[r
].out
: rld
[r
].out_reg
);
8265 int out_regno
= REGNO (out
);
8266 enum machine_mode mode
= GET_MODE (out
);
8268 /* REG_RTX is now set or clobbered by the main instruction.
8269 As the comment above explains, forget_old_reloads_1 only
8270 sees the original instruction, and there is no guarantee
8271 that the original instruction also clobbered REG_RTX.
8272 For example, if find_reloads sees that the input side of
8273 a matched operand pair dies in this instruction, it may
8274 use the input register as the reload register.
8276 Calling forget_old_reloads_1 is a waste of effort if
8277 REG_RTX is also the output register.
8279 If we know that REG_RTX holds the value of a pseudo
8280 register, the code after the call will record that fact. */
8281 if (rld
[r
].reg_rtx
&& rld
[r
].reg_rtx
!= out
)
8282 forget_old_reloads_1 (rld
[r
].reg_rtx
, NULL_RTX
, NULL
);
8284 if (!HARD_REGISTER_NUM_P (out_regno
))
8286 rtx src_reg
, store_insn
= NULL_RTX
;
8288 reg_last_reload_reg
[out_regno
] = 0;
8290 /* If we can find a hard register that is stored, record
8291 the storing insn so that we may delete this insn with
8292 delete_output_reload. */
8293 src_reg
= reload_reg_rtx_for_output
[r
];
8295 /* If this is an optional reload, try to find the source reg
8296 from an input reload. */
8299 rtx set
= single_set (insn
);
8300 if (set
&& SET_DEST (set
) == rld
[r
].out
)
8304 src_reg
= SET_SRC (set
);
8306 for (k
= 0; k
< n_reloads
; k
++)
8308 if (rld
[k
].in
== src_reg
)
8310 src_reg
= reload_reg_rtx_for_input
[k
];
8317 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
8318 if (src_reg
&& REG_P (src_reg
)
8319 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
8321 int src_regno
, src_nregs
, k
;
8324 gcc_assert (GET_MODE (src_reg
) == mode
);
8325 src_regno
= REGNO (src_reg
);
8326 src_nregs
= hard_regno_nregs
[src_regno
][mode
];
8327 /* The place where to find a death note varies with
8328 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8329 necessarily checked exactly in the code that moves
8330 notes, so just check both locations. */
8331 note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
8332 if (! note
&& store_insn
)
8333 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
8334 for (k
= 0; k
< src_nregs
; k
++)
8336 spill_reg_store
[src_regno
+ k
] = store_insn
;
8337 spill_reg_stored_to
[src_regno
+ k
] = out
;
8338 reg_reloaded_contents
[src_regno
+ k
] = out_regno
;
8339 reg_reloaded_insn
[src_regno
+ k
] = store_insn
;
8340 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ k
);
8341 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ k
);
8342 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno
+ k
,
8344 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8347 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8349 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ k
);
8351 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8353 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8355 reg_last_reload_reg
[out_regno
] = src_reg
;
8356 /* We have to set reg_has_output_reload here, or else
8357 forget_old_reloads_1 will clear reg_last_reload_reg
8359 SET_REGNO_REG_SET (®_has_output_reload
,
8365 int k
, out_nregs
= hard_regno_nregs
[out_regno
][mode
];
8367 for (k
= 0; k
< out_nregs
; k
++)
8368 reg_last_reload_reg
[out_regno
+ k
] = 0;
8372 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
8375 /* Go through the motions to emit INSN and test if it is strictly valid.
8376 Return the emitted insn if valid, else return NULL. */
8379 emit_insn_if_valid_for_reload (rtx insn
)
8381 rtx last
= get_last_insn ();
8384 insn
= emit_insn (insn
);
8385 code
= recog_memoized (insn
);
8389 extract_insn (insn
);
8390 /* We want constrain operands to treat this insn strictly in its
8391 validity determination, i.e., the way it would after reload has
8393 if (constrain_operands (1))
8397 delete_insns_since (last
);
8401 /* Emit code to perform a reload from IN (which may be a reload register) to
8402 OUT (which may also be a reload register). IN or OUT is from operand
8403 OPNUM with reload type TYPE.
8405 Returns first insn emitted. */
8408 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
8410 rtx last
= get_last_insn ();
8413 /* If IN is a paradoxical SUBREG, remove it and try to put the
8414 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8415 if (GET_CODE (in
) == SUBREG
8416 && (GET_MODE_SIZE (GET_MODE (in
))
8417 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
8418 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
8419 in
= SUBREG_REG (in
), out
= tem
;
8420 else if (GET_CODE (out
) == SUBREG
8421 && (GET_MODE_SIZE (GET_MODE (out
))
8422 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out
))))
8423 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (out
)), in
)) != 0)
8424 out
= SUBREG_REG (out
), in
= tem
;
8426 /* How to do this reload can get quite tricky. Normally, we are being
8427 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8428 register that didn't get a hard register. In that case we can just
8429 call emit_move_insn.
8431 We can also be asked to reload a PLUS that adds a register or a MEM to
8432 another register, constant or MEM. This can occur during frame pointer
8433 elimination and while reloading addresses. This case is handled by
8434 trying to emit a single insn to perform the add. If it is not valid,
8435 we use a two insn sequence.
8437 Or we can be asked to reload an unary operand that was a fragment of
8438 an addressing mode, into a register. If it isn't recognized as-is,
8439 we try making the unop operand and the reload-register the same:
8440 (set reg:X (unop:X expr:Y))
8441 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8443 Finally, we could be called to handle an 'o' constraint by putting
8444 an address into a register. In that case, we first try to do this
8445 with a named pattern of "reload_load_address". If no such pattern
8446 exists, we just emit a SET insn and hope for the best (it will normally
8447 be valid on machines that use 'o').
8449 This entire process is made complex because reload will never
8450 process the insns we generate here and so we must ensure that
8451 they will fit their constraints and also by the fact that parts of
8452 IN might be being reloaded separately and replaced with spill registers.
8453 Because of this, we are, in some sense, just guessing the right approach
8454 here. The one listed above seems to work.
8456 ??? At some point, this whole thing needs to be rethought. */
8458 if (GET_CODE (in
) == PLUS
8459 && (REG_P (XEXP (in
, 0))
8460 || GET_CODE (XEXP (in
, 0)) == SUBREG
8461 || MEM_P (XEXP (in
, 0)))
8462 && (REG_P (XEXP (in
, 1))
8463 || GET_CODE (XEXP (in
, 1)) == SUBREG
8464 || CONSTANT_P (XEXP (in
, 1))
8465 || MEM_P (XEXP (in
, 1))))
8467 /* We need to compute the sum of a register or a MEM and another
8468 register, constant, or MEM, and put it into the reload
8469 register. The best possible way of doing this is if the machine
8470 has a three-operand ADD insn that accepts the required operands.
8472 The simplest approach is to try to generate such an insn and see if it
8473 is recognized and matches its constraints. If so, it can be used.
8475 It might be better not to actually emit the insn unless it is valid,
8476 but we need to pass the insn as an operand to `recog' and
8477 `extract_insn' and it is simpler to emit and then delete the insn if
8478 not valid than to dummy things up. */
8480 rtx op0
, op1
, tem
, insn
;
8483 op0
= find_replacement (&XEXP (in
, 0));
8484 op1
= find_replacement (&XEXP (in
, 1));
8486 /* Since constraint checking is strict, commutativity won't be
8487 checked, so we need to do that here to avoid spurious failure
8488 if the add instruction is two-address and the second operand
8489 of the add is the same as the reload reg, which is frequently
8490 the case. If the insn would be A = B + A, rearrange it so
8491 it will be A = A + B as constrain_operands expects. */
8493 if (REG_P (XEXP (in
, 1))
8494 && REGNO (out
) == REGNO (XEXP (in
, 1)))
8495 tem
= op0
, op0
= op1
, op1
= tem
;
8497 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
8498 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
8500 insn
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
8504 /* If that failed, we must use a conservative two-insn sequence.
8506 Use a move to copy one operand into the reload register. Prefer
8507 to reload a constant, MEM or pseudo since the move patterns can
8508 handle an arbitrary operand. If OP1 is not a constant, MEM or
8509 pseudo and OP1 is not a valid operand for an add instruction, then
8512 After reloading one of the operands into the reload register, add
8513 the reload register to the output register.
8515 If there is another way to do this for a specific machine, a
8516 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8519 code
= (int) optab_handler (add_optab
, GET_MODE (out
));
8521 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
8523 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
8524 || (code
!= CODE_FOR_nothing
8525 && ! ((*insn_data
[code
].operand
[2].predicate
)
8526 (op1
, insn_data
[code
].operand
[2].mode
))))
8527 tem
= op0
, op0
= op1
, op1
= tem
;
8529 gen_reload (out
, op0
, opnum
, type
);
8531 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8532 This fixes a problem on the 32K where the stack pointer cannot
8533 be used as an operand of an add insn. */
8535 if (rtx_equal_p (op0
, op1
))
8538 insn
= emit_insn_if_valid_for_reload (gen_add2_insn (out
, op1
));
8541 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8542 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8546 /* If that failed, copy the address register to the reload register.
8547 Then add the constant to the reload register. */
8549 gcc_assert (!reg_overlap_mentioned_p (out
, op0
));
8550 gen_reload (out
, op1
, opnum
, type
);
8551 insn
= emit_insn (gen_add2_insn (out
, op0
));
8552 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8555 #ifdef SECONDARY_MEMORY_NEEDED
8556 /* If we need a memory location to do the move, do it that way. */
8557 else if ((REG_P (in
)
8558 || (GET_CODE (in
) == SUBREG
&& REG_P (SUBREG_REG (in
))))
8559 && reg_or_subregno (in
) < FIRST_PSEUDO_REGISTER
8561 || (GET_CODE (out
) == SUBREG
&& REG_P (SUBREG_REG (out
))))
8562 && reg_or_subregno (out
) < FIRST_PSEUDO_REGISTER
8563 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in
)),
8564 REGNO_REG_CLASS (reg_or_subregno (out
)),
8567 /* Get the memory to use and rewrite both registers to its mode. */
8568 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
8570 if (GET_MODE (loc
) != GET_MODE (out
))
8571 out
= gen_rtx_REG (GET_MODE (loc
), REGNO (out
));
8573 if (GET_MODE (loc
) != GET_MODE (in
))
8574 in
= gen_rtx_REG (GET_MODE (loc
), REGNO (in
));
8576 gen_reload (loc
, in
, opnum
, type
);
8577 gen_reload (out
, loc
, opnum
, type
);
8580 else if (REG_P (out
) && UNARY_P (in
))
8587 op1
= find_replacement (&XEXP (in
, 0));
8588 if (op1
!= XEXP (in
, 0))
8589 in
= gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
), op1
);
8591 /* First, try a plain SET. */
8592 set
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
8596 /* If that failed, move the inner operand to the reload
8597 register, and try the same unop with the inner expression
8598 replaced with the reload register. */
8600 if (GET_MODE (op1
) != GET_MODE (out
))
8601 out_moded
= gen_rtx_REG (GET_MODE (op1
), REGNO (out
));
8605 gen_reload (out_moded
, op1
, opnum
, type
);
8608 = gen_rtx_SET (VOIDmode
, out
,
8609 gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
),
8611 insn
= emit_insn_if_valid_for_reload (insn
);
8614 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8618 fatal_insn ("Failure trying to reload:", set
);
8620 /* If IN is a simple operand, use gen_move_insn. */
8621 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
8623 tem
= emit_insn (gen_move_insn (out
, in
));
8624 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8625 mark_jump_label (in
, tem
, 0);
8628 #ifdef HAVE_reload_load_address
8629 else if (HAVE_reload_load_address
)
8630 emit_insn (gen_reload_load_address (out
, in
));
8633 /* Otherwise, just write (set OUT IN) and hope for the best. */
8635 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
8637 /* Return the first insn emitted.
8638 We can not just return get_last_insn, because there may have
8639 been multiple instructions emitted. Also note that gen_move_insn may
8640 emit more than one insn itself, so we can not assume that there is one
8641 insn emitted per emit_insn_before call. */
8643 return last
? NEXT_INSN (last
) : get_insns ();
8646 /* Delete a previously made output-reload whose result we now believe
8647 is not needed. First we double-check.
8649 INSN is the insn now being processed.
8650 LAST_RELOAD_REG is the hard register number for which we want to delete
8651 the last output reload.
8652 J is the reload-number that originally used REG. The caller has made
8653 certain that reload J doesn't use REG any longer for input.
8654 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8657 delete_output_reload (rtx insn
, int j
, int last_reload_reg
, rtx new_reload_reg
)
8659 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
8660 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
8663 int n_inherited
= 0;
8669 /* It is possible that this reload has been only used to set another reload
8670 we eliminated earlier and thus deleted this instruction too. */
8671 if (INSN_DELETED_P (output_reload_insn
))
8674 /* Get the raw pseudo-register referred to. */
8676 while (GET_CODE (reg
) == SUBREG
)
8677 reg
= SUBREG_REG (reg
);
8678 substed
= reg_equiv_memory_loc
[REGNO (reg
)];
8680 /* This is unsafe if the operand occurs more often in the current
8681 insn than it is inherited. */
8682 for (k
= n_reloads
- 1; k
>= 0; k
--)
8684 rtx reg2
= rld
[k
].in
;
8687 if (MEM_P (reg2
) || reload_override_in
[k
])
8688 reg2
= rld
[k
].in_reg
;
8690 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
8691 reg2
= XEXP (rld
[k
].in_reg
, 0);
8693 while (GET_CODE (reg2
) == SUBREG
)
8694 reg2
= SUBREG_REG (reg2
);
8695 if (rtx_equal_p (reg2
, reg
))
8697 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
8703 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
8704 if (CALL_P (insn
) && CALL_INSN_FUNCTION_USAGE (insn
))
8705 n_occurrences
+= count_occurrences (CALL_INSN_FUNCTION_USAGE (insn
),
8708 n_occurrences
+= count_occurrences (PATTERN (insn
),
8709 eliminate_regs (substed
, VOIDmode
,
8711 for (i1
= reg_equiv_alt_mem_list
[REGNO (reg
)]; i1
; i1
= XEXP (i1
, 1))
8713 gcc_assert (!rtx_equal_p (XEXP (i1
, 0), substed
));
8714 n_occurrences
+= count_occurrences (PATTERN (insn
), XEXP (i1
, 0), 0);
8716 if (n_occurrences
> n_inherited
)
8719 regno
= REGNO (reg
);
8720 if (regno
>= FIRST_PSEUDO_REGISTER
)
8723 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
8725 /* If the pseudo-reg we are reloading is no longer referenced
8726 anywhere between the store into it and here,
8727 and we're within the same basic block, then the value can only
8728 pass through the reload reg and end up here.
8729 Otherwise, give up--return. */
8730 for (i1
= NEXT_INSN (output_reload_insn
);
8731 i1
!= insn
; i1
= NEXT_INSN (i1
))
8733 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
8735 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
8736 && refers_to_regno_p (regno
, regno
+ nregs
, PATTERN (i1
), NULL
))
8738 /* If this is USE in front of INSN, we only have to check that
8739 there are no more references than accounted for by inheritance. */
8740 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
8742 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
8743 i1
= NEXT_INSN (i1
);
8745 if (n_occurrences
<= n_inherited
&& i1
== insn
)
8751 /* We will be deleting the insn. Remove the spill reg information. */
8752 for (k
= hard_regno_nregs
[last_reload_reg
][GET_MODE (reg
)]; k
-- > 0; )
8754 spill_reg_store
[last_reload_reg
+ k
] = 0;
8755 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
8758 /* The caller has already checked that REG dies or is set in INSN.
8759 It has also checked that we are optimizing, and thus some
8760 inaccuracies in the debugging information are acceptable.
8761 So we could just delete output_reload_insn. But in some cases
8762 we can improve the debugging information without sacrificing
8763 optimization - maybe even improving the code: See if the pseudo
8764 reg has been completely replaced with reload regs. If so, delete
8765 the store insn and forget we had a stack slot for the pseudo. */
8766 if (rld
[j
].out
!= rld
[j
].in
8767 && REG_N_DEATHS (REGNO (reg
)) == 1
8768 && REG_N_SETS (REGNO (reg
)) == 1
8769 && REG_BASIC_BLOCK (REGNO (reg
)) >= NUM_FIXED_BLOCKS
8770 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
8774 /* We know that it was used only between here and the beginning of
8775 the current basic block. (We also know that the last use before
8776 INSN was the output reload we are thinking of deleting, but never
8777 mind that.) Search that range; see if any ref remains. */
8778 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8780 rtx set
= single_set (i2
);
8782 /* Uses which just store in the pseudo don't count,
8783 since if they are the only uses, they are dead. */
8784 if (set
!= 0 && SET_DEST (set
) == reg
)
8789 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
8790 && reg_mentioned_p (reg
, PATTERN (i2
)))
8792 /* Some other ref remains; just delete the output reload we
8794 delete_address_reloads (output_reload_insn
, insn
);
8795 delete_insn (output_reload_insn
);
8800 /* Delete the now-dead stores into this pseudo. Note that this
8801 loop also takes care of deleting output_reload_insn. */
8802 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8804 rtx set
= single_set (i2
);
8806 if (set
!= 0 && SET_DEST (set
) == reg
)
8808 delete_address_reloads (i2
, insn
);
8816 /* For the debugging info, say the pseudo lives in this reload reg. */
8817 reg_renumber
[REGNO (reg
)] = REGNO (new_reload_reg
);
8818 if (ira_conflicts_p
)
8819 /* Inform IRA about the change. */
8820 ira_mark_allocation_change (REGNO (reg
));
8821 alter_reg (REGNO (reg
), -1, false);
8825 delete_address_reloads (output_reload_insn
, insn
);
8826 delete_insn (output_reload_insn
);
8830 /* We are going to delete DEAD_INSN. Recursively delete loads of
8831 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8832 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8834 delete_address_reloads (rtx dead_insn
, rtx current_insn
)
8836 rtx set
= single_set (dead_insn
);
8837 rtx set2
, dst
, prev
, next
;
8840 rtx dst
= SET_DEST (set
);
8842 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
8844 /* If we deleted the store from a reloaded post_{in,de}c expression,
8845 we can delete the matching adds. */
8846 prev
= PREV_INSN (dead_insn
);
8847 next
= NEXT_INSN (dead_insn
);
8848 if (! prev
|| ! next
)
8850 set
= single_set (next
);
8851 set2
= single_set (prev
);
8853 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
8854 || !CONST_INT_P (XEXP (SET_SRC (set
), 1))
8855 || !CONST_INT_P (XEXP (SET_SRC (set2
), 1)))
8857 dst
= SET_DEST (set
);
8858 if (! rtx_equal_p (dst
, SET_DEST (set2
))
8859 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
8860 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
8861 || (INTVAL (XEXP (SET_SRC (set
), 1))
8862 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
8864 delete_related_insns (prev
);
8865 delete_related_insns (next
);
8868 /* Subfunction of delete_address_reloads: process registers found in X. */
8870 delete_address_reloads_1 (rtx dead_insn
, rtx x
, rtx current_insn
)
8872 rtx prev
, set
, dst
, i2
;
8874 enum rtx_code code
= GET_CODE (x
);
8878 const char *fmt
= GET_RTX_FORMAT (code
);
8879 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8882 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
8883 else if (fmt
[i
] == 'E')
8885 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8886 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
8893 if (spill_reg_order
[REGNO (x
)] < 0)
8896 /* Scan backwards for the insn that sets x. This might be a way back due
8898 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
8900 code
= GET_CODE (prev
);
8901 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
8905 if (reg_set_p (x
, PATTERN (prev
)))
8907 if (reg_referenced_p (x
, PATTERN (prev
)))
8910 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
8912 /* Check that PREV only sets the reload register. */
8913 set
= single_set (prev
);
8916 dst
= SET_DEST (set
);
8918 || ! rtx_equal_p (dst
, x
))
8920 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
8922 /* Check if DST was used in a later insn -
8923 it might have been inherited. */
8924 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
8930 if (reg_referenced_p (dst
, PATTERN (i2
)))
8932 /* If there is a reference to the register in the current insn,
8933 it might be loaded in a non-inherited reload. If no other
8934 reload uses it, that means the register is set before
8936 if (i2
== current_insn
)
8938 for (j
= n_reloads
- 1; j
>= 0; j
--)
8939 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
8940 || reload_override_in
[j
] == dst
)
8942 for (j
= n_reloads
- 1; j
>= 0; j
--)
8943 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
8952 /* If DST is still live at CURRENT_INSN, check if it is used for
8953 any reload. Note that even if CURRENT_INSN sets DST, we still
8954 have to check the reloads. */
8955 if (i2
== current_insn
)
8957 for (j
= n_reloads
- 1; j
>= 0; j
--)
8958 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
8959 || reload_override_in
[j
] == dst
)
8961 /* ??? We can't finish the loop here, because dst might be
8962 allocated to a pseudo in this block if no reload in this
8963 block needs any of the classes containing DST - see
8964 spill_hard_reg. There is no easy way to tell this, so we
8965 have to scan till the end of the basic block. */
8967 if (reg_set_p (dst
, PATTERN (i2
)))
8971 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
8972 reg_reloaded_contents
[REGNO (dst
)] = -1;
8976 /* Output reload-insns to reload VALUE into RELOADREG.
8977 VALUE is an autoincrement or autodecrement RTX whose operand
8978 is a register or memory location;
8979 so reloading involves incrementing that location.
8980 IN is either identical to VALUE, or some cheaper place to reload from.
8982 INC_AMOUNT is the number to increment or decrement by (always positive).
8983 This cannot be deduced from VALUE.
8985 Return the instruction that stores into RELOADREG. */
8988 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, int inc_amount
)
8990 /* REG or MEM to be copied and incremented. */
8991 rtx incloc
= find_replacement (&XEXP (value
, 0));
8992 /* Nonzero if increment after copying. */
8993 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
8994 || GET_CODE (value
) == POST_MODIFY
);
9000 rtx real_in
= in
== value
? incloc
: in
;
9002 /* No hard register is equivalent to this register after
9003 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9004 we could inc/dec that register as well (maybe even using it for
9005 the source), but I'm not sure it's worth worrying about. */
9007 reg_last_reload_reg
[REGNO (incloc
)] = 0;
9009 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
9011 gcc_assert (GET_CODE (XEXP (value
, 1)) == PLUS
);
9012 inc
= find_replacement (&XEXP (XEXP (value
, 1), 1));
9016 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
9017 inc_amount
= -inc_amount
;
9019 inc
= GEN_INT (inc_amount
);
9022 /* If this is post-increment, first copy the location to the reload reg. */
9023 if (post
&& real_in
!= reloadreg
)
9024 emit_insn (gen_move_insn (reloadreg
, real_in
));
9028 /* See if we can directly increment INCLOC. Use a method similar to
9029 that in gen_reload. */
9031 last
= get_last_insn ();
9032 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
9033 gen_rtx_PLUS (GET_MODE (incloc
),
9036 code
= recog_memoized (add_insn
);
9039 extract_insn (add_insn
);
9040 if (constrain_operands (1))
9042 /* If this is a pre-increment and we have incremented the value
9043 where it lives, copy the incremented value to RELOADREG to
9044 be used as an address. */
9047 emit_insn (gen_move_insn (reloadreg
, incloc
));
9052 delete_insns_since (last
);
9055 /* If couldn't do the increment directly, must increment in RELOADREG.
9056 The way we do this depends on whether this is pre- or post-increment.
9057 For pre-increment, copy INCLOC to the reload register, increment it
9058 there, then save back. */
9062 if (in
!= reloadreg
)
9063 emit_insn (gen_move_insn (reloadreg
, real_in
));
9064 emit_insn (gen_add2_insn (reloadreg
, inc
));
9065 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
9070 Because this might be a jump insn or a compare, and because RELOADREG
9071 may not be available after the insn in an input reload, we must do
9072 the incrementation before the insn being reloaded for.
9074 We have already copied IN to RELOADREG. Increment the copy in
9075 RELOADREG, save that back, then decrement RELOADREG so it has
9076 the original value. */
9078 emit_insn (gen_add2_insn (reloadreg
, inc
));
9079 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
9080 if (CONST_INT_P (inc
))
9081 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-INTVAL (inc
))));
9083 emit_insn (gen_sub2_insn (reloadreg
, inc
));
9091 add_auto_inc_notes (rtx insn
, rtx x
)
9093 enum rtx_code code
= GET_CODE (x
);
9097 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
9099 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
9103 /* Scan all the operand sub-expressions. */
9104 fmt
= GET_RTX_FORMAT (code
);
9105 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9108 add_auto_inc_notes (insn
, XEXP (x
, i
));
9109 else if (fmt
[i
] == 'E')
9110 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9111 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));
9116 /* This is used by reload pass, that does emit some instructions after
9117 abnormal calls moving basic block end, but in fact it wants to emit
9118 them on the edge. Looks for abnormal call edges, find backward the
9119 proper call and fix the damage.
9121 Similar handle instructions throwing exceptions internally. */
9123 fixup_abnormal_edges (void)
9125 bool inserted
= false;
9133 /* Look for cases we are interested in - calls or instructions causing
9135 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
9137 if (e
->flags
& EDGE_ABNORMAL_CALL
)
9139 if ((e
->flags
& (EDGE_ABNORMAL
| EDGE_EH
))
9140 == (EDGE_ABNORMAL
| EDGE_EH
))
9143 if (e
&& !CALL_P (BB_END (bb
))
9144 && !can_throw_internal (BB_END (bb
)))
9148 /* Get past the new insns generated. Allow notes, as the insns
9149 may be already deleted. */
9151 while ((NONJUMP_INSN_P (insn
) || NOTE_P (insn
))
9152 && !can_throw_internal (insn
)
9153 && insn
!= BB_HEAD (bb
))
9154 insn
= PREV_INSN (insn
);
9156 if (CALL_P (insn
) || can_throw_internal (insn
))
9160 stop
= NEXT_INSN (BB_END (bb
));
9162 insn
= NEXT_INSN (insn
);
9164 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
9165 if (e
->flags
& EDGE_FALLTHRU
)
9168 while (insn
&& insn
!= stop
)
9170 next
= NEXT_INSN (insn
);
9175 /* Sometimes there's still the return value USE.
9176 If it's placed after a trapping call (i.e. that
9177 call is the last insn anyway), we have no fallthru
9178 edge. Simply delete this use and don't try to insert
9179 on the non-existent edge. */
9180 if (GET_CODE (PATTERN (insn
)) != USE
)
9182 /* We're not deleting it, we're moving it. */
9183 INSN_DELETED_P (insn
) = 0;
9184 PREV_INSN (insn
) = NULL_RTX
;
9185 NEXT_INSN (insn
) = NULL_RTX
;
9187 insert_insn_on_edge (insn
, e
);
9191 else if (!BARRIER_P (insn
))
9192 set_block_for_insn (insn
, NULL
);
9197 /* It may be that we don't find any such trapping insn. In this
9198 case we discovered quite late that the insn that had been
9199 marked as can_throw_internal in fact couldn't trap at all.
9200 So we should in fact delete the EH edges out of the block. */
9202 purge_dead_edges (bb
);
9206 /* We've possibly turned single trapping insn into multiple ones. */
9207 if (cfun
->can_throw_non_call_exceptions
)
9210 blocks
= sbitmap_alloc (last_basic_block
);
9211 sbitmap_ones (blocks
);
9212 find_many_sub_basic_blocks (blocks
);
9213 sbitmap_free (blocks
);
9217 commit_edge_insertions ();
9219 #ifdef ENABLE_CHECKING
9220 /* Verify that we didn't turn one trapping insn into many, and that
9221 we found and corrected all of the problems wrt fixups on the
9223 verify_flow_info ();