| blob | f58f192273e3ad313e154f28df0a88188cde36db |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #define INCLUDE_STRING
71 /* This file should be included last. */
74 /* Defined for convenience. */
75 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
77 /* Classifies an address.
79 ADDRESS_REG_IMM
80 A simple base register plus immediate offset.
82 ADDRESS_REG_WB
83 A base register indexed by immediate offset with writeback.
85 ADDRESS_REG_REG
86 A base register indexed by (optionally scaled) register.
88 ADDRESS_REG_UXTW
89 A base register indexed by (optionally scaled) zero-extended register.
91 ADDRESS_REG_SXTW
92 A base register indexed by (optionally scaled) sign-extended register.
94 ADDRESS_LO_SUM
95 A LO_SUM rtx with a base register and "LO12" symbol relocation.
97 ADDRESS_SYMBOLIC:
98 A constant symbolic address, in pc-relative literal pool. */
101 ADDRESS_REG_IMM,
102 ADDRESS_REG_WB,
103 ADDRESS_REG_REG,
104 ADDRESS_REG_UXTW,
105 ADDRESS_REG_SXTW,
106 ADDRESS_LO_SUM,
107 ADDRESS_SYMBOLIC
108 };
112 rtx base;
113 rtx offset;
116 };
118 struct simd_immediate_info
119 {
120 rtx value;
125 };
127 /* The current code model. */
130 #ifdef HAVE_AS_TLS
131 #undef TARGET_HAVE_TLS
132 #define TARGET_HAVE_TLS 1
133 #endif
137 const_tree,
145 vec_perm_indices);
148 const_tree type,
151 static machine_mode
154 /* Major revision number of the ARM Architecture implemented by the target. */
157 /* The processor for which instructions should be scheduled. */
160 /* Mask to specify which instruction scheduling options should be used. */
163 /* Global flag for PC relative loads. */
166 /* Support for command line parsing of boolean flags in the tuning
167 structures. */
168 struct aarch64_flag_desc
169 {
172 };
174 #define AARCH64_FUSION_PAIR(name, internal_name) \
175 { name, AARCH64_FUSE_##internal_name },
177 {
182 };
184 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
185 { name, AARCH64_EXTRA_TUNE_##internal_name },
187 {
192 };
194 /* Tuning parameters. */
197 {
198 {
203 },
210 };
213 {
214 {
219 },
226 };
229 {
230 {
235 },
242 };
245 {
246 {
251 },
258 };
261 {
263 /* Avoid the use of slow int<->fp moves for spilling by setting
264 their cost higher than memmov_cost. */
268 };
271 {
273 /* Avoid the use of slow int<->fp moves for spilling by setting
274 their cost higher than memmov_cost. */
278 };
281 {
283 /* Avoid the use of slow int<->fp moves for spilling by setting
284 their cost higher than memmov_cost. */
288 };
291 {
293 /* Avoid the use of slow int<->fp moves for spilling by setting
294 their cost higher than memmov_cost (actual, 4 and 9). */
298 };
301 {
306 };
309 {
311 /* Avoid the use of slow int<->fp moves for spilling by setting
312 their cost higher than memmov_cost. */
316 };
319 {
321 /* Avoid the use of int<->fp moves for spilling. */
325 };
328 {
330 /* Avoid the use of int<->fp moves for spilling. */
334 };
336 /* Generic costs for vector insn classes. */
338 {
354 };
356 /* ThunderX costs for vector insn classes. */
358 {
374 };
376 /* Generic costs for vector insn classes. */
378 {
394 };
397 {
413 };
415 /* Generic costs for vector insn classes. */
417 {
433 };
435 /* Costs for vector insn classes for Vulcan. */
437 {
453 };
455 /* Generic costs for branch instructions. */
457 {
460 };
462 /* Generic approximation modes. */
464 {
467 AARCH64_APPROX_NONE /* recip_sqrt */
468 };
470 /* Approximation modes for Exynos M1. */
472 {
475 AARCH64_APPROX_ALL /* recip_sqrt */
476 };
478 /* Approximation modes for X-Gene 1. */
480 {
483 AARCH64_APPROX_ALL /* recip_sqrt */
484 };
486 /* Generic prefetch settings (which disable prefetch). */
488 {
494 };
497 {
503 };
506 {
512 };
515 {
521 };
524 {
530 };
533 {
539 };
542 {
563 &generic_prefetch_tune
564 };
567 {
589 &generic_prefetch_tune
590 };
593 {
615 &generic_prefetch_tune
616 };
619 {
641 &generic_prefetch_tune
642 };
645 {
667 &generic_prefetch_tune
668 };
671 {
693 &generic_prefetch_tune
694 };
699 {
720 &exynosm1_prefetch_tune
721 };
724 {
745 &thunderxt88_prefetch_tune
746 };
749 {
769 (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW
771 &thunderx_prefetch_tune
772 };
775 {
796 &generic_prefetch_tune
797 };
800 {
822 &qdf24xx_prefetch_tune
823 };
825 /* Tuning structure for the Qualcomm Saphira core. Default to falkor values
826 for now. */
828 {
850 &generic_prefetch_tune
851 };
854 {
876 &thunderx2t99_prefetch_tune
877 };
879 /* Support for fine-grained override of the tuning structures. */
880 struct aarch64_tuning_override_function
881 {
884 };
889 static const struct aarch64_tuning_override_function
890 aarch64_tuning_override_functions[] =
891 {
895 };
897 /* A processor implementing AArch64. */
898 struct processor
899 {
907 };
909 /* Architectures implementing AArch64. */
911 {
912 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
913 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
916 };
918 /* Processor cores implementing AArch64. */
920 {
921 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
922 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
923 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
924 FLAGS, &COSTS##_tunings},
929 };
932 /* Target specification. These are populated by the -march, -mtune, -mcpu
933 handling code or by target attributes. */
938 /* The current tuning set. */
941 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
943 /* An ISA extension in the co-processor and main instruction set space. */
944 struct aarch64_option_extension
945 {
949 };
952 {
956 }
957 aarch64_cc;
959 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
961 /* The condition codes of the processor, and the inverse function. */
963 {
966 };
968 /* Generate code to enable conditional branches in functions over 1 MiB. */
972 {
989 }
991 void
993 {
997 else
999 }
1001 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
1002 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
1003 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
1004 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
1005 cost (in this case the best class is the lowest cost one). Using ALL_REGS
1006 irrespectively of its cost results in bad allocations with many redundant
1007 int<->FP moves which are expensive on various cores.
1008 To avoid this we don't allow ALL_REGS as the allocno class, but force a
1009 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
1010 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
1011 Otherwise set the allocno class depending on the mode.
1012 The result of this is that it is no longer inefficient to have a higher
1013 memory move cost than the register move cost.
1014 */
1016 static reg_class_t
1018 reg_class_t best_class)
1019 {
1020 machine_mode mode;
1030 }
1032 static unsigned int
1034 {
1038 }
1040 static int
1042 machine_mode mode)
1043 {
1051 }
1053 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
1054 unsigned
1056 {
1064 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
1065 equivalent DWARF register. */
1067 }
1069 /* Return TRUE if MODE is any of the large INT modes. */
1070 static bool
1072 {
1074 }
1076 /* Return TRUE if MODE is any of the vector modes. */
1077 static bool
1079 {
1082 }
1084 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1085 static bool
1088 {
1096 }
1098 /* Implement TARGET_HARD_REGNO_NREGS. */
1100 static unsigned int
1102 {
1104 {
1110 }
1112 }
1114 /* Implement TARGET_HARD_REGNO_MODE_OK. */
1116 static bool
1118 {
1123 /* The purpose of comparing with ptr_mode is to support the
1124 global register variable associated with the stack pointer
1125 register via the syntax of asm ("wsp") in ILP32. */
1135 {
1138 else
1140 }
1143 }
1145 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
1146 the lower 64 bits of a 128-bit register. Tell the compiler the callee
1147 clobbers the top 64 bits when restoring the bottom 64 bits. */
1149 static bool
1151 {
1153 }
1155 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1156 machine_mode
1158 machine_mode mode)
1159 {
1160 /* Handle modes that fit within single registers. */
1162 {
1165 else
1167 }
1168 /* Fall back to generic for multi-reg and very large modes. */
1169 else
1171 }
1173 /* Implement TARGET_CONSTANT_ALIGNMENT. Make strings word-aligned so
1174 that strcpy from constants will be faster. */
1176 static HOST_WIDE_INT
1178 {
1182 }
1184 /* Return true if calls to DECL should be treated as
1185 long-calls (ie called via a register). */
1186 static bool
1188 {
1190 }
1192 /* Return true if calls to symbol-ref SYM should be treated as
1193 long-calls (ie called via a register). */
1194 bool
1196 {
1198 }
1200 /* Return true if calls to symbol-ref SYM should not go through
1201 plt stubs. */
1203 bool
1205 {
1209 && decl
1210 && (!flag_plt
1216 }
1218 /* Return true if the offsets to a zero/sign-extract operation
1219 represent an expression that matches an extend operation. The
1220 operands represent the paramters from
1222 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1223 bool
1225 rtx extract_imm)
1226 {
1243 }
1245 /* Emit an insn that's a simple single-set. Both the operands must be
1246 known to be valid. */
1249 {
1251 }
1253 /* X and Y are two things to compare using CODE. Emit the compare insn and
1254 return the rtx for register 0 in the proper mode. */
1255 rtx
1257 {
1263 }
1265 /* Build the SYMBOL_REF for __tls_get_addr. */
1269 rtx
1271 {
1275 }
1277 /* Return the TLS model to use for ADDR. */
1279 static enum tls_model
1281 {
1286 {
1290 }
1295 }
1297 /* We'll allow lo_sum's in addresses in our legitimate addresses
1298 so that combine would take care of combining addresses where
1299 necessary, but for generation purposes, we'll generate the address
1300 as :
1301 RTL Absolute
1302 tmp = hi (symbol_ref); adrp x1, foo
1303 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1304 nop
1306 PIC TLS
1307 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1308 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1309 bl __tls_get_addr
1310 nop
1312 Load TLS symbol, depending on TLS mechanism and TLS access model.
1314 Global Dynamic - Traditional TLS:
1315 adrp tmp, :tlsgd:imm
1316 add dest, tmp, #:tlsgd_lo12:imm
1317 bl __tls_get_addr
1319 Global Dynamic - TLS Descriptors:
1320 adrp dest, :tlsdesc:imm
1321 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1322 add dest, dest, #:tlsdesc_lo12:imm
1323 blr tmp
1324 mrs tp, tpidr_el0
1325 add dest, dest, tp
1327 Initial Exec:
1328 mrs tp, tpidr_el0
1329 adrp tmp, :gottprel:imm
1330 ldr dest, [tmp, #:gottprel_lo12:imm]
1331 add dest, dest, tp
1333 Local Exec:
1334 mrs tp, tpidr_el0
1335 add t0, tp, #:tprel_hi12:imm, lsl #12
1336 add t0, t0, #:tprel_lo12_nc:imm
1337 */
1339 static void
1342 {
1344 {
1346 {
1347 /* In ILP32, the mode of dest can be either SImode or DImode. */
1359 }
1366 {
1369 rtx insn;
1370 rtx mem;
1372 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1373 here before rtl expand. Tree IVOPT will generate rtl pattern to
1374 decide rtx costs, in which case pic_offset_table_rtx is not
1375 initialized. For that case no need to generate the first adrp
1376 instruction as the final cost for global variable access is
1377 one instruction. */
1379 {
1380 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1381 using the page base as GOT base, the first page may be wasted,
1382 in the worst scenario, there is only 28K space for GOT).
1384 The generate instruction sequence for accessing global variable
1385 is:
1387 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1389 Only one instruction needed. But we must initialize
1390 pic_offset_table_rtx properly. We generate initialize insn for
1391 every global access, and allow CSE to remove all redundant.
1393 The final instruction sequences will look like the following
1394 for multiply global variables access.
1396 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1398 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1399 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1400 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1401 ... */
1410 }
1413 {
1416 else
1420 }
1421 else
1422 {
1427 }
1429 /* The operand is expected to be MEM. Whenever the related insn
1430 pattern changed, above code which calculate mem should be
1431 updated. */
1437 }
1440 {
1441 /* In ILP32, the mode of dest can be either SImode or DImode,
1442 while the got entry is always of SImode size. The mode of
1443 dest depends on how dest is used: if dest is assigned to a
1444 pointer (e.g. in the memory), it has SImode; it may have
1445 DImode if dest is dereferenced to access the memeory.
1446 This is why we have to handle three different ldr_got_small
1447 patterns here (two patterns for ILP32). */
1449 rtx insn;
1450 rtx mem;
1459 {
1462 else
1466 }
1467 else
1468 {
1473 }
1480 }
1483 {
1491 else
1499 }
1502 {
1505 rtx tp;
1509 /* In ILP32, the got entry is always of SImode size. Unlike
1510 small GOT, the dest is fixed at reg 0. */
1513 else
1524 }
1527 {
1528 /* In ILP32, the mode of dest can be either SImode or DImode,
1529 while the got entry is always of SImode size. The mode of
1530 dest depends on how dest is used: if dest is assigned to a
1531 pointer (e.g. in the memory), it has SImode; it may have
1532 DImode if dest is dereferenced to access the memeory.
1533 This is why we have to handle three different tlsie_small
1534 patterns here (two patterns for ILP32). */
1540 {
1543 else
1544 {
1547 }
1548 }
1549 else
1550 {
1553 }
1559 }
1565 {
1573 {
1596 }
1601 }
1608 {
1613 {
1616 else
1617 {
1620 }
1621 }
1622 else
1623 {
1626 }
1631 }
1635 }
1636 }
1638 /* Emit a move from SRC to DEST. Assume that the move expanders can
1639 handle all moves if !can_create_pseudo_p (). The distinction is
1640 important because, unlike emit_move_insn, the move expanders know
1641 how to force Pmode objects into the constant pool even when the
1642 constant pool address is not itself legitimate. */
1643 static rtx
1645 {
1649 }
1651 /* Split a 128-bit move operation into two 64-bit move operations,
1652 taking care to handle partial overlap of register to register
1653 copies. Special cases are needed when moving between GP regs and
1654 FP regs. SRC can be a register, constant or memory; DST a register
1655 or memory. If either operand is memory it must not have any side
1656 effects. */
1657 void
1659 {
1670 {
1674 /* Handle FP <-> GP regs. */
1676 {
1681 {
1684 }
1685 else
1686 {
1689 }
1691 }
1693 {
1698 {
1701 }
1702 else
1703 {
1706 }
1708 }
1709 }
1716 /* At most one pairing may overlap. */
1718 {
1721 }
1722 else
1723 {
1726 }
1727 }
1729 bool
1731 {
1734 }
1736 /* Split a complex SIMD combine. */
1738 void
1740 {
1752 {
1776 }
1780 }
1782 /* Split a complex SIMD move. */
1784 void
1786 {
1793 {
1799 {
1823 }
1827 }
1828 }
1830 bool
1833 {
1837 }
1840 static rtx
1842 {
1845 else
1846 {
1849 }
1850 }
1853 static rtx
1855 HOST_WIDE_INT offset)
1856 {
1858 {
1859 rtx high;
1860 /* Load the full offset into a register. This
1861 might be improvable in the future. */
1867 }
1869 }
1871 static int
1873 scalar_int_mode mode)
1874 {
1883 {
1887 }
1889 /* Check to see if the low 32 bits are either 0xffffXXXX or 0xXXXXffff
1890 (with XXXX non-zero). In that case check to see if the move can be done in
1891 a smaller mode. */
1896 {
1900 /* Check if we have to emit a second instruction by checking to see
1901 if any of the upper 32 bits of the original DI mode value is set. */
1912 }
1915 {
1917 {
1922 else
1925 }
1927 }
1929 /* Remaining cases are all for DImode. */
1938 {
1939 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
1940 For a 64-bit bitmask try whether changing 16 bits to all ones or
1941 zeroes creates a valid bitmask. To check any repeated bitmask,
1942 try using 16 bits from the other 32-bit half of val. */
1945 {
1956 }
1958 {
1960 {
1964 }
1966 }
1967 }
1969 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
1970 are emitted by the initial mov. If one_match > zero_match, skip set bits,
1971 otherwise skip zero bits. */
1983 {
1989 num_insns ++;
1990 }
1993 }
1995 /* Add DELTA to REGNUM in mode MODE. SCRATCHREG can be used to hold a
1996 temporary value if necessary. FRAME_RELATED_P should be true if
1997 the RTX_FRAME_RELATED flag should be set and CFA adjustments added
1998 to the generated instructions. If SCRATCHREG is known to hold
1999 abs (delta), EMIT_MOVE_IMM can be set to false to avoid emitting the
2000 immediate again.
2002 Since this function may be used to adjust the stack pointer, we must
2003 ensure that it cannot cause transient stack deallocation (for example
2004 by first incrementing SP and then decrementing when adjusting by a
2005 large immediate). */
2007 static void
2011 {
2019 /* Single instruction adjustment. */
2021 {
2025 }
2027 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits.
2028 Only do this if mdelta is not a 16-bit move as adjusting using a move
2029 is better. */
2031 {
2040 }
2042 /* Emit a move immediate if required and an addition/subtraction. */
2049 {
2053 }
2054 }
2058 HOST_WIDE_INT delta)
2059 {
2061 }
2065 {
2068 }
2072 {
2075 }
2077 void
2079 {
2084 /* Check on what type of symbol it is. */
2085 scalar_int_mode int_mode;
2090 {
2094 /* If we have (const (plus symbol offset)), separate out the offset
2095 before we start classifying the symbol. */
2100 {
2104 {
2111 }
2116 /* If we aren't generating PC relative literals, then
2117 we need to expand the literal pool access carefully.
2118 This is something that needs to be done in a number
2119 of places, so could well live as a separate function. */
2121 {
2128 }
2145 {
2152 }
2153 /* FALLTHRU */
2166 }
2167 }
2170 {
2173 else
2174 {
2178 }
2181 }
2185 }
2187 static bool
2189 tree exp ATTRIBUTE_UNUSED)
2190 {
2191 /* Currently, always true. */
2193 }
2195 /* Implement TARGET_PASS_BY_REFERENCE. */
2197 static bool
2199 machine_mode mode,
2200 const_tree type,
2202 {
2203 HOST_WIDE_INT size;
2204 machine_mode dummymode;
2207 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
2211 /* Aggregates are passed by reference based on their size. */
2213 {
2215 }
2217 /* Variable sized arguments are always returned by reference. */
2221 /* Can this be a candidate to be passed in fp/simd register(s)? */
2224 NULL))
2227 /* Arguments which are variable sized or larger than 2 registers are
2228 passed by reference unless they are a homogenous floating point
2229 aggregate. */
2231 }
2233 /* Return TRUE if VALTYPE is padded to its least significant bits. */
2234 static bool
2236 {
2237 machine_mode dummy_mode;
2240 /* Never happens in little-endian mode. */
2244 /* Only composite types smaller than or equal to 16 bytes can
2245 be potentially returned in registers. */
2251 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
2252 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
2253 is always passed/returned in the least significant bits of fp/simd
2254 register(s). */
2260 }
2262 /* Implement TARGET_FUNCTION_VALUE.
2263 Define how to find the value returned by a function. */
2265 static rtx
2268 {
2269 machine_mode mode;
2272 machine_mode ag_mode;
2279 {
2283 {
2286 }
2287 }
2291 {
2293 {
2296 }
2297 else
2298 {
2300 rtx par;
2304 {
2309 }
2311 }
2312 }
2313 else
2315 }
2317 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
2318 Return true if REGNO is the number of a hard register in which the values
2319 of called function may come back. */
2321 static bool
2323 {
2324 /* Maximum of 16 bytes can be returned in the general registers. Examples
2325 of 16-byte return values are: 128-bit integers and 16-byte small
2326 structures (excluding homogeneous floating-point aggregates). */
2330 /* Up to four fp/simd registers can return a function value, e.g. a
2331 homogeneous floating-point aggregate having four members. */
2336 }
2338 /* Implement TARGET_RETURN_IN_MEMORY.
2340 If the type T of the result of a function is such that
2341 void func (T arg)
2342 would require that arg be passed as a value in a register (or set of
2343 registers) according to the parameter passing rules, then the result
2344 is returned in the same registers as would be used for such an
2345 argument. */
2347 static bool
2349 {
2350 HOST_WIDE_INT size;
2351 machine_mode ag_mode;
2357 /* Simple scalar types always returned in registers. */
2361 type,
2364 NULL))
2367 /* Types larger than 2 registers returned in memory. */
2370 }
2372 static bool
2375 {
2378 type,
2380 nregs,
2381 NULL);
2382 }
2384 /* Given MODE and TYPE of a function argument, return the alignment in
2385 bits. The idea is to suppress any stronger alignment requested by
2386 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
2387 This is a helper function for local use only. */
2389 static unsigned int
2391 {
2412 }
2414 /* Layout a function argument according to the AAPCS64 rules. The rule
2415 numbers refer to the rule numbers in the AAPCS64. */
2417 static void
2419 const_tree type,
2421 {
2425 HOST_WIDE_INT size;
2427 /* We need to do this once per argument. */
2433 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
2434 size
2436 UNITS_PER_WORD);
2440 mode,
2441 type,
2444 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
2445 The following code thus handles passing by SIMD/FP registers first. */
2449 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
2450 and homogenous short-vector aggregates (HVA). */
2452 {
2457 {
2460 {
2463 }
2464 else
2465 {
2466 rtx par;
2470 {
2473 tmp = gen_rtx_EXPR_LIST
2477 }
2479 }
2481 }
2482 else
2483 {
2484 /* C.3 NSRN is set to 8. */
2487 }
2488 }
2493 /* C6 - C9. though the sign and zero extension semantics are
2494 handled elsewhere. This is the case where the argument fits
2495 entirely general registers. */
2497 {
2501 /* C.8 if the argument has an alignment of 16 then the NGRN is
2502 rounded up to the next even number. */
2505 /* The == 16 * BITS_PER_UNIT instead of >= 16 * BITS_PER_UNIT
2506 comparison is there because for > 16 * BITS_PER_UNIT
2507 alignment nregs should be > 2 and therefore it should be
2508 passed by reference rather than value. */
2510 {
2513 }
2515 /* NREGS can be 0 when e.g. an empty structure is to be passed.
2516 A reg is still generated for it, but the caller should be smart
2517 enough not to use it. */
2520 else
2521 {
2522 rtx par;
2527 {
2532 }
2534 }
2538 }
2540 /* C.11 */
2543 /* The argument is passed on stack; record the needed number of words for
2544 this argument and align the total size if necessary. */
2545 on_stack:
2552 }
2554 /* Implement TARGET_FUNCTION_ARG. */
2556 static rtx
2559 {
2568 }
2570 void
2572 const_tree fntype ATTRIBUTE_UNUSED,
2573 rtx libname ATTRIBUTE_UNUSED,
2574 const_tree fndecl ATTRIBUTE_UNUSED,
2576 {
2590 {
2597 }
2599 }
2601 static void
2603 machine_mode mode,
2604 const_tree type,
2606 {
2609 {
2619 }
2620 }
2622 bool
2624 {
2627 }
2629 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2630 PARM_BOUNDARY bits of alignment, but will be given anything up
2631 to STACK_BOUNDARY bits if the type requires it. This makes sure
2632 that both before and after the layout of each argument, the Next
2633 Stacked Argument Address (NSAA) will have a minimum alignment of
2634 8 bytes. */
2636 static unsigned int
2638 {
2641 }
2643 /* Implement TARGET_FUNCTION_ARG_PADDING.
2645 Small aggregate types are placed in the lowest memory address.
2647 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2649 static pad_direction
2651 {
2652 /* On little-endian targets, the least significant byte of every stack
2653 argument is passed at the lowest byte address of the stack slot. */
2657 /* Otherwise, integral, floating-point and pointer types are padded downward:
2658 the least significant byte of a stack argument is passed at the highest
2659 byte address of the stack slot. */
2666 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2668 }
2670 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2672 It specifies padding for the last (may also be the only)
2673 element of a block move between registers and memory. If
2674 assuming the block is in the memory, padding upward means that
2675 the last element is padded after its highest significant byte,
2676 while in downward padding, the last element is padded at the
2677 its least significant byte side.
2679 Small aggregates and small complex types are always padded
2680 upwards.
2682 We don't need to worry about homogeneous floating-point or
2683 short-vector aggregates; their move is not affected by the
2684 padding direction determined here. Regardless of endianness,
2685 each element of such an aggregate is put in the least
2686 significant bits of a fp/simd register.
2688 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2689 register has useful data, and return the opposite if the most
2690 significant byte does. */
2692 bool
2695 {
2697 /* Small composite types are always padded upward. */
2699 {
2704 }
2706 /* Otherwise, use the default padding. */
2708 }
2710 static scalar_int_mode
2712 {
2714 }
2716 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
2718 /* We use the 12-bit shifted immediate arithmetic instructions so values
2719 must be multiple of (1 << 12), i.e. 4096. */
2720 #define ARITH_FACTOR 4096
2722 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
2723 #error Cannot use simple address calculation for stack probing
2724 #endif
2726 /* The pair of scratch registers used for stack probing. */
2727 #define PROBE_STACK_FIRST_REG 9
2728 #define PROBE_STACK_SECOND_REG 10
2730 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
2731 inclusive. These are offsets from the current stack pointer. */
2733 static void
2735 {
2738 /* See the same assertion on PROBE_INTERVAL above. */
2741 /* See if we have a constant small number of probes to generate. If so,
2742 that's the easy case. */
2744 {
2751 }
2753 /* The run-time loop is made up of 8 insns in the generic case while the
2754 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
2756 {
2761 stack_pointer_rtx,
2765 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
2766 it exceeds SIZE. If only two probes are needed, this will not
2767 generate any code. Then probe at FIRST + SIZE. */
2769 {
2773 }
2777 {
2782 }
2783 else
2785 }
2787 /* Otherwise, do the same as above, but in a loop. Note that we must be
2788 extra careful with variables wrapping around because we might be at
2789 the very top (or the very bottom) of the address space and we have
2790 to be able to handle this case properly; in particular, we use an
2791 equality test for the loop condition. */
2792 else
2793 {
2796 /* Step 1: round SIZE to the previous multiple of the interval. */
2801 /* Step 2: compute initial and final value of the loop counter. */
2803 /* TEST_ADDR = SP + FIRST. */
2807 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
2810 {
2814 }
2815 else
2816 {
2819 }
2821 /* Step 3: the loop
2823 do
2824 {
2825 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
2826 probe at TEST_ADDR
2827 }
2828 while (TEST_ADDR != LAST_ADDR)
2830 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
2831 until it is equal to ROUNDED_SIZE. */
2836 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
2837 that SIZE is equal to ROUNDED_SIZE. */
2840 {
2844 {
2849 }
2850 else
2852 }
2853 }
2855 /* Make sure nothing is scheduled before we are done. */
2857 }
2859 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
2860 absolute addresses. */
2864 {
2871 /* Loop. */
2874 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
2879 /* Probe at TEST_ADDR. */
2882 /* Test if TEST_ADDR == LAST_ADDR. */
2886 /* Branch. */
2892 }
2894 /* Mark the registers that need to be saved by the callee and calculate
2895 the size of the callee-saved registers area and frame record (both FP
2896 and LR may be omitted). */
2897 static void
2899 {
2906 /* Force a frame chain for EH returns so the return address is at FP+8. */
2910 /* Emit a frame chain if the frame pointer is enabled.
2911 If -momit-leaf-frame-pointer is used, do not use a frame chain
2912 in leaf functions which do not use LR. */
2918 #define SLOT_NOT_REQUIRED (-2)
2919 #define SLOT_REQUIRED (-1)
2924 /* First mark all the registers that really need to be saved... */
2931 /* ... that includes the eh data registers (if needed)... */
2937 /* ... and any callee saved register that dataflow says is live. */
2947 {
2950 }
2953 {
2954 /* FP and LR are placed in the linkage record. */
2960 }
2962 /* Now assign stack slots for them. */
2965 {
2972 }
2980 {
2981 /* If there is an alignment gap between integer and fp callee-saves,
2982 allocate the last fp register to it if possible. */
2984 {
2987 }
2996 }
3002 HOST_WIDE_INT varargs_and_saved_regs_size
3029 {
3030 /* Simple, small frame with no outgoing arguments:
3031 stp reg1, reg2, [sp, -frame_size]!
3032 stp reg3, reg4, [sp, 16] */
3034 }
3039 {
3040 /* Frame with small outgoing arguments:
3041 sub sp, sp, frame_size
3042 stp reg1, reg2, [sp, outgoing_args_size]
3043 stp reg3, reg4, [sp, outgoing_args_size + 16] */
3047 }
3049 {
3050 /* Frame with large outgoing arguments but a small local area:
3051 stp reg1, reg2, [sp, -hard_fp_offset]!
3052 stp reg3, reg4, [sp, 16]
3053 sub sp, sp, outgoing_args_size */
3057 }
3058 else
3059 {
3060 /* Frame with large local area and outgoing arguments using frame pointer:
3061 sub sp, sp, hard_fp_offset
3062 stp x29, x30, [sp, 0]
3063 add x29, sp, 0
3064 stp reg3, reg4, [sp, 16]
3065 sub sp, sp, outgoing_args_size */
3069 }
3072 }
3074 /* Return true if the register REGNO is saved on entry to
3075 the current function. */
3077 static bool
3079 {
3081 }
3083 /* Return the next register up from REGNO up to LIMIT for the callee
3084 to save. */
3086 static unsigned
3088 {
3090 regno ++;
3092 }
3094 /* Push the register number REGNO of mode MODE to the stack with write-back
3095 adjusting the stack by ADJUSTMENT. */
3097 static void
3099 HOST_WIDE_INT adjustment)
3100 {
3111 }
3113 /* Generate and return an instruction to store the pair of registers
3114 REG and REG2 of mode MODE to location BASE with write-back adjusting
3115 the stack location BASE by ADJUSTMENT. */
3117 static rtx
3119 HOST_WIDE_INT adjustment)
3120 {
3122 {
3133 }
3134 }
3136 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
3137 stack pointer by ADJUSTMENT. */
3139 static void
3141 {
3156 }
3158 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
3159 adjusting it by ADJUSTMENT afterwards. */
3161 static rtx
3163 HOST_WIDE_INT adjustment)
3164 {
3166 {
3175 }
3176 }
3178 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
3179 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
3180 into CFI_OPS. */
3182 static void
3185 {
3192 {
3196 }
3197 else
3198 {
3203 }
3204 }
3206 /* Generate and return a store pair instruction of mode MODE to store
3207 register REG1 to MEM1 and register REG2 to MEM2. */
3209 static rtx
3211 rtx reg2)
3212 {
3214 {
3223 }
3224 }
3226 /* Generate and regurn a load pair isntruction of mode MODE to load register
3227 REG1 from MEM1 and register REG2 from MEM2. */
3229 static rtx
3231 rtx mem2)
3232 {
3234 {
3243 }
3244 }
3246 /* Return TRUE if return address signing should be enabled for the current
3247 function, otherwise return FALSE. */
3249 bool
3251 {
3252 /* This function should only be called after frame laid out. */
3255 /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
3256 if it's LR is pushed onto stack. */
3260 }
3262 /* Emit code to save the callee-saved registers from register number START
3263 to LIMIT to the stack at the location starting at offset START_OFFSET,
3264 skipping any write-back candidates if SKIP_WB is true. */
3266 static void
3269 {
3277 {
3279 HOST_WIDE_INT offset;
3292 offset));
3301 {
3303 rtx mem2;
3307 offset));
3309 reg2));
3311 /* The first part of a frame-related parallel insn is
3312 always assumed to be relevant to the frame
3313 calculations; subsequent parts, are only
3314 frame-related if explicitly marked. */
3317 }
3318 else
3322 }
3323 }
3325 /* Emit code to restore the callee registers of mode MODE from register
3326 number START up to and including LIMIT. Restore from the stack offset
3327 START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
3328 Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */
3330 static void
3334 {
3338 HOST_WIDE_INT offset;
3343 {
3364 {
3366 rtx mem2;
3374 }
3375 else
3378 }
3379 }
3383 HOST_WIDE_INT offset)
3384 {
3386 }
3390 {
3394 }
3396 bool
3398 {
3402 }
3404 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
3406 static sbitmap
3408 {
3414 /* The registers we need saved to the frame. */
3417 {
3422 /* Check that we can access the stack slot of the register with one
3423 direct load with no adjustments needed. */
3426 }
3428 /* Don't mess with the hard frame pointer. */
3434 /* If aarch64_layout_frame has chosen registers to store/restore with
3435 writeback don't interfere with them to avoid having to output explicit
3436 stack adjustment instructions. */
3446 }
3448 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
3450 static sbitmap
3452 {
3460 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
3469 }
3471 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
3472 Nothing to do for aarch64. */
3474 static void
3476 {
3477 }
3479 /* Return the next set bit in BMP from START onwards. Return the total number
3480 of bits in BMP if no set bit is found at or after START. */
3482 static unsigned int
3484 {
3495 }
3497 /* Do the work for aarch64_emit_prologue_components and
3498 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
3499 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
3500 for these components or the epilogue sequence. That is, it determines
3501 whether we should emit stores or loads and what kind of CFA notes to attach
3502 to the insns. Otherwise the logic for the two sequences is very
3503 similar. */
3505 static void
3507 {
3509 ? HARD_FRAME_POINTER_REGNUM
3517 {
3518 /* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
3519 so DFmode for the vector registers is enough. */
3531 /* No more registers to handle after REGNO.
3532 Emit a single save/restore and exit. */
3534 {
3539 else
3542 }
3545 /* The next register is not of the same class or its offset is not
3546 mergeable with the current one into a pair. */
3551 {
3556 else
3561 }
3563 /* REGNO2 can be saved/restored in a pair with REGNO. */
3575 else
3580 {
3583 }
3584 else
3585 {
3588 }
3591 }
3592 }
3594 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
3596 static void
3598 {
3600 }
3602 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
3604 static void
3606 {
3608 }
3610 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
3612 static void
3614 {
3618 }
3620 /* AArch64 stack frames generated by this compiler look like:
3622 +-------------------------------+
3623 | |
3624 | incoming stack arguments |
3625 | |
3626 +-------------------------------+
3627 | | <-- incoming stack pointer (aligned)
3628 | callee-allocated save area |
3629 | for register varargs |
3630 | |
3631 +-------------------------------+
3632 | local variables | <-- frame_pointer_rtx
3633 | |
3634 +-------------------------------+
3635 | padding0 | \
3636 +-------------------------------+ |
3637 | callee-saved registers | | frame.saved_regs_size
3638 +-------------------------------+ |
3639 | LR' | |
3640 +-------------------------------+ |
3641 | FP' | / <- hard_frame_pointer_rtx (aligned)
3642 +-------------------------------+
3643 | dynamic allocation |
3644 +-------------------------------+
3645 | padding |
3646 +-------------------------------+
3647 | outgoing stack arguments | <-- arg_pointer
3648 | |
3649 +-------------------------------+
3650 | | <-- stack_pointer_rtx (aligned)
3652 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
3653 but leave frame_pointer_rtx and hard_frame_pointer_rtx
3654 unchanged. */
3656 /* Generate the prologue instructions for entry into a function.
3657 Establish the stack frame by decreasing the stack pointer with a
3658 properly calculated size and, if necessary, create a frame record
3659 filled with the values of LR and previous frame pointer. The
3660 current FP is also set up if it is in use. */
3662 void
3664 {
3677 /* Sign return address for functions. */
3679 {
3683 }
3689 {
3691 {
3695 (frame_size
3697 }
3700 }
3708 {
3713 stack_pointer_rtx,
3717 }
3724 }
3726 /* Return TRUE if we can use a simple_return insn.
3728 This function checks whether the callee saved stack is empty, which
3729 means no restore actions are need. The pro_and_epilogue will use
3730 this to check whether shrink-wrapping opt is feasible. */
3732 bool
3734 {
3744 }
3746 /* Generate the epilogue instructions for returning from a function.
3747 This is almost exactly the reverse of the prolog sequence, except
3748 that we need to insert barriers to avoid scheduling loads that read
3749 from a deallocated stack, and we optimize the unwind records by
3750 emitting them all together if possible. */
3751 void
3753 {
3765 /* We need to add memory barrier to prevent read from deallocated stack. */
3769 /* Emit a barrier to prevent loads from a deallocated stack. */
3772 {
3775 }
3777 /* Restore the stack pointer from the frame pointer if it may not
3778 be the same as the stack pointer. */
3780 {
3782 hard_frame_pointer_rtx,
3784 /* If writeback is used when restoring callee-saves, the CFA
3785 is restored on the instruction doing the writeback. */
3787 }
3788 else
3803 {
3804 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
3810 }
3815 {
3816 /* Emit delayed restores and reset the CFA to be SP. */
3821 }
3823 /* We prefer to emit the combined return/authenticate instruction RETAA,
3824 however there are three cases in which we must instead emit an explicit
3825 authentication instruction.
3827 1) Sibcalls don't return in a normal way, so if we're about to call one
3828 we must authenticate.
3830 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
3831 generating code for !TARGET_ARMV8_3 we can't use it and must
3832 explicitly authenticate.
3834 3) On an eh_return path we make extra stack adjustments to update the
3835 canonical frame address to be the exception handler's CFA. We want
3836 to authenticate using the CFA of the function which calls eh_return.
3837 */
3840 {
3844 }
3846 /* Stack adjustment for exception handler. */
3848 {
3849 /* We need to unwind the stack by the offset computed by
3850 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
3851 to be SP; letting the CFA move during this adjustment
3852 is just as correct as retaining the CFA from the body
3853 of the function. Therefore, do nothing special. */
3855 }
3860 }
3862 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
3863 normally or return to a previous frame after unwinding.
3865 An EH return uses a single shared return sequence. The epilogue is
3866 exactly like a normal epilogue except that it has an extra input
3867 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
3868 that must be applied after the frame has been destroyed. An extra label
3869 is inserted before the epilogue which initializes this register to zero,
3870 and this is the entry point for a normal return.
3872 An actual EH return updates the return address, initializes the stack
3873 adjustment and jumps directly into the epilogue (bypassing the zeroing
3874 of the adjustment). Since the return address is typically saved on the
3875 stack when a function makes a call, the saved LR must be updated outside
3876 the epilogue.
3878 This poses problems as the store is generated well before the epilogue,
3879 so the offset of LR is not known yet. Also optimizations will remove the
3880 store as it appears dead, even after the epilogue is generated (as the
3881 base or offset for loading LR is different in many cases).
3883 To avoid these problems this implementation forces the frame pointer
3884 in eh_return functions so that the location of LR is fixed and known early.
3885 It also marks the store volatile, so no optimization is permitted to
3886 remove the store. */
3887 rtx
3889 {
3893 /* Mark the store volatile, so no optimization is permitted to remove it. */
3896 }
3898 /* Output code to add DELTA to the first argument, and then jump
3899 to FUNCTION. Used for C++ multiple inheritance. */
3900 static void
3902 HOST_WIDE_INT delta,
3903 HOST_WIDE_INT vcall_offset,
3904 tree function)
3905 {
3906 /* The this pointer is always in x0. Note that this differs from
3907 Arm where the this pointer maybe bumped to r1 if r0 is required
3908 to return a pointer to an aggregate. On AArch64 a result value
3909 pointer will be in x8. */
3919 else
3920 {
3929 {
3933 else
3935 }
3939 else
3946 else
3947 {
3949 Pmode);
3951 }
3955 else
3961 }
3963 /* Generate a tail call to the target function. */
3965 {
3968 }
3980 /* Stop pretending to be a post-reload pass. */
3982 }
3984 static bool
3986 {
3991 {
3995 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3996 TLS offsets, not real symbol references. */
3999 }
4001 }
4004 /* Return true if val can be encoded as a 12-bit unsigned immediate with
4005 a left shift of 0 or 12 bits. */
4006 bool
4008 {
4011 );
4012 }
4015 /* Return true if val is an immediate that can be loaded into a
4016 register by a MOVZ instruction. */
4017 static bool
4019 {
4021 {
4025 }
4026 else
4027 {
4028 /* Ignore sign extension. */
4030 }
4033 }
4035 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
4038 {
4044 };
4047 /* Return true if val is a valid bitmask immediate. */
4049 bool
4051 {
4055 /* Check for a single sequence of one bits and return quickly if so.
4056 The special cases of all ones and all zeroes returns false. */
4063 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
4067 /* Invert if the immediate doesn't start with a zero bit - this means we
4068 only need to search for sequences of one bits. */
4072 /* Find the first set bit and set tmp to val with the first sequence of one
4073 bits removed. Return success if there is a single sequence of ones. */
4080 /* Find the next set bit and compute the difference in bit position. */
4085 /* Check the bit position difference is a power of 2, and that the first
4086 sequence of one bits fits within 'bits' bits. */
4090 /* Check the sequence of one bits is repeated 64/bits times. */
4092 }
4094 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
4095 Assumed precondition: VAL_IN Is not zero. */
4097 unsigned HOST_WIDE_INT
4099 {
4106 }
4108 /* Create constant where bits outside of lowest bit set to highest bit set
4109 are set to 1. */
4111 unsigned HOST_WIDE_INT
4113 {
4115 }
4117 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
4119 bool
4121 {
4122 scalar_int_mode int_mode;
4135 }
4137 /* Return true if val is an immediate that can be loaded into a
4138 register in a single instruction. */
4139 bool
4141 {
4142 scalar_int_mode int_mode;
4149 }
4151 static bool
4153 {
4161 {
4165 else
4166 /* Avoid generating a 64-bit relocation in ILP32; leave
4167 to aarch64_expand_mov_immediate to handle it properly. */
4169 }
4172 }
4174 /* Implement TARGET_CASE_VALUES_THRESHOLD.
4175 The expansion for a table switch is quite expensive due to the number
4176 of instructions, the table lookup and hard to predict indirect jump.
4177 When optimizing for speed, and -O3 enabled, use the per-core tuning if
4178 set, otherwise use tables for > 16 cases as a tradeoff between size and
4179 performance. When optimizing for size, use the default setting. */
4181 static unsigned int
4183 {
4184 /* Use the specified limit for the number of cases before using jump
4185 tables at higher optimization levels. */
4189 else
4191 }
4193 /* Return true if register REGNO is a valid index register.
4194 STRICT_P is true if REG_OK_STRICT is in effect. */
4196 bool
4198 {
4200 {
4208 }
4210 }
4212 /* Return true if register REGNO is a valid base register for mode MODE.
4213 STRICT_P is true if REG_OK_STRICT is in effect. */
4215 bool
4217 {
4219 {
4227 }
4229 /* The fake registers will be eliminated to either the stack or
4230 hard frame pointer, both of which are usually valid base registers.
4231 Reload deals with the cases where the eliminated form isn't valid. */
4236 }
4238 /* Return true if X is a valid base register for mode MODE.
4239 STRICT_P is true if REG_OK_STRICT is in effect. */
4241 static bool
4243 {
4250 }
4252 /* Return true if address offset is a valid index. If it is, fill in INFO
4253 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
4255 static bool
4258 {
4260 rtx index;
4263 /* (reg:P) */
4266 {
4270 }
4271 /* (sign_extend:DI (reg:SI)) */
4276 {
4281 }
4282 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
4289 {
4294 }
4295 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
4302 {
4307 }
4308 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
4315 {
4323 }
4324 /* (and:DI (mult:DI (reg:DI) (const_int scale))
4325 (const_int 0xffffffff<<shift)) */
4332 {
4338 }
4339 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
4346 {
4354 }
4355 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
4356 (const_int 0xffffffff<<shift)) */
4363 {
4369 }
4370 /* (mult:P (reg:P) (const_int scale)) */
4375 {
4379 }
4380 /* (ashift:P (reg:P) (const_int shift)) */
4385 {
4389 }
4390 else
4403 {
4408 }
4411 }
4413 /* Return true if MODE is one of the modes for which we
4414 support LDP/STP operations. */
4416 static bool
4418 {
4423 }
4425 /* Return true if REGNO is a virtual pointer register, or an eliminable
4426 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
4427 include stack_pointer or hard_frame_pointer. */
4428 static bool
4430 {
4435 }
4437 /* Return true if X is a valid address for machine mode MODE. If it is,
4438 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
4439 effect. OUTER_CODE is PARALLEL for a load/store pair. */
4441 static bool
4445 {
4449 /* On BE, we use load/store pair for all large int mode load/stores.
4450 TI/TFmode may also use a load/store pair. */
4454 || (BYTES_BIG_ENDIAN
4458 !load_store_pair_p
4462 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
4463 REG addressing. */
4469 {
4485 {
4491 }
4496 {
4503 /* TImode and TFmode values are allowed in both pairs of X
4504 registers and individual Q registers. The available
4505 address modes are:
4506 X,X: 7-bit signed scaled offset
4507 Q: 9-bit signed offset
4508 We conservatively require an offset representable in either mode.
4509 When performing the check for pairs of X registers i.e. LDP/STP
4510 pass down DImode since that is the natural size of the LDP/STP
4511 instruction memory accesses. */
4517 /* A 7bit offset check because OImode will emit a ldp/stp
4518 instruction (only big endian will get here).
4519 For ldp/stp instructions, the offset is scaled for the size of a
4520 single element of the pair. */
4524 /* Three 9/12 bit offsets checks because CImode will emit three
4525 ldr/str instructions (only big endian will get here). */
4532 /* Two 7bit offsets checks because XImode will emit two ldp/stp
4533 instructions (only big endian will get here). */
4542 else
4545 }
4548 {
4549 /* Look for base + (scaled/extended) index register. */
4552 {
4555 }
4558 {
4561 }
4562 }
4583 {
4584 HOST_WIDE_INT offset;
4588 /* TImode and TFmode values are allowed in both pairs of X
4589 registers and individual Q registers. The available
4590 address modes are:
4591 X,X: 7-bit signed scaled offset
4592 Q: 9-bit signed offset
4593 We conservatively require an offset representable in either mode.
4594 */
4602 else
4604 }
4610 /* load literal: pc-relative constant pool entry. Only supported
4611 for SI mode or larger. */
4615 {
4623 }
4632 {
4637 {
4638 /* The symbol and offset must be aligned to the access size. */
4645 {
4649 }
4655 else
4664 }
4665 }
4670 }
4671 }
4673 /* Return true if the address X is valid for a PRFM instruction.
4674 STRICT_P is true if we should do strict checking with
4675 aarch64_classify_address. */
4677 bool
4679 {
4682 /* PRFM accepts the same addresses as DImode... */
4687 /* ... except writeback forms. */
4689 }
4691 bool
4693 {
4694 rtx offset;
4698 }
4700 /* Classify the base of symbolic expression X. */
4702 enum aarch64_symbol_type
4704 {
4705 rtx offset;
4709 }
4712 /* Return TRUE if X is a legitimate address for accessing memory in
4713 mode MODE. */
4714 static bool
4716 {
4720 }
4722 /* Return TRUE if X is a legitimate address for accessing memory in
4723 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
4724 pair operation. */
4725 bool
4728 {
4732 }
4734 /* Split an out-of-range address displacement into a base and offset.
4735 Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise
4736 to increase opportunities for sharing the base address of different sizes.
4737 Unaligned accesses use the signed 9-bit range, TImode/TFmode use
4738 the intersection of signed scaled 7-bit and signed 9-bit offset. */
4739 static bool
4741 {
4743 HOST_WIDE_INT base;
4749 else
4755 }
4757 /* Return the binary representation of floating point constant VALUE in INTVAL.
4758 If the value cannot be converted, return false without setting INTVAL.
4759 The conversion is done in the given MODE. */
4760 bool
4762 {
4764 /* We make a general exception for 0. */
4766 {
4769 }
4775 /* Only support up to DF mode. */
4787 {
4791 }
4792 else
4797 }
4799 /* Return TRUE if rtx X is an immediate constant that can be moved using a
4800 single MOV(+MOVK) followed by an FMOV. */
4801 bool
4803 {
4808 /* Determine whether it's cheaper to write float constants as
4809 mov/movk pairs over ldr/adrp pairs. */
4815 {
4817 ? SImode
4822 }
4825 }
4827 /* Return TRUE if rtx X is immediate constant 0.0 */
4828 bool
4830 {
4837 }
4839 /* Return TRUE if rtx X is immediate constant that fits in a single
4840 MOVI immediate operation. */
4841 bool
4843 {
4847 machine_mode vmode;
4848 scalar_int_mode imode;
4853 {
4857 /* We make a general exception for 0. */
4862 }
4866 else
4869 /* use a 64 bit mode for everything except for DI/DF mode, where we use
4870 a 128 bit vector mode. */
4877 }
4880 /* Return the fixed registers used for condition codes. */
4882 static bool
4884 {
4888 }
4890 /* This function is used by the call expanders of the machine description.
4891 RESULT is the register in which the result is returned. It's NULL for
4892 "call" and "sibcall".
4893 MEM is the location of the function call.
4894 SIBCALL indicates whether this function call is normal call or sibling call.
4895 It will generate different pattern accordingly. */
4897 void
4899 {
4901 rtvec vec;
4902 machine_mode mode;
4909 /* Decide if we should generate indirect calls by loading the
4910 address of the callee into a register before performing
4911 the branch-and-link. */
4925 else
4932 }
4934 /* Emit call insn with PAT and do aarch64-specific handling. */
4936 void
4938 {
4944 }
4946 machine_mode
4948 {
4949 /* All floating point compares return CCFP if it is an equality
4950 comparison, and CCFPE otherwise. */
4952 {
4954 {
4975 }
4976 }
4978 /* Equality comparisons of short modes against zero can be performed
4979 using the TST instruction with the appropriate bitmask. */
4985 /* Similarly, comparisons of zero_extends from shorter modes can
4986 be performed using an ANDS with an immediate mask. */
5002 /* A compare with a shifted operand. Because of canonicalization,
5003 the comparison will have to be swapped when we emit the assembly
5004 code. */
5012 /* Similarly for a negated operand, but we can only do this for
5013 equalities. */
5020 /* A test for unsigned overflow. */
5027 /* For everything else, return CCmode. */
5029 }
5031 static int
5034 int
5036 {
5043 }
5045 static int
5047 {
5049 {
5053 {
5067 }
5072 {
5084 }
5089 {
5101 }
5106 {
5112 }
5117 {
5121 }
5126 {
5130 }
5135 }
5138 }
5140 bool
5142 HOST_WIDE_INT minval,
5143 HOST_WIDE_INT maxval)
5144 {
5145 HOST_WIDE_INT firstval;
5162 }
5164 bool
5166 {
5168 }
5171 /* N Z C V. */
5172 #define AARCH64_CC_V 1
5173 #define AARCH64_CC_C (1 << 1)
5174 #define AARCH64_CC_Z (1 << 2)
5175 #define AARCH64_CC_N (1 << 3)
5177 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
5179 {
5196 };
5198 /* Print operand X to file F in a target specific manner according to CODE.
5199 The acceptable formatting commands given by CODE are:
5200 'c': An integer or symbol address without a preceding #
5201 sign.
5202 'e': Print the sign/zero-extend size as a character 8->b,
5203 16->h, 32->w.
5204 'p': Prints N such that 2^N == X (X must be power of 2 and
5205 const int).
5206 'P': Print the number of non-zero bits in X (a const_int).
5207 'H': Print the higher numbered register of a pair (TImode)
5208 of regs.
5209 'm': Print a condition (eq, ne, etc).
5210 'M': Same as 'm', but invert condition.
5211 'b/h/s/d/q': Print a scalar FP/SIMD register name.
5212 'S/T/U/V': Print a FP/SIMD register name for a register list.
5213 The register printed is the FP/SIMD register name
5214 of X + 0/1/2/3 for S/T/U/V.
5215 'R': Print a scalar FP/SIMD register name + 1.
5216 'X': Print bottom 16 bits of integer constant in hex.
5217 'w/x': Print a general register name or the zero register
5218 (32-bit or 64-bit).
5219 '0': Print a normal operand, if it's a general register,
5220 then we assume DImode.
5221 'k': Print NZCV for conditional compare instructions.
5222 'A': Output address constant representing the first
5223 argument of X, specifying a relocation offset
5224 if appropriate.
5225 'L': Output constant address specified by X
5226 with a relocation offset if appropriate.
5227 'G': Prints address of X, specifying a PC relative
5228 relocation mode if appropriate. */
5230 static void
5232 {
5234 {
5237 {
5249 {
5252 }
5253 /* Fall through. */
5257 }
5261 {
5266 {
5269 }
5272 {
5285 }
5286 }
5290 {
5294 {
5297 }
5300 }
5305 {
5308 }
5315 {
5318 }
5325 {
5327 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
5329 {
5333 }
5336 {
5339 }
5346 }
5355 {
5356 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5358 }
5367 {
5368 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5370 }
5376 {
5377 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5379 }
5385 {
5388 }
5396 {
5399 }
5402 {
5405 }
5408 {
5411 }
5413 /* Fall through */
5417 {
5420 }
5423 {
5430 /* Check all memory references are Pmode - even with ILP32. */
5446 {
5449 HOST_WIDE_INT_MIN,
5450 HOST_WIDE_INT_MAX));
5452 }
5454 {
5456 }
5457 else
5462 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
5463 be getting CONST_DOUBLEs holding integers. */
5466 {
5469 }
5471 {
5472 #define buf_size 20
5480 #undef buf_size
5481 }
5487 }
5495 {
5522 }
5528 {
5563 }
5569 {
5575 }
5580 {
5581 HOST_WIDE_INT cond_code;
5584 {
5587 }
5592 }
5598 }
5599 }
5601 static void
5603 {
5608 {
5612 else
5621 else
5630 else
5639 else
5646 {
5673 }
5684 }
5687 }
5689 bool
5691 {
5698 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
5699 referencing instruction, but they are constant offsets, not
5700 symbols. */
5706 {
5708 {
5714 }
5717 }
5720 }
5722 /* Implement REGNO_REG_CLASS. */
5724 enum reg_class
5726 {
5741 }
5743 static rtx
5745 {
5746 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
5747 where mask is selected by alignment and size of the offset.
5748 We try to pick as large a range for the offset as possible to
5749 maximize the chance of a CSE. However, for aligned addresses
5750 we limit the range to 4k so that structures with different sized
5751 elements are likely to use the same base. We need to be careful
5752 not to split a CONST for some forms of address expression, otherwise
5753 it will generate sub-optimal code. */
5756 {
5762 {
5766 /* Force any scaling into a temp for CSE. */
5770 /* Let the pointer register be in op0. */
5774 /* If the pointer is virtual or frame related, then we know that
5775 virtual register instantiation or register elimination is going
5776 to apply a second constant. We want the two constants folded
5777 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
5779 {
5783 }
5785 /* Otherwise, in order to encourage CSE (and thence loop strength
5786 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
5790 }
5792 /* Does it look like we'll need a 16-byte load/store-pair operation? */
5793 HOST_WIDE_INT base_offset;
5796 /* For offsets aren't a multiple of the access size, the limit is
5797 -256...255. */
5799 {
5802 /* BLKmode typically uses LDP of X-registers. */
5805 }
5806 /* Small negative offsets are supported. */
5811 /* Use 12-bit offset by access size. */
5812 else
5816 {
5820 }
5821 }
5824 }
5826 /* Return the reload icode required for a constant pool in mode. */
5827 static enum insn_code
5829 {
5831 {
5867 }
5870 }
5871 static reg_class_t
5873 reg_class_t rclass,
5874 machine_mode mode,
5876 {
5878 /* If we have to disable direct literal pool loads and stores because the
5879 function is too big, then we need a scratch register. */
5884 {
5887 }
5889 /* Without the TARGET_SIMD instructions we cannot move a Q register
5890 to a Q register directly. We need a scratch. */
5894 {
5900 }
5902 /* A TFmode or TImode memory access should be handled via an FP_REGS
5903 because AArch64 has richer addressing modes for LDR/STR instructions
5904 than LDP/STP instructions. */
5913 }
5915 static bool
5917 {
5918 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
5919 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
5922 {
5934 }
5937 }
5939 HOST_WIDE_INT
5941 {
5945 {
5952 }
5955 {
5959 }
5962 }
5964 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
5965 previous frame. */
5967 rtx
5969 {
5973 }
5976 static void
5978 {
5980 {
5983 }
5984 else
5985 {
5988 }
5993 }
5995 static void
5997 {
6001 /* Don't need to copy the trailing D-words, we fill those in below. */
6013 /* XXX We should really define a "clear_cache" pattern and use
6014 gen_clear_cache(). */
6019 ptr_mode);
6020 }
6022 static unsigned char
6024 {
6026 {
6034 return
6046 }
6048 }
6050 static reg_class_t
6052 {
6057 {
6063 }
6065 /* Register eliminiation can result in a request for
6066 SP+constant->FP_REGS. We cannot support such operations which
6067 use SP as source and an FP_REG as destination, so reject out
6068 right now. */
6070 {
6073 /* Look through a possible SUBREG introduced by ILP32. */
6079 POINTER_REGS));
6081 }
6084 }
6086 void
6088 {
6090 }
6092 static void
6094 {
6097 else
6098 {
6100 /* While priority is known to be in range [0, 65535], so 18 bytes
6101 would be enough, the compiler might not know that. To avoid
6102 -Wformat-truncation false positive, use a larger size. */
6109 }
6110 }
6112 static void
6114 {
6117 else
6118 {
6120 /* While priority is known to be in range [0, 65535], so 18 bytes
6121 would be enough, the compiler might not know that. To avoid
6122 -Wformat-truncation false positive, use a larger size. */
6129 }
6130 }
6134 {
6140 {
6141 {
6144 },
6145 {
6148 },
6149 {
6152 },
6153 /* We assume that DImode is only generated when not optimizing and
6154 that we don't really need 64-bit address offsets. That would
6155 imply an object file with 8GB of code in a single function! */
6156 {
6159 }
6160 };
6169 /* Need to implement table size reduction, by chaning the code below. */
6179 }
6182 /* Return size in bits of an arithmetic operand which is shifted/scaled and
6183 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
6184 operator. */
6186 int
6188 {
6190 {
6193 {
6197 }
6198 }
6200 }
6202 /* Constant pools are per function only when PC relative
6203 literal loads are true or we are in the large memory
6204 model. */
6208 {
6211 }
6213 static bool
6215 {
6216 /* Fixme:: In an ideal world this would work similar
6217 to the logic in aarch64_select_rtx_section but this
6218 breaks bootstrap in gcc go. For now we workaround
6219 this by returning false here. */
6221 }
6223 /* Select appropriate section for constants depending
6224 on where we place literal pools. */
6228 rtx x,
6230 {
6235 }
6237 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
6238 void
6240 HOST_WIDE_INT offset)
6241 {
6242 /* When using per-function literal pools, we must ensure that any code
6243 section is aligned to the minimal instruction length, lest we get
6244 errors from the assembler re "unaligned instructions". */
6247 }
6249 /* Costs. */
6251 /* Helper function for rtx cost calculation. Strip a shift expression
6252 from X. Returns the inner operand if successful, or the original
6253 expression on failure. */
6254 static rtx
6256 {
6259 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
6260 we can convert both to ROR during final output. */
6275 }
6277 /* Helper function for rtx cost calculation. Strip an extend
6278 expression from X. Returns the inner operand if successful, or the
6279 original expression on failure. We deal with a number of possible
6280 canonicalization variations here. If STRIP_SHIFT is true, then
6281 we can strip off a shift also. */
6282 static rtx
6284 {
6285 scalar_int_mode mode;
6291 /* Zero and sign extraction of a widened value. */
6299 /* It can also be represented (for zero-extend) as an AND with an
6300 immediate. */
6309 /* Now handle extended register, as this may also have an optional
6310 left shift by 1..4. */
6325 }
6327 /* Return true iff CODE is a shift supported in combination
6328 with arithmetic instructions. */
6330 static bool
6332 {
6334 }
6337 /* Return true iff X is a cheap shift without a sign extend. */
6339 static bool
6341 {
6367 }
6369 /* Helper function for rtx cost calculation. Calculate the cost of
6370 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
6371 Return the calculated cost of the expression, recursing manually in to
6372 operands where needed. */
6374 static int
6376 {
6392 /* Integer multiply/fma. */
6394 {
6395 /* The multiply will be canonicalized as a shift, cost it as such. */
6399 {
6403 {
6405 {
6406 /* If the shift is considered cheap,
6407 then don't add any cost. */
6409 ;
6411 /* ARITH + shift-by-register. */
6414 /* ARITH + extended register. We don't have a cost field
6415 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
6417 else
6418 /* ARITH + shift-by-immediate. */
6420 }
6421 else
6422 /* LSL (immediate). */
6425 }
6426 /* Strip extends as we will have costed them in the case above. */
6433 }
6435 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
6436 compound and let the below cases handle it. After all, MNEG is a
6437 special-case alias of MSUB. */
6439 {
6442 }
6444 /* Integer multiplies or FMAs have zero/sign extending variants. */
6449 {
6454 {
6456 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
6458 else
6459 /* MUL/SMULL/UMULL. */
6461 }
6464 }
6466 /* This is either an integer multiply or a MADD. In both cases
6467 we want to recurse and cost the operands. */
6472 {
6474 /* MADD/MSUB. */
6476 else
6477 /* MUL. */
6479 }
6482 }
6483 else
6484 {
6486 {
6487 /* Floating-point FMA/FMUL can also support negations of the
6488 operands, unless the rounding mode is upward or downward in
6489 which case FNMUL is different than FMUL with operand negation. */
6493 {
6498 }
6501 /* FMADD/FNMADD/FNMSUB/FMSUB. */
6503 else
6504 /* FMUL/FNMUL. */
6506 }
6511 }
6512 }
6514 static int
6516 machine_mode mode,
6517 addr_space_t as ATTRIBUTE_UNUSED,
6519 {
6527 {
6529 {
6530 /* This is a CONST or SYMBOL ref which will be split
6531 in a different way depending on the code model in use.
6532 Cost it through the generic infrastructure. */
6534 /* Divide through by the cost of one instruction to
6535 bring it to the same units as the address costs. */
6537 /* The cost is then the cost of preparing the address,
6538 followed by an immediate (possibly 0) offset. */
6540 }
6541 else
6542 {
6543 /* This is most likely a jump table from a case
6544 statement. */
6546 }
6547 }
6550 {
6562 else
6581 }
6585 {
6586 /* For the sake of calculating the cost of the shifted register
6587 component, we can treat same sized modes in the same way. */
6589 {
6602 /* We can't tell, or this is a 128-bit vector. */
6606 }
6607 }
6610 }
6612 /* Return the cost of a branch. If SPEED_P is true then the compiler is
6613 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
6614 to be taken. */
6616 int
6618 {
6619 /* When optimizing for speed, use the cost of unpredictable branches. */
6625 else
6627 }
6629 /* Return true if the RTX X in mode MODE is a zero or sign extract
6630 usable in an ADD or SUB (extended register) instruction. */
6631 static bool
6633 {
6634 /* Catch add with a sign extract.
6635 This is add_<optab><mode>_multp2. */
6638 {
6649 op1))
6650 {
6652 }
6653 }
6654 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
6655 No shift. */
6661 }
6663 static bool
6665 {
6667 {
6679 }
6680 }
6682 /* Return true iff X is an rtx that will match an extr instruction
6683 i.e. as described in the *extr<mode>5_insn family of patterns.
6684 OP0 and OP1 will be set to the operands of the shifts involved
6685 on success and will be NULL_RTX otherwise. */
6687 static bool
6689 {
6691 scalar_int_mode mode;
6706 {
6707 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
6719 {
6723 }
6724 }
6727 }
6729 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
6730 storing it in *COST. Result is true if the total cost of the operation
6731 has now been calculated. */
6732 static bool
6734 {
6735 rtx inner;
6736 rtx comparator;
6740 {
6744 }
6745 else
6746 {
6750 }
6753 {
6754 /* Conditional branch. */
6757 else
6758 {
6760 {
6762 {
6763 /* TBZ/TBNZ/CBZ/CBNZ. */
6765 /* TBZ/TBNZ. */
6768 else
6769 /* CBZ/CBNZ. */
6773 }
6774 }
6776 {
6777 /* TBZ/TBNZ. */
6780 }
6781 }
6782 }
6784 {
6785 /* CCMP. */
6787 {
6788 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
6792 {
6799 else
6801 }
6803 }
6805 /* It's a conditional operation based on the status flags,
6806 so it must be some flavor of CSEL. */
6808 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
6814 {
6815 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
6818 }
6823 }
6825 /* We don't know what this is, cost all operands. */
6827 }
6829 /* Check whether X is a bitfield operation of the form shift + extend that
6830 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
6831 operand to which the bitfield operation is applied. Otherwise return
6832 NULL_RTX. */
6834 static rtx
6836 {
6850 {
6868 }
6871 }
6873 /* Return true if the mask and a shift amount from an RTX of the form
6874 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
6875 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
6877 bool
6879 rtx shft_amnt)
6880 {
6885 }
6887 /* Calculate the cost of calculating X, storing it in *COST. Result
6888 is true if the total cost of the operation has now been calculated. */
6889 static bool
6892 {
6897 scalar_int_mode int_mode;
6899 /* By default, assume that everything has equivalent cost to the
6900 cheapest instruction. Any additional costs are applied as a delta
6901 above this default. */
6905 {
6907 /* The cost depends entirely on the operands to SET. */
6913 {
6916 {
6930 }
6939 /* Fall through. */
6941 /* The cost is one per vector-register copied. */
6943 {
6946 }
6947 /* const0_rtx is in general free, but we will use an
6948 instruction to set a register to 0. */
6950 {
6951 /* The cost is 1 per register copied. */
6954 }
6955 else
6956 /* Cost is just the cost of the RHS of the set. */
6962 /* Bit-field insertion. Strip any redundant widening of
6963 the RHS to meet the width of the target. */
6974 {
6975 /* MOV immediate is assumed to always be cheap. */
6977 }
6978 else
6979 {
6980 /* BFM. */
6984 }
6989 /* We can't make sense of this, assume default cost. */
6992 }
6996 /* If an instruction can incorporate a constant within the
6997 instruction, the instruction's expression avoids calling
6998 rtx_cost() on the constant. If rtx_cost() is called on a
6999 constant, then it is usually because the constant must be
7000 moved into a register by one or more instructions.
7002 The exception is constant 0, which can be expressed
7003 as XZR/WZR and is therefore free. The exception to this is
7004 if we have (set (reg) (const0_rtx)) in which case we must cost
7005 the move. However, we can catch that when we cost the SET, so
7006 we don't need to consider that here. */
7009 else
7010 {
7011 /* To an approximation, building any other constant is
7012 proportionally expensive to the number of instructions
7013 required to build that constant. This is true whether we
7014 are compiling for SPEED or otherwise. */
7019 }
7024 /* First determine number of instructions to do the move
7025 as an integer constant. */
7029 {
7035 ? SImode
7041 }
7044 {
7045 /* mov[df,sf]_aarch64. */
7047 /* FMOV (scalar immediate). */
7050 {
7051 /* This will be a load from memory. */
7054 else
7056 }
7057 else
7058 /* Otherwise this is +0.0. We get this using MOVI d0, #0
7059 or MOV v0.s[0], wzr - neither of which are modeled by the
7060 cost tables. Just use the default cost. */
7061 {
7062 }
7063 }
7069 {
7070 /* For loads we want the base cost of a load, plus an
7071 approximation for the additional cost of the addressing
7072 mode. */
7086 }
7094 {
7096 {
7097 /* FNEG. */
7099 }
7101 }
7104 {
7107 {
7108 /* CSETM. */
7111 }
7113 /* Cost this as SUB wzr, X. */
7117 }
7120 {
7121 /* Support (neg(fma...)) as a single instruction only if
7122 sign of zeros is unimportant. This matches the decision
7123 making in aarch64.md. */
7125 {
7126 /* FNMADD. */
7129 }
7131 {
7132 /* FNMUL. */
7135 }
7137 /* FNEG. */
7140 }
7147 {
7150 else
7152 }
7162 {
7166 }
7169 {
7170 /* TODO: A write to the CC flags possibly costs extra, this
7171 needs encoding in the cost tables. */
7174 /* ANDS. */
7176 {
7179 }
7182 {
7183 /* ADDS (and CMN alias). */
7186 }
7189 {
7190 /* SUBS. */
7193 }
7198 {
7199 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
7200 Handle it here directly rather than going to cost_logic
7201 since we know the immediate generated for the TST is valid
7202 so we can avoid creating an intermediate rtx for it only
7203 for costing purposes. */
7210 }
7213 {
7214 /* CMN. */
7221 }
7223 /* CMP.
7225 Compare can freely swap the order of operands, and
7226 canonicalization puts the more complex operation first.
7227 But the integer MINUS logic expects the shift/extend
7228 operation in op1. */
7231 {
7234 }
7236 }
7239 {
7240 /* FCMP. */
7245 {
7247 /* FCMP supports constant 0.0 for no extra cost. */
7249 }
7251 }
7254 {
7255 /* Vector compare. */
7260 {
7261 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
7262 cost. */
7264 }
7266 }
7270 {
7274 cost_minus:
7277 /* Detect valid immediates. */
7283 {
7285 /* SUB(S) (immediate). */
7288 }
7290 /* Look for SUB (extended register). */
7293 {
7301 }
7305 /* Cost this as an FMA-alike operation. */
7309 {
7312 speed);
7314 }
7319 {
7321 {
7322 /* Vector SUB. */
7324 }
7326 {
7327 /* SUB(S). */
7329 }
7331 {
7332 /* FSUB. */
7334 }
7335 }
7337 }
7340 {
7341 rtx new_op0;
7346 cost_plus:
7349 {
7350 /* CSINC. */
7354 }
7359 {
7363 /* ADD (immediate). */
7366 }
7370 /* Look for ADD (extended register). */
7373 {
7381 }
7383 /* Strip any extend, leave shifts behind as we will
7384 cost them through mult_cost. */
7389 {
7391 speed);
7393 }
7398 {
7400 {
7401 /* Vector ADD. */
7403 }
7405 {
7406 /* ADD. */
7408 }
7410 {
7411 /* FADD. */
7413 }
7414 }
7416 }
7422 {
7425 else
7427 }
7432 {
7436 {
7439 else
7441 }
7443 }
7446 {
7453 }
7454 /* Fall through. */
7457 cost_logic:
7462 {
7466 }
7474 {
7475 /* This is a UBFM/SBFM. */
7480 }
7483 {
7485 {
7486 /* We have a mask + shift version of a UBFIZ
7487 i.e. the *andim_ashift<mode>_bfiz pattern. */
7491 {
7498 }
7500 {
7501 /* We possibly get the immediate for free, this is not
7502 modelled. */
7509 }
7510 }
7511 else
7512 {
7515 /* Handle ORN, EON, or BIC. */
7521 /* If we had a shift on op0 then this is a logical-shift-
7522 by-register/immediate operation. Otherwise, this is just
7523 a logical operation. */
7525 {
7527 {
7528 /* Shift by immediate. */
7531 else
7533 }
7534 else
7536 }
7538 /* In both cases we want to cost both operands. */
7545 }
7546 }
7554 {
7555 /* Vector NOT. */
7558 }
7560 /* MVN-shifted-reg. */
7562 {
7569 }
7570 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
7571 Handle the second form here taking care that 'a' in the above can
7572 be a shift. */
7574 {
7583 {
7586 else
7588 }
7591 }
7592 /* MVN. */
7601 /* If a value is written in SI mode, then zero extended to DI
7602 mode, the operation will in general be free as a write to
7603 a 'w' register implicitly zeroes the upper bits of an 'x'
7604 register. However, if this is
7606 (set (reg) (zero_extend (reg)))
7608 we must cost the explicit register move. */
7612 {
7615 /* If OP_COST is non-zero, then the cost of the zero extend
7616 is effectively the cost of the inner operation. Otherwise
7617 we have a MOV instruction and we take the cost from the MOV
7618 itself. This is true independently of whether we are
7619 optimizing for space or time. */
7624 }
7626 {
7627 /* All loads can zero extend to any size for free. */
7630 }
7634 {
7639 }
7642 {
7644 {
7645 /* UMOV. */
7647 }
7648 else
7649 {
7650 /* We generate an AND instead of UXTB/UXTH. */
7652 }
7653 }
7658 {
7659 /* LDRSH. */
7661 {
7668 }
7670 }
7674 {
7679 }
7682 {
7685 else
7687 }
7695 {
7697 {
7699 {
7700 /* Vector shift (immediate). */
7702 }
7703 else
7704 {
7705 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
7706 aliases. */
7708 }
7709 }
7711 /* We can incorporate zero/sign extend for free. */
7718 }
7719 else
7720 {
7722 {
7724 /* Vector shift (register). */
7726 }
7727 else
7728 {
7730 /* LSLV. */
7736 {
7738 /* We already demanded XEXP (op1, 0) to be REG_P, so
7739 don't recurse into it. */
7741 }
7742 }
7744 }
7754 {
7755 /* ASR (immediate) and friends. */
7757 {
7760 else
7762 }
7766 }
7767 else
7768 {
7770 {
7772 /* Vector shift (register). */
7774 }
7775 else
7776 {
7778 /* ASR (register) and friends. */
7784 {
7786 /* We already demanded XEXP (op1, 0) to be REG_P, so
7787 don't recurse into it. */
7789 }
7790 }
7792 }
7798 {
7799 /* LDR. */
7802 }
7805 {
7806 /* ADRP, followed by ADD. */
7810 }
7813 {
7814 /* ADR. */
7817 }
7820 {
7821 /* One extra load instruction, after accessing the GOT. */
7825 }
7830 /* ADRP/ADD (immediate). */
7837 /* UBFX/SBFX. */
7839 {
7842 else
7844 }
7846 /* We can trust that the immediates used will be correct (there
7847 are no by-register forms), so we need only cost op0. */
7853 /* aarch64_rtx_mult_cost always handles recursion to its
7854 operands. */
7858 /* We can expand signed mod by power of 2 using a NEGS, two parallel
7859 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
7860 an unconditional negate. This case should only ever be reached through
7861 the set_smod_pow2_cheap check in expmed.c. */
7865 {
7866 /* We expand to 4 instructions. Reset the baseline. */
7874 }
7876 /* Fall-through. */
7879 {
7880 /* Slighly prefer UMOD over SMOD. */
7887 }
7894 {
7898 /* There is no integer SQRT, so only DIV and UDIV can get
7899 here. */
7901 /* Slighly prefer UDIV over SDIV. */
7903 else
7905 }
7931 {
7934 else
7936 }
7938 /* FMSUB, FNMADD, and FNMSUB are free. */
7945 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
7946 and the by-element operand as operand 0. */
7950 /* Catch vector-by-element operations. The by-element operand can
7951 either be (vec_duplicate (vec_select (x))) or just
7952 (vec_select (x)), depending on whether we are multiplying by
7953 a vector or a scalar.
7955 Canonicalization is not very good in these cases, FMA4 will put the
7956 by-element operand as operand 0, FNMA4 will have it as operand 1. */
7967 /* If the remaining parameters are not registers,
7968 get the cost to put them into registers. */
7982 {
7984 {
7985 /*Vector truncate. */
7987 }
7988 else
7990 }
7995 {
7997 {
7998 /*Vector conversion. */
8000 }
8001 else
8003 }
8009 /* Strip the rounding part. They will all be implemented
8010 by the fcvt* family of instructions anyway. */
8012 {
8021 }
8024 {
8027 else
8029 }
8031 /* We can combine fmul by a power of 2 followed by a fcvt into a single
8032 fixed-point fcvt. */
8037 {
8041 }
8048 {
8049 /* ABS (vector). */
8052 }
8054 {
8057 /* FABD, which is analogous to FADD. */
8059 {
8066 }
8067 /* Simple FABS is analogous to FNEG. */
8070 }
8071 else
8072 {
8073 /* Integer ABS will either be split to
8074 two arithmetic instructions, or will be an ABS
8075 (scalar), which we don't model. */
8079 }
8085 {
8088 else
8089 {
8090 /* FMAXNM/FMINNM/FMAX/FMIN.
8091 TODO: This may not be accurate for all implementations, but
8092 we do not model this in the cost tables. */
8094 }
8095 }
8099 /* The floating point round to integer frint* instructions. */
8101 {
8106 }
8109 {
8114 }
8119 /* Decompose <su>muldi3_highpart. */
8121 mode == DImode
8122 /* (lshiftrt:TI */
8125 /* (mult:TI */
8127 /* (ANY_EXTEND:TI (reg:DI))
8128 (ANY_EXTEND:TI (reg:DI))) */
8135 /* (const_int 64) */
8138 {
8139 /* UMULH/SMULH. */
8147 }
8149 /* Fall through. */
8152 }
8160 }
8162 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
8163 calculated for X. This cost is stored in *COST. Returns true
8164 if the total cost of X was calculated. */
8165 static bool
8168 {
8173 {
8178 }
8181 }
8183 static int
8186 {
8192 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
8199 /* Moving between GPR and stack cost is the same as GP2GP. */
8204 /* To/From the stack register, we move via the gprs. */
8210 {
8211 /* 128-bit operations on general registers require 2 instructions. */
8219 /* When AdvSIMD instructions are disabled it is not possible to move
8220 a 128-bit value directly between Q registers. This is handled in
8221 secondary reload. A general register is used as a scratch to move
8222 the upper DI value and the lower DI value is moved directly,
8223 hence the cost is the sum of three moves. */
8228 }
8238 }
8240 static int
8242 reg_class_t rclass ATTRIBUTE_UNUSED,
8244 {
8246 }
8248 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
8249 to optimize 1.0/sqrt. */
8251 static bool
8253 {
8255 && flag_unsafe_math_optimizations
8259 }
8261 /* Function to decide when to use the approximate reciprocal square root
8262 builtin. */
8264 static tree
8266 {
8272 }
8276 /* Select reciprocal square root initial estimate insn depending on machine
8277 mode. */
8279 static rsqrte_type
8281 {
8283 {
8290 }
8291 }
8295 /* Select reciprocal square root series step insn depending on machine mode. */
8297 static rsqrts_type
8299 {
8301 {
8308 }
8309 }
8311 /* Emit instruction sequence to compute either the approximate square root
8312 or its approximate reciprocal, depending on the flag RECP, and return
8313 whether the sequence was emitted or not. */
8315 bool
8317 {
8321 {
8324 }
8327 {
8334 || flag_trapping_math
8335 || !flag_unsafe_math_optimizations
8338 }
8339 else
8340 /* Caller assumes we cannot fail. */
8346 /* When calculating the approximate square root, compare the
8347 argument with 0.0 and create a mask. */
8353 /* Estimate the approximate reciprocal square root. */
8357 /* Iterate over the series twice for SF and thrice for DF. */
8360 /* Optionally iterate over the series once less for faster performance
8361 while sacrificing the accuracy. */
8364 iterations--;
8366 /* Iterate over the series to calculate the approximate reciprocal square
8367 root. */
8370 {
8378 }
8381 {
8382 /* Qualify the approximate reciprocal square root when the argument is
8383 0.0 by squashing the intermediary result to 0.0. */
8389 /* Calculate the approximate square root. */
8391 }
8393 /* Finalize the approximation. */
8397 }
8401 /* Select reciprocal initial estimate insn depending on machine mode. */
8403 static recpe_type
8405 {
8407 {
8414 }
8415 }
8419 /* Select reciprocal series step insn depending on machine mode. */
8421 static recps_type
8423 {
8425 {
8432 }
8433 }
8435 /* Emit the instruction sequence to compute the approximation for the division
8436 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
8438 bool
8440 {
8451 || flag_trapping_math
8452 || !flag_unsafe_math_optimizations
8457 /* Estimate the approximate reciprocal. */
8461 /* Iterate over the series twice for SF and thrice for DF. */
8464 /* Optionally iterate over the series once less for faster performance,
8465 while sacrificing the accuracy. */
8467 iterations--;
8469 /* Iterate over the series to calculate the approximate reciprocal. */
8472 {
8477 }
8480 {
8481 /* As the approximate reciprocal of DEN is already calculated, only
8482 calculate the approximate division when NUM is not 1.0. */
8485 }
8487 /* Finalize the approximation. */
8490 }
8492 /* Return the number of instructions that can be issued per cycle. */
8493 static int
8495 {
8497 }
8499 static int
8501 {
8505 }
8508 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
8509 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
8510 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
8512 static int
8515 {
8517 }
8520 /* Vectorizer cost model target hooks. */
8522 /* Implement targetm.vectorize.builtin_vectorization_cost. */
8523 static int
8525 tree vectype,
8527 {
8536 {
8587 }
8588 }
8590 /* Implement targetm.vectorize.add_stmt_cost. */
8591 static unsigned
8595 {
8600 {
8605 /* Statements in an inner loop relative to the loop being
8606 vectorized are weighted more heavily. The value here is
8607 arbitrary and could potentially be improved with analysis. */
8613 }
8616 }
8620 /* Parse the TO_PARSE string and put the architecture struct that it
8621 selects into RES and the architectural features into ISA_FLAGS.
8622 Return an aarch64_parse_opt_result describing the parse result.
8623 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
8625 static enum aarch64_parse_opt_result
8628 {
8640 else
8647 /* Loop through the list of supported ARCHes to find a match. */
8649 {
8651 {
8655 {
8656 /* TO_PARSE string contains at least one extension. */
8657 enum aarch64_parse_opt_result ext_res
8662 }
8663 /* Extension parsing was successful. Confirm the result
8664 arch and ISA flags. */
8668 }
8669 }
8671 /* ARCH name not found in list. */
8673 }
8675 /* Parse the TO_PARSE string and put the result tuning in RES and the
8676 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
8677 describing the parse result. If there is an error parsing, RES and
8678 ISA_FLAGS are left unchanged. */
8680 static enum aarch64_parse_opt_result
8683 {
8695 else
8702 /* Loop through the list of supported CPUs to find a match. */
8704 {
8706 {
8711 {
8712 /* TO_PARSE string contains at least one extension. */
8713 enum aarch64_parse_opt_result ext_res
8718 }
8719 /* Extension parsing was successfull. Confirm the result
8720 cpu and ISA flags. */
8724 }
8725 }
8727 /* CPU name not found in list. */
8729 }
8731 /* Parse the TO_PARSE string and put the cpu it selects into RES.
8732 Return an aarch64_parse_opt_result describing the parse result.
8733 If the parsing fails the RES does not change. */
8735 static enum aarch64_parse_opt_result
8737 {
8743 /* Loop through the list of supported CPUs to find a match. */
8745 {
8747 {
8750 }
8751 }
8753 /* CPU name not found in list. */
8755 }
8757 /* Parse TOKEN, which has length LENGTH to see if it is an option
8758 described in FLAG. If it is, return the index bit for that fusion type.
8759 If not, error (printing OPTION_NAME) and return zero. */
8761 static unsigned int
8766 {
8768 {
8772 }
8776 }
8778 /* Parse OPTION which is a comma-separated list of flags to enable.
8779 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
8780 default state we inherit from the CPU tuning structures. OPTION_NAME
8781 gives the top-level option we are parsing in the -moverride string,
8782 for use in error messages. */
8784 static unsigned int
8789 {
8796 {
8799 token_length,
8800 flags,
8801 option_name);
8802 /* If we find "none" (or, for simplicity's sake, an error) anywhere
8803 in the token stream, reset the supported operations. So:
8805 adrp+add.cmp+branch.none.adrp+add
8807 would have the result of turning on only adrp+add fusion. */
8813 }
8815 /* We ended with a comma, print something. */
8817 {
8820 }
8822 /* We still have one more token to parse. */
8825 token_length,
8826 flags,
8827 option_name);
8833 }
8835 /* Support for overriding instruction fusion. */
8837 static void
8840 {
8842 aarch64_fusible_pairs,
8845 }
8847 /* Support for overriding other tuning flags. */
8849 static void
8852 {
8853 tune->extra_tuning_flags
8855 aarch64_tuning_flags,
8858 }
8860 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
8861 we understand. If it is, extract the option string and handoff to
8862 the appropriate function. */
8864 void
8868 {
8874 {
8877 }
8879 /* Get the length of the option name. */
8881 /* Skip the '=' to get to the option string. */
8882 option_part++;
8885 {
8887 {
8890 }
8891 }
8895 }
8897 /* A checking mechanism for the implementation of the tls size. */
8899 static void
8901 {
8906 {
8908 /* Both the default and maximum TLS size allowed under tiny is 1M which
8909 needs two instructions to address, so we clamp the size to 24. */
8914 /* The maximum TLS size allowed under small is 4G. */
8919 /* The maximum TLS size allowed under large is 16E.
8920 FIXME: 16E should be 64bit, we only support 48bit offset now. */
8926 }
8929 }
8931 /* Parse STRING looking for options in the format:
8932 string :: option:string
8933 option :: name=substring
8934 name :: {a-z}
8935 substring :: defined by option. */
8937 static void
8940 {
8951 {
8953 /* Make this substring look like a string. */
8957 }
8959 /* One last option to parse. */
8962 }
8965 static void
8967 {
8968 /* PR 70044: We have to be careful about being called multiple times for the
8969 same function. This means all changes should be repeatable. */
8971 /* If the frame pointer is enabled, set it to a special value that behaves
8972 similar to frame pointer omission. If we don't do this all leaf functions
8973 will get a frame pointer even if flag_omit_leaf_frame_pointer is set.
8974 If flag_omit_frame_pointer has this special value, we must force the
8975 frame pointer if not in a leaf function. We also need to force it in a
8976 leaf function if flag_omit_frame_pointer is not set or if LR is used. */
8980 /* If not optimizing for size, set the default
8981 alignment to what the target wants. */
8983 {
8990 }
8992 /* We default to no pc-relative literal loads. */
8996 /* If -mpc-relative-literal-loads is set on the command line, this
8997 implies that the user asked for PC relative literal loads. */
9001 /* In the tiny memory model it makes no sense to disallow PC relative
9002 literal pool loads. */
9007 /* When enabling the lower precision Newton series for the square root, also
9008 enable it for the reciprocal square root, since the latter is an
9009 intermediary step for the former. */
9012 }
9014 /* 'Unpack' up the internal tuning structs and update the options
9015 in OPTS. The caller must have set up selected_tune and selected_arch
9016 as all the other target-specific codegen decisions are
9017 derived from them. */
9019 void
9021 {
9024 /* Make a copy of the tuning parameters attached to the core, which
9025 we may later overwrite. */
9033 /* This target defaults to strict volatile bitfields. */
9042 {
9054 }
9056 /* We don't mind passing in global_options_set here as we don't use
9057 the *options_set structs anyway. */
9059 queue_depth,
9063 /* Set up parameters to be used in prefetching algorithm. Do not
9064 override the defaults unless we are tuning for a core we have
9065 researched values for. */
9087 /* Use the alternative scheduling-pressure algorithm by default. */
9092 /* Enable sw prefetching at specified optimization level for
9093 CPUS that have prefetch. Lower optimization level threshold by 1
9094 when profiling is enabled. */
9102 }
9104 /* Print a hint with a suggestion for a core or architecture name that
9105 most closely resembles what the user passed in STR. ARCH is true if
9106 the user is asking for an architecture name. ARCH is false if the user
9107 is asking for a core name. */
9109 static void
9111 {
9122 }
9124 /* Print a hint with a suggestion for a core name that most closely resembles
9125 what the user passed in STR. */
9129 {
9131 }
9133 /* Print a hint with a suggestion for an architecture name that most closely
9134 resembles what the user passed in STR. */
9138 {
9140 }
9142 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
9143 specified in STR and throw errors if appropriate. Put the results if
9144 they are valid in RES and ISA_FLAGS. Return whether the option is
9145 valid. */
9147 static bool
9150 {
9151 enum aarch64_parse_opt_result parse_res
9158 {
9171 }
9174 }
9176 /* Validate a command-line -march option. Parse the arch and extensions
9177 (if any) specified in STR and throw errors if appropriate. Put the
9178 results, if they are valid, in RES and ISA_FLAGS. Return whether the
9179 option is valid. */
9181 static bool
9184 {
9185 enum aarch64_parse_opt_result parse_res
9192 {
9205 }
9208 }
9210 /* Validate a command-line -mtune option. Parse the cpu
9211 specified in STR and throw errors if appropriate. Put the
9212 result, if it is valid, in RES. Return whether the option is
9213 valid. */
9215 static bool
9217 {
9218 enum aarch64_parse_opt_result parse_res
9225 {
9235 }
9237 }
9239 /* Return the CPU corresponding to the enum CPU.
9240 If it doesn't specify a cpu, return the default. */
9244 {
9248 /* The & 0x3f is to extract the bottom 6 bits that encode the
9249 default cpu as selected by the --with-cpu GCC configure option
9250 in config.gcc.
9251 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
9252 flags mechanism should be reworked to make it more sane. */
9254 }
9256 /* Return the architecture corresponding to the enum ARCH.
9257 If it doesn't specify a valid architecture, return the default. */
9261 {
9268 }
9270 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
9271 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
9272 tuning structs. In particular it must set selected_tune and
9273 aarch64_isa_flags that define the available ISA features and tuning
9274 decisions. It must also set selected_arch as this will be used to
9275 output the .arch asm tags for each function. */
9277 static void
9279 {
9292 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
9293 If either of -march or -mtune is given, they override their
9294 respective component of -mcpu. */
9306 /* If the user did not specify a processor, choose the default
9307 one for them. This will be the CPU set during configuration using
9308 --with-cpu, otherwise it is "generic". */
9310 {
9312 {
9316 }
9317 else
9318 {
9319 /* Get default configure-time CPU. */
9322 }
9326 }
9327 /* If both -mcpu and -march are specified check that they are architecturally
9328 compatible, warn if they're not and prefer the -march ISA flags. */
9330 {
9332 {
9336 }
9341 }
9342 else
9343 {
9344 /* -mcpu but no -march. */
9351 }
9353 /* Set the arch as well as we will need it when outputing
9354 the .arch directive in assembly. */
9356 {
9359 }
9364 #ifndef HAVE_AS_MABI_OPTION
9365 /* The compiler may have been configured with 2.23.* binutils, which does
9366 not have support for ILP32. */
9369 #endif
9374 /* Make sure we properly set up the explicit options. */
9385 /* Save these options as the default ones in case we push and pop them later
9386 while processing functions with potential target attributes. */
9387 target_option_default_node = target_option_current_node
9389 }
9391 /* Implement targetm.override_options_after_change. */
9393 static void
9395 {
9397 }
9401 {
9405 }
9407 void
9409 {
9411 }
9413 /* A checking mechanism for the implementation of the various code models. */
9414 static void
9416 {
9418 {
9420 {
9425 #ifdef HAVE_AS_SMALL_PIC_RELOCS
9427 ? AARCH64_CMODEL_SMALL_PIC
9429 #else
9431 #endif
9439 }
9440 }
9441 else
9443 }
9445 /* Implement TARGET_OPTION_SAVE. */
9447 static void
9449 {
9451 }
9453 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
9454 using the information saved in PTR. */
9456 static void
9458 {
9466 }
9468 /* Implement TARGET_OPTION_PRINT. */
9470 static void
9472 {
9483 }
9487 void
9489 {
9491 }
9493 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
9494 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
9495 make sure optab availability predicates are recomputed when necessary. */
9497 void
9499 {
9504 else
9506 }
9508 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
9509 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
9510 of the function, if such exists. This function may be called multiple
9511 times on a single function so use aarch64_previous_fndecl to avoid
9512 setting up identical state. */
9514 static void
9516 {
9520 tree old_tree = (aarch64_previous_fndecl
9526 /* If current function has no attributes but the previous one did,
9527 use the default node. */
9531 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
9532 the default have been handled by aarch64_save_restore_target_globals from
9533 aarch64_pragma_target_parse. */
9539 /* First set the target options. */
9543 }
9545 /* Enum describing the various ways we can handle attributes.
9546 In many cases we can reuse the generic option handling machinery. */
9548 enum aarch64_attr_opt_type
9549 {
9553 aarch64_attr_custom /* Attribute requires a custom handling function. */
9554 };
9556 /* All the information needed to handle a target attribute.
9557 NAME is the name of the attribute.
9558 ATTR_TYPE specifies the type of behavior of the attribute as described
9559 in the definition of enum aarch64_attr_opt_type.
9560 ALLOW_NEG is true if the attribute supports a "no-" form.
9561 HANDLER is the function that takes the attribute string as an argument
9562 It is needed only when the ATTR_TYPE is aarch64_attr_custom.
9563 OPT_NUM is the enum specifying the option that the attribute modifies.
9564 This is needed for attributes that mirror the behavior of a command-line
9565 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
9566 aarch64_attr_enum. */
9568 struct aarch64_attribute_info
9569 {
9575 };
9577 /* Handle the ARCH_STR argument to the arch= target attribute. */
9579 static bool
9581 {
9583 enum aarch64_parse_opt_result parse_res
9587 {
9592 }
9595 {
9608 }
9611 }
9613 /* Handle the argument CPU_STR to the cpu= target attribute. */
9615 static bool
9617 {
9619 enum aarch64_parse_opt_result parse_res
9623 {
9631 }
9634 {
9647 }
9650 }
9652 /* Handle the argument STR to the tune= target attribute. */
9654 static bool
9656 {
9658 enum aarch64_parse_opt_result parse_res
9662 {
9667 }
9670 {
9677 }
9680 }
9682 /* Parse an architecture extensions target attribute string specified in STR.
9683 For example "+fp+nosimd". Show any errors if needed. Return TRUE
9684 if successful. Update aarch64_isa_flags to reflect the ISA features
9685 modified. */
9687 static bool
9689 {
9693 /* We allow "+nothing" in the beginning to clear out all architectural
9694 features if the user wants to handpick specific features. */
9696 {
9699 }
9704 {
9707 }
9710 {
9721 }
9724 }
9726 /* The target attributes that we support. On top of these we also support just
9727 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
9728 handled explicitly in aarch64_process_one_target_attr. */
9731 {
9733 OPT_mgeneral_regs_only },
9735 OPT_mfix_cortex_a53_835769 },
9737 OPT_mfix_cortex_a53_843419 },
9741 OPT_momit_leaf_frame_pointer },
9744 OPT_march_ },
9747 OPT_mtune_ },
9749 OPT_msign_return_address_ },
9751 };
9753 /* Parse ARG_STR which contains the definition of one target attribute.
9754 Show appropriate errors if any or return true if the attribute is valid. */
9756 static bool
9758 {
9764 {
9767 }
9772 /* Skip leading whitespace. */
9774 str_to_check++;
9776 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
9777 It is easier to detect and handle it explicitly here rather than going
9778 through the machinery for the rest of the target attributes in this
9779 function. */
9784 {
9787 }
9790 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
9791 and point ARG to "foo". */
9793 {
9795 arg++;
9796 }
9800 {
9801 /* If the names don't match up, or the user has given an argument
9802 to an attribute that doesn't accept one, or didn't give an argument
9803 to an attribute that expects one, fail to match. */
9812 {
9815 }
9817 /* If the name matches but the attribute does not allow "no-" versions
9818 then we can't match. */
9820 {
9823 }
9826 {
9827 /* Has a custom handler registered.
9828 For example, cpu=, arch=, tune=. */
9835 /* Either set or unset a boolean option. */
9837 {
9845 }
9846 /* Set or unset a bit in the target_flags. aarch64_handle_option
9847 should know what mask to apply given the option number. */
9849 {
9851 /* We only need to specify the option number.
9852 aarch64_handle_option will know which mask to apply. */
9858 }
9859 /* Use the option setting machinery to set an option to an enum. */
9861 {
9868 {
9871 global_dc);
9872 }
9873 else
9874 {
9876 }
9878 }
9881 }
9882 }
9884 /* If we reached here we either have found an attribute and validated
9885 it or didn't match any. If we matched an attribute but its arguments
9886 were malformed we will have returned false already. */
9888 }
9890 /* Count how many times the character C appears in
9891 NULL-terminated string STR. */
9893 static unsigned int
9895 {
9898 {
9900 res++;
9902 str++;
9903 }
9906 }
9908 /* Parse the tree in ARGS that contains the target attribute information
9909 and update the global target options space. */
9911 bool
9913 {
9915 {
9916 do
9917 {
9920 {
9923 }
9928 }
9931 {
9934 }
9941 {
9944 }
9946 /* Used to catch empty spaces between commas i.e.
9947 attribute ((target ("attr1,,attr2"))). */
9950 /* Handle multiple target attributes separated by ','. */
9955 {
9956 num_attrs++;
9958 {
9961 }
9964 }
9967 {
9970 }
9973 }
9975 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
9976 process attribute ((target ("..."))). */
9978 static bool
9980 {
9983 tree old_optimize;
9987 /* If what we're processing is the current pragma string then the
9988 target option node is already stored in target_option_current_node
9989 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
9990 having to re-parse the string. This is especially useful to keep
9991 arm_neon.h compile times down since that header contains a lot
9992 of intrinsics enclosed in pragmas. */
9994 {
9997 }
10003 /* If the function changed the optimization levels as well as setting
10004 target options, start with the optimizations specified. */
10009 /* Save the current target options to restore at the end. */
10012 /* If fndecl already has some target attributes applied to it, unpack
10013 them so that we add this attribute on top of them, rather than
10014 overwriting them. */
10016 {
10022 }
10023 else
10029 /* Set up any additional state. */
10031 {
10033 /* Initialize SIMD builtins if we haven't already.
10034 Set current_target_pragma to NULL for the duration so that
10035 the builtin initialization code doesn't try to tag the functions
10036 being built with the attributes specified by any current pragma, thus
10037 going into an infinite recursion. */
10039 {
10044 }
10046 }
10047 else
10053 {
10058 }
10066 }
10068 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
10069 tri-bool options (yes, no, don't care) and the default value is
10070 DEF, determine whether to reject inlining. */
10072 static bool
10075 {
10076 /* If the callee doesn't care, always allow inlining. */
10080 /* If the caller doesn't care, always allow inlining. */
10084 /* Otherwise, allow inlining if either the callee and caller values
10085 agree, or if the callee is using the default value. */
10087 }
10089 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
10090 to inline CALLEE into CALLER based on target-specific info.
10091 Make sure that the caller and callee have compatible architectural
10092 features. Then go through the other possible target attributes
10093 and see if they can block inlining. Try not to reject always_inline
10094 callees unless they are incompatible architecturally. */
10096 static bool
10098 {
10102 /* If callee has no option attributes, then it is ok to inline. */
10113 /* Callee's ISA flags should be a subset of the caller's. */
10118 /* Allow non-strict aligned functions inlining into strict
10119 aligned ones. */
10129 /* If the architectural features match up and the callee is always_inline
10130 then the other attributes don't matter. */
10142 /* Honour explicit requests to workaround errata. */
10155 /* If the user explicitly specified -momit-leaf-frame-pointer for the
10156 caller and calle and they don't match up, reject inlining. */
10163 /* If the callee has specific tuning overrides, respect them. */
10168 /* If the user specified tuning override strings for the
10169 caller and callee and they don't match up, reject inlining.
10170 We just do a string compare here, we don't analyze the meaning
10171 of the string, as it would be too costly for little gain. */
10179 }
10181 /* Return true if SYMBOL_REF X binds locally. */
10183 static bool
10185 {
10189 }
10191 /* Return true if SYMBOL_REF X is thread local */
10192 static bool
10194 {
10202 }
10204 /* Classify a TLS symbol into one of the TLS kinds. */
10205 enum aarch64_symbol_type
10207 {
10211 {
10218 {
10224 }
10235 else
10244 }
10245 }
10247 /* Return the method that should be used to access SYMBOL_REF or
10248 LABEL_REF X. */
10250 enum aarch64_symbol_type
10252 {
10254 {
10256 {
10271 }
10272 }
10275 {
10280 {
10282 /* When we retrieve symbol + offset address, we have to make sure
10283 the offset does not cause overflow of the final address. But
10284 we have no way of knowing the address of symbol at compile time
10285 so we can't accurately say if the distance between the PC and
10286 symbol + offset is outside the addressible range of +/-1M in the
10287 TINY code model. So we rely on images not being greater than
10288 1M and cap the offset at 1M and anything beyond 1M will have to
10289 be loaded using an alternative mechanism. Furthermore if the
10290 symbol is a weak reference to something that isn't known to
10291 resolve to a symbol in this module, then force to memory. */
10299 /* Same reasoning as the tiny code model, but the offset cap here is
10300 4G. */
10321 /* This is alright even in PIC code as the constant
10322 pool reference is always PC relative and within
10323 the same translation unit. */
10326 else
10331 }
10332 }
10334 /* By default push everything into the constant pool. */
10336 }
10338 bool
10340 {
10342 }
10344 bool
10346 {
10354 }
10356 /* Implement TARGET_LEGITIMATE_CONSTANT_P hook. Return true for constants
10357 that should be rematerialized rather than spilled. */
10359 static bool
10361 {
10362 /* Support CSE and rematerialization of common constants. */
10366 /* Do not allow vector struct mode constants. We could support
10367 0 and -1 easily, but they need support in aarch64-simd.md. */
10371 /* Do not allow wide int constants - this requires support in movti. */
10375 /* Do not allow const (plus (anchor_symbol, const_int)). */
10377 {
10378 rtx offset;
10384 }
10389 /* Treat symbols as constants. Avoid TLS symbols as they are complex,
10390 so spilling them is better than rematerialization. */
10394 /* Label references are always constant. */
10399 }
10401 rtx
10403 {
10409 /* Can return in any reg. */
10412 }
10414 /* On AAPCS systems, this is the "struct __va_list". */
10417 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
10418 Return the type to use as __builtin_va_list.
10420 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
10422 struct __va_list
10423 {
10424 void *__stack;
10425 void *__gr_top;
10426 void *__vr_top;
10427 int __gr_offs;
10428 int __vr_offs;
10429 }; */
10431 static tree
10433 {
10434 tree va_list_name;
10437 /* Create the type. */
10439 /* Give it the required name. */
10441 TYPE_DECL,
10443 va_list_type);
10448 /* Create the fields. */
10451 ptr_type_node);
10454 ptr_type_node);
10457 ptr_type_node);
10460 integer_type_node);
10463 integer_type_node);
10465 /* Tell tree-stdarg pass about our internal offset fields.
10466 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
10467 purpose to identify whether the code is updating va_list internal
10468 offset fields through irregular way. */
10490 /* Compute its layout. */
10494 }
10496 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
10497 static void
10499 {
10503 tree t;
10517 {
10520 }
10529 NULL_TREE);
10531 NULL_TREE);
10533 NULL_TREE);
10535 NULL_TREE);
10537 NULL_TREE);
10539 /* Emit code to initialize STACK, which points to the next varargs stack
10540 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
10541 by named arguments. STACK is 8-byte aligned. */
10548 /* Emit code to initialize GRTOP, the top of the GR save area.
10549 virtual_incoming_args_rtx should have been 16 byte aligned. */
10554 /* Emit code to initialize VRTOP, the top of the VR save area.
10555 This address is gr_save_area_bytes below GRTOP, rounded
10556 down to the next 16-byte boundary. */
10566 /* Emit code to initialize GROFF, the offset from GRTOP of the
10567 next GPR argument. */
10572 /* Likewise emit code to initialize VROFF, the offset from FTOP
10573 of the next VR argument. */
10577 }
10579 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
10581 static tree
10584 {
10585 tree addr;
10591 machine_mode mode;
10618 type,
10622 {
10623 /* TYPE passed in fp/simd registers. */
10635 {
10638 }
10641 {
10643 }
10644 }
10645 else
10646 {
10647 /* TYPE passed in general registers. */
10660 {
10662 }
10663 }
10665 /* Get a local temporary for the field value. */
10668 /* Emit code to branch if off >= 0. */
10674 {
10675 /* Emit: offs = (offs + 15) & -16. */
10681 }
10682 else
10685 /* Update ap.__[g|v]r_offs */
10690 /* String up. */
10694 /* [cond2] if (ap.__[g|v]r_offs > 0) */
10699 /* String up: make sure the assignment happens before the use. */
10703 /* Prepare the trees handling the argument that is passed on the stack;
10704 the top level node will store in ON_STACK. */
10707 {
10708 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
10716 }
10717 else
10719 /* Advance ap.__stack */
10727 /* String up roundup and advance. */
10730 /* String up with arg */
10732 /* Big-endianness related address adjustment. */
10735 {
10739 }
10744 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
10754 {
10755 /* type ha; // treat as "struct {ftype field[n];}"
10756 ... [computing offs]
10757 for (i = 0; i <nregs; ++i, offs += 16)
10758 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
10759 return ha; */
10763 /* Declare a local variable. */
10767 /* Establish the base type. */
10769 {
10788 {
10792 }
10796 }
10798 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
10806 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
10808 {
10818 }
10822 }
10832 }
10834 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
10836 static void
10840 {
10842 CUMULATIVE_ARGS local_cum;
10846 /* The caller has advanced CUM up to, but not beyond, the last named
10847 argument. Advance a local copy of CUM past the last "real" named
10848 argument, to find out how many registers are left over. */
10852 /* Found out how many registers we need to save.
10853 Honor tree-stdvar analysis results. */
10862 {
10865 }
10868 {
10870 {
10873 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
10881 }
10883 {
10884 /* We can't use move_block_from_reg, because it will use
10885 the wrong mode, storing D regs only. */
10889 /* Set OFF to the offset from virtual_incoming_args_rtx of
10890 the first vector register. The VR save area lies below
10891 the GR one, and is aligned to 16 bytes. */
10898 {
10906 }
10907 }
10908 }
10910 /* We don't save the size into *PRETEND_SIZE because we want to avoid
10911 any complication of having crtl->args.pretend_args_size changed. */
10916 }
10918 static void
10920 {
10923 {
10925 {
10928 }
10929 }
10930 }
10932 /* Walk down the type tree of TYPE counting consecutive base elements.
10933 If *MODEP is VOIDmode, then set it to the first valid floating point
10934 type. If a non-floating point type is found, or if a floating point
10935 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
10936 otherwise return the count in the sub-tree. */
10937 static int
10939 {
10940 machine_mode mode;
10941 HOST_WIDE_INT size;
10944 {
10974 /* Use V2SImode and V4SImode as representatives of all 64-bit
10975 and 128-bit vector types. */
10978 {
10987 }
10992 /* Vector modes are considered to be opaque: two vectors are
10993 equivalent for the purposes of being homogeneous aggregates
10994 if they are the same size. */
11001 {
11005 /* Can't handle incomplete types nor sizes that are not
11006 fixed. */
11013 || !index
11024 /* There must be no padding. */
11030 }
11033 {
11036 tree field;
11038 /* Can't handle incomplete types nor sizes that are not
11039 fixed. */
11045 {
11053 }
11055 /* There must be no padding. */
11061 }
11065 {
11066 /* These aren't very interesting except in a degenerate case. */
11069 tree field;
11071 /* Can't handle incomplete types nor sizes that are not
11072 fixed. */
11078 {
11086 }
11088 /* There must be no padding. */
11094 }
11098 }
11101 }
11103 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
11104 type as described in AAPCS64 \S 4.1.2.
11106 See the comment above aarch64_composite_type_p for the notes on MODE. */
11108 static bool
11110 machine_mode mode)
11111 {
11121 }
11123 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
11124 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
11125 array types. The C99 floating-point complex types are also considered
11126 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
11127 types, which are GCC extensions and out of the scope of AAPCS64, are
11128 treated as composite types here as well.
11130 Note that MODE itself is not sufficient in determining whether a type
11131 is such a composite type or not. This is because
11132 stor-layout.c:compute_record_mode may have already changed the MODE
11133 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
11134 structure with only one field may have its MODE set to the mode of the
11135 field. Also an integer mode whose size matches the size of the
11136 RECORD_TYPE type may be used to substitute the original mode
11137 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
11138 solely relied on. */
11140 static bool
11142 machine_mode mode)
11143 {
11156 }
11158 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
11159 shall be passed or returned in simd/fp register(s) (providing these
11160 parameter passing registers are available).
11162 Upon successful return, *COUNT returns the number of needed registers,
11163 *BASE_MODE returns the mode of the individual register and when IS_HAF
11164 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
11165 floating-point aggregate or a homogeneous short-vector aggregate. */
11167 static bool
11169 const_tree type,
11173 {
11181 {
11184 }
11186 {
11190 }
11192 {
11196 {
11199 }
11200 else
11202 }
11203 else
11208 }
11210 /* Implement TARGET_STRUCT_VALUE_RTX. */
11212 static rtx
11215 {
11217 }
11219 /* Implements target hook vector_mode_supported_p. */
11220 static bool
11222 {
11234 }
11236 /* Return appropriate SIMD container
11237 for MODE within a vector of WIDTH bits. */
11238 static machine_mode
11240 {
11243 {
11246 {
11263 }
11264 else
11266 {
11279 }
11280 }
11282 }
11284 /* Return 128-bit container as the preferred SIMD mode for MODE. */
11285 static machine_mode
11287 {
11289 }
11291 /* Return the bitmask of possible vector sizes for the vectorizer
11292 to iterate over. */
11293 static unsigned int
11295 {
11297 }
11299 /* Implement TARGET_MANGLE_TYPE. */
11303 {
11304 /* The AArch64 ABI documents say that "__va_list" has to be
11305 managled as if it is in the "std" namespace. */
11309 /* Half-precision float. */
11313 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
11314 builtin types. */
11318 /* Use the default mangling. */
11320 }
11322 /* Find the first rtx_insn before insn that will generate an assembly
11323 instruction. */
11327 {
11331 do
11332 {
11334 }
11338 }
11340 static bool
11342 {
11344 /* A number of these may be AArch32 only. */
11349 };
11352 {
11355 }
11358 }
11360 /* Check if there is a register dependency between a load and the insn
11361 for which we hold recog_data. */
11363 static bool
11365 {
11366 rtx load_reg;
11376 {
11382 }
11384 }
11387 /* When working around the Cortex-A53 erratum 835769,
11388 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
11389 instruction and has a preceding memory instruction such that a NOP
11390 should be inserted between them. */
11392 bool
11394 {
11397 rtx body;
11410 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
11411 Restore recog state to INSN to avoid state corruption. */
11419 /* If the previous insn is a memory op and there is no dependency between
11420 it and the DImode madd, emit a NOP between them. If body is NULL then we
11421 have a complex memory operation, probably a load/store pair.
11422 Be conservative for now and emit a NOP. */
11429 }
11432 /* Implement FINAL_PRESCAN_INSN. */
11434 void
11436 {
11439 }
11442 /* Return the equivalent letter for size. */
11443 static char
11445 {
11447 {
11453 }
11454 }
11456 /* Return true iff x is a uniform vector of floating-point
11457 constants, and the constant can be represented in
11458 quarter-precision form. Note, as aarch64_float_const_representable
11459 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
11460 static bool
11462 {
11463 rtx elt;
11467 }
11469 /* Return true for valid and false for invalid. */
11470 bool
11474 {
11475 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
11476 matches = 1; \
11477 for (i = 0; i < idx; i += (STRIDE)) \
11478 if (!(TEST)) \
11479 matches = 0; \
11480 if (matches) \
11481 { \
11482 immtype = (CLASS); \
11483 elsize = (ELSIZE); \
11484 eshift = (SHIFT); \
11485 emvn = (NEG); \
11486 break; \
11487 }
11497 {
11503 {
11505 scalar_float_mode elt_mode
11512 }
11515 }
11517 /* Splat vector constant out into a byte vector. */
11519 {
11520 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
11521 it must be laid out in the vector register in reverse order. */
11529 {
11532 }
11534 }
11536 /* Sanity check. */
11539 do
11540 {
11542 {
11558 }
11561 {
11577 }
11579 /* Shifting ones / 8-bit / 64-bit variants only checked
11580 for 'ALL' (MOVI/MVNI). */
11582 {
11599 }
11600 }
11607 {
11617 /* Un-invert bytes of recognized vector, if necessary. */
11623 {
11624 /* FIXME: Broken on 32-bit H_W_I hosts. */
11633 }
11634 else
11635 {
11639 /* Construct 'abcdefgh' because the assembler cannot handle
11640 generic constants. */
11645 }
11646 }
11649 #undef CHECK
11650 }
11652 /* Check of immediate shift constants are within range. */
11653 bool
11655 {
11659 else
11661 }
11663 /* Return true if X is a uniform vector where all elements
11664 are either the floating-point constant 0.0 or the
11665 integer constant 0. */
11666 bool
11668 {
11670 }
11673 /* Return the bitmask CONST_INT to select the bits required by a zero extract
11674 operation of width WIDTH at bit position POS. */
11676 rtx
11678 {
11682 unsigned HOST_WIDE_INT mask
11685 }
11687 bool
11689 {
11702 }
11704 /* Return a const_int vector of VAL. */
11705 rtx
11707 {
11710 }
11712 /* Check OP is a legal scalar immediate for the MOVI instruction. */
11714 bool
11716 {
11717 machine_mode vmode;
11722 }
11724 /* Construct and return a PARALLEL RTX vector with elements numbering the
11725 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
11726 the vector - from the perspective of the architecture. This does not
11727 line up with GCC's perspective on lane numbers, so we end up with
11728 different masks depending on our target endian-ness. The diagram
11729 below may help. We must draw the distinction when building masks
11730 which select one half of the vector. An instruction selecting
11731 architectural low-lanes for a big-endian target, must be described using
11732 a mask selecting GCC high-lanes.
11734 Big-Endian Little-Endian
11736 GCC 0 1 2 3 3 2 1 0
11737 | x | x | x | x | | x | x | x | x |
11738 Architecture 3 2 1 0 3 2 1 0
11740 Low Mask: { 2, 3 } { 0, 1 }
11741 High Mask: { 0, 1 } { 2, 3 }
11743 MODE Is the mode of the vector and NUNITS is the number of units in it. */
11745 rtx
11747 {
11752 rtx t1;
11757 else
11765 }
11767 /* Check OP for validity as a PARALLEL RTX vector with elements
11768 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
11769 from the perspective of the architecture. See the diagram above
11770 aarch64_simd_vect_par_cnst_half for more details. */
11772 bool
11775 {
11780 high);
11789 {
11796 }
11798 }
11800 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
11801 HIGH (exclusive). */
11802 void
11804 const_tree exp)
11805 {
11806 HOST_WIDE_INT lane;
11811 {
11814 else
11816 }
11817 }
11819 /* Peform endian correction on lane number N, which indexes a vector
11820 of mode MODE, and return the result as an SImode rtx. */
11822 rtx
11824 {
11826 }
11828 /* Return TRUE if OP is a valid vector addressing mode. */
11829 bool
11831 {
11834 }
11836 /* Emit a register copy from operand to operand, taking care not to
11837 early-clobber source registers in the process.
11839 COUNT is the number of components into which the copy needs to be
11840 decomposed. */
11841 void
11844 {
11854 else
11858 }
11860 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
11861 one of VSTRUCT modes: OI, CI, or XI. */
11862 int
11864 {
11866 }
11868 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
11869 alignment of a vector to 128 bits. */
11870 static HOST_WIDE_INT
11872 {
11875 }
11877 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
11878 static bool
11880 {
11884 /* We guarantee alignment for vectors up to 128-bits. */
11889 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
11891 }
11893 /* Return true if the vector misalignment factor is supported by the
11894 target. */
11895 static bool
11899 {
11901 {
11902 /* Return if movmisalign pattern is not supported for this mode. */
11906 /* Misalignment factor is unknown at compile time. */
11909 }
11911 is_packed);
11912 }
11914 /* If VALS is a vector constant that can be loaded into a register
11915 using DUP, generate instructions to do so and return an RTX to
11916 assign to the register. Otherwise return NULL_RTX. */
11917 static rtx
11919 {
11922 rtx x;
11927 /* We can load this constant by using DUP and a constant in a
11928 single ARM register. This will be cheaper than a vector
11929 load. */
11932 }
11935 /* Generate code to load VALS, which is a PARALLEL containing only
11936 constants (for vec_init) or CONST_VECTOR, efficiently into a
11937 register. Returns an RTX to copy into the register, or NULL_RTX
11938 for a PARALLEL that can not be converted into a CONST_VECTOR. */
11939 static rtx
11941 {
11943 rtx const_dup;
11952 {
11953 /* A CONST_VECTOR must contain only CONST_INTs and
11954 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
11955 Only store valid constants in a CONST_VECTOR. */
11957 {
11960 n_const++;
11961 }
11964 }
11965 else
11970 /* Load using MOVI/MVNI. */
11973 /* Loaded using DUP. */
11976 /* Load from constant pool. We can not take advantage of single-cycle
11977 LD1 because we need a PC-relative addressing mode. */
11979 else
11980 /* A PARALLEL containing something not valid inside CONST_VECTOR.
11981 We can not construct an initializer. */
11983 }
11985 /* Expand a vector initialisation sequence, such that TARGET is
11986 initialised to contain VALS. */
11988 void
11990 {
11993 /* The number of vector elements. */
11995 /* The number of vector elements which are not constant. */
11998 /* The first element of vals. */
12002 /* Count the number of variable elements to initialise. */
12004 {
12008 else
12012 }
12014 /* No variable elements, hand off to aarch64_simd_make_constant which knows
12015 how best to handle this. */
12017 {
12020 {
12023 }
12024 }
12026 /* Splat a single non-constant element if we can. */
12028 {
12032 }
12037 /* If there are only variable elements, try to optimize
12038 the insertion using dup for the most common element
12039 followed by insertions. */
12041 /* The algorithm will fill matches[*][0] with the earliest matching element,
12042 and matches[X][1] with the count of duplicate elements (if X is the
12043 earliest element which has duplicates). */
12046 {
12049 {
12051 {
12053 {
12057 }
12058 }
12059 }
12064 {
12067 }
12069 /* Create a duplicate of the most common element. */
12073 /* Insert the rest. */
12075 {
12081 }
12083 }
12085 /* Initialise a vector which is part-variable. We want to first try
12086 to build those lanes which are constant in the most efficient way we
12087 can. */
12089 {
12092 /* Load constant part of vector. We really don't care what goes into the
12093 parts we will overwrite, but we're more likely to be able to load the
12094 constant efficiently if it has fewer, larger, repeating parts
12095 (see aarch64_simd_valid_immediate). */
12097 {
12103 {
12104 /* Look in the copied vector, as more elements are const. */
12107 {
12110 }
12111 }
12113 }
12115 }
12117 /* Insert the variable lanes directly. */
12119 {
12125 }
12126 }
12128 static unsigned HOST_WIDE_INT
12130 {
12131 return
12132 (!SHIFT_COUNT_TRUNCATED
12135 }
12137 /* Select a format to encode pointers in exception handling data. */
12138 int
12140 {
12143 {
12149 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
12150 for everything. */
12154 /* No assumptions here. 8-byte relocs required. */
12157 }
12159 }
12161 /* The last .arch and .tune assembly strings that we printed. */
12165 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
12166 by the function fndecl. */
12168 void
12170 tree fndecl)
12171 {
12177 else
12188 /* Only update the assembler .arch string if it is distinct from the last
12189 such string we printed. */
12192 {
12195 }
12197 /* Print the cpu name we're tuning for in the comments, might be
12198 useful to readers of the generated asm. Do it only when it changes
12199 from function to function and verbose assembly is requested. */
12204 {
12208 }
12210 /* Don't forget the type directive for ELF. */
12213 }
12215 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
12217 static void
12219 {
12236 }
12238 /* Emit load exclusive. */
12240 static void
12243 {
12247 {
12254 }
12257 }
12259 /* Emit store exclusive. */
12261 static void
12264 {
12268 {
12275 }
12278 }
12280 /* Mark the previous jump instruction as unlikely. */
12282 static void
12284 {
12287 }
12289 /* Expand a compare and swap pattern. */
12291 void
12293 {
12298 gen_cas_fn gen;
12300 {
12301 gen_aarch64_compare_and_swapqi,
12302 gen_aarch64_compare_and_swaphi,
12303 gen_aarch64_compare_and_swapsi,
12304 gen_aarch64_compare_and_swapdi
12305 };
12307 {
12308 gen_aarch64_compare_and_swapqi_lse,
12309 gen_aarch64_compare_and_swaphi_lse,
12310 gen_aarch64_compare_and_swapsi_lse,
12311 gen_aarch64_compare_and_swapdi_lse
12312 };
12325 /* Normally the succ memory model must be stronger than fail, but in the
12326 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
12327 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
12334 {
12337 /* For short modes, we're going to perform the comparison in SImode,
12338 so do the zero-extension now. */
12342 /* Fall through. */
12346 /* Force the value into a register if needed. */
12353 }
12356 {
12363 }
12366 else
12377 }
12379 /* Test whether the target supports using a atomic load-operate instruction.
12380 CODE is the operation and AFTER is TRUE if the data in memory after the
12381 operation should be returned and FALSE if the data before the operation
12382 should be returned. Returns FALSE if the operation isn't supported by the
12383 architecture. */
12385 bool
12387 {
12392 {
12402 }
12403 }
12405 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
12406 sequence implementing an atomic operation. */
12408 static void
12410 {
12417 {
12419 }
12420 }
12422 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
12423 for the data in memory. EXPECTED is the value expected to be in memory.
12424 DESIRED is the value to store to memory. MEM is the memory location. MODEL
12425 is the memory ordering to use. */
12427 void
12430 rtx model)
12431 {
12433 machine_mode mode;
12438 {
12445 }
12447 /* Move the expected value into the CAS destination register. */
12450 /* Emit the CAS. */
12453 /* Compare the expected value with the value loaded by the CAS, to establish
12454 whether the swap was made. */
12456 }
12458 /* Split a compare and swap pattern. */
12460 void
12462 {
12464 machine_mode mode;
12469 rtx model_rtx;
12481 /* When OLDVAL is zero and we want the strong version we can emit a tighter
12482 loop:
12483 .label1:
12484 LD[A]XR rval, [mem]
12485 CBNZ rval, .label2
12486 ST[L]XR scratch, newval, [mem]
12487 CBNZ scratch, .label1
12488 .label2:
12489 CMP rval, 0. */
12494 {
12497 }
12500 /* The initial load can be relaxed for a __sync operation since a final
12501 barrier will be emitted to stop code hoisting. */
12505 else
12509 {
12514 }
12515 else
12516 {
12522 }
12527 {
12532 }
12533 else
12534 {
12538 }
12541 /* If we used a CBNZ in the exchange loop emit an explicit compare with RVAL
12542 to set the condition flags. If this is not used it will be removed by
12543 later passes. */
12545 {
12549 }
12550 /* Emit any final barrier needed for a __sync operation. */
12553 }
12555 /* Emit a BIC instruction. */
12557 static void
12559 {
12564 {
12569 }
12572 }
12574 /* Emit an atomic swap. */
12576 static void
12579 {
12583 {
12590 }
12593 }
12595 /* Operations supported by aarch64_emit_atomic_load_op. */
12597 enum aarch64_atomic_load_op_code
12598 {
12602 AARCH64_LDOP_BIC /* A & ~B */
12603 };
12605 /* Emit an atomic load-operate. */
12607 static void
12611 {
12614 {
12615 gen_aarch64_atomic_loadaddqi,
12616 gen_aarch64_atomic_loadaddhi,
12617 gen_aarch64_atomic_loadaddsi,
12618 gen_aarch64_atomic_loadadddi
12619 };
12621 {
12622 gen_aarch64_atomic_loadeorqi,
12623 gen_aarch64_atomic_loadeorhi,
12624 gen_aarch64_atomic_loadeorsi,
12625 gen_aarch64_atomic_loadeordi
12626 };
12628 {
12629 gen_aarch64_atomic_loadsetqi,
12630 gen_aarch64_atomic_loadsethi,
12631 gen_aarch64_atomic_loadsetsi,
12632 gen_aarch64_atomic_loadsetdi
12633 };
12635 {
12636 gen_aarch64_atomic_loadclrqi,
12637 gen_aarch64_atomic_loadclrhi,
12638 gen_aarch64_atomic_loadclrsi,
12639 gen_aarch64_atomic_loadclrdi
12640 };
12641 aarch64_atomic_load_op_fn gen;
12645 {
12652 }
12655 {
12662 }
12665 }
12667 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
12668 location to store the data read from memory. OUT_RESULT is the location to
12669 store the result of the operation. MEM is the memory location to read and
12670 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
12671 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
12672 be NULL. */
12674 void
12677 {
12681 aarch64_atomic_load_op_code ldop_code;
12682 rtx src;
12683 rtx x;
12691 /* Make sure the value is in a register, putting it into a destination
12692 register if it needs to be manipulated. */
12695 {
12698 }
12699 else
12703 /* Preprocess the data for the operation as necessary. If the operation is
12704 a SET then emit a swap instruction and finish. */
12706 {
12712 /* Negate the value and treat it as a PLUS. */
12713 {
12714 rtx neg_src;
12716 /* Resize the value if necessary. */
12725 }
12726 /* Fall-through. */
12740 {
12741 rtx not_src;
12743 /* Resize the value if necessary. */
12752 }
12757 /* The operation can't be done with atomic instructions. */
12759 }
12763 /* If necessary, calculate the data in memory after the update by redoing the
12764 operation from values in registers. */
12769 {
12773 }
12778 {
12794 }
12799 }
12801 /* Split an atomic operation. */
12803 void
12806 {
12812 rtx x;
12814 /* Split the atomic operation into a sequence. */
12822 else
12826 /* The initial load can be relaxed for a __sync operation since a final
12827 barrier will be emitted to stop code hoisting. */
12831 else
12835 {
12849 {
12852 }
12853 /* Fall through. */
12859 }
12869 /* Emit any final barrier needed for a __sync operation. */
12872 }
12874 static void
12876 {
12877 /* Half-precision float operations. The compiler handles all operations
12878 with NULL libfuncs by converting to SFmode. */
12880 /* Conversions. */
12884 /* Arithmetic. */
12891 /* Comparisons. */
12899 }
12901 /* Target hook for c_mode_for_suffix. */
12902 static machine_mode
12904 {
12909 }
12911 /* We can only represent floating point constants which will fit in
12912 "quarter-precision" values. These values are characterised by
12913 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
12914 by:
12916 (-1)^s * (n/16) * 2^r
12918 Where:
12919 's' is the sign bit.
12920 'n' is an integer in the range 16 <= n <= 31.
12921 'r' is an integer in the range -3 <= r <= 4. */
12923 /* Return true iff X can be represented by a quarter-precision
12924 floating point immediate operand X. Note, we cannot represent 0.0. */
12925 bool
12927 {
12928 /* This represents our current view of how many bits
12929 make up the mantissa. */
12939 /* We don't support HFmode constants yet. */
12945 /* We cannot represent infinities, NaNs or +/-zero. We won't
12946 know if we have +zero until we analyse the mantissa, but we
12947 can reject the other invalid values. */
12952 /* Extract exponent. */
12956 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
12957 highest (sign) bit, with a fixed binary point at bit point_pos.
12958 m1 holds the low part of the mantissa, m2 the high part.
12959 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
12960 bits for the mantissa, this can fail (low bits will be lost). */
12964 /* If the low part of the mantissa has bits set we cannot represent
12965 the value. */
12968 /* We have rejected the lower HOST_WIDE_INT, so update our
12969 understanding of how many bits lie in the mantissa and
12970 look only at the high HOST_WIDE_INT. */
12974 /* We can only represent values with a mantissa of the form 1.xxxx. */
12979 /* Having filtered unrepresentable values, we may now remove all
12980 but the highest 5 bits. */
12983 /* We cannot represent the value 0.0, so reject it. This is handled
12984 elsewhere. */
12988 /* Then, as bit 4 is always set, we can mask it off, leaving
12989 the mantissa in the range [0, 15]. */
12993 /* GCC internally does not use IEEE754-like encoding (where normalized
12994 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
12995 Our mantissa values are shifted 4 places to the left relative to
12996 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
12997 by 5 places to correct for GCC's representation. */
13001 }
13003 /* Returns the string with the instruction for AdvSIMD MOVI, MVNI, ORR or BIC
13004 immediate with a CONST_VECTOR of MODE and WIDTH. WHICH selects whether to
13005 output MOVI/MVNI, ORR or BIC immediate. */
13008 machine_mode mode,
13011 {
13021 /* This will return true to show const_vector is legal for use as either
13022 a AdvSIMD MOVI instruction (or, implicitly, MVNI), ORR or BIC immediate.
13023 It will also update INFO to show how the immediate should be generated.
13024 WHICH selects whether to check for MOVI/MVNI, ORR or BIC. */
13034 {
13036 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
13037 move immediate path. */
13040 else
13041 {
13050 else
13054 }
13055 }
13060 {
13070 else
13074 }
13075 else
13076 {
13077 /* For AARCH64_CHECK_BIC and AARCH64_CHECK_ORR. */
13083 else
13087 }
13089 }
13093 {
13095 /* If a floating point number was passed and we desire to use it in an
13096 integer mode do the conversion to integer. */
13098 {
13103 }
13105 machine_mode vmode;
13106 /* use a 64 bit mode for everything except for DI/DF mode, where we use
13107 a 128 bit vector mode. */
13113 }
13115 /* Split operands into moves from op[1] + op[2] into op[0]. */
13117 void
13119 {
13130 {
13131 /* No-op move. Can't split to nothing; emit something. */
13134 }
13136 /* Preserve register attributes for variable tracking. */
13141 /* Special case of reversed high/low parts. */
13144 {
13148 }
13150 {
13151 /* Try to avoid unnecessary moves if part of the result
13152 is in the right place already. */
13157 }
13158 else
13159 {
13164 }
13165 }
13167 /* vec_perm support. */
13169 #define MAX_VECT_LEN 16
13171 struct expand_vec_perm_d
13172 {
13174 auto_vec_perm_indices perm;
13175 machine_mode vmode;
13178 };
13180 /* Generate a variable permutation. */
13182 static void
13184 {
13195 {
13197 {
13198 /* Expand the argument to a V16QI mode by duplicating it. */
13202 }
13203 else
13204 {
13206 }
13207 }
13208 else
13209 {
13210 rtx pair;
13213 {
13217 }
13218 else
13219 {
13223 }
13224 }
13225 }
13227 /* Expand a vec_perm with the operands given by TARGET, OP0, OP1 and SEL.
13228 NELT is the number of elements in the vector. */
13230 void
13233 {
13236 rtx mask;
13238 /* The TBL instruction does not use a modulo index, so we must take care
13239 of that ourselves. */
13244 /* For big-endian, we also need to reverse the index within the vector
13245 (but not which vector). */
13247 {
13248 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
13253 }
13255 }
13257 /* Recognize patterns suitable for the TRN instructions. */
13258 static bool
13260 {
13268 /* Note that these are little-endian tests.
13269 We correct for big-endian later. */
13274 else
13279 {
13284 }
13286 /* Success! */
13293 {
13296 }
13302 }
13304 /* Recognize patterns suitable for the UZP instructions. */
13305 static bool
13307 {
13315 /* Note that these are little-endian tests.
13316 We correct for big-endian later. */
13321 else
13326 {
13330 }
13332 /* Success! */
13339 {
13342 }
13348 }
13350 /* Recognize patterns suitable for the ZIP instructions. */
13351 static bool
13353 {
13361 /* Note that these are little-endian tests.
13362 We correct for big-endian later. */
13365 /* Do Nothing. */
13366 ;
13369 else
13374 {
13381 }
13383 /* Success! */
13390 {
13393 }
13399 }
13401 /* Recognize patterns for the EXT insn. */
13403 static bool
13405 {
13407 rtx offset;
13411 /* Check if the extracted indices are increasing by one. */
13413 {
13416 {
13417 /* We'll pass the same vector in twice, so allow indices to wrap. */
13419 }
13422 }
13424 /* Success! */
13428 /* The case where (location == 0) is a no-op for both big- and little-endian,
13429 and is removed by the mid-end at optimization levels -O1 and higher. */
13432 {
13433 /* After setup, we want the high elements of the first vector (stored
13434 at the LSB end of the register), and the low elements of the second
13435 vector (stored at the MSB end of the register). So swap. */
13437 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
13439 }
13445 UNSPEC_EXT));
13447 }
13449 /* Recognize patterns for the REV insns. */
13451 static bool
13453 {
13467 else
13472 {
13473 /* This is guaranteed to be true as the value of diff
13474 is 7, 3, 1 and we should have enough elements in the
13475 queue to generate this. Getting a vector mask with a
13476 value of diff other than these values implies that
13477 something is wrong by the time we get here. */
13481 }
13483 /* Success! */
13488 unspec));
13490 }
13492 static bool
13494 {
13496 rtx in0;
13499 rtx lane;
13503 {
13506 }
13508 /* The generic preparation in aarch64_expand_vec_perm_const_1
13509 swaps the operand order and the permute indices if it finds
13510 d->perm[0] to be in the second operand. Thus, we can always
13511 use d->op0 and need not do any extra arithmetic to get the
13512 correct lane number. */
13520 }
13522 static bool
13524 {
13532 /* Generic code will try constant permutation twice. Once with the
13533 original mode and again with the elements lowered to QImode.
13534 So wait and don't do the selector expansion ourselves. */
13539 {
13542 /* If big-endian and two vectors we end up with a weird mixed-endian
13543 mode on NEON. Reverse the index within each word but not the word
13544 itself. */
13547 }
13553 }
13555 static bool
13557 {
13558 /* The pattern matching functions above are written to look for a small
13559 number to begin the sequence (0, 1, N/2). If we begin with an index
13560 from the second operand, we can swap the operands. */
13563 {
13569 }
13572 {
13586 }
13588 }
13590 /* Expand a vec_perm_const pattern with the operands given by TARGET,
13591 OP0, OP1 and SEL. NELT is the number of elements in the vector. */
13593 bool
13596 {
13610 {
13615 }
13618 {
13627 /* The elements of PERM do not suggest that only the first operand
13628 is used, but both operands are identical. Allow easier matching
13629 of the permutation by folding the permutation into the single
13630 input vector. */
13631 /* Fall Through. */
13643 }
13646 }
13648 static bool
13650 {
13659 /* Calculate whether all elements are in one vector. */
13662 {
13666 }
13668 /* If all elements are from the second vector, reindex as if from the
13669 first vector. */
13674 /* Check whether the mask can be applied to a single vector. */
13687 }
13689 /* Generate a byte permute mask for a register of mode MODE,
13690 which has NUNITS units. */
13692 rtx
13694 {
13695 /* We have to reverse each vector because we dont have
13696 a permuted load that can reverse-load according to ABI rules. */
13697 rtx mask;
13710 }
13712 /* Implement TARGET_MODES_TIEABLE_P. In principle we should always return
13713 true. However due to issues with register allocation it is preferable
13714 to avoid tieing integer scalar and FP scalar modes. Executing integer
13715 operations in general registers is better than treating them as scalar
13716 vector operations. This reduces latency and avoids redundant int<->FP
13717 moves. So tie modes if they are either the same class, or vector modes
13718 with other vector modes, vector structs or any scalar mode. */
13720 static bool
13722 {
13726 /* We specifically want to allow elements of "structure" modes to
13727 be tieable to the structure. This more general condition allows
13728 other rarer situations too. */
13732 /* Also allow any scalar modes with vectors. */
13738 }
13740 /* Return a new RTX holding the result of moving POINTER forward by
13741 AMOUNT bytes. */
13743 static rtx
13745 {
13750 }
13752 /* Return a new RTX holding the result of moving POINTER forward by the
13753 size of the mode it points to. */
13755 static rtx
13757 {
13761 }
13763 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
13764 MODE bytes. */
13766 static void
13768 machine_mode mode)
13769 {
13772 /* "Cast" the pointers to the correct mode. */
13775 /* Emit the memcpy. */
13778 /* Move the pointers forward. */
13781 }
13783 /* Expand movmem, as if from a __builtin_memcpy. Return true if
13784 we succeed, otherwise return false. */
13786 bool
13788 {
13792 rtx base;
13795 /* When optimizing for size, give a better estimate of the length of a
13796 memcpy call, but use the default otherwise. */
13799 /* We can't do anything smart if the amount to copy is not constant. */
13805 /* Try to keep the number of instructions low. For cases below 16 bytes we
13806 need to make at most two moves. For cases above 16 bytes it will be one
13807 move for each 16 byte chunk, then at most two additional moves. */
13817 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
13818 1-byte chunk. */
13820 {
13822 {
13825 }
13831 }
13833 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
13834 4-byte chunk, partially overlapping with the previously copied chunk. */
13836 {
13840 {
13846 }
13848 }
13850 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
13851 them, then (if applicable) an 8-byte chunk. */
13853 {
13855 {
13858 }
13859 else
13860 {
13863 }
13864 }
13866 /* Finish the final bytes of the copy. We can always do this in one
13867 instruction. We either copy the exact amount we need, or partially
13868 overlap with the previous chunk we copied and copy 8-bytes. */
13877 else
13878 {
13880 {
13884 }
13885 else
13886 {
13892 }
13893 }
13896 }
13898 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
13899 SImode stores. Handle the case when the constant has identical
13900 bottom and top halves. This is beneficial when the two stores can be
13901 merged into an STP and we avoid synthesising potentially expensive
13902 immediates twice. Return true if such a split is possible. */
13904 bool
13906 {
13915 unsigned int orig_cost
13917 unsigned int lo_cost
13920 /* We want to transform:
13921 MOV x1, 49370
13922 MOVK x1, 0x140, lsl 16
13923 MOVK x1, 0xc0da, lsl 32
13924 MOVK x1, 0x140, lsl 48
13925 STR x1, [x0]
13926 into:
13927 MOV w1, 49370
13928 MOVK w1, 0x140, lsl 16
13929 STP w1, w1, [x0]
13930 So we want to perform this only when we save two instructions
13931 or more. When optimizing for size, however, accept any code size
13932 savings we can. */
13947 /* Don't emit an explicit store pair as this may not be always profitable.
13948 Let the sched-fusion logic decide whether to merge them. */
13953 }
13955 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
13957 static unsigned HOST_WIDE_INT
13959 {
13961 }
13963 static bool
13968 {
13969 /* STORE_BY_PIECES can be used when copying a constant string, but
13970 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
13971 For now we always fail this and let the move_by_pieces code copy
13972 the string from read-only memory. */
13977 }
13979 static rtx
13982 {
13986 insn_code icode;
13997 {
14025 }
14030 {
14033 }
14042 {
14045 }
14051 }
14053 static rtx
14056 {
14060 insn_code icode;
14072 {
14100 }
14105 {
14108 }
14116 {
14121 }
14132 {
14135 }
14141 }
14143 #undef TARGET_GEN_CCMP_FIRST
14144 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
14146 #undef TARGET_GEN_CCMP_NEXT
14147 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
14149 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
14150 instruction fusion of some sort. */
14152 static bool
14154 {
14156 }
14159 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
14160 should be kept together during scheduling. */
14162 static bool
14164 {
14165 rtx set_dest;
14168 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
14175 {
14176 /* We are trying to match:
14177 prev (mov) == (set (reg r0) (const_int imm16))
14178 curr (movk) == (set (zero_extract (reg r0)
14179 (const_int 16)
14180 (const_int 16))
14181 (const_int imm16_1)) */
14193 {
14195 }
14196 }
14199 {
14201 /* We're trying to match:
14202 prev (adrp) == (set (reg r1)
14203 (high (symbol_ref ("SYM"))))
14204 curr (add) == (set (reg r0)
14205 (lo_sum (reg r1)
14206 (symbol_ref ("SYM"))))
14207 Note that r0 need not necessarily be the same as r1, especially
14208 during pre-regalloc scheduling. */
14212 {
14220 }
14221 }
14224 {
14226 /* We're trying to match:
14227 prev (movk) == (set (zero_extract (reg r0)
14228 (const_int 16)
14229 (const_int 32))
14230 (const_int imm16_1))
14231 curr (movk) == (set (zero_extract (reg r0)
14232 (const_int 16)
14233 (const_int 48))
14234 (const_int imm16_2)) */
14250 }
14252 {
14253 /* We're trying to match:
14254 prev (adrp) == (set (reg r0)
14255 (high (symbol_ref ("SYM"))))
14256 curr (ldr) == (set (reg r1)
14257 (mem (lo_sum (reg r0)
14258 (symbol_ref ("SYM")))))
14259 or
14260 curr (ldr) == (set (reg r1)
14261 (zero_extend (mem
14262 (lo_sum (reg r0)
14263 (symbol_ref ("SYM")))))) */
14266 {
14279 }
14280 }
14288 {
14292 rtx cc_reg_1;
14297 && prev
14299 {
14300 /* FIXME: this misses some which is considered simple arthematic
14301 instructions for ThunderX. Simple shifts are missed here. */
14307 }
14308 }
14311 && curr_set
14314 {
14315 /* We're trying to match:
14316 prev (alu_insn) == (set (r0) plus ((r0) (r1/imm)))
14317 curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0)
14318 (const_int 0))
14319 (label_ref ("SYM"))
14320 (pc)) */
14327 {
14328 /* Fuse ALU operations followed by conditional branch instruction. */
14330 {
14351 }
14352 }
14353 }
14356 }
14358 /* Return true iff the instruction fusion described by OP is enabled. */
14360 bool
14362 {
14364 }
14366 /* If MEM is in the form of [base+offset], extract the two parts
14367 of address and set to BASE and OFFSET, otherwise return false
14368 after clearing BASE and OFFSET. */
14370 bool
14372 {
14373 rtx addr;
14380 {
14384 }
14388 {
14392 }
14398 }
14400 /* Types for scheduling fusion. */
14401 enum sched_fusion_type
14402 {
14404 SCHED_FUSION_LD_SIGN_EXTEND,
14405 SCHED_FUSION_LD_ZERO_EXTEND,
14406 SCHED_FUSION_LD,
14407 SCHED_FUSION_ST,
14408 SCHED_FUSION_NUM
14409 };
14411 /* If INSN is a load or store of address in the form of [base+offset],
14412 extract the two parts and set to BASE and OFFSET. Return scheduling
14413 fusion type this INSN is. */
14415 static enum sched_fusion_type
14417 {
14435 {
14440 }
14442 {
14447 }
14452 {
14455 }
14456 else
14463 }
14465 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
14467 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
14468 and PRI are only calculated for these instructions. For other instruction,
14469 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
14470 type instruction fusion can be added by returning different priorities.
14472 It's important that irrelevant instructions get the largest FUSION_PRI. */
14474 static void
14477 {
14487 {
14491 }
14493 /* Set FUSION_PRI according to fusion type and base register. */
14496 /* Calculate PRI. */
14499 /* INSN with smaller offset goes first. */
14503 else
14508 }
14510 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
14511 Adjust priority of sha1h instructions so they are scheduled before
14512 other SHA1 instructions. */
14514 static int
14516 {
14520 {
14525 }
14528 }
14530 /* Given OPERANDS of consecutive load/store, check if we can merge
14531 them into ldp/stp. LOAD is true if they are load instructions.
14532 MODE is the mode of memory operands. */
14534 bool
14536 machine_mode mode)
14537 {
14543 {
14551 }
14552 else
14553 {
14558 }
14560 /* The mems cannot be volatile. */
14564 /* If we have SImode and slow unaligned ldp,
14565 check the alignment to be at least 8 byte. */
14569 && !optimize_size
14573 /* Check if the addresses are in the form of [base+offset]. */
14581 /* Check if the bases are same. */
14588 /* Check if the offsets are consecutive. */
14592 /* Check if the addresses are clobbered by load. */
14594 {
14598 /* In increasing order, the last load can clobber the address. */
14601 }
14605 else
14610 else
14613 /* Check if the registers are of same class. */
14618 }
14620 /* Given OPERANDS of consecutive load/store, check if we can merge
14621 them into ldp/stp by adjusting the offset. LOAD is true if they
14622 are load instructions. MODE is the mode of memory operands.
14624 Given below consecutive stores:
14626 str w1, [xb, 0x100]
14627 str w1, [xb, 0x104]
14628 str w1, [xb, 0x108]
14629 str w1, [xb, 0x10c]
14631 Though the offsets are out of the range supported by stp, we can
14632 still pair them after adjusting the offset, like:
14634 add scratch, xb, 0x100
14635 stp w1, w1, [scratch]
14636 stp w1, w1, [scratch, 0x8]
14638 The peephole patterns detecting this opportunity should guarantee
14639 the scratch register is avaliable. */
14641 bool
14643 scalar_mode mode)
14644 {
14651 {
14664 }
14665 else
14666 {
14675 }
14676 /* Skip if memory operand is by itslef valid for ldp/stp. */
14680 /* The mems cannot be volatile. */
14685 /* Check if the addresses are in the form of [base+offset]. */
14699 /* Check if the bases are same. */
14710 /* Check if the offsets are consecutive. */
14719 /* Check if the addresses are clobbered by load. */
14721 {
14727 /* In increasing order, the last load can clobber the address. */
14730 }
14732 /* If we have SImode and slow unaligned ldp,
14733 check the alignment to be at least 8 byte. */
14737 && !optimize_size
14743 else
14748 else
14753 else
14758 else
14761 /* Check if the registers are of same class. */
14766 }
14768 /* Given OPERANDS of consecutive load/store, this function pairs them
14769 into ldp/stp after adjusting the offset. It depends on the fact
14770 that addresses of load/store instructions are in increasing order.
14771 MODE is the mode of memory operands. CODE is the rtl operator
14772 which should be applied to all memory operands, it's SIGN_EXTEND,
14773 ZERO_EXTEND or UNKNOWN. */
14775 bool
14778 {
14784 {
14789 }
14790 else
14791 {
14797 }
14802 /* Adjust offset thus it can fit in ldp/stp instruction. */
14810 /* Further adjust to make sure all offsets are OK. */
14812 {
14815 }
14817 /* Make sure the adjustment can be done with ADD/SUB instructions. */
14822 {
14825 }
14827 /* Create new memory references. */
14831 /* Check if the adjusted address is OK for ldp/stp. */
14850 {
14855 }
14857 {
14862 }
14865 {
14870 }
14871 else
14872 {
14877 }
14879 /* Emit adjusting instruction. */
14881 /* Emit ldp/stp instructions. */
14889 }
14891 /* Return 1 if pseudo register should be created and used to hold
14892 GOT address for PIC code. */
14894 bool
14896 {
14898 }
14900 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
14902 static int
14904 {
14906 {
14913 }
14916 }
14919 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
14920 return the log2 of that value. Otherwise return -1. */
14922 int
14924 {
14939 }
14941 /* If X is a vector of equal CONST_DOUBLE values and that value is
14942 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
14944 int
14946 {
14962 }
14964 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
14965 to float.
14967 __fp16 always promotes through this hook.
14968 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
14969 through the generic excess precision logic rather than here. */
14971 static tree
14973 {
14979 }
14981 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
14983 static bool
14985 optimization_type opt_type)
14986 {
14988 {
14994 }
14995 }
14997 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
14998 if MODE is HFmode, and punt to the generic implementation otherwise. */
15000 static bool
15002 {
15006 }
15008 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
15009 if MODE is HFmode, and punt to the generic implementation otherwise. */
15011 static bool
15013 {
15017 }
15019 /* Set the value of FLT_EVAL_METHOD.
15020 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
15022 0: evaluate all operations and constants, whose semantic type has at
15023 most the range and precision of type float, to the range and
15024 precision of float; evaluate all other operations and constants to
15025 the range and precision of the semantic type;
15027 N, where _FloatN is a supported interchange floating type
15028 evaluate all operations and constants, whose semantic type has at
15029 most the range and precision of _FloatN type, to the range and
15030 precision of the _FloatN type; evaluate all other operations and
15031 constants to the range and precision of the semantic type;
15033 If we have the ARMv8.2-A extensions then we support _Float16 in native
15034 precision, so we should set this to 16. Otherwise, we support the type,
15035 but want to evaluate expressions in float precision, so set this to
15036 0. */
15038 static enum flt_eval_method
15040 {
15042 {
15045 /* We can calculate either in 16-bit range and precision or
15046 32-bit range and precision. Make that decision based on whether
15047 we have native support for the ARMv8.2-A 16-bit floating-point
15048 instructions or not. */
15050 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
15056 }
15058 }
15060 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
15061 scheduled for speculative execution. Reject the long-running division
15062 and square-root instructions. */
15064 static bool
15066 {
15068 {
15086 }
15087 }
15089 /* Target-specific selftests. */
15091 #if CHECKING_P
15095 /* Selftest for the RTL loader.
15096 Verify that the RTL loader copes with a dump from
15097 print_rtx_function. This is essentially just a test that class
15098 function_reader can handle a real dump, but it also verifies
15099 that lookup_reg_by_dump_name correctly handles hard regs.
15100 The presence of hard reg names in the dump means that the test is
15101 target-specific, hence it is in this file. */
15103 static void
15105 {
15117 /* Verify crtl->return_rtx. */
15121 }
15123 /* Run all target-specific selftests. */
15125 static void
15127 {
15129 }
15135 #undef TARGET_ADDRESS_COST
15136 #define TARGET_ADDRESS_COST aarch64_address_cost
15138 /* This hook will determines whether unnamed bitfields affect the alignment
15139 of the containing structure. The hook returns true if the structure
15140 should inherit the alignment requirements of an unnamed bitfield's
15141 type. */
15142 #undef TARGET_ALIGN_ANON_BITFIELD
15143 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
15145 #undef TARGET_ASM_ALIGNED_DI_OP
15148 #undef TARGET_ASM_ALIGNED_HI_OP
15151 #undef TARGET_ASM_ALIGNED_SI_OP
15154 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
15155 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
15156 hook_bool_const_tree_hwi_hwi_const_tree_true
15158 #undef TARGET_ASM_FILE_START
15159 #define TARGET_ASM_FILE_START aarch64_start_file
15161 #undef TARGET_ASM_OUTPUT_MI_THUNK
15162 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
15164 #undef TARGET_ASM_SELECT_RTX_SECTION
15165 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
15167 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
15168 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
15170 #undef TARGET_BUILD_BUILTIN_VA_LIST
15171 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
15173 #undef TARGET_CALLEE_COPIES
15174 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
15176 #undef TARGET_CAN_ELIMINATE
15177 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
15179 #undef TARGET_CAN_INLINE_P
15180 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
15182 #undef TARGET_CANNOT_FORCE_CONST_MEM
15183 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
15185 #undef TARGET_CASE_VALUES_THRESHOLD
15186 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
15188 #undef TARGET_CONDITIONAL_REGISTER_USAGE
15189 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
15191 /* Only the least significant bit is used for initialization guard
15192 variables. */
15193 #undef TARGET_CXX_GUARD_MASK_BIT
15194 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
15196 #undef TARGET_C_MODE_FOR_SUFFIX
15197 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
15199 #ifdef TARGET_BIG_ENDIAN_DEFAULT
15200 #undef TARGET_DEFAULT_TARGET_FLAGS
15201 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
15202 #endif
15204 #undef TARGET_CLASS_MAX_NREGS
15205 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
15207 #undef TARGET_BUILTIN_DECL
15208 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
15210 #undef TARGET_BUILTIN_RECIPROCAL
15211 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
15213 #undef TARGET_C_EXCESS_PRECISION
15214 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
15216 #undef TARGET_EXPAND_BUILTIN
15217 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
15219 #undef TARGET_EXPAND_BUILTIN_VA_START
15220 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
15222 #undef TARGET_FOLD_BUILTIN
15223 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
15225 #undef TARGET_FUNCTION_ARG
15226 #define TARGET_FUNCTION_ARG aarch64_function_arg
15228 #undef TARGET_FUNCTION_ARG_ADVANCE
15229 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
15231 #undef TARGET_FUNCTION_ARG_BOUNDARY
15232 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
15234 #undef TARGET_FUNCTION_ARG_PADDING
15235 #define TARGET_FUNCTION_ARG_PADDING aarch64_function_arg_padding
15237 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
15238 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
15240 #undef TARGET_FUNCTION_VALUE
15241 #define TARGET_FUNCTION_VALUE aarch64_function_value
15243 #undef TARGET_FUNCTION_VALUE_REGNO_P
15244 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
15246 #undef TARGET_GIMPLE_FOLD_BUILTIN
15247 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
15249 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
15250 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
15252 #undef TARGET_INIT_BUILTINS
15253 #define TARGET_INIT_BUILTINS aarch64_init_builtins
15255 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
15256 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
15257 aarch64_ira_change_pseudo_allocno_class
15259 #undef TARGET_LEGITIMATE_ADDRESS_P
15260 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
15262 #undef TARGET_LEGITIMATE_CONSTANT_P
15263 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
15265 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
15266 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
15267 aarch64_legitimize_address_displacement
15269 #undef TARGET_LIBGCC_CMP_RETURN_MODE
15270 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
15272 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
15273 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
15274 aarch64_libgcc_floating_mode_supported_p
15276 #undef TARGET_MANGLE_TYPE
15277 #define TARGET_MANGLE_TYPE aarch64_mangle_type
15279 #undef TARGET_MEMORY_MOVE_COST
15280 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
15282 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
15283 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
15285 #undef TARGET_MUST_PASS_IN_STACK
15286 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
15288 /* This target hook should return true if accesses to volatile bitfields
15289 should use the narrowest mode possible. It should return false if these
15290 accesses should use the bitfield container type. */
15291 #undef TARGET_NARROW_VOLATILE_BITFIELD
15292 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
15294 #undef TARGET_OPTION_OVERRIDE
15295 #define TARGET_OPTION_OVERRIDE aarch64_override_options
15297 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
15298 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
15299 aarch64_override_options_after_change
15301 #undef TARGET_OPTION_SAVE
15302 #define TARGET_OPTION_SAVE aarch64_option_save
15304 #undef TARGET_OPTION_RESTORE
15305 #define TARGET_OPTION_RESTORE aarch64_option_restore
15307 #undef TARGET_OPTION_PRINT
15308 #define TARGET_OPTION_PRINT aarch64_option_print
15310 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
15311 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
15313 #undef TARGET_SET_CURRENT_FUNCTION
15314 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
15316 #undef TARGET_PASS_BY_REFERENCE
15317 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
15319 #undef TARGET_PREFERRED_RELOAD_CLASS
15320 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
15322 #undef TARGET_SCHED_REASSOCIATION_WIDTH
15323 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
15325 #undef TARGET_PROMOTED_TYPE
15326 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
15328 #undef TARGET_SECONDARY_RELOAD
15329 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
15331 #undef TARGET_SHIFT_TRUNCATION_MASK
15332 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
15334 #undef TARGET_SETUP_INCOMING_VARARGS
15335 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
15337 #undef TARGET_STRUCT_VALUE_RTX
15338 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
15340 #undef TARGET_REGISTER_MOVE_COST
15341 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
15343 #undef TARGET_RETURN_IN_MEMORY
15344 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
15346 #undef TARGET_RETURN_IN_MSB
15347 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
15349 #undef TARGET_RTX_COSTS
15350 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
15352 #undef TARGET_SCALAR_MODE_SUPPORTED_P
15353 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
15355 #undef TARGET_SCHED_ISSUE_RATE
15356 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
15358 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
15359 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
15360 aarch64_sched_first_cycle_multipass_dfa_lookahead
15362 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
15363 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
15364 aarch64_first_cycle_multipass_dfa_lookahead_guard
15366 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
15367 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
15368 aarch64_get_separate_components
15370 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
15371 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
15372 aarch64_components_for_bb
15374 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
15375 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
15376 aarch64_disqualify_components
15378 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
15379 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
15380 aarch64_emit_prologue_components
15382 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
15383 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
15384 aarch64_emit_epilogue_components
15386 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
15387 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
15388 aarch64_set_handled_components
15390 #undef TARGET_TRAMPOLINE_INIT
15391 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
15393 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
15394 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
15396 #undef TARGET_VECTOR_MODE_SUPPORTED_P
15397 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
15399 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
15400 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
15401 aarch64_builtin_support_vector_misalignment
15403 #undef TARGET_ARRAY_MODE_SUPPORTED_P
15404 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
15406 #undef TARGET_VECTORIZE_ADD_STMT_COST
15407 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
15409 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
15410 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
15411 aarch64_builtin_vectorization_cost
15413 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
15414 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
15416 #undef TARGET_VECTORIZE_BUILTINS
15417 #define TARGET_VECTORIZE_BUILTINS
15419 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
15420 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
15421 aarch64_builtin_vectorized_function
15423 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
15424 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
15425 aarch64_autovectorize_vector_sizes
15427 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
15428 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
15429 aarch64_atomic_assign_expand_fenv
15431 /* Section anchor support. */
15433 #undef TARGET_MIN_ANCHOR_OFFSET
15434 #define TARGET_MIN_ANCHOR_OFFSET -256
15436 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
15437 byte offset; we can do much more for larger data types, but have no way
15438 to determine the size of the access. We assume accesses are aligned. */
15439 #undef TARGET_MAX_ANCHOR_OFFSET
15440 #define TARGET_MAX_ANCHOR_OFFSET 4095
15442 #undef TARGET_VECTOR_ALIGNMENT
15443 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
15445 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
15446 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
15447 aarch64_simd_vector_alignment_reachable
15449 /* vec_perm support. */
15451 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
15452 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
15453 aarch64_vectorize_vec_perm_const_ok
15455 #undef TARGET_INIT_LIBFUNCS
15456 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
15458 #undef TARGET_FIXED_CONDITION_CODE_REGS
15459 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
15461 #undef TARGET_FLAGS_REGNUM
15462 #define TARGET_FLAGS_REGNUM CC_REGNUM
15464 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
15465 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
15467 #undef TARGET_ASAN_SHADOW_OFFSET
15468 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
15470 #undef TARGET_LEGITIMIZE_ADDRESS
15471 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
15473 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
15474 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
15475 aarch64_use_by_pieces_infrastructure_p
15477 #undef TARGET_SCHED_CAN_SPECULATE_INSN
15478 #define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn
15480 #undef TARGET_CAN_USE_DOLOOP_P
15481 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
15483 #undef TARGET_SCHED_ADJUST_PRIORITY
15484 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
15486 #undef TARGET_SCHED_MACRO_FUSION_P
15487 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
15489 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
15490 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
15492 #undef TARGET_SCHED_FUSION_PRIORITY
15493 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
15495 #undef TARGET_UNSPEC_MAY_TRAP_P
15496 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
15498 #undef TARGET_USE_PSEUDO_PIC_REG
15499 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
15501 #undef TARGET_PRINT_OPERAND
15502 #define TARGET_PRINT_OPERAND aarch64_print_operand
15504 #undef TARGET_PRINT_OPERAND_ADDRESS
15505 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
15507 #undef TARGET_OPTAB_SUPPORTED_P
15508 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
15510 #undef TARGET_OMIT_STRUCT_RETURN_REG
15511 #define TARGET_OMIT_STRUCT_RETURN_REG true
15513 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
15514 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
15515 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
15517 #undef TARGET_HARD_REGNO_NREGS
15518 #define TARGET_HARD_REGNO_NREGS aarch64_hard_regno_nregs
15519 #undef TARGET_HARD_REGNO_MODE_OK
15520 #define TARGET_HARD_REGNO_MODE_OK aarch64_hard_regno_mode_ok
15522 #undef TARGET_MODES_TIEABLE_P
15523 #define TARGET_MODES_TIEABLE_P aarch64_modes_tieable_p
15525 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
15526 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
15527 aarch64_hard_regno_call_part_clobbered
15529 #undef TARGET_CONSTANT_ALIGNMENT
15530 #define TARGET_CONSTANT_ALIGNMENT aarch64_constant_alignment
15532 #if CHECKING_P
15533 #undef TARGET_RUN_TARGET_SELFTESTS
15534 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests