1 ;; Machine Description for Renesas RL78 processors
2 ;; Copyright (C) 2011-2013 Free Software Foundation, Inc.
3 ;; Contributed by Red Hat.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;---------- Moving ------------------------
23 (define_expand "movqi"
24 [(set (match_operand:QI 0 "nonimmediate_operand")
25 (match_operand:QI 1 "general_operand"))]
28 if (MEM_P (operand0) && MEM_P (operand1))
29 operands[1] = copy_to_mode_reg (QImode, operand1);
30 if (rl78_far_p (operand0) && rl78_far_p (operand1))
31 operands[1] = copy_to_mode_reg (QImode, operand1);
33 /* FIXME: Not sure how GCC can generate (SUBREG (SYMBOL_REF)),
34 but it does. Since this makes no sense, reject it here. */
35 if (GET_CODE (operand1) == SUBREG
36 && GET_CODE (XEXP (operand1, 0)) == SYMBOL_REF)
38 /* Similarly for (SUBREG (CONST (PLUS (SYMBOL_REF)))).
39 cf. g++.dg/abi/packed.C. */
40 if (GET_CODE (operand1) == SUBREG
41 && GET_CODE (XEXP (operand1, 0)) == CONST
42 && GET_CODE (XEXP (XEXP (operand1, 0), 0)) == PLUS
43 && GET_CODE (XEXP (XEXP (XEXP (operand1, 0), 0), 0)) == SYMBOL_REF)
46 if (CONST_INT_P (operand1) && ! IN_RANGE (INTVAL (operand1), (-1 << 8) + 1, (1 << 8) - 1))
51 (define_expand "movhi"
52 [(set (match_operand:HI 0 "nonimmediate_operand")
53 (match_operand:HI 1 "general_operand"))]
56 if (MEM_P (operand0) && MEM_P (operand1))
57 operands[1] = copy_to_mode_reg (HImode, operand1);
58 if (rl78_far_p (operand0) && rl78_far_p (operand1))
59 operands[1] = copy_to_mode_reg (HImode, operand1);
61 /* FIXME: Not sure how GCC can generate (SUBREG (SYMBOL_REF)),
62 but it does. Since this makes no sense, reject it here. */
63 if (GET_CODE (operand1) == SUBREG
64 && GET_CODE (XEXP (operand1, 0)) == SYMBOL_REF)
66 /* Similarly for (SUBREG (CONST (PLUS (SYMBOL_REF)))). */
67 if (GET_CODE (operand1) == SUBREG
68 && GET_CODE (XEXP (operand1, 0)) == CONST
69 && GET_CODE (XEXP (XEXP (operand1, 0), 0)) == PLUS
70 && GET_CODE (XEXP (XEXP (XEXP (operand1, 0), 0), 0)) == SYMBOL_REF)
75 (define_insn_and_split "movsi"
76 [(set (match_operand:SI 0 "nonimmediate_operand" "=vYS,v,Wfr")
77 (match_operand:SI 1 "general_operand" "viYS,Wfr,v"))]
81 [(set (match_operand:HI 2 "nonimmediate_operand")
82 (match_operand:HI 4 "general_operand"))
83 (set (match_operand:HI 3 "nonimmediate_operand")
84 (match_operand:HI 5 "general_operand"))]
85 "rl78_split_movsi (operands);"
86 [(set_attr "valloc" "op1")]
89 ;;---------- Conversions ------------------------
91 (define_expand "zero_extendqihi2"
92 [(set (match_operand:HI 0 "nonimmediate_operand")
93 (zero_extend:HI (match_operand:QI 1 "general_operand")))]
95 "if (rl78_force_nonfar_2 (operands, gen_zero_extendqihi2))
99 (define_expand "extendqihi2"
100 [(set (match_operand:HI 0 "nonimmediate_operand")
101 (sign_extend:HI (match_operand:QI 1 "general_operand")))]
103 "if (rl78_force_nonfar_2 (operands, gen_extendqihi2))
107 ;;---------- Arithmetic ------------------------
109 (define_expand "add<mode>3"
110 [(set (match_operand:QHI 0 "nonimmediate_operand")
111 (plus:QHI (match_operand:QHI 1 "general_operand")
112 (match_operand:QHI 2 "general_operand")))
115 "if (rl78_force_nonfar_3 (operands, gen_add<mode>3))
119 (define_expand "sub<mode>3"
120 [(set (match_operand:QHI 0 "nonimmediate_operand")
121 (minus:QHI (match_operand:QHI 1 "general_operand")
122 (match_operand:QHI 2 "general_operand")))
125 "if (rl78_force_nonfar_3 (operands, gen_sub<mode>3))
129 (define_expand "neg<mode>2"
130 [(set (match_operand:QHI 0 "nonimmediate_operand")
131 (minus:QHI (const_int 0)
132 (match_operand:QHI 1 "general_operand")))
135 "if (rl78_force_nonfar_2 (operands, gen_neg<mode>2))
139 (define_expand "umulqihi3"
140 [(set (match_operand:HI 0 "register_operand")
141 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand"))
142 (zero_extend:HI (match_operand:QI 2 "register_operand"))))]
147 (define_expand "andqi3"
148 [(set (match_operand:QI 0 "nonimmediate_operand")
149 (and:QI (match_operand:QI 1 "general_operand")
150 (match_operand:QI 2 "general_operand")))
153 "if (rl78_force_nonfar_3 (operands, gen_andqi3))
157 (define_expand "iorqi3"
158 [(set (match_operand:QI 0 "nonimmediate_operand")
159 (ior:QI (match_operand:QI 1 "general_operand")
160 (match_operand:QI 2 "general_operand")))
163 "if (rl78_force_nonfar_3 (operands, gen_iorqi3))
167 (define_expand "xorqi3"
168 [(set (match_operand:QI 0 "nonimmediate_operand")
169 (xor:QI (match_operand:QI 1 "general_operand")
170 (match_operand:QI 2 "general_operand")))
173 "if (rl78_force_nonfar_3 (operands, gen_xorqi3))
177 (define_expand "one_cmplqi2"
178 [(set (match_operand:QI 0 "nonimmediate_operand")
179 (xor:QI (match_operand:QI 1 "general_operand")
183 "if (rl78_force_nonfar_2 (operands, gen_one_cmplqi2))
187 ;;---------- Shifts ------------------------
189 (define_expand "ashl<mode>3"
190 [(set (match_operand:QHI 0 "nonimmediate_operand")
191 (ashift:QHI (match_operand:QHI 1 "general_operand")
192 (match_operand:QI 2 "general_operand")))
195 "if (rl78_force_nonfar_3 (operands, gen_ashl<mode>3))
199 (define_expand "ashr<mode>3"
200 [(set (match_operand:QHI 0 "nonimmediate_operand")
201 (ashiftrt:QHI (match_operand:QHI 1 "general_operand")
202 (match_operand:QI 2 "general_operand")))
205 "if (rl78_force_nonfar_3 (operands, gen_ashr<mode>3))
209 (define_expand "lshr<mode>3"
210 [(set (match_operand:QHI 0 "nonimmediate_operand")
211 (lshiftrt:QHI (match_operand:QHI 1 "general_operand")
212 (match_operand:QI 2 "general_operand")))
215 "if (rl78_force_nonfar_3 (operands, gen_lshr<mode>3))
219 (define_expand "ashrsi3"
220 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand")
221 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand")
222 (match_operand:SI 2 "nonmemory_operand")))
223 (clobber (reg:HI X_REG))])
229 (define_expand "lshrsi3"
230 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand")
231 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand")
232 (match_operand:SI 2 "nonmemory_operand")))
233 (clobber (reg:HI X_REG))])
239 (define_expand "ashlsi3"
240 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand")
241 (ashift:SI (match_operand:SI 1 "nonimmediate_operand")
242 (match_operand:SI 2 "nonmemory_operand")))
243 (clobber (reg:HI X_REG))])
249 ;;---------- Branching ------------------------
251 (define_expand "indirect_jump"
253 (match_operand:HI 0 "nonimmediate_operand"))]
258 (define_expand "call"
259 [(call (match_operand:HI 0 "memory_operand")
260 (match_operand 1 ""))]
265 (define_expand "call_value"
266 [(set (match_operand 0 "register_operand")
267 (call (match_operand:HI 1 "memory_operand")
268 (match_operand 2 "")))]
273 (define_expand "cbranchqi4"
274 [(set (pc) (if_then_else
275 (match_operator 0 "rl78_cmp_operator"
276 [(match_operand:QI 1 "general_operand")
277 (match_operand:QI 2 "general_operand")])
278 (label_ref (match_operand 3 "" ""))
281 "rl78_expand_compare (operands);"
284 (define_expand "cbranchhi4"
285 [(set (pc) (if_then_else
286 (match_operator 0 "rl78_cmp_operator"
287 [(match_operand:HI 1 "general_operand")
288 (match_operand:HI 2 "general_operand")])
289 (label_ref (match_operand 3 "" ""))
292 "rl78_expand_compare (operands);"
295 (define_expand "cbranchsi4"
296 [(parallel [(set (pc) (if_then_else
297 (match_operator 0 "rl78_cmp_operator"
298 [(match_operand:SI 1 "general_operand")
299 (match_operand:SI 2 "nonmemory_operand")])
300 (label_ref (match_operand 3 "" ""))
302 (clobber (reg:HI AX_REG))
305 "rl78_expand_compare (operands);"