1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
4 ;; Free Software Foundation, Inc.
5 ;; Mostly by William Schelter.
6 ;; x86_64 support added by Jan Hubicka
8 ;; This file is part of GNU CC.
10 ;; GNU CC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GNU CC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GNU CC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA. */
25 ;; The original PO technology requires these to be ordered by speed,
26 ;; so that assigner will pick the fastest.
28 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 ;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code
31 ;; updates for most instructions.
33 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
34 ;; constraint letters.
36 ;; The special asm out single letter directives following a '%' are:
37 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
39 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
40 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
41 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
42 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
43 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
44 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
45 ;; 'J' Print the appropriate jump operand.
47 ;; 'b' Print the QImode name of the register for the indicated operand.
48 ;; %b0 would print %al if operands[0] is reg 0.
49 ;; 'w' Likewise, print the HImode name of the register.
50 ;; 'k' Likewise, print the SImode name of the register.
51 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
52 ;; 'y' Print "st(0)" instead of "st" as a register.
57 [; Relocation specifiers
69 (UNSPEC_STACK_PROBE 10)
70 (UNSPEC_STACK_ALLOC 11)
72 (UNSPEC_SSE_PROLOGUE_SAVE 13)
77 (UNSPEC_TLS_LD_BASE 17)
79 ; Other random patterns
89 ; For SSE/MMX support:
100 (UNSPEC_NOP 45) ; prevents combiner cleverness
119 [(UNSPECV_BLOCKAGE 0)
120 (UNSPECV_EH_RETURN 13)
128 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
131 ;; In C guard expressions, put expressions which may be compile-time
132 ;; constants first. This allows for better optimization. For
133 ;; example, write "TARGET_64BIT && reload_completed", not
134 ;; "reload_completed && TARGET_64BIT".
137 ;; Processor type. This attribute must exactly match the processor_type
138 ;; enumeration in i386.h.
139 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4,k8"
140 (const (symbol_ref "ix86_tune")))
142 ;; A basic instruction type. Refinements due to arguments to be
143 ;; provided in other attributes.
146 alu,alu1,negnot,imov,imovx,lea,
147 incdec,ishift,ishift1,rotate,rotate1,imul,idiv,
148 icmp,test,ibr,setcc,icmov,
149 push,pop,call,callv,leave,
151 fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,
152 sselog,sseiadd,sseishft,sseimul,
153 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,
154 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
155 (const_string "other"))
157 ;; Main data type used by the insn
159 "unknown,none,QI,HI,SI,DI,SF,DF,XF,TI,V4SF,V2DF,V2SF"
160 (const_string "unknown"))
162 ;; The CPU unit operations uses.
163 (define_attr "unit" "integer,i387,sse,mmx,unknown"
164 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp")
165 (const_string "i387")
166 (eq_attr "type" "sselog,sseiadd,sseishft,sseimul,
167 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv")
169 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
171 (eq_attr "type" "other")
172 (const_string "unknown")]
173 (const_string "integer")))
175 ;; The (bounding maximum) length of an instruction immediate.
176 (define_attr "length_immediate" ""
177 (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv,leave")
179 (eq_attr "unit" "i387,sse,mmx")
181 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1,
183 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
184 (eq_attr "type" "imov,test")
185 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
186 (eq_attr "type" "call")
187 (if_then_else (match_operand 0 "constant_call_address_operand" "")
190 (eq_attr "type" "callv")
191 (if_then_else (match_operand 1 "constant_call_address_operand" "")
194 ;; We don't know the size before shorten_branches. Expect
195 ;; the instruction to fit for better scheduling.
196 (eq_attr "type" "ibr")
199 (symbol_ref "/* Update immediate_length and other attributes! */
202 ;; The (bounding maximum) length of an instruction address.
203 (define_attr "length_address" ""
204 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
206 (and (eq_attr "type" "call")
207 (match_operand 0 "constant_call_address_operand" ""))
209 (and (eq_attr "type" "callv")
210 (match_operand 1 "constant_call_address_operand" ""))
213 (symbol_ref "ix86_attr_length_address_default (insn)")))
215 ;; Set when length prefix is used.
216 (define_attr "prefix_data16" ""
217 (if_then_else (ior (eq_attr "mode" "HI")
218 (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
222 ;; Set when string REP prefix is used.
223 (define_attr "prefix_rep" ""
224 (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
228 ;; Set when 0f opcode prefix is used.
229 (define_attr "prefix_0f" ""
231 (ior (eq_attr "type" "imovx,setcc,icmov")
232 (eq_attr "unit" "sse,mmx"))
236 ;; Set when 0f opcode prefix is used.
237 (define_attr "prefix_rex" ""
238 (cond [(and (eq_attr "mode" "DI")
239 (eq_attr "type" "!push,pop,call,callv,leave,ibr"))
241 (and (eq_attr "mode" "QI")
242 (ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")
245 (ne (symbol_ref "x86_extended_reg_mentioned_p (insn)")
251 ;; Set when modrm byte is used.
252 (define_attr "modrm" ""
253 (cond [(eq_attr "type" "str,cld,leave")
255 (eq_attr "unit" "i387")
257 (and (eq_attr "type" "incdec")
258 (ior (match_operand:SI 1 "register_operand" "")
259 (match_operand:HI 1 "register_operand" "")))
261 (and (eq_attr "type" "push")
262 (not (match_operand 1 "memory_operand" "")))
264 (and (eq_attr "type" "pop")
265 (not (match_operand 0 "memory_operand" "")))
267 (and (eq_attr "type" "imov")
268 (and (match_operand 0 "register_operand" "")
269 (match_operand 1 "immediate_operand" "")))
271 (and (eq_attr "type" "call")
272 (match_operand 0 "constant_call_address_operand" ""))
274 (and (eq_attr "type" "callv")
275 (match_operand 1 "constant_call_address_operand" ""))
280 ;; The (bounding maximum) length of an instruction in bytes.
281 ;; ??? fistp is in fact fldcw/fistp/fldcw sequence. Later we may want
282 ;; to split it and compute proper length as for other insns.
283 (define_attr "length" ""
284 (cond [(eq_attr "type" "other,multi,fistp")
286 (eq_attr "type" "fcmp")
288 (eq_attr "unit" "i387")
290 (plus (attr "prefix_data16")
291 (attr "length_address")))]
292 (plus (plus (attr "modrm")
293 (plus (attr "prefix_0f")
294 (plus (attr "prefix_rex")
296 (plus (attr "prefix_rep")
297 (plus (attr "prefix_data16")
298 (plus (attr "length_immediate")
299 (attr "length_address")))))))
301 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
302 ;; `store' if there is a simple memory reference therein, or `unknown'
303 ;; if the instruction is complex.
305 (define_attr "memory" "none,load,store,both,unknown"
306 (cond [(eq_attr "type" "other,multi,str")
307 (const_string "unknown")
308 (eq_attr "type" "lea,fcmov,fpspc,cld")
309 (const_string "none")
310 (eq_attr "type" "fistp,leave")
311 (const_string "both")
312 (eq_attr "type" "push")
313 (if_then_else (match_operand 1 "memory_operand" "")
314 (const_string "both")
315 (const_string "store"))
316 (eq_attr "type" "pop")
317 (if_then_else (match_operand 0 "memory_operand" "")
318 (const_string "both")
319 (const_string "load"))
320 (eq_attr "type" "setcc")
321 (if_then_else (match_operand 0 "memory_operand" "")
322 (const_string "store")
323 (const_string "none"))
324 (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")
325 (if_then_else (ior (match_operand 0 "memory_operand" "")
326 (match_operand 1 "memory_operand" ""))
327 (const_string "load")
328 (const_string "none"))
329 (eq_attr "type" "ibr")
330 (if_then_else (match_operand 0 "memory_operand" "")
331 (const_string "load")
332 (const_string "none"))
333 (eq_attr "type" "call")
334 (if_then_else (match_operand 0 "constant_call_address_operand" "")
335 (const_string "none")
336 (const_string "load"))
337 (eq_attr "type" "callv")
338 (if_then_else (match_operand 1 "constant_call_address_operand" "")
339 (const_string "none")
340 (const_string "load"))
341 (and (eq_attr "type" "alu1,negnot")
342 (match_operand 1 "memory_operand" ""))
343 (const_string "both")
344 (and (match_operand 0 "memory_operand" "")
345 (match_operand 1 "memory_operand" ""))
346 (const_string "both")
347 (match_operand 0 "memory_operand" "")
348 (const_string "store")
349 (match_operand 1 "memory_operand" "")
350 (const_string "load")
353 imov,imovx,icmp,test,
355 sse,ssemov,ssecmp,ssecomi,ssecvt,sseicvt,
356 mmx,mmxmov,mmxcmp,mmxcvt")
357 (match_operand 2 "memory_operand" ""))
358 (const_string "load")
359 (and (eq_attr "type" "icmov")
360 (match_operand 3 "memory_operand" ""))
361 (const_string "load")
363 (const_string "none")))
365 ;; Indicates if an instruction has both an immediate and a displacement.
367 (define_attr "imm_disp" "false,true,unknown"
368 (cond [(eq_attr "type" "other,multi")
369 (const_string "unknown")
370 (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
371 (and (match_operand 0 "memory_displacement_operand" "")
372 (match_operand 1 "immediate_operand" "")))
373 (const_string "true")
374 (and (eq_attr "type" "alu,ishift,rotate,imul,idiv")
375 (and (match_operand 0 "memory_displacement_operand" "")
376 (match_operand 2 "immediate_operand" "")))
377 (const_string "true")
379 (const_string "false")))
381 ;; Indicates if an FP operation has an integer source.
383 (define_attr "fp_int_src" "false,true"
384 (const_string "false"))
386 ;; Describe a user's asm statement.
387 (define_asm_attributes
388 [(set_attr "length" "128")
389 (set_attr "type" "multi")])
391 (include "pentium.md")
394 (include "athlon.md")
396 ;; Compare instructions.
398 ;; All compare insns have expanders that save the operands away without
399 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
400 ;; after the cmp) will actually emit the cmpM.
402 (define_expand "cmpdi"
404 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
405 (match_operand:DI 1 "x86_64_general_operand" "")))]
408 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
409 operands[0] = force_reg (DImode, operands[0]);
410 ix86_compare_op0 = operands[0];
411 ix86_compare_op1 = operands[1];
415 (define_expand "cmpsi"
417 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
418 (match_operand:SI 1 "general_operand" "")))]
421 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
422 operands[0] = force_reg (SImode, operands[0]);
423 ix86_compare_op0 = operands[0];
424 ix86_compare_op1 = operands[1];
428 (define_expand "cmphi"
430 (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
431 (match_operand:HI 1 "general_operand" "")))]
434 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
435 operands[0] = force_reg (HImode, operands[0]);
436 ix86_compare_op0 = operands[0];
437 ix86_compare_op1 = operands[1];
441 (define_expand "cmpqi"
443 (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
444 (match_operand:QI 1 "general_operand" "")))]
447 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
448 operands[0] = force_reg (QImode, operands[0]);
449 ix86_compare_op0 = operands[0];
450 ix86_compare_op1 = operands[1];
454 (define_insn "cmpdi_ccno_1_rex64"
456 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
457 (match_operand:DI 1 "const0_operand" "n,n")))]
458 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
460 test{q}\t{%0, %0|%0, %0}
461 cmp{q}\t{%1, %0|%0, %1}"
462 [(set_attr "type" "test,icmp")
463 (set_attr "length_immediate" "0,1")
464 (set_attr "mode" "DI")])
466 (define_insn "*cmpdi_minus_1_rex64"
468 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
469 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
471 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)"
472 "cmp{q}\t{%1, %0|%0, %1}"
473 [(set_attr "type" "icmp")
474 (set_attr "mode" "DI")])
476 (define_expand "cmpdi_1_rex64"
478 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
479 (match_operand:DI 1 "general_operand" "")))]
483 (define_insn "cmpdi_1_insn_rex64"
485 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
486 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
487 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
488 "cmp{q}\t{%1, %0|%0, %1}"
489 [(set_attr "type" "icmp")
490 (set_attr "mode" "DI")])
493 (define_insn "*cmpsi_ccno_1"
495 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
496 (match_operand:SI 1 "const0_operand" "n,n")))]
497 "ix86_match_ccmode (insn, CCNOmode)"
499 test{l}\t{%0, %0|%0, %0}
500 cmp{l}\t{%1, %0|%0, %1}"
501 [(set_attr "type" "test,icmp")
502 (set_attr "length_immediate" "0,1")
503 (set_attr "mode" "SI")])
505 (define_insn "*cmpsi_minus_1"
507 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
508 (match_operand:SI 1 "general_operand" "ri,mr"))
510 "ix86_match_ccmode (insn, CCGOCmode)"
511 "cmp{l}\t{%1, %0|%0, %1}"
512 [(set_attr "type" "icmp")
513 (set_attr "mode" "SI")])
515 (define_expand "cmpsi_1"
517 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
518 (match_operand:SI 1 "general_operand" "ri,mr")))]
522 (define_insn "*cmpsi_1_insn"
524 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
525 (match_operand:SI 1 "general_operand" "ri,mr")))]
526 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
527 && ix86_match_ccmode (insn, CCmode)"
528 "cmp{l}\t{%1, %0|%0, %1}"
529 [(set_attr "type" "icmp")
530 (set_attr "mode" "SI")])
532 (define_insn "*cmphi_ccno_1"
534 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
535 (match_operand:HI 1 "const0_operand" "n,n")))]
536 "ix86_match_ccmode (insn, CCNOmode)"
538 test{w}\t{%0, %0|%0, %0}
539 cmp{w}\t{%1, %0|%0, %1}"
540 [(set_attr "type" "test,icmp")
541 (set_attr "length_immediate" "0,1")
542 (set_attr "mode" "HI")])
544 (define_insn "*cmphi_minus_1"
546 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
547 (match_operand:HI 1 "general_operand" "ri,mr"))
549 "ix86_match_ccmode (insn, CCGOCmode)"
550 "cmp{w}\t{%1, %0|%0, %1}"
551 [(set_attr "type" "icmp")
552 (set_attr "mode" "HI")])
554 (define_insn "*cmphi_1"
556 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
557 (match_operand:HI 1 "general_operand" "ri,mr")))]
558 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
559 && ix86_match_ccmode (insn, CCmode)"
560 "cmp{w}\t{%1, %0|%0, %1}"
561 [(set_attr "type" "icmp")
562 (set_attr "mode" "HI")])
564 (define_insn "*cmpqi_ccno_1"
566 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
567 (match_operand:QI 1 "const0_operand" "n,n")))]
568 "ix86_match_ccmode (insn, CCNOmode)"
570 test{b}\t{%0, %0|%0, %0}
571 cmp{b}\t{$0, %0|%0, 0}"
572 [(set_attr "type" "test,icmp")
573 (set_attr "length_immediate" "0,1")
574 (set_attr "mode" "QI")])
576 (define_insn "*cmpqi_1"
578 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
579 (match_operand:QI 1 "general_operand" "qi,mq")))]
580 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
581 && ix86_match_ccmode (insn, CCmode)"
582 "cmp{b}\t{%1, %0|%0, %1}"
583 [(set_attr "type" "icmp")
584 (set_attr "mode" "QI")])
586 (define_insn "*cmpqi_minus_1"
588 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
589 (match_operand:QI 1 "general_operand" "qi,mq"))
591 "ix86_match_ccmode (insn, CCGOCmode)"
592 "cmp{b}\t{%1, %0|%0, %1}"
593 [(set_attr "type" "icmp")
594 (set_attr "mode" "QI")])
596 (define_insn "*cmpqi_ext_1"
599 (match_operand:QI 0 "general_operand" "Qm")
602 (match_operand 1 "ext_register_operand" "Q")
605 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
606 "cmp{b}\t{%h1, %0|%0, %h1}"
607 [(set_attr "type" "icmp")
608 (set_attr "mode" "QI")])
610 (define_insn "*cmpqi_ext_1_rex64"
613 (match_operand:QI 0 "register_operand" "Q")
616 (match_operand 1 "ext_register_operand" "Q")
619 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
620 "cmp{b}\t{%h1, %0|%0, %h1}"
621 [(set_attr "type" "icmp")
622 (set_attr "mode" "QI")])
624 (define_insn "*cmpqi_ext_2"
629 (match_operand 0 "ext_register_operand" "Q")
632 (match_operand:QI 1 "const0_operand" "n")))]
633 "ix86_match_ccmode (insn, CCNOmode)"
635 [(set_attr "type" "test")
636 (set_attr "length_immediate" "0")
637 (set_attr "mode" "QI")])
639 (define_expand "cmpqi_ext_3"
644 (match_operand 0 "ext_register_operand" "")
647 (match_operand:QI 1 "general_operand" "")))]
651 (define_insn "cmpqi_ext_3_insn"
656 (match_operand 0 "ext_register_operand" "Q")
659 (match_operand:QI 1 "general_operand" "Qmn")))]
660 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
661 "cmp{b}\t{%1, %h0|%h0, %1}"
662 [(set_attr "type" "icmp")
663 (set_attr "mode" "QI")])
665 (define_insn "cmpqi_ext_3_insn_rex64"
670 (match_operand 0 "ext_register_operand" "Q")
673 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
674 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
675 "cmp{b}\t{%1, %h0|%h0, %1}"
676 [(set_attr "type" "icmp")
677 (set_attr "mode" "QI")])
679 (define_insn "*cmpqi_ext_4"
684 (match_operand 0 "ext_register_operand" "Q")
689 (match_operand 1 "ext_register_operand" "Q")
692 "ix86_match_ccmode (insn, CCmode)"
693 "cmp{b}\t{%h1, %h0|%h0, %h1}"
694 [(set_attr "type" "icmp")
695 (set_attr "mode" "QI")])
697 ;; These implement float point compares.
698 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
699 ;; which would allow mix and match FP modes on the compares. Which is what
700 ;; the old patterns did, but with many more of them.
702 (define_expand "cmpxf"
704 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
705 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
706 "!TARGET_64BIT && TARGET_80387"
708 ix86_compare_op0 = operands[0];
709 ix86_compare_op1 = operands[1];
713 (define_expand "cmptf"
715 (compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "")
716 (match_operand:TF 1 "cmp_fp_expander_operand" "")))]
719 ix86_compare_op0 = operands[0];
720 ix86_compare_op1 = operands[1];
724 (define_expand "cmpdf"
726 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
727 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
728 "TARGET_80387 || TARGET_SSE2"
730 ix86_compare_op0 = operands[0];
731 ix86_compare_op1 = operands[1];
735 (define_expand "cmpsf"
737 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
738 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
739 "TARGET_80387 || TARGET_SSE"
741 ix86_compare_op0 = operands[0];
742 ix86_compare_op1 = operands[1];
746 ;; FP compares, step 1:
747 ;; Set the FP condition codes.
749 ;; CCFPmode compare with exceptions
750 ;; CCFPUmode compare with no exceptions
752 ;; %%% It is an unfortunate fact that ftst has no non-popping variant,
753 ;; and that fp moves clobber the condition codes, and that there is
754 ;; currently no way to describe this fact to reg-stack. So there are
755 ;; no splitters yet for this.
757 ;; %%% YIKES! This scheme does not retain a strong connection between
758 ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not
759 ;; work! Only allow tos/mem with tos in op 0.
761 ;; Hmm, of course, this is what the actual _hardware_ does. Perhaps
762 ;; things aren't as bad as they sound...
764 (define_insn "*cmpfp_0"
765 [(set (match_operand:HI 0 "register_operand" "=a")
767 [(compare:CCFP (match_operand 1 "register_operand" "f")
768 (match_operand 2 "const0_operand" "X"))]
771 && FLOAT_MODE_P (GET_MODE (operands[1]))
772 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
774 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
775 return "ftst\;fnstsw\t%0\;fstp\t%y0";
777 return "ftst\;fnstsw\t%0";
779 [(set_attr "type" "multi")
781 (cond [(match_operand:SF 1 "" "")
783 (match_operand:DF 1 "" "")
786 (const_string "XF")))])
788 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
789 ;; used to manage the reg stack popping would not be preserved.
791 (define_insn "*cmpfp_2_sf"
794 (match_operand:SF 0 "register_operand" "f")
795 (match_operand:SF 1 "nonimmediate_operand" "fm")))]
797 "* return output_fp_compare (insn, operands, 0, 0);"
798 [(set_attr "type" "fcmp")
799 (set_attr "mode" "SF")])
801 (define_insn "*cmpfp_2_sf_1"
802 [(set (match_operand:HI 0 "register_operand" "=a")
805 (match_operand:SF 1 "register_operand" "f")
806 (match_operand:SF 2 "nonimmediate_operand" "fm"))]
809 "* return output_fp_compare (insn, operands, 2, 0);"
810 [(set_attr "type" "fcmp")
811 (set_attr "mode" "SF")])
813 (define_insn "*cmpfp_2_df"
816 (match_operand:DF 0 "register_operand" "f")
817 (match_operand:DF 1 "nonimmediate_operand" "fm")))]
819 "* return output_fp_compare (insn, operands, 0, 0);"
820 [(set_attr "type" "fcmp")
821 (set_attr "mode" "DF")])
823 (define_insn "*cmpfp_2_df_1"
824 [(set (match_operand:HI 0 "register_operand" "=a")
827 (match_operand:DF 1 "register_operand" "f")
828 (match_operand:DF 2 "nonimmediate_operand" "fm"))]
831 "* return output_fp_compare (insn, operands, 2, 0);"
832 [(set_attr "type" "multi")
833 (set_attr "mode" "DF")])
835 (define_insn "*cmpfp_2_xf"
838 (match_operand:XF 0 "register_operand" "f")
839 (match_operand:XF 1 "register_operand" "f")))]
840 "!TARGET_64BIT && TARGET_80387"
841 "* return output_fp_compare (insn, operands, 0, 0);"
842 [(set_attr "type" "fcmp")
843 (set_attr "mode" "XF")])
845 (define_insn "*cmpfp_2_tf"
848 (match_operand:TF 0 "register_operand" "f")
849 (match_operand:TF 1 "register_operand" "f")))]
851 "* return output_fp_compare (insn, operands, 0, 0);"
852 [(set_attr "type" "fcmp")
853 (set_attr "mode" "XF")])
855 (define_insn "*cmpfp_2_xf_1"
856 [(set (match_operand:HI 0 "register_operand" "=a")
859 (match_operand:XF 1 "register_operand" "f")
860 (match_operand:XF 2 "register_operand" "f"))]
862 "!TARGET_64BIT && TARGET_80387"
863 "* return output_fp_compare (insn, operands, 2, 0);"
864 [(set_attr "type" "multi")
865 (set_attr "mode" "XF")])
867 (define_insn "*cmpfp_2_tf_1"
868 [(set (match_operand:HI 0 "register_operand" "=a")
871 (match_operand:TF 1 "register_operand" "f")
872 (match_operand:TF 2 "register_operand" "f"))]
875 "* return output_fp_compare (insn, operands, 2, 0);"
876 [(set_attr "type" "multi")
877 (set_attr "mode" "XF")])
879 (define_insn "*cmpfp_2u"
882 (match_operand 0 "register_operand" "f")
883 (match_operand 1 "register_operand" "f")))]
885 && FLOAT_MODE_P (GET_MODE (operands[0]))
886 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
887 "* return output_fp_compare (insn, operands, 0, 1);"
888 [(set_attr "type" "fcmp")
890 (cond [(match_operand:SF 1 "" "")
892 (match_operand:DF 1 "" "")
895 (const_string "XF")))])
897 (define_insn "*cmpfp_2u_1"
898 [(set (match_operand:HI 0 "register_operand" "=a")
901 (match_operand 1 "register_operand" "f")
902 (match_operand 2 "register_operand" "f"))]
905 && FLOAT_MODE_P (GET_MODE (operands[1]))
906 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
907 "* return output_fp_compare (insn, operands, 2, 1);"
908 [(set_attr "type" "multi")
910 (cond [(match_operand:SF 1 "" "")
912 (match_operand:DF 1 "" "")
915 (const_string "XF")))])
917 ;; Patterns to match the SImode-in-memory ficom instructions.
919 ;; %%% Play games with accepting gp registers, as otherwise we have to
920 ;; force them to memory during rtl generation, which is no good. We
921 ;; can get rid of this once we teach reload to do memory input reloads
924 (define_insn "*ficom_1"
927 (match_operand 0 "register_operand" "f,f")
928 (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))]
929 "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0]))
930 && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])"
933 ;; Split the not-really-implemented gp register case into a
934 ;; push-op-pop sequence.
936 ;; %%% This is most efficient, but am I gonna get in trouble
937 ;; for separating cc0_setter and cc0_user?
942 (match_operand:SF 0 "register_operand" "")
943 (float (match_operand:SI 1 "register_operand" ""))))]
944 "0 && TARGET_80387 && reload_completed"
945 [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
946 (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2)))
947 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
948 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
949 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
950 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
952 ;; FP compares, step 2
953 ;; Move the fpsw to ax.
955 (define_insn "*x86_fnstsw_1"
956 [(set (match_operand:HI 0 "register_operand" "=a")
957 (unspec:HI [(reg 18)] UNSPEC_FNSTSW))]
960 [(set_attr "length" "2")
961 (set_attr "mode" "SI")
962 (set_attr "unit" "i387")
963 (set_attr "ppro_uops" "few")])
965 ;; FP compares, step 3
966 ;; Get ax into flags, general case.
968 (define_insn "x86_sahf_1"
970 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
973 [(set_attr "length" "1")
974 (set_attr "athlon_decode" "vector")
975 (set_attr "mode" "SI")
976 (set_attr "ppro_uops" "one")])
978 ;; Pentium Pro can do steps 1 through 3 in one go.
980 (define_insn "*cmpfp_i"
982 (compare:CCFP (match_operand 0 "register_operand" "f")
983 (match_operand 1 "register_operand" "f")))]
984 "TARGET_80387 && TARGET_CMOVE
985 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
986 && FLOAT_MODE_P (GET_MODE (operands[0]))
987 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
988 "* return output_fp_compare (insn, operands, 1, 0);"
989 [(set_attr "type" "fcmp")
991 (cond [(match_operand:SF 1 "" "")
993 (match_operand:DF 1 "" "")
996 (const_string "XF")))
997 (set_attr "athlon_decode" "vector")])
999 (define_insn "*cmpfp_i_sse"
1001 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
1002 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1004 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1005 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1006 "* return output_fp_compare (insn, operands, 1, 0);"
1007 [(set_attr "type" "fcmp,ssecomi")
1009 (if_then_else (match_operand:SF 1 "" "")
1011 (const_string "DF")))
1012 (set_attr "athlon_decode" "vector")])
1014 (define_insn "*cmpfp_i_sse_only"
1016 (compare:CCFP (match_operand 0 "register_operand" "x")
1017 (match_operand 1 "nonimmediate_operand" "xm")))]
1018 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1019 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1020 "* return output_fp_compare (insn, operands, 1, 0);"
1021 [(set_attr "type" "ssecomi")
1023 (if_then_else (match_operand:SF 1 "" "")
1025 (const_string "DF")))
1026 (set_attr "athlon_decode" "vector")])
1028 (define_insn "*cmpfp_iu"
1029 [(set (reg:CCFPU 17)
1030 (compare:CCFPU (match_operand 0 "register_operand" "f")
1031 (match_operand 1 "register_operand" "f")))]
1032 "TARGET_80387 && TARGET_CMOVE
1033 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1034 && FLOAT_MODE_P (GET_MODE (operands[0]))
1035 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1036 "* return output_fp_compare (insn, operands, 1, 1);"
1037 [(set_attr "type" "fcmp")
1039 (cond [(match_operand:SF 1 "" "")
1041 (match_operand:DF 1 "" "")
1044 (const_string "XF")))
1045 (set_attr "athlon_decode" "vector")])
1047 (define_insn "*cmpfp_iu_sse"
1048 [(set (reg:CCFPU 17)
1049 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
1050 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1052 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1053 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1054 "* return output_fp_compare (insn, operands, 1, 1);"
1055 [(set_attr "type" "fcmp,ssecomi")
1057 (if_then_else (match_operand:SF 1 "" "")
1059 (const_string "DF")))
1060 (set_attr "athlon_decode" "vector")])
1062 (define_insn "*cmpfp_iu_sse_only"
1063 [(set (reg:CCFPU 17)
1064 (compare:CCFPU (match_operand 0 "register_operand" "x")
1065 (match_operand 1 "nonimmediate_operand" "xm")))]
1066 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1067 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1068 "* return output_fp_compare (insn, operands, 1, 1);"
1069 [(set_attr "type" "ssecomi")
1071 (if_then_else (match_operand:SF 1 "" "")
1073 (const_string "DF")))
1074 (set_attr "athlon_decode" "vector")])
1076 ;; Move instructions.
1078 ;; General case of fullword move.
1080 (define_expand "movsi"
1081 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1082 (match_operand:SI 1 "general_operand" ""))]
1084 "ix86_expand_move (SImode, operands); DONE;")
1086 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1089 ;; %%% We don't use a post-inc memory reference because x86 is not a
1090 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1091 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1092 ;; targets without our curiosities, and it is just as easy to represent
1093 ;; this differently.
1095 (define_insn "*pushsi2"
1096 [(set (match_operand:SI 0 "push_operand" "=<")
1097 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1100 [(set_attr "type" "push")
1101 (set_attr "mode" "SI")])
1103 ;; For 64BIT abi we always round up to 8 bytes.
1104 (define_insn "*pushsi2_rex64"
1105 [(set (match_operand:SI 0 "push_operand" "=X")
1106 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1109 [(set_attr "type" "push")
1110 (set_attr "mode" "SI")])
1112 (define_insn "*pushsi2_prologue"
1113 [(set (match_operand:SI 0 "push_operand" "=<")
1114 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1115 (clobber (mem:BLK (scratch)))]
1118 [(set_attr "type" "push")
1119 (set_attr "mode" "SI")])
1121 (define_insn "*popsi1_epilogue"
1122 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1123 (mem:SI (reg:SI 7)))
1125 (plus:SI (reg:SI 7) (const_int 4)))
1126 (clobber (mem:BLK (scratch)))]
1129 [(set_attr "type" "pop")
1130 (set_attr "mode" "SI")])
1132 (define_insn "popsi1"
1133 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1134 (mem:SI (reg:SI 7)))
1136 (plus:SI (reg:SI 7) (const_int 4)))]
1139 [(set_attr "type" "pop")
1140 (set_attr "mode" "SI")])
1142 (define_insn "*movsi_xor"
1143 [(set (match_operand:SI 0 "register_operand" "=r")
1144 (match_operand:SI 1 "const0_operand" "i"))
1145 (clobber (reg:CC 17))]
1146 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1147 "xor{l}\t{%0, %0|%0, %0}"
1148 [(set_attr "type" "alu1")
1149 (set_attr "mode" "SI")
1150 (set_attr "length_immediate" "0")])
1152 (define_insn "*movsi_or"
1153 [(set (match_operand:SI 0 "register_operand" "=r")
1154 (match_operand:SI 1 "immediate_operand" "i"))
1155 (clobber (reg:CC 17))]
1156 "reload_completed && GET_CODE (operands[1]) == CONST_INT
1157 && INTVAL (operands[1]) == -1
1158 && (TARGET_PENTIUM || optimize_size)"
1160 operands[1] = constm1_rtx;
1161 return "or{l}\t{%1, %0|%0, %1}";
1163 [(set_attr "type" "alu1")
1164 (set_attr "mode" "SI")
1165 (set_attr "length_immediate" "1")])
1167 (define_insn "*movsi_1"
1168 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
1169 (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,rm,*Y,*Y,rm"))]
1170 "(TARGET_INTER_UNIT_MOVES || optimize_size)
1171 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1173 switch (get_attr_type (insn))
1176 if (get_attr_mode (insn) == MODE_TI)
1177 return "movdqa\t{%1, %0|%0, %1}";
1178 return "movd\t{%1, %0|%0, %1}";
1181 if (get_attr_mode (insn) == MODE_DI)
1182 return "movq\t{%1, %0|%0, %1}";
1183 return "movd\t{%1, %0|%0, %1}";
1186 return "lea{l}\t{%1, %0|%0, %1}";
1189 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1191 return "mov{l}\t{%1, %0|%0, %1}";
1195 (cond [(eq_attr "alternative" "2,3,4")
1196 (const_string "mmxmov")
1197 (eq_attr "alternative" "5,6,7")
1198 (const_string "ssemov")
1199 (and (ne (symbol_ref "flag_pic") (const_int 0))
1200 (match_operand:SI 1 "symbolic_operand" ""))
1201 (const_string "lea")
1203 (const_string "imov")))
1204 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1206 (define_insn "*movsi_1_nointernunit"
1207 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!m,!*y,!*Y,!m,!*Y")
1208 (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,m,*Y,*Y,m"))]
1209 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
1210 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1212 switch (get_attr_type (insn))
1215 if (get_attr_mode (insn) == MODE_TI)
1216 return "movdqa\t{%1, %0|%0, %1}";
1217 return "movd\t{%1, %0|%0, %1}";
1220 if (get_attr_mode (insn) == MODE_DI)
1221 return "movq\t{%1, %0|%0, %1}";
1222 return "movd\t{%1, %0|%0, %1}";
1225 return "lea{l}\t{%1, %0|%0, %1}";
1228 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1230 return "mov{l}\t{%1, %0|%0, %1}";
1234 (cond [(eq_attr "alternative" "2,3,4")
1235 (const_string "mmxmov")
1236 (eq_attr "alternative" "5,6,7")
1237 (const_string "ssemov")
1238 (and (ne (symbol_ref "flag_pic") (const_int 0))
1239 (match_operand:SI 1 "symbolic_operand" ""))
1240 (const_string "lea")
1242 (const_string "imov")))
1243 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1245 ;; Stores and loads of ax to arbitrary constant address.
1246 ;; We fake an second form of instruction to force reload to load address
1247 ;; into register when rax is not available
1248 (define_insn "*movabssi_1_rex64"
1249 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1250 (match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
1253 movabs{l}\t{%1, %P0|%P0, %1}
1254 mov{l}\t{%1, %a0|%a0, %1}
1255 movabs{l}\t{%1, %a0|%a0, %1}"
1256 [(set_attr "type" "imov")
1257 (set_attr "modrm" "0,*,*")
1258 (set_attr "length_address" "8,0,0")
1259 (set_attr "length_immediate" "0,*,*")
1260 (set_attr "memory" "store")
1261 (set_attr "mode" "SI")])
1263 (define_insn "*movabssi_2_rex64"
1264 [(set (match_operand:SI 0 "register_operand" "=a,r")
1265 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1268 movabs{l}\t{%P1, %0|%0, %P1}
1269 mov{l}\t{%a1, %0|%0, %a1}"
1270 [(set_attr "type" "imov")
1271 (set_attr "modrm" "0,*")
1272 (set_attr "length_address" "8,0")
1273 (set_attr "length_immediate" "0")
1274 (set_attr "memory" "load")
1275 (set_attr "mode" "SI")])
1277 (define_insn "*swapsi"
1278 [(set (match_operand:SI 0 "register_operand" "+r")
1279 (match_operand:SI 1 "register_operand" "+r"))
1284 [(set_attr "type" "imov")
1285 (set_attr "pent_pair" "np")
1286 (set_attr "athlon_decode" "vector")
1287 (set_attr "mode" "SI")
1288 (set_attr "modrm" "0")
1289 (set_attr "ppro_uops" "few")])
1291 (define_expand "movhi"
1292 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1293 (match_operand:HI 1 "general_operand" ""))]
1295 "ix86_expand_move (HImode, operands); DONE;")
1297 (define_insn "*pushhi2"
1298 [(set (match_operand:HI 0 "push_operand" "=<,<")
1299 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1302 push{w}\t{|WORD PTR }%1
1304 [(set_attr "type" "push")
1305 (set_attr "mode" "HI")])
1307 ;; For 64BIT abi we always round up to 8 bytes.
1308 (define_insn "*pushhi2_rex64"
1309 [(set (match_operand:HI 0 "push_operand" "=X")
1310 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1313 [(set_attr "type" "push")
1314 (set_attr "mode" "QI")])
1316 (define_insn "*movhi_1"
1317 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
1318 (match_operand:HI 1 "general_operand" "r,rn,rm,rn"))]
1319 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1321 switch (get_attr_type (insn))
1324 /* movzwl is faster than movw on p2 due to partial word stalls,
1325 though not as fast as an aligned movl. */
1326 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
1328 if (get_attr_mode (insn) == MODE_SI)
1329 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1331 return "mov{w}\t{%1, %0|%0, %1}";
1335 (cond [(and (eq_attr "alternative" "0")
1336 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1338 (eq (symbol_ref "TARGET_HIMODE_MATH")
1340 (const_string "imov")
1341 (and (eq_attr "alternative" "1,2")
1342 (match_operand:HI 1 "aligned_operand" ""))
1343 (const_string "imov")
1344 (and (ne (symbol_ref "TARGET_MOVX")
1346 (eq_attr "alternative" "0,2"))
1347 (const_string "imovx")
1349 (const_string "imov")))
1351 (cond [(eq_attr "type" "imovx")
1353 (and (eq_attr "alternative" "1,2")
1354 (match_operand:HI 1 "aligned_operand" ""))
1356 (and (eq_attr "alternative" "0")
1357 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1359 (eq (symbol_ref "TARGET_HIMODE_MATH")
1363 (const_string "HI")))])
1365 ;; Stores and loads of ax to arbitrary constant address.
1366 ;; We fake an second form of instruction to force reload to load address
1367 ;; into register when rax is not available
1368 (define_insn "*movabshi_1_rex64"
1369 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1370 (match_operand:HI 1 "nonmemory_operand" "a,er,i"))]
1373 movabs{w}\t{%1, %P0|%P0, %1}
1374 mov{w}\t{%1, %a0|%a0, %1}
1375 movabs{w}\t{%1, %a0|%a0, %1}"
1376 [(set_attr "type" "imov")
1377 (set_attr "modrm" "0,*,*")
1378 (set_attr "length_address" "8,0,0")
1379 (set_attr "length_immediate" "0,*,*")
1380 (set_attr "memory" "store")
1381 (set_attr "mode" "HI")])
1383 (define_insn "*movabshi_2_rex64"
1384 [(set (match_operand:HI 0 "register_operand" "=a,r")
1385 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1388 movabs{w}\t{%P1, %0|%0, %P1}
1389 mov{w}\t{%a1, %0|%0, %a1}"
1390 [(set_attr "type" "imov")
1391 (set_attr "modrm" "0,*")
1392 (set_attr "length_address" "8,0")
1393 (set_attr "length_immediate" "0")
1394 (set_attr "memory" "load")
1395 (set_attr "mode" "HI")])
1397 (define_insn "*swaphi_1"
1398 [(set (match_operand:HI 0 "register_operand" "+r")
1399 (match_operand:HI 1 "register_operand" "+r"))
1402 "TARGET_PARTIAL_REG_STALL"
1404 [(set_attr "type" "imov")
1405 (set_attr "pent_pair" "np")
1406 (set_attr "mode" "HI")
1407 (set_attr "modrm" "0")
1408 (set_attr "ppro_uops" "few")])
1410 (define_insn "*swaphi_2"
1411 [(set (match_operand:HI 0 "register_operand" "+r")
1412 (match_operand:HI 1 "register_operand" "+r"))
1415 "! TARGET_PARTIAL_REG_STALL"
1417 [(set_attr "type" "imov")
1418 (set_attr "pent_pair" "np")
1419 (set_attr "mode" "SI")
1420 (set_attr "modrm" "0")
1421 (set_attr "ppro_uops" "few")])
1423 (define_expand "movstricthi"
1424 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1425 (match_operand:HI 1 "general_operand" ""))]
1426 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1428 /* Don't generate memory->memory moves, go through a register */
1429 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1430 operands[1] = force_reg (HImode, operands[1]);
1433 (define_insn "*movstricthi_1"
1434 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1435 (match_operand:HI 1 "general_operand" "rn,m"))]
1436 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1437 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1438 "mov{w}\t{%1, %0|%0, %1}"
1439 [(set_attr "type" "imov")
1440 (set_attr "mode" "HI")])
1442 (define_insn "*movstricthi_xor"
1443 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1444 (match_operand:HI 1 "const0_operand" "i"))
1445 (clobber (reg:CC 17))]
1447 && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
1448 "xor{w}\t{%0, %0|%0, %0}"
1449 [(set_attr "type" "alu1")
1450 (set_attr "mode" "HI")
1451 (set_attr "length_immediate" "0")])
1453 (define_expand "movqi"
1454 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1455 (match_operand:QI 1 "general_operand" ""))]
1457 "ix86_expand_move (QImode, operands); DONE;")
1459 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1460 ;; "push a byte". But actually we use pushw, which has the effect
1461 ;; of rounding the amount pushed up to a halfword.
1463 (define_insn "*pushqi2"
1464 [(set (match_operand:QI 0 "push_operand" "=X,X")
1465 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1468 push{w}\t{|word ptr }%1
1470 [(set_attr "type" "push")
1471 (set_attr "mode" "HI")])
1473 ;; For 64BIT abi we always round up to 8 bytes.
1474 (define_insn "*pushqi2_rex64"
1475 [(set (match_operand:QI 0 "push_operand" "=X")
1476 (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
1479 [(set_attr "type" "push")
1480 (set_attr "mode" "QI")])
1482 ;; Situation is quite tricky about when to choose full sized (SImode) move
1483 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
1484 ;; partial register dependency machines (such as AMD Athlon), where QImode
1485 ;; moves issue extra dependency and for partial register stalls machines
1486 ;; that don't use QImode patterns (and QImode move cause stall on the next
1489 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
1490 ;; register stall machines with, where we use QImode instructions, since
1491 ;; partial register stall can be caused there. Then we use movzx.
1492 (define_insn "*movqi_1"
1493 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
1494 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
1495 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1497 switch (get_attr_type (insn))
1500 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
1502 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
1504 if (get_attr_mode (insn) == MODE_SI)
1505 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1507 return "mov{b}\t{%1, %0|%0, %1}";
1511 (cond [(and (eq_attr "alternative" "3")
1512 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1514 (eq (symbol_ref "TARGET_QIMODE_MATH")
1516 (const_string "imov")
1517 (eq_attr "alternative" "3,5")
1518 (const_string "imovx")
1519 (and (ne (symbol_ref "TARGET_MOVX")
1521 (eq_attr "alternative" "2"))
1522 (const_string "imovx")
1524 (const_string "imov")))
1526 (cond [(eq_attr "alternative" "3,4,5")
1528 (eq_attr "alternative" "6")
1530 (eq_attr "type" "imovx")
1532 (and (eq_attr "type" "imov")
1533 (and (eq_attr "alternative" "0,1,2")
1534 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
1537 ;; Avoid partial register stalls when not using QImode arithmetic
1538 (and (eq_attr "type" "imov")
1539 (and (eq_attr "alternative" "0,1,2")
1540 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
1542 (eq (symbol_ref "TARGET_QIMODE_MATH")
1546 (const_string "QI")))])
1548 (define_expand "reload_outqi"
1549 [(parallel [(match_operand:QI 0 "" "=m")
1550 (match_operand:QI 1 "register_operand" "r")
1551 (match_operand:QI 2 "register_operand" "=&q")])]
1555 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
1557 if (reg_overlap_mentioned_p (op2, op0))
1559 if (! q_regs_operand (op1, QImode))
1561 emit_insn (gen_movqi (op2, op1));
1564 emit_insn (gen_movqi (op0, op1));
1568 (define_insn "*swapqi"
1569 [(set (match_operand:QI 0 "register_operand" "+r")
1570 (match_operand:QI 1 "register_operand" "+r"))
1575 [(set_attr "type" "imov")
1576 (set_attr "pent_pair" "np")
1577 (set_attr "mode" "QI")
1578 (set_attr "modrm" "0")
1579 (set_attr "ppro_uops" "few")])
1581 (define_expand "movstrictqi"
1582 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1583 (match_operand:QI 1 "general_operand" ""))]
1584 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1586 /* Don't generate memory->memory moves, go through a register. */
1587 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1588 operands[1] = force_reg (QImode, operands[1]);
1591 (define_insn "*movstrictqi_1"
1592 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
1593 (match_operand:QI 1 "general_operand" "*qn,m"))]
1594 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1595 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1596 "mov{b}\t{%1, %0|%0, %1}"
1597 [(set_attr "type" "imov")
1598 (set_attr "mode" "QI")])
1600 (define_insn "*movstrictqi_xor"
1601 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
1602 (match_operand:QI 1 "const0_operand" "i"))
1603 (clobber (reg:CC 17))]
1604 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1605 "xor{b}\t{%0, %0|%0, %0}"
1606 [(set_attr "type" "alu1")
1607 (set_attr "mode" "QI")
1608 (set_attr "length_immediate" "0")])
1610 (define_insn "*movsi_extv_1"
1611 [(set (match_operand:SI 0 "register_operand" "=R")
1612 (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
1616 "movs{bl|x}\t{%h1, %0|%0, %h1}"
1617 [(set_attr "type" "imovx")
1618 (set_attr "mode" "SI")])
1620 (define_insn "*movhi_extv_1"
1621 [(set (match_operand:HI 0 "register_operand" "=R")
1622 (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
1626 "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
1627 [(set_attr "type" "imovx")
1628 (set_attr "mode" "SI")])
1630 (define_insn "*movqi_extv_1"
1631 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
1632 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1637 switch (get_attr_type (insn))
1640 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1642 return "mov{b}\t{%h1, %0|%0, %h1}";
1646 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1647 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1648 (ne (symbol_ref "TARGET_MOVX")
1650 (const_string "imovx")
1651 (const_string "imov")))
1653 (if_then_else (eq_attr "type" "imovx")
1655 (const_string "QI")))])
1657 (define_insn "*movqi_extv_1_rex64"
1658 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1659 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1664 switch (get_attr_type (insn))
1667 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1669 return "mov{b}\t{%h1, %0|%0, %h1}";
1673 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1674 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1675 (ne (symbol_ref "TARGET_MOVX")
1677 (const_string "imovx")
1678 (const_string "imov")))
1680 (if_then_else (eq_attr "type" "imovx")
1682 (const_string "QI")))])
1684 ;; Stores and loads of ax to arbitrary constant address.
1685 ;; We fake an second form of instruction to force reload to load address
1686 ;; into register when rax is not available
1687 (define_insn "*movabsqi_1_rex64"
1688 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1689 (match_operand:QI 1 "nonmemory_operand" "a,er,i"))]
1692 movabs{b}\t{%1, %P0|%P0, %1}
1693 mov{b}\t{%1, %a0|%a0, %1}
1694 movabs{b}\t{%1, %a0|%a0, %1}"
1695 [(set_attr "type" "imov")
1696 (set_attr "modrm" "0,*,*")
1697 (set_attr "length_address" "8,0,0")
1698 (set_attr "length_immediate" "0,*,*")
1699 (set_attr "memory" "store")
1700 (set_attr "mode" "QI")])
1702 (define_insn "*movabsqi_2_rex64"
1703 [(set (match_operand:QI 0 "register_operand" "=a,r")
1704 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1707 movabs{b}\t{%P1, %0|%0, %P1}
1708 mov{b}\t{%a1, %0|%0, %a1}"
1709 [(set_attr "type" "imov")
1710 (set_attr "modrm" "0,*")
1711 (set_attr "length_address" "8,0")
1712 (set_attr "length_immediate" "0")
1713 (set_attr "memory" "load")
1714 (set_attr "mode" "QI")])
1716 (define_insn "*movsi_extzv_1"
1717 [(set (match_operand:SI 0 "register_operand" "=R")
1718 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
1722 "movz{bl|x}\t{%h1, %0|%0, %h1}"
1723 [(set_attr "type" "imovx")
1724 (set_attr "mode" "SI")])
1726 (define_insn "*movqi_extzv_2"
1727 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
1728 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1733 switch (get_attr_type (insn))
1736 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1738 return "mov{b}\t{%h1, %0|%0, %h1}";
1742 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1743 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1744 (ne (symbol_ref "TARGET_MOVX")
1746 (const_string "imovx")
1747 (const_string "imov")))
1749 (if_then_else (eq_attr "type" "imovx")
1751 (const_string "QI")))])
1753 (define_insn "*movqi_extzv_2_rex64"
1754 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1755 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1760 switch (get_attr_type (insn))
1763 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1765 return "mov{b}\t{%h1, %0|%0, %h1}";
1769 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1770 (ne (symbol_ref "TARGET_MOVX")
1772 (const_string "imovx")
1773 (const_string "imov")))
1775 (if_then_else (eq_attr "type" "imovx")
1777 (const_string "QI")))])
1779 (define_insn "movsi_insv_1"
1780 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1783 (match_operand:SI 1 "general_operand" "Qmn"))]
1785 "mov{b}\t{%b1, %h0|%h0, %b1}"
1786 [(set_attr "type" "imov")
1787 (set_attr "mode" "QI")])
1789 (define_insn "*movsi_insv_1_rex64"
1790 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1793 (match_operand:SI 1 "nonmemory_operand" "Qn"))]
1795 "mov{b}\t{%b1, %h0|%h0, %b1}"
1796 [(set_attr "type" "imov")
1797 (set_attr "mode" "QI")])
1799 (define_insn "*movqi_insv_2"
1800 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1803 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
1807 "mov{b}\t{%h1, %h0|%h0, %h1}"
1808 [(set_attr "type" "imov")
1809 (set_attr "mode" "QI")])
1811 (define_expand "movdi"
1812 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1813 (match_operand:DI 1 "general_operand" ""))]
1815 "ix86_expand_move (DImode, operands); DONE;")
1817 (define_insn "*pushdi"
1818 [(set (match_operand:DI 0 "push_operand" "=<")
1819 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
1823 (define_insn "pushdi2_rex64"
1824 [(set (match_operand:DI 0 "push_operand" "=<,!<")
1825 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
1830 [(set_attr "type" "push,multi")
1831 (set_attr "mode" "DI")])
1833 ;; Convert impossible pushes of immediate to existing instructions.
1834 ;; First try to get scratch register and go through it. In case this
1835 ;; fails, push sign extended lower part first and then overwrite
1836 ;; upper part by 32bit move.
1838 [(match_scratch:DI 2 "r")
1839 (set (match_operand:DI 0 "push_operand" "")
1840 (match_operand:DI 1 "immediate_operand" ""))]
1841 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1842 && !x86_64_immediate_operand (operands[1], DImode)"
1843 [(set (match_dup 2) (match_dup 1))
1844 (set (match_dup 0) (match_dup 2))]
1847 ;; We need to define this as both peepholer and splitter for case
1848 ;; peephole2 pass is not run.
1850 [(set (match_operand:DI 0 "push_operand" "")
1851 (match_operand:DI 1 "immediate_operand" ""))]
1852 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1853 && !x86_64_immediate_operand (operands[1], DImode) && 1"
1854 [(set (match_dup 0) (match_dup 1))
1855 (set (match_dup 2) (match_dup 3))]
1856 "split_di (operands + 1, 1, operands + 2, operands + 3);
1857 operands[1] = gen_lowpart (DImode, operands[2]);
1858 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1863 [(set (match_operand:DI 0 "push_operand" "")
1864 (match_operand:DI 1 "immediate_operand" ""))]
1865 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
1866 && !symbolic_operand (operands[1], DImode)
1867 && !x86_64_immediate_operand (operands[1], DImode)"
1868 [(set (match_dup 0) (match_dup 1))
1869 (set (match_dup 2) (match_dup 3))]
1870 "split_di (operands + 1, 1, operands + 2, operands + 3);
1871 operands[1] = gen_lowpart (DImode, operands[2]);
1872 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1876 (define_insn "*pushdi2_prologue_rex64"
1877 [(set (match_operand:DI 0 "push_operand" "=<")
1878 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
1879 (clobber (mem:BLK (scratch)))]
1882 [(set_attr "type" "push")
1883 (set_attr "mode" "DI")])
1885 (define_insn "*popdi1_epilogue_rex64"
1886 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1887 (mem:DI (reg:DI 7)))
1889 (plus:DI (reg:DI 7) (const_int 8)))
1890 (clobber (mem:BLK (scratch)))]
1893 [(set_attr "type" "pop")
1894 (set_attr "mode" "DI")])
1896 (define_insn "popdi1"
1897 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1898 (mem:DI (reg:DI 7)))
1900 (plus:DI (reg:DI 7) (const_int 8)))]
1903 [(set_attr "type" "pop")
1904 (set_attr "mode" "DI")])
1906 (define_insn "*movdi_xor_rex64"
1907 [(set (match_operand:DI 0 "register_operand" "=r")
1908 (match_operand:DI 1 "const0_operand" "i"))
1909 (clobber (reg:CC 17))]
1910 "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
1911 && reload_completed"
1912 "xor{l}\t{%k0, %k0|%k0, %k0}"
1913 [(set_attr "type" "alu1")
1914 (set_attr "mode" "SI")
1915 (set_attr "length_immediate" "0")])
1917 (define_insn "*movdi_or_rex64"
1918 [(set (match_operand:DI 0 "register_operand" "=r")
1919 (match_operand:DI 1 "const_int_operand" "i"))
1920 (clobber (reg:CC 17))]
1921 "TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
1923 && GET_CODE (operands[1]) == CONST_INT
1924 && INTVAL (operands[1]) == -1"
1926 operands[1] = constm1_rtx;
1927 return "or{q}\t{%1, %0|%0, %1}";
1929 [(set_attr "type" "alu1")
1930 (set_attr "mode" "DI")
1931 (set_attr "length_immediate" "1")])
1933 (define_insn "*movdi_2"
1934 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*Y,!*Y")
1935 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
1937 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1941 movq\t{%1, %0|%0, %1}
1942 movq\t{%1, %0|%0, %1}
1943 movq\t{%1, %0|%0, %1}
1944 movdqa\t{%1, %0|%0, %1}
1945 movq\t{%1, %0|%0, %1}"
1946 [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov")
1947 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
1950 [(set (match_operand:DI 0 "push_operand" "")
1951 (match_operand:DI 1 "general_operand" ""))]
1952 "!TARGET_64BIT && reload_completed
1953 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1955 "ix86_split_long_move (operands); DONE;")
1957 ;; %%% This multiword shite has got to go.
1959 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1960 (match_operand:DI 1 "general_operand" ""))]
1961 "!TARGET_64BIT && reload_completed
1962 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
1963 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1965 "ix86_split_long_move (operands); DONE;")
1967 (define_insn "*movdi_1_rex64"
1968 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!rm,!*y,!*Y,!rm,!*Y")
1969 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,rm,*Y,*Y,rm"))]
1971 && (TARGET_INTER_UNIT_MOVES || optimize_size)
1972 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1974 switch (get_attr_type (insn))
1977 if (get_attr_mode (insn) == MODE_TI)
1978 return "movdqa\t{%1, %0|%0, %1}";
1981 /* Moves from and into integer register is done using movd opcode with
1983 if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
1984 return "movd\t{%1, %0|%0, %1}";
1985 return "movq\t{%1, %0|%0, %1}";
1989 return "lea{q}\t{%a1, %0|%0, %a1}";
1991 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1993 if (get_attr_mode (insn) == MODE_SI)
1994 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1995 else if (which_alternative == 2)
1996 return "movabs{q}\t{%1, %0|%0, %1}";
1998 return "mov{q}\t{%1, %0|%0, %1}";
2002 (cond [(eq_attr "alternative" "5,6,7")
2003 (const_string "mmxmov")
2004 (eq_attr "alternative" "8,9,10")
2005 (const_string "ssemov")
2006 (eq_attr "alternative" "4")
2007 (const_string "multi")
2008 (and (ne (symbol_ref "flag_pic") (const_int 0))
2009 (match_operand:DI 1 "symbolic_operand" ""))
2010 (const_string "lea")
2012 (const_string "imov")))
2013 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*")
2014 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*")
2015 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI")])
2017 (define_insn "*movdi_1_rex64_nointerunit"
2018 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!m,!*y,!*Y,!m,!*Y")
2019 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,m,*Y,*Y,m"))]
2021 && (!TARGET_INTER_UNIT_MOVES && !optimize_size)
2022 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2024 switch (get_attr_type (insn))
2027 if (get_attr_mode (insn) == MODE_TI)
2028 return "movdqa\t{%1, %0|%0, %1}";
2031 return "movq\t{%1, %0|%0, %1}";
2035 return "lea{q}\t{%a1, %0|%0, %a1}";
2037 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
2039 if (get_attr_mode (insn) == MODE_SI)
2040 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2041 else if (which_alternative == 2)
2042 return "movabs{q}\t{%1, %0|%0, %1}";
2044 return "mov{q}\t{%1, %0|%0, %1}";
2048 (cond [(eq_attr "alternative" "5,6,7")
2049 (const_string "mmxmov")
2050 (eq_attr "alternative" "8,9,10")
2051 (const_string "ssemov")
2052 (eq_attr "alternative" "4")
2053 (const_string "multi")
2054 (and (ne (symbol_ref "flag_pic") (const_int 0))
2055 (match_operand:DI 1 "symbolic_operand" ""))
2056 (const_string "lea")
2058 (const_string "imov")))
2059 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*")
2060 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*")
2061 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI")])
2063 ;; Stores and loads of ax to arbitrary constant address.
2064 ;; We fake an second form of instruction to force reload to load address
2065 ;; into register when rax is not available
2066 (define_insn "*movabsdi_1_rex64"
2067 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
2068 (match_operand:DI 1 "nonmemory_operand" "a,er,i"))]
2071 movabs{q}\t{%1, %P0|%P0, %1}
2072 mov{q}\t{%1, %a0|%a0, %1}
2073 movabs{q}\t{%1, %a0|%a0, %1}"
2074 [(set_attr "type" "imov")
2075 (set_attr "modrm" "0,*,*")
2076 (set_attr "length_address" "8,0,0")
2077 (set_attr "length_immediate" "0,*,*")
2078 (set_attr "memory" "store")
2079 (set_attr "mode" "DI")])
2081 (define_insn "*movabsdi_2_rex64"
2082 [(set (match_operand:DI 0 "register_operand" "=a,r")
2083 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2086 movabs{q}\t{%P1, %0|%0, %P1}
2087 mov{q}\t{%a1, %0|%0, %a1}"
2088 [(set_attr "type" "imov")
2089 (set_attr "modrm" "0,*")
2090 (set_attr "length_address" "8,0")
2091 (set_attr "length_immediate" "0")
2092 (set_attr "memory" "load")
2093 (set_attr "mode" "DI")])
2095 ;; Convert impossible stores of immediate to existing instructions.
2096 ;; First try to get scratch register and go through it. In case this
2097 ;; fails, move by 32bit parts.
2099 [(match_scratch:DI 2 "r")
2100 (set (match_operand:DI 0 "memory_operand" "")
2101 (match_operand:DI 1 "immediate_operand" ""))]
2102 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2103 && !x86_64_immediate_operand (operands[1], DImode)"
2104 [(set (match_dup 2) (match_dup 1))
2105 (set (match_dup 0) (match_dup 2))]
2108 ;; We need to define this as both peepholer and splitter for case
2109 ;; peephole2 pass is not run.
2111 [(set (match_operand:DI 0 "memory_operand" "")
2112 (match_operand:DI 1 "immediate_operand" ""))]
2113 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2114 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2115 [(set (match_dup 2) (match_dup 3))
2116 (set (match_dup 4) (match_dup 5))]
2117 "split_di (operands, 2, operands + 2, operands + 4);")
2120 [(set (match_operand:DI 0 "memory_operand" "")
2121 (match_operand:DI 1 "immediate_operand" ""))]
2122 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2123 && !symbolic_operand (operands[1], DImode)
2124 && !x86_64_immediate_operand (operands[1], DImode)"
2125 [(set (match_dup 2) (match_dup 3))
2126 (set (match_dup 4) (match_dup 5))]
2127 "split_di (operands, 2, operands + 2, operands + 4);")
2129 (define_insn "*swapdi_rex64"
2130 [(set (match_operand:DI 0 "register_operand" "+r")
2131 (match_operand:DI 1 "register_operand" "+r"))
2136 [(set_attr "type" "imov")
2137 (set_attr "pent_pair" "np")
2138 (set_attr "athlon_decode" "vector")
2139 (set_attr "mode" "DI")
2140 (set_attr "modrm" "0")
2141 (set_attr "ppro_uops" "few")])
2144 (define_expand "movsf"
2145 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2146 (match_operand:SF 1 "general_operand" ""))]
2148 "ix86_expand_move (SFmode, operands); DONE;")
2150 (define_insn "*pushsf"
2151 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2152 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2155 switch (which_alternative)
2158 return "push{l}\t%1";
2161 /* This insn should be already splitted before reg-stack. */
2165 [(set_attr "type" "multi,push,multi")
2166 (set_attr "mode" "SF,SI,SF")])
2168 (define_insn "*pushsf_rex64"
2169 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2170 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2173 switch (which_alternative)
2176 return "push{q}\t%q1";
2179 /* This insn should be already splitted before reg-stack. */
2183 [(set_attr "type" "multi,push,multi")
2184 (set_attr "mode" "SF,DI,SF")])
2187 [(set (match_operand:SF 0 "push_operand" "")
2188 (match_operand:SF 1 "memory_operand" ""))]
2190 && GET_CODE (operands[1]) == MEM
2191 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2192 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2195 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2198 ;; %%% Kill this when call knows how to work this out.
2200 [(set (match_operand:SF 0 "push_operand" "")
2201 (match_operand:SF 1 "any_fp_register_operand" ""))]
2203 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
2204 (set (mem:SF (reg:SI 7)) (match_dup 1))])
2207 [(set (match_operand:SF 0 "push_operand" "")
2208 (match_operand:SF 1 "any_fp_register_operand" ""))]
2210 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2211 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2213 (define_insn "*movsf_1"
2214 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y")
2215 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,rm,*y,*y"))]
2216 "(TARGET_INTER_UNIT_MOVES || optimize_size)
2217 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2218 && (reload_in_progress || reload_completed
2219 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2220 || GET_CODE (operands[1]) != CONST_DOUBLE
2221 || memory_operand (operands[0], SFmode))"
2223 switch (which_alternative)
2226 if (REG_P (operands[1])
2227 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2229 else if (STACK_TOP_P (operands[0]))
2230 return "fld%z1\t%y1";
2235 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2236 return "fstp%z0\t%y0";
2238 return "fst%z0\t%y0";
2241 return standard_80387_constant_opcode (operands[1]);
2245 return "mov{l}\t{%1, %0|%0, %1}";
2247 if (get_attr_mode (insn) == MODE_TI)
2248 return "pxor\t%0, %0";
2250 return "xorps\t%0, %0";
2252 if (get_attr_mode (insn) == MODE_V4SF)
2253 return "movaps\t{%1, %0|%0, %1}";
2255 return "movss\t{%1, %0|%0, %1}";
2258 return "movss\t{%1, %0|%0, %1}";
2262 return "movd\t{%1, %0|%0, %1}";
2265 return "movq\t{%1, %0|%0, %1}";
2271 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2273 (cond [(eq_attr "alternative" "3,4,9,10")
2275 (eq_attr "alternative" "5")
2277 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2279 (ne (symbol_ref "TARGET_SSE2")
2281 (eq (symbol_ref "optimize_size")
2284 (const_string "V4SF"))
2285 /* For architectures resolving dependencies on
2286 whole SSE registers use APS move to break dependency
2287 chains, otherwise use short move to avoid extra work.
2289 Do the same for architectures resolving dependencies on
2290 the parts. While in DF mode it is better to always handle
2291 just register parts, the SF mode is different due to lack
2292 of instructions to load just part of the register. It is
2293 better to maintain the whole registers in single format
2294 to avoid problems on using packed logical operations. */
2295 (eq_attr "alternative" "6")
2297 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2299 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2301 (const_string "V4SF")
2302 (const_string "SF"))
2303 (eq_attr "alternative" "11")
2304 (const_string "DI")]
2305 (const_string "SF")))])
2307 (define_insn "*movsf_1_nointerunit"
2308 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!m,!*y")
2309 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,m,*y,*y"))]
2310 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
2311 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2312 && (reload_in_progress || reload_completed
2313 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2314 || GET_CODE (operands[1]) != CONST_DOUBLE
2315 || memory_operand (operands[0], SFmode))"
2317 switch (which_alternative)
2320 if (REG_P (operands[1])
2321 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2323 if (REGNO (operands[0]) == FIRST_STACK_REG
2324 && TARGET_USE_FFREEP)
2325 return "ffreep\t%y0";
2328 else if (STACK_TOP_P (operands[0]))
2329 return "fld%z1\t%y1";
2334 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2335 return "fstp%z0\t%y0";
2337 return "fst%z0\t%y0";
2340 return standard_80387_constant_opcode (operands[1]);
2344 return "mov{l}\t{%1, %0|%0, %1}";
2346 if (get_attr_mode (insn) == MODE_TI)
2347 return "pxor\t%0, %0";
2349 return "xorps\t%0, %0";
2351 if (get_attr_mode (insn) == MODE_V4SF)
2352 return "movaps\t{%1, %0|%0, %1}";
2354 return "movss\t{%1, %0|%0, %1}";
2357 return "movss\t{%1, %0|%0, %1}";
2361 return "movd\t{%1, %0|%0, %1}";
2364 return "movq\t{%1, %0|%0, %1}";
2370 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2372 (cond [(eq_attr "alternative" "3,4,9,10")
2374 (eq_attr "alternative" "5")
2376 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2378 (ne (symbol_ref "TARGET_SSE2")
2380 (eq (symbol_ref "optimize_size")
2383 (const_string "V4SF"))
2384 /* For architectures resolving dependencies on
2385 whole SSE registers use APS move to break dependency
2386 chains, otherwise use short move to avoid extra work.
2388 Do the same for architectures resolving dependencies on
2389 the parts. While in DF mode it is better to always handle
2390 just register parts, the SF mode is different due to lack
2391 of instructions to load just part of the register. It is
2392 better to maintain the whole registers in single format
2393 to avoid problems on using packed logical operations. */
2394 (eq_attr "alternative" "6")
2396 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2398 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2400 (const_string "V4SF")
2401 (const_string "SF"))
2402 (eq_attr "alternative" "11")
2403 (const_string "DI")]
2404 (const_string "SF")))])
2406 (define_insn "*swapsf"
2407 [(set (match_operand:SF 0 "register_operand" "+f")
2408 (match_operand:SF 1 "register_operand" "+f"))
2411 "reload_completed || !TARGET_SSE"
2413 if (STACK_TOP_P (operands[0]))
2418 [(set_attr "type" "fxch")
2419 (set_attr "mode" "SF")])
2421 (define_expand "movdf"
2422 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2423 (match_operand:DF 1 "general_operand" ""))]
2425 "ix86_expand_move (DFmode, operands); DONE;")
2427 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2428 ;; Size of pushdf using integer instructions is 2+2*memory operand size
2429 ;; On the average, pushdf using integers can be still shorter. Allow this
2430 ;; pattern for optimize_size too.
2432 (define_insn "*pushdf_nointeger"
2433 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2434 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2435 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2437 /* This insn should be already splitted before reg-stack. */
2440 [(set_attr "type" "multi")
2441 (set_attr "mode" "DF,SI,SI,DF")])
2443 (define_insn "*pushdf_integer"
2444 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2445 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2446 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2448 /* This insn should be already splitted before reg-stack. */
2451 [(set_attr "type" "multi")
2452 (set_attr "mode" "DF,SI,DF")])
2454 ;; %%% Kill this when call knows how to work this out.
2456 [(set (match_operand:DF 0 "push_operand" "")
2457 (match_operand:DF 1 "any_fp_register_operand" ""))]
2458 "!TARGET_64BIT && reload_completed"
2459 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
2460 (set (mem:DF (reg:SI 7)) (match_dup 1))]
2464 [(set (match_operand:DF 0 "push_operand" "")
2465 (match_operand:DF 1 "any_fp_register_operand" ""))]
2466 "TARGET_64BIT && reload_completed"
2467 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2468 (set (mem:DF (reg:DI 7)) (match_dup 1))]
2472 [(set (match_operand:DF 0 "push_operand" "")
2473 (match_operand:DF 1 "general_operand" ""))]
2476 "ix86_split_long_move (operands); DONE;")
2478 ;; Moving is usually shorter when only FP registers are used. This separate
2479 ;; movdf pattern avoids the use of integer registers for FP operations
2480 ;; when optimizing for size.
2482 (define_insn "*movdf_nointeger"
2483 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2484 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,C,Y#f,YHm#f,Y#f"))]
2485 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2486 && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
2487 && (reload_in_progress || reload_completed
2488 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2489 || GET_CODE (operands[1]) != CONST_DOUBLE
2490 || memory_operand (operands[0], DFmode))"
2492 switch (which_alternative)
2495 if (REG_P (operands[1])
2496 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2498 if (REGNO (operands[0]) == FIRST_STACK_REG
2499 && TARGET_USE_FFREEP)
2500 return "ffreep\t%y0";
2503 else if (STACK_TOP_P (operands[0]))
2504 return "fld%z1\t%y1";
2509 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2510 return "fstp%z0\t%y0";
2512 return "fst%z0\t%y0";
2515 return standard_80387_constant_opcode (operands[1]);
2521 switch (get_attr_mode (insn))
2524 return "xorps\t%0, %0";
2526 return "xorpd\t%0, %0";
2528 return "pxor\t%0, %0";
2533 switch (get_attr_mode (insn))
2536 return "movaps\t{%1, %0|%0, %1}";
2538 return "movapd\t{%1, %0|%0, %1}";
2540 return "movsd\t{%1, %0|%0, %1}";
2545 if (get_attr_mode (insn) == MODE_V2DF)
2546 return "movlpd\t{%1, %0|%0, %1}";
2548 return "movsd\t{%1, %0|%0, %1}";
2550 return "movsd\t{%1, %0|%0, %1}";
2556 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2558 (cond [(eq_attr "alternative" "3,4")
2560 /* xorps is one byte shorter. */
2561 (eq_attr "alternative" "5")
2562 (cond [(ne (symbol_ref "optimize_size")
2564 (const_string "V4SF")
2565 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2567 (const_string "TI")]
2568 (const_string "V2DF"))
2569 /* For architectures resolving dependencies on
2570 whole SSE registers use APD move to break dependency
2571 chains, otherwise use short move to avoid extra work.
2573 movaps encodes one byte shorter. */
2574 (eq_attr "alternative" "6")
2576 [(ne (symbol_ref "optimize_size")
2578 (const_string "V4SF")
2579 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2581 (const_string "V2DF")]
2582 (const_string "DF"))
2583 /* For architectures resolving dependencies on register
2584 parts we may avoid extra work to zero out upper part
2586 (eq_attr "alternative" "7")
2588 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2590 (const_string "V2DF")
2591 (const_string "DF"))]
2592 (const_string "DF")))])
2594 (define_insn "*movdf_integer"
2595 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2596 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,C,Y#rf,Ym#rf,Y#rf"))]
2597 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2598 && ((!optimize_size && TARGET_INTEGER_DFMODE_MOVES) || TARGET_64BIT)
2599 && (reload_in_progress || reload_completed
2600 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2601 || GET_CODE (operands[1]) != CONST_DOUBLE
2602 || memory_operand (operands[0], DFmode))"
2604 switch (which_alternative)
2607 if (REG_P (operands[1])
2608 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2610 if (REGNO (operands[0]) == FIRST_STACK_REG
2611 && TARGET_USE_FFREEP)
2612 return "ffreep\t%y0";
2615 else if (STACK_TOP_P (operands[0]))
2616 return "fld%z1\t%y1";
2621 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2622 return "fstp%z0\t%y0";
2624 return "fst%z0\t%y0";
2627 return standard_80387_constant_opcode (operands[1]);
2634 switch (get_attr_mode (insn))
2637 return "xorps\t%0, %0";
2639 return "xorpd\t%0, %0";
2641 return "pxor\t%0, %0";
2646 switch (get_attr_mode (insn))
2649 return "movaps\t{%1, %0|%0, %1}";
2651 return "movapd\t{%1, %0|%0, %1}";
2653 return "movsd\t{%1, %0|%0, %1}";
2658 if (get_attr_mode (insn) == MODE_V2DF)
2659 return "movlpd\t{%1, %0|%0, %1}";
2661 return "movsd\t{%1, %0|%0, %1}";
2663 return "movsd\t{%1, %0|%0, %1}";
2669 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2671 (cond [(eq_attr "alternative" "3,4")
2673 /* xorps is one byte shorter. */
2674 (eq_attr "alternative" "5")
2675 (cond [(ne (symbol_ref "optimize_size")
2677 (const_string "V4SF")
2678 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2680 (const_string "TI")]
2681 (const_string "V2DF"))
2682 /* For architectures resolving dependencies on
2683 whole SSE registers use APD move to break dependency
2684 chains, otherwise use short move to avoid extra work.
2686 movaps encodes one byte shorter. */
2687 (eq_attr "alternative" "6")
2689 [(ne (symbol_ref "optimize_size")
2691 (const_string "V4SF")
2692 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2694 (const_string "V2DF")]
2695 (const_string "DF"))
2696 /* For architectures resolving dependencies on register
2697 parts we may avoid extra work to zero out upper part
2699 (eq_attr "alternative" "7")
2701 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2703 (const_string "V2DF")
2704 (const_string "DF"))]
2705 (const_string "DF")))])
2708 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2709 (match_operand:DF 1 "general_operand" ""))]
2711 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2712 && ! (ANY_FP_REG_P (operands[0]) ||
2713 (GET_CODE (operands[0]) == SUBREG
2714 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2715 && ! (ANY_FP_REG_P (operands[1]) ||
2716 (GET_CODE (operands[1]) == SUBREG
2717 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2719 "ix86_split_long_move (operands); DONE;")
2721 (define_insn "*swapdf"
2722 [(set (match_operand:DF 0 "register_operand" "+f")
2723 (match_operand:DF 1 "register_operand" "+f"))
2726 "reload_completed || !TARGET_SSE2"
2728 if (STACK_TOP_P (operands[0]))
2733 [(set_attr "type" "fxch")
2734 (set_attr "mode" "DF")])
2736 (define_expand "movxf"
2737 [(set (match_operand:XF 0 "nonimmediate_operand" "")
2738 (match_operand:XF 1 "general_operand" ""))]
2740 "ix86_expand_move (XFmode, operands); DONE;")
2742 (define_expand "movtf"
2743 [(set (match_operand:TF 0 "nonimmediate_operand" "")
2744 (match_operand:TF 1 "general_operand" ""))]
2746 "ix86_expand_move (TFmode, operands); DONE;")
2748 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2749 ;; Size of pushdf using integer instructions is 3+3*memory operand size
2750 ;; Pushing using integer instructions is longer except for constants
2751 ;; and direct memory references.
2752 ;; (assuming that any given constant is pushed only once, but this ought to be
2753 ;; handled elsewhere).
2755 (define_insn "*pushxf_nointeger"
2756 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
2757 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
2758 "!TARGET_64BIT && optimize_size"
2760 /* This insn should be already splitted before reg-stack. */
2763 [(set_attr "type" "multi")
2764 (set_attr "mode" "XF,SI,SI")])
2766 (define_insn "*pushtf_nointeger"
2767 [(set (match_operand:TF 0 "push_operand" "=<,<,<")
2768 (match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))]
2771 /* This insn should be already splitted before reg-stack. */
2774 [(set_attr "type" "multi")
2775 (set_attr "mode" "XF,SI,SI")])
2777 (define_insn "*pushxf_integer"
2778 [(set (match_operand:XF 0 "push_operand" "=<,<")
2779 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
2780 "!TARGET_64BIT && !optimize_size"
2782 /* This insn should be already splitted before reg-stack. */
2785 [(set_attr "type" "multi")
2786 (set_attr "mode" "XF,SI")])
2788 (define_insn "*pushtf_integer"
2789 [(set (match_operand:TF 0 "push_operand" "=<,<")
2790 (match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))]
2793 /* This insn should be already splitted before reg-stack. */
2796 [(set_attr "type" "multi")
2797 (set_attr "mode" "XF,SI")])
2800 [(set (match_operand 0 "push_operand" "")
2801 (match_operand 1 "general_operand" ""))]
2803 && (GET_MODE (operands[0]) == XFmode
2804 || GET_MODE (operands[0]) == TFmode
2805 || GET_MODE (operands[0]) == DFmode)
2806 && !ANY_FP_REG_P (operands[1])"
2808 "ix86_split_long_move (operands); DONE;")
2811 [(set (match_operand:XF 0 "push_operand" "")
2812 (match_operand:XF 1 "any_fp_register_operand" ""))]
2814 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
2815 (set (mem:XF (reg:SI 7)) (match_dup 1))])
2818 [(set (match_operand:TF 0 "push_operand" "")
2819 (match_operand:TF 1 "any_fp_register_operand" ""))]
2821 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
2822 (set (mem:TF (reg:SI 7)) (match_dup 1))])
2825 [(set (match_operand:TF 0 "push_operand" "")
2826 (match_operand:TF 1 "any_fp_register_operand" ""))]
2828 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
2829 (set (mem:TF (reg:DI 7)) (match_dup 1))])
2831 ;; Do not use integer registers when optimizing for size
2832 (define_insn "*movxf_nointeger"
2833 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2834 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2837 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2838 && (reload_in_progress || reload_completed
2839 || GET_CODE (operands[1]) != CONST_DOUBLE
2840 || memory_operand (operands[0], XFmode))"
2842 switch (which_alternative)
2845 if (REG_P (operands[1])
2846 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2848 if (REGNO (operands[0]) == FIRST_STACK_REG
2849 && TARGET_USE_FFREEP)
2850 return "ffreep\t%y0";
2853 else if (STACK_TOP_P (operands[0]))
2854 return "fld%z1\t%y1";
2859 /* There is no non-popping store to memory for XFmode. So if
2860 we need one, follow the store with a load. */
2861 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2862 return "fstp%z0\t%y0\;fld%z0\t%y0";
2864 return "fstp%z0\t%y0";
2867 return standard_80387_constant_opcode (operands[1]);
2874 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2875 (set_attr "mode" "XF,XF,XF,SI,SI")])
2877 (define_insn "*movtf_nointeger"
2878 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2879 (match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2880 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2882 && (reload_in_progress || reload_completed
2883 || GET_CODE (operands[1]) != CONST_DOUBLE
2884 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2885 || memory_operand (operands[0], TFmode))"
2887 switch (which_alternative)
2890 if (REG_P (operands[1])
2891 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2893 if (REGNO (operands[0]) == FIRST_STACK_REG
2894 && TARGET_USE_FFREEP)
2895 return "ffreep\t%y0";
2898 else if (STACK_TOP_P (operands[0]))
2899 return "fld%z1\t%y1";
2904 /* There is no non-popping store to memory for XFmode. So if
2905 we need one, follow the store with a load. */
2906 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2907 return "fstp%z0\t%y0\;fld%z0\t%y0";
2909 return "fstp%z0\t%y0";
2912 return standard_80387_constant_opcode (operands[1]);
2919 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2920 (set_attr "mode" "XF,XF,XF,SI,SI")])
2922 (define_insn "*movxf_integer"
2923 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2924 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2927 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2928 && (reload_in_progress || reload_completed
2929 || GET_CODE (operands[1]) != CONST_DOUBLE
2930 || memory_operand (operands[0], XFmode))"
2932 switch (which_alternative)
2935 if (REG_P (operands[1])
2936 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2938 if (REGNO (operands[0]) == FIRST_STACK_REG
2939 && TARGET_USE_FFREEP)
2940 return "ffreep\t%y0";
2943 else if (STACK_TOP_P (operands[0]))
2944 return "fld%z1\t%y1";
2949 /* There is no non-popping store to memory for XFmode. So if
2950 we need one, follow the store with a load. */
2951 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2952 return "fstp%z0\t%y0\;fld%z0\t%y0";
2954 return "fstp%z0\t%y0";
2957 return standard_80387_constant_opcode (operands[1]);
2964 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2965 (set_attr "mode" "XF,XF,XF,SI,SI")])
2967 (define_insn "*movtf_integer"
2968 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2969 (match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2970 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2972 && (reload_in_progress || reload_completed
2973 || GET_CODE (operands[1]) != CONST_DOUBLE
2974 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2975 || memory_operand (operands[0], TFmode))"
2977 switch (which_alternative)
2980 if (REG_P (operands[1])
2981 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2983 if (REGNO (operands[0]) == FIRST_STACK_REG
2984 && TARGET_USE_FFREEP)
2985 return "ffreep\t%y0";
2988 else if (STACK_TOP_P (operands[0]))
2989 return "fld%z1\t%y1";
2994 /* There is no non-popping store to memory for XFmode. So if
2995 we need one, follow the store with a load. */
2996 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2997 return "fstp%z0\t%y0\;fld%z0\t%y0";
2999 return "fstp%z0\t%y0";
3002 return standard_80387_constant_opcode (operands[1]);
3009 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3010 (set_attr "mode" "XF,XF,XF,SI,SI")])
3013 [(set (match_operand 0 "nonimmediate_operand" "")
3014 (match_operand 1 "general_operand" ""))]
3016 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3017 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode)
3018 && ! (ANY_FP_REG_P (operands[0]) ||
3019 (GET_CODE (operands[0]) == SUBREG
3020 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
3021 && ! (ANY_FP_REG_P (operands[1]) ||
3022 (GET_CODE (operands[1]) == SUBREG
3023 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
3025 "ix86_split_long_move (operands); DONE;")
3028 [(set (match_operand 0 "register_operand" "")
3029 (match_operand 1 "memory_operand" ""))]
3031 && GET_CODE (operands[1]) == MEM
3032 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode
3033 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
3034 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
3035 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
3036 && (!(SSE_REG_P (operands[0]) ||
3037 (GET_CODE (operands[0]) == SUBREG
3038 && SSE_REG_P (SUBREG_REG (operands[0]))))
3039 || standard_sse_constant_p (get_pool_constant (XEXP (operands[1], 0))))
3040 && (!(FP_REG_P (operands[0]) ||
3041 (GET_CODE (operands[0]) == SUBREG
3042 && FP_REG_P (SUBREG_REG (operands[0]))))
3043 || standard_80387_constant_p (get_pool_constant (XEXP (operands[1], 0))))"
3046 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
3048 (define_insn "swapxf"
3049 [(set (match_operand:XF 0 "register_operand" "+f")
3050 (match_operand:XF 1 "register_operand" "+f"))
3055 if (STACK_TOP_P (operands[0]))
3060 [(set_attr "type" "fxch")
3061 (set_attr "mode" "XF")])
3063 (define_insn "swaptf"
3064 [(set (match_operand:TF 0 "register_operand" "+f")
3065 (match_operand:TF 1 "register_operand" "+f"))
3070 if (STACK_TOP_P (operands[0]))
3075 [(set_attr "type" "fxch")
3076 (set_attr "mode" "XF")])
3078 ;; Zero extension instructions
3080 (define_expand "zero_extendhisi2"
3081 [(set (match_operand:SI 0 "register_operand" "")
3082 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
3085 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3087 operands[1] = force_reg (HImode, operands[1]);
3088 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
3093 (define_insn "zero_extendhisi2_and"
3094 [(set (match_operand:SI 0 "register_operand" "=r")
3095 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
3096 (clobber (reg:CC 17))]
3097 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3099 [(set_attr "type" "alu1")
3100 (set_attr "mode" "SI")])
3103 [(set (match_operand:SI 0 "register_operand" "")
3104 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
3105 (clobber (reg:CC 17))]
3106 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3107 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
3108 (clobber (reg:CC 17))])]
3111 (define_insn "*zero_extendhisi2_movzwl"
3112 [(set (match_operand:SI 0 "register_operand" "=r")
3113 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3114 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3115 "movz{wl|x}\t{%1, %0|%0, %1}"
3116 [(set_attr "type" "imovx")
3117 (set_attr "mode" "SI")])
3119 (define_expand "zero_extendqihi2"
3121 [(set (match_operand:HI 0 "register_operand" "")
3122 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3123 (clobber (reg:CC 17))])]
3127 (define_insn "*zero_extendqihi2_and"
3128 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
3129 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3130 (clobber (reg:CC 17))]
3131 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3133 [(set_attr "type" "alu1")
3134 (set_attr "mode" "HI")])
3136 (define_insn "*zero_extendqihi2_movzbw_and"
3137 [(set (match_operand:HI 0 "register_operand" "=r,r")
3138 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3139 (clobber (reg:CC 17))]
3140 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3142 [(set_attr "type" "imovx,alu1")
3143 (set_attr "mode" "HI")])
3145 (define_insn "*zero_extendqihi2_movzbw"
3146 [(set (match_operand:HI 0 "register_operand" "=r")
3147 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3148 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3149 "movz{bw|x}\t{%1, %0|%0, %1}"
3150 [(set_attr "type" "imovx")
3151 (set_attr "mode" "HI")])
3153 ;; For the movzbw case strip only the clobber
3155 [(set (match_operand:HI 0 "register_operand" "")
3156 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3157 (clobber (reg:CC 17))]
3159 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3160 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3161 [(set (match_operand:HI 0 "register_operand" "")
3162 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
3164 ;; When source and destination does not overlap, clear destination
3165 ;; first and then do the movb
3167 [(set (match_operand:HI 0 "register_operand" "")
3168 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3169 (clobber (reg:CC 17))]
3171 && ANY_QI_REG_P (operands[0])
3172 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3173 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3174 [(set (match_dup 0) (const_int 0))
3175 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3176 "operands[2] = gen_lowpart (QImode, operands[0]);")
3178 ;; Rest is handled by single and.
3180 [(set (match_operand:HI 0 "register_operand" "")
3181 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
3182 (clobber (reg:CC 17))]
3184 && true_regnum (operands[0]) == true_regnum (operands[1])"
3185 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
3186 (clobber (reg:CC 17))])]
3189 (define_expand "zero_extendqisi2"
3191 [(set (match_operand:SI 0 "register_operand" "")
3192 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3193 (clobber (reg:CC 17))])]
3197 (define_insn "*zero_extendqisi2_and"
3198 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
3199 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3200 (clobber (reg:CC 17))]
3201 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3203 [(set_attr "type" "alu1")
3204 (set_attr "mode" "SI")])
3206 (define_insn "*zero_extendqisi2_movzbw_and"
3207 [(set (match_operand:SI 0 "register_operand" "=r,r")
3208 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3209 (clobber (reg:CC 17))]
3210 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3212 [(set_attr "type" "imovx,alu1")
3213 (set_attr "mode" "SI")])
3215 (define_insn "*zero_extendqisi2_movzbw"
3216 [(set (match_operand:SI 0 "register_operand" "=r")
3217 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3218 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3219 "movz{bl|x}\t{%1, %0|%0, %1}"
3220 [(set_attr "type" "imovx")
3221 (set_attr "mode" "SI")])
3223 ;; For the movzbl case strip only the clobber
3225 [(set (match_operand:SI 0 "register_operand" "")
3226 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3227 (clobber (reg:CC 17))]
3229 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3230 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3232 (zero_extend:SI (match_dup 1)))])
3234 ;; When source and destination does not overlap, clear destination
3235 ;; first and then do the movb
3237 [(set (match_operand:SI 0 "register_operand" "")
3238 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3239 (clobber (reg:CC 17))]
3241 && ANY_QI_REG_P (operands[0])
3242 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3243 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3244 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3245 [(set (match_dup 0) (const_int 0))
3246 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3247 "operands[2] = gen_lowpart (QImode, operands[0]);")
3249 ;; Rest is handled by single and.
3251 [(set (match_operand:SI 0 "register_operand" "")
3252 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3253 (clobber (reg:CC 17))]
3255 && true_regnum (operands[0]) == true_regnum (operands[1])"
3256 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3257 (clobber (reg:CC 17))])]
3260 ;; %%% Kill me once multi-word ops are sane.
3261 (define_expand "zero_extendsidi2"
3262 [(set (match_operand:DI 0 "register_operand" "=r")
3263 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3267 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3272 (define_insn "zero_extendsidi2_32"
3273 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
3274 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r")))
3275 (clobber (reg:CC 17))]
3278 [(set_attr "mode" "SI")])
3280 (define_insn "zero_extendsidi2_rex64"
3281 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
3282 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))]
3285 mov\t{%k1, %k0|%k0, %k1}
3287 [(set_attr "type" "imovx,imov")
3288 (set_attr "mode" "SI,DI")])
3291 [(set (match_operand:DI 0 "memory_operand" "")
3292 (zero_extend:DI (match_dup 0)))]
3294 [(set (match_dup 4) (const_int 0))]
3295 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3298 [(set (match_operand:DI 0 "register_operand" "")
3299 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3300 (clobber (reg:CC 17))]
3301 "!TARGET_64BIT && reload_completed
3302 && true_regnum (operands[0]) == true_regnum (operands[1])"
3303 [(set (match_dup 4) (const_int 0))]
3304 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3307 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3308 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3309 (clobber (reg:CC 17))]
3310 "!TARGET_64BIT && reload_completed"
3311 [(set (match_dup 3) (match_dup 1))
3312 (set (match_dup 4) (const_int 0))]
3313 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3315 (define_insn "zero_extendhidi2"
3316 [(set (match_operand:DI 0 "register_operand" "=r,r")
3317 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3320 movz{wl|x}\t{%1, %k0|%k0, %1}
3321 movz{wq|x}\t{%1, %0|%0, %1}"
3322 [(set_attr "type" "imovx")
3323 (set_attr "mode" "SI,DI")])
3325 (define_insn "zero_extendqidi2"
3326 [(set (match_operand:DI 0 "register_operand" "=r,r")
3327 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3330 movz{bl|x}\t{%1, %k0|%k0, %1}
3331 movz{bq|x}\t{%1, %0|%0, %1}"
3332 [(set_attr "type" "imovx")
3333 (set_attr "mode" "SI,DI")])
3335 ;; Sign extension instructions
3337 (define_expand "extendsidi2"
3338 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3339 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3340 (clobber (reg:CC 17))
3341 (clobber (match_scratch:SI 2 ""))])]
3346 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3351 (define_insn "*extendsidi2_1"
3352 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3353 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3354 (clobber (reg:CC 17))
3355 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3359 (define_insn "extendsidi2_rex64"
3360 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3361 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3365 movs{lq|x}\t{%1,%0|%0, %1}"
3366 [(set_attr "type" "imovx")
3367 (set_attr "mode" "DI")
3368 (set_attr "prefix_0f" "0")
3369 (set_attr "modrm" "0,1")])
3371 (define_insn "extendhidi2"
3372 [(set (match_operand:DI 0 "register_operand" "=r")
3373 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3375 "movs{wq|x}\t{%1,%0|%0, %1}"
3376 [(set_attr "type" "imovx")
3377 (set_attr "mode" "DI")])
3379 (define_insn "extendqidi2"
3380 [(set (match_operand:DI 0 "register_operand" "=r")
3381 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3383 "movs{bq|x}\t{%1,%0|%0, %1}"
3384 [(set_attr "type" "imovx")
3385 (set_attr "mode" "DI")])
3387 ;; Extend to memory case when source register does die.
3389 [(set (match_operand:DI 0 "memory_operand" "")
3390 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3391 (clobber (reg:CC 17))
3392 (clobber (match_operand:SI 2 "register_operand" ""))]
3394 && dead_or_set_p (insn, operands[1])
3395 && !reg_mentioned_p (operands[1], operands[0]))"
3396 [(set (match_dup 3) (match_dup 1))
3397 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3398 (clobber (reg:CC 17))])
3399 (set (match_dup 4) (match_dup 1))]
3400 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3402 ;; Extend to memory case when source register does not die.
3404 [(set (match_operand:DI 0 "memory_operand" "")
3405 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3406 (clobber (reg:CC 17))
3407 (clobber (match_operand:SI 2 "register_operand" ""))]
3411 split_di (&operands[0], 1, &operands[3], &operands[4]);
3413 emit_move_insn (operands[3], operands[1]);
3415 /* Generate a cltd if possible and doing so it profitable. */
3416 if (true_regnum (operands[1]) == 0
3417 && true_regnum (operands[2]) == 1
3418 && (optimize_size || TARGET_USE_CLTD))
3420 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3424 emit_move_insn (operands[2], operands[1]);
3425 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3427 emit_move_insn (operands[4], operands[2]);
3431 ;; Extend to register case. Optimize case where source and destination
3432 ;; registers match and cases where we can use cltd.
3434 [(set (match_operand:DI 0 "register_operand" "")
3435 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3436 (clobber (reg:CC 17))
3437 (clobber (match_scratch:SI 2 ""))]
3441 split_di (&operands[0], 1, &operands[3], &operands[4]);
3443 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3444 emit_move_insn (operands[3], operands[1]);
3446 /* Generate a cltd if possible and doing so it profitable. */
3447 if (true_regnum (operands[3]) == 0
3448 && (optimize_size || TARGET_USE_CLTD))
3450 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3454 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3455 emit_move_insn (operands[4], operands[1]);
3457 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3461 (define_insn "extendhisi2"
3462 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3463 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3466 switch (get_attr_prefix_0f (insn))
3469 return "{cwtl|cwde}";
3471 return "movs{wl|x}\t{%1,%0|%0, %1}";
3474 [(set_attr "type" "imovx")
3475 (set_attr "mode" "SI")
3476 (set (attr "prefix_0f")
3477 ;; movsx is short decodable while cwtl is vector decoded.
3478 (if_then_else (and (eq_attr "cpu" "!k6")
3479 (eq_attr "alternative" "0"))
3481 (const_string "1")))
3483 (if_then_else (eq_attr "prefix_0f" "0")
3485 (const_string "1")))])
3487 (define_insn "*extendhisi2_zext"
3488 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3490 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3493 switch (get_attr_prefix_0f (insn))
3496 return "{cwtl|cwde}";
3498 return "movs{wl|x}\t{%1,%k0|%k0, %1}";
3501 [(set_attr "type" "imovx")
3502 (set_attr "mode" "SI")
3503 (set (attr "prefix_0f")
3504 ;; movsx is short decodable while cwtl is vector decoded.
3505 (if_then_else (and (eq_attr "cpu" "!k6")
3506 (eq_attr "alternative" "0"))
3508 (const_string "1")))
3510 (if_then_else (eq_attr "prefix_0f" "0")
3512 (const_string "1")))])
3514 (define_insn "extendqihi2"
3515 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3516 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3519 switch (get_attr_prefix_0f (insn))
3522 return "{cbtw|cbw}";
3524 return "movs{bw|x}\t{%1,%0|%0, %1}";
3527 [(set_attr "type" "imovx")
3528 (set_attr "mode" "HI")
3529 (set (attr "prefix_0f")
3530 ;; movsx is short decodable while cwtl is vector decoded.
3531 (if_then_else (and (eq_attr "cpu" "!k6")
3532 (eq_attr "alternative" "0"))
3534 (const_string "1")))
3536 (if_then_else (eq_attr "prefix_0f" "0")
3538 (const_string "1")))])
3540 (define_insn "extendqisi2"
3541 [(set (match_operand:SI 0 "register_operand" "=r")
3542 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3544 "movs{bl|x}\t{%1,%0|%0, %1}"
3545 [(set_attr "type" "imovx")
3546 (set_attr "mode" "SI")])
3548 (define_insn "*extendqisi2_zext"
3549 [(set (match_operand:DI 0 "register_operand" "=r")
3551 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3553 "movs{bl|x}\t{%1,%k0|%k0, %1}"
3554 [(set_attr "type" "imovx")
3555 (set_attr "mode" "SI")])
3557 ;; Conversions between float and double.
3559 ;; These are all no-ops in the model used for the 80387. So just
3562 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3563 (define_insn "*dummy_extendsfdf2"
3564 [(set (match_operand:DF 0 "push_operand" "=<")
3565 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3570 [(set (match_operand:DF 0 "push_operand" "")
3571 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3573 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
3574 (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
3577 [(set (match_operand:DF 0 "push_operand" "")
3578 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3580 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
3581 (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))])
3583 (define_insn "*dummy_extendsfxf2"
3584 [(set (match_operand:XF 0 "push_operand" "=<")
3585 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3590 [(set (match_operand:XF 0 "push_operand" "")
3591 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3593 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3594 (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3596 (define_insn "*dummy_extendsftf2"
3597 [(set (match_operand:TF 0 "push_operand" "=<")
3598 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3603 [(set (match_operand:TF 0 "push_operand" "")
3604 (float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))]
3606 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3607 (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))])
3610 [(set (match_operand:TF 0 "push_operand" "")
3611 (float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))]
3613 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3614 (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3616 (define_insn "*dummy_extenddfxf2"
3617 [(set (match_operand:XF 0 "push_operand" "=<")
3618 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3623 [(set (match_operand:XF 0 "push_operand" "")
3624 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3626 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3627 (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3629 (define_insn "*dummy_extenddftf2"
3630 [(set (match_operand:TF 0 "push_operand" "=<")
3631 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3636 [(set (match_operand:TF 0 "push_operand" "")
3637 (float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))]
3639 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3640 (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3643 [(set (match_operand:TF 0 "push_operand" "")
3644 (float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))]
3646 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3647 (set (mem:TF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3649 (define_expand "extendsfdf2"
3650 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3651 (float_extend:DF (match_operand:SF 1 "general_operand" "")))]
3652 "TARGET_80387 || TARGET_SSE2"
3654 /* ??? Needed for compress_float_constant since all fp constants
3655 are LEGITIMATE_CONSTANT_P. */
3656 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3657 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3658 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3659 operands[1] = force_reg (SFmode, operands[1]);
3662 (define_insn "*extendsfdf2_1"
3663 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
3664 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
3665 "(TARGET_80387 || TARGET_SSE2)
3666 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3668 switch (which_alternative)
3671 if (REG_P (operands[1])
3672 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3674 else if (STACK_TOP_P (operands[0]))
3675 return "fld%z1\t%y1";
3680 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3681 return "fstp%z0\t%y0";
3684 return "fst%z0\t%y0";
3686 return "cvtss2sd\t{%1, %0|%0, %1}";
3692 [(set_attr "type" "fmov,fmov,ssecvt")
3693 (set_attr "mode" "SF,XF,DF")])
3695 (define_insn "*extendsfdf2_1_sse_only"
3696 [(set (match_operand:DF 0 "register_operand" "=Y")
3697 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
3698 "!TARGET_80387 && TARGET_SSE2
3699 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3700 "cvtss2sd\t{%1, %0|%0, %1}"
3701 [(set_attr "type" "ssecvt")
3702 (set_attr "mode" "DF")])
3704 (define_expand "extendsfxf2"
3705 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3706 (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
3707 "!TARGET_64BIT && TARGET_80387"
3709 /* ??? Needed for compress_float_constant since all fp constants
3710 are LEGITIMATE_CONSTANT_P. */
3711 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3712 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3713 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3714 operands[1] = force_reg (SFmode, operands[1]);
3717 (define_insn "*extendsfxf2_1"
3718 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3719 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3720 "!TARGET_64BIT && TARGET_80387
3721 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3723 switch (which_alternative)
3726 if (REG_P (operands[1])
3727 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3729 else if (STACK_TOP_P (operands[0]))
3730 return "fld%z1\t%y1";
3735 /* There is no non-popping store to memory for XFmode. So if
3736 we need one, follow the store with a load. */
3737 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3738 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3740 return "fstp%z0\t%y0";
3746 [(set_attr "type" "fmov")
3747 (set_attr "mode" "SF,XF")])
3749 (define_expand "extendsftf2"
3750 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3751 (float_extend:TF (match_operand:SF 1 "general_operand" "")))]
3754 /* ??? Needed for compress_float_constant since all fp constants
3755 are LEGITIMATE_CONSTANT_P. */
3756 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3757 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3758 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3759 operands[1] = force_reg (SFmode, operands[1]);
3762 (define_insn "*extendsftf2_1"
3763 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
3764 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3766 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3768 switch (which_alternative)
3771 if (REG_P (operands[1])
3772 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3774 else if (STACK_TOP_P (operands[0]))
3775 return "fld%z1\t%y1";
3780 /* There is no non-popping store to memory for XFmode. So if
3781 we need one, follow the store with a load. */
3782 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3783 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3785 return "fstp%z0\t%y0";
3791 [(set_attr "type" "fmov")
3792 (set_attr "mode" "SF,XF")])
3794 (define_expand "extenddfxf2"
3795 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3796 (float_extend:XF (match_operand:DF 1 "general_operand" "")))]
3797 "!TARGET_64BIT && TARGET_80387"
3799 /* ??? Needed for compress_float_constant since all fp constants
3800 are LEGITIMATE_CONSTANT_P. */
3801 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3802 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3803 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3804 operands[1] = force_reg (DFmode, operands[1]);
3807 (define_insn "*extenddfxf2_1"
3808 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3809 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3810 "!TARGET_64BIT && TARGET_80387
3811 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3813 switch (which_alternative)
3816 if (REG_P (operands[1])
3817 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3819 else if (STACK_TOP_P (operands[0]))
3820 return "fld%z1\t%y1";
3825 /* There is no non-popping store to memory for XFmode. So if
3826 we need one, follow the store with a load. */
3827 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3828 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3830 return "fstp%z0\t%y0";
3836 [(set_attr "type" "fmov")
3837 (set_attr "mode" "DF,XF")])
3839 (define_expand "extenddftf2"
3840 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3841 (float_extend:TF (match_operand:DF 1 "general_operand" "")))]
3844 /* ??? Needed for compress_float_constant since all fp constants
3845 are LEGITIMATE_CONSTANT_P. */
3846 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3847 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3848 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3849 operands[1] = force_reg (DFmode, operands[1]);
3852 (define_insn "*extenddftf2_1"
3853 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
3854 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3856 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3858 switch (which_alternative)
3861 if (REG_P (operands[1])
3862 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3864 else if (STACK_TOP_P (operands[0]))
3865 return "fld%z1\t%y1";
3870 /* There is no non-popping store to memory for XFmode. So if
3871 we need one, follow the store with a load. */
3872 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3873 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3875 return "fstp%z0\t%y0";
3881 [(set_attr "type" "fmov")
3882 (set_attr "mode" "DF,XF")])
3884 ;; %%% This seems bad bad news.
3885 ;; This cannot output into an f-reg because there is no way to be sure
3886 ;; of truncating in that case. Otherwise this is just like a simple move
3887 ;; insn. So we pretend we can output to a reg in order to get better
3888 ;; register preferencing, but we really use a stack slot.
3890 (define_expand "truncdfsf2"
3891 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3893 (match_operand:DF 1 "register_operand" "")))
3894 (clobber (match_dup 2))])]
3895 "TARGET_80387 || TARGET_SSE2"
3898 operands[2] = assign_386_stack_local (SFmode, 0);
3901 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
3906 (define_insn "*truncdfsf2_1"
3907 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3909 (match_operand:DF 1 "register_operand" "f,f,f,f")))
3910 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3911 "TARGET_80387 && !TARGET_SSE2"
3913 switch (which_alternative)
3916 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3917 return "fstp%z0\t%y0";
3919 return "fst%z0\t%y0";
3924 [(set_attr "type" "fmov,multi,multi,multi")
3925 (set_attr "mode" "SF,SF,SF,SF")])
3927 (define_insn "*truncdfsf2_1_sse"
3928 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m#fxr,?f#xr,?r#fx,?x#fr,Y#fr")
3930 (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
3931 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3932 "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3934 switch (which_alternative)
3937 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3938 return "fstp%z0\t%y0";
3940 return "fst%z0\t%y0";
3947 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3948 (set_attr "mode" "SF,SF,SF,SF,DF")])
3950 (define_insn "*truncdfsf2_1_sse_nooverlap"
3951 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,&Y")
3953 (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
3954 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3955 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3957 switch (which_alternative)
3960 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3961 return "fstp%z0\t%y0";
3963 return "fst%z0\t%y0";
3970 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3971 (set_attr "mode" "SF,SF,SF,SF,DF")])
3973 (define_insn "*truncdfsf2_2"
3974 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,Y,!m")
3976 (match_operand:DF 1 "nonimmediate_operand" "Y,mY,f#Y")))]
3977 "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
3978 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3980 switch (which_alternative)
3984 return "cvtsd2ss\t{%1, %0|%0, %1}";
3986 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3987 return "fstp%z0\t%y0";
3989 return "fst%z0\t%y0";
3994 [(set_attr "type" "ssecvt,ssecvt,fmov")
3995 (set_attr "athlon_decode" "vector,double,*")
3996 (set_attr "mode" "SF,SF,SF")])
3998 (define_insn "*truncdfsf2_2_nooverlap"
3999 [(set (match_operand:SF 0 "nonimmediate_operand" "=&Y,!m")
4001 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
4002 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
4003 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4005 switch (which_alternative)
4010 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4011 return "fstp%z0\t%y0";
4013 return "fst%z0\t%y0";
4018 [(set_attr "type" "ssecvt,fmov")
4019 (set_attr "mode" "DF,SF")])
4021 (define_insn "*truncdfsf2_3"
4022 [(set (match_operand:SF 0 "memory_operand" "=m")
4024 (match_operand:DF 1 "register_operand" "f")))]
4027 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4028 return "fstp%z0\t%y0";
4030 return "fst%z0\t%y0";
4032 [(set_attr "type" "fmov")
4033 (set_attr "mode" "SF")])
4035 (define_insn "truncdfsf2_sse_only"
4036 [(set (match_operand:SF 0 "register_operand" "=Y,Y")
4038 (match_operand:DF 1 "nonimmediate_operand" "Y,mY")))]
4039 "!TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
4040 "cvtsd2ss\t{%1, %0|%0, %1}"
4041 [(set_attr "type" "ssecvt")
4042 (set_attr "athlon_decode" "vector,double")
4043 (set_attr "mode" "SF")])
4045 (define_insn "*truncdfsf2_sse_only_nooverlap"
4046 [(set (match_operand:SF 0 "register_operand" "=&Y")
4048 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
4049 "!TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
4051 [(set_attr "type" "ssecvt")
4052 (set_attr "mode" "DF")])
4055 [(set (match_operand:SF 0 "memory_operand" "")
4057 (match_operand:DF 1 "register_operand" "")))
4058 (clobber (match_operand:SF 2 "memory_operand" ""))]
4060 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4063 ; Avoid possible reformatting penalty on the destination by first
4066 [(set (match_operand:SF 0 "register_operand" "")
4068 (match_operand:DF 1 "nonimmediate_operand" "")))
4069 (clobber (match_operand 2 "" ""))]
4070 "TARGET_80387 && reload_completed
4071 && SSE_REG_P (operands[0])
4072 && !STACK_REG_P (operands[1])"
4076 if (!TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS)
4077 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
4080 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4081 src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
4082 /* simplify_gen_subreg refuses to widen memory references. */
4083 if (GET_CODE (src) == SUBREG)
4084 alter_subreg (&src);
4085 if (reg_overlap_mentioned_p (operands[0], operands[1]))
4087 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4088 emit_insn (gen_cvtsd2ss (dest, dest, src));
4094 [(set (match_operand:SF 0 "register_operand" "")
4096 (match_operand:DF 1 "nonimmediate_operand" "")))]
4097 "TARGET_80387 && reload_completed
4098 && SSE_REG_P (operands[0]) && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
4102 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4103 src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
4104 /* simplify_gen_subreg refuses to widen memory references. */
4105 if (GET_CODE (src) == SUBREG)
4106 alter_subreg (&src);
4107 if (reg_overlap_mentioned_p (operands[0], operands[1]))
4109 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4110 emit_insn (gen_cvtsd2ss (dest, dest, src));
4115 [(set (match_operand:SF 0 "register_operand" "")
4117 (match_operand:DF 1 "fp_register_operand" "")))
4118 (clobber (match_operand:SF 2 "memory_operand" ""))]
4119 "TARGET_80387 && reload_completed"
4120 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4121 (set (match_dup 0) (match_dup 2))]
4124 (define_expand "truncxfsf2"
4125 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4127 (match_operand:XF 1 "register_operand" "")))
4128 (clobber (match_dup 2))])]
4129 "!TARGET_64BIT && TARGET_80387"
4130 "operands[2] = assign_386_stack_local (SFmode, 0);")
4132 (define_insn "*truncxfsf2_1"
4133 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4135 (match_operand:XF 1 "register_operand" "f,f,f,f")))
4136 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4137 "!TARGET_64BIT && TARGET_80387"
4139 switch (which_alternative)
4142 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4143 return "fstp%z0\t%y0";
4145 return "fst%z0\t%y0";
4150 [(set_attr "type" "fmov,multi,multi,multi")
4151 (set_attr "mode" "SF")])
4153 (define_insn "*truncxfsf2_2"
4154 [(set (match_operand:SF 0 "memory_operand" "=m")
4156 (match_operand:XF 1 "register_operand" "f")))]
4157 "!TARGET_64BIT && TARGET_80387"
4159 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4160 return "fstp%z0\t%y0";
4162 return "fst%z0\t%y0";
4164 [(set_attr "type" "fmov")
4165 (set_attr "mode" "SF")])
4168 [(set (match_operand:SF 0 "memory_operand" "")
4170 (match_operand:XF 1 "register_operand" "")))
4171 (clobber (match_operand:SF 2 "memory_operand" ""))]
4173 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4177 [(set (match_operand:SF 0 "register_operand" "")
4179 (match_operand:XF 1 "register_operand" "")))
4180 (clobber (match_operand:SF 2 "memory_operand" ""))]
4181 "TARGET_80387 && reload_completed"
4182 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4183 (set (match_dup 0) (match_dup 2))]
4186 (define_expand "trunctfsf2"
4187 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4189 (match_operand:TF 1 "register_operand" "")))
4190 (clobber (match_dup 2))])]
4192 "operands[2] = assign_386_stack_local (SFmode, 0);")
4194 (define_insn "*trunctfsf2_1"
4195 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4197 (match_operand:TF 1 "register_operand" "f,f,f,f")))
4198 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4201 switch (which_alternative)
4204 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4205 return "fstp%z0\t%y0";
4207 return "fst%z0\t%y0";
4212 [(set_attr "type" "fmov,multi,multi,multi")
4213 (set_attr "mode" "SF")])
4215 (define_insn "*trunctfsf2_2"
4216 [(set (match_operand:SF 0 "memory_operand" "=m")
4218 (match_operand:TF 1 "register_operand" "f")))]
4221 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4222 return "fstp%z0\t%y0";
4224 return "fst%z0\t%y0";
4226 [(set_attr "type" "fmov")
4227 (set_attr "mode" "SF")])
4230 [(set (match_operand:SF 0 "memory_operand" "")
4232 (match_operand:TF 1 "register_operand" "")))
4233 (clobber (match_operand:SF 2 "memory_operand" ""))]
4235 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4239 [(set (match_operand:SF 0 "register_operand" "")
4241 (match_operand:TF 1 "register_operand" "")))
4242 (clobber (match_operand:SF 2 "memory_operand" ""))]
4243 "TARGET_80387 && reload_completed"
4244 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4245 (set (match_dup 0) (match_dup 2))]
4249 (define_expand "truncxfdf2"
4250 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4252 (match_operand:XF 1 "register_operand" "")))
4253 (clobber (match_dup 2))])]
4254 "!TARGET_64BIT && TARGET_80387"
4255 "operands[2] = assign_386_stack_local (DFmode, 0);")
4257 (define_insn "*truncxfdf2_1"
4258 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
4260 (match_operand:XF 1 "register_operand" "f,f,f,f")))
4261 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4262 "!TARGET_64BIT && TARGET_80387"
4264 switch (which_alternative)
4267 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4268 return "fstp%z0\t%y0";
4270 return "fst%z0\t%y0";
4276 [(set_attr "type" "fmov,multi,multi,multi")
4277 (set_attr "mode" "DF")])
4279 (define_insn "*truncxfdf2_2"
4280 [(set (match_operand:DF 0 "memory_operand" "=m")
4282 (match_operand:XF 1 "register_operand" "f")))]
4283 "!TARGET_64BIT && TARGET_80387"
4285 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4286 return "fstp%z0\t%y0";
4288 return "fst%z0\t%y0";
4290 [(set_attr "type" "fmov")
4291 (set_attr "mode" "DF")])
4294 [(set (match_operand:DF 0 "memory_operand" "")
4296 (match_operand:XF 1 "register_operand" "")))
4297 (clobber (match_operand:DF 2 "memory_operand" ""))]
4299 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4303 [(set (match_operand:DF 0 "register_operand" "")
4305 (match_operand:XF 1 "register_operand" "")))
4306 (clobber (match_operand:DF 2 "memory_operand" ""))]
4307 "TARGET_80387 && reload_completed"
4308 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4309 (set (match_dup 0) (match_dup 2))]
4312 (define_expand "trunctfdf2"
4313 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4315 (match_operand:TF 1 "register_operand" "")))
4316 (clobber (match_dup 2))])]
4318 "operands[2] = assign_386_stack_local (DFmode, 0);")
4320 (define_insn "*trunctfdf2_1"
4321 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
4323 (match_operand:TF 1 "register_operand" "f,f,f,f")))
4324 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4327 switch (which_alternative)
4330 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4331 return "fstp%z0\t%y0";
4333 return "fst%z0\t%y0";
4339 [(set_attr "type" "fmov,multi,multi,multi")
4340 (set_attr "mode" "DF")])
4342 (define_insn "*trunctfdf2_2"
4343 [(set (match_operand:DF 0 "memory_operand" "=m")
4345 (match_operand:TF 1 "register_operand" "f")))]
4348 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4349 return "fstp%z0\t%y0";
4351 return "fst%z0\t%y0";
4353 [(set_attr "type" "fmov")
4354 (set_attr "mode" "DF")])
4357 [(set (match_operand:DF 0 "memory_operand" "")
4359 (match_operand:TF 1 "register_operand" "")))
4360 (clobber (match_operand:DF 2 "memory_operand" ""))]
4362 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4366 [(set (match_operand:DF 0 "register_operand" "")
4368 (match_operand:TF 1 "register_operand" "")))
4369 (clobber (match_operand:DF 2 "memory_operand" ""))]
4370 "TARGET_80387 && reload_completed"
4371 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4372 (set (match_dup 0) (match_dup 2))]
4376 ;; %%% Break up all these bad boys.
4378 ;; Signed conversion to DImode.
4380 (define_expand "fix_truncxfdi2"
4381 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4382 (fix:DI (match_operand:XF 1 "register_operand" "")))]
4383 "!TARGET_64BIT && TARGET_80387"
4386 (define_expand "fix_trunctfdi2"
4387 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4388 (fix:DI (match_operand:TF 1 "register_operand" "")))]
4392 (define_expand "fix_truncdfdi2"
4393 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4394 (fix:DI (match_operand:DF 1 "register_operand" "")))]
4395 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
4397 if (TARGET_64BIT && TARGET_SSE2)
4399 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4400 emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
4401 if (out != operands[0])
4402 emit_move_insn (operands[0], out);
4407 (define_expand "fix_truncsfdi2"
4408 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4409 (fix:DI (match_operand:SF 1 "register_operand" "")))]
4410 "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
4412 if (TARGET_SSE && TARGET_64BIT)
4414 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4415 emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
4416 if (out != operands[0])
4417 emit_move_insn (operands[0], out);
4422 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4423 ;; of the machinery.
4424 (define_insn_and_split "*fix_truncdi_1"
4425 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4426 (fix:DI (match_operand 1 "register_operand" "f,f")))]
4427 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4428 && !reload_completed && !reload_in_progress
4429 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4434 ix86_optimize_mode_switching = 1;
4435 operands[2] = assign_386_stack_local (HImode, 1);
4436 operands[3] = assign_386_stack_local (HImode, 2);
4437 if (memory_operand (operands[0], VOIDmode))
4438 emit_insn (gen_fix_truncdi_memory (operands[0], operands[1],
4439 operands[2], operands[3]));
4442 operands[4] = assign_386_stack_local (DImode, 0);
4443 emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1],
4444 operands[2], operands[3],
4449 [(set_attr "type" "fistp")
4450 (set_attr "mode" "DI")])
4452 (define_insn "fix_truncdi_nomemory"
4453 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4454 (fix:DI (match_operand 1 "register_operand" "f,f")))
4455 (use (match_operand:HI 2 "memory_operand" "m,m"))
4456 (use (match_operand:HI 3 "memory_operand" "m,m"))
4457 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
4458 (clobber (match_scratch:DF 5 "=&1f,&1f"))]
4459 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4460 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4462 [(set_attr "type" "fistp")
4463 (set_attr "mode" "DI")])
4465 (define_insn "fix_truncdi_memory"
4466 [(set (match_operand:DI 0 "memory_operand" "=m")
4467 (fix:DI (match_operand 1 "register_operand" "f")))
4468 (use (match_operand:HI 2 "memory_operand" "m"))
4469 (use (match_operand:HI 3 "memory_operand" "m"))
4470 (clobber (match_scratch:DF 4 "=&1f"))]
4471 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4472 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4473 "* operands[5] = operands[4]; return output_fix_trunc (insn, operands);"
4474 [(set_attr "type" "fistp")
4475 (set_attr "mode" "DI")])
4478 [(set (match_operand:DI 0 "register_operand" "")
4479 (fix:DI (match_operand 1 "register_operand" "")))
4480 (use (match_operand:HI 2 "memory_operand" ""))
4481 (use (match_operand:HI 3 "memory_operand" ""))
4482 (clobber (match_operand:DI 4 "memory_operand" ""))
4483 (clobber (match_scratch 5 ""))]
4485 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
4488 (clobber (match_dup 5))])
4489 (set (match_dup 0) (match_dup 4))]
4493 [(set (match_operand:DI 0 "memory_operand" "")
4494 (fix:DI (match_operand 1 "register_operand" "")))
4495 (use (match_operand:HI 2 "memory_operand" ""))
4496 (use (match_operand:HI 3 "memory_operand" ""))
4497 (clobber (match_operand:DI 4 "memory_operand" ""))
4498 (clobber (match_scratch 5 ""))]
4500 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
4503 (clobber (match_dup 5))])]
4506 ;; When SSE available, it is always faster to use it!
4507 (define_insn "fix_truncsfdi_sse"
4508 [(set (match_operand:DI 0 "register_operand" "=r,r")
4509 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4510 "TARGET_64BIT && TARGET_SSE"
4511 "cvttss2si{q}\t{%1, %0|%0, %1}"
4512 [(set_attr "type" "sseicvt")
4513 (set_attr "mode" "SF")
4514 (set_attr "athlon_decode" "double,vector")])
4516 ;; Avoid vector decoded form of the instruction.
4518 [(match_scratch:SF 2 "x")
4519 (set (match_operand:DI 0 "register_operand" "")
4520 (fix:DI (match_operand:SF 1 "memory_operand" "")))]
4521 "TARGET_K8 && !optimize_size"
4522 [(set (match_dup 2) (match_dup 1))
4523 (set (match_dup 0) (fix:DI (match_dup 2)))]
4526 (define_insn "fix_truncdfdi_sse"
4527 [(set (match_operand:DI 0 "register_operand" "=r,r")
4528 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4529 "TARGET_64BIT && TARGET_SSE2"
4530 "cvttsd2si{q}\t{%1, %0|%0, %1}"
4531 [(set_attr "type" "sseicvt,sseicvt")
4532 (set_attr "mode" "DF")
4533 (set_attr "athlon_decode" "double,vector")])
4535 ;; Avoid vector decoded form of the instruction.
4537 [(match_scratch:DF 2 "Y")
4538 (set (match_operand:DI 0 "register_operand" "")
4539 (fix:DI (match_operand:DF 1 "memory_operand" "")))]
4540 "TARGET_K8 && !optimize_size"
4541 [(set (match_dup 2) (match_dup 1))
4542 (set (match_dup 0) (fix:DI (match_dup 2)))]
4545 ;; Signed conversion to SImode.
4547 (define_expand "fix_truncxfsi2"
4548 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4549 (fix:SI (match_operand:XF 1 "register_operand" "")))]
4550 "!TARGET_64BIT && TARGET_80387"
4553 (define_expand "fix_trunctfsi2"
4554 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4555 (fix:SI (match_operand:TF 1 "register_operand" "")))]
4559 (define_expand "fix_truncdfsi2"
4560 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4561 (fix:SI (match_operand:DF 1 "register_operand" "")))]
4562 "TARGET_80387 || TARGET_SSE2"
4566 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4567 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4568 if (out != operands[0])
4569 emit_move_insn (operands[0], out);
4574 (define_expand "fix_truncsfsi2"
4575 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4576 (fix:SI (match_operand:SF 1 "register_operand" "")))]
4577 "TARGET_80387 || TARGET_SSE"
4581 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4582 emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
4583 if (out != operands[0])
4584 emit_move_insn (operands[0], out);
4589 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4590 ;; of the machinery.
4591 (define_insn_and_split "*fix_truncsi_1"
4592 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4593 (fix:SI (match_operand 1 "register_operand" "f,f")))]
4594 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4595 && !reload_completed && !reload_in_progress
4596 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4601 ix86_optimize_mode_switching = 1;
4602 operands[2] = assign_386_stack_local (HImode, 1);
4603 operands[3] = assign_386_stack_local (HImode, 2);
4604 if (memory_operand (operands[0], VOIDmode))
4605 emit_insn (gen_fix_truncsi_memory (operands[0], operands[1],
4606 operands[2], operands[3]));
4609 operands[4] = assign_386_stack_local (SImode, 0);
4610 emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1],
4611 operands[2], operands[3],
4616 [(set_attr "type" "fistp")
4617 (set_attr "mode" "SI")])
4619 (define_insn "fix_truncsi_nomemory"
4620 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4621 (fix:SI (match_operand 1 "register_operand" "f,f")))
4622 (use (match_operand:HI 2 "memory_operand" "m,m"))
4623 (use (match_operand:HI 3 "memory_operand" "m,m"))
4624 (clobber (match_operand:SI 4 "memory_operand" "=m,m"))]
4625 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4626 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4628 [(set_attr "type" "fistp")
4629 (set_attr "mode" "SI")])
4631 (define_insn "fix_truncsi_memory"
4632 [(set (match_operand:SI 0 "memory_operand" "=m")
4633 (fix:SI (match_operand 1 "register_operand" "f")))
4634 (use (match_operand:HI 2 "memory_operand" "m"))
4635 (use (match_operand:HI 3 "memory_operand" "m"))]
4636 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4637 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4638 "* return output_fix_trunc (insn, operands);"
4639 [(set_attr "type" "fistp")
4640 (set_attr "mode" "SI")])
4642 ;; When SSE available, it is always faster to use it!
4643 (define_insn "fix_truncsfsi_sse"
4644 [(set (match_operand:SI 0 "register_operand" "=r,r")
4645 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4647 "cvttss2si\t{%1, %0|%0, %1}"
4648 [(set_attr "type" "sseicvt")
4649 (set_attr "mode" "DF")
4650 (set_attr "athlon_decode" "double,vector")])
4652 ;; Avoid vector decoded form of the instruction.
4654 [(match_scratch:SF 2 "x")
4655 (set (match_operand:SI 0 "register_operand" "")
4656 (fix:SI (match_operand:SF 1 "memory_operand" "")))]
4657 "TARGET_K8 && !optimize_size"
4658 [(set (match_dup 2) (match_dup 1))
4659 (set (match_dup 0) (fix:SI (match_dup 2)))]
4662 (define_insn "fix_truncdfsi_sse"
4663 [(set (match_operand:SI 0 "register_operand" "=r,r")
4664 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4666 "cvttsd2si\t{%1, %0|%0, %1}"
4667 [(set_attr "type" "sseicvt")
4668 (set_attr "mode" "DF")
4669 (set_attr "athlon_decode" "double,vector")])
4671 ;; Avoid vector decoded form of the instruction.
4673 [(match_scratch:DF 2 "Y")
4674 (set (match_operand:SI 0 "register_operand" "")
4675 (fix:SI (match_operand:DF 1 "memory_operand" "")))]
4676 "TARGET_K8 && !optimize_size"
4677 [(set (match_dup 2) (match_dup 1))
4678 (set (match_dup 0) (fix:SI (match_dup 2)))]
4682 [(set (match_operand:SI 0 "register_operand" "")
4683 (fix:SI (match_operand 1 "register_operand" "")))
4684 (use (match_operand:HI 2 "memory_operand" ""))
4685 (use (match_operand:HI 3 "memory_operand" ""))
4686 (clobber (match_operand:SI 4 "memory_operand" ""))]
4688 [(parallel [(set (match_dup 4) (fix:SI (match_dup 1)))
4690 (use (match_dup 3))])
4691 (set (match_dup 0) (match_dup 4))]
4695 [(set (match_operand:SI 0 "memory_operand" "")
4696 (fix:SI (match_operand 1 "register_operand" "")))
4697 (use (match_operand:HI 2 "memory_operand" ""))
4698 (use (match_operand:HI 3 "memory_operand" ""))
4699 (clobber (match_operand:SI 4 "memory_operand" ""))]
4701 [(parallel [(set (match_dup 0) (fix:SI (match_dup 1)))
4703 (use (match_dup 3))])]
4706 ;; Signed conversion to HImode.
4708 (define_expand "fix_truncxfhi2"
4709 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4710 (fix:HI (match_operand:XF 1 "register_operand" "")))]
4711 "!TARGET_64BIT && TARGET_80387"
4714 (define_expand "fix_trunctfhi2"
4715 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4716 (fix:HI (match_operand:TF 1 "register_operand" "")))]
4720 (define_expand "fix_truncdfhi2"
4721 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4722 (fix:HI (match_operand:DF 1 "register_operand" "")))]
4723 "TARGET_80387 && !TARGET_SSE2"
4726 (define_expand "fix_truncsfhi2"
4727 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4728 (fix:HI (match_operand:SF 1 "register_operand" "")))]
4729 "TARGET_80387 && !TARGET_SSE"
4732 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4733 ;; of the machinery.
4734 (define_insn_and_split "*fix_trunchi_1"
4735 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4736 (fix:HI (match_operand 1 "register_operand" "f,f")))]
4737 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4738 && !reload_completed && !reload_in_progress
4739 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4744 ix86_optimize_mode_switching = 1;
4745 operands[2] = assign_386_stack_local (HImode, 1);
4746 operands[3] = assign_386_stack_local (HImode, 2);
4747 if (memory_operand (operands[0], VOIDmode))
4748 emit_insn (gen_fix_trunchi_memory (operands[0], operands[1],
4749 operands[2], operands[3]));
4752 operands[4] = assign_386_stack_local (HImode, 0);
4753 emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1],
4754 operands[2], operands[3],
4759 [(set_attr "type" "fistp")
4760 (set_attr "mode" "HI")])
4762 (define_insn "fix_trunchi_nomemory"
4763 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4764 (fix:HI (match_operand 1 "register_operand" "f,f")))
4765 (use (match_operand:HI 2 "memory_operand" "m,m"))
4766 (use (match_operand:HI 3 "memory_operand" "m,m"))
4767 (clobber (match_operand:HI 4 "memory_operand" "=m,m"))]
4768 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4769 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4771 [(set_attr "type" "fistp")
4772 (set_attr "mode" "HI")])
4774 (define_insn "fix_trunchi_memory"
4775 [(set (match_operand:HI 0 "memory_operand" "=m")
4776 (fix:HI (match_operand 1 "register_operand" "f")))
4777 (use (match_operand:HI 2 "memory_operand" "m"))
4778 (use (match_operand:HI 3 "memory_operand" "m"))]
4779 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4780 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4781 "* return output_fix_trunc (insn, operands);"
4782 [(set_attr "type" "fistp")
4783 (set_attr "mode" "HI")])
4786 [(set (match_operand:HI 0 "memory_operand" "")
4787 (fix:HI (match_operand 1 "register_operand" "")))
4788 (use (match_operand:HI 2 "memory_operand" ""))
4789 (use (match_operand:HI 3 "memory_operand" ""))
4790 (clobber (match_operand:HI 4 "memory_operand" ""))]
4792 [(parallel [(set (match_dup 0) (fix:HI (match_dup 1)))
4794 (use (match_dup 3))])]
4798 [(set (match_operand:HI 0 "register_operand" "")
4799 (fix:HI (match_operand 1 "register_operand" "")))
4800 (use (match_operand:HI 2 "memory_operand" ""))
4801 (use (match_operand:HI 3 "memory_operand" ""))
4802 (clobber (match_operand:HI 4 "memory_operand" ""))]
4804 [(parallel [(set (match_dup 4) (fix:HI (match_dup 1)))
4807 (clobber (match_dup 4))])
4808 (set (match_dup 0) (match_dup 4))]
4812 (define_insn "x86_fnstcw_1"
4813 [(set (match_operand:HI 0 "memory_operand" "=m")
4814 (unspec:HI [(reg:HI 18)] UNSPEC_FSTCW))]
4817 [(set_attr "length" "2")
4818 (set_attr "mode" "HI")
4819 (set_attr "unit" "i387")
4820 (set_attr "ppro_uops" "few")])
4822 (define_insn "x86_fldcw_1"
4824 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
4827 [(set_attr "length" "2")
4828 (set_attr "mode" "HI")
4829 (set_attr "unit" "i387")
4830 (set_attr "athlon_decode" "vector")
4831 (set_attr "ppro_uops" "few")])
4833 ;; Conversion between fixed point and floating point.
4835 ;; Even though we only accept memory inputs, the backend _really_
4836 ;; wants to be able to do this between registers.
4838 (define_expand "floathisf2"
4839 [(set (match_operand:SF 0 "register_operand" "")
4840 (float:SF (match_operand:HI 1 "nonimmediate_operand" "")))]
4841 "TARGET_SSE || TARGET_80387"
4843 if (TARGET_SSE && TARGET_SSE_MATH)
4845 emit_insn (gen_floatsisf2 (operands[0],
4846 convert_to_mode (SImode, operands[1], 0)));
4851 (define_insn "*floathisf2_1"
4852 [(set (match_operand:SF 0 "register_operand" "=f,f")
4853 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4854 "TARGET_80387 && (!TARGET_SSE || !TARGET_SSE_MATH)"
4858 [(set_attr "type" "fmov,multi")
4859 (set_attr "mode" "SF")
4860 (set_attr "fp_int_src" "true")])
4862 (define_expand "floatsisf2"
4863 [(set (match_operand:SF 0 "register_operand" "")
4864 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4865 "TARGET_SSE || TARGET_80387"
4868 (define_insn "*floatsisf2_i387"
4869 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4870 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4871 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4875 cvtsi2ss\t{%1, %0|%0, %1}
4876 cvtsi2ss\t{%1, %0|%0, %1}"
4877 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4878 (set_attr "mode" "SF")
4879 (set_attr "athlon_decode" "*,*,vector,double")
4880 (set_attr "fp_int_src" "true")])
4882 (define_insn "*floatsisf2_sse"
4883 [(set (match_operand:SF 0 "register_operand" "=x,x")
4884 (float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4886 "cvtsi2ss\t{%1, %0|%0, %1}"
4887 [(set_attr "type" "sseicvt")
4888 (set_attr "mode" "SF")
4889 (set_attr "athlon_decode" "vector,double")
4890 (set_attr "fp_int_src" "true")])
4892 ; Avoid possible reformatting penalty on the destination by first
4895 [(set (match_operand:SF 0 "register_operand" "")
4896 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4897 "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
4898 && SSE_REG_P (operands[0])"
4902 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4903 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4904 emit_insn (gen_cvtsi2ss (dest, dest, operands[1]));
4908 (define_expand "floatdisf2"
4909 [(set (match_operand:SF 0 "register_operand" "")
4910 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4911 "(TARGET_64BIT && TARGET_SSE) || TARGET_80387"
4914 (define_insn "*floatdisf2_i387_only"
4915 [(set (match_operand:SF 0 "register_operand" "=f,?f")
4916 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4917 "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
4921 [(set_attr "type" "fmov,multi")
4922 (set_attr "mode" "SF")
4923 (set_attr "fp_int_src" "true")])
4925 (define_insn "*floatdisf2_i387"
4926 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4927 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4928 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4932 cvtsi2ss{q}\t{%1, %0|%0, %1}
4933 cvtsi2ss{q}\t{%1, %0|%0, %1}"
4934 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4935 (set_attr "mode" "SF")
4936 (set_attr "athlon_decode" "*,*,vector,double")
4937 (set_attr "fp_int_src" "true")])
4939 (define_insn "*floatdisf2_sse"
4940 [(set (match_operand:SF 0 "register_operand" "=x,x")
4941 (float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4942 "TARGET_64BIT && TARGET_SSE"
4943 "cvtsi2ss{q}\t{%1, %0|%0, %1}"
4944 [(set_attr "type" "sseicvt")
4945 (set_attr "mode" "SF")
4946 (set_attr "athlon_decode" "vector,double")
4947 (set_attr "fp_int_src" "true")])
4949 ; Avoid possible reformatting penalty on the destination by first
4952 [(set (match_operand:SF 0 "register_operand" "")
4953 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4954 "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
4955 && SSE_REG_P (operands[0])"
4959 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4960 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4961 emit_insn (gen_cvtsi2ssq (dest, dest, operands[1]));
4965 (define_expand "floathidf2"
4966 [(set (match_operand:DF 0 "register_operand" "")
4967 (float:DF (match_operand:HI 1 "nonimmediate_operand" "")))]
4968 "TARGET_SSE2 || TARGET_80387"
4970 if (TARGET_SSE && TARGET_SSE_MATH)
4972 emit_insn (gen_floatsidf2 (operands[0],
4973 convert_to_mode (SImode, operands[1], 0)));
4978 (define_insn "*floathidf2_1"
4979 [(set (match_operand:DF 0 "register_operand" "=f,f")
4980 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4981 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
4985 [(set_attr "type" "fmov,multi")
4986 (set_attr "mode" "DF")
4987 (set_attr "fp_int_src" "true")])
4989 (define_expand "floatsidf2"
4990 [(set (match_operand:DF 0 "register_operand" "")
4991 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
4992 "TARGET_80387 || TARGET_SSE2"
4995 (define_insn "*floatsidf2_i387"
4996 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
4997 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4998 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
5002 cvtsi2sd\t{%1, %0|%0, %1}
5003 cvtsi2sd\t{%1, %0|%0, %1}"
5004 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
5005 (set_attr "mode" "DF")
5006 (set_attr "athlon_decode" "*,*,double,direct")
5007 (set_attr "fp_int_src" "true")])
5009 (define_insn "*floatsidf2_sse"
5010 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
5011 (float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
5013 "cvtsi2sd\t{%1, %0|%0, %1}"
5014 [(set_attr "type" "sseicvt")
5015 (set_attr "mode" "DF")
5016 (set_attr "athlon_decode" "double,direct")
5017 (set_attr "fp_int_src" "true")])
5019 (define_expand "floatdidf2"
5020 [(set (match_operand:DF 0 "register_operand" "")
5021 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
5022 "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387"
5025 (define_insn "*floatdidf2_i387_only"
5026 [(set (match_operand:DF 0 "register_operand" "=f,?f")
5027 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5028 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
5032 [(set_attr "type" "fmov,multi")
5033 (set_attr "mode" "DF")
5034 (set_attr "fp_int_src" "true")])
5036 (define_insn "*floatdidf2_i387"
5037 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
5038 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
5039 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
5043 cvtsi2sd{q}\t{%1, %0|%0, %1}
5044 cvtsi2sd{q}\t{%1, %0|%0, %1}"
5045 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
5046 (set_attr "mode" "DF")
5047 (set_attr "athlon_decode" "*,*,double,direct")
5048 (set_attr "fp_int_src" "true")])
5050 (define_insn "*floatdidf2_sse"
5051 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
5052 (float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
5054 "cvtsi2sd{q}\t{%1, %0|%0, %1}"
5055 [(set_attr "type" "sseicvt")
5056 (set_attr "mode" "DF")
5057 (set_attr "athlon_decode" "double,direct")
5058 (set_attr "fp_int_src" "true")])
5060 (define_insn "floathixf2"
5061 [(set (match_operand:XF 0 "register_operand" "=f,f")
5062 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5063 "!TARGET_64BIT && TARGET_80387"
5067 [(set_attr "type" "fmov,multi")
5068 (set_attr "mode" "XF")
5069 (set_attr "fp_int_src" "true")])
5071 (define_insn "floathitf2"
5072 [(set (match_operand:TF 0 "register_operand" "=f,f")
5073 (float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5078 [(set_attr "type" "fmov,multi")
5079 (set_attr "mode" "XF")
5080 (set_attr "fp_int_src" "true")])
5082 (define_insn "floatsixf2"
5083 [(set (match_operand:XF 0 "register_operand" "=f,f")
5084 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5085 "!TARGET_64BIT && TARGET_80387"
5089 [(set_attr "type" "fmov,multi")
5090 (set_attr "mode" "XF")
5091 (set_attr "fp_int_src" "true")])
5093 (define_insn "floatsitf2"
5094 [(set (match_operand:TF 0 "register_operand" "=f,f")
5095 (float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5100 [(set_attr "type" "fmov,multi")
5101 (set_attr "mode" "XF")
5102 (set_attr "fp_int_src" "true")])
5104 (define_insn "floatdixf2"
5105 [(set (match_operand:XF 0 "register_operand" "=f,f")
5106 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5107 "!TARGET_64BIT && TARGET_80387"
5111 [(set_attr "type" "fmov,multi")
5112 (set_attr "mode" "XF")
5113 (set_attr "fp_int_src" "true")])
5115 (define_insn "floatditf2"
5116 [(set (match_operand:TF 0 "register_operand" "=f,f")
5117 (float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5122 [(set_attr "type" "fmov,multi")
5123 (set_attr "mode" "XF")
5124 (set_attr "fp_int_src" "true")])
5126 ;; %%% Kill these when reload knows how to do it.
5128 [(set (match_operand 0 "fp_register_operand" "")
5129 (float (match_operand 1 "register_operand" "")))]
5130 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
5133 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
5134 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
5135 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
5136 ix86_free_from_memory (GET_MODE (operands[1]));
5140 (define_expand "floatunssisf2"
5141 [(use (match_operand:SF 0 "register_operand" ""))
5142 (use (match_operand:SI 1 "register_operand" ""))]
5143 "TARGET_SSE && TARGET_SSE_MATH && !TARGET_64BIT"
5144 "x86_emit_floatuns (operands); DONE;")
5146 (define_expand "floatunsdisf2"
5147 [(use (match_operand:SF 0 "register_operand" ""))
5148 (use (match_operand:DI 1 "register_operand" ""))]
5149 "TARGET_SSE && TARGET_SSE_MATH && TARGET_64BIT"
5150 "x86_emit_floatuns (operands); DONE;")
5152 (define_expand "floatunsdidf2"
5153 [(use (match_operand:DF 0 "register_operand" ""))
5154 (use (match_operand:DI 1 "register_operand" ""))]
5155 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_64BIT"
5156 "x86_emit_floatuns (operands); DONE;")
5160 ;; %%% splits for addsidi3
5161 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
5162 ; (plus:DI (match_operand:DI 1 "general_operand" "")
5163 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
5165 (define_expand "adddi3"
5166 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5167 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5168 (match_operand:DI 2 "x86_64_general_operand" "")))
5169 (clobber (reg:CC 17))]
5171 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
5173 (define_insn "*adddi3_1"
5174 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
5175 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5176 (match_operand:DI 2 "general_operand" "roiF,riF")))
5177 (clobber (reg:CC 17))]
5178 "!TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5182 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5183 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5184 (match_operand:DI 2 "general_operand" "")))
5185 (clobber (reg:CC 17))]
5186 "!TARGET_64BIT && reload_completed"
5187 [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)]
5189 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
5190 (parallel [(set (match_dup 3)
5191 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5194 (clobber (reg:CC 17))])]
5195 "split_di (operands+0, 1, operands+0, operands+3);
5196 split_di (operands+1, 1, operands+1, operands+4);
5197 split_di (operands+2, 1, operands+2, operands+5);")
5199 (define_insn "adddi3_carry_rex64"
5200 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5201 (plus:DI (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
5202 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
5203 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
5204 (clobber (reg:CC 17))]
5205 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5206 "adc{q}\t{%2, %0|%0, %2}"
5207 [(set_attr "type" "alu")
5208 (set_attr "pent_pair" "pu")
5209 (set_attr "mode" "DI")
5210 (set_attr "ppro_uops" "few")])
5212 (define_insn "*adddi3_cc_rex64"
5214 (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
5215 (match_operand:DI 2 "x86_64_general_operand" "re,rm")]
5217 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5218 (plus:DI (match_dup 1) (match_dup 2)))]
5219 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5220 "add{q}\t{%2, %0|%0, %2}"
5221 [(set_attr "type" "alu")
5222 (set_attr "mode" "DI")])
5224 (define_insn "addqi3_carry"
5225 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm,r")
5226 (plus:QI (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
5227 (match_operand:QI 1 "nonimmediate_operand" "%0,0"))
5228 (match_operand:QI 2 "general_operand" "ri,rm")))
5229 (clobber (reg:CC 17))]
5230 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5231 "adc{b}\t{%2, %0|%0, %2}"
5232 [(set_attr "type" "alu")
5233 (set_attr "pent_pair" "pu")
5234 (set_attr "mode" "QI")
5235 (set_attr "ppro_uops" "few")])
5237 (define_insn "addhi3_carry"
5238 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
5239 (plus:HI (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
5240 (match_operand:HI 1 "nonimmediate_operand" "%0,0"))
5241 (match_operand:HI 2 "general_operand" "ri,rm")))
5242 (clobber (reg:CC 17))]
5243 "ix86_binary_operator_ok (PLUS, HImode, operands)"
5244 "adc{w}\t{%2, %0|%0, %2}"
5245 [(set_attr "type" "alu")
5246 (set_attr "pent_pair" "pu")
5247 (set_attr "mode" "HI")
5248 (set_attr "ppro_uops" "few")])
5250 (define_insn "addsi3_carry"
5251 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5252 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5253 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
5254 (match_operand:SI 2 "general_operand" "ri,rm")))
5255 (clobber (reg:CC 17))]
5256 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5257 "adc{l}\t{%2, %0|%0, %2}"
5258 [(set_attr "type" "alu")
5259 (set_attr "pent_pair" "pu")
5260 (set_attr "mode" "SI")
5261 (set_attr "ppro_uops" "few")])
5263 (define_insn "*addsi3_carry_zext"
5264 [(set (match_operand:DI 0 "register_operand" "=r")
5266 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5267 (match_operand:SI 1 "nonimmediate_operand" "%0"))
5268 (match_operand:SI 2 "general_operand" "rim"))))
5269 (clobber (reg:CC 17))]
5270 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5271 "adc{l}\t{%2, %k0|%k0, %2}"
5272 [(set_attr "type" "alu")
5273 (set_attr "pent_pair" "pu")
5274 (set_attr "mode" "SI")
5275 (set_attr "ppro_uops" "few")])
5277 (define_insn "*addsi3_cc"
5279 (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
5280 (match_operand:SI 2 "general_operand" "ri,rm")]
5282 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5283 (plus:SI (match_dup 1) (match_dup 2)))]
5284 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5285 "add{l}\t{%2, %0|%0, %2}"
5286 [(set_attr "type" "alu")
5287 (set_attr "mode" "SI")])
5289 (define_insn "addqi3_cc"
5291 (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5292 (match_operand:QI 2 "general_operand" "qi,qm")]
5294 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5295 (plus:QI (match_dup 1) (match_dup 2)))]
5296 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5297 "add{b}\t{%2, %0|%0, %2}"
5298 [(set_attr "type" "alu")
5299 (set_attr "mode" "QI")])
5301 (define_expand "addsi3"
5302 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
5303 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5304 (match_operand:SI 2 "general_operand" "")))
5305 (clobber (reg:CC 17))])]
5307 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
5309 (define_insn "*lea_1"
5310 [(set (match_operand:SI 0 "register_operand" "=r")
5311 (match_operand:SI 1 "address_operand" "p"))]
5313 "lea{l}\t{%a1, %0|%0, %a1}"
5314 [(set_attr "type" "lea")
5315 (set_attr "mode" "SI")])
5317 (define_insn "*lea_1_rex64"
5318 [(set (match_operand:SI 0 "register_operand" "=r")
5319 (subreg:SI (match_operand:DI 1 "address_operand" "p") 0))]
5321 "lea{l}\t{%a1, %0|%0, %a1}"
5322 [(set_attr "type" "lea")
5323 (set_attr "mode" "SI")])
5325 (define_insn "*lea_1_zext"
5326 [(set (match_operand:DI 0 "register_operand" "=r")
5327 (zero_extend:DI (subreg:SI (match_operand:DI 1 "address_operand" "p") 0)))]
5329 "lea{l}\t{%a1, %k0|%k0, %a1}"
5330 [(set_attr "type" "lea")
5331 (set_attr "mode" "SI")])
5333 (define_insn "*lea_2_rex64"
5334 [(set (match_operand:DI 0 "register_operand" "=r")
5335 (match_operand:DI 1 "address_operand" "p"))]
5337 "lea{q}\t{%a1, %0|%0, %a1}"
5338 [(set_attr "type" "lea")
5339 (set_attr "mode" "DI")])
5341 ;; The lea patterns for non-Pmodes needs to be matched by several
5342 ;; insns converted to real lea by splitters.
5344 (define_insn_and_split "*lea_general_1"
5345 [(set (match_operand 0 "register_operand" "=r")
5346 (plus (plus (match_operand 1 "index_register_operand" "r")
5347 (match_operand 2 "register_operand" "r"))
5348 (match_operand 3 "immediate_operand" "i")))]
5349 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5350 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5351 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5352 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5353 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5354 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5355 || GET_MODE (operands[3]) == VOIDmode)"
5357 "&& reload_completed"
5361 operands[0] = gen_lowpart (SImode, operands[0]);
5362 operands[1] = gen_lowpart (Pmode, operands[1]);
5363 operands[2] = gen_lowpart (Pmode, operands[2]);
5364 operands[3] = gen_lowpart (Pmode, operands[3]);
5365 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
5367 if (Pmode != SImode)
5368 pat = gen_rtx_SUBREG (SImode, pat, 0);
5369 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5372 [(set_attr "type" "lea")
5373 (set_attr "mode" "SI")])
5375 (define_insn_and_split "*lea_general_1_zext"
5376 [(set (match_operand:DI 0 "register_operand" "=r")
5378 (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "r")
5379 (match_operand:SI 2 "register_operand" "r"))
5380 (match_operand:SI 3 "immediate_operand" "i"))))]
5383 "&& reload_completed"
5385 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
5387 (match_dup 3)) 0)))]
5389 operands[1] = gen_lowpart (Pmode, operands[1]);
5390 operands[2] = gen_lowpart (Pmode, operands[2]);
5391 operands[3] = gen_lowpart (Pmode, operands[3]);
5393 [(set_attr "type" "lea")
5394 (set_attr "mode" "SI")])
5396 (define_insn_and_split "*lea_general_2"
5397 [(set (match_operand 0 "register_operand" "=r")
5398 (plus (mult (match_operand 1 "index_register_operand" "r")
5399 (match_operand 2 "const248_operand" "i"))
5400 (match_operand 3 "nonmemory_operand" "ri")))]
5401 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5402 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5403 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5404 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5405 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5406 || GET_MODE (operands[3]) == VOIDmode)"
5408 "&& reload_completed"
5412 operands[0] = gen_lowpart (SImode, operands[0]);
5413 operands[1] = gen_lowpart (Pmode, operands[1]);
5414 operands[3] = gen_lowpart (Pmode, operands[3]);
5415 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
5417 if (Pmode != SImode)
5418 pat = gen_rtx_SUBREG (SImode, pat, 0);
5419 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5422 [(set_attr "type" "lea")
5423 (set_attr "mode" "SI")])
5425 (define_insn_and_split "*lea_general_2_zext"
5426 [(set (match_operand:DI 0 "register_operand" "=r")
5428 (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
5429 (match_operand:SI 2 "const248_operand" "n"))
5430 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
5433 "&& reload_completed"
5435 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
5437 (match_dup 3)) 0)))]
5439 operands[1] = gen_lowpart (Pmode, operands[1]);
5440 operands[3] = gen_lowpart (Pmode, operands[3]);
5442 [(set_attr "type" "lea")
5443 (set_attr "mode" "SI")])
5445 (define_insn_and_split "*lea_general_3"
5446 [(set (match_operand 0 "register_operand" "=r")
5447 (plus (plus (mult (match_operand 1 "index_register_operand" "r")
5448 (match_operand 2 "const248_operand" "i"))
5449 (match_operand 3 "register_operand" "r"))
5450 (match_operand 4 "immediate_operand" "i")))]
5451 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5452 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5453 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5454 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5455 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
5457 "&& reload_completed"
5461 operands[0] = gen_lowpart (SImode, operands[0]);
5462 operands[1] = gen_lowpart (Pmode, operands[1]);
5463 operands[3] = gen_lowpart (Pmode, operands[3]);
5464 operands[4] = gen_lowpart (Pmode, operands[4]);
5465 pat = gen_rtx_PLUS (Pmode,
5466 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
5470 if (Pmode != SImode)
5471 pat = gen_rtx_SUBREG (SImode, pat, 0);
5472 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5475 [(set_attr "type" "lea")
5476 (set_attr "mode" "SI")])
5478 (define_insn_and_split "*lea_general_3_zext"
5479 [(set (match_operand:DI 0 "register_operand" "=r")
5481 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
5482 (match_operand:SI 2 "const248_operand" "n"))
5483 (match_operand:SI 3 "register_operand" "r"))
5484 (match_operand:SI 4 "immediate_operand" "i"))))]
5487 "&& reload_completed"
5489 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
5492 (match_dup 4)) 0)))]
5494 operands[1] = gen_lowpart (Pmode, operands[1]);
5495 operands[3] = gen_lowpart (Pmode, operands[3]);
5496 operands[4] = gen_lowpart (Pmode, operands[4]);
5498 [(set_attr "type" "lea")
5499 (set_attr "mode" "SI")])
5501 (define_insn "*adddi_1_rex64"
5502 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5503 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5504 (match_operand:DI 2 "x86_64_general_operand" "rme,re,re")))
5505 (clobber (reg:CC 17))]
5506 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5508 switch (get_attr_type (insn))
5511 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5512 return "lea{q}\t{%a2, %0|%0, %a2}";
5515 if (! rtx_equal_p (operands[0], operands[1]))
5517 if (operands[2] == const1_rtx)
5518 return "inc{q}\t%0";
5519 else if (operands[2] == constm1_rtx)
5520 return "dec{q}\t%0";
5525 if (! rtx_equal_p (operands[0], operands[1]))
5528 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5529 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5530 if (GET_CODE (operands[2]) == CONST_INT
5531 /* Avoid overflows. */
5532 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5533 && (INTVAL (operands[2]) == 128
5534 || (INTVAL (operands[2]) < 0
5535 && INTVAL (operands[2]) != -128)))
5537 operands[2] = GEN_INT (-INTVAL (operands[2]));
5538 return "sub{q}\t{%2, %0|%0, %2}";
5540 return "add{q}\t{%2, %0|%0, %2}";
5544 (cond [(eq_attr "alternative" "2")
5545 (const_string "lea")
5546 ; Current assemblers are broken and do not allow @GOTOFF in
5547 ; ought but a memory context.
5548 (match_operand:DI 2 "pic_symbolic_operand" "")
5549 (const_string "lea")
5550 (match_operand:DI 2 "incdec_operand" "")
5551 (const_string "incdec")
5553 (const_string "alu")))
5554 (set_attr "mode" "DI")])
5556 ;; Convert lea to the lea pattern to avoid flags dependency.
5558 [(set (match_operand:DI 0 "register_operand" "")
5559 (plus:DI (match_operand:DI 1 "register_operand" "")
5560 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5561 (clobber (reg:CC 17))]
5562 "TARGET_64BIT && reload_completed
5563 && true_regnum (operands[0]) != true_regnum (operands[1])"
5565 (plus:DI (match_dup 1)
5569 (define_insn "*adddi_2_rex64"
5572 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5573 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5575 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5576 (plus:DI (match_dup 1) (match_dup 2)))]
5577 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5578 && ix86_binary_operator_ok (PLUS, DImode, operands)
5579 /* Current assemblers are broken and do not allow @GOTOFF in
5580 ought but a memory context. */
5581 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5583 switch (get_attr_type (insn))
5586 if (! rtx_equal_p (operands[0], operands[1]))
5588 if (operands[2] == const1_rtx)
5589 return "inc{q}\t%0";
5590 else if (operands[2] == constm1_rtx)
5591 return "dec{q}\t%0";
5596 if (! rtx_equal_p (operands[0], operands[1]))
5598 /* ???? We ought to handle there the 32bit case too
5599 - do we need new constraint? */
5600 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5601 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5602 if (GET_CODE (operands[2]) == CONST_INT
5603 /* Avoid overflows. */
5604 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5605 && (INTVAL (operands[2]) == 128
5606 || (INTVAL (operands[2]) < 0
5607 && INTVAL (operands[2]) != -128)))
5609 operands[2] = GEN_INT (-INTVAL (operands[2]));
5610 return "sub{q}\t{%2, %0|%0, %2}";
5612 return "add{q}\t{%2, %0|%0, %2}";
5616 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5617 (const_string "incdec")
5618 (const_string "alu")))
5619 (set_attr "mode" "DI")])
5621 (define_insn "*adddi_3_rex64"
5623 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5624 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5625 (clobber (match_scratch:DI 0 "=r"))]
5627 && ix86_match_ccmode (insn, CCZmode)
5628 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5629 /* Current assemblers are broken and do not allow @GOTOFF in
5630 ought but a memory context. */
5631 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5633 switch (get_attr_type (insn))
5636 if (! rtx_equal_p (operands[0], operands[1]))
5638 if (operands[2] == const1_rtx)
5639 return "inc{q}\t%0";
5640 else if (operands[2] == constm1_rtx)
5641 return "dec{q}\t%0";
5646 if (! rtx_equal_p (operands[0], operands[1]))
5648 /* ???? We ought to handle there the 32bit case too
5649 - do we need new constraint? */
5650 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5651 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5652 if (GET_CODE (operands[2]) == CONST_INT
5653 /* Avoid overflows. */
5654 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5655 && (INTVAL (operands[2]) == 128
5656 || (INTVAL (operands[2]) < 0
5657 && INTVAL (operands[2]) != -128)))
5659 operands[2] = GEN_INT (-INTVAL (operands[2]));
5660 return "sub{q}\t{%2, %0|%0, %2}";
5662 return "add{q}\t{%2, %0|%0, %2}";
5666 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5667 (const_string "incdec")
5668 (const_string "alu")))
5669 (set_attr "mode" "DI")])
5671 ; For comparisons against 1, -1 and 128, we may generate better code
5672 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5673 ; is matched then. We can't accept general immediate, because for
5674 ; case of overflows, the result is messed up.
5675 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5677 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5678 ; only for comparisons not depending on it.
5679 (define_insn "*adddi_4_rex64"
5681 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5682 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5683 (clobber (match_scratch:DI 0 "=rm"))]
5685 && ix86_match_ccmode (insn, CCGCmode)"
5687 switch (get_attr_type (insn))
5690 if (operands[2] == constm1_rtx)
5691 return "inc{q}\t%0";
5692 else if (operands[2] == const1_rtx)
5693 return "dec{q}\t%0";
5698 if (! rtx_equal_p (operands[0], operands[1]))
5700 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5701 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5702 if ((INTVAL (operands[2]) == -128
5703 || (INTVAL (operands[2]) > 0
5704 && INTVAL (operands[2]) != 128))
5705 /* Avoid overflows. */
5706 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
5707 return "sub{q}\t{%2, %0|%0, %2}";
5708 operands[2] = GEN_INT (-INTVAL (operands[2]));
5709 return "add{q}\t{%2, %0|%0, %2}";
5713 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5714 (const_string "incdec")
5715 (const_string "alu")))
5716 (set_attr "mode" "DI")])
5718 (define_insn "*adddi_5_rex64"
5721 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5722 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5724 (clobber (match_scratch:DI 0 "=r"))]
5726 && ix86_match_ccmode (insn, CCGOCmode)
5727 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5728 /* Current assemblers are broken and do not allow @GOTOFF in
5729 ought but a memory context. */
5730 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5732 switch (get_attr_type (insn))
5735 if (! rtx_equal_p (operands[0], operands[1]))
5737 if (operands[2] == const1_rtx)
5738 return "inc{q}\t%0";
5739 else if (operands[2] == constm1_rtx)
5740 return "dec{q}\t%0";
5745 if (! rtx_equal_p (operands[0], operands[1]))
5747 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5748 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5749 if (GET_CODE (operands[2]) == CONST_INT
5750 /* Avoid overflows. */
5751 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5752 && (INTVAL (operands[2]) == 128
5753 || (INTVAL (operands[2]) < 0
5754 && INTVAL (operands[2]) != -128)))
5756 operands[2] = GEN_INT (-INTVAL (operands[2]));
5757 return "sub{q}\t{%2, %0|%0, %2}";
5759 return "add{q}\t{%2, %0|%0, %2}";
5763 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5764 (const_string "incdec")
5765 (const_string "alu")))
5766 (set_attr "mode" "DI")])
5769 (define_insn "*addsi_1"
5770 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5771 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5772 (match_operand:SI 2 "general_operand" "rmni,rni,rni")))
5773 (clobber (reg:CC 17))]
5774 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5776 switch (get_attr_type (insn))
5779 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5780 return "lea{l}\t{%a2, %0|%0, %a2}";
5783 if (! rtx_equal_p (operands[0], operands[1]))
5785 if (operands[2] == const1_rtx)
5786 return "inc{l}\t%0";
5787 else if (operands[2] == constm1_rtx)
5788 return "dec{l}\t%0";
5793 if (! rtx_equal_p (operands[0], operands[1]))
5796 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5797 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5798 if (GET_CODE (operands[2]) == CONST_INT
5799 && (INTVAL (operands[2]) == 128
5800 || (INTVAL (operands[2]) < 0
5801 && INTVAL (operands[2]) != -128)))
5803 operands[2] = GEN_INT (-INTVAL (operands[2]));
5804 return "sub{l}\t{%2, %0|%0, %2}";
5806 return "add{l}\t{%2, %0|%0, %2}";
5810 (cond [(eq_attr "alternative" "2")
5811 (const_string "lea")
5812 ; Current assemblers are broken and do not allow @GOTOFF in
5813 ; ought but a memory context.
5814 (match_operand:SI 2 "pic_symbolic_operand" "")
5815 (const_string "lea")
5816 (match_operand:SI 2 "incdec_operand" "")
5817 (const_string "incdec")
5819 (const_string "alu")))
5820 (set_attr "mode" "SI")])
5822 ;; Convert lea to the lea pattern to avoid flags dependency.
5824 [(set (match_operand 0 "register_operand" "")
5825 (plus (match_operand 1 "register_operand" "")
5826 (match_operand 2 "nonmemory_operand" "")))
5827 (clobber (reg:CC 17))]
5829 && true_regnum (operands[0]) != true_regnum (operands[1])"
5833 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5834 may confuse gen_lowpart. */
5835 if (GET_MODE (operands[0]) != Pmode)
5837 operands[1] = gen_lowpart (Pmode, operands[1]);
5838 operands[2] = gen_lowpart (Pmode, operands[2]);
5840 operands[0] = gen_lowpart (SImode, operands[0]);
5841 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5842 if (Pmode != SImode)
5843 pat = gen_rtx_SUBREG (SImode, pat, 0);
5844 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5848 ;; It may seem that nonimmediate operand is proper one for operand 1.
5849 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5850 ;; we take care in ix86_binary_operator_ok to not allow two memory
5851 ;; operands so proper swapping will be done in reload. This allow
5852 ;; patterns constructed from addsi_1 to match.
5853 (define_insn "addsi_1_zext"
5854 [(set (match_operand:DI 0 "register_operand" "=r,r")
5856 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5857 (match_operand:SI 2 "general_operand" "rmni,rni"))))
5858 (clobber (reg:CC 17))]
5859 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5861 switch (get_attr_type (insn))
5864 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5865 return "lea{l}\t{%a2, %k0|%k0, %a2}";
5868 if (operands[2] == const1_rtx)
5869 return "inc{l}\t%k0";
5870 else if (operands[2] == constm1_rtx)
5871 return "dec{l}\t%k0";
5876 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5877 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5878 if (GET_CODE (operands[2]) == CONST_INT
5879 && (INTVAL (operands[2]) == 128
5880 || (INTVAL (operands[2]) < 0
5881 && INTVAL (operands[2]) != -128)))
5883 operands[2] = GEN_INT (-INTVAL (operands[2]));
5884 return "sub{l}\t{%2, %k0|%k0, %2}";
5886 return "add{l}\t{%2, %k0|%k0, %2}";
5890 (cond [(eq_attr "alternative" "1")
5891 (const_string "lea")
5892 ; Current assemblers are broken and do not allow @GOTOFF in
5893 ; ought but a memory context.
5894 (match_operand:SI 2 "pic_symbolic_operand" "")
5895 (const_string "lea")
5896 (match_operand:SI 2 "incdec_operand" "")
5897 (const_string "incdec")
5899 (const_string "alu")))
5900 (set_attr "mode" "SI")])
5902 ;; Convert lea to the lea pattern to avoid flags dependency.
5904 [(set (match_operand:DI 0 "register_operand" "")
5906 (plus:SI (match_operand:SI 1 "register_operand" "")
5907 (match_operand:SI 2 "nonmemory_operand" ""))))
5908 (clobber (reg:CC 17))]
5909 "TARGET_64BIT && reload_completed
5910 && true_regnum (operands[0]) != true_regnum (operands[1])"
5912 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
5914 operands[1] = gen_lowpart (Pmode, operands[1]);
5915 operands[2] = gen_lowpart (Pmode, operands[2]);
5918 (define_insn "*addsi_2"
5921 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5922 (match_operand:SI 2 "general_operand" "rmni,rni"))
5924 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
5925 (plus:SI (match_dup 1) (match_dup 2)))]
5926 "ix86_match_ccmode (insn, CCGOCmode)
5927 && ix86_binary_operator_ok (PLUS, SImode, operands)
5928 /* Current assemblers are broken and do not allow @GOTOFF in
5929 ought but a memory context. */
5930 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5932 switch (get_attr_type (insn))
5935 if (! rtx_equal_p (operands[0], operands[1]))
5937 if (operands[2] == const1_rtx)
5938 return "inc{l}\t%0";
5939 else if (operands[2] == constm1_rtx)
5940 return "dec{l}\t%0";
5945 if (! rtx_equal_p (operands[0], operands[1]))
5947 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5948 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5949 if (GET_CODE (operands[2]) == CONST_INT
5950 && (INTVAL (operands[2]) == 128
5951 || (INTVAL (operands[2]) < 0
5952 && INTVAL (operands[2]) != -128)))
5954 operands[2] = GEN_INT (-INTVAL (operands[2]));
5955 return "sub{l}\t{%2, %0|%0, %2}";
5957 return "add{l}\t{%2, %0|%0, %2}";
5961 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5962 (const_string "incdec")
5963 (const_string "alu")))
5964 (set_attr "mode" "SI")])
5966 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5967 (define_insn "*addsi_2_zext"
5970 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5971 (match_operand:SI 2 "general_operand" "rmni"))
5973 (set (match_operand:DI 0 "register_operand" "=r")
5974 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5975 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5976 && ix86_binary_operator_ok (PLUS, SImode, operands)
5977 /* Current assemblers are broken and do not allow @GOTOFF in
5978 ought but a memory context. */
5979 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5981 switch (get_attr_type (insn))
5984 if (operands[2] == const1_rtx)
5985 return "inc{l}\t%k0";
5986 else if (operands[2] == constm1_rtx)
5987 return "dec{l}\t%k0";
5992 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5993 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5994 if (GET_CODE (operands[2]) == CONST_INT
5995 && (INTVAL (operands[2]) == 128
5996 || (INTVAL (operands[2]) < 0
5997 && INTVAL (operands[2]) != -128)))
5999 operands[2] = GEN_INT (-INTVAL (operands[2]));
6000 return "sub{l}\t{%2, %k0|%k0, %2}";
6002 return "add{l}\t{%2, %k0|%k0, %2}";
6006 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6007 (const_string "incdec")
6008 (const_string "alu")))
6009 (set_attr "mode" "SI")])
6011 (define_insn "*addsi_3"
6013 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
6014 (match_operand:SI 1 "nonimmediate_operand" "%0")))
6015 (clobber (match_scratch:SI 0 "=r"))]
6016 "ix86_match_ccmode (insn, CCZmode)
6017 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
6018 /* Current assemblers are broken and do not allow @GOTOFF in
6019 ought but a memory context. */
6020 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6022 switch (get_attr_type (insn))
6025 if (! rtx_equal_p (operands[0], operands[1]))
6027 if (operands[2] == const1_rtx)
6028 return "inc{l}\t%0";
6029 else if (operands[2] == constm1_rtx)
6030 return "dec{l}\t%0";
6035 if (! rtx_equal_p (operands[0], operands[1]))
6037 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6038 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6039 if (GET_CODE (operands[2]) == CONST_INT
6040 && (INTVAL (operands[2]) == 128
6041 || (INTVAL (operands[2]) < 0
6042 && INTVAL (operands[2]) != -128)))
6044 operands[2] = GEN_INT (-INTVAL (operands[2]));
6045 return "sub{l}\t{%2, %0|%0, %2}";
6047 return "add{l}\t{%2, %0|%0, %2}";
6051 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6052 (const_string "incdec")
6053 (const_string "alu")))
6054 (set_attr "mode" "SI")])
6056 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
6057 (define_insn "*addsi_3_zext"
6059 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
6060 (match_operand:SI 1 "nonimmediate_operand" "%0")))
6061 (set (match_operand:DI 0 "register_operand" "=r")
6062 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
6063 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
6064 && ix86_binary_operator_ok (PLUS, SImode, operands)
6065 /* Current assemblers are broken and do not allow @GOTOFF in
6066 ought but a memory context. */
6067 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6069 switch (get_attr_type (insn))
6072 if (operands[2] == const1_rtx)
6073 return "inc{l}\t%k0";
6074 else if (operands[2] == constm1_rtx)
6075 return "dec{l}\t%k0";
6080 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6081 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6082 if (GET_CODE (operands[2]) == CONST_INT
6083 && (INTVAL (operands[2]) == 128
6084 || (INTVAL (operands[2]) < 0
6085 && INTVAL (operands[2]) != -128)))
6087 operands[2] = GEN_INT (-INTVAL (operands[2]));
6088 return "sub{l}\t{%2, %k0|%k0, %2}";
6090 return "add{l}\t{%2, %k0|%k0, %2}";
6094 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6095 (const_string "incdec")
6096 (const_string "alu")))
6097 (set_attr "mode" "SI")])
6099 ; For comparisons against 1, -1 and 128, we may generate better code
6100 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
6101 ; is matched then. We can't accept general immediate, because for
6102 ; case of overflows, the result is messed up.
6103 ; This pattern also don't hold of 0x80000000, since the value overflows
6105 ; Also carry flag is reversed compared to cmp, so this conversion is valid
6106 ; only for comparisons not depending on it.
6107 (define_insn "*addsi_4"
6109 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
6110 (match_operand:SI 2 "const_int_operand" "n")))
6111 (clobber (match_scratch:SI 0 "=rm"))]
6112 "ix86_match_ccmode (insn, CCGCmode)
6113 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
6115 switch (get_attr_type (insn))
6118 if (operands[2] == constm1_rtx)
6119 return "inc{l}\t%0";
6120 else if (operands[2] == const1_rtx)
6121 return "dec{l}\t%0";
6126 if (! rtx_equal_p (operands[0], operands[1]))
6128 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6129 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6130 if ((INTVAL (operands[2]) == -128
6131 || (INTVAL (operands[2]) > 0
6132 && INTVAL (operands[2]) != 128)))
6133 return "sub{l}\t{%2, %0|%0, %2}";
6134 operands[2] = GEN_INT (-INTVAL (operands[2]));
6135 return "add{l}\t{%2, %0|%0, %2}";
6139 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6140 (const_string "incdec")
6141 (const_string "alu")))
6142 (set_attr "mode" "SI")])
6144 (define_insn "*addsi_5"
6147 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
6148 (match_operand:SI 2 "general_operand" "rmni"))
6150 (clobber (match_scratch:SI 0 "=r"))]
6151 "ix86_match_ccmode (insn, CCGOCmode)
6152 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
6153 /* Current assemblers are broken and do not allow @GOTOFF in
6154 ought but a memory context. */
6155 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6157 switch (get_attr_type (insn))
6160 if (! rtx_equal_p (operands[0], operands[1]))
6162 if (operands[2] == const1_rtx)
6163 return "inc{l}\t%0";
6164 else if (operands[2] == constm1_rtx)
6165 return "dec{l}\t%0";
6170 if (! rtx_equal_p (operands[0], operands[1]))
6172 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6173 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6174 if (GET_CODE (operands[2]) == CONST_INT
6175 && (INTVAL (operands[2]) == 128
6176 || (INTVAL (operands[2]) < 0
6177 && INTVAL (operands[2]) != -128)))
6179 operands[2] = GEN_INT (-INTVAL (operands[2]));
6180 return "sub{l}\t{%2, %0|%0, %2}";
6182 return "add{l}\t{%2, %0|%0, %2}";
6186 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6187 (const_string "incdec")
6188 (const_string "alu")))
6189 (set_attr "mode" "SI")])
6191 (define_expand "addhi3"
6192 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6193 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6194 (match_operand:HI 2 "general_operand" "")))
6195 (clobber (reg:CC 17))])]
6196 "TARGET_HIMODE_MATH"
6197 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
6199 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
6200 ;; type optimizations enabled by define-splits. This is not important
6201 ;; for PII, and in fact harmful because of partial register stalls.
6203 (define_insn "*addhi_1_lea"
6204 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
6205 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
6206 (match_operand:HI 2 "general_operand" "ri,rm,rni")))
6207 (clobber (reg:CC 17))]
6208 "!TARGET_PARTIAL_REG_STALL
6209 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6211 switch (get_attr_type (insn))
6216 if (operands[2] == const1_rtx)
6217 return "inc{w}\t%0";
6218 else if (operands[2] == constm1_rtx)
6219 return "dec{w}\t%0";
6223 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6224 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6225 if (GET_CODE (operands[2]) == CONST_INT
6226 && (INTVAL (operands[2]) == 128
6227 || (INTVAL (operands[2]) < 0
6228 && INTVAL (operands[2]) != -128)))
6230 operands[2] = GEN_INT (-INTVAL (operands[2]));
6231 return "sub{w}\t{%2, %0|%0, %2}";
6233 return "add{w}\t{%2, %0|%0, %2}";
6237 (if_then_else (eq_attr "alternative" "2")
6238 (const_string "lea")
6239 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6240 (const_string "incdec")
6241 (const_string "alu"))))
6242 (set_attr "mode" "HI,HI,SI")])
6244 (define_insn "*addhi_1"
6245 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6246 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6247 (match_operand:HI 2 "general_operand" "ri,rm")))
6248 (clobber (reg:CC 17))]
6249 "TARGET_PARTIAL_REG_STALL
6250 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6252 switch (get_attr_type (insn))
6255 if (operands[2] == const1_rtx)
6256 return "inc{w}\t%0";
6257 else if (operands[2] == constm1_rtx)
6258 return "dec{w}\t%0";
6262 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6263 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6264 if (GET_CODE (operands[2]) == CONST_INT
6265 && (INTVAL (operands[2]) == 128
6266 || (INTVAL (operands[2]) < 0
6267 && INTVAL (operands[2]) != -128)))
6269 operands[2] = GEN_INT (-INTVAL (operands[2]));
6270 return "sub{w}\t{%2, %0|%0, %2}";
6272 return "add{w}\t{%2, %0|%0, %2}";
6276 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6277 (const_string "incdec")
6278 (const_string "alu")))
6279 (set_attr "mode" "HI")])
6281 (define_insn "*addhi_2"
6284 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6285 (match_operand:HI 2 "general_operand" "rmni,rni"))
6287 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6288 (plus:HI (match_dup 1) (match_dup 2)))]
6289 "ix86_match_ccmode (insn, CCGOCmode)
6290 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6292 switch (get_attr_type (insn))
6295 if (operands[2] == const1_rtx)
6296 return "inc{w}\t%0";
6297 else if (operands[2] == constm1_rtx)
6298 return "dec{w}\t%0";
6302 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6303 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6304 if (GET_CODE (operands[2]) == CONST_INT
6305 && (INTVAL (operands[2]) == 128
6306 || (INTVAL (operands[2]) < 0
6307 && INTVAL (operands[2]) != -128)))
6309 operands[2] = GEN_INT (-INTVAL (operands[2]));
6310 return "sub{w}\t{%2, %0|%0, %2}";
6312 return "add{w}\t{%2, %0|%0, %2}";
6316 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6317 (const_string "incdec")
6318 (const_string "alu")))
6319 (set_attr "mode" "HI")])
6321 (define_insn "*addhi_3"
6323 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
6324 (match_operand:HI 1 "nonimmediate_operand" "%0")))
6325 (clobber (match_scratch:HI 0 "=r"))]
6326 "ix86_match_ccmode (insn, CCZmode)
6327 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6329 switch (get_attr_type (insn))
6332 if (operands[2] == const1_rtx)
6333 return "inc{w}\t%0";
6334 else if (operands[2] == constm1_rtx)
6335 return "dec{w}\t%0";
6339 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6340 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6341 if (GET_CODE (operands[2]) == CONST_INT
6342 && (INTVAL (operands[2]) == 128
6343 || (INTVAL (operands[2]) < 0
6344 && INTVAL (operands[2]) != -128)))
6346 operands[2] = GEN_INT (-INTVAL (operands[2]));
6347 return "sub{w}\t{%2, %0|%0, %2}";
6349 return "add{w}\t{%2, %0|%0, %2}";
6353 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6354 (const_string "incdec")
6355 (const_string "alu")))
6356 (set_attr "mode" "HI")])
6358 ; See comments above addsi_3_imm for details.
6359 (define_insn "*addhi_4"
6361 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
6362 (match_operand:HI 2 "const_int_operand" "n")))
6363 (clobber (match_scratch:HI 0 "=rm"))]
6364 "ix86_match_ccmode (insn, CCGCmode)
6365 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
6367 switch (get_attr_type (insn))
6370 if (operands[2] == constm1_rtx)
6371 return "inc{w}\t%0";
6372 else if (operands[2] == const1_rtx)
6373 return "dec{w}\t%0";
6378 if (! rtx_equal_p (operands[0], operands[1]))
6380 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6381 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6382 if ((INTVAL (operands[2]) == -128
6383 || (INTVAL (operands[2]) > 0
6384 && INTVAL (operands[2]) != 128)))
6385 return "sub{w}\t{%2, %0|%0, %2}";
6386 operands[2] = GEN_INT (-INTVAL (operands[2]));
6387 return "add{w}\t{%2, %0|%0, %2}";
6391 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6392 (const_string "incdec")
6393 (const_string "alu")))
6394 (set_attr "mode" "SI")])
6397 (define_insn "*addhi_5"
6400 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
6401 (match_operand:HI 2 "general_operand" "rmni"))
6403 (clobber (match_scratch:HI 0 "=r"))]
6404 "ix86_match_ccmode (insn, CCGOCmode)
6405 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6407 switch (get_attr_type (insn))
6410 if (operands[2] == const1_rtx)
6411 return "inc{w}\t%0";
6412 else if (operands[2] == constm1_rtx)
6413 return "dec{w}\t%0";
6417 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6418 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6419 if (GET_CODE (operands[2]) == CONST_INT
6420 && (INTVAL (operands[2]) == 128
6421 || (INTVAL (operands[2]) < 0
6422 && INTVAL (operands[2]) != -128)))
6424 operands[2] = GEN_INT (-INTVAL (operands[2]));
6425 return "sub{w}\t{%2, %0|%0, %2}";
6427 return "add{w}\t{%2, %0|%0, %2}";
6431 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6432 (const_string "incdec")
6433 (const_string "alu")))
6434 (set_attr "mode" "HI")])
6436 (define_expand "addqi3"
6437 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6438 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6439 (match_operand:QI 2 "general_operand" "")))
6440 (clobber (reg:CC 17))])]
6441 "TARGET_QIMODE_MATH"
6442 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
6444 ;; %%% Potential partial reg stall on alternative 2. What to do?
6445 (define_insn "*addqi_1_lea"
6446 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
6447 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
6448 (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
6449 (clobber (reg:CC 17))]
6450 "!TARGET_PARTIAL_REG_STALL
6451 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6453 int widen = (which_alternative == 2);
6454 switch (get_attr_type (insn))
6459 if (operands[2] == const1_rtx)
6460 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6461 else if (operands[2] == constm1_rtx)
6462 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6466 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6467 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6468 if (GET_CODE (operands[2]) == CONST_INT
6469 && (INTVAL (operands[2]) == 128
6470 || (INTVAL (operands[2]) < 0
6471 && INTVAL (operands[2]) != -128)))
6473 operands[2] = GEN_INT (-INTVAL (operands[2]));
6475 return "sub{l}\t{%2, %k0|%k0, %2}";
6477 return "sub{b}\t{%2, %0|%0, %2}";
6480 return "add{l}\t{%k2, %k0|%k0, %k2}";
6482 return "add{b}\t{%2, %0|%0, %2}";
6486 (if_then_else (eq_attr "alternative" "3")
6487 (const_string "lea")
6488 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6489 (const_string "incdec")
6490 (const_string "alu"))))
6491 (set_attr "mode" "QI,QI,SI,SI")])
6493 (define_insn "*addqi_1"
6494 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
6495 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6496 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
6497 (clobber (reg:CC 17))]
6498 "TARGET_PARTIAL_REG_STALL
6499 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6501 int widen = (which_alternative == 2);
6502 switch (get_attr_type (insn))
6505 if (operands[2] == const1_rtx)
6506 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6507 else if (operands[2] == constm1_rtx)
6508 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6512 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6513 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6514 if (GET_CODE (operands[2]) == CONST_INT
6515 && (INTVAL (operands[2]) == 128
6516 || (INTVAL (operands[2]) < 0
6517 && INTVAL (operands[2]) != -128)))
6519 operands[2] = GEN_INT (-INTVAL (operands[2]));
6521 return "sub{l}\t{%2, %k0|%k0, %2}";
6523 return "sub{b}\t{%2, %0|%0, %2}";
6526 return "add{l}\t{%k2, %k0|%k0, %k2}";
6528 return "add{b}\t{%2, %0|%0, %2}";
6532 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6533 (const_string "incdec")
6534 (const_string "alu")))
6535 (set_attr "mode" "QI,QI,SI")])
6537 (define_insn "*addqi_1_slp"
6538 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6539 (plus:QI (match_dup 0)
6540 (match_operand:QI 1 "general_operand" "qn,qnm")))
6541 (clobber (reg:CC 17))]
6542 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6543 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6545 switch (get_attr_type (insn))
6548 if (operands[1] == const1_rtx)
6549 return "inc{b}\t%0";
6550 else if (operands[1] == constm1_rtx)
6551 return "dec{b}\t%0";
6555 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */
6556 if (GET_CODE (operands[1]) == CONST_INT
6557 && INTVAL (operands[1]) < 0)
6559 operands[2] = GEN_INT (-INTVAL (operands[2]));
6560 return "sub{b}\t{%1, %0|%0, %1}";
6562 return "add{b}\t{%1, %0|%0, %1}";
6566 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6567 (const_string "incdec")
6568 (const_string "alu1")))
6569 (set_attr "mode" "QI")])
6571 (define_insn "*addqi_2"
6574 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6575 (match_operand:QI 2 "general_operand" "qmni,qni"))
6577 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6578 (plus:QI (match_dup 1) (match_dup 2)))]
6579 "ix86_match_ccmode (insn, CCGOCmode)
6580 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6582 switch (get_attr_type (insn))
6585 if (operands[2] == const1_rtx)
6586 return "inc{b}\t%0";
6587 else if (operands[2] == constm1_rtx
6588 || (GET_CODE (operands[2]) == CONST_INT
6589 && INTVAL (operands[2]) == 255))
6590 return "dec{b}\t%0";
6594 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6595 if (GET_CODE (operands[2]) == CONST_INT
6596 && INTVAL (operands[2]) < 0)
6598 operands[2] = GEN_INT (-INTVAL (operands[2]));
6599 return "sub{b}\t{%2, %0|%0, %2}";
6601 return "add{b}\t{%2, %0|%0, %2}";
6605 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6606 (const_string "incdec")
6607 (const_string "alu")))
6608 (set_attr "mode" "QI")])
6610 (define_insn "*addqi_3"
6612 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6613 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6614 (clobber (match_scratch:QI 0 "=q"))]
6615 "ix86_match_ccmode (insn, CCZmode)
6616 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6618 switch (get_attr_type (insn))
6621 if (operands[2] == const1_rtx)
6622 return "inc{b}\t%0";
6623 else if (operands[2] == constm1_rtx
6624 || (GET_CODE (operands[2]) == CONST_INT
6625 && INTVAL (operands[2]) == 255))
6626 return "dec{b}\t%0";
6630 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6631 if (GET_CODE (operands[2]) == CONST_INT
6632 && INTVAL (operands[2]) < 0)
6634 operands[2] = GEN_INT (-INTVAL (operands[2]));
6635 return "sub{b}\t{%2, %0|%0, %2}";
6637 return "add{b}\t{%2, %0|%0, %2}";
6641 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6642 (const_string "incdec")
6643 (const_string "alu")))
6644 (set_attr "mode" "QI")])
6646 ; See comments above addsi_3_imm for details.
6647 (define_insn "*addqi_4"
6649 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6650 (match_operand:QI 2 "const_int_operand" "n")))
6651 (clobber (match_scratch:QI 0 "=qm"))]
6652 "ix86_match_ccmode (insn, CCGCmode)
6653 && (INTVAL (operands[2]) & 0xff) != 0x80"
6655 switch (get_attr_type (insn))
6658 if (operands[2] == constm1_rtx
6659 || (GET_CODE (operands[2]) == CONST_INT
6660 && INTVAL (operands[2]) == 255))
6661 return "inc{b}\t%0";
6662 else if (operands[2] == const1_rtx)
6663 return "dec{b}\t%0";
6668 if (! rtx_equal_p (operands[0], operands[1]))
6670 if (INTVAL (operands[2]) < 0)
6672 operands[2] = GEN_INT (-INTVAL (operands[2]));
6673 return "add{b}\t{%2, %0|%0, %2}";
6675 return "sub{b}\t{%2, %0|%0, %2}";
6679 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6680 (const_string "incdec")
6681 (const_string "alu")))
6682 (set_attr "mode" "QI")])
6685 (define_insn "*addqi_5"
6688 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6689 (match_operand:QI 2 "general_operand" "qmni"))
6691 (clobber (match_scratch:QI 0 "=q"))]
6692 "ix86_match_ccmode (insn, CCGOCmode)
6693 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6695 switch (get_attr_type (insn))
6698 if (operands[2] == const1_rtx)
6699 return "inc{b}\t%0";
6700 else if (operands[2] == constm1_rtx
6701 || (GET_CODE (operands[2]) == CONST_INT
6702 && INTVAL (operands[2]) == 255))
6703 return "dec{b}\t%0";
6707 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6708 if (GET_CODE (operands[2]) == CONST_INT
6709 && INTVAL (operands[2]) < 0)
6711 operands[2] = GEN_INT (-INTVAL (operands[2]));
6712 return "sub{b}\t{%2, %0|%0, %2}";
6714 return "add{b}\t{%2, %0|%0, %2}";
6718 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6719 (const_string "incdec")
6720 (const_string "alu")))
6721 (set_attr "mode" "QI")])
6724 (define_insn "addqi_ext_1"
6725 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6730 (match_operand 1 "ext_register_operand" "0")
6733 (match_operand:QI 2 "general_operand" "Qmn")))
6734 (clobber (reg:CC 17))]
6737 switch (get_attr_type (insn))
6740 if (operands[2] == const1_rtx)
6741 return "inc{b}\t%h0";
6742 else if (operands[2] == constm1_rtx
6743 || (GET_CODE (operands[2]) == CONST_INT
6744 && INTVAL (operands[2]) == 255))
6745 return "dec{b}\t%h0";
6749 return "add{b}\t{%2, %h0|%h0, %2}";
6753 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6754 (const_string "incdec")
6755 (const_string "alu")))
6756 (set_attr "mode" "QI")])
6758 (define_insn "*addqi_ext_1_rex64"
6759 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6764 (match_operand 1 "ext_register_operand" "0")
6767 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6768 (clobber (reg:CC 17))]
6771 switch (get_attr_type (insn))
6774 if (operands[2] == const1_rtx)
6775 return "inc{b}\t%h0";
6776 else if (operands[2] == constm1_rtx
6777 || (GET_CODE (operands[2]) == CONST_INT
6778 && INTVAL (operands[2]) == 255))
6779 return "dec{b}\t%h0";
6783 return "add{b}\t{%2, %h0|%h0, %2}";
6787 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6788 (const_string "incdec")
6789 (const_string "alu")))
6790 (set_attr "mode" "QI")])
6792 (define_insn "*addqi_ext_2"
6793 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6798 (match_operand 1 "ext_register_operand" "%0")
6802 (match_operand 2 "ext_register_operand" "Q")
6805 (clobber (reg:CC 17))]
6807 "add{b}\t{%h2, %h0|%h0, %h2}"
6808 [(set_attr "type" "alu")
6809 (set_attr "mode" "QI")])
6811 ;; The patterns that match these are at the end of this file.
6813 (define_expand "addxf3"
6814 [(set (match_operand:XF 0 "register_operand" "")
6815 (plus:XF (match_operand:XF 1 "register_operand" "")
6816 (match_operand:XF 2 "register_operand" "")))]
6817 "!TARGET_64BIT && TARGET_80387"
6820 (define_expand "addtf3"
6821 [(set (match_operand:TF 0 "register_operand" "")
6822 (plus:TF (match_operand:TF 1 "register_operand" "")
6823 (match_operand:TF 2 "register_operand" "")))]
6827 (define_expand "adddf3"
6828 [(set (match_operand:DF 0 "register_operand" "")
6829 (plus:DF (match_operand:DF 1 "register_operand" "")
6830 (match_operand:DF 2 "nonimmediate_operand" "")))]
6831 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6834 (define_expand "addsf3"
6835 [(set (match_operand:SF 0 "register_operand" "")
6836 (plus:SF (match_operand:SF 1 "register_operand" "")
6837 (match_operand:SF 2 "nonimmediate_operand" "")))]
6838 "TARGET_80387 || TARGET_SSE_MATH"
6841 ;; Subtract instructions
6843 ;; %%% splits for subsidi3
6845 (define_expand "subdi3"
6846 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6847 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6848 (match_operand:DI 2 "x86_64_general_operand" "")))
6849 (clobber (reg:CC 17))])]
6851 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6853 (define_insn "*subdi3_1"
6854 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6855 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6856 (match_operand:DI 2 "general_operand" "roiF,riF")))
6857 (clobber (reg:CC 17))]
6858 "!TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6862 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6863 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6864 (match_operand:DI 2 "general_operand" "")))
6865 (clobber (reg:CC 17))]
6866 "!TARGET_64BIT && reload_completed"
6867 [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
6868 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6869 (parallel [(set (match_dup 3)
6870 (minus:SI (match_dup 4)
6871 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6873 (clobber (reg:CC 17))])]
6874 "split_di (operands+0, 1, operands+0, operands+3);
6875 split_di (operands+1, 1, operands+1, operands+4);
6876 split_di (operands+2, 1, operands+2, operands+5);")
6878 (define_insn "subdi3_carry_rex64"
6879 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6880 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6881 (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
6882 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6883 (clobber (reg:CC 17))]
6884 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6885 "sbb{q}\t{%2, %0|%0, %2}"
6886 [(set_attr "type" "alu")
6887 (set_attr "pent_pair" "pu")
6888 (set_attr "ppro_uops" "few")
6889 (set_attr "mode" "DI")])
6891 (define_insn "*subdi_1_rex64"
6892 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6893 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6894 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6895 (clobber (reg:CC 17))]
6896 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6897 "sub{q}\t{%2, %0|%0, %2}"
6898 [(set_attr "type" "alu")
6899 (set_attr "mode" "DI")])
6901 (define_insn "*subdi_2_rex64"
6904 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6905 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6907 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6908 (minus:DI (match_dup 1) (match_dup 2)))]
6909 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6910 && ix86_binary_operator_ok (MINUS, DImode, operands)"
6911 "sub{q}\t{%2, %0|%0, %2}"
6912 [(set_attr "type" "alu")
6913 (set_attr "mode" "DI")])
6915 (define_insn "*subdi_3_rex63"
6917 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
6918 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6919 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6920 (minus:DI (match_dup 1) (match_dup 2)))]
6921 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6922 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6923 "sub{q}\t{%2, %0|%0, %2}"
6924 [(set_attr "type" "alu")
6925 (set_attr "mode" "DI")])
6927 (define_insn "subqi3_carry"
6928 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm,r")
6929 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6930 (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
6931 (match_operand:QI 2 "general_operand" "ri,rm"))))
6932 (clobber (reg:CC 17))]
6933 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6934 "sbb{b}\t{%2, %0|%0, %2}"
6935 [(set_attr "type" "alu")
6936 (set_attr "pent_pair" "pu")
6937 (set_attr "ppro_uops" "few")
6938 (set_attr "mode" "QI")])
6940 (define_insn "subhi3_carry"
6941 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6942 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6943 (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
6944 (match_operand:HI 2 "general_operand" "ri,rm"))))
6945 (clobber (reg:CC 17))]
6946 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6947 "sbb{w}\t{%2, %0|%0, %2}"
6948 [(set_attr "type" "alu")
6949 (set_attr "pent_pair" "pu")
6950 (set_attr "ppro_uops" "few")
6951 (set_attr "mode" "HI")])
6953 (define_insn "subsi3_carry"
6954 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6955 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6956 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6957 (match_operand:SI 2 "general_operand" "ri,rm"))))
6958 (clobber (reg:CC 17))]
6959 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6960 "sbb{l}\t{%2, %0|%0, %2}"
6961 [(set_attr "type" "alu")
6962 (set_attr "pent_pair" "pu")
6963 (set_attr "ppro_uops" "few")
6964 (set_attr "mode" "SI")])
6966 (define_insn "subsi3_carry_zext"
6967 [(set (match_operand:DI 0 "register_operand" "=rm,r")
6969 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6970 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6971 (match_operand:SI 2 "general_operand" "ri,rm")))))
6972 (clobber (reg:CC 17))]
6973 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6974 "sbb{l}\t{%2, %k0|%k0, %2}"
6975 [(set_attr "type" "alu")
6976 (set_attr "pent_pair" "pu")
6977 (set_attr "ppro_uops" "few")
6978 (set_attr "mode" "SI")])
6980 (define_expand "subsi3"
6981 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
6982 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
6983 (match_operand:SI 2 "general_operand" "")))
6984 (clobber (reg:CC 17))])]
6986 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
6988 (define_insn "*subsi_1"
6989 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6990 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6991 (match_operand:SI 2 "general_operand" "ri,rm")))
6992 (clobber (reg:CC 17))]
6993 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6994 "sub{l}\t{%2, %0|%0, %2}"
6995 [(set_attr "type" "alu")
6996 (set_attr "mode" "SI")])
6998 (define_insn "*subsi_1_zext"
6999 [(set (match_operand:DI 0 "register_operand" "=r")
7001 (minus:SI (match_operand:SI 1 "register_operand" "0")
7002 (match_operand:SI 2 "general_operand" "rim"))))
7003 (clobber (reg:CC 17))]
7004 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
7005 "sub{l}\t{%2, %k0|%k0, %2}"
7006 [(set_attr "type" "alu")
7007 (set_attr "mode" "SI")])
7009 (define_insn "*subsi_2"
7012 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
7013 (match_operand:SI 2 "general_operand" "ri,rm"))
7015 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7016 (minus:SI (match_dup 1) (match_dup 2)))]
7017 "ix86_match_ccmode (insn, CCGOCmode)
7018 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7019 "sub{l}\t{%2, %0|%0, %2}"
7020 [(set_attr "type" "alu")
7021 (set_attr "mode" "SI")])
7023 (define_insn "*subsi_2_zext"
7026 (minus:SI (match_operand:SI 1 "register_operand" "0")
7027 (match_operand:SI 2 "general_operand" "rim"))
7029 (set (match_operand:DI 0 "register_operand" "=r")
7031 (minus:SI (match_dup 1)
7033 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
7034 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7035 "sub{l}\t{%2, %k0|%k0, %2}"
7036 [(set_attr "type" "alu")
7037 (set_attr "mode" "SI")])
7039 (define_insn "*subsi_3"
7041 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
7042 (match_operand:SI 2 "general_operand" "ri,rm")))
7043 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7044 (minus:SI (match_dup 1) (match_dup 2)))]
7045 "ix86_match_ccmode (insn, CCmode)
7046 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7047 "sub{l}\t{%2, %0|%0, %2}"
7048 [(set_attr "type" "alu")
7049 (set_attr "mode" "SI")])
7051 (define_insn "*subsi_3_zext"
7053 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
7054 (match_operand:SI 2 "general_operand" "rim")))
7055 (set (match_operand:DI 0 "register_operand" "=r")
7057 (minus:SI (match_dup 1)
7059 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
7060 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7061 "sub{q}\t{%2, %0|%0, %2}"
7062 [(set_attr "type" "alu")
7063 (set_attr "mode" "DI")])
7065 (define_expand "subhi3"
7066 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
7067 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
7068 (match_operand:HI 2 "general_operand" "")))
7069 (clobber (reg:CC 17))])]
7070 "TARGET_HIMODE_MATH"
7071 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
7073 (define_insn "*subhi_1"
7074 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7075 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
7076 (match_operand:HI 2 "general_operand" "ri,rm")))
7077 (clobber (reg:CC 17))]
7078 "ix86_binary_operator_ok (MINUS, HImode, operands)"
7079 "sub{w}\t{%2, %0|%0, %2}"
7080 [(set_attr "type" "alu")
7081 (set_attr "mode" "HI")])
7083 (define_insn "*subhi_2"
7086 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
7087 (match_operand:HI 2 "general_operand" "ri,rm"))
7089 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7090 (minus:HI (match_dup 1) (match_dup 2)))]
7091 "ix86_match_ccmode (insn, CCGOCmode)
7092 && ix86_binary_operator_ok (MINUS, HImode, operands)"
7093 "sub{w}\t{%2, %0|%0, %2}"
7094 [(set_attr "type" "alu")
7095 (set_attr "mode" "HI")])
7097 (define_insn "*subhi_3"
7099 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
7100 (match_operand:HI 2 "general_operand" "ri,rm")))
7101 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7102 (minus:HI (match_dup 1) (match_dup 2)))]
7103 "ix86_match_ccmode (insn, CCmode)
7104 && ix86_binary_operator_ok (MINUS, HImode, operands)"
7105 "sub{w}\t{%2, %0|%0, %2}"
7106 [(set_attr "type" "alu")
7107 (set_attr "mode" "HI")])
7109 (define_expand "subqi3"
7110 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
7111 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
7112 (match_operand:QI 2 "general_operand" "")))
7113 (clobber (reg:CC 17))])]
7114 "TARGET_QIMODE_MATH"
7115 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
7117 (define_insn "*subqi_1"
7118 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
7119 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
7120 (match_operand:QI 2 "general_operand" "qn,qmn")))
7121 (clobber (reg:CC 17))]
7122 "ix86_binary_operator_ok (MINUS, QImode, operands)"
7123 "sub{b}\t{%2, %0|%0, %2}"
7124 [(set_attr "type" "alu")
7125 (set_attr "mode" "QI")])
7127 (define_insn "*subqi_1_slp"
7128 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
7129 (minus:QI (match_dup 0)
7130 (match_operand:QI 1 "general_operand" "qn,qmn")))
7131 (clobber (reg:CC 17))]
7132 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
7133 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7134 "sub{b}\t{%1, %0|%0, %1}"
7135 [(set_attr "type" "alu1")
7136 (set_attr "mode" "QI")])
7138 (define_insn "*subqi_2"
7141 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
7142 (match_operand:QI 2 "general_operand" "qi,qm"))
7144 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
7145 (minus:HI (match_dup 1) (match_dup 2)))]
7146 "ix86_match_ccmode (insn, CCGOCmode)
7147 && ix86_binary_operator_ok (MINUS, QImode, operands)"
7148 "sub{b}\t{%2, %0|%0, %2}"
7149 [(set_attr "type" "alu")
7150 (set_attr "mode" "QI")])
7152 (define_insn "*subqi_3"
7154 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
7155 (match_operand:QI 2 "general_operand" "qi,qm")))
7156 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
7157 (minus:HI (match_dup 1) (match_dup 2)))]
7158 "ix86_match_ccmode (insn, CCmode)
7159 && ix86_binary_operator_ok (MINUS, QImode, operands)"
7160 "sub{b}\t{%2, %0|%0, %2}"
7161 [(set_attr "type" "alu")
7162 (set_attr "mode" "QI")])
7164 ;; The patterns that match these are at the end of this file.
7166 (define_expand "subxf3"
7167 [(set (match_operand:XF 0 "register_operand" "")
7168 (minus:XF (match_operand:XF 1 "register_operand" "")
7169 (match_operand:XF 2 "register_operand" "")))]
7170 "!TARGET_64BIT && TARGET_80387"
7173 (define_expand "subtf3"
7174 [(set (match_operand:TF 0 "register_operand" "")
7175 (minus:TF (match_operand:TF 1 "register_operand" "")
7176 (match_operand:TF 2 "register_operand" "")))]
7180 (define_expand "subdf3"
7181 [(set (match_operand:DF 0 "register_operand" "")
7182 (minus:DF (match_operand:DF 1 "register_operand" "")
7183 (match_operand:DF 2 "nonimmediate_operand" "")))]
7184 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7187 (define_expand "subsf3"
7188 [(set (match_operand:SF 0 "register_operand" "")
7189 (minus:SF (match_operand:SF 1 "register_operand" "")
7190 (match_operand:SF 2 "nonimmediate_operand" "")))]
7191 "TARGET_80387 || TARGET_SSE_MATH"
7194 ;; Multiply instructions
7196 (define_expand "muldi3"
7197 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7198 (mult:DI (match_operand:DI 1 "register_operand" "")
7199 (match_operand:DI 2 "x86_64_general_operand" "")))
7200 (clobber (reg:CC 17))])]
7204 (define_insn "*muldi3_1_rex64"
7205 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7206 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0")
7207 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
7208 (clobber (reg:CC 17))]
7210 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7212 imul{q}\t{%2, %1, %0|%0, %1, %2}
7213 imul{q}\t{%2, %1, %0|%0, %1, %2}
7214 imul{q}\t{%2, %0|%0, %2}"
7215 [(set_attr "type" "imul")
7216 (set_attr "prefix_0f" "0,0,1")
7217 (set (attr "athlon_decode")
7218 (cond [(eq_attr "cpu" "athlon")
7219 (const_string "vector")
7220 (eq_attr "alternative" "1")
7221 (const_string "vector")
7222 (and (eq_attr "alternative" "2")
7223 (match_operand 1 "memory_operand" ""))
7224 (const_string "vector")]
7225 (const_string "direct")))
7226 (set_attr "mode" "DI")])
7228 (define_expand "mulsi3"
7229 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7230 (mult:SI (match_operand:SI 1 "register_operand" "")
7231 (match_operand:SI 2 "general_operand" "")))
7232 (clobber (reg:CC 17))])]
7236 (define_insn "*mulsi3_1"
7237 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7238 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
7239 (match_operand:SI 2 "general_operand" "K,i,mr")))
7240 (clobber (reg:CC 17))]
7241 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7243 imul{l}\t{%2, %1, %0|%0, %1, %2}
7244 imul{l}\t{%2, %1, %0|%0, %1, %2}
7245 imul{l}\t{%2, %0|%0, %2}"
7246 [(set_attr "type" "imul")
7247 (set_attr "prefix_0f" "0,0,1")
7248 (set (attr "athlon_decode")
7249 (cond [(eq_attr "cpu" "athlon")
7250 (const_string "vector")
7251 (eq_attr "alternative" "1")
7252 (const_string "vector")
7253 (and (eq_attr "alternative" "2")
7254 (match_operand 1 "memory_operand" ""))
7255 (const_string "vector")]
7256 (const_string "direct")))
7257 (set_attr "mode" "SI")])
7259 (define_insn "*mulsi3_1_zext"
7260 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7262 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
7263 (match_operand:SI 2 "general_operand" "K,i,mr"))))
7264 (clobber (reg:CC 17))]
7266 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7268 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7269 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7270 imul{l}\t{%2, %k0|%k0, %2}"
7271 [(set_attr "type" "imul")
7272 (set_attr "prefix_0f" "0,0,1")
7273 (set (attr "athlon_decode")
7274 (cond [(eq_attr "cpu" "athlon")
7275 (const_string "vector")
7276 (eq_attr "alternative" "1")
7277 (const_string "vector")
7278 (and (eq_attr "alternative" "2")
7279 (match_operand 1 "memory_operand" ""))
7280 (const_string "vector")]
7281 (const_string "direct")))
7282 (set_attr "mode" "SI")])
7284 (define_expand "mulhi3"
7285 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7286 (mult:HI (match_operand:HI 1 "register_operand" "")
7287 (match_operand:HI 2 "general_operand" "")))
7288 (clobber (reg:CC 17))])]
7289 "TARGET_HIMODE_MATH"
7292 (define_insn "*mulhi3_1"
7293 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
7294 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
7295 (match_operand:HI 2 "general_operand" "K,i,mr")))
7296 (clobber (reg:CC 17))]
7297 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7299 imul{w}\t{%2, %1, %0|%0, %1, %2}
7300 imul{w}\t{%2, %1, %0|%0, %1, %2}
7301 imul{w}\t{%2, %0|%0, %2}"
7302 [(set_attr "type" "imul")
7303 (set_attr "prefix_0f" "0,0,1")
7304 (set (attr "athlon_decode")
7305 (cond [(eq_attr "cpu" "athlon")
7306 (const_string "vector")
7307 (eq_attr "alternative" "1,2")
7308 (const_string "vector")]
7309 (const_string "direct")))
7310 (set_attr "mode" "HI")])
7312 (define_expand "mulqi3"
7313 [(parallel [(set (match_operand:QI 0 "register_operand" "")
7314 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
7315 (match_operand:QI 2 "register_operand" "")))
7316 (clobber (reg:CC 17))])]
7317 "TARGET_QIMODE_MATH"
7320 (define_insn "*mulqi3_1"
7321 [(set (match_operand:QI 0 "register_operand" "=a")
7322 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
7323 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7324 (clobber (reg:CC 17))]
7326 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7328 [(set_attr "type" "imul")
7329 (set_attr "length_immediate" "0")
7330 (set (attr "athlon_decode")
7331 (if_then_else (eq_attr "cpu" "athlon")
7332 (const_string "vector")
7333 (const_string "direct")))
7334 (set_attr "mode" "QI")])
7336 (define_expand "umulqihi3"
7337 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7338 (mult:HI (zero_extend:HI
7339 (match_operand:QI 1 "nonimmediate_operand" ""))
7341 (match_operand:QI 2 "register_operand" ""))))
7342 (clobber (reg:CC 17))])]
7343 "TARGET_QIMODE_MATH"
7346 (define_insn "*umulqihi3_1"
7347 [(set (match_operand:HI 0 "register_operand" "=a")
7348 (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7349 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7350 (clobber (reg:CC 17))]
7352 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7354 [(set_attr "type" "imul")
7355 (set_attr "length_immediate" "0")
7356 (set (attr "athlon_decode")
7357 (if_then_else (eq_attr "cpu" "athlon")
7358 (const_string "vector")
7359 (const_string "direct")))
7360 (set_attr "mode" "QI")])
7362 (define_expand "mulqihi3"
7363 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7364 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
7365 (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
7366 (clobber (reg:CC 17))])]
7367 "TARGET_QIMODE_MATH"
7370 (define_insn "*mulqihi3_insn"
7371 [(set (match_operand:HI 0 "register_operand" "=a")
7372 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7373 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7374 (clobber (reg:CC 17))]
7376 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7378 [(set_attr "type" "imul")
7379 (set_attr "length_immediate" "0")
7380 (set (attr "athlon_decode")
7381 (if_then_else (eq_attr "cpu" "athlon")
7382 (const_string "vector")
7383 (const_string "direct")))
7384 (set_attr "mode" "QI")])
7386 (define_expand "umulditi3"
7387 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7388 (mult:TI (zero_extend:TI
7389 (match_operand:DI 1 "nonimmediate_operand" ""))
7391 (match_operand:DI 2 "register_operand" ""))))
7392 (clobber (reg:CC 17))])]
7396 (define_insn "*umulditi3_insn"
7397 [(set (match_operand:TI 0 "register_operand" "=A")
7398 (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7399 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7400 (clobber (reg:CC 17))]
7402 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7404 [(set_attr "type" "imul")
7405 (set_attr "ppro_uops" "few")
7406 (set_attr "length_immediate" "0")
7407 (set (attr "athlon_decode")
7408 (if_then_else (eq_attr "cpu" "athlon")
7409 (const_string "vector")
7410 (const_string "double")))
7411 (set_attr "mode" "DI")])
7413 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7414 (define_expand "umulsidi3"
7415 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7416 (mult:DI (zero_extend:DI
7417 (match_operand:SI 1 "nonimmediate_operand" ""))
7419 (match_operand:SI 2 "register_operand" ""))))
7420 (clobber (reg:CC 17))])]
7424 (define_insn "*umulsidi3_insn"
7425 [(set (match_operand:DI 0 "register_operand" "=A")
7426 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7427 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7428 (clobber (reg:CC 17))]
7430 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7432 [(set_attr "type" "imul")
7433 (set_attr "ppro_uops" "few")
7434 (set_attr "length_immediate" "0")
7435 (set (attr "athlon_decode")
7436 (if_then_else (eq_attr "cpu" "athlon")
7437 (const_string "vector")
7438 (const_string "double")))
7439 (set_attr "mode" "SI")])
7441 (define_expand "mulditi3"
7442 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7443 (mult:TI (sign_extend:TI
7444 (match_operand:DI 1 "nonimmediate_operand" ""))
7446 (match_operand:DI 2 "register_operand" ""))))
7447 (clobber (reg:CC 17))])]
7451 (define_insn "*mulditi3_insn"
7452 [(set (match_operand:TI 0 "register_operand" "=A")
7453 (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7454 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7455 (clobber (reg:CC 17))]
7457 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7459 [(set_attr "type" "imul")
7460 (set_attr "length_immediate" "0")
7461 (set (attr "athlon_decode")
7462 (if_then_else (eq_attr "cpu" "athlon")
7463 (const_string "vector")
7464 (const_string "double")))
7465 (set_attr "mode" "DI")])
7467 (define_expand "mulsidi3"
7468 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7469 (mult:DI (sign_extend:DI
7470 (match_operand:SI 1 "nonimmediate_operand" ""))
7472 (match_operand:SI 2 "register_operand" ""))))
7473 (clobber (reg:CC 17))])]
7477 (define_insn "*mulsidi3_insn"
7478 [(set (match_operand:DI 0 "register_operand" "=A")
7479 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7480 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7481 (clobber (reg:CC 17))]
7483 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7485 [(set_attr "type" "imul")
7486 (set_attr "length_immediate" "0")
7487 (set (attr "athlon_decode")
7488 (if_then_else (eq_attr "cpu" "athlon")
7489 (const_string "vector")
7490 (const_string "double")))
7491 (set_attr "mode" "SI")])
7493 (define_expand "umuldi3_highpart"
7494 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7497 (mult:TI (zero_extend:TI
7498 (match_operand:DI 1 "nonimmediate_operand" ""))
7500 (match_operand:DI 2 "register_operand" "")))
7502 (clobber (match_scratch:DI 3 ""))
7503 (clobber (reg:CC 17))])]
7507 (define_insn "*umuldi3_highpart_rex64"
7508 [(set (match_operand:DI 0 "register_operand" "=d")
7511 (mult:TI (zero_extend:TI
7512 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7514 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7516 (clobber (match_scratch:DI 3 "=1"))
7517 (clobber (reg:CC 17))]
7519 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7521 [(set_attr "type" "imul")
7522 (set_attr "ppro_uops" "few")
7523 (set_attr "length_immediate" "0")
7524 (set (attr "athlon_decode")
7525 (if_then_else (eq_attr "cpu" "athlon")
7526 (const_string "vector")
7527 (const_string "double")))
7528 (set_attr "mode" "DI")])
7530 (define_expand "umulsi3_highpart"
7531 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7534 (mult:DI (zero_extend:DI
7535 (match_operand:SI 1 "nonimmediate_operand" ""))
7537 (match_operand:SI 2 "register_operand" "")))
7539 (clobber (match_scratch:SI 3 ""))
7540 (clobber (reg:CC 17))])]
7544 (define_insn "*umulsi3_highpart_insn"
7545 [(set (match_operand:SI 0 "register_operand" "=d")
7548 (mult:DI (zero_extend:DI
7549 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7551 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7553 (clobber (match_scratch:SI 3 "=1"))
7554 (clobber (reg:CC 17))]
7555 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7557 [(set_attr "type" "imul")
7558 (set_attr "ppro_uops" "few")
7559 (set_attr "length_immediate" "0")
7560 (set (attr "athlon_decode")
7561 (if_then_else (eq_attr "cpu" "athlon")
7562 (const_string "vector")
7563 (const_string "double")))
7564 (set_attr "mode" "SI")])
7566 (define_insn "*umulsi3_highpart_zext"
7567 [(set (match_operand:DI 0 "register_operand" "=d")
7568 (zero_extend:DI (truncate:SI
7570 (mult:DI (zero_extend:DI
7571 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7573 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7575 (clobber (match_scratch:SI 3 "=1"))
7576 (clobber (reg:CC 17))]
7578 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7580 [(set_attr "type" "imul")
7581 (set_attr "ppro_uops" "few")
7582 (set_attr "length_immediate" "0")
7583 (set (attr "athlon_decode")
7584 (if_then_else (eq_attr "cpu" "athlon")
7585 (const_string "vector")
7586 (const_string "double")))
7587 (set_attr "mode" "SI")])
7589 (define_expand "smuldi3_highpart"
7590 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
7593 (mult:TI (sign_extend:TI
7594 (match_operand:DI 1 "nonimmediate_operand" ""))
7596 (match_operand:DI 2 "register_operand" "")))
7598 (clobber (match_scratch:DI 3 ""))
7599 (clobber (reg:CC 17))])]
7603 (define_insn "*smuldi3_highpart_rex64"
7604 [(set (match_operand:DI 0 "register_operand" "=d")
7607 (mult:TI (sign_extend:TI
7608 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7610 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7612 (clobber (match_scratch:DI 3 "=1"))
7613 (clobber (reg:CC 17))]
7615 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7617 [(set_attr "type" "imul")
7618 (set_attr "ppro_uops" "few")
7619 (set (attr "athlon_decode")
7620 (if_then_else (eq_attr "cpu" "athlon")
7621 (const_string "vector")
7622 (const_string "double")))
7623 (set_attr "mode" "DI")])
7625 (define_expand "smulsi3_highpart"
7626 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7629 (mult:DI (sign_extend:DI
7630 (match_operand:SI 1 "nonimmediate_operand" ""))
7632 (match_operand:SI 2 "register_operand" "")))
7634 (clobber (match_scratch:SI 3 ""))
7635 (clobber (reg:CC 17))])]
7639 (define_insn "*smulsi3_highpart_insn"
7640 [(set (match_operand:SI 0 "register_operand" "=d")
7643 (mult:DI (sign_extend:DI
7644 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7646 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7648 (clobber (match_scratch:SI 3 "=1"))
7649 (clobber (reg:CC 17))]
7650 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7652 [(set_attr "type" "imul")
7653 (set_attr "ppro_uops" "few")
7654 (set (attr "athlon_decode")
7655 (if_then_else (eq_attr "cpu" "athlon")
7656 (const_string "vector")
7657 (const_string "double")))
7658 (set_attr "mode" "SI")])
7660 (define_insn "*smulsi3_highpart_zext"
7661 [(set (match_operand:DI 0 "register_operand" "=d")
7662 (zero_extend:DI (truncate:SI
7664 (mult:DI (sign_extend:DI
7665 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7667 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7669 (clobber (match_scratch:SI 3 "=1"))
7670 (clobber (reg:CC 17))]
7672 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7674 [(set_attr "type" "imul")
7675 (set_attr "ppro_uops" "few")
7676 (set (attr "athlon_decode")
7677 (if_then_else (eq_attr "cpu" "athlon")
7678 (const_string "vector")
7679 (const_string "double")))
7680 (set_attr "mode" "SI")])
7682 ;; The patterns that match these are at the end of this file.
7684 (define_expand "mulxf3"
7685 [(set (match_operand:XF 0 "register_operand" "")
7686 (mult:XF (match_operand:XF 1 "register_operand" "")
7687 (match_operand:XF 2 "register_operand" "")))]
7688 "!TARGET_64BIT && TARGET_80387"
7691 (define_expand "multf3"
7692 [(set (match_operand:TF 0 "register_operand" "")
7693 (mult:TF (match_operand:TF 1 "register_operand" "")
7694 (match_operand:TF 2 "register_operand" "")))]
7698 (define_expand "muldf3"
7699 [(set (match_operand:DF 0 "register_operand" "")
7700 (mult:DF (match_operand:DF 1 "register_operand" "")
7701 (match_operand:DF 2 "nonimmediate_operand" "")))]
7702 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7705 (define_expand "mulsf3"
7706 [(set (match_operand:SF 0 "register_operand" "")
7707 (mult:SF (match_operand:SF 1 "register_operand" "")
7708 (match_operand:SF 2 "nonimmediate_operand" "")))]
7709 "TARGET_80387 || TARGET_SSE_MATH"
7712 ;; Divide instructions
7714 (define_insn "divqi3"
7715 [(set (match_operand:QI 0 "register_operand" "=a")
7716 (div:QI (match_operand:HI 1 "register_operand" "0")
7717 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7718 (clobber (reg:CC 17))]
7719 "TARGET_QIMODE_MATH"
7721 [(set_attr "type" "idiv")
7722 (set_attr "mode" "QI")
7723 (set_attr "ppro_uops" "few")])
7725 (define_insn "udivqi3"
7726 [(set (match_operand:QI 0 "register_operand" "=a")
7727 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7728 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7729 (clobber (reg:CC 17))]
7730 "TARGET_QIMODE_MATH"
7732 [(set_attr "type" "idiv")
7733 (set_attr "mode" "QI")
7734 (set_attr "ppro_uops" "few")])
7736 ;; The patterns that match these are at the end of this file.
7738 (define_expand "divxf3"
7739 [(set (match_operand:XF 0 "register_operand" "")
7740 (div:XF (match_operand:XF 1 "register_operand" "")
7741 (match_operand:XF 2 "register_operand" "")))]
7742 "!TARGET_64BIT && TARGET_80387"
7745 (define_expand "divtf3"
7746 [(set (match_operand:TF 0 "register_operand" "")
7747 (div:TF (match_operand:TF 1 "register_operand" "")
7748 (match_operand:TF 2 "register_operand" "")))]
7752 (define_expand "divdf3"
7753 [(set (match_operand:DF 0 "register_operand" "")
7754 (div:DF (match_operand:DF 1 "register_operand" "")
7755 (match_operand:DF 2 "nonimmediate_operand" "")))]
7756 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7759 (define_expand "divsf3"
7760 [(set (match_operand:SF 0 "register_operand" "")
7761 (div:SF (match_operand:SF 1 "register_operand" "")
7762 (match_operand:SF 2 "nonimmediate_operand" "")))]
7763 "TARGET_80387 || TARGET_SSE_MATH"
7766 ;; Remainder instructions.
7768 (define_expand "divmoddi4"
7769 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7770 (div:DI (match_operand:DI 1 "register_operand" "")
7771 (match_operand:DI 2 "nonimmediate_operand" "")))
7772 (set (match_operand:DI 3 "register_operand" "")
7773 (mod:DI (match_dup 1) (match_dup 2)))
7774 (clobber (reg:CC 17))])]
7778 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7779 ;; Penalize eax case slightly because it results in worse scheduling
7781 (define_insn "*divmoddi4_nocltd_rex64"
7782 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7783 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7784 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7785 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7786 (mod:DI (match_dup 2) (match_dup 3)))
7787 (clobber (reg:CC 17))]
7788 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7790 [(set_attr "type" "multi")])
7792 (define_insn "*divmoddi4_cltd_rex64"
7793 [(set (match_operand:DI 0 "register_operand" "=a")
7794 (div:DI (match_operand:DI 2 "register_operand" "a")
7795 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7796 (set (match_operand:DI 1 "register_operand" "=&d")
7797 (mod:DI (match_dup 2) (match_dup 3)))
7798 (clobber (reg:CC 17))]
7799 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7801 [(set_attr "type" "multi")])
7803 (define_insn "*divmoddi_noext_rex64"
7804 [(set (match_operand:DI 0 "register_operand" "=a")
7805 (div:DI (match_operand:DI 1 "register_operand" "0")
7806 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7807 (set (match_operand:DI 3 "register_operand" "=d")
7808 (mod:DI (match_dup 1) (match_dup 2)))
7809 (use (match_operand:DI 4 "register_operand" "3"))
7810 (clobber (reg:CC 17))]
7813 [(set_attr "type" "idiv")
7814 (set_attr "mode" "DI")
7815 (set_attr "ppro_uops" "few")])
7818 [(set (match_operand:DI 0 "register_operand" "")
7819 (div:DI (match_operand:DI 1 "register_operand" "")
7820 (match_operand:DI 2 "nonimmediate_operand" "")))
7821 (set (match_operand:DI 3 "register_operand" "")
7822 (mod:DI (match_dup 1) (match_dup 2)))
7823 (clobber (reg:CC 17))]
7824 "TARGET_64BIT && reload_completed"
7825 [(parallel [(set (match_dup 3)
7826 (ashiftrt:DI (match_dup 4) (const_int 63)))
7827 (clobber (reg:CC 17))])
7828 (parallel [(set (match_dup 0)
7829 (div:DI (reg:DI 0) (match_dup 2)))
7831 (mod:DI (reg:DI 0) (match_dup 2)))
7833 (clobber (reg:CC 17))])]
7835 /* Avoid use of cltd in favor of a mov+shift. */
7836 if (!TARGET_USE_CLTD && !optimize_size)
7838 if (true_regnum (operands[1]))
7839 emit_move_insn (operands[0], operands[1]);
7841 emit_move_insn (operands[3], operands[1]);
7842 operands[4] = operands[3];
7846 if (true_regnum (operands[1]))
7848 operands[4] = operands[1];
7853 (define_expand "divmodsi4"
7854 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7855 (div:SI (match_operand:SI 1 "register_operand" "")
7856 (match_operand:SI 2 "nonimmediate_operand" "")))
7857 (set (match_operand:SI 3 "register_operand" "")
7858 (mod:SI (match_dup 1) (match_dup 2)))
7859 (clobber (reg:CC 17))])]
7863 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7864 ;; Penalize eax case slightly because it results in worse scheduling
7866 (define_insn "*divmodsi4_nocltd"
7867 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7868 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7869 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7870 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7871 (mod:SI (match_dup 2) (match_dup 3)))
7872 (clobber (reg:CC 17))]
7873 "!optimize_size && !TARGET_USE_CLTD"
7875 [(set_attr "type" "multi")])
7877 (define_insn "*divmodsi4_cltd"
7878 [(set (match_operand:SI 0 "register_operand" "=a")
7879 (div:SI (match_operand:SI 2 "register_operand" "a")
7880 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7881 (set (match_operand:SI 1 "register_operand" "=&d")
7882 (mod:SI (match_dup 2) (match_dup 3)))
7883 (clobber (reg:CC 17))]
7884 "optimize_size || TARGET_USE_CLTD"
7886 [(set_attr "type" "multi")])
7888 (define_insn "*divmodsi_noext"
7889 [(set (match_operand:SI 0 "register_operand" "=a")
7890 (div:SI (match_operand:SI 1 "register_operand" "0")
7891 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7892 (set (match_operand:SI 3 "register_operand" "=d")
7893 (mod:SI (match_dup 1) (match_dup 2)))
7894 (use (match_operand:SI 4 "register_operand" "3"))
7895 (clobber (reg:CC 17))]
7898 [(set_attr "type" "idiv")
7899 (set_attr "mode" "SI")
7900 (set_attr "ppro_uops" "few")])
7903 [(set (match_operand:SI 0 "register_operand" "")
7904 (div:SI (match_operand:SI 1 "register_operand" "")
7905 (match_operand:SI 2 "nonimmediate_operand" "")))
7906 (set (match_operand:SI 3 "register_operand" "")
7907 (mod:SI (match_dup 1) (match_dup 2)))
7908 (clobber (reg:CC 17))]
7910 [(parallel [(set (match_dup 3)
7911 (ashiftrt:SI (match_dup 4) (const_int 31)))
7912 (clobber (reg:CC 17))])
7913 (parallel [(set (match_dup 0)
7914 (div:SI (reg:SI 0) (match_dup 2)))
7916 (mod:SI (reg:SI 0) (match_dup 2)))
7918 (clobber (reg:CC 17))])]
7920 /* Avoid use of cltd in favor of a mov+shift. */
7921 if (!TARGET_USE_CLTD && !optimize_size)
7923 if (true_regnum (operands[1]))
7924 emit_move_insn (operands[0], operands[1]);
7926 emit_move_insn (operands[3], operands[1]);
7927 operands[4] = operands[3];
7931 if (true_regnum (operands[1]))
7933 operands[4] = operands[1];
7937 (define_insn "divmodhi4"
7938 [(set (match_operand:HI 0 "register_operand" "=a")
7939 (div:HI (match_operand:HI 1 "register_operand" "0")
7940 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7941 (set (match_operand:HI 3 "register_operand" "=&d")
7942 (mod:HI (match_dup 1) (match_dup 2)))
7943 (clobber (reg:CC 17))]
7944 "TARGET_HIMODE_MATH"
7946 [(set_attr "type" "multi")
7947 (set_attr "length_immediate" "0")
7948 (set_attr "mode" "SI")])
7950 (define_insn "udivmoddi4"
7951 [(set (match_operand:DI 0 "register_operand" "=a")
7952 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7953 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7954 (set (match_operand:DI 3 "register_operand" "=&d")
7955 (umod:DI (match_dup 1) (match_dup 2)))
7956 (clobber (reg:CC 17))]
7958 "xor{q}\t%3, %3\;div{q}\t%2"
7959 [(set_attr "type" "multi")
7960 (set_attr "length_immediate" "0")
7961 (set_attr "mode" "DI")])
7963 (define_insn "*udivmoddi4_noext"
7964 [(set (match_operand:DI 0 "register_operand" "=a")
7965 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7966 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7967 (set (match_operand:DI 3 "register_operand" "=d")
7968 (umod:DI (match_dup 1) (match_dup 2)))
7970 (clobber (reg:CC 17))]
7973 [(set_attr "type" "idiv")
7974 (set_attr "ppro_uops" "few")
7975 (set_attr "mode" "DI")])
7978 [(set (match_operand:DI 0 "register_operand" "")
7979 (udiv:DI (match_operand:DI 1 "register_operand" "")
7980 (match_operand:DI 2 "nonimmediate_operand" "")))
7981 (set (match_operand:DI 3 "register_operand" "")
7982 (umod:DI (match_dup 1) (match_dup 2)))
7983 (clobber (reg:CC 17))]
7984 "TARGET_64BIT && reload_completed"
7985 [(set (match_dup 3) (const_int 0))
7986 (parallel [(set (match_dup 0)
7987 (udiv:DI (match_dup 1) (match_dup 2)))
7989 (umod:DI (match_dup 1) (match_dup 2)))
7991 (clobber (reg:CC 17))])]
7994 (define_insn "udivmodsi4"
7995 [(set (match_operand:SI 0 "register_operand" "=a")
7996 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7997 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7998 (set (match_operand:SI 3 "register_operand" "=&d")
7999 (umod:SI (match_dup 1) (match_dup 2)))
8000 (clobber (reg:CC 17))]
8002 "xor{l}\t%3, %3\;div{l}\t%2"
8003 [(set_attr "type" "multi")
8004 (set_attr "length_immediate" "0")
8005 (set_attr "mode" "SI")])
8007 (define_insn "*udivmodsi4_noext"
8008 [(set (match_operand:SI 0 "register_operand" "=a")
8009 (udiv:SI (match_operand:SI 1 "register_operand" "0")
8010 (match_operand:SI 2 "nonimmediate_operand" "rm")))
8011 (set (match_operand:SI 3 "register_operand" "=d")
8012 (umod:SI (match_dup 1) (match_dup 2)))
8014 (clobber (reg:CC 17))]
8017 [(set_attr "type" "idiv")
8018 (set_attr "ppro_uops" "few")
8019 (set_attr "mode" "SI")])
8022 [(set (match_operand:SI 0 "register_operand" "")
8023 (udiv:SI (match_operand:SI 1 "register_operand" "")
8024 (match_operand:SI 2 "nonimmediate_operand" "")))
8025 (set (match_operand:SI 3 "register_operand" "")
8026 (umod:SI (match_dup 1) (match_dup 2)))
8027 (clobber (reg:CC 17))]
8029 [(set (match_dup 3) (const_int 0))
8030 (parallel [(set (match_dup 0)
8031 (udiv:SI (match_dup 1) (match_dup 2)))
8033 (umod:SI (match_dup 1) (match_dup 2)))
8035 (clobber (reg:CC 17))])]
8038 (define_expand "udivmodhi4"
8039 [(set (match_dup 4) (const_int 0))
8040 (parallel [(set (match_operand:HI 0 "register_operand" "")
8041 (udiv:HI (match_operand:HI 1 "register_operand" "")
8042 (match_operand:HI 2 "nonimmediate_operand" "")))
8043 (set (match_operand:HI 3 "register_operand" "")
8044 (umod:HI (match_dup 1) (match_dup 2)))
8046 (clobber (reg:CC 17))])]
8047 "TARGET_HIMODE_MATH"
8048 "operands[4] = gen_reg_rtx (HImode);")
8050 (define_insn "*udivmodhi_noext"
8051 [(set (match_operand:HI 0 "register_operand" "=a")
8052 (udiv:HI (match_operand:HI 1 "register_operand" "0")
8053 (match_operand:HI 2 "nonimmediate_operand" "rm")))
8054 (set (match_operand:HI 3 "register_operand" "=d")
8055 (umod:HI (match_dup 1) (match_dup 2)))
8056 (use (match_operand:HI 4 "register_operand" "3"))
8057 (clobber (reg:CC 17))]
8060 [(set_attr "type" "idiv")
8061 (set_attr "mode" "HI")
8062 (set_attr "ppro_uops" "few")])
8064 ;; We can not use div/idiv for double division, because it causes
8065 ;; "division by zero" on the overflow and that's not what we expect
8066 ;; from truncate. Because true (non truncating) double division is
8067 ;; never generated, we can't create this insn anyway.
8070 ; [(set (match_operand:SI 0 "register_operand" "=a")
8072 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
8074 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
8075 ; (set (match_operand:SI 3 "register_operand" "=d")
8077 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
8078 ; (clobber (reg:CC 17))]
8080 ; "div{l}\t{%2, %0|%0, %2}"
8081 ; [(set_attr "type" "idiv")
8082 ; (set_attr "ppro_uops" "few")])
8084 ;;- Logical AND instructions
8086 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
8087 ;; Note that this excludes ah.
8089 (define_insn "*testdi_1_rex64"
8092 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%!*a,r,!*a,r,rm")
8093 (match_operand:DI 1 "x86_64_szext_general_operand" "Z,Z,e,e,re"))
8095 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8096 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8098 test{l}\t{%k1, %k0|%k0, %k1}
8099 test{l}\t{%k1, %k0|%k0, %k1}
8100 test{q}\t{%1, %0|%0, %1}
8101 test{q}\t{%1, %0|%0, %1}
8102 test{q}\t{%1, %0|%0, %1}"
8103 [(set_attr "type" "test")
8104 (set_attr "modrm" "0,1,0,1,1")
8105 (set_attr "mode" "SI,SI,DI,DI,DI")
8106 (set_attr "pent_pair" "uv,np,uv,np,uv")])
8108 (define_insn "testsi_1"
8111 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%!*a,r,rm")
8112 (match_operand:SI 1 "general_operand" "in,in,rin"))
8114 "ix86_match_ccmode (insn, CCNOmode)
8115 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8116 "test{l}\t{%1, %0|%0, %1}"
8117 [(set_attr "type" "test")
8118 (set_attr "modrm" "0,1,1")
8119 (set_attr "mode" "SI")
8120 (set_attr "pent_pair" "uv,np,uv")])
8122 (define_expand "testsi_ccno_1"
8125 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
8126 (match_operand:SI 1 "nonmemory_operand" ""))
8131 (define_insn "*testhi_1"
8133 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%!*a,r,rm")
8134 (match_operand:HI 1 "general_operand" "n,n,rn"))
8136 "ix86_match_ccmode (insn, CCNOmode)
8137 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8138 "test{w}\t{%1, %0|%0, %1}"
8139 [(set_attr "type" "test")
8140 (set_attr "modrm" "0,1,1")
8141 (set_attr "mode" "HI")
8142 (set_attr "pent_pair" "uv,np,uv")])
8144 (define_expand "testqi_ccz_1"
8146 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
8147 (match_operand:QI 1 "nonmemory_operand" ""))
8152 (define_insn "*testqi_1"
8154 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm,r")
8155 (match_operand:QI 1 "general_operand" "n,n,qn,n"))
8157 "ix86_match_ccmode (insn, CCNOmode)
8158 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8160 if (which_alternative == 3)
8162 if (GET_CODE (operands[1]) == CONST_INT
8163 && (INTVAL (operands[1]) & 0xffffff00))
8164 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
8165 return "test{l}\t{%1, %k0|%k0, %1}";
8167 return "test{b}\t{%1, %0|%0, %1}";
8169 [(set_attr "type" "test")
8170 (set_attr "modrm" "0,1,1,1")
8171 (set_attr "mode" "QI,QI,QI,SI")
8172 (set_attr "pent_pair" "uv,np,uv,np")])
8174 (define_expand "testqi_ext_ccno_0"
8179 (match_operand 0 "ext_register_operand" "")
8182 (match_operand 1 "const_int_operand" ""))
8187 (define_insn "*testqi_ext_0"
8192 (match_operand 0 "ext_register_operand" "Q")
8195 (match_operand 1 "const_int_operand" "n"))
8197 "ix86_match_ccmode (insn, CCNOmode)"
8198 "test{b}\t{%1, %h0|%h0, %1}"
8199 [(set_attr "type" "test")
8200 (set_attr "mode" "QI")
8201 (set_attr "length_immediate" "1")
8202 (set_attr "pent_pair" "np")])
8204 (define_insn "*testqi_ext_1"
8209 (match_operand 0 "ext_register_operand" "Q")
8213 (match_operand:QI 1 "general_operand" "Qm")))
8215 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8216 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8217 "test{b}\t{%1, %h0|%h0, %1}"
8218 [(set_attr "type" "test")
8219 (set_attr "mode" "QI")])
8221 (define_insn "*testqi_ext_1_rex64"
8226 (match_operand 0 "ext_register_operand" "Q")
8230 (match_operand:QI 1 "register_operand" "Q")))
8232 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8233 "test{b}\t{%1, %h0|%h0, %1}"
8234 [(set_attr "type" "test")
8235 (set_attr "mode" "QI")])
8237 (define_insn "*testqi_ext_2"
8242 (match_operand 0 "ext_register_operand" "Q")
8246 (match_operand 1 "ext_register_operand" "Q")
8250 "ix86_match_ccmode (insn, CCNOmode)"
8251 "test{b}\t{%h1, %h0|%h0, %h1}"
8252 [(set_attr "type" "test")
8253 (set_attr "mode" "QI")])
8255 ;; Combine likes to form bit extractions for some tests. Humor it.
8256 (define_insn "*testqi_ext_3"
8258 (compare (zero_extract:SI
8259 (match_operand 0 "nonimmediate_operand" "rm")
8260 (match_operand:SI 1 "const_int_operand" "")
8261 (match_operand:SI 2 "const_int_operand" ""))
8263 "ix86_match_ccmode (insn, CCNOmode)
8264 && (GET_MODE (operands[0]) == SImode
8265 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
8266 || GET_MODE (operands[0]) == HImode
8267 || GET_MODE (operands[0]) == QImode)"
8270 (define_insn "*testqi_ext_3_rex64"
8272 (compare (zero_extract:DI
8273 (match_operand 0 "nonimmediate_operand" "rm")
8274 (match_operand:DI 1 "const_int_operand" "")
8275 (match_operand:DI 2 "const_int_operand" ""))
8278 && ix86_match_ccmode (insn, CCNOmode)
8279 /* The code below cannot deal with constants outside HOST_WIDE_INT. */
8280 && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT
8281 /* Ensure that resulting mask is zero or sign extended operand. */
8282 && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
8283 || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64
8284 && INTVAL (operands[1]) > 32))
8285 && (GET_MODE (operands[0]) == SImode
8286 || GET_MODE (operands[0]) == DImode
8287 || GET_MODE (operands[0]) == HImode
8288 || GET_MODE (operands[0]) == QImode)"
8293 (compare (zero_extract
8294 (match_operand 0 "nonimmediate_operand" "")
8295 (match_operand 1 "const_int_operand" "")
8296 (match_operand 2 "const_int_operand" ""))
8298 "ix86_match_ccmode (insn, CCNOmode)"
8299 [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
8301 HOST_WIDE_INT len = INTVAL (operands[1]);
8302 HOST_WIDE_INT pos = INTVAL (operands[2]);
8304 enum machine_mode mode, submode;
8306 mode = GET_MODE (operands[0]);
8307 if (GET_CODE (operands[0]) == MEM)
8309 /* ??? Combine likes to put non-volatile mem extractions in QImode
8310 no matter the size of the test. So find a mode that works. */
8311 if (! MEM_VOLATILE_P (operands[0]))
8313 mode = smallest_mode_for_size (pos + len, MODE_INT);
8314 operands[0] = adjust_address (operands[0], mode, 0);
8317 else if (GET_CODE (operands[0]) == SUBREG
8318 && (submode = GET_MODE (SUBREG_REG (operands[0])),
8319 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
8320 && pos + len <= GET_MODE_BITSIZE (submode))
8322 /* Narrow a paradoxical subreg to prevent partial register stalls. */
8324 operands[0] = SUBREG_REG (operands[0]);
8326 else if (mode == HImode && pos + len <= 8)
8328 /* Small HImode tests can be converted to QImode. */
8330 operands[0] = gen_lowpart (QImode, operands[0]);
8333 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
8334 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
8336 operands[3] = gen_rtx_AND (mode, operands[0], gen_int_mode (mask, mode));
8339 ;; Convert HImode/SImode test instructions with immediate to QImode ones.
8340 ;; i386 does not allow to encode test with 8bit sign extended immediate, so
8341 ;; this is relatively important trick.
8342 ;; Do the conversion only post-reload to avoid limiting of the register class
8347 (and (match_operand 0 "register_operand" "")
8348 (match_operand 1 "const_int_operand" ""))
8351 && QI_REG_P (operands[0])
8352 && ((ix86_match_ccmode (insn, CCZmode)
8353 && !(INTVAL (operands[1]) & ~(255 << 8)))
8354 || (ix86_match_ccmode (insn, CCNOmode)
8355 && !(INTVAL (operands[1]) & ~(127 << 8))))
8356 && GET_MODE (operands[0]) != QImode"
8359 (and:SI (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8362 "operands[0] = gen_lowpart (SImode, operands[0]);
8363 operands[1] = gen_int_mode (INTVAL (operands[1]) >> 8, SImode);")
8368 (and (match_operand 0 "nonimmediate_operand" "")
8369 (match_operand 1 "const_int_operand" ""))
8372 && (!REG_P (operands[0]) || ANY_QI_REG_P (operands[0]))
8373 && ((ix86_match_ccmode (insn, CCZmode)
8374 && !(INTVAL (operands[1]) & ~255))
8375 || (ix86_match_ccmode (insn, CCNOmode)
8376 && !(INTVAL (operands[1]) & ~127)))
8377 && GET_MODE (operands[0]) != QImode"
8380 (and:QI (match_dup 0)
8383 "operands[0] = gen_lowpart (QImode, operands[0]);
8384 operands[1] = gen_lowpart (QImode, operands[1]);")
8387 ;; %%% This used to optimize known byte-wide and operations to memory,
8388 ;; and sometimes to QImode registers. If this is considered useful,
8389 ;; it should be done with splitters.
8391 (define_expand "anddi3"
8392 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8393 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
8394 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
8395 (clobber (reg:CC 17))]
8397 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
8399 (define_insn "*anddi_1_rex64"
8400 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
8401 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
8402 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
8403 (clobber (reg:CC 17))]
8404 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
8406 switch (get_attr_type (insn))
8410 enum machine_mode mode;
8412 if (GET_CODE (operands[2]) != CONST_INT)
8414 if (INTVAL (operands[2]) == 0xff)
8416 else if (INTVAL (operands[2]) == 0xffff)
8421 operands[1] = gen_lowpart (mode, operands[1]);
8423 return "movz{bq|x}\t{%1,%0|%0, %1}";
8425 return "movz{wq|x}\t{%1,%0|%0, %1}";
8429 if (! rtx_equal_p (operands[0], operands[1]))
8431 if (get_attr_mode (insn) == MODE_SI)
8432 return "and{l}\t{%k2, %k0|%k0, %k2}";
8434 return "and{q}\t{%2, %0|%0, %2}";
8437 [(set_attr "type" "alu,alu,alu,imovx")
8438 (set_attr "length_immediate" "*,*,*,0")
8439 (set_attr "mode" "SI,DI,DI,DI")])
8441 (define_insn "*anddi_2"
8443 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
8444 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
8446 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
8447 (and:DI (match_dup 1) (match_dup 2)))]
8448 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8449 && ix86_binary_operator_ok (AND, DImode, operands)"
8451 and{l}\t{%k2, %k0|%k0, %k2}
8452 and{q}\t{%2, %0|%0, %2}
8453 and{q}\t{%2, %0|%0, %2}"
8454 [(set_attr "type" "alu")
8455 (set_attr "mode" "SI,DI,DI")])
8457 (define_expand "andsi3"
8458 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8459 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
8460 (match_operand:SI 2 "general_operand" "")))
8461 (clobber (reg:CC 17))]
8463 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
8465 (define_insn "*andsi_1"
8466 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
8467 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
8468 (match_operand:SI 2 "general_operand" "ri,rm,L")))
8469 (clobber (reg:CC 17))]
8470 "ix86_binary_operator_ok (AND, SImode, operands)"
8472 switch (get_attr_type (insn))
8476 enum machine_mode mode;
8478 if (GET_CODE (operands[2]) != CONST_INT)
8480 if (INTVAL (operands[2]) == 0xff)
8482 else if (INTVAL (operands[2]) == 0xffff)
8487 operands[1] = gen_lowpart (mode, operands[1]);
8489 return "movz{bl|x}\t{%1,%0|%0, %1}";
8491 return "movz{wl|x}\t{%1,%0|%0, %1}";
8495 if (! rtx_equal_p (operands[0], operands[1]))
8497 return "and{l}\t{%2, %0|%0, %2}";
8500 [(set_attr "type" "alu,alu,imovx")
8501 (set_attr "length_immediate" "*,*,0")
8502 (set_attr "mode" "SI")])
8505 [(set (match_operand 0 "register_operand" "")
8507 (const_int -65536)))
8508 (clobber (reg:CC 17))]
8509 "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
8510 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8511 "operands[1] = gen_lowpart (HImode, operands[0]);")
8514 [(set (match_operand 0 "ext_register_operand" "")
8517 (clobber (reg:CC 17))]
8518 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8519 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8520 "operands[1] = gen_lowpart (QImode, operands[0]);")
8523 [(set (match_operand 0 "ext_register_operand" "")
8525 (const_int -65281)))
8526 (clobber (reg:CC 17))]
8527 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8528 [(parallel [(set (zero_extract:SI (match_dup 0)
8532 (zero_extract:SI (match_dup 0)
8535 (zero_extract:SI (match_dup 0)
8538 (clobber (reg:CC 17))])]
8539 "operands[0] = gen_lowpart (SImode, operands[0]);")
8541 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8542 (define_insn "*andsi_1_zext"
8543 [(set (match_operand:DI 0 "register_operand" "=r")
8545 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8546 (match_operand:SI 2 "general_operand" "rim"))))
8547 (clobber (reg:CC 17))]
8548 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
8549 "and{l}\t{%2, %k0|%k0, %2}"
8550 [(set_attr "type" "alu")
8551 (set_attr "mode" "SI")])
8553 (define_insn "*andsi_2"
8555 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8556 (match_operand:SI 2 "general_operand" "rim,ri"))
8558 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8559 (and:SI (match_dup 1) (match_dup 2)))]
8560 "ix86_match_ccmode (insn, CCNOmode)
8561 && ix86_binary_operator_ok (AND, SImode, operands)"
8562 "and{l}\t{%2, %0|%0, %2}"
8563 [(set_attr "type" "alu")
8564 (set_attr "mode" "SI")])
8566 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8567 (define_insn "*andsi_2_zext"
8569 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8570 (match_operand:SI 2 "general_operand" "rim"))
8572 (set (match_operand:DI 0 "register_operand" "=r")
8573 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
8574 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8575 && ix86_binary_operator_ok (AND, SImode, operands)"
8576 "and{l}\t{%2, %k0|%k0, %2}"
8577 [(set_attr "type" "alu")
8578 (set_attr "mode" "SI")])
8580 (define_expand "andhi3"
8581 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8582 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
8583 (match_operand:HI 2 "general_operand" "")))
8584 (clobber (reg:CC 17))]
8585 "TARGET_HIMODE_MATH"
8586 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8588 (define_insn "*andhi_1"
8589 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8590 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8591 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8592 (clobber (reg:CC 17))]
8593 "ix86_binary_operator_ok (AND, HImode, operands)"
8595 switch (get_attr_type (insn))
8598 if (GET_CODE (operands[2]) != CONST_INT)
8600 if (INTVAL (operands[2]) == 0xff)
8601 return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
8605 if (! rtx_equal_p (operands[0], operands[1]))
8608 return "and{w}\t{%2, %0|%0, %2}";
8611 [(set_attr "type" "alu,alu,imovx")
8612 (set_attr "length_immediate" "*,*,0")
8613 (set_attr "mode" "HI,HI,SI")])
8615 (define_insn "*andhi_2"
8617 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8618 (match_operand:HI 2 "general_operand" "rim,ri"))
8620 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8621 (and:HI (match_dup 1) (match_dup 2)))]
8622 "ix86_match_ccmode (insn, CCNOmode)
8623 && ix86_binary_operator_ok (AND, HImode, operands)"
8624 "and{w}\t{%2, %0|%0, %2}"
8625 [(set_attr "type" "alu")
8626 (set_attr "mode" "HI")])
8628 (define_expand "andqi3"
8629 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8630 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8631 (match_operand:QI 2 "general_operand" "")))
8632 (clobber (reg:CC 17))]
8633 "TARGET_QIMODE_MATH"
8634 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8636 ;; %%% Potential partial reg stall on alternative 2. What to do?
8637 (define_insn "*andqi_1"
8638 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8639 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8640 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8641 (clobber (reg:CC 17))]
8642 "ix86_binary_operator_ok (AND, QImode, operands)"
8644 and{b}\t{%2, %0|%0, %2}
8645 and{b}\t{%2, %0|%0, %2}
8646 and{l}\t{%k2, %k0|%k0, %k2}"
8647 [(set_attr "type" "alu")
8648 (set_attr "mode" "QI,QI,SI")])
8650 (define_insn "*andqi_1_slp"
8651 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8652 (and:QI (match_dup 0)
8653 (match_operand:QI 1 "general_operand" "qi,qmi")))
8654 (clobber (reg:CC 17))]
8655 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8656 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8657 "and{b}\t{%1, %0|%0, %1}"
8658 [(set_attr "type" "alu1")
8659 (set_attr "mode" "QI")])
8661 (define_insn "*andqi_2"
8664 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8665 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8667 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8668 (and:QI (match_dup 1) (match_dup 2)))]
8669 "ix86_match_ccmode (insn, CCNOmode)
8670 && ix86_binary_operator_ok (AND, QImode, operands)"
8672 if (which_alternative == 2)
8674 if (GET_CODE (operands[2]) == CONST_INT
8675 && (INTVAL (operands[2]) & 0xffffff00))
8676 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8677 return "and{l}\t{%2, %k0|%k0, %2}";
8679 return "and{b}\t{%2, %0|%0, %2}";
8681 [(set_attr "type" "alu")
8682 (set_attr "mode" "QI,QI,SI")])
8684 (define_insn "*andqi_2_slp"
8687 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8688 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8690 (set (strict_low_part (match_dup 0))
8691 (and:QI (match_dup 0) (match_dup 1)))]
8692 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8693 && ix86_match_ccmode (insn, CCNOmode)
8694 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8695 "and{b}\t{%1, %0|%0, %1}"
8696 [(set_attr "type" "alu1")
8697 (set_attr "mode" "QI")])
8699 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8700 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8701 ;; for a QImode operand, which of course failed.
8703 (define_insn "andqi_ext_0"
8704 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8709 (match_operand 1 "ext_register_operand" "0")
8712 (match_operand 2 "const_int_operand" "n")))
8713 (clobber (reg:CC 17))]
8715 "and{b}\t{%2, %h0|%h0, %2}"
8716 [(set_attr "type" "alu")
8717 (set_attr "length_immediate" "1")
8718 (set_attr "mode" "QI")])
8720 ;; Generated by peephole translating test to and. This shows up
8721 ;; often in fp comparisons.
8723 (define_insn "*andqi_ext_0_cc"
8728 (match_operand 1 "ext_register_operand" "0")
8731 (match_operand 2 "const_int_operand" "n"))
8733 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8742 "ix86_match_ccmode (insn, CCNOmode)"
8743 "and{b}\t{%2, %h0|%h0, %2}"
8744 [(set_attr "type" "alu")
8745 (set_attr "length_immediate" "1")
8746 (set_attr "mode" "QI")])
8748 (define_insn "*andqi_ext_1"
8749 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8754 (match_operand 1 "ext_register_operand" "0")
8758 (match_operand:QI 2 "general_operand" "Qm"))))
8759 (clobber (reg:CC 17))]
8761 "and{b}\t{%2, %h0|%h0, %2}"
8762 [(set_attr "type" "alu")
8763 (set_attr "length_immediate" "0")
8764 (set_attr "mode" "QI")])
8766 (define_insn "*andqi_ext_1_rex64"
8767 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8772 (match_operand 1 "ext_register_operand" "0")
8776 (match_operand 2 "ext_register_operand" "Q"))))
8777 (clobber (reg:CC 17))]
8779 "and{b}\t{%2, %h0|%h0, %2}"
8780 [(set_attr "type" "alu")
8781 (set_attr "length_immediate" "0")
8782 (set_attr "mode" "QI")])
8784 (define_insn "*andqi_ext_2"
8785 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8790 (match_operand 1 "ext_register_operand" "%0")
8794 (match_operand 2 "ext_register_operand" "Q")
8797 (clobber (reg:CC 17))]
8799 "and{b}\t{%h2, %h0|%h0, %h2}"
8800 [(set_attr "type" "alu")
8801 (set_attr "length_immediate" "0")
8802 (set_attr "mode" "QI")])
8804 ;; Convert wide AND instructions with immediate operand to shorter QImode
8805 ;; equivalents when possible.
8806 ;; Don't do the splitting with memory operands, since it introduces risk
8807 ;; of memory mismatch stalls. We may want to do the splitting for optimizing
8808 ;; for size, but that can (should?) be handled by generic code instead.
8810 [(set (match_operand 0 "register_operand" "")
8811 (and (match_operand 1 "register_operand" "")
8812 (match_operand 2 "const_int_operand" "")))
8813 (clobber (reg:CC 17))]
8815 && QI_REG_P (operands[0])
8816 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8817 && !(~INTVAL (operands[2]) & ~(255 << 8))
8818 && GET_MODE (operands[0]) != QImode"
8819 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8820 (and:SI (zero_extract:SI (match_dup 1)
8821 (const_int 8) (const_int 8))
8823 (clobber (reg:CC 17))])]
8824 "operands[0] = gen_lowpart (SImode, operands[0]);
8825 operands[1] = gen_lowpart (SImode, operands[1]);
8826 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8828 ;; Since AND can be encoded with sign extended immediate, this is only
8829 ;; profitable when 7th bit is not set.
8831 [(set (match_operand 0 "register_operand" "")
8832 (and (match_operand 1 "general_operand" "")
8833 (match_operand 2 "const_int_operand" "")))
8834 (clobber (reg:CC 17))]
8836 && ANY_QI_REG_P (operands[0])
8837 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8838 && !(~INTVAL (operands[2]) & ~255)
8839 && !(INTVAL (operands[2]) & 128)
8840 && GET_MODE (operands[0]) != QImode"
8841 [(parallel [(set (strict_low_part (match_dup 0))
8842 (and:QI (match_dup 1)
8844 (clobber (reg:CC 17))])]
8845 "operands[0] = gen_lowpart (QImode, operands[0]);
8846 operands[1] = gen_lowpart (QImode, operands[1]);
8847 operands[2] = gen_lowpart (QImode, operands[2]);")
8849 ;; Logical inclusive OR instructions
8851 ;; %%% This used to optimize known byte-wide and operations to memory.
8852 ;; If this is considered useful, it should be done with splitters.
8854 (define_expand "iordi3"
8855 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8856 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8857 (match_operand:DI 2 "x86_64_general_operand" "")))
8858 (clobber (reg:CC 17))]
8860 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8862 (define_insn "*iordi_1_rex64"
8863 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8864 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8865 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8866 (clobber (reg:CC 17))]
8868 && ix86_binary_operator_ok (IOR, DImode, operands)"
8869 "or{q}\t{%2, %0|%0, %2}"
8870 [(set_attr "type" "alu")
8871 (set_attr "mode" "DI")])
8873 (define_insn "*iordi_2_rex64"
8875 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8876 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8878 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8879 (ior:DI (match_dup 1) (match_dup 2)))]
8881 && ix86_match_ccmode (insn, CCNOmode)
8882 && ix86_binary_operator_ok (IOR, DImode, operands)"
8883 "or{q}\t{%2, %0|%0, %2}"
8884 [(set_attr "type" "alu")
8885 (set_attr "mode" "DI")])
8887 (define_insn "*iordi_3_rex64"
8889 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8890 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8892 (clobber (match_scratch:DI 0 "=r"))]
8894 && ix86_match_ccmode (insn, CCNOmode)
8895 && ix86_binary_operator_ok (IOR, DImode, operands)"
8896 "or{q}\t{%2, %0|%0, %2}"
8897 [(set_attr "type" "alu")
8898 (set_attr "mode" "DI")])
8901 (define_expand "iorsi3"
8902 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8903 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8904 (match_operand:SI 2 "general_operand" "")))
8905 (clobber (reg:CC 17))]
8907 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8909 (define_insn "*iorsi_1"
8910 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8911 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8912 (match_operand:SI 2 "general_operand" "ri,rmi")))
8913 (clobber (reg:CC 17))]
8914 "ix86_binary_operator_ok (IOR, SImode, operands)"
8915 "or{l}\t{%2, %0|%0, %2}"
8916 [(set_attr "type" "alu")
8917 (set_attr "mode" "SI")])
8919 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8920 (define_insn "*iorsi_1_zext"
8921 [(set (match_operand:DI 0 "register_operand" "=rm")
8923 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8924 (match_operand:SI 2 "general_operand" "rim"))))
8925 (clobber (reg:CC 17))]
8926 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8927 "or{l}\t{%2, %k0|%k0, %2}"
8928 [(set_attr "type" "alu")
8929 (set_attr "mode" "SI")])
8931 (define_insn "*iorsi_1_zext_imm"
8932 [(set (match_operand:DI 0 "register_operand" "=rm")
8933 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8934 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8935 (clobber (reg:CC 17))]
8937 "or{l}\t{%2, %k0|%k0, %2}"
8938 [(set_attr "type" "alu")
8939 (set_attr "mode" "SI")])
8941 (define_insn "*iorsi_2"
8943 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8944 (match_operand:SI 2 "general_operand" "rim,ri"))
8946 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8947 (ior:SI (match_dup 1) (match_dup 2)))]
8948 "ix86_match_ccmode (insn, CCNOmode)
8949 && ix86_binary_operator_ok (IOR, SImode, operands)"
8950 "or{l}\t{%2, %0|%0, %2}"
8951 [(set_attr "type" "alu")
8952 (set_attr "mode" "SI")])
8954 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8955 ;; ??? Special case for immediate operand is missing - it is tricky.
8956 (define_insn "*iorsi_2_zext"
8958 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8959 (match_operand:SI 2 "general_operand" "rim"))
8961 (set (match_operand:DI 0 "register_operand" "=r")
8962 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8963 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8964 && ix86_binary_operator_ok (IOR, SImode, operands)"
8965 "or{l}\t{%2, %k0|%k0, %2}"
8966 [(set_attr "type" "alu")
8967 (set_attr "mode" "SI")])
8969 (define_insn "*iorsi_2_zext_imm"
8971 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8972 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8974 (set (match_operand:DI 0 "register_operand" "=r")
8975 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8976 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8977 && ix86_binary_operator_ok (IOR, SImode, operands)"
8978 "or{l}\t{%2, %k0|%k0, %2}"
8979 [(set_attr "type" "alu")
8980 (set_attr "mode" "SI")])
8982 (define_insn "*iorsi_3"
8984 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8985 (match_operand:SI 2 "general_operand" "rim"))
8987 (clobber (match_scratch:SI 0 "=r"))]
8988 "ix86_match_ccmode (insn, CCNOmode)
8989 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8990 "or{l}\t{%2, %0|%0, %2}"
8991 [(set_attr "type" "alu")
8992 (set_attr "mode" "SI")])
8994 (define_expand "iorhi3"
8995 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8996 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
8997 (match_operand:HI 2 "general_operand" "")))
8998 (clobber (reg:CC 17))]
8999 "TARGET_HIMODE_MATH"
9000 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
9002 (define_insn "*iorhi_1"
9003 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
9004 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9005 (match_operand:HI 2 "general_operand" "rmi,ri")))
9006 (clobber (reg:CC 17))]
9007 "ix86_binary_operator_ok (IOR, HImode, operands)"
9008 "or{w}\t{%2, %0|%0, %2}"
9009 [(set_attr "type" "alu")
9010 (set_attr "mode" "HI")])
9012 (define_insn "*iorhi_2"
9014 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9015 (match_operand:HI 2 "general_operand" "rim,ri"))
9017 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9018 (ior:HI (match_dup 1) (match_dup 2)))]
9019 "ix86_match_ccmode (insn, CCNOmode)
9020 && ix86_binary_operator_ok (IOR, HImode, operands)"
9021 "or{w}\t{%2, %0|%0, %2}"
9022 [(set_attr "type" "alu")
9023 (set_attr "mode" "HI")])
9025 (define_insn "*iorhi_3"
9027 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9028 (match_operand:HI 2 "general_operand" "rim"))
9030 (clobber (match_scratch:HI 0 "=r"))]
9031 "ix86_match_ccmode (insn, CCNOmode)
9032 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9033 "or{w}\t{%2, %0|%0, %2}"
9034 [(set_attr "type" "alu")
9035 (set_attr "mode" "HI")])
9037 (define_expand "iorqi3"
9038 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9039 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
9040 (match_operand:QI 2 "general_operand" "")))
9041 (clobber (reg:CC 17))]
9042 "TARGET_QIMODE_MATH"
9043 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
9045 ;; %%% Potential partial reg stall on alternative 2. What to do?
9046 (define_insn "*iorqi_1"
9047 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9048 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9049 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9050 (clobber (reg:CC 17))]
9051 "ix86_binary_operator_ok (IOR, QImode, operands)"
9053 or{b}\t{%2, %0|%0, %2}
9054 or{b}\t{%2, %0|%0, %2}
9055 or{l}\t{%k2, %k0|%k0, %k2}"
9056 [(set_attr "type" "alu")
9057 (set_attr "mode" "QI,QI,SI")])
9059 (define_insn "*iorqi_1_slp"
9060 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
9061 (ior:QI (match_dup 0)
9062 (match_operand:QI 1 "general_operand" "qmi,qi")))
9063 (clobber (reg:CC 17))]
9064 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9065 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9066 "or{b}\t{%1, %0|%0, %1}"
9067 [(set_attr "type" "alu1")
9068 (set_attr "mode" "QI")])
9070 (define_insn "*iorqi_2"
9072 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9073 (match_operand:QI 2 "general_operand" "qim,qi"))
9075 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9076 (ior:QI (match_dup 1) (match_dup 2)))]
9077 "ix86_match_ccmode (insn, CCNOmode)
9078 && ix86_binary_operator_ok (IOR, QImode, operands)"
9079 "or{b}\t{%2, %0|%0, %2}"
9080 [(set_attr "type" "alu")
9081 (set_attr "mode" "QI")])
9083 (define_insn "*iorqi_2_slp"
9085 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
9086 (match_operand:QI 1 "general_operand" "qim,qi"))
9088 (set (strict_low_part (match_dup 0))
9089 (ior:QI (match_dup 0) (match_dup 1)))]
9090 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9091 && ix86_match_ccmode (insn, CCNOmode)
9092 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9093 "or{b}\t{%1, %0|%0, %1}"
9094 [(set_attr "type" "alu1")
9095 (set_attr "mode" "QI")])
9097 (define_insn "*iorqi_3"
9099 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9100 (match_operand:QI 2 "general_operand" "qim"))
9102 (clobber (match_scratch:QI 0 "=q"))]
9103 "ix86_match_ccmode (insn, CCNOmode)
9104 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9105 "or{b}\t{%2, %0|%0, %2}"
9106 [(set_attr "type" "alu")
9107 (set_attr "mode" "QI")])
9109 (define_insn "iorqi_ext_0"
9110 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9115 (match_operand 1 "ext_register_operand" "0")
9118 (match_operand 2 "const_int_operand" "n")))
9119 (clobber (reg:CC 17))]
9120 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9121 "or{b}\t{%2, %h0|%h0, %2}"
9122 [(set_attr "type" "alu")
9123 (set_attr "length_immediate" "1")
9124 (set_attr "mode" "QI")])
9126 (define_insn "*iorqi_ext_1"
9127 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9132 (match_operand 1 "ext_register_operand" "0")
9136 (match_operand:QI 2 "general_operand" "Qm"))))
9137 (clobber (reg:CC 17))]
9139 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9140 "or{b}\t{%2, %h0|%h0, %2}"
9141 [(set_attr "type" "alu")
9142 (set_attr "length_immediate" "0")
9143 (set_attr "mode" "QI")])
9145 (define_insn "*iorqi_ext_1_rex64"
9146 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9151 (match_operand 1 "ext_register_operand" "0")
9155 (match_operand 2 "ext_register_operand" "Q"))))
9156 (clobber (reg:CC 17))]
9158 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9159 "or{b}\t{%2, %h0|%h0, %2}"
9160 [(set_attr "type" "alu")
9161 (set_attr "length_immediate" "0")
9162 (set_attr "mode" "QI")])
9164 (define_insn "*iorqi_ext_2"
9165 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9169 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9172 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9175 (clobber (reg:CC 17))]
9176 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9177 "ior{b}\t{%h2, %h0|%h0, %h2}"
9178 [(set_attr "type" "alu")
9179 (set_attr "length_immediate" "0")
9180 (set_attr "mode" "QI")])
9183 [(set (match_operand 0 "register_operand" "")
9184 (ior (match_operand 1 "register_operand" "")
9185 (match_operand 2 "const_int_operand" "")))
9186 (clobber (reg:CC 17))]
9188 && QI_REG_P (operands[0])
9189 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9190 && !(INTVAL (operands[2]) & ~(255 << 8))
9191 && GET_MODE (operands[0]) != QImode"
9192 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9193 (ior:SI (zero_extract:SI (match_dup 1)
9194 (const_int 8) (const_int 8))
9196 (clobber (reg:CC 17))])]
9197 "operands[0] = gen_lowpart (SImode, operands[0]);
9198 operands[1] = gen_lowpart (SImode, operands[1]);
9199 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9201 ;; Since OR can be encoded with sign extended immediate, this is only
9202 ;; profitable when 7th bit is set.
9204 [(set (match_operand 0 "register_operand" "")
9205 (ior (match_operand 1 "general_operand" "")
9206 (match_operand 2 "const_int_operand" "")))
9207 (clobber (reg:CC 17))]
9209 && ANY_QI_REG_P (operands[0])
9210 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9211 && !(INTVAL (operands[2]) & ~255)
9212 && (INTVAL (operands[2]) & 128)
9213 && GET_MODE (operands[0]) != QImode"
9214 [(parallel [(set (strict_low_part (match_dup 0))
9215 (ior:QI (match_dup 1)
9217 (clobber (reg:CC 17))])]
9218 "operands[0] = gen_lowpart (QImode, operands[0]);
9219 operands[1] = gen_lowpart (QImode, operands[1]);
9220 operands[2] = gen_lowpart (QImode, operands[2]);")
9222 ;; Logical XOR instructions
9224 ;; %%% This used to optimize known byte-wide and operations to memory.
9225 ;; If this is considered useful, it should be done with splitters.
9227 (define_expand "xordi3"
9228 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9229 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
9230 (match_operand:DI 2 "x86_64_general_operand" "")))
9231 (clobber (reg:CC 17))]
9233 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
9235 (define_insn "*xordi_1_rex64"
9236 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
9237 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
9238 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
9239 (clobber (reg:CC 17))]
9241 && ix86_binary_operator_ok (XOR, DImode, operands)"
9243 xor{q}\t{%2, %0|%0, %2}
9244 xor{q}\t{%2, %0|%0, %2}"
9245 [(set_attr "type" "alu")
9246 (set_attr "mode" "DI,DI")])
9248 (define_insn "*xordi_2_rex64"
9250 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
9251 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
9253 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
9254 (xor:DI (match_dup 1) (match_dup 2)))]
9256 && ix86_match_ccmode (insn, CCNOmode)
9257 && ix86_binary_operator_ok (XOR, DImode, operands)"
9259 xor{q}\t{%2, %0|%0, %2}
9260 xor{q}\t{%2, %0|%0, %2}"
9261 [(set_attr "type" "alu")
9262 (set_attr "mode" "DI,DI")])
9264 (define_insn "*xordi_3_rex64"
9266 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
9267 (match_operand:DI 2 "x86_64_general_operand" "rem"))
9269 (clobber (match_scratch:DI 0 "=r"))]
9271 && ix86_match_ccmode (insn, CCNOmode)
9272 && ix86_binary_operator_ok (XOR, DImode, operands)"
9273 "xor{q}\t{%2, %0|%0, %2}"
9274 [(set_attr "type" "alu")
9275 (set_attr "mode" "DI")])
9277 (define_expand "xorsi3"
9278 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9279 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
9280 (match_operand:SI 2 "general_operand" "")))
9281 (clobber (reg:CC 17))]
9283 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
9285 (define_insn "*xorsi_1"
9286 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
9287 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9288 (match_operand:SI 2 "general_operand" "ri,rm")))
9289 (clobber (reg:CC 17))]
9290 "ix86_binary_operator_ok (XOR, SImode, operands)"
9291 "xor{l}\t{%2, %0|%0, %2}"
9292 [(set_attr "type" "alu")
9293 (set_attr "mode" "SI")])
9295 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9296 ;; Add speccase for immediates
9297 (define_insn "*xorsi_1_zext"
9298 [(set (match_operand:DI 0 "register_operand" "=r")
9300 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9301 (match_operand:SI 2 "general_operand" "rim"))))
9302 (clobber (reg:CC 17))]
9303 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9304 "xor{l}\t{%2, %k0|%k0, %2}"
9305 [(set_attr "type" "alu")
9306 (set_attr "mode" "SI")])
9308 (define_insn "*xorsi_1_zext_imm"
9309 [(set (match_operand:DI 0 "register_operand" "=r")
9310 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
9311 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
9312 (clobber (reg:CC 17))]
9313 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9314 "xor{l}\t{%2, %k0|%k0, %2}"
9315 [(set_attr "type" "alu")
9316 (set_attr "mode" "SI")])
9318 (define_insn "*xorsi_2"
9320 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9321 (match_operand:SI 2 "general_operand" "rim,ri"))
9323 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
9324 (xor:SI (match_dup 1) (match_dup 2)))]
9325 "ix86_match_ccmode (insn, CCNOmode)
9326 && ix86_binary_operator_ok (XOR, SImode, operands)"
9327 "xor{l}\t{%2, %0|%0, %2}"
9328 [(set_attr "type" "alu")
9329 (set_attr "mode" "SI")])
9331 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9332 ;; ??? Special case for immediate operand is missing - it is tricky.
9333 (define_insn "*xorsi_2_zext"
9335 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9336 (match_operand:SI 2 "general_operand" "rim"))
9338 (set (match_operand:DI 0 "register_operand" "=r")
9339 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
9340 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9341 && ix86_binary_operator_ok (XOR, SImode, operands)"
9342 "xor{l}\t{%2, %k0|%k0, %2}"
9343 [(set_attr "type" "alu")
9344 (set_attr "mode" "SI")])
9346 (define_insn "*xorsi_2_zext_imm"
9348 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9349 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
9351 (set (match_operand:DI 0 "register_operand" "=r")
9352 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
9353 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9354 && ix86_binary_operator_ok (XOR, SImode, operands)"
9355 "xor{l}\t{%2, %k0|%k0, %2}"
9356 [(set_attr "type" "alu")
9357 (set_attr "mode" "SI")])
9359 (define_insn "*xorsi_3"
9361 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9362 (match_operand:SI 2 "general_operand" "rim"))
9364 (clobber (match_scratch:SI 0 "=r"))]
9365 "ix86_match_ccmode (insn, CCNOmode)
9366 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9367 "xor{l}\t{%2, %0|%0, %2}"
9368 [(set_attr "type" "alu")
9369 (set_attr "mode" "SI")])
9371 (define_expand "xorhi3"
9372 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9373 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
9374 (match_operand:HI 2 "general_operand" "")))
9375 (clobber (reg:CC 17))]
9376 "TARGET_HIMODE_MATH"
9377 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
9379 (define_insn "*xorhi_1"
9380 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
9381 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9382 (match_operand:HI 2 "general_operand" "rmi,ri")))
9383 (clobber (reg:CC 17))]
9384 "ix86_binary_operator_ok (XOR, HImode, operands)"
9385 "xor{w}\t{%2, %0|%0, %2}"
9386 [(set_attr "type" "alu")
9387 (set_attr "mode" "HI")])
9389 (define_insn "*xorhi_2"
9391 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9392 (match_operand:HI 2 "general_operand" "rim,ri"))
9394 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9395 (xor:HI (match_dup 1) (match_dup 2)))]
9396 "ix86_match_ccmode (insn, CCNOmode)
9397 && ix86_binary_operator_ok (XOR, HImode, operands)"
9398 "xor{w}\t{%2, %0|%0, %2}"
9399 [(set_attr "type" "alu")
9400 (set_attr "mode" "HI")])
9402 (define_insn "*xorhi_3"
9404 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9405 (match_operand:HI 2 "general_operand" "rim"))
9407 (clobber (match_scratch:HI 0 "=r"))]
9408 "ix86_match_ccmode (insn, CCNOmode)
9409 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9410 "xor{w}\t{%2, %0|%0, %2}"
9411 [(set_attr "type" "alu")
9412 (set_attr "mode" "HI")])
9414 (define_expand "xorqi3"
9415 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9416 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
9417 (match_operand:QI 2 "general_operand" "")))
9418 (clobber (reg:CC 17))]
9419 "TARGET_QIMODE_MATH"
9420 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
9422 ;; %%% Potential partial reg stall on alternative 2. What to do?
9423 (define_insn "*xorqi_1"
9424 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9425 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9426 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9427 (clobber (reg:CC 17))]
9428 "ix86_binary_operator_ok (XOR, QImode, operands)"
9430 xor{b}\t{%2, %0|%0, %2}
9431 xor{b}\t{%2, %0|%0, %2}
9432 xor{l}\t{%k2, %k0|%k0, %k2}"
9433 [(set_attr "type" "alu")
9434 (set_attr "mode" "QI,QI,SI")])
9436 (define_insn "*xorqi_1_slp"
9437 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
9438 (xor:QI (match_dup 0)
9439 (match_operand:QI 1 "general_operand" "qi,qmi")))
9440 (clobber (reg:CC 17))]
9441 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9442 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9443 "xor{b}\t{%1, %0|%0, %1}"
9444 [(set_attr "type" "alu1")
9445 (set_attr "mode" "QI")])
9447 (define_insn "xorqi_ext_0"
9448 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9453 (match_operand 1 "ext_register_operand" "0")
9456 (match_operand 2 "const_int_operand" "n")))
9457 (clobber (reg:CC 17))]
9458 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9459 "xor{b}\t{%2, %h0|%h0, %2}"
9460 [(set_attr "type" "alu")
9461 (set_attr "length_immediate" "1")
9462 (set_attr "mode" "QI")])
9464 (define_insn "*xorqi_ext_1"
9465 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9470 (match_operand 1 "ext_register_operand" "0")
9474 (match_operand:QI 2 "general_operand" "Qm"))))
9475 (clobber (reg:CC 17))]
9477 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9478 "xor{b}\t{%2, %h0|%h0, %2}"
9479 [(set_attr "type" "alu")
9480 (set_attr "length_immediate" "0")
9481 (set_attr "mode" "QI")])
9483 (define_insn "*xorqi_ext_1_rex64"
9484 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9489 (match_operand 1 "ext_register_operand" "0")
9493 (match_operand 2 "ext_register_operand" "Q"))))
9494 (clobber (reg:CC 17))]
9496 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9497 "xor{b}\t{%2, %h0|%h0, %2}"
9498 [(set_attr "type" "alu")
9499 (set_attr "length_immediate" "0")
9500 (set_attr "mode" "QI")])
9502 (define_insn "*xorqi_ext_2"
9503 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9507 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9510 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9513 (clobber (reg:CC 17))]
9514 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9515 "xor{b}\t{%h2, %h0|%h0, %h2}"
9516 [(set_attr "type" "alu")
9517 (set_attr "length_immediate" "0")
9518 (set_attr "mode" "QI")])
9520 (define_insn "*xorqi_cc_1"
9523 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9524 (match_operand:QI 2 "general_operand" "qim,qi"))
9526 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9527 (xor:QI (match_dup 1) (match_dup 2)))]
9528 "ix86_match_ccmode (insn, CCNOmode)
9529 && ix86_binary_operator_ok (XOR, QImode, operands)"
9530 "xor{b}\t{%2, %0|%0, %2}"
9531 [(set_attr "type" "alu")
9532 (set_attr "mode" "QI")])
9534 (define_insn "*xorqi_2_slp"
9536 (compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
9537 (match_operand:QI 1 "general_operand" "qim,qi"))
9539 (set (strict_low_part (match_dup 0))
9540 (xor:QI (match_dup 0) (match_dup 1)))]
9541 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9542 && ix86_match_ccmode (insn, CCNOmode)
9543 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9544 "xor{b}\t{%1, %0|%0, %1}"
9545 [(set_attr "type" "alu1")
9546 (set_attr "mode" "QI")])
9548 (define_insn "*xorqi_cc_2"
9551 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9552 (match_operand:QI 2 "general_operand" "qim"))
9554 (clobber (match_scratch:QI 0 "=q"))]
9555 "ix86_match_ccmode (insn, CCNOmode)
9556 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9557 "xor{b}\t{%2, %0|%0, %2}"
9558 [(set_attr "type" "alu")
9559 (set_attr "mode" "QI")])
9561 (define_insn "*xorqi_cc_ext_1"
9566 (match_operand 1 "ext_register_operand" "0")
9569 (match_operand:QI 2 "general_operand" "qmn"))
9571 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
9575 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9577 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9578 "xor{b}\t{%2, %h0|%h0, %2}"
9579 [(set_attr "type" "alu")
9580 (set_attr "mode" "QI")])
9582 (define_insn "*xorqi_cc_ext_1_rex64"
9587 (match_operand 1 "ext_register_operand" "0")
9590 (match_operand:QI 2 "nonmemory_operand" "Qn"))
9592 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9596 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9598 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9599 "xor{b}\t{%2, %h0|%h0, %2}"
9600 [(set_attr "type" "alu")
9601 (set_attr "mode" "QI")])
9603 (define_expand "xorqi_cc_ext_1"
9609 (match_operand 1 "ext_register_operand" "")
9612 (match_operand:QI 2 "general_operand" ""))
9614 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9618 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9624 [(set (match_operand 0 "register_operand" "")
9625 (xor (match_operand 1 "register_operand" "")
9626 (match_operand 2 "const_int_operand" "")))
9627 (clobber (reg:CC 17))]
9629 && QI_REG_P (operands[0])
9630 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9631 && !(INTVAL (operands[2]) & ~(255 << 8))
9632 && GET_MODE (operands[0]) != QImode"
9633 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9634 (xor:SI (zero_extract:SI (match_dup 1)
9635 (const_int 8) (const_int 8))
9637 (clobber (reg:CC 17))])]
9638 "operands[0] = gen_lowpart (SImode, operands[0]);
9639 operands[1] = gen_lowpart (SImode, operands[1]);
9640 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9642 ;; Since XOR can be encoded with sign extended immediate, this is only
9643 ;; profitable when 7th bit is set.
9645 [(set (match_operand 0 "register_operand" "")
9646 (xor (match_operand 1 "general_operand" "")
9647 (match_operand 2 "const_int_operand" "")))
9648 (clobber (reg:CC 17))]
9650 && ANY_QI_REG_P (operands[0])
9651 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9652 && !(INTVAL (operands[2]) & ~255)
9653 && (INTVAL (operands[2]) & 128)
9654 && GET_MODE (operands[0]) != QImode"
9655 [(parallel [(set (strict_low_part (match_dup 0))
9656 (xor:QI (match_dup 1)
9658 (clobber (reg:CC 17))])]
9659 "operands[0] = gen_lowpart (QImode, operands[0]);
9660 operands[1] = gen_lowpart (QImode, operands[1]);
9661 operands[2] = gen_lowpart (QImode, operands[2]);")
9663 ;; Negation instructions
9665 (define_expand "negdi2"
9666 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
9667 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
9668 (clobber (reg:CC 17))])]
9670 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
9672 (define_insn "*negdi2_1"
9673 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
9674 (neg:DI (match_operand:DI 1 "general_operand" "0")))
9675 (clobber (reg:CC 17))]
9677 && ix86_unary_operator_ok (NEG, DImode, operands)"
9681 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9682 (neg:DI (match_operand:DI 1 "general_operand" "")))
9683 (clobber (reg:CC 17))]
9684 "!TARGET_64BIT && reload_completed"
9687 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
9688 (set (match_dup 0) (neg:SI (match_dup 2)))])
9691 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
9694 (clobber (reg:CC 17))])
9697 (neg:SI (match_dup 1)))
9698 (clobber (reg:CC 17))])]
9699 "split_di (operands+1, 1, operands+2, operands+3);
9700 split_di (operands+0, 1, operands+0, operands+1);")
9702 (define_insn "*negdi2_1_rex64"
9703 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9704 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
9705 (clobber (reg:CC 17))]
9706 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9708 [(set_attr "type" "negnot")
9709 (set_attr "mode" "DI")])
9711 ;; The problem with neg is that it does not perform (compare x 0),
9712 ;; it really performs (compare 0 x), which leaves us with the zero
9713 ;; flag being the only useful item.
9715 (define_insn "*negdi2_cmpz_rex64"
9717 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9719 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9720 (neg:DI (match_dup 1)))]
9721 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9723 [(set_attr "type" "negnot")
9724 (set_attr "mode" "DI")])
9727 (define_expand "negsi2"
9728 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
9729 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
9730 (clobber (reg:CC 17))])]
9732 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
9734 (define_insn "*negsi2_1"
9735 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9736 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
9737 (clobber (reg:CC 17))]
9738 "ix86_unary_operator_ok (NEG, SImode, operands)"
9740 [(set_attr "type" "negnot")
9741 (set_attr "mode" "SI")])
9743 ;; Combine is quite creative about this pattern.
9744 (define_insn "*negsi2_1_zext"
9745 [(set (match_operand:DI 0 "register_operand" "=r")
9746 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
9749 (clobber (reg:CC 17))]
9750 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9752 [(set_attr "type" "negnot")
9753 (set_attr "mode" "SI")])
9755 ;; The problem with neg is that it does not perform (compare x 0),
9756 ;; it really performs (compare 0 x), which leaves us with the zero
9757 ;; flag being the only useful item.
9759 (define_insn "*negsi2_cmpz"
9761 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9763 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9764 (neg:SI (match_dup 1)))]
9765 "ix86_unary_operator_ok (NEG, SImode, operands)"
9767 [(set_attr "type" "negnot")
9768 (set_attr "mode" "SI")])
9770 (define_insn "*negsi2_cmpz_zext"
9772 (compare:CCZ (lshiftrt:DI
9774 (match_operand:DI 1 "register_operand" "0")
9778 (set (match_operand:DI 0 "register_operand" "=r")
9779 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
9782 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9784 [(set_attr "type" "negnot")
9785 (set_attr "mode" "SI")])
9787 (define_expand "neghi2"
9788 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
9789 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
9790 (clobber (reg:CC 17))])]
9791 "TARGET_HIMODE_MATH"
9792 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
9794 (define_insn "*neghi2_1"
9795 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9796 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
9797 (clobber (reg:CC 17))]
9798 "ix86_unary_operator_ok (NEG, HImode, operands)"
9800 [(set_attr "type" "negnot")
9801 (set_attr "mode" "HI")])
9803 (define_insn "*neghi2_cmpz"
9805 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9807 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9808 (neg:HI (match_dup 1)))]
9809 "ix86_unary_operator_ok (NEG, HImode, operands)"
9811 [(set_attr "type" "negnot")
9812 (set_attr "mode" "HI")])
9814 (define_expand "negqi2"
9815 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
9816 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
9817 (clobber (reg:CC 17))])]
9818 "TARGET_QIMODE_MATH"
9819 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
9821 (define_insn "*negqi2_1"
9822 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9823 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
9824 (clobber (reg:CC 17))]
9825 "ix86_unary_operator_ok (NEG, QImode, operands)"
9827 [(set_attr "type" "negnot")
9828 (set_attr "mode" "QI")])
9830 (define_insn "*negqi2_cmpz"
9832 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9834 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9835 (neg:QI (match_dup 1)))]
9836 "ix86_unary_operator_ok (NEG, QImode, operands)"
9838 [(set_attr "type" "negnot")
9839 (set_attr "mode" "QI")])
9841 ;; Changing of sign for FP values is doable using integer unit too.
9843 (define_expand "negsf2"
9844 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9845 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9846 (clobber (reg:CC 17))])]
9850 /* In case operand is in memory, we will not use SSE. */
9851 if (memory_operand (operands[0], VOIDmode)
9852 && rtx_equal_p (operands[0], operands[1]))
9853 emit_insn (gen_negsf2_memory (operands[0], operands[1]));
9856 /* Using SSE is tricky, since we need bitwise negation of -0
9858 rtx reg = gen_reg_rtx (SFmode);
9859 rtx dest = operands[0];
9860 rtx imm = gen_lowpart (SFmode, gen_int_mode (0x80000000, SImode));
9862 operands[1] = force_reg (SFmode, operands[1]);
9863 operands[0] = force_reg (SFmode, operands[0]);
9864 reg = force_reg (V4SFmode,
9865 gen_rtx_CONST_VECTOR (V4SFmode,
9866 gen_rtvec (4, imm, CONST0_RTX (SFmode),
9867 CONST0_RTX (SFmode),
9868 CONST0_RTX (SFmode))));
9869 emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg));
9870 if (dest != operands[0])
9871 emit_move_insn (dest, operands[0]);
9875 ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
9877 (define_insn "negsf2_memory"
9878 [(set (match_operand:SF 0 "memory_operand" "=m")
9879 (neg:SF (match_operand:SF 1 "memory_operand" "0")))
9880 (clobber (reg:CC 17))]
9881 "ix86_unary_operator_ok (NEG, SFmode, operands)"
9884 (define_insn "negsf2_ifs"
9885 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
9886 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
9887 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
9888 (clobber (reg:CC 17))]
9890 && (reload_in_progress || reload_completed
9891 || (register_operand (operands[0], VOIDmode)
9892 && register_operand (operands[1], VOIDmode)))"
9896 [(set (match_operand:SF 0 "memory_operand" "")
9897 (neg:SF (match_operand:SF 1 "memory_operand" "")))
9898 (use (match_operand:SF 2 "" ""))
9899 (clobber (reg:CC 17))]
9901 [(parallel [(set (match_dup 0)
9902 (neg:SF (match_dup 1)))
9903 (clobber (reg:CC 17))])])
9906 [(set (match_operand:SF 0 "register_operand" "")
9907 (neg:SF (match_operand:SF 1 "register_operand" "")))
9908 (use (match_operand:V4SF 2 "" ""))
9909 (clobber (reg:CC 17))]
9910 "reload_completed && !SSE_REG_P (operands[0])"
9911 [(parallel [(set (match_dup 0)
9912 (neg:SF (match_dup 1)))
9913 (clobber (reg:CC 17))])])
9916 [(set (match_operand:SF 0 "register_operand" "")
9917 (neg:SF (match_operand:SF 1 "register_operand" "")))
9918 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
9919 (clobber (reg:CC 17))]
9920 "reload_completed && SSE_REG_P (operands[0])"
9921 [(set (subreg:TI (match_dup 0) 0)
9922 (xor:TI (match_dup 1)
9925 operands[1] = simplify_gen_subreg (TImode, operands[1], SFmode, 0);
9926 operands[2] = simplify_gen_subreg (TImode, operands[2], V4SFmode, 0);
9927 if (operands_match_p (operands[0], operands[2]))
9931 operands[1] = operands[2];
9937 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9938 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9940 (define_insn "*negsf2_if"
9941 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9942 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9943 (clobber (reg:CC 17))]
9944 "TARGET_80387 && !TARGET_SSE
9945 && ix86_unary_operator_ok (NEG, SFmode, operands)"
9949 [(set (match_operand:SF 0 "fp_register_operand" "")
9950 (neg:SF (match_operand:SF 1 "register_operand" "")))
9951 (clobber (reg:CC 17))]
9952 "TARGET_80387 && reload_completed"
9954 (neg:SF (match_dup 1)))]
9958 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
9959 (neg:SF (match_operand:SF 1 "register_operand" "")))
9960 (clobber (reg:CC 17))]
9961 "TARGET_80387 && reload_completed"
9962 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9963 (clobber (reg:CC 17))])]
9964 "operands[1] = gen_int_mode (0x80000000, SImode);
9965 operands[0] = gen_lowpart (SImode, operands[0]);")
9968 [(set (match_operand 0 "memory_operand" "")
9969 (neg (match_operand 1 "memory_operand" "")))
9970 (clobber (reg:CC 17))]
9971 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9972 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
9973 (clobber (reg:CC 17))])]
9975 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9977 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9980 operands[0] = adjust_address (operands[0], QImode, size - 1);
9981 operands[1] = gen_int_mode (0x80, QImode);
9984 (define_expand "negdf2"
9985 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9986 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9987 (clobber (reg:CC 17))])]
9991 /* In case operand is in memory, we will not use SSE. */
9992 if (memory_operand (operands[0], VOIDmode)
9993 && rtx_equal_p (operands[0], operands[1]))
9994 emit_insn (gen_negdf2_memory (operands[0], operands[1]));
9997 /* Using SSE is tricky, since we need bitwise negation of -0
10000 #if HOST_BITS_PER_WIDE_INT >= 64
10001 rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
10003 rtx imm = immed_double_const (0, 0x80000000, DImode);
10005 rtx dest = operands[0];
10007 operands[1] = force_reg (DFmode, operands[1]);
10008 operands[0] = force_reg (DFmode, operands[0]);
10009 imm = gen_lowpart (DFmode, imm);
10010 reg = force_reg (V2DFmode,
10011 gen_rtx_CONST_VECTOR (V2DFmode,
10012 gen_rtvec (2, imm, CONST0_RTX (DFmode))));
10013 emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg));
10014 if (dest != operands[0])
10015 emit_move_insn (dest, operands[0]);
10019 ix86_expand_unary_operator (NEG, DFmode, operands); DONE;")
10021 (define_insn "negdf2_memory"
10022 [(set (match_operand:DF 0 "memory_operand" "=m")
10023 (neg:DF (match_operand:DF 1 "memory_operand" "0")))
10024 (clobber (reg:CC 17))]
10025 "ix86_unary_operator_ok (NEG, DFmode, operands)"
10028 (define_insn "negdf2_ifs"
10029 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
10030 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
10031 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
10032 (clobber (reg:CC 17))]
10033 "!TARGET_64BIT && TARGET_SSE2
10034 && (reload_in_progress || reload_completed
10035 || (register_operand (operands[0], VOIDmode)
10036 && register_operand (operands[1], VOIDmode)))"
10039 (define_insn "*negdf2_ifs_rex64"
10040 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#f,Y#f,fm#Y")
10041 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
10042 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
10043 (clobber (reg:CC 17))]
10044 "TARGET_64BIT && TARGET_SSE2
10045 && (reload_in_progress || reload_completed
10046 || (register_operand (operands[0], VOIDmode)
10047 && register_operand (operands[1], VOIDmode)))"
10051 [(set (match_operand:DF 0 "memory_operand" "")
10052 (neg:DF (match_operand:DF 1 "memory_operand" "")))
10053 (use (match_operand:V2DF 2 "" ""))
10054 (clobber (reg:CC 17))]
10056 [(parallel [(set (match_dup 0)
10057 (neg:DF (match_dup 1)))
10058 (clobber (reg:CC 17))])])
10061 [(set (match_operand:DF 0 "register_operand" "")
10062 (neg:DF (match_operand:DF 1 "register_operand" "")))
10063 (use (match_operand:V2DF 2 "" ""))
10064 (clobber (reg:CC 17))]
10065 "reload_completed && !SSE_REG_P (operands[0])
10066 && (!TARGET_64BIT || FP_REG_P (operands[0]))"
10067 [(parallel [(set (match_dup 0)
10068 (neg:DF (match_dup 1)))
10069 (clobber (reg:CC 17))])])
10072 [(set (match_operand:DF 0 "register_operand" "")
10073 (neg:DF (match_operand:DF 1 "register_operand" "")))
10074 (use (match_operand:V2DF 2 "" ""))
10075 (clobber (reg:CC 17))]
10076 "TARGET_64BIT && reload_completed && GENERAL_REG_P (operands[0])"
10077 [(parallel [(set (match_dup 0)
10078 (xor:DI (match_dup 1) (match_dup 2)))
10079 (clobber (reg:CC 17))])]
10080 "operands[0] = gen_lowpart (DImode, operands[0]);
10081 operands[1] = gen_lowpart (DImode, operands[1]);
10082 operands[2] = gen_lowpart (DImode, operands[2]);")
10085 [(set (match_operand:DF 0 "register_operand" "")
10086 (neg:DF (match_operand:DF 1 "register_operand" "")))
10087 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
10088 (clobber (reg:CC 17))]
10089 "reload_completed && SSE_REG_P (operands[0])"
10090 [(set (subreg:TI (match_dup 0) 0)
10091 (xor:TI (match_dup 1)
10094 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
10095 operands[1] = simplify_gen_subreg (TImode, operands[1], DFmode, 0);
10096 operands[2] = simplify_gen_subreg (TImode, operands[2], V2DFmode, 0);
10097 /* Avoid possible reformatting on the operands. */
10098 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
10099 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
10100 if (operands_match_p (operands[0], operands[2]))
10104 operands[1] = operands[2];
10109 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10110 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10112 (define_insn "*negdf2_if"
10113 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
10114 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10115 (clobber (reg:CC 17))]
10116 "!TARGET_64BIT && TARGET_80387
10117 && ix86_unary_operator_ok (NEG, DFmode, operands)"
10120 ;; FIXME: We should to allow integer registers here. Problem is that
10121 ;; we need another scratch register to get constant from.
10122 ;; Forcing constant to mem if no register available in peep2 should be
10123 ;; safe even for PIC mode, because of RIP relative addressing.
10124 (define_insn "*negdf2_if_rex64"
10125 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
10126 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10127 (clobber (reg:CC 17))]
10128 "TARGET_64BIT && TARGET_80387
10129 && ix86_unary_operator_ok (NEG, DFmode, operands)"
10133 [(set (match_operand:DF 0 "fp_register_operand" "")
10134 (neg:DF (match_operand:DF 1 "register_operand" "")))
10135 (clobber (reg:CC 17))]
10136 "TARGET_80387 && reload_completed"
10137 [(set (match_dup 0)
10138 (neg:DF (match_dup 1)))]
10142 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
10143 (neg:DF (match_operand:DF 1 "register_operand" "")))
10144 (clobber (reg:CC 17))]
10145 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10146 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
10147 (clobber (reg:CC 17))])]
10148 "operands[4] = gen_int_mode (0x80000000, SImode);
10149 split_di (operands+0, 1, operands+2, operands+3);")
10151 (define_expand "negxf2"
10152 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
10153 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
10154 (clobber (reg:CC 17))])]
10155 "!TARGET_64BIT && TARGET_80387"
10156 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
10158 (define_expand "negtf2"
10159 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
10160 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
10161 (clobber (reg:CC 17))])]
10163 "ix86_expand_unary_operator (NEG, TFmode, operands); DONE;")
10165 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10166 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10168 (define_insn "*negxf2_if"
10169 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
10170 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
10171 (clobber (reg:CC 17))]
10172 "!TARGET_64BIT && TARGET_80387
10173 && ix86_unary_operator_ok (NEG, XFmode, operands)"
10177 [(set (match_operand:XF 0 "fp_register_operand" "")
10178 (neg:XF (match_operand:XF 1 "register_operand" "")))
10179 (clobber (reg:CC 17))]
10180 "TARGET_80387 && reload_completed"
10181 [(set (match_dup 0)
10182 (neg:XF (match_dup 1)))]
10186 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
10187 (neg:XF (match_operand:XF 1 "register_operand" "")))
10188 (clobber (reg:CC 17))]
10189 "TARGET_80387 && reload_completed"
10190 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
10191 (clobber (reg:CC 17))])]
10192 "operands[1] = GEN_INT (0x8000);
10193 operands[0] = gen_rtx_REG (SImode,
10194 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10196 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10197 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10199 (define_insn "*negtf2_if"
10200 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
10201 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
10202 (clobber (reg:CC 17))]
10203 "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)"
10207 [(set (match_operand:TF 0 "fp_register_operand" "")
10208 (neg:TF (match_operand:TF 1 "register_operand" "")))
10209 (clobber (reg:CC 17))]
10210 "TARGET_80387 && reload_completed"
10211 [(set (match_dup 0)
10212 (neg:TF (match_dup 1)))]
10216 [(set (match_operand:TF 0 "register_and_not_fp_reg_operand" "")
10217 (neg:TF (match_operand:TF 1 "register_operand" "")))
10218 (clobber (reg:CC 17))]
10219 "TARGET_80387 && reload_completed"
10220 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
10221 (clobber (reg:CC 17))])]
10222 "operands[1] = GEN_INT (0x8000);
10223 operands[0] = gen_rtx_REG (SImode,
10224 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10226 ;; Conditionalize these after reload. If they matches before reload, we
10227 ;; lose the clobber and ability to use integer instructions.
10229 (define_insn "*negsf2_1"
10230 [(set (match_operand:SF 0 "register_operand" "=f")
10231 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
10232 "TARGET_80387 && reload_completed"
10234 [(set_attr "type" "fsgn")
10235 (set_attr "mode" "SF")
10236 (set_attr "ppro_uops" "few")])
10238 (define_insn "*negdf2_1"
10239 [(set (match_operand:DF 0 "register_operand" "=f")
10240 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
10241 "TARGET_80387 && reload_completed"
10243 [(set_attr "type" "fsgn")
10244 (set_attr "mode" "DF")
10245 (set_attr "ppro_uops" "few")])
10247 (define_insn "*negextendsfdf2"
10248 [(set (match_operand:DF 0 "register_operand" "=f")
10249 (neg:DF (float_extend:DF
10250 (match_operand:SF 1 "register_operand" "0"))))]
10253 [(set_attr "type" "fsgn")
10254 (set_attr "mode" "DF")
10255 (set_attr "ppro_uops" "few")])
10257 (define_insn "*negxf2_1"
10258 [(set (match_operand:XF 0 "register_operand" "=f")
10259 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
10260 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10262 [(set_attr "type" "fsgn")
10263 (set_attr "mode" "XF")
10264 (set_attr "ppro_uops" "few")])
10266 (define_insn "*negextenddfxf2"
10267 [(set (match_operand:XF 0 "register_operand" "=f")
10268 (neg:XF (float_extend:XF
10269 (match_operand:DF 1 "register_operand" "0"))))]
10270 "!TARGET_64BIT && TARGET_80387"
10272 [(set_attr "type" "fsgn")
10273 (set_attr "mode" "XF")
10274 (set_attr "ppro_uops" "few")])
10276 (define_insn "*negextendsfxf2"
10277 [(set (match_operand:XF 0 "register_operand" "=f")
10278 (neg:XF (float_extend:XF
10279 (match_operand:SF 1 "register_operand" "0"))))]
10280 "!TARGET_64BIT && TARGET_80387"
10282 [(set_attr "type" "fsgn")
10283 (set_attr "mode" "XF")
10284 (set_attr "ppro_uops" "few")])
10286 (define_insn "*negtf2_1"
10287 [(set (match_operand:TF 0 "register_operand" "=f")
10288 (neg:TF (match_operand:TF 1 "register_operand" "0")))]
10289 "TARGET_80387 && reload_completed"
10291 [(set_attr "type" "fsgn")
10292 (set_attr "mode" "XF")
10293 (set_attr "ppro_uops" "few")])
10295 (define_insn "*negextenddftf2"
10296 [(set (match_operand:TF 0 "register_operand" "=f")
10297 (neg:TF (float_extend:TF
10298 (match_operand:DF 1 "register_operand" "0"))))]
10301 [(set_attr "type" "fsgn")
10302 (set_attr "mode" "XF")
10303 (set_attr "ppro_uops" "few")])
10305 (define_insn "*negextendsftf2"
10306 [(set (match_operand:TF 0 "register_operand" "=f")
10307 (neg:TF (float_extend:TF
10308 (match_operand:SF 1 "register_operand" "0"))))]
10311 [(set_attr "type" "fsgn")
10312 (set_attr "mode" "XF")
10313 (set_attr "ppro_uops" "few")])
10315 ;; Absolute value instructions
10317 (define_expand "abssf2"
10318 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
10319 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
10320 (clobber (reg:CC 17))])]
10324 /* In case operand is in memory, we will not use SSE. */
10325 if (memory_operand (operands[0], VOIDmode)
10326 && rtx_equal_p (operands[0], operands[1]))
10327 emit_insn (gen_abssf2_memory (operands[0], operands[1]));
10330 /* Using SSE is tricky, since we need bitwise negation of -0
10332 rtx reg = gen_reg_rtx (V4SFmode);
10333 rtx dest = operands[0];
10336 operands[1] = force_reg (SFmode, operands[1]);
10337 operands[0] = force_reg (SFmode, operands[0]);
10338 imm = gen_lowpart (SFmode, gen_int_mode(~0x80000000, SImode));
10339 reg = force_reg (V4SFmode,
10340 gen_rtx_CONST_VECTOR (V4SFmode,
10341 gen_rtvec (4, imm, CONST0_RTX (SFmode),
10342 CONST0_RTX (SFmode),
10343 CONST0_RTX (SFmode))));
10344 emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
10345 if (dest != operands[0])
10346 emit_move_insn (dest, operands[0]);
10350 ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
10352 (define_insn "abssf2_memory"
10353 [(set (match_operand:SF 0 "memory_operand" "=m")
10354 (abs:SF (match_operand:SF 1 "memory_operand" "0")))
10355 (clobber (reg:CC 17))]
10356 "ix86_unary_operator_ok (ABS, SFmode, operands)"
10359 (define_insn "abssf2_ifs"
10360 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
10361 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
10362 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
10363 (clobber (reg:CC 17))]
10365 && (reload_in_progress || reload_completed
10366 || (register_operand (operands[0], VOIDmode)
10367 && register_operand (operands[1], VOIDmode)))"
10371 [(set (match_operand:SF 0 "memory_operand" "")
10372 (abs:SF (match_operand:SF 1 "memory_operand" "")))
10373 (use (match_operand:V4SF 2 "" ""))
10374 (clobber (reg:CC 17))]
10376 [(parallel [(set (match_dup 0)
10377 (abs:SF (match_dup 1)))
10378 (clobber (reg:CC 17))])])
10381 [(set (match_operand:SF 0 "register_operand" "")
10382 (abs:SF (match_operand:SF 1 "register_operand" "")))
10383 (use (match_operand:V4SF 2 "" ""))
10384 (clobber (reg:CC 17))]
10385 "reload_completed && !SSE_REG_P (operands[0])"
10386 [(parallel [(set (match_dup 0)
10387 (abs:SF (match_dup 1)))
10388 (clobber (reg:CC 17))])])
10391 [(set (match_operand:SF 0 "register_operand" "")
10392 (abs:SF (match_operand:SF 1 "register_operand" "")))
10393 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
10394 (clobber (reg:CC 17))]
10395 "reload_completed && SSE_REG_P (operands[0])"
10396 [(set (subreg:TI (match_dup 0) 0)
10397 (and:TI (match_dup 1)
10400 operands[1] = simplify_gen_subreg (TImode, operands[1], SFmode, 0);
10401 operands[2] = simplify_gen_subreg (TImode, operands[2], V4SFmode, 0);
10402 if (operands_match_p (operands[0], operands[2]))
10406 operands[1] = operands[2];
10411 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10412 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10414 (define_insn "*abssf2_if"
10415 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
10416 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
10417 (clobber (reg:CC 17))]
10418 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
10422 [(set (match_operand:SF 0 "fp_register_operand" "")
10423 (abs:SF (match_operand:SF 1 "register_operand" "")))
10424 (clobber (reg:CC 17))]
10425 "TARGET_80387 && reload_completed"
10426 [(set (match_dup 0)
10427 (abs:SF (match_dup 1)))]
10431 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
10432 (abs:SF (match_operand:SF 1 "register_operand" "")))
10433 (clobber (reg:CC 17))]
10434 "TARGET_80387 && reload_completed"
10435 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10436 (clobber (reg:CC 17))])]
10437 "operands[1] = gen_int_mode (~0x80000000, SImode);
10438 operands[0] = gen_lowpart (SImode, operands[0]);")
10441 [(set (match_operand 0 "memory_operand" "")
10442 (abs (match_operand 1 "memory_operand" "")))
10443 (clobber (reg:CC 17))]
10444 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
10445 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
10446 (clobber (reg:CC 17))])]
10448 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
10450 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
10453 operands[0] = adjust_address (operands[0], QImode, size - 1);
10454 operands[1] = gen_int_mode (~0x80, QImode);
10457 (define_expand "absdf2"
10458 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
10459 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
10460 (clobber (reg:CC 17))])]
10464 /* In case operand is in memory, we will not use SSE. */
10465 if (memory_operand (operands[0], VOIDmode)
10466 && rtx_equal_p (operands[0], operands[1]))
10467 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
10470 /* Using SSE is tricky, since we need bitwise negation of -0
10472 rtx reg = gen_reg_rtx (V2DFmode);
10473 #if HOST_BITS_PER_WIDE_INT >= 64
10474 rtx imm = gen_int_mode (~(((HOST_WIDE_INT)1) << 63), DImode);
10476 rtx imm = immed_double_const (~0, ~0x80000000, DImode);
10478 rtx dest = operands[0];
10480 operands[1] = force_reg (DFmode, operands[1]);
10481 operands[0] = force_reg (DFmode, operands[0]);
10483 /* Produce LONG_DOUBLE with the proper immediate argument. */
10484 imm = gen_lowpart (DFmode, imm);
10485 reg = force_reg (V2DFmode,
10486 gen_rtx_CONST_VECTOR (V2DFmode,
10487 gen_rtvec (2, imm, CONST0_RTX (DFmode))));
10488 emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg));
10489 if (dest != operands[0])
10490 emit_move_insn (dest, operands[0]);
10494 ix86_expand_unary_operator (ABS, DFmode, operands); DONE;")
10496 (define_insn "absdf2_memory"
10497 [(set (match_operand:DF 0 "memory_operand" "=m")
10498 (abs:DF (match_operand:DF 1 "memory_operand" "0")))
10499 (clobber (reg:CC 17))]
10500 "ix86_unary_operator_ok (ABS, DFmode, operands)"
10503 (define_insn "absdf2_ifs"
10504 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr,mr#Yf")
10505 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
10506 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
10507 (clobber (reg:CC 17))]
10508 "!TARGET_64BIT && TARGET_SSE2
10509 && (reload_in_progress || reload_completed
10510 || (register_operand (operands[0], VOIDmode)
10511 && register_operand (operands[1], VOIDmode)))"
10514 (define_insn "*absdf2_ifs_rex64"
10515 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr")
10516 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
10517 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
10518 (clobber (reg:CC 17))]
10519 "TARGET_64BIT && TARGET_SSE2
10520 && (reload_in_progress || reload_completed
10521 || (register_operand (operands[0], VOIDmode)
10522 && register_operand (operands[1], VOIDmode)))"
10526 [(set (match_operand:DF 0 "memory_operand" "")
10527 (abs:DF (match_operand:DF 1 "memory_operand" "")))
10528 (use (match_operand:V2DF 2 "" ""))
10529 (clobber (reg:CC 17))]
10531 [(parallel [(set (match_dup 0)
10532 (abs:DF (match_dup 1)))
10533 (clobber (reg:CC 17))])])
10536 [(set (match_operand:DF 0 "register_operand" "")
10537 (abs:DF (match_operand:DF 1 "register_operand" "")))
10538 (use (match_operand:V2DF 2 "" ""))
10539 (clobber (reg:CC 17))]
10540 "reload_completed && !SSE_REG_P (operands[0])"
10541 [(parallel [(set (match_dup 0)
10542 (abs:DF (match_dup 1)))
10543 (clobber (reg:CC 17))])])
10546 [(set (match_operand:DF 0 "register_operand" "")
10547 (abs:DF (match_operand:DF 1 "register_operand" "")))
10548 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
10549 (clobber (reg:CC 17))]
10550 "reload_completed && SSE_REG_P (operands[0])"
10551 [(set (subreg:TI (match_dup 0) 0)
10552 (and:TI (match_dup 1)
10555 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
10556 operands[1] = simplify_gen_subreg (TImode, operands[1], DFmode, 0);
10557 operands[2] = simplify_gen_subreg (TImode, operands[2], V2DFmode, 0);
10558 /* Avoid possible reformatting on the operands. */
10559 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
10560 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
10561 if (operands_match_p (operands[0], operands[2]))
10565 operands[1] = operands[2];
10571 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10572 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10574 (define_insn "*absdf2_if"
10575 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
10576 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10577 (clobber (reg:CC 17))]
10578 "!TARGET_64BIT && TARGET_80387
10579 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10582 ;; FIXME: We should to allow integer registers here. Problem is that
10583 ;; we need another scratch register to get constant from.
10584 ;; Forcing constant to mem if no register available in peep2 should be
10585 ;; safe even for PIC mode, because of RIP relative addressing.
10586 (define_insn "*absdf2_if_rex64"
10587 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
10588 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10589 (clobber (reg:CC 17))]
10590 "TARGET_64BIT && TARGET_80387
10591 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10595 [(set (match_operand:DF 0 "fp_register_operand" "")
10596 (abs:DF (match_operand:DF 1 "register_operand" "")))
10597 (clobber (reg:CC 17))]
10598 "TARGET_80387 && reload_completed"
10599 [(set (match_dup 0)
10600 (abs:DF (match_dup 1)))]
10604 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
10605 (abs:DF (match_operand:DF 1 "register_operand" "")))
10606 (clobber (reg:CC 17))]
10607 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10608 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
10609 (clobber (reg:CC 17))])]
10610 "operands[4] = gen_int_mode (~0x80000000, SImode);
10611 split_di (operands+0, 1, operands+2, operands+3);")
10613 (define_expand "absxf2"
10614 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
10615 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
10616 (clobber (reg:CC 17))])]
10617 "!TARGET_64BIT && TARGET_80387"
10618 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
10620 (define_expand "abstf2"
10621 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
10622 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
10623 (clobber (reg:CC 17))])]
10625 "ix86_expand_unary_operator (ABS, TFmode, operands); DONE;")
10627 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10628 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10630 (define_insn "*absxf2_if"
10631 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
10632 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
10633 (clobber (reg:CC 17))]
10634 "!TARGET_64BIT && TARGET_80387
10635 && ix86_unary_operator_ok (ABS, XFmode, operands)"
10639 [(set (match_operand:XF 0 "fp_register_operand" "")
10640 (abs:XF (match_operand:XF 1 "register_operand" "")))
10641 (clobber (reg:CC 17))]
10642 "TARGET_80387 && reload_completed"
10643 [(set (match_dup 0)
10644 (abs:XF (match_dup 1)))]
10648 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
10649 (abs:XF (match_operand:XF 1 "register_operand" "")))
10650 (clobber (reg:CC 17))]
10651 "TARGET_80387 && reload_completed"
10652 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10653 (clobber (reg:CC 17))])]
10654 "operands[1] = GEN_INT (~0x8000);
10655 operands[0] = gen_rtx_REG (SImode,
10656 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10658 (define_insn "*abstf2_if"
10659 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
10660 (abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
10661 (clobber (reg:CC 17))]
10662 "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)"
10666 [(set (match_operand:TF 0 "fp_register_operand" "")
10667 (abs:TF (match_operand:TF 1 "register_operand" "")))
10668 (clobber (reg:CC 17))]
10669 "TARGET_80387 && reload_completed"
10670 [(set (match_dup 0)
10671 (abs:TF (match_dup 1)))]
10675 [(set (match_operand:TF 0 "register_and_not_any_fp_reg_operand" "")
10676 (abs:TF (match_operand:TF 1 "register_operand" "")))
10677 (clobber (reg:CC 17))]
10678 "TARGET_80387 && reload_completed"
10679 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10680 (clobber (reg:CC 17))])]
10681 "operands[1] = GEN_INT (~0x8000);
10682 operands[0] = gen_rtx_REG (SImode,
10683 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10685 (define_insn "*abssf2_1"
10686 [(set (match_operand:SF 0 "register_operand" "=f")
10687 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
10688 "TARGET_80387 && reload_completed"
10690 [(set_attr "type" "fsgn")
10691 (set_attr "mode" "SF")])
10693 (define_insn "*absdf2_1"
10694 [(set (match_operand:DF 0 "register_operand" "=f")
10695 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
10696 "TARGET_80387 && reload_completed"
10698 [(set_attr "type" "fsgn")
10699 (set_attr "mode" "DF")])
10701 (define_insn "*absextendsfdf2"
10702 [(set (match_operand:DF 0 "register_operand" "=f")
10703 (abs:DF (float_extend:DF
10704 (match_operand:SF 1 "register_operand" "0"))))]
10707 [(set_attr "type" "fsgn")
10708 (set_attr "mode" "DF")])
10710 (define_insn "*absxf2_1"
10711 [(set (match_operand:XF 0 "register_operand" "=f")
10712 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
10713 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10715 [(set_attr "type" "fsgn")
10716 (set_attr "mode" "DF")])
10718 (define_insn "*absextenddfxf2"
10719 [(set (match_operand:XF 0 "register_operand" "=f")
10720 (abs:XF (float_extend:XF
10721 (match_operand:DF 1 "register_operand" "0"))))]
10722 "!TARGET_64BIT && TARGET_80387"
10724 [(set_attr "type" "fsgn")
10725 (set_attr "mode" "XF")])
10727 (define_insn "*absextendsfxf2"
10728 [(set (match_operand:XF 0 "register_operand" "=f")
10729 (abs:XF (float_extend:XF
10730 (match_operand:SF 1 "register_operand" "0"))))]
10731 "!TARGET_64BIT && TARGET_80387"
10733 [(set_attr "type" "fsgn")
10734 (set_attr "mode" "XF")])
10736 (define_insn "*abstf2_1"
10737 [(set (match_operand:TF 0 "register_operand" "=f")
10738 (abs:TF (match_operand:TF 1 "register_operand" "0")))]
10739 "TARGET_80387 && reload_completed"
10741 [(set_attr "type" "fsgn")
10742 (set_attr "mode" "DF")])
10744 (define_insn "*absextenddftf2"
10745 [(set (match_operand:TF 0 "register_operand" "=f")
10746 (abs:TF (float_extend:TF
10747 (match_operand:DF 1 "register_operand" "0"))))]
10750 [(set_attr "type" "fsgn")
10751 (set_attr "mode" "XF")])
10753 (define_insn "*absextendsftf2"
10754 [(set (match_operand:TF 0 "register_operand" "=f")
10755 (abs:TF (float_extend:TF
10756 (match_operand:SF 1 "register_operand" "0"))))]
10759 [(set_attr "type" "fsgn")
10760 (set_attr "mode" "XF")])
10762 ;; One complement instructions
10764 (define_expand "one_cmpldi2"
10765 [(set (match_operand:DI 0 "nonimmediate_operand" "")
10766 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
10768 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
10770 (define_insn "*one_cmpldi2_1_rex64"
10771 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10772 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
10773 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
10775 [(set_attr "type" "negnot")
10776 (set_attr "mode" "DI")])
10778 (define_insn "*one_cmpldi2_2_rex64"
10780 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
10782 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10783 (not:DI (match_dup 1)))]
10784 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10785 && ix86_unary_operator_ok (NOT, DImode, operands)"
10787 [(set_attr "type" "alu1")
10788 (set_attr "mode" "DI")])
10792 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" ""))
10794 (set (match_operand:DI 0 "nonimmediate_operand" "")
10795 (not:DI (match_dup 1)))]
10796 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
10797 [(parallel [(set (reg:CCNO 17)
10798 (compare:CCNO (xor:DI (match_dup 1) (const_int -1))
10801 (xor:DI (match_dup 1) (const_int -1)))])]
10804 (define_expand "one_cmplsi2"
10805 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10806 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
10808 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
10810 (define_insn "*one_cmplsi2_1"
10811 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10812 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
10813 "ix86_unary_operator_ok (NOT, SImode, operands)"
10815 [(set_attr "type" "negnot")
10816 (set_attr "mode" "SI")])
10818 ;; ??? Currently never generated - xor is used instead.
10819 (define_insn "*one_cmplsi2_1_zext"
10820 [(set (match_operand:DI 0 "register_operand" "=r")
10821 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
10822 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
10824 [(set_attr "type" "negnot")
10825 (set_attr "mode" "SI")])
10827 (define_insn "*one_cmplsi2_2"
10829 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
10831 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10832 (not:SI (match_dup 1)))]
10833 "ix86_match_ccmode (insn, CCNOmode)
10834 && ix86_unary_operator_ok (NOT, SImode, operands)"
10836 [(set_attr "type" "alu1")
10837 (set_attr "mode" "SI")])
10841 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
10843 (set (match_operand:SI 0 "nonimmediate_operand" "")
10844 (not:SI (match_dup 1)))]
10845 "ix86_match_ccmode (insn, CCNOmode)"
10846 [(parallel [(set (reg:CCNO 17)
10847 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10850 (xor:SI (match_dup 1) (const_int -1)))])]
10853 ;; ??? Currently never generated - xor is used instead.
10854 (define_insn "*one_cmplsi2_2_zext"
10856 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10858 (set (match_operand:DI 0 "register_operand" "=r")
10859 (zero_extend:DI (not:SI (match_dup 1))))]
10860 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10861 && ix86_unary_operator_ok (NOT, SImode, operands)"
10863 [(set_attr "type" "alu1")
10864 (set_attr "mode" "SI")])
10868 (compare (not:SI (match_operand:SI 1 "register_operand" ""))
10870 (set (match_operand:DI 0 "register_operand" "")
10871 (zero_extend:DI (not:SI (match_dup 1))))]
10872 "ix86_match_ccmode (insn, CCNOmode)"
10873 [(parallel [(set (reg:CCNO 17)
10874 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10877 (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])]
10880 (define_expand "one_cmplhi2"
10881 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10882 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10883 "TARGET_HIMODE_MATH"
10884 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10886 (define_insn "*one_cmplhi2_1"
10887 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10888 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
10889 "ix86_unary_operator_ok (NOT, HImode, operands)"
10891 [(set_attr "type" "negnot")
10892 (set_attr "mode" "HI")])
10894 (define_insn "*one_cmplhi2_2"
10896 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10898 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10899 (not:HI (match_dup 1)))]
10900 "ix86_match_ccmode (insn, CCNOmode)
10901 && ix86_unary_operator_ok (NEG, HImode, operands)"
10903 [(set_attr "type" "alu1")
10904 (set_attr "mode" "HI")])
10908 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
10910 (set (match_operand:HI 0 "nonimmediate_operand" "")
10911 (not:HI (match_dup 1)))]
10912 "ix86_match_ccmode (insn, CCNOmode)"
10913 [(parallel [(set (reg:CCNO 17)
10914 (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
10917 (xor:HI (match_dup 1) (const_int -1)))])]
10920 ;; %%% Potential partial reg stall on alternative 1. What to do?
10921 (define_expand "one_cmplqi2"
10922 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10923 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10924 "TARGET_QIMODE_MATH"
10925 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
10927 (define_insn "*one_cmplqi2_1"
10928 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10929 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
10930 "ix86_unary_operator_ok (NOT, QImode, operands)"
10934 [(set_attr "type" "negnot")
10935 (set_attr "mode" "QI,SI")])
10937 (define_insn "*one_cmplqi2_2"
10939 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10941 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10942 (not:QI (match_dup 1)))]
10943 "ix86_match_ccmode (insn, CCNOmode)
10944 && ix86_unary_operator_ok (NOT, QImode, operands)"
10946 [(set_attr "type" "alu1")
10947 (set_attr "mode" "QI")])
10951 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
10953 (set (match_operand:QI 0 "nonimmediate_operand" "")
10954 (not:QI (match_dup 1)))]
10955 "ix86_match_ccmode (insn, CCNOmode)"
10956 [(parallel [(set (reg:CCNO 17)
10957 (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
10960 (xor:QI (match_dup 1) (const_int -1)))])]
10963 ;; Arithmetic shift instructions
10965 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10966 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10967 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10968 ;; from the assembler input.
10970 ;; This instruction shifts the target reg/mem as usual, but instead of
10971 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10972 ;; is a left shift double, bits are taken from the high order bits of
10973 ;; reg, else if the insn is a shift right double, bits are taken from the
10974 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10975 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10977 ;; Since sh[lr]d does not change the `reg' operand, that is done
10978 ;; separately, making all shifts emit pairs of shift double and normal
10979 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10980 ;; support a 63 bit shift, each shift where the count is in a reg expands
10981 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10983 ;; If the shift count is a constant, we need never emit more than one
10984 ;; shift pair, instead using moves and sign extension for counts greater
10987 (define_expand "ashldi3"
10988 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
10989 (ashift:DI (match_operand:DI 1 "shiftdi_operand" "")
10990 (match_operand:QI 2 "nonmemory_operand" "")))
10991 (clobber (reg:CC 17))])]
10994 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
10996 emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
10999 ix86_expand_binary_operator (ASHIFT, DImode, operands);
11003 (define_insn "*ashldi3_1_rex64"
11004 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
11005 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r")
11006 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
11007 (clobber (reg:CC 17))]
11008 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
11010 switch (get_attr_type (insn))
11013 if (operands[2] != const1_rtx)
11015 if (!rtx_equal_p (operands[0], operands[1]))
11017 return "add{q}\t{%0, %0|%0, %0}";
11020 if (GET_CODE (operands[2]) != CONST_INT
11021 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
11023 operands[1] = gen_rtx_MULT (DImode, operands[1],
11024 GEN_INT (1 << INTVAL (operands[2])));
11025 return "lea{q}\t{%a1, %0|%0, %a1}";
11028 if (REG_P (operands[2]))
11029 return "sal{q}\t{%b2, %0|%0, %b2}";
11030 else if (GET_CODE (operands[2]) == CONST_INT
11031 && INTVAL (operands[2]) == 1
11032 && (TARGET_SHIFT1 || optimize_size))
11033 return "sal{q}\t%0";
11035 return "sal{q}\t{%2, %0|%0, %2}";
11038 [(set (attr "type")
11039 (cond [(eq_attr "alternative" "1")
11040 (const_string "lea")
11041 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11043 (match_operand 0 "register_operand" ""))
11044 (match_operand 2 "const1_operand" ""))
11045 (const_string "alu")
11047 (const_string "ishift")))
11048 (set_attr "mode" "DI")])
11050 ;; Convert lea to the lea pattern to avoid flags dependency.
11052 [(set (match_operand:DI 0 "register_operand" "")
11053 (ashift:DI (match_operand:DI 1 "register_operand" "")
11054 (match_operand:QI 2 "immediate_operand" "")))
11055 (clobber (reg:CC 17))]
11056 "TARGET_64BIT && reload_completed
11057 && true_regnum (operands[0]) != true_regnum (operands[1])"
11058 [(set (match_dup 0)
11059 (mult:DI (match_dup 1)
11061 "operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);")
11063 ;; This pattern can't accept a variable shift count, since shifts by
11064 ;; zero don't affect the flags. We assume that shifts by constant
11065 ;; zero are optimized away.
11066 (define_insn "*ashldi3_cmp_rex64"
11069 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11070 (match_operand:QI 2 "immediate_operand" "e"))
11072 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11073 (ashift:DI (match_dup 1) (match_dup 2)))]
11074 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11075 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
11077 switch (get_attr_type (insn))
11080 if (operands[2] != const1_rtx)
11082 return "add{q}\t{%0, %0|%0, %0}";
11085 if (REG_P (operands[2]))
11086 return "sal{q}\t{%b2, %0|%0, %b2}";
11087 else if (GET_CODE (operands[2]) == CONST_INT
11088 && INTVAL (operands[2]) == 1
11089 && (TARGET_SHIFT1 || optimize_size))
11090 return "sal{q}\t%0";
11092 return "sal{q}\t{%2, %0|%0, %2}";
11095 [(set (attr "type")
11096 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11098 (match_operand 0 "register_operand" ""))
11099 (match_operand 2 "const1_operand" ""))
11100 (const_string "alu")
11102 (const_string "ishift")))
11103 (set_attr "mode" "DI")])
11105 (define_insn "ashldi3_1"
11106 [(set (match_operand:DI 0 "register_operand" "=r")
11107 (ashift:DI (match_operand:DI 1 "register_operand" "0")
11108 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11109 (clobber (match_scratch:SI 3 "=&r"))
11110 (clobber (reg:CC 17))]
11111 "!TARGET_64BIT && TARGET_CMOVE"
11113 [(set_attr "type" "multi")])
11115 (define_insn "*ashldi3_2"
11116 [(set (match_operand:DI 0 "register_operand" "=r")
11117 (ashift:DI (match_operand:DI 1 "register_operand" "0")
11118 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11119 (clobber (reg:CC 17))]
11122 [(set_attr "type" "multi")])
11125 [(set (match_operand:DI 0 "register_operand" "")
11126 (ashift:DI (match_operand:DI 1 "register_operand" "")
11127 (match_operand:QI 2 "nonmemory_operand" "")))
11128 (clobber (match_scratch:SI 3 ""))
11129 (clobber (reg:CC 17))]
11130 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11132 "ix86_split_ashldi (operands, operands[3]); DONE;")
11135 [(set (match_operand:DI 0 "register_operand" "")
11136 (ashift:DI (match_operand:DI 1 "register_operand" "")
11137 (match_operand:QI 2 "nonmemory_operand" "")))
11138 (clobber (reg:CC 17))]
11139 "!TARGET_64BIT && reload_completed"
11141 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
11143 (define_insn "x86_shld_1"
11144 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11145 (ior:SI (ashift:SI (match_dup 0)
11146 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11147 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
11148 (minus:QI (const_int 32) (match_dup 2)))))
11149 (clobber (reg:CC 17))]
11152 shld{l}\t{%2, %1, %0|%0, %1, %2}
11153 shld{l}\t{%s2%1, %0|%0, %1, %2}"
11154 [(set_attr "type" "ishift")
11155 (set_attr "prefix_0f" "1")
11156 (set_attr "mode" "SI")
11157 (set_attr "pent_pair" "np")
11158 (set_attr "athlon_decode" "vector")
11159 (set_attr "ppro_uops" "few")])
11161 (define_expand "x86_shift_adj_1"
11163 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
11166 (set (match_operand:SI 0 "register_operand" "")
11167 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
11168 (match_operand:SI 1 "register_operand" "")
11171 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
11172 (match_operand:SI 3 "register_operand" "r")
11177 (define_expand "x86_shift_adj_2"
11178 [(use (match_operand:SI 0 "register_operand" ""))
11179 (use (match_operand:SI 1 "register_operand" ""))
11180 (use (match_operand:QI 2 "register_operand" ""))]
11183 rtx label = gen_label_rtx ();
11186 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11188 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11189 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11190 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11191 gen_rtx_LABEL_REF (VOIDmode, label),
11193 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11194 JUMP_LABEL (tmp) = label;
11196 emit_move_insn (operands[0], operands[1]);
11197 emit_move_insn (operands[1], const0_rtx);
11199 emit_label (label);
11200 LABEL_NUSES (label) = 1;
11205 (define_expand "ashlsi3"
11206 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11207 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
11208 (match_operand:QI 2 "nonmemory_operand" "")))
11209 (clobber (reg:CC 17))]
11211 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
11213 (define_insn "*ashlsi3_1"
11214 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
11215 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
11216 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
11217 (clobber (reg:CC 17))]
11218 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11220 switch (get_attr_type (insn))
11223 if (operands[2] != const1_rtx)
11225 if (!rtx_equal_p (operands[0], operands[1]))
11227 return "add{l}\t{%0, %0|%0, %0}";
11233 if (REG_P (operands[2]))
11234 return "sal{l}\t{%b2, %0|%0, %b2}";
11235 else if (GET_CODE (operands[2]) == CONST_INT
11236 && INTVAL (operands[2]) == 1
11237 && (TARGET_SHIFT1 || optimize_size))
11238 return "sal{l}\t%0";
11240 return "sal{l}\t{%2, %0|%0, %2}";
11243 [(set (attr "type")
11244 (cond [(eq_attr "alternative" "1")
11245 (const_string "lea")
11246 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11248 (match_operand 0 "register_operand" ""))
11249 (match_operand 2 "const1_operand" ""))
11250 (const_string "alu")
11252 (const_string "ishift")))
11253 (set_attr "mode" "SI")])
11255 ;; Convert lea to the lea pattern to avoid flags dependency.
11257 [(set (match_operand 0 "register_operand" "")
11258 (ashift (match_operand 1 "index_register_operand" "")
11259 (match_operand:QI 2 "const_int_operand" "")))
11260 (clobber (reg:CC 17))]
11262 && true_regnum (operands[0]) != true_regnum (operands[1])"
11266 operands[0] = gen_lowpart (SImode, operands[0]);
11267 operands[1] = gen_lowpart (Pmode, operands[1]);
11268 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
11269 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
11270 if (Pmode != SImode)
11271 pat = gen_rtx_SUBREG (SImode, pat, 0);
11272 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
11276 ;; Rare case of shifting RSP is handled by generating move and shift
11278 [(set (match_operand 0 "register_operand" "")
11279 (ashift (match_operand 1 "register_operand" "")
11280 (match_operand:QI 2 "const_int_operand" "")))
11281 (clobber (reg:CC 17))]
11283 && true_regnum (operands[0]) != true_regnum (operands[1])"
11287 emit_move_insn (operands[1], operands[0]);
11288 pat = gen_rtx_SET (VOIDmode, operands[0],
11289 gen_rtx_ASHIFT (GET_MODE (operands[0]),
11290 operands[0], operands[2]));
11291 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
11292 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob)));
11296 (define_insn "*ashlsi3_1_zext"
11297 [(set (match_operand:DI 0 "register_operand" "=r,r")
11298 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
11299 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
11300 (clobber (reg:CC 17))]
11301 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11303 switch (get_attr_type (insn))
11306 if (operands[2] != const1_rtx)
11308 return "add{l}\t{%k0, %k0|%k0, %k0}";
11314 if (REG_P (operands[2]))
11315 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11316 else if (GET_CODE (operands[2]) == CONST_INT
11317 && INTVAL (operands[2]) == 1
11318 && (TARGET_SHIFT1 || optimize_size))
11319 return "sal{l}\t%k0";
11321 return "sal{l}\t{%2, %k0|%k0, %2}";
11324 [(set (attr "type")
11325 (cond [(eq_attr "alternative" "1")
11326 (const_string "lea")
11327 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11329 (match_operand 2 "const1_operand" ""))
11330 (const_string "alu")
11332 (const_string "ishift")))
11333 (set_attr "mode" "SI")])
11335 ;; Convert lea to the lea pattern to avoid flags dependency.
11337 [(set (match_operand:DI 0 "register_operand" "")
11338 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
11339 (match_operand:QI 2 "const_int_operand" ""))))
11340 (clobber (reg:CC 17))]
11341 "TARGET_64BIT && reload_completed
11342 && true_regnum (operands[0]) != true_regnum (operands[1])"
11343 [(set (match_dup 0) (zero_extend:DI
11344 (subreg:SI (mult:SI (match_dup 1)
11345 (match_dup 2)) 0)))]
11347 operands[1] = gen_lowpart (Pmode, operands[1]);
11348 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
11351 ;; This pattern can't accept a variable shift count, since shifts by
11352 ;; zero don't affect the flags. We assume that shifts by constant
11353 ;; zero are optimized away.
11354 (define_insn "*ashlsi3_cmp"
11357 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11358 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11360 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11361 (ashift:SI (match_dup 1) (match_dup 2)))]
11362 "ix86_match_ccmode (insn, CCGOCmode)
11363 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11365 switch (get_attr_type (insn))
11368 if (operands[2] != const1_rtx)
11370 return "add{l}\t{%0, %0|%0, %0}";
11373 if (REG_P (operands[2]))
11374 return "sal{l}\t{%b2, %0|%0, %b2}";
11375 else if (GET_CODE (operands[2]) == CONST_INT
11376 && INTVAL (operands[2]) == 1
11377 && (TARGET_SHIFT1 || optimize_size))
11378 return "sal{l}\t%0";
11380 return "sal{l}\t{%2, %0|%0, %2}";
11383 [(set (attr "type")
11384 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11386 (match_operand 0 "register_operand" ""))
11387 (match_operand 2 "const1_operand" ""))
11388 (const_string "alu")
11390 (const_string "ishift")))
11391 (set_attr "mode" "SI")])
11393 (define_insn "*ashlsi3_cmp_zext"
11396 (ashift:SI (match_operand:SI 1 "register_operand" "0")
11397 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11399 (set (match_operand:DI 0 "register_operand" "=r")
11400 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
11401 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11402 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11404 switch (get_attr_type (insn))
11407 if (operands[2] != const1_rtx)
11409 return "add{l}\t{%k0, %k0|%k0, %k0}";
11412 if (REG_P (operands[2]))
11413 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11414 else if (GET_CODE (operands[2]) == CONST_INT
11415 && INTVAL (operands[2]) == 1
11416 && (TARGET_SHIFT1 || optimize_size))
11417 return "sal{l}\t%k0";
11419 return "sal{l}\t{%2, %k0|%k0, %2}";
11422 [(set (attr "type")
11423 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11425 (match_operand 2 "const1_operand" ""))
11426 (const_string "alu")
11428 (const_string "ishift")))
11429 (set_attr "mode" "SI")])
11431 (define_expand "ashlhi3"
11432 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11433 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
11434 (match_operand:QI 2 "nonmemory_operand" "")))
11435 (clobber (reg:CC 17))]
11436 "TARGET_HIMODE_MATH"
11437 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
11439 (define_insn "*ashlhi3_1_lea"
11440 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
11441 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
11442 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
11443 (clobber (reg:CC 17))]
11444 "!TARGET_PARTIAL_REG_STALL
11445 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11447 switch (get_attr_type (insn))
11452 if (operands[2] != const1_rtx)
11454 return "add{w}\t{%0, %0|%0, %0}";
11457 if (REG_P (operands[2]))
11458 return "sal{w}\t{%b2, %0|%0, %b2}";
11459 else if (GET_CODE (operands[2]) == CONST_INT
11460 && INTVAL (operands[2]) == 1
11461 && (TARGET_SHIFT1 || optimize_size))
11462 return "sal{w}\t%0";
11464 return "sal{w}\t{%2, %0|%0, %2}";
11467 [(set (attr "type")
11468 (cond [(eq_attr "alternative" "1")
11469 (const_string "lea")
11470 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11472 (match_operand 0 "register_operand" ""))
11473 (match_operand 2 "const1_operand" ""))
11474 (const_string "alu")
11476 (const_string "ishift")))
11477 (set_attr "mode" "HI,SI")])
11479 (define_insn "*ashlhi3_1"
11480 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11481 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11482 (match_operand:QI 2 "nonmemory_operand" "cI")))
11483 (clobber (reg:CC 17))]
11484 "TARGET_PARTIAL_REG_STALL
11485 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11487 switch (get_attr_type (insn))
11490 if (operands[2] != const1_rtx)
11492 return "add{w}\t{%0, %0|%0, %0}";
11495 if (REG_P (operands[2]))
11496 return "sal{w}\t{%b2, %0|%0, %b2}";
11497 else if (GET_CODE (operands[2]) == CONST_INT
11498 && INTVAL (operands[2]) == 1
11499 && (TARGET_SHIFT1 || optimize_size))
11500 return "sal{w}\t%0";
11502 return "sal{w}\t{%2, %0|%0, %2}";
11505 [(set (attr "type")
11506 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11508 (match_operand 0 "register_operand" ""))
11509 (match_operand 2 "const1_operand" ""))
11510 (const_string "alu")
11512 (const_string "ishift")))
11513 (set_attr "mode" "HI")])
11515 ;; This pattern can't accept a variable shift count, since shifts by
11516 ;; zero don't affect the flags. We assume that shifts by constant
11517 ;; zero are optimized away.
11518 (define_insn "*ashlhi3_cmp"
11521 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11522 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11524 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11525 (ashift:HI (match_dup 1) (match_dup 2)))]
11526 "ix86_match_ccmode (insn, CCGOCmode)
11527 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11529 switch (get_attr_type (insn))
11532 if (operands[2] != const1_rtx)
11534 return "add{w}\t{%0, %0|%0, %0}";
11537 if (REG_P (operands[2]))
11538 return "sal{w}\t{%b2, %0|%0, %b2}";
11539 else if (GET_CODE (operands[2]) == CONST_INT
11540 && INTVAL (operands[2]) == 1
11541 && (TARGET_SHIFT1 || optimize_size))
11542 return "sal{w}\t%0";
11544 return "sal{w}\t{%2, %0|%0, %2}";
11547 [(set (attr "type")
11548 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11550 (match_operand 0 "register_operand" ""))
11551 (match_operand 2 "const1_operand" ""))
11552 (const_string "alu")
11554 (const_string "ishift")))
11555 (set_attr "mode" "HI")])
11557 (define_expand "ashlqi3"
11558 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11559 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
11560 (match_operand:QI 2 "nonmemory_operand" "")))
11561 (clobber (reg:CC 17))]
11562 "TARGET_QIMODE_MATH"
11563 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
11565 ;; %%% Potential partial reg stall on alternative 2. What to do?
11567 (define_insn "*ashlqi3_1_lea"
11568 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
11569 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
11570 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
11571 (clobber (reg:CC 17))]
11572 "!TARGET_PARTIAL_REG_STALL
11573 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11575 switch (get_attr_type (insn))
11580 if (operands[2] != const1_rtx)
11582 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11583 return "add{l}\t{%k0, %k0|%k0, %k0}";
11585 return "add{b}\t{%0, %0|%0, %0}";
11588 if (REG_P (operands[2]))
11590 if (get_attr_mode (insn) == MODE_SI)
11591 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11593 return "sal{b}\t{%b2, %0|%0, %b2}";
11595 else if (GET_CODE (operands[2]) == CONST_INT
11596 && INTVAL (operands[2]) == 1
11597 && (TARGET_SHIFT1 || optimize_size))
11599 if (get_attr_mode (insn) == MODE_SI)
11600 return "sal{l}\t%0";
11602 return "sal{b}\t%0";
11606 if (get_attr_mode (insn) == MODE_SI)
11607 return "sal{l}\t{%2, %k0|%k0, %2}";
11609 return "sal{b}\t{%2, %0|%0, %2}";
11613 [(set (attr "type")
11614 (cond [(eq_attr "alternative" "2")
11615 (const_string "lea")
11616 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11618 (match_operand 0 "register_operand" ""))
11619 (match_operand 2 "const1_operand" ""))
11620 (const_string "alu")
11622 (const_string "ishift")))
11623 (set_attr "mode" "QI,SI,SI")])
11625 (define_insn "*ashlqi3_1"
11626 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
11627 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11628 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
11629 (clobber (reg:CC 17))]
11630 "TARGET_PARTIAL_REG_STALL
11631 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11633 switch (get_attr_type (insn))
11636 if (operands[2] != const1_rtx)
11638 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11639 return "add{l}\t{%k0, %k0|%k0, %k0}";
11641 return "add{b}\t{%0, %0|%0, %0}";
11644 if (REG_P (operands[2]))
11646 if (get_attr_mode (insn) == MODE_SI)
11647 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11649 return "sal{b}\t{%b2, %0|%0, %b2}";
11651 else if (GET_CODE (operands[2]) == CONST_INT
11652 && INTVAL (operands[2]) == 1
11653 && (TARGET_SHIFT1 || optimize_size))
11655 if (get_attr_mode (insn) == MODE_SI)
11656 return "sal{l}\t%0";
11658 return "sal{b}\t%0";
11662 if (get_attr_mode (insn) == MODE_SI)
11663 return "sal{l}\t{%2, %k0|%k0, %2}";
11665 return "sal{b}\t{%2, %0|%0, %2}";
11669 [(set (attr "type")
11670 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11672 (match_operand 0 "register_operand" ""))
11673 (match_operand 2 "const1_operand" ""))
11674 (const_string "alu")
11676 (const_string "ishift")))
11677 (set_attr "mode" "QI,SI")])
11679 ;; This pattern can't accept a variable shift count, since shifts by
11680 ;; zero don't affect the flags. We assume that shifts by constant
11681 ;; zero are optimized away.
11682 (define_insn "*ashlqi3_cmp"
11685 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11686 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11688 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11689 (ashift:QI (match_dup 1) (match_dup 2)))]
11690 "ix86_match_ccmode (insn, CCGOCmode)
11691 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11693 switch (get_attr_type (insn))
11696 if (operands[2] != const1_rtx)
11698 return "add{b}\t{%0, %0|%0, %0}";
11701 if (REG_P (operands[2]))
11702 return "sal{b}\t{%b2, %0|%0, %b2}";
11703 else if (GET_CODE (operands[2]) == CONST_INT
11704 && INTVAL (operands[2]) == 1
11705 && (TARGET_SHIFT1 || optimize_size))
11706 return "sal{b}\t%0";
11708 return "sal{b}\t{%2, %0|%0, %2}";
11711 [(set (attr "type")
11712 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11714 (match_operand 0 "register_operand" ""))
11715 (match_operand 2 "const1_operand" ""))
11716 (const_string "alu")
11718 (const_string "ishift")))
11719 (set_attr "mode" "QI")])
11721 ;; See comment above `ashldi3' about how this works.
11723 (define_expand "ashrdi3"
11724 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11725 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11726 (match_operand:QI 2 "nonmemory_operand" "")))
11727 (clobber (reg:CC 17))])]
11730 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11732 emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2]));
11735 ix86_expand_binary_operator (ASHIFTRT, DImode, operands);
11739 (define_insn "ashrdi3_63_rex64"
11740 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
11741 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
11742 (match_operand:DI 2 "const_int_operand" "i,i")))
11743 (clobber (reg:CC 17))]
11744 "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size)
11745 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11748 sar{q}\t{%2, %0|%0, %2}"
11749 [(set_attr "type" "imovx,ishift")
11750 (set_attr "prefix_0f" "0,*")
11751 (set_attr "length_immediate" "0,*")
11752 (set_attr "modrm" "0,1")
11753 (set_attr "mode" "DI")])
11755 (define_insn "*ashrdi3_1_one_bit_rex64"
11756 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11757 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11758 (match_operand:QI 2 "const_int_1_operand" "")))
11759 (clobber (reg:CC 17))]
11760 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
11761 && (TARGET_SHIFT1 || optimize_size)"
11763 [(set_attr "type" "ishift")
11764 (set (attr "length")
11765 (if_then_else (match_operand:DI 0 "register_operand" "")
11767 (const_string "*")))])
11769 (define_insn "*ashrdi3_1_rex64"
11770 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11771 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11772 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11773 (clobber (reg:CC 17))]
11774 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11776 sar{q}\t{%2, %0|%0, %2}
11777 sar{q}\t{%b2, %0|%0, %b2}"
11778 [(set_attr "type" "ishift")
11779 (set_attr "mode" "DI")])
11781 ;; This pattern can't accept a variable shift count, since shifts by
11782 ;; zero don't affect the flags. We assume that shifts by constant
11783 ;; zero are optimized away.
11784 (define_insn "*ashrdi3_one_bit_cmp_rex64"
11787 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11788 (match_operand:QI 2 "const_int_1_operand" ""))
11790 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11791 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11792 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11793 && (TARGET_SHIFT1 || optimize_size)
11794 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11796 [(set_attr "type" "ishift")
11797 (set (attr "length")
11798 (if_then_else (match_operand:DI 0 "register_operand" "")
11800 (const_string "*")))])
11802 ;; This pattern can't accept a variable shift count, since shifts by
11803 ;; zero don't affect the flags. We assume that shifts by constant
11804 ;; zero are optimized away.
11805 (define_insn "*ashrdi3_cmp_rex64"
11808 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11809 (match_operand:QI 2 "const_int_operand" "n"))
11811 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11812 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11813 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11814 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11815 "sar{q}\t{%2, %0|%0, %2}"
11816 [(set_attr "type" "ishift")
11817 (set_attr "mode" "DI")])
11820 (define_insn "ashrdi3_1"
11821 [(set (match_operand:DI 0 "register_operand" "=r")
11822 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11823 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11824 (clobber (match_scratch:SI 3 "=&r"))
11825 (clobber (reg:CC 17))]
11826 "!TARGET_64BIT && TARGET_CMOVE"
11828 [(set_attr "type" "multi")])
11830 (define_insn "*ashrdi3_2"
11831 [(set (match_operand:DI 0 "register_operand" "=r")
11832 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11833 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11834 (clobber (reg:CC 17))]
11837 [(set_attr "type" "multi")])
11840 [(set (match_operand:DI 0 "register_operand" "")
11841 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11842 (match_operand:QI 2 "nonmemory_operand" "")))
11843 (clobber (match_scratch:SI 3 ""))
11844 (clobber (reg:CC 17))]
11845 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11847 "ix86_split_ashrdi (operands, operands[3]); DONE;")
11850 [(set (match_operand:DI 0 "register_operand" "")
11851 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11852 (match_operand:QI 2 "nonmemory_operand" "")))
11853 (clobber (reg:CC 17))]
11854 "!TARGET_64BIT && reload_completed"
11856 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
11858 (define_insn "x86_shrd_1"
11859 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11860 (ior:SI (ashiftrt:SI (match_dup 0)
11861 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11862 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
11863 (minus:QI (const_int 32) (match_dup 2)))))
11864 (clobber (reg:CC 17))]
11867 shrd{l}\t{%2, %1, %0|%0, %1, %2}
11868 shrd{l}\t{%s2%1, %0|%0, %1, %2}"
11869 [(set_attr "type" "ishift")
11870 (set_attr "prefix_0f" "1")
11871 (set_attr "pent_pair" "np")
11872 (set_attr "ppro_uops" "few")
11873 (set_attr "mode" "SI")])
11875 (define_expand "x86_shift_adj_3"
11876 [(use (match_operand:SI 0 "register_operand" ""))
11877 (use (match_operand:SI 1 "register_operand" ""))
11878 (use (match_operand:QI 2 "register_operand" ""))]
11881 rtx label = gen_label_rtx ();
11884 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11886 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11887 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11888 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11889 gen_rtx_LABEL_REF (VOIDmode, label),
11891 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11892 JUMP_LABEL (tmp) = label;
11894 emit_move_insn (operands[0], operands[1]);
11895 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
11897 emit_label (label);
11898 LABEL_NUSES (label) = 1;
11903 (define_insn "ashrsi3_31"
11904 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
11905 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
11906 (match_operand:SI 2 "const_int_operand" "i,i")))
11907 (clobber (reg:CC 17))]
11908 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11909 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11912 sar{l}\t{%2, %0|%0, %2}"
11913 [(set_attr "type" "imovx,ishift")
11914 (set_attr "prefix_0f" "0,*")
11915 (set_attr "length_immediate" "0,*")
11916 (set_attr "modrm" "0,1")
11917 (set_attr "mode" "SI")])
11919 (define_insn "*ashrsi3_31_zext"
11920 [(set (match_operand:DI 0 "register_operand" "=*d,r")
11921 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
11922 (match_operand:SI 2 "const_int_operand" "i,i"))))
11923 (clobber (reg:CC 17))]
11924 "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
11925 && INTVAL (operands[2]) == 31
11926 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11929 sar{l}\t{%2, %k0|%k0, %2}"
11930 [(set_attr "type" "imovx,ishift")
11931 (set_attr "prefix_0f" "0,*")
11932 (set_attr "length_immediate" "0,*")
11933 (set_attr "modrm" "0,1")
11934 (set_attr "mode" "SI")])
11936 (define_expand "ashrsi3"
11937 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11938 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11939 (match_operand:QI 2 "nonmemory_operand" "")))
11940 (clobber (reg:CC 17))]
11942 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
11944 (define_insn "*ashrsi3_1_one_bit"
11945 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11946 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11947 (match_operand:QI 2 "const_int_1_operand" "")))
11948 (clobber (reg:CC 17))]
11949 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11950 && (TARGET_SHIFT1 || optimize_size)"
11952 [(set_attr "type" "ishift")
11953 (set (attr "length")
11954 (if_then_else (match_operand:SI 0 "register_operand" "")
11956 (const_string "*")))])
11958 (define_insn "*ashrsi3_1_one_bit_zext"
11959 [(set (match_operand:DI 0 "register_operand" "=r")
11960 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11961 (match_operand:QI 2 "const_int_1_operand" ""))))
11962 (clobber (reg:CC 17))]
11963 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11964 && (TARGET_SHIFT1 || optimize_size)"
11966 [(set_attr "type" "ishift")
11967 (set_attr "length" "2")])
11969 (define_insn "*ashrsi3_1"
11970 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11971 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11972 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11973 (clobber (reg:CC 17))]
11974 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11976 sar{l}\t{%2, %0|%0, %2}
11977 sar{l}\t{%b2, %0|%0, %b2}"
11978 [(set_attr "type" "ishift")
11979 (set_attr "mode" "SI")])
11981 (define_insn "*ashrsi3_1_zext"
11982 [(set (match_operand:DI 0 "register_operand" "=r,r")
11983 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
11984 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11985 (clobber (reg:CC 17))]
11986 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11988 sar{l}\t{%2, %k0|%k0, %2}
11989 sar{l}\t{%b2, %k0|%k0, %b2}"
11990 [(set_attr "type" "ishift")
11991 (set_attr "mode" "SI")])
11993 ;; This pattern can't accept a variable shift count, since shifts by
11994 ;; zero don't affect the flags. We assume that shifts by constant
11995 ;; zero are optimized away.
11996 (define_insn "*ashrsi3_one_bit_cmp"
11999 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12000 (match_operand:QI 2 "const_int_1_operand" ""))
12002 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12003 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
12004 "ix86_match_ccmode (insn, CCGOCmode)
12005 && (TARGET_SHIFT1 || optimize_size)
12006 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12008 [(set_attr "type" "ishift")
12009 (set (attr "length")
12010 (if_then_else (match_operand:SI 0 "register_operand" "")
12012 (const_string "*")))])
12014 (define_insn "*ashrsi3_one_bit_cmp_zext"
12017 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
12018 (match_operand:QI 2 "const_int_1_operand" ""))
12020 (set (match_operand:DI 0 "register_operand" "=r")
12021 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
12022 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
12023 && (TARGET_SHIFT1 || optimize_size)
12024 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12026 [(set_attr "type" "ishift")
12027 (set_attr "length" "2")])
12029 ;; This pattern can't accept a variable shift count, since shifts by
12030 ;; zero don't affect the flags. We assume that shifts by constant
12031 ;; zero are optimized away.
12032 (define_insn "*ashrsi3_cmp"
12035 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12036 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12038 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12039 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
12040 "ix86_match_ccmode (insn, CCGOCmode)
12041 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12042 "sar{l}\t{%2, %0|%0, %2}"
12043 [(set_attr "type" "ishift")
12044 (set_attr "mode" "SI")])
12046 (define_insn "*ashrsi3_cmp_zext"
12049 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
12050 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12052 (set (match_operand:DI 0 "register_operand" "=r")
12053 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
12054 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12055 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12056 "sar{l}\t{%2, %k0|%k0, %2}"
12057 [(set_attr "type" "ishift")
12058 (set_attr "mode" "SI")])
12060 (define_expand "ashrhi3"
12061 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12062 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
12063 (match_operand:QI 2 "nonmemory_operand" "")))
12064 (clobber (reg:CC 17))]
12065 "TARGET_HIMODE_MATH"
12066 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
12068 (define_insn "*ashrhi3_1_one_bit"
12069 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12070 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12071 (match_operand:QI 2 "const_int_1_operand" "")))
12072 (clobber (reg:CC 17))]
12073 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
12074 && (TARGET_SHIFT1 || optimize_size)"
12076 [(set_attr "type" "ishift")
12077 (set (attr "length")
12078 (if_then_else (match_operand 0 "register_operand" "")
12080 (const_string "*")))])
12082 (define_insn "*ashrhi3_1"
12083 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12084 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12085 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12086 (clobber (reg:CC 17))]
12087 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
12089 sar{w}\t{%2, %0|%0, %2}
12090 sar{w}\t{%b2, %0|%0, %b2}"
12091 [(set_attr "type" "ishift")
12092 (set_attr "mode" "HI")])
12094 ;; This pattern can't accept a variable shift count, since shifts by
12095 ;; zero don't affect the flags. We assume that shifts by constant
12096 ;; zero are optimized away.
12097 (define_insn "*ashrhi3_one_bit_cmp"
12100 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12101 (match_operand:QI 2 "const_int_1_operand" ""))
12103 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12104 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
12105 "ix86_match_ccmode (insn, CCGOCmode)
12106 && (TARGET_SHIFT1 || optimize_size)
12107 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
12109 [(set_attr "type" "ishift")
12110 (set (attr "length")
12111 (if_then_else (match_operand 0 "register_operand" "")
12113 (const_string "*")))])
12115 ;; This pattern can't accept a variable shift count, since shifts by
12116 ;; zero don't affect the flags. We assume that shifts by constant
12117 ;; zero are optimized away.
12118 (define_insn "*ashrhi3_cmp"
12121 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12122 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12124 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12125 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
12126 "ix86_match_ccmode (insn, CCGOCmode)
12127 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
12128 "sar{w}\t{%2, %0|%0, %2}"
12129 [(set_attr "type" "ishift")
12130 (set_attr "mode" "HI")])
12132 (define_expand "ashrqi3"
12133 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12134 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
12135 (match_operand:QI 2 "nonmemory_operand" "")))
12136 (clobber (reg:CC 17))]
12137 "TARGET_QIMODE_MATH"
12138 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
12140 (define_insn "*ashrqi3_1_one_bit"
12141 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12142 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12143 (match_operand:QI 2 "const_int_1_operand" "")))
12144 (clobber (reg:CC 17))]
12145 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
12146 && (TARGET_SHIFT1 || optimize_size)"
12148 [(set_attr "type" "ishift")
12149 (set (attr "length")
12150 (if_then_else (match_operand 0 "register_operand" "")
12152 (const_string "*")))])
12154 (define_insn "*ashrqi3_1_one_bit_slp"
12155 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12156 (ashiftrt:QI (match_dup 0)
12157 (match_operand:QI 1 "const_int_1_operand" "")))
12158 (clobber (reg:CC 17))]
12159 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
12160 && (! TARGET_PARTIAL_REG_STALL || optimize_size)
12161 && (TARGET_SHIFT1 || optimize_size)"
12163 [(set_attr "type" "ishift1")
12164 (set (attr "length")
12165 (if_then_else (match_operand 0 "register_operand" "")
12167 (const_string "*")))])
12169 (define_insn "*ashrqi3_1"
12170 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12171 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12172 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12173 (clobber (reg:CC 17))]
12174 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
12176 sar{b}\t{%2, %0|%0, %2}
12177 sar{b}\t{%b2, %0|%0, %b2}"
12178 [(set_attr "type" "ishift")
12179 (set_attr "mode" "QI")])
12181 (define_insn "*ashrqi3_1_slp"
12182 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12183 (ashiftrt:QI (match_dup 0)
12184 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12185 (clobber (reg:CC 17))]
12186 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12187 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12189 sar{b}\t{%1, %0|%0, %1}
12190 sar{b}\t{%b1, %0|%0, %b1}"
12191 [(set_attr "type" "ishift1")
12192 (set_attr "mode" "QI")])
12194 ;; This pattern can't accept a variable shift count, since shifts by
12195 ;; zero don't affect the flags. We assume that shifts by constant
12196 ;; zero are optimized away.
12197 (define_insn "*ashrqi3_one_bit_cmp"
12200 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12201 (match_operand:QI 2 "const_int_1_operand" "I"))
12203 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12204 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
12205 "ix86_match_ccmode (insn, CCGOCmode)
12206 && (TARGET_SHIFT1 || optimize_size)
12207 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
12209 [(set_attr "type" "ishift")
12210 (set (attr "length")
12211 (if_then_else (match_operand 0 "register_operand" "")
12213 (const_string "*")))])
12215 ;; This pattern can't accept a variable shift count, since shifts by
12216 ;; zero don't affect the flags. We assume that shifts by constant
12217 ;; zero are optimized away.
12218 (define_insn "*ashrqi3_cmp"
12221 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12222 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12224 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12225 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
12226 "ix86_match_ccmode (insn, CCGOCmode)
12227 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
12228 "sar{b}\t{%2, %0|%0, %2}"
12229 [(set_attr "type" "ishift")
12230 (set_attr "mode" "QI")])
12232 ;; Logical shift instructions
12234 ;; See comment above `ashldi3' about how this works.
12236 (define_expand "lshrdi3"
12237 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
12238 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
12239 (match_operand:QI 2 "nonmemory_operand" "")))
12240 (clobber (reg:CC 17))])]
12243 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
12245 emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2]));
12248 ix86_expand_binary_operator (LSHIFTRT, DImode, operands);
12252 (define_insn "*lshrdi3_1_one_bit_rex64"
12253 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12254 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12255 (match_operand:QI 2 "const_int_1_operand" "")))
12256 (clobber (reg:CC 17))]
12257 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12258 && (TARGET_SHIFT1 || optimize_size)"
12260 [(set_attr "type" "ishift")
12261 (set (attr "length")
12262 (if_then_else (match_operand:DI 0 "register_operand" "")
12264 (const_string "*")))])
12266 (define_insn "*lshrdi3_1_rex64"
12267 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12268 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12269 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12270 (clobber (reg:CC 17))]
12271 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12273 shr{q}\t{%2, %0|%0, %2}
12274 shr{q}\t{%b2, %0|%0, %b2}"
12275 [(set_attr "type" "ishift")
12276 (set_attr "mode" "DI")])
12278 ;; This pattern can't accept a variable shift count, since shifts by
12279 ;; zero don't affect the flags. We assume that shifts by constant
12280 ;; zero are optimized away.
12281 (define_insn "*lshrdi3_cmp_one_bit_rex64"
12284 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12285 (match_operand:QI 2 "const_int_1_operand" ""))
12287 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12288 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
12289 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12290 && (TARGET_SHIFT1 || optimize_size)
12291 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12293 [(set_attr "type" "ishift")
12294 (set (attr "length")
12295 (if_then_else (match_operand:DI 0 "register_operand" "")
12297 (const_string "*")))])
12299 ;; This pattern can't accept a variable shift count, since shifts by
12300 ;; zero don't affect the flags. We assume that shifts by constant
12301 ;; zero are optimized away.
12302 (define_insn "*lshrdi3_cmp_rex64"
12305 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12306 (match_operand:QI 2 "const_int_operand" "e"))
12308 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12309 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
12310 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12311 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12312 "shr{q}\t{%2, %0|%0, %2}"
12313 [(set_attr "type" "ishift")
12314 (set_attr "mode" "DI")])
12316 (define_insn "lshrdi3_1"
12317 [(set (match_operand:DI 0 "register_operand" "=r")
12318 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
12319 (match_operand:QI 2 "nonmemory_operand" "Jc")))
12320 (clobber (match_scratch:SI 3 "=&r"))
12321 (clobber (reg:CC 17))]
12322 "!TARGET_64BIT && TARGET_CMOVE"
12324 [(set_attr "type" "multi")])
12326 (define_insn "*lshrdi3_2"
12327 [(set (match_operand:DI 0 "register_operand" "=r")
12328 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
12329 (match_operand:QI 2 "nonmemory_operand" "Jc")))
12330 (clobber (reg:CC 17))]
12333 [(set_attr "type" "multi")])
12336 [(set (match_operand:DI 0 "register_operand" "")
12337 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
12338 (match_operand:QI 2 "nonmemory_operand" "")))
12339 (clobber (match_scratch:SI 3 ""))
12340 (clobber (reg:CC 17))]
12341 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
12343 "ix86_split_lshrdi (operands, operands[3]); DONE;")
12346 [(set (match_operand:DI 0 "register_operand" "")
12347 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
12348 (match_operand:QI 2 "nonmemory_operand" "")))
12349 (clobber (reg:CC 17))]
12350 "!TARGET_64BIT && reload_completed"
12352 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
12354 (define_expand "lshrsi3"
12355 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12356 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
12357 (match_operand:QI 2 "nonmemory_operand" "")))
12358 (clobber (reg:CC 17))]
12360 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
12362 (define_insn "*lshrsi3_1_one_bit"
12363 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12364 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12365 (match_operand:QI 2 "const_int_1_operand" "")))
12366 (clobber (reg:CC 17))]
12367 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12368 && (TARGET_SHIFT1 || optimize_size)"
12370 [(set_attr "type" "ishift")
12371 (set (attr "length")
12372 (if_then_else (match_operand:SI 0 "register_operand" "")
12374 (const_string "*")))])
12376 (define_insn "*lshrsi3_1_one_bit_zext"
12377 [(set (match_operand:DI 0 "register_operand" "=r")
12378 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
12379 (match_operand:QI 2 "const_int_1_operand" "")))
12380 (clobber (reg:CC 17))]
12381 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12382 && (TARGET_SHIFT1 || optimize_size)"
12384 [(set_attr "type" "ishift")
12385 (set_attr "length" "2")])
12387 (define_insn "*lshrsi3_1"
12388 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12389 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12390 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12391 (clobber (reg:CC 17))]
12392 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12394 shr{l}\t{%2, %0|%0, %2}
12395 shr{l}\t{%b2, %0|%0, %b2}"
12396 [(set_attr "type" "ishift")
12397 (set_attr "mode" "SI")])
12399 (define_insn "*lshrsi3_1_zext"
12400 [(set (match_operand:DI 0 "register_operand" "=r,r")
12402 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12403 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12404 (clobber (reg:CC 17))]
12405 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12407 shr{l}\t{%2, %k0|%k0, %2}
12408 shr{l}\t{%b2, %k0|%k0, %b2}"
12409 [(set_attr "type" "ishift")
12410 (set_attr "mode" "SI")])
12412 ;; This pattern can't accept a variable shift count, since shifts by
12413 ;; zero don't affect the flags. We assume that shifts by constant
12414 ;; zero are optimized away.
12415 (define_insn "*lshrsi3_one_bit_cmp"
12418 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12419 (match_operand:QI 2 "const_int_1_operand" ""))
12421 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12422 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
12423 "ix86_match_ccmode (insn, CCGOCmode)
12424 && (TARGET_SHIFT1 || optimize_size)
12425 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12427 [(set_attr "type" "ishift")
12428 (set (attr "length")
12429 (if_then_else (match_operand:SI 0 "register_operand" "")
12431 (const_string "*")))])
12433 (define_insn "*lshrsi3_cmp_one_bit_zext"
12436 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
12437 (match_operand:QI 2 "const_int_1_operand" ""))
12439 (set (match_operand:DI 0 "register_operand" "=r")
12440 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
12441 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12442 && (TARGET_SHIFT1 || optimize_size)
12443 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12445 [(set_attr "type" "ishift")
12446 (set_attr "length" "2")])
12448 ;; This pattern can't accept a variable shift count, since shifts by
12449 ;; zero don't affect the flags. We assume that shifts by constant
12450 ;; zero are optimized away.
12451 (define_insn "*lshrsi3_cmp"
12454 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12455 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12457 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12458 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
12459 "ix86_match_ccmode (insn, CCGOCmode)
12460 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12461 "shr{l}\t{%2, %0|%0, %2}"
12462 [(set_attr "type" "ishift")
12463 (set_attr "mode" "SI")])
12465 (define_insn "*lshrsi3_cmp_zext"
12468 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
12469 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12471 (set (match_operand:DI 0 "register_operand" "=r")
12472 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
12473 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12474 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12475 "shr{l}\t{%2, %k0|%k0, %2}"
12476 [(set_attr "type" "ishift")
12477 (set_attr "mode" "SI")])
12479 (define_expand "lshrhi3"
12480 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12481 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
12482 (match_operand:QI 2 "nonmemory_operand" "")))
12483 (clobber (reg:CC 17))]
12484 "TARGET_HIMODE_MATH"
12485 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
12487 (define_insn "*lshrhi3_1_one_bit"
12488 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12489 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12490 (match_operand:QI 2 "const_int_1_operand" "")))
12491 (clobber (reg:CC 17))]
12492 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12493 && (TARGET_SHIFT1 || optimize_size)"
12495 [(set_attr "type" "ishift")
12496 (set (attr "length")
12497 (if_then_else (match_operand 0 "register_operand" "")
12499 (const_string "*")))])
12501 (define_insn "*lshrhi3_1"
12502 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12503 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12504 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12505 (clobber (reg:CC 17))]
12506 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12508 shr{w}\t{%2, %0|%0, %2}
12509 shr{w}\t{%b2, %0|%0, %b2}"
12510 [(set_attr "type" "ishift")
12511 (set_attr "mode" "HI")])
12513 ;; This pattern can't accept a variable shift count, since shifts by
12514 ;; zero don't affect the flags. We assume that shifts by constant
12515 ;; zero are optimized away.
12516 (define_insn "*lshrhi3_one_bit_cmp"
12519 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12520 (match_operand:QI 2 "const_int_1_operand" ""))
12522 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12523 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
12524 "ix86_match_ccmode (insn, CCGOCmode)
12525 && (TARGET_SHIFT1 || optimize_size)
12526 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12528 [(set_attr "type" "ishift")
12529 (set (attr "length")
12530 (if_then_else (match_operand:SI 0 "register_operand" "")
12532 (const_string "*")))])
12534 ;; This pattern can't accept a variable shift count, since shifts by
12535 ;; zero don't affect the flags. We assume that shifts by constant
12536 ;; zero are optimized away.
12537 (define_insn "*lshrhi3_cmp"
12540 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12541 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12543 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12544 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
12545 "ix86_match_ccmode (insn, CCGOCmode)
12546 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12547 "shr{w}\t{%2, %0|%0, %2}"
12548 [(set_attr "type" "ishift")
12549 (set_attr "mode" "HI")])
12551 (define_expand "lshrqi3"
12552 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12553 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
12554 (match_operand:QI 2 "nonmemory_operand" "")))
12555 (clobber (reg:CC 17))]
12556 "TARGET_QIMODE_MATH"
12557 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
12559 (define_insn "*lshrqi3_1_one_bit"
12560 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12561 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12562 (match_operand:QI 2 "const_int_1_operand" "")))
12563 (clobber (reg:CC 17))]
12564 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
12565 && (TARGET_SHIFT1 || optimize_size)"
12567 [(set_attr "type" "ishift")
12568 (set (attr "length")
12569 (if_then_else (match_operand 0 "register_operand" "")
12571 (const_string "*")))])
12573 (define_insn "*lshrqi3_1_one_bit_slp"
12574 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12575 (lshiftrt:QI (match_dup 0)
12576 (match_operand:QI 1 "const_int_1_operand" "")))
12577 (clobber (reg:CC 17))]
12578 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12579 && (TARGET_SHIFT1 || optimize_size)"
12581 [(set_attr "type" "ishift1")
12582 (set (attr "length")
12583 (if_then_else (match_operand 0 "register_operand" "")
12585 (const_string "*")))])
12587 (define_insn "*lshrqi3_1"
12588 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12589 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12590 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12591 (clobber (reg:CC 17))]
12592 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12594 shr{b}\t{%2, %0|%0, %2}
12595 shr{b}\t{%b2, %0|%0, %b2}"
12596 [(set_attr "type" "ishift")
12597 (set_attr "mode" "QI")])
12599 (define_insn "*lshrqi3_1_slp"
12600 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12601 (lshiftrt:QI (match_dup 0)
12602 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12603 (clobber (reg:CC 17))]
12604 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12605 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12607 shr{b}\t{%1, %0|%0, %1}
12608 shr{b}\t{%b1, %0|%0, %b1}"
12609 [(set_attr "type" "ishift1")
12610 (set_attr "mode" "QI")])
12612 ;; This pattern can't accept a variable shift count, since shifts by
12613 ;; zero don't affect the flags. We assume that shifts by constant
12614 ;; zero are optimized away.
12615 (define_insn "*lshrqi2_one_bit_cmp"
12618 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12619 (match_operand:QI 2 "const_int_1_operand" ""))
12621 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12622 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12623 "ix86_match_ccmode (insn, CCGOCmode)
12624 && (TARGET_SHIFT1 || optimize_size)
12625 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12627 [(set_attr "type" "ishift")
12628 (set (attr "length")
12629 (if_then_else (match_operand:SI 0 "register_operand" "")
12631 (const_string "*")))])
12633 ;; This pattern can't accept a variable shift count, since shifts by
12634 ;; zero don't affect the flags. We assume that shifts by constant
12635 ;; zero are optimized away.
12636 (define_insn "*lshrqi2_cmp"
12639 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12640 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12642 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12643 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12644 "ix86_match_ccmode (insn, CCGOCmode)
12645 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12646 "shr{b}\t{%2, %0|%0, %2}"
12647 [(set_attr "type" "ishift")
12648 (set_attr "mode" "QI")])
12650 ;; Rotate instructions
12652 (define_expand "rotldi3"
12653 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12654 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
12655 (match_operand:QI 2 "nonmemory_operand" "")))
12656 (clobber (reg:CC 17))]
12658 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
12660 (define_insn "*rotlsi3_1_one_bit_rex64"
12661 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12662 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12663 (match_operand:QI 2 "const_int_1_operand" "")))
12664 (clobber (reg:CC 17))]
12665 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
12666 && (TARGET_SHIFT1 || optimize_size)"
12668 [(set_attr "type" "rotate")
12669 (set (attr "length")
12670 (if_then_else (match_operand:DI 0 "register_operand" "")
12672 (const_string "*")))])
12674 (define_insn "*rotldi3_1_rex64"
12675 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12676 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12677 (match_operand:QI 2 "nonmemory_operand" "e,c")))
12678 (clobber (reg:CC 17))]
12679 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
12681 rol{q}\t{%2, %0|%0, %2}
12682 rol{q}\t{%b2, %0|%0, %b2}"
12683 [(set_attr "type" "rotate")
12684 (set_attr "mode" "DI")])
12686 (define_expand "rotlsi3"
12687 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12688 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
12689 (match_operand:QI 2 "nonmemory_operand" "")))
12690 (clobber (reg:CC 17))]
12692 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
12694 (define_insn "*rotlsi3_1_one_bit"
12695 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12696 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12697 (match_operand:QI 2 "const_int_1_operand" "")))
12698 (clobber (reg:CC 17))]
12699 "ix86_binary_operator_ok (ROTATE, SImode, operands)
12700 && (TARGET_SHIFT1 || optimize_size)"
12702 [(set_attr "type" "rotate")
12703 (set (attr "length")
12704 (if_then_else (match_operand:SI 0 "register_operand" "")
12706 (const_string "*")))])
12708 (define_insn "*rotlsi3_1_one_bit_zext"
12709 [(set (match_operand:DI 0 "register_operand" "=r")
12711 (rotate:SI (match_operand:SI 1 "register_operand" "0")
12712 (match_operand:QI 2 "const_int_1_operand" ""))))
12713 (clobber (reg:CC 17))]
12714 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
12715 && (TARGET_SHIFT1 || optimize_size)"
12717 [(set_attr "type" "rotate")
12718 (set_attr "length" "2")])
12720 (define_insn "*rotlsi3_1"
12721 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12722 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12723 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12724 (clobber (reg:CC 17))]
12725 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
12727 rol{l}\t{%2, %0|%0, %2}
12728 rol{l}\t{%b2, %0|%0, %b2}"
12729 [(set_attr "type" "rotate")
12730 (set_attr "mode" "SI")])
12732 (define_insn "*rotlsi3_1_zext"
12733 [(set (match_operand:DI 0 "register_operand" "=r,r")
12735 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
12736 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12737 (clobber (reg:CC 17))]
12738 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
12740 rol{l}\t{%2, %k0|%k0, %2}
12741 rol{l}\t{%b2, %k0|%k0, %b2}"
12742 [(set_attr "type" "rotate")
12743 (set_attr "mode" "SI")])
12745 (define_expand "rotlhi3"
12746 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12747 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
12748 (match_operand:QI 2 "nonmemory_operand" "")))
12749 (clobber (reg:CC 17))]
12750 "TARGET_HIMODE_MATH"
12751 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
12753 (define_insn "*rotlhi3_1_one_bit"
12754 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12755 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12756 (match_operand:QI 2 "const_int_1_operand" "")))
12757 (clobber (reg:CC 17))]
12758 "ix86_binary_operator_ok (ROTATE, HImode, operands)
12759 && (TARGET_SHIFT1 || optimize_size)"
12761 [(set_attr "type" "rotate")
12762 (set (attr "length")
12763 (if_then_else (match_operand 0 "register_operand" "")
12765 (const_string "*")))])
12767 (define_insn "*rotlhi3_1"
12768 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12769 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12770 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12771 (clobber (reg:CC 17))]
12772 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
12774 rol{w}\t{%2, %0|%0, %2}
12775 rol{w}\t{%b2, %0|%0, %b2}"
12776 [(set_attr "type" "rotate")
12777 (set_attr "mode" "HI")])
12779 (define_expand "rotlqi3"
12780 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12781 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
12782 (match_operand:QI 2 "nonmemory_operand" "")))
12783 (clobber (reg:CC 17))]
12784 "TARGET_QIMODE_MATH"
12785 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
12787 (define_insn "*rotlqi3_1_one_bit_slp"
12788 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12789 (rotate:QI (match_dup 0)
12790 (match_operand:QI 1 "const_int_1_operand" "")))
12791 (clobber (reg:CC 17))]
12792 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12793 && (TARGET_SHIFT1 || optimize_size)"
12795 [(set_attr "type" "rotate1")
12796 (set (attr "length")
12797 (if_then_else (match_operand 0 "register_operand" "")
12799 (const_string "*")))])
12801 (define_insn "*rotlqi3_1_one_bit"
12802 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12803 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12804 (match_operand:QI 2 "const_int_1_operand" "")))
12805 (clobber (reg:CC 17))]
12806 "ix86_binary_operator_ok (ROTATE, QImode, operands)
12807 && (TARGET_SHIFT1 || optimize_size)"
12809 [(set_attr "type" "rotate")
12810 (set (attr "length")
12811 (if_then_else (match_operand 0 "register_operand" "")
12813 (const_string "*")))])
12815 (define_insn "*rotlqi3_1_slp"
12816 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12817 (rotate:QI (match_dup 0)
12818 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12819 (clobber (reg:CC 17))]
12820 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12821 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12823 rol{b}\t{%1, %0|%0, %1}
12824 rol{b}\t{%b1, %0|%0, %b1}"
12825 [(set_attr "type" "rotate1")
12826 (set_attr "mode" "QI")])
12828 (define_insn "*rotlqi3_1"
12829 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12830 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12831 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12832 (clobber (reg:CC 17))]
12833 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
12835 rol{b}\t{%2, %0|%0, %2}
12836 rol{b}\t{%b2, %0|%0, %b2}"
12837 [(set_attr "type" "rotate")
12838 (set_attr "mode" "QI")])
12840 (define_expand "rotrdi3"
12841 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12842 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
12843 (match_operand:QI 2 "nonmemory_operand" "")))
12844 (clobber (reg:CC 17))]
12846 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
12848 (define_insn "*rotrdi3_1_one_bit_rex64"
12849 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12850 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12851 (match_operand:QI 2 "const_int_1_operand" "")))
12852 (clobber (reg:CC 17))]
12853 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
12854 && (TARGET_SHIFT1 || optimize_size)"
12856 [(set_attr "type" "rotate")
12857 (set (attr "length")
12858 (if_then_else (match_operand:DI 0 "register_operand" "")
12860 (const_string "*")))])
12862 (define_insn "*rotrdi3_1_rex64"
12863 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12864 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12865 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12866 (clobber (reg:CC 17))]
12867 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
12869 ror{q}\t{%2, %0|%0, %2}
12870 ror{q}\t{%b2, %0|%0, %b2}"
12871 [(set_attr "type" "rotate")
12872 (set_attr "mode" "DI")])
12874 (define_expand "rotrsi3"
12875 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12876 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
12877 (match_operand:QI 2 "nonmemory_operand" "")))
12878 (clobber (reg:CC 17))]
12880 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
12882 (define_insn "*rotrsi3_1_one_bit"
12883 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12884 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12885 (match_operand:QI 2 "const_int_1_operand" "")))
12886 (clobber (reg:CC 17))]
12887 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
12888 && (TARGET_SHIFT1 || optimize_size)"
12890 [(set_attr "type" "rotate")
12891 (set (attr "length")
12892 (if_then_else (match_operand:SI 0 "register_operand" "")
12894 (const_string "*")))])
12896 (define_insn "*rotrsi3_1_one_bit_zext"
12897 [(set (match_operand:DI 0 "register_operand" "=r")
12899 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
12900 (match_operand:QI 2 "const_int_1_operand" ""))))
12901 (clobber (reg:CC 17))]
12902 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
12903 && (TARGET_SHIFT1 || optimize_size)"
12905 [(set_attr "type" "rotate")
12906 (set (attr "length")
12907 (if_then_else (match_operand:SI 0 "register_operand" "")
12909 (const_string "*")))])
12911 (define_insn "*rotrsi3_1"
12912 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12913 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12914 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12915 (clobber (reg:CC 17))]
12916 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12918 ror{l}\t{%2, %0|%0, %2}
12919 ror{l}\t{%b2, %0|%0, %b2}"
12920 [(set_attr "type" "rotate")
12921 (set_attr "mode" "SI")])
12923 (define_insn "*rotrsi3_1_zext"
12924 [(set (match_operand:DI 0 "register_operand" "=r,r")
12926 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
12927 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12928 (clobber (reg:CC 17))]
12929 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12931 ror{l}\t{%2, %k0|%k0, %2}
12932 ror{l}\t{%b2, %k0|%k0, %b2}"
12933 [(set_attr "type" "rotate")
12934 (set_attr "mode" "SI")])
12936 (define_expand "rotrhi3"
12937 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12938 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
12939 (match_operand:QI 2 "nonmemory_operand" "")))
12940 (clobber (reg:CC 17))]
12941 "TARGET_HIMODE_MATH"
12942 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
12944 (define_insn "*rotrhi3_one_bit"
12945 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12946 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12947 (match_operand:QI 2 "const_int_1_operand" "")))
12948 (clobber (reg:CC 17))]
12949 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
12950 && (TARGET_SHIFT1 || optimize_size)"
12952 [(set_attr "type" "rotate")
12953 (set (attr "length")
12954 (if_then_else (match_operand 0 "register_operand" "")
12956 (const_string "*")))])
12958 (define_insn "*rotrhi3"
12959 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12960 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12961 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12962 (clobber (reg:CC 17))]
12963 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
12965 ror{w}\t{%2, %0|%0, %2}
12966 ror{w}\t{%b2, %0|%0, %b2}"
12967 [(set_attr "type" "rotate")
12968 (set_attr "mode" "HI")])
12970 (define_expand "rotrqi3"
12971 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12972 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
12973 (match_operand:QI 2 "nonmemory_operand" "")))
12974 (clobber (reg:CC 17))]
12975 "TARGET_QIMODE_MATH"
12976 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
12978 (define_insn "*rotrqi3_1_one_bit"
12979 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12980 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12981 (match_operand:QI 2 "const_int_1_operand" "")))
12982 (clobber (reg:CC 17))]
12983 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
12984 && (TARGET_SHIFT1 || optimize_size)"
12986 [(set_attr "type" "rotate")
12987 (set (attr "length")
12988 (if_then_else (match_operand 0 "register_operand" "")
12990 (const_string "*")))])
12992 (define_insn "*rotrqi3_1_one_bit_slp"
12993 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12994 (rotatert:QI (match_dup 0)
12995 (match_operand:QI 1 "const_int_1_operand" "")))
12996 (clobber (reg:CC 17))]
12997 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12998 && (TARGET_SHIFT1 || optimize_size)"
13000 [(set_attr "type" "rotate1")
13001 (set (attr "length")
13002 (if_then_else (match_operand 0 "register_operand" "")
13004 (const_string "*")))])
13006 (define_insn "*rotrqi3_1"
13007 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
13008 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
13009 (match_operand:QI 2 "nonmemory_operand" "I,c")))
13010 (clobber (reg:CC 17))]
13011 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
13013 ror{b}\t{%2, %0|%0, %2}
13014 ror{b}\t{%b2, %0|%0, %b2}"
13015 [(set_attr "type" "rotate")
13016 (set_attr "mode" "QI")])
13018 (define_insn "*rotrqi3_1_slp"
13019 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
13020 (rotatert:QI (match_dup 0)
13021 (match_operand:QI 1 "nonmemory_operand" "I,c")))
13022 (clobber (reg:CC 17))]
13023 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
13024 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
13026 ror{b}\t{%1, %0|%0, %1}
13027 ror{b}\t{%b1, %0|%0, %b1}"
13028 [(set_attr "type" "rotate1")
13029 (set_attr "mode" "QI")])
13031 ;; Bit set / bit test instructions
13033 (define_expand "extv"
13034 [(set (match_operand:SI 0 "register_operand" "")
13035 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
13036 (match_operand:SI 2 "immediate_operand" "")
13037 (match_operand:SI 3 "immediate_operand" "")))]
13040 /* Handle extractions from %ah et al. */
13041 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
13044 /* From mips.md: extract_bit_field doesn't verify that our source
13045 matches the predicate, so check it again here. */
13046 if (! register_operand (operands[1], VOIDmode))
13050 (define_expand "extzv"
13051 [(set (match_operand:SI 0 "register_operand" "")
13052 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
13053 (match_operand:SI 2 "immediate_operand" "")
13054 (match_operand:SI 3 "immediate_operand" "")))]
13057 /* Handle extractions from %ah et al. */
13058 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
13061 /* From mips.md: extract_bit_field doesn't verify that our source
13062 matches the predicate, so check it again here. */
13063 if (! register_operand (operands[1], VOIDmode))
13067 (define_expand "insv"
13068 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
13069 (match_operand:SI 1 "immediate_operand" "")
13070 (match_operand:SI 2 "immediate_operand" ""))
13071 (match_operand:SI 3 "register_operand" ""))]
13074 /* Handle extractions from %ah et al. */
13075 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
13078 /* From mips.md: insert_bit_field doesn't verify that our source
13079 matches the predicate, so check it again here. */
13080 if (! register_operand (operands[0], VOIDmode))
13084 ;; %%% bts, btr, btc, bt.
13086 ;; Store-flag instructions.
13088 ;; For all sCOND expanders, also expand the compare or test insn that
13089 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
13091 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
13092 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
13093 ;; way, which can later delete the movzx if only QImode is needed.
13095 (define_expand "seq"
13096 [(set (match_operand:QI 0 "register_operand" "")
13097 (eq:QI (reg:CC 17) (const_int 0)))]
13099 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
13101 (define_expand "sne"
13102 [(set (match_operand:QI 0 "register_operand" "")
13103 (ne:QI (reg:CC 17) (const_int 0)))]
13105 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
13107 (define_expand "sgt"
13108 [(set (match_operand:QI 0 "register_operand" "")
13109 (gt:QI (reg:CC 17) (const_int 0)))]
13111 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
13113 (define_expand "sgtu"
13114 [(set (match_operand:QI 0 "register_operand" "")
13115 (gtu:QI (reg:CC 17) (const_int 0)))]
13117 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
13119 (define_expand "slt"
13120 [(set (match_operand:QI 0 "register_operand" "")
13121 (lt:QI (reg:CC 17) (const_int 0)))]
13123 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
13125 (define_expand "sltu"
13126 [(set (match_operand:QI 0 "register_operand" "")
13127 (ltu:QI (reg:CC 17) (const_int 0)))]
13129 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
13131 (define_expand "sge"
13132 [(set (match_operand:QI 0 "register_operand" "")
13133 (ge:QI (reg:CC 17) (const_int 0)))]
13135 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
13137 (define_expand "sgeu"
13138 [(set (match_operand:QI 0 "register_operand" "")
13139 (geu:QI (reg:CC 17) (const_int 0)))]
13141 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
13143 (define_expand "sle"
13144 [(set (match_operand:QI 0 "register_operand" "")
13145 (le:QI (reg:CC 17) (const_int 0)))]
13147 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
13149 (define_expand "sleu"
13150 [(set (match_operand:QI 0 "register_operand" "")
13151 (leu:QI (reg:CC 17) (const_int 0)))]
13153 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
13155 (define_expand "sunordered"
13156 [(set (match_operand:QI 0 "register_operand" "")
13157 (unordered:QI (reg:CC 17) (const_int 0)))]
13158 "TARGET_80387 || TARGET_SSE"
13159 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
13161 (define_expand "sordered"
13162 [(set (match_operand:QI 0 "register_operand" "")
13163 (ordered:QI (reg:CC 17) (const_int 0)))]
13165 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
13167 (define_expand "suneq"
13168 [(set (match_operand:QI 0 "register_operand" "")
13169 (uneq:QI (reg:CC 17) (const_int 0)))]
13170 "TARGET_80387 || TARGET_SSE"
13171 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
13173 (define_expand "sunge"
13174 [(set (match_operand:QI 0 "register_operand" "")
13175 (unge:QI (reg:CC 17) (const_int 0)))]
13176 "TARGET_80387 || TARGET_SSE"
13177 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
13179 (define_expand "sungt"
13180 [(set (match_operand:QI 0 "register_operand" "")
13181 (ungt:QI (reg:CC 17) (const_int 0)))]
13182 "TARGET_80387 || TARGET_SSE"
13183 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
13185 (define_expand "sunle"
13186 [(set (match_operand:QI 0 "register_operand" "")
13187 (unle:QI (reg:CC 17) (const_int 0)))]
13188 "TARGET_80387 || TARGET_SSE"
13189 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
13191 (define_expand "sunlt"
13192 [(set (match_operand:QI 0 "register_operand" "")
13193 (unlt:QI (reg:CC 17) (const_int 0)))]
13194 "TARGET_80387 || TARGET_SSE"
13195 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
13197 (define_expand "sltgt"
13198 [(set (match_operand:QI 0 "register_operand" "")
13199 (ltgt:QI (reg:CC 17) (const_int 0)))]
13200 "TARGET_80387 || TARGET_SSE"
13201 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
13203 (define_insn "*setcc_1"
13204 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
13205 (match_operator:QI 1 "ix86_comparison_operator"
13206 [(reg 17) (const_int 0)]))]
13209 [(set_attr "type" "setcc")
13210 (set_attr "mode" "QI")])
13212 (define_insn "setcc_2"
13213 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
13214 (match_operator:QI 1 "ix86_comparison_operator"
13215 [(reg 17) (const_int 0)]))]
13218 [(set_attr "type" "setcc")
13219 (set_attr "mode" "QI")])
13221 ;; In general it is not safe to assume too much about CCmode registers,
13222 ;; so simplify-rtx stops when it sees a second one. Under certain
13223 ;; conditions this is safe on x86, so help combine not create
13230 [(set (match_operand:QI 0 "nonimmediate_operand" "")
13231 (ne:QI (match_operator 1 "ix86_comparison_operator"
13232 [(reg 17) (const_int 0)])
13235 [(set (match_dup 0) (match_dup 1))]
13237 PUT_MODE (operands[1], QImode);
13241 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
13242 (ne:QI (match_operator 1 "ix86_comparison_operator"
13243 [(reg 17) (const_int 0)])
13246 [(set (match_dup 0) (match_dup 1))]
13248 PUT_MODE (operands[1], QImode);
13252 [(set (match_operand:QI 0 "nonimmediate_operand" "")
13253 (eq:QI (match_operator 1 "ix86_comparison_operator"
13254 [(reg 17) (const_int 0)])
13257 [(set (match_dup 0) (match_dup 1))]
13259 rtx new_op1 = copy_rtx (operands[1]);
13260 operands[1] = new_op1;
13261 PUT_MODE (new_op1, QImode);
13262 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
13263 GET_MODE (XEXP (new_op1, 0))));
13265 /* Make sure that (a) the CCmode we have for the flags is strong
13266 enough for the reversed compare or (b) we have a valid FP compare. */
13267 if (! ix86_comparison_operator (new_op1, VOIDmode))
13272 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
13273 (eq:QI (match_operator 1 "ix86_comparison_operator"
13274 [(reg 17) (const_int 0)])
13277 [(set (match_dup 0) (match_dup 1))]
13279 rtx new_op1 = copy_rtx (operands[1]);
13280 operands[1] = new_op1;
13281 PUT_MODE (new_op1, QImode);
13282 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
13283 GET_MODE (XEXP (new_op1, 0))));
13285 /* Make sure that (a) the CCmode we have for the flags is strong
13286 enough for the reversed compare or (b) we have a valid FP compare. */
13287 if (! ix86_comparison_operator (new_op1, VOIDmode))
13291 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
13292 ;; subsequent logical operations are used to imitate conditional moves.
13293 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
13294 ;; it directly. Further holding this value in pseudo register might bring
13295 ;; problem in implicit normalization in spill code.
13296 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
13297 ;; instructions after reload by splitting the conditional move patterns.
13299 (define_insn "*sse_setccsf"
13300 [(set (match_operand:SF 0 "register_operand" "=x")
13301 (match_operator:SF 1 "sse_comparison_operator"
13302 [(match_operand:SF 2 "register_operand" "0")
13303 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
13304 "TARGET_SSE && reload_completed"
13305 "cmp%D1ss\t{%3, %0|%0, %3}"
13306 [(set_attr "type" "ssecmp")
13307 (set_attr "mode" "SF")])
13309 (define_insn "*sse_setccdf"
13310 [(set (match_operand:DF 0 "register_operand" "=Y")
13311 (match_operator:DF 1 "sse_comparison_operator"
13312 [(match_operand:DF 2 "register_operand" "0")
13313 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
13314 "TARGET_SSE2 && reload_completed"
13315 "cmp%D1sd\t{%3, %0|%0, %3}"
13316 [(set_attr "type" "ssecmp")
13317 (set_attr "mode" "DF")])
13319 ;; Basic conditional jump instructions.
13320 ;; We ignore the overflow flag for signed branch instructions.
13322 ;; For all bCOND expanders, also expand the compare or test insn that
13323 ;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
13325 (define_expand "beq"
13327 (if_then_else (match_dup 1)
13328 (label_ref (match_operand 0 "" ""))
13331 "ix86_expand_branch (EQ, operands[0]); DONE;")
13333 (define_expand "bne"
13335 (if_then_else (match_dup 1)
13336 (label_ref (match_operand 0 "" ""))
13339 "ix86_expand_branch (NE, operands[0]); DONE;")
13341 (define_expand "bgt"
13343 (if_then_else (match_dup 1)
13344 (label_ref (match_operand 0 "" ""))
13347 "ix86_expand_branch (GT, operands[0]); DONE;")
13349 (define_expand "bgtu"
13351 (if_then_else (match_dup 1)
13352 (label_ref (match_operand 0 "" ""))
13355 "ix86_expand_branch (GTU, operands[0]); DONE;")
13357 (define_expand "blt"
13359 (if_then_else (match_dup 1)
13360 (label_ref (match_operand 0 "" ""))
13363 "ix86_expand_branch (LT, operands[0]); DONE;")
13365 (define_expand "bltu"
13367 (if_then_else (match_dup 1)
13368 (label_ref (match_operand 0 "" ""))
13371 "ix86_expand_branch (LTU, operands[0]); DONE;")
13373 (define_expand "bge"
13375 (if_then_else (match_dup 1)
13376 (label_ref (match_operand 0 "" ""))
13379 "ix86_expand_branch (GE, operands[0]); DONE;")
13381 (define_expand "bgeu"
13383 (if_then_else (match_dup 1)
13384 (label_ref (match_operand 0 "" ""))
13387 "ix86_expand_branch (GEU, operands[0]); DONE;")
13389 (define_expand "ble"
13391 (if_then_else (match_dup 1)
13392 (label_ref (match_operand 0 "" ""))
13395 "ix86_expand_branch (LE, operands[0]); DONE;")
13397 (define_expand "bleu"
13399 (if_then_else (match_dup 1)
13400 (label_ref (match_operand 0 "" ""))
13403 "ix86_expand_branch (LEU, operands[0]); DONE;")
13405 (define_expand "bunordered"
13407 (if_then_else (match_dup 1)
13408 (label_ref (match_operand 0 "" ""))
13410 "TARGET_80387 || TARGET_SSE"
13411 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
13413 (define_expand "bordered"
13415 (if_then_else (match_dup 1)
13416 (label_ref (match_operand 0 "" ""))
13418 "TARGET_80387 || TARGET_SSE"
13419 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
13421 (define_expand "buneq"
13423 (if_then_else (match_dup 1)
13424 (label_ref (match_operand 0 "" ""))
13426 "TARGET_80387 || TARGET_SSE"
13427 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
13429 (define_expand "bunge"
13431 (if_then_else (match_dup 1)
13432 (label_ref (match_operand 0 "" ""))
13434 "TARGET_80387 || TARGET_SSE"
13435 "ix86_expand_branch (UNGE, operands[0]); DONE;")
13437 (define_expand "bungt"
13439 (if_then_else (match_dup 1)
13440 (label_ref (match_operand 0 "" ""))
13442 "TARGET_80387 || TARGET_SSE"
13443 "ix86_expand_branch (UNGT, operands[0]); DONE;")
13445 (define_expand "bunle"
13447 (if_then_else (match_dup 1)
13448 (label_ref (match_operand 0 "" ""))
13450 "TARGET_80387 || TARGET_SSE"
13451 "ix86_expand_branch (UNLE, operands[0]); DONE;")
13453 (define_expand "bunlt"
13455 (if_then_else (match_dup 1)
13456 (label_ref (match_operand 0 "" ""))
13458 "TARGET_80387 || TARGET_SSE"
13459 "ix86_expand_branch (UNLT, operands[0]); DONE;")
13461 (define_expand "bltgt"
13463 (if_then_else (match_dup 1)
13464 (label_ref (match_operand 0 "" ""))
13466 "TARGET_80387 || TARGET_SSE"
13467 "ix86_expand_branch (LTGT, operands[0]); DONE;")
13469 (define_insn "*jcc_1"
13471 (if_then_else (match_operator 1 "ix86_comparison_operator"
13472 [(reg 17) (const_int 0)])
13473 (label_ref (match_operand 0 "" ""))
13477 [(set_attr "type" "ibr")
13478 (set_attr "modrm" "0")
13479 (set (attr "length")
13480 (if_then_else (and (ge (minus (match_dup 0) (pc))
13482 (lt (minus (match_dup 0) (pc))
13487 (define_insn "*jcc_2"
13489 (if_then_else (match_operator 1 "ix86_comparison_operator"
13490 [(reg 17) (const_int 0)])
13492 (label_ref (match_operand 0 "" ""))))]
13495 [(set_attr "type" "ibr")
13496 (set_attr "modrm" "0")
13497 (set (attr "length")
13498 (if_then_else (and (ge (minus (match_dup 0) (pc))
13500 (lt (minus (match_dup 0) (pc))
13505 ;; In general it is not safe to assume too much about CCmode registers,
13506 ;; so simplify-rtx stops when it sees a second one. Under certain
13507 ;; conditions this is safe on x86, so help combine not create
13515 (if_then_else (ne (match_operator 0 "ix86_comparison_operator"
13516 [(reg 17) (const_int 0)])
13518 (label_ref (match_operand 1 "" ""))
13522 (if_then_else (match_dup 0)
13523 (label_ref (match_dup 1))
13526 PUT_MODE (operands[0], VOIDmode);
13531 (if_then_else (eq (match_operator 0 "ix86_comparison_operator"
13532 [(reg 17) (const_int 0)])
13534 (label_ref (match_operand 1 "" ""))
13538 (if_then_else (match_dup 0)
13539 (label_ref (match_dup 1))
13542 rtx new_op0 = copy_rtx (operands[0]);
13543 operands[0] = new_op0;
13544 PUT_MODE (new_op0, VOIDmode);
13545 PUT_CODE (new_op0, REVERSE_CONDITION (GET_CODE (new_op0),
13546 GET_MODE (XEXP (new_op0, 0))));
13548 /* Make sure that (a) the CCmode we have for the flags is strong
13549 enough for the reversed compare or (b) we have a valid FP compare. */
13550 if (! ix86_comparison_operator (new_op0, VOIDmode))
13554 ;; Define combination compare-and-branch fp compare instructions to use
13555 ;; during early optimization. Splitting the operation apart early makes
13556 ;; for bad code when we want to reverse the operation.
13558 (define_insn "*fp_jcc_1"
13560 (if_then_else (match_operator 0 "comparison_operator"
13561 [(match_operand 1 "register_operand" "f")
13562 (match_operand 2 "register_operand" "f")])
13563 (label_ref (match_operand 3 "" ""))
13565 (clobber (reg:CCFP 18))
13566 (clobber (reg:CCFP 17))]
13567 "TARGET_CMOVE && TARGET_80387
13568 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13569 && FLOAT_MODE_P (GET_MODE (operands[1]))
13570 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13571 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13574 (define_insn "*fp_jcc_1_sse"
13576 (if_then_else (match_operator 0 "comparison_operator"
13577 [(match_operand 1 "register_operand" "f#x,x#f")
13578 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
13579 (label_ref (match_operand 3 "" ""))
13581 (clobber (reg:CCFP 18))
13582 (clobber (reg:CCFP 17))]
13584 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13585 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13586 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13589 (define_insn "*fp_jcc_1_sse_only"
13591 (if_then_else (match_operator 0 "comparison_operator"
13592 [(match_operand 1 "register_operand" "x")
13593 (match_operand 2 "nonimmediate_operand" "xm")])
13594 (label_ref (match_operand 3 "" ""))
13596 (clobber (reg:CCFP 18))
13597 (clobber (reg:CCFP 17))]
13598 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13599 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13600 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13603 (define_insn "*fp_jcc_2"
13605 (if_then_else (match_operator 0 "comparison_operator"
13606 [(match_operand 1 "register_operand" "f")
13607 (match_operand 2 "register_operand" "f")])
13609 (label_ref (match_operand 3 "" ""))))
13610 (clobber (reg:CCFP 18))
13611 (clobber (reg:CCFP 17))]
13612 "TARGET_CMOVE && TARGET_80387
13613 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13614 && FLOAT_MODE_P (GET_MODE (operands[1]))
13615 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13616 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13619 (define_insn "*fp_jcc_2_sse"
13621 (if_then_else (match_operator 0 "comparison_operator"
13622 [(match_operand 1 "register_operand" "f#x,x#f")
13623 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
13625 (label_ref (match_operand 3 "" ""))))
13626 (clobber (reg:CCFP 18))
13627 (clobber (reg:CCFP 17))]
13629 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13630 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13631 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13634 (define_insn "*fp_jcc_2_sse_only"
13636 (if_then_else (match_operator 0 "comparison_operator"
13637 [(match_operand 1 "register_operand" "x")
13638 (match_operand 2 "nonimmediate_operand" "xm")])
13640 (label_ref (match_operand 3 "" ""))))
13641 (clobber (reg:CCFP 18))
13642 (clobber (reg:CCFP 17))]
13643 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13644 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13645 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13648 (define_insn "*fp_jcc_3"
13650 (if_then_else (match_operator 0 "comparison_operator"
13651 [(match_operand 1 "register_operand" "f")
13652 (match_operand 2 "nonimmediate_operand" "fm")])
13653 (label_ref (match_operand 3 "" ""))
13655 (clobber (reg:CCFP 18))
13656 (clobber (reg:CCFP 17))
13657 (clobber (match_scratch:HI 4 "=a"))]
13659 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13660 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13661 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13662 && SELECT_CC_MODE (GET_CODE (operands[0]),
13663 operands[1], operands[2]) == CCFPmode
13664 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13667 (define_insn "*fp_jcc_4"
13669 (if_then_else (match_operator 0 "comparison_operator"
13670 [(match_operand 1 "register_operand" "f")
13671 (match_operand 2 "nonimmediate_operand" "fm")])
13673 (label_ref (match_operand 3 "" ""))))
13674 (clobber (reg:CCFP 18))
13675 (clobber (reg:CCFP 17))
13676 (clobber (match_scratch:HI 4 "=a"))]
13678 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13679 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13680 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13681 && SELECT_CC_MODE (GET_CODE (operands[0]),
13682 operands[1], operands[2]) == CCFPmode
13683 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13686 (define_insn "*fp_jcc_5"
13688 (if_then_else (match_operator 0 "comparison_operator"
13689 [(match_operand 1 "register_operand" "f")
13690 (match_operand 2 "register_operand" "f")])
13691 (label_ref (match_operand 3 "" ""))
13693 (clobber (reg:CCFP 18))
13694 (clobber (reg:CCFP 17))
13695 (clobber (match_scratch:HI 4 "=a"))]
13697 && FLOAT_MODE_P (GET_MODE (operands[1]))
13698 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13699 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13702 (define_insn "*fp_jcc_6"
13704 (if_then_else (match_operator 0 "comparison_operator"
13705 [(match_operand 1 "register_operand" "f")
13706 (match_operand 2 "register_operand" "f")])
13708 (label_ref (match_operand 3 "" ""))))
13709 (clobber (reg:CCFP 18))
13710 (clobber (reg:CCFP 17))
13711 (clobber (match_scratch:HI 4 "=a"))]
13713 && FLOAT_MODE_P (GET_MODE (operands[1]))
13714 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13715 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13720 (if_then_else (match_operator 0 "comparison_operator"
13721 [(match_operand 1 "register_operand" "")
13722 (match_operand 2 "nonimmediate_operand" "")])
13723 (match_operand 3 "" "")
13724 (match_operand 4 "" "")))
13725 (clobber (reg:CCFP 18))
13726 (clobber (reg:CCFP 17))]
13730 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13731 operands[3], operands[4], NULL_RTX);
13737 (if_then_else (match_operator 0 "comparison_operator"
13738 [(match_operand 1 "register_operand" "")
13739 (match_operand 2 "nonimmediate_operand" "")])
13740 (match_operand 3 "" "")
13741 (match_operand 4 "" "")))
13742 (clobber (reg:CCFP 18))
13743 (clobber (reg:CCFP 17))
13744 (clobber (match_scratch:HI 5 "=a"))]
13747 (if_then_else (match_dup 6)
13751 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13752 operands[3], operands[4], operands[5]);
13756 ;; Unconditional and other jump instructions
13758 (define_insn "jump"
13760 (label_ref (match_operand 0 "" "")))]
13763 [(set_attr "type" "ibr")
13764 (set (attr "length")
13765 (if_then_else (and (ge (minus (match_dup 0) (pc))
13767 (lt (minus (match_dup 0) (pc))
13771 (set_attr "modrm" "0")])
13773 (define_expand "indirect_jump"
13774 [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))]
13778 (define_insn "*indirect_jump"
13779 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
13782 [(set_attr "type" "ibr")
13783 (set_attr "length_immediate" "0")])
13785 (define_insn "*indirect_jump_rtx64"
13786 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))]
13789 [(set_attr "type" "ibr")
13790 (set_attr "length_immediate" "0")])
13792 (define_expand "tablejump"
13793 [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))
13794 (use (label_ref (match_operand 1 "" "")))])]
13797 /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
13798 relative. Convert the relative address to an absolute address. */
13802 enum rtx_code code;
13808 op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
13810 else if (TARGET_MACHO || HAVE_AS_GOTOFF_IN_DATA)
13814 op1 = pic_offset_table_rtx;
13819 op0 = pic_offset_table_rtx;
13823 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
13828 (define_insn "*tablejump_1"
13829 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13830 (use (label_ref (match_operand 1 "" "")))]
13833 [(set_attr "type" "ibr")
13834 (set_attr "length_immediate" "0")])
13836 (define_insn "*tablejump_1_rtx64"
13837 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))
13838 (use (label_ref (match_operand 1 "" "")))]
13841 [(set_attr "type" "ibr")
13842 (set_attr "length_immediate" "0")])
13844 ;; Loop instruction
13846 ;; This is all complicated by the fact that since this is a jump insn
13847 ;; we must handle our own reloads.
13849 (define_expand "doloop_end"
13850 [(use (match_operand 0 "" "")) ; loop pseudo
13851 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13852 (use (match_operand 2 "" "")) ; max iterations
13853 (use (match_operand 3 "" "")) ; loop level
13854 (use (match_operand 4 "" ""))] ; label
13855 "!TARGET_64BIT && TARGET_USE_LOOP"
13858 /* Only use cloop on innermost loops. */
13859 if (INTVAL (operands[3]) > 1)
13861 if (GET_MODE (operands[0]) != SImode)
13863 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
13868 (define_insn "doloop_end_internal"
13870 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
13872 (label_ref (match_operand 0 "" ""))
13874 (set (match_operand:SI 2 "register_operand" "=1,1,*m*r")
13875 (plus:SI (match_dup 1)
13877 (clobber (match_scratch:SI 3 "=X,X,r"))
13878 (clobber (reg:CC 17))]
13879 "!TARGET_64BIT && TARGET_USE_LOOP"
13881 if (which_alternative != 0)
13883 if (get_attr_length (insn) == 2)
13884 return "%+loop\t%l0";
13886 return "dec{l}\t%1\;%+jne\t%l0";
13888 [(set_attr "ppro_uops" "many")
13889 (set (attr "length")
13890 (if_then_else (and (eq_attr "alternative" "0")
13891 (and (ge (minus (match_dup 0) (pc))
13893 (lt (minus (match_dup 0) (pc))
13897 ;; We don't know the type before shorten branches. Optimistically expect
13898 ;; the loop instruction to match.
13899 (set (attr "type") (const_string "ibr"))])
13903 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13905 (match_operand 0 "" "")
13908 (plus:SI (match_dup 1)
13910 (clobber (match_scratch:SI 2 ""))
13911 (clobber (reg:CC 17))]
13912 "!TARGET_64BIT && TARGET_USE_LOOP
13913 && reload_completed
13914 && REGNO (operands[1]) != 2"
13915 [(parallel [(set (reg:CCZ 17)
13916 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
13918 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
13919 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13926 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13928 (match_operand 0 "" "")
13930 (set (match_operand:SI 2 "nonimmediate_operand" "")
13931 (plus:SI (match_dup 1)
13933 (clobber (match_scratch:SI 3 ""))
13934 (clobber (reg:CC 17))]
13935 "!TARGET_64BIT && TARGET_USE_LOOP
13936 && reload_completed
13937 && (! REG_P (operands[2])
13938 || ! rtx_equal_p (operands[1], operands[2]))"
13939 [(set (match_dup 3) (match_dup 1))
13940 (parallel [(set (reg:CCZ 17)
13941 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
13943 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
13944 (set (match_dup 2) (match_dup 3))
13945 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13950 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
13953 [(set (reg 17) (match_operand 0 "" ""))
13954 (set (match_operand:QI 1 "register_operand" "")
13955 (match_operator:QI 2 "ix86_comparison_operator"
13956 [(reg 17) (const_int 0)]))
13957 (set (match_operand 3 "q_regs_operand" "")
13958 (zero_extend (match_dup 1)))]
13959 "(peep2_reg_dead_p (3, operands[1])
13960 || operands_match_p (operands[1], operands[3]))
13961 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13962 [(set (match_dup 4) (match_dup 0))
13963 (set (strict_low_part (match_dup 5))
13966 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13967 operands[5] = gen_lowpart (QImode, operands[3]);
13968 ix86_expand_clear (operands[3]);
13971 ;; Similar, but match zero_extendhisi2_and, which adds a clobber.
13974 [(set (reg 17) (match_operand 0 "" ""))
13975 (set (match_operand:QI 1 "register_operand" "")
13976 (match_operator:QI 2 "ix86_comparison_operator"
13977 [(reg 17) (const_int 0)]))
13978 (parallel [(set (match_operand 3 "q_regs_operand" "")
13979 (zero_extend (match_dup 1)))
13980 (clobber (reg:CC 17))])]
13981 "(peep2_reg_dead_p (3, operands[1])
13982 || operands_match_p (operands[1], operands[3]))
13983 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13984 [(set (match_dup 4) (match_dup 0))
13985 (set (strict_low_part (match_dup 5))
13988 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13989 operands[5] = gen_lowpart (QImode, operands[3]);
13990 ix86_expand_clear (operands[3]);
13993 ;; Call instructions.
13995 ;; The predicates normally associated with named expanders are not properly
13996 ;; checked for calls. This is a bug in the generic code, but it isn't that
13997 ;; easy to fix. Ignore it for now and be prepared to fix things up.
13999 ;; Call subroutine returning no value.
14001 (define_expand "call_pop"
14002 [(parallel [(call (match_operand:QI 0 "" "")
14003 (match_operand:SI 1 "" ""))
14005 (plus:SI (reg:SI 7)
14006 (match_operand:SI 3 "" "")))])]
14009 ix86_expand_call (NULL, operands[0], operands[1], operands[2], operands[3], 0);
14013 (define_insn "*call_pop_0"
14014 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
14015 (match_operand:SI 1 "" ""))
14016 (set (reg:SI 7) (plus:SI (reg:SI 7)
14017 (match_operand:SI 2 "immediate_operand" "")))]
14020 if (SIBLING_CALL_P (insn))
14023 return "call\t%P0";
14025 [(set_attr "type" "call")])
14027 (define_insn "*call_pop_1"
14028 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
14029 (match_operand:SI 1 "" ""))
14030 (set (reg:SI 7) (plus:SI (reg:SI 7)
14031 (match_operand:SI 2 "immediate_operand" "i")))]
14034 if (constant_call_address_operand (operands[0], Pmode))
14036 if (SIBLING_CALL_P (insn))
14039 return "call\t%P0";
14041 if (SIBLING_CALL_P (insn))
14044 return "call\t%A0";
14046 [(set_attr "type" "call")])
14048 (define_expand "call"
14049 [(call (match_operand:QI 0 "" "")
14050 (match_operand 1 "" ""))
14051 (use (match_operand 2 "" ""))]
14054 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 0);
14058 (define_expand "sibcall"
14059 [(call (match_operand:QI 0 "" "")
14060 (match_operand 1 "" ""))
14061 (use (match_operand 2 "" ""))]
14064 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 1);
14068 (define_insn "*call_0"
14069 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
14070 (match_operand 1 "" ""))]
14073 if (SIBLING_CALL_P (insn))
14076 return "call\t%P0";
14078 [(set_attr "type" "call")])
14080 (define_insn "*call_1"
14081 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
14082 (match_operand 1 "" ""))]
14083 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
14085 if (constant_call_address_operand (operands[0], QImode))
14086 return "call\t%P0";
14087 return "call\t%A0";
14089 [(set_attr "type" "call")])
14091 (define_insn "*sibcall_1"
14092 [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,c,d,a"))
14093 (match_operand 1 "" ""))]
14094 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
14096 if (constant_call_address_operand (operands[0], QImode))
14100 [(set_attr "type" "call")])
14102 (define_insn "*call_1_rex64"
14103 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
14104 (match_operand 1 "" ""))]
14105 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
14107 if (constant_call_address_operand (operands[0], QImode))
14108 return "call\t%P0";
14109 return "call\t%A0";
14111 [(set_attr "type" "call")])
14113 (define_insn "*sibcall_1_rex64"
14114 [(call (mem:QI (match_operand:DI 0 "constant_call_address_operand" ""))
14115 (match_operand 1 "" ""))]
14116 "SIBLING_CALL_P (insn) && TARGET_64BIT"
14118 [(set_attr "type" "call")])
14120 (define_insn "*sibcall_1_rex64_v"
14121 [(call (mem:QI (reg:DI 40))
14122 (match_operand 0 "" ""))]
14123 "SIBLING_CALL_P (insn) && TARGET_64BIT"
14125 [(set_attr "type" "call")])
14128 ;; Call subroutine, returning value in operand 0
14130 (define_expand "call_value_pop"
14131 [(parallel [(set (match_operand 0 "" "")
14132 (call (match_operand:QI 1 "" "")
14133 (match_operand:SI 2 "" "")))
14135 (plus:SI (reg:SI 7)
14136 (match_operand:SI 4 "" "")))])]
14139 ix86_expand_call (operands[0], operands[1], operands[2],
14140 operands[3], operands[4], 0);
14144 (define_expand "call_value"
14145 [(set (match_operand 0 "" "")
14146 (call (match_operand:QI 1 "" "")
14147 (match_operand:SI 2 "" "")))
14148 (use (match_operand:SI 3 "" ""))]
14149 ;; Operand 2 not used on the i386.
14152 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 0);
14156 (define_expand "sibcall_value"
14157 [(set (match_operand 0 "" "")
14158 (call (match_operand:QI 1 "" "")
14159 (match_operand:SI 2 "" "")))
14160 (use (match_operand:SI 3 "" ""))]
14161 ;; Operand 2 not used on the i386.
14164 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 1);
14168 ;; Call subroutine returning any type.
14170 (define_expand "untyped_call"
14171 [(parallel [(call (match_operand 0 "" "")
14173 (match_operand 1 "" "")
14174 (match_operand 2 "" "")])]
14179 /* In order to give reg-stack an easier job in validating two
14180 coprocessor registers as containing a possible return value,
14181 simply pretend the untyped call returns a complex long double
14184 ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
14185 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
14186 operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1),
14189 for (i = 0; i < XVECLEN (operands[2], 0); i++)
14191 rtx set = XVECEXP (operands[2], 0, i);
14192 emit_move_insn (SET_DEST (set), SET_SRC (set));
14195 /* The optimizer does not know that the call sets the function value
14196 registers we stored in the result block. We avoid problems by
14197 claiming that all hard registers are used and clobbered at this
14199 emit_insn (gen_blockage (const0_rtx));
14204 ;; Prologue and epilogue instructions
14206 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
14207 ;; all of memory. This blocks insns from being moved across this point.
14209 (define_insn "blockage"
14210 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_BLOCKAGE)]
14213 [(set_attr "length" "0")])
14215 ;; Insn emitted into the body of a function to return from a function.
14216 ;; This is only done if the function's epilogue is known to be simple.
14217 ;; See comments for ix86_can_use_return_insn_p in i386.c.
14219 (define_expand "return"
14221 "ix86_can_use_return_insn_p ()"
14223 if (current_function_pops_args)
14225 rtx popc = GEN_INT (current_function_pops_args);
14226 emit_jump_insn (gen_return_pop_internal (popc));
14231 (define_insn "return_internal"
14235 [(set_attr "length" "1")
14236 (set_attr "length_immediate" "0")
14237 (set_attr "modrm" "0")])
14239 (define_insn "return_pop_internal"
14241 (use (match_operand:SI 0 "const_int_operand" ""))]
14244 [(set_attr "length" "3")
14245 (set_attr "length_immediate" "2")
14246 (set_attr "modrm" "0")])
14248 (define_insn "return_indirect_internal"
14250 (use (match_operand:SI 0 "register_operand" "r"))]
14253 [(set_attr "type" "ibr")
14254 (set_attr "length_immediate" "0")])
14260 [(set_attr "length" "1")
14261 (set_attr "length_immediate" "0")
14262 (set_attr "modrm" "0")
14263 (set_attr "ppro_uops" "one")])
14265 (define_expand "prologue"
14268 "ix86_expand_prologue (); DONE;")
14270 (define_insn "set_got"
14271 [(set (match_operand:SI 0 "register_operand" "=r")
14272 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
14273 (clobber (reg:CC 17))]
14275 { return output_set_got (operands[0]); }
14276 [(set_attr "type" "multi")
14277 (set_attr "length" "12")])
14279 (define_expand "epilogue"
14282 "ix86_expand_epilogue (1); DONE;")
14284 (define_expand "sibcall_epilogue"
14287 "ix86_expand_epilogue (0); DONE;")
14289 (define_expand "eh_return"
14290 [(use (match_operand 0 "register_operand" ""))]
14293 rtx tmp, sa = EH_RETURN_STACKADJ_RTX, ra = operands[0];
14295 /* Tricky bit: we write the address of the handler to which we will
14296 be returning into someone else's stack frame, one word below the
14297 stack address we wish to restore. */
14298 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
14299 tmp = plus_constant (tmp, -UNITS_PER_WORD);
14300 tmp = gen_rtx_MEM (Pmode, tmp);
14301 emit_move_insn (tmp, ra);
14303 if (Pmode == SImode)
14304 emit_insn (gen_eh_return_si (sa));
14306 emit_insn (gen_eh_return_di (sa));
14311 (define_insn_and_split "eh_return_si"
14312 [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")]
14313 UNSPECV_EH_RETURN)]
14318 "ix86_expand_epilogue (2); DONE;")
14320 (define_insn_and_split "eh_return_di"
14321 [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
14322 UNSPECV_EH_RETURN)]
14327 "ix86_expand_epilogue (2); DONE;")
14329 (define_insn "leave"
14330 [(set (reg:SI 7) (plus:SI (reg:SI 6) (const_int 4)))
14331 (set (reg:SI 6) (mem:SI (reg:SI 6)))
14332 (clobber (mem:BLK (scratch)))]
14335 [(set_attr "type" "leave")])
14337 (define_insn "leave_rex64"
14338 [(set (reg:DI 7) (plus:DI (reg:DI 6) (const_int 8)))
14339 (set (reg:DI 6) (mem:DI (reg:DI 6)))
14340 (clobber (mem:BLK (scratch)))]
14343 [(set_attr "type" "leave")])
14345 (define_expand "ffssi2"
14347 [(set (match_operand:SI 0 "register_operand" "")
14348 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))
14349 (clobber (match_scratch:SI 2 ""))
14350 (clobber (reg:CC 17))])]
14354 (define_insn_and_split "*ffs_cmove"
14355 [(set (match_operand:SI 0 "register_operand" "=r")
14356 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14357 (clobber (match_scratch:SI 2 "=&r"))
14358 (clobber (reg:CC 17))]
14361 "&& reload_completed"
14362 [(set (match_dup 2) (const_int -1))
14363 (parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
14364 (set (match_dup 0) (ctz:SI (match_dup 1)))])
14365 (set (match_dup 0) (if_then_else:SI
14366 (eq (reg:CCZ 17) (const_int 0))
14369 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14370 (clobber (reg:CC 17))])]
14373 (define_insn_and_split "*ffs_no_cmove"
14374 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
14375 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14376 (clobber (match_scratch:SI 2 "=&r"))
14377 (clobber (reg:CC 17))]
14381 [(parallel [(set (match_dup 2) (const_int 0))
14382 (clobber (reg:CC 17))])
14383 (parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
14384 (set (match_dup 0) (ctz:SI (match_dup 1)))])
14385 (set (strict_low_part (match_dup 3))
14386 (eq:QI (reg:CCZ 17) (const_int 0)))
14387 (parallel [(set (match_dup 2) (neg:SI (match_dup 2)))
14388 (clobber (reg:CC 17))])
14389 (parallel [(set (match_dup 0) (ior:SI (match_dup 0) (match_dup 2)))
14390 (clobber (reg:CC 17))])
14391 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14392 (clobber (reg:CC 17))])]
14394 operands[3] = gen_lowpart (QImode, operands[2]);
14397 (define_insn "*ffssi_1"
14399 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
14401 (set (match_operand:SI 0 "register_operand" "=r")
14402 (ctz:SI (match_dup 1)))]
14404 "bsf{l}\t{%1, %0|%0, %1}"
14405 [(set_attr "prefix_0f" "1")
14406 (set_attr "ppro_uops" "few")])
14408 (define_insn "ctzsi2"
14409 [(set (match_operand:SI 0 "register_operand" "=r")
14410 (ctz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14411 (clobber (reg:CC 17))]
14413 "bsf{l}\t{%1, %0|%0, %1}"
14414 [(set_attr "prefix_0f" "1")
14415 (set_attr "ppro_uops" "few")])
14417 (define_expand "clzsi2"
14419 [(set (match_operand:SI 0 "register_operand" "")
14420 (minus:SI (const_int 31)
14421 (clz:SI (match_operand:SI 1 "nonimmediate_operand" ""))))
14422 (clobber (reg:CC 17))])
14424 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 31)))
14425 (clobber (reg:CC 17))])]
14429 (define_insn "*bsr"
14430 [(set (match_operand:SI 0 "register_operand" "=r")
14431 (minus:SI (const_int 31)
14432 (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
14433 (clobber (reg:CC 17))]
14435 "bsr{l}\t{%1, %0|%0, %1}"
14436 [(set_attr "prefix_0f" "1")
14437 (set_attr "ppro_uops" "few")])
14439 ;; Thread-local storage patterns for ELF.
14441 ;; Note that these code sequences must appear exactly as shown
14442 ;; in order to allow linker relaxation.
14444 (define_insn "*tls_global_dynamic_32_gnu"
14445 [(set (match_operand:SI 0 "register_operand" "=a")
14446 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14447 (match_operand:SI 2 "tls_symbolic_operand" "")
14448 (match_operand:SI 3 "call_insn_operand" "")]
14450 (clobber (match_scratch:SI 4 "=d"))
14451 (clobber (match_scratch:SI 5 "=c"))
14452 (clobber (reg:CC 17))]
14453 "!TARGET_64BIT && TARGET_GNU_TLS"
14454 "lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3"
14455 [(set_attr "type" "multi")
14456 (set_attr "length" "12")])
14458 (define_insn "*tls_global_dynamic_32_sun"
14459 [(set (match_operand:SI 0 "register_operand" "=a")
14460 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14461 (match_operand:SI 2 "tls_symbolic_operand" "")
14462 (match_operand:SI 3 "call_insn_operand" "")]
14464 (clobber (match_scratch:SI 4 "=d"))
14465 (clobber (match_scratch:SI 5 "=c"))
14466 (clobber (reg:CC 17))]
14467 "!TARGET_64BIT && TARGET_SUN_TLS"
14468 "lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]}
14469 push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop"
14470 [(set_attr "type" "multi")
14471 (set_attr "length" "14")])
14473 (define_expand "tls_global_dynamic_32"
14474 [(parallel [(set (match_operand:SI 0 "register_operand" "")
14477 (match_operand:SI 1 "tls_symbolic_operand" "")
14480 (clobber (match_scratch:SI 4 ""))
14481 (clobber (match_scratch:SI 5 ""))
14482 (clobber (reg:CC 17))])]
14486 operands[2] = pic_offset_table_rtx;
14489 operands[2] = gen_reg_rtx (Pmode);
14490 emit_insn (gen_set_got (operands[2]));
14492 operands[3] = ix86_tls_get_addr ();
14495 (define_insn "*tls_global_dynamic_64"
14496 [(set (match_operand:DI 0 "register_operand" "=a")
14497 (call (mem:QI (match_operand:DI 2 "call_insn_operand" ""))
14498 (match_operand:DI 3 "" "")))
14499 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
14502 ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|%%rdi, %a1@TLSGD[%%rip]}\;.word\t0x6666\;rex64\;call\t%P2"
14503 [(set_attr "type" "multi")
14504 (set_attr "length" "16")])
14506 (define_expand "tls_global_dynamic_64"
14507 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14508 (call (mem:QI (match_dup 2)) (const_int 0)))
14509 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
14513 operands[2] = ix86_tls_get_addr ();
14516 (define_insn "*tls_local_dynamic_base_32_gnu"
14517 [(set (match_operand:SI 0 "register_operand" "=a")
14518 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14519 (match_operand:SI 2 "call_insn_operand" "")]
14520 UNSPEC_TLS_LD_BASE))
14521 (clobber (match_scratch:SI 3 "=d"))
14522 (clobber (match_scratch:SI 4 "=c"))
14523 (clobber (reg:CC 17))]
14524 "!TARGET_64BIT && TARGET_GNU_TLS"
14525 "lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2"
14526 [(set_attr "type" "multi")
14527 (set_attr "length" "11")])
14529 (define_insn "*tls_local_dynamic_base_32_sun"
14530 [(set (match_operand:SI 0 "register_operand" "=a")
14531 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14532 (match_operand:SI 2 "call_insn_operand" "")]
14533 UNSPEC_TLS_LD_BASE))
14534 (clobber (match_scratch:SI 3 "=d"))
14535 (clobber (match_scratch:SI 4 "=c"))
14536 (clobber (reg:CC 17))]
14537 "!TARGET_64BIT && TARGET_SUN_TLS"
14538 "lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]}
14539 push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3"
14540 [(set_attr "type" "multi")
14541 (set_attr "length" "13")])
14543 (define_expand "tls_local_dynamic_base_32"
14544 [(parallel [(set (match_operand:SI 0 "register_operand" "")
14545 (unspec:SI [(match_dup 1) (match_dup 2)]
14546 UNSPEC_TLS_LD_BASE))
14547 (clobber (match_scratch:SI 3 ""))
14548 (clobber (match_scratch:SI 4 ""))
14549 (clobber (reg:CC 17))])]
14553 operands[1] = pic_offset_table_rtx;
14556 operands[1] = gen_reg_rtx (Pmode);
14557 emit_insn (gen_set_got (operands[1]));
14559 operands[2] = ix86_tls_get_addr ();
14562 (define_insn "*tls_local_dynamic_base_64"
14563 [(set (match_operand:DI 0 "register_operand" "=a")
14564 (call (mem:QI (match_operand:DI 1 "call_insn_operand" ""))
14565 (match_operand:DI 2 "" "")))
14566 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)]
14568 "lea{q}\t{%&@TLSLD(%%rip), %%rdi|%%rdi, %&@TLSLD[%%rip]}\;call\t%P1"
14569 [(set_attr "type" "multi")
14570 (set_attr "length" "12")])
14572 (define_expand "tls_local_dynamic_base_64"
14573 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14574 (call (mem:QI (match_dup 1)) (const_int 0)))
14575 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)])]
14578 operands[1] = ix86_tls_get_addr ();
14581 ;; Local dynamic of a single variable is a lose. Show combine how
14582 ;; to convert that back to global dynamic.
14584 (define_insn_and_split "*tls_local_dynamic_32_once"
14585 [(set (match_operand:SI 0 "register_operand" "=a")
14586 (plus:SI (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14587 (match_operand:SI 2 "call_insn_operand" "")]
14588 UNSPEC_TLS_LD_BASE)
14589 (const:SI (unspec:SI
14590 [(match_operand:SI 3 "tls_symbolic_operand" "")]
14592 (clobber (match_scratch:SI 4 "=d"))
14593 (clobber (match_scratch:SI 5 "=c"))
14594 (clobber (reg:CC 17))]
14598 [(parallel [(set (match_dup 0)
14599 (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2)]
14601 (clobber (match_dup 4))
14602 (clobber (match_dup 5))
14603 (clobber (reg:CC 17))])]
14606 ;; These patterns match the binary 387 instructions for addM3, subM3,
14607 ;; mulM3 and divM3. There are three patterns for each of DFmode and
14608 ;; SFmode. The first is the normal insn, the second the same insn but
14609 ;; with one operand a conversion, and the third the same insn but with
14610 ;; the other operand a conversion. The conversion may be SFmode or
14611 ;; SImode if the target mode DFmode, but only SImode if the target mode
14614 ;; Gcc is slightly more smart about handling normal two address instructions
14615 ;; so use special patterns for add and mull.
14616 (define_insn "*fop_sf_comm_nosse"
14617 [(set (match_operand:SF 0 "register_operand" "=f")
14618 (match_operator:SF 3 "binary_fp_operator"
14619 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14620 (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
14621 "TARGET_80387 && !TARGET_SSE_MATH
14622 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14623 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14624 "* return output_387_binary_op (insn, operands);"
14625 [(set (attr "type")
14626 (if_then_else (match_operand:SF 3 "mult_operator" "")
14627 (const_string "fmul")
14628 (const_string "fop")))
14629 (set_attr "mode" "SF")])
14631 (define_insn "*fop_sf_comm"
14632 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14633 (match_operator:SF 3 "binary_fp_operator"
14634 [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
14635 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
14636 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14637 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14638 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14639 "* return output_387_binary_op (insn, operands);"
14640 [(set (attr "type")
14641 (if_then_else (eq_attr "alternative" "1")
14642 (if_then_else (match_operand:SF 3 "mult_operator" "")
14643 (const_string "ssemul")
14644 (const_string "sseadd"))
14645 (if_then_else (match_operand:SF 3 "mult_operator" "")
14646 (const_string "fmul")
14647 (const_string "fop"))))
14648 (set_attr "mode" "SF")])
14650 (define_insn "*fop_sf_comm_sse"
14651 [(set (match_operand:SF 0 "register_operand" "=x")
14652 (match_operator:SF 3 "binary_fp_operator"
14653 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14654 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14655 "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14656 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14657 "* return output_387_binary_op (insn, operands);"
14658 [(set (attr "type")
14659 (if_then_else (match_operand:SF 3 "mult_operator" "")
14660 (const_string "ssemul")
14661 (const_string "sseadd")))
14662 (set_attr "mode" "SF")])
14664 (define_insn "*fop_df_comm_nosse"
14665 [(set (match_operand:DF 0 "register_operand" "=f")
14666 (match_operator:DF 3 "binary_fp_operator"
14667 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14668 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
14669 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14670 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14671 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14672 "* return output_387_binary_op (insn, operands);"
14673 [(set (attr "type")
14674 (if_then_else (match_operand:SF 3 "mult_operator" "")
14675 (const_string "fmul")
14676 (const_string "fop")))
14677 (set_attr "mode" "DF")])
14679 (define_insn "*fop_df_comm"
14680 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14681 (match_operator:DF 3 "binary_fp_operator"
14682 [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
14683 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
14684 "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
14685 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14686 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14687 "* return output_387_binary_op (insn, operands);"
14688 [(set (attr "type")
14689 (if_then_else (eq_attr "alternative" "1")
14690 (if_then_else (match_operand:SF 3 "mult_operator" "")
14691 (const_string "ssemul")
14692 (const_string "sseadd"))
14693 (if_then_else (match_operand:SF 3 "mult_operator" "")
14694 (const_string "fmul")
14695 (const_string "fop"))))
14696 (set_attr "mode" "DF")])
14698 (define_insn "*fop_df_comm_sse"
14699 [(set (match_operand:DF 0 "register_operand" "=Y")
14700 (match_operator:DF 3 "binary_fp_operator"
14701 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14702 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14703 "TARGET_SSE2 && TARGET_SSE_MATH
14704 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14705 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14706 "* return output_387_binary_op (insn, operands);"
14707 [(set (attr "type")
14708 (if_then_else (match_operand:SF 3 "mult_operator" "")
14709 (const_string "ssemul")
14710 (const_string "sseadd")))
14711 (set_attr "mode" "DF")])
14713 (define_insn "*fop_xf_comm"
14714 [(set (match_operand:XF 0 "register_operand" "=f")
14715 (match_operator:XF 3 "binary_fp_operator"
14716 [(match_operand:XF 1 "register_operand" "%0")
14717 (match_operand:XF 2 "register_operand" "f")]))]
14718 "!TARGET_64BIT && TARGET_80387
14719 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
14720 "* return output_387_binary_op (insn, operands);"
14721 [(set (attr "type")
14722 (if_then_else (match_operand:XF 3 "mult_operator" "")
14723 (const_string "fmul")
14724 (const_string "fop")))
14725 (set_attr "mode" "XF")])
14727 (define_insn "*fop_tf_comm"
14728 [(set (match_operand:TF 0 "register_operand" "=f")
14729 (match_operator:TF 3 "binary_fp_operator"
14730 [(match_operand:TF 1 "register_operand" "%0")
14731 (match_operand:TF 2 "register_operand" "f")]))]
14732 "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
14733 "* return output_387_binary_op (insn, operands);"
14734 [(set (attr "type")
14735 (if_then_else (match_operand:TF 3 "mult_operator" "")
14736 (const_string "fmul")
14737 (const_string "fop")))
14738 (set_attr "mode" "XF")])
14740 (define_insn "*fop_sf_1_nosse"
14741 [(set (match_operand:SF 0 "register_operand" "=f,f")
14742 (match_operator:SF 3 "binary_fp_operator"
14743 [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
14744 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
14745 "TARGET_80387 && !TARGET_SSE_MATH
14746 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14747 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14748 "* return output_387_binary_op (insn, operands);"
14749 [(set (attr "type")
14750 (cond [(match_operand:SF 3 "mult_operator" "")
14751 (const_string "fmul")
14752 (match_operand:SF 3 "div_operator" "")
14753 (const_string "fdiv")
14755 (const_string "fop")))
14756 (set_attr "mode" "SF")])
14758 (define_insn "*fop_sf_1"
14759 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
14760 (match_operator:SF 3 "binary_fp_operator"
14761 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
14762 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
14763 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14764 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14765 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14766 "* return output_387_binary_op (insn, operands);"
14767 [(set (attr "type")
14768 (cond [(and (eq_attr "alternative" "2")
14769 (match_operand:SF 3 "mult_operator" ""))
14770 (const_string "ssemul")
14771 (and (eq_attr "alternative" "2")
14772 (match_operand:SF 3 "div_operator" ""))
14773 (const_string "ssediv")
14774 (eq_attr "alternative" "2")
14775 (const_string "sseadd")
14776 (match_operand:SF 3 "mult_operator" "")
14777 (const_string "fmul")
14778 (match_operand:SF 3 "div_operator" "")
14779 (const_string "fdiv")
14781 (const_string "fop")))
14782 (set_attr "mode" "SF")])
14784 (define_insn "*fop_sf_1_sse"
14785 [(set (match_operand:SF 0 "register_operand" "=x")
14786 (match_operator:SF 3 "binary_fp_operator"
14787 [(match_operand:SF 1 "register_operand" "0")
14788 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14790 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14791 "* return output_387_binary_op (insn, operands);"
14792 [(set (attr "type")
14793 (cond [(match_operand:SF 3 "mult_operator" "")
14794 (const_string "ssemul")
14795 (match_operand:SF 3 "div_operator" "")
14796 (const_string "ssediv")
14798 (const_string "sseadd")))
14799 (set_attr "mode" "SF")])
14801 ;; ??? Add SSE splitters for these!
14802 (define_insn "*fop_sf_2"
14803 [(set (match_operand:SF 0 "register_operand" "=f,f")
14804 (match_operator:SF 3 "binary_fp_operator"
14805 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14806 (match_operand:SF 2 "register_operand" "0,0")]))]
14807 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14808 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14809 [(set (attr "type")
14810 (cond [(match_operand:SF 3 "mult_operator" "")
14811 (const_string "fmul")
14812 (match_operand:SF 3 "div_operator" "")
14813 (const_string "fdiv")
14815 (const_string "fop")))
14816 (set_attr "fp_int_src" "true")
14817 (set_attr "ppro_uops" "many")
14818 (set_attr "mode" "SI")])
14820 (define_insn "*fop_sf_3"
14821 [(set (match_operand:SF 0 "register_operand" "=f,f")
14822 (match_operator:SF 3 "binary_fp_operator"
14823 [(match_operand:SF 1 "register_operand" "0,0")
14824 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14825 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14826 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14827 [(set (attr "type")
14828 (cond [(match_operand:SF 3 "mult_operator" "")
14829 (const_string "fmul")
14830 (match_operand:SF 3 "div_operator" "")
14831 (const_string "fdiv")
14833 (const_string "fop")))
14834 (set_attr "fp_int_src" "true")
14835 (set_attr "ppro_uops" "many")
14836 (set_attr "mode" "SI")])
14838 (define_insn "*fop_df_1_nosse"
14839 [(set (match_operand:DF 0 "register_operand" "=f,f")
14840 (match_operator:DF 3 "binary_fp_operator"
14841 [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
14842 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
14843 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14844 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14845 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14846 "* return output_387_binary_op (insn, operands);"
14847 [(set (attr "type")
14848 (cond [(match_operand:DF 3 "mult_operator" "")
14849 (const_string "fmul")
14850 (match_operand:DF 3 "div_operator" "")
14851 (const_string "fdiv")
14853 (const_string "fop")))
14854 (set_attr "mode" "DF")])
14857 (define_insn "*fop_df_1"
14858 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
14859 (match_operator:DF 3 "binary_fp_operator"
14860 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
14861 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
14862 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14863 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14864 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14865 "* return output_387_binary_op (insn, operands);"
14866 [(set (attr "type")
14867 (cond [(and (eq_attr "alternative" "2")
14868 (match_operand:SF 3 "mult_operator" ""))
14869 (const_string "ssemul")
14870 (and (eq_attr "alternative" "2")
14871 (match_operand:SF 3 "div_operator" ""))
14872 (const_string "ssediv")
14873 (eq_attr "alternative" "2")
14874 (const_string "sseadd")
14875 (match_operand:DF 3 "mult_operator" "")
14876 (const_string "fmul")
14877 (match_operand:DF 3 "div_operator" "")
14878 (const_string "fdiv")
14880 (const_string "fop")))
14881 (set_attr "mode" "DF")])
14883 (define_insn "*fop_df_1_sse"
14884 [(set (match_operand:DF 0 "register_operand" "=Y")
14885 (match_operator:DF 3 "binary_fp_operator"
14886 [(match_operand:DF 1 "register_operand" "0")
14887 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14888 "TARGET_SSE2 && TARGET_SSE_MATH
14889 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14890 "* return output_387_binary_op (insn, operands);"
14891 [(set_attr "mode" "DF")
14893 (cond [(match_operand:SF 3 "mult_operator" "")
14894 (const_string "ssemul")
14895 (match_operand:SF 3 "div_operator" "")
14896 (const_string "ssediv")
14898 (const_string "sseadd")))])
14900 ;; ??? Add SSE splitters for these!
14901 (define_insn "*fop_df_2"
14902 [(set (match_operand:DF 0 "register_operand" "=f,f")
14903 (match_operator:DF 3 "binary_fp_operator"
14904 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14905 (match_operand:DF 2 "register_operand" "0,0")]))]
14906 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14907 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14908 [(set (attr "type")
14909 (cond [(match_operand:DF 3 "mult_operator" "")
14910 (const_string "fmul")
14911 (match_operand:DF 3 "div_operator" "")
14912 (const_string "fdiv")
14914 (const_string "fop")))
14915 (set_attr "fp_int_src" "true")
14916 (set_attr "ppro_uops" "many")
14917 (set_attr "mode" "SI")])
14919 (define_insn "*fop_df_3"
14920 [(set (match_operand:DF 0 "register_operand" "=f,f")
14921 (match_operator:DF 3 "binary_fp_operator"
14922 [(match_operand:DF 1 "register_operand" "0,0")
14923 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14924 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14925 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14926 [(set (attr "type")
14927 (cond [(match_operand:DF 3 "mult_operator" "")
14928 (const_string "fmul")
14929 (match_operand:DF 3 "div_operator" "")
14930 (const_string "fdiv")
14932 (const_string "fop")))
14933 (set_attr "fp_int_src" "true")
14934 (set_attr "ppro_uops" "many")
14935 (set_attr "mode" "SI")])
14937 (define_insn "*fop_df_4"
14938 [(set (match_operand:DF 0 "register_operand" "=f,f")
14939 (match_operator:DF 3 "binary_fp_operator"
14940 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14941 (match_operand:DF 2 "register_operand" "0,f")]))]
14942 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14943 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14944 "* return output_387_binary_op (insn, operands);"
14945 [(set (attr "type")
14946 (cond [(match_operand:DF 3 "mult_operator" "")
14947 (const_string "fmul")
14948 (match_operand:DF 3 "div_operator" "")
14949 (const_string "fdiv")
14951 (const_string "fop")))
14952 (set_attr "mode" "SF")])
14954 (define_insn "*fop_df_5"
14955 [(set (match_operand:DF 0 "register_operand" "=f,f")
14956 (match_operator:DF 3 "binary_fp_operator"
14957 [(match_operand:DF 1 "register_operand" "0,f")
14959 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14960 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14961 "* return output_387_binary_op (insn, operands);"
14962 [(set (attr "type")
14963 (cond [(match_operand:DF 3 "mult_operator" "")
14964 (const_string "fmul")
14965 (match_operand:DF 3 "div_operator" "")
14966 (const_string "fdiv")
14968 (const_string "fop")))
14969 (set_attr "mode" "SF")])
14971 (define_insn "*fop_df_6"
14972 [(set (match_operand:DF 0 "register_operand" "=f,f")
14973 (match_operator:DF 3 "binary_fp_operator"
14975 (match_operand:SF 1 "register_operand" "0,f"))
14977 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14978 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14979 "* return output_387_binary_op (insn, operands);"
14980 [(set (attr "type")
14981 (cond [(match_operand:DF 3 "mult_operator" "")
14982 (const_string "fmul")
14983 (match_operand:DF 3 "div_operator" "")
14984 (const_string "fdiv")
14986 (const_string "fop")))
14987 (set_attr "mode" "SF")])
14989 (define_insn "*fop_xf_1"
14990 [(set (match_operand:XF 0 "register_operand" "=f,f")
14991 (match_operator:XF 3 "binary_fp_operator"
14992 [(match_operand:XF 1 "register_operand" "0,f")
14993 (match_operand:XF 2 "register_operand" "f,0")]))]
14994 "!TARGET_64BIT && TARGET_80387
14995 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14996 "* return output_387_binary_op (insn, operands);"
14997 [(set (attr "type")
14998 (cond [(match_operand:XF 3 "mult_operator" "")
14999 (const_string "fmul")
15000 (match_operand:XF 3 "div_operator" "")
15001 (const_string "fdiv")
15003 (const_string "fop")))
15004 (set_attr "mode" "XF")])
15006 (define_insn "*fop_tf_1"
15007 [(set (match_operand:TF 0 "register_operand" "=f,f")
15008 (match_operator:TF 3 "binary_fp_operator"
15009 [(match_operand:TF 1 "register_operand" "0,f")
15010 (match_operand:TF 2 "register_operand" "f,0")]))]
15012 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
15013 "* return output_387_binary_op (insn, operands);"
15014 [(set (attr "type")
15015 (cond [(match_operand:TF 3 "mult_operator" "")
15016 (const_string "fmul")
15017 (match_operand:TF 3 "div_operator" "")
15018 (const_string "fdiv")
15020 (const_string "fop")))
15021 (set_attr "mode" "XF")])
15023 (define_insn "*fop_xf_2"
15024 [(set (match_operand:XF 0 "register_operand" "=f,f")
15025 (match_operator:XF 3 "binary_fp_operator"
15026 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
15027 (match_operand:XF 2 "register_operand" "0,0")]))]
15028 "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP"
15029 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
15030 [(set (attr "type")
15031 (cond [(match_operand:XF 3 "mult_operator" "")
15032 (const_string "fmul")
15033 (match_operand:XF 3 "div_operator" "")
15034 (const_string "fdiv")
15036 (const_string "fop")))
15037 (set_attr "fp_int_src" "true")
15038 (set_attr "mode" "SI")
15039 (set_attr "ppro_uops" "many")])
15041 (define_insn "*fop_tf_2"
15042 [(set (match_operand:TF 0 "register_operand" "=f,f")
15043 (match_operator:TF 3 "binary_fp_operator"
15044 [(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
15045 (match_operand:TF 2 "register_operand" "0,0")]))]
15046 "TARGET_80387 && TARGET_USE_FIOP"
15047 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
15048 [(set (attr "type")
15049 (cond [(match_operand:TF 3 "mult_operator" "")
15050 (const_string "fmul")
15051 (match_operand:TF 3 "div_operator" "")
15052 (const_string "fdiv")
15054 (const_string "fop")))
15055 (set_attr "fp_int_src" "true")
15056 (set_attr "mode" "SI")
15057 (set_attr "ppro_uops" "many")])
15059 (define_insn "*fop_xf_3"
15060 [(set (match_operand:XF 0 "register_operand" "=f,f")
15061 (match_operator:XF 3 "binary_fp_operator"
15062 [(match_operand:XF 1 "register_operand" "0,0")
15063 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
15064 "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP"
15065 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
15066 [(set (attr "type")
15067 (cond [(match_operand:XF 3 "mult_operator" "")
15068 (const_string "fmul")
15069 (match_operand:XF 3 "div_operator" "")
15070 (const_string "fdiv")
15072 (const_string "fop")))
15073 (set_attr "fp_int_src" "true")
15074 (set_attr "mode" "SI")
15075 (set_attr "ppro_uops" "many")])
15077 (define_insn "*fop_tf_3"
15078 [(set (match_operand:TF 0 "register_operand" "=f,f")
15079 (match_operator:TF 3 "binary_fp_operator"
15080 [(match_operand:TF 1 "register_operand" "0,0")
15081 (float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
15082 "TARGET_80387 && TARGET_USE_FIOP"
15083 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
15084 [(set (attr "type")
15085 (cond [(match_operand:TF 3 "mult_operator" "")
15086 (const_string "fmul")
15087 (match_operand:TF 3 "div_operator" "")
15088 (const_string "fdiv")
15090 (const_string "fop")))
15091 (set_attr "fp_int_src" "true")
15092 (set_attr "mode" "SI")
15093 (set_attr "ppro_uops" "many")])
15095 (define_insn "*fop_xf_4"
15096 [(set (match_operand:XF 0 "register_operand" "=f,f")
15097 (match_operator:XF 3 "binary_fp_operator"
15098 [(float_extend:XF (match_operand 1 "nonimmediate_operand" "fm,0"))
15099 (match_operand:XF 2 "register_operand" "0,f")]))]
15100 "!TARGET_64BIT && TARGET_80387"
15101 "* return output_387_binary_op (insn, operands);"
15102 [(set (attr "type")
15103 (cond [(match_operand:XF 3 "mult_operator" "")
15104 (const_string "fmul")
15105 (match_operand:XF 3 "div_operator" "")
15106 (const_string "fdiv")
15108 (const_string "fop")))
15109 (set_attr "mode" "SF")])
15111 (define_insn "*fop_tf_4"
15112 [(set (match_operand:TF 0 "register_operand" "=f,f")
15113 (match_operator:TF 3 "binary_fp_operator"
15114 [(float_extend:TF (match_operand 1 "nonimmediate_operand" "fm,0"))
15115 (match_operand:TF 2 "register_operand" "0,f")]))]
15117 "* return output_387_binary_op (insn, operands);"
15118 [(set (attr "type")
15119 (cond [(match_operand:TF 3 "mult_operator" "")
15120 (const_string "fmul")
15121 (match_operand:TF 3 "div_operator" "")
15122 (const_string "fdiv")
15124 (const_string "fop")))
15125 (set_attr "mode" "SF")])
15127 (define_insn "*fop_xf_5"
15128 [(set (match_operand:XF 0 "register_operand" "=f,f")
15129 (match_operator:XF 3 "binary_fp_operator"
15130 [(match_operand:XF 1 "register_operand" "0,f")
15132 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
15133 "!TARGET_64BIT && TARGET_80387"
15134 "* return output_387_binary_op (insn, operands);"
15135 [(set (attr "type")
15136 (cond [(match_operand:XF 3 "mult_operator" "")
15137 (const_string "fmul")
15138 (match_operand:XF 3 "div_operator" "")
15139 (const_string "fdiv")
15141 (const_string "fop")))
15142 (set_attr "mode" "SF")])
15144 (define_insn "*fop_tf_5"
15145 [(set (match_operand:TF 0 "register_operand" "=f,f")
15146 (match_operator:TF 3 "binary_fp_operator"
15147 [(match_operand:TF 1 "register_operand" "0,f")
15149 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
15151 "* return output_387_binary_op (insn, operands);"
15152 [(set (attr "type")
15153 (cond [(match_operand:TF 3 "mult_operator" "")
15154 (const_string "fmul")
15155 (match_operand:TF 3 "div_operator" "")
15156 (const_string "fdiv")
15158 (const_string "fop")))
15159 (set_attr "mode" "SF")])
15161 (define_insn "*fop_xf_6"
15162 [(set (match_operand:XF 0 "register_operand" "=f,f")
15163 (match_operator:XF 3 "binary_fp_operator"
15165 (match_operand 1 "register_operand" "0,f"))
15167 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
15168 "!TARGET_64BIT && TARGET_80387"
15169 "* return output_387_binary_op (insn, operands);"
15170 [(set (attr "type")
15171 (cond [(match_operand:XF 3 "mult_operator" "")
15172 (const_string "fmul")
15173 (match_operand:XF 3 "div_operator" "")
15174 (const_string "fdiv")
15176 (const_string "fop")))
15177 (set_attr "mode" "SF")])
15179 (define_insn "*fop_tf_6"
15180 [(set (match_operand:TF 0 "register_operand" "=f,f")
15181 (match_operator:TF 3 "binary_fp_operator"
15183 (match_operand 1 "register_operand" "0,f"))
15185 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
15187 "* return output_387_binary_op (insn, operands);"
15188 [(set (attr "type")
15189 (cond [(match_operand:TF 3 "mult_operator" "")
15190 (const_string "fmul")
15191 (match_operand:TF 3 "div_operator" "")
15192 (const_string "fdiv")
15194 (const_string "fop")))
15195 (set_attr "mode" "SF")])
15198 [(set (match_operand 0 "register_operand" "")
15199 (match_operator 3 "binary_fp_operator"
15200 [(float (match_operand:SI 1 "register_operand" ""))
15201 (match_operand 2 "register_operand" "")]))]
15202 "TARGET_80387 && reload_completed
15203 && FLOAT_MODE_P (GET_MODE (operands[0]))"
15206 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
15207 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
15208 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15209 gen_rtx_fmt_ee (GET_CODE (operands[3]),
15210 GET_MODE (operands[3]),
15213 ix86_free_from_memory (GET_MODE (operands[1]));
15218 [(set (match_operand 0 "register_operand" "")
15219 (match_operator 3 "binary_fp_operator"
15220 [(match_operand 1 "register_operand" "")
15221 (float (match_operand:SI 2 "register_operand" ""))]))]
15222 "TARGET_80387 && reload_completed
15223 && FLOAT_MODE_P (GET_MODE (operands[0]))"
15226 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
15227 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
15228 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15229 gen_rtx_fmt_ee (GET_CODE (operands[3]),
15230 GET_MODE (operands[3]),
15233 ix86_free_from_memory (GET_MODE (operands[2]));
15237 ;; FPU special functions.
15239 (define_expand "sqrtsf2"
15240 [(set (match_operand:SF 0 "register_operand" "")
15241 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
15242 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE_MATH"
15244 if (!TARGET_SSE_MATH)
15245 operands[1] = force_reg (SFmode, operands[1]);
15248 (define_insn "sqrtsf2_1"
15249 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
15250 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
15251 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15252 && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
15255 sqrtss\t{%1, %0|%0, %1}"
15256 [(set_attr "type" "fpspc,sse")
15257 (set_attr "mode" "SF,SF")
15258 (set_attr "athlon_decode" "direct,*")])
15260 (define_insn "sqrtsf2_1_sse_only"
15261 [(set (match_operand:SF 0 "register_operand" "=x")
15262 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
15263 "TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
15264 "sqrtss\t{%1, %0|%0, %1}"
15265 [(set_attr "type" "sse")
15266 (set_attr "mode" "SF")
15267 (set_attr "athlon_decode" "*")])
15269 (define_insn "sqrtsf2_i387"
15270 [(set (match_operand:SF 0 "register_operand" "=f")
15271 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
15272 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15273 && !TARGET_SSE_MATH"
15275 [(set_attr "type" "fpspc")
15276 (set_attr "mode" "SF")
15277 (set_attr "athlon_decode" "direct")])
15279 (define_expand "sqrtdf2"
15280 [(set (match_operand:DF 0 "register_operand" "")
15281 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
15282 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387)
15283 || (TARGET_SSE2 && TARGET_SSE_MATH)"
15285 if (!TARGET_SSE2 || !TARGET_SSE_MATH)
15286 operands[1] = force_reg (DFmode, operands[1]);
15289 (define_insn "sqrtdf2_1"
15290 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
15291 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
15292 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15293 && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
15296 sqrtsd\t{%1, %0|%0, %1}"
15297 [(set_attr "type" "fpspc,sse")
15298 (set_attr "mode" "DF,DF")
15299 (set_attr "athlon_decode" "direct,*")])
15301 (define_insn "sqrtdf2_1_sse_only"
15302 [(set (match_operand:DF 0 "register_operand" "=Y")
15303 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
15304 "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
15305 "sqrtsd\t{%1, %0|%0, %1}"
15306 [(set_attr "type" "sse")
15307 (set_attr "mode" "DF")
15308 (set_attr "athlon_decode" "*")])
15310 (define_insn "sqrtdf2_i387"
15311 [(set (match_operand:DF 0 "register_operand" "=f")
15312 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
15313 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15314 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
15316 [(set_attr "type" "fpspc")
15317 (set_attr "mode" "DF")
15318 (set_attr "athlon_decode" "direct")])
15320 (define_insn "*sqrtextendsfdf2"
15321 [(set (match_operand:DF 0 "register_operand" "=f")
15322 (sqrt:DF (float_extend:DF
15323 (match_operand:SF 1 "register_operand" "0"))))]
15324 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15325 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
15327 [(set_attr "type" "fpspc")
15328 (set_attr "mode" "DF")
15329 (set_attr "athlon_decode" "direct")])
15331 (define_insn "sqrtxf2"
15332 [(set (match_operand:XF 0 "register_operand" "=f")
15333 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
15334 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
15335 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
15337 [(set_attr "type" "fpspc")
15338 (set_attr "mode" "XF")
15339 (set_attr "athlon_decode" "direct")])
15341 (define_insn "sqrttf2"
15342 [(set (match_operand:TF 0 "register_operand" "=f")
15343 (sqrt:TF (match_operand:TF 1 "register_operand" "0")))]
15344 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15345 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
15347 [(set_attr "type" "fpspc")
15348 (set_attr "mode" "XF")
15349 (set_attr "athlon_decode" "direct")])
15351 (define_insn "*sqrtextenddfxf2"
15352 [(set (match_operand:XF 0 "register_operand" "=f")
15353 (sqrt:XF (float_extend:XF
15354 (match_operand:DF 1 "register_operand" "0"))))]
15355 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
15357 [(set_attr "type" "fpspc")
15358 (set_attr "mode" "XF")
15359 (set_attr "athlon_decode" "direct")])
15361 (define_insn "*sqrtextenddftf2"
15362 [(set (match_operand:TF 0 "register_operand" "=f")
15363 (sqrt:TF (float_extend:TF
15364 (match_operand:DF 1 "register_operand" "0"))))]
15365 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
15367 [(set_attr "type" "fpspc")
15368 (set_attr "mode" "XF")
15369 (set_attr "athlon_decode" "direct")])
15371 (define_insn "*sqrtextendsfxf2"
15372 [(set (match_operand:XF 0 "register_operand" "=f")
15373 (sqrt:XF (float_extend:XF
15374 (match_operand:SF 1 "register_operand" "0"))))]
15375 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
15377 [(set_attr "type" "fpspc")
15378 (set_attr "mode" "XF")
15379 (set_attr "athlon_decode" "direct")])
15381 (define_insn "*sqrtextendsftf2"
15382 [(set (match_operand:TF 0 "register_operand" "=f")
15383 (sqrt:TF (float_extend:TF
15384 (match_operand:SF 1 "register_operand" "0"))))]
15385 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
15387 [(set_attr "type" "fpspc")
15388 (set_attr "mode" "XF")
15389 (set_attr "athlon_decode" "direct")])
15391 (define_insn "sindf2"
15392 [(set (match_operand:DF 0 "register_operand" "=f")
15393 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
15394 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15395 && flag_unsafe_math_optimizations"
15397 [(set_attr "type" "fpspc")
15398 (set_attr "mode" "DF")])
15400 (define_insn "sinsf2"
15401 [(set (match_operand:SF 0 "register_operand" "=f")
15402 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
15403 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15404 && flag_unsafe_math_optimizations"
15406 [(set_attr "type" "fpspc")
15407 (set_attr "mode" "SF")])
15409 (define_insn "*sinextendsfdf2"
15410 [(set (match_operand:DF 0 "register_operand" "=f")
15411 (unspec:DF [(float_extend:DF
15412 (match_operand:SF 1 "register_operand" "0"))]
15414 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15415 && flag_unsafe_math_optimizations"
15417 [(set_attr "type" "fpspc")
15418 (set_attr "mode" "DF")])
15420 (define_insn "sinxf2"
15421 [(set (match_operand:XF 0 "register_operand" "=f")
15422 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
15423 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
15424 && flag_unsafe_math_optimizations"
15426 [(set_attr "type" "fpspc")
15427 (set_attr "mode" "XF")])
15429 (define_insn "sintf2"
15430 [(set (match_operand:TF 0 "register_operand" "=f")
15431 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_SIN))]
15432 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15433 && flag_unsafe_math_optimizations"
15435 [(set_attr "type" "fpspc")
15436 (set_attr "mode" "XF")])
15438 (define_insn "cosdf2"
15439 [(set (match_operand:DF 0 "register_operand" "=f")
15440 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
15441 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15442 && flag_unsafe_math_optimizations"
15444 [(set_attr "type" "fpspc")
15445 (set_attr "mode" "DF")])
15447 (define_insn "cossf2"
15448 [(set (match_operand:SF 0 "register_operand" "=f")
15449 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
15450 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15451 && flag_unsafe_math_optimizations"
15453 [(set_attr "type" "fpspc")
15454 (set_attr "mode" "SF")])
15456 (define_insn "*cosextendsfdf2"
15457 [(set (match_operand:DF 0 "register_operand" "=f")
15458 (unspec:DF [(float_extend:DF
15459 (match_operand:SF 1 "register_operand" "0"))]
15461 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15462 && flag_unsafe_math_optimizations"
15464 [(set_attr "type" "fpspc")
15465 (set_attr "mode" "DF")])
15467 (define_insn "cosxf2"
15468 [(set (match_operand:XF 0 "register_operand" "=f")
15469 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
15470 "!TARGET_64BIT && ! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15471 && flag_unsafe_math_optimizations"
15473 [(set_attr "type" "fpspc")
15474 (set_attr "mode" "XF")])
15476 (define_insn "costf2"
15477 [(set (match_operand:TF 0 "register_operand" "=f")
15478 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_COS))]
15479 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15480 && flag_unsafe_math_optimizations"
15482 [(set_attr "type" "fpspc")
15483 (set_attr "mode" "XF")])
15485 (define_insn "atan2df3"
15486 [(parallel [(set (match_operand:DF 0 "register_operand" "=f")
15487 (unspec:DF [(match_operand:DF 2 "register_operand" "0")
15488 (match_operand:DF 1 "register_operand" "u")]
15490 (clobber (match_dup 1))])]
15491 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15492 && flag_unsafe_math_optimizations"
15494 [(set_attr "type" "fpspc")
15495 (set_attr "mode" "DF")])
15497 (define_insn "atan2sf3"
15498 [(parallel [(set (match_operand:SF 0 "register_operand" "=f")
15499 (unspec:SF [(match_operand:SF 2 "register_operand" "0")
15500 (match_operand:SF 1 "register_operand" "u")]
15502 (clobber (match_dup 1))])]
15503 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15504 && flag_unsafe_math_optimizations"
15506 [(set_attr "type" "fpspc")
15507 (set_attr "mode" "SF")])
15509 (define_insn "atan2xf3"
15510 [(parallel [(set (match_operand:XF 0 "register_operand" "=f")
15511 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15512 (match_operand:XF 1 "register_operand" "u")]
15514 (clobber (match_dup 1))])]
15515 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15516 && flag_unsafe_math_optimizations"
15518 [(set_attr "type" "fpspc")
15519 (set_attr "mode" "XF")])
15521 (define_insn "atan2tf3"
15522 [(parallel [(set (match_operand:TF 0 "register_operand" "=f")
15523 (unspec:TF [(match_operand:TF 2 "register_operand" "0")
15524 (match_operand:TF 1 "register_operand" "u")]
15526 (clobber (match_dup 1))])]
15527 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15528 && flag_unsafe_math_optimizations"
15530 [(set_attr "type" "fpspc")
15531 (set_attr "mode" "XF")])
15533 (define_insn "*fyl2x_sfxf3"
15534 [(parallel [(set (match_operand:SF 0 "register_operand" "=f")
15535 (unspec:SF [(match_operand:SF 2 "register_operand" "0")
15536 (match_operand:XF 1 "register_operand" "u")]
15538 (clobber (match_dup 1))])]
15539 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15540 && flag_unsafe_math_optimizations"
15542 [(set_attr "type" "fpspc")
15543 (set_attr "mode" "SF")])
15545 (define_insn "*fyl2x_dfxf3"
15546 [(parallel [(set (match_operand:DF 0 "register_operand" "=f")
15547 (unspec:DF [(match_operand:DF 2 "register_operand" "0")
15548 (match_operand:XF 1 "register_operand" "u")]
15550 (clobber (match_dup 1))])]
15551 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15552 && flag_unsafe_math_optimizations"
15554 [(set_attr "type" "fpspc")
15555 (set_attr "mode" "DF")])
15557 (define_insn "*fyl2x_xf3"
15558 [(parallel [(set (match_operand:XF 0 "register_operand" "=f")
15559 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15560 (match_operand:XF 1 "register_operand" "u")]
15562 (clobber (match_dup 1))])]
15563 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15564 && flag_unsafe_math_optimizations"
15566 [(set_attr "type" "fpspc")
15567 (set_attr "mode" "XF")])
15569 (define_insn "*fyl2x_tfxf3"
15570 [(parallel [(set (match_operand:TF 0 "register_operand" "=f")
15571 (unspec:TF [(match_operand:TF 2 "register_operand" "0")
15572 (match_operand:XF 1 "register_operand" "u")]
15574 (clobber (match_dup 1))])]
15575 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15576 && flag_unsafe_math_optimizations"
15578 [(set_attr "type" "fpspc")
15579 (set_attr "mode" "XF")])
15581 (define_expand "logsf2"
15582 [(parallel [(set (match_operand:SF 0 "register_operand" "")
15583 (unspec:SF [(match_operand:SF 1 "register_operand" "")
15584 (match_dup 2)] UNSPEC_FYL2X))
15585 (clobber (match_dup 2))])]
15586 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15587 && flag_unsafe_math_optimizations"
15591 operands[2] = gen_reg_rtx (XFmode);
15592 temp = standard_80387_constant_rtx (4); /* fldln2 */
15593 emit_move_insn (operands[2], temp);
15596 (define_expand "logdf2"
15597 [(parallel [(set (match_operand:DF 0 "register_operand" "")
15598 (unspec:DF [(match_operand:DF 1 "register_operand" "")
15599 (match_dup 2)] UNSPEC_FYL2X))
15600 (clobber (match_dup 2))])]
15601 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15602 && flag_unsafe_math_optimizations"
15606 operands[2] = gen_reg_rtx (XFmode);
15607 temp = standard_80387_constant_rtx (4); /* fldln2 */
15608 emit_move_insn (operands[2], temp);
15611 (define_expand "logxf2"
15612 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15613 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15614 (match_dup 2)] UNSPEC_FYL2X))
15615 (clobber (match_dup 2))])]
15616 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15617 && flag_unsafe_math_optimizations"
15621 operands[2] = gen_reg_rtx (XFmode);
15622 temp = standard_80387_constant_rtx (4); /* fldln2 */
15623 emit_move_insn (operands[2], temp);
15626 (define_expand "logtf2"
15627 [(parallel [(set (match_operand:TF 0 "register_operand" "")
15628 (unspec:TF [(match_operand:TF 1 "register_operand" "")
15629 (match_dup 2)] UNSPEC_FYL2X))
15630 (clobber (match_dup 2))])]
15631 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15632 && flag_unsafe_math_optimizations"
15636 operands[2] = gen_reg_rtx (XFmode);
15637 temp = standard_80387_constant_rtx (4); /* fldln2 */
15638 emit_move_insn (operands[2], temp);
15641 ;; Block operation instructions
15644 [(set (reg:SI 19) (const_int 0))]
15647 [(set_attr "type" "cld")])
15649 (define_expand "movstrsi"
15650 [(use (match_operand:BLK 0 "memory_operand" ""))
15651 (use (match_operand:BLK 1 "memory_operand" ""))
15652 (use (match_operand:SI 2 "nonmemory_operand" ""))
15653 (use (match_operand:SI 3 "const_int_operand" ""))]
15656 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
15662 (define_expand "movstrdi"
15663 [(use (match_operand:BLK 0 "memory_operand" ""))
15664 (use (match_operand:BLK 1 "memory_operand" ""))
15665 (use (match_operand:DI 2 "nonmemory_operand" ""))
15666 (use (match_operand:DI 3 "const_int_operand" ""))]
15669 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
15675 ;; Most CPUs don't like single string operations
15676 ;; Handle this case here to simplify previous expander.
15678 (define_expand "strmovdi_rex64"
15679 [(set (match_dup 2)
15680 (mem:DI (match_operand:DI 1 "register_operand" "")))
15681 (set (mem:DI (match_operand:DI 0 "register_operand" ""))
15683 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
15684 (clobber (reg:CC 17))])
15685 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 8)))
15686 (clobber (reg:CC 17))])]
15689 if (TARGET_SINGLE_STRINGOP || optimize_size)
15691 emit_insn (gen_strmovdi_rex_1 (operands[0], operands[1], operands[0],
15696 operands[2] = gen_reg_rtx (DImode);
15700 (define_expand "strmovsi"
15701 [(set (match_dup 2)
15702 (mem:SI (match_operand:SI 1 "register_operand" "")))
15703 (set (mem:SI (match_operand:SI 0 "register_operand" ""))
15705 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
15706 (clobber (reg:CC 17))])
15707 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))
15708 (clobber (reg:CC 17))])]
15713 emit_insn (gen_strmovsi_rex64 (operands[0], operands[1]));
15716 if (TARGET_SINGLE_STRINGOP || optimize_size)
15718 emit_insn (gen_strmovsi_1 (operands[0], operands[1], operands[0],
15723 operands[2] = gen_reg_rtx (SImode);
15726 (define_expand "strmovsi_rex64"
15727 [(set (match_dup 2)
15728 (mem:SI (match_operand:DI 1 "register_operand" "")))
15729 (set (mem:SI (match_operand:DI 0 "register_operand" ""))
15731 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
15732 (clobber (reg:CC 17))])
15733 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 4)))
15734 (clobber (reg:CC 17))])]
15737 if (TARGET_SINGLE_STRINGOP || optimize_size)
15739 emit_insn (gen_strmovsi_rex_1 (operands[0], operands[1], operands[0],
15744 operands[2] = gen_reg_rtx (SImode);
15747 (define_expand "strmovhi"
15748 [(set (match_dup 2)
15749 (mem:HI (match_operand:SI 1 "register_operand" "")))
15750 (set (mem:HI (match_operand:SI 0 "register_operand" ""))
15752 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
15753 (clobber (reg:CC 17))])
15754 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))
15755 (clobber (reg:CC 17))])]
15760 emit_insn (gen_strmovhi_rex64 (operands[0], operands[1]));
15763 if (TARGET_SINGLE_STRINGOP || optimize_size)
15765 emit_insn (gen_strmovhi_1 (operands[0], operands[1], operands[0],
15770 operands[2] = gen_reg_rtx (HImode);
15773 (define_expand "strmovhi_rex64"
15774 [(set (match_dup 2)
15775 (mem:HI (match_operand:DI 1 "register_operand" "")))
15776 (set (mem:HI (match_operand:DI 0 "register_operand" ""))
15778 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
15779 (clobber (reg:CC 17))])
15780 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 2)))
15781 (clobber (reg:CC 17))])]
15784 if (TARGET_SINGLE_STRINGOP || optimize_size)
15786 emit_insn (gen_strmovhi_rex_1 (operands[0], operands[1], operands[0],
15791 operands[2] = gen_reg_rtx (HImode);
15794 (define_expand "strmovqi"
15795 [(set (match_dup 2)
15796 (mem:QI (match_operand:SI 1 "register_operand" "")))
15797 (set (mem:QI (match_operand:SI 0 "register_operand" ""))
15799 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
15800 (clobber (reg:CC 17))])
15801 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))
15802 (clobber (reg:CC 17))])]
15807 emit_insn (gen_strmovqi_rex64 (operands[0], operands[1]));
15810 if (TARGET_SINGLE_STRINGOP || optimize_size)
15812 emit_insn (gen_strmovqi_1 (operands[0], operands[1], operands[0],
15817 operands[2] = gen_reg_rtx (QImode);
15820 (define_expand "strmovqi_rex64"
15821 [(set (match_dup 2)
15822 (mem:QI (match_operand:DI 1 "register_operand" "")))
15823 (set (mem:QI (match_operand:DI 0 "register_operand" ""))
15825 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
15826 (clobber (reg:CC 17))])
15827 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 1)))
15828 (clobber (reg:CC 17))])]
15831 if (TARGET_SINGLE_STRINGOP || optimize_size)
15833 emit_insn (gen_strmovqi_rex_1 (operands[0], operands[1], operands[0],
15838 operands[2] = gen_reg_rtx (QImode);
15841 (define_insn "strmovdi_rex_1"
15842 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
15843 (mem:DI (match_operand:DI 3 "register_operand" "1")))
15844 (set (match_operand:DI 0 "register_operand" "=D")
15845 (plus:DI (match_dup 2)
15847 (set (match_operand:DI 1 "register_operand" "=S")
15848 (plus:DI (match_dup 3)
15851 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15853 [(set_attr "type" "str")
15854 (set_attr "mode" "DI")
15855 (set_attr "memory" "both")])
15857 (define_insn "strmovsi_1"
15858 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
15859 (mem:SI (match_operand:SI 3 "register_operand" "1")))
15860 (set (match_operand:SI 0 "register_operand" "=D")
15861 (plus:SI (match_dup 2)
15863 (set (match_operand:SI 1 "register_operand" "=S")
15864 (plus:SI (match_dup 3)
15867 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15869 [(set_attr "type" "str")
15870 (set_attr "mode" "SI")
15871 (set_attr "memory" "both")])
15873 (define_insn "strmovsi_rex_1"
15874 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
15875 (mem:SI (match_operand:DI 3 "register_operand" "1")))
15876 (set (match_operand:DI 0 "register_operand" "=D")
15877 (plus:DI (match_dup 2)
15879 (set (match_operand:DI 1 "register_operand" "=S")
15880 (plus:DI (match_dup 3)
15883 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15885 [(set_attr "type" "str")
15886 (set_attr "mode" "SI")
15887 (set_attr "memory" "both")])
15889 (define_insn "strmovhi_1"
15890 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
15891 (mem:HI (match_operand:SI 3 "register_operand" "1")))
15892 (set (match_operand:SI 0 "register_operand" "=D")
15893 (plus:SI (match_dup 2)
15895 (set (match_operand:SI 1 "register_operand" "=S")
15896 (plus:SI (match_dup 3)
15899 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15901 [(set_attr "type" "str")
15902 (set_attr "memory" "both")
15903 (set_attr "mode" "HI")])
15905 (define_insn "strmovhi_rex_1"
15906 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
15907 (mem:HI (match_operand:DI 3 "register_operand" "1")))
15908 (set (match_operand:DI 0 "register_operand" "=D")
15909 (plus:DI (match_dup 2)
15911 (set (match_operand:DI 1 "register_operand" "=S")
15912 (plus:DI (match_dup 3)
15915 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15917 [(set_attr "type" "str")
15918 (set_attr "memory" "both")
15919 (set_attr "mode" "HI")])
15921 (define_insn "strmovqi_1"
15922 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
15923 (mem:QI (match_operand:SI 3 "register_operand" "1")))
15924 (set (match_operand:SI 0 "register_operand" "=D")
15925 (plus:SI (match_dup 2)
15927 (set (match_operand:SI 1 "register_operand" "=S")
15928 (plus:SI (match_dup 3)
15931 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15933 [(set_attr "type" "str")
15934 (set_attr "memory" "both")
15935 (set_attr "mode" "QI")])
15937 (define_insn "strmovqi_rex_1"
15938 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
15939 (mem:QI (match_operand:DI 3 "register_operand" "1")))
15940 (set (match_operand:DI 0 "register_operand" "=D")
15941 (plus:DI (match_dup 2)
15943 (set (match_operand:DI 1 "register_operand" "=S")
15944 (plus:DI (match_dup 3)
15947 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15949 [(set_attr "type" "str")
15950 (set_attr "memory" "both")
15951 (set_attr "mode" "QI")])
15953 (define_insn "rep_movdi_rex64"
15954 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15955 (set (match_operand:DI 0 "register_operand" "=D")
15956 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
15958 (match_operand:DI 3 "register_operand" "0")))
15959 (set (match_operand:DI 1 "register_operand" "=S")
15960 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
15961 (match_operand:DI 4 "register_operand" "1")))
15962 (set (mem:BLK (match_dup 3))
15963 (mem:BLK (match_dup 4)))
15964 (use (match_dup 5))
15967 "{rep\;movsq|rep movsq}"
15968 [(set_attr "type" "str")
15969 (set_attr "prefix_rep" "1")
15970 (set_attr "memory" "both")
15971 (set_attr "mode" "DI")])
15973 (define_insn "rep_movsi"
15974 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
15975 (set (match_operand:SI 0 "register_operand" "=D")
15976 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
15978 (match_operand:SI 3 "register_operand" "0")))
15979 (set (match_operand:SI 1 "register_operand" "=S")
15980 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
15981 (match_operand:SI 4 "register_operand" "1")))
15982 (set (mem:BLK (match_dup 3))
15983 (mem:BLK (match_dup 4)))
15984 (use (match_dup 5))
15987 "{rep\;movsl|rep movsd}"
15988 [(set_attr "type" "str")
15989 (set_attr "prefix_rep" "1")
15990 (set_attr "memory" "both")
15991 (set_attr "mode" "SI")])
15993 (define_insn "rep_movsi_rex64"
15994 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15995 (set (match_operand:DI 0 "register_operand" "=D")
15996 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
15998 (match_operand:DI 3 "register_operand" "0")))
15999 (set (match_operand:DI 1 "register_operand" "=S")
16000 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
16001 (match_operand:DI 4 "register_operand" "1")))
16002 (set (mem:BLK (match_dup 3))
16003 (mem:BLK (match_dup 4)))
16004 (use (match_dup 5))
16007 "{rep\;movsl|rep movsd}"
16008 [(set_attr "type" "str")
16009 (set_attr "prefix_rep" "1")
16010 (set_attr "memory" "both")
16011 (set_attr "mode" "SI")])
16013 (define_insn "rep_movqi"
16014 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
16015 (set (match_operand:SI 0 "register_operand" "=D")
16016 (plus:SI (match_operand:SI 3 "register_operand" "0")
16017 (match_operand:SI 5 "register_operand" "2")))
16018 (set (match_operand:SI 1 "register_operand" "=S")
16019 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
16020 (set (mem:BLK (match_dup 3))
16021 (mem:BLK (match_dup 4)))
16022 (use (match_dup 5))
16025 "{rep\;movsb|rep movsb}"
16026 [(set_attr "type" "str")
16027 (set_attr "prefix_rep" "1")
16028 (set_attr "memory" "both")
16029 (set_attr "mode" "SI")])
16031 (define_insn "rep_movqi_rex64"
16032 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
16033 (set (match_operand:DI 0 "register_operand" "=D")
16034 (plus:DI (match_operand:DI 3 "register_operand" "0")
16035 (match_operand:DI 5 "register_operand" "2")))
16036 (set (match_operand:DI 1 "register_operand" "=S")
16037 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
16038 (set (mem:BLK (match_dup 3))
16039 (mem:BLK (match_dup 4)))
16040 (use (match_dup 5))
16043 "{rep\;movsb|rep movsb}"
16044 [(set_attr "type" "str")
16045 (set_attr "prefix_rep" "1")
16046 (set_attr "memory" "both")
16047 (set_attr "mode" "SI")])
16049 (define_expand "clrstrsi"
16050 [(use (match_operand:BLK 0 "memory_operand" ""))
16051 (use (match_operand:SI 1 "nonmemory_operand" ""))
16052 (use (match_operand 2 "const_int_operand" ""))]
16055 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
16061 (define_expand "clrstrdi"
16062 [(use (match_operand:BLK 0 "memory_operand" ""))
16063 (use (match_operand:DI 1 "nonmemory_operand" ""))
16064 (use (match_operand 2 "const_int_operand" ""))]
16067 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
16073 ;; Most CPUs don't like single string operations
16074 ;; Handle this case here to simplify previous expander.
16076 (define_expand "strsetdi_rex64"
16077 [(set (mem:DI (match_operand:DI 0 "register_operand" ""))
16078 (match_operand:DI 1 "register_operand" ""))
16079 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
16080 (clobber (reg:CC 17))])]
16083 if (TARGET_SINGLE_STRINGOP || optimize_size)
16085 emit_insn (gen_strsetdi_rex_1 (operands[0], operands[0], operands[1]));
16090 (define_expand "strsetsi"
16091 [(set (mem:SI (match_operand:SI 0 "register_operand" ""))
16092 (match_operand:SI 1 "register_operand" ""))
16093 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
16094 (clobber (reg:CC 17))])]
16099 emit_insn (gen_strsetsi_rex64 (operands[0], operands[1]));
16102 else if (TARGET_SINGLE_STRINGOP || optimize_size)
16104 emit_insn (gen_strsetsi_1 (operands[0], operands[0], operands[1]));
16109 (define_expand "strsetsi_rex64"
16110 [(set (mem:SI (match_operand:DI 0 "register_operand" ""))
16111 (match_operand:SI 1 "register_operand" ""))
16112 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
16113 (clobber (reg:CC 17))])]
16116 if (TARGET_SINGLE_STRINGOP || optimize_size)
16118 emit_insn (gen_strsetsi_rex_1 (operands[0], operands[0], operands[1]));
16123 (define_expand "strsethi"
16124 [(set (mem:HI (match_operand:SI 0 "register_operand" ""))
16125 (match_operand:HI 1 "register_operand" ""))
16126 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
16127 (clobber (reg:CC 17))])]
16132 emit_insn (gen_strsethi_rex64 (operands[0], operands[1]));
16135 else if (TARGET_SINGLE_STRINGOP || optimize_size)
16137 emit_insn (gen_strsethi_1 (operands[0], operands[0], operands[1]));
16142 (define_expand "strsethi_rex64"
16143 [(set (mem:HI (match_operand:DI 0 "register_operand" ""))
16144 (match_operand:HI 1 "register_operand" ""))
16145 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
16146 (clobber (reg:CC 17))])]
16149 if (TARGET_SINGLE_STRINGOP || optimize_size)
16151 emit_insn (gen_strsethi_rex_1 (operands[0], operands[0], operands[1]));
16156 (define_expand "strsetqi"
16157 [(set (mem:QI (match_operand:SI 0 "register_operand" ""))
16158 (match_operand:QI 1 "register_operand" ""))
16159 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
16160 (clobber (reg:CC 17))])]
16165 emit_insn (gen_strsetqi_rex64 (operands[0], operands[1]));
16168 else if (TARGET_SINGLE_STRINGOP || optimize_size)
16170 emit_insn (gen_strsetqi_1 (operands[0], operands[0], operands[1]));
16175 (define_expand "strsetqi_rex64"
16176 [(set (mem:QI (match_operand:DI 0 "register_operand" ""))
16177 (match_operand:QI 1 "register_operand" ""))
16178 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
16179 (clobber (reg:CC 17))])]
16182 if (TARGET_SINGLE_STRINGOP || optimize_size)
16184 emit_insn (gen_strsetqi_rex_1 (operands[0], operands[0], operands[1]));
16189 (define_insn "strsetdi_rex_1"
16190 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
16191 (match_operand:SI 2 "register_operand" "a"))
16192 (set (match_operand:DI 0 "register_operand" "=D")
16193 (plus:DI (match_dup 1)
16196 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16198 [(set_attr "type" "str")
16199 (set_attr "memory" "store")
16200 (set_attr "mode" "DI")])
16202 (define_insn "strsetsi_1"
16203 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
16204 (match_operand:SI 2 "register_operand" "a"))
16205 (set (match_operand:SI 0 "register_operand" "=D")
16206 (plus:SI (match_dup 1)
16209 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16211 [(set_attr "type" "str")
16212 (set_attr "memory" "store")
16213 (set_attr "mode" "SI")])
16215 (define_insn "strsetsi_rex_1"
16216 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
16217 (match_operand:SI 2 "register_operand" "a"))
16218 (set (match_operand:DI 0 "register_operand" "=D")
16219 (plus:DI (match_dup 1)
16222 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16224 [(set_attr "type" "str")
16225 (set_attr "memory" "store")
16226 (set_attr "mode" "SI")])
16228 (define_insn "strsethi_1"
16229 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
16230 (match_operand:HI 2 "register_operand" "a"))
16231 (set (match_operand:SI 0 "register_operand" "=D")
16232 (plus:SI (match_dup 1)
16235 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16237 [(set_attr "type" "str")
16238 (set_attr "memory" "store")
16239 (set_attr "mode" "HI")])
16241 (define_insn "strsethi_rex_1"
16242 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
16243 (match_operand:HI 2 "register_operand" "a"))
16244 (set (match_operand:DI 0 "register_operand" "=D")
16245 (plus:DI (match_dup 1)
16248 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16250 [(set_attr "type" "str")
16251 (set_attr "memory" "store")
16252 (set_attr "mode" "HI")])
16254 (define_insn "strsetqi_1"
16255 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
16256 (match_operand:QI 2 "register_operand" "a"))
16257 (set (match_operand:SI 0 "register_operand" "=D")
16258 (plus:SI (match_dup 1)
16261 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16263 [(set_attr "type" "str")
16264 (set_attr "memory" "store")
16265 (set_attr "mode" "QI")])
16267 (define_insn "strsetqi_rex_1"
16268 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
16269 (match_operand:QI 2 "register_operand" "a"))
16270 (set (match_operand:DI 0 "register_operand" "=D")
16271 (plus:DI (match_dup 1)
16274 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16276 [(set_attr "type" "str")
16277 (set_attr "memory" "store")
16278 (set_attr "mode" "QI")])
16280 (define_insn "rep_stosdi_rex64"
16281 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
16282 (set (match_operand:DI 0 "register_operand" "=D")
16283 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
16285 (match_operand:DI 3 "register_operand" "0")))
16286 (set (mem:BLK (match_dup 3))
16288 (use (match_operand:DI 2 "register_operand" "a"))
16289 (use (match_dup 4))
16292 "{rep\;stosq|rep stosq}"
16293 [(set_attr "type" "str")
16294 (set_attr "prefix_rep" "1")
16295 (set_attr "memory" "store")
16296 (set_attr "mode" "DI")])
16298 (define_insn "rep_stossi"
16299 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
16300 (set (match_operand:SI 0 "register_operand" "=D")
16301 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
16303 (match_operand:SI 3 "register_operand" "0")))
16304 (set (mem:BLK (match_dup 3))
16306 (use (match_operand:SI 2 "register_operand" "a"))
16307 (use (match_dup 4))
16310 "{rep\;stosl|rep stosd}"
16311 [(set_attr "type" "str")
16312 (set_attr "prefix_rep" "1")
16313 (set_attr "memory" "store")
16314 (set_attr "mode" "SI")])
16316 (define_insn "rep_stossi_rex64"
16317 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
16318 (set (match_operand:DI 0 "register_operand" "=D")
16319 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
16321 (match_operand:DI 3 "register_operand" "0")))
16322 (set (mem:BLK (match_dup 3))
16324 (use (match_operand:SI 2 "register_operand" "a"))
16325 (use (match_dup 4))
16328 "{rep\;stosl|rep stosd}"
16329 [(set_attr "type" "str")
16330 (set_attr "prefix_rep" "1")
16331 (set_attr "memory" "store")
16332 (set_attr "mode" "SI")])
16334 (define_insn "rep_stosqi"
16335 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
16336 (set (match_operand:SI 0 "register_operand" "=D")
16337 (plus:SI (match_operand:SI 3 "register_operand" "0")
16338 (match_operand:SI 4 "register_operand" "1")))
16339 (set (mem:BLK (match_dup 3))
16341 (use (match_operand:QI 2 "register_operand" "a"))
16342 (use (match_dup 4))
16345 "{rep\;stosb|rep stosb}"
16346 [(set_attr "type" "str")
16347 (set_attr "prefix_rep" "1")
16348 (set_attr "memory" "store")
16349 (set_attr "mode" "QI")])
16351 (define_insn "rep_stosqi_rex64"
16352 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
16353 (set (match_operand:DI 0 "register_operand" "=D")
16354 (plus:DI (match_operand:DI 3 "register_operand" "0")
16355 (match_operand:DI 4 "register_operand" "1")))
16356 (set (mem:BLK (match_dup 3))
16358 (use (match_operand:QI 2 "register_operand" "a"))
16359 (use (match_dup 4))
16362 "{rep\;stosb|rep stosb}"
16363 [(set_attr "type" "str")
16364 (set_attr "prefix_rep" "1")
16365 (set_attr "memory" "store")
16366 (set_attr "mode" "QI")])
16368 (define_expand "cmpstrsi"
16369 [(set (match_operand:SI 0 "register_operand" "")
16370 (compare:SI (match_operand:BLK 1 "general_operand" "")
16371 (match_operand:BLK 2 "general_operand" "")))
16372 (use (match_operand 3 "general_operand" ""))
16373 (use (match_operand 4 "immediate_operand" ""))]
16376 rtx addr1, addr2, out, outlow, count, countreg, align;
16378 /* Can't use this if the user has appropriated esi or edi. */
16379 if (global_regs[4] || global_regs[5])
16383 if (GET_CODE (out) != REG)
16384 out = gen_reg_rtx (SImode);
16386 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
16387 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
16389 count = operands[3];
16390 countreg = ix86_zero_extend_to_Pmode (count);
16392 /* %%% Iff we are testing strict equality, we can use known alignment
16393 to good advantage. This may be possible with combine, particularly
16394 once cc0 is dead. */
16395 align = operands[4];
16397 emit_insn (gen_cld ());
16398 if (GET_CODE (count) == CONST_INT)
16400 if (INTVAL (count) == 0)
16402 emit_move_insn (operands[0], const0_rtx);
16406 emit_insn (gen_cmpstrqi_nz_rex_1 (addr1, addr2, countreg, align,
16407 addr1, addr2, countreg));
16409 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
16410 addr1, addr2, countreg));
16416 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
16417 emit_insn (gen_cmpstrqi_rex_1 (addr1, addr2, countreg, align,
16418 addr1, addr2, countreg));
16422 emit_insn (gen_cmpsi_1 (countreg, countreg));
16423 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
16424 addr1, addr2, countreg));
16428 outlow = gen_lowpart (QImode, out);
16429 emit_insn (gen_cmpintqi (outlow));
16430 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
16432 if (operands[0] != out)
16433 emit_move_insn (operands[0], out);
16438 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
16440 (define_expand "cmpintqi"
16441 [(set (match_dup 1)
16442 (gtu:QI (reg:CC 17) (const_int 0)))
16444 (ltu:QI (reg:CC 17) (const_int 0)))
16445 (parallel [(set (match_operand:QI 0 "register_operand" "")
16446 (minus:QI (match_dup 1)
16448 (clobber (reg:CC 17))])]
16450 "operands[1] = gen_reg_rtx (QImode);
16451 operands[2] = gen_reg_rtx (QImode);")
16453 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
16454 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
16456 (define_insn "cmpstrqi_nz_1"
16458 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
16459 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
16460 (use (match_operand:SI 6 "register_operand" "2"))
16461 (use (match_operand:SI 3 "immediate_operand" "i"))
16463 (clobber (match_operand:SI 0 "register_operand" "=S"))
16464 (clobber (match_operand:SI 1 "register_operand" "=D"))
16465 (clobber (match_operand:SI 2 "register_operand" "=c"))]
16468 [(set_attr "type" "str")
16469 (set_attr "mode" "QI")
16470 (set_attr "prefix_rep" "1")])
16472 (define_insn "cmpstrqi_nz_rex_1"
16474 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
16475 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
16476 (use (match_operand:DI 6 "register_operand" "2"))
16477 (use (match_operand:SI 3 "immediate_operand" "i"))
16479 (clobber (match_operand:DI 0 "register_operand" "=S"))
16480 (clobber (match_operand:DI 1 "register_operand" "=D"))
16481 (clobber (match_operand:DI 2 "register_operand" "=c"))]
16484 [(set_attr "type" "str")
16485 (set_attr "mode" "QI")
16486 (set_attr "prefix_rep" "1")])
16488 ;; The same, but the count is not known to not be zero.
16490 (define_insn "cmpstrqi_1"
16492 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
16494 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
16495 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
16497 (use (match_operand:SI 3 "immediate_operand" "i"))
16500 (clobber (match_operand:SI 0 "register_operand" "=S"))
16501 (clobber (match_operand:SI 1 "register_operand" "=D"))
16502 (clobber (match_operand:SI 2 "register_operand" "=c"))]
16505 [(set_attr "type" "str")
16506 (set_attr "mode" "QI")
16507 (set_attr "prefix_rep" "1")])
16509 (define_insn "cmpstrqi_rex_1"
16511 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
16513 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
16514 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
16516 (use (match_operand:SI 3 "immediate_operand" "i"))
16519 (clobber (match_operand:DI 0 "register_operand" "=S"))
16520 (clobber (match_operand:DI 1 "register_operand" "=D"))
16521 (clobber (match_operand:DI 2 "register_operand" "=c"))]
16524 [(set_attr "type" "str")
16525 (set_attr "mode" "QI")
16526 (set_attr "prefix_rep" "1")])
16528 (define_expand "strlensi"
16529 [(set (match_operand:SI 0 "register_operand" "")
16530 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
16531 (match_operand:QI 2 "immediate_operand" "")
16532 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
16535 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
16541 (define_expand "strlendi"
16542 [(set (match_operand:DI 0 "register_operand" "")
16543 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
16544 (match_operand:QI 2 "immediate_operand" "")
16545 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
16548 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
16554 (define_insn "strlenqi_1"
16555 [(set (match_operand:SI 0 "register_operand" "=&c")
16556 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
16557 (match_operand:QI 2 "register_operand" "a")
16558 (match_operand:SI 3 "immediate_operand" "i")
16559 (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
16561 (clobber (match_operand:SI 1 "register_operand" "=D"))
16562 (clobber (reg:CC 17))]
16565 [(set_attr "type" "str")
16566 (set_attr "mode" "QI")
16567 (set_attr "prefix_rep" "1")])
16569 (define_insn "strlenqi_rex_1"
16570 [(set (match_operand:DI 0 "register_operand" "=&c")
16571 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
16572 (match_operand:QI 2 "register_operand" "a")
16573 (match_operand:DI 3 "immediate_operand" "i")
16574 (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
16576 (clobber (match_operand:DI 1 "register_operand" "=D"))
16577 (clobber (reg:CC 17))]
16580 [(set_attr "type" "str")
16581 (set_attr "mode" "QI")
16582 (set_attr "prefix_rep" "1")])
16584 ;; Peephole optimizations to clean up after cmpstr*. This should be
16585 ;; handled in combine, but it is not currently up to the task.
16586 ;; When used for their truth value, the cmpstr* expanders generate
16595 ;; The intermediate three instructions are unnecessary.
16597 ;; This one handles cmpstr*_nz_1...
16601 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
16602 (mem:BLK (match_operand 5 "register_operand" ""))))
16603 (use (match_operand 6 "register_operand" ""))
16604 (use (match_operand:SI 3 "immediate_operand" ""))
16606 (clobber (match_operand 0 "register_operand" ""))
16607 (clobber (match_operand 1 "register_operand" ""))
16608 (clobber (match_operand 2 "register_operand" ""))])
16609 (set (match_operand:QI 7 "register_operand" "")
16610 (gtu:QI (reg:CC 17) (const_int 0)))
16611 (set (match_operand:QI 8 "register_operand" "")
16612 (ltu:QI (reg:CC 17) (const_int 0)))
16614 (compare (match_dup 7) (match_dup 8)))
16616 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
16619 (compare:CC (mem:BLK (match_dup 4))
16620 (mem:BLK (match_dup 5))))
16621 (use (match_dup 6))
16622 (use (match_dup 3))
16624 (clobber (match_dup 0))
16625 (clobber (match_dup 1))
16626 (clobber (match_dup 2))])]
16629 ;; ...and this one handles cmpstr*_1.
16633 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
16635 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
16636 (mem:BLK (match_operand 5 "register_operand" "")))
16638 (use (match_operand:SI 3 "immediate_operand" ""))
16641 (clobber (match_operand 0 "register_operand" ""))
16642 (clobber (match_operand 1 "register_operand" ""))
16643 (clobber (match_operand 2 "register_operand" ""))])
16644 (set (match_operand:QI 7 "register_operand" "")
16645 (gtu:QI (reg:CC 17) (const_int 0)))
16646 (set (match_operand:QI 8 "register_operand" "")
16647 (ltu:QI (reg:CC 17) (const_int 0)))
16649 (compare (match_dup 7) (match_dup 8)))
16651 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
16654 (if_then_else:CC (ne (match_dup 6)
16656 (compare:CC (mem:BLK (match_dup 4))
16657 (mem:BLK (match_dup 5)))
16659 (use (match_dup 3))
16662 (clobber (match_dup 0))
16663 (clobber (match_dup 1))
16664 (clobber (match_dup 2))])]
16669 ;; Conditional move instructions.
16671 (define_expand "movdicc"
16672 [(set (match_operand:DI 0 "register_operand" "")
16673 (if_then_else:DI (match_operand 1 "comparison_operator" "")
16674 (match_operand:DI 2 "general_operand" "")
16675 (match_operand:DI 3 "general_operand" "")))]
16677 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16679 (define_insn "x86_movdicc_0_m1_rex64"
16680 [(set (match_operand:DI 0 "register_operand" "=r")
16681 (if_then_else:DI (match_operand 1 "ix86_carry_flag_operator" "")
16684 (clobber (reg:CC 17))]
16687 ; Since we don't have the proper number of operands for an alu insn,
16688 ; fill in all the blanks.
16689 [(set_attr "type" "alu")
16690 (set_attr "pent_pair" "pu")
16691 (set_attr "memory" "none")
16692 (set_attr "imm_disp" "false")
16693 (set_attr "mode" "DI")
16694 (set_attr "length_immediate" "0")])
16696 (define_insn "movdicc_c_rex64"
16697 [(set (match_operand:DI 0 "register_operand" "=r,r")
16698 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
16699 [(reg 17) (const_int 0)])
16700 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
16701 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
16702 "TARGET_64BIT && TARGET_CMOVE
16703 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16705 cmov%O2%C1\t{%2, %0|%0, %2}
16706 cmov%O2%c1\t{%3, %0|%0, %3}"
16707 [(set_attr "type" "icmov")
16708 (set_attr "mode" "DI")])
16710 (define_expand "movsicc"
16711 [(set (match_operand:SI 0 "register_operand" "")
16712 (if_then_else:SI (match_operand 1 "comparison_operator" "")
16713 (match_operand:SI 2 "general_operand" "")
16714 (match_operand:SI 3 "general_operand" "")))]
16716 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16718 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
16719 ;; the register first winds up with `sbbl $0,reg', which is also weird.
16720 ;; So just document what we're doing explicitly.
16722 (define_insn "x86_movsicc_0_m1"
16723 [(set (match_operand:SI 0 "register_operand" "=r")
16724 (if_then_else:SI (match_operand 1 "ix86_carry_flag_operator" "")
16727 (clobber (reg:CC 17))]
16730 ; Since we don't have the proper number of operands for an alu insn,
16731 ; fill in all the blanks.
16732 [(set_attr "type" "alu")
16733 (set_attr "pent_pair" "pu")
16734 (set_attr "memory" "none")
16735 (set_attr "imm_disp" "false")
16736 (set_attr "mode" "SI")
16737 (set_attr "length_immediate" "0")])
16739 (define_insn "*movsicc_noc"
16740 [(set (match_operand:SI 0 "register_operand" "=r,r")
16741 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
16742 [(reg 17) (const_int 0)])
16743 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
16744 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
16746 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16748 cmov%O2%C1\t{%2, %0|%0, %2}
16749 cmov%O2%c1\t{%3, %0|%0, %3}"
16750 [(set_attr "type" "icmov")
16751 (set_attr "mode" "SI")])
16753 (define_expand "movhicc"
16754 [(set (match_operand:HI 0 "register_operand" "")
16755 (if_then_else:HI (match_operand 1 "comparison_operator" "")
16756 (match_operand:HI 2 "general_operand" "")
16757 (match_operand:HI 3 "general_operand" "")))]
16758 "TARGET_HIMODE_MATH"
16759 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16761 (define_insn "*movhicc_noc"
16762 [(set (match_operand:HI 0 "register_operand" "=r,r")
16763 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
16764 [(reg 17) (const_int 0)])
16765 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
16766 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
16768 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16770 cmov%O2%C1\t{%2, %0|%0, %2}
16771 cmov%O2%c1\t{%3, %0|%0, %3}"
16772 [(set_attr "type" "icmov")
16773 (set_attr "mode" "HI")])
16775 (define_expand "movqicc"
16776 [(set (match_operand:QI 0 "register_operand" "")
16777 (if_then_else:QI (match_operand 1 "comparison_operator" "")
16778 (match_operand:QI 2 "general_operand" "")
16779 (match_operand:QI 3 "general_operand" "")))]
16780 "TARGET_QIMODE_MATH"
16781 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16783 (define_insn_and_split "*movqicc_noc"
16784 [(set (match_operand:QI 0 "register_operand" "=r,r")
16785 (if_then_else:QI (match_operator 1 "ix86_comparison_operator"
16786 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
16787 (match_operand:QI 2 "register_operand" "r,0")
16788 (match_operand:QI 3 "register_operand" "0,r")))]
16789 "TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
16791 "&& reload_completed"
16792 [(set (match_dup 0)
16793 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
16796 "operands[0] = gen_lowpart (SImode, operands[0]);
16797 operands[2] = gen_lowpart (SImode, operands[2]);
16798 operands[3] = gen_lowpart (SImode, operands[3]);"
16799 [(set_attr "type" "icmov")
16800 (set_attr "mode" "SI")])
16802 (define_expand "movsfcc"
16803 [(set (match_operand:SF 0 "register_operand" "")
16804 (if_then_else:SF (match_operand 1 "comparison_operator" "")
16805 (match_operand:SF 2 "register_operand" "")
16806 (match_operand:SF 3 "register_operand" "")))]
16808 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16810 (define_insn "*movsfcc_1"
16811 [(set (match_operand:SF 0 "register_operand" "=f#r,f#r,r#f,r#f")
16812 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16813 [(reg 17) (const_int 0)])
16814 (match_operand:SF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
16815 (match_operand:SF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
16817 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16819 fcmov%F1\t{%2, %0|%0, %2}
16820 fcmov%f1\t{%3, %0|%0, %3}
16821 cmov%O2%C1\t{%2, %0|%0, %2}
16822 cmov%O2%c1\t{%3, %0|%0, %3}"
16823 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
16824 (set_attr "mode" "SF,SF,SI,SI")])
16826 (define_expand "movdfcc"
16827 [(set (match_operand:DF 0 "register_operand" "")
16828 (if_then_else:DF (match_operand 1 "comparison_operator" "")
16829 (match_operand:DF 2 "register_operand" "")
16830 (match_operand:DF 3 "register_operand" "")))]
16832 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16834 (define_insn "*movdfcc_1"
16835 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,&r#f,&r#f")
16836 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16837 [(reg 17) (const_int 0)])
16838 (match_operand:DF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
16839 (match_operand:DF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
16840 "!TARGET_64BIT && TARGET_CMOVE
16841 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16843 fcmov%F1\t{%2, %0|%0, %2}
16844 fcmov%f1\t{%3, %0|%0, %3}
16847 [(set_attr "type" "fcmov,fcmov,multi,multi")
16848 (set_attr "mode" "DF")])
16850 (define_insn "*movdfcc_1_rex64"
16851 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,r#f,r#f")
16852 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16853 [(reg 17) (const_int 0)])
16854 (match_operand:DF 2 "nonimmediate_operand" "f#r,0#r,rm#f,0#f")
16855 (match_operand:DF 3 "nonimmediate_operand" "0#r,f#r,0#f,rm#f")))]
16856 "TARGET_64BIT && TARGET_CMOVE
16857 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16859 fcmov%F1\t{%2, %0|%0, %2}
16860 fcmov%f1\t{%3, %0|%0, %3}
16861 cmov%O2%C1\t{%2, %0|%0, %2}
16862 cmov%O2%c1\t{%3, %0|%0, %3}"
16863 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
16864 (set_attr "mode" "DF")])
16867 [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
16868 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16869 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
16870 (match_operand:DF 2 "nonimmediate_operand" "")
16871 (match_operand:DF 3 "nonimmediate_operand" "")))]
16872 "!TARGET_64BIT && reload_completed"
16873 [(set (match_dup 2)
16874 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
16878 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
16881 "split_di (operands+2, 1, operands+5, operands+6);
16882 split_di (operands+3, 1, operands+7, operands+8);
16883 split_di (operands, 1, operands+2, operands+3);")
16885 (define_expand "movxfcc"
16886 [(set (match_operand:XF 0 "register_operand" "")
16887 (if_then_else:XF (match_operand 1 "comparison_operator" "")
16888 (match_operand:XF 2 "register_operand" "")
16889 (match_operand:XF 3 "register_operand" "")))]
16890 "!TARGET_64BIT && TARGET_CMOVE"
16891 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16893 (define_expand "movtfcc"
16894 [(set (match_operand:TF 0 "register_operand" "")
16895 (if_then_else:TF (match_operand 1 "comparison_operator" "")
16896 (match_operand:TF 2 "register_operand" "")
16897 (match_operand:TF 3 "register_operand" "")))]
16899 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16901 (define_insn "*movxfcc_1"
16902 [(set (match_operand:XF 0 "register_operand" "=f,f")
16903 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
16904 [(reg 17) (const_int 0)])
16905 (match_operand:XF 2 "register_operand" "f,0")
16906 (match_operand:XF 3 "register_operand" "0,f")))]
16907 "!TARGET_64BIT && TARGET_CMOVE"
16909 fcmov%F1\t{%2, %0|%0, %2}
16910 fcmov%f1\t{%3, %0|%0, %3}"
16911 [(set_attr "type" "fcmov")
16912 (set_attr "mode" "XF")])
16914 (define_insn "*movtfcc_1"
16915 [(set (match_operand:TF 0 "register_operand" "=f,f")
16916 (if_then_else:TF (match_operator 1 "fcmov_comparison_operator"
16917 [(reg 17) (const_int 0)])
16918 (match_operand:TF 2 "register_operand" "f,0")
16919 (match_operand:TF 3 "register_operand" "0,f")))]
16922 fcmov%F1\t{%2, %0|%0, %2}
16923 fcmov%f1\t{%3, %0|%0, %3}"
16924 [(set_attr "type" "fcmov")
16925 (set_attr "mode" "XF")])
16927 (define_expand "minsf3"
16929 (set (match_operand:SF 0 "register_operand" "")
16930 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16931 (match_operand:SF 2 "nonimmediate_operand" ""))
16934 (clobber (reg:CC 17))])]
16938 (define_insn "*minsf"
16939 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
16940 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
16941 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
16944 (clobber (reg:CC 17))]
16945 "TARGET_SSE && TARGET_IEEE_FP"
16948 (define_insn "*minsf_nonieee"
16949 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
16950 (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
16951 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
16954 (clobber (reg:CC 17))]
16955 "TARGET_SSE && !TARGET_IEEE_FP
16956 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16960 [(set (match_operand:SF 0 "register_operand" "")
16961 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16962 (match_operand:SF 2 "nonimmediate_operand" ""))
16963 (match_operand:SF 3 "register_operand" "")
16964 (match_operand:SF 4 "nonimmediate_operand" "")))
16965 (clobber (reg:CC 17))]
16966 "SSE_REG_P (operands[0]) && reload_completed
16967 && ((operands_match_p (operands[1], operands[3])
16968 && operands_match_p (operands[2], operands[4]))
16969 || (operands_match_p (operands[1], operands[4])
16970 && operands_match_p (operands[2], operands[3])))"
16971 [(set (match_dup 0)
16972 (if_then_else:SF (lt (match_dup 1)
16977 ;; Conditional addition patterns
16978 (define_expand "addqicc"
16979 [(match_operand:QI 0 "register_operand" "")
16980 (match_operand 1 "comparison_operator" "")
16981 (match_operand:QI 2 "register_operand" "")
16982 (match_operand:QI 3 "const_int_operand" "")]
16984 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
16986 (define_expand "addhicc"
16987 [(match_operand:HI 0 "register_operand" "")
16988 (match_operand 1 "comparison_operator" "")
16989 (match_operand:HI 2 "register_operand" "")
16990 (match_operand:HI 3 "const_int_operand" "")]
16992 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
16994 (define_expand "addsicc"
16995 [(match_operand:SI 0 "register_operand" "")
16996 (match_operand 1 "comparison_operator" "")
16997 (match_operand:SI 2 "register_operand" "")
16998 (match_operand:SI 3 "const_int_operand" "")]
17000 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17002 (define_expand "adddicc"
17003 [(match_operand:DI 0 "register_operand" "")
17004 (match_operand 1 "comparison_operator" "")
17005 (match_operand:DI 2 "register_operand" "")
17006 (match_operand:DI 3 "const_int_operand" "")]
17008 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17010 ;; We can't represent the LT test directly. Do this by swapping the operands.
17013 [(set (match_operand:SF 0 "fp_register_operand" "")
17014 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
17015 (match_operand:SF 2 "register_operand" ""))
17016 (match_operand:SF 3 "register_operand" "")
17017 (match_operand:SF 4 "register_operand" "")))
17018 (clobber (reg:CC 17))]
17020 && ((operands_match_p (operands[1], operands[3])
17021 && operands_match_p (operands[2], operands[4]))
17022 || (operands_match_p (operands[1], operands[4])
17023 && operands_match_p (operands[2], operands[3])))"
17024 [(set (reg:CCFP 17)
17025 (compare:CCFP (match_dup 2)
17028 (if_then_else:SF (ge (reg:CCFP 17) (const_int 0))
17032 (define_insn "*minsf_sse"
17033 [(set (match_operand:SF 0 "register_operand" "=x")
17034 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
17035 (match_operand:SF 2 "nonimmediate_operand" "xm"))
17038 "TARGET_SSE && reload_completed"
17039 "minss\t{%2, %0|%0, %2}"
17040 [(set_attr "type" "sse")
17041 (set_attr "mode" "SF")])
17043 (define_expand "mindf3"
17045 (set (match_operand:DF 0 "register_operand" "")
17046 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
17047 (match_operand:DF 2 "nonimmediate_operand" ""))
17050 (clobber (reg:CC 17))])]
17051 "TARGET_SSE2 && TARGET_SSE_MATH"
17054 (define_insn "*mindf"
17055 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
17056 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
17057 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
17060 (clobber (reg:CC 17))]
17061 "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
17064 (define_insn "*mindf_nonieee"
17065 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
17066 (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
17067 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
17070 (clobber (reg:CC 17))]
17071 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
17072 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17076 [(set (match_operand:DF 0 "register_operand" "")
17077 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
17078 (match_operand:DF 2 "nonimmediate_operand" ""))
17079 (match_operand:DF 3 "register_operand" "")
17080 (match_operand:DF 4 "nonimmediate_operand" "")))
17081 (clobber (reg:CC 17))]
17082 "SSE_REG_P (operands[0]) && reload_completed
17083 && ((operands_match_p (operands[1], operands[3])
17084 && operands_match_p (operands[2], operands[4]))
17085 || (operands_match_p (operands[1], operands[4])
17086 && operands_match_p (operands[2], operands[3])))"
17087 [(set (match_dup 0)
17088 (if_then_else:DF (lt (match_dup 1)
17093 ;; We can't represent the LT test directly. Do this by swapping the operands.
17095 [(set (match_operand:DF 0 "fp_register_operand" "")
17096 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
17097 (match_operand:DF 2 "register_operand" ""))
17098 (match_operand:DF 3 "register_operand" "")
17099 (match_operand:DF 4 "register_operand" "")))
17100 (clobber (reg:CC 17))]
17102 && ((operands_match_p (operands[1], operands[3])
17103 && operands_match_p (operands[2], operands[4]))
17104 || (operands_match_p (operands[1], operands[4])
17105 && operands_match_p (operands[2], operands[3])))"
17106 [(set (reg:CCFP 17)
17107 (compare:CCFP (match_dup 2)
17110 (if_then_else:DF (ge (reg:CCFP 17) (const_int 0))
17114 (define_insn "*mindf_sse"
17115 [(set (match_operand:DF 0 "register_operand" "=Y")
17116 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
17117 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
17120 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
17121 "minsd\t{%2, %0|%0, %2}"
17122 [(set_attr "type" "sse")
17123 (set_attr "mode" "DF")])
17125 (define_expand "maxsf3"
17127 (set (match_operand:SF 0 "register_operand" "")
17128 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
17129 (match_operand:SF 2 "nonimmediate_operand" ""))
17132 (clobber (reg:CC 17))])]
17136 (define_insn "*maxsf"
17137 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
17138 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
17139 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
17142 (clobber (reg:CC 17))]
17143 "TARGET_SSE && TARGET_IEEE_FP"
17146 (define_insn "*maxsf_nonieee"
17147 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
17148 (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
17149 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
17152 (clobber (reg:CC 17))]
17153 "TARGET_SSE && !TARGET_IEEE_FP
17154 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17158 [(set (match_operand:SF 0 "register_operand" "")
17159 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
17160 (match_operand:SF 2 "nonimmediate_operand" ""))
17161 (match_operand:SF 3 "register_operand" "")
17162 (match_operand:SF 4 "nonimmediate_operand" "")))
17163 (clobber (reg:CC 17))]
17164 "SSE_REG_P (operands[0]) && reload_completed
17165 && ((operands_match_p (operands[1], operands[3])
17166 && operands_match_p (operands[2], operands[4]))
17167 || (operands_match_p (operands[1], operands[4])
17168 && operands_match_p (operands[2], operands[3])))"
17169 [(set (match_dup 0)
17170 (if_then_else:SF (gt (match_dup 1)
17176 [(set (match_operand:SF 0 "fp_register_operand" "")
17177 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
17178 (match_operand:SF 2 "register_operand" ""))
17179 (match_operand:SF 3 "register_operand" "")
17180 (match_operand:SF 4 "register_operand" "")))
17181 (clobber (reg:CC 17))]
17183 && ((operands_match_p (operands[1], operands[3])
17184 && operands_match_p (operands[2], operands[4]))
17185 || (operands_match_p (operands[1], operands[4])
17186 && operands_match_p (operands[2], operands[3])))"
17187 [(set (reg:CCFP 17)
17188 (compare:CCFP (match_dup 1)
17191 (if_then_else:SF (gt (reg:CCFP 17) (const_int 0))
17195 (define_insn "*maxsf_sse"
17196 [(set (match_operand:SF 0 "register_operand" "=x")
17197 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
17198 (match_operand:SF 2 "nonimmediate_operand" "xm"))
17201 "TARGET_SSE && reload_completed"
17202 "maxss\t{%2, %0|%0, %2}"
17203 [(set_attr "type" "sse")
17204 (set_attr "mode" "SF")])
17206 (define_expand "maxdf3"
17208 (set (match_operand:DF 0 "register_operand" "")
17209 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
17210 (match_operand:DF 2 "nonimmediate_operand" ""))
17213 (clobber (reg:CC 17))])]
17214 "TARGET_SSE2 && TARGET_SSE_MATH"
17217 (define_insn "*maxdf"
17218 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
17219 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
17220 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
17223 (clobber (reg:CC 17))]
17224 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
17227 (define_insn "*maxdf_nonieee"
17228 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
17229 (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
17230 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
17233 (clobber (reg:CC 17))]
17234 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
17235 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17239 [(set (match_operand:DF 0 "register_operand" "")
17240 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
17241 (match_operand:DF 2 "nonimmediate_operand" ""))
17242 (match_operand:DF 3 "register_operand" "")
17243 (match_operand:DF 4 "nonimmediate_operand" "")))
17244 (clobber (reg:CC 17))]
17245 "SSE_REG_P (operands[0]) && reload_completed
17246 && ((operands_match_p (operands[1], operands[3])
17247 && operands_match_p (operands[2], operands[4]))
17248 || (operands_match_p (operands[1], operands[4])
17249 && operands_match_p (operands[2], operands[3])))"
17250 [(set (match_dup 0)
17251 (if_then_else:DF (gt (match_dup 1)
17257 [(set (match_operand:DF 0 "fp_register_operand" "")
17258 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
17259 (match_operand:DF 2 "register_operand" ""))
17260 (match_operand:DF 3 "register_operand" "")
17261 (match_operand:DF 4 "register_operand" "")))
17262 (clobber (reg:CC 17))]
17264 && ((operands_match_p (operands[1], operands[3])
17265 && operands_match_p (operands[2], operands[4]))
17266 || (operands_match_p (operands[1], operands[4])
17267 && operands_match_p (operands[2], operands[3])))"
17268 [(set (reg:CCFP 17)
17269 (compare:CCFP (match_dup 1)
17272 (if_then_else:DF (gt (reg:CCFP 17) (const_int 0))
17276 (define_insn "*maxdf_sse"
17277 [(set (match_operand:DF 0 "register_operand" "=Y")
17278 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
17279 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
17282 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
17283 "maxsd\t{%2, %0|%0, %2}"
17284 [(set_attr "type" "sse")
17285 (set_attr "mode" "DF")])
17287 ;; Misc patterns (?)
17289 ;; This pattern exists to put a dependency on all ebp-based memory accesses.
17290 ;; Otherwise there will be nothing to keep
17292 ;; [(set (reg ebp) (reg esp))]
17293 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
17294 ;; (clobber (eflags)]
17295 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
17297 ;; in proper program order.
17298 (define_expand "pro_epilogue_adjust_stack"
17299 [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r")
17300 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
17301 (match_operand:SI 2 "immediate_operand" "i,i")))
17302 (clobber (reg:CC 17))
17303 (clobber (mem:BLK (scratch)))])]
17308 emit_insn (gen_pro_epilogue_adjust_stack_rex64
17309 (operands[0], operands[1], operands[2]));
17314 (define_insn "*pro_epilogue_adjust_stack_1"
17315 [(set (match_operand:SI 0 "register_operand" "=r,r")
17316 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
17317 (match_operand:SI 2 "immediate_operand" "i,i")))
17318 (clobber (reg:CC 17))
17319 (clobber (mem:BLK (scratch)))]
17322 switch (get_attr_type (insn))
17325 return "mov{l}\t{%1, %0|%0, %1}";
17328 if (GET_CODE (operands[2]) == CONST_INT
17329 && (INTVAL (operands[2]) == 128
17330 || (INTVAL (operands[2]) < 0
17331 && INTVAL (operands[2]) != -128)))
17333 operands[2] = GEN_INT (-INTVAL (operands[2]));
17334 return "sub{l}\t{%2, %0|%0, %2}";
17336 return "add{l}\t{%2, %0|%0, %2}";
17339 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
17340 return "lea{l}\t{%a2, %0|%0, %a2}";
17346 [(set (attr "type")
17347 (cond [(eq_attr "alternative" "0")
17348 (const_string "alu")
17349 (match_operand:SI 2 "const0_operand" "")
17350 (const_string "imov")
17352 (const_string "lea")))
17353 (set_attr "mode" "SI")])
17355 (define_insn "pro_epilogue_adjust_stack_rex64"
17356 [(set (match_operand:DI 0 "register_operand" "=r,r")
17357 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
17358 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
17359 (clobber (reg:CC 17))
17360 (clobber (mem:BLK (scratch)))]
17363 switch (get_attr_type (insn))
17366 return "mov{q}\t{%1, %0|%0, %1}";
17369 if (GET_CODE (operands[2]) == CONST_INT
17370 && (INTVAL (operands[2]) == 128
17371 || (INTVAL (operands[2]) < 0
17372 && INTVAL (operands[2]) != -128)))
17374 operands[2] = GEN_INT (-INTVAL (operands[2]));
17375 return "sub{q}\t{%2, %0|%0, %2}";
17377 return "add{q}\t{%2, %0|%0, %2}";
17380 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
17381 return "lea{q}\t{%a2, %0|%0, %a2}";
17387 [(set (attr "type")
17388 (cond [(eq_attr "alternative" "0")
17389 (const_string "alu")
17390 (match_operand:DI 2 "const0_operand" "")
17391 (const_string "imov")
17393 (const_string "lea")))
17394 (set_attr "mode" "DI")])
17397 ;; Placeholder for the conditional moves. This one is split either to SSE
17398 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
17399 ;; fact is that compares supported by the cmp??ss instructions are exactly
17400 ;; swapped of those supported by cmove sequence.
17401 ;; The EQ/NE comparisons also needs bit care, since they are not directly
17402 ;; supported by i387 comparisons and we do need to emit two conditional moves
17405 (define_insn "sse_movsfcc"
17406 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
17407 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
17408 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
17409 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
17410 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
17411 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
17412 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
17413 (clobber (reg:CC 17))]
17415 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
17416 /* Avoid combine from being smart and converting min/max
17417 instruction patterns into conditional moves. */
17418 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
17419 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
17420 || !rtx_equal_p (operands[4], operands[2])
17421 || !rtx_equal_p (operands[5], operands[3]))
17422 && (!TARGET_IEEE_FP
17423 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
17426 (define_insn "sse_movsfcc_eq"
17427 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
17428 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
17429 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
17430 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
17431 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
17432 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
17433 (clobber (reg:CC 17))]
17435 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17438 (define_insn "sse_movdfcc"
17439 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?f#Yr,?f#Yr,?r#Yf,?r#Yf,?r#Yf,?r#Yf")
17440 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
17441 [(match_operand:DF 4 "nonimmediate_operand" "0#fY,Y#fY,f#Y,f#Y,Ym#f,Ym#f,f#Y,f#Y,Ym#f,Ym#f")
17442 (match_operand:DF 5 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,f#Y,Y#f,Y#f,f#Y,f#Y,Y#f,Y#f")])
17443 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY")
17444 (match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY")))
17445 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
17446 (clobber (reg:CC 17))]
17448 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
17449 /* Avoid combine from being smart and converting min/max
17450 instruction patterns into conditional moves. */
17451 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
17452 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
17453 || !rtx_equal_p (operands[4], operands[2])
17454 || !rtx_equal_p (operands[5], operands[3]))
17455 && (!TARGET_IEEE_FP
17456 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
17459 (define_insn "sse_movdfcc_eq"
17460 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?r#Yf,?r#Yf")
17461 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fY,Y#fY,f#Y,Ym#f,f#Y,Ym#f")
17462 (match_operand:DF 4 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,Y#f,f#Y,Y#f"))
17463 (match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY")
17464 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY")))
17465 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
17466 (clobber (reg:CC 17))]
17468 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17471 ;; For non-sse moves just expand the usual cmove sequence.
17473 [(set (match_operand 0 "register_operand" "")
17474 (if_then_else (match_operator 1 "comparison_operator"
17475 [(match_operand 4 "nonimmediate_operand" "")
17476 (match_operand 5 "register_operand" "")])
17477 (match_operand 2 "nonimmediate_operand" "")
17478 (match_operand 3 "nonimmediate_operand" "")))
17479 (clobber (match_operand 6 "" ""))
17480 (clobber (reg:CC 17))]
17481 "!SSE_REG_P (operands[0]) && reload_completed
17482 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
17485 ix86_compare_op0 = operands[5];
17486 ix86_compare_op1 = operands[4];
17487 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
17488 VOIDmode, operands[5], operands[4]);
17489 ix86_expand_fp_movcc (operands);
17493 ;; Split SSE based conditional move into sequence:
17494 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
17495 ;; and op2, op0 - zero op2 if comparison was false
17496 ;; nand op0, op3 - load op3 to op0 if comparison was false
17497 ;; or op2, op0 - get the nonzero one into the result.
17499 [(set (match_operand 0 "register_operand" "")
17500 (if_then_else (match_operator 1 "sse_comparison_operator"
17501 [(match_operand 4 "register_operand" "")
17502 (match_operand 5 "nonimmediate_operand" "")])
17503 (match_operand 2 "register_operand" "")
17504 (match_operand 3 "register_operand" "")))
17505 (clobber (match_operand 6 "" ""))
17506 (clobber (reg:CC 17))]
17507 "SSE_REG_P (operands[0]) && reload_completed"
17508 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
17509 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
17510 (subreg:TI (match_dup 4) 0)))
17511 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0))
17512 (subreg:TI (match_dup 3) 0)))
17513 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
17514 (subreg:TI (match_dup 7) 0)))]
17516 if (GET_MODE (operands[2]) == DFmode
17517 && TARGET_SSE_PARTIAL_REGS && !optimize_size)
17519 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
17520 emit_insn (gen_sse2_unpcklpd (op, op, op));
17521 op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
17522 emit_insn (gen_sse2_unpcklpd (op, op, op));
17525 /* If op2 == op3, op3 would be clobbered before it is used. */
17526 if (operands_match_p (operands[2], operands[3]))
17528 emit_move_insn (operands[0], operands[2]);
17532 PUT_MODE (operands[1], GET_MODE (operands[0]));
17533 if (operands_match_p (operands[0], operands[4]))
17534 operands[6] = operands[4], operands[7] = operands[2];
17536 operands[6] = operands[2], operands[7] = operands[4];
17539 ;; Special case of conditional move we can handle effectively.
17540 ;; Do not brother with the integer/floating point case, since these are
17541 ;; bot considerably slower, unlike in the generic case.
17542 (define_insn "*sse_movsfcc_const0_1"
17543 [(set (match_operand:SF 0 "register_operand" "=&x")
17544 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
17545 [(match_operand:SF 4 "register_operand" "0")
17546 (match_operand:SF 5 "nonimmediate_operand" "xm")])
17547 (match_operand:SF 2 "register_operand" "x")
17548 (match_operand:SF 3 "const0_operand" "X")))]
17552 (define_insn "*sse_movsfcc_const0_2"
17553 [(set (match_operand:SF 0 "register_operand" "=&x")
17554 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
17555 [(match_operand:SF 4 "register_operand" "0")
17556 (match_operand:SF 5 "nonimmediate_operand" "xm")])
17557 (match_operand:SF 2 "const0_operand" "X")
17558 (match_operand:SF 3 "register_operand" "x")))]
17562 (define_insn "*sse_movsfcc_const0_3"
17563 [(set (match_operand:SF 0 "register_operand" "=&x")
17564 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
17565 [(match_operand:SF 4 "nonimmediate_operand" "xm")
17566 (match_operand:SF 5 "register_operand" "0")])
17567 (match_operand:SF 2 "register_operand" "x")
17568 (match_operand:SF 3 "const0_operand" "X")))]
17572 (define_insn "*sse_movsfcc_const0_4"
17573 [(set (match_operand:SF 0 "register_operand" "=&x")
17574 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
17575 [(match_operand:SF 4 "nonimmediate_operand" "xm")
17576 (match_operand:SF 5 "register_operand" "0")])
17577 (match_operand:SF 2 "const0_operand" "X")
17578 (match_operand:SF 3 "register_operand" "x")))]
17582 (define_insn "*sse_movdfcc_const0_1"
17583 [(set (match_operand:DF 0 "register_operand" "=&Y")
17584 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
17585 [(match_operand:DF 4 "register_operand" "0")
17586 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
17587 (match_operand:DF 2 "register_operand" "Y")
17588 (match_operand:DF 3 "const0_operand" "X")))]
17592 (define_insn "*sse_movdfcc_const0_2"
17593 [(set (match_operand:DF 0 "register_operand" "=&Y")
17594 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
17595 [(match_operand:DF 4 "register_operand" "0")
17596 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
17597 (match_operand:DF 2 "const0_operand" "X")
17598 (match_operand:DF 3 "register_operand" "Y")))]
17602 (define_insn "*sse_movdfcc_const0_3"
17603 [(set (match_operand:DF 0 "register_operand" "=&Y")
17604 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17605 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
17606 (match_operand:DF 5 "register_operand" "0")])
17607 (match_operand:DF 2 "register_operand" "Y")
17608 (match_operand:DF 3 "const0_operand" "X")))]
17612 (define_insn "*sse_movdfcc_const0_4"
17613 [(set (match_operand:DF 0 "register_operand" "=&Y")
17614 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17615 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
17616 (match_operand:DF 5 "register_operand" "0")])
17617 (match_operand:DF 2 "const0_operand" "X")
17618 (match_operand:DF 3 "register_operand" "Y")))]
17623 [(set (match_operand 0 "register_operand" "")
17624 (if_then_else (match_operator 1 "comparison_operator"
17625 [(match_operand 4 "nonimmediate_operand" "")
17626 (match_operand 5 "nonimmediate_operand" "")])
17627 (match_operand 2 "nonmemory_operand" "")
17628 (match_operand 3 "nonmemory_operand" "")))]
17629 "SSE_REG_P (operands[0]) && reload_completed
17630 && (const0_operand (operands[2], GET_MODE (operands[0]))
17631 || const0_operand (operands[3], GET_MODE (operands[0])))"
17632 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
17633 (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
17636 if (TARGET_SSE_PARTIAL_REGS && !optimize_size
17637 && GET_MODE (operands[2]) == DFmode)
17639 if (REG_P (operands[2]))
17641 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
17642 emit_insn (gen_sse2_unpcklpd (op, op, op));
17644 if (REG_P (operands[3]))
17646 rtx op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
17647 emit_insn (gen_sse2_unpcklpd (op, op, op));
17650 PUT_MODE (operands[1], GET_MODE (operands[0]));
17651 if (!sse_comparison_operator (operands[1], VOIDmode)
17652 || !rtx_equal_p (operands[0], operands[4]))
17654 rtx tmp = operands[5];
17655 operands[5] = operands[4];
17657 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
17659 if (!rtx_equal_p (operands[0], operands[4]))
17661 if (const0_operand (operands[2], GET_MODE (operands[0])))
17663 operands[7] = operands[3];
17664 operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
17669 operands[7] = operands[2];
17670 operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
17672 operands[7] = simplify_gen_subreg (TImode, operands[7],
17673 GET_MODE (operands[7]), 0);
17676 (define_expand "allocate_stack_worker"
17677 [(match_operand:SI 0 "register_operand" "")]
17678 "TARGET_STACK_PROBE"
17681 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
17683 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
17687 (define_insn "allocate_stack_worker_1"
17688 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
17689 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
17690 (clobber (match_dup 0))
17691 (clobber (reg:CC 17))]
17692 "!TARGET_64BIT && TARGET_STACK_PROBE"
17694 [(set_attr "type" "multi")
17695 (set_attr "length" "5")])
17697 (define_insn "allocate_stack_worker_rex64"
17698 [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
17699 (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
17700 (clobber (match_dup 0))
17701 (clobber (reg:CC 17))]
17702 "TARGET_64BIT && TARGET_STACK_PROBE"
17704 [(set_attr "type" "multi")
17705 (set_attr "length" "5")])
17707 (define_expand "allocate_stack"
17708 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
17709 (minus:SI (reg:SI 7)
17710 (match_operand:SI 1 "general_operand" "")))
17711 (clobber (reg:CC 17))])
17712 (parallel [(set (reg:SI 7)
17713 (minus:SI (reg:SI 7) (match_dup 1)))
17714 (clobber (reg:CC 17))])]
17715 "TARGET_STACK_PROBE"
17717 #ifdef CHECK_STACK_LIMIT
17718 if (GET_CODE (operands[1]) == CONST_INT
17719 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
17720 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
17724 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
17727 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
17731 (define_expand "builtin_setjmp_receiver"
17732 [(label_ref (match_operand 0 "" ""))]
17733 "!TARGET_64BIT && flag_pic"
17735 emit_insn (gen_set_got (pic_offset_table_rtx));
17739 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
17742 [(set (match_operand 0 "register_operand" "")
17743 (match_operator 3 "promotable_binary_operator"
17744 [(match_operand 1 "register_operand" "")
17745 (match_operand 2 "aligned_operand" "")]))
17746 (clobber (reg:CC 17))]
17747 "! TARGET_PARTIAL_REG_STALL && reload_completed
17748 && ((GET_MODE (operands[0]) == HImode
17749 && ((!optimize_size && !TARGET_FAST_PREFIX)
17750 || GET_CODE (operands[2]) != CONST_INT
17751 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
17752 || (GET_MODE (operands[0]) == QImode
17753 && (TARGET_PROMOTE_QImode || optimize_size)))"
17754 [(parallel [(set (match_dup 0)
17755 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
17756 (clobber (reg:CC 17))])]
17757 "operands[0] = gen_lowpart (SImode, operands[0]);
17758 operands[1] = gen_lowpart (SImode, operands[1]);
17759 if (GET_CODE (operands[3]) != ASHIFT)
17760 operands[2] = gen_lowpart (SImode, operands[2]);
17761 PUT_MODE (operands[3], SImode);")
17763 ; Promote the QImode tests, as i386 has encoding of the AND
17764 ; instruction with 32-bit sign-extended immediate and thus the
17765 ; instruction size is unchanged, except in the %eax case for
17766 ; which it is increased by one byte, hence the ! optimize_size.
17769 (compare (and (match_operand 1 "aligned_operand" "")
17770 (match_operand 2 "const_int_operand" ""))
17772 (set (match_operand 0 "register_operand" "")
17773 (and (match_dup 1) (match_dup 2)))]
17774 "! TARGET_PARTIAL_REG_STALL && reload_completed
17775 /* Ensure that the operand will remain sign-extended immediate. */
17776 && ix86_match_ccmode (insn, INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode)
17778 && ((GET_MODE (operands[0]) == HImode && ! TARGET_FAST_PREFIX)
17779 || (GET_MODE (operands[0]) == QImode && TARGET_PROMOTE_QImode))"
17780 [(parallel [(set (reg:CCNO 17)
17781 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
17784 (and:SI (match_dup 1) (match_dup 2)))])]
17786 = gen_int_mode (INTVAL (operands[2])
17787 & GET_MODE_MASK (GET_MODE (operands[0])),
17789 operands[0] = gen_lowpart (SImode, operands[0]);
17790 operands[1] = gen_lowpart (SImode, operands[1]);")
17792 ; Don't promote the QImode tests, as i386 doesn't have encoding of
17793 ; the TEST instruction with 32-bit sign-extended immediate and thus
17794 ; the instruction size would at least double, which is not what we
17795 ; want even with ! optimize_size.
17798 (compare (and (match_operand:HI 0 "aligned_operand" "")
17799 (match_operand:HI 1 "const_int_operand" ""))
17801 "! TARGET_PARTIAL_REG_STALL && reload_completed
17802 /* Ensure that the operand will remain sign-extended immediate. */
17803 && ix86_match_ccmode (insn, INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode)
17804 && ! TARGET_FAST_PREFIX
17805 && ! optimize_size"
17806 [(set (reg:CCNO 17)
17807 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
17810 = gen_int_mode (INTVAL (operands[1])
17811 & GET_MODE_MASK (GET_MODE (operands[0])),
17813 operands[0] = gen_lowpart (SImode, operands[0]);")
17816 [(set (match_operand 0 "register_operand" "")
17817 (neg (match_operand 1 "register_operand" "")))
17818 (clobber (reg:CC 17))]
17819 "! TARGET_PARTIAL_REG_STALL && reload_completed
17820 && (GET_MODE (operands[0]) == HImode
17821 || (GET_MODE (operands[0]) == QImode
17822 && (TARGET_PROMOTE_QImode || optimize_size)))"
17823 [(parallel [(set (match_dup 0)
17824 (neg:SI (match_dup 1)))
17825 (clobber (reg:CC 17))])]
17826 "operands[0] = gen_lowpart (SImode, operands[0]);
17827 operands[1] = gen_lowpart (SImode, operands[1]);")
17830 [(set (match_operand 0 "register_operand" "")
17831 (not (match_operand 1 "register_operand" "")))]
17832 "! TARGET_PARTIAL_REG_STALL && reload_completed
17833 && (GET_MODE (operands[0]) == HImode
17834 || (GET_MODE (operands[0]) == QImode
17835 && (TARGET_PROMOTE_QImode || optimize_size)))"
17836 [(set (match_dup 0)
17837 (not:SI (match_dup 1)))]
17838 "operands[0] = gen_lowpart (SImode, operands[0]);
17839 operands[1] = gen_lowpart (SImode, operands[1]);")
17842 [(set (match_operand 0 "register_operand" "")
17843 (if_then_else (match_operator 1 "comparison_operator"
17844 [(reg 17) (const_int 0)])
17845 (match_operand 2 "register_operand" "")
17846 (match_operand 3 "register_operand" "")))]
17847 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
17848 && (GET_MODE (operands[0]) == HImode
17849 || (GET_MODE (operands[0]) == QImode
17850 && (TARGET_PROMOTE_QImode || optimize_size)))"
17851 [(set (match_dup 0)
17852 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
17853 "operands[0] = gen_lowpart (SImode, operands[0]);
17854 operands[2] = gen_lowpart (SImode, operands[2]);
17855 operands[3] = gen_lowpart (SImode, operands[3]);")
17858 ;; RTL Peephole optimizations, run before sched2. These primarily look to
17859 ;; transform a complex memory operation into two memory to register operations.
17861 ;; Don't push memory operands
17863 [(set (match_operand:SI 0 "push_operand" "")
17864 (match_operand:SI 1 "memory_operand" ""))
17865 (match_scratch:SI 2 "r")]
17866 "! optimize_size && ! TARGET_PUSH_MEMORY"
17867 [(set (match_dup 2) (match_dup 1))
17868 (set (match_dup 0) (match_dup 2))]
17872 [(set (match_operand:DI 0 "push_operand" "")
17873 (match_operand:DI 1 "memory_operand" ""))
17874 (match_scratch:DI 2 "r")]
17875 "! optimize_size && ! TARGET_PUSH_MEMORY"
17876 [(set (match_dup 2) (match_dup 1))
17877 (set (match_dup 0) (match_dup 2))]
17880 ;; We need to handle SFmode only, because DFmode and XFmode is split to
17883 [(set (match_operand:SF 0 "push_operand" "")
17884 (match_operand:SF 1 "memory_operand" ""))
17885 (match_scratch:SF 2 "r")]
17886 "! optimize_size && ! TARGET_PUSH_MEMORY"
17887 [(set (match_dup 2) (match_dup 1))
17888 (set (match_dup 0) (match_dup 2))]
17892 [(set (match_operand:HI 0 "push_operand" "")
17893 (match_operand:HI 1 "memory_operand" ""))
17894 (match_scratch:HI 2 "r")]
17895 "! optimize_size && ! TARGET_PUSH_MEMORY"
17896 [(set (match_dup 2) (match_dup 1))
17897 (set (match_dup 0) (match_dup 2))]
17901 [(set (match_operand:QI 0 "push_operand" "")
17902 (match_operand:QI 1 "memory_operand" ""))
17903 (match_scratch:QI 2 "q")]
17904 "! optimize_size && ! TARGET_PUSH_MEMORY"
17905 [(set (match_dup 2) (match_dup 1))
17906 (set (match_dup 0) (match_dup 2))]
17909 ;; Don't move an immediate directly to memory when the instruction
17912 [(match_scratch:SI 1 "r")
17913 (set (match_operand:SI 0 "memory_operand" "")
17916 && ! TARGET_USE_MOV0
17917 && TARGET_SPLIT_LONG_MOVES
17918 && get_attr_length (insn) >= ix86_cost->large_insn
17919 && peep2_regno_dead_p (0, FLAGS_REG)"
17920 [(parallel [(set (match_dup 1) (const_int 0))
17921 (clobber (reg:CC 17))])
17922 (set (match_dup 0) (match_dup 1))]
17926 [(match_scratch:HI 1 "r")
17927 (set (match_operand:HI 0 "memory_operand" "")
17930 && ! TARGET_USE_MOV0
17931 && TARGET_SPLIT_LONG_MOVES
17932 && get_attr_length (insn) >= ix86_cost->large_insn
17933 && peep2_regno_dead_p (0, FLAGS_REG)"
17934 [(parallel [(set (match_dup 2) (const_int 0))
17935 (clobber (reg:CC 17))])
17936 (set (match_dup 0) (match_dup 1))]
17937 "operands[2] = gen_lowpart (SImode, operands[1]);")
17940 [(match_scratch:QI 1 "q")
17941 (set (match_operand:QI 0 "memory_operand" "")
17944 && ! TARGET_USE_MOV0
17945 && TARGET_SPLIT_LONG_MOVES
17946 && get_attr_length (insn) >= ix86_cost->large_insn
17947 && peep2_regno_dead_p (0, FLAGS_REG)"
17948 [(parallel [(set (match_dup 2) (const_int 0))
17949 (clobber (reg:CC 17))])
17950 (set (match_dup 0) (match_dup 1))]
17951 "operands[2] = gen_lowpart (SImode, operands[1]);")
17954 [(match_scratch:SI 2 "r")
17955 (set (match_operand:SI 0 "memory_operand" "")
17956 (match_operand:SI 1 "immediate_operand" ""))]
17958 && get_attr_length (insn) >= ix86_cost->large_insn
17959 && TARGET_SPLIT_LONG_MOVES"
17960 [(set (match_dup 2) (match_dup 1))
17961 (set (match_dup 0) (match_dup 2))]
17965 [(match_scratch:HI 2 "r")
17966 (set (match_operand:HI 0 "memory_operand" "")
17967 (match_operand:HI 1 "immediate_operand" ""))]
17968 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
17969 && TARGET_SPLIT_LONG_MOVES"
17970 [(set (match_dup 2) (match_dup 1))
17971 (set (match_dup 0) (match_dup 2))]
17975 [(match_scratch:QI 2 "q")
17976 (set (match_operand:QI 0 "memory_operand" "")
17977 (match_operand:QI 1 "immediate_operand" ""))]
17978 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
17979 && TARGET_SPLIT_LONG_MOVES"
17980 [(set (match_dup 2) (match_dup 1))
17981 (set (match_dup 0) (match_dup 2))]
17984 ;; Don't compare memory with zero, load and use a test instead.
17987 (compare (match_operand:SI 0 "memory_operand" "")
17989 (match_scratch:SI 3 "r")]
17990 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
17991 [(set (match_dup 3) (match_dup 0))
17992 (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
17995 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
17996 ;; Don't split NOTs with a displacement operand, because resulting XOR
17997 ;; will not be pairable anyway.
17999 ;; On AMD K6, NOT is vector decoded with memory operand that can not be
18000 ;; represented using a modRM byte. The XOR replacement is long decoded,
18001 ;; so this split helps here as well.
18003 ;; Note: Can't do this as a regular split because we can't get proper
18004 ;; lifetime information then.
18007 [(set (match_operand:SI 0 "nonimmediate_operand" "")
18008 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
18010 && peep2_regno_dead_p (0, FLAGS_REG)
18011 && ((TARGET_PENTIUM
18012 && (GET_CODE (operands[0]) != MEM
18013 || !memory_displacement_operand (operands[0], SImode)))
18014 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
18015 [(parallel [(set (match_dup 0)
18016 (xor:SI (match_dup 1) (const_int -1)))
18017 (clobber (reg:CC 17))])]
18021 [(set (match_operand:HI 0 "nonimmediate_operand" "")
18022 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
18024 && peep2_regno_dead_p (0, FLAGS_REG)
18025 && ((TARGET_PENTIUM
18026 && (GET_CODE (operands[0]) != MEM
18027 || !memory_displacement_operand (operands[0], HImode)))
18028 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
18029 [(parallel [(set (match_dup 0)
18030 (xor:HI (match_dup 1) (const_int -1)))
18031 (clobber (reg:CC 17))])]
18035 [(set (match_operand:QI 0 "nonimmediate_operand" "")
18036 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
18038 && peep2_regno_dead_p (0, FLAGS_REG)
18039 && ((TARGET_PENTIUM
18040 && (GET_CODE (operands[0]) != MEM
18041 || !memory_displacement_operand (operands[0], QImode)))
18042 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
18043 [(parallel [(set (match_dup 0)
18044 (xor:QI (match_dup 1) (const_int -1)))
18045 (clobber (reg:CC 17))])]
18048 ;; Non pairable "test imm, reg" instructions can be translated to
18049 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
18050 ;; byte opcode instead of two, have a short form for byte operands),
18051 ;; so do it for other CPUs as well. Given that the value was dead,
18052 ;; this should not create any new dependencies. Pass on the sub-word
18053 ;; versions if we're concerned about partial register stalls.
18057 (compare (and:SI (match_operand:SI 0 "register_operand" "")
18058 (match_operand:SI 1 "immediate_operand" ""))
18060 "ix86_match_ccmode (insn, CCNOmode)
18061 && (true_regnum (operands[0]) != 0
18062 || (GET_CODE (operands[1]) == CONST_INT
18063 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')))
18064 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18066 [(set (reg:CCNO 17)
18067 (compare:CCNO (and:SI (match_dup 0)
18071 (and:SI (match_dup 0) (match_dup 1)))])]
18074 ;; We don't need to handle HImode case, because it will be promoted to SImode
18075 ;; on ! TARGET_PARTIAL_REG_STALL
18079 (compare (and:QI (match_operand:QI 0 "register_operand" "")
18080 (match_operand:QI 1 "immediate_operand" ""))
18082 "! TARGET_PARTIAL_REG_STALL
18083 && ix86_match_ccmode (insn, CCNOmode)
18084 && true_regnum (operands[0]) != 0
18085 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18087 [(set (reg:CCNO 17)
18088 (compare:CCNO (and:QI (match_dup 0)
18092 (and:QI (match_dup 0) (match_dup 1)))])]
18100 (match_operand 0 "ext_register_operand" "")
18103 (match_operand 1 "const_int_operand" ""))
18105 "! TARGET_PARTIAL_REG_STALL
18106 && ix86_match_ccmode (insn, CCNOmode)
18107 && true_regnum (operands[0]) != 0
18108 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18109 [(parallel [(set (reg:CCNO 17)
18118 (set (zero_extract:SI (match_dup 0)
18129 ;; Don't do logical operations with memory inputs.
18131 [(match_scratch:SI 2 "r")
18132 (parallel [(set (match_operand:SI 0 "register_operand" "")
18133 (match_operator:SI 3 "arith_or_logical_operator"
18135 (match_operand:SI 1 "memory_operand" "")]))
18136 (clobber (reg:CC 17))])]
18137 "! optimize_size && ! TARGET_READ_MODIFY"
18138 [(set (match_dup 2) (match_dup 1))
18139 (parallel [(set (match_dup 0)
18140 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
18141 (clobber (reg:CC 17))])]
18145 [(match_scratch:SI 2 "r")
18146 (parallel [(set (match_operand:SI 0 "register_operand" "")
18147 (match_operator:SI 3 "arith_or_logical_operator"
18148 [(match_operand:SI 1 "memory_operand" "")
18150 (clobber (reg:CC 17))])]
18151 "! optimize_size && ! TARGET_READ_MODIFY"
18152 [(set (match_dup 2) (match_dup 1))
18153 (parallel [(set (match_dup 0)
18154 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
18155 (clobber (reg:CC 17))])]
18158 ; Don't do logical operations with memory outputs
18160 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
18161 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
18162 ; the same decoder scheduling characteristics as the original.
18165 [(match_scratch:SI 2 "r")
18166 (parallel [(set (match_operand:SI 0 "memory_operand" "")
18167 (match_operator:SI 3 "arith_or_logical_operator"
18169 (match_operand:SI 1 "nonmemory_operand" "")]))
18170 (clobber (reg:CC 17))])]
18171 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
18172 [(set (match_dup 2) (match_dup 0))
18173 (parallel [(set (match_dup 2)
18174 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
18175 (clobber (reg:CC 17))])
18176 (set (match_dup 0) (match_dup 2))]
18180 [(match_scratch:SI 2 "r")
18181 (parallel [(set (match_operand:SI 0 "memory_operand" "")
18182 (match_operator:SI 3 "arith_or_logical_operator"
18183 [(match_operand:SI 1 "nonmemory_operand" "")
18185 (clobber (reg:CC 17))])]
18186 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
18187 [(set (match_dup 2) (match_dup 0))
18188 (parallel [(set (match_dup 2)
18189 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
18190 (clobber (reg:CC 17))])
18191 (set (match_dup 0) (match_dup 2))]
18194 ;; Attempt to always use XOR for zeroing registers.
18196 [(set (match_operand 0 "register_operand" "")
18198 "(GET_MODE (operands[0]) == QImode
18199 || GET_MODE (operands[0]) == HImode
18200 || GET_MODE (operands[0]) == SImode
18201 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
18202 && (! TARGET_USE_MOV0 || optimize_size)
18203 && peep2_regno_dead_p (0, FLAGS_REG)"
18204 [(parallel [(set (match_dup 0) (const_int 0))
18205 (clobber (reg:CC 17))])]
18206 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
18210 [(set (strict_low_part (match_operand 0 "register_operand" ""))
18212 "(GET_MODE (operands[0]) == QImode
18213 || GET_MODE (operands[0]) == HImode)
18214 && (! TARGET_USE_MOV0 || optimize_size)
18215 && peep2_regno_dead_p (0, FLAGS_REG)"
18216 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
18217 (clobber (reg:CC 17))])])
18219 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
18221 [(set (match_operand 0 "register_operand" "")
18223 "(GET_MODE (operands[0]) == HImode
18224 || GET_MODE (operands[0]) == SImode
18225 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
18226 && (optimize_size || TARGET_PENTIUM)
18227 && peep2_regno_dead_p (0, FLAGS_REG)"
18228 [(parallel [(set (match_dup 0) (const_int -1))
18229 (clobber (reg:CC 17))])]
18230 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
18233 ;; Attempt to convert simple leas to adds. These can be created by
18236 [(set (match_operand:SI 0 "register_operand" "")
18237 (plus:SI (match_dup 0)
18238 (match_operand:SI 1 "nonmemory_operand" "")))]
18239 "peep2_regno_dead_p (0, FLAGS_REG)"
18240 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
18241 (clobber (reg:CC 17))])]
18245 [(set (match_operand:SI 0 "register_operand" "")
18246 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
18247 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
18248 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
18249 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
18250 (clobber (reg:CC 17))])]
18251 "operands[2] = gen_lowpart (SImode, operands[2]);")
18254 [(set (match_operand:DI 0 "register_operand" "")
18255 (plus:DI (match_dup 0)
18256 (match_operand:DI 1 "x86_64_general_operand" "")))]
18257 "peep2_regno_dead_p (0, FLAGS_REG)"
18258 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
18259 (clobber (reg:CC 17))])]
18263 [(set (match_operand:SI 0 "register_operand" "")
18264 (mult:SI (match_dup 0)
18265 (match_operand:SI 1 "const_int_operand" "")))]
18266 "exact_log2 (INTVAL (operands[1])) >= 0
18267 && peep2_regno_dead_p (0, FLAGS_REG)"
18268 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
18269 (clobber (reg:CC 17))])]
18270 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
18273 [(set (match_operand:DI 0 "register_operand" "")
18274 (mult:DI (match_dup 0)
18275 (match_operand:DI 1 "const_int_operand" "")))]
18276 "exact_log2 (INTVAL (operands[1])) >= 0
18277 && peep2_regno_dead_p (0, FLAGS_REG)"
18278 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
18279 (clobber (reg:CC 17))])]
18280 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
18283 [(set (match_operand:SI 0 "register_operand" "")
18284 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
18285 (match_operand:DI 2 "const_int_operand" "")) 0))]
18286 "exact_log2 (INTVAL (operands[2])) >= 0
18287 && REGNO (operands[0]) == REGNO (operands[1])
18288 && peep2_regno_dead_p (0, FLAGS_REG)"
18289 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
18290 (clobber (reg:CC 17))])]
18291 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
18293 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
18294 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
18295 ;; many CPUs it is also faster, since special hardware to avoid esp
18296 ;; dependencies is present.
18298 ;; While some of these conversions may be done using splitters, we use peepholes
18299 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
18301 ;; Convert prologue esp subtractions to push.
18302 ;; We need register to push. In order to keep verify_flow_info happy we have
18304 ;; - use scratch and clobber it in order to avoid dependencies
18305 ;; - use already live register
18306 ;; We can't use the second way right now, since there is no reliable way how to
18307 ;; verify that given register is live. First choice will also most likely in
18308 ;; fewer dependencies. On the place of esp adjustments it is very likely that
18309 ;; call clobbered registers are dead. We may want to use base pointer as an
18310 ;; alternative when no register is available later.
18313 [(match_scratch:SI 0 "r")
18314 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
18315 (clobber (reg:CC 17))
18316 (clobber (mem:BLK (scratch)))])]
18317 "optimize_size || !TARGET_SUB_ESP_4"
18318 [(clobber (match_dup 0))
18319 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
18320 (clobber (mem:BLK (scratch)))])])
18323 [(match_scratch:SI 0 "r")
18324 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
18325 (clobber (reg:CC 17))
18326 (clobber (mem:BLK (scratch)))])]
18327 "optimize_size || !TARGET_SUB_ESP_8"
18328 [(clobber (match_dup 0))
18329 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
18330 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
18331 (clobber (mem:BLK (scratch)))])])
18333 ;; Convert esp subtractions to push.
18335 [(match_scratch:SI 0 "r")
18336 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
18337 (clobber (reg:CC 17))])]
18338 "optimize_size || !TARGET_SUB_ESP_4"
18339 [(clobber (match_dup 0))
18340 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
18343 [(match_scratch:SI 0 "r")
18344 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
18345 (clobber (reg:CC 17))])]
18346 "optimize_size || !TARGET_SUB_ESP_8"
18347 [(clobber (match_dup 0))
18348 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
18349 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
18351 ;; Convert epilogue deallocator to pop.
18353 [(match_scratch:SI 0 "r")
18354 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18355 (clobber (reg:CC 17))
18356 (clobber (mem:BLK (scratch)))])]
18357 "optimize_size || !TARGET_ADD_ESP_4"
18358 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18359 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18360 (clobber (mem:BLK (scratch)))])]
18363 ;; Two pops case is tricky, since pop causes dependency on destination register.
18364 ;; We use two registers if available.
18366 [(match_scratch:SI 0 "r")
18367 (match_scratch:SI 1 "r")
18368 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
18369 (clobber (reg:CC 17))
18370 (clobber (mem:BLK (scratch)))])]
18371 "optimize_size || !TARGET_ADD_ESP_8"
18372 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18373 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18374 (clobber (mem:BLK (scratch)))])
18375 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
18376 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18380 [(match_scratch:SI 0 "r")
18381 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
18382 (clobber (reg:CC 17))
18383 (clobber (mem:BLK (scratch)))])]
18385 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18386 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18387 (clobber (mem:BLK (scratch)))])
18388 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18389 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18392 ;; Convert esp additions to pop.
18394 [(match_scratch:SI 0 "r")
18395 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18396 (clobber (reg:CC 17))])]
18398 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18399 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18402 ;; Two pops case is tricky, since pop causes dependency on destination register.
18403 ;; We use two registers if available.
18405 [(match_scratch:SI 0 "r")
18406 (match_scratch:SI 1 "r")
18407 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
18408 (clobber (reg:CC 17))])]
18410 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18411 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
18412 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
18413 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18417 [(match_scratch:SI 0 "r")
18418 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
18419 (clobber (reg:CC 17))])]
18421 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18422 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
18423 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18424 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18427 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
18428 ;; required and register dies.
18431 (compare (match_operand:SI 0 "register_operand" "")
18432 (match_operand:SI 1 "incdec_operand" "")))]
18433 "ix86_match_ccmode (insn, CCGCmode)
18434 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18435 [(parallel [(set (reg:CCGC 17)
18436 (compare:CCGC (match_dup 0)
18438 (clobber (match_dup 0))])]
18443 (compare (match_operand:HI 0 "register_operand" "")
18444 (match_operand:HI 1 "incdec_operand" "")))]
18445 "ix86_match_ccmode (insn, CCGCmode)
18446 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18447 [(parallel [(set (reg:CCGC 17)
18448 (compare:CCGC (match_dup 0)
18450 (clobber (match_dup 0))])]
18455 (compare (match_operand:QI 0 "register_operand" "")
18456 (match_operand:QI 1 "incdec_operand" "")))]
18457 "ix86_match_ccmode (insn, CCGCmode)
18458 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18459 [(parallel [(set (reg:CCGC 17)
18460 (compare:CCGC (match_dup 0)
18462 (clobber (match_dup 0))])]
18465 ;; Convert compares with 128 to shorter add -128
18468 (compare (match_operand:SI 0 "register_operand" "")
18470 "ix86_match_ccmode (insn, CCGCmode)
18471 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18472 [(parallel [(set (reg:CCGC 17)
18473 (compare:CCGC (match_dup 0)
18475 (clobber (match_dup 0))])]
18480 (compare (match_operand:HI 0 "register_operand" "")
18482 "ix86_match_ccmode (insn, CCGCmode)
18483 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18484 [(parallel [(set (reg:CCGC 17)
18485 (compare:CCGC (match_dup 0)
18487 (clobber (match_dup 0))])]
18491 [(match_scratch:DI 0 "r")
18492 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
18493 (clobber (reg:CC 17))
18494 (clobber (mem:BLK (scratch)))])]
18495 "optimize_size || !TARGET_SUB_ESP_4"
18496 [(clobber (match_dup 0))
18497 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18498 (clobber (mem:BLK (scratch)))])])
18501 [(match_scratch:DI 0 "r")
18502 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
18503 (clobber (reg:CC 17))
18504 (clobber (mem:BLK (scratch)))])]
18505 "optimize_size || !TARGET_SUB_ESP_8"
18506 [(clobber (match_dup 0))
18507 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18508 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18509 (clobber (mem:BLK (scratch)))])])
18511 ;; Convert esp subtractions to push.
18513 [(match_scratch:DI 0 "r")
18514 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
18515 (clobber (reg:CC 17))])]
18516 "optimize_size || !TARGET_SUB_ESP_4"
18517 [(clobber (match_dup 0))
18518 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
18521 [(match_scratch:DI 0 "r")
18522 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
18523 (clobber (reg:CC 17))])]
18524 "optimize_size || !TARGET_SUB_ESP_8"
18525 [(clobber (match_dup 0))
18526 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18527 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
18529 ;; Convert epilogue deallocator to pop.
18531 [(match_scratch:DI 0 "r")
18532 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18533 (clobber (reg:CC 17))
18534 (clobber (mem:BLK (scratch)))])]
18535 "optimize_size || !TARGET_ADD_ESP_4"
18536 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18537 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18538 (clobber (mem:BLK (scratch)))])]
18541 ;; Two pops case is tricky, since pop causes dependency on destination register.
18542 ;; We use two registers if available.
18544 [(match_scratch:DI 0 "r")
18545 (match_scratch:DI 1 "r")
18546 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18547 (clobber (reg:CC 17))
18548 (clobber (mem:BLK (scratch)))])]
18549 "optimize_size || !TARGET_ADD_ESP_8"
18550 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18551 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18552 (clobber (mem:BLK (scratch)))])
18553 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
18554 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18558 [(match_scratch:DI 0 "r")
18559 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18560 (clobber (reg:CC 17))
18561 (clobber (mem:BLK (scratch)))])]
18563 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18564 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18565 (clobber (mem:BLK (scratch)))])
18566 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18567 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18570 ;; Convert esp additions to pop.
18572 [(match_scratch:DI 0 "r")
18573 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18574 (clobber (reg:CC 17))])]
18576 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18577 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18580 ;; Two pops case is tricky, since pop causes dependency on destination register.
18581 ;; We use two registers if available.
18583 [(match_scratch:DI 0 "r")
18584 (match_scratch:DI 1 "r")
18585 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18586 (clobber (reg:CC 17))])]
18588 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18589 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
18590 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
18591 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18595 [(match_scratch:DI 0 "r")
18596 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18597 (clobber (reg:CC 17))])]
18599 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18600 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
18601 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18602 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18605 ;; Imul $32bit_imm, mem, reg is vector decoded, while
18606 ;; imul $32bit_imm, reg, reg is direct decoded.
18608 [(match_scratch:DI 3 "r")
18609 (parallel [(set (match_operand:DI 0 "register_operand" "")
18610 (mult:DI (match_operand:DI 1 "memory_operand" "")
18611 (match_operand:DI 2 "immediate_operand" "")))
18612 (clobber (reg:CC 17))])]
18613 "TARGET_K8 && !optimize_size
18614 && (GET_CODE (operands[2]) != CONST_INT
18615 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
18616 [(set (match_dup 3) (match_dup 1))
18617 (parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2)))
18618 (clobber (reg:CC 17))])]
18622 [(match_scratch:SI 3 "r")
18623 (parallel [(set (match_operand:SI 0 "register_operand" "")
18624 (mult:SI (match_operand:SI 1 "memory_operand" "")
18625 (match_operand:SI 2 "immediate_operand" "")))
18626 (clobber (reg:CC 17))])]
18627 "TARGET_K8 && !optimize_size
18628 && (GET_CODE (operands[2]) != CONST_INT
18629 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
18630 [(set (match_dup 3) (match_dup 1))
18631 (parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))
18632 (clobber (reg:CC 17))])]
18636 [(match_scratch:SI 3 "r")
18637 (parallel [(set (match_operand:DI 0 "register_operand" "")
18639 (mult:SI (match_operand:SI 1 "memory_operand" "")
18640 (match_operand:SI 2 "immediate_operand" ""))))
18641 (clobber (reg:CC 17))])]
18642 "TARGET_K8 && !optimize_size
18643 && (GET_CODE (operands[2]) != CONST_INT
18644 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
18645 [(set (match_dup 3) (match_dup 1))
18646 (parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
18647 (clobber (reg:CC 17))])]
18650 ;; imul $8/16bit_imm, regmem, reg is vector decoded.
18651 ;; Convert it into imul reg, reg
18652 ;; It would be better to force assembler to encode instruction using long
18653 ;; immediate, but there is apparently no way to do so.
18655 [(parallel [(set (match_operand:DI 0 "register_operand" "")
18656 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
18657 (match_operand:DI 2 "const_int_operand" "")))
18658 (clobber (reg:CC 17))])
18659 (match_scratch:DI 3 "r")]
18660 "TARGET_K8 && !optimize_size
18661 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
18662 [(set (match_dup 3) (match_dup 2))
18663 (parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
18664 (clobber (reg:CC 17))])]
18666 if (!rtx_equal_p (operands[0], operands[1]))
18667 emit_move_insn (operands[0], operands[1]);
18671 [(parallel [(set (match_operand:SI 0 "register_operand" "")
18672 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
18673 (match_operand:SI 2 "const_int_operand" "")))
18674 (clobber (reg:CC 17))])
18675 (match_scratch:SI 3 "r")]
18676 "TARGET_K8 && !optimize_size
18677 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
18678 [(set (match_dup 3) (match_dup 2))
18679 (parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
18680 (clobber (reg:CC 17))])]
18682 if (!rtx_equal_p (operands[0], operands[1]))
18683 emit_move_insn (operands[0], operands[1]);
18687 [(parallel [(set (match_operand:HI 0 "register_operand" "")
18688 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "")
18689 (match_operand:HI 2 "immediate_operand" "")))
18690 (clobber (reg:CC 17))])
18691 (match_scratch:HI 3 "r")]
18692 "TARGET_K8 && !optimize_size"
18693 [(set (match_dup 3) (match_dup 2))
18694 (parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
18695 (clobber (reg:CC 17))])]
18697 if (!rtx_equal_p (operands[0], operands[1]))
18698 emit_move_insn (operands[0], operands[1]);
18701 ;; Call-value patterns last so that the wildcard operand does not
18702 ;; disrupt insn-recog's switch tables.
18704 (define_insn "*call_value_pop_0"
18705 [(set (match_operand 0 "" "")
18706 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
18707 (match_operand:SI 2 "" "")))
18708 (set (reg:SI 7) (plus:SI (reg:SI 7)
18709 (match_operand:SI 3 "immediate_operand" "")))]
18712 if (SIBLING_CALL_P (insn))
18715 return "call\t%P1";
18717 [(set_attr "type" "callv")])
18719 (define_insn "*call_value_pop_1"
18720 [(set (match_operand 0 "" "")
18721 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
18722 (match_operand:SI 2 "" "")))
18723 (set (reg:SI 7) (plus:SI (reg:SI 7)
18724 (match_operand:SI 3 "immediate_operand" "i")))]
18727 if (constant_call_address_operand (operands[1], QImode))
18729 if (SIBLING_CALL_P (insn))
18732 return "call\t%P1";
18734 if (SIBLING_CALL_P (insn))
18737 return "call\t%A1";
18739 [(set_attr "type" "callv")])
18741 (define_insn "*call_value_0"
18742 [(set (match_operand 0 "" "")
18743 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
18744 (match_operand:SI 2 "" "")))]
18747 if (SIBLING_CALL_P (insn))
18750 return "call\t%P1";
18752 [(set_attr "type" "callv")])
18754 (define_insn "*call_value_0_rex64"
18755 [(set (match_operand 0 "" "")
18756 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
18757 (match_operand:DI 2 "const_int_operand" "")))]
18760 if (SIBLING_CALL_P (insn))
18763 return "call\t%P1";
18765 [(set_attr "type" "callv")])
18767 (define_insn "*call_value_1"
18768 [(set (match_operand 0 "" "")
18769 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
18770 (match_operand:SI 2 "" "")))]
18771 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
18773 if (constant_call_address_operand (operands[1], QImode))
18774 return "call\t%P1";
18775 return "call\t%*%1";
18777 [(set_attr "type" "callv")])
18779 (define_insn "*sibcall_value_1"
18780 [(set (match_operand 0 "" "")
18781 (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,c,d,a"))
18782 (match_operand:SI 2 "" "")))]
18783 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
18785 if (constant_call_address_operand (operands[1], QImode))
18787 return "jmp\t%*%1";
18789 [(set_attr "type" "callv")])
18791 (define_insn "*call_value_1_rex64"
18792 [(set (match_operand 0 "" "")
18793 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
18794 (match_operand:DI 2 "" "")))]
18795 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
18797 if (constant_call_address_operand (operands[1], QImode))
18798 return "call\t%P1";
18799 return "call\t%A1";
18801 [(set_attr "type" "callv")])
18803 (define_insn "*sibcall_value_1_rex64"
18804 [(set (match_operand 0 "" "")
18805 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
18806 (match_operand:DI 2 "" "")))]
18807 "SIBLING_CALL_P (insn) && TARGET_64BIT"
18809 [(set_attr "type" "callv")])
18811 (define_insn "*sibcall_value_1_rex64_v"
18812 [(set (match_operand 0 "" "")
18813 (call (mem:QI (reg:DI 40))
18814 (match_operand:DI 1 "" "")))]
18815 "SIBLING_CALL_P (insn) && TARGET_64BIT"
18817 [(set_attr "type" "callv")])
18819 (define_insn "trap"
18820 [(trap_if (const_int 1) (const_int 5))]
18824 ;;; ix86 doesn't have conditional trap instructions, but we fake them
18825 ;;; for the sake of bounds checking. By emitting bounds checks as
18826 ;;; conditional traps rather than as conditional jumps around
18827 ;;; unconditional traps we avoid introducing spurious basic-block
18828 ;;; boundaries and facilitate elimination of redundant checks. In
18829 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
18832 ;;; FIXME: Static branch prediction rules for ix86 are such that
18833 ;;; forward conditional branches predict as untaken. As implemented
18834 ;;; below, pseudo conditional traps violate that rule. We should use
18835 ;;; .pushsection/.popsection to place all of the `int 5's in a special
18836 ;;; section loaded at the end of the text segment and branch forward
18837 ;;; there on bounds-failure, and then jump back immediately (in case
18838 ;;; the system chooses to ignore bounds violations, or to report
18839 ;;; violations and continue execution).
18841 (define_expand "conditional_trap"
18842 [(trap_if (match_operator 0 "comparison_operator"
18843 [(match_dup 2) (const_int 0)])
18844 (match_operand 1 "const_int_operand" ""))]
18847 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
18848 ix86_expand_compare (GET_CODE (operands[0]),
18854 (define_insn "*conditional_trap_1"
18855 [(trap_if (match_operator 0 "comparison_operator"
18856 [(reg 17) (const_int 0)])
18857 (match_operand 1 "const_int_operand" ""))]
18860 operands[2] = gen_label_rtx ();
18861 output_asm_insn ("j%c0\t%l2\; int\t%1", operands);
18862 (*targetm.asm_out.internal_label) (asm_out_file, "L",
18863 CODE_LABEL_NUMBER (operands[2]));
18867 ;; Pentium III SIMD instructions.
18869 ;; Moves for SSE/MMX regs.
18871 (define_insn "movv4sf_internal"
18872 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
18873 (match_operand:V4SF 1 "vector_move_operand" "C,xm,x"))]
18877 movaps\t{%1, %0|%0, %1}
18878 movaps\t{%1, %0|%0, %1}"
18879 [(set_attr "type" "ssemov")
18880 (set_attr "mode" "V4SF")])
18883 [(set (match_operand:V4SF 0 "register_operand" "")
18884 (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))]
18886 [(set (match_dup 0)
18888 (vec_duplicate:V4SF (match_dup 1))
18892 operands[1] = simplify_gen_subreg (SFmode, operands[1], V4SFmode, 0);
18893 operands[2] = CONST0_RTX (V4SFmode);
18896 (define_insn "movv4si_internal"
18897 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,x,m")
18898 (match_operand:V4SI 1 "vector_move_operand" "C,xm,x"))]
18901 switch (which_alternative)
18904 if (get_attr_mode (insn) == MODE_V4SF)
18905 return "xorps\t%0, %0";
18907 return "pxor\t%0, %0";
18910 if (get_attr_mode (insn) == MODE_V4SF)
18911 return "movaps\t{%1, %0|%0, %1}";
18913 return "movdqa\t{%1, %0|%0, %1}";
18918 [(set_attr "type" "ssemov")
18920 (cond [(eq_attr "alternative" "0,1")
18922 (ne (symbol_ref "optimize_size")
18924 (const_string "V4SF")
18925 (const_string "TI"))
18926 (eq_attr "alternative" "2")
18928 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18930 (ne (symbol_ref "optimize_size")
18932 (const_string "V4SF")
18933 (const_string "TI"))]
18934 (const_string "TI")))])
18936 (define_insn "movv2di_internal"
18937 [(set (match_operand:V2DI 0 "nonimmediate_operand" "=x,x,m")
18938 (match_operand:V2DI 1 "vector_move_operand" "C,xm,x"))]
18941 switch (which_alternative)
18944 if (get_attr_mode (insn) == MODE_V4SF)
18945 return "xorps\t%0, %0";
18947 return "pxor\t%0, %0";
18950 if (get_attr_mode (insn) == MODE_V4SF)
18951 return "movaps\t{%1, %0|%0, %1}";
18953 return "movdqa\t{%1, %0|%0, %1}";
18958 [(set_attr "type" "ssemov")
18960 (cond [(eq_attr "alternative" "0,1")
18962 (ne (symbol_ref "optimize_size")
18964 (const_string "V4SF")
18965 (const_string "TI"))
18966 (eq_attr "alternative" "2")
18968 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18970 (ne (symbol_ref "optimize_size")
18972 (const_string "V4SF")
18973 (const_string "TI"))]
18974 (const_string "TI")))])
18977 [(set (match_operand:V2DF 0 "register_operand" "")
18978 (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))]
18980 [(set (match_dup 0)
18982 (vec_duplicate:V2DF (match_dup 1))
18986 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2DFmode, 0);
18987 operands[2] = CONST0_RTX (V2DFmode);
18990 (define_insn "movv8qi_internal"
18991 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,y,m")
18992 (match_operand:V8QI 1 "vector_move_operand" "C,ym,y"))]
18994 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18997 movq\t{%1, %0|%0, %1}
18998 movq\t{%1, %0|%0, %1}"
18999 [(set_attr "type" "mmxmov")
19000 (set_attr "mode" "DI")])
19002 (define_insn "movv4hi_internal"
19003 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,y,m")
19004 (match_operand:V4HI 1 "vector_move_operand" "C,ym,y"))]
19006 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19009 movq\t{%1, %0|%0, %1}
19010 movq\t{%1, %0|%0, %1}"
19011 [(set_attr "type" "mmxmov")
19012 (set_attr "mode" "DI")])
19014 (define_insn "movv2si_internal"
19015 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,y,m")
19016 (match_operand:V2SI 1 "vector_move_operand" "C,ym,y"))]
19018 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19021 movq\t{%1, %0|%0, %1}
19022 movq\t{%1, %0|%0, %1}"
19023 [(set_attr "type" "mmxcvt")
19024 (set_attr "mode" "DI")])
19026 (define_insn "movv2sf_internal"
19027 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,y,m")
19028 (match_operand:V2SF 1 "vector_move_operand" "C,ym,y"))]
19030 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19033 movq\t{%1, %0|%0, %1}
19034 movq\t{%1, %0|%0, %1}"
19035 [(set_attr "type" "mmxcvt")
19036 (set_attr "mode" "DI")])
19038 (define_expand "movti"
19039 [(set (match_operand:TI 0 "nonimmediate_operand" "")
19040 (match_operand:TI 1 "nonimmediate_operand" ""))]
19041 "TARGET_SSE || TARGET_64BIT"
19044 ix86_expand_move (TImode, operands);
19046 ix86_expand_vector_move (TImode, operands);
19050 (define_insn "movv2df_internal"
19051 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
19052 (match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))]
19054 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19056 switch (which_alternative)
19059 if (get_attr_mode (insn) == MODE_V4SF)
19060 return "xorps\t%0, %0";
19062 return "xorpd\t%0, %0";
19065 if (get_attr_mode (insn) == MODE_V4SF)
19066 return "movaps\t{%1, %0|%0, %1}";
19068 return "movapd\t{%1, %0|%0, %1}";
19073 [(set_attr "type" "ssemov")
19075 (cond [(eq_attr "alternative" "0,1")
19077 (ne (symbol_ref "optimize_size")
19079 (const_string "V4SF")
19080 (const_string "V2DF"))
19081 (eq_attr "alternative" "2")
19083 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19085 (ne (symbol_ref "optimize_size")
19087 (const_string "V4SF")
19088 (const_string "V2DF"))]
19089 (const_string "V2DF")))])
19091 (define_insn "movv8hi_internal"
19092 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,x,m")
19093 (match_operand:V8HI 1 "vector_move_operand" "C,xm,x"))]
19095 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19097 switch (which_alternative)
19100 if (get_attr_mode (insn) == MODE_V4SF)
19101 return "xorps\t%0, %0";
19103 return "pxor\t%0, %0";
19106 if (get_attr_mode (insn) == MODE_V4SF)
19107 return "movaps\t{%1, %0|%0, %1}";
19109 return "movdqa\t{%1, %0|%0, %1}";
19114 [(set_attr "type" "ssemov")
19116 (cond [(eq_attr "alternative" "0,1")
19118 (ne (symbol_ref "optimize_size")
19120 (const_string "V4SF")
19121 (const_string "TI"))
19122 (eq_attr "alternative" "2")
19124 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19126 (ne (symbol_ref "optimize_size")
19128 (const_string "V4SF")
19129 (const_string "TI"))]
19130 (const_string "TI")))])
19132 (define_insn "movv16qi_internal"
19133 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,x,m")
19134 (match_operand:V16QI 1 "nonimmediate_operand" "C,xm,x"))]
19136 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19138 switch (which_alternative)
19141 if (get_attr_mode (insn) == MODE_V4SF)
19142 return "xorps\t%0, %0";
19144 return "pxor\t%0, %0";
19147 if (get_attr_mode (insn) == MODE_V4SF)
19148 return "movaps\t{%1, %0|%0, %1}";
19150 return "movdqa\t{%1, %0|%0, %1}";
19155 [(set_attr "type" "ssemov")
19157 (cond [(eq_attr "alternative" "0,1")
19159 (ne (symbol_ref "optimize_size")
19161 (const_string "V4SF")
19162 (const_string "TI"))
19163 (eq_attr "alternative" "2")
19165 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19167 (ne (symbol_ref "optimize_size")
19169 (const_string "V4SF")
19170 (const_string "TI"))]
19171 (const_string "TI")))])
19173 (define_expand "movv2df"
19174 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
19175 (match_operand:V2DF 1 "nonimmediate_operand" ""))]
19178 ix86_expand_vector_move (V2DFmode, operands);
19182 (define_expand "movv8hi"
19183 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
19184 (match_operand:V8HI 1 "nonimmediate_operand" ""))]
19187 ix86_expand_vector_move (V8HImode, operands);
19191 (define_expand "movv16qi"
19192 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
19193 (match_operand:V16QI 1 "nonimmediate_operand" ""))]
19196 ix86_expand_vector_move (V16QImode, operands);
19200 (define_expand "movv4sf"
19201 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
19202 (match_operand:V4SF 1 "nonimmediate_operand" ""))]
19205 ix86_expand_vector_move (V4SFmode, operands);
19209 (define_expand "movv4si"
19210 [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
19211 (match_operand:V4SI 1 "nonimmediate_operand" ""))]
19214 ix86_expand_vector_move (V4SImode, operands);
19218 (define_expand "movv2di"
19219 [(set (match_operand:V2DI 0 "nonimmediate_operand" "")
19220 (match_operand:V2DI 1 "nonimmediate_operand" ""))]
19223 ix86_expand_vector_move (V2DImode, operands);
19227 (define_expand "movv2si"
19228 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
19229 (match_operand:V2SI 1 "nonimmediate_operand" ""))]
19232 ix86_expand_vector_move (V2SImode, operands);
19236 (define_expand "movv4hi"
19237 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
19238 (match_operand:V4HI 1 "nonimmediate_operand" ""))]
19241 ix86_expand_vector_move (V4HImode, operands);
19245 (define_expand "movv8qi"
19246 [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
19247 (match_operand:V8QI 1 "nonimmediate_operand" ""))]
19250 ix86_expand_vector_move (V8QImode, operands);
19254 (define_expand "movv2sf"
19255 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
19256 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
19259 ix86_expand_vector_move (V2SFmode, operands);
19263 (define_insn "*pushti"
19264 [(set (match_operand:TI 0 "push_operand" "=<")
19265 (match_operand:TI 1 "register_operand" "x"))]
19269 (define_insn "*pushv2df"
19270 [(set (match_operand:V2DF 0 "push_operand" "=<")
19271 (match_operand:V2DF 1 "register_operand" "x"))]
19275 (define_insn "*pushv2di"
19276 [(set (match_operand:V2DI 0 "push_operand" "=<")
19277 (match_operand:V2DI 1 "register_operand" "x"))]
19281 (define_insn "*pushv8hi"
19282 [(set (match_operand:V8HI 0 "push_operand" "=<")
19283 (match_operand:V8HI 1 "register_operand" "x"))]
19287 (define_insn "*pushv16qi"
19288 [(set (match_operand:V16QI 0 "push_operand" "=<")
19289 (match_operand:V16QI 1 "register_operand" "x"))]
19293 (define_insn "*pushv4sf"
19294 [(set (match_operand:V4SF 0 "push_operand" "=<")
19295 (match_operand:V4SF 1 "register_operand" "x"))]
19299 (define_insn "*pushv4si"
19300 [(set (match_operand:V4SI 0 "push_operand" "=<")
19301 (match_operand:V4SI 1 "register_operand" "x"))]
19305 (define_insn "*pushv2si"
19306 [(set (match_operand:V2SI 0 "push_operand" "=<")
19307 (match_operand:V2SI 1 "register_operand" "y"))]
19311 (define_insn "*pushv4hi"
19312 [(set (match_operand:V4HI 0 "push_operand" "=<")
19313 (match_operand:V4HI 1 "register_operand" "y"))]
19317 (define_insn "*pushv8qi"
19318 [(set (match_operand:V8QI 0 "push_operand" "=<")
19319 (match_operand:V8QI 1 "register_operand" "y"))]
19323 (define_insn "*pushv2sf"
19324 [(set (match_operand:V2SF 0 "push_operand" "=<")
19325 (match_operand:V2SF 1 "register_operand" "y"))]
19330 [(set (match_operand 0 "push_operand" "")
19331 (match_operand 1 "register_operand" ""))]
19332 "!TARGET_64BIT && reload_completed
19333 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
19334 [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 3)))
19335 (set (match_dup 2) (match_dup 1))]
19336 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
19337 stack_pointer_rtx);
19338 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
19341 [(set (match_operand 0 "push_operand" "")
19342 (match_operand 1 "register_operand" ""))]
19343 "TARGET_64BIT && reload_completed
19344 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
19345 [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 3)))
19346 (set (match_dup 2) (match_dup 1))]
19347 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
19348 stack_pointer_rtx);
19349 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
19352 (define_insn "movti_internal"
19353 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
19354 (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
19355 "TARGET_SSE && !TARGET_64BIT
19356 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19358 switch (which_alternative)
19361 if (get_attr_mode (insn) == MODE_V4SF)
19362 return "xorps\t%0, %0";
19364 return "pxor\t%0, %0";
19367 if (get_attr_mode (insn) == MODE_V4SF)
19368 return "movaps\t{%1, %0|%0, %1}";
19370 return "movdqa\t{%1, %0|%0, %1}";
19375 [(set_attr "type" "ssemov,ssemov,ssemov")
19377 (cond [(eq_attr "alternative" "0,1")
19379 (ne (symbol_ref "optimize_size")
19381 (const_string "V4SF")
19382 (const_string "TI"))
19383 (eq_attr "alternative" "2")
19385 (ne (symbol_ref "optimize_size")
19387 (const_string "V4SF")
19388 (const_string "TI"))]
19389 (const_string "TI")))])
19391 (define_insn "*movti_rex64"
19392 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,x,xm")
19393 (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
19395 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19397 switch (which_alternative)
19403 if (get_attr_mode (insn) == MODE_V4SF)
19404 return "xorps\t%0, %0";
19406 return "pxor\t%0, %0";
19409 if (get_attr_mode (insn) == MODE_V4SF)
19410 return "movaps\t{%1, %0|%0, %1}";
19412 return "movdqa\t{%1, %0|%0, %1}";
19417 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
19419 (cond [(eq_attr "alternative" "2,3")
19421 (ne (symbol_ref "optimize_size")
19423 (const_string "V4SF")
19424 (const_string "TI"))
19425 (eq_attr "alternative" "4")
19427 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19429 (ne (symbol_ref "optimize_size")
19431 (const_string "V4SF")
19432 (const_string "TI"))]
19433 (const_string "DI")))])
19436 [(set (match_operand:TI 0 "nonimmediate_operand" "")
19437 (match_operand:TI 1 "general_operand" ""))]
19438 "reload_completed && !SSE_REG_P (operands[0])
19439 && !SSE_REG_P (operands[1])"
19441 "ix86_split_long_move (operands); DONE;")
19443 ;; These two patterns are useful for specifying exactly whether to use
19444 ;; movaps or movups
19445 (define_insn "sse_movaps"
19446 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19447 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
19450 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19451 "movaps\t{%1, %0|%0, %1}"
19452 [(set_attr "type" "ssemov,ssemov")
19453 (set_attr "mode" "V4SF")])
19455 (define_insn "sse_movups"
19456 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19457 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
19460 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19461 "movups\t{%1, %0|%0, %1}"
19462 [(set_attr "type" "ssecvt,ssecvt")
19463 (set_attr "mode" "V4SF")])
19466 ;; SSE Strange Moves.
19468 (define_insn "sse_movmskps"
19469 [(set (match_operand:SI 0 "register_operand" "=r")
19470 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")]
19473 "movmskps\t{%1, %0|%0, %1}"
19474 [(set_attr "type" "ssecvt")
19475 (set_attr "mode" "V4SF")])
19477 (define_insn "mmx_pmovmskb"
19478 [(set (match_operand:SI 0 "register_operand" "=r")
19479 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
19481 "TARGET_SSE || TARGET_3DNOW_A"
19482 "pmovmskb\t{%1, %0|%0, %1}"
19483 [(set_attr "type" "ssecvt")
19484 (set_attr "mode" "V4SF")])
19487 (define_insn "mmx_maskmovq"
19488 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
19489 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
19490 (match_operand:V8QI 2 "register_operand" "y")]
19492 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
19493 ;; @@@ check ordering of operands in intel/nonintel syntax
19494 "maskmovq\t{%2, %1|%1, %2}"
19495 [(set_attr "type" "mmxcvt")
19496 (set_attr "mode" "DI")])
19498 (define_insn "mmx_maskmovq_rex"
19499 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
19500 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
19501 (match_operand:V8QI 2 "register_operand" "y")]
19503 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
19504 ;; @@@ check ordering of operands in intel/nonintel syntax
19505 "maskmovq\t{%2, %1|%1, %2}"
19506 [(set_attr "type" "mmxcvt")
19507 (set_attr "mode" "DI")])
19509 (define_insn "sse_movntv4sf"
19510 [(set (match_operand:V4SF 0 "memory_operand" "=m")
19511 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")]
19514 "movntps\t{%1, %0|%0, %1}"
19515 [(set_attr "type" "ssemov")
19516 (set_attr "mode" "V4SF")])
19518 (define_insn "sse_movntdi"
19519 [(set (match_operand:DI 0 "memory_operand" "=m")
19520 (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
19522 "TARGET_SSE || TARGET_3DNOW_A"
19523 "movntq\t{%1, %0|%0, %1}"
19524 [(set_attr "type" "mmxmov")
19525 (set_attr "mode" "DI")])
19527 (define_insn "sse_movhlps"
19528 [(set (match_operand:V4SF 0 "register_operand" "=x")
19530 (match_operand:V4SF 1 "register_operand" "0")
19531 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19532 (parallel [(const_int 2)
19538 "movhlps\t{%2, %0|%0, %2}"
19539 [(set_attr "type" "ssecvt")
19540 (set_attr "mode" "V4SF")])
19542 (define_insn "sse_movlhps"
19543 [(set (match_operand:V4SF 0 "register_operand" "=x")
19545 (match_operand:V4SF 1 "register_operand" "0")
19546 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19547 (parallel [(const_int 2)
19553 "movlhps\t{%2, %0|%0, %2}"
19554 [(set_attr "type" "ssecvt")
19555 (set_attr "mode" "V4SF")])
19557 (define_insn "sse_movhps"
19558 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19560 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
19561 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
19564 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
19565 "movhps\t{%2, %0|%0, %2}"
19566 [(set_attr "type" "ssecvt")
19567 (set_attr "mode" "V4SF")])
19569 (define_insn "sse_movlps"
19570 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19572 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
19573 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
19576 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
19577 "movlps\t{%2, %0|%0, %2}"
19578 [(set_attr "type" "ssecvt")
19579 (set_attr "mode" "V4SF")])
19581 (define_expand "sse_loadss"
19582 [(match_operand:V4SF 0 "register_operand" "")
19583 (match_operand:SF 1 "memory_operand" "")]
19586 emit_insn (gen_sse_loadss_1 (operands[0], operands[1],
19587 CONST0_RTX (V4SFmode)));
19591 (define_insn "sse_loadss_1"
19592 [(set (match_operand:V4SF 0 "register_operand" "=x")
19594 (vec_duplicate:V4SF (match_operand:SF 1 "memory_operand" "m"))
19595 (match_operand:V4SF 2 "const0_operand" "X")
19598 "movss\t{%1, %0|%0, %1}"
19599 [(set_attr "type" "ssemov")
19600 (set_attr "mode" "SF")])
19602 (define_insn "sse_movss"
19603 [(set (match_operand:V4SF 0 "register_operand" "=x")
19605 (match_operand:V4SF 1 "register_operand" "0")
19606 (match_operand:V4SF 2 "register_operand" "x")
19609 "movss\t{%2, %0|%0, %2}"
19610 [(set_attr "type" "ssemov")
19611 (set_attr "mode" "SF")])
19613 (define_insn "sse_storess"
19614 [(set (match_operand:SF 0 "memory_operand" "=m")
19616 (match_operand:V4SF 1 "register_operand" "x")
19617 (parallel [(const_int 0)])))]
19619 "movss\t{%1, %0|%0, %1}"
19620 [(set_attr "type" "ssemov")
19621 (set_attr "mode" "SF")])
19623 (define_insn "sse_shufps"
19624 [(set (match_operand:V4SF 0 "register_operand" "=x")
19625 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
19626 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
19627 (match_operand:SI 3 "immediate_operand" "i")]
19630 ;; @@@ check operand order for intel/nonintel syntax
19631 "shufps\t{%3, %2, %0|%0, %2, %3}"
19632 [(set_attr "type" "ssecvt")
19633 (set_attr "mode" "V4SF")])
19638 (define_insn "addv4sf3"
19639 [(set (match_operand:V4SF 0 "register_operand" "=x")
19640 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19641 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19643 "addps\t{%2, %0|%0, %2}"
19644 [(set_attr "type" "sseadd")
19645 (set_attr "mode" "V4SF")])
19647 (define_insn "vmaddv4sf3"
19648 [(set (match_operand:V4SF 0 "register_operand" "=x")
19650 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19651 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19655 "addss\t{%2, %0|%0, %2}"
19656 [(set_attr "type" "sseadd")
19657 (set_attr "mode" "SF")])
19659 (define_insn "subv4sf3"
19660 [(set (match_operand:V4SF 0 "register_operand" "=x")
19661 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19662 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19664 "subps\t{%2, %0|%0, %2}"
19665 [(set_attr "type" "sseadd")
19666 (set_attr "mode" "V4SF")])
19668 (define_insn "vmsubv4sf3"
19669 [(set (match_operand:V4SF 0 "register_operand" "=x")
19671 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19672 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19676 "subss\t{%2, %0|%0, %2}"
19677 [(set_attr "type" "sseadd")
19678 (set_attr "mode" "SF")])
19680 (define_insn "mulv4sf3"
19681 [(set (match_operand:V4SF 0 "register_operand" "=x")
19682 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
19683 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19685 "mulps\t{%2, %0|%0, %2}"
19686 [(set_attr "type" "ssemul")
19687 (set_attr "mode" "V4SF")])
19689 (define_insn "vmmulv4sf3"
19690 [(set (match_operand:V4SF 0 "register_operand" "=x")
19692 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
19693 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19697 "mulss\t{%2, %0|%0, %2}"
19698 [(set_attr "type" "ssemul")
19699 (set_attr "mode" "SF")])
19701 (define_insn "divv4sf3"
19702 [(set (match_operand:V4SF 0 "register_operand" "=x")
19703 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
19704 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19706 "divps\t{%2, %0|%0, %2}"
19707 [(set_attr "type" "ssediv")
19708 (set_attr "mode" "V4SF")])
19710 (define_insn "vmdivv4sf3"
19711 [(set (match_operand:V4SF 0 "register_operand" "=x")
19713 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
19714 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19718 "divss\t{%2, %0|%0, %2}"
19719 [(set_attr "type" "ssediv")
19720 (set_attr "mode" "SF")])
19723 ;; SSE square root/reciprocal
19725 (define_insn "rcpv4sf2"
19726 [(set (match_operand:V4SF 0 "register_operand" "=x")
19728 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
19730 "rcpps\t{%1, %0|%0, %1}"
19731 [(set_attr "type" "sse")
19732 (set_attr "mode" "V4SF")])
19734 (define_insn "vmrcpv4sf2"
19735 [(set (match_operand:V4SF 0 "register_operand" "=x")
19737 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
19739 (match_operand:V4SF 2 "register_operand" "0")
19742 "rcpss\t{%1, %0|%0, %1}"
19743 [(set_attr "type" "sse")
19744 (set_attr "mode" "SF")])
19746 (define_insn "rsqrtv4sf2"
19747 [(set (match_operand:V4SF 0 "register_operand" "=x")
19749 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
19751 "rsqrtps\t{%1, %0|%0, %1}"
19752 [(set_attr "type" "sse")
19753 (set_attr "mode" "V4SF")])
19755 (define_insn "vmrsqrtv4sf2"
19756 [(set (match_operand:V4SF 0 "register_operand" "=x")
19758 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
19760 (match_operand:V4SF 2 "register_operand" "0")
19763 "rsqrtss\t{%1, %0|%0, %1}"
19764 [(set_attr "type" "sse")
19765 (set_attr "mode" "SF")])
19767 (define_insn "sqrtv4sf2"
19768 [(set (match_operand:V4SF 0 "register_operand" "=x")
19769 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
19771 "sqrtps\t{%1, %0|%0, %1}"
19772 [(set_attr "type" "sse")
19773 (set_attr "mode" "V4SF")])
19775 (define_insn "vmsqrtv4sf2"
19776 [(set (match_operand:V4SF 0 "register_operand" "=x")
19778 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
19779 (match_operand:V4SF 2 "register_operand" "0")
19782 "sqrtss\t{%1, %0|%0, %1}"
19783 [(set_attr "type" "sse")
19784 (set_attr "mode" "SF")])
19786 ;; SSE logical operations.
19788 ;; SSE defines logical operations on floating point values. This brings
19789 ;; interesting challenge to RTL representation where logicals are only valid
19790 ;; on integral types. We deal with this by representing the floating point
19791 ;; logical as logical on arguments casted to TImode as this is what hardware
19792 ;; really does. Unfortunately hardware requires the type information to be
19793 ;; present and thus we must avoid subregs from being simplified and eliminated
19794 ;; in later compilation phases.
19796 ;; We have following variants from each instruction:
19797 ;; sse_andsf3 - the operation taking V4SF vector operands
19798 ;; and doing TImode cast on them
19799 ;; *sse_andsf3_memory - the operation taking one memory operand casted to
19800 ;; TImode, since backend insist on eliminating casts
19801 ;; on memory operands
19802 ;; sse_andti3_sf_1 - the operation taking SF scalar operands.
19803 ;; We can not accept memory operand here as instruction reads
19804 ;; whole scalar. This is generated only post reload by GCC
19805 ;; scalar float operations that expands to logicals (fabs)
19806 ;; sse_andti3_sf_2 - the operation taking SF scalar input and TImode
19807 ;; memory operand. Eventually combine can be able
19808 ;; to synthesize these using splitter.
19809 ;; sse2_anddf3, *sse2_anddf3_memory
19812 ;; These are not called andti3 etc. because we really really don't want
19813 ;; the compiler to widen DImode ands to TImode ands and then try to move
19814 ;; into DImode subregs of SSE registers, and them together, and move out
19815 ;; of DImode subregs again!
19816 ;; SSE1 single precision floating point logical operation
19817 (define_expand "sse_andv4sf3"
19818 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19819 (and:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
19820 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19824 (define_insn "*sse_andv4sf3"
19825 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19826 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19827 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19829 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19830 "andps\t{%2, %0|%0, %2}"
19831 [(set_attr "type" "sselog")
19832 (set_attr "mode" "V4SF")])
19834 (define_insn "*sse_andsf3"
19835 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19836 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19837 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19839 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19840 "andps\t{%2, %0|%0, %2}"
19841 [(set_attr "type" "sselog")
19842 (set_attr "mode" "V4SF")])
19844 (define_expand "sse_nandv4sf3"
19845 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19846 (and:TI (not:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0))
19847 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19851 (define_insn "*sse_nandv4sf3"
19852 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19853 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19854 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19856 "andnps\t{%2, %0|%0, %2}"
19857 [(set_attr "type" "sselog")
19858 (set_attr "mode" "V4SF")])
19860 (define_insn "*sse_nandsf3"
19861 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19862 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19863 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19865 "andnps\t{%2, %0|%0, %2}"
19866 [(set_attr "type" "sselog")
19867 (set_attr "mode" "V4SF")])
19869 (define_expand "sse_iorv4sf3"
19870 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19871 (ior:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
19872 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19876 (define_insn "*sse_iorv4sf3"
19877 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19878 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19879 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19881 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19882 "orps\t{%2, %0|%0, %2}"
19883 [(set_attr "type" "sselog")
19884 (set_attr "mode" "V4SF")])
19886 (define_insn "*sse_iorsf3"
19887 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19888 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19889 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19891 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19892 "orps\t{%2, %0|%0, %2}"
19893 [(set_attr "type" "sselog")
19894 (set_attr "mode" "V4SF")])
19896 (define_expand "sse_xorv4sf3"
19897 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19898 (xor:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
19899 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19901 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19904 (define_insn "*sse_xorv4sf3"
19905 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19906 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19907 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19909 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19910 "xorps\t{%2, %0|%0, %2}"
19911 [(set_attr "type" "sselog")
19912 (set_attr "mode" "V4SF")])
19914 (define_insn "*sse_xorsf3"
19915 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19916 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19917 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19919 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19920 "xorps\t{%2, %0|%0, %2}"
19921 [(set_attr "type" "sselog")
19922 (set_attr "mode" "V4SF")])
19924 ;; SSE2 double precision floating point logical operation
19926 (define_expand "sse2_andv2df3"
19927 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19928 (and:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0)
19929 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19933 (define_insn "*sse2_andv2df3"
19934 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19935 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19936 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19938 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19939 "andpd\t{%2, %0|%0, %2}"
19940 [(set_attr "type" "sselog")
19941 (set_attr "mode" "V2DF")])
19943 (define_insn "*sse2_andv2df3"
19944 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
19945 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19946 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19948 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19949 "andpd\t{%2, %0|%0, %2}"
19950 [(set_attr "type" "sselog")
19951 (set_attr "mode" "V2DF")])
19953 (define_expand "sse2_nandv2df3"
19954 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19955 (and:TI (not:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0))
19956 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19960 (define_insn "*sse2_nandv2df3"
19961 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19962 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19963 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19965 "andnpd\t{%2, %0|%0, %2}"
19966 [(set_attr "type" "sselog")
19967 (set_attr "mode" "V2DF")])
19969 (define_insn "*sse_nandti3_df"
19970 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
19971 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19972 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
19974 "andnpd\t{%2, %0|%0, %2}"
19975 [(set_attr "type" "sselog")
19976 (set_attr "mode" "V2DF")])
19978 (define_expand "sse2_iorv2df3"
19979 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19980 (ior:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0)
19981 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19985 (define_insn "*sse2_iorv2df3"
19986 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19987 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19988 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19990 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19991 "orpd\t{%2, %0|%0, %2}"
19992 [(set_attr "type" "sselog")
19993 (set_attr "mode" "V2DF")])
19995 (define_insn "*sse2_iordf3"
19996 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
19997 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19998 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20000 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20001 "orpd\t{%2, %0|%0, %2}"
20002 [(set_attr "type" "sselog")
20003 (set_attr "mode" "V2DF")])
20005 (define_expand "sse2_xorv2df3"
20006 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
20007 (xor:TI (subreg:TI (match_operand:V2DF 1 "nonimmediate_operand" "") 0)
20008 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
20012 (define_insn "*sse2_xorv2df3"
20013 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
20014 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20015 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20017 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20018 "xorpd\t{%2, %0|%0, %2}"
20019 [(set_attr "type" "sselog")
20020 (set_attr "mode" "V2DF")])
20022 (define_insn "*sse2_xordf3"
20023 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
20024 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20025 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20027 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20028 "xorpd\t{%2, %0|%0, %2}"
20029 [(set_attr "type" "sselog")
20030 (set_attr "mode" "V2DF")])
20032 ;; SSE2 integral logicals. These patterns must always come after floating
20033 ;; point ones since we don't want compiler to use integer opcodes on floating
20034 ;; point SSE values to avoid matching of subregs in the match_operand.
20035 (define_insn "*sse2_andti3"
20036 [(set (match_operand:TI 0 "register_operand" "=x")
20037 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20038 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20040 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20041 "pand\t{%2, %0|%0, %2}"
20042 [(set_attr "type" "sselog")
20043 (set_attr "mode" "TI")])
20045 (define_insn "sse2_andv2di3"
20046 [(set (match_operand:V2DI 0 "register_operand" "=x")
20047 (and:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
20048 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20050 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20051 "pand\t{%2, %0|%0, %2}"
20052 [(set_attr "type" "sselog")
20053 (set_attr "mode" "TI")])
20055 (define_insn "*sse2_nandti3"
20056 [(set (match_operand:TI 0 "register_operand" "=x")
20057 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
20058 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20060 "pandn\t{%2, %0|%0, %2}"
20061 [(set_attr "type" "sselog")
20062 (set_attr "mode" "TI")])
20064 (define_insn "sse2_nandv2di3"
20065 [(set (match_operand:V2DI 0 "register_operand" "=x")
20066 (and:V2DI (not:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "0"))
20067 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20069 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20070 "pandn\t{%2, %0|%0, %2}"
20071 [(set_attr "type" "sselog")
20072 (set_attr "mode" "TI")])
20074 (define_insn "*sse2_iorti3"
20075 [(set (match_operand:TI 0 "register_operand" "=x")
20076 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20077 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20079 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20080 "por\t{%2, %0|%0, %2}"
20081 [(set_attr "type" "sselog")
20082 (set_attr "mode" "TI")])
20084 (define_insn "sse2_iorv2di3"
20085 [(set (match_operand:V2DI 0 "register_operand" "=x")
20086 (ior:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
20087 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20089 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20090 "por\t{%2, %0|%0, %2}"
20091 [(set_attr "type" "sselog")
20092 (set_attr "mode" "TI")])
20094 (define_insn "*sse2_xorti3"
20095 [(set (match_operand:TI 0 "register_operand" "=x")
20096 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20097 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20099 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20100 "pxor\t{%2, %0|%0, %2}"
20101 [(set_attr "type" "sselog")
20102 (set_attr "mode" "TI")])
20104 (define_insn "sse2_xorv2di3"
20105 [(set (match_operand:V2DI 0 "register_operand" "=x")
20106 (xor:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
20107 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20109 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20110 "pxor\t{%2, %0|%0, %2}"
20111 [(set_attr "type" "sselog")
20112 (set_attr "mode" "TI")])
20114 ;; Use xor, but don't show input operands so they aren't live before
20116 (define_insn "sse_clrv4sf"
20117 [(set (match_operand:V4SF 0 "register_operand" "=x")
20118 (match_operand:V4SF 1 "const0_operand" "X"))]
20121 if (get_attr_mode (insn) == MODE_TI)
20122 return "pxor\t{%0, %0|%0, %0}";
20124 return "xorps\t{%0, %0|%0, %0}";
20126 [(set_attr "type" "sselog")
20127 (set_attr "memory" "none")
20130 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
20132 (ne (symbol_ref "TARGET_SSE2")
20134 (eq (symbol_ref "optimize_size")
20136 (const_string "TI")
20137 (const_string "V4SF")))])
20139 ;; Use xor, but don't show input operands so they aren't live before
20141 (define_insn "sse_clrv2df"
20142 [(set (match_operand:V2DF 0 "register_operand" "=x")
20143 (unspec:V2DF [(const_int 0)] UNSPEC_NOP))]
20145 "xorpd\t{%0, %0|%0, %0}"
20146 [(set_attr "type" "sselog")
20147 (set_attr "memory" "none")
20148 (set_attr "mode" "V4SF")])
20150 ;; SSE mask-generating compares
20152 (define_insn "maskcmpv4sf3"
20153 [(set (match_operand:V4SI 0 "register_operand" "=x")
20154 (match_operator:V4SI 3 "sse_comparison_operator"
20155 [(match_operand:V4SF 1 "register_operand" "0")
20156 (match_operand:V4SF 2 "register_operand" "x")]))]
20158 "cmp%D3ps\t{%2, %0|%0, %2}"
20159 [(set_attr "type" "ssecmp")
20160 (set_attr "mode" "V4SF")])
20162 (define_insn "maskncmpv4sf3"
20163 [(set (match_operand:V4SI 0 "register_operand" "=x")
20165 (match_operator:V4SI 3 "sse_comparison_operator"
20166 [(match_operand:V4SF 1 "register_operand" "0")
20167 (match_operand:V4SF 2 "register_operand" "x")])))]
20170 if (GET_CODE (operands[3]) == UNORDERED)
20171 return "cmpordps\t{%2, %0|%0, %2}";
20173 return "cmpn%D3ps\t{%2, %0|%0, %2}";
20175 [(set_attr "type" "ssecmp")
20176 (set_attr "mode" "V4SF")])
20178 (define_insn "vmmaskcmpv4sf3"
20179 [(set (match_operand:V4SI 0 "register_operand" "=x")
20181 (match_operator:V4SI 3 "sse_comparison_operator"
20182 [(match_operand:V4SF 1 "register_operand" "0")
20183 (match_operand:V4SF 2 "register_operand" "x")])
20184 (subreg:V4SI (match_dup 1) 0)
20187 "cmp%D3ss\t{%2, %0|%0, %2}"
20188 [(set_attr "type" "ssecmp")
20189 (set_attr "mode" "SF")])
20191 (define_insn "vmmaskncmpv4sf3"
20192 [(set (match_operand:V4SI 0 "register_operand" "=x")
20195 (match_operator:V4SI 3 "sse_comparison_operator"
20196 [(match_operand:V4SF 1 "register_operand" "0")
20197 (match_operand:V4SF 2 "register_operand" "x")]))
20198 (subreg:V4SI (match_dup 1) 0)
20202 if (GET_CODE (operands[3]) == UNORDERED)
20203 return "cmpordss\t{%2, %0|%0, %2}";
20205 return "cmpn%D3ss\t{%2, %0|%0, %2}";
20207 [(set_attr "type" "ssecmp")
20208 (set_attr "mode" "SF")])
20210 (define_insn "sse_comi"
20211 [(set (reg:CCFP 17)
20212 (compare:CCFP (vec_select:SF
20213 (match_operand:V4SF 0 "register_operand" "x")
20214 (parallel [(const_int 0)]))
20216 (match_operand:V4SF 1 "register_operand" "x")
20217 (parallel [(const_int 0)]))))]
20219 "comiss\t{%1, %0|%0, %1}"
20220 [(set_attr "type" "ssecomi")
20221 (set_attr "mode" "SF")])
20223 (define_insn "sse_ucomi"
20224 [(set (reg:CCFPU 17)
20225 (compare:CCFPU (vec_select:SF
20226 (match_operand:V4SF 0 "register_operand" "x")
20227 (parallel [(const_int 0)]))
20229 (match_operand:V4SF 1 "register_operand" "x")
20230 (parallel [(const_int 0)]))))]
20232 "ucomiss\t{%1, %0|%0, %1}"
20233 [(set_attr "type" "ssecomi")
20234 (set_attr "mode" "SF")])
20239 (define_insn "sse_unpckhps"
20240 [(set (match_operand:V4SF 0 "register_operand" "=x")
20242 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
20243 (parallel [(const_int 2)
20247 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
20248 (parallel [(const_int 0)
20254 "unpckhps\t{%2, %0|%0, %2}"
20255 [(set_attr "type" "ssecvt")
20256 (set_attr "mode" "V4SF")])
20258 (define_insn "sse_unpcklps"
20259 [(set (match_operand:V4SF 0 "register_operand" "=x")
20261 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
20262 (parallel [(const_int 0)
20266 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
20267 (parallel [(const_int 2)
20273 "unpcklps\t{%2, %0|%0, %2}"
20274 [(set_attr "type" "ssecvt")
20275 (set_attr "mode" "V4SF")])
20280 (define_insn "smaxv4sf3"
20281 [(set (match_operand:V4SF 0 "register_operand" "=x")
20282 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
20283 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20285 "maxps\t{%2, %0|%0, %2}"
20286 [(set_attr "type" "sse")
20287 (set_attr "mode" "V4SF")])
20289 (define_insn "vmsmaxv4sf3"
20290 [(set (match_operand:V4SF 0 "register_operand" "=x")
20292 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
20293 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20297 "maxss\t{%2, %0|%0, %2}"
20298 [(set_attr "type" "sse")
20299 (set_attr "mode" "SF")])
20301 (define_insn "sminv4sf3"
20302 [(set (match_operand:V4SF 0 "register_operand" "=x")
20303 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
20304 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20306 "minps\t{%2, %0|%0, %2}"
20307 [(set_attr "type" "sse")
20308 (set_attr "mode" "V4SF")])
20310 (define_insn "vmsminv4sf3"
20311 [(set (match_operand:V4SF 0 "register_operand" "=x")
20313 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
20314 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20318 "minss\t{%2, %0|%0, %2}"
20319 [(set_attr "type" "sse")
20320 (set_attr "mode" "SF")])
20322 ;; SSE <-> integer/MMX conversions
20324 (define_insn "cvtpi2ps"
20325 [(set (match_operand:V4SF 0 "register_operand" "=x")
20327 (match_operand:V4SF 1 "register_operand" "0")
20328 (vec_duplicate:V4SF
20329 (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym")))
20332 "cvtpi2ps\t{%2, %0|%0, %2}"
20333 [(set_attr "type" "ssecvt")
20334 (set_attr "mode" "V4SF")])
20336 (define_insn "cvtps2pi"
20337 [(set (match_operand:V2SI 0 "register_operand" "=y")
20339 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
20340 (parallel [(const_int 0) (const_int 1)])))]
20342 "cvtps2pi\t{%1, %0|%0, %1}"
20343 [(set_attr "type" "ssecvt")
20344 (set_attr "mode" "V4SF")])
20346 (define_insn "cvttps2pi"
20347 [(set (match_operand:V2SI 0 "register_operand" "=y")
20349 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
20351 (parallel [(const_int 0) (const_int 1)])))]
20353 "cvttps2pi\t{%1, %0|%0, %1}"
20354 [(set_attr "type" "ssecvt")
20355 (set_attr "mode" "SF")])
20357 (define_insn "cvtsi2ss"
20358 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
20360 (match_operand:V4SF 1 "register_operand" "0,0")
20361 (vec_duplicate:V4SF
20362 (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
20365 "cvtsi2ss\t{%2, %0|%0, %2}"
20366 [(set_attr "type" "sseicvt")
20367 (set_attr "athlon_decode" "vector,double")
20368 (set_attr "mode" "SF")])
20370 (define_insn "cvtsi2ssq"
20371 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
20373 (match_operand:V4SF 1 "register_operand" "0,0")
20374 (vec_duplicate:V4SF
20375 (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
20377 "TARGET_SSE && TARGET_64BIT"
20378 "cvtsi2ssq\t{%2, %0|%0, %2}"
20379 [(set_attr "type" "sseicvt")
20380 (set_attr "athlon_decode" "vector,double")
20381 (set_attr "mode" "SF")])
20383 (define_insn "cvtss2si"
20384 [(set (match_operand:SI 0 "register_operand" "=r,r")
20386 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
20387 (parallel [(const_int 0)])))]
20389 "cvtss2si\t{%1, %0|%0, %1}"
20390 [(set_attr "type" "sseicvt")
20391 (set_attr "athlon_decode" "double,vector")
20392 (set_attr "mode" "SI")])
20394 (define_insn "cvtss2siq"
20395 [(set (match_operand:DI 0 "register_operand" "=r,r")
20397 (fix:V4DI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
20398 (parallel [(const_int 0)])))]
20400 "cvtss2siq\t{%1, %0|%0, %1}"
20401 [(set_attr "type" "sseicvt")
20402 (set_attr "athlon_decode" "double,vector")
20403 (set_attr "mode" "DI")])
20405 (define_insn "cvttss2si"
20406 [(set (match_operand:SI 0 "register_operand" "=r,r")
20408 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
20410 (parallel [(const_int 0)])))]
20412 "cvttss2si\t{%1, %0|%0, %1}"
20413 [(set_attr "type" "sseicvt")
20414 (set_attr "mode" "SF")
20415 (set_attr "athlon_decode" "double,vector")])
20417 (define_insn "cvttss2siq"
20418 [(set (match_operand:DI 0 "register_operand" "=r,r")
20420 (unspec:V4DI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
20422 (parallel [(const_int 0)])))]
20423 "TARGET_SSE && TARGET_64BIT"
20424 "cvttss2siq\t{%1, %0|%0, %1}"
20425 [(set_attr "type" "sseicvt")
20426 (set_attr "mode" "SF")
20427 (set_attr "athlon_decode" "double,vector")])
20434 (define_insn "addv8qi3"
20435 [(set (match_operand:V8QI 0 "register_operand" "=y")
20436 (plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
20437 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20439 "paddb\t{%2, %0|%0, %2}"
20440 [(set_attr "type" "mmxadd")
20441 (set_attr "mode" "DI")])
20443 (define_insn "addv4hi3"
20444 [(set (match_operand:V4HI 0 "register_operand" "=y")
20445 (plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
20446 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20448 "paddw\t{%2, %0|%0, %2}"
20449 [(set_attr "type" "mmxadd")
20450 (set_attr "mode" "DI")])
20452 (define_insn "addv2si3"
20453 [(set (match_operand:V2SI 0 "register_operand" "=y")
20454 (plus:V2SI (match_operand:V2SI 1 "register_operand" "%0")
20455 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20457 "paddd\t{%2, %0|%0, %2}"
20458 [(set_attr "type" "mmxadd")
20459 (set_attr "mode" "DI")])
20461 (define_insn "mmx_adddi3"
20462 [(set (match_operand:DI 0 "register_operand" "=y")
20464 [(plus:DI (match_operand:DI 1 "register_operand" "%0")
20465 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20468 "paddq\t{%2, %0|%0, %2}"
20469 [(set_attr "type" "mmxadd")
20470 (set_attr "mode" "DI")])
20472 (define_insn "ssaddv8qi3"
20473 [(set (match_operand:V8QI 0 "register_operand" "=y")
20474 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
20475 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20477 "paddsb\t{%2, %0|%0, %2}"
20478 [(set_attr "type" "mmxadd")
20479 (set_attr "mode" "DI")])
20481 (define_insn "ssaddv4hi3"
20482 [(set (match_operand:V4HI 0 "register_operand" "=y")
20483 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
20484 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20486 "paddsw\t{%2, %0|%0, %2}"
20487 [(set_attr "type" "mmxadd")
20488 (set_attr "mode" "DI")])
20490 (define_insn "usaddv8qi3"
20491 [(set (match_operand:V8QI 0 "register_operand" "=y")
20492 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
20493 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20495 "paddusb\t{%2, %0|%0, %2}"
20496 [(set_attr "type" "mmxadd")
20497 (set_attr "mode" "DI")])
20499 (define_insn "usaddv4hi3"
20500 [(set (match_operand:V4HI 0 "register_operand" "=y")
20501 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
20502 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20504 "paddusw\t{%2, %0|%0, %2}"
20505 [(set_attr "type" "mmxadd")
20506 (set_attr "mode" "DI")])
20508 (define_insn "subv8qi3"
20509 [(set (match_operand:V8QI 0 "register_operand" "=y")
20510 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20511 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20513 "psubb\t{%2, %0|%0, %2}"
20514 [(set_attr "type" "mmxadd")
20515 (set_attr "mode" "DI")])
20517 (define_insn "subv4hi3"
20518 [(set (match_operand:V4HI 0 "register_operand" "=y")
20519 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20520 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20522 "psubw\t{%2, %0|%0, %2}"
20523 [(set_attr "type" "mmxadd")
20524 (set_attr "mode" "DI")])
20526 (define_insn "subv2si3"
20527 [(set (match_operand:V2SI 0 "register_operand" "=y")
20528 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
20529 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20531 "psubd\t{%2, %0|%0, %2}"
20532 [(set_attr "type" "mmxadd")
20533 (set_attr "mode" "DI")])
20535 (define_insn "mmx_subdi3"
20536 [(set (match_operand:DI 0 "register_operand" "=y")
20538 [(minus:DI (match_operand:DI 1 "register_operand" "0")
20539 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20542 "psubq\t{%2, %0|%0, %2}"
20543 [(set_attr "type" "mmxadd")
20544 (set_attr "mode" "DI")])
20546 (define_insn "sssubv8qi3"
20547 [(set (match_operand:V8QI 0 "register_operand" "=y")
20548 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20549 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20551 "psubsb\t{%2, %0|%0, %2}"
20552 [(set_attr "type" "mmxadd")
20553 (set_attr "mode" "DI")])
20555 (define_insn "sssubv4hi3"
20556 [(set (match_operand:V4HI 0 "register_operand" "=y")
20557 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20558 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20560 "psubsw\t{%2, %0|%0, %2}"
20561 [(set_attr "type" "mmxadd")
20562 (set_attr "mode" "DI")])
20564 (define_insn "ussubv8qi3"
20565 [(set (match_operand:V8QI 0 "register_operand" "=y")
20566 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20567 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20569 "psubusb\t{%2, %0|%0, %2}"
20570 [(set_attr "type" "mmxadd")
20571 (set_attr "mode" "DI")])
20573 (define_insn "ussubv4hi3"
20574 [(set (match_operand:V4HI 0 "register_operand" "=y")
20575 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20576 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20578 "psubusw\t{%2, %0|%0, %2}"
20579 [(set_attr "type" "mmxadd")
20580 (set_attr "mode" "DI")])
20582 (define_insn "mulv4hi3"
20583 [(set (match_operand:V4HI 0 "register_operand" "=y")
20584 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
20585 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20587 "pmullw\t{%2, %0|%0, %2}"
20588 [(set_attr "type" "mmxmul")
20589 (set_attr "mode" "DI")])
20591 (define_insn "smulv4hi3_highpart"
20592 [(set (match_operand:V4HI 0 "register_operand" "=y")
20595 (mult:V4SI (sign_extend:V4SI
20596 (match_operand:V4HI 1 "register_operand" "0"))
20598 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
20601 "pmulhw\t{%2, %0|%0, %2}"
20602 [(set_attr "type" "mmxmul")
20603 (set_attr "mode" "DI")])
20605 (define_insn "umulv4hi3_highpart"
20606 [(set (match_operand:V4HI 0 "register_operand" "=y")
20609 (mult:V4SI (zero_extend:V4SI
20610 (match_operand:V4HI 1 "register_operand" "0"))
20612 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
20614 "TARGET_SSE || TARGET_3DNOW_A"
20615 "pmulhuw\t{%2, %0|%0, %2}"
20616 [(set_attr "type" "mmxmul")
20617 (set_attr "mode" "DI")])
20619 (define_insn "mmx_pmaddwd"
20620 [(set (match_operand:V2SI 0 "register_operand" "=y")
20624 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
20625 (parallel [(const_int 0) (const_int 2)])))
20627 (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
20628 (parallel [(const_int 0) (const_int 2)]))))
20630 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
20631 (parallel [(const_int 1)
20633 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
20634 (parallel [(const_int 1)
20635 (const_int 3)]))))))]
20637 "pmaddwd\t{%2, %0|%0, %2}"
20638 [(set_attr "type" "mmxmul")
20639 (set_attr "mode" "DI")])
20642 ;; MMX logical operations
20643 ;; Note we don't want to declare these as regular iordi3 insns to prevent
20644 ;; normal code that also wants to use the FPU from getting broken.
20645 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
20646 (define_insn "mmx_iordi3"
20647 [(set (match_operand:DI 0 "register_operand" "=y")
20649 [(ior:DI (match_operand:DI 1 "register_operand" "%0")
20650 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20653 "por\t{%2, %0|%0, %2}"
20654 [(set_attr "type" "mmxadd")
20655 (set_attr "mode" "DI")])
20657 (define_insn "mmx_xordi3"
20658 [(set (match_operand:DI 0 "register_operand" "=y")
20660 [(xor:DI (match_operand:DI 1 "register_operand" "%0")
20661 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20664 "pxor\t{%2, %0|%0, %2}"
20665 [(set_attr "type" "mmxadd")
20666 (set_attr "mode" "DI")
20667 (set_attr "memory" "none")])
20669 ;; Same as pxor, but don't show input operands so that we don't think
20671 (define_insn "mmx_clrdi"
20672 [(set (match_operand:DI 0 "register_operand" "=y")
20673 (unspec:DI [(const_int 0)] UNSPEC_NOP))]
20675 "pxor\t{%0, %0|%0, %0}"
20676 [(set_attr "type" "mmxadd")
20677 (set_attr "mode" "DI")
20678 (set_attr "memory" "none")])
20680 (define_insn "mmx_anddi3"
20681 [(set (match_operand:DI 0 "register_operand" "=y")
20683 [(and:DI (match_operand:DI 1 "register_operand" "%0")
20684 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20687 "pand\t{%2, %0|%0, %2}"
20688 [(set_attr "type" "mmxadd")
20689 (set_attr "mode" "DI")])
20691 (define_insn "mmx_nanddi3"
20692 [(set (match_operand:DI 0 "register_operand" "=y")
20694 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
20695 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20698 "pandn\t{%2, %0|%0, %2}"
20699 [(set_attr "type" "mmxadd")
20700 (set_attr "mode" "DI")])
20703 ;; MMX unsigned averages/sum of absolute differences
20705 (define_insn "mmx_uavgv8qi3"
20706 [(set (match_operand:V8QI 0 "register_operand" "=y")
20708 (plus:V8QI (plus:V8QI
20709 (match_operand:V8QI 1 "register_operand" "0")
20710 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
20711 (const_vector:V8QI [(const_int 1)
20720 "TARGET_SSE || TARGET_3DNOW_A"
20721 "pavgb\t{%2, %0|%0, %2}"
20722 [(set_attr "type" "mmxshft")
20723 (set_attr "mode" "DI")])
20725 (define_insn "mmx_uavgv4hi3"
20726 [(set (match_operand:V4HI 0 "register_operand" "=y")
20728 (plus:V4HI (plus:V4HI
20729 (match_operand:V4HI 1 "register_operand" "0")
20730 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
20731 (const_vector:V4HI [(const_int 1)
20736 "TARGET_SSE || TARGET_3DNOW_A"
20737 "pavgw\t{%2, %0|%0, %2}"
20738 [(set_attr "type" "mmxshft")
20739 (set_attr "mode" "DI")])
20741 (define_insn "mmx_psadbw"
20742 [(set (match_operand:DI 0 "register_operand" "=y")
20743 (unspec:DI [(match_operand:V8QI 1 "register_operand" "0")
20744 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
20746 "TARGET_SSE || TARGET_3DNOW_A"
20747 "psadbw\t{%2, %0|%0, %2}"
20748 [(set_attr "type" "mmxshft")
20749 (set_attr "mode" "DI")])
20752 ;; MMX insert/extract/shuffle
20754 (define_insn "mmx_pinsrw"
20755 [(set (match_operand:V4HI 0 "register_operand" "=y")
20756 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
20757 (vec_duplicate:V4HI
20758 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
20759 (match_operand:SI 3 "immediate_operand" "i")))]
20760 "TARGET_SSE || TARGET_3DNOW_A"
20761 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
20762 [(set_attr "type" "mmxcvt")
20763 (set_attr "mode" "DI")])
20765 (define_insn "mmx_pextrw"
20766 [(set (match_operand:SI 0 "register_operand" "=r")
20767 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
20769 [(match_operand:SI 2 "immediate_operand" "i")]))))]
20770 "TARGET_SSE || TARGET_3DNOW_A"
20771 "pextrw\t{%2, %1, %0|%0, %1, %2}"
20772 [(set_attr "type" "mmxcvt")
20773 (set_attr "mode" "DI")])
20775 (define_insn "mmx_pshufw"
20776 [(set (match_operand:V4HI 0 "register_operand" "=y")
20777 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
20778 (match_operand:SI 2 "immediate_operand" "i")]
20780 "TARGET_SSE || TARGET_3DNOW_A"
20781 "pshufw\t{%2, %1, %0|%0, %1, %2}"
20782 [(set_attr "type" "mmxcvt")
20783 (set_attr "mode" "DI")])
20786 ;; MMX mask-generating comparisons
20788 (define_insn "eqv8qi3"
20789 [(set (match_operand:V8QI 0 "register_operand" "=y")
20790 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
20791 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20793 "pcmpeqb\t{%2, %0|%0, %2}"
20794 [(set_attr "type" "mmxcmp")
20795 (set_attr "mode" "DI")])
20797 (define_insn "eqv4hi3"
20798 [(set (match_operand:V4HI 0 "register_operand" "=y")
20799 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
20800 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20802 "pcmpeqw\t{%2, %0|%0, %2}"
20803 [(set_attr "type" "mmxcmp")
20804 (set_attr "mode" "DI")])
20806 (define_insn "eqv2si3"
20807 [(set (match_operand:V2SI 0 "register_operand" "=y")
20808 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
20809 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20811 "pcmpeqd\t{%2, %0|%0, %2}"
20812 [(set_attr "type" "mmxcmp")
20813 (set_attr "mode" "DI")])
20815 (define_insn "gtv8qi3"
20816 [(set (match_operand:V8QI 0 "register_operand" "=y")
20817 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
20818 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20820 "pcmpgtb\t{%2, %0|%0, %2}"
20821 [(set_attr "type" "mmxcmp")
20822 (set_attr "mode" "DI")])
20824 (define_insn "gtv4hi3"
20825 [(set (match_operand:V4HI 0 "register_operand" "=y")
20826 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
20827 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20829 "pcmpgtw\t{%2, %0|%0, %2}"
20830 [(set_attr "type" "mmxcmp")
20831 (set_attr "mode" "DI")])
20833 (define_insn "gtv2si3"
20834 [(set (match_operand:V2SI 0 "register_operand" "=y")
20835 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
20836 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20838 "pcmpgtd\t{%2, %0|%0, %2}"
20839 [(set_attr "type" "mmxcmp")
20840 (set_attr "mode" "DI")])
20843 ;; MMX max/min insns
20845 (define_insn "umaxv8qi3"
20846 [(set (match_operand:V8QI 0 "register_operand" "=y")
20847 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
20848 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20849 "TARGET_SSE || TARGET_3DNOW_A"
20850 "pmaxub\t{%2, %0|%0, %2}"
20851 [(set_attr "type" "mmxadd")
20852 (set_attr "mode" "DI")])
20854 (define_insn "smaxv4hi3"
20855 [(set (match_operand:V4HI 0 "register_operand" "=y")
20856 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
20857 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20858 "TARGET_SSE || TARGET_3DNOW_A"
20859 "pmaxsw\t{%2, %0|%0, %2}"
20860 [(set_attr "type" "mmxadd")
20861 (set_attr "mode" "DI")])
20863 (define_insn "uminv8qi3"
20864 [(set (match_operand:V8QI 0 "register_operand" "=y")
20865 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
20866 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20867 "TARGET_SSE || TARGET_3DNOW_A"
20868 "pminub\t{%2, %0|%0, %2}"
20869 [(set_attr "type" "mmxadd")
20870 (set_attr "mode" "DI")])
20872 (define_insn "sminv4hi3"
20873 [(set (match_operand:V4HI 0 "register_operand" "=y")
20874 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
20875 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20876 "TARGET_SSE || TARGET_3DNOW_A"
20877 "pminsw\t{%2, %0|%0, %2}"
20878 [(set_attr "type" "mmxadd")
20879 (set_attr "mode" "DI")])
20884 (define_insn "ashrv4hi3"
20885 [(set (match_operand:V4HI 0 "register_operand" "=y")
20886 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
20887 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20889 "psraw\t{%2, %0|%0, %2}"
20890 [(set_attr "type" "mmxshft")
20891 (set_attr "mode" "DI")])
20893 (define_insn "ashrv2si3"
20894 [(set (match_operand:V2SI 0 "register_operand" "=y")
20895 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
20896 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20898 "psrad\t{%2, %0|%0, %2}"
20899 [(set_attr "type" "mmxshft")
20900 (set_attr "mode" "DI")])
20902 (define_insn "lshrv4hi3"
20903 [(set (match_operand:V4HI 0 "register_operand" "=y")
20904 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
20905 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20907 "psrlw\t{%2, %0|%0, %2}"
20908 [(set_attr "type" "mmxshft")
20909 (set_attr "mode" "DI")])
20911 (define_insn "lshrv2si3"
20912 [(set (match_operand:V2SI 0 "register_operand" "=y")
20913 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
20914 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20916 "psrld\t{%2, %0|%0, %2}"
20917 [(set_attr "type" "mmxshft")
20918 (set_attr "mode" "DI")])
20920 ;; See logical MMX insns.
20921 (define_insn "mmx_lshrdi3"
20922 [(set (match_operand:DI 0 "register_operand" "=y")
20924 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
20925 (match_operand:DI 2 "nonmemory_operand" "yi"))]
20928 "psrlq\t{%2, %0|%0, %2}"
20929 [(set_attr "type" "mmxshft")
20930 (set_attr "mode" "DI")])
20932 (define_insn "ashlv4hi3"
20933 [(set (match_operand:V4HI 0 "register_operand" "=y")
20934 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
20935 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20937 "psllw\t{%2, %0|%0, %2}"
20938 [(set_attr "type" "mmxshft")
20939 (set_attr "mode" "DI")])
20941 (define_insn "ashlv2si3"
20942 [(set (match_operand:V2SI 0 "register_operand" "=y")
20943 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
20944 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20946 "pslld\t{%2, %0|%0, %2}"
20947 [(set_attr "type" "mmxshft")
20948 (set_attr "mode" "DI")])
20950 ;; See logical MMX insns.
20951 (define_insn "mmx_ashldi3"
20952 [(set (match_operand:DI 0 "register_operand" "=y")
20954 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
20955 (match_operand:DI 2 "nonmemory_operand" "yi"))]
20958 "psllq\t{%2, %0|%0, %2}"
20959 [(set_attr "type" "mmxshft")
20960 (set_attr "mode" "DI")])
20963 ;; MMX pack/unpack insns.
20965 (define_insn "mmx_packsswb"
20966 [(set (match_operand:V8QI 0 "register_operand" "=y")
20968 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
20969 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
20971 "packsswb\t{%2, %0|%0, %2}"
20972 [(set_attr "type" "mmxshft")
20973 (set_attr "mode" "DI")])
20975 (define_insn "mmx_packssdw"
20976 [(set (match_operand:V4HI 0 "register_operand" "=y")
20978 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
20979 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
20981 "packssdw\t{%2, %0|%0, %2}"
20982 [(set_attr "type" "mmxshft")
20983 (set_attr "mode" "DI")])
20985 (define_insn "mmx_packuswb"
20986 [(set (match_operand:V8QI 0 "register_operand" "=y")
20988 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
20989 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
20991 "packuswb\t{%2, %0|%0, %2}"
20992 [(set_attr "type" "mmxshft")
20993 (set_attr "mode" "DI")])
20995 (define_insn "mmx_punpckhbw"
20996 [(set (match_operand:V8QI 0 "register_operand" "=y")
20998 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
20999 (parallel [(const_int 4)
21007 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
21008 (parallel [(const_int 0)
21018 "punpckhbw\t{%2, %0|%0, %2}"
21019 [(set_attr "type" "mmxcvt")
21020 (set_attr "mode" "DI")])
21022 (define_insn "mmx_punpckhwd"
21023 [(set (match_operand:V4HI 0 "register_operand" "=y")
21025 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
21026 (parallel [(const_int 0)
21030 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
21031 (parallel [(const_int 2)
21037 "punpckhwd\t{%2, %0|%0, %2}"
21038 [(set_attr "type" "mmxcvt")
21039 (set_attr "mode" "DI")])
21041 (define_insn "mmx_punpckhdq"
21042 [(set (match_operand:V2SI 0 "register_operand" "=y")
21044 (match_operand:V2SI 1 "register_operand" "0")
21045 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
21046 (parallel [(const_int 1)
21050 "punpckhdq\t{%2, %0|%0, %2}"
21051 [(set_attr "type" "mmxcvt")
21052 (set_attr "mode" "DI")])
21054 (define_insn "mmx_punpcklbw"
21055 [(set (match_operand:V8QI 0 "register_operand" "=y")
21057 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
21058 (parallel [(const_int 0)
21066 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
21067 (parallel [(const_int 4)
21077 "punpcklbw\t{%2, %0|%0, %2}"
21078 [(set_attr "type" "mmxcvt")
21079 (set_attr "mode" "DI")])
21081 (define_insn "mmx_punpcklwd"
21082 [(set (match_operand:V4HI 0 "register_operand" "=y")
21084 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
21085 (parallel [(const_int 2)
21089 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
21090 (parallel [(const_int 0)
21096 "punpcklwd\t{%2, %0|%0, %2}"
21097 [(set_attr "type" "mmxcvt")
21098 (set_attr "mode" "DI")])
21100 (define_insn "mmx_punpckldq"
21101 [(set (match_operand:V2SI 0 "register_operand" "=y")
21103 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
21104 (parallel [(const_int 1)
21106 (match_operand:V2SI 2 "register_operand" "y")
21109 "punpckldq\t{%2, %0|%0, %2}"
21110 [(set_attr "type" "mmxcvt")
21111 (set_attr "mode" "DI")])
21114 ;; Miscellaneous stuff
21116 (define_insn "emms"
21117 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
21118 (clobber (reg:XF 8))
21119 (clobber (reg:XF 9))
21120 (clobber (reg:XF 10))
21121 (clobber (reg:XF 11))
21122 (clobber (reg:XF 12))
21123 (clobber (reg:XF 13))
21124 (clobber (reg:XF 14))
21125 (clobber (reg:XF 15))
21126 (clobber (reg:DI 29))
21127 (clobber (reg:DI 30))
21128 (clobber (reg:DI 31))
21129 (clobber (reg:DI 32))
21130 (clobber (reg:DI 33))
21131 (clobber (reg:DI 34))
21132 (clobber (reg:DI 35))
21133 (clobber (reg:DI 36))]
21136 [(set_attr "type" "mmx")
21137 (set_attr "memory" "unknown")])
21139 (define_insn "ldmxcsr"
21140 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
21144 [(set_attr "type" "sse")
21145 (set_attr "memory" "load")])
21147 (define_insn "stmxcsr"
21148 [(set (match_operand:SI 0 "memory_operand" "=m")
21149 (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
21152 [(set_attr "type" "sse")
21153 (set_attr "memory" "store")])
21155 (define_expand "sfence"
21156 [(set (match_dup 0)
21157 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
21158 "TARGET_SSE || TARGET_3DNOW_A"
21160 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
21161 MEM_VOLATILE_P (operands[0]) = 1;
21164 (define_insn "*sfence_insn"
21165 [(set (match_operand:BLK 0 "" "")
21166 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
21167 "TARGET_SSE || TARGET_3DNOW_A"
21169 [(set_attr "type" "sse")
21170 (set_attr "memory" "unknown")])
21172 (define_expand "sse_prologue_save"
21173 [(parallel [(set (match_operand:BLK 0 "" "")
21174 (unspec:BLK [(reg:DI 21)
21181 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
21182 (use (match_operand:DI 1 "register_operand" ""))
21183 (use (match_operand:DI 2 "immediate_operand" ""))
21184 (use (label_ref:DI (match_operand 3 "" "")))])]
21188 (define_insn "*sse_prologue_save_insn"
21189 [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
21190 (match_operand:DI 4 "const_int_operand" "n")))
21191 (unspec:BLK [(reg:DI 21)
21198 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
21199 (use (match_operand:DI 1 "register_operand" "r"))
21200 (use (match_operand:DI 2 "const_int_operand" "i"))
21201 (use (label_ref:DI (match_operand 3 "" "X")))]
21203 && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
21204 && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
21208 operands[0] = gen_rtx_MEM (Pmode,
21209 gen_rtx_PLUS (Pmode, operands[0], operands[4]));
21210 output_asm_insn (\"jmp\\t%A1\", operands);
21211 for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
21213 operands[4] = adjust_address (operands[0], DImode, i*16);
21214 operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
21215 PUT_MODE (operands[4], TImode);
21216 if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
21217 output_asm_insn (\"rex\", operands);
21218 output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands);
21220 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
21221 CODE_LABEL_NUMBER (operands[3]));
21225 [(set_attr "type" "other")
21226 (set_attr "length_immediate" "0")
21227 (set_attr "length_address" "0")
21228 (set_attr "length" "135")
21229 (set_attr "memory" "store")
21230 (set_attr "modrm" "0")
21231 (set_attr "mode" "DI")])
21233 ;; 3Dnow! instructions
21235 (define_insn "addv2sf3"
21236 [(set (match_operand:V2SF 0 "register_operand" "=y")
21237 (plus:V2SF (match_operand:V2SF 1 "register_operand" "0")
21238 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21240 "pfadd\\t{%2, %0|%0, %2}"
21241 [(set_attr "type" "mmxadd")
21242 (set_attr "mode" "V2SF")])
21244 (define_insn "subv2sf3"
21245 [(set (match_operand:V2SF 0 "register_operand" "=y")
21246 (minus:V2SF (match_operand:V2SF 1 "register_operand" "0")
21247 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21249 "pfsub\\t{%2, %0|%0, %2}"
21250 [(set_attr "type" "mmxadd")
21251 (set_attr "mode" "V2SF")])
21253 (define_insn "subrv2sf3"
21254 [(set (match_operand:V2SF 0 "register_operand" "=y")
21255 (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "ym")
21256 (match_operand:V2SF 1 "register_operand" "0")))]
21258 "pfsubr\\t{%2, %0|%0, %2}"
21259 [(set_attr "type" "mmxadd")
21260 (set_attr "mode" "V2SF")])
21262 (define_insn "gtv2sf3"
21263 [(set (match_operand:V2SI 0 "register_operand" "=y")
21264 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
21265 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21267 "pfcmpgt\\t{%2, %0|%0, %2}"
21268 [(set_attr "type" "mmxcmp")
21269 (set_attr "mode" "V2SF")])
21271 (define_insn "gev2sf3"
21272 [(set (match_operand:V2SI 0 "register_operand" "=y")
21273 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
21274 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21276 "pfcmpge\\t{%2, %0|%0, %2}"
21277 [(set_attr "type" "mmxcmp")
21278 (set_attr "mode" "V2SF")])
21280 (define_insn "eqv2sf3"
21281 [(set (match_operand:V2SI 0 "register_operand" "=y")
21282 (eq:V2SI (match_operand:V2SF 1 "register_operand" "0")
21283 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21285 "pfcmpeq\\t{%2, %0|%0, %2}"
21286 [(set_attr "type" "mmxcmp")
21287 (set_attr "mode" "V2SF")])
21289 (define_insn "pfmaxv2sf3"
21290 [(set (match_operand:V2SF 0 "register_operand" "=y")
21291 (smax:V2SF (match_operand:V2SF 1 "register_operand" "0")
21292 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21294 "pfmax\\t{%2, %0|%0, %2}"
21295 [(set_attr "type" "mmxadd")
21296 (set_attr "mode" "V2SF")])
21298 (define_insn "pfminv2sf3"
21299 [(set (match_operand:V2SF 0 "register_operand" "=y")
21300 (smin:V2SF (match_operand:V2SF 1 "register_operand" "0")
21301 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21303 "pfmin\\t{%2, %0|%0, %2}"
21304 [(set_attr "type" "mmxadd")
21305 (set_attr "mode" "V2SF")])
21307 (define_insn "mulv2sf3"
21308 [(set (match_operand:V2SF 0 "register_operand" "=y")
21309 (mult:V2SF (match_operand:V2SF 1 "register_operand" "0")
21310 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21312 "pfmul\\t{%2, %0|%0, %2}"
21313 [(set_attr "type" "mmxmul")
21314 (set_attr "mode" "V2SF")])
21316 (define_insn "femms"
21317 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
21318 (clobber (reg:XF 8))
21319 (clobber (reg:XF 9))
21320 (clobber (reg:XF 10))
21321 (clobber (reg:XF 11))
21322 (clobber (reg:XF 12))
21323 (clobber (reg:XF 13))
21324 (clobber (reg:XF 14))
21325 (clobber (reg:XF 15))
21326 (clobber (reg:DI 29))
21327 (clobber (reg:DI 30))
21328 (clobber (reg:DI 31))
21329 (clobber (reg:DI 32))
21330 (clobber (reg:DI 33))
21331 (clobber (reg:DI 34))
21332 (clobber (reg:DI 35))
21333 (clobber (reg:DI 36))]
21336 [(set_attr "type" "mmx")
21337 (set_attr "memory" "none")])
21339 (define_insn "pf2id"
21340 [(set (match_operand:V2SI 0 "register_operand" "=y")
21341 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
21343 "pf2id\\t{%1, %0|%0, %1}"
21344 [(set_attr "type" "mmxcvt")
21345 (set_attr "mode" "V2SF")])
21347 (define_insn "pf2iw"
21348 [(set (match_operand:V2SI 0 "register_operand" "=y")
21351 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
21353 "pf2iw\\t{%1, %0|%0, %1}"
21354 [(set_attr "type" "mmxcvt")
21355 (set_attr "mode" "V2SF")])
21357 (define_insn "pfacc"
21358 [(set (match_operand:V2SF 0 "register_operand" "=y")
21361 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
21362 (parallel [(const_int 0)]))
21363 (vec_select:SF (match_dup 1)
21364 (parallel [(const_int 1)])))
21366 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
21367 (parallel [(const_int 0)]))
21368 (vec_select:SF (match_dup 2)
21369 (parallel [(const_int 1)])))))]
21371 "pfacc\\t{%2, %0|%0, %2}"
21372 [(set_attr "type" "mmxadd")
21373 (set_attr "mode" "V2SF")])
21375 (define_insn "pfnacc"
21376 [(set (match_operand:V2SF 0 "register_operand" "=y")
21379 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
21380 (parallel [(const_int 0)]))
21381 (vec_select:SF (match_dup 1)
21382 (parallel [(const_int 1)])))
21384 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
21385 (parallel [(const_int 0)]))
21386 (vec_select:SF (match_dup 2)
21387 (parallel [(const_int 1)])))))]
21389 "pfnacc\\t{%2, %0|%0, %2}"
21390 [(set_attr "type" "mmxadd")
21391 (set_attr "mode" "V2SF")])
21393 (define_insn "pfpnacc"
21394 [(set (match_operand:V2SF 0 "register_operand" "=y")
21397 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
21398 (parallel [(const_int 0)]))
21399 (vec_select:SF (match_dup 1)
21400 (parallel [(const_int 1)])))
21402 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
21403 (parallel [(const_int 0)]))
21404 (vec_select:SF (match_dup 2)
21405 (parallel [(const_int 1)])))))]
21407 "pfpnacc\\t{%2, %0|%0, %2}"
21408 [(set_attr "type" "mmxadd")
21409 (set_attr "mode" "V2SF")])
21411 (define_insn "pi2fw"
21412 [(set (match_operand:V2SF 0 "register_operand" "=y")
21417 (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
21418 (parallel [(const_int 0)]))))
21421 (vec_select:SI (match_dup 1)
21422 (parallel [(const_int 1)])))))))]
21424 "pi2fw\\t{%1, %0|%0, %1}"
21425 [(set_attr "type" "mmxcvt")
21426 (set_attr "mode" "V2SF")])
21428 (define_insn "floatv2si2"
21429 [(set (match_operand:V2SF 0 "register_operand" "=y")
21430 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
21432 "pi2fd\\t{%1, %0|%0, %1}"
21433 [(set_attr "type" "mmxcvt")
21434 (set_attr "mode" "V2SF")])
21436 ;; This insn is identical to pavgb in operation, but the opcode is
21437 ;; different. To avoid accidentally matching pavgb, use an unspec.
21439 (define_insn "pavgusb"
21440 [(set (match_operand:V8QI 0 "register_operand" "=y")
21442 [(match_operand:V8QI 1 "register_operand" "0")
21443 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
21446 "pavgusb\\t{%2, %0|%0, %2}"
21447 [(set_attr "type" "mmxshft")
21448 (set_attr "mode" "TI")])
21450 ;; 3DNow reciprocal and sqrt
21452 (define_insn "pfrcpv2sf2"
21453 [(set (match_operand:V2SF 0 "register_operand" "=y")
21454 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
21457 "pfrcp\\t{%1, %0|%0, %1}"
21458 [(set_attr "type" "mmx")
21459 (set_attr "mode" "TI")])
21461 (define_insn "pfrcpit1v2sf3"
21462 [(set (match_operand:V2SF 0 "register_operand" "=y")
21463 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
21464 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
21467 "pfrcpit1\\t{%2, %0|%0, %2}"
21468 [(set_attr "type" "mmx")
21469 (set_attr "mode" "TI")])
21471 (define_insn "pfrcpit2v2sf3"
21472 [(set (match_operand:V2SF 0 "register_operand" "=y")
21473 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
21474 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
21477 "pfrcpit2\\t{%2, %0|%0, %2}"
21478 [(set_attr "type" "mmx")
21479 (set_attr "mode" "TI")])
21481 (define_insn "pfrsqrtv2sf2"
21482 [(set (match_operand:V2SF 0 "register_operand" "=y")
21483 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
21486 "pfrsqrt\\t{%1, %0|%0, %1}"
21487 [(set_attr "type" "mmx")
21488 (set_attr "mode" "TI")])
21490 (define_insn "pfrsqit1v2sf3"
21491 [(set (match_operand:V2SF 0 "register_operand" "=y")
21492 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
21493 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
21496 "pfrsqit1\\t{%2, %0|%0, %2}"
21497 [(set_attr "type" "mmx")
21498 (set_attr "mode" "TI")])
21500 (define_insn "pmulhrwv4hi3"
21501 [(set (match_operand:V4HI 0 "register_operand" "=y")
21507 (match_operand:V4HI 1 "register_operand" "0"))
21509 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
21510 (const_vector:V4SI [(const_int 32768)
21513 (const_int 32768)]))
21516 "pmulhrw\\t{%2, %0|%0, %2}"
21517 [(set_attr "type" "mmxmul")
21518 (set_attr "mode" "TI")])
21520 (define_insn "pswapdv2si2"
21521 [(set (match_operand:V2SI 0 "register_operand" "=y")
21522 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
21523 (parallel [(const_int 1) (const_int 0)])))]
21525 "pswapd\\t{%1, %0|%0, %1}"
21526 [(set_attr "type" "mmxcvt")
21527 (set_attr "mode" "TI")])
21529 (define_insn "pswapdv2sf2"
21530 [(set (match_operand:V2SF 0 "register_operand" "=y")
21531 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
21532 (parallel [(const_int 1) (const_int 0)])))]
21534 "pswapd\\t{%1, %0|%0, %1}"
21535 [(set_attr "type" "mmxcvt")
21536 (set_attr "mode" "TI")])
21538 (define_expand "prefetch"
21539 [(prefetch (match_operand 0 "address_operand" "")
21540 (match_operand:SI 1 "const_int_operand" "")
21541 (match_operand:SI 2 "const_int_operand" ""))]
21542 "TARGET_PREFETCH_SSE || TARGET_3DNOW"
21544 int rw = INTVAL (operands[1]);
21545 int locality = INTVAL (operands[2]);
21547 if (rw != 0 && rw != 1)
21549 if (locality < 0 || locality > 3)
21551 if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
21554 /* Use 3dNOW prefetch in case we are asking for write prefetch not
21555 suported by SSE counterpart or the SSE prefetch is not available
21556 (K6 machines). Otherwise use SSE prefetch as it allows specifying
21558 if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
21559 operands[2] = GEN_INT (3);
21561 operands[1] = const0_rtx;
21564 (define_insn "*prefetch_sse"
21565 [(prefetch (match_operand:SI 0 "address_operand" "p")
21567 (match_operand:SI 1 "const_int_operand" ""))]
21568 "TARGET_PREFETCH_SSE && !TARGET_64BIT"
21570 static const char * const patterns[4] = {
21571 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
21574 int locality = INTVAL (operands[1]);
21575 if (locality < 0 || locality > 3)
21578 return patterns[locality];
21580 [(set_attr "type" "sse")
21581 (set_attr "memory" "none")])
21583 (define_insn "*prefetch_sse_rex"
21584 [(prefetch (match_operand:DI 0 "address_operand" "p")
21586 (match_operand:SI 1 "const_int_operand" ""))]
21587 "TARGET_PREFETCH_SSE && TARGET_64BIT"
21589 static const char * const patterns[4] = {
21590 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
21593 int locality = INTVAL (operands[1]);
21594 if (locality < 0 || locality > 3)
21597 return patterns[locality];
21599 [(set_attr "type" "sse")
21600 (set_attr "memory" "none")])
21602 (define_insn "*prefetch_3dnow"
21603 [(prefetch (match_operand:SI 0 "address_operand" "p")
21604 (match_operand:SI 1 "const_int_operand" "n")
21606 "TARGET_3DNOW && !TARGET_64BIT"
21608 if (INTVAL (operands[1]) == 0)
21609 return "prefetch\t%a0";
21611 return "prefetchw\t%a0";
21613 [(set_attr "type" "mmx")
21614 (set_attr "memory" "none")])
21616 (define_insn "*prefetch_3dnow_rex"
21617 [(prefetch (match_operand:DI 0 "address_operand" "p")
21618 (match_operand:SI 1 "const_int_operand" "n")
21620 "TARGET_3DNOW && TARGET_64BIT"
21622 if (INTVAL (operands[1]) == 0)
21623 return "prefetch\t%a0";
21625 return "prefetchw\t%a0";
21627 [(set_attr "type" "mmx")
21628 (set_attr "memory" "none")])
21632 (define_insn "addv2df3"
21633 [(set (match_operand:V2DF 0 "register_operand" "=x")
21634 (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21635 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21637 "addpd\t{%2, %0|%0, %2}"
21638 [(set_attr "type" "sseadd")
21639 (set_attr "mode" "V2DF")])
21641 (define_insn "vmaddv2df3"
21642 [(set (match_operand:V2DF 0 "register_operand" "=x")
21643 (vec_merge:V2DF (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21644 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21648 "addsd\t{%2, %0|%0, %2}"
21649 [(set_attr "type" "sseadd")
21650 (set_attr "mode" "DF")])
21652 (define_insn "subv2df3"
21653 [(set (match_operand:V2DF 0 "register_operand" "=x")
21654 (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21655 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21657 "subpd\t{%2, %0|%0, %2}"
21658 [(set_attr "type" "sseadd")
21659 (set_attr "mode" "V2DF")])
21661 (define_insn "vmsubv2df3"
21662 [(set (match_operand:V2DF 0 "register_operand" "=x")
21663 (vec_merge:V2DF (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21664 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21668 "subsd\t{%2, %0|%0, %2}"
21669 [(set_attr "type" "sseadd")
21670 (set_attr "mode" "DF")])
21672 (define_insn "mulv2df3"
21673 [(set (match_operand:V2DF 0 "register_operand" "=x")
21674 (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
21675 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21677 "mulpd\t{%2, %0|%0, %2}"
21678 [(set_attr "type" "ssemul")
21679 (set_attr "mode" "V2DF")])
21681 (define_insn "vmmulv2df3"
21682 [(set (match_operand:V2DF 0 "register_operand" "=x")
21683 (vec_merge:V2DF (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
21684 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21688 "mulsd\t{%2, %0|%0, %2}"
21689 [(set_attr "type" "ssemul")
21690 (set_attr "mode" "DF")])
21692 (define_insn "divv2df3"
21693 [(set (match_operand:V2DF 0 "register_operand" "=x")
21694 (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
21695 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21697 "divpd\t{%2, %0|%0, %2}"
21698 [(set_attr "type" "ssediv")
21699 (set_attr "mode" "V2DF")])
21701 (define_insn "vmdivv2df3"
21702 [(set (match_operand:V2DF 0 "register_operand" "=x")
21703 (vec_merge:V2DF (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
21704 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21708 "divsd\t{%2, %0|%0, %2}"
21709 [(set_attr "type" "ssediv")
21710 (set_attr "mode" "DF")])
21714 (define_insn "smaxv2df3"
21715 [(set (match_operand:V2DF 0 "register_operand" "=x")
21716 (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
21717 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21719 "maxpd\t{%2, %0|%0, %2}"
21720 [(set_attr "type" "sseadd")
21721 (set_attr "mode" "V2DF")])
21723 (define_insn "vmsmaxv2df3"
21724 [(set (match_operand:V2DF 0 "register_operand" "=x")
21725 (vec_merge:V2DF (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
21726 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21730 "maxsd\t{%2, %0|%0, %2}"
21731 [(set_attr "type" "sseadd")
21732 (set_attr "mode" "DF")])
21734 (define_insn "sminv2df3"
21735 [(set (match_operand:V2DF 0 "register_operand" "=x")
21736 (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
21737 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21739 "minpd\t{%2, %0|%0, %2}"
21740 [(set_attr "type" "sseadd")
21741 (set_attr "mode" "V2DF")])
21743 (define_insn "vmsminv2df3"
21744 [(set (match_operand:V2DF 0 "register_operand" "=x")
21745 (vec_merge:V2DF (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
21746 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21750 "minsd\t{%2, %0|%0, %2}"
21751 [(set_attr "type" "sseadd")
21752 (set_attr "mode" "DF")])
21753 ;; SSE2 square root. There doesn't appear to be an extension for the
21754 ;; reciprocal/rsqrt instructions if the Intel manual is to be believed.
21756 (define_insn "sqrtv2df2"
21757 [(set (match_operand:V2DF 0 "register_operand" "=x")
21758 (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")))]
21760 "sqrtpd\t{%1, %0|%0, %1}"
21761 [(set_attr "type" "sse")
21762 (set_attr "mode" "V2DF")])
21764 (define_insn "vmsqrtv2df2"
21765 [(set (match_operand:V2DF 0 "register_operand" "=x")
21766 (vec_merge:V2DF (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm"))
21767 (match_operand:V2DF 2 "register_operand" "0")
21770 "sqrtsd\t{%1, %0|%0, %1}"
21771 [(set_attr "type" "sse")
21772 (set_attr "mode" "SF")])
21774 ;; SSE mask-generating compares
21776 (define_insn "maskcmpv2df3"
21777 [(set (match_operand:V2DI 0 "register_operand" "=x")
21778 (match_operator:V2DI 3 "sse_comparison_operator"
21779 [(match_operand:V2DF 1 "register_operand" "0")
21780 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))]
21782 "cmp%D3pd\t{%2, %0|%0, %2}"
21783 [(set_attr "type" "ssecmp")
21784 (set_attr "mode" "V2DF")])
21786 (define_insn "maskncmpv2df3"
21787 [(set (match_operand:V2DI 0 "register_operand" "=x")
21789 (match_operator:V2DI 3 "sse_comparison_operator"
21790 [(match_operand:V2DF 1 "register_operand" "0")
21791 (match_operand:V2DF 2 "nonimmediate_operand" "x")])))]
21794 if (GET_CODE (operands[3]) == UNORDERED)
21795 return "cmpordps\t{%2, %0|%0, %2}";
21797 return "cmpn%D3pd\t{%2, %0|%0, %2}";
21799 [(set_attr "type" "ssecmp")
21800 (set_attr "mode" "V2DF")])
21802 (define_insn "vmmaskcmpv2df3"
21803 [(set (match_operand:V2DI 0 "register_operand" "=x")
21805 (match_operator:V2DI 3 "sse_comparison_operator"
21806 [(match_operand:V2DF 1 "register_operand" "0")
21807 (match_operand:V2DF 2 "nonimmediate_operand" "x")])
21808 (subreg:V2DI (match_dup 1) 0)
21811 "cmp%D3sd\t{%2, %0|%0, %2}"
21812 [(set_attr "type" "ssecmp")
21813 (set_attr "mode" "DF")])
21815 (define_insn "vmmaskncmpv2df3"
21816 [(set (match_operand:V2DI 0 "register_operand" "=x")
21819 (match_operator:V2DI 3 "sse_comparison_operator"
21820 [(match_operand:V2DF 1 "register_operand" "0")
21821 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))
21822 (subreg:V2DI (match_dup 1) 0)
21826 if (GET_CODE (operands[3]) == UNORDERED)
21827 return "cmpordsd\t{%2, %0|%0, %2}";
21829 return "cmpn%D3sd\t{%2, %0|%0, %2}";
21831 [(set_attr "type" "ssecmp")
21832 (set_attr "mode" "DF")])
21834 (define_insn "sse2_comi"
21835 [(set (reg:CCFP 17)
21836 (compare:CCFP (vec_select:DF
21837 (match_operand:V2DF 0 "register_operand" "x")
21838 (parallel [(const_int 0)]))
21840 (match_operand:V2DF 1 "register_operand" "x")
21841 (parallel [(const_int 0)]))))]
21843 "comisd\t{%1, %0|%0, %1}"
21844 [(set_attr "type" "ssecomi")
21845 (set_attr "mode" "DF")])
21847 (define_insn "sse2_ucomi"
21848 [(set (reg:CCFPU 17)
21849 (compare:CCFPU (vec_select:DF
21850 (match_operand:V2DF 0 "register_operand" "x")
21851 (parallel [(const_int 0)]))
21853 (match_operand:V2DF 1 "register_operand" "x")
21854 (parallel [(const_int 0)]))))]
21856 "ucomisd\t{%1, %0|%0, %1}"
21857 [(set_attr "type" "ssecomi")
21858 (set_attr "mode" "DF")])
21860 ;; SSE Strange Moves.
21862 (define_insn "sse2_movmskpd"
21863 [(set (match_operand:SI 0 "register_operand" "=r")
21864 (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")]
21867 "movmskpd\t{%1, %0|%0, %1}"
21868 [(set_attr "type" "ssecvt")
21869 (set_attr "mode" "V2DF")])
21871 (define_insn "sse2_pmovmskb"
21872 [(set (match_operand:SI 0 "register_operand" "=r")
21873 (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
21876 "pmovmskb\t{%1, %0|%0, %1}"
21877 [(set_attr "type" "ssecvt")
21878 (set_attr "mode" "V2DF")])
21880 (define_insn "sse2_maskmovdqu"
21881 [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
21882 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
21883 (match_operand:V16QI 2 "register_operand" "x")]
21886 ;; @@@ check ordering of operands in intel/nonintel syntax
21887 "maskmovdqu\t{%2, %1|%1, %2}"
21888 [(set_attr "type" "ssecvt")
21889 (set_attr "mode" "TI")])
21891 (define_insn "sse2_maskmovdqu_rex64"
21892 [(set (mem:V16QI (match_operand:DI 0 "register_operand" "D"))
21893 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
21894 (match_operand:V16QI 2 "register_operand" "x")]
21897 ;; @@@ check ordering of operands in intel/nonintel syntax
21898 "maskmovdqu\t{%2, %1|%1, %2}"
21899 [(set_attr "type" "ssecvt")
21900 (set_attr "mode" "TI")])
21902 (define_insn "sse2_movntv2df"
21903 [(set (match_operand:V2DF 0 "memory_operand" "=m")
21904 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")]
21907 "movntpd\t{%1, %0|%0, %1}"
21908 [(set_attr "type" "ssecvt")
21909 (set_attr "mode" "V2DF")])
21911 (define_insn "sse2_movntv2di"
21912 [(set (match_operand:V2DI 0 "memory_operand" "=m")
21913 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
21916 "movntdq\t{%1, %0|%0, %1}"
21917 [(set_attr "type" "ssecvt")
21918 (set_attr "mode" "TI")])
21920 (define_insn "sse2_movntsi"
21921 [(set (match_operand:SI 0 "memory_operand" "=m")
21922 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
21925 "movnti\t{%1, %0|%0, %1}"
21926 [(set_attr "type" "ssecvt")
21927 (set_attr "mode" "V2DF")])
21929 ;; SSE <-> integer/MMX conversions
21931 ;; Conversions between SI and SF
21933 (define_insn "cvtdq2ps"
21934 [(set (match_operand:V4SF 0 "register_operand" "=x")
21935 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
21937 "cvtdq2ps\t{%1, %0|%0, %1}"
21938 [(set_attr "type" "ssecvt")
21939 (set_attr "mode" "V2DF")])
21941 (define_insn "cvtps2dq"
21942 [(set (match_operand:V4SI 0 "register_operand" "=x")
21943 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
21945 "cvtps2dq\t{%1, %0|%0, %1}"
21946 [(set_attr "type" "ssecvt")
21947 (set_attr "mode" "TI")])
21949 (define_insn "cvttps2dq"
21950 [(set (match_operand:V4SI 0 "register_operand" "=x")
21951 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
21954 "cvttps2dq\t{%1, %0|%0, %1}"
21955 [(set_attr "type" "ssecvt")
21956 (set_attr "mode" "TI")])
21958 ;; Conversions between SI and DF
21960 (define_insn "cvtdq2pd"
21961 [(set (match_operand:V2DF 0 "register_operand" "=x")
21962 (float:V2DF (vec_select:V2SI
21963 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
21966 (const_int 1)]))))]
21968 "cvtdq2pd\t{%1, %0|%0, %1}"
21969 [(set_attr "type" "ssecvt")
21970 (set_attr "mode" "V2DF")])
21972 (define_insn "cvtpd2dq"
21973 [(set (match_operand:V4SI 0 "register_operand" "=x")
21975 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
21976 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
21978 "cvtpd2dq\t{%1, %0|%0, %1}"
21979 [(set_attr "type" "ssecvt")
21980 (set_attr "mode" "TI")])
21982 (define_insn "cvttpd2dq"
21983 [(set (match_operand:V4SI 0 "register_operand" "=x")
21985 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
21987 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
21989 "cvttpd2dq\t{%1, %0|%0, %1}"
21990 [(set_attr "type" "ssecvt")
21991 (set_attr "mode" "TI")])
21993 (define_insn "cvtpd2pi"
21994 [(set (match_operand:V2SI 0 "register_operand" "=y")
21995 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
21997 "cvtpd2pi\t{%1, %0|%0, %1}"
21998 [(set_attr "type" "ssecvt")
21999 (set_attr "mode" "TI")])
22001 (define_insn "cvttpd2pi"
22002 [(set (match_operand:V2SI 0 "register_operand" "=y")
22003 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
22006 "cvttpd2pi\t{%1, %0|%0, %1}"
22007 [(set_attr "type" "ssecvt")
22008 (set_attr "mode" "TI")])
22010 (define_insn "cvtpi2pd"
22011 [(set (match_operand:V2DF 0 "register_operand" "=x")
22012 (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
22014 "cvtpi2pd\t{%1, %0|%0, %1}"
22015 [(set_attr "type" "ssecvt")
22016 (set_attr "mode" "TI")])
22018 ;; Conversions between SI and DF
22020 (define_insn "cvtsd2si"
22021 [(set (match_operand:SI 0 "register_operand" "=r,r")
22022 (fix:SI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
22023 (parallel [(const_int 0)]))))]
22025 "cvtsd2si\t{%1, %0|%0, %1}"
22026 [(set_attr "type" "sseicvt")
22027 (set_attr "athlon_decode" "double,vector")
22028 (set_attr "mode" "SI")])
22030 (define_insn "cvtsd2siq"
22031 [(set (match_operand:DI 0 "register_operand" "=r,r")
22032 (fix:DI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
22033 (parallel [(const_int 0)]))))]
22034 "TARGET_SSE2 && TARGET_64BIT"
22035 "cvtsd2siq\t{%1, %0|%0, %1}"
22036 [(set_attr "type" "sseicvt")
22037 (set_attr "athlon_decode" "double,vector")
22038 (set_attr "mode" "DI")])
22040 (define_insn "cvttsd2si"
22041 [(set (match_operand:SI 0 "register_operand" "=r,r")
22042 (unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
22043 (parallel [(const_int 0)]))] UNSPEC_FIX))]
22045 "cvttsd2si\t{%1, %0|%0, %1}"
22046 [(set_attr "type" "sseicvt")
22047 (set_attr "mode" "SI")
22048 (set_attr "athlon_decode" "double,vector")])
22050 (define_insn "cvttsd2siq"
22051 [(set (match_operand:DI 0 "register_operand" "=r,r")
22052 (unspec:DI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
22053 (parallel [(const_int 0)]))] UNSPEC_FIX))]
22054 "TARGET_SSE2 && TARGET_64BIT"
22055 "cvttsd2siq\t{%1, %0|%0, %1}"
22056 [(set_attr "type" "sseicvt")
22057 (set_attr "mode" "DI")
22058 (set_attr "athlon_decode" "double,vector")])
22060 (define_insn "cvtsi2sd"
22061 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
22062 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
22063 (vec_duplicate:V2DF
22065 (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
22068 "cvtsi2sd\t{%2, %0|%0, %2}"
22069 [(set_attr "type" "sseicvt")
22070 (set_attr "mode" "DF")
22071 (set_attr "athlon_decode" "double,direct")])
22073 (define_insn "cvtsi2sdq"
22074 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
22075 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
22076 (vec_duplicate:V2DF
22078 (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
22080 "TARGET_SSE2 && TARGET_64BIT"
22081 "cvtsi2sdq\t{%2, %0|%0, %2}"
22082 [(set_attr "type" "sseicvt")
22083 (set_attr "mode" "DF")
22084 (set_attr "athlon_decode" "double,direct")])
22086 ;; Conversions between SF and DF
22088 (define_insn "cvtsd2ss"
22089 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
22090 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0,0")
22091 (vec_duplicate:V4SF
22092 (float_truncate:V2SF
22093 (match_operand:V2DF 2 "nonimmediate_operand" "x,xm")))
22096 "cvtsd2ss\t{%2, %0|%0, %2}"
22097 [(set_attr "type" "ssecvt")
22098 (set_attr "athlon_decode" "vector,double")
22099 (set_attr "mode" "SF")])
22101 (define_insn "cvtss2sd"
22102 [(set (match_operand:V2DF 0 "register_operand" "=x")
22103 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0")
22106 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
22107 (parallel [(const_int 0)
22111 "cvtss2sd\t{%2, %0|%0, %2}"
22112 [(set_attr "type" "ssecvt")
22113 (set_attr "mode" "DF")])
22115 (define_insn "cvtpd2ps"
22116 [(set (match_operand:V4SF 0 "register_operand" "=x")
22119 (subreg:V2SI (float_truncate:V2SF
22120 (match_operand:V2DF 1 "nonimmediate_operand" "xm")) 0)
22121 (const_vector:V2SI [(const_int 0) (const_int 0)])) 0))]
22123 "cvtpd2ps\t{%1, %0|%0, %1}"
22124 [(set_attr "type" "ssecvt")
22125 (set_attr "mode" "V4SF")])
22127 (define_insn "cvtps2pd"
22128 [(set (match_operand:V2DF 0 "register_operand" "=x")
22130 (vec_select:V2SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")
22131 (parallel [(const_int 0)
22132 (const_int 1)]))))]
22134 "cvtps2pd\t{%1, %0|%0, %1}"
22135 [(set_attr "type" "ssecvt")
22136 (set_attr "mode" "V2DF")])
22138 ;; SSE2 variants of MMX insns
22142 (define_insn "addv16qi3"
22143 [(set (match_operand:V16QI 0 "register_operand" "=x")
22144 (plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
22145 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22147 "paddb\t{%2, %0|%0, %2}"
22148 [(set_attr "type" "sseiadd")
22149 (set_attr "mode" "TI")])
22151 (define_insn "addv8hi3"
22152 [(set (match_operand:V8HI 0 "register_operand" "=x")
22153 (plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
22154 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22156 "paddw\t{%2, %0|%0, %2}"
22157 [(set_attr "type" "sseiadd")
22158 (set_attr "mode" "TI")])
22160 (define_insn "addv4si3"
22161 [(set (match_operand:V4SI 0 "register_operand" "=x")
22162 (plus:V4SI (match_operand:V4SI 1 "register_operand" "%0")
22163 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22165 "paddd\t{%2, %0|%0, %2}"
22166 [(set_attr "type" "sseiadd")
22167 (set_attr "mode" "TI")])
22169 (define_insn "addv2di3"
22170 [(set (match_operand:V2DI 0 "register_operand" "=x")
22171 (plus:V2DI (match_operand:V2DI 1 "register_operand" "%0")
22172 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
22174 "paddq\t{%2, %0|%0, %2}"
22175 [(set_attr "type" "sseiadd")
22176 (set_attr "mode" "TI")])
22178 (define_insn "ssaddv16qi3"
22179 [(set (match_operand:V16QI 0 "register_operand" "=x")
22180 (ss_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
22181 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22183 "paddsb\t{%2, %0|%0, %2}"
22184 [(set_attr "type" "sseiadd")
22185 (set_attr "mode" "TI")])
22187 (define_insn "ssaddv8hi3"
22188 [(set (match_operand:V8HI 0 "register_operand" "=x")
22189 (ss_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
22190 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22192 "paddsw\t{%2, %0|%0, %2}"
22193 [(set_attr "type" "sseiadd")
22194 (set_attr "mode" "TI")])
22196 (define_insn "usaddv16qi3"
22197 [(set (match_operand:V16QI 0 "register_operand" "=x")
22198 (us_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
22199 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22201 "paddusb\t{%2, %0|%0, %2}"
22202 [(set_attr "type" "sseiadd")
22203 (set_attr "mode" "TI")])
22205 (define_insn "usaddv8hi3"
22206 [(set (match_operand:V8HI 0 "register_operand" "=x")
22207 (us_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
22208 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22210 "paddusw\t{%2, %0|%0, %2}"
22211 [(set_attr "type" "sseiadd")
22212 (set_attr "mode" "TI")])
22214 (define_insn "subv16qi3"
22215 [(set (match_operand:V16QI 0 "register_operand" "=x")
22216 (minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
22217 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22219 "psubb\t{%2, %0|%0, %2}"
22220 [(set_attr "type" "sseiadd")
22221 (set_attr "mode" "TI")])
22223 (define_insn "subv8hi3"
22224 [(set (match_operand:V8HI 0 "register_operand" "=x")
22225 (minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
22226 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22228 "psubw\t{%2, %0|%0, %2}"
22229 [(set_attr "type" "sseiadd")
22230 (set_attr "mode" "TI")])
22232 (define_insn "subv4si3"
22233 [(set (match_operand:V4SI 0 "register_operand" "=x")
22234 (minus:V4SI (match_operand:V4SI 1 "register_operand" "0")
22235 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22237 "psubd\t{%2, %0|%0, %2}"
22238 [(set_attr "type" "sseiadd")
22239 (set_attr "mode" "TI")])
22241 (define_insn "subv2di3"
22242 [(set (match_operand:V2DI 0 "register_operand" "=x")
22243 (minus:V2DI (match_operand:V2DI 1 "register_operand" "0")
22244 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
22246 "psubq\t{%2, %0|%0, %2}"
22247 [(set_attr "type" "sseiadd")
22248 (set_attr "mode" "TI")])
22250 (define_insn "sssubv16qi3"
22251 [(set (match_operand:V16QI 0 "register_operand" "=x")
22252 (ss_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
22253 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22255 "psubsb\t{%2, %0|%0, %2}"
22256 [(set_attr "type" "sseiadd")
22257 (set_attr "mode" "TI")])
22259 (define_insn "sssubv8hi3"
22260 [(set (match_operand:V8HI 0 "register_operand" "=x")
22261 (ss_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
22262 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22264 "psubsw\t{%2, %0|%0, %2}"
22265 [(set_attr "type" "sseiadd")
22266 (set_attr "mode" "TI")])
22268 (define_insn "ussubv16qi3"
22269 [(set (match_operand:V16QI 0 "register_operand" "=x")
22270 (us_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
22271 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22273 "psubusb\t{%2, %0|%0, %2}"
22274 [(set_attr "type" "sseiadd")
22275 (set_attr "mode" "TI")])
22277 (define_insn "ussubv8hi3"
22278 [(set (match_operand:V8HI 0 "register_operand" "=x")
22279 (us_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
22280 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22282 "psubusw\t{%2, %0|%0, %2}"
22283 [(set_attr "type" "sseiadd")
22284 (set_attr "mode" "TI")])
22286 (define_insn "mulv8hi3"
22287 [(set (match_operand:V8HI 0 "register_operand" "=x")
22288 (mult:V8HI (match_operand:V8HI 1 "register_operand" "0")
22289 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22291 "pmullw\t{%2, %0|%0, %2}"
22292 [(set_attr "type" "sseimul")
22293 (set_attr "mode" "TI")])
22295 (define_insn "smulv8hi3_highpart"
22296 [(set (match_operand:V8HI 0 "register_operand" "=x")
22299 (mult:V8SI (sign_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
22300 (sign_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
22303 "pmulhw\t{%2, %0|%0, %2}"
22304 [(set_attr "type" "sseimul")
22305 (set_attr "mode" "TI")])
22307 (define_insn "umulv8hi3_highpart"
22308 [(set (match_operand:V8HI 0 "register_operand" "=x")
22311 (mult:V8SI (zero_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
22312 (zero_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
22315 "pmulhuw\t{%2, %0|%0, %2}"
22316 [(set_attr "type" "sseimul")
22317 (set_attr "mode" "TI")])
22319 (define_insn "sse2_umulsidi3"
22320 [(set (match_operand:DI 0 "register_operand" "=y")
22321 (mult:DI (zero_extend:DI (vec_select:SI
22322 (match_operand:V2SI 1 "register_operand" "0")
22323 (parallel [(const_int 0)])))
22324 (zero_extend:DI (vec_select:SI
22325 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
22326 (parallel [(const_int 0)])))))]
22328 "pmuludq\t{%2, %0|%0, %2}"
22329 [(set_attr "type" "sseimul")
22330 (set_attr "mode" "TI")])
22332 (define_insn "sse2_umulv2siv2di3"
22333 [(set (match_operand:V2DI 0 "register_operand" "=x")
22334 (mult:V2DI (zero_extend:V2DI
22336 (match_operand:V4SI 1 "register_operand" "0")
22337 (parallel [(const_int 0) (const_int 2)])))
22340 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
22341 (parallel [(const_int 0) (const_int 2)])))))]
22343 "pmuludq\t{%2, %0|%0, %2}"
22344 [(set_attr "type" "sseimul")
22345 (set_attr "mode" "TI")])
22347 (define_insn "sse2_pmaddwd"
22348 [(set (match_operand:V4SI 0 "register_operand" "=x")
22351 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 1 "register_operand" "0")
22352 (parallel [(const_int 0)
22356 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 2 "nonimmediate_operand" "xm")
22357 (parallel [(const_int 0)
22362 (sign_extend:V4SI (vec_select:V4HI (match_dup 1)
22363 (parallel [(const_int 1)
22367 (sign_extend:V4SI (vec_select:V4HI (match_dup 2)
22368 (parallel [(const_int 1)
22371 (const_int 7)]))))))]
22373 "pmaddwd\t{%2, %0|%0, %2}"
22374 [(set_attr "type" "sseiadd")
22375 (set_attr "mode" "TI")])
22377 ;; Same as pxor, but don't show input operands so that we don't think
22379 (define_insn "sse2_clrti"
22380 [(set (match_operand:TI 0 "register_operand" "=x") (const_int 0))]
22383 if (get_attr_mode (insn) == MODE_TI)
22384 return "pxor\t%0, %0";
22386 return "xorps\t%0, %0";
22388 [(set_attr "type" "ssemov")
22389 (set_attr "memory" "none")
22392 (ne (symbol_ref "optimize_size")
22394 (const_string "V4SF")
22395 (const_string "TI")))])
22397 ;; MMX unsigned averages/sum of absolute differences
22399 (define_insn "sse2_uavgv16qi3"
22400 [(set (match_operand:V16QI 0 "register_operand" "=x")
22402 (plus:V16QI (plus:V16QI
22403 (match_operand:V16QI 1 "register_operand" "0")
22404 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
22405 (const_vector:V16QI [(const_int 1) (const_int 1)
22406 (const_int 1) (const_int 1)
22407 (const_int 1) (const_int 1)
22408 (const_int 1) (const_int 1)
22409 (const_int 1) (const_int 1)
22410 (const_int 1) (const_int 1)
22411 (const_int 1) (const_int 1)
22412 (const_int 1) (const_int 1)]))
22415 "pavgb\t{%2, %0|%0, %2}"
22416 [(set_attr "type" "sseiadd")
22417 (set_attr "mode" "TI")])
22419 (define_insn "sse2_uavgv8hi3"
22420 [(set (match_operand:V8HI 0 "register_operand" "=x")
22422 (plus:V8HI (plus:V8HI
22423 (match_operand:V8HI 1 "register_operand" "0")
22424 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
22425 (const_vector:V8HI [(const_int 1) (const_int 1)
22426 (const_int 1) (const_int 1)
22427 (const_int 1) (const_int 1)
22428 (const_int 1) (const_int 1)]))
22431 "pavgw\t{%2, %0|%0, %2}"
22432 [(set_attr "type" "sseiadd")
22433 (set_attr "mode" "TI")])
22435 ;; @@@ this isn't the right representation.
22436 (define_insn "sse2_psadbw"
22437 [(set (match_operand:V2DI 0 "register_operand" "=x")
22438 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
22439 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
22442 "psadbw\t{%2, %0|%0, %2}"
22443 [(set_attr "type" "sseiadd")
22444 (set_attr "mode" "TI")])
22447 ;; MMX insert/extract/shuffle
22449 (define_insn "sse2_pinsrw"
22450 [(set (match_operand:V8HI 0 "register_operand" "=x")
22451 (vec_merge:V8HI (match_operand:V8HI 1 "register_operand" "0")
22452 (vec_duplicate:V8HI
22454 (match_operand:SI 2 "nonimmediate_operand" "rm")))
22455 (match_operand:SI 3 "immediate_operand" "i")))]
22457 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
22458 [(set_attr "type" "ssecvt")
22459 (set_attr "mode" "TI")])
22461 (define_insn "sse2_pextrw"
22462 [(set (match_operand:SI 0 "register_operand" "=r")
22464 (vec_select:HI (match_operand:V8HI 1 "register_operand" "x")
22466 [(match_operand:SI 2 "immediate_operand" "i")]))))]
22468 "pextrw\t{%2, %1, %0|%0, %1, %2}"
22469 [(set_attr "type" "ssecvt")
22470 (set_attr "mode" "TI")])
22472 (define_insn "sse2_pshufd"
22473 [(set (match_operand:V4SI 0 "register_operand" "=x")
22474 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
22475 (match_operand:SI 2 "immediate_operand" "i")]
22478 "pshufd\t{%2, %1, %0|%0, %1, %2}"
22479 [(set_attr "type" "ssecvt")
22480 (set_attr "mode" "TI")])
22482 (define_insn "sse2_pshuflw"
22483 [(set (match_operand:V8HI 0 "register_operand" "=x")
22484 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
22485 (match_operand:SI 2 "immediate_operand" "i")]
22488 "pshuflw\t{%2, %1, %0|%0, %1, %2}"
22489 [(set_attr "type" "ssecvt")
22490 (set_attr "mode" "TI")])
22492 (define_insn "sse2_pshufhw"
22493 [(set (match_operand:V8HI 0 "register_operand" "=x")
22494 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
22495 (match_operand:SI 2 "immediate_operand" "i")]
22498 "pshufhw\t{%2, %1, %0|%0, %1, %2}"
22499 [(set_attr "type" "ssecvt")
22500 (set_attr "mode" "TI")])
22502 ;; MMX mask-generating comparisons
22504 (define_insn "eqv16qi3"
22505 [(set (match_operand:V16QI 0 "register_operand" "=x")
22506 (eq:V16QI (match_operand:V16QI 1 "register_operand" "0")
22507 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22509 "pcmpeqb\t{%2, %0|%0, %2}"
22510 [(set_attr "type" "ssecmp")
22511 (set_attr "mode" "TI")])
22513 (define_insn "eqv8hi3"
22514 [(set (match_operand:V8HI 0 "register_operand" "=x")
22515 (eq:V8HI (match_operand:V8HI 1 "register_operand" "0")
22516 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22518 "pcmpeqw\t{%2, %0|%0, %2}"
22519 [(set_attr "type" "ssecmp")
22520 (set_attr "mode" "TI")])
22522 (define_insn "eqv4si3"
22523 [(set (match_operand:V4SI 0 "register_operand" "=x")
22524 (eq:V4SI (match_operand:V4SI 1 "register_operand" "0")
22525 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22527 "pcmpeqd\t{%2, %0|%0, %2}"
22528 [(set_attr "type" "ssecmp")
22529 (set_attr "mode" "TI")])
22531 (define_insn "gtv16qi3"
22532 [(set (match_operand:V16QI 0 "register_operand" "=x")
22533 (gt:V16QI (match_operand:V16QI 1 "register_operand" "0")
22534 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22536 "pcmpgtb\t{%2, %0|%0, %2}"
22537 [(set_attr "type" "ssecmp")
22538 (set_attr "mode" "TI")])
22540 (define_insn "gtv8hi3"
22541 [(set (match_operand:V8HI 0 "register_operand" "=x")
22542 (gt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22543 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22545 "pcmpgtw\t{%2, %0|%0, %2}"
22546 [(set_attr "type" "ssecmp")
22547 (set_attr "mode" "TI")])
22549 (define_insn "gtv4si3"
22550 [(set (match_operand:V4SI 0 "register_operand" "=x")
22551 (gt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22552 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22554 "pcmpgtd\t{%2, %0|%0, %2}"
22555 [(set_attr "type" "ssecmp")
22556 (set_attr "mode" "TI")])
22559 ;; MMX max/min insns
22561 (define_insn "umaxv16qi3"
22562 [(set (match_operand:V16QI 0 "register_operand" "=x")
22563 (umax:V16QI (match_operand:V16QI 1 "register_operand" "0")
22564 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22566 "pmaxub\t{%2, %0|%0, %2}"
22567 [(set_attr "type" "sseiadd")
22568 (set_attr "mode" "TI")])
22570 (define_insn "smaxv8hi3"
22571 [(set (match_operand:V8HI 0 "register_operand" "=x")
22572 (smax:V8HI (match_operand:V8HI 1 "register_operand" "0")
22573 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22575 "pmaxsw\t{%2, %0|%0, %2}"
22576 [(set_attr "type" "sseiadd")
22577 (set_attr "mode" "TI")])
22579 (define_insn "uminv16qi3"
22580 [(set (match_operand:V16QI 0 "register_operand" "=x")
22581 (umin:V16QI (match_operand:V16QI 1 "register_operand" "0")
22582 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22584 "pminub\t{%2, %0|%0, %2}"
22585 [(set_attr "type" "sseiadd")
22586 (set_attr "mode" "TI")])
22588 (define_insn "sminv8hi3"
22589 [(set (match_operand:V8HI 0 "register_operand" "=x")
22590 (smin:V8HI (match_operand:V8HI 1 "register_operand" "0")
22591 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22593 "pminsw\t{%2, %0|%0, %2}"
22594 [(set_attr "type" "sseiadd")
22595 (set_attr "mode" "TI")])
22600 (define_insn "ashrv8hi3"
22601 [(set (match_operand:V8HI 0 "register_operand" "=x")
22602 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22603 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22605 "psraw\t{%2, %0|%0, %2}"
22606 [(set_attr "type" "sseishft")
22607 (set_attr "mode" "TI")])
22609 (define_insn "ashrv4si3"
22610 [(set (match_operand:V4SI 0 "register_operand" "=x")
22611 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22612 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22614 "psrad\t{%2, %0|%0, %2}"
22615 [(set_attr "type" "sseishft")
22616 (set_attr "mode" "TI")])
22618 (define_insn "lshrv8hi3"
22619 [(set (match_operand:V8HI 0 "register_operand" "=x")
22620 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22621 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22623 "psrlw\t{%2, %0|%0, %2}"
22624 [(set_attr "type" "sseishft")
22625 (set_attr "mode" "TI")])
22627 (define_insn "lshrv4si3"
22628 [(set (match_operand:V4SI 0 "register_operand" "=x")
22629 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22630 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22632 "psrld\t{%2, %0|%0, %2}"
22633 [(set_attr "type" "sseishft")
22634 (set_attr "mode" "TI")])
22636 (define_insn "lshrv2di3"
22637 [(set (match_operand:V2DI 0 "register_operand" "=x")
22638 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
22639 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22641 "psrlq\t{%2, %0|%0, %2}"
22642 [(set_attr "type" "sseishft")
22643 (set_attr "mode" "TI")])
22645 (define_insn "ashlv8hi3"
22646 [(set (match_operand:V8HI 0 "register_operand" "=x")
22647 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
22648 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22650 "psllw\t{%2, %0|%0, %2}"
22651 [(set_attr "type" "sseishft")
22652 (set_attr "mode" "TI")])
22654 (define_insn "ashlv4si3"
22655 [(set (match_operand:V4SI 0 "register_operand" "=x")
22656 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
22657 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22659 "pslld\t{%2, %0|%0, %2}"
22660 [(set_attr "type" "sseishft")
22661 (set_attr "mode" "TI")])
22663 (define_insn "ashlv2di3"
22664 [(set (match_operand:V2DI 0 "register_operand" "=x")
22665 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
22666 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22668 "psllq\t{%2, %0|%0, %2}"
22669 [(set_attr "type" "sseishft")
22670 (set_attr "mode" "TI")])
22672 (define_insn "ashrv8hi3_ti"
22673 [(set (match_operand:V8HI 0 "register_operand" "=x")
22674 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22675 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22677 "psraw\t{%2, %0|%0, %2}"
22678 [(set_attr "type" "sseishft")
22679 (set_attr "mode" "TI")])
22681 (define_insn "ashrv4si3_ti"
22682 [(set (match_operand:V4SI 0 "register_operand" "=x")
22683 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22684 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22686 "psrad\t{%2, %0|%0, %2}"
22687 [(set_attr "type" "sseishft")
22688 (set_attr "mode" "TI")])
22690 (define_insn "lshrv8hi3_ti"
22691 [(set (match_operand:V8HI 0 "register_operand" "=x")
22692 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22693 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22695 "psrlw\t{%2, %0|%0, %2}"
22696 [(set_attr "type" "sseishft")
22697 (set_attr "mode" "TI")])
22699 (define_insn "lshrv4si3_ti"
22700 [(set (match_operand:V4SI 0 "register_operand" "=x")
22701 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22702 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22704 "psrld\t{%2, %0|%0, %2}"
22705 [(set_attr "type" "sseishft")
22706 (set_attr "mode" "TI")])
22708 (define_insn "lshrv2di3_ti"
22709 [(set (match_operand:V2DI 0 "register_operand" "=x")
22710 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
22711 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22713 "psrlq\t{%2, %0|%0, %2}"
22714 [(set_attr "type" "sseishft")
22715 (set_attr "mode" "TI")])
22717 (define_insn "ashlv8hi3_ti"
22718 [(set (match_operand:V8HI 0 "register_operand" "=x")
22719 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
22720 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22722 "psllw\t{%2, %0|%0, %2}"
22723 [(set_attr "type" "sseishft")
22724 (set_attr "mode" "TI")])
22726 (define_insn "ashlv4si3_ti"
22727 [(set (match_operand:V4SI 0 "register_operand" "=x")
22728 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
22729 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22731 "pslld\t{%2, %0|%0, %2}"
22732 [(set_attr "type" "sseishft")
22733 (set_attr "mode" "TI")])
22735 (define_insn "ashlv2di3_ti"
22736 [(set (match_operand:V2DI 0 "register_operand" "=x")
22737 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
22738 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22740 "psllq\t{%2, %0|%0, %2}"
22741 [(set_attr "type" "sseishft")
22742 (set_attr "mode" "TI")])
22744 ;; See logical MMX insns for the reason for the unspec. Strictly speaking
22745 ;; we wouldn't need here it since we never generate TImode arithmetic.
22747 ;; There has to be some kind of prize for the weirdest new instruction...
22748 (define_insn "sse2_ashlti3"
22749 [(set (match_operand:TI 0 "register_operand" "=x")
22751 [(ashift:TI (match_operand:TI 1 "register_operand" "0")
22752 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
22753 (const_int 8)))] UNSPEC_NOP))]
22755 "pslldq\t{%2, %0|%0, %2}"
22756 [(set_attr "type" "sseishft")
22757 (set_attr "mode" "TI")])
22759 (define_insn "sse2_lshrti3"
22760 [(set (match_operand:TI 0 "register_operand" "=x")
22762 [(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
22763 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
22764 (const_int 8)))] UNSPEC_NOP))]
22766 "psrldq\t{%2, %0|%0, %2}"
22767 [(set_attr "type" "sseishft")
22768 (set_attr "mode" "TI")])
22772 (define_insn "sse2_unpckhpd"
22773 [(set (match_operand:V2DF 0 "register_operand" "=x")
22775 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
22776 (parallel [(const_int 1)]))
22777 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
22778 (parallel [(const_int 0)]))))]
22780 "unpckhpd\t{%2, %0|%0, %2}"
22781 [(set_attr "type" "ssecvt")
22782 (set_attr "mode" "TI")])
22784 (define_insn "sse2_unpcklpd"
22785 [(set (match_operand:V2DF 0 "register_operand" "=x")
22787 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
22788 (parallel [(const_int 0)]))
22789 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
22790 (parallel [(const_int 1)]))))]
22792 "unpcklpd\t{%2, %0|%0, %2}"
22793 [(set_attr "type" "ssecvt")
22794 (set_attr "mode" "TI")])
22796 ;; MMX pack/unpack insns.
22798 (define_insn "sse2_packsswb"
22799 [(set (match_operand:V16QI 0 "register_operand" "=x")
22801 (ss_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
22802 (ss_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
22804 "packsswb\t{%2, %0|%0, %2}"
22805 [(set_attr "type" "ssecvt")
22806 (set_attr "mode" "TI")])
22808 (define_insn "sse2_packssdw"
22809 [(set (match_operand:V8HI 0 "register_operand" "=x")
22811 (ss_truncate:V4HI (match_operand:V4SI 1 "register_operand" "0"))
22812 (ss_truncate:V4HI (match_operand:V4SI 2 "register_operand" "x"))))]
22814 "packssdw\t{%2, %0|%0, %2}"
22815 [(set_attr "type" "ssecvt")
22816 (set_attr "mode" "TI")])
22818 (define_insn "sse2_packuswb"
22819 [(set (match_operand:V16QI 0 "register_operand" "=x")
22821 (us_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
22822 (us_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
22824 "packuswb\t{%2, %0|%0, %2}"
22825 [(set_attr "type" "ssecvt")
22826 (set_attr "mode" "TI")])
22828 (define_insn "sse2_punpckhbw"
22829 [(set (match_operand:V16QI 0 "register_operand" "=x")
22831 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
22832 (parallel [(const_int 8) (const_int 0)
22833 (const_int 9) (const_int 1)
22834 (const_int 10) (const_int 2)
22835 (const_int 11) (const_int 3)
22836 (const_int 12) (const_int 4)
22837 (const_int 13) (const_int 5)
22838 (const_int 14) (const_int 6)
22839 (const_int 15) (const_int 7)]))
22840 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
22841 (parallel [(const_int 0) (const_int 8)
22842 (const_int 1) (const_int 9)
22843 (const_int 2) (const_int 10)
22844 (const_int 3) (const_int 11)
22845 (const_int 4) (const_int 12)
22846 (const_int 5) (const_int 13)
22847 (const_int 6) (const_int 14)
22848 (const_int 7) (const_int 15)]))
22849 (const_int 21845)))]
22851 "punpckhbw\t{%2, %0|%0, %2}"
22852 [(set_attr "type" "ssecvt")
22853 (set_attr "mode" "TI")])
22855 (define_insn "sse2_punpckhwd"
22856 [(set (match_operand:V8HI 0 "register_operand" "=x")
22858 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
22859 (parallel [(const_int 4) (const_int 0)
22860 (const_int 5) (const_int 1)
22861 (const_int 6) (const_int 2)
22862 (const_int 7) (const_int 3)]))
22863 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
22864 (parallel [(const_int 0) (const_int 4)
22865 (const_int 1) (const_int 5)
22866 (const_int 2) (const_int 6)
22867 (const_int 3) (const_int 7)]))
22870 "punpckhwd\t{%2, %0|%0, %2}"
22871 [(set_attr "type" "ssecvt")
22872 (set_attr "mode" "TI")])
22874 (define_insn "sse2_punpckhdq"
22875 [(set (match_operand:V4SI 0 "register_operand" "=x")
22877 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
22878 (parallel [(const_int 2) (const_int 0)
22879 (const_int 3) (const_int 1)]))
22880 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
22881 (parallel [(const_int 0) (const_int 2)
22882 (const_int 1) (const_int 3)]))
22885 "punpckhdq\t{%2, %0|%0, %2}"
22886 [(set_attr "type" "ssecvt")
22887 (set_attr "mode" "TI")])
22889 (define_insn "sse2_punpcklbw"
22890 [(set (match_operand:V16QI 0 "register_operand" "=x")
22892 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
22893 (parallel [(const_int 0) (const_int 8)
22894 (const_int 1) (const_int 9)
22895 (const_int 2) (const_int 10)
22896 (const_int 3) (const_int 11)
22897 (const_int 4) (const_int 12)
22898 (const_int 5) (const_int 13)
22899 (const_int 6) (const_int 14)
22900 (const_int 7) (const_int 15)]))
22901 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
22902 (parallel [(const_int 8) (const_int 0)
22903 (const_int 9) (const_int 1)
22904 (const_int 10) (const_int 2)
22905 (const_int 11) (const_int 3)
22906 (const_int 12) (const_int 4)
22907 (const_int 13) (const_int 5)
22908 (const_int 14) (const_int 6)
22909 (const_int 15) (const_int 7)]))
22910 (const_int 21845)))]
22912 "punpcklbw\t{%2, %0|%0, %2}"
22913 [(set_attr "type" "ssecvt")
22914 (set_attr "mode" "TI")])
22916 (define_insn "sse2_punpcklwd"
22917 [(set (match_operand:V8HI 0 "register_operand" "=x")
22919 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
22920 (parallel [(const_int 0) (const_int 4)
22921 (const_int 1) (const_int 5)
22922 (const_int 2) (const_int 6)
22923 (const_int 3) (const_int 7)]))
22924 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
22925 (parallel [(const_int 4) (const_int 0)
22926 (const_int 5) (const_int 1)
22927 (const_int 6) (const_int 2)
22928 (const_int 7) (const_int 3)]))
22931 "punpcklwd\t{%2, %0|%0, %2}"
22932 [(set_attr "type" "ssecvt")
22933 (set_attr "mode" "TI")])
22935 (define_insn "sse2_punpckldq"
22936 [(set (match_operand:V4SI 0 "register_operand" "=x")
22938 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
22939 (parallel [(const_int 0) (const_int 2)
22940 (const_int 1) (const_int 3)]))
22941 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
22942 (parallel [(const_int 2) (const_int 0)
22943 (const_int 3) (const_int 1)]))
22946 "punpckldq\t{%2, %0|%0, %2}"
22947 [(set_attr "type" "ssecvt")
22948 (set_attr "mode" "TI")])
22950 (define_insn "sse2_punpcklqdq"
22951 [(set (match_operand:V2DI 0 "register_operand" "=x")
22953 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
22954 (parallel [(const_int 1)
22956 (match_operand:V2DI 1 "register_operand" "0")
22959 "punpcklqdq\t{%2, %0|%0, %2}"
22960 [(set_attr "type" "ssecvt")
22961 (set_attr "mode" "TI")])
22963 (define_insn "sse2_punpckhqdq"
22964 [(set (match_operand:V2DI 0 "register_operand" "=x")
22966 (match_operand:V2DI 1 "register_operand" "0")
22967 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
22968 (parallel [(const_int 1)
22972 "punpckhqdq\t{%2, %0|%0, %2}"
22973 [(set_attr "type" "ssecvt")
22974 (set_attr "mode" "TI")])
22978 (define_insn "sse2_movapd"
22979 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
22980 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
22983 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
22984 "movapd\t{%1, %0|%0, %1}"
22985 [(set_attr "type" "ssemov")
22986 (set_attr "mode" "V2DF")])
22988 (define_insn "sse2_movupd"
22989 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
22990 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
22993 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
22994 "movupd\t{%1, %0|%0, %1}"
22995 [(set_attr "type" "ssecvt")
22996 (set_attr "mode" "V2DF")])
22998 (define_insn "sse2_movdqa"
22999 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
23000 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
23003 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
23004 "movdqa\t{%1, %0|%0, %1}"
23005 [(set_attr "type" "ssemov")
23006 (set_attr "mode" "TI")])
23008 (define_insn "sse2_movdqu"
23009 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
23010 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
23013 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
23014 "movdqu\t{%1, %0|%0, %1}"
23015 [(set_attr "type" "ssecvt")
23016 (set_attr "mode" "TI")])
23018 (define_insn "sse2_movdq2q"
23019 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y")
23020 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x")
23021 (parallel [(const_int 0)])))]
23022 "TARGET_SSE2 && !TARGET_64BIT"
23024 movq\t{%1, %0|%0, %1}
23025 movdq2q\t{%1, %0|%0, %1}"
23026 [(set_attr "type" "ssecvt")
23027 (set_attr "mode" "TI")])
23029 (define_insn "sse2_movdq2q_rex64"
23030 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y,r")
23031 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x,x")
23032 (parallel [(const_int 0)])))]
23033 "TARGET_SSE2 && TARGET_64BIT"
23035 movq\t{%1, %0|%0, %1}
23036 movdq2q\t{%1, %0|%0, %1}
23037 movd\t{%1, %0|%0, %1}"
23038 [(set_attr "type" "ssecvt")
23039 (set_attr "mode" "TI")])
23041 (define_insn "sse2_movq2dq"
23042 [(set (match_operand:V2DI 0 "register_operand" "=x,?x")
23043 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y")
23045 "TARGET_SSE2 && !TARGET_64BIT"
23047 movq\t{%1, %0|%0, %1}
23048 movq2dq\t{%1, %0|%0, %1}"
23049 [(set_attr "type" "ssecvt,ssemov")
23050 (set_attr "mode" "TI")])
23052 (define_insn "sse2_movq2dq_rex64"
23053 [(set (match_operand:V2DI 0 "register_operand" "=x,?x,?x")
23054 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y,r")
23056 "TARGET_SSE2 && TARGET_64BIT"
23058 movq\t{%1, %0|%0, %1}
23059 movq2dq\t{%1, %0|%0, %1}
23060 movd\t{%1, %0|%0, %1}"
23061 [(set_attr "type" "ssecvt,ssemov,ssecvt")
23062 (set_attr "mode" "TI")])
23064 (define_insn "sse2_movq"
23065 [(set (match_operand:V2DI 0 "register_operand" "=x")
23066 (vec_concat:V2DI (vec_select:DI
23067 (match_operand:V2DI 1 "nonimmediate_operand" "xm")
23068 (parallel [(const_int 0)]))
23071 "movq\t{%1, %0|%0, %1}"
23072 [(set_attr "type" "ssemov")
23073 (set_attr "mode" "TI")])
23075 (define_insn "sse2_loadd"
23076 [(set (match_operand:V4SI 0 "register_operand" "=x")
23078 (vec_duplicate:V4SI (match_operand:SI 1 "nonimmediate_operand" "mr"))
23079 (const_vector:V4SI [(const_int 0)
23085 "movd\t{%1, %0|%0, %1}"
23086 [(set_attr "type" "ssemov")
23087 (set_attr "mode" "TI")])
23089 (define_insn "sse2_stored"
23090 [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
23092 (match_operand:V4SI 1 "register_operand" "x")
23093 (parallel [(const_int 0)])))]
23095 "movd\t{%1, %0|%0, %1}"
23096 [(set_attr "type" "ssemov")
23097 (set_attr "mode" "TI")])
23099 (define_insn "sse2_movhpd"
23100 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
23102 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
23103 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
23105 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
23106 "movhpd\t{%2, %0|%0, %2}"
23107 [(set_attr "type" "ssecvt")
23108 (set_attr "mode" "V2DF")])
23110 (define_insn "sse2_movlpd"
23111 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
23113 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
23114 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
23116 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
23117 "movlpd\t{%2, %0|%0, %2}"
23118 [(set_attr "type" "ssecvt")
23119 (set_attr "mode" "V2DF")])
23121 (define_expand "sse2_loadsd"
23122 [(match_operand:V2DF 0 "register_operand" "")
23123 (match_operand:DF 1 "memory_operand" "")]
23126 emit_insn (gen_sse2_loadsd_1 (operands[0], operands[1],
23127 CONST0_RTX (V2DFmode)));
23131 (define_insn "sse2_loadsd_1"
23132 [(set (match_operand:V2DF 0 "register_operand" "=x")
23134 (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m"))
23135 (match_operand:V2DF 2 "const0_operand" "X")
23138 "movsd\t{%1, %0|%0, %1}"
23139 [(set_attr "type" "ssecvt")
23140 (set_attr "mode" "DF")])
23142 (define_insn "sse2_movsd"
23143 [(set (match_operand:V2DF 0 "register_operand" "=x")
23145 (match_operand:V2DF 1 "register_operand" "0")
23146 (match_operand:V2DF 2 "register_operand" "x")
23149 "movsd\t{%2, %0|%0, %2}"
23150 [(set_attr "type" "ssecvt")
23151 (set_attr "mode" "DF")])
23153 (define_insn "sse2_storesd"
23154 [(set (match_operand:DF 0 "memory_operand" "=m")
23156 (match_operand:V2DF 1 "register_operand" "x")
23157 (parallel [(const_int 0)])))]
23159 "movsd\t{%1, %0|%0, %1}"
23160 [(set_attr "type" "ssecvt")
23161 (set_attr "mode" "DF")])
23163 (define_insn "sse2_shufpd"
23164 [(set (match_operand:V2DF 0 "register_operand" "=x")
23165 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
23166 (match_operand:V2DF 2 "nonimmediate_operand" "xm")
23167 (match_operand:SI 3 "immediate_operand" "i")]
23170 ;; @@@ check operand order for intel/nonintel syntax
23171 "shufpd\t{%3, %2, %0|%0, %2, %3}"
23172 [(set_attr "type" "ssecvt")
23173 (set_attr "mode" "V2DF")])
23175 (define_insn "sse2_clflush"
23176 [(unspec_volatile [(match_operand 0 "address_operand" "p")]
23180 [(set_attr "type" "sse")
23181 (set_attr "memory" "unknown")])
23183 (define_expand "sse2_mfence"
23184 [(set (match_dup 0)
23185 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
23188 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
23189 MEM_VOLATILE_P (operands[0]) = 1;
23192 (define_insn "*mfence_insn"
23193 [(set (match_operand:BLK 0 "" "")
23194 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
23197 [(set_attr "type" "sse")
23198 (set_attr "memory" "unknown")])
23200 (define_expand "sse2_lfence"
23201 [(set (match_dup 0)
23202 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
23205 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
23206 MEM_VOLATILE_P (operands[0]) = 1;
23209 (define_insn "*lfence_insn"
23210 [(set (match_operand:BLK 0 "" "")
23211 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
23214 [(set_attr "type" "sse")
23215 (set_attr "memory" "unknown")])