1 ;; Frv Machine Description
2 ;; Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
3 ;; Contributed by Red Hat, Inc.
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; ::::::::::::::::::::
29 ;; ::::::::::::::::::::
35 (UNSPEC_PIC_PROLOGUE 3)
37 (UNSPEC_STACK_ADJUST 5)
38 (UNSPEC_EH_RETURN_EPILOGUE 6)])
42 ;; ::::::::::::::::::::
46 ;; ::::::::::::::::::::
48 ;; Standard Constraints
50 ;; `m' A memory operand is allowed, with any kind of address that the
51 ;; machine supports in general.
53 ;; `o' A memory operand is allowed, but only if the address is
54 ;; "offsettable". This means that adding a small integer (actually, the
55 ;; width in bytes of the operand, as determined by its machine mode) may be
56 ;; added to the address and the result is also a valid memory address.
58 ;; `V' A memory operand that is not offsettable. In other words,
59 ;; anything that would fit the `m' constraint but not the `o' constraint.
61 ;; `<' A memory operand with autodecrement addressing (either
62 ;; predecrement or postdecrement) is allowed.
64 ;; `>' A memory operand with autoincrement addressing (either
65 ;; preincrement or postincrement) is allowed.
67 ;; `r' A register operand is allowed provided that it is in a general
71 ;; Other letters can be defined in machine-dependent fashion to stand for
72 ;; particular classes of registers. `d', `a' and `f' are defined on the
73 ;; 68000/68020 to stand for data, address and floating point registers.
75 ;; `i' An immediate integer operand (one with constant value) is allowed.
76 ;; This includes symbolic constants whose values will be known only at
79 ;; `n' An immediate integer operand with a known numeric value is allowed.
80 ;; Many systems cannot support assembly-time constants for operands less
81 ;; than a word wide. Constraints for these operands should use `n' rather
84 ;; 'I' First machine-dependent integer constant (6 bit signed ints).
85 ;; 'J' Second machine-dependent integer constant (10 bit signed ints).
86 ;; 'K' Third machine-dependent integer constant (-2048).
87 ;; 'L' Fourth machine-dependent integer constant (16 bit signed ints).
88 ;; 'M' Fifth machine-dependent integer constant (16 bit unsigned ints).
89 ;; 'N' Sixth machine-dependent integer constant (-2047..-1).
90 ;; 'O' Seventh machine-dependent integer constant (zero).
91 ;; 'P' Eighth machine-dependent integer constant (1..2047).
93 ;; Other letters in the range `I' through `P' may be defined in a
94 ;; machine-dependent fashion to permit immediate integer operands with
95 ;; explicit integer values in specified ranges. For example, on the 68000,
96 ;; `I' is defined to stand for the range of values 1 to 8. This is the
97 ;; range permitted as a shift count in the shift instructions.
99 ;; `E' An immediate floating operand (expression code `const_double') is
100 ;; allowed, but only if the target floating point format is the same as
101 ;; that of the host machine (on which the compiler is running).
103 ;; `F' An immediate floating operand (expression code `const_double') is
106 ;; 'G' First machine-dependent const_double.
107 ;; 'H' Second machine-dependent const_double.
109 ;; `s' An immediate integer operand whose value is not an explicit
110 ;; integer is allowed.
112 ;; This might appear strange; if an insn allows a constant operand with a
113 ;; value not known at compile time, it certainly must allow any known
114 ;; value. So why use `s' instead of `i'? Sometimes it allows better code
117 ;; For example, on the 68000 in a fullword instruction it is possible to
118 ;; use an immediate operand; but if the immediate value is between -128 and
119 ;; 127, better code results from loading the value into a register and
120 ;; using the register. This is because the load into the register can be
121 ;; done with a `moveq' instruction. We arrange for this to happen by
122 ;; defining the letter `K' to mean "any integer outside the range -128 to
123 ;; 127", and then specifying `Ks' in the operand constraints.
125 ;; `g' Any register, memory or immediate integer operand is allowed,
126 ;; except for registers that are not general registers.
128 ;; `X' Any operand whatsoever is allowed, even if it does not satisfy
129 ;; `general_operand'. This is normally used in the constraint of a
130 ;; `match_scratch' when certain alternatives will not actually require a
133 ;; `0' Match operand 0.
134 ;; `1' Match operand 1.
135 ;; `2' Match operand 2.
136 ;; `3' Match operand 3.
137 ;; `4' Match operand 4.
138 ;; `5' Match operand 5.
139 ;; `6' Match operand 6.
140 ;; `7' Match operand 7.
141 ;; `8' Match operand 8.
142 ;; `9' Match operand 9.
144 ;; An operand that matches the specified operand number is allowed. If a
145 ;; digit is used together with letters within the same alternative, the
146 ;; digit should come last.
148 ;; This is called a "matching constraint" and what it really means is that
149 ;; the assembler has only a single operand that fills two roles considered
150 ;; separate in the RTL insn. For example, an add insn has two input
151 ;; operands and one output operand in the RTL, but on most CISC machines an
152 ;; add instruction really has only two operands, one of them an
153 ;; input-output operand:
157 ;; Matching constraints are used in these circumstances. More precisely,
158 ;; the two operands that match must include one input-only operand and one
159 ;; output-only operand. Moreover, the digit must be a smaller number than
160 ;; the number of the operand that uses it in the constraint.
162 ;; For operands to match in a particular case usually means that they are
163 ;; identical-looking RTL expressions. But in a few special cases specific
164 ;; kinds of dissimilarity are allowed. For example, `*x' as an input
165 ;; operand will match `*x++' as an output operand. For proper results in
166 ;; such cases, the output template should always use the output-operand's
167 ;; number when printing the operand.
169 ;; `p' An operand that is a valid memory address is allowed. This is for
170 ;; "load address" and "push address" instructions.
172 ;; `p' in the constraint must be accompanied by `address_operand' as the
173 ;; predicate in the `match_operand'. This predicate interprets the mode
174 ;; specified in the `match_operand' as the mode of the memory reference for
175 ;; which the address would be valid.
177 ;; `Q` First non constant, non register machine-dependent insns
178 ;; `R` Second non constant, non register machine-dependent insns
179 ;; `S` Third non constant, non register machine-dependent insns
180 ;; `T` Fourth non constant, non register machine-dependent insns
181 ;; `U` Fifth non constant, non register machine-dependent insns
183 ;; Letters in the range `Q' through `U' may be defined in a
184 ;; machine-dependent fashion to stand for arbitrary operand types. The
185 ;; machine description macro `EXTRA_CONSTRAINT' is passed the operand as
186 ;; its first argument and the constraint letter as its second operand.
188 ;; A typical use for this would be to distinguish certain types of memory
189 ;; references that affect other insn operands.
191 ;; Do not define these constraint letters to accept register references
192 ;; (`reg'); the reload pass does not expect this and would not handle it
195 ;; Multiple Alternative Constraints
196 ;; `?' Disparage slightly the alternative that the `?' appears in, as a
197 ;; choice when no alternative applies exactly. The compiler regards this
198 ;; alternative as one unit more costly for each `?' that appears in it.
200 ;; `!' Disparage severely the alternative that the `!' appears in. This
201 ;; alternative can still be used if it fits without reloading, but if
202 ;; reloading is needed, some other alternative will be used.
204 ;; Constraint modifiers
205 ;; `=' Means that this operand is write-only for this instruction: the
206 ;; previous value is discarded and replaced by output data.
208 ;; `+' Means that this operand is both read and written by the
211 ;; When the compiler fixes up the operands to satisfy the constraints, it
212 ;; needs to know which operands are inputs to the instruction and which are
213 ;; outputs from it. `=' identifies an output; `+' identifies an operand
214 ;; that is both input and output; all other operands are assumed to be
217 ;; `&' Means (in a particular alternative) that this operand is written
218 ;; before the instruction is finished using the input operands. Therefore,
219 ;; this operand may not lie in a register that is used as an input operand
220 ;; or as part of any memory address.
222 ;; `&' applies only to the alternative in which it is written. In
223 ;; constraints with multiple alternatives, sometimes one alternative
224 ;; requires `&' while others do not.
226 ;; `&' does not obviate the need to write `='.
228 ;; `%' Declares the instruction to be commutative for this operand and the
229 ;; following operand. This means that the compiler may interchange the two
230 ;; operands if that is the cheapest way to make all operands fit the
231 ;; constraints. This is often used in patterns for addition instructions
232 ;; that really have only two operands: the result must go in one of the
235 ;; `#' Says that all following characters, up to the next comma, are to be
236 ;; ignored as a constraint. They are significant only for choosing
237 ;; register preferences.
239 ;; `*' Says that the following character should be ignored when choosing
240 ;; register preferences. `*' has no effect on the meaning of the
241 ;; constraint as a constraint, and no effect on reloading.
244 ;; ::::::::::::::::::::
248 ;; ::::::::::::::::::::
250 ;; The `define_attr' expression is used to define each attribute required by
251 ;; the target machine. It looks like:
253 ;; (define_attr NAME LIST-OF-VALUES DEFAULT)
255 ;; NAME is a string specifying the name of the attribute being defined.
257 ;; LIST-OF-VALUES is either a string that specifies a comma-separated list of
258 ;; values that can be assigned to the attribute, or a null string to indicate
259 ;; that the attribute takes numeric values.
261 ;; DEFAULT is an attribute expression that gives the value of this attribute
262 ;; for insns that match patterns whose definition does not include an explicit
263 ;; value for this attribute.
265 ;; For each defined attribute, a number of definitions are written to the
266 ;; `insn-attr.h' file. For cases where an explicit set of values is specified
267 ;; for an attribute, the following are defined:
269 ;; * A `#define' is written for the symbol `HAVE_ATTR_NAME'.
271 ;; * An enumeral class is defined for `attr_NAME' with elements of the
272 ;; form `UPPER-NAME_UPPER-VALUE' where the attribute name and value are first
273 ;; converted to upper case.
275 ;; * A function `get_attr_NAME' is defined that is passed an insn and
276 ;; returns the attribute value for that insn.
278 ;; For example, if the following is present in the `md' file:
280 ;; (define_attr "type" "branch,fp,load,store,arith" ...)
282 ;; the following lines will be written to the file `insn-attr.h'.
284 ;; #define HAVE_ATTR_type
285 ;; enum attr_type {TYPE_BRANCH, TYPE_FP, TYPE_LOAD, TYPE_STORE, TYPE_ARITH};
286 ;; extern enum attr_type get_attr_type ();
288 ;; If the attribute takes numeric values, no `enum' type will be defined and
289 ;; the function to obtain the attribute's value will return `int'.
291 (define_attr "length" "" (const_int 4))
293 ;; Processor type -- this attribute must exactly match the processor_type
294 ;; enumeration in frv-protos.h.
296 (define_attr "cpu" "generic,fr500,fr400,fr300,simple,tomcat"
297 (const (symbol_ref "frv_cpu_type")))
299 ;; Attribute is "yes" for branches and jumps that span too great a distance
300 ;; to be implemented in the most natural way. Such instructions will use
301 ;; a call instruction in some way.
303 (define_attr "far_jump" "yes,no" (const_string "no"))
307 ;; The table below summarises the types of media instruction and their
308 ;; scheduling classification. Headings are:
310 ;; Type: the name of the define_attr type
311 ;; Conditions: "yes" if conditional variants are available
312 ;; FR500: Fujitsu's categorisation for the FR500
313 ;; FR400: Fujitsu's categorisation for the FR400 (but see below).
315 ;; On the FR400, media instructions are divided into 2 broad categories.
316 ;; Category 1 instructions can execute in either the M0 or M1 unit and can
317 ;; execute in parallel with other category 1 instructions. Category 2
318 ;; instructions must use the M0 unit, and therefore cannot run in parallel
319 ;; with other media instructions.
321 ;; The FR400 documentation also divides media instructions into one of seven
322 ;; categories (m1 to m7). m1 to m4 contain both Category 1 and Category 2
323 ;; instructions, so we use a combination of the categories here.
325 ;; Type Conditional FR500 FR400
326 ;; ---- ---------- ----- -----
327 ;; mlogic yes m1 m1:1
333 ;; mqaddh yes m1 m1:2
335 ;; munpackh no m2 m3:2
336 ;; mdpackh no m5 m3:2
337 ;; mbhconv yes m2 m3:2
340 ;; mexpdhw yes m2 m3:1
341 ;; mexpdhd yes m2 m3:2
347 ;; mqmulh yes m4 m2:2
348 ;; mqmulxh no m4 m2:2
349 ;; mqmach yes m4 m2:2
353 ;; mclracc no m3 m4:1
354 ;; mclracca no m6 m4:2
355 ;; mdunpackh no m2 n/a
356 ;; mbhconve no m2 n/a
357 ;; maddacc no n/a m2:1
358 ;; mdaddacc no n/a m2:2
363 ;; mqsath no n/a m1:2
367 "int,sethi,setlo,mul,div,gload,gstore,fload,fstore,movfg,movgf,branch,jump,jumpl,call,spr,trap,fsconv,fsadd,fsmul,fmas,fsdiv,sqrt_single,fdconv,fdadd,fdmul,fddiv,sqrt_double,mlogic,maveh,msath,maddh,mqaddh,mpackh,munpackh,mdpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx,mcut,mclracc,mclracca,mdunpackh,mbhconve,mrdacc,mwtacc,maddacc,mdaddacc,mabsh,mdrot,mcpl,mdcut,mqsath,mset,m7,ccr,multi,unknown"
368 (const_string "unknown"))
372 /* This is description of pipeline hazards based on DFA. The
373 following constructions can be used for this:
375 o define_cpu_unit string [string]) describes a cpu functional unit
376 (separated by comma).
378 1st operand: Names of cpu function units.
379 2nd operand: Name of automaton (see comments for
382 All define_reservations and define_cpu_units should have unique
383 names which can not be "nothing".
385 o (exclusion_set string string) means that each CPU function unit
386 in the first string can not be reserved simultaneously with each
387 unit whose name is in the second string and vise versa. CPU
388 units in the string are separated by commas. For example, it is
389 useful for description CPU with fully pipelined floating point
390 functional unit which can execute simultaneously only single
391 floating point insns or only double floating point insns.
393 o (presence_set string string) means that each CPU function unit in
394 the first string can not be reserved unless at least one of units
395 whose names are in the second string is reserved. This is an
396 asymmetric relation. CPU units in the string are separated by
397 commas. For example, it is useful for description that slot1 is
398 reserved after slot0 reservation for a VLIW processor.
400 o (absence_set string string) means that each CPU function unit in
401 the first string can not be reserved only if each unit whose name
402 is in the second string is not reserved. This is an asymmetric
403 relation (actually exclusion set is analogous to this one but it
404 is symmetric). CPU units in the string are separated by commas.
405 For example, it is useful for description that slot0 can not be
406 reserved after slot1 or slot2 reservation for a VLIW processor.
408 o (define_bypass number out_insn_names in_insn_names) names bypass with
409 given latency (the first number) from insns given by the first
410 string (see define_insn_reservation) into insns given by the
411 second string. Insn names in the strings are separated by
414 o (define_automaton string) describes names of an automaton
415 generated and used for pipeline hazards recognition. The names
416 are separated by comma. Actually it is possibly to generate the
417 single automaton but unfortunately it can be very large. If we
418 use more one automata, the summary size of the automata usually
419 is less than the single one. The automaton name is used in
420 define_cpu_unit. All automata should have unique names.
422 o (define_reservation string string) names reservation (the first
423 string) of cpu functional units (the 2nd string). Sometimes unit
424 reservations for different insns contain common parts. In such
425 case, you describe common part and use one its name (the 1st
426 parameter) in regular expression in define_insn_reservation. All
427 define_reservations, define results and define_cpu_units should
428 have unique names which can not be "nothing".
430 o (define_insn_reservation name default_latency condition regexpr)
431 describes reservation of cpu functional units (the 3nd operand)
432 for instruction which is selected by the condition (the 2nd
433 parameter). The first parameter is used for output of debugging
434 information. The reservations are described by a regular
435 expression according the following syntax:
437 regexp = regexp "," oneof
440 oneof = oneof "|" allof
443 allof = allof "+" repeat
446 repeat = element "*" number
449 element = cpu_function_name
455 1. "," is used for describing start of the next cycle in
458 2. "|" is used for describing the reservation described by the
459 first regular expression *or* the reservation described by
460 the second regular expression *or* etc.
462 3. "+" is used for describing the reservation described by the
463 first regular expression *and* the reservation described by
464 the second regular expression *and* etc.
466 4. "*" is used for convinience and simply means sequence in
467 which the regular expression are repeated NUMBER times with
468 cycle advancing (see ",").
470 5. cpu function unit name which means reservation.
472 6. reservation name -- see define_reservation.
474 7. string "nothing" means no units reservation.
478 (define_automaton "nodiv, idiv, div")
480 ;; An FR500 packet can contain a single control instruction or a sequence
481 ;; of up to four operations matching the regular expression:
483 ;; (I FM? I? FM? | FM? FM?) B? B?
485 ;; where I denotes an integer operation, FM a floating-point or media
486 ;; operation, and B a branch operation. There are two units for each type
487 ;; of instruction: I0 and I1, FM0 and FM1, and B0 and B1. Units are
488 ;; allocated left-to-right: the first integer instruction uses I0, the
489 ;; second uses I1, and so on.
491 ;; The FR400 is similar to the FR500 except that it allows only 2 operations
492 ;; per packet and has only one branch unit. We can use the FR500 conflict
493 ;; description for the FR400, but need to define different cpu_units
496 ;; Slot/unit combinations available on the FR400 and above:
497 (define_cpu_unit "sl0_i0, sl0_fm0, sl0_b0, sl0_c" "nodiv")
498 (define_cpu_unit "sl1_fm0, sl1_i1, sl1_fm1, sl1_b0" "nodiv")
500 ;; These are available on the FR500 and above:
501 (define_cpu_unit "sl1_b1" "nodiv")
502 (define_cpu_unit "sl2_i1, sl2_fm1, sl2_b0, sl2_b1" "nodiv")
503 (define_cpu_unit "sl3_fm1, sl3_b0, sl3_b1" "nodiv")
505 ;; The following describes conlicts by slots
507 (exclusion_set "sl0_i0" "sl0_fm0,sl0_b0,sl0_c")
508 (exclusion_set "sl0_fm0" "sl0_b0,sl0_c")
509 (exclusion_set "sl0_b0" "sl0_c")
512 (exclusion_set "sl1_fm0" "sl1_i1,sl1_fm1,sl1_b0,sl1_b1")
513 (exclusion_set "sl1_i1" "sl1_fm1,sl1_b0,sl1_b1")
514 (exclusion_set "sl1_fm1" "sl1_b0,sl1_b1")
515 (exclusion_set "sl1_b0" "sl1_b1")
518 (exclusion_set "sl2_i1" "sl2_fm1,sl2_b0,sl2_b1")
519 (exclusion_set "sl2_fm1" "sl2_b0,sl2_b1")
520 (exclusion_set "sl2_b0" "sl2_b1")
523 (exclusion_set "sl3_fm1" "sl3_b0,sl3_b1")
524 (exclusion_set "sl3_b0" "sl3_b1")
526 ;; The following describes conlicts by units
528 (exclusion_set "sl0_fm0" "sl1_fm0")
531 (exclusion_set "sl0_b0" "sl1_b0,sl2_b0,sl3_b0")
532 (exclusion_set "sl1_b0" "sl2_b0,sl3_b0")
533 (exclusion_set "sl2_b0" "sl3_b0")
536 (exclusion_set "sl1_i1" "sl2_i1")
539 (exclusion_set "sl1_fm1" "sl2_fm1,sl3_fm1")
540 (exclusion_set "sl2_fm1" "sl3_fm1")
543 (exclusion_set "sl1_b1" "sl2_b1,sl3_b1")
544 (exclusion_set "sl2_b1" "sl3_b1")
546 ;; The following describes remaining combinations of conflicts
548 (exclusion_set "sl0_i0" "sl1_fm1,sl1_b1")
549 (exclusion_set "sl0_fm0" "sl1_i1,sl1_b1,sl2_i1,sl2_fm1,sl3_fm1,sl3_b0")
550 (exclusion_set "sl0_b0" "sl1_fm0,sl1_i1,sl1_fm1,sl2_i1,sl2_fm1,sl2_b1,\
552 (exclusion_set "sl0_c" "sl1_fm0,sl1_i1,sl1_fm1,sl1_b0,sl1_b1,sl2_i1,sl2_fm1,\
553 sl2_b0,sl2_b1,sl3_fm1,sl3_b0,sl3_b1")
557 (exclusion_set "sl1_fm0" "sl2_b1")
558 (exclusion_set "sl1_i1" "sl2_fm1,sl2_b1,sl3_fm1,sl3_b0")
559 (exclusion_set "sl1_fm1" "sl2_i1,sl2_b1,sl3_b0")
560 (exclusion_set "sl1_b0" "sl2_i1,sl2_fm1,sl3_fm1,sl3_b1")
561 (exclusion_set "sl1_b1" "sl2_i1,sl2_fm1,sl2_b0,sl3_fm1,sl3_b0")
564 (exclusion_set "sl2_i1" "sl3_b1")
565 (exclusion_set "sl2_fm1" "sl3_b1")
566 (exclusion_set "sl2_b0" "sl3_fm1")
567 (exclusion_set "sl2_b1" "sl3_fm1,sl3_b0")
570 (exclusion_set "sl1_fm0" "sl2_i1,sl2_fm1,sl2_b0,sl2_b1,sl3_fm1,sl3_b0,sl3_b1")
571 (exclusion_set "sl3_fm1" "sl2_i1,sl2_fm1,sl2_b0,sl2_b1,sl3_b0,sl3_b1")
573 ;; ::::::::::::::::::::
575 ;; :: Generic/FR500 scheduler description
577 ;; ::::::::::::::::::::
579 ;; Define reservation in order to describe only in terms of units.
581 (define_reservation "i0" "sl0_i0")
582 (define_reservation "f0" "sl0_fm0|sl1_fm0")
583 (define_reservation "m0" "f0")
584 (define_reservation "b0" "sl0_b0|sl1_b0|sl2_b0|sl3_b0")
585 (define_reservation "c" "sl0_c")
586 (define_reservation "i1" "sl1_i1|sl2_i1")
587 (define_reservation "f1" "sl1_fm1|sl2_fm1|sl3_fm1")
588 (define_reservation "m1" "f1")
589 (define_reservation "b1" "sl1_b1|sl2_b1|sl3_b1")
592 ;; It is not possibly to issue load & store in one VLIW insn.
593 (define_cpu_unit "idiv1" "idiv")
594 (define_cpu_unit "idiv2" "idiv")
595 (define_cpu_unit "l0" "nodiv")
596 (define_cpu_unit "l1" "nodiv")
597 (define_cpu_unit "s0" "nodiv")
599 (exclusion_set "l1,l0" "s0")
601 ;; We set the default_latency of sethi to be 0 to allow sethi and setlo to be
602 ;; combined in the same VLIW instruction as allowed by the architecture. This
603 ;; assumes the only use of sethi is always followed by a setlo of the same
605 (define_insn_reservation "i1_sethi" 0
606 (and (eq_attr "cpu" "generic,fr500,tomcat")
607 (eq_attr "type" "sethi"))
610 (define_insn_reservation "i1_setlo" 1
611 (and (eq_attr "cpu" "generic,fr500,tomcat")
612 (eq_attr "type" "setlo"))
615 (define_insn_reservation "i1_int" 1
616 (and (eq_attr "cpu" "generic,fr500,tomcat")
617 (eq_attr "type" "int"))
620 (define_insn_reservation "i1_mul" 3
621 (and (eq_attr "cpu" "generic,fr500,tomcat")
622 (eq_attr "type" "mul"))
625 (define_insn_reservation "i1_div" 19
626 (and (eq_attr "cpu" "generic,fr500,tomcat")
627 (eq_attr "type" "div"))
628 "(i0|i1),(idiv1*18|idiv2*18)")
630 (define_insn_reservation "i2_gload" 4
631 (and (eq_attr "cpu" "generic,fr500,tomcat")
632 (eq_attr "type" "gload"))
635 (define_insn_reservation "i2_fload" 4
636 (and (eq_attr "cpu" "generic,fr500,tomcat")
637 (eq_attr "type" "fload"))
640 (define_insn_reservation "i3_gstore" 0
641 (and (eq_attr "cpu" "generic,fr500,tomcat")
642 (eq_attr "type" "gstore"))
645 (define_insn_reservation "i3_fstore" 0
646 (and (eq_attr "cpu" "generic,fr500,tomcat")
647 (eq_attr "type" "fstore"))
650 (define_insn_reservation "i4_move_gf" 3
651 (and (eq_attr "cpu" "generic,fr500,tomcat")
652 (eq_attr "type" "movgf"))
655 (define_insn_reservation "i4_move_fg" 3
656 (and (eq_attr "cpu" "generic,fr500,tomcat")
657 (eq_attr "type" "movfg"))
660 (define_insn_reservation "i5" 0
661 (and (eq_attr "cpu" "generic,fr500,tomcat")
662 (eq_attr "type" "jumpl"))
665 ;; Clear/commit is not generated now:
666 (define_insn_reservation "i6" 0 (const_int 0) "i0|i1")
669 ;; Branch-instructions
671 (define_insn_reservation "b1/b3" 0
672 (and (eq_attr "cpu" "generic,fr500,tomcat")
673 (eq_attr "type" "jump,branch,ccr"))
676 ;; The following insn is not generated now.
678 (define_insn_reservation "b2" 0 (const_int 0) "b0")
680 (define_insn_reservation "b4" 0
681 (and (eq_attr "cpu" "generic,fr500,tomcat")
682 (eq_attr "type" "call"))
685 ;; The following insns are not generated now.
686 (define_insn_reservation "b5" 0 (const_int 0) "b0|b1")
687 (define_insn_reservation "b6" 0 (const_int 0) "b0|b1")
690 (define_insn_reservation "trap" 0
691 (and (eq_attr "cpu" "generic,fr500,tomcat")
692 (eq_attr "type" "trap"))
695 (define_insn_reservation "control" 0
696 (and (eq_attr "cpu" "generic,fr500,tomcat")
697 (eq_attr "type" "spr"))
700 ;; Floating point insns
701 (define_cpu_unit "add0" "nodiv")
702 (define_cpu_unit "add1" "nodiv")
703 (define_cpu_unit "mul0" "nodiv")
704 (define_cpu_unit "mul1" "nodiv")
705 (define_cpu_unit "div1" "div")
706 (define_cpu_unit "div2" "div")
707 (define_cpu_unit "root" "div")
709 (define_bypass 4 "f1" "m1,m2,m3,m4,m5,m6,m7")
710 (define_insn_reservation "f1" 3
711 (and (eq_attr "cpu" "generic,fr500,tomcat")
712 (eq_attr "type" "fsconv,fdconv"))
715 (define_bypass 4 "f2" "m1,m2,m3,m4,m5,m6,m7")
716 (define_insn_reservation "f2" 3
717 (and (eq_attr "cpu" "generic,fr500,tomcat")
718 (eq_attr "type" "fsadd,fdadd"))
719 "(f0|f1)+(add0|add1)")
721 (define_bypass 4 "f3" "m1,m2,m3,m4,m5,m6,m7")
722 (define_insn_reservation "f3" 3
723 (and (eq_attr "cpu" "generic,fr500,tomcat")
724 (eq_attr "type" "fsmul,fdmul"))
725 "(f0|f1)+(mul0|mul1)")
727 (define_bypass 11 "f4_div" "m1,m2,m3,m4,m5,m6,m7")
728 (define_insn_reservation "f4_div" 10
729 (and (eq_attr "cpu" "generic,fr500,tomcat")
730 (eq_attr "type" "fsdiv,fddiv"))
731 "(f0|f1),(div1*9|div2*9)")
733 (define_bypass 16 "f4_root" "m1,m2,m3,m4,m5,m6,m7")
734 (define_insn_reservation "f4_root" 15
735 (and (eq_attr "cpu" "generic,fr500,tomcat")
736 (eq_attr "type" "sqrt_single,sqrt_double"))
739 (define_bypass 4 "f5" "m1,m2,m3,m4,m5,m6,m7")
740 (define_insn_reservation "f5" 3
741 (and (eq_attr "cpu" "generic,fr500,tomcat")
742 (eq_attr "type" "fmas"))
743 "(f0|f1)+(add0|add1)+(mul0|mul1)")
745 ;; The following insns are not generated by gcc now:
746 (define_insn_reservation "f6" 0 (const_int 0) "(f0|f1)+add0+add1")
747 (define_insn_reservation "f7" 0 (const_int 0) "(f0|f1)+mul0+mul1")
749 ;; Media insns. Now they are all not generated now.
750 (define_cpu_unit "m1_0" "nodiv")
751 (define_cpu_unit "m1_1" "nodiv")
752 (define_cpu_unit "m2_0" "nodiv")
753 (define_cpu_unit "m2_1" "nodiv")
754 (define_cpu_unit "m3_0" "nodiv")
755 (define_cpu_unit "m3_1" "nodiv")
756 (define_cpu_unit "m4_0" "nodiv")
757 (define_cpu_unit "m4_1" "nodiv")
758 (define_cpu_unit "m5" "nodiv")
759 (define_cpu_unit "m6" "nodiv")
760 (define_cpu_unit "m7" "nodiv")
762 (exclusion_set "m5,m6,m7" "m2_0,m2_1,m3_0,m3_1")
763 (exclusion_set "m5" "m6,m7")
764 (exclusion_set "m6" "m4_0,m4_1,m7")
765 (exclusion_set "m7" "m1_0,m1_1,add0,add1,mul0,mul1")
767 (define_bypass 2 "m1" "m1,m2,m3,m4,m5,m6,m7")
768 (define_bypass 4 "m1" "f1,f2,f3,f4_div,f4_root,f5,f6,f7")
769 (define_insn_reservation "m1" 3
770 (and (eq_attr "cpu" "generic,fr500,tomcat")
771 (eq_attr "type" "mlogic,maveh,msath,maddh,mqaddh"))
772 "(m0|m1)+(m1_0|m1_1)")
774 (define_bypass 2 "m2" "m1,m2,m3,m4,m5,m6,m7")
775 (define_bypass 4 "m2" "f1,f2,f3,f4_div,f4_root,f5,f6,f7")
776 (define_insn_reservation "m2" 3
777 (and (eq_attr "cpu" "generic,fr500,tomcat")
778 (eq_attr "type" "mrdacc,mpackh,munpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mcut,mdunpackh,mbhconve"))
779 "(m0|m1)+(m2_0|m2_1)")
781 (define_bypass 1 "m3" "m4")
782 (define_insn_reservation "m3" 2
783 (and (eq_attr "cpu" "generic,fr500,tomcat")
784 (eq_attr "type" "mclracc,mwtacc"))
785 "(m0|m1)+(m3_0|m3_1)")
787 (define_bypass 1 "m4" "m4")
788 (define_insn_reservation "m4" 2
789 (and (eq_attr "cpu" "generic,fr500,tomcat")
790 (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx"))
791 "(m0|m1)+(m4_0|m4_1)")
793 (define_bypass 2 "m5" "m1,m2,m3,m4,m5,m6,m7")
794 (define_bypass 4 "m5" "f1,f2,f3,f4_div,f4_root,f5,f6,f7")
795 (define_insn_reservation "m5" 3
796 (and (eq_attr "cpu" "generic,fr500,tomcat")
797 (eq_attr "type" "mdpackh"))
800 (define_bypass 1 "m6" "m4")
801 (define_insn_reservation "m6" 2
802 (and (eq_attr "cpu" "generic,fr500,tomcat")
803 (eq_attr "type" "mclracca"))
806 (define_bypass 2 "m7" "m1,m2,m3,m4,m5,m6,m7")
807 (define_bypass 4 "m7" "f1,f2,f3,f4_div,f4_root,f5,f6,f7")
809 (define_insn_reservation "m7" 3
810 (and (eq_attr "cpu" "generic,fr500,tomcat")
811 (eq_attr "type" "m7"))
814 ;; Unknown & multi insns starts on new cycle and the next insn starts
815 ;; on new cycle. To describe this we consider as a control insn.
816 (define_insn_reservation "unknown" 1
817 (and (eq_attr "cpu" "generic,fr500,tomcat")
818 (eq_attr "type" "unknown,multi"))
821 ;; ::::::::::::::::::::
823 ;; :: FR400 scheduler description
825 ;; ::::::::::::::::::::
827 ;; Category 2 media instructions use both media units, but can be packed
828 ;; with non-media instructions. Use fr400_m1unit to claim the M1 unit
829 ;; without claiming a slot.
831 (define_cpu_unit "fr400_m1unit" "nodiv")
833 (define_reservation "fr400_i0" "sl0_i0")
834 (define_reservation "fr400_i1" "sl1_i1")
835 (define_reservation "fr400_m0" "sl0_fm0|sl1_fm0")
836 (define_reservation "fr400_m1" "sl1_fm1")
837 (define_reservation "fr400_meither" "fr400_m0|(fr400_m1+fr400_m1unit)")
838 (define_reservation "fr400_mboth" "fr400_m0+fr400_m1unit")
839 (define_reservation "fr400_b" "sl0_b0|sl1_b0")
840 (define_reservation "fr400_c" "sl0_c")
842 ;; Name Class Units Latency
843 ;; ==== ===== ===== =======
845 ;; sethi I1 I0/I1 0 -- does not interfere with setlo
850 ;; fload I2 I0 4 -- only 3 if read by a media insn
851 ;; gstore I3 I0 0 -- provides no result
852 ;; fstore I3 I0 0 -- provides no result
855 ;; jumpl I5 I0 0 -- provides no result
857 ;; (*) The results of these instructions can be read one cycle earlier
858 ;; than indicated. The penalty given is for instructions with write-after-
859 ;; write dependencies.
861 ;; The FR400 can only do loads and stores in I0, so we there's no danger
862 ;; of memory unit collision in the same packet. There's only one divide
865 (define_insn_reservation "fr400_i1_int" 1
866 (and (eq_attr "cpu" "fr400")
867 (eq_attr "type" "int"))
870 (define_insn_reservation "fr400_i1_sethi" 0
871 (and (eq_attr "cpu" "fr400")
872 (eq_attr "type" "sethi"))
875 (define_insn_reservation "fr400_i1_setlo" 1
876 (and (eq_attr "cpu" "fr400")
877 (eq_attr "type" "setlo"))
880 (define_insn_reservation "fr400_i1_mul" 3
881 (and (eq_attr "cpu" "fr400")
882 (eq_attr "type" "mul"))
885 (define_insn_reservation "fr400_i1_div" 20
886 (and (eq_attr "cpu" "fr400")
887 (eq_attr "type" "div"))
890 (define_insn_reservation "fr400_i2_gload" 4
891 (and (eq_attr "cpu" "fr400")
892 (eq_attr "type" "gload"))
895 (define_insn_reservation "fr400_i2_fload" 4
896 (and (eq_attr "cpu" "fr400")
897 (eq_attr "type" "fload"))
900 (define_insn_reservation "fr400_i3_gstore" 0
901 (and (eq_attr "cpu" "fr400")
902 (eq_attr "type" "gstore"))
905 (define_insn_reservation "fr400_i3_fstore" 0
906 (and (eq_attr "cpu" "fr400")
907 (eq_attr "type" "fstore"))
910 (define_insn_reservation "fr400_i4_movfg" 3
911 (and (eq_attr "cpu" "fr400")
912 (eq_attr "type" "movfg"))
915 (define_insn_reservation "fr400_i4_movgf" 3
916 (and (eq_attr "cpu" "fr400")
917 (eq_attr "type" "movgf"))
920 (define_insn_reservation "fr400_i5_jumpl" 0
921 (and (eq_attr "cpu" "fr400")
922 (eq_attr "type" "jumpl"))
925 ;; The bypass between FPR loads and media instructions, described above.
929 "fr400_m1_1,fr400_m1_2,\
930 fr400_m2_1,fr400_m2_2,\
931 fr400_m3_1,fr400_m3_2,\
932 fr400_m4_1,fr400_m4_2,\
935 ;; The branch instructions all use the B unit and produce no result.
937 (define_insn_reservation "fr400_b" 0
938 (and (eq_attr "cpu" "fr400")
939 (eq_attr "type" "jump,branch,ccr,call"))
942 ;; Control instructions use the C unit, which excludes all the others.
944 (define_insn_reservation "fr400_c" 0
945 (and (eq_attr "cpu" "fr400")
946 (eq_attr "type" "spr,trap"))
949 ;; Unknown instructions use the C unit, since it requires single-operation
952 (define_insn_reservation "fr400_unknown" 1
953 (and (eq_attr "cpu" "fr400")
954 (eq_attr "type" "unknown,multi"))
957 ;; FP->FP moves are marked as "fsconv" instructions in the define_insns
958 ;; below, but are implemented on the FR400 using "mlogic" instructions.
959 ;; It's easier to class "fsconv" as a "m1:1" instruction than provide
960 ;; separate define_insns for the FR400.
962 ;; M1 instructions store their results in FPRs. Any instruction can read
963 ;; the result in the following cycle, so no penalty occurs.
965 (define_insn_reservation "fr400_m1_1" 1
966 (and (eq_attr "cpu" "fr400")
967 (eq_attr "type" "fsconv,mlogic,maveh,msath,maddh,mabsh,mset"))
970 (define_insn_reservation "fr400_m1_2" 1
971 (and (eq_attr "cpu" "fr400")
972 (eq_attr "type" "mqaddh,mqsath"))
975 ;; M2 instructions store their results in accumulators, which are read
976 ;; by M2 or M4 media commands. M2 instructions can read the results in
977 ;; the following cycle, but M4 instructions must wait a cycle more.
980 "fr400_m2_1,fr400_m2_2"
981 "fr400_m2_1,fr400_m2_2")
983 (define_insn_reservation "fr400_m2_1" 2
984 (and (eq_attr "cpu" "fr400")
985 (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mcpx,maddacc"))
988 (define_insn_reservation "fr400_m2_2" 2
989 (and (eq_attr "cpu" "fr400")
990 (eq_attr "type" "mqmulh,mqmulxh,mqmach,mqcpx,mdaddacc"))
993 ;; For our purposes, there seems to be little real difference between
994 ;; M1 and M3 instructions. Keep them separate anyway in case the distinction
997 (define_insn_reservation "fr400_m3_1" 1
998 (and (eq_attr "cpu" "fr400")
999 (eq_attr "type" "mpackh,mrot,mshift,mexpdhw"))
1002 (define_insn_reservation "fr400_m3_2" 1
1003 (and (eq_attr "cpu" "fr400")
1004 (eq_attr "type" "munpackh,mdpackh,mbhconv,mexpdhd,mwcut,mdrot,mcpl"))
1007 ;; M4 instructions write to accumulators or FPRs. MOVFG and STF
1008 ;; instructions can read an FPR result in the following cycle, but
1009 ;; M-unit instructions must wait a cycle more for either kind of result.
1012 "fr400_m4_1,fr400_m4_2"
1013 "fr400_i3_fstore,fr400_i4_movfg")
1015 (define_insn_reservation "fr400_m4_1" 2
1016 (and (eq_attr "cpu" "fr400")
1017 (eq_attr "type" "mrdacc,mcut,mclracc"))
1020 (define_insn_reservation "fr400_m4_2" 2
1021 (and (eq_attr "cpu" "fr400")
1022 (eq_attr "type" "mclracca,mdcut"))
1025 ;; M5 instructions always incur a 1-cycle penalty.
1027 (define_insn_reservation "fr400_m5" 2
1028 (and (eq_attr "cpu" "fr400")
1029 (eq_attr "type" "mwtacc"))
1032 ;; ::::::::::::::::::::
1034 ;; :: Simple/FR300 scheduler description
1036 ;; ::::::::::::::::::::
1038 ;; Fr300 or simple processor. To describe it as 1 insn issue
1039 ;; processor, we use control unit.
1041 (define_insn_reservation "fr300_lat1" 1
1042 (and (eq_attr "cpu" "fr300,simple")
1043 (eq_attr "type" "!gload,fload,movfg,movgf"))
1046 (define_insn_reservation "fr300_lat2" 2
1047 (and (eq_attr "cpu" "fr300,simple")
1048 (eq_attr "type" "gload,fload,movfg,movgf"))
1052 ;; ::::::::::::::::::::
1056 ;; ::::::::::::::::::::
1058 ;; The insn attribute mechanism can be used to specify the requirements for
1059 ;; delay slots, if any, on a target machine. An instruction is said to require
1060 ;; a "delay slot" if some instructions that are physically after the
1061 ;; instruction are executed as if they were located before it. Classic
1062 ;; examples are branch and call instructions, which often execute the following
1063 ;; instruction before the branch or call is performed.
1065 ;; On some machines, conditional branch instructions can optionally "annul"
1066 ;; instructions in the delay slot. This means that the instruction will not be
1067 ;; executed for certain branch outcomes. Both instructions that annul if the
1068 ;; branch is true and instructions that annul if the branch is false are
1071 ;; Delay slot scheduling differs from instruction scheduling in that
1072 ;; determining whether an instruction needs a delay slot is dependent only
1073 ;; on the type of instruction being generated, not on data flow between the
1074 ;; instructions. See the next section for a discussion of data-dependent
1075 ;; instruction scheduling.
1077 ;; The requirement of an insn needing one or more delay slots is indicated via
1078 ;; the `define_delay' expression. It has the following form:
1080 ;; (define_delay TEST
1081 ;; [DELAY-1 ANNUL-TRUE-1 ANNUL-FALSE-1
1082 ;; DELAY-2 ANNUL-TRUE-2 ANNUL-FALSE-2
1085 ;; TEST is an attribute test that indicates whether this `define_delay' applies
1086 ;; to a particular insn. If so, the number of required delay slots is
1087 ;; determined by the length of the vector specified as the second argument. An
1088 ;; insn placed in delay slot N must satisfy attribute test DELAY-N.
1089 ;; ANNUL-TRUE-N is an attribute test that specifies which insns may be annulled
1090 ;; if the branch is true. Similarly, ANNUL-FALSE-N specifies which insns in
1091 ;; the delay slot may be annulled if the branch is false. If annulling is not
1092 ;; supported for that delay slot, `(nil)' should be coded.
1094 ;; For example, in the common case where branch and call insns require a single
1095 ;; delay slot, which may contain any insn other than a branch or call, the
1096 ;; following would be placed in the `md' file:
1098 ;; (define_delay (eq_attr "type" "branch,call")
1099 ;; [(eq_attr "type" "!branch,call") (nil) (nil)])
1101 ;; Multiple `define_delay' expressions may be specified. In this case, each
1102 ;; such expression specifies different delay slot requirements and there must
1103 ;; be no insn for which tests in two `define_delay' expressions are both true.
1105 ;; For example, if we have a machine that requires one delay slot for branches
1106 ;; but two for calls, no delay slot can contain a branch or call insn, and any
1107 ;; valid insn in the delay slot for the branch can be annulled if the branch is
1108 ;; true, we might represent this as follows:
1110 ;; (define_delay (eq_attr "type" "branch")
1111 ;; [(eq_attr "type" "!branch,call")
1112 ;; (eq_attr "type" "!branch,call")
1115 ;; (define_delay (eq_attr "type" "call")
1116 ;; [(eq_attr "type" "!branch,call") (nil) (nil)
1117 ;; (eq_attr "type" "!branch,call") (nil) (nil)])
1119 ;; Note - it is the backend's responsibility to fill any unfilled delay slots
1120 ;; at assembler generation time. This is usually done by adding a special print
1121 ;; operand to the delayed insrtuction, and then in the PRINT_OPERAND function
1122 ;; calling dbr_sequence_length() to determine how many delay slots were filled.
1125 ;; --------------<machine>.md-----------------
1126 ;; (define_insn "call"
1127 ;; [(call (match_operand 0 "memory_operand" "m")
1128 ;; (match_operand 1 "" ""))]
1130 ;; "call_delayed %0,%1,%2%#"
1131 ;; [(set_attr "length" "4")
1132 ;; (set_attr "type" "call")])
1134 ;; -------------<machine>.h-------------------
1135 ;; #define PRINT_OPERAND_PUNCT_VALID_P(CODE) (CODE == '#')
1137 ;; ------------<machine>.c------------------
1139 ;; machine_print_operand (file, x, code)
1147 ;; if (dbr_sequence_length () == 0)
1148 ;; fputs ("\n\tnop", file);
1151 ;; ::::::::::::::::::::
1153 ;; :: Notes on Patterns
1155 ;; ::::::::::::::::::::
1157 ;; If you need to construct a sequence of assembler instructions in order
1158 ;; to implement a pattern be sure to escape any backslashes and double quotes
1159 ;; that you use, eg:
1161 ;; (define_insn "an example"
1165 ;; { static char buffer [100];
1166 ;; sprintf (buffer, \"insn \\t %d\", REGNO (operands[1]));
1171 ;; Also if there is more than one instruction, they can be separated by \\;
1172 ;; which is a space saving synonym for \\n\\t:
1174 ;; (define_insn "another example"
1178 ;; { static char buffer [100];
1179 ;; sprintf (buffer, \"insn1 \\t %d\\;insn2 \\t %%1\",
1180 ;; REGNO (operands[1]));
1187 ;; ::::::::::::::::::::
1191 ;; ::::::::::::::::::::
1193 ;; Wrap moves in define_expand to prevent memory->memory moves from being
1194 ;; generated at the RTL level, which generates better code for most machines
1195 ;; which can't do mem->mem moves.
1197 ;; If operand 0 is a `subreg' with mode M of a register whose own mode is wider
1198 ;; than M, the effect of this instruction is to store the specified value in
1199 ;; the part of the register that corresponds to mode M. The effect on the rest
1200 ;; of the register is undefined.
1202 ;; This class of patterns is special in several ways. First of all, each of
1203 ;; these names *must* be defined, because there is no other way to copy a datum
1204 ;; from one place to another.
1206 ;; Second, these patterns are not used solely in the RTL generation pass. Even
1207 ;; the reload pass can generate move insns to copy values from stack slots into
1208 ;; temporary registers. When it does so, one of the operands is a hard
1209 ;; register and the other is an operand that can need to be reloaded into a
1212 ;; Therefore, when given such a pair of operands, the pattern must
1213 ;; generate RTL which needs no reloading and needs no temporary
1214 ;; registers--no registers other than the operands. For example, if
1215 ;; you support the pattern with a `define_expand', then in such a
1216 ;; case the `define_expand' mustn't call `force_reg' or any other such
1217 ;; function which might generate new pseudo registers.
1219 ;; This requirement exists even for subword modes on a RISC machine
1220 ;; where fetching those modes from memory normally requires several
1221 ;; insns and some temporary registers. Look in `spur.md' to see how
1222 ;; the requirement can be satisfied.
1224 ;; During reload a memory reference with an invalid address may be passed as an
1225 ;; operand. Such an address will be replaced with a valid address later in the
1226 ;; reload pass. In this case, nothing may be done with the address except to
1227 ;; use it as it stands. If it is copied, it will not be replaced with a valid
1228 ;; address. No attempt should be made to make such an address into a valid
1229 ;; address and no routine (such as `change_address') that will do so may be
1230 ;; called. Note that `general_operand' will fail when applied to such an
1233 ;; The global variable `reload_in_progress' (which must be explicitly declared
1234 ;; if required) can be used to determine whether such special handling is
1237 ;; The variety of operands that have reloads depends on the rest of
1238 ;; the machine description, but typically on a RISC machine these can
1239 ;; only be pseudo registers that did not get hard registers, while on
1240 ;; other machines explicit memory references will get optional
1243 ;; If a scratch register is required to move an object to or from memory, it
1244 ;; can be allocated using `gen_reg_rtx' prior to reload. But this is
1245 ;; impossible during and after reload. If there are cases needing scratch
1246 ;; registers after reload, you must define `SECONDARY_INPUT_RELOAD_CLASS' and
1247 ;; perhaps also `SECONDARY_OUTPUT_RELOAD_CLASS' to detect them, and provide
1248 ;; patterns `reload_inM' or `reload_outM' to handle them.
1250 ;; The constraints on a `moveM' must permit moving any hard register to any
1251 ;; other hard register provided that `HARD_REGNO_MODE_OK' permits mode M in
1252 ;; both registers and `REGISTER_MOVE_COST' applied to their classes returns a
1255 ;; It is obligatory to support floating point `moveM' instructions
1256 ;; into and out of any registers that can hold fixed point values,
1257 ;; because unions and structures (which have modes `SImode' or
1258 ;; `DImode') can be in those registers and they may have floating
1261 ;; There may also be a need to support fixed point `moveM' instructions in and
1262 ;; out of floating point registers. Unfortunately, I have forgotten why this
1263 ;; was so, and I don't know whether it is still true. If `HARD_REGNO_MODE_OK'
1264 ;; rejects fixed point values in floating point registers, then the constraints
1265 ;; of the fixed point `moveM' instructions must be designed to avoid ever
1266 ;; trying to reload into a floating point register.
1268 (define_expand "movqi"
1269 [(set (match_operand:QI 0 "general_operand" "")
1270 (match_operand:QI 1 "general_operand" ""))]
1274 if (!reload_in_progress
1275 && !reload_completed
1276 && !register_operand (operands[0], QImode)
1277 && !reg_or_0_operand (operands[1], QImode))
1278 operands[1] = copy_to_mode_reg (QImode, operands[1]);
1281 (define_insn "*movqi_load"
1282 [(set (match_operand:QI 0 "register_operand" "=d,f")
1283 (match_operand:QI 1 "frv_load_operand" "m,m"))]
1285 "* return output_move_single (operands, insn);"
1286 [(set_attr "length" "4")
1287 (set_attr "type" "gload,fload")])
1289 (define_insn "*movqi_internal"
1290 [(set (match_operand:QI 0 "move_destination_operand" "=d,d,m,m,?f,?f,?d,?m,f")
1291 (match_operand:QI 1 "move_source_operand" "L,d,d,O, d, f, f, f,GO"))]
1292 "register_operand(operands[0], QImode) || reg_or_0_operand (operands[1], QImode)"
1293 "* return output_move_single (operands, insn);"
1294 [(set_attr "length" "4")
1295 (set_attr "type" "int,int,gstore,gstore,movgf,fsconv,movfg,fstore,movgf")])
1297 (define_expand "movhi"
1298 [(set (match_operand:HI 0 "general_operand" "")
1299 (match_operand:HI 1 "general_operand" ""))]
1303 if (!reload_in_progress
1304 && !reload_completed
1305 && !register_operand (operands[0], HImode)
1306 && !reg_or_0_operand (operands[1], HImode))
1307 operands[1] = copy_to_mode_reg (HImode, operands[1]);
1310 (define_insn "*movhi_load"
1311 [(set (match_operand:HI 0 "register_operand" "=d,f")
1312 (match_operand:HI 1 "frv_load_operand" "m,m"))]
1314 "* return output_move_single (operands, insn);"
1315 [(set_attr "length" "4")
1316 (set_attr "type" "gload,fload")])
1318 (define_insn "*movhi_internal"
1319 [(set (match_operand:HI 0 "move_destination_operand" "=d,d,d,m,m,?f,?f,?d,?m,f")
1320 (match_operand:HI 1 "move_source_operand" "L,i,d,d,O, d, f, f, f,GO"))]
1321 "register_operand(operands[0], HImode) || reg_or_0_operand (operands[1], HImode)"
1322 "* return output_move_single (operands, insn);"
1323 [(set_attr "length" "4,8,4,4,4,4,4,4,4,4")
1324 (set_attr "type" "int,multi,int,gstore,gstore,movgf,fsconv,movfg,fstore,movgf")])
1326 ;; Split 2 word load of constants into sethi/setlo instructions
1328 [(set (match_operand:HI 0 "integer_register_operand" "")
1329 (match_operand:HI 1 "int_2word_operand" ""))]
1332 (high:HI (match_dup 1)))
1334 (lo_sum:HI (match_dup 0)
1338 (define_insn "movhi_high"
1339 [(set (match_operand:HI 0 "integer_register_operand" "=d")
1340 (high:HI (match_operand:HI 1 "int_2word_operand" "i")))]
1343 [(set_attr "type" "sethi")
1344 (set_attr "length" "4")])
1346 (define_insn "movhi_lo_sum"
1347 [(set (match_operand:HI 0 "integer_register_operand" "+d")
1348 (lo_sum:HI (match_dup 0)
1349 (match_operand:HI 1 "int_2word_operand" "i")))]
1352 [(set_attr "type" "setlo")
1353 (set_attr "length" "4")])
1355 (define_expand "movsi"
1356 [(set (match_operand:SI 0 "move_destination_operand" "")
1357 (match_operand:SI 1 "move_source_operand" ""))]
1361 if (frv_emit_movsi (operands[0], operands[1]))
1365 ;; Note - it is best to only have one movsi pattern and to handle
1366 ;; all the various contingencies by the use of alternatives. This
1367 ;; allows reload the greatest amount of flexability (since reload will
1368 ;; only choose amoungst alternatives for a selected insn, it will not
1369 ;; replace the insn with another one).
1371 ;; Unfortunately, we do have to separate out load-type moves from the rest,
1372 ;; and only allow memory source operands in the former. If we do memory and
1373 ;; constant loads in a single pattern, reload will be tempted to force
1374 ;; constants into memory when the destination is a floating-point register.
1375 ;; That may make a function use a PIC pointer when it didn't before, and we
1376 ;; cannot change PIC usage (and hence stack layout) so late in the game.
1377 ;; The resulting sequences for loading cosntants into FPRs are preferable
1378 ;; even when we're not generating PIC code.
1380 (define_insn "*movsi_load"
1381 [(set (match_operand:SI 0 "register_operand" "=d,f")
1382 (match_operand:SI 1 "frv_load_operand" "m,m"))]
1384 "* return output_move_single (operands, insn);"
1385 [(set_attr "length" "4")
1386 (set_attr "type" "gload,fload")])
1388 (define_insn "*movsi_internal"
1389 [(set (match_operand:SI 0 "move_destination_operand" "=d,d,d,m,m,z,d,d,f,f,m,?f,?z")
1390 (match_operand:SI 1 "move_source_operand" "LQ,i,d,d,O,d,z,f,d,f,f,GO,GO"))]
1391 "register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)"
1392 "* return output_move_single (operands, insn);"
1393 [(set_attr "length" "4,8,4,4,4,4,4,4,4,4,4,4,4")
1394 (set_attr "type" "int,multi,int,gstore,gstore,spr,spr,movfg,movgf,fsconv,fstore,movgf,spr")])
1396 (define_insn "*movsi_lda_sdata"
1397 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1398 (plus:SI (match_operand:SI 1 "small_data_register_operand" "d")
1399 (match_operand:SI 2 "small_data_symbolic_operand" "Q")))]
1401 "addi %1, #gprel12(%2), %0"
1402 [(set_attr "type" "int")
1403 (set_attr "length" "4")])
1405 ;; Split 2 word load of constants into sethi/setlo instructions
1407 [(set (match_operand:SI 0 "integer_register_operand" "")
1408 (match_operand:SI 1 "int_2word_operand" ""))]
1411 (high:SI (match_dup 1)))
1413 (lo_sum:SI (match_dup 0)
1417 (define_insn "movsi_high"
1418 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1419 (high:SI (match_operand:SI 1 "int_2word_operand" "i")))]
1422 [(set_attr "type" "sethi")
1423 (set_attr "length" "4")])
1425 (define_insn "movsi_lo_sum"
1426 [(set (match_operand:SI 0 "integer_register_operand" "+d")
1427 (lo_sum:SI (match_dup 0)
1428 (match_operand:SI 1 "int_2word_operand" "i")))]
1431 [(set_attr "type" "setlo")
1432 (set_attr "length" "4")])
1434 ;; Split loads of addresses with PIC specified into 3 separate instructions
1435 (define_insn_and_split "*movsi_pic"
1436 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1437 (plus:SI (match_operand:SI 1 "pic_register_operand" "d")
1438 (match_operand:SI 2 "pic_symbolic_operand" "")))]
1443 (high:SI (match_dup 2)))
1445 (lo_sum:SI (match_dup 0)
1448 (plus:SI (match_dup 0) (match_dup 1)))]
1451 [(set_attr "type" "multi")
1452 (set_attr "length" "12")])
1454 (define_insn "movsi_high_pic"
1455 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1456 (high:SI (match_operand:SI 1 "pic_symbolic_operand" "")))]
1458 "sethi #gprelhi(%1), %0"
1459 [(set_attr "type" "sethi")
1460 (set_attr "length" "4")])
1462 (define_insn "movsi_lo_sum_pic"
1463 [(set (match_operand:SI 0 "integer_register_operand" "+d")
1464 (lo_sum:SI (match_dup 0)
1465 (match_operand:SI 1 "pic_symbolic_operand" "")))]
1467 "setlo #gprello(%1), %0"
1468 [(set_attr "type" "setlo")
1469 (set_attr "length" "4")])
1471 (define_expand "movdi"
1472 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1473 (match_operand:DI 1 "general_operand" ""))]
1477 if (!reload_in_progress
1478 && !reload_completed
1479 && !register_operand (operands[0], DImode)
1480 && !reg_or_0_operand (operands[1], DImode))
1481 operands[1] = copy_to_mode_reg (DImode, operands[1]);
1484 (define_insn "*movdi_double"
1485 [(set (match_operand:DI 0 "move_destination_operand" "=e,?h,??d,??f,R,?R,??m,??m,e,?h,??d,??f,?e,??d,?h,??f,R,m,e,??d,e,??d,?h,??f")
1486 (match_operand:DI 1 "move_source_operand" " e,h,d,f,e,h,d,f,R,R,m,m,h,f,e,d,GO,GO,GO,GO,nF,nF,GO,GO"))]
1488 && (register_operand (operands[0], DImode)
1489 || reg_or_0_operand (operands[1], DImode))"
1490 "* return output_move_double (operands, insn);"
1491 [(set_attr "length" "8,4,8,8,4,4,8,8,4,4,8,8,4,8,4,8,4,8,8,8,16,16,8,8")
1492 (set_attr "type" "multi,fdconv,multi,multi,gstore,fstore,gstore,fstore,gload,fload,gload,fload,movfg,movfg,movgf,movgf,gstore,gstore,multi,multi,multi,multi,movgf,movgf")])
1494 (define_insn "*movdi_nodouble"
1495 [(set (match_operand:DI 0 "move_destination_operand" "=e,?h,??d,??f,R,?R,??m,??m,e,?h,??d,??f,?e,??d,?h,??f,R,m,e,??d,e,??d,?h,??f")
1496 (match_operand:DI 1 "move_source_operand" " e,h,d,f,e,h,d,f,R,R,m,m,h,f,e,d,GO,GO,GO,GO,nF,nF,GO,GO"))]
1498 && (register_operand (operands[0], DImode)
1499 || reg_or_0_operand (operands[1], DImode))"
1500 "* return output_move_double (operands, insn);"
1501 [(set_attr "length" "8,8,8,8,4,4,8,8,4,4,8,8,8,8,8,8,4,8,8,8,16,16,8,8")
1502 (set_attr "type" "multi,multi,multi,multi,gstore,fstore,gstore,fstore,gload,fload,gload,fload,movfg,movfg,movgf,movgf,gstore,gstore,multi,multi,multi,multi,movgf,movgf")])
1505 [(set (match_operand:DI 0 "register_operand" "")
1506 (match_operand:DI 1 "dbl_memory_two_insn_operand" ""))]
1509 "frv_split_double_load (operands[0], operands[1]);")
1512 [(set (match_operand:DI 0 "odd_reg_operand" "")
1513 (match_operand:DI 1 "memory_operand" ""))]
1516 "frv_split_double_load (operands[0], operands[1]);")
1519 [(set (match_operand:DI 0 "dbl_memory_two_insn_operand" "")
1520 (match_operand:DI 1 "reg_or_0_operand" ""))]
1523 "frv_split_double_store (operands[0], operands[1]);")
1526 [(set (match_operand:DI 0 "memory_operand" "")
1527 (match_operand:DI 1 "odd_reg_operand" ""))]
1530 "frv_split_double_store (operands[0], operands[1]);")
1533 [(set (match_operand:DI 0 "register_operand" "")
1534 (match_operand:DI 1 "register_operand" ""))]
1536 && (odd_reg_operand (operands[0], DImode)
1537 || odd_reg_operand (operands[1], DImode)
1538 || (integer_register_operand (operands[0], DImode)
1539 && integer_register_operand (operands[1], DImode))
1541 && fpr_operand (operands[0], DImode)
1542 && fpr_operand (operands[1], DImode)))"
1543 [(set (match_dup 2) (match_dup 4))
1544 (set (match_dup 3) (match_dup 5))]
1547 rtx op0 = operands[0];
1548 rtx op0_low = gen_lowpart (SImode, op0);
1549 rtx op0_high = gen_highpart (SImode, op0);
1550 rtx op1 = operands[1];
1551 rtx op1_low = gen_lowpart (SImode, op1);
1552 rtx op1_high = gen_highpart (SImode, op1);
1554 /* We normally copy the low-numbered register first. However, if the first
1555 register operand 0 is the same as the second register of operand 1, we
1556 must copy in the opposite order. */
1558 if (REGNO (op0_high) == REGNO (op1_low))
1560 operands[2] = op0_low;
1561 operands[3] = op0_high;
1562 operands[4] = op1_low;
1563 operands[5] = op1_high;
1567 operands[2] = op0_high;
1568 operands[3] = op0_low;
1569 operands[4] = op1_high;
1570 operands[5] = op1_low;
1575 [(set (match_operand:DI 0 "register_operand" "")
1576 (match_operand:DI 1 "const_int_operand" ""))]
1578 [(set (match_dup 2) (match_dup 4))
1579 (set (match_dup 3) (match_dup 1))]
1582 rtx op0 = operands[0];
1583 rtx op1 = operands[1];
1585 operands[2] = gen_highpart (SImode, op0);
1586 operands[3] = gen_lowpart (SImode, op0);
1587 operands[4] = GEN_INT ((INTVAL (op1) < 0) ? -1 : 0);
1591 [(set (match_operand:DI 0 "register_operand" "")
1592 (match_operand:DI 1 "const_double_operand" ""))]
1594 [(set (match_dup 2) (match_dup 4))
1595 (set (match_dup 3) (match_dup 5))]
1598 rtx op0 = operands[0];
1599 rtx op1 = operands[1];
1601 operands[2] = gen_highpart (SImode, op0);
1602 operands[3] = gen_lowpart (SImode, op0);
1603 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (op1));
1604 operands[5] = GEN_INT (CONST_DOUBLE_LOW (op1));
1607 ;; Floating Point Moves
1609 ;; Note - Patterns for SF mode moves are compulsory, but
1610 ;; patterns for DF are optional, as GCC can synthesize them.
1612 (define_expand "movsf"
1613 [(set (match_operand:SF 0 "general_operand" "")
1614 (match_operand:SF 1 "general_operand" ""))]
1618 if (!reload_in_progress
1619 && !reload_completed
1620 && !register_operand (operands[0], SFmode)
1621 && !reg_or_0_operand (operands[1], SFmode))
1622 operands[1] = copy_to_mode_reg (SFmode, operands[1]);
1626 [(set (match_operand:SF 0 "integer_register_operand" "")
1627 (match_operand:SF 1 "int_2word_operand" ""))]
1630 (high:SF (match_dup 1)))
1632 (lo_sum:SF (match_dup 0)
1636 (define_insn "*movsf_load_has_fprs"
1637 [(set (match_operand:SF 0 "register_operand" "=f,d")
1638 (match_operand:SF 1 "frv_load_operand" "m,m"))]
1640 "* return output_move_single (operands, insn);"
1641 [(set_attr "length" "4")
1642 (set_attr "type" "fload,gload")])
1644 (define_insn "*movsf_internal_has_fprs"
1645 [(set (match_operand:SF 0 "move_destination_operand" "=f,f,m,m,?f,?d,?d,m,?d")
1646 (match_operand:SF 1 "move_source_operand" "f,OG,f,OG,d,f,d,d,F"))]
1648 && (register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode))"
1649 "* return output_move_single (operands, insn);"
1650 [(set_attr "length" "4,4,4,4,4,4,4,4,8")
1651 (set_attr "type" "fsconv,movgf,fstore,gstore,movgf,movfg,int,gstore,multi")])
1653 ;; If we don't support the double instructions, prefer gprs over fprs, since it
1654 ;; will all be emulated
1655 (define_insn "*movsf_internal_no_fprs"
1656 [(set (match_operand:SF 0 "move_destination_operand" "=d,d,m,d,d")
1657 (match_operand:SF 1 "move_source_operand" " d,OG,dOG,m,F"))]
1659 && (register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode))"
1660 "* return output_move_single (operands, insn);"
1661 [(set_attr "length" "4,4,4,4,8")
1662 (set_attr "type" "int,int,gstore,gload,multi")])
1664 (define_insn "movsf_high"
1665 [(set (match_operand:SF 0 "integer_register_operand" "=d")
1666 (high:SF (match_operand:SF 1 "int_2word_operand" "i")))]
1669 [(set_attr "type" "sethi")
1670 (set_attr "length" "4")])
1672 (define_insn "movsf_lo_sum"
1673 [(set (match_operand:SF 0 "integer_register_operand" "+d")
1674 (lo_sum:SF (match_dup 0)
1675 (match_operand:SF 1 "int_2word_operand" "i")))]
1678 [(set_attr "type" "setlo")
1679 (set_attr "length" "4")])
1681 (define_expand "movdf"
1682 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1683 (match_operand:DF 1 "general_operand" ""))]
1687 if (!reload_in_progress
1688 && !reload_completed
1689 && !register_operand (operands[0], DFmode)
1690 && !reg_or_0_operand (operands[1], DFmode))
1691 operands[1] = copy_to_mode_reg (DFmode, operands[1]);
1694 (define_insn "*movdf_double"
1695 [(set (match_operand:DF 0 "move_destination_operand" "=h,?e,??f,??d,R,?R,??m,??m,h,?e,??f,??d,?h,??f,?e,??d,R,m,h,??f,e,??d")
1696 (match_operand:DF 1 "move_source_operand" " h,e,f,d,h,e,f,d,R,R,m,m,e,d,h,f,GO,GO,GO,GO,GO,GO"))]
1698 && (register_operand (operands[0], DFmode)
1699 || reg_or_0_operand (operands[1], DFmode))"
1700 "* return output_move_double (operands, insn);"
1701 [(set_attr "length" "4,8,8,8,4,4,8,8,4,4,8,8,4,8,4,8,4,8,8,8,8,8")
1702 (set_attr "type" "fdconv,multi,multi,multi,fstore,gstore,fstore,gstore,fload,gload,fload,gload,movgf,movgf,movfg,movfg,gstore,gstore,movgf,movgf,multi,multi")])
1704 ;; If we don't support the double instructions, prefer gprs over fprs, since it
1705 ;; will all be emulated
1706 (define_insn "*movdf_nodouble"
1707 [(set (match_operand:DF 0 "move_destination_operand" "=e,?h,??d,??f,R,?R,??m,??m,e,?h,??d,??f,?e,??d,?h,??f,R,m,e,??d,e,??d,?h,??f")
1708 (match_operand:DF 1 "move_source_operand" " e,h,d,f,e,h,d,f,R,R,m,m,h,f,e,d,GO,GO,GO,GO,nF,nF,GO,GO"))]
1710 && (register_operand (operands[0], DFmode)
1711 || reg_or_0_operand (operands[1], DFmode))"
1712 "* return output_move_double (operands, insn);"
1713 [(set_attr "length" "8,8,8,8,4,4,8,8,4,4,8,8,8,8,8,8,4,8,8,8,16,16,8,8")
1714 (set_attr "type" "multi,multi,multi,multi,gstore,fstore,gstore,fstore,gload,fload,gload,fload,movfg,movfg,movgf,movgf,gstore,gstore,multi,multi,multi,multi,movgf,movgf")])
1717 [(set (match_operand:DF 0 "register_operand" "")
1718 (match_operand:DF 1 "dbl_memory_two_insn_operand" ""))]
1721 "frv_split_double_load (operands[0], operands[1]);")
1724 [(set (match_operand:DF 0 "odd_reg_operand" "")
1725 (match_operand:DF 1 "memory_operand" ""))]
1728 "frv_split_double_load (operands[0], operands[1]);")
1731 [(set (match_operand:DF 0 "dbl_memory_two_insn_operand" "")
1732 (match_operand:DF 1 "reg_or_0_operand" ""))]
1735 "frv_split_double_store (operands[0], operands[1]);")
1738 [(set (match_operand:DF 0 "memory_operand" "")
1739 (match_operand:DF 1 "odd_reg_operand" ""))]
1742 "frv_split_double_store (operands[0], operands[1]);")
1745 [(set (match_operand:DF 0 "register_operand" "")
1746 (match_operand:DF 1 "register_operand" ""))]
1748 && (odd_reg_operand (operands[0], DFmode)
1749 || odd_reg_operand (operands[1], DFmode)
1750 || (integer_register_operand (operands[0], DFmode)
1751 && integer_register_operand (operands[1], DFmode))
1753 && fpr_operand (operands[0], DFmode)
1754 && fpr_operand (operands[1], DFmode)))"
1755 [(set (match_dup 2) (match_dup 4))
1756 (set (match_dup 3) (match_dup 5))]
1759 rtx op0 = operands[0];
1760 rtx op0_low = gen_lowpart (SImode, op0);
1761 rtx op0_high = gen_highpart (SImode, op0);
1762 rtx op1 = operands[1];
1763 rtx op1_low = gen_lowpart (SImode, op1);
1764 rtx op1_high = gen_highpart (SImode, op1);
1766 /* We normally copy the low-numbered register first. However, if the first
1767 register operand 0 is the same as the second register of operand 1, we
1768 must copy in the opposite order. */
1770 if (REGNO (op0_high) == REGNO (op1_low))
1772 operands[2] = op0_low;
1773 operands[3] = op0_high;
1774 operands[4] = op1_low;
1775 operands[5] = op1_high;
1779 operands[2] = op0_high;
1780 operands[3] = op0_low;
1781 operands[4] = op1_high;
1782 operands[5] = op1_low;
1787 [(set (match_operand:DF 0 "register_operand" "")
1788 (match_operand:DF 1 "const_int_operand" ""))]
1790 [(set (match_dup 2) (match_dup 4))
1791 (set (match_dup 3) (match_dup 1))]
1794 rtx op0 = operands[0];
1795 rtx op1 = operands[1];
1797 operands[2] = gen_highpart (SImode, op0);
1798 operands[3] = gen_lowpart (SImode, op0);
1799 operands[4] = GEN_INT ((INTVAL (op1) < 0) ? -1 : 0);
1803 [(set (match_operand:DF 0 "register_operand" "")
1804 (match_operand:DF 1 "const_double_operand" ""))]
1806 [(set (match_dup 2) (match_dup 4))
1807 (set (match_dup 3) (match_dup 5))]
1810 rtx op0 = operands[0];
1811 rtx op1 = operands[1];
1815 REAL_VALUE_FROM_CONST_DOUBLE (rv, op1);
1816 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
1818 operands[2] = gen_highpart (SImode, op0);
1819 operands[3] = gen_lowpart (SImode, op0);
1820 operands[4] = GEN_INT (l[0]);
1821 operands[5] = GEN_INT (l[1]);
1824 ;; String/block move insn.
1825 ;; Argument 0 is the destination
1826 ;; Argument 1 is the source
1827 ;; Argument 2 is the length
1828 ;; Argument 3 is the alignment
1830 (define_expand "movstrsi"
1831 [(parallel [(set (match_operand:BLK 0 "" "")
1832 (match_operand:BLK 1 "" ""))
1833 (use (match_operand:SI 2 "" ""))
1834 (use (match_operand:SI 3 "" ""))])]
1838 if (frv_expand_block_move (operands))
1844 ;; String/block clear insn.
1845 ;; Argument 0 is the destination
1846 ;; Argument 1 is the length
1847 ;; Argument 2 is the alignment
1849 (define_expand "clrstrsi"
1850 [(parallel [(set (match_operand:BLK 0 "" "")
1852 (use (match_operand:SI 1 "" ""))
1853 (use (match_operand:SI 2 "" ""))])]
1857 if (frv_expand_block_clear (operands))
1864 ;; ::::::::::::::::::::
1866 ;; :: Reload CC registers
1868 ;; ::::::::::::::::::::
1870 ;; Use as a define_expand so that cse/gcse/combine can't accidentally
1871 ;; create movcc insns.
1873 (define_expand "movcc"
1874 [(parallel [(set (match_operand:CC 0 "move_destination_operand" "")
1875 (match_operand:CC 1 "move_source_operand" ""))
1876 (clobber (match_dup 2))])]
1880 if (! reload_in_progress && ! reload_completed)
1883 operands[2] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);
1886 (define_insn "*internal_movcc"
1887 [(set (match_operand:CC 0 "move_destination_operand" "=t,d,d,m,d")
1888 (match_operand:CC 1 "move_source_operand" "d,d,m,d,t"))
1889 (clobber (match_scratch:CC_CCR 2 "=X,X,X,X,&v"))]
1890 "reload_in_progress || reload_completed"
1897 [(set_attr "length" "4,4,4,4,20")
1898 (set_attr "type" "int,int,gload,gstore,multi")])
1900 ;; To move an ICC value to a GPR for a signed comparison, we create a value
1901 ;; that when compared to 0, sets the N and Z flags appropriately (we don't care
1902 ;; about the V and C flags, since these comparisons are signed).
1905 [(set (match_operand:CC 0 "integer_register_operand" "")
1906 (match_operand:CC 1 "icc_operand" ""))
1907 (clobber (match_operand:CC_CCR 2 "icr_operand" ""))]
1908 "reload_in_progress || reload_completed"
1912 rtx dest = simplify_gen_subreg (SImode, operands[0], CCmode, 0);
1913 rtx icc = operands[1];
1914 rtx icr = operands[2];
1918 emit_insn (gen_rtx_SET (VOIDmode, icr,
1919 gen_rtx_LT (CC_CCRmode, icc, const0_rtx)));
1921 emit_insn (gen_movsi (dest, const1_rtx));
1923 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
1924 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
1925 gen_rtx_SET (VOIDmode, dest,
1926 gen_rtx_NEG (SImode, dest))));
1928 emit_insn (gen_rtx_SET (VOIDmode, icr,
1929 gen_rtx_EQ (CC_CCRmode, icc, const0_rtx)));
1931 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
1932 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
1933 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
1935 operands[3] = get_insns ();
1939 (define_expand "reload_incc"
1940 [(parallel [(set (match_operand:CC 2 "integer_register_operand" "=&d")
1941 (match_operand:CC 1 "memory_operand" "m"))
1942 (clobber (match_scratch:CC_CCR 3 ""))])
1943 (parallel [(set (match_operand:CC 0 "icc_operand" "=t")
1945 (clobber (match_scratch:CC_CCR 4 ""))])]
1949 (define_expand "reload_outcc"
1950 [(parallel [(set (match_operand:CC 2 "integer_register_operand" "=&d")
1951 (match_operand:CC 1 "icc_operand" "t"))
1952 (clobber (match_dup 3))])
1953 (parallel [(set (match_operand:CC 0 "memory_operand" "=m")
1955 (clobber (match_scratch:CC_CCR 4 ""))])]
1957 "operands[3] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);")
1959 ;; Reload CC_UNSmode for unsigned integer comparisons
1960 ;; Use define_expand so that cse/gcse/combine can't create movcc_uns insns
1962 (define_expand "movcc_uns"
1963 [(parallel [(set (match_operand:CC_UNS 0 "move_destination_operand" "")
1964 (match_operand:CC_UNS 1 "move_source_operand" ""))
1965 (clobber (match_dup 2))])]
1969 if (! reload_in_progress && ! reload_completed)
1971 operands[2] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);
1974 (define_insn "*internal_movcc_uns"
1975 [(set (match_operand:CC_UNS 0 "move_destination_operand" "=t,d,d,m,d")
1976 (match_operand:CC_UNS 1 "move_source_operand" "d,d,m,d,t"))
1977 (clobber (match_scratch:CC_CCR 2 "=X,X,X,X,&v"))]
1978 "reload_in_progress || reload_completed"
1985 [(set_attr "length" "4,4,4,4,20")
1986 (set_attr "type" "int,int,gload,gstore,multi")])
1988 ;; To move an ICC value to a GPR for an unsigned comparison, we create a value
1989 ;; that when compared to 1, sets the Z, V, and C flags appropriately (we don't
1990 ;; care about the N flag, since these comparisons are unsigned).
1993 [(set (match_operand:CC_UNS 0 "integer_register_operand" "")
1994 (match_operand:CC_UNS 1 "icc_operand" ""))
1995 (clobber (match_operand:CC_CCR 2 "icr_operand" ""))]
1996 "reload_in_progress || reload_completed"
2000 rtx dest = simplify_gen_subreg (SImode, operands[0], CC_UNSmode, 0);
2001 rtx icc = operands[1];
2002 rtx icr = operands[2];
2006 emit_insn (gen_rtx_SET (VOIDmode, icr,
2007 gen_rtx_GTU (CC_CCRmode, icc, const0_rtx)));
2009 emit_insn (gen_movsi (dest, const1_rtx));
2011 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2012 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2013 gen_addsi3 (dest, dest, dest)));
2015 emit_insn (gen_rtx_SET (VOIDmode, icr,
2016 gen_rtx_LTU (CC_CCRmode, icc, const0_rtx)));
2018 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2019 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2020 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
2022 operands[3] = get_insns ();
2026 (define_expand "reload_incc_uns"
2027 [(parallel [(set (match_operand:CC_UNS 2 "integer_register_operand" "=&d")
2028 (match_operand:CC_UNS 1 "memory_operand" "m"))
2029 (clobber (match_scratch:CC_CCR 3 ""))])
2030 (parallel [(set (match_operand:CC_UNS 0 "icc_operand" "=t")
2032 (clobber (match_scratch:CC_CCR 4 ""))])]
2036 (define_expand "reload_outcc_uns"
2037 [(parallel [(set (match_operand:CC_UNS 2 "integer_register_operand" "=&d")
2038 (match_operand:CC_UNS 1 "icc_operand" "t"))
2039 (clobber (match_dup 3))])
2040 (parallel [(set (match_operand:CC_UNS 0 "memory_operand" "=m")
2042 (clobber (match_scratch:CC_CCR 4 ""))])]
2044 "operands[3] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);")
2046 ;; Reload CC_FPmode for floating point comparisons
2047 ;; We use a define_expand here so that cse/gcse/combine can't accidentally
2048 ;; create movcc insns. If this was a named define_insn, we would not be able
2049 ;; to make it conditional on reload.
2051 (define_expand "movcc_fp"
2052 [(set (match_operand:CC_FP 0 "move_destination_operand" "")
2053 (match_operand:CC_FP 1 "move_source_operand" ""))]
2057 if (! reload_in_progress && ! reload_completed)
2061 (define_insn "*movcc_fp_internal"
2062 [(set (match_operand:CC_FP 0 "move_destination_operand" "=d,d,d,m")
2063 (match_operand:CC_FP 1 "move_source_operand" "u,d,m,d"))]
2064 "TARGET_HAS_FPRS && (reload_in_progress || reload_completed)"
2070 [(set_attr "length" "12,4,4,4")
2071 (set_attr "type" "multi,int,gload,gstore")])
2074 (define_expand "reload_incc_fp"
2075 [(match_operand:CC_FP 0 "fcc_operand" "=u")
2076 (match_operand:CC_FP 1 "memory_operand" "m")
2077 (match_operand:TI 2 "integer_register_operand" "=&d")]
2081 rtx cc_op2 = simplify_gen_subreg (CC_FPmode, operands[2], TImode, 0);
2082 rtx int_op2 = simplify_gen_subreg (SImode, operands[2], TImode, 0);
2083 rtx temp1 = simplify_gen_subreg (SImode, operands[2], TImode, 4);
2084 rtx temp2 = simplify_gen_subreg (SImode, operands[2], TImode, 8);
2085 int shift = CC_SHIFT_RIGHT (REGNO (operands[0]));
2088 emit_insn (gen_movcc_fp (cc_op2, operands[1]));
2090 emit_insn (gen_ashlsi3 (int_op2, int_op2, GEN_INT (shift)));
2092 mask = ~ ((HOST_WIDE_INT)CC_MASK << shift);
2093 emit_insn (gen_movsi (temp1, GEN_INT (mask)));
2094 emit_insn (gen_update_fcc (operands[0], int_op2, temp1, temp2));
2098 (define_expand "reload_outcc_fp"
2099 [(set (match_operand:CC_FP 2 "integer_register_operand" "=&d")
2100 (match_operand:CC_FP 1 "fcc_operand" "u"))
2101 (set (match_operand:CC_FP 0 "memory_operand" "=m")
2106 ;; Convert a FCC value to gpr
2107 (define_insn "read_fcc"
2108 [(set (match_operand:SI 0 "integer_register_operand" "=d")
2109 (unspec:SI [(match_operand:CC_FP 1 "fcc_operand" "u")]
2113 [(set_attr "type" "spr")
2114 (set_attr "length" "4")])
2117 [(set (match_operand:CC_FP 0 "integer_register_operand" "")
2118 (match_operand:CC_FP 1 "fcc_operand" ""))]
2119 "reload_completed && TARGET_HAS_FPRS"
2123 rtx int_op0 = simplify_gen_subreg (SImode, operands[0], CC_FPmode, 0);
2124 int shift = CC_SHIFT_RIGHT (REGNO (operands[1]));
2128 emit_insn (gen_read_fcc (int_op0, operands[1]));
2130 emit_insn (gen_lshrsi3 (int_op0, int_op0, GEN_INT (shift)));
2132 emit_insn (gen_andsi3 (int_op0, int_op0, GEN_INT (CC_MASK)));
2134 operands[2] = get_insns ();
2138 ;; Move a gpr value to FCC.
2140 ;; Operand1 = reloaded value shifted appropriately
2141 ;; Operand2 = mask to eliminate current register
2142 ;; Operand3 = temporary to load/store ccr
2143 (define_insn "update_fcc"
2144 [(set (match_operand:CC_FP 0 "fcc_operand" "=u")
2145 (unspec:CC_FP [(match_operand:SI 1 "integer_register_operand" "d")
2146 (match_operand:SI 2 "integer_register_operand" "d")]
2148 (clobber (match_operand:SI 3 "integer_register_operand" "=&d"))]
2150 "movsg ccr, %3\;and %2, %3, %3\;or %1, %3, %3\;movgs %3, ccr"
2151 [(set_attr "type" "multi")
2152 (set_attr "length" "16")])
2154 ;; Reload CC_CCRmode for conditional execution registers
2155 (define_insn "movcc_ccr"
2156 [(set (match_operand:CC_CCR 0 "move_destination_operand" "=d,d,d,m,v,?w,C,d")
2157 (match_operand:CC_CCR 1 "move_source_operand" "C,d,m,d,n,n,C,L"))]
2168 [(set_attr "length" "8,4,4,4,8,12,4,4")
2169 (set_attr "type" "multi,int,gload,gstore,multi,multi,ccr,int")])
2171 (define_expand "reload_incc_ccr"
2172 [(match_operand:CC_CCR 0 "cr_operand" "=C")
2173 (match_operand:CC_CCR 1 "memory_operand" "m")
2174 (match_operand:CC_CCR 2 "integer_register_operand" "=&d")]
2178 rtx icc = gen_rtx_REG (CCmode, ICC_TEMP);
2179 rtx int_op2 = simplify_gen_subreg (SImode, operands[2], CC_CCRmode, 0);
2180 rtx icr = (ICR_P (REGNO (operands[0]))
2181 ? operands[0] : gen_rtx_REG (CC_CCRmode, ICR_TEMP));
2183 emit_insn (gen_movcc_ccr (operands[2], operands[1]));
2184 emit_insn (gen_cmpsi_cc (icc, int_op2, const0_rtx));
2185 emit_insn (gen_movcc_ccr (icr, gen_rtx_NE (CC_CCRmode, icc, const0_rtx)));
2187 if (! ICR_P (REGNO (operands[0])))
2188 emit_insn (gen_movcc_ccr (operands[0], icr));
2193 (define_expand "reload_outcc_ccr"
2194 [(set (match_operand:CC_CCR 2 "integer_register_operand" "=&d")
2195 (match_operand:CC_CCR 1 "cr_operand" "C"))
2196 (set (match_operand:CC_CCR 0 "memory_operand" "=m")
2202 [(set (match_operand:CC_CCR 0 "integer_register_operand" "")
2203 (match_operand:CC_CCR 1 "cr_operand" ""))]
2208 rtx int_op0 = simplify_gen_subreg (SImode, operands[0], CC_CCRmode, 0);
2211 emit_move_insn (operands[0], const1_rtx);
2212 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2213 gen_rtx_EQ (CC_CCRmode,
2216 gen_rtx_SET (VOIDmode, int_op0,
2219 operands[2] = get_insns ();
2224 [(set (match_operand:CC_CCR 0 "cr_operand" "")
2225 (match_operand:CC_CCR 1 "const_int_operand" ""))]
2230 rtx icc = gen_rtx_REG (CCmode, ICC_TEMP);
2231 rtx r0 = gen_rtx_REG (SImode, GPR_FIRST);
2232 rtx icr = (ICR_P (REGNO (operands[0]))
2233 ? operands[0] : gen_rtx_REG (CC_CCRmode, ICR_TEMP));
2237 emit_insn (gen_cmpsi_cc (icc, r0, const0_rtx));
2239 emit_insn (gen_movcc_ccr (icr,
2240 gen_rtx_fmt_ee (((INTVAL (operands[1]) == 0)
2241 ? EQ : NE), CC_CCRmode,
2244 if (! ICR_P (REGNO (operands[0])))
2245 emit_insn (gen_movcc_ccr (operands[0], icr));
2247 operands[2] = get_insns ();
2252 ;; ::::::::::::::::::::
2256 ;; ::::::::::::::::::::
2258 ;; Signed conversions from a smaller integer to a larger integer
2260 ;; These operations are optional. If they are not
2261 ;; present GCC will synthesize them for itself
2262 ;; Even though frv does not provide these instructions, we define them
2263 ;; to allow load + sign extend to be collapsed together
2264 (define_insn "extendqihi2"
2265 [(set (match_operand:HI 0 "integer_register_operand" "=d,d")
2266 (sign_extend:HI (match_operand:QI 1 "gpr_or_memory_operand" "d,m")))]
2271 [(set_attr "length" "8,4")
2272 (set_attr "type" "multi,gload")])
2275 [(set (match_operand:HI 0 "integer_register_operand" "")
2276 (sign_extend:HI (match_operand:QI 1 "integer_register_operand" "")))]
2282 rtx op0 = gen_lowpart (SImode, operands[0]);
2283 rtx op1 = gen_lowpart (SImode, operands[1]);
2284 rtx shift = GEN_INT (24);
2286 operands[2] = gen_ashlsi3 (op0, op1, shift);
2287 operands[3] = gen_ashrsi3 (op0, op0, shift);
2290 (define_insn "extendqisi2"
2291 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2292 (sign_extend:SI (match_operand:QI 1 "gpr_or_memory_operand" "d,m")))]
2297 [(set_attr "length" "8,4")
2298 (set_attr "type" "multi,gload")])
2301 [(set (match_operand:SI 0 "integer_register_operand" "")
2302 (sign_extend:SI (match_operand:QI 1 "integer_register_operand" "")))]
2308 rtx op0 = gen_lowpart (SImode, operands[0]);
2309 rtx op1 = gen_lowpart (SImode, operands[1]);
2310 rtx shift = GEN_INT (24);
2312 operands[2] = gen_ashlsi3 (op0, op1, shift);
2313 operands[3] = gen_ashrsi3 (op0, op0, shift);
2316 ;;(define_insn "extendqidi2"
2317 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2318 ;; (sign_extend:DI (match_operand:QI 1 "general_operand" "g")))]
2320 ;; "extendqihi2 %0,%1"
2321 ;; [(set_attr "length" "4")])
2323 (define_insn "extendhisi2"
2324 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2325 (sign_extend:SI (match_operand:HI 1 "gpr_or_memory_operand" "d,m")))]
2330 [(set_attr "length" "8,4")
2331 (set_attr "type" "multi,gload")])
2334 [(set (match_operand:SI 0 "integer_register_operand" "")
2335 (sign_extend:SI (match_operand:HI 1 "integer_register_operand" "")))]
2341 rtx op0 = gen_lowpart (SImode, operands[0]);
2342 rtx op1 = gen_lowpart (SImode, operands[1]);
2343 rtx shift = GEN_INT (16);
2345 operands[2] = gen_ashlsi3 (op0, op1, shift);
2346 operands[3] = gen_ashrsi3 (op0, op0, shift);
2349 ;;(define_insn "extendhidi2"
2350 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2351 ;; (sign_extend:DI (match_operand:HI 1 "general_operand" "g")))]
2353 ;; "extendhihi2 %0,%1"
2354 ;; [(set_attr "length" "4")])
2356 ;;(define_insn "extendsidi2"
2357 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2358 ;; (sign_extend:DI (match_operand:SI 1 "general_operand" "g")))]
2360 ;; "extendsidi2 %0,%1"
2361 ;; [(set_attr "length" "4")])
2363 ;; Unsigned conversions from a smaller integer to a larger integer
2364 (define_insn "zero_extendqihi2"
2365 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
2367 (match_operand:QI 1 "gpr_or_memory_operand" "d,L,m")))]
2373 [(set_attr "length" "4")
2374 (set_attr "type" "int,int,gload")])
2376 (define_insn "zero_extendqisi2"
2377 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
2379 (match_operand:QI 1 "gpr_or_memory_operand" "d,L,m")))]
2385 [(set_attr "length" "4")
2386 (set_attr "type" "int,int,gload")])
2388 ;;(define_insn "zero_extendqidi2"
2389 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2390 ;; (zero_extend:DI (match_operand:QI 1 "general_operand" "g")))]
2392 ;; "zero_extendqihi2 %0,%1"
2393 ;; [(set_attr "length" "4")])
2395 ;; Do not set the type for the sethi to "sethi", since the scheduler will think
2396 ;; the sethi takes 0 cycles as part of allowing sethi/setlo to be in the same
2397 ;; VLIW instruction.
2398 (define_insn "zero_extendhisi2"
2399 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2400 (zero_extend:SI (match_operand:HI 1 "gpr_or_memory_operand" "0,m")))]
2405 [(set_attr "length" "4")
2406 (set_attr "type" "int,gload")])
2408 ;;(define_insn "zero_extendhidi2"
2409 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2410 ;; (zero_extend:DI (match_operand:HI 1 "general_operand" "g")))]
2412 ;; "zero_extendhihi2 %0,%1"
2413 ;; [(set_attr "length" "4")])
2415 ;;(define_insn "zero_extendsidi2"
2416 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2417 ;; (zero_extend:DI (match_operand:SI 1 "general_operand" "g")))]
2419 ;; "zero_extendsidi2 %0,%1"
2420 ;; [(set_attr "length" "4")])
2422 ;;;; Convert between floating point types of different sizes.
2424 ;;(define_insn "extendsfdf2"
2425 ;; [(set (match_operand:DF 0 "register_operand" "=r")
2426 ;; (float_extend:DF (match_operand:SF 1 "register_operand" "r")))]
2428 ;; "extendsfdf2 %0,%1"
2429 ;; [(set_attr "length" "4")])
2431 ;;(define_insn "truncdfsf2"
2432 ;; [(set (match_operand:SF 0 "register_operand" "=r")
2433 ;; (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))]
2435 ;; "truncdfsf2 %0,%1"
2436 ;; [(set_attr "length" "4")])
2438 ;;;; Convert between signed integer types and floating point.
2439 (define_insn "floatsisf2"
2440 [(set (match_operand:SF 0 "fpr_operand" "=f")
2441 (float:SF (match_operand:SI 1 "fpr_operand" "f")))]
2444 [(set_attr "length" "4")
2445 (set_attr "type" "fsconv")])
2447 (define_insn "floatsidf2"
2448 [(set (match_operand:DF 0 "fpr_operand" "=h")
2449 (float:DF (match_operand:SI 1 "fpr_operand" "f")))]
2450 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
2452 [(set_attr "length" "4")
2453 (set_attr "type" "fdconv")])
2455 ;;(define_insn "floatdisf2"
2456 ;; [(set (match_operand:SF 0 "register_operand" "=r")
2457 ;; (float:SF (match_operand:DI 1 "register_operand" "r")))]
2459 ;; "floatdisf2 %0,%1"
2460 ;; [(set_attr "length" "4")])
2462 ;;(define_insn "floatdidf2"
2463 ;; [(set (match_operand:DF 0 "register_operand" "=r")
2464 ;; (float:DF (match_operand:DI 1 "register_operand" "r")))]
2466 ;; "floatdidf2 %0,%1"
2467 ;; [(set_attr "length" "4")])
2469 (define_insn "fix_truncsfsi2"
2470 [(set (match_operand:SI 0 "fpr_operand" "=f")
2471 (fix:SI (match_operand:SF 1 "fpr_operand" "f")))]
2474 [(set_attr "length" "4")
2475 (set_attr "type" "fsconv")])
2477 (define_insn "fix_truncdfsi2"
2478 [(set (match_operand:SI 0 "fpr_operand" "=f")
2479 (fix:SI (match_operand:DF 1 "fpr_operand" "h")))]
2480 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
2482 [(set_attr "length" "4")
2483 (set_attr "type" "fdconv")])
2485 ;;(define_insn "fix_truncsfdi2"
2486 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2487 ;; (fix:DI (match_operand:SF 1 "register_operand" "r")))]
2489 ;; "fix_truncsfdi2 %0,%1"
2490 ;; [(set_attr "length" "4")])
2492 ;;(define_insn "fix_truncdfdi2"
2493 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2494 ;; (fix:DI (match_operand:DF 1 "register_operand" "r")))]
2496 ;; "fix_truncdfdi2 %0,%1"
2497 ;; [(set_attr "length" "4")])
2499 ;;;; Convert between unsigned integer types and floating point.
2501 ;;(define_insn "floatunssisf2"
2502 ;; [(set (match_operand:SF 0 "register_operand" "=r")
2503 ;; (unsigned_float:SF (match_operand:SI 1 "register_operand" "r")))]
2505 ;; "floatunssisf2 %0,%1"
2506 ;; [(set_attr "length" "4")])
2508 ;;(define_insn "floatunssidf2"
2509 ;; [(set (match_operand:DF 0 "register_operand" "=r")
2510 ;; (unsigned_float:DF (match_operand:SI 1 "register_operand" "r")))]
2512 ;; "floatunssidf2 %0,%1"
2513 ;; [(set_attr "length" "4")])
2515 ;;(define_insn "floatunsdisf2"
2516 ;; [(set (match_operand:SF 0 "register_operand" "=r")
2517 ;; (unsigned_float:SF (match_operand:DI 1 "register_operand" "r")))]
2519 ;; "floatunsdisf2 %0,%1"
2520 ;; [(set_attr "length" "4")])
2522 ;;(define_insn "floatunsdidf2"
2523 ;; [(set (match_operand:DF 0 "register_operand" "=r")
2524 ;; (unsigned_float:DF (match_operand:DI 1 "register_operand" "r")))]
2526 ;; "floatunsdidf2 %0,%1"
2527 ;; [(set_attr "length" "4")])
2529 ;;(define_insn "fixuns_truncsfsi2"
2530 ;; [(set (match_operand:SI 0 "register_operand" "=r")
2531 ;; (unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))]
2533 ;; "fixuns_truncsfsi2 %0,%1"
2534 ;; [(set_attr "length" "4")])
2536 ;;(define_insn "fixuns_truncdfsi2"
2537 ;; [(set (match_operand:SI 0 "register_operand" "=r")
2538 ;; (unsigned_fix:SI (match_operand:DF 1 "register_operand" "r")))]
2540 ;; "fixuns_truncdfsi2 %0,%1"
2541 ;; [(set_attr "length" "4")])
2543 ;;(define_insn "fixuns_truncsfdi2"
2544 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2545 ;; (unsigned_fix:DI (match_operand:SF 1 "register_operand" "r")))]
2547 ;; "fixuns_truncsfdi2 %0,%1"
2548 ;; [(set_attr "length" "4")])
2550 ;;(define_insn "fixuns_truncdfdi2"
2551 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2552 ;; (unsigned_fix:DI (match_operand:DF 1 "register_operand" "r")))]
2554 ;; "fixuns_truncdfdi2 %0,%1"
2555 ;; [(set_attr "length" "4")])
2558 ;; ::::::::::::::::::::
2560 ;; :: 32 bit Integer arithmetic
2562 ;; ::::::::::::::::::::
2565 (define_insn "addsi3"
2566 [(set (match_operand:SI 0 "integer_register_operand" "=d")
2567 (plus:SI (match_operand:SI 1 "integer_register_operand" "%d")
2568 (match_operand:SI 2 "gpr_or_int12_operand" "dNOP")))]
2571 [(set_attr "length" "4")
2572 (set_attr "type" "int")])
2574 ;; Subtraction. No need to worry about constants, since the compiler
2575 ;; canonicalizes them into addsi3's. We prevent SUBREG's here to work around a
2576 ;; combine bug, that combines the 32x32->upper 32 bit multiply that uses a
2577 ;; SUBREG with a minus that shows up in modulus by constants.
2578 (define_insn "subsi3"
2579 [(set (match_operand:SI 0 "integer_register_operand" "=d")
2580 (minus:SI (match_operand:SI 1 "gpr_no_subreg_operand" "d")
2581 (match_operand:SI 2 "gpr_no_subreg_operand" "d")))]
2584 [(set_attr "length" "4")
2585 (set_attr "type" "int")])
2587 ;; Signed multiplication producing 64 bit results from 32 bit inputs
2588 ;; Note, frv doesn't have a 32x32->32 bit multiply, but the compiler
2589 ;; will do the 32x32->64 bit multiply and use the bottom word.
2590 (define_expand "mulsidi3"
2591 [(set (match_operand:DI 0 "integer_register_operand" "")
2592 (mult:DI (sign_extend:DI (match_operand:SI 1 "integer_register_operand" ""))
2593 (sign_extend:DI (match_operand:SI 2 "gpr_or_int12_operand" ""))))]
2597 if (GET_CODE (operands[2]) == CONST_INT)
2599 emit_insn (gen_mulsidi3_const (operands[0], operands[1], operands[2]));
2604 (define_insn "*mulsidi3_reg"
2605 [(set (match_operand:DI 0 "even_gpr_operand" "=e")
2606 (mult:DI (sign_extend:DI (match_operand:SI 1 "integer_register_operand" "%d"))
2607 (sign_extend:DI (match_operand:SI 2 "integer_register_operand" "d"))))]
2610 [(set_attr "length" "4")
2611 (set_attr "type" "mul")])
2613 (define_insn "mulsidi3_const"
2614 [(set (match_operand:DI 0 "even_gpr_operand" "=e")
2615 (mult:DI (sign_extend:DI (match_operand:SI 1 "integer_register_operand" "d"))
2616 (match_operand:SI 2 "int12_operand" "NOP")))]
2619 [(set_attr "length" "4")
2620 (set_attr "type" "mul")])
2622 ;; Unsigned multiplication producing 64 bit results from 32 bit inputs
2623 (define_expand "umulsidi3"
2624 [(set (match_operand:DI 0 "even_gpr_operand" "")
2625 (mult:DI (zero_extend:DI (match_operand:SI 1 "integer_register_operand" ""))
2626 (zero_extend:DI (match_operand:SI 2 "gpr_or_int12_operand" ""))))]
2630 if (GET_CODE (operands[2]) == CONST_INT)
2632 emit_insn (gen_umulsidi3_const (operands[0], operands[1], operands[2]));
2637 (define_insn "*mulsidi3_reg"
2638 [(set (match_operand:DI 0 "even_gpr_operand" "=e")
2639 (mult:DI (zero_extend:DI (match_operand:SI 1 "integer_register_operand" "%d"))
2640 (zero_extend:DI (match_operand:SI 2 "integer_register_operand" "d"))))]
2643 [(set_attr "length" "4")
2644 (set_attr "type" "mul")])
2646 (define_insn "umulsidi3_const"
2647 [(set (match_operand:DI 0 "even_gpr_operand" "=e")
2648 (mult:DI (zero_extend:DI (match_operand:SI 1 "integer_register_operand" "d"))
2649 (match_operand:SI 2 "int12_operand" "NOP")))]
2652 [(set_attr "length" "4")
2653 (set_attr "type" "mul")])
2656 (define_insn "divsi3"
2657 [(set (match_operand:SI 0 "register_operand" "=d,d")
2658 (div:SI (match_operand:SI 1 "register_operand" "d,d")
2659 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
2662 [(set_attr "length" "4")
2663 (set_attr "type" "div")])
2665 ;; Unsigned Division
2666 (define_insn "udivsi3"
2667 [(set (match_operand:SI 0 "register_operand" "=d,d")
2668 (udiv:SI (match_operand:SI 1 "register_operand" "d,d")
2669 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
2672 [(set_attr "length" "4")
2673 (set_attr "type" "div")])
2676 (define_insn "negsi2"
2677 [(set (match_operand:SI 0 "integer_register_operand" "=d")
2678 (neg:SI (match_operand:SI 1 "integer_register_operand" "d")))]
2681 [(set_attr "length" "4")
2682 (set_attr "type" "int")])
2684 ;; Find first one bit
2685 ;; (define_insn "ffssi2"
2686 ;; [(set (match_operand:SI 0 "register_operand" "=r")
2687 ;; (ffs:SI (match_operand:SI 1 "register_operand" "r")))]
2690 ;; [(set_attr "length" "4")])
2693 ;; ::::::::::::::::::::
2695 ;; :: 64 bit Integer arithmetic
2697 ;; ::::::::::::::::::::
2700 (define_expand "adddi3"
2701 [(parallel [(set (match_operand:DI 0 "integer_register_operand" "")
2702 (plus:DI (match_operand:DI 1 "integer_register_operand" "")
2703 (match_operand:DI 2 "gpr_or_int10_operand" "")))
2704 (clobber (match_scratch:CC 3 ""))])]
2708 if (GET_CODE (operands[2]) == CONST_INT
2709 && INTVAL (operands[2]) == -2048
2711 operands[2] = force_reg (DImode, operands[2]);
2714 (define_insn_and_split "*adddi3_internal"
2715 [(set (match_operand:DI 0 "integer_register_operand" "=&e,e,e,&e,e,&e,e")
2716 (plus:DI (match_operand:DI 1 "integer_register_operand" "%e,0,e,e,0,e,0")
2717 (match_operand:DI 2 "gpr_or_int10_operand" "e,e,0,N,N,OP,OP")))
2718 (clobber (match_scratch:CC 3 "=t,t,t,t,t,t,t"))]
2719 "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -2048"
2726 rtx op0_high = gen_highpart (SImode, operands[0]);
2727 rtx op1_high = gen_highpart (SImode, operands[1]);
2728 rtx op0_low = gen_lowpart (SImode, operands[0]);
2729 rtx op1_low = gen_lowpart (SImode, operands[1]);
2730 rtx op2 = operands[2];
2731 rtx op3 = operands[3];
2733 if (GET_CODE (op2) != CONST_INT)
2735 rtx op2_high = gen_highpart (SImode, operands[2]);
2736 rtx op2_low = gen_lowpart (SImode, operands[2]);
2737 operands[4] = gen_adddi3_lower (op0_low, op1_low, op2_low, op3);
2738 operands[5] = gen_adddi3_upper (op0_high, op1_high, op2_high, op3);
2740 else if (INTVAL (op2) >= 0)
2742 operands[4] = gen_adddi3_lower (op0_low, op1_low, op2, op3);
2743 operands[5] = gen_adddi3_upper (op0_high, op1_high, const0_rtx, op3);
2747 operands[4] = gen_subdi3_lower (op0_low, op1_low,
2748 GEN_INT (- INTVAL (op2)), op3);
2749 operands[5] = gen_subdi3_upper (op0_high, op1_high, const0_rtx, op3);
2752 [(set_attr "length" "8")
2753 (set_attr "type" "multi")])
2755 ;; Subtraction No need to worry about constants, since the compiler
2756 ;; canonicalizes them into adddi3's.
2757 (define_expand "subdi3"
2758 [(parallel [(set (match_operand:DI 0 "integer_register_operand" "")
2759 (minus:DI (match_operand:DI 1 "integer_register_operand" "")
2760 (match_operand:DI 2 "integer_register_operand" "")))
2761 (clobber (match_dup 3))])]
2765 operands[3] = gen_reg_rtx (CCmode);
2768 (define_insn_and_split "*subdi3_internal"
2769 [(set (match_operand:DI 0 "integer_register_operand" "=&e,e,e")
2770 (minus:DI (match_operand:DI 1 "integer_register_operand" "e,0,e")
2771 (match_operand:DI 2 "integer_register_operand" "e,e,0")))
2772 (clobber (match_operand:CC 3 "icc_operand" "=t,t,t"))]
2780 rtx op0_high = gen_highpart (SImode, operands[0]);
2781 rtx op1_high = gen_highpart (SImode, operands[1]);
2782 rtx op2_high = gen_highpart (SImode, operands[2]);
2783 rtx op0_low = gen_lowpart (SImode, operands[0]);
2784 rtx op1_low = gen_lowpart (SImode, operands[1]);
2785 rtx op2_low = gen_lowpart (SImode, operands[2]);
2786 rtx op3 = operands[3];
2788 operands[4] = gen_subdi3_lower (op0_low, op1_low, op2_low, op3);
2789 operands[5] = gen_subdi3_upper (op0_high, op1_high, op2_high, op3);
2791 [(set_attr "length" "8")
2792 (set_attr "type" "multi")])
2794 ;; Patterns for addsi3/subdi3 after spliting
2795 (define_insn "adddi3_lower"
2796 [(set (match_operand:SI 0 "integer_register_operand" "=d")
2797 (plus:SI (match_operand:SI 1 "integer_register_operand" "d")
2798 (match_operand:SI 2 "gpr_or_int10_operand" "dOP")))
2799 (set (match_operand:CC 3 "icc_operand" "=t")
2800 (compare:CC (plus:SI (match_dup 1)
2803 "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) >= 0"
2804 "add%I2cc %1,%2,%0,%3"
2805 [(set_attr "length" "4")
2806 (set_attr "type" "int")])
2808 (define_insn "adddi3_upper"
2809 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2810 (plus:SI (match_operand:SI 1 "integer_register_operand" "d,d")
2811 (plus:SI (match_operand:SI 2 "reg_or_0_operand" "d,O")
2812 (match_operand:CC 3 "icc_operand" "t,t"))))]
2817 [(set_attr "length" "4")
2818 (set_attr "type" "int")])
2820 (define_insn "subdi3_lower"
2821 [(set (match_operand:SI 0 "integer_register_operand" "=d")
2822 (minus:SI (match_operand:SI 1 "integer_register_operand" "d")
2823 (match_operand:SI 2 "gpr_or_int10_operand" "dOP")))
2824 (set (match_operand:CC 3 "icc_operand" "=t")
2825 (compare:CC (plus:SI (match_dup 1)
2828 "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) >= 0"
2829 "sub%I2cc %1,%2,%0,%3"
2830 [(set_attr "length" "4")
2831 (set_attr "type" "int")])
2833 (define_insn "subdi3_upper"
2834 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2835 (minus:SI (match_operand:SI 1 "integer_register_operand" "d,d")
2836 (minus:SI (match_operand:SI 2 "reg_or_0_operand" "d,O")
2837 (match_operand:CC 3 "icc_operand" "t,t"))))]
2842 [(set_attr "length" "4")
2843 (set_attr "type" "int")])
2845 ;; Multiplication (same size)
2846 ;; (define_insn "muldi3"
2847 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2848 ;; (mult:DI (match_operand:DI 1 "register_operand" "%r")
2849 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
2851 ;; "muldi3 %0,%1,%2"
2852 ;; [(set_attr "length" "4")])
2855 ;; (define_insn "divdi3"
2856 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2857 ;; (div:DI (match_operand:DI 1 "register_operand" "r")
2858 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
2860 ;; "divdi3 %0,%1,%2"
2861 ;; [(set_attr "length" "4")])
2863 ;; Undsgned Division
2864 ;; (define_insn "udivdi3"
2865 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2866 ;; (udiv:DI (match_operand:DI 1 "register_operand" "r")
2867 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
2869 ;; "udivdi3 %0,%1,%2"
2870 ;; [(set_attr "length" "4")])
2873 ;; (define_insn "negdi2"
2874 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2875 ;; (neg:DI (match_operand:DI 1 "register_operand" "r")))]
2878 ;; [(set_attr "length" "4")])
2880 ;; Find first one bit
2881 ;; (define_insn "ffsdi2"
2882 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2883 ;; (ffs:DI (match_operand:DI 1 "register_operand" "r")))]
2886 ;; [(set_attr "length" "4")])
2889 ;; ::::::::::::::::::::
2891 ;; :: 32 bit floating point arithmetic
2893 ;; ::::::::::::::::::::
2896 (define_insn "addsf3"
2897 [(set (match_operand:SF 0 "fpr_operand" "=f")
2898 (plus:SF (match_operand:SF 1 "fpr_operand" "%f")
2899 (match_operand:SF 2 "fpr_operand" "f")))]
2902 [(set_attr "length" "4")
2903 (set_attr "type" "fsadd")])
2906 (define_insn "subsf3"
2907 [(set (match_operand:SF 0 "fpr_operand" "=f")
2908 (minus:SF (match_operand:SF 1 "fpr_operand" "f")
2909 (match_operand:SF 2 "fpr_operand" "f")))]
2912 [(set_attr "length" "4")
2913 (set_attr "type" "fsadd")])
2916 (define_insn "mulsf3"
2917 [(set (match_operand:SF 0 "fpr_operand" "=f")
2918 (mult:SF (match_operand:SF 1 "fpr_operand" "%f")
2919 (match_operand:SF 2 "fpr_operand" "f")))]
2922 [(set_attr "length" "4")
2923 (set_attr "type" "fsmul")])
2925 ;; Multiplication with addition/subtraction
2926 (define_insn "*muladdsf4"
2927 [(set (match_operand:SF 0 "fpr_operand" "=f")
2928 (plus:SF (mult:SF (match_operand:SF 1 "fpr_operand" "%f")
2929 (match_operand:SF 2 "fpr_operand" "f"))
2930 (match_operand:SF 3 "fpr_operand" "0")))]
2931 "TARGET_HARD_FLOAT && TARGET_MULADD"
2933 [(set_attr "length" "4")
2934 (set_attr "type" "fmas")])
2936 (define_insn "*mulsubsf4"
2937 [(set (match_operand:SF 0 "fpr_operand" "=f")
2938 (minus:SF (mult:SF (match_operand:SF 1 "fpr_operand" "%f")
2939 (match_operand:SF 2 "fpr_operand" "f"))
2940 (match_operand:SF 3 "fpr_operand" "0")))]
2941 "TARGET_HARD_FLOAT && TARGET_MULADD"
2943 [(set_attr "length" "4")
2944 (set_attr "type" "fmas")])
2947 (define_insn "divsf3"
2948 [(set (match_operand:SF 0 "fpr_operand" "=f")
2949 (div:SF (match_operand:SF 1 "fpr_operand" "f")
2950 (match_operand:SF 2 "fpr_operand" "f")))]
2953 [(set_attr "length" "4")
2954 (set_attr "type" "fsdiv")])
2957 (define_insn "negsf2"
2958 [(set (match_operand:SF 0 "fpr_operand" "=f")
2959 (neg:SF (match_operand:SF 1 "fpr_operand" "f")))]
2962 [(set_attr "length" "4")
2963 (set_attr "type" "fsconv")])
2966 (define_insn "abssf2"
2967 [(set (match_operand:SF 0 "fpr_operand" "=f")
2968 (abs:SF (match_operand:SF 1 "fpr_operand" "f")))]
2971 [(set_attr "length" "4")
2972 (set_attr "type" "fsconv")])
2975 (define_insn "sqrtsf2"
2976 [(set (match_operand:SF 0 "fpr_operand" "=f")
2977 (sqrt:SF (match_operand:SF 1 "fpr_operand" "f")))]
2980 [(set_attr "length" "4")
2981 (set_attr "type" "sqrt_single")])
2984 ;; ::::::::::::::::::::
2986 ;; :: 64 bit floating point arithmetic
2988 ;; ::::::::::::::::::::
2991 (define_insn "adddf3"
2992 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
2993 (plus:DF (match_operand:DF 1 "fpr_operand" "%h")
2994 (match_operand:DF 2 "fpr_operand" "h")))]
2995 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
2997 [(set_attr "length" "4")
2998 (set_attr "type" "fdadd")])
3001 (define_insn "subdf3"
3002 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3003 (minus:DF (match_operand:DF 1 "fpr_operand" "h")
3004 (match_operand:DF 2 "fpr_operand" "h")))]
3005 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3007 [(set_attr "length" "4")
3008 (set_attr "type" "fdadd")])
3011 (define_insn "muldf3"
3012 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3013 (mult:DF (match_operand:DF 1 "fpr_operand" "%h")
3014 (match_operand:DF 2 "fpr_operand" "h")))]
3015 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3017 [(set_attr "length" "4")
3018 (set_attr "type" "fdmul")])
3020 ;; Multiplication with addition/subtraction
3021 (define_insn "*muladddf4"
3022 [(set (match_operand:DF 0 "fpr_operand" "=f")
3023 (plus:DF (mult:DF (match_operand:DF 1 "fpr_operand" "%f")
3024 (match_operand:DF 2 "fpr_operand" "f"))
3025 (match_operand:DF 3 "fpr_operand" "0")))]
3026 "TARGET_HARD_FLOAT && TARGET_DOUBLE && TARGET_MULADD"
3028 [(set_attr "length" "4")
3029 (set_attr "type" "fmas")])
3031 (define_insn "*mulsubdf4"
3032 [(set (match_operand:DF 0 "fpr_operand" "=f")
3033 (minus:DF (mult:DF (match_operand:DF 1 "fpr_operand" "%f")
3034 (match_operand:DF 2 "fpr_operand" "f"))
3035 (match_operand:DF 3 "fpr_operand" "0")))]
3036 "TARGET_HARD_FLOAT && TARGET_DOUBLE && TARGET_MULADD"
3038 [(set_attr "length" "4")
3039 (set_attr "type" "fmas")])
3042 (define_insn "divdf3"
3043 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3044 (div:DF (match_operand:DF 1 "fpr_operand" "h")
3045 (match_operand:DF 2 "fpr_operand" "h")))]
3046 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3048 [(set_attr "length" "4")
3049 (set_attr "type" "fddiv")])
3052 (define_insn "negdf2"
3053 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3054 (neg:DF (match_operand:DF 1 "fpr_operand" "h")))]
3055 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3057 [(set_attr "length" "4")
3058 (set_attr "type" "fdconv")])
3061 (define_insn "absdf2"
3062 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3063 (abs:DF (match_operand:DF 1 "fpr_operand" "h")))]
3064 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3066 [(set_attr "length" "4")
3067 (set_attr "type" "fdconv")])
3070 (define_insn "sqrtdf2"
3071 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3072 (sqrt:DF (match_operand:DF 1 "fpr_operand" "h")))]
3073 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3075 [(set_attr "length" "4")
3076 (set_attr "type" "sqrt_double")])
3079 ;; ::::::::::::::::::::
3081 ;; :: 32 bit Integer Shifts and Rotates
3083 ;; ::::::::::::::::::::
3085 ;; Arithmetic Shift Left
3086 (define_insn "ashlsi3"
3087 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
3088 (ashift:SI (match_operand:SI 1 "integer_register_operand" "d,d")
3089 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3092 [(set_attr "length" "4")
3093 (set_attr "type" "int")])
3095 ;; Arithmetic Shift Right
3096 (define_insn "ashrsi3"
3097 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
3098 (ashiftrt:SI (match_operand:SI 1 "integer_register_operand" "d,d")
3099 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3102 [(set_attr "length" "4")
3103 (set_attr "type" "int")])
3105 ;; Logical Shift Right
3106 (define_insn "lshrsi3"
3107 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
3108 (lshiftrt:SI (match_operand:SI 1 "integer_register_operand" "d,d")
3109 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3112 [(set_attr "length" "4")
3113 (set_attr "type" "int")])
3116 ;; (define_insn "rotlsi3"
3117 ;; [(set (match_operand:SI 0 "register_operand" "=r")
3118 ;; (rotate:SI (match_operand:SI 1 "register_operand" "r")
3119 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3121 ;; "rotlsi3 %0,%1,%2"
3122 ;; [(set_attr "length" "4")])
3125 ;; (define_insn "rotrsi3"
3126 ;; [(set (match_operand:SI 0 "register_operand" "=r")
3127 ;; (rotatert:SI (match_operand:SI 1 "register_operand" "r")
3128 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3130 ;; "rotrsi3 %0,%1,%2"
3131 ;; [(set_attr "length" "4")])
3134 ;; ::::::::::::::::::::
3136 ;; :: 64 bit Integer Shifts and Rotates
3138 ;; ::::::::::::::::::::
3140 ;; Arithmetic Shift Left
3141 ;; (define_insn "ashldi3"
3142 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3143 ;; (ashift:DI (match_operand:DI 1 "register_operand" "r")
3144 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3146 ;; "ashldi3 %0,%1,%2"
3147 ;; [(set_attr "length" "4")])
3149 ;; Arithmetic Shift Right
3150 ;; (define_insn "ashrdi3"
3151 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3152 ;; (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
3153 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3155 ;; "ashrdi3 %0,%1,%2"
3156 ;; [(set_attr "length" "4")])
3158 ;; Logical Shift Right
3159 ;; (define_insn "lshrdi3"
3160 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3161 ;; (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
3162 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3164 ;; "lshrdi3 %0,%1,%2"
3165 ;; [(set_attr "length" "4")])
3168 ;; (define_insn "rotldi3"
3169 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3170 ;; (rotate:DI (match_operand:DI 1 "register_operand" "r")
3171 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3173 ;; "rotldi3 %0,%1,%2"
3174 ;; [(set_attr "length" "4")])
3177 ;; (define_insn "rotrdi3"
3178 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3179 ;; (rotatert:DI (match_operand:DI 1 "register_operand" "r")
3180 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3182 ;; "rotrdi3 %0,%1,%2"
3183 ;; [(set_attr "length" "4")])
3186 ;; ::::::::::::::::::::
3188 ;; :: 32 Bit Integer Logical operations
3190 ;; ::::::::::::::::::::
3192 ;; Logical AND, 32 bit integers
3193 (define_insn "andsi3_media"
3194 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3195 (and:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
3196 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "dNOP,f")))]
3201 [(set_attr "length" "4")
3202 (set_attr "type" "int,mlogic")])
3204 (define_insn "andsi3_nomedia"
3205 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3206 (and:SI (match_operand:SI 1 "integer_register_operand" "%d")
3207 (match_operand:SI 2 "gpr_or_int12_operand" "dNOP")))]
3210 [(set_attr "length" "4")
3211 (set_attr "type" "int")])
3213 (define_expand "andsi3"
3214 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3215 (and:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")
3216 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "")))]
3220 ;; Inclusive OR, 32 bit integers
3221 (define_insn "iorsi3_media"
3222 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3223 (ior:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
3224 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "dNOP,f")))]
3229 [(set_attr "length" "4")
3230 (set_attr "type" "int,mlogic")])
3232 (define_insn "iorsi3_nomedia"
3233 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3234 (ior:SI (match_operand:SI 1 "integer_register_operand" "%d")
3235 (match_operand:SI 2 "gpr_or_int12_operand" "dNOP")))]
3238 [(set_attr "length" "4")
3239 (set_attr "type" "int")])
3241 (define_expand "iorsi3"
3242 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3243 (ior:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")
3244 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "")))]
3248 ;; Exclusive OR, 32 bit integers
3249 (define_insn "xorsi3_media"
3250 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3251 (xor:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
3252 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "dNOP,f")))]
3257 [(set_attr "length" "4")
3258 (set_attr "type" "int,mlogic")])
3260 (define_insn "xorsi3_nomedia"
3261 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3262 (xor:SI (match_operand:SI 1 "integer_register_operand" "%d")
3263 (match_operand:SI 2 "gpr_or_int12_operand" "dNOP")))]
3266 [(set_attr "length" "4")
3267 (set_attr "type" "int")])
3269 (define_expand "xorsi3"
3270 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3271 (xor:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")
3272 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "")))]
3276 ;; One's complement, 32 bit integers
3277 (define_insn "one_cmplsi2_media"
3278 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3279 (not:SI (match_operand:SI 1 "gpr_or_fpr_operand" "d,f")))]
3284 [(set_attr "length" "4")
3285 (set_attr "type" "int,mlogic")])
3287 (define_insn "one_cmplsi2_nomedia"
3288 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3289 (not:SI (match_operand:SI 1 "integer_register_operand" "d")))]
3292 [(set_attr "length" "4")
3293 (set_attr "type" "int")])
3295 (define_expand "one_cmplsi2"
3296 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3297 (not:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")))]
3302 ;; ::::::::::::::::::::
3304 ;; :: 64 Bit Integer Logical operations
3306 ;; ::::::::::::::::::::
3308 ;; Logical AND, 64 bit integers
3309 ;; (define_insn "anddi3"
3310 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3311 ;; (and:DI (match_operand:DI 1 "register_operand" "%r")
3312 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3314 ;; "anddi3 %0,%1,%2"
3315 ;; [(set_attr "length" "4")])
3317 ;; Includive OR, 64 bit integers
3318 ;; (define_insn "iordi3"
3319 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3320 ;; (ior:DI (match_operand:DI 1 "register_operand" "%r")
3321 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3323 ;; "iordi3 %0,%1,%2"
3324 ;; [(set_attr "length" "4")])
3326 ;; Excludive OR, 64 bit integers
3327 ;; (define_insn "xordi3"
3328 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3329 ;; (xor:DI (match_operand:DI 1 "register_operand" "%r")
3330 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3332 ;; "xordi3 %0,%1,%2"
3333 ;; [(set_attr "length" "4")])
3335 ;; One's complement, 64 bit integers
3336 ;; (define_insn "one_cmpldi2"
3337 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3338 ;; (not:DI (match_operand:DI 1 "register_operand" "r")))]
3341 ;; [(set_attr "length" "4")])
3344 ;; ::::::::::::::::::::
3346 ;; :: Combination of integer operation with comparison
3348 ;; ::::::::::::::::::::
3350 (define_insn "*combo_intop_compare1"
3351 [(set (match_operand:CC 0 "icc_operand" "=t")
3352 (compare:CC (match_operator:SI 1 "intop_compare_operator"
3353 [(match_operand:SI 2 "integer_register_operand" "d")
3354 (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
3357 "%O1%I3cc %2, %3, %., %0"
3358 [(set_attr "type" "int")
3359 (set_attr "length" "4")])
3361 (define_insn "*combo_intop_compare2"
3362 [(set (match_operand:CC_UNS 0 "icc_operand" "=t")
3363 (compare:CC_UNS (match_operator:SI 1 "intop_compare_operator"
3364 [(match_operand:SI 2 "integer_register_operand" "d")
3365 (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
3368 "%O1%I3cc %2, %3, %., %0"
3369 [(set_attr "type" "int")
3370 (set_attr "length" "4")])
3372 (define_insn "*combo_intop_compare3"
3373 [(set (match_operand:CC 0 "icc_operand" "=t")
3374 (compare:CC (match_operator:SI 1 "intop_compare_operator"
3375 [(match_operand:SI 2 "integer_register_operand" "d")
3376 (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
3378 (set (match_operand:SI 4 "integer_register_operand" "=d")
3379 (match_operator:SI 5 "intop_compare_operator"
3382 "GET_CODE (operands[1]) == GET_CODE (operands[5])"
3383 "%O1%I3cc %2, %3, %4, %0"
3384 [(set_attr "type" "int")
3385 (set_attr "length" "4")])
3387 (define_insn "*combo_intop_compare4"
3388 [(set (match_operand:CC_UNS 0 "icc_operand" "=t")
3389 (compare:CC_UNS (match_operator:SI 1 "intop_compare_operator"
3390 [(match_operand:SI 2 "integer_register_operand" "d")
3391 (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
3393 (set (match_operand:SI 4 "integer_register_operand" "=d")
3394 (match_operator:SI 5 "intop_compare_operator"
3397 "GET_CODE (operands[1]) == GET_CODE (operands[5])"
3398 "%O1%I3cc %2, %3, %4, %0"
3399 [(set_attr "type" "int")
3400 (set_attr "length" "4")])
3403 ;; ::::::::::::::::::::
3407 ;; ::::::::::::::::::::
3409 ;; Note, we store the operands in the comparison insns, and use them later
3410 ;; when generating the branch or scc operation.
3412 ;; First the routines called by the machine independent part of the compiler
3413 (define_expand "cmpsi"
3415 (compare (match_operand:SI 0 "integer_register_operand" "")
3416 (match_operand:SI 1 "gpr_or_int10_operand" "")))]
3420 frv_compare_op0 = operands[0];
3421 frv_compare_op1 = operands[1];
3425 ;(define_expand "cmpdi"
3427 ; (compare (match_operand:DI 0 "register_operand" "")
3428 ; (match_operand:DI 1 "nonmemory_operand" "")))]
3432 ; frv_compare_op0 = operands[0];
3433 ; frv_compare_op1 = operands[1];
3437 (define_expand "cmpsf"
3439 (compare (match_operand:SF 0 "fpr_operand" "")
3440 (match_operand:SF 1 "fpr_operand" "")))]
3444 frv_compare_op0 = operands[0];
3445 frv_compare_op1 = operands[1];
3449 (define_expand "cmpdf"
3451 (compare (match_operand:DF 0 "fpr_operand" "")
3452 (match_operand:DF 1 "fpr_operand" "")))]
3453 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3456 frv_compare_op0 = operands[0];
3457 frv_compare_op1 = operands[1];
3461 ;; Now, the actual comparisons, generated by the branch and/or scc operations
3463 (define_insn "cmpsi_cc"
3464 [(set (match_operand:CC 0 "icc_operand" "=t,t")
3465 (compare:CC (match_operand:SI 1 "integer_register_operand" "d,d")
3466 (match_operand:SI 2 "gpr_or_int10_operand" "d,J")))]
3469 [(set_attr "length" "4")
3470 (set_attr "type" "int")])
3472 (define_insn "*cmpsi_cc_uns"
3473 [(set (match_operand:CC_UNS 0 "icc_operand" "=t,t")
3474 (compare:CC_UNS (match_operand:SI 1 "integer_register_operand" "d,d")
3475 (match_operand:SI 2 "gpr_or_int10_operand" "d,J")))]
3478 [(set_attr "length" "4")
3479 (set_attr "type" "int")])
3481 (define_insn "*cmpsf_cc_fp"
3482 [(set (match_operand:CC_FP 0 "fcc_operand" "=u")
3483 (compare:CC_FP (match_operand:SF 1 "fpr_operand" "f")
3484 (match_operand:SF 2 "fpr_operand" "f")))]
3487 [(set_attr "length" "4")
3488 (set_attr "type" "fsadd")])
3490 (define_insn "*cmpdf_cc_fp"
3491 [(set (match_operand:CC_FP 0 "fcc_operand" "=u")
3492 (compare:CC_FP (match_operand:DF 1 "even_fpr_operand" "h")
3493 (match_operand:DF 2 "even_fpr_operand" "h")))]
3494 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3496 [(set_attr "length" "4")
3497 (set_attr "type" "fdadd")])
3500 ;; ::::::::::::::::::::
3504 ;; ::::::::::::::::::::
3506 ;; Define_expands called by the machine independent part of the compiler
3507 ;; to allocate a new comparison register. Each of these named patterns
3508 ;; must be present, and they cannot be amalgamated into one pattern.
3510 ;; If a fixed condition code register is being used, (as opposed to, say,
3511 ;; using cc0), then the expands should look like this:
3513 ;; (define_expand "<name_of_test>"
3514 ;; [(set (reg:CC <number_of_CC_register>)
3515 ;; (compare:CC (match_dup 1)
3518 ;; (if_then_else (eq:CC (reg:CC <number_of_CC_register>)
3520 ;; (label_ref (match_operand 0 "" ""))
3524 ;; operands[1] = frv_compare_op0;
3525 ;; operands[2] = frv_compare_op1;
3529 (define_expand "beq"
3530 [(use (match_operand 0 "" ""))]
3534 if (! frv_emit_cond_branch (EQ, operands[0]))
3540 (define_expand "bne"
3541 [(use (match_operand 0 "" ""))]
3545 if (! frv_emit_cond_branch (NE, operands[0]))
3551 (define_expand "blt"
3552 [(use (match_operand 0 "" ""))]
3556 if (! frv_emit_cond_branch (LT, operands[0]))
3562 (define_expand "ble"
3563 [(use (match_operand 0 "" ""))]
3567 if (! frv_emit_cond_branch (LE, operands[0]))
3573 (define_expand "bgt"
3574 [(use (match_operand 0 "" ""))]
3578 if (! frv_emit_cond_branch (GT, operands[0]))
3584 (define_expand "bge"
3585 [(use (match_operand 0 "" ""))]
3589 if (! frv_emit_cond_branch (GE, operands[0]))
3595 (define_expand "bltu"
3596 [(use (match_operand 0 "" ""))]
3600 if (! frv_emit_cond_branch (LTU, operands[0]))
3606 (define_expand "bleu"
3607 [(use (match_operand 0 "" ""))]
3611 if (! frv_emit_cond_branch (LEU, operands[0]))
3617 (define_expand "bgtu"
3618 [(use (match_operand 0 "" ""))]
3622 if (! frv_emit_cond_branch (GTU, operands[0]))
3628 (define_expand "bgeu"
3629 [(use (match_operand 0 "" ""))]
3633 if (! frv_emit_cond_branch (GEU, operands[0]))
3639 ;; Actual branches. We must allow for the (label_ref) and the (pc) to be
3640 ;; swapped. If they are swapped, it reverses the sense of the branch.
3642 ;; Note - unlike the define expands above, these patterns can be amalgamated
3643 ;; into one pattern for branch-if-true and one for branch-if-false. This does
3644 ;; require an operand operator to select the correct branch mnemonic.
3646 ;; If a fixed condition code register is being used, (as opposed to, say,
3647 ;; using cc0), then the expands could look like this:
3649 ;; (define_insn "*branch_true"
3651 ;; (if_then_else (match_operator:CC 0 "comparison_operator"
3652 ;; [(reg:CC <number_of_CC_register>)
3654 ;; (label_ref (match_operand 1 "" ""))
3658 ;; [(set_attr "length" "4")]
3661 ;; In the above example the %B is a directive to frv_print_operand()
3662 ;; to decode and print the correct branch mnemonic.
3664 (define_insn "*branch_signed_true"
3666 (if_then_else (match_operator:CC 0 "signed_relational_operator"
3667 [(match_operand 1 "icc_operand" "t")
3669 (label_ref (match_operand 2 "" ""))
3674 if (get_attr_length (insn) == 4)
3675 return \"b%c0 %1,%#,%l2\";
3677 return \"b%C0 %1,%#,1f\;call %l2\\n1:\";
3679 [(set (attr "length")
3681 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
3682 (le (minus (match_dup 2) (pc)) (const_int 32764)))
3685 (set (attr "far_jump")
3687 (eq_attr "length" "4")
3689 (const_string "yes")))
3692 (eq_attr "length" "4")
3693 (const_string "branch")
3694 (const_string "multi")))])
3696 (define_insn "*branch_signed_false"
3698 (if_then_else (match_operator:CC 0 "signed_relational_operator"
3699 [(match_operand 1 "icc_operand" "t")
3702 (label_ref (match_operand 2 "" ""))))]
3706 if (get_attr_length (insn) == 4)
3707 return \"b%C0 %1,%#,%l2\";
3709 return \"b%c0 %1,%#,1f\;call %l2\\n1:\";
3711 [(set (attr "length")
3713 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
3714 (le (minus (match_dup 2) (pc)) (const_int 32764)))
3717 (set (attr "far_jump")
3719 (eq_attr "length" "4")
3721 (const_string "yes")))
3724 (eq_attr "length" "4")
3725 (const_string "branch")
3726 (const_string "multi")))])
3728 (define_insn "*branch_unsigned_true"
3730 (if_then_else (match_operator:CC_UNS 0 "unsigned_relational_operator"
3731 [(match_operand 1 "icc_operand" "t")
3733 (label_ref (match_operand 2 "" ""))
3738 if (get_attr_length (insn) == 4)
3739 return \"b%c0 %1,%#,%l2\";
3741 return \"b%C0 %1,%#,1f\;call %l2\\n1:\";
3743 [(set (attr "length")
3745 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
3746 (le (minus (match_dup 2) (pc)) (const_int 32764)))
3749 (set (attr "far_jump")
3751 (eq_attr "length" "4")
3753 (const_string "yes")))
3756 (eq_attr "length" "4")
3757 (const_string "branch")
3758 (const_string "multi")))])
3760 (define_insn "*branch_unsigned_false"
3762 (if_then_else (match_operator:CC_UNS 0 "unsigned_relational_operator"
3763 [(match_operand 1 "icc_operand" "t")
3766 (label_ref (match_operand 2 "" ""))))]
3770 if (get_attr_length (insn) == 4)
3771 return \"b%C0 %1,%#,%l2\";
3773 return \"b%c0 %1,%#,1f\;call %l2\\n1:\";
3775 [(set (attr "length")
3777 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
3778 (le (minus (match_dup 2) (pc)) (const_int 32764)))
3781 (set (attr "far_jump")
3783 (eq_attr "length" "4")
3785 (const_string "yes")))
3788 (eq_attr "length" "4")
3789 (const_string "branch")
3790 (const_string "multi")))])
3792 (define_insn "*branch_fp_true"
3794 (if_then_else (match_operator:CC_FP 0 "float_relational_operator"
3795 [(match_operand 1 "fcc_operand" "u")
3797 (label_ref (match_operand 2 "" ""))
3802 if (get_attr_length (insn) == 4)
3803 return \"fb%f0 %1,%#,%l2\";
3805 return \"fb%F0 %1,%#,1f\;call %l2\\n1:\";
3807 [(set (attr "length")
3809 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
3810 (le (minus (match_dup 2) (pc)) (const_int 32764)))
3813 (set (attr "far_jump")
3815 (eq_attr "length" "4")
3817 (const_string "yes")))
3820 (eq_attr "length" "4")
3821 (const_string "branch")
3822 (const_string "multi")))])
3824 (define_insn "*branch_fp_false"
3826 (if_then_else (match_operator:CC_FP 0 "float_relational_operator"
3827 [(match_operand 1 "fcc_operand" "u")
3830 (label_ref (match_operand 2 "" ""))))]
3834 if (get_attr_length (insn) == 4)
3835 return \"fb%F0 %1,%#,%l2\";
3837 return \"fb%f0 %1,%#,1f\;call %l2\\n1:\";
3839 [(set (attr "length")
3841 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
3842 (le (minus (match_dup 2) (pc)) (const_int 32764)))
3845 (set (attr "far_jump")
3847 (eq_attr "length" "4")
3849 (const_string "yes")))
3852 (eq_attr "length" "4")
3853 (const_string "branch")
3854 (const_string "multi")))])
3857 ;; ::::::::::::::::::::
3859 ;; :: Set flag operations
3861 ;; ::::::::::::::::::::
3863 ;; Define_expands called by the machine independent part of the compiler
3864 ;; to allocate a new comparison register
3866 (define_expand "seq"
3867 [(match_operand:SI 0 "integer_register_operand" "")]
3871 if (! frv_emit_scc (EQ, operands[0]))
3877 (define_expand "sne"
3878 [(match_operand:SI 0 "integer_register_operand" "")]
3882 if (! frv_emit_scc (NE, operands[0]))
3888 (define_expand "slt"
3889 [(match_operand:SI 0 "integer_register_operand" "")]
3893 if (! frv_emit_scc (LT, operands[0]))
3899 (define_expand "sle"
3900 [(match_operand:SI 0 "integer_register_operand" "")]
3904 if (! frv_emit_scc (LE, operands[0]))
3910 (define_expand "sgt"
3911 [(match_operand:SI 0 "integer_register_operand" "")]
3915 if (! frv_emit_scc (GT, operands[0]))
3921 (define_expand "sge"
3922 [(match_operand:SI 0 "integer_register_operand" "")]
3926 if (! frv_emit_scc (GE, operands[0]))
3932 (define_expand "sltu"
3933 [(match_operand:SI 0 "integer_register_operand" "")]
3937 if (! frv_emit_scc (LTU, operands[0]))
3943 (define_expand "sleu"
3944 [(match_operand:SI 0 "integer_register_operand" "")]
3948 if (! frv_emit_scc (LEU, operands[0]))
3954 (define_expand "sgtu"
3955 [(match_operand:SI 0 "integer_register_operand" "")]
3959 if (! frv_emit_scc (GTU, operands[0]))
3965 (define_expand "sgeu"
3966 [(match_operand:SI 0 "integer_register_operand" "")]
3970 if (! frv_emit_scc (GEU, operands[0]))
3976 (define_insn "*scc_signed"
3977 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3978 (match_operator:SI 1 "signed_relational_operator"
3979 [(match_operand:CC 2 "icc_operand" "t")
3981 (clobber (match_operand:CC_CCR 3 "icr_operand" "=v"))]
3984 [(set_attr "length" "12")
3985 (set_attr "type" "multi")])
3987 (define_insn "*scc_unsigned"
3988 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3989 (match_operator:SI 1 "unsigned_relational_operator"
3990 [(match_operand:CC_UNS 2 "icc_operand" "t")
3992 (clobber (match_operand:CC_CCR 3 "icr_operand" "=v"))]
3995 [(set_attr "length" "12")
3996 (set_attr "type" "multi")])
3998 (define_insn "*scc_float"
3999 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4000 (match_operator:SI 1 "float_relational_operator"
4001 [(match_operand:CC_FP 2 "fcc_operand" "u")
4003 (clobber (match_operand:CC_CCR 3 "fcr_operand" "=w"))]
4006 [(set_attr "length" "12")
4007 (set_attr "type" "multi")])
4009 ;; XXX -- add reload_completed to the splits, because register allocation
4010 ;; currently isn't ready to see cond_exec packets.
4012 [(set (match_operand:SI 0 "integer_register_operand" "")
4013 (match_operator:SI 1 "relational_operator"
4014 [(match_operand 2 "cc_operand" "")
4016 (clobber (match_operand 3 "cr_operand" ""))]
4019 "operands[4] = frv_split_scc (operands[0], operands[1], operands[2],
4020 operands[3], (HOST_WIDE_INT) 1);")
4022 (define_insn "*scc_neg1_signed"
4023 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4024 (neg:SI (match_operator:SI 1 "signed_relational_operator"
4025 [(match_operand:CC 2 "icc_operand" "t")
4027 (clobber (match_operand:CC_CCR 3 "icr_operand" "=v"))]
4030 [(set_attr "length" "12")
4031 (set_attr "type" "multi")])
4033 (define_insn "*scc_neg1_unsigned"
4034 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4035 (neg:SI (match_operator:SI 1 "unsigned_relational_operator"
4036 [(match_operand:CC_UNS 2 "icc_operand" "t")
4038 (clobber (match_operand:CC_CCR 3 "icr_operand" "=v"))]
4041 [(set_attr "length" "12")
4042 (set_attr "type" "multi")])
4044 (define_insn "*scc_neg1_float"
4045 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4046 (neg:SI (match_operator:SI 1 "float_relational_operator"
4047 [(match_operand:CC_FP 2 "fcc_operand" "u")
4049 (clobber (match_operand:CC_CCR 3 "fcr_operand" "=w"))]
4052 [(set_attr "length" "12")
4053 (set_attr "type" "multi")])
4056 [(set (match_operand:SI 0 "integer_register_operand" "")
4057 (neg:SI (match_operator:SI 1 "relational_operator"
4058 [(match_operand 2 "cc_operand" "")
4060 (clobber (match_operand 3 "cr_operand" ""))]
4063 "operands[4] = frv_split_scc (operands[0], operands[1], operands[2],
4064 operands[3], (HOST_WIDE_INT) -1);")
4067 ;; ::::::::::::::::::::
4069 ;; :: Conditionally executed instructions
4071 ;; ::::::::::::::::::::
4073 ;; Convert ICC/FCC comparison into CCR bits so we can do conditional execution
4074 (define_insn "*ck_signed"
4075 [(set (match_operand:CC_CCR 0 "icr_operand" "=v")
4076 (match_operator:CC_CCR 1 "signed_relational_operator"
4077 [(match_operand:CC 2 "icc_operand" "t")
4081 [(set_attr "length" "4")
4082 (set_attr "type" "ccr")])
4084 (define_insn "*ck_unsigned"
4085 [(set (match_operand:CC_CCR 0 "icr_operand" "=v")
4086 (match_operator:CC_CCR 1 "unsigned_relational_operator"
4087 [(match_operand:CC_UNS 2 "icc_operand" "t")
4091 [(set_attr "length" "4")
4092 (set_attr "type" "ccr")])
4094 (define_insn "*fck_float"
4095 [(set (match_operand:CC_CCR 0 "fcr_operand" "=w")
4096 (match_operator:CC_CCR 1 "float_relational_operator"
4097 [(match_operand:CC_FP 2 "fcc_operand" "u")
4101 [(set_attr "length" "4")
4102 (set_attr "type" "ccr")])
4104 ;; Conditionally convert ICC/FCC comparison into CCR bits to provide && and ||
4105 ;; tests in conditional execution
4106 (define_insn "cond_exec_ck"
4107 [(set (match_operand:CC_CCR 0 "cr_operand" "=v,w")
4108 (if_then_else:CC_CCR (match_operator 1 "ccr_eqne_operator"
4109 [(match_operand 2 "cr_operand" "C,C")
4111 (match_operator 3 "relational_operator"
4112 [(match_operand 4 "cc_operand" "t,u")
4117 cck%c3 %4, %0, %2, %e1
4118 cfck%f3 %4, %0, %2, %e1"
4119 [(set_attr "length" "4")
4120 (set_attr "type" "ccr")])
4122 ;; Conditionally set a register to either 0 or another register
4123 (define_insn "*cond_exec_movqi"
4125 (match_operator 0 "ccr_eqne_operator"
4126 [(match_operand 1 "cr_operand" "C,C,C,C,C,C")
4128 (set (match_operand:QI 2 "condexec_dest_operand" "=d,d,U,?f,?f,?d")
4129 (match_operand:QI 3 "condexec_source_operand" "dO,U,dO,f,d,f")))]
4130 "register_operand(operands[2], QImode) || reg_or_0_operand (operands[3], QImode)"
4131 "* return output_condmove_single (operands, insn);"
4132 [(set_attr "length" "4")
4133 (set_attr "type" "int,gload,gstore,fsconv,movgf,movfg")])
4135 (define_insn "*cond_exec_movhi"
4137 (match_operator 0 "ccr_eqne_operator"
4138 [(match_operand 1 "cr_operand" "C,C,C,C,C,C")
4140 (set (match_operand:HI 2 "condexec_dest_operand" "=d,d,U,?f,?f,?d")
4141 (match_operand:HI 3 "condexec_source_operand" "dO,U,dO,f,d,f")))]
4142 "register_operand(operands[2], HImode) || reg_or_0_operand (operands[3], HImode)"
4143 "* return output_condmove_single (operands, insn);"
4144 [(set_attr "length" "4")
4145 (set_attr "type" "int,gload,gstore,fsconv,movgf,movfg")])
4147 (define_insn "*cond_exec_movsi"
4149 (match_operator 0 "ccr_eqne_operator"
4150 [(match_operand 1 "cr_operand" "C,C,C,C,C,C,C,C")
4152 (set (match_operand:SI 2 "condexec_dest_operand" "=d,d,U,?f,?f,?d,?f,?m")
4153 (match_operand:SI 3 "condexec_source_operand" "dO,U,dO,f,d,f,m,f")))]
4154 "register_operand(operands[2], SImode) || reg_or_0_operand (operands[3], SImode)"
4155 "* return output_condmove_single (operands, insn);"
4156 [(set_attr "length" "4")
4157 (set_attr "type" "int,gload,gstore,fsconv,movgf,movfg,fload,fstore")])
4160 (define_insn "*cond_exec_movsf_has_fprs"
4162 (match_operator 0 "ccr_eqne_operator"
4163 [(match_operand 1 "cr_operand" "C,C,C,C,C,C,C,C,C,C")
4165 (set (match_operand:SF 2 "condexec_dest_operand" "=f,?d,?d,?f,f,f,?d,U,?U,U")
4166 (match_operand:SF 3 "condexec_source_operand" "f,d,f,d,G,U,U,f,d,G")))]
4168 "* return output_condmove_single (operands, insn);"
4169 [(set_attr "length" "4")
4170 (set_attr "type" "fsconv,int,movgf,movfg,movgf,fload,gload,fstore,gstore,gstore")])
4172 (define_insn "*cond_exec_movsf_no_fprs"
4174 (match_operator 0 "ccr_eqne_operator"
4175 [(match_operand 1 "cr_operand" "C,C,C")
4177 (set (match_operand:SF 2 "condexec_dest_operand" "=d,d,U")
4178 (match_operand:SF 3 "condexec_source_operand" "d,U,dG")))]
4180 "* return output_condmove_single (operands, insn);"
4181 [(set_attr "length" "4")
4182 (set_attr "type" "int,gload,gstore")])
4184 (define_insn "*cond_exec_si_binary1"
4186 (match_operator 0 "ccr_eqne_operator"
4187 [(match_operand 1 "cr_operand" "C")
4189 (set (match_operand:SI 2 "integer_register_operand" "=d")
4190 (match_operator:SI 3 "condexec_si_binary_operator"
4191 [(match_operand:SI 4 "integer_register_operand" "d")
4192 (match_operand:SI 5 "integer_register_operand" "d")])))]
4196 switch (GET_CODE (operands[3]))
4198 case PLUS: return \"cadd %4, %z5, %2, %1, %e0\";
4199 case MINUS: return \"csub %4, %z5, %2, %1, %e0\";
4200 case AND: return \"cand %4, %z5, %2, %1, %e0\";
4201 case IOR: return \"cor %4, %z5, %2, %1, %e0\";
4202 case XOR: return \"cxor %4, %z5, %2, %1, %e0\";
4203 case ASHIFT: return \"csll %4, %z5, %2, %1, %e0\";
4204 case ASHIFTRT: return \"csra %4, %z5, %2, %1, %e0\";
4205 case LSHIFTRT: return \"csrl %4, %z5, %2, %1, %e0\";
4209 [(set_attr "length" "4")
4210 (set_attr "type" "int")])
4212 (define_insn "*cond_exec_si_binary2"
4214 (match_operator 0 "ccr_eqne_operator"
4215 [(match_operand 1 "cr_operand" "C")
4217 (set (match_operand:SI 2 "fpr_operand" "=f")
4218 (match_operator:SI 3 "condexec_si_media_operator"
4219 [(match_operand:SI 4 "fpr_operand" "f")
4220 (match_operand:SI 5 "fpr_operand" "f")])))]
4224 switch (GET_CODE (operands[3]))
4226 case AND: return \"cmand %4, %5, %2, %1, %e0\";
4227 case IOR: return \"cmor %4, %5, %2, %1, %e0\";
4228 case XOR: return \"cmxor %4, %5, %2, %1, %e0\";
4232 [(set_attr "length" "4")
4233 (set_attr "type" "mlogic")])
4235 ;; Note, flow does not (currently) know how to handle an operation that uses
4236 ;; only part of the hard registers allocated for a multiregister value, such as
4237 ;; DImode in this case if the user is only interested in the lower 32-bits. So
4238 ;; we emit a USE of the entire register after the csmul instruction so it won't
4239 ;; get confused. See frv_ifcvt_modify_insn for more details.
4241 (define_insn "*cond_exec_si_smul"
4243 (match_operator 0 "ccr_eqne_operator"
4244 [(match_operand 1 "cr_operand" "C")
4246 (set (match_operand:DI 2 "even_gpr_operand" "=e")
4247 (mult:DI (sign_extend:DI (match_operand:SI 3 "integer_register_operand" "%d"))
4248 (sign_extend:DI (match_operand:SI 4 "integer_register_operand" "d")))))]
4250 "csmul %3, %4, %2, %1, %e0"
4251 [(set_attr "length" "4")
4252 (set_attr "type" "mul")])
4254 (define_insn "*cond_exec_si_divide"
4256 (match_operator 0 "ccr_eqne_operator"
4257 [(match_operand 1 "cr_operand" "C")
4259 (set (match_operand:SI 2 "integer_register_operand" "=d")
4260 (match_operator:SI 3 "condexec_si_divide_operator"
4261 [(match_operand:SI 4 "integer_register_operand" "d")
4262 (match_operand:SI 5 "integer_register_operand" "d")])))]
4266 switch (GET_CODE (operands[3]))
4268 case DIV: return \"csdiv %4, %z5, %2, %1, %e0\";
4269 case UDIV: return \"cudiv %4, %z5, %2, %1, %e0\";
4273 [(set_attr "length" "4")
4274 (set_attr "type" "div")])
4276 (define_insn "*cond_exec_si_unary1"
4278 (match_operator 0 "ccr_eqne_operator"
4279 [(match_operand 1 "cr_operand" "C")
4281 (set (match_operand:SI 2 "integer_register_operand" "=d")
4282 (match_operator:SI 3 "condexec_si_unary_operator"
4283 [(match_operand:SI 4 "integer_register_operand" "d")])))]
4287 switch (GET_CODE (operands[3]))
4289 case NOT: return \"cnot %4, %2, %1, %e0\";
4290 case NEG: return \"csub %., %4, %2, %1, %e0\";
4294 [(set_attr "length" "4")
4295 (set_attr "type" "int")])
4297 (define_insn "*cond_exec_si_unary2"
4299 (match_operator 0 "ccr_eqne_operator"
4300 [(match_operand 1 "cr_operand" "C")
4302 (set (match_operand:SI 2 "fpr_operand" "=f")
4303 (not:SI (match_operand:SI 3 "fpr_operand" "f"))))]
4305 "cmnot %3, %2, %1, %e0"
4306 [(set_attr "length" "4")
4307 (set_attr "type" "mlogic")])
4309 (define_insn "*cond_exec_cmpsi_cc"
4311 (match_operator 0 "ccr_eqne_operator"
4312 [(match_operand 1 "cr_operand" "C")
4314 (set (match_operand:CC 2 "icc_operand" "=t")
4315 (compare:CC (match_operand:SI 3 "integer_register_operand" "d")
4316 (match_operand:SI 4 "reg_or_0_operand" "dO"))))]
4318 && REGNO (operands[1]) == REGNO (operands[2]) - ICC_FIRST + ICR_FIRST"
4319 "ccmp %3, %z4, %1, %e0"
4320 [(set_attr "length" "4")
4321 (set_attr "type" "int")])
4323 (define_insn "*cond_exec_cmpsi_cc_uns"
4325 (match_operator 0 "ccr_eqne_operator"
4326 [(match_operand 1 "cr_operand" "C")
4328 (set (match_operand:CC_UNS 2 "icc_operand" "=t")
4329 (compare:CC_UNS (match_operand:SI 3 "integer_register_operand" "d")
4330 (match_operand:SI 4 "reg_or_0_operand" "dO"))))]
4332 && REGNO (operands[1]) == REGNO (operands[2]) - ICC_FIRST + ICR_FIRST"
4333 "ccmp %3, %z4, %1, %e0"
4334 [(set_attr "length" "4")
4335 (set_attr "type" "int")])
4337 (define_insn "*cond_exec_sf_conv"
4339 (match_operator 0 "ccr_eqne_operator"
4340 [(match_operand 1 "cr_operand" "C")
4342 (set (match_operand:SF 2 "fpr_operand" "=f")
4343 (match_operator:SF 3 "condexec_sf_conv_operator"
4344 [(match_operand:SF 4 "fpr_operand" "f")])))]
4348 switch (GET_CODE (operands[3]))
4350 case ABS: return \"cfabss %4, %2, %1, %e0\";
4351 case NEG: return \"cfnegs %4, %2, %1, %e0\";
4355 [(set_attr "length" "4")
4356 (set_attr "type" "fsconv")])
4358 (define_insn "*cond_exec_sf_add"
4360 (match_operator 0 "ccr_eqne_operator"
4361 [(match_operand 1 "cr_operand" "C")
4363 (set (match_operand:SF 2 "fpr_operand" "=f")
4364 (match_operator:SF 3 "condexec_sf_add_operator"
4365 [(match_operand:SF 4 "fpr_operand" "f")
4366 (match_operand:SF 5 "fpr_operand" "f")])))]
4370 switch (GET_CODE (operands[3]))
4372 case PLUS: return \"cfadds %4, %5, %2, %1, %e0\";
4373 case MINUS: return \"cfsubs %4, %5, %2, %1, %e0\";
4377 [(set_attr "length" "4")
4378 (set_attr "type" "fsadd")])
4380 (define_insn "*cond_exec_sf_mul"
4382 (match_operator 0 "ccr_eqne_operator"
4383 [(match_operand 1 "cr_operand" "C")
4385 (set (match_operand:SF 2 "fpr_operand" "=f")
4386 (mult:SF (match_operand:SF 3 "fpr_operand" "f")
4387 (match_operand:SF 4 "fpr_operand" "f"))))]
4389 "cfmuls %3, %4, %2, %1, %e0"
4390 [(set_attr "length" "4")
4391 (set_attr "type" "fsmul")])
4393 (define_insn "*cond_exec_sf_div"
4395 (match_operator 0 "ccr_eqne_operator"
4396 [(match_operand 1 "cr_operand" "C")
4398 (set (match_operand:SF 2 "fpr_operand" "=f")
4399 (div:SF (match_operand:SF 3 "fpr_operand" "f")
4400 (match_operand:SF 4 "fpr_operand" "f"))))]
4402 "cfdivs %3, %4, %2, %1, %e0"
4403 [(set_attr "length" "4")
4404 (set_attr "type" "fsdiv")])
4406 (define_insn "*cond_exec_sf_sqrt"
4408 (match_operator 0 "ccr_eqne_operator"
4409 [(match_operand 1 "cr_operand" "C")
4411 (set (match_operand:SF 2 "fpr_operand" "=f")
4412 (sqrt:SF (match_operand:SF 3 "fpr_operand" "f"))))]
4414 "cfsqrts %3, %2, %1, %e0"
4415 [(set_attr "length" "4")
4416 (set_attr "type" "fsdiv")])
4418 (define_insn "*cond_exec_cmpsi_cc_fp"
4420 (match_operator 0 "ccr_eqne_operator"
4421 [(match_operand 1 "cr_operand" "C")
4423 (set (match_operand:CC_FP 2 "fcc_operand" "=u")
4424 (compare:CC_FP (match_operand:SF 3 "fpr_operand" "f")
4425 (match_operand:SF 4 "fpr_operand" "f"))))]
4426 "reload_completed && TARGET_HARD_FLOAT
4427 && REGNO (operands[1]) == REGNO (operands[2]) - FCC_FIRST + FCR_FIRST"
4428 "cfcmps %3, %4, %2, %1, %e0"
4429 [(set_attr "length" "4")
4430 (set_attr "type" "fsconv")])
4433 ;; ::::::::::::::::::::
4435 ;; :: Logical operations on CR registers
4437 ;; ::::::::::::::::::::
4439 ;; We use UNSPEC to encode andcr/iorcr/etc. rather than the normal RTL
4440 ;; operations, since the RTL operations only have an idea of TRUE and FALSE,
4441 ;; while the CRs have TRUE, FALSE, and UNDEFINED.
4443 (define_expand "andcr"
4444 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4445 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4446 (match_operand:CC_CCR 2 "cr_operand" "")
4447 (const_int 0)] UNSPEC_CR_LOGIC))]
4451 (define_expand "orcr"
4452 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4453 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4454 (match_operand:CC_CCR 2 "cr_operand" "")
4455 (const_int 1)] UNSPEC_CR_LOGIC))]
4459 (define_expand "xorcr"
4460 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4461 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4462 (match_operand:CC_CCR 2 "cr_operand" "")
4463 (const_int 2)] UNSPEC_CR_LOGIC))]
4467 (define_expand "nandcr"
4468 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4469 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4470 (match_operand:CC_CCR 2 "cr_operand" "")
4471 (const_int 3)] UNSPEC_CR_LOGIC))]
4475 (define_expand "norcr"
4476 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4477 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4478 (match_operand:CC_CCR 2 "cr_operand" "")
4479 (const_int 4)] UNSPEC_CR_LOGIC))]
4483 (define_expand "andncr"
4484 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4485 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4486 (match_operand:CC_CCR 2 "cr_operand" "")
4487 (const_int 5)] UNSPEC_CR_LOGIC))]
4491 (define_expand "orncr"
4492 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4493 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4494 (match_operand:CC_CCR 2 "cr_operand" "")
4495 (const_int 6)] UNSPEC_CR_LOGIC))]
4499 (define_expand "nandncr"
4500 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4501 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4502 (match_operand:CC_CCR 2 "cr_operand" "")
4503 (const_int 7)] UNSPEC_CR_LOGIC))]
4507 (define_expand "norncr"
4508 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4509 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4510 (match_operand:CC_CCR 2 "cr_operand" "")
4511 (const_int 8)] UNSPEC_CR_LOGIC))]
4515 (define_expand "notcr"
4516 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4517 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4519 (const_int 9)] UNSPEC_CR_LOGIC))]
4523 (define_insn "*logical_cr"
4524 [(set (match_operand:CC_CCR 0 "cr_operand" "=C")
4525 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "C")
4526 (match_operand:CC_CCR 2 "cr_operand" "C")
4527 (match_operand:SI 3 "const_int_operand" "n")]
4532 switch (INTVAL (operands[3]))
4535 case 0: return \"andcr %1, %2, %0\";
4536 case 1: return \"orcr %1, %2, %0\";
4537 case 2: return \"xorcr %1, %2, %0\";
4538 case 3: return \"nandcr %1, %2, %0\";
4539 case 4: return \"norcr %1, %2, %0\";
4540 case 5: return \"andncr %1, %2, %0\";
4541 case 6: return \"orncr %1, %2, %0\";
4542 case 7: return \"nandncr %1, %2, %0\";
4543 case 8: return \"norncr %1, %2, %0\";
4544 case 9: return \"notcr %1, %0\";
4547 fatal_insn (\"logical_cr\", insn);
4549 [(set_attr "length" "4")
4550 (set_attr "type" "ccr")])
4553 ;; ::::::::::::::::::::
4555 ;; :: Conditional move instructions
4557 ;; ::::::::::::::::::::
4560 ;; - conditional moves based on floating-point comparisons require
4561 ;; TARGET_HARD_FLOAT, because an FPU is required to do the comparison.
4563 ;; - conditional moves between FPRs based on integer comparisons
4564 ;; require TARGET_HAS_FPRS.
4566 (define_expand "movqicc"
4567 [(set (match_operand:QI 0 "integer_register_operand" "")
4568 (if_then_else:QI (match_operand 1 "" "")
4569 (match_operand:QI 2 "gpr_or_int_operand" "")
4570 (match_operand:QI 3 "gpr_or_int_operand" "")))]
4574 if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
4580 (define_insn "*movqicc_internal1_signed"
4581 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d")
4582 (if_then_else:QI (match_operator:CC 1 "signed_relational_operator"
4583 [(match_operand:CC 2 "icc_operand" "t,t,t")
4585 (match_operand:QI 3 "reg_or_0_operand" "0,dO,dO")
4586 (match_operand:QI 4 "reg_or_0_operand" "dO,0,dO")))
4587 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4590 [(set_attr "length" "8,8,12")
4591 (set_attr "type" "multi")])
4593 (define_insn "*movqicc_internal1_unsigned"
4594 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d")
4595 (if_then_else:QI (match_operator:CC_UNS 1 "unsigned_relational_operator"
4596 [(match_operand:CC_UNS 2 "icc_operand" "t,t,t")
4598 (match_operand:QI 3 "reg_or_0_operand" "0,dO,dO")
4599 (match_operand:QI 4 "reg_or_0_operand" "dO,0,dO")))
4600 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4603 [(set_attr "length" "8,8,12")
4604 (set_attr "type" "multi")])
4606 (define_insn "*movqicc_internal1_float"
4607 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d")
4608 (if_then_else:QI (match_operator:CC_FP 1 "float_relational_operator"
4609 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u")
4611 (match_operand:QI 3 "reg_or_0_operand" "0,dO,dO")
4612 (match_operand:QI 4 "reg_or_0_operand" "dO,0,dO")))
4613 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
4616 [(set_attr "length" "8,8,12")
4617 (set_attr "type" "multi")])
4619 (define_insn "*movqicc_internal2_signed"
4620 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d,d,d")
4621 (if_then_else:QI (match_operator:CC 1 "signed_relational_operator"
4622 [(match_operand:CC 2 "icc_operand" "t,t,t,t,t")
4624 (match_operand:QI 3 "const_int_operand" "O,O,L,n,n")
4625 (match_operand:QI 4 "const_int_operand" "L,n,O,O,n")))
4626 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4627 "(INTVAL (operands[3]) == 0
4628 || INTVAL (operands[4]) == 0
4629 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4630 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4632 [(set_attr "length" "8,12,8,12,12")
4633 (set_attr "type" "multi")])
4635 (define_insn "*movqicc_internal2_unsigned"
4636 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d,d,d")
4637 (if_then_else:QI (match_operator:CC_UNS 1 "unsigned_relational_operator"
4638 [(match_operand:CC_UNS 2 "icc_operand" "t,t,t,t,t")
4640 (match_operand:QI 3 "const_int_operand" "O,O,L,n,n")
4641 (match_operand:QI 4 "const_int_operand" "L,n,O,O,n")))
4642 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4643 "(INTVAL (operands[3]) == 0
4644 || INTVAL (operands[4]) == 0
4645 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4646 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4648 [(set_attr "length" "8,12,8,12,12")
4649 (set_attr "type" "multi")])
4651 (define_insn "*movqicc_internal2_float"
4652 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d,d,d")
4653 (if_then_else:QI (match_operator:CC_FP 1 "float_relational_operator"
4654 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u")
4656 (match_operand:QI 3 "const_int_operand" "O,O,L,n,n")
4657 (match_operand:QI 4 "const_int_operand" "L,n,O,O,n")))
4658 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))]
4660 && (INTVAL (operands[3]) == 0
4661 || INTVAL (operands[4]) == 0
4662 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4663 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4665 [(set_attr "length" "8,12,8,12,12")
4666 (set_attr "type" "multi")])
4669 [(set (match_operand:QI 0 "integer_register_operand" "")
4670 (if_then_else:QI (match_operator 1 "relational_operator"
4671 [(match_operand 2 "cc_operand" "")
4673 (match_operand:QI 3 "gpr_or_int_operand" "")
4674 (match_operand:QI 4 "gpr_or_int_operand" "")))
4675 (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
4678 "operands[6] = frv_split_cond_move (operands);")
4680 (define_expand "movhicc"
4681 [(set (match_operand:HI 0 "integer_register_operand" "")
4682 (if_then_else:HI (match_operand 1 "" "")
4683 (match_operand:HI 2 "gpr_or_int_operand" "")
4684 (match_operand:HI 3 "gpr_or_int_operand" "")))]
4688 if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
4694 (define_insn "*movhicc_internal1_signed"
4695 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
4696 (if_then_else:HI (match_operator:CC 1 "signed_relational_operator"
4697 [(match_operand:CC 2 "icc_operand" "t,t,t")
4699 (match_operand:HI 3 "reg_or_0_operand" "0,dO,dO")
4700 (match_operand:HI 4 "reg_or_0_operand" "dO,0,dO")))
4701 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4704 [(set_attr "length" "8,8,12")
4705 (set_attr "type" "multi")])
4707 (define_insn "*movhicc_internal1_unsigned"
4708 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
4709 (if_then_else:HI (match_operator:CC_UNS 1 "unsigned_relational_operator"
4710 [(match_operand:CC_UNS 2 "icc_operand" "t,t,t")
4712 (match_operand:HI 3 "reg_or_0_operand" "0,dO,dO")
4713 (match_operand:HI 4 "reg_or_0_operand" "dO,0,dO")))
4714 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4717 [(set_attr "length" "8,8,12")
4718 (set_attr "type" "multi")])
4720 (define_insn "*movhicc_internal1_float"
4721 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
4722 (if_then_else:HI (match_operator:CC_FP 1 "float_relational_operator"
4723 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u")
4725 (match_operand:HI 3 "reg_or_0_operand" "0,dO,dO")
4726 (match_operand:HI 4 "reg_or_0_operand" "dO,0,dO")))
4727 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
4730 [(set_attr "length" "8,8,12")
4731 (set_attr "type" "multi")])
4733 (define_insn "*movhicc_internal2_signed"
4734 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d,d,d")
4735 (if_then_else:HI (match_operator:CC 1 "signed_relational_operator"
4736 [(match_operand:CC 2 "icc_operand" "t,t,t,t,t")
4738 (match_operand:HI 3 "const_int_operand" "O,O,L,n,n")
4739 (match_operand:HI 4 "const_int_operand" "L,n,O,O,n")))
4740 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4741 "(INTVAL (operands[3]) == 0
4742 || INTVAL (operands[4]) == 0
4743 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4744 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4746 [(set_attr "length" "8,12,8,12,12")
4747 (set_attr "type" "multi")])
4749 (define_insn "*movhicc_internal2_unsigned"
4750 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d,d,d")
4751 (if_then_else:HI (match_operator:CC_UNS 1 "unsigned_relational_operator"
4752 [(match_operand:CC_UNS 2 "icc_operand" "t,t,t,t,t")
4754 (match_operand:HI 3 "const_int_operand" "O,O,L,n,n")
4755 (match_operand:HI 4 "const_int_operand" "L,n,O,O,n")))
4756 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4757 "(INTVAL (operands[3]) == 0
4758 || INTVAL (operands[4]) == 0
4759 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4760 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4762 [(set_attr "length" "8,12,8,12,12")
4763 (set_attr "type" "multi")])
4765 (define_insn "*movhicc_internal2_float"
4766 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d,d,d")
4767 (if_then_else:HI (match_operator:CC_FP 1 "float_relational_operator"
4768 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u")
4770 (match_operand:HI 3 "const_int_operand" "O,O,L,n,n")
4771 (match_operand:HI 4 "const_int_operand" "L,n,O,O,n")))
4772 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))]
4774 && (INTVAL (operands[3]) == 0
4775 || INTVAL (operands[4]) == 0
4776 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4777 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4779 [(set_attr "length" "8,12,8,12,12")
4780 (set_attr "type" "multi")])
4783 [(set (match_operand:HI 0 "integer_register_operand" "")
4784 (if_then_else:HI (match_operator 1 "relational_operator"
4785 [(match_operand 2 "cc_operand" "")
4787 (match_operand:HI 3 "gpr_or_int_operand" "")
4788 (match_operand:HI 4 "gpr_or_int_operand" "")))
4789 (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
4792 "operands[6] = frv_split_cond_move (operands);")
4794 (define_expand "movsicc"
4795 [(set (match_operand:SI 0 "integer_register_operand" "")
4796 (if_then_else:SI (match_operand 1 "" "")
4797 (match_operand:SI 2 "gpr_or_int_operand" "")
4798 (match_operand:SI 3 "gpr_or_int_operand" "")))]
4802 if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
4808 (define_insn "*movsicc_internal1_signed"
4809 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
4810 (if_then_else:SI (match_operator:CC 1 "signed_relational_operator"
4811 [(match_operand:CC 2 "icc_operand" "t,t,t")
4813 (match_operand:SI 3 "reg_or_0_operand" "0,dO,dO")
4814 (match_operand:SI 4 "reg_or_0_operand" "dO,0,dO")))
4815 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4818 [(set_attr "length" "8,8,12")
4819 (set_attr "type" "multi")])
4821 (define_insn "*movsicc_internal1_unsigned"
4822 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
4823 (if_then_else:SI (match_operator:CC_UNS 1 "unsigned_relational_operator"
4824 [(match_operand:CC_UNS 2 "icc_operand" "t,t,t")
4826 (match_operand:SI 3 "reg_or_0_operand" "0,dO,dO")
4827 (match_operand:SI 4 "reg_or_0_operand" "dO,0,dO")))
4828 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4831 [(set_attr "length" "8,8,12")
4832 (set_attr "type" "multi")])
4834 (define_insn "*movsicc_internal1_float"
4835 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
4836 (if_then_else:SI (match_operator:CC_FP 1 "float_relational_operator"
4837 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u")
4839 (match_operand:SI 3 "reg_or_0_operand" "0,dO,dO")
4840 (match_operand:SI 4 "reg_or_0_operand" "dO,0,dO")))
4841 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
4844 [(set_attr "length" "8,8,12")
4845 (set_attr "type" "multi")])
4847 (define_insn "*movsicc_internal2_signed"
4848 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d,d,d")
4849 (if_then_else:SI (match_operator:CC 1 "signed_relational_operator"
4850 [(match_operand:CC 2 "icc_operand" "t,t,t,t,t")
4852 (match_operand:SI 3 "const_int_operand" "O,O,L,n,n")
4853 (match_operand:SI 4 "const_int_operand" "L,n,O,O,n")))
4854 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4855 "(INTVAL (operands[3]) == 0
4856 || INTVAL (operands[4]) == 0
4857 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4858 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4860 [(set_attr "length" "8,12,8,12,12")
4861 (set_attr "type" "multi")])
4863 (define_insn "*movsicc_internal2_unsigned"
4864 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d,d,d")
4865 (if_then_else:SI (match_operator:CC_UNS 1 "unsigned_relational_operator"
4866 [(match_operand:CC_UNS 2 "icc_operand" "t,t,t,t,t")
4868 (match_operand:SI 3 "const_int_operand" "O,O,L,n,n")
4869 (match_operand:SI 4 "const_int_operand" "L,n,O,O,n")))
4870 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4871 "(INTVAL (operands[3]) == 0
4872 || INTVAL (operands[4]) == 0
4873 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4874 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4876 [(set_attr "length" "8,12,8,12,12")
4877 (set_attr "type" "multi")])
4879 (define_insn "*movsicc_internal2_float"
4880 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d,d,d")
4881 (if_then_else:SI (match_operator:CC_FP 1 "float_relational_operator"
4882 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u")
4884 (match_operand:SI 3 "const_int_operand" "O,O,L,n,n")
4885 (match_operand:SI 4 "const_int_operand" "L,n,O,O,n")))
4886 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))]
4888 && (INTVAL (operands[3]) == 0
4889 || INTVAL (operands[4]) == 0
4890 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4891 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4893 [(set_attr "length" "8,12,8,12,12")
4894 (set_attr "type" "multi")])
4897 [(set (match_operand:SI 0 "integer_register_operand" "")
4898 (if_then_else:SI (match_operator 1 "relational_operator"
4899 [(match_operand 2 "cc_operand" "")
4901 (match_operand:SI 3 "gpr_or_int_operand" "")
4902 (match_operand:SI 4 "gpr_or_int_operand" "")))
4903 (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
4906 "operands[6] = frv_split_cond_move (operands);")
4908 (define_expand "movsfcc"
4909 [(set (match_operand:SF 0 "register_operand" "")
4910 (if_then_else:SF (match_operand 1 "" "")
4911 (match_operand:SF 2 "register_operand" "")
4912 (match_operand:SF 3 "register_operand" "")))]
4916 if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
4922 (define_insn "*movsfcc_has_fprs_signed"
4923 [(set (match_operand:SF 0 "register_operand" "=f,f,f,?f,?f,?d")
4924 (if_then_else:SF (match_operator:CC 1 "signed_relational_operator"
4925 [(match_operand:CC 2 "icc_operand" "t,t,t,t,t,t")
4927 (match_operand:SF 3 "register_operand" "0,f,f,f,d,fd")
4928 (match_operand:SF 4 "register_operand" "f,0,f,d,fd,fd")))
4929 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v,v"))]
4932 [(set_attr "length" "8,8,12,12,12,12")
4933 (set_attr "type" "multi")])
4935 (define_insn "*movsfcc_has_fprs_unsigned"
4936 [(set (match_operand:SF 0 "register_operand" "=f,f,f,?f,?f,?d")
4937 (if_then_else:SF (match_operator:CC_UNS 1 "unsigned_relational_operator"
4938 [(match_operand:CC_UNS 2 "icc_operand" "t,t,t,t,t,t")
4940 (match_operand:SF 3 "register_operand" "0,f,f,f,d,fd")
4941 (match_operand:SF 4 "register_operand" "f,0,f,d,fd,fd")))
4942 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v,v"))]
4945 [(set_attr "length" "8,8,12,12,12,12")
4946 (set_attr "type" "multi")])
4948 (define_insn "*movsfcc_hardfloat_float"
4949 [(set (match_operand:SF 0 "register_operand" "=f,f,f,?f,?f,?d")
4950 (if_then_else:SF (match_operator:CC_FP 1 "float_relational_operator"
4951 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u,u")
4953 (match_operand:SF 3 "register_operand" "0,f,f,f,d,fd")
4954 (match_operand:SF 4 "register_operand" "f,0,f,d,fd,fd")))
4955 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w,w"))]
4958 [(set_attr "length" "8,8,12,12,12,12")
4959 (set_attr "type" "multi")])
4961 (define_insn "*movsfcc_no_fprs_signed"
4962 [(set (match_operand:SF 0 "integer_register_operand" "=d,d,d")
4963 (if_then_else:SF (match_operator:CC 1 "signed_relational_operator"
4964 [(match_operand:CC 2 "icc_operand" "t,t,t")
4966 (match_operand:SF 3 "integer_register_operand" "0,d,d")
4967 (match_operand:SF 4 "integer_register_operand" "d,0,d")))
4968 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4971 [(set_attr "length" "8,8,12")
4972 (set_attr "type" "multi")])
4974 (define_insn "*movsfcc_no_fprs_unsigned"
4975 [(set (match_operand:SF 0 "integer_register_operand" "=d,d,d")
4976 (if_then_else:SF (match_operator:CC_UNS 1 "unsigned_relational_operator"
4977 [(match_operand:CC_UNS 2 "icc_operand" "t,t,t")
4979 (match_operand:SF 3 "integer_register_operand" "0,d,d")
4980 (match_operand:SF 4 "integer_register_operand" "d,0,d")))
4981 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4984 [(set_attr "length" "8,8,12")
4985 (set_attr "type" "multi")])
4988 [(set (match_operand:SF 0 "register_operand" "")
4989 (if_then_else:SF (match_operator 1 "relational_operator"
4990 [(match_operand 2 "cc_operand" "")
4992 (match_operand:SF 3 "register_operand" "")
4993 (match_operand:SF 4 "register_operand" "")))
4994 (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
4997 "operands[6] = frv_split_cond_move (operands);")
5000 ;; ::::::::::::::::::::
5002 ;; :: Minimum, maximum, and integer absolute value
5004 ;; ::::::::::::::::::::
5006 ;; These 'instructions' are provided to give the compiler a slightly better
5007 ;; nudge at register allocation, then it would if it constructed the
5008 ;; instructions from basic building blocks (since it indicates it prefers one
5009 ;; of the operands to be the same as the destination. It also helps the
5010 ;; earlier passes of the compiler, by not breaking things into small basic
5013 (define_expand "abssi2"
5014 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
5015 (abs:SI (match_operand:SI 1 "integer_register_operand" "")))
5016 (clobber (match_dup 2))
5017 (clobber (match_dup 3))])]
5021 operands[2] = gen_reg_rtx (CCmode);
5022 operands[3] = gen_reg_rtx (CC_CCRmode);
5025 (define_insn_and_split "*abssi2_internal"
5026 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
5027 (abs:SI (match_operand:SI 1 "integer_register_operand" "0,d")))
5028 (clobber (match_operand:CC 2 "icc_operand" "=t,t"))
5029 (clobber (match_operand:CC_CCR 3 "icr_operand" "=v,v"))]
5034 "operands[4] = frv_split_abs (operands);"
5035 [(set_attr "length" "12,16")
5036 (set_attr "type" "multi")])
5038 (define_expand "sminsi3"
5039 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
5040 (smin:SI (match_operand:SI 1 "integer_register_operand" "")
5041 (match_operand:SI 2 "gpr_or_int10_operand" "")))
5042 (clobber (match_dup 3))
5043 (clobber (match_dup 4))])]
5047 operands[3] = gen_reg_rtx (CCmode);
5048 operands[4] = gen_reg_rtx (CC_CCRmode);
5051 (define_expand "smaxsi3"
5052 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
5053 (smax:SI (match_operand:SI 1 "integer_register_operand" "")
5054 (match_operand:SI 2 "gpr_or_int10_operand" "")))
5055 (clobber (match_dup 3))
5056 (clobber (match_dup 4))])]
5060 operands[3] = gen_reg_rtx (CCmode);
5061 operands[4] = gen_reg_rtx (CC_CCRmode);
5064 (define_insn_and_split "*minmax_si_signed"
5065 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,&d")
5066 (match_operator:SI 1 "minmax_operator"
5067 [(match_operand:SI 2 "integer_register_operand" "%0,dO,d")
5068 (match_operand:SI 3 "gpr_or_int10_operand" "dO,0,dJ")]))
5069 (clobber (match_operand:CC 4 "icc_operand" "=t,t,t"))
5070 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
5075 "operands[6] = frv_split_minmax (operands);"
5076 [(set_attr "length" "12,12,16")
5077 (set_attr "type" "multi")])
5079 (define_expand "uminsi3"
5080 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
5081 (umin:SI (match_operand:SI 1 "integer_register_operand" "")
5082 (match_operand:SI 2 "gpr_or_int10_operand" "")))
5083 (clobber (match_dup 3))
5084 (clobber (match_dup 4))])]
5088 operands[3] = gen_reg_rtx (CC_UNSmode);
5089 operands[4] = gen_reg_rtx (CC_CCRmode);
5092 (define_expand "umaxsi3"
5093 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
5094 (umax:SI (match_operand:SI 1 "integer_register_operand" "")
5095 (match_operand:SI 2 "gpr_or_int10_operand" "")))
5096 (clobber (match_dup 3))
5097 (clobber (match_dup 4))])]
5101 operands[3] = gen_reg_rtx (CC_UNSmode);
5102 operands[4] = gen_reg_rtx (CC_CCRmode);
5105 (define_insn_and_split "*minmax_si_unsigned"
5106 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,&d")
5107 (match_operator:SI 1 "minmax_operator"
5108 [(match_operand:SI 2 "integer_register_operand" "%0,dO,d")
5109 (match_operand:SI 3 "gpr_or_int10_operand" "dO,0,dJ")]))
5110 (clobber (match_operand:CC_UNS 4 "icc_operand" "=t,t,t"))
5111 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
5116 "operands[6] = frv_split_minmax (operands);"
5117 [(set_attr "length" "12,12,16")
5118 (set_attr "type" "multi")])
5120 (define_expand "sminsf3"
5121 [(parallel [(set (match_operand:SF 0 "fpr_operand" "")
5122 (smin:SF (match_operand:SF 1 "fpr_operand" "")
5123 (match_operand:SF 2 "fpr_operand" "")))
5124 (clobber (match_dup 3))
5125 (clobber (match_dup 4))])]
5126 "TARGET_COND_MOVE && TARGET_HARD_FLOAT"
5129 operands[3] = gen_reg_rtx (CC_FPmode);
5130 operands[4] = gen_reg_rtx (CC_CCRmode);
5133 (define_expand "smaxsf3"
5134 [(parallel [(set (match_operand:SF 0 "fpr_operand" "")
5135 (smax:SF (match_operand:SF 1 "fpr_operand" "")
5136 (match_operand:SF 2 "fpr_operand" "")))
5137 (clobber (match_dup 3))
5138 (clobber (match_dup 4))])]
5139 "TARGET_COND_MOVE && TARGET_HARD_FLOAT"
5142 operands[3] = gen_reg_rtx (CC_FPmode);
5143 operands[4] = gen_reg_rtx (CC_CCRmode);
5146 (define_insn_and_split "*minmax_sf"
5147 [(set (match_operand:SF 0 "fpr_operand" "=f,f,f")
5148 (match_operator:SF 1 "minmax_operator"
5149 [(match_operand:SF 2 "fpr_operand" "%0,f,f")
5150 (match_operand:SF 3 "fpr_operand" "f,0,f")]))
5151 (clobber (match_operand:CC_FP 4 "fcc_operand" "=u,u,u"))
5152 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
5153 "TARGET_COND_MOVE && TARGET_HARD_FLOAT"
5157 "operands[6] = frv_split_minmax (operands);"
5158 [(set_attr "length" "12,12,16")
5159 (set_attr "type" "multi")])
5161 (define_expand "smindf3"
5162 [(parallel [(set (match_operand:DF 0 "fpr_operand" "")
5163 (smin:DF (match_operand:DF 1 "fpr_operand" "")
5164 (match_operand:DF 2 "fpr_operand" "")))
5165 (clobber (match_dup 3))
5166 (clobber (match_dup 4))])]
5167 "TARGET_COND_MOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE"
5170 operands[3] = gen_reg_rtx (CC_FPmode);
5171 operands[4] = gen_reg_rtx (CC_CCRmode);
5174 (define_expand "smaxdf3"
5175 [(parallel [(set (match_operand:DF 0 "fpr_operand" "")
5176 (smax:DF (match_operand:DF 1 "fpr_operand" "")
5177 (match_operand:DF 2 "fpr_operand" "")))
5178 (clobber (match_dup 3))
5179 (clobber (match_dup 4))])]
5180 "TARGET_COND_MOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE"
5183 operands[3] = gen_reg_rtx (CC_FPmode);
5184 operands[4] = gen_reg_rtx (CC_CCRmode);
5187 (define_insn_and_split "*minmax_df"
5188 [(set (match_operand:DF 0 "fpr_operand" "=f,f,f")
5189 (match_operator:DF 1 "minmax_operator"
5190 [(match_operand:DF 2 "fpr_operand" "%0,f,f")
5191 (match_operand:DF 3 "fpr_operand" "f,0,f")]))
5192 (clobber (match_operand:CC_FP 4 "fcc_operand" "=u,u,u"))
5193 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
5194 "TARGET_COND_MOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE"
5198 "operands[6] = frv_split_minmax (operands);"
5199 [(set_attr "length" "12,12,16")
5200 (set_attr "type" "multi")])
5203 ;; ::::::::::::::::::::
5205 ;; :: Call and branch instructions
5207 ;; ::::::::::::::::::::
5209 ;; Subroutine call instruction returning no value. Operand 0 is the function
5210 ;; to call; operand 1 is the number of bytes of arguments pushed (in mode
5211 ;; `SImode', except it is normally a `const_int'); operand 2 is the number of
5212 ;; registers used as operands.
5214 ;; On most machines, operand 2 is not actually stored into the RTL pattern. It
5215 ;; is supplied for the sake of some RISC machines which need to put this
5216 ;; information into the assembler code; they can put it in the RTL instead of
5219 (define_expand "call"
5220 [(use (match_operand:QI 0 "" ""))
5221 (use (match_operand 1 "" ""))
5222 (use (match_operand 2 "" ""))
5223 (use (match_operand 3 "" ""))]
5227 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
5230 if (GET_CODE (operands[0]) != MEM)
5233 addr = XEXP (operands[0], 0);
5234 if (! call_operand (addr, Pmode))
5235 addr = force_reg (Pmode, addr);
5238 operands[2] = const0_rtx;
5240 emit_call_insn (gen_call_internal (addr, operands[1], operands[2], lr));
5244 (define_insn "call_internal"
5245 [(call (mem:QI (match_operand:SI 0 "call_operand" "S,dNOP"))
5246 (match_operand 1 "" ""))
5247 (use (match_operand 2 "" ""))
5248 (clobber (match_operand:SI 3 "lr_operand" "=l,l"))]
5253 [(set_attr "length" "4")
5254 (set_attr "type" "call,jumpl")])
5256 ;; Subroutine call instruction returning a value. Operand 0 is the hard
5257 ;; register in which the value is returned. There are three more operands, the
5258 ;; same as the three operands of the `call' instruction (but with numbers
5259 ;; increased by one).
5261 ;; Subroutines that return `BLKmode' objects use the `call' insn.
5263 (define_expand "call_value"
5264 [(use (match_operand 0 "" ""))
5265 (use (match_operand:QI 1 "" ""))
5266 (use (match_operand 2 "" ""))
5267 (use (match_operand 3 "" ""))
5268 (use (match_operand 4 "" ""))]
5272 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
5275 if (GET_CODE (operands[1]) != MEM)
5278 addr = XEXP (operands[1], 0);
5279 if (! call_operand (addr, Pmode))
5280 addr = force_reg (Pmode, addr);
5283 operands[3] = const0_rtx;
5285 emit_call_insn (gen_call_value_internal (operands[0], addr, operands[2],
5290 (define_insn "call_value_internal"
5291 [(set (match_operand 0 "register_operand" "=d,d")
5292 (call (mem:QI (match_operand:SI 1 "call_operand" "S,dNOP"))
5293 (match_operand 2 "" "")))
5294 (use (match_operand 3 "" ""))
5295 (clobber (match_operand:SI 4 "lr_operand" "=l,l"))]
5300 [(set_attr "length" "4")
5301 (set_attr "type" "call,jumpl")])
5303 ;; return instruction generated instead of jmp to epilog
5304 (define_expand "return"
5305 [(parallel [(return)
5307 (use (const_int 1))])]
5308 "direct_return_p ()"
5311 operands[0] = gen_rtx_REG (Pmode, LR_REGNO);
5314 ;; return instruction generated by the epilogue
5315 (define_expand "epilogue_return"
5316 [(parallel [(return)
5317 (use (match_operand:SI 0 "register_operand" ""))
5318 (use (const_int 0))])]
5322 (define_insn "*return_internal"
5324 (use (match_operand:SI 0 "register_operand" "l,d"))
5325 (use (match_operand:SI 1 "immediate_operand" "n,n"))]
5330 [(set_attr "length" "4")
5331 (set_attr "type" "jump,jumpl")])
5333 ;; A version of addsi3 for deallocating stack space at the end of the
5334 ;; epilogue. The addition is done in parallel with an (unspec_volatile),
5335 ;; which represents the clobbering of the deallocated space.
5336 (define_insn "stack_adjust"
5337 [(set (match_operand:SI 0 "register_operand" "=d")
5338 (plus:SI (match_operand:SI 1 "register_operand" "d")
5339 (match_operand:SI 2 "general_operand" "dNOP")))
5340 (unspec_volatile [(const_int 0)] UNSPEC_STACK_ADJUST)]
5343 [(set_attr "length" "4")
5344 (set_attr "type" "int")])
5346 ;; Normal unconditional jump
5348 ;; Use the "call" instruction for long branches, but prefer to use "bra" for
5349 ;; short ones since it does not force us to save the link register.
5351 ;; This define_insn uses the branch-shortening code to decide which
5352 ;; instruction it emits. Since the main branch-shortening interface is
5353 ;; through get_attr_length(), the two alternatives must be given different
5354 ;; lengths. Here we pretend that the far jump is 8 rather than 4 bytes
5355 ;; long, though both alternatives are really the same size.
5357 [(set (pc) (label_ref (match_operand 0 "" "")))]
5361 if (get_attr_length (insn) == 4)
5364 return \"call %l0\";
5366 [(set (attr "length")
5368 (and (ge (minus (match_dup 0) (pc)) (const_int -32768))
5369 (le (minus (match_dup 0) (pc)) (const_int 32764)))
5372 (set (attr "far_jump")
5374 (eq_attr "length" "4")
5376 (const_string "yes")))
5379 (eq_attr "length" "4")
5380 (const_string "jump")
5381 (const_string "call")))])
5383 ;; Indirect jump through a register
5384 (define_insn "indirect_jump"
5385 [(set (pc) (match_operand:SI 0 "register_operand" "d,l"))]
5390 [(set_attr "length" "4")
5391 (set_attr "type" "jumpl,branch")])
5393 ;; Instruction to jump to a variable address. This is a low-level capability
5394 ;; which can be used to implement a dispatch table when there is no `casesi'
5395 ;; pattern. Either the 'casesi' pattern or the 'tablejump' pattern, or both,
5396 ;; MUST be present in this file.
5398 ;; This pattern requires two operands: the address or offset, and a label which
5399 ;; should immediately precede the jump table. If the macro
5400 ;; `CASE_VECTOR_PC_RELATIVE' is defined then the first operand is an offset
5401 ;; which counts from the address of the table; otherwise, it is an absolute
5402 ;; address to jump to. In either case, the first operand has mode `Pmode'.
5404 ;; The `tablejump' insn is always the last insn before the jump table it uses.
5405 ;; Its assembler code normally has no need to use the second operand, but you
5406 ;; should incorporate it in the RTL pattern so that the jump optimizer will not
5407 ;; delete the table as unreachable code.
5409 (define_expand "tablejump"
5410 [(parallel [(set (pc) (match_operand:SI 0 "address_operand" "p"))
5411 (use (label_ref (match_operand 1 "" "")))])]
5415 (define_insn "tablejump_insn"
5416 [(set (pc) (match_operand:SI 0 "address_operand" "p"))
5417 (use (label_ref (match_operand 1 "" "")))]
5420 [(set_attr "length" "4")
5421 (set_attr "type" "jumpl")])
5423 ;; Implement switch statements when generating PIC code. Switches are
5424 ;; implemented by `tablejump' when not using -fpic.
5426 ;; Emit code here to do the range checking and make the index zero based.
5427 ;; operand 0 is the index
5428 ;; operand 1 is the lower bound
5429 ;; operand 2 is the range of indices (highest - lowest + 1)
5430 ;; operand 3 is the label that precedes the table itself
5431 ;; operand 4 is the fall through label
5433 (define_expand "casesi"
5434 [(use (match_operand:SI 0 "integer_register_operand" ""))
5435 (use (match_operand:SI 1 "const_int_operand" ""))
5436 (use (match_operand:SI 2 "const_int_operand" ""))
5437 (use (match_operand 3 "" ""))
5438 (use (match_operand 4 "" ""))]
5444 rtx low = operands[1];
5445 rtx range = operands[2];
5446 rtx table = operands[3];
5448 rtx fail = operands[4];
5453 if (GET_CODE (operands[1]) != CONST_INT)
5456 if (GET_CODE (operands[2]) != CONST_INT)
5459 /* If we can't generate an immediate instruction, promote to register */
5460 if (! IN_RANGE_P (INTVAL (range), -2048, 2047))
5461 range = force_reg (SImode, range);
5463 /* If low bound is 0, we don't have to subtract it. */
5464 if (INTVAL (operands[1]) == 0)
5468 indx = gen_reg_rtx (SImode);
5469 if (IN_RANGE_P (INTVAL (low), -2047, 2048))
5470 emit_insn (gen_addsi3 (indx, operands[0], GEN_INT (- INTVAL (low))));
5472 emit_insn (gen_subsi3 (indx, operands[0], force_reg (SImode, low)));
5475 /* Do an unsigned comparison (in the proper mode) between the index
5476 expression and the value which represents the length of the range.
5477 Since we just finished subtracting the lower bound of the range
5478 from the index expression, this comparison allows us to simultaneously
5479 check that the original index expression value is both greater than
5480 or equal to the minimum value of the range and less than or equal to
5481 the maximum value of the range. */
5483 emit_cmp_and_jump_insns (indx, range, GTU, NULL_RTX, SImode, 1, fail);
5485 /* Move the table address to a register */
5486 treg = gen_reg_rtx (Pmode);
5487 emit_insn (gen_movsi (treg, gen_rtx_LABEL_REF (VOIDmode, table)));
5489 /* scale index-low by wordsize */
5490 scale = gen_reg_rtx (SImode);
5491 emit_insn (gen_ashlsi3 (scale, indx, GEN_INT (2)));
5493 /* Load the address, add the start of the table back in,
5495 mem = gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, scale, treg));
5496 reg2 = gen_reg_rtx (SImode);
5497 reg3 = gen_reg_rtx (SImode);
5498 emit_insn (gen_movsi (reg2, mem));
5499 emit_insn (gen_addsi3 (reg3, reg2, treg));
5500 emit_jump_insn (gen_tablejump_insn (reg3, table));
5505 ;; ::::::::::::::::::::
5507 ;; :: Prologue and Epilogue instructions
5509 ;; ::::::::::::::::::::
5511 ;; Called after register allocation to add any instructions needed for the
5512 ;; prologue. Using a prologue insn is favored compared to putting all of the
5513 ;; instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
5514 ;; to intermix instructions with the saves of the caller saved registers. In
5515 ;; some cases, it might be necessary to emit a barrier instruction as the last
5516 ;; insn to prevent such scheduling.
5517 (define_expand "prologue"
5522 frv_expand_prologue ();
5526 ;; Called after register allocation to add any instructions needed for the
5527 ;; epilogue. Using an epilogue insn is favored compared to putting all of the
5528 ;; instructions in the FUNCTION_EPILOGUE macro, since it allows the scheduler
5529 ;; to intermix instructions with the restires of the caller saved registers.
5530 ;; In some cases, it might be necessary to emit a barrier instruction as the
5531 ;; first insn to prevent such scheduling.
5532 (define_expand "epilogue"
5537 frv_expand_epilogue (FALSE);
5541 ;; This pattern, if defined, emits RTL for exit from a function without the final
5542 ;; branch back to the calling function. This pattern will be emitted before any
5543 ;; sibling call (aka tail call) sites.
5545 ;; The sibcall_epilogue pattern must not clobber any arguments used for
5546 ;; parameter passing or any stack slots for arguments passed to the current
5548 (define_expand "sibcall_epilogue"
5553 frv_expand_epilogue (TRUE);
5557 ;; Set up the pic register to hold the address of the pic table
5558 (define_insn "pic_prologue"
5559 [(set (match_operand:SI 0 "integer_register_operand" "=d")
5560 (unspec_volatile:SI [(const_int 0)] UNSPEC_PIC_PROLOGUE))
5561 (clobber (match_operand:SI 1 "lr_operand" "=l"))
5562 (clobber (match_operand:SI 2 "integer_register_operand" "=d"))]
5566 static int frv_pic_labelno = 0;
5568 operands[3] = GEN_INT (frv_pic_labelno++);
5569 return \"call %P3\\n%P3:\;movsg %1, %0\;sethi #gprelhi(%P3), %2\;setlo #gprello(%P3), %2\;sub %0,%2,%0\";
5571 [(set_attr "length" "16")
5572 (set_attr "type" "multi")])
5574 ;; ::::::::::::::::::::
5576 ;; :: Miscellaneous instructions
5578 ;; ::::::::::::::::::::
5580 ;; No operation, needed in case the user uses -g but not -O.
5585 [(set_attr "length" "4")
5586 (set_attr "type" "int")])
5588 ;; Pseudo instruction that prevents the scheduler from moving code above this
5589 ;; point. Note, type unknown is used to make sure the VLIW instructions are
5590 ;; not continued past this point.
5591 (define_insn "blockage"
5592 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5595 [(set_attr "length" "0")
5596 (set_attr "type" "unknown")])
5598 ;; ::::::::::::::::::::
5600 ;; :: Media instructions
5602 ;; ::::::::::::::::::::
5604 ;; Unimplemented instructions:
5608 [(UNSPEC_MLOGIC 100)
5615 (UNSPEC_MUNPACKH 107)
5616 (UNSPEC_MDPACKH 108)
5621 (UNSPEC_MEXPDHW 113)
5622 (UNSPEC_MEXPDHD 114)
5629 (UNSPEC_MQMULXH 121)
5635 (UNSPEC_MRDACCG 127)
5637 (UNSPEC_MWTACCG 129)
5639 (UNSPEC_MCLRACC 131)
5640 (UNSPEC_MCLRACCA 132)
5643 (UNSPEC_MDUNPACKH 135)
5644 (UNSPEC_MDUNPACKH_INTERNAL 136)
5646 (UNSPEC_MBTOHE_INTERNAL 138)
5648 (UNSPEC_MBTOHE_INTERNAL 138)
5649 (UNSPEC_MQMACH2 139)
5650 (UNSPEC_MADDACC 140)
5651 (UNSPEC_MDADDACC 141)
5653 (UNSPEC_MDROTLI 143)
5656 (UNSPEC_MDCUTSSI 146)
5657 (UNSPEC_MQSATHS 147)
5658 (UNSPEC_MHSETLOS 148)
5659 (UNSPEC_MHSETLOH 149)
5660 (UNSPEC_MHSETHIS 150)
5661 (UNSPEC_MHSETHIH 151)
5662 (UNSPEC_MHDSETS 152)
5663 (UNSPEC_MHDSETH 153)
5666 ;; Logic operations: type "mlogic"
5668 (define_expand "mand"
5669 [(set (match_operand:SI 0 "fpr_operand" "")
5670 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
5671 (match_operand:SI 2 "fpr_operand" "")
5675 "operands[3] = GEN_INT (FRV_BUILTIN_MAND);")
5677 (define_expand "mor"
5678 [(set (match_operand:SI 0 "fpr_operand" "")
5679 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
5680 (match_operand:SI 2 "fpr_operand" "")
5684 "operands[3] = GEN_INT (FRV_BUILTIN_MOR);")
5686 (define_expand "mxor"
5687 [(set (match_operand:SI 0 "fpr_operand" "")
5688 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
5689 (match_operand:SI 2 "fpr_operand" "")
5693 "operands[3] = GEN_INT (FRV_BUILTIN_MXOR);")
5695 (define_insn "*mlogic"
5696 [(set (match_operand:SI 0 "fpr_operand" "=f")
5697 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5698 (match_operand:SI 2 "fpr_operand" "f")
5699 (match_operand:SI 3 "const_int_operand" "n")]
5704 switch (INTVAL (operands[3]))
5707 case FRV_BUILTIN_MAND: return \"mand %1, %2, %0\";
5708 case FRV_BUILTIN_MOR: return \"mor %1, %2, %0\";
5709 case FRV_BUILTIN_MXOR: return \"mxor %1, %2, %0\";
5712 fatal_insn (\"Bad media insn, mlogic\", insn);
5714 [(set_attr "length" "4")
5715 (set_attr "type" "mlogic")])
5717 (define_insn "*cond_exec_mlogic"
5719 (match_operator 0 "ccr_eqne_operator"
5720 [(match_operand 1 "cr_operand" "C")
5722 (set (match_operand:SI 2 "fpr_operand" "=f")
5723 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
5724 (match_operand:SI 4 "fpr_operand" "f")
5725 (match_operand:SI 5 "const_int_operand" "n")]
5730 switch (INTVAL (operands[5]))
5733 case FRV_BUILTIN_MAND: return \"cmand %3, %4, %2, %1, %e0\";
5734 case FRV_BUILTIN_MOR: return \"cmor %3, %4, %2, %1, %e0\";
5735 case FRV_BUILTIN_MXOR: return \"cmxor %3, %4, %2, %1, %e0\";
5738 fatal_insn (\"Bad media insn, cond_exec_mlogic\", insn);
5740 [(set_attr "length" "4")
5741 (set_attr "type" "mlogic")])
5743 ;; Logical not: type "mlogic"
5746 [(set (match_operand:SI 0 "fpr_operand" "=f")
5747 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MNOT))]
5750 [(set_attr "length" "4")
5751 (set_attr "type" "mlogic")])
5753 (define_insn "*cond_exec_mnot"
5755 (match_operator 0 "ccr_eqne_operator"
5756 [(match_operand 1 "cr_operand" "C")
5758 (set (match_operand:SI 2 "fpr_operand" "=f")
5759 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")] UNSPEC_MNOT)))]
5761 "cmnot %3, %2, %1, %e0"
5762 [(set_attr "length" "4")
5763 (set_attr "type" "mlogic")])
5765 ;; Dual average (halfword): type "maveh"
5767 (define_insn "maveh"
5768 [(set (match_operand:SI 0 "fpr_operand" "=f")
5769 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5770 (match_operand:SI 2 "fpr_operand" "f")]
5774 [(set_attr "length" "4")
5775 (set_attr "type" "maveh")])
5777 ;; Dual saturation (halfword): type "msath"
5779 (define_expand "msaths"
5780 [(set (match_operand:SI 0 "fpr_operand" "=f")
5781 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5782 (match_operand:SI 2 "fpr_operand" "f")
5786 "operands[3] = GEN_INT (FRV_BUILTIN_MSATHS);")
5788 (define_expand "msathu"
5789 [(set (match_operand:SI 0 "fpr_operand" "=f")
5790 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5791 (match_operand:SI 2 "fpr_operand" "f")
5795 "operands[3] = GEN_INT (FRV_BUILTIN_MSATHU);")
5797 (define_insn "*msath"
5798 [(set (match_operand:SI 0 "fpr_operand" "=f")
5799 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5800 (match_operand:SI 2 "fpr_operand" "f")
5801 (match_operand:SI 3 "const_int_operand" "n")]
5806 switch (INTVAL (operands[3]))
5809 case FRV_BUILTIN_MSATHS: return \"msaths %1, %2, %0\";
5810 case FRV_BUILTIN_MSATHU: return \"msathu %1, %2, %0\";
5813 fatal_insn (\"Bad media insn, msath\", insn);
5815 [(set_attr "length" "4")
5816 (set_attr "type" "msath")])
5818 ;; Dual addition/subtraction with saturation (halfword): type "maddh"
5820 (define_expand "maddhss"
5821 [(set (match_operand:SI 0 "fpr_operand" "=f")
5822 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5823 (match_operand:SI 2 "fpr_operand" "f")
5827 "operands[3] = GEN_INT (FRV_BUILTIN_MADDHSS);")
5829 (define_expand "maddhus"
5830 [(set (match_operand:SI 0 "fpr_operand" "=f")
5831 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5832 (match_operand:SI 2 "fpr_operand" "f")
5836 "operands[3] = GEN_INT (FRV_BUILTIN_MADDHUS);")
5838 (define_expand "msubhss"
5839 [(set (match_operand:SI 0 "fpr_operand" "=f")
5840 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5841 (match_operand:SI 2 "fpr_operand" "f")
5845 "operands[3] = GEN_INT (FRV_BUILTIN_MSUBHSS);")
5847 (define_expand "msubhus"
5848 [(set (match_operand:SI 0 "fpr_operand" "=f")
5849 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5850 (match_operand:SI 2 "fpr_operand" "f")
5854 "operands[3] = GEN_INT (FRV_BUILTIN_MSUBHUS);")
5856 (define_insn "*maddh"
5857 [(set (match_operand:SI 0 "fpr_operand" "=f")
5858 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5859 (match_operand:SI 2 "fpr_operand" "f")
5860 (match_operand:SI 3 "const_int_operand" "n")]
5865 switch (INTVAL (operands[3]))
5868 case FRV_BUILTIN_MADDHSS: return \"maddhss %1, %2, %0\";
5869 case FRV_BUILTIN_MADDHUS: return \"maddhus %1, %2, %0\";
5870 case FRV_BUILTIN_MSUBHSS: return \"msubhss %1, %2, %0\";
5871 case FRV_BUILTIN_MSUBHUS: return \"msubhus %1, %2, %0\";
5874 fatal_insn (\"Bad media insn, maddh\", insn);
5876 [(set_attr "length" "4")
5877 (set_attr "type" "maddh")])
5879 (define_insn "*cond_exec_maddh"
5881 (match_operator 0 "ccr_eqne_operator"
5882 [(match_operand 1 "cr_operand" "C")
5884 (set (match_operand:SI 2 "fpr_operand" "=f")
5885 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
5886 (match_operand:SI 4 "fpr_operand" "f")
5887 (match_operand:SI 5 "const_int_operand" "n")]
5892 switch (INTVAL (operands[5]))
5895 case FRV_BUILTIN_MADDHSS: return \"cmaddhss %3, %4, %2, %1, %e0\";
5896 case FRV_BUILTIN_MADDHUS: return \"cmaddhus %3, %4, %2, %1, %e0\";
5897 case FRV_BUILTIN_MSUBHSS: return \"cmsubhss %3, %4, %2, %1, %e0\";
5898 case FRV_BUILTIN_MSUBHUS: return \"cmsubhus %3, %4, %2, %1, %e0\";
5901 fatal_insn (\"Bad media insn, cond_exec_maddh\", insn);
5903 [(set_attr "length" "4")
5904 (set_attr "type" "maddh")])
5906 ;; Quad addition/subtraction with saturation (halfword): type "mqaddh"
5908 (define_expand "mqaddhss"
5909 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
5910 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
5911 (match_operand:DI 2 "even_fpr_operand" "h")
5915 "operands[3] = GEN_INT (FRV_BUILTIN_MQADDHSS);")
5917 (define_expand "mqaddhus"
5918 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
5919 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
5920 (match_operand:DI 2 "even_fpr_operand" "h")
5924 "operands[3] = GEN_INT (FRV_BUILTIN_MQADDHUS);")
5926 (define_expand "mqsubhss"
5927 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
5928 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
5929 (match_operand:DI 2 "even_fpr_operand" "h")
5933 "operands[3] = GEN_INT (FRV_BUILTIN_MQSUBHSS);")
5935 (define_expand "mqsubhus"
5936 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
5937 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
5938 (match_operand:DI 2 "even_fpr_operand" "h")
5942 "operands[3] = GEN_INT (FRV_BUILTIN_MQSUBHUS);")
5944 (define_insn "*mqaddh"
5945 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
5946 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
5947 (match_operand:DI 2 "even_fpr_operand" "h")
5948 (match_operand:SI 3 "const_int_operand" "n")]
5953 switch (INTVAL (operands[3]))
5956 case FRV_BUILTIN_MQADDHSS: return \"mqaddhss %1, %2, %0\";
5957 case FRV_BUILTIN_MQADDHUS: return \"mqaddhus %1, %2, %0\";
5958 case FRV_BUILTIN_MQSUBHSS: return \"mqsubhss %1, %2, %0\";
5959 case FRV_BUILTIN_MQSUBHUS: return \"mqsubhus %1, %2, %0\";
5962 fatal_insn (\"Bad media insn, mqaddh\", insn);
5964 [(set_attr "length" "4")
5965 (set_attr "type" "mqaddh")])
5967 (define_insn "*cond_exec_mqaddh"
5969 (match_operator 0 "ccr_eqne_operator"
5970 [(match_operand 1 "cr_operand" "C")
5972 (set (match_operand:DI 2 "even_fpr_operand" "=h")
5973 (unspec:DI [(match_operand:DI 3 "even_fpr_operand" "h")
5974 (match_operand:DI 4 "even_fpr_operand" "h")
5975 (match_operand:SI 5 "const_int_operand" "n")]
5980 switch (INTVAL (operands[5]))
5983 case FRV_BUILTIN_MQADDHSS: return \"cmqaddhss %3, %4, %2, %1, %e0\";
5984 case FRV_BUILTIN_MQADDHUS: return \"cmqaddhus %3, %4, %2, %1, %e0\";
5985 case FRV_BUILTIN_MQSUBHSS: return \"cmqsubhss %3, %4, %2, %1, %e0\";
5986 case FRV_BUILTIN_MQSUBHUS: return \"cmqsubhus %3, %4, %2, %1, %e0\";
5989 fatal_insn (\"Bad media insn, cond_exec_mqaddh\", insn);
5991 [(set_attr "length" "4")
5992 (set_attr "type" "mqaddh")])
5994 ;; Pack halfword: type "mpackh"
5996 (define_insn "mpackh"
5997 [(set (match_operand:SI 0 "fpr_operand" "=f")
5998 (unspec:SI [(match_operand:HI 1 "fpr_operand" "f")
5999 (match_operand:HI 2 "fpr_operand" "f")]
6003 [(set_attr "length" "4")
6004 (set_attr "type" "mpackh")])
6006 ;; Unpack halfword: type "mpackh"
6008 (define_insn "munpackh"
6009 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6010 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")]
6014 [(set_attr "length" "4")
6015 (set_attr "type" "munpackh")])
6017 ;; Dual pack halfword: type "mdpackh"
6019 (define_insn "mdpackh"
6020 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6021 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6022 (match_operand:DI 2 "even_fpr_operand" "h")]
6025 "mdpackh %1, %2, %0"
6026 [(set_attr "length" "4")
6027 (set_attr "type" "mdpackh")])
6029 ;; Byte-halfword conversion: type "mbhconv"
6031 (define_insn "mbtoh"
6032 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6033 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")]
6037 [(set_attr "length" "4")
6038 (set_attr "type" "mbhconv")])
6040 (define_insn "*cond_exec_mbtoh"
6042 (match_operator 0 "ccr_eqne_operator"
6043 [(match_operand 1 "cr_operand" "C")
6045 (set (match_operand:DI 2 "even_fpr_operand" "=h")
6046 (unspec:DI [(match_operand:SI 3 "fpr_operand" "f")]
6049 "cmbtoh %3, %2, %1, %e0"
6050 [(set_attr "length" "4")
6051 (set_attr "type" "mbhconv")])
6053 (define_insn "mhtob"
6054 [(set (match_operand:SI 0 "fpr_operand" "=f")
6055 (unspec:SI [(match_operand:DI 1 "even_fpr_operand" "h")]
6059 [(set_attr "length" "4")
6060 (set_attr "type" "mbhconv")])
6062 (define_insn "*cond_exec_mhtob"
6064 (match_operator 0 "ccr_eqne_operator"
6065 [(match_operand 1 "cr_operand" "C")
6067 (set (match_operand:SI 2 "fpr_operand" "=f")
6068 (unspec:SI [(match_operand:DI 3 "even_fpr_operand" "h")]
6071 "cmhtob %3, %2, %1, %e0"
6072 [(set_attr "length" "4")
6073 (set_attr "type" "mbhconv")])
6075 ;; Rotate: type "mrot"
6077 (define_expand "mrotli"
6078 [(set (match_operand:SI 0 "fpr_operand" "")
6079 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6080 (match_operand:SI 2 "uint5_operand" "")
6084 "operands[3] = GEN_INT (FRV_BUILTIN_MROTLI);")
6086 (define_expand "mrotri"
6087 [(set (match_operand:SI 0 "fpr_operand" "")
6088 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6089 (match_operand:SI 2 "uint5_operand" "")
6093 "operands[3] = GEN_INT (FRV_BUILTIN_MROTRI);")
6095 (define_insn "*mrot"
6096 [(set (match_operand:SI 0 "fpr_operand" "=f")
6097 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6098 (match_operand:SI 2 "uint5_operand" "I")
6099 (match_operand:SI 3 "const_int_operand" "n")]
6104 switch (INTVAL (operands[3]))
6107 case FRV_BUILTIN_MROTLI: return \"mrotli %1, %2, %0\";
6108 case FRV_BUILTIN_MROTRI: return \"mrotri %1, %2, %0\";
6111 fatal_insn (\"Bad media insn, mrot\", insn);
6113 [(set_attr "length" "4")
6114 (set_attr "type" "mrot")])
6116 ;; Dual shift halfword: type "msh"
6118 (define_expand "msllhi"
6119 [(set (match_operand:SI 0 "fpr_operand" "")
6120 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6121 (match_operand:SI 2 "uint4_operand" "")
6125 "operands[3] = GEN_INT (FRV_BUILTIN_MSLLHI);")
6127 (define_expand "msrlhi"
6128 [(set (match_operand:SI 0 "fpr_operand" "")
6129 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6130 (match_operand:SI 2 "uint4_operand" "")
6134 "operands[3] = GEN_INT (FRV_BUILTIN_MSRLHI);")
6136 (define_expand "msrahi"
6137 [(set (match_operand:SI 0 "fpr_operand" "")
6138 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6139 (match_operand:SI 2 "uint4_operand" "")
6143 "operands[3] = GEN_INT (FRV_BUILTIN_MSRAHI);")
6145 (define_insn "*mshift"
6146 [(set (match_operand:SI 0 "fpr_operand" "=f")
6147 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6148 (match_operand:SI 2 "uint4_operand" "I")
6149 (match_operand:SI 3 "const_int_operand" "n")]
6154 switch (INTVAL (operands[3]))
6157 case FRV_BUILTIN_MSLLHI: return \"msllhi %1, %2, %0\";
6158 case FRV_BUILTIN_MSRLHI: return \"msrlhi %1, %2, %0\";
6159 case FRV_BUILTIN_MSRAHI: return \"msrahi %1, %2, %0\";
6162 fatal_insn (\"Bad media insn, mshift\", insn);
6164 [(set_attr "length" "4")
6165 (set_attr "type" "mshift")])
6167 ;; Expand halfword to word: type "mexpdhw"
6169 (define_insn "mexpdhw"
6170 [(set (match_operand:SI 0 "even_fpr_operand" "=h")
6171 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6172 (match_operand:SI 2 "uint1_operand" "I")]
6175 "mexpdhw %1, %2, %0"
6176 [(set_attr "length" "4")
6177 (set_attr "type" "mexpdhw")])
6179 (define_insn "*cond_exec_mexpdhw"
6181 (match_operator 0 "ccr_eqne_operator"
6182 [(match_operand 1 "cr_operand" "C")
6184 (set (match_operand:SI 2 "even_fpr_operand" "=h")
6185 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
6186 (match_operand:SI 4 "uint1_operand" "I")]
6189 "cmexpdhw %3, %4, %2, %1, %e0"
6190 [(set_attr "length" "4")
6191 (set_attr "type" "mexpdhw")])
6193 ;; Expand halfword to double: type "mexpdhd"
6195 (define_insn "mexpdhd"
6196 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6197 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6198 (match_operand:SI 2 "uint1_operand" "I")]
6201 "mexpdhd %1, %2, %0"
6202 [(set_attr "length" "4")
6203 (set_attr "type" "mexpdhd")])
6205 (define_insn "*cond_exec_mexpdhd"
6207 (match_operator 0 "ccr_eqne_operator"
6208 [(match_operand 1 "cr_operand" "C")
6210 (set (match_operand:DI 2 "even_fpr_operand" "=h")
6211 (unspec:DI [(match_operand:SI 3 "fpr_operand" "f")
6212 (match_operand:SI 4 "uint1_operand" "I")]
6215 "cmexpdhd %3, %4, %2, %1, %e0"
6216 [(set_attr "length" "4")
6217 (set_attr "type" "mexpdhd")])
6219 ;; FR cut: type "mwcut"
6221 (define_insn "mwcut"
6222 [(set (match_operand:SI 0 "fpr_operand" "=f")
6223 (unspec:SI [(match_operand:DI 1 "fpr_operand" "f")
6224 (match_operand:SI 2 "fpr_or_int6_operand" "fI")]
6227 "mwcut%i2 %1, %2, %0"
6228 [(set_attr "length" "4")
6229 (set_attr "type" "mwcut")])
6231 ;; Dual multiplication (halfword): type "mmulh"
6233 (define_expand "mmulhs"
6234 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6235 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6236 (match_operand:SI 2 "fpr_operand" "f")
6239 (set (match_operand:HI 3 "accg_operand" "=B")
6240 (unspec:HI [(const_int 0)] UNSPEC_MMULH))])]
6242 "operands[4] = GEN_INT (FRV_BUILTIN_MMULHS);")
6244 (define_expand "mmulhu"
6245 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6246 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6247 (match_operand:SI 2 "fpr_operand" "f")
6250 (set (match_operand:HI 3 "accg_operand" "=B")
6251 (unspec:HI [(const_int 0)] UNSPEC_MMULH))])]
6253 "operands[4] = GEN_INT (FRV_BUILTIN_MMULHU);")
6255 (define_insn "*mmulh"
6256 [(set (match_operand:DI 0 "even_acc_operand" "=b")
6257 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6258 (match_operand:SI 2 "fpr_operand" "f")
6259 (match_operand:SI 3 "const_int_operand" "n")]
6261 (set (match_operand:HI 4 "accg_operand" "=B")
6262 (unspec:HI [(const_int 0)] UNSPEC_MMULH))]
6266 switch (INTVAL (operands[3]))
6269 case FRV_BUILTIN_MMULHS: return \"mmulhs %1, %2, %0\";
6270 case FRV_BUILTIN_MMULHU: return \"mmulhu %1, %2, %0\";
6273 fatal_insn (\"Bad media insn, mmulh\", insn);
6275 [(set_attr "length" "4")
6276 (set_attr "type" "mmulh")])
6278 (define_insn "*cond_exec_mmulh"
6280 (match_operator 0 "ccr_eqne_operator"
6281 [(match_operand 1 "cr_operand" "C")
6283 (parallel [(set (match_operand:DI 2 "even_acc_operand" "=b")
6284 (unspec:DI [(match_operand:SI 3 "fpr_operand" "f")
6285 (match_operand:SI 4 "fpr_operand" "f")
6286 (match_operand:SI 5 "const_int_operand" "n")]
6288 (set (match_operand:HI 6 "accg_operand" "=B")
6289 (unspec:HI [(const_int 0)] UNSPEC_MMULH))]))]
6293 switch (INTVAL (operands[5]))
6296 case FRV_BUILTIN_MMULHS: return \"cmmulhs %3, %4, %2, %1, %e0\";
6297 case FRV_BUILTIN_MMULHU: return \"cmmulhu %3, %4, %2, %1, %e0\";
6300 fatal_insn (\"Bad media insn, cond_exec_mmulh\", insn);
6302 [(set_attr "length" "4")
6303 (set_attr "type" "mmulh")])
6305 ;; Dual cross multiplication (halfword): type "mmulxh"
6307 (define_expand "mmulxhs"
6308 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6309 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6310 (match_operand:SI 2 "fpr_operand" "f")
6313 (set (match_operand:HI 3 "accg_operand" "=B")
6314 (unspec:HI [(const_int 0)] UNSPEC_MMULXH))])]
6316 "operands[4] = GEN_INT (FRV_BUILTIN_MMULXHS);")
6318 (define_expand "mmulxhu"
6319 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6320 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6321 (match_operand:SI 2 "fpr_operand" "f")
6324 (set (match_operand:HI 3 "accg_operand" "=B")
6325 (unspec:HI [(const_int 0)] UNSPEC_MMULXH))])]
6327 "operands[4] = GEN_INT (FRV_BUILTIN_MMULXHU);")
6329 (define_insn "*mmulxh"
6330 [(set (match_operand:DI 0 "even_acc_operand" "=b")
6331 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6332 (match_operand:SI 2 "fpr_operand" "f")
6333 (match_operand:SI 3 "const_int_operand" "n")]
6335 (set (match_operand:HI 4 "accg_operand" "=B")
6336 (unspec:HI [(const_int 0)] UNSPEC_MMULXH))]
6340 switch (INTVAL (operands[3]))
6343 case FRV_BUILTIN_MMULXHS: return \"mmulxhs %1, %2, %0\";
6344 case FRV_BUILTIN_MMULXHU: return \"mmulxhu %1, %2, %0\";
6347 fatal_insn (\"Bad media insn, mmulxh\", insn);
6349 [(set_attr "length" "4")
6350 (set_attr "type" "mmulxh")])
6352 ;; Dual product-sum (halfword): type "mmach"
6354 (define_expand "mmachs"
6355 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6356 (unspec:DI [(match_dup 0)
6357 (match_operand:SI 1 "fpr_operand" "f")
6358 (match_operand:SI 2 "fpr_operand" "f")
6359 (match_operand:HI 3 "accg_operand" "+B")
6363 (unspec:HI [(const_int 0)] UNSPEC_MMACH))])]
6365 "operands[4] = GEN_INT (FRV_BUILTIN_MMACHS);")
6367 (define_expand "mmachu"
6368 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6369 (unspec:DI [(match_dup 0)
6370 (match_operand:SI 1 "fpr_operand" "f")
6371 (match_operand:SI 2 "fpr_operand" "f")
6372 (match_operand:HI 3 "accg_operand" "+B")
6376 (unspec:HI [(const_int 0)] UNSPEC_MMACH))])]
6378 "operands[4] = GEN_INT (FRV_BUILTIN_MMACHU);")
6380 (define_insn "*mmach"
6381 [(set (match_operand:DI 0 "even_acc_operand" "+b")
6382 (unspec:DI [(match_dup 0)
6383 (match_operand:SI 1 "fpr_operand" "f")
6384 (match_operand:SI 2 "fpr_operand" "f")
6385 (match_operand:HI 3 "accg_operand" "+B")
6386 (match_operand:SI 4 "const_int_operand" "n")]
6388 (set (match_dup 3) (unspec:HI [(const_int 0)] UNSPEC_MMACH))]
6392 switch (INTVAL (operands[4]))
6395 case FRV_BUILTIN_MMACHS: return \"mmachs %1, %2, %0\";
6396 case FRV_BUILTIN_MMACHU: return \"mmachu %1, %2, %0\";
6399 fatal_insn (\"Bad media insn, mmach\", insn);
6401 [(set_attr "length" "4")
6402 (set_attr "type" "mmach")])
6404 (define_insn "*cond_exec_mmach"
6406 (match_operator 0 "ccr_eqne_operator"
6407 [(match_operand 1 "cr_operand" "C")
6409 (parallel [(set (match_operand:DI 2 "even_acc_operand" "+b")
6410 (unspec:DI [(match_dup 2)
6411 (match_operand:SI 3 "fpr_operand" "f")
6412 (match_operand:SI 4 "fpr_operand" "f")
6413 (match_operand:HI 5 "accg_operand" "+B")
6414 (match_operand:SI 6 "const_int_operand" "n")]
6417 (unspec:HI [(const_int 0)] UNSPEC_MMACH))]))]
6421 switch (INTVAL (operands[6]))
6424 case FRV_BUILTIN_MMACHS: return \"cmmachs %3, %4, %2, %1, %e0\";
6425 case FRV_BUILTIN_MMACHU: return \"cmmachu %3, %4, %2, %1, %e0\";
6428 fatal_insn (\"Bad media insn, cond_exec_mmach\", insn);
6430 [(set_attr "length" "4")
6431 (set_attr "type" "mmach")])
6433 ;; Dual product-difference: type "mmrdh"
6435 (define_expand "mmrdhs"
6436 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6437 (unspec:DI [(match_dup 0)
6438 (match_operand:SI 1 "fpr_operand" "f")
6439 (match_operand:SI 2 "fpr_operand" "f")
6440 (match_operand:HI 3 "accg_operand" "+B")
6444 (unspec:HI [(const_int 0)] UNSPEC_MMRDH))])]
6446 "operands[4] = GEN_INT (FRV_BUILTIN_MMRDHS);")
6448 (define_expand "mmrdhu"
6449 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6450 (unspec:DI [(match_dup 0)
6451 (match_operand:SI 1 "fpr_operand" "f")
6452 (match_operand:SI 2 "fpr_operand" "f")
6453 (match_operand:HI 3 "accg_operand" "+B")
6457 (unspec:HI [(const_int 0)] UNSPEC_MMRDH))])]
6459 "operands[4] = GEN_INT (FRV_BUILTIN_MMRDHU);")
6461 (define_insn "*mmrdh"
6462 [(set (match_operand:DI 0 "even_acc_operand" "+b")
6463 (unspec:DI [(match_dup 0)
6464 (match_operand:SI 1 "fpr_operand" "f")
6465 (match_operand:SI 2 "fpr_operand" "f")
6466 (match_operand:HI 3 "accg_operand" "+B")
6467 (match_operand:SI 4 "const_int_operand" "n")]
6470 (unspec:HI [(const_int 0)] UNSPEC_MMRDH))]
6474 switch (INTVAL (operands[4]))
6477 case FRV_BUILTIN_MMRDHS: return \"mmrdhs %1, %2, %0\";
6478 case FRV_BUILTIN_MMRDHU: return \"mmrdhu %1, %2, %0\";
6481 fatal_insn (\"Bad media insn, mrdh\", insn);
6483 [(set_attr "length" "4")
6484 (set_attr "type" "mmrdh")])
6486 ;; Quad multiply (halfword): type "mqmulh"
6488 (define_expand "mqmulhs"
6489 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6490 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6491 (match_operand:DI 2 "even_fpr_operand" "h")
6494 (set (match_operand:V4QI 3 "accg_operand" "=B")
6495 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))])]
6497 "operands[4] = GEN_INT (FRV_BUILTIN_MQMULHS);")
6499 (define_expand "mqmulhu"
6500 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6501 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6502 (match_operand:DI 2 "even_fpr_operand" "h")
6505 (set (match_operand:V4QI 3 "accg_operand" "=B")
6506 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))])]
6508 "operands[4] = GEN_INT (FRV_BUILTIN_MQMULHU);")
6510 (define_insn "*mqmulh"
6511 [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6512 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6513 (match_operand:DI 2 "even_fpr_operand" "h")
6514 (match_operand:SI 3 "const_int_operand" "n")]
6516 (set (match_operand:V4QI 4 "accg_operand" "=B")
6517 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))]
6521 switch (INTVAL (operands[3]))
6524 case FRV_BUILTIN_MQMULHS: return \"mqmulhs %1, %2, %0\";
6525 case FRV_BUILTIN_MQMULHU: return \"mqmulhu %1, %2, %0\";
6528 fatal_insn (\"Bad media insn, mqmulh\", insn);
6530 [(set_attr "length" "4")
6531 (set_attr "type" "mqmulh")])
6533 (define_insn "*cond_exec_mqmulh"
6535 (match_operator 0 "ccr_eqne_operator"
6536 [(match_operand 1 "cr_operand" "C")
6538 (parallel [(set (match_operand:V4SI 2 "quad_acc_operand" "=A")
6539 (unspec:V4SI [(match_operand:DI 3 "even_fpr_operand" "h")
6540 (match_operand:DI 4 "even_fpr_operand" "h")
6541 (match_operand:SI 5 "const_int_operand" "n")]
6543 (set (match_operand:V4QI 6 "accg_operand" "=B")
6544 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))]))]
6548 switch (INTVAL (operands[5]))
6551 case FRV_BUILTIN_MQMULHS: return \"cmqmulhs %3, %4, %2, %1, %e0\";
6552 case FRV_BUILTIN_MQMULHU: return \"cmqmulhu %3, %4, %2, %1, %e0\";
6555 fatal_insn (\"Bad media insn, cond_exec_mqmulh\", insn);
6557 [(set_attr "length" "4")
6558 (set_attr "type" "mqmulh")])
6560 ;; Quad cross multiply (halfword): type "mqmulxh"
6562 (define_expand "mqmulxhs"
6563 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6564 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6565 (match_operand:DI 2 "even_fpr_operand" "h")
6568 (set (match_operand:V4QI 3 "accg_operand" "=B")
6569 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULXH))])]
6571 "operands[4] = GEN_INT (FRV_BUILTIN_MQMULXHS);")
6573 (define_expand "mqmulxhu"
6574 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6575 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6576 (match_operand:DI 2 "even_fpr_operand" "h")
6579 (set (match_operand:V4QI 3 "accg_operand" "=B")
6580 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULXH))])]
6582 "operands[4] = GEN_INT (FRV_BUILTIN_MQMULXHU);")
6584 (define_insn "*mqmulxh"
6585 [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6586 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6587 (match_operand:DI 2 "even_fpr_operand" "h")
6588 (match_operand:SI 3 "const_int_operand" "n")]
6590 (set (match_operand:V4QI 4 "accg_operand" "=B")
6591 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULXH))]
6595 switch (INTVAL (operands[3]))
6598 case FRV_BUILTIN_MQMULXHS: return \"mqmulxhs %1, %2, %0\";
6599 case FRV_BUILTIN_MQMULXHU: return \"mqmulxhu %1, %2, %0\";
6602 fatal_insn (\"Bad media insn, mqmulxh\", insn);
6604 [(set_attr "length" "4")
6605 (set_attr "type" "mqmulxh")])
6607 ;; Quad product-sum (halfword): type "mqmach"
6609 (define_expand "mqmachs"
6610 [(parallel [(set (match_operand:V4SI 0 "even_acc_operand" "+A")
6611 (unspec:V4SI [(match_dup 0)
6612 (match_operand:DI 1 "even_fpr_operand" "h")
6613 (match_operand:DI 2 "even_fpr_operand" "h")
6614 (match_operand:V4QI 3 "accg_operand" "+B")
6618 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))])]
6620 "operands[4] = GEN_INT (FRV_BUILTIN_MQMACHS);")
6622 (define_expand "mqmachu"
6623 [(parallel [(set (match_operand:V4SI 0 "even_acc_operand" "+A")
6624 (unspec:V4SI [(match_dup 0)
6625 (match_operand:DI 1 "even_fpr_operand" "h")
6626 (match_operand:DI 2 "even_fpr_operand" "h")
6627 (match_operand:V4QI 3 "accg_operand" "+B")
6631 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))])]
6633 "operands[4] = GEN_INT (FRV_BUILTIN_MQMACHU);")
6635 (define_insn "*mqmach"
6636 [(set (match_operand:V4SI 0 "even_acc_operand" "+A")
6637 (unspec:V4SI [(match_dup 0)
6638 (match_operand:DI 1 "even_fpr_operand" "h")
6639 (match_operand:DI 2 "even_fpr_operand" "h")
6640 (match_operand:V4QI 3 "accg_operand" "+B")
6641 (match_operand:SI 4 "const_int_operand" "n")]
6644 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))]
6648 switch (INTVAL (operands[4]))
6651 case FRV_BUILTIN_MQMACHS: return \"mqmachs %1, %2, %0\";
6652 case FRV_BUILTIN_MQMACHU: return \"mqmachu %1, %2, %0\";
6655 fatal_insn (\"Bad media insn, mqmach\", insn);
6657 [(set_attr "length" "4")
6658 (set_attr "type" "mqmach")])
6660 (define_insn "*cond_exec_mqmach"
6662 (match_operator 0 "ccr_eqne_operator"
6663 [(match_operand 1 "cr_operand" "C")
6665 (parallel [(set (match_operand:V4SI 2 "even_acc_operand" "+A")
6666 (unspec:V4SI [(match_dup 2)
6667 (match_operand:DI 3 "even_fpr_operand" "h")
6668 (match_operand:DI 4 "even_fpr_operand" "h")
6669 (match_operand:V4QI 5 "accg_operand" "+B")
6670 (match_operand:SI 6 "const_int_operand" "n")]
6673 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))]))]
6677 switch (INTVAL (operands[6]))
6680 case FRV_BUILTIN_MQMACHS: return \"cmqmachs %3, %4, %2, %1, %e0\";
6681 case FRV_BUILTIN_MQMACHU: return \"cmqmachu %3, %4, %2, %1, %e0\";
6684 fatal_insn (\"Bad media insn, cond_exec_mqmach\", insn);
6686 [(set_attr "length" "4")
6687 (set_attr "type" "mqmach")])
6689 ;; Dual complex number product-sum (halfword)
6691 (define_expand "mcpxrs"
6692 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
6693 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6694 (match_operand:SI 2 "fpr_operand" "f")
6697 (set (match_operand:QI 3 "accg_operand" "=B")
6698 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
6700 "operands[4] = GEN_INT (FRV_BUILTIN_MCPXRS);")
6702 (define_expand "mcpxru"
6703 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
6704 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6705 (match_operand:SI 2 "fpr_operand" "f")
6708 (set (match_operand:QI 3 "accg_operand" "=B")
6709 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
6711 "operands[4] = GEN_INT (FRV_BUILTIN_MCPXRU);")
6713 (define_expand "mcpxis"
6714 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
6715 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6716 (match_operand:SI 2 "fpr_operand" "f")
6719 (set (match_operand:QI 3 "accg_operand" "=B")
6720 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
6722 "operands[4] = GEN_INT (FRV_BUILTIN_MCPXIS);")
6724 (define_expand "mcpxiu"
6725 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
6726 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6727 (match_operand:SI 2 "fpr_operand" "f")
6730 (set (match_operand:QI 3 "accg_operand" "=B")
6731 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
6733 "operands[4] = GEN_INT (FRV_BUILTIN_MCPXIU);")
6735 (define_insn "*mcpx"
6736 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
6737 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6738 (match_operand:SI 2 "fpr_operand" "f")
6739 (match_operand:SI 3 "const_int_operand" "n")]
6741 (set (match_operand:QI 4 "accg_operand" "=B")
6742 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
6746 switch (INTVAL (operands[3]))
6749 case FRV_BUILTIN_MCPXRS: return \"mcpxrs %1, %2, %0\";
6750 case FRV_BUILTIN_MCPXRU: return \"mcpxru %1, %2, %0\";
6751 case FRV_BUILTIN_MCPXIS: return \"mcpxis %1, %2, %0\";
6752 case FRV_BUILTIN_MCPXIU: return \"mcpxiu %1, %2, %0\";
6755 fatal_insn (\"Bad media insn, mcpx\", insn);
6757 [(set_attr "length" "4")
6758 (set_attr "type" "mcpx")])
6760 (define_insn "*cond_exec_mcpx"
6762 (match_operator 0 "ccr_eqne_operator"
6763 [(match_operand 1 "cr_operand" "C")
6765 (parallel [(set (match_operand:SI 2 "acc_operand" "=a")
6766 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
6767 (match_operand:SI 4 "fpr_operand" "f")
6768 (match_operand:SI 5 "const_int_operand" "n")]
6770 (set (match_operand:QI 6 "accg_operand" "=B")
6771 (unspec:QI [(const_int 0)] UNSPEC_MCPX))]))]
6775 switch (INTVAL (operands[5]))
6778 case FRV_BUILTIN_MCPXRS: return \"cmcpxrs %3, %4, %2, %1, %e0\";
6779 case FRV_BUILTIN_MCPXRU: return \"cmcpxru %3, %4, %2, %1, %e0\";
6780 case FRV_BUILTIN_MCPXIS: return \"cmcpxis %3, %4, %2, %1, %e0\";
6781 case FRV_BUILTIN_MCPXIU: return \"cmcpxiu %3, %4, %2, %1, %e0\";
6784 fatal_insn (\"Bad media insn, cond_exec_mcpx\", insn);
6786 [(set_attr "length" "4")
6787 (set_attr "type" "mcpx")])
6789 ;; Quad complex number product-sum (halfword): type "mqcpx"
6791 (define_expand "mqcpxrs"
6792 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6793 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
6794 (match_operand:DI 2 "fpr_operand" "f")
6797 (set (match_operand:HI 3 "accg_operand" "=B")
6798 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
6800 "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXRS);")
6802 (define_expand "mqcpxru"
6803 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6804 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
6805 (match_operand:DI 2 "fpr_operand" "f")
6808 (set (match_operand:HI 3 "accg_operand" "=B")
6809 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
6811 "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXRU);")
6813 (define_expand "mqcpxis"
6814 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6815 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
6816 (match_operand:DI 2 "fpr_operand" "f")
6819 (set (match_operand:HI 3 "accg_operand" "=B")
6820 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
6822 "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXIS);")
6824 (define_expand "mqcpxiu"
6825 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6826 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
6827 (match_operand:DI 2 "fpr_operand" "f")
6830 (set (match_operand:HI 3 "accg_operand" "=B")
6831 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
6833 "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXIU);")
6835 (define_insn "*mqcpx"
6836 [(set (match_operand:DI 0 "even_acc_operand" "=b")
6837 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
6838 (match_operand:DI 2 "fpr_operand" "f")
6839 (match_operand:SI 3 "const_int_operand" "n")]
6841 (set (match_operand:HI 4 "accg_operand" "=B")
6842 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))]
6846 switch (INTVAL (operands[3]))
6849 case FRV_BUILTIN_MQCPXRS: return \"mqcpxrs %1, %2, %0\";
6850 case FRV_BUILTIN_MQCPXRU: return \"mqcpxru %1, %2, %0\";
6851 case FRV_BUILTIN_MQCPXIS: return \"mqcpxis %1, %2, %0\";
6852 case FRV_BUILTIN_MQCPXIU: return \"mqcpxiu %1, %2, %0\";
6855 fatal_insn (\"Bad media insn, mqcpx\", insn);
6857 [(set_attr "length" "4")
6858 (set_attr "type" "mqcpx")])
6862 (define_expand "mcut"
6863 [(set (match_operand:SI 0 "fpr_operand" "=f")
6864 (unspec:SI [(match_operand:SI 1 "acc_operand" "a")
6865 (match_operand:SI 2 "fpr_or_int6_operand" "fI")
6866 (match_operand:QI 3 "accg_operand" "B")
6870 "operands[4] = GEN_INT (FRV_BUILTIN_MCUT);")
6872 (define_expand "mcutss"
6873 [(set (match_operand:SI 0 "fpr_operand" "=f")
6874 (unspec:SI [(match_operand:SI 1 "acc_operand" "a")
6875 (match_operand:SI 2 "fpr_or_int6_operand" "fI")
6876 (match_operand:QI 3 "accg_operand" "B")
6880 "operands[4] = GEN_INT (FRV_BUILTIN_MCUTSS);")
6882 (define_insn "*mcut"
6883 [(set (match_operand:SI 0 "fpr_operand" "=f")
6884 (unspec:SI [(match_operand:SI 1 "acc_operand" "a")
6885 (match_operand:SI 2 "fpr_or_int6_operand" "fI")
6886 (match_operand:QI 3 "accg_operand" "B")
6887 (match_operand:SI 4 "const_int_operand" "n")]
6892 switch (INTVAL (operands[4]))
6895 case FRV_BUILTIN_MCUT: return \"mcut%i2 %1, %2, %0\";
6896 case FRV_BUILTIN_MCUTSS: return \"mcutss%i2 %1, %2, %0\";
6899 fatal_insn (\"Bad media insn, mcut\", insn);
6901 [(set_attr "length" "4")
6902 (set_attr "type" "mcut")])
6904 ;; Accumulator read: type "mrdacc"
6906 (define_insn "mrdacc"
6907 [(set (match_operand:SI 0 "fpr_operand" "=f")
6908 (unspec:SI [(match_operand:SI 1 "acc_operand" "a")] UNSPEC_MRDACC))]
6911 [(set_attr "length" "4")
6912 (set_attr "type" "mrdacc")])
6914 (define_insn "mrdaccg"
6915 [(set (match_operand:SI 0 "fpr_operand" "=f")
6916 (unspec:SI [(match_operand:QI 1 "accg_operand" "B")] UNSPEC_MRDACCG))]
6919 [(set_attr "length" "4")
6920 (set_attr "type" "mrdacc")])
6922 ;; Accumulator write: type "mwtacc"
6924 (define_insn "mwtacc"
6925 [(set (match_operand:SI 0 "acc_operand" "=a")
6926 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MWTACC))]
6929 [(set_attr "length" "4")
6930 (set_attr "type" "mwtacc")])
6932 (define_insn "mwtaccg"
6933 [(set (match_operand:QI 0 "accg_operand" "=B")
6934 (unspec:QI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MWTACCG))]
6937 [(set_attr "length" "4")
6938 (set_attr "type" "mwtacc")])
6940 ;; Trap: This one executes on the control unit, not the media units.
6942 (define_insn "mtrap"
6943 [(unspec_volatile [(const_int 0)] UNSPEC_MTRAP)]
6946 [(set_attr "length" "4")
6947 (set_attr "type" "trap")])
6949 ;; Clear single accumulator: type "mclracc"
6951 (define_insn "mclracc_internal"
6952 [(set (match_operand:SI 0 "acc_operand" "=a")
6953 (unspec:SI [(const_int 0)] UNSPEC_MCLRACC))
6954 (set (match_operand:QI 1 "accg_operand" "=B")
6955 (unspec:QI [(const_int 0)] UNSPEC_MCLRACC))]
6958 [(set_attr "length" "4")
6959 (set_attr "type" "mclracc")])
6961 (define_expand "mclracc"
6962 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
6963 (unspec:SI [(const_int 0)] UNSPEC_MCLRACC))
6965 (unspec:QI [(const_int 0)] UNSPEC_MCLRACC))])]
6969 if (GET_CODE (operands[0]) != REG || !ACC_P (REGNO (operands[0])))
6972 operands[1] = frv_matching_accg_for_acc (operands[0]);
6975 ;; Clear all accumulators: type "mclracca"
6977 (define_insn "mclracca8_internal"
6978 [(set (match_operand:V4SI 0 "quad_acc_operand" "=b")
6979 (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
6980 (set (match_operand:V4SI 1 "quad_acc_operand" "=b")
6981 (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
6982 (set (match_operand:V4QI 2 "accg_operand" "=B")
6983 (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))
6984 (set (match_operand:V4QI 3 "accg_operand" "=B")
6985 (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))]
6986 "TARGET_MEDIA && TARGET_ACC_8"
6988 [(set_attr "length" "4")
6989 (set_attr "type" "mclracca")])
6991 (define_insn "mclracca4_internal"
6992 [(set (match_operand:V4SI 0 "quad_acc_operand" "=b")
6993 (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
6994 (set (match_operand:V4QI 1 "accg_operand" "=B")
6995 (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))]
6996 "TARGET_MEDIA && TARGET_ACC_4"
6998 [(set_attr "length" "4")
6999 (set_attr "type" "mclracca")])
7001 (define_expand "mclracca8"
7002 [(parallel [(set (match_dup 0) (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7003 (set (match_dup 1) (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7004 (set (match_dup 2) (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))
7005 (set (match_dup 3) (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))])]
7006 "TARGET_MEDIA && TARGET_ACC_8"
7009 operands[0] = gen_rtx_REG (V4SImode, ACC_FIRST);
7010 operands[1] = gen_rtx_REG (V4SImode, ACC_FIRST + 4);
7011 operands[2] = gen_rtx_REG (V4QImode, ACCG_FIRST);
7012 operands[3] = gen_rtx_REG (V4QImode, ACCG_FIRST + 4);
7015 (define_expand "mclracca4"
7016 [(parallel [(set (match_dup 0) (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7017 (set (match_dup 1) (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))])]
7018 "TARGET_MEDIA && TARGET_ACC_4"
7021 operands[0] = gen_rtx_REG (V4SImode, ACC_FIRST);
7022 operands[1] = gen_rtx_REG (V4QImode, ACCG_FIRST);
7025 (define_insn "mcop1"
7026 [(set (match_operand:SI 0 "fpr_operand" "=f")
7027 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7028 (match_operand:SI 2 "fpr_operand" "f")] UNSPEC_MCOP1))]
7031 [(set_attr "length" "4")
7032 ;; What is the class of the insn ???
7033 (set_attr "type" "multi")])
7035 (define_insn "mcop2"
7036 [(set (match_operand:SI 0 "fpr_operand" "=f")
7037 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7038 (match_operand:SI 2 "fpr_operand" "f")] UNSPEC_MCOP2))]
7041 [(set_attr "length" "4")
7042 ;; What is the class of the insn ???
7043 (set_attr "type" "multi")])
7045 (define_insn "*mdunpackh_internal"
7046 [(set (match_operand:V4SI 0 "quad_fpr_operand" "=x")
7047 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")]
7048 UNSPEC_MDUNPACKH_INTERNAL))]
7051 [(set_attr "length" "4")
7052 (set_attr "type" "mdunpackh")])
7054 (define_insn_and_split "mdunpackh"
7055 [(set (match_operand:V4SI 0 "memory_operand" "=o")
7056 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")]
7058 (clobber (match_scratch:V4SI 2 "=x"))]
7063 (unspec:V4SI [(match_dup 1)] UNSPEC_MDUNPACKH_INTERNAL))
7070 operands[3] = change_address (operands[0], DImode, NULL_RTX);
7071 operands[4] = gen_rtx_REG (DImode, REGNO (operands[2]));
7072 operands[5] = frv_index_memory (operands[0], DImode, 1);
7073 operands[6] = gen_rtx_REG (DImode, REGNO (operands[2])+2);
7075 [(set_attr "length" "20")
7076 (set_attr "type" "multi")])
7078 (define_insn "*mbtohe_internal"
7079 [(set (match_operand:V4SI 0 "quad_fpr_operand" "=x")
7080 (unspec:V4SI [(match_operand:SI 1 "fpr_operand" "f")]
7081 UNSPEC_MBTOHE_INTERNAL))]
7084 [(set_attr "length" "4")
7085 (set_attr "type" "mbhconve")])
7087 (define_insn_and_split "mbtohe"
7088 [(set (match_operand:V4SI 0 "memory_operand" "=o")
7089 (unspec:V4SI [(match_operand:SI 1 "fpr_operand" "f")]
7091 (clobber (match_scratch:V4SI 2 "=x"))]
7096 (unspec:V4SI [(match_dup 1)] UNSPEC_MBTOHE_INTERNAL))
7103 operands[3] = change_address (operands[0], DImode, NULL_RTX);
7104 operands[4] = gen_rtx_REG (DImode, REGNO (operands[2]));
7105 operands[5] = frv_index_memory (operands[0], DImode, 1);
7106 operands[6] = gen_rtx_REG (DImode, REGNO (operands[2])+2);
7108 [(set_attr "length" "20")
7109 (set_attr "type" "multi")])
7111 ;; Quad product-sum (halfword) instructions only found on the FR400.
7114 (define_expand "mqxmachs"
7115 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7116 (unspec:V4SI [(match_dup 0)
7117 (match_operand:DI 1 "even_fpr_operand" "")
7118 (match_operand:DI 2 "even_fpr_operand" "")
7119 (match_operand:V4QI 3 "accg_operand" "")
7123 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))])]
7125 "operands[4] = GEN_INT (FRV_BUILTIN_MQXMACHS);")
7127 (define_expand "mqxmacxhs"
7128 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7129 (unspec:V4SI [(match_dup 0)
7130 (match_operand:DI 1 "even_fpr_operand" "")
7131 (match_operand:DI 2 "even_fpr_operand" "")
7132 (match_operand:V4QI 3 "accg_operand" "")
7136 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))])]
7138 "operands[4] = GEN_INT (FRV_BUILTIN_MQXMACXHS);")
7140 (define_expand "mqmacxhs"
7141 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7142 (unspec:V4SI [(match_dup 0)
7143 (match_operand:DI 1 "even_fpr_operand" "")
7144 (match_operand:DI 2 "even_fpr_operand" "")
7145 (match_operand:V4QI 3 "accg_operand" "")
7149 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))])]
7151 "operands[4] = GEN_INT (FRV_BUILTIN_MQMACXHS);")
7153 (define_insn "*mqmach2"
7154 [(set (match_operand:V4SI 0 "quad_acc_operand" "+A")
7155 (unspec:V4SI [(match_dup 0)
7156 (match_operand:DI 1 "even_fpr_operand" "h")
7157 (match_operand:DI 2 "even_fpr_operand" "h")
7158 (match_operand:V4QI 3 "accg_operand" "+B")
7159 (match_operand:SI 4 "const_int_operand" "n")]
7162 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))]
7166 switch (INTVAL (operands[4]))
7169 case FRV_BUILTIN_MQXMACHS: return \"mqxmachs %1, %2, %0\";
7170 case FRV_BUILTIN_MQXMACXHS: return \"mqxmacxhs %1, %2, %0\";
7171 case FRV_BUILTIN_MQMACXHS: return \"mqmacxhs %1, %2, %0\";
7174 fatal_insn (\"Bad media insn, mqmach2\", insn);
7176 [(set_attr "length" "4")
7177 (set_attr "type" "mqmach")])
7179 ;; Accumulator addition/subtraction: type "maddacc"
7181 (define_expand "maddaccs"
7182 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "")
7183 (unspec:DI [(match_dup 0)
7184 (match_operand:DI 1 "even_acc_operand" "")]
7186 (set (match_operand:HI 2 "accg_operand" "")
7187 (unspec:HI [(match_dup 2)
7188 (match_operand:HI 3 "accg_operand" "")
7192 "operands[4] = GEN_INT (FRV_BUILTIN_MADDACCS);")
7194 (define_expand "msubaccs"
7195 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "")
7196 (unspec:DI [(match_dup 0)
7197 (match_operand:DI 1 "even_acc_operand" "")]
7199 (set (match_operand:HI 2 "accg_operand" "")
7200 (unspec:HI [(match_dup 2)
7201 (match_operand:HI 3 "accg_operand" "")
7205 "operands[4] = GEN_INT (FRV_BUILTIN_MSUBACCS);")
7207 (define_expand "masaccs"
7208 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "")
7209 (unspec:DI [(match_dup 0)
7210 (match_operand:DI 1 "even_acc_operand" "")]
7212 (set (match_operand:HI 2 "accg_operand" "")
7213 (unspec:HI [(match_dup 2)
7214 (match_operand:HI 3 "accg_operand" "")
7218 "operands[4] = GEN_INT (FRV_BUILTIN_MASACCS);")
7220 (define_insn "*maddacc"
7221 [(set (match_operand:DI 0 "even_acc_operand" "+b")
7222 (unspec:DI [(match_dup 0)
7223 (match_operand:DI 1 "even_acc_operand" "b")]
7225 (set (match_operand:HI 2 "accg_operand" "+B")
7226 (unspec:HI [(match_dup 2)
7227 (match_operand:HI 3 "accg_operand" "B")
7228 (match_operand:SI 4 "const_int_operand" "n")]
7233 switch (INTVAL (operands[4]))
7236 case FRV_BUILTIN_MADDACCS: return \"maddaccs %1, %0\";
7237 case FRV_BUILTIN_MSUBACCS: return \"msubaccs %1, %0\";
7238 case FRV_BUILTIN_MASACCS: return \"masaccs %1, %0\";
7241 fatal_insn (\"Bad media insn, maddacc\", insn);
7243 [(set_attr "length" "4")
7244 (set_attr "type" "maddacc")])
7246 ;; Dual accumulator addition/subtraction: type "mdaddacc"
7248 (define_expand "mdaddaccs"
7249 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7250 (unspec:V4SI [(match_dup 0)
7251 (match_operand:V4SI 1 "quad_acc_operand" "")]
7253 (set (match_operand:V4QI 2 "accg_operand" "")
7254 (unspec:V4QI [(match_dup 2)
7255 (match_operand:V4QI 3 "accg_operand" "")
7257 UNSPEC_MDADDACC))])]
7259 "operands[4] = GEN_INT (FRV_BUILTIN_MDADDACCS);")
7261 (define_expand "mdsubaccs"
7262 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7263 (unspec:V4SI [(match_dup 0)
7264 (match_operand:V4SI 1 "quad_acc_operand" "")]
7266 (set (match_operand:V4QI 2 "accg_operand" "")
7267 (unspec:V4QI [(match_dup 2)
7268 (match_operand:V4QI 3 "accg_operand" "")
7270 UNSPEC_MDADDACC))])]
7272 "operands[4] = GEN_INT (FRV_BUILTIN_MDSUBACCS);")
7274 (define_expand "mdasaccs"
7275 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7276 (unspec:V4SI [(match_dup 0)
7277 (match_operand:V4SI 1 "quad_acc_operand" "")]
7279 (set (match_operand:V4QI 2 "accg_operand" "")
7280 (unspec:V4QI [(match_dup 2)
7281 (match_operand:V4QI 3 "accg_operand" "")
7283 UNSPEC_MDADDACC))])]
7285 "operands[4] = GEN_INT (FRV_BUILTIN_MDASACCS);")
7287 (define_insn "*mdaddacc"
7288 [(set (match_operand:V4SI 0 "quad_acc_operand" "+A")
7289 (unspec:V4SI [(match_dup 0)
7290 (match_operand:V4SI 1 "quad_acc_operand" "A")]
7292 (set (match_operand:V4QI 2 "accg_operand" "+B")
7293 (unspec:V4QI [(match_dup 2)
7294 (match_operand:V4QI 3 "accg_operand" "B")
7295 (match_operand:SI 4 "const_int_operand" "n")]
7300 switch (INTVAL (operands[4]))
7303 case FRV_BUILTIN_MDADDACCS: return \"mdaddaccs %1, %0\";
7304 case FRV_BUILTIN_MDSUBACCS: return \"mdsubaccs %1, %0\";
7305 case FRV_BUILTIN_MDASACCS: return \"mdasaccs %1, %0\";
7308 fatal_insn (\"Bad media insn, mdaddacc\", insn);
7310 [(set_attr "length" "4")
7311 (set_attr "type" "mdaddacc")])
7313 ;; Dual absolute (halfword): type "mabsh"
7315 (define_insn "mabshs"
7316 [(set (match_operand:SI 0 "fpr_operand" "=f")
7317 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MABSHS))]
7320 [(set_attr "length" "4")
7321 (set_attr "type" "mabsh")])
7323 ;; Dual rotate: type "mdrot"
7325 (define_insn "mdrotli"
7326 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7327 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7328 (match_operand:SI 2 "uint5_operand" "I")]
7331 "mdrotli %1, %2, %0"
7332 [(set_attr "length" "4")
7333 (set_attr "type" "mdrot")])
7335 ;; Dual coupling (concatenation): type "mcpl"
7337 (define_insn "mcplhi"
7338 [(set (match_operand:SI 0 "fpr_operand" "=f")
7339 (unspec:SI [(match_operand:DI 1 "fpr_operand" "h")
7340 (match_operand:SI 2 "uint4_operand" "I")]
7344 [(set_attr "length" "4")
7345 (set_attr "type" "mcpl")])
7347 (define_insn "mcpli"
7348 [(set (match_operand:SI 0 "fpr_operand" "=f")
7349 (unspec:SI [(match_operand:DI 1 "fpr_operand" "h")
7350 (match_operand:SI 2 "uint5_operand" "I")]
7354 [(set_attr "length" "4")
7355 (set_attr "type" "mcpl")])
7357 ;; Dual cut: type "mdcut"
7359 (define_insn "mdcutssi"
7360 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7361 (unspec:DI [(match_operand:DI 1 "even_acc_operand" "b")
7362 (match_operand:SI 2 "int6_operand" "I")
7363 (match_operand:HI 3 "accg_operand" "B")]
7366 "mdcutssi %1, %2, %0"
7367 [(set_attr "length" "4")
7368 (set_attr "type" "mdcut")])
7370 ;; Quad saturate (halfword): type "mqsath"
7372 (define_insn "mqsaths"
7373 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7374 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7375 (match_operand:DI 2 "even_fpr_operand" "h")]
7378 "mqsaths %1, %2, %0"
7379 [(set_attr "length" "4")
7380 (set_attr "type" "mqsath")])
7382 ;; Set hi/lo instrctions: type "mset"
7384 (define_insn "mhsetlos"
7385 [(set (match_operand:SI 0 "fpr_operand" "=f")
7386 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7387 (match_operand:SI 2 "int12_operand" "NOP")]
7391 [(set_attr "length" "4")
7392 (set_attr "type" "mset")])
7394 (define_insn "mhsetloh"
7395 [(set (match_operand:SI 0 "fpr_operand" "=f")
7396 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7397 (match_operand:SI 2 "int5_operand" "I")]
7401 [(set_attr "length" "4")
7402 (set_attr "type" "mset")])
7404 (define_insn "mhsethis"
7405 [(set (match_operand:SI 0 "fpr_operand" "=f")
7406 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7407 (match_operand:SI 2 "int12_operand" "NOP")]
7411 [(set_attr "length" "4")
7412 (set_attr "type" "mset")])
7414 (define_insn "mhsethih"
7415 [(set (match_operand:SI 0 "fpr_operand" "=f")
7416 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7417 (match_operand:SI 2 "int5_operand" "I")]
7421 [(set_attr "length" "4")
7422 (set_attr "type" "mset")])
7424 (define_insn "mhdsets"
7425 [(set (match_operand:SI 0 "fpr_operand" "=f")
7426 (unspec:SI [(match_operand:SI 1 "int12_operand" "NOP")]
7430 [(set_attr "length" "4")
7431 (set_attr "type" "mset")])
7433 (define_insn "mhdseth"
7434 [(set (match_operand:SI 0 "fpr_operand" "=f")
7435 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7436 (match_operand:SI 2 "int5_operand" "I")]
7440 [(set_attr "length" "4")
7441 (set_attr "type" "mset")])