| blob | a9f07a239bd21f3885ce2fada5830955064d3bd5 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
60 enum upper_128bits_state
61 {
64 used /* Used or referenced. */
65 };
68 {
69 /* State of the upper 128bits of any AVX registers at exit. */
71 /* If the upper 128bits of any AVX registers are referenced. */
73 /* Number of vzerouppers in this block. */
75 /* TRUE if block has been processed. */
77 /* TRUE if block has been rescanned. */
81 #define BLOCK_INFO(B) ((block_info) (B)->aux)
83 enum call_avx256_state
84 {
85 /* Callee returns 256bit AVX register. */
87 /* Callee returns and passes 256bit AVX register. */
88 callee_return_pass_avx256,
89 /* Callee passes 256bit AVX register. */
90 callee_pass_avx256,
91 /* Callee doesn't return nor passe 256bit AVX register, or no
92 256bit AVX register in function return. */
93 call_no_avx256,
94 /* vzeroupper intrinsic. */
95 vzeroupper_intrinsic
96 };
98 /* Check if a 256bit AVX register is referenced in stores. */
100 static void
102 {
108 {
112 }
113 }
115 /* Helper function for move_or_delete_vzeroupper_1. Look for vzeroupper
116 in basic block BB. Delete it if upper 128bit AVX registers are
117 unused. If it isn't deleted, move it to just before a jump insn.
119 UPPER_128BITS_LIVE is TRUE if the upper 128bits of any AVX registers
120 are live at entry. */
122 static void
125 {
128 rtx pat;
137 /* BB_END changes when it is deleted. */
141 {
147 /* Move vzeroupper before jump/call. */
149 {
154 {
156 {
161 }
164 }
167 }
171 /* Check insn for vzeroupper intrinsic. */
174 {
176 {
177 /* Found vzeroupper intrinsic. */
180 }
181 }
182 else
183 {
184 /* Check insn for vzeroall intrinsic. */
188 {
191 /* Delete pending vzeroupper insertion. */
193 {
194 count--;
197 }
198 }
200 {
201 /* No need to call note_stores if the upper 128bits of
202 AVX registers are never referenced. */
206 }
208 }
210 /* Process vzeroupper intrinsic. */
211 count++;
215 {
216 /* Since the upper 128bits are cleared, callee must not pass
217 256bit AVX register. We only need to check if callee
218 returns 256bit AVX register. */
222 /* Remove unnecessary vzeroupper since upper 128bits are
223 cleared. */
225 {
228 }
229 count--;
231 }
232 else
233 {
234 /* Set state to UNUSED if callee doesn't return 256bit AVX
235 register. */
241 {
242 /* Must remove vzeroupper since callee passes in 256bit
243 AVX register. */
245 {
248 }
249 count--;
251 }
252 else
254 }
255 }
260 {
261 /* The upper 128bits of AVX registers are never referenced if
262 REFERENCED isn't updated. */
267 }
272 }
274 /* Helper function for move_or_delete_vzeroupper. Process vzeroupper
275 in BLOCK and its predecessor blocks recursively. */
277 static void
279 {
280 edge e;
281 edge_iterator ei;
295 /* Process all predecessor edges of this block. */
297 {
302 {
312 }
313 }
315 /* If state of any predecessor edges is unknown, we need to rescan. */
319 /* Process this block. */
321 }
323 /* Helper function for move_or_delete_vzeroupper. Rescan vzeroupper
324 in BLOCK and its predecessor blocks recursively. */
326 static void
328 {
329 edge e;
330 edge_iterator ei;
344 /* Rescan all predecessor edges of this block. */
346 {
350 /* For rescan, UKKNOWN state is treated as UNUSED. */
353 }
355 /* Rescan this block only if there are vzerouppers or the upper
356 128bits of AVX registers are referenced. */
359 {
365 }
366 else
368 }
370 /* Go through the instruction stream looking for vzeroupper. Delete
371 it if upper 128bit AVX registers are unused. If it isn't deleted,
372 move it to just before a jump insn. */
374 static void
376 {
377 edge e;
378 edge_iterator ei;
379 basic_block bb;
382 /* Set up block info for each basic block. */
385 /* Process successor blocks of all entry points. */
390 {
396 }
398 /* Process all basic blocks. */
403 {
406 }
408 /* Rescan all basic blocks if needed. */
410 {
416 }
419 }
423 #ifndef CHECK_STACK_LIMIT
424 #define CHECK_STACK_LIMIT (-1)
425 #endif
427 /* Return index of given mode in mult and division cost tables. */
428 #define MODE_INDEX(mode) \
429 ((mode) == QImode ? 0 \
430 : (mode) == HImode ? 1 \
431 : (mode) == SImode ? 2 \
432 : (mode) == DImode ? 3 \
433 : 4)
435 /* Processor costs (relative to an add) */
436 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
437 #define COSTS_N_BYTES(N) ((N) * 2)
439 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
441 const
464 in QImode, HImode and SImode.
465 Relative to reg-reg move (2). */
469 in SFmode, DFmode and XFmode */
471 in SFmode, DFmode and XFmode */
474 in SImode and DImode */
476 in SImode and DImode */
479 in SImode, DImode and TImode */
481 in SImode, DImode and TImode */
509 };
511 /* Processor costs (relative to an add) */
512 static const
535 in QImode, HImode and SImode.
536 Relative to reg-reg move (2). */
540 in SFmode, DFmode and XFmode */
542 in SFmode, DFmode and XFmode */
545 in SImode and DImode */
547 in SImode and DImode */
550 in SImode, DImode and TImode */
552 in SImode, DImode and TImode */
566 DUMMY_STRINGOP_ALGS},
568 DUMMY_STRINGOP_ALGS},
580 };
582 static const
605 in QImode, HImode and SImode.
606 Relative to reg-reg move (2). */
610 in SFmode, DFmode and XFmode */
612 in SFmode, DFmode and XFmode */
615 in SImode and DImode */
617 in SImode and DImode */
620 in SImode, DImode and TImode */
622 in SImode, DImode and TImode */
625 shared for code and data, so 4kB is
626 not really precise. */
638 DUMMY_STRINGOP_ALGS},
640 DUMMY_STRINGOP_ALGS},
652 };
654 static const
677 in QImode, HImode and SImode.
678 Relative to reg-reg move (2). */
682 in SFmode, DFmode and XFmode */
684 in SFmode, DFmode and XFmode */
687 in SImode and DImode */
689 in SImode and DImode */
692 in SImode, DImode and TImode */
694 in SImode, DImode and TImode */
708 DUMMY_STRINGOP_ALGS},
710 DUMMY_STRINGOP_ALGS},
722 };
724 static const
747 in QImode, HImode and SImode.
748 Relative to reg-reg move (2). */
752 in SFmode, DFmode and XFmode */
754 in SFmode, DFmode and XFmode */
757 in SImode and DImode */
759 in SImode and DImode */
762 in SImode, DImode and TImode */
764 in SImode, DImode and TImode */
777 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
778 (we ensure the alignment). For small blocks inline loop is still a
779 noticeable win, for bigger blocks either rep movsl or rep movsb is
780 way to go. Rep movsb has apparently more expensive startup time in CPU,
781 but after 4K the difference is down in the noise. */
784 DUMMY_STRINGOP_ALGS},
787 DUMMY_STRINGOP_ALGS},
799 };
801 static const
824 in QImode, HImode and SImode.
825 Relative to reg-reg move (2). */
829 in SFmode, DFmode and XFmode */
831 in SFmode, DFmode and XFmode */
835 in SImode and DImode */
837 in SImode and DImode */
840 in SImode, DImode and TImode */
842 in SImode, DImode and TImode */
856 DUMMY_STRINGOP_ALGS},
858 DUMMY_STRINGOP_ALGS},
870 };
872 static const
895 in QImode, HImode and SImode.
896 Relative to reg-reg move (2). */
900 in SFmode, DFmode and XFmode */
902 in SFmode, DFmode and XFmode */
905 in SImode and DImode */
907 in SImode and DImode */
910 in SImode, DImode and TImode */
912 in SImode, DImode and TImode */
916 have integrated l2 cache, but
917 optimizing for k6 is not important
918 enough to worry about that. */
929 DUMMY_STRINGOP_ALGS},
931 DUMMY_STRINGOP_ALGS},
943 };
945 static const
968 in QImode, HImode and SImode.
969 Relative to reg-reg move (2). */
973 in SFmode, DFmode and XFmode */
975 in SFmode, DFmode and XFmode */
978 in SImode and DImode */
980 in SImode and DImode */
983 in SImode, DImode and TImode */
985 in SImode, DImode and TImode */
998 /* For some reason, Athlon deals better with REP prefix (relative to loops)
999 compared to K8. Alignment becomes important after 8 bytes for memcpy and
1000 128 bytes for memset. */
1002 DUMMY_STRINGOP_ALGS},
1004 DUMMY_STRINGOP_ALGS},
1016 };
1018 static const
1041 in QImode, HImode and SImode.
1042 Relative to reg-reg move (2). */
1046 in SFmode, DFmode and XFmode */
1048 in SFmode, DFmode and XFmode */
1051 in SImode and DImode */
1053 in SImode and DImode */
1056 in SImode, DImode and TImode */
1058 in SImode, DImode and TImode */
1063 /* New AMD processors never drop prefetches; if they cannot be performed
1064 immediately, they are queued. We set number of simultaneous prefetches
1065 to a large constant to reflect this (it probably is not a good idea not
1066 to limit number of prefetches at all, as their execution also takes some
1067 time). */
1076 /* K8 has optimized REP instruction for medium sized blocks, but for very
1077 small blocks it is better to use loop. For large blocks, libcall can
1078 do nontemporary accesses and beat inline considerably. */
1095 };
1119 in QImode, HImode and SImode.
1120 Relative to reg-reg move (2). */
1124 in SFmode, DFmode and XFmode */
1126 in SFmode, DFmode and XFmode */
1129 in SImode and DImode */
1131 in SImode and DImode */
1134 in SImode, DImode and TImode */
1136 in SImode, DImode and TImode */
1138 /* On K8:
1139 MOVD reg64, xmmreg Double FSTORE 4
1140 MOVD reg32, xmmreg Double FSTORE 4
1141 On AMDFAM10:
1142 MOVD reg64, xmmreg Double FADD 3
1143 1/1 1/1
1144 MOVD reg32, xmmreg Double FADD 3
1145 1/1 1/1 */
1149 /* New AMD processors never drop prefetches; if they cannot be performed
1150 immediately, they are queued. We set number of simultaneous prefetches
1151 to a large constant to reflect this (it probably is not a good idea not
1152 to limit number of prefetches at all, as their execution also takes some
1153 time). */
1163 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
1164 very small blocks it is better to use loop. For large blocks, libcall can
1165 do nontemporary accesses and beat inline considerably. */
1182 };
1206 in QImode, HImode and SImode.
1207 Relative to reg-reg move (2). */
1211 in SFmode, DFmode and XFmode */
1213 in SFmode, DFmode and XFmode */
1216 in SImode and DImode */
1218 in SImode and DImode */
1221 in SImode, DImode and TImode */
1223 in SImode, DImode and TImode */
1225 /* On K8:
1226 MOVD reg64, xmmreg Double FSTORE 4
1227 MOVD reg32, xmmreg Double FSTORE 4
1228 On AMDFAM10:
1229 MOVD reg64, xmmreg Double FADD 3
1230 1/1 1/1
1231 MOVD reg32, xmmreg Double FADD 3
1232 1/1 1/1 */
1236 /* New AMD processors never drop prefetches; if they cannot be performed
1237 immediately, they are queued. We set number of simultaneous prefetches
1238 to a large constant to reflect this (it probably is not a good idea not
1239 to limit number of prefetches at all, as their execution also takes some
1240 time). */
1250 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
1251 very small blocks it is better to use loop. For large blocks, libcall
1252 can do nontemporary accesses and beat inline considerably. */
1269 };
1271 static const
1294 in QImode, HImode and SImode.
1295 Relative to reg-reg move (2). */
1299 in SFmode, DFmode and XFmode */
1301 in SFmode, DFmode and XFmode */
1304 in SImode and DImode */
1306 in SImode and DImode */
1309 in SImode, DImode and TImode */
1311 in SImode, DImode and TImode */
1325 DUMMY_STRINGOP_ALGS},
1328 DUMMY_STRINGOP_ALGS},
1340 };
1342 static const
1365 in QImode, HImode and SImode.
1366 Relative to reg-reg move (2). */
1370 in SFmode, DFmode and XFmode */
1372 in SFmode, DFmode and XFmode */
1375 in SImode and DImode */
1377 in SImode and DImode */
1380 in SImode, DImode and TImode */
1382 in SImode, DImode and TImode */
1413 };
1415 static const
1438 in QImode, HImode and SImode.
1439 Relative to reg-reg move (2). */
1443 in SFmode, DFmode and XFmode */
1445 in SFmode, DFmode and XFmode */
1448 in SImode and DImode */
1450 in SImode and DImode */
1453 in SImode, DImode and TImode */
1455 in SImode, DImode and TImode */
1486 };
1488 /* Generic64 should produce code tuned for Nocona and K8. */
1489 static const
1492 /* On all chips taken into consideration lea is 2 cycles and more. With
1493 this cost however our current implementation of synth_mult results in
1494 use of unnecessary temporary registers causing regression on several
1495 SPECfp benchmarks. */
1516 in QImode, HImode and SImode.
1517 Relative to reg-reg move (2). */
1521 in SFmode, DFmode and XFmode */
1523 in SFmode, DFmode and XFmode */
1526 in SImode and DImode */
1528 in SImode and DImode */
1531 in SImode, DImode and TImode */
1533 in SImode, DImode and TImode */
1539 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1540 value is increased to perhaps more appropriate value of 5. */
1563 };
1565 /* Generic32 should produce code tuned for PPro, Pentium4, Nocona,
1566 Athlon and K8. */
1567 static const
1590 in QImode, HImode and SImode.
1591 Relative to reg-reg move (2). */
1595 in SFmode, DFmode and XFmode */
1597 in SFmode, DFmode and XFmode */
1600 in SImode and DImode */
1602 in SImode and DImode */
1605 in SImode, DImode and TImode */
1607 in SImode, DImode and TImode */
1621 DUMMY_STRINGOP_ALGS},
1623 DUMMY_STRINGOP_ALGS},
1635 };
1639 /* Processor feature/optimization bitmasks. */
1640 #define m_386 (1<<PROCESSOR_I386)
1641 #define m_486 (1<<PROCESSOR_I486)
1642 #define m_PENT (1<<PROCESSOR_PENTIUM)
1643 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1644 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1645 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1646 #define m_CORE2_32 (1<<PROCESSOR_CORE2_32)
1647 #define m_CORE2_64 (1<<PROCESSOR_CORE2_64)
1648 #define m_COREI7_32 (1<<PROCESSOR_COREI7_32)
1649 #define m_COREI7_64 (1<<PROCESSOR_COREI7_64)
1650 #define m_COREI7 (m_COREI7_32 | m_COREI7_64)
1651 #define m_CORE2I7_32 (m_CORE2_32 | m_COREI7_32)
1652 #define m_CORE2I7_64 (m_CORE2_64 | m_COREI7_64)
1653 #define m_CORE2I7 (m_CORE2I7_32 | m_CORE2I7_64)
1654 #define m_ATOM (1<<PROCESSOR_ATOM)
1656 #define m_GEODE (1<<PROCESSOR_GEODE)
1657 #define m_K6 (1<<PROCESSOR_K6)
1658 #define m_K6_GEODE (m_K6 | m_GEODE)
1659 #define m_K8 (1<<PROCESSOR_K8)
1660 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1661 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1662 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1663 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
1664 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10 | m_BDVER1)
1666 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1667 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1669 /* Generic instruction choice should be common subset of supported CPUs
1670 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1671 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1673 /* Feature tests against the various tunings. */
1676 /* Feature tests against the various tunings used to create ix86_tune_features
1677 based on the processor mask. */
1679 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1680 negatively, so enabling for Generic64 seems like good code size
1681 tradeoff. We can't enable it for 32bit generic because it does not
1682 work well with PPro base chips. */
1685 /* X86_TUNE_PUSH_MEMORY */
1689 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1692 /* X86_TUNE_UNROLL_STRLEN */
1696 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1700 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1701 on simulation result. But after P4 was made, no performance benefit
1702 was observed with branch hints. It also increases the code size.
1703 As a result, icc never generates branch hints. */
1706 /* X86_TUNE_DOUBLE_WITH_ADD */
1709 /* X86_TUNE_USE_SAHF */
1713 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1714 partial dependencies. */
1718 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1719 register stalls on Generic32 compilation setting as well. However
1720 in current implementation the partial register stalls are not eliminated
1721 very well - they can be introduced via subregs synthesized by combine
1722 and can happen in caller/callee saving sequences. Because this option
1723 pays back little on PPro based chips and is in conflict with partial reg
1724 dependencies used by Athlon/P4 based chips, it is better to leave it off
1725 for generic32 for now. */
1726 m_PPRO,
1728 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1731 /* X86_TUNE_USE_HIMODE_FIOP */
1734 /* X86_TUNE_USE_SIMODE_FIOP */
1737 /* X86_TUNE_USE_MOV0 */
1738 m_K6,
1740 /* X86_TUNE_USE_CLTD */
1743 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1744 m_PENT4,
1746 /* X86_TUNE_SPLIT_LONG_MOVES */
1747 m_PPRO,
1749 /* X86_TUNE_READ_MODIFY_WRITE */
1752 /* X86_TUNE_READ_MODIFY */
1755 /* X86_TUNE_PROMOTE_QIMODE */
1759 /* X86_TUNE_FAST_PREFIX */
1762 /* X86_TUNE_SINGLE_STRINGOP */
1765 /* X86_TUNE_QIMODE_MATH */
1768 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1769 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1770 might be considered for Generic32 if our scheme for avoiding partial
1771 stalls was more effective. */
1774 /* X86_TUNE_PROMOTE_QI_REGS */
1777 /* X86_TUNE_PROMOTE_HI_REGS */
1778 m_PPRO,
1780 /* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
1781 over esp addition. */
1784 /* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
1785 over esp addition. */
1786 m_PENT,
1788 /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
1789 over esp subtraction. */
1792 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
1793 over esp subtraction. */
1796 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1797 for DFmode copies */
1801 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1804 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1805 conflict here in between PPro/Pentium4 based chips that thread 128bit
1806 SSE registers as single units versus K8 based chips that divide SSE
1807 registers to two 64bit halves. This knob promotes all store destinations
1808 to be 128bit to allow register renaming on 128bit SSE units, but usually
1809 results in one extra microop on 64bit SSE units. Experimental results
1810 shows that disabling this option on P4 brings over 20% SPECfp regression,
1811 while enabling it on K8 brings roughly 2.4% regression that can be partly
1812 masked by careful scheduling of moves. */
1816 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
1819 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
1822 /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
1823 m_BDVER1,
1825 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1826 are resolved on SSE register parts instead of whole registers, so we may
1827 maintain just lower part of scalar values in proper format leaving the
1828 upper part undefined. */
1829 m_ATHLON_K8,
1831 /* X86_TUNE_SSE_TYPELESS_STORES */
1832 m_AMD_MULTIPLE,
1834 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1837 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1840 /* X86_TUNE_PROLOGUE_USING_MOVE */
1843 /* X86_TUNE_EPILOGUE_USING_MOVE */
1846 /* X86_TUNE_SHIFT1 */
1849 /* X86_TUNE_USE_FFREEP */
1850 m_AMD_MULTIPLE,
1852 /* X86_TUNE_INTER_UNIT_MOVES */
1855 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1858 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1859 than 4 branch instructions in the 16 byte window. */
1863 /* X86_TUNE_SCHEDULE */
1867 /* X86_TUNE_USE_BT */
1870 /* X86_TUNE_USE_INCDEC */
1873 /* X86_TUNE_PAD_RETURNS */
1876 /* X86_TUNE_PAD_SHORT_FUNCTION: Pad short funtion. */
1877 m_ATOM,
1879 /* X86_TUNE_EXT_80387_CONSTANTS */
1883 /* X86_TUNE_SHORTEN_X87_SSE */
1886 /* X86_TUNE_AVOID_VECTOR_DECODE */
1889 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1890 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1893 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1894 vector path on AMD machines. */
1897 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1898 machines. */
1901 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1902 than a MOV. */
1903 m_PENT,
1905 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1906 but one byte longer. */
1907 m_PENT,
1909 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1910 operand that cannot be represented using a modRM byte. The XOR
1911 replacement is long decoded, so this split helps here as well. */
1912 m_K6,
1914 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1915 from FP to FP. */
1918 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1919 from integer to FP. */
1920 m_AMDFAM10,
1922 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1923 with a subsequent conditional jump instruction into a single
1924 compare-and-branch uop. */
1925 m_BDVER1,
1927 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
1928 will impact LEA instruction selection. */
1929 m_ATOM,
1931 /* X86_TUNE_VECTORIZE_DOUBLE: Enable double precision vector
1932 instructions. */
1934 };
1936 /* Feature tests against the various architecture variations. */
1939 /* Feature tests against the various architecture variations, used to create
1940 ix86_arch_features based on the processor mask. */
1942 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1945 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1948 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1951 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1954 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1956 };
1958 static const unsigned int x86_accumulate_outgoing_args
1962 static const unsigned int x86_arch_always_fancy_math_387
1968 /* In case the average insn count for single function invocation is
1969 lower than this constant, emit fast (but longer) prologue and
1970 epilogue code. */
1971 #define FAST_PROLOGUE_INSN_COUNT 20
1973 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1978 /* Array of the smallest class containing reg number REGNO, indexed by
1979 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1982 {
1983 /* ax, dx, cx, bx */
1985 /* si, di, bp, sp */
1987 /* FP registers */
1990 /* arg pointer */
1991 NON_Q_REGS,
1992 /* flags, fpsr, fpcr, frame */
1994 /* SSE registers */
1997 /* MMX registers */
2000 /* REX registers */
2003 /* SSE REX registers */
2006 };
2008 /* The "default" register map used in 32bit mode. */
2011 {
2019 };
2021 /* The "default" register map used in 64bit mode. */
2024 {
2032 };
2034 /* Define the register numbers to be used in Dwarf debugging information.
2035 The SVR4 reference port C compiler uses the following register numbers
2036 in its Dwarf output code:
2037 0 for %eax (gcc regno = 0)
2038 1 for %ecx (gcc regno = 2)
2039 2 for %edx (gcc regno = 1)
2040 3 for %ebx (gcc regno = 3)
2041 4 for %esp (gcc regno = 7)
2042 5 for %ebp (gcc regno = 6)
2043 6 for %esi (gcc regno = 4)
2044 7 for %edi (gcc regno = 5)
2045 The following three DWARF register numbers are never generated by
2046 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2047 believes these numbers have these meanings.
2048 8 for %eip (no gcc equivalent)
2049 9 for %eflags (gcc regno = 17)
2050 10 for %trapno (no gcc equivalent)
2051 It is not at all clear how we should number the FP stack registers
2052 for the x86 architecture. If the version of SDB on x86/svr4 were
2053 a bit less brain dead with respect to floating-point then we would
2054 have a precedent to follow with respect to DWARF register numbers
2055 for x86 FP registers, but the SDB on x86/svr4 is so completely
2056 broken with respect to FP registers that it is hardly worth thinking
2057 of it as something to strive for compatibility with.
2058 The version of x86/svr4 SDB I have at the moment does (partially)
2059 seem to believe that DWARF register number 11 is associated with
2060 the x86 register %st(0), but that's about all. Higher DWARF
2061 register numbers don't seem to be associated with anything in
2062 particular, and even for DWARF regno 11, SDB only seems to under-
2063 stand that it should say that a variable lives in %st(0) (when
2064 asked via an `=' command) if we said it was in DWARF regno 11,
2065 but SDB still prints garbage when asked for the value of the
2066 variable in question (via a `/' command).
2067 (Also note that the labels SDB prints for various FP stack regs
2068 when doing an `x' command are all wrong.)
2069 Note that these problems generally don't affect the native SVR4
2070 C compiler because it doesn't allow the use of -O with -g and
2071 because when it is *not* optimizing, it allocates a memory
2072 location for each floating-point variable, and the memory
2073 location is what gets described in the DWARF AT_location
2074 attribute for the variable in question.
2075 Regardless of the severe mental illness of the x86/svr4 SDB, we
2076 do something sensible here and we use the following DWARF
2077 register numbers. Note that these are all stack-top-relative
2078 numbers.
2079 11 for %st(0) (gcc regno = 8)
2080 12 for %st(1) (gcc regno = 9)
2081 13 for %st(2) (gcc regno = 10)
2082 14 for %st(3) (gcc regno = 11)
2083 15 for %st(4) (gcc regno = 12)
2084 16 for %st(5) (gcc regno = 13)
2085 17 for %st(6) (gcc regno = 14)
2086 18 for %st(7) (gcc regno = 15)
2087 */
2089 {
2097 };
2099 /* Define parameter passing and return registers. */
2102 {
2104 };
2107 {
2109 };
2112 {
2114 };
2116 /* Define the structure for the machine field in struct function. */
2121 rtx rtl;
2123 };
2125 /* Structure describing stack frame layout.
2126 Stack grows downward:
2128 [arguments]
2129 <- ARG_POINTER
2130 saved pc
2132 saved static chain if ix86_static_chain_on_stack
2134 saved frame pointer if frame_pointer_needed
2135 <- HARD_FRAME_POINTER
2136 [saved regs]
2137 <- regs_save_offset
2138 [padding0]
2140 [saved SSE regs]
2141 <- sse_regs_save_offset
2142 [padding1] |
2143 | <- FRAME_POINTER
2144 [va_arg registers] |
2145 |
2146 [frame] |
2147 |
2148 [padding2] | = to_allocate
2149 <- STACK_POINTER
2150 */
2151 struct ix86_frame
2152 {
2158 HOST_WIDE_INT frame;
2160 /* The offsets relative to ARG_POINTER. */
2161 HOST_WIDE_INT frame_pointer_offset;
2162 HOST_WIDE_INT hard_frame_pointer_offset;
2163 HOST_WIDE_INT stack_pointer_offset;
2164 HOST_WIDE_INT hfp_save_offset;
2165 HOST_WIDE_INT reg_save_offset;
2166 HOST_WIDE_INT sse_reg_save_offset;
2168 /* When save_regs_using_mov is set, emit prologue using
2169 move instead of push instructions. */
2171 };
2173 /* Code model option. */
2175 /* Asm dialect. */
2177 /* TLS dialects. */
2180 /* Which unit we are generating floating point math for. */
2183 /* Which cpu are we scheduling for. */
2186 /* Which cpu are we optimizing for. */
2189 /* Which instruction set architecture to use. */
2192 /* true if sse prefetch instruction is not NOOP. */
2195 /* ix86_regparm_string as a number */
2198 /* -mstackrealign option */
2213 /* Preferred alignment for stack boundary in bits. */
2216 /* Alignment for incoming stack boundary in bits specified at
2217 command line. */
2220 /* Default alignment for incoming stack boundary in bits. */
2223 /* Alignment for incoming stack boundary in bits. */
2226 /* The abi used by target. */
2229 /* Values 1-5: see jump.c */
2232 /* Calling abi specific va_list type nodes. */
2236 /* Variables which are this size or smaller are put in the data/bss
2237 or ldata/lbss sections. */
2241 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2245 /* Fence to use after loop using movnt. */
2246 tree x86_mfence;
2248 /* Register class used for passing given 64bit part of the argument.
2249 These represent classes as documented by the PS ABI, with the exception
2250 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2251 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2253 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2254 whenever possible (upper half does contain padding). */
2255 enum x86_64_reg_class
2256 {
2257 X86_64_NO_CLASS,
2258 X86_64_INTEGER_CLASS,
2259 X86_64_INTEGERSI_CLASS,
2260 X86_64_SSE_CLASS,
2261 X86_64_SSESF_CLASS,
2262 X86_64_SSEDF_CLASS,
2263 X86_64_SSEUP_CLASS,
2264 X86_64_X87_CLASS,
2265 X86_64_X87UP_CLASS,
2266 X86_64_COMPLEX_X87_CLASS,
2267 X86_64_MEMORY_CLASS
2268 };
2270 #define MAX_CLASSES 4
2272 /* Table of constants used by fldpi, fldln2, etc.... */
2276 \f
2281 const_tree);
2294 enum ix86_function_specific_strings
2295 {
2296 IX86_FUNCTION_SPECIFIC_ARCH,
2297 IX86_FUNCTION_SPECIFIC_TUNE,
2298 IX86_FUNCTION_SPECIFIC_FPMATH,
2299 IX86_FUNCTION_SPECIFIC_MAX
2300 };
2317 \f
2318 #ifndef SUBTARGET32_DEFAULT_CPU
2320 #endif
2322 /* The svr4 ABI for the i386 says that records and unions are returned
2323 in memory. */
2324 #ifndef DEFAULT_PCC_STRUCT_RETURN
2325 #define DEFAULT_PCC_STRUCT_RETURN 1
2326 #endif
2328 /* Whether -mtune= or -march= were specified */
2332 /* A mask of ix86_isa_flags that includes bit X if X
2333 was set or cleared on the command line. */
2336 /* Define a set of ISAs which are available when a given ISA is
2337 enabled. MMX and SSE ISAs are handled separately. */
2339 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
2340 #define OPTION_MASK_ISA_3DNOW_SET \
2341 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
2343 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
2344 #define OPTION_MASK_ISA_SSE2_SET \
2345 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
2346 #define OPTION_MASK_ISA_SSE3_SET \
2347 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
2348 #define OPTION_MASK_ISA_SSSE3_SET \
2349 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
2350 #define OPTION_MASK_ISA_SSE4_1_SET \
2351 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
2352 #define OPTION_MASK_ISA_SSE4_2_SET \
2353 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
2354 #define OPTION_MASK_ISA_AVX_SET \
2355 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
2356 #define OPTION_MASK_ISA_FMA_SET \
2357 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
2359 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
2360 as -msse4.2. */
2361 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
2363 #define OPTION_MASK_ISA_SSE4A_SET \
2364 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
2365 #define OPTION_MASK_ISA_FMA4_SET \
2366 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
2367 | OPTION_MASK_ISA_AVX_SET)
2368 #define OPTION_MASK_ISA_XOP_SET \
2369 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
2370 #define OPTION_MASK_ISA_LWP_SET \
2371 OPTION_MASK_ISA_LWP
2373 /* AES and PCLMUL need SSE2 because they use xmm registers */
2374 #define OPTION_MASK_ISA_AES_SET \
2375 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
2376 #define OPTION_MASK_ISA_PCLMUL_SET \
2377 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
2379 #define OPTION_MASK_ISA_ABM_SET \
2380 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
2382 #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
2383 #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
2384 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
2385 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
2386 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
2387 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
2388 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
2390 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
2391 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
2392 #define OPTION_MASK_ISA_F16C_SET \
2393 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
2395 /* Define a set of ISAs which aren't available when a given ISA is
2396 disabled. MMX and SSE ISAs are handled separately. */
2398 #define OPTION_MASK_ISA_MMX_UNSET \
2399 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
2400 #define OPTION_MASK_ISA_3DNOW_UNSET \
2401 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
2402 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
2404 #define OPTION_MASK_ISA_SSE_UNSET \
2405 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
2406 #define OPTION_MASK_ISA_SSE2_UNSET \
2407 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
2408 #define OPTION_MASK_ISA_SSE3_UNSET \
2409 (OPTION_MASK_ISA_SSE3 \
2410 | OPTION_MASK_ISA_SSSE3_UNSET \
2411 | OPTION_MASK_ISA_SSE4A_UNSET )
2412 #define OPTION_MASK_ISA_SSSE3_UNSET \
2413 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
2414 #define OPTION_MASK_ISA_SSE4_1_UNSET \
2415 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
2416 #define OPTION_MASK_ISA_SSE4_2_UNSET \
2417 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
2418 #define OPTION_MASK_ISA_AVX_UNSET \
2419 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
2420 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET)
2421 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
2423 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
2424 as -mno-sse4.1. */
2425 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
2427 #define OPTION_MASK_ISA_SSE4A_UNSET \
2428 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
2430 #define OPTION_MASK_ISA_FMA4_UNSET \
2431 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
2432 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
2433 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
2435 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
2436 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
2437 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
2438 #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
2439 #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
2440 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
2441 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
2442 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
2443 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
2444 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
2446 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
2447 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
2448 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
2450 /* Vectorization library interface and handlers. */
2456 /* Processor target table, indexed by processor number */
2457 struct ptt
2458 {
2465 };
2468 {
2479 /* Core 2 32-bit. */
2481 /* Core 2 64-bit. */
2483 /* Core i7 32-bit. */
2485 /* Core i7 64-bit. */
2492 };
2495 {
2519 "bdver1"
2520 };
2521 \f
2522 /* Return true if a red-zone is in use. */
2526 {
2528 }
2530 /* Implement TARGET_HANDLE_OPTION. */
2532 static bool
2534 {
2536 {
2539 {
2542 }
2543 else
2544 {
2547 }
2552 {
2555 }
2556 else
2557 {
2560 }
2568 {
2571 }
2572 else
2573 {
2576 }
2581 {
2584 }
2585 else
2586 {
2589 }
2594 {
2597 }
2598 else
2599 {
2602 }
2607 {
2610 }
2611 else
2612 {
2615 }
2620 {
2623 }
2624 else
2625 {
2628 }
2633 {
2636 }
2637 else
2638 {
2641 }
2646 {
2649 }
2650 else
2651 {
2654 }
2659 {
2662 }
2663 else
2664 {
2667 }
2682 {
2685 }
2686 else
2687 {
2690 }
2695 {
2698 }
2699 else
2700 {
2703 }
2708 {
2711 }
2712 else
2713 {
2716 }
2721 {
2724 }
2725 else
2726 {
2729 }
2734 {
2737 }
2738 else
2739 {
2742 }
2747 {
2750 }
2751 else
2752 {
2755 }
2760 {
2763 }
2764 else
2765 {
2768 }
2773 {
2776 }
2777 else
2778 {
2781 }
2786 {
2789 }
2790 else
2791 {
2794 }
2799 {
2802 }
2803 else
2804 {
2807 }
2812 {
2815 }
2816 else
2817 {
2820 }
2825 {
2828 }
2829 else
2830 {
2833 }
2838 {
2841 }
2842 else
2843 {
2846 }
2851 {
2854 }
2855 else
2856 {
2859 }
2864 {
2867 }
2868 else
2869 {
2872 }
2877 {
2880 }
2881 else
2882 {
2885 }
2890 {
2893 }
2894 else
2895 {
2898 }
2903 }
2904 }
2905 \f
2906 /* Return a string that documents the current -m options. The caller is
2907 responsible for freeing the string. */
2912 {
2913 struct ix86_target_opts
2914 {
2917 };
2919 /* This table is ordered so that options like -msse4.2 that imply
2920 preceding options while match those first. */
2922 {
2949 };
2951 /* Flag options. */
2953 {
2977 };
2993 /* Add -march= option. */
2995 {
2998 }
3000 /* Add -mtune= option. */
3002 {
3005 }
3007 /* Pick out the options in isa options. */
3009 {
3011 {
3014 }
3015 }
3018 {
3021 }
3023 /* Add flag options. */
3025 {
3027 {
3030 }
3031 }
3034 {
3037 }
3039 /* Add -fpmath= option. */
3041 {
3044 }
3046 /* Any options? */
3052 /* Size the string. */
3056 {
3061 }
3063 /* Build the string. */
3068 {
3075 {
3077 line_len++;
3080 {
3084 }
3085 }
3089 {
3093 }
3094 }
3100 }
3102 /* Return TRUE if software prefetching is beneficial for the
3103 given CPU. */
3105 static bool
3107 {
3109 {
3119 }
3120 }
3122 /* Return true, if profiling code should be emitted before
3123 prologue. Otherwise it returns false.
3124 Note: For x86 with "hotfix" it is sorried. */
3125 static bool
3127 {
3129 }
3131 /* Function that is callable from the debugger to print the current
3132 options. */
3133 void
3135 {
3141 {
3144 }
3145 else
3149 }
3150 \f
3151 /* Override various settings based on options. If MAIN_ARGS_P, the
3152 options are from the command line, otherwise they are from
3153 attributes. */
3155 static void
3157 {
3165 /* Comes from final.c -- no real reason to change it. */
3166 #define MAX_CODE_ALIGN 16
3168 enum pta_flags
3169 {
3199 /* if this reaches 32, need to widen struct pta flags below */
3200 };
3202 static struct pta
3203 {
3208 }
3210 {
3304 };
3308 /* Set up prefix/suffix so the error messages refer to either the command
3309 line argument, or the attribute(target). */
3311 {
3315 }
3316 else
3317 {
3321 }
3323 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3324 SUBTARGET_OVERRIDE_OPTIONS;
3325 #endif
3327 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3328 SUBSUBTARGET_OVERRIDE_OPTIONS;
3329 #endif
3331 /* -fPIC is the default for x86_64. */
3335 /* Need to check -mtune=generic first. */
3337 {
3340 /* As special support for cross compilers we read -mtune=native
3341 as -mtune=generic. With native compilers we won't see the
3342 -mtune=native, as it was changed by the driver. */
3344 {
3347 else
3349 }
3350 /* If this call is for setting the option attribute, allow the
3351 generic32/generic64 that was previously set. */
3355 ;
3363 }
3364 else
3365 {
3369 {
3372 }
3374 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
3375 need to use a sensible tune option. */
3379 {
3382 else
3384 }
3385 }
3388 {
3397 /* rep; movq isn't available in 32-bit code. */
3405 else
3408 }
3412 else
3415 /* Validate -mabi= value. */
3417 {
3422 else
3425 }
3426 else
3430 {
3443 else
3446 }
3447 else
3448 {
3449 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3450 use of rip-relative addressing. This eliminates fixups that
3451 would otherwise be needed if this object is to be placed in a
3452 DLL, and is essentially just as efficient as direct addressing. */
3457 else
3459 }
3461 {
3467 else
3470 }
3480 {
3483 /* Default cpu tuning to the architecture. */
3575 }
3590 {
3594 {
3596 {
3598 {
3606 }
3607 else
3610 }
3611 }
3612 else
3613 {
3614 /* Adjust tuning when compiling for 32-bit ABI. */
3616 {
3632 }
3633 }
3634 /* Intel CPUs have always interpreted SSE prefetch instructions as
3635 NOPs; so, we can enable SSE prefetch instructions even when
3636 -mtune (rather than -march) points us to a processor that has them.
3637 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3638 higher processors. */
3643 }
3653 #ifndef USE_IX86_FRAME_POINTER
3654 #define USE_IX86_FRAME_POINTER 0
3655 #endif
3657 #ifndef USE_X86_64_FRAME_POINTER
3658 #define USE_X86_64_FRAME_POINTER 0
3659 #endif
3661 /* Set the default values for switches whose default depends on TARGET_64BIT
3662 in case they weren't overwritten by command line options. */
3664 {
3673 }
3674 else
3675 {
3682 }
3686 else
3689 /* Arrange to set up i386_stack_locals for all functions. */
3692 /* Validate -mregparm= value. */
3694 {
3701 else
3703 }
3707 /* If the user has provided any of the -malign-* options,
3708 warn and use that value only if -falign-* is not set.
3709 Remove this code in GCC 3.2 or later. */
3711 {
3715 {
3720 else
3722 }
3723 }
3726 {
3730 {
3735 else
3737 }
3738 }
3741 {
3745 {
3750 else
3752 }
3753 }
3755 /* Default align_* from the processor table. */
3757 {
3760 }
3762 {
3765 }
3767 {
3769 }
3771 /* Validate -mbranch-cost= value, or provide default. */
3774 {
3778 else
3780 }
3782 {
3786 else
3788 }
3791 {
3796 else
3799 }
3802 {
3806 }
3809 {
3812 /* Enable by default the SSE and MMX builtins. Do allow the user to
3813 explicitly disable any of these. In particular, disabling SSE and
3814 MMX for kernel code is extremely useful. */
3816 ix86_isa_flags
3822 }
3823 else
3824 {
3828 ix86_isa_flags
3831 /* i386 ABI does not specify red zone. It still makes sense to use it
3832 when programmer takes care to stack from being destroyed. */
3835 }
3837 /* Keep nonleaf frame pointers. */
3843 /* If we're doing fast math, we don't care about comparison order
3844 wrt NaNs. This lets us use a shorter comparison sequence. */
3848 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3849 since the insns won't need emulation. */
3853 /* Likewise, if the target doesn't have a 387, or we've specified
3854 software floating point, don't use 387 inline intrinsics. */
3858 /* Turn on MMX builtins for -msse. */
3860 {
3863 }
3865 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3869 /* Validate -mpreferred-stack-boundary= value or default it to
3870 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3873 {
3879 {
3883 else
3886 }
3887 else
3889 }
3891 /* Set the default value for -mstackrealign. */
3897 /* Validate -mincoming-stack-boundary= value or default it to
3898 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3901 {
3906 else
3907 {
3909 ix86_incoming_stack_boundary
3911 }
3912 }
3914 /* Accept -msseregparm only if at least SSE support is enabled. */
3921 {
3925 {
3927 {
3930 }
3931 else
3933 }
3939 {
3941 {
3944 }
3946 {
3949 }
3950 else
3952 }
3953 else
3956 }
3958 /* If the i387 is disabled, then do not return values in it. */
3962 /* Use external vectorized library in vectorizing intrinsics. */
3964 {
3969 else
3973 }
3981 /* ??? Unwind info is not correct around the CFG unless either a frame
3982 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3983 unwind info generation to be aware of the CFG and propagating states
3984 around edges. */
3987 && flag_omit_frame_pointer
3989 {
3995 }
3997 /* If stack probes are required, the space used for large function
3998 arguments on the stack must also be probed, so enable
3999 -maccumulate-outgoing-args so this happens in the prologue. */
4002 {
4007 }
4009 /* For sane SSE instruction set generation we need fcomi instruction.
4010 It is safe to enable all CMOVE instructions. */
4014 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4015 {
4021 }
4023 /* When scheduling description is not available, disable scheduler pass
4024 so it won't slow down the compilation and make x87 code slower. */
4042 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4044 && HAVE_prefetch
4049 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4050 can be optimized to ap = __builtin_next_arg (0). */
4055 {
4066 }
4067 else
4068 {
4079 }
4081 #ifdef USE_IX86_CLD
4082 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4085 #endif
4088 {
4093 }
4095 {
4099 }
4101 {
4102 #if defined(PROFILE_BEFORE_PROLOGUE)
4104 #else
4106 #endif
4107 }
4109 /* Save the initial options in case the user does function specific options */
4111 target_option_default_node = target_option_current_node
4115 {
4116 /* When not optimize for size, enable vzeroupper optimization for
4117 TARGET_AVX with -fexpensive-optimizations. */
4119 && flag_expensive_optimizations
4122 }
4123 else
4124 {
4125 /* Disable vzeroupper pass if TARGET_AVX is disabled. */
4127 }
4128 }
4130 /* Return TRUE if VAL is passed in register with 256bit AVX modes. */
4132 static bool
4134 {
4142 {
4144 rtx r;
4147 {
4155 }
4156 }
4159 }
4161 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4163 static void
4165 {
4167 }
4169 /* Update register usage after having seen the compiler flags. */
4171 static void
4173 {
4178 {
4183 }
4185 /* The PIC register, if it exists, is fixed. */
4190 /* The MS_ABI changes the set of call-used registers. */
4192 {
4199 }
4201 /* The default setting of CLOBBERED_REGS is for 32-bit; add in the
4202 other call-clobbered regs for 64-bit. */
4204 {
4211 }
4213 /* If MMX is disabled, squash the registers. */
4219 /* If SSE is disabled, squash the registers. */
4225 /* If the FPU is disabled, squash the registers. */
4231 /* If 32-bit, squash the 64-bit registers. */
4233 {
4238 }
4239 }
4241 \f
4242 /* Save the current options */
4244 static void
4246 {
4257 /* The fields are char but the variables are not; make sure the
4258 values fit in the fields. */
4264 }
4266 /* Restore the current options */
4268 static void
4270 {
4286 /* Recreate the arch feature tests if the arch changed */
4288 {
4293 }
4295 /* Recreate the tune optimization tests */
4297 {
4302 }
4303 }
4305 /* Print the current options */
4307 static void
4310 {
4335 {
4338 }
4339 }
4341 \f
4342 /* Inner function to process the attribute((target(...))), take an argument and
4343 set the current options from the argument. If we have a list, recursively go
4344 over the list. */
4346 static bool
4348 {
4352 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4353 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4354 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4355 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4357 enum ix86_opt_type
4358 {
4359 ix86_opt_unknown,
4360 ix86_opt_yes,
4361 ix86_opt_no,
4362 ix86_opt_str,
4363 ix86_opt_isa
4364 };
4366 static const struct
4367 {
4374 /* isa options */
4399 /* string options */
4404 /* flag options */
4406 OPT_mcld,
4407 MASK_CLD),
4410 OPT_mfancy_math_387,
4411 MASK_NO_FANCY_MATH_387),
4414 OPT_mieee_fp,
4415 MASK_IEEE_FP),
4418 OPT_minline_all_stringops,
4419 MASK_INLINE_ALL_STRINGOPS),
4422 OPT_minline_stringops_dynamically,
4423 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4426 OPT_mno_align_stringops,
4427 MASK_NO_ALIGN_STRINGOPS),
4430 OPT_mrecip,
4431 MASK_RECIP),
4433 };
4435 /* If this is a list, recurse to get the options. */
4437 {
4446 }
4451 /* Handle multiple arguments separated by commas. */
4455 {
4469 {
4473 }
4474 else
4475 {
4478 }
4480 /* Recognize no-xxx. */
4482 {
4486 }
4487 else
4490 /* Find the option. */
4494 {
4500 {
4505 }
4506 }
4508 /* Process the option. */
4510 {
4513 }
4519 {
4525 else
4527 }
4530 {
4532 {
4535 }
4536 else
4538 }
4540 else
4542 }
4545 }
4547 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4549 tree
4551 {
4563 /* Process each of the options on the chain. */
4567 /* If the changed options are different from the default, rerun
4568 ix86_option_override_internal, and then save the options away.
4569 The string options are are attribute options, and will be undone
4570 when we copy the save structure. */
4576 {
4577 /* If we are using the default tune= or arch=, undo the string assigned,
4578 and use the default. */
4589 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4595 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4598 /* Add any builtin functions with the new isa if any. */
4601 /* Save the current options unless we are validating options for
4602 #pragma. */
4609 /* Free up memory allocated to hold the strings */
4613 }
4616 }
4618 /* Hook to validate attribute((target("string"))). */
4620 static bool
4623 tree args,
4625 {
4632 /* If the function changed the optimization levels as well as setting target
4633 options, start with the optimizations specified. */
4638 /* The target attributes may also change some optimization flags, so update
4639 the optimization options if necessary. */
4648 {
4653 }
4662 }
4664 \f
4665 /* Hook to determine if one function can safely inline another. */
4667 static bool
4669 {
4674 /* If callee has no option attributes, then it is ok to inline. */
4678 /* If caller has no option attributes, but callee does then it is not ok to
4679 inline. */
4683 else
4684 {
4688 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4689 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4690 function. */
4695 /* See if we have the same non-isa options. */
4699 /* See if arch, tune, etc. are the same. */
4712 else
4714 }
4717 }
4719 \f
4720 /* Remember the last target of ix86_set_current_function. */
4723 /* Establish appropriate back-end context for processing the function
4724 FNDECL. The argument might be NULL to indicate processing at top
4725 level, outside of any function scope. */
4726 static void
4728 {
4729 /* Only change the context if the function changes. This hook is called
4730 several times in the course of compiling a function, and we don't want to
4731 slow things down too much or call target_reinit when it isn't safe. */
4733 {
4734 tree old_tree = (ix86_previous_fndecl
4738 tree new_tree = (fndecl
4744 ;
4747 {
4751 }
4754 {
4760 }
4761 }
4762 }
4764 \f
4765 /* Return true if this goes in large data/bss. */
4767 static bool
4769 {
4773 /* Functions are never large data. */
4778 {
4784 }
4785 else
4786 {
4789 /* If this is an incomplete type with size 0, then we can't put it
4790 in data because it might be too big when completed. */
4793 }
4796 }
4798 /* Switch to the appropriate section for output of DECL.
4799 DECL is either a `VAR_DECL' node or a constant of some sort.
4800 RELOC indicates whether forming the initial value of DECL requires
4801 link-time relocations. */
4804 ATTRIBUTE_UNUSED;
4809 {
4812 {
4816 {
4850 /* We don't split these for medium model. Place them into
4851 default sections and hope for best. */
4853 }
4855 {
4856 /* We might get called with string constants, but get_named_section
4857 doesn't like them as they are not DECLs. Also, we need to set
4858 flags in that case. */
4862 }
4863 }
4865 }
4867 /* Build up a unique section name, expressed as a
4868 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4869 RELOC indicates whether the initial value of EXP requires
4870 link-time relocations. */
4872 static void ATTRIBUTE_UNUSED
4874 {
4877 {
4879 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4883 {
4907 /* We don't split these for medium model. Place them into
4908 default sections and hope for best. */
4910 }
4912 {
4919 /* If we're using one_only, then there needs to be a .gnu.linkonce
4920 prefix to the section name. */
4927 }
4928 }
4930 }
4932 #ifdef COMMON_ASM_OP
4933 /* This says how to output assembler code to declare an
4934 uninitialized external linkage data object.
4936 For medium model x86-64 we need to use .largecomm opcode for
4937 large objects. */
4938 void
4942 {
4946 else
4951 }
4952 #endif
4954 /* Utility function for targets to use in implementing
4955 ASM_OUTPUT_ALIGNED_BSS. */
4957 void
4961 {
4965 else
4968 #ifdef ASM_DECLARE_OBJECT_NAME
4971 #else
4972 /* Standard thing is just output label for the object. */
4976 }
4977 \f
4979 {
4980 /* Turn off -fschedule-insns by default. It tends to make the
4981 problem with not enough registers even worse. */
4982 #ifdef INSN_SCHEDULING
4984 #endif
4986 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4987 SUBTARGET_OPTIMIZATION_OPTIONS,
4988 #endif
4990 };
4992 /* Implement TARGET_OPTION_INIT_STRUCT. */
4994 static void
4996 {
4998 /* The Darwin libraries never set errno, so we might as well
4999 avoid calling them when that's the only reason we would. */
5005 }
5007 /* Decide whether we must probe the stack before any space allocation
5008 on this target. It's essentially TARGET_STACK_PROBE except when
5009 -fstack-check causes the stack to be already probed differently. */
5011 bool
5013 {
5014 /* Do not probe the stack twice if static stack checking is enabled. */
5019 }
5020 \f
5021 /* Decide whether we can make a sibling call to a function. DECL is the
5022 declaration of the function being targeted by the call and EXP is the
5023 CALL_EXPR representing the call. */
5025 static bool
5027 {
5031 /* If we are generating position-independent code, we cannot sibcall
5032 optimize any indirect call, or a direct call to a global function,
5033 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5035 && !TARGET_64BIT
5036 && flag_pic
5040 /* If we need to align the outgoing stack, then sibcalling would
5041 unalign the stack, which may break the called function. */
5047 {
5050 }
5051 else
5052 {
5053 /* We're looking at the CALL_EXPR, we need the type of the function. */
5058 }
5060 /* Check that the return value locations are the same. Like
5061 if we are returning floats on the 80387 register stack, we cannot
5062 make a sibcall from a function that doesn't return a float to a
5063 function that does or, conversely, from a function that does return
5064 a float to a function that doesn't; the necessary stack adjustment
5065 would not be executed. This is also the place we notice
5066 differences in the return value ABI. Note that it is ok for one
5067 of the functions to have void return type as long as the return
5068 value of the other is passed in a register. */
5073 {
5076 }
5078 {
5079 /* Disable sibcall if we need to generate vzeroupper after
5080 callee returns. */
5085 }
5090 {
5091 /* The SYSV ABI has more call-clobbered registers;
5092 disallow sibcalls from MS to SYSV. */
5096 }
5097 else
5098 {
5099 /* If this call is indirect, we'll need to be able to use a
5100 call-clobbered register for the address of the target function.
5101 Make sure that all such registers are not used for passing
5102 parameters. Note that DLLIMPORT functions are indirect. */
5105 {
5107 {
5108 /* ??? Need to count the actual number of registers to be used,
5109 not the possible number of registers. Fix later. */
5111 }
5112 }
5113 }
5115 /* Otherwise okay. That also includes certain types of indirect calls. */
5117 }
5119 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5120 and "sseregparm" calling convention attributes;
5121 arguments as in struct attribute_spec.handler. */
5123 static tree
5125 tree args,
5128 {
5133 {
5135 name);
5138 }
5140 /* Can combine regparm with all attributes but fastcall. */
5142 {
5143 tree cst;
5146 {
5148 }
5151 {
5153 }
5157 {
5160 name);
5162 }
5164 {
5168 }
5171 }
5174 {
5175 /* Do not warn when emulating the MS ABI. */
5180 name);
5183 }
5185 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5187 {
5189 {
5191 }
5193 {
5195 }
5197 {
5199 }
5201 {
5203 }
5204 }
5206 /* Can combine stdcall with fastcall (redundant), regparm and
5207 sseregparm. */
5209 {
5211 {
5213 }
5215 {
5217 }
5219 {
5221 }
5222 }
5224 /* Can combine cdecl with regparm and sseregparm. */
5226 {
5228 {
5230 }
5232 {
5234 }
5236 {
5238 }
5239 }
5241 {
5244 name);
5246 {
5248 }
5250 {
5252 }
5254 {
5256 }
5257 }
5259 /* Can combine sseregparm with all attributes. */
5262 }
5264 /* Return 0 if the attributes for two types are incompatible, 1 if they
5265 are compatible, and 2 if they are nearly compatible (which causes a
5266 warning to be generated). */
5268 static int
5270 {
5271 /* Check for mismatch of non-default calling convention. */
5278 /* Check for mismatched fastcall/regparm types. */
5285 /* Check for mismatched sseregparm types. */
5290 /* Check for mismatched thiscall types. */
5295 /* Check for mismatched return types (cdecl vs stdcall). */
5301 }
5302 \f
5303 /* Return the regparm value for a function with the indicated TYPE and DECL.
5304 DECL may be NULL when calling function indirectly
5305 or considering a libcall. */
5307 static int
5309 {
5310 tree attr;
5320 {
5323 }
5331 /* Use register calling convention for local functions when possible. */
5334 && optimize
5336 {
5337 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5340 {
5343 /* Make sure no regparm register is taken by a
5344 fixed register variable. */
5349 /* We don't want to use regparm(3) for nested functions as
5350 these use a static chain pointer in the third argument. */
5354 /* In 32-bit mode save a register for the split stack. */
5358 /* Each fixed register usage increases register pressure,
5359 so less registers should be used for argument passing.
5360 This functionality can be overriden by an explicit
5361 regparm value. */
5364 globals++;
5366 local_regparm
5371 }
5372 }
5375 }
5377 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5378 DFmode (2) arguments in SSE registers for a function with the
5379 indicated TYPE and DECL. DECL may be NULL when calling function
5380 indirectly or considering a libcall. Otherwise return 0. */
5382 static int
5384 {
5387 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5388 by the sseregparm attribute. */
5391 {
5393 {
5395 {
5399 else
5402 }
5404 }
5407 }
5409 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5410 (and DFmode for SSE2) arguments in SSE registers. */
5413 {
5414 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5418 }
5421 }
5423 /* Return true if EAX is live at the start of the function. Used by
5424 ix86_expand_prologue to determine if we need special help before
5425 calling allocate_stack_worker. */
5427 static bool
5429 {
5430 /* Cheat. Don't bother working forward from ix86_function_regparm
5431 to the function type to whether an actual argument is located in
5432 eax. Instead just look at cfg info, which is still close enough
5433 to correct at this point. This gives false positives for broken
5434 functions that might use uninitialized data that happens to be
5435 allocated in eax, but who cares? */
5437 }
5439 static bool
5441 {
5442 tree attr;
5450 }
5452 /* Value is the number of bytes of arguments automatically
5453 popped when returning from a subroutine call.
5454 FUNDECL is the declaration node of the function (as a tree),
5455 FUNTYPE is the data type of the function (as a tree),
5456 or for a library call it is an identifier node for the subroutine name.
5457 SIZE is the number of bytes of arguments passed on the stack.
5459 On the 80386, the RTD insn may be used to pop them if the number
5460 of args is fixed, but if the number is variable then the caller
5461 must pop them all. RTD can't be used for library calls now
5462 because the library is compiled with the Unix compiler.
5463 Use of RTD is a selectable option, since it is incompatible with
5464 standard Unix calling sequences. If the option is not selected,
5465 the caller must always pop the args.
5467 The attribute stdcall is equivalent to RTD on a per module basis. */
5469 static int
5471 {
5474 /* None of the 64-bit ABIs pop arguments. */
5480 /* Cdecl functions override -mrtd, and never pop the stack. */
5482 {
5483 /* Stdcall and fastcall functions will pop the stack if not
5484 variable args. */
5492 }
5494 /* Lose any fake structure return argument if it is passed on the stack. */
5497 {
5501 }
5504 }
5505 \f
5506 /* Argument support functions. */
5508 /* Return true when register may be used to pass function parameters. */
5509 bool
5511 {
5516 {
5520 else
5526 }
5529 {
5532 }
5533 else
5534 {
5538 }
5540 /* TODO: The function should depend on current function ABI but
5541 builtins.c would need updating then. Therefore we use the
5542 default ABI. */
5544 /* RAX is used as hidden argument to va_arg functions. */
5550 else
5557 }
5559 /* Return if we do not know how to pass TYPE solely in registers. */
5561 static bool
5563 {
5567 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5568 The layout_type routine is crafty and tries to trick us into passing
5569 currently unsupported vector types on the stack by using TImode. */
5572 }
5574 /* It returns the size, in bytes, of the area reserved for arguments passed
5575 in registers for the function represented by fndecl dependent to the used
5576 abi format. */
5577 int
5579 {
5583 else
5588 }
5590 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5591 call abi used. */
5592 enum calling_abi
5594 {
5596 {
5599 {
5602 }
5606 }
5608 }
5610 static bool
5612 {
5614 {
5618 else
5620 }
5622 }
5624 static enum calling_abi
5626 {
5630 }
5632 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
5633 call abi used. */
5634 enum calling_abi
5636 {
5640 }
5642 /* Write the extra assembler code needed to declare a function properly. */
5644 void
5646 tree decl)
5647 {
5651 {
5657 }
5659 #ifdef SUBTARGET_ASM_UNWIND_INIT
5661 #endif
5665 /* Output magic byte marker, if hot-patch attribute is set. */
5667 {
5669 {
5670 /* leaq [%rsp + 0], %rsp */
5673 }
5674 else
5675 {
5676 /* movl.s %edi, %edi
5677 push %ebp
5678 movl.s %esp, %ebp */
5681 }
5682 }
5683 }
5685 /* regclass.c */
5688 /* Implementation of call abi switching target hook. Specific to FNDECL
5689 the specific call register sets are set. See also
5690 ix86_conditional_register_usage for more details. */
5691 void
5693 {
5696 else
5698 }
5700 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
5701 re-initialization of init_regs each time we switch function context since
5702 this is needed only during RTL expansion. */
5703 static void
5705 {
5709 }
5711 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5712 for a call to a function whose data type is FNTYPE.
5713 For a library call, FNTYPE is 0. */
5715 void
5719 tree fndecl,
5721 {
5723 tree fnret_type;
5727 /* Initialize for the current callee. */
5729 {
5732 }
5735 {
5739 }
5740 else
5741 {
5746 else
5748 }
5751 {
5755 {
5756 /* The return value of this function uses 256bit AVX modes. */
5759 else
5761 }
5762 }
5766 /* Set up the number of registers to use for passing arguments. */
5773 {
5775 ? X86_64_REGPARM_MAX
5777 }
5779 {
5782 {
5784 ? X86_64_SSE_REGPARM_MAX
5786 }
5787 }
5794 /* Because type might mismatch in between caller and callee, we need to
5795 use actual type of function for local calls.
5796 FIXME: cgraph_analyze can be told to actually record if function uses
5797 va_start so for local functions maybe_vaarg can be made aggressive
5798 helping K&R code.
5799 FIXME: once typesytem is fixed, we won't need this code anymore. */
5807 {
5808 /* If there are variable arguments, then we won't pass anything
5809 in registers in 32-bit mode. */
5811 {
5819 }
5821 /* Use ecx and edx registers if function has fastcall attribute,
5822 else look for regparm information. */
5824 {
5826 {
5829 }
5831 {
5834 }
5835 else
5837 }
5839 /* Set up the number of SSE registers used for passing SFmode
5840 and DFmode arguments. Warn for mismatching ABI. */
5842 }
5843 }
5845 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
5846 But in the case of vector types, it is some vector mode.
5848 When we have only some of our vector isa extensions enabled, then there
5849 are some modes for which vector_mode_supported_p is false. For these
5850 modes, the generic vector support in gcc will choose some non-vector mode
5851 in order to implement the type. By computing the natural mode, we'll
5852 select the proper ABI location for the operand and not depend on whatever
5853 the middle-end decides to do with these vector types.
5855 The midde-end can't deal with the vector types > 16 bytes. In this
5856 case, we return the original mode and warn ABI change if CUM isn't
5857 NULL. */
5859 static enum machine_mode
5861 {
5865 {
5868 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5870 {
5875 else
5878 /* Get the mode which has this inner mode and number of units. */
5882 {
5884 {
5888 && !warnedavx
5890 {
5894 }
5896 }
5897 else
5899 }
5902 }
5903 }
5906 }
5908 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
5909 this may not agree with the mode that the type system has chosen for the
5910 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
5911 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5913 static rtx
5916 {
5917 rtx tmp;
5921 else
5922 {
5926 }
5929 }
5931 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5932 of this code is to classify each 8bytes of incoming argument by the register
5933 class and assign registers accordingly. */
5935 /* Return the union class of CLASS1 and CLASS2.
5936 See the x86-64 PS ABI for details. */
5938 static enum x86_64_reg_class
5940 {
5941 /* Rule #1: If both classes are equal, this is the resulting class. */
5945 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5946 the other class. */
5952 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5956 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5964 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5965 MEMORY is used. */
5974 /* Rule #6: Otherwise class SSE is used. */
5976 }
5978 /* Classify the argument of type TYPE and mode MODE.
5979 CLASSES will be filled by the register class used to pass each word
5980 of the operand. The number of words is returned. In case the parameter
5981 should be passed in memory, 0 is returned. As a special case for zero
5982 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5984 BIT_OFFSET is used internally for handling records and specifies offset
5985 of the offset in bits modulo 256 to avoid overflow cases.
5987 See the x86-64 PS ABI for details.
5988 */
5990 static int
5993 {
5994 HOST_WIDE_INT bytes =
5998 /* Variable sized entities are always passed/returned in memory. */
6006 /* Special case check for pointer to shared, on 64-bit target. */
6010 {
6013 }
6016 {
6018 tree field;
6021 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
6028 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6029 signalize memory class, so handle it as special case. */
6031 {
6034 }
6036 /* Classify each field of record and merge classes. */
6038 {
6040 /* And now merge the fields of structure. */
6042 {
6044 {
6050 /* Bitfields are always classified as integer. Handle them
6051 early, since later code would consider them to be
6052 misaligned integers. */
6054 {
6062 }
6063 else
6064 {
6069 /* Flexible array member is ignored. */
6076 {
6080 {
6083 "the ABI of passing struct with"
6084 " a flexible array member has"
6086 }
6088 }
6090 subclasses,
6099 }
6100 }
6101 }
6105 /* Arrays are handled as small records. */
6106 {
6113 /* The partial classes are now full classes. */
6124 }
6127 /* Unions are similar to RECORD_TYPE but offset is always 0.
6128 */
6130 {
6132 {
6140 bit_offset);
6145 }
6146 }
6151 }
6154 {
6155 /* When size > 16 bytes, if the first one isn't
6156 X86_64_SSE_CLASS or any other ones aren't
6157 X86_64_SSEUP_CLASS, everything should be passed in
6158 memory. */
6165 }
6167 /* Final merger cleanup. */
6169 {
6170 /* If one class is MEMORY, everything should be passed in
6171 memory. */
6175 /* The X86_64_SSEUP_CLASS should be always preceded by
6176 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6180 {
6181 /* The first one should never be X86_64_SSEUP_CLASS. */
6184 }
6186 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6187 everything should be passed in memory. */
6190 {
6193 /* The first one should never be X86_64_X87UP_CLASS. */
6196 {
6199 "the ABI of passing union with long double"
6201 }
6203 }
6204 }
6206 }
6208 /* Compute alignment needed. We align all types to natural boundaries with
6209 exception of XFmode that is aligned to 64bits. */
6211 {
6220 /* Misaligned fields are always returned in memory. */
6223 }
6225 /* for V1xx modes, just use the base mode */
6230 /* Classification of atomic types. */
6232 {
6248 {
6252 {
6255 }
6257 {
6260 }
6262 {
6266 }
6268 {
6271 }
6272 else
6274 }
6281 /* OImode shouldn't be used directly. */
6288 else
6306 else
6307 {
6311 {
6314 "the ABI of passing structure with complex float"
6316 }
6319 }
6328 /* This modes is larger than 16 bytes. */
6371 else
6375 }
6376 }
6378 /* Examine the argument and return set number of register required in each
6379 class. Return 0 iff parameter should be passed in memory. */
6380 static int
6383 {
6393 {
6415 }
6417 }
6419 /* Construct container for the argument used by GCC interface. See
6420 FUNCTION_ARG for the detailed description. */
6422 static rtx
6426 {
6427 /* The following variables hold the static issued_error state. */
6441 rtx ret;
6452 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6453 some less clueful developer tries to use floating-point anyway. */
6455 {
6457 {
6459 {
6462 }
6463 }
6465 {
6468 }
6470 }
6472 /* Likewise, error if the ABI requires us to return values in the
6473 x87 registers and the user specified -mno-80387. */
6479 {
6481 {
6484 }
6486 }
6488 /* First construct simple cases. Avoid SCmode, since we want to use
6489 single register to pass this type. */
6492 {
6507 /* Zero sized array, struct or class. */
6511 }
6532 /* Otherwise figure out the entries of the PARALLEL. */
6534 {
6538 {
6543 /* Merge TImodes on aligned occasions here too. */
6548 else
6550 /* We've requested 24 bytes we don't have mode for. Use DImode. */
6556 intreg++;
6563 sse_regno++;
6570 sse_regno++;
6575 {
6581 {
6583 i++;
6584 }
6585 else
6598 }
6603 sse_regno++;
6607 }
6608 }
6610 /* Empty aligned struct, union or class. */
6618 }
6620 /* Update the data in CUM to advance over an argument of mode MODE
6621 and data type TYPE. (TYPE is null for libcalls where that information
6622 may not be available.) */
6624 static void
6627 HOST_WIDE_INT words)
6628 {
6630 {
6637 /* FALLTHRU */
6648 {
6651 }
6655 /* OImode shouldn't be used directly. */
6664 /* FALLTHRU */
6680 {
6685 {
6688 }
6689 }
6699 {
6704 {
6707 }
6708 }
6710 }
6711 }
6713 static void
6716 {
6719 /* Unnamed 256bit vector mode parameters are passed on stack. */
6725 {
6730 }
6731 else
6732 {
6736 }
6737 }
6739 static void
6741 HOST_WIDE_INT words)
6742 {
6743 /* Otherwise, this should be passed indirect. */
6748 {
6751 }
6752 }
6754 /* Update the data in CUM to advance over an argument of mode MODE and
6755 data type TYPE. (TYPE is null for libcalls where that information
6756 may not be available.) */
6758 static void
6761 {
6766 else
6777 else
6779 }
6781 /* Define where to put the arguments to a function.
6782 Value is zero to push the argument on the stack,
6783 or a hard register in which to store the argument.
6785 MODE is the argument's machine mode.
6786 TYPE is the data type of the argument (as a tree).
6787 This is null for libcalls where that information may
6788 not be available.
6789 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6790 the preceding args and about the function being called.
6791 NAMED is nonzero if this argument is a named parameter
6792 (otherwise it is an extra parameter matching an ellipsis). */
6794 static rtx
6798 {
6801 /* Avoid the AL settings for the Unix64 ABI. */
6806 {
6813 /* FALLTHRU */
6819 {
6822 /* Fastcall allocates the first two DWORD (SImode) or
6823 smaller arguments to ECX and EDX if it isn't an
6824 aggregate type . */
6826 {
6832 /* ECX not EAX is the first allocated register. */
6835 }
6837 }
6846 /* FALLTHRU */
6848 /* In 32bit, we pass TImode in xmm registers. */
6856 {
6858 {
6862 }
6866 }
6870 /* OImode shouldn't be used directly. */
6880 {
6884 }
6894 {
6896 {
6900 }
6904 }
6906 }
6909 }
6911 static rtx
6914 {
6915 /* Handle a hidden AL argument containing number of registers
6916 for varargs x86-64 functions. */
6920 ? X86_64_SSE_REGPARM_MAX
6925 {
6935 /* Unnamed 256bit vector mode parameters are passed on stack. */
6939 }
6945 }
6947 static rtx
6950 HOST_WIDE_INT bytes)
6951 {
6954 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6955 We use value of -2 to specify that current function call is MSABI. */
6959 /* If we've run out of registers, it goes on the stack. */
6965 /* Only floating point modes are passed in anything but integer regs. */
6967 {
6970 else
6971 {
6974 /* Unnamed floating parameters are passed in both the
6975 SSE and integer registers. */
6981 }
6982 }
6983 /* Handle aggregated types passed in register. */
6985 {
6990 }
6993 }
6995 /* Return where to put the arguments to a function.
6996 Return zero to push the argument on the stack, or a hard register in which to store the argument.
6998 MODE is the argument's machine mode. TYPE is the data type of the
6999 argument. It is null for libcalls where that information may not be
7000 available. CUM gives information about the preceding args and about
7001 the function being called. NAMED is nonzero if this argument is a
7002 named parameter (otherwise it is an extra parameter matching an
7003 ellipsis). */
7005 static rtx
7008 {
7011 rtx arg;
7015 else
7019 /* To simplify the code below, represent vector types with a vector mode
7020 even if MMX/SSE are not active. */
7028 else
7032 {
7033 /* This argument uses 256bit AVX modes. */
7036 else
7038 }
7041 }
7043 /* A C expression that indicates when an argument must be passed by
7044 reference. If nonzero for an argument, a copy of that argument is
7045 made in memory and a pointer to the argument is passed instead of
7046 the argument itself. The pointer is passed in whatever way is
7047 appropriate for passing a pointer to that type. */
7049 static bool
7053 {
7054 /* See Windows x64 Software Convention. */
7056 {
7059 {
7060 /* Arrays are passed by reference. */
7065 {
7066 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7067 are passed by reference. */
7069 }
7070 }
7072 /* __m128 is passed by reference. */
7078 }
7079 }
7084 }
7086 /* Return true when TYPE should be 128bit aligned for 32bit argument
7087 passing ABI. XXX: This function is obsolete and is only used for
7088 checking psABI compatibility with previous versions of GCC. */
7090 static bool
7092 {
7104 {
7105 /* Walk the aggregates recursively. */
7107 {
7111 {
7112 tree field;
7114 /* Walk all the structure fields. */
7116 {
7120 }
7122 }
7125 /* Just for use if some languages passes arrays by value. */
7132 }
7133 }
7135 }
7137 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7138 XXX: This function is obsolete and is only used for checking psABI
7139 compatibility with previous versions of GCC. */
7141 static unsigned int
7144 {
7145 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7146 natural boundaries. */
7148 {
7149 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7150 make an exception for SSE modes since these require 128bit
7151 alignment.
7153 The handling here differs from field_alignment. ICC aligns MMX
7154 arguments to 4 byte boundaries, while structure fields are aligned
7155 to 8 byte boundaries. */
7157 {
7160 }
7161 else
7162 {
7165 }
7166 }
7170 }
7172 /* Return true when TYPE should be 128bit aligned for 32bit argument
7173 passing ABI. */
7175 static bool
7177 {
7187 {
7188 /* Walk the aggregates recursively. */
7190 {
7194 {
7195 tree field;
7197 /* Walk all the structure fields. */
7199 field;
7201 {
7205 }
7207 }
7210 /* Just for use if some languages passes arrays by value. */
7217 }
7218 }
7219 else
7223 }
7225 /* Gives the alignment boundary, in bits, of an argument with the
7226 specified mode and type. */
7228 static unsigned int
7230 {
7233 {
7234 /* Since the main variant type is used for call, we convert it to
7235 the main variant type. */
7238 }
7239 else
7243 else
7244 {
7249 {
7250 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7252 {
7255 }
7261 }
7264 && !warned
7266 saved_align))
7267 {
7270 "The ABI for passing parameters with %d-byte"
7273 }
7274 }
7277 }
7279 /* Return true if N is a possible register number of function value. */
7281 static bool
7283 {
7285 {
7290 /* TODO: The function should depend on current function ABI but
7291 builtins.c would need updating then. Therefore we use the
7292 default ABI. */
7304 }
7307 }
7309 /* Define how to find the value returned by a function.
7310 VALTYPE is the data type of the value (as a tree).
7311 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7312 otherwise, FUNC is 0. */
7314 static rtx
7317 {
7320 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7321 we normally prevent this case when mmx is not available. However
7322 some ABIs may require the result to be returned like DImode. */
7326 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7327 we prevent this case when sse is not available. However some ABIs
7328 may require the result to be returned like integer TImode. */
7333 /* 32-byte vector modes in %ymm0. */
7337 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7340 else
7341 /* Most things go in %eax. */
7344 /* Override FP return register with %xmm0 for local functions when
7345 SSE math is enabled or for functions with sseregparm attribute. */
7347 {
7352 }
7354 /* OImode shouldn't be used directly. */
7358 }
7360 static rtx
7362 const_tree valtype)
7363 {
7364 rtx ret;
7366 /* Handle libcalls, which don't provide a type node. */
7368 {
7370 {
7387 }
7388 }
7394 /* For zero sized structures, construct_container returns NULL, but we
7395 need to keep rest of compiler happy by returning meaningful value. */
7400 }
7402 static rtx
7404 {
7408 {
7410 {
7423 }
7424 }
7426 }
7428 static rtx
7431 {
7443 else
7445 }
7447 static rtx
7450 {
7456 }
7458 rtx
7460 {
7462 }
7464 /* Return true iff type is returned in memory. */
7466 static bool ATTRIBUTE_UNUSED
7468 {
7469 HOST_WIDE_INT size;
7480 {
7481 /* User-created vectors small enough to fit in EAX. */
7485 /* MMX/3dNow values are returned in MM0,
7486 except when it doesn't exits or the ABI prescribes otherwise. */
7490 /* SSE values are returned in XMM0, except when it doesn't exist. */
7494 /* AVX values are returned in YMM0, except when it doesn't exist. */
7497 }
7505 /* OImode shouldn't be used directly. */
7509 }
7511 static bool ATTRIBUTE_UNUSED
7513 {
7516 }
7518 static bool ATTRIBUTE_UNUSED
7520 {
7523 /* __m128 is returned in xmm0. */
7528 /* Otherwise, the size must be exactly in [1248]. */
7530 }
7532 static bool
7534 {
7535 #ifdef SUBTARGET_RETURN_IN_MEMORY
7537 #else
7541 {
7544 else
7546 }
7547 else
7549 #endif
7550 }
7552 /* When returning SSE vector types, we have a choice of either
7553 (1) being abi incompatible with a -march switch, or
7554 (2) generating an error.
7555 Given no good solution, I think the safest thing is one warning.
7556 The user won't be able to use -Werror, but....
7558 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
7559 called in response to actually generating a caller or callee that
7560 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
7561 via aggregate_value_p for general type probing from tree-ssa. */
7563 static rtx
7565 {
7569 {
7570 /* Look at the return type of the function, not the function type. */
7574 {
7577 {
7581 }
7582 }
7585 {
7587 {
7591 }
7592 }
7593 }
7596 }
7598 \f
7599 /* Create the va_list data type. */
7601 /* Returns the calling convention specific va_list date type.
7602 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
7604 static tree
7606 {
7609 /* For i386 we use plain pointer to argument area. */
7619 unsigned_type_node);
7622 unsigned_type_node);
7625 ptr_type_node);
7628 ptr_type_node);
7647 /* The correct type is an array type of one element. */
7649 }
7651 /* Setup the builtin va_list data type and for 64-bit the additional
7652 calling convention specific va_list data types. */
7654 static tree
7656 {
7659 /* Initialize abi specific va_list builtin types. */
7661 {
7662 tree t;
7664 {
7669 }
7670 else
7671 {
7676 }
7678 {
7683 }
7684 else
7685 {
7690 }
7691 }
7694 }
7696 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
7698 static void
7700 {
7702 alias_set_type set;
7705 /* GPR size of varargs save area. */
7708 else
7711 /* FPR size of varargs save area. We don't need it if we don't pass
7712 anything in SSE registers. */
7715 else
7729 {
7736 }
7739 {
7743 /* Now emit code to save SSE registers. The AX parameter contains number
7744 of SSE parameter registers used to call this function, though all we
7745 actually check here is the zero/non-zero status. */
7750 label));
7752 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
7753 we used movdqa (i.e. TImode) instead? Perhaps even better would
7754 be if we could determine the real mode of the data, via a hook
7755 into pass_stdarg. Ignore all that for now. */
7765 {
7773 }
7776 }
7777 }
7779 static void
7781 {
7786 {
7797 }
7798 }
7800 static void
7804 {
7805 CUMULATIVE_ARGS next_cum;
7806 tree fntype;
7808 /* This argument doesn't appear to be used anymore. Which is good,
7809 because the old code here didn't suppress rtl generation. */
7817 /* For varargs, we do not want to skip the dummy va_dcl argument.
7818 For stdargs, we do want to skip the last named argument. */
7825 else
7827 }
7829 /* Checks if TYPE is of kind va_list char *. */
7831 static bool
7833 {
7834 tree canonic;
7836 /* For 32-bit it is always true. */
7842 }
7844 /* Implement va_start. */
7846 static void
7848 {
7852 tree type;
7853 rtx ovf_rtx;
7857 {
7860 /* When we are splitting the stack, we can't refer to the stack
7861 arguments using internal_arg_pointer, because they may be on
7862 the old stack. The split stack prologue will arrange to
7863 leave a pointer to the old stack arguments in a scratch
7864 register, which we here copy to a pseudo-register. The split
7865 stack prologue can't set the pseudo-register directly because
7866 it (the prologue) runs before any registers have been saved. */
7870 {
7884 }
7885 }
7887 /* Only 64bit target needs something special. */
7889 {
7892 else
7893 {
7902 }
7904 }
7913 /* The following should be folded into the MEM_REF offset. */
7923 /* Count number of gp and fp argument registers used. */
7929 {
7935 }
7938 {
7944 }
7946 /* Find the overflow area. */
7950 else
7961 {
7962 /* Find the register save area.
7963 Prologue of the function save it right above stack frame. */
7972 }
7973 }
7975 /* Implement va_arg. */
7977 static tree
7980 {
7987 rtx container;
7989 tree ptrtype;
7993 /* Only 64bit target needs something special. */
8017 {
8024 /* Unnamed 256bit vector mode parameters are passed on stack. */
8026 {
8029 }
8037 }
8039 /* Pull the value out of the saved registers. */
8044 {
8058 /* In case we are passing structure, verify that it is consecutive block
8059 on the register save area. If not we need to do moves. */
8061 {
8062 /* Verify that all registers are strictly consecutive */
8064 {
8068 {
8073 }
8074 }
8075 else
8076 {
8080 {
8085 }
8086 }
8087 }
8089 {
8092 }
8093 else
8094 {
8097 }
8099 /* First ensure that we fit completely in registers. */
8101 {
8108 }
8110 {
8118 }
8120 /* Compute index to start of area used for integer regs. */
8122 {
8123 /* int_addr = gpr + sav; */
8127 }
8129 {
8130 /* sse_addr = fpr + sav; */
8134 }
8136 {
8140 /* addr = &temp; */
8145 {
8149 tree piece_type;
8150 tree addr_type;
8151 tree daddr_type;
8160 {
8165 }
8169 else
8176 {
8179 }
8180 else
8181 {
8184 }
8193 {
8198 }
8199 else
8200 {
8201 tree copy
8206 }
8208 }
8209 }
8212 {
8216 }
8219 {
8223 }
8228 }
8230 /* ... otherwise out of the overflow area. */
8232 /* When we align parameter on stack for caller, if the parameter
8233 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8234 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8235 here with caller. */
8240 /* Care for on-stack alignment if needed. */
8243 else
8244 {
8252 }
8270 }
8271 \f
8272 /* Return true if OPNUM's MEM should be matched
8273 in movabs* patterns. */
8275 bool
8277 {
8289 }
8290 \f
8291 /* Initialize the table of extra 80387 mathematical constants. */
8293 static void
8295 {
8297 {
8303 };
8307 {
8309 /* Ensure each constant is rounded to XFmode precision. */
8312 }
8315 }
8317 /* Return non-zero if the constant is something that
8318 can be loaded with a special instruction. */
8320 int
8322 {
8325 REAL_VALUE_TYPE r;
8337 /* For XFmode constants, try to find a special 80387 instruction when
8338 optimizing for size or on those CPUs that benefit from them. */
8341 {
8350 }
8352 /* Load of the constant -0.0 or -1.0 will be split as
8353 fldz;fchs or fld1;fchs sequence. */
8360 }
8362 /* Return the opcode of the special instruction to be used to load
8363 the constant X. */
8367 {
8369 {
8389 }
8390 }
8392 /* Return the CONST_DOUBLE representing the 80387 constant that is
8393 loaded by the specified special instruction. The argument IDX
8394 matches the return value from standard_80387_constant_p. */
8396 rtx
8398 {
8405 {
8416 }
8419 XFmode);
8420 }
8422 /* Return 1 if X is all 0s and 2 if x is all 1s
8423 in supported SSE vector mode. */
8425 int
8427 {
8434 {
8443 }
8446 }
8448 /* Return the opcode of the special instruction to be used to load
8449 the constant X. */
8453 {
8455 {
8458 {
8464 else
8469 else
8476 else
8481 else
8485 }
8490 }
8492 }
8494 /* Returns true if OP contains a symbol reference */
8496 bool
8498 {
8507 {
8509 {
8515 }
8519 }
8522 }
8524 /* Return true if it is appropriate to emit `ret' instructions in the
8525 body of a function. Do this only if the epilogue is simple, needing a
8526 couple of insns. Prior to reloading, we can't tell how many registers
8527 must be saved, so return false then. Return false if there is no frame
8528 marker to de-allocate. */
8530 bool
8532 {
8538 /* Don't allow more than 32k pop, since that's all we can do
8539 with one instruction. */
8546 }
8547 \f
8548 /* Value should be nonzero if functions must have frame pointers.
8549 Zero means the frame pointer need not be set up (and parms may
8550 be accessed via the stack pointer) in functions that seem suitable. */
8552 static bool
8554 {
8555 /* If we accessed previous frames, then the generated code expects
8556 to be able to access the saved ebp value in our frame. */
8560 /* Several x86 os'es need a frame pointer for other reasons,
8561 usually pertaining to setjmp. */
8565 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
8566 turns off the frame pointer by default. Turn it back on now if
8567 we've not got a leaf function. */
8569 && (!current_function_is_leaf
8577 }
8579 /* Record that the current function accesses previous call frames. */
8581 void
8583 {
8585 }
8586 \f
8587 #ifndef USE_HIDDEN_LINKONCE
8588 # if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
8589 # define USE_HIDDEN_LINKONCE 1
8590 # else
8591 # define USE_HIDDEN_LINKONCE 0
8592 # endif
8593 #endif
8597 /* Fills in the label name that should be used for a pc thunk for
8598 the given register. */
8600 static void
8602 {
8607 else
8609 }
8612 /* This function generates code for -fpic that loads %ebx with
8613 the return address of the caller and then returns. */
8615 static void
8617 {
8622 {
8624 tree decl;
8639 #if TARGET_MACHO
8641 {
8650 }
8651 else
8652 #endif
8654 {
8665 }
8666 else
8667 {
8670 }
8676 /* Make sure unwind info is emitted for the thunk if needed. */
8679 /* Pad stack IP move with 4 instructions (two NOPs count
8680 as one instruction). */
8682 {
8687 }
8698 }
8702 }
8704 /* Emit code for the SET_GOT patterns. */
8708 {
8714 {
8715 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
8720 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
8721 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
8722 an unadorned address. */
8727 }
8732 {
8737 else
8738 {
8740 #ifdef DWARF2_UNWIND_INFO
8741 /* The call to next label acts as a push. */
8743 {
8744 rtx insn;
8748 stack_pointer_rtx,
8753 }
8754 #endif
8755 }
8757 #if TARGET_MACHO
8758 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8759 is what will be referenced by the Mach-O PIC subsystem. */
8762 #endif
8768 {
8770 #ifdef DWARF2_UNWIND_INFO
8771 /* The pop is a pop and clobbers dest, but doesn't restore it
8772 for unwind info purposes. */
8774 {
8775 rtx insn;
8781 stack_pointer_rtx,
8786 }
8787 #endif
8788 }
8789 }
8790 else
8791 {
8796 #ifdef DWARF2_UNWIND_INFO
8797 /* Ensure all queued register saves are flushed before the
8798 call. */
8801 #endif
8805 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8806 is what will be referenced by the Mach-O PIC subsystem. */
8807 #if TARGET_MACHO
8810 else
8813 #endif
8814 }
8821 else
8825 }
8827 /* Generate an "push" pattern for input ARG. */
8829 static rtx
8831 {
8841 stack_pointer_rtx)),
8842 arg);
8843 }
8845 /* Generate an "pop" pattern for input ARG. */
8847 static rtx
8849 {
8851 arg,
8854 stack_pointer_rtx)));
8855 }
8857 /* Return >= 0 if there is an unused call-clobbered register available
8858 for the entire function. */
8860 static unsigned int
8862 {
8866 {
8868 /* Can't use the same register for both PIC and DRAP. */
8871 else
8876 }
8879 }
8881 /* Return 1 if we need to save REGNO. */
8882 static int
8884 {
8891 {
8895 }
8898 {
8901 {
8907 }
8908 }
8917 }
8919 /* Return number of saved general prupose registers. */
8921 static int
8923 {
8929 nregs ++;
8931 }
8933 /* Return number of saved SSE registrers. */
8935 static int
8937 {
8945 nregs ++;
8947 }
8949 /* Given FROM and TO register numbers, say whether this elimination is
8950 allowed. If stack alignment is needed, we can only replace argument
8951 pointer with hard frame pointer, or replace frame pointer with stack
8952 pointer. Otherwise, frame pointer elimination is automatically
8953 handled and all other eliminations are valid. */
8955 static bool
8957 {
8963 else
8965 }
8967 /* Return the offset between two registers, one to be eliminated, and the other
8968 its replacement, at the start of a routine. */
8970 HOST_WIDE_INT
8972 {
8981 else
8982 {
8990 }
8991 }
8993 /* In a dynamically-aligned function, we can't know the offset from
8994 stack pointer to frame pointer, so we must ensure that setjmp
8995 eliminates fp against the hard fp (%ebp) rather than trying to
8996 index from %esp up to the top of the frame across a gap that is
8997 of unknown (at compile-time) size. */
8998 static rtx
9000 {
9002 }
9004 /* On the x86 -fsplit-stack and -fstack-protector both use the same
9005 field in the TCB, so they can not be used together. */
9007 static bool
9010 {
9013 #ifndef TARGET_THREAD_SPLIT_STACK_OFFSET
9017 #else
9019 {
9024 }
9025 #endif
9028 }
9030 /* When using -fsplit-stack, the allocation routines set a field in
9031 the TCB to the bottom of the stack plus this much space, measured
9032 in bytes. */
9034 #define SPLIT_STACK_AVAILABLE 256
9036 /* Fill structure ix86_frame about frame of currently computed function. */
9038 static void
9040 {
9042 HOST_WIDE_INT offset;
9045 HOST_WIDE_INT to_allocate;
9053 /* MS ABI seem to require stack alignment to be always 16 except for function
9054 prologues and leaf. */
9058 {
9063 }
9069 /* For SEH we have to limit the amount of code movement into the prologue.
9070 At present we do this via a BLOCKAGE, at which point there's very little
9071 scheduling that can be done, which means that there's very little point
9072 in doing anything except PUSHs. */
9076 /* During reload iteration the amount of registers saved can change.
9077 Recompute the value as needed. Do not recompute when amount of registers
9078 didn't change as reload does multiple calls to the function and does not
9079 expect the decision to change within single iteration. */
9082 {
9088 /* The fast prologue uses move instead of push to save registers. This
9089 is significantly longer, but also executes faster as modern hardware
9090 can execute the moves in parallel, but can't do that for push/pop.
9092 Be careful about choosing what prologue to emit: When function takes
9093 many instructions to execute we may use slow version as well as in
9094 case function is known to be outside hot spot (this is known with
9095 feedback only). Weight the size of function by number of registers
9096 to save as it is cheap to use one or two push instructions but very
9097 slow to use many of them. */
9101 || (flag_branch_probabilities
9104 else
9107 }
9111 else
9114 /* If static stack checking is enabled and done with probes, the registers
9115 need to be saved before allocating the frame. */
9119 /* Skip return address. */
9122 /* Skip pushed static chain. */
9126 /* Skip saved base pointer. */
9131 /* The traditional frame pointer location is at the top of the frame. */
9134 /* Register save area */
9138 /* Align and set SSE register save area. */
9140 {
9141 /* The only ABI that has saved SSE registers (Win64) also has a
9142 16-byte aligned default stack, and thus we don't need to be
9143 within the re-aligned local stack frame to save them. */
9147 }
9150 /* The re-aligned stack starts here. Values before this point are not
9151 directly comparable with values below this point. In order to make
9152 sure that no value happens to be the same before and after, force
9153 the alignment computation below to add a non-zero value. */
9157 /* Va-arg area */
9161 /* Align start of frame for local function. */
9164 /* Frame pointer points here. */
9169 /* Add outgoing arguments area. Can be skipped if we eliminated
9170 all the function calls as dead code.
9171 Skipping is however impossible when function calls alloca. Alloca
9172 expander assumes that last crtl->outgoing_args_size
9173 of stack frame are unused. */
9177 {
9180 }
9181 else
9184 /* Align stack boundary. Only needed if we're calling another function
9185 or using alloca. */
9190 /* We've reached end of stack frame. */
9193 /* Size prologue needs to allocate. */
9201 && current_function_sp_is_unchanging
9202 && current_function_is_leaf
9204 {
9210 }
9211 else
9215 /* The SEH frame pointer location is near the bottom of the frame.
9216 This is enforced by the fact that the difference between the
9217 stack pointer and the frame pointer is limited to 240 bytes in
9218 the unwind data structure. */
9220 {
9221 HOST_WIDE_INT diff;
9223 /* If we can leave the frame pointer where it is, do so. */
9226 {
9227 /* Ideally we'd determine what portion of the local stack frame
9228 (within the constraint of the lowest 240) is most heavily used.
9229 But without that complication, simply bias the frame pointer
9230 by 128 bytes so as to maximize the amount of the local stack
9231 frame that is addressable with 8-bit offsets. */
9233 }
9234 }
9235 }
9237 /* This is semi-inlined memory_address_length, but simplified
9238 since we know that we're always dealing with reg+offset, and
9239 to avoid having to create and discard all that rtl. */
9243 {
9247 {
9248 /* EBP and R13 cannot be encoded without an offset. */
9250 }
9254 /* ESP and R12 must be encoded with a SIB byte. */
9256 len++;
9259 }
9261 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9262 The valid base registers are taken from CFUN->MACHINE->FS. */
9264 static rtx
9266 {
9272 {
9273 /* Choose the base register most likely to allow the most scheduling
9274 opportunities. Generally FP is valid througout the function,
9275 while DRAP must be reloaded within the epilogue. But choose either
9276 over the SP due to increased encoding size. */
9279 {
9282 }
9284 {
9287 }
9289 {
9292 }
9293 }
9294 else
9295 {
9296 HOST_WIDE_INT toffset;
9299 /* Choose the base register with the smallest address encoding.
9300 With a tie, choose FP > DRAP > SP. */
9302 {
9306 }
9308 {
9312 {
9316 }
9317 }
9319 {
9323 {
9327 }
9328 }
9329 }
9333 }
9335 /* Emit code to save registers in the prologue. */
9337 static void
9339 {
9341 rtx insn;
9345 {
9348 }
9349 }
9351 /* Emit a single register save at CFA - CFA_OFFSET. */
9353 static void
9355 HOST_WIDE_INT cfa_offset)
9356 {
9364 /* For SSE saves, we need to indicate the 128-bit alignment. */
9375 /* When saving registers into a re-aligned local stack frame, avoid
9376 any tricky guessing by dwarf2out. */
9378 {
9382 {
9383 /* A bit of a hack. We force the DRAP register to be saved in
9384 the re-aligned stack frame, which provides us with a copy
9385 of the CFA that will last past the prologue. Install it. */
9391 }
9392 else
9393 {
9394 /* The frame pointer is a stable reference within the
9395 aligned frame. Use it. */
9402 }
9403 }
9405 /* The memory may not be relative to the current CFA register,
9406 which means that we may need to generate a new pattern for
9407 use by the unwind info. */
9409 {
9413 }
9414 }
9416 /* Emit code to save registers using MOV insns.
9417 First register is stored at CFA - CFA_OFFSET. */
9418 static void
9420 {
9425 {
9428 }
9429 }
9431 /* Emit code to save SSE registers using MOV insns.
9432 First register is stored at CFA - CFA_OFFSET. */
9433 static void
9435 {
9440 {
9443 }
9444 }
9448 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9449 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9450 Don't add the note if the previously saved value will be left untouched
9451 within stack red-zone till return, as unwinders can find the same value
9452 in the register and on the stack. */
9454 static void
9456 {
9461 {
9464 }
9465 else
9466 queued_cfa_restores
9468 }
9470 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9472 static void
9474 {
9475 rtx last;
9479 ;
9484 }
9486 /* Expand prologue or epilogue stack adjustment.
9487 The pattern exist to put a dependency on all ebp-based memory accesses.
9488 STYLE should be negative if instructions should be marked as frame related,
9489 zero if %r11 register is live and cannot be freely used and positive
9490 otherwise. */
9492 static void
9495 {
9497 rtx insn;
9504 else
9505 {
9506 rtx tmp;
9507 /* r11 is used by indirect sibcall return as well, set before the
9508 epilogue and used after the epilogue. */
9511 else
9512 {
9516 }
9522 }
9529 {
9530 rtx r;
9540 }
9542 {
9545 {
9549 }
9550 }
9553 {
9558 {
9561 }
9563 {
9566 }
9567 else
9568 {
9569 /* Else there are two possibilities: SP itself, which we set
9570 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
9571 taken care of this by hand along the eh_return path. */
9574 }
9578 }
9579 }
9581 /* Find an available register to be used as dynamic realign argument
9582 pointer regsiter. Such a register will be written in prologue and
9583 used in begin of body, so it must not be
9584 1. parameter passing register.
9585 2. GOT pointer.
9586 We reuse static-chain register if it is available. Otherwise, we
9587 use DI for i386 and R13 for x86-64. We chose R13 since it has
9588 shorter encoding.
9590 Return: the regno of chosen register. */
9592 static unsigned int
9594 {
9598 {
9599 /* Use R13 for nested function or function need static chain.
9600 Since function with tail call may use any caller-saved
9601 registers in epilogue, DRAP must not use caller-saved
9602 register in such case. */
9607 }
9608 else
9609 {
9610 /* Use DI for nested function or function need static chain.
9611 Since function with tail call may use any caller-saved
9612 registers in epilogue, DRAP must not use caller-saved
9613 register in such case. */
9617 /* Reuse static chain register if it isn't used for parameter
9618 passing. */
9625 else
9627 }
9628 }
9630 /* Return minimum incoming stack alignment. */
9632 static unsigned int
9634 {
9637 /* Prefer the one specified at command line. */
9640 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
9641 if -mstackrealign is used, it isn't used for sibcall check and
9642 estimated stack alignment is 128bit. */
9644 && !TARGET_64BIT
9645 && ix86_force_align_arg_pointer
9648 else
9651 /* Incoming stack alignment can be changed on individual functions
9652 via force_align_arg_pointer attribute. We use the smallest
9653 incoming stack boundary. */
9659 /* The incoming stack frame has to be aligned at least at
9660 parm_stack_boundary. */
9664 /* Stack at entrance of main is aligned by runtime. We use the
9665 smallest incoming stack boundary. */
9673 }
9675 /* Update incoming stack boundary and estimated stack alignment. */
9677 static void
9679 {
9680 ix86_incoming_stack_boundary
9683 /* x86_64 vararg needs 16byte stack alignment for register save
9684 area. */
9689 }
9691 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
9692 needed or an rtx for DRAP otherwise. */
9694 static rtx
9696 {
9701 {
9702 /* Assign DRAP to vDRAP and returns vDRAP */
9704 rtx drap_vreg;
9705 rtx arg_ptr;
9718 {
9721 }
9723 }
9724 else
9726 }
9728 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
9730 static rtx
9732 {
9734 }
9737 rtx reg;
9739 };
9741 /* Return a short-lived scratch register for use on function entry.
9742 In 32-bit mode, it is valid only after the registers are saved
9743 in the prologue. This register must be released by means of
9744 release_scratch_register_on_entry once it is dead. */
9746 static void
9748 {
9754 {
9755 /* We always use R11 in 64-bit mode. */
9757 }
9758 else
9759 {
9761 bool fastcall_p
9765 int drap_regno
9768 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
9769 for the static chain register. */
9775 /* ecx is the static chain register. */
9781 /* esi is the static chain register. */
9787 else
9788 {
9791 }
9792 }
9796 {
9799 }
9800 }
9802 /* Release a scratch register obtained from the preceding function. */
9804 static void
9806 {
9808 {
9811 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
9816 }
9817 }
9819 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
9821 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
9823 static void
9825 {
9826 /* We skip the probe for the first interval + a small dope of 4 words and
9827 probe that many bytes past the specified size to maintain a protection
9828 area at the botton of the stack. */
9832 /* See if we have a constant small number of probes to generate. If so,
9833 that's the easy case. The run-time loop is made up of 11 insns in the
9834 generic case while the compile-time loop is made up of 3+2*(n-1) insns
9835 for n # of intervals. */
9837 {
9841 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
9842 values of N from 1 until it exceeds SIZE. If only one probe is
9843 needed, this will not generate any code. Then adjust and probe
9844 to PROBE_INTERVAL + SIZE. */
9846 {
9848 {
9851 }
9852 else
9858 }
9862 else
9869 /* Adjust back to account for the additional first interval. */
9873 }
9875 /* Otherwise, do the same as above, but in a loop. Note that we must be
9876 extra careful with variables wrapping around because we might be at
9877 the very top (or the very bottom) of the address space and we have
9878 to be able to handle this case properly; in particular, we use an
9879 equality test for the loop condition. */
9880 else
9881 {
9882 HOST_WIDE_INT rounded_size;
9888 /* Step 1: round SIZE to the previous multiple of the interval. */
9893 /* Step 2: compute initial and final value of the loop counter. */
9895 /* SP = SP_0 + PROBE_INTERVAL. */
9900 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
9904 stack_pointer_rtx)));
9907 /* Step 3: the loop
9909 while (SP != LAST_ADDR)
9910 {
9911 SP = SP + PROBE_INTERVAL
9912 probe at SP
9913 }
9915 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
9916 values of N from 1 until it is equal to ROUNDED_SIZE. */
9921 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
9922 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
9925 {
9930 }
9932 /* Adjust back to account for the additional first interval. */
9938 }
9943 /* Make sure nothing is scheduled before we are done. */
9945 }
9947 /* Adjust the stack pointer up to REG while probing it. */
9951 {
9961 /* Jump to END_LAB if SP == LAST_ADDR. */
9969 /* SP = SP + PROBE_INTERVAL. */
9973 /* Probe at SP. */
9984 }
9986 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
9987 inclusive. These are offsets from the current stack pointer. */
9989 static void
9991 {
9992 /* See if we have a constant small number of probes to generate. If so,
9993 that's the easy case. The run-time loop is made up of 7 insns in the
9994 generic case while the compile-time loop is made up of n insns for n #
9995 of intervals. */
9997 {
9998 HOST_WIDE_INT i;
10000 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10001 it exceeds SIZE. If only one probe is needed, this will not
10002 generate any code. Then probe at FIRST + SIZE. */
10007 }
10009 /* Otherwise, do the same as above, but in a loop. Note that we must be
10010 extra careful with variables wrapping around because we might be at
10011 the very top (or the very bottom) of the address space and we have
10012 to be able to handle this case properly; in particular, we use an
10013 equality test for the loop condition. */
10014 else
10015 {
10022 /* Step 1: round SIZE to the previous multiple of the interval. */
10027 /* Step 2: compute initial and final value of the loop counter. */
10029 /* TEST_OFFSET = FIRST. */
10032 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10036 /* Step 3: the loop
10038 while (TEST_ADDR != LAST_ADDR)
10039 {
10040 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10041 probe at TEST_ADDR
10042 }
10044 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10045 until it is equal to ROUNDED_SIZE. */
10050 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10051 that SIZE is equal to ROUNDED_SIZE. */
10055 stack_pointer_rtx,
10060 }
10062 /* Make sure nothing is scheduled before we are done. */
10064 }
10066 /* Probe a range of stack addresses from REG to END, inclusive. These are
10067 offsets from the current stack pointer. */
10071 {
10081 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10089 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10093 /* Probe at TEST_ADDR. */
10106 }
10108 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10109 to be generated in correct form. */
10110 static void
10112 {
10113 /* Check if stack realign is really needed after reload, and
10114 stores result in cfun */
10115 unsigned int incoming_stack_boundary
10119 < (current_function_is_leaf
10124 {
10125 /* After stack_realign_needed is finalized, we can't no longer
10126 change it. */
10128 }
10129 else
10130 {
10133 }
10134 }
10136 /* Expand the prologue into a bunch of separate insns. */
10138 void
10140 {
10145 HOST_WIDE_INT allocate;
10150 /* DRAP should not coexist with stack_realign_fp */
10155 /* Initialize CFA state for before the prologue. */
10159 /* Track SP offset to the CFA. We continue tracking this after we've
10160 swapped the CFA register away from SP. In the case of re-alignment
10161 this is fudged; we're interested to offsets within the local frame. */
10168 {
10169 /* We should have already generated an error for any use of
10170 ms_hook on a nested function. */
10173 /* Check if profiling is active and we shall use profiling before
10174 prologue variant. If so sorry. */
10179 /* In ix86_asm_output_function_label we emitted:
10180 8b ff movl.s %edi,%edi
10181 55 push %ebp
10182 8b ec movl.s %esp,%ebp
10184 This matches the hookable function prologue in Win32 API
10185 functions in Microsoft Windows XP Service Pack 2 and newer.
10186 Wine uses this to enable Windows apps to hook the Win32 API
10187 functions provided by Wine.
10189 What that means is that we've already set up the frame pointer. */
10193 {
10196 /* We've decided to use the frame pointer already set up.
10197 Describe this to the unwinder by pretending that both
10198 push and mov insns happen right here.
10200 Putting the unwind info here at the end of the ms_hook
10201 is done so that we can make absolutely certain we get
10202 the required byte sequence at the start of the function,
10203 rather than relying on an assembler that can produce
10204 the exact encoding required.
10206 However it does mean (in the unpatched case) that we have
10207 a 1 insn window where the asynchronous unwind info is
10208 incorrect. However, if we placed the unwind info at
10209 its correct location we would have incorrect unwind info
10210 in the patched case. Which is probably all moot since
10211 I don't expect Wine generates dwarf2 unwind info for the
10212 system libraries that use this feature. */
10218 stack_pointer_rtx);
10226 /* Note that gen_push incremented m->fs.cfa_offset, even
10227 though we didn't emit the push insn here. */
10231 }
10232 else
10233 {
10234 /* The frame pointer is not needed so pop %ebp again.
10235 This leaves us with a pristine state. */
10237 }
10238 }
10240 /* The first insn of a function that accepts its static chain on the
10241 stack is to push the register that would be filled in by a direct
10242 call. This insn will be skipped by the trampoline. */
10244 {
10248 /* We don't want to interpret this push insn as a register save,
10249 only as a stack adjustment. The real copy of the register as
10250 a save will be done later, if needed. */
10255 }
10257 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10258 of DRAP is needed and stack realignment is really needed after reload */
10260 {
10263 /* Only need to push parameter pointer reg if it is caller saved. */
10265 {
10266 /* Push arg pointer reg */
10269 }
10271 /* Grab the argument pointer. */
10278 /* Align the stack. */
10280 stack_pointer_rtx,
10284 /* Replicate the return address on the stack so that return
10285 address can be reached via (argp - 1) slot. This is needed
10286 to implement macro RETURN_ADDR_RTX and intrinsic function
10287 expand_builtin_return_addr etc. */
10293 /* For the purposes of frame and register save area addressing,
10294 we've started over with a new frame. */
10297 }
10300 {
10301 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10302 slower on all targets. Also sdb doesn't like it. */
10307 {
10315 }
10316 }
10321 {
10322 /* If saving registers via PUSH, do so now. */
10324 {
10328 }
10330 /* When using red zone we may start register saving before allocating
10331 the stack frame saving one cycle of the prologue. However, avoid
10332 doing this if we have to probe the stack; at least on x86_64 the
10333 stack probe can turn into a call that clobbers a red zone location. */
10335 && (! TARGET_STACK_PROBE
10337 {
10340 }
10341 }
10344 {
10348 /* The computation of the size of the re-aligned stack frame means
10349 that we must allocate the size of the register save area before
10350 performing the actual alignment. Otherwise we cannot guarantee
10351 that there's enough storage above the realignment point. */
10358 /* Align the stack. */
10360 stack_pointer_rtx,
10363 /* For the purposes of register save area addressing, the stack
10364 pointer is no longer valid. As for the value of sp_offset,
10365 see ix86_compute_frame_layout, which we need to match in order
10366 to pass verification of stack_pointer_offset at the end. */
10369 }
10374 {
10375 /* We start to count from ARG_POINTER. */
10378 /* If it was realigned, take into account the fake frame. */
10380 {
10387 /* This over-estimates by 1 minimal-stack-alignment-unit but
10388 mitigates that by counting in the new return address slot. */
10389 current_function_dynamic_stack_size
10391 }
10394 }
10396 /* The stack has already been decremented by the instruction calling us
10397 so we need to probe unconditionally to preserve the protection area. */
10399 {
10400 /* We expect the registers to be saved when probes are used. */
10404 {
10407 }
10408 else
10409 {
10417 else
10419 }
10420 }
10423 ;
10426 {
10430 }
10431 else
10432 {
10446 {
10449 }
10451 {
10455 }
10460 /* Use the fact that AX still contains ALLOCATE. */
10461 adjust_stack_insn = (TARGET_64BIT
10462 ? gen_pro_epilogue_adjust_stack_di_sub
10468 /* Note that SEH directives need to continue tracking the stack
10469 pointer even after the frame pointer has been set up. */
10471 {
10480 }
10484 {
10489 }
10491 {
10494 }
10495 }
10498 /* If we havn't already set up the frame pointer, do so now. */
10500 {
10512 }
10523 {
10530 }
10533 {
10535 {
10537 {
10547 }
10548 else
10550 }
10551 else
10553 }
10555 /* In the pic_reg_used case, make sure that the got load isn't deleted
10556 when mcount needs it. Blockage to avoid call movement across mcount
10557 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
10558 note. */
10563 {
10564 /* vDRAP is setup but after reload it turns out stack realign
10565 isn't necessary, here we will emit prologue to setup DRAP
10566 without stack realign adjustment */
10569 }
10571 /* Prevent instructions from being scheduled into register save push
10572 sequence when access to the redzone area is done through frame pointer.
10573 The offset between the frame pointer and the stack pointer is calculated
10574 relative to the value of the stack pointer at the end of the function
10575 prologue, and moving instructions that access redzone area via frame
10576 pointer inside push sequence violates this assumption. */
10580 /* Emit cld instruction if stringops are used in the function. */
10584 /* SEH requires that the prologue end within 256 bytes of the start of
10585 the function. Prevent instruction schedules that would extend that. */
10588 }
10590 /* Emit code to restore REG using a POP insn. */
10592 static void
10594 {
10603 {
10604 /* Previously we'd represented the CFA as an expression
10605 like *(%ebp - 8). We've just popped that value from
10606 the stack, which means we need to reset the CFA to
10607 the drap register. This will remain until we restore
10608 the stack pointer. */
10612 /* This means that the DRAP register is valid for addressing too. */
10615 }
10618 {
10625 }
10627 /* When the frame pointer is the CFA, and we pop it, we are
10628 swapping back to the stack pointer as the CFA. This happens
10629 for stack frames that don't allocate other data, so we assume
10630 the stack pointer is now pointing at the return address, i.e.
10631 the function entry state, which makes the offset be 1 word. */
10633 {
10636 {
10644 }
10645 }
10646 }
10648 /* Emit code to restore saved registers using POP insns. */
10650 static void
10652 {
10658 }
10660 /* Emit code and notes for the LEAVE instruction. */
10662 static void
10664 {
10676 {
10685 }
10686 }
10688 /* Emit code to restore saved registers using MOV insns.
10689 First register is restored from CFA - CFA_OFFSET. */
10690 static void
10693 {
10699 {
10708 {
10709 /* Previously we'd represented the CFA as an expression
10710 like *(%ebp - 8). We've just popped that value from
10711 the stack, which means we need to reset the CFA to
10712 the drap register. This will remain until we restore
10713 the stack pointer. */
10717 /* This means that the DRAP register is valid for addressing. */
10719 }
10720 else
10724 }
10725 }
10727 /* Emit code to restore saved registers using MOV insns.
10728 First register is restored from CFA - CFA_OFFSET. */
10729 static void
10732 {
10737 {
10739 rtx mem;
10749 }
10750 }
10752 /* Restore function stack, frame, and registers. */
10754 void
10756 {
10767 || (current_function_sp_is_unchanging
10772 /* The FP must be valid if the frame pointer is present. */
10777 /* We must have *some* valid pointer to the stack frame. */
10780 /* The DRAP is never valid at this point. */
10783 /* See the comment about red zone and frame
10784 pointer usage in ix86_expand_prologue. */
10791 /* Determine the CFA offset of the end of the red-zone. */
10794 {
10795 /* The red-zone begins below the return address. */
10798 /* When the register save area is in the aligned portion of
10799 the stack, determine the maximum runtime displacement that
10800 matches up with the aligned frame. */
10804 }
10806 /* Special care must be taken for the normal return case of a function
10807 using eh_return: the eax and edx registers are marked as saved, but
10808 not restored along this path. Adjust the save location to match. */
10812 /* EH_RETURN requires the use of moves to function properly. */
10815 /* SEH requires the use of pops to identify the epilogue. */
10818 /* If we're only restoring one register and sp is not valid then
10819 using a move instruction to restore the register since it's
10820 less work than reloading sp and popping the register. */
10833 && TARGET_USE_LEAVE
10837 else
10841 {
10842 /* Ensure that the entire register save area is addressable via
10843 the stack pointer, if we will restore via sp. */
10848 {
10852 style,
10854 }
10855 }
10857 /* If there are any SSE registers to restore, then we have to do it
10858 via moves, since there's obviously no pop for SSE regs. */
10864 {
10865 rtx t;
10870 /* eh_return epilogues need %ecx added to the stack pointer. */
10872 {
10875 /* Stack align doesn't work with eh_return. */
10877 /* Neither does regparm nested functions. */
10881 {
10889 /* Note that we use SA as a temporary CFA, as the return
10890 address is at the proper place relative to it. We
10891 pretend this happens at the FP restore insn because
10892 prior to this insn the FP would be stored at the wrong
10893 offset relative to SA, and after this insn we have no
10894 other reasonable register to use for the CFA. We don't
10895 bother resetting the CFA to the SP for the duration of
10896 the return insn. */
10909 }
10910 else
10911 {
10919 {
10923 UNITS_PER_WORD));
10925 }
10926 }
10929 }
10930 }
10931 else
10932 {
10933 /* SEH requires that the function end with (1) a stack adjustment
10934 if necessary, (2) a sequence of pops, and (3) a return or
10935 jump instruction. Prevent insns from the function body from
10936 being scheduled into this sequence. */
10938 {
10939 /* Prevent a catch region from being adjacent to the standard
10940 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
10941 several other flags that would be interesting to test are
10942 not yet set up. */
10945 else
10947 }
10949 /* First step is to deallocate the stack frame so that we can
10950 pop the registers. */
10952 {
10957 }
10959 {
10963 style,
10965 }
10968 }
10970 /* If we used a stack pointer and haven't already got rid of it,
10971 then do so now. */
10973 {
10974 /* If the stack pointer is valid and pointing at the frame
10975 pointer store address, then we only need a pop. */
10978 /* Leave results in shorter dependency chains on CPUs that are
10979 able to grok it fast. */
10984 else
10985 {
10987 hard_frame_pointer_rtx,
10990 }
10991 }
10994 {
10996 rtx insn;
11022 }
11024 /* At this point the stack pointer must be valid, and we must have
11025 restored all of the registers. We may not have deallocated the
11026 entire stack frame. We've delayed this until now because it may
11027 be possible to merge the local stack deallocation with the
11028 deallocation forced by ix86_static_chain_on_stack. */
11033 {
11037 }
11039 /* Sibcall epilogues don't want a return instruction. */
11041 {
11044 }
11046 /* Emit vzeroupper if needed. */
11053 {
11056 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11057 address, do explicit add, and jump indirectly to the caller. */
11060 {
11062 rtx insn;
11064 /* There is no "pascal" calling convention in any 64bit ABI. */
11080 }
11081 else
11083 }
11084 else
11087 /* Restore the state back to the state from the prologue,
11088 so that it's correct for the next epilogue. */
11090 }
11092 /* Reset from the function's potential modifications. */
11094 static void
11096 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11097 {
11100 #if TARGET_MACHO
11101 /* Mach-O doesn't support labels at the end of objects, so if
11102 it looks like we might want one, insert a NOP. */
11103 {
11114 }
11115 #endif
11117 }
11119 /* Return a scratch register to use in the split stack prologue. The
11120 split stack prologue is used for -fsplit-stack. It is the first
11121 instructions in the function, even before the regular prologue.
11122 The scratch register can be any caller-saved register which is not
11123 used for parameters or for the static chain. */
11125 static unsigned int
11127 {
11130 else
11131 {
11141 {
11143 {
11147 }
11149 }
11151 {
11154 else
11155 {
11157 {
11161 }
11163 }
11164 }
11165 else
11166 {
11167 /* FIXME: We could make this work by pushing a register
11168 around the addition and comparison. */
11171 }
11172 }
11173 }
11175 /* A SYMBOL_REF for the function which allocates new stackspace for
11176 -fsplit-stack. */
11180 /* A SYMBOL_REF for the more stack function when using the large
11181 model. */
11185 /* Handle -fsplit-stack. These are the first instructions in the
11186 function, even before the regular prologue. */
11188 void
11190 {
11192 HOST_WIDE_INT allocate;
11197 rtx fn;
11205 /* This is the label we will branch to if we have enough stack
11206 space. We expect the basic block reordering pass to reverse this
11207 branch if optimizing, so that we branch in the unlikely case. */
11210 /* We need to compare the stack pointer minus the frame size with
11211 the stack boundary in the TCB. The stack boundary always gives
11212 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11213 can compare directly. Otherwise we need to do an addition. */
11216 UNSPEC_STACK_CHECK);
11221 else
11222 {
11224 rtx offset;
11226 /* We need a scratch register to hold the stack pointer minus
11227 the required frame size. Since this is the very start of the
11228 function, the scratch register can be any caller-saved
11229 register which is not used for parameters. */
11236 {
11237 /* We don't use ix86_gen_add3 in this case because it will
11238 want to split to lea, but when not optimizing the insn
11239 will not be split after this point. */
11242 offset)));
11243 }
11244 else
11245 {
11248 stack_pointer_rtx));
11249 }
11251 }
11257 /* Mark the jump as very likely to be taken. */
11265 /* Get more stack space. We pass in the desired stack space and the
11266 size of the arguments to copy to the new stack. In 32-bit mode
11267 we push the parameters; __morestack will return on a new stack
11268 anyhow. In 64-bit mode we pass the parameters in r10 and
11269 r11. */
11274 {
11280 /* If this function uses a static chain, it will be in %r10.
11281 Preserve it across the call to __morestack. */
11283 {
11284 rtx rax;
11289 }
11292 {
11293 HOST_WIDE_INT argval;
11295 /* When using the large model we need to load the address
11296 into a register, and we've run out of registers. So we
11297 switch to a different calling convention, and we call a
11298 different function: __morestack_large. We pass the
11299 argument size in the upper 32 bits of r10 and pass the
11300 frame size in the lower 32 bits. */
11305 split_stack_fn_large =
11309 {
11319 UNSPEC_GOT);
11325 }
11326 else
11333 }
11334 else
11335 {
11339 }
11342 }
11343 else
11344 {
11347 }
11353 /* In order to make call/return prediction work right, we now need
11354 to execute a return instruction. See
11355 libgcc/config/i386/morestack.S for the details on how this works.
11357 For flow purposes gcc must not see this as a return
11358 instruction--we need control flow to continue at the subsequent
11359 label. Therefore, we use an unspec. */
11363 /* If we are in 64-bit mode and this function uses a static chain,
11364 we saved %r10 in %rax before calling _morestack. */
11369 /* If this function calls va_start, we need to store a pointer to
11370 the arguments on the old stack, because they may not have been
11371 all copied to the new stack. At this point the old stack can be
11372 found at the frame pointer value used by __morestack, because
11373 __morestack has set that up before calling back to us. Here we
11374 store that pointer in a scratch register, and in
11375 ix86_expand_prologue we store the scratch register in a stack
11376 slot. */
11378 {
11380 rtx frame_reg;
11387 /* 64-bit:
11388 fp -> old fp value
11389 return address within this function
11390 return address of caller of this function
11391 stack arguments
11392 So we add three words to get to the stack arguments.
11394 32-bit:
11395 fp -> old fp value
11396 return address within this function
11397 first argument to __morestack
11398 second argument to __morestack
11399 return address of caller of this function
11400 stack arguments
11401 So we add five words to get to the stack arguments.
11402 */
11413 }
11418 /* If this function calls va_start, we now have to set the scratch
11419 register for the case where we do not call __morestack. In this
11420 case we need to set it based on the stack pointer. */
11422 {
11429 }
11430 }
11432 /* We may have to tell the dataflow pass that the split stack prologue
11433 is initializing a scratch register. */
11435 static void
11437 {
11439 {
11442 }
11443 }
11444 \f
11445 /* Extract the parts of an RTL expression that is a valid memory address
11446 for an instruction. Return 0 if the structure of the address is
11447 grossly off. Return -1 if the address contains ASHIFT, so it is not
11448 strictly valid, but still used for computing length of lea instruction. */
11450 int
11452 {
11457 rtx tmp;
11464 {
11469 do
11470 {
11475 }
11482 {
11485 {
11508 && TARGET_TLS_DIRECT_SEG_REFS
11511 else
11521 else
11536 }
11537 }
11538 }
11540 {
11543 }
11545 {
11546 /* We're called for lea too, which implements ashift on occasion. */
11556 }
11557 else
11560 /* Extract the integral value of scale. */
11562 {
11566 }
11571 /* Avoid useless 0 displacement. */
11575 /* Allow arg pointer and stack pointer as index if there is not scaling. */
11580 {
11581 rtx tmp;
11584 }
11586 /* Special case: %ebp cannot be encoded as a base without a displacement.
11587 Similarly %r13. */
11589 && base_reg
11598 /* Special case: on K6, [%esi] makes the instruction vector decoded.
11599 Avoid this by transforming to [%esi+0].
11600 Reload calls address legitimization without cfun defined, so we need
11601 to test cfun for being non-NULL. */
11607 /* Special case: encode reg+reg instead of reg*2. */
11611 /* Special case: scaling cannot be encoded without base or displacement. */
11622 }
11623 \f
11624 /* Return cost of the memory address x.
11625 For i386, it is better to use a complex address than let gcc copy
11626 the address into a reg and make a new pseudo. But not if the address
11627 requires to two regs - that would mean more pseudos with longer
11628 lifetimes. */
11629 static int
11631 {
11643 /* Attempt to minimize number of registers in the address. */
11649 cost++;
11656 cost++;
11658 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
11659 since it's predecode logic can't detect the length of instructions
11660 and it degenerates to vector decoded. Increase cost of such
11661 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
11662 to split such addresses or even refuse such addresses at all.
11664 Following addressing modes are affected:
11665 [base+scale*index]
11666 [scale*index+disp]
11667 [base+index]
11669 The first and last case may be avoidable by explicitly coding the zero in
11670 memory address, but I don't have AMD-K6 machine handy to check this
11671 theory. */
11680 }
11681 \f
11682 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
11683 this is used for to form addresses to local data when -fPIC is in
11684 use. */
11686 static bool
11688 {
11691 }
11693 /* Determine if a given RTX is a valid constant. We already know this
11694 satisfies CONSTANT_P. */
11696 bool
11698 {
11700 {
11705 {
11709 }
11714 /* Only some unspecs are valid as "constants". */
11717 {
11733 }
11735 /* We must have drilled down to a symbol. */
11740 /* FALLTHRU */
11743 /* TLS symbols are never valid. */
11747 /* DLLIMPORT symbols are never valid. */
11752 #if TARGET_MACHO
11753 /* mdynamic-no-pic */
11756 #endif
11772 }
11774 /* Otherwise we handle everything else in the move patterns. */
11776 }
11778 /* Determine if it's legal to put X into the constant pool. This
11779 is not possible for the address of thread-local symbols, which
11780 is checked above. */
11782 static bool
11784 {
11785 /* We can always put integral constants and vectors in memory. */
11787 {
11795 }
11797 }
11800 /* Nonzero if the constant value X is a legitimate general operand
11801 when generating PIC code. It is given that flag_pic is on and
11802 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
11804 bool
11806 {
11807 rtx inner;
11810 {
11817 /* Only some unspecs are valid as "constants". */
11820 {
11833 }
11834 /* FALLTHRU */
11842 }
11843 }
11845 /* Determine if a given CONST RTX is a valid memory displacement
11846 in PIC mode. */
11848 bool
11850 {
11853 /* In 64bit mode we can allow direct addresses of symbols and labels
11854 when they are not dynamic symbols. */
11856 {
11860 {
11877 /* FALLTHRU */
11880 /* TLS references should always be enclosed in UNSPEC. */
11890 }
11891 }
11897 {
11898 /* We are unsafe to allow PLUS expressions. This limit allowed distance
11899 of GOT tables. We should not need these anyway. */
11911 }
11915 {
11920 }
11929 {
11933 /* We need to check for both symbols and labels because VxWorks loads
11934 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
11935 details. */
11939 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
11940 While ABI specify also 32bit relocation but we don't produce it in
11941 small PIC model at all. */
11963 }
11966 }
11968 /* Recognizes RTL expressions that are valid memory addresses for an
11969 instruction. The MODE argument is the machine mode for the MEM
11970 expression that wants to use this address.
11972 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
11973 convert common non-canonical forms to canonical form so that they will
11974 be recognized. */
11976 static bool
11979 {
11982 HOST_WIDE_INT scale;
11985 /* Decomposition failed. */
11993 /* Validate base register.
11995 Don't allow SUBREG's that span more than a word here. It can lead to spill
11996 failures when the base is one word out of a two word structure, which is
11997 represented internally as a DImode int. */
12000 {
12001 rtx reg;
12010 else
12011 /* Base is not a register. */
12015 /* Base is not in Pmode. */
12020 /* Base is not valid. */
12022 }
12024 /* Validate index register.
12026 Don't allow SUBREG's that span more than a word here -- same as above. */
12029 {
12030 rtx reg;
12039 else
12040 /* Index is not a register. */
12044 /* Index is not in Pmode. */
12049 /* Index is not valid. */
12051 }
12053 /* Validate scale factor. */
12055 {
12057 /* Scale without index. */
12061 /* Scale is not a valid multiplier. */
12063 }
12065 /* Validate displacement. */
12067 {
12072 {
12073 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12074 used. While ABI specify also 32bit relocations, we don't produce
12075 them at all and use IP relative instead. */
12082 /* 64bit address unspec. */
12102 /* Invalid address unspec. */
12104 }
12107 && (flag_pic
12108 || (TARGET_MACHO
12109 #if TARGET_MACHO
12110 && MACHOPIC_INDIRECT
12112 #endif
12113 )))
12114 {
12116 is_legitimate_pic:
12118 {
12119 /* foo@dtpoff(%rX) is ok. */
12126 /* Non-constant pic memory reference. */
12128 }
12131 /* Displacement is an invalid pic construct. */
12133 #if TARGET_MACHO
12135 /* displacment must be referenced via non_lazy_pointer */
12137 #endif
12139 /* This code used to verify that a symbolic pic displacement
12140 includes the pic_offset_table_rtx register.
12142 While this is good idea, unfortunately these constructs may
12143 be created by "adds using lea" optimization for incorrect
12144 code like:
12146 int a;
12147 int foo(int i)
12148 {
12149 return *(&a+i);
12150 }
12152 This code is nonsensical, but results in addressing
12153 GOT table with pic_offset_table_rtx base. We can't
12154 just refuse it easily, since it gets matched by
12155 "addsi3" pattern, that later gets split to lea in the
12156 case output register differs from input. While this
12157 can be handled by separate addsi pattern for this case
12158 that never results in lea, this seems to be easier and
12159 correct fix for crash to disable this test. */
12160 }
12167 /* Displacement is not constant. */
12171 /* Displacement is out of range. */
12173 }
12175 /* Everything looks valid. */
12177 }
12179 /* Determine if a given RTX is a valid constant address. */
12181 bool
12183 {
12185 }
12186 \f
12187 /* Return a unique alias set for the GOT. */
12189 static alias_set_type
12191 {
12196 }
12198 /* Return a legitimate reference for ORIG (an address) using the
12199 register REG. If REG is 0, a new pseudo is generated.
12201 There are two types of references that must be handled:
12203 1. Global data references must load the address from the GOT, via
12204 the PIC reg. An insn is emitted to do this load, and the reg is
12205 returned.
12207 2. Static data references, constant pool addresses, and code labels
12208 compute the address as an offset from the GOT, whose base is in
12209 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
12210 differentiate them from global data objects. The returned
12211 address is the PIC reg + an unspec constant.
12213 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
12214 reg also appears in the address. */
12216 static rtx
12218 {
12221 rtx base;
12223 #if TARGET_MACHO
12225 {
12228 /* Use the generic Mach-O PIC machinery. */
12230 }
12231 #endif
12238 {
12239 rtx tmpreg;
12240 /* This symbol may be referenced via a displacement from the PIC
12241 base address (@GOTOFF). */
12248 {
12250 UNSPEC_GOTOFF);
12252 }
12253 else
12258 else
12263 {
12267 }
12269 }
12271 {
12272 /* This symbol may be referenced via a displacement from the PIC
12273 base address (@GOTOFF). */
12280 {
12282 UNSPEC_GOTOFF);
12284 }
12285 else
12291 {
12294 }
12295 }
12297 /* We can't use @GOTOFF for text labels on VxWorks;
12298 see gotoff_operand. */
12300 {
12302 {
12308 {
12311 }
12312 }
12314 /* For x64 PE-COFF there is no GOT table. So we use address
12315 directly. */
12317 {
12325 }
12327 {
12335 /* Use directly gen_movsi, otherwise the address is loaded
12336 into register for CSE. We don't want to CSE this addresses,
12337 instead we CSE addresses from the GOT table, so skip this. */
12340 }
12341 else
12342 {
12343 /* This symbol must be referenced via a load from the
12344 Global Offset Table (@GOT). */
12360 }
12361 }
12362 else
12363 {
12366 {
12368 {
12371 }
12372 else
12374 }
12376 {
12379 /* We must match stuff we generate before. Assume the only
12380 unspecs that can get here are ours. Not that we could do
12381 anything with them anyway.... */
12387 }
12389 {
12392 /* Check first to see if this is a constant offset from a @GOTOFF
12393 symbol reference. */
12396 {
12398 {
12402 UNSPEC_GOTOFF);
12408 {
12411 }
12412 }
12413 else
12414 {
12417 {
12421 }
12422 }
12423 }
12424 else
12425 {
12432 else
12433 {
12435 {
12438 }
12440 }
12441 }
12442 }
12443 }
12445 }
12446 \f
12447 /* Load the thread pointer. If TO_REG is true, force it into a register. */
12449 static rtx
12451 {
12463 }
12465 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
12466 false if we expect this to be used for a memory address and true if
12467 we expect to load the address into a register. */
12469 static rtx
12471 {
12476 {
12482 {
12492 }
12495 else
12499 {
12503 }
12511 {
12523 }
12526 else
12530 {
12535 }
12543 {
12547 }
12553 {
12556 }
12558 {
12563 }
12565 {
12569 }
12570 else
12571 {
12574 }
12584 {
12588 }
12589 else
12590 {
12594 }
12604 {
12607 }
12608 else
12609 {
12613 }
12618 }
12621 }
12623 /* Create or return the unique __imp_DECL dllimport symbol corresponding
12624 to symbol DECL. */
12627 htab_t dllimport_map;
12629 static tree
12631 {
12638 tree to;
12639 rtx rtl;
12683 }
12685 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
12686 true if we require the result be a register. */
12688 static rtx
12690 {
12691 tree imp_decl;
12692 rtx x;
12701 }
12703 /* Try machine-dependent ways of modifying an illegitimate address
12704 to be legitimate. If we find one, return the new, valid address.
12705 This macro is used in only one place: `memory_address' in explow.c.
12707 OLDX is the address as it was before break_out_memory_refs was called.
12708 In some cases it is useful to look at this to decide what needs to be done.
12710 It is always safe for this macro to do nothing. It exists to recognize
12711 opportunities to optimize the output.
12713 For the 80386, we handle X+REG by loading X into a register R and
12714 using R+REG. R will go in a general reg and indexing will be used.
12715 However, if REG is a broken-out memory address or multiplication,
12716 nothing needs to be done because REG can certainly go in a general reg.
12718 When -fpic is used, special handling is needed for symbolic references.
12719 See comments by legitimize_pic_address in i386.c for details. */
12721 static rtx
12724 {
12735 {
12739 }
12742 {
12749 {
12752 }
12753 }
12758 #if TARGET_MACHO
12761 #endif
12763 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
12767 {
12772 }
12775 {
12776 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
12781 {
12787 }
12792 {
12798 }
12800 /* Put multiply first if it isn't already. */
12802 {
12807 }
12809 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
12810 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
12811 created by virtual register instantiation, register elimination, and
12812 similar optimizations. */
12814 {
12820 }
12822 /* Canonicalize
12823 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
12824 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
12829 {
12830 rtx constant;
12834 {
12837 }
12839 {
12842 }
12843 else
12847 {
12853 }
12854 }
12860 {
12863 }
12866 {
12869 }
12877 {
12880 }
12886 {
12894 }
12897 {
12905 }
12906 }
12909 }
12910 \f
12911 /* Print an integer constant expression in assembler syntax. Addition
12912 and subtraction are the only arithmetic that may appear in these
12913 expressions. FILE is the stdio stream to write to, X is the rtx, and
12914 CODE is the operand print code from the output string. */
12916 static void
12918 {
12922 {
12931 else
12932 {
12935 /* Mark the decl as referenced so that cgraph will
12936 output the function. */
12940 #if TARGET_MACHO
12944 #endif
12946 }
12954 /* FALLTHRU */
12965 /* This used to output parentheses around the expression,
12966 but that does not work on the 386 (either ATT or BSD assembler). */
12972 {
12973 /* We can use %d if the number is <32 bits and positive. */
12978 else
12980 }
12981 else
12982 /* We can't handle floating point constants;
12983 TARGET_PRINT_OPERAND must handle them. */
12988 /* Some assemblers need integer constants to appear first. */
12990 {
12994 }
12995 else
12996 {
13001 }
13016 {
13020 }
13025 {
13044 /* FIXME: This might be @TPOFF in Sun ld too. */
13053 else
13063 else
13069 #if TARGET_MACHO
13074 #endif
13078 }
13083 }
13084 }
13086 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
13087 We need to emit DTP-relative relocations. */
13089 static void ATTRIBUTE_UNUSED
13091 {
13096 {
13104 }
13105 }
13107 /* Return true if X is a representation of the PIC register. This copes
13108 with calls from ix86_find_base_term, where the register might have
13109 been replaced by a cselib value. */
13111 static bool
13113 {
13117 else
13119 }
13121 /* Helper function for ix86_delegitimize_address.
13122 Attempt to delegitimize TLS local-exec accesses. */
13124 static rtx
13126 {
13151 {
13156 }
13162 }
13164 /* In the name of slightly smaller debug output, and to cater to
13165 general assembler lossage, recognize PIC+GOTOFF and turn it back
13166 into a direct symbol reference.
13168 On Darwin, this is necessary to avoid a crash, because Darwin
13169 has a different PIC label for each routine but the DWARF debugging
13170 information is not associated with any particular routine, so it's
13171 necessary to remove references to the PIC label from RTL stored by
13172 the DWARF output code. */
13174 static rtx
13176 {
13178 /* addend is NULL or some rtx if x is something+GOTOFF where
13179 something doesn't include the PIC register. */
13181 /* reg_addend is NULL or a multiple of some register. */
13183 /* const_addend is NULL or a const_int. */
13185 /* This is the result, or NULL. */
13194 {
13205 }
13212 /* %ebx + GOT/GOTOFF */
13213 ;
13215 {
13216 /* %ebx + %reg * scale + GOT/GOTOFF */
13222 else
13223 {
13226 }
13227 }
13228 else
13234 {
13237 }
13256 {
13257 /* If the rest of original X doesn't involve the PIC register, add
13258 addend and subtract pic_offset_table_rtx. This can happen e.g.
13259 for code like:
13260 leal (%ebx, %ecx, 4), %ecx
13261 ...
13262 movl foo@GOTOFF(%ecx), %edx
13263 in which case we return (%ecx - %ebx) + foo. */
13266 pic_offset_table_rtx),
13267 result);
13268 else
13270 }
13274 }
13276 /* If X is a machine specific address (i.e. a symbol or label being
13277 referenced as a displacement from the GOT implemented using an
13278 UNSPEC), then return the base term. Otherwise return X. */
13280 rtx
13282 {
13283 rtx term;
13286 {
13300 }
13303 }
13304 \f
13305 static void
13308 {
13312 {
13315 }
13320 {
13323 {
13342 }
13346 {
13365 }
13372 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
13373 Those same assemblers have the same but opposite lossage on cmov. */
13378 else
13383 {
13396 }
13404 {
13417 }
13420 /* ??? As above. */
13429 /* ??? As above. */
13434 else
13445 }
13447 }
13449 /* Print the name of register X to FILE based on its machine mode and number.
13450 If CODE is 'w', pretend the mode is HImode.
13451 If CODE is 'b', pretend the mode is QImode.
13452 If CODE is 'k', pretend the mode is SImode.
13453 If CODE is 'q', pretend the mode is DImode.
13454 If CODE is 'x', pretend the mode is V4SFmode.
13455 If CODE is 't', pretend the mode is V8SFmode.
13456 If CODE is 'h', pretend the reg is the 'high' byte register.
13457 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
13458 If CODE is 'd', duplicate the operand for AVX instruction.
13459 */
13461 void
13463 {
13478 {
13482 }
13500 else
13503 /* Irritatingly, AMD extended registers use different naming convention
13504 from the normal registers. */
13506 {
13509 {
13528 }
13530 }
13534 {
13537 {
13540 }
13541 /* FALLTHRU */
13547 /* FALLTHRU */
13550 normal:
13565 {
13570 }
13574 }
13578 {
13581 else
13583 }
13584 }
13586 /* Locate some local-dynamic symbol still in use by this function
13587 so that we can print its name in some tls_local_dynamic_base
13588 pattern. */
13590 static int
13592 {
13597 {
13600 }
13603 }
13607 {
13608 rtx insn;
13619 }
13621 /* Meaning of CODE:
13622 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
13623 C -- print opcode suffix for set/cmov insn.
13624 c -- like C, but print reversed condition
13625 F,f -- likewise, but for floating-point.
13626 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
13627 otherwise nothing
13628 R -- print the prefix for register names.
13629 z -- print the opcode suffix for the size of the current operand.
13630 Z -- likewise, with special suffixes for x87 instructions.
13631 * -- print a star (in certain assembler syntax)
13632 A -- print an absolute memory reference.
13633 w -- print the operand as if it's a "word" (HImode) even if it isn't.
13634 s -- print a shift double count, followed by the assemblers argument
13635 delimiter.
13636 b -- print the QImode name of the register for the indicated operand.
13637 %b0 would print %al if operands[0] is reg 0.
13638 w -- likewise, print the HImode name of the register.
13639 k -- likewise, print the SImode name of the register.
13640 q -- likewise, print the DImode name of the register.
13641 x -- likewise, print the V4SFmode name of the register.
13642 t -- likewise, print the V8SFmode name of the register.
13643 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
13644 y -- print "st(0)" instead of "st" as a register.
13645 d -- print duplicated register operand for AVX instruction.
13646 D -- print condition for SSE cmp instruction.
13647 P -- if PIC, print an @PLT suffix.
13648 X -- don't print any sort of PIC '@' suffix for a symbol.
13649 & -- print some in-use local-dynamic symbol name.
13650 H -- print a memory address offset by 8; used for sse high-parts
13651 Y -- print condition for XOP pcom* instruction.
13652 + -- print a branch hint as 'cs' or 'ds' prefix
13653 ; -- print a semicolon (after prefixes due to bug in older gas).
13654 @ -- print a segment register of thread base pointer load
13655 */
13657 void
13659 {
13661 {
13663 {
13670 {
13675 else
13678 }
13682 {
13688 /* Intel syntax. For absolute addresses, registers should not
13689 be surrounded by braces. */
13691 {
13696 }
13701 }
13739 {
13740 /* Opcodes don't get size suffixes if using Intel opcodes. */
13745 {
13763 output_operand_lossage
13766 }
13767 }
13770 warning
13772 /* FALLTHRU */
13775 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
13780 {
13782 {
13784 #ifdef HAVE_AS_IX86_FILDS
13786 #endif
13794 #ifdef HAVE_AS_IX86_FILDQ
13796 #else
13798 #endif
13803 }
13804 }
13806 {
13807 /* 387 opcodes don't get size suffixes
13808 if the operands are registers. */
13813 {
13829 }
13830 }
13831 else
13832 {
13833 output_operand_lossage
13836 }
13838 output_operand_lossage
13857 {
13860 }
13864 /* Little bit of braindamage here. The SSE compare instructions
13865 does use completely different names for the comparisons that the
13866 fp conditional moves. */
13868 {
13870 {
13917 }
13918 }
13919 else
13920 {
13922 {
13957 }
13958 }
13961 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
13963 {
13965 {
13972 }
13974 }
13975 #endif
13979 {
13981 "condition code, invalid operand code "
13984 }
13989 {
13991 "condition code, invalid operand code "
13994 }
13995 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
13998 #endif
14002 /* Like above, but reverse condition */
14004 /* Check to see if argument to %c is really a constant
14005 and not a condition code which needs to be reversed. */
14007 {
14009 "condition code, invalid operand "
14012 }
14017 {
14019 "condition code, invalid operand "
14022 }
14023 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14026 #endif
14031 /* It doesn't actually matter what mode we use here, as we're
14032 only going to use this for printing. */
14037 {
14038 rtx x;
14046 {
14051 {
14055 /* Emit hints only in the case default branch prediction
14056 heuristics would fail. */
14058 {
14059 /* We use 3e (DS) prefix for taken branches and
14060 2e (CS) prefix for not taken branches. */
14063 else
14065 }
14066 }
14067 }
14069 }
14073 {
14124 }
14128 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
14130 #endif
14137 /* The kernel uses a different segment register for performance
14138 reasons; a system call would not have to trash the userspace
14139 segment register, which would be expensive. */
14142 else
14148 }
14149 }
14155 {
14156 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
14159 {
14162 {
14171 else
14177 }
14179 /* Check for explicit size override (codes 'b', 'w' and 'k') */
14189 }
14192 /* Avoid (%rip) for call operands. */
14198 else
14200 }
14203 {
14204 REAL_VALUE_TYPE r;
14212 /* Sign extend 32bit SFmode immediate to 8 bytes. */
14215 else
14217 }
14219 /* These float cases don't actually occur as immediate operands. */
14221 {
14226 }
14230 {
14235 }
14237 else
14238 {
14239 /* We have patterns that allow zero sets of memory, for instance.
14240 In 64-bit mode, we should probably support all 8-byte vectors,
14241 since we can in fact encode that into an immediate. */
14243 {
14246 }
14249 {
14251 {
14254 }
14257 {
14260 else
14262 }
14263 }
14268 else
14270 }
14271 }
14273 static bool
14275 {
14278 }
14279 \f
14280 /* Print a memory operand whose address is ADDR. */
14282 static void
14284 {
14298 {
14309 }
14311 /* Use one byte shorter RIP relative addressing for 64bit mode. */
14313 {
14325 }
14327 {
14328 /* Displacement only requires special attention. */
14331 {
14335 }
14338 else
14340 }
14341 else
14342 {
14344 {
14346 {
14351 else
14353 }
14359 {
14364 }
14366 }
14367 else
14368 {
14372 {
14373 /* Pull out the offset of a symbol; print any symbol itself. */
14377 {
14381 }
14389 else
14391 }
14395 {
14398 {
14402 }
14403 }
14406 else
14410 {
14415 }
14417 }
14418 }
14419 }
14421 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
14423 static bool
14425 {
14426 rtx op;
14433 {
14436 /* FIXME: This might be @TPOFF in Sun ld. */
14447 else
14459 else
14466 #if TARGET_MACHO
14472 #endif
14475 {
14480 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
14482 #else
14484 #endif
14487 }
14492 }
14495 }
14496 \f
14497 /* Split one or more double-mode RTL references into pairs of half-mode
14498 references. The RTL can be REG, offsettable MEM, integer constant, or
14499 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
14500 split and "num" is its length. lo_half and hi_half are output arrays
14501 that parallel "operands". */
14503 void
14506 {
14511 {
14520 }
14525 {
14528 /* simplify_subreg refuse to split volatile memory addresses,
14529 but we still have to handle it. */
14531 {
14534 }
14535 else
14536 {
14543 }
14544 }
14545 }
14546 \f
14547 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
14548 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
14549 is the expression of the binary operation. The output may either be
14550 emitted here, or returned to the caller, like all output_* functions.
14552 There is no guarantee that the operands are the same mode, as they
14553 might be within FLOAT or FLOAT_EXTEND expressions. */
14555 #ifndef SYSV386_COMPAT
14556 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
14557 wants to fix the assemblers because that causes incompatibility
14558 with gcc. No-one wants to fix gcc because that causes
14559 incompatibility with assemblers... You can use the option of
14560 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
14561 #define SYSV386_COMPAT 1
14562 #endif
14566 {
14572 #ifdef ENABLE_CHECKING
14573 /* Even if we do not want to check the inputs, this documents input
14574 constraints. Which helps in understanding the following code. */
14584 else
14586 #endif
14589 {
14594 else
14603 else
14612 else
14621 else
14628 }
14631 {
14633 {
14637 else
14639 }
14640 else
14641 {
14645 else
14647 }
14649 }
14653 {
14657 {
14661 }
14663 /* know operands[0] == operands[1]. */
14666 {
14669 }
14672 {
14674 /* How is it that we are storing to a dead operand[2]?
14675 Well, presumably operands[1] is dead too. We can't
14676 store the result to st(0) as st(0) gets popped on this
14677 instruction. Instead store to operands[2] (which I
14678 think has to be st(1)). st(1) will be popped later.
14679 gcc <= 2.8.1 didn't have this check and generated
14680 assembly code that the Unixware assembler rejected. */
14682 else
14685 }
14689 else
14696 {
14699 }
14702 {
14705 }
14708 {
14709 #if SYSV386_COMPAT
14710 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
14711 derived assemblers, confusingly reverse the direction of
14712 the operation for fsub{r} and fdiv{r} when the
14713 destination register is not st(0). The Intel assembler
14714 doesn't have this brain damage. Read !SYSV386_COMPAT to
14715 figure out what the hardware really does. */
14718 else
14720 #else
14722 /* As above for fmul/fadd, we can't store to st(0). */
14724 else
14726 #endif
14728 }
14731 {
14732 #if SYSV386_COMPAT
14735 else
14737 #else
14740 else
14742 #endif
14744 }
14747 {
14750 else
14753 }
14755 {
14756 #if SYSV386_COMPAT
14758 #else
14760 #endif
14761 }
14762 else
14763 {
14764 #if SYSV386_COMPAT
14766 #else
14768 #endif
14769 }
14774 }
14778 }
14780 /* Return needed mode for entity in optimize_mode_switching pass. */
14782 int
14784 {
14787 /* The mode UNINITIALIZED is used to store control word after a
14788 function call or ASM pattern. The mode ANY specify that function
14789 has no requirements on the control word and make no changes in the
14790 bits we are interested in. */
14804 {
14827 }
14830 }
14832 /* Output code to initialize control word copies used by trunc?f?i and
14833 rounding patterns. CURRENT_MODE is set to current control word,
14834 while NEW_MODE is set to new control word. */
14836 void
14838 {
14840 rtx new_mode;
14851 {
14853 {
14855 /* round toward zero (truncate) */
14861 /* round down toward -oo */
14868 /* round up toward +oo */
14875 /* mask precision exception for nearbyint() */
14882 }
14883 }
14884 else
14885 {
14887 {
14889 /* round toward zero (truncate) */
14895 /* round down toward -oo */
14901 /* round up toward +oo */
14907 /* mask precision exception for nearbyint() */
14914 }
14915 }
14921 }
14923 /* Output code for INSN to convert a float to a signed int. OPERANDS
14924 are the insn operands. The output may be [HSD]Imode and the input
14925 operand may be [SDX]Fmode. */
14929 {
14934 /* Jump through a hoop or two for DImode, since the hardware has no
14935 non-popping instruction. We used to do this a different way, but
14936 that was somewhat fragile and broke with post-reload splitters. */
14946 else
14947 {
14952 else
14956 }
14959 }
14961 /* Output code for x87 ffreep insn. The OPNO argument, which may only
14962 have the values zero or one, indicates the ffreep insn's operand
14963 from the OPERANDS array. */
14967 {
14969 #ifdef HAVE_AS_IX86_FFREEP
14971 #else
14972 {
14982 }
14983 #endif
14986 }
14989 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
14990 should be used. UNORDERED_P is true when fucom should be used. */
14994 {
15000 {
15003 }
15004 else
15005 {
15008 }
15011 {
15020 else
15022 else
15025 else
15027 }
15034 {
15036 {
15039 }
15040 else
15042 }
15045 && stack_top_dies
15048 {
15049 /* If both the top of the 387 stack dies, and the other operand
15050 is also a stack register that dies, then this must be a
15051 `fcompp' float compare */
15054 {
15055 /* There is no double popping fcomi variant. Fortunately,
15056 eflags is immune from the fstp's cc clobbering. */
15059 else
15062 }
15063 else
15064 {
15067 else
15069 }
15070 }
15071 else
15072 {
15073 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
15076 {
15084 NULL,
15085 NULL,
15092 NULL,
15093 NULL,
15094 NULL,
15095 NULL
15096 };
15111 }
15112 }
15114 void
15116 {
15119 #ifdef ASM_QUAD
15122 #else
15124 #endif
15127 }
15129 void
15131 {
15134 #ifdef ASM_QUAD
15137 #else
15139 #endif
15140 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
15146 #if TARGET_MACHO
15148 {
15152 }
15153 #endif
15154 else
15157 }
15158 \f
15159 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
15160 for the target. */
15162 void
15164 {
15165 rtx tmp;
15167 /* We play register width games, which are only valid after reload. */
15170 /* Avoid HImode and its attendant prefix byte. */
15175 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
15177 {
15180 }
15183 }
15185 /* X is an unchanging MEM. If it is a constant pool reference, return
15186 the constant pool rtx, else NULL. */
15188 rtx
15190 {
15197 }
15199 void
15201 {
15209 {
15212 {
15217 }
15221 }
15225 {
15238 {
15244 }
15245 }
15249 {
15251 {
15252 #if TARGET_MACHO
15253 /* dynamic-no-pic */
15255 {
15256 rtx temp = ((reload_in_progress
15264 }
15266 {
15270 }
15273 else
15274 {
15282 }
15283 /* dynamic-no-pic */
15284 #endif
15285 }
15286 else
15287 {
15291 {
15296 }
15297 }
15298 }
15299 else
15300 {
15311 /* Force large constants in 64bit compilation into register
15312 to get them CSEed. */
15324 {
15325 /* If we are loading a floating point constant to a register,
15326 force the value to memory now, since we'll get better code
15327 out the back end. */
15331 {
15336 }
15337 }
15338 }
15341 }
15343 void
15345 {
15349 /* Force constants other than zero into memory. We do not know how
15350 the instructions used to build constants modify the upper 64 bits
15351 of the register, once we have that information we may be able
15352 to handle some of them more efficiently. */
15361 /* We need to check memory alignment for SSE mode since attribute
15362 can make operands unaligned. */
15367 {
15370 /* ix86_expand_vector_move_misalign() does not like constants ... */
15376 /* ... nor both arguments in memory. */
15384 }
15386 /* Make operand1 a register if it isn't already. */
15390 {
15393 }
15396 }
15398 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
15399 straight to ix86_expand_vector_move. */
15400 /* Code generation for scalar reg-reg moves of single and double precision data:
15401 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
15402 movaps reg, reg
15403 else
15404 movss reg, reg
15405 if (x86_sse_partial_reg_dependency == true)
15406 movapd reg, reg
15407 else
15408 movsd reg, reg
15410 Code generation for scalar loads of double precision data:
15411 if (x86_sse_split_regs == true)
15412 movlpd mem, reg (gas syntax)
15413 else
15414 movsd mem, reg
15416 Code generation for unaligned packed loads of single precision data
15417 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
15418 if (x86_sse_unaligned_move_optimal)
15419 movups mem, reg
15421 if (x86_sse_partial_reg_dependency == true)
15422 {
15423 xorps reg, reg
15424 movlps mem, reg
15425 movhps mem+8, reg
15426 }
15427 else
15428 {
15429 movlps mem, reg
15430 movhps mem+8, reg
15431 }
15433 Code generation for unaligned packed loads of double precision data
15434 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
15435 if (x86_sse_unaligned_move_optimal)
15436 movupd mem, reg
15438 if (x86_sse_split_regs == true)
15439 {
15440 movlpd mem, reg
15441 movhpd mem+8, reg
15442 }
15443 else
15444 {
15445 movsd mem, reg
15446 movhpd mem+8, reg
15447 }
15448 */
15450 void
15452 {
15459 {
15461 {
15465 {
15467 /* If we're optimizing for size, movups is the smallest. */
15469 {
15474 }
15486 }
15493 {
15502 {
15507 }
15515 }
15520 }
15523 }
15526 {
15527 /* If we're optimizing for size, movups is the smallest. */
15530 {
15535 }
15537 /* ??? If we have typed data, then it would appear that using
15538 movdqu is the only way to get unaligned data loaded with
15539 integer type. */
15541 {
15546 }
15549 {
15550 rtx zero;
15553 {
15558 }
15560 /* When SSE registers are split into halves, we can avoid
15561 writing to the top half twice. */
15563 {
15566 }
15567 else
15568 {
15569 /* ??? Not sure about the best option for the Intel chips.
15570 The following would seem to satisfy; the register is
15571 entirely cleared, breaking the dependency chain. We
15572 then store to the upper half, with a dependency depth
15573 of one. A rumor has it that Intel recommends two movsd
15574 followed by an unpacklpd, but this is unconfirmed. And
15575 given that the dependency depth of the unpacklpd would
15576 still be one, I'm not sure why this would be better. */
15578 }
15584 }
15585 else
15586 {
15588 {
15593 }
15597 else
15606 }
15607 }
15609 {
15610 /* If we're optimizing for size, movups is the smallest. */
15613 {
15618 }
15620 /* ??? Similar to above, only less clear because of quote
15621 typeless stores unquote. */
15624 {
15629 }
15632 {
15634 {
15638 }
15639 else
15640 {
15645 }
15646 }
15647 else
15648 {
15653 {
15656 }
15657 else
15658 {
15663 }
15664 }
15665 }
15666 else
15668 }
15670 /* Expand a push in MODE. This is some mode for which we do not support
15671 proper push instructions, at least from the registers that we expect
15672 the value to live in. */
15674 void
15676 {
15677 rtx tmp;
15687 /* When we push an operand onto stack, it has to be aligned at least
15688 at the function argument boundary. However since we don't have
15689 the argument type, we can't determine the actual argument
15690 boundary. */
15692 }
15694 /* Helper function of ix86_fixup_binary_operands to canonicalize
15695 operand order. Returns true if the operands should be swapped. */
15697 static bool
15699 rtx operands[])
15700 {
15705 /* If the operation is not commutative, we can't do anything. */
15709 /* Highest priority is that src1 should match dst. */
15715 /* Next highest priority is that immediate constants come second. */
15721 /* Lowest priority is that memory references should come second. */
15728 }
15731 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
15732 destination to use for the operation. If different from the true
15733 destination in operands[0], a copy operation will be required. */
15735 rtx
15737 rtx operands[])
15738 {
15743 /* Canonicalize operand order. */
15745 {
15746 rtx temp;
15748 /* It is invalid to swap operands of different modes. */
15754 }
15756 /* Both source operands cannot be in memory. */
15758 {
15759 /* Optimization: Only read from memory once. */
15761 {
15764 }
15765 else
15767 }
15769 /* If the destination is memory, and we do not have matching source
15770 operands, do things in registers. */
15774 /* Source 1 cannot be a constant. */
15778 /* Source 1 cannot be a non-matching memory. */
15785 }
15787 /* Similarly, but assume that the destination has already been
15788 set up properly. */
15790 void
15793 {
15796 }
15798 /* Attempt to expand a binary operator. Make the expansion closer to the
15799 actual machine, then just general_operand, which will allow 3 separate
15800 memory references (one output, two input) in a single insn. */
15802 void
15804 rtx operands[])
15805 {
15812 /* Emit the instruction. */
15816 {
15817 /* Reload doesn't know about the flags register, and doesn't know that
15818 it doesn't want to clobber it. We can only do this with PLUS. */
15821 }
15825 {
15826 /* This is going to be an LEA; avoid splitting it later. */
15828 }
15829 else
15830 {
15833 }
15835 /* Fix up the destination if needed. */
15838 }
15840 /* Return TRUE or FALSE depending on whether the binary operator meets the
15841 appropriate constraints. */
15843 bool
15846 {
15851 /* Both source operands cannot be in memory. */
15855 /* Canonicalize operand order for commutative operators. */
15857 {
15861 }
15863 /* If the destination is memory, we must have a matching source operand. */
15867 /* Source 1 cannot be a constant. */
15871 /* Source 1 cannot be a non-matching memory. */
15873 {
15874 /* Support "andhi/andsi/anddi" as a zero-extending move. */
15882 }
15885 }
15887 /* Attempt to expand a unary operator. Make the expansion closer to the
15888 actual machine, then just general_operand, which will allow 2 separate
15889 memory references (one output, one input) in a single insn. */
15891 void
15893 rtx operands[])
15894 {
15901 /* If the destination is memory, and we do not have matching source
15902 operands, do things in registers. */
15905 {
15908 else
15910 }
15912 /* When source operand is memory, destination must match. */
15916 /* Emit the instruction. */
15920 {
15921 /* Reload doesn't know about the flags register, and doesn't know that
15922 it doesn't want to clobber it. */
15925 }
15926 else
15927 {
15930 }
15932 /* Fix up the destination if needed. */
15935 }
15937 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
15938 divisor are within the the range [0-255]. */
15940 void
15943 {
15952 {
15965 }
15972 /* Use 8bit unsigned divimod if dividend and divisor are within the
15973 the range [0-255]. */
15982 pc_rtx);
15987 /* Generate original signed/unsigned divimod. */
15992 /* Branch to the end. */
15996 /* Generate 8bit unsigned divide. */
15998 /* Don't use operands[0] for result of 8bit divide since not all
15999 registers support QImode ZERO_EXTRACT. */
16006 {
16009 }
16010 else
16011 {
16014 }
16016 /* Extract remainder from AH. */
16020 else
16021 {
16022 /* Need a new scratch register since the old one has result
16023 of 8bit divide. */
16027 }
16030 /* Zero extend quotient from AL. */
16036 }
16038 #define LEA_SEARCH_THRESHOLD 12
16040 /* Search backward for non-agu definition of register number REGNO1
16041 or register number REGNO2 in INSN's basic block until
16042 1. Pass LEA_SEARCH_THRESHOLD instructions, or
16043 2. Reach BB boundary, or
16044 3. Reach agu definition.
16045 Returns the distance between the non-agu definition point and INSN.
16046 If no definition point, returns -1. */
16048 static int
16050 rtx insn)
16051 {
16058 {
16061 {
16063 {
16064 distance++;
16070 {
16074 }
16075 }
16079 }
16080 }
16083 {
16084 edge e;
16085 edge_iterator ei;
16090 {
16093 }
16096 {
16101 {
16103 {
16104 distance++;
16110 {
16114 }
16115 }
16117 }
16118 }
16119 }
16123 done:
16124 /* get_attr_type may modify recog data. We want to make sure
16125 that recog data is valid for instruction INSN, on which
16126 distance_non_agu_define is called. INSN is unchanged here. */
16129 }
16131 /* Return the distance between INSN and the next insn that uses
16132 register number REGNO0 in memory address. Return -1 if no such
16133 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
16135 static int
16137 {
16144 {
16147 {
16149 {
16150 distance++;
16156 {
16157 /* Return DISTANCE if OP0 is used in memory
16158 address in NEXT. */
16160 }
16166 {
16167 /* Return -1 if OP0 is set in NEXT. */
16169 }
16170 }
16174 }
16175 }
16178 {
16179 edge e;
16180 edge_iterator ei;
16185 {
16188 }
16191 {
16196 {
16198 {
16199 distance++;
16205 {
16206 /* Return DISTANCE if OP0 is used in memory
16207 address in NEXT. */
16209 }
16215 {
16216 /* Return -1 if OP0 is set in NEXT. */
16218 }
16220 }
16222 }
16223 }
16224 }
16227 }
16229 /* Define this macro to tune LEA priority vs ADD, it take effect when
16230 there is a dilemma of choicing LEA or ADD
16231 Negative value: ADD is more preferred than LEA
16232 Zero: Netrual
16233 Positive value: LEA is more preferred than ADD*/
16234 #define IX86_LEA_PRIORITY 2
16236 /* Return true if it is ok to optimize an ADD operation to LEA
16237 operation to avoid flag register consumation. For most processors,
16238 ADD is faster than LEA. For the processors like ATOM, if the
16239 destination register of LEA holds an actual address which will be
16240 used soon, LEA is better and otherwise ADD is better. */
16242 bool
16244 {
16249 /* If a = b + c, (a!=b && a!=c), must use lea form. */
16255 else
16256 {
16259 /* Return false if REGNO0 isn't used in memory address. */
16268 /* If this insn has both backward non-agu dependence and forward
16269 agu dependence, the one with short distance take effect. */
16274 }
16275 }
16277 /* Return true if destination reg of SET_BODY is shift count of
16278 USE_BODY. */
16280 static bool
16282 {
16283 rtx set_dest;
16284 rtx shift_rtx;
16287 /* Retrieve destination of SET_BODY. */
16289 {
16298 use_body))
16303 }
16305 /* Retrieve shift count of USE_BODY. */
16307 {
16319 }
16327 {
16330 /* Return true if shift count is dest of SET_BODY. */
16334 }
16337 }
16339 /* Return true if destination reg of SET_INSN is shift count of
16340 USE_INSN. */
16342 bool
16344 {
16347 }
16349 /* Return TRUE or FALSE depending on whether the unary operator meets the
16350 appropriate constraints. */
16352 bool
16356 {
16357 /* If one of operands is memory, source and destination must match. */
16363 }
16365 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
16366 are ok, keeping in mind the possible movddup alternative. */
16368 bool
16370 {
16376 }
16378 /* Post-reload splitter for converting an SF or DFmode value in an
16379 SSE register into an unsigned SImode. */
16381 void
16383 {
16394 /* Load up the value into the low element. We must ensure that the other
16395 elements are valid floats -- zero is the easiest such value. */
16397 {
16400 else
16402 }
16403 else
16404 {
16409 else
16411 }
16431 else
16436 }
16438 /* Convert an unsigned DImode value into a DFmode, using only SSE.
16439 Expects the 64-bit DImode to be supplied in a pair of integral
16440 registers. Requires SSE2; will use SSE3 if available. For x86_32,
16441 -mfpmath=sse, !optimize_size only. */
16443 void
16445 {
16449 rtx x;
16455 {
16458 }
16459 else
16460 {
16464 }
16472 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
16475 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
16476 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
16477 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
16478 (0x1.0p84 + double(fp_value_hi_xmm)).
16479 Note these exponents differ by 32. */
16483 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
16484 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
16493 /* Add the upper and lower DFmode values together. */
16496 else
16497 {
16501 }
16504 }
16506 /* Not used, but eases macroization of patterns. */
16507 void
16509 rtx input ATTRIBUTE_UNUSED)
16510 {
16512 }
16514 /* Convert an unsigned SImode value into a DFmode. Only currently used
16515 for SSE, but applicable anywhere. */
16517 void
16519 {
16520 REAL_VALUE_TYPE TWO31r;
16535 }
16537 /* Convert a signed DImode value into a DFmode. Only used for SSE in
16538 32-bit mode; otherwise we have a direct convert instruction. */
16540 void
16542 {
16543 REAL_VALUE_TYPE TWO32r;
16561 }
16563 /* Convert an unsigned SImode value into a SFmode, using only SSE.
16564 For x86_32, -mfpmath=sse, !optimize_size only. */
16565 void
16567 {
16568 REAL_VALUE_TYPE ONE16r;
16587 }
16589 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
16590 then replicate the value for all elements of the vector
16591 register. */
16593 rtx
16595 {
16596 rtvec v;
16598 {
16613 else
16623 else
16631 else
16639 else
16645 }
16646 }
16648 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
16649 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
16650 for an SSE register. If VECT is true, then replicate the mask for
16651 all elements of the vector register. If INVERT is true, then create
16652 a mask excluding the sign bit. */
16654 rtx
16656 {
16660 rtx v;
16661 rtx mask;
16663 /* Find the sign bit, sign extended to 2*HWI. */
16665 {
16683 else
16691 {
16694 }
16695 else
16696 {
16697 rtvec vec;
16703 {
16706 }
16707 else
16717 }
16722 }
16727 /* Force this value into the low part of a fp vector constant. */
16736 }
16738 /* Generate code for floating point ABS or NEG. */
16740 void
16742 rtx operands[])
16743 {
16754 {
16760 }
16762 /* NEG and ABS performed with SSE use bitwise mask operations.
16763 Create the appropriate mask now. */
16766 else
16776 {
16778 rtvec par;
16783 else
16784 {
16787 }
16789 }
16790 else
16792 }
16794 /* Expand a copysign operation. Special case operand 0 being a constant. */
16796 void
16798 {
16812 else
16816 {
16823 {
16826 else
16827 {
16831 }
16832 }
16842 else
16846 }
16847 else
16848 {
16858 else
16862 }
16863 }
16865 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
16866 be a constant, and so has already been expanded into a vector constant. */
16868 void
16870 {
16886 {
16889 }
16890 }
16892 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
16893 so we have to do two masks. */
16895 void
16897 {
16912 {
16913 /* Shouldn't happen often (it's useless, obviously), but when it does
16914 we'd generate incorrect code if we continue below. */
16917 }
16920 {
16931 }
16932 else
16933 {
16935 {
16937 }
16939 {
16943 }
16947 {
16950 }
16952 {
16957 }
16959 }
16963 }
16965 /* Return TRUE or FALSE depending on whether the first SET in INSN
16966 has source and destination with matching CC modes, and that the
16967 CC mode is at least as constrained as REQ_MODE. */
16969 bool
16971 {
16972 rtx set;
16983 {
16993 /* FALLTHRU */
16997 /* FALLTHRU */
17001 /* FALLTHRU */
17011 }
17014 }
17016 /* Generate insn patterns to do an integer compare of OPERANDS. */
17018 static rtx
17020 {
17027 /* This is very simple, but making the interface the same as in the
17028 FP case makes the rest of the code easier. */
17032 /* Return the test that should be put into the flags user, i.e.
17033 the bcc, scc, or cmov instruction. */
17035 }
17037 /* Figure out whether to use ordered or unordered fp comparisons.
17038 Return the appropriate mode to use. */
17040 enum machine_mode
17042 {
17043 /* ??? In order to make all comparisons reversible, we do all comparisons
17044 non-trapping when compiling for IEEE. Once gcc is able to distinguish
17045 all forms trapping and nontrapping comparisons, we can make inequality
17046 comparisons trapping again, since it results in better code when using
17047 FCOM based compares. */
17049 }
17051 enum machine_mode
17053 {
17057 {
17060 }
17063 {
17064 /* Only zero flag is needed. */
17068 /* Codes needing carry flag. */
17071 /* Detect overflow checks. They need just the carry flag. */
17075 else
17079 /* Detect overflow checks. They need just the carry flag. */
17083 else
17085 /* Codes possibly doable only with sign flag when
17086 comparing against zero. */
17091 else
17092 /* For other cases Carry flag is not required. */
17094 /* Codes doable only with sign flag when comparing
17095 against zero, but we miss jump instruction for it
17096 so we need to use relational tests against overflow
17097 that thus needs to be zero. */
17102 else
17104 /* strcmp pattern do (use flags) and combine may ask us for proper
17105 mode. */
17110 }
17111 }
17113 /* Return the fixed registers used for condition codes. */
17115 static bool
17117 {
17121 }
17123 /* If two condition code modes are compatible, return a condition code
17124 mode which is compatible with both. Otherwise, return
17125 VOIDmode. */
17127 static enum machine_mode
17129 {
17141 {
17155 {
17169 }
17173 /* These are only compatible with themselves, which we already
17174 checked above. */
17176 }
17177 }
17180 /* Return a comparison we can do and that it is equivalent to
17181 swap_condition (code) apart possibly from orderedness.
17182 But, never change orderedness if TARGET_IEEE_FP, returning
17183 UNKNOWN in that case if necessary. */
17185 static enum rtx_code
17187 {
17189 {
17200 }
17201 }
17203 /* Return cost of comparison CODE using the best strategy for performance.
17204 All following functions do use number of instructions as a cost metrics.
17205 In future this should be tweaked to compute bytes for optimize_size and
17206 take into account performance of various instructions on various CPUs. */
17208 static int
17210 {
17213 /* The cost of code using bit-twiddling on %ah. */
17215 {
17238 }
17241 {
17248 }
17249 }
17251 /* Return strategy to use for floating-point. We assume that fcomi is always
17252 preferrable where available, since that is also true when looking at size
17253 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
17255 enum ix86_fpcmp_strategy
17257 {
17258 /* Do fcomi/sahf based test when profitable. */
17267 }
17269 /* Swap, force into registers, or otherwise massage the two operands
17270 to a fp comparison. The operands are updated in place; the new
17271 comparison code is returned. */
17273 static enum rtx_code
17275 {
17281 /* All of the unordered compare instructions only work on registers.
17282 The same is true of the fcomi compare instructions. The XFmode
17283 compare instructions require registers except when comparing
17284 against zero or when converting operand 1 from fixed point to
17285 floating point. */
17294 {
17297 }
17298 else
17299 {
17300 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
17301 things around if they appear profitable, otherwise force op0
17302 into a register. */
17308 {
17311 {
17312 rtx tmp;
17315 }
17316 }
17322 {
17327 {
17330 }
17331 else
17333 }
17334 }
17336 /* Try to rearrange the comparison to make it cheaper. */
17340 {
17341 rtx tmp;
17346 }
17351 }
17353 /* Convert comparison codes we use to represent FP comparison to integer
17354 code that will result in proper branch. Return UNKNOWN if no such code
17355 is available. */
17357 enum rtx_code
17359 {
17361 {
17384 }
17385 }
17387 /* Generate insn patterns to do a floating point compare of OPERANDS. */
17389 static rtx
17391 {
17398 /* Do fcomi/sahf based test when profitable. */
17400 {
17405 tmp);
17413 tmp);
17422 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
17429 /* In the unordered case, we have to check C2 for NaN's, which
17430 doesn't happen to work out to anything nice combination-wise.
17431 So do some bit twiddling on the value we've got in AH to come
17432 up with an appropriate set of condition codes. */
17436 {
17440 {
17443 }
17444 else
17445 {
17451 }
17456 {
17461 }
17462 else
17463 {
17466 }
17471 {
17474 }
17475 else
17476 {
17480 }
17485 {
17491 }
17492 else
17493 {
17496 }
17501 {
17506 }
17507 else
17508 {
17511 }
17516 {
17521 }
17522 else
17523 {
17526 }
17540 }
17545 }
17547 /* Return the test that should be put into the flags user, i.e.
17548 the bcc, scc, or cmov instruction. */
17551 const0_rtx);
17552 }
17554 static rtx
17556 {
17557 rtx ret;
17563 {
17566 }
17567 else
17571 }
17573 void
17575 {
17577 rtx tmp;
17580 {
17587 simple:
17591 pc_rtx);
17599 /* Expand DImode branch into multiple compare+branch. */
17600 {
17606 {
17609 }
17616 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
17617 avoid two branches. This costs one extra insn, so disable when
17618 optimizing for size. */
17623 {
17641 }
17643 /* Otherwise, if we are doing less-than or greater-or-equal-than,
17644 op1 is a constant and the low word is zero, then we can just
17645 examine the high word. Similarly for low word -1 and
17646 less-or-equal-than or greater-than. */
17650 {
17653 {
17656 }
17660 {
17663 }
17667 }
17669 /* Otherwise, we need two or three jumps. */
17678 {
17692 }
17694 /*
17695 * a < b =>
17696 * if (hi(a) < hi(b)) goto true;
17697 * if (hi(a) > hi(b)) goto false;
17698 * if (lo(a) < lo(b)) goto true;
17699 * false:
17700 */
17712 }
17717 }
17718 }
17720 /* Split branch based on floating point condition. */
17721 void
17724 {
17725 rtx condition;
17726 rtx i;
17729 {
17734 }
17737 tmp);
17739 /* Remove pushed operand from stack. */
17749 }
17751 void
17753 {
17754 rtx ret;
17761 }
17763 /* Expand comparison setting or clearing carry flag. Return true when
17764 successful and set pop for the operation. */
17765 static bool
17767 {
17771 /* Do not handle double-mode compares that go through special path. */
17776 {
17781 /* Shortcut: following common codes never translate
17782 into carry flag compares. */
17787 /* These comparisons require zero flag; swap operands so they won't. */
17790 {
17795 }
17797 /* Try to expand the comparison and verify that we end up with
17798 carry flag based comparison. This fails to be true only when
17799 we decide to expand comparison using arithmetic that is not
17800 too common scenario. */
17809 else
17818 }
17824 {
17829 /* Convert a==0 into (unsigned)a<1. */
17838 /* Convert a>b into b<a or a>=b-1. */
17842 {
17844 /* Bail out on overflow. We still can swap operands but that
17845 would force loading of the constant into register. */
17850 }
17851 else
17852 {
17857 }
17860 /* Convert a>=0 into (unsigned)a<0x80000000. */
17878 }
17879 /* Swapping operands may cause constant to appear as first operand. */
17881 {
17885 }
17889 }
17891 bool
17893 {
17912 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
17913 HImode insns, we'd be swallowed in word prefix ops. */
17919 {
17923 HOST_WIDE_INT diff;
17926 /* Sign bit compares are better done using shifts than we do by using
17927 sbb. */
17930 {
17931 /* Detect overlap between destination and compare sources. */
17935 {
17936 rtx flags;
17945 {
17947 compare_code
17949 }
17951 /* To simplify rest of code, restrict to the GEU case. */
17953 {
17959 }
17960 else
17961 {
17964 reverse_condition_maybe_unordered
17966 else
17969 }
17978 else
17981 }
17982 else
17983 {
17986 else
17987 {
17992 }
17994 }
17997 {
17998 /*
17999 * cmpl op0,op1
18000 * sbbl dest,dest
18001 * [addl dest, ct]
18002 *
18003 * Size 5 - 8.
18004 */
18009 }
18011 {
18012 /*
18013 * cmpl op0,op1
18014 * sbbl dest,dest
18015 * orl $ct, dest
18016 *
18017 * Size 8.
18018 */
18022 }
18024 {
18025 /*
18026 * cmpl op0,op1
18027 * sbbl dest,dest
18028 * notl dest
18029 * [addl dest, cf]
18030 *
18031 * Size 8 - 11.
18032 */
18038 }
18039 else
18040 {
18041 /*
18042 * cmpl op0,op1
18043 * sbbl dest,dest
18044 * [notl dest]
18045 * andl cf - ct, dest
18046 * [addl dest, ct]
18047 *
18048 * Size 8 - 11.
18049 */
18052 {
18056 }
18066 }
18072 }
18075 {
18078 HOST_WIDE_INT tmp;
18083 {
18086 /* We may be reversing unordered compare to normal compare, that
18087 is not valid in general (we may convert non-trapping condition
18088 to trapping one), however on i386 we currently emit all
18089 comparisons unordered. */
18092 }
18093 else
18094 {
18097 }
18098 }
18103 {
18108 {
18113 }
18114 }
18116 /* Optimize dest = (op0 < 0) ? -1 : cf. */
18120 {
18121 /* If lea code below could be used, only optimize
18122 if it results in a 2 insn sequence. */
18128 {
18129 /*
18130 * notl op1 (if necessary)
18131 * sarl $31, op1
18132 * orl cf, op1
18133 */
18135 {
18139 }
18150 }
18151 }
18159 {
18160 /*
18161 * xorl dest,dest
18162 * cmpl op1,op2
18163 * setcc dest
18164 * lea cf(dest*(ct-cf)),dest
18165 *
18166 * Size 14.
18167 *
18168 * This also catches the degenerate setcc-only case.
18169 */
18171 rtx tmp;
18177 /* On x86_64 the lea instruction operates on Pmode, so we need
18178 to get arithmetics done in proper mode to match. */
18181 else
18182 {
18183 rtx out1;
18186 nops++;
18188 {
18190 nops++;
18191 }
18192 }
18194 {
18196 nops++;
18197 }
18199 {
18202 else
18204 }
18209 }
18211 /*
18212 * General case: Jumpful:
18213 * xorl dest,dest cmpl op1, op2
18214 * cmpl op1, op2 movl ct, dest
18215 * setcc dest jcc 1f
18216 * decl dest movl cf, dest
18217 * andl (cf-ct),dest 1:
18218 * addl ct,dest
18219 *
18220 * Size 20. Size 14.
18221 *
18222 * This is reasonably steep, but branch mispredict costs are
18223 * high on modern cpus, so consider failing only if optimizing
18224 * for space.
18225 */
18230 {
18232 {
18239 {
18242 /* We may be reversing unordered compare to normal compare,
18243 that is not valid in general (we may convert non-trapping
18244 condition to trapping one), however on i386 we currently
18245 emit all comparisons unordered. */
18247 }
18248 else
18249 {
18253 }
18254 }
18257 {
18258 /* notl op1 (if needed)
18259 sarl $31, op1
18260 andl (cf-ct), op1
18261 addl ct, op1
18263 For x < 0 (resp. x <= -1) there will be no notl,
18264 so if possible swap the constants to get rid of the
18265 complement.
18266 True/false will be -1/0 while code below (store flag
18267 followed by decrement) is 0/-1, so the constants need
18268 to be exchanged once more. */
18271 {
18274 }
18275 else
18276 {
18280 }
18283 }
18284 else
18285 {
18289 constm1_rtx,
18291 }
18303 }
18304 }
18307 {
18308 /* Try a few things more with specific constants and a variable. */
18310 optab op;
18316 /* If one of the two operands is an interesting constant, load a
18317 constant with the above and mask it in with a logical operation. */
18320 {
18326 else
18328 }
18330 {
18336 else
18338 }
18339 else
18346 /* Recurse to get the constant loaded. */
18350 /* Mask in the interesting variable. */
18352 OPTAB_WIDEN);
18357 }
18359 /*
18360 * For comparison with above,
18361 *
18362 * movl cf,dest
18363 * movl ct,tmp
18364 * cmpl op1,op2
18365 * cmovcc tmp,dest
18366 *
18367 * Size 15.
18368 */
18390 }
18392 /* Swap, force into registers, or otherwise massage the two operands
18393 to an sse comparison with a mask result. Thus we differ a bit from
18394 ix86_prepare_fp_compare_args which expects to produce a flags result.
18396 The DEST operand exists to help determine whether to commute commutative
18397 operators. The POP0/POP1 operands are updated in place. The new
18398 comparison code is returned, or UNKNOWN if not implementable. */
18400 static enum rtx_code
18403 {
18404 rtx tmp;
18407 {
18410 /* We have no LTGT as an operator. We could implement it with
18411 NE & ORDERED, but this requires an extra temporary. It's
18412 not clear that it's worth it. */
18419 /* These are supported directly. */
18426 /* For commutative operators, try to canonicalize the destination
18427 operand to be first in the comparison - this helps reload to
18428 avoid extra moves. */
18431 /* FALLTHRU */
18437 /* These are not supported directly. Swap the comparison operands
18438 to transform into something that is supported. */
18447 }
18450 }
18452 /* Detect conditional moves that exactly match min/max operational
18453 semantics. Note that this is IEEE safe, as long as we don't
18454 interchange the operands.
18456 Returns FALSE if this conditional move doesn't match a MIN/MAX,
18457 and TRUE if the operation is successful and instructions are emitted. */
18459 static bool
18462 {
18465 rtx tmp;
18468 ;
18470 {
18474 }
18475 else
18482 else
18487 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
18488 but MODE may be a vector mode and thus not appropriate. */
18490 {
18492 rtvec v;
18497 }
18498 else
18499 {
18502 }
18506 }
18508 /* Expand an sse vector comparison. Return the register with the result. */
18510 static rtx
18513 {
18515 rtx x;
18530 }
18532 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
18533 operations. This is used for both scalar and vector conditional moves. */
18535 static void
18537 {
18542 {
18546 }
18548 {
18553 }
18555 {
18558 op_true,
18559 op_false));
18561 }
18562 else
18563 {
18570 else
18582 }
18583 }
18585 /* Expand a floating-point conditional move. Return true if successful. */
18587 bool
18589 {
18597 {
18600 /* Since we've no cmove for sse registers, don't force bad register
18601 allocation just to gain access to it. Deny movcc when the
18602 comparison mode doesn't match the move mode. */
18621 }
18623 /* The floating point conditional move instructions don't directly
18624 support conditions resulting from a signed integer comparison. */
18628 {
18633 }
18640 }
18642 /* Expand a floating-point vector conditional move; a vcond operation
18643 rather than a movcc operation. */
18645 bool
18647 {
18649 rtx cmp;
18664 }
18666 /* Expand a signed/unsigned integral vector conditional move. */
18668 bool
18670 {
18679 /* XOP supports all of the comparisons on all vector int types. */
18681 {
18682 /* Canonicalize the comparison to EQ, GT, GTU. */
18684 {
18701 /* FALLTHRU */
18711 }
18713 /* Only SSE4.1/SSE4.2 supports V2DImode. */
18715 {
18717 {
18719 /* SSE4.1 supports EQ. */
18726 /* SSE4.2 supports GT/GTU. */
18733 }
18734 }
18736 /* Unsigned parallel compare is not supported by the hardware.
18737 Play some tricks to turn this into a signed comparison
18738 against 0. */
18740 {
18744 {
18747 {
18751 /* Subtract (-(INT MAX) - 1) from both operands to make
18752 them signed. */
18765 }
18770 /* Perform a parallel unsigned saturating subtraction. */
18783 }
18784 }
18785 }
18793 }
18795 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
18796 true if we should do zero extension, else sign extension. HIGH_P is
18797 true if we want the N/2 high elements, else the low elements. */
18799 void
18801 {
18807 {
18811 else
18817 else
18823 else
18828 }
18834 else
18839 }
18841 /* This function performs the same task as ix86_expand_sse_unpack,
18842 but with SSE4.1 instructions. */
18844 void
18846 {
18852 {
18856 else
18862 else
18868 else
18873 }
18877 {
18878 /* Shift higher 8 bytes to lower 8 bytes. */
18883 }
18884 else
18888 }
18890 /* Expand conditional increment or decrement using adb/sbb instructions.
18891 The default case using setcc followed by the conditional move can be
18892 done by generic code. */
18893 bool
18895 {
18897 rtx flags;
18899 rtx compare_op;
18917 {
18920 }
18923 {
18927 reverse_condition_maybe_unordered
18929 else
18931 }
18935 /* Construct either adc or sbb insn. */
18937 {
18939 {
18954 }
18955 }
18956 else
18957 {
18959 {
18974 }
18975 }
18979 }
18982 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
18983 but works for floating pointer parameters and nonoffsetable memories.
18984 For pushes, it returns just stack offsets; the values will be saved
18985 in the right order. Maximally three parts are generated. */
18987 static int
18989 {
18994 else
19000 /* Optimize constant pool reference to immediates. This is used by fp
19001 moves, that force all constants to memory to allow combining. */
19003 {
19007 }
19010 {
19011 /* The only non-offsetable memories we handle are pushes. */
19020 }
19023 {
19025 /* Caution: if we looked through a constant pool memory above,
19026 the operand may actually have a different mode now. That's
19027 ok, since we want to pun this all the way back to an integer. */
19031 }
19034 {
19037 else
19038 {
19042 {
19046 }
19048 {
19053 }
19055 {
19056 REAL_VALUE_TYPE r;
19061 {
19076 }
19079 }
19080 else
19082 }
19083 }
19084 else
19085 {
19089 {
19092 {
19096 }
19098 {
19102 }
19104 {
19105 REAL_VALUE_TYPE r;
19111 /* Do not use shift by 32 to avoid warning on 32bit systems. */
19114 = gen_int_mode
19117 DImode);
19118 else
19125 = gen_int_mode
19128 DImode);
19129 else
19131 }
19132 else
19134 }
19135 }
19138 }
19140 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
19141 Return false when normal moves are needed; true when all required
19142 insns have been emitted. Operands 2-4 contain the input values
19143 int the correct order; operands 5-7 contain the output values. */
19145 void
19147 {
19155 /* The DFmode expanders may ask us to move double.
19156 For 64bit target this is single move. By hiding the fact
19157 here we simplify i386.md splitters. */
19159 {
19160 /* Optimize constant pool reference to immediates. This is used by
19161 fp moves, that force all constants to memory to allow combining. */
19168 {
19171 }
19172 else
19177 }
19179 /* The only non-offsettable memory we handle is push. */
19182 else
19189 /* When emitting push, take care for source operands on the stack. */
19192 {
19195 /* Compensate for the stack decrement by 4. */
19200 /* src_base refers to the stack pointer and is
19201 automatically decreased by emitted push. */
19205 }
19207 /* We need to do copy in the right order in case an address register
19208 of the source overlaps the destination. */
19210 {
19211 rtx tmp;
19214 {
19218 collisions++;
19219 }
19221 /* Collision in the middle part can be handled by reordering. */
19223 {
19226 }
19230 {
19232 {
19235 }
19236 else
19237 {
19240 }
19241 }
19243 /* If there are more collisions, we can't handle it by reordering.
19244 Do an lea to the last part and use only one colliding move. */
19246 {
19247 rtx base;
19253 /* Handle the case when the last part isn't valid for lea.
19254 Happens in 64-bit mode storing the 12-byte XFmode. */
19261 {
19264 }
19265 }
19266 }
19269 {
19271 {
19273 {
19278 }
19280 {
19283 }
19284 }
19285 else
19286 {
19287 /* In 64bit mode we don't have 32bit push available. In case this is
19288 register, it is OK - we will just use larger counterpart. We also
19289 retype memory - these comes from attempt to avoid REX prefix on
19290 moving of second half of TFmode value. */
19292 {
19294 {
19305 }
19309 }
19310 }
19314 }
19316 /* Choose correct order to not overwrite the source before it is copied. */
19326 {
19328 {
19331 }
19332 }
19333 else
19334 {
19336 {
19339 }
19340 }
19342 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
19344 {
19353 }
19359 }
19361 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
19362 left shift by a constant, either using a single shift or
19363 a sequence of add instructions. */
19365 static void
19367 {
19373 {
19377 }
19378 else
19379 {
19382 }
19383 }
19385 void
19387 {
19396 {
19401 {
19407 }
19408 else
19409 {
19417 }
19419 }
19426 {
19427 /* Assuming we've chosen a QImode capable registers, then 1 << N
19428 can be done with two 32/64-bit shifts, no branches, no cmoves. */
19430 {
19446 }
19448 /* Otherwise, we can get the same results by manually performing
19449 a bit extract operation on bit 5/6, and then performing the two
19450 shifts. The two methods of getting 0/1 into low/high are exactly
19451 the same size. Avoiding the shift in the bit extract case helps
19452 pentium4 a bit; no one else seems to care much either way. */
19453 else
19454 {
19459 HOST_WIDE_INT bits;
19460 rtx x;
19463 {
19469 }
19470 else
19471 {
19477 }
19481 else
19489 }
19494 }
19497 {
19498 /* For -1 << N, we can avoid the shld instruction, because we
19499 know that we're shifting 0...31/63 ones into a -1. */
19503 else
19505 }
19506 else
19507 {
19515 }
19520 {
19526 }
19527 else
19528 {
19533 }
19534 }
19536 void
19538 {
19548 {
19553 {
19559 }
19561 {
19570 }
19571 else
19572 {
19580 }
19581 }
19582 else
19583 {
19595 {
19603 scratch));
19604 }
19605 else
19606 {
19611 }
19612 }
19613 }
19615 void
19617 {
19627 {
19632 {
19639 }
19640 else
19641 {
19649 }
19650 }
19651 else
19652 {
19664 {
19670 scratch));
19671 }
19672 else
19673 {
19678 }
19679 }
19680 }
19682 /* Predict just emitted jump instruction to be taken with probability PROB. */
19683 static void
19685 {
19689 }
19691 /* Helper function for the string operations below. Dest VARIABLE whether
19692 it is aligned to VALUE bytes. If true, jump to the label. */
19693 static rtx
19695 {
19700 else
19706 else
19709 }
19711 /* Adjust COUNTER by the VALUE. */
19712 static void
19714 {
19719 }
19721 /* Zero extend possibly SImode EXP to Pmode register. */
19722 rtx
19724 {
19725 rtx r;
19733 }
19735 /* Divide COUNTREG by SCALE. */
19736 static rtx
19738 {
19739 rtx sc;
19751 }
19753 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
19754 DImode for constant loop counts. */
19756 static enum machine_mode
19758 {
19766 }
19768 /* When SRCPTR is non-NULL, output simple loop to move memory
19769 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
19770 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
19771 equivalent loop to set memory by VALUE (supposed to be in MODE).
19773 The size is rounded down to whole number of chunk size moved at once.
19774 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
19777 static void
19782 {
19787 rtx size;
19788 rtx x_addr;
19789 rtx y_addr;
19798 /* Those two should combine. */
19800 {
19804 }
19814 {
19818 /* When unrolling for chips that reorder memory reads and writes,
19819 we can save registers by using single temporary.
19820 Also using 4 temporaries is overkill in 32bit mode. */
19822 {
19824 {
19826 {
19827 destmem =
19829 srcmem =
19831 }
19833 }
19834 }
19835 else
19836 {
19840 {
19843 {
19844 srcmem =
19846 }
19848 }
19850 {
19852 {
19853 destmem =
19855 }
19857 }
19858 }
19859 }
19860 else
19862 {
19864 destmem =
19867 }
19877 {
19883 else
19885 }
19886 else
19894 {
19899 }
19901 }
19903 /* Output "rep; mov" instruction.
19904 Arguments have same meaning as for previous function */
19905 static void
19908 rtx count,
19910 {
19911 rtx destexp;
19912 rtx srcexp;
19913 rtx countreg;
19915 /* If the size is known, it is shorter to use rep movs. */
19926 {
19933 }
19934 else
19935 {
19938 }
19940 {
19947 }
19948 else
19949 {
19954 }
19957 }
19959 /* Output "rep; stos" instruction.
19960 Arguments have same meaning as for previous function */
19961 static void
19964 rtx orig_value)
19965 {
19966 rtx destexp;
19967 rtx countreg;
19974 {
19978 }
19979 else
19982 {
19987 }
19991 }
19993 static void
19996 {
20000 }
20002 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
20003 static void
20006 {
20009 {
20014 {
20016 {
20019 }
20020 else
20023 }
20025 {
20028 else
20029 {
20032 }
20034 }
20036 {
20039 }
20041 {
20044 }
20046 {
20049 }
20051 }
20053 {
20059 }
20061 /* When there are stringops, we can cheaply increase dest and src pointers.
20062 Otherwise we save code size by maintaining offset (zero is readily
20063 available from preceding rep operation) and using x86 addressing modes.
20064 */
20066 {
20068 {
20075 }
20077 {
20084 }
20086 {
20093 }
20094 }
20095 else
20096 {
20098 rtx tmp;
20101 {
20112 }
20114 {
20127 }
20129 {
20138 }
20139 }
20140 }
20142 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
20143 static void
20146 {
20147 count =
20153 }
20155 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
20156 static void
20158 {
20159 rtx dest;
20162 {
20167 {
20169 {
20174 }
20175 else
20178 }
20180 {
20182 {
20185 }
20186 else
20187 {
20192 }
20194 }
20196 {
20200 }
20202 {
20206 }
20208 {
20212 }
20214 }
20216 {
20219 }
20221 {
20224 {
20228 }
20229 else
20230 {
20236 }
20239 }
20241 {
20244 {
20247 }
20248 else
20249 {
20253 }
20256 }
20258 {
20264 }
20266 {
20272 }
20274 {
20280 }
20281 }
20283 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
20284 DESIRED_ALIGNMENT. */
20285 static void
20289 {
20291 {
20299 }
20301 {
20309 }
20311 {
20319 }
20321 }
20323 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
20324 ALIGN_BYTES is how many bytes need to be copied. */
20325 static rtx
20328 {
20338 {
20343 }
20345 {
20356 }
20358 {
20364 {
20372 }
20375 }
20381 {
20393 }
20400 }
20402 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
20403 DESIRED_ALIGNMENT. */
20404 static void
20407 {
20409 {
20416 }
20418 {
20425 }
20427 {
20434 }
20436 }
20438 /* Set enough from DST to align DST known to by aligned by ALIGN to
20439 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
20440 static rtx
20443 {
20447 {
20452 }
20454 {
20461 }
20463 {
20470 }
20477 }
20479 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
20480 static enum stringop_alg
20483 {
20486 /* Algorithms using the rep prefix want at least edi and ecx;
20487 additionally, memset wants eax and memcpy wants esi. Don't
20488 consider such algorithms if the user has appropriated those
20489 registers for their own purposes. */
20491 || (memset
20494 #define ALG_USABLE_P(alg) (rep_prefix_usable \
20495 || (alg != rep_prefix_1_byte \
20496 && alg != rep_prefix_4_byte \
20497 && alg != rep_prefix_8_byte))
20500 /* Even if the string operation call is cold, we still might spend a lot
20501 of time processing large blocks. */
20506 else
20514 else
20518 /* rep; movq or rep; movl is the smallest variant. */
20520 {
20523 else
20525 }
20526 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
20527 */
20531 {
20535 {
20536 /* We get here if the algorithms that were not libcall-based
20537 were rep-prefix based and we are unable to use rep prefixes
20538 based on global register usage. Break out of the loop and
20539 use the heuristic below. */
20543 {
20548 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
20549 last non-libcall inline algorithm. */
20551 {
20552 /* When the current size is best to be copied by a libcall,
20553 but we are still forced to inline, run the heuristic below
20554 that will pick code for medium sized blocks. */
20558 }
20561 }
20562 }
20564 }
20565 /* When asked to inline the call anyway, try to pick meaningful choice.
20566 We look for maximal size of block that is faster to copy by hand and
20567 take blocks of at most of that size guessing that average size will
20568 be roughly half of the block.
20570 If this turns out to be bad, we might simply specify the preferred
20571 choice in ix86_costs. */
20574 {
20581 {
20588 }
20589 /* If there aren't any usable algorithms, then recursing on
20590 smaller sizes isn't going to find anything. Just return the
20591 simple byte-at-a-time copy loop. */
20593 {
20594 /* Pick something reasonable. */
20598 }
20607 }
20609 #undef ALG_USABLE_P
20610 }
20612 /* Decide on alignment. We know that the operand is already aligned to ALIGN
20613 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
20614 static int
20618 {
20621 {
20632 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
20633 copying whole cacheline at once. */
20636 else
20640 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
20641 copying whole cacheline at once. */
20644 else
20652 }
20661 }
20663 /* Return the smallest power of 2 greater than VAL. */
20664 static int
20666 {
20671 }
20673 /* Expand string move (memcpy) operation. Use i386 string operations when
20674 profitable. expand_setmem contains similar code. The code depends upon
20675 architecture, block size and alignment, but always has the same
20676 overall structure:
20678 1) Prologue guard: Conditional that jumps up to epilogues for small
20679 blocks that can be handled by epilogue alone. This is faster but
20680 also needed for correctness, since prologue assume the block is larger
20681 than the desired alignment.
20683 Optional dynamic check for size and libcall for large
20684 blocks is emitted here too, with -minline-stringops-dynamically.
20686 2) Prologue: copy first few bytes in order to get destination aligned
20687 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
20688 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
20689 We emit either a jump tree on power of two sized blocks, or a byte loop.
20691 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
20692 with specified algorithm.
20694 4) Epilogue: code copying tail of the block that is too small to be
20695 handled by main body (or up to size guarded by prologue guard). */
20697 bool
20700 {
20701 rtx destreg;
20702 rtx srcreg;
20704 rtx tmp;
20717 /* i386 can do misaligned access on reasonably increased cost. */
20721 /* ALIGN is the minimum of destination and source alignment, but we care here
20722 just about destination alignment. */
20731 /* Make sure we don't need to care about overflow later on. */
20735 /* Step 0: Decide on preferred algorithm, desired alignment and
20736 size of chunks to be copied by main loop. */
20752 {
20777 }
20781 /* Step 1: Prologue guard. */
20783 /* Alignment code needs count to be in register. */
20785 {
20788 {
20789 align_bytes
20793 else
20795 }
20798 }
20801 /* Ensure that alignment prologue won't copy past end of block. */
20803 {
20805 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
20806 Make sure it is power of 2. */
20810 {
20812 {
20813 /* If main algorithm works on QImode, no epilogue is needed.
20814 For small sizes just don't align anything. */
20817 else
20819 }
20820 }
20821 else
20822 {
20829 else
20831 }
20832 }
20834 /* Emit code to decide on runtime whether library call or inline should be
20835 used. */
20837 {
20839 {
20841 {
20845 }
20846 }
20847 else
20848 {
20857 }
20858 }
20860 /* Step 2: Alignment prologue. */
20863 {
20865 {
20866 /* Except for the first move in epilogue, we no longer know
20867 constant offset in aliasing info. It don't seems to worth
20868 the pain to maintain it for the first move, so throw away
20869 the info early. */
20873 desired_align);
20874 }
20875 else
20876 {
20877 /* If we know how many bytes need to be stored before dst is
20878 sufficiently aligned, maintain aliasing info accurately. */
20883 }
20889 {
20890 /* It is possible that we copied enough so the main loop will not
20891 execute. */
20901 else
20903 }
20904 }
20906 {
20911 }
20915 /* Step 3: Main loop. */
20918 {
20931 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
20932 registers for 4 temporaries anyway. */
20935 expected_size);
20939 DImode);
20943 SImode);
20947 QImode);
20949 }
20950 /* Adjust properly the offset of src and dest memory for aliasing. */
20952 {
20957 }
20958 else
20959 {
20962 }
20964 /* Step 4: Epilogue to copy the remaining bytes. */
20965 epilogue:
20967 {
20968 /* When the main loop is done, COUNT_EXP might hold original count,
20969 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
20970 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
20971 bytes. Compensate if needed. */
20974 {
20975 tmp =
20978 OPTAB_DIRECT);
20981 }
20984 }
20988 epilogue_size_needed);
20992 }
20994 /* Helper function for memcpy. For QImode value 0xXY produce
20995 0xXYXYXYXY of wide specified by MODE. This is essentially
20996 a * 0x10101010, but we can do slightly better than
20997 synth_mult by unwinding the sequence by hand on CPUs with
20998 slow multiply. */
20999 static rtx
21001 {
21003 rtx tmp;
21010 {
21018 }
21027 nops--;
21032 {
21036 OPTAB_DIRECT);
21037 }
21038 else
21039 {
21045 else
21047 else
21048 {
21051 reg =
21053 }
21063 }
21064 }
21066 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
21067 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
21068 alignment from ALIGN to DESIRED_ALIGN. */
21069 static rtx
21071 {
21072 rtx promoted_val;
21081 else
21085 }
21087 /* Expand string clear operation (bzero). Use i386 string operations when
21088 profitable. See expand_movmem comment for explanation of individual
21089 steps performed. */
21090 bool
21093 {
21094 rtx destreg;
21096 rtx tmp;
21111 /* i386 can do misaligned access on reasonably increased cost. */
21120 /* Make sure we don't need to care about overflow later on. */
21124 /* Step 0: Decide on preferred algorithm, desired alignment and
21125 size of chunks to be copied by main loop. */
21140 {
21165 }
21168 /* Step 1: Prologue guard. */
21170 /* Alignment code needs count to be in register. */
21172 {
21175 {
21176 align_bytes
21180 else
21182 }
21184 {
21189 }
21190 }
21191 /* Do the cheap promotion to allow better CSE across the
21192 main loop and epilogue (ie one load of the big constant in the
21193 front of all code. */
21197 /* Ensure that alignment prologue won't copy past end of block. */
21199 {
21201 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
21202 Make sure it is power of 2. */
21205 /* To improve performance of small blocks, we jump around the VAL
21206 promoting mode. This mean that if the promoted VAL is not constant,
21207 we might not use it in the epilogue and have to use byte
21208 loop variant. */
21212 {
21214 {
21215 /* If main algorithm works on QImode, no epilogue is needed.
21216 For small sizes just don't align anything. */
21219 else
21221 }
21222 }
21223 else
21224 {
21231 else
21233 }
21234 }
21236 {
21245 }
21247 /* Step 2: Alignment prologue. */
21249 /* Do the expensive promotion once we branched off the small blocks. */
21256 {
21258 {
21259 /* Except for the first move in epilogue, we no longer know
21260 constant offset in aliasing info. It don't seems to worth
21261 the pain to maintain it for the first move, so throw away
21262 the info early. */
21265 desired_align);
21266 }
21267 else
21268 {
21269 /* If we know how many bytes need to be stored before dst is
21270 sufficiently aligned, maintain aliasing info accurately. */
21275 }
21281 {
21282 /* It is possible that we copied enough so the main loop will not
21283 execute. */
21293 else
21295 }
21296 }
21298 {
21304 }
21308 /* Step 3: Main loop. */
21311 {
21339 }
21340 /* Adjust properly the offset of src and dest memory for aliasing. */
21344 else
21347 /* Step 4: Epilogue to copy the remaining bytes. */
21350 {
21351 /* When the main loop is done, COUNT_EXP might hold original count,
21352 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
21353 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
21354 bytes. Compensate if needed. */
21357 {
21358 tmp =
21361 OPTAB_DIRECT);
21364 }
21367 }
21368 epilogue:
21370 {
21373 epilogue_size_needed);
21374 else
21376 epilogue_size_needed);
21377 }
21381 }
21383 /* Expand the appropriate insns for doing strlen if not just doing
21384 repnz; scasb
21386 out = result, initialized with the start address
21387 align_rtx = alignment of the address.
21388 scratch = scratch register, initialized with the startaddress when
21389 not aligned, otherwise undefined
21391 This is just the body. It needs the initializations mentioned above and
21392 some address computing at the end. These things are done in i386.md. */
21394 static void
21396 {
21398 rtx tmp;
21403 rtx mem;
21406 rtx cmp;
21412 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
21414 /* Is there a known alignment and is it less than 4? */
21416 {
21419 /* Is there a known alignment and is it not 2? */
21421 {
21425 /* Leave just the 3 lower bits. */
21435 }
21436 else
21437 {
21438 /* Since the alignment is 2, we have to check 2 or 0 bytes;
21439 check if is aligned to 4 - byte. */
21446 }
21450 /* Now compare the bytes. */
21452 /* Compare the first n unaligned byte on a byte per byte basis. */
21456 /* Increment the address. */
21459 /* Not needed with an alignment of 2 */
21461 {
21465 end_0_label);
21470 }
21473 end_0_label);
21476 }
21478 /* Generate loop to check 4 bytes at a time. It is not a good idea to
21479 align this loop. It gives only huge programs, but does not help to
21480 speed up. */
21487 /* This formula yields a nonzero result iff one of the bytes is zero.
21488 This saves three branches inside loop and many cycles. */
21496 align_4_label);
21499 {
21505 /* If zero is not in the first two bytes, move two bytes forward. */
21511 reg,
21512 tmpreg)));
21513 /* Emit lea manually to avoid clobbering of flags. */
21521 reg2,
21522 out)));
21523 }
21524 else
21525 {
21527 /* Is zero in the first two bytes? */
21534 pc_rtx);
21538 /* Not in the first two. Move two bytes forward. */
21544 }
21546 /* Avoid branch in fixing the byte. */
21554 }
21556 /* Expand strlen. */
21558 bool
21560 {
21563 /* The generic case of strlen expander is long. Avoid it's
21564 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
21567 && !TARGET_INLINE_ALL_STRINGOPS
21577 {
21578 /* Well it seems that some optimizer does not combine a call like
21579 foo(strlen(bar), strlen(bar));
21580 when the move and the subtraction is done here. It does calculate
21581 the length just once when these instructions are done inside of
21582 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
21583 often used and I use one fewer register for the lifetime of
21584 output_strlen_unroll() this is better. */
21590 /* strlensi_unroll_1 returns the address of the zero at the end of
21591 the string, like memchr(), so compute the length by subtracting
21592 the start address. */
21594 }
21595 else
21596 {
21597 rtx unspec;
21599 /* Can't use this if the user has appropriated eax, ecx, or edi. */
21612 /* If .md starts supporting :P, this can be done in .md. */
21618 }
21620 }
21622 /* For given symbol (function) construct code to compute address of it's PLT
21623 entry in large x86-64 PIC model. */
21624 rtx
21626 {
21636 }
21638 rtx
21640 rtx callarg2,
21642 {
21650 {
21651 #if TARGET_MACHO
21654 #endif
21655 }
21656 else
21657 {
21658 /* Static functions and indirect calls don't need the pic register. */
21663 }
21666 {
21670 }
21680 {
21683 }
21689 {
21693 }
21697 {
21698 /* We need to represent that SI and DI registers are clobbered
21699 by SYSV calls. */
21705 };
21709 UNSPEC_MS_TO_SYSV_CALL);
21716 gen_rtx_REG
21724 }
21726 /* Add UNSPEC_CALL_NEEDS_VZEROUPPER decoration. */
21728 {
21729 rtx unspec;
21733 {
21736 else
21738 }
21741 else
21746 else
21747 {
21750 UNSPEC_CALL_NEEDS_VZEROUPPER);
21753 }
21754 }
21761 }
21763 void
21765 {
21769 }
21771 /* Output the assembly for a call instruction. */
21775 {
21782 {
21785 /* SEH epilogue detection requires the indirect branch case
21786 to include REX.W. */
21789 else
21791 }
21793 /* SEH unwinding can require an extra nop to be emitted in several
21794 circumstances. Determine if we have one of those. */
21796 {
21797 rtx i;
21800 {
21801 /* If we get to another real insn, we don't need the nop. */
21805 /* If we get to the epilogue note, prevent a catch region from
21806 being adjacent to the standard epilogue sequence. If non-
21807 call-exceptions, we'll have done this during epilogue emission. */
21809 && !flag_non_call_exceptions
21811 {
21814 }
21815 }
21817 /* If we didn't find a real insn following the call, prevent the
21818 unwinder from looking into the next function. */
21821 }
21824 {
21827 else
21829 }
21830 else
21831 {
21834 else
21836 }
21837 }
21838 \f
21839 /* Clear stack slot assignments remembered from previous functions.
21840 This is called from INIT_EXPANDERS once before RTL is emitted for each
21841 function. */
21845 {
21854 }
21856 /* Return a MEM corresponding to a stack slot with mode MODE.
21857 Allocate a new slot if necessary.
21859 The RTL for a function can have several slots available: N is
21860 which slot to use. */
21862 rtx
21864 {
21869 /* Virtual slot is valid only before vregs are instantiated. */
21884 }
21886 /* Construct the SYMBOL_REF for the tls_get_addr function. */
21889 rtx
21891 {
21894 {
21896 (TARGET_ANY_GNU_TLS
21900 }
21903 }
21905 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
21908 rtx
21910 {
21913 {
21918 }
21921 }
21922 \f
21923 /* Calculate the length of the memory address in the instruction
21924 encoding. Does not include the one-byte modrm, opcode, or prefix. */
21926 int
21928 {
21953 /* Rule of thumb:
21954 - esp as the base always wants an index,
21955 - ebp as the base always wants a displacement,
21956 - r12 as the base always wants an index,
21957 - r13 as the base always wants a displacement. */
21959 /* Register Indirect. */
21961 {
21962 /* esp (for its index) and ebp (for its displacement) need
21963 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
21964 code. */
21973 }
21975 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
21976 is not disp32, but disp32(%rip), so for disp32
21977 SIB byte is needed, unless print_operand_address
21978 optimizes it into disp32(%rip) or (%rip) is implied
21979 by UNSPEC. */
21981 {
21984 {
22001 }
22002 }
22004 else
22005 {
22006 /* Find the length of the displacement constant. */
22008 {
22011 else
22013 }
22014 /* ebp always wants a displacement. Similarly r13. */
22019 /* An index requires the two-byte modrm form.... */
22021 /* ...like esp (or r12), which always wants an index. */
22027 }
22030 {
22037 }
22040 }
22042 /* Compute default value for "length_immediate" attribute. When SHORTFORM
22043 is set, expect that insn have 8bit immediate alternative. */
22044 int
22046 {
22052 {
22057 {
22060 {
22072 }
22074 {
22077 }
22078 }
22080 {
22090 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
22096 }
22097 }
22099 }
22100 /* Compute default value for "length_address" attribute. */
22101 int
22103 {
22107 {
22117 {
22122 }
22125 }
22130 {
22133 {
22138 constraints++;
22141 ;
22142 /* Skip ignored operands. */
22145 }
22147 }
22149 }
22151 /* Compute default value for "length_vex" attribute. It includes
22152 2 or 3 byte VEX prefix and 1 opcode byte. */
22154 int
22157 {
22160 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
22161 byte VEX prefix. */
22165 /* We can always use 2 byte VEX prefix in 32bit. */
22173 {
22174 /* REX.W bit uses 3 byte VEX prefix. */
22178 }
22179 else
22180 {
22181 /* REX.X or REX.B bits use 3 byte VEX prefix. */
22185 }
22188 }
22189 \f
22190 /* Return the maximum number of instructions a cpu can issue. */
22192 static int
22194 {
22196 {
22219 }
22220 }
22222 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
22223 by DEP_INSN and nothing set by DEP_INSN. */
22225 static int
22227 {
22230 /* Simplify the test for uninteresting insns. */
22238 {
22241 }
22246 {
22249 }
22250 else
22256 /* This test is true if the dependent insn reads the flags but
22257 not any other potentially set register. */
22265 }
22267 /* Return true iff USE_INSN has a memory address with operands set by
22268 SET_INSN. */
22270 bool
22272 {
22277 {
22280 }
22282 }
22284 static int
22286 {
22292 /* Anti and output dependencies have zero cost on all CPUs. */
22298 /* If we can't recognize the insns, we can't really do anything. */
22306 {
22308 /* Address Generation Interlock adds a cycle of latency. */
22310 {
22321 }
22325 /* ??? Compares pair with jump/setcc. */
22329 /* Floating point stores require value to be ready one cycle earlier. */
22339 /* INT->FP conversion is expensive. */
22343 /* There is one cycle extra latency between an FP op and a store. */
22351 /* Show ability of reorder buffer to hide latency of load by executing
22352 in parallel with previous instruction in case
22353 previous instruction is not needed to compute the address. */
22356 {
22357 /* Claim moves to take one cycle, as core can issue one load
22358 at time and the next load can start cycle later. */
22363 cost--;
22364 }
22370 /* The esp dependency is resolved before the instruction is really
22371 finished. */
22376 /* INT->FP conversion is expensive. */
22380 /* Show ability of reorder buffer to hide latency of load by executing
22381 in parallel with previous instruction in case
22382 previous instruction is not needed to compute the address. */
22385 {
22386 /* Claim moves to take one cycle, as core can issue one load
22387 at time and the next load can start cycle later. */
22393 else
22395 }
22407 /* Show ability of reorder buffer to hide latency of load by executing
22408 in parallel with previous instruction in case
22409 previous instruction is not needed to compute the address. */
22412 {
22416 /* Because of the difference between the length of integer and
22417 floating unit pipeline preparation stages, the memory operands
22418 for floating point are cheaper.
22420 ??? For Athlon it the difference is most probably 2. */
22423 else
22428 else
22430 }
22434 }
22437 }
22439 /* How many alternative schedules to try. This should be as wide as the
22440 scheduling freedom in the DFA, but no wider. Making this value too
22441 large results extra work for the scheduler. */
22443 static int
22445 {
22447 {
22459 /* Generally, we want haifa-sched:max_issue() to look ahead as far
22460 as many instructions can be executed on a cycle, i.e.,
22461 issue_rate. I wonder why tuning for many CPUs does not do this. */
22466 }
22467 }
22469 \f
22471 /* Model decoder of Core 2/i7.
22472 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
22473 track the instruction fetch block boundaries and make sure that long
22474 (9+ bytes) instructions are assigned to D0. */
22476 /* Maximum length of an insn that can be handled by
22477 a secondary decoder unit. '8' for Core 2/i7. */
22480 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
22481 '16' for Core 2/i7. */
22484 /* Maximum number of instructions decoder can handle per cycle.
22485 '6' for Core 2/i7. */
22489 ix86_first_cycle_multipass_data_t;
22491 const_ix86_first_cycle_multipass_data_t;
22493 /* A variable to store target state across calls to max_issue within
22494 one cycle. */
22498 /* Initialize DATA. */
22499 static void
22501 {
22502 ix86_first_cycle_multipass_data_t data
22509 }
22511 /* Advancing the cycle; reset ifetch block counts. */
22512 static void
22514 {
22521 }
22525 /* Filter out insns from ready_try that the core will not be able to issue
22526 on current cycle due to decoder. */
22527 static void
22528 core2i7_first_cycle_multipass_filter_ready_try
22531 {
22533 {
22534 rtx insn;
22544 (!first_cycle_insn_p
22546 /* ... or it would not fit into the ifetch block ... */
22548 /* ... or the decoder is full already ... */
22550 /* ... mask the insn out. */
22551 {
22556 }
22557 }
22558 }
22560 /* Prepare for a new round of multipass lookahead scheduling. */
22561 static void
22564 {
22565 ix86_first_cycle_multipass_data_t data
22567 const_ix86_first_cycle_multipass_data_t prev_data
22570 /* Restore the state from the end of the previous round. */
22574 /* Filter instructions that cannot be issued on current cycle due to
22575 decoder restrictions. */
22577 first_cycle_insn_p);
22578 }
22580 /* INSN is being issued in current solution. Account for its impact on
22581 the decoder model. */
22582 static void
22585 {
22586 ix86_first_cycle_multipass_data_t data
22588 const_ix86_first_cycle_multipass_data_t prev_data
22598 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
22600 {
22603 }
22605 {
22609 }
22612 /* Filter out insns from ready_try that the core will not be able to issue
22613 on current cycle due to decoder. */
22616 }
22618 /* Revert the effect on ready_try. */
22619 static void
22623 {
22624 const_ix86_first_cycle_multipass_data_t data
22627 sbitmap_iterator sbi;
22631 {
22633 }
22634 }
22636 /* Save the result of multipass lookahead scheduling for the next round. */
22637 static void
22639 {
22640 const_ix86_first_cycle_multipass_data_t data
22642 ix86_first_cycle_multipass_data_t next_data
22646 {
22649 }
22650 }
22652 /* Deallocate target data. */
22653 static void
22655 {
22656 ix86_first_cycle_multipass_data_t data
22660 {
22664 }
22665 }
22667 /* Prepare for scheduling pass. */
22668 static void
22672 {
22673 /* Install scheduling hooks for current CPU. Some of these hooks are used
22674 in time-critical parts of the scheduler, so we only set them up when
22675 they are actually used. */
22677 {
22697 /* Set decoder parameters. */
22712 }
22713 }
22715 \f
22716 /* Compute the alignment given to a constant that is being placed in memory.
22717 EXP is the constant and ALIGN is the alignment that the object would
22718 ordinarily have.
22719 The value of this function is used instead of that alignment to align
22720 the object. */
22722 int
22724 {
22727 {
22732 }
22738 }
22740 /* Compute the alignment for a static variable.
22741 TYPE is the data type, and ALIGN is the alignment that
22742 the object would ordinarily have. The value of this function is used
22743 instead of that alignment to align the object. */
22745 int
22747 {
22758 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
22759 to 16byte boundary. */
22761 {
22768 }
22771 {
22776 }
22778 {
22785 }
22790 {
22795 }
22798 {
22803 }
22806 }
22808 /* Compute the alignment for a local variable or a stack slot. EXP is
22809 the data type or decl itself, MODE is the widest mode available and
22810 ALIGN is the alignment that the object would ordinarily have. The
22811 value of this macro is used instead of that alignment to align the
22812 object. */
22814 unsigned int
22817 {
22821 {
22824 }
22825 else
22826 {
22829 }
22831 /* Don't do dynamic stack realignment for long long objects with
22832 -mpreferred-stack-boundary=2. */
22841 /* If TYPE is NULL, we are allocating a stack slot for caller-save
22842 register in MODE. We will return the largest alignment of XF
22843 and DF. */
22845 {
22849 }
22851 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
22852 to 16byte boundary. Exact wording is:
22854 An array uses the same alignment as its elements, except that a local or
22855 global array variable of length at least 16 bytes or
22856 a C99 variable-length array variable always has alignment of at least 16 bytes.
22858 This was added to allow use of aligned SSE instructions at arrays. This
22859 rule is meant for static storage (where compiler can not do the analysis
22860 by itself). We follow it for automatic variables only when convenient.
22861 We fully control everything in the function compiled and functions from
22862 other unit can not rely on the alignment.
22864 Exclude va_list type. It is the common case of local array where
22865 we can not benefit from the alignment. */
22868 {
22877 }
22879 {
22884 }
22886 {
22892 }
22897 {
22902 }
22905 {
22911 }
22913 }
22915 /* Compute the minimum required alignment for dynamic stack realignment
22916 purposes for a local variable, parameter or a stack slot. EXP is
22917 the data type or decl itself, MODE is its mode and ALIGN is the
22918 alignment that the object would ordinarily have. */
22920 unsigned int
22923 {
22927 {
22930 }
22931 else
22932 {
22935 }
22940 /* Don't do dynamic stack realignment for long long objects with
22941 -mpreferred-stack-boundary=2. */
22948 }
22949 \f
22950 /* Find a location for the static chain incoming to a nested function.
22951 This is a register, unless all free registers are used by arguments. */
22953 static rtx
22955 {
22962 {
22963 /* We always use R10 in 64-bit mode. */
22965 }
22966 else
22967 {
22968 tree fntype;
22969 /* By default in 32-bit mode we use ECX to pass the static chain. */
22974 {
22975 /* Fastcall functions use ecx/edx for arguments, which leaves
22976 us with EAX for the static chain. */
22978 }
22980 {
22981 /* Thiscall functions use ecx for arguments, which leaves
22982 us with EAX for the static chain. */
22984 }
22986 {
22987 /* For regparm 3, we have no free call-clobbered registers in
22988 which to store the static chain. In order to implement this,
22989 we have the trampoline push the static chain to the stack.
22990 However, we can't push a value below the return address when
22991 we call the nested function directly, so we have to use an
22992 alternate entry point. For this we use ESI, and have the
22993 alternate entry point push ESI, so that things appear the
22994 same once we're executing the nested function. */
22996 {
23001 }
23003 }
23004 }
23007 }
23009 /* Emit RTL insns to initialize the variable parts of a trampoline.
23010 FNDECL is the decl of the target address; M_TRAMP is a MEM for
23011 the trampoline, and CHAIN_VALUE is an RTX for the static chain
23012 to be passed to the target function. */
23014 static void
23016 {
23022 {
23026 /* Depending on the static chain location, either load a register
23027 with a constant, or push the constant to the stack. All of the
23028 instructions are the same size. */
23031 {
23036 else
23038 }
23039 else
23048 /* Compute offset from the end of the jmp to the target function.
23049 In the case in which the trampoline stores the static chain on
23050 the stack, we need to skip the first insn which pushes the
23051 (call-saved) register static chain; this push is 1 byte. */
23062 }
23063 else
23064 {
23067 /* Load the function address to r11. Try to load address using
23068 the shorter movl instead of movabs. We may want to support
23069 movq for kernel mode, but kernel does not use trampolines at
23070 the moment. */
23072 {
23081 }
23082 else
23083 {
23090 }
23092 /* Load static chain using movabs to r10. */
23100 /* Jump to r11; the last (unused) byte is a nop, only there to
23101 pad the write out to a single 32-bit store. */
23107 }
23109 #ifdef ENABLE_EXECUTE_STACK
23110 #ifdef CHECK_EXECUTE_STACK_ENABLED
23112 #endif
23115 #endif
23116 }
23117 \f
23118 /* The following file contains several enumerations and data structures
23119 built from the definitions in i386-builtin-types.def. */
23123 /* Table for the ix86 builtin non-function types. */
23126 /* Retrieve an element from the above table, building some of
23127 the types lazily. */
23129 static tree
23131 {
23143 {
23151 }
23152 else
23153 {
23159 else
23167 }
23171 }
23173 /* Table for the ix86 builtin function types. */
23176 /* Retrieve an element from the above table, building some of
23177 the types lazily. */
23179 static tree
23181 {
23182 tree type;
23191 {
23199 {
23202 }
23205 }
23206 else
23207 {
23213 }
23217 }
23220 /* Codes for all the SSE/MMX builtins. */
23221 enum ix86_builtins
23222 {
23223 IX86_BUILTIN_ADDPS,
23224 IX86_BUILTIN_ADDSS,
23225 IX86_BUILTIN_DIVPS,
23226 IX86_BUILTIN_DIVSS,
23227 IX86_BUILTIN_MULPS,
23228 IX86_BUILTIN_MULSS,
23229 IX86_BUILTIN_SUBPS,
23230 IX86_BUILTIN_SUBSS,
23232 IX86_BUILTIN_CMPEQPS,
23233 IX86_BUILTIN_CMPLTPS,
23234 IX86_BUILTIN_CMPLEPS,
23235 IX86_BUILTIN_CMPGTPS,
23236 IX86_BUILTIN_CMPGEPS,
23237 IX86_BUILTIN_CMPNEQPS,
23238 IX86_BUILTIN_CMPNLTPS,
23239 IX86_BUILTIN_CMPNLEPS,
23240 IX86_BUILTIN_CMPNGTPS,
23241 IX86_BUILTIN_CMPNGEPS,
23242 IX86_BUILTIN_CMPORDPS,
23243 IX86_BUILTIN_CMPUNORDPS,
23244 IX86_BUILTIN_CMPEQSS,
23245 IX86_BUILTIN_CMPLTSS,
23246 IX86_BUILTIN_CMPLESS,
23247 IX86_BUILTIN_CMPNEQSS,
23248 IX86_BUILTIN_CMPNLTSS,
23249 IX86_BUILTIN_CMPNLESS,
23250 IX86_BUILTIN_CMPNGTSS,
23251 IX86_BUILTIN_CMPNGESS,
23252 IX86_BUILTIN_CMPORDSS,
23253 IX86_BUILTIN_CMPUNORDSS,
23255 IX86_BUILTIN_COMIEQSS,
23256 IX86_BUILTIN_COMILTSS,
23257 IX86_BUILTIN_COMILESS,
23258 IX86_BUILTIN_COMIGTSS,
23259 IX86_BUILTIN_COMIGESS,
23260 IX86_BUILTIN_COMINEQSS,
23261 IX86_BUILTIN_UCOMIEQSS,
23262 IX86_BUILTIN_UCOMILTSS,
23263 IX86_BUILTIN_UCOMILESS,
23264 IX86_BUILTIN_UCOMIGTSS,
23265 IX86_BUILTIN_UCOMIGESS,
23266 IX86_BUILTIN_UCOMINEQSS,
23268 IX86_BUILTIN_CVTPI2PS,
23269 IX86_BUILTIN_CVTPS2PI,
23270 IX86_BUILTIN_CVTSI2SS,
23271 IX86_BUILTIN_CVTSI642SS,
23272 IX86_BUILTIN_CVTSS2SI,
23273 IX86_BUILTIN_CVTSS2SI64,
23274 IX86_BUILTIN_CVTTPS2PI,
23275 IX86_BUILTIN_CVTTSS2SI,
23276 IX86_BUILTIN_CVTTSS2SI64,
23278 IX86_BUILTIN_MAXPS,
23279 IX86_BUILTIN_MAXSS,
23280 IX86_BUILTIN_MINPS,
23281 IX86_BUILTIN_MINSS,
23283 IX86_BUILTIN_LOADUPS,
23284 IX86_BUILTIN_STOREUPS,
23285 IX86_BUILTIN_MOVSS,
23287 IX86_BUILTIN_MOVHLPS,
23288 IX86_BUILTIN_MOVLHPS,
23289 IX86_BUILTIN_LOADHPS,
23290 IX86_BUILTIN_LOADLPS,
23291 IX86_BUILTIN_STOREHPS,
23292 IX86_BUILTIN_STORELPS,
23294 IX86_BUILTIN_MASKMOVQ,
23295 IX86_BUILTIN_MOVMSKPS,
23296 IX86_BUILTIN_PMOVMSKB,
23298 IX86_BUILTIN_MOVNTPS,
23299 IX86_BUILTIN_MOVNTQ,
23301 IX86_BUILTIN_LOADDQU,
23302 IX86_BUILTIN_STOREDQU,
23304 IX86_BUILTIN_PACKSSWB,
23305 IX86_BUILTIN_PACKSSDW,
23306 IX86_BUILTIN_PACKUSWB,
23308 IX86_BUILTIN_PADDB,
23309 IX86_BUILTIN_PADDW,
23310 IX86_BUILTIN_PADDD,
23311 IX86_BUILTIN_PADDQ,
23312 IX86_BUILTIN_PADDSB,
23313 IX86_BUILTIN_PADDSW,
23314 IX86_BUILTIN_PADDUSB,
23315 IX86_BUILTIN_PADDUSW,
23316 IX86_BUILTIN_PSUBB,
23317 IX86_BUILTIN_PSUBW,
23318 IX86_BUILTIN_PSUBD,
23319 IX86_BUILTIN_PSUBQ,
23320 IX86_BUILTIN_PSUBSB,
23321 IX86_BUILTIN_PSUBSW,
23322 IX86_BUILTIN_PSUBUSB,
23323 IX86_BUILTIN_PSUBUSW,
23325 IX86_BUILTIN_PAND,
23326 IX86_BUILTIN_PANDN,
23327 IX86_BUILTIN_POR,
23328 IX86_BUILTIN_PXOR,
23330 IX86_BUILTIN_PAVGB,
23331 IX86_BUILTIN_PAVGW,
23333 IX86_BUILTIN_PCMPEQB,
23334 IX86_BUILTIN_PCMPEQW,
23335 IX86_BUILTIN_PCMPEQD,
23336 IX86_BUILTIN_PCMPGTB,
23337 IX86_BUILTIN_PCMPGTW,
23338 IX86_BUILTIN_PCMPGTD,
23340 IX86_BUILTIN_PMADDWD,
23342 IX86_BUILTIN_PMAXSW,
23343 IX86_BUILTIN_PMAXUB,
23344 IX86_BUILTIN_PMINSW,
23345 IX86_BUILTIN_PMINUB,
23347 IX86_BUILTIN_PMULHUW,
23348 IX86_BUILTIN_PMULHW,
23349 IX86_BUILTIN_PMULLW,
23351 IX86_BUILTIN_PSADBW,
23352 IX86_BUILTIN_PSHUFW,
23354 IX86_BUILTIN_PSLLW,
23355 IX86_BUILTIN_PSLLD,
23356 IX86_BUILTIN_PSLLQ,
23357 IX86_BUILTIN_PSRAW,
23358 IX86_BUILTIN_PSRAD,
23359 IX86_BUILTIN_PSRLW,
23360 IX86_BUILTIN_PSRLD,
23361 IX86_BUILTIN_PSRLQ,
23362 IX86_BUILTIN_PSLLWI,
23363 IX86_BUILTIN_PSLLDI,
23364 IX86_BUILTIN_PSLLQI,
23365 IX86_BUILTIN_PSRAWI,
23366 IX86_BUILTIN_PSRADI,
23367 IX86_BUILTIN_PSRLWI,
23368 IX86_BUILTIN_PSRLDI,
23369 IX86_BUILTIN_PSRLQI,
23371 IX86_BUILTIN_PUNPCKHBW,
23372 IX86_BUILTIN_PUNPCKHWD,
23373 IX86_BUILTIN_PUNPCKHDQ,
23374 IX86_BUILTIN_PUNPCKLBW,
23375 IX86_BUILTIN_PUNPCKLWD,
23376 IX86_BUILTIN_PUNPCKLDQ,
23378 IX86_BUILTIN_SHUFPS,
23380 IX86_BUILTIN_RCPPS,
23381 IX86_BUILTIN_RCPSS,
23382 IX86_BUILTIN_RSQRTPS,
23383 IX86_BUILTIN_RSQRTPS_NR,
23384 IX86_BUILTIN_RSQRTSS,
23385 IX86_BUILTIN_RSQRTF,
23386 IX86_BUILTIN_SQRTPS,
23387 IX86_BUILTIN_SQRTPS_NR,
23388 IX86_BUILTIN_SQRTSS,
23390 IX86_BUILTIN_UNPCKHPS,
23391 IX86_BUILTIN_UNPCKLPS,
23393 IX86_BUILTIN_ANDPS,
23394 IX86_BUILTIN_ANDNPS,
23395 IX86_BUILTIN_ORPS,
23396 IX86_BUILTIN_XORPS,
23398 IX86_BUILTIN_EMMS,
23399 IX86_BUILTIN_LDMXCSR,
23400 IX86_BUILTIN_STMXCSR,
23401 IX86_BUILTIN_SFENCE,
23403 /* 3DNow! Original */
23404 IX86_BUILTIN_FEMMS,
23405 IX86_BUILTIN_PAVGUSB,
23406 IX86_BUILTIN_PF2ID,
23407 IX86_BUILTIN_PFACC,
23408 IX86_BUILTIN_PFADD,
23409 IX86_BUILTIN_PFCMPEQ,
23410 IX86_BUILTIN_PFCMPGE,
23411 IX86_BUILTIN_PFCMPGT,
23412 IX86_BUILTIN_PFMAX,
23413 IX86_BUILTIN_PFMIN,
23414 IX86_BUILTIN_PFMUL,
23415 IX86_BUILTIN_PFRCP,
23416 IX86_BUILTIN_PFRCPIT1,
23417 IX86_BUILTIN_PFRCPIT2,
23418 IX86_BUILTIN_PFRSQIT1,
23419 IX86_BUILTIN_PFRSQRT,
23420 IX86_BUILTIN_PFSUB,
23421 IX86_BUILTIN_PFSUBR,
23422 IX86_BUILTIN_PI2FD,
23423 IX86_BUILTIN_PMULHRW,
23425 /* 3DNow! Athlon Extensions */
23426 IX86_BUILTIN_PF2IW,
23427 IX86_BUILTIN_PFNACC,
23428 IX86_BUILTIN_PFPNACC,
23429 IX86_BUILTIN_PI2FW,
23430 IX86_BUILTIN_PSWAPDSI,
23431 IX86_BUILTIN_PSWAPDSF,
23433 /* SSE2 */
23434 IX86_BUILTIN_ADDPD,
23435 IX86_BUILTIN_ADDSD,
23436 IX86_BUILTIN_DIVPD,
23437 IX86_BUILTIN_DIVSD,
23438 IX86_BUILTIN_MULPD,
23439 IX86_BUILTIN_MULSD,
23440 IX86_BUILTIN_SUBPD,
23441 IX86_BUILTIN_SUBSD,
23443 IX86_BUILTIN_CMPEQPD,
23444 IX86_BUILTIN_CMPLTPD,
23445 IX86_BUILTIN_CMPLEPD,
23446 IX86_BUILTIN_CMPGTPD,
23447 IX86_BUILTIN_CMPGEPD,
23448 IX86_BUILTIN_CMPNEQPD,
23449 IX86_BUILTIN_CMPNLTPD,
23450 IX86_BUILTIN_CMPNLEPD,
23451 IX86_BUILTIN_CMPNGTPD,
23452 IX86_BUILTIN_CMPNGEPD,
23453 IX86_BUILTIN_CMPORDPD,
23454 IX86_BUILTIN_CMPUNORDPD,
23455 IX86_BUILTIN_CMPEQSD,
23456 IX86_BUILTIN_CMPLTSD,
23457 IX86_BUILTIN_CMPLESD,
23458 IX86_BUILTIN_CMPNEQSD,
23459 IX86_BUILTIN_CMPNLTSD,
23460 IX86_BUILTIN_CMPNLESD,
23461 IX86_BUILTIN_CMPORDSD,
23462 IX86_BUILTIN_CMPUNORDSD,
23464 IX86_BUILTIN_COMIEQSD,
23465 IX86_BUILTIN_COMILTSD,
23466 IX86_BUILTIN_COMILESD,
23467 IX86_BUILTIN_COMIGTSD,
23468 IX86_BUILTIN_COMIGESD,
23469 IX86_BUILTIN_COMINEQSD,
23470 IX86_BUILTIN_UCOMIEQSD,
23471 IX86_BUILTIN_UCOMILTSD,
23472 IX86_BUILTIN_UCOMILESD,
23473 IX86_BUILTIN_UCOMIGTSD,
23474 IX86_BUILTIN_UCOMIGESD,
23475 IX86_BUILTIN_UCOMINEQSD,
23477 IX86_BUILTIN_MAXPD,
23478 IX86_BUILTIN_MAXSD,
23479 IX86_BUILTIN_MINPD,
23480 IX86_BUILTIN_MINSD,
23482 IX86_BUILTIN_ANDPD,
23483 IX86_BUILTIN_ANDNPD,
23484 IX86_BUILTIN_ORPD,
23485 IX86_BUILTIN_XORPD,
23487 IX86_BUILTIN_SQRTPD,
23488 IX86_BUILTIN_SQRTSD,
23490 IX86_BUILTIN_UNPCKHPD,
23491 IX86_BUILTIN_UNPCKLPD,
23493 IX86_BUILTIN_SHUFPD,
23495 IX86_BUILTIN_LOADUPD,
23496 IX86_BUILTIN_STOREUPD,
23497 IX86_BUILTIN_MOVSD,
23499 IX86_BUILTIN_LOADHPD,
23500 IX86_BUILTIN_LOADLPD,
23502 IX86_BUILTIN_CVTDQ2PD,
23503 IX86_BUILTIN_CVTDQ2PS,
23505 IX86_BUILTIN_CVTPD2DQ,
23506 IX86_BUILTIN_CVTPD2PI,
23507 IX86_BUILTIN_CVTPD2PS,
23508 IX86_BUILTIN_CVTTPD2DQ,
23509 IX86_BUILTIN_CVTTPD2PI,
23511 IX86_BUILTIN_CVTPI2PD,
23512 IX86_BUILTIN_CVTSI2SD,
23513 IX86_BUILTIN_CVTSI642SD,
23515 IX86_BUILTIN_CVTSD2SI,
23516 IX86_BUILTIN_CVTSD2SI64,
23517 IX86_BUILTIN_CVTSD2SS,
23518 IX86_BUILTIN_CVTSS2SD,
23519 IX86_BUILTIN_CVTTSD2SI,
23520 IX86_BUILTIN_CVTTSD2SI64,
23522 IX86_BUILTIN_CVTPS2DQ,
23523 IX86_BUILTIN_CVTPS2PD,
23524 IX86_BUILTIN_CVTTPS2DQ,
23526 IX86_BUILTIN_MOVNTI,
23527 IX86_BUILTIN_MOVNTPD,
23528 IX86_BUILTIN_MOVNTDQ,
23530 IX86_BUILTIN_MOVQ128,
23532 /* SSE2 MMX */
23533 IX86_BUILTIN_MASKMOVDQU,
23534 IX86_BUILTIN_MOVMSKPD,
23535 IX86_BUILTIN_PMOVMSKB128,
23537 IX86_BUILTIN_PACKSSWB128,
23538 IX86_BUILTIN_PACKSSDW128,
23539 IX86_BUILTIN_PACKUSWB128,
23541 IX86_BUILTIN_PADDB128,
23542 IX86_BUILTIN_PADDW128,
23543 IX86_BUILTIN_PADDD128,
23544 IX86_BUILTIN_PADDQ128,
23545 IX86_BUILTIN_PADDSB128,
23546 IX86_BUILTIN_PADDSW128,
23547 IX86_BUILTIN_PADDUSB128,
23548 IX86_BUILTIN_PADDUSW128,
23549 IX86_BUILTIN_PSUBB128,
23550 IX86_BUILTIN_PSUBW128,
23551 IX86_BUILTIN_PSUBD128,
23552 IX86_BUILTIN_PSUBQ128,
23553 IX86_BUILTIN_PSUBSB128,
23554 IX86_BUILTIN_PSUBSW128,
23555 IX86_BUILTIN_PSUBUSB128,
23556 IX86_BUILTIN_PSUBUSW128,
23558 IX86_BUILTIN_PAND128,
23559 IX86_BUILTIN_PANDN128,
23560 IX86_BUILTIN_POR128,
23561 IX86_BUILTIN_PXOR128,
23563 IX86_BUILTIN_PAVGB128,
23564 IX86_BUILTIN_PAVGW128,
23566 IX86_BUILTIN_PCMPEQB128,
23567 IX86_BUILTIN_PCMPEQW128,
23568 IX86_BUILTIN_PCMPEQD128,
23569 IX86_BUILTIN_PCMPGTB128,
23570 IX86_BUILTIN_PCMPGTW128,
23571 IX86_BUILTIN_PCMPGTD128,
23573 IX86_BUILTIN_PMADDWD128,
23575 IX86_BUILTIN_PMAXSW128,
23576 IX86_BUILTIN_PMAXUB128,
23577 IX86_BUILTIN_PMINSW128,
23578 IX86_BUILTIN_PMINUB128,
23580 IX86_BUILTIN_PMULUDQ,
23581 IX86_BUILTIN_PMULUDQ128,
23582 IX86_BUILTIN_PMULHUW128,
23583 IX86_BUILTIN_PMULHW128,
23584 IX86_BUILTIN_PMULLW128,
23586 IX86_BUILTIN_PSADBW128,
23587 IX86_BUILTIN_PSHUFHW,
23588 IX86_BUILTIN_PSHUFLW,
23589 IX86_BUILTIN_PSHUFD,
23591 IX86_BUILTIN_PSLLDQI128,
23592 IX86_BUILTIN_PSLLWI128,
23593 IX86_BUILTIN_PSLLDI128,
23594 IX86_BUILTIN_PSLLQI128,
23595 IX86_BUILTIN_PSRAWI128,
23596 IX86_BUILTIN_PSRADI128,
23597 IX86_BUILTIN_PSRLDQI128,
23598 IX86_BUILTIN_PSRLWI128,
23599 IX86_BUILTIN_PSRLDI128,
23600 IX86_BUILTIN_PSRLQI128,
23602 IX86_BUILTIN_PSLLDQ128,
23603 IX86_BUILTIN_PSLLW128,
23604 IX86_BUILTIN_PSLLD128,
23605 IX86_BUILTIN_PSLLQ128,
23606 IX86_BUILTIN_PSRAW128,
23607 IX86_BUILTIN_PSRAD128,
23608 IX86_BUILTIN_PSRLW128,
23609 IX86_BUILTIN_PSRLD128,
23610 IX86_BUILTIN_PSRLQ128,
23612 IX86_BUILTIN_PUNPCKHBW128,
23613 IX86_BUILTIN_PUNPCKHWD128,
23614 IX86_BUILTIN_PUNPCKHDQ128,
23615 IX86_BUILTIN_PUNPCKHQDQ128,
23616 IX86_BUILTIN_PUNPCKLBW128,
23617 IX86_BUILTIN_PUNPCKLWD128,
23618 IX86_BUILTIN_PUNPCKLDQ128,
23619 IX86_BUILTIN_PUNPCKLQDQ128,
23621 IX86_BUILTIN_CLFLUSH,
23622 IX86_BUILTIN_MFENCE,
23623 IX86_BUILTIN_LFENCE,
23625 IX86_BUILTIN_BSRSI,
23626 IX86_BUILTIN_BSRDI,
23627 IX86_BUILTIN_RDPMC,
23628 IX86_BUILTIN_RDTSC,
23629 IX86_BUILTIN_RDTSCP,
23630 IX86_BUILTIN_ROLQI,
23631 IX86_BUILTIN_ROLHI,
23632 IX86_BUILTIN_RORQI,
23633 IX86_BUILTIN_RORHI,
23635 /* SSE3. */
23636 IX86_BUILTIN_ADDSUBPS,
23637 IX86_BUILTIN_HADDPS,
23638 IX86_BUILTIN_HSUBPS,
23639 IX86_BUILTIN_MOVSHDUP,
23640 IX86_BUILTIN_MOVSLDUP,
23641 IX86_BUILTIN_ADDSUBPD,
23642 IX86_BUILTIN_HADDPD,
23643 IX86_BUILTIN_HSUBPD,
23644 IX86_BUILTIN_LDDQU,
23646 IX86_BUILTIN_MONITOR,
23647 IX86_BUILTIN_MWAIT,
23649 /* SSSE3. */
23650 IX86_BUILTIN_PHADDW,
23651 IX86_BUILTIN_PHADDD,
23652 IX86_BUILTIN_PHADDSW,
23653 IX86_BUILTIN_PHSUBW,
23654 IX86_BUILTIN_PHSUBD,
23655 IX86_BUILTIN_PHSUBSW,
23656 IX86_BUILTIN_PMADDUBSW,
23657 IX86_BUILTIN_PMULHRSW,
23658 IX86_BUILTIN_PSHUFB,
23659 IX86_BUILTIN_PSIGNB,
23660 IX86_BUILTIN_PSIGNW,
23661 IX86_BUILTIN_PSIGND,
23662 IX86_BUILTIN_PALIGNR,
23663 IX86_BUILTIN_PABSB,
23664 IX86_BUILTIN_PABSW,
23665 IX86_BUILTIN_PABSD,
23667 IX86_BUILTIN_PHADDW128,
23668 IX86_BUILTIN_PHADDD128,
23669 IX86_BUILTIN_PHADDSW128,
23670 IX86_BUILTIN_PHSUBW128,
23671 IX86_BUILTIN_PHSUBD128,
23672 IX86_BUILTIN_PHSUBSW128,
23673 IX86_BUILTIN_PMADDUBSW128,
23674 IX86_BUILTIN_PMULHRSW128,
23675 IX86_BUILTIN_PSHUFB128,
23676 IX86_BUILTIN_PSIGNB128,
23677 IX86_BUILTIN_PSIGNW128,
23678 IX86_BUILTIN_PSIGND128,
23679 IX86_BUILTIN_PALIGNR128,
23680 IX86_BUILTIN_PABSB128,
23681 IX86_BUILTIN_PABSW128,
23682 IX86_BUILTIN_PABSD128,
23684 /* AMDFAM10 - SSE4A New Instructions. */
23685 IX86_BUILTIN_MOVNTSD,
23686 IX86_BUILTIN_MOVNTSS,
23687 IX86_BUILTIN_EXTRQI,
23688 IX86_BUILTIN_EXTRQ,
23689 IX86_BUILTIN_INSERTQI,
23690 IX86_BUILTIN_INSERTQ,
23692 /* SSE4.1. */
23693 IX86_BUILTIN_BLENDPD,
23694 IX86_BUILTIN_BLENDPS,
23695 IX86_BUILTIN_BLENDVPD,
23696 IX86_BUILTIN_BLENDVPS,
23697 IX86_BUILTIN_PBLENDVB128,
23698 IX86_BUILTIN_PBLENDW128,
23700 IX86_BUILTIN_DPPD,
23701 IX86_BUILTIN_DPPS,
23703 IX86_BUILTIN_INSERTPS128,
23705 IX86_BUILTIN_MOVNTDQA,
23706 IX86_BUILTIN_MPSADBW128,
23707 IX86_BUILTIN_PACKUSDW128,
23708 IX86_BUILTIN_PCMPEQQ,
23709 IX86_BUILTIN_PHMINPOSUW128,
23711 IX86_BUILTIN_PMAXSB128,
23712 IX86_BUILTIN_PMAXSD128,
23713 IX86_BUILTIN_PMAXUD128,
23714 IX86_BUILTIN_PMAXUW128,
23716 IX86_BUILTIN_PMINSB128,
23717 IX86_BUILTIN_PMINSD128,
23718 IX86_BUILTIN_PMINUD128,
23719 IX86_BUILTIN_PMINUW128,
23721 IX86_BUILTIN_PMOVSXBW128,
23722 IX86_BUILTIN_PMOVSXBD128,
23723 IX86_BUILTIN_PMOVSXBQ128,
23724 IX86_BUILTIN_PMOVSXWD128,
23725 IX86_BUILTIN_PMOVSXWQ128,
23726 IX86_BUILTIN_PMOVSXDQ128,
23728 IX86_BUILTIN_PMOVZXBW128,
23729 IX86_BUILTIN_PMOVZXBD128,
23730 IX86_BUILTIN_PMOVZXBQ128,
23731 IX86_BUILTIN_PMOVZXWD128,
23732 IX86_BUILTIN_PMOVZXWQ128,
23733 IX86_BUILTIN_PMOVZXDQ128,
23735 IX86_BUILTIN_PMULDQ128,
23736 IX86_BUILTIN_PMULLD128,
23738 IX86_BUILTIN_ROUNDPD,
23739 IX86_BUILTIN_ROUNDPS,
23740 IX86_BUILTIN_ROUNDSD,
23741 IX86_BUILTIN_ROUNDSS,
23743 IX86_BUILTIN_PTESTZ,
23744 IX86_BUILTIN_PTESTC,
23745 IX86_BUILTIN_PTESTNZC,
23747 IX86_BUILTIN_VEC_INIT_V2SI,
23748 IX86_BUILTIN_VEC_INIT_V4HI,
23749 IX86_BUILTIN_VEC_INIT_V8QI,
23750 IX86_BUILTIN_VEC_EXT_V2DF,
23751 IX86_BUILTIN_VEC_EXT_V2DI,
23752 IX86_BUILTIN_VEC_EXT_V4SF,
23753 IX86_BUILTIN_VEC_EXT_V4SI,
23754 IX86_BUILTIN_VEC_EXT_V8HI,
23755 IX86_BUILTIN_VEC_EXT_V2SI,
23756 IX86_BUILTIN_VEC_EXT_V4HI,
23757 IX86_BUILTIN_VEC_EXT_V16QI,
23758 IX86_BUILTIN_VEC_SET_V2DI,
23759 IX86_BUILTIN_VEC_SET_V4SF,
23760 IX86_BUILTIN_VEC_SET_V4SI,
23761 IX86_BUILTIN_VEC_SET_V8HI,
23762 IX86_BUILTIN_VEC_SET_V4HI,
23763 IX86_BUILTIN_VEC_SET_V16QI,
23765 IX86_BUILTIN_VEC_PACK_SFIX,
23767 /* SSE4.2. */
23768 IX86_BUILTIN_CRC32QI,
23769 IX86_BUILTIN_CRC32HI,
23770 IX86_BUILTIN_CRC32SI,
23771 IX86_BUILTIN_CRC32DI,
23773 IX86_BUILTIN_PCMPESTRI128,
23774 IX86_BUILTIN_PCMPESTRM128,
23775 IX86_BUILTIN_PCMPESTRA128,
23776 IX86_BUILTIN_PCMPESTRC128,
23777 IX86_BUILTIN_PCMPESTRO128,
23778 IX86_BUILTIN_PCMPESTRS128,
23779 IX86_BUILTIN_PCMPESTRZ128,
23780 IX86_BUILTIN_PCMPISTRI128,
23781 IX86_BUILTIN_PCMPISTRM128,
23782 IX86_BUILTIN_PCMPISTRA128,
23783 IX86_BUILTIN_PCMPISTRC128,
23784 IX86_BUILTIN_PCMPISTRO128,
23785 IX86_BUILTIN_PCMPISTRS128,
23786 IX86_BUILTIN_PCMPISTRZ128,
23788 IX86_BUILTIN_PCMPGTQ,
23790 /* AES instructions */
23791 IX86_BUILTIN_AESENC128,
23792 IX86_BUILTIN_AESENCLAST128,
23793 IX86_BUILTIN_AESDEC128,
23794 IX86_BUILTIN_AESDECLAST128,
23795 IX86_BUILTIN_AESIMC128,
23796 IX86_BUILTIN_AESKEYGENASSIST128,
23798 /* PCLMUL instruction */
23799 IX86_BUILTIN_PCLMULQDQ128,
23801 /* AVX */
23802 IX86_BUILTIN_ADDPD256,
23803 IX86_BUILTIN_ADDPS256,
23804 IX86_BUILTIN_ADDSUBPD256,
23805 IX86_BUILTIN_ADDSUBPS256,
23806 IX86_BUILTIN_ANDPD256,
23807 IX86_BUILTIN_ANDPS256,
23808 IX86_BUILTIN_ANDNPD256,
23809 IX86_BUILTIN_ANDNPS256,
23810 IX86_BUILTIN_BLENDPD256,
23811 IX86_BUILTIN_BLENDPS256,
23812 IX86_BUILTIN_BLENDVPD256,
23813 IX86_BUILTIN_BLENDVPS256,
23814 IX86_BUILTIN_DIVPD256,
23815 IX86_BUILTIN_DIVPS256,
23816 IX86_BUILTIN_DPPS256,
23817 IX86_BUILTIN_HADDPD256,
23818 IX86_BUILTIN_HADDPS256,
23819 IX86_BUILTIN_HSUBPD256,
23820 IX86_BUILTIN_HSUBPS256,
23821 IX86_BUILTIN_MAXPD256,
23822 IX86_BUILTIN_MAXPS256,
23823 IX86_BUILTIN_MINPD256,
23824 IX86_BUILTIN_MINPS256,
23825 IX86_BUILTIN_MULPD256,
23826 IX86_BUILTIN_MULPS256,
23827 IX86_BUILTIN_ORPD256,
23828 IX86_BUILTIN_ORPS256,
23829 IX86_BUILTIN_SHUFPD256,
23830 IX86_BUILTIN_SHUFPS256,
23831 IX86_BUILTIN_SUBPD256,
23832 IX86_BUILTIN_SUBPS256,
23833 IX86_BUILTIN_XORPD256,
23834 IX86_BUILTIN_XORPS256,
23835 IX86_BUILTIN_CMPSD,
23836 IX86_BUILTIN_CMPSS,
23837 IX86_BUILTIN_CMPPD,
23838 IX86_BUILTIN_CMPPS,
23839 IX86_BUILTIN_CMPPD256,
23840 IX86_BUILTIN_CMPPS256,
23841 IX86_BUILTIN_CVTDQ2PD256,
23842 IX86_BUILTIN_CVTDQ2PS256,
23843 IX86_BUILTIN_CVTPD2PS256,
23844 IX86_BUILTIN_CVTPS2DQ256,
23845 IX86_BUILTIN_CVTPS2PD256,
23846 IX86_BUILTIN_CVTTPD2DQ256,
23847 IX86_BUILTIN_CVTPD2DQ256,
23848 IX86_BUILTIN_CVTTPS2DQ256,
23849 IX86_BUILTIN_EXTRACTF128PD256,
23850 IX86_BUILTIN_EXTRACTF128PS256,
23851 IX86_BUILTIN_EXTRACTF128SI256,
23852 IX86_BUILTIN_VZEROALL,
23853 IX86_BUILTIN_VZEROUPPER,
23854 IX86_BUILTIN_VPERMILVARPD,
23855 IX86_BUILTIN_VPERMILVARPS,
23856 IX86_BUILTIN_VPERMILVARPD256,
23857 IX86_BUILTIN_VPERMILVARPS256,
23858 IX86_BUILTIN_VPERMILPD,
23859 IX86_BUILTIN_VPERMILPS,
23860 IX86_BUILTIN_VPERMILPD256,
23861 IX86_BUILTIN_VPERMILPS256,
23862 IX86_BUILTIN_VPERMIL2PD,
23863 IX86_BUILTIN_VPERMIL2PS,
23864 IX86_BUILTIN_VPERMIL2PD256,
23865 IX86_BUILTIN_VPERMIL2PS256,
23866 IX86_BUILTIN_VPERM2F128PD256,
23867 IX86_BUILTIN_VPERM2F128PS256,
23868 IX86_BUILTIN_VPERM2F128SI256,
23869 IX86_BUILTIN_VBROADCASTSS,
23870 IX86_BUILTIN_VBROADCASTSD256,
23871 IX86_BUILTIN_VBROADCASTSS256,
23872 IX86_BUILTIN_VBROADCASTPD256,
23873 IX86_BUILTIN_VBROADCASTPS256,
23874 IX86_BUILTIN_VINSERTF128PD256,
23875 IX86_BUILTIN_VINSERTF128PS256,
23876 IX86_BUILTIN_VINSERTF128SI256,
23877 IX86_BUILTIN_LOADUPD256,
23878 IX86_BUILTIN_LOADUPS256,
23879 IX86_BUILTIN_STOREUPD256,
23880 IX86_BUILTIN_STOREUPS256,
23881 IX86_BUILTIN_LDDQU256,
23882 IX86_BUILTIN_MOVNTDQ256,
23883 IX86_BUILTIN_MOVNTPD256,
23884 IX86_BUILTIN_MOVNTPS256,
23885 IX86_BUILTIN_LOADDQU256,
23886 IX86_BUILTIN_STOREDQU256,
23887 IX86_BUILTIN_MASKLOADPD,
23888 IX86_BUILTIN_MASKLOADPS,
23889 IX86_BUILTIN_MASKSTOREPD,
23890 IX86_BUILTIN_MASKSTOREPS,
23891 IX86_BUILTIN_MASKLOADPD256,
23892 IX86_BUILTIN_MASKLOADPS256,
23893 IX86_BUILTIN_MASKSTOREPD256,
23894 IX86_BUILTIN_MASKSTOREPS256,
23895 IX86_BUILTIN_MOVSHDUP256,
23896 IX86_BUILTIN_MOVSLDUP256,
23897 IX86_BUILTIN_MOVDDUP256,
23899 IX86_BUILTIN_SQRTPD256,
23900 IX86_BUILTIN_SQRTPS256,
23901 IX86_BUILTIN_SQRTPS_NR256,
23902 IX86_BUILTIN_RSQRTPS256,
23903 IX86_BUILTIN_RSQRTPS_NR256,
23905 IX86_BUILTIN_RCPPS256,
23907 IX86_BUILTIN_ROUNDPD256,
23908 IX86_BUILTIN_ROUNDPS256,
23910 IX86_BUILTIN_UNPCKHPD256,
23911 IX86_BUILTIN_UNPCKLPD256,
23912 IX86_BUILTIN_UNPCKHPS256,
23913 IX86_BUILTIN_UNPCKLPS256,
23915 IX86_BUILTIN_SI256_SI,
23916 IX86_BUILTIN_PS256_PS,
23917 IX86_BUILTIN_PD256_PD,
23918 IX86_BUILTIN_SI_SI256,
23919 IX86_BUILTIN_PS_PS256,
23920 IX86_BUILTIN_PD_PD256,
23922 IX86_BUILTIN_VTESTZPD,
23923 IX86_BUILTIN_VTESTCPD,
23924 IX86_BUILTIN_VTESTNZCPD,
23925 IX86_BUILTIN_VTESTZPS,
23926 IX86_BUILTIN_VTESTCPS,
23927 IX86_BUILTIN_VTESTNZCPS,
23928 IX86_BUILTIN_VTESTZPD256,
23929 IX86_BUILTIN_VTESTCPD256,
23930 IX86_BUILTIN_VTESTNZCPD256,
23931 IX86_BUILTIN_VTESTZPS256,
23932 IX86_BUILTIN_VTESTCPS256,
23933 IX86_BUILTIN_VTESTNZCPS256,
23934 IX86_BUILTIN_PTESTZ256,
23935 IX86_BUILTIN_PTESTC256,
23936 IX86_BUILTIN_PTESTNZC256,
23938 IX86_BUILTIN_MOVMSKPD256,
23939 IX86_BUILTIN_MOVMSKPS256,
23941 /* TFmode support builtins. */
23942 IX86_BUILTIN_INFQ,
23943 IX86_BUILTIN_HUGE_VALQ,
23944 IX86_BUILTIN_FABSQ,
23945 IX86_BUILTIN_COPYSIGNQ,
23947 /* Vectorizer support builtins. */
23948 IX86_BUILTIN_CPYSGNPS,
23949 IX86_BUILTIN_CPYSGNPD,
23950 IX86_BUILTIN_CPYSGNPS256,
23951 IX86_BUILTIN_CPYSGNPD256,
23953 IX86_BUILTIN_CVTUDQ2PS,
23955 IX86_BUILTIN_VEC_PERM_V2DF,
23956 IX86_BUILTIN_VEC_PERM_V4SF,
23957 IX86_BUILTIN_VEC_PERM_V2DI,
23958 IX86_BUILTIN_VEC_PERM_V4SI,
23959 IX86_BUILTIN_VEC_PERM_V8HI,
23960 IX86_BUILTIN_VEC_PERM_V16QI,
23961 IX86_BUILTIN_VEC_PERM_V2DI_U,
23962 IX86_BUILTIN_VEC_PERM_V4SI_U,
23963 IX86_BUILTIN_VEC_PERM_V8HI_U,
23964 IX86_BUILTIN_VEC_PERM_V16QI_U,
23965 IX86_BUILTIN_VEC_PERM_V4DF,
23966 IX86_BUILTIN_VEC_PERM_V8SF,
23968 /* FMA4 and XOP instructions. */
23969 IX86_BUILTIN_VFMADDSS,
23970 IX86_BUILTIN_VFMADDSD,
23971 IX86_BUILTIN_VFMADDPS,
23972 IX86_BUILTIN_VFMADDPD,
23973 IX86_BUILTIN_VFMADDPS256,
23974 IX86_BUILTIN_VFMADDPD256,
23975 IX86_BUILTIN_VFMADDSUBPS,
23976 IX86_BUILTIN_VFMADDSUBPD,
23977 IX86_BUILTIN_VFMADDSUBPS256,
23978 IX86_BUILTIN_VFMADDSUBPD256,
23980 IX86_BUILTIN_VPCMOV,
23981 IX86_BUILTIN_VPCMOV_V2DI,
23982 IX86_BUILTIN_VPCMOV_V4SI,
23983 IX86_BUILTIN_VPCMOV_V8HI,
23984 IX86_BUILTIN_VPCMOV_V16QI,
23985 IX86_BUILTIN_VPCMOV_V4SF,
23986 IX86_BUILTIN_VPCMOV_V2DF,
23987 IX86_BUILTIN_VPCMOV256,
23988 IX86_BUILTIN_VPCMOV_V4DI256,
23989 IX86_BUILTIN_VPCMOV_V8SI256,
23990 IX86_BUILTIN_VPCMOV_V16HI256,
23991 IX86_BUILTIN_VPCMOV_V32QI256,
23992 IX86_BUILTIN_VPCMOV_V8SF256,
23993 IX86_BUILTIN_VPCMOV_V4DF256,
23995 IX86_BUILTIN_VPPERM,
23997 IX86_BUILTIN_VPMACSSWW,
23998 IX86_BUILTIN_VPMACSWW,
23999 IX86_BUILTIN_VPMACSSWD,
24000 IX86_BUILTIN_VPMACSWD,
24001 IX86_BUILTIN_VPMACSSDD,
24002 IX86_BUILTIN_VPMACSDD,
24003 IX86_BUILTIN_VPMACSSDQL,
24004 IX86_BUILTIN_VPMACSSDQH,
24005 IX86_BUILTIN_VPMACSDQL,
24006 IX86_BUILTIN_VPMACSDQH,
24007 IX86_BUILTIN_VPMADCSSWD,
24008 IX86_BUILTIN_VPMADCSWD,
24010 IX86_BUILTIN_VPHADDBW,
24011 IX86_BUILTIN_VPHADDBD,
24012 IX86_BUILTIN_VPHADDBQ,
24013 IX86_BUILTIN_VPHADDWD,
24014 IX86_BUILTIN_VPHADDWQ,
24015 IX86_BUILTIN_VPHADDDQ,
24016 IX86_BUILTIN_VPHADDUBW,
24017 IX86_BUILTIN_VPHADDUBD,
24018 IX86_BUILTIN_VPHADDUBQ,
24019 IX86_BUILTIN_VPHADDUWD,
24020 IX86_BUILTIN_VPHADDUWQ,
24021 IX86_BUILTIN_VPHADDUDQ,
24022 IX86_BUILTIN_VPHSUBBW,
24023 IX86_BUILTIN_VPHSUBWD,
24024 IX86_BUILTIN_VPHSUBDQ,
24026 IX86_BUILTIN_VPROTB,
24027 IX86_BUILTIN_VPROTW,
24028 IX86_BUILTIN_VPROTD,
24029 IX86_BUILTIN_VPROTQ,
24030 IX86_BUILTIN_VPROTB_IMM,
24031 IX86_BUILTIN_VPROTW_IMM,
24032 IX86_BUILTIN_VPROTD_IMM,
24033 IX86_BUILTIN_VPROTQ_IMM,
24035 IX86_BUILTIN_VPSHLB,
24036 IX86_BUILTIN_VPSHLW,
24037 IX86_BUILTIN_VPSHLD,
24038 IX86_BUILTIN_VPSHLQ,
24039 IX86_BUILTIN_VPSHAB,
24040 IX86_BUILTIN_VPSHAW,
24041 IX86_BUILTIN_VPSHAD,
24042 IX86_BUILTIN_VPSHAQ,
24044 IX86_BUILTIN_VFRCZSS,
24045 IX86_BUILTIN_VFRCZSD,
24046 IX86_BUILTIN_VFRCZPS,
24047 IX86_BUILTIN_VFRCZPD,
24048 IX86_BUILTIN_VFRCZPS256,
24049 IX86_BUILTIN_VFRCZPD256,
24051 IX86_BUILTIN_VPCOMEQUB,
24052 IX86_BUILTIN_VPCOMNEUB,
24053 IX86_BUILTIN_VPCOMLTUB,
24054 IX86_BUILTIN_VPCOMLEUB,
24055 IX86_BUILTIN_VPCOMGTUB,
24056 IX86_BUILTIN_VPCOMGEUB,
24057 IX86_BUILTIN_VPCOMFALSEUB,
24058 IX86_BUILTIN_VPCOMTRUEUB,
24060 IX86_BUILTIN_VPCOMEQUW,
24061 IX86_BUILTIN_VPCOMNEUW,
24062 IX86_BUILTIN_VPCOMLTUW,
24063 IX86_BUILTIN_VPCOMLEUW,
24064 IX86_BUILTIN_VPCOMGTUW,
24065 IX86_BUILTIN_VPCOMGEUW,
24066 IX86_BUILTIN_VPCOMFALSEUW,
24067 IX86_BUILTIN_VPCOMTRUEUW,
24069 IX86_BUILTIN_VPCOMEQUD,
24070 IX86_BUILTIN_VPCOMNEUD,
24071 IX86_BUILTIN_VPCOMLTUD,
24072 IX86_BUILTIN_VPCOMLEUD,
24073 IX86_BUILTIN_VPCOMGTUD,
24074 IX86_BUILTIN_VPCOMGEUD,
24075 IX86_BUILTIN_VPCOMFALSEUD,
24076 IX86_BUILTIN_VPCOMTRUEUD,
24078 IX86_BUILTIN_VPCOMEQUQ,
24079 IX86_BUILTIN_VPCOMNEUQ,
24080 IX86_BUILTIN_VPCOMLTUQ,
24081 IX86_BUILTIN_VPCOMLEUQ,
24082 IX86_BUILTIN_VPCOMGTUQ,
24083 IX86_BUILTIN_VPCOMGEUQ,
24084 IX86_BUILTIN_VPCOMFALSEUQ,
24085 IX86_BUILTIN_VPCOMTRUEUQ,
24087 IX86_BUILTIN_VPCOMEQB,
24088 IX86_BUILTIN_VPCOMNEB,
24089 IX86_BUILTIN_VPCOMLTB,
24090 IX86_BUILTIN_VPCOMLEB,
24091 IX86_BUILTIN_VPCOMGTB,
24092 IX86_BUILTIN_VPCOMGEB,
24093 IX86_BUILTIN_VPCOMFALSEB,
24094 IX86_BUILTIN_VPCOMTRUEB,
24096 IX86_BUILTIN_VPCOMEQW,
24097 IX86_BUILTIN_VPCOMNEW,
24098 IX86_BUILTIN_VPCOMLTW,
24099 IX86_BUILTIN_VPCOMLEW,
24100 IX86_BUILTIN_VPCOMGTW,
24101 IX86_BUILTIN_VPCOMGEW,
24102 IX86_BUILTIN_VPCOMFALSEW,
24103 IX86_BUILTIN_VPCOMTRUEW,
24105 IX86_BUILTIN_VPCOMEQD,
24106 IX86_BUILTIN_VPCOMNED,
24107 IX86_BUILTIN_VPCOMLTD,
24108 IX86_BUILTIN_VPCOMLED,
24109 IX86_BUILTIN_VPCOMGTD,
24110 IX86_BUILTIN_VPCOMGED,
24111 IX86_BUILTIN_VPCOMFALSED,
24112 IX86_BUILTIN_VPCOMTRUED,
24114 IX86_BUILTIN_VPCOMEQQ,
24115 IX86_BUILTIN_VPCOMNEQ,
24116 IX86_BUILTIN_VPCOMLTQ,
24117 IX86_BUILTIN_VPCOMLEQ,
24118 IX86_BUILTIN_VPCOMGTQ,
24119 IX86_BUILTIN_VPCOMGEQ,
24120 IX86_BUILTIN_VPCOMFALSEQ,
24121 IX86_BUILTIN_VPCOMTRUEQ,
24123 /* LWP instructions. */
24124 IX86_BUILTIN_LLWPCB,
24125 IX86_BUILTIN_SLWPCB,
24126 IX86_BUILTIN_LWPVAL32,
24127 IX86_BUILTIN_LWPVAL64,
24128 IX86_BUILTIN_LWPINS32,
24129 IX86_BUILTIN_LWPINS64,
24131 IX86_BUILTIN_CLZS,
24133 /* BMI instructions. */
24134 IX86_BUILTIN_BEXTR32,
24135 IX86_BUILTIN_BEXTR64,
24136 IX86_BUILTIN_CTZS,
24138 /* TBM instructions. */
24139 IX86_BUILTIN_BEXTRI32,
24140 IX86_BUILTIN_BEXTRI64,
24143 /* FSGSBASE instructions. */
24144 IX86_BUILTIN_RDFSBASE32,
24145 IX86_BUILTIN_RDFSBASE64,
24146 IX86_BUILTIN_RDGSBASE32,
24147 IX86_BUILTIN_RDGSBASE64,
24148 IX86_BUILTIN_WRFSBASE32,
24149 IX86_BUILTIN_WRFSBASE64,
24150 IX86_BUILTIN_WRGSBASE32,
24151 IX86_BUILTIN_WRGSBASE64,
24153 /* RDRND instructions. */
24154 IX86_BUILTIN_RDRAND16_STEP,
24155 IX86_BUILTIN_RDRAND32_STEP,
24156 IX86_BUILTIN_RDRAND64_STEP,
24158 /* F16C instructions. */
24159 IX86_BUILTIN_CVTPH2PS,
24160 IX86_BUILTIN_CVTPH2PS256,
24161 IX86_BUILTIN_CVTPS2PH,
24162 IX86_BUILTIN_CVTPS2PH256,
24164 IX86_BUILTIN_MAX
24165 };
24167 /* Table for the ix86 builtin decls. */
24170 /* Table of all of the builtin functions that are possible with different ISA's
24171 but are waiting to be built until a function is declared to use that
24172 ISA. */
24179 };
24184 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
24185 of which isa_flags to use in the ix86_builtins_isa array. Stores the
24186 function decl in the ix86_builtins array. Returns the function decl or
24187 NULL_TREE, if the builtin was not added.
24189 If the front end has a special hook for builtin functions, delay adding
24190 builtin functions that aren't in the current ISA until the ISA is changed
24191 with function specific optimization. Doing so, can save about 300K for the
24192 default compiler. When the builtin is expanded, check at that time whether
24193 it is valid.
24195 If the front end doesn't have a special hook, record all builtins, even if
24196 it isn't an instruction set in the current ISA in case the user uses
24197 function specific options for a different ISA, so that we don't get scope
24198 errors if a builtin is added in the middle of a function scope. */
24203 {
24207 {
24216 {
24222 }
24223 else
24224 {
24230 }
24231 }
24234 }
24236 /* Like def_builtin, but also marks the function decl "const". */
24241 {
24245 else
24249 }
24251 /* Add any new builtin functions for a given ISA that may not have been
24252 declared. This saves a bit of space compared to adding all of the
24253 declarations to the tree, even if we didn't use them. */
24255 static void
24257 {
24261 {
24264 {
24267 /* Don't define the builtin again. */
24273 NULL_TREE);
24278 }
24279 }
24280 }
24282 /* Bits for builtin_description.flag. */
24284 /* Set when we don't support the comparison natively, and should
24285 swap_comparison in order to support it. */
24286 #define BUILTIN_DESC_SWAP_OPERANDS 1
24288 struct builtin_description
24289 {
24296 };
24299 {
24300 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
24301 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
24302 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
24303 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
24304 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
24305 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
24306 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
24307 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
24308 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
24309 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
24310 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
24311 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
24312 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
24313 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
24314 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
24315 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
24316 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
24317 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
24318 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
24319 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
24320 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
24321 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
24322 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
24323 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
24324 };
24327 {
24328 /* SSE4.2 */
24329 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
24330 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
24331 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
24332 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
24333 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
24334 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
24335 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
24336 };
24339 {
24340 /* SSE4.2 */
24341 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
24342 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
24343 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
24344 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
24345 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
24346 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
24347 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
24348 };
24350 /* Special builtins with variable number of arguments. */
24352 {
24353 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtsc, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
24354 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtscp, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
24356 /* MMX */
24357 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
24359 /* 3DNow! */
24360 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
24362 /* SSE */
24363 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
24364 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
24365 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
24367 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
24368 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
24369 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
24370 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
24372 /* SSE or 3DNow!A */
24373 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
24374 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
24376 /* SSE2 */
24377 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
24378 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
24379 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
24380 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
24381 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
24382 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
24383 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
24384 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
24385 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
24387 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
24388 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
24390 /* SSE3 */
24391 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
24393 /* SSE4.1 */
24394 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
24396 /* SSE4A */
24397 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
24398 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
24400 /* AVX */
24401 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
24402 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
24404 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
24405 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
24406 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
24407 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
24408 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
24410 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
24411 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
24412 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
24413 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
24414 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
24415 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
24416 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
24418 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
24419 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
24420 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
24422 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
24423 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
24424 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
24425 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
24426 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
24427 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
24428 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
24429 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
24431 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
24432 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
24433 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
24434 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
24435 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
24436 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
24438 /* FSGSBASE */
24439 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
24440 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
24441 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
24442 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
24443 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
24444 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
24445 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
24446 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
24447 };
24449 /* Builtins with variable number of arguments. */
24451 {
24452 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
24453 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
24454 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdpmc, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
24455 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
24456 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
24457 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
24458 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
24460 /* MMX */
24461 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24462 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24463 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24464 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24465 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24466 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24468 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24469 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24470 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24471 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24472 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24473 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24474 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24475 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24477 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24478 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24480 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24481 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24482 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24483 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24485 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24486 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24487 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24488 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24489 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24490 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24492 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24493 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24494 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24495 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24496 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
24497 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
24499 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
24500 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
24501 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
24503 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
24505 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
24506 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
24507 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
24508 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
24509 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
24510 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
24512 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
24513 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
24514 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
24515 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
24516 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
24517 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
24519 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
24520 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
24521 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
24522 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
24524 /* 3DNow! */
24525 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
24526 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
24527 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
24528 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
24530 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24531 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24532 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24533 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
24534 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
24535 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
24536 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24537 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24538 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24539 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24540 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24541 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24542 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24543 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24544 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24546 /* 3DNow!A */
24547 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
24548 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
24549 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
24550 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
24551 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24552 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24554 /* SSE */
24555 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
24556 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
24557 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
24558 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
24559 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
24560 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
24561 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
24562 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
24563 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
24564 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
24565 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
24566 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
24568 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
24570 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24571 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24572 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24573 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24574 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24575 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24576 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24577 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24579 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
24580 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
24581 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
24582 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
24583 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
24584 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
24585 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
24586 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
24587 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
24588 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
24589 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
24590 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
24591 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
24592 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
24593 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
24594 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
24595 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
24596 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
24597 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
24598 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
24599 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
24600 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
24602 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24603 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24604 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24605 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24607 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24608 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24609 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24610 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24612 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24614 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24615 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24616 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24617 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24618 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24620 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
24621 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
24622 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
24624 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
24626 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
24627 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
24628 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
24630 /* SSE MMX or 3Dnow!A */
24631 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24632 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24633 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24635 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24636 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24637 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24638 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24640 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
24641 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
24643 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
24645 /* SSE2 */
24646 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
24648 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2df", IX86_BUILTIN_VEC_PERM_V2DF, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI },
24649 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4sf", IX86_BUILTIN_VEC_PERM_V4SF, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI },
24650 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2di", IX86_BUILTIN_VEC_PERM_V2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI },
24651 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4si", IX86_BUILTIN_VEC_PERM_V4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
24652 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8hi", IX86_BUILTIN_VEC_PERM_V8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI },
24653 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v16qi", IX86_BUILTIN_VEC_PERM_V16QI, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
24654 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2di_u", IX86_BUILTIN_VEC_PERM_V2DI_U, UNKNOWN, (int) V2UDI_FTYPE_V2UDI_V2UDI_V2UDI },
24655 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4si_u", IX86_BUILTIN_VEC_PERM_V4SI_U, UNKNOWN, (int) V4USI_FTYPE_V4USI_V4USI_V4USI },
24656 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8hi_u", IX86_BUILTIN_VEC_PERM_V8HI_U, UNKNOWN, (int) V8UHI_FTYPE_V8UHI_V8UHI_V8UHI },
24657 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v16qi_u", IX86_BUILTIN_VEC_PERM_V16QI_U, UNKNOWN, (int) V16UQI_FTYPE_V16UQI_V16UQI_V16UQI },
24658 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4df", IX86_BUILTIN_VEC_PERM_V4DF, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI },
24659 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8sf", IX86_BUILTIN_VEC_PERM_V8SF, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI },
24661 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
24662 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
24663 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
24664 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
24665 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
24666 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtudq2ps, "__builtin_ia32_cvtudq2ps", IX86_BUILTIN_CVTUDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
24668 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
24669 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
24670 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
24671 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
24672 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
24674 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
24676 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
24677 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
24678 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
24679 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
24681 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
24682 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
24683 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
24685 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24686 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24687 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24688 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24689 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24690 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24691 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24692 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24694 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
24695 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
24696 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
24697 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
24698 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
24699 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
24700 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
24701 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
24702 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
24703 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
24704 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
24705 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
24706 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
24707 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
24708 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
24709 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
24710 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
24711 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
24712 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
24713 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
24715 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24716 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24717 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24718 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24720 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24721 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24722 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24723 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24725 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24727 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24728 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24729 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24731 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
24733 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24734 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24735 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
24736 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24737 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24738 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24739 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
24740 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24742 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24743 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24744 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24745 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24746 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24747 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24748 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24749 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24751 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24752 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
24754 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24755 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24756 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24757 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24759 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24760 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24762 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24763 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24764 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
24765 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24766 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24767 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
24769 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24770 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24771 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24772 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24774 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24775 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24776 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
24777 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24778 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24779 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24780 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
24781 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24783 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
24784 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
24785 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
24787 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24788 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
24790 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
24791 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
24793 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
24795 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
24796 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
24797 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
24798 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
24800 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
24801 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
24802 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
24803 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
24804 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
24805 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
24806 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
24808 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
24809 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
24810 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
24811 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
24812 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
24813 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
24814 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
24816 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
24817 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
24818 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
24819 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
24821 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
24822 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
24823 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
24825 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
24827 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
24828 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
24830 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
24832 /* SSE2 MMX */
24833 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
24834 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
24836 /* SSE3 */
24837 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
24838 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
24840 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24841 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24842 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24843 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24844 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24845 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24847 /* SSSE3 */
24848 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
24849 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
24850 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
24851 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
24852 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
24853 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
24855 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24856 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24857 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
24858 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24859 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24860 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24861 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24862 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24863 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
24864 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24865 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24866 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24867 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
24868 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
24869 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24870 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24871 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24872 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24873 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24874 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24875 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24876 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24877 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
24878 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24880 /* SSSE3. */
24881 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
24882 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
24884 /* SSE4.1 */
24885 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
24886 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
24887 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
24888 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
24889 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
24890 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
24891 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
24892 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
24893 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
24894 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
24896 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
24897 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
24898 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
24899 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
24900 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
24901 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
24902 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
24903 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
24904 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
24905 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
24906 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
24907 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
24908 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
24910 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
24911 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24912 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24913 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
24914 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
24915 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24916 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
24917 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
24918 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
24919 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
24920 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
24921 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
24923 /* SSE4.1 */
24924 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
24925 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
24926 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
24927 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
24929 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
24930 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
24931 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
24933 /* SSE4.2 */
24934 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24935 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
24936 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
24937 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
24938 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
24940 /* SSE4A */
24941 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
24942 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
24943 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
24944 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24946 /* AES */
24947 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
24948 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
24950 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24951 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24952 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24953 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
24955 /* PCLMUL */
24956 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
24958 /* AVX */
24959 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
24960 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
24961 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
24962 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
24963 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
24964 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
24965 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
24966 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
24967 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
24968 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
24969 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
24970 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
24971 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
24972 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
24973 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
24974 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
24975 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
24976 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
24977 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
24978 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
24979 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
24980 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
24981 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
24982 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
24983 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
24984 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
24986 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
24987 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
24988 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
24989 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
24991 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
24992 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
24993 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
24994 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
24995 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
24996 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
24997 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
24998 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
24999 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
25000 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
25001 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
25002 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
25003 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
25004 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
25005 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
25006 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
25007 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
25008 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
25009 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
25010 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
25011 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
25012 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
25013 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
25014 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
25015 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
25016 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
25017 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
25018 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
25019 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
25020 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
25021 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
25022 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
25023 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
25024 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
25026 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
25027 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
25028 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
25030 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
25031 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
25032 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
25033 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
25034 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
25036 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
25038 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
25039 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
25041 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25042 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25043 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25044 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25046 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
25047 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
25048 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
25049 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
25050 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
25051 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
25053 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
25054 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
25055 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
25056 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
25057 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
25058 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
25059 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
25060 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
25061 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
25062 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
25063 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
25064 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
25065 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
25066 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
25067 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
25069 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
25070 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
25072 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25073 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25075 { OPTION_MASK_ISA_ABM, CODE_FOR_clzhi2_abm, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
25077 /* BMI */
25078 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
25079 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
25080 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
25082 /* TBM */
25083 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
25084 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
25086 /* F16C */
25087 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
25088 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
25089 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
25090 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
25091 };
25093 /* FMA4 and XOP. */
25094 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
25095 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
25096 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
25097 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
25098 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
25099 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
25100 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
25101 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
25102 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
25103 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
25104 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
25105 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
25106 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
25107 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
25108 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
25109 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
25110 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
25111 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
25112 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
25113 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
25114 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
25115 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
25116 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
25117 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
25118 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
25119 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
25120 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
25121 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
25122 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
25123 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
25124 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
25125 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
25126 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
25127 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
25128 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
25129 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
25130 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
25131 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
25132 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
25133 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
25134 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
25135 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
25136 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
25137 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
25138 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
25139 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
25140 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
25141 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
25142 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
25143 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
25144 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
25145 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
25148 {
25182 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
25183 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
25184 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
25185 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
25186 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
25187 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
25188 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
25190 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
25191 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
25192 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
25193 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
25194 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
25195 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
25196 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
25198 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
25200 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
25201 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
25202 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
25203 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
25204 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
25205 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
25206 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
25207 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
25208 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
25209 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
25210 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
25211 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
25213 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
25214 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
25215 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
25216 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
25217 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
25218 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
25219 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
25220 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
25221 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
25222 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
25223 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
25224 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
25225 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
25226 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
25227 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
25228 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
25230 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
25231 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
25232 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
25233 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
25234 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
25235 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
25237 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
25238 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
25239 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
25240 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
25241 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
25242 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
25243 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
25244 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
25245 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
25246 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
25247 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
25248 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
25249 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
25250 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
25251 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
25253 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
25254 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
25255 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
25256 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
25257 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
25258 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
25259 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
25261 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
25262 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
25263 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
25264 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
25265 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
25266 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
25267 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
25269 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
25270 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
25271 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
25272 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
25273 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
25274 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
25275 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
25277 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
25278 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
25279 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
25280 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
25281 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
25282 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
25283 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
25285 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
25286 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
25287 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
25288 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
25289 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
25290 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
25291 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
25293 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
25294 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
25295 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
25296 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
25297 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
25298 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
25299 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
25301 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
25302 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
25303 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
25304 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
25305 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
25306 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
25307 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
25309 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
25310 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
25311 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
25312 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
25313 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
25314 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
25315 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
25317 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
25318 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
25319 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
25320 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
25321 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
25322 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
25323 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
25324 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
25326 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
25327 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
25328 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
25329 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
25330 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
25331 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
25332 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
25333 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
25335 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
25336 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
25337 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
25338 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
25340 };
25342 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
25343 in the current target ISA to allow the user to compile particular modules
25344 with different target specific options that differ from the command line
25345 options. */
25346 static void
25348 {
25353 /* Add all special builtins with variable number of operands. */
25357 {
25363 }
25365 /* Add all builtins with variable number of operands. */
25369 {
25375 }
25377 /* pcmpestr[im] insns. */
25381 {
25384 else
25387 }
25389 /* pcmpistr[im] insns. */
25393 {
25396 else
25399 }
25401 /* comi/ucomi insns. */
25403 {
25406 else
25409 }
25411 /* SSE */
25417 /* SSE or 3DNow!A */
25420 IX86_BUILTIN_MASKMOVQ);
25422 /* SSE2 */
25431 /* SSE3. */
25437 /* AES */
25451 /* PCLMUL */
25455 /* RDRND */
25462 IX86_BUILTIN_RDRAND64_STEP);
25464 /* MMX access to the vec_init patterns. */
25469 V4HI_FTYPE_HI_HI_HI_HI,
25470 IX86_BUILTIN_VEC_INIT_V4HI);
25473 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
25474 IX86_BUILTIN_VEC_INIT_V8QI);
25476 /* Access to the vec_extract patterns. */
25498 /* Access to the vec_set patterns. */
25519 /* Add FMA4 multi-arg argument instructions */
25521 {
25527 }
25528 }
25530 /* Internal method for ix86_init_builtins. */
25532 static void
25534 {
25546 sysv_va_ref =
25549 fnvoid_va_end_ms =
25551 fnvoid_va_start_ms =
25553 fnvoid_va_end_sysv =
25555 fnvoid_va_start_sysv =
25557 NULL_TREE);
25558 fnvoid_va_copy_ms =
25560 NULL_TREE);
25561 fnvoid_va_copy_sysv =
25577 }
25579 static void
25581 {
25584 /* The __float80 type. */
25587 {
25588 /* The __float80 type. */
25593 }
25596 /* The __float128 type. */
25602 /* This macro is built by i386-builtin-types.awk. */
25603 DEFINE_BUILTIN_PRIMITIVE_TYPES;
25604 }
25606 static void
25608 {
25609 tree t;
25613 /* TFmode support builtins. */
25619 /* We will expand them to normal call if SSE2 isn't available since
25620 they are used by libgcc. */
25638 #ifdef SUBTARGET_INIT_BUILTINS
25639 SUBTARGET_INIT_BUILTINS;
25640 #endif
25641 }
25643 /* Return the ix86 builtin for CODE. */
25645 static tree
25647 {
25652 }
25654 /* Errors in the source file can cause expand_expr to return const0_rtx
25655 where we expect a vector. To avoid crashing, use one of the vector
25656 clear instructions. */
25657 static rtx
25659 {
25663 }
25665 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
25667 static rtx
25669 {
25670 rtx pat;
25690 {
25694 }
25708 }
25710 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
25712 static rtx
25716 {
25717 rtx pat;
25725 rtx op;
25732 {
25812 }
25822 {
25829 {
25831 {
25834 }
25835 }
25836 else
25837 {
25841 /* If we aren't optimizing, only allow one memory operand to be
25842 generated. */
25844 num_memory++;
25852 }
25856 }
25859 {
25870 else
25871 {
25877 }
25890 }
25897 }
25899 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
25900 insns with vec_merge. */
25902 static rtx
25904 rtx target)
25905 {
25906 rtx pat;
25933 }
25935 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
25937 static rtx
25940 {
25941 rtx pat;
25946 rtx op2;
25957 /* Swap operands if we have a comparison that isn't available in
25958 hardware. */
25960 {
25965 }
25985 }
25987 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
25989 static rtx
25991 rtx target)
25992 {
25993 rtx pat;
26007 /* Swap operands if we have a comparison that isn't available in
26008 hardware. */
26010 {
26014 }
26035 const0_rtx)));
26038 }
26040 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
26042 static rtx
26044 rtx target)
26045 {
26046 rtx pat;
26079 const0_rtx)));
26082 }
26084 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
26086 static rtx
26089 {
26090 rtx pat;
26128 {
26131 }
26134 {
26143 }
26145 {
26154 }
26155 else
26156 {
26163 }
26171 {
26176 emit_insn
26180 FLAGS_REG),
26181 const0_rtx)));
26183 }
26184 else
26186 }
26189 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
26191 static rtx
26194 {
26195 rtx pat;
26223 {
26226 }
26229 {
26238 }
26240 {
26249 }
26250 else
26251 {
26258 }
26266 {
26271 emit_insn
26275 FLAGS_REG),
26276 const0_rtx)));
26278 }
26279 else
26281 }
26283 /* Subroutine of ix86_expand_builtin to take care of insns with
26284 variable number of operands. */
26286 static rtx
26289 {
26294 struct
26295 {
26296 rtx op;
26308 {
26523 }
26528 {
26531 }
26534 {
26541 }
26542 else
26543 {
26546 }
26549 {
26556 {
26557 /* SIMD shift insns take either an 8-bit immediate or
26558 register as count. But builtin functions take int as
26559 count. If count doesn't match, we put it in register. */
26561 {
26565 }
26566 }
26568 {
26571 {
26613 {
26616 {
26619 }
26625 }
26627 }
26628 }
26629 else
26630 {
26634 /* If we aren't optimizing, only allow one memory operand to
26635 be generated. */
26637 num_memory++;
26640 {
26643 }
26644 else
26645 {
26648 }
26649 }
26653 }
26656 {
26673 }
26680 }
26682 /* Subroutine of ix86_expand_builtin to take care of special insns
26683 with variable number of operands. */
26685 static rtx
26688 {
26689 tree arg;
26692 struct
26693 {
26694 rtx op;
26704 {
26751 /* Reserve memory operand for target. */
26774 /* Reserve memory operand for target. */
26788 }
26793 {
26799 else
26802 }
26803 else
26804 {
26811 }
26814 {
26823 {
26825 {
26831 else
26834 }
26835 }
26836 else
26837 {
26839 {
26840 /* This must be the memory operand. */
26844 }
26845 else
26846 {
26847 /* This must be register. */
26854 }
26855 }
26859 }
26862 {
26877 }
26883 }
26885 /* Return the integer constant in ARG. Constrain it to be in the range
26886 of the subparts of VEC_TYPE; issue an error if not. */
26888 static int
26890 {
26895 {
26898 }
26901 }
26903 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
26904 ix86_expand_vector_init. We DO have language-level syntax for this, in
26905 the form of (type){ init-list }. Except that since we can't place emms
26906 instructions from inside the compiler, we can't allow the use of MMX
26907 registers unless the user explicitly asks for it. So we do *not* define
26908 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
26909 we have builtins invoked by mmintrin.h that gives us license to emit
26910 these sorts of instructions. */
26912 static rtx
26914 {
26924 {
26927 }
26934 }
26936 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
26937 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
26938 had a language-level syntax for referencing vector elements. */
26940 static rtx
26942 {
26946 rtx op0;
26966 }
26968 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
26969 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
26970 a language-level syntax for referencing vector elements. */
26972 static rtx
26974 {
26998 /* OP0 is the source of these builtin functions and shouldn't be
26999 modified. Create a copy, use it and return it as target. */
27005 }
27007 /* Expand an expression EXP that calls a built-in function,
27008 with result going to TARGET if that's convenient
27009 (and in mode MODE if that's convenient).
27010 SUBTARGET may be used as the target for computing one of EXP's operands.
27011 IGNORE is nonzero if the value is to be ignored. */
27013 static rtx
27017 {
27027 /* Determine whether the builtin function is available under the current ISA.
27028 Originally the builtin was not created if it wasn't applicable to the
27029 current ISA based on the command line switches. With function specific
27030 options, we need to check in the context of the function making the call
27031 whether it is supported. */
27034 {
27040 else
27041 {
27045 }
27047 }
27050 {
27054 ? CODE_FOR_mmx_maskmovq
27056 /* Note the arg order is different from the operand order. */
27171 {
27172 REAL_VALUE_TYPE inf;
27173 rtx tmp;
27185 }
27211 ? CODE_FOR_tbm_bextri_si
27214 {
27217 }
27218 else
27219 {
27228 }
27244 rdrand_step:
27251 /* Emit SImode conditional move. */
27253 {
27256 }
27259 else
27263 const0_rtx);
27277 }
27290 {
27294 /* Emit a normal call if SSE2 isn't available. */
27298 }
27323 }
27325 /* Returns a function decl for a vectorized version of the builtin function
27326 with builtin function code FN and the result vector type TYPE, or NULL_TREE
27327 if it is not available. */
27329 static tree
27331 tree type_in)
27332 {
27348 {
27351 {
27356 }
27361 {
27366 }
27377 {
27382 }
27387 {
27392 }
27397 {
27402 }
27407 {
27412 }
27417 {
27422 }
27427 }
27429 /* Dispatch to a handler for a vectorization library. */
27432 type_in);
27435 }
27437 /* Handler for an SVML-style interface to
27438 a library with vectorized intrinsics. */
27440 static tree
27442 {
27450 /* The SVML is suitable for unsafe math only. */
27463 {
27510 }
27519 {
27522 }
27523 else
27526 /* Convert to uppercase. */
27532 arity++;
27536 else
27539 /* Build a function declaration for the vectorized function. */
27548 }
27550 /* Handler for an ACML-style interface to
27551 a library with vectorized intrinsics. */
27553 static tree
27555 {
27563 /* The ACML is 64bits only and suitable for unsafe math only as
27564 it does not correctly support parts of IEEE with the required
27565 precision such as denormals. */
27579 {
27609 }
27617 arity++;
27621 else
27624 /* Build a function declaration for the vectorized function. */
27633 }
27636 /* Returns a decl of a function that implements conversion of an integer vector
27637 into a floating-point vector, or vice-versa. DEST_TYPE and SRC_TYPE
27638 are the types involved when converting according to CODE.
27639 Return NULL_TREE if it is not available. */
27641 static tree
27644 {
27649 {
27652 {
27655 {
27662 ? NULL_TREE
27666 }
27670 {
27673 ? NULL_TREE
27677 }
27681 }
27685 {
27688 {
27691 ? NULL_TREE
27695 ? NULL_TREE
27699 }
27704 {
27707 ? NULL_TREE
27711 }
27716 }
27720 }
27723 }
27725 /* Returns a code for a target-specific builtin that implements
27726 reciprocal of the function, or NULL_TREE if not available. */
27728 static tree
27731 {
27738 /* Machine dependent builtins. */
27740 {
27741 /* Vectorized version of sqrt to rsqrt conversion. */
27750 }
27751 else
27752 /* Normal builtins. */
27754 {
27755 /* Sqrt to rsqrt conversion. */
27761 }
27762 }
27763 \f
27764 /* Helper for avx_vpermilps256_operand et al. This is also used by
27765 the expansion functions to turn the parallel back into a mask.
27766 The return value is 0 for no match and the imm8+1 for a match. */
27768 int
27770 {
27778 /* Validate that all of the elements are constants, and not totally
27779 out of range. Copy the data into an integral array to make the
27780 subsequent checks easier. */
27782 {
27792 }
27795 {
27797 /* In the 256-bit DFmode case, we can only move elements within
27798 a 128-bit lane. */
27800 {
27804 }
27806 {
27810 }
27814 /* In the 256-bit SFmode case, we have full freedom of movement
27815 within the low 128-bit lane, but the high 128-bit lane must
27816 mirror the exact same pattern. */
27821 /* FALLTHRU */
27825 /* In the 128-bit case, we've full freedom in the placement of
27826 the elements from the source operand. */
27833 }
27835 /* Make sure success has a non-zero value by adding one. */
27837 }
27839 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
27840 the expansion functions to turn the parallel back into a mask.
27841 The return value is 0 for no match and the imm8+1 for a match. */
27843 int
27845 {
27853 /* Validate that all of the elements are constants, and not totally
27854 out of range. Copy the data into an integral array to make the
27855 subsequent checks easier. */
27857 {
27867 }
27869 /* Validate that the halves of the permute are halves. */
27877 /* Reconstruct the mask. */
27879 {
27885 }
27887 /* Make sure success has a non-zero value by adding one. */
27889 }
27890 \f
27892 /* Store OPERAND to the memory after reload is completed. This means
27893 that we can't easily use assign_stack_local. */
27894 rtx
27896 {
27897 rtx result;
27901 {
27904 stack_pointer_rtx,
27907 }
27909 {
27911 {
27915 /* FALLTHRU */
27921 stack_pointer_rtx)),
27922 operand));
27926 }
27928 }
27929 else
27930 {
27932 {
27934 {
27941 stack_pointer_rtx)),
27947 stack_pointer_rtx)),
27949 }
27952 /* Store HImodes as SImodes. */
27954 /* FALLTHRU */
27960 stack_pointer_rtx)),
27961 operand));
27965 }
27967 }
27969 }
27971 /* Free operand from the memory. */
27972 void
27974 {
27976 {
27981 else
27983 /* Use LEA to deallocate stack space. In peephole2 it will be converted
27984 to pop or add instruction if registers are available. */
27988 }
27989 }
27991 /* Implement TARGET_IRA_COVER_CLASSES. If -mfpmath=sse, we prefer
27992 SSE_REGS to FLOAT_REGS if their costs for a pseudo are the
27993 same. */
27996 {
27999 };
28002 };
28005 }
28007 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
28009 Put float CONST_DOUBLE in the constant pool instead of fp regs.
28010 QImode must go into class Q_REGS.
28011 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
28012 movdf to do mem-to-mem moves through integer regs. */
28014 static reg_class_t
28016 {
28019 /* We're only allowed to return a subclass of CLASS. Many of the
28020 following checks fail for NO_REGS, so eliminate that early. */
28024 /* All classes can load zeros. */
28028 /* Force constants into memory if we are loading a (nonzero) constant into
28029 an MMX or SSE register. This is because there are no MMX/SSE instructions
28030 to load from a constant. */
28035 /* Prefer SSE regs only, if we can use them for math. */
28039 /* Floating-point constants need more complex checks. */
28041 {
28042 /* General regs can load everything. */
28046 /* Floats can load 0 and 1 plus some others. Note that we eliminated
28047 zero above. We only want to wind up preferring 80387 registers if
28048 we plan on doing computation with them. */
28051 {
28052 /* Limit class to non-sse. */
28061 }
28064 }
28066 /* Generally when we see PLUS here, it's the function invariant
28067 (plus soft-fp const_int). Which can only be computed into general
28068 regs. */
28072 /* QImode constants are easy to load, but non-constant QImode data
28073 must go into Q_REGS. */
28075 {
28081 }
28084 }
28086 /* Discourage putting floating-point values in SSE registers unless
28087 SSE math is being used, and likewise for the 387 registers. */
28088 static reg_class_t
28090 {
28093 /* Restrict the output reload class to the register bank that we are doing
28094 math on. If we would like not to return a subset of CLASS, reject this
28095 alternative: if reload cannot do this, it will still use its choice. */
28101 {
28106 else
28108 }
28111 }
28113 static reg_class_t
28117 {
28118 /* QImode spills from non-QI registers require
28119 intermediate register on 32bit targets. */
28124 {
28129 else
28135 /* Return Q_REGS if the operand is in memory. */
28138 }
28141 }
28143 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
28145 static bool
28147 {
28149 {
28164 }
28167 }
28169 /* If we are copying between general and FP registers, we need a memory
28170 location. The same is true for SSE and MMX registers.
28172 To optimize register_move_cost performance, allow inline variant.
28174 The macro can't work reliably when one of the CLASSES is class containing
28175 registers from multiple units (SSE, MMX, integer). We avoid this by never
28176 combining those units in single alternative in the machine description.
28177 Ensure that this constraint holds to avoid unexpected surprises.
28179 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
28180 enforce these sanity checks. */
28185 {
28192 {
28195 }
28200 /* ??? This is a lie. We do have moves between mmx/general, and for
28201 mmx/sse2. But by saying we need secondary memory we discourage the
28202 register allocator from using the mmx registers unless needed. */
28207 {
28208 /* SSE1 doesn't have any direct moves from other classes. */
28212 /* If the target says that inter-unit moves are more expensive
28213 than moving through memory, then don't generate them. */
28217 /* Between SSE and general, we have moves no larger than word size. */
28220 }
28223 }
28225 bool
28228 {
28230 }
28232 /* Return true if the registers in CLASS cannot represent the change from
28233 modes FROM to TO. */
28235 bool
28238 {
28242 /* x87 registers can't do subreg at all, as all values are reformatted
28243 to extended precision. */
28248 {
28249 /* Vector registers do not support QI or HImode loads. If we don't
28250 disallow a change to these modes, reload will assume it's ok to
28251 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
28252 the vec_dupv4hi pattern. */
28256 /* Vector registers do not support subreg with nonzero offsets, which
28257 are otherwise valid for integer registers. Since we can't see
28258 whether we have a nonzero offset from here, prohibit all
28259 nonparadoxical subregs changing size. */
28262 }
28265 }
28267 /* Return the cost of moving data of mode M between a
28268 register and memory. A value of 2 is the default; this cost is
28269 relative to those in `REGISTER_MOVE_COST'.
28271 This function is used extensively by register_move_cost that is used to
28272 build tables at startup. Make it inline in this case.
28273 When IN is 2, return maximum of in and out move cost.
28275 If moving between registers and memory is more expensive than
28276 between two registers, you should define this macro to express the
28277 relative cost.
28279 Model also increased moving costs of QImode registers in non
28280 Q_REGS classes.
28281 */
28285 {
28288 {
28291 {
28303 }
28307 }
28309 {
28312 {
28324 }
28328 }
28330 {
28333 {
28342 }
28346 }
28348 {
28351 {
28357 else
28362 }
28363 else
28364 {
28369 else
28371 }
28378 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
28385 else
28389 }
28390 }
28392 static int
28395 {
28397 }
28400 /* Return the cost of moving data from a register in class CLASS1 to
28401 one in class CLASS2.
28403 It is not required that the cost always equal 2 when FROM is the same as TO;
28404 on some machines it is expensive to move between registers if they are not
28405 general registers. */
28407 static int
28409 reg_class_t class2_i)
28410 {
28414 /* In case we require secondary memory, compute cost of the store followed
28415 by load. In order to avoid bad register allocation choices, we need
28416 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
28419 {
28425 /* In case of copying from general_purpose_register we may emit multiple
28426 stores followed by single load causing memory size mismatch stall.
28427 Count this as arbitrarily high cost of 20. */
28431 /* In the case of FP/MMX moves, the registers actually overlap, and we
28432 have to switch modes in order to treat them differently. */
28438 }
28440 /* Moves between SSE/MMX and integer unit are expensive. */
28444 /* ??? By keeping returned value relatively high, we limit the number
28445 of moves between integer and MMX/SSE registers for all targets.
28446 Additionally, high value prevents problem with x86_modes_tieable_p(),
28447 where integer modes in MMX/SSE registers are not tieable
28448 because of missing QImode and HImode moves to, from or between
28449 MMX/SSE registers. */
28459 }
28461 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
28463 bool
28465 {
28466 /* Flags and only flags can only hold CCmode values. */
28476 {
28477 /* We implement the move patterns for all vector modes into and
28478 out of SSE registers, even when no operation instructions
28479 are available. OImode move is available only when AVX is
28480 enabled. */
28487 }
28489 {
28490 /* We implement the move patterns for 3DNOW modes even in MMX mode,
28491 so if the register is available at all, then we can move data of
28492 the given mode into or out of it. */
28495 }
28498 {
28499 /* Take care for QImode values - they can be in non-QI regs,
28500 but then they do cause partial register stalls. */
28506 }
28507 /* We handle both integer and floats in the general purpose registers. */
28514 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
28515 on to use that value in smaller contexts, this can easily force a
28516 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
28517 supporting DImode, allow it. */
28522 }
28524 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
28525 tieable integer mode. */
28527 static bool
28529 {
28531 {
28544 }
28545 }
28547 /* Return true if MODE1 is accessible in a register that can hold MODE2
28548 without copying. That is, all register classes that can hold MODE2
28549 can also hold MODE1. */
28551 bool
28553 {
28561 /* MODE2 being XFmode implies fp stack or general regs, which means we
28562 can tie any smaller floating point modes to it. Note that we do not
28563 tie this with TFmode. */
28567 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
28568 that we can tie it with SFmode. */
28572 /* If MODE2 is only appropriate for an SSE register, then tie with
28573 any other mode acceptable to SSE registers. */
28579 /* If MODE2 is appropriate for an MMX register, then tie
28580 with any other mode acceptable to MMX registers. */
28587 }
28589 /* Compute a (partial) cost for rtx X. Return true if the complete
28590 cost has been computed, and false if subexpressions should be
28591 scanned. In either case, *TOTAL contains the cost result. */
28593 static bool
28595 {
28601 {
28611 && (!TARGET_64BIT
28616 else
28623 else
28625 {
28634 /* Start with (MEM (SYMBOL_REF)), since that's where
28635 it'll probably end up. Add a penalty for size. */
28640 }
28644 /* The zero extensions is often completely free on x86_64, so make
28645 it as cheap as possible. */
28651 else
28662 {
28665 {
28668 }
28671 {
28674 }
28675 }
28676 /* FALLTHRU */
28683 {
28685 {
28688 else
28690 }
28691 else
28692 {
28695 else
28697 }
28698 }
28699 else
28700 {
28703 else
28705 }
28709 {
28710 rtx sub;
28715 /* ??? SSE scalar/vector cost should be used here. */
28716 /* ??? Bald assumption that fma has the same cost as fmul. */
28720 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
28731 }
28735 {
28736 /* ??? SSE scalar cost should be used here. */
28739 }
28741 {
28744 }
28746 {
28747 /* ??? SSE vector cost should be used here. */
28750 }
28751 else
28752 {
28757 {
28760 nbits++;
28761 }
28762 else
28763 /* This is arbitrary. */
28766 /* Compute costs correctly for widening multiplication. */
28770 {
28777 {
28781 else
28783 }
28787 }
28794 }
28801 /* ??? SSE cost should be used here. */
28806 /* ??? SSE vector cost should be used here. */
28808 else
28815 {
28820 {
28823 {
28830 }
28831 }
28834 {
28837 {
28842 }
28843 }
28845 {
28851 }
28852 }
28853 /* FALLTHRU */
28857 {
28858 /* ??? SSE cost should be used here. */
28861 }
28863 {
28866 }
28868 {
28869 /* ??? SSE vector cost should be used here. */
28872 }
28873 /* FALLTHRU */
28879 {
28886 }
28887 /* FALLTHRU */
28891 {
28892 /* ??? SSE cost should be used here. */
28895 }
28897 {
28900 }
28902 {
28903 /* ??? SSE vector cost should be used here. */
28906 }
28907 /* FALLTHRU */
28912 else
28921 {
28922 /* This kind of construct is implemented using test[bwl].
28923 Treat it as if we had an AND. */
28928 }
28938 /* ??? SSE cost should be used here. */
28943 /* ??? SSE vector cost should be used here. */
28949 /* ??? SSE cost should be used here. */
28954 /* ??? SSE vector cost should be used here. */
28967 /* ??? Assume all of these vector manipulation patterns are
28968 recognizable. In which case they all pretty much have the
28969 same cost. */
28975 }
28976 }
28978 #if TARGET_MACHO
28982 /* Given a symbol name and its associated stub, write out the
28983 definition of the stub. */
28985 void
28987 {
28992 /* For 64-bit we shouldn't get here. */
28995 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
29011 {
29014 else
29016 }
29017 else
29024 {
29026 }
29028 {
29029 /* PIC stub. */
29031 {
29032 /* 25-byte PIC stub using "CALL get_pc_thunk". */
29036 }
29037 else
29038 {
29039 /* 26-byte PIC stub using inline picbase: "CALL L42 ! L42: pop %eax". */
29042 }
29044 }
29045 else
29048 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
29049 it needs no stub-binding-helper. */
29056 {
29059 }
29060 else
29065 /* N.B. Keep the correspondence of these
29066 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
29067 old-pic/new-pic/non-pic stubs; altering this will break
29068 compatibility with existing dylibs. */
29070 {
29071 /* PIC stubs. */
29073 /* 25-byte PIC stub using "CALL get_pc_thunk". */
29075 else
29076 /* 26-byte PIC stub using inline picbase: "CALL L42 ! L42: pop %ebx". */
29078 }
29079 else
29080 /* 16-byte -mdynamic-no-pic stub. */
29086 }
29089 /* Order the registers for register allocator. */
29091 void
29093 {
29097 /* First allocate the local general purpose registers. */
29102 /* Global general purpose registers. */
29107 /* x87 registers come first in case we are doing FP math
29108 using them. */
29113 /* SSE registers. */
29119 /* x87 registers. */
29127 /* Initialize the rest of array as we do not allocate some registers
29128 at all. */
29131 }
29133 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
29134 in struct attribute_spec handler. */
29135 static tree
29137 tree args,
29140 {
29145 {
29147 name);
29150 }
29152 {
29154 name);
29157 }
29159 {
29160 tree cst;
29164 {
29167 name);
29169 }
29172 {
29175 name);
29177 }
29180 }
29183 }
29185 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
29186 struct attribute_spec.handler. */
29187 static tree
29189 tree args ATTRIBUTE_UNUSED,
29191 {
29196 {
29198 name);
29201 }
29203 {
29205 name);
29208 }
29210 /* Can combine regparm with all attributes but fastcall. */
29212 {
29214 {
29216 }
29219 }
29221 {
29223 {
29225 }
29228 }
29231 }
29233 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
29234 struct attribute_spec.handler. */
29235 static tree
29237 tree args ATTRIBUTE_UNUSED,
29239 {
29242 {
29245 }
29246 else
29251 {
29253 name);
29255 }
29261 {
29263 name);
29265 }
29268 }
29270 static tree
29272 tree args ATTRIBUTE_UNUSED,
29274 {
29276 {
29278 name);
29280 }
29282 }
29284 static bool
29286 {
29290 }
29292 /* Returns an expression indicating where the this parameter is
29293 located on entry to the FUNCTION. */
29295 static rtx
29297 {
29303 {
29308 else
29311 }
29316 {
29322 {
29327 }
29328 else
29329 {
29332 {
29337 }
29338 }
29340 }
29343 }
29345 /* Determine whether x86_output_mi_thunk can succeed. */
29347 static bool
29349 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
29351 {
29352 /* 64-bit can handle anything. */
29356 /* For 32-bit, everything's fine if we have one free register. */
29360 /* Need a free register for vcall_offset. */
29364 /* Need a free register for GOT references. */
29368 /* Otherwise ok. */
29370 }
29372 /* Output the assembler code for a thunk function. THUNK_DECL is the
29373 declaration for the thunk function itself, FUNCTION is the decl for
29374 the target function. DELTA is an immediate constant offset to be
29375 added to THIS. If VCALL_OFFSET is nonzero, the word at
29376 *(*this + vcall_offset) should be added to THIS. */
29378 static void
29382 {
29387 /* Make sure unwind info is emitted for the thunk if needed. */
29390 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
29391 pull it in now and let DELTA benefit. */
29395 {
29396 /* Put the this parameter into %eax. */
29400 }
29401 else
29404 /* Adjust the this parameter by a fixed constant. */
29406 {
29410 {
29412 {
29418 }
29421 else
29423 }
29426 else
29428 }
29430 /* Adjust the this parameter by a value stored in the vtable. */
29432 {
29435 else
29436 {
29444 }
29450 /* Adjust the this parameter. */
29453 {
29459 }
29462 }
29464 /* If necessary, drop THIS back to its stack slot. */
29466 {
29470 }
29474 {
29478 /* All thunks should be in the same object as their target,
29479 and thus binds_local_p should be true. */
29482 else
29483 {
29489 }
29490 }
29491 else
29492 {
29495 else
29496 #if TARGET_MACHO
29498 {
29501 sym_ref = (gen_rtx_SYMBOL_REF
29507 }
29508 else
29510 {
29517 }
29518 }
29520 }
29522 static void
29524 {
29526 #if TARGET_MACHO
29528 #endif
29535 }
29537 int
29539 {
29551 }
29553 /* Output assembler code to FILE to increment profiler label # LABELNO
29554 for profiling a function entry. */
29555 void
29557 {
29562 {
29563 #ifndef NO_PROFILE_COUNTERS
29565 #endif
29569 else
29571 }
29573 {
29574 #ifndef NO_PROFILE_COUNTERS
29577 #endif
29579 }
29580 else
29581 {
29582 #ifndef NO_PROFILE_COUNTERS
29585 #endif
29587 }
29588 }
29590 /* We don't have exact information about the insn sizes, but we may assume
29591 quite safely that we are informed about all 1 byte insns and memory
29592 address sizes. This is enough to eliminate unnecessary padding in
29593 99% of cases. */
29595 static int
29597 {
29603 /* Discard alignments we've emit and jump instructions. */
29610 /* Important case - calls are always 5 bytes.
29611 It is common to have many calls in the row. */
29620 /* For normal instructions we rely on get_attr_length being exact,
29621 with a few exceptions. */
29623 {
29627 {
29637 /* Otherwise trust get_attr_length. */
29639 }
29644 }
29647 else
29649 }
29651 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
29653 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
29654 window. */
29656 static void
29658 {
29663 /* Look for all minimal intervals of instructions containing 4 jumps.
29664 The intervals are bounded by START and INSN. NBYTES is the total
29665 size of instructions in the interval including INSN and not including
29666 START. When the NBYTES is smaller than 16 bytes, it is possible
29667 that the end of START and INSN ends up in the same 16byte page.
29669 The smallest offset in the page INSN can start is the case where START
29670 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
29671 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
29672 */
29674 {
29678 {
29684 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
29685 already in the current 16 byte page, because otherwise
29686 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
29687 bytes to reach 16 byte boundary. */
29695 {
29697 {
29704 else
29707 }
29708 }
29710 }
29721 njumps++;
29722 else
29726 {
29733 else
29736 }
29743 {
29750 }
29751 }
29752 }
29753 #endif
29755 /* AMD Athlon works faster
29756 when RET is not destination of conditional jump or directly preceded
29757 by other jump instruction. We avoid the penalty by inserting NOP just
29758 before the RET instructions in such cases. */
29759 static void
29761 {
29762 edge e;
29763 edge_iterator ei;
29766 {
29769 rtx prev;
29779 {
29780 edge e;
29781 edge_iterator ei;
29787 }
29789 {
29795 /* Empty functions get branch mispredict even when
29796 the jump destination is not visible to us. */
29799 }
29801 {
29804 }
29805 }
29806 }
29808 /* Count the minimum number of instructions in BB. Return 4 if the
29809 number of instructions >= 4. */
29811 static int
29813 {
29814 rtx insn;
29817 /* Count number of instructions in this block. Return 4 if the number
29818 of instructions >= 4. */
29820 {
29821 /* Only happen in exit blocks. */
29829 {
29830 insn_count++;
29833 }
29834 }
29837 }
29840 /* Count the minimum number of instructions in code path in BB.
29841 Return 4 if the number of instructions >= 4. */
29843 static int
29845 {
29846 edge e;
29847 edge_iterator ei;
29850 /* Only bother counting instructions along paths with no
29851 more than 2 basic blocks between entry and exit. Given
29852 that BB has an edge to exit, determine if a predecessor
29853 of BB has an edge from entry. If so, compute the number
29854 of instructions in the predecessor block. If there
29855 happen to be multiple such blocks, compute the minimum. */
29858 {
29859 edge prev_e;
29860 edge_iterator prev_ei;
29863 {
29866 }
29868 {
29870 {
29875 }
29876 }
29877 }
29883 }
29885 /* Pad short funtion to 4 instructions. */
29887 static void
29889 {
29890 edge e;
29891 edge_iterator ei;
29894 {
29897 {
29900 /* Pad short function. */
29902 {
29905 /* Find epilogue. */
29914 /* Two NOPs count as one instruction. */
29917 }
29918 }
29919 }
29920 }
29922 /* Implement machine specific optimizations. We implement padding of returns
29923 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
29924 static void
29926 {
29927 /* We are freeing block_for_insn in the toplev to keep compatibility
29928 with old MDEP_REORGS that are not CFG based. Recompute it now. */
29932 {
29937 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
29940 #endif
29941 }
29943 /* Run the vzeroupper optimization if needed. */
29946 }
29948 /* Return nonzero when QImode register that must be represented via REX prefix
29949 is used. */
29950 bool
29952 {
29960 }
29962 /* Return nonzero when P points to register encoded via REX prefix.
29963 Called via for_each_rtx. */
29964 static int
29966 {
29972 }
29974 /* Return true when INSN mentions register that must be encoded using REX
29975 prefix. */
29976 bool
29978 {
29981 }
29983 /* If profitable, negate (without causing overflow) integer constant
29984 of mode MODE at location LOC. Return true in this case. */
29985 bool
29987 {
29988 HOST_WIDE_INT val;
29994 {
29996 /* DImode x86_64 constants must fit in 32 bits. */
30009 }
30011 /* Avoid overflows. */
30017 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
30018 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
30021 {
30024 }
30027 }
30029 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
30030 optabs would emit if we didn't have TFmode patterns. */
30032 void
30034 {
30068 }
30069 \f
30070 /* AVX does not support 32-byte integer vector operations,
30071 thus the longest vector we are faced with is V16QImode. */
30072 #define MAX_VECT_LEN 16
30074 struct expand_vec_perm_d
30075 {
30081 };
30086 /* Get a vector mode of the same size as the original but with elements
30087 twice as wide. This is only guaranteed to apply to integral vectors. */
30091 {
30092 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
30097 }
30099 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
30100 with all elements equal to VAR. Return true if successful. */
30102 static bool
30105 {
30109 {
30114 /* FALLTHRU */
30124 {
30127 /* First attempt to recognize VAL as-is. */
30131 {
30132 rtx seq;
30133 /* If that fails, force VAL into a register. */
30144 }
30145 }
30152 {
30153 rtx x;
30160 }
30170 {
30174 permute:
30181 /* Extend to SImode using a paradoxical SUBREG. */
30185 /* Insert the SImode value as low element of a V4SImode vector. */
30193 }
30201 widen:
30202 /* Replicate the value once into the next wider mode and recurse. */
30203 {
30205 rtx x;
30221 }
30225 {
30234 }
30239 }
30240 }
30242 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
30243 whose ONE_VAR element is VAR, and other elements are zero. Return true
30244 if successful. */
30246 static bool
30249 {
30251 rtx new_target;
30256 {
30258 /* For SSE4.1, we normally use vector set. But if the second
30259 element is zero and inter-unit moves are OK, we use movq
30260 instead. */
30261 use_vector_set = (TARGET_64BIT
30262 && TARGET_SSE4_1
30263 && !(TARGET_INTER_UNIT_MOVES
30285 /* Use ix86_expand_vector_set in 64bit mode only. */
30290 }
30293 {
30298 }
30301 {
30306 /* FALLTHRU */
30321 else
30328 {
30329 /* We need to shuffle the value to the correct position, so
30330 create a new pseudo to store the intermediate result. */
30332 /* With SSE2, we can use the integer shuffle insns. */
30334 {
30336 const1_rtx,
30343 }
30345 /* Otherwise convert the intermediate result to V4SFmode and
30346 use the SSE1 shuffle instructions. */
30348 {
30351 }
30352 else
30356 const1_rtx,
30365 }
30380 widen:
30384 /* Zero extend the variable element to SImode and recurse. */
30397 }
30398 }
30400 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
30401 consisting of the values in VALS. It is known that all elements
30402 except ONE_VAR are constants. Return true if successful. */
30404 static bool
30407 {
30417 {
30422 /* For the two element vectors, it's just as easy to use
30423 the general case. */
30427 /* Use ix86_expand_vector_set in 64bit mode only. */
30449 widen:
30450 /* There's no way to set one QImode entry easily. Combine
30451 the variable value with its adjacent constant value, and
30452 promote to an HImode set. */
30455 {
30460 }
30461 else
30462 {
30465 }
30479 }
30484 }
30486 /* A subroutine of ix86_expand_vector_init_general. Use vector
30487 concatenate to handle the most general case: all values variable,
30488 and none identical. */
30490 static void
30493 {
30496 rtvec v;
30500 {
30503 {
30536 }
30549 {
30564 }
30569 {
30580 }
30583 half:
30584 /* FIXME: We process inputs backward to help RA. PR 36222. */
30588 {
30593 }
30597 {
30600 {
30604 }
30607 }
30608 else
30614 }
30615 }
30617 /* A subroutine of ix86_expand_vector_init_general. Use vector
30618 interleave to handle the most general case: all values variable,
30619 and none identical. */
30621 static void
30624 {
30633 {
30654 }
30657 {
30658 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
30662 /* Insert the SImode value as low element of V4SImode vector. */
30666 op0),
30668 const1_rtx);
30671 /* Cast the V4SImode vector back to a vector in orignal mode. */
30675 /* Load even elements into the second positon. */
30679 const1_rtx));
30681 /* Cast vector to FIRST_IMODE vector. */
30684 }
30686 /* Interleave low FIRST_IMODE vectors. */
30688 {
30692 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
30695 }
30697 /* Interleave low SECOND_IMODE vectors. */
30699 {
30702 {
30707 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
30708 vector. */
30711 }
30714 /* FALLTHRU */
30721 /* Cast the SECOND_IMODE vector back to a vector on original
30722 mode. */
30729 }
30730 }
30732 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
30733 all values variable, and none identical. */
30735 static void
30738 {
30744 {
30749 /* FALLTHRU */
30773 half:
30790 /* FALLTHRU */
30796 /* Don't use ix86_expand_vector_init_interleave if we can't
30797 move from GPR to SSE register directly. */
30813 }
30815 {
30827 {
30831 {
30837 else
30838 {
30843 }
30844 }
30847 }
30852 {
30858 }
30860 {
30866 }
30867 else
30869 }
30870 }
30872 /* Initialize vector TARGET via VALS. Suppress the use of MMX
30873 instructions unless MMX_OK is true. */
30875 void
30877 {
30884 rtx x;
30887 {
30897 }
30899 /* Constants are best loaded from the constant pool. */
30901 {
30904 }
30906 /* If all values are identical, broadcast the value. */
30912 /* Values where only one field is non-constant are best loaded from
30913 the pool and overwritten via move later. */
30915 {
30919 one_var))
30924 }
30927 }
30929 void
30931 {
30936 rtx tmp;
30938 = {
30945 };
30947 = {
30954 };
30958 {
30962 {
30967 else
30971 }
30980 {
30983 /* For the two element vectors, we implement a VEC_CONCAT with
30984 the extraction of the other element. */
30991 else
30996 }
31005 {
31011 /* tmp = target = A B C D */
31013 /* target = A A B B */
31015 /* target = X A B B */
31017 /* target = A X C D */
31024 /* tmp = target = A B C D */
31026 /* tmp = X B C D */
31028 /* target = A B X D */
31035 /* tmp = target = A B C D */
31037 /* tmp = X B C D */
31039 /* target = A B X D */
31047 }
31055 /* Element 0 handled by vec_merge below. */
31057 {
31060 }
31063 {
31064 /* With SSE2, use integer shuffles to swap element 0 and ELT,
31065 store into element 0, then shuffle them back. */
31082 }
31083 else
31084 {
31085 /* For SSE1, we have to reuse the V4SF code. */
31088 }
31141 half:
31142 /* Compute offset. */
31148 /* Extract the half. */
31152 /* Put val in tmp at elt. */
31155 /* Put it back. */
31161 }
31164 {
31168 }
31169 else
31170 {
31179 }
31180 }
31182 void
31184 {
31188 rtx tmp;
31191 {
31196 /* FALLTHRU */
31209 {
31229 }
31241 {
31243 {
31263 }
31267 }
31268 else
31269 {
31270 /* For SSE1, we have to reuse the V4SF code. */
31274 }
31289 /* ??? Could extract the appropriate HImode element and shift. */
31292 }
31295 {
31299 /* Let the rtl optimizers know about the zero extension performed. */
31301 {
31304 }
31307 }
31308 else
31309 {
31316 }
31317 }
31319 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
31320 pattern to reduce; DEST is the destination; IN is the input vector. */
31322 void
31324 {
31338 }
31339 \f
31340 /* Target hook for scalar_mode_supported_p. */
31341 static bool
31343 {
31348 else
31350 }
31352 /* Implements target hook vector_mode_supported_p. */
31353 static bool
31355 {
31367 }
31369 /* Target hook for c_mode_for_suffix. */
31370 static enum machine_mode
31372 {
31379 }
31381 /* Worker function for TARGET_MD_ASM_CLOBBERS.
31383 We do this in the new i386 backend to maintain source compatibility
31384 with the old cc0-based compiler. */
31386 static tree
31388 tree inputs ATTRIBUTE_UNUSED,
31389 tree clobbers)
31390 {
31392 clobbers);
31394 clobbers);
31396 }
31398 /* Implements target vector targetm.asm.encode_section_info. This
31399 is not used by netware. */
31401 static void ATTRIBUTE_UNUSED
31403 {
31410 }
31412 /* Worker function for REVERSE_CONDITION. */
31414 enum rtx_code
31416 {
31420 }
31422 /* Output code to perform an x87 FP register move, from OPERANDS[1]
31423 to OPERANDS[0]. */
31427 {
31429 {
31432 {
31436 }
31440 }
31442 {
31446 else
31447 {
31448 /* There is no non-popping store to memory for XFmode.
31449 So if we need one, follow the store with a load. */
31452 else
31454 }
31455 }
31456 else
31458 }
31460 /* Output code to perform a conditional jump to LABEL, if C2 flag in
31461 FP status register is set. */
31463 void
31465 {
31467 rtx temp;
31472 {
31477 }
31478 else
31479 {
31484 }
31488 pc_rtx);
31493 }
31495 /* Output code to perform a log1p XFmode calculation. */
31498 {
31504 rtx test;
31510 XFmode));
31524 }
31526 /* Output code to perform a Newton-Rhapson approximation of a single precision
31527 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
31530 {
31545 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
31547 /* x0 = rcp(b) estimate */
31550 UNSPEC_RCP)));
31551 /* e0 = x0 * a */
31554 /* e1 = x0 * b */
31557 /* x1 = 2. - e1 */
31560 /* res = e0 * x1 */
31563 }
31565 /* Output code to perform a Newton-Rhapson approximation of a
31566 single precision floating point [reciprocal] square root. */
31570 {
31572 REAL_VALUE_TYPE r;
31587 {
31590 }
31592 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
31593 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
31595 /* x0 = rsqrt(a) estimate */
31598 UNSPEC_RSQRT)));
31600 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
31602 {
31614 }
31616 /* e0 = x0 * a */
31619 /* e1 = e0 * x0 */
31623 /* e2 = e1 - 3. */
31630 /* e3 = -.5 * x0 */
31633 else
31634 /* e3 = -.5 * e0 */
31637 /* ret = e2 * e3 */
31640 }
31642 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
31644 static void ATTRIBUTE_UNUSED
31646 tree decl)
31647 {
31648 /* With Binutils 2.15, the "@unwind" marker must be specified on
31649 every occurrence of the ".eh_frame" section, not just the first
31650 one. */
31653 {
31657 }
31659 }
31661 /* Return the mangling of TYPE if it is an extended fundamental type. */
31665 {
31673 {
31675 /* __float128 is "g". */
31678 /* "long double" or __float80 is "e". */
31682 }
31683 }
31685 /* For 32-bit code we can save PIC register setup by using
31686 __stack_chk_fail_local hidden function instead of calling
31687 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
31688 register, so it is better to call __stack_chk_fail directly. */
31690 static tree
31692 {
31693 return TARGET_64BIT
31696 }
31698 /* Select a format to encode pointers in exception handling data. CODE
31699 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
31700 true if the symbol may be affected by dynamic relocations.
31702 ??? All x86 object file formats are capable of representing this.
31703 After all, the relocation needed is the same as for the call insn.
31704 Whether or not a particular assembler allows us to enter such, I
31705 guess we'll have to see. */
31706 int
31708 {
31710 {
31717 }
31722 }
31723 \f
31724 /* Expand copysign from SIGN to the positive value ABS_VALUE
31725 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
31726 the sign-bit. */
31727 static void
31729 {
31733 {
31740 else
31745 {
31746 /* We need to generate a scalar mode mask in this case. */
31751 }
31752 }
31753 else
31759 }
31761 /* Expand fabs (OP0) and return a new rtx that holds the result. The
31762 mask for masking out the sign-bit is stored in *SMASK, if that is
31763 non-null. */
31764 static rtx
31766 {
31775 else
31779 {
31780 /* We need to generate a scalar mode mask in this case. */
31785 }
31793 }
31795 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
31796 swapping the operands if SWAP_OPERANDS is true. The expanded
31797 code is a forward jump to a newly created label in case the
31798 comparison is true. The generated label rtx is returned. */
31799 static rtx
31802 {
31806 {
31810 }
31823 }
31825 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
31826 using comparison code CODE. Operands are swapped for the comparison if
31827 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
31828 static rtx
31831 {
31836 {
31840 }
31845 else
31850 }
31852 /* Generate and return a rtx of mode MODE for 2**n where n is the number
31853 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
31854 static rtx
31856 {
31857 REAL_VALUE_TYPE TWO52r;
31858 rtx TWO52;
31865 }
31867 /* Expand SSE sequence for computing lround from OP1 storing
31868 into OP0. */
31869 void
31871 {
31872 /* C code for the stuff we're doing below:
31873 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
31874 return (long)tmp;
31875 */
31879 rtx adj;
31881 /* load nextafter (0.5, 0.0) */
31886 /* adj = copysign (0.5, op1) */
31890 /* adj = op1 + adj */
31893 /* op0 = (imode)adj */
31895 }
31897 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
31898 into OPERAND0. */
31899 void
31901 {
31902 /* C code for the stuff we're doing below (for do_floor):
31903 xi = (long)op1;
31904 xi -= (double)xi > op1 ? 1 : 0;
31905 return xi;
31906 */
31911 /* reg = (long)op1 */
31915 /* freg = (double)reg */
31919 /* ireg = (freg > op1) ? ireg - 1 : ireg */
31930 }
31932 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
31933 result in OPERAND0. */
31934 void
31936 {
31937 /* C code for the stuff we're doing below:
31938 xa = fabs (operand1);
31939 if (!isless (xa, 2**52))
31940 return operand1;
31941 xa = xa + 2**52 - 2**52;
31942 return copysign (xa, operand1);
31943 */
31950 /* xa = abs (operand1) */
31953 /* if (!isless (xa, TWO52)) goto label; */
31966 }
31968 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
31969 into OPERAND0. */
31970 void
31972 {
31973 /* C code for the stuff we expand below.
31974 double xa = fabs (x), x2;
31975 if (!isless (xa, TWO52))
31976 return x;
31977 xa = xa + TWO52 - TWO52;
31978 x2 = copysign (xa, x);
31979 Compensate. Floor:
31980 if (x2 > x)
31981 x2 -= 1;
31982 Compensate. Ceil:
31983 if (x2 < x)
31984 x2 -= -1;
31985 return x2;
31986 */
31992 /* Temporary for holding the result, initialized to the input
31993 operand to ease control flow. */
31997 /* xa = abs (operand1) */
32000 /* if (!isless (xa, TWO52)) goto label; */
32003 /* xa = xa + TWO52 - TWO52; */
32007 /* xa = copysign (xa, operand1) */
32010 /* generate 1.0 or -1.0 */
32015 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
32019 /* We always need to subtract here to preserve signed zero. */
32028 }
32030 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
32031 into OPERAND0. */
32032 void
32034 {
32035 /* C code for the stuff we expand below.
32036 double xa = fabs (x), x2;
32037 if (!isless (xa, TWO52))
32038 return x;
32039 x2 = (double)(long)x;
32040 Compensate. Floor:
32041 if (x2 > x)
32042 x2 -= 1;
32043 Compensate. Ceil:
32044 if (x2 < x)
32045 x2 += 1;
32046 if (HONOR_SIGNED_ZEROS (mode))
32047 return copysign (x2, x);
32048 return x2;
32049 */
32055 /* Temporary for holding the result, initialized to the input
32056 operand to ease control flow. */
32060 /* xa = abs (operand1) */
32063 /* if (!isless (xa, TWO52)) goto label; */
32066 /* xa = (double)(long)x */
32071 /* generate 1.0 */
32074 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
32089 }
32091 /* Expand SSE sequence for computing round from OPERAND1 storing
32092 into OPERAND0. Sequence that works without relying on DImode truncation
32093 via cvttsd2siq that is only available on 64bit targets. */
32094 void
32096 {
32097 /* C code for the stuff we expand below.
32098 double xa = fabs (x), xa2, x2;
32099 if (!isless (xa, TWO52))
32100 return x;
32101 Using the absolute value and copying back sign makes
32102 -0.0 -> -0.0 correct.
32103 xa2 = xa + TWO52 - TWO52;
32104 Compensate.
32105 dxa = xa2 - xa;
32106 if (dxa <= -0.5)
32107 xa2 += 1;
32108 else if (dxa > 0.5)
32109 xa2 -= 1;
32110 x2 = copysign (xa2, x);
32111 return x2;
32112 */
32118 /* Temporary for holding the result, initialized to the input
32119 operand to ease control flow. */
32123 /* xa = abs (operand1) */
32126 /* if (!isless (xa, TWO52)) goto label; */
32129 /* xa2 = xa + TWO52 - TWO52; */
32133 /* dxa = xa2 - xa; */
32136 /* generate 0.5, 1.0 and -0.5 */
32142 /* Compensate. */
32144 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
32149 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
32155 /* res = copysign (xa2, operand1) */
32162 }
32164 /* Expand SSE sequence for computing trunc from OPERAND1 storing
32165 into OPERAND0. */
32166 void
32168 {
32169 /* C code for SSE variant we expand below.
32170 double xa = fabs (x), x2;
32171 if (!isless (xa, TWO52))
32172 return x;
32173 x2 = (double)(long)x;
32174 if (HONOR_SIGNED_ZEROS (mode))
32175 return copysign (x2, x);
32176 return x2;
32177 */
32183 /* Temporary for holding the result, initialized to the input
32184 operand to ease control flow. */
32188 /* xa = abs (operand1) */
32191 /* if (!isless (xa, TWO52)) goto label; */
32194 /* x = (double)(long)x */
32206 }
32208 /* Expand SSE sequence for computing trunc from OPERAND1 storing
32209 into OPERAND0. */
32210 void
32212 {
32216 /* C code for SSE variant we expand below.
32217 double xa = fabs (x), x2;
32218 if (!isless (xa, TWO52))
32219 return x;
32220 xa2 = xa + TWO52 - TWO52;
32221 Compensate:
32222 if (xa2 > xa)
32223 xa2 -= 1.0;
32224 x2 = copysign (xa2, x);
32225 return x2;
32226 */
32230 /* Temporary for holding the result, initialized to the input
32231 operand to ease control flow. */
32235 /* xa = abs (operand1) */
32238 /* if (!isless (xa, TWO52)) goto label; */
32241 /* res = xa + TWO52 - TWO52; */
32246 /* generate 1.0 */
32249 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
32257 /* res = copysign (res, operand1) */
32264 }
32266 /* Expand SSE sequence for computing round from OPERAND1 storing
32267 into OPERAND0. */
32268 void
32270 {
32271 /* C code for the stuff we're doing below:
32272 double xa = fabs (x);
32273 if (!isless (xa, TWO52))
32274 return x;
32275 xa = (double)(long)(xa + nextafter (0.5, 0.0));
32276 return copysign (xa, x);
32277 */
32283 /* Temporary for holding the result, initialized to the input
32284 operand to ease control flow. */
32292 /* load nextafter (0.5, 0.0) */
32297 /* xa = xa + 0.5 */
32301 /* xa = (double)(int64_t)xa */
32306 /* res = copysign (xa, operand1) */
32313 }
32314 \f
32316 /* Table of valid machine attributes. */
32318 {
32319 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
32320 /* Stdcall attribute says callee is responsible for popping arguments
32321 if they are not variable. */
32323 /* Fastcall attribute says callee is responsible for popping arguments
32324 if they are not variable. */
32326 /* Thiscall attribute says callee is responsible for popping arguments
32327 if they are not variable. */
32329 /* Cdecl attribute says the callee is a normal C declaration */
32331 /* Regparm attribute specifies how many integer arguments are to be
32332 passed in registers. */
32334 /* Sseregparm attribute says we are using x86_64 calling conventions
32335 for FP arguments. */
32337 /* force_align_arg_pointer says this function realigns the stack at entry. */
32340 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
32344 #endif
32347 #ifdef SUBTARGET_ATTRIBUTE_TABLE
32348 SUBTARGET_ATTRIBUTE_TABLE,
32349 #endif
32350 /* ms_abi and sysv_abi calling convention function attributes. */
32355 ix86_handle_callee_pop_aggregate_return },
32356 /* End element. */
32358 };
32360 /* Implement targetm.vectorize.builtin_vectorization_cost. */
32361 static int
32363 tree vectype ATTRIBUTE_UNUSED,
32365 {
32367 {
32407 }
32408 }
32411 /* Implement targetm.vectorize.builtin_vec_perm. */
32413 static tree
32415 {
32423 {
32430 get_di:
32441 get_si:
32460 }
32467 }
32469 /* Return a vector mode with twice as many elements as VMODE. */
32470 /* ??? Consider moving this to a table generated by genmodes.c. */
32472 static enum machine_mode
32474 {
32476 {
32499 }
32500 }
32502 /* Construct (set target (vec_select op0 (parallel perm))) and
32503 return true if that's a valid instruction in the active ISA. */
32505 static bool
32507 {
32520 {
32523 }
32525 }
32527 /* Similar, but generate a vec_concat from op0 and op1 as well. */
32529 static bool
32532 {
32534 rtx x;
32539 }
32541 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
32542 in terms of blendp[sd] / pblendw / pblendvb. */
32544 static bool
32546 {
32556 /* This is a blend, not a permute. Elements must stay in their
32557 respective lanes. */
32559 {
32563 }
32568 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
32569 decision should be extracted elsewhere, so that we only try that
32570 sequence once all budget==3 options have been tried. */
32572 /* For bytes, see if bytes move in pairs so we can use pblendw with
32573 an immediate argument, rather than pblendvb with a vector argument. */
32575 {
32581 {
32592 }
32593 }
32601 {
32625 do_subreg:
32634 }
32636 /* This matches five different patterns with the different modes. */
32642 }
32644 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
32645 in terms of the variable form of vpermilps.
32647 Note that we will have already failed the immediate input vpermilps,
32648 which requires that the high and low part shuffle be identical; the
32649 variable form doesn't require that. */
32651 static bool
32653 {
32660 /* We can only permute within the 128-bit lane. */
32662 {
32666 }
32672 {
32675 /* Within each 128-bit lane, the elements of op0 are numbered
32676 from 0 and the elements of op1 are numbered from 4. */
32683 }
32690 }
32692 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
32693 in terms of pshufb or vpperm. */
32695 static bool
32697 {
32713 {
32717 }
32726 else
32727 {
32730 }
32733 }
32735 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
32736 in a single instruction. */
32738 static bool
32740 {
32744 /* Check plain VEC_SELECT first, because AVX has instructions that could
32745 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
32746 input where SEL+CONCAT may not. */
32748 {
32757 /* There are plenty of patterns in sse.md that are written for
32758 SEL+CONCAT and are not replicated for a single op. Perhaps
32759 that should be changed, to avoid the nastiness here. */
32761 /* Recognize interleave style patterns, which means incrementing
32762 every other permutation operand. */
32764 {
32767 }
32771 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
32773 {
32775 {
32780 }
32784 }
32785 }
32787 /* Finally, try the fully general two operand permute. */
32791 /* Recognize interleave style patterns with reversed operands. */
32793 {
32795 {
32799 else
32802 }
32806 }
32808 /* Try the SSE4.1 blend variable merge instructions. */
32812 /* Try one of the AVX vpermil variable permutations. */
32816 /* Try the SSSE3 pshufb or XOP vpperm variable permutation. */
32821 }
32823 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
32824 in terms of a pair of pshuflw + pshufhw instructions. */
32826 static bool
32828 {
32836 /* The two permutations only operate in 64-bit lanes. */
32847 /* Emit the pshuflw. */
32854 /* Emit the pshufhw. */
32862 }
32864 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
32865 the permutation using the SSSE3 palignr instruction. This succeeds
32866 when all of the elements in PERM fit within one vector and we merely
32867 need to shift them down so that a single vector permutation has a
32868 chance to succeed. */
32870 static bool
32872 {
32876 rtx shift;
32878 /* Even with AVX, palignr only operates on 128-bit vectors. */
32884 {
32890 }
32894 /* Given that we have SSSE3, we know we'll be able to implement the
32895 single operand permutation after the palignr with pshufb. */
32908 {
32913 }
32915 /* Test for the degenerate case where the alignment by itself
32916 produces the desired permutation. */
32924 }
32926 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
32927 a two vector permutation into a single vector permutation by using
32928 an interleave operation to merge the vectors. */
32930 static bool
32932 {
32937 rtx seq;
32943 /* The 256-bit unpck[lh]p[sd] instructions only operate within the 128-bit
32944 lanes. We can use similar techniques with the vperm2f128 instruction,
32945 but it requires slightly different logic. */
32949 /* Examine from whence the elements come. */
32954 /* Split the two input vectors into 4 halves. */
32963 /* If the elements from the low halves use interleave low, and similarly
32964 for interleave high. If the elements are from mis-matched halves, we
32965 can use shufps for V4SF/V4SI or do a DImode shuffle. */
32967 {
32969 {
32974 }
32975 }
32977 {
32979 {
32984 }
32985 }
32987 {
32989 {
32994 }
32996 {
33001 }
33002 }
33004 {
33006 {
33011 }
33013 {
33018 }
33019 }
33020 else
33023 /* Use the remapping array set up above to move the elements from their
33024 swizzled locations into their final destinations. */
33027 {
33031 }
33036 /* Test if the final remap can be done with a single insn. For V4SFmode or
33037 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
33047 {
33051 }
33058 }
33060 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
33061 permutation with two pshufb insns and an ior. We should have already
33062 failed all two instruction sequences. */
33064 static bool
33066 {
33077 /* Generate two permutation masks. If the required element is within
33078 the given vector it is shuffled into the proper lane. If the required
33079 element is in the other vector, force a zero into the lane by setting
33080 bit 7 in the permutation mask. */
33083 {
33090 {
33093 }
33094 }
33114 }
33116 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
33117 and extract-odd permutations. */
33119 static bool
33121 {
33125 {
33130 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
33134 /* Now an unpck[lh]pd will produce the result required. */
33137 else
33143 {
33150 /* Shuffle within the 128-bit lanes to produce:
33151 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
33155 /* Shuffle the lanes around to produce:
33156 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
33160 /* Shuffle within the 128-bit lanes to produce:
33161 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
33164 /* Shuffle within the 128-bit lanes to produce:
33165 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
33168 /* Shuffle the lanes around to produce:
33169 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
33172 }
33179 /* These are always directly implementable by expand_vec_perm_1. */
33185 else
33186 {
33187 /* We need 2*log2(N)-1 operations to achieve odd/even
33188 with interleave. */
33197 else
33200 }
33206 else
33207 {
33219 else
33222 }
33227 }
33230 }
33232 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
33233 extract-even and extract-odd permutations. */
33235 static bool
33237 {
33249 }
33251 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
33252 permutations. We assume that expand_vec_perm_1 has already failed. */
33254 static bool
33256 {
33264 {
33267 /* These are special-cased in sse.md so that we can optionally
33268 use the vbroadcast instruction. They expand to two insns
33269 if the input happens to be in a register. */
33276 /* These are always implementable using standard shuffle patterns. */
33281 /* These can be implemented via interleave. We save one insn by
33282 stopping once we have promoted to V4SImode and then use pshufd. */
33283 do
33284 {
33288 {
33291 }
33297 }
33307 }
33308 }
33310 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
33311 broadcast permutations. */
33313 static bool
33315 {
33327 }
33329 /* The guts of ix86_expand_vec_perm_builtin, also used by the ok hook.
33330 With all of the interface bits taken care of, perform the expansion
33331 in D and return true on success. */
33333 static bool
33335 {
33336 /* Try a single instruction expansion. */
33340 /* Try sequences of two instructions. */
33354 /* Try sequences of three instructions. */
33359 /* ??? Look for narrow permutations whose element orderings would
33360 allow the promotion to a wider mode. */
33362 /* ??? Look for sequences of interleave or a wider permute that place
33363 the data into the correct lanes for a half-vector shuffle like
33364 pshuf[lh]w or vpermilps. */
33366 /* ??? Look for sequences of interleave that produce the desired results.
33367 The combinatorics of punpck[lh] get pretty ugly... */
33373 }
33375 /* Extract the values from the vector CST into the permutation array in D.
33376 Return 0 on error, 1 if all values from the permutation come from the
33377 first vector, 2 if all values from the second vector, and 3 otherwise. */
33379 static int
33381 {
33387 {
33398 }
33401 /* For all elements from second vector, fold the elements to first. */
33407 }
33409 static rtx
33411 {
33425 {
33429 }
33432 {
33442 {
33448 }
33450 /* The elements of PERM do not suggest that only the first operand
33451 is used, but both operands are identical. Allow easier matching
33452 of the permutation by folding the permutation into the single
33453 input vector. */
33454 {
33459 }
33460 /* FALLTHRU */
33473 }
33479 /* For compiler generated permutations, we should never got here, because
33480 the compiler should also be checking the ok hook. But since this is a
33481 builtin the user has access too, so don't abort. */
33483 {
33506 }
33507 exit_error:
33509 }
33511 /* Implement targetm.vectorize.builtin_vec_perm_ok. */
33513 static bool
33515 {
33524 /* Given sufficient ISA support we can just return true here
33525 for selected vector modes. */
33527 {
33528 /* All implementable with a single vpperm insn. */
33531 /* All implementable with 2 pshufb + 1 ior. */
33534 /* All implementable with shufpd or unpck[lh]pd. */
33537 }
33541 /* This hook is cannot be called in response to something that the
33542 user does (unlike the builtin expander) so we shouldn't ever see
33543 an error generated from the extract. */
33547 /* Implementable with shufps or pshufd. */
33551 /* Otherwise we have to go through the motions and see if we can
33552 figure out how to generate the requested permutation. */
33563 }
33565 void
33567 {
33581 /* We'll either be able to implement the permutation directly... */
33585 /* ... or we use the special-case patterns. */
33587 }
33588 \f
33589 /* This function returns the calling abi specific va_list type node.
33590 It returns the FNDECL specific va_list type. */
33592 static tree
33594 {
33601 else
33603 }
33605 /* Returns the canonical va_list type specified by TYPE. If there
33606 is no valid TYPE provided, it return NULL_TREE. */
33608 static tree
33610 {
33613 /* Resolve references and pointers to va_list type. */
33622 {
33627 {
33628 /* If va_list is an array type, the argument may have decayed
33629 to a pointer type, e.g. by being passed to another function.
33630 In that case, unwrap both types so that we can compare the
33631 underlying records. */
33634 {
33637 }
33638 }
33645 {
33646 /* If va_list is an array type, the argument may have decayed
33647 to a pointer type, e.g. by being passed to another function.
33648 In that case, unwrap both types so that we can compare the
33649 underlying records. */
33652 {
33655 }
33656 }
33663 {
33664 /* If va_list is an array type, the argument may have decayed
33665 to a pointer type, e.g. by being passed to another function.
33666 In that case, unwrap both types so that we can compare the
33667 underlying records. */
33670 {
33673 }
33674 }
33678 }
33680 }
33682 /* Iterate through the target-specific builtin types for va_list.
33683 IDX denotes the iterator, *PTREE is set to the result type of
33684 the va_list builtin, and *PNAME to its internal type.
33685 Returns zero if there is no element for this index, otherwise
33686 IDX should be increased upon the next call.
33687 Note, do not iterate a base builtin's name like __builtin_va_list.
33688 Used from c_common_nodes_and_builtins. */
33690 static int
33692 {
33694 {
33696 {
33709 }
33710 }
33713 }
33715 #undef TARGET_SCHED_DISPATCH
33716 #define TARGET_SCHED_DISPATCH has_dispatch
33717 #undef TARGET_SCHED_DISPATCH_DO
33718 #define TARGET_SCHED_DISPATCH_DO do_dispatch
33720 /* The size of the dispatch window is the total number of bytes of
33721 object code allowed in a window. */
33722 #define DISPATCH_WINDOW_SIZE 16
33724 /* Number of dispatch windows considered for scheduling. */
33725 #define MAX_DISPATCH_WINDOWS 3
33727 /* Maximum number of instructions in a window. */
33728 #define MAX_INSN 4
33730 /* Maximum number of immediate operands in a window. */
33731 #define MAX_IMM 4
33733 /* Maximum number of immediate bits allowed in a window. */
33734 #define MAX_IMM_SIZE 128
33736 /* Maximum number of 32 bit immediates allowed in a window. */
33737 #define MAX_IMM_32 4
33739 /* Maximum number of 64 bit immediates allowed in a window. */
33740 #define MAX_IMM_64 2
33742 /* Maximum total of loads or prefetches allowed in a window. */
33743 #define MAX_LOAD 2
33745 /* Maximum total of stores allowed in a window. */
33746 #define MAX_STORE 1
33748 #undef BIG
33749 #define BIG 100
33752 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
33755 disp_load,
33756 disp_store,
33757 disp_load_store,
33758 disp_prefetch,
33759 disp_imm,
33760 disp_imm_32,
33761 disp_imm_64,
33762 disp_branch,
33763 disp_cmp,
33764 disp_jcc,
33765 disp_last
33766 };
33768 /* Number of allowable groups in a dispatch window. It is an array
33769 indexed by dispatch_group enum. 100 is used as a big number,
33770 because the number of these kind of operations does not have any
33771 effect in dispatch window, but we need them for other reasons in
33772 the table. */
33775 };
33781 };
33783 /* Instruction path. */
33789 last_path
33790 };
33792 /* sched_insn_info defines a window to the instructions scheduled in
33793 the basic block. It contains a pointer to the insn_info table and
33794 the instruction scheduled.
33796 Windows are allocated for each basic block and are linked
33797 together. */
33799 rtx insn;
33806 /* Linked list of dispatch windows. This is a two way list of
33807 dispatch windows of a basic block. It contains information about
33808 the number of uops in the window and the total number of
33809 instructions and of bytes in the object code for this dispatch
33810 window. */
33828 /* Immediate valuse used in an insn. */
33830 {
33839 /* Get dispatch group of insn. */
33841 static enum dispatch_group
33843 {
33859 }
33861 /* Return true if insn is a compare instruction. */
33863 static bool
33865 {
33873 }
33875 /* Return true if a dispatch violation encountered. */
33877 static bool
33879 {
33883 }
33885 /* Return true if insn is a branch instruction. */
33887 static bool
33889 {
33891 }
33893 /* Return true if insn is a prefetch instruction. */
33895 static bool
33897 {
33899 }
33901 /* This function initializes a dispatch window and the list container holding a
33902 pointer to the window. */
33904 static void
33906 {
33912 else
33930 {
33936 }
33938 }
33940 /* This function allocates and initializes a dispatch window and the
33941 list container holding a pointer to the window. */
33945 {
33950 }
33952 /* This routine initializes the dispatch scheduling information. It
33953 initiates building dispatch scheduler tables and constructs the
33954 first dispatch window. */
33956 static void
33958 {
33959 /* Allocate a dispatch list and a window. */
33964 }
33966 /* This function returns true if a branch is detected. End of a basic block
33967 does not have to be a branch, but here we assume only branches end a
33968 window. */
33970 static bool
33972 {
33974 }
33976 /* This function is called when the end of a window processing is reached. */
33978 static void
33980 {
33983 {
33988 }
33990 }
33992 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
33993 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
33994 for 48 bytes of instructions. Note that these windows are not dispatch
33995 windows that their sizes are DISPATCH_WINDOW_SIZE. */
33999 {
34001 {
34006 }
34012 }
34014 /* Increment the number of immediate operands of an instruction. */
34016 static int
34018 {
34023 {
34030 else
34041 {
34044 }
34049 }
34052 }
34054 /* Compute number of immediate operands of an instruction. */
34056 static void
34058 {
34061 }
34063 /* Return total size of immediate operands of an instruction along with number
34064 of corresponding immediate-operands. It initializes its parameters to zero
34065 befor calling FIND_CONSTANT.
34066 INSN is the input instruction. IMM is the total of immediates.
34067 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
34068 bit immediates. */
34070 static int
34072 {
34080 }
34082 /* This function indicates if an operand of an instruction is an
34083 immediate. */
34085 static bool
34087 {
34096 }
34098 /* Return single or double path for instructions. */
34100 static enum insn_path
34102 {
34112 }
34114 /* Return insn dispatch group. */
34116 static enum dispatch_group
34118 {
34136 }
34138 /* Count number of GROUP restricted instructions in a dispatch
34139 window WINDOW_LIST. */
34141 static int
34143 {
34154 {
34173 }
34186 }
34188 /* This function returns true if insn satisfies dispatch rules on the
34189 last window scheduled. */
34191 static bool
34193 {
34201 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
34202 instructions should be given the lowest priority in the
34203 scheduling process in Haifa scheduler to make sure they will be
34204 scheduled in the same dispatch window as the refrence to them. */
34208 /* Check nonrestricted. */
34212 /* Get last dispatch window. */
34217 {
34222 /* Window 1 is full. Go for next window. */
34224 }
34231 /* See if it fits in the first window. */
34233 {
34234 /* The first widow should have only single and double path
34235 uops. */
34241 }
34243 }
34245 /* Add an instruction INSN with NUM_UOPS micro-operations to the
34246 dispatch window WINDOW_LIST. */
34248 static void
34250 {
34268 /* Initialize window with new instruction. */
34289 {
34292 }
34293 }
34295 /* Adds a scheduled instruction, INSN, to the current dispatch window.
34296 If the total bytes of instructions or the number of instructions in
34297 the window exceed allowable, it allocates a new window. */
34299 static void
34301 {
34324 /* Get the last dispatch window. */
34332 else
34335 /* If current window is full, get a new window.
34336 Window number zero is full, if MAX_INSN uops are scheduled in it.
34337 Window number one is full, if window zero's bytes plus window
34338 one's bytes is 32, or if the bytes of the new instruction added
34339 to the total makes it greater than 48, or it has already MAX_INSN
34340 instructions in it. */
34349 {
34352 }
34355 {
34359 {
34362 }
34363 }
34365 {
34370 {
34373 }
34376 }
34377 else
34381 {
34382 /* End of basic block is reached do end-basic-block process. */
34385 }
34386 }
34388 /* Print the dispatch window, WINDOW_NUM, to FILE. */
34390 DEBUG_FUNCTION static void
34392 {
34398 else
34412 {
34415 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
34421 }
34422 }
34424 /* Print to stdout a dispatch window. */
34426 DEBUG_FUNCTION void
34428 {
34430 }
34432 /* Print INSN dispatch information to FILE. */
34434 DEBUG_FUNCTION static void
34436 {
34459 }
34461 /* Print to STDERR the status of the ready list with respect to
34462 dispatch windows. */
34464 DEBUG_FUNCTION void
34466 {
34474 }
34476 /* This routine is the driver of the dispatch scheduler. */
34478 static void
34480 {
34485 }
34487 /* Return TRUE if Dispatch Scheduling is supported. */
34489 static bool
34491 {
34494 {
34510 }
34513 }
34515 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
34516 place emms and femms instructions. */
34518 static enum machine_mode
34520 {
34521 /* Disable double precision vectorizer if needed. */
34529 {
34544 }
34547 }
34549 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
34550 vectors. */
34552 static unsigned int
34554 {
34556 }
34558 /* Initialize the GCC target structure. */
34559 #undef TARGET_RETURN_IN_MEMORY
34560 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
34562 #undef TARGET_LEGITIMIZE_ADDRESS
34563 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
34565 #undef TARGET_ATTRIBUTE_TABLE
34566 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
34567 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
34568 # undef TARGET_MERGE_DECL_ATTRIBUTES
34569 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
34570 #endif
34572 #undef TARGET_COMP_TYPE_ATTRIBUTES
34573 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
34575 #undef TARGET_INIT_BUILTINS
34576 #define TARGET_INIT_BUILTINS ix86_init_builtins
34577 #undef TARGET_BUILTIN_DECL
34578 #define TARGET_BUILTIN_DECL ix86_builtin_decl
34579 #undef TARGET_EXPAND_BUILTIN
34580 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
34582 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
34583 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
34584 ix86_builtin_vectorized_function
34586 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
34587 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
34589 #undef TARGET_BUILTIN_RECIPROCAL
34590 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
34592 #undef TARGET_ASM_FUNCTION_EPILOGUE
34593 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
34595 #undef TARGET_ENCODE_SECTION_INFO
34596 #ifndef SUBTARGET_ENCODE_SECTION_INFO
34597 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
34598 #else
34599 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
34600 #endif
34602 #undef TARGET_ASM_OPEN_PAREN
34604 #undef TARGET_ASM_CLOSE_PAREN
34607 #undef TARGET_ASM_BYTE_OP
34608 #define TARGET_ASM_BYTE_OP ASM_BYTE
34610 #undef TARGET_ASM_ALIGNED_HI_OP
34611 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
34612 #undef TARGET_ASM_ALIGNED_SI_OP
34613 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
34614 #ifdef ASM_QUAD
34615 #undef TARGET_ASM_ALIGNED_DI_OP
34616 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
34617 #endif
34619 #undef TARGET_PROFILE_BEFORE_PROLOGUE
34620 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
34622 #undef TARGET_ASM_UNALIGNED_HI_OP
34623 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
34624 #undef TARGET_ASM_UNALIGNED_SI_OP
34625 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
34626 #undef TARGET_ASM_UNALIGNED_DI_OP
34627 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
34629 #undef TARGET_PRINT_OPERAND
34630 #define TARGET_PRINT_OPERAND ix86_print_operand
34631 #undef TARGET_PRINT_OPERAND_ADDRESS
34632 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
34633 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
34634 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
34635 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
34636 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
34638 #undef TARGET_SCHED_INIT_GLOBAL
34639 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
34640 #undef TARGET_SCHED_ADJUST_COST
34641 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
34642 #undef TARGET_SCHED_ISSUE_RATE
34643 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
34644 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
34645 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
34646 ia32_multipass_dfa_lookahead
34648 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
34649 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
34651 #ifdef HAVE_AS_TLS
34652 #undef TARGET_HAVE_TLS
34653 #define TARGET_HAVE_TLS true
34654 #endif
34655 #undef TARGET_CANNOT_FORCE_CONST_MEM
34656 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
34657 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
34658 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
34660 #undef TARGET_DELEGITIMIZE_ADDRESS
34661 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
34663 #undef TARGET_MS_BITFIELD_LAYOUT_P
34664 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
34666 #if TARGET_MACHO
34667 #undef TARGET_BINDS_LOCAL_P
34668 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
34669 #endif
34670 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
34671 #undef TARGET_BINDS_LOCAL_P
34672 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
34673 #endif
34675 #undef TARGET_ASM_OUTPUT_MI_THUNK
34676 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
34677 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
34678 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
34680 #undef TARGET_ASM_FILE_START
34681 #define TARGET_ASM_FILE_START x86_file_start
34683 #undef TARGET_DEFAULT_TARGET_FLAGS
34684 #define TARGET_DEFAULT_TARGET_FLAGS \
34685 (TARGET_DEFAULT \
34686 | TARGET_SUBTARGET_DEFAULT \
34687 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
34689 #undef TARGET_HANDLE_OPTION
34690 #define TARGET_HANDLE_OPTION ix86_handle_option
34692 #undef TARGET_OPTION_OVERRIDE
34693 #define TARGET_OPTION_OVERRIDE ix86_option_override
34694 #undef TARGET_OPTION_OPTIMIZATION_TABLE
34695 #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
34696 #undef TARGET_OPTION_INIT_STRUCT
34697 #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
34699 #undef TARGET_REGISTER_MOVE_COST
34700 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
34701 #undef TARGET_MEMORY_MOVE_COST
34702 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
34703 #undef TARGET_RTX_COSTS
34704 #define TARGET_RTX_COSTS ix86_rtx_costs
34705 #undef TARGET_ADDRESS_COST
34706 #define TARGET_ADDRESS_COST ix86_address_cost
34708 #undef TARGET_FIXED_CONDITION_CODE_REGS
34709 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
34710 #undef TARGET_CC_MODES_COMPATIBLE
34711 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
34713 #undef TARGET_MACHINE_DEPENDENT_REORG
34714 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
34716 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
34717 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
34719 #undef TARGET_BUILD_BUILTIN_VA_LIST
34720 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
34722 #undef TARGET_ENUM_VA_LIST_P
34723 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
34725 #undef TARGET_FN_ABI_VA_LIST
34726 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
34728 #undef TARGET_CANONICAL_VA_LIST_TYPE
34729 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
34731 #undef TARGET_EXPAND_BUILTIN_VA_START
34732 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
34734 #undef TARGET_MD_ASM_CLOBBERS
34735 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
34737 #undef TARGET_PROMOTE_PROTOTYPES
34738 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
34739 #undef TARGET_STRUCT_VALUE_RTX
34740 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
34741 #undef TARGET_SETUP_INCOMING_VARARGS
34742 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
34743 #undef TARGET_MUST_PASS_IN_STACK
34744 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
34745 #undef TARGET_FUNCTION_ARG_ADVANCE
34746 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
34747 #undef TARGET_FUNCTION_ARG
34748 #define TARGET_FUNCTION_ARG ix86_function_arg
34749 #undef TARGET_FUNCTION_ARG_BOUNDARY
34750 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
34751 #undef TARGET_PASS_BY_REFERENCE
34752 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
34753 #undef TARGET_INTERNAL_ARG_POINTER
34754 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
34755 #undef TARGET_UPDATE_STACK_BOUNDARY
34756 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
34757 #undef TARGET_GET_DRAP_RTX
34758 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
34759 #undef TARGET_STRICT_ARGUMENT_NAMING
34760 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
34761 #undef TARGET_STATIC_CHAIN
34762 #define TARGET_STATIC_CHAIN ix86_static_chain
34763 #undef TARGET_TRAMPOLINE_INIT
34764 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
34765 #undef TARGET_RETURN_POPS_ARGS
34766 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
34768 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
34769 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
34771 #undef TARGET_SCALAR_MODE_SUPPORTED_P
34772 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
34774 #undef TARGET_VECTOR_MODE_SUPPORTED_P
34775 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
34777 #undef TARGET_C_MODE_FOR_SUFFIX
34778 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
34780 #ifdef HAVE_AS_TLS
34781 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
34782 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
34783 #endif
34785 #ifdef SUBTARGET_INSERT_ATTRIBUTES
34786 #undef TARGET_INSERT_ATTRIBUTES
34787 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
34788 #endif
34790 #undef TARGET_MANGLE_TYPE
34791 #define TARGET_MANGLE_TYPE ix86_mangle_type
34793 #undef TARGET_STACK_PROTECT_FAIL
34794 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
34796 #undef TARGET_SUPPORTS_SPLIT_STACK
34797 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
34799 #undef TARGET_FUNCTION_VALUE
34800 #define TARGET_FUNCTION_VALUE ix86_function_value
34802 #undef TARGET_FUNCTION_VALUE_REGNO_P
34803 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
34805 #undef TARGET_SECONDARY_RELOAD
34806 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
34808 #undef TARGET_PREFERRED_RELOAD_CLASS
34809 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
34810 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
34811 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
34812 #undef TARGET_CLASS_LIKELY_SPILLED_P
34813 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
34815 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
34816 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
34817 ix86_builtin_vectorization_cost
34818 #undef TARGET_VECTORIZE_BUILTIN_VEC_PERM
34819 #define TARGET_VECTORIZE_BUILTIN_VEC_PERM \
34820 ix86_vectorize_builtin_vec_perm
34821 #undef TARGET_VECTORIZE_BUILTIN_VEC_PERM_OK
34822 #define TARGET_VECTORIZE_BUILTIN_VEC_PERM_OK \
34823 ix86_vectorize_builtin_vec_perm_ok
34824 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
34825 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
34826 ix86_preferred_simd_mode
34827 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
34828 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
34829 ix86_autovectorize_vector_sizes
34831 #undef TARGET_SET_CURRENT_FUNCTION
34832 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
34834 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
34835 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
34837 #undef TARGET_OPTION_SAVE
34838 #define TARGET_OPTION_SAVE ix86_function_specific_save
34840 #undef TARGET_OPTION_RESTORE
34841 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
34843 #undef TARGET_OPTION_PRINT
34844 #define TARGET_OPTION_PRINT ix86_function_specific_print
34846 #undef TARGET_CAN_INLINE_P
34847 #define TARGET_CAN_INLINE_P ix86_can_inline_p
34849 #undef TARGET_EXPAND_TO_RTL_HOOK
34850 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
34852 #undef TARGET_LEGITIMATE_ADDRESS_P
34853 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
34855 #undef TARGET_IRA_COVER_CLASSES
34856 #define TARGET_IRA_COVER_CLASSES i386_ira_cover_classes
34858 #undef TARGET_FRAME_POINTER_REQUIRED
34859 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
34861 #undef TARGET_CAN_ELIMINATE
34862 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
34864 #undef TARGET_EXTRA_LIVE_ON_ENTRY
34865 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
34867 #undef TARGET_ASM_CODE_END
34868 #define TARGET_ASM_CODE_END ix86_code_end
34870 #undef TARGET_CONDITIONAL_REGISTER_USAGE
34871 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
34874 \f