| blob | 46cd6db62ad83970dfbb61e7e93f827c26dfc63a |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
106 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
138 /* Number of attempts to combine instructions in this function. */
142 /* Number of attempts that got as far as substitution in this function. */
146 /* Number of instructions combined with added SETs in this function. */
150 /* Number of instructions combined in this function. */
154 /* Totals over entire compilation. */
158 /* combine_instructions may try to replace the right hand side of the
159 second instruction with the value of an associated REG_EQUAL note
160 before throwing it at try_combine. That is problematic when there
161 is a REG_DEAD note for a register used in the old right hand side
162 and can cause distribute_notes to do wrong things. This is the
163 second instruction if it has been so modified, null otherwise. */
167 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
171 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
174 \f
176 /* Record last point of death of (hard or pseudo) register n. */
179 /* Record last point of modification of (hard or pseudo) register n. */
182 /* The next group of fields allows the recording of the last value assigned
183 to (hard or pseudo) register n. We use this information to see if an
184 operation being processed is redundant given a prior operation performed
185 on the register. For example, an `and' with a constant is redundant if
186 all the zero bits are already known to be turned off.
188 We use an approach similar to that used by cse, but change it in the
189 following ways:
191 (1) We do not want to reinitialize at each label.
192 (2) It is useful, but not critical, to know the actual value assigned
193 to a register. Often just its form is helpful.
195 Therefore, we maintain the following fields:
197 last_set_value the last value assigned
198 last_set_label records the value of label_tick when the
199 register was assigned
200 last_set_table_tick records the value of label_tick when a
201 value using the register is assigned
202 last_set_invalid set to nonzero when it is not valid
203 to use the value of this register in some
204 register's value
206 To understand the usage of these tables, it is important to understand
207 the distinction between the value in last_set_value being valid and
208 the register being validly contained in some other expression in the
209 table.
211 (The next two parameters are out of date).
213 reg_stat[i].last_set_value is valid if it is nonzero, and either
214 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
216 Register I may validly appear in any expression returned for the value
217 of another register if reg_n_sets[i] is 1. It may also appear in the
218 value for register J if reg_stat[j].last_set_invalid is zero, or
219 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
221 If an expression is found in the table containing a register which may
222 not validly appear in an expression, the register is replaced by
223 something that won't match, (clobber (const_int 0)). */
225 /* Record last value assigned to (hard or pseudo) register n. */
227 rtx last_set_value;
229 /* Record the value of label_tick when an expression involving register n
230 is placed in last_set_value. */
234 /* Record the value of label_tick when the value for register n is placed in
235 last_set_value. */
239 /* These fields are maintained in parallel with last_set_value and are
240 used to store the mode in which the register was last set, the bits
241 that were known to be zero when it was last set, and the number of
242 sign bits copies it was known to have when it was last set. */
248 /* Set nonzero if references to register n in expressions should not be
249 used. last_set_invalid is set nonzero when this register is being
250 assigned to and last_set_table_tick == label_tick. */
254 /* Some registers that are set more than once and used in more than one
255 basic block are nevertheless always set in similar ways. For example,
256 a QImode register may be loaded from memory in two places on a machine
257 where byte loads zero extend.
259 We record in the following fields if a register has some leading bits
260 that are always equal to the sign bit, and what we know about the
261 nonzero bits of a register, specifically which bits are known to be
262 zero.
264 If an entry is zero, it means that we don't know anything special. */
270 /* Record the value of the label_tick when the last truncation
271 happened. The field truncated_to_mode is only valid if
272 truncation_label == label_tick. */
276 /* Record the last truncation seen for this register. If truncation
277 is not a nop to this mode we might be able to save an explicit
278 truncation if we know that value already contains a truncated
279 value. */
287 /* One plus the highest pseudo for which we track REG_N_SETS.
288 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
289 but during combine_split_insns new pseudos can be created. As we don't have
290 updated DF information in that case, it is hard to initialize the array
291 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
292 so instead of growing the arrays, just assume all newly created pseudos
293 during combine might be set multiple times. */
297 /* Record the luid of the last insn that invalidated memory
298 (anything that writes memory, and subroutine calls, but not pushes). */
302 /* Record the luid of the last CALL_INSN
303 so we can tell whether a potential combination crosses any calls. */
307 /* When `subst' is called, this is the insn that is being modified
308 (by combining in a previous insn). The PATTERN of this insn
309 is still the old pattern partially modified and it should not be
310 looked at, but this may be used to examine the successors of the insn
311 to judge whether a simplification is valid. */
315 /* This is the lowest LUID that `subst' is currently dealing with.
316 get_last_value will not return a value if the register was set at or
317 after this LUID. If not for this mechanism, we could get confused if
318 I2 or I1 in try_combine were an insn that used the old value of a register
319 to obtain a new value. In that case, we might erroneously get the
320 new value of the register when we wanted the old one. */
324 /* This contains any hard registers that are used in newpat; reg_dead_at_p
325 must consider all these registers to be always live. */
329 /* This is an insn to which a LOG_LINKS entry has been added. If this
330 insn is the earlier than I2 or I3, combine should rescan starting at
331 that location. */
335 /* Basic block in which we are performing combines. */
339 \f
340 /* Length of the currently allocated uid_insn_cost array. */
344 /* The following array records the insn_rtx_cost for every insn
345 in the instruction stream. */
349 /* The following array records the LOG_LINKS for every insn in the
350 instruction stream as struct insn_link pointers. */
356 };
360 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
361 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
363 #define FOR_EACH_LOG_LINK(L, INSN) \
364 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
366 /* Links for LOG_LINKS are allocated from this obstack. */
370 /* Allocate a link. */
374 {
382 }
384 /* Incremented for each basic block. */
388 /* Reset to label_tick for each extended basic block in scanning order. */
392 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
393 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
397 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
398 be safely used. It is zero while computing them and after combine has
399 completed. This former test prevents propagating values based on
400 previously set values, which can be incorrect if a variable is modified
401 in a loop. */
405 \f
406 /* Record one modification to rtl structure
407 to be undone by storing old_contents into *where. */
411 struct undo
412 {
417 };
419 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
420 num_undo says how many are currently recorded.
422 other_insn is nonzero if we have modified some other insn in the process
423 of working on subst_insn. It must be verified too. */
425 struct undobuf
426 {
430 };
434 /* Number of times the pseudo being substituted for
435 was found and replaced. */
440 machine_mode,
444 machine_mode,
516 \f
518 /* It is not safe to use ordinary gen_lowpart in combine.
519 See comments in gen_lowpart_for_combine. */
520 #undef RTL_HOOKS_GEN_LOWPART
521 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
523 /* Our implementation of gen_lowpart never emits a new pseudo. */
524 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
525 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
527 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
528 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
530 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
531 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
533 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
534 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
538 \f
539 /* Convenience wrapper for the canonicalize_comparison target hook.
540 Target hooks cannot use enum rtx_code. */
544 {
548 }
550 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
551 PATTERN can not be split. Otherwise, it returns an insn sequence.
552 This is a wrapper around split_insns which ensures that the
553 reg_stat vector is made larger if the splitter creates a new
554 register. */
558 {
567 }
569 /* This is used by find_single_use to locate an rtx in LOC that
570 contains exactly one use of DEST, which is typically either a REG
571 or CC0. It returns a pointer to the innermost rtx expression
572 containing DEST. Appearances of DEST that are being used to
573 totally replace it are not counted. */
577 {
586 {
590 CASE_CONST_ANY:
595 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
596 of a REG that occupies all of the REG, the insn uses DEST if
597 it is mentioned in the destination or the source. Otherwise, we
598 need just check the source. */
618 }
620 /* If it wasn't one of the common cases above, check each expression and
621 vector of this code. Look for a unique usage of DEST. */
625 {
627 {
632 else
638 /* Duplicate usage. */
640 }
642 {
646 {
652 else
659 }
660 }
661 }
664 }
667 /* See if DEST, produced in INSN, is used only a single time in the
668 sequel. If so, return a pointer to the innermost rtx expression in which
669 it is used.
671 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
673 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
674 care about REG_DEAD notes or LOG_LINKS.
676 Otherwise, we find the single use by finding an insn that has a
677 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
678 only referenced once in that insn, we know that it must be the first
679 and last insn referencing DEST. */
683 {
684 basic_block bb;
689 #ifdef HAVE_cc0
691 {
701 }
702 #endif
712 {
718 {
723 }
724 }
727 }
728 \f
729 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
730 insn. The substitution can be undone by undo_all. If INTO is already
731 set to NEWVAL, do not record this change. Because computing NEWVAL might
732 also call SUBST, we have to compute it before we put anything into
733 the undo table. */
735 static void
737 {
744 /* We'd like to catch as many invalid transformations here as
745 possible. Unfortunately, there are way too many mode changes
746 that are perfectly valid, so we'd waste too much effort for
747 little gain doing the checks here. Focus on catching invalid
748 transformations involving integer constants. */
751 {
752 /* Sanity check that we're replacing oldval with a CONST_INT
753 that is a valid sign-extension for the original mode. */
757 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
758 CONST_INT is not valid, because after the replacement, the
759 original mode would be gone. Unfortunately, we can't tell
760 when do_SUBST is called to replace the operand thereof, so we
761 perform this test on oldval instead, checking whether an
762 invalid replacement took place before we got here. */
767 }
771 else
780 }
782 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
784 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
785 for the value of a HOST_WIDE_INT value (including CONST_INT) is
786 not safe. */
788 static void
790 {
799 else
808 }
810 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
812 /* Similar to SUBST, but just substitute the mode. This is used when
813 changing the mode of a pseudo-register, so that any other
814 references to the entry in the regno_reg_rtx array will change as
815 well. */
817 static void
819 {
828 else
837 }
839 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
841 #ifndef HAVE_cc0
842 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
844 static void
846 {
855 else
864 }
866 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
867 #endif
868 \f
869 /* Subroutine of try_combine. Determine whether the replacement patterns
870 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
871 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
872 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
873 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
874 of all the instructions can be estimated and the replacements are more
875 expensive than the original sequence. */
877 static bool
880 {
885 /* Lookup the original insn_rtx_costs. */
890 {
893 {
897 }
898 else
899 {
903 }
904 }
905 else
906 {
909 }
911 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
912 correct that. */
917 /* Calculate the replacement insn_rtx_costs. */
920 {
924 }
925 else
926 {
929 }
932 {
938 {
941 }
942 else
944 }
946 /* Disallow this combination if both new_cost and old_cost are greater than
947 zero, and new_cost is greater than old cost. */
951 {
970 else
972 }
977 /* Update the uid_insn_cost array with the replacement costs. */
981 {
985 }
988 }
991 /* Delete any insns that copy a register to itself. */
993 static void
995 {
997 basic_block bb;
1000 {
1002 {
1005 {
1010 }
1011 }
1012 }
1013 }
1015 \f
1016 /* Return false if we do not want to (or cannot) combine DEF. */
1017 static bool
1019 {
1020 /* Do not consider if it is pre/post modification in MEM. */
1026 /* Do not combine frame pointer adjustments. */
1029 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1032 #endif
1033 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1035 #endif
1036 )
1040 }
1042 /* Return false if we do not want to (or cannot) combine USE. */
1043 static bool
1045 {
1046 /* Do not consider the usage of the stack pointer by function call. */
1051 }
1053 /* Fill in log links field for all insns. */
1055 static void
1057 {
1058 basic_block bb;
1065 /* Pass through each block from the end, recording the uses of each
1066 register and establishing log links when def is encountered.
1067 Note that we do not clear next_use array in order to save time,
1068 so we have to test whether the use is in the same basic block as def.
1070 There are a few cases below when we do not consider the definition or
1071 usage -- these are taken from original flow.c did. Don't ask me why it is
1072 done this way; I don't know and if it works, I don't want to know. */
1075 {
1077 {
1081 /* Log links are created only once. */
1085 {
1101 /* flow.c claimed:
1103 We don't build a LOG_LINK for hard registers contained
1104 in ASM_OPERANDs. If these registers get replaced,
1105 we might wind up changing the semantics of the insn,
1106 even if reload can make what appear to be valid
1107 assignments later. */
1112 /* Don't add duplicate links between instructions. */
1121 }
1126 }
1127 }
1130 }
1132 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1133 true if we found a LOG_LINK that proves that A feeds B. This only works
1134 if there are no instructions between A and B which could have a link
1135 depending on A, since in that case we would not record a link for B.
1136 We also check the implicit dependency created by a cc0 setter/user
1137 pair. */
1139 static bool
1141 {
1146 #ifdef HAVE_cc0
1149 #endif
1151 }
1152 \f
1153 /* Main entry point for combiner. F is the first insn of the function.
1154 NREGS is the first unused pseudo-reg number.
1156 Return nonzero if the combiner has turned an indirect jump
1157 instruction into a direct jump. */
1158 static int
1160 {
1162 #ifdef HAVE_cc0
1164 #endif
1167 basic_block last_bb;
1187 /* Allocate array for insn info. */
1195 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1196 problems when, for example, we have j <<= 1 in a loop. */
1201 /* Scan all SETs and see if we can deduce anything about what
1202 bits are known to be zero for some registers and how many copies
1203 of the sign bit are known to exist for those registers.
1205 Also set any known values so that we can use it while searching
1206 for what bits are known to be set. */
1209 /* Allow the entry block and the first block to fall into the same EBB.
1210 Conceptually the incoming promotions are assigned to the entry block. */
1215 {
1220 label_tick++;
1228 {
1229 #ifdef AUTO_INC_DEC
1230 rtx links;
1231 #endif
1237 insn);
1240 #ifdef AUTO_INC_DEC
1244 insn);
1245 #endif
1247 /* Record the current insn_rtx_cost of this instruction. */
1250 optimize_this_for_speed_p);
1254 }
1255 }
1259 /* Now scan all the insns in forward order. */
1267 {
1273 label_tick++;
1283 {
1297 /* See if we know about function return values before this
1298 insn based upon SUBREG flags. */
1301 /* See if we can find hardregs and subreg of pseudos in
1302 narrower modes. This could help turning TRUNCATEs
1303 into SUBREGs. */
1306 /* Try this insn with each insn it links back to. */
1312 {
1315 }
1317 /* Try each sequence of three linked insns ending with this one. */
1321 {
1324 /* If the linked insn has been replaced by a note, then there
1325 is no point in pursuing this chain any further. */
1333 {
1336 }
1337 }
1339 #ifdef HAVE_cc0
1340 /* Try to combine a jump insn that uses CC0
1341 with a preceding insn that sets CC0, and maybe with its
1342 logical predecessor as well.
1343 This is how we make decrement-and-branch insns.
1344 We need this special code because data flow connections
1345 via CC0 do not get entered in LOG_LINKS. */
1351 {
1362 }
1364 /* Do the same for an insn that explicitly references CC0. */
1371 {
1382 }
1384 /* Finally, see if any of the insns that this insn links to
1385 explicitly references CC0. If so, try this insn, that insn,
1386 and its predecessor if it sets CC0. */
1398 #endif
1400 /* Try combining an insn with two different insns whose results it
1401 uses. */
1411 {
1414 }
1416 /* Try four-instruction combinations. */
1419 {
1423 /* If the linked insn has been replaced by a note, then there
1424 is no point in pursuing this chain any further. */
1429 {
1433 /* I0 -> I1 -> I2 -> I3. */
1439 {
1442 }
1443 /* I0, I1 -> I2, I2 -> I3. */
1450 {
1453 }
1454 }
1457 {
1461 /* I0 -> I2; I1, I2 -> I3. */
1467 {
1470 }
1471 /* I0 -> I1; I1, I2 -> I3. */
1477 {
1480 }
1481 }
1482 }
1484 /* Try this insn with each REG_EQUAL note it links back to. */
1486 {
1492 /* Avoid using a register that may already been marked
1493 dead by an earlier instruction. */
1498 {
1499 /* Temporarily replace the set's source with the
1500 contents of the REG_EQUAL note. The insn will
1501 be deleted or recognized by try_combine. */
1509 last_combined_insn);
1512 {
1515 }
1517 }
1518 }
1523 retry:
1524 ;
1525 }
1526 }
1533 /* Clean up. */
1539 {
1542 {
1545 }
1547 }
1557 /* Make recognizer allow volatile MEMs again. */
1561 }
1563 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1565 static void
1567 {
1573 }
1574 \f
1575 /* Set up any promoted values for incoming argument registers. */
1577 static void
1579 {
1580 tree arg;
1585 {
1590 /* Only continue if the incoming argument is in a register. */
1594 /* Determine, if possible, whether all call sites of the current
1595 function lie within the current compilation unit. (This does
1596 take into account the exporting of a function via taking its
1597 address, and so forth.) */
1600 /* The mode and signedness of the argument before any promotions happen
1601 (equal to the mode of the pseudo holding it at that stage). */
1605 /* The mode and signedness of the argument after any source language and
1606 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1610 /* The mode and signedness of the argument as it is actually passed,
1611 see assign_parm_setup_reg in function.c. */
1615 /* The mode of the register in which the argument is being passed. */
1618 /* Eliminate sign extensions in the callee when:
1619 (a) A mode promotion has occurred; */
1622 /* (b) The mode of the register is the same as the mode of
1623 the argument as it is passed; */
1626 /* (c) There's no language level extension; */
1628 ;
1629 /* (c.1) All callers are from the current compilation unit. If that's
1630 the case we don't have to rely on an ABI, we only have to know
1631 what we're generating right now, and we know that we will do the
1632 mode1 to mode2 promotion with the given sign. */
1635 /* (c.2) The combination of the two promotions is useful. This is
1636 true when the signs match, or if the first promotion is unsigned.
1637 In the later case, (sign_extend (zero_extend x)) is the same as
1638 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1644 /* Record that the value was promoted from mode1 to mode3,
1645 so that any sign extension at the head of the current
1646 function may be eliminated. */
1650 }
1651 }
1653 /* Called via note_stores. If X is a pseudo that is narrower than
1654 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1656 If we are setting only a portion of X and we can't figure out what
1657 portion, assume all bits will be used since we don't know what will
1658 be happening.
1660 Similarly, set how many bits of X are known to be copies of the sign bit
1661 at all locations in the function. This is the smallest number implied
1662 by any set of X. */
1664 static void
1666 {
1672 /* If this register is undefined at the start of the file, we can't
1673 say what its contents were. */
1674 && ! REGNO_REG_SET_P
1677 {
1681 {
1685 }
1687 /* If this register is being initialized using itself, and the
1688 register is uninitialized in this basic block, and there are
1689 no LOG_LINKS which set the register, then part of the
1690 register is uninitialized. In that case we can't assume
1691 anything about the number of nonzero bits.
1693 ??? We could do better if we checked this in
1694 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1695 could avoid making assumptions about the insn which initially
1696 sets the register, while still using the information in other
1697 insns. We would have to be careful to check every insn
1698 involved in the combination. */
1704 {
1711 {
1715 }
1716 }
1718 /* If this is a complex assignment, see if we can convert it into a
1719 simple assignment. */
1722 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1723 set what we know about X. */
1728 {
1731 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1732 /* If X is narrower than a word and SRC is a non-negative
1733 constant that would appear negative in the mode of X,
1734 sign-extend it for use in reg_stat[].nonzero_bits because some
1735 machines (maybe most) will actually do the sign-extension
1736 and this is the conservative approach.
1738 ??? For 2.5, try to tighten up the MD files in this regard
1739 instead of this kludge. */
1746 #endif
1748 /* Don't call nonzero_bits if it cannot change anything. */
1755 }
1756 else
1757 {
1760 }
1761 }
1762 }
1763 \f
1764 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1765 optionally insns that were previously combined into I3 or that will be
1766 combined into the merger of INSN and I3. The order is PRED, PRED2,
1767 INSN, SUCC, SUCC2, I3.
1769 Return 0 if the combination is not allowed for any reason.
1771 If the combination is allowed, *PDEST will be set to the single
1772 destination of INSN and *PSRC to the single source, and this function
1773 will return 1. */
1775 static int
1779 {
1784 #ifdef AUTO_INC_DEC
1785 rtx link;
1786 #endif
1791 {
1793 {
1798 }
1803 }
1807 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1808 or a PARALLEL consisting of such a SET and CLOBBERs.
1810 If INSN has CLOBBER parallel parts, ignore them for our processing.
1811 By definition, these happen during the execution of the insn. When it
1812 is merged with another insn, all bets are off. If they are, in fact,
1813 needed and aren't also supplied in I3, they may be added by
1814 recog_for_combine. Otherwise, it won't match.
1816 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1817 note.
1819 Get the source and destination of INSN. If more than one, can't
1820 combine. */
1826 {
1828 {
1832 {
1833 /* This is important to combine floating point insns
1834 for the SH4 port. */
1836 /* Combining an isolated USE doesn't make sense.
1837 We depend here on combinable_i3pat to reject them. */
1838 /* The code below this loop only verifies that the inputs of
1839 the SET in INSN do not change. We call reg_set_between_p
1840 to verify that the REG in the USE does not change between
1841 I3 and INSN.
1842 If the USE in INSN was for a pseudo register, the matching
1843 insn pattern will likely match any register; combining this
1844 with any other USE would only be safe if we knew that the
1845 used registers have identical values, or if there was
1846 something to tell them apart, e.g. different modes. For
1847 now, we forgo such complicated tests and simply disallow
1848 combining of USES of pseudo registers with any other USE. */
1851 {
1856 do
1857 {
1867 }
1869 }
1872 /* We can ignore CLOBBERs. */
1877 /* Ignore SETs whose result isn't used but not those that
1878 have side-effects. */
1884 /* If we have already found a SET, this is a second one and
1885 so we cannot combine with this insn. */
1893 /* Anything else means we can't combine. */
1895 }
1896 }
1899 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1900 so don't do anything with it. */
1903 }
1904 else
1910 /* The simplification in expand_field_assignment may call back to
1911 get_last_value, so set safe guard here. */
1917 /* Don't eliminate a store in the stack pointer. */
1919 /* Don't combine with an insn that sets a register to itself if it has
1920 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1922 /* Can't merge an ASM_OPERANDS. */
1924 /* Can't merge a function call. */
1926 /* Don't eliminate a function call argument. */
1932 /* Don't substitute into an incremented register. */
1936 /* Don't substitute into a non-local goto, this confuses CFG. */
1938 /* Make sure that DEST is not used after SUCC but before I3. */
1939 || (!all_adjacent
1940 && ((succ2
1944 /* Make sure that the value that is to be substituted for the register
1945 does not use any registers whose values alter in between. However,
1946 If the insns are adjacent, a use can't cross a set even though we
1947 think it might (this can happen for a sequence of insns each setting
1948 the same destination; last_set of that register might point to
1949 a NOTE). If INSN has a REG_EQUIV note, the register is always
1950 equivalent to the memory so the substitution is valid even if there
1951 are intervening stores. Also, don't move a volatile asm or
1952 UNSPEC_VOLATILE across any other insns. */
1953 || (! all_adjacent
1959 /* Don't combine across a CALL_INSN, because that would possibly
1960 change whether the life span of some REGs crosses calls or not,
1961 and it is a pain to update that information.
1962 Exception: if source is a constant, moving it later can't hurt.
1963 Accept that as a special case. */
1967 /* DEST must either be a REG or CC0. */
1969 {
1970 /* If register alignment is being enforced for multi-word items in all
1971 cases except for parameters, it is possible to have a register copy
1972 insn referencing a hard register that is not allowed to contain the
1973 mode being copied and which would not be valid as an operand of most
1974 insns. Eliminate this problem by not combining with such an insn.
1976 Also, on some machines we don't want to extend the life of a hard
1977 register. */
1982 /* Don't extend the life of a hard register unless it is
1983 user variable (if we have few registers) or it can't
1984 fit into the desired register (meaning something special
1985 is going on).
1986 Also avoid substituting a return register into I3, because
1987 reload can't handle a conflict with constraints of other
1988 inputs. */
1992 }
2000 {
2003 /* If the clobber represents an earlyclobber operand, we must not
2004 substitute an expression containing the clobbered register.
2005 As we do not analyze the constraint strings here, we have to
2006 make the conservative assumption. However, if the register is
2007 a fixed hard reg, the clobber cannot represent any operand;
2008 we leave it up to the machine description to either accept or
2009 reject use-and-clobber patterns. */
2015 }
2017 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2018 or not), reject, unless nothing volatile comes between it and I3 */
2021 {
2022 /* Make sure neither succ nor succ2 contains a volatile reference. */
2027 /* We'll check insns between INSN and I3 below. */
2028 }
2030 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2031 to be an explicit register variable, and was chosen for a reason. */
2037 /* If INSN contains volatile references (specifically volatile MEMs),
2038 we cannot combine across any other volatile references.
2039 Even if INSN doesn't contain volatile references, any intervening
2040 volatile insn might affect machine state. */
2043 ? volatile_refs_p
2050 /* If INSN contains an autoincrement or autodecrement, make sure that
2051 register is not used between there and I3, and not already used in
2052 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2053 Also insist that I3 not be a jump; if it were one
2054 and the incremented register were spilled, we would lose. */
2056 #ifdef AUTO_INC_DEC
2071 #endif
2073 #ifdef HAVE_cc0
2074 /* Don't combine an insn that follows a CC0-setting insn.
2075 An insn that uses CC0 must not be separated from the one that sets it.
2076 We do, however, allow I2 to follow a CC0-setting insn if that insn
2077 is passed as I1; in that case it will be deleted also.
2078 We also allow combining in this case if all the insns are adjacent
2079 because that would leave the two CC0 insns adjacent as well.
2080 It would be more logical to test whether CC0 occurs inside I1 or I2,
2081 but that would be much slower, and this ought to be equivalent. */
2087 #endif
2089 /* If we get here, we have passed all the tests and the combination is
2090 to be allowed. */
2096 }
2097 \f
2098 /* LOC is the location within I3 that contains its pattern or the component
2099 of a PARALLEL of the pattern. We validate that it is valid for combining.
2101 One problem is if I3 modifies its output, as opposed to replacing it
2102 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2103 doing so would produce an insn that is not equivalent to the original insns.
2105 Consider:
2107 (set (reg:DI 101) (reg:DI 100))
2108 (set (subreg:SI (reg:DI 101) 0) <foo>)
2110 This is NOT equivalent to:
2112 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2113 (set (reg:DI 101) (reg:DI 100))])
2115 Not only does this modify 100 (in which case it might still be valid
2116 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2118 We can also run into a problem if I2 sets a register that I1
2119 uses and I1 gets directly substituted into I3 (not via I2). In that
2120 case, we would be getting the wrong value of I2DEST into I3, so we
2121 must reject the combination. This case occurs when I2 and I1 both
2122 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2123 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2124 of a SET must prevent combination from occurring. The same situation
2125 can occur for I0, in which case I0_NOT_IN_SRC is set.
2127 Before doing the above check, we first try to expand a field assignment
2128 into a set of logical operations.
2130 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2131 we place a register that is both set and used within I3. If more than one
2132 such register is detected, we fail.
2134 Return 1 if the combination is valid, zero otherwise. */
2136 static int
2139 {
2143 {
2148 rtx subdest;
2155 /* Check for the case where I3 modifies its output, as discussed
2156 above. We don't want to prevent pseudos from being combined
2157 into the address of a MEM, so only prevent the combination if
2158 i1 or i2 set the same MEM. */
2168 /* This is the same test done in can_combine_p except we can't test
2169 all_adjacent; we don't have to, since this instruction will stay
2170 in place, thus we are not considering increasing the lifetime of
2171 INNER_DEST.
2173 Also, if this insn sets a function argument, combining it with
2174 something that might need a spill could clobber a previous
2175 function argument; the all_adjacent test in can_combine_p also
2176 checks this; here, we do a more specific test for this case. */
2186 /* If DEST is used in I3, it is being killed in this insn, so
2187 record that for later. We have to consider paradoxical
2188 subregs here, since they kill the whole register, but we
2189 ignore partial subregs, STRICT_LOW_PART, etc.
2190 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2191 STACK_POINTER_REGNUM, since these are always considered to be
2192 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2202 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2204 #endif
2205 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2208 #endif
2210 {
2215 }
2216 }
2219 {
2226 }
2229 }
2230 \f
2231 /* Return 1 if X is an arithmetic expression that contains a multiplication
2232 and division. We don't count multiplications by powers of two here. */
2234 static int
2236 {
2238 {
2254 }
2255 }
2256 \f
2257 /* Determine whether INSN can be used in a combination. Return nonzero if
2258 not. This is used in try_combine to detect early some cases where we
2259 can't perform combinations. */
2261 static int
2263 {
2264 rtx set;
2267 /* If this isn't really an insn, we can't do anything.
2268 This can occur when flow deletes an insn that it has merged into an
2269 auto-increment address. */
2273 /* Never combine loads and stores involving hard regs that are likely
2274 to be spilled. The register allocator can usually handle such
2275 reg-reg moves by tying. If we allow the combiner to make
2276 substitutions of likely-spilled regs, reload might die.
2277 As an exception, we allow combinations involving fixed regs; these are
2278 not available to the register allocator so there's no risk involved. */
2299 }
2301 struct likely_spilled_retval_info
2302 {
2305 };
2307 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2308 hard registers that are known to be written to / clobbered in full. */
2309 static void
2311 {
2328 else
2331 }
2333 /* Return nonzero iff part of the return value is live during INSN, and
2334 it is likely spilled. This can happen when more than one insn is needed
2335 to copy the return value, e.g. when we consider to combine into the
2336 second copy insn for a complex value. */
2338 static int
2340 {
2342 rtx reg;
2345 /* We assume here that no machine mode needs more than
2346 32 hard registers when the value overlaps with a register
2347 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2362 /* Disregard parts of the return value that are set later. */
2371 /* Check if any of the (probably) live return value registers is
2372 likely spilled. */
2373 nregs --;
2374 do
2375 {
2381 }
2383 /* Adjust INSN after we made a change to its destination.
2385 Changing the destination can invalidate notes that say something about
2386 the results of the insn and a LOG_LINK pointing to the insn. */
2388 static void
2390 {
2391 /* For notes, be conservative and simply remove them. */
2394 /* The new insn will have a destination that was previously the destination
2395 of an insn just above it. Call distribute_links to make a LOG_LINK from
2396 the next use of that destination. */
2412 }
2414 /* Return TRUE if combine can reuse reg X in mode MODE.
2415 ADDED_SETS is nonzero if the original set is still required. */
2416 static bool
2418 {
2425 /* Allow hard registers if the new mode is legal, and occupies no more
2426 registers than the old mode. */
2432 /* Or a pseudo that is only used once. */
2435 && !added_sets
2437 }
2440 /* Check whether X, the destination of a set, refers to part of
2441 the register specified by REG. */
2443 static bool
2445 {
2446 /* Check that reg is an integer mode register. */
2457 }
2459 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2460 Note that the INSN should be deleted *after* removing dead edges, so
2461 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2462 but not for a (set (pc) (label_ref FOO)). */
2464 static void
2466 {
2474 {
2479 /* Remove barriers from the footer if there are any. */
2482 {
2485 else
2489 }
2492 }
2493 }
2495 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2496 by an arbitrary number of CLOBBERs. */
2497 static bool
2499 {
2517 }
2519 #ifndef HAVE_cc0
2520 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2521 CLOBBERs), can be split into individual SETs in that order, without
2522 changing semantics. */
2523 static bool
2525 {
2533 {
2542 }
2545 }
2546 #endif
2548 /* Try to combine the insns I0, I1 and I2 into I3.
2549 Here I0, I1 and I2 appear earlier than I3.
2550 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2551 I3.
2553 If we are combining more than two insns and the resulting insn is not
2554 recognized, try splitting it into two insns. If that happens, I2 and I3
2555 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2556 Otherwise, I0, I1 and I2 are pseudo-deleted.
2558 Return 0 if the combination does not work. Then nothing is changed.
2559 If we did the combination, return the insn at which combine should
2560 resume scanning.
2562 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2563 new direct jump instruction.
2565 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2566 been I3 passed to an earlier try_combine within the same basic
2567 block. */
2572 {
2573 /* New patterns for I3 and I2, respectively. */
2577 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2578 dead. */
2580 /* Total number of SETs to put into I3. */
2582 /* Nonzero if I2's or I1's body now appears in I3. */
2584 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2586 /* Contains I3 if the destination of I3 is used in its source, which means
2587 that the old life of I3 is being killed. If that usage is placed into
2588 I2 and not in I3, a REG_DEAD note must be made. */
2590 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2592 /* Copy of SET_SRC of I1 and I0, if needed. */
2594 /* Set if I2DEST was reused as a scratch register. */
2596 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2598 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2603 /* Notes that must be added to REG_NOTES in I3 and I2. */
2605 /* Notes that we substituted I3 into I2 instead of the normal case. */
2607 /* Notes that I1, I2 or I3 is a MULT operation. */
2614 rtx temp_expr;
2617 rtx new_other_notes;
2620 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2621 never be). */
2625 /* Only try four-insn combinations when there's high likelihood of
2626 success. Look for simple insns, such as loads of constants or
2627 binary operations involving a constant. */
2629 {
2639 {
2642 rtx src;
2647 {
2650 }
2652 ngood++;
2655 nshift++;
2656 }
2658 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2659 are likely manipulating its value. Ideally we'll be able to combine
2660 all four insns into a bitfield insertion of some kind.
2662 Note the source in I0 might be inside a sign/zero extension and the
2663 memory modes in I0 and I3 might be different. So extract the address
2664 from the destination of I3 and search for it in the source of I0.
2666 In the event that there's a match but the source/dest do not actually
2667 refer to the same memory, the worst that happens is we try some
2668 combinations that we wouldn't have otherwise. */
2670 /* Ensure the source of SET0 is a MEM, possibly buried inside
2671 an extension. */
2677 /* Ensure the destination of SET3 is a MEM. */
2679 /* Would it be better to extract the base address for the MEM
2680 in SET3 and look for that? I don't have cases where it matters
2681 but I could envision such cases. */
2687 }
2689 /* Exit early if one of the insns involved can't be used for
2690 combinations. */
2701 combine_attempts++;
2704 /* Reset the hard register usage information. */
2708 {
2715 else
2718 }
2720 /* If multiple insns feed into one of I2 or I3, they can be in any
2721 order. To simplify the code below, reorder them in sequence. */
2731 /* First check for one important special case that the code below will
2732 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2733 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2734 we may be able to replace that destination with the destination of I3.
2735 This occurs in the common code where we compute both a quotient and
2736 remainder into a structure, in which case we want to do the computation
2737 directly into the structure to avoid register-register copies.
2739 Note that this case handles both multiple sets in I2 and also cases
2740 where I2 has a number of CLOBBERs inside the PARALLEL.
2742 We make very conservative checks below and only try to handle the
2743 most common cases of this. For example, we only handle the case
2744 where I2 and I3 are adjacent to avoid making difficult register
2745 usage tests. */
2753 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2754 below would need to check what is inside (and reg_overlap_mentioned_p
2755 doesn't support those codes anyway). Don't allow those destinations;
2756 the resulting insn isn't likely to be recognized anyway. */
2762 {
2765 /* Make sure that the destination of I3,
2766 which we are going to substitute into one output of I2,
2767 is not used within another output of I2. We must avoid making this:
2768 (parallel [(set (mem (reg 69)) ...)
2769 (set (reg 69) ...)])
2770 which is not well-defined as to order of actions.
2771 (Besides, reload can't handle output reloads for this.)
2773 The problem can also happen if the dest of I3 is a memory ref,
2774 if another dest in I2 is an indirect memory ref. */
2782 /* Make sure this PARALLEL is not an asm. We do not allow combining
2783 that usually (see can_combine_p), so do not here either. */
2793 {
2794 combine_merges++;
2804 /* Replace the dest in I2 with our dest and make the resulting
2805 insn the new pattern for I3. Then skip to where we validate
2806 the pattern. Everything was set up above. */
2811 }
2812 }
2814 /* If I2 is setting a pseudo to a constant and I3 is setting some
2815 sub-part of it to another constant, merge them by making a new
2816 constant. */
2823 {
2829 {
2832 {
2838 }
2839 }
2840 else
2841 {
2846 }
2849 {
2850 /* If this is the low part, we're done. */
2852 ;
2853 /* Handle the case where inner is twice the size of outer. */
2857 /* Otherwise give up for now. */
2858 else
2860 }
2863 {
2867 wide_int o
2872 combine_merges++;
2879 /* Replace the source in I2 with the new constant and make the
2880 resulting insn the new pattern for I3. Then skip to where we
2881 validate the pattern. Everything was set up above. */
2887 /* The dest of I3 has been replaced with the dest of I2. */
2890 }
2891 }
2893 #ifndef HAVE_cc0
2894 /* If we have no I1 and I2 looks like:
2895 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2896 (set Y OP)])
2897 make up a dummy I1 that is
2898 (set Y OP)
2899 and change I2 to be
2900 (set (reg:CC X) (compare:CC Y (const_int 0)))
2902 (We can ignore any trailing CLOBBERs.)
2904 This undoes a previous combination and allows us to match a branch-and-
2905 decrement insn. */
2917 {
2918 /* We make I1 with the same INSN_UID as I2. This gives it
2919 the same DF_INSN_LUID for value tracking. Our fake I1 will
2920 never appear in the insn stream so giving it the same INSN_UID
2921 as I2 will not cause a problem. */
2934 }
2936 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2937 make those two SETs separate I1 and I2 insns, and make an I0 that is
2938 the original I1. */
2944 {
2945 /* If there is no I1, there is no I0 either. */
2948 /* We make I1 with the same INSN_UID as I2. This gives it
2949 the same DF_INSN_LUID for value tracking. Our fake I1 will
2950 never appear in the insn stream so giving it the same INSN_UID
2951 as I2 will not cause a problem. */
2959 }
2960 #endif
2962 /* Verify that I2 and I1 are valid for combining. */
2968 {
2971 }
2973 /* Record whether I2DEST is used in I2SRC and similarly for the other
2974 cases. Knowing this will help in register status updating below. */
2985 /* For the earlier insns, determine which of the subsequent ones they
2986 feed. */
2993 /* Ensure that I3's pattern can be the destination of combines. */
2999 {
3002 }
3004 /* See if any of the insns is a MULT operation. Unless one is, we will
3005 reject a combination that is, since it must be slower. Be conservative
3006 here. */
3014 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3015 We used to do this EXCEPT in one case: I3 has a post-inc in an
3016 output operand. However, that exception can give rise to insns like
3017 mov r3,(r3)+
3018 which is a famous insn on the PDP-11 where the value of r3 used as the
3019 source was model-dependent. Avoid this sort of thing. */
3021 #if 0
3027 /* It's not the exception. */
3028 #endif
3029 #ifdef AUTO_INC_DEC
3030 {
3031 rtx link;
3037 {
3040 }
3041 }
3042 #endif
3044 /* See if the SETs in I1 or I2 need to be kept around in the merged
3045 instruction: whenever the value set there is still needed past I3.
3046 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3048 For the SET in I1, we have two cases: if I1 and I2 independently feed
3049 into I3, the set in I1 needs to be kept around unless I1DEST dies
3050 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3051 in I1 needs to be kept around unless I1DEST dies or is set in either
3052 I2 or I3. The same considerations apply to I0. */
3059 else
3067 else
3070 /* We are about to copy insns for the case where they need to be kept
3071 around. Check that they can be copied in the merged instruction. */
3077 {
3080 }
3082 /* If the set in I2 needs to be kept around, we must make a copy of
3083 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3084 PATTERN (I2), we are only substituting for the original I1DEST, not into
3085 an already-substituted copy. This also prevents making self-referential
3086 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3087 I2DEST. */
3090 {
3093 else
3095 }
3098 {
3101 else
3103 }
3106 {
3109 else
3111 }
3113 combine_merges++;
3115 /* Substitute in the latest insn for the regs set by the earlier ones. */
3121 #ifndef HAVE_cc0
3122 /* Many machines that don't use CC0 have insns that can both perform an
3123 arithmetic operation and set the condition code. These operations will
3124 be represented as a PARALLEL with the first element of the vector
3125 being a COMPARE of an arithmetic operation with the constant zero.
3126 The second element of the vector will set some pseudo to the result
3127 of the same arithmetic operation. If we simplify the COMPARE, we won't
3128 match such a pattern and so will generate an extra insn. Here we test
3129 for this case, where both the comparison and the operation result are
3130 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3131 I2SRC. Later we will make the PARALLEL that contains I2. */
3137 {
3138 rtx newpat_dest;
3152 {
3157 }
3159 /* Do the rest only if op1 is const0_rtx, which may be the
3160 result of simplification. */
3162 {
3163 /* If a single use of the CC is found, prepare to modify it
3164 when SELECT_CC_MODE returns a new CC-class mode, or when
3165 the above simplify_compare_const() returned a new comparison
3166 operator. undobuf.other_insn is assigned the CC use insn
3167 when modifying it. */
3169 {
3170 #ifdef SELECT_CC_MODE
3171 machine_mode new_mode
3176 {
3181 else
3182 {
3185 }
3186 }
3187 #endif
3188 /* Cases for modifying the CC-using comparison. */
3190 /* ??? Do we need to verify the zero rtx? */
3192 {
3193 /* Replace cc_use_loc with entire new RTX. */
3198 }
3200 {
3201 /* Just replace the CC reg with a new mode. */
3204 }
3205 }
3207 /* Now we modify the current newpat:
3208 First, SET_DEST(newpat) is updated if the CC mode has been
3209 altered. For targets without SELECT_CC_MODE, this should be
3210 optimized away. */
3213 /* This is always done to propagate i2src into newpat. */
3216 /* Create new version of i2pat if needed; the below PARALLEL
3217 creation needs this to work correctly. */
3221 }
3222 }
3223 #endif
3226 {
3227 /* It is possible that the source of I2 or I1 may be performing
3228 an unneeded operation, such as a ZERO_EXTEND of something
3229 that is known to have the high part zero. Handle that case
3230 by letting subst look at the inner insns.
3232 Another way to do this would be to have a function that tries
3233 to simplify a single insn instead of merging two or more
3234 insns. We don't do this because of the potential of infinite
3235 loops and because of the potential extra memory required.
3236 However, doing it the way we are is a bit of a kludge and
3237 doesn't catch all cases.
3239 But only do this if -fexpensive-optimizations since it slows
3240 things down and doesn't usually win.
3242 This is not done in the COMPARE case above because the
3243 unmodified I2PAT is used in the PARALLEL and so a pattern
3244 with a modified I2SRC would not match. */
3247 {
3248 /* Pass pc_rtx so no substitutions are done, just
3249 simplifications. */
3251 {
3254 }
3258 }
3263 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3264 copy of I2SRC each time we substitute it, in order to avoid creating
3265 self-referential RTL when we will be substituting I1SRC for I1DEST
3266 later. Likewise if I0 feeds into I2, either directly or indirectly
3267 through I1, and I0DEST is in I0SRC. */
3274 /* Record whether I2's body now appears within I3's body. */
3276 }
3278 /* If we already got a failure, don't try to do more. Otherwise, try to
3279 substitute I1 if we have it. */
3282 {
3283 /* Check that an autoincrement side-effect on I1 has not been lost.
3284 This happens if I1DEST is mentioned in I2 and dies there, and
3285 has disappeared from the new pattern. */
3287 && i1_feeds_i2_n
3290 /* Before we can do this substitution, we must redo the test done
3291 above (see detailed comments there) that ensures I1DEST isn't
3292 mentioned in any SETs in NEWPAT that are field assignments. */
3295 {
3298 }
3303 /* If the following substitution will modify I1SRC, make a copy of it
3304 for the case where it is substituted for I1DEST in I2PAT later. */
3308 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3309 copy of I1SRC each time we substitute it, in order to avoid creating
3310 self-referential RTL when we will be substituting I0SRC for I0DEST
3311 later. */
3316 /* Record whether I1's body now appears within I3's body. */
3318 }
3320 /* Likewise for I0 if we have it. */
3323 {
3330 {
3333 }
3335 /* If the following substitution will modify I0SRC, make a copy of it
3336 for the case where it is substituted for I0DEST in I1PAT later. */
3339 /* And a copy for I0DEST in I2PAT substitution. */
3348 }
3350 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3351 to count all the ways that I2SRC and I1SRC can be used. */
3362 /* Fail if we tried to make a new register. */
3364 /* Fail if we couldn't do something and have a CLOBBER. */
3366 /* Fail if this new pattern is a MULT and we didn't have one before
3367 at the outer level. */
3370 {
3373 }
3375 /* If the actions of the earlier insns must be kept
3376 in addition to substituting them into the latest one,
3377 we must make a new PARALLEL for the latest insn
3378 to hold additional the SETs. */
3381 {
3383 combine_extras++;
3386 {
3392 }
3393 else
3394 {
3399 }
3405 {
3411 }
3413 {
3422 }
3423 }
3425 validate_replacement:
3427 /* Note which hard regs this insn has as inputs. */
3430 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3431 consider splitting this pattern, we might need these clobbers. */
3434 {
3440 }
3442 /* We have recognized nothing yet. */
3445 /* See if this is a PARALLEL of two SETs where one SET's destination is
3446 a register that is unused and this isn't marked as an instruction that
3447 might trap in an EH region. In that case, we just need the other SET.
3448 We prefer this over the PARALLEL.
3450 This can occur when simplifying a divmod insn. We *must* test for this
3451 case here because the code below that splits two independent SETs doesn't
3452 handle this case correctly when it updates the register status.
3454 It's pointless doing this if we originally had two sets, one from
3455 i3, and one from i2. Combining then splitting the parallel results
3456 in the original i2 again plus an invalid insn (which we delete).
3457 The net effect is only to move instructions around, which makes
3458 debug info less accurate. */
3463 {
3474 {
3477 }
3486 {
3492 }
3496 }
3498 /* Is the result of combination a valid instruction? */
3502 /* If we were combining three insns and the result is a simple SET
3503 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3504 insns. There are two ways to do this. It can be split using a
3505 machine-specific method (like when you have an addition of a large
3506 constant) or by combine in the function find_split_point. */
3510 {
3514 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3515 use I2DEST as a scratch register will help. In the latter case,
3516 convert I2DEST to the mode of the source of NEWPAT if we can. */
3520 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3521 inputs of NEWPAT. */
3523 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3524 possible to try that as a scratch reg. This would require adding
3525 more code to make it work though. */
3528 {
3531 /* First try to split using the original register as a
3532 scratch register. */
3536 i2dest)));
3539 /* If that didn't work, try changing the mode of I2DEST if
3540 we can. */
3545 {
3547 rtx ni2dest;
3551 else
3552 {
3555 }
3557 parallel = (gen_rtx_PARALLEL
3561 ni2dest))));
3566 {
3574 }
3575 }
3578 }
3580 /* If recog_for_combine has discarded clobbers, try to use them
3581 again for the split. */
3583 {
3586 }
3589 {
3594 }
3598 {
3608 /* If I2 or I3 has multiple SETs, we won't know how to track
3609 register status, so don't use these insns. If I2's destination
3610 is used between I2 and I3, we also can't use these insns. */
3620 /* It is possible that both insns now set the destination of I3.
3621 If so, we must show an extra use of it. */
3624 {
3643 }
3644 }
3646 /* If we can split it and use I2DEST, go ahead and see if that
3647 helps things be recognized. Verify that none of the registers
3648 are set between I2 and I3. */
3651 #ifdef HAVE_cc0
3653 #endif
3654 /* We need I2DEST in the proper mode. If it is a hard register
3655 or the only use of a pseudo, we can change its mode.
3656 Make sure we don't change a hard register to have a mode that
3657 isn't valid for it, or change the number of registers. */
3664 /* We can't overwrite I2DEST if its value is still used by
3665 NEWPAT. */
3667 {
3676 /* *SPLIT may be part of I2SRC, so make sure we have the
3677 original expression around for later debug processing.
3678 We should not need I2SRC any more in other cases. */
3681 else
3684 /* Get NEWDEST as a register in the proper mode. We have already
3685 validated that we can do this. */
3687 {
3690 else
3691 {
3694 }
3695 }
3697 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3698 an ASHIFT. This can occur if it was inside a PLUS and hence
3699 appeared to be a memory address. This is a kludge. */
3704 {
3707 /* Update split_code because we may not have a multiply
3708 anymore. */
3710 }
3712 #ifdef INSN_SCHEDULING
3713 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3714 be written as a ZERO_EXTEND. */
3716 {
3717 #ifdef LOAD_EXTEND_OP
3718 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3719 what it really is. */
3724 else
3725 #endif
3728 }
3729 #endif
3731 /* Attempt to split binary operators using arithmetic identities. */
3735 {
3742 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3744 {
3749 }
3750 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3757 {
3763 /* Split both "((X op Y) op X) op Y" and
3764 "((X op Y) op Y) op X" as "T op T" where T is
3765 "X op Y". */
3768 {
3774 }
3775 /* Split "((X op X) op Y) op Y)" as "T op T" where
3776 T is "X op Y". */
3778 {
3784 }
3785 }
3786 }
3789 {
3792 }
3796 /* recog_for_combine might have added CLOBBERs to newi2pat.
3797 Make sure NEWPAT does not depend on the clobbered regs. */
3801 {
3804 {
3807 }
3808 }
3810 /* If the split point was a MULT and we didn't have one before,
3811 don't use one now. */
3814 }
3815 }
3817 /* Check for a case where we loaded from memory in a narrow mode and
3818 then sign extended it, but we need both registers. In that case,
3819 we have a PARALLEL with both loads from the same memory location.
3820 We can split this into a load from memory followed by a register-register
3821 copy. This saves at least one insn, more if register allocation can
3822 eliminate the copy.
3824 We cannot do this if the destination of the first assignment is a
3825 condition code register or cc0. We eliminate this case by making sure
3826 the SET_DEST and SET_SRC have the same mode.
3828 We cannot do this if the destination of the second assignment is
3829 a register that we have already assumed is zero-extended. Similarly
3830 for a SUBREG of such a register. */
3865 {
3866 rtx ni2dest;
3880 }
3882 /* Similarly, check for a case where we have a PARALLEL of two independent
3883 SETs but we started with three insns. In this case, we can do the sets
3884 as two separate insns. This case occurs when some SET allows two
3885 other insns to combine, but the destination of that SET is still live.
3887 Also do this if we started with two insns and (at least) one of the
3888 resulting sets is a noop; this noop will be deleted later. */
3907 {
3911 /* Normally, it doesn't matter which of the two is done first,
3912 but the one that references cc0 can't be the second, and
3913 one which uses any regs/memory set in between i2 and i3 can't
3914 be first. The PARALLEL might also have been pre-existing in i3,
3915 so we need to make sure that we won't wrongly hoist a SET to i2
3916 that would conflict with a death note present in there. */
3923 #ifdef HAVE_cc0
3925 #endif
3926 /* If I3 is a jump, ensure that set0 is a jump so that
3927 we do not create invalid RTL. */
3929 )
3930 {
3933 }
3940 #ifdef HAVE_cc0
3942 #endif
3943 /* If I3 is a jump, ensure that set1 is a jump so that
3944 we do not create invalid RTL. */
3946 )
3947 {
3950 }
3951 else
3952 {
3955 }
3960 {
3961 /* recog_for_combine might have added CLOBBERs to newi2pat.
3962 Make sure NEWPAT does not depend on the clobbered regs. */
3964 {
3967 {
3970 {
3973 }
3974 }
3975 }
3978 }
3979 }
3981 /* If it still isn't recognized, fail and change things back the way they
3982 were. */
3984 /* Is the result a reasonable ASM_OPERANDS? */
3986 {
3989 }
3991 /* If we had to change another insn, make sure it is valid also. */
3993 {
4001 {
4004 }
4005 }
4007 #ifdef HAVE_cc0
4008 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4009 they are adjacent to each other or not. */
4010 {
4014 {
4017 }
4018 }
4019 #endif
4021 /* Only allow this combination if insn_rtx_costs reports that the
4022 replacement instructions are cheaper than the originals. */
4024 {
4027 }
4030 {
4035 {
4040 /* Temporarily revert mode back. */
4044 {
4045 /* If we used i2dest as a scratch register with a
4046 different mode, substitute it for the original
4047 i2src while its original mode is temporarily
4048 restored, and then clear i2scratch so that we don't
4049 do it again later. */
4051 this_basic_block);
4053 /* Put back the new mode. */
4055 }
4056 else
4057 {
4062 {
4065 }
4066 else
4067 {
4074 }
4076 /* We're dealing with a reg that changed mode but not
4077 meaning, so we want to turn it into a subreg for
4078 the new mode. However, because of REG sharing and
4079 because its mode had already changed, we have to do
4080 it in two steps. First, replace any debug uses of
4081 reg, with its original mode temporarily restored,
4082 with this copy we have created; then, replace the
4083 copy with the SUBREG of the original shared reg,
4084 once again changed to the new mode. */
4086 this_basic_block);
4090 this_basic_block);
4091 }
4092 }
4093 }
4095 /* If we will be able to accept this, we have made a
4096 change to the destination of I3. This requires us to
4097 do a few adjustments. */
4100 {
4103 }
4105 /* We now know that we can do this combination. Merge the insns and
4106 update the status of registers and LOG_LINKS. */
4109 {
4114 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4115 ensure that they are still valid. Then add any non-duplicate
4116 notes added by recog_for_combine. */
4118 {
4128 }
4132 NULL_RTX);
4133 }
4136 {
4139 rtx ni2dest;
4141 /* I3 now uses what used to be its destination and which is now
4142 I2's destination. This requires us to do a few adjustments. */
4146 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4147 so we still will.
4149 However, some later insn might be using I2's dest and have
4150 a LOG_LINK pointing at I3. We must remove this link.
4151 The simplest way to remove the link is to point it at I1,
4152 which we know will be a NOTE. */
4154 /* newi2pat is usually a SET here; however, recog_for_combine might
4155 have added some clobbers. */
4158 else
4165 {
4167 {
4173 }
4174 }
4175 }
4177 {
4182 /* Compute which registers we expect to eliminate. newi2pat may be setting
4183 either i3dest or i2dest, so we must check it. */
4186 || !i2dest_killed
4188 /* For i1, we need to compute both local elimination and global
4189 elimination information with respect to newi2pat because i1dest
4190 may be the same as i3dest, in which case newi2pat may be setting
4191 i1dest. Global information is used when distributing REG_DEAD
4192 note for i2 and i3, in which case it does matter if newi2pat sets
4193 i1dest or not.
4195 Local information is used when distributing REG_DEAD note for i1,
4196 in which case it doesn't matter if newi2pat sets i1dest or not.
4197 See PR62151, if we have four insns combination:
4198 i0: r0 <- i0src
4199 i1: r1 <- i1src (using r0)
4200 REG_DEAD (r0)
4201 i2: r0 <- i2src (using r1)
4202 i3: r3 <- i3src (using r0)
4203 ix: using r0
4204 From i1's point of view, r0 is eliminated, no matter if it is set
4205 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4206 should be discarded.
4208 Note local information only affects cases in forms like "I1->I2->I3",
4209 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4210 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4211 i0dest anyway. */
4213 || !i1dest_killed
4218 /* Same case as i1. */
4225 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4226 clear them. */
4234 /* Ensure that we do not have something that should not be shared but
4235 occurs multiple times in the new insns. Check this by first
4236 resetting all the `used' flags and then copying anything is shared. */
4260 {
4267 {
4268 /* I2SRC must still be meaningful at this point. Some splitting
4269 operations can invalidate I2SRC, but those operations do not
4270 apply to calls. */
4273 }
4281 }
4286 /* We had one special case above where I2 had more than one set and
4287 we replaced a destination of one of those sets with the destination
4288 of I3. In that case, we have to update LOG_LINKS of insns later
4289 in this basic block. Note that this (expensive) case is rare.
4291 Also, in this case, we must pretend that all REG_NOTEs for I2
4292 actually came from I3, so that REG_UNUSED notes from I2 will be
4293 properly handled. */
4296 {
4305 temp_insn
4315 {
4320 }
4321 else
4324 }
4332 {
4335 this_basic_block);
4338 }
4339 else
4340 {
4343 this_basic_block);
4345 }
4348 {
4353 this_basic_block);
4355 }
4358 {
4363 this_basic_block);
4365 }
4367 /* Get death notes for everything that is now used in either I3 or
4368 I2 and used to die in a previous insn. If we built two new
4369 patterns, move from I1 to I2 then I2 to I3 so that we get the
4370 proper movement on registers that I2 modifies. */
4376 else
4382 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4399 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4400 know these are REG_UNUSED and want them to go to the desired insn,
4401 so we always pass it as i3. */
4405 NULL_RTX);
4409 NULL_RTX);
4411 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4412 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4413 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4414 in that case, it might delete I2. Similarly for I2 and I1.
4415 Show an additional death due to the REG_DEAD note we make here. If
4416 we discard it in distribute_notes, we will decrement it again. */
4419 {
4424 else
4427 }
4430 {
4435 else
4438 }
4441 {
4446 else
4449 }
4452 {
4457 else
4460 }
4468 {
4473 /* The insn that used to set this register doesn't exist, and
4474 this life of the register may not exist either. See if one of
4475 I3's links points to an insn that sets I2DEST. If it does,
4476 that is now the last known value for I2DEST. If we don't update
4477 this and I2 set the register to a value that depended on its old
4478 contents, we will get confused. If this insn is used, thing
4479 will be set correctly in combine_instructions. */
4487 /* If the reg formerly set in I2 died only once and that was in I3,
4488 zero its use count so it won't make `reload' do any work. */
4491 && ! i2dest_in_i2src
4494 }
4497 {
4510 && ! i1dest_in_i1src
4513 }
4516 {
4529 && ! i0dest_in_i0src
4532 }
4534 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4535 been made to this insn. The order is important, because newi2pat
4536 can affect nonzero_bits of newpat. */
4540 }
4543 {
4545 {
4548 }
4550 }
4553 {
4555 {
4558 }
4560 }
4563 {
4565 {
4568 }
4570 }
4573 {
4575 {
4578 }
4580 }
4583 {
4585 {
4588 }
4590 }
4592 /* Set new_direct_jump_p if a new return or simple jump instruction
4593 has been created. Adjust the CFG accordingly. */
4595 {
4599 }
4604 {
4607 }
4609 /* A noop might also need cleaning up of CFG, if it comes from the
4610 simplification of a jump. */
4615 {
4618 }
4625 {
4628 }
4630 combine_successes++;
4637 else
4639 }
4640 \f
4641 /* Undo all the modifications recorded in undobuf. */
4643 static void
4645 {
4649 {
4652 {
4667 }
4671 }
4674 }
4676 /* We've committed to accepting the changes we made. Move all
4677 of the undos to the free list. */
4679 static void
4681 {
4685 {
4689 }
4691 }
4692 \f
4693 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4694 where we have an arithmetic expression and return that point. LOC will
4695 be inside INSN.
4697 try_combine will call this function to see if an insn can be split into
4698 two insns. */
4702 {
4711 /* First special-case some codes. */
4713 {
4715 #ifdef INSN_SCHEDULING
4716 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4717 point. */
4720 #endif
4724 #ifdef HAVE_lo_sum
4725 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4726 using LO_SUM and HIGH. */
4729 {
4737 }
4738 #endif
4740 /* If we have a PLUS whose second operand is a constant and the
4741 address is not valid, perhaps will can split it up using
4742 the machine-specific way to split large constants. We use
4743 the first pseudo-reg (one of the virtual regs) as a placeholder;
4744 it will not remain in the result. */
4749 {
4753 subst_insn);
4755 /* This should have produced two insns, each of which sets our
4756 placeholder. If the source of the second is a valid address,
4757 we can make put both sources together and make a split point
4758 in the middle. */
4771 && memory_address_addr_space_p
4774 {
4778 /* Replace the placeholder in SRC2 with SRC1. If we can
4779 find where in SRC2 it was placed, that can become our
4780 split point and we can replace this address with SRC2.
4781 Just try two obvious places. */
4792 {
4795 }
4796 }
4798 /* If that didn't work, perhaps the first operand is complex and
4799 needs to be computed separately, so make a split point there.
4800 This will occur on machines that just support REG + CONST
4801 and have a constant moved through some previous computation. */
4807 }
4809 /* If we have a PLUS whose first operand is complex, try computing it
4810 separately by making a split there. */
4821 #ifdef HAVE_cc0
4822 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4823 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4824 we need to put the operand into a register. So split at that
4825 point. */
4834 #endif
4836 /* See if we can split SET_SRC as it stands. */
4841 /* See if we can split SET_DEST as it stands. */
4846 /* See if this is a bitfield assignment with everything constant. If
4847 so, this is an IOR of an AND, so split it into that. */
4857 {
4863 unsigned HOST_WIDE_INT mask
4865 rtx or_mask;
4874 else
4875 {
4881 or_mask));
4882 }
4889 }
4891 /* Otherwise, see if this is an operation that we can split into two.
4892 If so, try to split that. */
4896 {
4898 /* If we are AND'ing with a large constant that is only a single
4899 bit and the result is only being used in a context where we
4900 need to know if it is zero or nonzero, replace it with a bit
4901 extraction. This will avoid the large constant, which might
4902 have taken more than one insn to make. If the constant were
4903 not a valid argument to the AND but took only one insn to make,
4904 this is no worse, but if it took more than one insn, it will
4905 be better. */
4915 {
4920 {
4923 }
4924 }
4928 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4929 is known to be on, this can be converted into a NEG of a shift. */
4935 {
4947 }
4953 /* We can't optimize if either mode is a partial integer
4954 mode as we don't know how many bits are significant
4955 in those modes. */
4969 {
4977 }
4982 }
4986 {
4989 /* For unsigned, we have a choice of a shift followed by an
4990 AND or two shifts. Use two shifts for field sizes where the
4991 constant might be too large. We assume here that we can
4992 always at least get 8-bit constants in an AND insn, which is
4993 true for every current RISC. */
4996 {
4997 unsigned HOST_WIDE_INT mask
5001 gen_rtx_LSHIFTRT
5009 }
5010 else
5011 {
5013 gen_rtx_fmt_ee
5024 }
5025 }
5027 /* See if this is a simple operation with a constant as the second
5028 operand. It might be that this constant is out of range and hence
5029 could be used as a split point. */
5037 /* Finally, see if this is a simple operation with its first operand
5038 not in a register. The operation might require this operand in a
5039 register, so return it as a split point. We can always do this
5040 because if the first operand were another operation, we would have
5041 already found it as a split point. */
5050 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5051 it is better to write this as (not (ior A B)) so we can split it.
5052 Similarly for IOR. */
5054 {
5062 }
5064 /* Many RISC machines have a large set of logical insns. If the
5065 second operand is a NOT, put it first so we will try to split the
5066 other operand first. */
5068 {
5072 }
5077 /* Canonicalization can produce (minus A (mult B C)), where C is a
5078 constant. It may be better to try splitting (plus (mult B -C) A)
5079 instead if this isn't a multiply by a power of two. */
5083 {
5091 mode)),
5094 }
5096 /* Split at a multiply-accumulate instruction. However if this is
5097 the SET_SRC, we likely do not have such an instruction and it's
5098 worthless to try this split. */
5104 }
5106 /* Otherwise, select our actions depending on our rtx class. */
5108 {
5114 /* ... fall through ... */
5122 /* ... fall through ... */
5124 /* Some machines have (and (shift ...) ...) insns. If X is not
5125 an AND, but XEXP (X, 0) is, use it as our split point. */
5135 /* Otherwise, we don't have a split point. */
5137 }
5138 }
5139 \f
5140 /* Throughout X, replace FROM with TO, and return the result.
5141 The result is TO if X is FROM;
5142 otherwise the result is X, but its contents may have been modified.
5143 If they were modified, a record was made in undobuf so that
5144 undo_all will (among other things) return X to its original state.
5146 If the number of changes necessary is too much to record to undo,
5147 the excess changes are not made, so the result is invalid.
5148 The changes already made can still be undone.
5149 undobuf.num_undo is incremented for such changes, so by testing that
5150 the caller can tell whether the result is valid.
5152 `n_occurrences' is incremented each time FROM is replaced.
5154 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5156 IN_COND is nonzero if we are at the top level of a condition.
5158 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5159 by copying if `n_occurrences' is nonzero. */
5161 static rtx
5163 {
5168 rtx new_rtx;
5170 /* Two expressions are equal if they are identical copies of a shared
5171 RTX or if they are both registers with the same register number
5172 and mode. */
5174 #define COMBINE_RTX_EQUAL_P(X,Y) \
5175 ((X) == (Y) \
5176 || (REG_P (X) && REG_P (Y) \
5177 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5179 /* Do not substitute into clobbers of regs -- this will never result in
5180 valid RTL. */
5185 {
5186 n_occurrences++;
5188 }
5190 /* If X and FROM are the same register but different modes, they
5191 will not have been seen as equal above. However, the log links code
5192 will make a LOG_LINKS entry for that case. If we do nothing, we
5193 will try to rerecognize our original insn and, when it succeeds,
5194 we will delete the feeding insn, which is incorrect.
5196 So force this insn not to match in this (rare) case. */
5201 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5202 of which may contain things that can be combined. */
5206 /* It is possible to have a subexpression appear twice in the insn.
5207 Suppose that FROM is a register that appears within TO.
5208 Then, after that subexpression has been scanned once by `subst',
5209 the second time it is scanned, TO may be found. If we were
5210 to scan TO here, we would find FROM within it and create a
5211 self-referent rtl structure which is completely wrong. */
5215 /* Parallel asm_operands need special attention because all of the
5216 inputs are shared across the arms. Furthermore, unsharing the
5217 rtl results in recognition failures. Failure to handle this case
5218 specially can result in circular rtl.
5220 Solve this by doing a normal pass across the first entry of the
5221 parallel, and only processing the SET_DESTs of the subsequent
5222 entries. Ug. */
5227 {
5230 /* If this substitution failed, this whole thing fails. */
5238 {
5244 {
5247 /* If this substitution failed, this whole thing fails. */
5253 }
5254 }
5255 }
5256 else
5257 {
5261 /* We don't need to process a SET_DEST that is a register, CC0,
5262 or PC, so set up to skip this common case. All other cases
5263 where we want to suppress replacing something inside a
5264 SET_SRC are handled via the IN_DEST operand. */
5271 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5272 constant. */
5277 {
5279 {
5282 {
5284 {
5287 n_occurrences++;
5288 }
5289 else
5290 {
5292 unique_copy);
5294 /* If this substitution failed, this whole thing
5295 fails. */
5299 }
5302 }
5303 }
5305 {
5306 /* If this is a register being set, ignore it. */
5313 ;
5316 {
5317 /* In general, don't install a subreg involving two
5318 modes not tieable. It can worsen register
5319 allocation, and can even make invalid reload
5320 insns, since the reg inside may need to be copied
5321 from in the outside mode, and that may be invalid
5322 if it is an fp reg copied in integer mode.
5324 We allow two exceptions to this: It is valid if
5325 it is inside another SUBREG and the mode of that
5326 SUBREG and the mode of the inside of TO is
5327 tieable and it is valid if X is a SET that copies
5328 FROM to CC0. */
5336 #ifdef HAVE_cc0
5338 #endif
5339 )
5351 n_occurrences++;
5352 }
5353 else
5354 /* If we are in a SET_DEST, suppress most cases unless we
5355 have gone inside a MEM, in which case we want to
5356 simplify the address. We assume here that things that
5357 are actually part of the destination have their inner
5358 parts in the first expression. This is true for SUBREG,
5359 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5360 things aside from REG and MEM that should appear in a
5361 SET_DEST. */
5363 (((in_dest
5369 unique_copy);
5371 /* If we found that we will have to reject this combination,
5372 indicate that by returning the CLOBBER ourselves, rather than
5373 an expression containing it. This will speed things up as
5374 well as prevent accidents where two CLOBBERs are considered
5375 to be equal, thus producing an incorrect simplification. */
5381 {
5389 }
5392 {
5396 }
5397 else
5399 }
5400 }
5401 }
5403 /* Check if we are loading something from the constant pool via float
5404 extension; in this case we would undo compress_float_constant
5405 optimization and degenerate constant load to an immediate value. */
5409 {
5413 }
5415 /* Try to simplify X. If the simplification changed the code, it is likely
5416 that further simplification will help, so loop, but limit the number
5417 of repetitions that will be performed. */
5420 {
5421 /* If X is sufficiently simple, don't bother trying to do anything
5422 with it. */
5431 /* We no longer know the original mode of operand 0 since we
5432 have changed the form of X) */
5434 }
5437 }
5438 \f
5439 /* Simplify X, a piece of RTL. We just operate on the expression at the
5440 outer level; call `subst' to simplify recursively. Return the new
5441 expression.
5443 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5444 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5445 of a condition. */
5447 static rtx
5450 {
5453 rtx temp;
5456 /* If this is a commutative operation, put a constant last and a complex
5457 expression first. We don't need to do this for comparisons here. */
5460 {
5464 }
5466 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5467 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5468 things. Check for cases where both arms are testing the same
5469 condition.
5471 Don't do anything if all operands are very simple. */
5484 {
5489 /* If everything is a comparison, what we have is highly unlikely
5490 to be simpler, so don't use it. */
5493 {
5500 /* Simplify the alternative arms; this may collapse the true and
5501 false arms to store-flag values. Be careful to use copy_rtx
5502 here since true_rtx or false_rtx might share RTL with x as a
5503 result of the if_then_else_cond call above. */
5507 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5508 is unlikely to be simpler. */
5511 {
5514 /* Restarting if we generate a store-flag expression will cause
5515 us to loop. Just drop through in this case. */
5517 /* If the result values are STORE_FLAG_VALUE and zero, we can
5518 just make the comparison operation. */
5529 /* Likewise, we can make the negate of a comparison operation
5530 if the result values are - STORE_FLAG_VALUE and zero. */
5538 mode);
5549 mode);
5550 else
5553 mode,
5554 VOIDmode,
5555 cond,
5556 cop1),
5561 }
5562 }
5563 }
5565 /* Try to fold this expression in case we have constants that weren't
5566 present before. */
5569 {
5577 {
5580 {
5584 }
5587 }
5600 }
5603 {
5608 }
5610 /* First see if we can apply the inverse distributive law. */
5613 {
5617 }
5619 /* If CODE is an associative operation not otherwise handled, see if we
5620 can associate some operands. This can win if they are constants or
5621 if they are logically related (i.e. (a & b) & a). */
5627 {
5629 {
5633 rtx inner;
5635 /* Make sure we pass the constant operand if any as the second
5636 one if this is a commutative operation. */
5638 {
5642 }
5648 /* For commutative operations, try the other pair if that one
5649 didn't simplify. */
5651 {
5656 }
5660 }
5661 }
5663 /* A little bit of algebraic simplification here. */
5665 {
5667 /* Ensure that our address has any ASHIFTs converted to MULT in case
5668 address-recognizing predicates are called later. */
5677 /* See if this can be moved to simplify_subreg. */
5680 /* Don't call gen_lowpart if the inner mode
5681 is VOIDmode and we cannot simplify it, as SUBREG without
5682 inner mode is invalid. */
5689 {
5690 rtx temp;
5696 /* If op is known to have all lower bits zero, the result is zero. */
5706 }
5708 /* Don't change the mode of the MEM if that would change the meaning
5709 of the address. */
5716 /* Note that we cannot do any narrowing for non-constants since
5717 we might have been counting on using the fact that some bits were
5718 zero. We now do this in the SET. */
5725 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5726 replaced by (lshiftrt X C). This will convert
5727 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5735 /* If X has only a single bit that might be nonzero, say, bit I, convert
5736 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5737 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5738 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5739 or a SUBREG of one since we'd be making the expression more
5740 complex if it was just a register. */
5746 {
5747 rtx temp1 = simplify_shift_const
5753 /* If all we did was surround TEMP with the two shifts, we
5754 haven't improved anything, so don't use it. Otherwise,
5755 we are better off with TEMP1. */
5760 }
5764 /* We can't handle truncation to a partial integer mode here
5765 because we don't know the real bitsize of the partial
5766 integer mode. */
5775 /* We can truncate a constant value and return it. */
5779 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5780 whose value is a comparison can be replaced with a subreg if
5781 STORE_FLAG_VALUE permits. */
5790 /* (const (const X)) can become (const X). Do it this way rather than
5791 returning the inner CONST since CONST can be shared with a
5792 REG_EQUAL note. */
5797 #ifdef HAVE_lo_sum
5799 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5800 can add in an offset. find_split_point will split this address up
5801 again if it doesn't match. */
5806 #endif
5809 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5810 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5811 bit-field and can be replaced by either a sign_extend or a
5812 sign_extract. The `and' may be a zero_extend and the two
5813 <c>, -<c> constants may be reversed. */
5828 return simplify_shift_const
5835 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5836 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5837 the bitsize of the mode - 1. This allows simplification of
5838 "a = (b & 8) == 0;" */
5850 /* If we are adding two things that have no bits in common, convert
5851 the addition into an IOR. This will often be further simplified,
5852 for example in cases like ((a & 1) + (a & 2)), which can
5853 become a & 3. */
5858 {
5859 /* Try to simplify the expression further. */
5863 /* If we could, great. If not, do not go ahead with the IOR
5864 replacement, since PLUS appears in many special purpose
5865 address arithmetic instructions. */
5873 }
5877 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5878 (and <foo> (const_int pow2-1)) */
5888 /* If we have (mult (plus A B) C), apply the distributive law and then
5889 the inverse distributive law to see if things simplify. This
5890 occurs mostly in addresses, often when unrolling loops. */
5893 {
5897 }
5899 /* Try simplify a*(b/c) as (a*b)/c. */
5902 {
5908 }
5912 /* If this is a divide by a power of two, treat it as a shift if
5913 its first operand is a shift. */
5931 /* If the first operand is a condition code, we can't do anything
5932 with it. */
5936 {
5944 /* Simplify our comparison, if possible. */
5947 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5948 if only the low-order bit is possibly nonzero in X (such as when
5949 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5950 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5951 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5952 (plus X 1).
5954 Remove any ZERO_EXTRACT we made when thinking this was a
5955 comparison. It may now be simpler to use, e.g., an AND. If a
5956 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5957 the call to make_compound_operation in the SET case.
5959 Don't apply these optimizations if the caller would
5960 prefer a comparison rather than a value.
5961 E.g., for the condition in an IF_THEN_ELSE most targets need
5962 an explicit comparison. */
5965 ;
5981 {
5985 mode);
5986 }
5993 {
5997 const1_rtx);
5998 }
6006 {
6009 }
6011 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6012 those above. */
6014 ;
6030 {
6034 mode);
6035 }
6043 {
6047 mode);
6048 }
6050 /* If X is 0/1, (eq X 0) is X-1. */
6056 {
6059 }
6061 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6062 one bit that might be nonzero, we can convert (ne x 0) to
6063 (ashift x c) where C puts the bit in the sign bit. Remove any
6064 AND with STORE_FLAG_VALUE when we are done, since we are only
6065 going to test the sign bit. */
6072 {
6078 else
6080 }
6082 /* If the code changed, return a whole new comparison.
6083 We also need to avoid using SUBST in cases where
6084 simplify_comparison has widened a comparison with a CONST_INT,
6085 since in that case the wider CONST_INT may fail the sanity
6086 checks in do_SUBST. */
6093 /* Otherwise, keep this operation, but maybe change its operands.
6094 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6097 }
6107 /* If we are processing SET_DEST, we are done. */
6125 /* If this is a shift by a constant amount, simplify it. */
6141 }
6144 }
6145 \f
6146 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6148 static rtx
6150 {
6157 rtx temp;
6160 rtx reversed;
6162 /* Simplify storing of the truth value. */
6167 /* Also when the truth value has to be reversed. */
6173 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6174 in it is being compared against certain values. Get the true and false
6175 comparisons and see if that says anything about the value of each arm. */
6181 {
6182 HOST_WIDE_INT nzb;
6188 /* If FALSE_CODE is EQ, swap the codes and arms. */
6191 {
6194 }
6196 /* If we are comparing against zero and the expression being tested has
6197 only a single bit that might be nonzero, that is its value when it is
6198 not equal to zero. Similarly if it is known to be -1 or 0. */
6202 {
6205 }
6209 {
6212 }
6214 /* Now simplify an arm if we know the value of the register in the
6215 branch and it is used in the arm. Be careful due to the potential
6216 of locally-shared RTL. */
6233 }
6235 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6236 reversed, do so to avoid needing two sets of patterns for
6237 subtract-and-branch insns. Similarly if we have a constant in the true
6238 arm, the false arm is the same as the first operand of the comparison, or
6239 the false arm is more complicated than the true arm. */
6252 {
6261 /* It is possible that the conditional has been simplified out. */
6264 }
6266 /* If the two arms are identical, we don't need the comparison. */
6271 /* Convert a == b ? b : a to "a". */
6283 /* Look for cases where we have (abs x) or (neg (abs X)). */
6286 && comparison_p
6293 {
6299 return
6302 mode);
6305 }
6307 /* Look for MIN or MAX. */
6310 && comparison_p
6315 {
6330 }
6332 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6333 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6334 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6335 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6336 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6337 neither 1 or -1, but it isn't worth checking for. */
6340 && comparison_p
6343 {
6359 /* If an identity-zero op is commutative, check whether there
6360 would be a match if we swapped the operands. */
6380 {
6384 }
6396 {
6400 }
6416 {
6420 }
6432 {
6436 }
6439 {
6445 const_true_rtx));
6453 }
6454 }
6456 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6457 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6458 negation of a single bit, we can convert this operation to a shift. We
6459 can actually do this more generally, but it doesn't seem worth it. */
6468 return
6472 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6482 }
6483 \f
6484 /* Simplify X, a SET expression. Return the new expression. */
6486 static rtx
6488 {
6491 machine_mode mode
6496 /* (set (pc) (return)) gets written as (return). */
6500 /* Now that we know for sure which bits of SRC we are using, see if we can
6501 simplify the expression for the object knowing that we only need the
6502 low-order bits. */
6505 {
6508 }
6510 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6511 the comparison result and try to simplify it unless we already have used
6512 undobuf.other_insn. */
6520 {
6529 {
6532 {
6535 }
6536 }
6537 else
6545 {
6549 }
6550 else
6551 {
6556 /* Attempt to simplify CC user. */
6558 {
6562 }
6564 /* Convert X into a no-op move. */
6568 }
6570 /* Simplify our comparison, if possible. */
6573 #ifdef SELECT_CC_MODE
6574 /* If this machine has CC modes other than CCmode, check to see if we
6575 need to use a different CC mode here. */
6584 else
6587 #ifndef HAVE_cc0
6588 /* If the mode changed, we have to change SET_DEST, the mode in the
6589 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6590 a hard register, just build new versions with the proper mode. If it
6591 is a pseudo, we lose unless it is only time we set the pseudo, in
6592 which case we can safely change its mode. */
6594 {
6596 {
6598 rtx new_dest;
6602 else
6603 {
6606 }
6613 }
6614 }
6618 /* If the code changed, we have to build a new comparison in
6619 undobuf.other_insn. */
6621 {
6630 /* If the only change we made was to change an EQ into an NE or
6631 vice versa, OP0 has only one bit that might be nonzero, and OP1
6632 is zero, check if changing the user of the condition code will
6633 produce a valid insn. If it won't, we can keep the original code
6634 in that insn by surrounding our operation with an XOR. */
6641 {
6646 {
6653 }
6654 }
6655 }
6660 /* Otherwise, if we didn't previously have a COMPARE in the
6661 correct mode, we need one. */
6663 {
6666 }
6668 {
6671 }
6672 /* Otherwise, update the COMPARE if needed. */
6674 {
6677 }
6678 }
6679 else
6680 {
6681 /* Get SET_SRC in a form where we have placed back any
6682 compound expressions. Then do the checks below. */
6685 }
6687 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6688 and X being a REG or (subreg (reg)), we may be able to convert this to
6689 (set (subreg:m2 x) (op)).
6691 We can always do this if M1 is narrower than M2 because that means that
6692 we only care about the low bits of the result.
6694 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6695 perform a narrower operation than requested since the high-order bits will
6696 be undefined. On machine where it is defined, this transformation is safe
6697 as long as M1 and M2 have the same number of words. */
6705 #ifndef WORD_REGISTER_OPERATIONS
6708 #endif
6709 #ifdef CANNOT_CHANGE_MODE_CLASS
6714 #endif
6718 {
6721 dest));
6725 }
6727 #ifdef HAVE_cc0
6728 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6729 in SRC. */
6735 {
6739 /* Here we make sure that we don't have a sign bit on. */
6742 {
6745 }
6746 }
6747 #endif
6749 #ifdef LOAD_EXTEND_OP
6750 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6751 would require a paradoxical subreg. Replace the subreg with a
6752 zero_extend to avoid the reload that would otherwise be required. */
6760 {
6766 }
6767 #endif
6769 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6770 are comparing an item known to be 0 or -1 against 0, use a logical
6771 operation instead. Check for one of the arms being an IOR of the other
6772 arm with some value. We compute three terms to be IOR'ed together. In
6773 practice, at most two will be nonzero. Then we do the IOR's. */
6781 #ifdef HAVE_conditional_move
6783 #endif
6788 {
6814 false_rtx);
6820 term3));
6823 }
6825 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6826 whole thing fail. */
6831 else
6832 /* Convert this into a field assignment operation, if possible. */
6834 }
6835 \f
6836 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6837 result. */
6839 static rtx
6841 {
6847 {
6849 /* We can call simplify_and_const_int only if we don't lose
6850 any (sign) bits when converting INTVAL (op1) to
6851 "unsigned HOST_WIDE_INT". */
6855 {
6862 }
6864 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6865 apply the distributive law and then the inverse distributive
6866 law to see if things simplify. */
6868 {
6872 }
6874 {
6878 }
6882 /* If we have (ior (and A B) C), apply the distributive law and then
6883 the inverse distributive law to see if things simplify. */
6886 {
6890 }
6893 {
6897 }
6902 }
6905 }
6906 \f
6907 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6908 operations" because they can be replaced with two more basic operations.
6909 ZERO_EXTEND is also considered "compound" because it can be replaced with
6910 an AND operation, which is simpler, though only one operation.
6912 The function expand_compound_operation is called with an rtx expression
6913 and will convert it to the appropriate shifts and AND operations,
6914 simplifying at each stage.
6916 The function make_compound_operation is called to convert an expression
6917 consisting of shifts and ANDs into the equivalent compound expression.
6918 It is the inverse of this function, loosely speaking. */
6920 static rtx
6922 {
6926 rtx tem;
6929 {
6933 /* We can't necessarily use a const_int for a multiword mode;
6934 it depends on implicitly extending the value.
6935 Since we don't know the right way to extend it,
6936 we can't tell whether the implicit way is right.
6938 Even for a mode that is no wider than a const_int,
6939 we can't win, because we need to sign extend one of its bits through
6940 the rest of it, and we don't know which bit. */
6944 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6945 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6946 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6947 reloaded. If not for that, MEM's would very rarely be safe.
6949 Reject MODEs bigger than a word, because we might not be able
6950 to reference a two-register group starting with an arbitrary register
6951 (and currently gen_lowpart might crash for a SUBREG). */
6956 /* Reject MODEs that aren't scalar integers because turning vector
6957 or complex modes into shifts causes problems. */
6963 /* If the inner object has VOIDmode (the only way this can happen
6964 is if it is an ASM_OPERANDS), we can't do anything since we don't
6965 know how much masking to do. */
6974 /* ... fall through ... */
6977 /* If the operand is a CLOBBER, just return it. */
6986 /* Reject MODEs that aren't scalar integers because turning vector
6987 or complex modes into shifts causes problems. */
6995 /* This should stay within the object being extracted, fail otherwise. */
7006 }
7007 /* Convert sign extension to zero extension, if we know that the high
7008 bit is not set, as this is easier to optimize. It will be converted
7009 back to cheaper alternative in make_extraction. */
7017 {
7021 /* Make sure this is a profitable operation. */
7028 else
7030 }
7032 /* We can optimize some special cases of ZERO_EXTEND. */
7034 {
7035 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7036 know that the last value didn't have any inappropriate bits
7037 set. */
7045 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7054 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7055 is a comparison and STORE_FLAG_VALUE permits. This is like
7056 the first case, but it works even when GET_MODE (x) is larger
7057 than HOST_WIDE_INT. */
7066 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7076 }
7078 /* If we reach here, we want to return a pair of shifts. The inner
7079 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7080 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7081 logical depending on the value of UNSIGNEDP.
7083 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7084 converted into an AND of a shift.
7086 We must check for the case where the left shift would have a negative
7087 count. This can happen in a case like (x >> 31) & 255 on machines
7088 that can't shift by a constant. On those machines, we would first
7089 combine the shift with the AND to produce a variable-position
7090 extraction. Then the constant of 31 would be substituted in
7091 to produce such a position. */
7095 {
7104 }
7111 else
7112 /* Any other cases we can't handle. */
7115 /* If we couldn't do this for some reason, return the original
7116 expression. */
7121 }
7122 \f
7123 /* X is a SET which contains an assignment of one object into
7124 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7125 or certain SUBREGS). If possible, convert it into a series of
7126 logical operations.
7128 We half-heartedly support variable positions, but do not at all
7129 support variable lengths. */
7131 static const_rtx
7133 {
7134 rtx inner;
7138 machine_mode compute_mode;
7140 /* Loop until we find something we can't simplify. */
7142 {
7145 {
7149 }
7152 {
7157 /* A constant position should stay within the width of INNER. */
7163 {
7171 /* If position is ADJUST - X, new position is X. */
7173 else
7174 {
7179 pos);
7180 }
7181 }
7182 }
7184 /* A SUBREG between two modes that occupy the same numbers of words
7185 can be done by moving the SUBREG to the source. */
7187 /* We need SUBREGs to compute nonzero_bits properly. */
7188 && nonzero_sign_valid
7193 {
7195 gen_lowpart
7199 }
7200 else
7208 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7210 {
7211 machine_mode imode;
7213 /* Don't do anything for vector or complex integral types. */
7217 /* Try to find an integral mode to pun with. */
7224 }
7226 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7230 /* Now compute the equivalent expression. Make a copy of INNER
7231 for the SET_DEST in case it is a MEM into which we will substitute;
7232 we don't want shared RTL in that case. */
7234 compute_mode);
7238 compute_mode,
7240 compute_mode),
7241 inner);
7246 mask),
7247 pos);
7252 }
7255 }
7256 \f
7257 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7258 it is an RTX that represents the (variable) starting position; otherwise,
7259 POS is the (constant) starting bit position. Both are counted from the LSB.
7261 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7263 IN_DEST is nonzero if this is a reference in the destination of a SET.
7264 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7265 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7266 be used.
7268 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7269 ZERO_EXTRACT should be built even for bits starting at bit 0.
7271 MODE is the desired mode of the result (if IN_DEST == 0).
7273 The result is an RTX for the extraction or NULL_RTX if the target
7274 can't handle it. */
7276 static rtx
7280 {
7281 /* This mode describes the size of the storage area
7282 to fetch the overall value from. Within that, we
7283 ignore the POS lowest bits, etc. */
7285 machine_mode inner_mode;
7286 machine_mode wanted_inner_mode;
7293 HOST_WIDE_INT orig_pos;
7299 {
7300 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7301 consider just the QI as the memory to extract from.
7302 The subreg adds or removes high bits; its mode is
7303 irrelevant to the meaning of this extraction,
7304 since POS and LEN count from the lsb. */
7308 }
7313 {
7314 /* We're extracting the least significant bits of an rtx
7315 (ashift X (const_int C)), where LEN > C. Extract the
7316 least significant (LEN - C) bits of X, giving an rtx
7317 whose mode is MODE, then shift it left C times. */
7323 }
7329 /* See if this can be done without an extraction. We never can if the
7330 width of the field is not the same as that of some integer mode. For
7331 registers, we can only avoid the extraction if the position is at the
7332 low-order bit and this is either not in the destination or we have the
7333 appropriate STRICT_LOW_PART operation available.
7335 For MEM, we can avoid an extract if the field starts on an appropriate
7336 boundary and we can change the mode of the memory reference. */
7345 && (! in_dest
7349 && (pos
7352 /* We can't do this if we are widening INNER_MODE (it
7353 may not be aligned, for one thing). */
7359 {
7360 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7361 field. If the original and current mode are the same, we need not
7362 adjust the offset. Otherwise, we do if bytes big endian.
7364 If INNER is not a MEM, get a piece consisting of just the field
7365 of interest (in this case POS % BITS_PER_WORD must be 0). */
7368 {
7369 HOST_WIDE_INT offset;
7371 /* POS counts from lsb, but make OFFSET count in memory order. */
7374 else
7378 }
7380 {
7382 {
7383 /* We can't call gen_lowpart in a DEST since we
7384 always want a SUBREG (see below) and it would sometimes
7385 return a new hard register. */
7387 {
7402 /* Avoid creating invalid subregs, for example when
7403 simplifying (x>>32)&255. */
7408 }
7409 else
7411 }
7412 else
7414 }
7415 else
7417 len >= HOST_BITS_PER_WIDE_INT
7422 /* If this extraction is going into the destination of a SET,
7423 make a STRICT_LOW_PART unless we made a MEM. */
7438 /* If we know that no extraneous bits are set, and that the high
7439 bit is not set, convert the extraction to the cheaper of
7440 sign and zero extension, that are equivalent in these cases. */
7446 {
7450 /* Prefer ZERO_EXTENSION, since it gives more information to
7451 backends. */
7456 }
7458 /* Otherwise, sign- or zero-extend unless we already are in the
7459 proper mode. */
7463 }
7465 /* Unless this is a COMPARE or we have a funny memory reference,
7466 don't do anything with zero-extending field extracts starting at
7467 the low-order bit since they are simple AND operations. */
7472 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7473 if the position is not a constant and the length is not 1. In all
7474 other cases, we would only be going outside our object in cases when
7475 an original shift would have been undefined. */
7484 /* If INNER is not from memory, we want it to have the mode of a register
7485 extraction pattern's structure operand, or word_mode if there is no
7486 such pattern. The same applies to extraction_mode and pos_mode
7487 and their respective operands.
7489 For memory, assume that the desired extraction_mode and pos_mode
7490 are the same as for a register operation, since at present we don't
7491 have named patterns for aligned memory structures. */
7495 {
7499 }
7501 /* Never narrow an object, since that might not be safe. */
7509 else
7510 {
7511 /* Be careful not to go beyond the extracted object and maintain the
7512 natural alignment of the memory. */
7516 {
7519 }
7520 }
7525 {
7526 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7527 BITS_BIG_ENDIAN style. If position is constant, compute new
7528 position. Otherwise, build subtraction.
7529 Note that POS is relative to the mode of the original argument.
7530 If it's a MEM we need to recompute POS relative to that.
7531 However, if we're extracting from (or inserting into) a register,
7532 we want to recompute POS relative to wanted_inner_mode. */
7539 else
7540 pos_rtx
7543 pos_rtx);
7544 /* POS may be less than 0 now, but we check for that below.
7545 Note that it can only be less than 0 if !MEM_P (inner). */
7546 }
7548 /* If INNER has a wider mode, and this is a constant extraction, try to
7549 make it smaller and adjust the byte to point to the byte containing
7550 the value. */
7553 && ! pos_rtx
7558 {
7561 /* The computations below will be correct if the machine is big
7562 endian in both bits and bytes or little endian in bits and bytes.
7563 If it is mixed, we must adjust. */
7565 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7566 adjust OFFSET to compensate. */
7571 /* We can now move to the desired byte. */
7582 }
7584 /* If INNER is not memory, get it into the proper mode. If we are changing
7585 its mode, POS must be a constant and smaller than the size of the new
7586 mode. */
7588 {
7589 /* On the LHS, don't create paradoxical subregs implicitely truncating
7590 the register unless TRULY_NOOP_TRUNCATION. */
7593 wanted_inner_mode))
7605 pos_rtx
7611 }
7613 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7614 have to zero extend. Otherwise, we can just use a SUBREG. */
7617 {
7621 /* If we know that no extraneous bits are set, and that the high
7622 bit is not set, convert extraction to cheaper one - either
7623 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7624 cases. */
7632 {
7636 /* Prefer ZERO_EXTENSION, since it gives more information to
7637 backends. */
7641 }
7643 }
7645 /* Make POS_RTX unless we already have it and it is correct. If we don't
7646 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7647 be a CONST_INT. */
7654 /* Make the required operation. See if we can use existing rtx. */
7661 }
7662 \f
7663 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7664 with any other operations in X. Return X without that shift if so. */
7666 static rtx
7668 {
7671 rtx tem;
7674 {
7676 /* This is the shift itself. If it is wide enough, we will return
7677 either the value being shifted if the shift count is equal to
7678 COUNT or a shift for the difference. */
7692 /* If we can safely shift this constant and we find the inner shift,
7693 make a new operation. */
7698 {
7702 }
7707 }
7710 }
7711 \f
7712 /* Look at the expression rooted at X. Look for expressions
7713 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7714 Form these expressions.
7716 Return the new rtx, usually just X.
7718 Also, for machines like the VAX that don't have logical shift insns,
7719 try to convert logical to arithmetic shift operations in cases where
7720 they are equivalent. This undoes the canonicalizations to logical
7721 shifts done elsewhere.
7723 We try, as much as possible, to re-use rtl expressions to save memory.
7725 IN_CODE says what kind of expression we are processing. Normally, it is
7726 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7727 being kludges), it is MEM. When processing the arguments of a comparison
7728 or a COMPARE against zero, it is COMPARE. */
7730 rtx
7732 {
7740 rtx tem;
7743 /* Select the code to be used in recursive calls. Once we are inside an
7744 address, we stay there. If we have a comparison, set to COMPARE,
7745 but once inside, go back to our default of SET. */
7754 /* Process depending on the code of this operation. If NEW is set
7755 nonzero, it will be returned. */
7758 {
7760 /* Convert shifts by constants into multiplications if inside
7761 an address. */
7766 {
7772 {
7775 }
7778 }
7788 {
7792 }
7795 {
7799 mode));
7801 }
7802 else
7803 {
7807 }
7818 {
7822 }
7825 {
7829 mode));
7831 }
7832 else
7833 {
7837 }
7841 /* If the second operand is not a constant, we can't do anything
7842 with it. */
7846 /* If the constant is a power of two minus one and the first operand
7847 is a logical right shift, make an extraction. */
7850 {
7854 }
7856 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7861 {
7863 next_code);
7867 }
7868 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7874 {
7875 /* Apply the distributive law, and then try to make extractions. */
7882 }
7884 /* If we are have (and (rotate X C) M) and C is larger than the number
7885 of bits in M, this is an extraction. */
7891 {
7897 }
7899 /* On machines without logical shifts, if the operand of the AND is
7900 a logical shift and our mask turns off all the propagated sign
7901 bits, we can replace the logical shift with an arithmetic shift. */
7909 {
7916 make_compound_operation
7919 }
7921 /* If the constant is one less than a power of two, this might be
7922 representable by an extraction even if no shift is present.
7923 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7924 we are in a COMPARE. */
7928 next_code),
7931 /* If we are in a comparison and this is an AND with a power of two,
7932 convert this into the appropriate bit extract. */
7937 next_code),
7943 /* If the sign bit is known to be zero, replace this with an
7944 arithmetic shift. */
7949 {
7952 next_code),
7955 }
7957 /* ... fall through ... */
7963 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7964 this is a SIGN_EXTRACT. */
7971 {
7978 }
7980 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7981 If so, try to merge the shifts into a SIGN_EXTEND. We could
7982 also do this for some cases of SIGN_EXTRACT, but it doesn't
7983 seem worth the effort; the case checked for occurs on Alpha. */
7999 /* Call ourselves recursively on the inner expression. If we are
8000 narrowing the object and it has a different RTL code from
8001 what it originally did, do this SUBREG as a force_to_mode. */
8002 {
8006 /* If in_code is COMPARE, it isn't always safe to pass it through
8007 to the recursive make_compound_operation call. */
8011 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8012 is (const_int 0), rather than
8013 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8023 simplified
8031 {
8032 rtx newer
8035 /* If we have something other than a SUBREG, we might have
8036 done an expansion, so rerun ourselves. */
8040 /* force_to_mode can expand compounds. If it just re-expanded the
8041 compound, use gen_lowpart to convert to the desired mode. */
8043 /* Likewise if it re-expanded the compound only partially.
8044 This happens for SUBREG of ZERO_EXTRACT if they extract
8045 the same number of bits. */
8054 }
8058 }
8063 }
8066 {
8069 }
8071 /* Now recursively process each operand of this operation. We need to
8072 handle ZERO_EXTEND specially so that we don't lose track of the
8073 inner mode. */
8075 {
8083 }
8088 {
8091 }
8094 {
8097 }
8099 maybe_swap:
8100 /* If this is a commutative operation, the changes to the operands
8101 may have made it noncanonical. */
8104 {
8108 }
8111 }
8112 \f
8113 /* Given M see if it is a value that would select a field of bits
8114 within an item, but not the entire word. Return -1 if not.
8115 Otherwise, return the starting position of the field, where 0 is the
8116 low-order bit.
8118 *PLEN is set to the length of the field. */
8120 static int
8122 {
8123 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8128 /* Now shift off the low-order zero bits and see if we have a
8129 power of two minus 1. */
8137 }
8138 \f
8139 /* If X refers to a register that equals REG in value, replace these
8140 references with REG. */
8141 static rtx
8143 {
8151 {
8187 {
8191 else
8193 }
8195 /* fall through */
8202 {
8205 {
8207 {
8210 }
8212 }
8213 }
8215 {
8218 {
8221 {
8223 {
8226 }
8228 }
8229 }
8230 }
8233 }
8236 }
8238 /* Return X converted to MODE. If the value is already truncated to
8239 MODE we can just return a subreg even though in the general case we
8240 would need an explicit truncation. */
8242 static rtx
8244 {
8249 {
8250 /* Bit-cast X into an integer mode. */
8255 }
8258 }
8260 /* See if X can be simplified knowing that we will only refer to it in
8261 MODE and will only refer to those bits that are nonzero in MASK.
8262 If other bits are being computed or if masking operations are done
8263 that select a superset of the bits in MASK, they can sometimes be
8264 ignored.
8266 Return a possibly simplified expression, but always convert X to
8267 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8269 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8270 are all off in X. This is used when X will be complemented, by either
8271 NOT, NEG, or XOR. */
8273 static rtx
8276 {
8279 machine_mode op_mode;
8283 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8284 code below will do the wrong thing since the mode of such an
8285 expression is VOIDmode.
8287 Also do nothing if X is a CLOBBER; this can happen if X was
8288 the return value from a call to gen_lowpart. */
8292 /* We want to perform the operation in its present mode unless we know
8293 that the operation is valid in MODE, in which case we do the operation
8294 in MODE. */
8299 /* It is not valid to do a right-shift in a narrower mode
8300 than the one it came in with. */
8305 /* Truncate MASK to fit OP_MODE. */
8309 /* When we have an arithmetic operation, or a shift whose count we
8310 do not know, we need to assume that all bits up to the highest-order
8311 bit in MASK will be needed. This is how we form such a mask. */
8314 else
8318 /* Determine what bits of X are guaranteed to be (non)zero. */
8321 /* If none of the bits in X are needed, return a zero. */
8325 /* If X is a CONST_INT, return a new one. Do this here since the
8326 test below will fail. */
8328 {
8331 else
8332 {
8335 }
8336 }
8338 /* If X is narrower than MODE and we want all the bits in X's mode, just
8339 get X in the proper mode. */
8344 /* We can ignore the effect of a SUBREG if it narrows the mode or
8345 if the constant masks to zero all the bits the mode doesn't have. */
8355 /* The arithmetic simplifications here only work for scalar integer modes. */
8360 {
8362 /* If X is a (clobber (const_int)), return it since we know we are
8363 generating something that won't match. */
8376 /* Similarly for a truncate. */
8380 /* If this is an AND with a constant, convert it into an AND
8381 whose constant is the AND of that constant with MASK. If it
8382 remains an AND of MASK, delete it since it is redundant. */
8385 {
8389 /* If X is still an AND, see if it is an AND with a mask that
8390 is just some low-order bits. If so, and it is MASK, we don't
8391 need it. */
8398 /* If it remains an AND, try making another AND with the bits
8399 in the mode mask that aren't in MASK turned on. If the
8400 constant in the AND is wide enough, this might make a
8401 cheaper constant. */
8406 {
8407 unsigned HOST_WIDE_INT cval
8410 rtx y;
8417 }
8420 }
8425 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8426 low-order bits (as in an alignment operation) and FOO is already
8427 aligned to that boundary, mask C1 to that boundary as well.
8428 This may eliminate that PLUS and, later, the AND. */
8430 {
8434 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8435 number, sign extend it. */
8448 }
8450 /* ... fall through ... */
8453 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8454 most significant bit in MASK since carries from those bits will
8455 affect the bits we are interested in. */
8460 /* If X is (minus C Y) where C's least set bit is larger than any bit
8461 in the mask, then we may replace with (neg Y). */
8464 {
8468 }
8470 /* Similarly, if C contains every bit in the fuller_mask, then we may
8471 replace with (not Y). */
8474 {
8478 }
8485 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8486 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8487 operation which may be a bitfield extraction. Ensure that the
8488 constant we form is not wider than the mode of X. */
8500 {
8509 }
8511 binop:
8512 /* For most binary operations, just propagate into the operation and
8513 change the mode if we have an operation of that mode. */
8518 /* If we ended up truncating both operands, truncate the result of the
8519 operation instead. */
8522 {
8525 }
8535 /* For left shifts, do the same, but just for the first operand.
8536 However, we cannot do anything with shifts where we cannot
8537 guarantee that the counts are smaller than the size of the mode
8538 because such a count will have a different meaning in a
8539 wider mode. */
8549 /* If the shift count is a constant and we can do arithmetic in
8550 the mode of the shift, refine which bits we need. Otherwise, use the
8551 conservative form of the mask. */
8557 else
8569 /* Here we can only do something if the shift count is a constant,
8570 this shift constant is valid for the host, and we can do arithmetic
8571 in OP_MODE. */
8577 {
8581 /* Select the mask of the bits we need for the shift operand. */
8584 /* We can only change the mode of the shift if we can do arithmetic
8585 in the mode of the shift and INNER_MASK is no wider than the
8586 width of X's mode. */
8594 }
8596 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8597 shift and AND produces only copies of the sign bit (C2 is one less
8598 than a power of two), we can do this with just a shift. */
8602 /* The shift puts one of the sign bit copies in the least significant
8603 bit. */
8608 /* Number of bits left after the shift must be more than the mask
8609 needs. */
8612 /* Must be more sign bit copies than the mask needs. */
8622 /* If we are just looking for the sign bit, we don't need this shift at
8623 all, even if it has a variable count. */
8627 /* If this is a shift by a constant, get a mask that contains those bits
8628 that are not copies of the sign bit. We then have two cases: If
8629 MASK only includes those bits, this can be a logical shift, which may
8630 allow simplifications. If MASK is a single-bit field not within
8631 those bits, we are requesting a copy of the sign bit and hence can
8632 shift the sign bit to the appropriate location. */
8636 {
8639 /* If the considered data is wider than HOST_WIDE_INT, we can't
8640 represent a mask for all its bits in a single scalar.
8641 But we only care about the lower bits, so calculate these. */
8644 {
8647 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8648 is the number of bits a full-width mask would have set.
8649 We need only shift if these are fewer than nonzero can
8650 hold. If not, we must keep all bits set in nonzero. */
8655 + HOST_BITS_PER_WIDE_INT
8657 }
8658 else
8659 {
8662 }
8665 {
8670 }
8673 {
8674 x = simplify_shift_const
8680 }
8681 }
8683 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8684 even if the shift count isn't a constant. */
8689 shiftrt:
8691 /* If this is a zero- or sign-extension operation that just affects bits
8692 we don't care about, remove it. Be sure the call above returned
8693 something that is still a shift. */
8703 next_select);
8709 /* If the shift count is constant and we can do computations
8710 in the mode of X, compute where the bits we care about are.
8711 Otherwise, we can't do anything. Don't change the mode of
8712 the shift or propagate MODE into the shift, though. */
8715 {
8725 }
8729 /* If we just want the low-order bit, the NEG isn't needed since it
8730 won't change the low-order bit. */
8734 /* We need any bits less significant than the most significant bit in
8735 MASK since carries from those bits will affect the bits we are
8736 interested in. */
8741 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8742 same as the XOR case above. Ensure that the constant we form is not
8743 wider than the mode of X. */
8751 {
8760 }
8762 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8763 use the full mask inside the NOT. */
8766 unop:
8769 next_select));
8775 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8776 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8777 which is equal to STORE_FLAG_VALUE. */
8789 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8790 written in a narrower mode. We play it safe and do not do so. */
8806 }
8808 /* Ensure we return a value of the proper mode. */
8810 }
8811 \f
8812 /* Return nonzero if X is an expression that has one of two values depending on
8813 whether some other value is zero or nonzero. In that case, we return the
8814 value that is being tested, *PTRUE is set to the value if the rtx being
8815 returned has a nonzero value, and *PFALSE is set to the other alternative.
8817 If we return zero, we set *PTRUE and *PFALSE to X. */
8819 static rtx
8821 {
8827 /* If we are comparing a value against zero, we are done. */
8830 {
8834 }
8836 /* If this is a unary operation whose operand has one of two values, apply
8837 our opcode to compute those values. */
8840 {
8845 }
8847 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8848 make can't possibly match and would suppress other optimizations. */
8850 ;
8852 /* If this is a binary operation, see if either side has only one of two
8853 values. If either one does or if both do and they are conditional on
8854 the same value, compute the new true and false values. */
8856 {
8862 {
8863 /* If if_then_else_cond returned zero, then true/false are the
8864 same rtl. We must copy one of them to prevent invalid rtl
8865 sharing. */
8872 {
8877 }
8878 else
8879 {
8882 }
8885 }
8887 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8888 operands is zero when the other is nonzero, and vice-versa,
8889 and STORE_FLAG_VALUE is 1 or -1. */
8895 {
8912 {
8919 const_true_rtx);
8921 }
8922 }
8924 /* Similarly for MULT, AND and UMIN, except that for these the result
8925 is always zero. */
8929 {
8943 {
8946 }
8947 }
8948 }
8951 {
8952 /* If we have IF_THEN_ELSE already, extract the condition and
8953 canonicalize it if it is NE or EQ. */
8959 {
8962 }
8963 else
8965 }
8967 /* If X is a SUBREG, we can narrow both the true and false values
8968 if the inner expression, if there is a condition. */
8972 {
8978 {
8982 }
8983 }
8985 /* If X is a constant, this isn't special and will cause confusions
8986 if we treat it as such. Likewise if it is equivalent to a constant. */
8989 ;
8991 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8992 will be least confusing to the rest of the compiler. */
8994 {
8997 }
8999 /* If X is known to be either 0 or -1, those are the true and
9000 false values when testing X. */
9004 {
9007 }
9009 /* Likewise for 0 or a single bit. */
9012 {
9015 }
9017 /* Otherwise fail; show no condition with true and false values the same. */
9020 }
9021 \f
9022 /* Return the value of expression X given the fact that condition COND
9023 is known to be true when applied to REG as its first operand and VAL
9024 as its second. X is known to not be shared and so can be modified in
9025 place.
9027 We only handle the simplest cases, and specifically those cases that
9028 arise with IF_THEN_ELSE expressions. */
9030 static rtx
9032 {
9034 rtx temp;
9041 /* If either operand of the condition is a floating point value,
9042 then we have to avoid collapsing an EQ comparison. */
9052 /* If X is (abs REG) and we know something about REG's relationship
9053 with zero, we may be able to simplify this. */
9057 {
9066 }
9068 /* The only other cases we handle are MIN, MAX, and comparisons if the
9069 operands are the same as REG and VAL. */
9072 {
9077 {
9079 {
9087 else
9089 }
9092 {
9095 /* Do not reverse the condition when it is NE or EQ.
9096 This is because we cannot conclude anything about
9097 the value of 'SMAX (x, y)' when x is not equal to y,
9098 but we can when x equals y. */
9104 {
9115 }
9116 }
9117 }
9118 }
9120 {
9125 {
9126 /* We must simplify subreg here, before we lose track of the
9127 original inner_mode. */
9132 else
9134 }
9137 }
9138 /* We don't have to handle SIGN_EXTEND here, because even in the
9139 case of replacing something with a modeless CONST_INT, a
9140 CONST_INT is already (supposed to be) a valid sign extension for
9141 its narrower mode, which implies it's already properly
9142 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9143 story is different. */
9145 {
9150 {
9151 /* We must simplify the zero_extend here, before we lose
9152 track of the original inner_mode. */
9157 else
9159 }
9162 }
9166 {
9173 }
9176 }
9177 \f
9178 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9179 assignment as a field assignment. */
9181 static int
9183 {
9185 {
9190 /* For big endian, adjust the memory offset. */
9195 else
9197 }
9205 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9206 Note that all SUBREGs of MEM are paradoxical; otherwise they
9207 would have been rewritten. */
9220 /* We used to see if get_last_value of X and Y were the same but that's
9221 not correct. In one direction, we'll cause the assignment to have
9222 the wrong destination and in the case, we'll import a register into this
9223 insn that might have already have been dead. So fail if none of the
9224 above cases are true. */
9226 }
9227 \f
9228 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9229 Return that assignment if so.
9231 We only handle the most common cases. */
9233 static rtx
9235 {
9238 rtx assign;
9240 HOST_WIDE_INT c1;
9241 HOST_WIDE_INT pos;
9243 rtx other;
9244 machine_mode mode;
9246 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9247 a clear of a one-bit field. We will have changed it to
9248 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9249 for a SUBREG. */
9255 {
9261 }
9271 {
9278 }
9280 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9281 one-bit field. */
9285 {
9291 }
9293 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9294 SRC is an AND with all bits of that field set, then we can discard
9295 the AND. */
9300 {
9307 else
9310 /* Complete overlap. We can remove the source AND. */
9314 /* Partial overlap. We can reduce the source AND. */
9316 {
9321 }
9322 }
9324 /* The other case we handle is assignments into a constant-position
9325 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9326 a mask that has all one bits except for a group of zero bits and
9327 OTHER is known to have zeros where C1 has ones, this is such an
9328 assignment. Compute the position and length from C1. Shift OTHER
9329 to the appropriate position, force it to the required mode, and
9330 make the extraction. Check for the AND in both operands. */
9332 /* One or more SUBREGs might obscure the constant-position field
9333 assignment. The first one we are likely to encounter is an outer
9334 narrowing SUBREG, which we can just strip for the purposes of
9335 identifying the constant-field assignment. */
9349 /* The second SUBREG that might get in the way is a paradoxical
9350 SUBREG around the first operand of the AND. We want to
9351 pretend the operand is as wide as the destination here. We
9352 do this by adjusting the MEM to wider mode for the sole
9353 purpose of the call to rtx_equal_for_field_assignment_p. Also
9354 note this trick only works for MEMs. */
9366 /* The second SUBREG that might get in the way is a paradoxical
9367 SUBREG around the first operand of the AND. We want to
9368 pretend the operand is as wide as the destination here. We
9369 do this by adjusting the MEM to wider mode for the sole
9370 purpose of the call to rtx_equal_for_field_assignment_p. Also
9371 note this trick only works for MEMs. */
9379 else
9392 /* The mode to use for the source is the mode of the assignment, or of
9393 what is inside a possible STRICT_LOW_PART. */
9397 /* Shift OTHER right POS places and make it the source, restricting it
9398 to the proper length and mode. */
9403 dest);
9410 /* If SRC is masked by an AND that does not make a difference in
9411 the value being stored, strip it. */
9422 }
9423 \f
9424 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9425 if so. */
9427 static rtx
9429 {
9433 rtx tem;
9435 /* Distributivity is not true for floating point as it can change the
9436 value. So we don't do it unless -funsafe-math-optimizations. */
9441 /* The outer operation can only be one of the following: */
9449 /* If either operand is a primitive we can't do anything, so get out
9450 fast. */
9460 /* See if the inner and outer operations distribute. */
9462 {
9467 /* These all distribute except over PLUS. */
9478 /* This is also a multiply, so it distributes over everything. */
9481 /* This used to handle SUBREG, but this turned out to be counter-
9482 productive, since (subreg (op ...)) usually is not handled by
9483 insn patterns, and this "optimization" therefore transformed
9484 recognizable patterns into unrecognizable ones. Therefore the
9485 SUBREG case was removed from here.
9487 It is possible that distributing SUBREG over arithmetic operations
9488 leads to an intermediate result than can then be optimized further,
9489 e.g. by moving the outer SUBREG to the other side of a SET as done
9490 in simplify_set. This seems to have been the original intent of
9491 handling SUBREGs here.
9493 However, with current GCC this does not appear to actually happen,
9494 at least on major platforms. If some case is found where removing
9495 the SUBREG case here prevents follow-on optimizations, distributing
9496 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9500 }
9502 /* Set LHS and RHS to the inner operands (A and B in the example
9503 above) and set OTHER to the common operand (C in the example).
9504 There is only one way to do this unless the inner operation is
9505 commutative. */
9517 else
9520 /* Form the new inner operation, seeing if it simplifies first. */
9523 /* There is one exception to the general way of distributing:
9524 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9526 {
9529 }
9531 /* We may be able to continuing distributing the result, so call
9532 ourselves recursively on the inner operation before forming the
9533 outer operation, which we return. */
9536 }
9538 /* See if X is of the form (* (+ A B) C), and if so convert to
9539 (+ (* A C) (* B C)) and try to simplify.
9541 Most of the time, this results in no change. However, if some of
9542 the operands are the same or inverses of each other, simplifications
9543 will result.
9545 For example, (and (ior A B) (not B)) can occur as the result of
9546 expanding a bit field assignment. When we apply the distributive
9547 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9548 which then simplifies to (and (A (not B))).
9550 Note that no checks happen on the validity of applying the inverse
9551 distributive law. This is pointless since we can do it in the
9552 few places where this routine is called.
9554 N is the index of the term that is decomposed (the arithmetic operation,
9555 i.e. (+ A B) in the first example above). !N is the index of the term that
9556 is distributed, i.e. of C in the first example above. */
9557 static rtx
9559 {
9560 machine_mode mode;
9564 /* Distributivity is not true for floating point as it can change the
9565 value. So we don't do it unless -funsafe-math-optimizations. */
9582 /* Special case (and (xor B C) (not A)), which is equivalent to
9583 (xor (ior A B) (ior A C)) */
9585 {
9588 }
9591 {
9592 /* Distribute the second term. */
9595 }
9596 else
9597 {
9598 /* Distribute the first term. */
9601 }
9611 }
9612 \f
9613 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9614 in MODE. Return an equivalent form, if different from (and VAROP
9615 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9617 static rtx
9620 {
9623 rtx orig_varop;
9631 /* Simplify VAROP knowing that we will be only looking at some of the
9632 bits in it.
9634 Note by passing in CONSTOP, we guarantee that the bits not set in
9635 CONSTOP are not significant and will never be examined. We must
9636 ensure that is the case by explicitly masking out those bits
9637 before returning. */
9640 /* If VAROP is a CLOBBER, we will fail so return it. */
9644 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9645 to VAROP and return the new constant. */
9649 /* See what bits may be nonzero in VAROP. Unlike the general case of
9650 a call to nonzero_bits, here we don't care about bits outside
9651 MODE. */
9655 /* Turn off all bits in the constant that are known to already be zero.
9656 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9657 which is tested below. */
9661 /* If we don't have any bits left, return zero. */
9665 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9666 a power of two, we can replace this with an ASHIFT. */
9671 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9672 or XOR, then try to apply the distributive law. This may eliminate
9673 operations if either branch can be simplified because of the AND.
9674 It may also make some cases more complex, but those cases probably
9675 won't match a pattern either with or without this. */
9678 return
9679 gen_lowpart
9681 apply_distributive_law
9686 constop),
9690 constop))));
9692 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9693 the AND and see if one of the operands simplifies to zero. If so, we
9694 may eliminate it. */
9698 {
9707 }
9709 /* Make a SUBREG if necessary. If we can't make it, fail. */
9714 /* If we are only masking insignificant bits, return VAROP. */
9721 /* Otherwise, return an AND. */
9723 }
9726 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9727 in MODE.
9729 Return an equivalent form, if different from X. Otherwise, return X. If
9730 X is zero, we are to always construct the equivalent form. */
9732 static rtx
9735 {
9746 }
9747 \f
9748 /* Given a REG, X, compute which bits in X can be nonzero.
9749 We don't care about bits outside of those defined in MODE.
9751 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9752 a shift, AND, or zero_extract, we can do better. */
9754 static rtx
9756 const_rtx known_x ATTRIBUTE_UNUSED,
9757 machine_mode known_mode ATTRIBUTE_UNUSED,
9760 {
9761 rtx tem;
9764 /* If X is a register whose nonzero bits value is current, use it.
9765 Otherwise, if X is a register whose value we can find, use that
9766 value. Otherwise, use the previously-computed global nonzero bits
9767 for this register. */
9781 && !REGNO_REG_SET_P
9784 {
9788 /* We don't know anything about the upper bits. */
9793 }
9798 {
9799 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9800 /* If X is narrower than MODE and TEM is a non-negative
9801 constant that would appear negative in the mode of X,
9802 sign-extend it for use in reg_nonzero_bits because some
9803 machines (maybe most) will actually do the sign-extension
9804 and this is the conservative approach.
9806 ??? For 2.5, try to tighten up the MD files in this regard
9807 instead of this kludge. */
9814 #endif
9816 }
9818 {
9822 /* We don't know anything about the upper bits. */
9826 }
9829 }
9831 /* Return the number of bits at the high-order end of X that are known to
9832 be equal to the sign bit. X will be used in mode MODE; if MODE is
9833 VOIDmode, X will be used in its own mode. The returned value will always
9834 be between 1 and the number of bits in MODE. */
9836 static rtx
9838 const_rtx known_x ATTRIBUTE_UNUSED,
9839 machine_mode known_mode
9840 ATTRIBUTE_UNUSED,
9843 {
9844 rtx tem;
9857 && !REGNO_REG_SET_P
9860 {
9863 }
9874 }
9875 \f
9876 /* Return the number of "extended" bits there are in X, when interpreted
9877 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9878 unsigned quantities, this is the number of high-order zero bits.
9879 For signed quantities, this is the number of copies of the sign bit
9880 minus 1. In both case, this function returns the number of "spare"
9881 bits. For example, if two quantities for which this function returns
9882 at least 1 are added, the addition is known not to overflow.
9884 This function will always return 0 unless called during combine, which
9885 implies that it must be called from a define_split. */
9887 unsigned int
9889 {
9899 }
9901 /* This function is called from `simplify_shift_const' to merge two
9902 outer operations. Specifically, we have already found that we need
9903 to perform operation *POP0 with constant *PCONST0 at the outermost
9904 position. We would now like to also perform OP1 with constant CONST1
9905 (with *POP0 being done last).
9907 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9908 the resulting operation. *PCOMP_P is set to 1 if we would need to
9909 complement the innermost operand, otherwise it is unchanged.
9911 MODE is the mode in which the operation will be done. No bits outside
9912 the width of this mode matter. It is assumed that the width of this mode
9913 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9915 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9916 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9917 result is simply *PCONST0.
9919 If the resulting operation cannot be expressed as one operation, we
9920 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9922 static int
9923 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
9924 {
9931 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9935 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9936 if OP0 is SET. */
9945 {
9947 {
9965 }
9966 }
9968 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9972 /* If the two constants aren't the same, we can't do anything. The
9973 remaining six cases can all be done. */
9977 else
9979 {
9982 /* (a & b) | b == b */
9985 /* (a ^ b) | b == a | b */
9986 {;}
9991 /* (a & b) ^ b == (~a) & b */
9994 /* (a | b) ^ b == a & ~b */
10000 /* (a | b) & b == b */
10003 /* (a ^ b) & b) == (~a) & b */
10008 }
10010 /* Check for NO-OP cases. */
10023 /* ??? Slightly redundant with the above mask, but not entirely.
10024 Moving this above means we'd have to sign-extend the mode mask
10025 for the final test. */
10030 }
10031 \f
10032 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10033 the shift in. The original shift operation CODE is performed on OP in
10034 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10035 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10036 result of the shift is subject to operation OUTER_CODE with operand
10037 OUTER_CONST. */
10039 static machine_mode
10043 {
10048 /* In general we can't perform in wider mode for right shift and rotate. */
10050 {
10052 /* We can still widen if the bits brought in from the left are identical
10053 to the sign bit of ORIG_MODE. */
10061 /* Similarly here but with zero bits. */
10066 /* We can also widen if the bits brought in will be masked off. This
10067 operation is performed in ORIG_MODE. */
10069 {
10075 }
10076 /* fall through */
10086 }
10087 }
10089 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10090 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10091 if we cannot simplify it. Otherwise, return a simplified value.
10093 The shift is normally computed in the widest mode we find in VAROP, as
10094 long as it isn't a different number of words than RESULT_MODE. Exceptions
10095 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10097 static rtx
10100 {
10106 unsigned int mode_words
10108 /* We form (outer_op (code varop count) (outer_const)). */
10114 /* Make sure and truncate the "natural" shift on the way in. We don't
10115 want to do this inside the loop as it makes it more difficult to
10116 combine shifts. */
10120 /* If we were given an invalid count, don't do anything except exactly
10121 what was requested. */
10128 /* Unless one of the branches of the `if' in this loop does a `continue',
10129 we will `break' the loop after the `if'. */
10132 {
10133 /* If we have an operand of (clobber (const_int 0)), fail. */
10137 /* Convert ROTATERT to ROTATE. */
10139 {
10144 else
10146 }
10151 /* Handle cases where the count is greater than the size of the mode
10152 minus 1. For ASHIFT, use the size minus one as the count (this can
10153 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10154 take the count modulo the size. For other shifts, the result is
10155 zero.
10157 Since these shifts are being produced by the compiler by combining
10158 multiple operations, each of which are defined, we know what the
10159 result is supposed to be. */
10162 {
10167 else
10168 {
10169 /* We can't simply return zero because there may be an
10170 outer op. */
10174 }
10175 }
10177 /* If we discovered we had to complement VAROP, leave. Making a NOT
10178 here would cause an infinite loop. */
10182 /* An arithmetic right shift of a quantity known to be -1 or 0
10183 is a no-op. */
10187 {
10190 }
10192 /* If we are doing an arithmetic right shift and discarding all but
10193 the sign bit copies, this is equivalent to doing a shift by the
10194 bitsize minus one. Convert it into that shift because it will often
10195 allow other simplifications. */
10202 /* We simplify the tests below and elsewhere by converting
10203 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10204 `make_compound_operation' will convert it to an ASHIFTRT for
10205 those machines (such as VAX) that don't have an LSHIFTRT. */
10222 {
10229 {
10232 }
10236 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10237 minus the width of a smaller mode, we can do this with a
10238 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10245 {
10254 }
10258 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10259 the same number of words as what we've seen so far. Then store
10260 the widest mode in MODE. */
10266 == mode_words
10269 {
10274 }
10278 /* Some machines use MULT instead of ASHIFT because MULT
10279 is cheaper. But it is still better on those machines to
10280 merge two shifts into one. */
10283 {
10284 varop
10290 }
10294 /* Similar, for when divides are cheaper. */
10297 {
10298 varop
10304 }
10308 /* If we are extracting just the sign bit of an arithmetic
10309 right shift, that shift is not needed. However, the sign
10310 bit of a wider mode may be different from what would be
10311 interpreted as the sign bit in a narrower mode, so, if
10312 the result is narrower, don't discard the shift. */
10317 {
10320 }
10322 /* ... fall through ... */
10327 /* Here we have two nested shifts. The result is usually the
10328 AND of a new shift with a mask. We compute the result below. */
10335 {
10339 rtx mask_rtx;
10341 /* We have one common special case. We can't do any merging if
10342 the inner code is an ASHIFTRT of a smaller mode. However, if
10343 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10344 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10345 we can convert it to
10346 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10347 This simplifies certain SIGN_EXTEND operations. */
10351 {
10352 /* C3 has the low-order C1 bits zero. */
10364 }
10366 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10367 than C1 high-order bits equal to the sign bit, we can convert
10368 this to either an ASHIFT or an ASHIFTRT depending on the
10369 two counts.
10371 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10377 {
10381 {
10384 }
10387 }
10389 /* There are some cases we can't do. If CODE is ASHIFTRT,
10390 we can only do this if FIRST_CODE is also ASHIFTRT.
10392 We can't do the case when CODE is ROTATE and FIRST_CODE is
10393 ASHIFTRT.
10395 If the mode of this shift is not the mode of the outer shift,
10396 we can't do this if either shift is a right shift or ROTATE.
10398 Finally, we can't do any of these if the mode is too wide
10399 unless the codes are the same.
10401 Handle the case where the shift codes are the same
10402 first. */
10405 {
10414 }
10425 /* To compute the mask to apply after the shift, shift the
10426 nonzero bits of the inner shift the same way the
10427 outer shift will. */
10430 result_mode);
10432 mask_rtx
10436 /* Give up if we can't compute an outer operation to use. */
10444 /* If the shifts are in the same direction, we add the
10445 counts. Otherwise, we subtract them. */
10449 else
10452 /* If COUNT is positive, the new shift is usually CODE,
10453 except for the two exceptions below, in which case it is
10454 FIRST_CODE. If the count is negative, FIRST_CODE should
10455 always be used */
10465 }
10467 /* If we have (A << B << C) for any shift, we can convert this to
10468 (A << C << B). This wins if A is a constant. Only try this if
10469 B is not a constant. */
10474 {
10481 }
10488 /* Make this fit the case below. */
10495 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10496 with C the size of VAROP - 1 and the shift is logical if
10497 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10498 we have an (le X 0) operation. If we have an arithmetic shift
10499 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10500 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10508 {
10511 const0_rtx);
10517 }
10519 /* If we have (shift (logical)), move the logical to the outside
10520 to allow it to possibly combine with another logical and the
10521 shift to combine with another shift. This also canonicalizes to
10522 what a ZERO_EXTRACT looks like. Also, some machines have
10523 (and (shift)) insns. */
10526 /* We can't do this if we have (ashiftrt (xor)) and the
10527 constant has its sign bit set in shift_mode with shift_mode
10528 wider than result_mode. */
10532 shift_mode))
10540 {
10543 }
10545 /* If we can't do that, try to simplify the shift in each arm of the
10546 logical expression, make a new logical expression, and apply
10547 the inverse distributive law. This also can't be done for
10548 (ashiftrt (xor)) where we've widened the shift and the constant
10549 changes the sign bit. */
10554 shift_mode)))
10555 {
10567 }
10571 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10572 says that the sign bit can be tested, FOO has mode MODE, C is
10573 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10574 that may be nonzero. */
10584 {
10588 }
10592 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10593 than the number of bits in the mode is equivalent to A. */
10597 {
10601 }
10603 /* NEG commutes with ASHIFT since it is multiplication. Move the
10604 NEG outside to allow shifts to combine. */
10608 {
10611 }
10615 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10616 is one less than the number of bits in the mode is
10617 equivalent to (xor A 1). */
10624 {
10628 }
10630 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10631 that might be nonzero in BAR are those being shifted out and those
10632 bits are known zero in FOO, we can replace the PLUS with FOO.
10633 Similarly in the other operand order. This code occurs when
10634 we are computing the size of a variable-size array. */
10641 {
10644 }
10652 result_mode)))
10653 {
10656 }
10658 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10668 {
10671 }
10673 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10674 signbit', and attempt to change the PLUS to an XOR and move it to
10675 the outer operation as is done above in the AND/IOR/XOR case
10676 leg for shift(logical). See details in logical handling above
10677 for reasoning in doing so. */
10688 {
10691 }
10696 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10697 with C the size of VAROP - 1 and the shift is logical if
10698 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10699 we have a (gt X 0) operation. If the shift is arithmetic with
10700 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10701 we have a (neg (gt X 0)) operation. */
10710 {
10713 const0_rtx);
10719 }
10723 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10724 if the truncate does not affect the value. */
10731 {
10734 varop_inner
10737 GEN_INT
10742 }
10747 }
10750 }
10755 /* We have now finished analyzing the shift. The result should be
10756 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10757 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10758 to the result of the shift. OUTER_CONST is the relevant constant,
10759 but we must turn off all bits turned off in the shift. */
10767 /* Make a SUBREG if necessary. If we can't make it, fail. */
10772 /* If we have an outer operation and we just made a shift, it is
10773 possible that we could have simplified the shift were it not
10774 for the outer operation. So try to do the simplification
10775 recursively. */
10779 else
10785 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10786 turn off all the bits that the shift would have turned off. */
10791 /* Do the remainder of the processing in RESULT_MODE. */
10794 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10795 operation. */
10800 {
10808 {
10809 /* This means that we have determined that the result is
10810 equivalent to a constant. This should be rare. */
10813 }
10816 else
10819 }
10822 }
10824 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10825 The result of the shift is RESULT_MODE. If we cannot simplify it,
10826 return X or, if it is NULL, synthesize the expression with
10827 simplify_gen_binary. Otherwise, return a simplified value.
10829 The shift is normally computed in the widest mode we find in VAROP, as
10830 long as it isn't a different number of words than RESULT_MODE. Exceptions
10831 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10833 static rtx
10836 {
10846 }
10848 \f
10849 /* Like recog, but we receive the address of a pointer to a new pattern.
10850 We try to match the rtx that the pointer points to.
10851 If that fails, we may try to modify or replace the pattern,
10852 storing the replacement into the same pointer object.
10854 Modifications include deletion or addition of CLOBBERs.
10856 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10857 the CLOBBERs are placed.
10859 The value is the final insn code from the pattern ultimately matched,
10860 or -1. */
10862 static int
10864 {
10866 rtx pat_without_clobbers;
10874 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10875 we use to indicate that something didn't match. If we find such a
10876 thing, force rejection. */
10890 {
10893 else
10896 }
10898 /* If it isn't, there is the possibility that we previously had an insn
10899 that clobbered some register as a side effect, but the combined
10900 insn doesn't need to do that. So try once more without the clobbers
10901 unless this represents an ASM insn. */
10905 {
10910 {
10913 pos++;
10914 }
10924 {
10927 else
10930 }
10931 }
10938 /* Recognize all noop sets, these will be killed by followup pass. */
10942 /* If we had any clobbers to add, make a new pattern than contains
10943 them. Then check to make sure that all of them are dead. */
10945 {
10955 else
10962 {
10967 {
10971 }
10972 }
10974 }
10978 {
10985 /* Allow targets to reject combined insn. */
10987 {
10990 dump_file);
10992 /* Callers expect recog_for_combine to strip
10993 clobbers from the pattern on failure. */
10998 }
11003 }
11009 }
11010 \f
11011 /* Like gen_lowpart_general but for use by combine. In combine it
11012 is not possible to create any new pseudoregs. However, it is
11013 safe to create invalid memory addresses, because combine will
11014 try to recognize them and all they will do is make the combine
11015 attempt fail.
11017 If for some reason this cannot do its job, an rtx
11018 (clobber (const_int 0)) is returned.
11019 An insn containing that will not be recognized. */
11021 static rtx
11023 {
11027 rtx result;
11032 /* We can only support MODE being wider than a word if X is a
11033 constant integer or has a mode the same size. */
11038 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11039 won't know what to do. So we will strip off the SUBREG here and
11040 process normally. */
11042 {
11045 /* For use in case we fall down into the address adjustments
11046 further below, we need to adjust the known mode and size of
11047 x; imode and isize, since we just adjusted x. */
11054 }
11062 {
11065 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11066 address. */
11071 /* If we want to refer to something bigger than the original memref,
11072 generate a paradoxical subreg instead. That will force a reload
11073 of the original memref X. */
11080 /* Adjust the address so that the address-after-the-data is
11081 unchanged. */
11086 }
11088 /* If X is a comparison operator, rewrite it in a new mode. This
11089 probably won't match, but may allow further simplifications. */
11093 /* If we couldn't simplify X any other way, just enclose it in a
11094 SUBREG. Normally, this SUBREG won't match, but some patterns may
11095 include an explicit SUBREG or we may simplify it further in combine. */
11096 else
11097 {
11099 rtx res;
11103 {
11108 }
11112 }
11114 fail:
11116 }
11117 \f
11118 /* Try to simplify a comparison between OP0 and a constant OP1,
11119 where CODE is the comparison code that will be tested, into a
11120 (CODE OP0 const0_rtx) form.
11122 The result is a possibly different comparison code to use.
11123 *POP1 may be updated. */
11125 static enum rtx_code
11128 {
11132 /* Get the constant we are comparing against and turn off all bits
11133 not on in our mode. */
11137 /* If we are comparing against a constant power of two and the value
11138 being compared can only have that single bit nonzero (e.g., it was
11139 `and'ed with that bit), we can replace this with a comparison
11140 with zero. */
11148 {
11151 }
11153 /* Similarly, if we are comparing a value known to be either -1 or
11154 0 with -1, change it to the opposite comparison against zero. */
11159 {
11162 }
11164 /* Do some canonicalizations based on the comparison code. We prefer
11165 comparisons against zero and then prefer equality comparisons.
11166 If we can reduce the size of a constant, we will do that too. */
11168 {
11170 /* < C is equivalent to <= (C - 1) */
11172 {
11175 /* ... fall through to LE case below. */
11176 }
11177 else
11181 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11183 {
11186 }
11188 /* If we are doing a <= 0 comparison on a value known to have
11189 a zero sign bit, we can replace this with == 0. */
11199 /* >= C is equivalent to > (C - 1). */
11201 {
11204 /* ... fall through to GT below. */
11205 }
11206 else
11210 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11212 {
11215 }
11217 /* If we are doing a > 0 comparison on a value known to have
11218 a zero sign bit, we can replace this with != 0. */
11228 /* < C is equivalent to <= (C - 1). */
11230 {
11233 /* ... fall through ... */
11234 }
11235 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11239 {
11243 }
11244 else
11248 /* unsigned <= 0 is equivalent to == 0 */
11251 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11255 {
11258 }
11262 /* >= C is equivalent to > (C - 1). */
11264 {
11267 /* ... fall through ... */
11268 }
11270 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11274 {
11278 }
11279 else
11283 /* unsigned > 0 is equivalent to != 0 */
11286 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11290 {
11293 }
11298 }
11302 }
11303 \f
11304 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11305 comparison code that will be tested.
11307 The result is a possibly different comparison code to use. *POP0 and
11308 *POP1 may be updated.
11310 It is possible that we might detect that a comparison is either always
11311 true or always false. However, we do not perform general constant
11312 folding in combine, so this knowledge isn't useful. Such tautologies
11313 should have been detected earlier. Hence we ignore all such cases. */
11315 static enum rtx_code
11317 {
11324 /* Try a few ways of applying the same transformation to both operands. */
11326 {
11327 #ifndef WORD_REGISTER_OPERATIONS
11328 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11329 so check specially. */
11344 - (GET_MODE_PRECISION
11346 {
11349 }
11350 #endif
11352 /* If both operands are the same constant shift, see if we can ignore the
11353 shift. We can if the shift is a rotate or if the bits shifted out of
11354 this shift are known to be zero for both inputs and if the type of
11355 comparison is compatible with the shift. */
11368 {
11381 else
11383 }
11385 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11386 SUBREGs are of the same mode, and, in both cases, the AND would
11387 be redundant if the comparison was done in the narrower mode,
11388 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11389 and the operand's possibly nonzero bits are 0xffffff01; in that case
11390 if we only care about QImode, we don't need the AND). This case
11391 occurs if the output mode of an scc insn is not SImode and
11392 STORE_FLAG_VALUE == 1 (e.g., the 386).
11394 Similarly, check for a case where the AND's are ZERO_EXTEND
11395 operations from some narrower mode even though a SUBREG is not
11396 present. */
11401 {
11418 {
11422 /* The resulting comparison is always unsigned since we masked
11423 off the original sign bit. */
11427 }
11434 {
11440 }
11444 }
11446 /* If both operands are NOT, we can strip off the outer operation
11447 and adjust the comparison code for swapped operands; similarly for
11448 NEG, except that this must be an equality comparison. */
11454 else
11456 }
11458 /* If the first operand is a constant, swap the operands and adjust the
11459 comparison code appropriately, but don't do this if the second operand
11460 is already a constant integer. */
11462 {
11465 }
11467 /* We now enter a loop during which we will try to simplify the comparison.
11468 For the most part, we only are concerned with comparisons with zero,
11469 but some things may really be comparisons with zero but not start
11470 out looking that way. */
11473 {
11480 HOST_WIDE_INT const_op;
11482 /* We only want to handle integral modes. This catches VOIDmode,
11483 CCmode, and the floating-point modes. An exception is that we
11484 can handle VOIDmode if OP0 is a COMPARE or a comparison
11485 operation. */
11492 /* Try to simplify the compare to constant, possibly changing the
11493 comparison op, and/or changing op1 to zero. */
11497 /* Compute some predicates to simplify code below. */
11504 /* If this is a sign bit comparison and we can do arithmetic in
11505 MODE, say that we will only be needing the sign bit of OP0. */
11512 /* Now try cases based on the opcode of OP0. If none of the cases
11513 does a "continue", we exit this loop immediately after the
11514 switch. */
11517 {
11519 /* If we are extracting a single bit from a variable position in
11520 a constant that has only a single bit set and are comparing it
11521 with zero, we can convert this into an equality comparison
11522 between the position and the location of the single bit. */
11523 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11524 have already reduced the shift count modulo the word size. */
11530 {
11538 /* Result is nonzero iff shift count is equal to I. */
11541 }
11543 /* ... fall through ... */
11548 {
11551 }
11555 /* If testing for equality, we can take the NOT of the constant. */
11558 {
11562 }
11564 /* If just looking at the sign bit, reverse the sense of the
11565 comparison. */
11567 {
11571 }
11575 /* If testing for equality, we can take the NEG of the constant. */
11578 {
11582 }
11584 /* The remaining cases only apply to comparisons with zero. */
11588 /* When X is ABS or is known positive,
11589 (neg X) is < 0 if and only if X != 0. */
11597 {
11601 }
11603 /* If we have NEG of something whose two high-order bits are the
11604 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11606 {
11610 }
11614 /* If we are testing equality and our count is a constant, we
11615 can perform the inverse operation on our RHS. */
11619 {
11623 }
11625 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11626 a particular bit. Convert it to an AND of a constant of that
11627 bit. This will be converted into a ZERO_EXTRACT. */
11631 {
11638 }
11640 /* Fall through. */
11643 /* ABS is ignorable inside an equality comparison with zero. */
11645 {
11648 }
11652 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11653 (compare FOO CONST) if CONST fits in FOO's mode and we
11654 are either testing inequality or have an unsigned
11655 comparison with ZERO_EXTEND or a signed comparison with
11656 SIGN_EXTEND. But don't do it if we don't have a compare
11657 insn of the given mode, since we'd have to revert it
11658 later on, and then we wouldn't know whether to sign- or
11659 zero-extend. */
11662 && ! unsigned_comparison_p
11666 {
11669 }
11673 /* Check for the case where we are comparing A - C1 with C2, that is
11675 (subreg:MODE (plus (A) (-C1))) op (C2)
11677 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11678 comparison in the wider mode. One of the following two conditions
11679 must be true in order for this to be valid:
11681 1. The mode extension results in the same bit pattern being added
11682 on both sides and the comparison is equality or unsigned. As
11683 C2 has been truncated to fit in MODE, the pattern can only be
11684 all 0s or all 1s.
11686 2. The mode extension results in the sign bit being copied on
11687 each side.
11689 The difficulty here is that we have predicates for A but not for
11690 (A - C1) so we need to check that C1 is within proper bounds so
11691 as to perturbate A as little as possible. */
11698 {
11707 /* (A - C1) zero-extends if it is positive and sign-extends
11708 if it is negative, C2 both zero- and sign-extends. */
11712 /* (A - C1) sign-extends if it is positive and 1-extends
11713 if it is negative, C2 both sign- and 1-extends. */
11720 /* (A - C1) always sign-extends, like C2. */
11724 {
11727 }
11728 }
11730 /* If the inner mode is narrower and we are extracting the low part,
11731 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11735 else
11738 /* ... fall through ... */
11748 {
11751 }
11755 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11756 this for equality comparisons due to pathological cases involving
11757 overflows. */
11761 {
11765 }
11767 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11770 {
11774 }
11778 /* We used to optimize signed comparisons against zero, but that
11779 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11780 arrive here as equality comparisons, or (GEU, LTU) are
11781 optimized away. No need to special-case them. */
11783 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11784 (eq B (minus A C)), whichever simplifies. We can only do
11785 this for equality comparisons due to pathological cases involving
11786 overflows. */
11790 {
11794 }
11799 {
11803 }
11805 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11806 of bits in X minus 1, is one iff X > 0. */
11811 {
11815 }
11819 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11820 if C is zero or B is a constant. */
11824 {
11828 }
11836 /* We can't do anything if OP0 is a condition code value, rather
11837 than an actual data value. */
11843 /* Get the two operands being compared. */
11846 else
11849 /* Check for the cases where we simply want the result of the
11850 earlier test or the opposite of that result. */
11854 {
11858 else
11862 {
11867 }
11868 }
11872 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11873 iff X <= 0. */
11877 {
11881 }
11885 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11886 will be converted to a ZERO_EXTRACT later. */
11890 {
11895 }
11897 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11898 zero and X is a comparison and C1 and C2 describe only bits set
11899 in STORE_FLAG_VALUE, we can compare with X. */
11907 {
11914 {
11917 }
11918 }
11920 /* If we are doing an equality comparison of an AND of a bit equal
11921 to the sign bit, replace this with a LT or GE comparison of
11922 the underlying value. */
11929 {
11933 }
11935 /* If this AND operation is really a ZERO_EXTEND from a narrower
11936 mode, the constant fits within that mode, and this is either an
11937 equality or unsigned comparison, try to do this comparison in
11938 the narrower mode.
11940 Note that in:
11942 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11943 -> (ne:DI (reg:SI 4) (const_int 0))
11945 unless TRULY_NOOP_TRUNCATION allows it or the register is
11946 known to hold a value of the required mode the
11947 transformation is invalid. */
11958 {
11961 }
11963 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11964 fits in both M1 and M2 and the SUBREG is either paradoxical
11965 or represents the low part, permute the SUBREG and the AND
11966 and try again. */
11968 {
11971 /* Require an integral mode, to avoid creating something like
11972 (AND:SF ...). */
11974 /* It is unsafe to commute the AND into the SUBREG if the
11975 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11976 not defined. As originally written the upper bits
11977 have a defined value due to the AND operation.
11978 However, if we commute the AND inside the SUBREG then
11979 they no longer have defined values and the meaning of
11980 the code has been changed. */
11982 #ifdef WORD_REGISTER_OPERATIONS
11985 #endif
11995 {
12001 }
12002 }
12004 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12008 {
12013 }
12015 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12016 (eq (and (lshiftrt X) 1) 0).
12017 Also handle the case where (not X) is expressed using xor. */
12021 {
12033 {
12034 op0
12039 }
12040 }
12044 /* If we have (compare (ashift FOO N) (const_int C)) and
12045 the high order N bits of FOO (N+1 if an inequality comparison)
12046 are known to be zero, we can do this by comparing FOO with C
12047 shifted right N bits so long as the low-order N bits of C are
12048 zero. */
12060 {
12061 /* We must perform a logical shift, not an arithmetic one,
12062 as we want the top N bits of C to be zero. */
12069 }
12071 /* If we are doing a sign bit comparison, it means we are testing
12072 a particular bit. Convert it to the appropriate AND. */
12075 {
12082 }
12084 /* If this an equality comparison with zero and we are shifting
12085 the low bit to the sign bit, we can convert this to an AND of the
12086 low-order bit. */
12090 {
12093 }
12097 /* If this is an equality comparison with zero, we can do this
12098 as a logical shift, which might be much simpler. */
12101 {
12106 }
12108 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12109 do the comparison in a narrower mode. */
12119 {
12122 }
12124 /* Likewise if OP0 is a PLUS of a sign extension with a
12125 constant, which is usually represented with the PLUS
12126 between the shifts. */
12138 {
12146 new_const);
12148 }
12150 /* ... fall through ... */
12152 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12153 the low order N bits of FOO are known to be zero, we can do this
12154 by comparing FOO with C shifted left N bits so long as no
12155 overflow occurs. Even if the low order N bits of FOO aren't known
12156 to be zero, if the comparison is >= or < we can use the same
12157 optimization and for > or <= by setting all the low
12158 order N bits in the comparison constant. */
12169 {
12170 unsigned HOST_WIDE_INT low_bits
12175 {
12176 /* If the shift was logical, then we must make the condition
12177 unsigned. */
12185 const_op
12190 }
12191 }
12193 /* If we are using this shift to extract just the sign bit, we
12194 can replace this with an LT or GE comparison. */
12199 {
12203 }
12208 }
12211 }
12213 /* Now make any compound operations involved in this comparison. Then,
12214 check for an outmost SUBREG on OP0 that is not doing anything or is
12215 paradoxical. The latter transformation must only be performed when
12216 it is known that the "extra" bits will be the same in op0 and op1 or
12217 that they don't matter. There are three cases to consider:
12219 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12220 care bits and we can assume they have any convenient value. So
12221 making the transformation is safe.
12223 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12224 In this case the upper bits of op0 are undefined. We should not make
12225 the simplification in that case as we do not know the contents of
12226 those bits.
12228 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12229 UNKNOWN. In that case we know those bits are zeros or ones. We must
12230 also be sure that they are the same as the upper bits of op1.
12232 We can never remove a SUBREG for a non-equality comparison because
12233 the sign bit is in a different place in the underlying object. */
12242 {
12244 {
12245 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12246 implemented. */
12248 {
12251 }
12252 }
12258 {
12264 }
12265 }
12267 /* We now do the opposite procedure: Some machines don't have compare
12268 insns in all modes. If OP0's mode is an integer mode smaller than a
12269 word and we can't do a compare in that mode, see if there is a larger
12270 mode for which we can do the compare. There are a number of cases in
12271 which we can use the wider mode. */
12281 {
12284 /* If this is a test for negative, we can make an explicit
12285 test of the sign bit. Test this first so we can use
12286 a paradoxical subreg to extend OP0. */
12290 {
12291 unsigned HOST_WIDE_INT sign
12298 }
12300 /* If the only nonzero bits in OP0 and OP1 are those in the
12301 narrower mode and this is an equality or unsigned comparison,
12302 we can use the wider mode. Similarly for sign-extended
12303 values, in which case it is true for all comparisons. */
12320 {
12321 /* If OP0 is an AND and we don't have an AND in MODE either,
12322 make a new AND in the proper mode. */
12330 else
12331 {
12333 {
12336 }
12337 else
12338 {
12341 }
12343 }
12344 }
12345 }
12347 /* We may have changed the comparison operands. Re-canonicalize. */
12349 {
12352 }
12354 /* If this machine only supports a subset of valid comparisons, see if we
12355 can convert an unsupported one into a supported one. */
12362 }
12363 \f
12364 /* Utility function for record_value_for_reg. Count number of
12365 rtxs in X. */
12366 static int
12368 {
12375 {
12395 }
12406 }
12407 \f
12408 /* Utility function for following routine. Called when X is part of a value
12409 being stored into last_set_value. Sets last_set_table_tick
12410 for each register mentioned. Similar to mention_regs in cse.c */
12412 static void
12414 {
12420 {
12426 {
12429 }
12432 }
12436 {
12437 /* Check for identical subexpressions. If x contains
12438 identical subexpression we only have to traverse one of
12439 them. */
12441 {
12442 /* Note that at this point x1 has already been
12443 processed. */
12447 /* If x0 and x1 are identical then there is no need to
12448 process x0. */
12452 /* If x0 is identical to a subexpression of x1 then while
12453 processing x1, x0 has already been processed. Thus we
12454 are done with x. */
12459 /* If x1 is identical to a subexpression of x0 then we
12460 still have to process the rest of x0. */
12463 {
12466 }
12467 }
12470 }
12474 }
12476 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12477 are saying that the register is clobbered and we no longer know its
12478 value. If INSN is zero, don't update reg_stat[].last_set; this is
12479 only permitted with VALUE also zero and is used to invalidate the
12480 register. */
12482 static void
12484 {
12490 /* If VALUE contains REG and we have a previous value for REG, substitute
12491 the previous value. */
12493 {
12494 rtx tem;
12496 /* Set things up so get_last_value is allowed to see anything set up to
12497 our insn. */
12501 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12502 it isn't going to be useful and will take a lot of time to process,
12503 so just use the CLOBBER. */
12506 {
12512 {
12513 /* If there are two or more occurrences of REG in VALUE,
12514 prevent the value from growing too much. */
12517 }
12520 }
12521 }
12523 /* For each register modified, show we don't know its value, that
12524 we don't know about its bitwise content, that its value has been
12525 updated, and that we don't know the location of the death of the
12526 register. */
12528 {
12540 }
12542 /* Mark registers that are being referenced in this value. */
12546 /* Now update the status of each register being set.
12547 If someone is using this register in this block, set this register
12548 to invalid since we will get confused between the two lives in this
12549 basic block. This makes using this register always invalid. In cse, we
12550 scan the table to invalidate all entries using this register, but this
12551 is too much work for us. */
12554 {
12560 else
12562 }
12564 /* The value being assigned might refer to X (like in "x++;"). In that
12565 case, we must replace it with (clobber (const_int 0)) to prevent
12566 infinite loops. */
12569 {
12573 }
12575 /* For the main register being modified, update the value, the mode, the
12576 nonzero bits, and the number of sign bit copies. */
12581 {
12589 rsp->last_set_sign_bit_copies
12591 }
12592 }
12594 /* Called via note_stores from record_dead_and_set_regs to handle one
12595 SET or CLOBBER in an insn. DATA is the instruction in which the
12596 set is occurring. */
12598 static void
12600 {
12607 {
12611 }
12614 {
12615 /* If we are setting the whole register, we know its value. Otherwise
12616 show that we don't know the value. We can handle SUBREG in
12617 some cases. */
12628 else
12630 }
12632 /* Ignore pushes, they clobber nothing. */
12635 }
12637 /* Update the records of when each REG was most recently set or killed
12638 for the things done by INSN. This is the last thing done in processing
12639 INSN in the combiner loop.
12641 We update reg_stat[], in particular fields last_set, last_set_value,
12642 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12643 last_death, and also the similar information mem_last_set (which insn
12644 most recently modified memory) and last_call_luid (which insn was the
12645 most recent subroutine call). */
12647 static void
12649 {
12650 rtx link;
12654 {
12657 {
12662 {
12667 }
12668 }
12671 }
12674 {
12675 hard_reg_set_iterator hrsi;
12677 {
12689 }
12693 /* We can't combine into a call pattern. Remember, though, that
12694 the return value register is set at this LUID. We could
12695 still replace a register with the return value from the
12696 wrong subroutine call! */
12698 }
12699 else
12701 }
12703 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12704 register present in the SUBREG, so for each such SUBREG go back and
12705 adjust nonzero and sign bit information of the registers that are
12706 known to have some zero/sign bits set.
12708 This is needed because when combine blows the SUBREGs away, the
12709 information on zero/sign bits is lost and further combines can be
12710 missed because of that. */
12712 static void
12714 {
12716 rtx set;
12724 {
12733 {
12736 }
12740 {
12743 }
12746 {
12749 }
12750 else
12752 }
12753 }
12755 /* Check if X, a register, is known to contain a value already
12756 truncated to MODE. In this case we can use a subreg to refer to
12757 the truncated value even though in the generic case we would need
12758 an explicit truncation. */
12760 static bool
12762 {
12774 }
12776 /* If X is a hard reg or a subreg record the mode that the register is
12777 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12778 to turn a truncate into a subreg using this information. Return true
12779 if traversing X is complete. */
12781 static bool
12783 {
12784 machine_mode truncated_mode;
12788 {
12799 }
12800 /* ??? For hard-regs we now record everything. We might be able to
12801 optimize this using last_set_mode. */
12804 else
12812 {
12815 }
12818 }
12820 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12821 the modes they are used in. This can help truning TRUNCATEs into
12822 SUBREGs. */
12824 static void
12826 {
12831 }
12833 /* Scan X for promoted SUBREGs. For each one found,
12834 note what it implies to the registers used in it. */
12836 static void
12838 {
12843 else
12844 {
12850 {
12860 }
12861 }
12862 }
12863 \f
12864 /* Verify that all the registers and memory references mentioned in *LOC are
12865 still valid. *LOC was part of a value set in INSN when label_tick was
12866 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12867 the invalid references with (clobber (const_int 0)) and return 1. This
12868 replacement is useful because we often can get useful information about
12869 the form of a value (e.g., if it was produced by a shift that always
12870 produces -1 or 0) even though we don't know exactly what registers it
12871 was produced from. */
12873 static int
12875 {
12882 {
12888 {
12891 /* If this is a pseudo-register that was only set once and not
12892 live at the beginning of the function, it is always valid. */
12896 && (!REGNO_REG_SET_P
12898 regno)))
12900 {
12904 }
12905 }
12908 }
12909 /* If this is a memory reference, make sure that there were no stores after
12910 it that might have clobbered the value. We don't have alias info, so we
12911 assume any store invalidates it. Moreover, we only have local UIDs, so
12912 we also assume that there were stores in the intervening basic blocks. */
12915 {
12919 }
12922 {
12924 {
12925 /* Check for identical subexpressions. If x contains
12926 identical subexpression we only have to traverse one of
12927 them. */
12929 {
12930 /* Note that at this point x0 has already been checked
12931 and found valid. */
12935 /* If x0 and x1 are identical then x is also valid. */
12939 /* If x1 is identical to a subexpression of x0 then
12940 while checking x0, x1 has already been checked. Thus
12941 it is valid and so as x. */
12946 /* If x0 is identical to a subexpression of x1 then x is
12947 valid iff the rest of x1 is valid. */
12950 return
12954 }
12959 }
12965 }
12967 /* If we haven't found a reason for it to be invalid, it is valid. */
12969 }
12971 /* Get the last value assigned to X, if known. Some registers
12972 in the value may be replaced with (clobber (const_int 0)) if their value
12973 is known longer known reliably. */
12975 static rtx
12977 {
12979 rtx value;
12982 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12983 then convert it to the desired mode. If this is a paradoxical SUBREG,
12984 we cannot predict what values the "extra" bits might have. */
12998 /* If we don't have a value, or if it isn't for this basic block and
12999 it's either a hard register, set more than once, or it's a live
13000 at the beginning of the function, return 0.
13002 Because if it's not live at the beginning of the function then the reg
13003 is always set before being used (is never used without being set).
13004 And, if it's set only once, and it's always set before use, then all
13005 uses must have the same last value, even if it's not from this basic
13006 block. */
13013 || REGNO_REG_SET_P
13017 /* If the value was set in a later insn than the ones we are processing,
13018 we can't use it even if the register was only set once. */
13023 /* If the value has all its registers valid, return it. */
13027 /* Otherwise, make a copy and replace any invalid register with
13028 (clobber (const_int 0)). If that fails for some reason, return 0. */
13035 }
13036 \f
13037 /* Return nonzero if expression X refers to a REG or to memory
13038 that is set in an instruction more recent than FROM_LUID. */
13040 static int
13042 {
13048 {
13052 #ifdef PUSH_ROUNDING
13053 /* Don't allow uses of the stack pointer to be moved,
13054 because we don't know whether the move crosses a push insn. */
13057 #endif
13059 {
13065 }
13067 }
13075 {
13077 {
13082 }
13086 }
13088 }
13089 \f
13090 /* Define three variables used for communication between the following
13091 routines. */
13096 /* Function called via note_stores from reg_dead_at_p.
13098 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13099 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13101 static void
13103 {
13113 }
13115 /* Return nonzero if REG is known to be dead at INSN.
13117 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13118 referencing REG, it is dead. If we hit a SET referencing REG, it is
13119 live. Otherwise, see if it is live or dead at the start of the basic
13120 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13121 must be assumed to be always live. */
13123 static int
13125 {
13126 basic_block block;
13129 /* Set variables for reg_dead_at_p_1. */
13135 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13136 we allow the machine description to decide whether use-and-clobber
13137 patterns are OK. */
13139 {
13143 }
13145 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13146 beginning of basic block. */
13149 {
13151 {
13161 }
13167 }
13169 /* Look at live-in sets for the basic block that we were in. */
13175 }
13176 \f
13177 /* Note hard registers in X that are used. */
13179 static void
13181 {
13187 {
13191 CASE_CONST_ANY:
13196 #ifdef HAVE_cc0
13197 /* CC0 must die in the insn after it is set, so we don't need to take
13198 special note of it here. */
13200 #endif
13204 /* If we are clobbering a MEM, mark any hard registers inside the
13205 address as used. */
13212 /* A hard reg in a wide mode may really be multiple registers.
13213 If so, mark all of them just like the first. */
13215 {
13216 /* None of this applies to the stack, frame or arg pointers. */
13218 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
13220 #endif
13221 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
13223 #endif
13228 }
13232 {
13233 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13234 the address. */
13246 }
13251 }
13253 /* Recursively scan the operands of this expression. */
13255 {
13259 {
13263 {
13268 }
13269 }
13270 }
13271 }
13272 \f
13273 /* Remove register number REGNO from the dead registers list of INSN.
13275 Return the note used to record the death, if there was one. */
13277 rtx
13279 {
13286 }
13288 /* For each register (hardware or pseudo) used within expression X, if its
13289 death is in an instruction with luid between FROM_LUID (inclusive) and
13290 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13291 list headed by PNOTES.
13293 That said, don't move registers killed by maybe_kill_insn.
13295 This is done when X is being merged by combination into TO_INSN. These
13296 notes will then be distributed as needed. */
13298 static void
13301 {
13307 {
13311 /* Don't move the register if it gets killed in between from and to. */
13320 {
13323 /* It is possible for the call above to return 0. This can occur
13324 when last_death points to I2 or I1 that we combined with.
13325 In that case make a new note.
13327 We must also check for the case where X is a hard register
13328 and NOTE is a death note for a range of hard registers
13329 including X. In that case, we must put REG_DEAD notes for
13330 the remaining registers in place of NOTE. */
13335 {
13344 }
13346 /* If we didn't find any note, or if we found a REG_DEAD note that
13347 covers only part of the given reg, and we have a multi-reg hard
13348 register, then to be safe we must check for REG_DEAD notes
13349 for each register other than the first. They could have
13350 their own REG_DEAD notes lying around. */
13357 {
13364 else
13370 }
13373 {
13376 }
13377 else
13379 }
13382 }
13385 {
13390 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13391 that accesses one word of a multi-word item, some
13392 piece of everything register in the expression is used by
13393 this insn, so remove any old death. */
13394 /* ??? So why do we test for equality of the sizes? */
13403 {
13406 }
13408 /* If this is some other SUBREG, we know it replaces the entire
13409 value, so use that as the destination. */
13413 /* If this is a MEM, adjust deaths of anything used in the address.
13414 For a REG (the only other possibility), the entire value is
13415 being replaced so the old value is not used in this insn. */
13421 }
13430 {
13432 {
13437 }
13440 }
13441 }
13442 \f
13443 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13444 pattern of an insn. X must be a REG. */
13446 static int
13448 {
13452 {
13454 rtx target;
13461 else
13478 }
13486 }
13487 \f
13488 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13489 as appropriate. I3 and I2 are the insns resulting from the combination
13490 insns including FROM (I2 may be zero).
13492 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13493 not need REG_DEAD notes because they are being substituted for. This
13494 saves searching in the most common cases.
13496 Each note in the list is either ignored or placed on some insns, depending
13497 on the type of note. */
13499 static void
13502 {
13504 rtx tem_note;
13508 {
13513 {
13516 /* Doesn't matter much where we put this, as long as it's somewhere.
13517 It is preferable to keep these notes on branches, which is most
13518 likely to be i3. */
13525 else
13526 {
13529 }
13533 /* These notes must remain with the call or trapping instruction. */
13538 else
13539 {
13545 /* ??? Otherwise assume we've combined things such that we
13546 can now prove that the instructions can't trap. Drop the
13547 note in this case. */
13548 }
13552 /* ??? How to distribute between i3-i1. Assume i3 contains the
13553 entire adjustment. Assert i3 contains at least some adjust. */
13555 {
13557 /* fixup_args_size_notes looks at REG_NORETURN note,
13558 so ensure the note is placed there first. */
13560 {
13564 {
13570 }
13571 }
13573 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13574 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13577 && !ACCUMULATE_OUTGOING_ARGS
13579 }
13586 /* These notes must remain with the call. It should not be
13587 possible for both I2 and I3 to be a call. */
13590 else
13591 {
13594 }
13598 /* Any clobbers for i3 may still exist, and so we must process
13599 REG_UNUSED notes from that insn.
13601 Any clobbers from i2 or i1 can only exist if they were added by
13602 recog_for_combine. In that case, recog_for_combine created the
13603 necessary REG_UNUSED notes. Trying to keep any original
13604 REG_UNUSED notes from these insns can cause incorrect output
13605 if it is for the same register as the original i3 dest.
13606 In that case, we will notice that the register is set in i3,
13607 and then add a REG_UNUSED note for the destination of i3, which
13608 is wrong. However, it is possible to have REG_UNUSED notes from
13609 i2 or i1 for register which were both used and clobbered, so
13610 we keep notes from i2 or i1 if they will turn into REG_DEAD
13611 notes. */
13613 /* If this register is set or clobbered in I3, put the note there
13614 unless there is one already. */
13616 {
13624 }
13625 /* Otherwise, if this register is used by I3, then this register
13626 now dies here, so we must put a REG_DEAD note here unless there
13627 is one already. */
13633 {
13636 }
13642 /* These notes say something about results of an insn. We can
13643 only support them if they used to be on I3 in which case they
13644 remain on I3. Otherwise they are ignored.
13646 If the note refers to an expression that is not a constant, we
13647 must also ignore the note since we cannot tell whether the
13648 equivalence is still true. It might be possible to do
13649 slightly better than this (we only have a problem if I2DEST
13650 or I1DEST is present in the expression), but it doesn't
13651 seem worth the trouble. */
13659 /* These notes say something about how a register is used. They must
13660 be present on any use of the register in I2 or I3. */
13665 {
13668 else
13670 }
13675 /* This can show up in several ways -- either directly in the
13676 pattern, or hidden off in the constant pool with (or without?)
13677 a REG_EQUAL note. */
13678 /* ??? Ignore the without-reg_equal-note problem for now. */
13690 {
13693 else
13695 }
13697 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13698 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13699 there. */
13704 {
13711 }
13717 {
13725 }
13729 /* This note says something about the value of a register prior
13730 to the execution of an insn. It is too much trouble to see
13731 if the note is still correct in all situations. It is better
13732 to simply delete it. */
13736 /* If we replaced the right hand side of FROM_INSN with a
13737 REG_EQUAL note, the original use of the dying register
13738 will not have been combined into I3 and I2. In such cases,
13739 FROM_INSN is guaranteed to be the first of the combined
13740 instructions, so we simply need to search back before
13741 FROM_INSN for the previous use or set of this register,
13742 then alter the notes there appropriately.
13744 If the register is used as an input in I3, it dies there.
13745 Similarly for I2, if it is nonzero and adjacent to I3.
13747 If the register is not used as an input in either I3 or I2
13748 and it is not one of the registers we were supposed to eliminate,
13749 there are two possibilities. We might have a non-adjacent I2
13750 or we might have somehow eliminated an additional register
13751 from a computation. For example, we might have had A & B where
13752 we discover that B will always be zero. In this case we will
13753 eliminate the reference to A.
13755 In both cases, we must search to see if we can find a previous
13756 use of A and put the death note there. */
13762 else
13763 {
13774 && !(i2mod
13776 i2mod_old_rhs)))
13781 /* If the new I2 sets the same register that is marked dead
13782 in the note, the note now should not be put on I2, as the
13783 note refers to a previous incarnation of the reg. */
13786 }
13789 {
13793 {
13795 {
13799 }
13801 /* If the register is being set at TEM_INSN, see if that is all
13802 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13803 into a REG_UNUSED note instead. Don't delete sets to
13804 global register vars. */
13808 {
13811 #ifdef HAVE_cc0
13813 #endif
13821 ;
13823 /* Verify that it was the set, and not a clobber that
13824 modified the register.
13826 CC0 targets must be careful to maintain setter/user
13827 pairs. If we cannot delete the setter due to side
13828 effects, mark the user with an UNUSED note instead
13829 of deleting it. */
13833 #ifdef HAVE_cc0
13837 #endif
13838 )
13839 {
13840 /* Move the notes and links of TEM_INSN elsewhere.
13841 This might delete other dead insns recursively.
13842 First set the pattern to something that won't use
13843 any register. */
13857 #ifdef HAVE_cc0
13858 /* Delete the setter too. */
13860 {
13873 }
13874 #endif
13875 }
13876 else
13877 {
13880 /* If there isn't already a REG_UNUSED note, put one
13881 here. Do not place a REG_DEAD note, even if
13882 the register is also used here; that would not
13883 match the algorithm used in lifetime analysis
13884 and can cause the consistency check in the
13885 scheduler to fail. */
13890 }
13891 }
13895 {
13898 /* If we are doing a 3->2 combination, and we have a
13899 register which formerly died in i3 and was not used
13900 by i2, which now no longer dies in i3 and is used in
13901 i2 but does not die in i2, and place is between i2
13902 and i3, then we may need to move a link from place to
13903 i2. */
13905 && from_insn
13908 {
13912 }
13914 }
13918 }
13920 }
13922 /* If the register is set or already dead at PLACE, we needn't do
13923 anything with this note if it is still a REG_DEAD note.
13924 We check here if it is set at all, not if is it totally replaced,
13925 which is what `dead_or_set_p' checks, so also check for it being
13926 set partially. */
13929 {
13935 {
13936 /* Unless the register previously died in PLACE, clear
13937 last_death. [I no longer understand why this is
13938 being done.] */
13942 }
13943 else
13946 /* If this is a death note for a hard reg that is occupying
13947 multiple registers, ensure that we are still using all
13948 parts of the object. If we find a piece of the object
13949 that is unused, we must arrange for an appropriate REG_DEAD
13950 note to be added for it. However, we can't just emit a USE
13951 and tag the note to it, since the register might actually
13952 be dead; so we recourse, and the recursive call then finds
13953 the previous insn that used this register. */
13957 {
13966 {
13969 }
13972 {
13973 /* Put only REG_DEAD notes for pieces that are
13974 not already dead or set. */
13978 {
13985 {
13987 NULL_RTX);
13991 NULL_RTX);
13992 }
13997 {
13999 {
14003 }
14007 {
14010 }
14011 }
14012 }
14015 }
14016 }
14017 }
14021 /* Any other notes should not be present at this point in the
14022 compilation. */
14024 }
14027 {
14030 }
14034 }
14035 }
14036 \f
14037 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14038 I3, I2, and I1 to new locations. This is also called to add a link
14039 pointing at I3 when I3's destination is changed. */
14041 static void
14043 {
14047 {
14054 /* If the insn that this link points to is a NOTE, ignore it. */
14063 {
14066 {
14082 }
14085 }
14086 else
14096 /* A LOG_LINK is defined as being placed on the first insn that uses
14097 a register and points to the insn that sets the register. Start
14098 searching at the next insn after the target of the link and stop
14099 when we reach a set of the register or the end of the basic block.
14101 Note that this correctly handles the link that used to point from
14102 I3 to I2. Also note that not much searching is typically done here
14103 since most links don't point very far away. */
14112 {
14116 }
14119 {
14122 }
14126 /* If we found a place to put the link, place it there unless there
14127 is already a link to the same insn as LINK at that point. */
14130 {
14138 {
14142 /* Set added_links_insn to the earliest insn we added a
14143 link to. */
14147 }
14148 }
14149 }
14150 }
14151 \f
14152 /* Check for any register or memory mentioned in EQUIV that is not
14153 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14154 of EXPR where some registers may have been replaced by constants. */
14156 static bool
14158 {
14161 {
14166 }
14168 }
14169 \f
14170 DEBUG_FUNCTION void
14172 {
14173 fprintf
14175 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14177 }
14179 void
14181 {
14182 fprintf
14184 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14186 }
14187 \f
14188 /* Try combining insns through substitution. */
14189 static unsigned int
14191 {
14201 rebuild_jump_labels_after_combine
14204 /* Combining insns may have turned an indirect jump into a
14205 direct jump. Rebuild the JUMP_LABEL fields of jumping
14206 instructions. */
14208 {
14213 }
14217 }
14222 {
14232 };
14235 {
14239 {}
14241 /* opt_pass methods: */
14244 {
14246 }
14252 rtl_opt_pass *
14254 {
14256 }