| blob | 2a66fd5c8bdf6dbccc407ab3290ee8723bb71448 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
96 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
106 #ifndef LOAD_EXTEND_OP
107 #define LOAD_EXTEND_OP(M) UNKNOWN
108 #endif
110 /* Number of attempts to combine instructions in this function. */
114 /* Number of attempts that got as far as substitution in this function. */
118 /* Number of instructions combined with added SETs in this function. */
122 /* Number of instructions combined in this function. */
126 /* Totals over entire compilation. */
130 /* combine_instructions may try to replace the right hand side of the
131 second instruction with the value of an associated REG_EQUAL note
132 before throwing it at try_combine. That is problematic when there
133 is a REG_DEAD note for a register used in the old right hand side
134 and can cause distribute_notes to do wrong things. This is the
135 second instruction if it has been so modified, null otherwise. */
139 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
143 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
146 \f
148 /* Record last point of death of (hard or pseudo) register n. */
151 /* Record last point of modification of (hard or pseudo) register n. */
154 /* The next group of fields allows the recording of the last value assigned
155 to (hard or pseudo) register n. We use this information to see if an
156 operation being processed is redundant given a prior operation performed
157 on the register. For example, an `and' with a constant is redundant if
158 all the zero bits are already known to be turned off.
160 We use an approach similar to that used by cse, but change it in the
161 following ways:
163 (1) We do not want to reinitialize at each label.
164 (2) It is useful, but not critical, to know the actual value assigned
165 to a register. Often just its form is helpful.
167 Therefore, we maintain the following fields:
169 last_set_value the last value assigned
170 last_set_label records the value of label_tick when the
171 register was assigned
172 last_set_table_tick records the value of label_tick when a
173 value using the register is assigned
174 last_set_invalid set to nonzero when it is not valid
175 to use the value of this register in some
176 register's value
178 To understand the usage of these tables, it is important to understand
179 the distinction between the value in last_set_value being valid and
180 the register being validly contained in some other expression in the
181 table.
183 (The next two parameters are out of date).
185 reg_stat[i].last_set_value is valid if it is nonzero, and either
186 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
188 Register I may validly appear in any expression returned for the value
189 of another register if reg_n_sets[i] is 1. It may also appear in the
190 value for register J if reg_stat[j].last_set_invalid is zero, or
191 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
193 If an expression is found in the table containing a register which may
194 not validly appear in an expression, the register is replaced by
195 something that won't match, (clobber (const_int 0)). */
197 /* Record last value assigned to (hard or pseudo) register n. */
199 rtx last_set_value;
201 /* Record the value of label_tick when an expression involving register n
202 is placed in last_set_value. */
206 /* Record the value of label_tick when the value for register n is placed in
207 last_set_value. */
211 /* These fields are maintained in parallel with last_set_value and are
212 used to store the mode in which the register was last set, the bits
213 that were known to be zero when it was last set, and the number of
214 sign bits copies it was known to have when it was last set. */
220 /* Set nonzero if references to register n in expressions should not be
221 used. last_set_invalid is set nonzero when this register is being
222 assigned to and last_set_table_tick == label_tick. */
226 /* Some registers that are set more than once and used in more than one
227 basic block are nevertheless always set in similar ways. For example,
228 a QImode register may be loaded from memory in two places on a machine
229 where byte loads zero extend.
231 We record in the following fields if a register has some leading bits
232 that are always equal to the sign bit, and what we know about the
233 nonzero bits of a register, specifically which bits are known to be
234 zero.
236 If an entry is zero, it means that we don't know anything special. */
242 /* Record the value of the label_tick when the last truncation
243 happened. The field truncated_to_mode is only valid if
244 truncation_label == label_tick. */
248 /* Record the last truncation seen for this register. If truncation
249 is not a nop to this mode we might be able to save an explicit
250 truncation if we know that value already contains a truncated
251 value. */
254 };
259 /* One plus the highest pseudo for which we track REG_N_SETS.
260 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
261 but during combine_split_insns new pseudos can be created. As we don't have
262 updated DF information in that case, it is hard to initialize the array
263 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
264 so instead of growing the arrays, just assume all newly created pseudos
265 during combine might be set multiple times. */
269 /* Record the luid of the last insn that invalidated memory
270 (anything that writes memory, and subroutine calls, but not pushes). */
274 /* Record the luid of the last CALL_INSN
275 so we can tell whether a potential combination crosses any calls. */
279 /* When `subst' is called, this is the insn that is being modified
280 (by combining in a previous insn). The PATTERN of this insn
281 is still the old pattern partially modified and it should not be
282 looked at, but this may be used to examine the successors of the insn
283 to judge whether a simplification is valid. */
287 /* This is the lowest LUID that `subst' is currently dealing with.
288 get_last_value will not return a value if the register was set at or
289 after this LUID. If not for this mechanism, we could get confused if
290 I2 or I1 in try_combine were an insn that used the old value of a register
291 to obtain a new value. In that case, we might erroneously get the
292 new value of the register when we wanted the old one. */
296 /* This contains any hard registers that are used in newpat; reg_dead_at_p
297 must consider all these registers to be always live. */
301 /* This is an insn to which a LOG_LINKS entry has been added. If this
302 insn is the earlier than I2 or I3, combine should rescan starting at
303 that location. */
307 /* Basic block in which we are performing combines. */
311 \f
312 /* Length of the currently allocated uid_insn_cost array. */
316 /* The following array records the insn_rtx_cost for every insn
317 in the instruction stream. */
321 /* The following array records the LOG_LINKS for every insn in the
322 instruction stream as struct insn_link pointers. */
328 };
332 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
333 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
335 #define FOR_EACH_LOG_LINK(L, INSN) \
336 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
338 /* Links for LOG_LINKS are allocated from this obstack. */
342 /* Allocate a link. */
346 {
354 }
356 /* Incremented for each basic block. */
360 /* Reset to label_tick for each extended basic block in scanning order. */
364 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
365 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
369 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
370 be safely used. It is zero while computing them and after combine has
371 completed. This former test prevents propagating values based on
372 previously set values, which can be incorrect if a variable is modified
373 in a loop. */
377 \f
378 /* Record one modification to rtl structure
379 to be undone by storing old_contents into *where. */
383 struct undo
384 {
389 };
391 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
392 num_undo says how many are currently recorded.
394 other_insn is nonzero if we have modified some other insn in the process
395 of working on subst_insn. It must be verified too. */
397 struct undobuf
398 {
402 };
406 /* Number of times the pseudo being substituted for
407 was found and replaced. */
412 machine_mode,
416 machine_mode,
488 \f
490 /* It is not safe to use ordinary gen_lowpart in combine.
491 See comments in gen_lowpart_for_combine. */
492 #undef RTL_HOOKS_GEN_LOWPART
493 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
495 /* Our implementation of gen_lowpart never emits a new pseudo. */
496 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
497 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
499 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
500 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
502 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
503 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
505 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
506 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
510 \f
511 /* Convenience wrapper for the canonicalize_comparison target hook.
512 Target hooks cannot use enum rtx_code. */
516 {
520 }
522 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
523 PATTERN can not be split. Otherwise, it returns an insn sequence.
524 This is a wrapper around split_insns which ensures that the
525 reg_stat vector is made larger if the splitter creates a new
526 register. */
530 {
539 }
541 /* This is used by find_single_use to locate an rtx in LOC that
542 contains exactly one use of DEST, which is typically either a REG
543 or CC0. It returns a pointer to the innermost rtx expression
544 containing DEST. Appearances of DEST that are being used to
545 totally replace it are not counted. */
549 {
558 {
562 CASE_CONST_ANY:
567 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
568 of a REG that occupies all of the REG, the insn uses DEST if
569 it is mentioned in the destination or the source. Otherwise, we
570 need just check the source. */
590 }
592 /* If it wasn't one of the common cases above, check each expression and
593 vector of this code. Look for a unique usage of DEST. */
597 {
599 {
604 else
610 /* Duplicate usage. */
612 }
614 {
618 {
624 else
631 }
632 }
633 }
636 }
639 /* See if DEST, produced in INSN, is used only a single time in the
640 sequel. If so, return a pointer to the innermost rtx expression in which
641 it is used.
643 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
645 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
646 care about REG_DEAD notes or LOG_LINKS.
648 Otherwise, we find the single use by finding an insn that has a
649 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
650 only referenced once in that insn, we know that it must be the first
651 and last insn referencing DEST. */
655 {
656 basic_block bb;
662 {
672 }
682 {
688 {
693 }
694 }
697 }
698 \f
699 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
700 insn. The substitution can be undone by undo_all. If INTO is already
701 set to NEWVAL, do not record this change. Because computing NEWVAL might
702 also call SUBST, we have to compute it before we put anything into
703 the undo table. */
705 static void
707 {
714 /* We'd like to catch as many invalid transformations here as
715 possible. Unfortunately, there are way too many mode changes
716 that are perfectly valid, so we'd waste too much effort for
717 little gain doing the checks here. Focus on catching invalid
718 transformations involving integer constants. */
721 {
722 /* Sanity check that we're replacing oldval with a CONST_INT
723 that is a valid sign-extension for the original mode. */
727 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
728 CONST_INT is not valid, because after the replacement, the
729 original mode would be gone. Unfortunately, we can't tell
730 when do_SUBST is called to replace the operand thereof, so we
731 perform this test on oldval instead, checking whether an
732 invalid replacement took place before we got here. */
737 }
741 else
750 }
752 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
754 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
755 for the value of a HOST_WIDE_INT value (including CONST_INT) is
756 not safe. */
758 static void
760 {
769 else
778 }
780 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
782 /* Similar to SUBST, but just substitute the mode. This is used when
783 changing the mode of a pseudo-register, so that any other
784 references to the entry in the regno_reg_rtx array will change as
785 well. */
787 static void
789 {
798 else
807 }
809 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
811 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
813 static void
815 {
824 else
833 }
835 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
836 \f
837 /* Subroutine of try_combine. Determine whether the replacement patterns
838 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
839 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
840 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
841 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
842 of all the instructions can be estimated and the replacements are more
843 expensive than the original sequence. */
845 static bool
848 {
853 /* Lookup the original insn_rtx_costs. */
858 {
861 {
865 }
866 else
867 {
871 }
872 }
873 else
874 {
877 }
879 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
880 correct that. */
885 /* Calculate the replacement insn_rtx_costs. */
888 {
892 }
893 else
894 {
897 }
900 {
906 {
909 }
910 else
912 }
914 /* Disallow this combination if both new_cost and old_cost are greater than
915 zero, and new_cost is greater than old cost. */
919 {
938 else
940 }
945 /* Update the uid_insn_cost array with the replacement costs. */
949 {
953 }
956 }
959 /* Delete any insns that copy a register to itself. */
961 static void
963 {
965 basic_block bb;
968 {
970 {
973 {
978 }
979 }
980 }
981 }
983 \f
984 /* Return false if we do not want to (or cannot) combine DEF. */
985 static bool
987 {
988 /* Do not consider if it is pre/post modification in MEM. */
994 /* Do not combine frame pointer adjustments. */
997 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1005 }
1007 /* Return false if we do not want to (or cannot) combine USE. */
1008 static bool
1010 {
1011 /* Do not consider the usage of the stack pointer by function call. */
1016 }
1018 /* Fill in log links field for all insns. */
1020 static void
1022 {
1023 basic_block bb;
1030 /* Pass through each block from the end, recording the uses of each
1031 register and establishing log links when def is encountered.
1032 Note that we do not clear next_use array in order to save time,
1033 so we have to test whether the use is in the same basic block as def.
1035 There are a few cases below when we do not consider the definition or
1036 usage -- these are taken from original flow.c did. Don't ask me why it is
1037 done this way; I don't know and if it works, I don't want to know. */
1040 {
1042 {
1046 /* Log links are created only once. */
1050 {
1066 /* flow.c claimed:
1068 We don't build a LOG_LINK for hard registers contained
1069 in ASM_OPERANDs. If these registers get replaced,
1070 we might wind up changing the semantics of the insn,
1071 even if reload can make what appear to be valid
1072 assignments later. */
1077 /* Don't add duplicate links between instructions. */
1086 }
1091 }
1092 }
1095 }
1097 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1098 true if we found a LOG_LINK that proves that A feeds B. This only works
1099 if there are no instructions between A and B which could have a link
1100 depending on A, since in that case we would not record a link for B.
1101 We also check the implicit dependency created by a cc0 setter/user
1102 pair. */
1104 static bool
1106 {
1114 }
1115 \f
1116 /* Main entry point for combiner. F is the first insn of the function.
1117 NREGS is the first unused pseudo-reg number.
1119 Return nonzero if the combiner has turned an indirect jump
1120 instruction into a direct jump. */
1121 static int
1123 {
1128 basic_block last_bb;
1148 /* Allocate array for insn info. */
1156 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1157 problems when, for example, we have j <<= 1 in a loop. */
1162 /* Scan all SETs and see if we can deduce anything about what
1163 bits are known to be zero for some registers and how many copies
1164 of the sign bit are known to exist for those registers.
1166 Also set any known values so that we can use it while searching
1167 for what bits are known to be set. */
1170 /* Allow the entry block and the first block to fall into the same EBB.
1171 Conceptually the incoming promotions are assigned to the entry block. */
1176 {
1181 label_tick++;
1189 {
1190 rtx links;
1196 insn);
1203 insn);
1205 /* Record the current insn_rtx_cost of this instruction. */
1208 optimize_this_for_speed_p);
1212 }
1213 }
1217 /* Now scan all the insns in forward order. */
1225 {
1231 label_tick++;
1241 {
1255 /* See if we know about function return values before this
1256 insn based upon SUBREG flags. */
1259 /* See if we can find hardregs and subreg of pseudos in
1260 narrower modes. This could help turning TRUNCATEs
1261 into SUBREGs. */
1264 /* Try this insn with each insn it links back to. */
1270 {
1273 }
1275 /* Try each sequence of three linked insns ending with this one. */
1279 {
1282 /* If the linked insn has been replaced by a note, then there
1283 is no point in pursuing this chain any further. */
1291 {
1294 }
1295 }
1297 /* Try to combine a jump insn that uses CC0
1298 with a preceding insn that sets CC0, and maybe with its
1299 logical predecessor as well.
1300 This is how we make decrement-and-branch insns.
1301 We need this special code because data flow connections
1302 via CC0 do not get entered in LOG_LINKS. */
1309 {
1320 }
1322 /* Do the same for an insn that explicitly references CC0. */
1329 {
1340 }
1342 /* Finally, see if any of the insns that this insn links to
1343 explicitly references CC0. If so, try this insn, that insn,
1344 and its predecessor if it sets CC0. */
1346 {
1358 }
1360 /* Try combining an insn with two different insns whose results it
1361 uses. */
1371 {
1374 }
1376 /* Try four-instruction combinations. */
1379 {
1383 /* If the linked insn has been replaced by a note, then there
1384 is no point in pursuing this chain any further. */
1389 {
1393 /* I0 -> I1 -> I2 -> I3. */
1399 {
1402 }
1403 /* I0, I1 -> I2, I2 -> I3. */
1410 {
1413 }
1414 }
1417 {
1421 /* I0 -> I2; I1, I2 -> I3. */
1427 {
1430 }
1431 /* I0 -> I1; I1, I2 -> I3. */
1437 {
1440 }
1441 }
1442 }
1444 /* Try this insn with each REG_EQUAL note it links back to. */
1446 {
1452 /* Avoid using a register that may already been marked
1453 dead by an earlier instruction. */
1458 {
1459 /* Temporarily replace the set's source with the
1460 contents of the REG_EQUAL note. The insn will
1461 be deleted or recognized by try_combine. */
1469 last_combined_insn);
1472 {
1475 }
1477 }
1478 }
1483 retry:
1484 ;
1485 }
1486 }
1493 /* Clean up. */
1499 {
1502 {
1505 }
1507 }
1517 /* Make recognizer allow volatile MEMs again. */
1521 }
1523 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1525 static void
1527 {
1533 }
1534 \f
1535 /* Set up any promoted values for incoming argument registers. */
1537 static void
1539 {
1540 tree arg;
1545 {
1550 /* Only continue if the incoming argument is in a register. */
1554 /* Determine, if possible, whether all call sites of the current
1555 function lie within the current compilation unit. (This does
1556 take into account the exporting of a function via taking its
1557 address, and so forth.) */
1560 /* The mode and signedness of the argument before any promotions happen
1561 (equal to the mode of the pseudo holding it at that stage). */
1565 /* The mode and signedness of the argument after any source language and
1566 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1570 /* The mode and signedness of the argument as it is actually passed,
1571 see assign_parm_setup_reg in function.c. */
1575 /* The mode of the register in which the argument is being passed. */
1578 /* Eliminate sign extensions in the callee when:
1579 (a) A mode promotion has occurred; */
1582 /* (b) The mode of the register is the same as the mode of
1583 the argument as it is passed; */
1586 /* (c) There's no language level extension; */
1588 ;
1589 /* (c.1) All callers are from the current compilation unit. If that's
1590 the case we don't have to rely on an ABI, we only have to know
1591 what we're generating right now, and we know that we will do the
1592 mode1 to mode2 promotion with the given sign. */
1595 /* (c.2) The combination of the two promotions is useful. This is
1596 true when the signs match, or if the first promotion is unsigned.
1597 In the later case, (sign_extend (zero_extend x)) is the same as
1598 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1604 /* Record that the value was promoted from mode1 to mode3,
1605 so that any sign extension at the head of the current
1606 function may be eliminated. */
1610 }
1611 }
1613 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1614 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1615 because some machines (maybe most) will actually do the sign-extension and
1616 this is the conservative approach.
1618 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1619 kludge. */
1621 static rtx
1623 {
1631 }
1633 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1634 and SET. */
1636 static void
1638 rtx x)
1639 {
1649 {
1653 }
1655 /* Don't call nonzero_bits if it cannot change anything. */
1657 {
1662 }
1664 /* Don't call num_sign_bit_copies if it cannot change anything. */
1666 {
1669 {
1673 }
1676 }
1677 }
1679 /* Called via note_stores. If X is a pseudo that is narrower than
1680 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1682 If we are setting only a portion of X and we can't figure out what
1683 portion, assume all bits will be used since we don't know what will
1684 be happening.
1686 Similarly, set how many bits of X are known to be copies of the sign bit
1687 at all locations in the function. This is the smallest number implied
1688 by any set of X. */
1690 static void
1692 {
1697 /* If this register is undefined at the start of the file, we can't
1698 say what its contents were. */
1699 && ! REGNO_REG_SET_P
1702 {
1706 {
1710 }
1712 /* If this register is being initialized using itself, and the
1713 register is uninitialized in this basic block, and there are
1714 no LOG_LINKS which set the register, then part of the
1715 register is uninitialized. In that case we can't assume
1716 anything about the number of nonzero bits.
1718 ??? We could do better if we checked this in
1719 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1720 could avoid making assumptions about the insn which initially
1721 sets the register, while still using the information in other
1722 insns. We would have to be careful to check every insn
1723 involved in the combination. */
1729 {
1736 {
1740 }
1741 }
1743 /* If this is a complex assignment, see if we can convert it into a
1744 simple assignment. */
1747 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1748 set what we know about X. */
1754 else
1755 {
1758 }
1759 }
1760 }
1761 \f
1762 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1763 optionally insns that were previously combined into I3 or that will be
1764 combined into the merger of INSN and I3. The order is PRED, PRED2,
1765 INSN, SUCC, SUCC2, I3.
1767 Return 0 if the combination is not allowed for any reason.
1769 If the combination is allowed, *PDEST will be set to the single
1770 destination of INSN and *PSRC to the single source, and this function
1771 will return 1. */
1773 static int
1777 {
1782 rtx link;
1787 {
1789 {
1794 }
1799 }
1803 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1804 or a PARALLEL consisting of such a SET and CLOBBERs.
1806 If INSN has CLOBBER parallel parts, ignore them for our processing.
1807 By definition, these happen during the execution of the insn. When it
1808 is merged with another insn, all bets are off. If they are, in fact,
1809 needed and aren't also supplied in I3, they may be added by
1810 recog_for_combine. Otherwise, it won't match.
1812 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1813 note.
1815 Get the source and destination of INSN. If more than one, can't
1816 combine. */
1822 {
1824 {
1828 {
1829 /* This is important to combine floating point insns
1830 for the SH4 port. */
1832 /* Combining an isolated USE doesn't make sense.
1833 We depend here on combinable_i3pat to reject them. */
1834 /* The code below this loop only verifies that the inputs of
1835 the SET in INSN do not change. We call reg_set_between_p
1836 to verify that the REG in the USE does not change between
1837 I3 and INSN.
1838 If the USE in INSN was for a pseudo register, the matching
1839 insn pattern will likely match any register; combining this
1840 with any other USE would only be safe if we knew that the
1841 used registers have identical values, or if there was
1842 something to tell them apart, e.g. different modes. For
1843 now, we forgo such complicated tests and simply disallow
1844 combining of USES of pseudo registers with any other USE. */
1847 {
1852 do
1853 {
1863 }
1865 }
1868 /* We can ignore CLOBBERs. */
1873 /* Ignore SETs whose result isn't used but not those that
1874 have side-effects. */
1880 /* If we have already found a SET, this is a second one and
1881 so we cannot combine with this insn. */
1889 /* Anything else means we can't combine. */
1891 }
1892 }
1895 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1896 so don't do anything with it. */
1899 }
1900 else
1906 /* The simplification in expand_field_assignment may call back to
1907 get_last_value, so set safe guard here. */
1913 /* Do not eliminate user-specified register if it is in an
1914 asm input because we may break the register asm usage defined
1915 in GCC manual if allow to do so.
1916 Be aware that this may cover more cases than we expect but this
1917 should be harmless. */
1922 /* Don't eliminate a store in the stack pointer. */
1924 /* Don't combine with an insn that sets a register to itself if it has
1925 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1927 /* Can't merge an ASM_OPERANDS. */
1929 /* Can't merge a function call. */
1931 /* Don't eliminate a function call argument. */
1937 /* Don't substitute into an incremented register. */
1941 /* Don't substitute into a non-local goto, this confuses CFG. */
1943 /* Make sure that DEST is not used after SUCC but before I3. */
1944 || (!all_adjacent
1945 && ((succ2
1949 /* Make sure that the value that is to be substituted for the register
1950 does not use any registers whose values alter in between. However,
1951 If the insns are adjacent, a use can't cross a set even though we
1952 think it might (this can happen for a sequence of insns each setting
1953 the same destination; last_set of that register might point to
1954 a NOTE). If INSN has a REG_EQUIV note, the register is always
1955 equivalent to the memory so the substitution is valid even if there
1956 are intervening stores. Also, don't move a volatile asm or
1957 UNSPEC_VOLATILE across any other insns. */
1958 || (! all_adjacent
1964 /* Don't combine across a CALL_INSN, because that would possibly
1965 change whether the life span of some REGs crosses calls or not,
1966 and it is a pain to update that information.
1967 Exception: if source is a constant, moving it later can't hurt.
1968 Accept that as a special case. */
1972 /* DEST must either be a REG or CC0. */
1974 {
1975 /* If register alignment is being enforced for multi-word items in all
1976 cases except for parameters, it is possible to have a register copy
1977 insn referencing a hard register that is not allowed to contain the
1978 mode being copied and which would not be valid as an operand of most
1979 insns. Eliminate this problem by not combining with such an insn.
1981 Also, on some machines we don't want to extend the life of a hard
1982 register. */
1987 /* Don't extend the life of a hard register unless it is
1988 user variable (if we have few registers) or it can't
1989 fit into the desired register (meaning something special
1990 is going on).
1991 Also avoid substituting a return register into I3, because
1992 reload can't handle a conflict with constraints of other
1993 inputs. */
1997 }
2005 {
2008 /* If the clobber represents an earlyclobber operand, we must not
2009 substitute an expression containing the clobbered register.
2010 As we do not analyze the constraint strings here, we have to
2011 make the conservative assumption. However, if the register is
2012 a fixed hard reg, the clobber cannot represent any operand;
2013 we leave it up to the machine description to either accept or
2014 reject use-and-clobber patterns. */
2020 }
2022 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2023 or not), reject, unless nothing volatile comes between it and I3 */
2026 {
2027 /* Make sure neither succ nor succ2 contains a volatile reference. */
2032 /* We'll check insns between INSN and I3 below. */
2033 }
2035 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2036 to be an explicit register variable, and was chosen for a reason. */
2042 /* If INSN contains volatile references (specifically volatile MEMs),
2043 we cannot combine across any other volatile references.
2044 Even if INSN doesn't contain volatile references, any intervening
2045 volatile insn might affect machine state. */
2048 ? volatile_refs_p
2055 /* If INSN contains an autoincrement or autodecrement, make sure that
2056 register is not used between there and I3, and not already used in
2057 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2058 Also insist that I3 not be a jump; if it were one
2059 and the incremented register were spilled, we would lose. */
2077 /* Don't combine an insn that follows a CC0-setting insn.
2078 An insn that uses CC0 must not be separated from the one that sets it.
2079 We do, however, allow I2 to follow a CC0-setting insn if that insn
2080 is passed as I1; in that case it will be deleted also.
2081 We also allow combining in this case if all the insns are adjacent
2082 because that would leave the two CC0 insns adjacent as well.
2083 It would be more logical to test whether CC0 occurs inside I1 or I2,
2084 but that would be much slower, and this ought to be equivalent. */
2087 {
2092 }
2094 /* If we get here, we have passed all the tests and the combination is
2095 to be allowed. */
2101 }
2102 \f
2103 /* LOC is the location within I3 that contains its pattern or the component
2104 of a PARALLEL of the pattern. We validate that it is valid for combining.
2106 One problem is if I3 modifies its output, as opposed to replacing it
2107 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2108 doing so would produce an insn that is not equivalent to the original insns.
2110 Consider:
2112 (set (reg:DI 101) (reg:DI 100))
2113 (set (subreg:SI (reg:DI 101) 0) <foo>)
2115 This is NOT equivalent to:
2117 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2118 (set (reg:DI 101) (reg:DI 100))])
2120 Not only does this modify 100 (in which case it might still be valid
2121 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2123 We can also run into a problem if I2 sets a register that I1
2124 uses and I1 gets directly substituted into I3 (not via I2). In that
2125 case, we would be getting the wrong value of I2DEST into I3, so we
2126 must reject the combination. This case occurs when I2 and I1 both
2127 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2128 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2129 of a SET must prevent combination from occurring. The same situation
2130 can occur for I0, in which case I0_NOT_IN_SRC is set.
2132 Before doing the above check, we first try to expand a field assignment
2133 into a set of logical operations.
2135 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2136 we place a register that is both set and used within I3. If more than one
2137 such register is detected, we fail.
2139 Return 1 if the combination is valid, zero otherwise. */
2141 static int
2144 {
2148 {
2153 rtx subdest;
2160 /* Check for the case where I3 modifies its output, as discussed
2161 above. We don't want to prevent pseudos from being combined
2162 into the address of a MEM, so only prevent the combination if
2163 i1 or i2 set the same MEM. */
2173 /* This is the same test done in can_combine_p except we can't test
2174 all_adjacent; we don't have to, since this instruction will stay
2175 in place, thus we are not considering increasing the lifetime of
2176 INNER_DEST.
2178 Also, if this insn sets a function argument, combining it with
2179 something that might need a spill could clobber a previous
2180 function argument; the all_adjacent test in can_combine_p also
2181 checks this; here, we do a more specific test for this case. */
2191 /* If DEST is used in I3, it is being killed in this insn, so
2192 record that for later. We have to consider paradoxical
2193 subregs here, since they kill the whole register, but we
2194 ignore partial subregs, STRICT_LOW_PART, etc.
2195 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2196 STACK_POINTER_REGNUM, since these are always considered to be
2197 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2207 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2213 {
2218 }
2219 }
2222 {
2229 }
2232 }
2233 \f
2234 /* Return 1 if X is an arithmetic expression that contains a multiplication
2235 and division. We don't count multiplications by powers of two here. */
2237 static int
2239 {
2241 {
2257 }
2258 }
2259 \f
2260 /* Determine whether INSN can be used in a combination. Return nonzero if
2261 not. This is used in try_combine to detect early some cases where we
2262 can't perform combinations. */
2264 static int
2266 {
2267 rtx set;
2270 /* If this isn't really an insn, we can't do anything.
2271 This can occur when flow deletes an insn that it has merged into an
2272 auto-increment address. */
2276 /* Never combine loads and stores involving hard regs that are likely
2277 to be spilled. The register allocator can usually handle such
2278 reg-reg moves by tying. If we allow the combiner to make
2279 substitutions of likely-spilled regs, reload might die.
2280 As an exception, we allow combinations involving fixed regs; these are
2281 not available to the register allocator so there's no risk involved. */
2302 }
2304 struct likely_spilled_retval_info
2305 {
2308 };
2310 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2311 hard registers that are known to be written to / clobbered in full. */
2312 static void
2314 {
2331 else
2334 }
2336 /* Return nonzero iff part of the return value is live during INSN, and
2337 it is likely spilled. This can happen when more than one insn is needed
2338 to copy the return value, e.g. when we consider to combine into the
2339 second copy insn for a complex value. */
2341 static int
2343 {
2345 rtx reg;
2348 /* We assume here that no machine mode needs more than
2349 32 hard registers when the value overlaps with a register
2350 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2365 /* Disregard parts of the return value that are set later. */
2374 /* Check if any of the (probably) live return value registers is
2375 likely spilled. */
2376 nregs --;
2377 do
2378 {
2384 }
2386 /* Adjust INSN after we made a change to its destination.
2388 Changing the destination can invalidate notes that say something about
2389 the results of the insn and a LOG_LINK pointing to the insn. */
2391 static void
2393 {
2394 /* For notes, be conservative and simply remove them. */
2397 /* The new insn will have a destination that was previously the destination
2398 of an insn just above it. Call distribute_links to make a LOG_LINK from
2399 the next use of that destination. */
2415 }
2417 /* Return TRUE if combine can reuse reg X in mode MODE.
2418 ADDED_SETS is nonzero if the original set is still required. */
2419 static bool
2421 {
2428 /* Allow hard registers if the new mode is legal, and occupies no more
2429 registers than the old mode. */
2434 /* Or a pseudo that is only used once. */
2437 && !added_sets
2439 }
2442 /* Check whether X, the destination of a set, refers to part of
2443 the register specified by REG. */
2445 static bool
2447 {
2448 /* Check that reg is an integer mode register. */
2459 }
2461 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2462 Note that the INSN should be deleted *after* removing dead edges, so
2463 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2464 but not for a (set (pc) (label_ref FOO)). */
2466 static void
2468 {
2476 {
2481 /* Remove barriers from the footer if there are any. */
2484 {
2487 else
2491 }
2494 }
2495 }
2497 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2498 by an arbitrary number of CLOBBERs. */
2499 static bool
2501 {
2519 }
2521 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2522 CLOBBERs), can be split into individual SETs in that order, without
2523 changing semantics. */
2524 static bool
2526 {
2534 {
2543 }
2546 }
2548 /* Try to combine the insns I0, I1 and I2 into I3.
2549 Here I0, I1 and I2 appear earlier than I3.
2550 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2551 I3.
2553 If we are combining more than two insns and the resulting insn is not
2554 recognized, try splitting it into two insns. If that happens, I2 and I3
2555 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2556 Otherwise, I0, I1 and I2 are pseudo-deleted.
2558 Return 0 if the combination does not work. Then nothing is changed.
2559 If we did the combination, return the insn at which combine should
2560 resume scanning.
2562 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2563 new direct jump instruction.
2565 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2566 been I3 passed to an earlier try_combine within the same basic
2567 block. */
2572 {
2573 /* New patterns for I3 and I2, respectively. */
2577 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2578 dead. */
2580 /* Total number of SETs to put into I3. */
2582 /* Nonzero if I2's or I1's body now appears in I3. */
2584 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2586 /* Contains I3 if the destination of I3 is used in its source, which means
2587 that the old life of I3 is being killed. If that usage is placed into
2588 I2 and not in I3, a REG_DEAD note must be made. */
2590 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2592 /* Copy of SET_SRC of I1 and I0, if needed. */
2594 /* Set if I2DEST was reused as a scratch register. */
2596 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2598 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2603 /* Notes that must be added to REG_NOTES in I3 and I2. */
2605 /* Notes that we substituted I3 into I2 instead of the normal case. */
2607 /* Notes that I1, I2 or I3 is a MULT operation. */
2614 rtx temp_expr;
2617 rtx new_other_notes;
2620 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2621 never be). */
2625 /* Only try four-insn combinations when there's high likelihood of
2626 success. Look for simple insns, such as loads of constants or
2627 binary operations involving a constant. */
2629 {
2639 {
2642 rtx src;
2647 {
2650 }
2652 ngood++;
2655 nshift++;
2656 }
2658 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2659 are likely manipulating its value. Ideally we'll be able to combine
2660 all four insns into a bitfield insertion of some kind.
2662 Note the source in I0 might be inside a sign/zero extension and the
2663 memory modes in I0 and I3 might be different. So extract the address
2664 from the destination of I3 and search for it in the source of I0.
2666 In the event that there's a match but the source/dest do not actually
2667 refer to the same memory, the worst that happens is we try some
2668 combinations that we wouldn't have otherwise. */
2670 /* Ensure the source of SET0 is a MEM, possibly buried inside
2671 an extension. */
2677 /* Ensure the destination of SET3 is a MEM. */
2679 /* Would it be better to extract the base address for the MEM
2680 in SET3 and look for that? I don't have cases where it matters
2681 but I could envision such cases. */
2687 }
2689 /* Exit early if one of the insns involved can't be used for
2690 combinations. */
2701 combine_attempts++;
2704 /* Reset the hard register usage information. */
2708 {
2715 else
2718 }
2720 /* If multiple insns feed into one of I2 or I3, they can be in any
2721 order. To simplify the code below, reorder them in sequence. */
2731 /* First check for one important special case that the code below will
2732 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2733 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2734 we may be able to replace that destination with the destination of I3.
2735 This occurs in the common code where we compute both a quotient and
2736 remainder into a structure, in which case we want to do the computation
2737 directly into the structure to avoid register-register copies.
2739 Note that this case handles both multiple sets in I2 and also cases
2740 where I2 has a number of CLOBBERs inside the PARALLEL.
2742 We make very conservative checks below and only try to handle the
2743 most common cases of this. For example, we only handle the case
2744 where I2 and I3 are adjacent to avoid making difficult register
2745 usage tests. */
2753 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2754 below would need to check what is inside (and reg_overlap_mentioned_p
2755 doesn't support those codes anyway). Don't allow those destinations;
2756 the resulting insn isn't likely to be recognized anyway. */
2762 {
2765 /* Make sure that the destination of I3,
2766 which we are going to substitute into one output of I2,
2767 is not used within another output of I2. We must avoid making this:
2768 (parallel [(set (mem (reg 69)) ...)
2769 (set (reg 69) ...)])
2770 which is not well-defined as to order of actions.
2771 (Besides, reload can't handle output reloads for this.)
2773 The problem can also happen if the dest of I3 is a memory ref,
2774 if another dest in I2 is an indirect memory ref. */
2782 /* Make sure this PARALLEL is not an asm. We do not allow combining
2783 that usually (see can_combine_p), so do not here either. */
2793 {
2794 combine_merges++;
2804 /* Replace the dest in I2 with our dest and make the resulting
2805 insn the new pattern for I3. Then skip to where we validate
2806 the pattern. Everything was set up above. */
2811 }
2812 }
2814 /* If I2 is setting a pseudo to a constant and I3 is setting some
2815 sub-part of it to another constant, merge them by making a new
2816 constant. */
2823 {
2829 {
2832 {
2838 }
2839 }
2840 else
2841 {
2846 }
2849 {
2850 /* If this is the low part, we're done. */
2852 ;
2853 /* Handle the case where inner is twice the size of outer. */
2857 /* Otherwise give up for now. */
2858 else
2860 }
2863 {
2867 wide_int o
2872 combine_merges++;
2879 /* Replace the source in I2 with the new constant and make the
2880 resulting insn the new pattern for I3. Then skip to where we
2881 validate the pattern. Everything was set up above. */
2887 /* The dest of I3 has been replaced with the dest of I2. */
2890 }
2891 }
2893 /* If we have no I1 and I2 looks like:
2894 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2895 (set Y OP)])
2896 make up a dummy I1 that is
2897 (set Y OP)
2898 and change I2 to be
2899 (set (reg:CC X) (compare:CC Y (const_int 0)))
2901 (We can ignore any trailing CLOBBERs.)
2903 This undoes a previous combination and allows us to match a branch-and-
2904 decrement insn. */
2916 {
2917 /* We make I1 with the same INSN_UID as I2. This gives it
2918 the same DF_INSN_LUID for value tracking. Our fake I1 will
2919 never appear in the insn stream so giving it the same INSN_UID
2920 as I2 will not cause a problem. */
2933 }
2935 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2936 make those two SETs separate I1 and I2 insns, and make an I0 that is
2937 the original I1. */
2943 {
2944 /* If there is no I1, there is no I0 either. */
2947 /* We make I1 with the same INSN_UID as I2. This gives it
2948 the same DF_INSN_LUID for value tracking. Our fake I1 will
2949 never appear in the insn stream so giving it the same INSN_UID
2950 as I2 will not cause a problem. */
2958 }
2960 /* Verify that I2 and I1 are valid for combining. */
2966 {
2969 }
2971 /* Record whether I2DEST is used in I2SRC and similarly for the other
2972 cases. Knowing this will help in register status updating below. */
2983 /* For the earlier insns, determine which of the subsequent ones they
2984 feed. */
2991 /* Ensure that I3's pattern can be the destination of combines. */
2997 {
3000 }
3002 /* See if any of the insns is a MULT operation. Unless one is, we will
3003 reject a combination that is, since it must be slower. Be conservative
3004 here. */
3012 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3013 We used to do this EXCEPT in one case: I3 has a post-inc in an
3014 output operand. However, that exception can give rise to insns like
3015 mov r3,(r3)+
3016 which is a famous insn on the PDP-11 where the value of r3 used as the
3017 source was model-dependent. Avoid this sort of thing. */
3019 #if 0
3025 /* It's not the exception. */
3026 #endif
3028 {
3029 rtx link;
3035 {
3038 }
3039 }
3041 /* See if the SETs in I1 or I2 need to be kept around in the merged
3042 instruction: whenever the value set there is still needed past I3.
3043 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3045 For the SET in I1, we have two cases: if I1 and I2 independently feed
3046 into I3, the set in I1 needs to be kept around unless I1DEST dies
3047 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3048 in I1 needs to be kept around unless I1DEST dies or is set in either
3049 I2 or I3. The same considerations apply to I0. */
3056 else
3064 else
3067 /* We are about to copy insns for the case where they need to be kept
3068 around. Check that they can be copied in the merged instruction. */
3074 {
3077 }
3079 /* If the set in I2 needs to be kept around, we must make a copy of
3080 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3081 PATTERN (I2), we are only substituting for the original I1DEST, not into
3082 an already-substituted copy. This also prevents making self-referential
3083 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3084 I2DEST. */
3087 {
3090 else
3092 }
3095 {
3098 else
3100 }
3103 {
3106 else
3108 }
3110 combine_merges++;
3112 /* Substitute in the latest insn for the regs set by the earlier ones. */
3118 /* Many machines that don't use CC0 have insns that can both perform an
3119 arithmetic operation and set the condition code. These operations will
3120 be represented as a PARALLEL with the first element of the vector
3121 being a COMPARE of an arithmetic operation with the constant zero.
3122 The second element of the vector will set some pseudo to the result
3123 of the same arithmetic operation. If we simplify the COMPARE, we won't
3124 match such a pattern and so will generate an extra insn. Here we test
3125 for this case, where both the comparison and the operation result are
3126 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3127 I2SRC. Later we will make the PARALLEL that contains I2. */
3133 {
3134 rtx newpat_dest;
3148 {
3153 }
3155 /* Do the rest only if op1 is const0_rtx, which may be the
3156 result of simplification. */
3158 {
3159 /* If a single use of the CC is found, prepare to modify it
3160 when SELECT_CC_MODE returns a new CC-class mode, or when
3161 the above simplify_compare_const() returned a new comparison
3162 operator. undobuf.other_insn is assigned the CC use insn
3163 when modifying it. */
3165 {
3166 #ifdef SELECT_CC_MODE
3167 machine_mode new_mode
3172 {
3177 else
3178 {
3181 }
3182 }
3183 #endif
3184 /* Cases for modifying the CC-using comparison. */
3186 /* ??? Do we need to verify the zero rtx? */
3188 {
3189 /* Replace cc_use_loc with entire new RTX. */
3194 }
3196 {
3197 /* Just replace the CC reg with a new mode. */
3200 }
3201 }
3203 /* Now we modify the current newpat:
3204 First, SET_DEST(newpat) is updated if the CC mode has been
3205 altered. For targets without SELECT_CC_MODE, this should be
3206 optimized away. */
3209 /* This is always done to propagate i2src into newpat. */
3212 /* Create new version of i2pat if needed; the below PARALLEL
3213 creation needs this to work correctly. */
3217 }
3218 }
3221 {
3222 /* It is possible that the source of I2 or I1 may be performing
3223 an unneeded operation, such as a ZERO_EXTEND of something
3224 that is known to have the high part zero. Handle that case
3225 by letting subst look at the inner insns.
3227 Another way to do this would be to have a function that tries
3228 to simplify a single insn instead of merging two or more
3229 insns. We don't do this because of the potential of infinite
3230 loops and because of the potential extra memory required.
3231 However, doing it the way we are is a bit of a kludge and
3232 doesn't catch all cases.
3234 But only do this if -fexpensive-optimizations since it slows
3235 things down and doesn't usually win.
3237 This is not done in the COMPARE case above because the
3238 unmodified I2PAT is used in the PARALLEL and so a pattern
3239 with a modified I2SRC would not match. */
3242 {
3243 /* Pass pc_rtx so no substitutions are done, just
3244 simplifications. */
3246 {
3249 }
3253 }
3258 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3259 copy of I2SRC each time we substitute it, in order to avoid creating
3260 self-referential RTL when we will be substituting I1SRC for I1DEST
3261 later. Likewise if I0 feeds into I2, either directly or indirectly
3262 through I1, and I0DEST is in I0SRC. */
3269 /* Record whether I2's body now appears within I3's body. */
3271 }
3273 /* If we already got a failure, don't try to do more. Otherwise, try to
3274 substitute I1 if we have it. */
3277 {
3278 /* Check that an autoincrement side-effect on I1 has not been lost.
3279 This happens if I1DEST is mentioned in I2 and dies there, and
3280 has disappeared from the new pattern. */
3282 && i1_feeds_i2_n
3285 /* Before we can do this substitution, we must redo the test done
3286 above (see detailed comments there) that ensures I1DEST isn't
3287 mentioned in any SETs in NEWPAT that are field assignments. */
3290 {
3293 }
3298 /* If the following substitution will modify I1SRC, make a copy of it
3299 for the case where it is substituted for I1DEST in I2PAT later. */
3303 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3304 copy of I1SRC each time we substitute it, in order to avoid creating
3305 self-referential RTL when we will be substituting I0SRC for I0DEST
3306 later. */
3311 /* Record whether I1's body now appears within I3's body. */
3313 }
3315 /* Likewise for I0 if we have it. */
3318 {
3325 {
3328 }
3330 /* If the following substitution will modify I0SRC, make a copy of it
3331 for the case where it is substituted for I0DEST in I1PAT later. */
3334 /* And a copy for I0DEST in I2PAT substitution. */
3343 }
3345 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3346 to count all the ways that I2SRC and I1SRC can be used. */
3357 /* Fail if we tried to make a new register. */
3359 /* Fail if we couldn't do something and have a CLOBBER. */
3361 /* Fail if this new pattern is a MULT and we didn't have one before
3362 at the outer level. */
3365 {
3368 }
3370 /* If the actions of the earlier insns must be kept
3371 in addition to substituting them into the latest one,
3372 we must make a new PARALLEL for the latest insn
3373 to hold additional the SETs. */
3376 {
3378 combine_extras++;
3381 {
3387 }
3388 else
3389 {
3394 }
3400 {
3406 }
3408 {
3417 }
3418 }
3420 validate_replacement:
3422 /* Note which hard regs this insn has as inputs. */
3425 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3426 consider splitting this pattern, we might need these clobbers. */
3429 {
3435 }
3437 /* We have recognized nothing yet. */
3440 /* See if this is a PARALLEL of two SETs where one SET's destination is
3441 a register that is unused and this isn't marked as an instruction that
3442 might trap in an EH region. In that case, we just need the other SET.
3443 We prefer this over the PARALLEL.
3445 This can occur when simplifying a divmod insn. We *must* test for this
3446 case here because the code below that splits two independent SETs doesn't
3447 handle this case correctly when it updates the register status.
3449 It's pointless doing this if we originally had two sets, one from
3450 i3, and one from i2. Combining then splitting the parallel results
3451 in the original i2 again plus an invalid insn (which we delete).
3452 The net effect is only to move instructions around, which makes
3453 debug info less accurate. */
3458 {
3469 {
3472 }
3481 {
3487 }
3491 }
3493 /* Is the result of combination a valid instruction? */
3497 /* If we were combining three insns and the result is a simple SET
3498 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3499 insns. There are two ways to do this. It can be split using a
3500 machine-specific method (like when you have an addition of a large
3501 constant) or by combine in the function find_split_point. */
3505 {
3509 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3510 use I2DEST as a scratch register will help. In the latter case,
3511 convert I2DEST to the mode of the source of NEWPAT if we can. */
3515 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3516 inputs of NEWPAT. */
3518 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3519 possible to try that as a scratch reg. This would require adding
3520 more code to make it work though. */
3523 {
3526 /* First try to split using the original register as a
3527 scratch register. */
3531 i2dest)));
3534 /* If that didn't work, try changing the mode of I2DEST if
3535 we can. */
3540 {
3542 rtx ni2dest;
3546 else
3547 {
3550 }
3552 parallel = (gen_rtx_PARALLEL
3556 ni2dest))));
3561 {
3569 }
3570 }
3573 }
3575 /* If recog_for_combine has discarded clobbers, try to use them
3576 again for the split. */
3578 {
3581 }
3584 {
3589 }
3593 {
3603 /* If I2 or I3 has multiple SETs, we won't know how to track
3604 register status, so don't use these insns. If I2's destination
3605 is used between I2 and I3, we also can't use these insns. */
3615 /* It is possible that both insns now set the destination of I3.
3616 If so, we must show an extra use of it. */
3619 {
3638 }
3639 }
3641 /* If we can split it and use I2DEST, go ahead and see if that
3642 helps things be recognized. Verify that none of the registers
3643 are set between I2 and I3. */
3647 /* We need I2DEST in the proper mode. If it is a hard register
3648 or the only use of a pseudo, we can change its mode.
3649 Make sure we don't change a hard register to have a mode that
3650 isn't valid for it, or change the number of registers. */
3657 /* We can't overwrite I2DEST if its value is still used by
3658 NEWPAT. */
3660 {
3669 /* *SPLIT may be part of I2SRC, so make sure we have the
3670 original expression around for later debug processing.
3671 We should not need I2SRC any more in other cases. */
3674 else
3677 /* Get NEWDEST as a register in the proper mode. We have already
3678 validated that we can do this. */
3680 {
3683 else
3684 {
3687 }
3688 }
3690 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3691 an ASHIFT. This can occur if it was inside a PLUS and hence
3692 appeared to be a memory address. This is a kludge. */
3697 {
3700 /* Update split_code because we may not have a multiply
3701 anymore. */
3703 }
3705 /* Similarly for (plus (mult FOO (const_int pow2))). */
3711 {
3715 /* Update split_code because we may not have a multiply
3716 anymore. */
3718 }
3720 #ifdef INSN_SCHEDULING
3721 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3722 be written as a ZERO_EXTEND. */
3724 {
3725 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3726 what it really is. */
3731 else
3734 }
3735 #endif
3737 /* Attempt to split binary operators using arithmetic identities. */
3741 {
3748 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3750 {
3755 }
3756 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3763 {
3769 /* Split both "((X op Y) op X) op Y" and
3770 "((X op Y) op Y) op X" as "T op T" where T is
3771 "X op Y". */
3774 {
3779 }
3780 /* Split "((X op X) op Y) op Y)" as "T op T" where
3781 T is "X op Y". */
3783 {
3789 }
3790 }
3791 }
3794 {
3797 }
3801 /* recog_for_combine might have added CLOBBERs to newi2pat.
3802 Make sure NEWPAT does not depend on the clobbered regs. */
3806 {
3809 {
3812 }
3813 }
3815 /* If the split point was a MULT and we didn't have one before,
3816 don't use one now. */
3819 }
3820 }
3822 /* Check for a case where we loaded from memory in a narrow mode and
3823 then sign extended it, but we need both registers. In that case,
3824 we have a PARALLEL with both loads from the same memory location.
3825 We can split this into a load from memory followed by a register-register
3826 copy. This saves at least one insn, more if register allocation can
3827 eliminate the copy.
3829 We cannot do this if the destination of the first assignment is a
3830 condition code register or cc0. We eliminate this case by making sure
3831 the SET_DEST and SET_SRC have the same mode.
3833 We cannot do this if the destination of the second assignment is
3834 a register that we have already assumed is zero-extended. Similarly
3835 for a SUBREG of such a register. */
3870 {
3871 rtx ni2dest;
3885 }
3887 /* Similarly, check for a case where we have a PARALLEL of two independent
3888 SETs but we started with three insns. In this case, we can do the sets
3889 as two separate insns. This case occurs when some SET allows two
3890 other insns to combine, but the destination of that SET is still live.
3892 Also do this if we started with two insns and (at least) one of the
3893 resulting sets is a noop; this noop will be deleted later. */
3912 {
3916 /* Normally, it doesn't matter which of the two is done first,
3917 but the one that references cc0 can't be the second, and
3918 one which uses any regs/memory set in between i2 and i3 can't
3919 be first. The PARALLEL might also have been pre-existing in i3,
3920 so we need to make sure that we won't wrongly hoist a SET to i2
3921 that would conflict with a death note present in there. */
3929 /* If I3 is a jump, ensure that set0 is a jump so that
3930 we do not create invalid RTL. */
3932 )
3933 {
3936 }
3944 /* If I3 is a jump, ensure that set1 is a jump so that
3945 we do not create invalid RTL. */
3947 )
3948 {
3951 }
3952 else
3953 {
3956 }
3961 {
3962 /* recog_for_combine might have added CLOBBERs to newi2pat.
3963 Make sure NEWPAT does not depend on the clobbered regs. */
3965 {
3968 {
3971 {
3974 }
3975 }
3976 }
3979 }
3980 }
3982 /* If it still isn't recognized, fail and change things back the way they
3983 were. */
3985 /* Is the result a reasonable ASM_OPERANDS? */
3987 {
3990 }
3992 /* If we had to change another insn, make sure it is valid also. */
3994 {
4002 {
4005 }
4006 }
4008 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4009 they are adjacent to each other or not. */
4011 {
4015 {
4018 }
4019 }
4021 /* Only allow this combination if insn_rtx_costs reports that the
4022 replacement instructions are cheaper than the originals. */
4024 {
4027 }
4030 {
4035 {
4040 /* Temporarily revert mode back. */
4044 {
4045 /* If we used i2dest as a scratch register with a
4046 different mode, substitute it for the original
4047 i2src while its original mode is temporarily
4048 restored, and then clear i2scratch so that we don't
4049 do it again later. */
4051 this_basic_block);
4053 /* Put back the new mode. */
4055 }
4056 else
4057 {
4062 {
4065 }
4066 else
4067 {
4074 }
4076 /* We're dealing with a reg that changed mode but not
4077 meaning, so we want to turn it into a subreg for
4078 the new mode. However, because of REG sharing and
4079 because its mode had already changed, we have to do
4080 it in two steps. First, replace any debug uses of
4081 reg, with its original mode temporarily restored,
4082 with this copy we have created; then, replace the
4083 copy with the SUBREG of the original shared reg,
4084 once again changed to the new mode. */
4086 this_basic_block);
4090 this_basic_block);
4091 }
4092 }
4093 }
4095 /* If we will be able to accept this, we have made a
4096 change to the destination of I3. This requires us to
4097 do a few adjustments. */
4100 {
4103 }
4105 /* We now know that we can do this combination. Merge the insns and
4106 update the status of registers and LOG_LINKS. */
4109 {
4114 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4115 ensure that they are still valid. Then add any non-duplicate
4116 notes added by recog_for_combine. */
4118 {
4128 }
4132 NULL_RTX);
4133 }
4136 {
4139 rtx ni2dest;
4141 /* I3 now uses what used to be its destination and which is now
4142 I2's destination. This requires us to do a few adjustments. */
4146 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4147 so we still will.
4149 However, some later insn might be using I2's dest and have
4150 a LOG_LINK pointing at I3. We must remove this link.
4151 The simplest way to remove the link is to point it at I1,
4152 which we know will be a NOTE. */
4154 /* newi2pat is usually a SET here; however, recog_for_combine might
4155 have added some clobbers. */
4158 else
4165 {
4167 {
4173 }
4174 }
4175 }
4177 {
4182 /* Compute which registers we expect to eliminate. newi2pat may be setting
4183 either i3dest or i2dest, so we must check it. */
4186 || !i2dest_killed
4188 /* For i1, we need to compute both local elimination and global
4189 elimination information with respect to newi2pat because i1dest
4190 may be the same as i3dest, in which case newi2pat may be setting
4191 i1dest. Global information is used when distributing REG_DEAD
4192 note for i2 and i3, in which case it does matter if newi2pat sets
4193 i1dest or not.
4195 Local information is used when distributing REG_DEAD note for i1,
4196 in which case it doesn't matter if newi2pat sets i1dest or not.
4197 See PR62151, if we have four insns combination:
4198 i0: r0 <- i0src
4199 i1: r1 <- i1src (using r0)
4200 REG_DEAD (r0)
4201 i2: r0 <- i2src (using r1)
4202 i3: r3 <- i3src (using r0)
4203 ix: using r0
4204 From i1's point of view, r0 is eliminated, no matter if it is set
4205 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4206 should be discarded.
4208 Note local information only affects cases in forms like "I1->I2->I3",
4209 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4210 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4211 i0dest anyway. */
4213 || !i1dest_killed
4218 /* Same case as i1. */
4225 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4226 clear them. */
4234 /* Ensure that we do not have something that should not be shared but
4235 occurs multiple times in the new insns. Check this by first
4236 resetting all the `used' flags and then copying anything is shared. */
4260 {
4267 {
4268 /* I2SRC must still be meaningful at this point. Some splitting
4269 operations can invalidate I2SRC, but those operations do not
4270 apply to calls. */
4273 }
4281 }
4286 /* We had one special case above where I2 had more than one set and
4287 we replaced a destination of one of those sets with the destination
4288 of I3. In that case, we have to update LOG_LINKS of insns later
4289 in this basic block. Note that this (expensive) case is rare.
4291 Also, in this case, we must pretend that all REG_NOTEs for I2
4292 actually came from I3, so that REG_UNUSED notes from I2 will be
4293 properly handled. */
4296 {
4305 temp_insn
4315 {
4320 }
4321 else
4324 }
4332 {
4335 this_basic_block);
4338 }
4339 else
4340 {
4343 this_basic_block);
4345 }
4348 {
4353 this_basic_block);
4355 }
4358 {
4363 this_basic_block);
4365 }
4367 /* Get death notes for everything that is now used in either I3 or
4368 I2 and used to die in a previous insn. If we built two new
4369 patterns, move from I1 to I2 then I2 to I3 so that we get the
4370 proper movement on registers that I2 modifies. */
4376 else
4382 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4399 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4400 know these are REG_UNUSED and want them to go to the desired insn,
4401 so we always pass it as i3. */
4405 NULL_RTX);
4409 NULL_RTX);
4411 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4412 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4413 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4414 in that case, it might delete I2. Similarly for I2 and I1.
4415 Show an additional death due to the REG_DEAD note we make here. If
4416 we discard it in distribute_notes, we will decrement it again. */
4419 {
4424 else
4427 }
4430 {
4435 else
4438 }
4441 {
4446 else
4449 }
4452 {
4457 else
4460 }
4468 {
4473 /* The insn that used to set this register doesn't exist, and
4474 this life of the register may not exist either. See if one of
4475 I3's links points to an insn that sets I2DEST. If it does,
4476 that is now the last known value for I2DEST. If we don't update
4477 this and I2 set the register to a value that depended on its old
4478 contents, we will get confused. If this insn is used, thing
4479 will be set correctly in combine_instructions. */
4487 /* If the reg formerly set in I2 died only once and that was in I3,
4488 zero its use count so it won't make `reload' do any work. */
4491 && ! i2dest_in_i2src
4494 }
4497 {
4510 && ! i1dest_in_i1src
4513 }
4516 {
4529 && ! i0dest_in_i0src
4532 }
4534 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4535 been made to this insn. The order is important, because newi2pat
4536 can affect nonzero_bits of newpat. */
4540 }
4543 {
4545 {
4548 }
4550 }
4553 {
4555 {
4558 }
4560 }
4563 {
4565 {
4568 }
4570 }
4573 {
4575 {
4578 }
4580 }
4583 {
4585 {
4588 }
4590 }
4592 /* Set new_direct_jump_p if a new return or simple jump instruction
4593 has been created. Adjust the CFG accordingly. */
4595 {
4599 }
4604 {
4607 }
4609 /* A noop might also need cleaning up of CFG, if it comes from the
4610 simplification of a jump. */
4615 {
4618 }
4625 {
4628 }
4630 combine_successes++;
4637 else
4639 }
4640 \f
4641 /* Get a marker for undoing to the current state. */
4645 {
4647 }
4649 /* Undo the modifications up to the marker. */
4651 static void
4653 {
4657 {
4662 {
4677 }
4681 }
4684 }
4686 /* Undo all the modifications recorded in undobuf. */
4688 static void
4690 {
4692 }
4694 /* We've committed to accepting the changes we made. Move all
4695 of the undos to the free list. */
4697 static void
4699 {
4703 {
4707 }
4709 }
4710 \f
4711 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4712 where we have an arithmetic expression and return that point. LOC will
4713 be inside INSN.
4715 try_combine will call this function to see if an insn can be split into
4716 two insns. */
4720 {
4729 /* First special-case some codes. */
4731 {
4733 #ifdef INSN_SCHEDULING
4734 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4735 point. */
4738 #endif
4742 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4743 using LO_SUM and HIGH. */
4746 {
4754 }
4756 /* If we have a PLUS whose second operand is a constant and the
4757 address is not valid, perhaps will can split it up using
4758 the machine-specific way to split large constants. We use
4759 the first pseudo-reg (one of the virtual regs) as a placeholder;
4760 it will not remain in the result. */
4765 {
4768 subst_insn);
4770 /* This should have produced two insns, each of which sets our
4771 placeholder. If the source of the second is a valid address,
4772 we can make put both sources together and make a split point
4773 in the middle. */
4786 && memory_address_addr_space_p
4789 {
4793 /* Replace the placeholder in SRC2 with SRC1. If we can
4794 find where in SRC2 it was placed, that can become our
4795 split point and we can replace this address with SRC2.
4796 Just try two obvious places. */
4807 {
4810 }
4811 }
4813 /* If that didn't work, perhaps the first operand is complex and
4814 needs to be computed separately, so make a split point there.
4815 This will occur on machines that just support REG + CONST
4816 and have a constant moved through some previous computation. */
4822 }
4824 /* If we have a PLUS whose first operand is complex, try computing it
4825 separately by making a split there. */
4836 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4837 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4838 we need to put the operand into a register. So split at that
4839 point. */
4849 /* See if we can split SET_SRC as it stands. */
4854 /* See if we can split SET_DEST as it stands. */
4859 /* See if this is a bitfield assignment with everything constant. If
4860 so, this is an IOR of an AND, so split it into that. */
4870 {
4876 unsigned HOST_WIDE_INT mask
4878 rtx or_mask;
4887 else
4888 {
4894 or_mask));
4895 }
4902 }
4904 /* Otherwise, see if this is an operation that we can split into two.
4905 If so, try to split that. */
4909 {
4911 /* If we are AND'ing with a large constant that is only a single
4912 bit and the result is only being used in a context where we
4913 need to know if it is zero or nonzero, replace it with a bit
4914 extraction. This will avoid the large constant, which might
4915 have taken more than one insn to make. If the constant were
4916 not a valid argument to the AND but took only one insn to make,
4917 this is no worse, but if it took more than one insn, it will
4918 be better. */
4928 {
4933 {
4936 }
4937 }
4941 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4942 is known to be on, this can be converted into a NEG of a shift. */
4948 {
4960 }
4966 /* We can't optimize if either mode is a partial integer
4967 mode as we don't know how many bits are significant
4968 in those modes. */
4982 {
4990 }
4995 }
4999 {
5002 /* For unsigned, we have a choice of a shift followed by an
5003 AND or two shifts. Use two shifts for field sizes where the
5004 constant might be too large. We assume here that we can
5005 always at least get 8-bit constants in an AND insn, which is
5006 true for every current RISC. */
5009 {
5010 unsigned HOST_WIDE_INT mask
5014 gen_rtx_LSHIFTRT
5022 }
5023 else
5024 {
5026 gen_rtx_fmt_ee
5037 }
5038 }
5040 /* See if this is a simple operation with a constant as the second
5041 operand. It might be that this constant is out of range and hence
5042 could be used as a split point. */
5050 /* Finally, see if this is a simple operation with its first operand
5051 not in a register. The operation might require this operand in a
5052 register, so return it as a split point. We can always do this
5053 because if the first operand were another operation, we would have
5054 already found it as a split point. */
5063 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5064 it is better to write this as (not (ior A B)) so we can split it.
5065 Similarly for IOR. */
5067 {
5075 }
5077 /* Many RISC machines have a large set of logical insns. If the
5078 second operand is a NOT, put it first so we will try to split the
5079 other operand first. */
5081 {
5085 }
5090 /* Canonicalization can produce (minus A (mult B C)), where C is a
5091 constant. It may be better to try splitting (plus (mult B -C) A)
5092 instead if this isn't a multiply by a power of two. */
5096 {
5104 mode)),
5107 }
5109 /* Split at a multiply-accumulate instruction. However if this is
5110 the SET_SRC, we likely do not have such an instruction and it's
5111 worthless to try this split. */
5120 }
5122 /* Otherwise, select our actions depending on our rtx class. */
5124 {
5130 /* ... fall through ... */
5138 /* ... fall through ... */
5140 /* Some machines have (and (shift ...) ...) insns. If X is not
5141 an AND, but XEXP (X, 0) is, use it as our split point. */
5151 /* Otherwise, we don't have a split point. */
5153 }
5154 }
5155 \f
5156 /* Throughout X, replace FROM with TO, and return the result.
5157 The result is TO if X is FROM;
5158 otherwise the result is X, but its contents may have been modified.
5159 If they were modified, a record was made in undobuf so that
5160 undo_all will (among other things) return X to its original state.
5162 If the number of changes necessary is too much to record to undo,
5163 the excess changes are not made, so the result is invalid.
5164 The changes already made can still be undone.
5165 undobuf.num_undo is incremented for such changes, so by testing that
5166 the caller can tell whether the result is valid.
5168 `n_occurrences' is incremented each time FROM is replaced.
5170 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5172 IN_COND is nonzero if we are at the top level of a condition.
5174 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5175 by copying if `n_occurrences' is nonzero. */
5177 static rtx
5179 {
5184 rtx new_rtx;
5186 /* Two expressions are equal if they are identical copies of a shared
5187 RTX or if they are both registers with the same register number
5188 and mode. */
5190 #define COMBINE_RTX_EQUAL_P(X,Y) \
5191 ((X) == (Y) \
5192 || (REG_P (X) && REG_P (Y) \
5193 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5195 /* Do not substitute into clobbers of regs -- this will never result in
5196 valid RTL. */
5201 {
5202 n_occurrences++;
5204 }
5206 /* If X and FROM are the same register but different modes, they
5207 will not have been seen as equal above. However, the log links code
5208 will make a LOG_LINKS entry for that case. If we do nothing, we
5209 will try to rerecognize our original insn and, when it succeeds,
5210 we will delete the feeding insn, which is incorrect.
5212 So force this insn not to match in this (rare) case. */
5217 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5218 of which may contain things that can be combined. */
5222 /* It is possible to have a subexpression appear twice in the insn.
5223 Suppose that FROM is a register that appears within TO.
5224 Then, after that subexpression has been scanned once by `subst',
5225 the second time it is scanned, TO may be found. If we were
5226 to scan TO here, we would find FROM within it and create a
5227 self-referent rtl structure which is completely wrong. */
5231 /* Parallel asm_operands need special attention because all of the
5232 inputs are shared across the arms. Furthermore, unsharing the
5233 rtl results in recognition failures. Failure to handle this case
5234 specially can result in circular rtl.
5236 Solve this by doing a normal pass across the first entry of the
5237 parallel, and only processing the SET_DESTs of the subsequent
5238 entries. Ug. */
5243 {
5246 /* If this substitution failed, this whole thing fails. */
5254 {
5260 {
5263 /* If this substitution failed, this whole thing fails. */
5269 }
5270 }
5271 }
5272 else
5273 {
5277 /* We don't need to process a SET_DEST that is a register, CC0,
5278 or PC, so set up to skip this common case. All other cases
5279 where we want to suppress replacing something inside a
5280 SET_SRC are handled via the IN_DEST operand. */
5287 /* Substituting into the operands of a widening MULT is not likely
5288 to create RTL matching a machine insn. */
5296 {
5299 else
5301 }
5303 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5304 constant. */
5309 {
5311 {
5314 {
5316 {
5319 n_occurrences++;
5320 }
5321 else
5322 {
5324 unique_copy);
5326 /* If this substitution failed, this whole thing
5327 fails. */
5331 }
5334 }
5335 }
5337 {
5338 /* If this is a register being set, ignore it. */
5345 ;
5348 {
5349 /* In general, don't install a subreg involving two
5350 modes not tieable. It can worsen register
5351 allocation, and can even make invalid reload
5352 insns, since the reg inside may need to be copied
5353 from in the outside mode, and that may be invalid
5354 if it is an fp reg copied in integer mode.
5356 We allow two exceptions to this: It is valid if
5357 it is inside another SUBREG and the mode of that
5358 SUBREG and the mode of the inside of TO is
5359 tieable and it is valid if X is a SET that copies
5360 FROM to CC0. */
5368 && (!HAVE_cc0
5383 n_occurrences++;
5384 }
5385 else
5386 /* If we are in a SET_DEST, suppress most cases unless we
5387 have gone inside a MEM, in which case we want to
5388 simplify the address. We assume here that things that
5389 are actually part of the destination have their inner
5390 parts in the first expression. This is true for SUBREG,
5391 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5392 things aside from REG and MEM that should appear in a
5393 SET_DEST. */
5395 (((in_dest
5401 unique_copy);
5403 /* If we found that we will have to reject this combination,
5404 indicate that by returning the CLOBBER ourselves, rather than
5405 an expression containing it. This will speed things up as
5406 well as prevent accidents where two CLOBBERs are considered
5407 to be equal, thus producing an incorrect simplification. */
5413 {
5421 }
5424 {
5428 }
5429 else
5431 }
5432 }
5433 }
5435 /* Check if we are loading something from the constant pool via float
5436 extension; in this case we would undo compress_float_constant
5437 optimization and degenerate constant load to an immediate value. */
5441 {
5445 }
5447 /* Try to simplify X. If the simplification changed the code, it is likely
5448 that further simplification will help, so loop, but limit the number
5449 of repetitions that will be performed. */
5452 {
5453 /* If X is sufficiently simple, don't bother trying to do anything
5454 with it. */
5463 /* We no longer know the original mode of operand 0 since we
5464 have changed the form of X) */
5466 }
5469 }
5470 \f
5471 /* Simplify X, a piece of RTL. We just operate on the expression at the
5472 outer level; call `subst' to simplify recursively. Return the new
5473 expression.
5475 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5476 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5477 of a condition. */
5479 static rtx
5482 {
5485 rtx temp;
5488 /* If this is a commutative operation, put a constant last and a complex
5489 expression first. We don't need to do this for comparisons here. */
5492 {
5496 }
5498 /* Try to fold this expression in case we have constants that weren't
5499 present before. */
5502 {
5510 {
5513 {
5517 }
5520 }
5533 }
5536 {
5541 }
5543 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5544 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5545 things. Check for cases where both arms are testing the same
5546 condition.
5548 Don't do anything if all operands are very simple. */
5561 {
5566 /* If everything is a comparison, what we have is highly unlikely
5567 to be simpler, so don't use it. */
5570 {
5577 /* Simplify the alternative arms; this may collapse the true and
5578 false arms to store-flag values. Be careful to use copy_rtx
5579 here since true_rtx or false_rtx might share RTL with x as a
5580 result of the if_then_else_cond call above. */
5584 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5585 is unlikely to be simpler. */
5588 {
5591 /* Restarting if we generate a store-flag expression will cause
5592 us to loop. Just drop through in this case. */
5594 /* If the result values are STORE_FLAG_VALUE and zero, we can
5595 just make the comparison operation. */
5606 /* Likewise, we can make the negate of a comparison operation
5607 if the result values are - STORE_FLAG_VALUE and zero. */
5615 mode);
5626 mode);
5627 else
5630 mode,
5631 VOIDmode,
5632 cond,
5633 cop1),
5638 }
5639 }
5640 }
5642 /* First see if we can apply the inverse distributive law. */
5645 {
5649 }
5651 /* If CODE is an associative operation not otherwise handled, see if we
5652 can associate some operands. This can win if they are constants or
5653 if they are logically related (i.e. (a & b) & a). */
5659 {
5661 {
5665 rtx inner;
5667 /* Make sure we pass the constant operand if any as the second
5668 one if this is a commutative operation. */
5676 /* For commutative operations, try the other pair if that one
5677 didn't simplify. */
5679 {
5684 }
5688 }
5689 }
5691 /* A little bit of algebraic simplification here. */
5693 {
5695 /* Ensure that our address has any ASHIFTs converted to MULT in case
5696 address-recognizing predicates are called later. */
5705 /* See if this can be moved to simplify_subreg. */
5708 /* Don't call gen_lowpart if the inner mode
5709 is VOIDmode and we cannot simplify it, as SUBREG without
5710 inner mode is invalid. */
5717 {
5718 rtx temp;
5724 /* If op is known to have all lower bits zero, the result is zero. */
5734 }
5736 /* Don't change the mode of the MEM if that would change the meaning
5737 of the address. */
5744 /* Note that we cannot do any narrowing for non-constants since
5745 we might have been counting on using the fact that some bits were
5746 zero. We now do this in the SET. */
5753 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5754 replaced by (lshiftrt X C). This will convert
5755 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5763 /* If X has only a single bit that might be nonzero, say, bit I, convert
5764 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5765 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5766 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5767 or a SUBREG of one since we'd be making the expression more
5768 complex if it was just a register. */
5774 {
5775 rtx temp1 = simplify_shift_const
5781 /* If all we did was surround TEMP with the two shifts, we
5782 haven't improved anything, so don't use it. Otherwise,
5783 we are better off with TEMP1. */
5788 }
5792 /* We can't handle truncation to a partial integer mode here
5793 because we don't know the real bitsize of the partial
5794 integer mode. */
5803 /* We can truncate a constant value and return it. */
5807 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5808 whose value is a comparison can be replaced with a subreg if
5809 STORE_FLAG_VALUE permits. */
5818 /* (const (const X)) can become (const X). Do it this way rather than
5819 returning the inner CONST since CONST can be shared with a
5820 REG_EQUAL note. */
5826 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5827 can add in an offset. find_split_point will split this address up
5828 again if it doesn't match. */
5835 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5836 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5837 bit-field and can be replaced by either a sign_extend or a
5838 sign_extract. The `and' may be a zero_extend and the two
5839 <c>, -<c> constants may be reversed. */
5854 return simplify_shift_const
5861 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5862 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5863 the bitsize of the mode - 1. This allows simplification of
5864 "a = (b & 8) == 0;" */
5876 /* If we are adding two things that have no bits in common, convert
5877 the addition into an IOR. This will often be further simplified,
5878 for example in cases like ((a & 1) + (a & 2)), which can
5879 become a & 3. */
5884 {
5885 /* Try to simplify the expression further. */
5889 /* If we could, great. If not, do not go ahead with the IOR
5890 replacement, since PLUS appears in many special purpose
5891 address arithmetic instructions. */
5899 }
5903 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5904 (and <foo> (const_int pow2-1)) */
5914 /* If we have (mult (plus A B) C), apply the distributive law and then
5915 the inverse distributive law to see if things simplify. This
5916 occurs mostly in addresses, often when unrolling loops. */
5919 {
5923 }
5925 /* Try simplify a*(b/c) as (a*b)/c. */
5928 {
5934 }
5938 /* If this is a divide by a power of two, treat it as a shift if
5939 its first operand is a shift. */
5957 /* If the first operand is a condition code, we can't do anything
5958 with it. */
5962 {
5970 /* Simplify our comparison, if possible. */
5973 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5974 if only the low-order bit is possibly nonzero in X (such as when
5975 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5976 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5977 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5978 (plus X 1).
5980 Remove any ZERO_EXTRACT we made when thinking this was a
5981 comparison. It may now be simpler to use, e.g., an AND. If a
5982 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5983 the call to make_compound_operation in the SET case.
5985 Don't apply these optimizations if the caller would
5986 prefer a comparison rather than a value.
5987 E.g., for the condition in an IF_THEN_ELSE most targets need
5988 an explicit comparison. */
5991 ;
6007 {
6011 mode);
6012 }
6019 {
6023 const1_rtx);
6024 }
6032 {
6035 }
6037 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6038 those above. */
6040 ;
6056 {
6060 mode);
6061 }
6069 {
6073 mode);
6074 }
6076 /* If X is 0/1, (eq X 0) is X-1. */
6082 {
6085 }
6087 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6088 one bit that might be nonzero, we can convert (ne x 0) to
6089 (ashift x c) where C puts the bit in the sign bit. Remove any
6090 AND with STORE_FLAG_VALUE when we are done, since we are only
6091 going to test the sign bit. */
6098 {
6104 else
6106 }
6108 /* If the code changed, return a whole new comparison.
6109 We also need to avoid using SUBST in cases where
6110 simplify_comparison has widened a comparison with a CONST_INT,
6111 since in that case the wider CONST_INT may fail the sanity
6112 checks in do_SUBST. */
6119 /* Otherwise, keep this operation, but maybe change its operands.
6120 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6123 }
6133 /* If we are processing SET_DEST, we are done. */
6151 /* If this is a shift by a constant amount, simplify it. */
6167 }
6170 }
6171 \f
6172 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6174 static rtx
6176 {
6183 rtx temp;
6186 rtx reversed;
6188 /* Simplify storing of the truth value. */
6193 /* Also when the truth value has to be reversed. */
6199 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6200 in it is being compared against certain values. Get the true and false
6201 comparisons and see if that says anything about the value of each arm. */
6207 {
6208 HOST_WIDE_INT nzb;
6214 /* If FALSE_CODE is EQ, swap the codes and arms. */
6217 {
6220 }
6222 /* If we are comparing against zero and the expression being tested has
6223 only a single bit that might be nonzero, that is its value when it is
6224 not equal to zero. Similarly if it is known to be -1 or 0. */
6228 {
6231 }
6235 {
6238 }
6240 /* Now simplify an arm if we know the value of the register in the
6241 branch and it is used in the arm. Be careful due to the potential
6242 of locally-shared RTL. */
6259 }
6261 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6262 reversed, do so to avoid needing two sets of patterns for
6263 subtract-and-branch insns. Similarly if we have a constant in the true
6264 arm, the false arm is the same as the first operand of the comparison, or
6265 the false arm is more complicated than the true arm. */
6278 {
6287 /* It is possible that the conditional has been simplified out. */
6290 }
6292 /* If the two arms are identical, we don't need the comparison. */
6297 /* Convert a == b ? b : a to "a". */
6309 /* Look for cases where we have (abs x) or (neg (abs X)). */
6312 && comparison_p
6319 {
6325 return
6328 mode);
6331 }
6333 /* Look for MIN or MAX. */
6336 && comparison_p
6341 {
6356 }
6358 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6359 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6360 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6361 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6362 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6363 neither 1 or -1, but it isn't worth checking for. */
6366 && comparison_p
6369 {
6385 /* If an identity-zero op is commutative, check whether there
6386 would be a match if we swapped the operands. */
6406 {
6410 }
6422 {
6426 }
6442 {
6446 }
6458 {
6462 }
6465 {
6471 const_true_rtx));
6479 }
6480 }
6482 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6483 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6484 negation of a single bit, we can convert this operation to a shift. We
6485 can actually do this more generally, but it doesn't seem worth it. */
6494 return
6498 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6508 }
6509 \f
6510 /* Simplify X, a SET expression. Return the new expression. */
6512 static rtx
6514 {
6517 machine_mode mode
6522 /* (set (pc) (return)) gets written as (return). */
6526 /* Now that we know for sure which bits of SRC we are using, see if we can
6527 simplify the expression for the object knowing that we only need the
6528 low-order bits. */
6531 {
6534 }
6536 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6537 the comparison result and try to simplify it unless we already have used
6538 undobuf.other_insn. */
6546 {
6555 {
6558 {
6561 }
6562 }
6563 else
6571 {
6575 }
6576 else
6577 {
6582 /* Attempt to simplify CC user. */
6584 {
6588 }
6590 /* Convert X into a no-op move. */
6594 }
6596 /* Simplify our comparison, if possible. */
6599 #ifdef SELECT_CC_MODE
6600 /* If this machine has CC modes other than CCmode, check to see if we
6601 need to use a different CC mode here. */
6610 else
6613 /* If the mode changed, we have to change SET_DEST, the mode in the
6614 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6615 a hard register, just build new versions with the proper mode. If it
6616 is a pseudo, we lose unless it is only time we set the pseudo, in
6617 which case we can safely change its mode. */
6619 {
6621 {
6623 rtx new_dest;
6627 else
6628 {
6631 }
6638 }
6639 }
6642 /* If the code changed, we have to build a new comparison in
6643 undobuf.other_insn. */
6645 {
6654 /* If the only change we made was to change an EQ into an NE or
6655 vice versa, OP0 has only one bit that might be nonzero, and OP1
6656 is zero, check if changing the user of the condition code will
6657 produce a valid insn. If it won't, we can keep the original code
6658 in that insn by surrounding our operation with an XOR. */
6665 {
6670 {
6677 }
6678 }
6679 }
6684 /* Don't generate a compare of a CC with 0, just use that CC. */
6686 {
6689 }
6690 /* Otherwise, if we didn't previously have the same COMPARE we
6691 want, create it from scratch. */
6694 {
6697 }
6698 }
6699 else
6700 {
6701 /* Get SET_SRC in a form where we have placed back any
6702 compound expressions. Then do the checks below. */
6705 }
6707 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6708 and X being a REG or (subreg (reg)), we may be able to convert this to
6709 (set (subreg:m2 x) (op)).
6711 We can always do this if M1 is narrower than M2 because that means that
6712 we only care about the low bits of the result.
6714 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6715 perform a narrower operation than requested since the high-order bits will
6716 be undefined. On machine where it is defined, this transformation is safe
6717 as long as M1 and M2 have the same number of words. */
6725 && (WORD_REGISTER_OPERATIONS
6728 #ifdef CANNOT_CHANGE_MODE_CLASS
6733 #endif
6737 {
6740 dest));
6744 }
6746 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6747 in SRC. */
6753 {
6757 /* Here we make sure that we don't have a sign bit on. */
6760 {
6763 }
6764 }
6766 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6767 would require a paradoxical subreg. Replace the subreg with a
6768 zero_extend to avoid the reload that would otherwise be required. */
6776 {
6782 }
6784 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6785 are comparing an item known to be 0 or -1 against 0, use a logical
6786 operation instead. Check for one of the arms being an IOR of the other
6787 arm with some value. We compute three terms to be IOR'ed together. In
6788 practice, at most two will be nonzero. Then we do the IOR's. */
6796 && (!HAVE_conditional_move
6802 {
6828 false_rtx);
6834 term3));
6837 }
6839 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6840 whole thing fail. */
6845 else
6846 /* Convert this into a field assignment operation, if possible. */
6848 }
6849 \f
6850 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6851 result. */
6853 static rtx
6855 {
6861 {
6863 /* We can call simplify_and_const_int only if we don't lose
6864 any (sign) bits when converting INTVAL (op1) to
6865 "unsigned HOST_WIDE_INT". */
6869 {
6876 }
6878 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6879 apply the distributive law and then the inverse distributive
6880 law to see if things simplify. */
6882 {
6886 }
6888 {
6892 }
6896 /* If we have (ior (and A B) C), apply the distributive law and then
6897 the inverse distributive law to see if things simplify. */
6900 {
6904 }
6907 {
6911 }
6916 }
6919 }
6920 \f
6921 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6922 operations" because they can be replaced with two more basic operations.
6923 ZERO_EXTEND is also considered "compound" because it can be replaced with
6924 an AND operation, which is simpler, though only one operation.
6926 The function expand_compound_operation is called with an rtx expression
6927 and will convert it to the appropriate shifts and AND operations,
6928 simplifying at each stage.
6930 The function make_compound_operation is called to convert an expression
6931 consisting of shifts and ANDs into the equivalent compound expression.
6932 It is the inverse of this function, loosely speaking. */
6934 static rtx
6936 {
6940 rtx tem;
6943 {
6947 /* We can't necessarily use a const_int for a multiword mode;
6948 it depends on implicitly extending the value.
6949 Since we don't know the right way to extend it,
6950 we can't tell whether the implicit way is right.
6952 Even for a mode that is no wider than a const_int,
6953 we can't win, because we need to sign extend one of its bits through
6954 the rest of it, and we don't know which bit. */
6958 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6959 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6960 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6961 reloaded. If not for that, MEM's would very rarely be safe.
6963 Reject MODEs bigger than a word, because we might not be able
6964 to reference a two-register group starting with an arbitrary register
6965 (and currently gen_lowpart might crash for a SUBREG). */
6970 /* Reject MODEs that aren't scalar integers because turning vector
6971 or complex modes into shifts causes problems. */
6977 /* If the inner object has VOIDmode (the only way this can happen
6978 is if it is an ASM_OPERANDS), we can't do anything since we don't
6979 know how much masking to do. */
6988 /* ... fall through ... */
6991 /* If the operand is a CLOBBER, just return it. */
7000 /* Reject MODEs that aren't scalar integers because turning vector
7001 or complex modes into shifts causes problems. */
7009 /* This should stay within the object being extracted, fail otherwise. */
7020 }
7021 /* Convert sign extension to zero extension, if we know that the high
7022 bit is not set, as this is easier to optimize. It will be converted
7023 back to cheaper alternative in make_extraction. */
7031 {
7036 /* Make sure this is a profitable operation. */
7043 else
7045 }
7047 /* We can optimize some special cases of ZERO_EXTEND. */
7049 {
7050 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7051 know that the last value didn't have any inappropriate bits
7052 set. */
7060 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7069 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7070 is a comparison and STORE_FLAG_VALUE permits. This is like
7071 the first case, but it works even when GET_MODE (x) is larger
7072 than HOST_WIDE_INT. */
7081 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7091 }
7093 /* If we reach here, we want to return a pair of shifts. The inner
7094 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7095 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7096 logical depending on the value of UNSIGNEDP.
7098 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7099 converted into an AND of a shift.
7101 We must check for the case where the left shift would have a negative
7102 count. This can happen in a case like (x >> 31) & 255 on machines
7103 that can't shift by a constant. On those machines, we would first
7104 combine the shift with the AND to produce a variable-position
7105 extraction. Then the constant of 31 would be substituted in
7106 to produce such a position. */
7110 {
7119 }
7126 else
7127 /* Any other cases we can't handle. */
7130 /* If we couldn't do this for some reason, return the original
7131 expression. */
7136 }
7137 \f
7138 /* X is a SET which contains an assignment of one object into
7139 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7140 or certain SUBREGS). If possible, convert it into a series of
7141 logical operations.
7143 We half-heartedly support variable positions, but do not at all
7144 support variable lengths. */
7146 static const_rtx
7148 {
7149 rtx inner;
7153 machine_mode compute_mode;
7155 /* Loop until we find something we can't simplify. */
7157 {
7160 {
7164 }
7167 {
7172 /* A constant position should stay within the width of INNER. */
7178 {
7186 /* If position is ADJUST - X, new position is X. */
7188 else
7189 {
7194 pos);
7195 }
7196 }
7197 }
7199 /* A SUBREG between two modes that occupy the same numbers of words
7200 can be done by moving the SUBREG to the source. */
7202 /* We need SUBREGs to compute nonzero_bits properly. */
7203 && nonzero_sign_valid
7208 {
7210 gen_lowpart
7214 }
7215 else
7223 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7225 {
7226 machine_mode imode;
7228 /* Don't do anything for vector or complex integral types. */
7232 /* Try to find an integral mode to pun with. */
7239 }
7241 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7245 /* Now compute the equivalent expression. Make a copy of INNER
7246 for the SET_DEST in case it is a MEM into which we will substitute;
7247 we don't want shared RTL in that case. */
7249 compute_mode);
7253 compute_mode,
7255 compute_mode),
7256 inner);
7261 mask),
7262 pos);
7267 }
7270 }
7271 \f
7272 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7273 it is an RTX that represents the (variable) starting position; otherwise,
7274 POS is the (constant) starting bit position. Both are counted from the LSB.
7276 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7278 IN_DEST is nonzero if this is a reference in the destination of a SET.
7279 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7280 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7281 be used.
7283 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7284 ZERO_EXTRACT should be built even for bits starting at bit 0.
7286 MODE is the desired mode of the result (if IN_DEST == 0).
7288 The result is an RTX for the extraction or NULL_RTX if the target
7289 can't handle it. */
7291 static rtx
7295 {
7296 /* This mode describes the size of the storage area
7297 to fetch the overall value from. Within that, we
7298 ignore the POS lowest bits, etc. */
7300 machine_mode inner_mode;
7301 machine_mode wanted_inner_mode;
7308 HOST_WIDE_INT orig_pos;
7314 {
7315 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7316 consider just the QI as the memory to extract from.
7317 The subreg adds or removes high bits; its mode is
7318 irrelevant to the meaning of this extraction,
7319 since POS and LEN count from the lsb. */
7323 }
7328 {
7329 /* We're extracting the least significant bits of an rtx
7330 (ashift X (const_int C)), where LEN > C. Extract the
7331 least significant (LEN - C) bits of X, giving an rtx
7332 whose mode is MODE, then shift it left C times. */
7338 }
7344 /* See if this can be done without an extraction. We never can if the
7345 width of the field is not the same as that of some integer mode. For
7346 registers, we can only avoid the extraction if the position is at the
7347 low-order bit and this is either not in the destination or we have the
7348 appropriate STRICT_LOW_PART operation available.
7350 For MEM, we can avoid an extract if the field starts on an appropriate
7351 boundary and we can change the mode of the memory reference. */
7360 && (! in_dest
7364 && (pos
7367 /* We can't do this if we are widening INNER_MODE (it
7368 may not be aligned, for one thing). */
7374 {
7375 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7376 field. If the original and current mode are the same, we need not
7377 adjust the offset. Otherwise, we do if bytes big endian.
7379 If INNER is not a MEM, get a piece consisting of just the field
7380 of interest (in this case POS % BITS_PER_WORD must be 0). */
7383 {
7384 HOST_WIDE_INT offset;
7386 /* POS counts from lsb, but make OFFSET count in memory order. */
7389 else
7393 }
7395 {
7397 {
7398 /* We can't call gen_lowpart in a DEST since we
7399 always want a SUBREG (see below) and it would sometimes
7400 return a new hard register. */
7402 {
7417 /* Avoid creating invalid subregs, for example when
7418 simplifying (x>>32)&255. */
7423 }
7424 else
7426 }
7427 else
7429 }
7430 else
7432 len >= HOST_BITS_PER_WIDE_INT
7437 /* If this extraction is going into the destination of a SET,
7438 make a STRICT_LOW_PART unless we made a MEM. */
7453 /* If we know that no extraneous bits are set, and that the high
7454 bit is not set, convert the extraction to the cheaper of
7455 sign and zero extension, that are equivalent in these cases. */
7461 {
7465 /* Prefer ZERO_EXTENSION, since it gives more information to
7466 backends. */
7471 }
7473 /* Otherwise, sign- or zero-extend unless we already are in the
7474 proper mode. */
7478 }
7480 /* Unless this is a COMPARE or we have a funny memory reference,
7481 don't do anything with zero-extending field extracts starting at
7482 the low-order bit since they are simple AND operations. */
7487 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7488 if the position is not a constant and the length is not 1. In all
7489 other cases, we would only be going outside our object in cases when
7490 an original shift would have been undefined. */
7499 /* If INNER is not from memory, we want it to have the mode of a register
7500 extraction pattern's structure operand, or word_mode if there is no
7501 such pattern. The same applies to extraction_mode and pos_mode
7502 and their respective operands.
7504 For memory, assume that the desired extraction_mode and pos_mode
7505 are the same as for a register operation, since at present we don't
7506 have named patterns for aligned memory structures. */
7510 {
7514 }
7516 /* Never narrow an object, since that might not be safe. */
7524 else
7525 {
7526 /* Be careful not to go beyond the extracted object and maintain the
7527 natural alignment of the memory. */
7531 {
7534 }
7535 }
7540 {
7541 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7542 BITS_BIG_ENDIAN style. If position is constant, compute new
7543 position. Otherwise, build subtraction.
7544 Note that POS is relative to the mode of the original argument.
7545 If it's a MEM we need to recompute POS relative to that.
7546 However, if we're extracting from (or inserting into) a register,
7547 we want to recompute POS relative to wanted_inner_mode. */
7554 else
7555 pos_rtx
7558 pos_rtx);
7559 /* POS may be less than 0 now, but we check for that below.
7560 Note that it can only be less than 0 if !MEM_P (inner). */
7561 }
7563 /* If INNER has a wider mode, and this is a constant extraction, try to
7564 make it smaller and adjust the byte to point to the byte containing
7565 the value. */
7568 && ! pos_rtx
7573 {
7576 /* The computations below will be correct if the machine is big
7577 endian in both bits and bytes or little endian in bits and bytes.
7578 If it is mixed, we must adjust. */
7580 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7581 adjust OFFSET to compensate. */
7586 /* We can now move to the desired byte. */
7597 }
7599 /* If INNER is not memory, get it into the proper mode. If we are changing
7600 its mode, POS must be a constant and smaller than the size of the new
7601 mode. */
7603 {
7604 /* On the LHS, don't create paradoxical subregs implicitely truncating
7605 the register unless TRULY_NOOP_TRUNCATION. */
7608 wanted_inner_mode))
7620 pos_rtx
7626 }
7628 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7629 have to zero extend. Otherwise, we can just use a SUBREG. */
7632 {
7636 /* If we know that no extraneous bits are set, and that the high
7637 bit is not set, convert extraction to cheaper one - either
7638 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7639 cases. */
7647 {
7651 /* Prefer ZERO_EXTENSION, since it gives more information to
7652 backends. */
7656 }
7658 }
7660 /* Make POS_RTX unless we already have it and it is correct. If we don't
7661 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7662 be a CONST_INT. */
7669 /* Make the required operation. See if we can use existing rtx. */
7676 }
7677 \f
7678 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7679 with any other operations in X. Return X without that shift if so. */
7681 static rtx
7683 {
7686 rtx tem;
7689 {
7691 /* This is the shift itself. If it is wide enough, we will return
7692 either the value being shifted if the shift count is equal to
7693 COUNT or a shift for the difference. */
7707 /* If we can safely shift this constant and we find the inner shift,
7708 make a new operation. */
7713 {
7717 }
7722 }
7725 }
7726 \f
7727 /* Look at the expression rooted at X. Look for expressions
7728 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7729 Form these expressions.
7731 Return the new rtx, usually just X.
7733 Also, for machines like the VAX that don't have logical shift insns,
7734 try to convert logical to arithmetic shift operations in cases where
7735 they are equivalent. This undoes the canonicalizations to logical
7736 shifts done elsewhere.
7738 We try, as much as possible, to re-use rtl expressions to save memory.
7740 IN_CODE says what kind of expression we are processing. Normally, it is
7741 SET. In a memory address it is MEM. When processing the arguments of
7742 a comparison or a COMPARE against zero, it is COMPARE. */
7744 rtx
7746 {
7754 rtx tem;
7757 /* Select the code to be used in recursive calls. Once we are inside an
7758 address, we stay there. If we have a comparison, set to COMPARE,
7759 but once inside, go back to our default of SET. */
7766 /* Process depending on the code of this operation. If NEW is set
7767 nonzero, it will be returned. */
7770 {
7772 /* Convert shifts by constants into multiplications if inside
7773 an address. */
7778 {
7784 {
7787 }
7790 }
7800 {
7804 }
7807 {
7811 mode));
7813 }
7814 else
7815 {
7819 }
7830 {
7834 }
7837 {
7841 mode));
7843 }
7844 else
7845 {
7849 }
7853 /* If the second operand is not a constant, we can't do anything
7854 with it. */
7858 /* If the constant is a power of two minus one and the first operand
7859 is a logical right shift, make an extraction. */
7862 {
7866 }
7868 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7873 {
7875 next_code);
7880 /* If that didn't give anything, see if the AND simplifies on
7881 its own. */
7883 {
7887 }
7888 }
7889 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7895 {
7896 /* Apply the distributive law, and then try to make extractions. */
7903 }
7905 /* If we are have (and (rotate X C) M) and C is larger than the number
7906 of bits in M, this is an extraction. */
7912 {
7918 }
7920 /* On machines without logical shifts, if the operand of the AND is
7921 a logical shift and our mask turns off all the propagated sign
7922 bits, we can replace the logical shift with an arithmetic shift. */
7930 {
7937 make_compound_operation
7940 }
7942 /* If the constant is one less than a power of two, this might be
7943 representable by an extraction even if no shift is present.
7944 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7945 we are in a COMPARE. */
7949 next_code),
7952 /* If we are in a comparison and this is an AND with a power of two,
7953 convert this into the appropriate bit extract. */
7958 next_code),
7964 /* If the sign bit is known to be zero, replace this with an
7965 arithmetic shift. */
7970 {
7973 next_code),
7976 }
7978 /* ... fall through ... */
7984 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7985 this is a SIGN_EXTRACT. */
7992 {
7999 }
8001 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8002 If so, try to merge the shifts into a SIGN_EXTEND. We could
8003 also do this for some cases of SIGN_EXTRACT, but it doesn't
8004 seem worth the effort; the case checked for occurs on Alpha. */
8020 /* Call ourselves recursively on the inner expression. If we are
8021 narrowing the object and it has a different RTL code from
8022 what it originally did, do this SUBREG as a force_to_mode. */
8023 {
8027 /* If in_code is COMPARE, it isn't always safe to pass it through
8028 to the recursive make_compound_operation call. */
8032 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8033 is (const_int 0), rather than
8034 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8044 simplified
8052 {
8053 rtx newer
8056 /* If we have something other than a SUBREG, we might have
8057 done an expansion, so rerun ourselves. */
8061 /* force_to_mode can expand compounds. If it just re-expanded the
8062 compound, use gen_lowpart to convert to the desired mode. */
8064 /* Likewise if it re-expanded the compound only partially.
8065 This happens for SUBREG of ZERO_EXTRACT if they extract
8066 the same number of bits. */
8075 }
8079 }
8084 }
8087 {
8090 }
8092 /* Now recursively process each operand of this operation. We need to
8093 handle ZERO_EXTEND specially so that we don't lose track of the
8094 inner mode. */
8096 {
8104 }
8109 {
8112 }
8115 {
8118 }
8120 maybe_swap:
8121 /* If this is a commutative operation, the changes to the operands
8122 may have made it noncanonical. */
8125 {
8129 }
8132 }
8133 \f
8134 /* Given M see if it is a value that would select a field of bits
8135 within an item, but not the entire word. Return -1 if not.
8136 Otherwise, return the starting position of the field, where 0 is the
8137 low-order bit.
8139 *PLEN is set to the length of the field. */
8141 static int
8143 {
8144 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8149 /* Now shift off the low-order zero bits and see if we have a
8150 power of two minus 1. */
8158 }
8159 \f
8160 /* If X refers to a register that equals REG in value, replace these
8161 references with REG. */
8162 static rtx
8164 {
8172 {
8208 {
8212 else
8214 }
8216 /* fall through */
8223 {
8226 {
8228 {
8231 }
8233 }
8234 }
8236 {
8239 {
8242 {
8244 {
8247 }
8249 }
8250 }
8251 }
8254 }
8257 }
8259 /* Return X converted to MODE. If the value is already truncated to
8260 MODE we can just return a subreg even though in the general case we
8261 would need an explicit truncation. */
8263 static rtx
8265 {
8270 {
8271 /* Bit-cast X into an integer mode. */
8276 }
8279 }
8281 /* See if X can be simplified knowing that we will only refer to it in
8282 MODE and will only refer to those bits that are nonzero in MASK.
8283 If other bits are being computed or if masking operations are done
8284 that select a superset of the bits in MASK, they can sometimes be
8285 ignored.
8287 Return a possibly simplified expression, but always convert X to
8288 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8290 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8291 are all off in X. This is used when X will be complemented, by either
8292 NOT, NEG, or XOR. */
8294 static rtx
8297 {
8300 machine_mode op_mode;
8304 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8305 code below will do the wrong thing since the mode of such an
8306 expression is VOIDmode.
8308 Also do nothing if X is a CLOBBER; this can happen if X was
8309 the return value from a call to gen_lowpart. */
8313 /* We want to perform the operation in its present mode unless we know
8314 that the operation is valid in MODE, in which case we do the operation
8315 in MODE. */
8320 /* It is not valid to do a right-shift in a narrower mode
8321 than the one it came in with. */
8326 /* Truncate MASK to fit OP_MODE. */
8330 /* When we have an arithmetic operation, or a shift whose count we
8331 do not know, we need to assume that all bits up to the highest-order
8332 bit in MASK will be needed. This is how we form such a mask. */
8335 else
8339 /* Determine what bits of X are guaranteed to be (non)zero. */
8342 /* If none of the bits in X are needed, return a zero. */
8346 /* If X is a CONST_INT, return a new one. Do this here since the
8347 test below will fail. */
8349 {
8352 else
8353 {
8356 }
8357 }
8359 /* If X is narrower than MODE and we want all the bits in X's mode, just
8360 get X in the proper mode. */
8365 /* We can ignore the effect of a SUBREG if it narrows the mode or
8366 if the constant masks to zero all the bits the mode doesn't have. */
8376 /* The arithmetic simplifications here only work for scalar integer modes. */
8381 {
8383 /* If X is a (clobber (const_int)), return it since we know we are
8384 generating something that won't match. */
8397 /* Similarly for a truncate. */
8401 /* If this is an AND with a constant, convert it into an AND
8402 whose constant is the AND of that constant with MASK. If it
8403 remains an AND of MASK, delete it since it is redundant. */
8406 {
8410 /* If X is still an AND, see if it is an AND with a mask that
8411 is just some low-order bits. If so, and it is MASK, we don't
8412 need it. */
8419 /* If it remains an AND, try making another AND with the bits
8420 in the mode mask that aren't in MASK turned on. If the
8421 constant in the AND is wide enough, this might make a
8422 cheaper constant. */
8427 {
8428 unsigned HOST_WIDE_INT cval
8431 rtx y;
8438 }
8441 }
8446 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8447 low-order bits (as in an alignment operation) and FOO is already
8448 aligned to that boundary, mask C1 to that boundary as well.
8449 This may eliminate that PLUS and, later, the AND. */
8451 {
8455 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8456 number, sign extend it. */
8469 }
8471 /* ... fall through ... */
8474 /* Substituting into the operands of a widening MULT is not likely to
8475 create RTL matching a machine insn. */
8485 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8486 most significant bit in MASK since carries from those bits will
8487 affect the bits we are interested in. */
8492 /* If X is (minus C Y) where C's least set bit is larger than any bit
8493 in the mask, then we may replace with (neg Y). */
8496 {
8500 }
8502 /* Similarly, if C contains every bit in the fuller_mask, then we may
8503 replace with (not Y). */
8506 {
8510 }
8517 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8518 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8519 operation which may be a bitfield extraction. Ensure that the
8520 constant we form is not wider than the mode of X. */
8532 {
8541 }
8543 binop:
8544 /* For most binary operations, just propagate into the operation and
8545 change the mode if we have an operation of that mode. */
8550 /* If we ended up truncating both operands, truncate the result of the
8551 operation instead. */
8554 {
8557 }
8567 /* For left shifts, do the same, but just for the first operand.
8568 However, we cannot do anything with shifts where we cannot
8569 guarantee that the counts are smaller than the size of the mode
8570 because such a count will have a different meaning in a
8571 wider mode. */
8581 /* If the shift count is a constant and we can do arithmetic in
8582 the mode of the shift, refine which bits we need. Otherwise, use the
8583 conservative form of the mask. */
8589 else
8601 /* Here we can only do something if the shift count is a constant,
8602 this shift constant is valid for the host, and we can do arithmetic
8603 in OP_MODE. */
8609 {
8613 /* Select the mask of the bits we need for the shift operand. */
8616 /* We can only change the mode of the shift if we can do arithmetic
8617 in the mode of the shift and INNER_MASK is no wider than the
8618 width of X's mode. */
8626 }
8628 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8629 shift and AND produces only copies of the sign bit (C2 is one less
8630 than a power of two), we can do this with just a shift. */
8634 /* The shift puts one of the sign bit copies in the least significant
8635 bit. */
8640 /* Number of bits left after the shift must be more than the mask
8641 needs. */
8644 /* Must be more sign bit copies than the mask needs. */
8654 /* If we are just looking for the sign bit, we don't need this shift at
8655 all, even if it has a variable count. */
8659 /* If this is a shift by a constant, get a mask that contains those bits
8660 that are not copies of the sign bit. We then have two cases: If
8661 MASK only includes those bits, this can be a logical shift, which may
8662 allow simplifications. If MASK is a single-bit field not within
8663 those bits, we are requesting a copy of the sign bit and hence can
8664 shift the sign bit to the appropriate location. */
8668 {
8671 /* If the considered data is wider than HOST_WIDE_INT, we can't
8672 represent a mask for all its bits in a single scalar.
8673 But we only care about the lower bits, so calculate these. */
8676 {
8679 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8680 is the number of bits a full-width mask would have set.
8681 We need only shift if these are fewer than nonzero can
8682 hold. If not, we must keep all bits set in nonzero. */
8687 + HOST_BITS_PER_WIDE_INT
8689 }
8690 else
8691 {
8694 }
8697 {
8702 }
8705 {
8706 x = simplify_shift_const
8712 }
8713 }
8715 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8716 even if the shift count isn't a constant. */
8721 shiftrt:
8723 /* If this is a zero- or sign-extension operation that just affects bits
8724 we don't care about, remove it. Be sure the call above returned
8725 something that is still a shift. */
8735 next_select);
8741 /* If the shift count is constant and we can do computations
8742 in the mode of X, compute where the bits we care about are.
8743 Otherwise, we can't do anything. Don't change the mode of
8744 the shift or propagate MODE into the shift, though. */
8747 {
8757 }
8761 /* If we just want the low-order bit, the NEG isn't needed since it
8762 won't change the low-order bit. */
8766 /* We need any bits less significant than the most significant bit in
8767 MASK since carries from those bits will affect the bits we are
8768 interested in. */
8773 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8774 same as the XOR case above. Ensure that the constant we form is not
8775 wider than the mode of X. */
8783 {
8792 }
8794 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8795 use the full mask inside the NOT. */
8798 unop:
8801 next_select));
8807 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8808 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8809 which is equal to STORE_FLAG_VALUE. */
8821 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8822 written in a narrower mode. We play it safe and do not do so. */
8838 }
8840 /* Ensure we return a value of the proper mode. */
8842 }
8843 \f
8844 /* Return nonzero if X is an expression that has one of two values depending on
8845 whether some other value is zero or nonzero. In that case, we return the
8846 value that is being tested, *PTRUE is set to the value if the rtx being
8847 returned has a nonzero value, and *PFALSE is set to the other alternative.
8849 If we return zero, we set *PTRUE and *PFALSE to X. */
8851 static rtx
8853 {
8859 /* If we are comparing a value against zero, we are done. */
8862 {
8866 }
8868 /* If this is a unary operation whose operand has one of two values, apply
8869 our opcode to compute those values. */
8872 {
8877 }
8879 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8880 make can't possibly match and would suppress other optimizations. */
8882 ;
8884 /* If this is a binary operation, see if either side has only one of two
8885 values. If either one does or if both do and they are conditional on
8886 the same value, compute the new true and false values. */
8888 {
8894 {
8895 /* If if_then_else_cond returned zero, then true/false are the
8896 same rtl. We must copy one of them to prevent invalid rtl
8897 sharing. */
8904 {
8909 }
8910 else
8911 {
8914 }
8917 }
8919 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8920 operands is zero when the other is nonzero, and vice-versa,
8921 and STORE_FLAG_VALUE is 1 or -1. */
8927 {
8944 {
8951 const_true_rtx);
8953 }
8954 }
8956 /* Similarly for MULT, AND and UMIN, except that for these the result
8957 is always zero. */
8961 {
8975 {
8978 }
8979 }
8980 }
8983 {
8984 /* If we have IF_THEN_ELSE already, extract the condition and
8985 canonicalize it if it is NE or EQ. */
8991 {
8994 }
8995 else
8997 }
8999 /* If X is a SUBREG, we can narrow both the true and false values
9000 if the inner expression, if there is a condition. */
9004 {
9010 {
9014 }
9015 }
9017 /* If X is a constant, this isn't special and will cause confusions
9018 if we treat it as such. Likewise if it is equivalent to a constant. */
9021 ;
9023 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9024 will be least confusing to the rest of the compiler. */
9026 {
9029 }
9031 /* If X is known to be either 0 or -1, those are the true and
9032 false values when testing X. */
9036 {
9039 }
9041 /* Likewise for 0 or a single bit. */
9044 {
9047 }
9049 /* Otherwise fail; show no condition with true and false values the same. */
9052 }
9053 \f
9054 /* Return the value of expression X given the fact that condition COND
9055 is known to be true when applied to REG as its first operand and VAL
9056 as its second. X is known to not be shared and so can be modified in
9057 place.
9059 We only handle the simplest cases, and specifically those cases that
9060 arise with IF_THEN_ELSE expressions. */
9062 static rtx
9064 {
9072 /* If either operand of the condition is a floating point value,
9073 then we have to avoid collapsing an EQ comparison. */
9083 /* If X is (abs REG) and we know something about REG's relationship
9084 with zero, we may be able to simplify this. */
9088 {
9097 }
9099 /* The only other cases we handle are MIN, MAX, and comparisons if the
9100 operands are the same as REG and VAL. */
9103 {
9105 {
9108 }
9111 {
9113 {
9121 else
9123 }
9126 {
9129 /* Do not reverse the condition when it is NE or EQ.
9130 This is because we cannot conclude anything about
9131 the value of 'SMAX (x, y)' when x is not equal to y,
9132 but we can when x equals y. */
9138 {
9149 }
9150 }
9151 }
9152 }
9154 {
9159 {
9160 /* We must simplify subreg here, before we lose track of the
9161 original inner_mode. */
9166 else
9168 }
9171 }
9172 /* We don't have to handle SIGN_EXTEND here, because even in the
9173 case of replacing something with a modeless CONST_INT, a
9174 CONST_INT is already (supposed to be) a valid sign extension for
9175 its narrower mode, which implies it's already properly
9176 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9177 story is different. */
9179 {
9184 {
9185 /* We must simplify the zero_extend here, before we lose
9186 track of the original inner_mode. */
9191 else
9193 }
9196 }
9200 {
9207 }
9210 }
9211 \f
9212 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9213 assignment as a field assignment. */
9215 static int
9217 {
9219 {
9224 /* For big endian, adjust the memory offset. */
9229 else
9231 }
9239 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9240 Note that all SUBREGs of MEM are paradoxical; otherwise they
9241 would have been rewritten. */
9254 /* We used to see if get_last_value of X and Y were the same but that's
9255 not correct. In one direction, we'll cause the assignment to have
9256 the wrong destination and in the case, we'll import a register into this
9257 insn that might have already have been dead. So fail if none of the
9258 above cases are true. */
9260 }
9261 \f
9262 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9263 Return that assignment if so.
9265 We only handle the most common cases. */
9267 static rtx
9269 {
9272 rtx assign;
9274 HOST_WIDE_INT c1;
9275 HOST_WIDE_INT pos;
9277 rtx other;
9278 machine_mode mode;
9280 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9281 a clear of a one-bit field. We will have changed it to
9282 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9283 for a SUBREG. */
9289 {
9295 }
9305 {
9312 }
9314 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9315 one-bit field. */
9319 {
9325 }
9327 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9328 SRC is an AND with all bits of that field set, then we can discard
9329 the AND. */
9334 {
9341 else
9344 /* Complete overlap. We can remove the source AND. */
9348 /* Partial overlap. We can reduce the source AND. */
9350 {
9355 }
9356 }
9358 /* The other case we handle is assignments into a constant-position
9359 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9360 a mask that has all one bits except for a group of zero bits and
9361 OTHER is known to have zeros where C1 has ones, this is such an
9362 assignment. Compute the position and length from C1. Shift OTHER
9363 to the appropriate position, force it to the required mode, and
9364 make the extraction. Check for the AND in both operands. */
9366 /* One or more SUBREGs might obscure the constant-position field
9367 assignment. The first one we are likely to encounter is an outer
9368 narrowing SUBREG, which we can just strip for the purposes of
9369 identifying the constant-field assignment. */
9383 /* The second SUBREG that might get in the way is a paradoxical
9384 SUBREG around the first operand of the AND. We want to
9385 pretend the operand is as wide as the destination here. We
9386 do this by adjusting the MEM to wider mode for the sole
9387 purpose of the call to rtx_equal_for_field_assignment_p. Also
9388 note this trick only works for MEMs. */
9400 /* The second SUBREG that might get in the way is a paradoxical
9401 SUBREG around the first operand of the AND. We want to
9402 pretend the operand is as wide as the destination here. We
9403 do this by adjusting the MEM to wider mode for the sole
9404 purpose of the call to rtx_equal_for_field_assignment_p. Also
9405 note this trick only works for MEMs. */
9413 else
9426 /* The mode to use for the source is the mode of the assignment, or of
9427 what is inside a possible STRICT_LOW_PART. */
9431 /* Shift OTHER right POS places and make it the source, restricting it
9432 to the proper length and mode. */
9437 dest);
9444 /* If SRC is masked by an AND that does not make a difference in
9445 the value being stored, strip it. */
9456 }
9457 \f
9458 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9459 if so. */
9461 static rtx
9463 {
9467 rtx tem;
9469 /* Distributivity is not true for floating point as it can change the
9470 value. So we don't do it unless -funsafe-math-optimizations. */
9475 /* The outer operation can only be one of the following: */
9483 /* If either operand is a primitive we can't do anything, so get out
9484 fast. */
9494 /* See if the inner and outer operations distribute. */
9496 {
9501 /* These all distribute except over PLUS. */
9512 /* This is also a multiply, so it distributes over everything. */
9515 /* This used to handle SUBREG, but this turned out to be counter-
9516 productive, since (subreg (op ...)) usually is not handled by
9517 insn patterns, and this "optimization" therefore transformed
9518 recognizable patterns into unrecognizable ones. Therefore the
9519 SUBREG case was removed from here.
9521 It is possible that distributing SUBREG over arithmetic operations
9522 leads to an intermediate result than can then be optimized further,
9523 e.g. by moving the outer SUBREG to the other side of a SET as done
9524 in simplify_set. This seems to have been the original intent of
9525 handling SUBREGs here.
9527 However, with current GCC this does not appear to actually happen,
9528 at least on major platforms. If some case is found where removing
9529 the SUBREG case here prevents follow-on optimizations, distributing
9530 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9534 }
9536 /* Set LHS and RHS to the inner operands (A and B in the example
9537 above) and set OTHER to the common operand (C in the example).
9538 There is only one way to do this unless the inner operation is
9539 commutative. */
9551 else
9554 /* Form the new inner operation, seeing if it simplifies first. */
9557 /* There is one exception to the general way of distributing:
9558 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9560 {
9563 }
9565 /* We may be able to continuing distributing the result, so call
9566 ourselves recursively on the inner operation before forming the
9567 outer operation, which we return. */
9570 }
9572 /* See if X is of the form (* (+ A B) C), and if so convert to
9573 (+ (* A C) (* B C)) and try to simplify.
9575 Most of the time, this results in no change. However, if some of
9576 the operands are the same or inverses of each other, simplifications
9577 will result.
9579 For example, (and (ior A B) (not B)) can occur as the result of
9580 expanding a bit field assignment. When we apply the distributive
9581 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9582 which then simplifies to (and (A (not B))).
9584 Note that no checks happen on the validity of applying the inverse
9585 distributive law. This is pointless since we can do it in the
9586 few places where this routine is called.
9588 N is the index of the term that is decomposed (the arithmetic operation,
9589 i.e. (+ A B) in the first example above). !N is the index of the term that
9590 is distributed, i.e. of C in the first example above. */
9591 static rtx
9593 {
9594 machine_mode mode;
9598 /* Distributivity is not true for floating point as it can change the
9599 value. So we don't do it unless -funsafe-math-optimizations. */
9616 /* Special case (and (xor B C) (not A)), which is equivalent to
9617 (xor (ior A B) (ior A C)) */
9619 {
9622 }
9625 {
9626 /* Distribute the second term. */
9629 }
9630 else
9631 {
9632 /* Distribute the first term. */
9635 }
9645 }
9646 \f
9647 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9648 in MODE. Return an equivalent form, if different from (and VAROP
9649 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9651 static rtx
9654 {
9657 rtx orig_varop;
9665 /* Simplify VAROP knowing that we will be only looking at some of the
9666 bits in it.
9668 Note by passing in CONSTOP, we guarantee that the bits not set in
9669 CONSTOP are not significant and will never be examined. We must
9670 ensure that is the case by explicitly masking out those bits
9671 before returning. */
9674 /* If VAROP is a CLOBBER, we will fail so return it. */
9678 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9679 to VAROP and return the new constant. */
9683 /* See what bits may be nonzero in VAROP. Unlike the general case of
9684 a call to nonzero_bits, here we don't care about bits outside
9685 MODE. */
9689 /* Turn off all bits in the constant that are known to already be zero.
9690 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9691 which is tested below. */
9695 /* If we don't have any bits left, return zero. */
9699 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9700 a power of two, we can replace this with an ASHIFT. */
9705 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9706 or XOR, then try to apply the distributive law. This may eliminate
9707 operations if either branch can be simplified because of the AND.
9708 It may also make some cases more complex, but those cases probably
9709 won't match a pattern either with or without this. */
9712 return
9713 gen_lowpart
9715 apply_distributive_law
9720 constop),
9724 constop))));
9726 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9727 the AND and see if one of the operands simplifies to zero. If so, we
9728 may eliminate it. */
9732 {
9741 }
9743 /* Make a SUBREG if necessary. If we can't make it, fail. */
9748 /* If we are only masking insignificant bits, return VAROP. */
9755 /* Otherwise, return an AND. */
9757 }
9760 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9761 in MODE.
9763 Return an equivalent form, if different from X. Otherwise, return X. If
9764 X is zero, we are to always construct the equivalent form. */
9766 static rtx
9769 {
9780 }
9781 \f
9782 /* Given a REG, X, compute which bits in X can be nonzero.
9783 We don't care about bits outside of those defined in MODE.
9785 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9786 a shift, AND, or zero_extract, we can do better. */
9788 static rtx
9790 const_rtx known_x ATTRIBUTE_UNUSED,
9791 machine_mode known_mode ATTRIBUTE_UNUSED,
9794 {
9795 rtx tem;
9798 /* If X is a register whose nonzero bits value is current, use it.
9799 Otherwise, if X is a register whose value we can find, use that
9800 value. Otherwise, use the previously-computed global nonzero bits
9801 for this register. */
9815 && !REGNO_REG_SET_P
9818 {
9822 /* We don't know anything about the upper bits. */
9827 }
9832 {
9838 }
9840 {
9844 /* We don't know anything about the upper bits. */
9848 }
9851 }
9853 /* Return the number of bits at the high-order end of X that are known to
9854 be equal to the sign bit. X will be used in mode MODE; if MODE is
9855 VOIDmode, X will be used in its own mode. The returned value will always
9856 be between 1 and the number of bits in MODE. */
9858 static rtx
9860 const_rtx known_x ATTRIBUTE_UNUSED,
9861 machine_mode known_mode
9862 ATTRIBUTE_UNUSED,
9865 {
9866 rtx tem;
9879 && !REGNO_REG_SET_P
9882 {
9885 }
9896 }
9897 \f
9898 /* Return the number of "extended" bits there are in X, when interpreted
9899 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9900 unsigned quantities, this is the number of high-order zero bits.
9901 For signed quantities, this is the number of copies of the sign bit
9902 minus 1. In both case, this function returns the number of "spare"
9903 bits. For example, if two quantities for which this function returns
9904 at least 1 are added, the addition is known not to overflow.
9906 This function will always return 0 unless called during combine, which
9907 implies that it must be called from a define_split. */
9909 unsigned int
9911 {
9921 }
9923 /* This function is called from `simplify_shift_const' to merge two
9924 outer operations. Specifically, we have already found that we need
9925 to perform operation *POP0 with constant *PCONST0 at the outermost
9926 position. We would now like to also perform OP1 with constant CONST1
9927 (with *POP0 being done last).
9929 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9930 the resulting operation. *PCOMP_P is set to 1 if we would need to
9931 complement the innermost operand, otherwise it is unchanged.
9933 MODE is the mode in which the operation will be done. No bits outside
9934 the width of this mode matter. It is assumed that the width of this mode
9935 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9937 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9938 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9939 result is simply *PCONST0.
9941 If the resulting operation cannot be expressed as one operation, we
9942 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9944 static int
9945 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
9946 {
9953 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9957 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9958 if OP0 is SET. */
9967 {
9969 {
9987 }
9988 }
9990 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9994 /* If the two constants aren't the same, we can't do anything. The
9995 remaining six cases can all be done. */
9999 else
10001 {
10004 /* (a & b) | b == b */
10007 /* (a ^ b) | b == a | b */
10008 {;}
10013 /* (a & b) ^ b == (~a) & b */
10016 /* (a | b) ^ b == a & ~b */
10022 /* (a | b) & b == b */
10025 /* (a ^ b) & b) == (~a) & b */
10030 }
10032 /* Check for NO-OP cases. */
10045 /* ??? Slightly redundant with the above mask, but not entirely.
10046 Moving this above means we'd have to sign-extend the mode mask
10047 for the final test. */
10052 }
10053 \f
10054 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10055 the shift in. The original shift operation CODE is performed on OP in
10056 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10057 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10058 result of the shift is subject to operation OUTER_CODE with operand
10059 OUTER_CONST. */
10061 static machine_mode
10065 {
10070 /* In general we can't perform in wider mode for right shift and rotate. */
10072 {
10074 /* We can still widen if the bits brought in from the left are identical
10075 to the sign bit of ORIG_MODE. */
10083 /* Similarly here but with zero bits. */
10088 /* We can also widen if the bits brought in will be masked off. This
10089 operation is performed in ORIG_MODE. */
10091 {
10097 }
10098 /* fall through */
10108 }
10109 }
10111 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10112 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10113 if we cannot simplify it. Otherwise, return a simplified value.
10115 The shift is normally computed in the widest mode we find in VAROP, as
10116 long as it isn't a different number of words than RESULT_MODE. Exceptions
10117 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10119 static rtx
10122 {
10128 unsigned int mode_words
10130 /* We form (outer_op (code varop count) (outer_const)). */
10136 /* Make sure and truncate the "natural" shift on the way in. We don't
10137 want to do this inside the loop as it makes it more difficult to
10138 combine shifts. */
10142 /* If we were given an invalid count, don't do anything except exactly
10143 what was requested. */
10150 /* Unless one of the branches of the `if' in this loop does a `continue',
10151 we will `break' the loop after the `if'. */
10154 {
10155 /* If we have an operand of (clobber (const_int 0)), fail. */
10159 /* Convert ROTATERT to ROTATE. */
10161 {
10166 else
10168 }
10173 /* Handle cases where the count is greater than the size of the mode
10174 minus 1. For ASHIFT, use the size minus one as the count (this can
10175 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10176 take the count modulo the size. For other shifts, the result is
10177 zero.
10179 Since these shifts are being produced by the compiler by combining
10180 multiple operations, each of which are defined, we know what the
10181 result is supposed to be. */
10184 {
10189 else
10190 {
10191 /* We can't simply return zero because there may be an
10192 outer op. */
10196 }
10197 }
10199 /* If we discovered we had to complement VAROP, leave. Making a NOT
10200 here would cause an infinite loop. */
10204 /* An arithmetic right shift of a quantity known to be -1 or 0
10205 is a no-op. */
10209 {
10212 }
10214 /* If we are doing an arithmetic right shift and discarding all but
10215 the sign bit copies, this is equivalent to doing a shift by the
10216 bitsize minus one. Convert it into that shift because it will often
10217 allow other simplifications. */
10224 /* We simplify the tests below and elsewhere by converting
10225 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10226 `make_compound_operation' will convert it to an ASHIFTRT for
10227 those machines (such as VAX) that don't have an LSHIFTRT. */
10244 {
10251 {
10254 }
10258 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10259 minus the width of a smaller mode, we can do this with a
10260 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10267 {
10276 }
10280 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10281 the same number of words as what we've seen so far. Then store
10282 the widest mode in MODE. */
10288 == mode_words
10291 {
10296 }
10300 /* Some machines use MULT instead of ASHIFT because MULT
10301 is cheaper. But it is still better on those machines to
10302 merge two shifts into one. */
10305 {
10306 varop
10312 }
10316 /* Similar, for when divides are cheaper. */
10319 {
10320 varop
10326 }
10330 /* If we are extracting just the sign bit of an arithmetic
10331 right shift, that shift is not needed. However, the sign
10332 bit of a wider mode may be different from what would be
10333 interpreted as the sign bit in a narrower mode, so, if
10334 the result is narrower, don't discard the shift. */
10339 {
10342 }
10344 /* ... fall through ... */
10349 /* Here we have two nested shifts. The result is usually the
10350 AND of a new shift with a mask. We compute the result below. */
10357 {
10361 rtx mask_rtx;
10363 /* We have one common special case. We can't do any merging if
10364 the inner code is an ASHIFTRT of a smaller mode. However, if
10365 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10366 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10367 we can convert it to
10368 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10369 This simplifies certain SIGN_EXTEND operations. */
10373 {
10374 /* C3 has the low-order C1 bits zero. */
10386 }
10388 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10389 than C1 high-order bits equal to the sign bit, we can convert
10390 this to either an ASHIFT or an ASHIFTRT depending on the
10391 two counts.
10393 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10399 {
10403 {
10406 }
10409 }
10411 /* There are some cases we can't do. If CODE is ASHIFTRT,
10412 we can only do this if FIRST_CODE is also ASHIFTRT.
10414 We can't do the case when CODE is ROTATE and FIRST_CODE is
10415 ASHIFTRT.
10417 If the mode of this shift is not the mode of the outer shift,
10418 we can't do this if either shift is a right shift or ROTATE.
10420 Finally, we can't do any of these if the mode is too wide
10421 unless the codes are the same.
10423 Handle the case where the shift codes are the same
10424 first. */
10427 {
10436 }
10447 /* To compute the mask to apply after the shift, shift the
10448 nonzero bits of the inner shift the same way the
10449 outer shift will. */
10452 result_mode);
10454 mask_rtx
10458 /* Give up if we can't compute an outer operation to use. */
10466 /* If the shifts are in the same direction, we add the
10467 counts. Otherwise, we subtract them. */
10471 else
10474 /* If COUNT is positive, the new shift is usually CODE,
10475 except for the two exceptions below, in which case it is
10476 FIRST_CODE. If the count is negative, FIRST_CODE should
10477 always be used */
10487 }
10489 /* If we have (A << B << C) for any shift, we can convert this to
10490 (A << C << B). This wins if A is a constant. Only try this if
10491 B is not a constant. */
10496 {
10503 }
10510 /* Make this fit the case below. */
10517 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10518 with C the size of VAROP - 1 and the shift is logical if
10519 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10520 we have an (le X 0) operation. If we have an arithmetic shift
10521 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10522 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10530 {
10533 const0_rtx);
10539 }
10541 /* If we have (shift (logical)), move the logical to the outside
10542 to allow it to possibly combine with another logical and the
10543 shift to combine with another shift. This also canonicalizes to
10544 what a ZERO_EXTRACT looks like. Also, some machines have
10545 (and (shift)) insns. */
10548 /* We can't do this if we have (ashiftrt (xor)) and the
10549 constant has its sign bit set in shift_mode with shift_mode
10550 wider than result_mode. */
10554 shift_mode))
10562 {
10565 }
10567 /* If we can't do that, try to simplify the shift in each arm of the
10568 logical expression, make a new logical expression, and apply
10569 the inverse distributive law. This also can't be done for
10570 (ashiftrt (xor)) where we've widened the shift and the constant
10571 changes the sign bit. */
10576 shift_mode)))
10577 {
10589 }
10593 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10594 says that the sign bit can be tested, FOO has mode MODE, C is
10595 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10596 that may be nonzero. */
10606 {
10610 }
10614 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10615 than the number of bits in the mode is equivalent to A. */
10619 {
10623 }
10625 /* NEG commutes with ASHIFT since it is multiplication. Move the
10626 NEG outside to allow shifts to combine. */
10630 {
10633 }
10637 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10638 is one less than the number of bits in the mode is
10639 equivalent to (xor A 1). */
10646 {
10650 }
10652 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10653 that might be nonzero in BAR are those being shifted out and those
10654 bits are known zero in FOO, we can replace the PLUS with FOO.
10655 Similarly in the other operand order. This code occurs when
10656 we are computing the size of a variable-size array. */
10663 {
10666 }
10674 result_mode)))
10675 {
10678 }
10680 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10690 {
10693 }
10695 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10696 signbit', and attempt to change the PLUS to an XOR and move it to
10697 the outer operation as is done above in the AND/IOR/XOR case
10698 leg for shift(logical). See details in logical handling above
10699 for reasoning in doing so. */
10710 {
10713 }
10718 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10719 with C the size of VAROP - 1 and the shift is logical if
10720 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10721 we have a (gt X 0) operation. If the shift is arithmetic with
10722 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10723 we have a (neg (gt X 0)) operation. */
10732 {
10735 const0_rtx);
10741 }
10745 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10746 if the truncate does not affect the value. */
10753 {
10756 varop_inner
10759 GEN_INT
10764 }
10769 }
10772 }
10777 /* We have now finished analyzing the shift. The result should be
10778 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10779 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10780 to the result of the shift. OUTER_CONST is the relevant constant,
10781 but we must turn off all bits turned off in the shift. */
10789 /* Make a SUBREG if necessary. If we can't make it, fail. */
10794 /* If we have an outer operation and we just made a shift, it is
10795 possible that we could have simplified the shift were it not
10796 for the outer operation. So try to do the simplification
10797 recursively. */
10801 else
10807 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10808 turn off all the bits that the shift would have turned off. */
10813 /* Do the remainder of the processing in RESULT_MODE. */
10816 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10817 operation. */
10822 {
10830 {
10831 /* This means that we have determined that the result is
10832 equivalent to a constant. This should be rare. */
10835 }
10838 else
10841 }
10844 }
10846 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10847 The result of the shift is RESULT_MODE. If we cannot simplify it,
10848 return X or, if it is NULL, synthesize the expression with
10849 simplify_gen_binary. Otherwise, return a simplified value.
10851 The shift is normally computed in the widest mode we find in VAROP, as
10852 long as it isn't a different number of words than RESULT_MODE. Exceptions
10853 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10855 static rtx
10858 {
10868 }
10870 \f
10871 /* A subroutine of recog_for_combine. See there for arguments and
10872 return value. */
10874 static int
10876 {
10878 rtx pat_without_clobbers;
10886 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10887 we use to indicate that something didn't match. If we find such a
10888 thing, force rejection. */
10902 {
10905 else
10908 }
10910 /* If it isn't, there is the possibility that we previously had an insn
10911 that clobbered some register as a side effect, but the combined
10912 insn doesn't need to do that. So try once more without the clobbers
10913 unless this represents an ASM insn. */
10917 {
10922 {
10925 pos++;
10926 }
10936 {
10939 else
10942 }
10943 }
10950 /* Recognize all noop sets, these will be killed by followup pass. */
10954 /* If we had any clobbers to add, make a new pattern than contains
10955 them. Then check to make sure that all of them are dead. */
10957 {
10967 else
10974 {
10979 {
10983 }
10984 }
10986 }
10990 {
10997 /* Allow targets to reject combined insn. */
10999 {
11002 dump_file);
11004 /* Callers expect recog_for_combine to strip
11005 clobbers from the pattern on failure. */
11010 }
11015 }
11021 }
11023 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11024 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11025 Return whether anything was so changed. */
11027 static bool
11029 {
11034 {
11043 {
11051 }
11056 {
11059 }
11060 else
11065 mask--;
11071 }
11074 }
11076 /* Like recog, but we receive the address of a pointer to a new pattern.
11077 We try to match the rtx that the pointer points to.
11078 If that fails, we may try to modify or replace the pattern,
11079 storing the replacement into the same pointer object.
11081 Modifications include deletion or addition of CLOBBERs. If the
11082 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11083 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11084 (and undo if that fails).
11086 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11087 the CLOBBERs are placed.
11089 The value is the final insn code from the pattern ultimately matched,
11090 or -1. */
11092 static int
11094 {
11106 {
11109 {
11113 }
11114 }
11117 {
11122 }
11125 }
11126 \f
11127 /* Like gen_lowpart_general but for use by combine. In combine it
11128 is not possible to create any new pseudoregs. However, it is
11129 safe to create invalid memory addresses, because combine will
11130 try to recognize them and all they will do is make the combine
11131 attempt fail.
11133 If for some reason this cannot do its job, an rtx
11134 (clobber (const_int 0)) is returned.
11135 An insn containing that will not be recognized. */
11137 static rtx
11139 {
11143 rtx result;
11148 /* We can only support MODE being wider than a word if X is a
11149 constant integer or has a mode the same size. */
11154 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11155 won't know what to do. So we will strip off the SUBREG here and
11156 process normally. */
11158 {
11161 /* For use in case we fall down into the address adjustments
11162 further below, we need to adjust the known mode and size of
11163 x; imode and isize, since we just adjusted x. */
11170 }
11178 {
11181 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11182 address. */
11187 /* If we want to refer to something bigger than the original memref,
11188 generate a paradoxical subreg instead. That will force a reload
11189 of the original memref X. */
11196 /* Adjust the address so that the address-after-the-data is
11197 unchanged. */
11202 }
11204 /* If X is a comparison operator, rewrite it in a new mode. This
11205 probably won't match, but may allow further simplifications. */
11209 /* If we couldn't simplify X any other way, just enclose it in a
11210 SUBREG. Normally, this SUBREG won't match, but some patterns may
11211 include an explicit SUBREG or we may simplify it further in combine. */
11212 else
11213 {
11214 rtx res;
11217 {
11222 }
11226 }
11228 fail:
11230 }
11231 \f
11232 /* Try to simplify a comparison between OP0 and a constant OP1,
11233 where CODE is the comparison code that will be tested, into a
11234 (CODE OP0 const0_rtx) form.
11236 The result is a possibly different comparison code to use.
11237 *POP1 may be updated. */
11239 static enum rtx_code
11242 {
11246 /* Get the constant we are comparing against and turn off all bits
11247 not on in our mode. */
11251 /* If we are comparing against a constant power of two and the value
11252 being compared can only have that single bit nonzero (e.g., it was
11253 `and'ed with that bit), we can replace this with a comparison
11254 with zero. */
11262 {
11265 }
11267 /* Similarly, if we are comparing a value known to be either -1 or
11268 0 with -1, change it to the opposite comparison against zero. */
11273 {
11276 }
11278 /* Do some canonicalizations based on the comparison code. We prefer
11279 comparisons against zero and then prefer equality comparisons.
11280 If we can reduce the size of a constant, we will do that too. */
11282 {
11284 /* < C is equivalent to <= (C - 1) */
11286 {
11289 /* ... fall through to LE case below. */
11290 }
11291 else
11295 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11297 {
11300 }
11302 /* If we are doing a <= 0 comparison on a value known to have
11303 a zero sign bit, we can replace this with == 0. */
11313 /* >= C is equivalent to > (C - 1). */
11315 {
11318 /* ... fall through to GT below. */
11319 }
11320 else
11324 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11326 {
11329 }
11331 /* If we are doing a > 0 comparison on a value known to have
11332 a zero sign bit, we can replace this with != 0. */
11342 /* < C is equivalent to <= (C - 1). */
11344 {
11347 /* ... fall through ... */
11348 }
11349 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11353 {
11357 }
11358 else
11362 /* unsigned <= 0 is equivalent to == 0 */
11365 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11369 {
11372 }
11376 /* >= C is equivalent to > (C - 1). */
11378 {
11381 /* ... fall through ... */
11382 }
11384 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11388 {
11392 }
11393 else
11397 /* unsigned > 0 is equivalent to != 0 */
11400 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11404 {
11407 }
11412 }
11416 }
11417 \f
11418 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11419 comparison code that will be tested.
11421 The result is a possibly different comparison code to use. *POP0 and
11422 *POP1 may be updated.
11424 It is possible that we might detect that a comparison is either always
11425 true or always false. However, we do not perform general constant
11426 folding in combine, so this knowledge isn't useful. Such tautologies
11427 should have been detected earlier. Hence we ignore all such cases. */
11429 static enum rtx_code
11431 {
11438 /* Try a few ways of applying the same transformation to both operands. */
11440 {
11441 #if !WORD_REGISTER_OPERATIONS
11442 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11443 so check specially. */
11458 - (GET_MODE_PRECISION
11460 {
11463 }
11464 #endif
11466 /* If both operands are the same constant shift, see if we can ignore the
11467 shift. We can if the shift is a rotate or if the bits shifted out of
11468 this shift are known to be zero for both inputs and if the type of
11469 comparison is compatible with the shift. */
11482 {
11495 else
11497 }
11499 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11500 SUBREGs are of the same mode, and, in both cases, the AND would
11501 be redundant if the comparison was done in the narrower mode,
11502 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11503 and the operand's possibly nonzero bits are 0xffffff01; in that case
11504 if we only care about QImode, we don't need the AND). This case
11505 occurs if the output mode of an scc insn is not SImode and
11506 STORE_FLAG_VALUE == 1 (e.g., the 386).
11508 Similarly, check for a case where the AND's are ZERO_EXTEND
11509 operations from some narrower mode even though a SUBREG is not
11510 present. */
11515 {
11532 {
11536 /* The resulting comparison is always unsigned since we masked
11537 off the original sign bit. */
11541 }
11548 {
11554 }
11558 }
11560 /* If both operands are NOT, we can strip off the outer operation
11561 and adjust the comparison code for swapped operands; similarly for
11562 NEG, except that this must be an equality comparison. */
11568 else
11570 }
11572 /* If the first operand is a constant, swap the operands and adjust the
11573 comparison code appropriately, but don't do this if the second operand
11574 is already a constant integer. */
11576 {
11579 }
11581 /* We now enter a loop during which we will try to simplify the comparison.
11582 For the most part, we only are concerned with comparisons with zero,
11583 but some things may really be comparisons with zero but not start
11584 out looking that way. */
11587 {
11594 HOST_WIDE_INT const_op;
11596 /* We only want to handle integral modes. This catches VOIDmode,
11597 CCmode, and the floating-point modes. An exception is that we
11598 can handle VOIDmode if OP0 is a COMPARE or a comparison
11599 operation. */
11606 /* Try to simplify the compare to constant, possibly changing the
11607 comparison op, and/or changing op1 to zero. */
11611 /* Compute some predicates to simplify code below. */
11618 /* If this is a sign bit comparison and we can do arithmetic in
11619 MODE, say that we will only be needing the sign bit of OP0. */
11626 /* Now try cases based on the opcode of OP0. If none of the cases
11627 does a "continue", we exit this loop immediately after the
11628 switch. */
11631 {
11633 /* If we are extracting a single bit from a variable position in
11634 a constant that has only a single bit set and are comparing it
11635 with zero, we can convert this into an equality comparison
11636 between the position and the location of the single bit. */
11637 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11638 have already reduced the shift count modulo the word size. */
11644 {
11652 /* Result is nonzero iff shift count is equal to I. */
11655 }
11657 /* ... fall through ... */
11662 {
11665 }
11669 /* If testing for equality, we can take the NOT of the constant. */
11672 {
11676 }
11678 /* If just looking at the sign bit, reverse the sense of the
11679 comparison. */
11681 {
11685 }
11689 /* If testing for equality, we can take the NEG of the constant. */
11692 {
11696 }
11698 /* The remaining cases only apply to comparisons with zero. */
11702 /* When X is ABS or is known positive,
11703 (neg X) is < 0 if and only if X != 0. */
11711 {
11715 }
11717 /* If we have NEG of something whose two high-order bits are the
11718 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11720 {
11724 }
11728 /* If we are testing equality and our count is a constant, we
11729 can perform the inverse operation on our RHS. */
11733 {
11737 }
11739 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11740 a particular bit. Convert it to an AND of a constant of that
11741 bit. This will be converted into a ZERO_EXTRACT. */
11745 {
11752 }
11754 /* Fall through. */
11757 /* ABS is ignorable inside an equality comparison with zero. */
11759 {
11762 }
11766 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11767 (compare FOO CONST) if CONST fits in FOO's mode and we
11768 are either testing inequality or have an unsigned
11769 comparison with ZERO_EXTEND or a signed comparison with
11770 SIGN_EXTEND. But don't do it if we don't have a compare
11771 insn of the given mode, since we'd have to revert it
11772 later on, and then we wouldn't know whether to sign- or
11773 zero-extend. */
11776 && ! unsigned_comparison_p
11780 {
11783 }
11787 /* Check for the case where we are comparing A - C1 with C2, that is
11789 (subreg:MODE (plus (A) (-C1))) op (C2)
11791 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11792 comparison in the wider mode. One of the following two conditions
11793 must be true in order for this to be valid:
11795 1. The mode extension results in the same bit pattern being added
11796 on both sides and the comparison is equality or unsigned. As
11797 C2 has been truncated to fit in MODE, the pattern can only be
11798 all 0s or all 1s.
11800 2. The mode extension results in the sign bit being copied on
11801 each side.
11803 The difficulty here is that we have predicates for A but not for
11804 (A - C1) so we need to check that C1 is within proper bounds so
11805 as to perturbate A as little as possible. */
11812 {
11821 /* (A - C1) zero-extends if it is positive and sign-extends
11822 if it is negative, C2 both zero- and sign-extends. */
11826 /* (A - C1) sign-extends if it is positive and 1-extends
11827 if it is negative, C2 both sign- and 1-extends. */
11834 /* (A - C1) always sign-extends, like C2. */
11838 {
11841 }
11842 }
11844 /* If the inner mode is narrower and we are extracting the low part,
11845 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11849 else
11852 /* ... fall through ... */
11862 {
11865 }
11869 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11870 this for equality comparisons due to pathological cases involving
11871 overflows. */
11875 {
11879 }
11881 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11884 {
11888 }
11892 /* We used to optimize signed comparisons against zero, but that
11893 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11894 arrive here as equality comparisons, or (GEU, LTU) are
11895 optimized away. No need to special-case them. */
11897 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11898 (eq B (minus A C)), whichever simplifies. We can only do
11899 this for equality comparisons due to pathological cases involving
11900 overflows. */
11904 {
11908 }
11913 {
11917 }
11919 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11920 of bits in X minus 1, is one iff X > 0. */
11925 {
11929 }
11933 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11934 if C is zero or B is a constant. */
11938 {
11942 }
11950 /* We can't do anything if OP0 is a condition code value, rather
11951 than an actual data value. */
11957 /* Get the two operands being compared. */
11960 else
11963 /* Check for the cases where we simply want the result of the
11964 earlier test or the opposite of that result. */
11968 {
11972 else
11976 {
11981 }
11982 }
11986 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11987 iff X <= 0. */
11991 {
11995 }
11999 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12000 will be converted to a ZERO_EXTRACT later. */
12004 {
12009 }
12011 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12012 zero and X is a comparison and C1 and C2 describe only bits set
12013 in STORE_FLAG_VALUE, we can compare with X. */
12021 {
12028 {
12031 }
12032 }
12034 /* If we are doing an equality comparison of an AND of a bit equal
12035 to the sign bit, replace this with a LT or GE comparison of
12036 the underlying value. */
12043 {
12047 }
12049 /* If this AND operation is really a ZERO_EXTEND from a narrower
12050 mode, the constant fits within that mode, and this is either an
12051 equality or unsigned comparison, try to do this comparison in
12052 the narrower mode.
12054 Note that in:
12056 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12057 -> (ne:DI (reg:SI 4) (const_int 0))
12059 unless TRULY_NOOP_TRUNCATION allows it or the register is
12060 known to hold a value of the required mode the
12061 transformation is invalid. */
12069 {
12072 }
12074 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12075 fits in both M1 and M2 and the SUBREG is either paradoxical
12076 or represents the low part, permute the SUBREG and the AND
12077 and try again. */
12080 {
12083 /* Require an integral mode, to avoid creating something like
12084 (AND:SF ...). */
12086 /* It is unsafe to commute the AND into the SUBREG if the
12087 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12088 not defined. As originally written the upper bits
12089 have a defined value due to the AND operation.
12090 However, if we commute the AND inside the SUBREG then
12091 they no longer have defined values and the meaning of
12092 the code has been changed.
12093 Also C1 should not change value in the smaller mode,
12094 see PR67028 (a positive C1 can become negative in the
12095 smaller mode, so that the AND does no longer mask the
12096 upper bits). */
12097 && ((WORD_REGISTER_OPERATIONS
12109 {
12115 }
12116 }
12118 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12122 {
12127 }
12129 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12130 (eq (and (lshiftrt X) 1) 0).
12131 Also handle the case where (not X) is expressed using xor. */
12135 {
12147 {
12148 op0
12153 }
12154 }
12158 /* If we have (compare (ashift FOO N) (const_int C)) and
12159 the high order N bits of FOO (N+1 if an inequality comparison)
12160 are known to be zero, we can do this by comparing FOO with C
12161 shifted right N bits so long as the low-order N bits of C are
12162 zero. */
12174 {
12175 /* We must perform a logical shift, not an arithmetic one,
12176 as we want the top N bits of C to be zero. */
12183 }
12185 /* If we are doing a sign bit comparison, it means we are testing
12186 a particular bit. Convert it to the appropriate AND. */
12189 {
12196 }
12198 /* If this an equality comparison with zero and we are shifting
12199 the low bit to the sign bit, we can convert this to an AND of the
12200 low-order bit. */
12204 {
12207 }
12211 /* If this is an equality comparison with zero, we can do this
12212 as a logical shift, which might be much simpler. */
12215 {
12220 }
12222 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12223 do the comparison in a narrower mode. */
12233 {
12236 }
12238 /* Likewise if OP0 is a PLUS of a sign extension with a
12239 constant, which is usually represented with the PLUS
12240 between the shifts. */
12252 {
12260 new_const);
12262 }
12264 /* ... fall through ... */
12266 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12267 the low order N bits of FOO are known to be zero, we can do this
12268 by comparing FOO with C shifted left N bits so long as no
12269 overflow occurs. Even if the low order N bits of FOO aren't known
12270 to be zero, if the comparison is >= or < we can use the same
12271 optimization and for > or <= by setting all the low
12272 order N bits in the comparison constant. */
12283 {
12284 unsigned HOST_WIDE_INT low_bits
12289 {
12290 /* If the shift was logical, then we must make the condition
12291 unsigned. */
12299 const_op
12304 }
12305 }
12307 /* If we are using this shift to extract just the sign bit, we
12308 can replace this with an LT or GE comparison. */
12313 {
12317 }
12322 }
12325 }
12327 /* Now make any compound operations involved in this comparison. Then,
12328 check for an outmost SUBREG on OP0 that is not doing anything or is
12329 paradoxical. The latter transformation must only be performed when
12330 it is known that the "extra" bits will be the same in op0 and op1 or
12331 that they don't matter. There are three cases to consider:
12333 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12334 care bits and we can assume they have any convenient value. So
12335 making the transformation is safe.
12337 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12338 In this case the upper bits of op0 are undefined. We should not make
12339 the simplification in that case as we do not know the contents of
12340 those bits.
12342 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12343 UNKNOWN. In that case we know those bits are zeros or ones. We must
12344 also be sure that they are the same as the upper bits of op1.
12346 We can never remove a SUBREG for a non-equality comparison because
12347 the sign bit is in a different place in the underlying object. */
12356 {
12358 {
12359 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12360 implemented. */
12362 {
12365 }
12366 }
12372 {
12378 }
12379 }
12381 /* We now do the opposite procedure: Some machines don't have compare
12382 insns in all modes. If OP0's mode is an integer mode smaller than a
12383 word and we can't do a compare in that mode, see if there is a larger
12384 mode for which we can do the compare. There are a number of cases in
12385 which we can use the wider mode. */
12395 {
12398 /* If this is a test for negative, we can make an explicit
12399 test of the sign bit. Test this first so we can use
12400 a paradoxical subreg to extend OP0. */
12404 {
12405 unsigned HOST_WIDE_INT sign
12412 }
12414 /* If the only nonzero bits in OP0 and OP1 are those in the
12415 narrower mode and this is an equality or unsigned comparison,
12416 we can use the wider mode. Similarly for sign-extended
12417 values, in which case it is true for all comparisons. */
12434 {
12435 /* If OP0 is an AND and we don't have an AND in MODE either,
12436 make a new AND in the proper mode. */
12444 else
12445 {
12447 {
12450 }
12451 else
12452 {
12455 }
12457 }
12458 }
12459 }
12461 /* We may have changed the comparison operands. Re-canonicalize. */
12463 {
12466 }
12468 /* If this machine only supports a subset of valid comparisons, see if we
12469 can convert an unsupported one into a supported one. */
12476 }
12477 \f
12478 /* Utility function for record_value_for_reg. Count number of
12479 rtxs in X. */
12480 static int
12482 {
12489 {
12509 }
12520 }
12521 \f
12522 /* Utility function for following routine. Called when X is part of a value
12523 being stored into last_set_value. Sets last_set_table_tick
12524 for each register mentioned. Similar to mention_regs in cse.c */
12526 static void
12528 {
12534 {
12540 {
12543 }
12546 }
12550 {
12551 /* Check for identical subexpressions. If x contains
12552 identical subexpression we only have to traverse one of
12553 them. */
12555 {
12556 /* Note that at this point x1 has already been
12557 processed. */
12561 /* If x0 and x1 are identical then there is no need to
12562 process x0. */
12566 /* If x0 is identical to a subexpression of x1 then while
12567 processing x1, x0 has already been processed. Thus we
12568 are done with x. */
12573 /* If x1 is identical to a subexpression of x0 then we
12574 still have to process the rest of x0. */
12577 {
12580 }
12581 }
12584 }
12588 }
12590 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12591 are saying that the register is clobbered and we no longer know its
12592 value. If INSN is zero, don't update reg_stat[].last_set; this is
12593 only permitted with VALUE also zero and is used to invalidate the
12594 register. */
12596 static void
12598 {
12604 /* If VALUE contains REG and we have a previous value for REG, substitute
12605 the previous value. */
12607 {
12608 rtx tem;
12610 /* Set things up so get_last_value is allowed to see anything set up to
12611 our insn. */
12615 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12616 it isn't going to be useful and will take a lot of time to process,
12617 so just use the CLOBBER. */
12620 {
12626 {
12627 /* If there are two or more occurrences of REG in VALUE,
12628 prevent the value from growing too much. */
12631 }
12634 }
12635 }
12637 /* For each register modified, show we don't know its value, that
12638 we don't know about its bitwise content, that its value has been
12639 updated, and that we don't know the location of the death of the
12640 register. */
12642 {
12654 }
12656 /* Mark registers that are being referenced in this value. */
12660 /* Now update the status of each register being set.
12661 If someone is using this register in this block, set this register
12662 to invalid since we will get confused between the two lives in this
12663 basic block. This makes using this register always invalid. In cse, we
12664 scan the table to invalidate all entries using this register, but this
12665 is too much work for us. */
12668 {
12674 else
12676 }
12678 /* The value being assigned might refer to X (like in "x++;"). In that
12679 case, we must replace it with (clobber (const_int 0)) to prevent
12680 infinite loops. */
12683 {
12687 }
12689 /* For the main register being modified, update the value, the mode, the
12690 nonzero bits, and the number of sign bit copies. */
12695 {
12703 rsp->last_set_sign_bit_copies
12705 }
12706 }
12708 /* Called via note_stores from record_dead_and_set_regs to handle one
12709 SET or CLOBBER in an insn. DATA is the instruction in which the
12710 set is occurring. */
12712 static void
12714 {
12721 {
12725 }
12728 {
12729 /* If we are setting the whole register, we know its value. Otherwise
12730 show that we don't know the value. We can handle SUBREG in
12731 some cases. */
12742 else
12744 }
12746 /* Ignore pushes, they clobber nothing. */
12749 }
12751 /* Update the records of when each REG was most recently set or killed
12752 for the things done by INSN. This is the last thing done in processing
12753 INSN in the combiner loop.
12755 We update reg_stat[], in particular fields last_set, last_set_value,
12756 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12757 last_death, and also the similar information mem_last_set (which insn
12758 most recently modified memory) and last_call_luid (which insn was the
12759 most recent subroutine call). */
12761 static void
12763 {
12764 rtx link;
12768 {
12771 {
12776 {
12781 }
12782 }
12785 }
12788 {
12789 hard_reg_set_iterator hrsi;
12791 {
12803 }
12807 /* We can't combine into a call pattern. Remember, though, that
12808 the return value register is set at this LUID. We could
12809 still replace a register with the return value from the
12810 wrong subroutine call! */
12812 }
12813 else
12815 }
12817 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12818 register present in the SUBREG, so for each such SUBREG go back and
12819 adjust nonzero and sign bit information of the registers that are
12820 known to have some zero/sign bits set.
12822 This is needed because when combine blows the SUBREGs away, the
12823 information on zero/sign bits is lost and further combines can be
12824 missed because of that. */
12826 static void
12828 {
12830 rtx set;
12838 {
12847 {
12850 }
12854 {
12857 }
12860 {
12863 }
12864 else
12866 }
12867 }
12869 /* Check if X, a register, is known to contain a value already
12870 truncated to MODE. In this case we can use a subreg to refer to
12871 the truncated value even though in the generic case we would need
12872 an explicit truncation. */
12874 static bool
12876 {
12888 }
12890 /* If X is a hard reg or a subreg record the mode that the register is
12891 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12892 to turn a truncate into a subreg using this information. Return true
12893 if traversing X is complete. */
12895 static bool
12897 {
12898 machine_mode truncated_mode;
12902 {
12913 }
12914 /* ??? For hard-regs we now record everything. We might be able to
12915 optimize this using last_set_mode. */
12918 else
12926 {
12929 }
12932 }
12934 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12935 the modes they are used in. This can help truning TRUNCATEs into
12936 SUBREGs. */
12938 static void
12940 {
12945 }
12947 /* Scan X for promoted SUBREGs. For each one found,
12948 note what it implies to the registers used in it. */
12950 static void
12952 {
12957 else
12958 {
12964 {
12974 }
12975 }
12976 }
12977 \f
12978 /* Verify that all the registers and memory references mentioned in *LOC are
12979 still valid. *LOC was part of a value set in INSN when label_tick was
12980 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12981 the invalid references with (clobber (const_int 0)) and return 1. This
12982 replacement is useful because we often can get useful information about
12983 the form of a value (e.g., if it was produced by a shift that always
12984 produces -1 or 0) even though we don't know exactly what registers it
12985 was produced from. */
12987 static int
12989 {
12996 {
13002 {
13005 /* If this is a pseudo-register that was only set once and not
13006 live at the beginning of the function, it is always valid. */
13010 && (!REGNO_REG_SET_P
13012 regno)))
13014 {
13018 }
13019 }
13022 }
13023 /* If this is a memory reference, make sure that there were no stores after
13024 it that might have clobbered the value. We don't have alias info, so we
13025 assume any store invalidates it. Moreover, we only have local UIDs, so
13026 we also assume that there were stores in the intervening basic blocks. */
13029 {
13033 }
13036 {
13038 {
13039 /* Check for identical subexpressions. If x contains
13040 identical subexpression we only have to traverse one of
13041 them. */
13043 {
13044 /* Note that at this point x0 has already been checked
13045 and found valid. */
13049 /* If x0 and x1 are identical then x is also valid. */
13053 /* If x1 is identical to a subexpression of x0 then
13054 while checking x0, x1 has already been checked. Thus
13055 it is valid and so as x. */
13060 /* If x0 is identical to a subexpression of x1 then x is
13061 valid iff the rest of x1 is valid. */
13064 return
13068 }
13073 }
13079 }
13081 /* If we haven't found a reason for it to be invalid, it is valid. */
13083 }
13085 /* Get the last value assigned to X, if known. Some registers
13086 in the value may be replaced with (clobber (const_int 0)) if their value
13087 is known longer known reliably. */
13089 static rtx
13091 {
13093 rtx value;
13096 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13097 then convert it to the desired mode. If this is a paradoxical SUBREG,
13098 we cannot predict what values the "extra" bits might have. */
13112 /* If we don't have a value, or if it isn't for this basic block and
13113 it's either a hard register, set more than once, or it's a live
13114 at the beginning of the function, return 0.
13116 Because if it's not live at the beginning of the function then the reg
13117 is always set before being used (is never used without being set).
13118 And, if it's set only once, and it's always set before use, then all
13119 uses must have the same last value, even if it's not from this basic
13120 block. */
13127 || REGNO_REG_SET_P
13131 /* If the value was set in a later insn than the ones we are processing,
13132 we can't use it even if the register was only set once. */
13137 /* If the value has all its registers valid, return it. */
13141 /* Otherwise, make a copy and replace any invalid register with
13142 (clobber (const_int 0)). If that fails for some reason, return 0. */
13149 }
13150 \f
13151 /* Return nonzero if expression X refers to a REG or to memory
13152 that is set in an instruction more recent than FROM_LUID. */
13154 static int
13156 {
13162 {
13166 #ifdef PUSH_ROUNDING
13167 /* Don't allow uses of the stack pointer to be moved,
13168 because we don't know whether the move crosses a push insn. */
13171 #endif
13173 {
13179 }
13181 }
13189 {
13191 {
13196 }
13200 }
13202 }
13203 \f
13204 /* Define three variables used for communication between the following
13205 routines. */
13210 /* Function called via note_stores from reg_dead_at_p.
13212 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13213 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13215 static void
13217 {
13227 }
13229 /* Return nonzero if REG is known to be dead at INSN.
13231 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13232 referencing REG, it is dead. If we hit a SET referencing REG, it is
13233 live. Otherwise, see if it is live or dead at the start of the basic
13234 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13235 must be assumed to be always live. */
13237 static int
13239 {
13240 basic_block block;
13243 /* Set variables for reg_dead_at_p_1. */
13249 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13250 we allow the machine description to decide whether use-and-clobber
13251 patterns are OK. */
13253 {
13257 }
13259 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13260 beginning of basic block. */
13263 {
13265 {
13275 }
13281 }
13283 /* Look at live-in sets for the basic block that we were in. */
13289 }
13290 \f
13291 /* Note hard registers in X that are used. */
13293 static void
13295 {
13301 {
13305 CASE_CONST_ANY:
13310 /* CC0 must die in the insn after it is set, so we don't need to take
13311 special note of it here. */
13316 /* If we are clobbering a MEM, mark any hard registers inside the
13317 address as used. */
13324 /* A hard reg in a wide mode may really be multiple registers.
13325 If so, mark all of them just like the first. */
13327 {
13328 /* None of this applies to the stack, frame or arg pointers. */
13330 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13338 }
13342 {
13343 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13344 the address. */
13356 }
13361 }
13363 /* Recursively scan the operands of this expression. */
13365 {
13369 {
13373 {
13378 }
13379 }
13380 }
13381 }
13382 \f
13383 /* Remove register number REGNO from the dead registers list of INSN.
13385 Return the note used to record the death, if there was one. */
13387 rtx
13389 {
13396 }
13398 /* For each register (hardware or pseudo) used within expression X, if its
13399 death is in an instruction with luid between FROM_LUID (inclusive) and
13400 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13401 list headed by PNOTES.
13403 That said, don't move registers killed by maybe_kill_insn.
13405 This is done when X is being merged by combination into TO_INSN. These
13406 notes will then be distributed as needed. */
13408 static void
13411 {
13417 {
13421 /* Don't move the register if it gets killed in between from and to. */
13430 {
13433 /* It is possible for the call above to return 0. This can occur
13434 when last_death points to I2 or I1 that we combined with.
13435 In that case make a new note.
13437 We must also check for the case where X is a hard register
13438 and NOTE is a death note for a range of hard registers
13439 including X. In that case, we must put REG_DEAD notes for
13440 the remaining registers in place of NOTE. */
13445 {
13454 }
13456 /* If we didn't find any note, or if we found a REG_DEAD note that
13457 covers only part of the given reg, and we have a multi-reg hard
13458 register, then to be safe we must check for REG_DEAD notes
13459 for each register other than the first. They could have
13460 their own REG_DEAD notes lying around. */
13467 {
13474 else
13480 }
13483 {
13486 }
13487 else
13489 }
13492 }
13495 {
13500 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13501 that accesses one word of a multi-word item, some
13502 piece of everything register in the expression is used by
13503 this insn, so remove any old death. */
13504 /* ??? So why do we test for equality of the sizes? */
13513 {
13516 }
13518 /* If this is some other SUBREG, we know it replaces the entire
13519 value, so use that as the destination. */
13523 /* If this is a MEM, adjust deaths of anything used in the address.
13524 For a REG (the only other possibility), the entire value is
13525 being replaced so the old value is not used in this insn. */
13531 }
13540 {
13542 {
13547 }
13550 }
13551 }
13552 \f
13553 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13554 pattern of an insn. X must be a REG. */
13556 static int
13558 {
13562 {
13564 rtx target;
13571 else
13588 }
13596 }
13597 \f
13598 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13599 as appropriate. I3 and I2 are the insns resulting from the combination
13600 insns including FROM (I2 may be zero).
13602 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13603 not need REG_DEAD notes because they are being substituted for. This
13604 saves searching in the most common cases.
13606 Each note in the list is either ignored or placed on some insns, depending
13607 on the type of note. */
13609 static void
13612 {
13614 rtx tem_note;
13618 {
13623 {
13626 /* Doesn't matter much where we put this, as long as it's somewhere.
13627 It is preferable to keep these notes on branches, which is most
13628 likely to be i3. */
13635 else
13636 {
13639 }
13643 /* These notes must remain with the call or trapping instruction. */
13648 else
13649 {
13655 /* ??? Otherwise assume we've combined things such that we
13656 can now prove that the instructions can't trap. Drop the
13657 note in this case. */
13658 }
13662 /* ??? How to distribute between i3-i1. Assume i3 contains the
13663 entire adjustment. Assert i3 contains at least some adjust. */
13665 {
13667 /* fixup_args_size_notes looks at REG_NORETURN note,
13668 so ensure the note is placed there first. */
13670 {
13674 {
13680 }
13681 }
13683 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13684 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13687 && !ACCUMULATE_OUTGOING_ARGS
13689 }
13696 /* These notes must remain with the call. It should not be
13697 possible for both I2 and I3 to be a call. */
13700 else
13701 {
13704 }
13708 /* Any clobbers for i3 may still exist, and so we must process
13709 REG_UNUSED notes from that insn.
13711 Any clobbers from i2 or i1 can only exist if they were added by
13712 recog_for_combine. In that case, recog_for_combine created the
13713 necessary REG_UNUSED notes. Trying to keep any original
13714 REG_UNUSED notes from these insns can cause incorrect output
13715 if it is for the same register as the original i3 dest.
13716 In that case, we will notice that the register is set in i3,
13717 and then add a REG_UNUSED note for the destination of i3, which
13718 is wrong. However, it is possible to have REG_UNUSED notes from
13719 i2 or i1 for register which were both used and clobbered, so
13720 we keep notes from i2 or i1 if they will turn into REG_DEAD
13721 notes. */
13723 /* If this register is set or clobbered in I3, put the note there
13724 unless there is one already. */
13726 {
13734 }
13735 /* Otherwise, if this register is used by I3, then this register
13736 now dies here, so we must put a REG_DEAD note here unless there
13737 is one already. */
13743 {
13746 }
13752 /* These notes say something about results of an insn. We can
13753 only support them if they used to be on I3 in which case they
13754 remain on I3. Otherwise they are ignored.
13756 If the note refers to an expression that is not a constant, we
13757 must also ignore the note since we cannot tell whether the
13758 equivalence is still true. It might be possible to do
13759 slightly better than this (we only have a problem if I2DEST
13760 or I1DEST is present in the expression), but it doesn't
13761 seem worth the trouble. */
13769 /* These notes say something about how a register is used. They must
13770 be present on any use of the register in I2 or I3. */
13775 {
13778 else
13780 }
13785 /* This can show up in several ways -- either directly in the
13786 pattern, or hidden off in the constant pool with (or without?)
13787 a REG_EQUAL note. */
13788 /* ??? Ignore the without-reg_equal-note problem for now. */
13800 {
13803 else
13805 }
13807 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13808 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13809 there. */
13814 {
13821 }
13827 {
13835 }
13839 /* This note says something about the value of a register prior
13840 to the execution of an insn. It is too much trouble to see
13841 if the note is still correct in all situations. It is better
13842 to simply delete it. */
13846 /* If we replaced the right hand side of FROM_INSN with a
13847 REG_EQUAL note, the original use of the dying register
13848 will not have been combined into I3 and I2. In such cases,
13849 FROM_INSN is guaranteed to be the first of the combined
13850 instructions, so we simply need to search back before
13851 FROM_INSN for the previous use or set of this register,
13852 then alter the notes there appropriately.
13854 If the register is used as an input in I3, it dies there.
13855 Similarly for I2, if it is nonzero and adjacent to I3.
13857 If the register is not used as an input in either I3 or I2
13858 and it is not one of the registers we were supposed to eliminate,
13859 there are two possibilities. We might have a non-adjacent I2
13860 or we might have somehow eliminated an additional register
13861 from a computation. For example, we might have had A & B where
13862 we discover that B will always be zero. In this case we will
13863 eliminate the reference to A.
13865 In both cases, we must search to see if we can find a previous
13866 use of A and put the death note there. */
13872 else
13873 {
13884 && !(i2mod
13886 i2mod_old_rhs)))
13891 /* If the new I2 sets the same register that is marked dead
13892 in the note, the note now should not be put on I2, as the
13893 note refers to a previous incarnation of the reg. */
13896 }
13899 {
13903 {
13905 {
13909 }
13911 /* If the register is being set at TEM_INSN, see if that is all
13912 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13913 into a REG_UNUSED note instead. Don't delete sets to
13914 global register vars. */
13918 {
13929 ;
13931 /* Verify that it was the set, and not a clobber that
13932 modified the register.
13934 CC0 targets must be careful to maintain setter/user
13935 pairs. If we cannot delete the setter due to side
13936 effects, mark the user with an UNUSED note instead
13937 of deleting it. */
13941 && (!HAVE_cc0
13945 {
13946 /* Move the notes and links of TEM_INSN elsewhere.
13947 This might delete other dead insns recursively.
13948 First set the pattern to something that won't use
13949 any register. */
13963 /* Delete the setter too. */
13965 {
13978 }
13979 }
13980 else
13981 {
13984 /* If there isn't already a REG_UNUSED note, put one
13985 here. Do not place a REG_DEAD note, even if
13986 the register is also used here; that would not
13987 match the algorithm used in lifetime analysis
13988 and can cause the consistency check in the
13989 scheduler to fail. */
13994 }
13995 }
13999 {
14002 /* If we are doing a 3->2 combination, and we have a
14003 register which formerly died in i3 and was not used
14004 by i2, which now no longer dies in i3 and is used in
14005 i2 but does not die in i2, and place is between i2
14006 and i3, then we may need to move a link from place to
14007 i2. */
14009 && from_insn
14012 {
14016 }
14018 }
14022 }
14024 }
14026 /* If the register is set or already dead at PLACE, we needn't do
14027 anything with this note if it is still a REG_DEAD note.
14028 We check here if it is set at all, not if is it totally replaced,
14029 which is what `dead_or_set_p' checks, so also check for it being
14030 set partially. */
14033 {
14039 {
14040 /* Unless the register previously died in PLACE, clear
14041 last_death. [I no longer understand why this is
14042 being done.] */
14046 }
14047 else
14050 /* If this is a death note for a hard reg that is occupying
14051 multiple registers, ensure that we are still using all
14052 parts of the object. If we find a piece of the object
14053 that is unused, we must arrange for an appropriate REG_DEAD
14054 note to be added for it. However, we can't just emit a USE
14055 and tag the note to it, since the register might actually
14056 be dead; so we recourse, and the recursive call then finds
14057 the previous insn that used this register. */
14060 {
14069 {
14072 }
14075 {
14076 /* Put only REG_DEAD notes for pieces that are
14077 not already dead or set. */
14081 {
14088 {
14090 NULL_RTX);
14094 NULL_RTX);
14095 }
14100 {
14102 {
14106 }
14110 {
14113 }
14114 }
14115 }
14118 }
14119 }
14120 }
14124 /* Any other notes should not be present at this point in the
14125 compilation. */
14127 }
14130 {
14133 }
14137 }
14138 }
14139 \f
14140 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14141 I3, I2, and I1 to new locations. This is also called to add a link
14142 pointing at I3 when I3's destination is changed. */
14144 static void
14146 {
14150 {
14157 /* If the insn that this link points to is a NOTE, ignore it. */
14166 {
14169 {
14185 }
14188 }
14189 else
14199 /* A LOG_LINK is defined as being placed on the first insn that uses
14200 a register and points to the insn that sets the register. Start
14201 searching at the next insn after the target of the link and stop
14202 when we reach a set of the register or the end of the basic block.
14204 Note that this correctly handles the link that used to point from
14205 I3 to I2. Also note that not much searching is typically done here
14206 since most links don't point very far away. */
14215 {
14219 }
14222 {
14225 }
14229 /* If we found a place to put the link, place it there unless there
14230 is already a link to the same insn as LINK at that point. */
14233 {
14241 {
14245 /* Set added_links_insn to the earliest insn we added a
14246 link to. */
14250 }
14251 }
14252 }
14253 }
14254 \f
14255 /* Check for any register or memory mentioned in EQUIV that is not
14256 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14257 of EXPR where some registers may have been replaced by constants. */
14259 static bool
14261 {
14264 {
14269 }
14271 }
14272 \f
14273 DEBUG_FUNCTION void
14275 {
14276 fprintf
14278 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14280 }
14282 void
14284 {
14285 fprintf
14287 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14289 }
14290 \f
14291 /* Try combining insns through substitution. */
14292 static unsigned int
14294 {
14304 rebuild_jump_labels_after_combine
14307 /* Combining insns may have turned an indirect jump into a
14308 direct jump. Rebuild the JUMP_LABEL fields of jumping
14309 instructions. */
14311 {
14316 }
14320 }
14325 {
14335 };
14338 {
14342 {}
14344 /* opt_pass methods: */
14347 {
14349 }
14355 rtl_opt_pass *
14357 {
14359 }