1 /* Expand the basic unary and binary arithmetic operations, for GNU compiler.
2 Copyright (C) 1987-2018 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
35 #include "diagnostic-core.h"
36 #include "rtx-vector-builder.h"
38 /* Include insn-config.h before expr.h so that HAVE_conditional_move
39 is properly defined. */
40 #include "stor-layout.h"
45 #include "optabs-tree.h"
48 static void prepare_float_lib_cmp (rtx
, rtx
, enum rtx_code
, rtx
*,
50 static rtx
expand_unop_direct (machine_mode
, optab
, rtx
, rtx
, int);
51 static void emit_libcall_block_1 (rtx_insn
*, rtx
, rtx
, rtx
, bool);
53 /* Debug facility for use in GDB. */
54 void debug_optab_libfuncs (void);
56 /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to
57 the result of operation CODE applied to OP0 (and OP1 if it is a binary
60 If the last insn does not set TARGET, don't do anything, but return 1.
62 If the last insn or a previous insn sets TARGET and TARGET is one of OP0
63 or OP1, don't add the REG_EQUAL note but return 0. Our caller can then
64 try again, ensuring that TARGET is not one of the operands. */
67 add_equal_note (rtx_insn
*insns
, rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
73 gcc_assert (insns
&& INSN_P (insns
) && NEXT_INSN (insns
));
75 if (GET_RTX_CLASS (code
) != RTX_COMM_ARITH
76 && GET_RTX_CLASS (code
) != RTX_BIN_ARITH
77 && GET_RTX_CLASS (code
) != RTX_COMM_COMPARE
78 && GET_RTX_CLASS (code
) != RTX_COMPARE
79 && GET_RTX_CLASS (code
) != RTX_UNARY
)
82 if (GET_CODE (target
) == ZERO_EXTRACT
)
85 for (last_insn
= insns
;
86 NEXT_INSN (last_insn
) != NULL_RTX
;
87 last_insn
= NEXT_INSN (last_insn
))
90 /* If TARGET is in OP0 or OP1, punt. We'd end up with a note referencing
91 a value changing in the insn, so the note would be invalid for CSE. */
92 if (reg_overlap_mentioned_p (target
, op0
)
93 || (op1
&& reg_overlap_mentioned_p (target
, op1
)))
96 && (rtx_equal_p (target
, op0
)
97 || (op1
&& rtx_equal_p (target
, op1
))))
99 /* For MEM target, with MEM = MEM op X, prefer no REG_EQUAL note
100 over expanding it as temp = MEM op X, MEM = temp. If the target
101 supports MEM = MEM op X instructions, it is sometimes too hard
102 to reconstruct that form later, especially if X is also a memory,
103 and due to multiple occurrences of addresses the address might
104 be forced into register unnecessarily.
105 Note that not emitting the REG_EQUIV note might inhibit
106 CSE in some cases. */
107 set
= single_set (last_insn
);
109 && GET_CODE (SET_SRC (set
)) == code
110 && MEM_P (SET_DEST (set
))
111 && (rtx_equal_p (SET_DEST (set
), XEXP (SET_SRC (set
), 0))
112 || (op1
&& rtx_equal_p (SET_DEST (set
),
113 XEXP (SET_SRC (set
), 1)))))
119 set
= set_for_reg_notes (last_insn
);
123 if (! rtx_equal_p (SET_DEST (set
), target
)
124 /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */
125 && (GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
126 || ! rtx_equal_p (XEXP (SET_DEST (set
), 0), target
)))
129 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
139 if (GET_MODE (op0
) != VOIDmode
&& GET_MODE (target
) != GET_MODE (op0
))
141 note
= gen_rtx_fmt_e (code
, GET_MODE (op0
), copy_rtx (op0
));
142 if (GET_MODE_UNIT_SIZE (GET_MODE (op0
))
143 > GET_MODE_UNIT_SIZE (GET_MODE (target
)))
144 note
= simplify_gen_unary (TRUNCATE
, GET_MODE (target
),
145 note
, GET_MODE (op0
));
147 note
= simplify_gen_unary (ZERO_EXTEND
, GET_MODE (target
),
148 note
, GET_MODE (op0
));
153 note
= gen_rtx_fmt_e (code
, GET_MODE (target
), copy_rtx (op0
));
157 note
= gen_rtx_fmt_ee (code
, GET_MODE (target
), copy_rtx (op0
), copy_rtx (op1
));
159 set_unique_reg_note (last_insn
, REG_EQUAL
, note
);
164 /* Given two input operands, OP0 and OP1, determine what the correct from_mode
165 for a widening operation would be. In most cases this would be OP0, but if
166 that's a constant it'll be VOIDmode, which isn't useful. */
169 widened_mode (machine_mode to_mode
, rtx op0
, rtx op1
)
171 machine_mode m0
= GET_MODE (op0
);
172 machine_mode m1
= GET_MODE (op1
);
175 if (m0
== VOIDmode
&& m1
== VOIDmode
)
177 else if (m0
== VOIDmode
|| GET_MODE_UNIT_SIZE (m0
) < GET_MODE_UNIT_SIZE (m1
))
182 if (GET_MODE_UNIT_SIZE (result
) > GET_MODE_UNIT_SIZE (to_mode
))
188 /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP
189 says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need
190 not actually do a sign-extend or zero-extend, but can leave the
191 higher-order bits of the result rtx undefined, for example, in the case
192 of logical operations, but not right shifts. */
195 widen_operand (rtx op
, machine_mode mode
, machine_mode oldmode
,
196 int unsignedp
, int no_extend
)
199 scalar_int_mode int_mode
;
201 /* If we don't have to extend and this is a constant, return it. */
202 if (no_extend
&& GET_MODE (op
) == VOIDmode
)
205 /* If we must extend do so. If OP is a SUBREG for a promoted object, also
206 extend since it will be more efficient to do so unless the signedness of
207 a promoted object differs from our extension. */
209 || !is_a
<scalar_int_mode
> (mode
, &int_mode
)
210 || (GET_CODE (op
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (op
)
211 && SUBREG_CHECK_PROMOTED_SIGN (op
, unsignedp
)))
212 return convert_modes (mode
, oldmode
, op
, unsignedp
);
214 /* If MODE is no wider than a single word, we return a lowpart or paradoxical
216 if (GET_MODE_SIZE (int_mode
) <= UNITS_PER_WORD
)
217 return gen_lowpart (int_mode
, force_reg (GET_MODE (op
), op
));
219 /* Otherwise, get an object of MODE, clobber it, and set the low-order
222 result
= gen_reg_rtx (int_mode
);
223 emit_clobber (result
);
224 emit_move_insn (gen_lowpart (GET_MODE (op
), result
), op
);
228 /* Expand vector widening operations.
230 There are two different classes of operations handled here:
231 1) Operations whose result is wider than all the arguments to the operation.
232 Examples: VEC_UNPACK_HI/LO_EXPR, VEC_WIDEN_MULT_HI/LO_EXPR
233 In this case OP0 and optionally OP1 would be initialized,
234 but WIDE_OP wouldn't (not relevant for this case).
235 2) Operations whose result is of the same size as the last argument to the
236 operation, but wider than all the other arguments to the operation.
237 Examples: WIDEN_SUM_EXPR, VEC_DOT_PROD_EXPR.
238 In the case WIDE_OP, OP0 and optionally OP1 would be initialized.
240 E.g, when called to expand the following operations, this is how
241 the arguments will be initialized:
243 widening-sum 2 oprnd0 - oprnd1
244 widening-dot-product 3 oprnd0 oprnd1 oprnd2
245 widening-mult 2 oprnd0 oprnd1 -
246 type-promotion (vec-unpack) 1 oprnd0 - - */
249 expand_widen_pattern_expr (sepops ops
, rtx op0
, rtx op1
, rtx wide_op
,
250 rtx target
, int unsignedp
)
252 struct expand_operand eops
[4];
253 tree oprnd0
, oprnd1
, oprnd2
;
254 machine_mode wmode
= VOIDmode
, tmode0
, tmode1
= VOIDmode
;
255 optab widen_pattern_optab
;
256 enum insn_code icode
;
257 int nops
= TREE_CODE_LENGTH (ops
->code
);
261 tmode0
= TYPE_MODE (TREE_TYPE (oprnd0
));
262 if (ops
->code
== VEC_UNPACK_FIX_TRUNC_HI_EXPR
263 || ops
->code
== VEC_UNPACK_FIX_TRUNC_LO_EXPR
)
264 /* The sign is from the result type rather than operand's type
267 = optab_for_tree_code (ops
->code
, ops
->type
, optab_default
);
270 = optab_for_tree_code (ops
->code
, TREE_TYPE (oprnd0
), optab_default
);
271 if (ops
->code
== WIDEN_MULT_PLUS_EXPR
272 || ops
->code
== WIDEN_MULT_MINUS_EXPR
)
273 icode
= find_widening_optab_handler (widen_pattern_optab
,
274 TYPE_MODE (TREE_TYPE (ops
->op2
)),
277 icode
= optab_handler (widen_pattern_optab
, tmode0
);
278 gcc_assert (icode
!= CODE_FOR_nothing
);
283 tmode1
= TYPE_MODE (TREE_TYPE (oprnd1
));
286 /* The last operand is of a wider mode than the rest of the operands. */
291 gcc_assert (tmode1
== tmode0
);
294 wmode
= TYPE_MODE (TREE_TYPE (oprnd2
));
298 create_output_operand (&eops
[op
++], target
, TYPE_MODE (ops
->type
));
299 create_convert_operand_from (&eops
[op
++], op0
, tmode0
, unsignedp
);
301 create_convert_operand_from (&eops
[op
++], op1
, tmode1
, unsignedp
);
303 create_convert_operand_from (&eops
[op
++], wide_op
, wmode
, unsignedp
);
304 expand_insn (icode
, op
, eops
);
305 return eops
[0].value
;
308 /* Generate code to perform an operation specified by TERNARY_OPTAB
309 on operands OP0, OP1 and OP2, with result having machine-mode MODE.
311 UNSIGNEDP is for the case where we have to widen the operands
312 to perform the operation. It says to use zero-extension.
314 If TARGET is nonzero, the value
315 is generated there, if it is convenient to do so.
316 In all cases an rtx is returned for the locus of the value;
317 this may or may not be TARGET. */
320 expand_ternary_op (machine_mode mode
, optab ternary_optab
, rtx op0
,
321 rtx op1
, rtx op2
, rtx target
, int unsignedp
)
323 struct expand_operand ops
[4];
324 enum insn_code icode
= optab_handler (ternary_optab
, mode
);
326 gcc_assert (optab_handler (ternary_optab
, mode
) != CODE_FOR_nothing
);
328 create_output_operand (&ops
[0], target
, mode
);
329 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
330 create_convert_operand_from (&ops
[2], op1
, mode
, unsignedp
);
331 create_convert_operand_from (&ops
[3], op2
, mode
, unsignedp
);
332 expand_insn (icode
, 4, ops
);
337 /* Like expand_binop, but return a constant rtx if the result can be
338 calculated at compile time. The arguments and return value are
339 otherwise the same as for expand_binop. */
342 simplify_expand_binop (machine_mode mode
, optab binoptab
,
343 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
344 enum optab_methods methods
)
346 if (CONSTANT_P (op0
) && CONSTANT_P (op1
))
348 rtx x
= simplify_binary_operation (optab_to_code (binoptab
),
354 return expand_binop (mode
, binoptab
, op0
, op1
, target
, unsignedp
, methods
);
357 /* Like simplify_expand_binop, but always put the result in TARGET.
358 Return true if the expansion succeeded. */
361 force_expand_binop (machine_mode mode
, optab binoptab
,
362 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
363 enum optab_methods methods
)
365 rtx x
= simplify_expand_binop (mode
, binoptab
, op0
, op1
,
366 target
, unsignedp
, methods
);
370 emit_move_insn (target
, x
);
374 /* Create a new vector value in VMODE with all elements set to OP. The
375 mode of OP must be the element mode of VMODE. If OP is a constant,
376 then the return value will be a constant. */
379 expand_vector_broadcast (machine_mode vmode
, rtx op
)
384 gcc_checking_assert (VECTOR_MODE_P (vmode
));
386 if (valid_for_const_vector_p (vmode
, op
))
387 return gen_const_vec_duplicate (vmode
, op
);
389 insn_code icode
= optab_handler (vec_duplicate_optab
, vmode
);
390 if (icode
!= CODE_FOR_nothing
)
392 struct expand_operand ops
[2];
393 create_output_operand (&ops
[0], NULL_RTX
, vmode
);
394 create_input_operand (&ops
[1], op
, GET_MODE (op
));
395 expand_insn (icode
, 2, ops
);
399 if (!GET_MODE_NUNITS (vmode
).is_constant (&n
))
402 /* ??? If the target doesn't have a vec_init, then we have no easy way
403 of performing this operation. Most of this sort of generic support
404 is hidden away in the vector lowering support in gimple. */
405 icode
= convert_optab_handler (vec_init_optab
, vmode
,
406 GET_MODE_INNER (vmode
));
407 if (icode
== CODE_FOR_nothing
)
410 vec
= rtvec_alloc (n
);
411 for (int i
= 0; i
< n
; ++i
)
412 RTVEC_ELT (vec
, i
) = op
;
413 rtx ret
= gen_reg_rtx (vmode
);
414 emit_insn (GEN_FCN (icode
) (ret
, gen_rtx_PARALLEL (vmode
, vec
)));
419 /* This subroutine of expand_doubleword_shift handles the cases in which
420 the effective shift value is >= BITS_PER_WORD. The arguments and return
421 value are the same as for the parent routine, except that SUPERWORD_OP1
422 is the shift count to use when shifting OUTOF_INPUT into INTO_TARGET.
423 INTO_TARGET may be null if the caller has decided to calculate it. */
426 expand_superword_shift (optab binoptab
, rtx outof_input
, rtx superword_op1
,
427 rtx outof_target
, rtx into_target
,
428 int unsignedp
, enum optab_methods methods
)
430 if (into_target
!= 0)
431 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, superword_op1
,
432 into_target
, unsignedp
, methods
))
435 if (outof_target
!= 0)
437 /* For a signed right shift, we must fill OUTOF_TARGET with copies
438 of the sign bit, otherwise we must fill it with zeros. */
439 if (binoptab
!= ashr_optab
)
440 emit_move_insn (outof_target
, CONST0_RTX (word_mode
));
442 if (!force_expand_binop (word_mode
, binoptab
, outof_input
,
443 gen_int_shift_amount (word_mode
,
445 outof_target
, unsignedp
, methods
))
451 /* This subroutine of expand_doubleword_shift handles the cases in which
452 the effective shift value is < BITS_PER_WORD. The arguments and return
453 value are the same as for the parent routine. */
456 expand_subword_shift (scalar_int_mode op1_mode
, optab binoptab
,
457 rtx outof_input
, rtx into_input
, rtx op1
,
458 rtx outof_target
, rtx into_target
,
459 int unsignedp
, enum optab_methods methods
,
460 unsigned HOST_WIDE_INT shift_mask
)
462 optab reverse_unsigned_shift
, unsigned_shift
;
465 reverse_unsigned_shift
= (binoptab
== ashl_optab
? lshr_optab
: ashl_optab
);
466 unsigned_shift
= (binoptab
== ashl_optab
? ashl_optab
: lshr_optab
);
468 /* The low OP1 bits of INTO_TARGET come from the high bits of OUTOF_INPUT.
469 We therefore need to shift OUTOF_INPUT by (BITS_PER_WORD - OP1) bits in
470 the opposite direction to BINOPTAB. */
471 if (CONSTANT_P (op1
) || shift_mask
>= BITS_PER_WORD
)
473 carries
= outof_input
;
474 tmp
= immed_wide_int_const (wi::shwi (BITS_PER_WORD
,
475 op1_mode
), op1_mode
);
476 tmp
= simplify_expand_binop (op1_mode
, sub_optab
, tmp
, op1
,
481 /* We must avoid shifting by BITS_PER_WORD bits since that is either
482 the same as a zero shift (if shift_mask == BITS_PER_WORD - 1) or
483 has unknown behavior. Do a single shift first, then shift by the
484 remainder. It's OK to use ~OP1 as the remainder if shift counts
485 are truncated to the mode size. */
486 carries
= expand_binop (word_mode
, reverse_unsigned_shift
,
487 outof_input
, const1_rtx
, 0, unsignedp
, methods
);
488 if (shift_mask
== BITS_PER_WORD
- 1)
490 tmp
= immed_wide_int_const
491 (wi::minus_one (GET_MODE_PRECISION (op1_mode
)), op1_mode
);
492 tmp
= simplify_expand_binop (op1_mode
, xor_optab
, op1
, tmp
,
497 tmp
= immed_wide_int_const (wi::shwi (BITS_PER_WORD
- 1,
498 op1_mode
), op1_mode
);
499 tmp
= simplify_expand_binop (op1_mode
, sub_optab
, tmp
, op1
,
503 if (tmp
== 0 || carries
== 0)
505 carries
= expand_binop (word_mode
, reverse_unsigned_shift
,
506 carries
, tmp
, 0, unsignedp
, methods
);
510 /* Shift INTO_INPUT logically by OP1. This is the last use of INTO_INPUT
511 so the result can go directly into INTO_TARGET if convenient. */
512 tmp
= expand_binop (word_mode
, unsigned_shift
, into_input
, op1
,
513 into_target
, unsignedp
, methods
);
517 /* Now OR in the bits carried over from OUTOF_INPUT. */
518 if (!force_expand_binop (word_mode
, ior_optab
, tmp
, carries
,
519 into_target
, unsignedp
, methods
))
522 /* Use a standard word_mode shift for the out-of half. */
523 if (outof_target
!= 0)
524 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, op1
,
525 outof_target
, unsignedp
, methods
))
532 /* Try implementing expand_doubleword_shift using conditional moves.
533 The shift is by < BITS_PER_WORD if (CMP_CODE CMP1 CMP2) is true,
534 otherwise it is by >= BITS_PER_WORD. SUBWORD_OP1 and SUPERWORD_OP1
535 are the shift counts to use in the former and latter case. All other
536 arguments are the same as the parent routine. */
539 expand_doubleword_shift_condmove (scalar_int_mode op1_mode
, optab binoptab
,
540 enum rtx_code cmp_code
, rtx cmp1
, rtx cmp2
,
541 rtx outof_input
, rtx into_input
,
542 rtx subword_op1
, rtx superword_op1
,
543 rtx outof_target
, rtx into_target
,
544 int unsignedp
, enum optab_methods methods
,
545 unsigned HOST_WIDE_INT shift_mask
)
547 rtx outof_superword
, into_superword
;
549 /* Put the superword version of the output into OUTOF_SUPERWORD and
551 outof_superword
= outof_target
!= 0 ? gen_reg_rtx (word_mode
) : 0;
552 if (outof_target
!= 0 && subword_op1
== superword_op1
)
554 /* The value INTO_TARGET >> SUBWORD_OP1, which we later store in
555 OUTOF_TARGET, is the same as the value of INTO_SUPERWORD. */
556 into_superword
= outof_target
;
557 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
558 outof_superword
, 0, unsignedp
, methods
))
563 into_superword
= gen_reg_rtx (word_mode
);
564 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
565 outof_superword
, into_superword
,
570 /* Put the subword version directly in OUTOF_TARGET and INTO_TARGET. */
571 if (!expand_subword_shift (op1_mode
, binoptab
,
572 outof_input
, into_input
, subword_op1
,
573 outof_target
, into_target
,
574 unsignedp
, methods
, shift_mask
))
577 /* Select between them. Do the INTO half first because INTO_SUPERWORD
578 might be the current value of OUTOF_TARGET. */
579 if (!emit_conditional_move (into_target
, cmp_code
, cmp1
, cmp2
, op1_mode
,
580 into_target
, into_superword
, word_mode
, false))
583 if (outof_target
!= 0)
584 if (!emit_conditional_move (outof_target
, cmp_code
, cmp1
, cmp2
, op1_mode
,
585 outof_target
, outof_superword
,
592 /* Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts.
593 OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first
594 input operand; the shift moves bits in the direction OUTOF_INPUT->
595 INTO_TARGET. OUTOF_TARGET and INTO_TARGET are the equivalent words
596 of the target. OP1 is the shift count and OP1_MODE is its mode.
597 If OP1 is constant, it will have been truncated as appropriate
598 and is known to be nonzero.
600 If SHIFT_MASK is zero, the result of word shifts is undefined when the
601 shift count is outside the range [0, BITS_PER_WORD). This routine must
602 avoid generating such shifts for OP1s in the range [0, BITS_PER_WORD * 2).
604 If SHIFT_MASK is nonzero, all word-mode shift counts are effectively
605 masked by it and shifts in the range [BITS_PER_WORD, SHIFT_MASK) will
606 fill with zeros or sign bits as appropriate.
608 If SHIFT_MASK is BITS_PER_WORD - 1, this routine will synthesize
609 a doubleword shift whose equivalent mask is BITS_PER_WORD * 2 - 1.
610 Doing this preserves semantics required by SHIFT_COUNT_TRUNCATED.
611 In all other cases, shifts by values outside [0, BITS_PER_UNIT * 2)
614 BINOPTAB, UNSIGNEDP and METHODS are as for expand_binop. This function
615 may not use INTO_INPUT after modifying INTO_TARGET, and similarly for
616 OUTOF_INPUT and OUTOF_TARGET. OUTOF_TARGET can be null if the parent
617 function wants to calculate it itself.
619 Return true if the shift could be successfully synthesized. */
622 expand_doubleword_shift (scalar_int_mode op1_mode
, optab binoptab
,
623 rtx outof_input
, rtx into_input
, rtx op1
,
624 rtx outof_target
, rtx into_target
,
625 int unsignedp
, enum optab_methods methods
,
626 unsigned HOST_WIDE_INT shift_mask
)
628 rtx superword_op1
, tmp
, cmp1
, cmp2
;
629 enum rtx_code cmp_code
;
631 /* See if word-mode shifts by BITS_PER_WORD...BITS_PER_WORD * 2 - 1 will
632 fill the result with sign or zero bits as appropriate. If so, the value
633 of OUTOF_TARGET will always be (SHIFT OUTOF_INPUT OP1). Recursively call
634 this routine to calculate INTO_TARGET (which depends on both OUTOF_INPUT
635 and INTO_INPUT), then emit code to set up OUTOF_TARGET.
637 This isn't worthwhile for constant shifts since the optimizers will
638 cope better with in-range shift counts. */
639 if (shift_mask
>= BITS_PER_WORD
641 && !CONSTANT_P (op1
))
643 if (!expand_doubleword_shift (op1_mode
, binoptab
,
644 outof_input
, into_input
, op1
,
646 unsignedp
, methods
, shift_mask
))
648 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, op1
,
649 outof_target
, unsignedp
, methods
))
654 /* Set CMP_CODE, CMP1 and CMP2 so that the rtx (CMP_CODE CMP1 CMP2)
655 is true when the effective shift value is less than BITS_PER_WORD.
656 Set SUPERWORD_OP1 to the shift count that should be used to shift
657 OUTOF_INPUT into INTO_TARGET when the condition is false. */
658 tmp
= immed_wide_int_const (wi::shwi (BITS_PER_WORD
, op1_mode
), op1_mode
);
659 if (!CONSTANT_P (op1
) && shift_mask
== BITS_PER_WORD
- 1)
661 /* Set CMP1 to OP1 & BITS_PER_WORD. The result is zero iff OP1
662 is a subword shift count. */
663 cmp1
= simplify_expand_binop (op1_mode
, and_optab
, op1
, tmp
,
665 cmp2
= CONST0_RTX (op1_mode
);
671 /* Set CMP1 to OP1 - BITS_PER_WORD. */
672 cmp1
= simplify_expand_binop (op1_mode
, sub_optab
, op1
, tmp
,
674 cmp2
= CONST0_RTX (op1_mode
);
676 superword_op1
= cmp1
;
681 /* If we can compute the condition at compile time, pick the
682 appropriate subroutine. */
683 tmp
= simplify_relational_operation (cmp_code
, SImode
, op1_mode
, cmp1
, cmp2
);
684 if (tmp
!= 0 && CONST_INT_P (tmp
))
686 if (tmp
== const0_rtx
)
687 return expand_superword_shift (binoptab
, outof_input
, superword_op1
,
688 outof_target
, into_target
,
691 return expand_subword_shift (op1_mode
, binoptab
,
692 outof_input
, into_input
, op1
,
693 outof_target
, into_target
,
694 unsignedp
, methods
, shift_mask
);
697 /* Try using conditional moves to generate straight-line code. */
698 if (HAVE_conditional_move
)
700 rtx_insn
*start
= get_last_insn ();
701 if (expand_doubleword_shift_condmove (op1_mode
, binoptab
,
702 cmp_code
, cmp1
, cmp2
,
703 outof_input
, into_input
,
705 outof_target
, into_target
,
706 unsignedp
, methods
, shift_mask
))
708 delete_insns_since (start
);
711 /* As a last resort, use branches to select the correct alternative. */
712 rtx_code_label
*subword_label
= gen_label_rtx ();
713 rtx_code_label
*done_label
= gen_label_rtx ();
716 do_compare_rtx_and_jump (cmp1
, cmp2
, cmp_code
, false, op1_mode
,
718 profile_probability::uninitialized ());
721 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
722 outof_target
, into_target
,
726 emit_jump_insn (targetm
.gen_jump (done_label
));
728 emit_label (subword_label
);
730 if (!expand_subword_shift (op1_mode
, binoptab
,
731 outof_input
, into_input
, op1
,
732 outof_target
, into_target
,
733 unsignedp
, methods
, shift_mask
))
736 emit_label (done_label
);
740 /* Subroutine of expand_binop. Perform a double word multiplication of
741 operands OP0 and OP1 both of mode MODE, which is exactly twice as wide
742 as the target's word_mode. This function return NULL_RTX if anything
743 goes wrong, in which case it may have already emitted instructions
744 which need to be deleted.
746 If we want to multiply two two-word values and have normal and widening
747 multiplies of single-word values, we can do this with three smaller
750 The multiplication proceeds as follows:
751 _______________________
752 [__op0_high_|__op0_low__]
753 _______________________
754 * [__op1_high_|__op1_low__]
755 _______________________________________________
756 _______________________
757 (1) [__op0_low__*__op1_low__]
758 _______________________
759 (2a) [__op0_low__*__op1_high_]
760 _______________________
761 (2b) [__op0_high_*__op1_low__]
762 _______________________
763 (3) [__op0_high_*__op1_high_]
766 This gives a 4-word result. Since we are only interested in the
767 lower 2 words, partial result (3) and the upper words of (2a) and
768 (2b) don't need to be calculated. Hence (2a) and (2b) can be
769 calculated using non-widening multiplication.
771 (1), however, needs to be calculated with an unsigned widening
772 multiplication. If this operation is not directly supported we
773 try using a signed widening multiplication and adjust the result.
774 This adjustment works as follows:
776 If both operands are positive then no adjustment is needed.
778 If the operands have different signs, for example op0_low < 0 and
779 op1_low >= 0, the instruction treats the most significant bit of
780 op0_low as a sign bit instead of a bit with significance
781 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low
782 with 2**BITS_PER_WORD - op0_low, and two's complements the
783 result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to
786 Similarly, if both operands are negative, we need to add
787 (op0_low + op1_low) * 2**BITS_PER_WORD.
789 We use a trick to adjust quickly. We logically shift op0_low right
790 (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to
791 op0_high (op1_high) before it is used to calculate 2b (2a). If no
792 logical shift exists, we do an arithmetic right shift and subtract
796 expand_doubleword_mult (machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
797 bool umulp
, enum optab_methods methods
)
799 int low
= (WORDS_BIG_ENDIAN
? 1 : 0);
800 int high
= (WORDS_BIG_ENDIAN
? 0 : 1);
801 rtx wordm1
= (umulp
? NULL_RTX
802 : gen_int_shift_amount (word_mode
, BITS_PER_WORD
- 1));
803 rtx product
, adjust
, product_high
, temp
;
805 rtx op0_high
= operand_subword_force (op0
, high
, mode
);
806 rtx op0_low
= operand_subword_force (op0
, low
, mode
);
807 rtx op1_high
= operand_subword_force (op1
, high
, mode
);
808 rtx op1_low
= operand_subword_force (op1
, low
, mode
);
810 /* If we're using an unsigned multiply to directly compute the product
811 of the low-order words of the operands and perform any required
812 adjustments of the operands, we begin by trying two more multiplications
813 and then computing the appropriate sum.
815 We have checked above that the required addition is provided.
816 Full-word addition will normally always succeed, especially if
817 it is provided at all, so we don't worry about its failure. The
818 multiplication may well fail, however, so we do handle that. */
822 /* ??? This could be done with emit_store_flag where available. */
823 temp
= expand_binop (word_mode
, lshr_optab
, op0_low
, wordm1
,
824 NULL_RTX
, 1, methods
);
826 op0_high
= expand_binop (word_mode
, add_optab
, op0_high
, temp
,
827 NULL_RTX
, 0, OPTAB_DIRECT
);
830 temp
= expand_binop (word_mode
, ashr_optab
, op0_low
, wordm1
,
831 NULL_RTX
, 0, methods
);
834 op0_high
= expand_binop (word_mode
, sub_optab
, op0_high
, temp
,
835 NULL_RTX
, 0, OPTAB_DIRECT
);
842 adjust
= expand_binop (word_mode
, smul_optab
, op0_high
, op1_low
,
843 NULL_RTX
, 0, OPTAB_DIRECT
);
847 /* OP0_HIGH should now be dead. */
851 /* ??? This could be done with emit_store_flag where available. */
852 temp
= expand_binop (word_mode
, lshr_optab
, op1_low
, wordm1
,
853 NULL_RTX
, 1, methods
);
855 op1_high
= expand_binop (word_mode
, add_optab
, op1_high
, temp
,
856 NULL_RTX
, 0, OPTAB_DIRECT
);
859 temp
= expand_binop (word_mode
, ashr_optab
, op1_low
, wordm1
,
860 NULL_RTX
, 0, methods
);
863 op1_high
= expand_binop (word_mode
, sub_optab
, op1_high
, temp
,
864 NULL_RTX
, 0, OPTAB_DIRECT
);
871 temp
= expand_binop (word_mode
, smul_optab
, op1_high
, op0_low
,
872 NULL_RTX
, 0, OPTAB_DIRECT
);
876 /* OP1_HIGH should now be dead. */
878 adjust
= expand_binop (word_mode
, add_optab
, adjust
, temp
,
879 NULL_RTX
, 0, OPTAB_DIRECT
);
881 if (target
&& !REG_P (target
))
884 /* *_widen_optab needs to determine operand mode, make sure at least
885 one operand has non-VOID mode. */
886 if (GET_MODE (op0_low
) == VOIDmode
&& GET_MODE (op1_low
) == VOIDmode
)
887 op0_low
= force_reg (word_mode
, op0_low
);
890 product
= expand_binop (mode
, umul_widen_optab
, op0_low
, op1_low
,
891 target
, 1, OPTAB_DIRECT
);
893 product
= expand_binop (mode
, smul_widen_optab
, op0_low
, op1_low
,
894 target
, 1, OPTAB_DIRECT
);
899 product_high
= operand_subword (product
, high
, 1, mode
);
900 adjust
= expand_binop (word_mode
, add_optab
, product_high
, adjust
,
901 NULL_RTX
, 0, OPTAB_DIRECT
);
902 emit_move_insn (product_high
, adjust
);
906 /* Wrapper around expand_binop which takes an rtx code to specify
907 the operation to perform, not an optab pointer. All other
908 arguments are the same. */
910 expand_simple_binop (machine_mode mode
, enum rtx_code code
, rtx op0
,
911 rtx op1
, rtx target
, int unsignedp
,
912 enum optab_methods methods
)
914 optab binop
= code_to_optab (code
);
917 return expand_binop (mode
, binop
, op0
, op1
, target
, unsignedp
, methods
);
920 /* Return whether OP0 and OP1 should be swapped when expanding a commutative
921 binop. Order them according to commutative_operand_precedence and, if
922 possible, try to put TARGET or a pseudo first. */
924 swap_commutative_operands_with_target (rtx target
, rtx op0
, rtx op1
)
926 int op0_prec
= commutative_operand_precedence (op0
);
927 int op1_prec
= commutative_operand_precedence (op1
);
929 if (op0_prec
< op1_prec
)
932 if (op0_prec
> op1_prec
)
935 /* With equal precedence, both orders are ok, but it is better if the
936 first operand is TARGET, or if both TARGET and OP0 are pseudos. */
937 if (target
== 0 || REG_P (target
))
938 return (REG_P (op1
) && !REG_P (op0
)) || target
== op1
;
940 return rtx_equal_p (op1
, target
);
943 /* Return true if BINOPTAB implements a shift operation. */
946 shift_optab_p (optab binoptab
)
948 switch (optab_to_code (binoptab
))
964 /* Return true if BINOPTAB implements a commutative binary operation. */
967 commutative_optab_p (optab binoptab
)
969 return (GET_RTX_CLASS (optab_to_code (binoptab
)) == RTX_COMM_ARITH
970 || binoptab
== smul_widen_optab
971 || binoptab
== umul_widen_optab
972 || binoptab
== smul_highpart_optab
973 || binoptab
== umul_highpart_optab
);
976 /* X is to be used in mode MODE as operand OPN to BINOPTAB. If we're
977 optimizing, and if the operand is a constant that costs more than
978 1 instruction, force the constant into a register and return that
979 register. Return X otherwise. UNSIGNEDP says whether X is unsigned. */
982 avoid_expensive_constant (machine_mode mode
, optab binoptab
,
983 int opn
, rtx x
, bool unsignedp
)
985 bool speed
= optimize_insn_for_speed_p ();
990 && (rtx_cost (x
, mode
, optab_to_code (binoptab
), opn
, speed
)
991 > set_src_cost (x
, mode
, speed
)))
995 HOST_WIDE_INT intval
= trunc_int_for_mode (INTVAL (x
), mode
);
996 if (intval
!= INTVAL (x
))
997 x
= GEN_INT (intval
);
1000 x
= convert_modes (mode
, VOIDmode
, x
, unsignedp
);
1001 x
= force_reg (mode
, x
);
1006 /* Helper function for expand_binop: handle the case where there
1007 is an insn ICODE that directly implements the indicated operation.
1008 Returns null if this is not possible. */
1010 expand_binop_directly (enum insn_code icode
, machine_mode mode
, optab binoptab
,
1012 rtx target
, int unsignedp
, enum optab_methods methods
,
1015 machine_mode xmode0
= insn_data
[(int) icode
].operand
[1].mode
;
1016 machine_mode xmode1
= insn_data
[(int) icode
].operand
[2].mode
;
1017 machine_mode mode0
, mode1
, tmp_mode
;
1018 struct expand_operand ops
[3];
1021 rtx xop0
= op0
, xop1
= op1
;
1022 bool canonicalize_op1
= false;
1024 /* If it is a commutative operator and the modes would match
1025 if we would swap the operands, we can save the conversions. */
1026 commutative_p
= commutative_optab_p (binoptab
);
1028 && GET_MODE (xop0
) != xmode0
&& GET_MODE (xop1
) != xmode1
1029 && GET_MODE (xop0
) == xmode1
&& GET_MODE (xop1
) == xmode1
)
1030 std::swap (xop0
, xop1
);
1032 /* If we are optimizing, force expensive constants into a register. */
1033 xop0
= avoid_expensive_constant (xmode0
, binoptab
, 0, xop0
, unsignedp
);
1034 if (!shift_optab_p (binoptab
))
1035 xop1
= avoid_expensive_constant (xmode1
, binoptab
, 1, xop1
, unsignedp
);
1037 /* Shifts and rotates often use a different mode for op1 from op0;
1038 for VOIDmode constants we don't know the mode, so force it
1039 to be canonicalized using convert_modes. */
1040 canonicalize_op1
= true;
1042 /* In case the insn wants input operands in modes different from
1043 those of the actual operands, convert the operands. It would
1044 seem that we don't need to convert CONST_INTs, but we do, so
1045 that they're properly zero-extended, sign-extended or truncated
1048 mode0
= GET_MODE (xop0
) != VOIDmode
? GET_MODE (xop0
) : mode
;
1049 if (xmode0
!= VOIDmode
&& xmode0
!= mode0
)
1051 xop0
= convert_modes (xmode0
, mode0
, xop0
, unsignedp
);
1055 mode1
= ((GET_MODE (xop1
) != VOIDmode
|| canonicalize_op1
)
1056 ? GET_MODE (xop1
) : mode
);
1057 if (xmode1
!= VOIDmode
&& xmode1
!= mode1
)
1059 xop1
= convert_modes (xmode1
, mode1
, xop1
, unsignedp
);
1063 /* If operation is commutative,
1064 try to make the first operand a register.
1065 Even better, try to make it the same as the target.
1066 Also try to make the last operand a constant. */
1068 && swap_commutative_operands_with_target (target
, xop0
, xop1
))
1069 std::swap (xop0
, xop1
);
1071 /* Now, if insn's predicates don't allow our operands, put them into
1074 if (binoptab
== vec_pack_trunc_optab
1075 || binoptab
== vec_pack_usat_optab
1076 || binoptab
== vec_pack_ssat_optab
1077 || binoptab
== vec_pack_ufix_trunc_optab
1078 || binoptab
== vec_pack_sfix_trunc_optab
1079 || binoptab
== vec_packu_float_optab
1080 || binoptab
== vec_packs_float_optab
)
1082 /* The mode of the result is different then the mode of the
1084 tmp_mode
= insn_data
[(int) icode
].operand
[0].mode
;
1085 if (VECTOR_MODE_P (mode
)
1086 && maybe_ne (GET_MODE_NUNITS (tmp_mode
), 2 * GET_MODE_NUNITS (mode
)))
1088 delete_insns_since (last
);
1095 create_output_operand (&ops
[0], target
, tmp_mode
);
1096 create_input_operand (&ops
[1], xop0
, mode0
);
1097 create_input_operand (&ops
[2], xop1
, mode1
);
1098 pat
= maybe_gen_insn (icode
, 3, ops
);
1101 /* If PAT is composed of more than one insn, try to add an appropriate
1102 REG_EQUAL note to it. If we can't because TEMP conflicts with an
1103 operand, call expand_binop again, this time without a target. */
1104 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
1105 && ! add_equal_note (pat
, ops
[0].value
,
1106 optab_to_code (binoptab
),
1107 ops
[1].value
, ops
[2].value
))
1109 delete_insns_since (last
);
1110 return expand_binop (mode
, binoptab
, op0
, op1
, NULL_RTX
,
1111 unsignedp
, methods
);
1115 return ops
[0].value
;
1117 delete_insns_since (last
);
1121 /* Generate code to perform an operation specified by BINOPTAB
1122 on operands OP0 and OP1, with result having machine-mode MODE.
1124 UNSIGNEDP is for the case where we have to widen the operands
1125 to perform the operation. It says to use zero-extension.
1127 If TARGET is nonzero, the value
1128 is generated there, if it is convenient to do so.
1129 In all cases an rtx is returned for the locus of the value;
1130 this may or may not be TARGET. */
1133 expand_binop (machine_mode mode
, optab binoptab
, rtx op0
, rtx op1
,
1134 rtx target
, int unsignedp
, enum optab_methods methods
)
1136 enum optab_methods next_methods
1137 = (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
1138 ? OPTAB_WIDEN
: methods
);
1139 enum mode_class mclass
;
1140 enum insn_code icode
;
1141 machine_mode wider_mode
;
1142 scalar_int_mode int_mode
;
1145 rtx_insn
*entry_last
= get_last_insn ();
1148 mclass
= GET_MODE_CLASS (mode
);
1150 /* If subtracting an integer constant, convert this into an addition of
1151 the negated constant. */
1153 if (binoptab
== sub_optab
&& CONST_INT_P (op1
))
1155 op1
= negate_rtx (mode
, op1
);
1156 binoptab
= add_optab
;
1158 /* For shifts, constant invalid op1 might be expanded from different
1159 mode than MODE. As those are invalid, force them to a register
1160 to avoid further problems during expansion. */
1161 else if (CONST_INT_P (op1
)
1162 && shift_optab_p (binoptab
)
1163 && UINTVAL (op1
) >= GET_MODE_BITSIZE (GET_MODE_INNER (mode
)))
1165 op1
= gen_int_mode (INTVAL (op1
), GET_MODE_INNER (mode
));
1166 op1
= force_reg (GET_MODE_INNER (mode
), op1
);
1169 /* Record where to delete back to if we backtrack. */
1170 last
= get_last_insn ();
1172 /* If we can do it with a three-operand insn, do so. */
1174 if (methods
!= OPTAB_MUST_WIDEN
)
1176 if (convert_optab_p (binoptab
))
1178 machine_mode from_mode
= widened_mode (mode
, op0
, op1
);
1179 icode
= find_widening_optab_handler (binoptab
, mode
, from_mode
);
1182 icode
= optab_handler (binoptab
, mode
);
1183 if (icode
!= CODE_FOR_nothing
)
1185 temp
= expand_binop_directly (icode
, mode
, binoptab
, op0
, op1
,
1186 target
, unsignedp
, methods
, last
);
1192 /* If we were trying to rotate, and that didn't work, try rotating
1193 the other direction before falling back to shifts and bitwise-or. */
1194 if (((binoptab
== rotl_optab
1195 && (icode
= optab_handler (rotr_optab
, mode
)) != CODE_FOR_nothing
)
1196 || (binoptab
== rotr_optab
1197 && (icode
= optab_handler (rotl_optab
, mode
)) != CODE_FOR_nothing
))
1198 && is_int_mode (mode
, &int_mode
))
1200 optab otheroptab
= (binoptab
== rotl_optab
? rotr_optab
: rotl_optab
);
1202 unsigned int bits
= GET_MODE_PRECISION (int_mode
);
1204 if (CONST_INT_P (op1
))
1205 newop1
= gen_int_shift_amount (int_mode
, bits
- INTVAL (op1
));
1206 else if (targetm
.shift_truncation_mask (int_mode
) == bits
- 1)
1207 newop1
= negate_rtx (GET_MODE (op1
), op1
);
1209 newop1
= expand_binop (GET_MODE (op1
), sub_optab
,
1210 gen_int_mode (bits
, GET_MODE (op1
)), op1
,
1211 NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
1213 temp
= expand_binop_directly (icode
, int_mode
, otheroptab
, op0
, newop1
,
1214 target
, unsignedp
, methods
, last
);
1219 /* If this is a multiply, see if we can do a widening operation that
1220 takes operands of this mode and makes a wider mode. */
1222 if (binoptab
== smul_optab
1223 && GET_MODE_2XWIDER_MODE (mode
).exists (&wider_mode
)
1224 && (convert_optab_handler ((unsignedp
1226 : smul_widen_optab
),
1227 wider_mode
, mode
) != CODE_FOR_nothing
))
1229 /* *_widen_optab needs to determine operand mode, make sure at least
1230 one operand has non-VOID mode. */
1231 if (GET_MODE (op0
) == VOIDmode
&& GET_MODE (op1
) == VOIDmode
)
1232 op0
= force_reg (mode
, op0
);
1233 temp
= expand_binop (wider_mode
,
1234 unsignedp
? umul_widen_optab
: smul_widen_optab
,
1235 op0
, op1
, NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
1239 if (GET_MODE_CLASS (mode
) == MODE_INT
1240 && TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (temp
)))
1241 return gen_lowpart (mode
, temp
);
1243 return convert_to_mode (mode
, temp
, unsignedp
);
1247 /* If this is a vector shift by a scalar, see if we can do a vector
1248 shift by a vector. If so, broadcast the scalar into a vector. */
1249 if (mclass
== MODE_VECTOR_INT
)
1251 optab otheroptab
= unknown_optab
;
1253 if (binoptab
== ashl_optab
)
1254 otheroptab
= vashl_optab
;
1255 else if (binoptab
== ashr_optab
)
1256 otheroptab
= vashr_optab
;
1257 else if (binoptab
== lshr_optab
)
1258 otheroptab
= vlshr_optab
;
1259 else if (binoptab
== rotl_optab
)
1260 otheroptab
= vrotl_optab
;
1261 else if (binoptab
== rotr_optab
)
1262 otheroptab
= vrotr_optab
;
1265 && (icode
= optab_handler (otheroptab
, mode
)) != CODE_FOR_nothing
)
1267 /* The scalar may have been extended to be too wide. Truncate
1268 it back to the proper size to fit in the broadcast vector. */
1269 scalar_mode inner_mode
= GET_MODE_INNER (mode
);
1270 if (!CONST_INT_P (op1
)
1271 && (GET_MODE_BITSIZE (as_a
<scalar_int_mode
> (GET_MODE (op1
)))
1272 > GET_MODE_BITSIZE (inner_mode
)))
1273 op1
= force_reg (inner_mode
,
1274 simplify_gen_unary (TRUNCATE
, inner_mode
, op1
,
1276 rtx vop1
= expand_vector_broadcast (mode
, op1
);
1279 temp
= expand_binop_directly (icode
, mode
, otheroptab
, op0
, vop1
,
1280 target
, unsignedp
, methods
, last
);
1287 /* Look for a wider mode of the same class for which we think we
1288 can open-code the operation. Check for a widening multiply at the
1289 wider mode as well. */
1291 if (CLASS_HAS_WIDER_MODES_P (mclass
)
1292 && methods
!= OPTAB_DIRECT
&& methods
!= OPTAB_LIB
)
1293 FOR_EACH_WIDER_MODE (wider_mode
, mode
)
1295 machine_mode next_mode
;
1296 if (optab_handler (binoptab
, wider_mode
) != CODE_FOR_nothing
1297 || (binoptab
== smul_optab
1298 && GET_MODE_WIDER_MODE (wider_mode
).exists (&next_mode
)
1299 && (find_widening_optab_handler ((unsignedp
1301 : smul_widen_optab
),
1303 != CODE_FOR_nothing
)))
1305 rtx xop0
= op0
, xop1
= op1
;
1308 /* For certain integer operations, we need not actually extend
1309 the narrow operands, as long as we will truncate
1310 the results to the same narrowness. */
1312 if ((binoptab
== ior_optab
|| binoptab
== and_optab
1313 || binoptab
== xor_optab
1314 || binoptab
== add_optab
|| binoptab
== sub_optab
1315 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
1316 && mclass
== MODE_INT
)
1319 xop0
= avoid_expensive_constant (mode
, binoptab
, 0,
1321 if (binoptab
!= ashl_optab
)
1322 xop1
= avoid_expensive_constant (mode
, binoptab
, 1,
1326 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
, no_extend
);
1328 /* The second operand of a shift must always be extended. */
1329 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
1330 no_extend
&& binoptab
!= ashl_optab
);
1332 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
1333 unsignedp
, OPTAB_DIRECT
);
1336 if (mclass
!= MODE_INT
1337 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
1340 target
= gen_reg_rtx (mode
);
1341 convert_move (target
, temp
, 0);
1345 return gen_lowpart (mode
, temp
);
1348 delete_insns_since (last
);
1352 /* If operation is commutative,
1353 try to make the first operand a register.
1354 Even better, try to make it the same as the target.
1355 Also try to make the last operand a constant. */
1356 if (commutative_optab_p (binoptab
)
1357 && swap_commutative_operands_with_target (target
, op0
, op1
))
1358 std::swap (op0
, op1
);
1360 /* These can be done a word at a time. */
1361 if ((binoptab
== and_optab
|| binoptab
== ior_optab
|| binoptab
== xor_optab
)
1362 && is_int_mode (mode
, &int_mode
)
1363 && GET_MODE_SIZE (int_mode
) > UNITS_PER_WORD
1364 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
)
1369 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1370 won't be accurate, so use a new target. */
1374 || !valid_multiword_target_p (target
))
1375 target
= gen_reg_rtx (int_mode
);
1379 /* Do the actual arithmetic. */
1380 machine_mode op0_mode
= GET_MODE (op0
);
1381 machine_mode op1_mode
= GET_MODE (op1
);
1382 if (op0_mode
== VOIDmode
)
1383 op0_mode
= int_mode
;
1384 if (op1_mode
== VOIDmode
)
1385 op1_mode
= int_mode
;
1386 for (i
= 0; i
< GET_MODE_BITSIZE (int_mode
) / BITS_PER_WORD
; i
++)
1388 rtx target_piece
= operand_subword (target
, i
, 1, int_mode
);
1389 rtx x
= expand_binop (word_mode
, binoptab
,
1390 operand_subword_force (op0
, i
, op0_mode
),
1391 operand_subword_force (op1
, i
, op1_mode
),
1392 target_piece
, unsignedp
, next_methods
);
1397 if (target_piece
!= x
)
1398 emit_move_insn (target_piece
, x
);
1401 insns
= get_insns ();
1404 if (i
== GET_MODE_BITSIZE (int_mode
) / BITS_PER_WORD
)
1411 /* Synthesize double word shifts from single word shifts. */
1412 if ((binoptab
== lshr_optab
|| binoptab
== ashl_optab
1413 || binoptab
== ashr_optab
)
1414 && is_int_mode (mode
, &int_mode
)
1415 && (CONST_INT_P (op1
) || optimize_insn_for_speed_p ())
1416 && GET_MODE_SIZE (int_mode
) == 2 * UNITS_PER_WORD
1417 && GET_MODE_PRECISION (int_mode
) == GET_MODE_BITSIZE (int_mode
)
1418 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
1419 && optab_handler (ashl_optab
, word_mode
) != CODE_FOR_nothing
1420 && optab_handler (lshr_optab
, word_mode
) != CODE_FOR_nothing
)
1422 unsigned HOST_WIDE_INT shift_mask
, double_shift_mask
;
1423 scalar_int_mode op1_mode
;
1425 double_shift_mask
= targetm
.shift_truncation_mask (int_mode
);
1426 shift_mask
= targetm
.shift_truncation_mask (word_mode
);
1427 op1_mode
= (GET_MODE (op1
) != VOIDmode
1428 ? as_a
<scalar_int_mode
> (GET_MODE (op1
))
1431 /* Apply the truncation to constant shifts. */
1432 if (double_shift_mask
> 0 && CONST_INT_P (op1
))
1433 op1
= gen_int_mode (INTVAL (op1
) & double_shift_mask
, op1_mode
);
1435 if (op1
== CONST0_RTX (op1_mode
))
1438 /* Make sure that this is a combination that expand_doubleword_shift
1439 can handle. See the comments there for details. */
1440 if (double_shift_mask
== 0
1441 || (shift_mask
== BITS_PER_WORD
- 1
1442 && double_shift_mask
== BITS_PER_WORD
* 2 - 1))
1445 rtx into_target
, outof_target
;
1446 rtx into_input
, outof_input
;
1447 int left_shift
, outof_word
;
1449 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1450 won't be accurate, so use a new target. */
1454 || !valid_multiword_target_p (target
))
1455 target
= gen_reg_rtx (int_mode
);
1459 /* OUTOF_* is the word we are shifting bits away from, and
1460 INTO_* is the word that we are shifting bits towards, thus
1461 they differ depending on the direction of the shift and
1462 WORDS_BIG_ENDIAN. */
1464 left_shift
= binoptab
== ashl_optab
;
1465 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
1467 outof_target
= operand_subword (target
, outof_word
, 1, int_mode
);
1468 into_target
= operand_subword (target
, 1 - outof_word
, 1, int_mode
);
1470 outof_input
= operand_subword_force (op0
, outof_word
, int_mode
);
1471 into_input
= operand_subword_force (op0
, 1 - outof_word
, int_mode
);
1473 if (expand_doubleword_shift (op1_mode
, binoptab
,
1474 outof_input
, into_input
, op1
,
1475 outof_target
, into_target
,
1476 unsignedp
, next_methods
, shift_mask
))
1478 insns
= get_insns ();
1488 /* Synthesize double word rotates from single word shifts. */
1489 if ((binoptab
== rotl_optab
|| binoptab
== rotr_optab
)
1490 && is_int_mode (mode
, &int_mode
)
1491 && CONST_INT_P (op1
)
1492 && GET_MODE_PRECISION (int_mode
) == 2 * BITS_PER_WORD
1493 && optab_handler (ashl_optab
, word_mode
) != CODE_FOR_nothing
1494 && optab_handler (lshr_optab
, word_mode
) != CODE_FOR_nothing
)
1497 rtx into_target
, outof_target
;
1498 rtx into_input
, outof_input
;
1500 int shift_count
, left_shift
, outof_word
;
1502 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1503 won't be accurate, so use a new target. Do this also if target is not
1504 a REG, first because having a register instead may open optimization
1505 opportunities, and second because if target and op0 happen to be MEMs
1506 designating the same location, we would risk clobbering it too early
1507 in the code sequence we generate below. */
1512 || !valid_multiword_target_p (target
))
1513 target
= gen_reg_rtx (int_mode
);
1517 shift_count
= INTVAL (op1
);
1519 /* OUTOF_* is the word we are shifting bits away from, and
1520 INTO_* is the word that we are shifting bits towards, thus
1521 they differ depending on the direction of the shift and
1522 WORDS_BIG_ENDIAN. */
1524 left_shift
= (binoptab
== rotl_optab
);
1525 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
1527 outof_target
= operand_subword (target
, outof_word
, 1, int_mode
);
1528 into_target
= operand_subword (target
, 1 - outof_word
, 1, int_mode
);
1530 outof_input
= operand_subword_force (op0
, outof_word
, int_mode
);
1531 into_input
= operand_subword_force (op0
, 1 - outof_word
, int_mode
);
1533 if (shift_count
== BITS_PER_WORD
)
1535 /* This is just a word swap. */
1536 emit_move_insn (outof_target
, into_input
);
1537 emit_move_insn (into_target
, outof_input
);
1542 rtx into_temp1
, into_temp2
, outof_temp1
, outof_temp2
;
1543 HOST_WIDE_INT first_shift_count
, second_shift_count
;
1544 optab reverse_unsigned_shift
, unsigned_shift
;
1546 reverse_unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
1547 ? lshr_optab
: ashl_optab
);
1549 unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
1550 ? ashl_optab
: lshr_optab
);
1552 if (shift_count
> BITS_PER_WORD
)
1554 first_shift_count
= shift_count
- BITS_PER_WORD
;
1555 second_shift_count
= 2 * BITS_PER_WORD
- shift_count
;
1559 first_shift_count
= BITS_PER_WORD
- shift_count
;
1560 second_shift_count
= shift_count
;
1562 rtx first_shift_count_rtx
1563 = gen_int_shift_amount (word_mode
, first_shift_count
);
1564 rtx second_shift_count_rtx
1565 = gen_int_shift_amount (word_mode
, second_shift_count
);
1567 into_temp1
= expand_binop (word_mode
, unsigned_shift
,
1568 outof_input
, first_shift_count_rtx
,
1569 NULL_RTX
, unsignedp
, next_methods
);
1570 into_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
1571 into_input
, second_shift_count_rtx
,
1572 NULL_RTX
, unsignedp
, next_methods
);
1574 if (into_temp1
!= 0 && into_temp2
!= 0)
1575 inter
= expand_binop (word_mode
, ior_optab
, into_temp1
, into_temp2
,
1576 into_target
, unsignedp
, next_methods
);
1580 if (inter
!= 0 && inter
!= into_target
)
1581 emit_move_insn (into_target
, inter
);
1583 outof_temp1
= expand_binop (word_mode
, unsigned_shift
,
1584 into_input
, first_shift_count_rtx
,
1585 NULL_RTX
, unsignedp
, next_methods
);
1586 outof_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
1587 outof_input
, second_shift_count_rtx
,
1588 NULL_RTX
, unsignedp
, next_methods
);
1590 if (inter
!= 0 && outof_temp1
!= 0 && outof_temp2
!= 0)
1591 inter
= expand_binop (word_mode
, ior_optab
,
1592 outof_temp1
, outof_temp2
,
1593 outof_target
, unsignedp
, next_methods
);
1595 if (inter
!= 0 && inter
!= outof_target
)
1596 emit_move_insn (outof_target
, inter
);
1599 insns
= get_insns ();
1609 /* These can be done a word at a time by propagating carries. */
1610 if ((binoptab
== add_optab
|| binoptab
== sub_optab
)
1611 && is_int_mode (mode
, &int_mode
)
1612 && GET_MODE_SIZE (int_mode
) >= 2 * UNITS_PER_WORD
1613 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
)
1616 optab otheroptab
= binoptab
== add_optab
? sub_optab
: add_optab
;
1617 const unsigned int nwords
= GET_MODE_BITSIZE (int_mode
) / BITS_PER_WORD
;
1618 rtx carry_in
= NULL_RTX
, carry_out
= NULL_RTX
;
1619 rtx xop0
, xop1
, xtarget
;
1621 /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG
1622 value is one of those, use it. Otherwise, use 1 since it is the
1623 one easiest to get. */
1624 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
1625 int normalizep
= STORE_FLAG_VALUE
;
1630 /* Prepare the operands. */
1631 xop0
= force_reg (int_mode
, op0
);
1632 xop1
= force_reg (int_mode
, op1
);
1634 xtarget
= gen_reg_rtx (int_mode
);
1636 if (target
== 0 || !REG_P (target
) || !valid_multiword_target_p (target
))
1639 /* Indicate for flow that the entire target reg is being set. */
1641 emit_clobber (xtarget
);
1643 /* Do the actual arithmetic. */
1644 for (i
= 0; i
< nwords
; i
++)
1646 int index
= (WORDS_BIG_ENDIAN
? nwords
- i
- 1 : i
);
1647 rtx target_piece
= operand_subword (xtarget
, index
, 1, int_mode
);
1648 rtx op0_piece
= operand_subword_force (xop0
, index
, int_mode
);
1649 rtx op1_piece
= operand_subword_force (xop1
, index
, int_mode
);
1652 /* Main add/subtract of the input operands. */
1653 x
= expand_binop (word_mode
, binoptab
,
1654 op0_piece
, op1_piece
,
1655 target_piece
, unsignedp
, next_methods
);
1661 /* Store carry from main add/subtract. */
1662 carry_out
= gen_reg_rtx (word_mode
);
1663 carry_out
= emit_store_flag_force (carry_out
,
1664 (binoptab
== add_optab
1667 word_mode
, 1, normalizep
);
1674 /* Add/subtract previous carry to main result. */
1675 newx
= expand_binop (word_mode
,
1676 normalizep
== 1 ? binoptab
: otheroptab
,
1678 NULL_RTX
, 1, next_methods
);
1682 /* Get out carry from adding/subtracting carry in. */
1683 rtx carry_tmp
= gen_reg_rtx (word_mode
);
1684 carry_tmp
= emit_store_flag_force (carry_tmp
,
1685 (binoptab
== add_optab
1688 word_mode
, 1, normalizep
);
1690 /* Logical-ior the two poss. carry together. */
1691 carry_out
= expand_binop (word_mode
, ior_optab
,
1692 carry_out
, carry_tmp
,
1693 carry_out
, 0, next_methods
);
1697 emit_move_insn (target_piece
, newx
);
1701 if (x
!= target_piece
)
1702 emit_move_insn (target_piece
, x
);
1705 carry_in
= carry_out
;
1708 if (i
== GET_MODE_BITSIZE (int_mode
) / (unsigned) BITS_PER_WORD
)
1710 if (optab_handler (mov_optab
, int_mode
) != CODE_FOR_nothing
1711 || ! rtx_equal_p (target
, xtarget
))
1713 rtx_insn
*temp
= emit_move_insn (target
, xtarget
);
1715 set_dst_reg_note (temp
, REG_EQUAL
,
1716 gen_rtx_fmt_ee (optab_to_code (binoptab
),
1717 int_mode
, copy_rtx (xop0
),
1728 delete_insns_since (last
);
1731 /* Attempt to synthesize double word multiplies using a sequence of word
1732 mode multiplications. We first attempt to generate a sequence using a
1733 more efficient unsigned widening multiply, and if that fails we then
1734 try using a signed widening multiply. */
1736 if (binoptab
== smul_optab
1737 && is_int_mode (mode
, &int_mode
)
1738 && GET_MODE_SIZE (int_mode
) == 2 * UNITS_PER_WORD
1739 && optab_handler (smul_optab
, word_mode
) != CODE_FOR_nothing
1740 && optab_handler (add_optab
, word_mode
) != CODE_FOR_nothing
)
1742 rtx product
= NULL_RTX
;
1743 if (convert_optab_handler (umul_widen_optab
, int_mode
, word_mode
)
1744 != CODE_FOR_nothing
)
1746 product
= expand_doubleword_mult (int_mode
, op0
, op1
, target
,
1749 delete_insns_since (last
);
1752 if (product
== NULL_RTX
1753 && (convert_optab_handler (smul_widen_optab
, int_mode
, word_mode
)
1754 != CODE_FOR_nothing
))
1756 product
= expand_doubleword_mult (int_mode
, op0
, op1
, target
,
1759 delete_insns_since (last
);
1762 if (product
!= NULL_RTX
)
1764 if (optab_handler (mov_optab
, int_mode
) != CODE_FOR_nothing
)
1766 rtx_insn
*move
= emit_move_insn (target
? target
: product
,
1768 set_dst_reg_note (move
,
1770 gen_rtx_fmt_ee (MULT
, int_mode
,
1773 target
? target
: product
);
1779 /* It can't be open-coded in this mode.
1780 Use a library call if one is available and caller says that's ok. */
1782 libfunc
= optab_libfunc (binoptab
, mode
);
1784 && (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
))
1788 machine_mode op1_mode
= mode
;
1793 if (shift_optab_p (binoptab
))
1795 op1_mode
= targetm
.libgcc_shift_count_mode ();
1796 /* Specify unsigned here,
1797 since negative shift counts are meaningless. */
1798 op1x
= convert_to_mode (op1_mode
, op1
, 1);
1801 if (GET_MODE (op0
) != VOIDmode
1802 && GET_MODE (op0
) != mode
)
1803 op0
= convert_to_mode (mode
, op0
, unsignedp
);
1805 /* Pass 1 for NO_QUEUE so we don't lose any increments
1806 if the libcall is cse'd or moved. */
1807 value
= emit_library_call_value (libfunc
,
1808 NULL_RTX
, LCT_CONST
, mode
,
1809 op0
, mode
, op1x
, op1_mode
);
1811 insns
= get_insns ();
1814 bool trapv
= trapv_binoptab_p (binoptab
);
1815 target
= gen_reg_rtx (mode
);
1816 emit_libcall_block_1 (insns
, target
, value
,
1818 : gen_rtx_fmt_ee (optab_to_code (binoptab
),
1819 mode
, op0
, op1
), trapv
);
1824 delete_insns_since (last
);
1826 /* It can't be done in this mode. Can we do it in a wider mode? */
1828 if (! (methods
== OPTAB_WIDEN
|| methods
== OPTAB_LIB_WIDEN
1829 || methods
== OPTAB_MUST_WIDEN
))
1831 /* Caller says, don't even try. */
1832 delete_insns_since (entry_last
);
1836 /* Compute the value of METHODS to pass to recursive calls.
1837 Don't allow widening to be tried recursively. */
1839 methods
= (methods
== OPTAB_LIB_WIDEN
? OPTAB_LIB
: OPTAB_DIRECT
);
1841 /* Look for a wider mode of the same class for which it appears we can do
1844 if (CLASS_HAS_WIDER_MODES_P (mclass
))
1846 /* This code doesn't make sense for conversion optabs, since we
1847 wouldn't then want to extend the operands to be the same size
1849 gcc_assert (!convert_optab_p (binoptab
));
1850 FOR_EACH_WIDER_MODE (wider_mode
, mode
)
1852 if (optab_handler (binoptab
, wider_mode
)
1853 || (methods
== OPTAB_LIB
1854 && optab_libfunc (binoptab
, wider_mode
)))
1856 rtx xop0
= op0
, xop1
= op1
;
1859 /* For certain integer operations, we need not actually extend
1860 the narrow operands, as long as we will truncate
1861 the results to the same narrowness. */
1863 if ((binoptab
== ior_optab
|| binoptab
== and_optab
1864 || binoptab
== xor_optab
1865 || binoptab
== add_optab
|| binoptab
== sub_optab
1866 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
1867 && mclass
== MODE_INT
)
1870 xop0
= widen_operand (xop0
, wider_mode
, mode
,
1871 unsignedp
, no_extend
);
1873 /* The second operand of a shift must always be extended. */
1874 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
1875 no_extend
&& binoptab
!= ashl_optab
);
1877 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
1878 unsignedp
, methods
);
1881 if (mclass
!= MODE_INT
1882 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
1885 target
= gen_reg_rtx (mode
);
1886 convert_move (target
, temp
, 0);
1890 return gen_lowpart (mode
, temp
);
1893 delete_insns_since (last
);
1898 delete_insns_since (entry_last
);
1902 /* Expand a binary operator which has both signed and unsigned forms.
1903 UOPTAB is the optab for unsigned operations, and SOPTAB is for
1906 If we widen unsigned operands, we may use a signed wider operation instead
1907 of an unsigned wider operation, since the result would be the same. */
1910 sign_expand_binop (machine_mode mode
, optab uoptab
, optab soptab
,
1911 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
1912 enum optab_methods methods
)
1915 optab direct_optab
= unsignedp
? uoptab
: soptab
;
1918 /* Do it without widening, if possible. */
1919 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
,
1920 unsignedp
, OPTAB_DIRECT
);
1921 if (temp
|| methods
== OPTAB_DIRECT
)
1924 /* Try widening to a signed int. Disable any direct use of any
1925 signed insn in the current mode. */
1926 save_enable
= swap_optab_enable (soptab
, mode
, false);
1928 temp
= expand_binop (mode
, soptab
, op0
, op1
, target
,
1929 unsignedp
, OPTAB_WIDEN
);
1931 /* For unsigned operands, try widening to an unsigned int. */
1932 if (!temp
&& unsignedp
)
1933 temp
= expand_binop (mode
, uoptab
, op0
, op1
, target
,
1934 unsignedp
, OPTAB_WIDEN
);
1935 if (temp
|| methods
== OPTAB_WIDEN
)
1938 /* Use the right width libcall if that exists. */
1939 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
,
1940 unsignedp
, OPTAB_LIB
);
1941 if (temp
|| methods
== OPTAB_LIB
)
1944 /* Must widen and use a libcall, use either signed or unsigned. */
1945 temp
= expand_binop (mode
, soptab
, op0
, op1
, target
,
1946 unsignedp
, methods
);
1947 if (!temp
&& unsignedp
)
1948 temp
= expand_binop (mode
, uoptab
, op0
, op1
, target
,
1949 unsignedp
, methods
);
1952 /* Undo the fiddling above. */
1954 swap_optab_enable (soptab
, mode
, true);
1958 /* Generate code to perform an operation specified by UNOPPTAB
1959 on operand OP0, with two results to TARG0 and TARG1.
1960 We assume that the order of the operands for the instruction
1961 is TARG0, TARG1, OP0.
1963 Either TARG0 or TARG1 may be zero, but what that means is that
1964 the result is not actually wanted. We will generate it into
1965 a dummy pseudo-reg and discard it. They may not both be zero.
1967 Returns 1 if this operation can be performed; 0 if not. */
1970 expand_twoval_unop (optab unoptab
, rtx op0
, rtx targ0
, rtx targ1
,
1973 machine_mode mode
= GET_MODE (targ0
? targ0
: targ1
);
1974 enum mode_class mclass
;
1975 machine_mode wider_mode
;
1976 rtx_insn
*entry_last
= get_last_insn ();
1979 mclass
= GET_MODE_CLASS (mode
);
1982 targ0
= gen_reg_rtx (mode
);
1984 targ1
= gen_reg_rtx (mode
);
1986 /* Record where to go back to if we fail. */
1987 last
= get_last_insn ();
1989 if (optab_handler (unoptab
, mode
) != CODE_FOR_nothing
)
1991 struct expand_operand ops
[3];
1992 enum insn_code icode
= optab_handler (unoptab
, mode
);
1994 create_fixed_operand (&ops
[0], targ0
);
1995 create_fixed_operand (&ops
[1], targ1
);
1996 create_convert_operand_from (&ops
[2], op0
, mode
, unsignedp
);
1997 if (maybe_expand_insn (icode
, 3, ops
))
2001 /* It can't be done in this mode. Can we do it in a wider mode? */
2003 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2005 FOR_EACH_WIDER_MODE (wider_mode
, mode
)
2007 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
2009 rtx t0
= gen_reg_rtx (wider_mode
);
2010 rtx t1
= gen_reg_rtx (wider_mode
);
2011 rtx cop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
2013 if (expand_twoval_unop (unoptab
, cop0
, t0
, t1
, unsignedp
))
2015 convert_move (targ0
, t0
, unsignedp
);
2016 convert_move (targ1
, t1
, unsignedp
);
2020 delete_insns_since (last
);
2025 delete_insns_since (entry_last
);
2029 /* Generate code to perform an operation specified by BINOPTAB
2030 on operands OP0 and OP1, with two results to TARG1 and TARG2.
2031 We assume that the order of the operands for the instruction
2032 is TARG0, OP0, OP1, TARG1, which would fit a pattern like
2033 [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))].
2035 Either TARG0 or TARG1 may be zero, but what that means is that
2036 the result is not actually wanted. We will generate it into
2037 a dummy pseudo-reg and discard it. They may not both be zero.
2039 Returns 1 if this operation can be performed; 0 if not. */
2042 expand_twoval_binop (optab binoptab
, rtx op0
, rtx op1
, rtx targ0
, rtx targ1
,
2045 machine_mode mode
= GET_MODE (targ0
? targ0
: targ1
);
2046 enum mode_class mclass
;
2047 machine_mode wider_mode
;
2048 rtx_insn
*entry_last
= get_last_insn ();
2051 mclass
= GET_MODE_CLASS (mode
);
2054 targ0
= gen_reg_rtx (mode
);
2056 targ1
= gen_reg_rtx (mode
);
2058 /* Record where to go back to if we fail. */
2059 last
= get_last_insn ();
2061 if (optab_handler (binoptab
, mode
) != CODE_FOR_nothing
)
2063 struct expand_operand ops
[4];
2064 enum insn_code icode
= optab_handler (binoptab
, mode
);
2065 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
2066 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
2067 rtx xop0
= op0
, xop1
= op1
;
2069 /* If we are optimizing, force expensive constants into a register. */
2070 xop0
= avoid_expensive_constant (mode0
, binoptab
, 0, xop0
, unsignedp
);
2071 xop1
= avoid_expensive_constant (mode1
, binoptab
, 1, xop1
, unsignedp
);
2073 create_fixed_operand (&ops
[0], targ0
);
2074 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
2075 create_convert_operand_from (&ops
[2], op1
, mode
, unsignedp
);
2076 create_fixed_operand (&ops
[3], targ1
);
2077 if (maybe_expand_insn (icode
, 4, ops
))
2079 delete_insns_since (last
);
2082 /* It can't be done in this mode. Can we do it in a wider mode? */
2084 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2086 FOR_EACH_WIDER_MODE (wider_mode
, mode
)
2088 if (optab_handler (binoptab
, wider_mode
) != CODE_FOR_nothing
)
2090 rtx t0
= gen_reg_rtx (wider_mode
);
2091 rtx t1
= gen_reg_rtx (wider_mode
);
2092 rtx cop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
2093 rtx cop1
= convert_modes (wider_mode
, mode
, op1
, unsignedp
);
2095 if (expand_twoval_binop (binoptab
, cop0
, cop1
,
2098 convert_move (targ0
, t0
, unsignedp
);
2099 convert_move (targ1
, t1
, unsignedp
);
2103 delete_insns_since (last
);
2108 delete_insns_since (entry_last
);
2112 /* Expand the two-valued library call indicated by BINOPTAB, but
2113 preserve only one of the values. If TARG0 is non-NULL, the first
2114 value is placed into TARG0; otherwise the second value is placed
2115 into TARG1. Exactly one of TARG0 and TARG1 must be non-NULL. The
2116 value stored into TARG0 or TARG1 is equivalent to (CODE OP0 OP1).
2117 This routine assumes that the value returned by the library call is
2118 as if the return value was of an integral mode twice as wide as the
2119 mode of OP0. Returns 1 if the call was successful. */
2122 expand_twoval_binop_libfunc (optab binoptab
, rtx op0
, rtx op1
,
2123 rtx targ0
, rtx targ1
, enum rtx_code code
)
2126 machine_mode libval_mode
;
2131 /* Exactly one of TARG0 or TARG1 should be non-NULL. */
2132 gcc_assert (!targ0
!= !targ1
);
2134 mode
= GET_MODE (op0
);
2135 libfunc
= optab_libfunc (binoptab
, mode
);
2139 /* The value returned by the library function will have twice as
2140 many bits as the nominal MODE. */
2141 libval_mode
= smallest_int_mode_for_size (2 * GET_MODE_BITSIZE (mode
));
2143 libval
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
2147 /* Get the part of VAL containing the value that we want. */
2148 libval
= simplify_gen_subreg (mode
, libval
, libval_mode
,
2149 targ0
? 0 : GET_MODE_SIZE (mode
));
2150 insns
= get_insns ();
2152 /* Move the into the desired location. */
2153 emit_libcall_block (insns
, targ0
? targ0
: targ1
, libval
,
2154 gen_rtx_fmt_ee (code
, mode
, op0
, op1
));
2160 /* Wrapper around expand_unop which takes an rtx code to specify
2161 the operation to perform, not an optab pointer. All other
2162 arguments are the same. */
2164 expand_simple_unop (machine_mode mode
, enum rtx_code code
, rtx op0
,
2165 rtx target
, int unsignedp
)
2167 optab unop
= code_to_optab (code
);
2170 return expand_unop (mode
, unop
, op0
, target
, unsignedp
);
2176 (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)).
2178 A similar operation can be used for clrsb. UNOPTAB says which operation
2179 we are trying to expand. */
2181 widen_leading (scalar_int_mode mode
, rtx op0
, rtx target
, optab unoptab
)
2183 opt_scalar_int_mode wider_mode_iter
;
2184 FOR_EACH_WIDER_MODE (wider_mode_iter
, mode
)
2186 scalar_int_mode wider_mode
= wider_mode_iter
.require ();
2187 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
2192 last
= get_last_insn ();
2195 target
= gen_reg_rtx (mode
);
2196 xop0
= widen_operand (op0
, wider_mode
, mode
,
2197 unoptab
!= clrsb_optab
, false);
2198 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
2199 unoptab
!= clrsb_optab
);
2202 (wider_mode
, sub_optab
, temp
,
2203 gen_int_mode (GET_MODE_PRECISION (wider_mode
)
2204 - GET_MODE_PRECISION (mode
),
2206 target
, true, OPTAB_DIRECT
);
2208 delete_insns_since (last
);
2216 /* Try calculating clz of a double-word quantity as two clz's of word-sized
2217 quantities, choosing which based on whether the high word is nonzero. */
2219 expand_doubleword_clz (scalar_int_mode mode
, rtx op0
, rtx target
)
2221 rtx xop0
= force_reg (mode
, op0
);
2222 rtx subhi
= gen_highpart (word_mode
, xop0
);
2223 rtx sublo
= gen_lowpart (word_mode
, xop0
);
2224 rtx_code_label
*hi0_label
= gen_label_rtx ();
2225 rtx_code_label
*after_label
= gen_label_rtx ();
2229 /* If we were not given a target, use a word_mode register, not a
2230 'mode' register. The result will fit, and nobody is expecting
2231 anything bigger (the return type of __builtin_clz* is int). */
2233 target
= gen_reg_rtx (word_mode
);
2235 /* In any case, write to a word_mode scratch in both branches of the
2236 conditional, so we can ensure there is a single move insn setting
2237 'target' to tag a REG_EQUAL note on. */
2238 result
= gen_reg_rtx (word_mode
);
2242 /* If the high word is not equal to zero,
2243 then clz of the full value is clz of the high word. */
2244 emit_cmp_and_jump_insns (subhi
, CONST0_RTX (word_mode
), EQ
, 0,
2245 word_mode
, true, hi0_label
);
2247 temp
= expand_unop_direct (word_mode
, clz_optab
, subhi
, result
, true);
2252 convert_move (result
, temp
, true);
2254 emit_jump_insn (targetm
.gen_jump (after_label
));
2257 /* Else clz of the full value is clz of the low word plus the number
2258 of bits in the high word. */
2259 emit_label (hi0_label
);
2261 temp
= expand_unop_direct (word_mode
, clz_optab
, sublo
, 0, true);
2264 temp
= expand_binop (word_mode
, add_optab
, temp
,
2265 gen_int_mode (GET_MODE_BITSIZE (word_mode
), word_mode
),
2266 result
, true, OPTAB_DIRECT
);
2270 convert_move (result
, temp
, true);
2272 emit_label (after_label
);
2273 convert_move (target
, result
, true);
2278 add_equal_note (seq
, target
, CLZ
, xop0
, 0);
2287 /* Try calculating popcount of a double-word quantity as two popcount's of
2288 word-sized quantities and summing up the results. */
2290 expand_doubleword_popcount (scalar_int_mode mode
, rtx op0
, rtx target
)
2297 t0
= expand_unop_direct (word_mode
, popcount_optab
,
2298 operand_subword_force (op0
, 0, mode
), NULL_RTX
,
2300 t1
= expand_unop_direct (word_mode
, popcount_optab
,
2301 operand_subword_force (op0
, 1, mode
), NULL_RTX
,
2309 /* If we were not given a target, use a word_mode register, not a
2310 'mode' register. The result will fit, and nobody is expecting
2311 anything bigger (the return type of __builtin_popcount* is int). */
2313 target
= gen_reg_rtx (word_mode
);
2315 t
= expand_binop (word_mode
, add_optab
, t0
, t1
, target
, 0, OPTAB_DIRECT
);
2320 add_equal_note (seq
, t
, POPCOUNT
, op0
, 0);
2328 (parity:narrow (low (x) ^ high (x))) */
2330 expand_doubleword_parity (scalar_int_mode mode
, rtx op0
, rtx target
)
2332 rtx t
= expand_binop (word_mode
, xor_optab
,
2333 operand_subword_force (op0
, 0, mode
),
2334 operand_subword_force (op0
, 1, mode
),
2335 NULL_RTX
, 0, OPTAB_DIRECT
);
2336 return expand_unop (word_mode
, parity_optab
, t
, target
, true);
2342 (lshiftrt:wide (bswap:wide x) ((width wide) - (width narrow))). */
2344 widen_bswap (scalar_int_mode mode
, rtx op0
, rtx target
)
2348 opt_scalar_int_mode wider_mode_iter
;
2350 FOR_EACH_WIDER_MODE (wider_mode_iter
, mode
)
2351 if (optab_handler (bswap_optab
, wider_mode_iter
.require ())
2352 != CODE_FOR_nothing
)
2355 if (!wider_mode_iter
.exists ())
2358 scalar_int_mode wider_mode
= wider_mode_iter
.require ();
2359 last
= get_last_insn ();
2361 x
= widen_operand (op0
, wider_mode
, mode
, true, true);
2362 x
= expand_unop (wider_mode
, bswap_optab
, x
, NULL_RTX
, true);
2364 gcc_assert (GET_MODE_PRECISION (wider_mode
) == GET_MODE_BITSIZE (wider_mode
)
2365 && GET_MODE_PRECISION (mode
) == GET_MODE_BITSIZE (mode
));
2367 x
= expand_shift (RSHIFT_EXPR
, wider_mode
, x
,
2368 GET_MODE_BITSIZE (wider_mode
)
2369 - GET_MODE_BITSIZE (mode
),
2375 target
= gen_reg_rtx (mode
);
2376 emit_move_insn (target
, gen_lowpart (mode
, x
));
2379 delete_insns_since (last
);
2384 /* Try calculating bswap as two bswaps of two word-sized operands. */
2387 expand_doubleword_bswap (machine_mode mode
, rtx op
, rtx target
)
2391 t1
= expand_unop (word_mode
, bswap_optab
,
2392 operand_subword_force (op
, 0, mode
), NULL_RTX
, true);
2393 t0
= expand_unop (word_mode
, bswap_optab
,
2394 operand_subword_force (op
, 1, mode
), NULL_RTX
, true);
2396 if (target
== 0 || !valid_multiword_target_p (target
))
2397 target
= gen_reg_rtx (mode
);
2399 emit_clobber (target
);
2400 emit_move_insn (operand_subword (target
, 0, 1, mode
), t0
);
2401 emit_move_insn (operand_subword (target
, 1, 1, mode
), t1
);
2406 /* Try calculating (parity x) as (and (popcount x) 1), where
2407 popcount can also be done in a wider mode. */
2409 expand_parity (scalar_int_mode mode
, rtx op0
, rtx target
)
2411 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2412 opt_scalar_int_mode wider_mode_iter
;
2413 FOR_EACH_MODE_FROM (wider_mode_iter
, mode
)
2415 scalar_int_mode wider_mode
= wider_mode_iter
.require ();
2416 if (optab_handler (popcount_optab
, wider_mode
) != CODE_FOR_nothing
)
2421 last
= get_last_insn ();
2423 if (target
== 0 || GET_MODE (target
) != wider_mode
)
2424 target
= gen_reg_rtx (wider_mode
);
2426 xop0
= widen_operand (op0
, wider_mode
, mode
, true, false);
2427 temp
= expand_unop (wider_mode
, popcount_optab
, xop0
, NULL_RTX
,
2430 temp
= expand_binop (wider_mode
, and_optab
, temp
, const1_rtx
,
2431 target
, true, OPTAB_DIRECT
);
2435 if (mclass
!= MODE_INT
2436 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
2437 return convert_to_mode (mode
, temp
, 0);
2439 return gen_lowpart (mode
, temp
);
2442 delete_insns_since (last
);
2448 /* Try calculating ctz(x) as K - clz(x & -x) ,
2449 where K is GET_MODE_PRECISION(mode) - 1.
2451 Both __builtin_ctz and __builtin_clz are undefined at zero, so we
2452 don't have to worry about what the hardware does in that case. (If
2453 the clz instruction produces the usual value at 0, which is K, the
2454 result of this code sequence will be -1; expand_ffs, below, relies
2455 on this. It might be nice to have it be K instead, for consistency
2456 with the (very few) processors that provide a ctz with a defined
2457 value, but that would take one more instruction, and it would be
2458 less convenient for expand_ffs anyway. */
2461 expand_ctz (scalar_int_mode mode
, rtx op0
, rtx target
)
2466 if (optab_handler (clz_optab
, mode
) == CODE_FOR_nothing
)
2471 temp
= expand_unop_direct (mode
, neg_optab
, op0
, NULL_RTX
, true);
2473 temp
= expand_binop (mode
, and_optab
, op0
, temp
, NULL_RTX
,
2474 true, OPTAB_DIRECT
);
2476 temp
= expand_unop_direct (mode
, clz_optab
, temp
, NULL_RTX
, true);
2478 temp
= expand_binop (mode
, sub_optab
,
2479 gen_int_mode (GET_MODE_PRECISION (mode
) - 1, mode
),
2481 true, OPTAB_DIRECT
);
2491 add_equal_note (seq
, temp
, CTZ
, op0
, 0);
2497 /* Try calculating ffs(x) using ctz(x) if we have that instruction, or
2498 else with the sequence used by expand_clz.
2500 The ffs builtin promises to return zero for a zero value and ctz/clz
2501 may have an undefined value in that case. If they do not give us a
2502 convenient value, we have to generate a test and branch. */
2504 expand_ffs (scalar_int_mode mode
, rtx op0
, rtx target
)
2506 HOST_WIDE_INT val
= 0;
2507 bool defined_at_zero
= false;
2511 if (optab_handler (ctz_optab
, mode
) != CODE_FOR_nothing
)
2515 temp
= expand_unop_direct (mode
, ctz_optab
, op0
, 0, true);
2519 defined_at_zero
= (CTZ_DEFINED_VALUE_AT_ZERO (mode
, val
) == 2);
2521 else if (optab_handler (clz_optab
, mode
) != CODE_FOR_nothing
)
2524 temp
= expand_ctz (mode
, op0
, 0);
2528 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, val
) == 2)
2530 defined_at_zero
= true;
2531 val
= (GET_MODE_PRECISION (mode
) - 1) - val
;
2537 if (defined_at_zero
&& val
== -1)
2538 /* No correction needed at zero. */;
2541 /* We don't try to do anything clever with the situation found
2542 on some processors (eg Alpha) where ctz(0:mode) ==
2543 bitsize(mode). If someone can think of a way to send N to -1
2544 and leave alone all values in the range 0..N-1 (where N is a
2545 power of two), cheaper than this test-and-branch, please add it.
2547 The test-and-branch is done after the operation itself, in case
2548 the operation sets condition codes that can be recycled for this.
2549 (This is true on i386, for instance.) */
2551 rtx_code_label
*nonzero_label
= gen_label_rtx ();
2552 emit_cmp_and_jump_insns (op0
, CONST0_RTX (mode
), NE
, 0,
2553 mode
, true, nonzero_label
);
2555 convert_move (temp
, GEN_INT (-1), false);
2556 emit_label (nonzero_label
);
2559 /* temp now has a value in the range -1..bitsize-1. ffs is supposed
2560 to produce a value in the range 0..bitsize. */
2561 temp
= expand_binop (mode
, add_optab
, temp
, gen_int_mode (1, mode
),
2562 target
, false, OPTAB_DIRECT
);
2569 add_equal_note (seq
, temp
, FFS
, op0
, 0);
2578 /* Extract the OMODE lowpart from VAL, which has IMODE. Under certain
2579 conditions, VAL may already be a SUBREG against which we cannot generate
2580 a further SUBREG. In this case, we expect forcing the value into a
2581 register will work around the situation. */
2584 lowpart_subreg_maybe_copy (machine_mode omode
, rtx val
,
2588 ret
= lowpart_subreg (omode
, val
, imode
);
2591 val
= force_reg (imode
, val
);
2592 ret
= lowpart_subreg (omode
, val
, imode
);
2593 gcc_assert (ret
!= NULL
);
2598 /* Expand a floating point absolute value or negation operation via a
2599 logical operation on the sign bit. */
2602 expand_absneg_bit (enum rtx_code code
, scalar_float_mode mode
,
2603 rtx op0
, rtx target
)
2605 const struct real_format
*fmt
;
2606 int bitpos
, word
, nwords
, i
;
2607 scalar_int_mode imode
;
2611 /* The format has to have a simple sign bit. */
2612 fmt
= REAL_MODE_FORMAT (mode
);
2616 bitpos
= fmt
->signbit_rw
;
2620 /* Don't create negative zeros if the format doesn't support them. */
2621 if (code
== NEG
&& !fmt
->has_signed_zero
)
2624 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
2626 if (!int_mode_for_mode (mode
).exists (&imode
))
2635 if (FLOAT_WORDS_BIG_ENDIAN
)
2636 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
2638 word
= bitpos
/ BITS_PER_WORD
;
2639 bitpos
= bitpos
% BITS_PER_WORD
;
2640 nwords
= (GET_MODE_BITSIZE (mode
) + BITS_PER_WORD
- 1) / BITS_PER_WORD
;
2643 wide_int mask
= wi::set_bit_in_zero (bitpos
, GET_MODE_PRECISION (imode
));
2649 || (nwords
> 1 && !valid_multiword_target_p (target
)))
2650 target
= gen_reg_rtx (mode
);
2656 for (i
= 0; i
< nwords
; ++i
)
2658 rtx targ_piece
= operand_subword (target
, i
, 1, mode
);
2659 rtx op0_piece
= operand_subword_force (op0
, i
, mode
);
2663 temp
= expand_binop (imode
, code
== ABS
? and_optab
: xor_optab
,
2665 immed_wide_int_const (mask
, imode
),
2666 targ_piece
, 1, OPTAB_LIB_WIDEN
);
2667 if (temp
!= targ_piece
)
2668 emit_move_insn (targ_piece
, temp
);
2671 emit_move_insn (targ_piece
, op0_piece
);
2674 insns
= get_insns ();
2681 temp
= expand_binop (imode
, code
== ABS
? and_optab
: xor_optab
,
2682 gen_lowpart (imode
, op0
),
2683 immed_wide_int_const (mask
, imode
),
2684 gen_lowpart (imode
, target
), 1, OPTAB_LIB_WIDEN
);
2685 target
= lowpart_subreg_maybe_copy (mode
, temp
, imode
);
2687 set_dst_reg_note (get_last_insn (), REG_EQUAL
,
2688 gen_rtx_fmt_e (code
, mode
, copy_rtx (op0
)),
2695 /* As expand_unop, but will fail rather than attempt the operation in a
2696 different mode or with a libcall. */
2698 expand_unop_direct (machine_mode mode
, optab unoptab
, rtx op0
, rtx target
,
2701 if (optab_handler (unoptab
, mode
) != CODE_FOR_nothing
)
2703 struct expand_operand ops
[2];
2704 enum insn_code icode
= optab_handler (unoptab
, mode
);
2705 rtx_insn
*last
= get_last_insn ();
2708 create_output_operand (&ops
[0], target
, mode
);
2709 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
2710 pat
= maybe_gen_insn (icode
, 2, ops
);
2713 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
2714 && ! add_equal_note (pat
, ops
[0].value
,
2715 optab_to_code (unoptab
),
2716 ops
[1].value
, NULL_RTX
))
2718 delete_insns_since (last
);
2719 return expand_unop (mode
, unoptab
, op0
, NULL_RTX
, unsignedp
);
2724 return ops
[0].value
;
2730 /* Generate code to perform an operation specified by UNOPTAB
2731 on operand OP0, with result having machine-mode MODE.
2733 UNSIGNEDP is for the case where we have to widen the operands
2734 to perform the operation. It says to use zero-extension.
2736 If TARGET is nonzero, the value
2737 is generated there, if it is convenient to do so.
2738 In all cases an rtx is returned for the locus of the value;
2739 this may or may not be TARGET. */
2742 expand_unop (machine_mode mode
, optab unoptab
, rtx op0
, rtx target
,
2745 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2746 machine_mode wider_mode
;
2747 scalar_int_mode int_mode
;
2748 scalar_float_mode float_mode
;
2752 temp
= expand_unop_direct (mode
, unoptab
, op0
, target
, unsignedp
);
2756 /* It can't be done in this mode. Can we open-code it in a wider mode? */
2758 /* Widening (or narrowing) clz needs special treatment. */
2759 if (unoptab
== clz_optab
)
2761 if (is_a
<scalar_int_mode
> (mode
, &int_mode
))
2763 temp
= widen_leading (int_mode
, op0
, target
, unoptab
);
2767 if (GET_MODE_SIZE (int_mode
) == 2 * UNITS_PER_WORD
2768 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
2770 temp
= expand_doubleword_clz (int_mode
, op0
, target
);
2779 if (unoptab
== clrsb_optab
)
2781 if (is_a
<scalar_int_mode
> (mode
, &int_mode
))
2783 temp
= widen_leading (int_mode
, op0
, target
, unoptab
);
2790 if (unoptab
== popcount_optab
2791 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
2792 && GET_MODE_SIZE (int_mode
) == 2 * UNITS_PER_WORD
2793 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
2794 && optimize_insn_for_speed_p ())
2796 temp
= expand_doubleword_popcount (int_mode
, op0
, target
);
2801 if (unoptab
== parity_optab
2802 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
2803 && GET_MODE_SIZE (int_mode
) == 2 * UNITS_PER_WORD
2804 && (optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
2805 || optab_handler (popcount_optab
, word_mode
) != CODE_FOR_nothing
)
2806 && optimize_insn_for_speed_p ())
2808 temp
= expand_doubleword_parity (int_mode
, op0
, target
);
2813 /* Widening (or narrowing) bswap needs special treatment. */
2814 if (unoptab
== bswap_optab
)
2816 /* HImode is special because in this mode BSWAP is equivalent to ROTATE
2817 or ROTATERT. First try these directly; if this fails, then try the
2818 obvious pair of shifts with allowed widening, as this will probably
2819 be always more efficient than the other fallback methods. */
2825 if (optab_handler (rotl_optab
, mode
) != CODE_FOR_nothing
)
2827 temp
= expand_binop (mode
, rotl_optab
, op0
,
2828 gen_int_shift_amount (mode
, 8),
2829 target
, unsignedp
, OPTAB_DIRECT
);
2834 if (optab_handler (rotr_optab
, mode
) != CODE_FOR_nothing
)
2836 temp
= expand_binop (mode
, rotr_optab
, op0
,
2837 gen_int_shift_amount (mode
, 8),
2838 target
, unsignedp
, OPTAB_DIRECT
);
2843 last
= get_last_insn ();
2845 temp1
= expand_binop (mode
, ashl_optab
, op0
,
2846 gen_int_shift_amount (mode
, 8), NULL_RTX
,
2847 unsignedp
, OPTAB_WIDEN
);
2848 temp2
= expand_binop (mode
, lshr_optab
, op0
,
2849 gen_int_shift_amount (mode
, 8), NULL_RTX
,
2850 unsignedp
, OPTAB_WIDEN
);
2853 temp
= expand_binop (mode
, ior_optab
, temp1
, temp2
, target
,
2854 unsignedp
, OPTAB_WIDEN
);
2859 delete_insns_since (last
);
2862 if (is_a
<scalar_int_mode
> (mode
, &int_mode
))
2864 temp
= widen_bswap (int_mode
, op0
, target
);
2868 if (GET_MODE_SIZE (int_mode
) == 2 * UNITS_PER_WORD
2869 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
2871 temp
= expand_doubleword_bswap (mode
, op0
, target
);
2880 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2881 FOR_EACH_WIDER_MODE (wider_mode
, mode
)
2883 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
2886 rtx_insn
*last
= get_last_insn ();
2888 /* For certain operations, we need not actually extend
2889 the narrow operand, as long as we will truncate the
2890 results to the same narrowness. */
2892 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
2893 (unoptab
== neg_optab
2894 || unoptab
== one_cmpl_optab
)
2895 && mclass
== MODE_INT
);
2897 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
2902 if (mclass
!= MODE_INT
2903 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
2906 target
= gen_reg_rtx (mode
);
2907 convert_move (target
, temp
, 0);
2911 return gen_lowpart (mode
, temp
);
2914 delete_insns_since (last
);
2918 /* These can be done a word at a time. */
2919 if (unoptab
== one_cmpl_optab
2920 && is_int_mode (mode
, &int_mode
)
2921 && GET_MODE_SIZE (int_mode
) > UNITS_PER_WORD
2922 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
2927 if (target
== 0 || target
== op0
|| !valid_multiword_target_p (target
))
2928 target
= gen_reg_rtx (int_mode
);
2932 /* Do the actual arithmetic. */
2933 for (i
= 0; i
< GET_MODE_BITSIZE (int_mode
) / BITS_PER_WORD
; i
++)
2935 rtx target_piece
= operand_subword (target
, i
, 1, int_mode
);
2936 rtx x
= expand_unop (word_mode
, unoptab
,
2937 operand_subword_force (op0
, i
, int_mode
),
2938 target_piece
, unsignedp
);
2940 if (target_piece
!= x
)
2941 emit_move_insn (target_piece
, x
);
2944 insns
= get_insns ();
2951 if (optab_to_code (unoptab
) == NEG
)
2953 /* Try negating floating point values by flipping the sign bit. */
2954 if (is_a
<scalar_float_mode
> (mode
, &float_mode
))
2956 temp
= expand_absneg_bit (NEG
, float_mode
, op0
, target
);
2961 /* If there is no negation pattern, and we have no negative zero,
2962 try subtracting from zero. */
2963 if (!HONOR_SIGNED_ZEROS (mode
))
2965 temp
= expand_binop (mode
, (unoptab
== negv_optab
2966 ? subv_optab
: sub_optab
),
2967 CONST0_RTX (mode
), op0
, target
,
2968 unsignedp
, OPTAB_DIRECT
);
2974 /* Try calculating parity (x) as popcount (x) % 2. */
2975 if (unoptab
== parity_optab
&& is_a
<scalar_int_mode
> (mode
, &int_mode
))
2977 temp
= expand_parity (int_mode
, op0
, target
);
2982 /* Try implementing ffs (x) in terms of clz (x). */
2983 if (unoptab
== ffs_optab
&& is_a
<scalar_int_mode
> (mode
, &int_mode
))
2985 temp
= expand_ffs (int_mode
, op0
, target
);
2990 /* Try implementing ctz (x) in terms of clz (x). */
2991 if (unoptab
== ctz_optab
&& is_a
<scalar_int_mode
> (mode
, &int_mode
))
2993 temp
= expand_ctz (int_mode
, op0
, target
);
2999 /* Now try a library call in this mode. */
3000 libfunc
= optab_libfunc (unoptab
, mode
);
3006 machine_mode outmode
= mode
;
3008 /* All of these functions return small values. Thus we choose to
3009 have them return something that isn't a double-word. */
3010 if (unoptab
== ffs_optab
|| unoptab
== clz_optab
|| unoptab
== ctz_optab
3011 || unoptab
== clrsb_optab
|| unoptab
== popcount_optab
3012 || unoptab
== parity_optab
)
3014 = GET_MODE (hard_libcall_value (TYPE_MODE (integer_type_node
),
3015 optab_libfunc (unoptab
, mode
)));
3019 /* Pass 1 for NO_QUEUE so we don't lose any increments
3020 if the libcall is cse'd or moved. */
3021 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
, outmode
,
3023 insns
= get_insns ();
3026 target
= gen_reg_rtx (outmode
);
3027 bool trapv
= trapv_unoptab_p (unoptab
);
3029 eq_value
= NULL_RTX
;
3032 eq_value
= gen_rtx_fmt_e (optab_to_code (unoptab
), mode
, op0
);
3033 if (GET_MODE_UNIT_SIZE (outmode
) < GET_MODE_UNIT_SIZE (mode
))
3034 eq_value
= simplify_gen_unary (TRUNCATE
, outmode
, eq_value
, mode
);
3035 else if (GET_MODE_UNIT_SIZE (outmode
) > GET_MODE_UNIT_SIZE (mode
))
3036 eq_value
= simplify_gen_unary (ZERO_EXTEND
,
3037 outmode
, eq_value
, mode
);
3039 emit_libcall_block_1 (insns
, target
, value
, eq_value
, trapv
);
3044 /* It can't be done in this mode. Can we do it in a wider mode? */
3046 if (CLASS_HAS_WIDER_MODES_P (mclass
))
3048 FOR_EACH_WIDER_MODE (wider_mode
, mode
)
3050 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
3051 || optab_libfunc (unoptab
, wider_mode
))
3054 rtx_insn
*last
= get_last_insn ();
3056 /* For certain operations, we need not actually extend
3057 the narrow operand, as long as we will truncate the
3058 results to the same narrowness. */
3059 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
3060 (unoptab
== neg_optab
3061 || unoptab
== one_cmpl_optab
3062 || unoptab
== bswap_optab
)
3063 && mclass
== MODE_INT
);
3065 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
3068 /* If we are generating clz using wider mode, adjust the
3069 result. Similarly for clrsb. */
3070 if ((unoptab
== clz_optab
|| unoptab
== clrsb_optab
)
3073 scalar_int_mode wider_int_mode
3074 = as_a
<scalar_int_mode
> (wider_mode
);
3075 int_mode
= as_a
<scalar_int_mode
> (mode
);
3077 (wider_mode
, sub_optab
, temp
,
3078 gen_int_mode (GET_MODE_PRECISION (wider_int_mode
)
3079 - GET_MODE_PRECISION (int_mode
),
3081 target
, true, OPTAB_DIRECT
);
3084 /* Likewise for bswap. */
3085 if (unoptab
== bswap_optab
&& temp
!= 0)
3087 scalar_int_mode wider_int_mode
3088 = as_a
<scalar_int_mode
> (wider_mode
);
3089 int_mode
= as_a
<scalar_int_mode
> (mode
);
3090 gcc_assert (GET_MODE_PRECISION (wider_int_mode
)
3091 == GET_MODE_BITSIZE (wider_int_mode
)
3092 && GET_MODE_PRECISION (int_mode
)
3093 == GET_MODE_BITSIZE (int_mode
));
3095 temp
= expand_shift (RSHIFT_EXPR
, wider_int_mode
, temp
,
3096 GET_MODE_BITSIZE (wider_int_mode
)
3097 - GET_MODE_BITSIZE (int_mode
),
3103 if (mclass
!= MODE_INT
)
3106 target
= gen_reg_rtx (mode
);
3107 convert_move (target
, temp
, 0);
3111 return gen_lowpart (mode
, temp
);
3114 delete_insns_since (last
);
3119 /* One final attempt at implementing negation via subtraction,
3120 this time allowing widening of the operand. */
3121 if (optab_to_code (unoptab
) == NEG
&& !HONOR_SIGNED_ZEROS (mode
))
3124 temp
= expand_binop (mode
,
3125 unoptab
== negv_optab
? subv_optab
: sub_optab
,
3126 CONST0_RTX (mode
), op0
,
3127 target
, unsignedp
, OPTAB_LIB_WIDEN
);
3135 /* Emit code to compute the absolute value of OP0, with result to
3136 TARGET if convenient. (TARGET may be 0.) The return value says
3137 where the result actually is to be found.
3139 MODE is the mode of the operand; the mode of the result is
3140 different but can be deduced from MODE.
3145 expand_abs_nojump (machine_mode mode
, rtx op0
, rtx target
,
3146 int result_unsignedp
)
3150 if (GET_MODE_CLASS (mode
) != MODE_INT
3152 result_unsignedp
= 1;
3154 /* First try to do it with a special abs instruction. */
3155 temp
= expand_unop (mode
, result_unsignedp
? abs_optab
: absv_optab
,
3160 /* For floating point modes, try clearing the sign bit. */
3161 scalar_float_mode float_mode
;
3162 if (is_a
<scalar_float_mode
> (mode
, &float_mode
))
3164 temp
= expand_absneg_bit (ABS
, float_mode
, op0
, target
);
3169 /* If we have a MAX insn, we can do this as MAX (x, -x). */
3170 if (optab_handler (smax_optab
, mode
) != CODE_FOR_nothing
3171 && !HONOR_SIGNED_ZEROS (mode
))
3173 rtx_insn
*last
= get_last_insn ();
3175 temp
= expand_unop (mode
, result_unsignedp
? neg_optab
: negv_optab
,
3178 temp
= expand_binop (mode
, smax_optab
, op0
, temp
, target
, 0,
3184 delete_insns_since (last
);
3187 /* If this machine has expensive jumps, we can do integer absolute
3188 value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)),
3189 where W is the width of MODE. */
3191 scalar_int_mode int_mode
;
3192 if (is_int_mode (mode
, &int_mode
)
3193 && BRANCH_COST (optimize_insn_for_speed_p (),
3196 rtx extended
= expand_shift (RSHIFT_EXPR
, int_mode
, op0
,
3197 GET_MODE_PRECISION (int_mode
) - 1,
3200 temp
= expand_binop (int_mode
, xor_optab
, extended
, op0
, target
, 0,
3203 temp
= expand_binop (int_mode
,
3204 result_unsignedp
? sub_optab
: subv_optab
,
3205 temp
, extended
, target
, 0, OPTAB_LIB_WIDEN
);
3215 expand_abs (machine_mode mode
, rtx op0
, rtx target
,
3216 int result_unsignedp
, int safe
)
3219 rtx_code_label
*op1
;
3221 if (GET_MODE_CLASS (mode
) != MODE_INT
3223 result_unsignedp
= 1;
3225 temp
= expand_abs_nojump (mode
, op0
, target
, result_unsignedp
);
3229 /* If that does not win, use conditional jump and negate. */
3231 /* It is safe to use the target if it is the same
3232 as the source if this is also a pseudo register */
3233 if (op0
== target
&& REG_P (op0
)
3234 && REGNO (op0
) >= FIRST_PSEUDO_REGISTER
)
3237 op1
= gen_label_rtx ();
3238 if (target
== 0 || ! safe
3239 || GET_MODE (target
) != mode
3240 || (MEM_P (target
) && MEM_VOLATILE_P (target
))
3242 && REGNO (target
) < FIRST_PSEUDO_REGISTER
))
3243 target
= gen_reg_rtx (mode
);
3245 emit_move_insn (target
, op0
);
3248 do_compare_rtx_and_jump (target
, CONST0_RTX (mode
), GE
, 0, mode
,
3249 NULL_RTX
, NULL
, op1
,
3250 profile_probability::uninitialized ());
3252 op0
= expand_unop (mode
, result_unsignedp
? neg_optab
: negv_optab
,
3255 emit_move_insn (target
, op0
);
3261 /* Emit code to compute the one's complement absolute value of OP0
3262 (if (OP0 < 0) OP0 = ~OP0), with result to TARGET if convenient.
3263 (TARGET may be NULL_RTX.) The return value says where the result
3264 actually is to be found.
3266 MODE is the mode of the operand; the mode of the result is
3267 different but can be deduced from MODE. */
3270 expand_one_cmpl_abs_nojump (machine_mode mode
, rtx op0
, rtx target
)
3274 /* Not applicable for floating point modes. */
3275 if (FLOAT_MODE_P (mode
))
3278 /* If we have a MAX insn, we can do this as MAX (x, ~x). */
3279 if (optab_handler (smax_optab
, mode
) != CODE_FOR_nothing
)
3281 rtx_insn
*last
= get_last_insn ();
3283 temp
= expand_unop (mode
, one_cmpl_optab
, op0
, NULL_RTX
, 0);
3285 temp
= expand_binop (mode
, smax_optab
, op0
, temp
, target
, 0,
3291 delete_insns_since (last
);
3294 /* If this machine has expensive jumps, we can do one's complement
3295 absolute value of X as (((signed) x >> (W-1)) ^ x). */
3297 scalar_int_mode int_mode
;
3298 if (is_int_mode (mode
, &int_mode
)
3299 && BRANCH_COST (optimize_insn_for_speed_p (),
3302 rtx extended
= expand_shift (RSHIFT_EXPR
, int_mode
, op0
,
3303 GET_MODE_PRECISION (int_mode
) - 1,
3306 temp
= expand_binop (int_mode
, xor_optab
, extended
, op0
, target
, 0,
3316 /* A subroutine of expand_copysign, perform the copysign operation using the
3317 abs and neg primitives advertised to exist on the target. The assumption
3318 is that we have a split register file, and leaving op0 in fp registers,
3319 and not playing with subregs so much, will help the register allocator. */
3322 expand_copysign_absneg (scalar_float_mode mode
, rtx op0
, rtx op1
, rtx target
,
3323 int bitpos
, bool op0_is_abs
)
3325 scalar_int_mode imode
;
3326 enum insn_code icode
;
3328 rtx_code_label
*label
;
3333 /* Check if the back end provides an insn that handles signbit for the
3335 icode
= optab_handler (signbit_optab
, mode
);
3336 if (icode
!= CODE_FOR_nothing
)
3338 imode
= as_a
<scalar_int_mode
> (insn_data
[(int) icode
].operand
[0].mode
);
3339 sign
= gen_reg_rtx (imode
);
3340 emit_unop_insn (icode
, sign
, op1
, UNKNOWN
);
3344 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
3346 if (!int_mode_for_mode (mode
).exists (&imode
))
3348 op1
= gen_lowpart (imode
, op1
);
3355 if (FLOAT_WORDS_BIG_ENDIAN
)
3356 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
3358 word
= bitpos
/ BITS_PER_WORD
;
3359 bitpos
= bitpos
% BITS_PER_WORD
;
3360 op1
= operand_subword_force (op1
, word
, mode
);
3363 wide_int mask
= wi::set_bit_in_zero (bitpos
, GET_MODE_PRECISION (imode
));
3364 sign
= expand_binop (imode
, and_optab
, op1
,
3365 immed_wide_int_const (mask
, imode
),
3366 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3371 op0
= expand_unop (mode
, abs_optab
, op0
, target
, 0);
3378 if (target
== NULL_RTX
)
3379 target
= copy_to_reg (op0
);
3381 emit_move_insn (target
, op0
);
3384 label
= gen_label_rtx ();
3385 emit_cmp_and_jump_insns (sign
, const0_rtx
, EQ
, NULL_RTX
, imode
, 1, label
);
3387 if (CONST_DOUBLE_AS_FLOAT_P (op0
))
3388 op0
= simplify_unary_operation (NEG
, mode
, op0
, mode
);
3390 op0
= expand_unop (mode
, neg_optab
, op0
, target
, 0);
3392 emit_move_insn (target
, op0
);
3400 /* A subroutine of expand_copysign, perform the entire copysign operation
3401 with integer bitmasks. BITPOS is the position of the sign bit; OP0_IS_ABS
3402 is true if op0 is known to have its sign bit clear. */
3405 expand_copysign_bit (scalar_float_mode mode
, rtx op0
, rtx op1
, rtx target
,
3406 int bitpos
, bool op0_is_abs
)
3408 scalar_int_mode imode
;
3409 int word
, nwords
, i
;
3413 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
3415 if (!int_mode_for_mode (mode
).exists (&imode
))
3424 if (FLOAT_WORDS_BIG_ENDIAN
)
3425 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
3427 word
= bitpos
/ BITS_PER_WORD
;
3428 bitpos
= bitpos
% BITS_PER_WORD
;
3429 nwords
= (GET_MODE_BITSIZE (mode
) + BITS_PER_WORD
- 1) / BITS_PER_WORD
;
3432 wide_int mask
= wi::set_bit_in_zero (bitpos
, GET_MODE_PRECISION (imode
));
3437 || (nwords
> 1 && !valid_multiword_target_p (target
)))
3438 target
= gen_reg_rtx (mode
);
3444 for (i
= 0; i
< nwords
; ++i
)
3446 rtx targ_piece
= operand_subword (target
, i
, 1, mode
);
3447 rtx op0_piece
= operand_subword_force (op0
, i
, mode
);
3453 = expand_binop (imode
, and_optab
, op0_piece
,
3454 immed_wide_int_const (~mask
, imode
),
3455 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3456 op1
= expand_binop (imode
, and_optab
,
3457 operand_subword_force (op1
, i
, mode
),
3458 immed_wide_int_const (mask
, imode
),
3459 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3461 temp
= expand_binop (imode
, ior_optab
, op0_piece
, op1
,
3462 targ_piece
, 1, OPTAB_LIB_WIDEN
);
3463 if (temp
!= targ_piece
)
3464 emit_move_insn (targ_piece
, temp
);
3467 emit_move_insn (targ_piece
, op0_piece
);
3470 insns
= get_insns ();
3477 op1
= expand_binop (imode
, and_optab
, gen_lowpart (imode
, op1
),
3478 immed_wide_int_const (mask
, imode
),
3479 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3481 op0
= gen_lowpart (imode
, op0
);
3483 op0
= expand_binop (imode
, and_optab
, op0
,
3484 immed_wide_int_const (~mask
, imode
),
3485 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3487 temp
= expand_binop (imode
, ior_optab
, op0
, op1
,
3488 gen_lowpart (imode
, target
), 1, OPTAB_LIB_WIDEN
);
3489 target
= lowpart_subreg_maybe_copy (mode
, temp
, imode
);
3495 /* Expand the C99 copysign operation. OP0 and OP1 must be the same
3496 scalar floating point mode. Return NULL if we do not know how to
3497 expand the operation inline. */
3500 expand_copysign (rtx op0
, rtx op1
, rtx target
)
3502 scalar_float_mode mode
;
3503 const struct real_format
*fmt
;
3507 mode
= as_a
<scalar_float_mode
> (GET_MODE (op0
));
3508 gcc_assert (GET_MODE (op1
) == mode
);
3510 /* First try to do it with a special instruction. */
3511 temp
= expand_binop (mode
, copysign_optab
, op0
, op1
,
3512 target
, 0, OPTAB_DIRECT
);
3516 fmt
= REAL_MODE_FORMAT (mode
);
3517 if (fmt
== NULL
|| !fmt
->has_signed_zero
)
3521 if (CONST_DOUBLE_AS_FLOAT_P (op0
))
3523 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0
)))
3524 op0
= simplify_unary_operation (ABS
, mode
, op0
, mode
);
3528 if (fmt
->signbit_ro
>= 0
3529 && (CONST_DOUBLE_AS_FLOAT_P (op0
)
3530 || (optab_handler (neg_optab
, mode
) != CODE_FOR_nothing
3531 && optab_handler (abs_optab
, mode
) != CODE_FOR_nothing
)))
3533 temp
= expand_copysign_absneg (mode
, op0
, op1
, target
,
3534 fmt
->signbit_ro
, op0_is_abs
);
3539 if (fmt
->signbit_rw
< 0)
3541 return expand_copysign_bit (mode
, op0
, op1
, target
,
3542 fmt
->signbit_rw
, op0_is_abs
);
3545 /* Generate an instruction whose insn-code is INSN_CODE,
3546 with two operands: an output TARGET and an input OP0.
3547 TARGET *must* be nonzero, and the output is always stored there.
3548 CODE is an rtx code such that (CODE OP0) is an rtx that describes
3549 the value that is stored into TARGET.
3551 Return false if expansion failed. */
3554 maybe_emit_unop_insn (enum insn_code icode
, rtx target
, rtx op0
,
3557 struct expand_operand ops
[2];
3560 create_output_operand (&ops
[0], target
, GET_MODE (target
));
3561 create_input_operand (&ops
[1], op0
, GET_MODE (op0
));
3562 pat
= maybe_gen_insn (icode
, 2, ops
);
3566 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
3568 add_equal_note (pat
, ops
[0].value
, code
, ops
[1].value
, NULL_RTX
);
3572 if (ops
[0].value
!= target
)
3573 emit_move_insn (target
, ops
[0].value
);
3576 /* Generate an instruction whose insn-code is INSN_CODE,
3577 with two operands: an output TARGET and an input OP0.
3578 TARGET *must* be nonzero, and the output is always stored there.
3579 CODE is an rtx code such that (CODE OP0) is an rtx that describes
3580 the value that is stored into TARGET. */
3583 emit_unop_insn (enum insn_code icode
, rtx target
, rtx op0
, enum rtx_code code
)
3585 bool ok
= maybe_emit_unop_insn (icode
, target
, op0
, code
);
3589 struct no_conflict_data
3592 rtx_insn
*first
, *insn
;
3596 /* Called via note_stores by emit_libcall_block. Set P->must_stay if
3597 the currently examined clobber / store has to stay in the list of
3598 insns that constitute the actual libcall block. */
3600 no_conflict_move_test (rtx dest
, const_rtx set
, void *p0
)
3602 struct no_conflict_data
*p
= (struct no_conflict_data
*) p0
;
3604 /* If this inns directly contributes to setting the target, it must stay. */
3605 if (reg_overlap_mentioned_p (p
->target
, dest
))
3606 p
->must_stay
= true;
3607 /* If we haven't committed to keeping any other insns in the list yet,
3608 there is nothing more to check. */
3609 else if (p
->insn
== p
->first
)
3611 /* If this insn sets / clobbers a register that feeds one of the insns
3612 already in the list, this insn has to stay too. */
3613 else if (reg_overlap_mentioned_p (dest
, PATTERN (p
->first
))
3614 || (CALL_P (p
->first
) && (find_reg_fusage (p
->first
, USE
, dest
)))
3615 || reg_used_between_p (dest
, p
->first
, p
->insn
)
3616 /* Likewise if this insn depends on a register set by a previous
3617 insn in the list, or if it sets a result (presumably a hard
3618 register) that is set or clobbered by a previous insn.
3619 N.B. the modified_*_p (SET_DEST...) tests applied to a MEM
3620 SET_DEST perform the former check on the address, and the latter
3621 check on the MEM. */
3622 || (GET_CODE (set
) == SET
3623 && (modified_in_p (SET_SRC (set
), p
->first
)
3624 || modified_in_p (SET_DEST (set
), p
->first
)
3625 || modified_between_p (SET_SRC (set
), p
->first
, p
->insn
)
3626 || modified_between_p (SET_DEST (set
), p
->first
, p
->insn
))))
3627 p
->must_stay
= true;
3631 /* Emit code to make a call to a constant function or a library call.
3633 INSNS is a list containing all insns emitted in the call.
3634 These insns leave the result in RESULT. Our block is to copy RESULT
3635 to TARGET, which is logically equivalent to EQUIV.
3637 We first emit any insns that set a pseudo on the assumption that these are
3638 loading constants into registers; doing so allows them to be safely cse'ed
3639 between blocks. Then we emit all the other insns in the block, followed by
3640 an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL
3641 note with an operand of EQUIV. */
3644 emit_libcall_block_1 (rtx_insn
*insns
, rtx target
, rtx result
, rtx equiv
,
3645 bool equiv_may_trap
)
3647 rtx final_dest
= target
;
3648 rtx_insn
*next
, *last
, *insn
;
3650 /* If this is a reg with REG_USERVAR_P set, then it could possibly turn
3651 into a MEM later. Protect the libcall block from this change. */
3652 if (! REG_P (target
) || REG_USERVAR_P (target
))
3653 target
= gen_reg_rtx (GET_MODE (target
));
3655 /* If we're using non-call exceptions, a libcall corresponding to an
3656 operation that may trap may also trap. */
3657 /* ??? See the comment in front of make_reg_eh_region_note. */
3658 if (cfun
->can_throw_non_call_exceptions
3659 && (equiv_may_trap
|| may_trap_p (equiv
)))
3661 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3664 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
3667 int lp_nr
= INTVAL (XEXP (note
, 0));
3668 if (lp_nr
== 0 || lp_nr
== INT_MIN
)
3669 remove_note (insn
, note
);
3675 /* Look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION
3676 reg note to indicate that this call cannot throw or execute a nonlocal
3677 goto (unless there is already a REG_EH_REGION note, in which case
3679 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3681 make_reg_eh_region_note_nothrow_nononlocal (insn
);
3684 /* First emit all insns that set pseudos. Remove them from the list as
3685 we go. Avoid insns that set pseudos which were referenced in previous
3686 insns. These can be generated by move_by_pieces, for example,
3687 to update an address. Similarly, avoid insns that reference things
3688 set in previous insns. */
3690 for (insn
= insns
; insn
; insn
= next
)
3692 rtx set
= single_set (insn
);
3694 next
= NEXT_INSN (insn
);
3696 if (set
!= 0 && REG_P (SET_DEST (set
))
3697 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
3699 struct no_conflict_data data
;
3701 data
.target
= const0_rtx
;
3705 note_stores (PATTERN (insn
), no_conflict_move_test
, &data
);
3706 if (! data
.must_stay
)
3708 if (PREV_INSN (insn
))
3709 SET_NEXT_INSN (PREV_INSN (insn
)) = next
;
3714 SET_PREV_INSN (next
) = PREV_INSN (insn
);
3720 /* Some ports use a loop to copy large arguments onto the stack.
3721 Don't move anything outside such a loop. */
3726 /* Write the remaining insns followed by the final copy. */
3727 for (insn
= insns
; insn
; insn
= next
)
3729 next
= NEXT_INSN (insn
);
3734 last
= emit_move_insn (target
, result
);
3736 set_dst_reg_note (last
, REG_EQUAL
, copy_rtx (equiv
), target
);
3738 if (final_dest
!= target
)
3739 emit_move_insn (final_dest
, target
);
3743 emit_libcall_block (rtx_insn
*insns
, rtx target
, rtx result
, rtx equiv
)
3745 emit_libcall_block_1 (insns
, target
, result
, equiv
, false);
3748 /* Nonzero if we can perform a comparison of mode MODE straightforwardly.
3749 PURPOSE describes how this comparison will be used. CODE is the rtx
3750 comparison code we will be using.
3752 ??? Actually, CODE is slightly weaker than that. A target is still
3753 required to implement all of the normal bcc operations, but not
3754 required to implement all (or any) of the unordered bcc operations. */
3757 can_compare_p (enum rtx_code code
, machine_mode mode
,
3758 enum can_compare_purpose purpose
)
3761 test
= gen_rtx_fmt_ee (code
, mode
, const0_rtx
, const0_rtx
);
3764 enum insn_code icode
;
3766 if (purpose
== ccp_jump
3767 && (icode
= optab_handler (cbranch_optab
, mode
)) != CODE_FOR_nothing
3768 && insn_operand_matches (icode
, 0, test
))
3770 if (purpose
== ccp_store_flag
3771 && (icode
= optab_handler (cstore_optab
, mode
)) != CODE_FOR_nothing
3772 && insn_operand_matches (icode
, 1, test
))
3774 if (purpose
== ccp_cmov
3775 && optab_handler (cmov_optab
, mode
) != CODE_FOR_nothing
)
3778 mode
= GET_MODE_WIDER_MODE (mode
).else_void ();
3779 PUT_MODE (test
, mode
);
3781 while (mode
!= VOIDmode
);
3786 /* This function is called when we are going to emit a compare instruction that
3787 compares the values found in X and Y, using the rtl operator COMPARISON.
3789 If they have mode BLKmode, then SIZE specifies the size of both operands.
3791 UNSIGNEDP nonzero says that the operands are unsigned;
3792 this matters if they need to be widened (as given by METHODS).
3794 *PTEST is where the resulting comparison RTX is returned or NULL_RTX
3795 if we failed to produce one.
3797 *PMODE is the mode of the inputs (in case they are const_int).
3799 This function performs all the setup necessary so that the caller only has
3800 to emit a single comparison insn. This setup can involve doing a BLKmode
3801 comparison or emitting a library call to perform the comparison if no insn
3802 is available to handle it.
3803 The values which are passed in through pointers can be modified; the caller
3804 should perform the comparison on the modified values. Constant
3805 comparisons must have already been folded. */
3808 prepare_cmp_insn (rtx x
, rtx y
, enum rtx_code comparison
, rtx size
,
3809 int unsignedp
, enum optab_methods methods
,
3810 rtx
*ptest
, machine_mode
*pmode
)
3812 machine_mode mode
= *pmode
;
3814 machine_mode cmp_mode
;
3815 enum mode_class mclass
;
3817 /* The other methods are not needed. */
3818 gcc_assert (methods
== OPTAB_DIRECT
|| methods
== OPTAB_WIDEN
3819 || methods
== OPTAB_LIB_WIDEN
);
3821 if (CONST_SCALAR_INT_P (y
))
3822 canonicalize_comparison (mode
, &comparison
, &y
);
3824 /* If we are optimizing, force expensive constants into a register. */
3825 if (CONSTANT_P (x
) && optimize
3826 && (rtx_cost (x
, mode
, COMPARE
, 0, optimize_insn_for_speed_p ())
3827 > COSTS_N_INSNS (1)))
3828 x
= force_reg (mode
, x
);
3830 if (CONSTANT_P (y
) && optimize
3831 && (rtx_cost (y
, mode
, COMPARE
, 1, optimize_insn_for_speed_p ())
3832 > COSTS_N_INSNS (1)))
3833 y
= force_reg (mode
, y
);
3836 /* Make sure if we have a canonical comparison. The RTL
3837 documentation states that canonical comparisons are required only
3838 for targets which have cc0. */
3839 gcc_assert (!CONSTANT_P (x
) || CONSTANT_P (y
));
3842 /* Don't let both operands fail to indicate the mode. */
3843 if (GET_MODE (x
) == VOIDmode
&& GET_MODE (y
) == VOIDmode
)
3844 x
= force_reg (mode
, x
);
3845 if (mode
== VOIDmode
)
3846 mode
= GET_MODE (x
) != VOIDmode
? GET_MODE (x
) : GET_MODE (y
);
3848 /* Handle all BLKmode compares. */
3850 if (mode
== BLKmode
)
3852 machine_mode result_mode
;
3853 enum insn_code cmp_code
;
3856 = GEN_INT (MIN (MEM_ALIGN (x
), MEM_ALIGN (y
)) / BITS_PER_UNIT
);
3860 /* Try to use a memory block compare insn - either cmpstr
3861 or cmpmem will do. */
3862 opt_scalar_int_mode cmp_mode_iter
;
3863 FOR_EACH_MODE_IN_CLASS (cmp_mode_iter
, MODE_INT
)
3865 scalar_int_mode cmp_mode
= cmp_mode_iter
.require ();
3866 cmp_code
= direct_optab_handler (cmpmem_optab
, cmp_mode
);
3867 if (cmp_code
== CODE_FOR_nothing
)
3868 cmp_code
= direct_optab_handler (cmpstr_optab
, cmp_mode
);
3869 if (cmp_code
== CODE_FOR_nothing
)
3870 cmp_code
= direct_optab_handler (cmpstrn_optab
, cmp_mode
);
3871 if (cmp_code
== CODE_FOR_nothing
)
3874 /* Must make sure the size fits the insn's mode. */
3875 if (CONST_INT_P (size
)
3876 ? INTVAL (size
) >= (1 << GET_MODE_BITSIZE (cmp_mode
))
3877 : (GET_MODE_BITSIZE (as_a
<scalar_int_mode
> (GET_MODE (size
)))
3878 > GET_MODE_BITSIZE (cmp_mode
)))
3881 result_mode
= insn_data
[cmp_code
].operand
[0].mode
;
3882 result
= gen_reg_rtx (result_mode
);
3883 size
= convert_to_mode (cmp_mode
, size
, 1);
3884 emit_insn (GEN_FCN (cmp_code
) (result
, x
, y
, size
, opalign
));
3886 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, result
, const0_rtx
);
3887 *pmode
= result_mode
;
3891 if (methods
!= OPTAB_LIB
&& methods
!= OPTAB_LIB_WIDEN
)
3894 /* Otherwise call a library function. */
3895 result
= emit_block_comp_via_libcall (XEXP (x
, 0), XEXP (y
, 0), size
);
3899 mode
= TYPE_MODE (integer_type_node
);
3900 methods
= OPTAB_LIB_WIDEN
;
3904 /* Don't allow operands to the compare to trap, as that can put the
3905 compare and branch in different basic blocks. */
3906 if (cfun
->can_throw_non_call_exceptions
)
3909 x
= copy_to_reg (x
);
3911 y
= copy_to_reg (y
);
3914 if (GET_MODE_CLASS (mode
) == MODE_CC
)
3916 enum insn_code icode
= optab_handler (cbranch_optab
, CCmode
);
3917 test
= gen_rtx_fmt_ee (comparison
, VOIDmode
, x
, y
);
3918 gcc_assert (icode
!= CODE_FOR_nothing
3919 && insn_operand_matches (icode
, 0, test
));
3924 mclass
= GET_MODE_CLASS (mode
);
3925 test
= gen_rtx_fmt_ee (comparison
, VOIDmode
, x
, y
);
3926 FOR_EACH_MODE_FROM (cmp_mode
, mode
)
3928 enum insn_code icode
;
3929 icode
= optab_handler (cbranch_optab
, cmp_mode
);
3930 if (icode
!= CODE_FOR_nothing
3931 && insn_operand_matches (icode
, 0, test
))
3933 rtx_insn
*last
= get_last_insn ();
3934 rtx op0
= prepare_operand (icode
, x
, 1, mode
, cmp_mode
, unsignedp
);
3935 rtx op1
= prepare_operand (icode
, y
, 2, mode
, cmp_mode
, unsignedp
);
3937 && insn_operand_matches (icode
, 1, op0
)
3938 && insn_operand_matches (icode
, 2, op1
))
3940 XEXP (test
, 0) = op0
;
3941 XEXP (test
, 1) = op1
;
3946 delete_insns_since (last
);
3949 if (methods
== OPTAB_DIRECT
|| !CLASS_HAS_WIDER_MODES_P (mclass
))
3953 if (methods
!= OPTAB_LIB_WIDEN
)
3956 if (SCALAR_FLOAT_MODE_P (mode
))
3958 /* Small trick if UNORDERED isn't implemented by the hardware. */
3959 if (comparison
== UNORDERED
&& rtx_equal_p (x
, y
))
3961 prepare_cmp_insn (x
, y
, UNLT
, NULL_RTX
, unsignedp
, OPTAB_WIDEN
,
3967 prepare_float_lib_cmp (x
, y
, comparison
, ptest
, pmode
);
3972 machine_mode ret_mode
;
3974 /* Handle a libcall just for the mode we are using. */
3975 libfunc
= optab_libfunc (cmp_optab
, mode
);
3976 gcc_assert (libfunc
);
3978 /* If we want unsigned, and this mode has a distinct unsigned
3979 comparison routine, use that. */
3982 rtx ulibfunc
= optab_libfunc (ucmp_optab
, mode
);
3987 ret_mode
= targetm
.libgcc_cmp_return_mode ();
3988 result
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
3989 ret_mode
, x
, mode
, y
, mode
);
3991 /* There are two kinds of comparison routines. Biased routines
3992 return 0/1/2, and unbiased routines return -1/0/1. Other parts
3993 of gcc expect that the comparison operation is equivalent
3994 to the modified comparison. For signed comparisons compare the
3995 result against 1 in the biased case, and zero in the unbiased
3996 case. For unsigned comparisons always compare against 1 after
3997 biasing the unbiased result by adding 1. This gives us a way to
3999 The comparisons in the fixed-point helper library are always
4004 if (!TARGET_LIB_INT_CMP_BIASED
&& !ALL_FIXED_POINT_MODE_P (mode
))
4007 x
= plus_constant (ret_mode
, result
, 1);
4013 prepare_cmp_insn (x
, y
, comparison
, NULL_RTX
, unsignedp
, methods
,
4023 /* Before emitting an insn with code ICODE, make sure that X, which is going
4024 to be used for operand OPNUM of the insn, is converted from mode MODE to
4025 WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and
4026 that it is accepted by the operand predicate. Return the new value. */
4029 prepare_operand (enum insn_code icode
, rtx x
, int opnum
, machine_mode mode
,
4030 machine_mode wider_mode
, int unsignedp
)
4032 if (mode
!= wider_mode
)
4033 x
= convert_modes (wider_mode
, mode
, x
, unsignedp
);
4035 if (!insn_operand_matches (icode
, opnum
, x
))
4037 machine_mode op_mode
= insn_data
[(int) icode
].operand
[opnum
].mode
;
4038 if (reload_completed
)
4040 if (GET_MODE (x
) != op_mode
&& GET_MODE (x
) != VOIDmode
)
4042 x
= copy_to_mode_reg (op_mode
, x
);
4048 /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know
4049 we can do the branch. */
4052 emit_cmp_and_jump_insn_1 (rtx test
, machine_mode mode
, rtx label
,
4053 profile_probability prob
)
4055 machine_mode optab_mode
;
4056 enum mode_class mclass
;
4057 enum insn_code icode
;
4060 mclass
= GET_MODE_CLASS (mode
);
4061 optab_mode
= (mclass
== MODE_CC
) ? CCmode
: mode
;
4062 icode
= optab_handler (cbranch_optab
, optab_mode
);
4064 gcc_assert (icode
!= CODE_FOR_nothing
);
4065 gcc_assert (insn_operand_matches (icode
, 0, test
));
4066 insn
= emit_jump_insn (GEN_FCN (icode
) (test
, XEXP (test
, 0),
4067 XEXP (test
, 1), label
));
4068 if (prob
.initialized_p ()
4069 && profile_status_for_fn (cfun
) != PROFILE_ABSENT
4072 && any_condjump_p (insn
)
4073 && !find_reg_note (insn
, REG_BR_PROB
, 0))
4074 add_reg_br_prob_note (insn
, prob
);
4077 /* Generate code to compare X with Y so that the condition codes are
4078 set and to jump to LABEL if the condition is true. If X is a
4079 constant and Y is not a constant, then the comparison is swapped to
4080 ensure that the comparison RTL has the canonical form.
4082 UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they
4083 need to be widened. UNSIGNEDP is also used to select the proper
4084 branch condition code.
4086 If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y.
4088 MODE is the mode of the inputs (in case they are const_int).
4090 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
4091 It will be potentially converted into an unsigned variant based on
4092 UNSIGNEDP to select a proper jump instruction.
4094 PROB is the probability of jumping to LABEL. */
4097 emit_cmp_and_jump_insns (rtx x
, rtx y
, enum rtx_code comparison
, rtx size
,
4098 machine_mode mode
, int unsignedp
, rtx label
,
4099 profile_probability prob
)
4101 rtx op0
= x
, op1
= y
;
4104 /* Swap operands and condition to ensure canonical RTL. */
4105 if (swap_commutative_operands_p (x
, y
)
4106 && can_compare_p (swap_condition (comparison
), mode
, ccp_jump
))
4109 comparison
= swap_condition (comparison
);
4112 /* If OP0 is still a constant, then both X and Y must be constants
4113 or the opposite comparison is not supported. Force X into a register
4114 to create canonical RTL. */
4115 if (CONSTANT_P (op0
))
4116 op0
= force_reg (mode
, op0
);
4119 comparison
= unsigned_condition (comparison
);
4121 prepare_cmp_insn (op0
, op1
, comparison
, size
, unsignedp
, OPTAB_LIB_WIDEN
,
4123 emit_cmp_and_jump_insn_1 (test
, mode
, label
, prob
);
4127 /* Emit a library call comparison between floating point X and Y.
4128 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */
4131 prepare_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
,
4132 rtx
*ptest
, machine_mode
*pmode
)
4134 enum rtx_code swapped
= swap_condition (comparison
);
4135 enum rtx_code reversed
= reverse_condition_maybe_unordered (comparison
);
4136 machine_mode orig_mode
= GET_MODE (x
);
4138 rtx true_rtx
, false_rtx
;
4139 rtx value
, target
, equiv
;
4142 bool reversed_p
= false;
4143 scalar_int_mode cmp_mode
= targetm
.libgcc_cmp_return_mode ();
4145 FOR_EACH_MODE_FROM (mode
, orig_mode
)
4147 if (code_to_optab (comparison
)
4148 && (libfunc
= optab_libfunc (code_to_optab (comparison
), mode
)))
4151 if (code_to_optab (swapped
)
4152 && (libfunc
= optab_libfunc (code_to_optab (swapped
), mode
)))
4155 comparison
= swapped
;
4159 if (code_to_optab (reversed
)
4160 && (libfunc
= optab_libfunc (code_to_optab (reversed
), mode
)))
4162 comparison
= reversed
;
4168 gcc_assert (mode
!= VOIDmode
);
4170 if (mode
!= orig_mode
)
4172 x
= convert_to_mode (mode
, x
, 0);
4173 y
= convert_to_mode (mode
, y
, 0);
4176 /* Attach a REG_EQUAL note describing the semantics of the libcall to
4177 the RTL. The allows the RTL optimizers to delete the libcall if the
4178 condition can be determined at compile-time. */
4179 if (comparison
== UNORDERED
4180 || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
))
4182 true_rtx
= const_true_rtx
;
4183 false_rtx
= const0_rtx
;
4190 true_rtx
= const0_rtx
;
4191 false_rtx
= const_true_rtx
;
4195 true_rtx
= const_true_rtx
;
4196 false_rtx
= const0_rtx
;
4200 true_rtx
= const1_rtx
;
4201 false_rtx
= const0_rtx
;
4205 true_rtx
= const0_rtx
;
4206 false_rtx
= constm1_rtx
;
4210 true_rtx
= constm1_rtx
;
4211 false_rtx
= const0_rtx
;
4215 true_rtx
= const0_rtx
;
4216 false_rtx
= const1_rtx
;
4224 if (comparison
== UNORDERED
)
4226 rtx temp
= simplify_gen_relational (NE
, cmp_mode
, mode
, x
, x
);
4227 equiv
= simplify_gen_relational (NE
, cmp_mode
, mode
, y
, y
);
4228 equiv
= simplify_gen_ternary (IF_THEN_ELSE
, cmp_mode
, cmp_mode
,
4229 temp
, const_true_rtx
, equiv
);
4233 equiv
= simplify_gen_relational (comparison
, cmp_mode
, mode
, x
, y
);
4234 if (! FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
))
4235 equiv
= simplify_gen_ternary (IF_THEN_ELSE
, cmp_mode
, cmp_mode
,
4236 equiv
, true_rtx
, false_rtx
);
4240 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
4241 cmp_mode
, x
, mode
, y
, mode
);
4242 insns
= get_insns ();
4245 target
= gen_reg_rtx (cmp_mode
);
4246 emit_libcall_block (insns
, target
, value
, equiv
);
4248 if (comparison
== UNORDERED
4249 || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
)
4251 *ptest
= gen_rtx_fmt_ee (reversed_p
? EQ
: NE
, VOIDmode
, target
, false_rtx
);
4253 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, target
, const0_rtx
);
4258 /* Generate code to indirectly jump to a location given in the rtx LOC. */
4261 emit_indirect_jump (rtx loc
)
4263 if (!targetm
.have_indirect_jump ())
4264 sorry ("indirect jumps are not available on this target");
4267 struct expand_operand ops
[1];
4268 create_address_operand (&ops
[0], loc
);
4269 expand_jump_insn (targetm
.code_for_indirect_jump
, 1, ops
);
4275 /* Emit a conditional move instruction if the machine supports one for that
4276 condition and machine mode.
4278 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4279 the mode to use should they be constants. If it is VOIDmode, they cannot
4282 OP2 should be stored in TARGET if the comparison is true, otherwise OP3
4283 should be stored there. MODE is the mode to use should they be constants.
4284 If it is VOIDmode, they cannot both be constants.
4286 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4287 is not supported. */
4290 emit_conditional_move (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
4291 machine_mode cmode
, rtx op2
, rtx op3
,
4292 machine_mode mode
, int unsignedp
)
4296 enum insn_code icode
;
4297 enum rtx_code reversed
;
4299 /* If the two source operands are identical, that's just a move. */
4301 if (rtx_equal_p (op2
, op3
))
4304 target
= gen_reg_rtx (mode
);
4306 emit_move_insn (target
, op3
);
4310 /* If one operand is constant, make it the second one. Only do this
4311 if the other operand is not constant as well. */
4313 if (swap_commutative_operands_p (op0
, op1
))
4315 std::swap (op0
, op1
);
4316 code
= swap_condition (code
);
4319 /* get_condition will prefer to generate LT and GT even if the old
4320 comparison was against zero, so undo that canonicalization here since
4321 comparisons against zero are cheaper. */
4322 if (code
== LT
&& op1
== const1_rtx
)
4323 code
= LE
, op1
= const0_rtx
;
4324 else if (code
== GT
&& op1
== constm1_rtx
)
4325 code
= GE
, op1
= const0_rtx
;
4327 if (cmode
== VOIDmode
)
4328 cmode
= GET_MODE (op0
);
4330 enum rtx_code orig_code
= code
;
4331 bool swapped
= false;
4332 if (swap_commutative_operands_p (op2
, op3
)
4333 && ((reversed
= reversed_comparison_code_parts (code
, op0
, op1
, NULL
))
4336 std::swap (op2
, op3
);
4341 if (mode
== VOIDmode
)
4342 mode
= GET_MODE (op2
);
4344 icode
= direct_optab_handler (movcc_optab
, mode
);
4346 if (icode
== CODE_FOR_nothing
)
4350 target
= gen_reg_rtx (mode
);
4352 for (int pass
= 0; ; pass
++)
4354 code
= unsignedp
? unsigned_condition (code
) : code
;
4355 comparison
= simplify_gen_relational (code
, VOIDmode
, cmode
, op0
, op1
);
4357 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4358 punt and let the caller figure out how best to deal with this
4360 if (COMPARISON_P (comparison
))
4362 saved_pending_stack_adjust save
;
4363 save_pending_stack_adjust (&save
);
4364 last
= get_last_insn ();
4365 do_pending_stack_adjust ();
4366 machine_mode cmpmode
= cmode
;
4367 prepare_cmp_insn (XEXP (comparison
, 0), XEXP (comparison
, 1),
4368 GET_CODE (comparison
), NULL_RTX
, unsignedp
,
4369 OPTAB_WIDEN
, &comparison
, &cmpmode
);
4372 struct expand_operand ops
[4];
4374 create_output_operand (&ops
[0], target
, mode
);
4375 create_fixed_operand (&ops
[1], comparison
);
4376 create_input_operand (&ops
[2], op2
, mode
);
4377 create_input_operand (&ops
[3], op3
, mode
);
4378 if (maybe_expand_insn (icode
, 4, ops
))
4380 if (ops
[0].value
!= target
)
4381 convert_move (target
, ops
[0].value
, false);
4385 delete_insns_since (last
);
4386 restore_pending_stack_adjust (&save
);
4392 /* If the preferred op2/op3 order is not usable, retry with other
4393 operand order, perhaps it will expand successfully. */
4396 else if ((reversed
= reversed_comparison_code_parts (orig_code
, op0
, op1
,
4402 std::swap (op2
, op3
);
4407 /* Emit a conditional negate or bitwise complement using the
4408 negcc or notcc optabs if available. Return NULL_RTX if such operations
4409 are not available. Otherwise return the RTX holding the result.
4410 TARGET is the desired destination of the result. COMP is the comparison
4411 on which to negate. If COND is true move into TARGET the negation
4412 or bitwise complement of OP1. Otherwise move OP2 into TARGET.
4413 CODE is either NEG or NOT. MODE is the machine mode in which the
4414 operation is performed. */
4417 emit_conditional_neg_or_complement (rtx target
, rtx_code code
,
4418 machine_mode mode
, rtx cond
, rtx op1
,
4421 optab op
= unknown_optab
;
4424 else if (code
== NOT
)
4429 insn_code icode
= direct_optab_handler (op
, mode
);
4431 if (icode
== CODE_FOR_nothing
)
4435 target
= gen_reg_rtx (mode
);
4437 rtx_insn
*last
= get_last_insn ();
4438 struct expand_operand ops
[4];
4440 create_output_operand (&ops
[0], target
, mode
);
4441 create_fixed_operand (&ops
[1], cond
);
4442 create_input_operand (&ops
[2], op1
, mode
);
4443 create_input_operand (&ops
[3], op2
, mode
);
4445 if (maybe_expand_insn (icode
, 4, ops
))
4447 if (ops
[0].value
!= target
)
4448 convert_move (target
, ops
[0].value
, false);
4452 delete_insns_since (last
);
4456 /* Emit a conditional addition instruction if the machine supports one for that
4457 condition and machine mode.
4459 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4460 the mode to use should they be constants. If it is VOIDmode, they cannot
4463 OP2 should be stored in TARGET if the comparison is false, otherwise OP2+OP3
4464 should be stored there. MODE is the mode to use should they be constants.
4465 If it is VOIDmode, they cannot both be constants.
4467 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4468 is not supported. */
4471 emit_conditional_add (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
4472 machine_mode cmode
, rtx op2
, rtx op3
,
4473 machine_mode mode
, int unsignedp
)
4477 enum insn_code icode
;
4479 /* If one operand is constant, make it the second one. Only do this
4480 if the other operand is not constant as well. */
4482 if (swap_commutative_operands_p (op0
, op1
))
4484 std::swap (op0
, op1
);
4485 code
= swap_condition (code
);
4488 /* get_condition will prefer to generate LT and GT even if the old
4489 comparison was against zero, so undo that canonicalization here since
4490 comparisons against zero are cheaper. */
4491 if (code
== LT
&& op1
== const1_rtx
)
4492 code
= LE
, op1
= const0_rtx
;
4493 else if (code
== GT
&& op1
== constm1_rtx
)
4494 code
= GE
, op1
= const0_rtx
;
4496 if (cmode
== VOIDmode
)
4497 cmode
= GET_MODE (op0
);
4499 if (mode
== VOIDmode
)
4500 mode
= GET_MODE (op2
);
4502 icode
= optab_handler (addcc_optab
, mode
);
4504 if (icode
== CODE_FOR_nothing
)
4508 target
= gen_reg_rtx (mode
);
4510 code
= unsignedp
? unsigned_condition (code
) : code
;
4511 comparison
= simplify_gen_relational (code
, VOIDmode
, cmode
, op0
, op1
);
4513 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4514 return NULL and let the caller figure out how best to deal with this
4516 if (!COMPARISON_P (comparison
))
4519 do_pending_stack_adjust ();
4520 last
= get_last_insn ();
4521 prepare_cmp_insn (XEXP (comparison
, 0), XEXP (comparison
, 1),
4522 GET_CODE (comparison
), NULL_RTX
, unsignedp
, OPTAB_WIDEN
,
4523 &comparison
, &cmode
);
4526 struct expand_operand ops
[4];
4528 create_output_operand (&ops
[0], target
, mode
);
4529 create_fixed_operand (&ops
[1], comparison
);
4530 create_input_operand (&ops
[2], op2
, mode
);
4531 create_input_operand (&ops
[3], op3
, mode
);
4532 if (maybe_expand_insn (icode
, 4, ops
))
4534 if (ops
[0].value
!= target
)
4535 convert_move (target
, ops
[0].value
, false);
4539 delete_insns_since (last
);
4543 /* These functions attempt to generate an insn body, rather than
4544 emitting the insn, but if the gen function already emits them, we
4545 make no attempt to turn them back into naked patterns. */
4547 /* Generate and return an insn body to add Y to X. */
4550 gen_add2_insn (rtx x
, rtx y
)
4552 enum insn_code icode
= optab_handler (add_optab
, GET_MODE (x
));
4554 gcc_assert (insn_operand_matches (icode
, 0, x
));
4555 gcc_assert (insn_operand_matches (icode
, 1, x
));
4556 gcc_assert (insn_operand_matches (icode
, 2, y
));
4558 return GEN_FCN (icode
) (x
, x
, y
);
4561 /* Generate and return an insn body to add r1 and c,
4562 storing the result in r0. */
4565 gen_add3_insn (rtx r0
, rtx r1
, rtx c
)
4567 enum insn_code icode
= optab_handler (add_optab
, GET_MODE (r0
));
4569 if (icode
== CODE_FOR_nothing
4570 || !insn_operand_matches (icode
, 0, r0
)
4571 || !insn_operand_matches (icode
, 1, r1
)
4572 || !insn_operand_matches (icode
, 2, c
))
4575 return GEN_FCN (icode
) (r0
, r1
, c
);
4579 have_add2_insn (rtx x
, rtx y
)
4581 enum insn_code icode
;
4583 gcc_assert (GET_MODE (x
) != VOIDmode
);
4585 icode
= optab_handler (add_optab
, GET_MODE (x
));
4587 if (icode
== CODE_FOR_nothing
)
4590 if (!insn_operand_matches (icode
, 0, x
)
4591 || !insn_operand_matches (icode
, 1, x
)
4592 || !insn_operand_matches (icode
, 2, y
))
4598 /* Generate and return an insn body to add Y to X. */
4601 gen_addptr3_insn (rtx x
, rtx y
, rtx z
)
4603 enum insn_code icode
= optab_handler (addptr3_optab
, GET_MODE (x
));
4605 gcc_assert (insn_operand_matches (icode
, 0, x
));
4606 gcc_assert (insn_operand_matches (icode
, 1, y
));
4607 gcc_assert (insn_operand_matches (icode
, 2, z
));
4609 return GEN_FCN (icode
) (x
, y
, z
);
4612 /* Return true if the target implements an addptr pattern and X, Y,
4613 and Z are valid for the pattern predicates. */
4616 have_addptr3_insn (rtx x
, rtx y
, rtx z
)
4618 enum insn_code icode
;
4620 gcc_assert (GET_MODE (x
) != VOIDmode
);
4622 icode
= optab_handler (addptr3_optab
, GET_MODE (x
));
4624 if (icode
== CODE_FOR_nothing
)
4627 if (!insn_operand_matches (icode
, 0, x
)
4628 || !insn_operand_matches (icode
, 1, y
)
4629 || !insn_operand_matches (icode
, 2, z
))
4635 /* Generate and return an insn body to subtract Y from X. */
4638 gen_sub2_insn (rtx x
, rtx y
)
4640 enum insn_code icode
= optab_handler (sub_optab
, GET_MODE (x
));
4642 gcc_assert (insn_operand_matches (icode
, 0, x
));
4643 gcc_assert (insn_operand_matches (icode
, 1, x
));
4644 gcc_assert (insn_operand_matches (icode
, 2, y
));
4646 return GEN_FCN (icode
) (x
, x
, y
);
4649 /* Generate and return an insn body to subtract r1 and c,
4650 storing the result in r0. */
4653 gen_sub3_insn (rtx r0
, rtx r1
, rtx c
)
4655 enum insn_code icode
= optab_handler (sub_optab
, GET_MODE (r0
));
4657 if (icode
== CODE_FOR_nothing
4658 || !insn_operand_matches (icode
, 0, r0
)
4659 || !insn_operand_matches (icode
, 1, r1
)
4660 || !insn_operand_matches (icode
, 2, c
))
4663 return GEN_FCN (icode
) (r0
, r1
, c
);
4667 have_sub2_insn (rtx x
, rtx y
)
4669 enum insn_code icode
;
4671 gcc_assert (GET_MODE (x
) != VOIDmode
);
4673 icode
= optab_handler (sub_optab
, GET_MODE (x
));
4675 if (icode
== CODE_FOR_nothing
)
4678 if (!insn_operand_matches (icode
, 0, x
)
4679 || !insn_operand_matches (icode
, 1, x
)
4680 || !insn_operand_matches (icode
, 2, y
))
4686 /* Generate the body of an insn to extend Y (with mode MFROM)
4687 into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */
4690 gen_extend_insn (rtx x
, rtx y
, machine_mode mto
,
4691 machine_mode mfrom
, int unsignedp
)
4693 enum insn_code icode
= can_extend_p (mto
, mfrom
, unsignedp
);
4694 return GEN_FCN (icode
) (x
, y
);
4697 /* Generate code to convert FROM to floating point
4698 and store in TO. FROM must be fixed point and not VOIDmode.
4699 UNSIGNEDP nonzero means regard FROM as unsigned.
4700 Normally this is done by correcting the final value
4701 if it is negative. */
4704 expand_float (rtx to
, rtx from
, int unsignedp
)
4706 enum insn_code icode
;
4708 scalar_mode from_mode
, to_mode
;
4709 machine_mode fmode
, imode
;
4710 bool can_do_signed
= false;
4712 /* Crash now, because we won't be able to decide which mode to use. */
4713 gcc_assert (GET_MODE (from
) != VOIDmode
);
4715 /* Look for an insn to do the conversion. Do it in the specified
4716 modes if possible; otherwise convert either input, output or both to
4717 wider mode. If the integer mode is wider than the mode of FROM,
4718 we can do the conversion signed even if the input is unsigned. */
4720 FOR_EACH_MODE_FROM (fmode
, GET_MODE (to
))
4721 FOR_EACH_MODE_FROM (imode
, GET_MODE (from
))
4723 int doing_unsigned
= unsignedp
;
4725 if (fmode
!= GET_MODE (to
)
4726 && (significand_size (fmode
)
4727 < GET_MODE_UNIT_PRECISION (GET_MODE (from
))))
4730 icode
= can_float_p (fmode
, imode
, unsignedp
);
4731 if (icode
== CODE_FOR_nothing
&& unsignedp
)
4733 enum insn_code scode
= can_float_p (fmode
, imode
, 0);
4734 if (scode
!= CODE_FOR_nothing
)
4735 can_do_signed
= true;
4736 if (imode
!= GET_MODE (from
))
4737 icode
= scode
, doing_unsigned
= 0;
4740 if (icode
!= CODE_FOR_nothing
)
4742 if (imode
!= GET_MODE (from
))
4743 from
= convert_to_mode (imode
, from
, unsignedp
);
4745 if (fmode
!= GET_MODE (to
))
4746 target
= gen_reg_rtx (fmode
);
4748 emit_unop_insn (icode
, target
, from
,
4749 doing_unsigned
? UNSIGNED_FLOAT
: FLOAT
);
4752 convert_move (to
, target
, 0);
4757 /* Unsigned integer, and no way to convert directly. Convert as signed,
4758 then unconditionally adjust the result. */
4761 && is_a
<scalar_mode
> (GET_MODE (to
), &to_mode
)
4762 && is_a
<scalar_mode
> (GET_MODE (from
), &from_mode
))
4764 opt_scalar_mode fmode_iter
;
4765 rtx_code_label
*label
= gen_label_rtx ();
4767 REAL_VALUE_TYPE offset
;
4769 /* Look for a usable floating mode FMODE wider than the source and at
4770 least as wide as the target. Using FMODE will avoid rounding woes
4771 with unsigned values greater than the signed maximum value. */
4773 FOR_EACH_MODE_FROM (fmode_iter
, to_mode
)
4775 scalar_mode fmode
= fmode_iter
.require ();
4776 if (GET_MODE_PRECISION (from_mode
) < GET_MODE_BITSIZE (fmode
)
4777 && can_float_p (fmode
, from_mode
, 0) != CODE_FOR_nothing
)
4781 if (!fmode_iter
.exists (&fmode
))
4783 /* There is no such mode. Pretend the target is wide enough. */
4786 /* Avoid double-rounding when TO is narrower than FROM. */
4787 if ((significand_size (fmode
) + 1)
4788 < GET_MODE_PRECISION (from_mode
))
4791 rtx_code_label
*neglabel
= gen_label_rtx ();
4793 /* Don't use TARGET if it isn't a register, is a hard register,
4794 or is the wrong mode. */
4796 || REGNO (target
) < FIRST_PSEUDO_REGISTER
4797 || GET_MODE (target
) != fmode
)
4798 target
= gen_reg_rtx (fmode
);
4801 do_pending_stack_adjust ();
4803 /* Test whether the sign bit is set. */
4804 emit_cmp_and_jump_insns (from
, const0_rtx
, LT
, NULL_RTX
, imode
,
4807 /* The sign bit is not set. Convert as signed. */
4808 expand_float (target
, from
, 0);
4809 emit_jump_insn (targetm
.gen_jump (label
));
4812 /* The sign bit is set.
4813 Convert to a usable (positive signed) value by shifting right
4814 one bit, while remembering if a nonzero bit was shifted
4815 out; i.e., compute (from & 1) | (from >> 1). */
4817 emit_label (neglabel
);
4818 temp
= expand_binop (imode
, and_optab
, from
, const1_rtx
,
4819 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4820 temp1
= expand_shift (RSHIFT_EXPR
, imode
, from
, 1, NULL_RTX
, 1);
4821 temp
= expand_binop (imode
, ior_optab
, temp
, temp1
, temp
, 1,
4823 expand_float (target
, temp
, 0);
4825 /* Multiply by 2 to undo the shift above. */
4826 temp
= expand_binop (fmode
, add_optab
, target
, target
,
4827 target
, 0, OPTAB_LIB_WIDEN
);
4829 emit_move_insn (target
, temp
);
4831 do_pending_stack_adjust ();
4837 /* If we are about to do some arithmetic to correct for an
4838 unsigned operand, do it in a pseudo-register. */
4840 if (to_mode
!= fmode
4841 || !REG_P (to
) || REGNO (to
) < FIRST_PSEUDO_REGISTER
)
4842 target
= gen_reg_rtx (fmode
);
4844 /* Convert as signed integer to floating. */
4845 expand_float (target
, from
, 0);
4847 /* If FROM is negative (and therefore TO is negative),
4848 correct its value by 2**bitwidth. */
4850 do_pending_stack_adjust ();
4851 emit_cmp_and_jump_insns (from
, const0_rtx
, GE
, NULL_RTX
, from_mode
,
4855 real_2expN (&offset
, GET_MODE_PRECISION (from_mode
), fmode
);
4856 temp
= expand_binop (fmode
, add_optab
, target
,
4857 const_double_from_real_value (offset
, fmode
),
4858 target
, 0, OPTAB_LIB_WIDEN
);
4860 emit_move_insn (target
, temp
);
4862 do_pending_stack_adjust ();
4867 /* No hardware instruction available; call a library routine. */
4872 convert_optab tab
= unsignedp
? ufloat_optab
: sfloat_optab
;
4874 if (is_narrower_int_mode (GET_MODE (from
), SImode
))
4875 from
= convert_to_mode (SImode
, from
, unsignedp
);
4877 libfunc
= convert_optab_libfunc (tab
, GET_MODE (to
), GET_MODE (from
));
4878 gcc_assert (libfunc
);
4882 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
4883 GET_MODE (to
), from
, GET_MODE (from
));
4884 insns
= get_insns ();
4887 emit_libcall_block (insns
, target
, value
,
4888 gen_rtx_fmt_e (unsignedp
? UNSIGNED_FLOAT
: FLOAT
,
4889 GET_MODE (to
), from
));
4894 /* Copy result to requested destination
4895 if we have been computing in a temp location. */
4899 if (GET_MODE (target
) == GET_MODE (to
))
4900 emit_move_insn (to
, target
);
4902 convert_move (to
, target
, 0);
4906 /* Generate code to convert FROM to fixed point and store in TO. FROM
4907 must be floating point. */
4910 expand_fix (rtx to
, rtx from
, int unsignedp
)
4912 enum insn_code icode
;
4914 machine_mode fmode
, imode
;
4915 opt_scalar_mode fmode_iter
;
4916 bool must_trunc
= false;
4918 /* We first try to find a pair of modes, one real and one integer, at
4919 least as wide as FROM and TO, respectively, in which we can open-code
4920 this conversion. If the integer mode is wider than the mode of TO,
4921 we can do the conversion either signed or unsigned. */
4923 FOR_EACH_MODE_FROM (fmode
, GET_MODE (from
))
4924 FOR_EACH_MODE_FROM (imode
, GET_MODE (to
))
4926 int doing_unsigned
= unsignedp
;
4928 icode
= can_fix_p (imode
, fmode
, unsignedp
, &must_trunc
);
4929 if (icode
== CODE_FOR_nothing
&& imode
!= GET_MODE (to
) && unsignedp
)
4930 icode
= can_fix_p (imode
, fmode
, 0, &must_trunc
), doing_unsigned
= 0;
4932 if (icode
!= CODE_FOR_nothing
)
4934 rtx_insn
*last
= get_last_insn ();
4935 if (fmode
!= GET_MODE (from
))
4936 from
= convert_to_mode (fmode
, from
, 0);
4940 rtx temp
= gen_reg_rtx (GET_MODE (from
));
4941 from
= expand_unop (GET_MODE (from
), ftrunc_optab
, from
,
4945 if (imode
!= GET_MODE (to
))
4946 target
= gen_reg_rtx (imode
);
4948 if (maybe_emit_unop_insn (icode
, target
, from
,
4949 doing_unsigned
? UNSIGNED_FIX
: FIX
))
4952 convert_move (to
, target
, unsignedp
);
4955 delete_insns_since (last
);
4959 /* For an unsigned conversion, there is one more way to do it.
4960 If we have a signed conversion, we generate code that compares
4961 the real value to the largest representable positive number. If if
4962 is smaller, the conversion is done normally. Otherwise, subtract
4963 one plus the highest signed number, convert, and add it back.
4965 We only need to check all real modes, since we know we didn't find
4966 anything with a wider integer mode.
4968 This code used to extend FP value into mode wider than the destination.
4969 This is needed for decimal float modes which cannot accurately
4970 represent one plus the highest signed number of the same size, but
4971 not for binary modes. Consider, for instance conversion from SFmode
4974 The hot path through the code is dealing with inputs smaller than 2^63
4975 and doing just the conversion, so there is no bits to lose.
4977 In the other path we know the value is positive in the range 2^63..2^64-1
4978 inclusive. (as for other input overflow happens and result is undefined)
4979 So we know that the most important bit set in mantissa corresponds to
4980 2^63. The subtraction of 2^63 should not generate any rounding as it
4981 simply clears out that bit. The rest is trivial. */
4983 scalar_int_mode to_mode
;
4985 && is_a
<scalar_int_mode
> (GET_MODE (to
), &to_mode
)
4986 && HWI_COMPUTABLE_MODE_P (to_mode
))
4987 FOR_EACH_MODE_FROM (fmode_iter
, as_a
<scalar_mode
> (GET_MODE (from
)))
4989 scalar_mode fmode
= fmode_iter
.require ();
4990 if (CODE_FOR_nothing
!= can_fix_p (to_mode
, fmode
,
4992 && (!DECIMAL_FLOAT_MODE_P (fmode
)
4993 || (GET_MODE_BITSIZE (fmode
) > GET_MODE_PRECISION (to_mode
))))
4996 REAL_VALUE_TYPE offset
;
4998 rtx_code_label
*lab1
, *lab2
;
5001 bitsize
= GET_MODE_PRECISION (to_mode
);
5002 real_2expN (&offset
, bitsize
- 1, fmode
);
5003 limit
= const_double_from_real_value (offset
, fmode
);
5004 lab1
= gen_label_rtx ();
5005 lab2
= gen_label_rtx ();
5007 if (fmode
!= GET_MODE (from
))
5008 from
= convert_to_mode (fmode
, from
, 0);
5010 /* See if we need to do the subtraction. */
5011 do_pending_stack_adjust ();
5012 emit_cmp_and_jump_insns (from
, limit
, GE
, NULL_RTX
,
5013 GET_MODE (from
), 0, lab1
);
5015 /* If not, do the signed "fix" and branch around fixup code. */
5016 expand_fix (to
, from
, 0);
5017 emit_jump_insn (targetm
.gen_jump (lab2
));
5020 /* Otherwise, subtract 2**(N-1), convert to signed number,
5021 then add 2**(N-1). Do the addition using XOR since this
5022 will often generate better code. */
5024 target
= expand_binop (GET_MODE (from
), sub_optab
, from
, limit
,
5025 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
5026 expand_fix (to
, target
, 0);
5027 target
= expand_binop (to_mode
, xor_optab
, to
,
5029 (HOST_WIDE_INT_1
<< (bitsize
- 1),
5031 to
, 1, OPTAB_LIB_WIDEN
);
5034 emit_move_insn (to
, target
);
5038 if (optab_handler (mov_optab
, to_mode
) != CODE_FOR_nothing
)
5040 /* Make a place for a REG_NOTE and add it. */
5041 insn
= emit_move_insn (to
, to
);
5042 set_dst_reg_note (insn
, REG_EQUAL
,
5043 gen_rtx_fmt_e (UNSIGNED_FIX
, to_mode
,
5052 /* We can't do it with an insn, so use a library call. But first ensure
5053 that the mode of TO is at least as wide as SImode, since those are the
5054 only library calls we know about. */
5056 if (is_narrower_int_mode (GET_MODE (to
), SImode
))
5058 target
= gen_reg_rtx (SImode
);
5060 expand_fix (target
, from
, unsignedp
);
5068 convert_optab tab
= unsignedp
? ufix_optab
: sfix_optab
;
5069 libfunc
= convert_optab_libfunc (tab
, GET_MODE (to
), GET_MODE (from
));
5070 gcc_assert (libfunc
);
5074 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
5075 GET_MODE (to
), from
, GET_MODE (from
));
5076 insns
= get_insns ();
5079 emit_libcall_block (insns
, target
, value
,
5080 gen_rtx_fmt_e (unsignedp
? UNSIGNED_FIX
: FIX
,
5081 GET_MODE (to
), from
));
5086 if (GET_MODE (to
) == GET_MODE (target
))
5087 emit_move_insn (to
, target
);
5089 convert_move (to
, target
, 0);
5094 /* Promote integer arguments for a libcall if necessary.
5095 emit_library_call_value cannot do the promotion because it does not
5096 know if it should do a signed or unsigned promotion. This is because
5097 there are no tree types defined for libcalls. */
5100 prepare_libcall_arg (rtx arg
, int uintp
)
5102 scalar_int_mode mode
;
5103 machine_mode arg_mode
;
5104 if (is_a
<scalar_int_mode
> (GET_MODE (arg
), &mode
))
5106 /* If we need to promote the integer function argument we need to do
5107 it here instead of inside emit_library_call_value because in
5108 emit_library_call_value we don't know if we should do a signed or
5109 unsigned promotion. */
5112 arg_mode
= promote_function_mode (NULL_TREE
, mode
,
5113 &unsigned_p
, NULL_TREE
, 0);
5114 if (arg_mode
!= mode
)
5115 return convert_to_mode (arg_mode
, arg
, uintp
);
5120 /* Generate code to convert FROM or TO a fixed-point.
5121 If UINTP is true, either TO or FROM is an unsigned integer.
5122 If SATP is true, we need to saturate the result. */
5125 expand_fixed_convert (rtx to
, rtx from
, int uintp
, int satp
)
5127 machine_mode to_mode
= GET_MODE (to
);
5128 machine_mode from_mode
= GET_MODE (from
);
5130 enum rtx_code this_code
;
5131 enum insn_code code
;
5136 if (to_mode
== from_mode
)
5138 emit_move_insn (to
, from
);
5144 tab
= satp
? satfractuns_optab
: fractuns_optab
;
5145 this_code
= satp
? UNSIGNED_SAT_FRACT
: UNSIGNED_FRACT_CONVERT
;
5149 tab
= satp
? satfract_optab
: fract_optab
;
5150 this_code
= satp
? SAT_FRACT
: FRACT_CONVERT
;
5152 code
= convert_optab_handler (tab
, to_mode
, from_mode
);
5153 if (code
!= CODE_FOR_nothing
)
5155 emit_unop_insn (code
, to
, from
, this_code
);
5159 libfunc
= convert_optab_libfunc (tab
, to_mode
, from_mode
);
5160 gcc_assert (libfunc
);
5162 from
= prepare_libcall_arg (from
, uintp
);
5163 from_mode
= GET_MODE (from
);
5166 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
, to_mode
,
5168 insns
= get_insns ();
5171 emit_libcall_block (insns
, to
, value
,
5172 gen_rtx_fmt_e (optab_to_code (tab
), to_mode
, from
));
5175 /* Generate code to convert FROM to fixed point and store in TO. FROM
5176 must be floating point, TO must be signed. Use the conversion optab
5177 TAB to do the conversion. */
5180 expand_sfix_optab (rtx to
, rtx from
, convert_optab tab
)
5182 enum insn_code icode
;
5184 machine_mode fmode
, imode
;
5186 /* We first try to find a pair of modes, one real and one integer, at
5187 least as wide as FROM and TO, respectively, in which we can open-code
5188 this conversion. If the integer mode is wider than the mode of TO,
5189 we can do the conversion either signed or unsigned. */
5191 FOR_EACH_MODE_FROM (fmode
, GET_MODE (from
))
5192 FOR_EACH_MODE_FROM (imode
, GET_MODE (to
))
5194 icode
= convert_optab_handler (tab
, imode
, fmode
);
5195 if (icode
!= CODE_FOR_nothing
)
5197 rtx_insn
*last
= get_last_insn ();
5198 if (fmode
!= GET_MODE (from
))
5199 from
= convert_to_mode (fmode
, from
, 0);
5201 if (imode
!= GET_MODE (to
))
5202 target
= gen_reg_rtx (imode
);
5204 if (!maybe_emit_unop_insn (icode
, target
, from
, UNKNOWN
))
5206 delete_insns_since (last
);
5210 convert_move (to
, target
, 0);
5218 /* Report whether we have an instruction to perform the operation
5219 specified by CODE on operands of mode MODE. */
5221 have_insn_for (enum rtx_code code
, machine_mode mode
)
5223 return (code_to_optab (code
)
5224 && (optab_handler (code_to_optab (code
), mode
)
5225 != CODE_FOR_nothing
));
5228 /* Print information about the current contents of the optabs on
5232 debug_optab_libfuncs (void)
5236 /* Dump the arithmetic optabs. */
5237 for (i
= FIRST_NORM_OPTAB
; i
<= LAST_NORMLIB_OPTAB
; ++i
)
5238 for (j
= 0; j
< NUM_MACHINE_MODES
; ++j
)
5240 rtx l
= optab_libfunc ((optab
) i
, (machine_mode
) j
);
5243 gcc_assert (GET_CODE (l
) == SYMBOL_REF
);
5244 fprintf (stderr
, "%s\t%s:\t%s\n",
5245 GET_RTX_NAME (optab_to_code ((optab
) i
)),
5251 /* Dump the conversion optabs. */
5252 for (i
= FIRST_CONV_OPTAB
; i
<= LAST_CONVLIB_OPTAB
; ++i
)
5253 for (j
= 0; j
< NUM_MACHINE_MODES
; ++j
)
5254 for (k
= 0; k
< NUM_MACHINE_MODES
; ++k
)
5256 rtx l
= convert_optab_libfunc ((optab
) i
, (machine_mode
) j
,
5260 gcc_assert (GET_CODE (l
) == SYMBOL_REF
);
5261 fprintf (stderr
, "%s\t%s\t%s:\t%s\n",
5262 GET_RTX_NAME (optab_to_code ((optab
) i
)),
5270 /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition
5271 CODE. Return 0 on failure. */
5274 gen_cond_trap (enum rtx_code code
, rtx op1
, rtx op2
, rtx tcode
)
5276 machine_mode mode
= GET_MODE (op1
);
5277 enum insn_code icode
;
5281 if (mode
== VOIDmode
)
5284 icode
= optab_handler (ctrap_optab
, mode
);
5285 if (icode
== CODE_FOR_nothing
)
5288 /* Some targets only accept a zero trap code. */
5289 if (!insn_operand_matches (icode
, 3, tcode
))
5292 do_pending_stack_adjust ();
5294 prepare_cmp_insn (op1
, op2
, code
, NULL_RTX
, false, OPTAB_DIRECT
,
5299 insn
= GEN_FCN (icode
) (trap_rtx
, XEXP (trap_rtx
, 0), XEXP (trap_rtx
, 1),
5302 /* If that failed, then give up. */
5310 insn
= get_insns ();
5315 /* Return rtx code for TCODE. Use UNSIGNEDP to select signed
5316 or unsigned operation code. */
5319 get_rtx_code (enum tree_code tcode
, bool unsignedp
)
5331 code
= unsignedp
? LTU
: LT
;
5334 code
= unsignedp
? LEU
: LE
;
5337 code
= unsignedp
? GTU
: GT
;
5340 code
= unsignedp
? GEU
: GE
;
5343 case UNORDERED_EXPR
:
5382 /* Return a comparison rtx of mode CMP_MODE for COND. Use UNSIGNEDP to
5383 select signed or unsigned operators. OPNO holds the index of the
5384 first comparison operand for insn ICODE. Do not generate the
5385 compare instruction itself. */
5388 vector_compare_rtx (machine_mode cmp_mode
, enum tree_code tcode
,
5389 tree t_op0
, tree t_op1
, bool unsignedp
,
5390 enum insn_code icode
, unsigned int opno
)
5392 struct expand_operand ops
[2];
5393 rtx rtx_op0
, rtx_op1
;
5394 machine_mode m0
, m1
;
5395 enum rtx_code rcode
= get_rtx_code (tcode
, unsignedp
);
5397 gcc_assert (TREE_CODE_CLASS (tcode
) == tcc_comparison
);
5399 /* Expand operands. For vector types with scalar modes, e.g. where int64x1_t
5400 has mode DImode, this can produce a constant RTX of mode VOIDmode; in such
5401 cases, use the original mode. */
5402 rtx_op0
= expand_expr (t_op0
, NULL_RTX
, TYPE_MODE (TREE_TYPE (t_op0
)),
5404 m0
= GET_MODE (rtx_op0
);
5406 m0
= TYPE_MODE (TREE_TYPE (t_op0
));
5408 rtx_op1
= expand_expr (t_op1
, NULL_RTX
, TYPE_MODE (TREE_TYPE (t_op1
)),
5410 m1
= GET_MODE (rtx_op1
);
5412 m1
= TYPE_MODE (TREE_TYPE (t_op1
));
5414 create_input_operand (&ops
[0], rtx_op0
, m0
);
5415 create_input_operand (&ops
[1], rtx_op1
, m1
);
5416 if (!maybe_legitimize_operands (icode
, opno
, 2, ops
))
5418 return gen_rtx_fmt_ee (rcode
, cmp_mode
, ops
[0].value
, ops
[1].value
);
5421 /* Check if vec_perm mask SEL is a constant equivalent to a shift of
5422 the first vec_perm operand, assuming the second operand is a constant
5423 vector of zeros. Return the shift distance in bits if so, or NULL_RTX
5424 if the vec_perm is not a shift. MODE is the mode of the value being
5427 shift_amt_for_vec_perm_mask (machine_mode mode
, const vec_perm_indices
&sel
)
5429 unsigned int bitsize
= GET_MODE_UNIT_BITSIZE (mode
);
5430 poly_int64 first
= sel
[0];
5431 if (maybe_ge (sel
[0], GET_MODE_NUNITS (mode
)))
5434 if (!sel
.series_p (0, 1, first
, 1))
5437 if (!GET_MODE_NUNITS (mode
).is_constant (&nelt
))
5439 for (unsigned int i
= 1; i
< nelt
; i
++)
5441 poly_int64 expected
= i
+ first
;
5442 /* Indices into the second vector are all equivalent. */
5443 if (maybe_lt (sel
[i
], nelt
)
5444 ? maybe_ne (sel
[i
], expected
)
5445 : maybe_lt (expected
, nelt
))
5450 return gen_int_shift_amount (mode
, first
* bitsize
);
5453 /* A subroutine of expand_vec_perm_var for expanding one vec_perm insn. */
5456 expand_vec_perm_1 (enum insn_code icode
, rtx target
,
5457 rtx v0
, rtx v1
, rtx sel
)
5459 machine_mode tmode
= GET_MODE (target
);
5460 machine_mode smode
= GET_MODE (sel
);
5461 struct expand_operand ops
[4];
5463 gcc_assert (GET_MODE_CLASS (smode
) == MODE_VECTOR_INT
5464 || mode_for_int_vector (tmode
).require () == smode
);
5465 create_output_operand (&ops
[0], target
, tmode
);
5466 create_input_operand (&ops
[3], sel
, smode
);
5468 /* Make an effort to preserve v0 == v1. The target expander is able to
5469 rely on this to determine if we're permuting a single input operand. */
5470 if (rtx_equal_p (v0
, v1
))
5472 if (!insn_operand_matches (icode
, 1, v0
))
5473 v0
= force_reg (tmode
, v0
);
5474 gcc_checking_assert (insn_operand_matches (icode
, 1, v0
));
5475 gcc_checking_assert (insn_operand_matches (icode
, 2, v0
));
5477 create_fixed_operand (&ops
[1], v0
);
5478 create_fixed_operand (&ops
[2], v0
);
5482 create_input_operand (&ops
[1], v0
, tmode
);
5483 create_input_operand (&ops
[2], v1
, tmode
);
5486 if (maybe_expand_insn (icode
, 4, ops
))
5487 return ops
[0].value
;
5491 /* Implement a permutation of vectors v0 and v1 using the permutation
5492 vector in SEL and return the result. Use TARGET to hold the result
5493 if nonnull and convenient.
5495 MODE is the mode of the vectors being permuted (V0 and V1). SEL_MODE
5496 is the TYPE_MODE associated with SEL, or BLKmode if SEL isn't known
5497 to have a particular mode. */
5500 expand_vec_perm_const (machine_mode mode
, rtx v0
, rtx v1
,
5501 const vec_perm_builder
&sel
, machine_mode sel_mode
,
5504 if (!target
|| !register_operand (target
, mode
))
5505 target
= gen_reg_rtx (mode
);
5507 /* Set QIMODE to a different vector mode with byte elements.
5508 If no such mode, or if MODE already has byte elements, use VOIDmode. */
5509 machine_mode qimode
;
5510 if (!qimode_for_vec_perm (mode
).exists (&qimode
))
5513 rtx_insn
*last
= get_last_insn ();
5515 bool single_arg_p
= rtx_equal_p (v0
, v1
);
5516 /* Always specify two input vectors here and leave the target to handle
5517 cases in which the inputs are equal. Not all backends can cope with
5518 the single-input representation when testing for a double-input
5519 target instruction. */
5520 vec_perm_indices
indices (sel
, 2, GET_MODE_NUNITS (mode
));
5522 /* See if this can be handled with a vec_shr. We only do this if the
5523 second vector is all zeroes. */
5524 insn_code shift_code
= optab_handler (vec_shr_optab
, mode
);
5525 insn_code shift_code_qi
= ((qimode
!= VOIDmode
&& qimode
!= mode
)
5526 ? optab_handler (vec_shr_optab
, qimode
)
5527 : CODE_FOR_nothing
);
5529 if (v1
== CONST0_RTX (GET_MODE (v1
))
5530 && (shift_code
!= CODE_FOR_nothing
5531 || shift_code_qi
!= CODE_FOR_nothing
))
5533 rtx shift_amt
= shift_amt_for_vec_perm_mask (mode
, indices
);
5536 struct expand_operand ops
[3];
5537 if (shift_code
!= CODE_FOR_nothing
)
5539 create_output_operand (&ops
[0], target
, mode
);
5540 create_input_operand (&ops
[1], v0
, mode
);
5541 create_convert_operand_from_type (&ops
[2], shift_amt
, sizetype
);
5542 if (maybe_expand_insn (shift_code
, 3, ops
))
5543 return ops
[0].value
;
5545 if (shift_code_qi
!= CODE_FOR_nothing
)
5547 rtx tmp
= gen_reg_rtx (qimode
);
5548 create_output_operand (&ops
[0], tmp
, qimode
);
5549 create_input_operand (&ops
[1], gen_lowpart (qimode
, v0
), qimode
);
5550 create_convert_operand_from_type (&ops
[2], shift_amt
, sizetype
);
5551 if (maybe_expand_insn (shift_code_qi
, 3, ops
))
5552 return gen_lowpart (mode
, ops
[0].value
);
5557 if (targetm
.vectorize
.vec_perm_const
!= NULL
)
5559 v0
= force_reg (mode
, v0
);
5563 v1
= force_reg (mode
, v1
);
5565 if (targetm
.vectorize
.vec_perm_const (mode
, target
, v0
, v1
, indices
))
5569 /* Fall back to a constant byte-based permutation. */
5570 vec_perm_indices qimode_indices
;
5571 rtx target_qi
= NULL_RTX
, v0_qi
= NULL_RTX
, v1_qi
= NULL_RTX
;
5572 if (qimode
!= VOIDmode
)
5574 qimode_indices
.new_expanded_vector (indices
, GET_MODE_UNIT_SIZE (mode
));
5575 target_qi
= gen_reg_rtx (qimode
);
5576 v0_qi
= gen_lowpart (qimode
, v0
);
5577 v1_qi
= gen_lowpart (qimode
, v1
);
5578 if (targetm
.vectorize
.vec_perm_const
!= NULL
5579 && targetm
.vectorize
.vec_perm_const (qimode
, target_qi
, v0_qi
,
5580 v1_qi
, qimode_indices
))
5581 return gen_lowpart (mode
, target_qi
);
5584 /* Otherwise expand as a fully variable permuation. */
5586 /* The optabs are only defined for selectors with the same width
5587 as the values being permuted. */
5588 machine_mode required_sel_mode
;
5589 if (!mode_for_int_vector (mode
).exists (&required_sel_mode
)
5590 || !VECTOR_MODE_P (required_sel_mode
))
5592 delete_insns_since (last
);
5596 /* We know that it is semantically valid to treat SEL as having SEL_MODE.
5597 If that isn't the mode we want then we need to prove that using
5598 REQUIRED_SEL_MODE is OK. */
5599 if (sel_mode
!= required_sel_mode
)
5601 if (!selector_fits_mode_p (required_sel_mode
, indices
))
5603 delete_insns_since (last
);
5606 sel_mode
= required_sel_mode
;
5609 insn_code icode
= direct_optab_handler (vec_perm_optab
, mode
);
5610 if (icode
!= CODE_FOR_nothing
)
5612 rtx sel_rtx
= vec_perm_indices_to_rtx (sel_mode
, indices
);
5613 rtx tmp
= expand_vec_perm_1 (icode
, target
, v0
, v1
, sel_rtx
);
5618 if (qimode
!= VOIDmode
5619 && selector_fits_mode_p (qimode
, qimode_indices
))
5621 icode
= direct_optab_handler (vec_perm_optab
, qimode
);
5622 if (icode
!= CODE_FOR_nothing
)
5624 rtx sel_qi
= vec_perm_indices_to_rtx (qimode
, qimode_indices
);
5625 rtx tmp
= expand_vec_perm_1 (icode
, target_qi
, v0_qi
, v1_qi
, sel_qi
);
5627 return gen_lowpart (mode
, tmp
);
5631 delete_insns_since (last
);
5635 /* Implement a permutation of vectors v0 and v1 using the permutation
5636 vector in SEL and return the result. Use TARGET to hold the result
5637 if nonnull and convenient.
5639 MODE is the mode of the vectors being permuted (V0 and V1).
5640 SEL must have the integer equivalent of MODE and is known to be
5641 unsuitable for permutes with a constant permutation vector. */
5644 expand_vec_perm_var (machine_mode mode
, rtx v0
, rtx v1
, rtx sel
, rtx target
)
5646 enum insn_code icode
;
5650 u
= GET_MODE_UNIT_SIZE (mode
);
5652 if (!target
|| GET_MODE (target
) != mode
)
5653 target
= gen_reg_rtx (mode
);
5655 icode
= direct_optab_handler (vec_perm_optab
, mode
);
5656 if (icode
!= CODE_FOR_nothing
)
5658 tmp
= expand_vec_perm_1 (icode
, target
, v0
, v1
, sel
);
5663 /* As a special case to aid several targets, lower the element-based
5664 permutation to a byte-based permutation and try again. */
5665 machine_mode qimode
;
5666 if (!qimode_for_vec_perm (mode
).exists (&qimode
)
5667 || maybe_gt (GET_MODE_NUNITS (qimode
), GET_MODE_MASK (QImode
) + 1))
5669 icode
= direct_optab_handler (vec_perm_optab
, qimode
);
5670 if (icode
== CODE_FOR_nothing
)
5673 /* Multiply each element by its byte size. */
5674 machine_mode selmode
= GET_MODE (sel
);
5676 sel
= expand_simple_binop (selmode
, PLUS
, sel
, sel
,
5677 NULL
, 0, OPTAB_DIRECT
);
5679 sel
= expand_simple_binop (selmode
, ASHIFT
, sel
,
5680 gen_int_shift_amount (selmode
, exact_log2 (u
)),
5681 NULL
, 0, OPTAB_DIRECT
);
5682 gcc_assert (sel
!= NULL
);
5684 /* Broadcast the low byte each element into each of its bytes.
5685 The encoding has U interleaved stepped patterns, one for each
5686 byte of an element. */
5687 vec_perm_builder
const_sel (GET_MODE_SIZE (mode
), u
, 3);
5688 unsigned int low_byte_in_u
= BYTES_BIG_ENDIAN
? u
- 1 : 0;
5689 for (i
= 0; i
< 3; ++i
)
5690 for (unsigned int j
= 0; j
< u
; ++j
)
5691 const_sel
.quick_push (i
* u
+ low_byte_in_u
);
5692 sel
= gen_lowpart (qimode
, sel
);
5693 sel
= expand_vec_perm_const (qimode
, sel
, sel
, const_sel
, qimode
, NULL
);
5694 gcc_assert (sel
!= NULL
);
5696 /* Add the byte offset to each byte element. */
5697 /* Note that the definition of the indicies here is memory ordering,
5698 so there should be no difference between big and little endian. */
5699 rtx_vector_builder
byte_indices (qimode
, u
, 1);
5700 for (i
= 0; i
< u
; ++i
)
5701 byte_indices
.quick_push (GEN_INT (i
));
5702 tmp
= byte_indices
.build ();
5703 sel_qi
= expand_simple_binop (qimode
, PLUS
, sel
, tmp
,
5704 sel
, 0, OPTAB_DIRECT
);
5705 gcc_assert (sel_qi
!= NULL
);
5707 tmp
= mode
!= qimode
? gen_reg_rtx (qimode
) : target
;
5708 tmp
= expand_vec_perm_1 (icode
, tmp
, gen_lowpart (qimode
, v0
),
5709 gen_lowpart (qimode
, v1
), sel_qi
);
5711 tmp
= gen_lowpart (mode
, tmp
);
5715 /* Generate insns for a VEC_COND_EXPR with mask, given its TYPE and its
5719 expand_vec_cond_mask_expr (tree vec_cond_type
, tree op0
, tree op1
, tree op2
,
5722 struct expand_operand ops
[4];
5723 machine_mode mode
= TYPE_MODE (vec_cond_type
);
5724 machine_mode mask_mode
= TYPE_MODE (TREE_TYPE (op0
));
5725 enum insn_code icode
= get_vcond_mask_icode (mode
, mask_mode
);
5726 rtx mask
, rtx_op1
, rtx_op2
;
5728 if (icode
== CODE_FOR_nothing
)
5731 mask
= expand_normal (op0
);
5732 rtx_op1
= expand_normal (op1
);
5733 rtx_op2
= expand_normal (op2
);
5735 mask
= force_reg (mask_mode
, mask
);
5736 rtx_op1
= force_reg (GET_MODE (rtx_op1
), rtx_op1
);
5738 create_output_operand (&ops
[0], target
, mode
);
5739 create_input_operand (&ops
[1], rtx_op1
, mode
);
5740 create_input_operand (&ops
[2], rtx_op2
, mode
);
5741 create_input_operand (&ops
[3], mask
, mask_mode
);
5742 expand_insn (icode
, 4, ops
);
5744 return ops
[0].value
;
5747 /* Generate insns for a VEC_COND_EXPR, given its TYPE and its
5751 expand_vec_cond_expr (tree vec_cond_type
, tree op0
, tree op1
, tree op2
,
5754 struct expand_operand ops
[6];
5755 enum insn_code icode
;
5756 rtx comparison
, rtx_op1
, rtx_op2
;
5757 machine_mode mode
= TYPE_MODE (vec_cond_type
);
5758 machine_mode cmp_op_mode
;
5761 enum tree_code tcode
;
5763 if (COMPARISON_CLASS_P (op0
))
5765 op0a
= TREE_OPERAND (op0
, 0);
5766 op0b
= TREE_OPERAND (op0
, 1);
5767 tcode
= TREE_CODE (op0
);
5771 gcc_assert (VECTOR_BOOLEAN_TYPE_P (TREE_TYPE (op0
)));
5772 if (get_vcond_mask_icode (mode
, TYPE_MODE (TREE_TYPE (op0
)))
5773 != CODE_FOR_nothing
)
5774 return expand_vec_cond_mask_expr (vec_cond_type
, op0
, op1
,
5779 gcc_assert (GET_MODE_CLASS (TYPE_MODE (TREE_TYPE (op0
)))
5780 == MODE_VECTOR_INT
);
5782 op0b
= build_zero_cst (TREE_TYPE (op0
));
5786 cmp_op_mode
= TYPE_MODE (TREE_TYPE (op0a
));
5787 unsignedp
= TYPE_UNSIGNED (TREE_TYPE (op0a
));
5790 gcc_assert (known_eq (GET_MODE_SIZE (mode
), GET_MODE_SIZE (cmp_op_mode
))
5791 && known_eq (GET_MODE_NUNITS (mode
),
5792 GET_MODE_NUNITS (cmp_op_mode
)));
5794 icode
= get_vcond_icode (mode
, cmp_op_mode
, unsignedp
);
5795 if (icode
== CODE_FOR_nothing
)
5797 if (tcode
== EQ_EXPR
|| tcode
== NE_EXPR
)
5798 icode
= get_vcond_eq_icode (mode
, cmp_op_mode
);
5799 if (icode
== CODE_FOR_nothing
)
5803 comparison
= vector_compare_rtx (VOIDmode
, tcode
, op0a
, op0b
, unsignedp
,
5805 rtx_op1
= expand_normal (op1
);
5806 rtx_op2
= expand_normal (op2
);
5808 create_output_operand (&ops
[0], target
, mode
);
5809 create_input_operand (&ops
[1], rtx_op1
, mode
);
5810 create_input_operand (&ops
[2], rtx_op2
, mode
);
5811 create_fixed_operand (&ops
[3], comparison
);
5812 create_fixed_operand (&ops
[4], XEXP (comparison
, 0));
5813 create_fixed_operand (&ops
[5], XEXP (comparison
, 1));
5814 expand_insn (icode
, 6, ops
);
5815 return ops
[0].value
;
5818 /* Generate VEC_SERIES_EXPR <OP0, OP1>, returning a value of mode VMODE.
5819 Use TARGET for the result if nonnull and convenient. */
5822 expand_vec_series_expr (machine_mode vmode
, rtx op0
, rtx op1
, rtx target
)
5824 struct expand_operand ops
[3];
5825 enum insn_code icode
;
5826 machine_mode emode
= GET_MODE_INNER (vmode
);
5828 icode
= direct_optab_handler (vec_series_optab
, vmode
);
5829 gcc_assert (icode
!= CODE_FOR_nothing
);
5831 create_output_operand (&ops
[0], target
, vmode
);
5832 create_input_operand (&ops
[1], op0
, emode
);
5833 create_input_operand (&ops
[2], op1
, emode
);
5835 expand_insn (icode
, 3, ops
);
5836 return ops
[0].value
;
5839 /* Generate insns for a vector comparison into a mask. */
5842 expand_vec_cmp_expr (tree type
, tree exp
, rtx target
)
5844 struct expand_operand ops
[4];
5845 enum insn_code icode
;
5847 machine_mode mask_mode
= TYPE_MODE (type
);
5851 enum tree_code tcode
;
5853 op0a
= TREE_OPERAND (exp
, 0);
5854 op0b
= TREE_OPERAND (exp
, 1);
5855 tcode
= TREE_CODE (exp
);
5857 unsignedp
= TYPE_UNSIGNED (TREE_TYPE (op0a
));
5858 vmode
= TYPE_MODE (TREE_TYPE (op0a
));
5860 icode
= get_vec_cmp_icode (vmode
, mask_mode
, unsignedp
);
5861 if (icode
== CODE_FOR_nothing
)
5863 if (tcode
== EQ_EXPR
|| tcode
== NE_EXPR
)
5864 icode
= get_vec_cmp_eq_icode (vmode
, mask_mode
);
5865 if (icode
== CODE_FOR_nothing
)
5869 comparison
= vector_compare_rtx (mask_mode
, tcode
, op0a
, op0b
,
5870 unsignedp
, icode
, 2);
5871 create_output_operand (&ops
[0], target
, mask_mode
);
5872 create_fixed_operand (&ops
[1], comparison
);
5873 create_fixed_operand (&ops
[2], XEXP (comparison
, 0));
5874 create_fixed_operand (&ops
[3], XEXP (comparison
, 1));
5875 expand_insn (icode
, 4, ops
);
5876 return ops
[0].value
;
5879 /* Expand a highpart multiply. */
5882 expand_mult_highpart (machine_mode mode
, rtx op0
, rtx op1
,
5883 rtx target
, bool uns_p
)
5885 struct expand_operand eops
[3];
5886 enum insn_code icode
;
5892 method
= can_mult_highpart_p (mode
, uns_p
);
5898 tab1
= uns_p
? umul_highpart_optab
: smul_highpart_optab
;
5899 return expand_binop (mode
, tab1
, op0
, op1
, target
, uns_p
,
5902 tab1
= uns_p
? vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
5903 tab2
= uns_p
? vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
5906 tab1
= uns_p
? vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
5907 tab2
= uns_p
? vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
5908 if (BYTES_BIG_ENDIAN
)
5909 std::swap (tab1
, tab2
);
5915 icode
= optab_handler (tab1
, mode
);
5916 wmode
= insn_data
[icode
].operand
[0].mode
;
5917 gcc_checking_assert (known_eq (2 * GET_MODE_NUNITS (wmode
),
5918 GET_MODE_NUNITS (mode
)));
5919 gcc_checking_assert (known_eq (GET_MODE_SIZE (wmode
), GET_MODE_SIZE (mode
)));
5921 create_output_operand (&eops
[0], gen_reg_rtx (wmode
), wmode
);
5922 create_input_operand (&eops
[1], op0
, mode
);
5923 create_input_operand (&eops
[2], op1
, mode
);
5924 expand_insn (icode
, 3, eops
);
5925 m1
= gen_lowpart (mode
, eops
[0].value
);
5927 create_output_operand (&eops
[0], gen_reg_rtx (wmode
), wmode
);
5928 create_input_operand (&eops
[1], op0
, mode
);
5929 create_input_operand (&eops
[2], op1
, mode
);
5930 expand_insn (optab_handler (tab2
, mode
), 3, eops
);
5931 m2
= gen_lowpart (mode
, eops
[0].value
);
5933 vec_perm_builder sel
;
5936 /* The encoding has 2 interleaved stepped patterns. */
5937 sel
.new_vector (GET_MODE_NUNITS (mode
), 2, 3);
5938 for (i
= 0; i
< 6; ++i
)
5939 sel
.quick_push (!BYTES_BIG_ENDIAN
+ (i
& ~1)
5940 + ((i
& 1) ? GET_MODE_NUNITS (mode
) : 0));
5944 /* The encoding has a single interleaved stepped pattern. */
5945 sel
.new_vector (GET_MODE_NUNITS (mode
), 1, 3);
5946 for (i
= 0; i
< 3; ++i
)
5947 sel
.quick_push (2 * i
+ (BYTES_BIG_ENDIAN
? 0 : 1));
5950 return expand_vec_perm_const (mode
, m1
, m2
, sel
, BLKmode
, target
);
5953 /* Helper function to find the MODE_CC set in a sync_compare_and_swap
5957 find_cc_set (rtx x
, const_rtx pat
, void *data
)
5959 if (REG_P (x
) && GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
5960 && GET_CODE (pat
) == SET
)
5962 rtx
*p_cc_reg
= (rtx
*) data
;
5963 gcc_assert (!*p_cc_reg
);
5968 /* This is a helper function for the other atomic operations. This function
5969 emits a loop that contains SEQ that iterates until a compare-and-swap
5970 operation at the end succeeds. MEM is the memory to be modified. SEQ is
5971 a set of instructions that takes a value from OLD_REG as an input and
5972 produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be
5973 set to the current contents of MEM. After SEQ, a compare-and-swap will
5974 attempt to update MEM with NEW_REG. The function returns true when the
5975 loop was generated successfully. */
5978 expand_compare_and_swap_loop (rtx mem
, rtx old_reg
, rtx new_reg
, rtx seq
)
5980 machine_mode mode
= GET_MODE (mem
);
5981 rtx_code_label
*label
;
5982 rtx cmp_reg
, success
, oldval
;
5984 /* The loop we want to generate looks like
5990 (success, cmp_reg) = compare-and-swap(mem, old_reg, new_reg)
5994 Note that we only do the plain load from memory once. Subsequent
5995 iterations use the value loaded by the compare-and-swap pattern. */
5997 label
= gen_label_rtx ();
5998 cmp_reg
= gen_reg_rtx (mode
);
6000 emit_move_insn (cmp_reg
, mem
);
6002 emit_move_insn (old_reg
, cmp_reg
);
6008 if (!expand_atomic_compare_and_swap (&success
, &oldval
, mem
, old_reg
,
6009 new_reg
, false, MEMMODEL_SYNC_SEQ_CST
,
6013 if (oldval
!= cmp_reg
)
6014 emit_move_insn (cmp_reg
, oldval
);
6016 /* Mark this jump predicted not taken. */
6017 emit_cmp_and_jump_insns (success
, const0_rtx
, EQ
, const0_rtx
,
6018 GET_MODE (success
), 1, label
,
6019 profile_probability::guessed_never ());
6024 /* This function tries to emit an atomic_exchange intruction. VAL is written
6025 to *MEM using memory model MODEL. The previous contents of *MEM are returned,
6026 using TARGET if possible. */
6029 maybe_emit_atomic_exchange (rtx target
, rtx mem
, rtx val
, enum memmodel model
)
6031 machine_mode mode
= GET_MODE (mem
);
6032 enum insn_code icode
;
6034 /* If the target supports the exchange directly, great. */
6035 icode
= direct_optab_handler (atomic_exchange_optab
, mode
);
6036 if (icode
!= CODE_FOR_nothing
)
6038 struct expand_operand ops
[4];
6040 create_output_operand (&ops
[0], target
, mode
);
6041 create_fixed_operand (&ops
[1], mem
);
6042 create_input_operand (&ops
[2], val
, mode
);
6043 create_integer_operand (&ops
[3], model
);
6044 if (maybe_expand_insn (icode
, 4, ops
))
6045 return ops
[0].value
;
6051 /* This function tries to implement an atomic exchange operation using
6052 __sync_lock_test_and_set. VAL is written to *MEM using memory model MODEL.
6053 The previous contents of *MEM are returned, using TARGET if possible.
6054 Since this instructionn is an acquire barrier only, stronger memory
6055 models may require additional barriers to be emitted. */
6058 maybe_emit_sync_lock_test_and_set (rtx target
, rtx mem
, rtx val
,
6059 enum memmodel model
)
6061 machine_mode mode
= GET_MODE (mem
);
6062 enum insn_code icode
;
6063 rtx_insn
*last_insn
= get_last_insn ();
6065 icode
= optab_handler (sync_lock_test_and_set_optab
, mode
);
6067 /* Legacy sync_lock_test_and_set is an acquire barrier. If the pattern
6068 exists, and the memory model is stronger than acquire, add a release
6069 barrier before the instruction. */
6071 if (is_mm_seq_cst (model
) || is_mm_release (model
) || is_mm_acq_rel (model
))
6072 expand_mem_thread_fence (model
);
6074 if (icode
!= CODE_FOR_nothing
)
6076 struct expand_operand ops
[3];
6077 create_output_operand (&ops
[0], target
, mode
);
6078 create_fixed_operand (&ops
[1], mem
);
6079 create_input_operand (&ops
[2], val
, mode
);
6080 if (maybe_expand_insn (icode
, 3, ops
))
6081 return ops
[0].value
;
6084 /* If an external test-and-set libcall is provided, use that instead of
6085 any external compare-and-swap that we might get from the compare-and-
6086 swap-loop expansion later. */
6087 if (!can_compare_and_swap_p (mode
, false))
6089 rtx libfunc
= optab_libfunc (sync_lock_test_and_set_optab
, mode
);
6090 if (libfunc
!= NULL
)
6094 addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
6095 return emit_library_call_value (libfunc
, NULL_RTX
, LCT_NORMAL
,
6096 mode
, addr
, ptr_mode
,
6101 /* If the test_and_set can't be emitted, eliminate any barrier that might
6102 have been emitted. */
6103 delete_insns_since (last_insn
);
6107 /* This function tries to implement an atomic exchange operation using a
6108 compare_and_swap loop. VAL is written to *MEM. The previous contents of
6109 *MEM are returned, using TARGET if possible. No memory model is required
6110 since a compare_and_swap loop is seq-cst. */
6113 maybe_emit_compare_and_swap_exchange_loop (rtx target
, rtx mem
, rtx val
)
6115 machine_mode mode
= GET_MODE (mem
);
6117 if (can_compare_and_swap_p (mode
, true))
6119 if (!target
|| !register_operand (target
, mode
))
6120 target
= gen_reg_rtx (mode
);
6121 if (expand_compare_and_swap_loop (mem
, target
, val
, NULL_RTX
))
6128 /* This function tries to implement an atomic test-and-set operation
6129 using the atomic_test_and_set instruction pattern. A boolean value
6130 is returned from the operation, using TARGET if possible. */
6133 maybe_emit_atomic_test_and_set (rtx target
, rtx mem
, enum memmodel model
)
6135 machine_mode pat_bool_mode
;
6136 struct expand_operand ops
[3];
6138 if (!targetm
.have_atomic_test_and_set ())
6141 /* While we always get QImode from __atomic_test_and_set, we get
6142 other memory modes from __sync_lock_test_and_set. Note that we
6143 use no endian adjustment here. This matches the 4.6 behavior
6144 in the Sparc backend. */
6145 enum insn_code icode
= targetm
.code_for_atomic_test_and_set
;
6146 gcc_checking_assert (insn_data
[icode
].operand
[1].mode
== QImode
);
6147 if (GET_MODE (mem
) != QImode
)
6148 mem
= adjust_address_nv (mem
, QImode
, 0);
6150 pat_bool_mode
= insn_data
[icode
].operand
[0].mode
;
6151 create_output_operand (&ops
[0], target
, pat_bool_mode
);
6152 create_fixed_operand (&ops
[1], mem
);
6153 create_integer_operand (&ops
[2], model
);
6155 if (maybe_expand_insn (icode
, 3, ops
))
6156 return ops
[0].value
;
6160 /* This function expands the legacy _sync_lock test_and_set operation which is
6161 generally an atomic exchange. Some limited targets only allow the
6162 constant 1 to be stored. This is an ACQUIRE operation.
6164 TARGET is an optional place to stick the return value.
6165 MEM is where VAL is stored. */
6168 expand_sync_lock_test_and_set (rtx target
, rtx mem
, rtx val
)
6172 /* Try an atomic_exchange first. */
6173 ret
= maybe_emit_atomic_exchange (target
, mem
, val
, MEMMODEL_SYNC_ACQUIRE
);
6177 ret
= maybe_emit_sync_lock_test_and_set (target
, mem
, val
,
6178 MEMMODEL_SYNC_ACQUIRE
);
6182 ret
= maybe_emit_compare_and_swap_exchange_loop (target
, mem
, val
);
6186 /* If there are no other options, try atomic_test_and_set if the value
6187 being stored is 1. */
6188 if (val
== const1_rtx
)
6189 ret
= maybe_emit_atomic_test_and_set (target
, mem
, MEMMODEL_SYNC_ACQUIRE
);
6194 /* This function expands the atomic test_and_set operation:
6195 atomically store a boolean TRUE into MEM and return the previous value.
6197 MEMMODEL is the memory model variant to use.
6198 TARGET is an optional place to stick the return value. */
6201 expand_atomic_test_and_set (rtx target
, rtx mem
, enum memmodel model
)
6203 machine_mode mode
= GET_MODE (mem
);
6204 rtx ret
, trueval
, subtarget
;
6206 ret
= maybe_emit_atomic_test_and_set (target
, mem
, model
);
6210 /* Be binary compatible with non-default settings of trueval, and different
6211 cpu revisions. E.g. one revision may have atomic-test-and-set, but
6212 another only has atomic-exchange. */
6213 if (targetm
.atomic_test_and_set_trueval
== 1)
6215 trueval
= const1_rtx
;
6216 subtarget
= target
? target
: gen_reg_rtx (mode
);
6220 trueval
= gen_int_mode (targetm
.atomic_test_and_set_trueval
, mode
);
6221 subtarget
= gen_reg_rtx (mode
);
6224 /* Try the atomic-exchange optab... */
6225 ret
= maybe_emit_atomic_exchange (subtarget
, mem
, trueval
, model
);
6227 /* ... then an atomic-compare-and-swap loop ... */
6229 ret
= maybe_emit_compare_and_swap_exchange_loop (subtarget
, mem
, trueval
);
6231 /* ... before trying the vaguely defined legacy lock_test_and_set. */
6233 ret
= maybe_emit_sync_lock_test_and_set (subtarget
, mem
, trueval
, model
);
6235 /* Recall that the legacy lock_test_and_set optab was allowed to do magic
6236 things with the value 1. Thus we try again without trueval. */
6237 if (!ret
&& targetm
.atomic_test_and_set_trueval
!= 1)
6238 ret
= maybe_emit_sync_lock_test_and_set (subtarget
, mem
, const1_rtx
, model
);
6240 /* Failing all else, assume a single threaded environment and simply
6241 perform the operation. */
6244 /* If the result is ignored skip the move to target. */
6245 if (subtarget
!= const0_rtx
)
6246 emit_move_insn (subtarget
, mem
);
6248 emit_move_insn (mem
, trueval
);
6252 /* Recall that have to return a boolean value; rectify if trueval
6253 is not exactly one. */
6254 if (targetm
.atomic_test_and_set_trueval
!= 1)
6255 ret
= emit_store_flag_force (target
, NE
, ret
, const0_rtx
, mode
, 0, 1);
6260 /* This function expands the atomic exchange operation:
6261 atomically store VAL in MEM and return the previous value in MEM.
6263 MEMMODEL is the memory model variant to use.
6264 TARGET is an optional place to stick the return value. */
6267 expand_atomic_exchange (rtx target
, rtx mem
, rtx val
, enum memmodel model
)
6269 machine_mode mode
= GET_MODE (mem
);
6272 /* If loads are not atomic for the required size and we are not called to
6273 provide a __sync builtin, do not do anything so that we stay consistent
6274 with atomic loads of the same size. */
6275 if (!can_atomic_load_p (mode
) && !is_mm_sync (model
))
6278 ret
= maybe_emit_atomic_exchange (target
, mem
, val
, model
);
6280 /* Next try a compare-and-swap loop for the exchange. */
6282 ret
= maybe_emit_compare_and_swap_exchange_loop (target
, mem
, val
);
6287 /* This function expands the atomic compare exchange operation:
6289 *PTARGET_BOOL is an optional place to store the boolean success/failure.
6290 *PTARGET_OVAL is an optional place to store the old value from memory.
6291 Both target parameters may be NULL or const0_rtx to indicate that we do
6292 not care about that return value. Both target parameters are updated on
6293 success to the actual location of the corresponding result.
6295 MEMMODEL is the memory model variant to use.
6297 The return value of the function is true for success. */
6300 expand_atomic_compare_and_swap (rtx
*ptarget_bool
, rtx
*ptarget_oval
,
6301 rtx mem
, rtx expected
, rtx desired
,
6302 bool is_weak
, enum memmodel succ_model
,
6303 enum memmodel fail_model
)
6305 machine_mode mode
= GET_MODE (mem
);
6306 struct expand_operand ops
[8];
6307 enum insn_code icode
;
6308 rtx target_oval
, target_bool
= NULL_RTX
;
6311 /* If loads are not atomic for the required size and we are not called to
6312 provide a __sync builtin, do not do anything so that we stay consistent
6313 with atomic loads of the same size. */
6314 if (!can_atomic_load_p (mode
) && !is_mm_sync (succ_model
))
6317 /* Load expected into a register for the compare and swap. */
6318 if (MEM_P (expected
))
6319 expected
= copy_to_reg (expected
);
6321 /* Make sure we always have some place to put the return oldval.
6322 Further, make sure that place is distinct from the input expected,
6323 just in case we need that path down below. */
6324 if (ptarget_oval
&& *ptarget_oval
== const0_rtx
)
6325 ptarget_oval
= NULL
;
6327 if (ptarget_oval
== NULL
6328 || (target_oval
= *ptarget_oval
) == NULL
6329 || reg_overlap_mentioned_p (expected
, target_oval
))
6330 target_oval
= gen_reg_rtx (mode
);
6332 icode
= direct_optab_handler (atomic_compare_and_swap_optab
, mode
);
6333 if (icode
!= CODE_FOR_nothing
)
6335 machine_mode bool_mode
= insn_data
[icode
].operand
[0].mode
;
6337 if (ptarget_bool
&& *ptarget_bool
== const0_rtx
)
6338 ptarget_bool
= NULL
;
6340 /* Make sure we always have a place for the bool operand. */
6341 if (ptarget_bool
== NULL
6342 || (target_bool
= *ptarget_bool
) == NULL
6343 || GET_MODE (target_bool
) != bool_mode
)
6344 target_bool
= gen_reg_rtx (bool_mode
);
6346 /* Emit the compare_and_swap. */
6347 create_output_operand (&ops
[0], target_bool
, bool_mode
);
6348 create_output_operand (&ops
[1], target_oval
, mode
);
6349 create_fixed_operand (&ops
[2], mem
);
6350 create_input_operand (&ops
[3], expected
, mode
);
6351 create_input_operand (&ops
[4], desired
, mode
);
6352 create_integer_operand (&ops
[5], is_weak
);
6353 create_integer_operand (&ops
[6], succ_model
);
6354 create_integer_operand (&ops
[7], fail_model
);
6355 if (maybe_expand_insn (icode
, 8, ops
))
6357 /* Return success/failure. */
6358 target_bool
= ops
[0].value
;
6359 target_oval
= ops
[1].value
;
6364 /* Otherwise fall back to the original __sync_val_compare_and_swap
6365 which is always seq-cst. */
6366 icode
= optab_handler (sync_compare_and_swap_optab
, mode
);
6367 if (icode
!= CODE_FOR_nothing
)
6371 create_output_operand (&ops
[0], target_oval
, mode
);
6372 create_fixed_operand (&ops
[1], mem
);
6373 create_input_operand (&ops
[2], expected
, mode
);
6374 create_input_operand (&ops
[3], desired
, mode
);
6375 if (!maybe_expand_insn (icode
, 4, ops
))
6378 target_oval
= ops
[0].value
;
6380 /* If the caller isn't interested in the boolean return value,
6381 skip the computation of it. */
6382 if (ptarget_bool
== NULL
)
6385 /* Otherwise, work out if the compare-and-swap succeeded. */
6387 if (have_insn_for (COMPARE
, CCmode
))
6388 note_stores (PATTERN (get_last_insn ()), find_cc_set
, &cc_reg
);
6391 target_bool
= emit_store_flag_force (target_bool
, EQ
, cc_reg
,
6392 const0_rtx
, VOIDmode
, 0, 1);
6395 goto success_bool_from_val
;
6398 /* Also check for library support for __sync_val_compare_and_swap. */
6399 libfunc
= optab_libfunc (sync_compare_and_swap_optab
, mode
);
6400 if (libfunc
!= NULL
)
6402 rtx addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
6403 rtx target
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_NORMAL
,
6404 mode
, addr
, ptr_mode
,
6405 expected
, mode
, desired
, mode
);
6406 emit_move_insn (target_oval
, target
);
6408 /* Compute the boolean return value only if requested. */
6410 goto success_bool_from_val
;
6418 success_bool_from_val
:
6419 target_bool
= emit_store_flag_force (target_bool
, EQ
, target_oval
,
6420 expected
, VOIDmode
, 1, 1);
6422 /* Make sure that the oval output winds up where the caller asked. */
6424 *ptarget_oval
= target_oval
;
6426 *ptarget_bool
= target_bool
;
6430 /* Generate asm volatile("" : : : "memory") as the memory blockage. */
6433 expand_asm_memory_blockage (void)
6437 asm_op
= gen_rtx_ASM_OPERANDS (VOIDmode
, "", "", 0,
6438 rtvec_alloc (0), rtvec_alloc (0),
6439 rtvec_alloc (0), UNKNOWN_LOCATION
);
6440 MEM_VOLATILE_P (asm_op
) = 1;
6442 clob
= gen_rtx_SCRATCH (VOIDmode
);
6443 clob
= gen_rtx_MEM (BLKmode
, clob
);
6444 clob
= gen_rtx_CLOBBER (VOIDmode
, clob
);
6446 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, asm_op
, clob
)));
6449 /* Do not propagate memory accesses across this point. */
6452 expand_memory_blockage (void)
6454 if (targetm
.have_memory_blockage ())
6455 emit_insn (targetm
.gen_memory_blockage ());
6457 expand_asm_memory_blockage ();
6460 /* This routine will either emit the mem_thread_fence pattern or issue a
6461 sync_synchronize to generate a fence for memory model MEMMODEL. */
6464 expand_mem_thread_fence (enum memmodel model
)
6466 if (is_mm_relaxed (model
))
6468 if (targetm
.have_mem_thread_fence ())
6470 emit_insn (targetm
.gen_mem_thread_fence (GEN_INT (model
)));
6471 expand_memory_blockage ();
6473 else if (targetm
.have_memory_barrier ())
6474 emit_insn (targetm
.gen_memory_barrier ());
6475 else if (synchronize_libfunc
!= NULL_RTX
)
6476 emit_library_call (synchronize_libfunc
, LCT_NORMAL
, VOIDmode
);
6478 expand_memory_blockage ();
6481 /* Emit a signal fence with given memory model. */
6484 expand_mem_signal_fence (enum memmodel model
)
6486 /* No machine barrier is required to implement a signal fence, but
6487 a compiler memory barrier must be issued, except for relaxed MM. */
6488 if (!is_mm_relaxed (model
))
6489 expand_memory_blockage ();
6492 /* This function expands the atomic load operation:
6493 return the atomically loaded value in MEM.
6495 MEMMODEL is the memory model variant to use.
6496 TARGET is an option place to stick the return value. */
6499 expand_atomic_load (rtx target
, rtx mem
, enum memmodel model
)
6501 machine_mode mode
= GET_MODE (mem
);
6502 enum insn_code icode
;
6504 /* If the target supports the load directly, great. */
6505 icode
= direct_optab_handler (atomic_load_optab
, mode
);
6506 if (icode
!= CODE_FOR_nothing
)
6508 struct expand_operand ops
[3];
6509 rtx_insn
*last
= get_last_insn ();
6510 if (is_mm_seq_cst (model
))
6511 expand_memory_blockage ();
6513 create_output_operand (&ops
[0], target
, mode
);
6514 create_fixed_operand (&ops
[1], mem
);
6515 create_integer_operand (&ops
[2], model
);
6516 if (maybe_expand_insn (icode
, 3, ops
))
6518 if (!is_mm_relaxed (model
))
6519 expand_memory_blockage ();
6520 return ops
[0].value
;
6522 delete_insns_since (last
);
6525 /* If the size of the object is greater than word size on this target,
6526 then we assume that a load will not be atomic. We could try to
6527 emulate a load with a compare-and-swap operation, but the store that
6528 doing this could result in would be incorrect if this is a volatile
6529 atomic load or targetting read-only-mapped memory. */
6530 if (maybe_gt (GET_MODE_PRECISION (mode
), BITS_PER_WORD
))
6531 /* If there is no atomic load, leave the library call. */
6534 /* Otherwise assume loads are atomic, and emit the proper barriers. */
6535 if (!target
|| target
== const0_rtx
)
6536 target
= gen_reg_rtx (mode
);
6538 /* For SEQ_CST, emit a barrier before the load. */
6539 if (is_mm_seq_cst (model
))
6540 expand_mem_thread_fence (model
);
6542 emit_move_insn (target
, mem
);
6544 /* Emit the appropriate barrier after the load. */
6545 expand_mem_thread_fence (model
);
6550 /* This function expands the atomic store operation:
6551 Atomically store VAL in MEM.
6552 MEMMODEL is the memory model variant to use.
6553 USE_RELEASE is true if __sync_lock_release can be used as a fall back.
6554 function returns const0_rtx if a pattern was emitted. */
6557 expand_atomic_store (rtx mem
, rtx val
, enum memmodel model
, bool use_release
)
6559 machine_mode mode
= GET_MODE (mem
);
6560 enum insn_code icode
;
6561 struct expand_operand ops
[3];
6563 /* If the target supports the store directly, great. */
6564 icode
= direct_optab_handler (atomic_store_optab
, mode
);
6565 if (icode
!= CODE_FOR_nothing
)
6567 rtx_insn
*last
= get_last_insn ();
6568 if (!is_mm_relaxed (model
))
6569 expand_memory_blockage ();
6570 create_fixed_operand (&ops
[0], mem
);
6571 create_input_operand (&ops
[1], val
, mode
);
6572 create_integer_operand (&ops
[2], model
);
6573 if (maybe_expand_insn (icode
, 3, ops
))
6575 if (is_mm_seq_cst (model
))
6576 expand_memory_blockage ();
6579 delete_insns_since (last
);
6582 /* If using __sync_lock_release is a viable alternative, try it.
6583 Note that this will not be set to true if we are expanding a generic
6584 __atomic_store_n. */
6587 icode
= direct_optab_handler (sync_lock_release_optab
, mode
);
6588 if (icode
!= CODE_FOR_nothing
)
6590 create_fixed_operand (&ops
[0], mem
);
6591 create_input_operand (&ops
[1], const0_rtx
, mode
);
6592 if (maybe_expand_insn (icode
, 2, ops
))
6594 /* lock_release is only a release barrier. */
6595 if (is_mm_seq_cst (model
))
6596 expand_mem_thread_fence (model
);
6602 /* If the size of the object is greater than word size on this target,
6603 a default store will not be atomic. */
6604 if (maybe_gt (GET_MODE_PRECISION (mode
), BITS_PER_WORD
))
6606 /* If loads are atomic or we are called to provide a __sync builtin,
6607 we can try a atomic_exchange and throw away the result. Otherwise,
6608 don't do anything so that we do not create an inconsistency between
6609 loads and stores. */
6610 if (can_atomic_load_p (mode
) || is_mm_sync (model
))
6612 rtx target
= maybe_emit_atomic_exchange (NULL_RTX
, mem
, val
, model
);
6614 target
= maybe_emit_compare_and_swap_exchange_loop (NULL_RTX
, mem
,
6622 /* Otherwise assume stores are atomic, and emit the proper barriers. */
6623 expand_mem_thread_fence (model
);
6625 emit_move_insn (mem
, val
);
6627 /* For SEQ_CST, also emit a barrier after the store. */
6628 if (is_mm_seq_cst (model
))
6629 expand_mem_thread_fence (model
);
6635 /* Structure containing the pointers and values required to process the
6636 various forms of the atomic_fetch_op and atomic_op_fetch builtins. */
6638 struct atomic_op_functions
6640 direct_optab mem_fetch_before
;
6641 direct_optab mem_fetch_after
;
6642 direct_optab mem_no_result
;
6645 direct_optab no_result
;
6646 enum rtx_code reverse_code
;
6650 /* Fill in structure pointed to by OP with the various optab entries for an
6651 operation of type CODE. */
6654 get_atomic_op_for_code (struct atomic_op_functions
*op
, enum rtx_code code
)
6656 gcc_assert (op
!= NULL
);
6658 /* If SWITCHABLE_TARGET is defined, then subtargets can be switched
6659 in the source code during compilation, and the optab entries are not
6660 computable until runtime. Fill in the values at runtime. */
6664 op
->mem_fetch_before
= atomic_fetch_add_optab
;
6665 op
->mem_fetch_after
= atomic_add_fetch_optab
;
6666 op
->mem_no_result
= atomic_add_optab
;
6667 op
->fetch_before
= sync_old_add_optab
;
6668 op
->fetch_after
= sync_new_add_optab
;
6669 op
->no_result
= sync_add_optab
;
6670 op
->reverse_code
= MINUS
;
6673 op
->mem_fetch_before
= atomic_fetch_sub_optab
;
6674 op
->mem_fetch_after
= atomic_sub_fetch_optab
;
6675 op
->mem_no_result
= atomic_sub_optab
;
6676 op
->fetch_before
= sync_old_sub_optab
;
6677 op
->fetch_after
= sync_new_sub_optab
;
6678 op
->no_result
= sync_sub_optab
;
6679 op
->reverse_code
= PLUS
;
6682 op
->mem_fetch_before
= atomic_fetch_xor_optab
;
6683 op
->mem_fetch_after
= atomic_xor_fetch_optab
;
6684 op
->mem_no_result
= atomic_xor_optab
;
6685 op
->fetch_before
= sync_old_xor_optab
;
6686 op
->fetch_after
= sync_new_xor_optab
;
6687 op
->no_result
= sync_xor_optab
;
6688 op
->reverse_code
= XOR
;
6691 op
->mem_fetch_before
= atomic_fetch_and_optab
;
6692 op
->mem_fetch_after
= atomic_and_fetch_optab
;
6693 op
->mem_no_result
= atomic_and_optab
;
6694 op
->fetch_before
= sync_old_and_optab
;
6695 op
->fetch_after
= sync_new_and_optab
;
6696 op
->no_result
= sync_and_optab
;
6697 op
->reverse_code
= UNKNOWN
;
6700 op
->mem_fetch_before
= atomic_fetch_or_optab
;
6701 op
->mem_fetch_after
= atomic_or_fetch_optab
;
6702 op
->mem_no_result
= atomic_or_optab
;
6703 op
->fetch_before
= sync_old_ior_optab
;
6704 op
->fetch_after
= sync_new_ior_optab
;
6705 op
->no_result
= sync_ior_optab
;
6706 op
->reverse_code
= UNKNOWN
;
6709 op
->mem_fetch_before
= atomic_fetch_nand_optab
;
6710 op
->mem_fetch_after
= atomic_nand_fetch_optab
;
6711 op
->mem_no_result
= atomic_nand_optab
;
6712 op
->fetch_before
= sync_old_nand_optab
;
6713 op
->fetch_after
= sync_new_nand_optab
;
6714 op
->no_result
= sync_nand_optab
;
6715 op
->reverse_code
= UNKNOWN
;
6722 /* See if there is a more optimal way to implement the operation "*MEM CODE VAL"
6723 using memory order MODEL. If AFTER is true the operation needs to return
6724 the value of *MEM after the operation, otherwise the previous value.
6725 TARGET is an optional place to place the result. The result is unused if
6727 Return the result if there is a better sequence, otherwise NULL_RTX. */
6730 maybe_optimize_fetch_op (rtx target
, rtx mem
, rtx val
, enum rtx_code code
,
6731 enum memmodel model
, bool after
)
6733 /* If the value is prefetched, or not used, it may be possible to replace
6734 the sequence with a native exchange operation. */
6735 if (!after
|| target
== const0_rtx
)
6737 /* fetch_and (&x, 0, m) can be replaced with exchange (&x, 0, m). */
6738 if (code
== AND
&& val
== const0_rtx
)
6740 if (target
== const0_rtx
)
6741 target
= gen_reg_rtx (GET_MODE (mem
));
6742 return maybe_emit_atomic_exchange (target
, mem
, val
, model
);
6745 /* fetch_or (&x, -1, m) can be replaced with exchange (&x, -1, m). */
6746 if (code
== IOR
&& val
== constm1_rtx
)
6748 if (target
== const0_rtx
)
6749 target
= gen_reg_rtx (GET_MODE (mem
));
6750 return maybe_emit_atomic_exchange (target
, mem
, val
, model
);
6757 /* Try to emit an instruction for a specific operation varaition.
6758 OPTAB contains the OP functions.
6759 TARGET is an optional place to return the result. const0_rtx means unused.
6760 MEM is the memory location to operate on.
6761 VAL is the value to use in the operation.
6762 USE_MEMMODEL is TRUE if the variation with a memory model should be tried.
6763 MODEL is the memory model, if used.
6764 AFTER is true if the returned result is the value after the operation. */
6767 maybe_emit_op (const struct atomic_op_functions
*optab
, rtx target
, rtx mem
,
6768 rtx val
, bool use_memmodel
, enum memmodel model
, bool after
)
6770 machine_mode mode
= GET_MODE (mem
);
6771 struct expand_operand ops
[4];
6772 enum insn_code icode
;
6776 /* Check to see if there is a result returned. */
6777 if (target
== const0_rtx
)
6781 icode
= direct_optab_handler (optab
->mem_no_result
, mode
);
6782 create_integer_operand (&ops
[2], model
);
6787 icode
= direct_optab_handler (optab
->no_result
, mode
);
6791 /* Otherwise, we need to generate a result. */
6796 icode
= direct_optab_handler (after
? optab
->mem_fetch_after
6797 : optab
->mem_fetch_before
, mode
);
6798 create_integer_operand (&ops
[3], model
);
6803 icode
= optab_handler (after
? optab
->fetch_after
6804 : optab
->fetch_before
, mode
);
6807 create_output_operand (&ops
[op_counter
++], target
, mode
);
6809 if (icode
== CODE_FOR_nothing
)
6812 create_fixed_operand (&ops
[op_counter
++], mem
);
6813 /* VAL may have been promoted to a wider mode. Shrink it if so. */
6814 create_convert_operand_to (&ops
[op_counter
++], val
, mode
, true);
6816 if (maybe_expand_insn (icode
, num_ops
, ops
))
6817 return (target
== const0_rtx
? const0_rtx
: ops
[0].value
);
6823 /* This function expands an atomic fetch_OP or OP_fetch operation:
6824 TARGET is an option place to stick the return value. const0_rtx indicates
6825 the result is unused.
6826 atomically fetch MEM, perform the operation with VAL and return it to MEM.
6827 CODE is the operation being performed (OP)
6828 MEMMODEL is the memory model variant to use.
6829 AFTER is true to return the result of the operation (OP_fetch).
6830 AFTER is false to return the value before the operation (fetch_OP).
6832 This function will *only* generate instructions if there is a direct
6833 optab. No compare and swap loops or libcalls will be generated. */
6836 expand_atomic_fetch_op_no_fallback (rtx target
, rtx mem
, rtx val
,
6837 enum rtx_code code
, enum memmodel model
,
6840 machine_mode mode
= GET_MODE (mem
);
6841 struct atomic_op_functions optab
;
6843 bool unused_result
= (target
== const0_rtx
);
6845 get_atomic_op_for_code (&optab
, code
);
6847 /* Check to see if there are any better instructions. */
6848 result
= maybe_optimize_fetch_op (target
, mem
, val
, code
, model
, after
);
6852 /* Check for the case where the result isn't used and try those patterns. */
6855 /* Try the memory model variant first. */
6856 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, true);
6860 /* Next try the old style withuot a memory model. */
6861 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, true);
6865 /* There is no no-result pattern, so try patterns with a result. */
6869 /* Try the __atomic version. */
6870 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, after
);
6874 /* Try the older __sync version. */
6875 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, after
);
6879 /* If the fetch value can be calculated from the other variation of fetch,
6880 try that operation. */
6881 if (after
|| unused_result
|| optab
.reverse_code
!= UNKNOWN
)
6883 /* Try the __atomic version, then the older __sync version. */
6884 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, !after
);
6886 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, !after
);
6890 /* If the result isn't used, no need to do compensation code. */
6894 /* Issue compensation code. Fetch_after == fetch_before OP val.
6895 Fetch_before == after REVERSE_OP val. */
6897 code
= optab
.reverse_code
;
6900 result
= expand_simple_binop (mode
, AND
, result
, val
, NULL_RTX
,
6901 true, OPTAB_LIB_WIDEN
);
6902 result
= expand_simple_unop (mode
, NOT
, result
, target
, true);
6905 result
= expand_simple_binop (mode
, code
, result
, val
, target
,
6906 true, OPTAB_LIB_WIDEN
);
6911 /* No direct opcode can be generated. */
6917 /* This function expands an atomic fetch_OP or OP_fetch operation:
6918 TARGET is an option place to stick the return value. const0_rtx indicates
6919 the result is unused.
6920 atomically fetch MEM, perform the operation with VAL and return it to MEM.
6921 CODE is the operation being performed (OP)
6922 MEMMODEL is the memory model variant to use.
6923 AFTER is true to return the result of the operation (OP_fetch).
6924 AFTER is false to return the value before the operation (fetch_OP). */
6926 expand_atomic_fetch_op (rtx target
, rtx mem
, rtx val
, enum rtx_code code
,
6927 enum memmodel model
, bool after
)
6929 machine_mode mode
= GET_MODE (mem
);
6931 bool unused_result
= (target
== const0_rtx
);
6933 /* If loads are not atomic for the required size and we are not called to
6934 provide a __sync builtin, do not do anything so that we stay consistent
6935 with atomic loads of the same size. */
6936 if (!can_atomic_load_p (mode
) && !is_mm_sync (model
))
6939 result
= expand_atomic_fetch_op_no_fallback (target
, mem
, val
, code
, model
,
6945 /* Add/sub can be implemented by doing the reverse operation with -(val). */
6946 if (code
== PLUS
|| code
== MINUS
)
6949 enum rtx_code reverse
= (code
== PLUS
? MINUS
: PLUS
);
6952 tmp
= expand_simple_unop (mode
, NEG
, val
, NULL_RTX
, true);
6953 result
= expand_atomic_fetch_op_no_fallback (target
, mem
, tmp
, reverse
,
6957 /* PLUS worked so emit the insns and return. */
6964 /* PLUS did not work, so throw away the negation code and continue. */
6968 /* Try the __sync libcalls only if we can't do compare-and-swap inline. */
6969 if (!can_compare_and_swap_p (mode
, false))
6973 enum rtx_code orig_code
= code
;
6974 struct atomic_op_functions optab
;
6976 get_atomic_op_for_code (&optab
, code
);
6977 libfunc
= optab_libfunc (after
? optab
.fetch_after
6978 : optab
.fetch_before
, mode
);
6980 && (after
|| unused_result
|| optab
.reverse_code
!= UNKNOWN
))
6984 code
= optab
.reverse_code
;
6985 libfunc
= optab_libfunc (after
? optab
.fetch_before
6986 : optab
.fetch_after
, mode
);
6988 if (libfunc
!= NULL
)
6990 rtx addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
6991 result
= emit_library_call_value (libfunc
, NULL
, LCT_NORMAL
, mode
,
6992 addr
, ptr_mode
, val
, mode
);
6994 if (!unused_result
&& fixup
)
6995 result
= expand_simple_binop (mode
, code
, result
, val
, target
,
6996 true, OPTAB_LIB_WIDEN
);
7000 /* We need the original code for any further attempts. */
7004 /* If nothing else has succeeded, default to a compare and swap loop. */
7005 if (can_compare_and_swap_p (mode
, true))
7008 rtx t0
= gen_reg_rtx (mode
), t1
;
7012 /* If the result is used, get a register for it. */
7015 if (!target
|| !register_operand (target
, mode
))
7016 target
= gen_reg_rtx (mode
);
7017 /* If fetch_before, copy the value now. */
7019 emit_move_insn (target
, t0
);
7022 target
= const0_rtx
;
7027 t1
= expand_simple_binop (mode
, AND
, t1
, val
, NULL_RTX
,
7028 true, OPTAB_LIB_WIDEN
);
7029 t1
= expand_simple_unop (mode
, code
, t1
, NULL_RTX
, true);
7032 t1
= expand_simple_binop (mode
, code
, t1
, val
, NULL_RTX
, true,
7035 /* For after, copy the value now. */
7036 if (!unused_result
&& after
)
7037 emit_move_insn (target
, t1
);
7038 insn
= get_insns ();
7041 if (t1
!= NULL
&& expand_compare_and_swap_loop (mem
, t0
, t1
, insn
))
7048 /* Return true if OPERAND is suitable for operand number OPNO of
7049 instruction ICODE. */
7052 insn_operand_matches (enum insn_code icode
, unsigned int opno
, rtx operand
)
7054 return (!insn_data
[(int) icode
].operand
[opno
].predicate
7055 || (insn_data
[(int) icode
].operand
[opno
].predicate
7056 (operand
, insn_data
[(int) icode
].operand
[opno
].mode
)));
7059 /* TARGET is a target of a multiword operation that we are going to
7060 implement as a series of word-mode operations. Return true if
7061 TARGET is suitable for this purpose. */
7064 valid_multiword_target_p (rtx target
)
7069 mode
= GET_MODE (target
);
7070 if (!GET_MODE_SIZE (mode
).is_constant (&size
))
7072 for (i
= 0; i
< size
; i
+= UNITS_PER_WORD
)
7073 if (!validate_subreg (word_mode
, mode
, target
, i
))
7078 /* Make OP describe an input operand that has value INTVAL and that has
7079 no inherent mode. This function should only be used for operands that
7080 are always expand-time constants. The backend may request that INTVAL
7081 be copied into a different kind of rtx, but it must specify the mode
7082 of that rtx if so. */
7085 create_integer_operand (struct expand_operand
*op
, poly_int64 intval
)
7087 create_expand_operand (op
, EXPAND_INTEGER
,
7088 gen_int_mode (intval
, MAX_MODE_INT
),
7089 VOIDmode
, false, intval
);
7092 /* Like maybe_legitimize_operand, but do not change the code of the
7093 current rtx value. */
7096 maybe_legitimize_operand_same_code (enum insn_code icode
, unsigned int opno
,
7097 struct expand_operand
*op
)
7099 /* See if the operand matches in its current form. */
7100 if (insn_operand_matches (icode
, opno
, op
->value
))
7103 /* If the operand is a memory whose address has no side effects,
7104 try forcing the address into a non-virtual pseudo register.
7105 The check for side effects is important because copy_to_mode_reg
7106 cannot handle things like auto-modified addresses. */
7107 if (insn_data
[(int) icode
].operand
[opno
].allows_mem
&& MEM_P (op
->value
))
7112 addr
= XEXP (mem
, 0);
7113 if (!(REG_P (addr
) && REGNO (addr
) > LAST_VIRTUAL_REGISTER
)
7114 && !side_effects_p (addr
))
7119 last
= get_last_insn ();
7120 mode
= get_address_mode (mem
);
7121 mem
= replace_equiv_address (mem
, copy_to_mode_reg (mode
, addr
));
7122 if (insn_operand_matches (icode
, opno
, mem
))
7127 delete_insns_since (last
);
7134 /* Try to make OP match operand OPNO of instruction ICODE. Return true
7135 on success, storing the new operand value back in OP. */
7138 maybe_legitimize_operand (enum insn_code icode
, unsigned int opno
,
7139 struct expand_operand
*op
)
7141 machine_mode mode
, imode
;
7142 bool old_volatile_ok
, result
;
7148 old_volatile_ok
= volatile_ok
;
7150 result
= maybe_legitimize_operand_same_code (icode
, opno
, op
);
7151 volatile_ok
= old_volatile_ok
;
7155 gcc_assert (mode
!= VOIDmode
);
7157 && op
->value
!= const0_rtx
7158 && GET_MODE (op
->value
) == mode
7159 && maybe_legitimize_operand_same_code (icode
, opno
, op
))
7162 op
->value
= gen_reg_rtx (mode
);
7168 gcc_assert (mode
!= VOIDmode
);
7169 gcc_assert (GET_MODE (op
->value
) == VOIDmode
7170 || GET_MODE (op
->value
) == mode
);
7171 if (maybe_legitimize_operand_same_code (icode
, opno
, op
))
7174 op
->value
= copy_to_mode_reg (mode
, op
->value
);
7177 case EXPAND_CONVERT_TO
:
7178 gcc_assert (mode
!= VOIDmode
);
7179 op
->value
= convert_to_mode (mode
, op
->value
, op
->unsigned_p
);
7182 case EXPAND_CONVERT_FROM
:
7183 if (GET_MODE (op
->value
) != VOIDmode
)
7184 mode
= GET_MODE (op
->value
);
7186 /* The caller must tell us what mode this value has. */
7187 gcc_assert (mode
!= VOIDmode
);
7189 imode
= insn_data
[(int) icode
].operand
[opno
].mode
;
7190 if (imode
!= VOIDmode
&& imode
!= mode
)
7192 op
->value
= convert_modes (imode
, mode
, op
->value
, op
->unsigned_p
);
7197 case EXPAND_ADDRESS
:
7198 op
->value
= convert_memory_address (as_a
<scalar_int_mode
> (mode
),
7202 case EXPAND_INTEGER
:
7203 mode
= insn_data
[(int) icode
].operand
[opno
].mode
;
7204 if (mode
!= VOIDmode
7205 && known_eq (trunc_int_for_mode (op
->int_value
, mode
),
7208 op
->value
= gen_int_mode (op
->int_value
, mode
);
7213 return insn_operand_matches (icode
, opno
, op
->value
);
7216 /* Make OP describe an input operand that should have the same value
7217 as VALUE, after any mode conversion that the target might request.
7218 TYPE is the type of VALUE. */
7221 create_convert_operand_from_type (struct expand_operand
*op
,
7222 rtx value
, tree type
)
7224 create_convert_operand_from (op
, value
, TYPE_MODE (type
),
7225 TYPE_UNSIGNED (type
));
7228 /* Return true if the requirements on operands OP1 and OP2 of instruction
7229 ICODE are similar enough for the result of legitimizing OP1 to be
7230 reusable for OP2. OPNO1 and OPNO2 are the operand numbers associated
7231 with OP1 and OP2 respectively. */
7234 can_reuse_operands_p (enum insn_code icode
,
7235 unsigned int opno1
, unsigned int opno2
,
7236 const struct expand_operand
*op1
,
7237 const struct expand_operand
*op2
)
7239 /* Check requirements that are common to all types. */
7240 if (op1
->type
!= op2
->type
7241 || op1
->mode
!= op2
->mode
7242 || (insn_data
[(int) icode
].operand
[opno1
].mode
7243 != insn_data
[(int) icode
].operand
[opno2
].mode
))
7246 /* Check the requirements for specific types. */
7250 /* Outputs must remain distinct. */
7255 case EXPAND_ADDRESS
:
7256 case EXPAND_INTEGER
:
7259 case EXPAND_CONVERT_TO
:
7260 case EXPAND_CONVERT_FROM
:
7261 return op1
->unsigned_p
== op2
->unsigned_p
;
7266 /* Try to make operands [OPS, OPS + NOPS) match operands [OPNO, OPNO + NOPS)
7267 of instruction ICODE. Return true on success, leaving the new operand
7268 values in the OPS themselves. Emit no code on failure. */
7271 maybe_legitimize_operands (enum insn_code icode
, unsigned int opno
,
7272 unsigned int nops
, struct expand_operand
*ops
)
7274 rtx_insn
*last
= get_last_insn ();
7275 rtx
*orig_values
= XALLOCAVEC (rtx
, nops
);
7276 for (unsigned int i
= 0; i
< nops
; i
++)
7278 orig_values
[i
] = ops
[i
].value
;
7280 /* First try reusing the result of an earlier legitimization.
7281 This avoids duplicate rtl and ensures that tied operands
7284 This search is linear, but NOPS is bounded at compile time
7285 to a small number (current a single digit). */
7288 if (can_reuse_operands_p (icode
, opno
+ j
, opno
+ i
, &ops
[j
], &ops
[i
])
7289 && rtx_equal_p (orig_values
[j
], orig_values
[i
])
7291 && insn_operand_matches (icode
, opno
+ i
, ops
[j
].value
))
7293 ops
[i
].value
= copy_rtx (ops
[j
].value
);
7297 /* Otherwise try legitimizing the operand on its own. */
7298 if (j
== i
&& !maybe_legitimize_operand (icode
, opno
+ i
, &ops
[i
]))
7300 delete_insns_since (last
);
7307 /* Try to generate instruction ICODE, using operands [OPS, OPS + NOPS)
7308 as its operands. Return the instruction pattern on success,
7309 and emit any necessary set-up code. Return null and emit no
7313 maybe_gen_insn (enum insn_code icode
, unsigned int nops
,
7314 struct expand_operand
*ops
)
7316 gcc_assert (nops
== (unsigned int) insn_data
[(int) icode
].n_generator_args
);
7317 if (!maybe_legitimize_operands (icode
, 0, nops
, ops
))
7323 return GEN_FCN (icode
) (ops
[0].value
);
7325 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
);
7327 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
);
7329 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
7332 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
7333 ops
[3].value
, ops
[4].value
);
7335 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
7336 ops
[3].value
, ops
[4].value
, ops
[5].value
);
7338 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
7339 ops
[3].value
, ops
[4].value
, ops
[5].value
,
7342 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
7343 ops
[3].value
, ops
[4].value
, ops
[5].value
,
7344 ops
[6].value
, ops
[7].value
);
7346 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
7347 ops
[3].value
, ops
[4].value
, ops
[5].value
,
7348 ops
[6].value
, ops
[7].value
, ops
[8].value
);
7353 /* Try to emit instruction ICODE, using operands [OPS, OPS + NOPS)
7354 as its operands. Return true on success and emit no code on failure. */
7357 maybe_expand_insn (enum insn_code icode
, unsigned int nops
,
7358 struct expand_operand
*ops
)
7360 rtx_insn
*pat
= maybe_gen_insn (icode
, nops
, ops
);
7369 /* Like maybe_expand_insn, but for jumps. */
7372 maybe_expand_jump_insn (enum insn_code icode
, unsigned int nops
,
7373 struct expand_operand
*ops
)
7375 rtx_insn
*pat
= maybe_gen_insn (icode
, nops
, ops
);
7378 emit_jump_insn (pat
);
7384 /* Emit instruction ICODE, using operands [OPS, OPS + NOPS)
7388 expand_insn (enum insn_code icode
, unsigned int nops
,
7389 struct expand_operand
*ops
)
7391 if (!maybe_expand_insn (icode
, nops
, ops
))
7395 /* Like expand_insn, but for jumps. */
7398 expand_jump_insn (enum insn_code icode
, unsigned int nops
,
7399 struct expand_operand
*ops
)
7401 if (!maybe_expand_jump_insn (icode
, nops
, ops
))