1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992-2013 Free Software Foundation, Inc.
3 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
40 #include "diagnostic-core.h"
46 #include "common/common-target.h"
47 #include "target-def.h"
48 #include "langhooks.h"
52 /* Return nonzero if there is a bypass for the output of
53 OUT_INSN and the fp store IN_INSN. */
55 pa_fpstore_bypass_p (rtx out_insn
, rtx in_insn
)
57 enum machine_mode store_mode
;
58 enum machine_mode other_mode
;
61 if (recog_memoized (in_insn
) < 0
62 || (get_attr_type (in_insn
) != TYPE_FPSTORE
63 && get_attr_type (in_insn
) != TYPE_FPSTORE_LOAD
)
64 || recog_memoized (out_insn
) < 0)
67 store_mode
= GET_MODE (SET_SRC (PATTERN (in_insn
)));
69 set
= single_set (out_insn
);
73 other_mode
= GET_MODE (SET_SRC (set
));
75 return (GET_MODE_SIZE (store_mode
) == GET_MODE_SIZE (other_mode
));
79 #ifndef DO_FRAME_NOTES
80 #ifdef INCOMING_RETURN_ADDR_RTX
81 #define DO_FRAME_NOTES 1
83 #define DO_FRAME_NOTES 0
87 static void pa_option_override (void);
88 static void copy_reg_pointer (rtx
, rtx
);
89 static void fix_range (const char *);
90 static int hppa_register_move_cost (enum machine_mode mode
, reg_class_t
,
92 static int hppa_address_cost (rtx
, enum machine_mode mode
, addr_space_t
, bool);
93 static bool hppa_rtx_costs (rtx
, int, int, int, int *, bool);
94 static inline rtx
force_mode (enum machine_mode
, rtx
);
95 static void pa_reorg (void);
96 static void pa_combine_instructions (void);
97 static int pa_can_combine_p (rtx
, rtx
, rtx
, int, rtx
, rtx
, rtx
);
98 static bool forward_branch_p (rtx
);
99 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT
, unsigned *);
100 static void compute_zdepdi_operands (unsigned HOST_WIDE_INT
, unsigned *);
101 static int compute_movmem_length (rtx
);
102 static int compute_clrmem_length (rtx
);
103 static bool pa_assemble_integer (rtx
, unsigned int, int);
104 static void remove_useless_addtr_insns (int);
105 static void store_reg (int, HOST_WIDE_INT
, int);
106 static void store_reg_modify (int, int, HOST_WIDE_INT
);
107 static void load_reg (int, HOST_WIDE_INT
, int);
108 static void set_reg_plus_d (int, int, HOST_WIDE_INT
, int);
109 static rtx
pa_function_value (const_tree
, const_tree
, bool);
110 static rtx
pa_libcall_value (enum machine_mode
, const_rtx
);
111 static bool pa_function_value_regno_p (const unsigned int);
112 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT
);
113 static void update_total_code_bytes (unsigned int);
114 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT
);
115 static int pa_adjust_cost (rtx
, rtx
, rtx
, int);
116 static int pa_adjust_priority (rtx
, int);
117 static int pa_issue_rate (void);
118 static void pa_som_asm_init_sections (void) ATTRIBUTE_UNUSED
;
119 static section
*pa_som_tm_clone_table_section (void) ATTRIBUTE_UNUSED
;
120 static section
*pa_select_section (tree
, int, unsigned HOST_WIDE_INT
)
122 static void pa_encode_section_info (tree
, rtx
, int);
123 static const char *pa_strip_name_encoding (const char *);
124 static bool pa_function_ok_for_sibcall (tree
, tree
);
125 static void pa_globalize_label (FILE *, const char *)
127 static void pa_asm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
128 HOST_WIDE_INT
, tree
);
129 #if !defined(USE_COLLECT2)
130 static void pa_asm_out_constructor (rtx
, int);
131 static void pa_asm_out_destructor (rtx
, int);
133 static void pa_init_builtins (void);
134 static rtx
pa_expand_builtin (tree
, rtx
, rtx
, enum machine_mode mode
, int);
135 static rtx
hppa_builtin_saveregs (void);
136 static void hppa_va_start (tree
, rtx
);
137 static tree
hppa_gimplify_va_arg_expr (tree
, tree
, gimple_seq
*, gimple_seq
*);
138 static bool pa_scalar_mode_supported_p (enum machine_mode
);
139 static bool pa_commutative_p (const_rtx x
, int outer_code
);
140 static void copy_fp_args (rtx
) ATTRIBUTE_UNUSED
;
141 static int length_fp_args (rtx
) ATTRIBUTE_UNUSED
;
142 static rtx
hppa_legitimize_address (rtx
, rtx
, enum machine_mode
);
143 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED
;
144 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED
;
145 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED
;
146 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED
;
147 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED
;
148 static void pa_som_file_start (void) ATTRIBUTE_UNUSED
;
149 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED
;
150 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED
;
151 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED
;
152 static void output_deferred_plabels (void);
153 static void output_deferred_profile_counters (void) ATTRIBUTE_UNUSED
;
154 #ifdef ASM_OUTPUT_EXTERNAL_REAL
155 static void pa_hpux_file_end (void);
157 static void pa_init_libfuncs (void);
158 static rtx
pa_struct_value_rtx (tree
, int);
159 static bool pa_pass_by_reference (cumulative_args_t
, enum machine_mode
,
161 static int pa_arg_partial_bytes (cumulative_args_t
, enum machine_mode
,
163 static void pa_function_arg_advance (cumulative_args_t
, enum machine_mode
,
165 static rtx
pa_function_arg (cumulative_args_t
, enum machine_mode
,
167 static unsigned int pa_function_arg_boundary (enum machine_mode
, const_tree
);
168 static struct machine_function
* pa_init_machine_status (void);
169 static reg_class_t
pa_secondary_reload (bool, rtx
, reg_class_t
,
171 secondary_reload_info
*);
172 static void pa_extra_live_on_entry (bitmap
);
173 static enum machine_mode
pa_promote_function_mode (const_tree
,
174 enum machine_mode
, int *,
177 static void pa_asm_trampoline_template (FILE *);
178 static void pa_trampoline_init (rtx
, tree
, rtx
);
179 static rtx
pa_trampoline_adjust_address (rtx
);
180 static rtx
pa_delegitimize_address (rtx
);
181 static bool pa_print_operand_punct_valid_p (unsigned char);
182 static rtx
pa_internal_arg_pointer (void);
183 static bool pa_can_eliminate (const int, const int);
184 static void pa_conditional_register_usage (void);
185 static enum machine_mode
pa_c_mode_for_suffix (char);
186 static section
*pa_function_section (tree
, enum node_frequency
, bool, bool);
187 static bool pa_cannot_force_const_mem (enum machine_mode
, rtx
);
188 static bool pa_legitimate_constant_p (enum machine_mode
, rtx
);
189 static unsigned int pa_section_type_flags (tree
, const char *, int);
190 static bool pa_legitimate_address_p (enum machine_mode
, rtx
, bool);
192 /* The following extra sections are only used for SOM. */
193 static GTY(()) section
*som_readonly_data_section
;
194 static GTY(()) section
*som_one_only_readonly_data_section
;
195 static GTY(()) section
*som_one_only_data_section
;
196 static GTY(()) section
*som_tm_clone_table_section
;
198 /* Counts for the number of callee-saved general and floating point
199 registers which were saved by the current function's prologue. */
200 static int gr_saved
, fr_saved
;
202 /* Boolean indicating whether the return pointer was saved by the
203 current function's prologue. */
204 static bool rp_saved
;
206 static rtx
find_addr_reg (rtx
);
208 /* Keep track of the number of bytes we have output in the CODE subspace
209 during this compilation so we'll know when to emit inline long-calls. */
210 unsigned long total_code_bytes
;
212 /* The last address of the previous function plus the number of bytes in
213 associated thunks that have been output. This is used to determine if
214 a thunk can use an IA-relative branch to reach its target function. */
215 static unsigned int last_address
;
217 /* Variables to handle plabels that we discover are necessary at assembly
218 output time. They are output after the current function. */
219 struct GTY(()) deferred_plabel
224 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel
*
226 static size_t n_deferred_plabels
= 0;
228 /* Initialize the GCC target structure. */
230 #undef TARGET_OPTION_OVERRIDE
231 #define TARGET_OPTION_OVERRIDE pa_option_override
233 #undef TARGET_ASM_ALIGNED_HI_OP
234 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
235 #undef TARGET_ASM_ALIGNED_SI_OP
236 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
237 #undef TARGET_ASM_ALIGNED_DI_OP
238 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
239 #undef TARGET_ASM_UNALIGNED_HI_OP
240 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
241 #undef TARGET_ASM_UNALIGNED_SI_OP
242 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
243 #undef TARGET_ASM_UNALIGNED_DI_OP
244 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
245 #undef TARGET_ASM_INTEGER
246 #define TARGET_ASM_INTEGER pa_assemble_integer
248 #undef TARGET_ASM_FUNCTION_PROLOGUE
249 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
250 #undef TARGET_ASM_FUNCTION_EPILOGUE
251 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
253 #undef TARGET_FUNCTION_VALUE
254 #define TARGET_FUNCTION_VALUE pa_function_value
255 #undef TARGET_LIBCALL_VALUE
256 #define TARGET_LIBCALL_VALUE pa_libcall_value
257 #undef TARGET_FUNCTION_VALUE_REGNO_P
258 #define TARGET_FUNCTION_VALUE_REGNO_P pa_function_value_regno_p
260 #undef TARGET_LEGITIMIZE_ADDRESS
261 #define TARGET_LEGITIMIZE_ADDRESS hppa_legitimize_address
263 #undef TARGET_SCHED_ADJUST_COST
264 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
265 #undef TARGET_SCHED_ADJUST_PRIORITY
266 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
267 #undef TARGET_SCHED_ISSUE_RATE
268 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
270 #undef TARGET_ENCODE_SECTION_INFO
271 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
272 #undef TARGET_STRIP_NAME_ENCODING
273 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
275 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
276 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
278 #undef TARGET_COMMUTATIVE_P
279 #define TARGET_COMMUTATIVE_P pa_commutative_p
281 #undef TARGET_ASM_OUTPUT_MI_THUNK
282 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
283 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
284 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
286 #undef TARGET_ASM_FILE_END
287 #ifdef ASM_OUTPUT_EXTERNAL_REAL
288 #define TARGET_ASM_FILE_END pa_hpux_file_end
290 #define TARGET_ASM_FILE_END output_deferred_plabels
293 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
294 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P pa_print_operand_punct_valid_p
296 #if !defined(USE_COLLECT2)
297 #undef TARGET_ASM_CONSTRUCTOR
298 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
299 #undef TARGET_ASM_DESTRUCTOR
300 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
303 #undef TARGET_INIT_BUILTINS
304 #define TARGET_INIT_BUILTINS pa_init_builtins
306 #undef TARGET_EXPAND_BUILTIN
307 #define TARGET_EXPAND_BUILTIN pa_expand_builtin
309 #undef TARGET_REGISTER_MOVE_COST
310 #define TARGET_REGISTER_MOVE_COST hppa_register_move_cost
311 #undef TARGET_RTX_COSTS
312 #define TARGET_RTX_COSTS hppa_rtx_costs
313 #undef TARGET_ADDRESS_COST
314 #define TARGET_ADDRESS_COST hppa_address_cost
316 #undef TARGET_MACHINE_DEPENDENT_REORG
317 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
319 #undef TARGET_INIT_LIBFUNCS
320 #define TARGET_INIT_LIBFUNCS pa_init_libfuncs
322 #undef TARGET_PROMOTE_FUNCTION_MODE
323 #define TARGET_PROMOTE_FUNCTION_MODE pa_promote_function_mode
324 #undef TARGET_PROMOTE_PROTOTYPES
325 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
327 #undef TARGET_STRUCT_VALUE_RTX
328 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
329 #undef TARGET_RETURN_IN_MEMORY
330 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
331 #undef TARGET_MUST_PASS_IN_STACK
332 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
333 #undef TARGET_PASS_BY_REFERENCE
334 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
335 #undef TARGET_CALLEE_COPIES
336 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
337 #undef TARGET_ARG_PARTIAL_BYTES
338 #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes
339 #undef TARGET_FUNCTION_ARG
340 #define TARGET_FUNCTION_ARG pa_function_arg
341 #undef TARGET_FUNCTION_ARG_ADVANCE
342 #define TARGET_FUNCTION_ARG_ADVANCE pa_function_arg_advance
343 #undef TARGET_FUNCTION_ARG_BOUNDARY
344 #define TARGET_FUNCTION_ARG_BOUNDARY pa_function_arg_boundary
346 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
347 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
348 #undef TARGET_EXPAND_BUILTIN_VA_START
349 #define TARGET_EXPAND_BUILTIN_VA_START hppa_va_start
350 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
351 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
353 #undef TARGET_SCALAR_MODE_SUPPORTED_P
354 #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p
356 #undef TARGET_CANNOT_FORCE_CONST_MEM
357 #define TARGET_CANNOT_FORCE_CONST_MEM pa_cannot_force_const_mem
359 #undef TARGET_SECONDARY_RELOAD
360 #define TARGET_SECONDARY_RELOAD pa_secondary_reload
362 #undef TARGET_EXTRA_LIVE_ON_ENTRY
363 #define TARGET_EXTRA_LIVE_ON_ENTRY pa_extra_live_on_entry
365 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
366 #define TARGET_ASM_TRAMPOLINE_TEMPLATE pa_asm_trampoline_template
367 #undef TARGET_TRAMPOLINE_INIT
368 #define TARGET_TRAMPOLINE_INIT pa_trampoline_init
369 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
370 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS pa_trampoline_adjust_address
371 #undef TARGET_DELEGITIMIZE_ADDRESS
372 #define TARGET_DELEGITIMIZE_ADDRESS pa_delegitimize_address
373 #undef TARGET_INTERNAL_ARG_POINTER
374 #define TARGET_INTERNAL_ARG_POINTER pa_internal_arg_pointer
375 #undef TARGET_CAN_ELIMINATE
376 #define TARGET_CAN_ELIMINATE pa_can_eliminate
377 #undef TARGET_CONDITIONAL_REGISTER_USAGE
378 #define TARGET_CONDITIONAL_REGISTER_USAGE pa_conditional_register_usage
379 #undef TARGET_C_MODE_FOR_SUFFIX
380 #define TARGET_C_MODE_FOR_SUFFIX pa_c_mode_for_suffix
381 #undef TARGET_ASM_FUNCTION_SECTION
382 #define TARGET_ASM_FUNCTION_SECTION pa_function_section
384 #undef TARGET_LEGITIMATE_CONSTANT_P
385 #define TARGET_LEGITIMATE_CONSTANT_P pa_legitimate_constant_p
386 #undef TARGET_SECTION_TYPE_FLAGS
387 #define TARGET_SECTION_TYPE_FLAGS pa_section_type_flags
388 #undef TARGET_LEGITIMATE_ADDRESS_P
389 #define TARGET_LEGITIMATE_ADDRESS_P pa_legitimate_address_p
391 struct gcc_target targetm
= TARGET_INITIALIZER
;
393 /* Parse the -mfixed-range= option string. */
396 fix_range (const char *const_str
)
399 char *str
, *dash
, *comma
;
401 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
402 REG2 are either register names or register numbers. The effect
403 of this option is to mark the registers in the range from REG1 to
404 REG2 as ``fixed'' so they won't be used by the compiler. This is
405 used, e.g., to ensure that kernel mode code doesn't use fr4-fr31. */
407 i
= strlen (const_str
);
408 str
= (char *) alloca (i
+ 1);
409 memcpy (str
, const_str
, i
+ 1);
413 dash
= strchr (str
, '-');
416 warning (0, "value of -mfixed-range must have form REG1-REG2");
421 comma
= strchr (dash
+ 1, ',');
425 first
= decode_reg_name (str
);
428 warning (0, "unknown register name: %s", str
);
432 last
= decode_reg_name (dash
+ 1);
435 warning (0, "unknown register name: %s", dash
+ 1);
443 warning (0, "%s-%s is an empty range", str
, dash
+ 1);
447 for (i
= first
; i
<= last
; ++i
)
448 fixed_regs
[i
] = call_used_regs
[i
] = 1;
457 /* Check if all floating point registers have been fixed. */
458 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
463 target_flags
|= MASK_DISABLE_FPREGS
;
466 /* Implement the TARGET_OPTION_OVERRIDE hook. */
469 pa_option_override (void)
472 cl_deferred_option
*opt
;
473 vec
<cl_deferred_option
> *v
474 = (vec
<cl_deferred_option
> *) pa_deferred_options
;
477 FOR_EACH_VEC_ELT (*v
, i
, opt
)
479 switch (opt
->opt_index
)
481 case OPT_mfixed_range_
:
482 fix_range (opt
->arg
);
490 /* Unconditional branches in the delay slot are not compatible with dwarf2
491 call frame information. There is no benefit in using this optimization
492 on PA8000 and later processors. */
493 if (pa_cpu
>= PROCESSOR_8000
494 || (targetm_common
.except_unwind_info (&global_options
) == UI_DWARF2
496 || flag_unwind_tables
)
497 target_flags
&= ~MASK_JUMP_IN_DELAY
;
499 if (flag_pic
&& TARGET_PORTABLE_RUNTIME
)
501 warning (0, "PIC code generation is not supported in the portable runtime model");
504 if (flag_pic
&& TARGET_FAST_INDIRECT_CALLS
)
506 warning (0, "PIC code generation is not compatible with fast indirect calls");
509 if (! TARGET_GAS
&& write_symbols
!= NO_DEBUG
)
511 warning (0, "-g is only supported when using GAS on this processor,");
512 warning (0, "-g option disabled");
513 write_symbols
= NO_DEBUG
;
517 /* FIXME: Disable auto increment and decrement processing until reload
518 is completed. See PR middle-end 56791. */
519 flag_auto_inc_dec
= reload_completed
;
522 /* We only support the "big PIC" model now. And we always generate PIC
523 code when in 64bit mode. */
524 if (flag_pic
== 1 || TARGET_64BIT
)
527 /* Disable -freorder-blocks-and-partition as we don't support hot and
528 cold partitioning. */
529 if (flag_reorder_blocks_and_partition
)
531 inform (input_location
,
532 "-freorder-blocks-and-partition does not work "
533 "on this architecture");
534 flag_reorder_blocks_and_partition
= 0;
535 flag_reorder_blocks
= 1;
538 /* We can't guarantee that .dword is available for 32-bit targets. */
539 if (UNITS_PER_WORD
== 4)
540 targetm
.asm_out
.aligned_op
.di
= NULL
;
542 /* The unaligned ops are only available when using GAS. */
545 targetm
.asm_out
.unaligned_op
.hi
= NULL
;
546 targetm
.asm_out
.unaligned_op
.si
= NULL
;
547 targetm
.asm_out
.unaligned_op
.di
= NULL
;
550 init_machine_status
= pa_init_machine_status
;
555 PA_BUILTIN_COPYSIGNQ
,
558 PA_BUILTIN_HUGE_VALQ
,
562 static GTY(()) tree pa_builtins
[(int) PA_BUILTIN_max
];
565 pa_init_builtins (void)
567 #ifdef DONT_HAVE_FPUTC_UNLOCKED
569 tree decl
= builtin_decl_explicit (BUILT_IN_PUTC_UNLOCKED
);
570 set_builtin_decl (BUILT_IN_FPUTC_UNLOCKED
, decl
,
571 builtin_decl_implicit_p (BUILT_IN_PUTC_UNLOCKED
));
578 if ((decl
= builtin_decl_explicit (BUILT_IN_FINITE
)) != NULL_TREE
)
579 set_user_assembler_name (decl
, "_Isfinite");
580 if ((decl
= builtin_decl_explicit (BUILT_IN_FINITEF
)) != NULL_TREE
)
581 set_user_assembler_name (decl
, "_Isfinitef");
585 if (HPUX_LONG_DOUBLE_LIBRARY
)
589 /* Under HPUX, the __float128 type is a synonym for "long double". */
590 (*lang_hooks
.types
.register_builtin_type
) (long_double_type_node
,
593 /* TFmode support builtins. */
594 ftype
= build_function_type_list (long_double_type_node
,
595 long_double_type_node
,
597 decl
= add_builtin_function ("__builtin_fabsq", ftype
,
598 PA_BUILTIN_FABSQ
, BUILT_IN_MD
,
599 "_U_Qfabs", NULL_TREE
);
600 TREE_READONLY (decl
) = 1;
601 pa_builtins
[PA_BUILTIN_FABSQ
] = decl
;
603 ftype
= build_function_type_list (long_double_type_node
,
604 long_double_type_node
,
605 long_double_type_node
,
607 decl
= add_builtin_function ("__builtin_copysignq", ftype
,
608 PA_BUILTIN_COPYSIGNQ
, BUILT_IN_MD
,
609 "_U_Qfcopysign", NULL_TREE
);
610 TREE_READONLY (decl
) = 1;
611 pa_builtins
[PA_BUILTIN_COPYSIGNQ
] = decl
;
613 ftype
= build_function_type_list (long_double_type_node
, NULL_TREE
);
614 decl
= add_builtin_function ("__builtin_infq", ftype
,
615 PA_BUILTIN_INFQ
, BUILT_IN_MD
,
617 pa_builtins
[PA_BUILTIN_INFQ
] = decl
;
619 decl
= add_builtin_function ("__builtin_huge_valq", ftype
,
620 PA_BUILTIN_HUGE_VALQ
, BUILT_IN_MD
,
622 pa_builtins
[PA_BUILTIN_HUGE_VALQ
] = decl
;
627 pa_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
628 enum machine_mode mode ATTRIBUTE_UNUSED
,
629 int ignore ATTRIBUTE_UNUSED
)
631 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
632 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
636 case PA_BUILTIN_FABSQ
:
637 case PA_BUILTIN_COPYSIGNQ
:
638 return expand_call (exp
, target
, ignore
);
640 case PA_BUILTIN_INFQ
:
641 case PA_BUILTIN_HUGE_VALQ
:
643 enum machine_mode target_mode
= TYPE_MODE (TREE_TYPE (exp
));
648 tmp
= CONST_DOUBLE_FROM_REAL_VALUE (inf
, target_mode
);
650 tmp
= validize_mem (force_const_mem (target_mode
, tmp
));
653 target
= gen_reg_rtx (target_mode
);
655 emit_move_insn (target
, tmp
);
666 /* Function to init struct machine_function.
667 This will be called, via a pointer variable,
668 from push_function_context. */
670 static struct machine_function
*
671 pa_init_machine_status (void)
673 return ggc_alloc_cleared_machine_function ();
676 /* If FROM is a probable pointer register, mark TO as a probable
677 pointer register with the same pointer alignment as FROM. */
680 copy_reg_pointer (rtx to
, rtx from
)
682 if (REG_POINTER (from
))
683 mark_reg_pointer (to
, REGNO_POINTER_ALIGN (REGNO (from
)));
686 /* Return 1 if X contains a symbolic expression. We know these
687 expressions will have one of a few well defined forms, so
688 we need only check those forms. */
690 pa_symbolic_expression_p (rtx x
)
693 /* Strip off any HIGH. */
694 if (GET_CODE (x
) == HIGH
)
697 return symbolic_operand (x
, VOIDmode
);
700 /* Accept any constant that can be moved in one instruction into a
703 pa_cint_ok_for_move (HOST_WIDE_INT ival
)
705 /* OK if ldo, ldil, or zdepi, can be used. */
706 return (VAL_14_BITS_P (ival
)
707 || pa_ldil_cint_p (ival
)
708 || pa_zdepi_cint_p (ival
));
711 /* True iff ldil can be used to load this CONST_INT. The least
712 significant 11 bits of the value must be zero and the value must
713 not change sign when extended from 32 to 64 bits. */
715 pa_ldil_cint_p (HOST_WIDE_INT ival
)
717 HOST_WIDE_INT x
= ival
& (((HOST_WIDE_INT
) -1 << 31) | 0x7ff);
719 return x
== 0 || x
== ((HOST_WIDE_INT
) -1 << 31);
722 /* True iff zdepi can be used to generate this CONST_INT.
723 zdepi first sign extends a 5-bit signed number to a given field
724 length, then places this field anywhere in a zero. */
726 pa_zdepi_cint_p (unsigned HOST_WIDE_INT x
)
728 unsigned HOST_WIDE_INT lsb_mask
, t
;
730 /* This might not be obvious, but it's at least fast.
731 This function is critical; we don't have the time loops would take. */
733 t
= ((x
>> 4) + lsb_mask
) & ~(lsb_mask
- 1);
734 /* Return true iff t is a power of two. */
735 return ((t
& (t
- 1)) == 0);
738 /* True iff depi or extru can be used to compute (reg & mask).
739 Accept bit pattern like these:
744 pa_and_mask_p (unsigned HOST_WIDE_INT mask
)
747 mask
+= mask
& -mask
;
748 return (mask
& (mask
- 1)) == 0;
751 /* True iff depi can be used to compute (reg | MASK). */
753 pa_ior_mask_p (unsigned HOST_WIDE_INT mask
)
755 mask
+= mask
& -mask
;
756 return (mask
& (mask
- 1)) == 0;
759 /* Legitimize PIC addresses. If the address is already
760 position-independent, we return ORIG. Newly generated
761 position-independent addresses go to REG. If we need more
762 than one register, we lose. */
765 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
769 gcc_assert (!PA_SYMBOL_REF_TLS_P (orig
));
771 /* Labels need special handling. */
772 if (pic_label_operand (orig
, mode
))
776 /* We do not want to go through the movXX expanders here since that
777 would create recursion.
779 Nor do we really want to call a generator for a named pattern
780 since that requires multiple patterns if we want to support
783 So instead we just emit the raw set, which avoids the movXX
784 expanders completely. */
785 mark_reg_pointer (reg
, BITS_PER_UNIT
);
786 insn
= emit_insn (gen_rtx_SET (VOIDmode
, reg
, orig
));
788 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
789 add_reg_note (insn
, REG_EQUAL
, orig
);
791 /* During and after reload, we need to generate a REG_LABEL_OPERAND note
792 and update LABEL_NUSES because this is not done automatically. */
793 if (reload_in_progress
|| reload_completed
)
795 /* Extract LABEL_REF. */
796 if (GET_CODE (orig
) == CONST
)
797 orig
= XEXP (XEXP (orig
, 0), 0);
798 /* Extract CODE_LABEL. */
799 orig
= XEXP (orig
, 0);
800 add_reg_note (insn
, REG_LABEL_OPERAND
, orig
);
801 /* Make sure we have label and not a note. */
803 LABEL_NUSES (orig
)++;
805 crtl
->uses_pic_offset_table
= 1;
808 if (GET_CODE (orig
) == SYMBOL_REF
)
814 /* Before reload, allocate a temporary register for the intermediate
815 result. This allows the sequence to be deleted when the final
816 result is unused and the insns are trivially dead. */
817 tmp_reg
= ((reload_in_progress
|| reload_completed
)
818 ? reg
: gen_reg_rtx (Pmode
));
820 if (function_label_operand (orig
, VOIDmode
))
822 /* Force function label into memory in word mode. */
823 orig
= XEXP (force_const_mem (word_mode
, orig
), 0);
824 /* Load plabel address from DLT. */
825 emit_move_insn (tmp_reg
,
826 gen_rtx_PLUS (word_mode
, pic_offset_table_rtx
,
827 gen_rtx_HIGH (word_mode
, orig
)));
829 = gen_const_mem (Pmode
,
830 gen_rtx_LO_SUM (Pmode
, tmp_reg
,
831 gen_rtx_UNSPEC (Pmode
,
834 emit_move_insn (reg
, pic_ref
);
835 /* Now load address of function descriptor. */
836 pic_ref
= gen_rtx_MEM (Pmode
, reg
);
840 /* Load symbol reference from DLT. */
841 emit_move_insn (tmp_reg
,
842 gen_rtx_PLUS (word_mode
, pic_offset_table_rtx
,
843 gen_rtx_HIGH (word_mode
, orig
)));
845 = gen_const_mem (Pmode
,
846 gen_rtx_LO_SUM (Pmode
, tmp_reg
,
847 gen_rtx_UNSPEC (Pmode
,
852 crtl
->uses_pic_offset_table
= 1;
853 mark_reg_pointer (reg
, BITS_PER_UNIT
);
854 insn
= emit_move_insn (reg
, pic_ref
);
856 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
857 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
861 else if (GET_CODE (orig
) == CONST
)
865 if (GET_CODE (XEXP (orig
, 0)) == PLUS
866 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
870 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
872 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
873 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
874 base
== reg
? 0 : reg
);
876 if (GET_CODE (orig
) == CONST_INT
)
878 if (INT_14_BITS (orig
))
879 return plus_constant (Pmode
, base
, INTVAL (orig
));
880 orig
= force_reg (Pmode
, orig
);
882 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
883 /* Likewise, should we set special REG_NOTEs here? */
889 static GTY(()) rtx gen_tls_tga
;
892 gen_tls_get_addr (void)
895 gen_tls_tga
= init_one_libfunc ("__tls_get_addr");
900 hppa_tls_call (rtx arg
)
904 ret
= gen_reg_rtx (Pmode
);
905 emit_library_call_value (gen_tls_get_addr (), ret
,
906 LCT_CONST
, Pmode
, 1, arg
, Pmode
);
912 legitimize_tls_address (rtx addr
)
914 rtx ret
, insn
, tmp
, t1
, t2
, tp
;
916 /* Currently, we can't handle anything but a SYMBOL_REF. */
917 if (GET_CODE (addr
) != SYMBOL_REF
)
920 switch (SYMBOL_REF_TLS_MODEL (addr
))
922 case TLS_MODEL_GLOBAL_DYNAMIC
:
923 tmp
= gen_reg_rtx (Pmode
);
925 emit_insn (gen_tgd_load_pic (tmp
, addr
));
927 emit_insn (gen_tgd_load (tmp
, addr
));
928 ret
= hppa_tls_call (tmp
);
931 case TLS_MODEL_LOCAL_DYNAMIC
:
932 ret
= gen_reg_rtx (Pmode
);
933 tmp
= gen_reg_rtx (Pmode
);
936 emit_insn (gen_tld_load_pic (tmp
, addr
));
938 emit_insn (gen_tld_load (tmp
, addr
));
939 t1
= hppa_tls_call (tmp
);
942 t2
= gen_reg_rtx (Pmode
);
943 emit_libcall_block (insn
, t2
, t1
,
944 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
946 emit_insn (gen_tld_offset_load (ret
, addr
, t2
));
949 case TLS_MODEL_INITIAL_EXEC
:
950 tp
= gen_reg_rtx (Pmode
);
951 tmp
= gen_reg_rtx (Pmode
);
952 ret
= gen_reg_rtx (Pmode
);
953 emit_insn (gen_tp_load (tp
));
955 emit_insn (gen_tie_load_pic (tmp
, addr
));
957 emit_insn (gen_tie_load (tmp
, addr
));
958 emit_move_insn (ret
, gen_rtx_PLUS (Pmode
, tp
, tmp
));
961 case TLS_MODEL_LOCAL_EXEC
:
962 tp
= gen_reg_rtx (Pmode
);
963 ret
= gen_reg_rtx (Pmode
);
964 emit_insn (gen_tp_load (tp
));
965 emit_insn (gen_tle_load (ret
, addr
, tp
));
975 /* Try machine-dependent ways of modifying an illegitimate address
976 to be legitimate. If we find one, return the new, valid address.
977 This macro is used in only one place: `memory_address' in explow.c.
979 OLDX is the address as it was before break_out_memory_refs was called.
980 In some cases it is useful to look at this to decide what needs to be done.
982 It is always safe for this macro to do nothing. It exists to recognize
983 opportunities to optimize the output.
985 For the PA, transform:
987 memory(X + <large int>)
991 if (<large int> & mask) >= 16
992 Y = (<large int> & ~mask) + mask + 1 Round up.
994 Y = (<large int> & ~mask) Round down.
996 memory (Z + (<large int> - Y));
998 This is for CSE to find several similar references, and only use one Z.
1000 X can either be a SYMBOL_REF or REG, but because combine cannot
1001 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
1002 D will not fit in 14 bits.
1004 MODE_FLOAT references allow displacements which fit in 5 bits, so use
1007 MODE_INT references allow displacements which fit in 14 bits, so use
1010 This relies on the fact that most mode MODE_FLOAT references will use FP
1011 registers and most mode MODE_INT references will use integer registers.
1012 (In the rare case of an FP register used in an integer MODE, we depend
1013 on secondary reloads to clean things up.)
1016 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
1017 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
1018 addressing modes to be used).
1020 Put X and Z into registers. Then put the entire expression into
1024 hppa_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1025 enum machine_mode mode
)
1029 /* We need to canonicalize the order of operands in unscaled indexed
1030 addresses since the code that checks if an address is valid doesn't
1031 always try both orders. */
1032 if (!TARGET_NO_SPACE_REGS
1033 && GET_CODE (x
) == PLUS
1034 && GET_MODE (x
) == Pmode
1035 && REG_P (XEXP (x
, 0))
1036 && REG_P (XEXP (x
, 1))
1037 && REG_POINTER (XEXP (x
, 0))
1038 && !REG_POINTER (XEXP (x
, 1)))
1039 return gen_rtx_PLUS (Pmode
, XEXP (x
, 1), XEXP (x
, 0));
1041 if (pa_tls_referenced_p (x
))
1042 return legitimize_tls_address (x
);
1044 return legitimize_pic_address (x
, mode
, gen_reg_rtx (Pmode
));
1046 /* Strip off CONST. */
1047 if (GET_CODE (x
) == CONST
)
1050 /* Special case. Get the SYMBOL_REF into a register and use indexing.
1051 That should always be safe. */
1052 if (GET_CODE (x
) == PLUS
1053 && GET_CODE (XEXP (x
, 0)) == REG
1054 && GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
)
1056 rtx reg
= force_reg (Pmode
, XEXP (x
, 1));
1057 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
, reg
, XEXP (x
, 0)));
1060 /* Note we must reject symbols which represent function addresses
1061 since the assembler/linker can't handle arithmetic on plabels. */
1062 if (GET_CODE (x
) == PLUS
1063 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1064 && ((GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
1065 && !FUNCTION_NAME_P (XSTR (XEXP (x
, 0), 0)))
1066 || GET_CODE (XEXP (x
, 0)) == REG
))
1068 rtx int_part
, ptr_reg
;
1070 int offset
= INTVAL (XEXP (x
, 1));
1073 mask
= (GET_MODE_CLASS (mode
) == MODE_FLOAT
1074 && !INT14_OK_STRICT
? 0x1f : 0x3fff);
1076 /* Choose which way to round the offset. Round up if we
1077 are >= halfway to the next boundary. */
1078 if ((offset
& mask
) >= ((mask
+ 1) / 2))
1079 newoffset
= (offset
& ~ mask
) + mask
+ 1;
1081 newoffset
= (offset
& ~ mask
);
1083 /* If the newoffset will not fit in 14 bits (ldo), then
1084 handling this would take 4 or 5 instructions (2 to load
1085 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1086 add the new offset and the SYMBOL_REF.) Combine can
1087 not handle 4->2 or 5->2 combinations, so do not create
1089 if (! VAL_14_BITS_P (newoffset
)
1090 && GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
1092 rtx const_part
= plus_constant (Pmode
, XEXP (x
, 0), newoffset
);
1095 gen_rtx_HIGH (Pmode
, const_part
));
1098 gen_rtx_LO_SUM (Pmode
,
1099 tmp_reg
, const_part
));
1103 if (! VAL_14_BITS_P (newoffset
))
1104 int_part
= force_reg (Pmode
, GEN_INT (newoffset
));
1106 int_part
= GEN_INT (newoffset
);
1108 ptr_reg
= force_reg (Pmode
,
1109 gen_rtx_PLUS (Pmode
,
1110 force_reg (Pmode
, XEXP (x
, 0)),
1113 return plus_constant (Pmode
, ptr_reg
, offset
- newoffset
);
1116 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1118 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
1119 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1120 && pa_shadd_constant_p (INTVAL (XEXP (XEXP (x
, 0), 1)))
1121 && (OBJECT_P (XEXP (x
, 1))
1122 || GET_CODE (XEXP (x
, 1)) == SUBREG
)
1123 && GET_CODE (XEXP (x
, 1)) != CONST
)
1125 int val
= INTVAL (XEXP (XEXP (x
, 0), 1));
1129 if (GET_CODE (reg1
) != REG
)
1130 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
1132 reg2
= XEXP (XEXP (x
, 0), 0);
1133 if (GET_CODE (reg2
) != REG
)
1134 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
1136 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
,
1137 gen_rtx_MULT (Pmode
,
1143 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1145 Only do so for floating point modes since this is more speculative
1146 and we lose if it's an integer store. */
1147 if (GET_CODE (x
) == PLUS
1148 && GET_CODE (XEXP (x
, 0)) == PLUS
1149 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
1150 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
1151 && pa_shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
1152 && (mode
== SFmode
|| mode
== DFmode
))
1155 /* First, try and figure out what to use as a base register. */
1156 rtx reg1
, reg2
, base
, idx
;
1158 reg1
= XEXP (XEXP (x
, 0), 1);
1163 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1164 then pa_emit_move_sequence will turn on REG_POINTER so we'll know
1165 it's a base register below. */
1166 if (GET_CODE (reg1
) != REG
)
1167 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
1169 if (GET_CODE (reg2
) != REG
)
1170 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
1172 /* Figure out what the base and index are. */
1174 if (GET_CODE (reg1
) == REG
1175 && REG_POINTER (reg1
))
1178 idx
= gen_rtx_PLUS (Pmode
,
1179 gen_rtx_MULT (Pmode
,
1180 XEXP (XEXP (XEXP (x
, 0), 0), 0),
1181 XEXP (XEXP (XEXP (x
, 0), 0), 1)),
1184 else if (GET_CODE (reg2
) == REG
1185 && REG_POINTER (reg2
))
1194 /* If the index adds a large constant, try to scale the
1195 constant so that it can be loaded with only one insn. */
1196 if (GET_CODE (XEXP (idx
, 1)) == CONST_INT
1197 && VAL_14_BITS_P (INTVAL (XEXP (idx
, 1))
1198 / INTVAL (XEXP (XEXP (idx
, 0), 1)))
1199 && INTVAL (XEXP (idx
, 1)) % INTVAL (XEXP (XEXP (idx
, 0), 1)) == 0)
1201 /* Divide the CONST_INT by the scale factor, then add it to A. */
1202 int val
= INTVAL (XEXP (idx
, 1));
1204 val
/= INTVAL (XEXP (XEXP (idx
, 0), 1));
1205 reg1
= XEXP (XEXP (idx
, 0), 0);
1206 if (GET_CODE (reg1
) != REG
)
1207 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
1209 reg1
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, reg1
, GEN_INT (val
)));
1211 /* We can now generate a simple scaled indexed address. */
1214 (Pmode
, gen_rtx_PLUS (Pmode
,
1215 gen_rtx_MULT (Pmode
, reg1
,
1216 XEXP (XEXP (idx
, 0), 1)),
1220 /* If B + C is still a valid base register, then add them. */
1221 if (GET_CODE (XEXP (idx
, 1)) == CONST_INT
1222 && INTVAL (XEXP (idx
, 1)) <= 4096
1223 && INTVAL (XEXP (idx
, 1)) >= -4096)
1225 int val
= INTVAL (XEXP (XEXP (idx
, 0), 1));
1228 reg1
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, base
, XEXP (idx
, 1)));
1230 reg2
= XEXP (XEXP (idx
, 0), 0);
1231 if (GET_CODE (reg2
) != CONST_INT
)
1232 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
1234 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
,
1235 gen_rtx_MULT (Pmode
,
1241 /* Get the index into a register, then add the base + index and
1242 return a register holding the result. */
1244 /* First get A into a register. */
1245 reg1
= XEXP (XEXP (idx
, 0), 0);
1246 if (GET_CODE (reg1
) != REG
)
1247 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
1249 /* And get B into a register. */
1250 reg2
= XEXP (idx
, 1);
1251 if (GET_CODE (reg2
) != REG
)
1252 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
1254 reg1
= force_reg (Pmode
,
1255 gen_rtx_PLUS (Pmode
,
1256 gen_rtx_MULT (Pmode
, reg1
,
1257 XEXP (XEXP (idx
, 0), 1)),
1260 /* Add the result to our base register and return. */
1261 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
, base
, reg1
));
1265 /* Uh-oh. We might have an address for x[n-100000]. This needs
1266 special handling to avoid creating an indexed memory address
1267 with x-100000 as the base.
1269 If the constant part is small enough, then it's still safe because
1270 there is a guard page at the beginning and end of the data segment.
1272 Scaled references are common enough that we want to try and rearrange the
1273 terms so that we can use indexing for these addresses too. Only
1274 do the optimization for floatint point modes. */
1276 if (GET_CODE (x
) == PLUS
1277 && pa_symbolic_expression_p (XEXP (x
, 1)))
1279 /* Ugly. We modify things here so that the address offset specified
1280 by the index expression is computed first, then added to x to form
1281 the entire address. */
1283 rtx regx1
, regx2
, regy1
, regy2
, y
;
1285 /* Strip off any CONST. */
1287 if (GET_CODE (y
) == CONST
)
1290 if (GET_CODE (y
) == PLUS
|| GET_CODE (y
) == MINUS
)
1292 /* See if this looks like
1293 (plus (mult (reg) (shadd_const))
1294 (const (plus (symbol_ref) (const_int))))
1296 Where const_int is small. In that case the const
1297 expression is a valid pointer for indexing.
1299 If const_int is big, but can be divided evenly by shadd_const
1300 and added to (reg). This allows more scaled indexed addresses. */
1301 if (GET_CODE (XEXP (y
, 0)) == SYMBOL_REF
1302 && GET_CODE (XEXP (x
, 0)) == MULT
1303 && GET_CODE (XEXP (y
, 1)) == CONST_INT
1304 && INTVAL (XEXP (y
, 1)) >= -4096
1305 && INTVAL (XEXP (y
, 1)) <= 4095
1306 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1307 && pa_shadd_constant_p (INTVAL (XEXP (XEXP (x
, 0), 1))))
1309 int val
= INTVAL (XEXP (XEXP (x
, 0), 1));
1313 if (GET_CODE (reg1
) != REG
)
1314 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
1316 reg2
= XEXP (XEXP (x
, 0), 0);
1317 if (GET_CODE (reg2
) != REG
)
1318 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
1320 return force_reg (Pmode
,
1321 gen_rtx_PLUS (Pmode
,
1322 gen_rtx_MULT (Pmode
,
1327 else if ((mode
== DFmode
|| mode
== SFmode
)
1328 && GET_CODE (XEXP (y
, 0)) == SYMBOL_REF
1329 && GET_CODE (XEXP (x
, 0)) == MULT
1330 && GET_CODE (XEXP (y
, 1)) == CONST_INT
1331 && INTVAL (XEXP (y
, 1)) % INTVAL (XEXP (XEXP (x
, 0), 1)) == 0
1332 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1333 && pa_shadd_constant_p (INTVAL (XEXP (XEXP (x
, 0), 1))))
1336 = force_reg (Pmode
, GEN_INT (INTVAL (XEXP (y
, 1))
1337 / INTVAL (XEXP (XEXP (x
, 0), 1))));
1338 regx2
= XEXP (XEXP (x
, 0), 0);
1339 if (GET_CODE (regx2
) != REG
)
1340 regx2
= force_reg (Pmode
, force_operand (regx2
, 0));
1341 regx2
= force_reg (Pmode
, gen_rtx_fmt_ee (GET_CODE (y
), Pmode
,
1345 gen_rtx_PLUS (Pmode
,
1346 gen_rtx_MULT (Pmode
, regx2
,
1347 XEXP (XEXP (x
, 0), 1)),
1348 force_reg (Pmode
, XEXP (y
, 0))));
1350 else if (GET_CODE (XEXP (y
, 1)) == CONST_INT
1351 && INTVAL (XEXP (y
, 1)) >= -4096
1352 && INTVAL (XEXP (y
, 1)) <= 4095)
1354 /* This is safe because of the guard page at the
1355 beginning and end of the data space. Just
1356 return the original address. */
1361 /* Doesn't look like one we can optimize. */
1362 regx1
= force_reg (Pmode
, force_operand (XEXP (x
, 0), 0));
1363 regy1
= force_reg (Pmode
, force_operand (XEXP (y
, 0), 0));
1364 regy2
= force_reg (Pmode
, force_operand (XEXP (y
, 1), 0));
1365 regx1
= force_reg (Pmode
,
1366 gen_rtx_fmt_ee (GET_CODE (y
), Pmode
,
1368 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
, regx1
, regy1
));
1376 /* Implement the TARGET_REGISTER_MOVE_COST hook.
1378 Compute extra cost of moving data between one register class
1381 Make moves from SAR so expensive they should never happen. We used to
1382 have 0xffff here, but that generates overflow in rare cases.
1384 Copies involving a FP register and a non-FP register are relatively
1385 expensive because they must go through memory.
1387 Other copies are reasonably cheap. */
1390 hppa_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
1391 reg_class_t from
, reg_class_t to
)
1393 if (from
== SHIFT_REGS
)
1395 else if (to
== SHIFT_REGS
&& FP_REG_CLASS_P (from
))
1397 else if ((FP_REG_CLASS_P (from
) && ! FP_REG_CLASS_P (to
))
1398 || (FP_REG_CLASS_P (to
) && ! FP_REG_CLASS_P (from
)))
1404 /* For the HPPA, REG and REG+CONST is cost 0
1405 and addresses involving symbolic constants are cost 2.
1407 PIC addresses are very expensive.
1409 It is no coincidence that this has the same structure
1410 as pa_legitimate_address_p. */
1413 hppa_address_cost (rtx X
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1414 addr_space_t as ATTRIBUTE_UNUSED
,
1415 bool speed ATTRIBUTE_UNUSED
)
1417 switch (GET_CODE (X
))
1430 /* Compute a (partial) cost for rtx X. Return true if the complete
1431 cost has been computed, and false if subexpressions should be
1432 scanned. In either case, *TOTAL contains the cost result. */
1435 hppa_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
1436 int *total
, bool speed ATTRIBUTE_UNUSED
)
1443 if (INTVAL (x
) == 0)
1445 else if (INT_14_BITS (x
))
1462 if ((x
== CONST0_RTX (DFmode
) || x
== CONST0_RTX (SFmode
))
1463 && outer_code
!= SET
)
1470 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
1472 *total
= COSTS_N_INSNS (3);
1476 /* A mode size N times larger than SImode needs O(N*N) more insns. */
1477 factor
= GET_MODE_SIZE (GET_MODE (x
)) / 4;
1481 if (TARGET_PA_11
&& !TARGET_DISABLE_FPREGS
&& !TARGET_SOFT_FLOAT
)
1482 *total
= factor
* factor
* COSTS_N_INSNS (8);
1484 *total
= factor
* factor
* COSTS_N_INSNS (20);
1488 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
1490 *total
= COSTS_N_INSNS (14);
1498 /* A mode size N times larger than SImode needs O(N*N) more insns. */
1499 factor
= GET_MODE_SIZE (GET_MODE (x
)) / 4;
1503 *total
= factor
* factor
* COSTS_N_INSNS (60);
1506 case PLUS
: /* this includes shNadd insns */
1508 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
1510 *total
= COSTS_N_INSNS (3);
1514 /* A size N times larger than UNITS_PER_WORD needs N times as
1515 many insns, taking N times as long. */
1516 factor
= GET_MODE_SIZE (GET_MODE (x
)) / UNITS_PER_WORD
;
1519 *total
= factor
* COSTS_N_INSNS (1);
1525 *total
= COSTS_N_INSNS (1);
1533 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1534 new rtx with the correct mode. */
1536 force_mode (enum machine_mode mode
, rtx orig
)
1538 if (mode
== GET_MODE (orig
))
1541 gcc_assert (REGNO (orig
) < FIRST_PSEUDO_REGISTER
);
1543 return gen_rtx_REG (mode
, REGNO (orig
));
1546 /* Return 1 if *X is a thread-local symbol. */
1549 pa_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
1551 return PA_SYMBOL_REF_TLS_P (*x
);
1554 /* Return 1 if X contains a thread-local symbol. */
1557 pa_tls_referenced_p (rtx x
)
1559 if (!TARGET_HAVE_TLS
)
1562 return for_each_rtx (&x
, &pa_tls_symbol_ref_1
, 0);
1565 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1568 pa_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1570 return pa_tls_referenced_p (x
);
1573 /* Emit insns to move operands[1] into operands[0].
1575 Return 1 if we have written out everything that needs to be done to
1576 do the move. Otherwise, return 0 and the caller will emit the move
1579 Note SCRATCH_REG may not be in the proper mode depending on how it
1580 will be used. This routine is responsible for creating a new copy
1581 of SCRATCH_REG in the proper mode. */
1584 pa_emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
1586 register rtx operand0
= operands
[0];
1587 register rtx operand1
= operands
[1];
1590 /* We can only handle indexed addresses in the destination operand
1591 of floating point stores. Thus, we need to break out indexed
1592 addresses from the destination operand. */
1593 if (GET_CODE (operand0
) == MEM
&& IS_INDEX_ADDR_P (XEXP (operand0
, 0)))
1595 gcc_assert (can_create_pseudo_p ());
1597 tem
= copy_to_mode_reg (Pmode
, XEXP (operand0
, 0));
1598 operand0
= replace_equiv_address (operand0
, tem
);
1601 /* On targets with non-equivalent space registers, break out unscaled
1602 indexed addresses from the source operand before the final CSE.
1603 We have to do this because the REG_POINTER flag is not correctly
1604 carried through various optimization passes and CSE may substitute
1605 a pseudo without the pointer set for one with the pointer set. As
1606 a result, we loose various opportunities to create insns with
1607 unscaled indexed addresses. */
1608 if (!TARGET_NO_SPACE_REGS
1609 && !cse_not_expected
1610 && GET_CODE (operand1
) == MEM
1611 && GET_CODE (XEXP (operand1
, 0)) == PLUS
1612 && REG_P (XEXP (XEXP (operand1
, 0), 0))
1613 && REG_P (XEXP (XEXP (operand1
, 0), 1)))
1615 = replace_equiv_address (operand1
,
1616 copy_to_mode_reg (Pmode
, XEXP (operand1
, 0)));
1619 && reload_in_progress
&& GET_CODE (operand0
) == REG
1620 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
1621 operand0
= reg_equiv_mem (REGNO (operand0
));
1622 else if (scratch_reg
1623 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
1624 && GET_CODE (SUBREG_REG (operand0
)) == REG
1625 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
1627 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1628 the code which tracks sets/uses for delete_output_reload. */
1629 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
1630 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
1631 SUBREG_BYTE (operand0
));
1632 operand0
= alter_subreg (&temp
, true);
1636 && reload_in_progress
&& GET_CODE (operand1
) == REG
1637 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
1638 operand1
= reg_equiv_mem (REGNO (operand1
));
1639 else if (scratch_reg
1640 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
1641 && GET_CODE (SUBREG_REG (operand1
)) == REG
1642 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
1644 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1645 the code which tracks sets/uses for delete_output_reload. */
1646 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
1647 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
1648 SUBREG_BYTE (operand1
));
1649 operand1
= alter_subreg (&temp
, true);
1652 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
1653 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
1654 != XEXP (operand0
, 0)))
1655 operand0
= replace_equiv_address (operand0
, tem
);
1657 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
1658 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
1659 != XEXP (operand1
, 0)))
1660 operand1
= replace_equiv_address (operand1
, tem
);
1662 /* Handle secondary reloads for loads/stores of FP registers from
1663 REG+D addresses where D does not fit in 5 or 14 bits, including
1664 (subreg (mem (addr))) cases. */
1666 && fp_reg_operand (operand0
, mode
)
1667 && (MEM_P (operand1
)
1668 || (GET_CODE (operand1
) == SUBREG
1669 && MEM_P (XEXP (operand1
, 0))))
1670 && !floating_point_store_memory_operand (operand1
, mode
))
1672 if (GET_CODE (operand1
) == SUBREG
)
1673 operand1
= XEXP (operand1
, 0);
1675 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1676 it in WORD_MODE regardless of what mode it was originally given
1678 scratch_reg
= force_mode (word_mode
, scratch_reg
);
1680 /* D might not fit in 14 bits either; for such cases load D into
1682 if (reg_plus_base_memory_operand (operand1
, mode
)
1685 && INT_14_BITS (XEXP (XEXP (operand1
, 0), 1))))
1687 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
1688 emit_move_insn (scratch_reg
,
1689 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
1691 XEXP (XEXP (operand1
, 0), 0),
1695 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
1696 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
1697 replace_equiv_address (operand1
, scratch_reg
)));
1700 else if (scratch_reg
1701 && fp_reg_operand (operand1
, mode
)
1702 && (MEM_P (operand0
)
1703 || (GET_CODE (operand0
) == SUBREG
1704 && MEM_P (XEXP (operand0
, 0))))
1705 && !floating_point_store_memory_operand (operand0
, mode
))
1707 if (GET_CODE (operand0
) == SUBREG
)
1708 operand0
= XEXP (operand0
, 0);
1710 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1711 it in WORD_MODE regardless of what mode it was originally given
1713 scratch_reg
= force_mode (word_mode
, scratch_reg
);
1715 /* D might not fit in 14 bits either; for such cases load D into
1717 if (reg_plus_base_memory_operand (operand0
, mode
)
1720 && INT_14_BITS (XEXP (XEXP (operand0
, 0), 1))))
1722 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
1723 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
1726 XEXP (XEXP (operand0
, 0),
1731 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
1732 emit_insn (gen_rtx_SET (VOIDmode
,
1733 replace_equiv_address (operand0
, scratch_reg
),
1737 /* Handle secondary reloads for loads of FP registers from constant
1738 expressions by forcing the constant into memory. For the most part,
1739 this is only necessary for SImode and DImode.
1741 Use scratch_reg to hold the address of the memory location. */
1742 else if (scratch_reg
1743 && CONSTANT_P (operand1
)
1744 && fp_reg_operand (operand0
, mode
))
1746 rtx const_mem
, xoperands
[2];
1748 if (operand1
== CONST0_RTX (mode
))
1750 emit_insn (gen_rtx_SET (VOIDmode
, operand0
, operand1
));
1754 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1755 it in WORD_MODE regardless of what mode it was originally given
1757 scratch_reg
= force_mode (word_mode
, scratch_reg
);
1759 /* Force the constant into memory and put the address of the
1760 memory location into scratch_reg. */
1761 const_mem
= force_const_mem (mode
, operand1
);
1762 xoperands
[0] = scratch_reg
;
1763 xoperands
[1] = XEXP (const_mem
, 0);
1764 pa_emit_move_sequence (xoperands
, Pmode
, 0);
1766 /* Now load the destination register. */
1767 emit_insn (gen_rtx_SET (mode
, operand0
,
1768 replace_equiv_address (const_mem
, scratch_reg
)));
1771 /* Handle secondary reloads for SAR. These occur when trying to load
1772 the SAR from memory or a constant. */
1773 else if (scratch_reg
1774 && GET_CODE (operand0
) == REG
1775 && REGNO (operand0
) < FIRST_PSEUDO_REGISTER
1776 && REGNO_REG_CLASS (REGNO (operand0
)) == SHIFT_REGS
1777 && (GET_CODE (operand1
) == MEM
|| GET_CODE (operand1
) == CONST_INT
))
1779 /* D might not fit in 14 bits either; for such cases load D into
1781 if (GET_CODE (operand1
) == MEM
1782 && !memory_address_p (GET_MODE (operand0
), XEXP (operand1
, 0)))
1784 /* We are reloading the address into the scratch register, so we
1785 want to make sure the scratch register is a full register. */
1786 scratch_reg
= force_mode (word_mode
, scratch_reg
);
1788 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
1789 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
,
1792 XEXP (XEXP (operand1
, 0),
1796 /* Now we are going to load the scratch register from memory,
1797 we want to load it in the same width as the original MEM,
1798 which must be the same as the width of the ultimate destination,
1800 scratch_reg
= force_mode (GET_MODE (operand0
), scratch_reg
);
1802 emit_move_insn (scratch_reg
,
1803 replace_equiv_address (operand1
, scratch_reg
));
1807 /* We want to load the scratch register using the same mode as
1808 the ultimate destination. */
1809 scratch_reg
= force_mode (GET_MODE (operand0
), scratch_reg
);
1811 emit_move_insn (scratch_reg
, operand1
);
1814 /* And emit the insn to set the ultimate destination. We know that
1815 the scratch register has the same mode as the destination at this
1817 emit_move_insn (operand0
, scratch_reg
);
1820 /* Handle the most common case: storing into a register. */
1821 else if (register_operand (operand0
, mode
))
1823 /* Legitimize TLS symbol references. This happens for references
1824 that aren't a legitimate constant. */
1825 if (PA_SYMBOL_REF_TLS_P (operand1
))
1826 operand1
= legitimize_tls_address (operand1
);
1828 if (register_operand (operand1
, mode
)
1829 || (GET_CODE (operand1
) == CONST_INT
1830 && pa_cint_ok_for_move (INTVAL (operand1
)))
1831 || (operand1
== CONST0_RTX (mode
))
1832 || (GET_CODE (operand1
) == HIGH
1833 && !symbolic_operand (XEXP (operand1
, 0), VOIDmode
))
1834 /* Only `general_operands' can come here, so MEM is ok. */
1835 || GET_CODE (operand1
) == MEM
)
1837 /* Various sets are created during RTL generation which don't
1838 have the REG_POINTER flag correctly set. After the CSE pass,
1839 instruction recognition can fail if we don't consistently
1840 set this flag when performing register copies. This should
1841 also improve the opportunities for creating insns that use
1842 unscaled indexing. */
1843 if (REG_P (operand0
) && REG_P (operand1
))
1845 if (REG_POINTER (operand1
)
1846 && !REG_POINTER (operand0
)
1847 && !HARD_REGISTER_P (operand0
))
1848 copy_reg_pointer (operand0
, operand1
);
1851 /* When MEMs are broken out, the REG_POINTER flag doesn't
1852 get set. In some cases, we can set the REG_POINTER flag
1853 from the declaration for the MEM. */
1854 if (REG_P (operand0
)
1855 && GET_CODE (operand1
) == MEM
1856 && !REG_POINTER (operand0
))
1858 tree decl
= MEM_EXPR (operand1
);
1860 /* Set the register pointer flag and register alignment
1861 if the declaration for this memory reference is a
1867 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1869 if (TREE_CODE (decl
) == COMPONENT_REF
)
1870 decl
= TREE_OPERAND (decl
, 1);
1872 type
= TREE_TYPE (decl
);
1873 type
= strip_array_types (type
);
1875 if (POINTER_TYPE_P (type
))
1879 type
= TREE_TYPE (type
);
1880 /* Using TYPE_ALIGN_OK is rather conservative as
1881 only the ada frontend actually sets it. */
1882 align
= (TYPE_ALIGN_OK (type
) ? TYPE_ALIGN (type
)
1884 mark_reg_pointer (operand0
, align
);
1889 emit_insn (gen_rtx_SET (VOIDmode
, operand0
, operand1
));
1893 else if (GET_CODE (operand0
) == MEM
)
1895 if (mode
== DFmode
&& operand1
== CONST0_RTX (mode
)
1896 && !(reload_in_progress
|| reload_completed
))
1898 rtx temp
= gen_reg_rtx (DFmode
);
1900 emit_insn (gen_rtx_SET (VOIDmode
, temp
, operand1
));
1901 emit_insn (gen_rtx_SET (VOIDmode
, operand0
, temp
));
1904 if (register_operand (operand1
, mode
) || operand1
== CONST0_RTX (mode
))
1906 /* Run this case quickly. */
1907 emit_insn (gen_rtx_SET (VOIDmode
, operand0
, operand1
));
1910 if (! (reload_in_progress
|| reload_completed
))
1912 operands
[0] = validize_mem (operand0
);
1913 operands
[1] = operand1
= force_reg (mode
, operand1
);
1917 /* Simplify the source if we need to.
1918 Note we do have to handle function labels here, even though we do
1919 not consider them legitimate constants. Loop optimizations can
1920 call the emit_move_xxx with one as a source. */
1921 if ((GET_CODE (operand1
) != HIGH
&& immediate_operand (operand1
, mode
))
1922 || (GET_CODE (operand1
) == HIGH
1923 && symbolic_operand (XEXP (operand1
, 0), mode
))
1924 || function_label_operand (operand1
, VOIDmode
)
1925 || pa_tls_referenced_p (operand1
))
1929 if (GET_CODE (operand1
) == HIGH
)
1932 operand1
= XEXP (operand1
, 0);
1934 if (symbolic_operand (operand1
, mode
))
1936 /* Argh. The assembler and linker can't handle arithmetic
1939 So we force the plabel into memory, load operand0 from
1940 the memory location, then add in the constant part. */
1941 if ((GET_CODE (operand1
) == CONST
1942 && GET_CODE (XEXP (operand1
, 0)) == PLUS
1943 && function_label_operand (XEXP (XEXP (operand1
, 0), 0),
1945 || function_label_operand (operand1
, VOIDmode
))
1947 rtx temp
, const_part
;
1949 /* Figure out what (if any) scratch register to use. */
1950 if (reload_in_progress
|| reload_completed
)
1952 scratch_reg
= scratch_reg
? scratch_reg
: operand0
;
1953 /* SCRATCH_REG will hold an address and maybe the actual
1954 data. We want it in WORD_MODE regardless of what mode it
1955 was originally given to us. */
1956 scratch_reg
= force_mode (word_mode
, scratch_reg
);
1959 scratch_reg
= gen_reg_rtx (Pmode
);
1961 if (GET_CODE (operand1
) == CONST
)
1963 /* Save away the constant part of the expression. */
1964 const_part
= XEXP (XEXP (operand1
, 0), 1);
1965 gcc_assert (GET_CODE (const_part
) == CONST_INT
);
1967 /* Force the function label into memory. */
1968 temp
= force_const_mem (mode
, XEXP (XEXP (operand1
, 0), 0));
1972 /* No constant part. */
1973 const_part
= NULL_RTX
;
1975 /* Force the function label into memory. */
1976 temp
= force_const_mem (mode
, operand1
);
1980 /* Get the address of the memory location. PIC-ify it if
1982 temp
= XEXP (temp
, 0);
1984 temp
= legitimize_pic_address (temp
, mode
, scratch_reg
);
1986 /* Put the address of the memory location into our destination
1989 pa_emit_move_sequence (operands
, mode
, scratch_reg
);
1991 /* Now load from the memory location into our destination
1993 operands
[1] = gen_rtx_MEM (Pmode
, operands
[0]);
1994 pa_emit_move_sequence (operands
, mode
, scratch_reg
);
1996 /* And add back in the constant part. */
1997 if (const_part
!= NULL_RTX
)
1998 expand_inc (operand0
, const_part
);
2007 if (reload_in_progress
|| reload_completed
)
2009 temp
= scratch_reg
? scratch_reg
: operand0
;
2010 /* TEMP will hold an address and maybe the actual
2011 data. We want it in WORD_MODE regardless of what mode it
2012 was originally given to us. */
2013 temp
= force_mode (word_mode
, temp
);
2016 temp
= gen_reg_rtx (Pmode
);
2018 /* (const (plus (symbol) (const_int))) must be forced to
2019 memory during/after reload if the const_int will not fit
2021 if (GET_CODE (operand1
) == CONST
2022 && GET_CODE (XEXP (operand1
, 0)) == PLUS
2023 && GET_CODE (XEXP (XEXP (operand1
, 0), 1)) == CONST_INT
2024 && !INT_14_BITS (XEXP (XEXP (operand1
, 0), 1))
2025 && (reload_completed
|| reload_in_progress
)
2028 rtx const_mem
= force_const_mem (mode
, operand1
);
2029 operands
[1] = legitimize_pic_address (XEXP (const_mem
, 0),
2031 operands
[1] = replace_equiv_address (const_mem
, operands
[1]);
2032 pa_emit_move_sequence (operands
, mode
, temp
);
2036 operands
[1] = legitimize_pic_address (operand1
, mode
, temp
);
2037 if (REG_P (operand0
) && REG_P (operands
[1]))
2038 copy_reg_pointer (operand0
, operands
[1]);
2039 emit_insn (gen_rtx_SET (VOIDmode
, operand0
, operands
[1]));
2042 /* On the HPPA, references to data space are supposed to use dp,
2043 register 27, but showing it in the RTL inhibits various cse
2044 and loop optimizations. */
2049 if (reload_in_progress
|| reload_completed
)
2051 temp
= scratch_reg
? scratch_reg
: operand0
;
2052 /* TEMP will hold an address and maybe the actual
2053 data. We want it in WORD_MODE regardless of what mode it
2054 was originally given to us. */
2055 temp
= force_mode (word_mode
, temp
);
2058 temp
= gen_reg_rtx (mode
);
2060 /* Loading a SYMBOL_REF into a register makes that register
2061 safe to be used as the base in an indexed address.
2063 Don't mark hard registers though. That loses. */
2064 if (GET_CODE (operand0
) == REG
2065 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
2066 mark_reg_pointer (operand0
, BITS_PER_UNIT
);
2067 if (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
)
2068 mark_reg_pointer (temp
, BITS_PER_UNIT
);
2071 set
= gen_rtx_SET (mode
, operand0
, temp
);
2073 set
= gen_rtx_SET (VOIDmode
,
2075 gen_rtx_LO_SUM (mode
, temp
, operand1
));
2077 emit_insn (gen_rtx_SET (VOIDmode
,
2079 gen_rtx_HIGH (mode
, operand1
)));
2085 else if (pa_tls_referenced_p (operand1
))
2090 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
2092 addend
= XEXP (XEXP (tmp
, 0), 1);
2093 tmp
= XEXP (XEXP (tmp
, 0), 0);
2096 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
2097 tmp
= legitimize_tls_address (tmp
);
2100 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
2101 tmp
= force_operand (tmp
, operands
[0]);
2105 else if (GET_CODE (operand1
) != CONST_INT
2106 || !pa_cint_ok_for_move (INTVAL (operand1
)))
2110 HOST_WIDE_INT value
= 0;
2111 HOST_WIDE_INT insv
= 0;
2114 if (GET_CODE (operand1
) == CONST_INT
)
2115 value
= INTVAL (operand1
);
2118 && GET_CODE (operand1
) == CONST_INT
2119 && HOST_BITS_PER_WIDE_INT
> 32
2120 && GET_MODE_BITSIZE (GET_MODE (operand0
)) > 32)
2124 /* Extract the low order 32 bits of the value and sign extend.
2125 If the new value is the same as the original value, we can
2126 can use the original value as-is. If the new value is
2127 different, we use it and insert the most-significant 32-bits
2128 of the original value into the final result. */
2129 nval
= ((value
& (((HOST_WIDE_INT
) 2 << 31) - 1))
2130 ^ ((HOST_WIDE_INT
) 1 << 31)) - ((HOST_WIDE_INT
) 1 << 31);
2133 #if HOST_BITS_PER_WIDE_INT > 32
2134 insv
= value
>= 0 ? value
>> 32 : ~(~value
>> 32);
2138 operand1
= GEN_INT (nval
);
2142 if (reload_in_progress
|| reload_completed
)
2143 temp
= scratch_reg
? scratch_reg
: operand0
;
2145 temp
= gen_reg_rtx (mode
);
2147 /* We don't directly split DImode constants on 32-bit targets
2148 because PLUS uses an 11-bit immediate and the insn sequence
2149 generated is not as efficient as the one using HIGH/LO_SUM. */
2150 if (GET_CODE (operand1
) == CONST_INT
2151 && GET_MODE_BITSIZE (mode
) <= BITS_PER_WORD
2152 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
2155 /* Directly break constant into high and low parts. This
2156 provides better optimization opportunities because various
2157 passes recognize constants split with PLUS but not LO_SUM.
2158 We use a 14-bit signed low part except when the addition
2159 of 0x4000 to the high part might change the sign of the
2161 HOST_WIDE_INT low
= value
& 0x3fff;
2162 HOST_WIDE_INT high
= value
& ~ 0x3fff;
2166 if (high
== 0x7fffc000 || (mode
== HImode
&& high
== 0x4000))
2174 emit_insn (gen_rtx_SET (VOIDmode
, temp
, GEN_INT (high
)));
2175 operands
[1] = gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
2179 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
2180 gen_rtx_HIGH (mode
, operand1
)));
2181 operands
[1] = gen_rtx_LO_SUM (mode
, temp
, operand1
);
2184 insn
= emit_move_insn (operands
[0], operands
[1]);
2186 /* Now insert the most significant 32 bits of the value
2187 into the register. When we don't have a second register
2188 available, it could take up to nine instructions to load
2189 a 64-bit integer constant. Prior to reload, we force
2190 constants that would take more than three instructions
2191 to load to the constant pool. During and after reload,
2192 we have to handle all possible values. */
2195 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
2196 register and the value to be inserted is outside the
2197 range that can be loaded with three depdi instructions. */
2198 if (temp
!= operand0
&& (insv
>= 16384 || insv
< -16384))
2200 operand1
= GEN_INT (insv
);
2202 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
2203 gen_rtx_HIGH (mode
, operand1
)));
2204 emit_move_insn (temp
, gen_rtx_LO_SUM (mode
, temp
, operand1
));
2206 emit_insn (gen_insvdi (operand0
, GEN_INT (32),
2209 emit_insn (gen_insvsi (operand0
, GEN_INT (32),
2214 int len
= 5, pos
= 27;
2216 /* Insert the bits using the depdi instruction. */
2219 HOST_WIDE_INT v5
= ((insv
& 31) ^ 16) - 16;
2220 HOST_WIDE_INT sign
= v5
< 0;
2222 /* Left extend the insertion. */
2223 insv
= (insv
>= 0 ? insv
>> len
: ~(~insv
>> len
));
2224 while (pos
> 0 && (insv
& 1) == sign
)
2226 insv
= (insv
>= 0 ? insv
>> 1 : ~(~insv
>> 1));
2232 emit_insn (gen_insvdi (operand0
, GEN_INT (len
),
2233 GEN_INT (pos
), GEN_INT (v5
)));
2235 emit_insn (gen_insvsi (operand0
, GEN_INT (len
),
2236 GEN_INT (pos
), GEN_INT (v5
)));
2238 len
= pos
> 0 && pos
< 5 ? pos
: 5;
2244 set_unique_reg_note (insn
, REG_EQUAL
, op1
);
2249 /* Now have insn-emit do whatever it normally does. */
2253 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
2254 it will need a link/runtime reloc). */
2257 pa_reloc_needed (tree exp
)
2261 switch (TREE_CODE (exp
))
2266 case POINTER_PLUS_EXPR
:
2269 reloc
= pa_reloc_needed (TREE_OPERAND (exp
, 0));
2270 reloc
|= pa_reloc_needed (TREE_OPERAND (exp
, 1));
2274 case NON_LVALUE_EXPR
:
2275 reloc
= pa_reloc_needed (TREE_OPERAND (exp
, 0));
2281 unsigned HOST_WIDE_INT ix
;
2283 FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (exp
), ix
, value
)
2285 reloc
|= pa_reloc_needed (value
);
2299 /* Return the best assembler insn template
2300 for moving operands[1] into operands[0] as a fullword. */
2302 pa_singlemove_string (rtx
*operands
)
2304 HOST_WIDE_INT intval
;
2306 if (GET_CODE (operands
[0]) == MEM
)
2307 return "stw %r1,%0";
2308 if (GET_CODE (operands
[1]) == MEM
)
2310 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2315 gcc_assert (GET_MODE (operands
[1]) == SFmode
);
2317 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2319 REAL_VALUE_FROM_CONST_DOUBLE (d
, operands
[1]);
2320 REAL_VALUE_TO_TARGET_SINGLE (d
, i
);
2322 operands
[1] = GEN_INT (i
);
2323 /* Fall through to CONST_INT case. */
2325 if (GET_CODE (operands
[1]) == CONST_INT
)
2327 intval
= INTVAL (operands
[1]);
2329 if (VAL_14_BITS_P (intval
))
2331 else if ((intval
& 0x7ff) == 0)
2332 return "ldil L'%1,%0";
2333 else if (pa_zdepi_cint_p (intval
))
2334 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2336 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2338 return "copy %1,%0";
2342 /* Compute position (in OP[1]) and width (in OP[2])
2343 useful for copying IMM to a register using the zdepi
2344 instructions. Store the immediate value to insert in OP[0]. */
2346 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm
, unsigned *op
)
2350 /* Find the least significant set bit in IMM. */
2351 for (lsb
= 0; lsb
< 32; lsb
++)
2358 /* Choose variants based on *sign* of the 5-bit field. */
2359 if ((imm
& 0x10) == 0)
2360 len
= (lsb
<= 28) ? 4 : 32 - lsb
;
2363 /* Find the width of the bitstring in IMM. */
2364 for (len
= 5; len
< 32 - lsb
; len
++)
2366 if ((imm
& ((unsigned HOST_WIDE_INT
) 1 << len
)) == 0)
2370 /* Sign extend IMM as a 5-bit value. */
2371 imm
= (imm
& 0xf) - 0x10;
2379 /* Compute position (in OP[1]) and width (in OP[2])
2380 useful for copying IMM to a register using the depdi,z
2381 instructions. Store the immediate value to insert in OP[0]. */
2384 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm
, unsigned *op
)
2386 int lsb
, len
, maxlen
;
2388 maxlen
= MIN (HOST_BITS_PER_WIDE_INT
, 64);
2390 /* Find the least significant set bit in IMM. */
2391 for (lsb
= 0; lsb
< maxlen
; lsb
++)
2398 /* Choose variants based on *sign* of the 5-bit field. */
2399 if ((imm
& 0x10) == 0)
2400 len
= (lsb
<= maxlen
- 4) ? 4 : maxlen
- lsb
;
2403 /* Find the width of the bitstring in IMM. */
2404 for (len
= 5; len
< maxlen
- lsb
; len
++)
2406 if ((imm
& ((unsigned HOST_WIDE_INT
) 1 << len
)) == 0)
2410 /* Extend length if host is narrow and IMM is negative. */
2411 if (HOST_BITS_PER_WIDE_INT
== 32 && len
== maxlen
- lsb
)
2414 /* Sign extend IMM as a 5-bit value. */
2415 imm
= (imm
& 0xf) - 0x10;
2423 /* Output assembler code to perform a doubleword move insn
2424 with operands OPERANDS. */
2427 pa_output_move_double (rtx
*operands
)
2429 enum { REGOP
, OFFSOP
, MEMOP
, CNSTOP
, RNDOP
} optype0
, optype1
;
2431 rtx addreg0
= 0, addreg1
= 0;
2433 /* First classify both operands. */
2435 if (REG_P (operands
[0]))
2437 else if (offsettable_memref_p (operands
[0]))
2439 else if (GET_CODE (operands
[0]) == MEM
)
2444 if (REG_P (operands
[1]))
2446 else if (CONSTANT_P (operands
[1]))
2448 else if (offsettable_memref_p (operands
[1]))
2450 else if (GET_CODE (operands
[1]) == MEM
)
2455 /* Check for the cases that the operand constraints are not
2456 supposed to allow to happen. */
2457 gcc_assert (optype0
== REGOP
|| optype1
== REGOP
);
2459 /* Handle copies between general and floating registers. */
2461 if (optype0
== REGOP
&& optype1
== REGOP
2462 && FP_REG_P (operands
[0]) ^ FP_REG_P (operands
[1]))
2464 if (FP_REG_P (operands
[0]))
2466 output_asm_insn ("{stws|stw} %1,-16(%%sp)", operands
);
2467 output_asm_insn ("{stws|stw} %R1,-12(%%sp)", operands
);
2468 return "{fldds|fldd} -16(%%sp),%0";
2472 output_asm_insn ("{fstds|fstd} %1,-16(%%sp)", operands
);
2473 output_asm_insn ("{ldws|ldw} -16(%%sp),%0", operands
);
2474 return "{ldws|ldw} -12(%%sp),%R0";
2478 /* Handle auto decrementing and incrementing loads and stores
2479 specifically, since the structure of the function doesn't work
2480 for them without major modification. Do it better when we learn
2481 this port about the general inc/dec addressing of PA.
2482 (This was written by tege. Chide him if it doesn't work.) */
2484 if (optype0
== MEMOP
)
2486 /* We have to output the address syntax ourselves, since print_operand
2487 doesn't deal with the addresses we want to use. Fix this later. */
2489 rtx addr
= XEXP (operands
[0], 0);
2490 if (GET_CODE (addr
) == POST_INC
|| GET_CODE (addr
) == POST_DEC
)
2492 rtx high_reg
= gen_rtx_SUBREG (SImode
, operands
[1], 0);
2494 operands
[0] = XEXP (addr
, 0);
2495 gcc_assert (GET_CODE (operands
[1]) == REG
2496 && GET_CODE (operands
[0]) == REG
);
2498 gcc_assert (!reg_overlap_mentioned_p (high_reg
, addr
));
2500 /* No overlap between high target register and address
2501 register. (We do this in a non-obvious way to
2502 save a register file writeback) */
2503 if (GET_CODE (addr
) == POST_INC
)
2504 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2505 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2507 else if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
2509 rtx high_reg
= gen_rtx_SUBREG (SImode
, operands
[1], 0);
2511 operands
[0] = XEXP (addr
, 0);
2512 gcc_assert (GET_CODE (operands
[1]) == REG
2513 && GET_CODE (operands
[0]) == REG
);
2515 gcc_assert (!reg_overlap_mentioned_p (high_reg
, addr
));
2516 /* No overlap between high target register and address
2517 register. (We do this in a non-obvious way to save a
2518 register file writeback) */
2519 if (GET_CODE (addr
) == PRE_INC
)
2520 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2521 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2524 if (optype1
== MEMOP
)
2526 /* We have to output the address syntax ourselves, since print_operand
2527 doesn't deal with the addresses we want to use. Fix this later. */
2529 rtx addr
= XEXP (operands
[1], 0);
2530 if (GET_CODE (addr
) == POST_INC
|| GET_CODE (addr
) == POST_DEC
)
2532 rtx high_reg
= gen_rtx_SUBREG (SImode
, operands
[0], 0);
2534 operands
[1] = XEXP (addr
, 0);
2535 gcc_assert (GET_CODE (operands
[0]) == REG
2536 && GET_CODE (operands
[1]) == REG
);
2538 if (!reg_overlap_mentioned_p (high_reg
, addr
))
2540 /* No overlap between high target register and address
2541 register. (We do this in a non-obvious way to
2542 save a register file writeback) */
2543 if (GET_CODE (addr
) == POST_INC
)
2544 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2545 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2549 /* This is an undefined situation. We should load into the
2550 address register *and* update that register. Probably
2551 we don't need to handle this at all. */
2552 if (GET_CODE (addr
) == POST_INC
)
2553 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2554 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2557 else if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
2559 rtx high_reg
= gen_rtx_SUBREG (SImode
, operands
[0], 0);
2561 operands
[1] = XEXP (addr
, 0);
2562 gcc_assert (GET_CODE (operands
[0]) == REG
2563 && GET_CODE (operands
[1]) == REG
);
2565 if (!reg_overlap_mentioned_p (high_reg
, addr
))
2567 /* No overlap between high target register and address
2568 register. (We do this in a non-obvious way to
2569 save a register file writeback) */
2570 if (GET_CODE (addr
) == PRE_INC
)
2571 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2572 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2576 /* This is an undefined situation. We should load into the
2577 address register *and* update that register. Probably
2578 we don't need to handle this at all. */
2579 if (GET_CODE (addr
) == PRE_INC
)
2580 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2581 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2584 else if (GET_CODE (addr
) == PLUS
2585 && GET_CODE (XEXP (addr
, 0)) == MULT
)
2588 rtx high_reg
= gen_rtx_SUBREG (SImode
, operands
[0], 0);
2590 if (!reg_overlap_mentioned_p (high_reg
, addr
))
2592 xoperands
[0] = high_reg
;
2593 xoperands
[1] = XEXP (addr
, 1);
2594 xoperands
[2] = XEXP (XEXP (addr
, 0), 0);
2595 xoperands
[3] = XEXP (XEXP (addr
, 0), 1);
2596 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2598 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2602 xoperands
[0] = high_reg
;
2603 xoperands
[1] = XEXP (addr
, 1);
2604 xoperands
[2] = XEXP (XEXP (addr
, 0), 0);
2605 xoperands
[3] = XEXP (XEXP (addr
, 0), 1);
2606 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2608 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2613 /* If an operand is an unoffsettable memory ref, find a register
2614 we can increment temporarily to make it refer to the second word. */
2616 if (optype0
== MEMOP
)
2617 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2619 if (optype1
== MEMOP
)
2620 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2622 /* Ok, we can do one word at a time.
2623 Normally we do the low-numbered word first.
2625 In either case, set up in LATEHALF the operands to use
2626 for the high-numbered word and in some cases alter the
2627 operands in OPERANDS to be suitable for the low-numbered word. */
2629 if (optype0
== REGOP
)
2630 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2631 else if (optype0
== OFFSOP
)
2632 latehalf
[0] = adjust_address_nv (operands
[0], SImode
, 4);
2634 latehalf
[0] = operands
[0];
2636 if (optype1
== REGOP
)
2637 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2638 else if (optype1
== OFFSOP
)
2639 latehalf
[1] = adjust_address_nv (operands
[1], SImode
, 4);
2640 else if (optype1
== CNSTOP
)
2641 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2643 latehalf
[1] = operands
[1];
2645 /* If the first move would clobber the source of the second one,
2646 do them in the other order.
2648 This can happen in two cases:
2650 mem -> register where the first half of the destination register
2651 is the same register used in the memory's address. Reload
2652 can create such insns.
2654 mem in this case will be either register indirect or register
2655 indirect plus a valid offset.
2657 register -> register move where REGNO(dst) == REGNO(src + 1)
2658 someone (Tim/Tege?) claimed this can happen for parameter loads.
2660 Handle mem -> register case first. */
2661 if (optype0
== REGOP
2662 && (optype1
== MEMOP
|| optype1
== OFFSOP
)
2663 && refers_to_regno_p (REGNO (operands
[0]), REGNO (operands
[0]) + 1,
2666 /* Do the late half first. */
2668 output_asm_insn ("ldo 4(%0),%0", &addreg1
);
2669 output_asm_insn (pa_singlemove_string (latehalf
), latehalf
);
2673 output_asm_insn ("ldo -4(%0),%0", &addreg1
);
2674 return pa_singlemove_string (operands
);
2677 /* Now handle register -> register case. */
2678 if (optype0
== REGOP
&& optype1
== REGOP
2679 && REGNO (operands
[0]) == REGNO (operands
[1]) + 1)
2681 output_asm_insn (pa_singlemove_string (latehalf
), latehalf
);
2682 return pa_singlemove_string (operands
);
2685 /* Normal case: do the two words, low-numbered first. */
2687 output_asm_insn (pa_singlemove_string (operands
), operands
);
2689 /* Make any unoffsettable addresses point at high-numbered word. */
2691 output_asm_insn ("ldo 4(%0),%0", &addreg0
);
2693 output_asm_insn ("ldo 4(%0),%0", &addreg1
);
2696 output_asm_insn (pa_singlemove_string (latehalf
), latehalf
);
2698 /* Undo the adds we just did. */
2700 output_asm_insn ("ldo -4(%0),%0", &addreg0
);
2702 output_asm_insn ("ldo -4(%0),%0", &addreg1
);
2708 pa_output_fp_move_double (rtx
*operands
)
2710 if (FP_REG_P (operands
[0]))
2712 if (FP_REG_P (operands
[1])
2713 || operands
[1] == CONST0_RTX (GET_MODE (operands
[0])))
2714 output_asm_insn ("fcpy,dbl %f1,%0", operands
);
2716 output_asm_insn ("fldd%F1 %1,%0", operands
);
2718 else if (FP_REG_P (operands
[1]))
2720 output_asm_insn ("fstd%F0 %1,%0", operands
);
2726 gcc_assert (operands
[1] == CONST0_RTX (GET_MODE (operands
[0])));
2728 /* This is a pain. You have to be prepared to deal with an
2729 arbitrary address here including pre/post increment/decrement.
2731 so avoid this in the MD. */
2732 gcc_assert (GET_CODE (operands
[0]) == REG
);
2734 xoperands
[1] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2735 xoperands
[0] = operands
[0];
2736 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands
);
2741 /* Return a REG that occurs in ADDR with coefficient 1.
2742 ADDR can be effectively incremented by incrementing REG. */
2745 find_addr_reg (rtx addr
)
2747 while (GET_CODE (addr
) == PLUS
)
2749 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2750 addr
= XEXP (addr
, 0);
2751 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2752 addr
= XEXP (addr
, 1);
2753 else if (CONSTANT_P (XEXP (addr
, 0)))
2754 addr
= XEXP (addr
, 1);
2755 else if (CONSTANT_P (XEXP (addr
, 1)))
2756 addr
= XEXP (addr
, 0);
2760 gcc_assert (GET_CODE (addr
) == REG
);
2764 /* Emit code to perform a block move.
2766 OPERANDS[0] is the destination pointer as a REG, clobbered.
2767 OPERANDS[1] is the source pointer as a REG, clobbered.
2768 OPERANDS[2] is a register for temporary storage.
2769 OPERANDS[3] is a register for temporary storage.
2770 OPERANDS[4] is the size as a CONST_INT
2771 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2772 OPERANDS[6] is another temporary register. */
2775 pa_output_block_move (rtx
*operands
, int size_is_constant ATTRIBUTE_UNUSED
)
2777 int align
= INTVAL (operands
[5]);
2778 unsigned long n_bytes
= INTVAL (operands
[4]);
2780 /* We can't move more than a word at a time because the PA
2781 has no longer integer move insns. (Could use fp mem ops?) */
2782 if (align
> (TARGET_64BIT
? 8 : 4))
2783 align
= (TARGET_64BIT
? 8 : 4);
2785 /* Note that we know each loop below will execute at least twice
2786 (else we would have open-coded the copy). */
2790 /* Pre-adjust the loop counter. */
2791 operands
[4] = GEN_INT (n_bytes
- 16);
2792 output_asm_insn ("ldi %4,%2", operands
);
2795 output_asm_insn ("ldd,ma 8(%1),%3", operands
);
2796 output_asm_insn ("ldd,ma 8(%1),%6", operands
);
2797 output_asm_insn ("std,ma %3,8(%0)", operands
);
2798 output_asm_insn ("addib,>= -16,%2,.-12", operands
);
2799 output_asm_insn ("std,ma %6,8(%0)", operands
);
2801 /* Handle the residual. There could be up to 7 bytes of
2802 residual to copy! */
2803 if (n_bytes
% 16 != 0)
2805 operands
[4] = GEN_INT (n_bytes
% 8);
2806 if (n_bytes
% 16 >= 8)
2807 output_asm_insn ("ldd,ma 8(%1),%3", operands
);
2808 if (n_bytes
% 8 != 0)
2809 output_asm_insn ("ldd 0(%1),%6", operands
);
2810 if (n_bytes
% 16 >= 8)
2811 output_asm_insn ("std,ma %3,8(%0)", operands
);
2812 if (n_bytes
% 8 != 0)
2813 output_asm_insn ("stdby,e %6,%4(%0)", operands
);
2818 /* Pre-adjust the loop counter. */
2819 operands
[4] = GEN_INT (n_bytes
- 8);
2820 output_asm_insn ("ldi %4,%2", operands
);
2823 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands
);
2824 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands
);
2825 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands
);
2826 output_asm_insn ("addib,>= -8,%2,.-12", operands
);
2827 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands
);
2829 /* Handle the residual. There could be up to 7 bytes of
2830 residual to copy! */
2831 if (n_bytes
% 8 != 0)
2833 operands
[4] = GEN_INT (n_bytes
% 4);
2834 if (n_bytes
% 8 >= 4)
2835 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands
);
2836 if (n_bytes
% 4 != 0)
2837 output_asm_insn ("ldw 0(%1),%6", operands
);
2838 if (n_bytes
% 8 >= 4)
2839 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands
);
2840 if (n_bytes
% 4 != 0)
2841 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands
);
2846 /* Pre-adjust the loop counter. */
2847 operands
[4] = GEN_INT (n_bytes
- 4);
2848 output_asm_insn ("ldi %4,%2", operands
);
2851 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands
);
2852 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands
);
2853 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands
);
2854 output_asm_insn ("addib,>= -4,%2,.-12", operands
);
2855 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands
);
2857 /* Handle the residual. */
2858 if (n_bytes
% 4 != 0)
2860 if (n_bytes
% 4 >= 2)
2861 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands
);
2862 if (n_bytes
% 2 != 0)
2863 output_asm_insn ("ldb 0(%1),%6", operands
);
2864 if (n_bytes
% 4 >= 2)
2865 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands
);
2866 if (n_bytes
% 2 != 0)
2867 output_asm_insn ("stb %6,0(%0)", operands
);
2872 /* Pre-adjust the loop counter. */
2873 operands
[4] = GEN_INT (n_bytes
- 2);
2874 output_asm_insn ("ldi %4,%2", operands
);
2877 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands
);
2878 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands
);
2879 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands
);
2880 output_asm_insn ("addib,>= -2,%2,.-12", operands
);
2881 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands
);
2883 /* Handle the residual. */
2884 if (n_bytes
% 2 != 0)
2886 output_asm_insn ("ldb 0(%1),%3", operands
);
2887 output_asm_insn ("stb %3,0(%0)", operands
);
2896 /* Count the number of insns necessary to handle this block move.
2898 Basic structure is the same as emit_block_move, except that we
2899 count insns rather than emit them. */
2902 compute_movmem_length (rtx insn
)
2904 rtx pat
= PATTERN (insn
);
2905 unsigned int align
= INTVAL (XEXP (XVECEXP (pat
, 0, 7), 0));
2906 unsigned long n_bytes
= INTVAL (XEXP (XVECEXP (pat
, 0, 6), 0));
2907 unsigned int n_insns
= 0;
2909 /* We can't move more than four bytes at a time because the PA
2910 has no longer integer move insns. (Could use fp mem ops?) */
2911 if (align
> (TARGET_64BIT
? 8 : 4))
2912 align
= (TARGET_64BIT
? 8 : 4);
2914 /* The basic copying loop. */
2918 if (n_bytes
% (2 * align
) != 0)
2920 if ((n_bytes
% (2 * align
)) >= align
)
2923 if ((n_bytes
% align
) != 0)
2927 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2931 /* Emit code to perform a block clear.
2933 OPERANDS[0] is the destination pointer as a REG, clobbered.
2934 OPERANDS[1] is a register for temporary storage.
2935 OPERANDS[2] is the size as a CONST_INT
2936 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2939 pa_output_block_clear (rtx
*operands
, int size_is_constant ATTRIBUTE_UNUSED
)
2941 int align
= INTVAL (operands
[3]);
2942 unsigned long n_bytes
= INTVAL (operands
[2]);
2944 /* We can't clear more than a word at a time because the PA
2945 has no longer integer move insns. */
2946 if (align
> (TARGET_64BIT
? 8 : 4))
2947 align
= (TARGET_64BIT
? 8 : 4);
2949 /* Note that we know each loop below will execute at least twice
2950 (else we would have open-coded the copy). */
2954 /* Pre-adjust the loop counter. */
2955 operands
[2] = GEN_INT (n_bytes
- 16);
2956 output_asm_insn ("ldi %2,%1", operands
);
2959 output_asm_insn ("std,ma %%r0,8(%0)", operands
);
2960 output_asm_insn ("addib,>= -16,%1,.-4", operands
);
2961 output_asm_insn ("std,ma %%r0,8(%0)", operands
);
2963 /* Handle the residual. There could be up to 7 bytes of
2964 residual to copy! */
2965 if (n_bytes
% 16 != 0)
2967 operands
[2] = GEN_INT (n_bytes
% 8);
2968 if (n_bytes
% 16 >= 8)
2969 output_asm_insn ("std,ma %%r0,8(%0)", operands
);
2970 if (n_bytes
% 8 != 0)
2971 output_asm_insn ("stdby,e %%r0,%2(%0)", operands
);
2976 /* Pre-adjust the loop counter. */
2977 operands
[2] = GEN_INT (n_bytes
- 8);
2978 output_asm_insn ("ldi %2,%1", operands
);
2981 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands
);
2982 output_asm_insn ("addib,>= -8,%1,.-4", operands
);
2983 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands
);
2985 /* Handle the residual. There could be up to 7 bytes of
2986 residual to copy! */
2987 if (n_bytes
% 8 != 0)
2989 operands
[2] = GEN_INT (n_bytes
% 4);
2990 if (n_bytes
% 8 >= 4)
2991 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands
);
2992 if (n_bytes
% 4 != 0)
2993 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands
);
2998 /* Pre-adjust the loop counter. */
2999 operands
[2] = GEN_INT (n_bytes
- 4);
3000 output_asm_insn ("ldi %2,%1", operands
);
3003 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands
);
3004 output_asm_insn ("addib,>= -4,%1,.-4", operands
);
3005 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands
);
3007 /* Handle the residual. */
3008 if (n_bytes
% 4 != 0)
3010 if (n_bytes
% 4 >= 2)
3011 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands
);
3012 if (n_bytes
% 2 != 0)
3013 output_asm_insn ("stb %%r0,0(%0)", operands
);
3018 /* Pre-adjust the loop counter. */
3019 operands
[2] = GEN_INT (n_bytes
- 2);
3020 output_asm_insn ("ldi %2,%1", operands
);
3023 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands
);
3024 output_asm_insn ("addib,>= -2,%1,.-4", operands
);
3025 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands
);
3027 /* Handle the residual. */
3028 if (n_bytes
% 2 != 0)
3029 output_asm_insn ("stb %%r0,0(%0)", operands
);
3038 /* Count the number of insns necessary to handle this block move.
3040 Basic structure is the same as emit_block_move, except that we
3041 count insns rather than emit them. */
3044 compute_clrmem_length (rtx insn
)
3046 rtx pat
= PATTERN (insn
);
3047 unsigned int align
= INTVAL (XEXP (XVECEXP (pat
, 0, 4), 0));
3048 unsigned long n_bytes
= INTVAL (XEXP (XVECEXP (pat
, 0, 3), 0));
3049 unsigned int n_insns
= 0;
3051 /* We can't clear more than a word at a time because the PA
3052 has no longer integer move insns. */
3053 if (align
> (TARGET_64BIT
? 8 : 4))
3054 align
= (TARGET_64BIT
? 8 : 4);
3056 /* The basic loop. */
3060 if (n_bytes
% (2 * align
) != 0)
3062 if ((n_bytes
% (2 * align
)) >= align
)
3065 if ((n_bytes
% align
) != 0)
3069 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
3075 pa_output_and (rtx
*operands
)
3077 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) != 0)
3079 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
3080 int ls0
, ls1
, ms0
, p
, len
;
3082 for (ls0
= 0; ls0
< 32; ls0
++)
3083 if ((mask
& (1 << ls0
)) == 0)
3086 for (ls1
= ls0
; ls1
< 32; ls1
++)
3087 if ((mask
& (1 << ls1
)) != 0)
3090 for (ms0
= ls1
; ms0
< 32; ms0
++)
3091 if ((mask
& (1 << ms0
)) == 0)
3094 gcc_assert (ms0
== 32);
3102 operands
[2] = GEN_INT (len
);
3103 return "{extru|extrw,u} %1,31,%2,%0";
3107 /* We could use this `depi' for the case above as well, but `depi'
3108 requires one more register file access than an `extru'. */
3113 operands
[2] = GEN_INT (p
);
3114 operands
[3] = GEN_INT (len
);
3115 return "{depi|depwi} 0,%2,%3,%0";
3119 return "and %1,%2,%0";
3122 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3123 storing the result in operands[0]. */
3125 pa_output_64bit_and (rtx
*operands
)
3127 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) != 0)
3129 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
3130 int ls0
, ls1
, ms0
, p
, len
;
3132 for (ls0
= 0; ls0
< HOST_BITS_PER_WIDE_INT
; ls0
++)
3133 if ((mask
& ((unsigned HOST_WIDE_INT
) 1 << ls0
)) == 0)
3136 for (ls1
= ls0
; ls1
< HOST_BITS_PER_WIDE_INT
; ls1
++)
3137 if ((mask
& ((unsigned HOST_WIDE_INT
) 1 << ls1
)) != 0)
3140 for (ms0
= ls1
; ms0
< HOST_BITS_PER_WIDE_INT
; ms0
++)
3141 if ((mask
& ((unsigned HOST_WIDE_INT
) 1 << ms0
)) == 0)
3144 gcc_assert (ms0
== HOST_BITS_PER_WIDE_INT
);
3146 if (ls1
== HOST_BITS_PER_WIDE_INT
)
3152 operands
[2] = GEN_INT (len
);
3153 return "extrd,u %1,63,%2,%0";
3157 /* We could use this `depi' for the case above as well, but `depi'
3158 requires one more register file access than an `extru'. */
3163 operands
[2] = GEN_INT (p
);
3164 operands
[3] = GEN_INT (len
);
3165 return "depdi 0,%2,%3,%0";
3169 return "and %1,%2,%0";
3173 pa_output_ior (rtx
*operands
)
3175 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
3176 int bs0
, bs1
, p
, len
;
3178 if (INTVAL (operands
[2]) == 0)
3179 return "copy %1,%0";
3181 for (bs0
= 0; bs0
< 32; bs0
++)
3182 if ((mask
& (1 << bs0
)) != 0)
3185 for (bs1
= bs0
; bs1
< 32; bs1
++)
3186 if ((mask
& (1 << bs1
)) == 0)
3189 gcc_assert (bs1
== 32 || ((unsigned HOST_WIDE_INT
) 1 << bs1
) > mask
);
3194 operands
[2] = GEN_INT (p
);
3195 operands
[3] = GEN_INT (len
);
3196 return "{depi|depwi} -1,%2,%3,%0";
3199 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3200 storing the result in operands[0]. */
3202 pa_output_64bit_ior (rtx
*operands
)
3204 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
3205 int bs0
, bs1
, p
, len
;
3207 if (INTVAL (operands
[2]) == 0)
3208 return "copy %1,%0";
3210 for (bs0
= 0; bs0
< HOST_BITS_PER_WIDE_INT
; bs0
++)
3211 if ((mask
& ((unsigned HOST_WIDE_INT
) 1 << bs0
)) != 0)
3214 for (bs1
= bs0
; bs1
< HOST_BITS_PER_WIDE_INT
; bs1
++)
3215 if ((mask
& ((unsigned HOST_WIDE_INT
) 1 << bs1
)) == 0)
3218 gcc_assert (bs1
== HOST_BITS_PER_WIDE_INT
3219 || ((unsigned HOST_WIDE_INT
) 1 << bs1
) > mask
);
3224 operands
[2] = GEN_INT (p
);
3225 operands
[3] = GEN_INT (len
);
3226 return "depdi -1,%2,%3,%0";
3229 /* Target hook for assembling integer objects. This code handles
3230 aligned SI and DI integers specially since function references
3231 must be preceded by P%. */
3234 pa_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
3236 if (size
== UNITS_PER_WORD
3238 && function_label_operand (x
, VOIDmode
))
3240 fputs (size
== 8? "\t.dword\t" : "\t.word\t", asm_out_file
);
3242 /* We don't want an OPD when generating fast indirect calls. */
3243 if (!TARGET_FAST_INDIRECT_CALLS
)
3244 fputs ("P%", asm_out_file
);
3246 output_addr_const (asm_out_file
, x
);
3247 fputc ('\n', asm_out_file
);
3250 return default_assemble_integer (x
, size
, aligned_p
);
3253 /* Output an ascii string. */
3255 pa_output_ascii (FILE *file
, const char *p
, int size
)
3259 unsigned char partial_output
[16]; /* Max space 4 chars can occupy. */
3261 /* The HP assembler can only take strings of 256 characters at one
3262 time. This is a limitation on input line length, *not* the
3263 length of the string. Sigh. Even worse, it seems that the
3264 restriction is in number of input characters (see \xnn &
3265 \whatever). So we have to do this very carefully. */
3267 fputs ("\t.STRING \"", file
);
3270 for (i
= 0; i
< size
; i
+= 4)
3274 for (io
= 0, co
= 0; io
< MIN (4, size
- i
); io
++)
3276 register unsigned int c
= (unsigned char) p
[i
+ io
];
3278 if (c
== '\"' || c
== '\\')
3279 partial_output
[co
++] = '\\';
3280 if (c
>= ' ' && c
< 0177)
3281 partial_output
[co
++] = c
;
3285 partial_output
[co
++] = '\\';
3286 partial_output
[co
++] = 'x';
3287 hexd
= c
/ 16 - 0 + '0';
3289 hexd
-= '9' - 'a' + 1;
3290 partial_output
[co
++] = hexd
;
3291 hexd
= c
% 16 - 0 + '0';
3293 hexd
-= '9' - 'a' + 1;
3294 partial_output
[co
++] = hexd
;
3297 if (chars_output
+ co
> 243)
3299 fputs ("\"\n\t.STRING \"", file
);
3302 fwrite (partial_output
, 1, (size_t) co
, file
);
3306 fputs ("\"\n", file
);
3309 /* Try to rewrite floating point comparisons & branches to avoid
3310 useless add,tr insns.
3312 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3313 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3314 first attempt to remove useless add,tr insns. It is zero
3315 for the second pass as reorg sometimes leaves bogus REG_DEAD
3318 When CHECK_NOTES is zero we can only eliminate add,tr insns
3319 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3322 remove_useless_addtr_insns (int check_notes
)
3325 static int pass
= 0;
3327 /* This is fairly cheap, so always run it when optimizing. */
3331 int fbranch_count
= 0;
3333 /* Walk all the insns in this function looking for fcmp & fbranch
3334 instructions. Keep track of how many of each we find. */
3335 for (insn
= get_insns (); insn
; insn
= next_insn (insn
))
3339 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3340 if (GET_CODE (insn
) != INSN
&& GET_CODE (insn
) != JUMP_INSN
)
3343 tmp
= PATTERN (insn
);
3345 /* It must be a set. */
3346 if (GET_CODE (tmp
) != SET
)
3349 /* If the destination is CCFP, then we've found an fcmp insn. */
3350 tmp
= SET_DEST (tmp
);
3351 if (GET_CODE (tmp
) == REG
&& REGNO (tmp
) == 0)
3357 tmp
= PATTERN (insn
);
3358 /* If this is an fbranch instruction, bump the fbranch counter. */
3359 if (GET_CODE (tmp
) == SET
3360 && SET_DEST (tmp
) == pc_rtx
3361 && GET_CODE (SET_SRC (tmp
)) == IF_THEN_ELSE
3362 && GET_CODE (XEXP (SET_SRC (tmp
), 0)) == NE
3363 && GET_CODE (XEXP (XEXP (SET_SRC (tmp
), 0), 0)) == REG
3364 && REGNO (XEXP (XEXP (SET_SRC (tmp
), 0), 0)) == 0)
3372 /* Find all floating point compare + branch insns. If possible,
3373 reverse the comparison & the branch to avoid add,tr insns. */
3374 for (insn
= get_insns (); insn
; insn
= next_insn (insn
))
3378 /* Ignore anything that isn't an INSN. */
3379 if (GET_CODE (insn
) != INSN
)
3382 tmp
= PATTERN (insn
);
3384 /* It must be a set. */
3385 if (GET_CODE (tmp
) != SET
)
3388 /* The destination must be CCFP, which is register zero. */
3389 tmp
= SET_DEST (tmp
);
3390 if (GET_CODE (tmp
) != REG
|| REGNO (tmp
) != 0)
3393 /* INSN should be a set of CCFP.
3395 See if the result of this insn is used in a reversed FP
3396 conditional branch. If so, reverse our condition and
3397 the branch. Doing so avoids useless add,tr insns. */
3398 next
= next_insn (insn
);
3401 /* Jumps, calls and labels stop our search. */
3402 if (GET_CODE (next
) == JUMP_INSN
3403 || GET_CODE (next
) == CALL_INSN
3404 || GET_CODE (next
) == CODE_LABEL
)
3407 /* As does another fcmp insn. */
3408 if (GET_CODE (next
) == INSN
3409 && GET_CODE (PATTERN (next
)) == SET
3410 && GET_CODE (SET_DEST (PATTERN (next
))) == REG
3411 && REGNO (SET_DEST (PATTERN (next
))) == 0)
3414 next
= next_insn (next
);
3417 /* Is NEXT_INSN a branch? */
3419 && GET_CODE (next
) == JUMP_INSN
)
3421 rtx pattern
= PATTERN (next
);
3423 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3424 and CCFP dies, then reverse our conditional and the branch
3425 to avoid the add,tr. */
3426 if (GET_CODE (pattern
) == SET
3427 && SET_DEST (pattern
) == pc_rtx
3428 && GET_CODE (SET_SRC (pattern
)) == IF_THEN_ELSE
3429 && GET_CODE (XEXP (SET_SRC (pattern
), 0)) == NE
3430 && GET_CODE (XEXP (XEXP (SET_SRC (pattern
), 0), 0)) == REG
3431 && REGNO (XEXP (XEXP (SET_SRC (pattern
), 0), 0)) == 0
3432 && GET_CODE (XEXP (SET_SRC (pattern
), 1)) == PC
3433 && (fcmp_count
== fbranch_count
3435 && find_regno_note (next
, REG_DEAD
, 0))))
3437 /* Reverse the branch. */
3438 tmp
= XEXP (SET_SRC (pattern
), 1);
3439 XEXP (SET_SRC (pattern
), 1) = XEXP (SET_SRC (pattern
), 2);
3440 XEXP (SET_SRC (pattern
), 2) = tmp
;
3441 INSN_CODE (next
) = -1;
3443 /* Reverse our condition. */
3444 tmp
= PATTERN (insn
);
3445 PUT_CODE (XEXP (tmp
, 1),
3446 (reverse_condition_maybe_unordered
3447 (GET_CODE (XEXP (tmp
, 1)))));
3457 /* You may have trouble believing this, but this is the 32 bit HP-PA
3462 Variable arguments (optional; any number may be allocated)
3464 SP-(4*(N+9)) arg word N
3469 Fixed arguments (must be allocated; may remain unused)
3478 SP-32 External Data Pointer (DP)
3480 SP-24 External/stub RP (RP')
3484 SP-8 Calling Stub RP (RP'')
3489 SP-0 Stack Pointer (points to next available address)
3493 /* This function saves registers as follows. Registers marked with ' are
3494 this function's registers (as opposed to the previous function's).
3495 If a frame_pointer isn't needed, r4 is saved as a general register;
3496 the space for the frame pointer is still allocated, though, to keep
3502 SP (FP') Previous FP
3503 SP + 4 Alignment filler (sigh)
3504 SP + 8 Space for locals reserved here.
3508 SP + n All call saved register used.
3512 SP + o All call saved fp registers used.
3516 SP + p (SP') points to next available address.
3520 /* Global variables set by output_function_prologue(). */
3521 /* Size of frame. Need to know this to emit return insns from
3523 static HOST_WIDE_INT actual_fsize
, local_fsize
;
3524 static int save_fregs
;
3526 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3527 Handle case where DISP > 8k by using the add_high_const patterns.
3529 Note in DISP > 8k case, we will leave the high part of the address
3530 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3533 store_reg (int reg
, HOST_WIDE_INT disp
, int base
)
3535 rtx insn
, dest
, src
, basereg
;
3537 src
= gen_rtx_REG (word_mode
, reg
);
3538 basereg
= gen_rtx_REG (Pmode
, base
);
3539 if (VAL_14_BITS_P (disp
))
3541 dest
= gen_rtx_MEM (word_mode
, plus_constant (Pmode
, basereg
, disp
));
3542 insn
= emit_move_insn (dest
, src
);
3544 else if (TARGET_64BIT
&& !VAL_32_BITS_P (disp
))
3546 rtx delta
= GEN_INT (disp
);
3547 rtx tmpreg
= gen_rtx_REG (Pmode
, 1);
3549 emit_move_insn (tmpreg
, delta
);
3550 insn
= emit_move_insn (tmpreg
, gen_rtx_PLUS (Pmode
, tmpreg
, basereg
));
3553 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
3554 gen_rtx_SET (VOIDmode
, tmpreg
,
3555 gen_rtx_PLUS (Pmode
, basereg
, delta
)));
3556 RTX_FRAME_RELATED_P (insn
) = 1;
3558 dest
= gen_rtx_MEM (word_mode
, tmpreg
);
3559 insn
= emit_move_insn (dest
, src
);
3563 rtx delta
= GEN_INT (disp
);
3564 rtx high
= gen_rtx_PLUS (Pmode
, basereg
, gen_rtx_HIGH (Pmode
, delta
));
3565 rtx tmpreg
= gen_rtx_REG (Pmode
, 1);
3567 emit_move_insn (tmpreg
, high
);
3568 dest
= gen_rtx_MEM (word_mode
, gen_rtx_LO_SUM (Pmode
, tmpreg
, delta
));
3569 insn
= emit_move_insn (dest
, src
);
3571 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
3572 gen_rtx_SET (VOIDmode
,
3573 gen_rtx_MEM (word_mode
,
3574 gen_rtx_PLUS (word_mode
,
3581 RTX_FRAME_RELATED_P (insn
) = 1;
3584 /* Emit RTL to store REG at the memory location specified by BASE and then
3585 add MOD to BASE. MOD must be <= 8k. */
3588 store_reg_modify (int base
, int reg
, HOST_WIDE_INT mod
)
3590 rtx insn
, basereg
, srcreg
, delta
;
3592 gcc_assert (VAL_14_BITS_P (mod
));
3594 basereg
= gen_rtx_REG (Pmode
, base
);
3595 srcreg
= gen_rtx_REG (word_mode
, reg
);
3596 delta
= GEN_INT (mod
);
3598 insn
= emit_insn (gen_post_store (basereg
, srcreg
, delta
));
3601 RTX_FRAME_RELATED_P (insn
) = 1;
3603 /* RTX_FRAME_RELATED_P must be set on each frame related set
3604 in a parallel with more than one element. */
3605 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn
), 0, 0)) = 1;
3606 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn
), 0, 1)) = 1;
3610 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3611 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3612 whether to add a frame note or not.
3614 In the DISP > 8k case, we leave the high part of the address in %r1.
3615 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3618 set_reg_plus_d (int reg
, int base
, HOST_WIDE_INT disp
, int note
)
3622 if (VAL_14_BITS_P (disp
))
3624 insn
= emit_move_insn (gen_rtx_REG (Pmode
, reg
),
3625 plus_constant (Pmode
,
3626 gen_rtx_REG (Pmode
, base
), disp
));
3628 else if (TARGET_64BIT
&& !VAL_32_BITS_P (disp
))
3630 rtx basereg
= gen_rtx_REG (Pmode
, base
);
3631 rtx delta
= GEN_INT (disp
);
3632 rtx tmpreg
= gen_rtx_REG (Pmode
, 1);
3634 emit_move_insn (tmpreg
, delta
);
3635 insn
= emit_move_insn (gen_rtx_REG (Pmode
, reg
),
3636 gen_rtx_PLUS (Pmode
, tmpreg
, basereg
));
3638 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
3639 gen_rtx_SET (VOIDmode
, tmpreg
,
3640 gen_rtx_PLUS (Pmode
, basereg
, delta
)));
3644 rtx basereg
= gen_rtx_REG (Pmode
, base
);
3645 rtx delta
= GEN_INT (disp
);
3646 rtx tmpreg
= gen_rtx_REG (Pmode
, 1);
3648 emit_move_insn (tmpreg
,
3649 gen_rtx_PLUS (Pmode
, basereg
,
3650 gen_rtx_HIGH (Pmode
, delta
)));
3651 insn
= emit_move_insn (gen_rtx_REG (Pmode
, reg
),
3652 gen_rtx_LO_SUM (Pmode
, tmpreg
, delta
));
3655 if (DO_FRAME_NOTES
&& note
)
3656 RTX_FRAME_RELATED_P (insn
) = 1;
3660 pa_compute_frame_size (HOST_WIDE_INT size
, int *fregs_live
)
3665 /* The code in pa_expand_prologue and pa_expand_epilogue must
3666 be consistent with the rounding and size calculation done here.
3667 Change them at the same time. */
3669 /* We do our own stack alignment. First, round the size of the
3670 stack locals up to a word boundary. */
3671 size
= (size
+ UNITS_PER_WORD
- 1) & ~(UNITS_PER_WORD
- 1);
3673 /* Space for previous frame pointer + filler. If any frame is
3674 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3675 waste some space here for the sake of HP compatibility. The
3676 first slot is only used when the frame pointer is needed. */
3677 if (size
|| frame_pointer_needed
)
3678 size
+= STARTING_FRAME_OFFSET
;
3680 /* If the current function calls __builtin_eh_return, then we need
3681 to allocate stack space for registers that will hold data for
3682 the exception handler. */
3683 if (DO_FRAME_NOTES
&& crtl
->calls_eh_return
)
3687 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
3689 size
+= i
* UNITS_PER_WORD
;
3692 /* Account for space used by the callee general register saves. */
3693 for (i
= 18, j
= frame_pointer_needed
? 4 : 3; i
>= j
; i
--)
3694 if (df_regs_ever_live_p (i
))
3695 size
+= UNITS_PER_WORD
;
3697 /* Account for space used by the callee floating point register saves. */
3698 for (i
= FP_SAVED_REG_LAST
; i
>= FP_SAVED_REG_FIRST
; i
-= FP_REG_STEP
)
3699 if (df_regs_ever_live_p (i
)
3700 || (!TARGET_64BIT
&& df_regs_ever_live_p (i
+ 1)))
3704 /* We always save both halves of the FP register, so always
3705 increment the frame size by 8 bytes. */
3709 /* If any of the floating registers are saved, account for the
3710 alignment needed for the floating point register save block. */
3713 size
= (size
+ 7) & ~7;
3718 /* The various ABIs include space for the outgoing parameters in the
3719 size of the current function's stack frame. We don't need to align
3720 for the outgoing arguments as their alignment is set by the final
3721 rounding for the frame as a whole. */
3722 size
+= crtl
->outgoing_args_size
;
3724 /* Allocate space for the fixed frame marker. This space must be
3725 allocated for any function that makes calls or allocates
3727 if (!crtl
->is_leaf
|| size
)
3728 size
+= TARGET_64BIT
? 48 : 32;
3730 /* Finally, round to the preferred stack boundary. */
3731 return ((size
+ PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
3732 & ~(PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
3735 /* Generate the assembly code for function entry. FILE is a stdio
3736 stream to output the code to. SIZE is an int: how many units of
3737 temporary storage to allocate.
3739 Refer to the array `regs_ever_live' to determine which registers to
3740 save; `regs_ever_live[I]' is nonzero if register number I is ever
3741 used in the function. This function is responsible for knowing
3742 which registers should not be saved even if used. */
3744 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3745 of memory. If any fpu reg is used in the function, we allocate
3746 such a block here, at the bottom of the frame, just in case it's needed.
3748 If this function is a leaf procedure, then we may choose not
3749 to do a "save" insn. The decision about whether or not
3750 to do this is made in regclass.c. */
3753 pa_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
3755 /* The function's label and associated .PROC must never be
3756 separated and must be output *after* any profiling declarations
3757 to avoid changing spaces/subspaces within a procedure. */
3758 ASM_OUTPUT_LABEL (file
, XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0));
3759 fputs ("\t.PROC\n", file
);
3761 /* pa_expand_prologue does the dirty work now. We just need
3762 to output the assembler directives which denote the start
3764 fprintf (file
, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC
, actual_fsize
);
3766 fputs (",NO_CALLS", file
);
3768 fputs (",CALLS", file
);
3770 fputs (",SAVE_RP", file
);
3772 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3773 at the beginning of the frame and that it is used as the frame
3774 pointer for the frame. We do this because our current frame
3775 layout doesn't conform to that specified in the HP runtime
3776 documentation and we need a way to indicate to programs such as
3777 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3778 isn't used by HP compilers but is supported by the assembler.
3779 However, SAVE_SP is supposed to indicate that the previous stack
3780 pointer has been saved in the frame marker. */
3781 if (frame_pointer_needed
)
3782 fputs (",SAVE_SP", file
);
3784 /* Pass on information about the number of callee register saves
3785 performed in the prologue.
3787 The compiler is supposed to pass the highest register number
3788 saved, the assembler then has to adjust that number before
3789 entering it into the unwind descriptor (to account for any
3790 caller saved registers with lower register numbers than the
3791 first callee saved register). */
3793 fprintf (file
, ",ENTRY_GR=%d", gr_saved
+ 2);
3796 fprintf (file
, ",ENTRY_FR=%d", fr_saved
+ 11);
3798 fputs ("\n\t.ENTRY\n", file
);
3800 remove_useless_addtr_insns (0);
3804 pa_expand_prologue (void)
3806 int merge_sp_adjust_with_store
= 0;
3807 HOST_WIDE_INT size
= get_frame_size ();
3808 HOST_WIDE_INT offset
;
3816 /* Compute total size for frame pointer, filler, locals and rounding to
3817 the next word boundary. Similar code appears in pa_compute_frame_size
3818 and must be changed in tandem with this code. */
3819 local_fsize
= (size
+ UNITS_PER_WORD
- 1) & ~(UNITS_PER_WORD
- 1);
3820 if (local_fsize
|| frame_pointer_needed
)
3821 local_fsize
+= STARTING_FRAME_OFFSET
;
3823 actual_fsize
= pa_compute_frame_size (size
, &save_fregs
);
3824 if (flag_stack_usage_info
)
3825 current_function_static_stack_size
= actual_fsize
;
3827 /* Compute a few things we will use often. */
3828 tmpreg
= gen_rtx_REG (word_mode
, 1);
3830 /* Save RP first. The calling conventions manual states RP will
3831 always be stored into the caller's frame at sp - 20 or sp - 16
3832 depending on which ABI is in use. */
3833 if (df_regs_ever_live_p (2) || crtl
->calls_eh_return
)
3835 store_reg (2, TARGET_64BIT
? -16 : -20, STACK_POINTER_REGNUM
);
3841 /* Allocate the local frame and set up the frame pointer if needed. */
3842 if (actual_fsize
!= 0)
3844 if (frame_pointer_needed
)
3846 /* Copy the old frame pointer temporarily into %r1. Set up the
3847 new stack pointer, then store away the saved old frame pointer
3848 into the stack at sp and at the same time update the stack
3849 pointer by actual_fsize bytes. Two versions, first
3850 handles small (<8k) frames. The second handles large (>=8k)
3852 insn
= emit_move_insn (tmpreg
, hard_frame_pointer_rtx
);
3854 RTX_FRAME_RELATED_P (insn
) = 1;
3856 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
3858 RTX_FRAME_RELATED_P (insn
) = 1;
3860 if (VAL_14_BITS_P (actual_fsize
))
3861 store_reg_modify (STACK_POINTER_REGNUM
, 1, actual_fsize
);
3864 /* It is incorrect to store the saved frame pointer at *sp,
3865 then increment sp (writes beyond the current stack boundary).
3867 So instead use stwm to store at *sp and post-increment the
3868 stack pointer as an atomic operation. Then increment sp to
3869 finish allocating the new frame. */
3870 HOST_WIDE_INT adjust1
= 8192 - 64;
3871 HOST_WIDE_INT adjust2
= actual_fsize
- adjust1
;
3873 store_reg_modify (STACK_POINTER_REGNUM
, 1, adjust1
);
3874 set_reg_plus_d (STACK_POINTER_REGNUM
, STACK_POINTER_REGNUM
,
3878 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3879 we need to store the previous stack pointer (frame pointer)
3880 into the frame marker on targets that use the HP unwind
3881 library. This allows the HP unwind library to be used to
3882 unwind GCC frames. However, we are not fully compatible
3883 with the HP library because our frame layout differs from
3884 that specified in the HP runtime specification.
3886 We don't want a frame note on this instruction as the frame
3887 marker moves during dynamic stack allocation.
3889 This instruction also serves as a blockage to prevent
3890 register spills from being scheduled before the stack
3891 pointer is raised. This is necessary as we store
3892 registers using the frame pointer as a base register,
3893 and the frame pointer is set before sp is raised. */
3894 if (TARGET_HPUX_UNWIND_LIBRARY
)
3896 rtx addr
= gen_rtx_PLUS (word_mode
, stack_pointer_rtx
,
3897 GEN_INT (TARGET_64BIT
? -8 : -4));
3899 emit_move_insn (gen_rtx_MEM (word_mode
, addr
),
3900 hard_frame_pointer_rtx
);
3903 emit_insn (gen_blockage ());
3905 /* no frame pointer needed. */
3908 /* In some cases we can perform the first callee register save
3909 and allocating the stack frame at the same time. If so, just
3910 make a note of it and defer allocating the frame until saving
3911 the callee registers. */
3912 if (VAL_14_BITS_P (actual_fsize
) && local_fsize
== 0)
3913 merge_sp_adjust_with_store
= 1;
3914 /* Can not optimize. Adjust the stack frame by actual_fsize
3917 set_reg_plus_d (STACK_POINTER_REGNUM
, STACK_POINTER_REGNUM
,
3922 /* Normal register save.
3924 Do not save the frame pointer in the frame_pointer_needed case. It
3925 was done earlier. */
3926 if (frame_pointer_needed
)
3928 offset
= local_fsize
;
3930 /* Saving the EH return data registers in the frame is the simplest
3931 way to get the frame unwind information emitted. We put them
3932 just before the general registers. */
3933 if (DO_FRAME_NOTES
&& crtl
->calls_eh_return
)
3935 unsigned int i
, regno
;
3939 regno
= EH_RETURN_DATA_REGNO (i
);
3940 if (regno
== INVALID_REGNUM
)
3943 store_reg (regno
, offset
, HARD_FRAME_POINTER_REGNUM
);
3944 offset
+= UNITS_PER_WORD
;
3948 for (i
= 18; i
>= 4; i
--)
3949 if (df_regs_ever_live_p (i
) && ! call_used_regs
[i
])
3951 store_reg (i
, offset
, HARD_FRAME_POINTER_REGNUM
);
3952 offset
+= UNITS_PER_WORD
;
3955 /* Account for %r3 which is saved in a special place. */
3958 /* No frame pointer needed. */
3961 offset
= local_fsize
- actual_fsize
;
3963 /* Saving the EH return data registers in the frame is the simplest
3964 way to get the frame unwind information emitted. */
3965 if (DO_FRAME_NOTES
&& crtl
->calls_eh_return
)
3967 unsigned int i
, regno
;
3971 regno
= EH_RETURN_DATA_REGNO (i
);
3972 if (regno
== INVALID_REGNUM
)
3975 /* If merge_sp_adjust_with_store is nonzero, then we can
3976 optimize the first save. */
3977 if (merge_sp_adjust_with_store
)
3979 store_reg_modify (STACK_POINTER_REGNUM
, regno
, -offset
);
3980 merge_sp_adjust_with_store
= 0;
3983 store_reg (regno
, offset
, STACK_POINTER_REGNUM
);
3984 offset
+= UNITS_PER_WORD
;
3988 for (i
= 18; i
>= 3; i
--)
3989 if (df_regs_ever_live_p (i
) && ! call_used_regs
[i
])
3991 /* If merge_sp_adjust_with_store is nonzero, then we can
3992 optimize the first GR save. */
3993 if (merge_sp_adjust_with_store
)
3995 store_reg_modify (STACK_POINTER_REGNUM
, i
, -offset
);
3996 merge_sp_adjust_with_store
= 0;
3999 store_reg (i
, offset
, STACK_POINTER_REGNUM
);
4000 offset
+= UNITS_PER_WORD
;
4004 /* If we wanted to merge the SP adjustment with a GR save, but we never
4005 did any GR saves, then just emit the adjustment here. */
4006 if (merge_sp_adjust_with_store
)
4007 set_reg_plus_d (STACK_POINTER_REGNUM
, STACK_POINTER_REGNUM
,
4011 /* The hppa calling conventions say that %r19, the pic offset
4012 register, is saved at sp - 32 (in this function's frame)
4013 when generating PIC code. FIXME: What is the correct thing
4014 to do for functions which make no calls and allocate no
4015 frame? Do we need to allocate a frame, or can we just omit
4016 the save? For now we'll just omit the save.
4018 We don't want a note on this insn as the frame marker can
4019 move if there is a dynamic stack allocation. */
4020 if (flag_pic
&& actual_fsize
!= 0 && !TARGET_64BIT
)
4022 rtx addr
= gen_rtx_PLUS (word_mode
, stack_pointer_rtx
, GEN_INT (-32));
4024 emit_move_insn (gen_rtx_MEM (word_mode
, addr
), pic_offset_table_rtx
);
4028 /* Align pointer properly (doubleword boundary). */
4029 offset
= (offset
+ 7) & ~7;
4031 /* Floating point register store. */
4036 /* First get the frame or stack pointer to the start of the FP register
4038 if (frame_pointer_needed
)
4040 set_reg_plus_d (1, HARD_FRAME_POINTER_REGNUM
, offset
, 0);
4041 base
= hard_frame_pointer_rtx
;
4045 set_reg_plus_d (1, STACK_POINTER_REGNUM
, offset
, 0);
4046 base
= stack_pointer_rtx
;
4049 /* Now actually save the FP registers. */
4050 for (i
= FP_SAVED_REG_LAST
; i
>= FP_SAVED_REG_FIRST
; i
-= FP_REG_STEP
)
4052 if (df_regs_ever_live_p (i
)
4053 || (! TARGET_64BIT
&& df_regs_ever_live_p (i
+ 1)))
4055 rtx addr
, insn
, reg
;
4056 addr
= gen_rtx_MEM (DFmode
,
4057 gen_rtx_POST_INC (word_mode
, tmpreg
));
4058 reg
= gen_rtx_REG (DFmode
, i
);
4059 insn
= emit_move_insn (addr
, reg
);
4062 RTX_FRAME_RELATED_P (insn
) = 1;
4065 rtx mem
= gen_rtx_MEM (DFmode
,
4066 plus_constant (Pmode
, base
,
4068 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4069 gen_rtx_SET (VOIDmode
, mem
, reg
));
4073 rtx meml
= gen_rtx_MEM (SFmode
,
4074 plus_constant (Pmode
, base
,
4076 rtx memr
= gen_rtx_MEM (SFmode
,
4077 plus_constant (Pmode
, base
,
4079 rtx regl
= gen_rtx_REG (SFmode
, i
);
4080 rtx regr
= gen_rtx_REG (SFmode
, i
+ 1);
4081 rtx setl
= gen_rtx_SET (VOIDmode
, meml
, regl
);
4082 rtx setr
= gen_rtx_SET (VOIDmode
, memr
, regr
);
4085 RTX_FRAME_RELATED_P (setl
) = 1;
4086 RTX_FRAME_RELATED_P (setr
) = 1;
4087 vec
= gen_rtvec (2, setl
, setr
);
4088 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4089 gen_rtx_SEQUENCE (VOIDmode
, vec
));
4092 offset
+= GET_MODE_SIZE (DFmode
);
4099 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
4100 Handle case where DISP > 8k by using the add_high_const patterns. */
4103 load_reg (int reg
, HOST_WIDE_INT disp
, int base
)
4105 rtx dest
= gen_rtx_REG (word_mode
, reg
);
4106 rtx basereg
= gen_rtx_REG (Pmode
, base
);
4109 if (VAL_14_BITS_P (disp
))
4110 src
= gen_rtx_MEM (word_mode
, plus_constant (Pmode
, basereg
, disp
));
4111 else if (TARGET_64BIT
&& !VAL_32_BITS_P (disp
))
4113 rtx delta
= GEN_INT (disp
);
4114 rtx tmpreg
= gen_rtx_REG (Pmode
, 1);
4116 emit_move_insn (tmpreg
, delta
);
4117 if (TARGET_DISABLE_INDEXING
)
4119 emit_move_insn (tmpreg
, gen_rtx_PLUS (Pmode
, tmpreg
, basereg
));
4120 src
= gen_rtx_MEM (word_mode
, tmpreg
);
4123 src
= gen_rtx_MEM (word_mode
, gen_rtx_PLUS (Pmode
, tmpreg
, basereg
));
4127 rtx delta
= GEN_INT (disp
);
4128 rtx high
= gen_rtx_PLUS (Pmode
, basereg
, gen_rtx_HIGH (Pmode
, delta
));
4129 rtx tmpreg
= gen_rtx_REG (Pmode
, 1);
4131 emit_move_insn (tmpreg
, high
);
4132 src
= gen_rtx_MEM (word_mode
, gen_rtx_LO_SUM (Pmode
, tmpreg
, delta
));
4135 emit_move_insn (dest
, src
);
4138 /* Update the total code bytes output to the text section. */
4141 update_total_code_bytes (unsigned int nbytes
)
4143 if ((TARGET_PORTABLE_RUNTIME
|| !TARGET_GAS
|| !TARGET_SOM
)
4144 && !IN_NAMED_SECTION_P (cfun
->decl
))
4146 unsigned int old_total
= total_code_bytes
;
4148 total_code_bytes
+= nbytes
;
4150 /* Be prepared to handle overflows. */
4151 if (old_total
> total_code_bytes
)
4152 total_code_bytes
= UINT_MAX
;
4156 /* This function generates the assembly code for function exit.
4157 Args are as for output_function_prologue ().
4159 The function epilogue should not depend on the current stack
4160 pointer! It should use the frame pointer only. This is mandatory
4161 because of alloca; we also take advantage of it to omit stack
4162 adjustments before returning. */
4165 pa_output_function_epilogue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
4167 rtx insn
= get_last_insn ();
4170 /* pa_expand_epilogue does the dirty work now. We just need
4171 to output the assembler directives which denote the end
4174 To make debuggers happy, emit a nop if the epilogue was completely
4175 eliminated due to a volatile call as the last insn in the
4176 current function. That way the return address (in %r2) will
4177 always point to a valid instruction in the current function. */
4179 /* Get the last real insn. */
4180 if (GET_CODE (insn
) == NOTE
)
4181 insn
= prev_real_insn (insn
);
4183 /* If it is a sequence, then look inside. */
4184 if (insn
&& GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
)
4185 insn
= XVECEXP (PATTERN (insn
), 0, 0);
4187 /* If insn is a CALL_INSN, then it must be a call to a volatile
4188 function (otherwise there would be epilogue insns). */
4189 if (insn
&& GET_CODE (insn
) == CALL_INSN
)
4191 fputs ("\tnop\n", file
);
4197 fputs ("\t.EXIT\n\t.PROCEND\n", file
);
4199 if (TARGET_SOM
&& TARGET_GAS
)
4201 /* We are done with this subspace except possibly for some additional
4202 debug information. Forget that we are in this subspace to ensure
4203 that the next function is output in its own subspace. */
4205 cfun
->machine
->in_nsubspa
= 2;
4208 /* Thunks do their own insn accounting. */
4212 if (INSN_ADDRESSES_SET_P ())
4214 last_address
= extra_nop
? 4 : 0;
4215 insn
= get_last_nonnote_insn ();
4218 last_address
+= INSN_ADDRESSES (INSN_UID (insn
));
4220 last_address
+= insn_default_length (insn
);
4222 last_address
= ((last_address
+ FUNCTION_BOUNDARY
/ BITS_PER_UNIT
- 1)
4223 & ~(FUNCTION_BOUNDARY
/ BITS_PER_UNIT
- 1));
4226 last_address
= UINT_MAX
;
4228 /* Finally, update the total number of code bytes output so far. */
4229 update_total_code_bytes (last_address
);
4233 pa_expand_epilogue (void)
4236 HOST_WIDE_INT offset
;
4237 HOST_WIDE_INT ret_off
= 0;
4239 int merge_sp_adjust_with_load
= 0;
4241 /* We will use this often. */
4242 tmpreg
= gen_rtx_REG (word_mode
, 1);
4244 /* Try to restore RP early to avoid load/use interlocks when
4245 RP gets used in the return (bv) instruction. This appears to still
4246 be necessary even when we schedule the prologue and epilogue. */
4249 ret_off
= TARGET_64BIT
? -16 : -20;
4250 if (frame_pointer_needed
)
4252 load_reg (2, ret_off
, HARD_FRAME_POINTER_REGNUM
);
4257 /* No frame pointer, and stack is smaller than 8k. */
4258 if (VAL_14_BITS_P (ret_off
- actual_fsize
))
4260 load_reg (2, ret_off
- actual_fsize
, STACK_POINTER_REGNUM
);
4266 /* General register restores. */
4267 if (frame_pointer_needed
)
4269 offset
= local_fsize
;
4271 /* If the current function calls __builtin_eh_return, then we need
4272 to restore the saved EH data registers. */
4273 if (DO_FRAME_NOTES
&& crtl
->calls_eh_return
)
4275 unsigned int i
, regno
;
4279 regno
= EH_RETURN_DATA_REGNO (i
);
4280 if (regno
== INVALID_REGNUM
)
4283 load_reg (regno
, offset
, HARD_FRAME_POINTER_REGNUM
);
4284 offset
+= UNITS_PER_WORD
;
4288 for (i
= 18; i
>= 4; i
--)
4289 if (df_regs_ever_live_p (i
) && ! call_used_regs
[i
])
4291 load_reg (i
, offset
, HARD_FRAME_POINTER_REGNUM
);
4292 offset
+= UNITS_PER_WORD
;
4297 offset
= local_fsize
- actual_fsize
;
4299 /* If the current function calls __builtin_eh_return, then we need
4300 to restore the saved EH data registers. */
4301 if (DO_FRAME_NOTES
&& crtl
->calls_eh_return
)
4303 unsigned int i
, regno
;
4307 regno
= EH_RETURN_DATA_REGNO (i
);
4308 if (regno
== INVALID_REGNUM
)
4311 /* Only for the first load.
4312 merge_sp_adjust_with_load holds the register load
4313 with which we will merge the sp adjustment. */
4314 if (merge_sp_adjust_with_load
== 0
4316 && VAL_14_BITS_P (-actual_fsize
))
4317 merge_sp_adjust_with_load
= regno
;
4319 load_reg (regno
, offset
, STACK_POINTER_REGNUM
);
4320 offset
+= UNITS_PER_WORD
;
4324 for (i
= 18; i
>= 3; i
--)
4326 if (df_regs_ever_live_p (i
) && ! call_used_regs
[i
])
4328 /* Only for the first load.
4329 merge_sp_adjust_with_load holds the register load
4330 with which we will merge the sp adjustment. */
4331 if (merge_sp_adjust_with_load
== 0
4333 && VAL_14_BITS_P (-actual_fsize
))
4334 merge_sp_adjust_with_load
= i
;
4336 load_reg (i
, offset
, STACK_POINTER_REGNUM
);
4337 offset
+= UNITS_PER_WORD
;
4342 /* Align pointer properly (doubleword boundary). */
4343 offset
= (offset
+ 7) & ~7;
4345 /* FP register restores. */
4348 /* Adjust the register to index off of. */
4349 if (frame_pointer_needed
)
4350 set_reg_plus_d (1, HARD_FRAME_POINTER_REGNUM
, offset
, 0);
4352 set_reg_plus_d (1, STACK_POINTER_REGNUM
, offset
, 0);
4354 /* Actually do the restores now. */
4355 for (i
= FP_SAVED_REG_LAST
; i
>= FP_SAVED_REG_FIRST
; i
-= FP_REG_STEP
)
4356 if (df_regs_ever_live_p (i
)
4357 || (! TARGET_64BIT
&& df_regs_ever_live_p (i
+ 1)))
4359 rtx src
= gen_rtx_MEM (DFmode
,
4360 gen_rtx_POST_INC (word_mode
, tmpreg
));
4361 rtx dest
= gen_rtx_REG (DFmode
, i
);
4362 emit_move_insn (dest
, src
);
4366 /* Emit a blockage insn here to keep these insns from being moved to
4367 an earlier spot in the epilogue, or into the main instruction stream.
4369 This is necessary as we must not cut the stack back before all the
4370 restores are finished. */
4371 emit_insn (gen_blockage ());
4373 /* Reset stack pointer (and possibly frame pointer). The stack
4374 pointer is initially set to fp + 64 to avoid a race condition. */
4375 if (frame_pointer_needed
)
4377 rtx delta
= GEN_INT (-64);
4379 set_reg_plus_d (STACK_POINTER_REGNUM
, HARD_FRAME_POINTER_REGNUM
, 64, 0);
4380 emit_insn (gen_pre_load (hard_frame_pointer_rtx
,
4381 stack_pointer_rtx
, delta
));
4383 /* If we were deferring a callee register restore, do it now. */
4384 else if (merge_sp_adjust_with_load
)
4386 rtx delta
= GEN_INT (-actual_fsize
);
4387 rtx dest
= gen_rtx_REG (word_mode
, merge_sp_adjust_with_load
);
4389 emit_insn (gen_pre_load (dest
, stack_pointer_rtx
, delta
));
4391 else if (actual_fsize
!= 0)
4392 set_reg_plus_d (STACK_POINTER_REGNUM
, STACK_POINTER_REGNUM
,
4395 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4396 frame greater than 8k), do so now. */
4398 load_reg (2, ret_off
, STACK_POINTER_REGNUM
);
4400 if (DO_FRAME_NOTES
&& crtl
->calls_eh_return
)
4402 rtx sa
= EH_RETURN_STACKADJ_RTX
;
4404 emit_insn (gen_blockage ());
4405 emit_insn (TARGET_64BIT
4406 ? gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
, sa
)
4407 : gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, sa
));
4412 pa_can_use_return_insn (void)
4414 if (!reload_completed
)
4417 if (frame_pointer_needed
)
4420 if (df_regs_ever_live_p (2))
4426 return pa_compute_frame_size (get_frame_size (), 0) == 0;
4430 hppa_pic_save_rtx (void)
4432 return get_hard_reg_initial_val (word_mode
, PIC_OFFSET_TABLE_REGNUM
);
4435 #ifndef NO_DEFERRED_PROFILE_COUNTERS
4436 #define NO_DEFERRED_PROFILE_COUNTERS 0
4440 /* Vector of funcdef numbers. */
4441 static vec
<int> funcdef_nos
;
4443 /* Output deferred profile counters. */
4445 output_deferred_profile_counters (void)
4450 if (funcdef_nos
.is_empty ())
4453 switch_to_section (data_section
);
4454 align
= MIN (BIGGEST_ALIGNMENT
, LONG_TYPE_SIZE
);
4455 ASM_OUTPUT_ALIGN (asm_out_file
, floor_log2 (align
/ BITS_PER_UNIT
));
4457 for (i
= 0; funcdef_nos
.iterate (i
, &n
); i
++)
4459 targetm
.asm_out
.internal_label (asm_out_file
, "LP", n
);
4460 assemble_integer (const0_rtx
, LONG_TYPE_SIZE
/ BITS_PER_UNIT
, align
, 1);
4463 funcdef_nos
.release ();
4467 hppa_profile_hook (int label_no
)
4469 /* We use SImode for the address of the function in both 32 and
4470 64-bit code to avoid having to provide DImode versions of the
4471 lcla2 and load_offset_label_address insn patterns. */
4472 rtx reg
= gen_reg_rtx (SImode
);
4473 rtx label_rtx
= gen_label_rtx ();
4474 rtx begin_label_rtx
, call_insn
;
4475 char begin_label_name
[16];
4477 ASM_GENERATE_INTERNAL_LABEL (begin_label_name
, FUNC_BEGIN_PROLOG_LABEL
,
4479 begin_label_rtx
= gen_rtx_SYMBOL_REF (SImode
, ggc_strdup (begin_label_name
));
4482 emit_move_insn (arg_pointer_rtx
,
4483 gen_rtx_PLUS (word_mode
, virtual_outgoing_args_rtx
,
4486 emit_move_insn (gen_rtx_REG (word_mode
, 26), gen_rtx_REG (word_mode
, 2));
4488 /* The address of the function is loaded into %r25 with an instruction-
4489 relative sequence that avoids the use of relocations. The sequence
4490 is split so that the load_offset_label_address instruction can
4491 occupy the delay slot of the call to _mcount. */
4493 emit_insn (gen_lcla2 (reg
, label_rtx
));
4495 emit_insn (gen_lcla1 (reg
, label_rtx
));
4497 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode
, 25),
4498 reg
, begin_label_rtx
, label_rtx
));
4500 #if !NO_DEFERRED_PROFILE_COUNTERS
4502 rtx count_label_rtx
, addr
, r24
;
4503 char count_label_name
[16];
4505 funcdef_nos
.safe_push (label_no
);
4506 ASM_GENERATE_INTERNAL_LABEL (count_label_name
, "LP", label_no
);
4507 count_label_rtx
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (count_label_name
));
4509 addr
= force_reg (Pmode
, count_label_rtx
);
4510 r24
= gen_rtx_REG (Pmode
, 24);
4511 emit_move_insn (r24
, addr
);
4514 emit_call_insn (gen_call (gen_rtx_MEM (Pmode
,
4515 gen_rtx_SYMBOL_REF (Pmode
,
4517 GEN_INT (TARGET_64BIT
? 24 : 12)));
4519 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
), r24
);
4524 emit_call_insn (gen_call (gen_rtx_MEM (Pmode
,
4525 gen_rtx_SYMBOL_REF (Pmode
,
4527 GEN_INT (TARGET_64BIT
? 16 : 8)));
4531 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
), gen_rtx_REG (SImode
, 25));
4532 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
), gen_rtx_REG (SImode
, 26));
4534 /* Indicate the _mcount call cannot throw, nor will it execute a
4536 make_reg_eh_region_note_nothrow_nononlocal (call_insn
);
4539 /* Fetch the return address for the frame COUNT steps up from
4540 the current frame, after the prologue. FRAMEADDR is the
4541 frame pointer of the COUNT frame.
4543 We want to ignore any export stub remnants here. To handle this,
4544 we examine the code at the return address, and if it is an export
4545 stub, we return a memory rtx for the stub return address stored
4548 The value returned is used in two different ways:
4550 1. To find a function's caller.
4552 2. To change the return address for a function.
4554 This function handles most instances of case 1; however, it will
4555 fail if there are two levels of stubs to execute on the return
4556 path. The only way I believe that can happen is if the return value
4557 needs a parameter relocation, which never happens for C code.
4559 This function handles most instances of case 2; however, it will
4560 fail if we did not originally have stub code on the return path
4561 but will need stub code on the new return path. This can happen if
4562 the caller & callee are both in the main program, but the new
4563 return location is in a shared library. */
4566 pa_return_addr_rtx (int count
, rtx frameaddr
)
4573 /* The instruction stream at the return address of a PA1.X export stub is:
4575 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4576 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4577 0x00011820 | stub+16: mtsp r1,sr0
4578 0xe0400002 | stub+20: be,n 0(sr0,rp)
4580 0xe0400002 must be specified as -532676606 so that it won't be
4581 rejected as an invalid immediate operand on 64-bit hosts.
4583 The instruction stream at the return address of a PA2.0 export stub is:
4585 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4586 0xe840d002 | stub+12: bve,n (rp)
4589 HOST_WIDE_INT insns
[4];
4595 rp
= get_hard_reg_initial_val (Pmode
, 2);
4597 if (TARGET_64BIT
|| TARGET_NO_SPACE_REGS
)
4600 /* If there is no export stub then just use the value saved from
4601 the return pointer register. */
4603 saved_rp
= gen_reg_rtx (Pmode
);
4604 emit_move_insn (saved_rp
, rp
);
4606 /* Get pointer to the instruction stream. We have to mask out the
4607 privilege level from the two low order bits of the return address
4608 pointer here so that ins will point to the start of the first
4609 instruction that would have been executed if we returned. */
4610 ins
= copy_to_reg (gen_rtx_AND (Pmode
, rp
, MASK_RETURN_ADDR
));
4611 label
= gen_label_rtx ();
4615 insns
[0] = 0x4bc23fd1;
4616 insns
[1] = -398405630;
4621 insns
[0] = 0x4bc23fd1;
4622 insns
[1] = 0x004010a1;
4623 insns
[2] = 0x00011820;
4624 insns
[3] = -532676606;
4628 /* Check the instruction stream at the normal return address for the
4629 export stub. If it is an export stub, than our return address is
4630 really in -24[frameaddr]. */
4632 for (i
= 0; i
< len
; i
++)
4634 rtx op0
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, ins
, i
* 4));
4635 rtx op1
= GEN_INT (insns
[i
]);
4636 emit_cmp_and_jump_insns (op0
, op1
, NE
, NULL
, SImode
, 0, label
);
4639 /* Here we know that our return address points to an export
4640 stub. We don't want to return the address of the export stub,
4641 but rather the return address of the export stub. That return
4642 address is stored at -24[frameaddr]. */
4644 emit_move_insn (saved_rp
,
4646 memory_address (Pmode
,
4647 plus_constant (Pmode
, frameaddr
,
4656 pa_emit_bcond_fp (rtx operands
[])
4658 enum rtx_code code
= GET_CODE (operands
[0]);
4659 rtx operand0
= operands
[1];
4660 rtx operand1
= operands
[2];
4661 rtx label
= operands
[3];
4663 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCFPmode
, 0),
4664 gen_rtx_fmt_ee (code
, CCFPmode
, operand0
, operand1
)));
4666 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
4667 gen_rtx_IF_THEN_ELSE (VOIDmode
,
4670 gen_rtx_REG (CCFPmode
, 0),
4672 gen_rtx_LABEL_REF (VOIDmode
, label
),
4677 /* Adjust the cost of a scheduling dependency. Return the new cost of
4678 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4681 pa_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
4683 enum attr_type attr_type
;
4685 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4686 true dependencies as they are described with bypasses now. */
4687 if (pa_cpu
>= PROCESSOR_8000
|| REG_NOTE_KIND (link
) == 0)
4690 if (! recog_memoized (insn
))
4693 attr_type
= get_attr_type (insn
);
4695 switch (REG_NOTE_KIND (link
))
4698 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4701 if (attr_type
== TYPE_FPLOAD
)
4703 rtx pat
= PATTERN (insn
);
4704 rtx dep_pat
= PATTERN (dep_insn
);
4705 if (GET_CODE (pat
) == PARALLEL
)
4707 /* This happens for the fldXs,mb patterns. */
4708 pat
= XVECEXP (pat
, 0, 0);
4710 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
4711 /* If this happens, we have to extend this to schedule
4712 optimally. Return 0 for now. */
4715 if (reg_mentioned_p (SET_DEST (pat
), SET_SRC (dep_pat
)))
4717 if (! recog_memoized (dep_insn
))
4719 switch (get_attr_type (dep_insn
))
4726 case TYPE_FPSQRTSGL
:
4727 case TYPE_FPSQRTDBL
:
4728 /* A fpload can't be issued until one cycle before a
4729 preceding arithmetic operation has finished if
4730 the target of the fpload is any of the sources
4731 (or destination) of the arithmetic operation. */
4732 return insn_default_latency (dep_insn
) - 1;
4739 else if (attr_type
== TYPE_FPALU
)
4741 rtx pat
= PATTERN (insn
);
4742 rtx dep_pat
= PATTERN (dep_insn
);
4743 if (GET_CODE (pat
) == PARALLEL
)
4745 /* This happens for the fldXs,mb patterns. */
4746 pat
= XVECEXP (pat
, 0, 0);
4748 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
4749 /* If this happens, we have to extend this to schedule
4750 optimally. Return 0 for now. */
4753 if (reg_mentioned_p (SET_DEST (pat
), SET_SRC (dep_pat
)))
4755 if (! recog_memoized (dep_insn
))
4757 switch (get_attr_type (dep_insn
))
4761 case TYPE_FPSQRTSGL
:
4762 case TYPE_FPSQRTDBL
:
4763 /* An ALU flop can't be issued until two cycles before a
4764 preceding divide or sqrt operation has finished if
4765 the target of the ALU flop is any of the sources
4766 (or destination) of the divide or sqrt operation. */
4767 return insn_default_latency (dep_insn
) - 2;
4775 /* For other anti dependencies, the cost is 0. */
4778 case REG_DEP_OUTPUT
:
4779 /* Output dependency; DEP_INSN writes a register that INSN writes some
4781 if (attr_type
== TYPE_FPLOAD
)
4783 rtx pat
= PATTERN (insn
);
4784 rtx dep_pat
= PATTERN (dep_insn
);
4785 if (GET_CODE (pat
) == PARALLEL
)
4787 /* This happens for the fldXs,mb patterns. */
4788 pat
= XVECEXP (pat
, 0, 0);
4790 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
4791 /* If this happens, we have to extend this to schedule
4792 optimally. Return 0 for now. */
4795 if (reg_mentioned_p (SET_DEST (pat
), SET_DEST (dep_pat
)))
4797 if (! recog_memoized (dep_insn
))
4799 switch (get_attr_type (dep_insn
))
4806 case TYPE_FPSQRTSGL
:
4807 case TYPE_FPSQRTDBL
:
4808 /* A fpload can't be issued until one cycle before a
4809 preceding arithmetic operation has finished if
4810 the target of the fpload is the destination of the
4811 arithmetic operation.
4813 Exception: For PA7100LC, PA7200 and PA7300, the cost
4814 is 3 cycles, unless they bundle together. We also
4815 pay the penalty if the second insn is a fpload. */
4816 return insn_default_latency (dep_insn
) - 1;
4823 else if (attr_type
== TYPE_FPALU
)
4825 rtx pat
= PATTERN (insn
);
4826 rtx dep_pat
= PATTERN (dep_insn
);
4827 if (GET_CODE (pat
) == PARALLEL
)
4829 /* This happens for the fldXs,mb patterns. */
4830 pat
= XVECEXP (pat
, 0, 0);
4832 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
4833 /* If this happens, we have to extend this to schedule
4834 optimally. Return 0 for now. */
4837 if (reg_mentioned_p (SET_DEST (pat
), SET_DEST (dep_pat
)))
4839 if (! recog_memoized (dep_insn
))
4841 switch (get_attr_type (dep_insn
))
4845 case TYPE_FPSQRTSGL
:
4846 case TYPE_FPSQRTDBL
:
4847 /* An ALU flop can't be issued until two cycles before a
4848 preceding divide or sqrt operation has finished if
4849 the target of the ALU flop is also the target of
4850 the divide or sqrt operation. */
4851 return insn_default_latency (dep_insn
) - 2;
4859 /* For other output dependencies, the cost is 0. */
4867 /* Adjust scheduling priorities. We use this to try and keep addil
4868 and the next use of %r1 close together. */
4870 pa_adjust_priority (rtx insn
, int priority
)
4872 rtx set
= single_set (insn
);
4876 src
= SET_SRC (set
);
4877 dest
= SET_DEST (set
);
4878 if (GET_CODE (src
) == LO_SUM
4879 && symbolic_operand (XEXP (src
, 1), VOIDmode
)
4880 && ! read_only_operand (XEXP (src
, 1), VOIDmode
))
4883 else if (GET_CODE (src
) == MEM
4884 && GET_CODE (XEXP (src
, 0)) == LO_SUM
4885 && symbolic_operand (XEXP (XEXP (src
, 0), 1), VOIDmode
)
4886 && ! read_only_operand (XEXP (XEXP (src
, 0), 1), VOIDmode
))
4889 else if (GET_CODE (dest
) == MEM
4890 && GET_CODE (XEXP (dest
, 0)) == LO_SUM
4891 && symbolic_operand (XEXP (XEXP (dest
, 0), 1), VOIDmode
)
4892 && ! read_only_operand (XEXP (XEXP (dest
, 0), 1), VOIDmode
))
4898 /* The 700 can only issue a single insn at a time.
4899 The 7XXX processors can issue two insns at a time.
4900 The 8000 can issue 4 insns at a time. */
4902 pa_issue_rate (void)
4906 case PROCESSOR_700
: return 1;
4907 case PROCESSOR_7100
: return 2;
4908 case PROCESSOR_7100LC
: return 2;
4909 case PROCESSOR_7200
: return 2;
4910 case PROCESSOR_7300
: return 2;
4911 case PROCESSOR_8000
: return 4;
4920 /* Return any length plus adjustment needed by INSN which already has
4921 its length computed as LENGTH. Return LENGTH if no adjustment is
4924 Also compute the length of an inline block move here as it is too
4925 complicated to express as a length attribute in pa.md. */
4927 pa_adjust_insn_length (rtx insn
, int length
)
4929 rtx pat
= PATTERN (insn
);
4931 /* If length is negative or undefined, provide initial length. */
4932 if ((unsigned int) length
>= INT_MAX
)
4934 if (GET_CODE (pat
) == SEQUENCE
)
4935 insn
= XVECEXP (pat
, 0, 0);
4937 switch (get_attr_type (insn
))
4940 length
= pa_attr_length_millicode_call (insn
);
4943 length
= pa_attr_length_call (insn
, 0);
4946 length
= pa_attr_length_call (insn
, 1);
4949 length
= pa_attr_length_indirect_call (insn
);
4951 case TYPE_SH_FUNC_ADRS
:
4952 length
= pa_attr_length_millicode_call (insn
) + 20;
4959 /* Jumps inside switch tables which have unfilled delay slots need
4961 if (GET_CODE (insn
) == JUMP_INSN
4962 && GET_CODE (pat
) == PARALLEL
4963 && get_attr_type (insn
) == TYPE_BTABLE_BRANCH
)
4965 /* Block move pattern. */
4966 else if (GET_CODE (insn
) == INSN
4967 && GET_CODE (pat
) == PARALLEL
4968 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
4969 && GET_CODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == MEM
4970 && GET_CODE (XEXP (XVECEXP (pat
, 0, 0), 1)) == MEM
4971 && GET_MODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == BLKmode
4972 && GET_MODE (XEXP (XVECEXP (pat
, 0, 0), 1)) == BLKmode
)
4973 length
+= compute_movmem_length (insn
) - 4;
4974 /* Block clear pattern. */
4975 else if (GET_CODE (insn
) == INSN
4976 && GET_CODE (pat
) == PARALLEL
4977 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
4978 && GET_CODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == MEM
4979 && XEXP (XVECEXP (pat
, 0, 0), 1) == const0_rtx
4980 && GET_MODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == BLKmode
)
4981 length
+= compute_clrmem_length (insn
) - 4;
4982 /* Conditional branch with an unfilled delay slot. */
4983 else if (GET_CODE (insn
) == JUMP_INSN
&& ! simplejump_p (insn
))
4985 /* Adjust a short backwards conditional with an unfilled delay slot. */
4986 if (GET_CODE (pat
) == SET
4988 && JUMP_LABEL (insn
) != NULL_RTX
4989 && ! forward_branch_p (insn
))
4991 else if (GET_CODE (pat
) == PARALLEL
4992 && get_attr_type (insn
) == TYPE_PARALLEL_BRANCH
4995 /* Adjust dbra insn with short backwards conditional branch with
4996 unfilled delay slot -- only for case where counter is in a
4997 general register register. */
4998 else if (GET_CODE (pat
) == PARALLEL
4999 && GET_CODE (XVECEXP (pat
, 0, 1)) == SET
5000 && GET_CODE (XEXP (XVECEXP (pat
, 0, 1), 0)) == REG
5001 && ! FP_REG_P (XEXP (XVECEXP (pat
, 0, 1), 0))
5003 && ! forward_branch_p (insn
))
5009 /* Implement the TARGET_PRINT_OPERAND_PUNCT_VALID_P hook. */
5012 pa_print_operand_punct_valid_p (unsigned char code
)
5023 /* Print operand X (an rtx) in assembler syntax to file FILE.
5024 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
5025 For `%' followed by punctuation, CODE is the punctuation and X is null. */
5028 pa_print_operand (FILE *file
, rtx x
, int code
)
5033 /* Output a 'nop' if there's nothing for the delay slot. */
5034 if (dbr_sequence_length () == 0)
5035 fputs ("\n\tnop", file
);
5038 /* Output a nullification completer if there's nothing for the */
5039 /* delay slot or nullification is requested. */
5040 if (dbr_sequence_length () == 0 ||
5042 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0))))
5046 /* Print out the second register name of a register pair.
5047 I.e., R (6) => 7. */
5048 fputs (reg_names
[REGNO (x
) + 1], file
);
5051 /* A register or zero. */
5053 || (x
== CONST0_RTX (DFmode
))
5054 || (x
== CONST0_RTX (SFmode
)))
5056 fputs ("%r0", file
);
5062 /* A register or zero (floating point). */
5064 || (x
== CONST0_RTX (DFmode
))
5065 || (x
== CONST0_RTX (SFmode
)))
5067 fputs ("%fr0", file
);
5076 xoperands
[0] = XEXP (XEXP (x
, 0), 0);
5077 xoperands
[1] = XVECEXP (XEXP (XEXP (x
, 0), 1), 0, 0);
5078 pa_output_global_address (file
, xoperands
[1], 0);
5079 fprintf (file
, "(%s)", reg_names
[REGNO (xoperands
[0])]);
5083 case 'C': /* Plain (C)ondition */
5085 switch (GET_CODE (x
))
5088 fputs ("=", file
); break;
5090 fputs ("<>", file
); break;
5092 fputs (">", file
); break;
5094 fputs (">=", file
); break;
5096 fputs (">>=", file
); break;
5098 fputs (">>", file
); break;
5100 fputs ("<", file
); break;
5102 fputs ("<=", file
); break;
5104 fputs ("<<=", file
); break;
5106 fputs ("<<", file
); break;
5111 case 'N': /* Condition, (N)egated */
5112 switch (GET_CODE (x
))
5115 fputs ("<>", file
); break;
5117 fputs ("=", file
); break;
5119 fputs ("<=", file
); break;
5121 fputs ("<", file
); break;
5123 fputs ("<<", file
); break;
5125 fputs ("<<=", file
); break;
5127 fputs (">=", file
); break;
5129 fputs (">", file
); break;
5131 fputs (">>", file
); break;
5133 fputs (">>=", file
); break;
5138 /* For floating point comparisons. Note that the output
5139 predicates are the complement of the desired mode. The
5140 conditions for GT, GE, LT, LE and LTGT cause an invalid
5141 operation exception if the result is unordered and this
5142 exception is enabled in the floating-point status register. */
5144 switch (GET_CODE (x
))
5147 fputs ("!=", file
); break;
5149 fputs ("=", file
); break;
5151 fputs ("!>", file
); break;
5153 fputs ("!>=", file
); break;
5155 fputs ("!<", file
); break;
5157 fputs ("!<=", file
); break;
5159 fputs ("!<>", file
); break;
5161 fputs ("!?<=", file
); break;
5163 fputs ("!?<", file
); break;
5165 fputs ("!?>=", file
); break;
5167 fputs ("!?>", file
); break;
5169 fputs ("!?=", file
); break;
5171 fputs ("!?", file
); break;
5173 fputs ("?", file
); break;
5178 case 'S': /* Condition, operands are (S)wapped. */
5179 switch (GET_CODE (x
))
5182 fputs ("=", file
); break;
5184 fputs ("<>", file
); break;
5186 fputs ("<", file
); break;
5188 fputs ("<=", file
); break;
5190 fputs ("<<=", file
); break;
5192 fputs ("<<", file
); break;
5194 fputs (">", file
); break;
5196 fputs (">=", file
); break;
5198 fputs (">>=", file
); break;
5200 fputs (">>", file
); break;
5205 case 'B': /* Condition, (B)oth swapped and negate. */
5206 switch (GET_CODE (x
))
5209 fputs ("<>", file
); break;
5211 fputs ("=", file
); break;
5213 fputs (">=", file
); break;
5215 fputs (">", file
); break;
5217 fputs (">>", file
); break;
5219 fputs (">>=", file
); break;
5221 fputs ("<=", file
); break;
5223 fputs ("<", file
); break;
5225 fputs ("<<", file
); break;
5227 fputs ("<<=", file
); break;
5233 gcc_assert (GET_CODE (x
) == CONST_INT
);
5234 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~INTVAL (x
));
5237 gcc_assert (GET_CODE (x
) == CONST_INT
);
5238 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 64 - (INTVAL (x
) & 63));
5241 gcc_assert (GET_CODE (x
) == CONST_INT
);
5242 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 32 - (INTVAL (x
) & 31));
5245 gcc_assert (GET_CODE (x
) == CONST_INT
&& exact_log2 (INTVAL (x
)) >= 0);
5246 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
5249 gcc_assert (GET_CODE (x
) == CONST_INT
);
5250 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 63 - (INTVAL (x
) & 63));
5253 gcc_assert (GET_CODE (x
) == CONST_INT
);
5254 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 31 - (INTVAL (x
) & 31));
5257 if (GET_CODE (x
) == CONST_INT
)
5262 switch (GET_CODE (XEXP (x
, 0)))
5266 if (ASSEMBLER_DIALECT
== 0)
5267 fputs ("s,mb", file
);
5269 fputs (",mb", file
);
5273 if (ASSEMBLER_DIALECT
== 0)
5274 fputs ("s,ma", file
);
5276 fputs (",ma", file
);
5279 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
5280 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == REG
)
5282 if (ASSEMBLER_DIALECT
== 0)
5285 else if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
5286 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == MULT
)
5288 if (ASSEMBLER_DIALECT
== 0)
5289 fputs ("x,s", file
);
5293 else if (code
== 'F' && ASSEMBLER_DIALECT
== 0)
5297 if (code
== 'F' && ASSEMBLER_DIALECT
== 0)
5303 pa_output_global_address (file
, x
, 0);
5306 pa_output_global_address (file
, x
, 1);
5308 case 0: /* Don't do anything special */
5313 compute_zdepwi_operands (INTVAL (x
), op
);
5314 fprintf (file
, "%d,%d,%d", op
[0], op
[1], op
[2]);
5320 compute_zdepdi_operands (INTVAL (x
), op
);
5321 fprintf (file
, "%d,%d,%d", op
[0], op
[1], op
[2]);
5325 /* We can get here from a .vtable_inherit due to our
5326 CONSTANT_ADDRESS_P rejecting perfectly good constant
5332 if (GET_CODE (x
) == REG
)
5334 fputs (reg_names
[REGNO (x
)], file
);
5335 if (TARGET_64BIT
&& FP_REG_P (x
) && GET_MODE_SIZE (GET_MODE (x
)) <= 4)
5341 && GET_MODE_SIZE (GET_MODE (x
)) <= 4
5342 && (REGNO (x
) & 1) == 0)
5345 else if (GET_CODE (x
) == MEM
)
5347 int size
= GET_MODE_SIZE (GET_MODE (x
));
5348 rtx base
= NULL_RTX
;
5349 switch (GET_CODE (XEXP (x
, 0)))
5353 base
= XEXP (XEXP (x
, 0), 0);
5354 fprintf (file
, "-%d(%s)", size
, reg_names
[REGNO (base
)]);
5358 base
= XEXP (XEXP (x
, 0), 0);
5359 fprintf (file
, "%d(%s)", size
, reg_names
[REGNO (base
)]);
5362 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
)
5363 fprintf (file
, "%s(%s)",
5364 reg_names
[REGNO (XEXP (XEXP (XEXP (x
, 0), 0), 0))],
5365 reg_names
[REGNO (XEXP (XEXP (x
, 0), 1))]);
5366 else if (GET_CODE (XEXP (XEXP (x
, 0), 1)) == MULT
)
5367 fprintf (file
, "%s(%s)",
5368 reg_names
[REGNO (XEXP (XEXP (XEXP (x
, 0), 1), 0))],
5369 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
5370 else if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
5371 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == REG
)
5373 /* Because the REG_POINTER flag can get lost during reload,
5374 pa_legitimate_address_p canonicalizes the order of the
5375 index and base registers in the combined move patterns. */
5376 rtx base
= XEXP (XEXP (x
, 0), 1);
5377 rtx index
= XEXP (XEXP (x
, 0), 0);
5379 fprintf (file
, "%s(%s)",
5380 reg_names
[REGNO (index
)], reg_names
[REGNO (base
)]);
5383 output_address (XEXP (x
, 0));
5386 output_address (XEXP (x
, 0));
5391 output_addr_const (file
, x
);
5394 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5397 pa_output_global_address (FILE *file
, rtx x
, int round_constant
)
5400 /* Imagine (high (const (plus ...))). */
5401 if (GET_CODE (x
) == HIGH
)
5404 if (GET_CODE (x
) == SYMBOL_REF
&& read_only_operand (x
, VOIDmode
))
5405 output_addr_const (file
, x
);
5406 else if (GET_CODE (x
) == SYMBOL_REF
&& !flag_pic
)
5408 output_addr_const (file
, x
);
5409 fputs ("-$global$", file
);
5411 else if (GET_CODE (x
) == CONST
)
5413 const char *sep
= "";
5414 int offset
= 0; /* assembler wants -$global$ at end */
5415 rtx base
= NULL_RTX
;
5417 switch (GET_CODE (XEXP (XEXP (x
, 0), 0)))
5420 base
= XEXP (XEXP (x
, 0), 0);
5421 output_addr_const (file
, base
);
5424 offset
= INTVAL (XEXP (XEXP (x
, 0), 0));
5430 switch (GET_CODE (XEXP (XEXP (x
, 0), 1)))
5433 base
= XEXP (XEXP (x
, 0), 1);
5434 output_addr_const (file
, base
);
5437 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
5443 /* How bogus. The compiler is apparently responsible for
5444 rounding the constant if it uses an LR field selector.
5446 The linker and/or assembler seem a better place since
5447 they have to do this kind of thing already.
5449 If we fail to do this, HP's optimizing linker may eliminate
5450 an addil, but not update the ldw/stw/ldo instruction that
5451 uses the result of the addil. */
5453 offset
= ((offset
+ 0x1000) & ~0x1fff);
5455 switch (GET_CODE (XEXP (x
, 0)))
5468 gcc_assert (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
);
5476 if (!read_only_operand (base
, VOIDmode
) && !flag_pic
)
5477 fputs ("-$global$", file
);
5479 fprintf (file
, "%s%d", sep
, offset
);
5482 output_addr_const (file
, x
);
5485 /* Output boilerplate text to appear at the beginning of the file.
5486 There are several possible versions. */
5487 #define aputs(x) fputs(x, asm_out_file)
5489 pa_file_start_level (void)
5492 aputs ("\t.LEVEL 2.0w\n");
5493 else if (TARGET_PA_20
)
5494 aputs ("\t.LEVEL 2.0\n");
5495 else if (TARGET_PA_11
)
5496 aputs ("\t.LEVEL 1.1\n");
5498 aputs ("\t.LEVEL 1.0\n");
5502 pa_file_start_space (int sortspace
)
5504 aputs ("\t.SPACE $PRIVATE$");
5507 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31");
5509 aputs ("\n\t.SUBSPA $TM_CLONE_TABLE$,QUAD=1,ALIGN=8,ACCESS=31");
5510 aputs ("\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5511 "\n\t.SPACE $TEXT$");
5514 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5515 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5519 pa_file_start_file (int want_version
)
5521 if (write_symbols
!= NO_DEBUG
)
5523 output_file_directive (asm_out_file
, main_input_filename
);
5525 aputs ("\t.version\t\"01.01\"\n");
5530 pa_file_start_mcount (const char *aswhat
)
5533 fprintf (asm_out_file
, "\t.IMPORT _mcount,%s\n", aswhat
);
5537 pa_elf_file_start (void)
5539 pa_file_start_level ();
5540 pa_file_start_mcount ("ENTRY");
5541 pa_file_start_file (0);
5545 pa_som_file_start (void)
5547 pa_file_start_level ();
5548 pa_file_start_space (0);
5549 aputs ("\t.IMPORT $global$,DATA\n"
5550 "\t.IMPORT $$dyncall,MILLICODE\n");
5551 pa_file_start_mcount ("CODE");
5552 pa_file_start_file (0);
5556 pa_linux_file_start (void)
5558 pa_file_start_file (1);
5559 pa_file_start_level ();
5560 pa_file_start_mcount ("CODE");
5564 pa_hpux64_gas_file_start (void)
5566 pa_file_start_level ();
5567 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5569 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, "_mcount", "function");
5571 pa_file_start_file (1);
5575 pa_hpux64_hpas_file_start (void)
5577 pa_file_start_level ();
5578 pa_file_start_space (1);
5579 pa_file_start_mcount ("CODE");
5580 pa_file_start_file (0);
5584 /* Search the deferred plabel list for SYMBOL and return its internal
5585 label. If an entry for SYMBOL is not found, a new entry is created. */
5588 pa_get_deferred_plabel (rtx symbol
)
5590 const char *fname
= XSTR (symbol
, 0);
5593 /* See if we have already put this function on the list of deferred
5594 plabels. This list is generally small, so a liner search is not
5595 too ugly. If it proves too slow replace it with something faster. */
5596 for (i
= 0; i
< n_deferred_plabels
; i
++)
5597 if (strcmp (fname
, XSTR (deferred_plabels
[i
].symbol
, 0)) == 0)
5600 /* If the deferred plabel list is empty, or this entry was not found
5601 on the list, create a new entry on the list. */
5602 if (deferred_plabels
== NULL
|| i
== n_deferred_plabels
)
5606 if (deferred_plabels
== 0)
5607 deferred_plabels
= ggc_alloc_deferred_plabel ();
5609 deferred_plabels
= GGC_RESIZEVEC (struct deferred_plabel
,
5611 n_deferred_plabels
+ 1);
5613 i
= n_deferred_plabels
++;
5614 deferred_plabels
[i
].internal_label
= gen_label_rtx ();
5615 deferred_plabels
[i
].symbol
= symbol
;
5617 /* Gross. We have just implicitly taken the address of this
5618 function. Mark it in the same manner as assemble_name. */
5619 id
= maybe_get_identifier (targetm
.strip_name_encoding (fname
));
5621 mark_referenced (id
);
5624 return deferred_plabels
[i
].internal_label
;
5628 output_deferred_plabels (void)
5632 /* If we have some deferred plabels, then we need to switch into the
5633 data or readonly data section, and align it to a 4 byte boundary
5634 before outputting the deferred plabels. */
5635 if (n_deferred_plabels
)
5637 switch_to_section (flag_pic
? data_section
: readonly_data_section
);
5638 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
5641 /* Now output the deferred plabels. */
5642 for (i
= 0; i
< n_deferred_plabels
; i
++)
5644 targetm
.asm_out
.internal_label (asm_out_file
, "L",
5645 CODE_LABEL_NUMBER (deferred_plabels
[i
].internal_label
));
5646 assemble_integer (deferred_plabels
[i
].symbol
,
5647 TARGET_64BIT
? 8 : 4, TARGET_64BIT
? 64 : 32, 1);
5651 /* Initialize optabs to point to emulation routines. */
5654 pa_init_libfuncs (void)
5656 if (HPUX_LONG_DOUBLE_LIBRARY
)
5658 set_optab_libfunc (add_optab
, TFmode
, "_U_Qfadd");
5659 set_optab_libfunc (sub_optab
, TFmode
, "_U_Qfsub");
5660 set_optab_libfunc (smul_optab
, TFmode
, "_U_Qfmpy");
5661 set_optab_libfunc (sdiv_optab
, TFmode
, "_U_Qfdiv");
5662 set_optab_libfunc (smin_optab
, TFmode
, "_U_Qmin");
5663 set_optab_libfunc (smax_optab
, TFmode
, "_U_Qfmax");
5664 set_optab_libfunc (sqrt_optab
, TFmode
, "_U_Qfsqrt");
5665 set_optab_libfunc (abs_optab
, TFmode
, "_U_Qfabs");
5666 set_optab_libfunc (neg_optab
, TFmode
, "_U_Qfneg");
5668 set_optab_libfunc (eq_optab
, TFmode
, "_U_Qfeq");
5669 set_optab_libfunc (ne_optab
, TFmode
, "_U_Qfne");
5670 set_optab_libfunc (gt_optab
, TFmode
, "_U_Qfgt");
5671 set_optab_libfunc (ge_optab
, TFmode
, "_U_Qfge");
5672 set_optab_libfunc (lt_optab
, TFmode
, "_U_Qflt");
5673 set_optab_libfunc (le_optab
, TFmode
, "_U_Qfle");
5674 set_optab_libfunc (unord_optab
, TFmode
, "_U_Qfunord");
5676 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_U_Qfcnvff_sgl_to_quad");
5677 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_U_Qfcnvff_dbl_to_quad");
5678 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_U_Qfcnvff_quad_to_sgl");
5679 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_U_Qfcnvff_quad_to_dbl");
5681 set_conv_libfunc (sfix_optab
, SImode
, TFmode
,
5682 TARGET_64BIT
? "__U_Qfcnvfxt_quad_to_sgl"
5683 : "_U_Qfcnvfxt_quad_to_sgl");
5684 set_conv_libfunc (sfix_optab
, DImode
, TFmode
,
5685 "_U_Qfcnvfxt_quad_to_dbl");
5686 set_conv_libfunc (ufix_optab
, SImode
, TFmode
,
5687 "_U_Qfcnvfxt_quad_to_usgl");
5688 set_conv_libfunc (ufix_optab
, DImode
, TFmode
,
5689 "_U_Qfcnvfxt_quad_to_udbl");
5691 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
,
5692 "_U_Qfcnvxf_sgl_to_quad");
5693 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
,
5694 "_U_Qfcnvxf_dbl_to_quad");
5695 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
,
5696 "_U_Qfcnvxf_usgl_to_quad");
5697 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
,
5698 "_U_Qfcnvxf_udbl_to_quad");
5701 if (TARGET_SYNC_LIBCALL
)
5702 init_sync_libfuncs (UNITS_PER_WORD
);
5705 /* HP's millicode routines mean something special to the assembler.
5706 Keep track of which ones we have used. */
5708 enum millicodes
{ remI
, remU
, divI
, divU
, mulI
, end1000
};
5709 static void import_milli (enum millicodes
);
5710 static char imported
[(int) end1000
];
5711 static const char * const milli_names
[] = {"remI", "remU", "divI", "divU", "mulI"};
5712 static const char import_string
[] = ".IMPORT $$....,MILLICODE";
5713 #define MILLI_START 10
5716 import_milli (enum millicodes code
)
5718 char str
[sizeof (import_string
)];
5720 if (!imported
[(int) code
])
5722 imported
[(int) code
] = 1;
5723 strcpy (str
, import_string
);
5724 strncpy (str
+ MILLI_START
, milli_names
[(int) code
], 4);
5725 output_asm_insn (str
, 0);
5729 /* The register constraints have put the operands and return value in
5730 the proper registers. */
5733 pa_output_mul_insn (int unsignedp ATTRIBUTE_UNUSED
, rtx insn
)
5735 import_milli (mulI
);
5736 return pa_output_millicode_call (insn
, gen_rtx_SYMBOL_REF (Pmode
, "$$mulI"));
5739 /* Emit the rtl for doing a division by a constant. */
5741 /* Do magic division millicodes exist for this value? */
5742 const int pa_magic_milli
[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1};
5744 /* We'll use an array to keep track of the magic millicodes and
5745 whether or not we've used them already. [n][0] is signed, [n][1] is
5748 static int div_milli
[16][2];
5751 pa_emit_hpdiv_const (rtx
*operands
, int unsignedp
)
5753 if (GET_CODE (operands
[2]) == CONST_INT
5754 && INTVAL (operands
[2]) > 0
5755 && INTVAL (operands
[2]) < 16
5756 && pa_magic_milli
[INTVAL (operands
[2])])
5758 rtx ret
= gen_rtx_REG (SImode
, TARGET_64BIT
? 2 : 31);
5760 emit_move_insn (gen_rtx_REG (SImode
, 26), operands
[1]);
5764 gen_rtvec (6, gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, 29),
5765 gen_rtx_fmt_ee (unsignedp
? UDIV
: DIV
,
5767 gen_rtx_REG (SImode
, 26),
5769 gen_rtx_CLOBBER (VOIDmode
, operands
[4]),
5770 gen_rtx_CLOBBER (VOIDmode
, operands
[3]),
5771 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 26)),
5772 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 25)),
5773 gen_rtx_CLOBBER (VOIDmode
, ret
))));
5774 emit_move_insn (operands
[0], gen_rtx_REG (SImode
, 29));
5781 pa_output_div_insn (rtx
*operands
, int unsignedp
, rtx insn
)
5785 /* If the divisor is a constant, try to use one of the special
5787 if (GET_CODE (operands
[0]) == CONST_INT
)
5789 static char buf
[100];
5790 divisor
= INTVAL (operands
[0]);
5791 if (!div_milli
[divisor
][unsignedp
])
5793 div_milli
[divisor
][unsignedp
] = 1;
5795 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands
);
5797 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands
);
5801 sprintf (buf
, "$$divU_" HOST_WIDE_INT_PRINT_DEC
,
5802 INTVAL (operands
[0]));
5803 return pa_output_millicode_call (insn
,
5804 gen_rtx_SYMBOL_REF (SImode
, buf
));
5808 sprintf (buf
, "$$divI_" HOST_WIDE_INT_PRINT_DEC
,
5809 INTVAL (operands
[0]));
5810 return pa_output_millicode_call (insn
,
5811 gen_rtx_SYMBOL_REF (SImode
, buf
));
5814 /* Divisor isn't a special constant. */
5819 import_milli (divU
);
5820 return pa_output_millicode_call (insn
,
5821 gen_rtx_SYMBOL_REF (SImode
, "$$divU"));
5825 import_milli (divI
);
5826 return pa_output_millicode_call (insn
,
5827 gen_rtx_SYMBOL_REF (SImode
, "$$divI"));
5832 /* Output a $$rem millicode to do mod. */
5835 pa_output_mod_insn (int unsignedp
, rtx insn
)
5839 import_milli (remU
);
5840 return pa_output_millicode_call (insn
,
5841 gen_rtx_SYMBOL_REF (SImode
, "$$remU"));
5845 import_milli (remI
);
5846 return pa_output_millicode_call (insn
,
5847 gen_rtx_SYMBOL_REF (SImode
, "$$remI"));
5852 pa_output_arg_descriptor (rtx call_insn
)
5854 const char *arg_regs
[4];
5855 enum machine_mode arg_mode
;
5857 int i
, output_flag
= 0;
5860 /* We neither need nor want argument location descriptors for the
5861 64bit runtime environment or the ELF32 environment. */
5862 if (TARGET_64BIT
|| TARGET_ELF32
)
5865 for (i
= 0; i
< 4; i
++)
5868 /* Specify explicitly that no argument relocations should take place
5869 if using the portable runtime calling conventions. */
5870 if (TARGET_PORTABLE_RUNTIME
)
5872 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5877 gcc_assert (GET_CODE (call_insn
) == CALL_INSN
);
5878 for (link
= CALL_INSN_FUNCTION_USAGE (call_insn
);
5879 link
; link
= XEXP (link
, 1))
5881 rtx use
= XEXP (link
, 0);
5883 if (! (GET_CODE (use
) == USE
5884 && GET_CODE (XEXP (use
, 0)) == REG
5885 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use
, 0)))))
5888 arg_mode
= GET_MODE (XEXP (use
, 0));
5889 regno
= REGNO (XEXP (use
, 0));
5890 if (regno
>= 23 && regno
<= 26)
5892 arg_regs
[26 - regno
] = "GR";
5893 if (arg_mode
== DImode
)
5894 arg_regs
[25 - regno
] = "GR";
5896 else if (regno
>= 32 && regno
<= 39)
5898 if (arg_mode
== SFmode
)
5899 arg_regs
[(regno
- 32) / 2] = "FR";
5902 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5903 arg_regs
[(regno
- 34) / 2] = "FR";
5904 arg_regs
[(regno
- 34) / 2 + 1] = "FU";
5906 arg_regs
[(regno
- 34) / 2] = "FU";
5907 arg_regs
[(regno
- 34) / 2 + 1] = "FR";
5912 fputs ("\t.CALL ", asm_out_file
);
5913 for (i
= 0; i
< 4; i
++)
5918 fputc (',', asm_out_file
);
5919 fprintf (asm_out_file
, "ARGW%d=%s", i
, arg_regs
[i
]);
5922 fputc ('\n', asm_out_file
);
5925 /* Inform reload about cases where moving X with a mode MODE to or from
5926 a register in RCLASS requires an extra scratch or immediate register.
5927 Return the class needed for the immediate register. */
5930 pa_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
5931 enum machine_mode mode
, secondary_reload_info
*sri
)
5934 enum reg_class rclass
= (enum reg_class
) rclass_i
;
5936 /* Handle the easy stuff first. */
5937 if (rclass
== R1_REGS
)
5943 if (rclass
== BASE_REG_CLASS
&& regno
< FIRST_PSEUDO_REGISTER
)
5949 /* If we have something like (mem (mem (...)), we can safely assume the
5950 inner MEM will end up in a general register after reloading, so there's
5951 no need for a secondary reload. */
5952 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == MEM
)
5955 /* Trying to load a constant into a FP register during PIC code
5956 generation requires %r1 as a scratch register. For float modes,
5957 the only legitimate constant is CONST0_RTX. However, there are
5958 a few patterns that accept constant double operands. */
5960 && FP_REG_CLASS_P (rclass
)
5961 && (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
))
5966 sri
->icode
= CODE_FOR_reload_insi_r1
;
5970 sri
->icode
= CODE_FOR_reload_indi_r1
;
5974 sri
->icode
= CODE_FOR_reload_insf_r1
;
5978 sri
->icode
= CODE_FOR_reload_indf_r1
;
5987 /* Secondary reloads of symbolic expressions require %r1 as a scratch
5988 register when we're generating PIC code or when the operand isn't
5990 if (pa_symbolic_expression_p (x
))
5992 if (GET_CODE (x
) == HIGH
)
5995 if (flag_pic
|| !read_only_operand (x
, VOIDmode
))
6000 sri
->icode
= CODE_FOR_reload_insi_r1
;
6004 sri
->icode
= CODE_FOR_reload_indi_r1
;
6014 /* Profiling showed the PA port spends about 1.3% of its compilation
6015 time in true_regnum from calls inside pa_secondary_reload_class. */
6016 if (regno
>= FIRST_PSEUDO_REGISTER
|| GET_CODE (x
) == SUBREG
)
6017 regno
= true_regnum (x
);
6019 /* Handle reloads for floating point loads and stores. */
6020 if ((regno
>= FIRST_PSEUDO_REGISTER
|| regno
== -1)
6021 && FP_REG_CLASS_P (rclass
))
6027 /* We don't need an intermediate for indexed and LO_SUM DLT
6028 memory addresses. When INT14_OK_STRICT is true, it might
6029 appear that we could directly allow register indirect
6030 memory addresses. However, this doesn't work because we
6031 don't support SUBREGs in floating-point register copies
6032 and reload doesn't tell us when it's going to use a SUBREG. */
6033 if (IS_INDEX_ADDR_P (x
)
6034 || IS_LO_SUM_DLT_ADDR_P (x
))
6037 /* Request intermediate general register. */
6038 return GENERAL_REGS
;
6041 /* Request a secondary reload with a general scratch register
6042 for everything else. ??? Could symbolic operands be handled
6043 directly when generating non-pic PA 2.0 code? */
6045 ? direct_optab_handler (reload_in_optab
, mode
)
6046 : direct_optab_handler (reload_out_optab
, mode
));
6050 /* A SAR<->FP register copy requires an intermediate general register
6051 and secondary memory. We need a secondary reload with a general
6052 scratch register for spills. */
6053 if (rclass
== SHIFT_REGS
)
6056 if (regno
>= FIRST_PSEUDO_REGISTER
|| regno
< 0)
6059 ? direct_optab_handler (reload_in_optab
, mode
)
6060 : direct_optab_handler (reload_out_optab
, mode
));
6064 /* Handle FP copy. */
6065 if (FP_REG_CLASS_P (REGNO_REG_CLASS (regno
)))
6066 return GENERAL_REGS
;
6069 if (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
6070 && REGNO_REG_CLASS (regno
) == SHIFT_REGS
6071 && FP_REG_CLASS_P (rclass
))
6072 return GENERAL_REGS
;
6077 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. The argument pointer
6078 is only marked as live on entry by df-scan when it is a fixed
6079 register. It isn't a fixed register in the 64-bit runtime,
6080 so we need to mark it here. */
6083 pa_extra_live_on_entry (bitmap regs
)
6086 bitmap_set_bit (regs
, ARG_POINTER_REGNUM
);
6089 /* Implement EH_RETURN_HANDLER_RTX. The MEM needs to be volatile
6090 to prevent it from being deleted. */
6093 pa_eh_return_handler_rtx (void)
6097 tmp
= gen_rtx_PLUS (word_mode
, hard_frame_pointer_rtx
,
6098 TARGET_64BIT
? GEN_INT (-16) : GEN_INT (-20));
6099 tmp
= gen_rtx_MEM (word_mode
, tmp
);
6104 /* In the 32-bit runtime, arguments larger than eight bytes are passed
6105 by invisible reference. As a GCC extension, we also pass anything
6106 with a zero or variable size by reference.
6108 The 64-bit runtime does not describe passing any types by invisible
6109 reference. The internals of GCC can't currently handle passing
6110 empty structures, and zero or variable length arrays when they are
6111 not passed entirely on the stack or by reference. Thus, as a GCC
6112 extension, we pass these types by reference. The HP compiler doesn't
6113 support these types, so hopefully there shouldn't be any compatibility
6114 issues. This may have to be revisited when HP releases a C99 compiler
6115 or updates the ABI. */
6118 pa_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
6119 enum machine_mode mode
, const_tree type
,
6120 bool named ATTRIBUTE_UNUSED
)
6125 size
= int_size_in_bytes (type
);
6127 size
= GET_MODE_SIZE (mode
);
6132 return size
<= 0 || size
> 8;
6136 pa_function_arg_padding (enum machine_mode mode
, const_tree type
)
6141 && (AGGREGATE_TYPE_P (type
)
6142 || TREE_CODE (type
) == COMPLEX_TYPE
6143 || TREE_CODE (type
) == VECTOR_TYPE
)))
6145 /* Return none if justification is not required. */
6147 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
6148 && (int_size_in_bytes (type
) * BITS_PER_UNIT
) % PARM_BOUNDARY
== 0)
6151 /* The directions set here are ignored when a BLKmode argument larger
6152 than a word is placed in a register. Different code is used for
6153 the stack and registers. This makes it difficult to have a
6154 consistent data representation for both the stack and registers.
6155 For both runtimes, the justification and padding for arguments on
6156 the stack and in registers should be identical. */
6158 /* The 64-bit runtime specifies left justification for aggregates. */
6161 /* The 32-bit runtime architecture specifies right justification.
6162 When the argument is passed on the stack, the argument is padded
6163 with garbage on the left. The HP compiler pads with zeros. */
6167 if (GET_MODE_BITSIZE (mode
) < PARM_BOUNDARY
)
6174 /* Do what is necessary for `va_start'. We look at the current function
6175 to determine if stdargs or varargs is used and fill in an initial
6176 va_list. A pointer to this constructor is returned. */
6179 hppa_builtin_saveregs (void)
6182 tree fntype
= TREE_TYPE (current_function_decl
);
6183 int argadj
= ((!stdarg_p (fntype
))
6184 ? UNITS_PER_WORD
: 0);
6187 offset
= plus_constant (Pmode
, crtl
->args
.arg_offset_rtx
, argadj
);
6189 offset
= crtl
->args
.arg_offset_rtx
;
6195 /* Adjust for varargs/stdarg differences. */
6197 offset
= plus_constant (Pmode
, crtl
->args
.arg_offset_rtx
, -argadj
);
6199 offset
= crtl
->args
.arg_offset_rtx
;
6201 /* We need to save %r26 .. %r19 inclusive starting at offset -64
6202 from the incoming arg pointer and growing to larger addresses. */
6203 for (i
= 26, off
= -64; i
>= 19; i
--, off
+= 8)
6204 emit_move_insn (gen_rtx_MEM (word_mode
,
6205 plus_constant (Pmode
,
6206 arg_pointer_rtx
, off
)),
6207 gen_rtx_REG (word_mode
, i
));
6209 /* The incoming args pointer points just beyond the flushback area;
6210 normally this is not a serious concern. However, when we are doing
6211 varargs/stdargs we want to make the arg pointer point to the start
6212 of the incoming argument area. */
6213 emit_move_insn (virtual_incoming_args_rtx
,
6214 plus_constant (Pmode
, arg_pointer_rtx
, -64));
6216 /* Now return a pointer to the first anonymous argument. */
6217 return copy_to_reg (expand_binop (Pmode
, add_optab
,
6218 virtual_incoming_args_rtx
,
6219 offset
, 0, 0, OPTAB_LIB_WIDEN
));
6222 /* Store general registers on the stack. */
6223 dest
= gen_rtx_MEM (BLKmode
,
6224 plus_constant (Pmode
, crtl
->args
.internal_arg_pointer
,
6226 set_mem_alias_set (dest
, get_varargs_alias_set ());
6227 set_mem_align (dest
, BITS_PER_WORD
);
6228 move_block_from_reg (23, dest
, 4);
6230 /* move_block_from_reg will emit code to store the argument registers
6231 individually as scalar stores.
6233 However, other insns may later load from the same addresses for
6234 a structure load (passing a struct to a varargs routine).
6236 The alias code assumes that such aliasing can never happen, so we
6237 have to keep memory referencing insns from moving up beyond the
6238 last argument register store. So we emit a blockage insn here. */
6239 emit_insn (gen_blockage ());
6241 return copy_to_reg (expand_binop (Pmode
, add_optab
,
6242 crtl
->args
.internal_arg_pointer
,
6243 offset
, 0, 0, OPTAB_LIB_WIDEN
));
6247 hppa_va_start (tree valist
, rtx nextarg
)
6249 nextarg
= expand_builtin_saveregs ();
6250 std_expand_builtin_va_start (valist
, nextarg
);
6254 hppa_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6259 /* Args grow upward. We can use the generic routines. */
6260 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6262 else /* !TARGET_64BIT */
6264 tree ptr
= build_pointer_type (type
);
6267 unsigned int size
, ofs
;
6270 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
6274 ptr
= build_pointer_type (type
);
6276 size
= int_size_in_bytes (type
);
6277 valist_type
= TREE_TYPE (valist
);
6279 /* Args grow down. Not handled by generic routines. */
6281 u
= fold_convert (sizetype
, size_in_bytes (type
));
6282 u
= fold_build1 (NEGATE_EXPR
, sizetype
, u
);
6283 t
= fold_build_pointer_plus (valist
, u
);
6285 /* Align to 4 or 8 byte boundary depending on argument size. */
6287 u
= build_int_cst (TREE_TYPE (t
), (HOST_WIDE_INT
)(size
> 4 ? -8 : -4));
6288 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
, u
);
6289 t
= fold_convert (valist_type
, t
);
6291 t
= build2 (MODIFY_EXPR
, valist_type
, valist
, t
);
6293 ofs
= (8 - size
) % 4;
6295 t
= fold_build_pointer_plus_hwi (t
, ofs
);
6297 t
= fold_convert (ptr
, t
);
6298 t
= build_va_arg_indirect_ref (t
);
6301 t
= build_va_arg_indirect_ref (t
);
6307 /* True if MODE is valid for the target. By "valid", we mean able to
6308 be manipulated in non-trivial ways. In particular, this means all
6309 the arithmetic is supported.
6311 Currently, TImode is not valid as the HP 64-bit runtime documentation
6312 doesn't document the alignment and calling conventions for this type.
6313 Thus, we return false when PRECISION is 2 * BITS_PER_WORD and
6314 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */
6317 pa_scalar_mode_supported_p (enum machine_mode mode
)
6319 int precision
= GET_MODE_PRECISION (mode
);
6321 switch (GET_MODE_CLASS (mode
))
6323 case MODE_PARTIAL_INT
:
6325 if (precision
== CHAR_TYPE_SIZE
)
6327 if (precision
== SHORT_TYPE_SIZE
)
6329 if (precision
== INT_TYPE_SIZE
)
6331 if (precision
== LONG_TYPE_SIZE
)
6333 if (precision
== LONG_LONG_TYPE_SIZE
)
6338 if (precision
== FLOAT_TYPE_SIZE
)
6340 if (precision
== DOUBLE_TYPE_SIZE
)
6342 if (precision
== LONG_DOUBLE_TYPE_SIZE
)
6346 case MODE_DECIMAL_FLOAT
:
6354 /* Return TRUE if INSN, a jump insn, has an unfilled delay slot and
6355 it branches into the delay slot. Otherwise, return FALSE. */
6358 branch_to_delay_slot_p (rtx insn
)
6362 if (dbr_sequence_length ())
6365 jump_insn
= next_active_insn (JUMP_LABEL (insn
));
6368 insn
= next_active_insn (insn
);
6369 if (jump_insn
== insn
)
6372 /* We can't rely on the length of asms. So, we return FALSE when
6373 the branch is followed by an asm. */
6375 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
6376 || extract_asm_operands (PATTERN (insn
)) != NULL_RTX
6377 || get_attr_length (insn
) > 0)
6384 /* Return TRUE if INSN, a forward jump insn, needs a nop in its delay slot.
6386 This occurs when INSN has an unfilled delay slot and is followed
6387 by an asm. Disaster can occur if the asm is empty and the jump
6388 branches into the delay slot. So, we add a nop in the delay slot
6389 when this occurs. */
6392 branch_needs_nop_p (rtx insn
)
6396 if (dbr_sequence_length ())
6399 jump_insn
= next_active_insn (JUMP_LABEL (insn
));
6402 insn
= next_active_insn (insn
);
6403 if (!insn
|| jump_insn
== insn
)
6406 if (!(GET_CODE (PATTERN (insn
)) == ASM_INPUT
6407 || extract_asm_operands (PATTERN (insn
)) != NULL_RTX
)
6408 && get_attr_length (insn
) > 0)
6415 /* Return TRUE if INSN, a forward jump insn, can use nullification
6416 to skip the following instruction. This avoids an extra cycle due
6417 to a mis-predicted branch when we fall through. */
6420 use_skip_p (rtx insn
)
6422 rtx jump_insn
= next_active_insn (JUMP_LABEL (insn
));
6426 insn
= next_active_insn (insn
);
6428 /* We can't rely on the length of asms, so we can't skip asms. */
6430 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
6431 || extract_asm_operands (PATTERN (insn
)) != NULL_RTX
)
6433 if (get_attr_length (insn
) == 4
6434 && jump_insn
== next_active_insn (insn
))
6436 if (get_attr_length (insn
) > 0)
6443 /* This routine handles all the normal conditional branch sequences we
6444 might need to generate. It handles compare immediate vs compare
6445 register, nullification of delay slots, varying length branches,
6446 negated branches, and all combinations of the above. It returns the
6447 output appropriate to emit the branch corresponding to all given
6451 pa_output_cbranch (rtx
*operands
, int negated
, rtx insn
)
6453 static char buf
[100];
6455 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
6456 int length
= get_attr_length (insn
);
6459 /* A conditional branch to the following instruction (e.g. the delay slot)
6460 is asking for a disaster. This can happen when not optimizing and
6461 when jump optimization fails.
6463 While it is usually safe to emit nothing, this can fail if the
6464 preceding instruction is a nullified branch with an empty delay
6465 slot and the same branch target as this branch. We could check
6466 for this but jump optimization should eliminate nop jumps. It
6467 is always safe to emit a nop. */
6468 if (branch_to_delay_slot_p (insn
))
6471 /* The doubleword form of the cmpib instruction doesn't have the LEU
6472 and GTU conditions while the cmpb instruction does. Since we accept
6473 zero for cmpb, we must ensure that we use cmpb for the comparison. */
6474 if (GET_MODE (operands
[1]) == DImode
&& operands
[2] == const0_rtx
)
6475 operands
[2] = gen_rtx_REG (DImode
, 0);
6476 if (GET_MODE (operands
[2]) == DImode
&& operands
[1] == const0_rtx
)
6477 operands
[1] = gen_rtx_REG (DImode
, 0);
6479 /* If this is a long branch with its delay slot unfilled, set `nullify'
6480 as it can nullify the delay slot and save a nop. */
6481 if (length
== 8 && dbr_sequence_length () == 0)
6484 /* If this is a short forward conditional branch which did not get
6485 its delay slot filled, the delay slot can still be nullified. */
6486 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
6487 nullify
= forward_branch_p (insn
);
6489 /* A forward branch over a single nullified insn can be done with a
6490 comclr instruction. This avoids a single cycle penalty due to
6491 mis-predicted branch if we fall through (branch not taken). */
6492 useskip
= (length
== 4 && nullify
) ? use_skip_p (insn
) : FALSE
;
6496 /* All short conditional branches except backwards with an unfilled
6500 strcpy (buf
, "{com%I2clr,|cmp%I2clr,}");
6502 strcpy (buf
, "{com%I2b,|cmp%I2b,}");
6503 if (GET_MODE (operands
[1]) == DImode
)
6506 strcat (buf
, "%B3");
6508 strcat (buf
, "%S3");
6510 strcat (buf
, " %2,%r1,%%r0");
6513 if (branch_needs_nop_p (insn
))
6514 strcat (buf
, ",n %2,%r1,%0%#");
6516 strcat (buf
, ",n %2,%r1,%0");
6519 strcat (buf
, " %2,%r1,%0");
6522 /* All long conditionals. Note a short backward branch with an
6523 unfilled delay slot is treated just like a long backward branch
6524 with an unfilled delay slot. */
6526 /* Handle weird backwards branch with a filled delay slot
6527 which is nullified. */
6528 if (dbr_sequence_length () != 0
6529 && ! forward_branch_p (insn
)
6532 strcpy (buf
, "{com%I2b,|cmp%I2b,}");
6533 if (GET_MODE (operands
[1]) == DImode
)
6536 strcat (buf
, "%S3");
6538 strcat (buf
, "%B3");
6539 strcat (buf
, ",n %2,%r1,.+12\n\tb %0");
6541 /* Handle short backwards branch with an unfilled delay slot.
6542 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6543 taken and untaken branches. */
6544 else if (dbr_sequence_length () == 0
6545 && ! forward_branch_p (insn
)
6546 && INSN_ADDRESSES_SET_P ()
6547 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn
)))
6548 - INSN_ADDRESSES (INSN_UID (insn
)) - 8))
6550 strcpy (buf
, "{com%I2b,|cmp%I2b,}");
6551 if (GET_MODE (operands
[1]) == DImode
)
6554 strcat (buf
, "%B3 %2,%r1,%0%#");
6556 strcat (buf
, "%S3 %2,%r1,%0%#");
6560 strcpy (buf
, "{com%I2clr,|cmp%I2clr,}");
6561 if (GET_MODE (operands
[1]) == DImode
)
6564 strcat (buf
, "%S3");
6566 strcat (buf
, "%B3");
6568 strcat (buf
, " %2,%r1,%%r0\n\tb,n %0");
6570 strcat (buf
, " %2,%r1,%%r0\n\tb %0");
6575 /* The reversed conditional branch must branch over one additional
6576 instruction if the delay slot is filled and needs to be extracted
6577 by pa_output_lbranch. If the delay slot is empty or this is a
6578 nullified forward branch, the instruction after the reversed
6579 condition branch must be nullified. */
6580 if (dbr_sequence_length () == 0
6581 || (nullify
&& forward_branch_p (insn
)))
6585 operands
[4] = GEN_INT (length
);
6590 operands
[4] = GEN_INT (length
+ 4);
6593 /* Create a reversed conditional branch which branches around
6594 the following insns. */
6595 if (GET_MODE (operands
[1]) != DImode
)
6601 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6604 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6610 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6613 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6622 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6625 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6631 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6634 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6638 output_asm_insn (buf
, operands
);
6639 return pa_output_lbranch (operands
[0], insn
, xdelay
);
6644 /* This routine handles output of long unconditional branches that
6645 exceed the maximum range of a simple branch instruction. Since
6646 we don't have a register available for the branch, we save register
6647 %r1 in the frame marker, load the branch destination DEST into %r1,
6648 execute the branch, and restore %r1 in the delay slot of the branch.
6650 Since long branches may have an insn in the delay slot and the
6651 delay slot is used to restore %r1, we in general need to extract
6652 this insn and execute it before the branch. However, to facilitate
6653 use of this function by conditional branches, we also provide an
6654 option to not extract the delay insn so that it will be emitted
6655 after the long branch. So, if there is an insn in the delay slot,
6656 it is extracted if XDELAY is nonzero.
6658 The lengths of the various long-branch sequences are 20, 16 and 24
6659 bytes for the portable runtime, non-PIC and PIC cases, respectively. */
6662 pa_output_lbranch (rtx dest
, rtx insn
, int xdelay
)
6666 xoperands
[0] = dest
;
6668 /* First, free up the delay slot. */
6669 if (xdelay
&& dbr_sequence_length () != 0)
6671 /* We can't handle a jump in the delay slot. */
6672 gcc_assert (GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
);
6674 final_scan_insn (NEXT_INSN (insn
), asm_out_file
,
6677 /* Now delete the delay insn. */
6678 SET_INSN_DELETED (NEXT_INSN (insn
));
6681 /* Output an insn to save %r1. The runtime documentation doesn't
6682 specify whether the "Clean Up" slot in the callers frame can
6683 be clobbered by the callee. It isn't copied by HP's builtin
6684 alloca, so this suggests that it can be clobbered if necessary.
6685 The "Static Link" location is copied by HP builtin alloca, so
6686 we avoid using it. Using the cleanup slot might be a problem
6687 if we have to interoperate with languages that pass cleanup
6688 information. However, it should be possible to handle these
6689 situations with GCC's asm feature.
6691 The "Current RP" slot is reserved for the called procedure, so
6692 we try to use it when we don't have a frame of our own. It's
6693 rather unlikely that we won't have a frame when we need to emit
6696 Really the way to go long term is a register scavenger; goto
6697 the target of the jump and find a register which we can use
6698 as a scratch to hold the value in %r1. Then, we wouldn't have
6699 to free up the delay slot or clobber a slot that may be needed
6700 for other purposes. */
6703 if (actual_fsize
== 0 && !df_regs_ever_live_p (2))
6704 /* Use the return pointer slot in the frame marker. */
6705 output_asm_insn ("std %%r1,-16(%%r30)", xoperands
);
6707 /* Use the slot at -40 in the frame marker since HP builtin
6708 alloca doesn't copy it. */
6709 output_asm_insn ("std %%r1,-40(%%r30)", xoperands
);
6713 if (actual_fsize
== 0 && !df_regs_ever_live_p (2))
6714 /* Use the return pointer slot in the frame marker. */
6715 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands
);
6717 /* Use the "Clean Up" slot in the frame marker. In GCC,
6718 the only other use of this location is for copying a
6719 floating point double argument from a floating-point
6720 register to two general registers. The copy is done
6721 as an "atomic" operation when outputting a call, so it
6722 won't interfere with our using the location here. */
6723 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands
);
6726 if (TARGET_PORTABLE_RUNTIME
)
6728 output_asm_insn ("ldil L'%0,%%r1", xoperands
);
6729 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands
);
6730 output_asm_insn ("bv %%r0(%%r1)", xoperands
);
6734 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands
);
6735 if (TARGET_SOM
|| !TARGET_GAS
)
6737 xoperands
[1] = gen_label_rtx ();
6738 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands
);
6739 targetm
.asm_out
.internal_label (asm_out_file
, "L",
6740 CODE_LABEL_NUMBER (xoperands
[1]));
6741 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands
);
6745 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands
);
6746 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands
);
6748 output_asm_insn ("bv %%r0(%%r1)", xoperands
);
6751 /* Now output a very long branch to the original target. */
6752 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands
);
6754 /* Now restore the value of %r1 in the delay slot. */
6757 if (actual_fsize
== 0 && !df_regs_ever_live_p (2))
6758 return "ldd -16(%%r30),%%r1";
6760 return "ldd -40(%%r30),%%r1";
6764 if (actual_fsize
== 0 && !df_regs_ever_live_p (2))
6765 return "ldw -20(%%r30),%%r1";
6767 return "ldw -12(%%r30),%%r1";
6771 /* This routine handles all the branch-on-bit conditional branch sequences we
6772 might need to generate. It handles nullification of delay slots,
6773 varying length branches, negated branches and all combinations of the
6774 above. it returns the appropriate output template to emit the branch. */
6777 pa_output_bb (rtx
*operands ATTRIBUTE_UNUSED
, int negated
, rtx insn
, int which
)
6779 static char buf
[100];
6781 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
6782 int length
= get_attr_length (insn
);
6785 /* A conditional branch to the following instruction (e.g. the delay slot) is
6786 asking for a disaster. I do not think this can happen as this pattern
6787 is only used when optimizing; jump optimization should eliminate the
6788 jump. But be prepared just in case. */
6790 if (branch_to_delay_slot_p (insn
))
6793 /* If this is a long branch with its delay slot unfilled, set `nullify'
6794 as it can nullify the delay slot and save a nop. */
6795 if (length
== 8 && dbr_sequence_length () == 0)
6798 /* If this is a short forward conditional branch which did not get
6799 its delay slot filled, the delay slot can still be nullified. */
6800 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
6801 nullify
= forward_branch_p (insn
);
6803 /* A forward branch over a single nullified insn can be done with a
6804 extrs instruction. This avoids a single cycle penalty due to
6805 mis-predicted branch if we fall through (branch not taken). */
6806 useskip
= (length
== 4 && nullify
) ? use_skip_p (insn
) : FALSE
;
6811 /* All short conditional branches except backwards with an unfilled
6815 strcpy (buf
, "{extrs,|extrw,s,}");
6817 strcpy (buf
, "bb,");
6818 if (useskip
&& GET_MODE (operands
[0]) == DImode
)
6819 strcpy (buf
, "extrd,s,*");
6820 else if (GET_MODE (operands
[0]) == DImode
)
6821 strcpy (buf
, "bb,*");
6822 if ((which
== 0 && negated
)
6823 || (which
== 1 && ! negated
))
6828 strcat (buf
, " %0,%1,1,%%r0");
6829 else if (nullify
&& negated
)
6831 if (branch_needs_nop_p (insn
))
6832 strcat (buf
, ",n %0,%1,%3%#");
6834 strcat (buf
, ",n %0,%1,%3");
6836 else if (nullify
&& ! negated
)
6838 if (branch_needs_nop_p (insn
))
6839 strcat (buf
, ",n %0,%1,%2%#");
6841 strcat (buf
, ",n %0,%1,%2");
6843 else if (! nullify
&& negated
)
6844 strcat (buf
, " %0,%1,%3");
6845 else if (! nullify
&& ! negated
)
6846 strcat (buf
, " %0,%1,%2");
6849 /* All long conditionals. Note a short backward branch with an
6850 unfilled delay slot is treated just like a long backward branch
6851 with an unfilled delay slot. */
6853 /* Handle weird backwards branch with a filled delay slot
6854 which is nullified. */
6855 if (dbr_sequence_length () != 0
6856 && ! forward_branch_p (insn
)
6859 strcpy (buf
, "bb,");
6860 if (GET_MODE (operands
[0]) == DImode
)
6862 if ((which
== 0 && negated
)
6863 || (which
== 1 && ! negated
))
6868 strcat (buf
, ",n %0,%1,.+12\n\tb %3");
6870 strcat (buf
, ",n %0,%1,.+12\n\tb %2");
6872 /* Handle short backwards branch with an unfilled delay slot.
6873 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6874 taken and untaken branches. */
6875 else if (dbr_sequence_length () == 0
6876 && ! forward_branch_p (insn
)
6877 && INSN_ADDRESSES_SET_P ()
6878 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn
)))
6879 - INSN_ADDRESSES (INSN_UID (insn
)) - 8))
6881 strcpy (buf
, "bb,");
6882 if (GET_MODE (operands
[0]) == DImode
)
6884 if ((which
== 0 && negated
)
6885 || (which
== 1 && ! negated
))
6890 strcat (buf
, " %0,%1,%3%#");
6892 strcat (buf
, " %0,%1,%2%#");
6896 if (GET_MODE (operands
[0]) == DImode
)
6897 strcpy (buf
, "extrd,s,*");
6899 strcpy (buf
, "{extrs,|extrw,s,}");
6900 if ((which
== 0 && negated
)
6901 || (which
== 1 && ! negated
))
6905 if (nullify
&& negated
)
6906 strcat (buf
, " %0,%1,1,%%r0\n\tb,n %3");
6907 else if (nullify
&& ! negated
)
6908 strcat (buf
, " %0,%1,1,%%r0\n\tb,n %2");
6910 strcat (buf
, " %0,%1,1,%%r0\n\tb %3");
6912 strcat (buf
, " %0,%1,1,%%r0\n\tb %2");
6917 /* The reversed conditional branch must branch over one additional
6918 instruction if the delay slot is filled and needs to be extracted
6919 by pa_output_lbranch. If the delay slot is empty or this is a
6920 nullified forward branch, the instruction after the reversed
6921 condition branch must be nullified. */
6922 if (dbr_sequence_length () == 0
6923 || (nullify
&& forward_branch_p (insn
)))
6927 operands
[4] = GEN_INT (length
);
6932 operands
[4] = GEN_INT (length
+ 4);
6935 if (GET_MODE (operands
[0]) == DImode
)
6936 strcpy (buf
, "bb,*");
6938 strcpy (buf
, "bb,");
6939 if ((which
== 0 && negated
)
6940 || (which
== 1 && !negated
))
6945 strcat (buf
, ",n %0,%1,.+%4");
6947 strcat (buf
, " %0,%1,.+%4");
6948 output_asm_insn (buf
, operands
);
6949 return pa_output_lbranch (negated
? operands
[3] : operands
[2],
6955 /* This routine handles all the branch-on-variable-bit conditional branch
6956 sequences we might need to generate. It handles nullification of delay
6957 slots, varying length branches, negated branches and all combinations
6958 of the above. it returns the appropriate output template to emit the
6962 pa_output_bvb (rtx
*operands ATTRIBUTE_UNUSED
, int negated
, rtx insn
,
6965 static char buf
[100];
6967 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
6968 int length
= get_attr_length (insn
);
6971 /* A conditional branch to the following instruction (e.g. the delay slot) is
6972 asking for a disaster. I do not think this can happen as this pattern
6973 is only used when optimizing; jump optimization should eliminate the
6974 jump. But be prepared just in case. */
6976 if (branch_to_delay_slot_p (insn
))
6979 /* If this is a long branch with its delay slot unfilled, set `nullify'
6980 as it can nullify the delay slot and save a nop. */
6981 if (length
== 8 && dbr_sequence_length () == 0)
6984 /* If this is a short forward conditional branch which did not get
6985 its delay slot filled, the delay slot can still be nullified. */
6986 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
6987 nullify
= forward_branch_p (insn
);
6989 /* A forward branch over a single nullified insn can be done with a
6990 extrs instruction. This avoids a single cycle penalty due to
6991 mis-predicted branch if we fall through (branch not taken). */
6992 useskip
= (length
== 4 && nullify
) ? use_skip_p (insn
) : FALSE
;
6997 /* All short conditional branches except backwards with an unfilled
7001 strcpy (buf
, "{vextrs,|extrw,s,}");
7003 strcpy (buf
, "{bvb,|bb,}");
7004 if (useskip
&& GET_MODE (operands
[0]) == DImode
)
7005 strcpy (buf
, "extrd,s,*");
7006 else if (GET_MODE (operands
[0]) == DImode
)
7007 strcpy (buf
, "bb,*");
7008 if ((which
== 0 && negated
)
7009 || (which
== 1 && ! negated
))
7014 strcat (buf
, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
7015 else if (nullify
&& negated
)
7017 if (branch_needs_nop_p (insn
))
7018 strcat (buf
, "{,n %0,%3%#|,n %0,%%sar,%3%#}");
7020 strcat (buf
, "{,n %0,%3|,n %0,%%sar,%3}");
7022 else if (nullify
&& ! negated
)
7024 if (branch_needs_nop_p (insn
))
7025 strcat (buf
, "{,n %0,%2%#|,n %0,%%sar,%2%#}");
7027 strcat (buf
, "{,n %0,%2|,n %0,%%sar,%2}");
7029 else if (! nullify
&& negated
)
7030 strcat (buf
, "{ %0,%3| %0,%%sar,%3}");
7031 else if (! nullify
&& ! negated
)
7032 strcat (buf
, "{ %0,%2| %0,%%sar,%2}");
7035 /* All long conditionals. Note a short backward branch with an
7036 unfilled delay slot is treated just like a long backward branch
7037 with an unfilled delay slot. */
7039 /* Handle weird backwards branch with a filled delay slot
7040 which is nullified. */
7041 if (dbr_sequence_length () != 0
7042 && ! forward_branch_p (insn
)
7045 strcpy (buf
, "{bvb,|bb,}");
7046 if (GET_MODE (operands
[0]) == DImode
)
7048 if ((which
== 0 && negated
)
7049 || (which
== 1 && ! negated
))
7054 strcat (buf
, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
7056 strcat (buf
, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
7058 /* Handle short backwards branch with an unfilled delay slot.
7059 Using a bb;nop rather than extrs;bl saves 1 cycle for both
7060 taken and untaken branches. */
7061 else if (dbr_sequence_length () == 0
7062 && ! forward_branch_p (insn
)
7063 && INSN_ADDRESSES_SET_P ()
7064 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn
)))
7065 - INSN_ADDRESSES (INSN_UID (insn
)) - 8))
7067 strcpy (buf
, "{bvb,|bb,}");
7068 if (GET_MODE (operands
[0]) == DImode
)
7070 if ((which
== 0 && negated
)
7071 || (which
== 1 && ! negated
))
7076 strcat (buf
, "{ %0,%3%#| %0,%%sar,%3%#}");
7078 strcat (buf
, "{ %0,%2%#| %0,%%sar,%2%#}");
7082 strcpy (buf
, "{vextrs,|extrw,s,}");
7083 if (GET_MODE (operands
[0]) == DImode
)
7084 strcpy (buf
, "extrd,s,*");
7085 if ((which
== 0 && negated
)
7086 || (which
== 1 && ! negated
))
7090 if (nullify
&& negated
)
7091 strcat (buf
, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
7092 else if (nullify
&& ! negated
)
7093 strcat (buf
, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
7095 strcat (buf
, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
7097 strcat (buf
, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
7102 /* The reversed conditional branch must branch over one additional
7103 instruction if the delay slot is filled and needs to be extracted
7104 by pa_output_lbranch. If the delay slot is empty or this is a
7105 nullified forward branch, the instruction after the reversed
7106 condition branch must be nullified. */
7107 if (dbr_sequence_length () == 0
7108 || (nullify
&& forward_branch_p (insn
)))
7112 operands
[4] = GEN_INT (length
);
7117 operands
[4] = GEN_INT (length
+ 4);
7120 if (GET_MODE (operands
[0]) == DImode
)
7121 strcpy (buf
, "bb,*");
7123 strcpy (buf
, "{bvb,|bb,}");
7124 if ((which
== 0 && negated
)
7125 || (which
== 1 && !negated
))
7130 strcat (buf
, ",n {%0,.+%4|%0,%%sar,.+%4}");
7132 strcat (buf
, " {%0,.+%4|%0,%%sar,.+%4}");
7133 output_asm_insn (buf
, operands
);
7134 return pa_output_lbranch (negated
? operands
[3] : operands
[2],
7140 /* Return the output template for emitting a dbra type insn.
7142 Note it may perform some output operations on its own before
7143 returning the final output string. */
7145 pa_output_dbra (rtx
*operands
, rtx insn
, int which_alternative
)
7147 int length
= get_attr_length (insn
);
7149 /* A conditional branch to the following instruction (e.g. the delay slot) is
7150 asking for a disaster. Be prepared! */
7152 if (branch_to_delay_slot_p (insn
))
7154 if (which_alternative
== 0)
7155 return "ldo %1(%0),%0";
7156 else if (which_alternative
== 1)
7158 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands
);
7159 output_asm_insn ("ldw -16(%%r30),%4", operands
);
7160 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands
);
7161 return "{fldws|fldw} -16(%%r30),%0";
7165 output_asm_insn ("ldw %0,%4", operands
);
7166 return "ldo %1(%4),%4\n\tstw %4,%0";
7170 if (which_alternative
== 0)
7172 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
7175 /* If this is a long branch with its delay slot unfilled, set `nullify'
7176 as it can nullify the delay slot and save a nop. */
7177 if (length
== 8 && dbr_sequence_length () == 0)
7180 /* If this is a short forward conditional branch which did not get
7181 its delay slot filled, the delay slot can still be nullified. */
7182 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
7183 nullify
= forward_branch_p (insn
);
7190 if (branch_needs_nop_p (insn
))
7191 return "addib,%C2,n %1,%0,%3%#";
7193 return "addib,%C2,n %1,%0,%3";
7196 return "addib,%C2 %1,%0,%3";
7199 /* Handle weird backwards branch with a fulled delay slot
7200 which is nullified. */
7201 if (dbr_sequence_length () != 0
7202 && ! forward_branch_p (insn
)
7204 return "addib,%N2,n %1,%0,.+12\n\tb %3";
7205 /* Handle short backwards branch with an unfilled delay slot.
7206 Using a addb;nop rather than addi;bl saves 1 cycle for both
7207 taken and untaken branches. */
7208 else if (dbr_sequence_length () == 0
7209 && ! forward_branch_p (insn
)
7210 && INSN_ADDRESSES_SET_P ()
7211 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn
)))
7212 - INSN_ADDRESSES (INSN_UID (insn
)) - 8))
7213 return "addib,%C2 %1,%0,%3%#";
7215 /* Handle normal cases. */
7217 return "addi,%N2 %1,%0,%0\n\tb,n %3";
7219 return "addi,%N2 %1,%0,%0\n\tb %3";
7222 /* The reversed conditional branch must branch over one additional
7223 instruction if the delay slot is filled and needs to be extracted
7224 by pa_output_lbranch. If the delay slot is empty or this is a
7225 nullified forward branch, the instruction after the reversed
7226 condition branch must be nullified. */
7227 if (dbr_sequence_length () == 0
7228 || (nullify
&& forward_branch_p (insn
)))
7232 operands
[4] = GEN_INT (length
);
7237 operands
[4] = GEN_INT (length
+ 4);
7241 output_asm_insn ("addib,%N2,n %1,%0,.+%4", operands
);
7243 output_asm_insn ("addib,%N2 %1,%0,.+%4", operands
);
7245 return pa_output_lbranch (operands
[3], insn
, xdelay
);
7249 /* Deal with gross reload from FP register case. */
7250 else if (which_alternative
== 1)
7252 /* Move loop counter from FP register to MEM then into a GR,
7253 increment the GR, store the GR into MEM, and finally reload
7254 the FP register from MEM from within the branch's delay slot. */
7255 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
7257 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands
);
7259 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
7260 else if (length
== 28)
7261 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
7264 operands
[5] = GEN_INT (length
- 16);
7265 output_asm_insn ("{comb|cmpb},%B2 %%r0,%4,.+%5", operands
);
7266 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands
);
7267 return pa_output_lbranch (operands
[3], insn
, 0);
7270 /* Deal with gross reload from memory case. */
7273 /* Reload loop counter from memory, the store back to memory
7274 happens in the branch's delay slot. */
7275 output_asm_insn ("ldw %0,%4", operands
);
7277 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
7278 else if (length
== 16)
7279 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
7282 operands
[5] = GEN_INT (length
- 4);
7283 output_asm_insn ("addib,%N2 %1,%4,.+%5\n\tstw %4,%0", operands
);
7284 return pa_output_lbranch (operands
[3], insn
, 0);
7289 /* Return the output template for emitting a movb type insn.
7291 Note it may perform some output operations on its own before
7292 returning the final output string. */
7294 pa_output_movb (rtx
*operands
, rtx insn
, int which_alternative
,
7295 int reverse_comparison
)
7297 int length
= get_attr_length (insn
);
7299 /* A conditional branch to the following instruction (e.g. the delay slot) is
7300 asking for a disaster. Be prepared! */
7302 if (branch_to_delay_slot_p (insn
))
7304 if (which_alternative
== 0)
7305 return "copy %1,%0";
7306 else if (which_alternative
== 1)
7308 output_asm_insn ("stw %1,-16(%%r30)", operands
);
7309 return "{fldws|fldw} -16(%%r30),%0";
7311 else if (which_alternative
== 2)
7317 /* Support the second variant. */
7318 if (reverse_comparison
)
7319 PUT_CODE (operands
[2], reverse_condition (GET_CODE (operands
[2])));
7321 if (which_alternative
== 0)
7323 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
7326 /* If this is a long branch with its delay slot unfilled, set `nullify'
7327 as it can nullify the delay slot and save a nop. */
7328 if (length
== 8 && dbr_sequence_length () == 0)
7331 /* If this is a short forward conditional branch which did not get
7332 its delay slot filled, the delay slot can still be nullified. */
7333 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
7334 nullify
= forward_branch_p (insn
);
7341 if (branch_needs_nop_p (insn
))
7342 return "movb,%C2,n %1,%0,%3%#";
7344 return "movb,%C2,n %1,%0,%3";
7347 return "movb,%C2 %1,%0,%3";
7350 /* Handle weird backwards branch with a filled delay slot
7351 which is nullified. */
7352 if (dbr_sequence_length () != 0
7353 && ! forward_branch_p (insn
)
7355 return "movb,%N2,n %1,%0,.+12\n\tb %3";
7357 /* Handle short backwards branch with an unfilled delay slot.
7358 Using a movb;nop rather than or;bl saves 1 cycle for both
7359 taken and untaken branches. */
7360 else if (dbr_sequence_length () == 0
7361 && ! forward_branch_p (insn
)
7362 && INSN_ADDRESSES_SET_P ()
7363 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn
)))
7364 - INSN_ADDRESSES (INSN_UID (insn
)) - 8))
7365 return "movb,%C2 %1,%0,%3%#";
7366 /* Handle normal cases. */
7368 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
7370 return "or,%N2 %1,%%r0,%0\n\tb %3";
7373 /* The reversed conditional branch must branch over one additional
7374 instruction if the delay slot is filled and needs to be extracted
7375 by pa_output_lbranch. If the delay slot is empty or this is a
7376 nullified forward branch, the instruction after the reversed
7377 condition branch must be nullified. */
7378 if (dbr_sequence_length () == 0
7379 || (nullify
&& forward_branch_p (insn
)))
7383 operands
[4] = GEN_INT (length
);
7388 operands
[4] = GEN_INT (length
+ 4);
7392 output_asm_insn ("movb,%N2,n %1,%0,.+%4", operands
);
7394 output_asm_insn ("movb,%N2 %1,%0,.+%4", operands
);
7396 return pa_output_lbranch (operands
[3], insn
, xdelay
);
7399 /* Deal with gross reload for FP destination register case. */
7400 else if (which_alternative
== 1)
7402 /* Move source register to MEM, perform the branch test, then
7403 finally load the FP register from MEM from within the branch's
7405 output_asm_insn ("stw %1,-16(%%r30)", operands
);
7407 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
7408 else if (length
== 16)
7409 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
7412 operands
[4] = GEN_INT (length
- 4);
7413 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4", operands
);
7414 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands
);
7415 return pa_output_lbranch (operands
[3], insn
, 0);
7418 /* Deal with gross reload from memory case. */
7419 else if (which_alternative
== 2)
7421 /* Reload loop counter from memory, the store back to memory
7422 happens in the branch's delay slot. */
7424 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
7425 else if (length
== 12)
7426 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
7429 operands
[4] = GEN_INT (length
);
7430 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tstw %1,%0",
7432 return pa_output_lbranch (operands
[3], insn
, 0);
7435 /* Handle SAR as a destination. */
7439 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
7440 else if (length
== 12)
7441 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
7444 operands
[4] = GEN_INT (length
);
7445 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tmtsar %r1",
7447 return pa_output_lbranch (operands
[3], insn
, 0);
7452 /* Copy any FP arguments in INSN into integer registers. */
7454 copy_fp_args (rtx insn
)
7459 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
7461 int arg_mode
, regno
;
7462 rtx use
= XEXP (link
, 0);
7464 if (! (GET_CODE (use
) == USE
7465 && GET_CODE (XEXP (use
, 0)) == REG
7466 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use
, 0)))))
7469 arg_mode
= GET_MODE (XEXP (use
, 0));
7470 regno
= REGNO (XEXP (use
, 0));
7472 /* Is it a floating point register? */
7473 if (regno
>= 32 && regno
<= 39)
7475 /* Copy the FP register into an integer register via memory. */
7476 if (arg_mode
== SFmode
)
7478 xoperands
[0] = XEXP (use
, 0);
7479 xoperands
[1] = gen_rtx_REG (SImode
, 26 - (regno
- 32) / 2);
7480 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands
);
7481 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands
);
7485 xoperands
[0] = XEXP (use
, 0);
7486 xoperands
[1] = gen_rtx_REG (DImode
, 25 - (regno
- 34) / 2);
7487 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands
);
7488 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands
);
7489 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands
);
7495 /* Compute length of the FP argument copy sequence for INSN. */
7497 length_fp_args (rtx insn
)
7502 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
7504 int arg_mode
, regno
;
7505 rtx use
= XEXP (link
, 0);
7507 if (! (GET_CODE (use
) == USE
7508 && GET_CODE (XEXP (use
, 0)) == REG
7509 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use
, 0)))))
7512 arg_mode
= GET_MODE (XEXP (use
, 0));
7513 regno
= REGNO (XEXP (use
, 0));
7515 /* Is it a floating point register? */
7516 if (regno
>= 32 && regno
<= 39)
7518 if (arg_mode
== SFmode
)
7528 /* Return the attribute length for the millicode call instruction INSN.
7529 The length must match the code generated by pa_output_millicode_call.
7530 We include the delay slot in the returned length as it is better to
7531 over estimate the length than to under estimate it. */
7534 pa_attr_length_millicode_call (rtx insn
)
7536 unsigned long distance
= -1;
7537 unsigned long total
= IN_NAMED_SECTION_P (cfun
->decl
) ? 0 : total_code_bytes
;
7539 if (INSN_ADDRESSES_SET_P ())
7541 distance
= (total
+ insn_current_reference_address (insn
));
7542 if (distance
< total
)
7548 if (!TARGET_LONG_CALLS
&& distance
< 7600000)
7553 else if (TARGET_PORTABLE_RUNTIME
)
7557 if (!TARGET_LONG_CALLS
&& distance
< MAX_PCREL17F_OFFSET
)
7567 /* INSN is a function call. It may have an unconditional jump
7570 CALL_DEST is the routine we are calling. */
7573 pa_output_millicode_call (rtx insn
, rtx call_dest
)
7575 int attr_length
= get_attr_length (insn
);
7576 int seq_length
= dbr_sequence_length ();
7581 xoperands
[0] = call_dest
;
7582 xoperands
[2] = gen_rtx_REG (Pmode
, TARGET_64BIT
? 2 : 31);
7584 /* Handle the common case where we are sure that the branch will
7585 reach the beginning of the $CODE$ subspace. The within reach
7586 form of the $$sh_func_adrs call has a length of 28. Because it
7587 has an attribute type of sh_func_adrs, it never has a nonzero
7588 sequence length (i.e., the delay slot is never filled). */
7589 if (!TARGET_LONG_CALLS
7590 && (attr_length
== 8
7591 || (attr_length
== 28
7592 && get_attr_type (insn
) == TYPE_SH_FUNC_ADRS
)))
7594 output_asm_insn ("{bl|b,l} %0,%2", xoperands
);
7600 /* It might seem that one insn could be saved by accessing
7601 the millicode function using the linkage table. However,
7602 this doesn't work in shared libraries and other dynamically
7603 loaded objects. Using a pc-relative sequence also avoids
7604 problems related to the implicit use of the gp register. */
7605 output_asm_insn ("b,l .+8,%%r1", xoperands
);
7609 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands
);
7610 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands
);
7614 xoperands
[1] = gen_label_rtx ();
7615 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands
);
7616 targetm
.asm_out
.internal_label (asm_out_file
, "L",
7617 CODE_LABEL_NUMBER (xoperands
[1]));
7618 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands
);
7621 output_asm_insn ("bve,l (%%r1),%%r2", xoperands
);
7623 else if (TARGET_PORTABLE_RUNTIME
)
7625 /* Pure portable runtime doesn't allow be/ble; we also don't
7626 have PIC support in the assembler/linker, so this sequence
7629 /* Get the address of our target into %r1. */
7630 output_asm_insn ("ldil L'%0,%%r1", xoperands
);
7631 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands
);
7633 /* Get our return address into %r31. */
7634 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands
);
7635 output_asm_insn ("addi 8,%%r31,%%r31", xoperands
);
7637 /* Jump to our target address in %r1. */
7638 output_asm_insn ("bv %%r0(%%r1)", xoperands
);
7642 output_asm_insn ("ldil L'%0,%%r1", xoperands
);
7644 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands
);
7646 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands
);
7650 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands
);
7651 output_asm_insn ("addi 16,%%r1,%%r31", xoperands
);
7653 if (TARGET_SOM
|| !TARGET_GAS
)
7655 /* The HP assembler can generate relocations for the
7656 difference of two symbols. GAS can do this for a
7657 millicode symbol but not an arbitrary external
7658 symbol when generating SOM output. */
7659 xoperands
[1] = gen_label_rtx ();
7660 targetm
.asm_out
.internal_label (asm_out_file
, "L",
7661 CODE_LABEL_NUMBER (xoperands
[1]));
7662 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands
);
7663 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands
);
7667 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands
);
7668 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
7672 /* Jump to our target address in %r1. */
7673 output_asm_insn ("bv %%r0(%%r1)", xoperands
);
7677 if (seq_length
== 0)
7678 output_asm_insn ("nop", xoperands
);
7680 /* We are done if there isn't a jump in the delay slot. */
7681 if (seq_length
== 0 || GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
)
7684 /* This call has an unconditional jump in its delay slot. */
7685 xoperands
[0] = XEXP (PATTERN (NEXT_INSN (insn
)), 1);
7687 /* See if the return address can be adjusted. Use the containing
7688 sequence insn's address. */
7689 if (INSN_ADDRESSES_SET_P ())
7691 seq_insn
= NEXT_INSN (PREV_INSN (XVECEXP (final_sequence
, 0, 0)));
7692 distance
= (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn
))))
7693 - INSN_ADDRESSES (INSN_UID (seq_insn
)) - 8);
7695 if (VAL_14_BITS_P (distance
))
7697 xoperands
[1] = gen_label_rtx ();
7698 output_asm_insn ("ldo %0-%1(%2),%2", xoperands
);
7699 targetm
.asm_out
.internal_label (asm_out_file
, "L",
7700 CODE_LABEL_NUMBER (xoperands
[1]));
7703 /* ??? This branch may not reach its target. */
7704 output_asm_insn ("nop\n\tb,n %0", xoperands
);
7707 /* ??? This branch may not reach its target. */
7708 output_asm_insn ("nop\n\tb,n %0", xoperands
);
7710 /* Delete the jump. */
7711 SET_INSN_DELETED (NEXT_INSN (insn
));
7716 /* Return the attribute length of the call instruction INSN. The SIBCALL
7717 flag indicates whether INSN is a regular call or a sibling call. The
7718 length returned must be longer than the code actually generated by
7719 pa_output_call. Since branch shortening is done before delay branch
7720 sequencing, there is no way to determine whether or not the delay
7721 slot will be filled during branch shortening. Even when the delay
7722 slot is filled, we may have to add a nop if the delay slot contains
7723 a branch that can't reach its target. Thus, we always have to include
7724 the delay slot in the length estimate. This used to be done in
7725 pa_adjust_insn_length but we do it here now as some sequences always
7726 fill the delay slot and we can save four bytes in the estimate for
7730 pa_attr_length_call (rtx insn
, int sibcall
)
7733 rtx call
, call_dest
;
7736 rtx pat
= PATTERN (insn
);
7737 unsigned long distance
= -1;
7739 gcc_assert (GET_CODE (insn
) == CALL_INSN
);
7741 if (INSN_ADDRESSES_SET_P ())
7743 unsigned long total
;
7745 total
= IN_NAMED_SECTION_P (cfun
->decl
) ? 0 : total_code_bytes
;
7746 distance
= (total
+ insn_current_reference_address (insn
));
7747 if (distance
< total
)
7751 gcc_assert (GET_CODE (pat
) == PARALLEL
);
7753 /* Get the call rtx. */
7754 call
= XVECEXP (pat
, 0, 0);
7755 if (GET_CODE (call
) == SET
)
7756 call
= SET_SRC (call
);
7758 gcc_assert (GET_CODE (call
) == CALL
);
7760 /* Determine if this is a local call. */
7761 call_dest
= XEXP (XEXP (call
, 0), 0);
7762 call_decl
= SYMBOL_REF_DECL (call_dest
);
7763 local_call
= call_decl
&& targetm
.binds_local_p (call_decl
);
7765 /* pc-relative branch. */
7766 if (!TARGET_LONG_CALLS
7767 && ((TARGET_PA_20
&& !sibcall
&& distance
< 7600000)
7768 || distance
< MAX_PCREL17F_OFFSET
))
7771 /* 64-bit plabel sequence. */
7772 else if (TARGET_64BIT
&& !local_call
)
7773 length
+= sibcall
? 28 : 24;
7775 /* non-pic long absolute branch sequence. */
7776 else if ((TARGET_LONG_ABS_CALL
|| local_call
) && !flag_pic
)
7779 /* long pc-relative branch sequence. */
7780 else if (TARGET_LONG_PIC_SDIFF_CALL
7781 || (TARGET_GAS
&& !TARGET_SOM
7782 && (TARGET_LONG_PIC_PCREL_CALL
|| local_call
)))
7786 if (!TARGET_PA_20
&& !TARGET_NO_SPACE_REGS
&& (!local_call
|| flag_pic
))
7790 /* 32-bit plabel sequence. */
7796 length
+= length_fp_args (insn
);
7806 if (!TARGET_NO_SPACE_REGS
&& (!local_call
|| flag_pic
))
7814 /* INSN is a function call. It may have an unconditional jump
7817 CALL_DEST is the routine we are calling. */
7820 pa_output_call (rtx insn
, rtx call_dest
, int sibcall
)
7822 int delay_insn_deleted
= 0;
7823 int delay_slot_filled
= 0;
7824 int seq_length
= dbr_sequence_length ();
7825 tree call_decl
= SYMBOL_REF_DECL (call_dest
);
7826 int local_call
= call_decl
&& targetm
.binds_local_p (call_decl
);
7829 xoperands
[0] = call_dest
;
7831 /* Handle the common case where we're sure that the branch will reach
7832 the beginning of the "$CODE$" subspace. This is the beginning of
7833 the current function if we are in a named section. */
7834 if (!TARGET_LONG_CALLS
&& pa_attr_length_call (insn
, sibcall
) == 8)
7836 xoperands
[1] = gen_rtx_REG (word_mode
, sibcall
? 0 : 2);
7837 output_asm_insn ("{bl|b,l} %0,%1", xoperands
);
7841 if (TARGET_64BIT
&& !local_call
)
7843 /* ??? As far as I can tell, the HP linker doesn't support the
7844 long pc-relative sequence described in the 64-bit runtime
7845 architecture. So, we use a slightly longer indirect call. */
7846 xoperands
[0] = pa_get_deferred_plabel (call_dest
);
7847 xoperands
[1] = gen_label_rtx ();
7849 /* If this isn't a sibcall, we put the load of %r27 into the
7850 delay slot. We can't do this in a sibcall as we don't
7851 have a second call-clobbered scratch register available. */
7853 && GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
7856 final_scan_insn (NEXT_INSN (insn
), asm_out_file
,
7859 /* Now delete the delay insn. */
7860 SET_INSN_DELETED (NEXT_INSN (insn
));
7861 delay_insn_deleted
= 1;
7864 output_asm_insn ("addil LT'%0,%%r27", xoperands
);
7865 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands
);
7866 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands
);
7870 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands
);
7871 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands
);
7872 output_asm_insn ("bve (%%r1)", xoperands
);
7876 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands
);
7877 output_asm_insn ("bve,l (%%r2),%%r2", xoperands
);
7878 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands
);
7879 delay_slot_filled
= 1;
7884 int indirect_call
= 0;
7886 /* Emit a long call. There are several different sequences
7887 of increasing length and complexity. In most cases,
7888 they don't allow an instruction in the delay slot. */
7889 if (!((TARGET_LONG_ABS_CALL
|| local_call
) && !flag_pic
)
7890 && !TARGET_LONG_PIC_SDIFF_CALL
7891 && !(TARGET_GAS
&& !TARGET_SOM
7892 && (TARGET_LONG_PIC_PCREL_CALL
|| local_call
))
7897 && GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
7901 || ((TARGET_LONG_ABS_CALL
|| local_call
) && !flag_pic
)))
7903 /* A non-jump insn in the delay slot. By definition we can
7904 emit this insn before the call (and in fact before argument
7906 final_scan_insn (NEXT_INSN (insn
), asm_out_file
, optimize
, 0,
7909 /* Now delete the delay insn. */
7910 SET_INSN_DELETED (NEXT_INSN (insn
));
7911 delay_insn_deleted
= 1;
7914 if ((TARGET_LONG_ABS_CALL
|| local_call
) && !flag_pic
)
7916 /* This is the best sequence for making long calls in
7917 non-pic code. Unfortunately, GNU ld doesn't provide
7918 the stub needed for external calls, and GAS's support
7919 for this with the SOM linker is buggy. It is safe
7920 to use this for local calls. */
7921 output_asm_insn ("ldil L'%0,%%r1", xoperands
);
7923 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands
);
7927 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7930 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands
);
7932 output_asm_insn ("copy %%r31,%%r2", xoperands
);
7933 delay_slot_filled
= 1;
7938 if (TARGET_LONG_PIC_SDIFF_CALL
)
7940 /* The HP assembler and linker can handle relocations
7941 for the difference of two symbols. The HP assembler
7942 recognizes the sequence as a pc-relative call and
7943 the linker provides stubs when needed. */
7944 xoperands
[1] = gen_label_rtx ();
7945 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands
);
7946 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands
);
7947 targetm
.asm_out
.internal_label (asm_out_file
, "L",
7948 CODE_LABEL_NUMBER (xoperands
[1]));
7949 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands
);
7951 else if (TARGET_GAS
&& !TARGET_SOM
7952 && (TARGET_LONG_PIC_PCREL_CALL
|| local_call
))
7954 /* GAS currently can't generate the relocations that
7955 are needed for the SOM linker under HP-UX using this
7956 sequence. The GNU linker doesn't generate the stubs
7957 that are needed for external calls on TARGET_ELF32
7958 with this sequence. For now, we have to use a
7959 longer plabel sequence when using GAS. */
7960 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands
);
7961 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7963 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7968 /* Emit a long plabel-based call sequence. This is
7969 essentially an inline implementation of $$dyncall.
7970 We don't actually try to call $$dyncall as this is
7971 as difficult as calling the function itself. */
7972 xoperands
[0] = pa_get_deferred_plabel (call_dest
);
7973 xoperands
[1] = gen_label_rtx ();
7975 /* Since the call is indirect, FP arguments in registers
7976 need to be copied to the general registers. Then, the
7977 argument relocation stub will copy them back. */
7979 copy_fp_args (insn
);
7983 output_asm_insn ("addil LT'%0,%%r19", xoperands
);
7984 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands
);
7985 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands
);
7989 output_asm_insn ("addil LR'%0-$global$,%%r27",
7991 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7995 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands
);
7996 output_asm_insn ("depi 0,31,2,%%r1", xoperands
);
7997 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands
);
7998 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands
);
8000 if (!sibcall
&& !TARGET_PA_20
)
8002 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands
);
8003 if (TARGET_NO_SPACE_REGS
|| (local_call
&& !flag_pic
))
8004 output_asm_insn ("addi 8,%%r2,%%r2", xoperands
);
8006 output_asm_insn ("addi 16,%%r2,%%r2", xoperands
);
8013 output_asm_insn ("bve (%%r1)", xoperands
);
8018 output_asm_insn ("bve,l (%%r1),%%r2", xoperands
);
8019 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands
);
8020 delay_slot_filled
= 1;
8023 output_asm_insn ("bve,l (%%r1),%%r2", xoperands
);
8028 if (!TARGET_NO_SPACE_REGS
&& (!local_call
|| flag_pic
))
8029 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
8034 if (TARGET_NO_SPACE_REGS
|| (local_call
&& !flag_pic
))
8035 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands
);
8037 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands
);
8041 if (TARGET_NO_SPACE_REGS
|| (local_call
&& !flag_pic
))
8042 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands
);
8044 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands
);
8047 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands
);
8049 output_asm_insn ("copy %%r31,%%r2", xoperands
);
8050 delay_slot_filled
= 1;
8057 if (!delay_slot_filled
&& (seq_length
== 0 || delay_insn_deleted
))
8058 output_asm_insn ("nop", xoperands
);
8060 /* We are done if there isn't a jump in the delay slot. */
8062 || delay_insn_deleted
8063 || GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
)
8066 /* A sibcall should never have a branch in the delay slot. */
8067 gcc_assert (!sibcall
);
8069 /* This call has an unconditional jump in its delay slot. */
8070 xoperands
[0] = XEXP (PATTERN (NEXT_INSN (insn
)), 1);
8072 if (!delay_slot_filled
&& INSN_ADDRESSES_SET_P ())
8074 /* See if the return address can be adjusted. Use the containing
8075 sequence insn's address. This would break the regular call/return@
8076 relationship assumed by the table based eh unwinder, so only do that
8077 if the call is not possibly throwing. */
8078 rtx seq_insn
= NEXT_INSN (PREV_INSN (XVECEXP (final_sequence
, 0, 0)));
8079 int distance
= (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn
))))
8080 - INSN_ADDRESSES (INSN_UID (seq_insn
)) - 8);
8082 if (VAL_14_BITS_P (distance
)
8083 && !(can_throw_internal (insn
) || can_throw_external (insn
)))
8085 xoperands
[1] = gen_label_rtx ();
8086 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands
);
8087 targetm
.asm_out
.internal_label (asm_out_file
, "L",
8088 CODE_LABEL_NUMBER (xoperands
[1]));
8091 output_asm_insn ("nop\n\tb,n %0", xoperands
);
8094 output_asm_insn ("b,n %0", xoperands
);
8096 /* Delete the jump. */
8097 SET_INSN_DELETED (NEXT_INSN (insn
));
8102 /* Return the attribute length of the indirect call instruction INSN.
8103 The length must match the code generated by output_indirect call.
8104 The returned length includes the delay slot. Currently, the delay
8105 slot of an indirect call sequence is not exposed and it is used by
8106 the sequence itself. */
8109 pa_attr_length_indirect_call (rtx insn
)
8111 unsigned long distance
= -1;
8112 unsigned long total
= IN_NAMED_SECTION_P (cfun
->decl
) ? 0 : total_code_bytes
;
8114 if (INSN_ADDRESSES_SET_P ())
8116 distance
= (total
+ insn_current_reference_address (insn
));
8117 if (distance
< total
)
8124 if (TARGET_FAST_INDIRECT_CALLS
8125 || (!TARGET_LONG_CALLS
8126 && !TARGET_PORTABLE_RUNTIME
8127 && ((TARGET_PA_20
&& !TARGET_SOM
&& distance
< 7600000)
8128 || distance
< MAX_PCREL17F_OFFSET
)))
8134 if (TARGET_PORTABLE_RUNTIME
)
8137 /* Out of reach, can use ble. */
8142 pa_output_indirect_call (rtx insn
, rtx call_dest
)
8148 xoperands
[0] = call_dest
;
8149 output_asm_insn ("ldd 16(%0),%%r2", xoperands
);
8150 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands
);
8154 /* First the special case for kernels, level 0 systems, etc. */
8155 if (TARGET_FAST_INDIRECT_CALLS
)
8156 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
8158 /* Now the normal case -- we can reach $$dyncall directly or
8159 we're sure that we can get there via a long-branch stub.
8161 No need to check target flags as the length uniquely identifies
8162 the remaining cases. */
8163 if (pa_attr_length_indirect_call (insn
) == 8)
8165 /* The HP linker sometimes substitutes a BLE for BL/B,L calls to
8166 $$dyncall. Since BLE uses %r31 as the link register, the 22-bit
8167 variant of the B,L instruction can't be used on the SOM target. */
8168 if (TARGET_PA_20
&& !TARGET_SOM
)
8169 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
8171 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
8174 /* Long millicode call, but we are not generating PIC or portable runtime
8176 if (pa_attr_length_indirect_call (insn
) == 12)
8177 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
8179 /* Long millicode call for portable runtime. */
8180 if (pa_attr_length_indirect_call (insn
) == 20)
8181 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
8183 /* We need a long PIC call to $$dyncall. */
8184 xoperands
[0] = NULL_RTX
;
8185 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands
);
8186 if (TARGET_SOM
|| !TARGET_GAS
)
8188 xoperands
[0] = gen_label_rtx ();
8189 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands
);
8190 targetm
.asm_out
.internal_label (asm_out_file
, "L",
8191 CODE_LABEL_NUMBER (xoperands
[0]));
8192 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands
);
8196 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands
);
8197 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
8200 output_asm_insn ("blr %%r0,%%r2", xoperands
);
8201 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands
);
8205 /* In HPUX 8.0's shared library scheme, special relocations are needed
8206 for function labels if they might be passed to a function
8207 in a shared library (because shared libraries don't live in code
8208 space), and special magic is needed to construct their address. */
8211 pa_encode_label (rtx sym
)
8213 const char *str
= XSTR (sym
, 0);
8214 int len
= strlen (str
) + 1;
8217 p
= newstr
= XALLOCAVEC (char, len
+ 1);
8221 XSTR (sym
, 0) = ggc_alloc_string (newstr
, len
);
8225 pa_encode_section_info (tree decl
, rtx rtl
, int first
)
8227 int old_referenced
= 0;
8229 if (!first
&& MEM_P (rtl
) && GET_CODE (XEXP (rtl
, 0)) == SYMBOL_REF
)
8231 = SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) & SYMBOL_FLAG_REFERENCED
;
8233 default_encode_section_info (decl
, rtl
, first
);
8235 if (first
&& TEXT_SPACE_P (decl
))
8237 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
8238 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8239 pa_encode_label (XEXP (rtl
, 0));
8241 else if (old_referenced
)
8242 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= old_referenced
;
8245 /* This is sort of inverse to pa_encode_section_info. */
8248 pa_strip_name_encoding (const char *str
)
8250 str
+= (*str
== '@');
8251 str
+= (*str
== '*');
8255 /* Returns 1 if OP is a function label involved in a simple addition
8256 with a constant. Used to keep certain patterns from matching
8257 during instruction combination. */
8259 pa_is_function_label_plus_const (rtx op
)
8261 /* Strip off any CONST. */
8262 if (GET_CODE (op
) == CONST
)
8265 return (GET_CODE (op
) == PLUS
8266 && function_label_operand (XEXP (op
, 0), VOIDmode
)
8267 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
8270 /* Output assembly code for a thunk to FUNCTION. */
8273 pa_asm_output_mi_thunk (FILE *file
, tree thunk_fndecl
, HOST_WIDE_INT delta
,
8274 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
8277 static unsigned int current_thunk_number
;
8278 int val_14
= VAL_14_BITS_P (delta
);
8279 unsigned int old_last_address
= last_address
, nbytes
= 0;
8283 xoperands
[0] = XEXP (DECL_RTL (function
), 0);
8284 xoperands
[1] = XEXP (DECL_RTL (thunk_fndecl
), 0);
8285 xoperands
[2] = GEN_INT (delta
);
8287 final_start_function (emit_barrier (), file
, 1);
8289 /* Output the thunk. We know that the function is in the same
8290 translation unit (i.e., the same space) as the thunk, and that
8291 thunks are output after their method. Thus, we don't need an
8292 external branch to reach the function. With SOM and GAS,
8293 functions and thunks are effectively in different sections.
8294 Thus, we can always use a IA-relative branch and the linker
8295 will add a long branch stub if necessary.
8297 However, we have to be careful when generating PIC code on the
8298 SOM port to ensure that the sequence does not transfer to an
8299 import stub for the target function as this could clobber the
8300 return value saved at SP-24. This would also apply to the
8301 32-bit linux port if the multi-space model is implemented. */
8302 if ((!TARGET_LONG_CALLS
&& TARGET_SOM
&& !TARGET_PORTABLE_RUNTIME
8303 && !(flag_pic
&& TREE_PUBLIC (function
))
8304 && (TARGET_GAS
|| last_address
< 262132))
8305 || (!TARGET_LONG_CALLS
&& !TARGET_SOM
&& !TARGET_PORTABLE_RUNTIME
8306 && ((targetm_common
.have_named_sections
8307 && DECL_SECTION_NAME (thunk_fndecl
) != NULL
8308 /* The GNU 64-bit linker has rather poor stub management.
8309 So, we use a long branch from thunks that aren't in
8310 the same section as the target function. */
8312 && (DECL_SECTION_NAME (thunk_fndecl
)
8313 != DECL_SECTION_NAME (function
)))
8314 || ((DECL_SECTION_NAME (thunk_fndecl
)
8315 == DECL_SECTION_NAME (function
))
8316 && last_address
< 262132)))
8317 /* In this case, we need to be able to reach the start of
8318 the stub table even though the function is likely closer
8319 and can be jumped to directly. */
8320 || (targetm_common
.have_named_sections
8321 && DECL_SECTION_NAME (thunk_fndecl
) == NULL
8322 && DECL_SECTION_NAME (function
) == NULL
8323 && total_code_bytes
< MAX_PCREL17F_OFFSET
)
8325 || (!targetm_common
.have_named_sections
8326 && total_code_bytes
< MAX_PCREL17F_OFFSET
))))
8329 output_asm_insn ("addil L'%2,%%r26", xoperands
);
8331 output_asm_insn ("b %0", xoperands
);
8335 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands
);
8340 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands
);
8344 else if (TARGET_64BIT
)
8346 /* We only have one call-clobbered scratch register, so we can't
8347 make use of the delay slot if delta doesn't fit in 14 bits. */
8350 output_asm_insn ("addil L'%2,%%r26", xoperands
);
8351 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands
);
8354 output_asm_insn ("b,l .+8,%%r1", xoperands
);
8358 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands
);
8359 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands
);
8363 xoperands
[3] = GEN_INT (val_14
? 8 : 16);
8364 output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands
);
8369 output_asm_insn ("bv %%r0(%%r1)", xoperands
);
8370 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands
);
8375 output_asm_insn ("bv,n %%r0(%%r1)", xoperands
);
8379 else if (TARGET_PORTABLE_RUNTIME
)
8381 output_asm_insn ("ldil L'%0,%%r1", xoperands
);
8382 output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands
);
8385 output_asm_insn ("addil L'%2,%%r26", xoperands
);
8387 output_asm_insn ("bv %%r0(%%r22)", xoperands
);
8391 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands
);
8396 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands
);
8400 else if (TARGET_SOM
&& flag_pic
&& TREE_PUBLIC (function
))
8402 /* The function is accessible from outside this module. The only
8403 way to avoid an import stub between the thunk and function is to
8404 call the function directly with an indirect sequence similar to
8405 that used by $$dyncall. This is possible because $$dyncall acts
8406 as the import stub in an indirect call. */
8407 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHN", current_thunk_number
);
8408 xoperands
[3] = gen_rtx_SYMBOL_REF (Pmode
, label
);
8409 output_asm_insn ("addil LT'%3,%%r19", xoperands
);
8410 output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands
);
8411 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands
);
8412 output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands
);
8413 output_asm_insn ("depi 0,31,2,%%r22", xoperands
);
8414 output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands
);
8415 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands
);
8419 output_asm_insn ("addil L'%2,%%r26", xoperands
);
8425 output_asm_insn ("bve (%%r22)", xoperands
);
8428 else if (TARGET_NO_SPACE_REGS
)
8430 output_asm_insn ("be 0(%%sr4,%%r22)", xoperands
);
8435 output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands
);
8436 output_asm_insn ("mtsp %%r21,%%sr0", xoperands
);
8437 output_asm_insn ("be 0(%%sr0,%%r22)", xoperands
);
8442 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands
);
8444 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands
);
8448 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands
);
8450 if (TARGET_SOM
|| !TARGET_GAS
)
8452 output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands
);
8453 output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands
);
8457 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands
);
8458 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands
);
8462 output_asm_insn ("addil L'%2,%%r26", xoperands
);
8464 output_asm_insn ("bv %%r0(%%r22)", xoperands
);
8468 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands
);
8473 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands
);
8480 output_asm_insn ("addil L'%2,%%r26", xoperands
);
8482 output_asm_insn ("ldil L'%0,%%r22", xoperands
);
8483 output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands
);
8487 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands
);
8492 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands
);
8497 final_end_function ();
8499 if (TARGET_SOM
&& flag_pic
&& TREE_PUBLIC (function
))
8501 switch_to_section (data_section
);
8502 output_asm_insn (".align 4", xoperands
);
8503 ASM_OUTPUT_LABEL (file
, label
);
8504 output_asm_insn (".word P'%0", xoperands
);
8507 current_thunk_number
++;
8508 nbytes
= ((nbytes
+ FUNCTION_BOUNDARY
/ BITS_PER_UNIT
- 1)
8509 & ~(FUNCTION_BOUNDARY
/ BITS_PER_UNIT
- 1));
8510 last_address
+= nbytes
;
8511 if (old_last_address
> last_address
)
8512 last_address
= UINT_MAX
;
8513 update_total_code_bytes (nbytes
);
8516 /* Only direct calls to static functions are allowed to be sibling (tail)
8519 This restriction is necessary because some linker generated stubs will
8520 store return pointers into rp' in some cases which might clobber a
8521 live value already in rp'.
8523 In a sibcall the current function and the target function share stack
8524 space. Thus if the path to the current function and the path to the
8525 target function save a value in rp', they save the value into the
8526 same stack slot, which has undesirable consequences.
8528 Because of the deferred binding nature of shared libraries any function
8529 with external scope could be in a different load module and thus require
8530 rp' to be saved when calling that function. So sibcall optimizations
8531 can only be safe for static function.
8533 Note that GCC never needs return value relocations, so we don't have to
8534 worry about static calls with return value relocations (which require
8537 It is safe to perform a sibcall optimization when the target function
8538 will never return. */
8540 pa_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
8542 if (TARGET_PORTABLE_RUNTIME
)
8545 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
8546 single subspace mode and the call is not indirect. As far as I know,
8547 there is no operating system support for the multiple subspace mode.
8548 It might be possible to support indirect calls if we didn't use
8549 $$dyncall (see the indirect sequence generated in pa_output_call). */
8551 return (decl
!= NULL_TREE
);
8553 /* Sibcalls are not ok because the arg pointer register is not a fixed
8554 register. This prevents the sibcall optimization from occurring. In
8555 addition, there are problems with stub placement using GNU ld. This
8556 is because a normal sibcall branch uses a 17-bit relocation while
8557 a regular call branch uses a 22-bit relocation. As a result, more
8558 care needs to be taken in the placement of long-branch stubs. */
8562 /* Sibcalls are only ok within a translation unit. */
8563 return (decl
&& !TREE_PUBLIC (decl
));
8566 /* ??? Addition is not commutative on the PA due to the weird implicit
8567 space register selection rules for memory addresses. Therefore, we
8568 don't consider a + b == b + a, as this might be inside a MEM. */
8570 pa_commutative_p (const_rtx x
, int outer_code
)
8572 return (COMMUTATIVE_P (x
)
8573 && (TARGET_NO_SPACE_REGS
8574 || (outer_code
!= UNKNOWN
&& outer_code
!= MEM
)
8575 || GET_CODE (x
) != PLUS
));
8578 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8579 use in fmpyadd instructions. */
8581 pa_fmpyaddoperands (rtx
*operands
)
8583 enum machine_mode mode
= GET_MODE (operands
[0]);
8585 /* Must be a floating point mode. */
8586 if (mode
!= SFmode
&& mode
!= DFmode
)
8589 /* All modes must be the same. */
8590 if (! (mode
== GET_MODE (operands
[1])
8591 && mode
== GET_MODE (operands
[2])
8592 && mode
== GET_MODE (operands
[3])
8593 && mode
== GET_MODE (operands
[4])
8594 && mode
== GET_MODE (operands
[5])))
8597 /* All operands must be registers. */
8598 if (! (GET_CODE (operands
[1]) == REG
8599 && GET_CODE (operands
[2]) == REG
8600 && GET_CODE (operands
[3]) == REG
8601 && GET_CODE (operands
[4]) == REG
8602 && GET_CODE (operands
[5]) == REG
))
8605 /* Only 2 real operands to the addition. One of the input operands must
8606 be the same as the output operand. */
8607 if (! rtx_equal_p (operands
[3], operands
[4])
8608 && ! rtx_equal_p (operands
[3], operands
[5]))
8611 /* Inout operand of add cannot conflict with any operands from multiply. */
8612 if (rtx_equal_p (operands
[3], operands
[0])
8613 || rtx_equal_p (operands
[3], operands
[1])
8614 || rtx_equal_p (operands
[3], operands
[2]))
8617 /* multiply cannot feed into addition operands. */
8618 if (rtx_equal_p (operands
[4], operands
[0])
8619 || rtx_equal_p (operands
[5], operands
[0]))
8622 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8624 && (REGNO_REG_CLASS (REGNO (operands
[0])) != FPUPPER_REGS
8625 || REGNO_REG_CLASS (REGNO (operands
[1])) != FPUPPER_REGS
8626 || REGNO_REG_CLASS (REGNO (operands
[2])) != FPUPPER_REGS
8627 || REGNO_REG_CLASS (REGNO (operands
[3])) != FPUPPER_REGS
8628 || REGNO_REG_CLASS (REGNO (operands
[4])) != FPUPPER_REGS
8629 || REGNO_REG_CLASS (REGNO (operands
[5])) != FPUPPER_REGS
))
8632 /* Passed. Operands are suitable for fmpyadd. */
8636 #if !defined(USE_COLLECT2)
8638 pa_asm_out_constructor (rtx symbol
, int priority
)
8640 if (!function_label_operand (symbol
, VOIDmode
))
8641 pa_encode_label (symbol
);
8643 #ifdef CTORS_SECTION_ASM_OP
8644 default_ctor_section_asm_out_constructor (symbol
, priority
);
8646 # ifdef TARGET_ASM_NAMED_SECTION
8647 default_named_section_asm_out_constructor (symbol
, priority
);
8649 default_stabs_asm_out_constructor (symbol
, priority
);
8655 pa_asm_out_destructor (rtx symbol
, int priority
)
8657 if (!function_label_operand (symbol
, VOIDmode
))
8658 pa_encode_label (symbol
);
8660 #ifdef DTORS_SECTION_ASM_OP
8661 default_dtor_section_asm_out_destructor (symbol
, priority
);
8663 # ifdef TARGET_ASM_NAMED_SECTION
8664 default_named_section_asm_out_destructor (symbol
, priority
);
8666 default_stabs_asm_out_destructor (symbol
, priority
);
8672 /* This function places uninitialized global data in the bss section.
8673 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
8674 function on the SOM port to prevent uninitialized global data from
8675 being placed in the data section. */
8678 pa_asm_output_aligned_bss (FILE *stream
,
8680 unsigned HOST_WIDE_INT size
,
8683 switch_to_section (bss_section
);
8684 fprintf (stream
, "\t.align %u\n", align
/ BITS_PER_UNIT
);
8686 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8687 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
8690 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8691 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8694 fprintf (stream
, "\t.align %u\n", align
/ BITS_PER_UNIT
);
8695 ASM_OUTPUT_LABEL (stream
, name
);
8696 fprintf (stream
, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
8699 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
8700 that doesn't allow the alignment of global common storage to be directly
8701 specified. The SOM linker aligns common storage based on the rounded
8702 value of the NUM_BYTES parameter in the .comm directive. It's not
8703 possible to use the .align directive as it doesn't affect the alignment
8704 of the label associated with a .comm directive. */
8707 pa_asm_output_aligned_common (FILE *stream
,
8709 unsigned HOST_WIDE_INT size
,
8712 unsigned int max_common_align
;
8714 max_common_align
= TARGET_64BIT
? 128 : (size
>= 4096 ? 256 : 64);
8715 if (align
> max_common_align
)
8717 warning (0, "alignment (%u) for %s exceeds maximum alignment "
8718 "for global common data. Using %u",
8719 align
/ BITS_PER_UNIT
, name
, max_common_align
/ BITS_PER_UNIT
);
8720 align
= max_common_align
;
8723 switch_to_section (bss_section
);
8725 assemble_name (stream
, name
);
8726 fprintf (stream
, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
8727 MAX (size
, align
/ BITS_PER_UNIT
));
8730 /* We can't use .comm for local common storage as the SOM linker effectively
8731 treats the symbol as universal and uses the same storage for local symbols
8732 with the same name in different object files. The .block directive
8733 reserves an uninitialized block of storage. However, it's not common
8734 storage. Fortunately, GCC never requests common storage with the same
8735 name in any given translation unit. */
8738 pa_asm_output_aligned_local (FILE *stream
,
8740 unsigned HOST_WIDE_INT size
,
8743 switch_to_section (bss_section
);
8744 fprintf (stream
, "\t.align %u\n", align
/ BITS_PER_UNIT
);
8747 fprintf (stream
, "%s", LOCAL_ASM_OP
);
8748 assemble_name (stream
, name
);
8749 fprintf (stream
, "\n");
8752 ASM_OUTPUT_LABEL (stream
, name
);
8753 fprintf (stream
, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
8756 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8757 use in fmpysub instructions. */
8759 pa_fmpysuboperands (rtx
*operands
)
8761 enum machine_mode mode
= GET_MODE (operands
[0]);
8763 /* Must be a floating point mode. */
8764 if (mode
!= SFmode
&& mode
!= DFmode
)
8767 /* All modes must be the same. */
8768 if (! (mode
== GET_MODE (operands
[1])
8769 && mode
== GET_MODE (operands
[2])
8770 && mode
== GET_MODE (operands
[3])
8771 && mode
== GET_MODE (operands
[4])
8772 && mode
== GET_MODE (operands
[5])))
8775 /* All operands must be registers. */
8776 if (! (GET_CODE (operands
[1]) == REG
8777 && GET_CODE (operands
[2]) == REG
8778 && GET_CODE (operands
[3]) == REG
8779 && GET_CODE (operands
[4]) == REG
8780 && GET_CODE (operands
[5]) == REG
))
8783 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8784 operation, so operands[4] must be the same as operand[3]. */
8785 if (! rtx_equal_p (operands
[3], operands
[4]))
8788 /* multiply cannot feed into subtraction. */
8789 if (rtx_equal_p (operands
[5], operands
[0]))
8792 /* Inout operand of sub cannot conflict with any operands from multiply. */
8793 if (rtx_equal_p (operands
[3], operands
[0])
8794 || rtx_equal_p (operands
[3], operands
[1])
8795 || rtx_equal_p (operands
[3], operands
[2]))
8798 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8800 && (REGNO_REG_CLASS (REGNO (operands
[0])) != FPUPPER_REGS
8801 || REGNO_REG_CLASS (REGNO (operands
[1])) != FPUPPER_REGS
8802 || REGNO_REG_CLASS (REGNO (operands
[2])) != FPUPPER_REGS
8803 || REGNO_REG_CLASS (REGNO (operands
[3])) != FPUPPER_REGS
8804 || REGNO_REG_CLASS (REGNO (operands
[4])) != FPUPPER_REGS
8805 || REGNO_REG_CLASS (REGNO (operands
[5])) != FPUPPER_REGS
))
8808 /* Passed. Operands are suitable for fmpysub. */
8812 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8813 constants for shadd instructions. */
8815 pa_shadd_constant_p (int val
)
8817 if (val
== 2 || val
== 4 || val
== 8)
8823 /* Return TRUE if INSN branches forward. */
8826 forward_branch_p (rtx insn
)
8828 rtx lab
= JUMP_LABEL (insn
);
8830 /* The INSN must have a jump label. */
8831 gcc_assert (lab
!= NULL_RTX
);
8833 if (INSN_ADDRESSES_SET_P ())
8834 return INSN_ADDRESSES (INSN_UID (lab
)) > INSN_ADDRESSES (INSN_UID (insn
));
8841 insn
= NEXT_INSN (insn
);
8847 /* Return 1 if INSN is in the delay slot of a call instruction. */
8849 pa_jump_in_call_delay (rtx insn
)
8852 if (GET_CODE (insn
) != JUMP_INSN
)
8855 if (PREV_INSN (insn
)
8856 && PREV_INSN (PREV_INSN (insn
))
8857 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn
)))) == INSN
)
8859 rtx test_insn
= next_real_insn (PREV_INSN (PREV_INSN (insn
)));
8861 return (GET_CODE (PATTERN (test_insn
)) == SEQUENCE
8862 && XVECEXP (PATTERN (test_insn
), 0, 1) == insn
);
8869 /* Output an unconditional move and branch insn. */
8872 pa_output_parallel_movb (rtx
*operands
, rtx insn
)
8874 int length
= get_attr_length (insn
);
8876 /* These are the cases in which we win. */
8878 return "mov%I1b,tr %1,%0,%2";
8880 /* None of the following cases win, but they don't lose either. */
8883 if (dbr_sequence_length () == 0)
8885 /* Nothing in the delay slot, fake it by putting the combined
8886 insn (the copy or add) in the delay slot of a bl. */
8887 if (GET_CODE (operands
[1]) == CONST_INT
)
8888 return "b %2\n\tldi %1,%0";
8890 return "b %2\n\tcopy %1,%0";
8894 /* Something in the delay slot, but we've got a long branch. */
8895 if (GET_CODE (operands
[1]) == CONST_INT
)
8896 return "ldi %1,%0\n\tb %2";
8898 return "copy %1,%0\n\tb %2";
8902 if (GET_CODE (operands
[1]) == CONST_INT
)
8903 output_asm_insn ("ldi %1,%0", operands
);
8905 output_asm_insn ("copy %1,%0", operands
);
8906 return pa_output_lbranch (operands
[2], insn
, 1);
8909 /* Output an unconditional add and branch insn. */
8912 pa_output_parallel_addb (rtx
*operands
, rtx insn
)
8914 int length
= get_attr_length (insn
);
8916 /* To make life easy we want operand0 to be the shared input/output
8917 operand and operand1 to be the readonly operand. */
8918 if (operands
[0] == operands
[1])
8919 operands
[1] = operands
[2];
8921 /* These are the cases in which we win. */
8923 return "add%I1b,tr %1,%0,%3";
8925 /* None of the following cases win, but they don't lose either. */
8928 if (dbr_sequence_length () == 0)
8929 /* Nothing in the delay slot, fake it by putting the combined
8930 insn (the copy or add) in the delay slot of a bl. */
8931 return "b %3\n\tadd%I1 %1,%0,%0";
8933 /* Something in the delay slot, but we've got a long branch. */
8934 return "add%I1 %1,%0,%0\n\tb %3";
8937 output_asm_insn ("add%I1 %1,%0,%0", operands
);
8938 return pa_output_lbranch (operands
[3], insn
, 1);
8941 /* Return nonzero if INSN (a jump insn) immediately follows a call
8942 to a named function. This is used to avoid filling the delay slot
8943 of the jump since it can usually be eliminated by modifying RP in
8944 the delay slot of the call. */
8947 pa_following_call (rtx insn
)
8949 if (! TARGET_JUMP_IN_DELAY
)
8952 /* Find the previous real insn, skipping NOTEs. */
8953 insn
= PREV_INSN (insn
);
8954 while (insn
&& GET_CODE (insn
) == NOTE
)
8955 insn
= PREV_INSN (insn
);
8957 /* Check for CALL_INSNs and millicode calls. */
8959 && ((GET_CODE (insn
) == CALL_INSN
8960 && get_attr_type (insn
) != TYPE_DYNCALL
)
8961 || (GET_CODE (insn
) == INSN
8962 && GET_CODE (PATTERN (insn
)) != SEQUENCE
8963 && GET_CODE (PATTERN (insn
)) != USE
8964 && GET_CODE (PATTERN (insn
)) != CLOBBER
8965 && get_attr_type (insn
) == TYPE_MILLI
)))
8971 /* We use this hook to perform a PA specific optimization which is difficult
8972 to do in earlier passes.
8974 We want the delay slots of branches within jump tables to be filled.
8975 None of the compiler passes at the moment even has the notion that a
8976 PA jump table doesn't contain addresses, but instead contains actual
8979 Because we actually jump into the table, the addresses of each entry
8980 must stay constant in relation to the beginning of the table (which
8981 itself must stay constant relative to the instruction to jump into
8982 it). I don't believe we can guarantee earlier passes of the compiler
8983 will adhere to those rules.
8985 So, late in the compilation process we find all the jump tables, and
8986 expand them into real code -- e.g. each entry in the jump table vector
8987 will get an appropriate label followed by a jump to the final target.
8989 Reorg and the final jump pass can then optimize these branches and
8990 fill their delay slots. We end up with smaller, more efficient code.
8992 The jump instructions within the table are special; we must be able
8993 to identify them during assembly output (if the jumps don't get filled
8994 we need to emit a nop rather than nullifying the delay slot)). We
8995 identify jumps in switch tables by using insns with the attribute
8996 type TYPE_BTABLE_BRANCH.
8998 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8999 insns. This serves two purposes, first it prevents jump.c from
9000 noticing that the last N entries in the table jump to the instruction
9001 immediately after the table and deleting the jumps. Second, those
9002 insns mark where we should emit .begin_brtab and .end_brtab directives
9003 when using GAS (allows for better link time optimizations). */
9010 remove_useless_addtr_insns (1);
9012 if (pa_cpu
< PROCESSOR_8000
)
9013 pa_combine_instructions ();
9016 /* This is fairly cheap, so always run it if optimizing. */
9017 if (optimize
> 0 && !TARGET_BIG_SWITCH
)
9019 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
9020 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9022 rtx pattern
, tmp
, location
, label
;
9023 unsigned int length
, i
;
9025 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
9026 if (GET_CODE (insn
) != JUMP_INSN
9027 || (GET_CODE (PATTERN (insn
)) != ADDR_VEC
9028 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
))
9031 /* Emit marker for the beginning of the branch table. */
9032 emit_insn_before (gen_begin_brtab (), insn
);
9034 pattern
= PATTERN (insn
);
9035 location
= PREV_INSN (insn
);
9036 length
= XVECLEN (pattern
, GET_CODE (pattern
) == ADDR_DIFF_VEC
);
9038 for (i
= 0; i
< length
; i
++)
9040 /* Emit a label before each jump to keep jump.c from
9041 removing this code. */
9042 tmp
= gen_label_rtx ();
9043 LABEL_NUSES (tmp
) = 1;
9044 emit_label_after (tmp
, location
);
9045 location
= NEXT_INSN (location
);
9047 if (GET_CODE (pattern
) == ADDR_VEC
)
9048 label
= XEXP (XVECEXP (pattern
, 0, i
), 0);
9050 label
= XEXP (XVECEXP (pattern
, 1, i
), 0);
9052 tmp
= gen_short_jump (label
);
9054 /* Emit the jump itself. */
9055 tmp
= emit_jump_insn_after (tmp
, location
);
9056 JUMP_LABEL (tmp
) = label
;
9057 LABEL_NUSES (label
)++;
9058 location
= NEXT_INSN (location
);
9060 /* Emit a BARRIER after the jump. */
9061 emit_barrier_after (location
);
9062 location
= NEXT_INSN (location
);
9065 /* Emit marker for the end of the branch table. */
9066 emit_insn_before (gen_end_brtab (), location
);
9067 location
= NEXT_INSN (location
);
9068 emit_barrier_after (location
);
9070 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
9076 /* Still need brtab marker insns. FIXME: the presence of these
9077 markers disables output of the branch table to readonly memory,
9078 and any alignment directives that might be needed. Possibly,
9079 the begin_brtab insn should be output before the label for the
9080 table. This doesn't matter at the moment since the tables are
9081 always output in the text section. */
9082 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9084 /* Find an ADDR_VEC insn. */
9085 if (GET_CODE (insn
) != JUMP_INSN
9086 || (GET_CODE (PATTERN (insn
)) != ADDR_VEC
9087 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
))
9090 /* Now generate markers for the beginning and end of the
9092 emit_insn_before (gen_begin_brtab (), insn
);
9093 emit_insn_after (gen_end_brtab (), insn
);
9098 /* The PA has a number of odd instructions which can perform multiple
9099 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
9100 it may be profitable to combine two instructions into one instruction
9101 with two outputs. It's not profitable PA2.0 machines because the
9102 two outputs would take two slots in the reorder buffers.
9104 This routine finds instructions which can be combined and combines
9105 them. We only support some of the potential combinations, and we
9106 only try common ways to find suitable instructions.
9108 * addb can add two registers or a register and a small integer
9109 and jump to a nearby (+-8k) location. Normally the jump to the
9110 nearby location is conditional on the result of the add, but by
9111 using the "true" condition we can make the jump unconditional.
9112 Thus addb can perform two independent operations in one insn.
9114 * movb is similar to addb in that it can perform a reg->reg
9115 or small immediate->reg copy and jump to a nearby (+-8k location).
9117 * fmpyadd and fmpysub can perform a FP multiply and either an
9118 FP add or FP sub if the operands of the multiply and add/sub are
9119 independent (there are other minor restrictions). Note both
9120 the fmpy and fadd/fsub can in theory move to better spots according
9121 to data dependencies, but for now we require the fmpy stay at a
9124 * Many of the memory operations can perform pre & post updates
9125 of index registers. GCC's pre/post increment/decrement addressing
9126 is far too simple to take advantage of all the possibilities. This
9127 pass may not be suitable since those insns may not be independent.
9129 * comclr can compare two ints or an int and a register, nullify
9130 the following instruction and zero some other register. This
9131 is more difficult to use as it's harder to find an insn which
9132 will generate a comclr than finding something like an unconditional
9133 branch. (conditional moves & long branches create comclr insns).
9135 * Most arithmetic operations can conditionally skip the next
9136 instruction. They can be viewed as "perform this operation
9137 and conditionally jump to this nearby location" (where nearby
9138 is an insns away). These are difficult to use due to the
9139 branch length restrictions. */
9142 pa_combine_instructions (void)
9144 rtx anchor
, new_rtx
;
9146 /* This can get expensive since the basic algorithm is on the
9147 order of O(n^2) (or worse). Only do it for -O2 or higher
9148 levels of optimization. */
9152 /* Walk down the list of insns looking for "anchor" insns which
9153 may be combined with "floating" insns. As the name implies,
9154 "anchor" instructions don't move, while "floating" insns may
9156 new_rtx
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, NULL_RTX
, NULL_RTX
));
9157 new_rtx
= make_insn_raw (new_rtx
);
9159 for (anchor
= get_insns (); anchor
; anchor
= NEXT_INSN (anchor
))
9161 enum attr_pa_combine_type anchor_attr
;
9162 enum attr_pa_combine_type floater_attr
;
9164 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
9165 Also ignore any special USE insns. */
9166 if ((GET_CODE (anchor
) != INSN
9167 && GET_CODE (anchor
) != JUMP_INSN
9168 && GET_CODE (anchor
) != CALL_INSN
)
9169 || GET_CODE (PATTERN (anchor
)) == USE
9170 || GET_CODE (PATTERN (anchor
)) == CLOBBER
9171 || GET_CODE (PATTERN (anchor
)) == ADDR_VEC
9172 || GET_CODE (PATTERN (anchor
)) == ADDR_DIFF_VEC
)
9175 anchor_attr
= get_attr_pa_combine_type (anchor
);
9176 /* See if anchor is an insn suitable for combination. */
9177 if (anchor_attr
== PA_COMBINE_TYPE_FMPY
9178 || anchor_attr
== PA_COMBINE_TYPE_FADDSUB
9179 || (anchor_attr
== PA_COMBINE_TYPE_UNCOND_BRANCH
9180 && ! forward_branch_p (anchor
)))
9184 for (floater
= PREV_INSN (anchor
);
9186 floater
= PREV_INSN (floater
))
9188 if (GET_CODE (floater
) == NOTE
9189 || (GET_CODE (floater
) == INSN
9190 && (GET_CODE (PATTERN (floater
)) == USE
9191 || GET_CODE (PATTERN (floater
)) == CLOBBER
)))
9194 /* Anything except a regular INSN will stop our search. */
9195 if (GET_CODE (floater
) != INSN
9196 || GET_CODE (PATTERN (floater
)) == ADDR_VEC
9197 || GET_CODE (PATTERN (floater
)) == ADDR_DIFF_VEC
)
9203 /* See if FLOATER is suitable for combination with the
9205 floater_attr
= get_attr_pa_combine_type (floater
);
9206 if ((anchor_attr
== PA_COMBINE_TYPE_FMPY
9207 && floater_attr
== PA_COMBINE_TYPE_FADDSUB
)
9208 || (anchor_attr
== PA_COMBINE_TYPE_FADDSUB
9209 && floater_attr
== PA_COMBINE_TYPE_FMPY
))
9211 /* If ANCHOR and FLOATER can be combined, then we're
9212 done with this pass. */
9213 if (pa_can_combine_p (new_rtx
, anchor
, floater
, 0,
9214 SET_DEST (PATTERN (floater
)),
9215 XEXP (SET_SRC (PATTERN (floater
)), 0),
9216 XEXP (SET_SRC (PATTERN (floater
)), 1)))
9220 else if (anchor_attr
== PA_COMBINE_TYPE_UNCOND_BRANCH
9221 && floater_attr
== PA_COMBINE_TYPE_ADDMOVE
)
9223 if (GET_CODE (SET_SRC (PATTERN (floater
))) == PLUS
)
9225 if (pa_can_combine_p (new_rtx
, anchor
, floater
, 0,
9226 SET_DEST (PATTERN (floater
)),
9227 XEXP (SET_SRC (PATTERN (floater
)), 0),
9228 XEXP (SET_SRC (PATTERN (floater
)), 1)))
9233 if (pa_can_combine_p (new_rtx
, anchor
, floater
, 0,
9234 SET_DEST (PATTERN (floater
)),
9235 SET_SRC (PATTERN (floater
)),
9236 SET_SRC (PATTERN (floater
))))
9242 /* If we didn't find anything on the backwards scan try forwards. */
9244 && (anchor_attr
== PA_COMBINE_TYPE_FMPY
9245 || anchor_attr
== PA_COMBINE_TYPE_FADDSUB
))
9247 for (floater
= anchor
; floater
; floater
= NEXT_INSN (floater
))
9249 if (GET_CODE (floater
) == NOTE
9250 || (GET_CODE (floater
) == INSN
9251 && (GET_CODE (PATTERN (floater
)) == USE
9252 || GET_CODE (PATTERN (floater
)) == CLOBBER
)))
9256 /* Anything except a regular INSN will stop our search. */
9257 if (GET_CODE (floater
) != INSN
9258 || GET_CODE (PATTERN (floater
)) == ADDR_VEC
9259 || GET_CODE (PATTERN (floater
)) == ADDR_DIFF_VEC
)
9265 /* See if FLOATER is suitable for combination with the
9267 floater_attr
= get_attr_pa_combine_type (floater
);
9268 if ((anchor_attr
== PA_COMBINE_TYPE_FMPY
9269 && floater_attr
== PA_COMBINE_TYPE_FADDSUB
)
9270 || (anchor_attr
== PA_COMBINE_TYPE_FADDSUB
9271 && floater_attr
== PA_COMBINE_TYPE_FMPY
))
9273 /* If ANCHOR and FLOATER can be combined, then we're
9274 done with this pass. */
9275 if (pa_can_combine_p (new_rtx
, anchor
, floater
, 1,
9276 SET_DEST (PATTERN (floater
)),
9277 XEXP (SET_SRC (PATTERN (floater
)),
9279 XEXP (SET_SRC (PATTERN (floater
)),
9286 /* FLOATER will be nonzero if we found a suitable floating
9287 insn for combination with ANCHOR. */
9289 && (anchor_attr
== PA_COMBINE_TYPE_FADDSUB
9290 || anchor_attr
== PA_COMBINE_TYPE_FMPY
))
9292 /* Emit the new instruction and delete the old anchor. */
9293 emit_insn_before (gen_rtx_PARALLEL
9295 gen_rtvec (2, PATTERN (anchor
),
9296 PATTERN (floater
))),
9299 SET_INSN_DELETED (anchor
);
9301 /* Emit a special USE insn for FLOATER, then delete
9302 the floating insn. */
9303 emit_insn_before (gen_rtx_USE (VOIDmode
, floater
), floater
);
9304 delete_insn (floater
);
9309 && anchor_attr
== PA_COMBINE_TYPE_UNCOND_BRANCH
)
9312 /* Emit the new_jump instruction and delete the old anchor. */
9314 = emit_jump_insn_before (gen_rtx_PARALLEL
9316 gen_rtvec (2, PATTERN (anchor
),
9317 PATTERN (floater
))),
9320 JUMP_LABEL (temp
) = JUMP_LABEL (anchor
);
9321 SET_INSN_DELETED (anchor
);
9323 /* Emit a special USE insn for FLOATER, then delete
9324 the floating insn. */
9325 emit_insn_before (gen_rtx_USE (VOIDmode
, floater
), floater
);
9326 delete_insn (floater
);
9334 pa_can_combine_p (rtx new_rtx
, rtx anchor
, rtx floater
, int reversed
, rtx dest
,
9337 int insn_code_number
;
9340 /* Create a PARALLEL with the patterns of ANCHOR and
9341 FLOATER, try to recognize it, then test constraints
9342 for the resulting pattern.
9344 If the pattern doesn't match or the constraints
9345 aren't met keep searching for a suitable floater
9347 XVECEXP (PATTERN (new_rtx
), 0, 0) = PATTERN (anchor
);
9348 XVECEXP (PATTERN (new_rtx
), 0, 1) = PATTERN (floater
);
9349 INSN_CODE (new_rtx
) = -1;
9350 insn_code_number
= recog_memoized (new_rtx
);
9351 if (insn_code_number
< 0
9352 || (extract_insn (new_rtx
), ! constrain_operands (1)))
9366 /* There's up to three operands to consider. One
9367 output and two inputs.
9369 The output must not be used between FLOATER & ANCHOR
9370 exclusive. The inputs must not be set between
9371 FLOATER and ANCHOR exclusive. */
9373 if (reg_used_between_p (dest
, start
, end
))
9376 if (reg_set_between_p (src1
, start
, end
))
9379 if (reg_set_between_p (src2
, start
, end
))
9382 /* If we get here, then everything is good. */
9386 /* Return nonzero if references for INSN are delayed.
9388 Millicode insns are actually function calls with some special
9389 constraints on arguments and register usage.
9391 Millicode calls always expect their arguments in the integer argument
9392 registers, and always return their result in %r29 (ret1). They
9393 are expected to clobber their arguments, %r1, %r29, and the return
9394 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
9396 This function tells reorg that the references to arguments and
9397 millicode calls do not appear to happen until after the millicode call.
9398 This allows reorg to put insns which set the argument registers into the
9399 delay slot of the millicode call -- thus they act more like traditional
9402 Note we cannot consider side effects of the insn to be delayed because
9403 the branch and link insn will clobber the return pointer. If we happened
9404 to use the return pointer in the delay slot of the call, then we lose.
9406 get_attr_type will try to recognize the given insn, so make sure to
9407 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
9410 pa_insn_refs_are_delayed (rtx insn
)
9412 return ((GET_CODE (insn
) == INSN
9413 && GET_CODE (PATTERN (insn
)) != SEQUENCE
9414 && GET_CODE (PATTERN (insn
)) != USE
9415 && GET_CODE (PATTERN (insn
)) != CLOBBER
9416 && get_attr_type (insn
) == TYPE_MILLI
));
9419 /* Promote the return value, but not the arguments. */
9421 static enum machine_mode
9422 pa_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
9423 enum machine_mode mode
,
9424 int *punsignedp ATTRIBUTE_UNUSED
,
9425 const_tree fntype ATTRIBUTE_UNUSED
,
9428 if (for_return
== 0)
9430 return promote_mode (type
, mode
, punsignedp
);
9433 /* On the HP-PA the value is found in register(s) 28(-29), unless
9434 the mode is SF or DF. Then the value is returned in fr4 (32).
9436 This must perform the same promotions as PROMOTE_MODE, else promoting
9437 return values in TARGET_PROMOTE_FUNCTION_MODE will not work correctly.
9439 Small structures must be returned in a PARALLEL on PA64 in order
9440 to match the HP Compiler ABI. */
9443 pa_function_value (const_tree valtype
,
9444 const_tree func ATTRIBUTE_UNUSED
,
9445 bool outgoing ATTRIBUTE_UNUSED
)
9447 enum machine_mode valmode
;
9449 if (AGGREGATE_TYPE_P (valtype
)
9450 || TREE_CODE (valtype
) == COMPLEX_TYPE
9451 || TREE_CODE (valtype
) == VECTOR_TYPE
)
9455 /* Aggregates with a size less than or equal to 128 bits are
9456 returned in GR 28(-29). They are left justified. The pad
9457 bits are undefined. Larger aggregates are returned in
9461 int ub
= int_size_in_bytes (valtype
) <= UNITS_PER_WORD
? 1 : 2;
9463 for (i
= 0; i
< ub
; i
++)
9465 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
9466 gen_rtx_REG (DImode
, 28 + i
),
9471 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (ub
, loc
));
9473 else if (int_size_in_bytes (valtype
) > UNITS_PER_WORD
)
9475 /* Aggregates 5 to 8 bytes in size are returned in general
9476 registers r28-r29 in the same manner as other non
9477 floating-point objects. The data is right-justified and
9478 zero-extended to 64 bits. This is opposite to the normal
9479 justification used on big endian targets and requires
9480 special treatment. */
9481 rtx loc
= gen_rtx_EXPR_LIST (VOIDmode
,
9482 gen_rtx_REG (DImode
, 28), const0_rtx
);
9483 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec (1, loc
));
9487 if ((INTEGRAL_TYPE_P (valtype
)
9488 && GET_MODE_BITSIZE (TYPE_MODE (valtype
)) < BITS_PER_WORD
)
9489 || POINTER_TYPE_P (valtype
))
9490 valmode
= word_mode
;
9492 valmode
= TYPE_MODE (valtype
);
9494 if (TREE_CODE (valtype
) == REAL_TYPE
9495 && !AGGREGATE_TYPE_P (valtype
)
9496 && TYPE_MODE (valtype
) != TFmode
9497 && !TARGET_SOFT_FLOAT
)
9498 return gen_rtx_REG (valmode
, 32);
9500 return gen_rtx_REG (valmode
, 28);
9503 /* Implement the TARGET_LIBCALL_VALUE hook. */
9506 pa_libcall_value (enum machine_mode mode
,
9507 const_rtx fun ATTRIBUTE_UNUSED
)
9509 if (! TARGET_SOFT_FLOAT
9510 && (mode
== SFmode
|| mode
== DFmode
))
9511 return gen_rtx_REG (mode
, 32);
9513 return gen_rtx_REG (mode
, 28);
9516 /* Implement the TARGET_FUNCTION_VALUE_REGNO_P hook. */
9519 pa_function_value_regno_p (const unsigned int regno
)
9522 || (! TARGET_SOFT_FLOAT
&& regno
== 32))
9528 /* Update the data in CUM to advance over an argument
9529 of mode MODE and data type TYPE.
9530 (TYPE is null for libcalls where that information may not be available.) */
9533 pa_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
9534 const_tree type
, bool named ATTRIBUTE_UNUSED
)
9536 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9537 int arg_size
= FUNCTION_ARG_SIZE (mode
, type
);
9539 cum
->nargs_prototype
--;
9540 cum
->words
+= (arg_size
9541 + ((cum
->words
& 01)
9542 && type
!= NULL_TREE
9546 /* Return the location of a parameter that is passed in a register or NULL
9547 if the parameter has any component that is passed in memory.
9549 This is new code and will be pushed to into the net sources after
9552 ??? We might want to restructure this so that it looks more like other
9555 pa_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
9556 const_tree type
, bool named ATTRIBUTE_UNUSED
)
9558 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9559 int max_arg_words
= (TARGET_64BIT
? 8 : 4);
9566 if (mode
== VOIDmode
)
9569 arg_size
= FUNCTION_ARG_SIZE (mode
, type
);
9571 /* If this arg would be passed partially or totally on the stack, then
9572 this routine should return zero. pa_arg_partial_bytes will
9573 handle arguments which are split between regs and stack slots if
9574 the ABI mandates split arguments. */
9577 /* The 32-bit ABI does not split arguments. */
9578 if (cum
->words
+ arg_size
> max_arg_words
)
9584 alignment
= cum
->words
& 1;
9585 if (cum
->words
+ alignment
>= max_arg_words
)
9589 /* The 32bit ABIs and the 64bit ABIs are rather different,
9590 particularly in their handling of FP registers. We might
9591 be able to cleverly share code between them, but I'm not
9592 going to bother in the hope that splitting them up results
9593 in code that is more easily understood. */
9597 /* Advance the base registers to their current locations.
9599 Remember, gprs grow towards smaller register numbers while
9600 fprs grow to higher register numbers. Also remember that
9601 although FP regs are 32-bit addressable, we pretend that
9602 the registers are 64-bits wide. */
9603 gpr_reg_base
= 26 - cum
->words
;
9604 fpr_reg_base
= 32 + cum
->words
;
9606 /* Arguments wider than one word and small aggregates need special
9610 || (type
&& (AGGREGATE_TYPE_P (type
)
9611 || TREE_CODE (type
) == COMPLEX_TYPE
9612 || TREE_CODE (type
) == VECTOR_TYPE
)))
9614 /* Double-extended precision (80-bit), quad-precision (128-bit)
9615 and aggregates including complex numbers are aligned on
9616 128-bit boundaries. The first eight 64-bit argument slots
9617 are associated one-to-one, with general registers r26
9618 through r19, and also with floating-point registers fr4
9619 through fr11. Arguments larger than one word are always
9620 passed in general registers.
9622 Using a PARALLEL with a word mode register results in left
9623 justified data on a big-endian target. */
9626 int i
, offset
= 0, ub
= arg_size
;
9628 /* Align the base register. */
9629 gpr_reg_base
-= alignment
;
9631 ub
= MIN (ub
, max_arg_words
- cum
->words
- alignment
);
9632 for (i
= 0; i
< ub
; i
++)
9634 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
9635 gen_rtx_REG (DImode
, gpr_reg_base
),
9641 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (ub
, loc
));
9646 /* If the argument is larger than a word, then we know precisely
9647 which registers we must use. */
9661 /* Structures 5 to 8 bytes in size are passed in the general
9662 registers in the same manner as other non floating-point
9663 objects. The data is right-justified and zero-extended
9664 to 64 bits. This is opposite to the normal justification
9665 used on big endian targets and requires special treatment.
9666 We now define BLOCK_REG_PADDING to pad these objects.
9667 Aggregates, complex and vector types are passed in the same
9668 manner as structures. */
9670 || (type
&& (AGGREGATE_TYPE_P (type
)
9671 || TREE_CODE (type
) == COMPLEX_TYPE
9672 || TREE_CODE (type
) == VECTOR_TYPE
)))
9674 rtx loc
= gen_rtx_EXPR_LIST (VOIDmode
,
9675 gen_rtx_REG (DImode
, gpr_reg_base
),
9677 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec (1, loc
));
9682 /* We have a single word (32 bits). A simple computation
9683 will get us the register #s we need. */
9684 gpr_reg_base
= 26 - cum
->words
;
9685 fpr_reg_base
= 32 + 2 * cum
->words
;
9689 /* Determine if the argument needs to be passed in both general and
9690 floating point registers. */
9691 if (((TARGET_PORTABLE_RUNTIME
|| TARGET_64BIT
|| TARGET_ELF32
)
9692 /* If we are doing soft-float with portable runtime, then there
9693 is no need to worry about FP regs. */
9694 && !TARGET_SOFT_FLOAT
9695 /* The parameter must be some kind of scalar float, else we just
9696 pass it in integer registers. */
9697 && GET_MODE_CLASS (mode
) == MODE_FLOAT
9698 /* The target function must not have a prototype. */
9699 && cum
->nargs_prototype
<= 0
9700 /* libcalls do not need to pass items in both FP and general
9702 && type
!= NULL_TREE
9703 /* All this hair applies to "outgoing" args only. This includes
9704 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
9706 /* Also pass outgoing floating arguments in both registers in indirect
9707 calls with the 32 bit ABI and the HP assembler since there is no
9708 way to the specify argument locations in static functions. */
9713 && GET_MODE_CLASS (mode
) == MODE_FLOAT
))
9719 gen_rtx_EXPR_LIST (VOIDmode
,
9720 gen_rtx_REG (mode
, fpr_reg_base
),
9722 gen_rtx_EXPR_LIST (VOIDmode
,
9723 gen_rtx_REG (mode
, gpr_reg_base
),
9728 /* See if we should pass this parameter in a general register. */
9729 if (TARGET_SOFT_FLOAT
9730 /* Indirect calls in the normal 32bit ABI require all arguments
9731 to be passed in general registers. */
9732 || (!TARGET_PORTABLE_RUNTIME
9736 /* If the parameter is not a scalar floating-point parameter,
9737 then it belongs in GPRs. */
9738 || GET_MODE_CLASS (mode
) != MODE_FLOAT
9739 /* Structure with single SFmode field belongs in GPR. */
9740 || (type
&& AGGREGATE_TYPE_P (type
)))
9741 retval
= gen_rtx_REG (mode
, gpr_reg_base
);
9743 retval
= gen_rtx_REG (mode
, fpr_reg_base
);
9748 /* Arguments larger than one word are double word aligned. */
9751 pa_function_arg_boundary (enum machine_mode mode
, const_tree type
)
9753 bool singleword
= (type
9754 ? (integer_zerop (TYPE_SIZE (type
))
9755 || !TREE_CONSTANT (TYPE_SIZE (type
))
9756 || int_size_in_bytes (type
) <= UNITS_PER_WORD
)
9757 : GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
);
9759 return singleword
? PARM_BOUNDARY
: MAX_PARM_BOUNDARY
;
9762 /* If this arg would be passed totally in registers or totally on the stack,
9763 then this routine should return zero. */
9766 pa_arg_partial_bytes (cumulative_args_t cum_v
, enum machine_mode mode
,
9767 tree type
, bool named ATTRIBUTE_UNUSED
)
9769 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9770 unsigned int max_arg_words
= 8;
9771 unsigned int offset
= 0;
9776 if (FUNCTION_ARG_SIZE (mode
, type
) > 1 && (cum
->words
& 1))
9779 if (cum
->words
+ offset
+ FUNCTION_ARG_SIZE (mode
, type
) <= max_arg_words
)
9780 /* Arg fits fully into registers. */
9782 else if (cum
->words
+ offset
>= max_arg_words
)
9783 /* Arg fully on the stack. */
9787 return (max_arg_words
- cum
->words
- offset
) * UNITS_PER_WORD
;
9791 /* A get_unnamed_section callback for switching to the text section.
9793 This function is only used with SOM. Because we don't support
9794 named subspaces, we can only create a new subspace or switch back
9795 to the default text subspace. */
9798 som_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
9800 gcc_assert (TARGET_SOM
);
9803 if (cfun
&& cfun
->machine
&& !cfun
->machine
->in_nsubspa
)
9805 /* We only want to emit a .nsubspa directive once at the
9806 start of the function. */
9807 cfun
->machine
->in_nsubspa
= 1;
9809 /* Create a new subspace for the text. This provides
9810 better stub placement and one-only functions. */
9812 && DECL_ONE_ONLY (cfun
->decl
)
9813 && !DECL_WEAK (cfun
->decl
))
9815 output_section_asm_op ("\t.SPACE $TEXT$\n"
9816 "\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,"
9817 "ACCESS=44,SORT=24,COMDAT");
9823 /* There isn't a current function or the body of the current
9824 function has been completed. So, we are changing to the
9825 text section to output debugging information. Thus, we
9826 need to forget that we are in the text section so that
9827 varasm.c will call us when text_section is selected again. */
9828 gcc_assert (!cfun
|| !cfun
->machine
9829 || cfun
->machine
->in_nsubspa
== 2);
9832 output_section_asm_op ("\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$");
9835 output_section_asm_op ("\t.SPACE $TEXT$\n\t.SUBSPA $CODE$");
9838 /* A get_unnamed_section callback for switching to comdat data
9839 sections. This function is only used with SOM. */
9842 som_output_comdat_data_section_asm_op (const void *data
)
9845 output_section_asm_op (data
);
9848 /* Implement TARGET_ASM_INITIALIZE_SECTIONS */
9851 pa_som_asm_init_sections (void)
9854 = get_unnamed_section (0, som_output_text_section_asm_op
, NULL
);
9856 /* SOM puts readonly data in the default $LIT$ subspace when PIC code
9857 is not being generated. */
9858 som_readonly_data_section
9859 = get_unnamed_section (0, output_section_asm_op
,
9860 "\t.SPACE $TEXT$\n\t.SUBSPA $LIT$");
9862 /* When secondary definitions are not supported, SOM makes readonly
9863 data one-only by creating a new $LIT$ subspace in $TEXT$ with
9865 som_one_only_readonly_data_section
9866 = get_unnamed_section (0, som_output_comdat_data_section_asm_op
,
9868 "\t.NSUBSPA $LIT$,QUAD=0,ALIGN=8,"
9869 "ACCESS=0x2c,SORT=16,COMDAT");
9872 /* When secondary definitions are not supported, SOM makes data one-only
9873 by creating a new $DATA$ subspace in $PRIVATE$ with the comdat flag. */
9874 som_one_only_data_section
9875 = get_unnamed_section (SECTION_WRITE
,
9876 som_output_comdat_data_section_asm_op
,
9877 "\t.SPACE $PRIVATE$\n"
9878 "\t.NSUBSPA $DATA$,QUAD=1,ALIGN=8,"
9879 "ACCESS=31,SORT=24,COMDAT");
9882 som_tm_clone_table_section
9883 = get_unnamed_section (0, output_section_asm_op
,
9884 "\t.SPACE $PRIVATE$\n\t.SUBSPA $TM_CLONE_TABLE$");
9886 /* FIXME: HPUX ld generates incorrect GOT entries for "T" fixups
9887 which reference data within the $TEXT$ space (for example constant
9888 strings in the $LIT$ subspace).
9890 The assemblers (GAS and HP as) both have problems with handling
9891 the difference of two symbols which is the other correct way to
9892 reference constant data during PIC code generation.
9894 So, there's no way to reference constant data which is in the
9895 $TEXT$ space during PIC generation. Instead place all constant
9896 data into the $PRIVATE$ subspace (this reduces sharing, but it
9897 works correctly). */
9898 readonly_data_section
= flag_pic
? data_section
: som_readonly_data_section
;
9900 /* We must not have a reference to an external symbol defined in a
9901 shared library in a readonly section, else the SOM linker will
9904 So, we force exception information into the data section. */
9905 exception_section
= data_section
;
9908 /* Implement TARGET_ASM_TM_CLONE_TABLE_SECTION. */
9911 pa_som_tm_clone_table_section (void)
9913 return som_tm_clone_table_section
;
9916 /* On hpux10, the linker will give an error if we have a reference
9917 in the read-only data section to a symbol defined in a shared
9918 library. Therefore, expressions that might require a reloc can
9919 not be placed in the read-only data section. */
9922 pa_select_section (tree exp
, int reloc
,
9923 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
9925 if (TREE_CODE (exp
) == VAR_DECL
9926 && TREE_READONLY (exp
)
9927 && !TREE_THIS_VOLATILE (exp
)
9928 && DECL_INITIAL (exp
)
9929 && (DECL_INITIAL (exp
) == error_mark_node
9930 || TREE_CONSTANT (DECL_INITIAL (exp
)))
9934 && DECL_ONE_ONLY (exp
)
9935 && !DECL_WEAK (exp
))
9936 return som_one_only_readonly_data_section
;
9938 return readonly_data_section
;
9940 else if (CONSTANT_CLASS_P (exp
) && !reloc
)
9941 return readonly_data_section
;
9943 && TREE_CODE (exp
) == VAR_DECL
9944 && DECL_ONE_ONLY (exp
)
9945 && !DECL_WEAK (exp
))
9946 return som_one_only_data_section
;
9948 return data_section
;
9952 pa_globalize_label (FILE *stream
, const char *name
)
9954 /* We only handle DATA objects here, functions are globalized in
9955 ASM_DECLARE_FUNCTION_NAME. */
9956 if (! FUNCTION_NAME_P (name
))
9958 fputs ("\t.EXPORT ", stream
);
9959 assemble_name (stream
, name
);
9960 fputs (",DATA\n", stream
);
9964 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9967 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
9968 int incoming ATTRIBUTE_UNUSED
)
9970 return gen_rtx_REG (Pmode
, PA_STRUCT_VALUE_REGNUM
);
9973 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9976 pa_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
9978 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9979 PA64 ABI says that objects larger than 128 bits are returned in memory.
9980 Note, int_size_in_bytes can return -1 if the size of the object is
9981 variable or larger than the maximum value that can be expressed as
9982 a HOST_WIDE_INT. It can also return zero for an empty type. The
9983 simplest way to handle variable and empty types is to pass them in
9984 memory. This avoids problems in defining the boundaries of argument
9985 slots, allocating registers, etc. */
9986 return (int_size_in_bytes (type
) > (TARGET_64BIT
? 16 : 8)
9987 || int_size_in_bytes (type
) <= 0);
9990 /* Structure to hold declaration and name of external symbols that are
9991 emitted by GCC. We generate a vector of these symbols and output them
9992 at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true.
9993 This avoids putting out names that are never really used. */
9995 typedef struct GTY(()) extern_symbol
10001 /* Define gc'd vector type for extern_symbol. */
10003 /* Vector of extern_symbol pointers. */
10004 static GTY(()) vec
<extern_symbol
, va_gc
> *extern_symbols
;
10006 #ifdef ASM_OUTPUT_EXTERNAL_REAL
10007 /* Mark DECL (name NAME) as an external reference (assembler output
10008 file FILE). This saves the names to output at the end of the file
10009 if actually referenced. */
10012 pa_hpux_asm_output_external (FILE *file
, tree decl
, const char *name
)
10014 gcc_assert (file
== asm_out_file
);
10015 extern_symbol p
= {decl
, name
};
10016 vec_safe_push (extern_symbols
, p
);
10019 /* Output text required at the end of an assembler file.
10020 This includes deferred plabels and .import directives for
10021 all external symbols that were actually referenced. */
10024 pa_hpux_file_end (void)
10029 if (!NO_DEFERRED_PROFILE_COUNTERS
)
10030 output_deferred_profile_counters ();
10032 output_deferred_plabels ();
10034 for (i
= 0; vec_safe_iterate (extern_symbols
, i
, &p
); i
++)
10036 tree decl
= p
->decl
;
10038 if (!TREE_ASM_WRITTEN (decl
)
10039 && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl
), 0)))
10040 ASM_OUTPUT_EXTERNAL_REAL (asm_out_file
, decl
, p
->name
);
10043 vec_free (extern_symbols
);
10047 /* Return true if a change from mode FROM to mode TO for a register
10048 in register class RCLASS is invalid. */
10051 pa_cannot_change_mode_class (enum machine_mode from
, enum machine_mode to
,
10052 enum reg_class rclass
)
10057 /* Reject changes to/from complex and vector modes. */
10058 if (COMPLEX_MODE_P (from
) || VECTOR_MODE_P (from
)
10059 || COMPLEX_MODE_P (to
) || VECTOR_MODE_P (to
))
10062 if (GET_MODE_SIZE (from
) == GET_MODE_SIZE (to
))
10065 /* There is no way to load QImode or HImode values directly from
10066 memory. SImode loads to the FP registers are not zero extended.
10067 On the 64-bit target, this conflicts with the definition of
10068 LOAD_EXTEND_OP. Thus, we can't allow changing between modes
10069 with different sizes in the floating-point registers. */
10070 if (MAYBE_FP_REG_CLASS_P (rclass
))
10073 /* HARD_REGNO_MODE_OK places modes with sizes larger than a word
10074 in specific sets of registers. Thus, we cannot allow changing
10075 to a larger mode when it's larger than a word. */
10076 if (GET_MODE_SIZE (to
) > UNITS_PER_WORD
10077 && GET_MODE_SIZE (to
) > GET_MODE_SIZE (from
))
10083 /* Returns TRUE if it is a good idea to tie two pseudo registers
10084 when one has mode MODE1 and one has mode MODE2.
10085 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
10086 for any hard reg, then this must be FALSE for correct output.
10088 We should return FALSE for QImode and HImode because these modes
10089 are not ok in the floating-point registers. However, this prevents
10090 tieing these modes to SImode and DImode in the general registers.
10091 So, this isn't a good idea. We rely on HARD_REGNO_MODE_OK and
10092 CANNOT_CHANGE_MODE_CLASS to prevent these modes from being used
10093 in the floating-point registers. */
10096 pa_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
10098 /* Don't tie modes in different classes. */
10099 if (GET_MODE_CLASS (mode1
) != GET_MODE_CLASS (mode2
))
10106 /* Length in units of the trampoline instruction code. */
10108 #define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40))
10111 /* Output assembler code for a block containing the constant parts
10112 of a trampoline, leaving space for the variable parts.\
10114 The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM
10115 and then branches to the specified routine.
10117 This code template is copied from text segment to stack location
10118 and then patched with pa_trampoline_init to contain valid values,
10119 and then entered as a subroutine.
10121 It is best to keep this as small as possible to avoid having to
10122 flush multiple lines in the cache. */
10125 pa_asm_trampoline_template (FILE *f
)
10129 fputs ("\tldw 36(%r22),%r21\n", f
);
10130 fputs ("\tbb,>=,n %r21,30,.+16\n", f
);
10131 if (ASSEMBLER_DIALECT
== 0)
10132 fputs ("\tdepi 0,31,2,%r21\n", f
);
10134 fputs ("\tdepwi 0,31,2,%r21\n", f
);
10135 fputs ("\tldw 4(%r21),%r19\n", f
);
10136 fputs ("\tldw 0(%r21),%r21\n", f
);
10139 fputs ("\tbve (%r21)\n", f
);
10140 fputs ("\tldw 40(%r22),%r29\n", f
);
10141 fputs ("\t.word 0\n", f
);
10142 fputs ("\t.word 0\n", f
);
10146 fputs ("\tldsid (%r21),%r1\n", f
);
10147 fputs ("\tmtsp %r1,%sr0\n", f
);
10148 fputs ("\tbe 0(%sr0,%r21)\n", f
);
10149 fputs ("\tldw 40(%r22),%r29\n", f
);
10151 fputs ("\t.word 0\n", f
);
10152 fputs ("\t.word 0\n", f
);
10153 fputs ("\t.word 0\n", f
);
10154 fputs ("\t.word 0\n", f
);
10158 fputs ("\t.dword 0\n", f
);
10159 fputs ("\t.dword 0\n", f
);
10160 fputs ("\t.dword 0\n", f
);
10161 fputs ("\t.dword 0\n", f
);
10162 fputs ("\tmfia %r31\n", f
);
10163 fputs ("\tldd 24(%r31),%r1\n", f
);
10164 fputs ("\tldd 24(%r1),%r27\n", f
);
10165 fputs ("\tldd 16(%r1),%r1\n", f
);
10166 fputs ("\tbve (%r1)\n", f
);
10167 fputs ("\tldd 32(%r31),%r31\n", f
);
10168 fputs ("\t.dword 0 ; fptr\n", f
);
10169 fputs ("\t.dword 0 ; static link\n", f
);
10173 /* Emit RTL insns to initialize the variable parts of a trampoline.
10174 FNADDR is an RTX for the address of the function's pure code.
10175 CXT is an RTX for the static chain value for the function.
10177 Move the function address to the trampoline template at offset 36.
10178 Move the static chain value to trampoline template at offset 40.
10179 Move the trampoline address to trampoline template at offset 44.
10180 Move r19 to trampoline template at offset 48. The latter two
10181 words create a plabel for the indirect call to the trampoline.
10183 A similar sequence is used for the 64-bit port but the plabel is
10184 at the beginning of the trampoline.
10186 Finally, the cache entries for the trampoline code are flushed.
10187 This is necessary to ensure that the trampoline instruction sequence
10188 is written to memory prior to any attempts at prefetching the code
10192 pa_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
10194 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
10195 rtx start_addr
= gen_reg_rtx (Pmode
);
10196 rtx end_addr
= gen_reg_rtx (Pmode
);
10197 rtx line_length
= gen_reg_rtx (Pmode
);
10200 emit_block_move (m_tramp
, assemble_trampoline_template (),
10201 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
10202 r_tramp
= force_reg (Pmode
, XEXP (m_tramp
, 0));
10206 tmp
= adjust_address (m_tramp
, Pmode
, 36);
10207 emit_move_insn (tmp
, fnaddr
);
10208 tmp
= adjust_address (m_tramp
, Pmode
, 40);
10209 emit_move_insn (tmp
, chain_value
);
10211 /* Create a fat pointer for the trampoline. */
10212 tmp
= adjust_address (m_tramp
, Pmode
, 44);
10213 emit_move_insn (tmp
, r_tramp
);
10214 tmp
= adjust_address (m_tramp
, Pmode
, 48);
10215 emit_move_insn (tmp
, gen_rtx_REG (Pmode
, 19));
10217 /* fdc and fic only use registers for the address to flush,
10218 they do not accept integer displacements. We align the
10219 start and end addresses to the beginning of their respective
10220 cache lines to minimize the number of lines flushed. */
10221 emit_insn (gen_andsi3 (start_addr
, r_tramp
,
10222 GEN_INT (-MIN_CACHELINE_SIZE
)));
10223 tmp
= force_reg (Pmode
, plus_constant (Pmode
, r_tramp
,
10224 TRAMPOLINE_CODE_SIZE
-1));
10225 emit_insn (gen_andsi3 (end_addr
, tmp
,
10226 GEN_INT (-MIN_CACHELINE_SIZE
)));
10227 emit_move_insn (line_length
, GEN_INT (MIN_CACHELINE_SIZE
));
10228 emit_insn (gen_dcacheflushsi (start_addr
, end_addr
, line_length
));
10229 emit_insn (gen_icacheflushsi (start_addr
, end_addr
, line_length
,
10230 gen_reg_rtx (Pmode
),
10231 gen_reg_rtx (Pmode
)));
10235 tmp
= adjust_address (m_tramp
, Pmode
, 56);
10236 emit_move_insn (tmp
, fnaddr
);
10237 tmp
= adjust_address (m_tramp
, Pmode
, 64);
10238 emit_move_insn (tmp
, chain_value
);
10240 /* Create a fat pointer for the trampoline. */
10241 tmp
= adjust_address (m_tramp
, Pmode
, 16);
10242 emit_move_insn (tmp
, force_reg (Pmode
, plus_constant (Pmode
,
10244 tmp
= adjust_address (m_tramp
, Pmode
, 24);
10245 emit_move_insn (tmp
, gen_rtx_REG (Pmode
, 27));
10247 /* fdc and fic only use registers for the address to flush,
10248 they do not accept integer displacements. We align the
10249 start and end addresses to the beginning of their respective
10250 cache lines to minimize the number of lines flushed. */
10251 tmp
= force_reg (Pmode
, plus_constant (Pmode
, r_tramp
, 32));
10252 emit_insn (gen_anddi3 (start_addr
, tmp
,
10253 GEN_INT (-MIN_CACHELINE_SIZE
)));
10254 tmp
= force_reg (Pmode
, plus_constant (Pmode
, tmp
,
10255 TRAMPOLINE_CODE_SIZE
- 1));
10256 emit_insn (gen_anddi3 (end_addr
, tmp
,
10257 GEN_INT (-MIN_CACHELINE_SIZE
)));
10258 emit_move_insn (line_length
, GEN_INT (MIN_CACHELINE_SIZE
));
10259 emit_insn (gen_dcacheflushdi (start_addr
, end_addr
, line_length
));
10260 emit_insn (gen_icacheflushdi (start_addr
, end_addr
, line_length
,
10261 gen_reg_rtx (Pmode
),
10262 gen_reg_rtx (Pmode
)));
10266 /* Perform any machine-specific adjustment in the address of the trampoline.
10267 ADDR contains the address that was passed to pa_trampoline_init.
10268 Adjust the trampoline address to point to the plabel at offset 44. */
10271 pa_trampoline_adjust_address (rtx addr
)
10274 addr
= memory_address (Pmode
, plus_constant (Pmode
, addr
, 46));
10279 pa_delegitimize_address (rtx orig_x
)
10281 rtx x
= delegitimize_mem_from_attrs (orig_x
);
10283 if (GET_CODE (x
) == LO_SUM
10284 && GET_CODE (XEXP (x
, 1)) == UNSPEC
10285 && XINT (XEXP (x
, 1), 1) == UNSPEC_DLTIND14R
)
10286 return gen_const_mem (Pmode
, XVECEXP (XEXP (x
, 1), 0, 0));
10291 pa_internal_arg_pointer (void)
10293 /* The argument pointer and the hard frame pointer are the same in
10294 the 32-bit runtime, so we don't need a copy. */
10296 return copy_to_reg (virtual_incoming_args_rtx
);
10298 return virtual_incoming_args_rtx
;
10301 /* Given FROM and TO register numbers, say whether this elimination is allowed.
10302 Frame pointer elimination is automatically handled. */
10305 pa_can_eliminate (const int from
, const int to
)
10307 /* The argument cannot be eliminated in the 64-bit runtime. */
10308 if (TARGET_64BIT
&& from
== ARG_POINTER_REGNUM
)
10311 return (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
10312 ? ! frame_pointer_needed
10316 /* Define the offset between two registers, FROM to be eliminated and its
10317 replacement TO, at the start of a routine. */
10319 pa_initial_elimination_offset (int from
, int to
)
10321 HOST_WIDE_INT offset
;
10323 if ((from
== HARD_FRAME_POINTER_REGNUM
|| from
== FRAME_POINTER_REGNUM
)
10324 && to
== STACK_POINTER_REGNUM
)
10325 offset
= -pa_compute_frame_size (get_frame_size (), 0);
10326 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
10329 gcc_unreachable ();
10335 pa_conditional_register_usage (void)
10339 if (!TARGET_64BIT
&& !TARGET_PA_11
)
10341 for (i
= 56; i
<= FP_REG_LAST
; i
++)
10342 fixed_regs
[i
] = call_used_regs
[i
] = 1;
10343 for (i
= 33; i
< 56; i
+= 2)
10344 fixed_regs
[i
] = call_used_regs
[i
] = 1;
10346 if (TARGET_DISABLE_FPREGS
|| TARGET_SOFT_FLOAT
)
10348 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
10349 fixed_regs
[i
] = call_used_regs
[i
] = 1;
10352 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
10355 /* Target hook for c_mode_for_suffix. */
10357 static enum machine_mode
10358 pa_c_mode_for_suffix (char suffix
)
10360 if (HPUX_LONG_DOUBLE_LIBRARY
)
10369 /* Target hook for function_section. */
10372 pa_function_section (tree decl
, enum node_frequency freq
,
10373 bool startup
, bool exit
)
10375 /* Put functions in text section if target doesn't have named sections. */
10376 if (!targetm_common
.have_named_sections
)
10377 return text_section
;
10379 /* Force nested functions into the same section as the containing
10382 && DECL_SECTION_NAME (decl
) == NULL_TREE
10383 && DECL_CONTEXT (decl
) != NULL_TREE
10384 && TREE_CODE (DECL_CONTEXT (decl
)) == FUNCTION_DECL
10385 && DECL_SECTION_NAME (DECL_CONTEXT (decl
)) == NULL_TREE
)
10386 return function_section (DECL_CONTEXT (decl
));
10388 /* Otherwise, use the default function section. */
10389 return default_function_section (decl
, freq
, startup
, exit
);
10392 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
10394 In 64-bit mode, we reject CONST_DOUBLES. We also reject CONST_INTS
10395 that need more than three instructions to load prior to reload. This
10396 limit is somewhat arbitrary. It takes three instructions to load a
10397 CONST_INT from memory but two are memory accesses. It may be better
10398 to increase the allowed range for CONST_INTS. We may also be able
10399 to handle CONST_DOUBLES. */
10402 pa_legitimate_constant_p (enum machine_mode mode
, rtx x
)
10404 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& x
!= CONST0_RTX (mode
))
10407 if (!NEW_HP_ASSEMBLER
&& !TARGET_GAS
&& GET_CODE (x
) == LABEL_REF
)
10410 /* TLS_MODEL_GLOBAL_DYNAMIC and TLS_MODEL_LOCAL_DYNAMIC are not
10411 legitimate constants. The other variants can't be handled by
10412 the move patterns after reload starts. */
10413 if (pa_tls_referenced_p (x
))
10416 if (TARGET_64BIT
&& GET_CODE (x
) == CONST_DOUBLE
)
10420 && HOST_BITS_PER_WIDE_INT
> 32
10421 && GET_CODE (x
) == CONST_INT
10422 && !reload_in_progress
10423 && !reload_completed
10424 && !LEGITIMATE_64BIT_CONST_INT_P (INTVAL (x
))
10425 && !pa_cint_ok_for_move (INTVAL (x
)))
10428 if (function_label_operand (x
, mode
))
10434 /* Implement TARGET_SECTION_TYPE_FLAGS. */
10436 static unsigned int
10437 pa_section_type_flags (tree decl
, const char *name
, int reloc
)
10439 unsigned int flags
;
10441 flags
= default_section_type_flags (decl
, name
, reloc
);
10443 /* Function labels are placed in the constant pool. This can
10444 cause a section conflict if decls are put in ".data.rel.ro"
10445 or ".data.rel.ro.local" using the __attribute__ construct. */
10446 if (strcmp (name
, ".data.rel.ro") == 0
10447 || strcmp (name
, ".data.rel.ro.local") == 0)
10448 flags
|= SECTION_WRITE
| SECTION_RELRO
;
10453 /* pa_legitimate_address_p recognizes an RTL expression that is a
10454 valid memory address for an instruction. The MODE argument is the
10455 machine mode for the MEM expression that wants to use this address.
10457 On HP PA-RISC, the legitimate address forms are REG+SMALLINT,
10458 REG+REG, and REG+(REG*SCALE). The indexed address forms are only
10459 available with floating point loads and stores, and integer loads.
10460 We get better code by allowing indexed addresses in the initial
10463 The acceptance of indexed addresses as legitimate implies that we
10464 must provide patterns for doing indexed integer stores, or the move
10465 expanders must force the address of an indexed store to a register.
10466 We have adopted the latter approach.
10468 Another function of pa_legitimate_address_p is to ensure that
10469 the base register is a valid pointer for indexed instructions.
10470 On targets that have non-equivalent space registers, we have to
10471 know at the time of assembler output which register in a REG+REG
10472 pair is the base register. The REG_POINTER flag is sometimes lost
10473 in reload and the following passes, so it can't be relied on during
10474 code generation. Thus, we either have to canonicalize the order
10475 of the registers in REG+REG indexed addresses, or treat REG+REG
10476 addresses separately and provide patterns for both permutations.
10478 The latter approach requires several hundred additional lines of
10479 code in pa.md. The downside to canonicalizing is that a PLUS
10480 in the wrong order can't combine to form to make a scaled indexed
10481 memory operand. As we won't need to canonicalize the operands if
10482 the REG_POINTER lossage can be fixed, it seems better canonicalize.
10484 We initially break out scaled indexed addresses in canonical order
10485 in pa_emit_move_sequence. LEGITIMIZE_ADDRESS also canonicalizes
10486 scaled indexed addresses during RTL generation. However, fold_rtx
10487 has its own opinion on how the operands of a PLUS should be ordered.
10488 If one of the operands is equivalent to a constant, it will make
10489 that operand the second operand. As the base register is likely to
10490 be equivalent to a SYMBOL_REF, we have made it the second operand.
10492 pa_legitimate_address_p accepts REG+REG as legitimate when the
10493 operands are in the order INDEX+BASE on targets with non-equivalent
10494 space registers, and in any order on targets with equivalent space
10495 registers. It accepts both MULT+BASE and BASE+MULT for scaled indexing.
10497 We treat a SYMBOL_REF as legitimate if it is part of the current
10498 function's constant-pool, because such addresses can actually be
10499 output as REG+SMALLINT. */
10502 pa_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
10505 && (strict
? STRICT_REG_OK_FOR_BASE_P (x
)
10506 : REG_OK_FOR_BASE_P (x
)))
10507 || ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_DEC
10508 || GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == POST_INC
)
10509 && REG_P (XEXP (x
, 0))
10510 && (strict
? STRICT_REG_OK_FOR_BASE_P (XEXP (x
, 0))
10511 : REG_OK_FOR_BASE_P (XEXP (x
, 0)))))
10514 if (GET_CODE (x
) == PLUS
)
10518 /* For REG+REG, the base register should be in XEXP (x, 1),
10519 so check it first. */
10520 if (REG_P (XEXP (x
, 1))
10521 && (strict
? STRICT_REG_OK_FOR_BASE_P (XEXP (x
, 1))
10522 : REG_OK_FOR_BASE_P (XEXP (x
, 1))))
10523 base
= XEXP (x
, 1), index
= XEXP (x
, 0);
10524 else if (REG_P (XEXP (x
, 0))
10525 && (strict
? STRICT_REG_OK_FOR_BASE_P (XEXP (x
, 0))
10526 : REG_OK_FOR_BASE_P (XEXP (x
, 0))))
10527 base
= XEXP (x
, 0), index
= XEXP (x
, 1);
10531 if (GET_CODE (index
) == CONST_INT
)
10533 if (INT_5_BITS (index
))
10536 /* When INT14_OK_STRICT is false, a secondary reload is needed
10537 to adjust the displacement of SImode and DImode floating point
10538 instructions but this may fail when the register also needs
10539 reloading. So, we return false when STRICT is true. We
10540 also reject long displacements for float mode addresses since
10541 the majority of accesses will use floating point instructions
10542 that don't support 14-bit offsets. */
10543 if (!INT14_OK_STRICT
10544 && (strict
|| !(reload_in_progress
|| reload_completed
))
10549 return base14_operand (index
, mode
);
10552 if (!TARGET_DISABLE_INDEXING
10553 /* Only accept the "canonical" INDEX+BASE operand order
10554 on targets with non-equivalent space registers. */
10555 && (TARGET_NO_SPACE_REGS
10557 : (base
== XEXP (x
, 1) && REG_P (index
)
10558 && (reload_completed
10559 || (reload_in_progress
&& HARD_REGISTER_P (base
))
10560 || REG_POINTER (base
))
10561 && (reload_completed
10562 || (reload_in_progress
&& HARD_REGISTER_P (index
))
10563 || !REG_POINTER (index
))))
10564 && MODE_OK_FOR_UNSCALED_INDEXING_P (mode
)
10565 && (strict
? STRICT_REG_OK_FOR_INDEX_P (index
)
10566 : REG_OK_FOR_INDEX_P (index
))
10567 && borx_reg_operand (base
, Pmode
)
10568 && borx_reg_operand (index
, Pmode
))
10571 if (!TARGET_DISABLE_INDEXING
10572 && GET_CODE (index
) == MULT
10573 && MODE_OK_FOR_SCALED_INDEXING_P (mode
)
10574 && REG_P (XEXP (index
, 0))
10575 && GET_MODE (XEXP (index
, 0)) == Pmode
10576 && (strict
? STRICT_REG_OK_FOR_INDEX_P (XEXP (index
, 0))
10577 : REG_OK_FOR_INDEX_P (XEXP (index
, 0)))
10578 && GET_CODE (XEXP (index
, 1)) == CONST_INT
10579 && INTVAL (XEXP (index
, 1))
10580 == (HOST_WIDE_INT
) GET_MODE_SIZE (mode
)
10581 && borx_reg_operand (base
, Pmode
))
10587 if (GET_CODE (x
) == LO_SUM
)
10589 rtx y
= XEXP (x
, 0);
10591 if (GET_CODE (y
) == SUBREG
)
10592 y
= SUBREG_REG (y
);
10595 && (strict
? STRICT_REG_OK_FOR_BASE_P (y
)
10596 : REG_OK_FOR_BASE_P (y
)))
10598 /* Needed for -fPIC */
10600 && GET_CODE (XEXP (x
, 1)) == UNSPEC
)
10603 if (!INT14_OK_STRICT
10604 && (strict
|| !(reload_in_progress
|| reload_completed
))
10609 if (CONSTANT_P (XEXP (x
, 1)))
10615 if (GET_CODE (x
) == CONST_INT
&& INT_5_BITS (x
))
10621 /* Look for machine dependent ways to make the invalid address AD a
10624 For the PA, transform:
10626 memory(X + <large int>)
10630 if (<large int> & mask) >= 16
10631 Y = (<large int> & ~mask) + mask + 1 Round up.
10633 Y = (<large int> & ~mask) Round down.
10635 memory (Z + (<large int> - Y));
10637 This makes reload inheritance and reload_cse work better since Z
10640 There may be more opportunities to improve code with this hook. */
10643 pa_legitimize_reload_address (rtx ad
, enum machine_mode mode
,
10644 int opnum
, int type
,
10645 int ind_levels ATTRIBUTE_UNUSED
)
10647 long offset
, newoffset
, mask
;
10648 rtx new_rtx
, temp
= NULL_RTX
;
10650 mask
= (GET_MODE_CLASS (mode
) == MODE_FLOAT
10651 && !INT14_OK_STRICT
? 0x1f : 0x3fff);
10653 if (optimize
&& GET_CODE (ad
) == PLUS
)
10654 temp
= simplify_binary_operation (PLUS
, Pmode
,
10655 XEXP (ad
, 0), XEXP (ad
, 1));
10657 new_rtx
= temp
? temp
: ad
;
10660 && GET_CODE (new_rtx
) == PLUS
10661 && GET_CODE (XEXP (new_rtx
, 0)) == REG
10662 && GET_CODE (XEXP (new_rtx
, 1)) == CONST_INT
)
10664 offset
= INTVAL (XEXP ((new_rtx
), 1));
10666 /* Choose rounding direction. Round up if we are >= halfway. */
10667 if ((offset
& mask
) >= ((mask
+ 1) / 2))
10668 newoffset
= (offset
& ~mask
) + mask
+ 1;
10670 newoffset
= offset
& ~mask
;
10672 /* Ensure that long displacements are aligned. */
10674 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
10675 || (TARGET_64BIT
&& (mode
) == DImode
)))
10676 newoffset
&= ~(GET_MODE_SIZE (mode
) - 1);
10678 if (newoffset
!= 0 && VAL_14_BITS_P (newoffset
))
10680 temp
= gen_rtx_PLUS (Pmode
, XEXP (new_rtx
, 0),
10681 GEN_INT (newoffset
));
10682 ad
= gen_rtx_PLUS (Pmode
, temp
, GEN_INT (offset
- newoffset
));
10683 push_reload (XEXP (ad
, 0), 0, &XEXP (ad
, 0), 0,
10684 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
10685 opnum
, (enum reload_type
) type
);