1 ;;- Machine description for Renesas / SuperH SH.
2 ;; Copyright (C) 1993-2014 Free Software Foundation, Inc.
3 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
4 ;; Improved by Jim Wilson (wilson@cygnus.com).
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
23 ;; ??? Should prepend a * to all pattern names which are not used.
24 ;; This will make the compiler smaller, and rebuilds after changes faster.
26 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
27 ;; sequences. Especially the sequences for arithmetic right shifts.
29 ;; ??? Should check all DImode patterns for consistency and usefulness.
31 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
32 ;; way to generate them.
34 ;; BSR is not generated by the compiler proper, but when relaxing, it
35 ;; generates .uses pseudo-ops that allow linker relaxation to create
36 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
38 ;; Special constraints for SH machine description:
45 ;; Special formats used for outputting SH instructions:
47 ;; %. -- print a .s if insn needs delay slot
48 ;; %@ -- print rte/rts if is/isn't an interrupt function
49 ;; %# -- output a nop if there is nothing to put in the delay slot
50 ;; %O -- print a constant without the #
51 ;; %R -- print the lsw reg of a double
52 ;; %S -- print the msw reg of a double
53 ;; %T -- print next word of a double REG or MEM
55 ;; Special predicates:
57 ;; arith_operand -- operand is valid source for arithmetic op
58 ;; arith_reg_operand -- operand is valid register for arithmetic op
59 ;; general_movdst_operand -- operand is valid move destination
60 ;; general_movsrc_operand -- operand is valid move source
61 ;; logical_operand -- operand is valid source for logical op
63 ;; -------------------------------------------------------------------------
65 ;; -------------------------------------------------------------------------
79 ;; Virtual FPSCR - bits that are used by FP ops.
82 ;; Virtual FPSCR - bits that are updated by FP ops.
119 (FPSCR_PR 524288) ;; 1 << 19
120 (FPSCR_SZ 1048576) ;; 1 << 20
121 (FPSCR_FR 2097152) ;; 1 << 21
124 (define_c_enum "unspec" [
125 ;; These are used with unspec.
164 ;; (unspec [VAL SHIFT] UNSPEC_EXTRACT_S16) computes (short) (VAL >> SHIFT).
165 ;; UNSPEC_EXTRACT_U16 is the unsigned equivalent.
168 ;; (unspec [TARGET ANCHOR] UNSPEC_SYMOFF) == TARGET - ANCHOR.
170 ;; (unspec [OFFSET ANCHOR] UNSPEC_PCREL_SYMOFF) == OFFSET - (ANCHOR - .).
173 UNSPEC_BUILTIN_STRLEN
176 (define_c_enum "unspecv" [
177 ;; These are used with unspec_volatile.
194 ;; -------------------------------------------------------------------------
196 ;; -------------------------------------------------------------------------
201 "sh1,sh2,sh2e,sh2a,sh3,sh3e,sh4,sh4a,sh5"
202 (const (symbol_ref "sh_cpu_attr")))
204 (define_attr "endian" "big,little"
205 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
206 (const_string "little") (const_string "big"))))
208 ;; Indicate if the default fpu mode is single precision.
209 (define_attr "fpu_single" "yes,no"
210 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
211 (const_string "yes") (const_string "no"))))
213 (define_attr "fmovd" "yes,no"
214 (const (if_then_else (symbol_ref "TARGET_FMOVD")
215 (const_string "yes") (const_string "no"))))
217 (define_attr "pipe_model" "sh1,sh4,sh5media"
219 (cond [(symbol_ref "TARGET_SHMEDIA") (const_string "sh5media")
220 (symbol_ref "TARGET_SUPERSCALAR") (const_string "sh4")]
221 (const_string "sh1"))))
223 ;; cbranch conditional branch instructions
224 ;; jump unconditional jumps
225 ;; arith ordinary arithmetic
226 ;; arith3 a compound insn that behaves similarly to a sequence of
227 ;; three insns of type arith
228 ;; arith3b like above, but might end with a redirected branch
230 ;; load_si Likewise, SImode variant for general register.
231 ;; fload Likewise, but load to fp register.
233 ;; fstore floating point register to memory
234 ;; move general purpose register to register
235 ;; movi8 8-bit immediate to general purpose register
236 ;; mt_group other sh4 mt instructions
237 ;; fmove register to register, floating point
238 ;; smpy word precision integer multiply
239 ;; dmpy longword or doublelongword precision integer multiply
241 ;; pload load of pr reg, which can't be put into delay slot of rts
242 ;; prset copy register to pr reg, ditto
243 ;; pstore store of pr reg, which can't be put into delay slot of jsr
244 ;; prget copy pr to register, ditto
245 ;; pcload pc relative load of constant value
246 ;; pcfload Likewise, but load to fp register.
247 ;; pcload_si Likewise, SImode variant for general register.
248 ;; rte return from exception
249 ;; sfunc special function call with known used registers
250 ;; call function call
252 ;; fpscr_toggle toggle a bit in the fpscr
253 ;; fdiv floating point divide (or square root)
254 ;; gp_fpul move from general purpose register to fpul
255 ;; fpul_gp move from fpul to general purpose register
256 ;; mac_gp move from mac[lh] to general purpose register
257 ;; gp_mac move from general purpose register to mac[lh]
258 ;; mac_mem move from mac[lh] to memory
259 ;; mem_mac move from memory to mac[lh]
260 ;; dfp_arith,dfp_mul, fp_cmp,dfp_cmp,dfp_conv
261 ;; ftrc_s fix_truncsfsi2_i4
262 ;; dfdiv double precision floating point divide (or square root)
263 ;; cwb ic_invalidate_line_i
264 ;; movua SH4a unaligned load
265 ;; fsrra square root reciprocal approximate
266 ;; fsca sine and cosine approximate
267 ;; tls_load load TLS related address
268 ;; arith_media SHmedia arithmetic, logical, and shift instructions
269 ;; cbranch_media SHmedia conditional branch instructions
270 ;; cmp_media SHmedia compare instructions
271 ;; dfdiv_media SHmedia double precision divide and square root
272 ;; dfmul_media SHmedia double precision multiply instruction
273 ;; dfparith_media SHmedia double precision floating point arithmetic
274 ;; dfpconv_media SHmedia double precision floating point conversions
275 ;; dmpy_media SHmedia longword multiply
276 ;; fcmp_media SHmedia floating point compare instructions
277 ;; fdiv_media SHmedia single precision divide and square root
278 ;; fload_media SHmedia floating point register load instructions
279 ;; fmove_media SHmedia floating point register moves (inc. fabs and fneg)
280 ;; fparith_media SHmedia single precision floating point arithmetic
281 ;; fpconv_media SHmedia single precision floating point conversions
282 ;; fstore_media SHmedia floating point register store instructions
283 ;; gettr_media SHmedia gettr instruction
284 ;; invalidate_line_media SHmedia invalidate_line sequence
285 ;; jump_media SHmedia unconditional branch instructions
286 ;; load_media SHmedia general register load instructions
287 ;; pt_media SHmedia pt instruction (expanded by assembler)
288 ;; ptabs_media SHmedia ptabs instruction
289 ;; store_media SHmedia general register store instructions
290 ;; mcmp_media SHmedia multimedia compare, absolute, saturating ops
291 ;; mac_media SHmedia mac-style fixed point operations
292 ;; d2mpy_media SHmedia: two 32-bit integer multiplies
293 ;; atrans_media SHmedia approximate transcendental functions
294 ;; ustore_media SHmedia unaligned stores
295 ;; nil no-op move, will be deleted.
298 "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,
299 fload,store,fstore,move,movi8,fmove,smpy,dmpy,return,pload,prset,pstore,
300 prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fpscr_toggle,fdiv,ftrc_s,
301 dfp_arith,dfp_mul,fp_cmp,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,
302 gp_mac,mac_mem,mem_mac,mem_fpscr,gp_fpscr,cwb,movua,fsrra,fsca,tls_load,
303 arith_media,cbranch_media,cmp_media,dfdiv_media,dfmul_media,dfparith_media,
304 dfpconv_media,dmpy_media,fcmp_media,fdiv_media,fload_media,fmove_media,
305 fparith_media,fpconv_media,fstore_media,gettr_media,invalidate_line_media,
306 jump_media,load_media,pt_media,ptabs_media,store_media,mcmp_media,mac_media,
307 d2mpy_media,atrans_media,ustore_media,nil,other"
308 (const_string "other"))
310 ;; We define a new attribute namely "insn_class".We use
311 ;; this for the DFA based pipeline description.
313 ;; mt_group SH4 "mt" group instructions.
315 ;; ex_group SH4 "ex" group instructions.
317 ;; ls_group SH4 "ls" group instructions.
319 (define_attr "insn_class"
320 "mt_group,ex_group,ls_group,br_group,fe_group,co_group,none"
321 (cond [(eq_attr "type" "move,mt_group") (const_string "mt_group")
322 (eq_attr "type" "movi8,arith,dyn_shift") (const_string "ex_group")
323 (eq_attr "type" "fmove,load,pcload,load_si,pcload_si,fload,pcfload,
324 store,fstore,gp_fpul,fpul_gp") (const_string "ls_group")
325 (eq_attr "type" "cbranch,jump") (const_string "br_group")
326 (eq_attr "type" "fp,fp_cmp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
327 (const_string "fe_group")
328 (eq_attr "type" "jump_ind,smpy,dmpy,mac_gp,return,pload,prset,pstore,
329 prget,rte,sfunc,call,dfp_cmp,mem_fpscr,gp_fpscr,cwb,
330 gp_mac,mac_mem,mem_mac") (const_string "co_group")]
331 (const_string "none")))
333 ;; nil are zero instructions, and arith3 / arith3b are multiple instructions,
334 ;; so these do not belong in an insn group, although they are modeled
335 ;; with their own define_insn_reservations.
337 ;; Indicate what precision must be selected in fpscr for this insn, if any.
338 (define_attr "fp_mode" "single,double,none" (const_string "none"))
340 ;; Indicate if the fpu mode is set by this instruction
341 ;; "unknown" must have the value as "none" in fp_mode, and means
342 ;; that the instruction/abi has left the processor in an unknown
344 ;; "none" means that nothing has changed and no mode is set.
345 ;; This attribute is only used for the Renesas ABI.
346 (define_attr "fp_set" "single,double,unknown,none" (const_string "none"))
348 ; If a conditional branch destination is within -252..258 bytes away
349 ; from the instruction it can be 2 bytes long. Something in the
350 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
351 ; branches are initially assumed to be 16 bytes long.
352 ; In machine_dependent_reorg, we split all branches that are longer than
355 ;; The maximum range used for SImode constant pool entries is 1018. A final
356 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
357 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
358 ;; instruction around the pool table, 2 bytes of alignment before the table,
359 ;; and 30 bytes of alignment after the table. That gives a maximum total
360 ;; pool size of 1058 bytes.
361 ;; Worst case code/pool content size ratio is 1:2 (using asms).
362 ;; Thus, in the worst case, there is one instruction in front of a maximum
363 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
364 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
365 ;; If we have a forward branch, the initial table will be put after the
366 ;; unconditional branch.
368 ;; ??? We could do much better by keeping track of the actual pcloads within
369 ;; the branch range and in the pcload range in front of the branch range.
371 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
373 (define_attr "short_cbranch_p" "no,yes"
374 (cond [(match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
376 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
378 (match_test "NEXT_INSN (PREV_INSN (insn)) != insn")
380 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
382 ] (const_string "no")))
384 (define_attr "med_branch_p" "no,yes"
385 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
388 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
390 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
393 ] (const_string "no")))
395 (define_attr "med_cbranch_p" "no,yes"
396 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
399 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
401 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
404 ] (const_string "no")))
406 (define_attr "braf_branch_p" "no,yes"
407 (cond [(match_test "! TARGET_SH2")
409 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
412 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
414 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
417 ] (const_string "no")))
419 (define_attr "braf_cbranch_p" "no,yes"
420 (cond [(match_test "! TARGET_SH2")
422 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
425 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
427 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
430 ] (const_string "no")))
432 ;; An unconditional jump in the range -4092..4098 can be 2 bytes long.
433 ;; For wider ranges, we need a combination of a code and a data part.
434 ;; If we can get a scratch register for a long range jump, the code
435 ;; part can be 4 bytes long; otherwise, it must be 8 bytes long.
436 ;; If the jump is in the range -32764..32770, the data part can be 2 bytes
437 ;; long; otherwise, it must be 6 bytes long.
439 ;; All other instructions are two bytes long by default.
441 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
442 ;; but getattrtab doesn't understand this.
443 (define_attr "length" ""
444 (cond [(eq_attr "type" "cbranch")
445 (cond [(eq_attr "short_cbranch_p" "yes")
447 (eq_attr "med_cbranch_p" "yes")
449 (eq_attr "braf_cbranch_p" "yes")
451 ;; ??? using pc is not computed transitively.
452 (ne (match_dup 0) (match_dup 0))
454 (match_test "flag_pic")
457 (eq_attr "type" "jump")
458 (cond [(eq_attr "med_branch_p" "yes")
460 (and (match_test "prev_nonnote_insn (insn)")
461 (and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))")
463 (eq (symbol_ref "INSN_CODE (prev_nonnote_insn (insn))")
464 (symbol_ref "code_for_indirect_jump_scratch"))))
465 (cond [(eq_attr "braf_branch_p" "yes")
467 (not (match_test "flag_pic"))
469 (match_test "TARGET_SH2")
470 (const_int 10)] (const_int 18))
471 (eq_attr "braf_branch_p" "yes")
473 ;; ??? using pc is not computed transitively.
474 (ne (match_dup 0) (match_dup 0))
476 (match_test "flag_pic")
479 (eq_attr "type" "pt_media")
480 (if_then_else (match_test "TARGET_SHMEDIA64")
481 (const_int 20) (const_int 12))
482 (and (eq_attr "type" "jump_media")
483 (match_test "TARGET_SH5_CUT2_WORKAROUND"))
485 ] (if_then_else (match_test "TARGET_SHMEDIA")
489 ;; DFA descriptions for the pipelines
492 (include "shmedia.md")
495 (include "iterators.md")
496 (include "predicates.md")
497 (include "constraints.md")
499 ;; Definitions for filling delay slots
501 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
503 (define_attr "banked" "yes,no"
504 (cond [(match_test "sh_loads_bankedreg_p (insn)")
505 (const_string "yes")]
506 (const_string "no")))
508 ;; ??? This should be (nil) instead of (const_int 0)
509 (define_attr "hit_stack" "yes,no"
510 (cond [(not (match_test "find_regno_note (insn, REG_INC, SP_REG)"))
512 (const_string "yes")))
514 (define_attr "interrupt_function" "no,yes"
515 (const (symbol_ref "current_function_interrupt")))
517 (define_attr "in_delay_slot" "yes,no"
518 (cond [(eq_attr "type" "cbranch") (const_string "no")
519 (eq_attr "type" "pcload,pcload_si") (const_string "no")
520 (eq_attr "type" "fpscr_toggle") (const_string "no")
521 (eq_attr "needs_delay_slot" "yes") (const_string "no")
522 (eq_attr "length" "2") (const_string "yes")
523 ] (const_string "no")))
525 (define_attr "cond_delay_slot" "yes,no"
526 (cond [(eq_attr "in_delay_slot" "yes") (const_string "yes")
527 ] (const_string "no")))
529 (define_attr "is_sfunc" ""
530 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
532 (define_attr "is_mac_media" ""
533 (if_then_else (eq_attr "type" "mac_media") (const_int 1) (const_int 0)))
535 (define_attr "branch_zero" "yes,no"
536 (cond [(eq_attr "type" "!cbranch") (const_string "no")
537 (ne (symbol_ref "(next_active_insn (insn)\
538 == (prev_active_insn\
539 (XEXP (SET_SRC (PATTERN (insn)), 1))))\
540 && get_attr_length (next_active_insn (insn)) == 2")
542 (const_string "yes")]
543 (const_string "no")))
545 ;; SH4 Double-precision computation with double-precision result -
546 ;; the two halves are ready at different times.
547 (define_attr "dfp_comp" "yes,no"
548 (cond [(eq_attr "type" "dfp_arith,dfp_mul,dfp_conv,dfdiv") (const_string "yes")]
549 (const_string "no")))
551 ;; Insns for which the latency of a preceding fp insn is decreased by one.
552 (define_attr "late_fp_use" "yes,no" (const_string "no"))
553 ;; And feeding insns for which this relevant.
554 (define_attr "any_fp_comp" "yes,no"
555 (cond [(eq_attr "type" "fp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
556 (const_string "yes")]
557 (const_string "no")))
559 (define_attr "any_int_load" "yes,no"
560 (cond [(eq_attr "type" "load,load_si,pcload,pcload_si")
561 (const_string "yes")]
562 (const_string "no")))
564 (define_attr "highpart" "user, ignore, extend, depend, must_split"
565 (const_string "user"))
568 (eq_attr "needs_delay_slot" "yes")
569 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
571 ;; Since a normal return (rts) implicitly uses the PR register,
572 ;; we can't allow PR register loads in an rts delay slot.
573 ;; On the SH1* and SH2*, the rte instruction reads the return pc from the
574 ;; stack, and thus we can't put a pop instruction in its delay slot.
575 ;; On the SH3* and SH4*, the rte instruction does not use the stack, so a
576 ;; pop instruction can go in the delay slot, unless it references a banked
577 ;; register (the register bank is switched by rte).
579 (eq_attr "type" "return")
580 [(and (eq_attr "in_delay_slot" "yes")
581 (ior (and (eq_attr "interrupt_function" "no")
582 (eq_attr "type" "!pload,prset"))
583 (and (eq_attr "interrupt_function" "yes")
584 (ior (match_test "TARGET_SH3") (eq_attr "hit_stack" "no"))
585 (eq_attr "banked" "no"))))
588 ;; Since a call implicitly uses the PR register, we can't allow
589 ;; a PR register store in a jsr delay slot.
592 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
593 [(and (eq_attr "in_delay_slot" "yes")
594 (eq_attr "type" "!pstore,prget")) (nil) (nil)])
596 ;; Say that we have annulled true branches, since this gives smaller and
597 ;; faster code when branches are predicted as not taken.
599 ;; ??? The non-annulled condition should really be "in_delay_slot",
600 ;; but insns that can be filled in non-annulled get priority over insns
601 ;; that can only be filled in anulled.
604 (and (eq_attr "type" "cbranch")
605 (match_test "TARGET_SH2"))
606 ;; SH2e has a hardware bug that pretty much prohibits the use of
607 ;; annulled delay slots.
608 [(eq_attr "cond_delay_slot" "yes") (and (eq_attr "cond_delay_slot" "yes")
609 (not (eq_attr "cpu" "sh2e"))) (nil)])
611 ;; -------------------------------------------------------------------------
612 ;; SImode signed integer comparisons
613 ;; -------------------------------------------------------------------------
615 ;; Various patterns to generate the TST #imm, R0 instruction.
616 ;; Although this adds some pressure on the R0 register, it can potentially
617 ;; result in faster code, even if the operand has to be moved to R0 first.
618 ;; This is because on SH4 TST #imm, R0 and MOV Rm, Rn are both MT group
619 ;; instructions and thus will be executed in parallel. On SH4A TST #imm, R0
620 ;; is an EX group instruction but still can be executed in parallel with the
621 ;; MT group MOV Rm, Rn instruction.
623 ;; Usual TST #imm, R0 patterns for SI, HI and QI
624 ;; This is usually used for bit patterns other than contiguous bits
626 (define_insn "tstsi_t"
628 (eq:SI (and:SI (match_operand:SI 0 "logical_operand" "%z,r")
629 (match_operand:SI 1 "logical_operand" "K08,r"))
633 [(set_attr "type" "mt_group")])
635 (define_insn "tsthi_t"
637 (eq:SI (subreg:SI (and:HI (match_operand:HI 0 "logical_operand" "%z")
638 (match_operand 1 "const_int_operand")) 0)
641 && CONST_OK_FOR_K08 (INTVAL (operands[1]))"
643 [(set_attr "type" "mt_group")])
645 (define_insn "tstqi_t"
647 (eq:SI (subreg:SI (and:QI (match_operand:QI 0 "logical_operand" "%z")
648 (match_operand 1 "const_int_operand")) 0)
651 && (CONST_OK_FOR_K08 (INTVAL (operands[1]))
652 || CONST_OK_FOR_I08 (INTVAL (operands[1])))"
654 operands[1] = GEN_INT (INTVAL (operands[1]) & 255);
657 [(set_attr "type" "mt_group")])
659 ;; Test low QI subreg against zero.
660 ;; This avoids unnecessary zero extension before the test.
661 (define_insn "*tstqi_t_zero"
663 (eq:SI (match_operand:QI 0 "logical_operand" "z") (const_int 0)))]
666 [(set_attr "type" "mt_group")])
668 ;; This pattern might be risky because it also tests the upper bits and not
669 ;; only the subreg. However, it seems that combine will get to this only
670 ;; when testing sign/zero extended values. In this case the extended upper
671 ;; bits do not matter.
672 (define_insn "*tst<mode>_t_zero"
676 (and:SI (match_operand:SI 0 "arith_reg_operand" "%r")
677 (match_operand:SI 1 "arith_reg_operand" "r")) <lowpart_le>)
679 "TARGET_SH1 && TARGET_LITTLE_ENDIAN"
681 [(set_attr "type" "mt_group")])
683 (define_insn "*tst<mode>_t_zero"
687 (and:SI (match_operand:SI 0 "arith_reg_operand" "%r")
688 (match_operand:SI 1 "arith_reg_operand" "r")) <lowpart_be>)
690 "TARGET_SH1 && TARGET_BIG_ENDIAN"
692 [(set_attr "type" "mt_group")])
694 ;; Extract LSB, negate and store in T bit.
695 (define_insn "tstsi_t_and_not"
697 (and:SI (not:SI (match_operand:SI 0 "logical_operand" "z"))
701 [(set_attr "type" "mt_group")])
703 ;; Extract contiguous bits and compare them against zero.
704 (define_insn "tst<mode>_t_zero_extract_eq"
706 (eq:SI (zero_extract:SI (match_operand:QIHISIDI 0 "logical_operand" "z")
707 (match_operand:SI 1 "const_int_operand")
708 (match_operand:SI 2 "const_int_operand"))
711 && CONST_OK_FOR_K08 (ZERO_EXTRACT_ANDMASK (operands[1], operands[2]))"
713 operands[1] = GEN_INT (ZERO_EXTRACT_ANDMASK (operands[1], operands[2]));
716 [(set_attr "type" "mt_group")])
718 ;; This split is required when testing bits in a QI subreg.
723 (zero_extract:SI (match_operand 0 "logical_operand")
724 (match_operand 1 "const_int_operand")
725 (match_operand 2 "const_int_operand"))
726 (match_operand 3 "const_int_operand")
730 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2]) == INTVAL (operands[3])
731 && CONST_OK_FOR_K08 (INTVAL (operands[3]))"
732 [(set (reg:SI T_REG) (eq:SI (and:SI (match_dup 0) (match_dup 3))
735 if (GET_MODE (operands[0]) == QImode)
736 operands[0] = simplify_gen_subreg (SImode, operands[0], QImode, 0);
739 ;; Extract single bit, negate and store it in the T bit.
740 ;; Not used for SH4A.
741 (define_insn "tstsi_t_zero_extract_xor"
743 (zero_extract:SI (xor:SI (match_operand:SI 0 "logical_operand" "z")
744 (match_operand:SI 3 "const_int_operand"))
745 (match_operand:SI 1 "const_int_operand")
746 (match_operand:SI 2 "const_int_operand")))]
748 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2]) == INTVAL (operands[3])
749 && CONST_OK_FOR_K08 (INTVAL (operands[3]))"
751 [(set_attr "type" "mt_group")])
753 ;; Extract single bit, negate and store it in the T bit.
754 ;; Used for SH4A little endian.
755 (define_insn "tstsi_t_zero_extract_subreg_xor_little"
758 (subreg:QI (xor:SI (match_operand:SI 0 "logical_operand" "z")
759 (match_operand:SI 3 "const_int_operand")) 0)
760 (match_operand:SI 1 "const_int_operand")
761 (match_operand:SI 2 "const_int_operand")))]
762 "TARGET_SH1 && TARGET_LITTLE_ENDIAN
763 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2])
764 == (INTVAL (operands[3]) & 255)
765 && CONST_OK_FOR_K08 (INTVAL (operands[3]) & 255)"
767 operands[3] = GEN_INT (INTVAL (operands[3]) & 255);
770 [(set_attr "type" "mt_group")])
772 ;; Extract single bit, negate and store it in the T bit.
773 ;; Used for SH4A big endian.
774 (define_insn "tstsi_t_zero_extract_subreg_xor_big"
777 (subreg:QI (xor:SI (match_operand:SI 0 "logical_operand" "z")
778 (match_operand:SI 3 "const_int_operand")) 3)
779 (match_operand:SI 1 "const_int_operand")
780 (match_operand:SI 2 "const_int_operand")))]
781 "TARGET_SH1 && TARGET_BIG_ENDIAN
782 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2])
783 == (INTVAL (operands[3]) & 255)
784 && CONST_OK_FOR_K08 (INTVAL (operands[3]) & 255)"
786 operands[3] = GEN_INT (INTVAL (operands[3]) & 255);
789 [(set_attr "type" "mt_group")])
791 (define_insn "cmpeqsi_t"
793 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
794 (match_operand:SI 1 "arith_operand" "N,rI08,r")))]
800 [(set_attr "type" "mt_group")])
802 ;; FIXME: For some reason, on SH4A and SH2A combine fails to simplify this
803 ;; pattern by itself. What this actually does is:
804 ;; x == 0: (1 >> 0-0) & 1 = 1
805 ;; x != 0: (1 >> 0-x) & 1 = 0
806 ;; Without this the test pr51244-8.c fails on SH2A and SH4A.
807 (define_insn_and_split "*cmpeqsi_t"
811 (neg:SI (match_operand:SI 0 "arith_reg_operand" "r")))
816 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))])
818 (define_insn "cmpgtsi_t"
820 (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
821 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
826 [(set_attr "type" "mt_group")])
828 (define_insn "cmpgesi_t"
830 (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
831 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
836 [(set_attr "type" "mt_group")])
838 ;; FIXME: This is actually wrong. There is no way to literally move a
839 ;; general reg to t reg. Luckily, it seems that this pattern will be only
840 ;; used when the general reg is known be either '0' or '1' during combine.
841 ;; What we actually need is reg != 0 -> T, but we have only reg == 0 -> T.
842 ;; Due to interactions with other patterns, combine fails to pick the latter
843 ;; and invert the dependent logic.
844 (define_insn "*negtstsi"
845 [(set (reg:SI T_REG) (match_operand:SI 0 "arith_reg_operand" "r"))]
848 [(set_attr "type" "mt_group")])
850 ;; Some integer sign comparison patterns can be realized with the div0s insn.
851 ;; div0s Rm,Rn T = (Rm >> 31) ^ (Rn >> 31)
852 (define_insn "cmp_div0s_0"
854 (lshiftrt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "%r")
855 (match_operand:SI 1 "arith_reg_operand" "r"))
859 [(set_attr "type" "arith")])
861 (define_insn "cmp_div0s_1"
863 (lt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "%r")
864 (match_operand:SI 1 "arith_reg_operand" "r"))
868 [(set_attr "type" "arith")])
870 (define_insn_and_split "*cmp_div0s_0"
871 [(set (match_operand:SI 0 "arith_reg_dest" "")
872 (lshiftrt:SI (xor:SI (match_operand:SI 1 "arith_reg_operand" "")
873 (match_operand:SI 2 "arith_reg_operand" ""))
875 (clobber (reg:SI T_REG))]
880 (lshiftrt:SI (xor:SI (match_dup 1) (match_dup 2)) (const_int 31)))
881 (set (match_dup 0) (reg:SI T_REG))])
883 (define_insn "*cmp_div0s_0"
885 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand" "%r")
887 (ge:SI (match_operand:SI 1 "arith_reg_operand" "r")
891 [(set_attr "type" "arith")])
893 (define_insn_and_split "*cmp_div0s_1"
894 [(set (match_operand:SI 0 "arith_reg_dest" "")
895 (ge:SI (xor:SI (match_operand:SI 1 "arith_reg_operand" "")
896 (match_operand:SI 2 "arith_reg_operand" ""))
898 (clobber (reg:SI T_REG))]
901 "&& can_create_pseudo_p ()"
903 ;; We have to go through the movnegt expander here which will handle the
904 ;; SH2A vs non-SH2A cases.
906 emit_insn (gen_cmp_div0s_1 (operands[1], operands[2]));
907 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
911 (define_insn_and_split "*cmp_div0s_1"
913 (ge:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "")
914 (match_operand:SI 1 "arith_reg_operand" ""))
918 "&& can_create_pseudo_p ()"
919 [(set (reg:SI T_REG) (lt:SI (xor:SI (match_dup 0) (match_dup 1))
921 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
923 (define_insn_and_split "*cmp_div0s_1"
925 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
927 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
931 "&& can_create_pseudo_p ()"
932 [(set (reg:SI T_REG) (lt:SI (xor:SI (match_dup 0) (match_dup 1))
934 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
936 ;; -------------------------------------------------------------------------
937 ;; SImode compare and branch
938 ;; -------------------------------------------------------------------------
940 (define_expand "cbranchsi4"
942 (if_then_else (match_operator 0 "comparison_operator"
943 [(match_operand:SI 1 "arith_operand" "")
944 (match_operand:SI 2 "arith_operand" "")])
945 (label_ref (match_operand 3 "" ""))
947 (clobber (reg:SI T_REG))]
951 emit_jump_insn (gen_cbranchint4_media (operands[0], operands[1],
952 operands[2], operands[3]));
954 expand_cbranchsi4 (operands, LAST_AND_UNUSED_RTX_CODE, -1);
959 ;; Combine patterns to invert compare and branch operations for which we
960 ;; don't have actual comparison insns. These patterns are used in cases
961 ;; which appear after the initial cbranchsi expansion, which also does
962 ;; some condition inversion.
965 (if_then_else (ne (match_operand:SI 0 "arith_reg_operand" "")
966 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
967 (label_ref (match_operand 2))
969 (clobber (reg:SI T_REG))]
971 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (match_dup 1)))
972 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
973 (label_ref (match_dup 2))
976 ;; FIXME: Similar to the *cmpeqsi_t pattern above, for some reason, on SH4A
977 ;; and SH2A combine fails to simplify this pattern by itself.
978 ;; What this actually does is:
979 ;; x == 0: (1 >> 0-0) & 1 = 1
980 ;; x != 0: (1 >> 0-x) & 1 = 0
981 ;; Without this the test pr51244-8.c fails on SH2A and SH4A.
985 (eq (and:SI (lshiftrt:SI
987 (neg:SI (match_operand:SI 0 "arith_reg_operand" "")))
990 (label_ref (match_operand 2))
992 (clobber (reg:SI T_REG))]
994 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))
995 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
996 (label_ref (match_dup 2))
999 ;; FIXME: These could probably use code iterators for the compare op.
1002 (if_then_else (le (match_operand:SI 0 "arith_reg_operand" "")
1003 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1004 (label_ref (match_operand 2))
1006 (clobber (reg:SI T_REG))]
1008 [(set (reg:SI T_REG) (gt:SI (match_dup 0) (match_dup 1)))
1009 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1010 (label_ref (match_dup 2))
1015 (if_then_else (lt (match_operand:SI 0 "arith_reg_operand" "")
1016 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1017 (label_ref (match_operand 2))
1019 (clobber (reg:SI T_REG))]
1021 [(set (reg:SI T_REG) (ge:SI (match_dup 0) (match_dup 1)))
1022 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1023 (label_ref (match_dup 2))
1028 (if_then_else (leu (match_operand:SI 0 "arith_reg_operand" "")
1029 (match_operand:SI 1 "arith_reg_operand" ""))
1030 (label_ref (match_operand 2))
1032 (clobber (reg:SI T_REG))]
1034 [(set (reg:SI T_REG) (gtu:SI (match_dup 0) (match_dup 1)))
1035 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1036 (label_ref (match_dup 2))
1041 (if_then_else (ltu (match_operand:SI 0 "arith_reg_operand" "")
1042 (match_operand:SI 1 "arith_reg_operand" ""))
1043 (label_ref (match_operand 2))
1045 (clobber (reg:SI T_REG))]
1047 [(set (reg:SI T_REG) (geu:SI (match_dup 0) (match_dup 1)))
1048 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1049 (label_ref (match_dup 2))
1052 ;; Compare and branch combine patterns for div0s comparisons.
1053 (define_insn_and_split "*cbranch_div0s"
1055 (if_then_else (lt (xor:SI (match_operand:SI 0 "arith_reg_operand" "")
1056 (match_operand:SI 1 "arith_reg_operand" ""))
1058 (label_ref (match_operand 2))
1060 (clobber (reg:SI T_REG))]
1064 [(set (reg:SI T_REG)
1065 (lt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 0)))
1067 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1068 (label_ref (match_dup 2))
1071 (define_insn_and_split "*cbranch_div0s"
1073 (if_then_else (ge (xor:SI (match_operand:SI 0 "arith_reg_operand" "")
1074 (match_operand:SI 1 "arith_reg_operand" ""))
1076 (label_ref (match_operand 2))
1078 (clobber (reg:SI T_REG))]
1082 [(set (reg:SI T_REG)
1083 (lt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 0)))
1085 (if_then_else (eq (reg:SI T_REG) (const_int 0))
1086 (label_ref (match_dup 2))
1089 ;; -------------------------------------------------------------------------
1090 ;; SImode unsigned integer comparisons
1091 ;; -------------------------------------------------------------------------
1093 ;; Usually comparisons of 'unsigned int >= 0' are optimized away completely.
1094 ;; However, especially when optimizations are off (e.g. -O0) such comparisons
1095 ;; might remain and we have to handle them. If the '>= 0' case wasn't
1096 ;; handled here, something else would just load a '0' into the second operand
1097 ;; and do the comparison. We can do slightly better by just setting the
1099 (define_insn_and_split "cmpgeusi_t"
1100 [(set (reg:SI T_REG)
1101 (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1102 (match_operand:SI 1 "arith_reg_or_0_operand" "r")))]
1105 "&& satisfies_constraint_Z (operands[1])"
1106 [(set (reg:SI T_REG) (const_int 1))]
1108 [(set_attr "type" "mt_group")])
1110 (define_insn "cmpgtusi_t"
1111 [(set (reg:SI T_REG)
1112 (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1113 (match_operand:SI 1 "arith_reg_operand" "r")))]
1116 [(set_attr "type" "mt_group")])
1118 ;; -------------------------------------------------------------------------
1119 ;; DImode compare and branch
1120 ;; -------------------------------------------------------------------------
1122 ;; arith3 patterns don't work well with the sh4-300 branch prediction mechanism.
1123 ;; Therefore, we aim to have a set of three branches that go straight to the
1124 ;; destination, i.e. only one of them is taken at any one time.
1125 ;; This mechanism should also be slightly better for the sh4-200.
1127 (define_expand "cbranchdi4"
1129 (if_then_else (match_operator 0 "comparison_operator"
1130 [(match_operand:DI 1 "arith_operand" "")
1131 (match_operand:DI 2 "arith_operand" "")])
1132 (label_ref (match_operand 3 "" ""))
1134 (clobber (match_dup 4))
1135 (clobber (reg:SI T_REG))]
1136 "TARGET_CBRANCHDI4 || TARGET_SH2 || TARGET_SHMEDIA"
1138 enum rtx_code comparison;
1142 emit_jump_insn (gen_cbranchint4_media (operands[0], operands[1],
1143 operands[2], operands[3]));
1146 else if (!TARGET_CBRANCHDI4)
1148 sh_emit_compare_and_branch (operands, DImode);
1153 if (expand_cbranchdi4 (operands, LAST_AND_UNUSED_RTX_CODE))
1156 comparison = prepare_cbranch_operands (operands, DImode,
1157 LAST_AND_UNUSED_RTX_CODE);
1158 if (comparison != GET_CODE (operands[0]))
1160 = gen_rtx_fmt_ee (comparison, VOIDmode, operands[1], operands[2]);
1161 operands[4] = gen_rtx_SCRATCH (SImode);
1165 (define_insn_and_split "cbranchdi4_i"
1167 (if_then_else (match_operator 0 "comparison_operator"
1168 [(match_operand:DI 1 "arith_operand" "r,r")
1169 (match_operand:DI 2 "arith_operand" "rN,I08")])
1170 (label_ref (match_operand 3 "" ""))
1172 (clobber (match_scratch:SI 4 "=X,&r"))
1173 (clobber (reg:SI T_REG))]
1176 "&& reload_completed"
1179 if (!expand_cbranchdi4 (operands, GET_CODE (operands[0])))
1184 ;; -------------------------------------------------------------------------
1185 ;; DImode signed integer comparisons
1186 ;; -------------------------------------------------------------------------
1189 [(set (reg:SI T_REG)
1190 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
1191 (match_operand:DI 1 "arith_operand" "r"))
1195 return output_branchy_insn (EQ, "tst\t%S1,%S0;bf\t%l9;tst\t%R1,%R0",
1198 [(set_attr "length" "6")
1199 (set_attr "type" "arith3b")])
1201 (define_insn "cmpeqdi_t"
1202 [(set (reg:SI T_REG)
1203 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1204 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
1207 static const char* alt[] =
1214 "cmp/eq %S1,%S0" "\n"
1216 " cmp/eq %R1,%R0" "\n"
1219 return alt[which_alternative];
1221 [(set_attr "length" "6")
1222 (set_attr "type" "arith3b")])
1225 [(set (reg:SI T_REG)
1226 (eq:SI (match_operand:DI 0 "arith_reg_operand" "")
1227 (match_operand:DI 1 "arith_reg_or_0_operand" "")))]
1228 ;; If we applied this split when not optimizing, it would only be
1229 ;; applied during the machine-dependent reorg, when no new basic blocks
1231 "TARGET_SH1 && reload_completed && optimize"
1232 [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
1233 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1234 (label_ref (match_dup 6))
1236 (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
1239 operands[2] = gen_highpart (SImode, operands[0]);
1240 operands[3] = operands[1] == const0_rtx
1242 : gen_highpart (SImode, operands[1]);
1243 operands[4] = gen_lowpart (SImode, operands[0]);
1244 operands[5] = gen_lowpart (SImode, operands[1]);
1245 operands[6] = gen_label_rtx ();
1248 (define_insn "cmpgtdi_t"
1249 [(set (reg:SI T_REG)
1250 (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1251 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1254 static const char* alt[] =
1256 "cmp/eq %S1,%S0" "\n"
1258 " cmp/gt %S1,%S0" "\n"
1259 " cmp/hi %R1,%R0" "\n"
1265 " cmp/hi %S0,%R0" "\n"
1268 return alt[which_alternative];
1270 [(set_attr "length" "8")
1271 (set_attr "type" "arith3")])
1273 (define_insn "cmpgedi_t"
1274 [(set (reg:SI T_REG)
1275 (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1276 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1279 static const char* alt[] =
1281 "cmp/eq %S1,%S0" "\n"
1283 " cmp/ge %S1,%S0" "\n"
1284 " cmp/hs %R1,%R0" "\n"
1289 return alt[which_alternative];
1291 [(set_attr "length" "8,2")
1292 (set_attr "type" "arith3,mt_group")])
1294 ;; -------------------------------------------------------------------------
1295 ;; DImode unsigned integer comparisons
1296 ;; -------------------------------------------------------------------------
1298 (define_insn "cmpgeudi_t"
1299 [(set (reg:SI T_REG)
1300 (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1301 (match_operand:DI 1 "arith_reg_operand" "r")))]
1304 return "cmp/eq %S1,%S0" "\n"
1306 " cmp/hs %S1,%S0" "\n"
1307 " cmp/hs %R1,%R0" "\n"
1310 [(set_attr "length" "8")
1311 (set_attr "type" "arith3")])
1313 (define_insn "cmpgtudi_t"
1314 [(set (reg:SI T_REG)
1315 (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1316 (match_operand:DI 1 "arith_reg_operand" "r")))]
1319 return "cmp/eq %S1,%S0" "\n"
1321 " cmp/hi %S1,%S0" "\n"
1322 " cmp/hi %R1,%R0" "\n"
1325 [(set_attr "length" "8")
1326 (set_attr "type" "arith3")])
1328 (define_insn "cmpeqsi_media"
1329 [(set (match_operand:SI 0 "register_operand" "=r")
1330 (eq:SI (match_operand:SI 1 "logical_operand" "%r")
1331 (match_operand:SI 2 "cmp_operand" "Nr")))]
1334 [(set_attr "type" "cmp_media")])
1336 (define_insn "cmpeqdi_media"
1337 [(set (match_operand:SI 0 "register_operand" "=r")
1338 (eq:SI (match_operand:DI 1 "register_operand" "%r")
1339 (match_operand:DI 2 "cmp_operand" "Nr")))]
1342 [(set_attr "type" "cmp_media")])
1344 (define_insn "cmpgtsi_media"
1345 [(set (match_operand:SI 0 "register_operand" "=r")
1346 (gt:SI (match_operand:SI 1 "cmp_operand" "Nr")
1347 (match_operand:SI 2 "cmp_operand" "rN")))]
1349 "cmpgt %N1, %N2, %0"
1350 [(set_attr "type" "cmp_media")])
1352 (define_insn "cmpgtdi_media"
1353 [(set (match_operand:SI 0 "register_operand" "=r")
1354 (gt:SI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
1355 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
1357 "cmpgt %N1, %N2, %0"
1358 [(set_attr "type" "cmp_media")])
1360 (define_insn "cmpgtusi_media"
1361 [(set (match_operand:SI 0 "register_operand" "=r")
1362 (gtu:SI (match_operand:SI 1 "cmp_operand" "Nr")
1363 (match_operand:SI 2 "cmp_operand" "rN")))]
1365 "cmpgtu %N1, %N2, %0"
1366 [(set_attr "type" "cmp_media")])
1368 (define_insn "cmpgtudi_media"
1369 [(set (match_operand:SI 0 "register_operand" "=r")
1370 (gtu:SI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
1371 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
1373 "cmpgtu %N1, %N2, %0"
1374 [(set_attr "type" "cmp_media")])
1376 ; This pattern is for combine.
1377 (define_insn "*cmpne0sisi_media"
1378 [(set (match_operand:SI 0 "register_operand" "=r")
1379 (ne:SI (match_operand:SI 1 "arith_reg_operand" "r") (const_int 0)))]
1382 [(set_attr "type" "cmp_media")])
1384 ;; -------------------------------------------------------------------------
1385 ;; Conditional move instructions
1386 ;; -------------------------------------------------------------------------
1388 ;; The insn names may seem reversed, but note that cmveq performs the move
1389 ;; if op1 == 0, and cmvne does it if op1 != 0.
1391 (define_insn "movdicc_false"
1392 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1393 (if_then_else:DI (eq (match_operand:DI 1 "arith_reg_operand" "r")
1395 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
1396 (match_operand:DI 3 "arith_reg_operand" "0")))]
1399 [(set_attr "type" "arith_media")])
1401 (define_insn "movdicc_true"
1402 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1403 (if_then_else:DI (ne (match_operand:DI 1 "arith_reg_operand" "r")
1405 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
1406 (match_operand:DI 3 "arith_reg_operand" "0")))]
1409 [(set_attr "type" "arith_media")])
1412 [(set (match_operand:DI 0 "arith_reg_dest" "")
1413 (if_then_else:DI (match_operator 3 "equality_comparison_operator"
1414 [(match_operand:DI 1 "arith_reg_operand" "")
1416 (match_operand:DI 2 "arith_reg_dest" "")
1418 (set (match_dup 2) (match_dup 0))]
1419 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
1421 (if_then_else:DI (match_dup 3) (match_dup 0) (match_dup 2)))]
1423 operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[3])),
1424 VOIDmode, operands[1], CONST0_RTX (DImode));
1428 [(set (match_operand:DI 0 "general_movdst_operand" "")
1429 (match_operand:DI 1 "arith_reg_or_0_operand" ""))
1430 (set (match_operand:DI 2 "arith_reg_dest" "")
1431 (if_then_else:DI (match_operator 4 "equality_comparison_operator"
1432 [(match_operand:DI 3 "arith_reg_operand" "")
1436 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
1438 (if_then_else:DI (match_dup 4) (match_dup 1) (match_dup 2)))]
1441 (define_expand "movdicc"
1442 [(set (match_operand:DI 0 "register_operand" "")
1443 (if_then_else:DI (match_operand 1 "comparison_operator" "")
1444 (match_operand:DI 2 "register_operand" "")
1445 (match_operand:DI 3 "register_operand" "")))]
1448 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
1449 && GET_MODE (XEXP (operands[1], 0)) == DImode
1450 && XEXP (operands[1], 1) == const0_rtx)
1454 if (!can_create_pseudo_p ())
1457 operands[1] = sh_emit_cheap_store_flag (GET_MODE (operands[0]),
1458 GET_CODE (operands[1]),
1459 XEXP (operands[1], 0),
1460 XEXP (operands[1], 1));
1466 ;; Add SImode variants for cmveq / cmvne to compensate for not promoting
1467 ;; SImode to DImode.
1468 (define_insn "movsicc_false"
1469 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1470 (if_then_else:SI (eq (match_operand:SI 1 "arith_reg_operand" "r")
1472 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
1473 (match_operand:SI 3 "arith_reg_operand" "0")))]
1476 [(set_attr "type" "arith_media")])
1478 (define_insn "movsicc_true"
1479 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1480 (if_then_else:SI (ne (match_operand:SI 1 "arith_reg_operand" "r")
1482 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
1483 (match_operand:SI 3 "arith_reg_operand" "0")))]
1486 [(set_attr "type" "arith_media")])
1489 [(set (match_operand:SI 0 "arith_reg_dest" "")
1490 (if_then_else:SI (match_operator 3 "equality_comparison_operator"
1491 [(match_operand:SI 1 "arith_reg_operand" "")
1493 (match_operand:SI 2 "arith_reg_dest" "")
1495 (set (match_dup 2) (match_dup 0))]
1496 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
1498 (if_then_else:SI (match_dup 3) (match_dup 0) (match_dup 2)))]
1500 operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[3])),
1501 VOIDmode, operands[1], CONST0_RTX (SImode));
1505 [(set (match_operand:SI 0 "general_movdst_operand" "")
1506 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1507 (set (match_operand:SI 2 "arith_reg_dest" "")
1508 (if_then_else:SI (match_operator 4 "equality_comparison_operator"
1509 [(match_operand:SI 3 "arith_reg_operand" "")
1513 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])
1514 && (!REG_P (operands[1]) || GENERAL_REGISTER_P (REGNO (operands[1])))"
1516 (if_then_else:SI (match_dup 4) (match_dup 1) (match_dup 2)))]
1518 replace_rtx (operands[4], operands[0], operands[1]);
1522 [(set (match_operand 0 "any_register_operand" "")
1523 (match_operand 1 "any_register_operand" ""))
1524 (set (match_operand 2 "any_register_operand" "") (match_operand 3 "" ""))
1525 (set (match_operand 4 "" "") (match_operand 5 "" ""))]
1526 "(HARD_REGNO_NREGS (REGNO (operands[0]), GET_MODE (operands[2]))
1527 <= HARD_REGNO_NREGS (REGNO (operands[0]), GET_MODE (operands[0])))
1528 && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[2])
1529 && ! FIND_REG_INC_NOTE (peep2_next_insn (2), operands[0])
1530 && ! FIND_REG_INC_NOTE (peep2_next_insn (2), operands[2])
1531 && ! reg_overlap_mentioned_p (operands[0], operands[3])
1532 && ! reg_overlap_mentioned_p (operands[2], operands[0])
1533 && ! reg_overlap_mentioned_p (operands[0], operands[1])
1534 && (REGNO_REG_CLASS (REGNO (operands[0]))
1535 == REGNO_REG_CLASS (REGNO (operands[2])))
1536 && (REGNO_REG_CLASS (REGNO (operands[1]))
1537 == REGNO_REG_CLASS (REGNO (operands[0])))"
1538 [(set (match_dup 0) (match_dup 3))
1539 (set (match_dup 4) (match_dup 5))]
1542 rtx_insn *insn1, *insn2;
1543 rtx replacements[4];
1545 /* We want to replace occurrences of operands[0] with operands[1] and
1546 operands[2] with operands[0] in operands[4]/operands[5].
1547 Doing just two replace_rtx calls naively would result in the second
1548 replacement undoing all that the first did if operands[1] and operands[2]
1549 are identical, so we must do this simultaneously. */
1550 replacements[0] = operands[0];
1551 replacements[1] = operands[1];
1552 replacements[2] = operands[2];
1553 replacements[3] = operands[0];
1554 if (!replace_n_hard_rtx (operands[5], replacements, 2, 0)
1555 || !replace_n_hard_rtx (operands[4], replacements, 2, 0)
1556 || !replace_n_hard_rtx (operands[2], replacements, 2, 0))
1559 operands[5] = replace_n_hard_rtx (operands[5], replacements, 2, 1);
1560 replace_n_hard_rtx (operands[4], replacements, 2, 1);
1561 operands[2] = replace_n_hard_rtx (operands[2], replacements, 2, 1);
1562 /* The operands array is aliased to recog_data.operand, which gets
1563 clobbered by extract_insn, so finish with it now. */
1564 set1 = gen_rtx_SET (VOIDmode, operands[2], operands[3]);
1565 set2 = gen_rtx_SET (VOIDmode, operands[4], operands[5]);
1566 /* ??? The last insn might be a jump insn, but the generic peephole2 code
1567 always uses emit_insn. */
1568 /* Check that we don't violate matching constraints or earlyclobbers. */
1569 basic_block bb = BLOCK_FOR_INSN (peep2_next_insn (2));
1570 insn1 = emit_insn (set1);
1571 extract_insn (insn1);
1572 if (! constrain_operands (1, get_preferred_alternatives (insn1, bb)))
1574 insn2 = emit (set2);
1575 if (GET_CODE (insn2) == BARRIER)
1577 extract_insn (insn2);
1578 if (! constrain_operands (1, get_preferred_alternatives (insn2, bb)))
1581 std::swap (replacements[0], replacements[1]);
1582 std::swap (replacements[2], replacements[3]);
1583 replace_n_hard_rtx (SET_DEST (set1), replacements, 2, 1);
1584 replace_n_hard_rtx (SET_DEST (set2), replacements, 2, 1);
1585 replace_n_hard_rtx (SET_SRC (set2), replacements, 2, 1);
1591 ;; The register allocator is rather clumsy in handling multi-way conditional
1592 ;; moves, so allow the combiner to make them, and we split them up after
1594 (define_insn_and_split "*movsicc_umin"
1595 [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
1596 (umin:SI (if_then_else:SI
1597 (eq (match_operand:SI 1 "arith_reg_operand" "r")
1599 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
1600 (match_operand:SI 3 "register_operand" "0"))
1601 (match_operand:SI 4 "arith_reg_or_0_operand" "r")))
1602 (clobber (match_scratch:SI 5 "=&r"))]
1603 "TARGET_SHMEDIA && !can_create_pseudo_p ()"
1605 "TARGET_SHMEDIA && reload_completed"
1608 emit_insn (gen_movsicc_false (operands[0], operands[1], operands[2],
1610 emit_insn (gen_cmpgtusi_media (operands[5], operands[4], operands[0]));
1611 emit_insn (gen_movsicc_false (operands[0], operands[5], operands[4],
1616 (define_insn "*movsicc_t_false"
1617 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1618 (if_then_else (eq (reg:SI T_REG) (const_int 0))
1619 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1620 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1621 "TARGET_PRETEND_CMOVE
1622 && (arith_reg_operand (operands[1], SImode)
1623 || (immediate_operand (operands[1], SImode)
1624 && satisfies_constraint_I08 (operands[1])))"
1630 [(set_attr "type" "mt_group,arith") ;; poor approximation
1631 (set_attr "length" "4")])
1633 (define_insn "*movsicc_t_true"
1634 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1635 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1636 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1637 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1638 "TARGET_PRETEND_CMOVE
1639 && (arith_reg_operand (operands[1], SImode)
1640 || (immediate_operand (operands[1], SImode)
1641 && satisfies_constraint_I08 (operands[1])))"
1647 [(set_attr "type" "mt_group,arith") ;; poor approximation
1648 (set_attr "length" "4")])
1650 (define_expand "movsicc"
1651 [(set (match_operand:SI 0 "arith_reg_dest" "")
1652 (if_then_else:SI (match_operand 1 "comparison_operator" "")
1653 (match_operand:SI 2 "arith_reg_or_0_operand" "")
1654 (match_operand:SI 3 "arith_reg_operand" "")))]
1655 "TARGET_SHMEDIA || TARGET_PRETEND_CMOVE"
1657 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
1658 && GET_MODE (XEXP (operands[1], 0)) == SImode
1660 || (REG_P (XEXP (operands[1], 0))
1661 && REGNO (XEXP (operands[1], 0)) == T_REG))
1662 && XEXP (operands[1], 1) == const0_rtx)
1665 else if (TARGET_PRETEND_CMOVE)
1667 enum rtx_code code = GET_CODE (operands[1]);
1668 enum rtx_code new_code = code;
1669 rtx op0 = XEXP (operands[1], 0);
1670 rtx op1 = XEXP (operands[1], 1);
1672 if (! currently_expanding_to_rtl)
1676 case LT: case LE: case LEU: case LTU:
1677 if (GET_MODE_CLASS (GET_MODE (op0)) != MODE_INT)
1680 new_code = reverse_condition (code);
1682 case EQ: case GT: case GE: case GEU: case GTU:
1687 sh_emit_scc_to_t (new_code, op0, op1);
1688 operands[1] = gen_rtx_fmt_ee (new_code == code ? NE : EQ, VOIDmode,
1689 gen_rtx_REG (SImode, T_REG), const0_rtx);
1693 if (!can_create_pseudo_p ())
1696 operands[1] = sh_emit_cheap_store_flag (GET_MODE (operands[0]),
1697 GET_CODE (operands[1]),
1698 XEXP (operands[1], 0),
1699 XEXP (operands[1], 1));
1705 (define_expand "movqicc"
1706 [(set (match_operand:QI 0 "register_operand" "")
1707 (if_then_else:QI (match_operand 1 "comparison_operator" "")
1708 (match_operand:QI 2 "register_operand" "")
1709 (match_operand:QI 3 "register_operand" "")))]
1712 operands[0] = simplify_gen_subreg (SImode, operands[0], QImode, 0);
1713 operands[2] = simplify_gen_subreg (SImode, operands[2], QImode, 0);
1714 operands[3] = simplify_gen_subreg (SImode, operands[3], QImode, 0);
1715 emit (gen_movsicc (operands[0], operands[1], operands[2], operands[3]));
1719 ;; -------------------------------------------------------------------------
1720 ;; Addition instructions
1721 ;; -------------------------------------------------------------------------
1723 (define_expand "adddi3"
1724 [(set (match_operand:DI 0 "arith_reg_operand")
1725 (plus:DI (match_operand:DI 1 "arith_reg_operand")
1726 (match_operand:DI 2 "arith_operand")))]
1731 operands[2] = force_reg (DImode, operands[2]);
1732 emit_insn (gen_adddi3_compact (operands[0], operands[1], operands[2]));
1737 (define_insn "*adddi3_media"
1738 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
1739 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
1740 (match_operand:DI 2 "arith_operand" "r,I10")))]
1745 [(set_attr "type" "arith_media")])
1747 (define_insn "*adddisi3_media"
1748 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r,r") 0)
1749 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
1750 (match_operand:DI 2 "arith_operand" "r,I10")))]
1755 [(set_attr "type" "arith_media")
1756 (set_attr "highpart" "ignore")])
1758 (define_insn "adddi3z_media"
1759 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1761 (plus:SI (match_operand:SI 1 "extend_reg_operand" "r")
1762 (match_operand:SI 2 "extend_reg_or_0_operand" "rN"))))]
1764 "addz.l %1, %N2, %0"
1765 [(set_attr "type" "arith_media")
1766 (set_attr "highpart" "ignore")])
1768 (define_insn_and_split "adddi3_compact"
1769 [(set (match_operand:DI 0 "arith_reg_dest")
1770 (plus:DI (match_operand:DI 1 "arith_reg_operand")
1771 (match_operand:DI 2 "arith_reg_operand")))
1772 (clobber (reg:SI T_REG))]
1775 "&& can_create_pseudo_p ()"
1778 emit_insn (gen_clrt ());
1779 emit_insn (gen_addc (gen_lowpart (SImode, operands[0]),
1780 gen_lowpart (SImode, operands[1]),
1781 gen_lowpart (SImode, operands[2])));
1782 emit_insn (gen_addc (gen_highpart (SImode, operands[0]),
1783 gen_highpart (SImode, operands[1]),
1784 gen_highpart (SImode, operands[2])));
1789 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1790 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
1791 (match_operand:SI 2 "arith_reg_operand" "r"))
1794 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
1797 [(set_attr "type" "arith")])
1799 ;; A simplified version of the addc insn, where the exact value of the
1800 ;; T bit doesn't matter. This is easier for combine to pick up.
1801 ;; We allow a reg or 0 for one of the operands in order to be able to
1802 ;; do 'reg + T' sequences. Reload will load the constant 0 into the reg
1804 ;; FIXME: The load of constant 0 should be split out before reload, or else
1805 ;; it will be difficult to hoist or combine the constant load.
1806 (define_insn "*addc"
1807 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1808 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
1809 (match_operand:SI 2 "arith_reg_or_0_operand" "r"))
1810 (match_operand:SI 3 "t_reg_operand" "")))
1811 (clobber (reg:SI T_REG))]
1814 [(set_attr "type" "arith")])
1816 ;; Split 'reg + reg + 1' into a sett addc sequence, as it can be scheduled
1817 ;; better, if the sett insn can be done early.
1818 (define_insn_and_split "*addc_r_r_1"
1819 [(set (match_operand:SI 0 "arith_reg_dest" "")
1820 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
1821 (match_operand:SI 2 "arith_reg_operand" ""))
1823 (clobber (reg:SI T_REG))]
1827 [(set (reg:SI T_REG) (const_int 1))
1828 (parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (match_dup 2))
1830 (clobber (reg:SI T_REG))])])
1832 ;; Left shifts by one are usually done with an add insn to avoid T_REG
1833 ;; clobbers. Thus addc can also be used to do something like '(x << 1) + 1'.
1834 (define_insn_and_split "*addc_2r_1"
1835 [(set (match_operand:SI 0 "arith_reg_dest")
1836 (plus:SI (mult:SI (match_operand:SI 1 "arith_reg_operand")
1839 (clobber (reg:SI T_REG))]
1843 [(set (reg:SI T_REG) (const_int 1))
1844 (parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (match_dup 1))
1846 (clobber (reg:SI T_REG))])])
1848 ;; Sometimes combine will try to do 'reg + (0-reg) + 1' if the *addc pattern
1849 ;; matched. Split this up into a simple sub add sequence, as this will save
1850 ;; us one sett insn.
1851 (define_insn_and_split "*minus_plus_one"
1852 [(set (match_operand:SI 0 "arith_reg_dest" "")
1853 (plus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
1854 (match_operand:SI 2 "arith_reg_operand" ""))
1859 [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
1860 (set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))])
1862 ;; Split 'reg + T' into 'reg + 0 + T' to utilize the addc insn.
1863 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
1864 ;; operation, as opposed to sequences such as
1868 ;; Even if the constant is not CSE-ed, a sequence such as
1871 ;; can be scheduled much better since the load of the constant can be
1872 ;; done earlier, before any comparison insns that store the result in
1874 (define_insn_and_split "*addc_t_r"
1875 [(set (match_operand:SI 0 "arith_reg_dest")
1876 (plus:SI (match_operand:SI 1 "t_reg_operand")
1877 (match_operand:SI 2 "arith_reg_operand")))
1878 (clobber (reg:SI T_REG))]
1882 [(parallel [(set (match_dup 0)
1883 (plus:SI (plus:SI (match_dup 2) (const_int 0))
1885 (clobber (reg:SI T_REG))])])
1887 (define_insn_and_split "*addc_r_t"
1888 [(set (match_operand:SI 0 "arith_reg_dest")
1889 (plus:SI (match_operand:SI 1 "arith_reg_operand")
1890 (match_operand:SI 2 "t_reg_operand")))
1891 (clobber (reg:SI T_REG))]
1895 [(parallel [(set (match_dup 0)
1896 (plus:SI (plus:SI (match_dup 1) (const_int 0))
1898 (clobber (reg:SI T_REG))])])
1900 ;; Use shlr-addc to do 'reg + (reg & 1)'.
1901 (define_insn_and_split "*addc_r_lsb"
1902 [(set (match_operand:SI 0 "arith_reg_dest")
1903 (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
1905 (match_operand:SI 2 "arith_reg_operand")))
1906 (clobber (reg:SI T_REG))]
1909 "&& can_create_pseudo_p ()"
1910 [(parallel [(set (match_dup 0) (plus:SI (reg:SI T_REG) (match_dup 2)))
1911 (clobber (reg:SI T_REG))])]
1913 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[1]));
1916 ;; Use shlr-addc to do 'reg + reg + (reg & 1)'.
1917 (define_insn_and_split "*addc_r_r_lsb"
1918 [(set (match_operand:SI 0 "arith_reg_dest")
1919 (plus:SI (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
1921 (match_operand:SI 2 "arith_reg_operand"))
1922 (match_operand:SI 3 "arith_reg_operand")))
1923 (clobber (reg:SI T_REG))]
1926 "&& can_create_pseudo_p ()"
1927 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3))
1929 (clobber (reg:SI T_REG))])]
1931 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[1]));
1934 ;; Canonicalize 'reg + (reg & 1) + reg' into 'reg + reg + (reg & 1)'.
1935 (define_insn_and_split "*addc_r_lsb_r"
1936 [(set (match_operand:SI 0 "arith_reg_dest")
1937 (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
1939 (plus:SI (match_operand:SI 2 "arith_reg_operand")
1940 (match_operand:SI 3 "arith_reg_operand"))))
1941 (clobber (reg:SI T_REG))]
1944 "&& can_create_pseudo_p ()"
1945 [(parallel [(set (match_dup 0)
1946 (plus:SI (plus:SI (and:SI (match_dup 1) (const_int 1))
1949 (clobber (reg:SI T_REG))])])
1951 ;; Canonicalize '2 * reg + (reg & 1)' into 'reg + reg + (reg & 1)'.
1952 (define_insn_and_split "*addc_2r_lsb"
1953 [(set (match_operand:SI 0 "arith_reg_dest")
1954 (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
1956 (mult:SI (match_operand:SI 2 "arith_reg_operand")
1958 (clobber (reg:SI T_REG))]
1961 "&& can_create_pseudo_p ()"
1962 [(parallel [(set (match_dup 0)
1963 (plus:SI (plus:SI (and:SI (match_dup 1) (const_int 1))
1966 (clobber (reg:SI T_REG))])])
1968 ;; Use shll-addc to do 'reg + ((unsigned int)reg >> 31)'.
1969 (define_insn_and_split "*addc_r_msb"
1970 [(set (match_operand:SI 0 "arith_reg_dest")
1971 (plus:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
1973 (match_operand:SI 2 "arith_reg_operand")))
1974 (clobber (reg:SI T_REG))]
1977 "&& can_create_pseudo_p ()"
1978 [(parallel [(set (match_dup 0) (plus:SI (reg:SI T_REG) (match_dup 2)))
1979 (clobber (reg:SI T_REG))])]
1981 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[1]));
1984 ;; Use shll-addc to do 'reg + reg + ((unsigned int)reg >> 31)'.
1985 (define_insn_and_split "*addc_r_r_msb"
1986 [(set (match_operand:SI 0 "arith_reg_dest")
1987 (plus:SI (plus:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
1989 (match_operand:SI 2 "arith_reg_operand"))
1990 (match_operand:SI 3 "arith_reg_operand")))
1991 (clobber (reg:SI T_REG))]
1994 "&& can_create_pseudo_p ()"
1995 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3))
1997 (clobber (reg:SI T_REG))])]
1999 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[1]));
2002 ;; Canonicalize '2 * reg + ((unsigned int)reg >> 31)'
2003 ;; into 'reg + reg + (reg & 1)'.
2004 (define_insn_and_split "*addc_2r_msb"
2005 [(set (match_operand:SI 0 "arith_reg_dest")
2006 (plus:SI (mult:SI (match_operand:SI 1 "arith_reg_operand")
2008 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
2010 (clobber (reg:SI T_REG))]
2013 "&& can_create_pseudo_p ()"
2014 [(parallel [(set (match_dup 0)
2015 (plus:SI (plus:SI (lshiftrt:SI (match_dup 2) (const_int 31))
2018 (clobber (reg:SI T_REG))])])
2020 (define_expand "addsi3"
2021 [(set (match_operand:SI 0 "arith_reg_operand" "")
2022 (plus:SI (match_operand:SI 1 "arith_operand" "")
2023 (match_operand:SI 2 "arith_or_int_operand" "")))]
2027 operands[1] = force_reg (SImode, operands[1]);
2028 else if (! arith_operand (operands[2], SImode))
2030 if (reg_overlap_mentioned_p (operands[0], operands[1]))
2035 (define_insn "addsi3_media"
2036 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
2037 (plus:SI (match_operand:SI 1 "extend_reg_operand" "%r,r")
2038 (match_operand:SI 2 "arith_operand" "r,I10")))]
2043 [(set_attr "type" "arith_media")
2044 (set_attr "highpart" "ignore")])
2046 (define_insn "addsidi3_media"
2047 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
2048 (sign_extend:DI (plus:SI (match_operand:SI 1 "extend_reg_operand"
2050 (match_operand:SI 2 "arith_operand"
2056 [(set_attr "type" "arith_media")
2057 (set_attr "highpart" "ignore")])
2059 (define_insn_and_split "*addsi3_compact"
2060 [(set (match_operand:SI 0 "arith_reg_dest" "=r,&r")
2061 (plus:SI (match_operand:SI 1 "arith_operand" "%0,r")
2062 (match_operand:SI 2 "arith_or_int_operand" "rI08,rn")))]
2064 && (rtx_equal_p (operands[0], operands[1])
2065 && arith_operand (operands[2], SImode))
2066 || ! reg_overlap_mentioned_p (operands[0], operands[1])"
2071 && ! reg_overlap_mentioned_p (operands[0], operands[1])"
2072 [(set (match_dup 0) (match_dup 2))
2073 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
2075 [(set_attr "type" "arith")])
2077 ;; -------------------------------------------------------------------------
2078 ;; Subtraction instructions
2079 ;; -------------------------------------------------------------------------
2081 (define_expand "subdi3"
2082 [(set (match_operand:DI 0 "arith_reg_operand" "")
2083 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "")
2084 (match_operand:DI 2 "arith_reg_operand" "")))]
2089 operands[1] = force_reg (DImode, operands[1]);
2090 emit_insn (gen_subdi3_compact (operands[0], operands[1], operands[2]));
2095 (define_insn "*subdi3_media"
2096 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
2097 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN")
2098 (match_operand:DI 2 "arith_reg_operand" "r")))]
2101 [(set_attr "type" "arith_media")])
2103 (define_insn "subdisi3_media"
2104 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
2105 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN")
2106 (match_operand:DI 2 "arith_reg_operand" "r")))]
2109 [(set_attr "type" "arith_media")
2110 (set_attr "highpart" "ignore")])
2112 (define_insn_and_split "subdi3_compact"
2113 [(set (match_operand:DI 0 "arith_reg_dest")
2114 (minus:DI (match_operand:DI 1 "arith_reg_operand")
2115 (match_operand:DI 2 "arith_reg_operand")))
2116 (clobber (reg:SI T_REG))]
2119 "&& can_create_pseudo_p ()"
2122 emit_insn (gen_clrt ());
2123 emit_insn (gen_subc (gen_lowpart (SImode, operands[0]),
2124 gen_lowpart (SImode, operands[1]),
2125 gen_lowpart (SImode, operands[2])));
2126 emit_insn (gen_subc (gen_highpart (SImode, operands[0]),
2127 gen_highpart (SImode, operands[1]),
2128 gen_highpart (SImode, operands[2])));
2133 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2134 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2135 (match_operand:SI 2 "arith_reg_operand" "r"))
2138 (gtu:SI (minus:SI (minus:SI (match_dup 1) (match_dup 2))
2143 [(set_attr "type" "arith")])
2145 ;; A simplified version of the subc insn, where the exact value of the
2146 ;; T bit doesn't matter. This is easier for combine to pick up.
2147 ;; We allow a reg or 0 for one of the operands in order to be able to
2148 ;; do 'reg - T' sequences. Reload will load the constant 0 into the reg
2150 (define_insn "*subc"
2151 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2152 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2153 (match_operand:SI 2 "arith_reg_or_0_operand" "r"))
2154 (match_operand:SI 3 "t_reg_operand" "")))
2155 (clobber (reg:SI T_REG))]
2158 [(set_attr "type" "arith")])
2160 ;; Split reg - reg - 1 into a sett subc sequence, as it can be scheduled
2161 ;; better, if the sett insn can be done early.
2162 ;; Notice that combine turns 'a - b - 1' into 'a + (~b)'.
2163 (define_insn_and_split "*subc"
2164 [(set (match_operand:SI 0 "arith_reg_dest" "")
2165 (plus:SI (not:SI (match_operand:SI 1 "arith_reg_operand" ""))
2166 (match_operand:SI 2 "arith_reg_operand" "")))
2167 (clobber (reg:SI T_REG))]
2171 [(set (reg:SI T_REG) (const_int 1))
2172 (parallel [(set (match_dup 0)
2173 (minus:SI (minus:SI (match_dup 2) (match_dup 1))
2175 (clobber (reg:SI T_REG))])])
2177 ;; Split 'reg - T' into 'reg - 0 - T' to utilize the subc insn.
2178 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
2179 ;; operation, as opposed to sequences such as
2183 ;; Even if the constant is not CSE-ed, a sequence such as
2186 ;; can be scheduled much better since the load of the constant can be
2187 ;; done earlier, before any comparison insns that store the result in
2189 (define_insn_and_split "*subc"
2190 [(set (match_operand:SI 0 "arith_reg_dest" "")
2191 (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
2192 (match_operand:SI 2 "t_reg_operand" "")))
2193 (clobber (reg:SI T_REG))]
2197 [(parallel [(set (match_dup 0)
2198 (minus:SI (minus:SI (match_dup 1) (const_int 0))
2200 (clobber (reg:SI T_REG))])])
2202 (define_insn "*subsi3_internal"
2203 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2204 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2205 (match_operand:SI 2 "arith_reg_operand" "r")))]
2208 [(set_attr "type" "arith")])
2210 (define_insn_and_split "*subsi3_media"
2211 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2212 (minus:SI (match_operand:SI 1 "minuend_operand" "rN")
2213 (match_operand:SI 2 "extend_reg_operand" "r")))]
2215 && (operands[1] != constm1_rtx
2216 || (GET_CODE (operands[2]) != TRUNCATE
2217 && GET_CODE (operands[2]) != SUBREG))"
2219 "operands[1] == constm1_rtx"
2220 [(set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))]
2222 [(set_attr "type" "arith_media")
2223 (set_attr "highpart" "ignore")])
2226 [(set (match_operand:SI 0 "arith_reg_dest" "")
2227 (zero_extend:SI (subreg:QI (not:SI (subreg:SI (match_operand:QI 1
2228 "general_extend_operand"
2230 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
2231 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
2232 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 255)))]
2236 [(set (match_operand:SI 0 "arith_reg_dest" "")
2237 (zero_extend:SI (subreg:QI (not:SI (subreg:SI (match_operand:QI 1
2238 "general_extend_operand"
2240 "TARGET_SHMEDIA && TARGET_BIG_ENDIAN"
2241 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
2242 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 255)))]
2250 ;; since this will sometimes save one instruction.
2251 ;; Otherwise we might get a sequence like
2255 ;; if the source and dest regs are the same.
2256 (define_expand "subsi3"
2257 [(set (match_operand:SI 0 "arith_reg_operand" "")
2258 (minus:SI (match_operand:SI 1 "arith_operand" "")
2259 (match_operand:SI 2 "arith_reg_operand" "")))]
2262 if (TARGET_SH1 && CONST_INT_P (operands[1]))
2264 emit_insn (gen_negsi2 (operands[0], operands[2]));
2265 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
2270 if (!can_create_pseudo_p ()
2271 && ! arith_reg_or_0_operand (operands[1], SImode))
2273 if (operands[1] != const0_rtx && GET_CODE (operands[1]) != SUBREG)
2274 operands[1] = force_reg (SImode, operands[1]);
2278 ;; -------------------------------------------------------------------------
2279 ;; Division instructions
2280 ;; -------------------------------------------------------------------------
2282 ;; We take advantage of the library routines which don't clobber as many
2283 ;; registers as a normal function call would.
2285 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
2286 ;; also has an effect on the register that holds the address of the sfunc.
2287 ;; To make this work, we have an extra dummy insn that shows the use
2288 ;; of this register for reorg.
2290 (define_insn "use_sfunc_addr"
2291 [(set (reg:SI PR_REG)
2292 (unspec:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
2293 "TARGET_SH1 && check_use_sfunc_addr (insn, operands[0])"
2295 [(set_attr "length" "0")])
2297 (define_insn "udivsi3_sh2a"
2298 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2299 (udiv:SI (match_operand:SI 1 "arith_reg_operand" "0")
2300 (match_operand:SI 2 "arith_reg_operand" "z")))]
2303 [(set_attr "type" "arith")
2304 (set_attr "in_delay_slot" "no")])
2306 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
2307 ;; hard register 0. If we used hard register 0, then the next instruction
2308 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
2309 ;; gets allocated to a stack slot that needs its address reloaded, then
2310 ;; there is nothing to prevent reload from using r0 to reload the address.
2311 ;; This reload would clobber the value in r0 we are trying to store.
2312 ;; If we let reload allocate r0, then this problem can never happen.
2313 (define_insn "udivsi3_i1"
2314 [(set (match_operand:SI 0 "register_operand" "=z")
2315 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2316 (clobber (reg:SI T_REG))
2317 (clobber (reg:SI PR_REG))
2318 (clobber (reg:SI R1_REG))
2319 (clobber (reg:SI R4_REG))
2320 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2321 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2323 [(set_attr "type" "sfunc")
2324 (set_attr "needs_delay_slot" "yes")])
2326 ; Since shmedia-nofpu code could be linked against shcompact code, and
2327 ; the udivsi3 libcall has the same name, we must consider all registers
2328 ; clobbered that are in the union of the registers clobbered by the
2329 ; shmedia and the shcompact implementation. Note, if the shcompact
2330 ; implementation actually used shcompact code, we'd need to clobber
2331 ; also r23 and fr23.
2332 (define_insn "udivsi3_i1_media"
2333 [(set (match_operand:SI 0 "register_operand" "=z")
2334 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2335 (clobber (reg:SI T_MEDIA_REG))
2336 (clobber (reg:SI PR_MEDIA_REG))
2337 (clobber (reg:SI R20_REG))
2338 (clobber (reg:SI R21_REG))
2339 (clobber (reg:SI R22_REG))
2340 (clobber (reg:DI TR0_REG))
2341 (clobber (reg:DI TR1_REG))
2342 (clobber (reg:DI TR2_REG))
2343 (use (match_operand 1 "target_reg_operand" "b"))]
2344 "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
2346 [(set_attr "type" "sfunc")
2347 (set_attr "needs_delay_slot" "yes")])
2349 (define_expand "udivsi3_i4_media"
2351 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
2353 (zero_extend:DI (match_operand:SI 2 "register_operand" "")))
2354 (set (match_dup 5) (float:DF (match_dup 3)))
2355 (set (match_dup 6) (float:DF (match_dup 4)))
2356 (set (match_dup 7) (div:DF (match_dup 5) (match_dup 6)))
2357 (set (match_dup 8) (fix:DI (match_dup 7)))
2358 (set (match_operand:SI 0 "register_operand" "")
2359 (truncate:SI (match_dup 8)))]
2360 "TARGET_SHMEDIA_FPU"
2362 operands[3] = gen_reg_rtx (DImode);
2363 operands[4] = gen_reg_rtx (DImode);
2364 operands[5] = gen_reg_rtx (DFmode);
2365 operands[6] = gen_reg_rtx (DFmode);
2366 operands[7] = gen_reg_rtx (DFmode);
2367 operands[8] = gen_reg_rtx (DImode);
2370 (define_insn "udivsi3_i4"
2371 [(set (match_operand:SI 0 "register_operand" "=y")
2372 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2373 (clobber (reg:SI T_REG))
2374 (clobber (reg:SI PR_REG))
2375 (clobber (reg:DF DR0_REG))
2376 (clobber (reg:DF DR2_REG))
2377 (clobber (reg:DF DR4_REG))
2378 (clobber (reg:SI R0_REG))
2379 (clobber (reg:SI R1_REG))
2380 (clobber (reg:SI R4_REG))
2381 (clobber (reg:SI R5_REG))
2382 (clobber (reg:SI FPSCR_STAT_REG))
2383 (use (reg:SI FPSCR_MODES_REG))
2384 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2385 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2387 [(set_attr "type" "sfunc")
2388 (set_attr "fp_mode" "double")
2389 (set_attr "needs_delay_slot" "yes")])
2391 (define_insn "udivsi3_i4_single"
2392 [(set (match_operand:SI 0 "register_operand" "=y")
2393 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2394 (clobber (reg:SI T_REG))
2395 (clobber (reg:SI PR_REG))
2396 (clobber (reg:DF DR0_REG))
2397 (clobber (reg:DF DR2_REG))
2398 (clobber (reg:DF DR4_REG))
2399 (clobber (reg:SI R0_REG))
2400 (clobber (reg:SI R1_REG))
2401 (clobber (reg:SI R4_REG))
2402 (clobber (reg:SI R5_REG))
2403 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2404 "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE || TARGET_SHCOMPACT)
2405 && TARGET_FPU_SINGLE"
2407 [(set_attr "type" "sfunc")
2408 (set_attr "needs_delay_slot" "yes")])
2410 (define_insn "udivsi3_i4_int"
2411 [(set (match_operand:SI 0 "register_operand" "=z")
2412 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2413 (clobber (reg:SI T_REG))
2414 (clobber (reg:SI R1_REG))
2415 (clobber (reg:SI PR_REG))
2416 (clobber (reg:SI MACH_REG))
2417 (clobber (reg:SI MACL_REG))
2418 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2421 [(set_attr "type" "sfunc")
2422 (set_attr "needs_delay_slot" "yes")])
2425 (define_expand "udivsi3"
2426 [(set (match_dup 3) (symbol_ref:SI "__udivsi3"))
2427 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
2428 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
2429 (parallel [(set (match_operand:SI 0 "register_operand" "")
2430 (udiv:SI (reg:SI R4_REG)
2432 (clobber (reg:SI T_REG))
2433 (clobber (reg:SI PR_REG))
2434 (clobber (reg:SI R4_REG))
2435 (use (match_dup 3))])]
2440 operands[3] = gen_reg_rtx (Pmode);
2441 /* Emit the move of the address to a pseudo outside of the libcall. */
2442 if (TARGET_DIVIDE_CALL_TABLE)
2444 /* libgcc2:__udivmoddi4 is not supposed to use an actual division, since
2445 that causes problems when the divide code is supposed to come from a
2446 separate library. Division by zero is undefined, so dividing 1 can be
2447 implemented by comparing with the divisor. */
2448 if (operands[1] == const1_rtx && currently_expanding_to_rtl)
2450 rtx test = gen_rtx_GEU (VOIDmode, operands[1], operands[2]);
2451 emit_insn (gen_cstoresi4 (operands[0], test,
2452 operands[1], operands[2]));
2455 else if (operands[2] == const0_rtx)
2457 emit_move_insn (operands[0], operands[2]);
2460 function_symbol (operands[3], "__udivsi3_i4i", SFUNC_GOT);
2461 last = gen_udivsi3_i4_int (operands[0], operands[3]);
2463 else if (TARGET_DIVIDE_CALL_FP)
2465 function_symbol (operands[3], "__udivsi3_i4", SFUNC_STATIC);
2466 if (TARGET_FPU_SINGLE)
2467 last = gen_udivsi3_i4_single (operands[0], operands[3]);
2469 last = gen_udivsi3_i4 (operands[0], operands[3]);
2471 else if (TARGET_SHMEDIA_FPU)
2473 operands[1] = force_reg (SImode, operands[1]);
2474 operands[2] = force_reg (SImode, operands[2]);
2475 emit_insn (gen_udivsi3_i4_media (operands[0], operands[1], operands[2]));
2478 else if (TARGET_SH2A)
2480 operands[1] = force_reg (SImode, operands[1]);
2481 operands[2] = force_reg (SImode, operands[2]);
2482 emit_insn (gen_udivsi3_sh2a (operands[0], operands[1], operands[2]));
2485 else if (TARGET_SH5)
2487 function_symbol (operands[3],
2488 TARGET_FPU_ANY ? "__udivsi3_i4" : "__udivsi3",
2492 last = gen_udivsi3_i1_media (operands[0], operands[3]);
2493 else if (TARGET_FPU_ANY)
2494 last = gen_udivsi3_i4_single (operands[0], operands[3]);
2496 last = gen_udivsi3_i1 (operands[0], operands[3]);
2500 function_symbol (operands[3], "__udivsi3", SFUNC_STATIC);
2501 last = gen_udivsi3_i1 (operands[0], operands[3]);
2503 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2504 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2509 (define_insn "divsi3_sh2a"
2510 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2511 (div:SI (match_operand:SI 1 "arith_reg_operand" "0")
2512 (match_operand:SI 2 "arith_reg_operand" "z")))]
2515 [(set_attr "type" "arith")
2516 (set_attr "in_delay_slot" "no")])
2518 (define_insn "divsi3_i1"
2519 [(set (match_operand:SI 0 "register_operand" "=z")
2520 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2521 (clobber (reg:SI T_REG))
2522 (clobber (reg:SI PR_REG))
2523 (clobber (reg:SI R1_REG))
2524 (clobber (reg:SI R2_REG))
2525 (clobber (reg:SI R3_REG))
2526 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2527 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2529 [(set_attr "type" "sfunc")
2530 (set_attr "needs_delay_slot" "yes")])
2532 (define_insn "divsi3_i1_media"
2533 [(set (match_operand:SI 0 "register_operand" "=z")
2534 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2535 (clobber (reg:SI T_MEDIA_REG))
2536 (clobber (reg:SI PR_MEDIA_REG))
2537 (clobber (reg:SI R1_REG))
2538 (clobber (reg:SI R20_REG))
2539 (clobber (reg:SI R21_REG))
2540 (clobber (reg:SI TR0_REG))
2541 (use (match_operand 1 "target_reg_operand" "b"))]
2542 "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
2544 [(set_attr "type" "sfunc")])
2546 (define_insn "divsi3_media_2"
2547 [(set (match_operand:SI 0 "register_operand" "=z")
2548 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2549 (clobber (reg:SI T_MEDIA_REG))
2550 (clobber (reg:SI PR_MEDIA_REG))
2551 (clobber (reg:SI R1_REG))
2552 (clobber (reg:SI R21_REG))
2553 (clobber (reg:SI TR0_REG))
2554 (use (reg:SI R20_REG))
2555 (use (match_operand 1 "target_reg_operand" "b"))]
2556 "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
2558 [(set_attr "type" "sfunc")])
2560 ;; This pattern acts as a placeholder for -mdiv=inv:call to carry
2561 ;; hard reg clobbers and data dependencies that we need when we want
2562 ;; to rematerialize the division into a call.
2563 (define_insn_and_split "divsi_inv_call"
2564 [(set (match_operand:SI 0 "register_operand" "=r")
2565 (div:SI (match_operand:SI 1 "register_operand" "r")
2566 (match_operand:SI 2 "register_operand" "r")))
2567 (clobber (reg:SI R4_REG))
2568 (clobber (reg:SI R5_REG))
2569 (clobber (reg:SI T_MEDIA_REG))
2570 (clobber (reg:SI PR_MEDIA_REG))
2571 (clobber (reg:SI R1_REG))
2572 (clobber (reg:SI R21_REG))
2573 (clobber (reg:SI TR0_REG))
2574 (clobber (reg:SI R20_REG))
2575 (use (match_operand:SI 3 "register_operand" "r"))]
2578 "&& (reload_in_progress || reload_completed)"
2579 [(set (match_dup 0) (match_dup 3))]
2581 [(set_attr "highpart" "must_split")])
2583 ;; This is the combiner pattern for -mdiv=inv:call .
2584 (define_insn_and_split "*divsi_inv_call_combine"
2585 [(set (match_operand:SI 0 "register_operand" "=z")
2586 (div:SI (match_operand:SI 1 "register_operand" "r")
2587 (match_operand:SI 2 "register_operand" "r")))
2588 (clobber (reg:SI R4_REG))
2589 (clobber (reg:SI R5_REG))
2590 (clobber (reg:SI T_MEDIA_REG))
2591 (clobber (reg:SI PR_MEDIA_REG))
2592 (clobber (reg:SI R1_REG))
2593 (clobber (reg:SI R21_REG))
2594 (clobber (reg:SI TR0_REG))
2595 (clobber (reg:SI R20_REG))
2596 (use (unspec:SI [(match_dup 1)
2597 (match_operand:SI 3 "" "")
2598 (unspec:SI [(match_operand:SI 4 "" "")
2600 (match_operand:DI 5 "" "")]
2602 (match_operand:DI 6 "" "")
2605 UNSPEC_DIV_INV_M3))]
2608 "&& (reload_in_progress || reload_completed)"
2611 const char *name = sh_divsi3_libfunc;
2612 enum sh_function_kind kind = SFUNC_GOT;
2615 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
2616 emit_move_insn (gen_rtx_REG (SImode, R5_REG), operands[2]);
2617 while (TARGET_DIVIDE_INV_CALL2)
2619 rtx x = operands[3];
2621 if (GET_CODE (x) != UNSPEC || XINT (x, 1) != UNSPEC_DIV_INV_M1)
2623 x = XVECEXP (x, 0, 0);
2624 name = "__sdivsi3_2";
2625 kind = SFUNC_STATIC;
2626 emit_move_insn (gen_rtx_REG (DImode, R20_REG), x);
2629 sym = function_symbol (NULL, name, kind);
2630 emit_insn (gen_divsi3_media_2 (operands[0], sym));
2633 [(set_attr "highpart" "must_split")])
2635 (define_expand "divsi3_i4_media"
2636 [(set (match_dup 3) (float:DF (match_operand:SI 1 "register_operand" "r")))
2637 (set (match_dup 4) (float:DF (match_operand:SI 2 "register_operand" "r")))
2638 (set (match_dup 5) (div:DF (match_dup 3) (match_dup 4)))
2639 (set (match_operand:SI 0 "register_operand" "=r")
2640 (fix:SI (match_dup 5)))]
2641 "TARGET_SHMEDIA_FPU"
2643 operands[3] = gen_reg_rtx (DFmode);
2644 operands[4] = gen_reg_rtx (DFmode);
2645 operands[5] = gen_reg_rtx (DFmode);
2648 (define_insn "divsi3_i4"
2649 [(set (match_operand:SI 0 "register_operand" "=y")
2650 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2651 (clobber (reg:SI PR_REG))
2652 (clobber (reg:DF DR0_REG))
2653 (clobber (reg:DF DR2_REG))
2654 (clobber (reg:SI FPSCR_STAT_REG))
2655 (use (reg:SI FPSCR_MODES_REG))
2656 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2657 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2659 [(set_attr "type" "sfunc")
2660 (set_attr "fp_mode" "double")
2661 (set_attr "needs_delay_slot" "yes")])
2663 (define_insn "divsi3_i4_single"
2664 [(set (match_operand:SI 0 "register_operand" "=y")
2665 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2666 (clobber (reg:SI PR_REG))
2667 (clobber (reg:DF DR0_REG))
2668 (clobber (reg:DF DR2_REG))
2669 (clobber (reg:SI R2_REG))
2670 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2671 "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE || TARGET_SHCOMPACT)
2672 && TARGET_FPU_SINGLE"
2674 [(set_attr "type" "sfunc")
2675 (set_attr "needs_delay_slot" "yes")])
2677 (define_insn "divsi3_i4_int"
2678 [(set (match_operand:SI 0 "register_operand" "=z")
2679 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2680 (clobber (reg:SI T_REG))
2681 (clobber (reg:SI PR_REG))
2682 (clobber (reg:SI R1_REG))
2683 (clobber (reg:SI MACH_REG))
2684 (clobber (reg:SI MACL_REG))
2685 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2688 [(set_attr "type" "sfunc")
2689 (set_attr "needs_delay_slot" "yes")])
2691 (define_expand "divsi3"
2692 [(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
2693 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
2694 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
2695 (parallel [(set (match_operand:SI 0 "register_operand" "")
2696 (div:SI (reg:SI R4_REG)
2698 (clobber (reg:SI T_REG))
2699 (clobber (reg:SI PR_REG))
2700 (clobber (reg:SI R1_REG))
2701 (clobber (reg:SI R2_REG))
2702 (clobber (reg:SI R3_REG))
2703 (use (match_dup 3))])]
2708 operands[3] = gen_reg_rtx (Pmode);
2709 /* Emit the move of the address to a pseudo outside of the libcall. */
2710 if (TARGET_DIVIDE_CALL_TABLE)
2712 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2713 last = gen_divsi3_i4_int (operands[0], operands[3]);
2715 else if (TARGET_DIVIDE_CALL_FP)
2717 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_STATIC);
2718 if (TARGET_FPU_SINGLE)
2719 last = gen_divsi3_i4_single (operands[0], operands[3]);
2721 last = gen_divsi3_i4 (operands[0], operands[3]);
2723 else if (TARGET_SH2A)
2725 operands[1] = force_reg (SImode, operands[1]);
2726 operands[2] = force_reg (SImode, operands[2]);
2727 emit_insn (gen_divsi3_sh2a (operands[0], operands[1], operands[2]));
2730 else if (TARGET_DIVIDE_INV)
2732 rtx dividend = operands[1];
2733 rtx divisor = operands[2];
2735 rtx nsb_res = gen_reg_rtx (DImode);
2736 rtx norm64 = gen_reg_rtx (DImode);
2737 rtx tab_ix = gen_reg_rtx (DImode);
2738 rtx norm32 = gen_reg_rtx (SImode);
2739 rtx i92 = force_reg (DImode, GEN_INT (92));
2740 rtx scratch0a = gen_reg_rtx (DImode);
2741 rtx scratch0b = gen_reg_rtx (DImode);
2742 rtx inv0 = gen_reg_rtx (SImode);
2743 rtx scratch1a = gen_reg_rtx (DImode);
2744 rtx scratch1b = gen_reg_rtx (DImode);
2745 rtx shift = gen_reg_rtx (DImode);
2747 rtx inv1 = gen_reg_rtx (SImode);
2748 rtx scratch2a = gen_reg_rtx (DImode);
2749 rtx scratch2b = gen_reg_rtx (SImode);
2750 rtx inv2 = gen_reg_rtx (SImode);
2751 rtx scratch3a = gen_reg_rtx (DImode);
2752 rtx scratch3b = gen_reg_rtx (DImode);
2753 rtx scratch3c = gen_reg_rtx (DImode);
2754 rtx scratch3d = gen_reg_rtx (SImode);
2755 rtx scratch3e = gen_reg_rtx (DImode);
2756 rtx result = gen_reg_rtx (SImode);
2758 if (! arith_reg_or_0_operand (dividend, SImode))
2759 dividend = force_reg (SImode, dividend);
2760 if (! arith_reg_operand (divisor, SImode))
2761 divisor = force_reg (SImode, divisor);
2762 if (flag_pic && Pmode != DImode)
2764 tab_base = gen_rtx_SYMBOL_REF (Pmode, "__div_table");
2765 tab_base = gen_datalabel_ref (tab_base);
2766 tab_base = force_reg (DImode, gen_rtx_SIGN_EXTEND (DImode, tab_base));
2770 tab_base = gen_rtx_SYMBOL_REF (DImode, "__div_table");
2771 tab_base = gen_datalabel_ref (tab_base);
2772 tab_base = force_reg (DImode, tab_base);
2774 if (TARGET_DIVIDE_INV20U)
2775 i2p27 = force_reg (DImode, GEN_INT (-2 << 27));
2777 i2p27 = GEN_INT (0);
2778 if (TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)
2779 i43 = force_reg (DImode, GEN_INT (43));
2782 emit_insn (gen_nsbdi (nsb_res,
2783 simplify_gen_subreg (DImode, divisor, SImode, 0)));
2784 emit_insn (gen_ashldi3_media (norm64,
2785 gen_rtx_SUBREG (DImode, divisor, 0),
2787 emit_insn (gen_ashrdi3_media (tab_ix, norm64, GEN_INT (58)));
2788 emit_insn (gen_ashrdisi3_media_high (norm32, norm64, GEN_INT (32)));
2789 emit_insn (gen_divsi_inv_m1 (inv1, tab_base, tab_ix, norm32,
2790 inv0, scratch0a, scratch0b,
2791 scratch1a, scratch1b));
2792 emit_insn (gen_subdi3 (shift, i92, nsb_res));
2793 emit_insn (gen_divsi_inv_m2 (inv2, norm32, inv1, i92,
2795 emit_insn (gen_divsi_inv_m3 (result, dividend, inv1, inv2, shift,
2797 scratch3a, scratch3b, scratch3c,
2798 scratch2a, scratch2b, scratch3d, scratch3e));
2799 if (TARGET_DIVIDE_INV_CALL || TARGET_DIVIDE_INV_CALL2)
2800 emit_insn (gen_divsi_inv_call (operands[0], dividend, divisor, result));
2801 else if (TARGET_DIVIDE_INV_FP)
2802 emit_insn (gen_divsi_inv_fp (operands[0], dividend, divisor, result,
2803 gen_reg_rtx (SImode), gen_reg_rtx (SImode),
2804 gen_reg_rtx (DFmode), gen_reg_rtx (DFmode),
2805 gen_reg_rtx (DFmode)));
2807 emit_move_insn (operands[0], result);
2810 else if (TARGET_SHMEDIA_FPU && TARGET_DIVIDE_FP)
2812 operands[1] = force_reg (SImode, operands[1]);
2813 operands[2] = force_reg (SImode, operands[2]);
2814 emit_insn (gen_divsi3_i4_media (operands[0], operands[1], operands[2]));
2817 else if (TARGET_SH5)
2819 if (TARGET_DIVIDE_CALL2)
2821 rtx tab_base = gen_rtx_SYMBOL_REF (Pmode, "__div_table");
2822 tab_base = gen_datalabel_ref (tab_base);
2823 emit_move_insn (gen_rtx_REG (Pmode, R20_REG), tab_base);
2825 if (TARGET_FPU_ANY && TARGET_SH1)
2826 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_STATIC);
2827 else if (TARGET_DIVIDE_CALL2)
2828 function_symbol (operands[3], "__sdivsi3_2", SFUNC_STATIC);
2830 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2833 last = ((TARGET_DIVIDE_CALL2 ? gen_divsi3_media_2 : gen_divsi3_i1_media)
2834 (operands[0], operands[3]));
2835 else if (TARGET_FPU_ANY)
2836 last = gen_divsi3_i4_single (operands[0], operands[3]);
2838 last = gen_divsi3_i1 (operands[0], operands[3]);
2842 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2843 last = gen_divsi3_i1 (operands[0], operands[3]);
2845 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2846 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2851 ;; operands: scratch, tab_base, tab_ix
2852 ;; These are unspecs because we could generate an indexed addressing mode
2853 ;; even if -m5-32media, where INDEX_REG_CLASS == NO_REGS, and this would
2854 ;; confuse reload. See PR27117.
2855 (define_insn "divsi_inv_qitable"
2856 [(set (match_operand:DI 0 "register_operand" "=r")
2857 (zero_extend:DI (unspec:QI [(match_operand:DI 1 "register_operand" "r")
2858 (match_operand:DI 2 "register_operand" "r")]
2859 UNSPEC_DIV_INV_TABLE)))]
2862 [(set_attr "type" "load_media")
2863 (set_attr "highpart" "user")])
2865 ;; operands: scratch, tab_base, tab_ix
2866 (define_insn "divsi_inv_hitable"
2867 [(set (match_operand:DI 0 "register_operand" "=r")
2868 (sign_extend:DI (unspec:HI [(match_operand:DI 1 "register_operand" "r")
2869 (match_operand:DI 2 "register_operand" "r")]
2870 UNSPEC_DIV_INV_TABLE)))]
2873 [(set_attr "type" "load_media")
2874 (set_attr "highpart" "user")])
2876 ;; operands: inv0, tab_base, tab_ix, norm32
2877 ;; scratch equiv in sdivsi3_2: r19, r21
2878 (define_expand "divsi_inv_m0"
2879 [(set (match_operand:SI 0 "register_operand" "=r")
2880 (unspec:SI [(match_operand:DI 1 "register_operand" "r")
2881 (match_operand:DI 2 "register_operand" "r")
2882 (match_operand:SI 3 "register_operand" "r")]
2884 (clobber (match_operand:DI 4 "register_operand" "=r"))
2885 (clobber (match_operand:DI 5 "register_operand" "=r"))]
2892 ldx.ub r20, r21, r19 // u0.8
2894 muls.l r25, r19, r19 // s2.38
2895 ldx.w r20, r21, r21 // s2.14
2896 shari r19, 24, r19 // truncate to s2.14
2897 sub r21, r19, r19 // some 11 bit inverse in s1.14
2900 rtx inv0 = operands[0];
2901 rtx tab_base = operands[1];
2902 rtx tab_ix = operands[2];
2903 rtx norm32 = operands[3];
2904 rtx scratch0 = operands[4];
2905 rtx scratch0_si = gen_lowpart (SImode, scratch0);
2906 rtx scratch1 = operands[5];
2908 emit_insn (gen_divsi_inv_qitable (scratch0, tab_base, tab_ix));
2909 emit_insn (gen_ashldi3_media (scratch1, tab_ix, GEN_INT (1)));
2910 emit_insn (gen_mulsidi3_media (scratch0, norm32, scratch0_si));
2911 emit_insn (gen_divsi_inv_hitable (scratch1, tab_base, scratch1));
2912 emit_insn (gen_ashrdi3_media (scratch0, scratch0, GEN_INT (24)));
2913 emit_insn (gen_subdisi3_media (inv0, scratch1, scratch0));
2917 ;; operands: inv1, tab_base, tab_ix, norm32
2918 (define_insn_and_split "divsi_inv_m1"
2919 [(set (match_operand:SI 0 "register_operand" "=r")
2920 (unspec:SI [(match_operand:DI 1 "register_operand" "r")
2921 (match_operand:DI 2 "register_operand" "r")
2922 (match_operand:SI 3 "register_operand" "r")]
2924 (clobber (match_operand:SI 4 "register_operand" "=r"))
2925 (clobber (match_operand:DI 5 "register_operand" "=r"))
2926 (clobber (match_operand:DI 6 "register_operand" "=r"))
2927 (clobber (match_operand:DI 7 "register_operand" "=r"))
2928 (clobber (match_operand:DI 8 "register_operand" "=r"))]
2931 "&& !can_create_pseudo_p ()"
2935 muls.l r19, r19, r18 // u0.28
2936 muls.l r25, r18, r18 // s2.58
2937 shlli r19, 45, r0 // multiply by two and convert to s2.58
2939 shari r18, 28, r18 // some 18 bit inverse in s1.30
2942 rtx inv1 = operands[0];
2943 rtx tab_base = operands[1];
2944 rtx tab_ix = operands[2];
2945 rtx norm32 = operands[3];
2946 rtx inv0 = operands[4];
2947 rtx inv0_di = simplify_gen_subreg (DImode, inv0, SImode, 0);
2948 rtx scratch0a = operands[5];
2949 rtx scratch0b = operands[6];
2950 rtx scratch0 = operands[7];
2951 rtx scratch1 = operands[8];
2952 rtx scratch1_si = gen_lowpart (SImode, scratch1);
2954 emit_insn (gen_divsi_inv_m0 (inv0, tab_base, tab_ix, norm32,
2955 scratch0a, scratch0b));
2956 emit_insn (gen_mulsidi3_media (scratch1, inv0, inv0));
2957 emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch1_si));
2958 emit_insn (gen_ashldi3_media (scratch0, inv0_di, GEN_INT (45)));
2959 emit_insn (gen_subdi3 (scratch1, scratch0, scratch1));
2960 emit_insn (gen_ashrdisi3_media_opaque (inv1, scratch1, GEN_INT (28)));
2964 ;; operands: inv2, norm32, inv1, i92
2965 (define_insn_and_split "divsi_inv_m2"
2966 [(set (match_operand:SI 0 "register_operand" "=r")
2967 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2968 (match_operand:SI 2 "register_operand" "r")
2969 (match_operand:DI 3 "register_operand" "r")]
2971 (clobber (match_operand:DI 4 "register_operand" "=r"))]
2974 "&& !can_create_pseudo_p ()"
2978 muls.l r18, r25, r0 // s2.60
2979 shari r0, 16, r0 // s-16.44
2981 muls.l r0, r18, r19 // s-16.74
2982 shari r19, 30, r19 // s-16.44
2984 rtx inv2 = operands[0];
2985 rtx norm32 = operands[1];
2986 rtx inv1 = operands[2];
2987 rtx i92 = operands[3];
2988 rtx scratch0 = operands[4];
2989 rtx scratch0_si = gen_lowpart (SImode, scratch0);
2991 emit_insn (gen_mulsidi3_media (scratch0, inv1, norm32));
2992 emit_insn (gen_ashrdi3_media (scratch0, scratch0, GEN_INT (16)));
2993 emit_insn (gen_subdi3 (scratch0, i92, scratch0));
2994 emit_insn (gen_mulsidi3_media (scratch0, scratch0_si, inv1));
2995 emit_insn (gen_ashrdisi3_media_opaque (inv2, scratch0, GEN_INT (30)));
2999 (define_insn_and_split "divsi_inv_m3"
3000 [(set (match_operand:SI 0 "register_operand" "=r")
3001 (unspec:SI [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
3002 (match_operand:SI 2 "register_operand" "r")
3003 (match_operand:SI 3 "register_operand" "r")
3004 (match_operand:DI 4 "register_operand" "r")
3005 (match_operand:DI 5 "arith_reg_or_0_operand" "rN")
3006 (match_operand:DI 6 "arith_reg_or_0_operand" "rN")]
3008 (clobber (match_operand:DI 7 "register_operand" "=r"))
3009 (clobber (match_operand:DI 8 "register_operand" "=r"))
3010 (clobber (match_operand:DI 9 "register_operand" "=r"))
3011 (clobber (match_operand:DI 10 "register_operand" "=r"))
3012 (clobber (match_operand:SI 11 "register_operand" "=r"))
3013 (clobber (match_operand:SI 12 "register_operand" "=r"))
3014 (clobber (match_operand:DI 13 "register_operand" "=r"))]
3017 "&& !can_create_pseudo_p ()"
3021 r0: result r1: shift r4: dividend r18: inv1 r19: inv2
3022 r0: scratch0 r19: scratch1 r21: scratch2
3024 muls.l r18, r4, r25 // s32.30
3025 muls.l r19, r4, r19 // s15.30
3027 shari r19, 14, r19 // s18.-14
3033 rtx result = operands[0];
3034 rtx dividend = operands[1];
3035 rtx inv1 = operands[2];
3036 rtx inv2 = operands[3];
3037 rtx shift = operands[4];
3038 rtx scratch0 = operands[7];
3039 rtx scratch1 = operands[8];
3040 rtx scratch2 = operands[9];
3042 if (satisfies_constraint_N (dividend))
3044 emit_move_insn (result, dividend);
3048 emit_insn (gen_mulsidi3_media (scratch0, inv1, dividend));
3049 emit_insn (gen_mulsidi3_media (scratch1, inv2, dividend));
3050 emit_insn (gen_ashrdi3_media (scratch2, scratch0, GEN_INT (63)));
3051 emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (14)));
3052 emit_insn (gen_adddi3 (scratch0, scratch0, scratch1));
3053 emit_insn (gen_ashrdi3_media (scratch0, scratch0, shift));
3054 emit_insn (gen_subdisi3_media (result, scratch0, scratch2));
3058 ;; operands: quotient, dividend, inv1, inv2, shift, i2p27, i43
3059 ;; inv1: tab_base, tab_ix, norm32
3060 ;; inv2: norm32, inv1, i92
3061 (define_insn_and_split "divsi_inv_m1_3"
3062 [(set (match_operand:SI 0 "register_operand" "=r")
3063 (unspec:SI [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
3064 (unspec:SI [(match_operand:DI 2 "register_operand" "r")
3065 (match_operand:DI 3 "register_operand" "r")
3066 (match_operand:SI 4 "register_operand" "r")]
3068 (unspec:SI [(match_dup 4)
3069 (unspec:SI [(match_dup 2)
3071 (match_dup 4)] UNSPEC_DIV_INV_M1)
3072 (match_operand:SI 5 "" "")]
3074 (match_operand:DI 6 "register_operand" "r")
3075 (match_operand:DI 7 "arith_reg_or_0_operand" "rN")
3076 (match_operand:DI 8 "arith_reg_or_0_operand" "rN")]
3078 (clobber (match_operand:DI 9 "register_operand" "=r"))
3079 (clobber (match_operand:DI 10 "register_operand" "=r"))
3080 (clobber (match_operand:DI 11 "register_operand" "=r"))
3081 (clobber (match_operand:DI 12 "register_operand" "=r"))
3082 (clobber (match_operand:SI 13 "register_operand" "=r"))
3083 (clobber (match_operand:SI 14 "register_operand" "=r"))
3084 (clobber (match_operand:DI 15 "register_operand" "=r"))]
3086 && (TARGET_DIVIDE_INV_MINLAT
3087 || TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)"
3089 "&& !can_create_pseudo_p ()"
3092 rtx result = operands[0];
3093 rtx dividend = operands[1];
3094 rtx tab_base = operands[2];
3095 rtx tab_ix = operands[3];
3096 rtx norm32 = operands[4];
3097 /* rtx i92 = operands[5]; */
3098 rtx shift = operands[6];
3099 rtx i2p27 = operands[7];
3100 rtx i43 = operands[8];
3101 rtx scratch0 = operands[9];
3102 rtx scratch0_si = gen_lowpart (SImode, scratch0);
3103 rtx scratch1 = operands[10];
3104 rtx scratch1_si = gen_lowpart (SImode, scratch1);
3105 rtx scratch2 = operands[11];
3106 rtx scratch3 = operands[12];
3107 rtx scratch4 = operands[13];
3108 rtx scratch4_di = simplify_gen_subreg (DImode, scratch4, SImode, 0);
3109 rtx scratch5 = operands[14];
3110 rtx scratch5_di = simplify_gen_subreg (DImode, scratch5, SImode, 0);
3111 rtx scratch6 = operands[15];
3113 emit_insn (gen_divsi_inv_m0 (scratch4, tab_base, tab_ix, norm32,
3114 scratch0, scratch1));
3115 /* inv0 == scratch4 */
3116 if (! TARGET_DIVIDE_INV20U)
3118 emit_insn (gen_mulsidi3_media (scratch0, scratch4, scratch4));
3120 emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch0_si));
3124 emit_insn (gen_mulsidi3_media (scratch1, scratch4, scratch4));
3125 emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch1_si));
3127 emit_insn (gen_ashldi3_media (scratch2, scratch4_di, GEN_INT (45)));
3128 emit_insn (gen_subdi3 (scratch1, scratch2, scratch1));
3129 emit_insn (gen_ashrdisi3_media_opaque (scratch4, scratch1, GEN_INT (28)));
3130 /* inv1 == scratch4 */
3132 if (TARGET_DIVIDE_INV_MINLAT)
3134 emit_insn (gen_mulsidi3_media (scratch1, scratch4, norm32));
3135 emit_insn (gen_mulsidi3_media (scratch2, dividend, scratch4));
3136 emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (16)));
3137 emit_insn (gen_mulsidi3_media (scratch1, scratch1_si, scratch4));
3138 emit_insn (gen_ashrdi3_media (scratch3, scratch2, GEN_INT (63)));
3139 emit_insn (gen_ashrsi3_media (scratch5, dividend, GEN_INT (14)));
3140 emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (30)));
3141 emit_insn (gen_mulsidi3_media (scratch1, scratch1_si, scratch5));
3142 emit_insn (gen_xordi3 (scratch0, scratch3, i2p27));
3143 emit_insn (gen_adddi3 (scratch2, scratch2, scratch0));
3144 emit_insn (gen_subdi3 (scratch2, scratch2, scratch1));
3148 rtx label = gen_rtx_LABEL_REF (Pmode, gen_label_rtx ());
3149 /* Use separate scratch regs for nsb and sign to allow scheduling. */
3150 emit_insn (gen_nsbdi (scratch6,
3151 simplify_gen_subreg (DImode, dividend, SImode, 0)));
3152 emit_insn (gen_xorsi3 (scratch5, dividend, norm32));
3153 emit_insn (gen_ashrdi3_media (scratch3, scratch5_di, GEN_INT (63)));
3154 emit_insn (gen_divsi_inv20 (scratch2,
3155 norm32, scratch4, dividend,
3156 scratch6, scratch3, i43,
3157 /* scratch0 may be shared with i2p27. */
3158 scratch0, scratch1, scratch5,
3159 label, label, i2p27));
3161 emit_insn (gen_ashrdi3_media (scratch2, scratch2, shift));
3162 emit_insn (gen_subdisi3_media (result, scratch2, scratch3));
3166 (define_insn "divsi_inv20"
3167 [(set (match_operand:DI 0 "register_operand" "=&r")
3168 (unspec:DI [(match_operand:SI 1 "register_operand" "r")
3169 (match_operand:SI 2 "register_operand" "r")
3170 (match_operand:SI 3 "register_operand" "r")
3171 (match_operand:DI 4 "register_operand" "r")
3172 (match_operand:DI 5 "register_operand" "r")
3173 (match_operand:DI 6 "register_operand" "r")
3174 (match_operand:DI 12 "register_operand" "r")
3175 (match_operand 10 "target_operand" "b")
3176 (match_operand 11 "immediate_operand" "i")]
3178 (clobber (match_operand:DI 7 "register_operand" "=&r"))
3179 (clobber (match_operand:DI 8 "register_operand" "=&r"))
3180 (clobber (match_operand:SI 9 "register_operand" "=r"))]
3182 && (TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)"
3184 /* operands: %0 div_result, %1 norm32, %2 inv1, %3 dividend,
3185 %4 dividend_nsb, %5 result_sign, %6 i43, %12 i2p27,
3186 %7 round_scratch, %8 scratch0 (di), %9 scratch1 (si)
3187 %10 label (tr), %11 label (imm)
3189 muls.l inv1, norm32, scratch0 // s2.60
3190 muls.l inv1, dividend, result // s32.30
3191 xor i2p27, result_sign, round_scratch
3192 bge/u dividend_nsb, i43, tr.. (label)
3193 shari scratch0, 16, scratch0 // s-16.44
3194 muls.l sratch0_si, inv1, scratch0 // s-16.74
3195 sub result, round_scratch, result
3196 shari dividend, 14, scratch1 // s19.-14
3197 shari scratch0, 30, scratch0 // s-16.44
3198 muls.l scratch0, scratch1, round_scratch // s15.30
3200 sub result, round_scratch, result */
3202 const bool likely = TARGET_DIVIDE_INV20L;
3205 "muls.l %2, %3, %0" "\n"
3206 " xor %12, %5, %7" "\n"
3207 " bge/l %4, %6, %10" "\n"
3208 " muls.l %2, %1, %8" "\n"
3209 " shari %8, 16, %8" "\n"
3210 " muls.l %8, %2, %8" "\n"
3211 " shari %3, 14, %9" "\n"
3212 " shari %8, 30, %8" "\n"
3213 " muls.l %8, %9, %8" "\n"
3214 " sub %0, %8, %0" "\n"
3215 "%11: add %0, %7, %0";
3218 "muls.l %2, %1, %8" "\n"
3219 " muls.l %2, %3, %0" "\n"
3220 " xor %12, %5, %7" "\n"
3221 " bge/u %4, %6, %10" "\n"
3222 " shari %8, 16, %8" "\n"
3223 " muls.l %8, %2, %8" "\n"
3224 " sub %0, %7, %0" "\n"
3225 " shari %3, 14, %9" "\n"
3226 " shari %8, 30, %8" "\n"
3227 " muls.l %8, %9, %7" "\n"
3228 "%11: sub %0, %7, %0";
3231 (define_insn_and_split "divsi_inv_fp"
3232 [(set (match_operand:SI 0 "general_movdst_operand" "=rf")
3233 (div:SI (match_operand:SI 1 "general_movsrc_operand" "rf")
3234 (match_operand:SI 2 "register_operand" "rf")))
3235 (use (match_operand:SI 3 "general_movsrc_operand" "r"))
3236 (clobber (match_operand:SI 4 "register_operand" "=r"))
3237 (clobber (match_operand:SI 5 "register_operand" "=r"))
3238 (clobber (match_operand:DF 6 "register_operand" "=r"))
3239 (clobber (match_operand:DF 7 "register_operand" "=r"))
3240 (clobber (match_operand:DF 8 "register_operand" "=r"))]
3241 "TARGET_SHMEDIA_FPU"
3243 "&& (reload_in_progress || reload_completed)"
3244 [(set (match_dup 0) (match_dup 3))]
3246 [(set_attr "highpart" "must_split")])
3248 ;; If a matching group of divide-by-inverse instructions is in the same
3249 ;; basic block after gcse & loop optimizations, we want to transform them
3250 ;; to a straight division using floating point for TARGET_DIVIDE_INV_FP.
3251 (define_insn_and_split "*divsi_inv_fp_combine"
3252 [(set (match_operand:SI 0 "register_operand" "=f")
3253 (div:SI (match_operand:SI 1 "register_operand" "f")
3254 (match_operand:SI 2 "register_operand" "f")))
3255 (use (unspec:SI [(match_dup 1)
3256 (match_operand:SI 3 "" "")
3257 (unspec:SI [(match_operand:SI 4 "" "")
3259 (match_operand:DI 5 "" "")] UNSPEC_DIV_INV_M2)
3260 (match_operand:DI 6 "" "")
3262 (const_int 0)] UNSPEC_DIV_INV_M3))
3263 (clobber (match_operand:SI 7 "fp_arith_reg_operand" ""))
3264 (clobber (match_operand:SI 8 "fp_arith_reg_operand" ""))
3265 (clobber (match_operand:DF 9 "fp_arith_reg_operand" ""))
3266 (clobber (match_operand:DF 10 "fp_arith_reg_operand" ""))
3267 (clobber (match_operand:DF 11 "fp_arith_reg_operand" ""))]
3268 "TARGET_SHMEDIA_FPU && TARGET_DIVIDE_INV_FP && !can_create_pseudo_p ()"
3271 [(set (match_dup 9) (float:DF (match_dup 1)))
3272 (set (match_dup 10) (float:DF (match_dup 2)))
3273 (set (match_dup 11) (div:DF (match_dup 9) (match_dup 10)))
3275 (fix:SI (match_dup 11)))
3276 (set (match_dup 0) (match_dup 8))]
3278 if (! fp_arith_reg_operand (operands[1], SImode))
3280 emit_move_insn (operands[7], operands[1]);
3281 operands[1] = operands[7];
3283 if (! fp_arith_reg_operand (operands[2], SImode))
3285 emit_move_insn (operands[8], operands[2]);
3286 operands[2] = operands[8];
3289 [(set_attr "highpart" "must_split")])
3291 ;; -------------------------------------------------------------------------
3292 ;; Multiplication instructions
3293 ;; -------------------------------------------------------------------------
3295 (define_insn "umulhisi3_i"
3296 [(set (reg:SI MACL_REG)
3297 (mult:SI (zero_extend:SI
3298 (match_operand:HI 0 "arith_reg_operand" "r"))
3300 (match_operand:HI 1 "arith_reg_operand" "r"))))]
3303 [(set_attr "type" "smpy")])
3305 (define_insn "mulhisi3_i"
3306 [(set (reg:SI MACL_REG)
3307 (mult:SI (sign_extend:SI
3308 (match_operand:HI 0 "arith_reg_operand" "r"))
3310 (match_operand:HI 1 "arith_reg_operand" "r"))))]
3313 [(set_attr "type" "smpy")])
3315 (define_expand "mulhisi3"
3316 [(set (reg:SI MACL_REG)
3317 (mult:SI (sign_extend:SI
3318 (match_operand:HI 1 "arith_reg_operand" ""))
3320 (match_operand:HI 2 "arith_reg_operand" ""))))
3321 (set (match_operand:SI 0 "arith_reg_operand" "")
3328 macl = gen_rtx_REG (SImode, MACL_REG);
3330 emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
3331 insn = get_insns ();
3333 /* expand_binop can't find a suitable code in umul_widen_optab to
3334 make a REG_EQUAL note from, so make one here.
3335 See also smulsi3_highpart.
3336 ??? Alternatively, we could put this at the calling site of expand_binop,
3337 i.e. expand_expr. */
3338 /* Use emit_libcall_block for loop invariant code motion and to make
3339 a REG_EQUAL note. */
3340 emit_libcall_block (insn, operands[0], macl, SET_SRC (single_set (insn)));
3345 (define_expand "umulhisi3"
3346 [(set (reg:SI MACL_REG)
3347 (mult:SI (zero_extend:SI
3348 (match_operand:HI 1 "arith_reg_operand" ""))
3350 (match_operand:HI 2 "arith_reg_operand" ""))))
3351 (set (match_operand:SI 0 "arith_reg_operand" "")
3358 macl = gen_rtx_REG (SImode, MACL_REG);
3360 emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
3361 insn = get_insns ();
3363 /* expand_binop can't find a suitable code in umul_widen_optab to
3364 make a REG_EQUAL note from, so make one here.
3365 See also smulsi3_highpart.
3366 ??? Alternatively, we could put this at the calling site of expand_binop,
3367 i.e. expand_expr. */
3368 /* Use emit_libcall_block for loop invariant code motion and to make
3369 a REG_EQUAL note. */
3370 emit_libcall_block (insn, operands[0], macl, SET_SRC (single_set (insn)));
3375 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
3376 ;; a call to a routine which clobbers known registers.
3378 [(set (match_operand:SI 1 "register_operand" "=z")
3379 (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
3380 (clobber (reg:SI MACL_REG))
3381 (clobber (reg:SI T_REG))
3382 (clobber (reg:SI PR_REG))
3383 (clobber (reg:SI R3_REG))
3384 (clobber (reg:SI R2_REG))
3385 (clobber (reg:SI R1_REG))
3386 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
3389 [(set_attr "type" "sfunc")
3390 (set_attr "needs_delay_slot" "yes")])
3392 (define_expand "mulsi3_call"
3393 [(set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
3394 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
3395 (parallel[(set (match_operand:SI 0 "register_operand" "")
3396 (mult:SI (reg:SI R4_REG)
3398 (clobber (reg:SI MACL_REG))
3399 (clobber (reg:SI T_REG))
3400 (clobber (reg:SI PR_REG))
3401 (clobber (reg:SI R3_REG))
3402 (clobber (reg:SI R2_REG))
3403 (clobber (reg:SI R1_REG))
3404 (use (match_operand:SI 3 "register_operand" ""))])]
3408 (define_insn "mul_r"
3409 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3410 (mult:SI (match_operand:SI 1 "arith_reg_operand" "0")
3411 (match_operand:SI 2 "arith_reg_operand" "z")))]
3414 [(set_attr "type" "dmpy")])
3416 (define_insn "mul_l"
3417 [(set (reg:SI MACL_REG)
3418 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
3419 (match_operand:SI 1 "arith_reg_operand" "r")))]
3422 [(set_attr "type" "dmpy")])
3424 (define_expand "mulsi3"
3425 [(set (reg:SI MACL_REG)
3426 (mult:SI (match_operand:SI 1 "arith_reg_operand" "")
3427 (match_operand:SI 2 "arith_reg_operand" "")))
3428 (set (match_operand:SI 0 "arith_reg_operand" "")
3434 /* The address must be set outside the libcall,
3435 since it goes into a pseudo. */
3436 rtx sym = function_symbol (NULL, "__mulsi3", SFUNC_STATIC);
3437 rtx addr = force_reg (SImode, sym);
3438 rtx insns = gen_mulsi3_call (operands[0], operands[1],
3444 rtx macl = gen_rtx_REG (SImode, MACL_REG);
3446 emit_insn (gen_mul_l (operands[1], operands[2]));
3447 /* consec_sets_giv can only recognize the first insn that sets a
3448 giv as the giv insn. So we must tag this also with a REG_EQUAL
3450 emit_insn (gen_movsi_i ((operands[0]), macl));
3455 (define_insn "mulsidi3_i"
3456 [(set (reg:SI MACH_REG)
3460 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3461 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3463 (set (reg:SI MACL_REG)
3464 (mult:SI (match_dup 0)
3468 [(set_attr "type" "dmpy")])
3470 (define_expand "mulsidi3"
3471 [(set (match_operand:DI 0 "arith_reg_dest" "")
3472 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3473 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))]
3474 "TARGET_SH2 || TARGET_SHMEDIA"
3478 emit_insn (gen_mulsidi3_compact (operands[0], operands[1], operands[2]));
3483 (define_insn "mulsidi3_media"
3484 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3485 (mult:DI (sign_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
3486 (sign_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
3489 [(set_attr "type" "dmpy_media")
3490 (set_attr "highpart" "ignore")])
3492 (define_insn_and_split "mulsidi3_compact"
3493 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3495 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
3496 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
3497 (clobber (reg:SI MACH_REG))
3498 (clobber (reg:SI MACL_REG))]
3504 rtx low_dst = gen_lowpart (SImode, operands[0]);
3505 rtx high_dst = gen_highpart (SImode, operands[0]);
3507 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
3509 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
3510 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
3511 /* We need something to tag the possible REG_EQUAL notes on to. */
3512 emit_move_insn (operands[0], operands[0]);
3516 (define_insn "umulsidi3_i"
3517 [(set (reg:SI MACH_REG)
3521 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3522 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3524 (set (reg:SI MACL_REG)
3525 (mult:SI (match_dup 0)
3529 [(set_attr "type" "dmpy")])
3531 (define_expand "umulsidi3"
3532 [(set (match_operand:DI 0 "arith_reg_dest" "")
3533 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3534 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))]
3535 "TARGET_SH2 || TARGET_SHMEDIA"
3539 emit_insn (gen_umulsidi3_compact (operands[0], operands[1], operands[2]));
3544 (define_insn "umulsidi3_media"
3545 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3546 (mult:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
3547 (zero_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
3550 [(set_attr "type" "dmpy_media")
3551 (set_attr "highpart" "ignore")])
3553 (define_insn_and_split "umulsidi3_compact"
3554 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3556 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
3557 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
3558 (clobber (reg:SI MACH_REG))
3559 (clobber (reg:SI MACL_REG))]
3565 rtx low_dst = gen_lowpart (SImode, operands[0]);
3566 rtx high_dst = gen_highpart (SImode, operands[0]);
3568 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
3570 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
3571 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
3572 /* We need something to tag the possible REG_EQUAL notes on to. */
3573 emit_move_insn (operands[0], operands[0]);
3577 (define_insn "smulsi3_highpart_i"
3578 [(set (reg:SI MACH_REG)
3582 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3583 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3585 (clobber (reg:SI MACL_REG))]
3588 [(set_attr "type" "dmpy")])
3590 (define_expand "smulsi3_highpart"
3592 [(set (reg:SI MACH_REG)
3596 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3597 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
3599 (clobber (reg:SI MACL_REG))])
3600 (set (match_operand:SI 0 "arith_reg_operand" "")
3607 mach = gen_rtx_REG (SImode, MACH_REG);
3609 emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
3610 insn = get_insns ();
3612 /* expand_binop can't find a suitable code in mul_highpart_optab to
3613 make a REG_EQUAL note from, so make one here.
3614 See also {,u}mulhisi.
3615 ??? Alternatively, we could put this at the calling site of expand_binop,
3616 i.e. expand_mult_highpart. */
3617 /* Use emit_libcall_block for loop invariant code motion and to make
3618 a REG_EQUAL note. */
3619 emit_libcall_block (insn, operands[0], mach, SET_SRC (single_set (insn)));
3624 (define_insn "umulsi3_highpart_i"
3625 [(set (reg:SI MACH_REG)
3629 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3630 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3632 (clobber (reg:SI MACL_REG))]
3635 [(set_attr "type" "dmpy")])
3637 (define_expand "umulsi3_highpart"
3639 [(set (reg:SI MACH_REG)
3643 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3644 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
3646 (clobber (reg:SI MACL_REG))])
3647 (set (match_operand:SI 0 "arith_reg_operand" "")
3654 mach = gen_rtx_REG (SImode, MACH_REG);
3656 emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
3657 insn = get_insns ();
3659 /* Use emit_libcall_block for loop invariant code motion and to make
3660 a REG_EQUAL note. */
3661 emit_libcall_block (insn, operands[0], mach, SET_SRC (single_set (insn)));
3666 (define_insn_and_split "muldi3"
3667 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3668 (mult:DI (match_operand:DI 1 "arith_reg_operand" "r")
3669 (match_operand:DI 2 "arith_reg_operand" "r")))
3670 (clobber (match_scratch:DI 3 "=&r"))
3671 (clobber (match_scratch:DI 4 "=r"))]
3677 rtx op3_v2si, op2_v2si;
3679 op3_v2si = operands[3];
3680 if (GET_CODE (op3_v2si) == SIGN_EXTEND)
3682 op3_v2si = XEXP (op3_v2si, 0);
3683 op3_v2si = simplify_gen_subreg (DImode, op3_v2si, GET_MODE (op3_v2si), 0);
3685 op3_v2si = simplify_gen_subreg (V2SImode, op3_v2si, DImode, 0);
3686 op2_v2si = operands[2];
3687 if (GET_CODE (op2_v2si) == SIGN_EXTEND)
3689 op2_v2si = XEXP (op2_v2si, 0);
3690 op2_v2si = simplify_gen_subreg (DImode, op2_v2si, GET_MODE (op2_v2si), 0);
3692 op2_v2si = simplify_gen_subreg (V2SImode, op2_v2si, DImode, 0);
3693 emit_insn (gen_rotldi3 (operands[3], operands[1], GEN_INT (32)));
3694 emit_insn (gen_mulv2si3 (op3_v2si, op3_v2si, op2_v2si));
3695 emit_insn (gen_umulsidi3_media (operands[4],
3696 sh_gen_truncate (SImode, operands[1], 0),
3697 sh_gen_truncate (SImode, operands[2], 0)));
3698 emit_insn (gen_anddi3 (operands[0], operands[3], GEN_INT (0xffffffff00000000LL)));
3699 emit_insn (gen_ashldi3_media (operands[3], operands[3], GEN_INT (32)));
3700 emit_insn (gen_adddi3 (operands[0], operands[3], operands[0]));
3701 emit_insn (gen_adddi3 (operands[0], operands[4], operands[0]));
3705 ;; -------------------------------------------------------------------------
3706 ;; Logical operations
3707 ;; -------------------------------------------------------------------------
3709 (define_expand "andsi3"
3710 [(set (match_operand:SI 0 "arith_reg_operand" "")
3711 (and:SI (match_operand:SI 1 "logical_reg_operand" "")
3712 (match_operand:SI 2 "logical_and_operand" "")))]
3715 /* If it is possible to turn the and insn into a zero extension
3716 already, redundant zero extensions will be folded, which results
3718 Ideally the splitter of *andsi_compact would be enough, if redundant
3719 zero extensions were detected after the combine pass, which does not
3720 happen at the moment. */
3723 if (satisfies_constraint_Jmb (operands[2]))
3725 emit_insn (gen_zero_extendqisi2 (operands[0],
3726 gen_lowpart (QImode, operands[1])));
3729 else if (satisfies_constraint_Jmw (operands[2]))
3731 emit_insn (gen_zero_extendhisi2 (operands[0],
3732 gen_lowpart (HImode, operands[1])));
3738 (define_insn_and_split "*andsi_compact"
3739 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r,z,r")
3740 (and:SI (match_operand:SI 1 "arith_reg_operand" "%r,r,0,0")
3741 (match_operand:SI 2 "logical_and_operand" "Jmb,Jmw,K08,r")))]
3749 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
3751 if (satisfies_constraint_Jmb (operands[2]))
3752 operands[1] = gen_lowpart (QImode, operands[1]);
3753 else if (satisfies_constraint_Jmw (operands[2]))
3754 operands[1] = gen_lowpart (HImode, operands[1]);
3758 [(set_attr "type" "arith")])
3760 (define_insn "*andsi3_media"
3761 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3762 (and:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
3763 (match_operand:SI 2 "logical_operand" "r,I10")))]
3768 [(set_attr "type" "arith_media")])
3770 (define_insn "*andsi3_bclr"
3771 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3772 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0")
3773 (match_operand:SI 2 "const_int_operand" "Psz")))]
3774 "TARGET_SH2A && satisfies_constraint_Psz (operands[2])"
3776 [(set_attr "type" "arith")])
3778 (define_insn_and_split "anddi3"
3779 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r,r")
3780 (and:DI (match_operand:DI 1 "arith_reg_operand" "%r,r,r")
3781 (match_operand:DI 2 "and_operand" "r,I10,J16")))]
3788 && ! logical_operand (operands[2], DImode)"
3791 if ((unsigned)INTVAL (operands[2]) == (unsigned) 0xffffffff)
3792 emit_insn (gen_mshflo_l_di (operands[0], operands[1], CONST0_RTX (DImode)));
3794 emit_insn (gen_mshfhi_l_di (operands[0], CONST0_RTX (DImode), operands[1]));
3797 [(set_attr "type" "arith_media")])
3799 (define_insn "andcsi3"
3800 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3801 (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
3802 (not:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
3805 [(set_attr "type" "arith_media")])
3807 (define_insn "andcdi3"
3808 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3809 (and:DI (match_operand:DI 1 "arith_reg_operand" "r")
3810 (not:DI (match_operand:DI 2 "arith_reg_operand" "r"))))]
3813 [(set_attr "type" "arith_media")])
3815 (define_expand "iorsi3"
3816 [(set (match_operand:SI 0 "arith_reg_operand" "")
3817 (ior:SI (match_operand:SI 1 "logical_reg_operand" "")
3818 (match_operand:SI 2 "logical_operand" "")))]
3822 (define_insn "*iorsi3_compact"
3823 [(set (match_operand:SI 0 "arith_reg_dest" "=r,z")
3824 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
3825 (match_operand:SI 2 "logical_operand" "r,K08")))]
3827 && !(TARGET_SH2A && satisfies_constraint_Pso (operands[2]))"
3829 [(set_attr "type" "arith")])
3831 (define_insn "*iorsi3_media"
3832 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3833 (ior:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
3834 (match_operand:SI 2 "logical_operand" "r,I10")))]
3839 [(set_attr "type" "arith_media")])
3841 (define_insn "*iorsi3_bset"
3842 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3843 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0")
3844 (match_operand:SI 2 "const_int_operand" "Pso")))]
3845 "TARGET_SH2A && satisfies_constraint_Pso (operands[2])"
3847 [(set_attr "type" "arith")])
3849 (define_insn "iordi3"
3850 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3851 (ior:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
3852 (match_operand:DI 2 "logical_operand" "r,I10")))]
3857 [(set_attr "type" "arith_media")])
3859 (define_insn_and_split "*logical_sidi3"
3860 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3861 (sign_extend:DI (match_operator:SI 3 "logical_operator"
3862 [(match_operand:SI 1 "arith_reg_operand" "%r,r")
3863 (match_operand:SI 2 "logical_operand" "r,I10")])))]
3866 "&& reload_completed"
3867 [(set (match_dup 0) (match_dup 3))]
3870 = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
3871 simplify_gen_subreg (DImode, operands[1], SImode, 0),
3872 simplify_gen_subreg (DImode, operands[2], SImode, 0));
3875 (define_insn_and_split "*logical_sidisi3"
3876 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3877 (truncate:SI (sign_extend:DI
3878 (match_operator:SI 3 "logical_operator"
3879 [(match_operand:SI 1 "arith_reg_operand" "%r,r")
3880 (match_operand:SI 2 "logical_operand" "r,I10")]))))]
3884 [(set (match_dup 0) (match_dup 3))])
3886 (define_insn_and_split "*logical_sidi3_2"
3887 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3888 (sign_extend:DI (truncate:SI (sign_extend:DI
3889 (match_operator:SI 3 "logical_operator"
3890 [(match_operand:SI 1 "arith_reg_operand" "%r,r")
3891 (match_operand:SI 2 "logical_operand" "r,I10")])))))]
3895 [(set (match_dup 0) (sign_extend:DI (match_dup 3)))])
3897 (define_expand "xorsi3"
3898 [(set (match_operand:SI 0 "arith_reg_operand" "")
3899 (xor:SI (match_operand:SI 1 "logical_reg_operand" "")
3900 (match_operand:SI 2 "xor_operand" "")))]
3904 (define_insn "*xorsi3_compact"
3905 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
3906 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
3907 (match_operand:SI 2 "logical_operand" "K08,r")))]
3910 [(set_attr "type" "arith")])
3912 ;; The *logical_op_t pattern helps combine eliminating sign/zero extensions
3913 ;; of results where one of the inputs is a T bit store. Notice that this
3914 ;; pattern must not match during reload. If reload picks this pattern it
3915 ;; will be impossible to split it afterwards.
3916 (define_insn_and_split "*logical_op_t"
3917 [(set (match_operand:SI 0 "arith_reg_dest")
3918 (match_operator:SI 3 "logical_operator"
3919 [(match_operand:SI 1 "arith_reg_operand")
3920 (match_operand:SI 2 "t_reg_operand")]))]
3921 "TARGET_SH1 && can_create_pseudo_p ()"
3924 [(set (match_dup 4) (reg:SI T_REG))
3925 (set (match_dup 0) (match_dup 3))]
3927 operands[4] = gen_reg_rtx (SImode);
3928 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3929 operands[1], operands[4]);
3932 (define_insn "*xorsi3_media"
3933 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3934 (xor:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
3935 (match_operand:SI 2 "xor_operand" "r,I06")))]
3940 [(set_attr "type" "arith_media")])
3942 (define_insn "xordi3"
3943 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3944 (xor:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
3945 (match_operand:DI 2 "xor_operand" "r,I06")))]
3950 [(set_attr "type" "arith_media")])
3952 ;; Combiner bridge pattern for 2 * sign extend -> logical op -> truncate.
3953 ;; converts 2 * sign extend -> logical op into logical op -> sign extend
3955 [(set (match_operand:DI 0 "arith_reg_dest" "")
3956 (sign_extend:DI (match_operator 4 "binary_logical_operator"
3957 [(match_operand 1 "any_register_operand" "")
3958 (match_operand 2 "any_register_operand" "")])))]
3960 [(set (match_dup 5) (match_dup 4))
3961 (set (match_dup 0) (sign_extend:DI (match_dup 5)))]
3963 machine_mode inmode = GET_MODE (operands[1]);
3966 if (GET_CODE (operands[0]) == SUBREG)
3968 offset = SUBREG_BYTE (operands[0]);
3969 operands[0] = SUBREG_REG (operands[0]);
3971 gcc_assert (REG_P (operands[0]));
3972 if (TARGET_BIG_ENDIAN)
3973 offset += 8 - GET_MODE_SIZE (inmode);
3974 operands[5] = gen_rtx_SUBREG (inmode, operands[0], offset);
3977 ;; -------------------------------------------------------------------------
3978 ;; Shifts and rotates
3979 ;; -------------------------------------------------------------------------
3981 (define_expand "rotldi3"
3982 [(set (match_operand:DI 0 "arith_reg_dest" "")
3983 (rotate:DI (match_operand:DI 1 "arith_reg_operand" "")
3984 (match_operand:HI 2 "mextr_bit_offset" "")))]
3987 if (! mextr_bit_offset (operands[2], HImode))
3991 (define_insn "rotldi3_mextr"
3992 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3993 (rotate:DI (match_operand:DI 1 "arith_reg_operand" "r")
3994 (match_operand:HI 2 "mextr_bit_offset" "i")))]
3997 static char templ[16];
3998 sprintf (templ, "mextr%d %%1,%%1,%%0",
3999 8 - (int) (INTVAL (operands[2]) >> 3));
4002 [(set_attr "type" "arith_media")])
4004 (define_expand "rotrdi3"
4005 [(set (match_operand:DI 0 "arith_reg_dest" "")
4006 (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "")
4007 (match_operand:HI 2 "mextr_bit_offset" "")))]
4010 if (! mextr_bit_offset (operands[2], HImode))
4014 (define_insn "rotrdi3_mextr"
4015 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4016 (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "r")
4017 (match_operand:HI 2 "mextr_bit_offset" "i")))]
4020 static char templ[16];
4021 sprintf (templ, "mextr%d %%1,%%1,%%0", (int) INTVAL (operands[2]) >> 3);
4024 [(set_attr "type" "arith_media")])
4027 [(set (match_operand:DI 0 "arith_reg_dest" "")
4028 (ior:DI (zero_extend:DI (mem:QI (match_operand 1
4029 "ua_address_operand" "")))
4030 (ashift:DI (match_operand:DI 2 "arith_reg_operand" "")
4032 (clobber (match_operand:DI 3 "register_operand" ""))]
4034 [(match_dup 4) (match_dup 5)]
4036 operands[4] = ((TARGET_LITTLE_ENDIAN ? gen_ldhi_q : gen_ldlo_q)
4037 (operands[3], operands[1]));
4038 operands[5] = gen_mextr_rl (operands[0], operands[3], operands[2],
4039 GEN_INT (56), GEN_INT (8));
4042 (define_expand "rotrsi3"
4043 [(set (match_operand:SI 0 "arith_reg_dest")
4044 (rotatert:SI (match_operand:SI 1 "arith_reg_operand")
4045 (match_operand:SI 2 "const_int_operand")))]
4048 HOST_WIDE_INT ival = INTVAL (operands[2]);
4051 emit_insn (gen_rotrsi3_1 (operands[0], operands[1]));
4058 (define_insn "rotrsi3_1"
4059 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4060 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
4063 (and:SI (match_dup 1) (const_int 1)))]
4066 [(set_attr "type" "arith")])
4068 ;; A slimplified version of rotr for combine.
4069 (define_insn "*rotrsi3_1"
4070 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4071 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
4073 (clobber (reg:SI T_REG))]
4076 [(set_attr "type" "arith")])
4078 (define_insn "rotlsi3_1"
4079 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4080 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
4083 (lshiftrt:SI (match_dup 1) (const_int 31)))]
4086 [(set_attr "type" "arith")])
4088 ;; A simplified version of rotl for combine.
4089 (define_insn "*rotlsi3_1"
4090 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4091 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
4093 (clobber (reg:SI T_REG))]
4096 [(set_attr "type" "arith")])
4098 (define_insn "rotlsi3_31"
4099 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4100 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
4102 (clobber (reg:SI T_REG))]
4105 [(set_attr "type" "arith")])
4107 (define_insn "rotlsi3_16"
4108 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4109 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
4113 [(set_attr "type" "arith")])
4115 (define_expand "rotlsi3"
4116 [(set (match_operand:SI 0 "arith_reg_dest")
4117 (rotate:SI (match_operand:SI 1 "arith_reg_operand")
4118 (match_operand:SI 2 "const_int_operand")))]
4121 static const char rot_tab[] = {
4122 000, 000, 000, 000, 000, 000, 010, 001,
4123 001, 001, 011, 013, 003, 003, 003, 003,
4124 003, 003, 003, 003, 003, 013, 012, 002,
4125 002, 002, 010, 000, 000, 000, 000, 000,
4128 int count = INTVAL (operands[2]);
4129 int choice = rot_tab[count];
4130 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
4136 emit_move_insn (operands[0], operands[1]);
4137 count -= (count & 16) * 2;
4140 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
4147 parts[0] = gen_reg_rtx (SImode);
4148 parts[1] = gen_reg_rtx (SImode);
4149 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
4150 emit_move_insn (parts[choice-1], operands[1]);
4151 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
4152 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
4153 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
4154 count = (count & ~16) - 8;
4158 for (; count > 0; count--)
4159 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
4160 for (; count < 0; count++)
4161 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
4166 (define_insn "rotlhi3_8"
4167 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4168 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
4172 [(set_attr "type" "arith")])
4174 (define_expand "rotlhi3"
4175 [(set (match_operand:HI 0 "arith_reg_operand")
4176 (rotate:HI (match_operand:HI 1 "arith_reg_operand")
4177 (match_operand:HI 2 "const_int_operand")))]
4180 if (INTVAL (operands[2]) != 8)
4184 ;; The rotcr and rotcl insns are used primarily in DImode shifts by one.
4185 ;; They can also be used to implement things like
4187 ;; int x0 = (y >> 1) | (t << 31); // rotcr
4188 ;; int x1 = (y << 1) | t; // rotcl
4189 (define_insn "rotcr"
4190 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4191 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4193 (ashift:SI (match_operand:SI 2 "t_reg_operand")
4196 (and:SI (match_dup 1) (const_int 1)))]
4199 [(set_attr "type" "arith")])
4201 (define_insn "rotcl"
4202 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4203 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4205 (match_operand:SI 2 "t_reg_operand")))
4207 (lshiftrt:SI (match_dup 1) (const_int 31)))]
4210 [(set_attr "type" "arith")])
4212 ;; Simplified rotcr version for combine, which allows arbitrary shift
4213 ;; amounts for the reg. If the shift amount is '1' rotcr can be used
4214 ;; directly. Otherwise we have to insert a shift in between.
4215 (define_insn_and_split "*rotcr"
4216 [(set (match_operand:SI 0 "arith_reg_dest")
4217 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
4218 (match_operand:SI 2 "const_int_operand"))
4219 (ashift:SI (match_operand:SI 3 "arith_reg_or_t_reg_operand")
4221 (clobber (reg:SI T_REG))]
4224 "&& can_create_pseudo_p ()"
4227 if (INTVAL (operands[2]) > 1)
4229 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
4230 rtx prev_set_t_insn = NULL_RTX;
4231 rtx tmp_t_reg = NULL_RTX;
4233 /* If we're going to emit a shift sequence that clobbers the T_REG,
4234 try to find the previous insn that sets the T_REG and emit the
4235 shift insn before that insn, to remove the T_REG dependency.
4236 If the insn that sets the T_REG cannot be found, store the T_REG
4237 in a temporary reg and restore it after the shift. */
4238 if (sh_lshrsi_clobbers_t_reg_p (shift_count)
4239 && ! sh_dynamicalize_shift_p (shift_count))
4241 prev_set_t_insn = prev_nonnote_insn_bb (curr_insn);
4243 /* Skip the nott insn, which was probably inserted by the splitter
4244 of *rotcr_neg_t. Don't use one of the recog functions
4245 here during insn splitting, since that causes problems in later
4247 if (prev_set_t_insn != NULL_RTX)
4249 rtx pat = PATTERN (prev_set_t_insn);
4250 if (GET_CODE (pat) == SET
4251 && t_reg_operand (XEXP (pat, 0), SImode)
4252 && negt_reg_operand (XEXP (pat, 1), SImode))
4253 prev_set_t_insn = prev_nonnote_insn_bb (prev_set_t_insn);
4256 if (! (prev_set_t_insn != NULL_RTX
4257 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
4258 && ! reg_referenced_p (get_t_reg_rtx (),
4259 PATTERN (prev_set_t_insn))))
4261 prev_set_t_insn = NULL_RTX;
4262 tmp_t_reg = gen_reg_rtx (SImode);
4263 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
4267 rtx shift_result = gen_reg_rtx (SImode);
4268 rtx shift_insn = gen_lshrsi3 (shift_result, operands[1], shift_count);
4269 operands[1] = shift_result;
4271 /* Emit the shift insn before the insn that sets T_REG, if possible. */
4272 if (prev_set_t_insn != NULL_RTX)
4273 emit_insn_before (shift_insn, prev_set_t_insn);
4275 emit_insn (shift_insn);
4277 /* Restore T_REG if it has been saved before. */
4278 if (tmp_t_reg != NULL_RTX)
4279 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
4282 /* For the rotcr insn to work, operands[3] must be in T_REG.
4283 If it is not we can get it there by shifting it right one bit.
4284 In this case T_REG is not an input for this insn, thus we don't have to
4285 pay attention as of where to insert the shlr insn. */
4286 if (! t_reg_operand (operands[3], SImode))
4288 /* We don't care about the shifted result here, only the T_REG. */
4289 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
4290 operands[3] = get_t_reg_rtx ();
4293 emit_insn (gen_rotcr (operands[0], operands[1], operands[3]));
4297 ;; If combine tries the same as above but with swapped operands, split
4298 ;; it so that it will try the pattern above.
4300 [(set (match_operand:SI 0 "arith_reg_dest")
4301 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_or_t_reg_operand")
4303 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
4304 (match_operand:SI 3 "const_int_operand"))))]
4305 "TARGET_SH1 && can_create_pseudo_p ()"
4306 [(parallel [(set (match_dup 0)
4307 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
4308 (ashift:SI (match_dup 1) (const_int 31))))
4309 (clobber (reg:SI T_REG))])])
4311 ;; Basically the same as the rotcr pattern above, but for rotcl.
4312 ;; FIXME: Fold copy pasted split code for rotcr and rotcl.
4313 (define_insn_and_split "*rotcl"
4314 [(set (match_operand:SI 0 "arith_reg_dest")
4315 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4316 (match_operand:SI 2 "const_int_operand"))
4317 (and:SI (match_operand:SI 3 "arith_reg_or_t_reg_operand")
4319 (clobber (reg:SI T_REG))]
4322 "&& can_create_pseudo_p ()"
4325 gcc_assert (INTVAL (operands[2]) > 0);
4327 if (INTVAL (operands[2]) > 1)
4329 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
4330 rtx prev_set_t_insn = NULL_RTX;
4331 rtx tmp_t_reg = NULL_RTX;
4333 /* If we're going to emit a shift sequence that clobbers the T_REG,
4334 try to find the previous insn that sets the T_REG and emit the
4335 shift insn before that insn, to remove the T_REG dependency.
4336 If the insn that sets the T_REG cannot be found, store the T_REG
4337 in a temporary reg and restore it after the shift. */
4338 if (sh_ashlsi_clobbers_t_reg_p (shift_count)
4339 && ! sh_dynamicalize_shift_p (shift_count))
4341 prev_set_t_insn = prev_nonnote_insn_bb (curr_insn);
4343 /* Skip the nott insn, which was probably inserted by the splitter
4344 of *rotcl_neg_t. Don't use one of the recog functions
4345 here during insn splitting, since that causes problems in later
4347 if (prev_set_t_insn != NULL_RTX)
4349 rtx pat = PATTERN (prev_set_t_insn);
4350 if (GET_CODE (pat) == SET
4351 && t_reg_operand (XEXP (pat, 0), SImode)
4352 && negt_reg_operand (XEXP (pat, 1), SImode))
4353 prev_set_t_insn = prev_nonnote_insn_bb (prev_set_t_insn);
4356 if (! (prev_set_t_insn != NULL_RTX
4357 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
4358 && ! reg_referenced_p (get_t_reg_rtx (),
4359 PATTERN (prev_set_t_insn))))
4361 prev_set_t_insn = NULL_RTX;
4362 tmp_t_reg = gen_reg_rtx (SImode);
4363 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
4367 rtx shift_result = gen_reg_rtx (SImode);
4368 rtx shift_insn = gen_ashlsi3 (shift_result, operands[1], shift_count);
4369 operands[1] = shift_result;
4371 /* Emit the shift insn before the insn that sets T_REG, if possible. */
4372 if (prev_set_t_insn != NULL_RTX)
4373 emit_insn_before (shift_insn, prev_set_t_insn);
4375 emit_insn (shift_insn);
4377 /* Restore T_REG if it has been saved before. */
4378 if (tmp_t_reg != NULL_RTX)
4379 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
4382 /* For the rotcl insn to work, operands[3] must be in T_REG.
4383 If it is not we can get it there by shifting it right one bit.
4384 In this case T_REG is not an input for this insn, thus we don't have to
4385 pay attention as of where to insert the shlr insn. */
4386 if (! t_reg_operand (operands[3], SImode))
4388 /* We don't care about the shifted result here, only the T_REG. */
4389 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
4390 operands[3] = get_t_reg_rtx ();
4393 emit_insn (gen_rotcl (operands[0], operands[1], operands[3]));
4397 ;; rotcl combine pattern variations
4398 (define_insn_and_split "*rotcl"
4399 [(set (match_operand:SI 0 "arith_reg_dest")
4400 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4401 (match_operand:SI 2 "const_int_operand"))
4402 (match_operand:SI 3 "t_reg_operand")))
4403 (clobber (reg:SI T_REG))]
4406 "&& can_create_pseudo_p ()"
4407 [(parallel [(set (match_dup 0)
4408 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
4409 (and:SI (match_dup 3) (const_int 1))))
4410 (clobber (reg:SI T_REG))])])
4412 (define_insn_and_split "*rotcl"
4413 [(set (match_operand:SI 0 "arith_reg_dest")
4414 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_or_t_reg_operand")
4416 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
4417 (match_operand:SI 3 "const_int_operand"))))
4418 (clobber (reg:SI T_REG))]
4421 "&& can_create_pseudo_p ()"
4422 [(parallel [(set (match_dup 0)
4423 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
4424 (and:SI (match_dup 1) (const_int 1))))
4425 (clobber (reg:SI T_REG))])])
4427 (define_insn_and_split "*rotcl"
4428 [(set (match_operand:SI 0 "arith_reg_dest")
4429 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4430 (match_operand:SI 2 "const_int_operand"))
4431 (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
4433 (clobber (reg:SI T_REG))]
4436 "&& can_create_pseudo_p ()"
4437 [(parallel [(set (match_dup 0)
4438 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
4439 (and:SI (reg:SI T_REG) (const_int 1))))
4440 (clobber (reg:SI T_REG))])]
4442 /* We don't care about the result of the left shift, only the T_REG. */
4443 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
4446 (define_insn_and_split "*rotcl"
4447 [(set (match_operand:SI 0 "arith_reg_dest")
4448 (ior:SI (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
4450 (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4451 (match_operand:SI 2 "const_int_operand"))))
4452 (clobber (reg:SI T_REG))]
4455 "&& can_create_pseudo_p ()"
4456 [(parallel [(set (match_dup 0)
4457 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
4458 (and:SI (reg:SI T_REG) (const_int 1))))
4459 (clobber (reg:SI T_REG))])]
4461 /* We don't care about the result of the left shift, only the T_REG. */
4462 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
4465 ;; rotcr combine bridge pattern which will make combine try out more
4466 ;; complex patterns.
4467 (define_insn_and_split "*rotcr"
4468 [(set (match_operand:SI 0 "arith_reg_dest")
4469 (ashift:SI (match_operand:SI 1 "t_reg_operand") (const_int 31)))]
4473 [(set (match_dup 0) (match_dup 1))
4474 (parallel [(set (match_dup 0)
4475 (ior:SI (lshiftrt:SI (match_dup 0) (const_int 1))
4476 (ashift:SI (match_dup 1) (const_int 31))))
4478 (and:SI (match_dup 0) (const_int 1)))])])
4480 (define_insn_and_split "*rotcr"
4481 [(set (match_operand:SI 0 "arith_reg_dest")
4482 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
4483 (const_int -2147483648)) ;; 0xffffffff80000000
4484 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
4486 (clobber (reg:SI T_REG))]
4489 "&& can_create_pseudo_p ()"
4492 rtx tmp = gen_reg_rtx (SImode);
4493 emit_insn (gen_shll (tmp, operands[1]));
4494 emit_insn (gen_rotcr (operands[0], operands[2], get_t_reg_rtx ()));
4498 ;; rotcr combine patterns for rotating in the negated T_REG value.
4499 (define_insn_and_split "*rotcr_neg_t"
4500 [(set (match_operand:SI 0 "arith_reg_dest")
4501 (ior:SI (match_operand:SI 1 "negt_reg_shl31_operand")
4502 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
4503 (match_operand:SI 3 "const_int_operand"))))
4504 (clobber (reg:SI T_REG))]
4507 "&& can_create_pseudo_p ()"
4508 [(parallel [(set (match_dup 0)
4509 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
4510 (ashift:SI (reg:SI T_REG) (const_int 31))))
4511 (clobber (reg:SI T_REG))])]
4513 emit_insn (gen_nott (get_t_reg_rtx ()));
4516 (define_insn_and_split "*rotcr_neg_t"
4517 [(set (match_operand:SI 0 "arith_reg_dest")
4518 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
4519 (match_operand:SI 2 "const_int_operand"))
4520 (match_operand:SI 3 "negt_reg_shl31_operand")))
4521 (clobber (reg:SI T_REG))]
4524 "&& can_create_pseudo_p ()"
4525 [(parallel [(set (match_dup 0)
4526 (ior:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4527 (ashift:SI (reg:SI T_REG) (const_int 31))))
4528 (clobber (reg:SI T_REG))])]
4530 emit_insn (gen_nott (get_t_reg_rtx ()));
4533 ;; rotcl combine patterns for rotating in the negated T_REG value.
4534 ;; For some strange reason these have to be specified as splits which combine
4535 ;; will pick up. If they are specified as insn_and_split like the
4536 ;; *rotcr_neg_t patterns above, combine would recognize them successfully
4537 ;; but not emit them on non-SH2A targets.
4539 [(set (match_operand:SI 0 "arith_reg_dest")
4540 (ior:SI (match_operand:SI 1 "negt_reg_operand")
4541 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
4542 (match_operand:SI 3 "const_int_operand"))))]
4544 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
4545 (parallel [(set (match_dup 0)
4546 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
4547 (and:SI (reg:SI T_REG) (const_int 1))))
4548 (clobber (reg:SI T_REG))])])
4551 [(set (match_operand:SI 0 "arith_reg_dest")
4552 (ior:SI (ashift:SI (match_operand:SI 2 "arith_reg_operand")
4553 (match_operand:SI 3 "const_int_operand"))
4554 (match_operand:SI 1 "negt_reg_operand")))]
4556 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
4557 (parallel [(set (match_dup 0)
4558 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
4559 (and:SI (reg:SI T_REG) (const_int 1))))
4560 (clobber (reg:SI T_REG))])])
4562 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4563 ;; SImode shift left
4565 (define_expand "ashlsi3"
4566 [(set (match_operand:SI 0 "arith_reg_operand" "")
4567 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
4568 (match_operand:SI 2 "shift_count_operand" "")))]
4573 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
4575 operands[2] = GEN_INT (-INTVAL (operands[2]));
4576 emit_insn (gen_ashrsi3_media (operands[0], operands[1], operands[2]));
4579 emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2]));
4583 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
4584 operands[2] = force_reg (SImode, operands[2]);
4586 /* If the ashlsi3_* insn is going to clobber the T_REG it must be
4588 if (CONST_INT_P (operands[2])
4589 && sh_ashlsi_clobbers_t_reg_p (operands[2])
4590 && ! sh_dynamicalize_shift_p (operands[2]))
4592 emit_insn (gen_ashlsi3_n_clobbers_t (operands[0], operands[1],
4597 /* Expand a library call for the dynamic shift. */
4598 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
4600 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
4601 rtx funcaddr = gen_reg_rtx (Pmode);
4602 function_symbol (funcaddr, "__ashlsi3_r0", SFUNC_STATIC);
4603 emit_insn (gen_ashlsi3_d_call (operands[0], operands[2], funcaddr));
4609 (define_insn "ashlsi3_k"
4610 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4611 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
4612 (match_operand:SI 2 "p27_shift_count_operand" "M,P27")))]
4617 [(set_attr "type" "arith")])
4619 (define_insn_and_split "ashlsi3_d"
4620 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4621 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4622 (match_operand:SI 2 "shift_count_operand" "r")))]
4625 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
4626 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
4629 if (satisfies_constraint_P27 (operands[2]))
4631 emit_insn (gen_ashlsi3_k (operands[0], operands[1], operands[2]));
4634 else if (! satisfies_constraint_P27 (operands[2]))
4636 /* This must happen before reload, otherwise the constant will be moved
4637 into a register due to the "r" constraint, after which this split
4638 cannot be done anymore.
4639 Unfortunately the move insn will not always be eliminated.
4640 Also, here we must not create a shift sequence that clobbers the
4642 emit_move_insn (operands[0], operands[1]);
4643 gen_shifty_op (ASHIFT, operands);
4649 [(set_attr "type" "dyn_shift")])
4651 ;; If dynamic shifts are not available use a library function.
4652 ;; By specifying the pattern we reduce the number of call clobbered regs.
4653 ;; In order to make combine understand the truncation of the shift amount
4654 ;; operand we have to allow it to use pseudo regs for the shift operands.
4655 (define_insn "ashlsi3_d_call"
4656 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
4657 (ashift:SI (reg:SI R4_REG)
4658 (and:SI (match_operand:SI 1 "arith_reg_operand" "z")
4660 (use (match_operand:SI 2 "arith_reg_operand" "r"))
4661 (clobber (reg:SI T_REG))
4662 (clobber (reg:SI PR_REG))]
4663 "TARGET_SH1 && !TARGET_DYNSHIFT"
4665 [(set_attr "type" "sfunc")
4666 (set_attr "needs_delay_slot" "yes")])
4668 (define_insn_and_split "ashlsi3_n"
4669 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4670 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4671 (match_operand:SI 2 "not_p27_shift_count_operand" "")))]
4672 "TARGET_SH1 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
4674 "&& (reload_completed
4675 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
4678 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
4680 /* If this pattern was picked and dynamic shifts are supported, switch
4681 to dynamic shift pattern before reload. */
4682 operands[2] = force_reg (SImode, operands[2]);
4683 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
4686 gen_shifty_op (ASHIFT, operands);
4691 (define_insn_and_split "ashlsi3_n_clobbers_t"
4692 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4693 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4694 (match_operand:SI 2 "not_p27_shift_count_operand" "")))
4695 (clobber (reg:SI T_REG))]
4696 "TARGET_SH1 && sh_ashlsi_clobbers_t_reg_p (operands[2])"
4698 "&& (reload_completed || INTVAL (operands[2]) == 31
4699 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
4702 if (INTVAL (operands[2]) == 31)
4704 /* If the shift amount is 31 we split into a different sequence before
4705 reload so that it gets a chance to allocate R0 for the sequence.
4706 If it fails to do so (due to pressure on R0), it will take one insn
4707 more for the and. */
4708 emit_insn (gen_andsi3 (operands[0], operands[1], const1_rtx));
4709 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
4711 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
4713 /* If this pattern was picked and dynamic shifts are supported, switch
4714 to dynamic shift pattern before reload. */
4715 operands[2] = force_reg (SImode, operands[2]);
4716 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
4719 gen_shifty_op (ASHIFT, operands);
4725 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4726 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
4728 (lt:SI (match_dup 1) (const_int 0)))]
4731 [(set_attr "type" "arith")])
4733 (define_insn "*ashlsi_c_void"
4734 [(set (reg:SI T_REG)
4735 (lt:SI (match_operand:SI 0 "arith_reg_operand" "r") (const_int 0)))
4736 (clobber (match_scratch:SI 1 "=0"))]
4737 "TARGET_SH1 && cse_not_expected"
4739 [(set_attr "type" "arith")])
4742 [(set (match_operand:SI 0 "arith_reg_dest" "") (const_int 0))
4744 (gt:SI (match_dup 0) (match_operand:SI 1 "arith_reg_operand" "")))]
4746 && peep2_reg_dead_p (2, operands[0])
4747 && peep2_reg_dead_p (2, operands[1])"
4750 emit_insn (gen_shll (operands[1], operands[1]));
4754 (define_insn "ashlsi3_media"
4755 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4756 (ashift:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
4757 (match_operand:SI 2 "shift_count_operand" "r,n")))]
4762 [(set_attr "type" "arith_media")
4763 (set_attr "highpart" "ignore")])
4765 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4766 ;; HImode shift left
4768 (define_expand "ashlhi3"
4769 [(parallel [(set (match_operand:HI 0 "arith_reg_operand" "")
4770 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
4771 (match_operand:SI 2 "nonmemory_operand" "")))
4772 (clobber (reg:SI T_REG))])]
4775 if (!CONST_INT_P (operands[2]))
4777 /* It may be possible to call gen_ashlhi3 directly with more generic
4778 operands. Make sure operands[1] is a HImode register here. */
4779 if (!arith_reg_operand (operands[1], HImode))
4780 operands[1] = copy_to_mode_reg (HImode, operands[1]);
4783 (define_insn "ashlhi3_k"
4784 [(set (match_operand:HI 0 "arith_reg_dest" "=r,r")
4785 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
4786 (match_operand:HI 2 "const_int_operand" "M,P27")))]
4787 "TARGET_SH1 && satisfies_constraint_P27 (operands[2])"
4791 [(set_attr "type" "arith")])
4793 (define_insn_and_split "*ashlhi3_n"
4794 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4795 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
4796 (match_operand:HI 2 "const_int_operand" "n")))
4797 (clobber (reg:SI T_REG))]
4800 "&& reload_completed"
4801 [(use (reg:SI R0_REG))]
4803 gen_shifty_hi_op (ASHIFT, operands);
4807 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4808 ;; DImode shift left
4810 (define_expand "ashldi3"
4811 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
4812 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
4813 (match_operand:DI 2 "immediate_operand" "")))
4814 (clobber (reg:SI T_REG))])]
4819 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
4821 operands[2] = GEN_INT (-INTVAL (operands[2]));
4822 emit_insn (gen_ashrdi3_media (operands[0], operands[1], operands[2]));
4825 emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2]));
4828 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
4830 emit_insn (gen_ashldi3_k (operands[0], operands[1]));
4833 else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 32)
4835 emit_insn (gen_ashldi3_std (operands[0], operands[1], operands[2]));
4842 ;; Expander for DImode shift left with SImode operations.
4843 (define_expand "ashldi3_std"
4844 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4845 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
4846 (match_operand:DI 2 "const_int_operand" "n")))]
4847 "TARGET_SH1 && INTVAL (operands[2]) < 32"
4849 rtx low_src = gen_lowpart (SImode, operands[1]);
4850 rtx high_src = gen_highpart (SImode, operands[1]);
4851 rtx dst = gen_reg_rtx (DImode);
4852 rtx low_dst = gen_lowpart (SImode, dst);
4853 rtx high_dst = gen_highpart (SImode, dst);
4854 rtx tmp0 = gen_reg_rtx (SImode);
4855 rtx tmp1 = gen_reg_rtx (SImode);
4857 emit_insn (gen_lshrsi3 (tmp0, low_src, GEN_INT (32 - INTVAL (operands[2]))));
4858 emit_insn (gen_ashlsi3 (low_dst, low_src, operands[2]));
4859 emit_insn (gen_ashlsi3 (tmp1, high_src, operands[2]));
4860 emit_insn (gen_iorsi3 (high_dst, tmp0, tmp1));
4861 emit_move_insn (operands[0], dst);
4865 (define_insn_and_split "ashldi3_k"
4866 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4867 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
4869 (clobber (reg:SI T_REG))]
4872 "&& reload_completed"
4875 rtx high = gen_highpart (SImode, operands[0]);
4876 rtx low = gen_lowpart (SImode, operands[0]);
4877 emit_insn (gen_shll (low, low));
4878 emit_insn (gen_rotcl (high, high, get_t_reg_rtx ()));
4882 (define_insn "ashldi3_media"
4883 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
4884 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
4885 (match_operand:DI 2 "shift_count_operand" "r,n")))]
4890 [(set_attr "type" "arith_media")])
4892 (define_insn "*ashldisi3_media"
4893 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
4894 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
4895 (match_operand:DI 2 "const_int_operand" "n")))]
4896 "TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
4897 "shlli.l %1, %2, %0"
4898 [(set_attr "type" "arith_media")
4899 (set_attr "highpart" "ignore")])
4901 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4902 ;; SImode arithmetic shift right
4904 ;; We can't do HImode right shifts correctly unless we start out with an
4905 ;; explicit zero / sign extension; doing that would result in worse overall
4906 ;; code, so just let the machine independent code widen the mode.
4907 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
4909 (define_expand "ashrsi3"
4910 [(parallel [(set (match_operand:SI 0 "arith_reg_dest" "")
4911 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
4912 (match_operand:SI 2 "nonmemory_operand" "")))
4913 (clobber (reg:SI T_REG))])]
4918 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
4920 operands[2] = GEN_INT (-INTVAL (operands[2]));
4921 emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2]));
4924 emit_insn (gen_ashrsi3_media (operands[0], operands[1], operands[2]));
4927 if (expand_ashiftrt (operands))
4934 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4935 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4938 (and:SI (match_dup 1) (const_int 1)))]
4941 [(set_attr "type" "arith")])
4943 (define_insn "ashrsi3_k"
4944 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4945 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4946 (match_operand:SI 2 "const_int_operand" "M")))
4947 (clobber (reg:SI T_REG))]
4948 "TARGET_SH1 && INTVAL (operands[2]) == 1"
4950 [(set_attr "type" "arith")])
4952 (define_insn_and_split "ashrsi2_16"
4953 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4954 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
4959 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
4960 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
4962 operands[2] = gen_lowpart (HImode, operands[0]);
4965 (define_insn_and_split "ashrsi2_31"
4966 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4967 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4969 (clobber (reg:SI T_REG))]
4975 emit_insn (gen_shll (operands[0], operands[1]));
4976 emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ()));
4980 (define_insn "ashrsi3_d"
4981 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4982 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4983 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
4986 [(set_attr "type" "dyn_shift")])
4988 (define_insn "ashrsi3_n"
4989 [(set (reg:SI R4_REG)
4990 (ashiftrt:SI (reg:SI R4_REG)
4991 (match_operand:SI 0 "const_int_operand" "i")))
4992 (clobber (reg:SI T_REG))
4993 (clobber (reg:SI PR_REG))
4994 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
4997 [(set_attr "type" "sfunc")
4998 (set_attr "needs_delay_slot" "yes")])
5000 (define_insn "ashrsi3_media"
5001 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
5002 (ashiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
5003 (match_operand:SI 2 "shift_count_operand" "r,n")))]
5008 [(set_attr "type" "arith_media")
5009 (set_attr "highpart" "ignore")])
5011 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5012 ;; DImode arithmetic shift right
5014 (define_expand "ashrdi3"
5015 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
5016 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
5017 (match_operand:DI 2 "immediate_operand" "")))
5018 (clobber (reg:SI T_REG))])]
5023 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
5025 operands[2] = GEN_INT (-INTVAL (operands[2]));
5026 emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2]));
5029 emit_insn (gen_ashrdi3_media (operands[0], operands[1], operands[2]));
5032 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
5036 (define_insn_and_split "ashrdi3_k"
5037 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5038 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
5040 (clobber (reg:SI T_REG))]
5043 "&& reload_completed"
5046 rtx high = gen_highpart (SImode, operands[0]);
5047 rtx low = gen_lowpart (SImode, operands[0]);
5048 emit_insn (gen_shar (high, high));
5049 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
5053 (define_insn "ashrdi3_media"
5054 [(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
5055 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
5056 (match_operand:DI 2 "shift_count_operand" "r,n")))]
5058 && (arith_reg_dest (operands[0], DImode)
5059 || (CONST_INT_P (operands[2]) && INTVAL (operands[2]) >= 32))"
5063 [(set_attr "type" "arith_media")])
5065 (define_insn "*ashrdisi3_media"
5066 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
5067 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
5068 (match_operand:DI 2 "const_int_operand" "n")))]
5069 "TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
5070 "shari.l %1, %2, %0"
5071 [(set_attr "type" "arith_media")
5072 (set_attr "highpart" "ignore")])
5074 (define_insn "ashrdisi3_media_high"
5075 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5077 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
5078 (match_operand:DI 2 "const_int_operand" "n"))))]
5079 "TARGET_SHMEDIA && INTVAL (operands[2]) >= 32"
5081 [(set_attr "type" "arith_media")])
5083 (define_insn "ashrdisi3_media_opaque"
5084 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5085 (unspec:SI [(match_operand:DI 1 "arith_reg_operand" "r")
5086 (match_operand:DI 2 "const_int_operand" "n")]
5090 [(set_attr "type" "arith_media")])
5092 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5093 ;; SImode logical shift right
5095 (define_expand "lshrsi3"
5096 [(set (match_operand:SI 0 "arith_reg_dest" "")
5097 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
5098 (match_operand:SI 2 "shift_count_operand" "")))]
5103 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
5105 operands[2] = GEN_INT (-INTVAL (operands[2]));
5106 emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2]));
5109 emit_insn (gen_lshrsi3_media (operands[0], operands[1], operands[2]));
5113 /* If a dynamic shift is supposed to be used, expand the lshrsi3_d insn
5114 here, otherwise the pattern will never match due to the shift amount reg
5117 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
5119 rtx neg_count = force_reg (SImode,
5120 gen_int_mode (- INTVAL (operands[2]), SImode));
5121 emit_insn (gen_lshrsi3_d (operands[0], operands[1], neg_count));
5125 if (TARGET_DYNSHIFT && ! CONST_INT_P (operands[2]))
5127 rtx neg_count = gen_reg_rtx (SImode);
5128 emit_insn (gen_negsi2 (neg_count, operands[2]));
5129 emit_insn (gen_lshrsi3_d (operands[0], operands[1], neg_count));
5133 /* If the lshrsi3_* insn is going to clobber the T_REG it must be
5135 if (CONST_INT_P (operands[2])
5136 && sh_lshrsi_clobbers_t_reg_p (operands[2])
5137 && ! sh_dynamicalize_shift_p (operands[2]))
5139 emit_insn (gen_lshrsi3_n_clobbers_t (operands[0], operands[1],
5144 /* Expand a library call for the dynamic shift. */
5145 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
5147 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
5148 rtx funcaddr = gen_reg_rtx (Pmode);
5149 function_symbol (funcaddr, "__lshrsi3_r0", SFUNC_STATIC);
5150 emit_insn (gen_lshrsi3_d_call (operands[0], operands[2], funcaddr));
5155 (define_insn "lshrsi3_k"
5156 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5157 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5158 (match_operand:SI 2 "p27_rshift_count_operand" "P27")))]
5161 [(set_attr "type" "arith")])
5163 (define_insn_and_split "lshrsi3_d"
5164 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5165 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5166 (neg:SI (match_operand:SI 2 "shift_count_operand" "r"))))]
5169 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
5170 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
5173 if (satisfies_constraint_P27 (operands[2]))
5175 /* This will not be done for a shift amount of 1, because it would
5176 clobber the T_REG. */
5177 emit_insn (gen_lshrsi3_k (operands[0], operands[1], operands[2]));
5180 else if (! satisfies_constraint_P27 (operands[2]))
5182 /* This must happen before reload, otherwise the constant will be moved
5183 into a register due to the "r" constraint, after which this split
5184 cannot be done anymore.
5185 Unfortunately the move insn will not always be eliminated.
5186 Also, here we must not create a shift sequence that clobbers the
5188 emit_move_insn (operands[0], operands[1]);
5189 gen_shifty_op (LSHIFTRT, operands);
5195 [(set_attr "type" "dyn_shift")])
5197 ;; If dynamic shifts are not available use a library function.
5198 ;; By specifying the pattern we reduce the number of call clobbered regs.
5199 ;; In order to make combine understand the truncation of the shift amount
5200 ;; operand we have to allow it to use pseudo regs for the shift operands.
5201 (define_insn "lshrsi3_d_call"
5202 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
5203 (lshiftrt:SI (reg:SI R4_REG)
5204 (and:SI (match_operand:SI 1 "arith_reg_operand" "z")
5206 (use (match_operand:SI 2 "arith_reg_operand" "r"))
5207 (clobber (reg:SI T_REG))
5208 (clobber (reg:SI PR_REG))]
5209 "TARGET_SH1 && !TARGET_DYNSHIFT"
5211 [(set_attr "type" "sfunc")
5212 (set_attr "needs_delay_slot" "yes")])
5214 (define_insn_and_split "lshrsi3_n"
5215 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5216 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5217 (match_operand:SI 2 "not_p27_rshift_count_operand")))]
5218 "TARGET_SH1 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
5220 "&& (reload_completed
5221 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
5224 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
5226 /* If this pattern was picked and dynamic shifts are supported, switch
5227 to dynamic shift pattern before reload. */
5228 operands[2] = force_reg (SImode,
5229 gen_int_mode (- INTVAL (operands[2]), SImode));
5230 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
5233 gen_shifty_op (LSHIFTRT, operands);
5238 ;; The lshrsi3_n_clobbers_t pattern also works as a simplified version of
5239 ;; the shlr pattern.
5240 (define_insn_and_split "lshrsi3_n_clobbers_t"
5241 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5242 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5243 (match_operand:SI 2 "not_p27_rshift_count_operand")))
5244 (clobber (reg:SI T_REG))]
5245 "TARGET_SH1 && sh_lshrsi_clobbers_t_reg_p (operands[2])"
5247 "&& (reload_completed || INTVAL (operands[2]) == 31
5248 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
5251 if (INTVAL (operands[2]) == 31)
5253 emit_insn (gen_shll (operands[0], operands[1]));
5254 emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
5256 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
5258 /* If this pattern was picked and dynamic shifts are supported, switch
5259 to dynamic shift pattern before reload. */
5260 operands[2] = force_reg (SImode,
5261 gen_int_mode (- INTVAL (operands[2]), SImode));
5262 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
5265 gen_shifty_op (LSHIFTRT, operands);
5271 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5272 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5275 (and:SI (match_dup 1) (const_int 1)))]
5278 [(set_attr "type" "arith")])
5280 (define_insn "lshrsi3_media"
5281 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
5282 (lshiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
5283 (match_operand:SI 2 "shift_count_operand" "r,n")))]
5288 [(set_attr "type" "arith_media")
5289 (set_attr "highpart" "ignore")])
5291 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5292 ;; DImode logical shift right
5294 (define_expand "lshrdi3"
5295 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
5296 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
5297 (match_operand:DI 2 "immediate_operand" "")))
5298 (clobber (reg:SI T_REG))])]
5303 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
5305 operands[2] = GEN_INT (-INTVAL (operands[2]));
5306 emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2]));
5309 emit_insn (gen_lshrdi3_media (operands[0], operands[1], operands[2]));
5312 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
5316 (define_insn_and_split "lshrdi3_k"
5317 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5318 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
5320 (clobber (reg:SI T_REG))]
5323 "&& reload_completed"
5326 rtx high = gen_highpart (SImode, operands[0]);
5327 rtx low = gen_lowpart (SImode, operands[0]);
5328 emit_insn (gen_shlr (high, high));
5329 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
5333 (define_insn "lshrdi3_media"
5334 [(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
5335 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
5336 (match_operand:DI 2 "shift_count_operand" "r,n")))]
5338 && (arith_reg_dest (operands[0], DImode)
5339 || (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 32))"
5343 [(set_attr "type" "arith_media")])
5345 (define_insn "*lshrdisi3_media"
5346 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
5347 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
5348 (match_operand:DI 2 "const_int_operand" "n")))]
5349 "TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
5350 "shlri.l %1, %2, %0"
5351 [(set_attr "type" "arith_media")
5352 (set_attr "highpart" "ignore")])
5354 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5355 ;; Combined left/right shifts
5358 [(set (match_operand:SI 0 "register_operand" "")
5359 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
5360 (match_operand:SI 2 "const_int_operand" ""))
5361 (match_operand:SI 3 "const_int_operand" "")))]
5362 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
5363 [(use (reg:SI R0_REG))]
5365 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
5371 [(set (match_operand:SI 0 "register_operand" "")
5372 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
5373 (match_operand:SI 2 "const_int_operand" ""))
5374 (match_operand:SI 3 "const_int_operand" "")))
5375 (clobber (reg:SI T_REG))]
5376 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
5377 [(use (reg:SI R0_REG))]
5379 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
5385 [(set (match_operand:SI 0 "register_operand" "=r")
5386 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
5387 (match_operand:SI 2 "const_int_operand" "n"))
5388 (match_operand:SI 3 "const_int_operand" "n")))
5389 (clobber (reg:SI T_REG))]
5390 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 1"
5392 [(set (attr "length")
5393 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
5395 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
5397 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
5399 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
5401 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
5403 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
5405 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
5406 (const_string "16")]
5407 (const_string "18")))
5408 (set_attr "type" "arith")])
5411 [(set (match_operand:SI 0 "register_operand" "=z")
5412 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
5413 (match_operand:SI 2 "const_int_operand" "n"))
5414 (match_operand:SI 3 "const_int_operand" "n")))
5415 (clobber (reg:SI T_REG))]
5416 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 2"
5418 [(set (attr "length")
5419 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
5421 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
5423 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
5425 (const_string "10")))
5426 (set_attr "type" "arith")])
5428 ;; shift left / and combination with a scratch register: The combine pass
5429 ;; does not accept the individual instructions, even though they are
5430 ;; cheap. But it needs a precise description so that it is usable after
5432 (define_insn "and_shl_scratch"
5433 [(set (match_operand:SI 0 "register_operand" "=r,&r")
5437 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
5438 (match_operand:SI 2 "const_int_operand" "N,n"))
5439 (match_operand:SI 3 "" "0,r"))
5440 (match_operand:SI 4 "const_int_operand" "n,n"))
5441 (match_operand:SI 5 "const_int_operand" "n,n")))
5442 (clobber (reg:SI T_REG))]
5445 [(set (attr "length")
5446 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
5448 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
5450 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
5452 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
5453 (const_string "10")]
5454 (const_string "12")))
5455 (set_attr "type" "arith")])
5458 [(set (match_operand:SI 0 "register_operand" "")
5462 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
5463 (match_operand:SI 2 "const_int_operand" ""))
5464 (match_operand:SI 3 "register_operand" ""))
5465 (match_operand:SI 4 "const_int_operand" ""))
5466 (match_operand:SI 5 "const_int_operand" "")))
5467 (clobber (reg:SI T_REG))]
5469 [(use (reg:SI R0_REG))]
5471 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
5473 if (INTVAL (operands[2]))
5475 gen_shifty_op (LSHIFTRT, operands);
5477 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
5478 operands[2] = operands[4];
5479 gen_shifty_op (ASHIFT, operands);
5480 if (INTVAL (operands[5]))
5482 operands[2] = operands[5];
5483 gen_shifty_op (LSHIFTRT, operands);
5488 ;; signed left/right shift combination.
5490 [(set (match_operand:SI 0 "register_operand" "")
5492 (ashift:SI (match_operand:SI 1 "register_operand" "")
5493 (match_operand:SI 2 "const_int_operand" ""))
5494 (match_operand:SI 3 "const_int_operand" "")
5496 (clobber (reg:SI T_REG))]
5498 [(use (reg:SI R0_REG))]
5500 if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1]))
5505 (define_insn "shl_sext_ext"
5506 [(set (match_operand:SI 0 "register_operand" "=r")
5508 (ashift:SI (match_operand:SI 1 "register_operand" "0")
5509 (match_operand:SI 2 "const_int_operand" "n"))
5510 (match_operand:SI 3 "const_int_operand" "n")
5512 (clobber (reg:SI T_REG))]
5513 "TARGET_SH1 && (unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
5515 [(set (attr "length")
5516 (cond [(match_test "shl_sext_length (insn)")
5518 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
5520 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
5522 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
5524 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
5526 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
5528 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
5530 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
5531 (const_string "16")]
5532 (const_string "18")))
5533 (set_attr "type" "arith")])
5535 (define_insn "shl_sext_sub"
5536 [(set (match_operand:SI 0 "register_operand" "=z")
5538 (ashift:SI (match_operand:SI 1 "register_operand" "0")
5539 (match_operand:SI 2 "const_int_operand" "n"))
5540 (match_operand:SI 3 "const_int_operand" "n")
5542 (clobber (reg:SI T_REG))]
5543 "TARGET_SH1 && (shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
5545 [(set (attr "length")
5546 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
5548 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
5550 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
5552 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
5553 (const_string "12")]
5554 (const_string "14")))
5555 (set_attr "type" "arith")])
5557 ;; The xtrct_left and xtrct_right patterns are used in expansions of DImode
5558 ;; shifts by 16, and allow the xtrct instruction to be generated from C
5560 (define_insn "xtrct_left"
5561 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5562 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
5564 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
5568 [(set_attr "type" "arith")])
5570 (define_insn "xtrct_right"
5571 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5572 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5574 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
5578 [(set_attr "type" "arith")])
5580 ;; -------------------------------------------------------------------------
5582 ;; -------------------------------------------------------------------------
5585 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5586 (neg:SI (plus:SI (reg:SI T_REG)
5587 (match_operand:SI 1 "arith_reg_operand" "r"))))
5589 (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
5593 [(set_attr "type" "arith")])
5595 ;; A simplified version of the negc insn, where the exact value of the
5596 ;; T bit doesn't matter. This is easier for combine to pick up.
5597 ;; Notice that '0 - x - 1' is the same as '~x', thus we don't specify
5598 ;; extra patterns for this case.
5599 (define_insn "*negc"
5600 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5601 (minus:SI (neg:SI (match_operand:SI 1 "arith_reg_operand" "r"))
5602 (match_operand:SI 2 "t_reg_operand" "")))
5603 (clobber (reg:SI T_REG))]
5606 [(set_attr "type" "arith")])
5608 (define_insn "*negdi_media"
5609 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5610 (neg:DI (match_operand:DI 1 "arith_reg_operand" "r")))]
5613 [(set_attr "type" "arith_media")])
5615 ;; Don't split into individual negc insns immediately so that neg:DI (abs:DI)
5617 (define_expand "negdi2"
5618 [(parallel [(set (match_operand:DI 0 "arith_reg_dest")
5619 (neg:DI (match_operand:DI 1 "arith_reg_operand")))
5620 (clobber (reg:SI T_REG))])]
5623 (define_insn_and_split "*negdi2"
5624 [(set (match_operand:DI 0 "arith_reg_dest")
5625 (neg:DI (match_operand:DI 1 "arith_reg_operand")))
5626 (clobber (reg:SI T_REG))]
5629 "&& can_create_pseudo_p ()"
5632 emit_insn (gen_clrt ());
5633 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
5634 gen_lowpart (SImode, operands[1])));
5635 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
5636 gen_highpart (SImode, operands[1])));
5640 (define_insn "negsi2"
5641 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5642 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
5645 [(set_attr "type" "arith")])
5647 (define_insn_and_split "one_cmplsi2"
5648 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5649 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
5652 "&& can_create_pseudo_p ()"
5653 [(set (reg:SI T_REG) (ge:SI (match_dup 1) (const_int 0)))
5654 (set (match_dup 0) (reg:SI T_REG))]
5657 If the result of 'unsigned int <= 0x7FFFFFFF' ends up as the following
5660 (set (reg0) (not:SI (reg0) (reg1)))
5661 (parallel [(set (reg2) (lshiftrt:SI (reg0) (const_int 31)))
5662 (clobber (reg:SI T_REG))])
5664 ... match and combine the sequence manually in the split pass after the
5665 combine pass. Notice that combine does try the target pattern of this
5666 split, but if the pattern is added it interferes with other patterns, in
5667 particular with the div0s comparisons.
5668 This could also be done with a peephole but doing it here before register
5669 allocation can save one temporary.
5670 When we're here, the not:SI pattern obviously has been matched already
5671 and we only have to see whether the following insn is the left shift. */
5673 rtx i = next_nonnote_insn_bb (curr_insn);
5674 if (i == NULL_RTX || !NONJUMP_INSN_P (i))
5677 rtx p = PATTERN (i);
5678 if (GET_CODE (p) != PARALLEL || XVECLEN (p, 0) != 2)
5681 rtx p0 = XVECEXP (p, 0, 0);
5682 rtx p1 = XVECEXP (p, 0, 1);
5684 if (/* (set (reg2) (lshiftrt:SI (reg0) (const_int 31))) */
5685 GET_CODE (p0) == SET
5686 && GET_CODE (XEXP (p0, 1)) == LSHIFTRT
5687 && REG_P (XEXP (XEXP (p0, 1), 0))
5688 && REGNO (XEXP (XEXP (p0, 1), 0)) == REGNO (operands[0])
5689 && CONST_INT_P (XEXP (XEXP (p0, 1), 1))
5690 && INTVAL (XEXP (XEXP (p0, 1), 1)) == 31
5692 /* (clobber (reg:SI T_REG)) */
5693 && GET_CODE (p1) == CLOBBER && REG_P (XEXP (p1, 0))
5694 && REGNO (XEXP (p1, 0)) == T_REG)
5696 operands[0] = XEXP (p0, 0);
5697 set_insn_deleted (i);
5702 [(set_attr "type" "arith")])
5704 (define_expand "one_cmpldi2"
5705 [(set (match_operand:DI 0 "arith_reg_dest" "")
5706 (xor:DI (match_operand:DI 1 "arith_reg_operand" "")
5708 "TARGET_SHMEDIA" "")
5710 (define_expand "abs<mode>2"
5711 [(parallel [(set (match_operand:SIDI 0 "arith_reg_dest")
5712 (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand")))
5713 (clobber (reg:SI T_REG))])]
5716 (define_insn_and_split "*abs<mode>2"
5717 [(set (match_operand:SIDI 0 "arith_reg_dest")
5718 (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand")))
5719 (clobber (reg:SI T_REG))]
5722 "&& can_create_pseudo_p ()"
5725 if (<MODE>mode == SImode)
5726 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
5729 rtx high_src = gen_highpart (SImode, operands[1]);
5730 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
5733 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
5738 (define_insn_and_split "*negabs<mode>2"
5739 [(set (match_operand:SIDI 0 "arith_reg_dest")
5740 (neg:SIDI (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand"))))
5741 (clobber (reg:SI T_REG))]
5744 "&& can_create_pseudo_p ()"
5747 if (<MODE>mode == SImode)
5748 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
5751 rtx high_src = gen_highpart (SImode, operands[1]);
5752 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
5755 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
5760 ;; The SH4 202 can do zero-offset branches without pipeline stalls.
5761 ;; This can be used as some kind of conditional execution, which is useful
5763 ;; Actually the instruction scheduling should decide whether to use a
5764 ;; zero-offset branch or not for any generic case involving a single
5765 ;; instruction on SH4 202.
5766 (define_insn_and_split "negsi_cond"
5767 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
5769 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand" "M,N"))
5770 (match_operand:SI 1 "arith_reg_operand" "0,0")
5771 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r,r"))))]
5772 "TARGET_SH1 && TARGET_ZDCBRANCH"
5774 static const char* alt[] =
5784 return alt[which_alternative];
5786 "TARGET_SH1 && ! TARGET_ZDCBRANCH"
5789 rtx skip_neg_label = gen_label_rtx ();
5791 emit_move_insn (operands[0], operands[1]);
5793 emit_jump_insn (INTVAL (operands[3])
5794 ? gen_branch_true (skip_neg_label)
5795 : gen_branch_false (skip_neg_label));
5797 emit_label_after (skip_neg_label,
5798 emit_insn (gen_negsi2 (operands[0], operands[1])));
5801 [(set_attr "type" "arith") ;; poor approximation
5802 (set_attr "length" "4")])
5804 (define_insn_and_split "negdi_cond"
5805 [(set (match_operand:DI 0 "arith_reg_dest")
5807 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand"))
5808 (match_operand:DI 1 "arith_reg_operand")
5809 (neg:DI (match_operand:DI 2 "arith_reg_operand"))))
5810 (clobber (reg:SI T_REG))]
5813 "&& can_create_pseudo_p ()"
5816 rtx skip_neg_label = gen_label_rtx ();
5818 emit_move_insn (operands[0], operands[1]);
5820 emit_jump_insn (INTVAL (operands[3])
5821 ? gen_branch_true (skip_neg_label)
5822 : gen_branch_false (skip_neg_label));
5824 if (!INTVAL (operands[3]))
5825 emit_insn (gen_clrt ());
5827 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
5828 gen_lowpart (SImode, operands[1])));
5829 emit_label_after (skip_neg_label,
5830 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
5831 gen_highpart (SImode, operands[1]))));
5835 (define_expand "bswapsi2"
5836 [(set (match_operand:SI 0 "arith_reg_dest" "")
5837 (bswap:SI (match_operand:SI 1 "arith_reg_operand" "")))]
5840 if (! can_create_pseudo_p ())
5844 rtx tmp0 = gen_reg_rtx (SImode);
5845 rtx tmp1 = gen_reg_rtx (SImode);
5847 emit_insn (gen_swapbsi2 (tmp0, operands[1]));
5848 emit_insn (gen_rotlsi3_16 (tmp1, tmp0));
5849 emit_insn (gen_swapbsi2 (operands[0], tmp1));
5854 (define_insn "swapbsi2"
5855 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5856 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
5857 (const_int 4294901760))
5858 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
5860 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
5861 (const_int 255)))))]
5864 [(set_attr "type" "arith")])
5866 ;; The *swapbisi2_and_shl8 pattern helps the combine pass simplifying
5867 ;; partial byte swap expressions such as...
5868 ;; ((x & 0xFF) << 8) | ((x >> 8) & 0xFF).
5869 ;; ...which are currently not handled by the tree optimizers.
5870 ;; The combine pass will not initially try to combine the full expression,
5871 ;; but only some sub-expressions. In such a case the *swapbisi2_and_shl8
5872 ;; pattern acts as an intermediate pattern that will eventually lead combine
5873 ;; to the swapbsi2 pattern above.
5874 ;; As a side effect this also improves code that does (x & 0xFF) << 8
5875 ;; or (x << 8) & 0xFF00.
5876 (define_insn_and_split "*swapbisi2_and_shl8"
5877 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5878 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
5881 (match_operand:SI 2 "arith_reg_operand" "r")))]
5882 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
5884 "&& can_create_pseudo_p ()"
5887 rtx tmp0 = gen_reg_rtx (SImode);
5888 rtx tmp1 = gen_reg_rtx (SImode);
5890 emit_insn (gen_zero_extendqisi2 (tmp0, gen_lowpart (QImode, operands[1])));
5891 emit_insn (gen_swapbsi2 (tmp1, tmp0));
5892 emit_insn (gen_iorsi3 (operands[0], tmp1, operands[2]));
5896 ;; The *swapbhisi2 pattern is, like the *swapbisi2_and_shl8 pattern, another
5897 ;; intermediate pattern that will help the combine pass arriving at swapbsi2.
5898 (define_insn_and_split "*swapbhisi2"
5899 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5900 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
5903 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))))]
5904 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
5906 "&& can_create_pseudo_p ()"
5909 rtx tmp = gen_reg_rtx (SImode);
5911 emit_insn (gen_zero_extendhisi2 (tmp, gen_lowpart (HImode, operands[1])));
5912 emit_insn (gen_swapbsi2 (operands[0], tmp));
5916 ;; In some cases the swapbsi2 pattern might leave a sequence such as...
5920 ;; which can be simplified to...
5923 [(set (match_operand:SI 0 "arith_reg_dest" "")
5924 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
5925 (const_int 4294901760))
5926 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
5928 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
5930 (set (match_operand:SI 2 "arith_reg_dest" "")
5932 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
5934 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
5935 (const_int 4294901760))
5936 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
5938 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
5939 (const_int 255)))))])
5941 ;; -------------------------------------------------------------------------
5942 ;; Zero extension instructions
5943 ;; -------------------------------------------------------------------------
5945 (define_insn "zero_extendsidi2"
5946 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5947 (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "r")))]
5949 "addz.l %1, r63, %0"
5950 [(set_attr "type" "arith_media")
5951 (set_attr "highpart" "extend")])
5953 (define_insn "zero_extendhidi2"
5954 [(set (match_operand:DI 0 "register_operand" "=r,r")
5955 (zero_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
5960 [(set_attr "type" "*,load_media")
5961 (set (attr "highpart")
5962 (cond [(match_test "sh_contains_memref_p (insn)")
5963 (const_string "user")]
5964 (const_string "ignore")))])
5967 [(set (match_operand:DI 0 "register_operand" "")
5968 (zero_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
5969 "TARGET_SHMEDIA && reload_completed"
5970 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
5971 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 48)))]
5973 if (GET_CODE (operands[1]) == TRUNCATE)
5974 operands[1] = XEXP (operands[1], 0);
5977 ;; ??? when a truncated input to a zero_extend is reloaded, reload will
5978 ;; reload the entire truncate expression.
5979 (define_insn_and_split "*loaddi_trunc"
5980 [(set (match_operand 0 "any_register_operand" "=r")
5981 (truncate (match_operand:DI 1 "memory_operand" "m")))]
5982 "TARGET_SHMEDIA && reload_completed"
5984 "TARGET_SHMEDIA && reload_completed"
5985 [(set (match_dup 0) (match_dup 1))]
5987 operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0]));
5990 (define_insn "zero_extendqidi2"
5991 [(set (match_operand:DI 0 "register_operand" "=r,r")
5992 (zero_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
5997 [(set_attr "type" "arith_media,load_media")
5998 (set (attr "highpart")
5999 (cond [(match_test "sh_contains_memref_p (insn)")
6000 (const_string "user")]
6001 (const_string "ignore")))])
6003 (define_expand "zero_extend<mode>si2"
6004 [(set (match_operand:SI 0 "arith_reg_dest")
6005 (zero_extend:SI (match_operand:QIHI 1 "zero_extend_operand")))])
6007 (define_insn_and_split "*zero_extend<mode>si2_compact"
6008 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6009 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
6012 "&& can_create_pseudo_p ()"
6013 [(set (match_dup 0) (match_dup 2))]
6015 /* Sometimes combine fails to combine a T bit or negated T bit store to a
6016 reg with a following zero extension. In the split pass after combine,
6017 try to figure out how the extended reg was set. If it originated from
6018 the T bit we can replace the zero extension with a reg move, which will
6019 be eliminated. Notice that this also helps the *cbranch_t splitter when
6020 it tries to post-combine tests and conditional branches, as it does not
6021 check for zero extensions. */
6022 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
6023 if (operands[2] == NULL_RTX)
6026 [(set_attr "type" "arith")])
6028 (define_insn "*zero_extendhisi2_media"
6029 [(set (match_operand:SI 0 "register_operand" "=r,r")
6030 (zero_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
6035 [(set_attr "type" "arith_media,load_media")
6036 (set (attr "highpart")
6037 (cond [(match_test "sh_contains_memref_p (insn)")
6038 (const_string "user")]
6039 (const_string "ignore")))])
6042 [(set (match_operand:SI 0 "register_operand" "")
6043 (zero_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
6044 "TARGET_SHMEDIA && reload_completed"
6045 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
6046 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))]
6048 rtx op1 = operands[1];
6050 if (GET_CODE (op1) == TRUNCATE)
6051 op1 = XEXP (op1, 0);
6053 = simplify_gen_subreg (SImode, op1, GET_MODE (op1),
6054 subreg_lowpart_offset (SImode, GET_MODE (op1)));
6057 (define_insn "*zero_extendqisi2_media"
6058 [(set (match_operand:SI 0 "register_operand" "=r,r")
6059 (zero_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
6064 [(set_attr "type" "arith_media,load_media")
6065 (set (attr "highpart")
6066 (cond [(match_test "sh_contains_memref_p (insn)")
6067 (const_string "user")]
6068 (const_string "ignore")))])
6070 (define_insn "zero_extendqihi2"
6071 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
6072 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
6075 [(set_attr "type" "arith")])
6077 ;; SH2A supports two zero extending load instructions: movu.b and movu.w.
6078 ;; They could also be used for simple memory addresses like @Rn by setting
6079 ;; the displacement value to zero. However, doing so too early results in
6080 ;; missed opportunities for other optimizations such as post-inc or index
6081 ;; addressing loads.
6082 ;; Although the 'zero_extend_movu_operand' predicate does not allow simple
6083 ;; register addresses (an address without a displacement, index, post-inc),
6084 ;; zero-displacement addresses might be generated during reload, wich are
6085 ;; simplified to simple register addresses in turn. Thus, we have to
6086 ;; provide the Sdd and Sra alternatives in the patterns.
6087 (define_insn "*zero_extend<mode>si2_disp_mem"
6088 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
6090 (match_operand:QIHI 1 "zero_extend_movu_operand" "Sdd,Sra")))]
6094 movu.<bw> @(0,%t1),%0"
6095 [(set_attr "type" "load")
6096 (set_attr "length" "4")])
6098 ;; Convert the zero extending loads in sequences such as:
6099 ;; movu.b @(1,r5),r0 movu.w @(2,r5),r0
6100 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
6102 ;; back to sign extending loads like:
6103 ;; mov.b @(1,r5),r0 mov.w @(2,r5),r0
6104 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
6106 ;; if the extension type is irrelevant. The sign extending mov.{b|w} insn
6107 ;; is only 2 bytes in size if the displacement is {K04|K05}.
6108 ;; If the displacement is greater it doesn't matter, so we convert anyways.
6110 [(set (match_operand:SI 0 "arith_reg_dest" "")
6111 (zero_extend:SI (match_operand 1 "displacement_mem_operand" "")))
6112 (set (match_operand 2 "nonimmediate_operand" "")
6113 (match_operand 3 "arith_reg_operand" ""))]
6115 && REGNO (operands[0]) == REGNO (operands[3])
6116 && peep2_reg_dead_p (2, operands[0])
6117 && GET_MODE_SIZE (GET_MODE (operands[2]))
6118 <= GET_MODE_SIZE (GET_MODE (operands[1]))"
6119 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
6120 (set (match_dup 2) (match_dup 3))])
6122 ;; Fold sequences such as
6126 ;; movu.b @(0,r3),r7
6127 ;; This does not reduce the code size but the number of instructions is
6128 ;; halved, which results in faster code.
6130 [(set (match_operand:SI 0 "arith_reg_dest" "")
6131 (sign_extend:SI (match_operand 1 "simple_mem_operand" "")))
6132 (set (match_operand:SI 2 "arith_reg_dest" "")
6133 (zero_extend:SI (match_operand 3 "arith_reg_operand" "")))]
6135 && GET_MODE (operands[1]) == GET_MODE (operands[3])
6136 && (GET_MODE (operands[1]) == QImode || GET_MODE (operands[1]) == HImode)
6137 && REGNO (operands[0]) == REGNO (operands[3])
6138 && (REGNO (operands[2]) == REGNO (operands[0])
6139 || peep2_reg_dead_p (2, operands[0]))"
6140 [(set (match_dup 2) (zero_extend:SI (match_dup 4)))]
6143 = replace_equiv_address (operands[1],
6144 gen_rtx_PLUS (SImode, XEXP (operands[1], 0),
6148 ;; -------------------------------------------------------------------------
6149 ;; Sign extension instructions
6150 ;; -------------------------------------------------------------------------
6152 ;; ??? This should be a define expand.
6153 ;; ??? Or perhaps it should be dropped?
6155 ;; convert_move generates good code for SH[1-4].
6156 (define_insn "extendsidi2"
6157 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6158 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,?f")))]
6164 [(set_attr "type" "arith_media,load_media,fpconv_media")
6165 (set (attr "highpart")
6166 (cond [(match_test "sh_contains_memref_p (insn)")
6167 (const_string "user")]
6168 (const_string "extend")))])
6170 (define_insn "extendhidi2"
6171 [(set (match_operand:DI 0 "register_operand" "=r,r")
6172 (sign_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
6177 [(set_attr "type" "*,load_media")
6178 (set (attr "highpart")
6179 (cond [(match_test "sh_contains_memref_p (insn)")
6180 (const_string "user")]
6181 (const_string "ignore")))])
6184 [(set (match_operand:DI 0 "register_operand" "")
6185 (sign_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
6186 "TARGET_SHMEDIA && reload_completed"
6187 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
6188 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 48)))]
6190 if (GET_CODE (operands[1]) == TRUNCATE)
6191 operands[1] = XEXP (operands[1], 0);
6194 (define_insn "extendqidi2"
6195 [(set (match_operand:DI 0 "register_operand" "=r,r")
6196 (sign_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
6201 [(set_attr "type" "*,load_media")
6202 (set (attr "highpart")
6203 (cond [(match_test "sh_contains_memref_p (insn)")
6204 (const_string "user")]
6205 (const_string "ignore")))])
6208 [(set (match_operand:DI 0 "register_operand" "")
6209 (sign_extend:DI (match_operand:QI 1 "extend_reg_operand" "")))]
6210 "TARGET_SHMEDIA && reload_completed"
6211 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 56)))
6212 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))]
6214 if (GET_CODE (operands[1]) == TRUNCATE)
6215 operands[1] = XEXP (operands[1], 0);
6218 (define_expand "extend<mode>si2"
6219 [(set (match_operand:SI 0 "arith_reg_dest")
6220 (sign_extend:SI (match_operand:QIHI 1 "general_extend_operand")))])
6222 (define_insn "*extendhisi2_media"
6223 [(set (match_operand:SI 0 "register_operand" "=r,r")
6224 (sign_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
6229 [(set_attr "type" "arith_media,load_media")
6230 (set (attr "highpart")
6231 (cond [(match_test "sh_contains_memref_p (insn)")
6232 (const_string "user")]
6233 (const_string "ignore")))])
6236 [(set (match_operand:SI 0 "register_operand" "")
6237 (sign_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
6238 "TARGET_SHMEDIA && reload_completed"
6239 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
6240 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))]
6242 rtx op1 = operands[1];
6243 if (GET_CODE (op1) == TRUNCATE)
6244 op1 = XEXP (op1, 0);
6246 = simplify_gen_subreg (SImode, op1, GET_MODE (op1),
6247 subreg_lowpart_offset (SImode, GET_MODE (op1)));
6250 (define_insn_and_split "*extend<mode>si2_compact_reg"
6251 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6252 (sign_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
6255 "&& can_create_pseudo_p ()"
6256 [(set (match_dup 0) (match_dup 2))]
6258 /* Sometimes combine fails to combine a T bit or negated T bit store to a
6259 reg with a following sign extension. In the split pass after combine,
6260 try to figure the extended reg was set. If it originated from the T
6261 bit we can replace the sign extension with a reg move, which will be
6263 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
6264 if (operands[2] == NULL_RTX)
6267 [(set_attr "type" "arith")])
6269 ;; FIXME: Fold non-SH2A and SH2A alternatives with "enabled" attribute.
6271 (define_insn "*extend<mode>si2_compact_mem_disp"
6272 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
6276 (match_operand:SI 1 "arith_reg_operand" "%r,r")
6277 (match_operand:SI 2 "const_int_operand" "<disp04>,N")))))]
6278 "TARGET_SH1 && ! TARGET_SH2A
6279 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
6281 mov.<bw> @(%O2,%1),%0
6283 [(set_attr "type" "load")])
6285 (define_insn "*extend<mode>si2_compact_mem_disp"
6286 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r,r")
6290 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
6291 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>")))))]
6292 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
6294 mov.<bw> @(%O2,%1),%0
6296 mov.<bw> @(%O2,%1),%0"
6297 [(set_attr "type" "load")
6298 (set_attr "length" "2,2,4")])
6300 ;; The *_snd patterns will take care of other QImode/HImode addressing
6301 ;; modes than displacement addressing. They must be defined _after_ the
6302 ;; displacement addressing patterns. Otherwise the displacement addressing
6303 ;; patterns will not be picked.
6304 (define_insn "*extend<mode>si2_compact_snd"
6305 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6307 (match_operand:QIHI 1 "movsrc_no_disp_mem_operand" "Snd")))]
6310 [(set_attr "type" "load")])
6312 (define_insn "*extendqisi2_media"
6313 [(set (match_operand:SI 0 "register_operand" "=r,r")
6314 (sign_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
6319 [(set_attr "type" "arith_media,load_media")
6320 (set (attr "highpart")
6321 (cond [(match_test "sh_contains_memref_p (insn)")
6322 (const_string "user")]
6323 (const_string "ignore")))])
6326 [(set (match_operand:SI 0 "register_operand" "")
6327 (sign_extend:SI (match_operand:QI 1 "extend_reg_operand" "")))]
6328 "TARGET_SHMEDIA && reload_completed"
6329 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24)))
6330 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))]
6332 rtx op1 = operands[1];
6333 if (GET_CODE (op1) == TRUNCATE)
6334 op1 = XEXP (op1, 0);
6336 = simplify_gen_subreg (SImode, op1, GET_MODE (op1),
6337 subreg_lowpart_offset (SImode, GET_MODE (op1)));
6340 (define_expand "extendqihi2"
6341 [(set (match_operand:HI 0 "arith_reg_dest")
6342 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand")))]
6345 (define_insn "*extendqihi2_compact_reg"
6346 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
6347 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
6350 [(set_attr "type" "arith")])
6352 ;; It would seem useful to combine the truncXi patterns into the movXi
6353 ;; patterns, but unary operators are ignored when matching constraints,
6354 ;; so we need separate patterns.
6355 (define_insn "truncdisi2"
6356 [(set (match_operand:SI 0 "general_movdst_operand" "=r,m,m,f,r,f")
6357 (truncate:SI (match_operand:DI 1 "register_operand" "r,r,f,r,f,f")))]
6366 [(set_attr "type" "arith_media,store_media,fstore_media,fload_media,
6367 fpconv_media,fmove_media")
6368 (set (attr "highpart")
6369 (cond [(match_test "sh_contains_memref_p (insn)")
6370 (const_string "user")]
6371 (const_string "extend")))])
6373 (define_insn "truncdihi2"
6374 [(set (match_operand:HI 0 "general_movdst_operand" "=?r,m")
6375 (truncate:HI (match_operand:DI 1 "register_operand" "r,r")))]
6378 static const char* alt[] =
6380 "shlli %1,48,%0" "\n"
6385 return alt[which_alternative];
6387 [(set_attr "type" "arith_media,store_media")
6388 (set_attr "length" "8,4")
6389 (set (attr "highpart")
6390 (cond [(match_test "sh_contains_memref_p (insn)")
6391 (const_string "user")]
6392 (const_string "extend")))])
6394 ; N.B. This should agree with LOAD_EXTEND_OP and movqi.
6395 ; Because we use zero extension, we can't provide signed QImode compares
6396 ; using a simple compare or conditional branch insn.
6397 (define_insn "truncdiqi2"
6398 [(set (match_operand:QI 0 "general_movdst_operand" "=r,m")
6399 (truncate:QI (match_operand:DI 1 "register_operand" "r,r")))]
6404 [(set_attr "type" "arith_media,store")
6405 (set (attr "highpart")
6406 (cond [(match_test "sh_contains_memref_p (insn)")
6407 (const_string "user")]
6408 (const_string "extend")))])
6410 ;; -------------------------------------------------------------------------
6411 ;; Move instructions
6412 ;; -------------------------------------------------------------------------
6414 ;; define push and pop so it is easy for sh.c
6415 ;; We can't use push and pop on SHcompact because the stack must always
6416 ;; be 8-byte aligned.
6417 (define_expand "push"
6418 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
6419 (match_operand:SI 0 "register_operand" "r,l,x"))]
6420 "TARGET_SH1 && ! TARGET_SH5"
6423 (define_expand "pop"
6424 [(set (match_operand:SI 0 "register_operand" "=r,l,x")
6425 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
6426 "TARGET_SH1 && ! TARGET_SH5"
6429 (define_expand "push_e"
6430 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG)))
6431 (match_operand:SF 0 "" ""))
6432 (use (reg:SI FPSCR_MODES_REG))
6433 (clobber (scratch:SI))])]
6434 "TARGET_SH1 && ! TARGET_SH5"
6437 (define_insn "push_fpul"
6438 [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
6439 "TARGET_SH2E && ! TARGET_SH5"
6441 [(set_attr "type" "fstore")
6442 (set_attr "late_fp_use" "yes")
6443 (set_attr "hit_stack" "yes")])
6445 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
6447 (define_expand "push_4"
6448 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG)))
6449 (match_operand:DF 0 "" ""))
6450 (use (reg:SI FPSCR_MODES_REG))
6451 (clobber (scratch:SI))])]
6452 "TARGET_SH1 && ! TARGET_SH5"
6455 (define_expand "pop_e"
6456 [(parallel [(set (match_operand:SF 0 "" "")
6457 (mem:SF (post_inc:SI (reg:SI SP_REG))))
6458 (use (reg:SI FPSCR_MODES_REG))
6459 (clobber (scratch:SI))])]
6460 "TARGET_SH1 && ! TARGET_SH5"
6463 (define_insn "pop_fpul"
6464 [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
6465 "TARGET_SH2E && ! TARGET_SH5"
6467 [(set_attr "type" "load")
6468 (set_attr "hit_stack" "yes")])
6470 (define_expand "pop_4"
6471 [(parallel [(set (match_operand:DF 0 "" "")
6472 (mem:DF (post_inc:SI (reg:SI SP_REG))))
6473 (use (reg:SI FPSCR_MODES_REG))
6474 (clobber (scratch:SI))])]
6475 "TARGET_SH1 && ! TARGET_SH5"
6478 (define_expand "push_fpscr"
6485 gen_frame_mem (SImode, gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)))),
6486 REG_INC, stack_pointer_rtx);
6490 (define_expand "pop_fpscr"
6497 gen_frame_mem (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)))),
6498 REG_INC, stack_pointer_rtx);
6502 ;; The clrt and sett patterns can happen as the result of optimization and
6504 ;; Comparisons might get simplified to a move of zero or 1 into the T reg.
6505 ;; In this case they might not disappear completely, because the T reg is
6506 ;; a fixed hard reg.
6507 ;; When DImode operations that use the T reg as carry/borrow are split into
6508 ;; individual SImode operations, the T reg is usually cleared before the
6509 ;; first SImode insn.
6511 [(set (reg:SI T_REG) (const_int 0))]
6514 [(set_attr "type" "mt_group")])
6517 [(set (reg:SI T_REG) (const_int 1))]
6520 [(set_attr "type" "mt_group")])
6522 ;; Use the combine pass to transform sequences such as
6526 ;; mov.l @(r0,r4),r0
6532 ;; See also PR 39423.
6533 ;; Notice that these patterns have a T_REG clobber, because the shift
6534 ;; sequence that will be split out might clobber the T_REG. Ideally, the
6535 ;; clobber would be added conditionally, depending on the result of
6536 ;; sh_ashlsi_clobbers_t_reg_p. When splitting out the shifts we must go
6537 ;; through the ashlsi3 expander in order to get the right shift insn --
6538 ;; a T_REG clobbering or non-clobbering shift sequence or dynamic shift.
6539 ;; FIXME: Combine never tries this kind of patterns for DImode.
6540 (define_insn_and_split "*movsi_index_disp_load"
6541 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6542 (match_operand:SI 1 "mem_index_disp_operand" "m"))
6543 (clobber (reg:SI T_REG))]
6546 "&& can_create_pseudo_p ()"
6547 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
6548 (set (match_dup 0) (match_dup 7))]
6550 rtx mem = operands[1];
6551 rtx plus0_rtx = XEXP (mem, 0);
6552 rtx plus1_rtx = XEXP (plus0_rtx, 0);
6553 rtx mult_rtx = XEXP (plus1_rtx, 0);
6555 operands[1] = XEXP (mult_rtx, 0);
6556 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
6557 operands[3] = XEXP (plus1_rtx, 1);
6558 operands[4] = XEXP (plus0_rtx, 1);
6559 operands[5] = gen_reg_rtx (SImode);
6560 operands[6] = gen_reg_rtx (SImode);
6562 replace_equiv_address (mem,
6563 gen_rtx_PLUS (SImode, operands[6], operands[4]));
6565 emit_insn (gen_ashlsi3 (operands[5], operands[1], operands[2]));
6568 (define_insn_and_split "*movhi_index_disp_load"
6569 [(set (match_operand:SI 0 "arith_reg_dest")
6570 (SZ_EXTEND:SI (match_operand:HI 1 "mem_index_disp_operand")))
6571 (clobber (reg:SI T_REG))]
6574 "&& can_create_pseudo_p ()"
6577 rtx mem = operands[1];
6578 rtx plus0_rtx = XEXP (mem, 0);
6579 rtx plus1_rtx = XEXP (plus0_rtx, 0);
6580 rtx mult_rtx = XEXP (plus1_rtx, 0);
6582 rtx op_1 = XEXP (mult_rtx, 0);
6583 rtx op_2 = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
6584 rtx op_3 = XEXP (plus1_rtx, 1);
6585 rtx op_4 = XEXP (plus0_rtx, 1);
6586 rtx op_5 = gen_reg_rtx (SImode);
6587 rtx op_6 = gen_reg_rtx (SImode);
6588 rtx op_7 = replace_equiv_address (mem, gen_rtx_PLUS (SImode, op_6, op_4));
6590 emit_insn (gen_ashlsi3 (op_5, op_1, op_2));
6591 emit_insn (gen_addsi3 (op_6, op_5, op_3));
6593 if (<CODE> == SIGN_EXTEND)
6595 emit_insn (gen_extendhisi2 (operands[0], op_7));
6598 else if (<CODE> == ZERO_EXTEND)
6600 /* On SH2A the movu.w insn can be used for zero extending loads. */
6602 emit_insn (gen_zero_extendhisi2 (operands[0], op_7));
6605 emit_insn (gen_extendhisi2 (operands[0], op_7));
6606 emit_insn (gen_zero_extendhisi2 (operands[0],
6607 gen_lowpart (HImode, operands[0])));
6615 (define_insn_and_split "*mov<mode>_index_disp_store"
6616 [(set (match_operand:HISI 0 "mem_index_disp_operand" "=m")
6617 (match_operand:HISI 1 "arith_reg_operand" "r"))
6618 (clobber (reg:SI T_REG))]
6621 "&& can_create_pseudo_p ()"
6622 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
6623 (set (match_dup 7) (match_dup 1))]
6625 rtx mem = operands[0];
6626 rtx plus0_rtx = XEXP (mem, 0);
6627 rtx plus1_rtx = XEXP (plus0_rtx, 0);
6628 rtx mult_rtx = XEXP (plus1_rtx, 0);
6630 operands[0] = XEXP (mult_rtx, 0);
6631 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
6632 operands[3] = XEXP (plus1_rtx, 1);
6633 operands[4] = XEXP (plus0_rtx, 1);
6634 operands[5] = gen_reg_rtx (SImode);
6635 operands[6] = gen_reg_rtx (SImode);
6637 replace_equiv_address (mem,
6638 gen_rtx_PLUS (SImode, operands[6], operands[4]));
6640 emit_insn (gen_ashlsi3 (operands[5], operands[0], operands[2]));
6643 ;; t/r must come after r/r, lest reload will try to reload stuff like
6644 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
6645 ;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
6646 (define_insn "movsi_i"
6647 [(set (match_operand:SI 0 "general_movdst_operand"
6648 "=r,r,r,r,r,r,m,<,<,x,l,x,l,r")
6649 (match_operand:SI 1 "general_movsrc_operand"
6650 "Q,r,I08,mr,x,l,r,x,l,r,r,>,>,i"))]
6654 && (register_operand (operands[0], SImode)
6655 || register_operand (operands[1], SImode))"
6671 [(set_attr "type" "pcload_si,move,movi8,load_si,mac_gp,prget,store,mac_mem,
6672 pstore,gp_mac,prset,mem_mac,pload,pcload_si")
6673 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
6675 ;; t/r must come after r/r, lest reload will try to reload stuff like
6676 ;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
6677 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
6678 ;; will require a reload.
6679 ;; ??? We can't include f/f because we need the proper FPSCR setting when
6680 ;; TARGET_FMOVD is in effect, and mode switching is done before reload.
6681 (define_insn "movsi_ie"
6682 [(set (match_operand:SI 0 "general_movdst_operand"
6683 "=r,r,r,r,r,r,r,r,mr,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
6684 (match_operand:SI 1 "general_movsrc_operand"
6685 "Q,r,I08,I20,I28,mr,x,l,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
6686 "(TARGET_SH2E || TARGET_SH2A)
6687 && ((register_operand (operands[0], SImode)
6688 && !fpscr_operand (operands[0], SImode))
6689 || (register_operand (operands[1], SImode)
6690 && !fpscr_operand (operands[1], SImode)))"
6715 ! move optimized away"
6716 [(set_attr "type" "pcload_si,move,movi8,move,move,load_si,mac_gp,prget,store,
6717 mac_mem,pstore,gp_mac,prset,mem_mac,pload,load,fstore,
6718 pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
6719 (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
6720 (set_attr_alternative "length"
6727 (match_test "TARGET_SH2A")
6728 (const_int 4) (const_int 2))
6732 (match_test "TARGET_SH2A")
6733 (const_int 4) (const_int 2))
6750 (define_insn "movsi_i_lowpart"
6751 [(set (strict_low_part
6752 (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,m,r"))
6753 (match_operand:SI 1 "general_movsrc_operand" "Q,r,I08,mr,x,l,r,i"))]
6755 && (register_operand (operands[0], SImode)
6756 || register_operand (operands[1], SImode))"
6766 [(set_attr "type" "pcload,move,arith,load,mac_gp,prget,store,pcload")])
6768 (define_insn_and_split "load_ra"
6769 [(set (match_operand:SI 0 "general_movdst_operand" "")
6770 (unspec:SI [(match_operand:SI 1 "register_operand" "")] UNSPEC_RA))]
6773 "&& ! currently_expanding_to_rtl"
6774 [(set (match_dup 0) (match_dup 1))]
6776 if (TARGET_SHCOMPACT && crtl->saves_all_registers)
6777 operands[1] = gen_frame_mem (SImode, return_address_pointer_rtx);
6780 ;; The '?'s in the following constraints may not reflect the time taken
6781 ;; to perform the move. They are there to discourage the use of floating-
6782 ;; point registers for storing integer values.
6783 (define_insn "*movsi_media"
6784 [(set (match_operand:SI 0 "general_movdst_operand"
6785 "=r,r,r,r,m,f?,m,f?,r,f?,*b,r,b")
6786 (match_operand:SI 1 "general_movsrc_operand"
6787 "r,I16Css,nCpg,m,rZ,m,f?,rZ,f?,f?,r,*b,Csy"))]
6789 && (register_operand (operands[0], SImode)
6790 || sh_register_operand (operands[1], SImode)
6791 || GET_CODE (operands[1]) == TRUNCATE)"
6806 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
6807 fload_media,fstore_media,fload_media,fpconv_media,
6808 fmove_media,ptabs_media,gettr_media,pt_media")
6809 (set_attr "length" "4,4,8,4,4,4,4,4,4,4,4,4,12")
6810 (set (attr "highpart")
6811 (cond [(match_test "sh_contains_memref_p (insn)")
6812 (const_string "user")]
6813 (const_string "ignore")))])
6815 (define_insn "*movsi_media_nofpu"
6816 [(set (match_operand:SI 0 "general_movdst_operand"
6817 "=r,r,r,r,m,*b,r,*b")
6818 (match_operand:SI 1 "general_movsrc_operand"
6819 "r,I16Css,nCpg,m,rZ,r,*b,Csy"))]
6821 && (register_operand (operands[0], SImode)
6822 || sh_register_operand (operands[1], SImode)
6823 || GET_CODE (operands[1]) == TRUNCATE)"
6833 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
6834 ptabs_media,gettr_media,pt_media")
6835 (set_attr "length" "4,4,8,4,4,4,4,12")
6836 (set (attr "highpart")
6837 (cond [(match_test "sh_contains_memref_p (insn)")
6838 (const_string "user")]
6839 (const_string "ignore")))])
6841 (define_expand "movsi_const"
6842 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
6843 (const:SI (unspec:SI [(match_operand:DI 1 "immediate_operand" "s")
6844 (const_int 16)] UNSPEC_EXTRACT_S16)))
6846 (ior:SI (ashift:SI (match_dup 0) (const_int 16))
6847 (const:SI (unspec:SI [(match_dup 1)
6848 (const_int 0)] UNSPEC_EXTRACT_U16))))]
6849 "TARGET_SHMEDIA && reload_completed
6850 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
6852 if (GET_CODE (operands[1]) == LABEL_REF
6853 && GET_CODE (XEXP (operands[1], 0)) == CODE_LABEL)
6854 LABEL_NUSES (XEXP (operands[1], 0)) += 2;
6855 else if (GOTOFF_P (operands[1]))
6857 rtx unspec = XEXP (operands[1], 0);
6859 if (! UNSPEC_GOTOFF_P (unspec))
6861 unspec = XEXP (unspec, 0);
6862 if (! UNSPEC_GOTOFF_P (unspec))
6865 if (GET_CODE (XVECEXP (unspec , 0, 0)) == LABEL_REF
6866 && (GET_CODE (XEXP (XVECEXP (unspec, 0, 0), 0)) == CODE_LABEL))
6867 LABEL_NUSES (XEXP (XVECEXP (unspec, 0, 0), 0)) += 2;
6871 (define_expand "movsi_const_16bit"
6872 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
6873 (const:SI (unspec:SI [(match_operand:DI 1 "immediate_operand" "s")
6874 (const_int 0)] UNSPEC_EXTRACT_S16)))]
6875 "TARGET_SHMEDIA && flag_pic && reload_completed
6876 && GET_CODE (operands[1]) == SYMBOL_REF"
6880 [(set (match_operand:SI 0 "arith_reg_dest" "")
6881 (match_operand:SI 1 "immediate_operand" ""))]
6882 "TARGET_SHMEDIA && reload_completed
6883 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
6886 rtx insn = emit_insn (gen_movsi_const (operands[0], operands[1]));
6888 set_unique_reg_note (insn, REG_EQUAL, copy_rtx (operands[1]));
6894 [(set (match_operand:SI 0 "register_operand" "")
6895 (match_operand:SI 1 "immediate_operand" ""))]
6896 "TARGET_SHMEDIA && reload_completed
6897 && ((CONST_INT_P (operands[1])
6898 && ! satisfies_constraint_I16 (operands[1]))
6899 || GET_CODE (operands[1]) == CONST_DOUBLE)"
6900 [(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
6902 (define_expand "movsi"
6903 [(set (match_operand:SI 0 "general_movdst_operand" "")
6904 (match_operand:SI 1 "general_movsrc_operand" ""))]
6907 prepare_move_operands (operands, SImode);
6910 (define_expand "ic_invalidate_line"
6911 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand" "+r")
6912 (match_dup 1)] UNSPEC_ICACHE)
6913 (clobber (scratch:SI))])]
6914 "TARGET_HARD_SH4 || TARGET_SH5"
6918 emit_insn (gen_ic_invalidate_line_media (operands[0]));
6921 else if (TARGET_SHCOMPACT)
6923 operands[1] = function_symbol (NULL, "__ic_invalidate", SFUNC_STATIC);
6924 operands[1] = force_reg (Pmode, operands[1]);
6925 emit_insn (gen_ic_invalidate_line_compact (operands[0], operands[1]));
6928 else if (TARGET_SH4A || TARGET_SH4_300)
6930 emit_insn (gen_ic_invalidate_line_sh4a (operands[0]));
6933 operands[0] = force_reg (Pmode, operands[0]);
6934 operands[1] = force_reg (Pmode, GEN_INT (trunc_int_for_mode (0xf0000008,
6938 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
6939 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
6940 ;; the requirement *1*00 for associative address writes. The alignment of
6941 ;; %0 implies that its least significant bit is cleared,
6942 ;; thus we clear the V bit of a matching entry if there is one.
6943 (define_insn "ic_invalidate_line_i"
6944 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
6945 (match_operand:SI 1 "register_operand" "r")]
6947 (clobber (match_scratch:SI 2 "=&r"))]
6950 return "ocbwb @%0" "\n"
6951 " extu.w %0,%2" "\n"
6955 [(set_attr "length" "8")
6956 (set_attr "type" "cwb")])
6958 (define_insn "ic_invalidate_line_sh4a"
6959 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
6961 "TARGET_SH4A || TARGET_SH4_300"
6963 return "ocbwb @%0" "\n"
6967 [(set_attr "length" "16") ;; FIXME: Why 16 and not 6? Looks like typo.
6968 (set_attr "type" "cwb")])
6970 ;; ??? could make arg 0 an offsettable memory operand to allow to save
6971 ;; an add in the code that calculates the address.
6972 (define_insn "ic_invalidate_line_media"
6973 [(unspec_volatile [(match_operand 0 "any_register_operand" "r")]
6977 return "ocbwb %0,0" "\n"
6982 [(set_attr "length" "16")
6983 (set_attr "type" "invalidate_line_media")])
6985 (define_insn "ic_invalidate_line_compact"
6986 [(unspec_volatile [(match_operand:SI 0 "register_operand" "z")
6987 (match_operand:SI 1 "register_operand" "r")]
6989 (clobber (reg:SI PR_REG))]
6992 [(set_attr "type" "sfunc")
6993 (set_attr "needs_delay_slot" "yes")])
6995 (define_expand "initialize_trampoline"
6996 [(match_operand:SI 0 "" "")
6997 (match_operand:SI 1 "" "")
6998 (match_operand:SI 2 "" "")]
7003 tramp = force_reg (Pmode, operands[0]);
7004 sfun = force_reg (Pmode, function_symbol (NULL, "__init_trampoline",
7006 emit_move_insn (gen_rtx_REG (SImode, R2_REG), operands[1]);
7007 emit_move_insn (gen_rtx_REG (SImode, R3_REG), operands[2]);
7009 emit_insn (gen_initialize_trampoline_compact (tramp, sfun));
7013 (define_insn "initialize_trampoline_compact"
7014 [(unspec_volatile [(match_operand:SI 0 "register_operand" "z")
7015 (match_operand:SI 1 "register_operand" "r")
7016 (reg:SI R2_REG) (reg:SI R3_REG)]
7019 (clobber (reg:SI PR_REG))]
7022 [(set_attr "type" "sfunc")
7023 (set_attr "needs_delay_slot" "yes")])
7025 (define_expand "mov<mode>"
7026 [(set (match_operand:QIHI 0 "general_movdst_operand")
7027 (match_operand:QIHI 1 "general_movsrc_operand"))]
7030 if (can_create_pseudo_p () && CONST_INT_P (operands[1])
7031 && REG_P (operands[0]) && REGNO (operands[0]) != R0_REG)
7033 rtx reg = gen_reg_rtx(SImode);
7034 emit_move_insn (reg, operands[1]);
7035 operands[1] = gen_lowpart (<MODE>mode, reg);
7038 prepare_move_operands (operands, <MODE>mode);
7041 ;; Specifying the displacement addressing load / store patterns separately
7042 ;; before the generic movqi / movhi pattern allows controlling the order
7043 ;; in which load / store insns are selected in a more fine grained way.
7044 ;; FIXME: The non-SH2A and SH2A variants should be combined by adding
7045 ;; "enabled" attribute as it is done in other targets.
7046 (define_insn "*mov<mode>_store_mem_disp04"
7048 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r,r")
7049 (match_operand:SI 1 "const_int_operand" "<disp04>,N")))
7050 (match_operand:QIHI 2 "arith_reg_operand" "z,r"))]
7051 "TARGET_SH1 && sh_legitimate_index_p (<MODE>mode, operands[1], false, true)"
7053 mov.<bw> %2,@(%O1,%0)
7055 [(set_attr "type" "store")])
7057 (define_insn "*mov<mode>_store_mem_disp12"
7059 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r")
7060 (match_operand:SI 1 "const_int_operand" "<disp12>")))
7061 (match_operand:QIHI 2 "arith_reg_operand" "r"))]
7062 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[1], true, true)"
7063 "mov.<bw> %2,@(%O1,%0)"
7064 [(set_attr "type" "store")
7065 (set_attr "length" "4")])
7067 (define_insn "*mov<mode>_load_mem_disp04"
7068 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r")
7070 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r")
7071 (match_operand:SI 2 "const_int_operand" "<disp04>,N"))))]
7072 "TARGET_SH1 && ! TARGET_SH2A
7073 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
7075 mov.<bw> @(%O2,%1),%0
7077 [(set_attr "type" "load")])
7079 (define_insn "*mov<mode>_load_mem_disp12"
7080 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r,r")
7083 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
7084 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>"))))]
7085 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
7087 mov.<bw> @(%O2,%1),%0
7089 mov.<bw> @(%O2,%1),%0"
7090 [(set_attr "type" "load")
7091 (set_attr "length" "2,2,4")])
7093 ;; The order of the constraint alternatives is important here.
7094 ;; Q/r has to come first, otherwise PC relative loads might wrongly get
7095 ;; placed into delay slots. Since there is no QImode PC relative load, the
7096 ;; Q constraint and general_movsrc_operand will reject it for QImode.
7097 ;; The Snd alternatives should come before Sdd in order to avoid a preference
7098 ;; of using r0 als the register operand for addressing modes other than
7099 ;; displacement addressing.
7100 ;; The Sdd alternatives allow only r0 as register operand, even though on
7101 ;; SH2A any register could be allowed by switching to a 32 bit insn.
7102 ;; Generally sticking to the r0 is preferrable, since it generates smaller
7103 ;; code. Obvious r0 reloads can then be eliminated with a peephole on SH2A.
7104 (define_insn "*mov<mode>"
7105 [(set (match_operand:QIHI 0 "general_movdst_operand"
7106 "=r,r,r,Snd,r, Sdd,z, r,l")
7107 (match_operand:QIHI 1 "general_movsrc_operand"
7108 "Q,r,i,r, Snd,z, Sdd,l,r"))]
7110 && (arith_reg_operand (operands[0], <MODE>mode)
7111 || arith_reg_operand (operands[1], <MODE>mode))"
7122 [(set_attr "type" "pcload,move,movi8,store,load,store,load,prget,prset")
7123 (set (attr "length")
7124 (cond [(and (match_operand 0 "displacement_mem_operand")
7125 (not (match_operand 0 "short_displacement_mem_operand")))
7127 (and (match_operand 1 "displacement_mem_operand")
7128 (not (match_operand 1 "short_displacement_mem_operand")))
7132 (define_insn "*movqi_media"
7133 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,r,m")
7134 (match_operand:QI 1 "general_movsrc_operand" "r,I16Css,m,rZ"))]
7136 && (arith_reg_operand (operands[0], QImode)
7137 || extend_reg_or_0_operand (operands[1], QImode))"
7143 [(set_attr "type" "arith_media,arith_media,load_media,store_media")
7144 (set (attr "highpart")
7145 (cond [(match_test "sh_contains_memref_p (insn)")
7146 (const_string "user")]
7147 (const_string "ignore")))])
7149 (define_expand "reload_inqi"
7150 [(set (match_operand:SI 2 "" "=&r")
7151 (match_operand:QI 1 "inqhi_operand" ""))
7152 (set (match_operand:QI 0 "arith_reg_operand" "=r")
7153 (truncate:QI (match_dup 3)))]
7156 rtx inner = XEXP (operands[1], 0);
7157 int regno = REGNO (inner);
7159 regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1;
7160 operands[1] = gen_rtx_REG (SImode, regno);
7161 operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
7164 (define_insn "*movhi_media"
7165 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m")
7166 (match_operand:HI 1 "general_movsrc_operand" "r,I16Css,n,m,rZ"))]
7168 && (arith_reg_operand (operands[0], HImode)
7169 || arith_reg_or_0_operand (operands[1], HImode))"
7176 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
7177 (set (attr "highpart")
7178 (cond [(match_test "sh_contains_memref_p (insn)")
7179 (const_string "user")]
7180 (const_string "ignore")))])
7183 [(set (match_operand:HI 0 "register_operand" "")
7184 (match_operand:HI 1 "immediate_operand" ""))]
7185 "TARGET_SHMEDIA && reload_completed
7186 && ! satisfies_constraint_I16 (operands[1])"
7187 [(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
7189 (define_expand "reload_inhi"
7190 [(set (match_operand:SI 2 "" "=&r")
7191 (match_operand:HI 1 "inqhi_operand" ""))
7192 (set (match_operand:HI 0 "arith_reg_operand" "=r")
7193 (truncate:HI (match_dup 3)))]
7196 rtx inner = XEXP (operands[1], 0);
7197 int regno = REGNO (inner);
7199 regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1;
7200 operands[1] = gen_rtx_REG (SImode, regno);
7201 operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
7204 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
7205 ;; compiled with -m2 -ml -O3 -funroll-loops
7206 (define_insn "*movdi_i"
7207 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
7208 (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I08,i,x,r"))]
7210 && (arith_reg_operand (operands[0], DImode)
7211 || arith_reg_operand (operands[1], DImode))"
7213 return output_movedouble (insn, operands, DImode);
7215 [(set_attr "length" "4")
7216 (set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
7218 ;; If the output is a register and the input is memory or a register, we have
7219 ;; to be careful and see which word needs to be loaded first.
7221 [(set (match_operand:DI 0 "general_movdst_operand" "")
7222 (match_operand:DI 1 "general_movsrc_operand" ""))]
7223 "TARGET_SH1 && reload_completed"
7224 [(set (match_dup 2) (match_dup 3))
7225 (set (match_dup 4) (match_dup 5))]
7229 if ((MEM_P (operands[0])
7230 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
7231 || (MEM_P (operands[1])
7232 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
7235 switch (GET_CODE (operands[0]))
7238 regno = REGNO (operands[0]);
7241 regno = subreg_regno (operands[0]);
7251 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
7253 operands[2] = operand_subword (operands[0], 0, 0, DImode);
7254 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7255 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7256 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7260 operands[2] = operand_subword (operands[0], 1, 0, DImode);
7261 operands[3] = operand_subword (operands[1], 1, 0, DImode);
7262 operands[4] = operand_subword (operands[0], 0, 0, DImode);
7263 operands[5] = operand_subword (operands[1], 0, 0, DImode);
7266 if (operands[2] == 0 || operands[3] == 0
7267 || operands[4] == 0 || operands[5] == 0)
7271 ;; The '?'s in the following constraints may not reflect the time taken
7272 ;; to perform the move. They are there to discourage the use of floating-
7273 ;; point registers for storing integer values.
7274 (define_insn "*movdi_media"
7275 [(set (match_operand:DI 0 "general_movdst_operand"
7276 "=r,r,r,rl,m,f?,m,f?,r,f?,*b,r,*b")
7277 (match_operand:DI 1 "general_movsrc_operand"
7278 "r,I16Css,nCpgF,m,rlZ,m,f?,rZ,f?,f?,r,*b,Csy"))]
7280 && (register_operand (operands[0], DImode)
7281 || sh_register_operand (operands[1], DImode))"
7296 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
7297 fload_media,fstore_media,fload_media,dfpconv_media,
7298 fmove_media,ptabs_media,gettr_media,pt_media")
7299 (set_attr "length" "4,4,16,4,4,4,4,4,4,4,4,4,*")])
7301 (define_insn "*movdi_media_nofpu"
7302 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,rl,m,*b,r,*b");
7303 (match_operand:DI 1 "general_movsrc_operand" "r,I16Css,nCpgF,m,rlZ,r,*b,Csy"))]
7305 && (register_operand (operands[0], DImode)
7306 || sh_register_operand (operands[1], DImode))"
7316 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
7317 ptabs_media,gettr_media,pt_media")
7318 (set_attr "length" "4,4,16,4,4,4,4,*")])
7320 (define_insn "*movdi_media_I16"
7321 [(set (match_operand:DI 0 "ext_dest_operand" "=r")
7322 (match_operand:DI 1 "const_int_operand" "I16"))]
7323 "TARGET_SHMEDIA && reload_completed"
7325 [(set_attr "type" "arith_media")
7326 (set_attr "length" "4")])
7329 [(set (match_operand:DI 0 "arith_reg_dest" "")
7330 (match_operand:DI 1 "immediate_operand" ""))]
7331 "TARGET_SHMEDIA && reload_completed
7332 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
7333 [(set (match_dup 0) (match_dup 1))]
7337 if (TARGET_SHMEDIA64)
7338 insn = emit_insn (gen_movdi_const (operands[0], operands[1]));
7340 insn = emit_insn (gen_movdi_const_32bit (operands[0], operands[1]));
7342 set_unique_reg_note (insn, REG_EQUAL, copy_rtx (operands[1]));
7347 (define_expand "movdi_const"
7348 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7349 (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
7350 (const_int 48)] UNSPEC_EXTRACT_S16)))
7352 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7353 (const:DI (unspec:DI [(match_dup 1)
7354 (const_int 32)] UNSPEC_EXTRACT_U16))))
7356 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7357 (const:DI (unspec:DI [(match_dup 1)
7358 (const_int 16)] UNSPEC_EXTRACT_U16))))
7360 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7361 (const:DI (unspec:DI [(match_dup 1)
7362 (const_int 0)] UNSPEC_EXTRACT_U16))))]
7363 "TARGET_SHMEDIA64 && reload_completed
7364 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
7366 sh_mark_label (operands[1], 4);
7369 (define_expand "movdi_const_32bit"
7370 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7371 (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
7372 (const_int 16)] UNSPEC_EXTRACT_S16)))
7374 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7375 (const:DI (unspec:DI [(match_dup 1)
7376 (const_int 0)] UNSPEC_EXTRACT_U16))))]
7377 "TARGET_SHMEDIA32 && reload_completed
7378 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
7380 sh_mark_label (operands[1], 2);
7383 (define_expand "movdi_const_16bit"
7384 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7385 (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
7386 (const_int 0)] UNSPEC_EXTRACT_S16)))]
7387 "TARGET_SHMEDIA && flag_pic && reload_completed
7388 && GET_CODE (operands[1]) == SYMBOL_REF"
7392 [(set (match_operand:DI 0 "ext_dest_operand" "")
7393 (match_operand:DI 1 "immediate_operand" ""))]
7394 "TARGET_SHMEDIA && reload_completed
7395 && CONST_INT_P (operands[1])
7396 && ! satisfies_constraint_I16 (operands[1])"
7397 [(set (match_dup 0) (match_dup 2))
7400 unsigned HOST_WIDE_INT val = INTVAL (operands[1]);
7401 unsigned HOST_WIDE_INT low = val;
7402 unsigned HOST_WIDE_INT high = val;
7403 unsigned HOST_WIDE_INT sign;
7404 unsigned HOST_WIDE_INT val2 = val ^ (val-1);
7406 /* Zero-extend the 16 least-significant bits. */
7409 /* Arithmetic shift right the word by 16 bits. */
7411 if (GET_CODE (operands[0]) == SUBREG
7412 && GET_MODE (SUBREG_REG (operands[0])) == SImode)
7421 sign <<= (HOST_BITS_PER_WIDE_INT - 16 - 1);
7427 /* If we can't generate the constant with a two-insn movi / shori
7428 sequence, try some other strategies. */
7429 if (! CONST_OK_FOR_I16 (high))
7431 /* Try constant load / left shift. We know VAL != 0. */
7432 val2 = val ^ (val-1);
7435 int trailing_zeroes = exact_log2 ((val2 >> 16) + 1) + 15;
7437 if (CONST_OK_FOR_I16 (val >> trailing_zeroes)
7438 || (! CONST_OK_FOR_I16 (high >> 16)
7439 && CONST_OK_FOR_I16 (val >> (trailing_zeroes + 16))))
7441 val2 = (HOST_WIDE_INT) val >> trailing_zeroes;
7442 operands[1] = gen_ashldi3_media (operands[0], operands[0],
7443 GEN_INT (trailing_zeroes));
7447 /* Try constant load / right shift. */
7448 val2 = (val >> 15) + 1;
7449 if (val2 == (val2 & -val2))
7451 int shift = 49 - exact_log2 (val2);
7453 val2 = trunc_int_for_mode (val << shift, DImode);
7454 if (CONST_OK_FOR_I16 (val2))
7456 operands[1] = gen_lshrdi3_media (operands[0], operands[0],
7462 val2 = val & 0xffff;
7463 if ((val >> 16 & 0xffff) == val2
7464 && (val >> 32 & 0xffff) == val2
7465 && (val >> 48 & 0xffff) == val2)
7467 val2 = (HOST_WIDE_INT) val >> 48;
7468 operands[1] = gen_rtx_REG (V4HImode, true_regnum (operands[0]));
7469 operands[1] = gen_mperm_w0 (operands[1], operands[1]);
7472 /* Try movi / mshflo.l */
7473 val2 = (HOST_WIDE_INT) val >> 32;
7474 if (val2 == ((unsigned HOST_WIDE_INT)
7475 trunc_int_for_mode (val, SImode)))
7477 operands[1] = gen_mshflo_l_di (operands[0], operands[0],
7481 /* Try movi / mshflo.l w/ r63. */
7482 val2 = val + ((HOST_WIDE_INT) -1 << 32);
7483 if ((HOST_WIDE_INT) val2 < 0 && CONST_OK_FOR_I16 (val2))
7485 operands[1] = gen_mshflo_l_di (operands[0], operands[0],
7491 operands[1] = gen_shori_media (operands[0], operands[0], GEN_INT (low));
7494 operands[2] = GEN_INT (val2);
7498 [(set (match_operand:DI 0 "ext_dest_operand" "")
7499 (match_operand:DI 1 "immediate_operand" ""))]
7500 "TARGET_SHMEDIA && reload_completed
7501 && GET_CODE (operands[1]) == CONST_DOUBLE"
7502 [(set (match_dup 0) (match_dup 2))
7504 (ior:DI (ashift:DI (match_dup 0) (const_int 16)) (match_dup 1)))]
7506 unsigned HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[1]);
7507 unsigned HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[1]);
7508 unsigned HOST_WIDE_INT val = low;
7509 unsigned HOST_WIDE_INT sign;
7511 /* Zero-extend the 16 least-significant bits. */
7513 operands[1] = GEN_INT (val);
7515 /* Arithmetic shift right the double-word by 16 bits. */
7517 low |= (high & 0xffff) << (HOST_BITS_PER_WIDE_INT - 16);
7520 sign <<= (HOST_BITS_PER_WIDE_INT - 16 - 1);
7524 /* This will only be true if high is a sign-extension of low, i.e.,
7525 it must be either 0 or (unsigned)-1, and be zero iff the
7526 most-significant bit of low is set. */
7527 if (high + (low >> (HOST_BITS_PER_WIDE_INT - 1)) == 0)
7528 operands[2] = GEN_INT (low);
7530 operands[2] = immed_double_const (low, high, DImode);
7533 (define_insn "shori_media"
7534 [(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
7535 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0,0")
7537 (match_operand:DI 2 "immediate_operand" "K16Csu,nF")))]
7538 "TARGET_SHMEDIA && (reload_completed || arith_reg_dest (operands[0], DImode))"
7542 [(set_attr "type" "arith_media,*")])
7544 (define_insn "*shori_media_si"
7545 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
7546 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
7548 (match_operand:SI 2 "immediate_operand" "K16Csu")))]
7552 (define_expand "movdi"
7553 [(set (match_operand:DI 0 "general_movdst_operand" "")
7554 (match_operand:DI 1 "general_movsrc_operand" ""))]
7557 prepare_move_operands (operands, DImode);
7560 (define_insn "movdf_media"
7561 [(set (match_operand:DF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
7562 (match_operand:DF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
7564 && (register_operand (operands[0], DFmode)
7565 || sh_register_operand (operands[1], DFmode))"
7576 [(set_attr "type" "fmove_media,fload_media,dfpconv_media,arith_media,*,
7577 fload_media,fstore_media,load_media,store_media")])
7579 (define_insn "movdf_media_nofpu"
7580 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
7581 (match_operand:DF 1 "general_movsrc_operand" "r,F,m,rZ"))]
7583 && (register_operand (operands[0], DFmode)
7584 || sh_register_operand (operands[1], DFmode))"
7590 [(set_attr "type" "arith_media,*,load_media,store_media")])
7593 [(set (match_operand:DF 0 "arith_reg_dest" "")
7594 (match_operand:DF 1 "immediate_operand" ""))]
7595 "TARGET_SHMEDIA && reload_completed"
7596 [(set (match_dup 3) (match_dup 2))]
7598 int endian = WORDS_BIG_ENDIAN ? 1 : 0;
7600 REAL_VALUE_TYPE value;
7602 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
7603 REAL_VALUE_TO_TARGET_DOUBLE (value, values);
7605 if (HOST_BITS_PER_WIDE_INT >= 64)
7606 operands[2] = immed_double_const ((unsigned long) values[endian]
7607 | ((HOST_WIDE_INT) values[1 - endian]
7611 gcc_assert (HOST_BITS_PER_WIDE_INT == 32);
7612 operands[2] = immed_double_const (values[endian], values[1 - endian],
7616 operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0]));
7619 ;; FIXME: This should be a define_insn_and_split.
7620 (define_insn "movdf_k"
7621 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
7622 (match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
7624 && (! (TARGET_SH4 || TARGET_SH2A_DOUBLE) || reload_completed
7625 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
7626 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
7627 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
7628 && (arith_reg_operand (operands[0], DFmode)
7629 || arith_reg_operand (operands[1], DFmode))"
7631 return output_movedouble (insn, operands, DFmode);
7633 [(set_attr "length" "4")
7634 (set_attr "type" "move,pcload,load,store")])
7636 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
7637 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
7638 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
7639 ;; the d/m/c/X alternative, which is split later into single-precision
7640 ;; instructions. And when not optimizing, no splits are done before fixing
7641 ;; up pcloads, so we need usable length information for that.
7642 (define_insn "movdf_i4"
7643 [(set (match_operand:DF 0 "general_movdst_operand" "=d,r,d,d,m,r,r,m,!??r,!???d")
7644 (match_operand:DF 1 "general_movsrc_operand" "d,r,F,m,d,FQ,m,r,d,r"))
7645 (use (reg:SI FPSCR_MODES_REG))
7646 (clobber (match_scratch:SI 2 "=X,X,&z,X,X,X,X,X,X,X"))]
7647 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7648 && (arith_reg_operand (operands[0], DFmode)
7649 || arith_reg_operand (operands[1], DFmode))"
7651 switch (which_alternative)
7655 return "fmov %1,%0";
7656 else if (REGNO (operands[0]) != REGNO (operands[1]) + 1)
7657 return "fmov %R1,%R0" "\n"
7660 return "fmov %S1,%S0" "\n"
7664 return "fmov.d %1,%0";
7669 [(set_attr_alternative "length"
7670 [(if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 8))
7672 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
7673 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
7674 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
7676 (const_int 8) (const_int 8) ;; these need only 8 bytes for @(r0,rn)
7677 ;; We can't use 4-byte push/pop on SHcompact, so we have to
7678 ;; increment or decrement r15 explicitly.
7680 (match_test "TARGET_SHCOMPACT")
7681 (const_int 10) (const_int 8))
7683 (match_test "TARGET_SHCOMPACT")
7684 (const_int 10) (const_int 8))])
7685 (set_attr "type" "fmove,move,pcfload,fload,fstore,pcload,load,store,load,fload")
7686 (set_attr "late_fp_use" "*,*,*,*,yes,*,*,*,*,*")
7687 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
7688 (const_string "double")
7689 (const_string "none")))])
7691 ;; Moving DFmode between fp/general registers through memory
7692 ;; (the top of the stack) is faster than moving through fpul even for
7693 ;; little endian. Because the type of an instruction is important for its
7694 ;; scheduling, it is beneficial to split these operations, rather than
7695 ;; emitting them in one single chunk, even if this will expose a stack
7696 ;; use that will prevent scheduling of other stack accesses beyond this
7699 [(set (match_operand:DF 0 "register_operand")
7700 (match_operand:DF 1 "register_operand"))
7701 (use (reg:SI FPSCR_MODES_REG))
7702 (clobber (match_scratch:SI 2))]
7703 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && reload_completed
7704 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
7709 if (TARGET_SH5 && true_regnum (operands[1]) < 16)
7711 emit_move_insn (stack_pointer_rtx,
7712 plus_constant (Pmode, stack_pointer_rtx, -8));
7713 tos = gen_tmp_stack_mem (DFmode, stack_pointer_rtx);
7716 tos = gen_tmp_stack_mem (DFmode,
7717 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
7718 insn = emit_insn (gen_movdf_i4 (tos, operands[1]));
7719 if (! (TARGET_SH5 && true_regnum (operands[1]) < 16))
7720 add_reg_note (insn, REG_INC, stack_pointer_rtx);
7721 if (TARGET_SH5 && true_regnum (operands[0]) < 16)
7722 tos = gen_tmp_stack_mem (DFmode, stack_pointer_rtx);
7724 tos = gen_tmp_stack_mem (DFmode,
7725 gen_rtx_POST_INC (Pmode, stack_pointer_rtx));
7726 insn = emit_insn (gen_movdf_i4 (operands[0], tos));
7727 if (TARGET_SH5 && true_regnum (operands[0]) < 16)
7728 emit_move_insn (stack_pointer_rtx,
7729 plus_constant (Pmode, stack_pointer_rtx, 8));
7731 add_reg_note (insn, REG_INC, stack_pointer_rtx);
7735 ;; local-alloc sometimes allocates scratch registers even when not required,
7736 ;; so we must be prepared to handle these.
7738 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
7740 [(set (match_operand:DF 0 "general_movdst_operand" "")
7741 (match_operand:DF 1 "general_movsrc_operand" ""))
7742 (use (reg:SI FPSCR_MODES_REG))
7743 (clobber (match_scratch:SI 2))]
7744 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7746 && true_regnum (operands[0]) < 16
7747 && true_regnum (operands[1]) < 16"
7748 [(set (match_dup 0) (match_dup 1))]
7750 /* If this was a reg <-> mem operation with base + index reg addressing,
7751 we have to handle this in a special way. */
7752 rtx mem = operands[0];
7754 if (! memory_operand (mem, DFmode))
7759 if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0)
7760 mem = SUBREG_REG (mem);
7763 rtx addr = XEXP (mem, 0);
7764 if (GET_CODE (addr) == PLUS
7765 && REG_P (XEXP (addr, 0))
7766 && REG_P (XEXP (addr, 1)))
7769 rtx reg0 = gen_rtx_REG (Pmode, 0);
7770 rtx regop = operands[store_p], word0 ,word1;
7772 if (GET_CODE (regop) == SUBREG)
7773 alter_subreg (®op, true);
7774 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
7778 mem = copy_rtx (mem);
7779 PUT_MODE (mem, SImode);
7780 word0 = gen_rtx_SUBREG (SImode, regop, 0);
7781 alter_subreg (&word0, true);
7782 word1 = gen_rtx_SUBREG (SImode, regop, 4);
7783 alter_subreg (&word1, true);
7784 if (store_p || ! refers_to_regno_p (REGNO (word0),
7785 REGNO (word0) + 1, addr, 0))
7788 ? gen_movsi_ie (mem, word0)
7789 : gen_movsi_ie (word0, mem));
7790 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
7791 mem = copy_rtx (mem);
7793 ? gen_movsi_ie (mem, word1)
7794 : gen_movsi_ie (word1, mem));
7795 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
7799 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
7800 emit_insn (gen_movsi_ie (word1, mem));
7801 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
7802 mem = copy_rtx (mem);
7803 emit_insn (gen_movsi_ie (word0, mem));
7810 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
7812 [(set (match_operand:DF 0 "register_operand" "")
7813 (match_operand:DF 1 "memory_operand" ""))
7814 (use (reg:SI FPSCR_MODES_REG))
7815 (clobber (reg:SI R0_REG))]
7816 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && reload_completed"
7817 [(parallel [(set (match_dup 0) (match_dup 1))
7818 (use (reg:SI FPSCR_MODES_REG))
7819 (clobber (scratch:SI))])]
7822 (define_expand "reload_indf__frn"
7823 [(parallel [(set (match_operand:DF 0 "register_operand" "=a")
7824 (match_operand:DF 1 "immediate_operand" "FQ"))
7825 (use (reg:SI FPSCR_MODES_REG))
7826 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
7830 (define_expand "reload_outdf__RnFRm"
7831 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
7832 (match_operand:DF 1 "register_operand" "af,r"))
7833 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
7837 ;; Simplify no-op moves.
7839 [(set (match_operand:SF 0 "register_operand" "")
7840 (match_operand:SF 1 "register_operand" ""))
7841 (use (reg:SI FPSCR_MODES_REG))
7842 (clobber (match_scratch:SI 2))]
7843 "TARGET_SH2E && reload_completed
7844 && true_regnum (operands[0]) == true_regnum (operands[1])"
7845 [(set (match_dup 0) (match_dup 0))]
7848 ;; fmovd substitute post-reload splits
7850 [(set (match_operand:DF 0 "register_operand" "")
7851 (match_operand:DF 1 "register_operand" ""))
7852 (use (reg:SI FPSCR_MODES_REG))
7853 (clobber (match_scratch:SI 2))]
7854 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
7855 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
7856 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
7859 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
7860 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst),
7861 gen_rtx_REG (SFmode, src)));
7862 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst + 1),
7863 gen_rtx_REG (SFmode, src + 1)));
7868 [(set (match_operand:DF 0 "register_operand" "")
7869 (mem:DF (match_operand:SI 1 "register_operand" "")))
7870 (use (reg:SI FPSCR_MODES_REG))
7871 (clobber (match_scratch:SI 2))]
7872 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
7873 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
7874 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
7877 int regno = true_regnum (operands[0]);
7879 rtx mem = SET_SRC (XVECEXP (PATTERN (curr_insn), 0, 0));
7881 = change_address (mem, SFmode, gen_rtx_POST_INC (Pmode, operands[1]));
7882 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
7883 regno + SH_REG_MSW_OFFSET),
7885 add_reg_note (insn, REG_INC, operands[1]);
7886 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
7887 regno + SH_REG_LSW_OFFSET),
7888 change_address (mem, SFmode, NULL_RTX)));
7893 [(set (match_operand:DF 0 "register_operand" "")
7894 (match_operand:DF 1 "memory_operand" ""))
7895 (use (reg:SI FPSCR_MODES_REG))
7896 (clobber (match_scratch:SI 2))]
7897 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
7898 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
7901 int regno = true_regnum (operands[0]);
7903 rtx mem2 = change_address (operands[1], SFmode, NULL_RTX);
7904 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
7905 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
7907 operands[1] = copy_rtx (mem2);
7908 addr = XEXP (mem2, 0);
7910 switch (GET_CODE (addr))
7913 /* This is complicated. If the register is an arithmetic register
7914 we can just fall through to the REG+DISP case below. Otherwise
7915 we have to use a combination of POST_INC and REG addressing... */
7916 if (! arith_reg_operand (operands[1], SFmode))
7918 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
7919 insn = emit_insn (gen_movsf_ie (reg0, mem2));
7920 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7922 emit_insn (gen_movsf_ie (reg1, operands[1]));
7924 /* If we have modified the stack pointer, the value that we have
7925 read with post-increment might be modified by an interrupt,
7926 so write it back. */
7927 if (REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
7928 emit_insn (gen_push_e (reg0));
7930 emit_insn (gen_addsi3 (XEXP (operands[1], 0), XEXP (operands[1], 0),
7937 emit_insn (gen_movsf_ie (reg0, operands[1]));
7938 operands[1] = copy_rtx (operands[1]);
7939 XEXP (operands[1], 0) = plus_constant (Pmode, addr, 4);
7940 emit_insn (gen_movsf_ie (reg1, operands[1]));
7944 insn = emit_insn (gen_movsf_ie (reg0, operands[1]));
7945 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7947 insn = emit_insn (gen_movsf_ie (reg1, operands[1]));
7948 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7960 [(set (match_operand:DF 0 "memory_operand" "")
7961 (match_operand:DF 1 "register_operand" ""))
7962 (use (reg:SI FPSCR_MODES_REG))
7963 (clobber (match_scratch:SI 2))]
7964 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
7965 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
7968 int regno = true_regnum (operands[1]);
7970 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
7971 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
7973 operands[0] = copy_rtx (operands[0]);
7974 PUT_MODE (operands[0], SFmode);
7975 addr = XEXP (operands[0], 0);
7977 switch (GET_CODE (addr))
7980 /* This is complicated. If the register is an arithmetic register
7981 we can just fall through to the REG+DISP case below. Otherwise
7982 we have to use a combination of REG and PRE_DEC addressing... */
7983 if (! arith_reg_operand (operands[0], SFmode))
7985 emit_insn (gen_addsi3 (addr, addr, GEN_INT (4)));
7986 emit_insn (gen_movsf_ie (operands[0], reg1));
7988 operands[0] = copy_rtx (operands[0]);
7989 XEXP (operands[0], 0) = addr = gen_rtx_PRE_DEC (SImode, addr);
7991 insn = emit_insn (gen_movsf_ie (operands[0], reg0));
7992 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7998 /* Since REG+DISP addressing has already been decided upon by gcc
7999 we can rely upon it having chosen an arithmetic register as the
8000 register component of the address. Just emit the lower numbered
8001 register first, to the lower address, then the higher numbered
8002 register to the higher address. */
8003 emit_insn (gen_movsf_ie (operands[0], reg0));
8005 operands[0] = copy_rtx (operands[0]);
8006 XEXP (operands[0], 0) = plus_constant (Pmode, addr, 4);
8008 emit_insn (gen_movsf_ie (operands[0], reg1));
8012 /* This is easy. Output the word to go to the higher address
8013 first (ie the word in the higher numbered register) then the
8014 word to go to the lower address. */
8016 insn = emit_insn (gen_movsf_ie (operands[0], reg1));
8017 add_reg_note (insn, REG_INC, XEXP (addr, 0));
8019 insn = emit_insn (gen_movsf_ie (operands[0], reg0));
8020 add_reg_note (insn, REG_INC, XEXP (addr, 0));
8032 ;; If the output is a register and the input is memory or a register, we have
8033 ;; to be careful and see which word needs to be loaded first.
8035 [(set (match_operand:DF 0 "general_movdst_operand" "")
8036 (match_operand:DF 1 "general_movsrc_operand" ""))]
8037 "TARGET_SH1 && reload_completed"
8038 [(set (match_dup 2) (match_dup 3))
8039 (set (match_dup 4) (match_dup 5))]
8043 if ((MEM_P (operands[0])
8044 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
8045 || (MEM_P (operands[1])
8046 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
8049 switch (GET_CODE (operands[0]))
8052 regno = REGNO (operands[0]);
8055 regno = subreg_regno (operands[0]);
8065 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
8067 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
8068 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
8069 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
8070 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
8074 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
8075 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
8076 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
8077 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
8080 if (operands[2] == 0 || operands[3] == 0
8081 || operands[4] == 0 || operands[5] == 0)
8085 (define_expand "movdf"
8086 [(set (match_operand:DF 0 "general_movdst_operand" "")
8087 (match_operand:DF 1 "general_movsrc_operand" ""))]
8090 prepare_move_operands (operands, DFmode);
8093 if (TARGET_SHMEDIA_FPU)
8094 emit_insn (gen_movdf_media (operands[0], operands[1]));
8096 emit_insn (gen_movdf_media_nofpu (operands[0], operands[1]));
8099 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
8101 emit_insn (gen_movdf_i4 (operands[0], operands[1]));
8106 ;;This is incompatible with the way gcc uses subregs.
8107 ;;(define_insn "movv2sf_i"
8108 ;; [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,m")
8109 ;; (match_operand:V2SF 1 "nonimmediate_operand" "f,m,f"))]
8110 ;; "TARGET_SHMEDIA_FPU
8111 ;; && (fp_arith_reg_operand (operands[0], V2SFmode)
8112 ;; || fp_arith_reg_operand (operands[1], V2SFmode))"
8116 ;; fst%M0.p %m0, %1"
8117 ;; [(set_attr "type" "*,fload_media,fstore_media")])
8118 (define_insn_and_split "movv2sf_i"
8119 [(set (match_operand:V2SF 0 "general_movdst_operand" "=f,rf,r,m,mf")
8120 (match_operand:V2SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))]
8121 "TARGET_SHMEDIA_FPU"
8123 "TARGET_SHMEDIA_FPU && reload_completed"
8124 [(set (match_dup 0) (match_dup 1))]
8126 operands[0] = simplify_gen_subreg (DFmode, operands[0], V2SFmode, 0);
8127 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2SFmode, 0);
8130 (define_expand "movv2sf"
8131 [(set (match_operand:V2SF 0 "general_movdst_operand" "")
8132 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
8133 "TARGET_SHMEDIA_FPU"
8135 prepare_move_operands (operands, V2SFmode);
8138 (define_expand "addv2sf3"
8139 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8140 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8141 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8142 "TARGET_SHMEDIA_FPU"
8144 sh_expand_binop_v2sf (PLUS, operands[0], operands[1], operands[2]);
8148 (define_expand "subv2sf3"
8149 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8150 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8151 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8152 "TARGET_SHMEDIA_FPU"
8154 sh_expand_binop_v2sf (MINUS, operands[0], operands[1], operands[2]);
8158 (define_expand "mulv2sf3"
8159 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8160 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8161 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8162 "TARGET_SHMEDIA_FPU"
8164 sh_expand_binop_v2sf (MULT, operands[0], operands[1], operands[2]);
8168 (define_expand "divv2sf3"
8169 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8170 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8171 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8172 "TARGET_SHMEDIA_FPU"
8174 sh_expand_binop_v2sf (DIV, operands[0], operands[1], operands[2]);
8178 (define_insn_and_split "*movv4sf_i"
8179 [(set (match_operand:V4SF 0 "general_movdst_operand" "=f,rf,r,m,mf")
8180 (match_operand:V4SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))]
8181 "TARGET_SHMEDIA_FPU"
8183 "&& reload_completed"
8186 for (int i = 0; i < 4/2; i++)
8190 if (MEM_P (operands[0]))
8191 x = adjust_address (operands[0], V2SFmode,
8192 i * GET_MODE_SIZE (V2SFmode));
8194 x = simplify_gen_subreg (V2SFmode, operands[0], V4SFmode, i * 8);
8196 if (MEM_P (operands[1]))
8197 y = adjust_address (operands[1], V2SFmode,
8198 i * GET_MODE_SIZE (V2SFmode));
8200 y = simplify_gen_subreg (V2SFmode, operands[1], V4SFmode, i * 8);
8202 emit_insn (gen_movv2sf_i (x, y));
8207 [(set_attr "length" "8")])
8209 (define_expand "movv4sf"
8210 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
8211 (match_operand:V4SF 1 "general_operand" ""))]
8212 "TARGET_SHMEDIA_FPU"
8214 prepare_move_operands (operands, V4SFmode);
8217 (define_insn_and_split "*movv16sf_i"
8218 [(set (match_operand:V16SF 0 "nonimmediate_operand" "=f,f,m")
8219 (match_operand:V16SF 1 "nonimmediate_operand" "f,m,f"))]
8220 "TARGET_SHMEDIA_FPU"
8222 "&& reload_completed"
8225 for (int i = 0; i < 16/2; i++)
8229 if (MEM_P (operands[0]))
8230 x = adjust_address (operands[0], V2SFmode,
8231 i * GET_MODE_SIZE (V2SFmode));
8234 x = gen_rtx_SUBREG (V2SFmode, operands[0], i * 8);
8235 alter_subreg (&x, true);
8238 if (MEM_P (operands[1]))
8239 y = adjust_address (operands[1], V2SFmode,
8240 i * GET_MODE_SIZE (V2SFmode));
8243 y = gen_rtx_SUBREG (V2SFmode, operands[1], i * 8);
8244 alter_subreg (&y, true);
8247 emit_insn (gen_movv2sf_i (x, y));
8252 [(set_attr "length" "32")])
8254 (define_expand "movv16sf"
8255 [(set (match_operand:V16SF 0 "nonimmediate_operand" "=f,f,m")
8256 (match_operand:V16SF 1 "nonimmediate_operand" "f,m,f"))]
8257 "TARGET_SHMEDIA_FPU"
8259 prepare_move_operands (operands, V16SFmode);
8262 (define_insn "movsf_media"
8263 [(set (match_operand:SF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
8264 (match_operand:SF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
8266 && (register_operand (operands[0], SFmode)
8267 || sh_register_operand (operands[1], SFmode))"
8278 [(set_attr "type" "fmove_media,fload_media,fpconv_media,arith_media,*,fload_media,fstore_media,load_media,store_media")
8279 (set (attr "highpart")
8280 (cond [(match_test "sh_contains_memref_p (insn)")
8281 (const_string "user")]
8282 (const_string "ignore")))])
8284 (define_insn "movsf_media_nofpu"
8285 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,m")
8286 (match_operand:SF 1 "general_movsrc_operand" "r,F,m,rZ"))]
8288 && (register_operand (operands[0], SFmode)
8289 || sh_register_operand (operands[1], SFmode))"
8295 [(set_attr "type" "arith_media,*,load_media,store_media")
8296 (set (attr "highpart")
8297 (cond [(match_test "sh_contains_memref_p (insn)")
8298 (const_string "user")]
8299 (const_string "ignore")))])
8302 [(set (match_operand:SF 0 "arith_reg_dest" "")
8303 (match_operand:SF 1 "immediate_operand" ""))]
8304 "TARGET_SHMEDIA && reload_completed
8305 && ! FP_REGISTER_P (true_regnum (operands[0]))"
8306 [(set (match_dup 3) (match_dup 2))]
8309 REAL_VALUE_TYPE value;
8311 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
8312 REAL_VALUE_TO_TARGET_SINGLE (value, values);
8313 operands[2] = GEN_INT (values);
8315 operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0]));
8318 (define_insn "movsf_i"
8319 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
8320 (match_operand:SF 1 "general_movsrc_operand" "r,G,FQ,mr,r,r,l"))]
8323 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
8324 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
8325 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
8326 && (arith_reg_operand (operands[0], SFmode)
8327 || arith_reg_operand (operands[1], SFmode))"
8336 [(set_attr "type" "move,move,pcload,load,store,move,move")])
8338 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
8339 ;; update_flow_info would not know where to put REG_EQUAL notes
8340 ;; when the destination changes mode.
8341 (define_insn "movsf_ie"
8342 [(set (match_operand:SF 0 "general_movdst_operand"
8343 "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,<,y,y")
8344 (match_operand:SF 1 "general_movsrc_operand"
8345 "f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
8346 (use (reg:SI FPSCR_MODES_REG))
8347 (clobber (match_scratch:SI 2 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))]
8349 && (arith_reg_operand (operands[0], SFmode) || fpul_operand (operands[0], SFmode)
8350 || arith_reg_operand (operands[1], SFmode) || fpul_operand (operands[1], SFmode)
8351 || arith_reg_operand (operands[2], SImode))"
8371 ! move optimized away"
8372 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,
8373 store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil")
8374 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
8375 (set_attr_alternative "length"
8382 (match_test "TARGET_SH2A")
8383 (const_int 4) (const_int 2))
8385 (match_test "TARGET_SH2A")
8386 (const_int 4) (const_int 2))
8389 (match_test "TARGET_SH2A")
8390 (const_int 4) (const_int 2))
8392 (match_test "TARGET_SH2A")
8393 (const_int 4) (const_int 2))
8403 (set_attr_alternative "fp_mode"
8404 [(if_then_else (eq_attr "fmovd" "yes")
8405 (const_string "single") (const_string "none"))
8406 (const_string "none")
8407 (const_string "single")
8408 (const_string "single")
8409 (const_string "none")
8410 (if_then_else (eq_attr "fmovd" "yes")
8411 (const_string "single") (const_string "none"))
8412 (if_then_else (eq_attr "fmovd" "yes")
8413 (const_string "single") (const_string "none"))
8414 (const_string "none")
8415 (const_string "none")
8416 (const_string "none")
8417 (const_string "none")
8418 (const_string "none")
8419 (const_string "none")
8420 (const_string "none")
8421 (const_string "none")
8422 (const_string "none")
8423 (const_string "none")
8424 (const_string "none")
8425 (const_string "none")])])
8427 (define_insn_and_split "movsf_ie_ra"
8428 [(set (match_operand:SF 0 "general_movdst_operand"
8429 "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,<,y,y")
8430 (match_operand:SF 1 "general_movsrc_operand"
8431 "f,r,G,H,FQ,m,f,FQ,m,r,y,f,>,fr,y,r,y,>,y"))
8432 (use (reg:SI FPSCR_MODES_REG))
8433 (clobber (match_scratch:SF 2 "=r,r,X,X,&z,r,r,X,r,r,r,r,r,y,r,r,r,r,r"))
8436 && (arith_reg_operand (operands[0], SFmode)
8437 || fpul_operand (operands[0], SFmode)
8438 || arith_reg_operand (operands[1], SFmode)
8439 || fpul_operand (operands[1], SFmode))"
8459 ! move optimized away"
8461 && sh_movsf_ie_ra_split_p (operands[0], operands[1], operands[2])"
8464 if (! rtx_equal_p (operands[0], operands[1]))
8466 emit_insn (gen_movsf_ie (operands[2], operands[1]));
8467 emit_insn (gen_movsf_ie (operands[0], operands[2]));
8470 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,
8471 store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil")
8472 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
8473 (set_attr_alternative "length"
8480 (match_test "TARGET_SH2A")
8481 (const_int 4) (const_int 2))
8483 (match_test "TARGET_SH2A")
8484 (const_int 4) (const_int 2))
8487 (match_test "TARGET_SH2A")
8488 (const_int 4) (const_int 2))
8490 (match_test "TARGET_SH2A")
8491 (const_int 4) (const_int 2))
8501 (set_attr_alternative "fp_mode"
8502 [(if_then_else (eq_attr "fmovd" "yes")
8503 (const_string "single") (const_string "none"))
8504 (const_string "none")
8505 (const_string "single")
8506 (const_string "single")
8507 (const_string "none")
8508 (if_then_else (eq_attr "fmovd" "yes")
8509 (const_string "single") (const_string "none"))
8510 (if_then_else (eq_attr "fmovd" "yes")
8511 (const_string "single") (const_string "none"))
8512 (const_string "none")
8513 (const_string "none")
8514 (const_string "none")
8515 (const_string "none")
8516 (const_string "none")
8517 (const_string "none")
8518 (const_string "none")
8519 (const_string "none")
8520 (const_string "none")
8521 (const_string "none")
8522 (const_string "none")
8523 (const_string "none")])])
8526 [(set (match_operand:SF 0 "register_operand" "")
8527 (match_operand:SF 1 "register_operand" ""))
8528 (use (reg:SI FPSCR_MODES_REG))
8529 (clobber (reg:SI FPUL_REG))]
8531 [(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
8532 (use (reg:SI FPSCR_MODES_REG))
8533 (clobber (scratch:SI))])
8534 (parallel [(set (match_dup 0) (reg:SF FPUL_REG))
8535 (use (reg:SI FPSCR_MODES_REG))
8536 (clobber (scratch:SI))])]
8539 (define_expand "movsf"
8540 [(set (match_operand:SF 0 "general_movdst_operand" "")
8541 (match_operand:SF 1 "general_movsrc_operand" ""))]
8544 prepare_move_operands (operands, SFmode);
8547 if (TARGET_SHMEDIA_FPU)
8548 emit_insn (gen_movsf_media (operands[0], operands[1]));
8550 emit_insn (gen_movsf_media_nofpu (operands[0], operands[1]));
8555 if (lra_in_progress)
8557 if (GET_CODE (operands[0]) == SCRATCH)
8559 emit_insn (gen_movsf_ie_ra (operands[0], operands[1]));
8563 emit_insn (gen_movsf_ie (operands[0], operands[1]));
8568 (define_insn "mov_nop"
8569 [(set (match_operand 0 "any_register_operand" "") (match_dup 0))]
8572 [(set_attr "length" "0")
8573 (set_attr "type" "nil")])
8575 (define_expand "reload_insf__frn"
8576 [(parallel [(set (match_operand:SF 0 "register_operand" "=a")
8577 (match_operand:SF 1 "immediate_operand" "FQ"))
8578 (use (reg:SI FPSCR_MODES_REG))
8579 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
8583 (define_expand "reload_insi__i_fpul"
8584 [(parallel [(set (match_operand:SI 0 "fpul_operand" "=y")
8585 (match_operand:SI 1 "immediate_operand" "i"))
8586 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
8590 (define_expand "ptabs"
8591 [(set (match_operand 0 "" "=b") (match_operand 1 "" "r"))]
8594 if (!TARGET_PT_FIXED)
8596 rtx eq = operands[1];
8598 /* ??? For canonical RTL we really should remove any CONST from EQ
8599 before wrapping it in the AND, and finally wrap the EQ into a
8600 const if is constant. However, for reload we must expose the
8601 input register or symbolic constant, and we can't have
8602 different insn structures outside of the operands for different
8603 alternatives of the same pattern. */
8604 eq = gen_rtx_EQ (SImode, gen_rtx_AND (Pmode, eq, GEN_INT (3)),
8607 = (gen_rtx_IF_THEN_ELSE
8610 gen_rtx_MEM (PDImode, operands[1]),
8611 gen_rtx_fmt_e (TARGET_SHMEDIA32 ? SIGN_EXTEND : TRUNCATE,
8612 PDImode, operands[1])));
8616 ;; expanded by ptabs expander.
8617 (define_insn "*extendsipdi_media"
8618 [(set (match_operand:PDI 0 "target_reg_operand" "=b,b");
8619 (if_then_else:PDI (eq (and:SI (match_operand:SI 1 "target_operand"
8623 (mem:PDI (match_dup 1))
8624 (sign_extend:PDI (match_dup 1))))]
8625 "TARGET_SHMEDIA && !TARGET_PT_FIXED"
8629 [(set_attr "type" "ptabs_media,pt_media")
8630 (set_attr "length" "4,*")])
8632 (define_insn "*truncdipdi_media"
8633 [(set (match_operand:PDI 0 "target_reg_operand" "=b,b");
8634 (if_then_else:PDI (eq (and:DI (match_operand:DI 1 "target_operand"
8638 (mem:PDI (match_dup 1))
8639 (truncate:PDI (match_dup 1))))]
8640 "TARGET_SHMEDIA && !TARGET_PT_FIXED"
8644 [(set_attr "type" "ptabs_media,pt_media")
8645 (set_attr "length" "4,*")])
8647 (define_insn "*movsi_y"
8648 [(set (match_operand:SI 0 "register_operand" "=y,y")
8649 (match_operand:SI 1 "immediate_operand" "Qi,I08"))
8650 (clobber (match_scratch:SI 2 "=&z,r"))]
8652 && (reload_in_progress || reload_completed)"
8654 [(set_attr "length" "4")
8655 (set_attr "type" "pcload,move")])
8658 [(set (match_operand:SI 0 "register_operand" "")
8659 (match_operand:SI 1 "immediate_operand" ""))
8660 (clobber (match_operand:SI 2 "register_operand" ""))]
8662 [(set (match_dup 2) (match_dup 1))
8663 (set (match_dup 0) (match_dup 2))]
8666 ;; ------------------------------------------------------------------------
8667 ;; Define the real conditional branch instructions.
8668 ;; ------------------------------------------------------------------------
8670 (define_expand "branch_true"
8671 [(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
8672 (label_ref (match_operand 0))
8676 (define_expand "branch_false"
8677 [(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
8678 (label_ref (match_operand 0))
8682 (define_insn_and_split "*cbranch_t"
8683 [(set (pc) (if_then_else (match_operand 1 "cbranch_treg_value")
8684 (label_ref (match_operand 0))
8688 return output_branch (sh_eval_treg_value (operands[1]), insn, operands);
8693 /* Try to canonicalize the branch condition if it is not one of:
8694 (ne (reg:SI T_REG) (const_int 0))
8695 (eq (reg:SI T_REG) (const_int 0))
8697 Instead of splitting out a new insn, we modify the current insn's
8698 operands as needed. This preserves things such as REG_DEAD notes. */
8700 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
8701 && REG_P (XEXP (operands[1], 0)) && REGNO (XEXP (operands[1], 0)) == T_REG
8702 && XEXP (operands[1], 1) == const0_rtx)
8705 int branch_cond = sh_eval_treg_value (operands[1]);
8706 rtx new_cond_rtx = NULL_RTX;
8708 if (branch_cond == 0)
8709 new_cond_rtx = gen_rtx_EQ (VOIDmode, get_t_reg_rtx (), const0_rtx);
8710 else if (branch_cond == 1)
8711 new_cond_rtx = gen_rtx_NE (VOIDmode, get_t_reg_rtx (), const0_rtx);
8713 if (new_cond_rtx != NULL_RTX)
8714 validate_change (curr_insn, &XEXP (XEXP (PATTERN (curr_insn), 1), 0),
8715 new_cond_rtx, false);
8718 [(set_attr "type" "cbranch")])
8720 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
8721 ;; which destination is too far away.
8722 ;; The const_int_operand is distinct for each branch target; it avoids
8723 ;; unwanted matches with redundant_insn.
8724 (define_insn "block_branch_redirect"
8725 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BBR))]
8728 [(set_attr "length" "0")])
8730 ;; This one has the additional purpose to record a possible scratch register
8731 ;; for the following branch.
8732 ;; ??? Unfortunately, just setting the scratch register is not good enough,
8733 ;; because the insn then might be deemed dead and deleted. And we can't
8734 ;; make the use in the jump insn explicit because that would disable
8735 ;; delay slot scheduling from the target.
8736 (define_insn "indirect_jump_scratch"
8737 [(set (match_operand:SI 0 "register_operand" "=r")
8738 (unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))
8739 (set (pc) (unspec [(const_int 0)] UNSPEC_BBR))]
8742 [(set_attr "length" "0")])
8744 ;; This one is used to preemt an insn from beyond the bra / braf / jmp
8745 ;; being pulled into the delay slot of a condbranch that has been made to
8746 ;; jump around the unconditional jump because it was out of range.
8747 (define_insn "stuff_delay_slot"
8749 (unspec [(match_operand:SI 0 "const_int_operand" "") (pc)
8750 (match_operand:SI 1 "const_int_operand" "")] UNSPEC_BBR))]
8753 [(set_attr "length" "0")
8754 (set_attr "cond_delay_slot" "yes")])
8756 ;; Conditional branch insns
8758 (define_expand "cbranchint4_media"
8760 (if_then_else (match_operator 0 "shmedia_cbranch_comparison_operator"
8761 [(match_operand 1 "" "")
8762 (match_operand 2 "" "")])
8763 (match_operand 3 "" "")
8767 machine_mode mode = GET_MODE (operands[1]);
8768 if (mode == VOIDmode)
8769 mode = GET_MODE (operands[2]);
8770 if (GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)
8772 operands[1] = force_reg (mode, operands[1]);
8773 if (CONSTANT_P (operands[2])
8774 && (! satisfies_constraint_I06 (operands[2])))
8775 operands[2] = force_reg (mode, operands[2]);
8779 if (operands[1] != const0_rtx)
8780 operands[1] = force_reg (mode, operands[1]);
8781 if (operands[2] != const0_rtx)
8782 operands[2] = force_reg (mode, operands[2]);
8784 switch (GET_CODE (operands[0]))
8790 operands[0] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[0])),
8791 VOIDmode, operands[2], operands[1]);
8792 operands[1] = XEXP (operands[0], 0);
8793 operands[2] = XEXP (operands[0], 1);
8796 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
8797 VOIDmode, operands[1], operands[2]);
8800 operands[3] = gen_rtx_LABEL_REF (Pmode, operands[3]);
8803 (define_expand "cbranchfp4_media"
8805 (if_then_else (match_operator 0 "sh_float_comparison_operator"
8806 [(match_operand 1 "" "")
8807 (match_operand 2 "" "")])
8808 (match_operand 3 "" "")
8812 rtx tmp = gen_reg_rtx (SImode);
8814 if (GET_CODE (operands[0]) == NE)
8815 cmp = gen_rtx_EQ (SImode, operands[1], operands[2]);
8817 cmp = gen_rtx_fmt_ee (GET_CODE (operands[0]), SImode,
8818 operands[1], operands[2]);
8820 emit_insn (gen_cstore4_media (tmp, cmp, operands[1], operands[2]));
8822 if (GET_CODE (cmp) == GET_CODE (operands[0]))
8823 operands[0] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
8825 operands[0] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
8827 operands[2] = const0_rtx;
8828 operands[3] = gen_rtx_LABEL_REF (Pmode, operands[3]);
8831 (define_insn "*beq_media_i"
8833 (if_then_else (match_operator 3 "equality_comparison_operator"
8834 [(match_operand:DI 1 "arith_reg_operand" "r,r")
8835 (match_operand:DI 2 "arith_operand" "r,I06")])
8836 (match_operand 0 "target_operand" "b,b")
8841 b%o3i%' %1, %2, %0%>"
8842 [(set_attr "type" "cbranch_media")])
8844 (define_insn "*beq_media_i32"
8846 (if_then_else (match_operator 3 "equality_comparison_operator"
8847 [(match_operand:SI 1 "arith_reg_operand" "r,r")
8848 (match_operand:SI 2 "arith_operand" "r,I06")])
8849 (match_operand 0 "target_operand" "b,b")
8854 b%o3i%' %1, %2, %0%>"
8855 [(set_attr "type" "cbranch_media")])
8857 (define_insn "*bgt_media_i"
8859 (if_then_else (match_operator 3 "greater_comparison_operator"
8860 [(match_operand:DI 1 "arith_reg_or_0_operand" "rN")
8861 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")])
8862 (match_operand 0 "target_operand" "b")
8865 "b%o3%' %N1, %N2, %0%>"
8866 [(set_attr "type" "cbranch_media")])
8868 (define_insn "*bgt_media_i32"
8870 (if_then_else (match_operator 3 "greater_comparison_operator"
8871 [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
8872 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")])
8873 (match_operand 0 "target_operand" "b")
8876 "b%o3%' %N1, %N2, %0%>"
8877 [(set_attr "type" "cbranch_media")])
8879 ;; These are only needed to make invert_jump() happy - otherwise, jump
8880 ;; optimization will be silently disabled.
8881 (define_insn "*blt_media_i"
8883 (if_then_else (match_operator 3 "less_comparison_operator"
8884 [(match_operand:DI 1 "arith_reg_or_0_operand" "rN")
8885 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")])
8886 (match_operand 0 "target_operand" "b")
8889 "b%o3%' %N2, %N1, %0%>"
8890 [(set_attr "type" "cbranch_media")])
8892 (define_insn "*blt_media_i32"
8894 (if_then_else (match_operator 3 "less_comparison_operator"
8895 [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
8896 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")])
8897 (match_operand 0 "target_operand" "b")
8900 "b%o3%' %N2, %N1, %0%>"
8901 [(set_attr "type" "cbranch_media")])
8903 ;; combiner splitter for test-and-branch on single bit in register. This
8904 ;; is endian dependent because the non-paradoxical subreg looks different
8909 (match_operator 3 "equality_comparison_operator"
8912 (subreg:DI (match_operand:SI 1 "extend_reg_operand" "") 0)
8914 (match_operand 2 "const_int_operand" "")) 0)
8916 (match_operand 0 "target_operand" "")
8918 (clobber (match_operand:SI 4 "arith_reg_dest" ""))]
8919 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
8920 [(set (match_dup 4) (ashift:SI (match_dup 1) (match_dup 5)))
8921 (set (pc) (if_then_else (match_dup 6) (match_dup 0) (pc)))]
8923 operands[5] = GEN_INT (31 - INTVAL (operands[2]));
8924 operands[6] = (GET_CODE (operands[3]) == EQ
8925 ? gen_rtx_GE (VOIDmode, operands[4], const0_rtx)
8926 : gen_rtx_GT (VOIDmode, const0_rtx, operands[4]));
8929 ; operand 0 is the loop count pseudo register
8930 ; operand 1 is the label to jump to at the top of the loop
8931 (define_expand "doloop_end"
8932 [(parallel [(set (pc)
8933 (if_then_else (ne:SI (match_operand:SI 0 "" "")
8935 (label_ref (match_operand 1 "" ""))
8938 (plus:SI (match_dup 0) (const_int -1)))
8939 (clobber (reg:SI T_REG))])]
8942 if (GET_MODE (operands[0]) != SImode)
8944 emit_jump_insn (gen_doloop_end_split (operands[0], operands[1], operands[0]));
8948 (define_insn_and_split "doloop_end_split"
8950 (if_then_else (ne:SI (match_operand:SI 2 "arith_reg_dest" "0")
8952 (label_ref (match_operand 1 "" ""))
8954 (set (match_operand:SI 0 "arith_reg_dest" "=r")
8955 (plus:SI (match_dup 2) (const_int -1)))
8956 (clobber (reg:SI T_REG))]
8960 [(parallel [(set (reg:SI T_REG)
8961 (eq:SI (match_dup 2) (const_int 1)))
8962 (set (match_dup 0) (plus:SI (match_dup 2) (const_int -1)))])
8963 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
8964 (label_ref (match_dup 1))
8967 [(set_attr "type" "cbranch")])
8969 ;; ------------------------------------------------------------------------
8970 ;; Jump and linkage insns
8971 ;; ------------------------------------------------------------------------
8973 (define_insn "jump_compact"
8975 (label_ref (match_operand 0 "" "")))]
8976 "TARGET_SH1 && !CROSSING_JUMP_P (insn)"
8978 /* The length is 16 if the delay slot is unfilled. */
8979 if (get_attr_length(insn) > 4)
8980 return output_far_jump(insn, operands[0]);
8984 [(set_attr "type" "jump")
8985 (set_attr "needs_delay_slot" "yes")])
8987 ;; ??? It would be much saner to explicitly use the scratch register
8988 ;; in the jump insn, and have indirect_jump_scratch only set it,
8989 ;; but fill_simple_delay_slots would refuse to do delay slot filling
8990 ;; from the target then, as it uses simplejump_p.
8991 ;;(define_insn "jump_compact_far"
8993 ;; (label_ref (match_operand 0 "" "")))
8994 ;; (use (match_operand 1 "register_operand" "r")]
8996 ;; "* return output_far_jump(insn, operands[0], operands[1]);"
8997 ;; [(set_attr "type" "jump")
8998 ;; (set_attr "needs_delay_slot" "yes")])
9000 (define_insn "jump_media"
9002 (match_operand 0 "target_operand" "b"))]
9005 [(set_attr "type" "jump_media")])
9007 (define_expand "jump"
9009 (label_ref (match_operand 0 "" "")))]
9013 emit_jump_insn (gen_jump_compact (operands[0]));
9014 else if (TARGET_SHMEDIA)
9016 if (reload_in_progress || reload_completed)
9018 emit_jump_insn (gen_jump_media (gen_rtx_LABEL_REF (Pmode, operands[0])));
9023 (define_insn "force_mode_for_call"
9024 [(use (reg:SI FPSCR_MODES_REG))]
9027 [(set_attr "length" "0")
9028 (set (attr "fp_mode")
9029 (if_then_else (eq_attr "fpu_single" "yes")
9030 (const_string "single") (const_string "double")))])
9032 (define_insn "calli"
9033 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9034 (match_operand 1 "" ""))
9035 (use (reg:SI FPSCR_MODES_REG))
9036 (clobber (reg:SI PR_REG))]
9039 if (TARGET_SH2A && (dbr_sequence_length () == 0))
9044 [(set_attr "type" "call")
9045 (set (attr "fp_mode")
9046 (if_then_else (eq_attr "fpu_single" "yes")
9047 (const_string "single") (const_string "double")))
9048 (set_attr "needs_delay_slot" "yes")
9049 (set_attr "fp_set" "unknown")])
9051 ;; This is TBR relative jump instruction for SH2A architecture.
9052 ;; Its use is enabled by assigning an attribute "function_vector"
9053 ;; and the vector number to a function during its declaration.
9054 (define_insn "calli_tbr_rel"
9055 [(call (mem (match_operand:SI 0 "symbol_ref_operand" ""))
9056 (match_operand 1 "" ""))
9057 (use (reg:SI FPSCR_MODES_REG))
9058 (clobber (reg:SI PR_REG))]
9059 "TARGET_SH2A && sh2a_is_function_vector_call (operands[0])"
9061 unsigned HOST_WIDE_INT vect_num;
9062 vect_num = sh2a_get_function_vector_number (operands[0]);
9063 operands[2] = GEN_INT (vect_num * 4);
9065 return "jsr/n @@(%O2,tbr)";
9067 [(set_attr "type" "call")
9068 (set (attr "fp_mode")
9069 (if_then_else (eq_attr "fpu_single" "yes")
9070 (const_string "single") (const_string "double")))
9071 (set_attr "needs_delay_slot" "no")
9072 (set_attr "fp_set" "unknown")])
9074 ;; This is a pc-rel call, using bsrf, for use with PIC.
9075 (define_insn "calli_pcrel"
9076 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9077 (match_operand 1 "" ""))
9078 (use (reg:SI FPSCR_MODES_REG))
9079 (use (reg:SI PIC_REG))
9080 (use (match_operand 2 "" ""))
9081 (clobber (reg:SI PR_REG))]
9084 return "bsrf %0" "\n"
9087 [(set_attr "type" "call")
9088 (set (attr "fp_mode")
9089 (if_then_else (eq_attr "fpu_single" "yes")
9090 (const_string "single") (const_string "double")))
9091 (set_attr "needs_delay_slot" "yes")
9092 (set_attr "fp_set" "unknown")])
9094 (define_insn_and_split "call_pcrel"
9095 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
9096 (match_operand 1 "" ""))
9097 (use (reg:SI FPSCR_MODES_REG))
9098 (use (reg:SI PIC_REG))
9099 (clobber (reg:SI PR_REG))
9100 (clobber (match_scratch:SI 2 "=r"))]
9106 rtx lab = PATTERN (gen_call_site ());
9108 if (SYMBOL_REF_LOCAL_P (operands[0]))
9109 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
9111 emit_insn (gen_symPLT_label2reg (operands[2], operands[0], lab));
9112 emit_call_insn (gen_calli_pcrel (operands[2], operands[1], copy_rtx (lab)));
9115 [(set_attr "type" "call")
9116 (set (attr "fp_mode")
9117 (if_then_else (eq_attr "fpu_single" "yes")
9118 (const_string "single") (const_string "double")))
9119 (set_attr "needs_delay_slot" "yes")
9120 (set_attr "fp_set" "unknown")])
9122 (define_insn "call_compact"
9123 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9124 (match_operand 1 "" ""))
9125 (match_operand 2 "immediate_operand" "n")
9126 (use (reg:SI R0_REG))
9127 (use (reg:SI R1_REG))
9128 (use (reg:SI FPSCR_MODES_REG))
9129 (clobber (reg:SI PR_REG))]
9130 "TARGET_SHCOMPACT && ! (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
9132 [(set_attr "type" "call")
9133 (set (attr "fp_mode")
9134 (if_then_else (eq_attr "fpu_single" "yes")
9135 (const_string "single") (const_string "double")))
9136 (set_attr "needs_delay_slot" "yes")])
9138 (define_insn "call_compact_rettramp"
9139 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9140 (match_operand 1 "" ""))
9141 (match_operand 2 "immediate_operand" "n")
9142 (use (reg:SI R0_REG))
9143 (use (reg:SI R1_REG))
9144 (use (reg:SI FPSCR_MODES_REG))
9145 (clobber (reg:SI R10_REG))
9146 (clobber (reg:SI PR_REG))]
9147 "TARGET_SHCOMPACT && (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
9149 [(set_attr "type" "call")
9150 (set (attr "fp_mode")
9151 (if_then_else (eq_attr "fpu_single" "yes")
9152 (const_string "single") (const_string "double")))
9153 (set_attr "needs_delay_slot" "yes")])
9155 (define_insn "call_media"
9156 [(call (mem:DI (match_operand 0 "target_reg_operand" "b"))
9157 (match_operand 1 "" ""))
9158 (clobber (reg:DI PR_MEDIA_REG))]
9161 [(set_attr "type" "jump_media")])
9163 (define_insn "call_valuei"
9164 [(set (match_operand 0 "" "=rf")
9165 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9166 (match_operand 2 "" "")))
9167 (use (reg:SI FPSCR_MODES_REG))
9168 (clobber (reg:SI PR_REG))]
9171 if (TARGET_SH2A && (dbr_sequence_length () == 0))
9176 [(set_attr "type" "call")
9177 (set (attr "fp_mode")
9178 (if_then_else (eq_attr "fpu_single" "yes")
9179 (const_string "single") (const_string "double")))
9180 (set_attr "needs_delay_slot" "yes")
9181 (set_attr "fp_set" "unknown")])
9183 ;; This is TBR relative jump instruction for SH2A architecture.
9184 ;; Its use is enabled by assigning an attribute "function_vector"
9185 ;; and the vector number to a function during its declaration.
9186 (define_insn "call_valuei_tbr_rel"
9187 [(set (match_operand 0 "" "=rf")
9188 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
9189 (match_operand 2 "" "")))
9190 (use (reg:SI FPSCR_MODES_REG))
9191 (clobber (reg:SI PR_REG))]
9192 "TARGET_SH2A && sh2a_is_function_vector_call (operands[1])"
9194 unsigned HOST_WIDE_INT vect_num;
9195 vect_num = sh2a_get_function_vector_number (operands[1]);
9196 operands[3] = GEN_INT (vect_num * 4);
9198 return "jsr/n @@(%O3,tbr)";
9200 [(set_attr "type" "call")
9201 (set (attr "fp_mode")
9202 (if_then_else (eq_attr "fpu_single" "yes")
9203 (const_string "single") (const_string "double")))
9204 (set_attr "needs_delay_slot" "no")
9205 (set_attr "fp_set" "unknown")])
9207 (define_insn "call_valuei_pcrel"
9208 [(set (match_operand 0 "" "=rf")
9209 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9210 (match_operand 2 "" "")))
9211 (use (reg:SI FPSCR_MODES_REG))
9212 (use (reg:SI PIC_REG))
9213 (use (match_operand 3 "" ""))
9214 (clobber (reg:SI PR_REG))]
9217 return "bsrf %1" "\n"
9220 [(set_attr "type" "call")
9221 (set (attr "fp_mode")
9222 (if_then_else (eq_attr "fpu_single" "yes")
9223 (const_string "single") (const_string "double")))
9224 (set_attr "needs_delay_slot" "yes")
9225 (set_attr "fp_set" "unknown")])
9227 (define_insn_and_split "call_value_pcrel"
9228 [(set (match_operand 0 "" "=rf")
9229 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
9230 (match_operand 2 "" "")))
9231 (use (reg:SI FPSCR_MODES_REG))
9232 (use (reg:SI PIC_REG))
9233 (clobber (reg:SI PR_REG))
9234 (clobber (match_scratch:SI 3 "=r"))]
9240 rtx lab = PATTERN (gen_call_site ());
9242 if (SYMBOL_REF_LOCAL_P (operands[1]))
9243 emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
9245 emit_insn (gen_symPLT_label2reg (operands[3], operands[1], lab));
9246 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
9247 operands[2], copy_rtx (lab)));
9250 [(set_attr "type" "call")
9251 (set (attr "fp_mode")
9252 (if_then_else (eq_attr "fpu_single" "yes")
9253 (const_string "single") (const_string "double")))
9254 (set_attr "needs_delay_slot" "yes")
9255 (set_attr "fp_set" "unknown")])
9257 (define_insn "call_value_compact"
9258 [(set (match_operand 0 "" "=rf")
9259 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9260 (match_operand 2 "" "")))
9261 (match_operand 3 "immediate_operand" "n")
9262 (use (reg:SI R0_REG))
9263 (use (reg:SI R1_REG))
9264 (use (reg:SI FPSCR_MODES_REG))
9265 (clobber (reg:SI PR_REG))]
9266 "TARGET_SHCOMPACT && ! (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
9268 [(set_attr "type" "call")
9269 (set (attr "fp_mode")
9270 (if_then_else (eq_attr "fpu_single" "yes")
9271 (const_string "single") (const_string "double")))
9272 (set_attr "needs_delay_slot" "yes")])
9274 (define_insn "call_value_compact_rettramp"
9275 [(set (match_operand 0 "" "=rf")
9276 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9277 (match_operand 2 "" "")))
9278 (match_operand 3 "immediate_operand" "n")
9279 (use (reg:SI R0_REG))
9280 (use (reg:SI R1_REG))
9281 (use (reg:SI FPSCR_MODES_REG))
9282 (clobber (reg:SI R10_REG))
9283 (clobber (reg:SI PR_REG))]
9284 "TARGET_SHCOMPACT && (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
9286 [(set_attr "type" "call")
9287 (set (attr "fp_mode")
9288 (if_then_else (eq_attr "fpu_single" "yes")
9289 (const_string "single") (const_string "double")))
9290 (set_attr "needs_delay_slot" "yes")])
9292 (define_insn "call_value_media"
9293 [(set (match_operand 0 "" "=rf")
9294 (call (mem:DI (match_operand 1 "target_reg_operand" "b"))
9295 (match_operand 2 "" "")))
9296 (clobber (reg:DI PR_MEDIA_REG))]
9299 [(set_attr "type" "jump_media")])
9301 (define_expand "call"
9302 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
9303 (match_operand 1 "" ""))
9304 (match_operand 2 "" "")
9305 (use (reg:SI FPSCR_MODES_REG))
9306 (clobber (reg:SI PR_REG))])]
9311 operands[0] = shmedia_prepare_call_address (operands[0], 0);
9312 emit_call_insn (gen_call_media (operands[0], operands[1]));
9315 else if (TARGET_SHCOMPACT && operands[2] && INTVAL (operands[2]))
9317 rtx cookie_rtx = operands[2];
9318 long cookie = INTVAL (cookie_rtx);
9319 rtx func = XEXP (operands[0], 0);
9324 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9326 rtx reg = gen_reg_rtx (Pmode);
9328 emit_insn (gen_symGOTPLT2reg (reg, func));
9332 func = legitimize_pic_address (func, Pmode, 0);
9335 r0 = gen_rtx_REG (SImode, R0_REG);
9336 r1 = gen_rtx_REG (SImode, R1_REG);
9338 /* Since such a call function may use all call-clobbered
9339 registers, we force a mode switch earlier, so that we don't
9340 run out of registers when adjusting fpscr for the call. */
9341 emit_insn (gen_force_mode_for_call ());
9344 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9345 operands[0] = force_reg (SImode, operands[0]);
9347 emit_move_insn (r0, func);
9348 emit_move_insn (r1, cookie_rtx);
9350 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9351 emit_call_insn (gen_call_compact_rettramp (operands[0], operands[1],
9354 emit_call_insn (gen_call_compact (operands[0], operands[1],
9359 else if (TARGET_SHCOMPACT && flag_pic
9360 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
9361 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
9363 rtx reg = gen_reg_rtx (Pmode);
9365 emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[0], 0)));
9366 XEXP (operands[0], 0) = reg;
9368 if (!flag_pic && TARGET_SH2A
9369 && MEM_P (operands[0])
9370 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
9372 if (sh2a_is_function_vector_call (XEXP (operands[0], 0)))
9374 emit_call_insn (gen_calli_tbr_rel (XEXP (operands[0], 0),
9379 if (flag_pic && TARGET_SH2
9380 && MEM_P (operands[0])
9381 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
9383 emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1]));
9388 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
9389 operands[1] = operands[2];
9392 emit_call_insn (gen_calli (operands[0], operands[1]));
9396 (define_insn "call_pop_compact"
9397 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9398 (match_operand 1 "" ""))
9399 (match_operand 2 "immediate_operand" "n")
9400 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9401 (match_operand 3 "immediate_operand" "n")))
9402 (use (reg:SI R0_REG))
9403 (use (reg:SI R1_REG))
9404 (use (reg:SI FPSCR_MODES_REG))
9405 (clobber (reg:SI PR_REG))]
9406 "TARGET_SHCOMPACT && ! (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
9408 [(set_attr "type" "call")
9409 (set (attr "fp_mode")
9410 (if_then_else (eq_attr "fpu_single" "yes")
9411 (const_string "single") (const_string "double")))
9412 (set_attr "needs_delay_slot" "yes")])
9414 (define_insn "call_pop_compact_rettramp"
9415 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9416 (match_operand 1 "" ""))
9417 (match_operand 2 "immediate_operand" "n")
9418 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9419 (match_operand 3 "immediate_operand" "n")))
9420 (use (reg:SI R0_REG))
9421 (use (reg:SI R1_REG))
9422 (use (reg:SI FPSCR_MODES_REG))
9423 (clobber (reg:SI R10_REG))
9424 (clobber (reg:SI PR_REG))]
9425 "TARGET_SHCOMPACT && (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
9427 [(set_attr "type" "call")
9428 (set (attr "fp_mode")
9429 (if_then_else (eq_attr "fpu_single" "yes")
9430 (const_string "single") (const_string "double")))
9431 (set_attr "needs_delay_slot" "yes")])
9433 (define_expand "call_pop"
9434 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
9435 (match_operand 1 "" ""))
9436 (match_operand 2 "" "")
9437 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9438 (match_operand 3 "" "")))])]
9446 gcc_assert (operands[2] && INTVAL (operands[2]));
9447 cookie_rtx = operands[2];
9448 cookie = INTVAL (cookie_rtx);
9449 func = XEXP (operands[0], 0);
9453 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9455 rtx reg = gen_reg_rtx (Pmode);
9456 emit_insn (gen_symGOTPLT2reg (reg, func));
9460 func = legitimize_pic_address (func, Pmode, 0);
9463 r0 = gen_rtx_REG (SImode, R0_REG);
9464 r1 = gen_rtx_REG (SImode, R1_REG);
9466 /* Since such a call function may use all call-clobbered
9467 registers, we force a mode switch earlier, so that we don't
9468 run out of registers when adjusting fpscr for the call. */
9469 emit_insn (gen_force_mode_for_call ());
9471 operands[0] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
9473 operands[0] = force_reg (SImode, operands[0]);
9475 emit_move_insn (r0, func);
9476 emit_move_insn (r1, cookie_rtx);
9478 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9479 emit_call_insn (gen_call_pop_compact_rettramp
9480 (operands[0], operands[1], operands[2], operands[3]));
9482 emit_call_insn (gen_call_pop_compact
9483 (operands[0], operands[1], operands[2], operands[3]));
9488 (define_expand "call_value"
9489 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
9490 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
9491 (match_operand 2 "" "")))
9492 (match_operand 3 "" "")
9493 (use (reg:SI FPSCR_MODES_REG))
9494 (clobber (reg:SI PR_REG))])]
9499 operands[1] = shmedia_prepare_call_address (operands[1], 0);
9500 emit_call_insn (gen_call_value_media (operands[0], operands[1],
9504 else if (TARGET_SHCOMPACT && operands[3] && INTVAL (operands[3]))
9506 rtx cookie_rtx = operands[3];
9507 long cookie = INTVAL (cookie_rtx);
9508 rtx func = XEXP (operands[1], 0);
9513 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9515 rtx reg = gen_reg_rtx (Pmode);
9517 emit_insn (gen_symGOTPLT2reg (reg, func));
9521 func = legitimize_pic_address (func, Pmode, 0);
9524 r0 = gen_rtx_REG (SImode, R0_REG);
9525 r1 = gen_rtx_REG (SImode, R1_REG);
9527 /* Since such a call function may use all call-clobbered
9528 registers, we force a mode switch earlier, so that we don't
9529 run out of registers when adjusting fpscr for the call. */
9530 emit_insn (gen_force_mode_for_call ());
9533 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9534 operands[1] = force_reg (SImode, operands[1]);
9536 emit_move_insn (r0, func);
9537 emit_move_insn (r1, cookie_rtx);
9539 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9540 emit_call_insn (gen_call_value_compact_rettramp (operands[0],
9545 emit_call_insn (gen_call_value_compact (operands[0], operands[1],
9546 operands[2], operands[3]));
9550 else if (TARGET_SHCOMPACT && flag_pic
9551 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
9552 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
9554 rtx reg = gen_reg_rtx (Pmode);
9556 emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[1], 0)));
9557 XEXP (operands[1], 0) = reg;
9559 if (!flag_pic && TARGET_SH2A
9560 && MEM_P (operands[1])
9561 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
9563 if (sh2a_is_function_vector_call (XEXP (operands[1], 0)))
9565 emit_call_insn (gen_call_valuei_tbr_rel (operands[0],
9566 XEXP (operands[1], 0), operands[2]));
9570 if (flag_pic && TARGET_SH2
9571 && MEM_P (operands[1])
9572 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
9574 emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0),
9579 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
9581 emit_call_insn (gen_call_valuei (operands[0], operands[1], operands[2]));
9585 (define_insn "sibcalli"
9586 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
9587 (match_operand 1 "" ""))
9588 (use (reg:SI FPSCR_MODES_REG))
9592 [(set_attr "needs_delay_slot" "yes")
9593 (set (attr "fp_mode")
9594 (if_then_else (eq_attr "fpu_single" "yes")
9595 (const_string "single") (const_string "double")))
9596 (set_attr "type" "jump_ind")])
9598 (define_insn "sibcalli_pcrel"
9599 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
9600 (match_operand 1 "" ""))
9601 (use (match_operand 2 "" ""))
9602 (use (reg:SI FPSCR_MODES_REG))
9606 return "braf %0" "\n"
9609 [(set_attr "needs_delay_slot" "yes")
9610 (set (attr "fp_mode")
9611 (if_then_else (eq_attr "fpu_single" "yes")
9612 (const_string "single") (const_string "double")))
9613 (set_attr "type" "jump_ind")])
9615 ;; This uses an unspec to describe that the symbol_ref is very close.
9616 (define_insn "sibcalli_thunk"
9617 [(call (mem:SI (unspec:SI [(match_operand:SI 0 "symbol_ref_operand" "")]
9619 (match_operand 1 "" ""))
9620 (use (reg:SI FPSCR_MODES_REG))
9624 [(set_attr "needs_delay_slot" "yes")
9625 (set (attr "fp_mode")
9626 (if_then_else (eq_attr "fpu_single" "yes")
9627 (const_string "single") (const_string "double")))
9628 (set_attr "type" "jump")
9629 (set_attr "length" "2")])
9631 (define_insn_and_split "sibcall_pcrel"
9632 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
9633 (match_operand 1 "" ""))
9634 (use (reg:SI FPSCR_MODES_REG))
9635 (clobber (match_scratch:SI 2 "=k"))
9642 rtx lab = PATTERN (gen_call_site ());
9645 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
9646 call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
9648 SIBLING_CALL_P (call_insn) = 1;
9651 [(set_attr "needs_delay_slot" "yes")
9652 (set (attr "fp_mode")
9653 (if_then_else (eq_attr "fpu_single" "yes")
9654 (const_string "single") (const_string "double")))
9655 (set_attr "type" "jump_ind")])
9657 (define_insn "sibcall_compact"
9658 [(call (mem:SI (match_operand:SI 0 "register_operand" "k,k"))
9659 (match_operand 1 "" ""))
9661 (use (match_operand:SI 2 "register_operand" "z,x"))
9662 (use (reg:SI R1_REG))
9663 (use (reg:SI FPSCR_MODES_REG))
9664 ;; We want to make sure the `x' above will only match MACH_REG
9665 ;; because sibcall_epilogue may clobber MACL_REG.
9666 (clobber (reg:SI MACL_REG))]
9669 static const char* alt[] =
9676 return alt[which_alternative];
9678 [(set_attr "needs_delay_slot" "yes,no")
9679 (set_attr "length" "2,4")
9680 (set (attr "fp_mode") (const_string "single"))
9681 (set_attr "type" "jump_ind")])
9683 (define_insn "sibcall_media"
9684 [(call (mem:DI (match_operand 0 "target_reg_operand" "k"))
9685 (match_operand 1 "" ""))
9686 (use (reg:SI PR_MEDIA_REG))
9690 [(set_attr "type" "jump_media")])
9692 (define_expand "sibcall"
9694 [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
9695 (match_operand 1 "" ""))
9696 (match_operand 2 "" "")
9697 (use (reg:SI FPSCR_MODES_REG))
9703 operands[0] = shmedia_prepare_call_address (operands[0], 1);
9704 emit_call_insn (gen_sibcall_media (operands[0], operands[1]));
9707 else if (TARGET_SHCOMPACT && operands[2]
9708 && (INTVAL (operands[2]) & ~ CALL_COOKIE_RET_TRAMP (1)))
9710 rtx cookie_rtx = operands[2];
9711 long cookie = INTVAL (cookie_rtx);
9712 rtx func = XEXP (operands[0], 0);
9717 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9719 rtx reg = gen_reg_rtx (Pmode);
9721 emit_insn (gen_symGOT2reg (reg, func));
9725 func = legitimize_pic_address (func, Pmode, 0);
9728 /* FIXME: if we could tell whether all argument registers are
9729 already taken, we could decide whether to force the use of
9730 MACH_REG or to stick to R0_REG. Unfortunately, there's no
9731 simple way to tell. We could use the CALL_COOKIE, but we
9732 can't currently tell a register used for regular argument
9733 passing from one that is unused. If we leave it up to reload
9734 to decide which register to use, it seems to always choose
9735 R0_REG, which leaves no available registers in SIBCALL_REGS
9736 to hold the address of the trampoline. */
9737 mach = gen_rtx_REG (SImode, MACH_REG);
9738 r1 = gen_rtx_REG (SImode, R1_REG);
9740 /* Since such a call function may use all call-clobbered
9741 registers, we force a mode switch earlier, so that we don't
9742 run out of registers when adjusting fpscr for the call. */
9743 emit_insn (gen_force_mode_for_call ());
9746 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9747 operands[0] = force_reg (SImode, operands[0]);
9749 /* We don't need a return trampoline, since the callee will
9750 return directly to the upper caller. */
9751 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9753 cookie &= ~ CALL_COOKIE_RET_TRAMP (1);
9754 cookie_rtx = GEN_INT (cookie);
9757 emit_move_insn (mach, func);
9758 emit_move_insn (r1, cookie_rtx);
9760 emit_call_insn (gen_sibcall_compact (operands[0], operands[1], mach));
9763 else if (TARGET_SHCOMPACT && flag_pic
9764 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
9765 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
9767 rtx reg = gen_reg_rtx (Pmode);
9769 emit_insn (gen_symGOT2reg (reg, XEXP (operands[0], 0)));
9770 XEXP (operands[0], 0) = reg;
9772 if (flag_pic && TARGET_SH2
9773 && MEM_P (operands[0])
9774 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
9775 /* The PLT needs the PIC register, but the epilogue would have
9776 to restore it, so we can only use PC-relative PIC calls for
9777 static functions. */
9778 && SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
9780 emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
9784 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
9786 emit_call_insn (gen_sibcalli (operands[0], operands[1]));
9790 (define_insn "sibcall_valuei"
9791 [(set (match_operand 0 "" "=rf")
9792 (call (mem:SI (match_operand:SI 1 "register_operand" "k"))
9793 (match_operand 2 "" "")))
9794 (use (reg:SI FPSCR_MODES_REG))
9798 [(set_attr "needs_delay_slot" "yes")
9799 (set (attr "fp_mode")
9800 (if_then_else (eq_attr "fpu_single" "yes")
9801 (const_string "single") (const_string "double")))
9802 (set_attr "type" "jump_ind")])
9804 (define_insn "sibcall_valuei_pcrel"
9805 [(set (match_operand 0 "" "=rf")
9806 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k"))
9807 (match_operand 2 "" "")))
9808 (use (match_operand 3 "" ""))
9809 (use (reg:SI FPSCR_MODES_REG))
9813 return "braf %1" "\n"
9816 [(set_attr "needs_delay_slot" "yes")
9817 (set (attr "fp_mode")
9818 (if_then_else (eq_attr "fpu_single" "yes")
9819 (const_string "single") (const_string "double")))
9820 (set_attr "type" "jump_ind")])
9822 (define_insn_and_split "sibcall_value_pcrel"
9823 [(set (match_operand 0 "" "=rf")
9824 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
9825 (match_operand 2 "" "")))
9826 (use (reg:SI FPSCR_MODES_REG))
9827 (clobber (match_scratch:SI 3 "=k"))
9834 rtx lab = PATTERN (gen_call_site ());
9837 emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
9838 call_insn = emit_call_insn (gen_sibcall_valuei_pcrel (operands[0],
9842 SIBLING_CALL_P (call_insn) = 1;
9845 [(set_attr "needs_delay_slot" "yes")
9846 (set (attr "fp_mode")
9847 (if_then_else (eq_attr "fpu_single" "yes")
9848 (const_string "single") (const_string "double")))
9849 (set_attr "type" "jump_ind")])
9851 (define_insn "sibcall_value_compact"
9852 [(set (match_operand 0 "" "=rf,rf")
9853 (call (mem:SI (match_operand:SI 1 "register_operand" "k,k"))
9854 (match_operand 2 "" "")))
9856 (use (match_operand:SI 3 "register_operand" "z,x"))
9857 (use (reg:SI R1_REG))
9858 (use (reg:SI FPSCR_MODES_REG))
9859 ;; We want to make sure the `x' above will only match MACH_REG
9860 ;; because sibcall_epilogue may clobber MACL_REG.
9861 (clobber (reg:SI MACL_REG))]
9864 static const char* alt[] =
9871 return alt[which_alternative];
9873 [(set_attr "needs_delay_slot" "yes,no")
9874 (set_attr "length" "2,4")
9875 (set (attr "fp_mode") (const_string "single"))
9876 (set_attr "type" "jump_ind")])
9878 (define_insn "sibcall_value_media"
9879 [(set (match_operand 0 "" "=rf")
9880 (call (mem:DI (match_operand 1 "target_reg_operand" "k"))
9881 (match_operand 2 "" "")))
9882 (use (reg:SI PR_MEDIA_REG))
9886 [(set_attr "type" "jump_media")])
9888 (define_expand "sibcall_value"
9890 [(set (match_operand 0 "arith_reg_operand" "")
9891 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
9892 (match_operand 2 "" "")))
9893 (match_operand 3 "" "")
9894 (use (reg:SI FPSCR_MODES_REG))
9900 operands[1] = shmedia_prepare_call_address (operands[1], 1);
9901 emit_call_insn (gen_sibcall_value_media (operands[0], operands[1],
9905 else if (TARGET_SHCOMPACT && operands[3]
9906 && (INTVAL (operands[3]) & ~ CALL_COOKIE_RET_TRAMP (1)))
9908 rtx cookie_rtx = operands[3];
9909 long cookie = INTVAL (cookie_rtx);
9910 rtx func = XEXP (operands[1], 0);
9915 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9917 rtx reg = gen_reg_rtx (Pmode);
9919 emit_insn (gen_symGOT2reg (reg, func));
9923 func = legitimize_pic_address (func, Pmode, 0);
9926 /* FIXME: if we could tell whether all argument registers are
9927 already taken, we could decide whether to force the use of
9928 MACH_REG or to stick to R0_REG. Unfortunately, there's no
9929 simple way to tell. We could use the CALL_COOKIE, but we
9930 can't currently tell a register used for regular argument
9931 passing from one that is unused. If we leave it up to reload
9932 to decide which register to use, it seems to always choose
9933 R0_REG, which leaves no available registers in SIBCALL_REGS
9934 to hold the address of the trampoline. */
9935 mach = gen_rtx_REG (SImode, MACH_REG);
9936 r1 = gen_rtx_REG (SImode, R1_REG);
9938 /* Since such a call function may use all call-clobbered
9939 registers, we force a mode switch earlier, so that we don't
9940 run out of registers when adjusting fpscr for the call. */
9941 emit_insn (gen_force_mode_for_call ());
9944 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9945 operands[1] = force_reg (SImode, operands[1]);
9947 /* We don't need a return trampoline, since the callee will
9948 return directly to the upper caller. */
9949 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9951 cookie &= ~ CALL_COOKIE_RET_TRAMP (1);
9952 cookie_rtx = GEN_INT (cookie);
9955 emit_move_insn (mach, func);
9956 emit_move_insn (r1, cookie_rtx);
9958 emit_call_insn (gen_sibcall_value_compact (operands[0], operands[1],
9959 operands[2], mach));
9962 else if (TARGET_SHCOMPACT && flag_pic
9963 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
9964 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
9966 rtx reg = gen_reg_rtx (Pmode);
9968 emit_insn (gen_symGOT2reg (reg, XEXP (operands[1], 0)));
9969 XEXP (operands[1], 0) = reg;
9971 if (flag_pic && TARGET_SH2
9972 && MEM_P (operands[1])
9973 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
9974 /* The PLT needs the PIC register, but the epilogue would have
9975 to restore it, so we can only use PC-relative PIC calls for
9976 static functions. */
9977 && SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
9979 emit_call_insn (gen_sibcall_value_pcrel (operands[0],
9980 XEXP (operands[1], 0),
9985 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
9987 emit_call_insn (gen_sibcall_valuei (operands[0], operands[1], operands[2]));
9991 (define_insn "call_value_pop_compact"
9992 [(set (match_operand 0 "" "=rf")
9993 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9994 (match_operand 2 "" "")))
9995 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9996 (match_operand 4 "immediate_operand" "n")))
9997 (match_operand 3 "immediate_operand" "n")
9998 (use (reg:SI R0_REG))
9999 (use (reg:SI R1_REG))
10000 (use (reg:SI FPSCR_MODES_REG))
10001 (clobber (reg:SI PR_REG))]
10002 "TARGET_SHCOMPACT && ! (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
10004 [(set_attr "type" "call")
10005 (set (attr "fp_mode")
10006 (if_then_else (eq_attr "fpu_single" "yes")
10007 (const_string "single") (const_string "double")))
10008 (set_attr "needs_delay_slot" "yes")])
10010 (define_insn "call_value_pop_compact_rettramp"
10011 [(set (match_operand 0 "" "=rf")
10012 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
10013 (match_operand 2 "" "")))
10014 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
10015 (match_operand 4 "immediate_operand" "n")))
10016 (match_operand 3 "immediate_operand" "n")
10017 (use (reg:SI R0_REG))
10018 (use (reg:SI R1_REG))
10019 (use (reg:SI FPSCR_MODES_REG))
10020 (clobber (reg:SI R10_REG))
10021 (clobber (reg:SI PR_REG))]
10022 "TARGET_SHCOMPACT && (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
10024 [(set_attr "type" "call")
10025 (set (attr "fp_mode")
10026 (if_then_else (eq_attr "fpu_single" "yes")
10027 (const_string "single") (const_string "double")))
10028 (set_attr "needs_delay_slot" "yes")])
10030 (define_expand "call_value_pop"
10031 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
10032 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
10033 (match_operand 2 "" "")))
10034 (match_operand 3 "" "")
10035 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
10036 (match_operand 4 "" "")))])]
10044 gcc_assert (TARGET_SHCOMPACT && operands[3] && INTVAL (operands[3]));
10045 cookie_rtx = operands[3];
10046 cookie = INTVAL (cookie_rtx);
10047 func = XEXP (operands[1], 0);
10051 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
10053 rtx reg = gen_reg_rtx (Pmode);
10055 emit_insn (gen_symGOTPLT2reg (reg, func));
10059 func = legitimize_pic_address (func, Pmode, 0);
10062 r0 = gen_rtx_REG (SImode, R0_REG);
10063 r1 = gen_rtx_REG (SImode, R1_REG);
10065 /* Since such a call function may use all call-clobbered
10066 registers, we force a mode switch earlier, so that we don't
10067 run out of registers when adjusting fpscr for the call. */
10068 emit_insn (gen_force_mode_for_call ());
10070 operands[1] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
10072 operands[1] = force_reg (SImode, operands[1]);
10074 emit_move_insn (r0, func);
10075 emit_move_insn (r1, cookie_rtx);
10077 if (cookie & CALL_COOKIE_RET_TRAMP (1))
10078 emit_call_insn (gen_call_value_pop_compact_rettramp
10079 (operands[0], operands[1], operands[2],
10080 operands[3], operands[4]));
10082 emit_call_insn (gen_call_value_pop_compact
10083 (operands[0], operands[1], operands[2],
10084 operands[3], operands[4]));
10089 (define_expand "sibcall_epilogue"
10093 sh_expand_epilogue (true);
10094 if (TARGET_SHCOMPACT)
10099 /* If epilogue clobbers r0, preserve it in macl. */
10100 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10101 if ((set = single_set (insn))
10102 && REG_P (SET_DEST (set))
10103 && REGNO (SET_DEST (set)) == R0_REG)
10105 rtx r0 = gen_rtx_REG (SImode, R0_REG);
10106 rtx tmp = gen_rtx_REG (SImode, MACL_REG);
10108 /* We can't tell at this point whether the sibcall is a
10109 sibcall_compact and, if it is, whether it uses r0 or
10110 mach as operand 2, so let the instructions that
10111 preserve r0 be optimized away if r0 turns out to be
10113 emit_insn_before (gen_rtx_SET (SImode, tmp, r0), insn);
10114 emit_move_insn (r0, tmp);
10121 (define_insn "indirect_jump_compact"
10123 (match_operand:SI 0 "arith_reg_operand" "r"))]
10126 [(set_attr "needs_delay_slot" "yes")
10127 (set_attr "type" "jump_ind")])
10129 (define_expand "indirect_jump"
10131 (match_operand 0 "register_operand" ""))]
10134 if (GET_MODE (operands[0]) != Pmode)
10135 operands[0] = gen_rtx_SUBREG (Pmode, operands[0], 0);
10138 ;; The use of operand 1 / 2 helps us distinguish case table jumps
10139 ;; which can be present in structured code from indirect jumps which can not
10140 ;; be present in structured code. This allows -fprofile-arcs to work.
10142 ;; For SH1 processors.
10143 (define_insn "casesi_jump_1"
10145 (match_operand:SI 0 "register_operand" "r"))
10146 (use (label_ref (match_operand 1 "" "")))]
10149 [(set_attr "needs_delay_slot" "yes")
10150 (set_attr "type" "jump_ind")])
10152 ;; For all later processors.
10153 (define_insn "casesi_jump_2"
10154 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
10155 (label_ref (match_operand 1 "" ""))))
10156 (use (label_ref (match_operand 2 "" "")))]
10158 && (! INSN_UID (operands[1]) || prev_real_insn (operands[1]) == insn)"
10160 [(set_attr "needs_delay_slot" "yes")
10161 (set_attr "type" "jump_ind")])
10163 (define_insn "casesi_jump_media"
10164 [(set (pc) (match_operand 0 "target_reg_operand" "b"))
10165 (use (label_ref (match_operand 1 "" "")))]
10168 [(set_attr "type" "jump_media")])
10170 ;; Call subroutine returning any type.
10171 ;; ??? This probably doesn't work.
10172 (define_expand "untyped_call"
10173 [(parallel [(call (match_operand 0 "" "")
10175 (match_operand 1 "" "")
10176 (match_operand 2 "" "")])]
10177 "(TARGET_SH2E || TARGET_SH2A) || TARGET_SHMEDIA"
10179 if (! TARGET_SHMEDIA)
10181 /* RA does not know that the call sets the function value registers.
10182 We avoid problems by claiming that those registers are clobbered
10184 for (int i = 0; i < XVECLEN (operands[2], 0); i++)
10186 rtx set = XVECEXP (operands[2], 0, i);
10187 emit_clobber (SET_SRC (set));
10191 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
10193 for (int i = 0; i < XVECLEN (operands[2], 0); i++)
10195 rtx set = XVECEXP (operands[2], 0, i);
10196 emit_move_insn (SET_DEST (set), SET_SRC (set));
10199 /* The optimizer does not know that the call sets the function value
10200 registers we stored in the result block. We avoid problems by
10201 claiming that all hard registers are used and clobbered at this
10203 emit_insn (gen_blockage ());
10208 ;; ------------------------------------------------------------------------
10210 ;; ------------------------------------------------------------------------
10212 (define_insn "dect"
10213 [(set (reg:SI T_REG)
10214 (eq:SI (match_operand:SI 1 "arith_reg_dest" "0") (const_int 1)))
10215 (set (match_operand:SI 0 "arith_reg_dest" "=r")
10216 (plus:SI (match_dup 1) (const_int -1)))]
10219 [(set_attr "type" "arith")])
10226 ;; Load address of a label. This is only generated by the casesi expand,
10227 ;; and by machine_dependent_reorg (fixing up fp moves).
10228 ;; This must use unspec, because this only works for labels that are
10230 (define_insn "mova"
10231 [(set (reg:SI R0_REG)
10232 (unspec:SI [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
10235 [(set_attr "in_delay_slot" "no")
10236 (set_attr "type" "arith")])
10238 ;; machine_dependent_reorg will make this a `mova'.
10239 (define_insn "mova_const"
10240 [(set (reg:SI R0_REG)
10241 (unspec:SI [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
10244 [(set_attr "in_delay_slot" "no")
10245 (set_attr "type" "arith")])
10247 (define_expand "GOTaddr2picreg"
10248 [(set (reg:SI R0_REG)
10249 (unspec:SI [(const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC))]
10251 (set (match_dup 0) (const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC)))
10252 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
10255 if (TARGET_VXWORKS_RTP)
10257 rtx gott_base = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE);
10258 rtx gott_index = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
10259 emit_insn (gen_vxworks_picreg (gott_base, gott_index));
10263 operands[0] = gen_rtx_REG (Pmode, PIC_REG);
10264 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
10266 if (TARGET_SHMEDIA)
10268 rtx tr = gen_rtx_REG (Pmode, TR0_REG);
10269 rtx pic = operands[0];
10270 rtx lab = PATTERN (gen_call_site ());
10273 equiv = operands[1];
10274 operands[1] = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, operands[1], lab),
10275 UNSPEC_PCREL_SYMOFF);
10276 operands[1] = gen_rtx_CONST (Pmode, operands[1]);
10278 if (Pmode == SImode)
10280 emit_insn (gen_movsi_const (pic, operands[1]));
10281 emit_insn (gen_ptrel_si (tr, pic, copy_rtx (lab)));
10285 emit_insn (gen_movdi_const (pic, operands[1]));
10286 emit_insn (gen_ptrel_di (tr, pic, copy_rtx (lab)));
10289 insn = emit_move_insn (operands[0], tr);
10291 set_unique_reg_note (insn, REG_EQUAL, equiv);
10297 ;; A helper for GOTaddr2picreg to finish up the initialization of the
10299 (define_expand "vxworks_picreg"
10300 [(set (reg:SI PIC_REG)
10301 (const:SI (unspec:SI [(match_operand:SI 0 "" "")] UNSPEC_PIC)))
10302 (set (reg:SI R0_REG)
10303 (const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PIC)))
10304 (set (reg:SI PIC_REG)
10305 (mem:SI (reg:SI PIC_REG)))
10306 (set (reg:SI PIC_REG)
10307 (mem:SI (plus:SI (reg:SI PIC_REG)
10308 (reg:SI R0_REG))))]
10309 "TARGET_VXWORKS_RTP")
10311 (define_insn "*ptb"
10312 [(set (match_operand 0 "target_reg_operand" "=b")
10313 (const (unspec [(match_operand 1 "" "Csy")]
10314 UNSPEC_DATALABEL)))]
10315 "TARGET_SHMEDIA && flag_pic
10316 && satisfies_constraint_Csy (operands[1])"
10317 "ptb/u datalabel %1, %0"
10318 [(set_attr "type" "ptabs_media")
10319 (set_attr "length" "*")])
10321 (define_insn "ptrel_si"
10322 [(set (match_operand:SI 0 "target_reg_operand" "=b")
10323 (plus:SI (match_operand:SI 1 "register_operand" "r")
10325 (match_operand:SI 2 "" "")]
10327 "%O2: ptrel/u %1, %0"
10328 [(set_attr "type" "ptabs_media")])
10330 (define_insn "ptrel_di"
10331 [(set (match_operand:DI 0 "target_reg_operand" "=b")
10332 (plus:DI (match_operand:DI 1 "register_operand" "r")
10334 (match_operand:DI 2 "" "")]
10336 "%O2: ptrel/u %1, %0"
10337 [(set_attr "type" "ptabs_media")])
10339 (define_expand "builtin_setjmp_receiver"
10340 [(match_operand 0 "" "")]
10343 emit_insn (gen_GOTaddr2picreg ());
10347 (define_expand "call_site"
10348 [(unspec [(match_dup 0)] UNSPEC_CALLER)]
10351 static HOST_WIDE_INT i = 0;
10352 operands[0] = GEN_INT (i);
10356 ;; op0 = op1 + r12 but hide it before reload completed. See the comment
10357 ;; in symGOT_load expand.
10358 (define_insn_and_split "chk_guard_add"
10359 [(set (match_operand:SI 0 "register_operand" "=&r")
10360 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
10365 "TARGET_SH1 && reload_completed"
10366 [(set (match_dup 0) (reg:SI PIC_REG))
10367 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
10369 [(set_attr "type" "arith")])
10371 (define_expand "sym_label2reg"
10372 [(set (match_operand:SI 0 "" "")
10373 (const:SI (unspec:SI [(match_operand:SI 1 "" "")
10374 (const (plus:SI (match_operand:SI 2 "" "")
10379 (define_expand "symGOT_load"
10380 [(set (match_dup 2) (match_operand 1 "" ""))
10381 (set (match_dup 3) (plus (match_dup 2) (reg PIC_REG)))
10382 (set (match_operand 0 "" "") (mem (match_dup 3)))]
10387 operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
10388 operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
10390 if (TARGET_SHMEDIA)
10392 rtx reg = operands[2];
10394 if (Pmode == DImode)
10397 emit_insn (gen_movdi_const_32bit (reg, operands[1]));
10399 emit_insn (gen_movdi_const_16bit (reg, operands[1]));
10404 emit_insn (gen_movsi_const (reg, operands[1]));
10406 emit_insn (gen_movsi_const_16bit (reg, operands[1]));
10410 emit_move_insn (operands[2], operands[1]);
10412 /* When stack protector inserts codes after the result is set to
10413 R0, @(rX, r12) will cause a spill failure for R0. Use a unspec
10414 insn to avoid combining (set A (plus rX r12)) and (set op0 (mem A))
10415 when rX is a GOT address for the guard symbol. Ugly but doesn't
10416 matter because this is a rare situation. */
10417 if (!TARGET_SHMEDIA
10418 && flag_stack_protect
10419 && GET_CODE (operands[1]) == CONST
10420 && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
10421 && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == SYMBOL_REF
10422 && strcmp (XSTR (XVECEXP (XEXP (operands[1], 0), 0, 0), 0),
10423 "__stack_chk_guard") == 0)
10424 emit_insn (gen_chk_guard_add (operands[3], operands[2]));
10426 emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2],
10427 gen_rtx_REG (Pmode, PIC_REG)));
10429 /* N.B. This is not constant for a GOTPLT relocation. */
10430 mem = gen_rtx_MEM (Pmode, operands[3]);
10431 MEM_NOTRAP_P (mem) = 1;
10432 /* ??? Should we have a special alias set for the GOT? */
10433 emit_move_insn (operands[0], mem);
10438 (define_expand "sym2GOT"
10439 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOT))]
10443 (define_expand "symGOT2reg"
10444 [(match_operand 0 "" "") (match_operand 1 "" "")]
10449 gotsym = gen_sym2GOT (operands[1]);
10450 PUT_MODE (gotsym, Pmode);
10451 insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
10453 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
10458 (define_expand "symGOTPLT2reg"
10459 [(match_operand 0 "" "") (match_operand 1 "" "")]
10462 rtx pltsym = gen_rtx_CONST (Pmode,
10463 gen_rtx_UNSPEC (Pmode,
10464 gen_rtvec (1, operands[1]),
10466 emit_insn (gen_symGOT_load (operands[0], pltsym));
10470 (define_expand "sym2GOTOFF"
10471 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTOFF))]
10475 (define_expand "symGOTOFF2reg"
10476 [(match_operand 0 "" "") (match_operand 1 "" "")]
10479 rtx gotoffsym, insn;
10480 rtx t = (!can_create_pseudo_p ()
10482 : gen_reg_rtx (GET_MODE (operands[0])));
10484 gotoffsym = gen_sym2GOTOFF (operands[1]);
10485 PUT_MODE (gotoffsym, Pmode);
10486 emit_move_insn (t, gotoffsym);
10487 insn = emit_move_insn (operands[0],
10488 gen_rtx_PLUS (Pmode, t,
10489 gen_rtx_REG (Pmode, PIC_REG)));
10491 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
10496 (define_expand "symPLT_label2reg"
10497 [(set (match_operand:SI 0 "" "")
10500 [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PLT))
10501 (const:SI (plus:SI (match_operand:SI 2 "" "")
10502 (const_int 2)))] UNSPEC_PCREL_SYMOFF)))
10503 ;; Even though the PIC register is not really used by the call
10504 ;; sequence in which this is expanded, the PLT code assumes the PIC
10505 ;; register is set, so we must not skip its initialization. Since
10506 ;; we only use this expand as part of calling sequences, and never
10507 ;; to take the address of a function, this is the best point to
10508 ;; insert the (use). Using the PLT to take the address of a
10509 ;; function would be wrong, not only because the PLT entry could
10510 ;; then be called from a function that doesn't initialize the PIC
10511 ;; register to the proper GOT, but also because pointers to the
10512 ;; same function might not compare equal, should they be set by
10513 ;; different shared libraries.
10514 (use (reg:SI PIC_REG))]
10518 (define_expand "sym2PIC"
10519 [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_PIC))]
10523 ;; -------------------------------------------------------------------------
10524 ;; TLS code generation.
10526 ;; FIXME: The multi-insn asm blocks should be converted to use
10527 ;; define_insn_and_split.
10528 ;; See the thread [PATCH/RFA] SH TLS support on gcc-patches
10529 ;; <http://gcc.gnu.org/ml/gcc-patches/2003-02/msg01898.html>
10532 (define_insn "tls_global_dynamic"
10533 [(set (match_operand:SI 0 "register_operand" "=&z")
10534 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
10537 (use (reg:SI FPSCR_MODES_REG))
10538 (use (reg:SI PIC_REG))
10539 (clobber (reg:SI PR_REG))
10540 (clobber (scratch:SI))]
10543 return "mov.l 1f,r4" "\n"
10545 " mov.l 2f,r1" "\n"
10552 "1: .long %a1@TLSGD" "\n"
10553 "2: .long __tls_get_addr@PLT" "\n"
10556 [(set_attr "type" "tls_load")
10557 (set_attr "length" "26")])
10559 (define_insn "tls_local_dynamic"
10560 [(set (match_operand:SI 0 "register_operand" "=&z")
10561 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
10564 (use (reg:SI FPSCR_MODES_REG))
10565 (use (reg:SI PIC_REG))
10566 (clobber (reg:SI PR_REG))
10567 (clobber (scratch:SI))]
10570 return "mov.l 1f,r4" "\n"
10572 " mov.l 2f,r1" "\n"
10579 "1: .long %a1@TLSLDM" "\n"
10580 "2: .long __tls_get_addr@PLT" "\n"
10583 [(set_attr "type" "tls_load")
10584 (set_attr "length" "26")])
10586 (define_expand "sym2DTPOFF"
10587 [(const (unspec [(match_operand 0 "" "")] UNSPEC_DTPOFF))]
10591 (define_expand "symDTPOFF2reg"
10592 [(match_operand 0 "" "") (match_operand 1 "" "") (match_operand 2 "" "")]
10596 rtx t = (!can_create_pseudo_p ()
10598 : gen_reg_rtx (GET_MODE (operands[0])));
10600 dtpoffsym = gen_sym2DTPOFF (operands[1]);
10601 PUT_MODE (dtpoffsym, Pmode);
10602 emit_move_insn (t, dtpoffsym);
10603 emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, operands[2]));
10607 (define_expand "sym2GOTTPOFF"
10608 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTTPOFF))]
10612 (define_insn "tls_initial_exec"
10613 [(set (match_operand:SI 0 "register_operand" "=&r")
10614 (unspec:SI [(match_operand:SI 1 "" "")]
10616 (use (reg:SI GBR_REG))
10617 (use (reg:SI PIC_REG))
10618 (clobber (reg:SI R0_REG))]
10621 return "mov.l 1f,r0" "\n"
10623 " mov.l @(r0,r12),r0" "\n"
10627 "1: .long %a1" "\n"
10630 [(set_attr "type" "tls_load")
10631 (set_attr "length" "16")])
10633 (define_expand "sym2TPOFF"
10634 [(const (unspec [(match_operand 0 "" "")] UNSPEC_TPOFF))]
10638 (define_expand "symTPOFF2reg"
10639 [(match_operand 0 "" "") (match_operand 1 "" "")]
10644 tpoffsym = gen_sym2TPOFF (operands[1]);
10645 PUT_MODE (tpoffsym, Pmode);
10646 emit_move_insn (operands[0], tpoffsym);
10650 ;;------------------------------------------------------------------------------
10651 ;; Thread pointer getter and setter.
10653 ;; On SH the thread pointer is kept in the GBR.
10654 ;; These patterns are usually expanded from the respective built-in functions.
10655 (define_expand "get_thread_pointersi"
10656 [(set (match_operand:SI 0 "register_operand") (reg:SI GBR_REG))]
10659 ;; The store_gbr insn can also be used on !TARGET_SH1 for doing TLS accesses.
10660 (define_insn "store_gbr"
10661 [(set (match_operand:SI 0 "register_operand" "=r") (reg:SI GBR_REG))]
10664 [(set_attr "type" "tls_load")])
10666 (define_expand "set_thread_pointersi"
10667 [(set (reg:SI GBR_REG)
10668 (unspec_volatile:SI [(match_operand:SI 0 "register_operand")]
10672 (define_insn "load_gbr"
10673 [(set (reg:SI GBR_REG)
10674 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
10678 [(set_attr "type" "move")])
10680 ;;------------------------------------------------------------------------------
10681 ;; Thread pointer relative memory loads and stores.
10683 ;; On SH there are GBR displacement address modes which can be utilized to
10684 ;; access memory behind the thread pointer.
10685 ;; Since we do not allow using GBR for general purpose memory accesses, these
10686 ;; GBR addressing modes are formed by the combine pass.
10687 ;; This could be done with fewer patterns than below by using a mem predicate
10688 ;; for the GBR mem, but then reload would try to reload addresses with a
10689 ;; zero displacement for some strange reason.
10691 (define_insn "*mov<mode>_gbr_load"
10692 [(set (match_operand:QIHISI 0 "register_operand" "=z")
10693 (mem:QIHISI (plus:SI (reg:SI GBR_REG)
10694 (match_operand:QIHISI 1 "gbr_displacement"))))]
10696 "mov.<bwl> @(%O1,gbr),%0"
10697 [(set_attr "type" "load")])
10699 (define_insn "*mov<mode>_gbr_load"
10700 [(set (match_operand:QIHISI 0 "register_operand" "=z")
10701 (mem:QIHISI (reg:SI GBR_REG)))]
10703 "mov.<bwl> @(0,gbr),%0"
10704 [(set_attr "type" "load")])
10706 (define_insn "*mov<mode>_gbr_load"
10707 [(set (match_operand:SI 0 "register_operand" "=z")
10709 (mem:QIHI (plus:SI (reg:SI GBR_REG)
10710 (match_operand:QIHI 1 "gbr_displacement")))))]
10712 "mov.<bw> @(%O1,gbr),%0"
10713 [(set_attr "type" "load")])
10715 (define_insn "*mov<mode>_gbr_load"
10716 [(set (match_operand:SI 0 "register_operand" "=z")
10717 (sign_extend:SI (mem:QIHI (reg:SI GBR_REG))))]
10719 "mov.<bw> @(0,gbr),%0"
10720 [(set_attr "type" "load")])
10722 (define_insn "*mov<mode>_gbr_store"
10723 [(set (mem:QIHISI (plus:SI (reg:SI GBR_REG)
10724 (match_operand:QIHISI 0 "gbr_displacement")))
10725 (match_operand:QIHISI 1 "register_operand" "z"))]
10727 "mov.<bwl> %1,@(%O0,gbr)"
10728 [(set_attr "type" "store")])
10730 (define_insn "*mov<mode>_gbr_store"
10731 [(set (mem:QIHISI (reg:SI GBR_REG))
10732 (match_operand:QIHISI 0 "register_operand" "z"))]
10734 "mov.<bwl> %0,@(0,gbr)"
10735 [(set_attr "type" "store")])
10737 ;; DImode memory accesses have to be split in two SImode accesses.
10738 ;; Split them before reload, so that it gets a better chance to figure out
10739 ;; how to deal with the R0 restriction for the individual SImode accesses.
10740 ;; Do not match this insn during or after reload because it can't be split
10742 (define_insn_and_split "*movdi_gbr_load"
10743 [(set (match_operand:DI 0 "register_operand")
10744 (match_operand:DI 1 "gbr_address_mem"))]
10745 "TARGET_SH1 && can_create_pseudo_p ()"
10748 [(set (match_dup 3) (match_dup 5))
10749 (set (match_dup 4) (match_dup 6))]
10751 /* Swap low/high part load order on little endian, so that the result reg
10752 of the second load can be used better. */
10753 int off = TARGET_LITTLE_ENDIAN ? 1 : 0;
10754 operands[3 + off] = gen_lowpart (SImode, operands[0]);
10755 operands[5 + off] = gen_lowpart (SImode, operands[1]);
10756 operands[4 - off] = gen_highpart (SImode, operands[0]);
10757 operands[6 - off] = gen_highpart (SImode, operands[1]);
10760 (define_insn_and_split "*movdi_gbr_store"
10761 [(set (match_operand:DI 0 "gbr_address_mem")
10762 (match_operand:DI 1 "register_operand"))]
10763 "TARGET_SH1 && can_create_pseudo_p ()"
10766 [(set (match_dup 3) (match_dup 5))
10767 (set (match_dup 4) (match_dup 6))]
10769 /* Swap low/high part store order on big endian, so that stores of function
10770 call results can save a reg copy. */
10771 int off = TARGET_LITTLE_ENDIAN ? 0 : 1;
10772 operands[3 + off] = gen_lowpart (SImode, operands[0]);
10773 operands[5 + off] = gen_lowpart (SImode, operands[1]);
10774 operands[4 - off] = gen_highpart (SImode, operands[0]);
10775 operands[6 - off] = gen_highpart (SImode, operands[1]);
10778 ;; Sometimes memory accesses do not get combined with the store_gbr insn,
10779 ;; in particular when the displacements are in the range of the regular move
10780 ;; insns. Thus, in the first split pass after the combine pass we search
10781 ;; for missed opportunities and try to fix them up ourselves.
10782 ;; If an equivalent GBR address can be determined the load / store is split
10783 ;; into one of the GBR load / store patterns.
10784 ;; All of that must happen before reload (GBR address modes use R0 as the
10785 ;; other operand) and there's no point of doing it if the GBR is not
10786 ;; referenced in a function at all.
10788 [(set (match_operand:QIHISIDI 0 "register_operand")
10789 (match_operand:QIHISIDI 1 "memory_operand"))]
10790 "TARGET_SH1 && !reload_in_progress && !reload_completed
10791 && df_regs_ever_live_p (GBR_REG)"
10792 [(set (match_dup 0) (match_dup 1))]
10794 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
10795 if (gbr_mem != NULL_RTX)
10796 operands[1] = replace_equiv_address (operands[1], gbr_mem);
10802 [(set (match_operand:SI 0 "register_operand")
10803 (sign_extend:SI (match_operand:QIHI 1 "memory_operand")))]
10804 "TARGET_SH1 && !reload_in_progress && !reload_completed
10805 && df_regs_ever_live_p (GBR_REG)"
10806 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
10808 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
10809 if (gbr_mem != NULL_RTX)
10810 operands[1] = replace_equiv_address (operands[1], gbr_mem);
10815 ;; On SH2A we've got movu.b and movu.w for doing zero-extending mem loads.
10816 ;; Split those so that a GBR load can be used.
10818 [(set (match_operand:SI 0 "register_operand")
10819 (zero_extend:SI (match_operand:QIHI 1 "memory_operand")))]
10820 "TARGET_SH2A && !reload_in_progress && !reload_completed
10821 && df_regs_ever_live_p (GBR_REG)"
10822 [(set (match_dup 2) (match_dup 1))
10823 (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
10825 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
10826 if (gbr_mem != NULL_RTX)
10828 operands[2] = gen_reg_rtx (GET_MODE (operands[1]));
10829 operands[1] = replace_equiv_address (operands[1], gbr_mem);
10836 [(set (match_operand:QIHISIDI 0 "memory_operand")
10837 (match_operand:QIHISIDI 1 "register_operand"))]
10838 "TARGET_SH1 && !reload_in_progress && !reload_completed
10839 && df_regs_ever_live_p (GBR_REG)"
10840 [(set (match_dup 0) (match_dup 1))]
10842 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[0]);
10843 if (gbr_mem != NULL_RTX)
10844 operands[0] = replace_equiv_address (operands[0], gbr_mem);
10849 ;;------------------------------------------------------------------------------
10850 ;; case instruction for switch statements.
10852 ;; operand 0 is index
10853 ;; operand 1 is the minimum bound
10854 ;; operand 2 is the maximum bound - minimum bound + 1
10855 ;; operand 3 is CODE_LABEL for the table;
10856 ;; operand 4 is the CODE_LABEL to go to if index out of range.
10857 (define_expand "casesi"
10858 [(match_operand:SI 0 "arith_reg_operand" "")
10859 (match_operand:SI 1 "arith_reg_operand" "")
10860 (match_operand:SI 2 "arith_reg_operand" "")
10861 (match_operand 3 "" "") (match_operand 4 "" "")]
10864 rtx reg = gen_reg_rtx (SImode);
10865 rtx reg2 = gen_reg_rtx (SImode);
10866 if (TARGET_SHMEDIA)
10868 rtx reg = gen_reg_rtx (DImode);
10869 rtx reg2 = gen_reg_rtx (DImode);
10870 rtx reg3 = gen_reg_rtx (Pmode);
10871 rtx reg4 = gen_reg_rtx (Pmode);
10872 rtx reg5 = gen_reg_rtx (Pmode);
10875 operands[0] = convert_modes (DImode, SImode, operands[0], 0);
10876 operands[1] = convert_modes (DImode, SImode, operands[1], 0);
10877 operands[2] = convert_modes (DImode, SImode, operands[2], 1);
10879 test = gen_rtx_GT (VOIDmode, operands[1], operands[0]);
10880 emit_jump_insn (gen_cbranchdi4 (test, operands[1], operands[0],
10882 emit_move_insn (reg, gen_rtx_MINUS (DImode, operands[0], operands[1]));
10883 test = gen_rtx_GTU (VOIDmode, reg, operands[2]);
10884 emit_jump_insn (gen_cbranchdi4 (test, reg, operands[2], operands[4]));
10885 emit_insn (gen_casesi_shift_media (reg2, reg, operands[3]));
10886 emit_move_insn (reg3, gen_datalabel_ref (gen_rtx_LABEL_REF
10887 (Pmode, operands[3])));
10888 /* Messy: can we subreg to clean this up? */
10889 if (Pmode == DImode)
10890 load = gen_casesi_load_media (reg4, reg3, reg2, operands[3]);
10892 load = gen_casesi_load_media (reg4,
10893 gen_rtx_SUBREG (DImode, reg3, 0),
10894 reg2, operands[3]);
10895 PUT_MODE (SET_SRC (load), Pmode);
10897 /* ??? The following add could be eliminated if we used ptrel. */
10898 emit_move_insn (reg5, gen_rtx_PLUS (Pmode, reg3, reg4));
10899 emit_jump_insn (gen_casesi_jump_media (reg5, operands[3]));
10903 operands[1] = copy_to_mode_reg (SImode, operands[1]);
10904 operands[2] = copy_to_mode_reg (SImode, operands[2]);
10905 /* If optimizing, casesi_worker depends on the mode of the instruction
10906 before label it 'uses' - operands[3]. */
10907 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
10909 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
10911 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
10913 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
10914 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
10915 operands[3], but to lab. We will fix this up in
10916 machine_dependent_reorg. */
10921 (define_expand "casesi_0"
10922 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
10923 (set (match_dup 4) (minus:SI (match_dup 4)
10924 (match_operand:SI 1 "arith_operand" "")))
10925 (set (reg:SI T_REG)
10926 (gtu:SI (match_dup 4)
10927 (match_operand:SI 2 "arith_reg_operand" "")))
10929 (if_then_else (ne (reg:SI T_REG)
10931 (label_ref (match_operand 3 "" ""))
10936 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
10937 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
10938 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
10939 (define_insn "casesi_worker_0"
10940 [(set (match_operand:SI 0 "register_operand" "=r,r")
10941 (unspec:SI [(match_operand:SI 1 "register_operand" "0,r")
10942 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
10943 (clobber (match_scratch:SI 3 "=X,1"))
10944 (clobber (match_scratch:SI 4 "=&z,z"))]
10949 [(set (match_operand:SI 0 "register_operand" "")
10950 (unspec:SI [(match_operand:SI 1 "register_operand" "")
10951 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
10952 (clobber (match_scratch:SI 3 ""))
10953 (clobber (match_scratch:SI 4 ""))]
10954 "TARGET_SH1 && ! TARGET_SH2 && reload_completed"
10955 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
10956 (parallel [(set (match_dup 0)
10957 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
10958 (label_ref (match_dup 2))] UNSPEC_CASESI))
10959 (clobber (match_dup 3))])
10960 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
10962 if (GET_CODE (operands[2]) == CODE_LABEL)
10963 LABEL_NUSES (operands[2])++;
10967 [(set (match_operand:SI 0 "register_operand" "")
10968 (unspec:SI [(match_operand:SI 1 "register_operand" "")
10969 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
10970 (clobber (match_scratch:SI 3 ""))
10971 (clobber (match_scratch:SI 4 ""))]
10972 "TARGET_SH2 && reload_completed"
10973 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
10974 (parallel [(set (match_dup 0)
10975 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
10976 (label_ref (match_dup 2))] UNSPEC_CASESI))
10977 (clobber (match_dup 3))])]
10979 if (GET_CODE (operands[2]) == CODE_LABEL)
10980 LABEL_NUSES (operands[2])++;
10983 (define_insn "casesi_worker_1"
10984 [(set (match_operand:SI 0 "register_operand" "=r,r")
10985 (unspec:SI [(reg:SI R0_REG)
10986 (match_operand:SI 1 "register_operand" "0,r")
10987 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
10988 (clobber (match_scratch:SI 3 "=X,1"))]
10991 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2])));
10993 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
10995 switch (GET_MODE (diff_vec))
10998 return "shll2 %1" "\n"
10999 " mov.l @(r0,%1),%0";
11001 return "add %1,%1" "\n"
11002 " mov.w @(r0,%1),%0";
11004 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
11005 return "mov.b @(r0,%1),%0" "\n"
11008 return "mov.b @(r0,%1),%0";
11011 gcc_unreachable ();
11014 [(set_attr "length" "4")])
11016 (define_insn "casesi_worker_2"
11017 [(set (match_operand:SI 0 "register_operand" "=r,r")
11018 (unspec:SI [(reg:SI R0_REG)
11019 (match_operand:SI 1 "register_operand" "0,r")
11020 (label_ref (match_operand 2 "" ""))
11021 (label_ref (match_operand 3 "" ""))] UNSPEC_CASESI))
11022 (clobber (match_operand:SI 4 "" "=X,1"))]
11023 "TARGET_SH2 && reload_completed && flag_pic"
11025 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2])));
11026 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
11028 switch (GET_MODE (diff_vec))
11031 return "shll2 %1" "\n"
11033 " mova %O3,r0" "\n"
11034 " mov.l @(r0,%1),%0";
11036 return "add %1,%1" "\n"
11038 " mova %O3,r0" "\n"
11039 " mov.w @(r0,%1),%0";
11041 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
11042 return "add r0,%1" "\n"
11043 " mova %O3,r0" "\n"
11044 " mov.b @(r0,%1),%0" "\n"
11047 return "add r0,%1" "\n"
11048 " mova %O3,r0" "\n"
11049 " mov.b @(r0,%1),%0";
11051 gcc_unreachable ();
11054 [(set_attr "length" "8")])
11056 (define_insn "casesi_shift_media"
11057 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
11058 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
11059 (unspec:DI [(label_ref:DI (match_operand 2 "" ""))]
11063 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2])));
11065 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
11067 switch (GET_MODE (diff_vec))
11070 return "shlli %1, 2, %0";
11072 return "shlli %1, 1, %0";
11074 if (rtx_equal_p (operands[0], operands[1]))
11076 return "add %1, r63, %0";
11078 gcc_unreachable ();
11081 [(set_attr "type" "arith_media")])
11083 (define_insn "casesi_load_media"
11084 [(set (match_operand 0 "any_arith_reg_dest" "=r")
11085 (mem (unspec [(match_operand:DI 1 "arith_reg_operand" "r")
11086 (match_operand:DI 2 "arith_reg_operand" "r")
11087 (label_ref:DI (match_operand 3 "" ""))] UNSPEC_CASESI)))]
11090 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[3])));
11092 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
11094 switch (GET_MODE (diff_vec))
11097 return "ldx.l %1, %2, %0";
11100 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
11101 return "ldx.uw %1, %2, %0";
11103 return "ldx.w %1, %2, %0";
11105 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
11106 return "ldx.ub %1, %2, %0";
11107 return "ldx.b %1, %2, %0";
11109 gcc_unreachable ();
11112 [(set_attr "type" "load_media")])
11114 (define_expand "simple_return"
11116 "sh_can_use_simple_return_p ()")
11118 (define_expand "return"
11120 "reload_completed && epilogue_completed"
11122 if (TARGET_SHMEDIA)
11124 emit_jump_insn (gen_return_media ());
11128 if (TARGET_SHCOMPACT
11129 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1)))
11131 emit_jump_insn (gen_shcompact_return_tramp ());
11136 (define_insn "*<code>_i"
11138 "TARGET_SH1 && ! (TARGET_SHCOMPACT
11139 && (crtl->args.info.call_cookie
11140 & CALL_COOKIE_RET_TRAMP (1)))
11141 && reload_completed
11142 && ! sh_cfun_trap_exit_p ()"
11144 if (TARGET_SH2A && (dbr_sequence_length () == 0)
11145 && !current_function_interrupt)
11150 [(set_attr "type" "return")
11151 (set_attr "needs_delay_slot" "yes")])
11153 ;; trapa has no delay slot.
11154 (define_insn "*return_trapa"
11156 "TARGET_SH1 && !TARGET_SHCOMPACT
11157 && reload_completed"
11159 [(set_attr "type" "return")])
11161 (define_expand "shcompact_return_tramp"
11164 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))"
11166 rtx reg = gen_rtx_REG (Pmode, R0_REG);
11168 function_symbol (reg, "__GCC_shcompact_return_trampoline", SFUNC_STATIC);
11169 emit_jump_insn (gen_shcompact_return_tramp_i ());
11173 (define_insn "shcompact_return_tramp_i"
11174 [(parallel [(return) (use (reg:SI R0_REG))])]
11176 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))"
11178 [(set_attr "type" "jump_ind")
11179 (set_attr "needs_delay_slot" "yes")])
11181 (define_insn "return_media_i"
11182 [(parallel [(return) (use (match_operand 0 "target_reg_operand" "k"))])]
11183 "TARGET_SHMEDIA && reload_completed"
11185 [(set_attr "type" "jump_media")])
11187 (define_insn "return_media_rte"
11189 "TARGET_SHMEDIA && reload_completed && current_function_interrupt"
11191 [(set_attr "type" "jump_media")])
11193 (define_expand "return_media"
11195 "TARGET_SHMEDIA && reload_completed"
11197 int tr_regno = sh_media_register_for_return ();
11200 if (current_function_interrupt)
11202 emit_jump_insn (gen_return_media_rte ());
11207 rtx r18 = gen_rtx_REG (Pmode, PR_MEDIA_REG);
11209 gcc_assert (call_really_used_regs[TR0_REG] && !fixed_regs[TR0_REG]);
11210 tr_regno = TR0_REG;
11211 tr = gen_rtx_REG (Pmode, tr_regno);
11212 emit_move_insn (tr, r18);
11215 tr = gen_rtx_REG (Pmode, tr_regno);
11217 emit_jump_insn (gen_return_media_i (tr));
11221 (define_insn "shcompact_preserve_incoming_args"
11222 [(set (match_operand:SI 0 "register_operand" "+r")
11223 (unspec:SI [(match_dup 0)] UNSPEC_COMPACT_ARGS))]
11226 [(set_attr "length" "0")])
11228 (define_insn "shcompact_incoming_args"
11229 [(set (reg:SI R2_REG) (unspec:SI [(reg:SI R2_REG)] UNSPEC_COMPACT_ARGS))
11230 (set (reg:SI R3_REG) (unspec:SI [(reg:SI R3_REG)] UNSPEC_COMPACT_ARGS))
11231 (set (reg:SI R4_REG) (unspec:SI [(reg:SI R4_REG)] UNSPEC_COMPACT_ARGS))
11232 (set (reg:SI R5_REG) (unspec:SI [(reg:SI R5_REG)] UNSPEC_COMPACT_ARGS))
11233 (set (reg:SI R6_REG) (unspec:SI [(reg:SI R6_REG)] UNSPEC_COMPACT_ARGS))
11234 (set (reg:SI R7_REG) (unspec:SI [(reg:SI R7_REG)] UNSPEC_COMPACT_ARGS))
11235 (set (reg:SI R8_REG) (unspec:SI [(reg:SI R8_REG)] UNSPEC_COMPACT_ARGS))
11236 (set (reg:SI R9_REG) (unspec:SI [(reg:SI R9_REG)] UNSPEC_COMPACT_ARGS))
11237 (set (mem:BLK (reg:SI MACL_REG))
11238 (unspec:BLK [(reg:SI MACH_REG)] UNSPEC_COMPACT_ARGS))
11239 (use (reg:SI R0_REG))
11240 (clobber (reg:SI R0_REG))
11241 (clobber (reg:SI MACL_REG))
11242 (clobber (reg:SI MACH_REG))
11243 (clobber (reg:SI PR_REG))]
11246 [(set_attr "needs_delay_slot" "yes")])
11248 (define_insn "shmedia_save_restore_regs_compact"
11249 [(set (reg:SI SP_REG)
11250 (plus:SI (reg:SI SP_REG)
11251 (match_operand:SI 0 "immediate_operand" "i")))
11252 (use (reg:SI R0_REG))
11253 (clobber (reg:SI PR_REG))]
11255 && (INTVAL (operands[0]) == SHMEDIA_REGS_STACK_ADJUST ()
11256 || INTVAL (operands[0]) == - SHMEDIA_REGS_STACK_ADJUST ())"
11258 [(set_attr "needs_delay_slot" "yes")])
11260 (define_expand "prologue"
11264 sh_expand_prologue ();
11268 (define_expand "epilogue"
11272 sh_expand_epilogue (false);
11274 || (TARGET_SHCOMPACT
11275 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))))
11277 emit_jump_insn (gen_return ());
11282 (define_expand "eh_return"
11283 [(use (match_operand 0 "register_operand" ""))]
11286 rtx ra = operands[0];
11288 if (TARGET_SHMEDIA64)
11289 emit_insn (gen_eh_set_ra_di (ra));
11291 emit_insn (gen_eh_set_ra_si (ra));
11296 ;; Clobber the return address on the stack. We can't expand this
11297 ;; until we know where it will be put in the stack frame.
11299 (define_insn "eh_set_ra_si"
11300 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
11302 (clobber (match_scratch:SI 1 "=&r"))]
11303 "! TARGET_SHMEDIA64"
11306 (define_insn "eh_set_ra_di"
11307 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
11309 (clobber (match_scratch:DI 1 "=&r"))]
11314 [(unspec_volatile [(match_operand 0 "register_operand" "")]
11316 (clobber (match_scratch 1 ""))]
11320 sh_set_return_address (operands[0], operands[1]);
11324 (define_insn "blockage"
11325 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
11328 [(set_attr "length" "0")])
11330 ;; Define movml instructions for SH2A target. Currently they are
11331 ;; used to push and pop all banked registers only.
11333 (define_insn "movml_push_banked"
11334 [(set (match_operand:SI 0 "register_operand" "=r")
11335 (plus (match_dup 0) (const_int -32)))
11336 (set (mem:SI (plus:SI (match_dup 0) (const_int 28))) (reg:SI R7_REG))
11337 (set (mem:SI (plus:SI (match_dup 0) (const_int 24))) (reg:SI R6_REG))
11338 (set (mem:SI (plus:SI (match_dup 0) (const_int 20))) (reg:SI R5_REG))
11339 (set (mem:SI (plus:SI (match_dup 0) (const_int 16))) (reg:SI R4_REG))
11340 (set (mem:SI (plus:SI (match_dup 0) (const_int 12))) (reg:SI R3_REG))
11341 (set (mem:SI (plus:SI (match_dup 0) (const_int 8))) (reg:SI R2_REG))
11342 (set (mem:SI (plus:SI (match_dup 0) (const_int 4))) (reg:SI R1_REG))
11343 (set (mem:SI (plus:SI (match_dup 0) (const_int 0))) (reg:SI R0_REG))]
11344 "TARGET_SH2A && REGNO (operands[0]) == 15"
11346 [(set_attr "in_delay_slot" "no")])
11348 (define_insn "movml_pop_banked"
11349 [(set (match_operand:SI 0 "register_operand" "=r")
11350 (plus (match_dup 0) (const_int 32)))
11351 (set (reg:SI R0_REG) (mem:SI (plus:SI (match_dup 0) (const_int -32))))
11352 (set (reg:SI R1_REG) (mem:SI (plus:SI (match_dup 0) (const_int -28))))
11353 (set (reg:SI R2_REG) (mem:SI (plus:SI (match_dup 0) (const_int -24))))
11354 (set (reg:SI R3_REG) (mem:SI (plus:SI (match_dup 0) (const_int -20))))
11355 (set (reg:SI R4_REG) (mem:SI (plus:SI (match_dup 0) (const_int -16))))
11356 (set (reg:SI R5_REG) (mem:SI (plus:SI (match_dup 0) (const_int -12))))
11357 (set (reg:SI R6_REG) (mem:SI (plus:SI (match_dup 0) (const_int -8))))
11358 (set (reg:SI R7_REG) (mem:SI (plus:SI (match_dup 0) (const_int -4))))]
11359 "TARGET_SH2A && REGNO (operands[0]) == 15"
11361 [(set_attr "in_delay_slot" "no")])
11363 ;; ------------------------------------------------------------------------
11364 ;; Scc instructions
11365 ;; ------------------------------------------------------------------------
11367 (define_insn "movt"
11368 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11369 (match_operand:SI 1 "t_reg_operand"))]
11372 [(set_attr "type" "arith")])
11374 (define_insn "movrt"
11375 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11376 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
11379 [(set_attr "type" "arith")])
11381 (define_expand "cstore4_media"
11382 [(set (match_operand:SI 0 "register_operand" "=r")
11383 (match_operator:SI 1 "sh_float_comparison_operator"
11384 [(match_operand 2 "logical_operand" "")
11385 (match_operand 3 "cmp_operand" "")]))]
11388 machine_mode mode = GET_MODE (operands[2]);
11389 enum rtx_code code = GET_CODE (operands[1]);
11391 if (mode == VOIDmode)
11392 mode = GET_MODE (operands[3]);
11393 if (operands[2] == const0_rtx)
11395 if (code == EQ || code == NE)
11396 operands[2] = operands[3], operands[3] = const0_rtx;
11399 operands[2] = force_reg (mode, operands[2]);
11400 if (operands[3] != const0_rtx)
11401 operands[3] = force_reg (mode, operands[3]);
11407 swap = invert = !FLOAT_MODE_P (mode);
11412 swap = FLOAT_MODE_P (mode), invert = !swap;
11417 swap = true, invert = false;
11424 swap = invert = false;
11428 swap = invert = true;
11432 gcc_unreachable ();
11437 std::swap (operands[2], operands[3]);
11438 code = swap_condition (code);
11443 rtx tem = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
11444 code = reverse_condition (code);
11445 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, operands[2], operands[3]);
11446 emit_insn (gen_cstore4_media (tem, operands[1],
11447 operands[2], operands[3]));
11450 operands[3] = const0_rtx;
11453 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, operands[2], operands[3]);
11456 (define_expand "cstoresi4"
11457 [(set (match_operand:SI 0 "register_operand" "=r")
11458 (match_operator:SI 1 "comparison_operator"
11459 [(match_operand:SI 2 "cmpsi_operand" "")
11460 (match_operand:SI 3 "arith_operand" "")]))]
11461 "TARGET_SH1 || TARGET_SHMEDIA"
11463 if (TARGET_SHMEDIA)
11465 emit_insn (gen_cstore4_media (operands[0], operands[1],
11466 operands[2], operands[3]));
11470 if (sh_expand_t_scc (operands))
11473 if (! currently_expanding_to_rtl)
11476 sh_emit_compare_and_set (operands, SImode);
11480 (define_expand "cstoredi4"
11481 [(set (match_operand:SI 0 "register_operand" "=r")
11482 (match_operator:SI 1 "comparison_operator"
11483 [(match_operand:DI 2 "arith_operand" "")
11484 (match_operand:DI 3 "arith_operand" "")]))]
11485 "TARGET_SH2 || TARGET_SHMEDIA"
11487 if (TARGET_SHMEDIA)
11489 emit_insn (gen_cstore4_media (operands[0], operands[1],
11490 operands[2], operands[3]));
11494 if (sh_expand_t_scc (operands))
11497 if (! currently_expanding_to_rtl)
11500 sh_emit_compare_and_set (operands, DImode);
11504 ;; Move the complement of the T reg to a reg.
11505 ;; On SH2A the movrt insn can be used.
11506 ;; On anything else than SH2A this has to be done with multiple instructions.
11507 ;; One obvious way would be:
11512 ;; However, this puts pressure on r0 in most cases and thus the following is
11518 ;; If the constant -1 can be CSE-ed or lifted out of a loop it effectively
11519 ;; becomes a one instruction operation. Moreover, care must be taken that
11520 ;; the insn can still be combined with inverted compare and branch code
11521 ;; around it. On the other hand, if a function returns the complement of
11522 ;; a previous comparison result in the T bit, the xor #1,r0 approach might
11523 ;; lead to better code.
11524 (define_expand "movnegt"
11525 [(set (match_operand:SI 0 "arith_reg_dest" "")
11526 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
11530 emit_insn (gen_movrt (operands[0], operands[1]));
11533 rtx val = force_reg (SImode, gen_int_mode (-1, SImode));
11534 emit_insn (gen_movrt_negc (operands[0], operands[1], val));
11539 (define_insn_and_split "movrt_negc"
11540 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11541 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
11542 (set (reg:SI T_REG) (const_int 1))
11543 (use (match_operand:SI 2 "arith_reg_operand" "r"))]
11549 if (sh_split_movrt_negc_to_movt_xor (curr_insn, operands))
11554 [(set_attr "type" "arith")])
11556 ;; The -1 constant will not be CSE-ed for the *movrt_negc pattern, but the
11557 ;; pattern can be used by the combine pass. Using a scratch reg for the
11558 ;; -1 constant results in slightly better register allocations compared to
11559 ;; generating a pseudo reg before reload.
11560 (define_insn_and_split "*movrt_negc"
11561 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11562 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
11563 (clobber (match_scratch:SI 2 "=r"))
11564 (clobber (reg:SI T_REG))]
11565 "TARGET_SH1 && ! TARGET_SH2A"
11570 if (sh_split_movrt_negc_to_movt_xor (curr_insn, operands))
11572 else if (reload_completed)
11574 emit_move_insn (operands[2], gen_int_mode (-1, SImode));
11575 emit_insn (gen_movrt_negc (operands[0], operands[1], operands[2]));
11582 ;; Store the negated T bit in a reg using r0 and xor. This one doesn't
11583 ;; clobber the T bit, which is useful when storing the T bit and the
11584 ;; negated T bit in parallel. On SH2A the movrt insn can be used for that.
11585 ;; Usually we don't want this insn to be matched, except for cases where the
11586 ;; T bit clobber is really not appreciated. Hence the extra use on T_REG.
11587 (define_insn_and_split "movrt_xor"
11588 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
11589 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
11590 (use (reg:SI T_REG))]
11593 "&& reload_completed"
11594 [(set (match_dup 0) (reg:SI T_REG))
11595 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))])
11597 ;; Use negc to store the T bit in a MSB of a reg in the following way:
11598 ;; T = 1: 0x80000000 -> reg
11599 ;; T = 0: 0x7FFFFFFF -> reg
11600 ;; This works because 0 - 0x80000000 = 0x80000000.
11602 ;; This insn must not match again after it has been split into the constant
11603 ;; load and negc. This is accomplished by the special negc insn that
11604 ;; has a use on the operand.
11605 (define_insn_and_split "*mov_t_msb_neg"
11606 [(set (match_operand:SI 0 "arith_reg_dest")
11607 (minus:SI (const_int -2147483648) ;; 0x80000000
11608 (match_operand 1 "t_reg_operand")))
11609 (clobber (reg:SI T_REG))]
11612 "&& can_create_pseudo_p ()"
11613 [(set (match_dup 2) (const_int -2147483648))
11614 (parallel [(set (match_dup 0) (minus:SI (neg:SI (match_dup 2))
11616 (clobber (reg:SI T_REG))
11617 (use (match_dup 2))])]
11619 operands[2] = gen_reg_rtx (SImode);
11622 (define_insn "*mov_t_msb_neg_negc"
11623 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11624 (minus:SI (neg:SI (match_operand:SI 1 "arith_reg_operand" "r"))
11625 (match_operand:SI 2 "t_reg_operand")))
11626 (clobber (reg:SI T_REG))
11627 (use (match_dup 1))]
11630 [(set_attr "type" "arith")])
11632 ;; These are essentially the same as above, but with the inverted T bit.
11633 ;; Combine recognizes the split patterns, but does not take them sometimes
11634 ;; if the T_REG clobber is specified. Instead it tries to split out the
11635 ;; T bit negation. Since these splits are supposed to be taken only by
11636 ;; combine, it will see the T_REG clobber of the *mov_t_msb_neg insn, so this
11639 [(set (match_operand:SI 0 "arith_reg_dest")
11640 (plus:SI (match_operand 1 "negt_reg_operand")
11641 (const_int 2147483647)))] ;; 0x7fffffff
11642 "TARGET_SH1 && can_create_pseudo_p ()"
11643 [(parallel [(set (match_dup 0)
11644 (minus:SI (const_int -2147483648) (reg:SI T_REG)))
11645 (clobber (reg:SI T_REG))])])
11648 [(set (match_operand:SI 0 "arith_reg_dest")
11649 (if_then_else:SI (match_operand 1 "t_reg_operand")
11650 (const_int 2147483647) ;; 0x7fffffff
11651 (const_int -2147483648)))] ;; 0x80000000
11652 "TARGET_SH1 && can_create_pseudo_p ()"
11653 [(parallel [(set (match_dup 0)
11654 (minus:SI (const_int -2147483648) (reg:SI T_REG)))
11655 (clobber (reg:SI T_REG))])])
11657 ;; The *negnegt pattern helps the combine pass to figure out how to fold
11658 ;; an explicit double T bit negation.
11659 (define_insn_and_split "*negnegt"
11660 [(set (reg:SI T_REG)
11661 (eq:SI (match_operand 0 "negt_reg_operand" "") (const_int 0)))]
11667 ;; Store T bit as all zeros or ones in a reg.
11668 (define_insn "mov_neg_si_t"
11669 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11670 (neg:SI (match_operand 1 "t_reg_operand" "")))]
11673 [(set_attr "type" "arith")])
11675 ;; Store negated T bit as all zeros or ones in a reg.
11676 ;; Use the following sequence:
11677 ;; subc Rn,Rn ! Rn = Rn - Rn - T; T = T
11678 ;; not Rn,Rn ! Rn = 0 - Rn
11680 [(set (match_operand:SI 0 "arith_reg_dest" "")
11681 (neg:SI (match_operand 1 "negt_reg_operand" "")))]
11683 [(set (match_dup 0) (neg:SI (reg:SI T_REG)))
11684 (set (match_dup 0) (not:SI (match_dup 0)))])
11686 ;; The *movtt pattern eliminates redundant T bit to T bit moves / tests.
11687 (define_insn_and_split "*movtt"
11688 [(set (reg:SI T_REG)
11689 (eq:SI (match_operand 0 "t_reg_operand" "") (const_int 1)))]
11695 ;; Invert the T bit.
11696 ;; On SH2A we can use the nott insn. On anything else this must be done with
11697 ;; multiple insns like:
11700 ;; This requires an additional pseudo. The SH specific sh_treg_combine RTL
11701 ;; pass will look for this insn. Disallow using it if pseudos can't be
11703 (define_insn_and_split "nott"
11704 [(set (reg:SI T_REG)
11705 (xor:SI (match_operand:SI 0 "t_reg_operand") (const_int 1)))]
11706 "TARGET_SH2A || (TARGET_SH1 && can_create_pseudo_p ())"
11708 gcc_assert (TARGET_SH2A);
11711 "! TARGET_SH2A && can_create_pseudo_p ()"
11712 [(set (match_dup 0) (reg:SI T_REG))
11713 (set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))]
11715 operands[0] = gen_reg_rtx (SImode);
11718 ;; Store T bit as MSB in a reg.
11719 ;; T = 0: 0x00000000 -> reg
11720 ;; T = 1: 0x80000000 -> reg
11721 (define_insn_and_split "*movt_msb"
11722 [(set (match_operand:SI 0 "arith_reg_dest")
11723 (mult:SI (match_operand:SI 1 "t_reg_operand")
11724 (const_int -2147483648))) ;; 0xffffffff80000000
11725 (clobber (reg:SI T_REG))]
11729 [(set (match_dup 0) (ashift:SI (reg:SI T_REG) (const_int 31)))])
11731 ;; Store inverted T bit as MSB in a reg.
11732 ;; T = 0: 0x80000000 -> reg
11733 ;; T = 1: 0x00000000 -> reg
11734 ;; On SH2A we can get away without clobbering the T_REG using the movrt insn.
11735 ;; On non SH2A we resort to the following sequence:
11739 ;; The T bit value will be modified during the sequence, but the rotcr insn
11740 ;; will restore its original value.
11741 (define_insn_and_split "*negt_msb"
11742 [(set (match_operand:SI 0 "arith_reg_dest")
11743 (match_operand:SI 1 "negt_reg_shl31_operand"))]
11746 "&& can_create_pseudo_p ()"
11749 rtx tmp = gen_reg_rtx (SImode);
11753 emit_insn (gen_movrt (tmp, get_t_reg_rtx ()));
11754 emit_insn (gen_rotrsi3 (operands[0], tmp, const1_rtx));
11758 emit_move_insn (tmp, get_t_reg_rtx ());
11759 emit_insn (gen_cmpeqsi_t (tmp, const0_rtx));
11760 emit_insn (gen_rotcr (operands[0], tmp, get_t_reg_rtx ()));
11765 ;; The *cset_zero patterns convert optimizations such as
11766 ;; "if (test) x = 0;"
11768 ;; "x &= -(test == 0);"
11769 ;; back to conditional branch sequences if zero-displacement branches
11771 ;; FIXME: These patterns can be removed when conditional execution patterns
11772 ;; are implemented, since ifcvt will not perform these optimizations if
11773 ;; conditional execution is supported.
11774 (define_insn "*cset_zero"
11775 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11776 (and:SI (plus:SI (match_operand:SI 1 "t_reg_operand")
11778 (match_operand:SI 2 "arith_reg_operand" "0")))]
11779 "TARGET_SH1 && TARGET_ZDCBRANCH"
11781 return "bf 0f" "\n"
11785 [(set_attr "type" "arith") ;; poor approximation
11786 (set_attr "length" "4")])
11788 (define_insn "*cset_zero"
11789 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11790 (if_then_else:SI (match_operand:SI 1 "cbranch_treg_value")
11791 (match_operand:SI 2 "arith_reg_operand" "0")
11793 "TARGET_SH1 && TARGET_ZDCBRANCH"
11795 int tval = sh_eval_treg_value (operands[1]);
11797 return "bt 0f" "\n"
11800 else if (tval == false)
11801 return "bf 0f" "\n"
11805 gcc_unreachable ();
11807 [(set_attr "type" "arith") ;; poor approximation
11808 (set_attr "length" "4")])
11810 (define_expand "cstoresf4"
11811 [(set (match_operand:SI 0 "register_operand" "=r")
11812 (match_operator:SI 1 "sh_float_comparison_operator"
11813 [(match_operand:SF 2 "arith_operand" "")
11814 (match_operand:SF 3 "arith_operand" "")]))]
11815 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
11817 if (TARGET_SHMEDIA)
11819 emit_insn (gen_cstore4_media (operands[0], operands[1],
11820 operands[2], operands[3]));
11824 if (! currently_expanding_to_rtl)
11827 sh_emit_compare_and_set (operands, SFmode);
11831 (define_expand "cstoredf4"
11832 [(set (match_operand:SI 0 "register_operand" "=r")
11833 (match_operator:SI 1 "sh_float_comparison_operator"
11834 [(match_operand:DF 2 "arith_operand" "")
11835 (match_operand:DF 3 "arith_operand" "")]))]
11836 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
11838 if (TARGET_SHMEDIA)
11840 emit_insn (gen_cstore4_media (operands[0], operands[1],
11841 operands[2], operands[3]));
11845 if (! currently_expanding_to_rtl)
11848 sh_emit_compare_and_set (operands, DFmode);
11852 ;; -------------------------------------------------------------------------
11853 ;; Instructions to cope with inline literal tables
11854 ;; -------------------------------------------------------------------------
11856 ;; 2 byte integer in line
11857 (define_insn "consttable_2"
11858 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
11859 (match_operand 1 "" "")]
11863 if (operands[1] != const0_rtx)
11864 assemble_integer (operands[0], 2, BITS_PER_UNIT * 2, 1);
11867 [(set_attr "length" "2")
11868 (set_attr "in_delay_slot" "no")])
11870 ;; 4 byte integer in line
11871 (define_insn "consttable_4"
11872 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
11873 (match_operand 1 "" "")]
11877 if (operands[1] != const0_rtx)
11879 assemble_integer (operands[0], 4, BITS_PER_UNIT * 4, 1);
11880 mark_symbol_refs_as_used (operands[0]);
11884 [(set_attr "length" "4")
11885 (set_attr "in_delay_slot" "no")])
11887 ;; 8 byte integer in line
11888 (define_insn "consttable_8"
11889 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
11890 (match_operand 1 "" "")]
11894 if (operands[1] != const0_rtx)
11895 assemble_integer (operands[0], 8, BITS_PER_UNIT * 8, 1);
11898 [(set_attr "length" "8")
11899 (set_attr "in_delay_slot" "no")])
11901 ;; 4 byte floating point
11902 (define_insn "consttable_sf"
11903 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")
11904 (match_operand 1 "" "")]
11908 if (operands[1] != const0_rtx)
11911 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
11912 assemble_real (d, SFmode, GET_MODE_ALIGNMENT (SFmode));
11916 [(set_attr "length" "4")
11917 (set_attr "in_delay_slot" "no")])
11919 ;; 8 byte floating point
11920 (define_insn "consttable_df"
11921 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")
11922 (match_operand 1 "" "")]
11926 if (operands[1] != const0_rtx)
11929 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
11930 assemble_real (d, DFmode, GET_MODE_ALIGNMENT (DFmode));
11934 [(set_attr "length" "8")
11935 (set_attr "in_delay_slot" "no")])
11937 ;; Alignment is needed for some constant tables; it may also be added for
11938 ;; Instructions at the start of loops, or after unconditional branches.
11939 ;; ??? We would get more accurate lengths if we did instruction
11940 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
11941 ;; here is too conservative.
11943 ;; align to a two byte boundary
11944 (define_expand "align_2"
11945 [(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)]
11949 ;; Align to a four byte boundary.
11950 ;; align_4 and align_log are instructions for the starts of loops, or
11951 ;; after unconditional branches, which may take up extra room.
11952 (define_expand "align_4"
11953 [(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)]
11957 ;; Align to a cache line boundary.
11958 (define_insn "align_log"
11959 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)]
11962 [(set_attr "length" "0")
11963 (set_attr "in_delay_slot" "no")])
11965 ;; Emitted at the end of the literal table, used to emit the
11966 ;; 32bit branch labels if needed.
11967 (define_insn "consttable_end"
11968 [(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)]
11971 return output_jump_label_table ();
11973 [(set_attr "in_delay_slot" "no")])
11975 ;; Emitted at the end of the window in the literal table.
11976 (define_insn "consttable_window_end"
11977 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_WINDOW_END)]
11980 [(set_attr "length" "0")
11981 (set_attr "in_delay_slot" "no")])
11983 ;; -------------------------------------------------------------------------
11984 ;; Minimum / maximum operations.
11985 ;; -------------------------------------------------------------------------
11987 ;; The SH2A clips.b and clips.w insns do a signed min-max function. If smin
11988 ;; and smax standard name patterns are defined, they will be used during
11989 ;; initial expansion and combine will then be able to form the actual min-max
11991 ;; The clips.b and clips.w set the SR.CS bit if the value in the register is
11992 ;; clipped, but there is currently no way of making use of this information.
11993 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
11994 (define_expand "<code>si3"
11995 [(parallel [(set (match_operand:SI 0 "arith_reg_dest")
11996 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
11997 (match_operand 2 "const_int_operand")))
11998 (clobber (reg:SI T_REG))])]
12001 /* Force the comparison value into a register, because greater-than
12002 comparisons can work only on registers. Combine will be able to pick up
12003 the constant value from the REG_EQUAL note when trying to form a min-max
12005 operands[2] = force_reg (SImode, operands[2]);
12009 ;; smax (smin (...))
12011 ;; smin (smax (...))
12012 (define_insn_and_split "*clips"
12013 [(set (match_operand:SI 0 "arith_reg_dest")
12014 (smax:SI (smin:SI (match_operand:SI 1 "arith_reg_operand")
12015 (match_operand 2 "clips_max_const_int"))
12016 (match_operand 3 "clips_min_const_int")))]
12020 [(set (match_dup 0)
12021 (smin:SI (smax:SI (match_dup 1) (match_dup 3)) (match_dup 2)))])
12023 (define_insn "*clips"
12024 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
12025 (smin:SI (smax:SI (match_operand:SI 1 "arith_reg_operand" "0")
12026 (match_operand 2 "clips_min_const_int"))
12027 (match_operand 3 "clips_max_const_int")))]
12030 if (INTVAL (operands[3]) == 127)
12031 return "clips.b %0";
12032 else if (INTVAL (operands[3]) == 32767)
12033 return "clips.w %0";
12035 gcc_unreachable ();
12037 [(set_attr "type" "arith")])
12039 ;; If the expanded smin or smax patterns were not combined, split them into
12040 ;; a compare and branch sequence, because there are no real smin or smax
12042 (define_insn_and_split "*<code>si3"
12043 [(set (match_operand:SI 0 "arith_reg_dest")
12044 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
12045 (match_operand:SI 2 "arith_reg_or_0_or_1_operand")))
12046 (clobber (reg:SI T_REG))]
12047 "TARGET_SH2A && can_create_pseudo_p ()"
12052 rtx skip_label = gen_label_rtx ();
12053 emit_move_insn (operands[0], operands[1]);
12055 rtx cmp_val = operands[2];
12056 if (satisfies_constraint_M (cmp_val))
12057 cmp_val = const0_rtx;
12059 emit_insn (gen_cmpgtsi_t (operands[0], cmp_val));
12060 emit_jump_insn (<CODE> == SMIN
12061 ? gen_branch_false (skip_label)
12062 : gen_branch_true (skip_label));
12064 emit_label_after (skip_label, emit_move_insn (operands[0], operands[2]));
12068 ;; The SH2A clipu.b and clipu.w insns can be used to implement a min function
12069 ;; with a register and a constant.
12070 ;; The clipu.b and clipu.w set the SR.CS bit if the value in the register is
12071 ;; clipped, but there is currently no way of making use of this information.
12072 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
12073 (define_expand "uminsi3"
12074 [(set (match_operand:SI 0 "arith_reg_dest")
12075 (umin:SI (match_operand:SI 1 "arith_reg_operand")
12076 (match_operand 2 "const_int_operand")))]
12079 if (INTVAL (operands[2]) == 1)
12081 emit_insn (gen_clipu_one (operands[0], operands[1]));
12084 else if (! clipu_max_const_int (operands[2], VOIDmode))
12088 (define_insn "*clipu"
12089 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
12090 (umin:SI (match_operand:SI 1 "arith_reg_operand" "0")
12091 (match_operand 2 "clipu_max_const_int")))]
12094 if (INTVAL (operands[2]) == 255)
12095 return "clipu.b %0";
12096 else if (INTVAL (operands[2]) == 65535)
12097 return "clipu.w %0";
12099 gcc_unreachable ();
12101 [(set_attr "type" "arith")])
12103 (define_insn_and_split "clipu_one"
12104 [(set (match_operand:SI 0 "arith_reg_dest")
12105 (umin:SI (match_operand:SI 1 "arith_reg_operand") (const_int 1)))
12106 (clobber (reg:SI T_REG))]
12109 "&& can_create_pseudo_p ()"
12112 emit_insn (gen_cmpeqsi_t (operands[1], const0_rtx));
12113 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
12117 ;; -------------------------------------------------------------------------
12119 ;; -------------------------------------------------------------------------
12121 ;; String/block move insn.
12123 (define_expand "movmemsi"
12124 [(parallel [(set (mem:BLK (match_operand:BLK 0))
12125 (mem:BLK (match_operand:BLK 1)))
12126 (use (match_operand:SI 2 "nonmemory_operand"))
12127 (use (match_operand:SI 3 "immediate_operand"))
12128 (clobber (reg:SI PR_REG))
12129 (clobber (reg:SI R4_REG))
12130 (clobber (reg:SI R5_REG))
12131 (clobber (reg:SI R0_REG))])]
12132 "TARGET_SH1 && ! TARGET_SH5"
12134 if (expand_block_move (operands))
12140 (define_insn "block_move_real"
12141 [(parallel [(set (mem:BLK (reg:SI R4_REG))
12142 (mem:BLK (reg:SI R5_REG)))
12143 (use (match_operand:SI 0 "arith_reg_operand" "r"))
12144 (clobber (reg:SI PR_REG))
12145 (clobber (reg:SI R0_REG))])]
12146 "TARGET_SH1 && ! TARGET_HARD_SH4"
12148 [(set_attr "type" "sfunc")
12149 (set_attr "needs_delay_slot" "yes")])
12151 (define_insn "block_lump_real"
12152 [(parallel [(set (mem:BLK (reg:SI R4_REG))
12153 (mem:BLK (reg:SI R5_REG)))
12154 (use (match_operand:SI 0 "arith_reg_operand" "r"))
12155 (use (reg:SI R6_REG))
12156 (clobber (reg:SI PR_REG))
12157 (clobber (reg:SI T_REG))
12158 (clobber (reg:SI R4_REG))
12159 (clobber (reg:SI R5_REG))
12160 (clobber (reg:SI R6_REG))
12161 (clobber (reg:SI R0_REG))])]
12162 "TARGET_SH1 && ! TARGET_HARD_SH4"
12164 [(set_attr "type" "sfunc")
12165 (set_attr "needs_delay_slot" "yes")])
12167 (define_insn "block_move_real_i4"
12168 [(parallel [(set (mem:BLK (reg:SI R4_REG))
12169 (mem:BLK (reg:SI R5_REG)))
12170 (use (match_operand:SI 0 "arith_reg_operand" "r"))
12171 (clobber (reg:SI PR_REG))
12172 (clobber (reg:SI R0_REG))
12173 (clobber (reg:SI R1_REG))
12174 (clobber (reg:SI R2_REG))])]
12177 [(set_attr "type" "sfunc")
12178 (set_attr "needs_delay_slot" "yes")])
12180 (define_insn "block_lump_real_i4"
12181 [(parallel [(set (mem:BLK (reg:SI R4_REG))
12182 (mem:BLK (reg:SI R5_REG)))
12183 (use (match_operand:SI 0 "arith_reg_operand" "r"))
12184 (use (reg:SI R6_REG))
12185 (clobber (reg:SI PR_REG))
12186 (clobber (reg:SI T_REG))
12187 (clobber (reg:SI R4_REG))
12188 (clobber (reg:SI R5_REG))
12189 (clobber (reg:SI R6_REG))
12190 (clobber (reg:SI R0_REG))
12191 (clobber (reg:SI R1_REG))
12192 (clobber (reg:SI R2_REG))
12193 (clobber (reg:SI R3_REG))])]
12196 [(set_attr "type" "sfunc")
12197 (set_attr "needs_delay_slot" "yes")])
12199 ;; byte compare pattern
12201 ;; !((temp & 0xF000) && (temp & 0x0F00) && (temp & 0x00F0) && (temp & 0x000F))
12202 (define_insn "cmpstr_t"
12203 [(set (reg:SI T_REG)
12208 (xor:SI (match_operand:SI 0 "arith_reg_operand" "r")
12209 (match_operand:SI 1 "arith_reg_operand" "r"))
12210 (const_int 8) (const_int 0))
12211 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
12212 (const_int 8) (const_int 8)))
12213 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
12214 (const_int 8) (const_int 16)))
12215 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
12216 (const_int 8) (const_int 24)))
12220 [(set_attr "type" "mt_group")])
12222 (define_expand "cmpstrsi"
12223 [(set (match_operand:SI 0 "register_operand")
12224 (compare:SI (match_operand:BLK 1 "memory_operand")
12225 (match_operand:BLK 2 "memory_operand")))
12226 (use (match_operand 3 "immediate_operand"))]
12227 "TARGET_SH1 && optimize"
12229 if (! optimize_insn_for_size_p () && sh_expand_cmpstr (operands))
12235 (define_expand "cmpstrnsi"
12236 [(set (match_operand:SI 0 "register_operand")
12237 (compare:SI (match_operand:BLK 1 "memory_operand")
12238 (match_operand:BLK 2 "memory_operand")))
12239 (use (match_operand:SI 3 "immediate_operand"))
12240 (use (match_operand:SI 4 "immediate_operand"))]
12241 "TARGET_SH1 && optimize"
12243 if (! optimize_insn_for_size_p () && sh_expand_cmpnstr (operands))
12249 (define_expand "strlensi"
12250 [(set (match_operand:SI 0 "register_operand")
12251 (unspec:SI [(match_operand:BLK 1 "memory_operand")
12252 (match_operand:SI 2 "immediate_operand")
12253 (match_operand:SI 3 "immediate_operand")]
12254 UNSPEC_BUILTIN_STRLEN))]
12255 "TARGET_SH1 && optimize"
12257 if (! optimize_insn_for_size_p () && sh_expand_strlen (operands))
12263 (define_expand "setmemqi"
12264 [(parallel [(set (match_operand:BLK 0 "memory_operand")
12265 (match_operand 2 "const_int_operand"))
12266 (use (match_operand:QI 1 "const_int_operand"))
12267 (use (match_operand:QI 3 "const_int_operand"))])]
12268 "TARGET_SH1 && optimize"
12270 if (optimize_insn_for_size_p ())
12273 sh_expand_setmem (operands);
12278 ;; -------------------------------------------------------------------------
12279 ;; Floating point instructions.
12280 ;; -------------------------------------------------------------------------
12282 ;; FIXME: For now we disallow any memory operands for fpscr loads/stores,
12283 ;; except for post-inc loads and pre-dec stores for push/pop purposes.
12284 ;; This avoids problems with reload. As a consequence, user initiated fpscr
12285 ;; stores to memory will always be ferried through a general register.
12286 ;; User initiated fpscr loads always have to undergo bit masking to preserve
12287 ;; the current fpu mode settings for the compiler generated code. Thus such
12288 ;; fpscr loads will always have to go through general registers anyways.
12289 (define_insn "lds_fpscr"
12290 [(set (reg:SI FPSCR_REG)
12291 (match_operand:SI 0 "fpscr_movsrc_operand" "r,>"))
12292 (set (reg:SI FPSCR_STAT_REG)
12293 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_STAT))
12294 (set (reg:SI FPSCR_MODES_REG)
12295 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
12300 [(set_attr "type" "gp_fpscr,mem_fpscr")])
12302 ;; A move fpscr -> reg schedules like a move mac -> reg. Thus we use mac_gp
12304 (define_insn "sts_fpscr"
12305 [(set (match_operand:SI 0 "fpscr_movdst_operand" "=r,<")
12306 (reg:SI FPSCR_REG))
12307 (use (reg:SI FPSCR_STAT_REG))
12308 (use (reg:SI FPSCR_MODES_REG))]
12313 [(set_attr "type" "mac_gp,fstore")])
12315 (define_expand "set_fpscr"
12316 [(parallel [(set (reg:SI FPSCR_REG)
12317 (match_operand:SI 0 "general_operand"))
12318 (set (reg:SI FPSCR_STAT_REG)
12319 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))])]
12322 /* We have to mask out the FR, SZ and PR bits. To do that, we need to
12323 get the current FPSCR value first.
12324 (a & ~mask) | (b & mask) = a ^ ((a ^ b) & mask) */
12326 rtx mask = force_reg (SImode, GEN_INT (FPSCR_FR | FPSCR_SZ | FPSCR_PR));
12328 rtx a = force_reg (SImode, operands[0]);
12330 rtx b = gen_reg_rtx (SImode);
12331 emit_insn (gen_sts_fpscr (b));
12333 rtx a_xor_b = gen_reg_rtx (SImode);
12334 emit_insn (gen_xorsi3 (a_xor_b, a, b));
12336 rtx a_xor_b_and_mask = gen_reg_rtx (SImode);
12337 emit_insn (gen_andsi3 (a_xor_b_and_mask, a_xor_b, mask));
12339 rtx r = gen_reg_rtx (SImode);
12340 emit_insn (gen_xorsi3 (r, a_xor_b_and_mask, a));
12341 emit_insn (gen_lds_fpscr (r));
12346 ;; ??? This uses the fp unit, but has no type indicating that.
12347 ;; If we did that, this would either give a bogus latency or introduce
12348 ;; a bogus FIFO constraint.
12349 ;; Since this insn is currently only used for prologues/epilogues,
12350 ;; it is probably best to claim no function unit, which matches the
12351 ;; current setting.
12352 (define_insn "toggle_sz"
12353 [(set (reg:SI FPSCR_REG)
12354 (xor:SI (reg:SI FPSCR_REG) (const_int FPSCR_SZ)))
12355 (set (reg:SI FPSCR_MODES_REG)
12356 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
12357 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12359 [(set_attr "type" "fpscr_toggle") (set_attr "fp_set" "unknown")])
12361 ;; Toggle FPU precision PR mode.
12363 (define_insn "toggle_pr"
12364 [(set (reg:SI FPSCR_REG)
12365 (xor:SI (reg:SI FPSCR_REG) (const_int FPSCR_PR)))
12366 (set (reg:SI FPSCR_MODES_REG)
12367 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
12370 [(set_attr "type" "fpscr_toggle")])
12372 (define_expand "addsf3"
12373 [(set (match_operand:SF 0 "fp_arith_reg_operand")
12374 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand")
12375 (match_operand:SF 2 "fp_arith_reg_operand")))]
12376 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12380 emit_insn (gen_addsf3_i (operands[0], operands[1], operands[2]));
12385 (define_insn "*addsf3_media"
12386 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12387 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
12388 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12389 "TARGET_SHMEDIA_FPU"
12390 "fadd.s %1, %2, %0"
12391 [(set_attr "type" "fparith_media")])
12393 (define_insn_and_split "unary_sf_op"
12394 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12399 (parallel [(not:BI (match_operand 3 "const_int_operand" "n"))]))
12400 (match_operator:SF 2 "unary_float_operator"
12401 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
12402 (parallel [(match_operand 4
12403 "const_int_operand" "n")]))]))
12404 (parallel [(not:BI (match_dup 3)) (match_dup 3)])))]
12405 "TARGET_SHMEDIA_FPU"
12407 "TARGET_SHMEDIA_FPU && reload_completed"
12408 [(set (match_dup 5) (match_dup 6))]
12410 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
12411 rtx op1 = gen_rtx_REG (SFmode,
12412 (true_regnum (operands[1])
12413 + (INTVAL (operands[4]) ^ endian)));
12415 operands[7] = gen_rtx_REG (SFmode,
12416 (true_regnum (operands[0])
12417 + (INTVAL (operands[3]) ^ endian)));
12418 operands[6] = gen_rtx_fmt_e (GET_CODE (operands[2]), SFmode, op1);
12420 [(set_attr "type" "fparith_media")])
12422 (define_insn_and_split "binary_sf_op0"
12423 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12425 (match_operator:SF 3 "binary_float_operator"
12426 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
12427 (parallel [(const_int 0)]))
12428 (vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
12429 (parallel [(const_int 0)]))])
12432 (parallel [(const_int 1)]))))]
12433 "TARGET_SHMEDIA_FPU"
12435 "&& reload_completed"
12436 [(set (match_dup 4) (match_dup 5))]
12438 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
12439 rtx op1 = gen_rtx_REG (SFmode,
12440 true_regnum (operands[1]) + endian);
12441 rtx op2 = gen_rtx_REG (SFmode,
12442 true_regnum (operands[2]) + endian);
12444 operands[4] = gen_rtx_REG (SFmode,
12445 true_regnum (operands[0]) + endian);
12446 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2);
12448 [(set_attr "type" "fparith_media")])
12450 (define_insn_and_split "binary_sf_op1"
12451 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12455 (parallel [(const_int 0)]))
12456 (match_operator:SF 3 "binary_float_operator"
12457 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
12458 (parallel [(const_int 1)]))
12459 (vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
12460 (parallel [(const_int 1)]))])))]
12461 "TARGET_SHMEDIA_FPU"
12463 "&& reload_completed"
12464 [(set (match_dup 4) (match_dup 5))]
12466 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
12467 rtx op1 = gen_rtx_REG (SFmode, true_regnum (operands[1]) + (1 ^ endian));
12468 rtx op2 = gen_rtx_REG (SFmode, true_regnum (operands[2]) + (1 ^ endian));
12470 operands[4] = gen_rtx_REG (SFmode, true_regnum (operands[0]) + (1 ^ endian));
12471 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2);
12473 [(set_attr "type" "fparith_media")])
12475 (define_insn "addsf3_i"
12476 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12477 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
12478 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
12479 (clobber (reg:SI FPSCR_STAT_REG))
12480 (use (reg:SI FPSCR_MODES_REG))]
12483 [(set_attr "type" "fp")
12484 (set_attr "fp_mode" "single")])
12486 (define_expand "subsf3"
12487 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12488 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
12489 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
12490 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12494 emit_insn (gen_subsf3_i (operands[0], operands[1], operands[2]));
12499 (define_insn "*subsf3_media"
12500 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12501 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
12502 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12503 "TARGET_SHMEDIA_FPU"
12504 "fsub.s %1, %2, %0"
12505 [(set_attr "type" "fparith_media")])
12507 (define_insn "subsf3_i"
12508 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12509 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
12510 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
12511 (clobber (reg:SI FPSCR_STAT_REG))
12512 (use (reg:SI FPSCR_MODES_REG))]
12515 [(set_attr "type" "fp")
12516 (set_attr "fp_mode" "single")])
12518 (define_expand "mulsf3"
12519 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12520 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
12521 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
12522 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12526 emit_insn (gen_mulsf3_i (operands[0], operands[1], operands[2]));
12531 (define_insn "*mulsf3_media"
12532 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12533 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
12534 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12535 "TARGET_SHMEDIA_FPU"
12536 "fmul.s %1, %2, %0"
12537 [(set_attr "type" "fparith_media")])
12539 (define_insn "mulsf3_i"
12540 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12541 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
12542 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
12543 (clobber (reg:SI FPSCR_STAT_REG))
12544 (use (reg:SI FPSCR_MODES_REG))]
12547 [(set_attr "type" "fp")
12548 (set_attr "fp_mode" "single")])
12550 ;; FMA (fused multiply-add) patterns
12551 (define_expand "fmasf4"
12552 [(set (match_operand:SF 0 "fp_arith_reg_operand")
12553 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand")
12554 (match_operand:SF 2 "fp_arith_reg_operand")
12555 (match_operand:SF 3 "fp_arith_reg_operand")))]
12556 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12560 emit_insn (gen_fmasf4_i (operands[0], operands[1], operands[2],
12566 (define_insn "fmasf4_i"
12567 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12568 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand" "w")
12569 (match_operand:SF 2 "fp_arith_reg_operand" "f")
12570 (match_operand:SF 3 "fp_arith_reg_operand" "0")))
12571 (clobber (reg:SI FPSCR_STAT_REG))
12572 (use (reg:SI FPSCR_MODES_REG))]
12575 [(set_attr "type" "fp")
12576 (set_attr "fp_mode" "single")])
12578 (define_insn "fmasf4_media"
12579 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12580 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
12581 (match_operand:SF 2 "fp_arith_reg_operand" "f")
12582 (match_operand:SF 3 "fp_arith_reg_operand" "0")))]
12583 "TARGET_SHMEDIA_FPU"
12584 "fmac.s %1, %2, %0"
12585 [(set_attr "type" "fparith_media")])
12587 ;; For some cases such as 'a * b + a' the FMA pattern is not generated by
12588 ;; previous transformations. If FMA is generally allowed, let the combine
12589 ;; pass utilize it.
12590 (define_insn_and_split "*fmasf4"
12591 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12592 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%w")
12593 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
12594 (match_operand:SF 3 "arith_reg_operand" "0")))
12595 (clobber (reg:SI FPSCR_STAT_REG))
12596 (use (reg:SI FPSCR_MODES_REG))]
12597 "TARGET_SH2E && flag_fp_contract_mode != FP_CONTRACT_OFF"
12599 "&& can_create_pseudo_p ()"
12600 [(parallel [(set (match_dup 0)
12601 (fma:SF (match_dup 1) (match_dup 2) (match_dup 3)))
12602 (clobber (reg:SI FPSCR_STAT_REG))
12603 (use (reg:SI FPSCR_MODES_REG))])]
12605 /* Change 'b * a + a' into 'a * b + a'.
12606 This is better for register allocation. */
12607 if (REGNO (operands[2]) == REGNO (operands[3]))
12608 std::swap (operands[1], operands[2]);
12610 [(set_attr "type" "fp")
12611 (set_attr "fp_mode" "single")])
12613 (define_insn "*fmasf4_media"
12614 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12615 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
12616 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
12617 (match_operand:SF 3 "fp_arith_reg_operand" "0")))]
12618 "TARGET_SHMEDIA_FPU && flag_fp_contract_mode != FP_CONTRACT_OFF"
12619 "fmac.s %1, %2, %0"
12620 [(set_attr "type" "fparith_media")])
12622 (define_expand "divsf3"
12623 [(set (match_operand:SF 0 "fp_arith_reg_operand")
12624 (div:SF (match_operand:SF 1 "fp_arith_reg_operand")
12625 (match_operand:SF 2 "fp_arith_reg_operand")))]
12626 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12630 emit_insn (gen_divsf3_i (operands[0], operands[1], operands[2]));
12635 (define_insn "*divsf3_media"
12636 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12637 (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
12638 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12639 "TARGET_SHMEDIA_FPU"
12640 "fdiv.s %1, %2, %0"
12641 [(set_attr "type" "fdiv_media")])
12643 (define_insn "divsf3_i"
12644 [(set (match_operand:SF 0 "fp_arith_reg_dest" "=f")
12645 (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
12646 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
12647 (clobber (reg:SI FPSCR_STAT_REG))
12648 (use (reg:SI FPSCR_MODES_REG))]
12651 [(set_attr "type" "fdiv")
12652 (set_attr "fp_mode" "single")])
12654 (define_insn "floatdisf2"
12655 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12656 (float:SF (match_operand:DI 1 "fp_arith_reg_operand" "f")))]
12657 "TARGET_SHMEDIA_FPU"
12659 [(set_attr "type" "fpconv_media")])
12661 (define_expand "floatsisf2"
12662 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12663 (float:SF (match_operand:SI 1 "fpul_operand" "")))]
12664 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12666 if (!TARGET_SHMEDIA_FPU)
12668 emit_insn (gen_floatsisf2_i4 (operands[0], operands[1]));
12673 (define_insn "*floatsisf2_media"
12674 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12675 (float:SF (match_operand:SI 1 "fp_arith_reg_operand" "f")))]
12676 "TARGET_SHMEDIA_FPU"
12678 [(set_attr "type" "fpconv_media")])
12680 (define_insn "floatsisf2_i4"
12681 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12682 (float:SF (match_operand:SI 1 "fpul_operand" "y")))
12683 (clobber (reg:SI FPSCR_STAT_REG))
12684 (use (reg:SI FPSCR_MODES_REG))]
12687 [(set_attr "type" "fp")
12688 (set_attr "fp_mode" "single")])
12690 (define_insn "fix_truncsfdi2"
12691 [(set (match_operand:DI 0 "fp_arith_reg_dest" "=f")
12692 (fix:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12693 "TARGET_SHMEDIA_FPU"
12695 [(set_attr "type" "fpconv_media")])
12697 (define_expand "fix_truncsfsi2"
12698 [(set (match_operand:SI 0 "fpul_operand" "=y")
12699 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12700 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12702 if (!TARGET_SHMEDIA_FPU)
12704 emit_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1]));
12709 (define_insn "*fix_truncsfsi2_media"
12710 [(set (match_operand:SI 0 "fp_arith_reg_operand" "=f")
12711 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12712 "TARGET_SHMEDIA_FPU"
12714 [(set_attr "type" "fpconv_media")])
12716 (define_insn "fix_truncsfsi2_i4"
12717 [(set (match_operand:SI 0 "fpul_operand" "=y")
12718 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))
12719 (clobber (reg:SI FPSCR_STAT_REG))
12720 (use (reg:SI FPSCR_MODES_REG))]
12723 [(set_attr "type" "ftrc_s")
12724 (set_attr "fp_mode" "single")])
12726 (define_insn "cmpgtsf_t"
12727 [(set (reg:SI T_REG)
12728 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12729 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
12730 (clobber (reg:SI FPSCR_STAT_REG))
12731 (use (reg:SI FPSCR_MODES_REG))]
12732 "TARGET_SH2E || TARGET_SH4 || TARGET_SH2A_SINGLE"
12734 [(set_attr "type" "fp_cmp")
12735 (set_attr "fp_mode" "single")])
12737 (define_insn "cmpeqsf_t"
12738 [(set (reg:SI T_REG)
12739 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12740 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
12741 (clobber (reg:SI FPSCR_STAT_REG))
12742 (use (reg:SI FPSCR_MODES_REG))]
12743 "TARGET_SH2E || TARGET_SH4 || TARGET_SH2A_SINGLE"
12745 [(set_attr "type" "fp_cmp")
12746 (set_attr "fp_mode" "single")])
12748 (define_insn "ieee_ccmpeqsf_t"
12749 [(set (reg:SI T_REG)
12750 (ior:SI (reg:SI T_REG)
12751 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12752 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))
12753 (clobber (reg:SI FPSCR_STAT_REG))
12754 (use (reg:SI FPSCR_MODES_REG))]
12755 "TARGET_IEEE && TARGET_SH2E"
12757 return output_ieee_ccmpeq (insn, operands);
12759 [(set_attr "length" "4")
12760 (set_attr "fp_mode" "single")])
12762 (define_insn "cmpeqsf_media"
12763 [(set (match_operand:SI 0 "register_operand" "=r")
12764 (eq:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
12765 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12766 "TARGET_SHMEDIA_FPU"
12767 "fcmpeq.s %1, %2, %0"
12768 [(set_attr "type" "fcmp_media")])
12770 (define_insn "cmpgtsf_media"
12771 [(set (match_operand:SI 0 "register_operand" "=r")
12772 (gt:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
12773 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12774 "TARGET_SHMEDIA_FPU"
12775 "fcmpgt.s %1, %2, %0"
12776 [(set_attr "type" "fcmp_media")])
12778 (define_insn "cmpgesf_media"
12779 [(set (match_operand:SI 0 "register_operand" "=r")
12780 (ge:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
12781 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12782 "TARGET_SHMEDIA_FPU"
12783 "fcmpge.s %1, %2, %0"
12784 [(set_attr "type" "fcmp_media")])
12786 (define_insn "cmpunsf_media"
12787 [(set (match_operand:SI 0 "register_operand" "=r")
12788 (unordered:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
12789 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12790 "TARGET_SHMEDIA_FPU"
12791 "fcmpun.s %1, %2, %0"
12792 [(set_attr "type" "fcmp_media")])
12794 (define_expand "cbranchsf4"
12796 (if_then_else (match_operator 0 "sh_float_comparison_operator"
12797 [(match_operand:SF 1 "arith_operand" "")
12798 (match_operand:SF 2 "arith_operand" "")])
12799 (match_operand 3 "" "")
12801 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12803 if (TARGET_SHMEDIA)
12804 emit_jump_insn (gen_cbranchfp4_media (operands[0], operands[1], operands[2],
12807 sh_emit_compare_and_branch (operands, SFmode);
12811 (define_expand "negsf2"
12812 [(set (match_operand:SF 0 "fp_arith_reg_operand")
12813 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand")))]
12814 "TARGET_SH2E || TARGET_SHMEDIA_FPU")
12816 (define_insn "*negsf2_media"
12817 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12818 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12819 "TARGET_SHMEDIA_FPU"
12821 [(set_attr "type" "fmove_media")])
12823 (define_insn "*negsf2_i"
12824 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12825 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))]
12828 [(set_attr "type" "fmove")])
12830 (define_expand "sqrtsf2"
12831 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12832 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
12833 "TARGET_SH3E || TARGET_SHMEDIA_FPU"
12837 emit_insn (gen_sqrtsf2_i (operands[0], operands[1]));
12842 (define_insn "*sqrtsf2_media"
12843 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12844 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12845 "TARGET_SHMEDIA_FPU"
12847 [(set_attr "type" "fdiv_media")])
12849 (define_insn "sqrtsf2_i"
12850 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12851 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
12852 (clobber (reg:SI FPSCR_STAT_REG))
12853 (use (reg:SI FPSCR_MODES_REG))]
12856 [(set_attr "type" "fdiv")
12857 (set_attr "fp_mode" "single")])
12859 (define_insn "rsqrtsf2"
12860 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12861 (div:SF (match_operand:SF 1 "immediate_operand" "i")
12862 (sqrt:SF (match_operand:SF 2 "fp_arith_reg_operand" "0"))))
12863 (clobber (reg:SI FPSCR_STAT_REG))
12864 (use (reg:SI FPSCR_MODES_REG))]
12865 "TARGET_FPU_ANY && TARGET_FSRRA
12866 && operands[1] == CONST1_RTX (SFmode)"
12868 [(set_attr "type" "fsrra")
12869 (set_attr "fp_mode" "single")])
12871 ;; When the sincos pattern is defined, the builtin functions sin and cos
12872 ;; will be expanded to the sincos pattern and one of the output values will
12874 (define_expand "sincossf3"
12875 [(set (match_operand:SF 0 "nonimmediate_operand")
12876 (unspec:SF [(match_operand:SF 2 "fp_arith_reg_operand")] UNSPEC_FCOSA))
12877 (set (match_operand:SF 1 "nonimmediate_operand")
12878 (unspec:SF [(match_dup 2)] UNSPEC_FSINA))]
12879 "TARGET_FPU_ANY && TARGET_FSCA"
12881 rtx scaled = gen_reg_rtx (SFmode);
12882 rtx truncated = gen_reg_rtx (SImode);
12883 rtx fsca = gen_reg_rtx (V2SFmode);
12884 rtx scale_reg = force_reg (SFmode, sh_fsca_sf2int ());
12886 emit_insn (gen_mulsf3 (scaled, operands[2], scale_reg));
12887 emit_insn (gen_fix_truncsfsi2 (truncated, scaled));
12888 emit_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf ()));
12890 emit_move_insn (operands[0], gen_rtx_SUBREG (SFmode, fsca, 4));
12891 emit_move_insn (operands[1], gen_rtx_SUBREG (SFmode, fsca, 0));
12895 (define_insn_and_split "fsca"
12896 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12898 (unspec:SF [(mult:SF
12899 (float:SF (match_operand:SI 1 "fpul_fsca_operand" "y"))
12900 (match_operand:SF 2 "fsca_scale_factor" "i"))
12902 (unspec:SF [(mult:SF (float:SF (match_dup 1)) (match_dup 2))
12904 (clobber (reg:SI FPSCR_STAT_REG))
12905 (use (reg:SI FPSCR_MODES_REG))]
12906 "TARGET_FPU_ANY && TARGET_FSCA"
12908 "&& !fpul_operand (operands[1], SImode)"
12911 /* If operands[1] is something like (fix:SF (float:SF (reg:SI))) reduce it
12912 to a simple reg, otherwise reload will have trouble reloading the
12913 pseudo into fpul. */
12914 rtx x = XEXP (operands[1], 0);
12915 while (x != NULL_RTX && !fpul_operand (x, SImode))
12917 gcc_assert (GET_CODE (x) == FIX || GET_CODE (x) == FLOAT);
12920 gcc_assert (x != NULL_RTX && fpul_operand (x, SImode));
12921 emit_insn (gen_fsca (operands[0], x, operands[2]));
12924 [(set_attr "type" "fsca")
12925 (set_attr "fp_mode" "single")])
12927 (define_expand "abssf2"
12928 [(set (match_operand:SF 0 "fp_arith_reg_operand")
12929 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand")))]
12930 "TARGET_SH2E || TARGET_SHMEDIA_FPU")
12932 (define_insn "*abssf2_media"
12933 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12934 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12935 "TARGET_SHMEDIA_FPU"
12937 [(set_attr "type" "fmove_media")])
12939 (define_insn "*abssf2_i"
12940 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12941 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))]
12944 [(set_attr "type" "fmove")])
12946 (define_expand "adddf3"
12947 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
12948 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
12949 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
12950 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
12952 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
12954 emit_insn (gen_adddf3_i (operands[0], operands[1], operands[2]));
12959 (define_insn "*adddf3_media"
12960 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12961 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f")
12962 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
12963 "TARGET_SHMEDIA_FPU"
12964 "fadd.d %1, %2, %0"
12965 [(set_attr "type" "dfparith_media")])
12967 (define_insn "adddf3_i"
12968 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12969 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
12970 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
12971 (clobber (reg:SI FPSCR_STAT_REG))
12972 (use (reg:SI FPSCR_MODES_REG))]
12973 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12975 [(set_attr "type" "dfp_arith")
12976 (set_attr "fp_mode" "double")])
12978 (define_expand "subdf3"
12979 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
12980 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
12981 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
12982 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
12984 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
12986 emit_insn (gen_subdf3_i (operands[0], operands[1], operands[2]));
12991 (define_insn "*subdf3_media"
12992 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12993 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")
12994 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
12995 "TARGET_SHMEDIA_FPU"
12996 "fsub.d %1, %2, %0"
12997 [(set_attr "type" "dfparith_media")])
12999 (define_insn "subdf3_i"
13000 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13001 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
13002 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
13003 (clobber (reg:SI FPSCR_STAT_REG))
13004 (use (reg:SI FPSCR_MODES_REG))]
13005 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13007 [(set_attr "type" "dfp_arith")
13008 (set_attr "fp_mode" "double")])
13010 (define_expand "muldf3"
13011 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
13012 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
13013 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
13014 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13016 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13018 emit_insn (gen_muldf3_i (operands[0], operands[1], operands[2]));
13023 (define_insn "*muldf3_media"
13024 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13025 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f")
13026 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13027 "TARGET_SHMEDIA_FPU"
13028 "fmul.d %1, %2, %0"
13029 [(set_attr "type" "dfmul_media")])
13031 (define_insn "muldf3_i"
13032 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13033 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
13034 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
13035 (clobber (reg:SI FPSCR_STAT_REG))
13036 (use (reg:SI FPSCR_MODES_REG))]
13037 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13039 [(set_attr "type" "dfp_mul")
13040 (set_attr "fp_mode" "double")])
13042 (define_expand "divdf3"
13043 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
13044 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
13045 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
13046 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13048 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13050 emit_insn (gen_divdf3_i (operands[0], operands[1], operands[2]));
13055 (define_insn "*divdf3_media"
13056 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13057 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")
13058 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13059 "TARGET_SHMEDIA_FPU"
13060 "fdiv.d %1, %2, %0"
13061 [(set_attr "type" "dfdiv_media")])
13063 (define_insn "divdf3_i"
13064 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13065 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
13066 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
13067 (clobber (reg:SI FPSCR_STAT_REG))
13068 (use (reg:SI FPSCR_MODES_REG))]
13069 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13071 [(set_attr "type" "dfdiv")
13072 (set_attr "fp_mode" "double")])
13074 (define_insn "floatdidf2"
13075 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13076 (float:DF (match_operand:DI 1 "fp_arith_reg_operand" "f")))]
13077 "TARGET_SHMEDIA_FPU"
13079 [(set_attr "type" "dfpconv_media")])
13081 (define_expand "floatsidf2"
13082 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
13083 (float:DF (match_operand:SI 1 "fpul_operand" "")))]
13084 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13086 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13088 emit_insn (gen_floatsidf2_i (operands[0], operands[1]));
13093 (define_insn "*floatsidf2_media"
13094 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13095 (float:DF (match_operand:SI 1 "fp_arith_reg_operand" "f")))]
13096 "TARGET_SHMEDIA_FPU"
13098 [(set_attr "type" "dfpconv_media")])
13100 (define_insn "floatsidf2_i"
13101 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13102 (float:DF (match_operand:SI 1 "fpul_operand" "y")))
13103 (clobber (reg:SI FPSCR_STAT_REG))
13104 (use (reg:SI FPSCR_MODES_REG))]
13105 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13107 [(set_attr "type" "dfp_conv")
13108 (set_attr "fp_mode" "double")])
13110 (define_insn "fix_truncdfdi2"
13111 [(set (match_operand:DI 0 "fp_arith_reg_dest" "=f")
13112 (fix:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13113 "TARGET_SHMEDIA_FPU"
13115 [(set_attr "type" "dfpconv_media")])
13117 (define_expand "fix_truncdfsi2"
13118 [(set (match_operand:SI 0 "fpul_operand" "")
13119 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "")))]
13120 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13122 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13124 emit_insn (gen_fix_truncdfsi2_i (operands[0], operands[1]));
13129 (define_insn "*fix_truncdfsi2_media"
13130 [(set (match_operand:SI 0 "fp_arith_reg_operand" "=f")
13131 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13132 "TARGET_SHMEDIA_FPU"
13134 [(set_attr "type" "dfpconv_media")])
13136 (define_insn "fix_truncdfsi2_i"
13137 [(set (match_operand:SI 0 "fpul_operand" "=y")
13138 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
13139 (clobber (reg:SI FPSCR_STAT_REG))
13140 (use (reg:SI FPSCR_MODES_REG))]
13141 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13143 [(set_attr "type" "dfp_conv")
13144 (set_attr "dfp_comp" "no")
13145 (set_attr "fp_mode" "double")])
13147 (define_insn "cmpgtdf_t"
13148 [(set (reg:SI T_REG)
13149 (gt:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
13150 (match_operand:DF 1 "fp_arith_reg_operand" "f")))
13151 (clobber (reg:SI FPSCR_STAT_REG))
13152 (use (reg:SI FPSCR_MODES_REG))]
13153 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13155 [(set_attr "type" "dfp_cmp")
13156 (set_attr "fp_mode" "double")])
13158 (define_insn "cmpeqdf_t"
13159 [(set (reg:SI T_REG)
13160 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
13161 (match_operand:DF 1 "fp_arith_reg_operand" "f")))
13162 (clobber (reg:SI FPSCR_STAT_REG))
13163 (use (reg:SI FPSCR_MODES_REG))]
13164 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13166 [(set_attr "type" "dfp_cmp")
13167 (set_attr "fp_mode" "double")])
13169 (define_insn "*ieee_ccmpeqdf_t"
13170 [(set (reg:SI T_REG)
13171 (ior:SI (reg:SI T_REG)
13172 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
13173 (match_operand:DF 1 "fp_arith_reg_operand" "f"))))
13174 (clobber (reg:SI FPSCR_STAT_REG))
13175 (use (reg:SI FPSCR_MODES_REG))]
13176 "TARGET_IEEE && (TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13178 return output_ieee_ccmpeq (insn, operands);
13180 [(set_attr "length" "4")
13181 (set_attr "fp_mode" "double")])
13183 (define_insn "cmpeqdf_media"
13184 [(set (match_operand:SI 0 "register_operand" "=r")
13185 (eq:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
13186 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13187 "TARGET_SHMEDIA_FPU"
13188 "fcmpeq.d %1,%2,%0"
13189 [(set_attr "type" "fcmp_media")])
13191 (define_insn "cmpgtdf_media"
13192 [(set (match_operand:SI 0 "register_operand" "=r")
13193 (gt:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
13194 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13195 "TARGET_SHMEDIA_FPU"
13196 "fcmpgt.d %1,%2,%0"
13197 [(set_attr "type" "fcmp_media")])
13199 (define_insn "cmpgedf_media"
13200 [(set (match_operand:SI 0 "register_operand" "=r")
13201 (ge:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
13202 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13203 "TARGET_SHMEDIA_FPU"
13204 "fcmpge.d %1,%2,%0"
13205 [(set_attr "type" "fcmp_media")])
13207 (define_insn "cmpundf_media"
13208 [(set (match_operand:SI 0 "register_operand" "=r")
13209 (unordered:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
13210 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13211 "TARGET_SHMEDIA_FPU"
13212 "fcmpun.d %1,%2,%0"
13213 [(set_attr "type" "fcmp_media")])
13215 (define_expand "cbranchdf4"
13217 (if_then_else (match_operator 0 "sh_float_comparison_operator"
13218 [(match_operand:DF 1 "arith_operand" "")
13219 (match_operand:DF 2 "arith_operand" "")])
13220 (match_operand 3 "" "")
13222 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13224 if (TARGET_SHMEDIA)
13225 emit_jump_insn (gen_cbranchfp4_media (operands[0], operands[1], operands[2],
13228 sh_emit_compare_and_branch (operands, DFmode);
13232 (define_expand "negdf2"
13233 [(set (match_operand:DF 0 "fp_arith_reg_operand")
13234 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
13235 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU")
13237 (define_insn "*negdf2_media"
13238 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13239 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13240 "TARGET_SHMEDIA_FPU"
13242 [(set_attr "type" "fmove_media")])
13244 (define_insn "*negdf2_i"
13245 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13246 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))]
13247 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13249 [(set_attr "type" "fmove")])
13251 (define_expand "sqrtdf2"
13252 [(set (match_operand:DF 0 "fp_arith_reg_operand")
13253 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
13254 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13256 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13258 emit_insn (gen_sqrtdf2_i (operands[0], operands[1]));
13263 (define_insn "*sqrtdf2_media"
13264 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13265 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13266 "TARGET_SHMEDIA_FPU"
13268 [(set_attr "type" "dfdiv_media")])
13270 (define_insn "sqrtdf2_i"
13271 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13272 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
13273 (clobber (reg:SI FPSCR_STAT_REG))
13274 (use (reg:SI FPSCR_MODES_REG))]
13275 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13277 [(set_attr "type" "dfdiv")
13278 (set_attr "fp_mode" "double")])
13280 (define_expand "absdf2"
13281 [(set (match_operand:DF 0 "fp_arith_reg_operand")
13282 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
13283 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU")
13285 (define_insn "*absdf2_media"
13286 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13287 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13288 "TARGET_SHMEDIA_FPU"
13290 [(set_attr "type" "fmove_media")])
13292 (define_insn "*absdf2_i"
13293 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13294 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))]
13295 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13297 [(set_attr "type" "fmove")])
13299 (define_expand "extendsfdf2"
13300 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
13301 (float_extend:DF (match_operand:SF 1 "fpul_operand" "")))]
13302 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13304 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13306 emit_insn (gen_extendsfdf2_i4 (operands[0], operands[1]));
13311 (define_insn "*extendsfdf2_media"
13312 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13313 (float_extend:DF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
13314 "TARGET_SHMEDIA_FPU"
13316 [(set_attr "type" "dfpconv_media")])
13318 (define_insn "extendsfdf2_i4"
13319 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13320 (float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
13321 (clobber (reg:SI FPSCR_STAT_REG))
13322 (use (reg:SI FPSCR_MODES_REG))]
13323 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13325 [(set_attr "type" "fp")
13326 (set_attr "fp_mode" "double")])
13328 (define_expand "truncdfsf2"
13329 [(set (match_operand:SF 0 "fpul_operand" "")
13330 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "")))]
13331 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13333 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13335 emit_insn (gen_truncdfsf2_i4 (operands[0], operands[1]));
13340 (define_insn "*truncdfsf2_media"
13341 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13342 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13343 "TARGET_SHMEDIA_FPU"
13345 [(set_attr "type" "dfpconv_media")])
13347 (define_insn "truncdfsf2_i4"
13348 [(set (match_operand:SF 0 "fpul_operand" "=y")
13349 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
13350 (clobber (reg:SI FPSCR_STAT_REG))
13351 (use (reg:SI FPSCR_MODES_REG))]
13352 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13354 [(set_attr "type" "fp")
13355 (set_attr "fp_mode" "double")])
13357 ;; -------------------------------------------------------------------------
13358 ;; Bit field extract patterns.
13359 ;; -------------------------------------------------------------------------
13361 ;; These give better code for packed bitfields, because they allow
13362 ;; auto-increment addresses to be generated.
13364 (define_expand "insv"
13365 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
13366 (match_operand:SI 1 "immediate_operand" "")
13367 (match_operand:SI 2 "immediate_operand" ""))
13368 (match_operand:SI 3 "general_operand" ""))]
13369 "TARGET_SH1 && TARGET_BIG_ENDIAN"
13371 rtx addr_target, orig_address, shift_reg, qi_val;
13372 HOST_WIDE_INT bitsize, size, v = 0;
13373 rtx x = operands[3];
13375 if (TARGET_SH2A && TARGET_BITOPS
13376 && (satisfies_constraint_Sbw (operands[0])
13377 || satisfies_constraint_Sbv (operands[0]))
13378 && satisfies_constraint_M (operands[1])
13379 && satisfies_constraint_K03 (operands[2]))
13381 if (satisfies_constraint_N (operands[3]))
13383 emit_insn (gen_bclr_m2a (operands[0], operands[2]));
13386 else if (satisfies_constraint_M (operands[3]))
13388 emit_insn (gen_bset_m2a (operands[0], operands[2]));
13391 else if ((REG_P (operands[3]) && REGNO (operands[3]) == T_REG)
13392 && satisfies_constraint_M (operands[1]))
13394 emit_insn (gen_bst_m2a (operands[0], operands[2]));
13397 else if (REG_P (operands[3])
13398 && satisfies_constraint_M (operands[1]))
13400 emit_insn (gen_bld_reg (operands[3], const0_rtx));
13401 emit_insn (gen_bst_m2a (operands[0], operands[2]));
13405 /* ??? expmed doesn't care for non-register predicates. */
13406 if (! memory_operand (operands[0], VOIDmode)
13407 || ! immediate_operand (operands[1], VOIDmode)
13408 || ! immediate_operand (operands[2], VOIDmode)
13409 || ! general_operand (x, VOIDmode))
13411 /* If this isn't a 16 / 24 / 32 bit field, or if
13412 it doesn't start on a byte boundary, then fail. */
13413 bitsize = INTVAL (operands[1]);
13414 if (bitsize < 16 || bitsize > 32 || bitsize % 8 != 0
13415 || (INTVAL (operands[2]) % 8) != 0)
13418 size = bitsize / 8;
13419 orig_address = XEXP (operands[0], 0);
13420 shift_reg = gen_reg_rtx (SImode);
13421 if (CONST_INT_P (x))
13424 qi_val = force_reg (QImode, GEN_INT (trunc_int_for_mode (v, QImode)));
13428 emit_insn (gen_movsi (shift_reg, operands[3]));
13429 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
13431 addr_target = copy_addr_to_reg (plus_constant (Pmode,
13432 orig_address, size - 1));
13434 operands[0] = replace_equiv_address (operands[0], addr_target);
13435 emit_insn (gen_movqi (operands[0], qi_val));
13439 if (CONST_INT_P (x))
13441 = force_reg (QImode, GEN_INT (trunc_int_for_mode (v >>= 8, QImode)));
13444 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
13445 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
13447 emit_insn (gen_addsi3 (addr_target, addr_target, constm1_rtx));
13448 emit_insn (gen_movqi (operands[0], qi_val));
13454 (define_insn "movua"
13455 [(set (match_operand:SI 0 "register_operand" "=z")
13456 (unspec:SI [(match_operand:BLK 1 "unaligned_load_operand" "Sua>")]
13460 [(set_attr "type" "movua")])
13462 ;; We shouldn't need this, but cse replaces increments with references
13463 ;; to other regs before flow has a chance to create post_inc
13464 ;; addressing modes, and only postreload's cse_move2add brings the
13465 ;; increments back to a usable form.
13467 [(set (match_operand:SI 0 "register_operand" "")
13468 (sign_extract:SI (mem:SI (match_operand:SI 1 "register_operand" ""))
13469 (const_int 32) (const_int 0)))
13470 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
13471 "TARGET_SH4A && REGNO (operands[0]) != REGNO (operands[1])"
13472 [(set (match_operand:SI 0 "register_operand" "")
13473 (sign_extract:SI (mem:SI (post_inc:SI
13474 (match_operand:SI 1 "register_operand" "")))
13475 (const_int 32) (const_int 0)))]
13478 (define_expand "extv"
13479 [(set (match_operand:SI 0 "register_operand" "")
13480 (sign_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
13481 (match_operand 2 "const_int_operand" "")
13482 (match_operand 3 "const_int_operand" "")))]
13483 "TARGET_SH4A || TARGET_SH2A"
13485 if (TARGET_SH2A && TARGET_BITOPS
13486 && (satisfies_constraint_Sbw (operands[1])
13487 || satisfies_constraint_Sbv (operands[1]))
13488 && satisfies_constraint_M (operands[2])
13489 && satisfies_constraint_K03 (operands[3]))
13491 emit_insn (gen_bldsign_m2a (operands[1], operands[3]));
13492 if (REGNO (operands[0]) != T_REG)
13493 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
13497 && INTVAL (operands[2]) == 32
13498 && INTVAL (operands[3]) == 0
13499 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
13501 rtx src = adjust_address (operands[1], BLKmode, 0);
13502 set_mem_size (src, 4);
13503 emit_insn (gen_movua (operands[0], src));
13510 (define_expand "extzv"
13511 [(set (match_operand:SI 0 "register_operand" "")
13512 (zero_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
13513 (match_operand 2 "const_int_operand" "")
13514 (match_operand 3 "const_int_operand" "")))]
13515 "TARGET_SH4A || TARGET_SH2A"
13517 if (TARGET_SH2A && TARGET_BITOPS
13518 && (satisfies_constraint_Sbw (operands[1])
13519 || satisfies_constraint_Sbv (operands[1]))
13520 && satisfies_constraint_M (operands[2])
13521 && satisfies_constraint_K03 (operands[3]))
13523 emit_insn (gen_bld_m2a (operands[1], operands[3]));
13524 if (REGNO (operands[0]) != T_REG)
13525 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
13529 && INTVAL (operands[2]) == 32
13530 && INTVAL (operands[3]) == 0
13531 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
13533 rtx src = adjust_address (operands[1], BLKmode, 0);
13534 set_mem_size (src, 4);
13535 emit_insn (gen_movua (operands[0], src));
13542 ;; SH2A instructions for bitwise operations.
13543 ;; FIXME: Convert multiple instruction insns to insn_and_split.
13544 ;; FIXME: Use iterators to fold at least and,xor,or insn variations.
13546 ;; Clear a bit in a memory location.
13547 (define_insn "bclr_m2a"
13548 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
13550 (not:QI (ashift:QI (const_int 1)
13551 (match_operand:QI 1 "const_int_operand" "K03,K03")))
13553 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13556 bclr.b %1,@(0,%t0)"
13557 [(set_attr "length" "4,4")])
13559 (define_insn "bclrmem_m2a"
13560 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
13561 (and:QI (match_dup 0)
13562 (match_operand:QI 1 "const_int_operand" "Psz,Psz")))]
13563 "TARGET_SH2A && satisfies_constraint_Psz (operands[1]) && TARGET_BITOPS"
13566 bclr.b %W1,@(0,%t0)"
13567 [(set_attr "length" "4,4")])
13569 ;; Set a bit in a memory location.
13570 (define_insn "bset_m2a"
13571 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
13573 (ashift:QI (const_int 1)
13574 (match_operand:QI 1 "const_int_operand" "K03,K03"))
13576 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13579 bset.b %1,@(0,%t0)"
13580 [(set_attr "length" "4,4")])
13582 (define_insn "bsetmem_m2a"
13583 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
13584 (ior:QI (match_dup 0)
13585 (match_operand:QI 1 "const_int_operand" "Pso,Pso")))]
13586 "TARGET_SH2A && satisfies_constraint_Pso (operands[1]) && TARGET_BITOPS"
13589 bset.b %V1,@(0,%t0)"
13590 [(set_attr "length" "4,4")])
13592 ;;; Transfer the contents of the T bit to a specified bit of memory.
13593 (define_insn "bst_m2a"
13594 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,m")
13595 (if_then_else (eq (reg:SI T_REG) (const_int 0))
13597 (not:QI (ashift:QI (const_int 1)
13598 (match_operand:QI 1 "const_int_operand" "K03,K03")))
13601 (ashift:QI (const_int 1) (match_dup 1))
13603 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13607 [(set_attr "length" "4")])
13609 ;; Store a specified bit of memory in the T bit.
13610 (define_insn "bld_m2a"
13611 [(set (reg:SI T_REG)
13613 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,Sbv")
13615 (match_operand 1 "const_int_operand" "K03,K03")))]
13616 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13620 [(set_attr "length" "4,4")])
13622 ;; Store a specified bit of memory in the T bit.
13623 (define_insn "bldsign_m2a"
13624 [(set (reg:SI T_REG)
13626 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
13628 (match_operand 1 "const_int_operand" "K03,K03")))]
13629 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13633 [(set_attr "length" "4,4")])
13635 ;; Store a specified bit of the LSB 8 bits of a register in the T bit.
13636 (define_insn "bld_reg"
13637 [(set (reg:SI T_REG)
13638 (zero_extract:SI (match_operand:SI 0 "arith_reg_operand" "r")
13640 (match_operand 1 "const_int_operand" "K03")))]
13641 "TARGET_SH2A && satisfies_constraint_K03 (operands[1])"
13644 (define_insn "*bld_regqi"
13645 [(set (reg:SI T_REG)
13646 (zero_extract:SI (match_operand:QI 0 "arith_reg_operand" "r")
13648 (match_operand 1 "const_int_operand" "K03")))]
13649 "TARGET_SH2A && satisfies_constraint_K03 (operands[1])"
13652 ;; Take logical and of a specified bit of memory with the T bit and
13653 ;; store its result in the T bit.
13654 (define_insn "band_m2a"
13655 [(set (reg:SI T_REG)
13656 (and:SI (reg:SI T_REG)
13658 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
13660 (match_operand 1 "const_int_operand" "K03,K03"))))]
13661 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13664 band.b %1,@(0,%t0)"
13665 [(set_attr "length" "4,4")])
13667 (define_insn "bandreg_m2a"
13668 [(set (match_operand:SI 0 "register_operand" "=r,r")
13669 (and:SI (zero_extract:SI
13670 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
13672 (match_operand 2 "const_int_operand" "K03,K03"))
13673 (match_operand:SI 3 "register_operand" "r,r")))]
13674 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
13676 static const char* alt[] =
13678 "band.b %2,%1" "\n"
13681 "band.b %2,@(0,%t1)" "\n"
13684 return alt[which_alternative];
13686 [(set_attr "length" "6,6")])
13688 ;; Take logical or of a specified bit of memory with the T bit and
13689 ;; store its result in the T bit.
13690 (define_insn "bor_m2a"
13691 [(set (reg:SI T_REG)
13692 (ior:SI (reg:SI T_REG)
13694 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
13696 (match_operand 1 "const_int_operand" "K03,K03"))))]
13697 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13701 [(set_attr "length" "4,4")])
13703 (define_insn "borreg_m2a"
13704 [(set (match_operand:SI 0 "register_operand" "=r,r")
13705 (ior:SI (zero_extract:SI
13706 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
13708 (match_operand 2 "const_int_operand" "K03,K03"))
13709 (match_operand:SI 3 "register_operand" "=r,r")))]
13710 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
13712 static const char* alt[] =
13717 "bor.b %2,@(0,%t1)" "\n"
13720 return alt[which_alternative];
13722 [(set_attr "length" "6,6")])
13724 ;; Take exclusive or of a specified bit of memory with the T bit and
13725 ;; store its result in the T bit.
13726 (define_insn "bxor_m2a"
13727 [(set (reg:SI T_REG)
13728 (xor:SI (reg:SI T_REG)
13730 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
13732 (match_operand 1 "const_int_operand" "K03,K03"))))]
13733 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13736 bxor.b %1,@(0,%t0)"
13737 [(set_attr "length" "4,4")])
13739 (define_insn "bxorreg_m2a"
13740 [(set (match_operand:SI 0 "register_operand" "=r,r")
13741 (xor:SI (zero_extract:SI
13742 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
13744 (match_operand 2 "const_int_operand" "K03,K03"))
13745 (match_operand:SI 3 "register_operand" "=r,r")))]
13746 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
13748 static const char* alt[] =
13750 "bxor.b %2,%1" "\n"
13753 "bxor.b %2,@(0,%t1)" "\n"
13756 return alt[which_alternative];
13758 [(set_attr "length" "6,6")])
13760 ;; -------------------------------------------------------------------------
13762 ;; -------------------------------------------------------------------------
13763 ;; This matches cases where the bit in a memory location is set.
13765 [(set (match_operand:SI 0 "register_operand")
13766 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
13768 (ior:SI (match_dup 0)
13769 (match_operand:SI 2 "const_int_operand")))
13771 (match_operand 3 "arith_reg_operand"))]
13772 "TARGET_SH2A && TARGET_BITOPS
13773 && satisfies_constraint_Pso (operands[2])
13774 && REGNO (operands[0]) == REGNO (operands[3])"
13775 [(set (match_dup 1)
13776 (ior:QI (match_dup 1) (match_dup 2)))]
13779 ;; This matches cases where the bit in a memory location is cleared.
13781 [(set (match_operand:SI 0 "register_operand")
13782 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
13784 (and:SI (match_dup 0)
13785 (match_operand:SI 2 "const_int_operand")))
13787 (match_operand 3 "arith_reg_operand"))]
13788 "TARGET_SH2A && TARGET_BITOPS
13789 && satisfies_constraint_Psz (operands[2])
13790 && REGNO (operands[0]) == REGNO (operands[3])"
13791 [(set (match_dup 1)
13792 (and:QI (match_dup 1) (match_dup 2)))]
13795 ;; This matches cases where a stack pointer increment at the start of the
13796 ;; epilogue combines with a stack slot read loading the return value.
13798 [(set (match_operand:SI 0 "arith_reg_operand" "")
13799 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
13800 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
13801 "TARGET_SH1 && REGNO (operands[1]) != REGNO (operands[0])"
13804 ;; See the comment on the dt combiner pattern above.
13806 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
13807 (plus:SI (match_dup 0)
13809 (set (reg:SI T_REG)
13810 (eq:SI (match_dup 0) (const_int 0)))]
13814 ;; The following peepholes fold load sequences for which reload was not
13815 ;; able to generate a displacement addressing move insn.
13816 ;; This can happen when reload has to transform a move insn
13817 ;; without displacement into one with displacement. Or when reload can't
13818 ;; fit a displacement into the insn's constraints. In the latter case, the
13819 ;; load destination reg remains at r0, which reload compensates by inserting
13820 ;; another mov insn.
13824 ;; mov.{b,w} @(r0,r15),r0
13827 ;; mov.{b,w} @(54,r15),r3
13830 [(set (match_operand:SI 0 "arith_reg_dest" "")
13831 (match_operand:SI 1 "const_int_operand" ""))
13832 (set (match_operand:SI 2 "arith_reg_dest" "")
13834 (mem:QI (plus:SI (match_dup 0)
13835 (match_operand:SI 3 "arith_reg_operand" "")))))
13836 (set (match_operand:QI 4 "arith_reg_dest" "")
13837 (match_operand:QI 5 "arith_reg_operand" ""))]
13839 && sh_legitimate_index_p (QImode, operands[1], true, true)
13840 && REGNO (operands[2]) == REGNO (operands[5])
13841 && peep2_reg_dead_p (3, operands[5])"
13842 [(set (match_dup 4) (mem:QI (plus:SI (match_dup 3) (match_dup 1))))]
13846 [(set (match_operand:SI 0 "arith_reg_dest" "")
13847 (match_operand:SI 1 "const_int_operand" ""))
13848 (set (match_operand:SI 2 "arith_reg_dest" "")
13850 (mem:HI (plus:SI (match_dup 0)
13851 (match_operand:SI 3 "arith_reg_operand" "")))))
13852 (set (match_operand:HI 4 "arith_reg_dest" "")
13853 (match_operand:HI 5 "arith_reg_operand" ""))]
13855 && sh_legitimate_index_p (HImode, operands[1], true, true)
13856 && REGNO (operands[2]) == REGNO (operands[5])
13857 && peep2_reg_dead_p (3, operands[5])"
13858 [(set (match_dup 4) (mem:HI (plus:SI (match_dup 3) (match_dup 1))))]
13863 ;; mov.{b,w} @(r0,r15),r1
13865 ;; mov.{b,w} @(54,r15),r1
13868 [(set (match_operand:SI 0 "arith_reg_dest" "")
13869 (match_operand:SI 1 "const_int_operand" ""))
13870 (set (match_operand:SI 2 "arith_reg_dest" "")
13872 (mem:QI (plus:SI (match_dup 0)
13873 (match_operand:SI 3 "arith_reg_operand" "")))))]
13875 && sh_legitimate_index_p (QImode, operands[1], true, true)
13876 && (peep2_reg_dead_p (2, operands[0])
13877 || REGNO (operands[0]) == REGNO (operands[2]))"
13878 [(set (match_dup 2)
13879 (sign_extend:SI (mem:QI (plus:SI (match_dup 3) (match_dup 1)))))]
13883 [(set (match_operand:SI 0 "arith_reg_dest" "")
13884 (match_operand:SI 1 "const_int_operand" ""))
13885 (set (match_operand:SI 2 "arith_reg_dest" "")
13887 (mem:HI (plus:SI (match_dup 0)
13888 (match_operand:SI 3 "arith_reg_operand" "")))))]
13890 && sh_legitimate_index_p (HImode, operands[1], true, true)
13891 && (peep2_reg_dead_p (2, operands[0])
13892 || REGNO (operands[0]) == REGNO (operands[2]))"
13893 [(set (match_dup 2)
13894 (sign_extend:SI (mem:HI (plus:SI (match_dup 3) (match_dup 1)))))]
13898 ;; mov.{b,w} @(r0,r15),r0
13901 ;; mov.{b,w} @(r0,r15),r3
13903 ;; This can happen when initially a displacement address is picked, where
13904 ;; the destination reg is fixed to r0, and then the address is transformed
13905 ;; into 'r0 + reg'.
13907 [(set (match_operand:SI 0 "arith_reg_dest" "")
13909 (mem:QI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
13910 (match_operand:SI 2 "arith_reg_operand" "")))))
13911 (set (match_operand:QI 3 "arith_reg_dest" "")
13912 (match_operand:QI 4 "arith_reg_operand" ""))]
13914 && REGNO (operands[0]) == REGNO (operands[4])
13915 && peep2_reg_dead_p (2, operands[0])"
13916 [(set (match_dup 3)
13917 (mem:QI (plus:SI (match_dup 1) (match_dup 2))))]
13921 [(set (match_operand:SI 0 "arith_reg_dest" "")
13923 (mem:HI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
13924 (match_operand:SI 2 "arith_reg_operand" "")))))
13925 (set (match_operand:HI 3 "arith_reg_dest" "")
13926 (match_operand:HI 4 "arith_reg_operand" ""))]
13928 && REGNO (operands[0]) == REGNO (operands[4])
13929 && peep2_reg_dead_p (2, operands[0])"
13930 [(set (match_dup 3)
13931 (mem:HI (plus:SI (match_dup 1) (match_dup 2))))]
13935 [(set (match_operand:SI 0 "register_operand" "=r")
13936 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
13937 (set (mem:SF (match_dup 0))
13938 (match_operand:SF 2 "general_movsrc_operand" ""))]
13939 "TARGET_SH1 && REGNO (operands[0]) == 0
13940 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
13941 || (GET_CODE (operands[2]) == SUBREG
13942 && REGNO (SUBREG_REG (operands[2])) < 16))
13943 && reg_unused_after (operands[0], insn)"
13944 "mov.l %2,@(%0,%1)")
13947 [(set (match_operand:SI 0 "register_operand" "=r")
13948 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
13949 (set (match_operand:SF 2 "general_movdst_operand" "")
13951 (mem:SF (match_dup 0)))]
13952 "TARGET_SH1 && REGNO (operands[0]) == 0
13953 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
13954 || (GET_CODE (operands[2]) == SUBREG
13955 && REGNO (SUBREG_REG (operands[2])) < 16))
13956 && reg_unused_after (operands[0], insn)"
13957 "mov.l @(%0,%1),%2")
13960 [(set (match_operand:SI 0 "register_operand" "=r")
13961 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
13962 (set (mem:SF (match_dup 0))
13963 (match_operand:SF 2 "general_movsrc_operand" ""))]
13964 "TARGET_SH2E && REGNO (operands[0]) == 0
13965 && ((REG_P (operands[2])
13966 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
13967 || (GET_CODE (operands[2]) == SUBREG
13968 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
13969 && reg_unused_after (operands[0], insn)"
13970 "fmov{.s|} %2,@(%0,%1)")
13973 [(set (match_operand:SI 0 "register_operand" "=r")
13974 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
13975 (set (match_operand:SF 2 "general_movdst_operand" "")
13977 (mem:SF (match_dup 0)))]
13978 "TARGET_SH2E && REGNO (operands[0]) == 0
13979 && ((REG_P (operands[2])
13980 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
13981 || (GET_CODE (operands[2]) == SUBREG
13982 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
13983 && reg_unused_after (operands[0], insn)"
13984 "fmov{.s|} @(%0,%1),%2")
13986 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF).
13987 (define_insn "sp_switch_1"
13988 [(set (reg:SI SP_REG) (unspec_volatile [(match_operand:SI 0 "" "")]
13989 UNSPECV_SP_SWITCH_B))]
13992 return "mov.l r0,@-r15" "\n"
13993 " mov.l %0,r0" "\n"
13994 " mov.l @r0,r0" "\n"
13995 " mov.l r15,@-r0" "\n"
13998 [(set_attr "length" "10")])
14000 ;; Switch back to the original stack for interrupt functions with the
14001 ;; sp_switch attribute.
14002 (define_insn "sp_switch_2"
14003 [(unspec_volatile [(const_int 0)]
14004 UNSPECV_SP_SWITCH_E)]
14007 return "mov.l @r15,r15" "\n"
14010 [(set_attr "length" "4")])
14012 ;; -------------------------------------------------------------------------
14013 ;; Integer vector moves
14014 ;; -------------------------------------------------------------------------
14016 (define_expand "movv8qi"
14017 [(set (match_operand:V8QI 0 "general_movdst_operand" "")
14018 (match_operand:V8QI 1 "general_movsrc_operand" ""))]
14021 prepare_move_operands (operands, V8QImode);
14024 (define_insn "movv8qi_i"
14025 [(set (match_operand:V8QI 0 "general_movdst_operand" "=r,r,r,rl,m")
14026 (match_operand:V8QI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
14028 && (register_operand (operands[0], V8QImode)
14029 || sh_register_operand (operands[1], V8QImode))"
14036 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
14037 (set_attr "length" "4,4,16,4,4")])
14040 [(set (match_operand:V8QI 0 "arith_reg_dest" "")
14041 (subreg:V8QI (const_int 0) 0))]
14043 [(set (match_dup 0)
14044 (const_vector:V8QI [(const_int 0) (const_int 0) (const_int 0)
14045 (const_int 0) (const_int 0) (const_int 0)
14046 (const_int 0) (const_int 0)]))])
14049 [(set (match_operand 0 "arith_reg_dest" "")
14050 (match_operand 1 "sh_rep_vec" ""))]
14051 "TARGET_SHMEDIA && reload_completed
14052 && GET_MODE (operands[0]) == GET_MODE (operands[1])
14053 && sh_vector_mode_supported_p (GET_MODE (operands[0]))
14054 && GET_MODE_SIZE (GET_MODE (operands[0])) == 8
14055 && (XVECEXP (operands[1], 0, 0) != const0_rtx
14056 || XVECEXP (operands[1], 0, 1) != const0_rtx)
14057 && (XVECEXP (operands[1], 0, 0) != constm1_rtx
14058 || XVECEXP (operands[1], 0, 1) != constm1_rtx)"
14059 [(set (match_dup 0) (match_dup 1))
14062 int unit_size = GET_MODE_UNIT_SIZE (GET_MODE (operands[1]));
14063 rtx elt1 = XVECEXP (operands[1], 0, 1);
14066 operands[2] = gen_mshflo_l (operands[0], operands[0], operands[0]);
14070 operands[0] = gen_rtx_REG (V4HImode, true_regnum (operands[0]));
14071 operands[2] = gen_mperm_w0 (operands[0], operands[0]);
14073 operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0]));
14074 operands[1] = XVECEXP (operands[1], 0, 0);
14077 if (CONST_INT_P (operands[1]) && CONST_INT_P (elt1))
14079 = GEN_INT (TARGET_LITTLE_ENDIAN
14080 ? (INTVAL (operands[1]) & 0xff) + (INTVAL (elt1) << 8)
14081 : (INTVAL (operands[1]) << 8) + (INTVAL (elt1) & 0xff));
14084 operands[0] = gen_rtx_REG (V2QImode, true_regnum (operands[0]));
14086 = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, operands[1], elt1));
14092 [(set (match_operand 0 "arith_reg_dest" "")
14093 (match_operand 1 "sh_const_vec" ""))]
14094 "TARGET_SHMEDIA && reload_completed
14095 && GET_MODE (operands[0]) == GET_MODE (operands[1])
14096 && sh_vector_mode_supported_p (GET_MODE (operands[0]))"
14097 [(set (match_dup 0) (match_dup 1))]
14099 rtx v = operands[1];
14100 machine_mode new_mode
14101 = mode_for_size (GET_MODE_BITSIZE (GET_MODE (v)), MODE_INT, 0);
14103 operands[0] = gen_rtx_REG (new_mode, true_regnum (operands[0]));
14105 = simplify_subreg (new_mode, operands[1], GET_MODE (operands[1]), 0);
14108 (define_expand "movv2hi"
14109 [(set (match_operand:V2HI 0 "general_movdst_operand" "")
14110 (match_operand:V2HI 1 "general_movsrc_operand" ""))]
14113 prepare_move_operands (operands, V2HImode);
14116 (define_insn "movv2hi_i"
14117 [(set (match_operand:V2HI 0 "general_movdst_operand" "=r,r,r,rl,m")
14118 (match_operand:V2HI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
14120 && (register_operand (operands[0], V2HImode)
14121 || sh_register_operand (operands[1], V2HImode))"
14128 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
14129 (set_attr "length" "4,4,16,4,4")
14130 (set (attr "highpart")
14131 (cond [(match_test "sh_contains_memref_p (insn)")
14132 (const_string "user")]
14133 (const_string "ignore")))])
14135 (define_expand "movv4hi"
14136 [(set (match_operand:V4HI 0 "general_movdst_operand" "")
14137 (match_operand:V4HI 1 "general_movsrc_operand" ""))]
14140 prepare_move_operands (operands, V4HImode);
14143 (define_insn "movv4hi_i"
14144 [(set (match_operand:V4HI 0 "general_movdst_operand" "=r,r,r,rl,m")
14145 (match_operand:V4HI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
14147 && (register_operand (operands[0], V4HImode)
14148 || sh_register_operand (operands[1], V4HImode))"
14155 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
14156 (set_attr "length" "4,4,16,4,4")
14157 (set_attr "highpart" "depend")])
14159 (define_expand "movv2si"
14160 [(set (match_operand:V2SI 0 "general_movdst_operand" "")
14161 (match_operand:V2SI 1 "general_movsrc_operand" ""))]
14164 prepare_move_operands (operands, V2SImode);
14167 (define_insn "movv2si_i"
14168 [(set (match_operand:V2SI 0 "general_movdst_operand" "=r,r,r,rl,m")
14169 (match_operand:V2SI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
14171 && (register_operand (operands[0], V2SImode)
14172 || sh_register_operand (operands[1], V2SImode))"
14179 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
14180 (set_attr "length" "4,4,16,4,4")
14181 (set_attr "highpart" "depend")])
14183 ;; -------------------------------------------------------------------------
14184 ;; Multimedia Intrinsics
14185 ;; -------------------------------------------------------------------------
14187 (define_insn "absv2si2"
14188 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14189 (abs:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")))]
14192 [(set_attr "type" "mcmp_media")
14193 (set_attr "highpart" "depend")])
14195 (define_insn "absv4hi2"
14196 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14197 (abs:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")))]
14200 [(set_attr "type" "mcmp_media")
14201 (set_attr "highpart" "depend")])
14203 (define_insn "addv2si3"
14204 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14205 (plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r")
14206 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
14208 "madd.l %1, %2, %0"
14209 [(set_attr "type" "arith_media")
14210 (set_attr "highpart" "depend")])
14212 (define_insn "addv4hi3"
14213 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14214 (plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r")
14215 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
14217 "madd.w %1, %2, %0"
14218 [(set_attr "type" "arith_media")
14219 (set_attr "highpart" "depend")])
14221 (define_insn_and_split "addv2hi3"
14222 [(set (match_operand:V2HI 0 "arith_reg_dest" "=r")
14223 (plus:V2HI (match_operand:V2HI 1 "extend_reg_operand" "%r")
14224 (match_operand:V2HI 2 "extend_reg_operand" "r")))]
14230 rtx src0 = simplify_gen_subreg (V4HImode, operands[1], V2HImode, 0);
14231 rtx src1 = simplify_gen_subreg (V4HImode, operands[2], V2HImode, 0);
14232 rtx v4hi_dst = simplify_gen_subreg (V4HImode, operands[0], V2HImode, 0);
14233 rtx di_dst = simplify_gen_subreg (DImode, operands[0], V2HImode, 0);
14234 rtx si_dst = simplify_gen_subreg (SImode, operands[0], V2HImode, 0);
14236 emit_insn (gen_addv4hi3 (v4hi_dst, src0, src1));
14237 emit_insn (gen_truncdisi2 (si_dst, di_dst));
14240 [(set_attr "highpart" "must_split")])
14242 (define_insn "ssaddv2si3"
14243 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14244 (ss_plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r")
14245 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
14247 "madds.l %1, %2, %0"
14248 [(set_attr "type" "mcmp_media")
14249 (set_attr "highpart" "depend")])
14251 (define_insn "usaddv8qi3"
14252 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14253 (us_plus:V8QI (match_operand:V8QI 1 "arith_reg_operand" "%r")
14254 (match_operand:V8QI 2 "arith_reg_operand" "r")))]
14256 "madds.ub %1, %2, %0"
14257 [(set_attr "type" "mcmp_media")
14258 (set_attr "highpart" "depend")])
14260 (define_insn "ssaddv4hi3"
14261 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14262 (ss_plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r")
14263 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
14265 "madds.w %1, %2, %0"
14266 [(set_attr "type" "mcmp_media")
14267 (set_attr "highpart" "depend")])
14269 (define_insn "negcmpeqv8qi"
14270 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14272 (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
14273 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
14275 "mcmpeq.b %N1, %N2, %0"
14276 [(set_attr "type" "mcmp_media")
14277 (set_attr "highpart" "depend")])
14279 (define_insn "negcmpeqv2si"
14280 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14282 (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
14283 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
14285 "mcmpeq.l %N1, %N2, %0"
14286 [(set_attr "type" "mcmp_media")
14287 (set_attr "highpart" "depend")])
14289 (define_insn "negcmpeqv4hi"
14290 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14292 (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
14293 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
14295 "mcmpeq.w %N1, %N2, %0"
14296 [(set_attr "type" "mcmp_media")
14297 (set_attr "highpart" "depend")])
14299 (define_insn "negcmpgtuv8qi"
14300 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14301 (neg:V8QI (gtu:V8QI
14302 (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
14303 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
14305 "mcmpgt.ub %N1, %N2, %0"
14306 [(set_attr "type" "mcmp_media")
14307 (set_attr "highpart" "depend")])
14309 (define_insn "negcmpgtv2si"
14310 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14312 (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
14313 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
14315 "mcmpgt.l %N1, %N2, %0"
14316 [(set_attr "type" "mcmp_media")
14317 (set_attr "highpart" "depend")])
14319 (define_insn "negcmpgtv4hi"
14320 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14322 (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
14323 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
14325 "mcmpgt.w %N1, %N2, %0"
14326 [(set_attr "type" "mcmp_media")
14327 (set_attr "highpart" "depend")])
14329 (define_insn "mcmv"
14330 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14331 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14332 (match_operand:DI 2 "arith_reg_operand" "r"))
14333 (and:DI (match_operand:DI 3 "arith_reg_operand" "0")
14334 (not:DI (match_dup 2)))))]
14337 [(set_attr "type" "arith_media")
14338 (set_attr "highpart" "depend")])
14340 (define_insn "mcnvs_lw"
14341 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14343 (ss_truncate:V2HI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ"))
14345 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
14347 "mcnvs.lw %N1, %N2, %0"
14348 [(set_attr "type" "mcmp_media")])
14350 (define_insn "mcnvs_wb"
14351 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14353 (ss_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
14355 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
14357 "mcnvs.wb %N1, %N2, %0"
14358 [(set_attr "type" "mcmp_media")])
14360 (define_insn "mcnvs_wub"
14361 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14363 (us_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
14365 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
14367 "mcnvs.wub %N1, %N2, %0"
14368 [(set_attr "type" "mcmp_media")])
14370 (define_insn "mextr_rl"
14371 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14372 (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14373 (match_operand:HI 3 "mextr_bit_offset" "i"))
14374 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
14375 (match_operand:HI 4 "mextr_bit_offset" "i"))))]
14376 "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
14378 static char templ[21];
14379 sprintf (templ, "mextr%d %%N1, %%N2, %%0",
14380 (int) INTVAL (operands[3]) >> 3);
14383 [(set_attr "type" "arith_media")])
14385 (define_insn "*mextr_lr"
14386 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14387 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14388 (match_operand:HI 3 "mextr_bit_offset" "i"))
14389 (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
14390 (match_operand:HI 4 "mextr_bit_offset" "i"))))]
14391 "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
14393 static char templ[21];
14394 sprintf (templ, "mextr%d %%N2, %%N1, %%0",
14395 (int) INTVAL (operands[4]) >> 3);
14398 [(set_attr "type" "arith_media")])
14400 ; mextrN can be modelled with vec_select / vec_concat, but the selection
14401 ; vector then varies depending on endianness.
14402 (define_expand "mextr1"
14403 [(match_operand:DI 0 "arith_reg_dest" "")
14404 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14405 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14408 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14409 GEN_INT (1 * 8), GEN_INT (7 * 8)));
14413 (define_expand "mextr2"
14414 [(match_operand:DI 0 "arith_reg_dest" "")
14415 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14416 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14419 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14420 GEN_INT (2 * 8), GEN_INT (6 * 8)));
14424 (define_expand "mextr3"
14425 [(match_operand:DI 0 "arith_reg_dest" "")
14426 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14427 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14430 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14431 GEN_INT (3 * 8), GEN_INT (5 * 8)));
14435 (define_expand "mextr4"
14436 [(match_operand:DI 0 "arith_reg_dest" "")
14437 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14438 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14441 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14442 GEN_INT (4 * 8), GEN_INT (4 * 8)));
14446 (define_expand "mextr5"
14447 [(match_operand:DI 0 "arith_reg_dest" "")
14448 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14449 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14452 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14453 GEN_INT (5 * 8), GEN_INT (3 * 8)));
14457 (define_expand "mextr6"
14458 [(match_operand:DI 0 "arith_reg_dest" "")
14459 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14460 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14463 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14464 GEN_INT (6 * 8), GEN_INT (2 * 8)));
14468 (define_expand "mextr7"
14469 [(match_operand:DI 0 "arith_reg_dest" "")
14470 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14471 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14474 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14475 GEN_INT (7 * 8), GEN_INT (1 * 8)));
14479 (define_expand "mmacfx_wl"
14480 [(match_operand:V2SI 0 "arith_reg_dest" "")
14481 (match_operand:V2HI 1 "extend_reg_operand" "")
14482 (match_operand:V2HI 2 "extend_reg_operand" "")
14483 (match_operand:V2SI 3 "arith_reg_operand" "")]
14486 emit_insn (gen_mmacfx_wl_i (operands[0], operands[3],
14487 operands[1], operands[2]));
14491 ;; This could be highpart ignore if it only had inputs 2 or 3, but input 1
14493 (define_insn "mmacfx_wl_i"
14494 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14496 (match_operand:V2SI 1 "arith_reg_operand" "0")
14501 (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r"))
14502 (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r"))))
14505 "mmacfx.wl %2, %3, %0"
14506 [(set_attr "type" "mac_media")
14507 (set_attr "highpart" "depend")])
14509 (define_expand "mmacnfx_wl"
14510 [(match_operand:V2SI 0 "arith_reg_dest" "")
14511 (match_operand:V2HI 1 "extend_reg_operand" "")
14512 (match_operand:V2HI 2 "extend_reg_operand" "")
14513 (match_operand:V2SI 3 "arith_reg_operand" "")]
14516 emit_insn (gen_mmacnfx_wl_i (operands[0], operands[3],
14517 operands[1], operands[2]));
14521 (define_insn "mmacnfx_wl_i"
14522 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14524 (match_operand:V2SI 1 "arith_reg_operand" "0")
14529 (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r"))
14530 (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r"))))
14533 "mmacnfx.wl %2, %3, %0"
14534 [(set_attr "type" "mac_media")
14535 (set_attr "highpart" "depend")])
14537 (define_insn "mulv2si3"
14538 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14539 (mult:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
14540 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
14542 "mmul.l %1, %2, %0"
14543 [(set_attr "type" "d2mpy_media")
14544 (set_attr "highpart" "depend")])
14546 (define_insn "mulv4hi3"
14547 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14548 (mult:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
14549 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
14551 "mmul.w %1, %2, %0"
14552 [(set_attr "type" "dmpy_media")
14553 (set_attr "highpart" "depend")])
14555 (define_insn "mmulfx_l"
14556 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14560 (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r"))
14561 (sign_extend:V2DI (match_operand:V2SI 2 "arith_reg_operand" "r")))
14564 "mmulfx.l %1, %2, %0"
14565 [(set_attr "type" "d2mpy_media")
14566 (set_attr "highpart" "depend")])
14568 (define_insn "mmulfx_w"
14569 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14573 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14574 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
14577 "mmulfx.w %1, %2, %0"
14578 [(set_attr "type" "dmpy_media")
14579 (set_attr "highpart" "depend")])
14581 (define_insn "mmulfxrp_w"
14582 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14587 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14588 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
14592 "mmulfxrp.w %1, %2, %0"
14593 [(set_attr "type" "dmpy_media")
14594 (set_attr "highpart" "depend")])
14597 (define_expand "mmulhi_wl"
14598 [(match_operand:V2SI 0 "arith_reg_dest" "")
14599 (match_operand:V4HI 1 "arith_reg_operand" "")
14600 (match_operand:V4HI 2 "arith_reg_operand" "")]
14603 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul23_wl : gen_mmul01_wl)
14604 (operands[0], operands[1], operands[2]));
14608 (define_expand "mmullo_wl"
14609 [(match_operand:V2SI 0 "arith_reg_dest" "")
14610 (match_operand:V4HI 1 "arith_reg_operand" "")
14611 (match_operand:V4HI 2 "arith_reg_operand" "")]
14614 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul01_wl : gen_mmul23_wl)
14615 (operands[0], operands[1], operands[2]));
14619 (define_insn "mmul23_wl"
14620 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14623 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14624 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
14625 (parallel [(const_int 2) (const_int 3)])))]
14628 return (TARGET_LITTLE_ENDIAN
14629 ? "mmulhi.wl %1, %2, %0"
14630 : "mmullo.wl %1, %2, %0");
14632 [(set_attr "type" "dmpy_media")
14633 (set (attr "highpart")
14634 (cond [(eq_attr "endian" "big") (const_string "ignore")]
14635 (const_string "user")))])
14637 (define_insn "mmul01_wl"
14638 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14641 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14642 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
14643 (parallel [(const_int 0) (const_int 1)])))]
14646 return (TARGET_LITTLE_ENDIAN
14647 ? "mmullo.wl %1, %2, %0"
14648 : "mmulhi.wl %1, %2, %0");
14650 [(set_attr "type" "dmpy_media")
14651 (set (attr "highpart")
14652 (cond [(eq_attr "endian" "little") (const_string "ignore")]
14653 (const_string "user")))])
14656 (define_expand "mmulsum_wq"
14657 [(match_operand:DI 0 "arith_reg_dest" "")
14658 (match_operand:V4HI 1 "arith_reg_operand" "")
14659 (match_operand:V4HI 2 "arith_reg_operand" "")
14660 (match_operand:DI 3 "arith_reg_operand" "")]
14663 emit_insn (gen_mmulsum_wq_i (operands[0], operands[3],
14664 operands[1], operands[2]));
14668 (define_insn "mmulsum_wq_i"
14669 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14670 (plus:DI (match_operand:DI 1 "arith_reg_operand" "0")
14675 (sign_extend:V4DI (match_operand:V4HI 2 "arith_reg_operand" "r"))
14676 (sign_extend:V4DI (match_operand:V4HI 3 "arith_reg_operand" "r")))
14677 (parallel [(const_int 0)]))
14678 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
14679 (sign_extend:V4DI (match_dup 3)))
14680 (parallel [(const_int 1)])))
14682 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
14683 (sign_extend:V4DI (match_dup 3)))
14684 (parallel [(const_int 2)]))
14685 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
14686 (sign_extend:V4DI (match_dup 3)))
14687 (parallel [(const_int 3)]))))))]
14689 "mmulsum.wq %2, %3, %0"
14690 [(set_attr "type" "mac_media")])
14692 (define_expand "mperm_w"
14693 [(match_operand:V4HI 0 "arith_reg_dest" "=r")
14694 (match_operand:V4HI 1 "arith_reg_operand" "r")
14695 (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")]
14698 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mperm_w_little : gen_mperm_w_big)
14699 (operands[0], operands[1], operands[2]));
14703 ; This use of vec_select isn't exactly correct according to rtl.texi
14704 ; (because not constant), but it seems a straightforward extension.
14705 (define_insn "mperm_w_little"
14706 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14708 (match_operand:V4HI 1 "arith_reg_operand" "r")
14710 [(zero_extract:QI (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")
14711 (const_int 2) (const_int 0))
14712 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 2))
14713 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 4))
14714 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 6))])))]
14715 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
14716 "mperm.w %1, %N2, %0"
14717 [(set_attr "type" "arith_media")])
14719 (define_insn "mperm_w_big"
14720 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14722 (match_operand:V4HI 1 "arith_reg_operand" "r")
14724 [(zero_extract:QI (not:QI (match_operand:QI 2
14725 "extend_reg_or_0_operand" "rZ"))
14726 (const_int 2) (const_int 0))
14727 (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 2))
14728 (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 4))
14729 (zero_extract:QI (not:QI (match_dup 2))
14730 (const_int 2) (const_int 6))])))]
14731 "TARGET_SHMEDIA && TARGET_BIG_ENDIAN"
14732 "mperm.w %1, %N2, %0"
14733 [(set_attr "type" "arith_media")])
14735 (define_insn "mperm_w0"
14736 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14737 (vec_duplicate:V4HI (truncate:HI (match_operand 1
14738 "trunc_hi_operand" "r"))))]
14740 "mperm.w %1, r63, %0"
14741 [(set_attr "type" "arith_media")
14742 (set_attr "highpart" "ignore")])
14744 (define_expand "msad_ubq"
14745 [(match_operand:DI 0 "arith_reg_dest" "")
14746 (match_operand:V8QI 1 "arith_reg_or_0_operand" "")
14747 (match_operand:V8QI 2 "arith_reg_or_0_operand" "")
14748 (match_operand:DI 3 "arith_reg_operand" "")]
14751 emit_insn (gen_msad_ubq_i (operands[0], operands[3],
14752 operands[1], operands[2]));
14756 (define_insn "msad_ubq_i"
14757 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14762 (match_operand:DI 1 "arith_reg_operand" "0")
14763 (abs:DI (vec_select:DI
14766 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
14768 (match_operand:V8QI 3 "arith_reg_or_0_operand" "rZ")))
14769 (parallel [(const_int 0)]))))
14770 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14771 (zero_extend:V8DI (match_dup 3)))
14772 (parallel [(const_int 1)]))))
14774 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14775 (zero_extend:V8DI (match_dup 3)))
14776 (parallel [(const_int 2)])))
14777 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14778 (zero_extend:V8DI (match_dup 3)))
14779 (parallel [(const_int 3)])))))
14782 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14783 (zero_extend:V8DI (match_dup 3)))
14784 (parallel [(const_int 4)])))
14785 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14786 (zero_extend:V8DI (match_dup 3)))
14787 (parallel [(const_int 5)]))))
14789 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14790 (zero_extend:V8DI (match_dup 3)))
14791 (parallel [(const_int 6)])))
14792 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14793 (zero_extend:V8DI (match_dup 3)))
14794 (parallel [(const_int 7)])))))))]
14796 "msad.ubq %N2, %N3, %0"
14797 [(set_attr "type" "mac_media")])
14799 (define_insn "mshalds_l"
14800 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14803 (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r"))
14804 (and:DI (match_operand:DI 2 "arith_reg_operand" "r")
14805 (const_int 31)))))]
14807 "mshalds.l %1, %2, %0"
14808 [(set_attr "type" "mcmp_media")
14809 (set_attr "highpart" "depend")])
14811 (define_insn "mshalds_w"
14812 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14815 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14816 (and:DI (match_operand:DI 2 "arith_reg_operand" "r")
14817 (const_int 15)))))]
14819 "mshalds.w %1, %2, %0"
14820 [(set_attr "type" "mcmp_media")
14821 (set_attr "highpart" "depend")])
14823 (define_insn "ashrv2si3"
14824 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14825 (ashiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
14826 (match_operand:DI 2 "arith_reg_operand" "r")))]
14828 "mshard.l %1, %2, %0"
14829 [(set_attr "type" "arith_media")
14830 (set_attr "highpart" "depend")])
14832 (define_insn "ashrv4hi3"
14833 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14834 (ashiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
14835 (match_operand:DI 2 "arith_reg_operand" "r")))]
14837 "mshard.w %1, %2, %0"
14838 [(set_attr "type" "arith_media")
14839 (set_attr "highpart" "depend")])
14841 (define_insn "mshards_q"
14842 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
14844 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
14845 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ"))))]
14847 "mshards.q %1, %N2, %0"
14848 [(set_attr "type" "mcmp_media")])
14850 (define_expand "mshfhi_b"
14851 [(match_operand:V8QI 0 "arith_reg_dest" "")
14852 (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
14853 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
14856 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_b : gen_mshf0_b)
14857 (operands[0], operands[1], operands[2]));
14861 (define_expand "mshflo_b"
14862 [(match_operand:V8QI 0 "arith_reg_dest" "")
14863 (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
14864 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
14867 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_b : gen_mshf4_b)
14868 (operands[0], operands[1], operands[2]));
14872 (define_insn "mshf4_b"
14874 (match_operand:V8QI 0 "arith_reg_dest" "=r")
14876 (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
14877 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
14878 (parallel [(const_int 4) (const_int 12) (const_int 5) (const_int 13)
14879 (const_int 6) (const_int 14) (const_int 7) (const_int 15)])))]
14882 return (TARGET_LITTLE_ENDIAN
14883 ? "mshfhi.b %N1, %N2, %0"
14884 : "mshflo.b %N1, %N2, %0");
14886 [(set_attr "type" "arith_media")
14887 (set (attr "highpart")
14888 (cond [(eq_attr "endian" "big") (const_string "ignore")]
14889 (const_string "user")))])
14891 (define_insn "mshf0_b"
14893 (match_operand:V8QI 0 "arith_reg_dest" "=r")
14895 (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
14896 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
14897 (parallel [(const_int 0) (const_int 8) (const_int 1) (const_int 9)
14898 (const_int 2) (const_int 10) (const_int 3) (const_int 11)])))]
14901 return (TARGET_LITTLE_ENDIAN
14902 ? "mshflo.b %N1, %N2, %0"
14903 : "mshfhi.b %N1, %N2, %0");
14905 [(set_attr "type" "arith_media")
14906 (set (attr "highpart")
14907 (cond [(eq_attr "endian" "little") (const_string "ignore")]
14908 (const_string "user")))])
14910 (define_expand "mshfhi_l"
14911 [(match_operand:V2SI 0 "arith_reg_dest" "")
14912 (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
14913 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
14916 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_l : gen_mshf0_l)
14917 (operands[0], operands[1], operands[2]));
14921 (define_expand "mshflo_l"
14922 [(match_operand:V2SI 0 "arith_reg_dest" "")
14923 (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
14924 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
14927 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_l : gen_mshf4_l)
14928 (operands[0], operands[1], operands[2]));
14932 (define_insn "mshf4_l"
14933 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14935 (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
14936 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
14937 (parallel [(const_int 1) (const_int 3)])))]
14940 return (TARGET_LITTLE_ENDIAN
14941 ? "mshfhi.l %N1, %N2, %0"
14942 : "mshflo.l %N1, %N2, %0");
14944 [(set_attr "type" "arith_media")
14945 (set (attr "highpart")
14946 (cond [(eq_attr "endian" "big") (const_string "ignore")]
14947 (const_string "user")))])
14949 (define_insn "mshf0_l"
14950 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14952 (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
14953 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
14954 (parallel [(const_int 0) (const_int 2)])))]
14957 return (TARGET_LITTLE_ENDIAN
14958 ? "mshflo.l %N1, %N2, %0"
14959 : "mshfhi.l %N1, %N2, %0");
14961 [(set_attr "type" "arith_media")
14962 (set (attr "highpart")
14963 (cond [(eq_attr "endian" "little") (const_string "ignore")]
14964 (const_string "user")))])
14966 (define_expand "mshfhi_w"
14967 [(match_operand:V4HI 0 "arith_reg_dest" "")
14968 (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
14969 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
14972 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_w : gen_mshf0_w)
14973 (operands[0], operands[1], operands[2]));
14977 (define_expand "mshflo_w"
14978 [(match_operand:V4HI 0 "arith_reg_dest" "")
14979 (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
14980 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
14983 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_w : gen_mshf4_w)
14984 (operands[0], operands[1], operands[2]));
14988 (define_insn "mshf4_w"
14989 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14991 (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
14992 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
14993 (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))]
14996 return (TARGET_LITTLE_ENDIAN
14997 ? "mshfhi.w %N1, %N2, %0"
14998 : "mshflo.w %N1, %N2, %0");
15000 [(set_attr "type" "arith_media")
15001 (set (attr "highpart")
15002 (cond [(eq_attr "endian" "big") (const_string "ignore")]
15003 (const_string "user")))])
15005 (define_insn "mshf0_w"
15006 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15008 (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
15009 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
15010 (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))]
15013 return (TARGET_LITTLE_ENDIAN
15014 ? "mshflo.w %N1, %N2, %0"
15015 : "mshfhi.w %N1, %N2, %0");
15017 [(set_attr "type" "arith_media")
15018 (set (attr "highpart")
15019 (cond [(eq_attr "endian" "little") (const_string "ignore")]
15020 (const_string "user")))])
15022 (define_insn "mshflo_w_x"
15023 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15025 (vec_concat:V4HI (match_operand:V2HI 1 "extend_reg_or_0_operand" "rZ")
15026 (match_operand:V2HI 2 "extend_reg_or_0_operand" "rZ"))
15027 (parallel [(const_int 2) (const_int 0) (const_int 3) (const_int 1)])))]
15029 "mshflo.w %N1, %N2, %0"
15030 [(set_attr "type" "arith_media")
15031 (set_attr "highpart" "ignore")])
15033 ;; These are useful to expand ANDs and as combiner patterns.
15034 (define_insn_and_split "mshfhi_l_di"
15035 [(set (match_operand:DI 0 "arith_reg_dest" "=r,f")
15036 (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ,f")
15038 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ,?f")
15039 (const_int -4294967296))))]
15042 mshfhi.l %N1, %N2, %0
15044 "TARGET_SHMEDIA && reload_completed
15045 && ! GENERAL_REGISTER_P (true_regnum (operands[0]))"
15046 [(set (match_dup 3) (match_dup 4))
15047 (set (match_dup 5) (match_dup 6))]
15049 operands[3] = gen_lowpart (SImode, operands[0]);
15050 operands[4] = gen_highpart (SImode, operands[1]);
15051 operands[5] = gen_highpart (SImode, operands[0]);
15052 operands[6] = gen_highpart (SImode, operands[2]);
15054 [(set_attr "type" "arith_media")])
15056 (define_insn "*mshfhi_l_di_rev"
15057 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15058 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15059 (const_int -4294967296))
15060 (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
15063 "mshfhi.l %N2, %N1, %0"
15064 [(set_attr "type" "arith_media")])
15067 [(set (match_operand:DI 0 "arith_reg_dest" "")
15068 (ior:DI (zero_extend:DI (match_operand:SI 1
15069 "extend_reg_or_0_operand" ""))
15070 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "")
15071 (const_int -4294967296))))
15072 (clobber (match_operand:DI 3 "arith_reg_dest" ""))]
15076 emit_insn (gen_ashldi3_media (operands[3],
15077 simplify_gen_subreg (DImode, operands[1],
15080 emit_insn (gen_mshfhi_l_di (operands[0], operands[3], operands[2]));
15084 (define_insn "mshflo_l_di"
15085 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15086 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15087 (const_int 4294967295))
15088 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
15092 "mshflo.l %N1, %N2, %0"
15093 [(set_attr "type" "arith_media")
15094 (set_attr "highpart" "ignore")])
15096 (define_insn "*mshflo_l_di_rev"
15097 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15098 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15100 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
15101 (const_int 4294967295))))]
15104 "mshflo.l %N2, %N1, %0"
15105 [(set_attr "type" "arith_media")
15106 (set_attr "highpart" "ignore")])
15108 ;; Combiner pattern for trampoline initialization.
15109 (define_insn_and_split "*double_shori"
15110 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15111 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
15113 (match_operand:DI 2 "const_int_operand" "n")))]
15115 && ! (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xffffffffUL)"
15117 "rtx_equal_p (operands[0], operands[1])"
15120 HOST_WIDE_INT v = INTVAL (operands[2]);
15122 emit_insn (gen_shori_media (operands[0], operands[0], GEN_INT (v >> 16)));
15123 emit_insn (gen_shori_media (operands[0], operands[0], GEN_INT (v & 65535)));
15126 [(set_attr "highpart" "ignore")])
15128 (define_insn "*mshflo_l_di_x"
15129 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15130 (ior:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_or_0_operand"
15132 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
15135 "mshflo.l %N1, %N2, %0"
15136 [(set_attr "type" "arith_media")
15137 (set_attr "highpart" "ignore")])
15139 (define_insn_and_split "concat_v2sf"
15140 [(set (match_operand:V2SF 0 "register_operand" "=r,f,f?")
15141 ;; (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,0,f")
15142 (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,f,f")
15143 (match_operand:SF 2 "register_operand" "rZ,f,f")))]
15146 mshflo.l %N1, %N2, %0
15149 "TARGET_SHMEDIA && reload_completed
15150 && ! GENERAL_REGISTER_P (true_regnum (operands[0]))"
15151 [(set (match_dup 3) (match_dup 1))
15152 (set (match_dup 4) (match_dup 2))]
15154 operands[3] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 0);
15155 operands[4] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 4);
15157 [(set_attr "type" "arith_media")
15158 (set_attr "highpart" "ignore")])
15160 (define_insn "*mshflo_l_di_x_rev"
15161 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15162 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15165 (match_operand:SI 2 "extend_reg_or_0_operand" "rZ"))))]
15167 "mshflo.l %N2, %N1, %0"
15168 [(set_attr "type" "arith_media")
15169 (set_attr "highpart" "ignore")])
15171 (define_insn "ashlv2si3"
15172 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15173 (ashift:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
15174 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
15176 "mshlld.l %1, %2, %0"
15177 [(set_attr "type" "arith_media")
15178 (set_attr "highpart" "depend")])
15181 [(set (match_operand 0 "any_register_operand" "")
15182 (match_operator 3 "shift_operator"
15183 [(match_operand 1 "any_register_operand" "")
15184 (match_operand 2 "shift_count_reg_operand" "")]))]
15185 "TARGET_SHMEDIA && ! register_operand (operands[2], VOIDmode)"
15186 [(set (match_dup 0) (match_dup 3))]
15188 rtx count = operands[2];
15189 machine_mode outer_mode = GET_MODE (operands[2]), inner_mode;
15191 while (GET_CODE (count) == ZERO_EXTEND || GET_CODE (count) == SIGN_EXTEND
15192 || (GET_CODE (count) == SUBREG && SUBREG_BYTE (count) == 0)
15193 || GET_CODE (count) == TRUNCATE)
15194 count = XEXP (count, 0);
15195 inner_mode = GET_MODE (count);
15196 count = simplify_gen_subreg (outer_mode, count, inner_mode,
15197 subreg_lowpart_offset (outer_mode, inner_mode));
15198 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), GET_MODE (operands[3]),
15199 operands[1], count);
15202 (define_insn "ashlv4hi3"
15203 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15204 (ashift:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
15205 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
15207 "mshlld.w %1, %2, %0"
15208 [(set_attr "type" "arith_media")
15209 (set_attr "highpart" "depend")])
15211 (define_insn "lshrv2si3"
15212 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15213 (lshiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
15214 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
15216 "mshlrd.l %1, %2, %0"
15217 [(set_attr "type" "arith_media")
15218 (set_attr "highpart" "depend")])
15220 (define_insn "lshrv4hi3"
15221 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15222 (lshiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
15223 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
15225 "mshlrd.w %1, %2, %0"
15226 [(set_attr "type" "arith_media")
15227 (set_attr "highpart" "depend")])
15229 (define_insn "subv2si3"
15230 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15231 (minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
15232 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
15234 "msub.l %N1, %2, %0"
15235 [(set_attr "type" "arith_media")
15236 (set_attr "highpart" "depend")])
15238 (define_insn "subv4hi3"
15239 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15240 (minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
15241 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
15243 "msub.w %N1, %2, %0"
15244 [(set_attr "type" "arith_media")
15245 (set_attr "highpart" "depend")])
15247 (define_insn_and_split "subv2hi3"
15248 [(set (match_operand:V2HI 0 "arith_reg_dest" "=r")
15249 (minus:V2HI (match_operand:V2HI 1 "arith_reg_or_0_operand" "rZ")
15250 (match_operand:V2HI 2 "arith_reg_operand" "r")))]
15256 rtx src0 = simplify_gen_subreg (V4HImode, operands[1], V2HImode, 0);
15257 rtx src1 = simplify_gen_subreg (V4HImode, operands[2], V2HImode, 0);
15258 rtx v4hi_dst = simplify_gen_subreg (V4HImode, operands[0], V2HImode, 0);
15259 rtx di_dst = simplify_gen_subreg (DImode, operands[0], V2HImode, 0);
15260 rtx si_dst = simplify_gen_subreg (SImode, operands[0], V2HImode, 0);
15262 emit_insn (gen_subv4hi3 (v4hi_dst, src0, src1));
15263 emit_insn (gen_truncdisi2 (si_dst, di_dst));
15266 [(set_attr "highpart" "must_split")])
15268 (define_insn "sssubv2si3"
15269 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15270 (ss_minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
15271 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
15273 "msubs.l %N1, %2, %0"
15274 [(set_attr "type" "mcmp_media")
15275 (set_attr "highpart" "depend")])
15277 (define_insn "ussubv8qi3"
15278 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
15279 (us_minus:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
15280 (match_operand:V8QI 2 "arith_reg_operand" "r")))]
15282 "msubs.ub %N1, %2, %0"
15283 [(set_attr "type" "mcmp_media")
15284 (set_attr "highpart" "depend")])
15286 (define_insn "sssubv4hi3"
15287 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15288 (ss_minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
15289 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
15291 "msubs.w %N1, %2, %0"
15292 [(set_attr "type" "mcmp_media")
15293 (set_attr "highpart" "depend")])
15295 ;; -------------------------------------------------------------------------
15296 ;; Floating Point Intrinsics
15297 ;; -------------------------------------------------------------------------
15299 (define_insn "fcosa_s"
15300 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
15301 (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")]
15305 [(set_attr "type" "atrans_media")])
15307 (define_insn "fsina_s"
15308 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
15309 (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")]
15313 [(set_attr "type" "atrans_media")])
15315 (define_insn "fipr"
15316 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
15317 (plus:SF (plus:SF (vec_select:SF (mult:V4SF (match_operand:V4SF 1
15318 "fp_arith_reg_operand" "f")
15319 (match_operand:V4SF 2
15320 "fp_arith_reg_operand" "f"))
15321 (parallel [(const_int 0)]))
15322 (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
15323 (parallel [(const_int 1)])))
15324 (plus:SF (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
15325 (parallel [(const_int 2)]))
15326 (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
15327 (parallel [(const_int 3)])))))]
15329 "fipr.s %1, %2, %0"
15330 [(set_attr "type" "fparith_media")])
15332 (define_insn "fsrra_s"
15333 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
15334 (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "f")]
15338 [(set_attr "type" "atrans_media")])
15340 (define_insn "ftrv"
15341 [(set (match_operand:V4SF 0 "fp_arith_reg_operand" "=f")
15345 (vec_select:V4SF (match_operand:V16SF 1 "fp_arith_reg_operand" "f")
15346 (parallel [(const_int 0) (const_int 5)
15347 (const_int 10) (const_int 15)]))
15348 (match_operand:V4SF 2 "fp_arith_reg_operand" "f"))
15350 (vec_select:V4SF (match_dup 1)
15351 (parallel [(const_int 4) (const_int 9)
15352 (const_int 14) (const_int 3)]))
15353 (vec_select:V4SF (match_dup 2)
15354 (parallel [(const_int 1) (const_int 2)
15355 (const_int 3) (const_int 0)]))))
15358 (vec_select:V4SF (match_dup 1)
15359 (parallel [(const_int 8) (const_int 13)
15360 (const_int 2) (const_int 7)]))
15361 (vec_select:V4SF (match_dup 2)
15362 (parallel [(const_int 2) (const_int 3)
15363 (const_int 0) (const_int 1)])))
15365 (vec_select:V4SF (match_dup 1)
15366 (parallel [(const_int 12) (const_int 1)
15367 (const_int 6) (const_int 11)]))
15368 (vec_select:V4SF (match_dup 2)
15369 (parallel [(const_int 3) (const_int 0)
15370 (const_int 1) (const_int 2)]))))))]
15372 "ftrv.s %1, %2, %0"
15373 [(set_attr "type" "fparith_media")])
15375 (define_insn "ldhi_l"
15376 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15378 (mem:SI (plus:SI (ior:SI (match_operand:QI 1 "ua_address_operand" "p")
15381 (plus:SI (and:SI (match_dup 1) (const_int 3)) (const_int 1))
15385 [(set_attr "type" "load_media")])
15387 (define_insn "ldhi_q"
15388 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15390 (mem:DI (plus:SI (ior:SI (match_operand:QI 1 "ua_address_operand" "p")
15393 (plus:SI (and:SI (match_dup 1) (const_int 7)) (const_int 1))
15397 [(set_attr "type" "load_media")])
15399 (define_insn_and_split "*ldhi_q_comb0"
15400 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15402 (mem:DI (plus:SI (ior:SI (plus:SI
15403 (match_operand:SI 1 "register_operand" "r")
15404 (match_operand:SI 2 "ua_offset" "I06"))
15407 (plus:SI (and:SI (match_dup 1) (const_int 7))
15410 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & 7) == 0"
15415 emit_insn (gen_ldhi_q (operands[0],
15416 gen_rtx_PLUS (SImode, operands[1], operands[2])));
15420 (define_insn_and_split "*ldhi_q_comb1"
15421 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15423 (mem:DI (plus:SI (ior:SI (plus:SI
15424 (match_operand:SI 1 "register_operand" "r")
15425 (match_operand:SI 2 "ua_offset" "I06"))
15428 (plus:SI (and:SI (plus:SI (match_dup 1)
15429 (match_operand:SI 3 "ua_offset" "I06"))
15433 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & -8)
15434 && (INTVAL (operands[2]) & 7) == INTVAL (operands[3])"
15439 emit_insn (gen_ldhi_q (operands[0],
15440 gen_rtx_PLUS (SImode, operands[1], operands[2])));
15444 (define_insn "ldlo_l"
15445 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15447 (mem:SI (and:SI (match_operand:QI 1 "ua_address_operand" "p")
15449 (minus:SI (const_int 4) (and:SI (match_dup 1) (const_int 3)))
15450 (and:SI (match_dup 1) (const_int 3))))]
15453 [(set_attr "type" "load_media")])
15455 (define_insn "ldlo_q"
15456 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15458 (mem:DI (and:SI (match_operand:QI 1 "ua_address_operand" "p")
15460 (minus:SI (const_int 8) (and:SI (match_dup 1) (const_int 7)))
15461 (and:SI (match_dup 1) (const_int 7))))]
15464 [(set_attr "type" "load_media")])
15466 (define_insn_and_split "*ldlo_q_comb0"
15467 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15469 (mem:DI (and:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
15470 (match_operand:SI 2 "ua_offset" "I06"))
15472 (minus:SI (const_int 8) (and:SI (match_dup 1) (const_int 7)))
15473 (and:SI (match_dup 1) (const_int 7))))]
15474 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & 7) == 0"
15479 emit_insn (gen_ldlo_q (operands[0],
15480 gen_rtx_PLUS (SImode, operands[1], operands[2])));
15484 (define_insn_and_split "*ldlo_q_comb1"
15485 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15487 (mem:DI (and:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
15488 (match_operand:SI 2 "ua_offset" "I06"))
15490 (minus:SI (const_int 8)
15491 (and:SI (plus:SI (match_dup 1)
15492 (match_operand:SI 3 "ua_offset" "I06"))
15494 (and:SI (plus:SI (match_dup 1) (match_dup 3)) (const_int 7))))]
15495 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & -8)
15496 && (INTVAL (operands[2]) & 7) == INTVAL (operands[3])"
15501 emit_insn (gen_ldlo_q (operands[0],
15502 gen_rtx_PLUS (SImode, operands[1], operands[2])));
15506 (define_insn "sthi_l"
15507 [(set (zero_extract:SI
15508 (mem:SI (plus:SI (ior:SI (match_operand:QI 0 "ua_address_operand" "p")
15511 (plus:SI (and:SI (match_dup 0) (const_int 3)) (const_int 1))
15513 (match_operand:SI 1 "arith_reg_operand" "r"))]
15516 [(set_attr "type" "ustore_media")])
15518 ;; All unaligned stores are considered to be 'narrow' because they typically
15519 ;; operate on less that a quadword, and when they operate on a full quadword,
15520 ;; the vanilla store high / store low sequence will cause a stall if not
15521 ;; scheduled apart.
15522 (define_insn "sthi_q"
15523 [(set (zero_extract:DI
15524 (mem:DI (plus:SI (ior:SI (match_operand:QI 0 "ua_address_operand" "p")
15527 (plus:SI (and:SI (match_dup 0) (const_int 7)) (const_int 1))
15529 (match_operand:DI 1 "arith_reg_operand" "r"))]
15532 [(set_attr "type" "ustore_media")])
15534 (define_insn_and_split "*sthi_q_comb0"
15535 [(set (zero_extract:DI
15536 (mem:DI (plus:SI (ior:SI (plus:SI
15537 (match_operand:SI 0 "register_operand" "r")
15538 (match_operand:SI 1 "ua_offset" "I06"))
15541 (plus:SI (and:SI (match_dup 0) (const_int 7)) (const_int 1))
15543 (match_operand:DI 2 "arith_reg_operand" "r"))]
15544 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == 0"
15549 emit_insn (gen_sthi_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
15554 (define_insn_and_split "*sthi_q_comb1"
15555 [(set (zero_extract:DI
15556 (mem:DI (plus:SI (ior:SI (plus:SI
15557 (match_operand:SI 0 "register_operand" "r")
15558 (match_operand:SI 1 "ua_offset" "I06"))
15561 (plus:SI (and:SI (plus:SI (match_dup 0)
15562 (match_operand:SI 2 "ua_offset" "I06"))
15566 (match_operand:DI 3 "arith_reg_operand" "r"))]
15567 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & -8)
15568 && (INTVAL (operands[1]) & 7) == INTVAL (operands[2])"
15573 emit_insn (gen_sthi_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
15578 ;; This is highpart user because the address is used as full 64 bit.
15579 (define_insn "stlo_l"
15580 [(set (zero_extract:SI
15581 (mem:SI (and:SI (match_operand:QI 0 "ua_address_operand" "p")
15583 (minus:SI (const_int 4) (and:SI (match_dup 0) (const_int 3)))
15584 (and:SI (match_dup 0) (const_int 3)))
15585 (match_operand:SI 1 "arith_reg_operand" "r"))]
15588 [(set_attr "type" "ustore_media")])
15590 (define_insn "stlo_q"
15591 [(set (zero_extract:DI
15592 (mem:DI (and:SI (match_operand:QI 0 "ua_address_operand" "p")
15594 (minus:SI (const_int 8) (and:SI (match_dup 0) (const_int 7)))
15595 (and:SI (match_dup 0) (const_int 7)))
15596 (match_operand:DI 1 "arith_reg_operand" "r"))]
15599 [(set_attr "type" "ustore_media")])
15601 (define_insn_and_split "*stlo_q_comb0"
15602 [(set (zero_extract:DI
15603 (mem:DI (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
15604 (match_operand:SI 1 "ua_offset" "I06"))
15606 (minus:SI (const_int 8) (and:SI (match_dup 0) (const_int 7)))
15607 (and:SI (match_dup 0) (const_int 7)))
15608 (match_operand:DI 2 "arith_reg_operand" "r"))]
15609 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == 0"
15614 emit_insn (gen_stlo_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
15619 (define_insn_and_split "*stlo_q_comb1"
15620 [(set (zero_extract:DI
15621 (mem:DI (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
15622 (match_operand:SI 1 "ua_offset" "I06"))
15624 (minus:SI (const_int 8)
15625 (and:SI (plus:SI (match_dup 0)
15626 (match_operand:SI 2 "ua_offset" "I06"))
15628 (and:SI (plus:SI (match_dup 0) (match_dup 2)) (const_int 7)))
15629 (match_operand:DI 3 "arith_reg_operand" "r"))]
15630 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == INTVAL (operands[2])"
15635 emit_insn (gen_stlo_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
15640 (define_insn "ldhi_l64"
15641 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15643 (mem:SI (plus:DI (ior:DI (match_operand:QI 1 "ua_address_operand" "p")
15646 (plus:DI (and:DI (match_dup 1) (const_int 3)) (const_int 1))
15650 [(set_attr "type" "load_media")])
15652 (define_insn "ldhi_q64"
15653 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15655 (mem:DI (plus:DI (ior:DI (match_operand:QI 1 "ua_address_operand" "p")
15658 (plus:DI (and:DI (match_dup 1) (const_int 7)) (const_int 1))
15662 [(set_attr "type" "load_media")])
15664 (define_insn "ldlo_l64"
15665 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15667 (mem:SI (and:DI (match_operand:QI 1 "ua_address_operand" "p")
15669 (minus:DI (const_int 4) (and:DI (match_dup 1) (const_int 3)))
15670 (and:DI (match_dup 1) (const_int 3))))]
15673 [(set_attr "type" "load_media")])
15675 (define_insn "ldlo_q64"
15676 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15678 (mem:DI (and:DI (match_operand:QI 1 "ua_address_operand" "p")
15680 (minus:DI (const_int 8) (and:DI (match_dup 1) (const_int 7)))
15681 (and:DI (match_dup 1) (const_int 7))))]
15684 [(set_attr "type" "load_media")])
15686 (define_insn "sthi_l64"
15687 [(set (zero_extract:SI
15688 (mem:SI (plus:DI (ior:DI (match_operand:QI 0 "ua_address_operand" "p")
15691 (plus:DI (and:DI (match_dup 0) (const_int 3)) (const_int 1))
15693 (match_operand:SI 1 "arith_reg_operand" "r"))]
15696 [(set_attr "type" "ustore_media")])
15698 (define_insn "sthi_q64"
15699 [(set (zero_extract:DI
15700 (mem:DI (plus:DI (ior:DI (match_operand:QI 0 "ua_address_operand" "p")
15703 (plus:DI (and:DI (match_dup 0) (const_int 7)) (const_int 1))
15705 (match_operand:DI 1 "arith_reg_operand" "r"))]
15708 [(set_attr "type" "ustore_media")])
15710 (define_insn "stlo_l64"
15711 [(set (zero_extract:SI
15712 (mem:SI (and:DI (match_operand:QI 0 "ua_address_operand" "p")
15714 (minus:DI (const_int 4) (and:DI (match_dup 0) (const_int 3)))
15715 (and:DI (match_dup 0) (const_int 3)))
15716 (match_operand:SI 1 "arith_reg_operand" "r"))]
15719 [(set_attr "type" "ustore_media")])
15721 (define_insn "stlo_q64"
15722 [(set (zero_extract:DI
15723 (mem:DI (and:DI (match_operand:QI 0 "ua_address_operand" "p")
15725 (minus:DI (const_int 8) (and:DI (match_dup 0) (const_int 7)))
15726 (and:DI (match_dup 0) (const_int 7)))
15727 (match_operand:DI 1 "arith_reg_operand" "r"))]
15730 [(set_attr "type" "ustore_media")])
15733 [(set (match_operand:QI 0 "arith_reg_dest" "=r")
15734 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
15738 [(set_attr "type" "arith_media")])
15740 (define_insn "nsbsi"
15741 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15743 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
15747 [(set_attr "type" "arith_media")])
15749 (define_insn "nsbdi"
15750 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15752 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
15756 [(set_attr "type" "arith_media")])
15758 (define_expand "ffsdi2"
15759 [(set (match_operand:DI 0 "arith_reg_dest" "")
15760 (ffs:DI (match_operand:DI 1 "arith_reg_operand" "")))]
15763 rtx scratch = gen_reg_rtx (DImode);
15766 emit_insn (gen_adddi3 (scratch, operands[1], constm1_rtx));
15767 emit_insn (gen_xordi3 (scratch, operands[1], scratch));
15768 emit_insn (gen_lshrdi3_media (scratch, scratch, const1_rtx));
15769 emit_insn (gen_nsbdi (scratch, scratch));
15770 emit_insn (gen_adddi3 (scratch, scratch, GEN_INT (-64)));
15771 emit_insn (gen_movdicc_false (scratch, operands[1], const0_rtx, scratch));
15772 last = emit_insn (gen_subdi3 (operands[0], const0_rtx, scratch));
15773 set_unique_reg_note (last, REG_EQUAL, gen_rtx_FFS (DImode, operands[0]));
15778 (define_expand "ffssi2"
15779 [(set (match_operand:SI 0 "arith_reg_dest" "")
15780 (ffs:SI (match_operand:SI 1 "arith_reg_operand" "")))]
15783 rtx scratch = gen_reg_rtx (SImode);
15784 rtx discratch = gen_reg_rtx (DImode);
15787 emit_insn (gen_adddi3 (discratch,
15788 simplify_gen_subreg (DImode, operands[1], SImode, 0),
15790 emit_insn (gen_andcdi3 (discratch,
15791 simplify_gen_subreg (DImode, operands[1], SImode, 0),
15793 emit_insn (gen_nsbsi (scratch, discratch));
15794 last = emit_insn (gen_subsi3 (operands[0],
15795 force_reg (SImode, GEN_INT (63)), scratch));
15796 set_unique_reg_note (last, REG_EQUAL, gen_rtx_FFS (SImode, operands[0]));
15801 (define_insn "byterev"
15802 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
15803 (vec_select:V8QI (match_operand:V8QI 1 "arith_reg_operand" "r")
15804 (parallel [(const_int 7) (const_int 6) (const_int 5)
15805 (const_int 4) (const_int 3) (const_int 2)
15806 (const_int 1) (const_int 0)])))]
15809 [(set_attr "type" "arith_media")])
15811 ;; In user mode, the "pref" instruction will raise a RADDERR exception
15812 ;; for accesses to [0x80000000,0xffffffff]. This makes it an unsuitable
15813 ;; implementation of __builtin_prefetch for VxWorks RTPs.
15814 (define_expand "prefetch"
15815 [(prefetch (match_operand 0 "address_operand" "")
15816 (match_operand:SI 1 "const_int_operand" "")
15817 (match_operand:SI 2 "const_int_operand" ""))]
15818 "(TARGET_SH2A || TARGET_SH3 || TARGET_SH5)
15819 && (TARGET_SHMEDIA || ! TARGET_VXWORKS_RTP)")
15821 (define_insn "*prefetch"
15822 [(prefetch (match_operand:SI 0 "register_operand" "r")
15823 (match_operand:SI 1 "const_int_operand" "n")
15824 (match_operand:SI 2 "const_int_operand" "n"))]
15825 "(TARGET_SH2A || TARGET_SH3 || TARGET_SHCOMPACT) && ! TARGET_VXWORKS_RTP"
15827 [(set_attr "type" "other")])
15829 (define_insn "*prefetch_media"
15830 [(prefetch (match_operand:QI 0 "address_operand" "p")
15831 (match_operand:SI 1 "const_int_operand" "n")
15832 (match_operand:SI 2 "const_int_operand" "n"))]
15835 operands[0] = gen_rtx_MEM (QImode, operands[0]);
15836 output_asm_insn ("ld%M0.b %m0,r63", operands);
15839 [(set_attr "type" "other")])
15841 (define_insn "alloco_i"
15842 [(set (mem:BLK (match_operand:QI 0 "cache_address_operand" "p"))
15843 (unspec:BLK [(const_int 0)] UNSPEC_ALLOCO))]
15848 if (GET_CODE (operands[0]) == PLUS)
15850 xops[0] = XEXP (operands[0], 0);
15851 xops[1] = XEXP (operands[0], 1);
15855 xops[0] = operands[0];
15856 xops[1] = const0_rtx;
15858 output_asm_insn ("alloco %0, %1", xops);
15861 [(set_attr "type" "other")])
15864 [(set (match_operand 0 "any_register_operand" "")
15865 (match_operand 1 "" ""))]
15866 "TARGET_SHMEDIA && reload_completed"
15867 [(set (match_dup 0) (match_dup 1))]
15869 if (!shmedia_cleanup_truncate (operands[1]))
15873 ;; -------------------------------------------------------------------------
15874 ;; Stack Protector Patterns
15875 ;; -------------------------------------------------------------------------
15877 (define_expand "stack_protect_set"
15878 [(set (match_operand 0 "memory_operand" "")
15879 (match_operand 1 "memory_operand" ""))]
15882 if (TARGET_SHMEDIA)
15884 if (TARGET_SHMEDIA64)
15885 emit_insn (gen_stack_protect_set_di_media (operands[0], operands[1]));
15887 emit_insn (gen_stack_protect_set_si_media (operands[0], operands[1]));
15890 emit_insn (gen_stack_protect_set_si (operands[0], operands[1]));
15895 (define_insn "stack_protect_set_si"
15896 [(set (match_operand:SI 0 "memory_operand" "=m")
15897 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
15898 (set (match_scratch:SI 2 "=&r") (const_int 0))]
15901 return "mov.l %1,%2" "\n"
15902 " mov.l %2,%0" "\n"
15905 [(set_attr "type" "other")
15906 (set_attr "length" "6")])
15908 (define_insn "stack_protect_set_si_media"
15909 [(set (match_operand:SI 0 "memory_operand" "=m")
15910 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
15911 (set (match_scratch:SI 2 "=&r") (const_int 0))]
15914 return "ld%M1.l %m1,%2" "\n"
15915 " st%M0.l %m0,%2" "\n"
15918 [(set_attr "type" "other")
15919 (set_attr "length" "12")])
15921 (define_insn "stack_protect_set_di_media"
15922 [(set (match_operand:DI 0 "memory_operand" "=m")
15923 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
15924 (set (match_scratch:DI 2 "=&r") (const_int 0))]
15927 return "ld%M1.q %m1,%2" "\n"
15928 " st%M0.q %m0,%2" "\n"
15931 [(set_attr "type" "other")
15932 (set_attr "length" "12")])
15934 (define_expand "stack_protect_test"
15935 [(match_operand 0 "memory_operand" "")
15936 (match_operand 1 "memory_operand" "")
15937 (match_operand 2 "" "")]
15940 if (TARGET_SHMEDIA)
15942 rtx tmp = gen_reg_rtx (GET_MODE (operands[0]));
15945 test = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
15946 if (TARGET_SHMEDIA64)
15948 emit_insn (gen_stack_protect_test_di_media (tmp, operands[0],
15950 emit_jump_insn (gen_cbranchdi4 (test, tmp, const0_rtx, operands[2]));
15954 emit_insn (gen_stack_protect_test_si_media (tmp, operands[0],
15956 emit_jump_insn (gen_cbranchsi4 (test, tmp, const0_rtx, operands[2]));
15961 emit_insn (gen_stack_protect_test_si (operands[0], operands[1]));
15962 emit_jump_insn (gen_branch_true (operands[2]));
15968 (define_insn "stack_protect_test_si"
15969 [(set (reg:SI T_REG)
15970 (unspec:SI [(match_operand:SI 0 "memory_operand" "m")
15971 (match_operand:SI 1 "memory_operand" "m")]
15973 (set (match_scratch:SI 2 "=&r") (const_int 0))
15974 (set (match_scratch:SI 3 "=&r") (const_int 0))]
15977 return "mov.l %0,%2" "\n"
15978 " mov.l %1,%3" "\n"
15979 " cmp/eq %2,%3" "\n"
15983 [(set_attr "type" "other")
15984 (set_attr "length" "10")])
15986 (define_insn "stack_protect_test_si_media"
15987 [(set (match_operand:SI 0 "register_operand" "=&r")
15988 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
15989 (match_operand:SI 2 "memory_operand" "m")]
15991 (set (match_scratch:SI 3 "=&r") (const_int 0))]
15994 return "ld%M1.l %m1,%0" "\n"
15995 " ld%M2.l %m2,%3" "\n"
15996 " cmpeq %0,%3,%0" "\n"
15999 [(set_attr "type" "other")
16000 (set_attr "length" "16")])
16002 (define_insn "stack_protect_test_di_media"
16003 [(set (match_operand:DI 0 "register_operand" "=&r")
16004 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
16005 (match_operand:DI 2 "memory_operand" "m")]
16007 (set (match_scratch:DI 3 "=&r") (const_int 0))]
16010 return "ld%M1.q %m1,%0" "\n"
16011 " ld%M2.q %m2,%3" "\n"
16012 " cmpeq %0,%3,%0" "\n"
16015 [(set_attr "type" "other")
16016 (set_attr "length" "16")])
16018 ;; -------------------------------------------------------------------------
16019 ;; Atomic operations
16020 ;; -------------------------------------------------------------------------
16022 (include "sync.md")