gcc/testsuite/gcc.target/aarch64/sve/slp_4.c

   1 /* { dg-do compile } */
   2 /* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=scalable" } */
   3
   4 #include <stdint.h>
   5
   6 #define VEC_PERM(TYPE)                                          \
   7 TYPE __attribute__ ((noinline, noclone))                        \
   8 vec_slp_##TYPE (TYPE *restrict a, int n)                        \
   9 {                                                               \
  10   for (int i = 0; i < n; ++i)                                   \
  11     {                                                           \
  12       a[i * 8] += 99;                                           \
  13       a[i * 8 + 1] += 11;                                       \
  14       a[i * 8 + 2] += 17;                                       \
  15       a[i * 8 + 3] += 80;                                       \
  16       a[i * 8 + 4] += 63;                                       \
  17       a[i * 8 + 5] += 37;                                       \
  18       a[i * 8 + 6] += 24;                                       \
  19       a[i * 8 + 7] += 81;                                       \
  20     }                                                           \
  21 }
  22
  23 #define TEST_ALL(T)                             \
  24   T (int8_t)                                    \
  25   T (uint8_t)                                   \
  26   T (int16_t)                                   \
  27   T (uint16_t)                                  \
  28   T (int32_t)                                   \
  29   T (uint32_t)                                  \
  30   T (int64_t)                                   \
  31   T (uint64_t)                                  \
  32   T (_Float16)                                  \
  33   T (float)                                     \
  34   T (double)
  35
  36 TEST_ALL (VEC_PERM)
  37
  38 /* 1 for each 8-bit type, 4 for each 32-bit type and 8 for double.  */
  39 /* { dg-final { scan-assembler-times {\tld1rd\tz[0-9]+\.d, } 22 { target aarch64_little_endian } } } */
  40 /* { dg-final { scan-assembler-times {\tld1rqb\tz[0-9]+\.b, } 2 { target aarch64_big_endian } } } */
  41 /* { dg-final { scan-assembler-times {\tld1rd\tz[0-9]+\.d, } 20 { target aarch64_big_endian } } } */
  42 /* 1 for each 16-bit type.  */
  43 /* { dg-final { scan-assembler-times {\tld1rqh\tz[0-9]\.h, } 3 } } */
  44 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #99\n} 2 } } */
  45 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #11\n} 2 } } */
  46 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #17\n} 2 } } */
  47 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #80\n} 2 } } */
  48 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #63\n} 2 } } */
  49 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #37\n} 2 } } */
  50 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #24\n} 2 } } */
  51 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #81\n} 2 } } */
  52 /* The 32-bit types need:
  53
  54       ZIP1 ZIP1 (2 ZIP2s optimized away)
  55       ZIP1 ZIP2
  56
  57    and the 64-bit types need:
  58
  59       ZIP1 ZIP1 ZIP1 ZIP1 (4 ZIP2s optimized away)
  60       ZIP1 ZIP2 ZIP1 ZIP2
  61       ZIP1 ZIP2 ZIP1 ZIP2.  */
  62 /* { dg-final { scan-assembler-times {\tzip1\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 33 } } */
  63 /* { dg-final { scan-assembler-times {\tzip2\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 15 } } */
  64
  65 /* The loop should be fully-masked.  The 32-bit types need two loads
  66    and stores each and the 64-bit types need four.  */
  67 /* { dg-final { scan-assembler-times {\tld1b\t} 2 } } */
  68 /* { dg-final { scan-assembler-times {\tst1b\t} 2 } } */
  69 /* { dg-final { scan-assembler-times {\tld1h\t} 3 } } */
  70 /* { dg-final { scan-assembler-times {\tst1h\t} 3 } } */
  71 /* { dg-final { scan-assembler-times {\tld1w\t} 6 } } */
  72 /* { dg-final { scan-assembler-times {\tst1w\t} 6 } } */
  73 /* { dg-final { scan-assembler-times {\tld1d\t} 12 } } */
  74 /* { dg-final { scan-assembler-times {\tst1d\t} 12 } } */
  75 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.b} 4 } } */
  76 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.h} 6 } } */
  77 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.s} 12 } } */
  78 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.d} 24 } } */
  79 /* { dg-final { scan-assembler-not {\tldr} } } */
  80 /* { dg-final { scan-assembler-not {\tstr} } } */
  81
  82 /* { dg-final { scan-assembler-not {\tuqdec[bh]\t} } } */
  83 /* We use UQDECW instead of UQDECD ..., MUL #2.  */
  84 /* { dg-final { scan-assembler-times {\tuqdecw\t} 6 } } */
  85 /* { dg-final { scan-assembler-times {\tuqdecd\t} 6 } } */