[AArch64] Prefer LD1RQ for big-endian SVE
[official-gcc.git] / gcc / testsuite / gcc.target / aarch64 / sve / slp_3.c
blob0f9f01a00565b1d6f702b3d784a67a08d570dbaf
1 /* { dg-do compile } */
2 /* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=scalable" } */
4 #include <stdint.h>
6 #define VEC_PERM(TYPE) \
7 TYPE __attribute__ ((noinline, noclone)) \
8 vec_slp_##TYPE (TYPE *restrict a, int n) \
9 { \
10 for (int i = 0; i < n; ++i) \
11 { \
12 a[i * 4] += 41; \
13 a[i * 4 + 1] += 25; \
14 a[i * 4 + 2] += 31; \
15 a[i * 4 + 3] += 62; \
16 } \
19 #define TEST_ALL(T) \
20 T (int8_t) \
21 T (uint8_t) \
22 T (int16_t) \
23 T (uint16_t) \
24 T (int32_t) \
25 T (uint32_t) \
26 T (int64_t) \
27 T (uint64_t) \
28 T (_Float16) \
29 T (float) \
30 T (double)
32 TEST_ALL (VEC_PERM)
34 /* 1 for each 8-bit type. */
35 /* { dg-final { scan-assembler-times {\tld1rw\tz[0-9]+\.s, } 2 { target aarch64_little_endian } } } */
36 /* { dg-final { scan-assembler-times {\tld1rqb\tz[0-9]+\.b, } 2 { target aarch64_big_endian } } } */
37 /* 1 for each 16-bit type and 4 for double. */
38 /* { dg-final { scan-assembler-times {\tld1rd\tz[0-9]+\.d, } 7 { target aarch64_little_endian } } } */
39 /* { dg-final { scan-assembler-times {\tld1rqh\tz[0-9]+\.h, } 3 { target aarch64_big_endian } } } */
40 /* { dg-final { scan-assembler-times {\tld1rd\tz[0-9]+\.d, } 4 { target aarch64_big_endian } } } */
41 /* 1 for each 32-bit type. */
42 /* { dg-final { scan-assembler-times {\tld1rqw\tz[0-9]+\.s, } 3 } } */
43 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #41\n} 2 } } */
44 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #25\n} 2 } } */
45 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #31\n} 2 } } */
46 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #62\n} 2 } } */
47 /* The 64-bit types need:
49 ZIP1 ZIP1 (2 ZIP2s optimized away)
50 ZIP1 ZIP2. */
51 /* { dg-final { scan-assembler-times {\tzip1\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 9 } } */
52 /* { dg-final { scan-assembler-times {\tzip2\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 3 } } */
54 /* The loop should be fully-masked. The 64-bit types need two loads
55 and stores each. */
56 /* { dg-final { scan-assembler-times {\tld1b\t} 2 } } */
57 /* { dg-final { scan-assembler-times {\tst1b\t} 2 } } */
58 /* { dg-final { scan-assembler-times {\tld1h\t} 3 } } */
59 /* { dg-final { scan-assembler-times {\tst1h\t} 3 } } */
60 /* { dg-final { scan-assembler-times {\tld1w\t} 3 } } */
61 /* { dg-final { scan-assembler-times {\tst1w\t} 3 } } */
62 /* { dg-final { scan-assembler-times {\tld1d\t} 6 } } */
63 /* { dg-final { scan-assembler-times {\tst1d\t} 6 } } */
64 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.b} 4 } } */
65 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.h} 6 } } */
66 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.s} 6 } } */
67 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.d} 12 } } */
68 /* { dg-final { scan-assembler-not {\tldr} } } */
69 /* { dg-final { scan-assembler-not {\tstr} } } */
71 /* { dg-final { scan-assembler-not {\tuqdec[bhw]\t} } } */
72 /* { dg-final { scan-assembler-times {\tuqdecd\t} 3 } } */