| blob | 6296ffe959f62ac5515a3d32e617a909f829f090 |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2018 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
24 #define INCLUDE_STRING
75 /* This file should be included last. */
78 /* Defined for convenience. */
79 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
81 /* Classifies an address.
83 ADDRESS_REG_IMM
84 A simple base register plus immediate offset.
86 ADDRESS_REG_WB
87 A base register indexed by immediate offset with writeback.
89 ADDRESS_REG_REG
90 A base register indexed by (optionally scaled) register.
92 ADDRESS_REG_UXTW
93 A base register indexed by (optionally scaled) zero-extended register.
95 ADDRESS_REG_SXTW
96 A base register indexed by (optionally scaled) sign-extended register.
98 ADDRESS_LO_SUM
99 A LO_SUM rtx with a base register and "LO12" symbol relocation.
101 ADDRESS_SYMBOLIC:
102 A constant symbolic address, in pc-relative literal pool. */
105 ADDRESS_REG_IMM,
106 ADDRESS_REG_WB,
107 ADDRESS_REG_REG,
108 ADDRESS_REG_UXTW,
109 ADDRESS_REG_SXTW,
110 ADDRESS_LO_SUM,
111 ADDRESS_SYMBOLIC
112 };
116 rtx base;
117 rtx offset;
118 poly_int64 const_offset;
121 };
123 /* Information about a legitimate vector immediate operand. */
124 struct simd_immediate_info
125 {
136 /* The mode of the elements. */
137 scalar_mode elt_mode;
139 /* The value of each element if all elements are the same, or the
140 first value if the constant is a series. */
141 rtx value;
143 /* The value of the step if the constant is a series, null otherwise. */
144 rtx step;
146 /* The instruction to use to move the immediate into a vector. */
147 insn_type insn;
149 /* The kind of shift modifier to use, and the number of bits to shift.
150 This is (LSL, 0) if no shift is needed. */
151 modifier_type modifier;
153 };
155 /* Construct a floating-point immediate in which each element has mode
156 ELT_MODE_IN and value VALUE_IN. */
157 inline simd_immediate_info
161 {}
163 /* Construct an integer immediate in which each element has mode ELT_MODE_IN
164 and value VALUE_IN. The other parameters are as for the structure
165 fields. */
166 inline simd_immediate_info
173 {}
175 /* Construct an integer immediate in which each element has mode ELT_MODE_IN
176 and where element I is equal to VALUE_IN + I * STEP_IN. */
177 inline simd_immediate_info
181 {}
183 /* The current code model. */
186 /* The number of 64-bit elements in an SVE vector. */
187 poly_uint16 aarch64_sve_vg;
189 #ifdef HAVE_AS_TLS
190 #undef TARGET_HAVE_TLS
191 #define TARGET_HAVE_TLS 1
192 #endif
196 const_tree,
205 const_tree type,
211 /* Major revision number of the ARM Architecture implemented by the target. */
214 /* The processor for which instructions should be scheduled. */
217 /* Mask to specify which instruction scheduling options should be used. */
220 /* Global flag for PC relative loads. */
223 /* Support for command line parsing of boolean flags in the tuning
224 structures. */
225 struct aarch64_flag_desc
226 {
229 };
231 #define AARCH64_FUSION_PAIR(name, internal_name) \
232 { name, AARCH64_FUSE_##internal_name },
234 {
239 };
241 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
242 { name, AARCH64_EXTRA_TUNE_##internal_name },
244 {
249 };
251 /* Tuning parameters. */
254 {
255 {
260 },
267 };
270 {
271 {
276 },
283 };
286 {
287 {
292 },
299 };
302 {
303 {
308 },
315 };
318 {
320 /* Avoid the use of slow int<->fp moves for spilling by setting
321 their cost higher than memmov_cost. */
325 };
328 {
330 /* Avoid the use of slow int<->fp moves for spilling by setting
331 their cost higher than memmov_cost. */
335 };
338 {
340 /* Avoid the use of slow int<->fp moves for spilling by setting
341 their cost higher than memmov_cost. */
345 };
348 {
350 /* Avoid the use of slow int<->fp moves for spilling by setting
351 their cost higher than memmov_cost (actual, 4 and 9). */
355 };
358 {
363 };
366 {
368 /* Avoid the use of slow int<->fp moves for spilling by setting
369 their cost higher than memmov_cost. */
373 };
376 {
378 /* Avoid the use of int<->fp moves for spilling. */
382 };
385 {
387 /* Avoid the use of int<->fp moves for spilling. */
391 };
393 /* Generic costs for vector insn classes. */
395 {
411 };
413 /* ThunderX costs for vector insn classes. */
415 {
431 };
433 /* Generic costs for vector insn classes. */
435 {
451 };
454 {
470 };
472 /* Generic costs for vector insn classes. */
474 {
490 };
492 /* Costs for vector insn classes for Vulcan. */
494 {
510 };
512 /* Generic costs for branch instructions. */
514 {
517 };
519 /* Generic approximation modes. */
521 {
524 AARCH64_APPROX_NONE /* recip_sqrt */
525 };
527 /* Approximation modes for Exynos M1. */
529 {
532 AARCH64_APPROX_ALL /* recip_sqrt */
533 };
535 /* Approximation modes for X-Gene 1. */
537 {
540 AARCH64_APPROX_ALL /* recip_sqrt */
541 };
543 /* Generic prefetch settings (which disable prefetch). */
545 {
551 };
554 {
560 };
563 {
569 };
572 {
578 };
581 {
587 };
590 {
596 };
599 {
620 &generic_prefetch_tune
621 };
624 {
646 &generic_prefetch_tune
647 };
650 {
672 &generic_prefetch_tune
673 };
676 {
698 &generic_prefetch_tune
699 };
702 {
724 &generic_prefetch_tune
725 };
728 {
750 &generic_prefetch_tune
751 };
756 {
777 &exynosm1_prefetch_tune
778 };
781 {
802 &thunderxt88_prefetch_tune
803 };
806 {
826 (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW
828 &thunderx_prefetch_tune
829 };
832 {
853 &generic_prefetch_tune
854 };
857 {
879 &qdf24xx_prefetch_tune
880 };
882 /* Tuning structure for the Qualcomm Saphira core. Default to falkor values
883 for now. */
885 {
907 &generic_prefetch_tune
908 };
911 {
933 &thunderx2t99_prefetch_tune
934 };
936 /* Support for fine-grained override of the tuning structures. */
937 struct aarch64_tuning_override_function
938 {
941 };
946 static const struct aarch64_tuning_override_function
947 aarch64_tuning_override_functions[] =
948 {
952 };
954 /* A processor implementing AArch64. */
955 struct processor
956 {
964 };
966 /* Architectures implementing AArch64. */
968 {
969 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
970 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
973 };
975 /* Processor cores implementing AArch64. */
977 {
978 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
979 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
980 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
981 FLAGS, &COSTS##_tunings},
986 };
989 /* Target specification. These are populated by the -march, -mtune, -mcpu
990 handling code or by target attributes. */
995 /* The current tuning set. */
998 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
1000 /* An ISA extension in the co-processor and main instruction set space. */
1001 struct aarch64_option_extension
1002 {
1006 };
1009 {
1013 }
1014 aarch64_cc;
1016 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
1018 /* The condition codes of the processor, and the inverse function. */
1020 {
1023 };
1025 /* Generate code to enable conditional branches in functions over 1 MiB. */
1029 {
1046 }
1048 void
1050 {
1054 else
1056 }
1058 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
1059 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
1060 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
1061 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
1062 cost (in this case the best class is the lowest cost one). Using ALL_REGS
1063 irrespectively of its cost results in bad allocations with many redundant
1064 int<->FP moves which are expensive on various cores.
1065 To avoid this we don't allow ALL_REGS as the allocno class, but force a
1066 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
1067 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
1068 Otherwise set the allocno class depending on the mode.
1069 The result of this is that it is no longer inefficient to have a higher
1070 memory move cost than the register move cost.
1071 */
1073 static reg_class_t
1075 reg_class_t best_class)
1076 {
1077 machine_mode mode;
1087 }
1089 static unsigned int
1091 {
1095 }
1097 static int
1099 machine_mode mode)
1100 {
1108 }
1110 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
1111 unsigned
1113 {
1125 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
1126 equivalent DWARF register. */
1128 }
1130 /* Return true if MODE is any of the Advanced SIMD structure modes. */
1131 static bool
1133 {
1136 }
1138 /* Return true if MODE is an SVE predicate mode. */
1139 static bool
1141 {
1147 }
1149 /* Three mutually-exclusive flags describing a vector or predicate type. */
1153 /* Can be used in combination with VEC_ADVSIMD or VEC_SVE_DATA to indicate
1154 a structure of 2, 3 or 4 vectors. */
1156 /* Useful combinations of the above. */
1160 /* Return a set of flags describing the vector properties of mode MODE.
1161 Ignore modes that are not supported by the current target. */
1162 static unsigned int
1164 {
1180 {
1182 {
1189 }
1191 /* This includes V1DF but not V1DI (which doesn't exist). */
1196 }
1199 }
1201 /* Return true if MODE is any of the data vector modes, including
1202 structure modes. */
1203 static bool
1205 {
1207 }
1209 /* Return true if MODE is an SVE data vector mode; either a single vector
1210 or a structure of vectors. */
1211 static bool
1213 {
1215 }
1217 /* Implement target hook TARGET_ARRAY_MODE. */
1218 static opt_machine_mode
1220 {
1227 }
1229 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1230 static bool
1233 {
1241 }
1243 /* Return the SVE predicate mode to use for elements that have
1244 ELEM_NBYTES bytes, if such a mode exists. */
1246 opt_machine_mode
1248 {
1250 {
1259 }
1261 }
1263 /* Implement TARGET_VECTORIZE_GET_MASK_MODE. */
1265 static opt_machine_mode
1267 {
1269 {
1271 machine_mode pred_mode;
1274 }
1277 }
1279 /* Implement TARGET_HARD_REGNO_NREGS. */
1281 static unsigned int
1283 {
1284 /* ??? Logically we should only need to provide a value when
1285 HARD_REGNO_MODE_OK says that the combination is valid,
1286 but at the moment we need to handle all modes. Just ignore
1287 any runtime parts for registers that can't store them. */
1290 {
1303 }
1305 }
1307 /* Implement TARGET_HARD_REGNO_MODE_OK. */
1309 static bool
1311 {
1316 /* This must have the same size as _Unwind_Word. */
1327 /* The purpose of comparing with ptr_mode is to support the
1328 global register variable associated with the stack pointer
1329 register via the syntax of asm ("wsp") in ILP32. */
1339 {
1342 else
1344 }
1347 }
1349 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
1350 the lower 64 bits of a 128-bit register. Tell the compiler the callee
1351 clobbers the top 64 bits when restoring the bottom 64 bits. */
1353 static bool
1355 {
1357 }
1359 /* Implement REGMODE_NATURAL_SIZE. */
1360 poly_uint64
1362 {
1363 /* The natural size for SVE data modes is one SVE data vector,
1364 and similarly for predicates. We can't independently modify
1365 anything smaller than that. */
1366 /* ??? For now, only do this for variable-width SVE registers.
1367 Doing it for constant-sized registers breaks lower-subreg.c. */
1368 /* ??? And once that's fixed, we should probably have similar
1369 code for Advanced SIMD. */
1371 {
1377 }
1379 }
1381 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1382 machine_mode
1384 machine_mode mode)
1385 {
1386 /* The predicate mode determines which bits are significant and
1387 which are "don't care". Decreasing the number of lanes would
1388 lose data while increasing the number of lanes would make bits
1389 unnecessarily significant. */
1394 else
1396 }
1398 /* Implement TARGET_CONSTANT_ALIGNMENT. Make strings word-aligned so
1399 that strcpy from constants will be faster. */
1401 static HOST_WIDE_INT
1403 {
1407 }
1409 /* Return true if calls to DECL should be treated as
1410 long-calls (ie called via a register). */
1411 static bool
1413 {
1415 }
1417 /* Return true if calls to symbol-ref SYM should be treated as
1418 long-calls (ie called via a register). */
1419 bool
1421 {
1423 }
1425 /* Return true if calls to symbol-ref SYM should not go through
1426 plt stubs. */
1428 bool
1430 {
1434 && decl
1435 && (!flag_plt
1441 }
1443 /* Return true if the offsets to a zero/sign-extract operation
1444 represent an expression that matches an extend operation. The
1445 operands represent the paramters from
1447 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1448 bool
1450 rtx extract_imm)
1451 {
1468 }
1470 /* Emit an insn that's a simple single-set. Both the operands must be
1471 known to be valid. */
1474 {
1476 }
1478 /* X and Y are two things to compare using CODE. Emit the compare insn and
1479 return the rtx for register 0 in the proper mode. */
1480 rtx
1482 {
1488 }
1490 /* Build the SYMBOL_REF for __tls_get_addr. */
1494 rtx
1496 {
1500 }
1502 /* Return the TLS model to use for ADDR. */
1504 static enum tls_model
1506 {
1509 {
1510 poly_int64 addend;
1514 }
1519 }
1521 /* We'll allow lo_sum's in addresses in our legitimate addresses
1522 so that combine would take care of combining addresses where
1523 necessary, but for generation purposes, we'll generate the address
1524 as :
1525 RTL Absolute
1526 tmp = hi (symbol_ref); adrp x1, foo
1527 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1528 nop
1530 PIC TLS
1531 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1532 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1533 bl __tls_get_addr
1534 nop
1536 Load TLS symbol, depending on TLS mechanism and TLS access model.
1538 Global Dynamic - Traditional TLS:
1539 adrp tmp, :tlsgd:imm
1540 add dest, tmp, #:tlsgd_lo12:imm
1541 bl __tls_get_addr
1543 Global Dynamic - TLS Descriptors:
1544 adrp dest, :tlsdesc:imm
1545 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1546 add dest, dest, #:tlsdesc_lo12:imm
1547 blr tmp
1548 mrs tp, tpidr_el0
1549 add dest, dest, tp
1551 Initial Exec:
1552 mrs tp, tpidr_el0
1553 adrp tmp, :gottprel:imm
1554 ldr dest, [tmp, #:gottprel_lo12:imm]
1555 add dest, dest, tp
1557 Local Exec:
1558 mrs tp, tpidr_el0
1559 add t0, tp, #:tprel_hi12:imm, lsl #12
1560 add t0, t0, #:tprel_lo12_nc:imm
1561 */
1563 static void
1566 {
1568 {
1570 {
1571 /* In ILP32, the mode of dest can be either SImode or DImode. */
1583 }
1590 {
1593 rtx insn;
1594 rtx mem;
1596 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1597 here before rtl expand. Tree IVOPT will generate rtl pattern to
1598 decide rtx costs, in which case pic_offset_table_rtx is not
1599 initialized. For that case no need to generate the first adrp
1600 instruction as the final cost for global variable access is
1601 one instruction. */
1603 {
1604 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1605 using the page base as GOT base, the first page may be wasted,
1606 in the worst scenario, there is only 28K space for GOT).
1608 The generate instruction sequence for accessing global variable
1609 is:
1611 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1613 Only one instruction needed. But we must initialize
1614 pic_offset_table_rtx properly. We generate initialize insn for
1615 every global access, and allow CSE to remove all redundant.
1617 The final instruction sequences will look like the following
1618 for multiply global variables access.
1620 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1622 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1623 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1624 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1625 ... */
1634 }
1637 {
1640 else
1644 }
1645 else
1646 {
1651 }
1653 /* The operand is expected to be MEM. Whenever the related insn
1654 pattern changed, above code which calculate mem should be
1655 updated. */
1661 }
1664 {
1665 /* In ILP32, the mode of dest can be either SImode or DImode,
1666 while the got entry is always of SImode size. The mode of
1667 dest depends on how dest is used: if dest is assigned to a
1668 pointer (e.g. in the memory), it has SImode; it may have
1669 DImode if dest is dereferenced to access the memeory.
1670 This is why we have to handle three different ldr_got_small
1671 patterns here (two patterns for ILP32). */
1673 rtx insn;
1674 rtx mem;
1683 {
1686 else
1690 }
1691 else
1692 {
1697 }
1704 }
1707 {
1715 else
1723 }
1726 {
1729 rtx tp;
1733 /* In ILP32, the got entry is always of SImode size. Unlike
1734 small GOT, the dest is fixed at reg 0. */
1737 else
1748 }
1751 {
1752 /* In ILP32, the mode of dest can be either SImode or DImode,
1753 while the got entry is always of SImode size. The mode of
1754 dest depends on how dest is used: if dest is assigned to a
1755 pointer (e.g. in the memory), it has SImode; it may have
1756 DImode if dest is dereferenced to access the memeory.
1757 This is why we have to handle three different tlsie_small
1758 patterns here (two patterns for ILP32). */
1764 {
1767 else
1768 {
1771 }
1772 }
1773 else
1774 {
1777 }
1783 }
1789 {
1797 {
1820 }
1825 }
1832 {
1837 {
1840 else
1841 {
1844 }
1845 }
1846 else
1847 {
1850 }
1855 }
1859 }
1860 }
1862 /* Emit a move from SRC to DEST. Assume that the move expanders can
1863 handle all moves if !can_create_pseudo_p (). The distinction is
1864 important because, unlike emit_move_insn, the move expanders know
1865 how to force Pmode objects into the constant pool even when the
1866 constant pool address is not itself legitimate. */
1867 static rtx
1869 {
1873 }
1875 /* Split a 128-bit move operation into two 64-bit move operations,
1876 taking care to handle partial overlap of register to register
1877 copies. Special cases are needed when moving between GP regs and
1878 FP regs. SRC can be a register, constant or memory; DST a register
1879 or memory. If either operand is memory it must not have any side
1880 effects. */
1881 void
1883 {
1894 {
1898 /* Handle FP <-> GP regs. */
1900 {
1905 {
1908 }
1909 else
1910 {
1913 }
1915 }
1917 {
1922 {
1925 }
1926 else
1927 {
1930 }
1932 }
1933 }
1940 /* At most one pairing may overlap. */
1942 {
1945 }
1946 else
1947 {
1950 }
1951 }
1953 bool
1955 {
1958 }
1960 /* Split a complex SIMD combine. */
1962 void
1964 {
1976 {
2000 }
2004 }
2006 /* Split a complex SIMD move. */
2008 void
2010 {
2017 {
2023 {
2047 }
2051 }
2052 }
2054 bool
2057 {
2061 }
2064 static rtx
2066 {
2069 else
2070 {
2074 }
2075 }
2077 /* Return true if we can move VALUE into a register using a single
2078 CNT[BHWD] instruction. */
2080 static bool
2082 {
2084 /* The coefficient must be [1, 16] * {2, 4, 8, 16}. */
2089 }
2091 /* Likewise for rtx X. */
2093 bool
2095 {
2096 poly_int64 value;
2098 }
2100 /* Return the asm string for an instruction with a CNT-like vector size
2101 operand (a vector pattern followed by a multiplier in the range [1, 16]).
2102 PREFIX is the mnemonic without the size suffix and OPERANDS is the
2103 first part of the operands template (the part that comes before the
2104 vector size itself). FACTOR is the number of quadwords.
2105 NELTS_PER_VQ, if nonzero, is the number of elements in each quadword.
2106 If it is zero, we can use any element size. */
2112 {
2116 /* There is some overlap in the ranges of the four CNT instructions.
2117 Here we always use the smallest possible element size, so that the
2118 multiplier is 1 whereever possible. */
2129 else
2134 }
2136 /* Return the asm string for an instruction with a CNT-like vector size
2137 operand (a vector pattern followed by a multiplier in the range [1, 16]).
2138 PREFIX is the mnemonic without the size suffix and OPERANDS is the
2139 first part of the operands template (the part that comes before the
2140 vector size itself). X is the value of the vector size operand,
2141 as a polynomial integer rtx. */
2145 rtx x)
2146 {
2151 }
2153 /* Return true if we can add VALUE to a register using a single ADDVL
2154 or ADDPL instruction. */
2156 static bool
2158 {
2162 /* FACTOR counts VG / 2, so a value of 2 is one predicate width
2163 and a value of 16 is one vector width. */
2166 }
2168 /* Likewise for rtx X. */
2170 bool
2172 {
2173 poly_int64 value;
2176 }
2178 /* Return the asm string for adding ADDVL or ADDPL immediate X to operand 1
2179 and storing the result in operand 0. */
2183 {
2188 /* Use INC or DEC if possible. */
2190 {
2197 }
2202 else
2205 }
2207 /* Return true if X is a valid immediate for an SVE vector INC or DEC
2208 instruction. If it is, store the number of elements in each vector
2209 quadword in *NELTS_PER_VQ_OUT (if nonnull) and store the multiplication
2210 factor in *FACTOR_OUT (if nonnull). */
2212 bool
2215 {
2216 rtx elt;
2217 poly_int64 value;
2225 /* There's no vector INCB. */
2232 /* The coefficient must be [1, 16] * NELTS_PER_VQ. */
2242 }
2244 /* Return true if X is a valid immediate for an SVE vector INC or DEC
2245 instruction. */
2247 bool
2249 {
2251 }
2253 /* Return the asm template for an SVE vector INC or DEC instruction.
2254 OPERANDS gives the operands before the vector count and X is the
2255 value of the vector count operand itself. */
2259 {
2266 nelts_per_vq);
2267 else
2269 nelts_per_vq);
2270 }
2272 static int
2274 scalar_int_mode mode)
2275 {
2284 {
2288 }
2290 /* Check to see if the low 32 bits are either 0xffffXXXX or 0xXXXXffff
2291 (with XXXX non-zero). In that case check to see if the move can be done in
2292 a smaller mode. */
2297 {
2301 /* Check if we have to emit a second instruction by checking to see
2302 if any of the upper 32 bits of the original DI mode value is set. */
2313 }
2316 {
2318 {
2323 else
2326 }
2328 }
2330 /* Remaining cases are all for DImode. */
2339 {
2340 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
2341 For a 64-bit bitmask try whether changing 16 bits to all ones or
2342 zeroes creates a valid bitmask. To check any repeated bitmask,
2343 try using 16 bits from the other 32-bit half of val. */
2346 {
2357 }
2359 {
2361 {
2365 }
2367 }
2368 }
2370 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
2371 are emitted by the initial mov. If one_match > zero_match, skip set bits,
2372 otherwise skip zero bits. */
2384 {
2390 num_insns ++;
2391 }
2394 }
2396 /* Return whether imm is a 128-bit immediate which is simple enough to
2397 expand inline. */
2398 bool
2400 {
2411 }
2414 /* Return the number of temporary registers that aarch64_add_offset_1
2415 would need to add OFFSET to a register. */
2417 static unsigned int
2419 {
2421 }
2423 /* A subroutine of aarch64_add_offset. Set DEST to SRC + OFFSET for
2424 a non-polynomial OFFSET. MODE is the mode of the addition.
2425 FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should
2426 be set and CFA adjustments added to the generated instructions.
2428 TEMP1, if nonnull, is a register of mode MODE that can be used as a
2429 temporary if register allocation is already complete. This temporary
2430 register may overlap DEST but must not overlap SRC. If TEMP1 is known
2431 to hold abs (OFFSET), EMIT_MOVE_IMM can be set to false to avoid emitting
2432 the immediate again.
2434 Since this function may be used to adjust the stack pointer, we must
2435 ensure that it cannot cause transient stack deallocation (for example
2436 by first incrementing SP and then decrementing when adjusting by a
2437 large immediate). */
2439 static void
2443 {
2451 {
2453 {
2456 }
2458 }
2460 /* Single instruction adjustment. */
2462 {
2466 }
2468 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits
2469 and either:
2471 a) the offset cannot be loaded by a 16-bit move or
2472 b) there is no spare register into which we can move it. */
2476 {
2485 }
2487 /* Emit a move immediate if required and an addition/subtraction. */
2489 {
2492 }
2497 {
2501 }
2502 }
2504 /* Return the number of temporary registers that aarch64_add_offset
2505 would need to move OFFSET into a register or add OFFSET to a register;
2506 ADD_P is true if we want the latter rather than the former. */
2508 static unsigned int
2510 {
2511 /* This follows the same structure as aarch64_add_offset. */
2520 /* Need one register for the ADDVL/ADDPL result. */
2523 {
2526 /* Need one register for the CNT result and one for the multiplication
2527 factor. If necessary, the second temporary can be reused for the
2528 constant part of the offset. */
2530 /* Need one register for the CNT result (which might then
2531 be shifted). */
2533 }
2535 }
2537 /* If X can be represented as a poly_int64, return the number
2538 of temporaries that are required to add it to a register.
2539 Return -1 otherwise. */
2541 int
2543 {
2544 poly_int64 offset;
2548 }
2550 /* Set DEST to SRC + OFFSET. MODE is the mode of the addition.
2551 FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should
2552 be set and CFA adjustments added to the generated instructions.
2554 TEMP1, if nonnull, is a register of mode MODE that can be used as a
2555 temporary if register allocation is already complete. This temporary
2556 register may overlap DEST if !FRAME_RELATED_P but must not overlap SRC.
2557 If TEMP1 is known to hold abs (OFFSET), EMIT_MOVE_IMM can be set to
2558 false to avoid emitting the immediate again.
2560 TEMP2, if nonnull, is a second temporary register that doesn't
2561 overlap either DEST or REG.
2563 Since this function may be used to adjust the stack pointer, we must
2564 ensure that it cannot cause transient stack deallocation (for example
2565 by first incrementing SP and then decrementing when adjusting by a
2566 large immediate). */
2568 static void
2572 {
2576 || !frame_related_p
2580 /* Try using ADDVL or ADDPL to add the whole value. */
2582 {
2587 }
2589 /* Coefficient 1 is multiplied by the number of 128-bit blocks in an
2590 SVE vector register, over and above the minimum size of 128 bits.
2591 This is equivalent to half the value returned by CNTD with a
2592 vector shape of ALL. */
2596 /* Try using ADDVL or ADDPL to add the VG-based part. */
2600 {
2603 {
2607 }
2608 else
2609 {
2614 }
2615 }
2616 /* Otherwise use a CNT-based sequence. */
2618 {
2619 /* Use a subtraction if we have a negative factor. */
2622 {
2625 }
2627 /* Calculate CNTD * FACTOR / 2. First try to fold the division
2628 into the multiplication. */
2629 rtx val;
2632 /* Use a right shift by 1. */
2634 else
2638 {
2640 {
2641 /* "CNTB Xn, ALL, MUL #FACTOR" is out of range, so calculate
2642 the value with the minimum multiplier and shift it into
2643 position. */
2647 }
2649 }
2650 else
2651 {
2652 /* Use CNTD, then multiply it by FACTOR. */
2656 /* Go back to using a negative multiplication factor if we have
2657 no register from which to subtract. */
2659 {
2662 }
2666 }
2669 {
2670 /* Multiply by 1 << SHIFT. */
2673 }
2675 {
2676 /* Divide by 2. */
2679 }
2681 /* Calculate SRC +/- CNTD * FACTOR / 2. */
2683 {
2686 }
2688 {
2691 }
2694 {
2697 {
2701 poly_offset)));
2702 }
2706 }
2707 else
2708 {
2712 }
2715 }
2719 }
2721 /* Like aarch64_add_offset, but the offset is given as an rtx rather
2722 than a poly_int64. */
2724 void
2727 {
2730 }
2732 /* Add DELTA to the stack pointer, marking the instructions frame-related.
2733 TEMP1 is available as a temporary if nonnull. EMIT_MOVE_IMM is false
2734 if TEMP1 already contains abs (DELTA). */
2738 {
2741 }
2743 /* Subtract DELTA from the stack pointer, marking the instructions
2744 frame-related if FRAME_RELATED_P. TEMP1 is available as a temporary
2745 if nonnull. */
2749 {
2752 }
2754 /* Set DEST to (vec_series BASE STEP). */
2756 static void
2758 {
2762 /* Each operand can be a register or an immediate in the range [-16, 15]. */
2769 }
2771 /* Try to duplicate SRC into SVE register DEST, given that SRC is an
2772 integer of mode INT_MODE. Return true on success. */
2774 static bool
2776 rtx src)
2777 {
2778 /* If the constant is smaller than 128 bits, we can do the move
2779 using a vector of SRC_MODEs. */
2781 {
2788 }
2790 /* Use LD1RQ[BHWD] to load the 128 bits from memory. */
2795 /* Make sure that the address is legitimate. */
2797 {
2800 }
2809 }
2811 /* Expand a move of general CONST_VECTOR SRC into DEST, given that it
2812 isn't a simple duplicate or series. */
2814 static void
2816 {
2823 {
2824 /* The constant is a repeating seqeuence of at least two elements,
2825 where the repeating elements occupy no more than 128 bits.
2826 Get an integer representation of the replicated value. */
2827 scalar_int_mode int_mode;
2829 /* For now, always use LD1RQ to load the value on big-endian
2830 targets, since the handling of smaller integers includes a
2831 subreg that is semantically an element reverse. */
2833 else
2834 {
2838 }
2843 }
2845 /* Expand each pattern individually. */
2846 rtx_vector_builder builder;
2849 {
2854 }
2856 /* Use permutes to interleave the separate vectors. */
2858 {
2861 {
2866 }
2867 }
2869 }
2871 /* Set DEST to immediate IMM. For SVE vector modes, GEN_VEC_DUPLICATE
2872 is a pattern that can be used to set DEST to a replicated scalar
2873 element. */
2875 void
2878 {
2881 /* Check on what type of symbol it is. */
2882 scalar_int_mode int_mode;
2888 {
2889 rtx mem;
2890 poly_int64 offset;
2891 HOST_WIDE_INT const_offset;
2894 /* If we have (const (plus symbol offset)), separate out the offset
2895 before we start classifying the symbol. */
2898 /* We must always add an offset involving VL separately, rather than
2899 folding it into the relocation. */
2901 {
2904 else
2905 {
2906 /* Do arithmetic on 32-bit values if the result is smaller
2907 than that. */
2909 {
2910 /* It is invalid to do symbol calculations in modes
2911 narrower than SImode. */
2915 }
2917 {
2921 }
2922 else
2925 }
2927 }
2931 {
2935 {
2941 }
2946 /* If we aren't generating PC relative literals, then
2947 we need to expand the literal pool access carefully.
2948 This is something that needs to be done in a number
2949 of places, so could well live as a separate function. */
2951 {
2958 }
2975 {
2981 }
2982 /* FALLTHRU */
2995 }
2996 }
2999 {
3007 {
3008 /* If the constant is out of range of an SVE vector move,
3009 load it from memory if we can, otherwise move it into
3010 a register and use a DUP. */
3016 {
3019 }
3021 }
3025 else
3026 {
3030 }
3033 }
3037 }
3039 /* Emit an SVE predicated move from SRC to DEST. PRED is a predicate
3040 that is known to contain PTRUE. */
3042 void
3044 {
3047 UNSPEC_MERGE_PTRUE)));
3048 }
3050 /* Expand a pre-RA SVE data move from SRC to DEST in which at least one
3051 operand is in memory. In this case we need to use the predicated LD1
3052 and ST1 instead of LDR and STR, both for correctness on big-endian
3053 targets and because LD1 and ST1 support a wider range of addressing modes.
3054 PRED_MODE is the mode of the predicate.
3056 See the comment at the head of aarch64-sve.md for details about the
3057 big-endian handling. */
3059 void
3061 {
3066 {
3070 else
3073 }
3075 }
3077 static bool
3079 tree exp ATTRIBUTE_UNUSED)
3080 {
3081 /* Currently, always true. */
3083 }
3085 /* Implement TARGET_PASS_BY_REFERENCE. */
3087 static bool
3089 machine_mode mode,
3090 const_tree type,
3092 {
3093 HOST_WIDE_INT size;
3094 machine_mode dummymode;
3097 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
3100 else
3101 /* No frontends can create types with variable-sized modes, so we
3102 shouldn't be asked to pass or return them. */
3105 /* Aggregates are passed by reference based on their size. */
3107 {
3109 }
3111 /* Variable sized arguments are always returned by reference. */
3115 /* Can this be a candidate to be passed in fp/simd register(s)? */
3118 NULL))
3121 /* Arguments which are variable sized or larger than 2 registers are
3122 passed by reference unless they are a homogenous floating point
3123 aggregate. */
3125 }
3127 /* Return TRUE if VALTYPE is padded to its least significant bits. */
3128 static bool
3130 {
3131 machine_mode dummy_mode;
3134 /* Never happens in little-endian mode. */
3138 /* Only composite types smaller than or equal to 16 bytes can
3139 be potentially returned in registers. */
3145 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
3146 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
3147 is always passed/returned in the least significant bits of fp/simd
3148 register(s). */
3154 }
3156 /* Implement TARGET_FUNCTION_VALUE.
3157 Define how to find the value returned by a function. */
3159 static rtx
3162 {
3163 machine_mode mode;
3166 machine_mode ag_mode;
3173 {
3177 {
3180 }
3181 }
3185 {
3187 {
3190 }
3191 else
3192 {
3194 rtx par;
3198 {
3203 }
3205 }
3206 }
3207 else
3209 }
3211 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
3212 Return true if REGNO is the number of a hard register in which the values
3213 of called function may come back. */
3215 static bool
3217 {
3218 /* Maximum of 16 bytes can be returned in the general registers. Examples
3219 of 16-byte return values are: 128-bit integers and 16-byte small
3220 structures (excluding homogeneous floating-point aggregates). */
3224 /* Up to four fp/simd registers can return a function value, e.g. a
3225 homogeneous floating-point aggregate having four members. */
3230 }
3232 /* Implement TARGET_RETURN_IN_MEMORY.
3234 If the type T of the result of a function is such that
3235 void func (T arg)
3236 would require that arg be passed as a value in a register (or set of
3237 registers) according to the parameter passing rules, then the result
3238 is returned in the same registers as would be used for such an
3239 argument. */
3241 static bool
3243 {
3244 HOST_WIDE_INT size;
3245 machine_mode ag_mode;
3251 /* Simple scalar types always returned in registers. */
3255 type,
3258 NULL))
3261 /* Types larger than 2 registers returned in memory. */
3264 }
3266 static bool
3269 {
3272 type,
3274 nregs,
3275 NULL);
3276 }
3278 /* Given MODE and TYPE of a function argument, return the alignment in
3279 bits. The idea is to suppress any stronger alignment requested by
3280 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
3281 This is a helper function for local use only. */
3283 static unsigned int
3285 {
3306 }
3308 /* Layout a function argument according to the AAPCS64 rules. The rule
3309 numbers refer to the rule numbers in the AAPCS64. */
3311 static void
3313 const_tree type,
3315 {
3319 HOST_WIDE_INT size;
3321 /* We need to do this once per argument. */
3327 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
3330 else
3331 /* No frontends can create types with variable-sized modes, so we
3332 shouldn't be asked to pass or return them. */
3338 mode,
3339 type,
3342 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
3343 The following code thus handles passing by SIMD/FP registers first. */
3347 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
3348 and homogenous short-vector aggregates (HVA). */
3350 {
3355 {
3358 {
3361 }
3362 else
3363 {
3364 rtx par;
3368 {
3371 rtx offset = gen_int_mode
3375 }
3377 }
3379 }
3380 else
3381 {
3382 /* C.3 NSRN is set to 8. */
3385 }
3386 }
3391 /* C6 - C9. though the sign and zero extension semantics are
3392 handled elsewhere. This is the case where the argument fits
3393 entirely general registers. */
3395 {
3399 /* C.8 if the argument has an alignment of 16 then the NGRN is
3400 rounded up to the next even number. */
3403 /* The == 16 * BITS_PER_UNIT instead of >= 16 * BITS_PER_UNIT
3404 comparison is there because for > 16 * BITS_PER_UNIT
3405 alignment nregs should be > 2 and therefore it should be
3406 passed by reference rather than value. */
3408 {
3411 }
3413 /* NREGS can be 0 when e.g. an empty structure is to be passed.
3414 A reg is still generated for it, but the caller should be smart
3415 enough not to use it. */
3418 else
3419 {
3420 rtx par;
3425 {
3430 }
3432 }
3436 }
3438 /* C.11 */
3441 /* The argument is passed on stack; record the needed number of words for
3442 this argument and align the total size if necessary. */
3443 on_stack:
3450 }
3452 /* Implement TARGET_FUNCTION_ARG. */
3454 static rtx
3457 {
3466 }
3468 void
3470 const_tree fntype ATTRIBUTE_UNUSED,
3471 rtx libname ATTRIBUTE_UNUSED,
3472 const_tree fndecl ATTRIBUTE_UNUSED,
3474 {
3488 {
3495 }
3497 }
3499 static void
3501 machine_mode mode,
3502 const_tree type,
3504 {
3507 {
3517 }
3518 }
3520 bool
3522 {
3525 }
3527 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
3528 PARM_BOUNDARY bits of alignment, but will be given anything up
3529 to STACK_BOUNDARY bits if the type requires it. This makes sure
3530 that both before and after the layout of each argument, the Next
3531 Stacked Argument Address (NSAA) will have a minimum alignment of
3532 8 bytes. */
3534 static unsigned int
3536 {
3539 }
3541 /* Implement TARGET_GET_RAW_RESULT_MODE and TARGET_GET_RAW_ARG_MODE. */
3543 static fixed_size_mode
3545 {
3547 /* Don't use the SVE part of the register for __builtin_apply and
3548 __builtin_return. The SVE registers aren't used by the normal PCS,
3549 so using them there would be a waste of time. The PCS extensions
3550 for SVE types are fundamentally incompatible with the
3551 __builtin_return/__builtin_apply interface. */
3554 }
3556 /* Implement TARGET_FUNCTION_ARG_PADDING.
3558 Small aggregate types are placed in the lowest memory address.
3560 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
3562 static pad_direction
3564 {
3565 /* On little-endian targets, the least significant byte of every stack
3566 argument is passed at the lowest byte address of the stack slot. */
3570 /* Otherwise, integral, floating-point and pointer types are padded downward:
3571 the least significant byte of a stack argument is passed at the highest
3572 byte address of the stack slot. */
3579 /* Everything else padded upward, i.e. data in first byte of stack slot. */
3581 }
3583 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
3585 It specifies padding for the last (may also be the only)
3586 element of a block move between registers and memory. If
3587 assuming the block is in the memory, padding upward means that
3588 the last element is padded after its highest significant byte,
3589 while in downward padding, the last element is padded at the
3590 its least significant byte side.
3592 Small aggregates and small complex types are always padded
3593 upwards.
3595 We don't need to worry about homogeneous floating-point or
3596 short-vector aggregates; their move is not affected by the
3597 padding direction determined here. Regardless of endianness,
3598 each element of such an aggregate is put in the least
3599 significant bits of a fp/simd register.
3601 Return !BYTES_BIG_ENDIAN if the least significant byte of the
3602 register has useful data, and return the opposite if the most
3603 significant byte does. */
3605 bool
3608 {
3610 /* Small composite types are always padded upward. */
3612 {
3613 HOST_WIDE_INT size;
3616 else
3617 /* No frontends can create types with variable-sized modes, so we
3618 shouldn't be asked to pass or return them. */
3622 }
3624 /* Otherwise, use the default padding. */
3626 }
3628 static scalar_int_mode
3630 {
3632 }
3634 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
3636 /* We use the 12-bit shifted immediate arithmetic instructions so values
3637 must be multiple of (1 << 12), i.e. 4096. */
3638 #define ARITH_FACTOR 4096
3640 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
3641 #error Cannot use simple address calculation for stack probing
3642 #endif
3644 /* The pair of scratch registers used for stack probing. */
3645 #define PROBE_STACK_FIRST_REG 9
3646 #define PROBE_STACK_SECOND_REG 10
3648 /* Emit code to probe a range of stack addresses from FIRST to FIRST+POLY_SIZE,
3649 inclusive. These are offsets from the current stack pointer. */
3651 static void
3653 {
3654 HOST_WIDE_INT size;
3656 {
3659 }
3663 /* See the same assertion on PROBE_INTERVAL above. */
3666 /* See if we have a constant small number of probes to generate. If so,
3667 that's the easy case. */
3669 {
3676 }
3678 /* The run-time loop is made up of 8 insns in the generic case while the
3679 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
3681 {
3686 stack_pointer_rtx,
3690 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
3691 it exceeds SIZE. If only two probes are needed, this will not
3692 generate any code. Then probe at FIRST + SIZE. */
3694 {
3698 }
3702 {
3707 }
3708 else
3710 }
3712 /* Otherwise, do the same as above, but in a loop. Note that we must be
3713 extra careful with variables wrapping around because we might be at
3714 the very top (or the very bottom) of the address space and we have
3715 to be able to handle this case properly; in particular, we use an
3716 equality test for the loop condition. */
3717 else
3718 {
3721 /* Step 1: round SIZE to the previous multiple of the interval. */
3726 /* Step 2: compute initial and final value of the loop counter. */
3728 /* TEST_ADDR = SP + FIRST. */
3732 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
3735 {
3739 }
3740 else
3741 {
3744 }
3746 /* Step 3: the loop
3748 do
3749 {
3750 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
3751 probe at TEST_ADDR
3752 }
3753 while (TEST_ADDR != LAST_ADDR)
3755 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
3756 until it is equal to ROUNDED_SIZE. */
3761 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
3762 that SIZE is equal to ROUNDED_SIZE. */
3765 {
3769 {
3774 }
3775 else
3777 }
3778 }
3780 /* Make sure nothing is scheduled before we are done. */
3782 }
3784 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
3785 absolute addresses. */
3789 {
3796 /* Loop. */
3799 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
3804 /* Probe at TEST_ADDR. */
3807 /* Test if TEST_ADDR == LAST_ADDR. */
3811 /* Branch. */
3817 }
3819 /* Mark the registers that need to be saved by the callee and calculate
3820 the size of the callee-saved registers area and frame record (both FP
3821 and LR may be omitted). */
3822 static void
3824 {
3831 /* Force a frame chain for EH returns so the return address is at FP+8. */
3835 /* Emit a frame chain if the frame pointer is enabled.
3836 If -momit-leaf-frame-pointer is used, do not use a frame chain
3837 in leaf functions which do not use LR. */
3843 #define SLOT_NOT_REQUIRED (-2)
3844 #define SLOT_REQUIRED (-1)
3849 /* First mark all the registers that really need to be saved... */
3856 /* ... that includes the eh data registers (if needed)... */
3862 /* ... and any callee saved register that dataflow says is live. */
3872 {
3875 }
3878 {
3879 /* FP and LR are placed in the linkage record. */
3885 }
3887 /* Now assign stack slots for them. */
3890 {
3897 }
3905 {
3906 /* If there is an alignment gap between integer and fp callee-saves,
3907 allocate the last fp register to it if possible. */
3909 {
3912 }
3921 }
3927 HOST_WIDE_INT varargs_and_saved_regs_size
3935 /* Both these values are already aligned. */
3959 {
3960 /* Simple, small frame with no outgoing arguments:
3961 stp reg1, reg2, [sp, -frame_size]!
3962 stp reg3, reg4, [sp, 16] */
3964 }
3969 max_push_offset)))
3970 {
3971 /* Frame with small outgoing arguments:
3972 sub sp, sp, frame_size
3973 stp reg1, reg2, [sp, outgoing_args_size]
3974 stp reg3, reg4, [sp, outgoing_args_size + 16] */
3978 }
3981 {
3982 /* Frame with large outgoing arguments but a small local area:
3983 stp reg1, reg2, [sp, -hard_fp_offset]!
3984 stp reg3, reg4, [sp, 16]
3985 sub sp, sp, outgoing_args_size */
3989 }
3990 else
3991 {
3992 /* Frame with large local area and outgoing arguments using frame pointer:
3993 sub sp, sp, hard_fp_offset
3994 stp x29, x30, [sp, 0]
3995 add x29, sp, 0
3996 stp reg3, reg4, [sp, 16]
3997 sub sp, sp, outgoing_args_size */
4001 }
4004 }
4006 /* Return true if the register REGNO is saved on entry to
4007 the current function. */
4009 static bool
4011 {
4013 }
4015 /* Return the next register up from REGNO up to LIMIT for the callee
4016 to save. */
4018 static unsigned
4020 {
4022 regno ++;
4024 }
4026 /* Push the register number REGNO of mode MODE to the stack with write-back
4027 adjusting the stack by ADJUSTMENT. */
4029 static void
4031 HOST_WIDE_INT adjustment)
4032 {
4043 }
4045 /* Generate and return an instruction to store the pair of registers
4046 REG and REG2 of mode MODE to location BASE with write-back adjusting
4047 the stack location BASE by ADJUSTMENT. */
4049 static rtx
4051 HOST_WIDE_INT adjustment)
4052 {
4054 {
4065 }
4066 }
4068 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
4069 stack pointer by ADJUSTMENT. */
4071 static void
4073 {
4088 }
4090 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
4091 adjusting it by ADJUSTMENT afterwards. */
4093 static rtx
4095 HOST_WIDE_INT adjustment)
4096 {
4098 {
4107 }
4108 }
4110 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
4111 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
4112 into CFI_OPS. */
4114 static void
4117 {
4124 {
4128 }
4129 else
4130 {
4135 }
4136 }
4138 /* Generate and return a store pair instruction of mode MODE to store
4139 register REG1 to MEM1 and register REG2 to MEM2. */
4141 static rtx
4143 rtx reg2)
4144 {
4146 {
4155 }
4156 }
4158 /* Generate and regurn a load pair isntruction of mode MODE to load register
4159 REG1 from MEM1 and register REG2 from MEM2. */
4161 static rtx
4163 rtx mem2)
4164 {
4166 {
4175 }
4176 }
4178 /* Return TRUE if return address signing should be enabled for the current
4179 function, otherwise return FALSE. */
4181 bool
4183 {
4184 /* This function should only be called after frame laid out. */
4187 /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
4188 if it's LR is pushed onto stack. */
4192 }
4194 /* Emit code to save the callee-saved registers from register number START
4195 to LIMIT to the stack at the location starting at offset START_OFFSET,
4196 skipping any write-back candidates if SKIP_WB is true. */
4198 static void
4201 {
4209 {
4211 poly_int64 offset;
4224 offset));
4233 {
4235 rtx mem2;
4239 offset));
4241 reg2));
4243 /* The first part of a frame-related parallel insn is
4244 always assumed to be relevant to the frame
4245 calculations; subsequent parts, are only
4246 frame-related if explicitly marked. */
4249 }
4250 else
4254 }
4255 }
4257 /* Emit code to restore the callee registers of mode MODE from register
4258 number START up to and including LIMIT. Restore from the stack offset
4259 START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
4260 Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */
4262 static void
4266 {
4270 poly_int64 offset;
4275 {
4296 {
4298 rtx mem2;
4306 }
4307 else
4310 }
4311 }
4313 /* Return true if OFFSET is a signed 4-bit value multiplied by the size
4314 of MODE. */
4318 {
4319 HOST_WIDE_INT multiple;
4322 }
4324 /* Return true if OFFSET is a unsigned 6-bit value multiplied by the size
4325 of MODE. */
4329 {
4330 HOST_WIDE_INT multiple;
4333 }
4335 /* Return true if OFFSET is a signed 7-bit value multiplied by the size
4336 of MODE. */
4338 bool
4340 {
4341 HOST_WIDE_INT multiple;
4344 }
4346 /* Return true if OFFSET is a signed 9-bit value. */
4350 poly_int64 offset)
4351 {
4352 HOST_WIDE_INT const_offset;
4355 }
4357 /* Return true if OFFSET is a signed 9-bit value multiplied by the size
4358 of MODE. */
4362 {
4363 HOST_WIDE_INT multiple;
4366 }
4368 /* Return true if OFFSET is an unsigned 12-bit value multiplied by the size
4369 of MODE. */
4373 {
4374 HOST_WIDE_INT multiple;
4377 }
4379 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
4381 static sbitmap
4383 {
4389 /* The registers we need saved to the frame. */
4392 {
4397 /* Check that we can access the stack slot of the register with one
4398 direct load with no adjustments needed. */
4401 }
4403 /* Don't mess with the hard frame pointer. */
4409 /* If aarch64_layout_frame has chosen registers to store/restore with
4410 writeback don't interfere with them to avoid having to output explicit
4411 stack adjustment instructions. */
4421 }
4423 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
4425 static sbitmap
4427 {
4435 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
4444 }
4446 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
4447 Nothing to do for aarch64. */
4449 static void
4451 {
4452 }
4454 /* Return the next set bit in BMP from START onwards. Return the total number
4455 of bits in BMP if no set bit is found at or after START. */
4457 static unsigned int
4459 {
4470 }
4472 /* Do the work for aarch64_emit_prologue_components and
4473 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
4474 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
4475 for these components or the epilogue sequence. That is, it determines
4476 whether we should emit stores or loads and what kind of CFA notes to attach
4477 to the insns. Otherwise the logic for the two sequences is very
4478 similar. */
4480 static void
4482 {
4484 ? HARD_FRAME_POINTER_REGNUM
4492 {
4493 /* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
4494 so DFmode for the vector registers is enough. */
4506 /* No more registers to handle after REGNO.
4507 Emit a single save/restore and exit. */
4509 {
4514 else
4517 }
4520 /* The next register is not of the same class or its offset is not
4521 mergeable with the current one into a pair. */
4526 {
4531 else
4536 }
4538 /* REGNO2 can be saved/restored in a pair with REGNO. */
4550 else
4555 {
4558 }
4559 else
4560 {
4563 }
4566 }
4567 }
4569 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
4571 static void
4573 {
4575 }
4577 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
4579 static void
4581 {
4583 }
4585 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
4587 static void
4589 {
4593 }
4595 /* Add a REG_CFA_EXPRESSION note to INSN to say that register REG
4596 is saved at BASE + OFFSET. */
4598 static void
4601 {
4605 }
4607 /* AArch64 stack frames generated by this compiler look like:
4609 +-------------------------------+
4610 | |
4611 | incoming stack arguments |
4612 | |
4613 +-------------------------------+
4614 | | <-- incoming stack pointer (aligned)
4615 | callee-allocated save area |
4616 | for register varargs |
4617 | |
4618 +-------------------------------+
4619 | local variables | <-- frame_pointer_rtx
4620 | |
4621 +-------------------------------+
4622 | padding0 | \
4623 +-------------------------------+ |
4624 | callee-saved registers | | frame.saved_regs_size
4625 +-------------------------------+ |
4626 | LR' | |
4627 +-------------------------------+ |
4628 | FP' | / <- hard_frame_pointer_rtx (aligned)
4629 +-------------------------------+
4630 | dynamic allocation |
4631 +-------------------------------+
4632 | padding |
4633 +-------------------------------+
4634 | outgoing stack arguments | <-- arg_pointer
4635 | |
4636 +-------------------------------+
4637 | | <-- stack_pointer_rtx (aligned)
4639 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
4640 but leave frame_pointer_rtx and hard_frame_pointer_rtx
4641 unchanged. */
4643 /* Generate the prologue instructions for entry into a function.
4644 Establish the stack frame by decreasing the stack pointer with a
4645 properly calculated size and, if necessary, create a frame record
4646 filled with the values of LR and previous frame pointer. The
4647 current FP is also set up if it is in use. */
4649 void
4651 {
4664 /* Sign return address for functions. */
4666 {
4670 }
4676 {
4678 {
4682 (frame_size
4684 }
4687 }
4698 {
4701 {
4706 }
4711 {
4712 /* Variable-sized frames need to describe the save slot
4713 address using DW_CFA_expression rather than DW_CFA_offset.
4714 This means that, without taking further action, the
4715 locations of the registers that we've already saved would
4716 remain based on the stack pointer even after we redefine
4717 the CFA based on the frame pointer. We therefore need new
4718 DW_CFA_expressions to re-express the save slots with addresses
4719 based on the frame pointer. */
4723 /* Add an explicit CFA definition if this was previously
4724 implicit. */
4726 {
4728 callee_offset);
4731 }
4733 /* Change the save slot expressions for the registers that
4734 we've already saved. */
4739 reg_offset);
4740 }
4742 }
4749 }
4751 /* Return TRUE if we can use a simple_return insn.
4753 This function checks whether the callee saved stack is empty, which
4754 means no restore actions are need. The pro_and_epilogue will use
4755 this to check whether shrink-wrapping opt is feasible. */
4757 bool
4759 {
4769 }
4771 /* Generate the epilogue instructions for returning from a function.
4772 This is almost exactly the reverse of the prolog sequence, except
4773 that we need to insert barriers to avoid scheduling loads that read
4774 from a deallocated stack, and we optimize the unwind records by
4775 emitting them all together if possible. */
4776 void
4778 {
4789 /* A stack clash protection prologue may not have left IP0_REGNUM or
4790 IP1_REGNUM in a usable state. The same is true for allocations
4791 with an SVE component, since we then need both temporary registers
4792 for each allocation. */
4797 /* We need to add memory barrier to prevent read from deallocated stack. */
4798 bool need_barrier_p
4802 /* Emit a barrier to prevent loads from a deallocated stack. */
4806 {
4809 }
4811 /* Restore the stack pointer from the frame pointer if it may not
4812 be the same as the stack pointer. */
4817 /* If writeback is used when restoring callee-saves, the CFA
4818 is restored on the instruction doing the writeback. */
4822 else
4838 {
4839 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
4845 }
4851 {
4852 /* Emit delayed restores and reset the CFA to be SP. */
4857 }
4859 /* We prefer to emit the combined return/authenticate instruction RETAA,
4860 however there are three cases in which we must instead emit an explicit
4861 authentication instruction.
4863 1) Sibcalls don't return in a normal way, so if we're about to call one
4864 we must authenticate.
4866 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
4867 generating code for !TARGET_ARMV8_3 we can't use it and must
4868 explicitly authenticate.
4870 3) On an eh_return path we make extra stack adjustments to update the
4871 canonical frame address to be the exception handler's CFA. We want
4872 to authenticate using the CFA of the function which calls eh_return.
4873 */
4876 {
4880 }
4882 /* Stack adjustment for exception handler. */
4884 {
4885 /* We need to unwind the stack by the offset computed by
4886 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
4887 to be SP; letting the CFA move during this adjustment
4888 is just as correct as retaining the CFA from the body
4889 of the function. Therefore, do nothing special. */
4891 }
4896 }
4898 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
4899 normally or return to a previous frame after unwinding.
4901 An EH return uses a single shared return sequence. The epilogue is
4902 exactly like a normal epilogue except that it has an extra input
4903 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
4904 that must be applied after the frame has been destroyed. An extra label
4905 is inserted before the epilogue which initializes this register to zero,
4906 and this is the entry point for a normal return.
4908 An actual EH return updates the return address, initializes the stack
4909 adjustment and jumps directly into the epilogue (bypassing the zeroing
4910 of the adjustment). Since the return address is typically saved on the
4911 stack when a function makes a call, the saved LR must be updated outside
4912 the epilogue.
4914 This poses problems as the store is generated well before the epilogue,
4915 so the offset of LR is not known yet. Also optimizations will remove the
4916 store as it appears dead, even after the epilogue is generated (as the
4917 base or offset for loading LR is different in many cases).
4919 To avoid these problems this implementation forces the frame pointer
4920 in eh_return functions so that the location of LR is fixed and known early.
4921 It also marks the store volatile, so no optimization is permitted to
4922 remove the store. */
4923 rtx
4925 {
4929 /* Mark the store volatile, so no optimization is permitted to remove it. */
4932 }
4934 /* Output code to add DELTA to the first argument, and then jump
4935 to FUNCTION. Used for C++ multiple inheritance. */
4936 static void
4938 HOST_WIDE_INT delta,
4939 HOST_WIDE_INT vcall_offset,
4940 tree function)
4941 {
4942 /* The this pointer is always in x0. Note that this differs from
4943 Arm where the this pointer maybe bumped to r1 if r0 is required
4944 to return a pointer to an aggregate. On AArch64 a result value
4945 pointer will be in x8. */
4959 else
4960 {
4965 {
4969 else
4972 }
4976 else
4983 else
4984 {
4986 Pmode);
4988 }
4992 else
4998 }
5000 /* Generate a tail call to the target function. */
5002 {
5005 }
5017 /* Stop pretending to be a post-reload pass. */
5019 }
5021 static bool
5023 {
5028 {
5032 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
5033 TLS offsets, not real symbol references. */
5036 }
5038 }
5041 /* Return true if val can be encoded as a 12-bit unsigned immediate with
5042 a left shift of 0 or 12 bits. */
5043 bool
5045 {
5048 );
5049 }
5052 /* Return true if val is an immediate that can be loaded into a
5053 register by a MOVZ instruction. */
5054 static bool
5056 {
5058 {
5062 }
5063 else
5064 {
5065 /* Ignore sign extension. */
5067 }
5070 }
5072 /* VAL is a value with the inner mode of MODE. Replicate it to fill a
5073 64-bit (DImode) integer. */
5075 static unsigned HOST_WIDE_INT
5077 {
5080 {
5084 }
5086 }
5088 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
5091 {
5097 };
5100 /* Return true if val is a valid bitmask immediate. */
5102 bool
5104 {
5108 /* Check for a single sequence of one bits and return quickly if so.
5109 The special cases of all ones and all zeroes returns false. */
5116 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
5120 /* Invert if the immediate doesn't start with a zero bit - this means we
5121 only need to search for sequences of one bits. */
5125 /* Find the first set bit and set tmp to val with the first sequence of one
5126 bits removed. Return success if there is a single sequence of ones. */
5133 /* Find the next set bit and compute the difference in bit position. */
5138 /* Check the bit position difference is a power of 2, and that the first
5139 sequence of one bits fits within 'bits' bits. */
5143 /* Check the sequence of one bits is repeated 64/bits times. */
5145 }
5147 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
5148 Assumed precondition: VAL_IN Is not zero. */
5150 unsigned HOST_WIDE_INT
5152 {
5159 }
5161 /* Create constant where bits outside of lowest bit set to highest bit set
5162 are set to 1. */
5164 unsigned HOST_WIDE_INT
5166 {
5168 }
5170 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
5172 bool
5174 {
5175 scalar_int_mode int_mode;
5188 }
5190 /* Return true if val is an immediate that can be loaded into a
5191 register in a single instruction. */
5192 bool
5194 {
5195 scalar_int_mode int_mode;
5202 }
5204 static bool
5206 {
5212 /* There's no way to calculate VL-based values using relocations. */
5220 {
5224 else
5225 /* Avoid generating a 64-bit relocation in ILP32; leave
5226 to aarch64_expand_mov_immediate to handle it properly. */
5228 }
5231 }
5233 /* Implement TARGET_CASE_VALUES_THRESHOLD.
5234 The expansion for a table switch is quite expensive due to the number
5235 of instructions, the table lookup and hard to predict indirect jump.
5236 When optimizing for speed, and -O3 enabled, use the per-core tuning if
5237 set, otherwise use tables for > 16 cases as a tradeoff between size and
5238 performance. When optimizing for size, use the default setting. */
5240 static unsigned int
5242 {
5243 /* Use the specified limit for the number of cases before using jump
5244 tables at higher optimization levels. */
5248 else
5250 }
5252 /* Return true if register REGNO is a valid index register.
5253 STRICT_P is true if REG_OK_STRICT is in effect. */
5255 bool
5257 {
5259 {
5267 }
5269 }
5271 /* Return true if register REGNO is a valid base register for mode MODE.
5272 STRICT_P is true if REG_OK_STRICT is in effect. */
5274 bool
5276 {
5278 {
5286 }
5288 /* The fake registers will be eliminated to either the stack or
5289 hard frame pointer, both of which are usually valid base registers.
5290 Reload deals with the cases where the eliminated form isn't valid. */
5295 }
5297 /* Return true if X is a valid base register for mode MODE.
5298 STRICT_P is true if REG_OK_STRICT is in effect. */
5300 static bool
5302 {
5309 }
5311 /* Return true if address offset is a valid index. If it is, fill in INFO
5312 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
5314 static bool
5317 {
5319 rtx index;
5322 /* (reg:P) */
5325 {
5329 }
5330 /* (sign_extend:DI (reg:SI)) */
5335 {
5340 }
5341 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
5348 {
5353 }
5354 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
5361 {
5366 }
5367 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
5374 {
5382 }
5383 /* (and:DI (mult:DI (reg:DI) (const_int scale))
5384 (const_int 0xffffffff<<shift)) */
5391 {
5397 }
5398 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
5405 {
5413 }
5414 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
5415 (const_int 0xffffffff<<shift)) */
5422 {
5428 }
5429 /* (mult:P (reg:P) (const_int scale)) */
5434 {
5438 }
5439 /* (ashift:P (reg:P) (const_int shift)) */
5444 {
5448 }
5449 else
5458 {
5462 }
5463 else
5464 {
5469 }
5473 {
5478 }
5481 }
5483 /* Return true if MODE is one of the modes for which we
5484 support LDP/STP operations. */
5486 static bool
5488 {
5493 }
5495 /* Return true if REGNO is a virtual pointer register, or an eliminable
5496 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
5497 include stack_pointer or hard_frame_pointer. */
5498 static bool
5500 {
5505 }
5507 /* Return true if X is a valid address of type TYPE for machine mode MODE.
5508 If it is, fill in INFO appropriately. STRICT_P is true if
5509 REG_OK_STRICT is in effect. */
5511 static bool
5515 {
5518 poly_int64 offset;
5520 HOST_WIDE_INT const_size;
5522 /* On BE, we use load/store pair for all large int mode load/stores.
5523 TI/TFmode may also use a load/store pair. */
5536 /* For SVE, only accept [Rn], [Rn, Rm, LSL #shift] and
5537 [Rn, #offset, MUL VL]. */
5542 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
5543 REG addressing. */
5545 && !BYTES_BIG_ENDIAN
5553 {
5570 {
5577 }
5582 {
5588 /* TImode and TFmode values are allowed in both pairs of X
5589 registers and individual Q registers. The available
5590 address modes are:
5591 X,X: 7-bit signed scaled offset
5592 Q: 9-bit signed offset
5593 We conservatively require an offset representable in either mode.
5594 When performing the check for pairs of X registers i.e. LDP/STP
5595 pass down DImode since that is the natural size of the LDP/STP
5596 instruction memory accesses. */
5602 /* A 7bit offset check because OImode will emit a ldp/stp
5603 instruction (only big endian will get here).
5604 For ldp/stp instructions, the offset is scaled for the size of a
5605 single element of the pair. */
5609 /* Three 9/12 bit offsets checks because CImode will emit three
5610 ldr/str instructions (only big endian will get here). */
5617 /* Two 7bit offsets checks because XImode will emit two ldp/stp
5618 instructions (only big endian will get here). */
5624 /* Make "m" use the LD1 offset range for SVE data modes, so
5625 that pre-RTL optimizers like ivopts will work to that
5626 instead of the wider LDR/STR range. */
5633 {
5634 poly_int64 end_offset = (offset
5641 end_offset)));
5642 }
5651 else
5654 }
5657 {
5658 /* Look for base + (scaled/extended) index register. */
5661 {
5664 }
5667 {
5670 }
5671 }
5692 {
5696 /* TImode and TFmode values are allowed in both pairs of X
5697 registers and individual Q registers. The available
5698 address modes are:
5699 X,X: 7-bit signed scaled offset
5700 Q: 9-bit signed offset
5701 We conservatively require an offset representable in either mode.
5702 */
5711 else
5713 }
5719 /* load literal: pc-relative constant pool entry. Only supported
5720 for SI mode or larger. */
5726 {
5734 }
5743 {
5749 {
5750 /* The symbol and offset must be aligned to the access size. */
5756 {
5760 }
5766 else
5775 }
5776 }
5781 }
5782 }
5784 /* Return true if the address X is valid for a PRFM instruction.
5785 STRICT_P is true if we should do strict checking with
5786 aarch64_classify_address. */
5788 bool
5790 {
5793 /* PRFM accepts the same addresses as DImode... */
5798 /* ... except writeback forms. */
5800 }
5802 bool
5804 {
5805 rtx offset;
5809 }
5811 /* Classify the base of symbolic expression X. */
5813 enum aarch64_symbol_type
5815 {
5816 rtx offset;
5820 }
5823 /* Return TRUE if X is a legitimate address for accessing memory in
5824 mode MODE. */
5825 static bool
5827 {
5831 }
5833 /* Return TRUE if X is a legitimate address of type TYPE for accessing
5834 memory in mode MODE. STRICT_P is true if REG_OK_STRICT is in effect. */
5835 bool
5837 aarch64_addr_query_type type)
5838 {
5842 }
5844 /* Implement TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT. */
5846 static bool
5848 poly_int64 orig_offset,
5849 machine_mode mode)
5850 {
5851 HOST_WIDE_INT size;
5853 {
5856 /* A general SVE offset is A * VQ + B. Remove the A component from
5857 coefficient 0 in order to get the constant B. */
5860 /* Split an out-of-range address displacement into a base and
5861 offset. Use 4KB range for 1- and 2-byte accesses and a 16KB
5862 range otherwise to increase opportunities for sharing the base
5863 address of different sizes. Unaligned accesses use the signed
5864 9-bit range, TImode/TFmode use the intersection of signed
5865 scaled 7-bit and signed 9-bit offset. */
5870 else
5876 /* Split the offset into second_offset and the rest. */
5880 }
5881 else
5882 {
5883 /* Get the mode we should use as the basis of the range. For structure
5884 modes this is the mode of one vector. */
5886 machine_mode step_mode
5889 /* Get the "mul vl" multiplier we'd like to use. */
5893 /* LDR supports a 9-bit range, but the move patterns for
5894 structure modes require all vectors to be in range of the
5895 same base. The simplest way of accomodating that while still
5896 promoting reuse of anchor points between different modes is
5897 to use an 8-bit range unconditionally. */
5899 else
5900 /* Predicates are only handled singly, so we might as well use
5901 the full range. */
5906 /* Convert the "mul vl" multiplier into a byte offset. */
5911 /* Split the offset into second_offset and the rest. */
5915 }
5916 }
5918 /* Return the binary representation of floating point constant VALUE in INTVAL.
5919 If the value cannot be converted, return false without setting INTVAL.
5920 The conversion is done in the given MODE. */
5921 bool
5923 {
5925 /* We make a general exception for 0. */
5927 {
5930 }
5932 scalar_float_mode mode;
5936 /* Only support up to DF mode. */
5948 {
5952 }
5953 else
5958 }
5960 /* Return TRUE if rtx X is an immediate constant that can be moved using a
5961 single MOV(+MOVK) followed by an FMOV. */
5962 bool
5964 {
5969 /* Determine whether it's cheaper to write float constants as
5970 mov/movk pairs over ldr/adrp pairs. */
5976 {
5978 ? SImode
5983 }
5986 }
5988 /* Return TRUE if rtx X is immediate constant 0.0 */
5989 bool
5991 {
5998 }
6000 /* Return TRUE if rtx X is immediate constant that fits in a single
6001 MOVI immediate operation. */
6002 bool
6004 {
6008 machine_mode vmode;
6009 scalar_int_mode imode;
6014 {
6018 /* We make a general exception for 0. */
6023 }
6027 else
6030 /* use a 64 bit mode for everything except for DI/DF mode, where we use
6031 a 128 bit vector mode. */
6038 }
6041 /* Return the fixed registers used for condition codes. */
6043 static bool
6045 {
6049 }
6051 /* This function is used by the call expanders of the machine description.
6052 RESULT is the register in which the result is returned. It's NULL for
6053 "call" and "sibcall".
6054 MEM is the location of the function call.
6055 SIBCALL indicates whether this function call is normal call or sibling call.
6056 It will generate different pattern accordingly. */
6058 void
6060 {
6062 rtvec vec;
6063 machine_mode mode;
6070 /* Decide if we should generate indirect calls by loading the
6071 address of the callee into a register before performing
6072 the branch-and-link. */
6086 else
6093 }
6095 /* Emit call insn with PAT and do aarch64-specific handling. */
6097 void
6099 {
6105 }
6107 machine_mode
6109 {
6110 /* All floating point compares return CCFP if it is an equality
6111 comparison, and CCFPE otherwise. */
6113 {
6115 {
6136 }
6137 }
6139 /* Equality comparisons of short modes against zero can be performed
6140 using the TST instruction with the appropriate bitmask. */
6146 /* Similarly, comparisons of zero_extends from shorter modes can
6147 be performed using an ANDS with an immediate mask. */
6163 /* A compare with a shifted operand. Because of canonicalization,
6164 the comparison will have to be swapped when we emit the assembly
6165 code. */
6173 /* Similarly for a negated operand, but we can only do this for
6174 equalities. */
6181 /* A test for unsigned overflow. */
6188 /* For everything else, return CCmode. */
6190 }
6192 static int
6195 int
6197 {
6204 }
6206 static int
6208 {
6210 {
6214 {
6228 }
6233 {
6245 }
6250 {
6262 }
6267 {
6273 }
6278 {
6282 }
6287 {
6291 }
6296 }
6299 }
6301 bool
6303 HOST_WIDE_INT minval,
6304 HOST_WIDE_INT maxval)
6305 {
6306 rtx elt;
6310 }
6312 bool
6314 {
6316 }
6318 /* Return true if VEC is a constant in which every element is in the range
6319 [MINVAL, MAXVAL]. The elements do not need to have the same value. */
6321 static bool
6323 HOST_WIDE_INT minval,
6324 HOST_WIDE_INT maxval)
6325 {
6337 {
6342 }
6344 }
6346 /* N Z C V. */
6347 #define AARCH64_CC_V 1
6348 #define AARCH64_CC_C (1 << 1)
6349 #define AARCH64_CC_Z (1 << 2)
6350 #define AARCH64_CC_N (1 << 3)
6352 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
6354 {
6371 };
6373 /* Print floating-point vector immediate operand X to F, negating it
6374 first if NEGATE is true. Return true on success, false if it isn't
6375 a constant we can handle. */
6377 static bool
6379 {
6380 rtx elt;
6389 /* We only handle the SVE single-bit immediates here. */
6396 else
6400 }
6402 /* Return the equivalent letter for size. */
6403 static char
6405 {
6407 {
6413 }
6414 }
6416 /* Print operand X to file F in a target specific manner according to CODE.
6417 The acceptable formatting commands given by CODE are:
6418 'c': An integer or symbol address without a preceding #
6419 sign.
6420 'C': Take the duplicated element in a vector constant
6421 and print it in hex.
6422 'D': Take the duplicated element in a vector constant
6423 and print it as an unsigned integer, in decimal.
6424 'e': Print the sign/zero-extend size as a character 8->b,
6425 16->h, 32->w.
6426 'p': Prints N such that 2^N == X (X must be power of 2 and
6427 const int).
6428 'P': Print the number of non-zero bits in X (a const_int).
6429 'H': Print the higher numbered register of a pair (TImode)
6430 of regs.
6431 'm': Print a condition (eq, ne, etc).
6432 'M': Same as 'm', but invert condition.
6433 'N': Take the duplicated element in a vector constant
6434 and print the negative of it in decimal.
6435 'b/h/s/d/q': Print a scalar FP/SIMD register name.
6436 'S/T/U/V': Print a FP/SIMD register name for a register list.
6437 The register printed is the FP/SIMD register name
6438 of X + 0/1/2/3 for S/T/U/V.
6439 'R': Print a scalar FP/SIMD register name + 1.
6440 'X': Print bottom 16 bits of integer constant in hex.
6441 'w/x': Print a general register name or the zero register
6442 (32-bit or 64-bit).
6443 '0': Print a normal operand, if it's a general register,
6444 then we assume DImode.
6445 'k': Print NZCV for conditional compare instructions.
6446 'A': Output address constant representing the first
6447 argument of X, specifying a relocation offset
6448 if appropriate.
6449 'L': Output constant address specified by X
6450 with a relocation offset if appropriate.
6451 'G': Prints address of X, specifying a PC relative
6452 relocation mode if appropriate.
6453 'y': Output address of LDP or STP - this is used for
6454 some LDP/STPs which don't use a PARALLEL in their
6455 pattern (so the mode needs to be adjusted).
6456 'z': Output address of a typical LDP or STP. */
6458 static void
6460 {
6461 rtx elt;
6463 {
6466 {
6478 {
6481 }
6482 /* Fall through. */
6486 }
6490 {
6495 {
6498 }
6501 {
6514 }
6515 }
6519 {
6523 {
6526 }
6529 }
6534 {
6537 }
6544 {
6547 }
6554 {
6556 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
6558 {
6562 }
6565 {
6568 }
6575 }
6580 {
6583 }
6589 ;
6590 else
6591 {
6594 }
6603 {
6604 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
6606 }
6615 {
6616 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
6618 }
6626 {
6627 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
6629 }
6635 {
6638 }
6643 {
6644 /* Print a replicated constant in hex. */
6646 {
6649 }
6652 }
6656 {
6657 /* Print a replicated constant in decimal, treating it as
6658 unsigned. */
6660 {
6663 }
6666 }
6673 {
6676 }
6679 {
6682 }
6685 {
6688 }
6690 /* Fall through */
6694 {
6697 }
6700 {
6703 {
6706 else
6707 {
6708 char suffix
6713 }
6714 }
6715 else
6734 {
6737 }
6738 /* fall through */
6742 {
6745 }
6751 ;
6752 else
6753 {
6756 }
6760 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
6761 be getting CONST_DOUBLEs holding integers. */
6764 {
6767 }
6769 {
6770 #define buf_size 20
6778 #undef buf_size
6779 }
6785 }
6793 {
6820 }
6826 {
6861 }
6867 {
6873 }
6878 {
6879 HOST_WIDE_INT cond_code;
6882 {
6885 }
6890 }
6895 {
6900 {
6903 }
6906 /* LDP/STP which uses a single double-width memory operand.
6907 Adjust the mode to appear like a typical LDP/STP.
6908 Currently this is supported for 16-byte accesses only. */
6913 }
6919 }
6920 }
6922 /* Print address 'x' of a memory access with mode 'mode'.
6923 'op' is the context required by aarch64_classify_address. It can either be
6924 MEM for a normal memory access or PARALLEL for LDP/STP. */
6925 static bool
6927 aarch64_addr_query_type type)
6928 {
6932 /* Check all addresses are Pmode - including ILP32. */
6937 {
6942 {
6943 HOST_WIDE_INT vnum
6948 }
6950 {
6951 HOST_WIDE_INT vnum
6956 }
6957 else
6966 else
6975 else
6984 else
6990 /* Writeback is only supported for fixed-width modes. */
6993 {
7016 }
7028 }
7031 }
7033 /* Print address 'x' of a LDP/STP with mode 'mode'. */
7034 static bool
7036 {
7038 }
7040 /* Print address 'x' of a memory access with mode 'mode'. */
7041 static void
7043 {
7046 }
7048 bool
7050 {
7057 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
7058 referencing instruction, but they are constant offsets, not
7059 symbols. */
7065 {
7067 {
7073 }
7076 }
7079 }
7081 /* Implement REGNO_REG_CLASS. */
7083 enum reg_class
7085 {
7103 }
7105 /* OFFSET is an address offset for mode MODE, which has SIZE bytes.
7106 If OFFSET is out of range, return an offset of an anchor point
7107 that is in range. Return 0 otherwise. */
7109 static HOST_WIDE_INT
7111 machine_mode mode)
7112 {
7113 /* Does it look like we'll need a 16-byte load/store-pair operation? */
7117 /* For offsets that aren't a multiple of the access size, the limit is
7118 -256...255. */
7120 {
7121 /* BLKmode typically uses LDP of X-registers. */
7125 }
7127 /* Small negative offsets are supported. */
7134 /* Use 12-bit offset by access size. */
7136 }
7138 static rtx
7140 {
7141 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
7142 where mask is selected by alignment and size of the offset.
7143 We try to pick as large a range for the offset as possible to
7144 maximize the chance of a CSE. However, for aligned addresses
7145 we limit the range to 4k so that structures with different sized
7146 elements are likely to use the same base. We need to be careful
7147 not to split a CONST for some forms of address expression, otherwise
7148 it will generate sub-optimal code. */
7151 {
7157 {
7161 /* Force any scaling into a temp for CSE. */
7165 /* Let the pointer register be in op0. */
7169 /* If the pointer is virtual or frame related, then we know that
7170 virtual register instantiation or register elimination is going
7171 to apply a second constant. We want the two constants folded
7172 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
7174 {
7178 }
7180 /* Otherwise, in order to encourage CSE (and thence loop strength
7181 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
7185 }
7187 HOST_WIDE_INT size;
7189 {
7191 mode);
7193 {
7197 }
7198 }
7199 }
7202 }
7204 /* Return the reload icode required for a constant pool in mode. */
7205 static enum insn_code
7207 {
7209 {
7245 }
7248 }
7249 static reg_class_t
7251 reg_class_t rclass,
7252 machine_mode mode,
7254 {
7255 /* Use aarch64_sve_reload_be for SVE reloads that cannot be handled
7256 directly by the *aarch64_sve_mov<mode>_be move pattern. See the
7257 comment at the head of aarch64-sve.md for more details about the
7258 big-endian handling. */
7264 {
7267 }
7269 /* If we have to disable direct literal pool loads and stores because the
7270 function is too big, then we need a scratch register. */
7275 {
7278 }
7280 /* Without the TARGET_SIMD instructions we cannot move a Q register
7281 to a Q register directly. We need a scratch. */
7285 {
7291 }
7293 /* A TFmode or TImode memory access should be handled via an FP_REGS
7294 because AArch64 has richer addressing modes for LDR/STR instructions
7295 than LDP/STP instructions. */
7304 }
7306 static bool
7308 {
7311 /* If we need a frame pointer, ARG_POINTER_REGNUM and FRAME_POINTER_REGNUM
7312 can only eliminate to HARD_FRAME_POINTER_REGNUM. */
7316 }
7318 poly_int64
7320 {
7324 {
7331 }
7334 {
7338 }
7341 }
7343 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
7344 previous frame. */
7346 rtx
7348 {
7352 }
7355 static void
7357 {
7359 {
7362 }
7363 else
7364 {
7367 }
7372 }
7374 static void
7376 {
7380 /* Don't need to copy the trailing D-words, we fill those in below. */
7392 /* XXX We should really define a "clear_cache" pattern and use
7393 gen_clear_cache(). */
7398 ptr_mode);
7399 }
7401 static unsigned char
7403 {
7404 /* ??? Logically we should only need to provide a value when
7405 HARD_REGNO_MODE_OK says that at least one register in REGCLASS
7406 can hold MODE, but at the moment we need to handle all modes.
7407 Just ignore any runtime parts for registers that can't store them. */
7411 {
7437 }
7439 }
7441 static reg_class_t
7443 {
7448 {
7454 }
7456 /* Register eliminiation can result in a request for
7457 SP+constant->FP_REGS. We cannot support such operations which
7458 use SP as source and an FP_REG as destination, so reject out
7459 right now. */
7461 {
7464 /* Look through a possible SUBREG introduced by ILP32. */
7470 POINTER_REGS));
7472 }
7475 }
7477 void
7479 {
7481 }
7483 static void
7485 {
7488 else
7489 {
7491 /* While priority is known to be in range [0, 65535], so 18 bytes
7492 would be enough, the compiler might not know that. To avoid
7493 -Wformat-truncation false positive, use a larger size. */
7500 }
7501 }
7503 static void
7505 {
7508 else
7509 {
7511 /* While priority is known to be in range [0, 65535], so 18 bytes
7512 would be enough, the compiler might not know that. To avoid
7513 -Wformat-truncation false positive, use a larger size. */
7520 }
7521 }
7525 {
7531 {
7532 {
7535 },
7536 {
7539 },
7540 {
7543 },
7544 /* We assume that DImode is only generated when not optimizing and
7545 that we don't really need 64-bit address offsets. That would
7546 imply an object file with 8GB of code in a single function! */
7547 {
7550 }
7551 };
7560 /* Need to implement table size reduction, by chaning the code below. */
7570 }
7573 /* Return size in bits of an arithmetic operand which is shifted/scaled and
7574 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
7575 operator. */
7577 int
7579 {
7581 {
7584 {
7588 }
7589 }
7591 }
7593 /* Constant pools are per function only when PC relative
7594 literal loads are true or we are in the large memory
7595 model. */
7599 {
7602 }
7604 static bool
7606 {
7607 /* Fixme:: In an ideal world this would work similar
7608 to the logic in aarch64_select_rtx_section but this
7609 breaks bootstrap in gcc go. For now we workaround
7610 this by returning false here. */
7612 }
7614 /* Select appropriate section for constants depending
7615 on where we place literal pools. */
7619 rtx x,
7621 {
7626 }
7628 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
7629 void
7631 HOST_WIDE_INT offset)
7632 {
7633 /* When using per-function literal pools, we must ensure that any code
7634 section is aligned to the minimal instruction length, lest we get
7635 errors from the assembler re "unaligned instructions". */
7638 }
7640 /* Costs. */
7642 /* Helper function for rtx cost calculation. Strip a shift expression
7643 from X. Returns the inner operand if successful, or the original
7644 expression on failure. */
7645 static rtx
7647 {
7650 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
7651 we can convert both to ROR during final output. */
7666 }
7668 /* Helper function for rtx cost calculation. Strip an extend
7669 expression from X. Returns the inner operand if successful, or the
7670 original expression on failure. We deal with a number of possible
7671 canonicalization variations here. If STRIP_SHIFT is true, then
7672 we can strip off a shift also. */
7673 static rtx
7675 {
7676 scalar_int_mode mode;
7682 /* Zero and sign extraction of a widened value. */
7690 /* It can also be represented (for zero-extend) as an AND with an
7691 immediate. */
7700 /* Now handle extended register, as this may also have an optional
7701 left shift by 1..4. */
7716 }
7718 /* Return true iff CODE is a shift supported in combination
7719 with arithmetic instructions. */
7721 static bool
7723 {
7725 }
7728 /* Return true iff X is a cheap shift without a sign extend. */
7730 static bool
7732 {
7758 }
7760 /* Helper function for rtx cost calculation. Calculate the cost of
7761 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
7762 Return the calculated cost of the expression, recursing manually in to
7763 operands where needed. */
7765 static int
7767 {
7783 /* Integer multiply/fma. */
7785 {
7786 /* The multiply will be canonicalized as a shift, cost it as such. */
7790 {
7794 {
7796 {
7797 /* If the shift is considered cheap,
7798 then don't add any cost. */
7800 ;
7802 /* ARITH + shift-by-register. */
7805 /* ARITH + extended register. We don't have a cost field
7806 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
7808 else
7809 /* ARITH + shift-by-immediate. */
7811 }
7812 else
7813 /* LSL (immediate). */
7816 }
7817 /* Strip extends as we will have costed them in the case above. */
7824 }
7826 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
7827 compound and let the below cases handle it. After all, MNEG is a
7828 special-case alias of MSUB. */
7830 {
7833 }
7835 /* Integer multiplies or FMAs have zero/sign extending variants. */
7840 {
7845 {
7847 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
7849 else
7850 /* MUL/SMULL/UMULL. */
7852 }
7855 }
7857 /* This is either an integer multiply or a MADD. In both cases
7858 we want to recurse and cost the operands. */
7863 {
7865 /* MADD/MSUB. */
7867 else
7868 /* MUL. */
7870 }
7873 }
7874 else
7875 {
7877 {
7878 /* Floating-point FMA/FMUL can also support negations of the
7879 operands, unless the rounding mode is upward or downward in
7880 which case FNMUL is different than FMUL with operand negation. */
7884 {
7889 }
7892 /* FMADD/FNMADD/FNMSUB/FMSUB. */
7894 else
7895 /* FMUL/FNMUL. */
7897 }
7902 }
7903 }
7905 static int
7907 machine_mode mode,
7908 addr_space_t as ATTRIBUTE_UNUSED,
7910 {
7918 {
7920 {
7921 /* This is a CONST or SYMBOL ref which will be split
7922 in a different way depending on the code model in use.
7923 Cost it through the generic infrastructure. */
7925 /* Divide through by the cost of one instruction to
7926 bring it to the same units as the address costs. */
7928 /* The cost is then the cost of preparing the address,
7929 followed by an immediate (possibly 0) offset. */
7931 }
7932 else
7933 {
7934 /* This is most likely a jump table from a case
7935 statement. */
7937 }
7938 }
7941 {
7953 else
7972 }
7976 {
7977 /* For the sake of calculating the cost of the shifted register
7978 component, we can treat same sized modes in the same way. */
7985 else
7986 /* We can't tell, or this is a 128-bit vector. */
7988 }
7991 }
7993 /* Return the cost of a branch. If SPEED_P is true then the compiler is
7994 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
7995 to be taken. */
7997 int
7999 {
8000 /* When optimizing for speed, use the cost of unpredictable branches. */
8006 else
8008 }
8010 /* Return true if the RTX X in mode MODE is a zero or sign extract
8011 usable in an ADD or SUB (extended register) instruction. */
8012 static bool
8014 {
8015 /* Catch add with a sign extract.
8016 This is add_<optab><mode>_multp2. */
8019 {
8030 op1))
8031 {
8033 }
8034 }
8035 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
8036 No shift. */
8042 }
8044 static bool
8046 {
8048 {
8060 }
8061 }
8063 /* Return true iff X is an rtx that will match an extr instruction
8064 i.e. as described in the *extr<mode>5_insn family of patterns.
8065 OP0 and OP1 will be set to the operands of the shifts involved
8066 on success and will be NULL_RTX otherwise. */
8068 static bool
8070 {
8072 scalar_int_mode mode;
8087 {
8088 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
8100 {
8104 }
8105 }
8108 }
8110 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
8111 storing it in *COST. Result is true if the total cost of the operation
8112 has now been calculated. */
8113 static bool
8115 {
8116 rtx inner;
8117 rtx comparator;
8121 {
8125 }
8126 else
8127 {
8131 }
8134 {
8135 /* Conditional branch. */
8138 else
8139 {
8141 {
8143 {
8144 /* TBZ/TBNZ/CBZ/CBNZ. */
8146 /* TBZ/TBNZ. */
8149 else
8150 /* CBZ/CBNZ. */
8154 }
8155 }
8157 {
8158 /* TBZ/TBNZ. */
8161 }
8162 }
8163 }
8165 {
8166 /* CCMP. */
8168 {
8169 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
8173 {
8180 else
8182 }
8184 }
8186 /* It's a conditional operation based on the status flags,
8187 so it must be some flavor of CSEL. */
8189 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
8195 {
8196 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
8199 }
8204 }
8206 /* We don't know what this is, cost all operands. */
8208 }
8210 /* Check whether X is a bitfield operation of the form shift + extend that
8211 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
8212 operand to which the bitfield operation is applied. Otherwise return
8213 NULL_RTX. */
8215 static rtx
8217 {
8231 {
8249 }
8252 }
8254 /* Return true if the mask and a shift amount from an RTX of the form
8255 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
8256 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
8258 bool
8260 rtx shft_amnt)
8261 {
8266 }
8268 /* Calculate the cost of calculating X, storing it in *COST. Result
8269 is true if the total cost of the operation has now been calculated. */
8270 static bool
8273 {
8278 scalar_int_mode int_mode;
8280 /* By default, assume that everything has equivalent cost to the
8281 cheapest instruction. Any additional costs are applied as a delta
8282 above this default. */
8286 {
8288 /* The cost depends entirely on the operands to SET. */
8294 {
8297 {
8311 }
8320 /* Fall through. */
8322 /* The cost is one per vector-register copied. */
8324 {
8327 }
8328 /* const0_rtx is in general free, but we will use an
8329 instruction to set a register to 0. */
8331 {
8332 /* The cost is 1 per register copied. */
8335 }
8336 else
8337 /* Cost is just the cost of the RHS of the set. */
8343 /* Bit-field insertion. Strip any redundant widening of
8344 the RHS to meet the width of the target. */
8355 {
8356 /* MOV immediate is assumed to always be cheap. */
8358 }
8359 else
8360 {
8361 /* BFM. */
8365 }
8370 /* We can't make sense of this, assume default cost. */
8373 }
8377 /* If an instruction can incorporate a constant within the
8378 instruction, the instruction's expression avoids calling
8379 rtx_cost() on the constant. If rtx_cost() is called on a
8380 constant, then it is usually because the constant must be
8381 moved into a register by one or more instructions.
8383 The exception is constant 0, which can be expressed
8384 as XZR/WZR and is therefore free. The exception to this is
8385 if we have (set (reg) (const0_rtx)) in which case we must cost
8386 the move. However, we can catch that when we cost the SET, so
8387 we don't need to consider that here. */
8390 else
8391 {
8392 /* To an approximation, building any other constant is
8393 proportionally expensive to the number of instructions
8394 required to build that constant. This is true whether we
8395 are compiling for SPEED or otherwise. */
8400 }
8405 /* First determine number of instructions to do the move
8406 as an integer constant. */
8410 {
8416 ? SImode
8422 }
8425 {
8426 /* mov[df,sf]_aarch64. */
8428 /* FMOV (scalar immediate). */
8431 {
8432 /* This will be a load from memory. */
8435 else
8437 }
8438 else
8439 /* Otherwise this is +0.0. We get this using MOVI d0, #0
8440 or MOV v0.s[0], wzr - neither of which are modeled by the
8441 cost tables. Just use the default cost. */
8442 {
8443 }
8444 }
8450 {
8451 /* For loads we want the base cost of a load, plus an
8452 approximation for the additional cost of the addressing
8453 mode. */
8467 }
8475 {
8477 {
8478 /* FNEG. */
8480 }
8482 }
8485 {
8488 {
8489 /* CSETM. */
8492 }
8494 /* Cost this as SUB wzr, X. */
8498 }
8501 {
8502 /* Support (neg(fma...)) as a single instruction only if
8503 sign of zeros is unimportant. This matches the decision
8504 making in aarch64.md. */
8506 {
8507 /* FNMADD. */
8510 }
8512 {
8513 /* FNMUL. */
8516 }
8518 /* FNEG. */
8521 }
8528 {
8531 else
8533 }
8543 {
8547 }
8550 {
8551 /* TODO: A write to the CC flags possibly costs extra, this
8552 needs encoding in the cost tables. */
8555 /* ANDS. */
8557 {
8560 }
8563 {
8564 /* ADDS (and CMN alias). */
8567 }
8570 {
8571 /* SUBS. */
8574 }
8579 {
8580 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
8581 Handle it here directly rather than going to cost_logic
8582 since we know the immediate generated for the TST is valid
8583 so we can avoid creating an intermediate rtx for it only
8584 for costing purposes. */
8591 }
8594 {
8595 /* CMN. */
8602 }
8604 /* CMP.
8606 Compare can freely swap the order of operands, and
8607 canonicalization puts the more complex operation first.
8608 But the integer MINUS logic expects the shift/extend
8609 operation in op1. */
8612 {
8615 }
8617 }
8620 {
8621 /* FCMP. */
8626 {
8628 /* FCMP supports constant 0.0 for no extra cost. */
8630 }
8632 }
8635 {
8636 /* Vector compare. */
8641 {
8642 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
8643 cost. */
8645 }
8647 }
8651 {
8655 cost_minus:
8658 /* Detect valid immediates. */
8664 {
8666 /* SUB(S) (immediate). */
8669 }
8671 /* Look for SUB (extended register). */
8674 {
8682 }
8686 /* Cost this as an FMA-alike operation. */
8690 {
8693 speed);
8695 }
8700 {
8702 {
8703 /* Vector SUB. */
8705 }
8707 {
8708 /* SUB(S). */
8710 }
8712 {
8713 /* FSUB. */
8715 }
8716 }
8718 }
8721 {
8722 rtx new_op0;
8727 cost_plus:
8730 {
8731 /* CSINC. */
8735 }
8740 {
8744 /* ADD (immediate). */
8747 }
8751 /* Look for ADD (extended register). */
8754 {
8762 }
8764 /* Strip any extend, leave shifts behind as we will
8765 cost them through mult_cost. */
8770 {
8772 speed);
8774 }
8779 {
8781 {
8782 /* Vector ADD. */
8784 }
8786 {
8787 /* ADD. */
8789 }
8791 {
8792 /* FADD. */
8794 }
8795 }
8797 }
8803 {
8806 else
8808 }
8813 {
8817 {
8820 else
8822 }
8824 }
8827 {
8834 }
8835 /* Fall through. */
8838 cost_logic:
8843 {
8847 }
8855 {
8856 /* This is a UBFM/SBFM. */
8861 }
8864 {
8866 {
8867 /* We have a mask + shift version of a UBFIZ
8868 i.e. the *andim_ashift<mode>_bfiz pattern. */
8872 {
8879 }
8881 {
8882 /* We possibly get the immediate for free, this is not
8883 modelled. */
8890 }
8891 }
8892 else
8893 {
8896 /* Handle ORN, EON, or BIC. */
8902 /* If we had a shift on op0 then this is a logical-shift-
8903 by-register/immediate operation. Otherwise, this is just
8904 a logical operation. */
8906 {
8908 {
8909 /* Shift by immediate. */
8912 else
8914 }
8915 else
8917 }
8919 /* In both cases we want to cost both operands. */
8926 }
8927 }
8935 {
8936 /* Vector NOT. */
8939 }
8941 /* MVN-shifted-reg. */
8943 {
8950 }
8951 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
8952 Handle the second form here taking care that 'a' in the above can
8953 be a shift. */
8955 {
8964 {
8967 else
8969 }
8972 }
8973 /* MVN. */
8982 /* If a value is written in SI mode, then zero extended to DI
8983 mode, the operation will in general be free as a write to
8984 a 'w' register implicitly zeroes the upper bits of an 'x'
8985 register. However, if this is
8987 (set (reg) (zero_extend (reg)))
8989 we must cost the explicit register move. */
8993 {
8996 /* If OP_COST is non-zero, then the cost of the zero extend
8997 is effectively the cost of the inner operation. Otherwise
8998 we have a MOV instruction and we take the cost from the MOV
8999 itself. This is true independently of whether we are
9000 optimizing for space or time. */
9005 }
9007 {
9008 /* All loads can zero extend to any size for free. */
9011 }
9015 {
9020 }
9023 {
9025 {
9026 /* UMOV. */
9028 }
9029 else
9030 {
9031 /* We generate an AND instead of UXTB/UXTH. */
9033 }
9034 }
9039 {
9040 /* LDRSH. */
9042 {
9049 }
9051 }
9055 {
9060 }
9063 {
9066 else
9068 }
9076 {
9078 {
9080 {
9081 /* Vector shift (immediate). */
9083 }
9084 else
9085 {
9086 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
9087 aliases. */
9089 }
9090 }
9092 /* We can incorporate zero/sign extend for free. */
9099 }
9100 else
9101 {
9103 {
9105 /* Vector shift (register). */
9107 }
9108 else
9109 {
9111 /* LSLV. */
9118 {
9120 /* We already demanded XEXP (op1, 0) to be REG_P, so
9121 don't recurse into it. */
9123 }
9124 }
9126 }
9136 {
9137 /* ASR (immediate) and friends. */
9139 {
9142 else
9144 }
9148 }
9149 else
9150 {
9152 {
9154 /* Vector shift (register). */
9156 }
9157 else
9158 {
9160 /* ASR (register) and friends. */
9167 {
9169 /* We already demanded XEXP (op1, 0) to be REG_P, so
9170 don't recurse into it. */
9172 }
9173 }
9175 }
9181 {
9182 /* LDR. */
9185 }
9188 {
9189 /* ADRP, followed by ADD. */
9193 }
9196 {
9197 /* ADR. */
9200 }
9203 {
9204 /* One extra load instruction, after accessing the GOT. */
9208 }
9213 /* ADRP/ADD (immediate). */
9220 /* UBFX/SBFX. */
9222 {
9225 else
9227 }
9229 /* We can trust that the immediates used will be correct (there
9230 are no by-register forms), so we need only cost op0. */
9236 /* aarch64_rtx_mult_cost always handles recursion to its
9237 operands. */
9241 /* We can expand signed mod by power of 2 using a NEGS, two parallel
9242 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
9243 an unconditional negate. This case should only ever be reached through
9244 the set_smod_pow2_cheap check in expmed.c. */
9248 {
9249 /* We expand to 4 instructions. Reset the baseline. */
9257 }
9259 /* Fall-through. */
9262 {
9263 /* Slighly prefer UMOD over SMOD. */
9270 }
9277 {
9281 /* There is no integer SQRT, so only DIV and UDIV can get
9282 here. */
9284 /* Slighly prefer UDIV over SDIV. */
9286 else
9288 }
9314 {
9317 else
9319 }
9321 /* FMSUB, FNMADD, and FNMSUB are free. */
9328 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
9329 and the by-element operand as operand 0. */
9333 /* Catch vector-by-element operations. The by-element operand can
9334 either be (vec_duplicate (vec_select (x))) or just
9335 (vec_select (x)), depending on whether we are multiplying by
9336 a vector or a scalar.
9338 Canonicalization is not very good in these cases, FMA4 will put the
9339 by-element operand as operand 0, FNMA4 will have it as operand 1. */
9350 /* If the remaining parameters are not registers,
9351 get the cost to put them into registers. */
9365 {
9367 {
9368 /*Vector truncate. */
9370 }
9371 else
9373 }
9378 {
9380 {
9381 /*Vector conversion. */
9383 }
9384 else
9386 }
9392 /* Strip the rounding part. They will all be implemented
9393 by the fcvt* family of instructions anyway. */
9395 {
9404 }
9407 {
9410 else
9412 }
9414 /* We can combine fmul by a power of 2 followed by a fcvt into a single
9415 fixed-point fcvt. */
9420 {
9424 }
9431 {
9432 /* ABS (vector). */
9435 }
9437 {
9440 /* FABD, which is analogous to FADD. */
9442 {
9449 }
9450 /* Simple FABS is analogous to FNEG. */
9453 }
9454 else
9455 {
9456 /* Integer ABS will either be split to
9457 two arithmetic instructions, or will be an ABS
9458 (scalar), which we don't model. */
9462 }
9468 {
9471 else
9472 {
9473 /* FMAXNM/FMINNM/FMAX/FMIN.
9474 TODO: This may not be accurate for all implementations, but
9475 we do not model this in the cost tables. */
9477 }
9478 }
9482 /* The floating point round to integer frint* instructions. */
9484 {
9489 }
9492 {
9497 }
9502 /* Decompose <su>muldi3_highpart. */
9504 mode == DImode
9505 /* (lshiftrt:TI */
9508 /* (mult:TI */
9510 /* (ANY_EXTEND:TI (reg:DI))
9511 (ANY_EXTEND:TI (reg:DI))) */
9518 /* (const_int 64) */
9521 {
9522 /* UMULH/SMULH. */
9530 }
9532 /* Fall through. */
9535 }
9543 }
9545 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
9546 calculated for X. This cost is stored in *COST. Returns true
9547 if the total cost of X was calculated. */
9548 static bool
9551 {
9556 {
9561 }
9564 }
9566 static int
9569 {
9575 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
9582 /* Moving between GPR and stack cost is the same as GP2GP. */
9587 /* To/From the stack register, we move via the gprs. */
9593 {
9594 /* 128-bit operations on general registers require 2 instructions. */
9602 /* When AdvSIMD instructions are disabled it is not possible to move
9603 a 128-bit value directly between Q registers. This is handled in
9604 secondary reload. A general register is used as a scratch to move
9605 the upper DI value and the lower DI value is moved directly,
9606 hence the cost is the sum of three moves. */
9611 }
9621 }
9623 static int
9625 reg_class_t rclass ATTRIBUTE_UNUSED,
9627 {
9629 }
9631 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
9632 to optimize 1.0/sqrt. */
9634 static bool
9636 {
9638 && flag_unsafe_math_optimizations
9642 }
9644 /* Function to decide when to use the approximate reciprocal square root
9645 builtin. */
9647 static tree
9649 {
9655 }
9659 /* Select reciprocal square root initial estimate insn depending on machine
9660 mode. */
9662 static rsqrte_type
9664 {
9666 {
9673 }
9674 }
9678 /* Select reciprocal square root series step insn depending on machine mode. */
9680 static rsqrts_type
9682 {
9684 {
9691 }
9692 }
9694 /* Emit instruction sequence to compute either the approximate square root
9695 or its approximate reciprocal, depending on the flag RECP, and return
9696 whether the sequence was emitted or not. */
9698 bool
9700 {
9704 {
9707 }
9710 {
9717 || flag_trapping_math
9718 || !flag_unsafe_math_optimizations
9721 }
9722 else
9723 /* Caller assumes we cannot fail. */
9729 /* When calculating the approximate square root, compare the
9730 argument with 0.0 and create a mask. */
9736 /* Estimate the approximate reciprocal square root. */
9740 /* Iterate over the series twice for SF and thrice for DF. */
9743 /* Optionally iterate over the series once less for faster performance
9744 while sacrificing the accuracy. */
9747 iterations--;
9749 /* Iterate over the series to calculate the approximate reciprocal square
9750 root. */
9753 {
9761 }
9764 {
9765 /* Qualify the approximate reciprocal square root when the argument is
9766 0.0 by squashing the intermediary result to 0.0. */
9772 /* Calculate the approximate square root. */
9774 }
9776 /* Finalize the approximation. */
9780 }
9784 /* Select reciprocal initial estimate insn depending on machine mode. */
9786 static recpe_type
9788 {
9790 {
9797 }
9798 }
9802 /* Select reciprocal series step insn depending on machine mode. */
9804 static recps_type
9806 {
9808 {
9815 }
9816 }
9818 /* Emit the instruction sequence to compute the approximation for the division
9819 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
9821 bool
9823 {
9834 || flag_trapping_math
9835 || !flag_unsafe_math_optimizations
9843 /* Estimate the approximate reciprocal. */
9847 /* Iterate over the series twice for SF and thrice for DF. */
9850 /* Optionally iterate over the series once less for faster performance,
9851 while sacrificing the accuracy. */
9853 iterations--;
9855 /* Iterate over the series to calculate the approximate reciprocal. */
9858 {
9863 }
9866 {
9867 /* As the approximate reciprocal of DEN is already calculated, only
9868 calculate the approximate division when NUM is not 1.0. */
9871 }
9873 /* Finalize the approximation. */
9876 }
9878 /* Return the number of instructions that can be issued per cycle. */
9879 static int
9881 {
9883 }
9885 static int
9887 {
9891 }
9894 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
9895 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
9896 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
9898 static int
9901 {
9903 }
9906 /* Vectorizer cost model target hooks. */
9908 /* Implement targetm.vectorize.builtin_vectorization_cost. */
9909 static int
9911 tree vectype,
9913 {
9922 {
9973 }
9974 }
9976 /* Implement targetm.vectorize.add_stmt_cost. */
9977 static unsigned
9981 {
9986 {
9991 /* Statements in an inner loop relative to the loop being
9992 vectorized are weighted more heavily. The value here is
9993 arbitrary and could potentially be improved with analysis. */
9999 }
10002 }
10006 /* Parse the TO_PARSE string and put the architecture struct that it
10007 selects into RES and the architectural features into ISA_FLAGS.
10008 Return an aarch64_parse_opt_result describing the parse result.
10009 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
10011 static enum aarch64_parse_opt_result
10014 {
10026 else
10033 /* Loop through the list of supported ARCHes to find a match. */
10035 {
10037 {
10041 {
10042 /* TO_PARSE string contains at least one extension. */
10043 enum aarch64_parse_opt_result ext_res
10048 }
10049 /* Extension parsing was successful. Confirm the result
10050 arch and ISA flags. */
10054 }
10055 }
10057 /* ARCH name not found in list. */
10059 }
10061 /* Parse the TO_PARSE string and put the result tuning in RES and the
10062 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
10063 describing the parse result. If there is an error parsing, RES and
10064 ISA_FLAGS are left unchanged. */
10066 static enum aarch64_parse_opt_result
10069 {
10081 else
10088 /* Loop through the list of supported CPUs to find a match. */
10090 {
10092 {
10097 {
10098 /* TO_PARSE string contains at least one extension. */
10099 enum aarch64_parse_opt_result ext_res
10104 }
10105 /* Extension parsing was successfull. Confirm the result
10106 cpu and ISA flags. */
10110 }
10111 }
10113 /* CPU name not found in list. */
10115 }
10117 /* Parse the TO_PARSE string and put the cpu it selects into RES.
10118 Return an aarch64_parse_opt_result describing the parse result.
10119 If the parsing fails the RES does not change. */
10121 static enum aarch64_parse_opt_result
10123 {
10129 /* Loop through the list of supported CPUs to find a match. */
10131 {
10133 {
10136 }
10137 }
10139 /* CPU name not found in list. */
10141 }
10143 /* Parse TOKEN, which has length LENGTH to see if it is an option
10144 described in FLAG. If it is, return the index bit for that fusion type.
10145 If not, error (printing OPTION_NAME) and return zero. */
10147 static unsigned int
10152 {
10154 {
10158 }
10162 }
10164 /* Parse OPTION which is a comma-separated list of flags to enable.
10165 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
10166 default state we inherit from the CPU tuning structures. OPTION_NAME
10167 gives the top-level option we are parsing in the -moverride string,
10168 for use in error messages. */
10170 static unsigned int
10175 {
10182 {
10185 token_length,
10186 flags,
10187 option_name);
10188 /* If we find "none" (or, for simplicity's sake, an error) anywhere
10189 in the token stream, reset the supported operations. So:
10191 adrp+add.cmp+branch.none.adrp+add
10193 would have the result of turning on only adrp+add fusion. */
10199 }
10201 /* We ended with a comma, print something. */
10203 {
10206 }
10208 /* We still have one more token to parse. */
10211 token_length,
10212 flags,
10213 option_name);
10219 }
10221 /* Support for overriding instruction fusion. */
10223 static void
10226 {
10228 aarch64_fusible_pairs,
10231 }
10233 /* Support for overriding other tuning flags. */
10235 static void
10238 {
10239 tune->extra_tuning_flags
10241 aarch64_tuning_flags,
10244 }
10246 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
10247 we understand. If it is, extract the option string and handoff to
10248 the appropriate function. */
10250 void
10254 {
10260 {
10263 }
10265 /* Get the length of the option name. */
10267 /* Skip the '=' to get to the option string. */
10268 option_part++;
10271 {
10273 {
10276 }
10277 }
10281 }
10283 /* A checking mechanism for the implementation of the tls size. */
10285 static void
10287 {
10292 {
10294 /* Both the default and maximum TLS size allowed under tiny is 1M which
10295 needs two instructions to address, so we clamp the size to 24. */
10300 /* The maximum TLS size allowed under small is 4G. */
10305 /* The maximum TLS size allowed under large is 16E.
10306 FIXME: 16E should be 64bit, we only support 48bit offset now. */
10312 }
10315 }
10317 /* Parse STRING looking for options in the format:
10318 string :: option:string
10319 option :: name=substring
10320 name :: {a-z}
10321 substring :: defined by option. */
10323 static void
10326 {
10337 {
10339 /* Make this substring look like a string. */
10343 }
10345 /* One last option to parse. */
10348 }
10351 static void
10353 {
10354 /* PR 70044: We have to be careful about being called multiple times for the
10355 same function. This means all changes should be repeatable. */
10357 /* If the frame pointer is enabled, set it to a special value that behaves
10358 similar to frame pointer omission. If we don't do this all leaf functions
10359 will get a frame pointer even if flag_omit_leaf_frame_pointer is set.
10360 If flag_omit_frame_pointer has this special value, we must force the
10361 frame pointer if not in a leaf function. We also need to force it in a
10362 leaf function if flag_omit_frame_pointer is not set or if LR is used. */
10366 /* If not optimizing for size, set the default
10367 alignment to what the target wants. */
10369 {
10376 }
10378 /* We default to no pc-relative literal loads. */
10382 /* If -mpc-relative-literal-loads is set on the command line, this
10383 implies that the user asked for PC relative literal loads. */
10387 /* In the tiny memory model it makes no sense to disallow PC relative
10388 literal pool loads. */
10393 /* When enabling the lower precision Newton series for the square root, also
10394 enable it for the reciprocal square root, since the latter is an
10395 intermediary step for the former. */
10398 }
10400 /* 'Unpack' up the internal tuning structs and update the options
10401 in OPTS. The caller must have set up selected_tune and selected_arch
10402 as all the other target-specific codegen decisions are
10403 derived from them. */
10405 void
10407 {
10410 /* Make a copy of the tuning parameters attached to the core, which
10411 we may later overwrite. */
10419 /* This target defaults to strict volatile bitfields. */
10428 {
10440 }
10442 /* We don't mind passing in global_options_set here as we don't use
10443 the *options_set structs anyway. */
10445 queue_depth,
10449 /* Set up parameters to be used in prefetching algorithm. Do not
10450 override the defaults unless we are tuning for a core we have
10451 researched values for. */
10473 /* Use the alternative scheduling-pressure algorithm by default. */
10478 /* Enable sw prefetching at specified optimization level for
10479 CPUS that have prefetch. Lower optimization level threshold by 1
10480 when profiling is enabled. */
10488 }
10490 /* Print a hint with a suggestion for a core or architecture name that
10491 most closely resembles what the user passed in STR. ARCH is true if
10492 the user is asking for an architecture name. ARCH is false if the user
10493 is asking for a core name. */
10495 static void
10497 {
10508 }
10510 /* Print a hint with a suggestion for a core name that most closely resembles
10511 what the user passed in STR. */
10515 {
10517 }
10519 /* Print a hint with a suggestion for an architecture name that most closely
10520 resembles what the user passed in STR. */
10524 {
10526 }
10528 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
10529 specified in STR and throw errors if appropriate. Put the results if
10530 they are valid in RES and ISA_FLAGS. Return whether the option is
10531 valid. */
10533 static bool
10536 {
10537 enum aarch64_parse_opt_result parse_res
10544 {
10557 }
10560 }
10562 /* Validate a command-line -march option. Parse the arch and extensions
10563 (if any) specified in STR and throw errors if appropriate. Put the
10564 results, if they are valid, in RES and ISA_FLAGS. Return whether the
10565 option is valid. */
10567 static bool
10570 {
10571 enum aarch64_parse_opt_result parse_res
10578 {
10591 }
10594 }
10596 /* Validate a command-line -mtune option. Parse the cpu
10597 specified in STR and throw errors if appropriate. Put the
10598 result, if it is valid, in RES. Return whether the option is
10599 valid. */
10601 static bool
10603 {
10604 enum aarch64_parse_opt_result parse_res
10611 {
10621 }
10623 }
10625 /* Return the CPU corresponding to the enum CPU.
10626 If it doesn't specify a cpu, return the default. */
10630 {
10634 /* The & 0x3f is to extract the bottom 6 bits that encode the
10635 default cpu as selected by the --with-cpu GCC configure option
10636 in config.gcc.
10637 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
10638 flags mechanism should be reworked to make it more sane. */
10640 }
10642 /* Return the architecture corresponding to the enum ARCH.
10643 If it doesn't specify a valid architecture, return the default. */
10647 {
10654 }
10656 /* Return the VG value associated with -msve-vector-bits= value VALUE. */
10658 static poly_uint16
10660 {
10661 /* For now generate vector-length agnostic code for -msve-vector-bits=128.
10662 This ensures we can clearly distinguish SVE and Advanced SIMD modes when
10663 deciding which .md file patterns to use and when deciding whether
10664 something is a legitimate address or constant. */
10667 else
10669 }
10671 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
10672 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
10673 tuning structs. In particular it must set selected_tune and
10674 aarch64_isa_flags that define the available ISA features and tuning
10675 decisions. It must also set selected_arch as this will be used to
10676 output the .arch asm tags for each function. */
10678 static void
10680 {
10693 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
10694 If either of -march or -mtune is given, they override their
10695 respective component of -mcpu. */
10707 /* If the user did not specify a processor, choose the default
10708 one for them. This will be the CPU set during configuration using
10709 --with-cpu, otherwise it is "generic". */
10711 {
10713 {
10717 }
10718 else
10719 {
10720 /* Get default configure-time CPU. */
10723 }
10727 }
10728 /* If both -mcpu and -march are specified check that they are architecturally
10729 compatible, warn if they're not and prefer the -march ISA flags. */
10731 {
10733 {
10737 }
10742 }
10743 else
10744 {
10745 /* -mcpu but no -march. */
10752 }
10754 /* Set the arch as well as we will need it when outputing
10755 the .arch directive in assembly. */
10757 {
10760 }
10765 #ifndef HAVE_AS_MABI_OPTION
10766 /* The compiler may have been configured with 2.23.* binutils, which does
10767 not have support for ILP32. */
10770 #endif
10772 /* Convert -msve-vector-bits to a VG count. */
10778 /* Make sure we properly set up the explicit options. */
10789 /* Save these options as the default ones in case we push and pop them later
10790 while processing functions with potential target attributes. */
10791 target_option_default_node = target_option_current_node
10793 }
10795 /* Implement targetm.override_options_after_change. */
10797 static void
10799 {
10801 }
10805 {
10809 }
10811 void
10813 {
10815 }
10817 /* A checking mechanism for the implementation of the various code models. */
10818 static void
10820 {
10822 {
10824 {
10829 #ifdef HAVE_AS_SMALL_PIC_RELOCS
10831 ? AARCH64_CMODEL_SMALL_PIC
10833 #else
10835 #endif
10843 }
10844 }
10845 else
10847 }
10849 /* Implement TARGET_OPTION_SAVE. */
10851 static void
10853 {
10855 }
10857 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
10858 using the information saved in PTR. */
10860 static void
10862 {
10870 }
10872 /* Implement TARGET_OPTION_PRINT. */
10874 static void
10876 {
10887 }
10891 void
10893 {
10895 }
10897 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
10898 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
10899 make sure optab availability predicates are recomputed when necessary. */
10901 void
10903 {
10908 else
10910 }
10912 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
10913 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
10914 of the function, if such exists. This function may be called multiple
10915 times on a single function so use aarch64_previous_fndecl to avoid
10916 setting up identical state. */
10918 static void
10920 {
10924 tree old_tree = (aarch64_previous_fndecl
10930 /* If current function has no attributes but the previous one did,
10931 use the default node. */
10935 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
10936 the default have been handled by aarch64_save_restore_target_globals from
10937 aarch64_pragma_target_parse. */
10943 /* First set the target options. */
10947 }
10949 /* Enum describing the various ways we can handle attributes.
10950 In many cases we can reuse the generic option handling machinery. */
10952 enum aarch64_attr_opt_type
10953 {
10957 aarch64_attr_custom /* Attribute requires a custom handling function. */
10958 };
10960 /* All the information needed to handle a target attribute.
10961 NAME is the name of the attribute.
10962 ATTR_TYPE specifies the type of behavior of the attribute as described
10963 in the definition of enum aarch64_attr_opt_type.
10964 ALLOW_NEG is true if the attribute supports a "no-" form.
10965 HANDLER is the function that takes the attribute string as an argument
10966 It is needed only when the ATTR_TYPE is aarch64_attr_custom.
10967 OPT_NUM is the enum specifying the option that the attribute modifies.
10968 This is needed for attributes that mirror the behavior of a command-line
10969 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
10970 aarch64_attr_enum. */
10972 struct aarch64_attribute_info
10973 {
10979 };
10981 /* Handle the ARCH_STR argument to the arch= target attribute. */
10983 static bool
10985 {
10987 enum aarch64_parse_opt_result parse_res
10991 {
10996 }
10999 {
11012 }
11015 }
11017 /* Handle the argument CPU_STR to the cpu= target attribute. */
11019 static bool
11021 {
11023 enum aarch64_parse_opt_result parse_res
11027 {
11035 }
11038 {
11051 }
11054 }
11056 /* Handle the argument STR to the tune= target attribute. */
11058 static bool
11060 {
11062 enum aarch64_parse_opt_result parse_res
11066 {
11071 }
11074 {
11081 }
11084 }
11086 /* Parse an architecture extensions target attribute string specified in STR.
11087 For example "+fp+nosimd". Show any errors if needed. Return TRUE
11088 if successful. Update aarch64_isa_flags to reflect the ISA features
11089 modified. */
11091 static bool
11093 {
11097 /* We allow "+nothing" in the beginning to clear out all architectural
11098 features if the user wants to handpick specific features. */
11100 {
11103 }
11108 {
11111 }
11114 {
11125 }
11128 }
11130 /* The target attributes that we support. On top of these we also support just
11131 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
11132 handled explicitly in aarch64_process_one_target_attr. */
11135 {
11137 OPT_mgeneral_regs_only },
11139 OPT_mfix_cortex_a53_835769 },
11141 OPT_mfix_cortex_a53_843419 },
11145 OPT_momit_leaf_frame_pointer },
11148 OPT_march_ },
11151 OPT_mtune_ },
11153 OPT_msign_return_address_ },
11155 };
11157 /* Parse ARG_STR which contains the definition of one target attribute.
11158 Show appropriate errors if any or return true if the attribute is valid. */
11160 static bool
11162 {
11168 {
11171 }
11176 /* Skip leading whitespace. */
11178 str_to_check++;
11180 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
11181 It is easier to detect and handle it explicitly here rather than going
11182 through the machinery for the rest of the target attributes in this
11183 function. */
11188 {
11191 }
11194 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
11195 and point ARG to "foo". */
11197 {
11199 arg++;
11200 }
11204 {
11205 /* If the names don't match up, or the user has given an argument
11206 to an attribute that doesn't accept one, or didn't give an argument
11207 to an attribute that expects one, fail to match. */
11216 {
11219 }
11221 /* If the name matches but the attribute does not allow "no-" versions
11222 then we can't match. */
11224 {
11227 }
11230 {
11231 /* Has a custom handler registered.
11232 For example, cpu=, arch=, tune=. */
11239 /* Either set or unset a boolean option. */
11241 {
11249 }
11250 /* Set or unset a bit in the target_flags. aarch64_handle_option
11251 should know what mask to apply given the option number. */
11253 {
11255 /* We only need to specify the option number.
11256 aarch64_handle_option will know which mask to apply. */
11262 }
11263 /* Use the option setting machinery to set an option to an enum. */
11265 {
11272 {
11275 global_dc);
11276 }
11277 else
11278 {
11280 }
11282 }
11285 }
11286 }
11288 /* If we reached here we either have found an attribute and validated
11289 it or didn't match any. If we matched an attribute but its arguments
11290 were malformed we will have returned false already. */
11292 }
11294 /* Count how many times the character C appears in
11295 NULL-terminated string STR. */
11297 static unsigned int
11299 {
11302 {
11304 res++;
11306 str++;
11307 }
11310 }
11312 /* Parse the tree in ARGS that contains the target attribute information
11313 and update the global target options space. */
11315 bool
11317 {
11319 {
11320 do
11321 {
11324 {
11327 }
11332 }
11335 {
11338 }
11345 {
11348 }
11350 /* Used to catch empty spaces between commas i.e.
11351 attribute ((target ("attr1,,attr2"))). */
11354 /* Handle multiple target attributes separated by ','. */
11359 {
11360 num_attrs++;
11362 {
11365 }
11368 }
11371 {
11374 }
11377 }
11379 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
11380 process attribute ((target ("..."))). */
11382 static bool
11384 {
11387 tree old_optimize;
11391 /* If what we're processing is the current pragma string then the
11392 target option node is already stored in target_option_current_node
11393 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
11394 having to re-parse the string. This is especially useful to keep
11395 arm_neon.h compile times down since that header contains a lot
11396 of intrinsics enclosed in pragmas. */
11398 {
11401 }
11407 /* If the function changed the optimization levels as well as setting
11408 target options, start with the optimizations specified. */
11413 /* Save the current target options to restore at the end. */
11416 /* If fndecl already has some target attributes applied to it, unpack
11417 them so that we add this attribute on top of them, rather than
11418 overwriting them. */
11420 {
11426 }
11427 else
11433 /* Set up any additional state. */
11435 {
11437 /* Initialize SIMD builtins if we haven't already.
11438 Set current_target_pragma to NULL for the duration so that
11439 the builtin initialization code doesn't try to tag the functions
11440 being built with the attributes specified by any current pragma, thus
11441 going into an infinite recursion. */
11443 {
11448 }
11450 }
11451 else
11457 {
11462 }
11470 }
11472 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
11473 tri-bool options (yes, no, don't care) and the default value is
11474 DEF, determine whether to reject inlining. */
11476 static bool
11479 {
11480 /* If the callee doesn't care, always allow inlining. */
11484 /* If the caller doesn't care, always allow inlining. */
11488 /* Otherwise, allow inlining if either the callee and caller values
11489 agree, or if the callee is using the default value. */
11491 }
11493 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
11494 to inline CALLEE into CALLER based on target-specific info.
11495 Make sure that the caller and callee have compatible architectural
11496 features. Then go through the other possible target attributes
11497 and see if they can block inlining. Try not to reject always_inline
11498 callees unless they are incompatible architecturally. */
11500 static bool
11502 {
11506 /* If callee has no option attributes, then it is ok to inline. */
11517 /* Callee's ISA flags should be a subset of the caller's. */
11522 /* Allow non-strict aligned functions inlining into strict
11523 aligned ones. */
11533 /* If the architectural features match up and the callee is always_inline
11534 then the other attributes don't matter. */
11546 /* Honour explicit requests to workaround errata. */
11559 /* If the user explicitly specified -momit-leaf-frame-pointer for the
11560 caller and calle and they don't match up, reject inlining. */
11567 /* If the callee has specific tuning overrides, respect them. */
11572 /* If the user specified tuning override strings for the
11573 caller and callee and they don't match up, reject inlining.
11574 We just do a string compare here, we don't analyze the meaning
11575 of the string, as it would be too costly for little gain. */
11583 }
11585 /* Return true if SYMBOL_REF X binds locally. */
11587 static bool
11589 {
11593 }
11595 /* Return true if SYMBOL_REF X is thread local */
11596 static bool
11598 {
11606 }
11608 /* Classify a TLS symbol into one of the TLS kinds. */
11609 enum aarch64_symbol_type
11611 {
11615 {
11622 {
11628 }
11639 else
11648 }
11649 }
11651 /* Return the correct method for accessing X + OFFSET, where X is either
11652 a SYMBOL_REF or LABEL_REF. */
11654 enum aarch64_symbol_type
11656 {
11658 {
11660 {
11675 }
11676 }
11679 {
11684 {
11686 /* When we retrieve symbol + offset address, we have to make sure
11687 the offset does not cause overflow of the final address. But
11688 we have no way of knowing the address of symbol at compile time
11689 so we can't accurately say if the distance between the PC and
11690 symbol + offset is outside the addressible range of +/-1M in the
11691 TINY code model. So we rely on images not being greater than
11692 1M and cap the offset at 1M and anything beyond 1M will have to
11693 be loaded using an alternative mechanism. Furthermore if the
11694 symbol is a weak reference to something that isn't known to
11695 resolve to a symbol in this module, then force to memory. */
11703 /* Same reasoning as the tiny code model, but the offset cap here is
11704 4G. */
11725 /* This is alright even in PIC code as the constant
11726 pool reference is always PC relative and within
11727 the same translation unit. */
11730 else
11735 }
11736 }
11738 /* By default push everything into the constant pool. */
11740 }
11742 bool
11744 {
11746 }
11748 bool
11750 {
11758 }
11760 /* Implement TARGET_LEGITIMATE_CONSTANT_P hook. Return true for constants
11761 that should be rematerialized rather than spilled. */
11763 static bool
11765 {
11766 /* Support CSE and rematerialization of common constants. */
11772 /* Do not allow vector struct mode constants for Advanced SIMD.
11773 We could support 0 and -1 easily, but they need support in
11774 aarch64-simd.md. */
11779 /* Only accept variable-length vector constants if they can be
11780 handled directly.
11782 ??? It would be possible to handle rematerialization of other
11783 constants via secondary reloads. */
11790 /* Accept polynomial constants that can be calculated by using the
11791 destination of a move as the sole temporary. Constants that
11792 require a second temporary cannot be rematerialized (they can't be
11793 forced to memory and also aren't legitimate constants). */
11794 poly_int64 offset;
11798 /* If an offset is being added to something else, we need to allow the
11799 base to be moved into the destination register, meaning that there
11800 are no free temporaries for the offset. */
11805 /* Do not allow const (plus (anchor_symbol, const_int)). */
11809 /* Treat symbols as constants. Avoid TLS symbols as they are complex,
11810 so spilling them is better than rematerialization. */
11814 /* Label references are always constant. */
11819 }
11821 rtx
11823 {
11829 /* Can return in any reg. */
11832 }
11834 /* On AAPCS systems, this is the "struct __va_list". */
11837 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
11838 Return the type to use as __builtin_va_list.
11840 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
11842 struct __va_list
11843 {
11844 void *__stack;
11845 void *__gr_top;
11846 void *__vr_top;
11847 int __gr_offs;
11848 int __vr_offs;
11849 }; */
11851 static tree
11853 {
11854 tree va_list_name;
11857 /* Create the type. */
11859 /* Give it the required name. */
11861 TYPE_DECL,
11863 va_list_type);
11868 /* Create the fields. */
11871 ptr_type_node);
11874 ptr_type_node);
11877 ptr_type_node);
11880 integer_type_node);
11883 integer_type_node);
11885 /* Tell tree-stdarg pass about our internal offset fields.
11886 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
11887 purpose to identify whether the code is updating va_list internal
11888 offset fields through irregular way. */
11910 /* Compute its layout. */
11914 }
11916 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
11917 static void
11919 {
11923 tree t;
11937 {
11940 }
11949 NULL_TREE);
11951 NULL_TREE);
11953 NULL_TREE);
11955 NULL_TREE);
11957 NULL_TREE);
11959 /* Emit code to initialize STACK, which points to the next varargs stack
11960 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
11961 by named arguments. STACK is 8-byte aligned. */
11968 /* Emit code to initialize GRTOP, the top of the GR save area.
11969 virtual_incoming_args_rtx should have been 16 byte aligned. */
11974 /* Emit code to initialize VRTOP, the top of the VR save area.
11975 This address is gr_save_area_bytes below GRTOP, rounded
11976 down to the next 16-byte boundary. */
11986 /* Emit code to initialize GROFF, the offset from GRTOP of the
11987 next GPR argument. */
11992 /* Likewise emit code to initialize VROFF, the offset from FTOP
11993 of the next VR argument. */
11997 }
11999 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
12001 static tree
12004 {
12005 tree addr;
12011 machine_mode mode;
12038 type,
12042 {
12043 /* No frontends can create types with variable-sized modes, so we
12044 shouldn't be asked to pass or return them. */
12047 /* TYPE passed in fp/simd registers. */
12059 {
12062 }
12065 {
12067 }
12068 }
12069 else
12070 {
12071 /* TYPE passed in general registers. */
12084 {
12086 }
12087 }
12089 /* Get a local temporary for the field value. */
12092 /* Emit code to branch if off >= 0. */
12098 {
12099 /* Emit: offs = (offs + 15) & -16. */
12105 }
12106 else
12109 /* Update ap.__[g|v]r_offs */
12114 /* String up. */
12118 /* [cond2] if (ap.__[g|v]r_offs > 0) */
12123 /* String up: make sure the assignment happens before the use. */
12127 /* Prepare the trees handling the argument that is passed on the stack;
12128 the top level node will store in ON_STACK. */
12131 {
12132 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
12140 }
12141 else
12143 /* Advance ap.__stack */
12151 /* String up roundup and advance. */
12154 /* String up with arg */
12156 /* Big-endianness related address adjustment. */
12159 {
12163 }
12168 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
12178 {
12179 /* type ha; // treat as "struct {ftype field[n];}"
12180 ... [computing offs]
12181 for (i = 0; i <nregs; ++i, offs += 16)
12182 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
12183 return ha; */
12187 /* Declare a local variable. */
12191 /* Establish the base type. */
12193 {
12212 {
12216 }
12220 }
12222 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
12230 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
12232 {
12242 }
12246 }
12256 }
12258 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
12260 static void
12264 {
12266 CUMULATIVE_ARGS local_cum;
12270 /* The caller has advanced CUM up to, but not beyond, the last named
12271 argument. Advance a local copy of CUM past the last "real" named
12272 argument, to find out how many registers are left over. */
12276 /* Found out how many registers we need to save.
12277 Honor tree-stdvar analysis results. */
12286 {
12289 }
12292 {
12294 {
12297 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
12305 }
12307 {
12308 /* We can't use move_block_from_reg, because it will use
12309 the wrong mode, storing D regs only. */
12313 /* Set OFF to the offset from virtual_incoming_args_rtx of
12314 the first vector register. The VR save area lies below
12315 the GR one, and is aligned to 16 bytes. */
12322 {
12330 }
12331 }
12332 }
12334 /* We don't save the size into *PRETEND_SIZE because we want to avoid
12335 any complication of having crtl->args.pretend_args_size changed. */
12340 }
12342 static void
12344 {
12347 {
12349 {
12352 }
12353 }
12356 {
12359 }
12360 }
12362 /* Walk down the type tree of TYPE counting consecutive base elements.
12363 If *MODEP is VOIDmode, then set it to the first valid floating point
12364 type. If a non-floating point type is found, or if a floating point
12365 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
12366 otherwise return the count in the sub-tree. */
12367 static int
12369 {
12370 machine_mode mode;
12371 HOST_WIDE_INT size;
12374 {
12404 /* Use V2SImode and V4SImode as representatives of all 64-bit
12405 and 128-bit vector types. */
12408 {
12417 }
12422 /* Vector modes are considered to be opaque: two vectors are
12423 equivalent for the purposes of being homogeneous aggregates
12424 if they are the same size. */
12431 {
12435 /* Can't handle incomplete types nor sizes that are not
12436 fixed. */
12443 || !index
12454 /* There must be no padding. */
12460 }
12463 {
12466 tree field;
12468 /* Can't handle incomplete types nor sizes that are not
12469 fixed. */
12475 {
12483 }
12485 /* There must be no padding. */
12491 }
12495 {
12496 /* These aren't very interesting except in a degenerate case. */
12499 tree field;
12501 /* Can't handle incomplete types nor sizes that are not
12502 fixed. */
12508 {
12516 }
12518 /* There must be no padding. */
12524 }
12528 }
12531 }
12533 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
12534 type as described in AAPCS64 \S 4.1.2.
12536 See the comment above aarch64_composite_type_p for the notes on MODE. */
12538 static bool
12540 machine_mode mode)
12541 {
12551 }
12553 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
12554 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
12555 array types. The C99 floating-point complex types are also considered
12556 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
12557 types, which are GCC extensions and out of the scope of AAPCS64, are
12558 treated as composite types here as well.
12560 Note that MODE itself is not sufficient in determining whether a type
12561 is such a composite type or not. This is because
12562 stor-layout.c:compute_record_mode may have already changed the MODE
12563 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
12564 structure with only one field may have its MODE set to the mode of the
12565 field. Also an integer mode whose size matches the size of the
12566 RECORD_TYPE type may be used to substitute the original mode
12567 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
12568 solely relied on. */
12570 static bool
12572 machine_mode mode)
12573 {
12586 }
12588 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
12589 shall be passed or returned in simd/fp register(s) (providing these
12590 parameter passing registers are available).
12592 Upon successful return, *COUNT returns the number of needed registers,
12593 *BASE_MODE returns the mode of the individual register and when IS_HAF
12594 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
12595 floating-point aggregate or a homogeneous short-vector aggregate. */
12597 static bool
12599 const_tree type,
12603 {
12611 {
12614 }
12616 {
12620 }
12622 {
12626 {
12629 }
12630 else
12632 }
12633 else
12638 }
12640 /* Implement TARGET_STRUCT_VALUE_RTX. */
12642 static rtx
12645 {
12647 }
12649 /* Implements target hook vector_mode_supported_p. */
12650 static bool
12652 {
12655 }
12657 /* Return appropriate SIMD container
12658 for MODE within a vector of WIDTH bits. */
12659 static machine_mode
12661 {
12664 {
12681 }
12685 {
12688 {
12705 }
12706 else
12708 {
12721 }
12722 }
12724 }
12726 /* Return 128-bit container as the preferred SIMD mode for MODE. */
12727 static machine_mode
12729 {
12732 }
12734 /* Return a list of possible vector sizes for the vectorizer
12735 to iterate over. */
12736 static void
12738 {
12743 }
12745 /* Implement TARGET_MANGLE_TYPE. */
12749 {
12750 /* The AArch64 ABI documents say that "__va_list" has to be
12751 managled as if it is in the "std" namespace. */
12755 /* Half-precision float. */
12759 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
12760 builtin types. */
12764 /* Use the default mangling. */
12766 }
12768 /* Find the first rtx_insn before insn that will generate an assembly
12769 instruction. */
12773 {
12777 do
12778 {
12780 }
12784 }
12786 static bool
12788 {
12790 /* A number of these may be AArch32 only. */
12795 };
12798 {
12801 }
12804 }
12806 /* Check if there is a register dependency between a load and the insn
12807 for which we hold recog_data. */
12809 static bool
12811 {
12812 rtx load_reg;
12822 {
12828 }
12830 }
12833 /* When working around the Cortex-A53 erratum 835769,
12834 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
12835 instruction and has a preceding memory instruction such that a NOP
12836 should be inserted between them. */
12838 bool
12840 {
12843 rtx body;
12856 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
12857 Restore recog state to INSN to avoid state corruption. */
12865 /* If the previous insn is a memory op and there is no dependency between
12866 it and the DImode madd, emit a NOP between them. If body is NULL then we
12867 have a complex memory operation, probably a load/store pair.
12868 Be conservative for now and emit a NOP. */
12875 }
12878 /* Implement FINAL_PRESCAN_INSN. */
12880 void
12882 {
12885 }
12888 /* Return true if BASE_OR_STEP is a valid immediate operand for an SVE INDEX
12889 instruction. */
12891 bool
12893 {
12896 }
12898 /* Return true if X is a valid immediate for the SVE ADD and SUB
12899 instructions. Negate X first if NEGATE_P is true. */
12901 bool
12903 {
12904 rtx elt;
12918 }
12920 /* Return true if X is a valid immediate operand for an SVE logical
12921 instruction such as AND. */
12923 bool
12925 {
12926 rtx elt;
12932 }
12934 /* Return true if X is a valid immediate for the SVE DUP and CPY
12935 instructions. */
12937 bool
12939 {
12940 rtx elt;
12950 }
12952 /* Return true if X is a valid immediate operand for an SVE CMP instruction.
12953 SIGNED_P says whether the operand is signed rather than unsigned. */
12955 bool
12957 {
12958 rtx elt;
12962 && (signed_p
12965 }
12967 /* Return true if X is a valid immediate operand for an SVE FADD or FSUB
12968 instruction. Negate X first if NEGATE_P is true. */
12970 bool
12972 {
12973 rtx elt;
12974 REAL_VALUE_TYPE r;
12990 }
12992 /* Return true if X is a valid immediate operand for an SVE FMUL
12993 instruction. */
12995 bool
12997 {
12998 rtx elt;
13000 /* GCC will never generate a multiply with an immediate of 2, so there is no
13001 point testing for it (even though it is a valid constant). */
13005 }
13007 /* Return true if replicating VAL32 is a valid 2-byte or 4-byte immediate
13008 for the Advanced SIMD operation described by WHICH and INSN. If INFO
13009 is nonnull, use it to describe valid immediates. */
13010 static bool
13015 {
13016 /* Try a 4-byte immediate with LSL. */
13019 {
13024 }
13026 /* Try a 2-byte immediate with LSL. */
13031 {
13036 }
13038 /* Try a 4-byte immediate with MSL, except for cases that MVN
13039 can handle. */
13042 {
13045 {
13050 }
13051 }
13054 }
13056 /* Return true if replicating VAL64 is a valid immediate for the
13057 Advanced SIMD operation described by WHICH. If INFO is nonnull,
13058 use it to describe valid immediates. */
13059 static bool
13063 {
13069 {
13080 /* Try using a replicated byte. */
13084 {
13088 }
13089 }
13091 /* Try using a bit-to-bytemask. */
13093 {
13096 {
13100 }
13102 {
13106 }
13107 }
13109 }
13111 /* Return true if replicating VAL64 gives a valid immediate for an SVE MOV
13112 instruction. If INFO is nonnull, use it to describe valid immediates. */
13114 static bool
13117 {
13121 {
13125 {
13130 }
13131 }
13134 {
13135 /* DUP with no shift. */
13139 }
13141 {
13142 /* DUP with LSL #8. */
13146 }
13148 {
13149 /* DUPM. */
13153 }
13155 }
13157 /* Return true if OP is a valid SIMD immediate for the operation
13158 described by WHICH. If INFO is nonnull, use it to describe valid
13159 immediates. */
13160 bool
13163 {
13177 {
13186 }
13190 else
13193 /* Handle PFALSE and PTRUE. */
13198 scalar_float_mode elt_float_mode;
13201 {
13205 {
13209 }
13210 }
13218 /* Expand the vector constant out into a byte vector, with the least
13219 significant byte of the register first. */
13223 {
13224 /* The vector is provided in gcc endian-neutral fashion.
13225 For aarch64_be Advanced SIMD, it must be laid out in the vector
13226 register in reverse order. */
13238 {
13241 }
13242 }
13244 /* The immediate must repeat every eight bytes. */
13250 /* Get the repeating 8-byte value as an integer. No endian correction
13251 is needed here because bytes is already in lsb-first order. */
13259 else
13261 }
13263 /* Check whether X is a VEC_SERIES-like constant that starts at 0 and
13264 has a step in the range of INDEX. Return the index expression if so,
13265 otherwise return null. */
13266 rtx
13268 {
13275 }
13277 /* Check of immediate shift constants are within range. */
13278 bool
13280 {
13284 else
13286 }
13288 /* Return the bitmask CONST_INT to select the bits required by a zero extract
13289 operation of width WIDTH at bit position POS. */
13291 rtx
13293 {
13297 unsigned HOST_WIDE_INT mask
13300 }
13302 bool
13304 {
13323 }
13325 /* Return a const_int vector of VAL. */
13326 rtx
13328 {
13331 }
13333 /* Check OP is a legal scalar immediate for the MOVI instruction. */
13335 bool
13337 {
13338 machine_mode vmode;
13343 }
13345 /* Construct and return a PARALLEL RTX vector with elements numbering the
13346 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
13347 the vector - from the perspective of the architecture. This does not
13348 line up with GCC's perspective on lane numbers, so we end up with
13349 different masks depending on our target endian-ness. The diagram
13350 below may help. We must draw the distinction when building masks
13351 which select one half of the vector. An instruction selecting
13352 architectural low-lanes for a big-endian target, must be described using
13353 a mask selecting GCC high-lanes.
13355 Big-Endian Little-Endian
13357 GCC 0 1 2 3 3 2 1 0
13358 | x | x | x | x | | x | x | x | x |
13359 Architecture 3 2 1 0 3 2 1 0
13361 Low Mask: { 2, 3 } { 0, 1 }
13362 High Mask: { 0, 1 } { 2, 3 }
13364 MODE Is the mode of the vector and NUNITS is the number of units in it. */
13366 rtx
13368 {
13373 rtx t1;
13378 else
13386 }
13388 /* Check OP for validity as a PARALLEL RTX vector with elements
13389 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
13390 from the perspective of the architecture. See the diagram above
13391 aarch64_simd_vect_par_cnst_half for more details. */
13393 bool
13396 {
13410 {
13417 }
13419 }
13421 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
13422 HIGH (exclusive). */
13423 void
13425 const_tree exp)
13426 {
13427 HOST_WIDE_INT lane;
13432 {
13435 else
13437 }
13438 }
13440 /* Peform endian correction on lane number N, which indexes a vector
13441 of mode MODE, and return the result as an SImode rtx. */
13443 rtx
13445 {
13447 }
13449 /* Return TRUE if OP is a valid vector addressing mode. */
13451 bool
13453 {
13456 }
13458 /* Return true if OP is a valid MEM operand for an SVE LD1R instruction. */
13460 bool
13462 {
13464 scalar_mode mode;
13471 }
13473 /* Return true if OP is a valid MEM operand for an SVE LDR instruction.
13474 The conditions for STR are the same. */
13475 bool
13477 {
13484 }
13486 /* Return true if OP is a valid MEM operand for an SVE_STRUCT mode.
13487 We need to be able to access the individual pieces, so the range
13488 is different from LD[234] and ST[234]. */
13489 bool
13491 {
13498 ADDR_QUERY_ANY)
13506 }
13508 /* Emit a register copy from operand to operand, taking care not to
13509 early-clobber source registers in the process.
13511 COUNT is the number of components into which the copy needs to be
13512 decomposed. */
13513 void
13516 {
13526 else
13530 }
13532 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
13533 one of VSTRUCT modes: OI, CI, or XI. */
13534 int
13536 {
13537 /* This is only used (and only meaningful) for Advanced SIMD, not SVE. */
13539 }
13541 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
13542 alignment of a vector to 128 bits. SVE predicates have an alignment of
13543 16 bits. */
13544 static HOST_WIDE_INT
13546 {
13548 /* ??? Checking the mode isn't ideal, but VECTOR_BOOLEAN_TYPE_P can
13549 be set for non-predicate vectors of booleans. Modes are the most
13550 direct way we have of identifying real SVE predicate types. */
13554 }
13556 /* Implement target hook TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT. */
13557 static HOST_WIDE_INT
13559 {
13561 {
13562 /* If the length of the vector is fixed, try to align to that length,
13563 otherwise don't try to align at all. */
13564 HOST_WIDE_INT result;
13568 }
13570 }
13572 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
13573 static bool
13575 {
13579 /* For fixed-length vectors, check that the vectorizer will aim for
13580 full-vector alignment. This isn't true for generic GCC vectors
13581 that are wider than the ABI maximum of 128 bits. */
13587 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
13589 }
13591 /* Return true if the vector misalignment factor is supported by the
13592 target. */
13593 static bool
13597 {
13599 {
13600 /* Return if movmisalign pattern is not supported for this mode. */
13604 /* Misalignment factor is unknown at compile time. */
13607 }
13609 is_packed);
13610 }
13612 /* If VALS is a vector constant that can be loaded into a register
13613 using DUP, generate instructions to do so and return an RTX to
13614 assign to the register. Otherwise return NULL_RTX. */
13615 static rtx
13617 {
13620 rtx x;
13625 /* We can load this constant by using DUP and a constant in a
13626 single ARM register. This will be cheaper than a vector
13627 load. */
13630 }
13633 /* Generate code to load VALS, which is a PARALLEL containing only
13634 constants (for vec_init) or CONST_VECTOR, efficiently into a
13635 register. Returns an RTX to copy into the register, or NULL_RTX
13636 for a PARALLEL that can not be converted into a CONST_VECTOR. */
13637 static rtx
13639 {
13641 rtx const_dup;
13649 {
13650 /* A CONST_VECTOR must contain only CONST_INTs and
13651 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
13652 Only store valid constants in a CONST_VECTOR. */
13655 {
13658 n_const++;
13659 }
13662 }
13663 else
13668 /* Load using MOVI/MVNI. */
13671 /* Loaded using DUP. */
13674 /* Load from constant pool. We can not take advantage of single-cycle
13675 LD1 because we need a PC-relative addressing mode. */
13677 else
13678 /* A PARALLEL containing something not valid inside CONST_VECTOR.
13679 We can not construct an initializer. */
13681 }
13683 /* Expand a vector initialisation sequence, such that TARGET is
13684 initialised to contain VALS. */
13686 void
13688 {
13691 /* The number of vector elements. */
13693 /* The number of vector elements which are not constant. */
13696 /* The first element of vals. */
13700 /* Count the number of variable elements to initialise. */
13702 {
13706 else
13710 }
13712 /* No variable elements, hand off to aarch64_simd_make_constant which knows
13713 how best to handle this. */
13715 {
13718 {
13721 }
13722 }
13724 /* Splat a single non-constant element if we can. */
13726 {
13730 }
13735 /* If there are only variable elements, try to optimize
13736 the insertion using dup for the most common element
13737 followed by insertions. */
13739 /* The algorithm will fill matches[*][0] with the earliest matching element,
13740 and matches[X][1] with the count of duplicate elements (if X is the
13741 earliest element which has duplicates). */
13744 {
13747 {
13749 {
13751 {
13755 }
13756 }
13757 }
13762 {
13765 }
13767 /* Create a duplicate of the most common element. */
13771 /* Insert the rest. */
13773 {
13779 }
13781 }
13783 /* Initialise a vector which is part-variable. We want to first try
13784 to build those lanes which are constant in the most efficient way we
13785 can. */
13787 {
13790 /* Load constant part of vector. We really don't care what goes into the
13791 parts we will overwrite, but we're more likely to be able to load the
13792 constant efficiently if it has fewer, larger, repeating parts
13793 (see aarch64_simd_valid_immediate). */
13795 {
13801 {
13802 /* Look in the copied vector, as more elements are const. */
13805 {
13808 }
13809 }
13811 }
13813 }
13815 /* Insert the variable lanes directly. */
13817 {
13823 }
13824 }
13826 static unsigned HOST_WIDE_INT
13828 {
13832 }
13834 /* Select a format to encode pointers in exception handling data. */
13835 int
13837 {
13840 {
13846 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
13847 for everything. */
13851 /* No assumptions here. 8-byte relocs required. */
13854 }
13856 }
13858 /* The last .arch and .tune assembly strings that we printed. */
13862 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
13863 by the function fndecl. */
13865 void
13867 tree fndecl)
13868 {
13874 else
13885 /* Only update the assembler .arch string if it is distinct from the last
13886 such string we printed. */
13889 {
13892 }
13894 /* Print the cpu name we're tuning for in the comments, might be
13895 useful to readers of the generated asm. Do it only when it changes
13896 from function to function and verbose assembly is requested. */
13901 {
13905 }
13907 /* Don't forget the type directive for ELF. */
13910 }
13912 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
13914 static void
13916 {
13933 }
13935 /* Emit load exclusive. */
13937 static void
13940 {
13944 {
13951 }
13954 }
13956 /* Emit store exclusive. */
13958 static void
13961 {
13965 {
13972 }
13975 }
13977 /* Mark the previous jump instruction as unlikely. */
13979 static void
13981 {
13984 }
13986 /* Expand a compare and swap pattern. */
13988 void
13990 {
13995 gen_cas_fn gen;
13997 {
13998 gen_aarch64_compare_and_swapqi,
13999 gen_aarch64_compare_and_swaphi,
14000 gen_aarch64_compare_and_swapsi,
14001 gen_aarch64_compare_and_swapdi
14002 };
14004 {
14005 gen_aarch64_compare_and_swapqi_lse,
14006 gen_aarch64_compare_and_swaphi_lse,
14007 gen_aarch64_compare_and_swapsi_lse,
14008 gen_aarch64_compare_and_swapdi_lse
14009 };
14022 /* Normally the succ memory model must be stronger than fail, but in the
14023 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
14024 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
14031 {
14034 /* For short modes, we're going to perform the comparison in SImode,
14035 so do the zero-extension now. */
14039 /* Fall through. */
14043 /* Force the value into a register if needed. */
14050 }
14053 {
14060 }
14063 else
14074 }
14076 /* Test whether the target supports using a atomic load-operate instruction.
14077 CODE is the operation and AFTER is TRUE if the data in memory after the
14078 operation should be returned and FALSE if the data before the operation
14079 should be returned. Returns FALSE if the operation isn't supported by the
14080 architecture. */
14082 bool
14084 {
14089 {
14099 }
14100 }
14102 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
14103 sequence implementing an atomic operation. */
14105 static void
14107 {
14114 {
14116 }
14117 }
14119 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
14120 for the data in memory. EXPECTED is the value expected to be in memory.
14121 DESIRED is the value to store to memory. MEM is the memory location. MODEL
14122 is the memory ordering to use. */
14124 void
14127 rtx model)
14128 {
14130 machine_mode mode;
14135 {
14142 }
14144 /* Move the expected value into the CAS destination register. */
14147 /* Emit the CAS. */
14150 /* Compare the expected value with the value loaded by the CAS, to establish
14151 whether the swap was made. */
14153 }
14155 /* Split a compare and swap pattern. */
14157 void
14159 {
14161 machine_mode mode;
14166 rtx model_rtx;
14178 /* When OLDVAL is zero and we want the strong version we can emit a tighter
14179 loop:
14180 .label1:
14181 LD[A]XR rval, [mem]
14182 CBNZ rval, .label2
14183 ST[L]XR scratch, newval, [mem]
14184 CBNZ scratch, .label1
14185 .label2:
14186 CMP rval, 0. */
14191 {
14194 }
14197 /* The initial load can be relaxed for a __sync operation since a final
14198 barrier will be emitted to stop code hoisting. */
14202 else
14206 {
14211 }
14212 else
14213 {
14219 }
14224 {
14229 }
14230 else
14231 {
14235 }
14238 /* If we used a CBNZ in the exchange loop emit an explicit compare with RVAL
14239 to set the condition flags. If this is not used it will be removed by
14240 later passes. */
14242 {
14246 }
14247 /* Emit any final barrier needed for a __sync operation. */
14250 }
14252 /* Emit a BIC instruction. */
14254 static void
14256 {
14261 {
14266 }
14269 }
14271 /* Emit an atomic swap. */
14273 static void
14276 {
14280 {
14287 }
14290 }
14292 /* Operations supported by aarch64_emit_atomic_load_op. */
14294 enum aarch64_atomic_load_op_code
14295 {
14299 AARCH64_LDOP_BIC /* A & ~B */
14300 };
14302 /* Emit an atomic load-operate. */
14304 static void
14308 {
14311 {
14312 gen_aarch64_atomic_loadaddqi,
14313 gen_aarch64_atomic_loadaddhi,
14314 gen_aarch64_atomic_loadaddsi,
14315 gen_aarch64_atomic_loadadddi
14316 };
14318 {
14319 gen_aarch64_atomic_loadeorqi,
14320 gen_aarch64_atomic_loadeorhi,
14321 gen_aarch64_atomic_loadeorsi,
14322 gen_aarch64_atomic_loadeordi
14323 };
14325 {
14326 gen_aarch64_atomic_loadsetqi,
14327 gen_aarch64_atomic_loadsethi,
14328 gen_aarch64_atomic_loadsetsi,
14329 gen_aarch64_atomic_loadsetdi
14330 };
14332 {
14333 gen_aarch64_atomic_loadclrqi,
14334 gen_aarch64_atomic_loadclrhi,
14335 gen_aarch64_atomic_loadclrsi,
14336 gen_aarch64_atomic_loadclrdi
14337 };
14338 aarch64_atomic_load_op_fn gen;
14342 {
14349 }
14352 {
14359 }
14362 }
14364 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
14365 location to store the data read from memory. OUT_RESULT is the location to
14366 store the result of the operation. MEM is the memory location to read and
14367 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
14368 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
14369 be NULL. */
14371 void
14374 {
14378 aarch64_atomic_load_op_code ldop_code;
14379 rtx src;
14380 rtx x;
14388 /* Make sure the value is in a register, putting it into a destination
14389 register if it needs to be manipulated. */
14392 {
14395 }
14396 else
14400 /* Preprocess the data for the operation as necessary. If the operation is
14401 a SET then emit a swap instruction and finish. */
14403 {
14409 /* Negate the value and treat it as a PLUS. */
14410 {
14411 rtx neg_src;
14413 /* Resize the value if necessary. */
14422 }
14423 /* Fall-through. */
14437 {
14438 rtx not_src;
14440 /* Resize the value if necessary. */
14449 }
14454 /* The operation can't be done with atomic instructions. */
14456 }
14460 /* If necessary, calculate the data in memory after the update by redoing the
14461 operation from values in registers. */
14466 {
14470 }
14475 {
14491 }
14496 }
14498 /* Split an atomic operation. */
14500 void
14503 {
14509 rtx x;
14511 /* Split the atomic operation into a sequence. */
14519 else
14523 /* The initial load can be relaxed for a __sync operation since a final
14524 barrier will be emitted to stop code hoisting. */
14528 else
14532 {
14546 {
14549 }
14550 /* Fall through. */
14556 }
14566 /* Emit any final barrier needed for a __sync operation. */
14569 }
14571 static void
14573 {
14574 /* Half-precision float operations. The compiler handles all operations
14575 with NULL libfuncs by converting to SFmode. */
14577 /* Conversions. */
14581 /* Arithmetic. */
14588 /* Comparisons. */
14596 }
14598 /* Target hook for c_mode_for_suffix. */
14599 static machine_mode
14601 {
14606 }
14608 /* We can only represent floating point constants which will fit in
14609 "quarter-precision" values. These values are characterised by
14610 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
14611 by:
14613 (-1)^s * (n/16) * 2^r
14615 Where:
14616 's' is the sign bit.
14617 'n' is an integer in the range 16 <= n <= 31.
14618 'r' is an integer in the range -3 <= r <= 4. */
14620 /* Return true iff X can be represented by a quarter-precision
14621 floating point immediate operand X. Note, we cannot represent 0.0. */
14622 bool
14624 {
14625 /* This represents our current view of how many bits
14626 make up the mantissa. */
14636 /* We don't support HFmode constants yet. */
14642 /* We cannot represent infinities, NaNs or +/-zero. We won't
14643 know if we have +zero until we analyse the mantissa, but we
14644 can reject the other invalid values. */
14649 /* Extract exponent. */
14653 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
14654 highest (sign) bit, with a fixed binary point at bit point_pos.
14655 m1 holds the low part of the mantissa, m2 the high part.
14656 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
14657 bits for the mantissa, this can fail (low bits will be lost). */
14661 /* If the low part of the mantissa has bits set we cannot represent
14662 the value. */
14665 /* We have rejected the lower HOST_WIDE_INT, so update our
14666 understanding of how many bits lie in the mantissa and
14667 look only at the high HOST_WIDE_INT. */
14671 /* We can only represent values with a mantissa of the form 1.xxxx. */
14676 /* Having filtered unrepresentable values, we may now remove all
14677 but the highest 5 bits. */
14680 /* We cannot represent the value 0.0, so reject it. This is handled
14681 elsewhere. */
14685 /* Then, as bit 4 is always set, we can mask it off, leaving
14686 the mantissa in the range [0, 15]. */
14690 /* GCC internally does not use IEEE754-like encoding (where normalized
14691 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
14692 Our mantissa values are shifted 4 places to the left relative to
14693 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
14694 by 5 places to correct for GCC's representation. */
14698 }
14700 /* Returns the string with the instruction for AdvSIMD MOVI, MVNI, ORR or BIC
14701 immediate with a CONST_VECTOR of MODE and WIDTH. WHICH selects whether to
14702 output MOVI/MVNI, ORR or BIC immediate. */
14706 {
14716 /* This will return true to show const_vector is legal for use as either
14717 a AdvSIMD MOVI instruction (or, implicitly, MVNI), ORR or BIC immediate.
14718 It will also update INFO to show how the immediate should be generated.
14719 WHICH selects whether to check for MOVI/MVNI, ORR or BIC. */
14727 {
14729 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
14730 move immediate path. */
14733 else
14734 {
14743 else
14747 }
14748 }
14753 {
14763 else
14767 }
14768 else
14769 {
14770 /* For AARCH64_CHECK_BIC and AARCH64_CHECK_ORR. */
14776 else
14780 }
14782 }
14786 {
14788 /* If a floating point number was passed and we desire to use it in an
14789 integer mode do the conversion to integer. */
14791 {
14796 }
14798 machine_mode vmode;
14799 /* use a 64 bit mode for everything except for DI/DF mode, where we use
14800 a 128 bit vector mode. */
14806 }
14808 /* Return the output string to use for moving immediate CONST_VECTOR
14809 into an SVE register. */
14813 {
14824 {
14829 }
14832 {
14835 else
14836 {
14846 }
14847 }
14852 }
14854 /* Return the asm format for a PTRUE instruction whose destination has
14855 mode MODE. SUFFIX is the element size suffix. */
14859 {
14864 else
14867 }
14869 /* Split operands into moves from op[1] + op[2] into op[0]. */
14871 void
14873 {
14884 {
14885 /* No-op move. Can't split to nothing; emit something. */
14888 }
14890 /* Preserve register attributes for variable tracking. */
14895 /* Special case of reversed high/low parts. */
14898 {
14902 }
14904 {
14905 /* Try to avoid unnecessary moves if part of the result
14906 is in the right place already. */
14911 }
14912 else
14913 {
14918 }
14919 }
14921 /* vec_perm support. */
14923 struct expand_vec_perm_d
14924 {
14926 vec_perm_indices perm;
14927 machine_mode vmode;
14931 };
14933 /* Generate a variable permutation. */
14935 static void
14937 {
14948 {
14950 {
14951 /* Expand the argument to a V16QI mode by duplicating it. */
14955 }
14956 else
14957 {
14959 }
14960 }
14961 else
14962 {
14963 rtx pair;
14966 {
14970 }
14971 else
14972 {
14976 }
14977 }
14978 }
14980 /* Expand a vec_perm with the operands given by TARGET, OP0, OP1 and SEL.
14981 NELT is the number of elements in the vector. */
14983 void
14986 {
14989 rtx mask;
14991 /* The TBL instruction does not use a modulo index, so we must take care
14992 of that ourselves. */
14997 /* For big-endian, we also need to reverse the index within the vector
14998 (but not which vector). */
15000 {
15001 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
15006 }
15008 }
15010 /* Generate (set TARGET (unspec [OP0 OP1] CODE)). */
15012 static void
15014 {
15018 }
15020 /* Expand an SVE vec_perm with the given operands. */
15022 void
15024 {
15027 /* Enforced by the pattern condition. */
15030 /* Note: vec_perm indices are supposed to wrap when they go beyond the
15031 size of the two value vectors, i.e. the upper bits of the indices
15032 are effectively ignored. SVE TBL instead produces 0 for any
15033 out-of-range indices, so we need to modulo all the vec_perm indices
15034 to ensure they are all in range. */
15037 /* Check if the sel only references the first values vector. */
15040 {
15043 }
15045 /* Check if the two values vectors are the same. */
15047 {
15053 }
15055 /* Run TBL on for each value vector and combine the results. */
15062 {
15067 }
15074 else
15076 }
15078 /* Recognize patterns suitable for the TRN instructions. */
15079 static bool
15081 {
15082 HOST_WIDE_INT odd;
15090 /* Note that these are little-endian tests.
15091 We correct for big-endian later. */
15098 /* Success! */
15104 /* We don't need a big-endian lane correction for SVE; see the comment
15105 at the head of aarch64-sve.md for details. */
15107 {
15110 }
15116 }
15118 /* Recognize patterns suitable for the UZP instructions. */
15119 static bool
15121 {
15122 HOST_WIDE_INT odd;
15129 /* Note that these are little-endian tests.
15130 We correct for big-endian later. */
15136 /* Success! */
15142 /* We don't need a big-endian lane correction for SVE; see the comment
15143 at the head of aarch64-sve.md for details. */
15145 {
15148 }
15154 }
15156 /* Recognize patterns suitable for the ZIP instructions. */
15157 static bool
15159 {
15168 /* Note that these are little-endian tests.
15169 We correct for big-endian later. */
15177 /* Success! */
15183 /* We don't need a big-endian lane correction for SVE; see the comment
15184 at the head of aarch64-sve.md for details. */
15186 {
15189 }
15195 }
15197 /* Recognize patterns for the EXT insn. */
15199 static bool
15201 {
15202 HOST_WIDE_INT location;
15203 rtx offset;
15205 /* The first element always refers to the first vector.
15206 Check if the extracted indices are increasing by one. */
15212 /* Success! */
15216 /* The case where (location == 0) is a no-op for both big- and little-endian,
15217 and is removed by the mid-end at optimization levels -O1 and higher.
15219 We don't need a big-endian lane correction for SVE; see the comment
15220 at the head of aarch64-sve.md for details. */
15222 {
15223 /* After setup, we want the high elements of the first vector (stored
15224 at the LSB end of the register), and the low elements of the second
15225 vector (stored at the MSB end of the register). So swap. */
15227 /* location != 0 (above), so safe to assume (nelt - location) < nelt.
15228 to_constant () is safe since this is restricted to Advanced SIMD
15229 vectors. */
15231 }
15237 UNSPEC_EXT));
15239 }
15241 /* Recognize patterns for the REV{64,32,16} insns, which reverse elements
15242 within each 64-bit, 32-bit or 16-bit granule. */
15244 static bool
15246 {
15247 HOST_WIDE_INT diff;
15249 machine_mode pred_mode;
15258 {
15261 }
15263 {
15266 }
15268 {
15271 }
15272 else
15280 /* Success! */
15286 {
15289 UNSPEC_MERGE_PTRUE);
15290 }
15293 }
15295 /* Recognize patterns for the REV insn, which reverses elements within
15296 a full vector. */
15298 static bool
15300 {
15309 /* Success! */
15316 }
15318 static bool
15320 {
15322 rtx in0;
15323 HOST_WIDE_INT elt;
15325 rtx lane;
15335 /* Success! */
15339 /* The generic preparation in aarch64_expand_vec_perm_const_1
15340 swaps the operand order and the permute indices if it finds
15341 d->perm[0] to be in the second operand. Thus, we can always
15342 use d->op0 and need not do any extra arithmetic to get the
15343 correct lane number. */
15351 }
15353 static bool
15355 {
15359 /* Make sure that the indices are constant. */
15368 /* Generic code will try constant permutation twice. Once with the
15369 original mode and again with the elements lowered to QImode.
15370 So wait and don't do the selector expansion ourselves. */
15374 /* to_constant is safe since this routine is specific to Advanced SIMD
15375 vectors. */
15378 /* If big-endian and two vectors we end up with a weird mixed-endian
15379 mode on NEON. Reverse the index within each word but not the word
15380 itself. to_constant is safe because we checked is_constant above. */
15390 }
15392 /* Try to implement D using an SVE TBL instruction. */
15394 static bool
15396 {
15399 /* Permuting two variable-length vectors could overflow the
15400 index range. */
15411 }
15413 static bool
15415 {
15416 /* The pattern matching functions above are written to look for a small
15417 number to begin the sequence (0, 1, N/2). If we begin with an index
15418 from the second operand, we can swap the operands. */
15421 {
15424 }
15430 {
15449 }
15451 }
15453 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
15455 static bool
15458 {
15461 /* Check whether the mask can be applied to a single vector. */
15465 {
15468 }
15470 {
15473 }
15474 else
15494 }
15496 /* Generate a byte permute mask for a register of mode MODE,
15497 which has NUNITS units. */
15499 rtx
15501 {
15502 /* We have to reverse each vector because we dont have
15503 a permuted load that can reverse-load according to ABI rules. */
15504 rtx mask;
15517 }
15519 /* Return true if X is a valid second operand for the SVE instruction
15520 that implements integer comparison OP_CODE. */
15522 static bool
15524 {
15529 {
15544 }
15545 }
15547 /* Return the UNSPEC_COND_* code for comparison CODE. */
15549 static unsigned int
15551 {
15553 {
15578 }
15579 }
15581 /* Return an (unspec:PRED_MODE [PRED OP0 OP1] UNSPEC_COND_<X>) expression,
15582 where <X> is the operation associated with comparison CODE. */
15584 static rtx
15587 {
15590 }
15592 /* Expand an SVE integer comparison:
15594 TARGET = CODE (OP0, OP1). */
15596 void
15598 {
15608 }
15610 /* Emit an instruction:
15612 (set TARGET (unspec:PRED_MODE [PRED OP0 OP1] UNSPEC_COND_<X>))
15614 where <X> is the operation associated with comparison CODE. */
15616 static void
15619 {
15622 }
15624 /* Emit:
15626 (set TMP1 (unspec:PRED_MODE [PTRUE OP0 OP1] UNSPEC_COND_<X1>))
15627 (set TMP2 (unspec:PRED_MODE [PTRUE OP0 OP1] UNSPEC_COND_<X2>))
15628 (set TARGET (and:PRED_MODE (ior:PRED_MODE TMP1 TMP2) PTRUE))
15630 where <Xi> is the operation associated with comparison CODEi. */
15632 static void
15636 {
15643 ptrue));
15644 }
15646 /* If CAN_INVERT_P, emit an instruction:
15648 (set TARGET (unspec:PRED_MODE [PRED OP0 OP1] UNSPEC_COND_<X>))
15650 where <X> is the operation associated with comparison CODE. Otherwise
15651 emit:
15653 (set TMP (unspec:PRED_MODE [PRED OP0 OP1] UNSPEC_COND_<X>))
15654 (set TARGET (and:PRED_MODE (not:PRED_MODE TMP) PTRUE))
15656 where the second instructions sets TARGET to the inverse of TMP. */
15658 static void
15662 {
15665 else
15666 {
15671 ptrue));
15672 }
15673 }
15675 /* Expand an SVE floating-point comparison:
15677 TARGET = CODE (OP0, OP1)
15679 If CAN_INVERT_P is true, the caller can also handle inverted results;
15680 return true if the result is in fact inverted. */
15682 bool
15685 {
15691 {
15693 /* UNORDERED has no immediate form. */
15704 /* There is native support for the comparison. */
15709 /* There is native support for the inverse comparison. */
15713 can_invert_p);
15717 /* This is a trapping operation (LT or GT). */
15723 {
15724 /* This would trap for signaling NaNs. */
15729 }
15730 /* fall through */
15736 {
15739 {
15740 /* Only compare the elements that are known to be ordered. */
15745 }
15748 else
15753 }
15757 }
15758 }
15760 /* Expand an SVE vcond pattern with operands OPS. DATA_MODE is the mode
15761 of the data being selected and CMP_MODE is the mode of the values being
15762 compared. */
15764 void
15767 {
15768 machine_mode pred_mode
15773 {
15777 }
15778 else
15783 }
15785 /* Implement TARGET_MODES_TIEABLE_P. In principle we should always return
15786 true. However due to issues with register allocation it is preferable
15787 to avoid tieing integer scalar and FP scalar modes. Executing integer
15788 operations in general registers is better than treating them as scalar
15789 vector operations. This reduces latency and avoids redundant int<->FP
15790 moves. So tie modes if they are either the same class, or vector modes
15791 with other vector modes, vector structs or any scalar mode. */
15793 static bool
15795 {
15799 /* We specifically want to allow elements of "structure" modes to
15800 be tieable to the structure. This more general condition allows
15801 other rarer situations too. The reason we don't extend this to
15802 predicate modes is that there are no predicate structure modes
15803 nor any specific instructions for extracting part of a predicate
15804 register. */
15809 /* Also allow any scalar modes with vectors. */
15815 }
15817 /* Return a new RTX holding the result of moving POINTER forward by
15818 AMOUNT bytes. */
15820 static rtx
15822 {
15827 }
15829 /* Return a new RTX holding the result of moving POINTER forward by the
15830 size of the mode it points to. */
15832 static rtx
15834 {
15836 }
15838 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
15839 MODE bytes. */
15841 static void
15843 machine_mode mode)
15844 {
15847 /* "Cast" the pointers to the correct mode. */
15850 /* Emit the memcpy. */
15853 /* Move the pointers forward. */
15856 }
15858 /* Expand movmem, as if from a __builtin_memcpy. Return true if
15859 we succeed, otherwise return false. */
15861 bool
15863 {
15867 rtx base;
15870 /* When optimizing for size, give a better estimate of the length of a
15871 memcpy call, but use the default otherwise. */
15874 /* We can't do anything smart if the amount to copy is not constant. */
15880 /* Try to keep the number of instructions low. For cases below 16 bytes we
15881 need to make at most two moves. For cases above 16 bytes it will be one
15882 move for each 16 byte chunk, then at most two additional moves. */
15892 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
15893 1-byte chunk. */
15895 {
15897 {
15900 }
15906 }
15908 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
15909 4-byte chunk, partially overlapping with the previously copied chunk. */
15911 {
15915 {
15921 }
15923 }
15925 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
15926 them, then (if applicable) an 8-byte chunk. */
15928 {
15930 {
15933 }
15934 else
15935 {
15938 }
15939 }
15941 /* Finish the final bytes of the copy. We can always do this in one
15942 instruction. We either copy the exact amount we need, or partially
15943 overlap with the previous chunk we copied and copy 8-bytes. */
15952 else
15953 {
15955 {
15959 }
15960 else
15961 {
15967 }
15968 }
15971 }
15973 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
15974 SImode stores. Handle the case when the constant has identical
15975 bottom and top halves. This is beneficial when the two stores can be
15976 merged into an STP and we avoid synthesising potentially expensive
15977 immediates twice. Return true if such a split is possible. */
15979 bool
15981 {
15990 unsigned int orig_cost
15992 unsigned int lo_cost
15995 /* We want to transform:
15996 MOV x1, 49370
15997 MOVK x1, 0x140, lsl 16
15998 MOVK x1, 0xc0da, lsl 32
15999 MOVK x1, 0x140, lsl 48
16000 STR x1, [x0]
16001 into:
16002 MOV w1, 49370
16003 MOVK w1, 0x140, lsl 16
16004 STP w1, w1, [x0]
16005 So we want to perform this only when we save two instructions
16006 or more. When optimizing for size, however, accept any code size
16007 savings we can. */
16022 /* Don't emit an explicit store pair as this may not be always profitable.
16023 Let the sched-fusion logic decide whether to merge them. */
16028 }
16030 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
16032 static unsigned HOST_WIDE_INT
16034 {
16036 }
16038 static rtx
16041 {
16045 insn_code icode;
16056 {
16084 }
16089 {
16092 }
16101 {
16104 }
16110 }
16112 static rtx
16115 {
16119 insn_code icode;
16131 {
16159 }
16164 {
16167 }
16175 {
16180 }
16191 {
16194 }
16200 }
16202 #undef TARGET_GEN_CCMP_FIRST
16203 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
16205 #undef TARGET_GEN_CCMP_NEXT
16206 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
16208 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
16209 instruction fusion of some sort. */
16211 static bool
16213 {
16215 }
16218 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
16219 should be kept together during scheduling. */
16221 static bool
16223 {
16224 rtx set_dest;
16227 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
16234 {
16235 /* We are trying to match:
16236 prev (mov) == (set (reg r0) (const_int imm16))
16237 curr (movk) == (set (zero_extract (reg r0)
16238 (const_int 16)
16239 (const_int 16))
16240 (const_int imm16_1)) */
16252 {
16254 }
16255 }
16258 {
16260 /* We're trying to match:
16261 prev (adrp) == (set (reg r1)
16262 (high (symbol_ref ("SYM"))))
16263 curr (add) == (set (reg r0)
16264 (lo_sum (reg r1)
16265 (symbol_ref ("SYM"))))
16266 Note that r0 need not necessarily be the same as r1, especially
16267 during pre-regalloc scheduling. */
16271 {
16279 }
16280 }
16283 {
16285 /* We're trying to match:
16286 prev (movk) == (set (zero_extract (reg r0)
16287 (const_int 16)
16288 (const_int 32))
16289 (const_int imm16_1))
16290 curr (movk) == (set (zero_extract (reg r0)
16291 (const_int 16)
16292 (const_int 48))
16293 (const_int imm16_2)) */
16309 }
16311 {
16312 /* We're trying to match:
16313 prev (adrp) == (set (reg r0)
16314 (high (symbol_ref ("SYM"))))
16315 curr (ldr) == (set (reg r1)
16316 (mem (lo_sum (reg r0)
16317 (symbol_ref ("SYM")))))
16318 or
16319 curr (ldr) == (set (reg r1)
16320 (zero_extend (mem
16321 (lo_sum (reg r0)
16322 (symbol_ref ("SYM")))))) */
16325 {
16338 }
16339 }
16347 {
16351 rtx cc_reg_1;
16356 && prev
16358 {
16359 /* FIXME: this misses some which is considered simple arthematic
16360 instructions for ThunderX. Simple shifts are missed here. */
16366 }
16367 }
16370 && curr_set
16373 {
16374 /* We're trying to match:
16375 prev (alu_insn) == (set (r0) plus ((r0) (r1/imm)))
16376 curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0)
16377 (const_int 0))
16378 (label_ref ("SYM"))
16379 (pc)) */
16386 {
16387 /* Fuse ALU operations followed by conditional branch instruction. */
16389 {
16410 }
16411 }
16412 }
16415 }
16417 /* Return true iff the instruction fusion described by OP is enabled. */
16419 bool
16421 {
16423 }
16425 /* If MEM is in the form of [base+offset], extract the two parts
16426 of address and set to BASE and OFFSET, otherwise return false
16427 after clearing BASE and OFFSET. */
16429 bool
16431 {
16432 rtx addr;
16439 {
16443 }
16447 {
16451 }
16457 }
16459 /* Types for scheduling fusion. */
16460 enum sched_fusion_type
16461 {
16463 SCHED_FUSION_LD_SIGN_EXTEND,
16464 SCHED_FUSION_LD_ZERO_EXTEND,
16465 SCHED_FUSION_LD,
16466 SCHED_FUSION_ST,
16467 SCHED_FUSION_NUM
16468 };
16470 /* If INSN is a load or store of address in the form of [base+offset],
16471 extract the two parts and set to BASE and OFFSET. Return scheduling
16472 fusion type this INSN is. */
16474 static enum sched_fusion_type
16476 {
16494 {
16499 }
16501 {
16506 }
16511 {
16514 }
16515 else
16522 }
16524 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
16526 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
16527 and PRI are only calculated for these instructions. For other instruction,
16528 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
16529 type instruction fusion can be added by returning different priorities.
16531 It's important that irrelevant instructions get the largest FUSION_PRI. */
16533 static void
16536 {
16546 {
16550 }
16552 /* Set FUSION_PRI according to fusion type and base register. */
16555 /* Calculate PRI. */
16558 /* INSN with smaller offset goes first. */
16562 else
16567 }
16569 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
16570 Adjust priority of sha1h instructions so they are scheduled before
16571 other SHA1 instructions. */
16573 static int
16575 {
16579 {
16584 }
16587 }
16589 /* Given OPERANDS of consecutive load/store, check if we can merge
16590 them into ldp/stp. LOAD is true if they are load instructions.
16591 MODE is the mode of memory operands. */
16593 bool
16595 machine_mode mode)
16596 {
16602 {
16610 }
16611 else
16612 {
16617 }
16619 /* The mems cannot be volatile. */
16623 /* If we have SImode and slow unaligned ldp,
16624 check the alignment to be at least 8 byte. */
16628 && !optimize_size
16632 /* Check if the addresses are in the form of [base+offset]. */
16640 /* Check if the bases are same. */
16646 /* We should only be trying this for fixed-sized modes. There is no
16647 SVE LDP/STP instruction. */
16649 /* Check if the offsets are consecutive. */
16653 /* Check if the addresses are clobbered by load. */
16655 {
16659 /* In increasing order, the last load can clobber the address. */
16662 }
16666 else
16671 else
16674 /* Check if the registers are of same class. */
16679 }
16681 /* Given OPERANDS of consecutive load/store, check if we can merge
16682 them into ldp/stp by adjusting the offset. LOAD is true if they
16683 are load instructions. MODE is the mode of memory operands.
16685 Given below consecutive stores:
16687 str w1, [xb, 0x100]
16688 str w1, [xb, 0x104]
16689 str w1, [xb, 0x108]
16690 str w1, [xb, 0x10c]
16692 Though the offsets are out of the range supported by stp, we can
16693 still pair them after adjusting the offset, like:
16695 add scratch, xb, 0x100
16696 stp w1, w1, [scratch]
16697 stp w1, w1, [scratch, 0x8]
16699 The peephole patterns detecting this opportunity should guarantee
16700 the scratch register is avaliable. */
16702 bool
16704 scalar_mode mode)
16705 {
16712 {
16725 }
16726 else
16727 {
16736 }
16737 /* Skip if memory operand is by itslef valid for ldp/stp. */
16741 /* The mems cannot be volatile. */
16746 /* Check if the addresses are in the form of [base+offset]. */
16760 /* Check if the bases are same. */
16771 /* Check if the offsets are consecutive. */
16780 /* Check if the addresses are clobbered by load. */
16782 {
16788 /* In increasing order, the last load can clobber the address. */
16791 }
16793 /* If we have SImode and slow unaligned ldp,
16794 check the alignment to be at least 8 byte. */
16798 && !optimize_size
16804 else
16809 else
16814 else
16819 else
16822 /* Check if the registers are of same class. */
16827 }
16829 /* Given OPERANDS of consecutive load/store, this function pairs them
16830 into ldp/stp after adjusting the offset. It depends on the fact
16831 that addresses of load/store instructions are in increasing order.
16832 MODE is the mode of memory operands. CODE is the rtl operator
16833 which should be applied to all memory operands, it's SIGN_EXTEND,
16834 ZERO_EXTEND or UNKNOWN. */
16836 bool
16839 {
16845 {
16850 }
16851 else
16852 {
16858 }
16863 /* Adjust offset thus it can fit in ldp/stp instruction. */
16871 /* Further adjust to make sure all offsets are OK. */
16873 {
16876 }
16878 /* Make sure the adjustment can be done with ADD/SUB instructions. */
16883 {
16886 }
16888 /* Create new memory references. */
16892 /* Check if the adjusted address is OK for ldp/stp. */
16911 {
16916 }
16918 {
16923 }
16926 {
16931 }
16932 else
16933 {
16938 }
16940 /* Emit adjusting instruction. */
16942 /* Emit ldp/stp instructions. */
16950 }
16952 /* Implement TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE. Assume for now that
16953 it isn't worth branching around empty masked ops (including masked
16954 stores). */
16956 static bool
16958 {
16960 }
16962 /* Return 1 if pseudo register should be created and used to hold
16963 GOT address for PIC code. */
16965 bool
16967 {
16969 }
16971 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
16973 static int
16975 {
16977 {
16984 }
16987 }
16990 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
16991 return the log2 of that value. Otherwise return -1. */
16993 int
16995 {
17010 }
17012 /* If X is a vector of equal CONST_DOUBLE values and that value is
17013 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
17015 int
17017 {
17035 }
17037 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
17038 to float.
17040 __fp16 always promotes through this hook.
17041 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
17042 through the generic excess precision logic rather than here. */
17044 static tree
17046 {
17052 }
17054 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
17056 static bool
17058 optimization_type opt_type)
17059 {
17061 {
17067 }
17068 }
17070 /* Implement the TARGET_DWARF_POLY_INDETERMINATE_VALUE hook. */
17072 static unsigned int
17075 {
17076 /* Polynomial invariant 1 == (VG / 2) - 1. */
17081 }
17083 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
17084 if MODE is HFmode, and punt to the generic implementation otherwise. */
17086 static bool
17088 {
17092 }
17094 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
17095 if MODE is HFmode, and punt to the generic implementation otherwise. */
17097 static bool
17099 {
17103 }
17105 /* Set the value of FLT_EVAL_METHOD.
17106 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
17108 0: evaluate all operations and constants, whose semantic type has at
17109 most the range and precision of type float, to the range and
17110 precision of float; evaluate all other operations and constants to
17111 the range and precision of the semantic type;
17113 N, where _FloatN is a supported interchange floating type
17114 evaluate all operations and constants, whose semantic type has at
17115 most the range and precision of _FloatN type, to the range and
17116 precision of the _FloatN type; evaluate all other operations and
17117 constants to the range and precision of the semantic type;
17119 If we have the ARMv8.2-A extensions then we support _Float16 in native
17120 precision, so we should set this to 16. Otherwise, we support the type,
17121 but want to evaluate expressions in float precision, so set this to
17122 0. */
17124 static enum flt_eval_method
17126 {
17128 {
17131 /* We can calculate either in 16-bit range and precision or
17132 32-bit range and precision. Make that decision based on whether
17133 we have native support for the ARMv8.2-A 16-bit floating-point
17134 instructions or not. */
17136 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
17142 }
17144 }
17146 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
17147 scheduled for speculative execution. Reject the long-running division
17148 and square-root instructions. */
17150 static bool
17152 {
17154 {
17172 }
17173 }
17175 /* Implement TARGET_COMPUTE_PRESSURE_CLASSES. */
17177 static int
17179 {
17183 /* PR_REGS isn't a useful pressure class because many predicate pseudo
17184 registers need to go in PR_LO_REGS at some point during their
17185 lifetime. Splitting it into two halves has the effect of making
17186 all predicates count against PR_LO_REGS, so that we try whenever
17187 possible to restrict the number of live predicates to 8. This
17188 greatly reduces the amount of spilling in certain loops. */
17192 }
17194 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
17196 static bool
17199 {
17200 /* See the comment at the head of aarch64-sve.md for details. */
17205 }
17207 /* Implement TARGET_EARLY_REMAT_MODES. */
17209 static void
17211 {
17212 /* SVE values are not normally live across a call, so it should be
17213 worth doing early rematerialization even in VL-specific mode. */
17215 {
17220 }
17221 }
17223 /* Target-specific selftests. */
17225 #if CHECKING_P
17229 /* Selftest for the RTL loader.
17230 Verify that the RTL loader copes with a dump from
17231 print_rtx_function. This is essentially just a test that class
17232 function_reader can handle a real dump, but it also verifies
17233 that lookup_reg_by_dump_name correctly handles hard regs.
17234 The presence of hard reg names in the dump means that the test is
17235 target-specific, hence it is in this file. */
17237 static void
17239 {
17251 /* Verify crtl->return_rtx. */
17255 }
17257 /* Run all target-specific selftests. */
17259 static void
17261 {
17263 }
17269 #undef TARGET_ADDRESS_COST
17270 #define TARGET_ADDRESS_COST aarch64_address_cost
17272 /* This hook will determines whether unnamed bitfields affect the alignment
17273 of the containing structure. The hook returns true if the structure
17274 should inherit the alignment requirements of an unnamed bitfield's
17275 type. */
17276 #undef TARGET_ALIGN_ANON_BITFIELD
17277 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
17279 #undef TARGET_ASM_ALIGNED_DI_OP
17282 #undef TARGET_ASM_ALIGNED_HI_OP
17285 #undef TARGET_ASM_ALIGNED_SI_OP
17288 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
17289 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
17290 hook_bool_const_tree_hwi_hwi_const_tree_true
17292 #undef TARGET_ASM_FILE_START
17293 #define TARGET_ASM_FILE_START aarch64_start_file
17295 #undef TARGET_ASM_OUTPUT_MI_THUNK
17296 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
17298 #undef TARGET_ASM_SELECT_RTX_SECTION
17299 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
17301 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
17302 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
17304 #undef TARGET_BUILD_BUILTIN_VA_LIST
17305 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
17307 #undef TARGET_CALLEE_COPIES
17308 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
17310 #undef TARGET_CAN_ELIMINATE
17311 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
17313 #undef TARGET_CAN_INLINE_P
17314 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
17316 #undef TARGET_CANNOT_FORCE_CONST_MEM
17317 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
17319 #undef TARGET_CASE_VALUES_THRESHOLD
17320 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
17322 #undef TARGET_CONDITIONAL_REGISTER_USAGE
17323 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
17325 /* Only the least significant bit is used for initialization guard
17326 variables. */
17327 #undef TARGET_CXX_GUARD_MASK_BIT
17328 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
17330 #undef TARGET_C_MODE_FOR_SUFFIX
17331 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
17333 #ifdef TARGET_BIG_ENDIAN_DEFAULT
17334 #undef TARGET_DEFAULT_TARGET_FLAGS
17335 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
17336 #endif
17338 #undef TARGET_CLASS_MAX_NREGS
17339 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
17341 #undef TARGET_BUILTIN_DECL
17342 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
17344 #undef TARGET_BUILTIN_RECIPROCAL
17345 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
17347 #undef TARGET_C_EXCESS_PRECISION
17348 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
17350 #undef TARGET_EXPAND_BUILTIN
17351 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
17353 #undef TARGET_EXPAND_BUILTIN_VA_START
17354 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
17356 #undef TARGET_FOLD_BUILTIN
17357 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
17359 #undef TARGET_FUNCTION_ARG
17360 #define TARGET_FUNCTION_ARG aarch64_function_arg
17362 #undef TARGET_FUNCTION_ARG_ADVANCE
17363 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
17365 #undef TARGET_FUNCTION_ARG_BOUNDARY
17366 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
17368 #undef TARGET_FUNCTION_ARG_PADDING
17369 #define TARGET_FUNCTION_ARG_PADDING aarch64_function_arg_padding
17371 #undef TARGET_GET_RAW_RESULT_MODE
17372 #define TARGET_GET_RAW_RESULT_MODE aarch64_get_reg_raw_mode
17373 #undef TARGET_GET_RAW_ARG_MODE
17374 #define TARGET_GET_RAW_ARG_MODE aarch64_get_reg_raw_mode
17376 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
17377 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
17379 #undef TARGET_FUNCTION_VALUE
17380 #define TARGET_FUNCTION_VALUE aarch64_function_value
17382 #undef TARGET_FUNCTION_VALUE_REGNO_P
17383 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
17385 #undef TARGET_GIMPLE_FOLD_BUILTIN
17386 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
17388 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
17389 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
17391 #undef TARGET_INIT_BUILTINS
17392 #define TARGET_INIT_BUILTINS aarch64_init_builtins
17394 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
17395 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
17396 aarch64_ira_change_pseudo_allocno_class
17398 #undef TARGET_LEGITIMATE_ADDRESS_P
17399 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
17401 #undef TARGET_LEGITIMATE_CONSTANT_P
17402 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
17404 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
17405 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
17406 aarch64_legitimize_address_displacement
17408 #undef TARGET_LIBGCC_CMP_RETURN_MODE
17409 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
17411 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
17412 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
17413 aarch64_libgcc_floating_mode_supported_p
17415 #undef TARGET_MANGLE_TYPE
17416 #define TARGET_MANGLE_TYPE aarch64_mangle_type
17418 #undef TARGET_MEMORY_MOVE_COST
17419 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
17421 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
17422 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
17424 #undef TARGET_MUST_PASS_IN_STACK
17425 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
17427 /* This target hook should return true if accesses to volatile bitfields
17428 should use the narrowest mode possible. It should return false if these
17429 accesses should use the bitfield container type. */
17430 #undef TARGET_NARROW_VOLATILE_BITFIELD
17431 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
17433 #undef TARGET_OPTION_OVERRIDE
17434 #define TARGET_OPTION_OVERRIDE aarch64_override_options
17436 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
17437 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
17438 aarch64_override_options_after_change
17440 #undef TARGET_OPTION_SAVE
17441 #define TARGET_OPTION_SAVE aarch64_option_save
17443 #undef TARGET_OPTION_RESTORE
17444 #define TARGET_OPTION_RESTORE aarch64_option_restore
17446 #undef TARGET_OPTION_PRINT
17447 #define TARGET_OPTION_PRINT aarch64_option_print
17449 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
17450 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
17452 #undef TARGET_SET_CURRENT_FUNCTION
17453 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
17455 #undef TARGET_PASS_BY_REFERENCE
17456 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
17458 #undef TARGET_PREFERRED_RELOAD_CLASS
17459 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
17461 #undef TARGET_SCHED_REASSOCIATION_WIDTH
17462 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
17464 #undef TARGET_PROMOTED_TYPE
17465 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
17467 #undef TARGET_SECONDARY_RELOAD
17468 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
17470 #undef TARGET_SHIFT_TRUNCATION_MASK
17471 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
17473 #undef TARGET_SETUP_INCOMING_VARARGS
17474 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
17476 #undef TARGET_STRUCT_VALUE_RTX
17477 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
17479 #undef TARGET_REGISTER_MOVE_COST
17480 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
17482 #undef TARGET_RETURN_IN_MEMORY
17483 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
17485 #undef TARGET_RETURN_IN_MSB
17486 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
17488 #undef TARGET_RTX_COSTS
17489 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
17491 #undef TARGET_SCALAR_MODE_SUPPORTED_P
17492 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
17494 #undef TARGET_SCHED_ISSUE_RATE
17495 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
17497 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
17498 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
17499 aarch64_sched_first_cycle_multipass_dfa_lookahead
17501 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
17502 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
17503 aarch64_first_cycle_multipass_dfa_lookahead_guard
17505 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
17506 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
17507 aarch64_get_separate_components
17509 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
17510 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
17511 aarch64_components_for_bb
17513 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
17514 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
17515 aarch64_disqualify_components
17517 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
17518 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
17519 aarch64_emit_prologue_components
17521 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
17522 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
17523 aarch64_emit_epilogue_components
17525 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
17526 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
17527 aarch64_set_handled_components
17529 #undef TARGET_TRAMPOLINE_INIT
17530 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
17532 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
17533 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
17535 #undef TARGET_VECTOR_MODE_SUPPORTED_P
17536 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
17538 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
17539 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
17540 aarch64_builtin_support_vector_misalignment
17542 #undef TARGET_ARRAY_MODE
17543 #define TARGET_ARRAY_MODE aarch64_array_mode
17545 #undef TARGET_ARRAY_MODE_SUPPORTED_P
17546 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
17548 #undef TARGET_VECTORIZE_ADD_STMT_COST
17549 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
17551 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
17552 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
17553 aarch64_builtin_vectorization_cost
17555 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
17556 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
17558 #undef TARGET_VECTORIZE_BUILTINS
17559 #define TARGET_VECTORIZE_BUILTINS
17561 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
17562 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
17563 aarch64_builtin_vectorized_function
17565 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
17566 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
17567 aarch64_autovectorize_vector_sizes
17569 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
17570 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
17571 aarch64_atomic_assign_expand_fenv
17573 /* Section anchor support. */
17575 #undef TARGET_MIN_ANCHOR_OFFSET
17576 #define TARGET_MIN_ANCHOR_OFFSET -256
17578 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
17579 byte offset; we can do much more for larger data types, but have no way
17580 to determine the size of the access. We assume accesses are aligned. */
17581 #undef TARGET_MAX_ANCHOR_OFFSET
17582 #define TARGET_MAX_ANCHOR_OFFSET 4095
17584 #undef TARGET_VECTOR_ALIGNMENT
17585 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
17587 #undef TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT
17588 #define TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT \
17589 aarch64_vectorize_preferred_vector_alignment
17590 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
17591 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
17592 aarch64_simd_vector_alignment_reachable
17594 /* vec_perm support. */
17596 #undef TARGET_VECTORIZE_VEC_PERM_CONST
17597 #define TARGET_VECTORIZE_VEC_PERM_CONST \
17598 aarch64_vectorize_vec_perm_const
17600 #undef TARGET_VECTORIZE_GET_MASK_MODE
17601 #define TARGET_VECTORIZE_GET_MASK_MODE aarch64_get_mask_mode
17602 #undef TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE
17603 #define TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE \
17604 aarch64_empty_mask_is_expensive
17606 #undef TARGET_INIT_LIBFUNCS
17607 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
17609 #undef TARGET_FIXED_CONDITION_CODE_REGS
17610 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
17612 #undef TARGET_FLAGS_REGNUM
17613 #define TARGET_FLAGS_REGNUM CC_REGNUM
17615 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
17616 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
17618 #undef TARGET_ASAN_SHADOW_OFFSET
17619 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
17621 #undef TARGET_LEGITIMIZE_ADDRESS
17622 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
17624 #undef TARGET_SCHED_CAN_SPECULATE_INSN
17625 #define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn
17627 #undef TARGET_CAN_USE_DOLOOP_P
17628 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
17630 #undef TARGET_SCHED_ADJUST_PRIORITY
17631 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
17633 #undef TARGET_SCHED_MACRO_FUSION_P
17634 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
17636 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
17637 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
17639 #undef TARGET_SCHED_FUSION_PRIORITY
17640 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
17642 #undef TARGET_UNSPEC_MAY_TRAP_P
17643 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
17645 #undef TARGET_USE_PSEUDO_PIC_REG
17646 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
17648 #undef TARGET_PRINT_OPERAND
17649 #define TARGET_PRINT_OPERAND aarch64_print_operand
17651 #undef TARGET_PRINT_OPERAND_ADDRESS
17652 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
17654 #undef TARGET_OPTAB_SUPPORTED_P
17655 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
17657 #undef TARGET_OMIT_STRUCT_RETURN_REG
17658 #define TARGET_OMIT_STRUCT_RETURN_REG true
17660 #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
17661 #define TARGET_DWARF_POLY_INDETERMINATE_VALUE \
17662 aarch64_dwarf_poly_indeterminate_value
17664 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
17665 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
17666 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
17668 #undef TARGET_HARD_REGNO_NREGS
17669 #define TARGET_HARD_REGNO_NREGS aarch64_hard_regno_nregs
17670 #undef TARGET_HARD_REGNO_MODE_OK
17671 #define TARGET_HARD_REGNO_MODE_OK aarch64_hard_regno_mode_ok
17673 #undef TARGET_MODES_TIEABLE_P
17674 #define TARGET_MODES_TIEABLE_P aarch64_modes_tieable_p
17676 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
17677 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
17678 aarch64_hard_regno_call_part_clobbered
17680 #undef TARGET_CONSTANT_ALIGNMENT
17681 #define TARGET_CONSTANT_ALIGNMENT aarch64_constant_alignment
17683 #undef TARGET_COMPUTE_PRESSURE_CLASSES
17684 #define TARGET_COMPUTE_PRESSURE_CLASSES aarch64_compute_pressure_classes
17686 #undef TARGET_CAN_CHANGE_MODE_CLASS
17687 #define TARGET_CAN_CHANGE_MODE_CLASS aarch64_can_change_mode_class
17689 #undef TARGET_SELECT_EARLY_REMAT_MODES
17690 #define TARGET_SELECT_EARLY_REMAT_MODES aarch64_select_early_remat_modes
17692 #if CHECKING_P
17693 #undef TARGET_RUN_TARGET_SELFTESTS
17694 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests