| blob | d693fdb2d336857c1403d0251b714558df7ac5fc |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
110 #ifndef CHECK_STACK_LIMIT
111 #define CHECK_STACK_LIMIT (-1)
112 #endif
114 /* Return index of given mode in mult and division cost tables. */
115 #define MODE_INDEX(mode) \
116 ((mode) == QImode ? 0 \
117 : (mode) == HImode ? 1 \
118 : (mode) == SImode ? 2 \
119 : (mode) == DImode ? 3 \
120 : 4)
122 /* Processor costs (relative to an add) */
123 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
124 #define COSTS_N_BYTES(N) ((N) * 2)
126 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
135 const
158 in QImode, HImode and SImode.
159 Relative to reg-reg move (2). */
163 in SFmode, DFmode and XFmode */
165 in SFmode, DFmode and XFmode */
168 in SImode and DImode */
170 in SImode and DImode */
173 in SImode, DImode and TImode */
175 in SImode, DImode and TImode */
188 ix86_size_memcpy,
189 ix86_size_memset,
201 };
203 /* Processor costs (relative to an add) */
206 DUMMY_STRINGOP_ALGS};
209 DUMMY_STRINGOP_ALGS};
211 static const
234 in QImode, HImode and SImode.
235 Relative to reg-reg move (2). */
239 in SFmode, DFmode and XFmode */
241 in SFmode, DFmode and XFmode */
244 in SImode and DImode */
246 in SImode and DImode */
249 in SImode, DImode and TImode */
251 in SImode, DImode and TImode */
264 i386_memcpy,
265 i386_memset,
277 };
281 DUMMY_STRINGOP_ALGS};
284 DUMMY_STRINGOP_ALGS};
286 static const
309 in QImode, HImode and SImode.
310 Relative to reg-reg move (2). */
314 in SFmode, DFmode and XFmode */
316 in SFmode, DFmode and XFmode */
319 in SImode and DImode */
321 in SImode and DImode */
324 in SImode, DImode and TImode */
326 in SImode, DImode and TImode */
329 shared for code and data, so 4kB is
330 not really precise. */
341 i486_memcpy,
342 i486_memset,
354 };
358 DUMMY_STRINGOP_ALGS};
361 DUMMY_STRINGOP_ALGS};
363 static const
386 in QImode, HImode and SImode.
387 Relative to reg-reg move (2). */
391 in SFmode, DFmode and XFmode */
393 in SFmode, DFmode and XFmode */
396 in SImode and DImode */
398 in SImode and DImode */
401 in SImode, DImode and TImode */
403 in SImode, DImode and TImode */
416 pentium_memcpy,
417 pentium_memset,
429 };
431 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
432 (we ensure the alignment). For small blocks inline loop is still a
433 noticeable win, for bigger blocks either rep movsl or rep movsb is
434 way to go. Rep movsb has apparently more expensive startup time in CPU,
435 but after 4K the difference is down in the noise. */
440 DUMMY_STRINGOP_ALGS};
445 DUMMY_STRINGOP_ALGS};
446 static const
469 in QImode, HImode and SImode.
470 Relative to reg-reg move (2). */
474 in SFmode, DFmode and XFmode */
476 in SFmode, DFmode and XFmode */
479 in SImode and DImode */
481 in SImode and DImode */
484 in SImode, DImode and TImode */
486 in SImode, DImode and TImode */
499 pentiumpro_memcpy,
500 pentiumpro_memset,
512 };
516 DUMMY_STRINGOP_ALGS};
519 DUMMY_STRINGOP_ALGS};
520 static const
543 in QImode, HImode and SImode.
544 Relative to reg-reg move (2). */
548 in SFmode, DFmode and XFmode */
550 in SFmode, DFmode and XFmode */
554 in SImode and DImode */
556 in SImode and DImode */
559 in SImode, DImode and TImode */
561 in SImode, DImode and TImode */
574 geode_memcpy,
575 geode_memset,
587 };
591 DUMMY_STRINGOP_ALGS};
594 DUMMY_STRINGOP_ALGS};
595 static const
618 in QImode, HImode and SImode.
619 Relative to reg-reg move (2). */
623 in SFmode, DFmode and XFmode */
625 in SFmode, DFmode and XFmode */
628 in SImode and DImode */
630 in SImode and DImode */
633 in SImode, DImode and TImode */
635 in SImode, DImode and TImode */
639 have integrated l2 cache, but
640 optimizing for k6 is not important
641 enough to worry about that. */
651 k6_memcpy,
652 k6_memset,
664 };
666 /* For some reason, Athlon deals better with REP prefix (relative to loops)
667 compared to K8. Alignment becomes important after 8 bytes for memcpy and
668 128 bytes for memset. */
671 DUMMY_STRINGOP_ALGS};
674 DUMMY_STRINGOP_ALGS};
675 static const
698 in QImode, HImode and SImode.
699 Relative to reg-reg move (2). */
703 in SFmode, DFmode and XFmode */
705 in SFmode, DFmode and XFmode */
708 in SImode and DImode */
710 in SImode and DImode */
713 in SImode, DImode and TImode */
715 in SImode, DImode and TImode */
728 athlon_memcpy,
729 athlon_memset,
741 };
743 /* K8 has optimized REP instruction for medium sized blocks, but for very
744 small blocks it is better to use loop. For large blocks, libcall can
745 do nontemporary accesses and beat inline considerably. */
756 static const
779 in QImode, HImode and SImode.
780 Relative to reg-reg move (2). */
784 in SFmode, DFmode and XFmode */
786 in SFmode, DFmode and XFmode */
789 in SImode and DImode */
791 in SImode and DImode */
794 in SImode, DImode and TImode */
796 in SImode, DImode and TImode */
801 /* New AMD processors never drop prefetches; if they cannot be performed
802 immediately, they are queued. We set number of simultaneous prefetches
803 to a large constant to reflect this (it probably is not a good idea not
804 to limit number of prefetches at all, as their execution also takes some
805 time). */
815 k8_memcpy,
816 k8_memset,
828 };
830 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
831 very small blocks it is better to use loop. For large blocks, libcall can
832 do nontemporary accesses and beat inline considerably. */
865 in QImode, HImode and SImode.
866 Relative to reg-reg move (2). */
870 in SFmode, DFmode and XFmode */
872 in SFmode, DFmode and XFmode */
875 in SImode and DImode */
877 in SImode and DImode */
880 in SImode, DImode and TImode */
882 in SImode, DImode and TImode */
884 /* On K8:
885 MOVD reg64, xmmreg Double FSTORE 4
886 MOVD reg32, xmmreg Double FSTORE 4
887 On AMDFAM10:
888 MOVD reg64, xmmreg Double FADD 3
889 1/1 1/1
890 MOVD reg32, xmmreg Double FADD 3
891 1/1 1/1 */
895 /* New AMD processors never drop prefetches; if they cannot be performed
896 immediately, they are queued. We set number of simultaneous prefetches
897 to a large constant to reflect this (it probably is not a good idea not
898 to limit number of prefetches at all, as their execution also takes some
899 time). */
909 amdfam10_memcpy,
910 amdfam10_memset,
922 };
924 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
925 very small blocks it is better to use loop. For large blocks, libcall
926 can do nontemporary accesses and beat inline considerably. */
960 in QImode, HImode and SImode.
961 Relative to reg-reg move (2). */
965 in SFmode, DFmode and XFmode */
967 in SFmode, DFmode and XFmode */
970 in SImode and DImode */
972 in SImode and DImode */
975 in SImode, DImode and TImode */
977 in SImode, DImode and TImode */
979 /* On K8:
980 MOVD reg64, xmmreg Double FSTORE 4
981 MOVD reg32, xmmreg Double FSTORE 4
982 On AMDFAM10:
983 MOVD reg64, xmmreg Double FADD 3
984 1/1 1/1
985 MOVD reg32, xmmreg Double FADD 3
986 1/1 1/1 */
990 /* New AMD processors never drop prefetches; if they cannot be performed
991 immediately, they are queued. We set number of simultaneous prefetches
992 to a large constant to reflect this (it probably is not a good idea not
993 to limit number of prefetches at all, as their execution also takes some
994 time). */
1004 bdver1_memcpy,
1005 bdver1_memset,
1017 };
1019 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1020 very small blocks it is better to use loop. For large blocks, libcall
1021 can do nontemporary accesses and beat inline considerably. */
1056 in QImode, HImode and SImode.
1057 Relative to reg-reg move (2). */
1061 in SFmode, DFmode and XFmode */
1063 in SFmode, DFmode and XFmode */
1066 in SImode and DImode */
1068 in SImode and DImode */
1071 in SImode, DImode and TImode */
1073 in SImode, DImode and TImode */
1075 /* On K8:
1076 MOVD reg64, xmmreg Double FSTORE 4
1077 MOVD reg32, xmmreg Double FSTORE 4
1078 On AMDFAM10:
1079 MOVD reg64, xmmreg Double FADD 3
1080 1/1 1/1
1081 MOVD reg32, xmmreg Double FADD 3
1082 1/1 1/1 */
1086 /* New AMD processors never drop prefetches; if they cannot be performed
1087 immediately, they are queued. We set number of simultaneous prefetches
1088 to a large constant to reflect this (it probably is not a good idea not
1089 to limit number of prefetches at all, as their execution also takes some
1090 time). */
1100 bdver2_memcpy,
1101 bdver2_memset,
1113 };
1116 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1117 very small blocks it is better to use loop. For large blocks, libcall
1118 can do nontemporary accesses and beat inline considerably. */
1151 in QImode, HImode and SImode.
1152 Relative to reg-reg move (2). */
1156 in SFmode, DFmode and XFmode */
1158 in SFmode, DFmode and XFmode */
1161 in SImode and DImode */
1163 in SImode and DImode */
1166 in SImode, DImode and TImode */
1168 in SImode, DImode and TImode */
1173 /* New AMD processors never drop prefetches; if they cannot be performed
1174 immediately, they are queued. We set number of simultaneous prefetches
1175 to a large constant to reflect this (it probably is not a good idea not
1176 to limit number of prefetches at all, as their execution also takes some
1177 time). */
1187 bdver3_memcpy,
1188 bdver3_memset,
1200 };
1202 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1203 very small blocks it is better to use loop. For large blocks, libcall
1204 can do nontemporary accesses and beat inline considerably. */
1237 in QImode, HImode and SImode.
1238 Relative to reg-reg move (2). */
1242 in SFmode, DFmode and XFmode */
1244 in SFmode, DFmode and XFmode */
1247 in SImode and DImode */
1249 in SImode and DImode */
1252 in SImode, DImode and TImode */
1254 in SImode, DImode and TImode */
1259 /* New AMD processors never drop prefetches; if they cannot be performed
1260 immediately, they are queued. We set number of simultaneous prefetches
1261 to a large constant to reflect this (it probably is not a good idea not
1262 to limit number of prefetches at all, as their execution also takes some
1263 time). */
1273 bdver4_memcpy,
1274 bdver4_memset,
1286 };
1288 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1289 very small blocks it is better to use loop. For large blocks, libcall can
1290 do nontemporary accesses and beat inline considerably. */
1323 in QImode, HImode and SImode.
1324 Relative to reg-reg move (2). */
1328 in SFmode, DFmode and XFmode */
1330 in SFmode, DFmode and XFmode */
1333 in SImode and DImode */
1335 in SImode and DImode */
1338 in SImode, DImode and TImode */
1340 in SImode, DImode and TImode */
1342 /* On K8:
1343 MOVD reg64, xmmreg Double FSTORE 4
1344 MOVD reg32, xmmreg Double FSTORE 4
1345 On AMDFAM10:
1346 MOVD reg64, xmmreg Double FADD 3
1347 1/1 1/1
1348 MOVD reg32, xmmreg Double FADD 3
1349 1/1 1/1 */
1362 btver1_memcpy,
1363 btver1_memset,
1375 };
1409 in QImode, HImode and SImode.
1410 Relative to reg-reg move (2). */
1414 in SFmode, DFmode and XFmode */
1416 in SFmode, DFmode and XFmode */
1419 in SImode and DImode */
1421 in SImode and DImode */
1424 in SImode, DImode and TImode */
1426 in SImode, DImode and TImode */
1428 /* On K8:
1429 MOVD reg64, xmmreg Double FSTORE 4
1430 MOVD reg32, xmmreg Double FSTORE 4
1431 On AMDFAM10:
1432 MOVD reg64, xmmreg Double FADD 3
1433 1/1 1/1
1434 MOVD reg32, xmmreg Double FADD 3
1435 1/1 1/1 */
1447 btver2_memcpy,
1448 btver2_memset,
1460 };
1464 DUMMY_STRINGOP_ALGS};
1468 DUMMY_STRINGOP_ALGS};
1470 static const
1493 in QImode, HImode and SImode.
1494 Relative to reg-reg move (2). */
1498 in SFmode, DFmode and XFmode */
1500 in SFmode, DFmode and XFmode */
1503 in SImode and DImode */
1505 in SImode and DImode */
1508 in SImode, DImode and TImode */
1510 in SImode, DImode and TImode */
1523 pentium4_memcpy,
1524 pentium4_memset,
1536 };
1549 static const
1572 in QImode, HImode and SImode.
1573 Relative to reg-reg move (2). */
1577 in SFmode, DFmode and XFmode */
1579 in SFmode, DFmode and XFmode */
1582 in SImode and DImode */
1584 in SImode and DImode */
1587 in SImode, DImode and TImode */
1589 in SImode, DImode and TImode */
1602 nocona_memcpy,
1603 nocona_memset,
1615 };
1626 static const
1649 in QImode, HImode and SImode.
1650 Relative to reg-reg move (2). */
1654 in SFmode, DFmode and XFmode */
1656 in SFmode, DFmode and XFmode */
1659 in SImode and DImode */
1661 in SImode and DImode */
1664 in SImode, DImode and TImode */
1666 in SImode, DImode and TImode */
1679 atom_memcpy,
1680 atom_memset,
1692 };
1703 static const
1726 in QImode, HImode and SImode.
1727 Relative to reg-reg move (2). */
1731 in SFmode, DFmode and XFmode */
1733 in SFmode, DFmode and XFmode */
1736 in SImode and DImode */
1738 in SImode and DImode */
1741 in SImode, DImode and TImode */
1743 in SImode, DImode and TImode */
1756 slm_memcpy,
1757 slm_memset,
1769 };
1780 static const
1803 in QImode, HImode and SImode.
1804 Relative to reg-reg move (2). */
1808 in SFmode, DFmode and XFmode */
1810 in SFmode, DFmode and XFmode */
1813 in SImode and DImode */
1815 in SImode and DImode */
1818 in SImode, DImode and TImode */
1820 in SImode, DImode and TImode */
1833 intel_memcpy,
1834 intel_memset,
1846 };
1848 /* Generic should produce code tuned for Core-i7 (and newer chips)
1849 and btver1 (and newer chips). */
1861 static const
1864 /* On all chips taken into consideration lea is 2 cycles and more. With
1865 this cost however our current implementation of synth_mult results in
1866 use of unnecessary temporary registers causing regression on several
1867 SPECfp benchmarks. */
1888 in QImode, HImode and SImode.
1889 Relative to reg-reg move (2). */
1893 in SFmode, DFmode and XFmode */
1895 in SFmode, DFmode and XFmode */
1898 in SImode and DImode */
1900 in SImode and DImode */
1903 in SImode, DImode and TImode */
1905 in SImode, DImode and TImode */
1911 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1912 value is increased to perhaps more appropriate value of 5. */
1920 generic_memcpy,
1921 generic_memset,
1933 };
1935 /* core_cost should produce code tuned for Core familly of CPUs. */
1948 static const
1951 /* On all chips taken into consideration lea is 2 cycles and more. With
1952 this cost however our current implementation of synth_mult results in
1953 use of unnecessary temporary registers causing regression on several
1954 SPECfp benchmarks. */
1975 in QImode, HImode and SImode.
1976 Relative to reg-reg move (2). */
1980 in SFmode, DFmode and XFmode */
1982 in SFmode, DFmode and XFmode */
1985 in SImode and DImode */
1987 in SImode and DImode */
1990 in SImode, DImode and TImode */
1992 in SImode, DImode and TImode */
1998 /* FIXME perhaps more appropriate value is 5. */
2006 core_memcpy,
2007 core_memset,
2019 };
2022 /* Set by -mtune. */
2025 /* Set by -mtune or -Os. */
2028 /* Processor feature/optimization bitmasks. */
2029 #define m_386 (1<<PROCESSOR_I386)
2030 #define m_486 (1<<PROCESSOR_I486)
2031 #define m_PENT (1<<PROCESSOR_PENTIUM)
2032 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2033 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2034 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2035 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2036 #define m_CORE2 (1<<PROCESSOR_CORE2)
2037 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2038 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2039 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2040 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2041 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2042 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2043 #define m_KNL (1<<PROCESSOR_KNL)
2044 #define m_INTEL (1<<PROCESSOR_INTEL)
2046 #define m_GEODE (1<<PROCESSOR_GEODE)
2047 #define m_K6 (1<<PROCESSOR_K6)
2048 #define m_K6_GEODE (m_K6 | m_GEODE)
2049 #define m_K8 (1<<PROCESSOR_K8)
2050 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2051 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2052 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2053 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2054 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2055 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2056 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2057 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2058 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2059 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2060 #define m_BTVER (m_BTVER1 | m_BTVER2)
2061 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2063 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2066 #undef DEF_TUNE
2067 #define DEF_TUNE(tune, name, selector) name,
2069 #undef DEF_TUNE
2070 };
2072 /* Feature tests against the various tunings. */
2075 /* Feature tests against the various tunings used to create ix86_tune_features
2076 based on the processor mask. */
2078 #undef DEF_TUNE
2079 #define DEF_TUNE(tune, name, selector) selector,
2081 #undef DEF_TUNE
2082 };
2084 /* Feature tests against the various architecture variations. */
2087 /* Feature tests against the various architecture variations, used to create
2088 ix86_arch_features based on the processor mask. */
2090 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2093 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2096 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2099 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2102 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2104 };
2106 /* In case the average insn count for single function invocation is
2107 lower than this constant, emit fast (but longer) prologue and
2108 epilogue code. */
2109 #define FAST_PROLOGUE_INSN_COUNT 20
2111 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2116 /* Array of the smallest class containing reg number REGNO, indexed by
2117 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2120 {
2121 /* ax, dx, cx, bx */
2123 /* si, di, bp, sp */
2125 /* FP registers */
2128 /* arg pointer */
2129 NON_Q_REGS,
2130 /* flags, fpsr, fpcr, frame */
2132 /* SSE registers */
2135 /* MMX registers */
2138 /* REX registers */
2141 /* SSE REX registers */
2144 /* AVX-512 SSE registers */
2149 /* Mask registers. */
2152 /* MPX bound registers */
2154 };
2156 /* The "default" register map used in 32bit mode. */
2159 {
2171 };
2173 /* The "default" register map used in 64bit mode. */
2176 {
2188 };
2190 /* Define the register numbers to be used in Dwarf debugging information.
2191 The SVR4 reference port C compiler uses the following register numbers
2192 in its Dwarf output code:
2193 0 for %eax (gcc regno = 0)
2194 1 for %ecx (gcc regno = 2)
2195 2 for %edx (gcc regno = 1)
2196 3 for %ebx (gcc regno = 3)
2197 4 for %esp (gcc regno = 7)
2198 5 for %ebp (gcc regno = 6)
2199 6 for %esi (gcc regno = 4)
2200 7 for %edi (gcc regno = 5)
2201 The following three DWARF register numbers are never generated by
2202 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2203 believes these numbers have these meanings.
2204 8 for %eip (no gcc equivalent)
2205 9 for %eflags (gcc regno = 17)
2206 10 for %trapno (no gcc equivalent)
2207 It is not at all clear how we should number the FP stack registers
2208 for the x86 architecture. If the version of SDB on x86/svr4 were
2209 a bit less brain dead with respect to floating-point then we would
2210 have a precedent to follow with respect to DWARF register numbers
2211 for x86 FP registers, but the SDB on x86/svr4 is so completely
2212 broken with respect to FP registers that it is hardly worth thinking
2213 of it as something to strive for compatibility with.
2214 The version of x86/svr4 SDB I have at the moment does (partially)
2215 seem to believe that DWARF register number 11 is associated with
2216 the x86 register %st(0), but that's about all. Higher DWARF
2217 register numbers don't seem to be associated with anything in
2218 particular, and even for DWARF regno 11, SDB only seems to under-
2219 stand that it should say that a variable lives in %st(0) (when
2220 asked via an `=' command) if we said it was in DWARF regno 11,
2221 but SDB still prints garbage when asked for the value of the
2222 variable in question (via a `/' command).
2223 (Also note that the labels SDB prints for various FP stack regs
2224 when doing an `x' command are all wrong.)
2225 Note that these problems generally don't affect the native SVR4
2226 C compiler because it doesn't allow the use of -O with -g and
2227 because when it is *not* optimizing, it allocates a memory
2228 location for each floating-point variable, and the memory
2229 location is what gets described in the DWARF AT_location
2230 attribute for the variable in question.
2231 Regardless of the severe mental illness of the x86/svr4 SDB, we
2232 do something sensible here and we use the following DWARF
2233 register numbers. Note that these are all stack-top-relative
2234 numbers.
2235 11 for %st(0) (gcc regno = 8)
2236 12 for %st(1) (gcc regno = 9)
2237 13 for %st(2) (gcc regno = 10)
2238 14 for %st(3) (gcc regno = 11)
2239 15 for %st(4) (gcc regno = 12)
2240 16 for %st(5) (gcc regno = 13)
2241 17 for %st(6) (gcc regno = 14)
2242 18 for %st(7) (gcc regno = 15)
2243 */
2245 {
2257 };
2259 /* Define parameter passing and return registers. */
2262 {
2264 };
2267 {
2269 };
2272 {
2274 };
2276 /* Additional registers that are clobbered by SYSV calls. */
2279 {
2284 };
2286 /* Define the structure for the machine field in struct function. */
2291 rtx rtl;
2293 };
2295 /* Structure describing stack frame layout.
2296 Stack grows downward:
2298 [arguments]
2299 <- ARG_POINTER
2300 saved pc
2302 saved static chain if ix86_static_chain_on_stack
2304 saved frame pointer if frame_pointer_needed
2305 <- HARD_FRAME_POINTER
2306 [saved regs]
2307 <- regs_save_offset
2308 [padding0]
2310 [saved SSE regs]
2311 <- sse_regs_save_offset
2312 [padding1] |
2313 | <- FRAME_POINTER
2314 [va_arg registers] |
2315 |
2316 [frame] |
2317 |
2318 [padding2] | = to_allocate
2319 <- STACK_POINTER
2320 */
2321 struct ix86_frame
2322 {
2329 /* The offsets relative to ARG_POINTER. */
2330 HOST_WIDE_INT frame_pointer_offset;
2331 HOST_WIDE_INT hard_frame_pointer_offset;
2332 HOST_WIDE_INT stack_pointer_offset;
2333 HOST_WIDE_INT hfp_save_offset;
2334 HOST_WIDE_INT reg_save_offset;
2335 HOST_WIDE_INT sse_reg_save_offset;
2337 /* When save_regs_using_mov is set, emit prologue using
2338 move instead of push instructions. */
2340 };
2342 /* Which cpu are we scheduling for. */
2345 /* Which cpu are we optimizing for. */
2348 /* Which instruction set architecture to use. */
2351 /* True if processor has SSE prefetch instruction. */
2354 /* -mstackrealign option */
2371 /* Preferred alignment for stack boundary in bits. */
2374 /* Alignment for incoming stack boundary in bits specified at
2375 command line. */
2378 /* Default alignment for incoming stack boundary in bits. */
2381 /* Alignment for incoming stack boundary in bits. */
2384 /* Calling abi specific va_list type nodes. */
2388 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2392 /* Fence to use after loop using movnt. */
2393 tree x86_mfence;
2395 /* Register class used for passing given 64bit part of the argument.
2396 These represent classes as documented by the PS ABI, with the exception
2397 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2398 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2400 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2401 whenever possible (upper half does contain padding). */
2402 enum x86_64_reg_class
2403 {
2404 X86_64_NO_CLASS,
2405 X86_64_INTEGER_CLASS,
2406 X86_64_INTEGERSI_CLASS,
2407 X86_64_SSE_CLASS,
2408 X86_64_SSESF_CLASS,
2409 X86_64_SSEDF_CLASS,
2410 X86_64_SSEUP_CLASS,
2411 X86_64_X87_CLASS,
2412 X86_64_X87UP_CLASS,
2413 X86_64_COMPLEX_X87_CLASS,
2414 X86_64_MEMORY_CLASS
2415 };
2417 #define MAX_CLASSES 8
2419 /* Table of constants used by fldpi, fldln2, etc.... */
2423 \f
2428 const_tree);
2440 enum ix86_function_specific_strings
2441 {
2442 IX86_FUNCTION_SPECIFIC_ARCH,
2443 IX86_FUNCTION_SPECIFIC_TUNE,
2444 IX86_FUNCTION_SPECIFIC_MAX
2445 };
2466 \f
2467 #ifndef SUBTARGET32_DEFAULT_CPU
2469 #endif
2471 /* Whether -mtune= or -march= were specified */
2475 /* Vectorization library interface and handlers. */
2481 /* Processor target table, indexed by processor number */
2482 struct ptt
2483 {
2491 };
2493 /* This table must be in sync with enum processor_type in i386.h. */
2495 {
2522 };
2523 \f
2524 static unsigned int
2526 {
2529 /* vzeroupper instructions are inserted immediately after reload to
2530 account for possible spills from 256bit registers. The pass
2531 reuses mode switching infrastructure by re-running mode insertion
2532 pass, so disable entities that have already been processed. */
2538 /* Call optimize_mode_switching. */
2541 }
2546 {
2556 };
2559 {
2563 {}
2565 /* opt_pass methods: */
2567 {
2569 }
2572 {
2574 }
2580 rtl_opt_pass *
2582 {
2584 }
2586 /* Return true if a red-zone is in use. */
2590 {
2592 }
2593 \f
2594 /* Return a string that documents the current -m options. The caller is
2595 responsible for freeing the string. */
2601 {
2602 struct ix86_target_opts
2603 {
2606 };
2608 /* This table is ordered so that options like -msse4.2 that imply
2609 preceding options while match those first. */
2611 {
2664 };
2666 /* Flag options. */
2668 {
2697 };
2714 /* Add -march= option. */
2716 {
2719 }
2721 /* Add -mtune= option. */
2723 {
2726 }
2728 /* Add -m32/-m64/-mx32. */
2730 {
2733 else
2735 isa &= ~ (OPTION_MASK_ISA_64BIT
2736 | OPTION_MASK_ABI_64
2738 }
2739 else
2743 /* Pick out the options in isa options. */
2745 {
2747 {
2750 }
2751 }
2754 {
2757 isa);
2758 }
2760 /* Add flag options. */
2762 {
2764 {
2767 }
2768 }
2771 {
2774 }
2776 /* Add -fpmath= option. */
2778 {
2781 {
2796 }
2797 }
2799 /* Any options? */
2805 /* Size the string. */
2809 {
2814 }
2816 /* Build the string. */
2821 {
2828 {
2830 line_len++;
2833 {
2837 }
2838 }
2842 {
2846 }
2847 }
2853 }
2855 /* Return true, if profiling code should be emitted before
2856 prologue. Otherwise it returns false.
2857 Note: For x86 with "hotfix" it is sorried. */
2858 static bool
2860 {
2862 }
2864 /* Function that is callable from the debugger to print the current
2865 options. */
2866 void ATTRIBUTE_UNUSED
2868 {
2874 {
2877 }
2878 else
2882 }
2885 #define DEF_ENUM
2886 #define DEF_ALG(alg, name) #name,
2888 #undef DEF_ENUM
2889 #undef DEF_ALG
2890 };
2892 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2893 The string is of the following form (or comma separated list of it):
2895 strategy_alg:max_size:[align|noalign]
2897 where the full size range for the strategy is either [0, max_size] or
2898 [min_size, max_size], in which min_size is the max_size + 1 of the
2899 preceding range. The last size range must have max_size == -1.
2901 Examples:
2903 1.
2904 -mmemcpy-strategy=libcall:-1:noalign
2906 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2909 2.
2910 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2912 This is to tell the compiler to use the following strategy for memset
2913 1) when the expected size is between [1, 16], use rep_8byte strategy;
2914 2) when the size is between [17, 2048], use vector_loop;
2915 3) when the size is > 2048, use libcall. */
2917 struct stringop_size_range
2918 {
2920 stringop_alg alg;
2922 };
2924 static void
2926 {
2934 else
2939 do
2940 {
2950 {
2954 }
2957 {
2961 }
2968 {
2970 alg_name,
2973 }
2981 else
2982 {
2986 }
2987 n++;
2989 }
2993 {
2998 }
3001 {
3005 }
3007 /* Now override the default algs array. */
3009 {
3015 }
3016 }
3018 \f
3019 /* parse -mtune-ctrl= option. When DUMP is true,
3020 print the features that are explicitly set. */
3022 static void
3024 {
3032 do
3033 {
3040 {
3041 curr_feature_string++;
3043 }
3045 {
3047 {
3053 }
3054 }
3059 }
3062 }
3064 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3065 processor type. */
3067 static void
3069 {
3074 {
3077 else
3079 }
3082 {
3087 }
3090 }
3093 /* Override various settings based on options. If MAIN_ARGS_P, the
3094 options are from the command line, otherwise they are from
3095 attributes. */
3097 static void
3101 {
3109 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3110 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3111 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3112 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3113 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3114 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3115 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3116 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3117 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3118 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3119 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3120 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3121 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3122 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3123 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3124 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3125 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3126 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3127 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3128 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3129 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3130 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3131 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3132 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3133 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3134 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3135 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3136 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3137 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3138 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3139 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3140 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3141 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3142 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3143 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3144 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3145 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3146 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3147 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3148 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3149 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3150 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3151 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3152 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3153 #define PTA_MPX (HOST_WIDE_INT_1 << 44)
3154 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3155 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3156 #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
3157 #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
3158 #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
3159 #define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
3160 #define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
3161 #define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
3162 #define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53)
3163 #define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54)
3164 #define PTA_CLWB (HOST_WIDE_INT_1 << 55)
3165 #define PTA_PCOMMIT (HOST_WIDE_INT_1 << 56)
3167 #define PTA_CORE2 \
3168 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3169 | PTA_CX16 | PTA_FXSR)
3170 #define PTA_NEHALEM \
3171 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3172 #define PTA_WESTMERE \
3173 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3174 #define PTA_SANDYBRIDGE \
3175 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3176 #define PTA_IVYBRIDGE \
3177 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3178 #define PTA_HASWELL \
3179 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3180 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3181 #define PTA_BROADWELL \
3182 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3183 #define PTA_KNL \
3184 (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
3185 #define PTA_BONNELL \
3186 (PTA_CORE2 | PTA_MOVBE)
3187 #define PTA_SILVERMONT \
3188 (PTA_WESTMERE | PTA_MOVBE)
3190 /* if this reaches 64, need to widen struct pta flags below */
3192 static struct pta
3193 {
3198 }
3200 {
3234 PTA_SANDYBRIDGE},
3236 PTA_SANDYBRIDGE},
3238 PTA_IVYBRIDGE},
3240 PTA_IVYBRIDGE},
3332 PTA_64BIT
3334 };
3336 /* -mrecip options. */
3337 static struct
3338 {
3341 }
3343 {
3350 };
3354 /* Set up prefix/suffix so the error messages refer to either the command
3355 line argument, or the attribute(target). */
3357 {
3361 }
3362 else
3363 {
3367 }
3369 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3370 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3373 #ifdef TARGET_BI_ARCH
3374 else
3375 {
3376 #if TARGET_BI_ARCH == 1
3377 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3378 is on and OPTION_MASK_ABI_X32 is off. We turn off
3379 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3380 -mx32. */
3383 #else
3384 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3385 on and OPTION_MASK_ABI_64 is off. We turn off
3386 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3387 -m64 or OPTION_MASK_CODE16 is turned on by -m16. */
3391 #endif
3392 }
3393 #endif
3396 {
3397 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3398 OPTION_MASK_ABI_64 for TARGET_X32. */
3401 }
3404 | OPTION_MASK_ABI_X32
3407 {
3408 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3409 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3412 }
3414 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3415 SUBTARGET_OVERRIDE_OPTIONS;
3416 #endif
3418 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3419 SUBSUBTARGET_OVERRIDE_OPTIONS;
3420 #endif
3422 /* -fPIC is the default for x86_64. */
3426 /* Need to check -mtune=generic first. */
3428 {
3429 /* As special support for cross compilers we read -mtune=native
3430 as -mtune=generic. With native compilers we won't see the
3431 -mtune=native, as it was changed by the driver. */
3433 {
3435 }
3440 }
3441 else
3442 {
3446 {
3447 opts->x_ix86_tune_string
3450 }
3452 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3453 or defaulted. We need to use a sensible tune option. */
3455 {
3457 }
3458 }
3462 {
3463 /* rep; movq isn't available in 32-bit code. */
3466 }
3469 opts->x_ix86_arch_string
3472 else
3476 {
3484 }
3485 else
3492 /* For targets using ms ABI enable ms-extensions, if not
3493 explicit turned off. For non-ms ABI we turn off this
3494 option. */
3499 {
3501 {
3545 {
3548 }
3556 }
3557 }
3558 else
3559 {
3560 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3561 use of rip-relative addressing. This eliminates fixups that
3562 would otherwise be needed if this object is to be placed in a
3563 DLL, and is essentially just as efficient as direct addressing. */
3569 else
3571 }
3573 {
3576 }
3584 {
3587 /* Default cpu tuning to the architecture. */
3765 }
3789 {
3793 {
3795 {
3797 {
3805 }
3806 else
3809 }
3810 }
3811 /* Intel CPUs have always interpreted SSE prefetch instructions as
3812 NOPs; so, we can enable SSE prefetch instructions even when
3813 -mtune (rather than -march) points us to a processor that has them.
3814 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3815 higher processors. */
3820 }
3828 #ifndef USE_IX86_FRAME_POINTER
3829 #define USE_IX86_FRAME_POINTER 0
3830 #endif
3832 #ifndef USE_X86_64_FRAME_POINTER
3833 #define USE_X86_64_FRAME_POINTER 0
3834 #endif
3836 /* Set the default values for switches whose default depends on TARGET_64BIT
3837 in case they weren't overwritten by command line options. */
3839 {
3847 opts->x_flag_unwind_tables
3851 }
3852 else
3853 {
3855 opts->x_flag_omit_frame_pointer
3861 }
3866 else
3869 /* Arrange to set up i386_stack_locals for all functions. */
3872 /* Validate -mregparm= value. */
3874 {
3878 {
3882 }
3883 }
3887 /* Default align_* from the processor table. */
3889 {
3892 }
3894 {
3897 }
3899 {
3901 }
3903 /* Provide default for -mbranch-cost= value. */
3908 {
3909 opts->x_target_flags
3912 /* Enable by default the SSE and MMX builtins. Do allow the user to
3913 explicitly disable any of these. In particular, disabling SSE and
3914 MMX for kernel code is extremely useful. */
3916 opts->x_ix86_isa_flags
3923 }
3924 else
3925 {
3926 opts->x_target_flags
3930 opts->x_ix86_isa_flags
3933 /* i386 ABI does not specify red zone. It still makes sense to use it
3934 when programmer takes care to stack from being destroyed. */
3937 }
3939 /* Keep nonleaf frame pointers. */
3945 /* If we're doing fast math, we don't care about comparison order
3946 wrt NaNs. This lets us use a shorter comparison sequence. */
3950 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3951 since the insns won't need emulation. */
3955 /* Likewise, if the target doesn't have a 387, or we've specified
3956 software floating point, don't use 387 inline intrinsics. */
3960 /* Turn on MMX builtins for -msse. */
3962 opts->x_ix86_isa_flags
3965 /* Enable SSE prefetch. */
3970 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
3973 opts->x_ix86_isa_flags
3976 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3979 opts->x_ix86_isa_flags
3982 /* Enable lzcnt instruction for -mabm. */
3984 opts->x_ix86_isa_flags
3987 /* Validate -mpreferred-stack-boundary= value or default it to
3988 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3991 {
3998 {
4002 else
4005 }
4006 else
4007 ix86_preferred_stack_boundary
4009 }
4011 /* Set the default value for -mstackrealign. */
4017 /* Validate -mincoming-stack-boundary= value or default it to
4018 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
4021 {
4028 else
4029 {
4030 ix86_user_incoming_stack_boundary
4032 ix86_incoming_stack_boundary
4034 }
4035 }
4037 #ifndef NO_PROFILE_COUNTERS
4040 #endif
4044 /* Accept -msseregparm only if at least SSE support is enabled. */
4050 {
4052 {
4054 {
4057 }
4060 {
4063 }
4064 }
4065 }
4066 /* For all chips supporting SSE2, -mfpmath=sse performs better than
4067 fpmath=387. The second is however default at many targets since the
4068 extra 80bit precision of temporaries is considered to be part of ABI.
4069 Overwrite the default at least for -ffast-math.
4070 TODO: -mfpmath=both seems to produce same performing code with bit
4071 smaller binaries. It is however not clear if register allocation is
4072 ready for this setting.
4073 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
4074 codegen. We may switch to 387 with -ffast-math for size optimized
4075 functions. */
4079 else
4082 /* If the i387 is disabled, then do not return values in it. */
4086 /* Use external vectorized library in vectorizing intrinsics. */
4089 {
4100 }
4107 /* If stack probes are required, the space used for large function
4108 arguments on the stack must also be probed, so enable
4109 -maccumulate-outgoing-args so this happens in the prologue. */
4112 {
4117 }
4119 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4120 {
4126 }
4128 /* When scheduling description is not available, disable scheduler pass
4129 so it won't slow down the compilation and make x87 code slower. */
4150 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4152 && HAVE_prefetch
4157 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4158 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4163 {
4166 {
4168 ix86_gen_tls_local_dynamic_base_64
4170 }
4171 else
4172 {
4174 ix86_gen_tls_local_dynamic_base_64
4176 }
4177 }
4178 else
4182 {
4192 }
4193 else
4194 {
4204 }
4206 #ifdef USE_IX86_CLD
4207 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4210 #endif
4213 {
4218 }
4220 {
4224 }
4226 {
4227 #if defined(PROFILE_BEFORE_PROLOGUE)
4229 #else
4231 #endif
4232 }
4234 /* When not opts->x_optimize for size, enable vzeroupper optimization for
4235 TARGET_AVX with -fexpensive-optimizations and split 32-byte
4236 AVX unaligned load/store. */
4238 {
4248 /* Enable 128-bit AVX instruction generation
4249 for the auto-vectorizer. */
4253 }
4256 {
4263 {
4266 {
4268 q++;
4269 }
4270 else
4275 else
4276 {
4279 {
4282 }
4285 {
4289 }
4290 }
4295 else
4297 }
4298 }
4305 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4306 for 64-bit Bionic. */
4311 ? MASK_LONG_DOUBLE_128
4314 /* Only one of them can be active. */
4318 /* Save the initial options in case the user does function specific
4319 options. */
4321 target_option_default_node = target_option_current_node
4324 /* Handle stack protector */
4326 opts->x_ix86_stack_protector_guard
4329 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4331 {
4335 }
4338 {
4342 }
4343 }
4345 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4347 static void
4349 {
4351 struct register_pass_info insert_vzeroupper_info
4354 };
4359 /* This needs to be done at start up. It's convenient to do it here. */
4361 }
4363 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
4366 {
4370 }
4372 /* Update register usage after having seen the compiler flags. */
4374 static void
4376 {
4380 /* The PIC register, if it exists, is fixed. */
4385 /* For 32-bit targets, squash the REX registers. */
4387 {
4394 }
4396 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4404 {
4405 /* Set/reset conditionally defined registers from
4406 CALL_USED_REGISTERS initializer. */
4410 /* Calculate registers of CLOBBERED_REGS register set
4411 as call used registers from GENERAL_REGS register set. */
4415 }
4417 /* If MMX is disabled, squash the registers. */
4423 /* If SSE is disabled, squash the registers. */
4429 /* If the FPU is disabled, squash the registers. */
4435 /* If AVX512F is disabled, squash the registers. */
4437 {
4443 }
4445 /* If MPX is disabled, squash the registers. */
4449 }
4451 \f
4452 /* Save the current options */
4454 static void
4457 {
4492 /* The fields are char but the variables are not; make sure the
4493 values fit in the fields. */
4498 }
4500 /* Restore the current options */
4502 static void
4505 {
4511 /* We don't change -fPIC. */
4548 /* Recreate the arch feature tests if the arch changed */
4550 {
4555 }
4557 /* Recreate the tune optimization tests */
4560 }
4562 /* Print the current options */
4564 static void
4567 {
4585 {
4588 }
4589 }
4591 \f
4592 /* Inner function to process the attribute((target(...))), take an argument and
4593 set the current options from the argument. If we have a list, recursively go
4594 over the list. */
4596 static bool
4601 {
4605 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4606 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4607 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4608 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4609 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4611 enum ix86_opt_type
4612 {
4613 ix86_opt_unknown,
4614 ix86_opt_yes,
4615 ix86_opt_no,
4616 ix86_opt_str,
4617 ix86_opt_enum,
4618 ix86_opt_isa
4619 };
4621 static const struct
4622 {
4629 /* isa options */
4682 /* enum options */
4685 /* string options */
4689 /* flag options */
4691 OPT_mcld,
4692 MASK_CLD),
4695 OPT_mfancy_math_387,
4696 MASK_NO_FANCY_MATH_387),
4699 OPT_mieee_fp,
4700 MASK_IEEE_FP),
4703 OPT_minline_all_stringops,
4704 MASK_INLINE_ALL_STRINGOPS),
4707 OPT_minline_stringops_dynamically,
4708 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4711 OPT_mno_align_stringops,
4712 MASK_NO_ALIGN_STRINGOPS),
4715 OPT_mrecip,
4716 MASK_RECIP),
4718 };
4720 /* If this is a list, recurse to get the options. */
4722 {
4729 enum_opts_set))
4733 }
4736 {
4739 }
4741 /* Handle multiple arguments separated by commas. */
4745 {
4759 {
4763 }
4764 else
4765 {
4768 }
4770 /* Recognize no-xxx. */
4772 {
4776 }
4777 else
4780 /* Find the option. */
4784 {
4792 {
4797 }
4798 }
4800 /* Process the option. */
4802 {
4805 }
4808 {
4814 }
4817 {
4823 else
4825 }
4828 {
4830 {
4833 }
4834 else
4836 }
4839 {
4847 global_dc);
4848 else
4849 {
4852 }
4853 }
4855 else
4857 }
4860 }
4862 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4864 tree
4868 {
4883 /* Process each of the options on the chain. */
4888 /* If the changed options are different from the default, rerun
4889 ix86_option_override_internal, and then save the options away.
4890 The string options are are attribute options, and will be undone
4891 when we copy the save structure. */
4897 {
4898 /* If we are using the default tune= or arch=, undo the string assigned,
4899 and use the default. */
4910 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4915 {
4918 }
4920 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4923 /* Add any builtin functions with the new isa if any. */
4926 /* Save the current options unless we are validating options for
4927 #pragma. */
4934 /* Free up memory allocated to hold the strings */
4937 }
4940 }
4942 /* Hook to validate attribute((target("string"))). */
4944 static bool
4947 tree args,
4949 {
4954 /* attribute((target("default"))) does nothing, beyond
4955 affecting multi-versioning. */
4964 /* Get the optimization options of the current function. */
4970 /* Init func_options. */
4978 /* Initialize func_options to the default before its target options can
4979 be set. */
4992 {
4997 }
5000 }
5002 \f
5003 /* Hook to determine if one function can safely inline another. */
5005 static bool
5007 {
5012 /* If callee has no option attributes, then it is ok to inline. */
5016 /* If caller has no option attributes, but callee does then it is not ok to
5017 inline. */
5021 else
5022 {
5026 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
5027 can inline a SSE2 function but a SSE2 function can't inline a SSE4
5028 function. */
5033 /* See if we have the same non-isa options. */
5037 /* See if arch, tune, etc. are the same. */
5050 else
5052 }
5055 }
5057 \f
5058 /* Remember the last target of ix86_set_current_function. */
5061 /* Set target globals to default. */
5063 static void
5065 {
5066 tree old_tree = (ix86_previous_fndecl
5071 {
5079 else
5082 }
5083 }
5085 /* Invalidate ix86_previous_fndecl cache. */
5086 void
5088 {
5091 }
5093 /* Establish appropriate back-end context for processing the function
5094 FNDECL. The argument might be NULL to indicate processing at top
5095 level, outside of any function scope. */
5096 static void
5098 {
5099 /* Only change the context if the function changes. This hook is called
5100 several times in the course of compiling a function, and we don't want to
5101 slow things down too much or call target_reinit when it isn't safe. */
5103 {
5104 tree old_tree = (ix86_previous_fndecl
5108 tree new_tree = (fndecl
5113 ;
5116 {
5121 else
5124 }
5129 }
5130 }
5132 \f
5133 /* Return true if this goes in large data/bss. */
5135 static bool
5137 {
5141 /* Functions are never large data. */
5145 /* Automatic variables are never large data. */
5150 {
5156 }
5157 else
5158 {
5161 /* If this is an incomplete type with size 0, then we can't put it
5162 in data because it might be too big when completed. Also,
5163 int_size_in_bytes returns -1 if size can vary or is larger than
5164 an integer in which case also it is safer to assume that it goes in
5165 large data. */
5168 }
5171 }
5173 /* Switch to the appropriate section for output of DECL.
5174 DECL is either a `VAR_DECL' node or a constant of some sort.
5175 RELOC indicates whether forming the initial value of DECL requires
5176 link-time relocations. */
5181 {
5183 {
5187 {
5221 /* We don't split these for medium model. Place them into
5222 default sections and hope for best. */
5224 }
5226 {
5227 /* We might get called with string constants, but get_named_section
5228 doesn't like them as they are not DECLs. Also, we need to set
5229 flags in that case. */
5233 }
5234 }
5236 }
5238 /* Select a set of attributes for section NAME based on the properties
5239 of DECL and whether or not RELOC indicates that DECL's initializer
5240 might contain runtime relocations. */
5242 static unsigned int ATTRIBUTE_UNUSED
5244 {
5258 }
5260 /* Build up a unique section name, expressed as a
5261 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5262 RELOC indicates whether the initial value of EXP requires
5263 link-time relocations. */
5265 static void ATTRIBUTE_UNUSED
5267 {
5269 {
5271 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5275 {
5299 /* We don't split these for medium model. Place them into
5300 default sections and hope for best. */
5302 }
5304 {
5311 /* If we're using one_only, then there needs to be a .gnu.linkonce
5312 prefix to the section name. */
5319 }
5320 }
5322 }
5324 #ifdef COMMON_ASM_OP
5325 /* This says how to output assembler code to declare an
5326 uninitialized external linkage data object.
5328 For medium model x86-64 we need to use .largecomm opcode for
5329 large objects. */
5330 void
5334 {
5338 else
5343 }
5344 #endif
5346 /* Utility function for targets to use in implementing
5347 ASM_OUTPUT_ALIGNED_BSS. */
5349 void
5352 {
5356 else
5359 #ifdef ASM_DECLARE_OBJECT_NAME
5362 #else
5363 /* Standard thing is just output label for the object. */
5367 }
5368 \f
5369 /* Decide whether we must probe the stack before any space allocation
5370 on this target. It's essentially TARGET_STACK_PROBE except when
5371 -fstack-check causes the stack to be already probed differently. */
5373 bool
5375 {
5376 /* Do not probe the stack twice if static stack checking is enabled. */
5381 }
5382 \f
5383 /* Decide whether we can make a sibling call to a function. DECL is the
5384 declaration of the function being targeted by the call and EXP is the
5385 CALL_EXPR representing the call. */
5387 static bool
5389 {
5393 /* If we are generating position-independent code, we cannot sibcall
5394 optimize any indirect call, or a direct call to a global function,
5395 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5397 && !TARGET_64BIT
5398 && flag_pic
5402 /* If we need to align the outgoing stack, then sibcalling would
5403 unalign the stack, which may break the called function. */
5409 {
5412 }
5413 else
5414 {
5415 /* We're looking at the CALL_EXPR, we need the type of the function. */
5420 }
5422 /* Check that the return value locations are the same. Like
5423 if we are returning floats on the 80387 register stack, we cannot
5424 make a sibcall from a function that doesn't return a float to a
5425 function that does or, conversely, from a function that does return
5426 a float to a function that doesn't; the necessary stack adjustment
5427 would not be executed. This is also the place we notice
5428 differences in the return value ABI. Note that it is ok for one
5429 of the functions to have void return type as long as the return
5430 value of the other is passed in a register. */
5435 {
5438 }
5440 ;
5445 {
5446 /* The SYSV ABI has more call-clobbered registers;
5447 disallow sibcalls from MS to SYSV. */
5451 }
5452 else
5453 {
5454 /* If this call is indirect, we'll need to be able to use a
5455 call-clobbered register for the address of the target function.
5456 Make sure that all such registers are not used for passing
5457 parameters. Note that DLLIMPORT functions are indirect. */
5460 {
5462 {
5463 /* ??? Need to count the actual number of registers to be used,
5464 not the possible number of registers. Fix later. */
5466 }
5467 }
5468 }
5470 /* Otherwise okay. That also includes certain types of indirect calls. */
5472 }
5474 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5475 and "sseregparm" calling convention attributes;
5476 arguments as in struct attribute_spec.handler. */
5478 static tree
5480 tree args,
5483 {
5488 {
5490 name);
5493 }
5495 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5497 {
5498 tree cst;
5501 {
5503 }
5506 {
5508 }
5512 {
5515 name);
5517 }
5519 {
5523 }
5526 }
5529 {
5530 /* Do not warn when emulating the MS ABI. */
5535 name);
5538 }
5540 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5542 {
5544 {
5546 }
5548 {
5550 }
5552 {
5554 }
5556 {
5558 }
5559 }
5561 /* Can combine stdcall with fastcall (redundant), regparm and
5562 sseregparm. */
5564 {
5566 {
5568 }
5570 {
5572 }
5574 {
5576 }
5577 }
5579 /* Can combine cdecl with regparm and sseregparm. */
5581 {
5583 {
5585 }
5587 {
5589 }
5591 {
5593 }
5594 }
5596 {
5599 name);
5601 {
5603 }
5605 {
5607 }
5609 {
5611 }
5612 }
5614 /* Can combine sseregparm with all attributes. */
5617 }
5619 /* The transactional memory builtins are implicitly regparm or fastcall
5620 depending on the ABI. Override the generic do-nothing attribute that
5621 these builtins were declared with, and replace it with one of the two
5622 attributes that we expect elsewhere. */
5624 static tree
5627 {
5628 tree alt;
5630 /* In no case do we want to add the placeholder attribute. */
5633 /* The 64-bit ABI is unchanged for transactional memory. */
5637 /* ??? Is there a better way to validate 32-bit windows? We have
5638 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5641 else
5642 {
5645 }
5649 }
5651 /* This function determines from TYPE the calling-convention. */
5653 unsigned int
5655 {
5658 tree attrs;
5665 {
5675 /* Regparam isn't allowed for thiscall and fastcall. */
5677 {
5682 }
5686 }
5693 || is_stdarg
5699 }
5701 /* Return 0 if the attributes for two types are incompatible, 1 if they
5702 are compatible, and 2 if they are nearly compatible (which causes a
5703 warning to be generated). */
5705 static int
5707 {
5723 }
5724 \f
5725 /* Return the regparm value for a function with the indicated TYPE and DECL.
5726 DECL may be NULL when calling function indirectly
5727 or considering a libcall. */
5729 static int
5731 {
5732 tree attr;
5743 {
5746 {
5749 }
5750 }
5756 /* Use register calling convention for local functions when possible. */
5759 /* Caller and callee must agree on the calling convention, so
5760 checking here just optimize means that with
5761 __attribute__((optimize (...))) caller could use regparm convention
5762 and callee not, or vice versa. Instead look at whether the callee
5763 is optimized or not. */
5766 {
5767 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5770 {
5773 /* Make sure no regparm register is taken by a
5774 fixed register variable. */
5779 /* We don't want to use regparm(3) for nested functions as
5780 these use a static chain pointer in the third argument. */
5784 /* In 32-bit mode save a register for the split stack. */
5788 /* Each fixed register usage increases register pressure,
5789 so less registers should be used for argument passing.
5790 This functionality can be overriden by an explicit
5791 regparm value. */
5794 globals++;
5796 local_regparm
5801 }
5802 }
5805 }
5807 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5808 DFmode (2) arguments in SSE registers for a function with the
5809 indicated TYPE and DECL. DECL may be NULL when calling function
5810 indirectly or considering a libcall. Otherwise return 0. */
5812 static int
5814 {
5817 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5818 by the sseregparm attribute. */
5821 {
5823 {
5825 {
5829 else
5832 }
5834 }
5837 }
5839 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5840 (and DFmode for SSE2) arguments in SSE registers. */
5843 {
5844 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5848 }
5851 }
5853 /* Return true if EAX is live at the start of the function. Used by
5854 ix86_expand_prologue to determine if we need special help before
5855 calling allocate_stack_worker. */
5857 static bool
5859 {
5860 /* Cheat. Don't bother working forward from ix86_function_regparm
5861 to the function type to whether an actual argument is located in
5862 eax. Instead just look at cfg info, which is still close enough
5863 to correct at this point. This gives false positives for broken
5864 functions that might use uninitialized data that happens to be
5865 allocated in eax, but who cares? */
5867 }
5869 static bool
5871 {
5872 tree attr;
5875 {
5881 /* For 32-bit MS-ABI the default is to keep aggregate
5882 return pointer. */
5885 }
5887 }
5889 /* Value is the number of bytes of arguments automatically
5890 popped when returning from a subroutine call.
5891 FUNDECL is the declaration node of the function (as a tree),
5892 FUNTYPE is the data type of the function (as a tree),
5893 or for a library call it is an identifier node for the subroutine name.
5894 SIZE is the number of bytes of arguments passed on the stack.
5896 On the 80386, the RTD insn may be used to pop them if the number
5897 of args is fixed, but if the number is variable then the caller
5898 must pop them all. RTD can't be used for library calls now
5899 because the library is compiled with the Unix compiler.
5900 Use of RTD is a selectable option, since it is incompatible with
5901 standard Unix calling sequences. If the option is not selected,
5902 the caller must always pop the args.
5904 The attribute stdcall is equivalent to RTD on a per module basis. */
5906 static int
5908 {
5911 /* None of the 64-bit ABIs pop arguments. */
5922 /* Lose any fake structure return argument if it is passed on the stack. */
5925 {
5929 }
5932 }
5934 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5936 static bool
5938 {
5939 /* Check operand constraints in case hard registers were propagated
5940 into insn pattern. This check prevents combine pass from
5941 generating insn patterns with invalid hard register operands.
5942 These invalid insns can eventually confuse reload to error out
5943 with a spill failure. See also PRs 46829 and 46843. */
5945 {
5954 {
5962 /* For pre-AVX disallow unaligned loads/stores where the
5963 instructions don't support it. */
5967 {
5971 }
5973 /* A unary operator may be accepted by the predicate, but it
5974 is irrelevant for matching constraints. */
5979 {
5987 }
5994 /* Operand has no constraints, anything is OK. */
5999 {
6004 && operands_match_p
6008 {
6011 }
6012 }
6016 }
6017 }
6020 }
6021 \f
6022 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
6024 static unsigned HOST_WIDE_INT
6026 {
6030 }
6031 \f
6032 /* Argument support functions. */
6034 /* Return true when register may be used to pass function parameters. */
6035 bool
6037 {
6042 {
6046 else
6052 }
6058 /* TODO: The function should depend on current function ABI but
6059 builtins.c would need updating then. Therefore we use the
6060 default ABI. */
6062 /* RAX is used as hidden argument to va_arg functions. */
6068 else
6075 }
6077 /* Return if we do not know how to pass TYPE solely in registers. */
6079 static bool
6081 {
6085 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
6086 The layout_type routine is crafty and tries to trick us into passing
6087 currently unsupported vector types on the stack by using TImode. */
6090 }
6092 /* It returns the size, in bytes, of the area reserved for arguments passed
6093 in registers for the function represented by fndecl dependent to the used
6094 abi format. */
6095 int
6097 {
6101 else
6106 }
6108 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
6109 call abi used. */
6110 enum calling_abi
6112 {
6114 {
6117 {
6119 {
6121 {
6124 {
6127 }
6128 }
6130 }
6131 }
6135 }
6137 }
6139 /* We add this as a workaround in order to use libc_has_function
6140 hook in i386.md. */
6141 bool
6143 {
6145 }
6147 static bool
6149 {
6151 {
6155 else
6157 }
6159 }
6161 static enum calling_abi
6163 {
6167 }
6169 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6170 call abi used. */
6171 enum calling_abi
6173 {
6177 }
6179 /* Write the extra assembler code needed to declare a function properly. */
6181 void
6183 tree decl)
6184 {
6188 {
6194 }
6196 #ifdef SUBTARGET_ASM_UNWIND_INIT
6198 #endif
6202 /* Output magic byte marker, if hot-patch attribute is set. */
6204 {
6206 {
6207 /* leaq [%rsp + 0], %rsp */
6210 }
6211 else
6212 {
6213 /* movl.s %edi, %edi
6214 push %ebp
6215 movl.s %esp, %ebp */
6218 }
6219 }
6220 }
6222 /* regclass.c */
6225 /* Implementation of call abi switching target hook. Specific to FNDECL
6226 the specific call register sets are set. See also
6227 ix86_conditional_register_usage for more details. */
6228 void
6230 {
6233 else
6235 }
6237 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6238 expensive re-initialization of init_regs each time we switch function context
6239 since this is needed only during RTL expansion. */
6240 static void
6242 {
6246 }
6248 /* Return 1 if pseudo register should be created and used to hold
6249 GOT address for PIC code. */
6250 static bool
6252 {
6259 }
6261 /* Initialize large model PIC register. */
6263 static void
6265 {
6267 rtx tmp_reg;
6276 label));
6280 }
6282 /* Create and initialize PIC register if required. */
6283 static void
6285 {
6286 edge entry_edge;
6295 {
6298 else
6300 }
6301 else
6302 {
6303 /* If there is future mcount call in the function it is more profitable
6304 to emit SET_GOT into ABI defined REAL_PIC_OFFSET_TABLE_REGNUM. */
6313 }
6321 }
6323 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6324 for a call to a function whose data type is FNTYPE.
6325 For a library call, FNTYPE is 0. */
6327 void
6331 tree fndecl,
6333 {
6339 {
6342 }
6343 else
6344 {
6347 }
6351 /* Set up the number of registers to use for passing arguments. */
6354 {
6356 ? X86_64_REGPARM_MAX
6358 }
6360 {
6363 {
6365 ? X86_64_SSE_REGPARM_MAX
6367 }
6368 }
6376 /* Because type might mismatch in between caller and callee, we need to
6377 use actual type of function for local calls.
6378 FIXME: cgraph_analyze can be told to actually record if function uses
6379 va_start so for local functions maybe_vaarg can be made aggressive
6380 helping K&R code.
6381 FIXME: once typesytem is fixed, we won't need this code anymore. */
6394 {
6395 /* If there are variable arguments, then we won't pass anything
6396 in registers in 32-bit mode. */
6398 {
6407 }
6409 /* Use ecx and edx registers if function has fastcall attribute,
6410 else look for regparm information. */
6412 {
6415 {
6418 }
6420 {
6423 }
6424 else
6426 }
6428 /* Set up the number of SSE registers used for passing SFmode
6429 and DFmode arguments. Warn for mismatching ABI. */
6431 }
6432 }
6434 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6435 But in the case of vector types, it is some vector mode.
6437 When we have only some of our vector isa extensions enabled, then there
6438 are some modes for which vector_mode_supported_p is false. For these
6439 modes, the generic vector support in gcc will choose some non-vector mode
6440 in order to implement the type. By computing the natural mode, we'll
6441 select the proper ABI location for the operand and not depend on whatever
6442 the middle-end decides to do with these vector types.
6444 The midde-end can't deal with the vector types > 16 bytes. In this
6445 case, we return the original mode and warn ABI change if CUM isn't
6446 NULL.
6448 If INT_RETURN is true, warn ABI change if the vector mode isn't
6449 available for function return value. */
6451 static machine_mode
6454 {
6458 {
6461 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6463 {
6468 else
6471 /* Get the mode which has this inner mode and number of units. */
6475 {
6477 {
6482 {
6486 }
6488 {
6492 }
6495 }
6497 {
6502 {
6506 }
6508 {
6512 }
6515 }
6518 {
6523 {
6527 }
6529 {
6533 }
6534 }
6536 {
6541 {
6545 }
6547 {
6551 }
6552 }
6554 }
6557 }
6558 }
6561 }
6563 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6564 this may not agree with the mode that the type system has chosen for the
6565 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6566 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6568 static rtx
6571 {
6572 rtx tmp;
6576 else
6577 {
6581 }
6584 }
6586 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6587 of this code is to classify each 8bytes of incoming argument by the register
6588 class and assign registers accordingly. */
6590 /* Return the union class of CLASS1 and CLASS2.
6591 See the x86-64 PS ABI for details. */
6593 static enum x86_64_reg_class
6595 {
6596 /* Rule #1: If both classes are equal, this is the resulting class. */
6600 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6601 the other class. */
6607 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6611 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6619 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6620 MEMORY is used. */
6629 /* Rule #6: Otherwise class SSE is used. */
6631 }
6633 /* Classify the argument of type TYPE and mode MODE.
6634 CLASSES will be filled by the register class used to pass each word
6635 of the operand. The number of words is returned. In case the parameter
6636 should be passed in memory, 0 is returned. As a special case for zero
6637 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6639 BIT_OFFSET is used internally for handling records and specifies offset
6640 of the offset in bits modulo 512 to avoid overflow cases.
6642 See the x86-64 PS ABI for details.
6643 */
6645 static int
6648 {
6649 HOST_WIDE_INT bytes =
6651 int words
6654 /* Variable sized entities are always passed/returned in memory. */
6663 {
6665 tree field;
6668 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6675 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6676 signalize memory class, so handle it as special case. */
6678 {
6681 }
6683 /* Classify each field of record and merge classes. */
6685 {
6687 /* And now merge the fields of structure. */
6689 {
6691 {
6697 /* Bitfields are always classified as integer. Handle them
6698 early, since later code would consider them to be
6699 misaligned integers. */
6701 {
6710 }
6711 else
6712 {
6717 /* Flexible array member is ignored. */
6724 {
6728 {
6731 "the ABI of passing struct with"
6732 " a flexible array member has"
6734 }
6736 }
6738 subclasses,
6748 }
6749 }
6750 }
6754 /* Arrays are handled as small records. */
6755 {
6762 /* The partial classes are now full classes. */
6773 }
6776 /* Unions are similar to RECORD_TYPE but offset is always 0.
6777 */
6779 {
6781 {
6789 bit_offset);
6794 }
6795 }
6800 }
6803 {
6804 /* When size > 16 bytes, if the first one isn't
6805 X86_64_SSE_CLASS or any other ones aren't
6806 X86_64_SSEUP_CLASS, everything should be passed in
6807 memory. */
6814 }
6816 /* Final merger cleanup. */
6818 {
6819 /* If one class is MEMORY, everything should be passed in
6820 memory. */
6824 /* The X86_64_SSEUP_CLASS should be always preceded by
6825 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6829 {
6830 /* The first one should never be X86_64_SSEUP_CLASS. */
6833 }
6835 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6836 everything should be passed in memory. */
6839 {
6842 /* The first one should never be X86_64_X87UP_CLASS. */
6845 {
6848 "the ABI of passing union with long double"
6850 }
6852 }
6853 }
6855 }
6857 /* Compute alignment needed. We align all types to natural boundaries with
6858 exception of XFmode that is aligned to 64bits. */
6860 {
6869 /* Misaligned fields are always returned in memory. */
6872 }
6874 /* for V1xx modes, just use the base mode */
6879 /* Classification of atomic types. */
6881 {
6897 {
6900 /* Analyze last 128 bits only. */
6904 {
6907 }
6909 {
6912 }
6914 {
6918 }
6920 {
6923 }
6924 else
6926 }
6933 /* OImode shouldn't be used directly. */
6940 else
6958 else
6959 {
6963 {
6966 "the ABI of passing structure with complex float"
6968 }
6971 }
6980 /* This modes is larger than 16 bytes. */
7038 else
7042 }
7043 }
7045 /* Examine the argument and return set number of register required in each
7046 class. Return true iff parameter should be passed in memory. */
7048 static bool
7051 {
7062 {
7083 }
7086 }
7088 /* Construct container for the argument used by GCC interface. See
7089 FUNCTION_ARG for the detailed description. */
7091 static rtx
7095 {
7096 /* The following variables hold the static issued_error state. */
7101 machine_mode tmpmode;
7110 rtx ret;
7121 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
7122 some less clueful developer tries to use floating-point anyway. */
7124 {
7126 {
7128 {
7131 }
7132 }
7134 {
7137 }
7139 }
7141 /* Likewise, error if the ABI requires us to return values in the
7142 x87 registers and the user specified -mno-80387. */
7148 {
7150 {
7153 }
7155 }
7157 /* First construct simple cases. Avoid SCmode, since we want to use
7158 single register to pass this type. */
7161 {
7176 /* Zero sized array, struct or class. */
7180 }
7219 /* Otherwise figure out the entries of the PARALLEL. */
7221 {
7225 {
7230 /* Merge TImodes on aligned occasions here too. */
7232 tmpmode
7236 else
7238 /* We've requested 24 bytes we
7239 don't have mode for. Use DImode. */
7246 intreg++;
7254 sse_regno++;
7262 sse_regno++;
7267 {
7273 {
7275 i++;
7276 }
7277 else
7302 }
7308 sse_regno++;
7312 }
7313 }
7315 /* Empty aligned struct, union or class. */
7323 }
7325 /* Update the data in CUM to advance over an argument of mode MODE
7326 and data type TYPE. (TYPE is null for libcalls where that information
7327 may not be available.)
7329 Return a number of integer regsiters advanced over. */
7331 static int
7334 HOST_WIDE_INT words)
7335 {
7339 {
7346 /* FALLTHRU */
7358 {
7361 }
7365 /* OImode shouldn't be used directly. */
7374 /* FALLTHRU */
7396 {
7401 {
7404 }
7405 }
7415 {
7420 {
7423 }
7424 }
7426 }
7429 }
7431 static int
7434 {
7437 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7444 {
7450 }
7451 else
7452 {
7457 }
7458 }
7460 static int
7462 HOST_WIDE_INT words)
7463 {
7464 /* Otherwise, this should be passed indirect. */
7469 {
7473 }
7475 }
7477 /* Update the data in CUM to advance over an argument of mode MODE and
7478 data type TYPE. (TYPE is null for libcalls where that information
7479 may not be available.) */
7481 static void
7484 {
7491 else
7500 {
7501 /* If we pass bounds in BT then just update remained bounds count. */
7503 {
7506 }
7508 /* Update remained number of bounds to force. */
7515 }
7517 /* The first arg not going to Bounds Tables resets this counter. */
7519 /* For unnamed args we always pass bounds to avoid bounds mess when
7520 passed and received types do not match. If bounds do not follow
7521 unnamed arg, still pretend required number of bounds were passed. */
7523 {
7526 }
7532 else
7535 /* For stdarg we expect bounds to be passed for each value passed
7536 in register. */
7539 /* For pointers passed in memory we expect bounds passed in Bounds
7540 Table. */
7543 }
7545 /* Define where to put the arguments to a function.
7546 Value is zero to push the argument on the stack,
7547 or a hard register in which to store the argument.
7549 MODE is the argument's machine mode.
7550 TYPE is the data type of the argument (as a tree).
7551 This is null for libcalls where that information may
7552 not be available.
7553 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7554 the preceding args and about the function being called.
7555 NAMED is nonzero if this argument is a named parameter
7556 (otherwise it is an extra parameter matching an ellipsis). */
7558 static rtx
7562 {
7563 /* Avoid the AL settings for the Unix64 ABI. */
7568 {
7575 /* FALLTHRU */
7581 {
7584 /* Fastcall allocates the first two DWORD (SImode) or
7585 smaller arguments to ECX and EDX if it isn't an
7586 aggregate type . */
7588 {
7594 /* ECX not EAX is the first allocated register. */
7597 }
7599 }
7608 /* FALLTHRU */
7610 /* In 32bit, we pass TImode in xmm registers. */
7618 {
7622 }
7627 /* OImode and XImode shouldn't be used directly. */
7643 {
7647 }
7657 {
7661 }
7663 }
7666 }
7668 static rtx
7671 {
7672 /* Handle a hidden AL argument containing number of registers
7673 for varargs x86-64 functions. */
7677 ? X86_64_SSE_REGPARM_MAX
7682 {
7698 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7702 }
7708 }
7710 static rtx
7713 HOST_WIDE_INT bytes)
7714 {
7717 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7718 We use value of -2 to specify that current function call is MSABI. */
7722 /* If we've run out of registers, it goes on the stack. */
7728 /* Only floating point modes are passed in anything but integer regs. */
7730 {
7733 else
7734 {
7737 /* Unnamed floating parameters are passed in both the
7738 SSE and integer registers. */
7744 }
7745 }
7746 /* Handle aggregated types passed in register. */
7748 {
7753 }
7756 }
7758 /* Return where to put the arguments to a function.
7759 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7761 MODE is the argument's machine mode. TYPE is the data type of the
7762 argument. It is null for libcalls where that information may not be
7763 available. CUM gives information about the preceding args and about
7764 the function being called. NAMED is nonzero if this argument is a
7765 named parameter (otherwise it is an extra parameter matching an
7766 ellipsis). */
7768 static rtx
7771 {
7775 rtx arg;
7777 /* All pointer bounds argumntas are handled separately here. */
7780 {
7781 /* Return NULL if bounds are forced to go in Bounds Table. */
7784 /* Return the next available bound reg if any. */
7787 /* Return the next special slot number otherwise. */
7788 else
7792 }
7796 else
7800 /* To simplify the code below, represent vector types with a vector mode
7801 even if MMX/SSE are not active. */
7809 else
7813 }
7815 /* A C expression that indicates when an argument must be passed by
7816 reference. If nonzero for an argument, a copy of that argument is
7817 made in memory and a pointer to the argument is passed instead of
7818 the argument itself. The pointer is passed in whatever way is
7819 appropriate for passing a pointer to that type. */
7821 static bool
7824 {
7827 /* See Windows x64 Software Convention. */
7829 {
7832 {
7833 /* Arrays are passed by reference. */
7838 {
7839 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7840 are passed by reference. */
7842 }
7843 }
7845 /* __m128 is passed by reference. */
7851 }
7852 }
7857 }
7859 /* Return true when TYPE should be 128bit aligned for 32bit argument
7860 passing ABI. XXX: This function is obsolete and is only used for
7861 checking psABI compatibility with previous versions of GCC. */
7863 static bool
7865 {
7877 {
7878 /* Walk the aggregates recursively. */
7880 {
7884 {
7885 tree field;
7887 /* Walk all the structure fields. */
7889 {
7893 }
7895 }
7898 /* Just for use if some languages passes arrays by value. */
7905 }
7906 }
7908 }
7910 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7911 XXX: This function is obsolete and is only used for checking psABI
7912 compatibility with previous versions of GCC. */
7914 static unsigned int
7917 {
7918 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7919 natural boundaries. */
7921 {
7922 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7923 make an exception for SSE modes since these require 128bit
7924 alignment.
7926 The handling here differs from field_alignment. ICC aligns MMX
7927 arguments to 4 byte boundaries, while structure fields are aligned
7928 to 8 byte boundaries. */
7930 {
7933 }
7934 else
7935 {
7938 }
7939 }
7943 }
7945 /* Return true when TYPE should be 128bit aligned for 32bit argument
7946 passing ABI. */
7948 static bool
7950 {
7960 {
7961 /* Walk the aggregates recursively. */
7963 {
7967 {
7968 tree field;
7970 /* Walk all the structure fields. */
7972 field;
7974 {
7978 }
7980 }
7983 /* Just for use if some languages passes arrays by value. */
7990 }
7991 }
7992 else
7996 }
7998 /* Gives the alignment boundary, in bits, of an argument with the
7999 specified mode and type. */
8001 static unsigned int
8003 {
8006 {
8007 /* Since the main variant type is used for call, we convert it to
8008 the main variant type. */
8011 }
8012 else
8016 else
8017 {
8022 {
8023 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
8025 {
8028 }
8034 }
8037 && !warned
8039 saved_align))
8040 {
8043 "The ABI for passing parameters with %d-byte"
8046 }
8047 }
8050 }
8052 /* Return true if N is a possible register number of function value. */
8054 static bool
8056 {
8058 {
8070 /* Complex values are returned in %st(0)/%st(1) pair. */
8073 /* TODO: The function should depend on current function ABI but
8074 builtins.c would need updating then. Therefore we use the
8075 default ABI. */
8080 /* Complex values are returned in %xmm0/%xmm1 pair. */
8089 }
8092 }
8094 /* Define how to find the value returned by a function.
8095 VALTYPE is the data type of the value (as a tree).
8096 If the precise function being called is known, FUNC is its FUNCTION_DECL;
8097 otherwise, FUNC is 0. */
8099 static rtx
8102 {
8105 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
8106 we normally prevent this case when mmx is not available. However
8107 some ABIs may require the result to be returned like DImode. */
8111 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
8112 we prevent this case when sse is not available. However some ABIs
8113 may require the result to be returned like integer TImode. */
8118 /* 32-byte vector modes in %ymm0. */
8122 /* 64-byte vector modes in %zmm0. */
8126 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
8129 else
8130 /* Most things go in %eax. */
8133 /* Override FP return register with %xmm0 for local functions when
8134 SSE math is enabled or for functions with sseregparm attribute. */
8136 {
8141 }
8143 /* OImode shouldn't be used directly. */
8147 }
8149 static rtx
8151 const_tree valtype)
8152 {
8153 rtx ret;
8155 /* Handle libcalls, which don't provide a type node. */
8157 {
8161 {
8180 }
8183 }
8185 {
8186 /* Pointers are always returned in word_mode. */
8188 }
8194 /* For zero sized structures, construct_container returns NULL, but we
8195 need to keep rest of compiler happy by returning meaningful value. */
8200 }
8202 static rtx
8204 const_tree valtype)
8205 {
8209 {
8211 {
8230 }
8231 }
8233 }
8235 static rtx
8238 {
8253 else
8255 }
8257 static rtx
8259 {
8265 }
8267 /* Return an RTX representing a place where a function returns
8268 or recieves pointer bounds or NULL if no bounds are returned.
8270 VALTYPE is a data type of a value returned by the function.
8272 FN_DECL_OR_TYPE is a tree node representing FUNCTION_DECL
8273 or FUNCTION_TYPE of the function.
8275 If OUTGOING is false, return a place in which the caller will
8276 see the return value. Otherwise, return a place where a
8277 function returns a value. */
8279 static rtx
8281 const_tree fntype_or_decl ATTRIBUTE_UNUSED,
8283 {
8289 {
8290 bitmap slots;
8292 bitmap_iterator bi;
8300 {
8305 }
8311 }
8312 else
8316 }
8318 /* Pointer function arguments and return values are promoted to
8319 word_mode. */
8321 static machine_mode
8325 {
8327 {
8330 }
8332 for_return);
8333 }
8335 /* Return true if a structure, union or array with MODE containing FIELD
8336 should be accessed using BLKmode. */
8338 static bool
8340 {
8341 /* Union with XFmode must be in BLKmode. */
8345 }
8347 rtx
8349 {
8351 }
8353 /* Return true iff type is returned in memory. */
8355 static bool
8357 {
8358 #ifdef SUBTARGET_RETURN_IN_MEMORY
8360 #else
8362 HOST_WIDE_INT size;
8368 {
8370 {
8373 /* __m128 is returned in xmm0. */
8382 /* Otherwise, the size must be exactly in [1248]. */
8384 }
8385 else
8386 {
8391 }
8392 }
8393 else
8394 {
8404 {
8405 /* User-created vectors small enough to fit in EAX. */
8409 /* Unless ABI prescibes otherwise,
8410 MMX/3dNow values are returned in MM0 if available. */
8415 /* SSE values are returned in XMM0 if available. */
8419 /* AVX values are returned in YMM0 if available. */
8423 /* AVX512F values are returned in ZMM0 if available. */
8426 }
8434 /* OImode shouldn't be used directly. */
8438 }
8439 #endif
8440 }
8442 \f
8443 /* Create the va_list data type. */
8445 /* Returns the calling convention specific va_list date type.
8446 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8448 static tree
8450 {
8453 /* For i386 we use plain pointer to argument area. */
8463 unsigned_type_node);
8466 unsigned_type_node);
8469 ptr_type_node);
8472 ptr_type_node);
8491 /* The correct type is an array type of one element. */
8493 }
8495 /* Setup the builtin va_list data type and for 64-bit the additional
8496 calling convention specific va_list data types. */
8498 static tree
8500 {
8503 /* Initialize abi specific va_list builtin types. */
8505 {
8506 tree t;
8508 {
8513 }
8514 else
8515 {
8520 }
8522 {
8527 }
8528 else
8529 {
8534 }
8535 }
8538 }
8540 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8542 static void
8544 {
8546 alias_set_type set;
8549 /* GPR size of varargs save area. */
8552 else
8555 /* FPR size of varargs save area. We don't need it if we don't pass
8556 anything in SSE registers. */
8559 else
8573 {
8581 }
8584 {
8585 machine_mode smode;
8587 rtx test;
8589 /* Now emit code to save SSE registers. The AX parameter contains number
8590 of SSE parameter registers used to call this function, though all we
8591 actually check here is the zero/non-zero status. */
8596 label));
8598 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8599 we used movdqa (i.e. TImode) instead? Perhaps even better would
8600 be if we could determine the real mode of the data, via a hook
8601 into pass_stdarg. Ignore all that for now. */
8611 {
8620 }
8623 }
8624 }
8626 static void
8628 {
8632 /* Reset to zero, as there might be a sysv vaarg used
8633 before. */
8638 {
8649 }
8650 }
8652 static void
8655 {
8657 CUMULATIVE_ARGS next_cum;
8658 tree fntype;
8660 /* This argument doesn't appear to be used anymore. Which is good,
8661 because the old code here didn't suppress rtl generation. */
8669 /* For varargs, we do not want to skip the dummy va_dcl argument.
8670 For stdargs, we do want to skip the last named argument. */
8678 else
8680 }
8682 static void
8685 tree type,
8688 {
8690 CUMULATIVE_ARGS next_cum;
8691 tree fntype;
8692 rtx save_area;
8697 /* Do nothing if we use plain pointer to argument area. */
8703 /* For varargs, we do not want to skip the dummy va_dcl argument.
8704 For stdargs, we do want to skip the last named argument. */
8718 {
8723 rtx bounds;
8727 else
8728 {
8729 rtx ldx_addr =
8736 }
8742 bnd_reg++;
8743 }
8744 }
8747 /* Checks if TYPE is of kind va_list char *. */
8749 static bool
8751 {
8752 tree canonic;
8754 /* For 32-bit it is always true. */
8760 }
8762 /* Implement va_start. */
8764 static void
8766 {
8770 tree type;
8771 rtx ovf_rtx;
8775 {
8778 /* When we are splitting the stack, we can't refer to the stack
8779 arguments using internal_arg_pointer, because they may be on
8780 the old stack. The split stack prologue will arrange to
8781 leave a pointer to the old stack arguments in a scratch
8782 register, which we here copy to a pseudo-register. The split
8783 stack prologue can't set the pseudo-register directly because
8784 it (the prologue) runs before any registers have been saved. */
8788 {
8789 rtx reg;
8803 }
8804 }
8806 /* Only 64bit target needs something special. */
8808 {
8811 else
8812 {
8822 /* Store zero bounds for va_list. */
8826 next));
8828 }
8830 }
8839 /* The following should be folded into the MEM_REF offset. */
8849 /* Count number of gp and fp argument registers used. */
8855 {
8861 }
8864 {
8870 }
8872 /* Find the overflow area. */
8876 else
8882 /* Store zero bounds for overflow area pointer. */
8891 {
8892 /* Find the register save area.
8893 Prologue of the function save it right above stack frame. */
8899 /* Store zero bounds for save area pointer. */
8906 }
8907 }
8909 /* Implement va_arg. */
8911 static tree
8914 {
8921 rtx container;
8923 tree ptrtype;
8924 machine_mode nat_mode;
8927 /* Only 64bit target needs something special. */
8951 {
8964 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
8966 {
8969 }
8977 }
8979 /* Pull the value out of the saved registers. */
8984 {
8998 /* In case we are passing structure, verify that it is consecutive block
8999 on the register save area. If not we need to do moves. */
9001 {
9002 /* Verify that all registers are strictly consecutive */
9004 {
9008 {
9013 }
9014 }
9015 else
9016 {
9020 {
9025 }
9026 }
9027 }
9029 {
9032 }
9033 else
9034 {
9037 }
9039 /* First ensure that we fit completely in registers. */
9041 {
9048 }
9050 {
9058 }
9060 /* Compute index to start of area used for integer regs. */
9062 {
9063 /* int_addr = gpr + sav; */
9066 }
9068 {
9069 /* sse_addr = fpr + sav; */
9072 }
9074 {
9078 /* addr = &temp; */
9083 {
9087 tree piece_type;
9088 tree addr_type;
9089 tree daddr_type;
9098 {
9103 }
9107 else
9114 {
9117 }
9118 else
9119 {
9122 }
9129 {
9134 }
9135 else
9136 {
9137 tree copy
9142 }
9144 }
9145 }
9148 {
9152 }
9155 {
9159 }
9164 }
9166 /* ... otherwise out of the overflow area. */
9168 /* When we align parameter on stack for caller, if the parameter
9169 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
9170 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
9171 here with caller. */
9176 /* Care for on-stack alignment if needed. */
9179 else
9180 {
9185 }
9202 }
9203 \f
9204 /* Return true if OPNUM's MEM should be matched
9205 in movabs* patterns. */
9207 bool
9209 {
9221 }
9222 \f
9223 /* Initialize the table of extra 80387 mathematical constants. */
9225 static void
9227 {
9229 {
9235 };
9239 {
9241 /* Ensure each constant is rounded to XFmode precision. */
9244 }
9247 }
9249 /* Return non-zero if the constant is something that
9250 can be loaded with a special instruction. */
9252 int
9254 {
9257 REAL_VALUE_TYPE r;
9269 /* For XFmode constants, try to find a special 80387 instruction when
9270 optimizing for size or on those CPUs that benefit from them. */
9273 {
9282 }
9284 /* Load of the constant -0.0 or -1.0 will be split as
9285 fldz;fchs or fld1;fchs sequence. */
9292 }
9294 /* Return the opcode of the special instruction to be used to load
9295 the constant X. */
9299 {
9301 {
9321 }
9322 }
9324 /* Return the CONST_DOUBLE representing the 80387 constant that is
9325 loaded by the specified special instruction. The argument IDX
9326 matches the return value from standard_80387_constant_p. */
9328 rtx
9330 {
9337 {
9348 }
9351 XFmode);
9352 }
9354 /* Return 1 if X is all 0s and 2 if x is all 1s
9355 in supported SSE/AVX vector mode. */
9357 int
9359 {
9366 {
9387 }
9390 }
9392 /* Return the opcode of the special instruction to be used to load
9393 the constant X. */
9397 {
9399 {
9402 {
9429 }
9439 else
9444 }
9446 }
9448 /* Returns true if OP contains a symbol reference */
9450 bool
9452 {
9461 {
9463 {
9469 }
9473 }
9476 }
9478 /* Return true if it is appropriate to emit `ret' instructions in the
9479 body of a function. Do this only if the epilogue is simple, needing a
9480 couple of insns. Prior to reloading, we can't tell how many registers
9481 must be saved, so return false then. Return false if there is no frame
9482 marker to de-allocate. */
9484 bool
9486 {
9492 /* Don't allow more than 32k pop, since that's all we can do
9493 with one instruction. */
9500 }
9501 \f
9502 /* Value should be nonzero if functions must have frame pointers.
9503 Zero means the frame pointer need not be set up (and parms may
9504 be accessed via the stack pointer) in functions that seem suitable. */
9506 static bool
9508 {
9509 /* If we accessed previous frames, then the generated code expects
9510 to be able to access the saved ebp value in our frame. */
9514 /* Several x86 os'es need a frame pointer for other reasons,
9515 usually pertaining to setjmp. */
9519 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9523 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9524 allocation is 4GB. */
9528 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9529 turns off the frame pointer by default. Turn it back on now if
9530 we've not got a leaf function. */
9540 }
9542 /* Record that the current function accesses previous call frames. */
9544 void
9546 {
9548 }
9549 \f
9550 #ifndef USE_HIDDEN_LINKONCE
9551 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9552 # define USE_HIDDEN_LINKONCE 1
9553 # else
9554 # define USE_HIDDEN_LINKONCE 0
9555 # endif
9556 #endif
9560 /* Fills in the label name that should be used for a pc thunk for
9561 the given register. */
9563 static void
9565 {
9570 else
9572 }
9575 /* This function generates code for -fpic that loads %ebx with
9576 the return address of the caller and then returns. */
9578 static void
9580 {
9585 {
9587 tree decl;
9603 #if TARGET_MACHO
9605 {
9614 }
9615 else
9616 #endif
9618 {
9629 }
9630 else
9631 {
9634 }
9640 /* Make sure unwind info is emitted for the thunk if needed. */
9643 /* Pad stack IP move with 4 instructions (two NOPs count
9644 as one instruction). */
9646 {
9651 }
9662 }
9666 }
9668 /* Emit code for the SET_GOT patterns. */
9672 {
9678 {
9679 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9684 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9685 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9686 an unadorned address. */
9691 }
9696 {
9698 /* We don't need a pic base, we're not producing pic. */
9705 }
9706 else
9707 {
9716 #if TARGET_MACHO
9717 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9718 This is what will be referenced by the Mach-O PIC subsystem. */
9722 /* When we are restoring the pic base at the site of a nonlocal label,
9723 and we decided to emit the pic base above, we will still output a
9724 local label used for calculating the correction offset (even though
9725 the offset will be 0 in that case). */
9729 #endif
9730 }
9736 }
9738 /* Generate an "push" pattern for input ARG. */
9740 static rtx
9742 {
9755 stack_pointer_rtx)),
9756 arg);
9757 }
9759 /* Generate an "pop" pattern for input ARG. */
9761 static rtx
9763 {
9768 arg,
9771 stack_pointer_rtx)));
9772 }
9774 /* Return >= 0 if there is an unused call-clobbered register available
9775 for the entire function. */
9777 static unsigned int
9779 {
9786 {
9788 /* Can't use the same register for both PIC and DRAP. */
9791 else
9796 }
9799 }
9801 /* Return TRUE if we need to save REGNO. */
9803 static bool
9805 {
9808 {
9810 {
9811 /* REAL_PIC_OFFSET_TABLE_REGNUM used by call to
9812 _mcount in prologue. */
9815 }
9822 }
9825 {
9828 {
9834 }
9835 }
9846 }
9848 /* Return number of saved general prupose registers. */
9850 static int
9852 {
9858 nregs ++;
9860 }
9862 /* Return number of saved SSE registrers. */
9864 static int
9866 {
9874 nregs ++;
9876 }
9878 /* Given FROM and TO register numbers, say whether this elimination is
9879 allowed. If stack alignment is needed, we can only replace argument
9880 pointer with hard frame pointer, or replace frame pointer with stack
9881 pointer. Otherwise, frame pointer elimination is automatically
9882 handled and all other eliminations are valid. */
9884 static bool
9886 {
9892 else
9894 }
9896 /* Return the offset between two registers, one to be eliminated, and the other
9897 its replacement, at the start of a routine. */
9899 HOST_WIDE_INT
9901 {
9910 else
9911 {
9919 }
9920 }
9922 /* In a dynamically-aligned function, we can't know the offset from
9923 stack pointer to frame pointer, so we must ensure that setjmp
9924 eliminates fp against the hard fp (%ebp) rather than trying to
9925 index from %esp up to the top of the frame across a gap that is
9926 of unknown (at compile-time) size. */
9927 static rtx
9929 {
9931 }
9933 /* When using -fsplit-stack, the allocation routines set a field in
9934 the TCB to the bottom of the stack plus this much space, measured
9935 in bytes. */
9937 #define SPLIT_STACK_AVAILABLE 256
9939 /* Fill structure ix86_frame about frame of currently computed function. */
9941 static void
9943 {
9945 HOST_WIDE_INT offset;
9948 HOST_WIDE_INT to_allocate;
9953 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
9954 function prologues and leaf. */
9958 {
9961 }
9962 /* preferred_stack_boundary is never updated for call
9963 expanded from tls descriptor. Update it here. We don't update it in
9964 expand stage because according to the comments before
9965 ix86_current_function_calls_tls_descriptor, tls calls may be optimized
9966 away. */
9969 {
9973 }
9982 /* For SEH we have to limit the amount of code movement into the prologue.
9983 At present we do this via a BLOCKAGE, at which point there's very little
9984 scheduling that can be done, which means that there's very little point
9985 in doing anything except PUSHs. */
9989 /* During reload iteration the amount of registers saved can change.
9990 Recompute the value as needed. Do not recompute when amount of registers
9991 didn't change as reload does multiple calls to the function and does not
9992 expect the decision to change within single iteration. */
9995 {
10001 /* The fast prologue uses move instead of push to save registers. This
10002 is significantly longer, but also executes faster as modern hardware
10003 can execute the moves in parallel, but can't do that for push/pop.
10005 Be careful about choosing what prologue to emit: When function takes
10006 many instructions to execute we may use slow version as well as in
10007 case function is known to be outside hot spot (this is known with
10008 feedback only). Weight the size of function by number of registers
10009 to save as it is cheap to use one or two push instructions but very
10010 slow to use many of them. */
10014 || (flag_branch_probabilities
10017 else
10020 }
10022 frame->save_regs_using_mov
10024 /* If static stack checking is enabled and done with probes,
10025 the registers need to be saved before allocating the frame. */
10028 /* Skip return address. */
10031 /* Skip pushed static chain. */
10035 /* Skip saved base pointer. */
10040 /* The traditional frame pointer location is at the top of the frame. */
10043 /* Register save area */
10047 /* On SEH target, registers are pushed just before the frame pointer
10048 location. */
10052 /* Align and set SSE register save area. */
10054 {
10055 /* The only ABI that has saved SSE registers (Win64) also has a
10056 16-byte aligned default stack, and thus we don't need to be
10057 within the re-aligned local stack frame to save them. */
10061 }
10064 /* The re-aligned stack starts here. Values before this point are not
10065 directly comparable with values below this point. In order to make
10066 sure that no value happens to be the same before and after, force
10067 the alignment computation below to add a non-zero value. */
10071 /* Va-arg area */
10075 /* Align start of frame for local function. */
10084 /* Frame pointer points here. */
10089 /* Add outgoing arguments area. Can be skipped if we eliminated
10090 all the function calls as dead code.
10091 Skipping is however impossible when function calls alloca. Alloca
10092 expander assumes that last crtl->outgoing_args_size
10093 of stack frame are unused. */
10097 {
10100 }
10101 else
10104 /* Align stack boundary. Only needed if we're calling another function
10105 or using alloca. */
10110 /* We've reached end of stack frame. */
10113 /* Size prologue needs to allocate. */
10124 {
10130 }
10131 else
10135 /* The SEH frame pointer location is near the bottom of the frame.
10136 This is enforced by the fact that the difference between the
10137 stack pointer and the frame pointer is limited to 240 bytes in
10138 the unwind data structure. */
10140 {
10141 HOST_WIDE_INT diff;
10143 /* If we can leave the frame pointer where it is, do so. Also, returns
10144 the establisher frame for __builtin_frame_address (0). */
10149 {
10150 /* Ideally we'd determine what portion of the local stack frame
10151 (within the constraint of the lowest 240) is most heavily used.
10152 But without that complication, simply bias the frame pointer
10153 by 128 bytes so as to maximize the amount of the local stack
10154 frame that is addressable with 8-bit offsets. */
10156 }
10157 }
10158 }
10160 /* This is semi-inlined memory_address_length, but simplified
10161 since we know that we're always dealing with reg+offset, and
10162 to avoid having to create and discard all that rtl. */
10166 {
10170 {
10171 /* EBP and R13 cannot be encoded without an offset. */
10173 }
10177 /* ESP and R12 must be encoded with a SIB byte. */
10179 len++;
10182 }
10184 /* Return an RTX that points to CFA_OFFSET within the stack frame.
10185 The valid base registers are taken from CFUN->MACHINE->FS. */
10187 static rtx
10189 {
10195 {
10196 /* Choose the base register most likely to allow the most scheduling
10197 opportunities. Generally FP is valid throughout the function,
10198 while DRAP must be reloaded within the epilogue. But choose either
10199 over the SP due to increased encoding size. */
10202 {
10205 }
10207 {
10210 }
10212 {
10215 }
10216 }
10217 else
10218 {
10219 HOST_WIDE_INT toffset;
10222 /* Choose the base register with the smallest address encoding.
10223 With a tie, choose FP > DRAP > SP. */
10225 {
10229 }
10231 {
10235 {
10239 }
10240 }
10242 {
10246 {
10250 }
10251 }
10252 }
10256 }
10258 /* Emit code to save registers in the prologue. */
10260 static void
10262 {
10264 rtx insn;
10268 {
10271 }
10272 }
10274 /* Emit a single register save at CFA - CFA_OFFSET. */
10276 static void
10278 HOST_WIDE_INT cfa_offset)
10279 {
10287 /* For SSE saves, we need to indicate the 128-bit alignment. */
10298 /* When saving registers into a re-aligned local stack frame, avoid
10299 any tricky guessing by dwarf2out. */
10301 {
10305 {
10306 /* A bit of a hack. We force the DRAP register to be saved in
10307 the re-aligned stack frame, which provides us with a copy
10308 of the CFA that will last past the prologue. Install it. */
10314 }
10315 else
10316 {
10317 /* The frame pointer is a stable reference within the
10318 aligned frame. Use it. */
10325 }
10326 }
10328 /* The memory may not be relative to the current CFA register,
10329 which means that we may need to generate a new pattern for
10330 use by the unwind info. */
10332 {
10337 }
10338 }
10340 /* Emit code to save registers using MOV insns.
10341 First register is stored at CFA - CFA_OFFSET. */
10342 static void
10344 {
10349 {
10352 }
10353 }
10355 /* Emit code to save SSE registers using MOV insns.
10356 First register is stored at CFA - CFA_OFFSET. */
10357 static void
10359 {
10364 {
10367 }
10368 }
10372 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
10373 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
10374 Don't add the note if the previously saved value will be left untouched
10375 within stack red-zone till return, as unwinders can find the same value
10376 in the register and on the stack. */
10378 static void
10380 {
10386 {
10389 }
10390 else
10391 queued_cfa_restores
10393 }
10395 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
10397 static void
10399 {
10400 rtx last;
10404 ;
10409 }
10411 /* Expand prologue or epilogue stack adjustment.
10412 The pattern exist to put a dependency on all ebp-based memory accesses.
10413 STYLE should be negative if instructions should be marked as frame related,
10414 zero if %r11 register is live and cannot be freely used and positive
10415 otherwise. */
10417 static void
10420 {
10422 rtx insn;
10429 else
10430 {
10431 rtx tmp;
10432 /* r11 is used by indirect sibcall return as well, set before the
10433 epilogue and used after the epilogue. */
10436 else
10437 {
10441 }
10447 }
10454 {
10455 rtx r;
10465 }
10467 {
10470 {
10474 }
10475 }
10478 {
10483 {
10486 }
10488 {
10491 }
10492 else
10493 {
10494 /* Else there are two possibilities: SP itself, which we set
10495 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10496 taken care of this by hand along the eh_return path. */
10499 }
10503 }
10504 }
10506 /* Find an available register to be used as dynamic realign argument
10507 pointer regsiter. Such a register will be written in prologue and
10508 used in begin of body, so it must not be
10509 1. parameter passing register.
10510 2. GOT pointer.
10511 We reuse static-chain register if it is available. Otherwise, we
10512 use DI for i386 and R13 for x86-64. We chose R13 since it has
10513 shorter encoding.
10515 Return: the regno of chosen register. */
10517 static unsigned int
10519 {
10523 {
10524 /* Use R13 for nested function or function need static chain.
10525 Since function with tail call may use any caller-saved
10526 registers in epilogue, DRAP must not use caller-saved
10527 register in such case. */
10532 }
10533 else
10534 {
10535 /* Use DI for nested function or function need static chain.
10536 Since function with tail call may use any caller-saved
10537 registers in epilogue, DRAP must not use caller-saved
10538 register in such case. */
10542 /* Reuse static chain register if it isn't used for parameter
10543 passing. */
10545 {
10549 }
10551 }
10552 }
10554 /* Return minimum incoming stack alignment. */
10556 static unsigned int
10558 {
10561 /* Prefer the one specified at command line. */
10564 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10565 if -mstackrealign is used, it isn't used for sibcall check and
10566 estimated stack alignment is 128bit. */
10568 && !TARGET_64BIT
10569 && ix86_force_align_arg_pointer
10572 else
10575 /* Incoming stack alignment can be changed on individual functions
10576 via force_align_arg_pointer attribute. We use the smallest
10577 incoming stack boundary. */
10583 /* The incoming stack frame has to be aligned at least at
10584 parm_stack_boundary. */
10588 /* Stack at entrance of main is aligned by runtime. We use the
10589 smallest incoming stack boundary. */
10597 }
10599 /* Update incoming stack boundary and estimated stack alignment. */
10601 static void
10603 {
10604 ix86_incoming_stack_boundary
10607 /* x86_64 vararg needs 16byte stack alignment for register save
10608 area. */
10613 }
10615 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10616 needed or an rtx for DRAP otherwise. */
10618 static rtx
10620 {
10625 {
10626 /* Assign DRAP to vDRAP and returns vDRAP */
10628 rtx drap_vreg;
10629 rtx arg_ptr;
10642 {
10645 }
10647 }
10648 else
10650 }
10652 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10654 static rtx
10656 {
10658 }
10661 rtx reg;
10663 };
10665 /* Return a short-lived scratch register for use on function entry.
10666 In 32-bit mode, it is valid only after the registers are saved
10667 in the prologue. This register must be released by means of
10668 release_scratch_register_on_entry once it is dead. */
10670 static void
10672 {
10678 {
10679 /* We always use R11 in 64-bit mode. */
10681 }
10682 else
10683 {
10685 bool fastcall_p
10687 bool thiscall_p
10691 int drap_regno
10694 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10695 for the static chain register. */
10699 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10700 for the static chain register. */
10705 /* ecx is the static chain register. */
10707 && !static_chain_p
10712 /* esi is the static chain register. */
10718 else
10719 {
10722 }
10723 }
10727 {
10730 }
10731 }
10733 /* Release a scratch register obtained from the preceding function. */
10735 static void
10737 {
10739 {
10743 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10749 }
10750 }
10752 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10754 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10756 static void
10758 {
10759 /* We skip the probe for the first interval + a small dope of 4 words and
10760 probe that many bytes past the specified size to maintain a protection
10761 area at the botton of the stack. */
10765 /* See if we have a constant small number of probes to generate. If so,
10766 that's the easy case. The run-time loop is made up of 11 insns in the
10767 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10768 for n # of intervals. */
10770 {
10774 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10775 values of N from 1 until it exceeds SIZE. If only one probe is
10776 needed, this will not generate any code. Then adjust and probe
10777 to PROBE_INTERVAL + SIZE. */
10779 {
10781 {
10784 }
10785 else
10792 }
10796 else
10804 /* Adjust back to account for the additional first interval. */
10808 }
10810 /* Otherwise, do the same as above, but in a loop. Note that we must be
10811 extra careful with variables wrapping around because we might be at
10812 the very top (or the very bottom) of the address space and we have
10813 to be able to handle this case properly; in particular, we use an
10814 equality test for the loop condition. */
10815 else
10816 {
10817 HOST_WIDE_INT rounded_size;
10823 /* Step 1: round SIZE to the previous multiple of the interval. */
10828 /* Step 2: compute initial and final value of the loop counter. */
10830 /* SP = SP_0 + PROBE_INTERVAL. */
10835 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10839 stack_pointer_rtx)));
10842 /* Step 3: the loop
10844 while (SP != LAST_ADDR)
10845 {
10846 SP = SP + PROBE_INTERVAL
10847 probe at SP
10848 }
10850 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10851 values of N from 1 until it is equal to ROUNDED_SIZE. */
10856 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10857 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10860 {
10865 }
10867 /* Adjust back to account for the additional first interval. */
10873 }
10877 /* Even if the stack pointer isn't the CFA register, we need to correctly
10878 describe the adjustments made to it, in particular differentiate the
10879 frame-related ones from the frame-unrelated ones. */
10881 {
10894 }
10896 /* Make sure nothing is scheduled before we are done. */
10898 }
10900 /* Adjust the stack pointer up to REG while probing it. */
10904 {
10914 /* Jump to END_LAB if SP == LAST_ADDR. */
10922 /* SP = SP + PROBE_INTERVAL. */
10926 /* Probe at SP. */
10937 }
10939 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10940 inclusive. These are offsets from the current stack pointer. */
10942 static void
10944 {
10945 /* See if we have a constant small number of probes to generate. If so,
10946 that's the easy case. The run-time loop is made up of 7 insns in the
10947 generic case while the compile-time loop is made up of n insns for n #
10948 of intervals. */
10950 {
10951 HOST_WIDE_INT i;
10953 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10954 it exceeds SIZE. If only one probe is needed, this will not
10955 generate any code. Then probe at FIRST + SIZE. */
10962 }
10964 /* Otherwise, do the same as above, but in a loop. Note that we must be
10965 extra careful with variables wrapping around because we might be at
10966 the very top (or the very bottom) of the address space and we have
10967 to be able to handle this case properly; in particular, we use an
10968 equality test for the loop condition. */
10969 else
10970 {
10977 /* Step 1: round SIZE to the previous multiple of the interval. */
10982 /* Step 2: compute initial and final value of the loop counter. */
10984 /* TEST_OFFSET = FIRST. */
10987 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10991 /* Step 3: the loop
10993 while (TEST_ADDR != LAST_ADDR)
10994 {
10995 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10996 probe at TEST_ADDR
10997 }
10999 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11000 until it is equal to ROUNDED_SIZE. */
11005 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11006 that SIZE is equal to ROUNDED_SIZE. */
11011 stack_pointer_rtx,
11016 }
11018 /* Make sure nothing is scheduled before we are done. */
11020 }
11022 /* Probe a range of stack addresses from REG to END, inclusive. These are
11023 offsets from the current stack pointer. */
11027 {
11037 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11045 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11049 /* Probe at TEST_ADDR. */
11062 }
11064 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
11065 to be generated in correct form. */
11066 static void
11068 {
11069 /* Check if stack realign is really needed after reload, and
11070 stores result in cfun */
11071 unsigned int incoming_stack_boundary
11080 {
11081 /* After stack_realign_needed is finalized, we can't no longer
11082 change it. */
11085 }
11087 /* If the only reason for frame_pointer_needed is that we conservatively
11088 assumed stack realignment might be needed, but in the end nothing that
11089 needed the stack alignment had been spilled, clear frame_pointer_needed
11090 and say we don't need stack realignment. */
11092 && frame_pointer_needed
11094 && flag_omit_frame_pointer
11096 && !ix86_current_function_calls_tls_descriptor
11105 {
11107 basic_block bb;
11114 HARD_FRAME_POINTER_REGNUM);
11116 {
11121 set_up_by_prologue))
11122 {
11126 }
11127 }
11129 /* If drap has been set, but it actually isn't live at the start
11130 of the function, there is no reason to set it up. */
11132 {
11135 {
11138 }
11139 }
11140 else
11155 }
11159 }
11161 /* Delete SET_GOT right after entry block if it is allocated to reg. */
11163 static void
11165 {
11171 {
11174 {
11180 }
11181 }
11182 }
11184 /* Expand the prologue into a bunch of separate insns. */
11186 void
11188 {
11192 HOST_WIDE_INT allocate;
11198 /* DRAP should not coexist with stack_realign_fp */
11203 /* Initialize CFA state for before the prologue. */
11207 /* Track SP offset to the CFA. We continue tracking this after we've
11208 swapped the CFA register away from SP. In the case of re-alignment
11209 this is fudged; we're interested to offsets within the local frame. */
11216 {
11217 /* We should have already generated an error for any use of
11218 ms_hook on a nested function. */
11221 /* Check if profiling is active and we shall use profiling before
11222 prologue variant. If so sorry. */
11227 /* In ix86_asm_output_function_label we emitted:
11228 8b ff movl.s %edi,%edi
11229 55 push %ebp
11230 8b ec movl.s %esp,%ebp
11232 This matches the hookable function prologue in Win32 API
11233 functions in Microsoft Windows XP Service Pack 2 and newer.
11234 Wine uses this to enable Windows apps to hook the Win32 API
11235 functions provided by Wine.
11237 What that means is that we've already set up the frame pointer. */
11241 {
11244 /* We've decided to use the frame pointer already set up.
11245 Describe this to the unwinder by pretending that both
11246 push and mov insns happen right here.
11248 Putting the unwind info here at the end of the ms_hook
11249 is done so that we can make absolutely certain we get
11250 the required byte sequence at the start of the function,
11251 rather than relying on an assembler that can produce
11252 the exact encoding required.
11254 However it does mean (in the unpatched case) that we have
11255 a 1 insn window where the asynchronous unwind info is
11256 incorrect. However, if we placed the unwind info at
11257 its correct location we would have incorrect unwind info
11258 in the patched case. Which is probably all moot since
11259 I don't expect Wine generates dwarf2 unwind info for the
11260 system libraries that use this feature. */
11266 stack_pointer_rtx);
11274 /* Note that gen_push incremented m->fs.cfa_offset, even
11275 though we didn't emit the push insn here. */
11279 }
11280 else
11281 {
11282 /* The frame pointer is not needed so pop %ebp again.
11283 This leaves us with a pristine state. */
11285 }
11286 }
11288 /* The first insn of a function that accepts its static chain on the
11289 stack is to push the register that would be filled in by a direct
11290 call. This insn will be skipped by the trampoline. */
11292 {
11296 /* We don't want to interpret this push insn as a register save,
11297 only as a stack adjustment. The real copy of the register as
11298 a save will be done later, if needed. */
11303 }
11305 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
11306 of DRAP is needed and stack realignment is really needed after reload */
11308 {
11311 /* Only need to push parameter pointer reg if it is caller saved. */
11313 {
11314 /* Push arg pointer reg */
11317 }
11319 /* Grab the argument pointer. */
11326 /* Align the stack. */
11328 stack_pointer_rtx,
11332 /* Replicate the return address on the stack so that return
11333 address can be reached via (argp - 1) slot. This is needed
11334 to implement macro RETURN_ADDR_RTX and intrinsic function
11335 expand_builtin_return_addr etc. */
11341 /* For the purposes of frame and register save area addressing,
11342 we've started over with a new frame. */
11345 }
11351 {
11352 /* Note: AT&T enter does NOT have reversed args. Enter is probably
11353 slower on all targets. Also sdb doesn't like it. */
11357 /* Push registers now, before setting the frame pointer
11358 on SEH target. */
11360 && TARGET_SEH
11362 {
11366 }
11369 {
11377 }
11378 }
11381 {
11382 /* If saving registers via PUSH, do so now. */
11384 {
11388 }
11390 /* When using red zone we may start register saving before allocating
11391 the stack frame saving one cycle of the prologue. However, avoid
11392 doing this if we have to probe the stack; at least on x86_64 the
11393 stack probe can turn into a call that clobbers a red zone location. */
11395 && (! TARGET_STACK_PROBE
11397 {
11400 }
11401 }
11404 {
11408 /* The computation of the size of the re-aligned stack frame means
11409 that we must allocate the size of the register save area before
11410 performing the actual alignment. Otherwise we cannot guarantee
11411 that there's enough storage above the realignment point. */
11418 /* Align the stack. */
11420 stack_pointer_rtx,
11423 /* For the purposes of register save area addressing, the stack
11424 pointer is no longer valid. As for the value of sp_offset,
11425 see ix86_compute_frame_layout, which we need to match in order
11426 to pass verification of stack_pointer_offset at the end. */
11429 }
11434 {
11435 /* We start to count from ARG_POINTER. */
11438 /* If it was realigned, take into account the fake frame. */
11440 {
11447 /* This over-estimates by 1 minimal-stack-alignment-unit but
11448 mitigates that by counting in the new return address slot. */
11449 current_function_dynamic_stack_size
11451 }
11454 }
11456 /* On SEH target with very large frame size, allocate an area to save
11457 SSE registers (as the very large allocation won't be described). */
11461 {
11462 HOST_WIDE_INT sse_size =
11467 /* No need to do stack checking as the area will be immediately
11468 written. */
11475 }
11477 /* The stack has already been decremented by the instruction calling us
11478 so probe if the size is non-negative to preserve the protection area. */
11480 {
11481 /* We expect the registers to be saved when probes are used. */
11485 {
11488 {
11491 }
11492 }
11493 else
11494 {
11501 {
11503 {
11506 }
11507 else
11509 }
11510 else
11511 {
11513 {
11517 }
11518 else
11520 }
11521 }
11522 }
11525 ;
11528 {
11532 }
11533 else
11534 {
11546 {
11549 /* Note that SEH directives need to continue tracking the stack
11550 pointer even after the frame pointer has been set up. */
11552 {
11556 }
11557 }
11560 {
11565 {
11569 }
11570 }
11575 /* Use the fact that AX still contains ALLOCATE. */
11577 ? gen_pro_epilogue_adjust_stack_di_sub
11584 {
11592 }
11595 /* Use stack_pointer_rtx for relative addressing so that code
11596 works for realigned stack, too. */
11598 {
11605 }
11607 {
11612 }
11613 }
11616 /* If we havn't already set up the frame pointer, do so now. */
11618 {
11630 }
11637 /* For the mcount profiling on 32 bit PIC mode we need to emit SET_GOT
11638 in PROLOGUE. */
11640 {
11646 /* Deleting already emmitted SET_GOT if exist and allocated to
11647 REAL_PIC_OFFSET_TABLE_REGNUM. */
11649 }
11652 {
11653 /* vDRAP is setup but after reload it turns out stack realign
11654 isn't necessary, here we will emit prologue to setup DRAP
11655 without stack realign adjustment */
11658 }
11660 /* Prevent instructions from being scheduled into register save push
11661 sequence when access to the redzone area is done through frame pointer.
11662 The offset between the frame pointer and the stack pointer is calculated
11663 relative to the value of the stack pointer at the end of the function
11664 prologue, and moving instructions that access redzone area via frame
11665 pointer inside push sequence violates this assumption. */
11669 /* Emit cld instruction if stringops are used in the function. */
11673 /* SEH requires that the prologue end within 256 bytes of the start of
11674 the function. Prevent instruction schedules that would extend that.
11675 Further, prevent alloca modifications to the stack pointer from being
11676 combined with prologue modifications. */
11679 }
11681 /* Emit code to restore REG using a POP insn. */
11683 static void
11685 {
11694 {
11695 /* Previously we'd represented the CFA as an expression
11696 like *(%ebp - 8). We've just popped that value from
11697 the stack, which means we need to reset the CFA to
11698 the drap register. This will remain until we restore
11699 the stack pointer. */
11703 /* This means that the DRAP register is valid for addressing too. */
11706 }
11709 {
11716 }
11718 /* When the frame pointer is the CFA, and we pop it, we are
11719 swapping back to the stack pointer as the CFA. This happens
11720 for stack frames that don't allocate other data, so we assume
11721 the stack pointer is now pointing at the return address, i.e.
11722 the function entry state, which makes the offset be 1 word. */
11724 {
11727 {
11735 }
11736 }
11737 }
11739 /* Emit code to restore saved registers using POP insns. */
11741 static void
11743 {
11749 }
11751 /* Emit code and notes for the LEAVE instruction. */
11753 static void
11755 {
11767 {
11775 }
11778 }
11780 /* Emit code to restore saved registers using MOV insns.
11781 First register is restored from CFA - CFA_OFFSET. */
11782 static void
11785 {
11791 {
11800 {
11801 /* Previously we'd represented the CFA as an expression
11802 like *(%ebp - 8). We've just popped that value from
11803 the stack, which means we need to reset the CFA to
11804 the drap register. This will remain until we restore
11805 the stack pointer. */
11809 /* This means that the DRAP register is valid for addressing. */
11811 }
11812 else
11816 }
11817 }
11819 /* Emit code to restore saved registers using MOV insns.
11820 First register is restored from CFA - CFA_OFFSET. */
11821 static void
11824 {
11829 {
11831 rtx mem;
11841 }
11842 }
11844 /* Restore function stack, frame, and registers. */
11846 void
11848 {
11864 /* The FP must be valid if the frame pointer is present. */
11869 /* We must have *some* valid pointer to the stack frame. */
11872 /* The DRAP is never valid at this point. */
11875 /* See the comment about red zone and frame
11876 pointer usage in ix86_expand_prologue. */
11883 /* Determine the CFA offset of the end of the red-zone. */
11886 {
11887 /* The red-zone begins below the return address. */
11890 /* When the register save area is in the aligned portion of
11891 the stack, determine the maximum runtime displacement that
11892 matches up with the aligned frame. */
11896 }
11898 /* Special care must be taken for the normal return case of a function
11899 using eh_return: the eax and edx registers are marked as saved, but
11900 not restored along this path. Adjust the save location to match. */
11904 /* EH_RETURN requires the use of moves to function properly. */
11907 /* SEH requires the use of pops to identify the epilogue. */
11910 /* If we're only restoring one register and sp is not valid then
11911 using a move instruction to restore the register since it's
11912 less work than reloading sp and popping the register. */
11925 && TARGET_USE_LEAVE
11929 else
11933 {
11934 /* Ensure that the entire register save area is addressable via
11935 the stack pointer, if we will restore via sp. */
11940 {
11944 style,
11946 }
11947 }
11949 /* If there are any SSE registers to restore, then we have to do it
11950 via moves, since there's obviously no pop for SSE regs. */
11956 {
11957 rtx t;
11962 /* eh_return epilogues need %ecx added to the stack pointer. */
11964 {
11967 /* Stack align doesn't work with eh_return. */
11969 /* Neither does regparm nested functions. */
11973 {
11981 /* Note that we use SA as a temporary CFA, as the return
11982 address is at the proper place relative to it. We
11983 pretend this happens at the FP restore insn because
11984 prior to this insn the FP would be stored at the wrong
11985 offset relative to SA, and after this insn we have no
11986 other reasonable register to use for the CFA. We don't
11987 bother resetting the CFA to the SP for the duration of
11988 the return insn. */
12001 }
12002 else
12003 {
12011 {
12015 UNITS_PER_WORD));
12017 }
12018 }
12021 }
12022 }
12023 else
12024 {
12025 /* SEH requires that the function end with (1) a stack adjustment
12026 if necessary, (2) a sequence of pops, and (3) a return or
12027 jump instruction. Prevent insns from the function body from
12028 being scheduled into this sequence. */
12030 {
12031 /* Prevent a catch region from being adjacent to the standard
12032 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
12033 several other flags that would be interesting to test are
12034 not yet set up. */
12037 else
12039 }
12041 /* First step is to deallocate the stack frame so that we can
12042 pop the registers. Also do it on SEH target for very large
12043 frame as the emitted instructions aren't allowed by the ABI in
12044 epilogues. */
12046 || (TARGET_SEH
12049 {
12054 }
12056 {
12060 style,
12062 }
12065 }
12067 /* If we used a stack pointer and haven't already got rid of it,
12068 then do so now. */
12070 {
12071 /* If the stack pointer is valid and pointing at the frame
12072 pointer store address, then we only need a pop. */
12075 /* Leave results in shorter dependency chains on CPUs that are
12076 able to grok it fast. */
12081 else
12082 {
12084 hard_frame_pointer_rtx,
12087 }
12088 }
12091 {
12093 rtx insn;
12119 }
12121 /* At this point the stack pointer must be valid, and we must have
12122 restored all of the registers. We may not have deallocated the
12123 entire stack frame. We've delayed this until now because it may
12124 be possible to merge the local stack deallocation with the
12125 deallocation forced by ix86_static_chain_on_stack. */
12130 {
12134 }
12135 else
12138 /* Sibcall epilogues don't want a return instruction. */
12140 {
12143 }
12146 {
12149 /* i386 can only pop 64K bytes. If asked to pop more, pop return
12150 address, do explicit add, and jump indirectly to the caller. */
12153 {
12155 rtx insn;
12157 /* There is no "pascal" calling convention in any 64bit ABI. */
12174 }
12175 else
12177 }
12178 else
12181 /* Restore the state back to the state from the prologue,
12182 so that it's correct for the next epilogue. */
12184 }
12186 /* Reset from the function's potential modifications. */
12188 static void
12190 {
12194 #if TARGET_MACHO
12195 /* Mach-O doesn't support labels at the end of objects, so if
12196 it looks like we might want one, insert a NOP. */
12197 {
12203 {
12204 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
12205 notes only, instead set their CODE_LABEL_NUMBER to -1,
12206 otherwise there would be code generation differences
12207 in between -g and -g0. */
12211 }
12221 }
12222 #endif
12224 }
12226 /* Return a scratch register to use in the split stack prologue. The
12227 split stack prologue is used for -fsplit-stack. It is the first
12228 instructions in the function, even before the regular prologue.
12229 The scratch register can be any caller-saved register which is not
12230 used for parameters or for the static chain. */
12232 static unsigned int
12234 {
12237 else
12238 {
12251 {
12253 {
12257 }
12259 }
12261 {
12265 }
12267 {
12270 else
12271 {
12273 {
12277 }
12279 }
12280 }
12281 else
12282 {
12283 /* FIXME: We could make this work by pushing a register
12284 around the addition and comparison. */
12287 }
12288 }
12289 }
12291 /* A SYMBOL_REF for the function which allocates new stackspace for
12292 -fsplit-stack. */
12296 /* A SYMBOL_REF for the more stack function when using the large
12297 model. */
12301 /* Handle -fsplit-stack. These are the first instructions in the
12302 function, even before the regular prologue. */
12304 void
12306 {
12308 HOST_WIDE_INT allocate;
12314 rtx fn;
12322 /* This is the label we will branch to if we have enough stack
12323 space. We expect the basic block reordering pass to reverse this
12324 branch if optimizing, so that we branch in the unlikely case. */
12327 /* We need to compare the stack pointer minus the frame size with
12328 the stack boundary in the TCB. The stack boundary always gives
12329 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
12330 can compare directly. Otherwise we need to do an addition. */
12333 UNSPEC_STACK_CHECK);
12338 else
12339 {
12341 rtx offset;
12343 /* We need a scratch register to hold the stack pointer minus
12344 the required frame size. Since this is the very start of the
12345 function, the scratch register can be any caller-saved
12346 register which is not used for parameters. */
12353 {
12354 /* We don't use ix86_gen_add3 in this case because it will
12355 want to split to lea, but when not optimizing the insn
12356 will not be split after this point. */
12359 offset)));
12360 }
12361 else
12362 {
12365 stack_pointer_rtx));
12366 }
12368 }
12374 /* Mark the jump as very likely to be taken. */
12379 {
12382 }
12385 /* Get more stack space. We pass in the desired stack space and the
12386 size of the arguments to copy to the new stack. In 32-bit mode
12387 we push the parameters; __morestack will return on a new stack
12388 anyhow. In 64-bit mode we pass the parameters in r10 and
12389 r11. */
12394 {
12400 /* If this function uses a static chain, it will be in %r10.
12401 Preserve it across the call to __morestack. */
12403 {
12404 rtx rax;
12409 }
12413 {
12414 HOST_WIDE_INT argval;
12417 /* When using the large model we need to load the address
12418 into a register, and we've run out of registers. So we
12419 switch to a different calling convention, and we call a
12420 different function: __morestack_large. We pass the
12421 argument size in the upper 32 bits of r10 and pass the
12422 frame size in the lower 32 bits. */
12427 {
12428 split_stack_fn_large =
12431 }
12433 {
12435 rtx x;
12444 UNSPEC_GOT);
12450 }
12451 else
12458 }
12459 else
12460 {
12464 }
12467 }
12468 else
12469 {
12472 }
12478 /* In order to make call/return prediction work right, we now need
12479 to execute a return instruction. See
12480 libgcc/config/i386/morestack.S for the details on how this works.
12482 For flow purposes gcc must not see this as a return
12483 instruction--we need control flow to continue at the subsequent
12484 label. Therefore, we use an unspec. */
12488 /* If we are in 64-bit mode and this function uses a static chain,
12489 we saved %r10 in %rax before calling _morestack. */
12494 /* If this function calls va_start, we need to store a pointer to
12495 the arguments on the old stack, because they may not have been
12496 all copied to the new stack. At this point the old stack can be
12497 found at the frame pointer value used by __morestack, because
12498 __morestack has set that up before calling back to us. Here we
12499 store that pointer in a scratch register, and in
12500 ix86_expand_prologue we store the scratch register in a stack
12501 slot. */
12503 {
12505 rtx frame_reg;
12512 /* 64-bit:
12513 fp -> old fp value
12514 return address within this function
12515 return address of caller of this function
12516 stack arguments
12517 So we add three words to get to the stack arguments.
12519 32-bit:
12520 fp -> old fp value
12521 return address within this function
12522 first argument to __morestack
12523 second argument to __morestack
12524 return address of caller of this function
12525 stack arguments
12526 So we add five words to get to the stack arguments.
12527 */
12538 }
12543 /* If this function calls va_start, we now have to set the scratch
12544 register for the case where we do not call __morestack. In this
12545 case we need to set it based on the stack pointer. */
12547 {
12554 }
12555 }
12557 /* We may have to tell the dataflow pass that the split stack prologue
12558 is initializing a scratch register. */
12560 static void
12562 {
12564 {
12567 }
12568 }
12569 \f
12570 /* Extract the parts of an RTL expression that is a valid memory address
12571 for an instruction. Return 0 if the structure of the address is
12572 grossly off. Return -1 if the address contains ASHIFT, so it is not
12573 strictly valid, but still used for computing length of lea instruction. */
12575 int
12577 {
12582 rtx tmp;
12586 /* Allow zero-extended SImode addresses,
12587 they will be emitted with addr32 prefix. */
12589 {
12592 {
12596 }
12599 {
12606 }
12607 }
12609 /* Allow SImode subregs of DImode addresses,
12610 they will be emitted with addr32 prefix. */
12612 {
12615 {
12619 }
12620 }
12625 {
12628 else
12630 }
12632 {
12637 do
12638 {
12643 }
12650 {
12653 {
12678 /* FALLTHRU */
12682 && TARGET_TLS_DIRECT_SEG_REFS
12685 else
12692 /* FALLTHRU */
12699 else
12714 }
12715 }
12716 }
12718 {
12721 }
12723 {
12724 /* We're called for lea too, which implements ashift on occasion. */
12734 }
12735 else
12739 {
12741 ;
12744 ;
12745 else
12747 }
12749 /* Extract the integral value of scale. */
12751 {
12755 }
12760 /* Avoid useless 0 displacement. */
12764 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12769 {
12772 }
12774 /* Special case: %ebp cannot be encoded as a base without a displacement.
12775 Similarly %r13. */
12777 && base_reg
12786 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12787 Avoid this by transforming to [%esi+0].
12788 Reload calls address legitimization without cfun defined, so we need
12789 to test cfun for being non-NULL. */
12795 /* Special case: encode reg+reg instead of reg*2. */
12799 /* Special case: scaling cannot be encoded without base or displacement. */
12810 }
12811 \f
12812 /* Return cost of the memory address x.
12813 For i386, it is better to use a complex address than let gcc copy
12814 the address into a reg and make a new pseudo. But not if the address
12815 requires to two regs - that would mean more pseudos with longer
12816 lifetimes. */
12817 static int
12819 {
12831 /* Attempt to minimize number of registers in the address. */
12837 cost++;
12839 /* When address base or index is "pic_offset_table_rtx" we don't increase
12840 address cost. When a memopt with "pic_offset_table_rtx" is not invariant
12841 itself it most likely means that base or index is not invariant.
12842 Therefore only "pic_offset_table_rtx" could be hoisted out, which is not
12843 profitable for x86. */
12846 || (!pic_offset_table_rtx
12851 || (!pic_offset_table_rtx
12855 cost++;
12857 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12858 since it's predecode logic can't detect the length of instructions
12859 and it degenerates to vector decoded. Increase cost of such
12860 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12861 to split such addresses or even refuse such addresses at all.
12863 Following addressing modes are affected:
12864 [base+scale*index]
12865 [scale*index+disp]
12866 [base+index]
12868 The first and last case may be avoidable by explicitly coding the zero in
12869 memory address, but I don't have AMD-K6 machine handy to check this
12870 theory. */
12879 }
12880 \f
12881 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
12882 this is used for to form addresses to local data when -fPIC is in
12883 use. */
12885 static bool
12887 {
12890 }
12892 /* Determine if a given RTX is a valid constant. We already know this
12893 satisfies CONSTANT_P. */
12895 static bool
12897 {
12898 /* Pointer bounds constants are not valid. */
12903 {
12908 {
12912 }
12917 /* Only some unspecs are valid as "constants". */
12920 {
12936 }
12938 /* We must have drilled down to a symbol. */
12943 /* FALLTHRU */
12946 /* TLS symbols are never valid. */
12950 /* DLLIMPORT symbols are never valid. */
12955 #if TARGET_MACHO
12956 /* mdynamic-no-pic */
12959 #endif
12975 }
12977 /* Otherwise we handle everything else in the move patterns. */
12979 }
12981 /* Determine if it's legal to put X into the constant pool. This
12982 is not possible for the address of thread-local symbols, which
12983 is checked above. */
12985 static bool
12987 {
12988 /* We can always put integral constants and vectors in memory. */
12990 {
12998 }
13000 }
13002 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
13003 otherwise zero. */
13005 static bool
13007 {
13013 }
13016 /* Nonzero if the constant value X is a legitimate general operand
13017 when generating PIC code. It is given that flag_pic is on and
13018 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
13020 bool
13022 {
13023 rtx inner;
13026 {
13033 /* Only some unspecs are valid as "constants". */
13036 {
13049 }
13050 /* FALLTHRU */
13058 }
13059 }
13061 /* Determine if a given CONST RTX is a valid memory displacement
13062 in PIC mode. */
13064 bool
13066 {
13069 /* In 64bit mode we can allow direct addresses of symbols and labels
13070 when they are not dynamic symbols. */
13072 {
13076 {
13100 /* FALLTHRU */
13103 /* TLS references should always be enclosed in UNSPEC.
13104 The dllimported symbol needs always to be resolved. */
13110 {
13118 /* Function-symbols need to be resolved only for
13119 large-model.
13120 For the small-model we don't need to resolve anything
13121 here. */
13126 /* Non-external symbols don't need to be resolved for
13127 large, and medium-model. */
13132 }
13135 || (HAVE_LD_PIE_COPYRELOC
13136 && flag_pie
13145 }
13146 }
13152 {
13153 /* We are unsafe to allow PLUS expressions. This limit allowed distance
13154 of GOT tables. We should not need these anyway. */
13166 }
13170 {
13175 }
13184 {
13188 /* We need to check for both symbols and labels because VxWorks loads
13189 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
13190 details. */
13194 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
13195 While ABI specify also 32bit relocation but we don't produce it in
13196 small PIC model at all. */
13218 }
13221 }
13223 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
13224 replace the input X, or the original X if no replacement is called for.
13225 The output parameter *WIN is 1 if the calling macro should goto WIN,
13226 0 if it should not. */
13228 bool
13231 {
13232 /* Reload can generate:
13234 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
13235 (reg:DI 97))
13236 (reg:DI 2 cx))
13238 This RTX is rejected from ix86_legitimate_address_p due to
13239 non-strictness of base register 97. Following this rejection,
13240 reload pushes all three components into separate registers,
13241 creating invalid memory address RTX.
13243 Following code reloads only the invalid part of the
13244 memory address RTX. */
13250 {
13256 {
13261 }
13265 {
13270 }
13274 }
13277 }
13279 /* Determine if op is suitable RTX for an address register.
13280 Return naked register if a register or a register subreg is
13281 found, otherwise return NULL_RTX. */
13283 static rtx
13285 {
13288 /* Only SImode or DImode registers can form the address. */
13295 {
13303 /* Don't allow SUBREGs that span more than a word. It can
13304 lead to spill failures when the register is one word out
13305 of a two word structure. */
13309 /* Allow only SUBREGs of non-eliminable hard registers. */
13312 }
13314 /* Op is not a register. */
13316 }
13318 /* Recognizes RTL expressions that are valid memory addresses for an
13319 instruction. The MODE argument is the machine mode for the MEM
13320 expression that wants to use this address.
13322 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
13323 convert common non-canonical forms to canonical form so that they will
13324 be recognized. */
13326 static bool
13328 {
13331 HOST_WIDE_INT scale;
13335 /* Decomposition failed. */
13344 /* Validate base register. */
13346 {
13354 /* Base is not valid. */
13356 }
13358 /* Validate index register. */
13360 {
13368 /* Index is not valid. */
13370 }
13372 /* Index and base should have the same mode. */
13377 /* Address override works only on the (%reg) part of %fs:(%reg). */
13383 /* Validate scale factor. */
13385 {
13387 /* Scale without index. */
13391 /* Scale is not a valid multiplier. */
13393 }
13395 /* Validate displacement. */
13397 {
13402 {
13403 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
13404 used. While ABI specify also 32bit relocations, we don't produce
13405 them at all and use IP relative instead. */
13412 /* 64bit address unspec. */
13432 /* Invalid address unspec. */
13434 }
13437 && (flag_pic
13438 || (TARGET_MACHO
13439 #if TARGET_MACHO
13440 && MACHOPIC_INDIRECT
13442 #endif
13443 )))
13444 {
13446 is_legitimate_pic:
13448 {
13449 /* foo@dtpoff(%rX) is ok. */
13456 /* Non-constant pic memory reference. */
13458 }
13461 /* Displacement is an invalid pic construct. */
13463 #if TARGET_MACHO
13466 /* displacment must be referenced via non_lazy_pointer */
13468 #endif
13470 /* This code used to verify that a symbolic pic displacement
13471 includes the pic_offset_table_rtx register.
13473 While this is good idea, unfortunately these constructs may
13474 be created by "adds using lea" optimization for incorrect
13475 code like:
13477 int a;
13478 int foo(int i)
13479 {
13480 return *(&a+i);
13481 }
13483 This code is nonsensical, but results in addressing
13484 GOT table with pic_offset_table_rtx base. We can't
13485 just refuse it easily, since it gets matched by
13486 "addsi3" pattern, that later gets split to lea in the
13487 case output register differs from input. While this
13488 can be handled by separate addsi pattern for this case
13489 that never results in lea, this seems to be easier and
13490 correct fix for crash to disable this test. */
13491 }
13498 /* Displacement is not constant. */
13502 /* Displacement is out of range. */
13504 /* In x32 mode, constant addresses are sign extended to 64bit, so
13505 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13510 }
13512 /* Everything looks valid. */
13514 }
13516 /* Determine if a given RTX is a valid constant address. */
13518 bool
13520 {
13522 }
13523 \f
13524 /* Return a unique alias set for the GOT. */
13526 static alias_set_type
13528 {
13533 }
13535 /* Set regs_ever_live for PIC base address register
13536 to true if required. */
13537 static void
13539 {
13542 }
13544 /* Return a legitimate reference for ORIG (an address) using the
13545 register REG. If REG is 0, a new pseudo is generated.
13547 There are two types of references that must be handled:
13549 1. Global data references must load the address from the GOT, via
13550 the PIC reg. An insn is emitted to do this load, and the reg is
13551 returned.
13553 2. Static data references, constant pool addresses, and code labels
13554 compute the address as an offset from the GOT, whose base is in
13555 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13556 differentiate them from global data objects. The returned
13557 address is the PIC reg + an unspec constant.
13559 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13560 reg also appears in the address. */
13562 static rtx
13564 {
13568 #if TARGET_MACHO
13570 {
13573 /* Use the generic Mach-O PIC machinery. */
13575 }
13576 #endif
13579 {
13583 }
13589 {
13590 rtx tmpreg;
13591 /* This symbol may be referenced via a displacement from the PIC
13592 base address (@GOTOFF). */
13598 {
13600 UNSPEC_GOTOFF);
13602 }
13603 else
13608 else
13613 {
13617 }
13618 else
13620 }
13622 {
13623 /* This symbol may be referenced via a displacement from the PIC
13624 base address (@GOTOFF). */
13630 {
13632 UNSPEC_GOTOFF);
13634 }
13635 else
13641 {
13644 }
13645 }
13647 /* We can't use @GOTOFF for text labels on VxWorks;
13648 see gotoff_operand. */
13650 {
13655 /* For x64 PE-COFF there is no GOT table. So we use address
13656 directly. */
13658 {
13666 }
13668 {
13676 /* Use directly gen_movsi, otherwise the address is loaded
13677 into register for CSE. We don't want to CSE this addresses,
13678 instead we CSE addresses from the GOT table, so skip this. */
13681 }
13682 else
13683 {
13684 /* This symbol must be referenced via a load from the
13685 Global Offset Table (@GOT). */
13700 }
13701 }
13702 else
13703 {
13706 {
13708 {
13711 }
13712 else
13714 }
13716 {
13719 /* We must match stuff we generate before. Assume the only
13720 unspecs that can get here are ours. Not that we could do
13721 anything with them anyway.... */
13727 }
13729 {
13732 /* Check first to see if this is a constant offset from a @GOTOFF
13733 symbol reference. */
13736 {
13738 {
13741 UNSPEC_GOTOFF);
13747 {
13750 }
13751 }
13752 else
13753 {
13756 {
13760 }
13761 }
13762 }
13763 else
13764 {
13767 new_rtx
13771 {
13774 {
13777 new_rtx
13779 }
13780 else
13782 }
13783 else
13784 {
13787 {
13790 }
13792 }
13793 }
13794 }
13795 }
13797 }
13798 \f
13799 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13801 static rtx
13803 {
13807 {
13812 }
13818 }
13820 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13824 static rtx
13826 {
13828 {
13834 }
13837 {
13839 UNSPEC_PLTOFF);
13842 }
13845 }
13847 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13851 rtx
13853 {
13855 {
13856 ix86_tls_module_base_symbol
13861 }
13864 }
13866 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13867 false if we expect this to be used for a memory address and true if
13868 we expect to load the address into a register. */
13870 static rtx
13872 {
13878 /* Fall back to global dynamic model if tool chain cannot support local
13879 dynamic. */
13886 {
13891 {
13894 else
13895 {
13898 }
13899 }
13902 {
13905 else
13915 }
13916 else
13917 {
13921 {
13926 emit_call_insn
13936 }
13937 else
13939 }
13946 {
13949 else
13950 {
13953 }
13954 }
13957 {
13962 else
13968 }
13969 else
13970 {
13974 {
13977 rtx eqv;
13980 emit_call_insn
13985 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
13986 share the LD_BASE result with other LD model accesses. */
13988 UNSPEC_TLS_LD_BASE);
13992 }
13993 else
13995 }
14003 {
14010 }
14015 {
14017 {
14018 /* The Sun linker took the AMD64 TLS spec literally
14019 and can only handle %rax as destination of the
14020 initial executable code sequence. */
14025 }
14027 /* Generate DImode references to avoid %fs:(%reg32)
14028 problems and linker IE->LE relaxation bug. */
14032 }
14034 {
14038 }
14040 {
14044 }
14045 else
14046 {
14049 }
14059 {
14064 }
14065 else
14066 {
14070 }
14080 {
14084 }
14085 else
14086 {
14090 }
14095 }
14098 }
14100 /* Create or return the unique __imp_DECL dllimport symbol corresponding
14101 to symbol DECL if BEIMPORT is true. Otherwise create or return the
14102 unique refptr-DECL symbol corresponding to symbol DECL. */
14105 {
14109 {
14111 }
14113 static void
14115 {
14121 else
14123 }
14124 };
14128 static tree
14130 {
14136 tree to;
14137 rtx rtl;
14164 else
14177 {
14179 #ifdef SUB_TARGET_RECORD_STUB
14181 #endif
14182 }
14191 }
14193 /* Expand SYMBOL into its corresponding far-addresse symbol.
14194 WANT_REG is true if we require the result be a register. */
14196 static rtx
14198 {
14199 tree imp_decl;
14200 rtx x;
14209 }
14211 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
14212 true if we require the result be a register. */
14214 static rtx
14216 {
14217 tree imp_decl;
14218 rtx x;
14227 }
14229 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
14230 is true if we require the result be a register. */
14232 static rtx
14234 {
14239 {
14246 {
14249 }
14250 }
14266 {
14269 }
14271 }
14273 /* Try machine-dependent ways of modifying an illegitimate address
14274 to be legitimate. If we find one, return the new, valid address.
14275 This macro is used in only one place: `memory_address' in explow.c.
14277 OLDX is the address as it was before break_out_memory_refs was called.
14278 In some cases it is useful to look at this to decide what needs to be done.
14280 It is always safe for this macro to do nothing. It exists to recognize
14281 opportunities to optimize the output.
14283 For the 80386, we handle X+REG by loading X into a register R and
14284 using R+REG. R will go in a general reg and indexing will be used.
14285 However, if REG is a broken-out memory address or multiplication,
14286 nothing needs to be done because REG can certainly go in a general reg.
14288 When -fpic is used, special handling is needed for symbolic references.
14289 See comments by legitimize_pic_address in i386.c for details. */
14291 static rtx
14293 {
14304 {
14308 }
14311 {
14315 }
14320 #if TARGET_MACHO
14323 #endif
14325 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
14329 {
14334 }
14337 {
14338 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
14343 {
14349 }
14354 {
14360 }
14362 /* Put multiply first if it isn't already. */
14364 {
14369 }
14371 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
14372 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
14373 created by virtual register instantiation, register elimination, and
14374 similar optimizations. */
14376 {
14382 }
14384 /* Canonicalize
14385 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
14386 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
14391 {
14392 rtx constant;
14396 {
14399 }
14401 {
14404 }
14405 else
14409 {
14416 }
14417 }
14423 {
14426 }
14429 {
14432 }
14440 {
14443 }
14449 {
14453 {
14456 }
14460 }
14463 {
14467 {
14470 }
14474 }
14475 }
14478 }
14479 \f
14480 /* Print an integer constant expression in assembler syntax. Addition
14481 and subtraction are the only arithmetic that may appear in these
14482 expressions. FILE is the stdio stream to write to, X is the rtx, and
14483 CODE is the operand print code from the output string. */
14485 static void
14487 {
14491 {
14500 else
14501 {
14504 /* Mark the decl as referenced so that cgraph will
14505 output the function. */
14509 #if TARGET_MACHO
14513 #endif
14515 }
14523 /* FALLTHRU */
14534 /* This used to output parentheses around the expression,
14535 but that does not work on the 386 (either ATT or BSD assembler). */
14541 {
14542 /* We can use %d if the number is <32 bits and positive. */
14547 else
14549 }
14550 else
14551 /* We can't handle floating point constants;
14552 TARGET_PRINT_OPERAND must handle them. */
14557 /* Some assemblers need integer constants to appear first. */
14559 {
14563 }
14564 else
14565 {
14570 }
14585 {
14589 }
14594 {
14613 /* FIXME: This might be @TPOFF in Sun ld too. */
14622 else
14632 else
14638 #if TARGET_MACHO
14643 #endif
14647 }
14652 }
14653 }
14655 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14656 We need to emit DTP-relative relocations. */
14658 static void ATTRIBUTE_UNUSED
14660 {
14665 {
14673 }
14674 }
14676 /* Return true if X is a representation of the PIC register. This copes
14677 with calls from ix86_find_base_term, where the register might have
14678 been replaced by a cselib value. */
14680 static bool
14682 {
14689 {
14697 }
14698 else
14700 }
14702 /* Helper function for ix86_delegitimize_address.
14703 Attempt to delegitimize TLS local-exec accesses. */
14705 static rtx
14707 {
14732 {
14737 }
14743 }
14745 /* In the name of slightly smaller debug output, and to cater to
14746 general assembler lossage, recognize PIC+GOTOFF and turn it back
14747 into a direct symbol reference.
14749 On Darwin, this is necessary to avoid a crash, because Darwin
14750 has a different PIC label for each routine but the DWARF debugging
14751 information is not associated with any particular routine, so it's
14752 necessary to remove references to the PIC label from RTL stored by
14753 the DWARF output code. */
14755 static rtx
14757 {
14759 /* addend is NULL or some rtx if x is something+GOTOFF where
14760 something doesn't include the PIC register. */
14762 /* reg_addend is NULL or a multiple of some register. */
14764 /* const_addend is NULL or a const_int. */
14766 /* This is the result, or NULL. */
14775 {
14782 {
14788 }
14795 {
14798 {
14803 }
14805 }
14810 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14811 and -mcmodel=medium -fpic. */
14812 }
14819 /* %ebx + GOT/GOTOFF */
14820 ;
14822 {
14823 /* %ebx + %reg * scale + GOT/GOTOFF */
14829 else
14830 {
14833 }
14834 }
14835 else
14841 {
14844 }
14865 {
14866 /* If the rest of original X doesn't involve the PIC register, add
14867 addend and subtract pic_offset_table_rtx. This can happen e.g.
14868 for code like:
14869 leal (%ebx, %ecx, 4), %ecx
14870 ...
14871 movl foo@GOTOFF(%ecx), %edx
14872 in which case we return (%ecx - %ebx) + foo
14873 or (%ecx - _GLOBAL_OFFSET_TABLE_) + foo if pseudo_pic_reg
14874 and reload has completed. */
14878 pic_offset_table_rtx),
14879 result);
14881 {
14885 }
14886 else
14888 }
14890 {
14894 }
14896 }
14898 /* If X is a machine specific address (i.e. a symbol or label being
14899 referenced as a displacement from the GOT implemented using an
14900 UNSPEC), then return the base term. Otherwise return X. */
14902 rtx
14904 {
14905 rtx term;
14908 {
14922 }
14925 }
14926 \f
14927 static void
14930 {
14934 {
14937 }
14942 {
14945 {
14964 }
14968 {
14987 }
14994 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
14995 Those same assemblers have the same but opposite lossage on cmov. */
14998 else
15003 {
15016 }
15023 else
15028 {
15041 }
15048 else
15058 else
15069 }
15071 }
15073 /* Print the name of register X to FILE based on its machine mode and number.
15074 If CODE is 'w', pretend the mode is HImode.
15075 If CODE is 'b', pretend the mode is QImode.
15076 If CODE is 'k', pretend the mode is SImode.
15077 If CODE is 'q', pretend the mode is DImode.
15078 If CODE is 'x', pretend the mode is V4SFmode.
15079 If CODE is 't', pretend the mode is V8SFmode.
15080 If CODE is 'g', pretend the mode is V16SFmode.
15081 If CODE is 'h', pretend the reg is the 'high' byte register.
15082 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
15083 If CODE is 'd', duplicate the operand for AVX instruction.
15084 */
15086 void
15088 {
15097 {
15101 }
15128 else
15131 /* Irritatingly, AMD extended registers use different naming convention
15132 from the normal registers: "r%d[bwd]" */
15134 {
15139 {
15153 /* no suffix */
15158 }
15160 }
15164 {
15167 {
15170 }
15171 /* FALLTHRU */
15177 /* FALLTHRU */
15180 normal:
15195 {
15200 }
15203 {
15208 }
15212 }
15216 {
15219 else
15221 }
15222 }
15224 /* Meaning of CODE:
15225 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
15226 C -- print opcode suffix for set/cmov insn.
15227 c -- like C, but print reversed condition
15228 F,f -- likewise, but for floating-point.
15229 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
15230 otherwise nothing
15231 R -- print embeded rounding and sae.
15232 r -- print only sae.
15233 z -- print the opcode suffix for the size of the current operand.
15234 Z -- likewise, with special suffixes for x87 instructions.
15235 * -- print a star (in certain assembler syntax)
15236 A -- print an absolute memory reference.
15237 E -- print address with DImode register names if TARGET_64BIT.
15238 w -- print the operand as if it's a "word" (HImode) even if it isn't.
15239 s -- print a shift double count, followed by the assemblers argument
15240 delimiter.
15241 b -- print the QImode name of the register for the indicated operand.
15242 %b0 would print %al if operands[0] is reg 0.
15243 w -- likewise, print the HImode name of the register.
15244 k -- likewise, print the SImode name of the register.
15245 q -- likewise, print the DImode name of the register.
15246 x -- likewise, print the V4SFmode name of the register.
15247 t -- likewise, print the V8SFmode name of the register.
15248 g -- likewise, print the V16SFmode name of the register.
15249 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
15250 y -- print "st(0)" instead of "st" as a register.
15251 d -- print duplicated register operand for AVX instruction.
15252 D -- print condition for SSE cmp instruction.
15253 P -- if PIC, print an @PLT suffix.
15254 p -- print raw symbol name.
15255 X -- don't print any sort of PIC '@' suffix for a symbol.
15256 & -- print some in-use local-dynamic symbol name.
15257 H -- print a memory address offset by 8; used for sse high-parts
15258 Y -- print condition for XOP pcom* instruction.
15259 + -- print a branch hint as 'cs' or 'ds' prefix
15260 ; -- print a semicolon (after prefixes due to bug in older gas).
15261 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
15262 @ -- print a segment register of thread base pointer load
15263 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
15264 ! -- print MPX prefix for jxx/call/ret instructions if required.
15265 */
15267 void
15269 {
15271 {
15273 {
15276 {
15282 /* Intel syntax. For absolute addresses, registers should not
15283 be surrounded by braces. */
15285 {
15290 }
15295 }
15301 /* Wrap address in an UNSPEC to declare special handling. */
15339 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15344 {
15358 output_operand_lossage
15361 }
15364 #endif
15369 {
15370 /* Opcodes don't get size suffixes if using Intel opcodes. */
15375 {
15393 output_operand_lossage
15396 }
15397 }
15400 warning
15402 /* FALLTHRU */
15405 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
15410 {
15412 {
15414 #ifdef HAVE_AS_IX86_FILDS
15416 #endif
15424 #ifdef HAVE_AS_IX86_FILDQ
15426 #else
15428 #endif
15433 }
15434 }
15436 {
15437 /* 387 opcodes don't get size suffixes
15438 if the operands are registers. */
15443 {
15459 }
15460 }
15461 else
15462 {
15463 output_operand_lossage
15466 }
15468 output_operand_lossage
15489 {
15492 }
15497 {
15548 }
15552 /* Little bit of braindamage here. The SSE compare instructions
15553 does use completely different names for the comparisons that the
15554 fp conditional moves. */
15556 {
15559 {
15562 }
15568 {
15571 }
15577 {
15580 }
15589 {
15592 }
15598 {
15601 }
15607 {
15610 }
15621 }
15626 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15629 #endif
15634 {
15638 }
15642 file);
15647 {
15651 }
15652 /* It doesn't actually matter what mode we use here, as we're
15653 only going to use this for printing. */
15655 /* Output 'qword ptr' for intel assembler dialect. */
15664 #ifdef HAVE_AS_IX86_HLE
15666 #else
15668 #endif
15670 #ifdef HAVE_AS_IX86_HLE
15672 #else
15674 #endif
15675 /* We do not want to print value of the operand. */
15704 {
15719 }
15732 {
15737 else
15740 }
15743 {
15744 rtx x;
15753 {
15758 {
15760 bool cputaken
15763 /* Emit hints only in the case default branch prediction
15764 heuristics would fail. */
15766 {
15767 /* We use 3e (DS) prefix for taken branches and
15768 2e (CS) prefix for not taken branches. */
15771 else
15773 }
15774 }
15775 }
15777 }
15780 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15782 #endif
15789 /* The kernel uses a different segment register for performance
15790 reasons; a system call would not have to trash the userspace
15791 segment register, which would be expensive. */
15794 else
15814 }
15815 }
15821 {
15822 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15825 {
15828 {
15837 else
15844 }
15846 /* Check for explicit size override (codes 'b', 'w', 'k',
15847 'q' and 'x') */
15861 }
15864 /* Avoid (%rip) for call operands. */
15870 else
15872 }
15875 {
15876 REAL_VALUE_TYPE r;
15884 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15888 else
15890 }
15893 {
15894 REAL_VALUE_TYPE r;
15903 }
15905 /* These float cases don't actually occur as immediate operands. */
15907 {
15912 }
15914 else
15915 {
15916 /* We have patterns that allow zero sets of memory, for instance.
15917 In 64-bit mode, we should probably support all 8-byte vectors,
15918 since we can in fact encode that into an immediate. */
15920 {
15923 }
15926 {
15928 {
15931 }
15934 {
15937 else
15939 }
15940 }
15945 else
15947 }
15948 }
15950 static bool
15952 {
15955 }
15956 \f
15957 /* Print a memory operand whose address is ADDR. */
15959 static void
15961 {
15970 {
15977 }
15979 {
15983 }
15985 {
15989 {
15992 }
15995 }
15997 {
16002 }
16003 else
16014 {
16025 }
16027 /* Use one byte shorter RIP relative addressing for 64bit mode. */
16029 {
16041 }
16043 {
16044 /* Displacement only requires special attention. */
16047 {
16051 }
16054 else
16056 }
16057 else
16058 {
16059 /* Print SImode register names to force addr32 prefix. */
16061 {
16062 #ifdef ENABLE_CHECKING
16065 {
16076 }
16077 #endif
16080 }
16082 && TARGET_X32
16083 && disp
16086 {
16087 /* X32 runs in 64-bit mode, where displacement, DISP, in
16088 address DISP(%r64), is encoded as 32-bit immediate sign-
16089 extended from 32-bit to 64-bit. For -0x40000300(%r64),
16090 address is %r64 + 0xffffffffbffffd00. When %r64 <
16091 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
16092 which is invalid for x32. The correct address is %r64
16093 - 0x40000300 == 0xf7ffdd64. To properly encode
16094 -0x40000300(%r64) for x32, we zero-extend negative
16095 displacement by forcing addr32 prefix which truncates
16096 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
16097 zero-extend all negative displacements, including -1(%rsp).
16098 However, for small negative displacements, sign-extension
16099 won't cause overflow. We only zero-extend negative
16100 displacements if they < -16*1024*1024, which is also used
16101 to check legitimate address displacements for PIC. */
16103 }
16106 {
16108 {
16113 else
16115 }
16121 {
16126 }
16128 }
16129 else
16130 {
16134 {
16135 /* Pull out the offset of a symbol; print any symbol itself. */
16139 {
16143 }
16151 else
16153 }
16157 {
16160 {
16164 }
16165 }
16168 else
16172 {
16177 }
16179 }
16180 }
16181 }
16183 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
16185 static bool
16187 {
16188 rtx op;
16195 {
16198 /* FIXME: This might be @TPOFF in Sun ld. */
16209 else
16221 else
16228 #if TARGET_MACHO
16234 #endif
16237 {
16242 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
16244 #else
16246 #endif
16249 }
16254 }
16257 }
16258 \f
16259 /* Split one or more double-mode RTL references into pairs of half-mode
16260 references. The RTL can be REG, offsettable MEM, integer constant, or
16261 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
16262 split and "num" is its length. lo_half and hi_half are output arrays
16263 that parallel "operands". */
16265 void
16268 {
16269 machine_mode half_mode;
16273 {
16282 }
16287 {
16290 /* simplify_subreg refuse to split volatile memory addresses,
16291 but we still have to handle it. */
16293 {
16296 }
16297 else
16298 {
16305 }
16306 }
16307 }
16308 \f
16309 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
16310 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
16311 is the expression of the binary operation. The output may either be
16312 emitted here, or returned to the caller, like all output_* functions.
16314 There is no guarantee that the operands are the same mode, as they
16315 might be within FLOAT or FLOAT_EXTEND expressions. */
16317 #ifndef SYSV386_COMPAT
16318 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
16319 wants to fix the assemblers because that causes incompatibility
16320 with gcc. No-one wants to fix gcc because that causes
16321 incompatibility with assemblers... You can use the option of
16322 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
16323 #define SYSV386_COMPAT 1
16324 #endif
16328 {
16334 #ifdef ENABLE_CHECKING
16335 /* Even if we do not want to check the inputs, this documents input
16336 constraints. Which helps in understanding the following code. */
16346 else
16348 #endif
16351 {
16356 else
16365 else
16374 else
16383 else
16390 }
16393 {
16395 {
16399 else
16401 }
16402 else
16403 {
16407 else
16409 }
16411 }
16415 {
16419 {
16423 }
16425 /* know operands[0] == operands[1]. */
16428 {
16431 }
16434 {
16436 /* How is it that we are storing to a dead operand[2]?
16437 Well, presumably operands[1] is dead too. We can't
16438 store the result to st(0) as st(0) gets popped on this
16439 instruction. Instead store to operands[2] (which I
16440 think has to be st(1)). st(1) will be popped later.
16441 gcc <= 2.8.1 didn't have this check and generated
16442 assembly code that the Unixware assembler rejected. */
16444 else
16447 }
16451 else
16458 {
16461 }
16464 {
16467 }
16470 {
16471 #if SYSV386_COMPAT
16472 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16473 derived assemblers, confusingly reverse the direction of
16474 the operation for fsub{r} and fdiv{r} when the
16475 destination register is not st(0). The Intel assembler
16476 doesn't have this brain damage. Read !SYSV386_COMPAT to
16477 figure out what the hardware really does. */
16480 else
16482 #else
16484 /* As above for fmul/fadd, we can't store to st(0). */
16486 else
16488 #endif
16490 }
16493 {
16494 #if SYSV386_COMPAT
16497 else
16499 #else
16502 else
16504 #endif
16506 }
16509 {
16512 else
16515 }
16517 {
16518 #if SYSV386_COMPAT
16520 #else
16522 #endif
16523 }
16524 else
16525 {
16526 #if SYSV386_COMPAT
16528 #else
16530 #endif
16531 }
16536 }
16540 }
16542 /* Check if a 256bit AVX register is referenced inside of EXP. */
16544 static bool
16546 {
16552 }
16554 /* Return needed mode for entity in optimize_mode_switching pass. */
16556 static int
16558 {
16560 {
16561 rtx link;
16563 /* Needed mode is set to AVX_U128_CLEAN if there are
16564 no 256bit modes used in function arguments. */
16566 link;
16568 {
16570 {
16575 }
16576 }
16579 }
16581 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16582 changes state only when a 256bit register is written to, but we need
16583 to prevent the compiler from moving optimal insertion point above
16584 eventual read from 256bit register. */
16591 }
16593 /* Return mode that i387 must be switched into
16594 prior to the execution of insn. */
16596 static int
16598 {
16601 /* The mode UNINITIALIZED is used to store control word after a
16602 function call or ASM pattern. The mode ANY specify that function
16603 has no requirements on the control word and make no changes in the
16604 bits we are interested in. */
16618 {
16641 }
16644 }
16646 /* Return mode that entity must be switched into
16647 prior to the execution of insn. */
16649 static int
16651 {
16653 {
16663 }
16665 }
16667 /* Check if a 256bit AVX register is referenced in stores. */
16669 static void
16671 {
16673 {
16676 }
16677 }
16679 /* Calculate mode of upper 128bit AVX registers after the insn. */
16681 static int
16683 {
16690 /* We know that state is clean after CALL insn if there are no
16691 256bit registers used in the function return register. */
16693 {
16698 }
16700 /* Otherwise, return current mode. Remember that if insn
16701 references AVX 256bit registers, the mode was already changed
16702 to DIRTY from MODE_NEEDED. */
16704 }
16706 /* Return the mode that an insn results in. */
16708 int
16710 {
16712 {
16722 }
16723 }
16725 static int
16727 {
16728 tree arg;
16730 /* Entry mode is set to AVX_U128_DIRTY if there are
16731 256bit modes used in function arguments. */
16734 {
16739 }
16742 }
16744 /* Return a mode that ENTITY is assumed to be
16745 switched to at function entry. */
16747 static int
16749 {
16751 {
16761 }
16762 }
16764 static int
16766 {
16769 /* Exit mode is set to AVX_U128_DIRTY if there are
16770 256bit modes used in the function return register. */
16775 }
16777 /* Return a mode that ENTITY is assumed to be
16778 switched to at function exit. */
16780 static int
16782 {
16784 {
16794 }
16795 }
16797 static int
16799 {
16801 }
16803 /* Output code to initialize control word copies used by trunc?f?i and
16804 rounding patterns. CURRENT_MODE is set to current control word,
16805 while NEW_MODE is set to new control word. */
16807 static void
16809 {
16811 rtx new_mode;
16822 {
16824 {
16826 /* round toward zero (truncate) */
16832 /* round down toward -oo */
16839 /* round up toward +oo */
16846 /* mask precision exception for nearbyint() */
16853 }
16854 }
16855 else
16856 {
16858 {
16860 /* round toward zero (truncate) */
16866 /* round down toward -oo */
16872 /* round up toward +oo */
16878 /* mask precision exception for nearbyint() */
16885 }
16886 }
16892 }
16894 /* Emit vzeroupper. */
16896 void
16898 {
16901 /* Cancel automatic vzeroupper insertion if there are
16902 live call-saved SSE registers at the insertion point. */
16914 }
16916 /* Generate one or more insns to set ENTITY to MODE. */
16918 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
16919 is the set of hard registers live at the point where the insn(s)
16920 are to be inserted. */
16922 static void
16924 HARD_REG_SET regs_live)
16925 {
16927 {
16942 }
16943 }
16945 /* Output code for INSN to convert a float to a signed int. OPERANDS
16946 are the insn operands. The output may be [HSD]Imode and the input
16947 operand may be [SDX]Fmode. */
16951 {
16956 /* Jump through a hoop or two for DImode, since the hardware has no
16957 non-popping instruction. We used to do this a different way, but
16958 that was somewhat fragile and broke with post-reload splitters. */
16968 else
16969 {
16974 else
16978 }
16981 }
16983 /* Output code for x87 ffreep insn. The OPNO argument, which may only
16984 have the values zero or one, indicates the ffreep insn's operand
16985 from the OPERANDS array. */
16989 {
16991 #ifdef HAVE_AS_IX86_FFREEP
16993 #else
16994 {
17004 }
17005 #endif
17008 }
17011 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
17012 should be used. UNORDERED_P is true when fucom should be used. */
17016 {
17022 {
17025 }
17026 else
17027 {
17030 }
17033 {
17037 else
17039 else
17042 else
17044 }
17051 {
17053 {
17056 }
17057 else
17059 }
17062 && stack_top_dies
17065 {
17066 /* If both the top of the 387 stack dies, and the other operand
17067 is also a stack register that dies, then this must be a
17068 `fcompp' float compare */
17071 {
17072 /* There is no double popping fcomi variant. Fortunately,
17073 eflags is immune from the fstp's cc clobbering. */
17076 else
17079 }
17080 else
17081 {
17084 else
17086 }
17087 }
17088 else
17089 {
17090 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
17093 {
17101 NULL,
17102 NULL,
17109 NULL,
17110 NULL,
17111 NULL,
17112 NULL
17113 };
17128 }
17129 }
17131 void
17133 {
17136 #ifdef ASM_QUAD
17139 #else
17141 #endif
17144 }
17146 void
17148 {
17151 #ifdef ASM_QUAD
17154 #else
17156 #endif
17157 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
17163 #if TARGET_MACHO
17165 {
17169 }
17170 #endif
17171 else
17174 }
17175 \f
17176 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
17177 for the target. */
17179 void
17181 {
17182 rtx tmp;
17184 /* We play register width games, which are only valid after reload. */
17187 /* Avoid HImode and its attendant prefix byte. */
17193 {
17196 }
17199 }
17201 /* X is an unchanging MEM. If it is a constant pool reference, return
17202 the constant pool rtx, else NULL. */
17204 rtx
17206 {
17213 }
17215 void
17217 {
17225 {
17226 rtx tmp;
17230 {
17236 }
17239 }
17243 {
17246 rtx tmp;
17251 else
17255 {
17262 }
17263 }
17267 {
17269 {
17270 #if TARGET_MACHO
17271 /* dynamic-no-pic */
17273 {
17274 rtx temp = ((reload_in_progress
17282 }
17284 {
17288 }
17291 else
17292 {
17300 }
17301 /* dynamic-no-pic */
17302 #endif
17303 }
17304 else
17305 {
17309 {
17315 }
17316 }
17317 }
17318 else
17319 {
17330 /* Force large constants in 64bit compilation into register
17331 to get them CSEed. */
17343 {
17344 /* If we are loading a floating point constant to a register,
17345 force the value to memory now, since we'll get better code
17346 out the back end. */
17350 {
17355 }
17356 }
17357 }
17360 }
17362 void
17364 {
17371 /* Force constants other than zero into memory. We do not know how
17372 the instructions used to build constants modify the upper 64 bits
17373 of the register, once we have that information we may be able
17374 to handle some of them more efficiently. */
17383 /* We need to check memory alignment for SSE mode since attribute
17384 can make operands unaligned. */
17389 {
17392 /* ix86_expand_vector_move_misalign() does not like constants ... */
17398 /* ... nor both arguments in memory. */
17406 }
17408 /* Make operand1 a register if it isn't already. */
17412 {
17415 }
17418 }
17420 /* Split 32-byte AVX unaligned load and store if needed. */
17422 static void
17424 {
17425 rtx m;
17429 machine_mode mode;
17432 {
17453 }
17456 {
17458 {
17465 }
17466 /* Normal *mov<mode>_internal pattern will handle
17467 unaligned loads just fine if misaligned_operand
17468 is true, and without the UNSPEC it can be combined
17469 with arithmetic instructions. */
17472 else
17474 }
17476 {
17478 {
17483 }
17484 else
17486 }
17487 else
17489 }
17491 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17492 straight to ix86_expand_vector_move. */
17493 /* Code generation for scalar reg-reg moves of single and double precision data:
17494 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17495 movaps reg, reg
17496 else
17497 movss reg, reg
17498 if (x86_sse_partial_reg_dependency == true)
17499 movapd reg, reg
17500 else
17501 movsd reg, reg
17503 Code generation for scalar loads of double precision data:
17504 if (x86_sse_split_regs == true)
17505 movlpd mem, reg (gas syntax)
17506 else
17507 movsd mem, reg
17509 Code generation for unaligned packed loads of single precision data
17510 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17511 if (x86_sse_unaligned_move_optimal)
17512 movups mem, reg
17514 if (x86_sse_partial_reg_dependency == true)
17515 {
17516 xorps reg, reg
17517 movlps mem, reg
17518 movhps mem+8, reg
17519 }
17520 else
17521 {
17522 movlps mem, reg
17523 movhps mem+8, reg
17524 }
17526 Code generation for unaligned packed loads of double precision data
17527 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17528 if (x86_sse_unaligned_move_optimal)
17529 movupd mem, reg
17531 if (x86_sse_split_regs == true)
17532 {
17533 movlpd mem, reg
17534 movhpd mem+8, reg
17535 }
17536 else
17537 {
17538 movsd mem, reg
17539 movhpd mem+8, reg
17540 }
17541 */
17543 void
17545 {
17554 {
17556 {
17560 {
17562 {
17565 }
17566 else
17568 }
17570 /* FALLTHRU */
17574 {
17589 }
17595 else
17603 }
17606 }
17610 {
17612 {
17616 {
17618 {
17621 }
17622 else
17624 }
17626 /* FALLTHRU */
17636 }
17639 }
17642 {
17643 /* Normal *mov<mode>_internal pattern will handle
17644 unaligned loads just fine if misaligned_operand
17645 is true, and without the UNSPEC it can be combined
17646 with arithmetic instructions. */
17652 /* ??? If we have typed data, then it would appear that using
17653 movdqu is the only way to get unaligned data loaded with
17654 integer type. */
17656 {
17658 {
17661 }
17663 /* We will eventually emit movups based on insn attributes. */
17667 }
17669 {
17670 rtx zero;
17673 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17674 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17676 {
17677 /* We will eventually emit movups based on insn attributes. */
17680 }
17682 /* When SSE registers are split into halves, we can avoid
17683 writing to the top half twice. */
17685 {
17688 }
17689 else
17690 {
17691 /* ??? Not sure about the best option for the Intel chips.
17692 The following would seem to satisfy; the register is
17693 entirely cleared, breaking the dependency chain. We
17694 then store to the upper half, with a dependency depth
17695 of one. A rumor has it that Intel recommends two movsd
17696 followed by an unpacklpd, but this is unconfirmed. And
17697 given that the dependency depth of the unpacklpd would
17698 still be one, I'm not sure why this would be better. */
17700 }
17706 }
17707 else
17708 {
17709 rtx t;
17712 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17713 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17715 {
17717 {
17720 }
17727 }
17731 else
17736 else
17745 }
17746 }
17748 {
17750 {
17753 /* We will eventually emit movups based on insn attributes. */
17755 }
17757 {
17759 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17760 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17762 /* We will eventually emit movups based on insn attributes. */
17764 else
17765 {
17770 }
17771 }
17772 else
17773 {
17778 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17779 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17781 {
17784 }
17785 else
17786 {
17791 }
17792 }
17793 }
17794 else
17796 }
17798 /* Helper function of ix86_fixup_binary_operands to canonicalize
17799 operand order. Returns true if the operands should be swapped. */
17801 static bool
17803 rtx operands[])
17804 {
17809 /* If the operation is not commutative, we can't do anything. */
17813 /* Highest priority is that src1 should match dst. */
17819 /* Next highest priority is that immediate constants come second. */
17825 /* Lowest priority is that memory references should come second. */
17832 }
17835 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17836 destination to use for the operation. If different from the true
17837 destination in operands[0], a copy operation will be required. */
17839 rtx
17841 rtx operands[])
17842 {
17847 /* Canonicalize operand order. */
17849 {
17850 /* It is invalid to swap operands of different modes. */
17854 }
17856 /* Both source operands cannot be in memory. */
17858 {
17859 /* Optimization: Only read from memory once. */
17861 {
17864 }
17867 else
17869 }
17871 /* If the destination is memory, and we do not have matching source
17872 operands, do things in registers. */
17876 /* Source 1 cannot be a constant. */
17880 /* Source 1 cannot be a non-matching memory. */
17884 /* Improve address combine. */
17893 }
17895 /* Similarly, but assume that the destination has already been
17896 set up properly. */
17898 void
17901 {
17904 }
17906 /* Attempt to expand a binary operator. Make the expansion closer to the
17907 actual machine, then just general_operand, which will allow 3 separate
17908 memory references (one output, two input) in a single insn. */
17910 void
17912 rtx operands[])
17913 {
17920 /* Emit the instruction. */
17924 {
17925 /* Reload doesn't know about the flags register, and doesn't know that
17926 it doesn't want to clobber it. We can only do this with PLUS. */
17929 }
17933 {
17934 /* This is going to be an LEA; avoid splitting it later. */
17936 }
17937 else
17938 {
17941 }
17943 /* Fix up the destination if needed. */
17946 }
17948 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
17949 the given OPERANDS. */
17951 void
17953 rtx operands[])
17954 {
17957 {
17960 }
17962 {
17965 }
17966 /* Optimize (__m128i) d | (__m128i) e and similar code
17967 when d and e are float vectors into float vector logical
17968 insn. In C/C++ without using intrinsics there is no other way
17969 to express vector logical operation on float vectors than
17970 to cast them temporarily to integer vectors. */
17972 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17981 {
17982 rtx dst;
17984 {
17993 {
17996 }
17997 else
17998 {
18003 }
18014 }
18015 }
18024 }
18026 /* Return TRUE or FALSE depending on whether the binary operator meets the
18027 appropriate constraints. */
18029 bool
18032 {
18037 /* Both source operands cannot be in memory. */
18041 /* Canonicalize operand order for commutative operators. */
18045 /* If the destination is memory, we must have a matching source operand. */
18049 /* Source 1 cannot be a constant. */
18053 /* Source 1 cannot be a non-matching memory. */
18055 /* Support "andhi/andsi/anddi" as a zero-extending move. */
18063 }
18065 /* Attempt to expand a unary operator. Make the expansion closer to the
18066 actual machine, then just general_operand, which will allow 2 separate
18067 memory references (one output, one input) in a single insn. */
18069 void
18071 rtx operands[])
18072 {
18079 /* If the destination is memory, and we do not have matching source
18080 operands, do things in registers. */
18083 {
18086 else
18088 }
18090 /* When source operand is memory, destination must match. */
18094 /* Emit the instruction. */
18098 {
18099 /* Reload doesn't know about the flags register, and doesn't know that
18100 it doesn't want to clobber it. */
18103 }
18104 else
18105 {
18108 }
18110 /* Fix up the destination if needed. */
18113 }
18115 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
18116 divisor are within the range [0-255]. */
18118 void
18121 {
18130 {
18143 }
18150 /* Use 8bit unsigned divimod if dividend and divisor are within
18151 the range [0-255]. */
18160 pc_rtx);
18165 /* Generate original signed/unsigned divimod. */
18170 /* Branch to the end. */
18174 /* Generate 8bit unsigned divide. */
18176 /* Don't use operands[0] for result of 8bit divide since not all
18177 registers support QImode ZERO_EXTRACT. */
18184 {
18187 }
18188 else
18189 {
18192 }
18194 /* Extract remainder from AH. */
18198 else
18199 {
18200 /* Need a new scratch register since the old one has result
18201 of 8bit divide. */
18205 }
18208 /* Zero extend quotient from AL. */
18214 }
18216 #define LEA_MAX_STALL (3)
18217 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
18219 /* Increase given DISTANCE in half-cycles according to
18220 dependencies between PREV and NEXT instructions.
18221 Add 1 half-cycle if there is no dependency and
18222 go to next cycle if there is some dependecy. */
18224 static unsigned int
18226 {
18242 }
18244 /* Function checks if instruction INSN defines register number
18245 REGNO1 or REGNO2. */
18247 static bool
18249 rtx insn)
18250 {
18251 df_ref def;
18261 }
18263 /* Function checks if instruction INSN uses register number
18264 REGNO as a part of address expression. */
18266 static bool
18268 {
18269 df_ref use;
18276 }
18278 /* Search backward for non-agu definition of register number REGNO1
18279 or register number REGNO2 in basic block starting from instruction
18280 START up to head of basic block or instruction INSN.
18282 Function puts true value into *FOUND var if definition was found
18283 and false otherwise.
18285 Distance in half-cycles between START and found instruction or head
18286 of BB is added to DISTANCE and returned. */
18288 static int
18292 {
18302 {
18304 {
18307 {
18310 {
18313 }
18314 }
18317 }
18322 }
18325 }
18327 /* Search backward for non-agu definition of register number REGNO1
18328 or register number REGNO2 in INSN's basic block until
18329 1. Pass LEA_SEARCH_THRESHOLD instructions, or
18330 2. Reach neighbour BBs boundary, or
18331 3. Reach agu definition.
18332 Returns the distance between the non-agu definition point and INSN.
18333 If no definition point, returns -1. */
18335 static int
18338 {
18349 {
18350 edge e;
18351 edge_iterator ei;
18356 {
18359 }
18365 else
18366 {
18371 {
18372 int bb_dist
18378 {
18385 }
18386 }
18389 }
18390 }
18392 /* get_attr_type may modify recog data. We want to make sure
18393 that recog data is valid for instruction INSN, on which
18394 distance_non_agu_define is called. INSN is unchanged here. */
18401 }
18403 /* Return the distance in half-cycles between INSN and the next
18404 insn that uses register number REGNO in memory address added
18405 to DISTANCE. Return -1 if REGNO0 is set.
18407 Put true value into *FOUND if register usage was found and
18408 false otherwise.
18409 Put true value into *REDEFINED if register redefinition was
18410 found and false otherwise. */
18412 static int
18416 {
18425 {
18428 /* If insn and start belong to the same bb, set prev to insn,
18429 so the call to increase_distance will increase the distance
18430 between insns by 1. */
18432 }
18437 {
18439 {
18442 {
18443 /* Return DISTANCE if OP0 is used in memory
18444 address in NEXT. */
18447 }
18450 {
18451 /* Return -1 if OP0 is set in NEXT. */
18454 }
18457 }
18463 }
18466 }
18468 /* Return the distance between INSN and the next insn that uses
18469 register number REGNO0 in memory address. Return -1 if no such
18470 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18472 static int
18474 {
18486 {
18487 edge e;
18488 edge_iterator ei;
18493 {
18496 }
18502 else
18503 {
18509 {
18510 int bb_dist
18515 {
18522 }
18523 }
18526 }
18527 }
18533 }
18535 /* Define this macro to tune LEA priority vs ADD, it take effect when
18536 there is a dilemma of choicing LEA or ADD
18537 Negative value: ADD is more preferred than LEA
18538 Zero: Netrual
18539 Positive value: LEA is more preferred than ADD*/
18540 #define IX86_LEA_PRIORITY 0
18542 /* Return true if usage of lea INSN has performance advantage
18543 over a sequence of instructions. Instructions sequence has
18544 SPLIT_COST cycles higher latency than lea latency. */
18546 static bool
18549 {
18552 /* For Silvermont if using a 2-source or 3-source LEA for
18553 non-destructive destination purposes, or due to wanting
18554 ability to use SCALE, the use of LEA is justified. */
18556 {
18564 }
18570 {
18571 /* If there is no non AGU operand definition, no AGU
18572 operand usage and split cost is 0 then both lea
18573 and non lea variants have same priority. Currently
18574 we prefer lea for 64 bit code and non lea on 32 bit
18575 code. */
18578 else
18580 }
18582 /* With longer definitions distance lea is more preferable.
18583 Here we change it to take into account splitting cost and
18584 lea priority. */
18587 /* If there is no use in memory addess then we just check
18588 that split cost exceeds AGU stall. */
18592 /* If this insn has both backward non-agu dependence and forward
18593 agu dependence, the one with short distance takes effect. */
18595 }
18597 /* Return true if it is legal to clobber flags by INSN and
18598 false otherwise. */
18600 static bool
18602 {
18604 df_ref use;
18605 bitmap live;
18608 {
18610 {
18617 }
18623 }
18627 }
18629 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18630 move and add to avoid AGU stalls. */
18632 bool
18634 {
18637 /* Check if we need to optimize. */
18641 /* Check it is correct to split here. */
18649 /* We need to split only adds with non destructive
18650 destination operand. */
18653 else
18655 }
18657 /* Return true if we should emit lea instruction instead of mov
18658 instruction. */
18660 bool
18662 {
18665 /* Check if we need to optimize. */
18669 /* Use lea for reg to reg moves only. */
18677 }
18679 /* Return true if we need to split lea into a sequence of
18680 instructions to avoid AGU stalls. */
18682 bool
18684 {
18690 /* Check we need to optimize. */
18694 /* The "at least two components" test below might not catch simple
18695 move or zero extension insns if parts.base is non-NULL and parts.disp
18696 is const0_rtx as the only components in the address, e.g. if the
18697 register is %rbp or %r13. As this test is much cheaper and moves or
18698 zero extensions are the common case, do this check first. */
18704 /* Check if it is OK to split here. */
18711 /* There should be at least two components in the address. */
18716 /* We should not split into add if non legitimate pic
18717 operand is used as displacement. */
18732 /* Compute how many cycles we will add to execution time
18733 if split lea into a sequence of instructions. */
18735 {
18736 /* Have to use mov instruction if non desctructive
18737 destination form is used. */
18741 /* Have to add index to base if both exist. */
18745 /* Have to use shift and adds if scale is 2 or greater. */
18747 {
18752 else
18754 }
18756 /* Have to use add instruction with immediate if
18757 disp is non zero. */
18761 /* Subtract the price of lea. */
18763 }
18767 }
18769 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18770 matches destination. RTX includes clobber of FLAGS_REG. */
18772 static void
18775 {
18782 }
18784 /* Return true if regno1 def is nearest to the insn. */
18786 static bool
18788 {
18795 {
18797 {
18800 }
18806 }
18808 /* None of the regs is defined in the bb. */
18810 }
18812 /* Split lea instructions into a sequence of instructions
18813 which are executed on ALU to avoid AGU stalls.
18814 It is assumed that it is allowed to clobber flags register
18815 at lea position. */
18817 void
18819 {
18835 {
18838 }
18841 {
18844 }
18850 {
18851 /* Case r1 = r1 + ... */
18853 {
18854 /* If we have a case r1 = r1 + C * r2 then we
18855 should use multiplication which is very
18856 expensive. Assume cost model is wrong if we
18857 have such case here. */
18862 }
18863 else
18864 {
18865 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18869 /* Use shift for scaling. */
18878 }
18879 }
18881 {
18884 }
18885 else
18886 {
18888 {
18891 }
18893 {
18896 }
18897 else
18898 {
18903 else
18904 {
18905 rtx tmp1;
18907 /* Find better operand for SET instruction, depending
18908 on which definition is farther from the insn. */
18911 else
18921 }
18924 }
18928 }
18929 }
18931 /* Return true if it is ok to optimize an ADD operation to LEA
18932 operation to avoid flag register consumation. For most processors,
18933 ADD is faster than LEA. For the processors like BONNELL, if the
18934 destination register of LEA holds an actual address which will be
18935 used soon, LEA is better and otherwise ADD is better. */
18937 bool
18939 {
18944 /* If a = b + c, (a!=b && a!=c), must use lea form. */
18952 }
18954 /* Return true if destination reg of SET_BODY is shift count of
18955 USE_BODY. */
18957 static bool
18959 {
18960 rtx set_dest;
18961 rtx shift_rtx;
18964 /* Retrieve destination of SET_BODY. */
18966 {
18975 use_body))
18980 }
18982 /* Retrieve shift count of USE_BODY. */
18984 {
18996 }
19004 {
19007 /* Return true if shift count is dest of SET_BODY. */
19009 {
19010 /* Add check since it can be invoked before register
19011 allocation in pre-reload schedule. */
19017 }
19018 }
19021 }
19023 /* Return true if destination reg of SET_INSN is shift count of
19024 USE_INSN. */
19026 bool
19028 {
19031 }
19033 /* Return TRUE or FALSE depending on whether the unary operator meets the
19034 appropriate constraints. */
19036 bool
19038 machine_mode,
19040 {
19041 /* If one of operands is memory, source and destination must match. */
19047 }
19049 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
19050 are ok, keeping in mind the possible movddup alternative. */
19052 bool
19054 {
19060 }
19062 /* Post-reload splitter for converting an SF or DFmode value in an
19063 SSE register into an unsigned SImode. */
19065 void
19067 {
19068 machine_mode vecmode;
19078 /* Load up the value into the low element. We must ensure that the other
19079 elements are valid floats -- zero is the easiest such value. */
19081 {
19084 else
19086 }
19087 else
19088 {
19093 else
19095 }
19115 else
19120 }
19122 /* Convert an unsigned DImode value into a DFmode, using only SSE.
19123 Expects the 64-bit DImode to be supplied in a pair of integral
19124 registers. Requires SSE2; will use SSE3 if available. For x86_32,
19125 -mfpmath=sse, !optimize_size only. */
19127 void
19129 {
19133 rtx x;
19139 {
19142 }
19143 else
19144 {
19148 }
19156 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
19159 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
19160 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
19161 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
19162 (0x1.0p84 + double(fp_value_hi_xmm)).
19163 Note these exponents differ by 32. */
19167 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
19168 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
19177 /* Add the upper and lower DFmode values together. */
19180 else
19181 {
19185 }
19188 }
19190 /* Not used, but eases macroization of patterns. */
19191 void
19193 {
19195 }
19197 /* Convert an unsigned SImode value into a DFmode. Only currently used
19198 for SSE, but applicable anywhere. */
19200 void
19202 {
19203 REAL_VALUE_TYPE TWO31r;
19218 }
19220 /* Convert a signed DImode value into a DFmode. Only used for SSE in
19221 32-bit mode; otherwise we have a direct convert instruction. */
19223 void
19225 {
19226 REAL_VALUE_TYPE TWO32r;
19244 }
19246 /* Convert an unsigned SImode value into a SFmode, using only SSE.
19247 For x86_32, -mfpmath=sse, !optimize_size only. */
19248 void
19250 {
19251 REAL_VALUE_TYPE ONE16r;
19270 }
19272 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
19273 a vector of unsigned ints VAL to vector of floats TARGET. */
19275 void
19277 {
19279 REAL_VALUE_TYPE TWO16r;
19286 else
19291 OPTAB_DIRECT);
19302 OPTAB_DIRECT);
19304 OPTAB_DIRECT);
19307 }
19309 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
19310 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
19311 This is done by doing just signed conversion if < 0x1p31, and otherwise by
19312 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
19314 rtx
19316 {
19317 REAL_VALUE_TYPE TWO31r;
19332 {
19338 }
19347 OPTAB_DIRECT);
19348 else
19349 {
19355 OPTAB_DIRECT);
19356 }
19359 }
19361 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
19362 then replicate the value for all elements of the vector
19363 register. */
19365 rtx
19367 {
19369 rtvec v;
19370 machine_mode scalar_mode;
19373 {
19406 }
19407 }
19409 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
19410 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
19411 for an SSE register. If VECT is true, then replicate the mask for
19412 all elements of the vector register. If INVERT is true, then create
19413 a mask excluding the sign bit. */
19415 rtx
19417 {
19421 rtx v;
19422 rtx mask;
19424 /* Find the sign bit, sign extended to 2*HWI. */
19426 {
19450 else
19458 {
19461 }
19462 else
19463 {
19464 rtvec vec;
19470 {
19473 }
19474 else
19484 }
19489 }
19494 /* Force this value into the low part of a fp vector constant. */
19503 }
19505 /* Generate code for floating point ABS or NEG. */
19507 void
19509 rtx operands[])
19510 {
19521 {
19527 }
19529 /* NEG and ABS performed with SSE use bitwise mask operations.
19530 Create the appropriate mask now. */
19533 else
19543 {
19545 rtvec par;
19550 else
19551 {
19554 }
19556 }
19557 else
19559 }
19561 /* Expand a copysign operation. Special case operand 0 being a constant. */
19563 void
19565 {
19579 else
19583 {
19590 {
19593 else
19594 {
19598 }
19599 }
19609 else
19613 }
19614 else
19615 {
19625 else
19629 }
19630 }
19632 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19633 be a constant, and so has already been expanded into a vector constant. */
19635 void
19637 {
19653 {
19656 }
19657 }
19659 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19660 so we have to do two masks. */
19662 void
19664 {
19679 {
19680 /* Shouldn't happen often (it's useless, obviously), but when it does
19681 we'd generate incorrect code if we continue below. */
19684 }
19687 {
19698 }
19699 else
19700 {
19702 {
19704 }
19706 {
19710 }
19714 {
19717 }
19719 {
19724 }
19726 }
19730 }
19732 /* Return TRUE or FALSE depending on whether the first SET in INSN
19733 has source and destination with matching CC modes, and that the
19734 CC mode is at least as constrained as REQ_MODE. */
19736 bool
19738 {
19739 rtx set;
19740 machine_mode set_mode;
19750 {
19760 /* FALLTHRU */
19764 /* FALLTHRU */
19768 /* FALLTHRU */
19782 }
19785 }
19787 /* Generate insn patterns to do an integer compare of OPERANDS. */
19789 static rtx
19791 {
19792 machine_mode cmpmode;
19798 /* This is very simple, but making the interface the same as in the
19799 FP case makes the rest of the code easier. */
19803 /* Return the test that should be put into the flags user, i.e.
19804 the bcc, scc, or cmov instruction. */
19806 }
19808 /* Figure out whether to use ordered or unordered fp comparisons.
19809 Return the appropriate mode to use. */
19811 machine_mode
19813 {
19814 /* ??? In order to make all comparisons reversible, we do all comparisons
19815 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19816 all forms trapping and nontrapping comparisons, we can make inequality
19817 comparisons trapping again, since it results in better code when using
19818 FCOM based compares. */
19820 }
19822 machine_mode
19824 {
19828 {
19831 }
19834 {
19835 /* Only zero flag is needed. */
19839 /* Codes needing carry flag. */
19842 /* Detect overflow checks. They need just the carry flag. */
19846 else
19851 /* Codes possibly doable only with sign flag when
19852 comparing against zero. */
19857 else
19858 /* For other cases Carry flag is not required. */
19860 /* Codes doable only with sign flag when comparing
19861 against zero, but we miss jump instruction for it
19862 so we need to use relational tests against overflow
19863 that thus needs to be zero. */
19868 else
19870 /* strcmp pattern do (use flags) and combine may ask us for proper
19871 mode. */
19876 }
19877 }
19879 /* Return the fixed registers used for condition codes. */
19881 static bool
19883 {
19887 }
19889 /* If two condition code modes are compatible, return a condition code
19890 mode which is compatible with both. Otherwise, return
19891 VOIDmode. */
19893 static machine_mode
19895 {
19912 {
19926 {
19940 }
19944 /* These are only compatible with themselves, which we already
19945 checked above. */
19947 }
19948 }
19951 /* Return a comparison we can do and that it is equivalent to
19952 swap_condition (code) apart possibly from orderedness.
19953 But, never change orderedness if TARGET_IEEE_FP, returning
19954 UNKNOWN in that case if necessary. */
19956 static enum rtx_code
19958 {
19960 {
19971 }
19972 }
19974 /* Return cost of comparison CODE using the best strategy for performance.
19975 All following functions do use number of instructions as a cost metrics.
19976 In future this should be tweaked to compute bytes for optimize_size and
19977 take into account performance of various instructions on various CPUs. */
19979 static int
19981 {
19984 /* The cost of code using bit-twiddling on %ah. */
19986 {
20009 }
20012 {
20019 }
20020 }
20022 /* Return strategy to use for floating-point. We assume that fcomi is always
20023 preferrable where available, since that is also true when looking at size
20024 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
20026 enum ix86_fpcmp_strategy
20028 {
20029 /* Do fcomi/sahf based test when profitable. */
20038 }
20040 /* Swap, force into registers, or otherwise massage the two operands
20041 to a fp comparison. The operands are updated in place; the new
20042 comparison code is returned. */
20044 static enum rtx_code
20046 {
20052 /* All of the unordered compare instructions only work on registers.
20053 The same is true of the fcomi compare instructions. The XFmode
20054 compare instructions require registers except when comparing
20055 against zero or when converting operand 1 from fixed point to
20056 floating point. */
20065 {
20068 }
20069 else
20070 {
20071 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
20072 things around if they appear profitable, otherwise force op0
20073 into a register. */
20079 {
20082 {
20085 }
20086 }
20092 {
20097 {
20100 }
20101 else
20103 }
20104 }
20106 /* Try to rearrange the comparison to make it cheaper. */
20110 {
20115 }
20120 }
20122 /* Convert comparison codes we use to represent FP comparison to integer
20123 code that will result in proper branch. Return UNKNOWN if no such code
20124 is available. */
20126 enum rtx_code
20128 {
20130 {
20153 }
20154 }
20156 /* Generate insn patterns to do a floating point compare of OPERANDS. */
20158 static rtx
20160 {
20167 /* Do fcomi/sahf based test when profitable. */
20169 {
20174 tmp);
20182 tmp);
20191 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
20198 /* In the unordered case, we have to check C2 for NaN's, which
20199 doesn't happen to work out to anything nice combination-wise.
20200 So do some bit twiddling on the value we've got in AH to come
20201 up with an appropriate set of condition codes. */
20205 {
20209 {
20212 }
20213 else
20214 {
20220 }
20225 {
20230 }
20231 else
20232 {
20235 }
20240 {
20243 }
20244 else
20245 {
20249 }
20254 {
20260 }
20261 else
20262 {
20265 }
20270 {
20275 }
20276 else
20277 {
20280 }
20285 {
20290 }
20291 else
20292 {
20295 }
20309 }
20314 }
20316 /* Return the test that should be put into the flags user, i.e.
20317 the bcc, scc, or cmov instruction. */
20320 const0_rtx);
20321 }
20323 static rtx
20325 {
20326 rtx ret;
20332 {
20335 }
20336 else
20340 }
20342 void
20344 {
20346 rtx tmp;
20349 {
20356 simple:
20360 pc_rtx);
20368 /* Expand DImode branch into multiple compare+branch. */
20369 {
20373 machine_mode submode;
20376 {
20379 }
20386 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
20387 avoid two branches. This costs one extra insn, so disable when
20388 optimizing for size. */
20393 {
20411 }
20413 /* Otherwise, if we are doing less-than or greater-or-equal-than,
20414 op1 is a constant and the low word is zero, then we can just
20415 examine the high word. Similarly for low word -1 and
20416 less-or-equal-than or greater-than. */
20420 {
20423 {
20426 }
20430 {
20433 }
20437 }
20439 /* Otherwise, we need two or three jumps. */
20448 {
20462 }
20464 /*
20465 * a < b =>
20466 * if (hi(a) < hi(b)) goto true;
20467 * if (hi(a) > hi(b)) goto false;
20468 * if (lo(a) < lo(b)) goto true;
20469 * false:
20470 */
20482 }
20487 }
20488 }
20490 /* Split branch based on floating point condition. */
20491 void
20494 {
20495 rtx condition;
20496 rtx i;
20499 {
20504 }
20507 tmp);
20515 }
20517 void
20519 {
20520 rtx ret;
20527 }
20529 /* Expand comparison setting or clearing carry flag. Return true when
20530 successful and set pop for the operation. */
20531 static bool
20533 {
20534 machine_mode mode =
20537 /* Do not handle double-mode compares that go through special path. */
20542 {
20543 rtx compare_op;
20548 /* Shortcut: following common codes never translate
20549 into carry flag compares. */
20554 /* These comparisons require zero flag; swap operands so they won't. */
20557 {
20560 }
20562 /* Try to expand the comparison and verify that we end up with
20563 carry flag based comparison. This fails to be true only when
20564 we decide to expand comparison using arithmetic that is not
20565 too common scenario. */
20574 else
20583 }
20589 {
20594 /* Convert a==0 into (unsigned)a<1. */
20603 /* Convert a>b into b<a or a>=b-1. */
20607 {
20609 /* Bail out on overflow. We still can swap operands but that
20610 would force loading of the constant into register. */
20615 }
20616 else
20617 {
20620 }
20623 /* Convert a>=0 into (unsigned)a<0x80000000. */
20641 }
20642 /* Swapping operands may cause constant to appear as first operand. */
20644 {
20648 }
20652 }
20654 bool
20656 {
20659 rtx compare_op;
20681 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20682 HImode insns, we'd be swallowed in word prefix ops. */
20688 {
20692 HOST_WIDE_INT diff;
20695 /* Sign bit compares are better done using shifts than we do by using
20696 sbb. */
20699 {
20700 /* Detect overlap between destination and compare sources. */
20704 {
20705 rtx flags;
20714 {
20716 compare_code
20718 }
20720 /* To simplify rest of code, restrict to the GEU case. */
20722 {
20728 }
20729 else
20730 {
20733 reverse_condition_maybe_unordered
20735 else
20738 }
20747 else
20750 }
20751 else
20752 {
20755 else
20756 {
20761 }
20763 }
20766 {
20767 /*
20768 * cmpl op0,op1
20769 * sbbl dest,dest
20770 * [addl dest, ct]
20771 *
20772 * Size 5 - 8.
20773 */
20778 }
20780 {
20781 /*
20782 * cmpl op0,op1
20783 * sbbl dest,dest
20784 * orl $ct, dest
20785 *
20786 * Size 8.
20787 */
20791 }
20793 {
20794 /*
20795 * cmpl op0,op1
20796 * sbbl dest,dest
20797 * notl dest
20798 * [addl dest, cf]
20799 *
20800 * Size 8 - 11.
20801 */
20807 }
20808 else
20809 {
20810 /*
20811 * cmpl op0,op1
20812 * sbbl dest,dest
20813 * [notl dest]
20814 * andl cf - ct, dest
20815 * [addl dest, ct]
20816 *
20817 * Size 8 - 11.
20818 */
20821 {
20825 }
20835 }
20841 }
20844 {
20851 {
20854 /* We may be reversing unordered compare to normal compare, that
20855 is not valid in general (we may convert non-trapping condition
20856 to trapping one), however on i386 we currently emit all
20857 comparisons unordered. */
20860 }
20861 else
20862 {
20865 }
20866 }
20871 {
20876 {
20881 }
20882 }
20884 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20888 {
20889 /* If lea code below could be used, only optimize
20890 if it results in a 2 insn sequence. */
20896 {
20897 /*
20898 * notl op1 (if necessary)
20899 * sarl $31, op1
20900 * orl cf, op1
20901 */
20903 {
20907 }
20918 }
20919 }
20927 {
20928 /*
20929 * xorl dest,dest
20930 * cmpl op1,op2
20931 * setcc dest
20932 * lea cf(dest*(ct-cf)),dest
20933 *
20934 * Size 14.
20935 *
20936 * This also catches the degenerate setcc-only case.
20937 */
20939 rtx tmp;
20945 /* On x86_64 the lea instruction operates on Pmode, so we need
20946 to get arithmetics done in proper mode to match. */
20949 else
20950 {
20951 rtx out1;
20954 nops++;
20956 {
20958 nops++;
20959 }
20960 }
20962 {
20964 nops++;
20965 }
20967 {
20970 else
20972 }
20977 }
20979 /*
20980 * General case: Jumpful:
20981 * xorl dest,dest cmpl op1, op2
20982 * cmpl op1, op2 movl ct, dest
20983 * setcc dest jcc 1f
20984 * decl dest movl cf, dest
20985 * andl (cf-ct),dest 1:
20986 * addl ct,dest
20987 *
20988 * Size 20. Size 14.
20989 *
20990 * This is reasonably steep, but branch mispredict costs are
20991 * high on modern cpus, so consider failing only if optimizing
20992 * for space.
20993 */
20998 {
21000 {
21007 {
21010 /* We may be reversing unordered compare to normal compare,
21011 that is not valid in general (we may convert non-trapping
21012 condition to trapping one), however on i386 we currently
21013 emit all comparisons unordered. */
21015 }
21016 else
21017 {
21021 }
21022 }
21025 {
21026 /* notl op1 (if needed)
21027 sarl $31, op1
21028 andl (cf-ct), op1
21029 addl ct, op1
21031 For x < 0 (resp. x <= -1) there will be no notl,
21032 so if possible swap the constants to get rid of the
21033 complement.
21034 True/false will be -1/0 while code below (store flag
21035 followed by decrement) is 0/-1, so the constants need
21036 to be exchanged once more. */
21039 {
21042 }
21043 else
21047 }
21048 else
21049 {
21053 constm1_rtx,
21055 }
21067 }
21068 }
21071 {
21072 /* Try a few things more with specific constants and a variable. */
21074 optab op;
21080 /* If one of the two operands is an interesting constant, load a
21081 constant with the above and mask it in with a logical operation. */
21084 {
21090 else
21092 }
21094 {
21100 else
21102 }
21103 else
21110 /* Recurse to get the constant loaded. */
21114 /* Mask in the interesting variable. */
21116 OPTAB_WIDEN);
21121 }
21123 /*
21124 * For comparison with above,
21125 *
21126 * movl cf,dest
21127 * movl ct,tmp
21128 * cmpl op1,op2
21129 * cmovcc tmp,dest
21130 *
21131 * Size 15.
21132 */
21154 }
21156 /* Swap, force into registers, or otherwise massage the two operands
21157 to an sse comparison with a mask result. Thus we differ a bit from
21158 ix86_prepare_fp_compare_args which expects to produce a flags result.
21160 The DEST operand exists to help determine whether to commute commutative
21161 operators. The POP0/POP1 operands are updated in place. The new
21162 comparison code is returned, or UNKNOWN if not implementable. */
21164 static enum rtx_code
21167 {
21169 {
21172 /* AVX supports all the needed comparisons. */
21175 /* We have no LTGT as an operator. We could implement it with
21176 NE & ORDERED, but this requires an extra temporary. It's
21177 not clear that it's worth it. */
21184 /* These are supported directly. */
21191 /* AVX has 3 operand comparisons, no need to swap anything. */
21194 /* For commutative operators, try to canonicalize the destination
21195 operand to be first in the comparison - this helps reload to
21196 avoid extra moves. */
21199 /* FALLTHRU */
21205 /* These are not supported directly before AVX, and furthermore
21206 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
21207 comparison operands to transform into something that is
21208 supported. */
21215 }
21218 }
21220 /* Detect conditional moves that exactly match min/max operational
21221 semantics. Note that this is IEEE safe, as long as we don't
21222 interchange the operands.
21224 Returns FALSE if this conditional move doesn't match a MIN/MAX,
21225 and TRUE if the operation is successful and instructions are emitted. */
21227 static bool
21230 {
21231 machine_mode mode;
21233 rtx tmp;
21236 ;
21239 else
21246 else
21251 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
21252 but MODE may be a vector mode and thus not appropriate. */
21254 {
21256 rtvec v;
21261 }
21262 else
21263 {
21266 }
21270 }
21272 /* Expand an sse vector comparison. Return the register with the result. */
21274 static rtx
21277 {
21281 /* In general case result of comparison can differ from operands' type. */
21282 machine_mode cmp_mode;
21284 /* In AVX512F the result of comparison is an integer mask. */
21286 rtx x;
21289 {
21294 }
21295 else
21308 /* Compare patterns for int modes are unspec in AVX512F only. */
21310 {
21314 {
21323 }
21326 {
21329 }
21330 }
21334 {
21337 }
21338 else
21342 }
21344 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
21345 operations. This is used for both scalar and vector conditional moves. */
21347 static void
21349 {
21353 /* In AVX512F the result of comparison is an integer mask. */
21361 {
21363 }
21366 {
21370 }
21373 {
21378 }
21381 {
21385 }
21388 {
21396 op_true,
21397 op_false)));
21398 }
21399 else
21400 {
21410 {
21424 {
21431 }
21446 {
21453 }
21477 }
21480 {
21484 }
21485 else
21486 {
21492 else
21504 }
21505 }
21506 }
21508 /* Expand a floating-point conditional move. Return true if successful. */
21510 bool
21512 {
21520 {
21521 machine_mode cmode;
21523 /* Since we've no cmove for sse registers, don't force bad register
21524 allocation just to gain access to it. Deny movcc when the
21525 comparison mode doesn't match the move mode. */
21544 }
21551 /* The floating point conditional move instructions don't directly
21552 support conditions resulting from a signed integer comparison. */
21556 {
21561 }
21568 }
21570 /* Expand a floating-point vector conditional move; a vcond operation
21571 rather than a movcc operation. */
21573 bool
21575 {
21577 rtx cmp;
21582 {
21583 rtx temp;
21585 {
21602 }
21604 OPTAB_DIRECT);
21607 }
21617 }
21619 /* Expand a signed/unsigned integral vector conditional move. */
21621 bool
21623 {
21633 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21634 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21643 {
21647 {
21653 }
21656 {
21662 }
21663 }
21672 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21676 ;
21677 else
21678 {
21679 /* Canonicalize the comparison to EQ, GT, GTU. */
21681 {
21698 /* FALLTHRU */
21708 }
21710 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21712 {
21714 {
21716 /* SSE4.1 supports EQ. */
21723 /* SSE4.2 supports GT/GTU. */
21730 }
21731 }
21733 /* Unsigned parallel compare is not supported by the hardware.
21734 Play some tricks to turn this into a signed comparison
21735 against 0. */
21737 {
21741 {
21748 {
21753 {
21762 }
21763 /* Subtract (-(INT MAX) - 1) from both operands to make
21764 them signed. */
21775 }
21784 /* Perform a parallel unsigned saturating subtraction. */
21797 }
21798 }
21799 }
21801 /* Allow the comparison to be done in one mode, but the movcc to
21802 happen in another mode. */
21804 {
21807 }
21808 else
21809 {
21815 }
21820 }
21822 /* AVX512F does support 64-byte integer vector operations,
21823 thus the longest vector we are faced with is V64QImode. */
21824 #define MAX_VECT_LEN 64
21826 struct expand_vec_perm_d
21827 {
21830 machine_mode vmode;
21834 };
21836 static bool
21839 {
21840 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21841 expander, so args are either in d, or in op0, op1 etc. */
21847 {
21878 {
21881 }
21885 {
21888 }
21892 {
21895 }
21911 {
21914 }
21918 {
21921 }
21925 {
21928 }
21932 }
21937 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21938 expander, so args are either in d, or in op0, op1 etc. */
21940 {
21948 }
21952 }
21954 /* Expand a variable vector permutation. */
21956 void
21958 {
21969 /* Number of elements in the vector. */
21978 {
21980 {
21981 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
21982 an constant shuffle operand. With a tiny bit of effort we can
21983 use VPERMD instead. A re-interpretation stall for V4DFmode is
21984 unfortunate but there's no avoiding it.
21985 Similarly for V16HImode we don't have instructions for variable
21986 shuffling, while for V32QImode we can use after preparing suitable
21987 masks vpshufb; vpshufb; vpermq; vpor. */
21990 {
21994 }
21995 else
21996 {
22000 }
22003 /* Replicate the low bits of the V4DImode mask into V8SImode:
22004 mask = { A B C D }
22005 t1 = { A A B B C C D D }. */
22013 else
22016 /* Multiply the shuffle indicies by two. */
22018 OPTAB_DIRECT);
22020 /* Add one to the odd shuffle indicies:
22021 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
22023 {
22026 }
22030 OPTAB_DIRECT);
22032 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
22037 }
22040 {
22042 /* The VPERMD and VPERMPS instructions already properly ignore
22043 the high bits of the shuffle elements. No need for us to
22044 perform an AND ourselves. */
22046 {
22051 }
22052 else
22053 {
22059 }
22066 else
22067 {
22073 }
22077 /* By combining the two 128-bit input vectors into one 256-bit
22078 input vector, we can use VPERMD and VPERMPS for the full
22079 two-operand shuffle. */
22111 /* From mask create two adjusted masks, which contain the same
22112 bits as mask in the low 7 bits of each vector element.
22113 The first mask will have the most significant bit clear
22114 if it requests element from the same 128-bit lane
22115 and MSB set if it requests element from the other 128-bit lane.
22116 The second mask will have the opposite values of the MSB,
22117 and additionally will have its 128-bit lanes swapped.
22118 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
22119 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
22120 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
22121 stands for other 12 bytes. */
22122 /* The bit whether element is from the same lane or the other
22123 lane is bit 4, so shift it up by 3 to the MSB position. */
22127 /* Clear MSB bits from the mask just in case it had them set. */
22129 /* After this t1 will have MSB set for elements from other lane. */
22131 /* Clear bits other than MSB. */
22133 /* Or in the lower bits from mask into t3. */
22135 /* And invert MSB bits in t1, so MSB is set for elements from the same
22136 lane. */
22138 /* Swap 128-bit lanes in t3. */
22143 /* And or in the lower bits from mask into t1. */
22146 {
22147 /* Each of these shuffles will put 0s in places where
22148 element from the other 128-bit lane is needed, otherwise
22149 will shuffle in the requested value. */
22153 /* For t3 the 128-bit lanes are swapped again. */
22158 /* And oring both together leads to the result. */
22165 }
22168 /* Similarly to the above one_operand_shuffle code,
22169 just for repeated twice for each operand. merge_two:
22170 code will merge the two results together. */
22194 }
22195 }
22198 {
22199 /* The XOP VPPERM insn supports three inputs. By ignoring the
22200 one_operand_shuffle special case, we avoid creating another
22201 set of constant vectors in memory. */
22204 /* mask = mask & {2*w-1, ...} */
22206 }
22207 else
22208 {
22209 /* mask = mask & {w-1, ...} */
22211 }
22219 /* For non-QImode operations, convert the word permutation control
22220 into a byte permutation control. */
22222 {
22227 /* Convert mask to vector of chars. */
22230 /* Replicate each of the input bytes into byte positions:
22231 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
22232 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
22233 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
22240 else
22243 /* Convert it into the byte positions by doing
22244 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
22250 }
22252 /* The actual shuffle operations all operate on V16QImode. */
22257 {
22264 }
22266 {
22273 }
22274 else
22275 {
22279 /* Shuffle the two input vectors independently. */
22285 merge_two:
22286 /* Then merge them together. The key is whether any given control
22287 element contained a bit set that indicates the second word. */
22291 {
22292 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
22293 more shuffle to convert the V2DI input mask into a V4SI
22294 input mask. At which point the masking that expand_int_vcond
22295 will work as desired. */
22303 }
22325 }
22326 }
22328 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
22329 true if we should do zero extension, else sign extension. HIGH_P is
22330 true if we want the N/2 high elements, else the low elements. */
22332 void
22334 {
22336 rtx tmp;
22339 {
22345 {
22349 else
22352 extract
22358 else
22361 extract
22367 else
22370 extract
22376 else
22379 extract
22385 else
22388 extract
22394 else
22397 extract
22403 else
22409 else
22415 else
22420 }
22423 {
22426 }
22428 {
22429 /* Shift higher 8 bytes to lower 8 bytes. */
22434 }
22435 else
22439 }
22440 else
22441 {
22445 {
22449 else
22455 else
22461 else
22466 }
22470 else
22477 }
22478 }
22480 /* Expand conditional increment or decrement using adb/sbb instructions.
22481 The default case using setcc followed by the conditional move can be
22482 done by generic code. */
22483 bool
22485 {
22487 rtx flags;
22489 rtx compare_op;
22492 machine_mode mode;
22507 {
22510 }
22513 {
22517 reverse_condition_maybe_unordered
22519 else
22521 }
22525 /* Construct either adc or sbb insn. */
22527 {
22529 {
22544 }
22545 }
22546 else
22547 {
22549 {
22564 }
22565 }
22569 }
22572 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22573 but works for floating pointer parameters and nonoffsetable memories.
22574 For pushes, it returns just stack offsets; the values will be saved
22575 in the right order. Maximally three parts are generated. */
22577 static int
22579 {
22584 else
22590 /* Optimize constant pool reference to immediates. This is used by fp
22591 moves, that force all constants to memory to allow combining. */
22593 {
22597 }
22600 {
22601 /* The only non-offsetable memories we handle are pushes. */
22610 }
22613 {
22615 /* Caution: if we looked through a constant pool memory above,
22616 the operand may actually have a different mode now. That's
22617 ok, since we want to pun this all the way back to an integer. */
22621 }
22624 {
22627 else
22628 {
22632 {
22636 }
22638 {
22643 }
22645 {
22646 REAL_VALUE_TYPE r;
22651 {
22658 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22659 long double may not be 80-bit. */
22668 }
22671 }
22672 else
22674 }
22675 }
22676 else
22677 {
22681 {
22684 {
22688 }
22690 {
22694 }
22696 {
22697 REAL_VALUE_TYPE r;
22703 /* Do not use shift by 32 to avoid warning on 32bit systems. */
22706 = gen_int_mode
22709 DImode);
22710 else
22717 = gen_int_mode
22720 DImode);
22721 else
22723 }
22724 else
22726 }
22727 }
22730 }
22732 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22733 Return false when normal moves are needed; true when all required
22734 insns have been emitted. Operands 2-4 contain the input values
22735 int the correct order; operands 5-7 contain the output values. */
22737 void
22739 {
22747 /* The DFmode expanders may ask us to move double.
22748 For 64bit target this is single move. By hiding the fact
22749 here we simplify i386.md splitters. */
22751 {
22752 /* Optimize constant pool reference to immediates. This is used by
22753 fp moves, that force all constants to memory to allow combining. */
22760 {
22763 }
22764 else
22769 }
22771 /* The only non-offsettable memory we handle is push. */
22774 else
22781 /* When emitting push, take care for source operands on the stack. */
22784 {
22787 /* Compensate for the stack decrement by 4. */
22792 /* src_base refers to the stack pointer and is
22793 automatically decreased by emitted push. */
22797 }
22799 /* We need to do copy in the right order in case an address register
22800 of the source overlaps the destination. */
22802 {
22803 rtx tmp;
22806 {
22810 collisions++;
22811 }
22813 /* Collision in the middle part can be handled by reordering. */
22815 {
22818 }
22822 {
22824 {
22827 }
22828 else
22829 {
22832 }
22833 }
22835 /* If there are more collisions, we can't handle it by reordering.
22836 Do an lea to the last part and use only one colliding move. */
22838 {
22839 rtx base;
22845 /* Handle the case when the last part isn't valid for lea.
22846 Happens in 64-bit mode storing the 12-byte XFmode. */
22853 {
22856 }
22857 }
22858 }
22861 {
22863 {
22865 {
22870 }
22872 {
22875 }
22876 }
22877 else
22878 {
22879 /* In 64bit mode we don't have 32bit push available. In case this is
22880 register, it is OK - we will just use larger counterpart. We also
22881 retype memory - these comes from attempt to avoid REX prefix on
22882 moving of second half of TFmode value. */
22884 {
22886 {
22897 }
22901 }
22902 }
22906 }
22908 /* Choose correct order to not overwrite the source before it is copied. */
22918 {
22920 {
22923 }
22924 }
22925 else
22926 {
22928 {
22931 }
22932 }
22934 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
22936 {
22945 }
22951 }
22953 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
22954 left shift by a constant, either using a single shift or
22955 a sequence of add instructions. */
22957 static void
22959 {
22965 {
22969 }
22970 else
22971 {
22974 }
22975 }
22977 void
22979 {
22988 {
22993 {
22999 }
23000 else
23001 {
23009 }
23011 }
23018 {
23019 /* Assuming we've chosen a QImode capable registers, then 1 << N
23020 can be done with two 32/64-bit shifts, no branches, no cmoves. */
23022 {
23038 }
23040 /* Otherwise, we can get the same results by manually performing
23041 a bit extract operation on bit 5/6, and then performing the two
23042 shifts. The two methods of getting 0/1 into low/high are exactly
23043 the same size. Avoiding the shift in the bit extract case helps
23044 pentium4 a bit; no one else seems to care much either way. */
23045 else
23046 {
23047 machine_mode half_mode;
23051 HOST_WIDE_INT bits;
23052 rtx x;
23055 {
23061 }
23062 else
23063 {
23069 }
23073 else
23081 }
23086 }
23089 {
23090 /* For -1 << N, we can avoid the shld instruction, because we
23091 know that we're shifting 0...31/63 ones into a -1. */
23095 else
23097 }
23098 else
23099 {
23107 }
23112 {
23118 }
23119 else
23120 {
23125 }
23126 }
23128 void
23130 {
23140 {
23145 {
23151 }
23153 {
23162 }
23163 else
23164 {
23172 }
23173 }
23174 else
23175 {
23187 {
23195 scratch));
23196 }
23197 else
23198 {
23203 }
23204 }
23205 }
23207 void
23209 {
23219 {
23224 {
23231 }
23232 else
23233 {
23241 }
23242 }
23243 else
23244 {
23256 {
23262 scratch));
23263 }
23264 else
23265 {
23270 }
23271 }
23272 }
23274 /* Predict just emitted jump instruction to be taken with probability PROB. */
23275 static void
23277 {
23281 }
23283 /* Helper function for the string operations below. Dest VARIABLE whether
23284 it is aligned to VALUE bytes. If true, jump to the label. */
23287 {
23292 else
23298 else
23301 }
23303 /* Adjust COUNTER by the VALUE. */
23304 static void
23306 {
23311 }
23313 /* Zero extend possibly SImode EXP to Pmode register. */
23314 rtx
23316 {
23318 }
23320 /* Divide COUNTREG by SCALE. */
23321 static rtx
23323 {
23324 rtx sc;
23336 }
23338 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
23339 DImode for constant loop counts. */
23341 static machine_mode
23343 {
23351 }
23353 /* Copy the address to a Pmode register. This is used for x32 to
23354 truncate DImode TLS address to a SImode register. */
23356 static rtx
23358 {
23361 else
23362 {
23365 }
23366 }
23368 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
23369 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
23370 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
23371 memory by VALUE (supposed to be in MODE).
23373 The size is rounded down to whole number of chunk size moved at once.
23374 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
23377 static void
23382 {
23389 rtx size;
23398 /* Those two should combine. */
23400 {
23404 }
23411 /* This assert could be relaxed - in this case we'll need to compute
23412 smallest power of two, containing in PIECE_SIZE_N and pass it to
23413 offset_address. */
23419 {
23423 /* When unrolling for chips that reorder memory reads and writes,
23424 we can save registers by using single temporary.
23425 Also using 4 temporaries is overkill in 32bit mode. */
23427 {
23429 {
23431 {
23432 destmem =
23434 srcmem =
23436 }
23438 }
23439 }
23440 else
23441 {
23445 {
23448 {
23449 srcmem =
23451 }
23453 }
23455 {
23457 {
23458 destmem =
23460 }
23462 }
23463 }
23464 }
23465 else
23467 {
23469 destmem =
23472 }
23482 {
23488 else
23490 }
23491 else
23499 {
23504 }
23506 }
23508 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
23509 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
23510 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
23511 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
23512 ORIG_VALUE is the original value passed to memset to fill the memory with.
23513 Other arguments have same meaning as for previous function. */
23515 static void
23518 rtx count,
23520 {
23521 rtx destexp;
23522 rtx srcexp;
23523 rtx countreg;
23524 HOST_WIDE_INT rounded_count;
23526 /* If possible, it is shorter to use rep movs.
23527 TODO: Maybe it is better to move this logic to decide_alg. */
23538 {
23542 }
23543 else
23546 {
23551 }
23556 {
23559 }
23560 else
23561 {
23565 {
23569 }
23570 else
23573 {
23578 }
23579 else
23580 {
23583 }
23586 }
23587 }
23589 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23590 DESTMEM.
23591 SRC is passed by pointer to be updated on return.
23592 Return value is updated DST. */
23593 static rtx
23595 HOST_WIDE_INT size_to_move)
23596 {
23599 machine_mode move_mode;
23602 /* Find the widest mode in which we could perform moves.
23603 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23604 it until move of such size is supported. */
23609 {
23613 }
23615 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23616 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23618 {
23623 {
23627 }
23628 }
23634 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23638 {
23639 /* We move from memory to memory, so we'll need to do it via
23640 a temporary register. */
23651 piece_size);
23653 piece_size);
23654 }
23656 /* Update DST and SRC rtx. */
23659 }
23661 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23662 static void
23665 {
23668 {
23673 /* For now MAX_SIZE should be a power of 2. This assert could be
23674 relaxed, but it'll require a bit more complicated epilogue
23675 expanding. */
23678 {
23681 }
23683 }
23685 {
23691 }
23693 /* When there are stringops, we can cheaply increase dest and src pointers.
23694 Otherwise we save code size by maintaining offset (zero is readily
23695 available from preceding rep operation) and using x86 addressing modes.
23696 */
23698 {
23700 {
23707 }
23709 {
23716 }
23718 {
23725 }
23726 }
23727 else
23728 {
23730 rtx tmp;
23733 {
23744 }
23746 {
23759 }
23761 {
23770 }
23771 }
23772 }
23774 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23775 with value PROMOTED_VAL.
23776 SRC is passed by pointer to be updated on return.
23777 Return value is updated DST. */
23778 static rtx
23780 HOST_WIDE_INT size_to_move)
23781 {
23784 machine_mode move_mode;
23787 /* Find the widest mode in which we could perform moves.
23788 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23789 it until move of such size is supported. */
23794 {
23797 }
23804 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23808 {
23810 {
23813 piece_size);
23815 }
23823 piece_size);
23824 }
23826 /* Update DST rtx. */
23828 }
23829 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23830 static void
23833 {
23834 count =
23840 }
23842 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23843 static void
23846 {
23847 rtx dest;
23850 {
23855 /* For now MAX_SIZE should be a power of 2. This assert could be
23856 relaxed, but it'll require a bit more complicated epilogue
23857 expanding. */
23860 {
23862 {
23865 else
23867 }
23868 }
23870 }
23872 {
23875 }
23877 {
23880 {
23885 }
23886 else
23887 {
23896 }
23899 }
23901 {
23904 {
23907 }
23908 else
23909 {
23914 }
23917 }
23919 {
23925 }
23927 {
23933 }
23935 {
23941 }
23942 }
23944 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
23945 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
23946 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
23947 ignored.
23948 Return value is updated DESTMEM. */
23949 static rtx
23954 {
23957 {
23959 {
23962 {
23965 else
23967 }
23968 else
23974 }
23975 }
23977 }
23979 /* Test if COUNT&SIZE is nonzero and if so, expand movme
23980 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
23981 and jump to DONE_LABEL. */
23982 static void
23988 {
23991 rtx modesize;
23994 /* If we do not have vector value to copy, we must reduce size. */
23996 {
23998 {
24003 }
24004 else
24006 }
24007 else
24008 {
24009 /* Choose appropriate vector mode. */
24015 }
24020 {
24023 else
24024 {
24027 }
24029 }
24035 {
24039 }
24041 {
24044 else
24045 {
24048 }
24050 }
24056 }
24058 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
24059 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
24060 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
24061 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
24062 DONE_LABEL is a label after the whole copying sequence. The label is created
24063 on demand if *DONE_LABEL is NULL.
24064 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
24065 bounds after the initial copies.
24067 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
24068 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
24069 we will dispatch to a library call for large blocks.
24071 In pseudocode we do:
24073 if (COUNT < SIZE)
24074 {
24075 Assume that SIZE is 4. Bigger sizes are handled analogously
24076 if (COUNT & 4)
24077 {
24078 copy 4 bytes from SRCPTR to DESTPTR
24079 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
24080 goto done_label
24081 }
24082 if (!COUNT)
24083 goto done_label;
24084 copy 1 byte from SRCPTR to DESTPTR
24085 if (COUNT & 2)
24086 {
24087 copy 2 bytes from SRCPTR to DESTPTR
24088 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
24089 }
24090 }
24091 else
24092 {
24093 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
24094 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
24096 OLD_DESPTR = DESTPTR;
24097 Align DESTPTR up to DESIRED_ALIGN
24098 SRCPTR += DESTPTR - OLD_DESTPTR
24099 COUNT -= DEST_PTR - OLD_DESTPTR
24100 if (DYNAMIC_CHECK)
24101 Round COUNT down to multiple of SIZE
24102 << optional caller supplied zero size guard is here >>
24103 << optional caller suppplied dynamic check is here >>
24104 << caller supplied main copy loop is here >>
24105 }
24106 done_label:
24107 */
24108 static void
24111 machine_mode mode,
24121 {
24124 rtx modesize;
24126 rtx mode_value;
24128 /* Chose proper value to copy. */
24131 else
24135 /* See if block is big or small, handle small blocks. */
24137 {
24148 /* Handle sizes > 3. */
24155 /* Nothing to copy? Jump to DONE_LABEL if so */
24159 /* Do a byte copy. */
24163 else
24164 {
24167 }
24169 /* Handle sizes 2 and 3. */
24176 else
24177 {
24182 }
24188 }
24189 else
24193 /* Start memcpy for COUNT >= SIZE. */
24195 {
24198 }
24200 /* Copy first desired_align bytes. */
24206 {
24209 else
24210 {
24213 }
24216 }
24219 /* Copy last SIZE bytes. */
24226 else
24227 {
24233 }
24235 {
24239 else
24240 {
24243 }
24244 }
24246 /* Align destination. */
24248 {
24252 /* Align destptr up, place it to new register. */
24259 /* See how many bytes we skipped. */
24263 /* Adjust srcptr and count. */
24269 /* We copied at most size + prolog_size. */
24272 else
24275 /* Our loops always round down the bock size, but for dispatch to library
24276 we need precise value. */
24280 }
24281 else
24282 {
24284 /* Decrease count, so we won't end up copying last word twice. */
24288 else
24292 }
24293 }
24296 /* This function is like the previous one, except here we know how many bytes
24297 need to be copied. That allows us to update alignment not only of DST, which
24298 is returned, but also of SRC, which is passed as a pointer for that
24299 reason. */
24300 static rtx
24305 {
24313 {
24317 }
24322 {
24324 {
24326 {
24329 else
24331 }
24332 else
24335 }
24336 }
24343 {
24349 {
24352 {
24356 }
24361 }
24365 }
24368 }
24370 /* Return true if ALG can be used in current context.
24371 Assume we expand memset if MEMSET is true. */
24372 static bool
24374 {
24379 /* Algorithms using the rep prefix want at least edi and ecx;
24380 additionally, memset wants eax and memcpy wants esi. Don't
24381 consider such algorithms if the user has appropriated those
24382 registers for their own purposes. */
24389 }
24391 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
24392 static enum stringop_alg
24396 {
24407 /* Even if the string operation call is cold, we still might spend a lot
24408 of time processing large blocks. */
24414 else
24420 else
24423 /* See maximal size for user defined algorithm. */
24425 {
24432 }
24434 /* If expected size is not known but max size is small enough
24435 so inline version is a win, set expected size into
24436 the range. */
24441 /* If user specified the algorithm, honnor it if possible. */
24445 /* rep; movq or rep; movl is the smallest variant. */
24447 {
24452 else
24455 }
24456 /* Very tiny blocks are best handled via the loop, REP is expensive to
24457 setup. */
24461 {
24465 {
24466 /* We get here if the algorithms that were not libcall-based
24467 were rep-prefix based and we are unable to use rep prefixes
24468 based on global register usage. Break out of the loop and
24469 use the heuristic below. */
24473 {
24477 {
24480 }
24481 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
24482 last non-libcall inline algorithm. */
24484 {
24485 /* When the current size is best to be copied by a libcall,
24486 but we are still forced to inline, run the heuristic below
24487 that will pick code for medium sized blocks. */
24489 {
24492 }
24495 }
24497 {
24500 }
24501 }
24502 }
24503 }
24504 /* When asked to inline the call anyway, try to pick meaningful choice.
24505 We look for maximal size of block that is faster to copy by hand and
24506 take blocks of at most of that size guessing that average size will
24507 be roughly half of the block.
24509 If this turns out to be bad, we might simply specify the preferred
24510 choice in ix86_costs. */
24514 {
24517 /* If there aren't any usable algorithms, then recursing on
24518 smaller sizes isn't going to find anything. Just return the
24519 simple byte-at-a-time copy loop. */
24521 {
24522 /* Pick something reasonable. */
24526 }
24534 else
24537 }
24540 }
24542 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24543 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24544 static int
24548 machine_mode move_mode)
24549 {
24560 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24561 copying whole cacheline at once. */
24574 }
24577 /* Helper function for memcpy. For QImode value 0xXY produce
24578 0xXYXYXYXY of wide specified by MODE. This is essentially
24579 a * 0x10101010, but we can do slightly better than
24580 synth_mult by unwinding the sequence by hand on CPUs with
24581 slow multiply. */
24582 static rtx
24584 {
24586 rtx tmp;
24593 {
24601 }
24610 nops--;
24615 {
24619 OPTAB_DIRECT);
24620 }
24621 else
24622 {
24628 else
24630 else
24631 {
24634 reg =
24636 }
24646 }
24647 }
24649 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24650 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24651 alignment from ALIGN to DESIRED_ALIGN. */
24652 static rtx
24655 {
24656 rtx promoted_val;
24665 else
24669 }
24671 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24672 operations when profitable. The code depends upon architecture, block size
24673 and alignment, but always has one of the following overall structures:
24675 Aligned move sequence:
24677 1) Prologue guard: Conditional that jumps up to epilogues for small
24678 blocks that can be handled by epilogue alone. This is faster
24679 but also needed for correctness, since prologue assume the block
24680 is larger than the desired alignment.
24682 Optional dynamic check for size and libcall for large
24683 blocks is emitted here too, with -minline-stringops-dynamically.
24685 2) Prologue: copy first few bytes in order to get destination
24686 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24687 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24688 copied. We emit either a jump tree on power of two sized
24689 blocks, or a byte loop.
24691 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24692 with specified algorithm.
24694 4) Epilogue: code copying tail of the block that is too small to be
24695 handled by main body (or up to size guarded by prologue guard).
24697 Misaligned move sequence
24699 1) missaligned move prologue/epilogue containing:
24700 a) Prologue handling small memory blocks and jumping to done_label
24701 (skipped if blocks are known to be large enough)
24702 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24703 needed by single possibly misaligned move
24704 (skipped if alignment is not needed)
24705 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24707 2) Zero size guard dispatching to done_label, if needed
24709 3) dispatch to library call, if needed,
24711 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24712 with specified algorithm. */
24713 bool
24719 {
24720 rtx destreg;
24723 rtx tmp;
24739 /* TODO: Once value ranges are available, fill in proper data. */
24747 /* i386 can do misaligned access on reasonably increased cost. */
24751 /* ALIGN is the minimum of destination and source alignment, but we care here
24752 just about destination alignment. */
24758 {
24761 /* When COUNT is 0, there is nothing to do. */
24764 }
24765 else
24766 {
24775 }
24777 /* Make sure we don't need to care about overflow later on. */
24781 /* Step 0: Decide on preferred algorithm, desired alignment and
24782 size of chunks to be copied by main loop. */
24784 issetmem,
24791 /* For now vector-version of memset is generated only for memory zeroing, as
24792 creating of promoted vector value is very cheap in this case. */
24805 {
24824 /* Find the widest supported mode. */
24830 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24831 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24833 {
24838 }
24850 }
24858 /* Step 1: Prologue guard. */
24860 /* Alignment code needs count to be in register. */
24862 {
24865 {
24866 align_bytes
24870 else
24872 }
24875 }
24878 /* Misaligned move sequences handle both prologue and epilogue at once.
24879 Default code generation results in a smaller code for large alignments
24880 and also avoids redundant job when sizes are known precisely. */
24881 misaligned_prologue_used
24882 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
24888 /* Do the cheap promotion to allow better CSE across the
24889 main loop and epilogue (ie one load of the big constant in the
24890 front of all code.
24891 For now the misaligned move sequences do not have fast path
24892 without broadcasting. */
24894 {
24896 {
24902 }
24903 else
24904 {
24907 }
24908 }
24909 /* Misaligned move sequences handles both prologues and epilogues at once.
24910 Default code generation results in smaller code for large alignments and
24911 also avoids redundant job when sizes are known precisely. */
24913 {
24914 /* Misaligned move prologue handled small blocks by itself. */
24915 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
24920 desired_align < align
24929 {
24930 /* It is possible that we copied enough so the main loop will not
24931 execute. */
24941 else
24943 }
24944 }
24945 /* Ensure that alignment prologue won't copy past end of block. */
24947 {
24949 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
24950 Make sure it is power of 2. */
24953 /* To improve performance of small blocks, we jump around the VAL
24954 promoting mode. This mean that if the promoted VAL is not constant,
24955 we might not use it in the epilogue and have to use byte
24956 loop variant. */
24961 {
24962 /* If main algorithm works on QImode, no epilogue is needed.
24963 For small sizes just don't align anything. */
24966 else
24968 }
24971 {
24978 else
24980 }
24981 }
24983 /* Emit code to decide on runtime whether library call or inline should be
24984 used. */
24986 {
24988 {
24990 {
24994 }
24995 }
24996 else
24997 {
25007 else
25011 }
25012 }
25014 /* Step 2: Alignment prologue. */
25015 /* Do the expensive promotion once we branched off the small blocks. */
25021 {
25023 {
25024 /* Except for the first move in prologue, we no longer know
25025 constant offset in aliasing info. It don't seems to worth
25026 the pain to maintain it for the first move, so throw away
25027 the info early. */
25034 issetmem);
25035 /* At most desired_align - align bytes are copied. */
25038 else
25040 }
25041 else
25042 {
25043 /* If we know how many bytes need to be stored before dst is
25044 sufficiently aligned, maintain aliasing info accurately. */
25046 srcreg,
25047 promoted_val,
25048 vec_promoted_val,
25049 desired_align,
25050 align_bytes,
25051 issetmem);
25058 }
25060 && !min_size
25065 {
25066 /* It is possible that we copied enough so the main loop will not
25067 execute. */
25077 else
25079 }
25080 }
25082 {
25089 }
25093 /* Step 3: Main loop. */
25096 {
25119 }
25120 /* Adjust properly the offset of src and dest memory for aliasing. */
25122 {
25128 }
25129 else
25130 {
25134 }
25136 /* Step 4: Epilogue to copy the remaining bytes. */
25137 epilogue:
25139 {
25140 /* When the main loop is done, COUNT_EXP might hold original count,
25141 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
25142 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
25143 bytes. Compensate if needed. */
25146 {
25147 tmp =
25150 OPTAB_DIRECT);
25153 }
25156 }
25159 {
25162 epilogue_size_needed);
25163 else
25164 {
25168 epilogue_size_needed);
25169 else
25171 epilogue_size_needed);
25172 }
25173 }
25177 }
25180 /* Expand the appropriate insns for doing strlen if not just doing
25181 repnz; scasb
25183 out = result, initialized with the start address
25184 align_rtx = alignment of the address.
25185 scratch = scratch register, initialized with the startaddress when
25186 not aligned, otherwise undefined
25188 This is just the body. It needs the initializations mentioned above and
25189 some address computing at the end. These things are done in i386.md. */
25191 static void
25193 {
25195 rtx tmp;
25200 rtx mem;
25203 rtx cmp;
25209 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
25211 /* Is there a known alignment and is it less than 4? */
25213 {
25216 /* Is there a known alignment and is it not 2? */
25218 {
25222 /* Leave just the 3 lower bits. */
25232 }
25233 else
25234 {
25235 /* Since the alignment is 2, we have to check 2 or 0 bytes;
25236 check if is aligned to 4 - byte. */
25243 }
25247 /* Now compare the bytes. */
25249 /* Compare the first n unaligned byte on a byte per byte basis. */
25253 /* Increment the address. */
25256 /* Not needed with an alignment of 2 */
25258 {
25262 end_0_label);
25267 }
25270 end_0_label);
25273 }
25275 /* Generate loop to check 4 bytes at a time. It is not a good idea to
25276 align this loop. It gives only huge programs, but does not help to
25277 speed up. */
25284 /* This formula yields a nonzero result iff one of the bytes is zero.
25285 This saves three branches inside loop and many cycles. */
25293 align_4_label);
25296 {
25302 /* If zero is not in the first two bytes, move two bytes forward. */
25308 reg,
25309 tmpreg)));
25310 /* Emit lea manually to avoid clobbering of flags. */
25318 reg2,
25319 out)));
25320 }
25321 else
25322 {
25324 /* Is zero in the first two bytes? */
25331 pc_rtx);
25335 /* Not in the first two. Move two bytes forward. */
25341 }
25343 /* Avoid branch in fixing the byte. */
25351 }
25353 /* Expand strlen. */
25355 bool
25357 {
25360 /* The generic case of strlen expander is long. Avoid it's
25361 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
25364 && !TARGET_INLINE_ALL_STRINGOPS
25374 {
25375 /* Well it seems that some optimizer does not combine a call like
25376 foo(strlen(bar), strlen(bar));
25377 when the move and the subtraction is done here. It does calculate
25378 the length just once when these instructions are done inside of
25379 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
25380 often used and I use one fewer register for the lifetime of
25381 output_strlen_unroll() this is better. */
25387 /* strlensi_unroll_1 returns the address of the zero at the end of
25388 the string, like memchr(), so compute the length by subtracting
25389 the start address. */
25391 }
25392 else
25393 {
25394 rtx unspec;
25396 /* Can't use this if the user has appropriated eax, ecx, or edi. */
25409 /* If .md starts supporting :P, this can be done in .md. */
25415 }
25417 }
25419 /* For given symbol (function) construct code to compute address of it's PLT
25420 entry in large x86-64 PIC model. */
25421 static rtx
25423 {
25436 }
25438 rtx
25440 rtx callarg2,
25442 {
25452 {
25453 #if TARGET_MACHO
25456 #endif
25457 }
25458 else
25459 {
25460 /* Static functions and indirect calls don't need the pic register. */
25462 && (!TARGET_64BIT
25467 {
25471 pic_offset_table_rtx);
25472 }
25473 }
25475 /* Skip setting up RAX register for -mskip-rax-setup when there are no
25476 parameters passed in vector registers. */
25481 {
25485 }
25488 && !TARGET_PECOFF
25496 {
25499 }
25504 {
25505 /* We should add bounds as destination register in case
25506 pointer with bounds may be returned. */
25508 {
25513 }
25516 }
25520 {
25524 }
25528 {
25529 int const cregs_size
25534 {
25539 }
25540 }
25549 }
25551 /* Output the assembly for a call instruction. */
25555 {
25561 {
25564 /* SEH epilogue detection requires the indirect branch case
25565 to include REX.W. */
25568 else
25573 }
25575 /* SEH unwinding can require an extra nop to be emitted in several
25576 circumstances. Determine if we have one of those. */
25578 {
25582 {
25583 /* If we get to another real insn, we don't need the nop. */
25587 /* If we get to the epilogue note, prevent a catch region from
25588 being adjacent to the standard epilogue sequence. If non-
25589 call-exceptions, we'll have done this during epilogue emission. */
25591 && !flag_non_call_exceptions
25593 {
25596 }
25597 }
25599 /* If we didn't find a real insn following the call, prevent the
25600 unwinder from looking into the next function. */
25603 }
25607 else
25616 }
25617 \f
25618 /* Clear stack slot assignments remembered from previous functions.
25619 This is called from INIT_EXPANDERS once before RTL is emitted for each
25620 function. */
25624 {
25632 }
25634 /* Return a MEM corresponding to a stack slot with mode MODE.
25635 Allocate a new slot if necessary.
25637 The RTL for a function can have several slots available: N is
25638 which slot to use. */
25640 rtx
25642 {
25659 }
25661 static void
25663 {
25669 }
25670 \f
25671 /* Check whether x86 address PARTS is a pc-relative address. */
25673 static bool
25675 {
25683 {
25685 {
25702 }
25703 }
25705 }
25707 /* Calculate the length of the memory address in the instruction encoding.
25708 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25709 or other prefixes. We never generate addr32 prefix for LEA insn. */
25711 int
25713 {
25730 /* If this is not LEA instruction, add the length of addr32 prefix. */
25735 len++;
25749 /* Rule of thumb:
25750 - esp as the base always wants an index,
25751 - ebp as the base always wants a displacement,
25752 - r12 as the base always wants an index,
25753 - r13 as the base always wants a displacement. */
25755 /* Register Indirect. */
25757 {
25758 /* esp (for its index) and ebp (for its displacement) need
25759 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25760 code. */
25767 len++;
25768 }
25770 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25771 is not disp32, but disp32(%rip), so for disp32
25772 SIB byte is needed, unless print_operand_address
25773 optimizes it into disp32(%rip) or (%rip) is implied
25774 by UNSPEC. */
25776 {
25779 len++;
25780 }
25781 else
25782 {
25783 /* Find the length of the displacement constant. */
25785 {
25788 else
25790 }
25791 /* ebp always wants a displacement. Similarly r13. */
25793 len++;
25795 /* An index requires the two-byte modrm form.... */
25797 /* ...like esp (or r12), which always wants an index. */
25801 len++;
25802 }
25805 }
25807 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25808 is set, expect that insn have 8bit immediate alternative. */
25809 int
25811 {
25817 {
25822 {
25825 {
25837 }
25839 {
25842 }
25843 }
25845 {
25855 /* Immediates for DImode instructions are encoded
25856 as 32bit sign extended values. */
25862 }
25863 }
25865 }
25867 /* Compute default value for "length_address" attribute. */
25868 int
25870 {
25874 {
25885 }
25890 {
25893 {
25898 constraints++;
25901 ;
25902 /* Skip ignored operands. */
25905 }
25907 }
25909 }
25911 /* Compute default value for "length_vex" attribute. It includes
25912 2 or 3 byte VEX prefix and 1 opcode byte. */
25914 int
25917 {
25920 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
25921 byte VEX prefix. */
25925 /* We can always use 2 byte VEX prefix in 32bit. */
25933 {
25934 /* REX.W bit uses 3 byte VEX prefix. */
25938 }
25939 else
25940 {
25941 /* REX.X or REX.B bits use 3 byte VEX prefix. */
25945 }
25948 }
25949 \f
25950 /* Return the maximum number of instructions a cpu can issue. */
25952 static int
25954 {
25956 {
25988 }
25989 }
25991 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
25992 by DEP_INSN and nothing set by DEP_INSN. */
25994 static bool
25996 {
25999 /* Simplify the test for uninteresting insns. */
26007 {
26010 }
26015 {
26018 }
26019 else
26025 /* This test is true if the dependent insn reads the flags but
26026 not any other potentially set register. */
26034 }
26036 /* Return true iff USE_INSN has a memory address with operands set by
26037 SET_INSN. */
26039 bool
26041 {
26046 {
26049 }
26051 }
26053 /* Helper function for exact_store_load_dependency.
26054 Return true if addr is found in insn. */
26055 static bool
26057 {
26064 {
26070 CASE_CONST_ANY:
26079 }
26083 {
26085 {
26095 }
26096 }
26098 }
26100 /* Return true if there exists exact dependency for store & load, i.e.
26101 the same memory address is used in them. */
26102 static bool
26104 {
26118 }
26120 static int
26122 {
26128 /* Anti and output dependencies have zero cost on all CPUs. */
26134 /* If we can't recognize the insns, we can't really do anything. */
26142 {
26144 /* Address Generation Interlock adds a cycle of latency. */
26146 {
26157 }
26161 /* ??? Compares pair with jump/setcc. */
26165 /* Floating point stores require value to be ready one cycle earlier. */
26173 /* INT->FP conversion is expensive. */
26177 /* There is one cycle extra latency between an FP op and a store. */
26187 /* Show ability of reorder buffer to hide latency of load by executing
26188 in parallel with previous instruction in case
26189 previous instruction is not needed to compute the address. */
26192 {
26193 /* Claim moves to take one cycle, as core can issue one load
26194 at time and the next load can start cycle later. */
26199 cost--;
26200 }
26204 /* The esp dependency is resolved before
26205 the instruction is really finished. */
26210 /* INT->FP conversion is expensive. */
26216 /* Show ability of reorder buffer to hide latency of load by executing
26217 in parallel with previous instruction in case
26218 previous instruction is not needed to compute the address. */
26221 {
26222 /* Claim moves to take one cycle, as core can issue one load
26223 at time and the next load can start cycle later. */
26229 else
26231 }
26242 /* Stack engine allows to execute push&pop instructions in parall. */
26246 /* FALLTHRU */
26252 /* Show ability of reorder buffer to hide latency of load by executing
26253 in parallel with previous instruction in case
26254 previous instruction is not needed to compute the address. */
26257 {
26261 /* Because of the difference between the length of integer and
26262 floating unit pipeline preparation stages, the memory operands
26263 for floating point are cheaper.
26265 ??? For Athlon it the difference is most probably 2. */
26268 else
26273 else
26275 }
26282 /* Stack engine allows to execute push&pop instructions in parall. */
26289 /* Show ability of reorder buffer to hide latency of load by executing
26290 in parallel with previous instruction in case
26291 previous instruction is not needed to compute the address. */
26294 {
26297 else
26299 }
26308 /* Increase cost of integer loads. */
26311 {
26314 {
26317 else
26318 {
26319 /* Increase cost of ld/st for short int types only
26320 because of store forwarding issue. */
26324 {
26325 /* Increase cost of store/load insn if exact
26326 dependence exists and it is load insn. */
26331 }
26332 }
26333 }
26334 }
26338 }
26341 }
26343 /* How many alternative schedules to try. This should be as wide as the
26344 scheduling freedom in the DFA, but no wider. Making this value too
26345 large results extra work for the scheduler. */
26347 static int
26349 {
26351 {
26363 /* We use lookahead value 4 for BD both before and after reload
26364 schedules. Plan is to have value 8 included for O3. */
26375 /* Generally, we want haifa-sched:max_issue() to look ahead as far
26376 as many instructions can be executed on a cycle, i.e.,
26377 issue_rate. I wonder why tuning for many CPUs does not do this. */
26380 /* Don't use lookahead for pre-reload schedule to save compile time. */
26385 }
26386 }
26388 /* Return true if target platform supports macro-fusion. */
26390 static bool
26392 {
26394 }
26396 /* Check whether current microarchitecture support macro fusion
26397 for insn pair "CONDGEN + CONDJMP". Refer to
26398 "Intel Architectures Optimization Reference Manual". */
26400 static bool
26402 {
26423 {
26428 {
26432 else
26434 }
26435 }
26442 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
26443 supported. */
26450 /* No fusion for RIP-relative address. */
26457 ix86_address parts;
26463 }
26468 /* Check whether conditional jump use Sign or Overflow Flags. */
26476 /* Return true for TYPE_TEST and TYPE_ICMP. */
26481 /* The following is the case that macro-fusion for alu + jmp. */
26485 /* No fusion for alu op with memory destination operand. */
26490 /* Macro-fusion for inc/dec + unsigned conditional jump is not
26491 supported. */
26500 }
26502 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
26503 execution. It is applied if
26504 (1) IMUL instruction is on the top of list;
26505 (2) There exists the only producer of independent IMUL instruction in
26506 ready list.
26507 Return index of IMUL producer if it was found and -1 otherwise. */
26508 static int
26510 {
26513 sd_iterator_def sd_it;
26514 dep_t dep;
26521 /* Check that IMUL instruction is on the top of ready list. */
26530 /* Search for producer of independent IMUL instruction. */
26532 {
26536 /* Skip IMUL instruction. */
26546 {
26547 rtx con;
26558 {
26559 sd_iterator_def sd_it1;
26560 dep_t dep1;
26561 /* Check if there is no other dependee for IMUL. */
26564 {
26565 rtx pro;
26571 }
26574 }
26575 }
26578 }
26580 }
26582 /* Try to find the best candidate on the top of ready list if two insns
26583 have the same priority - candidate is best if its dependees were
26584 scheduled earlier. Applied for Silvermont only.
26585 Return true if top 2 insns must be interchanged. */
26586 static bool
26588 {
26591 rtx set;
26592 sd_iterator_def sd_it;
26593 dep_t dep;
26596 #define INSN_TICK(INSN) (HID (INSN)->tick)
26617 {
26620 /* Determine winner more precise. */
26622 {
26623 rtx pro;
26629 }
26631 {
26632 rtx pro;
26638 }
26641 {
26642 /* Determine winner - load must win. */
26648 }
26650 }
26652 #undef INSN_TICK
26653 }
26655 /* Perform possible reodering of ready list for Atom/Silvermont only.
26656 Return issue rate. */
26657 static int
26660 {
26667 /* Set up issue rate. */
26670 /* Do reodering for BONNELL/SILVERMONT only. */
26674 /* Nothing to do if ready list contains only 1 instruction. */
26678 /* Do reodering for post-reload scheduler only. */
26683 {
26688 /* Put IMUL producer (ready[index]) at the top of ready list. */
26694 }
26696 {
26700 /* Swap 2 top elements of ready list. */
26704 }
26706 }
26708 static bool
26711 /* Returns true if lhs of insn is HW function argument register and set up
26712 is_spilled to true if it is likely spilled HW register. */
26713 static bool
26715 {
26716 rtx dst;
26720 /* Call instructions are not movable, ignore it. */
26731 {
26732 /* Is it likely spilled HW register? */
26737 }
26739 }
26741 /* Add output dependencies for chain of function adjacent arguments if only
26742 there is a move to likely spilled HW register. Return first argument
26743 if at least one dependence was added or NULL otherwise. */
26746 {
26754 /* Find nearest to call argument passing instruction. */
26756 {
26765 }
26769 {
26776 {
26779 }
26781 {
26782 /* Add output depdendence between two function arguments if chain
26783 of output arguments contains likely spilled HW registers. */
26787 }
26788 else
26790 }
26794 }
26796 /* Add output or anti dependency from insn to first_arg to restrict its code
26797 motion. */
26798 static void
26800 {
26801 rtx set;
26802 rtx tmp;
26809 {
26810 /* Add output dependency to the first function argument. */
26813 }
26814 /* Add anti dependency. */
26816 }
26818 /* Avoid cross block motion of function argument through adding dependency
26819 from the first non-jump instruction in bb. */
26820 static void
26822 {
26826 {
26828 {
26831 {
26834 }
26835 }
26839 }
26840 }
26842 /* Hook for pre-reload schedule - avoid motion of function arguments
26843 passed in likely spilled HW registers. */
26844 static void
26846 {
26855 {
26858 {
26859 /* Add dependee for first argument to predecessors if only
26860 region contains more than one block. */
26864 /* Skip trivial regions and region head blocks that can have
26865 predecessors outside of region. */
26867 {
26868 edge e;
26869 edge_iterator ei;
26871 /* Regions are SCCs with the exception of selective
26872 scheduling with pipelining of outer blocks enabled.
26873 So also check that immediate predecessors of a non-head
26874 block are in the same region. */
26876 {
26877 /* Avoid creating of loop-carried dependencies through
26878 using topological ordering in the region. */
26882 }
26883 }
26887 }
26888 }
26891 }
26893 /* Hook for pre-reload schedule - set priority of moves from likely spilled
26894 HW registers to maximum, to schedule them at soon as possible. These are
26895 moves from function argument registers at the top of the function entry
26896 and moves from function return value registers after call. */
26897 static int
26899 {
26900 rtx set;
26910 {
26917 }
26920 }
26922 /* Model decoder of Core 2/i7.
26923 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
26924 track the instruction fetch block boundaries and make sure that long
26925 (9+ bytes) instructions are assigned to D0. */
26927 /* Maximum length of an insn that can be handled by
26928 a secondary decoder unit. '8' for Core 2/i7. */
26931 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
26932 '16' for Core 2/i7. */
26935 /* Maximum number of instructions decoder can handle per cycle.
26936 '6' for Core 2/i7. */
26940 ix86_first_cycle_multipass_data_t;
26942 const_ix86_first_cycle_multipass_data_t;
26944 /* A variable to store target state across calls to max_issue within
26945 one cycle. */
26949 /* Initialize DATA. */
26950 static void
26952 {
26953 ix86_first_cycle_multipass_data_t data
26960 }
26962 /* Advancing the cycle; reset ifetch block counts. */
26963 static void
26965 {
26972 }
26976 /* Filter out insns from ready_try that the core will not be able to issue
26977 on current cycle due to decoder. */
26978 static void
26979 core2i7_first_cycle_multipass_filter_ready_try
26982 {
26984 {
26995 (!first_cycle_insn_p
26997 /* ... or it would not fit into the ifetch block ... */
26999 /* ... or the decoder is full already ... */
27001 /* ... mask the insn out. */
27002 {
27007 }
27008 }
27009 }
27011 /* Prepare for a new round of multipass lookahead scheduling. */
27012 static void
27016 {
27017 ix86_first_cycle_multipass_data_t data
27019 const_ix86_first_cycle_multipass_data_t prev_data
27022 /* Restore the state from the end of the previous round. */
27026 /* Filter instructions that cannot be issued on current cycle due to
27027 decoder restrictions. */
27029 first_cycle_insn_p);
27030 }
27032 /* INSN is being issued in current solution. Account for its impact on
27033 the decoder model. */
27034 static void
27038 {
27039 ix86_first_cycle_multipass_data_t data
27041 const_ix86_first_cycle_multipass_data_t prev_data
27051 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
27053 {
27056 }
27058 {
27062 }
27065 /* Filter out insns from ready_try that the core will not be able to issue
27066 on current cycle due to decoder. */
27069 }
27071 /* Revert the effect on ready_try. */
27072 static void
27076 {
27077 const_ix86_first_cycle_multipass_data_t data
27080 sbitmap_iterator sbi;
27084 {
27086 }
27087 }
27089 /* Save the result of multipass lookahead scheduling for the next round. */
27090 static void
27092 {
27093 const_ix86_first_cycle_multipass_data_t data
27095 ix86_first_cycle_multipass_data_t next_data
27099 {
27102 }
27103 }
27105 /* Deallocate target data. */
27106 static void
27108 {
27109 ix86_first_cycle_multipass_data_t data
27113 {
27117 }
27118 }
27120 /* Prepare for scheduling pass. */
27121 static void
27123 {
27124 /* Install scheduling hooks for current CPU. Some of these hooks are used
27125 in time-critical parts of the scheduler, so we only set them up when
27126 they are actually used. */
27128 {
27133 /* Do not perform multipass scheduling for pre-reload schedule
27134 to save compile time. */
27136 {
27152 /* Set decoder parameters. */
27157 }
27158 /* ... Fall through ... */
27168 }
27169 }
27171 \f
27172 /* Compute the alignment given to a constant that is being placed in memory.
27173 EXP is the constant and ALIGN is the alignment that the object would
27174 ordinarily have.
27175 The value of this function is used instead of that alignment to align
27176 the object. */
27178 int
27180 {
27183 {
27188 }
27194 }
27196 /* Compute the alignment for a static variable.
27197 TYPE is the data type, and ALIGN is the alignment that
27198 the object would ordinarily have. The value of this function is used
27199 instead of that alignment to align the object. */
27201 int
27203 {
27204 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
27205 for symbols from other compilation units or symbols that don't need
27206 to bind locally. In order to preserve some ABI compatibility with
27207 those compilers, ensure we don't decrease alignment from what we
27208 used to assume. */
27212 /* A data structure, equal or greater than the size of a cache line
27213 (64 bytes in the Pentium 4 and other recent Intel processors, including
27214 processors based on Intel Core microarchitecture) should be aligned
27215 so that its base address is a multiple of a cache line size. */
27217 int max_align
27224 {
27228 }
27234 {
27241 }
27243 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27244 to 16byte boundary. */
27246 {
27253 }
27259 {
27264 }
27266 {
27273 }
27278 {
27283 }
27286 {
27291 }
27294 }
27296 /* Compute the alignment for a local variable or a stack slot. EXP is
27297 the data type or decl itself, MODE is the widest mode available and
27298 ALIGN is the alignment that the object would ordinarily have. The
27299 value of this macro is used instead of that alignment to align the
27300 object. */
27302 unsigned int
27305 {
27309 {
27312 }
27313 else
27314 {
27317 }
27319 /* Don't do dynamic stack realignment for long long objects with
27320 -mpreferred-stack-boundary=2. */
27329 /* If TYPE is NULL, we are allocating a stack slot for caller-save
27330 register in MODE. We will return the largest alignment of XF
27331 and DF. */
27333 {
27337 }
27339 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27340 to 16byte boundary. Exact wording is:
27342 An array uses the same alignment as its elements, except that a local or
27343 global array variable of length at least 16 bytes or
27344 a C99 variable-length array variable always has alignment of at least 16 bytes.
27346 This was added to allow use of aligned SSE instructions at arrays. This
27347 rule is meant for static storage (where compiler can not do the analysis
27348 by itself). We follow it for automatic variables only when convenient.
27349 We fully control everything in the function compiled and functions from
27350 other unit can not rely on the alignment.
27352 Exclude va_list type. It is the common case of local array where
27353 we can not benefit from the alignment.
27355 TODO: Probably one should optimize for size only when var is not escaping. */
27358 {
27368 }
27370 {
27375 }
27377 {
27383 }
27388 {
27393 }
27396 {
27402 }
27404 }
27406 /* Compute the minimum required alignment for dynamic stack realignment
27407 purposes for a local variable, parameter or a stack slot. EXP is
27408 the data type or decl itself, MODE is its mode and ALIGN is the
27409 alignment that the object would ordinarily have. */
27411 unsigned int
27414 {
27418 {
27421 }
27422 else
27423 {
27426 }
27431 /* Don't do dynamic stack realignment for long long objects with
27432 -mpreferred-stack-boundary=2. */
27439 }
27440 \f
27441 /* Find a location for the static chain incoming to a nested function.
27442 This is a register, unless all free registers are used by arguments. */
27444 static rtx
27446 {
27449 /* While this function won't be called by the middle-end when a static
27450 chain isn't needed, it's also used throughout the backend so it's
27451 easiest to keep this check centralized. */
27456 {
27457 /* We always use R10 in 64-bit mode. */
27459 }
27460 else
27461 {
27465 /* By default in 32-bit mode we use ECX to pass the static chain. */
27469 {
27472 }
27473 else
27474 {
27477 }
27481 {
27482 /* Fastcall functions use ecx/edx for arguments, which leaves
27483 us with EAX for the static chain.
27484 Thiscall functions use ecx for arguments, which also
27485 leaves us with EAX for the static chain. */
27487 }
27489 {
27490 /* Thiscall functions use ecx for arguments, which leaves
27491 us with EAX and EDX for the static chain.
27492 We are using for abi-compatibility EAX. */
27494 }
27496 {
27497 /* For regparm 3, we have no free call-clobbered registers in
27498 which to store the static chain. In order to implement this,
27499 we have the trampoline push the static chain to the stack.
27500 However, we can't push a value below the return address when
27501 we call the nested function directly, so we have to use an
27502 alternate entry point. For this we use ESI, and have the
27503 alternate entry point push ESI, so that things appear the
27504 same once we're executing the nested function. */
27506 {
27512 }
27514 }
27515 }
27518 }
27520 /* Emit RTL insns to initialize the variable parts of a trampoline.
27521 FNDECL is the decl of the target address; M_TRAMP is a MEM for
27522 the trampoline, and CHAIN_VALUE is an RTX for the static chain
27523 to be passed to the target function. */
27525 static void
27527 {
27535 {
27538 /* Load the function address to r11. Try to load address using
27539 the shorter movl instead of movabs. We may want to support
27540 movq for kernel mode, but kernel does not use trampolines at
27541 the moment. FNADDR is a 32bit address and may not be in
27542 DImode when ptr_mode == SImode. Always use movl in this
27543 case. */
27546 {
27555 }
27556 else
27557 {
27564 }
27566 /* Load static chain using movabs to r10. Use the shorter movl
27567 instead of movabs when ptr_mode == SImode. */
27569 {
27572 }
27573 else
27574 {
27577 }
27586 /* Jump to r11; the last (unused) byte is a nop, only there to
27587 pad the write out to a single 32-bit store. */
27591 }
27592 else
27593 {
27596 /* Depending on the static chain location, either load a register
27597 with a constant, or push the constant to the stack. All of the
27598 instructions are the same size. */
27601 {
27603 {
27610 }
27611 }
27612 else
27627 /* Compute offset from the end of the jmp to the target function.
27628 In the case in which the trampoline stores the static chain on
27629 the stack, we need to skip the first insn which pushes the
27630 (call-saved) register static chain; this push is 1 byte. */
27637 }
27641 #ifdef HAVE_ENABLE_EXECUTE_STACK
27642 #ifdef CHECK_EXECUTE_STACK_ENABLED
27644 #endif
27647 #endif
27648 }
27649 \f
27650 /* The following file contains several enumerations and data structures
27651 built from the definitions in i386-builtin-types.def. */
27655 /* Table for the ix86 builtin non-function types. */
27658 /* Retrieve an element from the above table, building some of
27659 the types lazily. */
27661 static tree
27663 {
27675 {
27676 machine_mode mode;
27683 }
27684 else
27685 {
27691 else
27699 }
27703 }
27705 /* Table for the ix86 builtin function types. */
27708 /* Retrieve an element from the above table, building some of
27709 the types lazily. */
27711 static tree
27713 {
27714 tree type;
27723 {
27731 {
27734 }
27737 }
27738 else
27739 {
27745 }
27749 }
27752 /* Codes for all the SSE/MMX builtins. */
27753 enum ix86_builtins
27754 {
27755 IX86_BUILTIN_ADDPS,
27756 IX86_BUILTIN_ADDSS,
27757 IX86_BUILTIN_DIVPS,
27758 IX86_BUILTIN_DIVSS,
27759 IX86_BUILTIN_MULPS,
27760 IX86_BUILTIN_MULSS,
27761 IX86_BUILTIN_SUBPS,
27762 IX86_BUILTIN_SUBSS,
27764 IX86_BUILTIN_CMPEQPS,
27765 IX86_BUILTIN_CMPLTPS,
27766 IX86_BUILTIN_CMPLEPS,
27767 IX86_BUILTIN_CMPGTPS,
27768 IX86_BUILTIN_CMPGEPS,
27769 IX86_BUILTIN_CMPNEQPS,
27770 IX86_BUILTIN_CMPNLTPS,
27771 IX86_BUILTIN_CMPNLEPS,
27772 IX86_BUILTIN_CMPNGTPS,
27773 IX86_BUILTIN_CMPNGEPS,
27774 IX86_BUILTIN_CMPORDPS,
27775 IX86_BUILTIN_CMPUNORDPS,
27776 IX86_BUILTIN_CMPEQSS,
27777 IX86_BUILTIN_CMPLTSS,
27778 IX86_BUILTIN_CMPLESS,
27779 IX86_BUILTIN_CMPNEQSS,
27780 IX86_BUILTIN_CMPNLTSS,
27781 IX86_BUILTIN_CMPNLESS,
27782 IX86_BUILTIN_CMPORDSS,
27783 IX86_BUILTIN_CMPUNORDSS,
27785 IX86_BUILTIN_COMIEQSS,
27786 IX86_BUILTIN_COMILTSS,
27787 IX86_BUILTIN_COMILESS,
27788 IX86_BUILTIN_COMIGTSS,
27789 IX86_BUILTIN_COMIGESS,
27790 IX86_BUILTIN_COMINEQSS,
27791 IX86_BUILTIN_UCOMIEQSS,
27792 IX86_BUILTIN_UCOMILTSS,
27793 IX86_BUILTIN_UCOMILESS,
27794 IX86_BUILTIN_UCOMIGTSS,
27795 IX86_BUILTIN_UCOMIGESS,
27796 IX86_BUILTIN_UCOMINEQSS,
27798 IX86_BUILTIN_CVTPI2PS,
27799 IX86_BUILTIN_CVTPS2PI,
27800 IX86_BUILTIN_CVTSI2SS,
27801 IX86_BUILTIN_CVTSI642SS,
27802 IX86_BUILTIN_CVTSS2SI,
27803 IX86_BUILTIN_CVTSS2SI64,
27804 IX86_BUILTIN_CVTTPS2PI,
27805 IX86_BUILTIN_CVTTSS2SI,
27806 IX86_BUILTIN_CVTTSS2SI64,
27808 IX86_BUILTIN_MAXPS,
27809 IX86_BUILTIN_MAXSS,
27810 IX86_BUILTIN_MINPS,
27811 IX86_BUILTIN_MINSS,
27813 IX86_BUILTIN_LOADUPS,
27814 IX86_BUILTIN_STOREUPS,
27815 IX86_BUILTIN_MOVSS,
27817 IX86_BUILTIN_MOVHLPS,
27818 IX86_BUILTIN_MOVLHPS,
27819 IX86_BUILTIN_LOADHPS,
27820 IX86_BUILTIN_LOADLPS,
27821 IX86_BUILTIN_STOREHPS,
27822 IX86_BUILTIN_STORELPS,
27824 IX86_BUILTIN_MASKMOVQ,
27825 IX86_BUILTIN_MOVMSKPS,
27826 IX86_BUILTIN_PMOVMSKB,
27828 IX86_BUILTIN_MOVNTPS,
27829 IX86_BUILTIN_MOVNTQ,
27831 IX86_BUILTIN_LOADDQU,
27832 IX86_BUILTIN_STOREDQU,
27834 IX86_BUILTIN_PACKSSWB,
27835 IX86_BUILTIN_PACKSSDW,
27836 IX86_BUILTIN_PACKUSWB,
27838 IX86_BUILTIN_PADDB,
27839 IX86_BUILTIN_PADDW,
27840 IX86_BUILTIN_PADDD,
27841 IX86_BUILTIN_PADDQ,
27842 IX86_BUILTIN_PADDSB,
27843 IX86_BUILTIN_PADDSW,
27844 IX86_BUILTIN_PADDUSB,
27845 IX86_BUILTIN_PADDUSW,
27846 IX86_BUILTIN_PSUBB,
27847 IX86_BUILTIN_PSUBW,
27848 IX86_BUILTIN_PSUBD,
27849 IX86_BUILTIN_PSUBQ,
27850 IX86_BUILTIN_PSUBSB,
27851 IX86_BUILTIN_PSUBSW,
27852 IX86_BUILTIN_PSUBUSB,
27853 IX86_BUILTIN_PSUBUSW,
27855 IX86_BUILTIN_PAND,
27856 IX86_BUILTIN_PANDN,
27857 IX86_BUILTIN_POR,
27858 IX86_BUILTIN_PXOR,
27860 IX86_BUILTIN_PAVGB,
27861 IX86_BUILTIN_PAVGW,
27863 IX86_BUILTIN_PCMPEQB,
27864 IX86_BUILTIN_PCMPEQW,
27865 IX86_BUILTIN_PCMPEQD,
27866 IX86_BUILTIN_PCMPGTB,
27867 IX86_BUILTIN_PCMPGTW,
27868 IX86_BUILTIN_PCMPGTD,
27870 IX86_BUILTIN_PMADDWD,
27872 IX86_BUILTIN_PMAXSW,
27873 IX86_BUILTIN_PMAXUB,
27874 IX86_BUILTIN_PMINSW,
27875 IX86_BUILTIN_PMINUB,
27877 IX86_BUILTIN_PMULHUW,
27878 IX86_BUILTIN_PMULHW,
27879 IX86_BUILTIN_PMULLW,
27881 IX86_BUILTIN_PSADBW,
27882 IX86_BUILTIN_PSHUFW,
27884 IX86_BUILTIN_PSLLW,
27885 IX86_BUILTIN_PSLLD,
27886 IX86_BUILTIN_PSLLQ,
27887 IX86_BUILTIN_PSRAW,
27888 IX86_BUILTIN_PSRAD,
27889 IX86_BUILTIN_PSRLW,
27890 IX86_BUILTIN_PSRLD,
27891 IX86_BUILTIN_PSRLQ,
27892 IX86_BUILTIN_PSLLWI,
27893 IX86_BUILTIN_PSLLDI,
27894 IX86_BUILTIN_PSLLQI,
27895 IX86_BUILTIN_PSRAWI,
27896 IX86_BUILTIN_PSRADI,
27897 IX86_BUILTIN_PSRLWI,
27898 IX86_BUILTIN_PSRLDI,
27899 IX86_BUILTIN_PSRLQI,
27901 IX86_BUILTIN_PUNPCKHBW,
27902 IX86_BUILTIN_PUNPCKHWD,
27903 IX86_BUILTIN_PUNPCKHDQ,
27904 IX86_BUILTIN_PUNPCKLBW,
27905 IX86_BUILTIN_PUNPCKLWD,
27906 IX86_BUILTIN_PUNPCKLDQ,
27908 IX86_BUILTIN_SHUFPS,
27910 IX86_BUILTIN_RCPPS,
27911 IX86_BUILTIN_RCPSS,
27912 IX86_BUILTIN_RSQRTPS,
27913 IX86_BUILTIN_RSQRTPS_NR,
27914 IX86_BUILTIN_RSQRTSS,
27915 IX86_BUILTIN_RSQRTF,
27916 IX86_BUILTIN_SQRTPS,
27917 IX86_BUILTIN_SQRTPS_NR,
27918 IX86_BUILTIN_SQRTSS,
27920 IX86_BUILTIN_UNPCKHPS,
27921 IX86_BUILTIN_UNPCKLPS,
27923 IX86_BUILTIN_ANDPS,
27924 IX86_BUILTIN_ANDNPS,
27925 IX86_BUILTIN_ORPS,
27926 IX86_BUILTIN_XORPS,
27928 IX86_BUILTIN_EMMS,
27929 IX86_BUILTIN_LDMXCSR,
27930 IX86_BUILTIN_STMXCSR,
27931 IX86_BUILTIN_SFENCE,
27933 IX86_BUILTIN_FXSAVE,
27934 IX86_BUILTIN_FXRSTOR,
27935 IX86_BUILTIN_FXSAVE64,
27936 IX86_BUILTIN_FXRSTOR64,
27938 IX86_BUILTIN_XSAVE,
27939 IX86_BUILTIN_XRSTOR,
27940 IX86_BUILTIN_XSAVE64,
27941 IX86_BUILTIN_XRSTOR64,
27943 IX86_BUILTIN_XSAVEOPT,
27944 IX86_BUILTIN_XSAVEOPT64,
27946 IX86_BUILTIN_XSAVEC,
27947 IX86_BUILTIN_XSAVEC64,
27949 IX86_BUILTIN_XSAVES,
27950 IX86_BUILTIN_XRSTORS,
27951 IX86_BUILTIN_XSAVES64,
27952 IX86_BUILTIN_XRSTORS64,
27954 /* 3DNow! Original */
27955 IX86_BUILTIN_FEMMS,
27956 IX86_BUILTIN_PAVGUSB,
27957 IX86_BUILTIN_PF2ID,
27958 IX86_BUILTIN_PFACC,
27959 IX86_BUILTIN_PFADD,
27960 IX86_BUILTIN_PFCMPEQ,
27961 IX86_BUILTIN_PFCMPGE,
27962 IX86_BUILTIN_PFCMPGT,
27963 IX86_BUILTIN_PFMAX,
27964 IX86_BUILTIN_PFMIN,
27965 IX86_BUILTIN_PFMUL,
27966 IX86_BUILTIN_PFRCP,
27967 IX86_BUILTIN_PFRCPIT1,
27968 IX86_BUILTIN_PFRCPIT2,
27969 IX86_BUILTIN_PFRSQIT1,
27970 IX86_BUILTIN_PFRSQRT,
27971 IX86_BUILTIN_PFSUB,
27972 IX86_BUILTIN_PFSUBR,
27973 IX86_BUILTIN_PI2FD,
27974 IX86_BUILTIN_PMULHRW,
27976 /* 3DNow! Athlon Extensions */
27977 IX86_BUILTIN_PF2IW,
27978 IX86_BUILTIN_PFNACC,
27979 IX86_BUILTIN_PFPNACC,
27980 IX86_BUILTIN_PI2FW,
27981 IX86_BUILTIN_PSWAPDSI,
27982 IX86_BUILTIN_PSWAPDSF,
27984 /* SSE2 */
27985 IX86_BUILTIN_ADDPD,
27986 IX86_BUILTIN_ADDSD,
27987 IX86_BUILTIN_DIVPD,
27988 IX86_BUILTIN_DIVSD,
27989 IX86_BUILTIN_MULPD,
27990 IX86_BUILTIN_MULSD,
27991 IX86_BUILTIN_SUBPD,
27992 IX86_BUILTIN_SUBSD,
27994 IX86_BUILTIN_CMPEQPD,
27995 IX86_BUILTIN_CMPLTPD,
27996 IX86_BUILTIN_CMPLEPD,
27997 IX86_BUILTIN_CMPGTPD,
27998 IX86_BUILTIN_CMPGEPD,
27999 IX86_BUILTIN_CMPNEQPD,
28000 IX86_BUILTIN_CMPNLTPD,
28001 IX86_BUILTIN_CMPNLEPD,
28002 IX86_BUILTIN_CMPNGTPD,
28003 IX86_BUILTIN_CMPNGEPD,
28004 IX86_BUILTIN_CMPORDPD,
28005 IX86_BUILTIN_CMPUNORDPD,
28006 IX86_BUILTIN_CMPEQSD,
28007 IX86_BUILTIN_CMPLTSD,
28008 IX86_BUILTIN_CMPLESD,
28009 IX86_BUILTIN_CMPNEQSD,
28010 IX86_BUILTIN_CMPNLTSD,
28011 IX86_BUILTIN_CMPNLESD,
28012 IX86_BUILTIN_CMPORDSD,
28013 IX86_BUILTIN_CMPUNORDSD,
28015 IX86_BUILTIN_COMIEQSD,
28016 IX86_BUILTIN_COMILTSD,
28017 IX86_BUILTIN_COMILESD,
28018 IX86_BUILTIN_COMIGTSD,
28019 IX86_BUILTIN_COMIGESD,
28020 IX86_BUILTIN_COMINEQSD,
28021 IX86_BUILTIN_UCOMIEQSD,
28022 IX86_BUILTIN_UCOMILTSD,
28023 IX86_BUILTIN_UCOMILESD,
28024 IX86_BUILTIN_UCOMIGTSD,
28025 IX86_BUILTIN_UCOMIGESD,
28026 IX86_BUILTIN_UCOMINEQSD,
28028 IX86_BUILTIN_MAXPD,
28029 IX86_BUILTIN_MAXSD,
28030 IX86_BUILTIN_MINPD,
28031 IX86_BUILTIN_MINSD,
28033 IX86_BUILTIN_ANDPD,
28034 IX86_BUILTIN_ANDNPD,
28035 IX86_BUILTIN_ORPD,
28036 IX86_BUILTIN_XORPD,
28038 IX86_BUILTIN_SQRTPD,
28039 IX86_BUILTIN_SQRTSD,
28041 IX86_BUILTIN_UNPCKHPD,
28042 IX86_BUILTIN_UNPCKLPD,
28044 IX86_BUILTIN_SHUFPD,
28046 IX86_BUILTIN_LOADUPD,
28047 IX86_BUILTIN_STOREUPD,
28048 IX86_BUILTIN_MOVSD,
28050 IX86_BUILTIN_LOADHPD,
28051 IX86_BUILTIN_LOADLPD,
28053 IX86_BUILTIN_CVTDQ2PD,
28054 IX86_BUILTIN_CVTDQ2PS,
28056 IX86_BUILTIN_CVTPD2DQ,
28057 IX86_BUILTIN_CVTPD2PI,
28058 IX86_BUILTIN_CVTPD2PS,
28059 IX86_BUILTIN_CVTTPD2DQ,
28060 IX86_BUILTIN_CVTTPD2PI,
28062 IX86_BUILTIN_CVTPI2PD,
28063 IX86_BUILTIN_CVTSI2SD,
28064 IX86_BUILTIN_CVTSI642SD,
28066 IX86_BUILTIN_CVTSD2SI,
28067 IX86_BUILTIN_CVTSD2SI64,
28068 IX86_BUILTIN_CVTSD2SS,
28069 IX86_BUILTIN_CVTSS2SD,
28070 IX86_BUILTIN_CVTTSD2SI,
28071 IX86_BUILTIN_CVTTSD2SI64,
28073 IX86_BUILTIN_CVTPS2DQ,
28074 IX86_BUILTIN_CVTPS2PD,
28075 IX86_BUILTIN_CVTTPS2DQ,
28077 IX86_BUILTIN_MOVNTI,
28078 IX86_BUILTIN_MOVNTI64,
28079 IX86_BUILTIN_MOVNTPD,
28080 IX86_BUILTIN_MOVNTDQ,
28082 IX86_BUILTIN_MOVQ128,
28084 /* SSE2 MMX */
28085 IX86_BUILTIN_MASKMOVDQU,
28086 IX86_BUILTIN_MOVMSKPD,
28087 IX86_BUILTIN_PMOVMSKB128,
28089 IX86_BUILTIN_PACKSSWB128,
28090 IX86_BUILTIN_PACKSSDW128,
28091 IX86_BUILTIN_PACKUSWB128,
28093 IX86_BUILTIN_PADDB128,
28094 IX86_BUILTIN_PADDW128,
28095 IX86_BUILTIN_PADDD128,
28096 IX86_BUILTIN_PADDQ128,
28097 IX86_BUILTIN_PADDSB128,
28098 IX86_BUILTIN_PADDSW128,
28099 IX86_BUILTIN_PADDUSB128,
28100 IX86_BUILTIN_PADDUSW128,
28101 IX86_BUILTIN_PSUBB128,
28102 IX86_BUILTIN_PSUBW128,
28103 IX86_BUILTIN_PSUBD128,
28104 IX86_BUILTIN_PSUBQ128,
28105 IX86_BUILTIN_PSUBSB128,
28106 IX86_BUILTIN_PSUBSW128,
28107 IX86_BUILTIN_PSUBUSB128,
28108 IX86_BUILTIN_PSUBUSW128,
28110 IX86_BUILTIN_PAND128,
28111 IX86_BUILTIN_PANDN128,
28112 IX86_BUILTIN_POR128,
28113 IX86_BUILTIN_PXOR128,
28115 IX86_BUILTIN_PAVGB128,
28116 IX86_BUILTIN_PAVGW128,
28118 IX86_BUILTIN_PCMPEQB128,
28119 IX86_BUILTIN_PCMPEQW128,
28120 IX86_BUILTIN_PCMPEQD128,
28121 IX86_BUILTIN_PCMPGTB128,
28122 IX86_BUILTIN_PCMPGTW128,
28123 IX86_BUILTIN_PCMPGTD128,
28125 IX86_BUILTIN_PMADDWD128,
28127 IX86_BUILTIN_PMAXSW128,
28128 IX86_BUILTIN_PMAXUB128,
28129 IX86_BUILTIN_PMINSW128,
28130 IX86_BUILTIN_PMINUB128,
28132 IX86_BUILTIN_PMULUDQ,
28133 IX86_BUILTIN_PMULUDQ128,
28134 IX86_BUILTIN_PMULHUW128,
28135 IX86_BUILTIN_PMULHW128,
28136 IX86_BUILTIN_PMULLW128,
28138 IX86_BUILTIN_PSADBW128,
28139 IX86_BUILTIN_PSHUFHW,
28140 IX86_BUILTIN_PSHUFLW,
28141 IX86_BUILTIN_PSHUFD,
28143 IX86_BUILTIN_PSLLDQI128,
28144 IX86_BUILTIN_PSLLWI128,
28145 IX86_BUILTIN_PSLLDI128,
28146 IX86_BUILTIN_PSLLQI128,
28147 IX86_BUILTIN_PSRAWI128,
28148 IX86_BUILTIN_PSRADI128,
28149 IX86_BUILTIN_PSRLDQI128,
28150 IX86_BUILTIN_PSRLWI128,
28151 IX86_BUILTIN_PSRLDI128,
28152 IX86_BUILTIN_PSRLQI128,
28154 IX86_BUILTIN_PSLLDQ128,
28155 IX86_BUILTIN_PSLLW128,
28156 IX86_BUILTIN_PSLLD128,
28157 IX86_BUILTIN_PSLLQ128,
28158 IX86_BUILTIN_PSRAW128,
28159 IX86_BUILTIN_PSRAD128,
28160 IX86_BUILTIN_PSRLW128,
28161 IX86_BUILTIN_PSRLD128,
28162 IX86_BUILTIN_PSRLQ128,
28164 IX86_BUILTIN_PUNPCKHBW128,
28165 IX86_BUILTIN_PUNPCKHWD128,
28166 IX86_BUILTIN_PUNPCKHDQ128,
28167 IX86_BUILTIN_PUNPCKHQDQ128,
28168 IX86_BUILTIN_PUNPCKLBW128,
28169 IX86_BUILTIN_PUNPCKLWD128,
28170 IX86_BUILTIN_PUNPCKLDQ128,
28171 IX86_BUILTIN_PUNPCKLQDQ128,
28173 IX86_BUILTIN_CLFLUSH,
28174 IX86_BUILTIN_MFENCE,
28175 IX86_BUILTIN_LFENCE,
28176 IX86_BUILTIN_PAUSE,
28178 IX86_BUILTIN_FNSTENV,
28179 IX86_BUILTIN_FLDENV,
28180 IX86_BUILTIN_FNSTSW,
28181 IX86_BUILTIN_FNCLEX,
28183 IX86_BUILTIN_BSRSI,
28184 IX86_BUILTIN_BSRDI,
28185 IX86_BUILTIN_RDPMC,
28186 IX86_BUILTIN_RDTSC,
28187 IX86_BUILTIN_RDTSCP,
28188 IX86_BUILTIN_ROLQI,
28189 IX86_BUILTIN_ROLHI,
28190 IX86_BUILTIN_RORQI,
28191 IX86_BUILTIN_RORHI,
28193 /* SSE3. */
28194 IX86_BUILTIN_ADDSUBPS,
28195 IX86_BUILTIN_HADDPS,
28196 IX86_BUILTIN_HSUBPS,
28197 IX86_BUILTIN_MOVSHDUP,
28198 IX86_BUILTIN_MOVSLDUP,
28199 IX86_BUILTIN_ADDSUBPD,
28200 IX86_BUILTIN_HADDPD,
28201 IX86_BUILTIN_HSUBPD,
28202 IX86_BUILTIN_LDDQU,
28204 IX86_BUILTIN_MONITOR,
28205 IX86_BUILTIN_MWAIT,
28207 /* SSSE3. */
28208 IX86_BUILTIN_PHADDW,
28209 IX86_BUILTIN_PHADDD,
28210 IX86_BUILTIN_PHADDSW,
28211 IX86_BUILTIN_PHSUBW,
28212 IX86_BUILTIN_PHSUBD,
28213 IX86_BUILTIN_PHSUBSW,
28214 IX86_BUILTIN_PMADDUBSW,
28215 IX86_BUILTIN_PMULHRSW,
28216 IX86_BUILTIN_PSHUFB,
28217 IX86_BUILTIN_PSIGNB,
28218 IX86_BUILTIN_PSIGNW,
28219 IX86_BUILTIN_PSIGND,
28220 IX86_BUILTIN_PALIGNR,
28221 IX86_BUILTIN_PABSB,
28222 IX86_BUILTIN_PABSW,
28223 IX86_BUILTIN_PABSD,
28225 IX86_BUILTIN_PHADDW128,
28226 IX86_BUILTIN_PHADDD128,
28227 IX86_BUILTIN_PHADDSW128,
28228 IX86_BUILTIN_PHSUBW128,
28229 IX86_BUILTIN_PHSUBD128,
28230 IX86_BUILTIN_PHSUBSW128,
28231 IX86_BUILTIN_PMADDUBSW128,
28232 IX86_BUILTIN_PMULHRSW128,
28233 IX86_BUILTIN_PSHUFB128,
28234 IX86_BUILTIN_PSIGNB128,
28235 IX86_BUILTIN_PSIGNW128,
28236 IX86_BUILTIN_PSIGND128,
28237 IX86_BUILTIN_PALIGNR128,
28238 IX86_BUILTIN_PABSB128,
28239 IX86_BUILTIN_PABSW128,
28240 IX86_BUILTIN_PABSD128,
28242 /* AMDFAM10 - SSE4A New Instructions. */
28243 IX86_BUILTIN_MOVNTSD,
28244 IX86_BUILTIN_MOVNTSS,
28245 IX86_BUILTIN_EXTRQI,
28246 IX86_BUILTIN_EXTRQ,
28247 IX86_BUILTIN_INSERTQI,
28248 IX86_BUILTIN_INSERTQ,
28250 /* SSE4.1. */
28251 IX86_BUILTIN_BLENDPD,
28252 IX86_BUILTIN_BLENDPS,
28253 IX86_BUILTIN_BLENDVPD,
28254 IX86_BUILTIN_BLENDVPS,
28255 IX86_BUILTIN_PBLENDVB128,
28256 IX86_BUILTIN_PBLENDW128,
28258 IX86_BUILTIN_DPPD,
28259 IX86_BUILTIN_DPPS,
28261 IX86_BUILTIN_INSERTPS128,
28263 IX86_BUILTIN_MOVNTDQA,
28264 IX86_BUILTIN_MPSADBW128,
28265 IX86_BUILTIN_PACKUSDW128,
28266 IX86_BUILTIN_PCMPEQQ,
28267 IX86_BUILTIN_PHMINPOSUW128,
28269 IX86_BUILTIN_PMAXSB128,
28270 IX86_BUILTIN_PMAXSD128,
28271 IX86_BUILTIN_PMAXUD128,
28272 IX86_BUILTIN_PMAXUW128,
28274 IX86_BUILTIN_PMINSB128,
28275 IX86_BUILTIN_PMINSD128,
28276 IX86_BUILTIN_PMINUD128,
28277 IX86_BUILTIN_PMINUW128,
28279 IX86_BUILTIN_PMOVSXBW128,
28280 IX86_BUILTIN_PMOVSXBD128,
28281 IX86_BUILTIN_PMOVSXBQ128,
28282 IX86_BUILTIN_PMOVSXWD128,
28283 IX86_BUILTIN_PMOVSXWQ128,
28284 IX86_BUILTIN_PMOVSXDQ128,
28286 IX86_BUILTIN_PMOVZXBW128,
28287 IX86_BUILTIN_PMOVZXBD128,
28288 IX86_BUILTIN_PMOVZXBQ128,
28289 IX86_BUILTIN_PMOVZXWD128,
28290 IX86_BUILTIN_PMOVZXWQ128,
28291 IX86_BUILTIN_PMOVZXDQ128,
28293 IX86_BUILTIN_PMULDQ128,
28294 IX86_BUILTIN_PMULLD128,
28296 IX86_BUILTIN_ROUNDSD,
28297 IX86_BUILTIN_ROUNDSS,
28299 IX86_BUILTIN_ROUNDPD,
28300 IX86_BUILTIN_ROUNDPS,
28302 IX86_BUILTIN_FLOORPD,
28303 IX86_BUILTIN_CEILPD,
28304 IX86_BUILTIN_TRUNCPD,
28305 IX86_BUILTIN_RINTPD,
28306 IX86_BUILTIN_ROUNDPD_AZ,
28308 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
28309 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
28310 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
28312 IX86_BUILTIN_FLOORPS,
28313 IX86_BUILTIN_CEILPS,
28314 IX86_BUILTIN_TRUNCPS,
28315 IX86_BUILTIN_RINTPS,
28316 IX86_BUILTIN_ROUNDPS_AZ,
28318 IX86_BUILTIN_FLOORPS_SFIX,
28319 IX86_BUILTIN_CEILPS_SFIX,
28320 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
28322 IX86_BUILTIN_PTESTZ,
28323 IX86_BUILTIN_PTESTC,
28324 IX86_BUILTIN_PTESTNZC,
28326 IX86_BUILTIN_VEC_INIT_V2SI,
28327 IX86_BUILTIN_VEC_INIT_V4HI,
28328 IX86_BUILTIN_VEC_INIT_V8QI,
28329 IX86_BUILTIN_VEC_EXT_V2DF,
28330 IX86_BUILTIN_VEC_EXT_V2DI,
28331 IX86_BUILTIN_VEC_EXT_V4SF,
28332 IX86_BUILTIN_VEC_EXT_V4SI,
28333 IX86_BUILTIN_VEC_EXT_V8HI,
28334 IX86_BUILTIN_VEC_EXT_V2SI,
28335 IX86_BUILTIN_VEC_EXT_V4HI,
28336 IX86_BUILTIN_VEC_EXT_V16QI,
28337 IX86_BUILTIN_VEC_SET_V2DI,
28338 IX86_BUILTIN_VEC_SET_V4SF,
28339 IX86_BUILTIN_VEC_SET_V4SI,
28340 IX86_BUILTIN_VEC_SET_V8HI,
28341 IX86_BUILTIN_VEC_SET_V4HI,
28342 IX86_BUILTIN_VEC_SET_V16QI,
28344 IX86_BUILTIN_VEC_PACK_SFIX,
28345 IX86_BUILTIN_VEC_PACK_SFIX256,
28347 /* SSE4.2. */
28348 IX86_BUILTIN_CRC32QI,
28349 IX86_BUILTIN_CRC32HI,
28350 IX86_BUILTIN_CRC32SI,
28351 IX86_BUILTIN_CRC32DI,
28353 IX86_BUILTIN_PCMPESTRI128,
28354 IX86_BUILTIN_PCMPESTRM128,
28355 IX86_BUILTIN_PCMPESTRA128,
28356 IX86_BUILTIN_PCMPESTRC128,
28357 IX86_BUILTIN_PCMPESTRO128,
28358 IX86_BUILTIN_PCMPESTRS128,
28359 IX86_BUILTIN_PCMPESTRZ128,
28360 IX86_BUILTIN_PCMPISTRI128,
28361 IX86_BUILTIN_PCMPISTRM128,
28362 IX86_BUILTIN_PCMPISTRA128,
28363 IX86_BUILTIN_PCMPISTRC128,
28364 IX86_BUILTIN_PCMPISTRO128,
28365 IX86_BUILTIN_PCMPISTRS128,
28366 IX86_BUILTIN_PCMPISTRZ128,
28368 IX86_BUILTIN_PCMPGTQ,
28370 /* AES instructions */
28371 IX86_BUILTIN_AESENC128,
28372 IX86_BUILTIN_AESENCLAST128,
28373 IX86_BUILTIN_AESDEC128,
28374 IX86_BUILTIN_AESDECLAST128,
28375 IX86_BUILTIN_AESIMC128,
28376 IX86_BUILTIN_AESKEYGENASSIST128,
28378 /* PCLMUL instruction */
28379 IX86_BUILTIN_PCLMULQDQ128,
28381 /* AVX */
28382 IX86_BUILTIN_ADDPD256,
28383 IX86_BUILTIN_ADDPS256,
28384 IX86_BUILTIN_ADDSUBPD256,
28385 IX86_BUILTIN_ADDSUBPS256,
28386 IX86_BUILTIN_ANDPD256,
28387 IX86_BUILTIN_ANDPS256,
28388 IX86_BUILTIN_ANDNPD256,
28389 IX86_BUILTIN_ANDNPS256,
28390 IX86_BUILTIN_BLENDPD256,
28391 IX86_BUILTIN_BLENDPS256,
28392 IX86_BUILTIN_BLENDVPD256,
28393 IX86_BUILTIN_BLENDVPS256,
28394 IX86_BUILTIN_DIVPD256,
28395 IX86_BUILTIN_DIVPS256,
28396 IX86_BUILTIN_DPPS256,
28397 IX86_BUILTIN_HADDPD256,
28398 IX86_BUILTIN_HADDPS256,
28399 IX86_BUILTIN_HSUBPD256,
28400 IX86_BUILTIN_HSUBPS256,
28401 IX86_BUILTIN_MAXPD256,
28402 IX86_BUILTIN_MAXPS256,
28403 IX86_BUILTIN_MINPD256,
28404 IX86_BUILTIN_MINPS256,
28405 IX86_BUILTIN_MULPD256,
28406 IX86_BUILTIN_MULPS256,
28407 IX86_BUILTIN_ORPD256,
28408 IX86_BUILTIN_ORPS256,
28409 IX86_BUILTIN_SHUFPD256,
28410 IX86_BUILTIN_SHUFPS256,
28411 IX86_BUILTIN_SUBPD256,
28412 IX86_BUILTIN_SUBPS256,
28413 IX86_BUILTIN_XORPD256,
28414 IX86_BUILTIN_XORPS256,
28415 IX86_BUILTIN_CMPSD,
28416 IX86_BUILTIN_CMPSS,
28417 IX86_BUILTIN_CMPPD,
28418 IX86_BUILTIN_CMPPS,
28419 IX86_BUILTIN_CMPPD256,
28420 IX86_BUILTIN_CMPPS256,
28421 IX86_BUILTIN_CVTDQ2PD256,
28422 IX86_BUILTIN_CVTDQ2PS256,
28423 IX86_BUILTIN_CVTPD2PS256,
28424 IX86_BUILTIN_CVTPS2DQ256,
28425 IX86_BUILTIN_CVTPS2PD256,
28426 IX86_BUILTIN_CVTTPD2DQ256,
28427 IX86_BUILTIN_CVTPD2DQ256,
28428 IX86_BUILTIN_CVTTPS2DQ256,
28429 IX86_BUILTIN_EXTRACTF128PD256,
28430 IX86_BUILTIN_EXTRACTF128PS256,
28431 IX86_BUILTIN_EXTRACTF128SI256,
28432 IX86_BUILTIN_VZEROALL,
28433 IX86_BUILTIN_VZEROUPPER,
28434 IX86_BUILTIN_VPERMILVARPD,
28435 IX86_BUILTIN_VPERMILVARPS,
28436 IX86_BUILTIN_VPERMILVARPD256,
28437 IX86_BUILTIN_VPERMILVARPS256,
28438 IX86_BUILTIN_VPERMILPD,
28439 IX86_BUILTIN_VPERMILPS,
28440 IX86_BUILTIN_VPERMILPD256,
28441 IX86_BUILTIN_VPERMILPS256,
28442 IX86_BUILTIN_VPERMIL2PD,
28443 IX86_BUILTIN_VPERMIL2PS,
28444 IX86_BUILTIN_VPERMIL2PD256,
28445 IX86_BUILTIN_VPERMIL2PS256,
28446 IX86_BUILTIN_VPERM2F128PD256,
28447 IX86_BUILTIN_VPERM2F128PS256,
28448 IX86_BUILTIN_VPERM2F128SI256,
28449 IX86_BUILTIN_VBROADCASTSS,
28450 IX86_BUILTIN_VBROADCASTSD256,
28451 IX86_BUILTIN_VBROADCASTSS256,
28452 IX86_BUILTIN_VBROADCASTPD256,
28453 IX86_BUILTIN_VBROADCASTPS256,
28454 IX86_BUILTIN_VINSERTF128PD256,
28455 IX86_BUILTIN_VINSERTF128PS256,
28456 IX86_BUILTIN_VINSERTF128SI256,
28457 IX86_BUILTIN_LOADUPD256,
28458 IX86_BUILTIN_LOADUPS256,
28459 IX86_BUILTIN_STOREUPD256,
28460 IX86_BUILTIN_STOREUPS256,
28461 IX86_BUILTIN_LDDQU256,
28462 IX86_BUILTIN_MOVNTDQ256,
28463 IX86_BUILTIN_MOVNTPD256,
28464 IX86_BUILTIN_MOVNTPS256,
28465 IX86_BUILTIN_LOADDQU256,
28466 IX86_BUILTIN_STOREDQU256,
28467 IX86_BUILTIN_MASKLOADPD,
28468 IX86_BUILTIN_MASKLOADPS,
28469 IX86_BUILTIN_MASKSTOREPD,
28470 IX86_BUILTIN_MASKSTOREPS,
28471 IX86_BUILTIN_MASKLOADPD256,
28472 IX86_BUILTIN_MASKLOADPS256,
28473 IX86_BUILTIN_MASKSTOREPD256,
28474 IX86_BUILTIN_MASKSTOREPS256,
28475 IX86_BUILTIN_MOVSHDUP256,
28476 IX86_BUILTIN_MOVSLDUP256,
28477 IX86_BUILTIN_MOVDDUP256,
28479 IX86_BUILTIN_SQRTPD256,
28480 IX86_BUILTIN_SQRTPS256,
28481 IX86_BUILTIN_SQRTPS_NR256,
28482 IX86_BUILTIN_RSQRTPS256,
28483 IX86_BUILTIN_RSQRTPS_NR256,
28485 IX86_BUILTIN_RCPPS256,
28487 IX86_BUILTIN_ROUNDPD256,
28488 IX86_BUILTIN_ROUNDPS256,
28490 IX86_BUILTIN_FLOORPD256,
28491 IX86_BUILTIN_CEILPD256,
28492 IX86_BUILTIN_TRUNCPD256,
28493 IX86_BUILTIN_RINTPD256,
28494 IX86_BUILTIN_ROUNDPD_AZ256,
28496 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
28497 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
28498 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
28500 IX86_BUILTIN_FLOORPS256,
28501 IX86_BUILTIN_CEILPS256,
28502 IX86_BUILTIN_TRUNCPS256,
28503 IX86_BUILTIN_RINTPS256,
28504 IX86_BUILTIN_ROUNDPS_AZ256,
28506 IX86_BUILTIN_FLOORPS_SFIX256,
28507 IX86_BUILTIN_CEILPS_SFIX256,
28508 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
28510 IX86_BUILTIN_UNPCKHPD256,
28511 IX86_BUILTIN_UNPCKLPD256,
28512 IX86_BUILTIN_UNPCKHPS256,
28513 IX86_BUILTIN_UNPCKLPS256,
28515 IX86_BUILTIN_SI256_SI,
28516 IX86_BUILTIN_PS256_PS,
28517 IX86_BUILTIN_PD256_PD,
28518 IX86_BUILTIN_SI_SI256,
28519 IX86_BUILTIN_PS_PS256,
28520 IX86_BUILTIN_PD_PD256,
28522 IX86_BUILTIN_VTESTZPD,
28523 IX86_BUILTIN_VTESTCPD,
28524 IX86_BUILTIN_VTESTNZCPD,
28525 IX86_BUILTIN_VTESTZPS,
28526 IX86_BUILTIN_VTESTCPS,
28527 IX86_BUILTIN_VTESTNZCPS,
28528 IX86_BUILTIN_VTESTZPD256,
28529 IX86_BUILTIN_VTESTCPD256,
28530 IX86_BUILTIN_VTESTNZCPD256,
28531 IX86_BUILTIN_VTESTZPS256,
28532 IX86_BUILTIN_VTESTCPS256,
28533 IX86_BUILTIN_VTESTNZCPS256,
28534 IX86_BUILTIN_PTESTZ256,
28535 IX86_BUILTIN_PTESTC256,
28536 IX86_BUILTIN_PTESTNZC256,
28538 IX86_BUILTIN_MOVMSKPD256,
28539 IX86_BUILTIN_MOVMSKPS256,
28541 /* AVX2 */
28542 IX86_BUILTIN_MPSADBW256,
28543 IX86_BUILTIN_PABSB256,
28544 IX86_BUILTIN_PABSW256,
28545 IX86_BUILTIN_PABSD256,
28546 IX86_BUILTIN_PACKSSDW256,
28547 IX86_BUILTIN_PACKSSWB256,
28548 IX86_BUILTIN_PACKUSDW256,
28549 IX86_BUILTIN_PACKUSWB256,
28550 IX86_BUILTIN_PADDB256,
28551 IX86_BUILTIN_PADDW256,
28552 IX86_BUILTIN_PADDD256,
28553 IX86_BUILTIN_PADDQ256,
28554 IX86_BUILTIN_PADDSB256,
28555 IX86_BUILTIN_PADDSW256,
28556 IX86_BUILTIN_PADDUSB256,
28557 IX86_BUILTIN_PADDUSW256,
28558 IX86_BUILTIN_PALIGNR256,
28559 IX86_BUILTIN_AND256I,
28560 IX86_BUILTIN_ANDNOT256I,
28561 IX86_BUILTIN_PAVGB256,
28562 IX86_BUILTIN_PAVGW256,
28563 IX86_BUILTIN_PBLENDVB256,
28564 IX86_BUILTIN_PBLENDVW256,
28565 IX86_BUILTIN_PCMPEQB256,
28566 IX86_BUILTIN_PCMPEQW256,
28567 IX86_BUILTIN_PCMPEQD256,
28568 IX86_BUILTIN_PCMPEQQ256,
28569 IX86_BUILTIN_PCMPGTB256,
28570 IX86_BUILTIN_PCMPGTW256,
28571 IX86_BUILTIN_PCMPGTD256,
28572 IX86_BUILTIN_PCMPGTQ256,
28573 IX86_BUILTIN_PHADDW256,
28574 IX86_BUILTIN_PHADDD256,
28575 IX86_BUILTIN_PHADDSW256,
28576 IX86_BUILTIN_PHSUBW256,
28577 IX86_BUILTIN_PHSUBD256,
28578 IX86_BUILTIN_PHSUBSW256,
28579 IX86_BUILTIN_PMADDUBSW256,
28580 IX86_BUILTIN_PMADDWD256,
28581 IX86_BUILTIN_PMAXSB256,
28582 IX86_BUILTIN_PMAXSW256,
28583 IX86_BUILTIN_PMAXSD256,
28584 IX86_BUILTIN_PMAXUB256,
28585 IX86_BUILTIN_PMAXUW256,
28586 IX86_BUILTIN_PMAXUD256,
28587 IX86_BUILTIN_PMINSB256,
28588 IX86_BUILTIN_PMINSW256,
28589 IX86_BUILTIN_PMINSD256,
28590 IX86_BUILTIN_PMINUB256,
28591 IX86_BUILTIN_PMINUW256,
28592 IX86_BUILTIN_PMINUD256,
28593 IX86_BUILTIN_PMOVMSKB256,
28594 IX86_BUILTIN_PMOVSXBW256,
28595 IX86_BUILTIN_PMOVSXBD256,
28596 IX86_BUILTIN_PMOVSXBQ256,
28597 IX86_BUILTIN_PMOVSXWD256,
28598 IX86_BUILTIN_PMOVSXWQ256,
28599 IX86_BUILTIN_PMOVSXDQ256,
28600 IX86_BUILTIN_PMOVZXBW256,
28601 IX86_BUILTIN_PMOVZXBD256,
28602 IX86_BUILTIN_PMOVZXBQ256,
28603 IX86_BUILTIN_PMOVZXWD256,
28604 IX86_BUILTIN_PMOVZXWQ256,
28605 IX86_BUILTIN_PMOVZXDQ256,
28606 IX86_BUILTIN_PMULDQ256,
28607 IX86_BUILTIN_PMULHRSW256,
28608 IX86_BUILTIN_PMULHUW256,
28609 IX86_BUILTIN_PMULHW256,
28610 IX86_BUILTIN_PMULLW256,
28611 IX86_BUILTIN_PMULLD256,
28612 IX86_BUILTIN_PMULUDQ256,
28613 IX86_BUILTIN_POR256,
28614 IX86_BUILTIN_PSADBW256,
28615 IX86_BUILTIN_PSHUFB256,
28616 IX86_BUILTIN_PSHUFD256,
28617 IX86_BUILTIN_PSHUFHW256,
28618 IX86_BUILTIN_PSHUFLW256,
28619 IX86_BUILTIN_PSIGNB256,
28620 IX86_BUILTIN_PSIGNW256,
28621 IX86_BUILTIN_PSIGND256,
28622 IX86_BUILTIN_PSLLDQI256,
28623 IX86_BUILTIN_PSLLWI256,
28624 IX86_BUILTIN_PSLLW256,
28625 IX86_BUILTIN_PSLLDI256,
28626 IX86_BUILTIN_PSLLD256,
28627 IX86_BUILTIN_PSLLQI256,
28628 IX86_BUILTIN_PSLLQ256,
28629 IX86_BUILTIN_PSRAWI256,
28630 IX86_BUILTIN_PSRAW256,
28631 IX86_BUILTIN_PSRADI256,
28632 IX86_BUILTIN_PSRAD256,
28633 IX86_BUILTIN_PSRLDQI256,
28634 IX86_BUILTIN_PSRLWI256,
28635 IX86_BUILTIN_PSRLW256,
28636 IX86_BUILTIN_PSRLDI256,
28637 IX86_BUILTIN_PSRLD256,
28638 IX86_BUILTIN_PSRLQI256,
28639 IX86_BUILTIN_PSRLQ256,
28640 IX86_BUILTIN_PSUBB256,
28641 IX86_BUILTIN_PSUBW256,
28642 IX86_BUILTIN_PSUBD256,
28643 IX86_BUILTIN_PSUBQ256,
28644 IX86_BUILTIN_PSUBSB256,
28645 IX86_BUILTIN_PSUBSW256,
28646 IX86_BUILTIN_PSUBUSB256,
28647 IX86_BUILTIN_PSUBUSW256,
28648 IX86_BUILTIN_PUNPCKHBW256,
28649 IX86_BUILTIN_PUNPCKHWD256,
28650 IX86_BUILTIN_PUNPCKHDQ256,
28651 IX86_BUILTIN_PUNPCKHQDQ256,
28652 IX86_BUILTIN_PUNPCKLBW256,
28653 IX86_BUILTIN_PUNPCKLWD256,
28654 IX86_BUILTIN_PUNPCKLDQ256,
28655 IX86_BUILTIN_PUNPCKLQDQ256,
28656 IX86_BUILTIN_PXOR256,
28657 IX86_BUILTIN_MOVNTDQA256,
28658 IX86_BUILTIN_VBROADCASTSS_PS,
28659 IX86_BUILTIN_VBROADCASTSS_PS256,
28660 IX86_BUILTIN_VBROADCASTSD_PD256,
28661 IX86_BUILTIN_VBROADCASTSI256,
28662 IX86_BUILTIN_PBLENDD256,
28663 IX86_BUILTIN_PBLENDD128,
28664 IX86_BUILTIN_PBROADCASTB256,
28665 IX86_BUILTIN_PBROADCASTW256,
28666 IX86_BUILTIN_PBROADCASTD256,
28667 IX86_BUILTIN_PBROADCASTQ256,
28668 IX86_BUILTIN_PBROADCASTB128,
28669 IX86_BUILTIN_PBROADCASTW128,
28670 IX86_BUILTIN_PBROADCASTD128,
28671 IX86_BUILTIN_PBROADCASTQ128,
28672 IX86_BUILTIN_VPERMVARSI256,
28673 IX86_BUILTIN_VPERMDF256,
28674 IX86_BUILTIN_VPERMVARSF256,
28675 IX86_BUILTIN_VPERMDI256,
28676 IX86_BUILTIN_VPERMTI256,
28677 IX86_BUILTIN_VEXTRACT128I256,
28678 IX86_BUILTIN_VINSERT128I256,
28679 IX86_BUILTIN_MASKLOADD,
28680 IX86_BUILTIN_MASKLOADQ,
28681 IX86_BUILTIN_MASKLOADD256,
28682 IX86_BUILTIN_MASKLOADQ256,
28683 IX86_BUILTIN_MASKSTORED,
28684 IX86_BUILTIN_MASKSTOREQ,
28685 IX86_BUILTIN_MASKSTORED256,
28686 IX86_BUILTIN_MASKSTOREQ256,
28687 IX86_BUILTIN_PSLLVV4DI,
28688 IX86_BUILTIN_PSLLVV2DI,
28689 IX86_BUILTIN_PSLLVV8SI,
28690 IX86_BUILTIN_PSLLVV4SI,
28691 IX86_BUILTIN_PSRAVV8SI,
28692 IX86_BUILTIN_PSRAVV4SI,
28693 IX86_BUILTIN_PSRLVV4DI,
28694 IX86_BUILTIN_PSRLVV2DI,
28695 IX86_BUILTIN_PSRLVV8SI,
28696 IX86_BUILTIN_PSRLVV4SI,
28698 IX86_BUILTIN_GATHERSIV2DF,
28699 IX86_BUILTIN_GATHERSIV4DF,
28700 IX86_BUILTIN_GATHERDIV2DF,
28701 IX86_BUILTIN_GATHERDIV4DF,
28702 IX86_BUILTIN_GATHERSIV4SF,
28703 IX86_BUILTIN_GATHERSIV8SF,
28704 IX86_BUILTIN_GATHERDIV4SF,
28705 IX86_BUILTIN_GATHERDIV8SF,
28706 IX86_BUILTIN_GATHERSIV2DI,
28707 IX86_BUILTIN_GATHERSIV4DI,
28708 IX86_BUILTIN_GATHERDIV2DI,
28709 IX86_BUILTIN_GATHERDIV4DI,
28710 IX86_BUILTIN_GATHERSIV4SI,
28711 IX86_BUILTIN_GATHERSIV8SI,
28712 IX86_BUILTIN_GATHERDIV4SI,
28713 IX86_BUILTIN_GATHERDIV8SI,
28715 /* AVX512F */
28716 IX86_BUILTIN_SI512_SI256,
28717 IX86_BUILTIN_PD512_PD256,
28718 IX86_BUILTIN_PS512_PS256,
28719 IX86_BUILTIN_SI512_SI,
28720 IX86_BUILTIN_PD512_PD,
28721 IX86_BUILTIN_PS512_PS,
28722 IX86_BUILTIN_ADDPD512,
28723 IX86_BUILTIN_ADDPS512,
28724 IX86_BUILTIN_ADDSD_ROUND,
28725 IX86_BUILTIN_ADDSS_ROUND,
28726 IX86_BUILTIN_ALIGND512,
28727 IX86_BUILTIN_ALIGNQ512,
28728 IX86_BUILTIN_BLENDMD512,
28729 IX86_BUILTIN_BLENDMPD512,
28730 IX86_BUILTIN_BLENDMPS512,
28731 IX86_BUILTIN_BLENDMQ512,
28732 IX86_BUILTIN_BROADCASTF32X4_512,
28733 IX86_BUILTIN_BROADCASTF64X4_512,
28734 IX86_BUILTIN_BROADCASTI32X4_512,
28735 IX86_BUILTIN_BROADCASTI64X4_512,
28736 IX86_BUILTIN_BROADCASTSD512,
28737 IX86_BUILTIN_BROADCASTSS512,
28738 IX86_BUILTIN_CMPD512,
28739 IX86_BUILTIN_CMPPD512,
28740 IX86_BUILTIN_CMPPS512,
28741 IX86_BUILTIN_CMPQ512,
28742 IX86_BUILTIN_CMPSD_MASK,
28743 IX86_BUILTIN_CMPSS_MASK,
28744 IX86_BUILTIN_COMIDF,
28745 IX86_BUILTIN_COMISF,
28746 IX86_BUILTIN_COMPRESSPD512,
28747 IX86_BUILTIN_COMPRESSPDSTORE512,
28748 IX86_BUILTIN_COMPRESSPS512,
28749 IX86_BUILTIN_COMPRESSPSSTORE512,
28750 IX86_BUILTIN_CVTDQ2PD512,
28751 IX86_BUILTIN_CVTDQ2PS512,
28752 IX86_BUILTIN_CVTPD2DQ512,
28753 IX86_BUILTIN_CVTPD2PS512,
28754 IX86_BUILTIN_CVTPD2UDQ512,
28755 IX86_BUILTIN_CVTPH2PS512,
28756 IX86_BUILTIN_CVTPS2DQ512,
28757 IX86_BUILTIN_CVTPS2PD512,
28758 IX86_BUILTIN_CVTPS2PH512,
28759 IX86_BUILTIN_CVTPS2UDQ512,
28760 IX86_BUILTIN_CVTSD2SS_ROUND,
28761 IX86_BUILTIN_CVTSI2SD64,
28762 IX86_BUILTIN_CVTSI2SS32,
28763 IX86_BUILTIN_CVTSI2SS64,
28764 IX86_BUILTIN_CVTSS2SD_ROUND,
28765 IX86_BUILTIN_CVTTPD2DQ512,
28766 IX86_BUILTIN_CVTTPD2UDQ512,
28767 IX86_BUILTIN_CVTTPS2DQ512,
28768 IX86_BUILTIN_CVTTPS2UDQ512,
28769 IX86_BUILTIN_CVTUDQ2PD512,
28770 IX86_BUILTIN_CVTUDQ2PS512,
28771 IX86_BUILTIN_CVTUSI2SD32,
28772 IX86_BUILTIN_CVTUSI2SD64,
28773 IX86_BUILTIN_CVTUSI2SS32,
28774 IX86_BUILTIN_CVTUSI2SS64,
28775 IX86_BUILTIN_DIVPD512,
28776 IX86_BUILTIN_DIVPS512,
28777 IX86_BUILTIN_DIVSD_ROUND,
28778 IX86_BUILTIN_DIVSS_ROUND,
28779 IX86_BUILTIN_EXPANDPD512,
28780 IX86_BUILTIN_EXPANDPD512Z,
28781 IX86_BUILTIN_EXPANDPDLOAD512,
28782 IX86_BUILTIN_EXPANDPDLOAD512Z,
28783 IX86_BUILTIN_EXPANDPS512,
28784 IX86_BUILTIN_EXPANDPS512Z,
28785 IX86_BUILTIN_EXPANDPSLOAD512,
28786 IX86_BUILTIN_EXPANDPSLOAD512Z,
28787 IX86_BUILTIN_EXTRACTF32X4,
28788 IX86_BUILTIN_EXTRACTF64X4,
28789 IX86_BUILTIN_EXTRACTI32X4,
28790 IX86_BUILTIN_EXTRACTI64X4,
28791 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28792 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28793 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28794 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28795 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28796 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28797 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28798 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28799 IX86_BUILTIN_GETEXPPD512,
28800 IX86_BUILTIN_GETEXPPS512,
28801 IX86_BUILTIN_GETEXPSD128,
28802 IX86_BUILTIN_GETEXPSS128,
28803 IX86_BUILTIN_GETMANTPD512,
28804 IX86_BUILTIN_GETMANTPS512,
28805 IX86_BUILTIN_GETMANTSD128,
28806 IX86_BUILTIN_GETMANTSS128,
28807 IX86_BUILTIN_INSERTF32X4,
28808 IX86_BUILTIN_INSERTF64X4,
28809 IX86_BUILTIN_INSERTI32X4,
28810 IX86_BUILTIN_INSERTI64X4,
28811 IX86_BUILTIN_LOADAPD512,
28812 IX86_BUILTIN_LOADAPS512,
28813 IX86_BUILTIN_LOADDQUDI512,
28814 IX86_BUILTIN_LOADDQUSI512,
28815 IX86_BUILTIN_LOADUPD512,
28816 IX86_BUILTIN_LOADUPS512,
28817 IX86_BUILTIN_MAXPD512,
28818 IX86_BUILTIN_MAXPS512,
28819 IX86_BUILTIN_MAXSD_ROUND,
28820 IX86_BUILTIN_MAXSS_ROUND,
28821 IX86_BUILTIN_MINPD512,
28822 IX86_BUILTIN_MINPS512,
28823 IX86_BUILTIN_MINSD_ROUND,
28824 IX86_BUILTIN_MINSS_ROUND,
28825 IX86_BUILTIN_MOVAPD512,
28826 IX86_BUILTIN_MOVAPS512,
28827 IX86_BUILTIN_MOVDDUP512,
28828 IX86_BUILTIN_MOVDQA32LOAD512,
28829 IX86_BUILTIN_MOVDQA32STORE512,
28830 IX86_BUILTIN_MOVDQA32_512,
28831 IX86_BUILTIN_MOVDQA64LOAD512,
28832 IX86_BUILTIN_MOVDQA64STORE512,
28833 IX86_BUILTIN_MOVDQA64_512,
28834 IX86_BUILTIN_MOVNTDQ512,
28835 IX86_BUILTIN_MOVNTDQA512,
28836 IX86_BUILTIN_MOVNTPD512,
28837 IX86_BUILTIN_MOVNTPS512,
28838 IX86_BUILTIN_MOVSHDUP512,
28839 IX86_BUILTIN_MOVSLDUP512,
28840 IX86_BUILTIN_MULPD512,
28841 IX86_BUILTIN_MULPS512,
28842 IX86_BUILTIN_MULSD_ROUND,
28843 IX86_BUILTIN_MULSS_ROUND,
28844 IX86_BUILTIN_PABSD512,
28845 IX86_BUILTIN_PABSQ512,
28846 IX86_BUILTIN_PADDD512,
28847 IX86_BUILTIN_PADDQ512,
28848 IX86_BUILTIN_PANDD512,
28849 IX86_BUILTIN_PANDND512,
28850 IX86_BUILTIN_PANDNQ512,
28851 IX86_BUILTIN_PANDQ512,
28852 IX86_BUILTIN_PBROADCASTD512,
28853 IX86_BUILTIN_PBROADCASTD512_GPR,
28854 IX86_BUILTIN_PBROADCASTMB512,
28855 IX86_BUILTIN_PBROADCASTMW512,
28856 IX86_BUILTIN_PBROADCASTQ512,
28857 IX86_BUILTIN_PBROADCASTQ512_GPR,
28858 IX86_BUILTIN_PCMPEQD512_MASK,
28859 IX86_BUILTIN_PCMPEQQ512_MASK,
28860 IX86_BUILTIN_PCMPGTD512_MASK,
28861 IX86_BUILTIN_PCMPGTQ512_MASK,
28862 IX86_BUILTIN_PCOMPRESSD512,
28863 IX86_BUILTIN_PCOMPRESSDSTORE512,
28864 IX86_BUILTIN_PCOMPRESSQ512,
28865 IX86_BUILTIN_PCOMPRESSQSTORE512,
28866 IX86_BUILTIN_PEXPANDD512,
28867 IX86_BUILTIN_PEXPANDD512Z,
28868 IX86_BUILTIN_PEXPANDDLOAD512,
28869 IX86_BUILTIN_PEXPANDDLOAD512Z,
28870 IX86_BUILTIN_PEXPANDQ512,
28871 IX86_BUILTIN_PEXPANDQ512Z,
28872 IX86_BUILTIN_PEXPANDQLOAD512,
28873 IX86_BUILTIN_PEXPANDQLOAD512Z,
28874 IX86_BUILTIN_PMAXSD512,
28875 IX86_BUILTIN_PMAXSQ512,
28876 IX86_BUILTIN_PMAXUD512,
28877 IX86_BUILTIN_PMAXUQ512,
28878 IX86_BUILTIN_PMINSD512,
28879 IX86_BUILTIN_PMINSQ512,
28880 IX86_BUILTIN_PMINUD512,
28881 IX86_BUILTIN_PMINUQ512,
28882 IX86_BUILTIN_PMOVDB512,
28883 IX86_BUILTIN_PMOVDB512_MEM,
28884 IX86_BUILTIN_PMOVDW512,
28885 IX86_BUILTIN_PMOVDW512_MEM,
28886 IX86_BUILTIN_PMOVQB512,
28887 IX86_BUILTIN_PMOVQB512_MEM,
28888 IX86_BUILTIN_PMOVQD512,
28889 IX86_BUILTIN_PMOVQD512_MEM,
28890 IX86_BUILTIN_PMOVQW512,
28891 IX86_BUILTIN_PMOVQW512_MEM,
28892 IX86_BUILTIN_PMOVSDB512,
28893 IX86_BUILTIN_PMOVSDB512_MEM,
28894 IX86_BUILTIN_PMOVSDW512,
28895 IX86_BUILTIN_PMOVSDW512_MEM,
28896 IX86_BUILTIN_PMOVSQB512,
28897 IX86_BUILTIN_PMOVSQB512_MEM,
28898 IX86_BUILTIN_PMOVSQD512,
28899 IX86_BUILTIN_PMOVSQD512_MEM,
28900 IX86_BUILTIN_PMOVSQW512,
28901 IX86_BUILTIN_PMOVSQW512_MEM,
28902 IX86_BUILTIN_PMOVSXBD512,
28903 IX86_BUILTIN_PMOVSXBQ512,
28904 IX86_BUILTIN_PMOVSXDQ512,
28905 IX86_BUILTIN_PMOVSXWD512,
28906 IX86_BUILTIN_PMOVSXWQ512,
28907 IX86_BUILTIN_PMOVUSDB512,
28908 IX86_BUILTIN_PMOVUSDB512_MEM,
28909 IX86_BUILTIN_PMOVUSDW512,
28910 IX86_BUILTIN_PMOVUSDW512_MEM,
28911 IX86_BUILTIN_PMOVUSQB512,
28912 IX86_BUILTIN_PMOVUSQB512_MEM,
28913 IX86_BUILTIN_PMOVUSQD512,
28914 IX86_BUILTIN_PMOVUSQD512_MEM,
28915 IX86_BUILTIN_PMOVUSQW512,
28916 IX86_BUILTIN_PMOVUSQW512_MEM,
28917 IX86_BUILTIN_PMOVZXBD512,
28918 IX86_BUILTIN_PMOVZXBQ512,
28919 IX86_BUILTIN_PMOVZXDQ512,
28920 IX86_BUILTIN_PMOVZXWD512,
28921 IX86_BUILTIN_PMOVZXWQ512,
28922 IX86_BUILTIN_PMULDQ512,
28923 IX86_BUILTIN_PMULLD512,
28924 IX86_BUILTIN_PMULUDQ512,
28925 IX86_BUILTIN_PORD512,
28926 IX86_BUILTIN_PORQ512,
28927 IX86_BUILTIN_PROLD512,
28928 IX86_BUILTIN_PROLQ512,
28929 IX86_BUILTIN_PROLVD512,
28930 IX86_BUILTIN_PROLVQ512,
28931 IX86_BUILTIN_PRORD512,
28932 IX86_BUILTIN_PRORQ512,
28933 IX86_BUILTIN_PRORVD512,
28934 IX86_BUILTIN_PRORVQ512,
28935 IX86_BUILTIN_PSHUFD512,
28936 IX86_BUILTIN_PSLLD512,
28937 IX86_BUILTIN_PSLLDI512,
28938 IX86_BUILTIN_PSLLQ512,
28939 IX86_BUILTIN_PSLLQI512,
28940 IX86_BUILTIN_PSLLVV16SI,
28941 IX86_BUILTIN_PSLLVV8DI,
28942 IX86_BUILTIN_PSRAD512,
28943 IX86_BUILTIN_PSRADI512,
28944 IX86_BUILTIN_PSRAQ512,
28945 IX86_BUILTIN_PSRAQI512,
28946 IX86_BUILTIN_PSRAVV16SI,
28947 IX86_BUILTIN_PSRAVV8DI,
28948 IX86_BUILTIN_PSRLD512,
28949 IX86_BUILTIN_PSRLDI512,
28950 IX86_BUILTIN_PSRLQ512,
28951 IX86_BUILTIN_PSRLQI512,
28952 IX86_BUILTIN_PSRLVV16SI,
28953 IX86_BUILTIN_PSRLVV8DI,
28954 IX86_BUILTIN_PSUBD512,
28955 IX86_BUILTIN_PSUBQ512,
28956 IX86_BUILTIN_PTESTMD512,
28957 IX86_BUILTIN_PTESTMQ512,
28958 IX86_BUILTIN_PTESTNMD512,
28959 IX86_BUILTIN_PTESTNMQ512,
28960 IX86_BUILTIN_PUNPCKHDQ512,
28961 IX86_BUILTIN_PUNPCKHQDQ512,
28962 IX86_BUILTIN_PUNPCKLDQ512,
28963 IX86_BUILTIN_PUNPCKLQDQ512,
28964 IX86_BUILTIN_PXORD512,
28965 IX86_BUILTIN_PXORQ512,
28966 IX86_BUILTIN_RCP14PD512,
28967 IX86_BUILTIN_RCP14PS512,
28968 IX86_BUILTIN_RCP14SD,
28969 IX86_BUILTIN_RCP14SS,
28970 IX86_BUILTIN_RNDSCALEPD,
28971 IX86_BUILTIN_RNDSCALEPS,
28972 IX86_BUILTIN_RNDSCALESD,
28973 IX86_BUILTIN_RNDSCALESS,
28974 IX86_BUILTIN_RSQRT14PD512,
28975 IX86_BUILTIN_RSQRT14PS512,
28976 IX86_BUILTIN_RSQRT14SD,
28977 IX86_BUILTIN_RSQRT14SS,
28978 IX86_BUILTIN_SCALEFPD512,
28979 IX86_BUILTIN_SCALEFPS512,
28980 IX86_BUILTIN_SCALEFSD,
28981 IX86_BUILTIN_SCALEFSS,
28982 IX86_BUILTIN_SHUFPD512,
28983 IX86_BUILTIN_SHUFPS512,
28984 IX86_BUILTIN_SHUF_F32x4,
28985 IX86_BUILTIN_SHUF_F64x2,
28986 IX86_BUILTIN_SHUF_I32x4,
28987 IX86_BUILTIN_SHUF_I64x2,
28988 IX86_BUILTIN_SQRTPD512,
28989 IX86_BUILTIN_SQRTPD512_MASK,
28990 IX86_BUILTIN_SQRTPS512_MASK,
28991 IX86_BUILTIN_SQRTPS_NR512,
28992 IX86_BUILTIN_SQRTSD_ROUND,
28993 IX86_BUILTIN_SQRTSS_ROUND,
28994 IX86_BUILTIN_STOREAPD512,
28995 IX86_BUILTIN_STOREAPS512,
28996 IX86_BUILTIN_STOREDQUDI512,
28997 IX86_BUILTIN_STOREDQUSI512,
28998 IX86_BUILTIN_STOREUPD512,
28999 IX86_BUILTIN_STOREUPS512,
29000 IX86_BUILTIN_SUBPD512,
29001 IX86_BUILTIN_SUBPS512,
29002 IX86_BUILTIN_SUBSD_ROUND,
29003 IX86_BUILTIN_SUBSS_ROUND,
29004 IX86_BUILTIN_UCMPD512,
29005 IX86_BUILTIN_UCMPQ512,
29006 IX86_BUILTIN_UNPCKHPD512,
29007 IX86_BUILTIN_UNPCKHPS512,
29008 IX86_BUILTIN_UNPCKLPD512,
29009 IX86_BUILTIN_UNPCKLPS512,
29010 IX86_BUILTIN_VCVTSD2SI32,
29011 IX86_BUILTIN_VCVTSD2SI64,
29012 IX86_BUILTIN_VCVTSD2USI32,
29013 IX86_BUILTIN_VCVTSD2USI64,
29014 IX86_BUILTIN_VCVTSS2SI32,
29015 IX86_BUILTIN_VCVTSS2SI64,
29016 IX86_BUILTIN_VCVTSS2USI32,
29017 IX86_BUILTIN_VCVTSS2USI64,
29018 IX86_BUILTIN_VCVTTSD2SI32,
29019 IX86_BUILTIN_VCVTTSD2SI64,
29020 IX86_BUILTIN_VCVTTSD2USI32,
29021 IX86_BUILTIN_VCVTTSD2USI64,
29022 IX86_BUILTIN_VCVTTSS2SI32,
29023 IX86_BUILTIN_VCVTTSS2SI64,
29024 IX86_BUILTIN_VCVTTSS2USI32,
29025 IX86_BUILTIN_VCVTTSS2USI64,
29026 IX86_BUILTIN_VFMADDPD512_MASK,
29027 IX86_BUILTIN_VFMADDPD512_MASK3,
29028 IX86_BUILTIN_VFMADDPD512_MASKZ,
29029 IX86_BUILTIN_VFMADDPS512_MASK,
29030 IX86_BUILTIN_VFMADDPS512_MASK3,
29031 IX86_BUILTIN_VFMADDPS512_MASKZ,
29032 IX86_BUILTIN_VFMADDSD3_ROUND,
29033 IX86_BUILTIN_VFMADDSS3_ROUND,
29034 IX86_BUILTIN_VFMADDSUBPD512_MASK,
29035 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
29036 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
29037 IX86_BUILTIN_VFMADDSUBPS512_MASK,
29038 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
29039 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
29040 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
29041 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
29042 IX86_BUILTIN_VFMSUBPD512_MASK3,
29043 IX86_BUILTIN_VFMSUBPS512_MASK3,
29044 IX86_BUILTIN_VFMSUBSD3_MASK3,
29045 IX86_BUILTIN_VFMSUBSS3_MASK3,
29046 IX86_BUILTIN_VFNMADDPD512_MASK,
29047 IX86_BUILTIN_VFNMADDPS512_MASK,
29048 IX86_BUILTIN_VFNMSUBPD512_MASK,
29049 IX86_BUILTIN_VFNMSUBPD512_MASK3,
29050 IX86_BUILTIN_VFNMSUBPS512_MASK,
29051 IX86_BUILTIN_VFNMSUBPS512_MASK3,
29052 IX86_BUILTIN_VPCLZCNTD512,
29053 IX86_BUILTIN_VPCLZCNTQ512,
29054 IX86_BUILTIN_VPCONFLICTD512,
29055 IX86_BUILTIN_VPCONFLICTQ512,
29056 IX86_BUILTIN_VPERMDF512,
29057 IX86_BUILTIN_VPERMDI512,
29058 IX86_BUILTIN_VPERMI2VARD512,
29059 IX86_BUILTIN_VPERMI2VARPD512,
29060 IX86_BUILTIN_VPERMI2VARPS512,
29061 IX86_BUILTIN_VPERMI2VARQ512,
29062 IX86_BUILTIN_VPERMILPD512,
29063 IX86_BUILTIN_VPERMILPS512,
29064 IX86_BUILTIN_VPERMILVARPD512,
29065 IX86_BUILTIN_VPERMILVARPS512,
29066 IX86_BUILTIN_VPERMT2VARD512,
29067 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
29068 IX86_BUILTIN_VPERMT2VARPD512,
29069 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
29070 IX86_BUILTIN_VPERMT2VARPS512,
29071 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
29072 IX86_BUILTIN_VPERMT2VARQ512,
29073 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
29074 IX86_BUILTIN_VPERMVARDF512,
29075 IX86_BUILTIN_VPERMVARDI512,
29076 IX86_BUILTIN_VPERMVARSF512,
29077 IX86_BUILTIN_VPERMVARSI512,
29078 IX86_BUILTIN_VTERNLOGD512_MASK,
29079 IX86_BUILTIN_VTERNLOGD512_MASKZ,
29080 IX86_BUILTIN_VTERNLOGQ512_MASK,
29081 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
29083 /* Mask arithmetic operations */
29084 IX86_BUILTIN_KAND16,
29085 IX86_BUILTIN_KANDN16,
29086 IX86_BUILTIN_KNOT16,
29087 IX86_BUILTIN_KOR16,
29088 IX86_BUILTIN_KORTESTC16,
29089 IX86_BUILTIN_KORTESTZ16,
29090 IX86_BUILTIN_KUNPCKBW,
29091 IX86_BUILTIN_KXNOR16,
29092 IX86_BUILTIN_KXOR16,
29093 IX86_BUILTIN_KMOV16,
29095 /* AVX512VL. */
29096 IX86_BUILTIN_PMOVUSQD256_MEM,
29097 IX86_BUILTIN_PMOVUSQD128_MEM,
29098 IX86_BUILTIN_PMOVSQD256_MEM,
29099 IX86_BUILTIN_PMOVSQD128_MEM,
29100 IX86_BUILTIN_PMOVQD256_MEM,
29101 IX86_BUILTIN_PMOVQD128_MEM,
29102 IX86_BUILTIN_PMOVUSQW256_MEM,
29103 IX86_BUILTIN_PMOVUSQW128_MEM,
29104 IX86_BUILTIN_PMOVSQW256_MEM,
29105 IX86_BUILTIN_PMOVSQW128_MEM,
29106 IX86_BUILTIN_PMOVQW256_MEM,
29107 IX86_BUILTIN_PMOVQW128_MEM,
29108 IX86_BUILTIN_PMOVUSQB256_MEM,
29109 IX86_BUILTIN_PMOVUSQB128_MEM,
29110 IX86_BUILTIN_PMOVSQB256_MEM,
29111 IX86_BUILTIN_PMOVSQB128_MEM,
29112 IX86_BUILTIN_PMOVQB256_MEM,
29113 IX86_BUILTIN_PMOVQB128_MEM,
29114 IX86_BUILTIN_PMOVUSDW256_MEM,
29115 IX86_BUILTIN_PMOVUSDW128_MEM,
29116 IX86_BUILTIN_PMOVSDW256_MEM,
29117 IX86_BUILTIN_PMOVSDW128_MEM,
29118 IX86_BUILTIN_PMOVDW256_MEM,
29119 IX86_BUILTIN_PMOVDW128_MEM,
29120 IX86_BUILTIN_PMOVUSDB256_MEM,
29121 IX86_BUILTIN_PMOVUSDB128_MEM,
29122 IX86_BUILTIN_PMOVSDB256_MEM,
29123 IX86_BUILTIN_PMOVSDB128_MEM,
29124 IX86_BUILTIN_PMOVDB256_MEM,
29125 IX86_BUILTIN_PMOVDB128_MEM,
29126 IX86_BUILTIN_MOVDQA64LOAD256_MASK,
29127 IX86_BUILTIN_MOVDQA64LOAD128_MASK,
29128 IX86_BUILTIN_MOVDQA32LOAD256_MASK,
29129 IX86_BUILTIN_MOVDQA32LOAD128_MASK,
29130 IX86_BUILTIN_MOVDQA64STORE256_MASK,
29131 IX86_BUILTIN_MOVDQA64STORE128_MASK,
29132 IX86_BUILTIN_MOVDQA32STORE256_MASK,
29133 IX86_BUILTIN_MOVDQA32STORE128_MASK,
29134 IX86_BUILTIN_LOADAPD256_MASK,
29135 IX86_BUILTIN_LOADAPD128_MASK,
29136 IX86_BUILTIN_LOADAPS256_MASK,
29137 IX86_BUILTIN_LOADAPS128_MASK,
29138 IX86_BUILTIN_STOREAPD256_MASK,
29139 IX86_BUILTIN_STOREAPD128_MASK,
29140 IX86_BUILTIN_STOREAPS256_MASK,
29141 IX86_BUILTIN_STOREAPS128_MASK,
29142 IX86_BUILTIN_LOADUPD256_MASK,
29143 IX86_BUILTIN_LOADUPD128_MASK,
29144 IX86_BUILTIN_LOADUPS256_MASK,
29145 IX86_BUILTIN_LOADUPS128_MASK,
29146 IX86_BUILTIN_STOREUPD256_MASK,
29147 IX86_BUILTIN_STOREUPD128_MASK,
29148 IX86_BUILTIN_STOREUPS256_MASK,
29149 IX86_BUILTIN_STOREUPS128_MASK,
29150 IX86_BUILTIN_LOADDQUDI256_MASK,
29151 IX86_BUILTIN_LOADDQUDI128_MASK,
29152 IX86_BUILTIN_LOADDQUSI256_MASK,
29153 IX86_BUILTIN_LOADDQUSI128_MASK,
29154 IX86_BUILTIN_LOADDQUHI256_MASK,
29155 IX86_BUILTIN_LOADDQUHI128_MASK,
29156 IX86_BUILTIN_LOADDQUQI256_MASK,
29157 IX86_BUILTIN_LOADDQUQI128_MASK,
29158 IX86_BUILTIN_STOREDQUDI256_MASK,
29159 IX86_BUILTIN_STOREDQUDI128_MASK,
29160 IX86_BUILTIN_STOREDQUSI256_MASK,
29161 IX86_BUILTIN_STOREDQUSI128_MASK,
29162 IX86_BUILTIN_STOREDQUHI256_MASK,
29163 IX86_BUILTIN_STOREDQUHI128_MASK,
29164 IX86_BUILTIN_STOREDQUQI256_MASK,
29165 IX86_BUILTIN_STOREDQUQI128_MASK,
29166 IX86_BUILTIN_COMPRESSPDSTORE256,
29167 IX86_BUILTIN_COMPRESSPDSTORE128,
29168 IX86_BUILTIN_COMPRESSPSSTORE256,
29169 IX86_BUILTIN_COMPRESSPSSTORE128,
29170 IX86_BUILTIN_PCOMPRESSQSTORE256,
29171 IX86_BUILTIN_PCOMPRESSQSTORE128,
29172 IX86_BUILTIN_PCOMPRESSDSTORE256,
29173 IX86_BUILTIN_PCOMPRESSDSTORE128,
29174 IX86_BUILTIN_EXPANDPDLOAD256,
29175 IX86_BUILTIN_EXPANDPDLOAD128,
29176 IX86_BUILTIN_EXPANDPSLOAD256,
29177 IX86_BUILTIN_EXPANDPSLOAD128,
29178 IX86_BUILTIN_PEXPANDQLOAD256,
29179 IX86_BUILTIN_PEXPANDQLOAD128,
29180 IX86_BUILTIN_PEXPANDDLOAD256,
29181 IX86_BUILTIN_PEXPANDDLOAD128,
29182 IX86_BUILTIN_EXPANDPDLOAD256Z,
29183 IX86_BUILTIN_EXPANDPDLOAD128Z,
29184 IX86_BUILTIN_EXPANDPSLOAD256Z,
29185 IX86_BUILTIN_EXPANDPSLOAD128Z,
29186 IX86_BUILTIN_PEXPANDQLOAD256Z,
29187 IX86_BUILTIN_PEXPANDQLOAD128Z,
29188 IX86_BUILTIN_PEXPANDDLOAD256Z,
29189 IX86_BUILTIN_PEXPANDDLOAD128Z,
29190 IX86_BUILTIN_PALIGNR256_MASK,
29191 IX86_BUILTIN_PALIGNR128_MASK,
29192 IX86_BUILTIN_MOVDQA64_256_MASK,
29193 IX86_BUILTIN_MOVDQA64_128_MASK,
29194 IX86_BUILTIN_MOVDQA32_256_MASK,
29195 IX86_BUILTIN_MOVDQA32_128_MASK,
29196 IX86_BUILTIN_MOVAPD256_MASK,
29197 IX86_BUILTIN_MOVAPD128_MASK,
29198 IX86_BUILTIN_MOVAPS256_MASK,
29199 IX86_BUILTIN_MOVAPS128_MASK,
29200 IX86_BUILTIN_MOVDQUHI256_MASK,
29201 IX86_BUILTIN_MOVDQUHI128_MASK,
29202 IX86_BUILTIN_MOVDQUQI256_MASK,
29203 IX86_BUILTIN_MOVDQUQI128_MASK,
29204 IX86_BUILTIN_MINPS128_MASK,
29205 IX86_BUILTIN_MAXPS128_MASK,
29206 IX86_BUILTIN_MINPD128_MASK,
29207 IX86_BUILTIN_MAXPD128_MASK,
29208 IX86_BUILTIN_MAXPD256_MASK,
29209 IX86_BUILTIN_MAXPS256_MASK,
29210 IX86_BUILTIN_MINPD256_MASK,
29211 IX86_BUILTIN_MINPS256_MASK,
29212 IX86_BUILTIN_MULPS128_MASK,
29213 IX86_BUILTIN_DIVPS128_MASK,
29214 IX86_BUILTIN_MULPD128_MASK,
29215 IX86_BUILTIN_DIVPD128_MASK,
29216 IX86_BUILTIN_DIVPD256_MASK,
29217 IX86_BUILTIN_DIVPS256_MASK,
29218 IX86_BUILTIN_MULPD256_MASK,
29219 IX86_BUILTIN_MULPS256_MASK,
29220 IX86_BUILTIN_ADDPD128_MASK,
29221 IX86_BUILTIN_ADDPD256_MASK,
29222 IX86_BUILTIN_ADDPS128_MASK,
29223 IX86_BUILTIN_ADDPS256_MASK,
29224 IX86_BUILTIN_SUBPD128_MASK,
29225 IX86_BUILTIN_SUBPD256_MASK,
29226 IX86_BUILTIN_SUBPS128_MASK,
29227 IX86_BUILTIN_SUBPS256_MASK,
29228 IX86_BUILTIN_XORPD256_MASK,
29229 IX86_BUILTIN_XORPD128_MASK,
29230 IX86_BUILTIN_XORPS256_MASK,
29231 IX86_BUILTIN_XORPS128_MASK,
29232 IX86_BUILTIN_ORPD256_MASK,
29233 IX86_BUILTIN_ORPD128_MASK,
29234 IX86_BUILTIN_ORPS256_MASK,
29235 IX86_BUILTIN_ORPS128_MASK,
29236 IX86_BUILTIN_BROADCASTF32x2_256,
29237 IX86_BUILTIN_BROADCASTI32x2_256,
29238 IX86_BUILTIN_BROADCASTI32x2_128,
29239 IX86_BUILTIN_BROADCASTF64X2_256,
29240 IX86_BUILTIN_BROADCASTI64X2_256,
29241 IX86_BUILTIN_BROADCASTF32X4_256,
29242 IX86_BUILTIN_BROADCASTI32X4_256,
29243 IX86_BUILTIN_EXTRACTF32X4_256,
29244 IX86_BUILTIN_EXTRACTI32X4_256,
29245 IX86_BUILTIN_DBPSADBW256,
29246 IX86_BUILTIN_DBPSADBW128,
29247 IX86_BUILTIN_CVTTPD2QQ256,
29248 IX86_BUILTIN_CVTTPD2QQ128,
29249 IX86_BUILTIN_CVTTPD2UQQ256,
29250 IX86_BUILTIN_CVTTPD2UQQ128,
29251 IX86_BUILTIN_CVTPD2QQ256,
29252 IX86_BUILTIN_CVTPD2QQ128,
29253 IX86_BUILTIN_CVTPD2UQQ256,
29254 IX86_BUILTIN_CVTPD2UQQ128,
29255 IX86_BUILTIN_CVTPD2UDQ256_MASK,
29256 IX86_BUILTIN_CVTPD2UDQ128_MASK,
29257 IX86_BUILTIN_CVTTPS2QQ256,
29258 IX86_BUILTIN_CVTTPS2QQ128,
29259 IX86_BUILTIN_CVTTPS2UQQ256,
29260 IX86_BUILTIN_CVTTPS2UQQ128,
29261 IX86_BUILTIN_CVTTPS2DQ256_MASK,
29262 IX86_BUILTIN_CVTTPS2DQ128_MASK,
29263 IX86_BUILTIN_CVTTPS2UDQ256,
29264 IX86_BUILTIN_CVTTPS2UDQ128,
29265 IX86_BUILTIN_CVTTPD2DQ256_MASK,
29266 IX86_BUILTIN_CVTTPD2DQ128_MASK,
29267 IX86_BUILTIN_CVTTPD2UDQ256_MASK,
29268 IX86_BUILTIN_CVTTPD2UDQ128_MASK,
29269 IX86_BUILTIN_CVTPD2DQ256_MASK,
29270 IX86_BUILTIN_CVTPD2DQ128_MASK,
29271 IX86_BUILTIN_CVTDQ2PD256_MASK,
29272 IX86_BUILTIN_CVTDQ2PD128_MASK,
29273 IX86_BUILTIN_CVTUDQ2PD256_MASK,
29274 IX86_BUILTIN_CVTUDQ2PD128_MASK,
29275 IX86_BUILTIN_CVTDQ2PS256_MASK,
29276 IX86_BUILTIN_CVTDQ2PS128_MASK,
29277 IX86_BUILTIN_CVTUDQ2PS256_MASK,
29278 IX86_BUILTIN_CVTUDQ2PS128_MASK,
29279 IX86_BUILTIN_CVTPS2PD256_MASK,
29280 IX86_BUILTIN_CVTPS2PD128_MASK,
29281 IX86_BUILTIN_PBROADCASTB256_MASK,
29282 IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
29283 IX86_BUILTIN_PBROADCASTB128_MASK,
29284 IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
29285 IX86_BUILTIN_PBROADCASTW256_MASK,
29286 IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
29287 IX86_BUILTIN_PBROADCASTW128_MASK,
29288 IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
29289 IX86_BUILTIN_PBROADCASTD256_MASK,
29290 IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
29291 IX86_BUILTIN_PBROADCASTD128_MASK,
29292 IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
29293 IX86_BUILTIN_PBROADCASTQ256_MASK,
29294 IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
29295 IX86_BUILTIN_PBROADCASTQ128_MASK,
29296 IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
29297 IX86_BUILTIN_BROADCASTSS256,
29298 IX86_BUILTIN_BROADCASTSS128,
29299 IX86_BUILTIN_BROADCASTSD256,
29300 IX86_BUILTIN_EXTRACTF64X2_256,
29301 IX86_BUILTIN_EXTRACTI64X2_256,
29302 IX86_BUILTIN_INSERTF32X4_256,
29303 IX86_BUILTIN_INSERTI32X4_256,
29304 IX86_BUILTIN_PMOVSXBW256_MASK,
29305 IX86_BUILTIN_PMOVSXBW128_MASK,
29306 IX86_BUILTIN_PMOVSXBD256_MASK,
29307 IX86_BUILTIN_PMOVSXBD128_MASK,
29308 IX86_BUILTIN_PMOVSXBQ256_MASK,
29309 IX86_BUILTIN_PMOVSXBQ128_MASK,
29310 IX86_BUILTIN_PMOVSXWD256_MASK,
29311 IX86_BUILTIN_PMOVSXWD128_MASK,
29312 IX86_BUILTIN_PMOVSXWQ256_MASK,
29313 IX86_BUILTIN_PMOVSXWQ128_MASK,
29314 IX86_BUILTIN_PMOVSXDQ256_MASK,
29315 IX86_BUILTIN_PMOVSXDQ128_MASK,
29316 IX86_BUILTIN_PMOVZXBW256_MASK,
29317 IX86_BUILTIN_PMOVZXBW128_MASK,
29318 IX86_BUILTIN_PMOVZXBD256_MASK,
29319 IX86_BUILTIN_PMOVZXBD128_MASK,
29320 IX86_BUILTIN_PMOVZXBQ256_MASK,
29321 IX86_BUILTIN_PMOVZXBQ128_MASK,
29322 IX86_BUILTIN_PMOVZXWD256_MASK,
29323 IX86_BUILTIN_PMOVZXWD128_MASK,
29324 IX86_BUILTIN_PMOVZXWQ256_MASK,
29325 IX86_BUILTIN_PMOVZXWQ128_MASK,
29326 IX86_BUILTIN_PMOVZXDQ256_MASK,
29327 IX86_BUILTIN_PMOVZXDQ128_MASK,
29328 IX86_BUILTIN_REDUCEPD256_MASK,
29329 IX86_BUILTIN_REDUCEPD128_MASK,
29330 IX86_BUILTIN_REDUCEPS256_MASK,
29331 IX86_BUILTIN_REDUCEPS128_MASK,
29332 IX86_BUILTIN_REDUCESD_MASK,
29333 IX86_BUILTIN_REDUCESS_MASK,
29334 IX86_BUILTIN_VPERMVARHI256_MASK,
29335 IX86_BUILTIN_VPERMVARHI128_MASK,
29336 IX86_BUILTIN_VPERMT2VARHI256,
29337 IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
29338 IX86_BUILTIN_VPERMT2VARHI128,
29339 IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
29340 IX86_BUILTIN_VPERMI2VARHI256,
29341 IX86_BUILTIN_VPERMI2VARHI128,
29342 IX86_BUILTIN_RCP14PD256,
29343 IX86_BUILTIN_RCP14PD128,
29344 IX86_BUILTIN_RCP14PS256,
29345 IX86_BUILTIN_RCP14PS128,
29346 IX86_BUILTIN_RSQRT14PD256_MASK,
29347 IX86_BUILTIN_RSQRT14PD128_MASK,
29348 IX86_BUILTIN_RSQRT14PS256_MASK,
29349 IX86_BUILTIN_RSQRT14PS128_MASK,
29350 IX86_BUILTIN_SQRTPD256_MASK,
29351 IX86_BUILTIN_SQRTPD128_MASK,
29352 IX86_BUILTIN_SQRTPS256_MASK,
29353 IX86_BUILTIN_SQRTPS128_MASK,
29354 IX86_BUILTIN_PADDB128_MASK,
29355 IX86_BUILTIN_PADDW128_MASK,
29356 IX86_BUILTIN_PADDD128_MASK,
29357 IX86_BUILTIN_PADDQ128_MASK,
29358 IX86_BUILTIN_PSUBB128_MASK,
29359 IX86_BUILTIN_PSUBW128_MASK,
29360 IX86_BUILTIN_PSUBD128_MASK,
29361 IX86_BUILTIN_PSUBQ128_MASK,
29362 IX86_BUILTIN_PADDSB128_MASK,
29363 IX86_BUILTIN_PADDSW128_MASK,
29364 IX86_BUILTIN_PSUBSB128_MASK,
29365 IX86_BUILTIN_PSUBSW128_MASK,
29366 IX86_BUILTIN_PADDUSB128_MASK,
29367 IX86_BUILTIN_PADDUSW128_MASK,
29368 IX86_BUILTIN_PSUBUSB128_MASK,
29369 IX86_BUILTIN_PSUBUSW128_MASK,
29370 IX86_BUILTIN_PADDB256_MASK,
29371 IX86_BUILTIN_PADDW256_MASK,
29372 IX86_BUILTIN_PADDD256_MASK,
29373 IX86_BUILTIN_PADDQ256_MASK,
29374 IX86_BUILTIN_PADDSB256_MASK,
29375 IX86_BUILTIN_PADDSW256_MASK,
29376 IX86_BUILTIN_PADDUSB256_MASK,
29377 IX86_BUILTIN_PADDUSW256_MASK,
29378 IX86_BUILTIN_PSUBB256_MASK,
29379 IX86_BUILTIN_PSUBW256_MASK,
29380 IX86_BUILTIN_PSUBD256_MASK,
29381 IX86_BUILTIN_PSUBQ256_MASK,
29382 IX86_BUILTIN_PSUBSB256_MASK,
29383 IX86_BUILTIN_PSUBSW256_MASK,
29384 IX86_BUILTIN_PSUBUSB256_MASK,
29385 IX86_BUILTIN_PSUBUSW256_MASK,
29386 IX86_BUILTIN_SHUF_F64x2_256,
29387 IX86_BUILTIN_SHUF_I64x2_256,
29388 IX86_BUILTIN_SHUF_I32x4_256,
29389 IX86_BUILTIN_SHUF_F32x4_256,
29390 IX86_BUILTIN_PMOVWB128,
29391 IX86_BUILTIN_PMOVWB256,
29392 IX86_BUILTIN_PMOVSWB128,
29393 IX86_BUILTIN_PMOVSWB256,
29394 IX86_BUILTIN_PMOVUSWB128,
29395 IX86_BUILTIN_PMOVUSWB256,
29396 IX86_BUILTIN_PMOVDB128,
29397 IX86_BUILTIN_PMOVDB256,
29398 IX86_BUILTIN_PMOVSDB128,
29399 IX86_BUILTIN_PMOVSDB256,
29400 IX86_BUILTIN_PMOVUSDB128,
29401 IX86_BUILTIN_PMOVUSDB256,
29402 IX86_BUILTIN_PMOVDW128,
29403 IX86_BUILTIN_PMOVDW256,
29404 IX86_BUILTIN_PMOVSDW128,
29405 IX86_BUILTIN_PMOVSDW256,
29406 IX86_BUILTIN_PMOVUSDW128,
29407 IX86_BUILTIN_PMOVUSDW256,
29408 IX86_BUILTIN_PMOVQB128,
29409 IX86_BUILTIN_PMOVQB256,
29410 IX86_BUILTIN_PMOVSQB128,
29411 IX86_BUILTIN_PMOVSQB256,
29412 IX86_BUILTIN_PMOVUSQB128,
29413 IX86_BUILTIN_PMOVUSQB256,
29414 IX86_BUILTIN_PMOVQW128,
29415 IX86_BUILTIN_PMOVQW256,
29416 IX86_BUILTIN_PMOVSQW128,
29417 IX86_BUILTIN_PMOVSQW256,
29418 IX86_BUILTIN_PMOVUSQW128,
29419 IX86_BUILTIN_PMOVUSQW256,
29420 IX86_BUILTIN_PMOVQD128,
29421 IX86_BUILTIN_PMOVQD256,
29422 IX86_BUILTIN_PMOVSQD128,
29423 IX86_BUILTIN_PMOVSQD256,
29424 IX86_BUILTIN_PMOVUSQD128,
29425 IX86_BUILTIN_PMOVUSQD256,
29426 IX86_BUILTIN_RANGEPD256,
29427 IX86_BUILTIN_RANGEPD128,
29428 IX86_BUILTIN_RANGEPS256,
29429 IX86_BUILTIN_RANGEPS128,
29430 IX86_BUILTIN_GETEXPPS256,
29431 IX86_BUILTIN_GETEXPPD256,
29432 IX86_BUILTIN_GETEXPPS128,
29433 IX86_BUILTIN_GETEXPPD128,
29434 IX86_BUILTIN_FIXUPIMMPD256_MASK,
29435 IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
29436 IX86_BUILTIN_FIXUPIMMPS256_MASK,
29437 IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
29438 IX86_BUILTIN_FIXUPIMMPD128_MASK,
29439 IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
29440 IX86_BUILTIN_FIXUPIMMPS128_MASK,
29441 IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
29442 IX86_BUILTIN_PABSQ256,
29443 IX86_BUILTIN_PABSQ128,
29444 IX86_BUILTIN_PABSD256_MASK,
29445 IX86_BUILTIN_PABSD128_MASK,
29446 IX86_BUILTIN_PMULHRSW256_MASK,
29447 IX86_BUILTIN_PMULHRSW128_MASK,
29448 IX86_BUILTIN_PMULHUW128_MASK,
29449 IX86_BUILTIN_PMULHUW256_MASK,
29450 IX86_BUILTIN_PMULHW256_MASK,
29451 IX86_BUILTIN_PMULHW128_MASK,
29452 IX86_BUILTIN_PMULLW256_MASK,
29453 IX86_BUILTIN_PMULLW128_MASK,
29454 IX86_BUILTIN_PMULLQ256,
29455 IX86_BUILTIN_PMULLQ128,
29456 IX86_BUILTIN_ANDPD256_MASK,
29457 IX86_BUILTIN_ANDPD128_MASK,
29458 IX86_BUILTIN_ANDPS256_MASK,
29459 IX86_BUILTIN_ANDPS128_MASK,
29460 IX86_BUILTIN_ANDNPD256_MASK,
29461 IX86_BUILTIN_ANDNPD128_MASK,
29462 IX86_BUILTIN_ANDNPS256_MASK,
29463 IX86_BUILTIN_ANDNPS128_MASK,
29464 IX86_BUILTIN_PSLLWI128_MASK,
29465 IX86_BUILTIN_PSLLDI128_MASK,
29466 IX86_BUILTIN_PSLLQI128_MASK,
29467 IX86_BUILTIN_PSLLW128_MASK,
29468 IX86_BUILTIN_PSLLD128_MASK,
29469 IX86_BUILTIN_PSLLQ128_MASK,
29470 IX86_BUILTIN_PSLLWI256_MASK ,
29471 IX86_BUILTIN_PSLLW256_MASK,
29472 IX86_BUILTIN_PSLLDI256_MASK,
29473 IX86_BUILTIN_PSLLD256_MASK,
29474 IX86_BUILTIN_PSLLQI256_MASK,
29475 IX86_BUILTIN_PSLLQ256_MASK,
29476 IX86_BUILTIN_PSRADI128_MASK,
29477 IX86_BUILTIN_PSRAD128_MASK,
29478 IX86_BUILTIN_PSRADI256_MASK,
29479 IX86_BUILTIN_PSRAD256_MASK,
29480 IX86_BUILTIN_PSRAQI128_MASK,
29481 IX86_BUILTIN_PSRAQ128_MASK,
29482 IX86_BUILTIN_PSRAQI256_MASK,
29483 IX86_BUILTIN_PSRAQ256_MASK,
29484 IX86_BUILTIN_PANDD256,
29485 IX86_BUILTIN_PANDD128,
29486 IX86_BUILTIN_PSRLDI128_MASK,
29487 IX86_BUILTIN_PSRLD128_MASK,
29488 IX86_BUILTIN_PSRLDI256_MASK,
29489 IX86_BUILTIN_PSRLD256_MASK,
29490 IX86_BUILTIN_PSRLQI128_MASK,
29491 IX86_BUILTIN_PSRLQ128_MASK,
29492 IX86_BUILTIN_PSRLQI256_MASK,
29493 IX86_BUILTIN_PSRLQ256_MASK,
29494 IX86_BUILTIN_PANDQ256,
29495 IX86_BUILTIN_PANDQ128,
29496 IX86_BUILTIN_PANDND256,
29497 IX86_BUILTIN_PANDND128,
29498 IX86_BUILTIN_PANDNQ256,
29499 IX86_BUILTIN_PANDNQ128,
29500 IX86_BUILTIN_PORD256,
29501 IX86_BUILTIN_PORD128,
29502 IX86_BUILTIN_PORQ256,
29503 IX86_BUILTIN_PORQ128,
29504 IX86_BUILTIN_PXORD256,
29505 IX86_BUILTIN_PXORD128,
29506 IX86_BUILTIN_PXORQ256,
29507 IX86_BUILTIN_PXORQ128,
29508 IX86_BUILTIN_PACKSSWB256_MASK,
29509 IX86_BUILTIN_PACKSSWB128_MASK,
29510 IX86_BUILTIN_PACKUSWB256_MASK,
29511 IX86_BUILTIN_PACKUSWB128_MASK,
29512 IX86_BUILTIN_RNDSCALEPS256,
29513 IX86_BUILTIN_RNDSCALEPD256,
29514 IX86_BUILTIN_RNDSCALEPS128,
29515 IX86_BUILTIN_RNDSCALEPD128,
29516 IX86_BUILTIN_VTERNLOGQ256_MASK,
29517 IX86_BUILTIN_VTERNLOGQ256_MASKZ,
29518 IX86_BUILTIN_VTERNLOGD256_MASK,
29519 IX86_BUILTIN_VTERNLOGD256_MASKZ,
29520 IX86_BUILTIN_VTERNLOGQ128_MASK,
29521 IX86_BUILTIN_VTERNLOGQ128_MASKZ,
29522 IX86_BUILTIN_VTERNLOGD128_MASK,
29523 IX86_BUILTIN_VTERNLOGD128_MASKZ,
29524 IX86_BUILTIN_SCALEFPD256,
29525 IX86_BUILTIN_SCALEFPS256,
29526 IX86_BUILTIN_SCALEFPD128,
29527 IX86_BUILTIN_SCALEFPS128,
29528 IX86_BUILTIN_VFMADDPD256_MASK,
29529 IX86_BUILTIN_VFMADDPD256_MASK3,
29530 IX86_BUILTIN_VFMADDPD256_MASKZ,
29531 IX86_BUILTIN_VFMADDPD128_MASK,
29532 IX86_BUILTIN_VFMADDPD128_MASK3,
29533 IX86_BUILTIN_VFMADDPD128_MASKZ,
29534 IX86_BUILTIN_VFMADDPS256_MASK,
29535 IX86_BUILTIN_VFMADDPS256_MASK3,
29536 IX86_BUILTIN_VFMADDPS256_MASKZ,
29537 IX86_BUILTIN_VFMADDPS128_MASK,
29538 IX86_BUILTIN_VFMADDPS128_MASK3,
29539 IX86_BUILTIN_VFMADDPS128_MASKZ,
29540 IX86_BUILTIN_VFMSUBPD256_MASK3,
29541 IX86_BUILTIN_VFMSUBPD128_MASK3,
29542 IX86_BUILTIN_VFMSUBPS256_MASK3,
29543 IX86_BUILTIN_VFMSUBPS128_MASK3,
29544 IX86_BUILTIN_VFNMADDPD256_MASK,
29545 IX86_BUILTIN_VFNMADDPD128_MASK,
29546 IX86_BUILTIN_VFNMADDPS256_MASK,
29547 IX86_BUILTIN_VFNMADDPS128_MASK,
29548 IX86_BUILTIN_VFNMSUBPD256_MASK,
29549 IX86_BUILTIN_VFNMSUBPD256_MASK3,
29550 IX86_BUILTIN_VFNMSUBPD128_MASK,
29551 IX86_BUILTIN_VFNMSUBPD128_MASK3,
29552 IX86_BUILTIN_VFNMSUBPS256_MASK,
29553 IX86_BUILTIN_VFNMSUBPS256_MASK3,
29554 IX86_BUILTIN_VFNMSUBPS128_MASK,
29555 IX86_BUILTIN_VFNMSUBPS128_MASK3,
29556 IX86_BUILTIN_VFMADDSUBPD256_MASK,
29557 IX86_BUILTIN_VFMADDSUBPD256_MASK3,
29558 IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
29559 IX86_BUILTIN_VFMADDSUBPD128_MASK,
29560 IX86_BUILTIN_VFMADDSUBPD128_MASK3,
29561 IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
29562 IX86_BUILTIN_VFMADDSUBPS256_MASK,
29563 IX86_BUILTIN_VFMADDSUBPS256_MASK3,
29564 IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
29565 IX86_BUILTIN_VFMADDSUBPS128_MASK,
29566 IX86_BUILTIN_VFMADDSUBPS128_MASK3,
29567 IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
29568 IX86_BUILTIN_VFMSUBADDPD256_MASK3,
29569 IX86_BUILTIN_VFMSUBADDPD128_MASK3,
29570 IX86_BUILTIN_VFMSUBADDPS256_MASK3,
29571 IX86_BUILTIN_VFMSUBADDPS128_MASK3,
29572 IX86_BUILTIN_INSERTF64X2_256,
29573 IX86_BUILTIN_INSERTI64X2_256,
29574 IX86_BUILTIN_PSRAVV16HI,
29575 IX86_BUILTIN_PSRAVV8HI,
29576 IX86_BUILTIN_PMADDUBSW256_MASK,
29577 IX86_BUILTIN_PMADDUBSW128_MASK,
29578 IX86_BUILTIN_PMADDWD256_MASK,
29579 IX86_BUILTIN_PMADDWD128_MASK,
29580 IX86_BUILTIN_PSRLVV16HI,
29581 IX86_BUILTIN_PSRLVV8HI,
29582 IX86_BUILTIN_CVTPS2DQ256_MASK,
29583 IX86_BUILTIN_CVTPS2DQ128_MASK,
29584 IX86_BUILTIN_CVTPS2UDQ256,
29585 IX86_BUILTIN_CVTPS2UDQ128,
29586 IX86_BUILTIN_CVTPS2QQ256,
29587 IX86_BUILTIN_CVTPS2QQ128,
29588 IX86_BUILTIN_CVTPS2UQQ256,
29589 IX86_BUILTIN_CVTPS2UQQ128,
29590 IX86_BUILTIN_GETMANTPS256,
29591 IX86_BUILTIN_GETMANTPS128,
29592 IX86_BUILTIN_GETMANTPD256,
29593 IX86_BUILTIN_GETMANTPD128,
29594 IX86_BUILTIN_MOVDDUP256_MASK,
29595 IX86_BUILTIN_MOVDDUP128_MASK,
29596 IX86_BUILTIN_MOVSHDUP256_MASK,
29597 IX86_BUILTIN_MOVSHDUP128_MASK,
29598 IX86_BUILTIN_MOVSLDUP256_MASK,
29599 IX86_BUILTIN_MOVSLDUP128_MASK,
29600 IX86_BUILTIN_CVTQQ2PS256,
29601 IX86_BUILTIN_CVTQQ2PS128,
29602 IX86_BUILTIN_CVTUQQ2PS256,
29603 IX86_BUILTIN_CVTUQQ2PS128,
29604 IX86_BUILTIN_CVTQQ2PD256,
29605 IX86_BUILTIN_CVTQQ2PD128,
29606 IX86_BUILTIN_CVTUQQ2PD256,
29607 IX86_BUILTIN_CVTUQQ2PD128,
29608 IX86_BUILTIN_VPERMT2VARQ256,
29609 IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
29610 IX86_BUILTIN_VPERMT2VARD256,
29611 IX86_BUILTIN_VPERMT2VARD256_MASKZ,
29612 IX86_BUILTIN_VPERMI2VARQ256,
29613 IX86_BUILTIN_VPERMI2VARD256,
29614 IX86_BUILTIN_VPERMT2VARPD256,
29615 IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
29616 IX86_BUILTIN_VPERMT2VARPS256,
29617 IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
29618 IX86_BUILTIN_VPERMI2VARPD256,
29619 IX86_BUILTIN_VPERMI2VARPS256,
29620 IX86_BUILTIN_VPERMT2VARQ128,
29621 IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
29622 IX86_BUILTIN_VPERMT2VARD128,
29623 IX86_BUILTIN_VPERMT2VARD128_MASKZ,
29624 IX86_BUILTIN_VPERMI2VARQ128,
29625 IX86_BUILTIN_VPERMI2VARD128,
29626 IX86_BUILTIN_VPERMT2VARPD128,
29627 IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
29628 IX86_BUILTIN_VPERMT2VARPS128,
29629 IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
29630 IX86_BUILTIN_VPERMI2VARPD128,
29631 IX86_BUILTIN_VPERMI2VARPS128,
29632 IX86_BUILTIN_PSHUFB256_MASK,
29633 IX86_BUILTIN_PSHUFB128_MASK,
29634 IX86_BUILTIN_PSHUFHW256_MASK,
29635 IX86_BUILTIN_PSHUFHW128_MASK,
29636 IX86_BUILTIN_PSHUFLW256_MASK,
29637 IX86_BUILTIN_PSHUFLW128_MASK,
29638 IX86_BUILTIN_PSHUFD256_MASK,
29639 IX86_BUILTIN_PSHUFD128_MASK,
29640 IX86_BUILTIN_SHUFPD256_MASK,
29641 IX86_BUILTIN_SHUFPD128_MASK,
29642 IX86_BUILTIN_SHUFPS256_MASK,
29643 IX86_BUILTIN_SHUFPS128_MASK,
29644 IX86_BUILTIN_PROLVQ256,
29645 IX86_BUILTIN_PROLVQ128,
29646 IX86_BUILTIN_PROLQ256,
29647 IX86_BUILTIN_PROLQ128,
29648 IX86_BUILTIN_PRORVQ256,
29649 IX86_BUILTIN_PRORVQ128,
29650 IX86_BUILTIN_PRORQ256,
29651 IX86_BUILTIN_PRORQ128,
29652 IX86_BUILTIN_PSRAVQ128,
29653 IX86_BUILTIN_PSRAVQ256,
29654 IX86_BUILTIN_PSLLVV4DI_MASK,
29655 IX86_BUILTIN_PSLLVV2DI_MASK,
29656 IX86_BUILTIN_PSLLVV8SI_MASK,
29657 IX86_BUILTIN_PSLLVV4SI_MASK,
29658 IX86_BUILTIN_PSRAVV8SI_MASK,
29659 IX86_BUILTIN_PSRAVV4SI_MASK,
29660 IX86_BUILTIN_PSRLVV4DI_MASK,
29661 IX86_BUILTIN_PSRLVV2DI_MASK,
29662 IX86_BUILTIN_PSRLVV8SI_MASK,
29663 IX86_BUILTIN_PSRLVV4SI_MASK,
29664 IX86_BUILTIN_PSRAWI256_MASK,
29665 IX86_BUILTIN_PSRAW256_MASK,
29666 IX86_BUILTIN_PSRAWI128_MASK,
29667 IX86_BUILTIN_PSRAW128_MASK,
29668 IX86_BUILTIN_PSRLWI256_MASK,
29669 IX86_BUILTIN_PSRLW256_MASK,
29670 IX86_BUILTIN_PSRLWI128_MASK,
29671 IX86_BUILTIN_PSRLW128_MASK,
29672 IX86_BUILTIN_PRORVD256,
29673 IX86_BUILTIN_PROLVD256,
29674 IX86_BUILTIN_PRORD256,
29675 IX86_BUILTIN_PROLD256,
29676 IX86_BUILTIN_PRORVD128,
29677 IX86_BUILTIN_PROLVD128,
29678 IX86_BUILTIN_PRORD128,
29679 IX86_BUILTIN_PROLD128,
29680 IX86_BUILTIN_FPCLASSPD256,
29681 IX86_BUILTIN_FPCLASSPD128,
29682 IX86_BUILTIN_FPCLASSSD,
29683 IX86_BUILTIN_FPCLASSPS256,
29684 IX86_BUILTIN_FPCLASSPS128,
29685 IX86_BUILTIN_FPCLASSSS,
29686 IX86_BUILTIN_CVTB2MASK128,
29687 IX86_BUILTIN_CVTB2MASK256,
29688 IX86_BUILTIN_CVTW2MASK128,
29689 IX86_BUILTIN_CVTW2MASK256,
29690 IX86_BUILTIN_CVTD2MASK128,
29691 IX86_BUILTIN_CVTD2MASK256,
29692 IX86_BUILTIN_CVTQ2MASK128,
29693 IX86_BUILTIN_CVTQ2MASK256,
29694 IX86_BUILTIN_CVTMASK2B128,
29695 IX86_BUILTIN_CVTMASK2B256,
29696 IX86_BUILTIN_CVTMASK2W128,
29697 IX86_BUILTIN_CVTMASK2W256,
29698 IX86_BUILTIN_CVTMASK2D128,
29699 IX86_BUILTIN_CVTMASK2D256,
29700 IX86_BUILTIN_CVTMASK2Q128,
29701 IX86_BUILTIN_CVTMASK2Q256,
29702 IX86_BUILTIN_PCMPEQB128_MASK,
29703 IX86_BUILTIN_PCMPEQB256_MASK,
29704 IX86_BUILTIN_PCMPEQW128_MASK,
29705 IX86_BUILTIN_PCMPEQW256_MASK,
29706 IX86_BUILTIN_PCMPEQD128_MASK,
29707 IX86_BUILTIN_PCMPEQD256_MASK,
29708 IX86_BUILTIN_PCMPEQQ128_MASK,
29709 IX86_BUILTIN_PCMPEQQ256_MASK,
29710 IX86_BUILTIN_PCMPGTB128_MASK,
29711 IX86_BUILTIN_PCMPGTB256_MASK,
29712 IX86_BUILTIN_PCMPGTW128_MASK,
29713 IX86_BUILTIN_PCMPGTW256_MASK,
29714 IX86_BUILTIN_PCMPGTD128_MASK,
29715 IX86_BUILTIN_PCMPGTD256_MASK,
29716 IX86_BUILTIN_PCMPGTQ128_MASK,
29717 IX86_BUILTIN_PCMPGTQ256_MASK,
29718 IX86_BUILTIN_PTESTMB128,
29719 IX86_BUILTIN_PTESTMB256,
29720 IX86_BUILTIN_PTESTMW128,
29721 IX86_BUILTIN_PTESTMW256,
29722 IX86_BUILTIN_PTESTMD128,
29723 IX86_BUILTIN_PTESTMD256,
29724 IX86_BUILTIN_PTESTMQ128,
29725 IX86_BUILTIN_PTESTMQ256,
29726 IX86_BUILTIN_PTESTNMB128,
29727 IX86_BUILTIN_PTESTNMB256,
29728 IX86_BUILTIN_PTESTNMW128,
29729 IX86_BUILTIN_PTESTNMW256,
29730 IX86_BUILTIN_PTESTNMD128,
29731 IX86_BUILTIN_PTESTNMD256,
29732 IX86_BUILTIN_PTESTNMQ128,
29733 IX86_BUILTIN_PTESTNMQ256,
29734 IX86_BUILTIN_PBROADCASTMB128,
29735 IX86_BUILTIN_PBROADCASTMB256,
29736 IX86_BUILTIN_PBROADCASTMW128,
29737 IX86_BUILTIN_PBROADCASTMW256,
29738 IX86_BUILTIN_COMPRESSPD256,
29739 IX86_BUILTIN_COMPRESSPD128,
29740 IX86_BUILTIN_COMPRESSPS256,
29741 IX86_BUILTIN_COMPRESSPS128,
29742 IX86_BUILTIN_PCOMPRESSQ256,
29743 IX86_BUILTIN_PCOMPRESSQ128,
29744 IX86_BUILTIN_PCOMPRESSD256,
29745 IX86_BUILTIN_PCOMPRESSD128,
29746 IX86_BUILTIN_EXPANDPD256,
29747 IX86_BUILTIN_EXPANDPD128,
29748 IX86_BUILTIN_EXPANDPS256,
29749 IX86_BUILTIN_EXPANDPS128,
29750 IX86_BUILTIN_PEXPANDQ256,
29751 IX86_BUILTIN_PEXPANDQ128,
29752 IX86_BUILTIN_PEXPANDD256,
29753 IX86_BUILTIN_PEXPANDD128,
29754 IX86_BUILTIN_EXPANDPD256Z,
29755 IX86_BUILTIN_EXPANDPD128Z,
29756 IX86_BUILTIN_EXPANDPS256Z,
29757 IX86_BUILTIN_EXPANDPS128Z,
29758 IX86_BUILTIN_PEXPANDQ256Z,
29759 IX86_BUILTIN_PEXPANDQ128Z,
29760 IX86_BUILTIN_PEXPANDD256Z,
29761 IX86_BUILTIN_PEXPANDD128Z,
29762 IX86_BUILTIN_PMAXSD256_MASK,
29763 IX86_BUILTIN_PMINSD256_MASK,
29764 IX86_BUILTIN_PMAXUD256_MASK,
29765 IX86_BUILTIN_PMINUD256_MASK,
29766 IX86_BUILTIN_PMAXSD128_MASK,
29767 IX86_BUILTIN_PMINSD128_MASK,
29768 IX86_BUILTIN_PMAXUD128_MASK,
29769 IX86_BUILTIN_PMINUD128_MASK,
29770 IX86_BUILTIN_PMAXSQ256_MASK,
29771 IX86_BUILTIN_PMINSQ256_MASK,
29772 IX86_BUILTIN_PMAXUQ256_MASK,
29773 IX86_BUILTIN_PMINUQ256_MASK,
29774 IX86_BUILTIN_PMAXSQ128_MASK,
29775 IX86_BUILTIN_PMINSQ128_MASK,
29776 IX86_BUILTIN_PMAXUQ128_MASK,
29777 IX86_BUILTIN_PMINUQ128_MASK,
29778 IX86_BUILTIN_PMINSB256_MASK,
29779 IX86_BUILTIN_PMINUB256_MASK,
29780 IX86_BUILTIN_PMAXSB256_MASK,
29781 IX86_BUILTIN_PMAXUB256_MASK,
29782 IX86_BUILTIN_PMINSB128_MASK,
29783 IX86_BUILTIN_PMINUB128_MASK,
29784 IX86_BUILTIN_PMAXSB128_MASK,
29785 IX86_BUILTIN_PMAXUB128_MASK,
29786 IX86_BUILTIN_PMINSW256_MASK,
29787 IX86_BUILTIN_PMINUW256_MASK,
29788 IX86_BUILTIN_PMAXSW256_MASK,
29789 IX86_BUILTIN_PMAXUW256_MASK,
29790 IX86_BUILTIN_PMINSW128_MASK,
29791 IX86_BUILTIN_PMINUW128_MASK,
29792 IX86_BUILTIN_PMAXSW128_MASK,
29793 IX86_BUILTIN_PMAXUW128_MASK,
29794 IX86_BUILTIN_VPCONFLICTQ256,
29795 IX86_BUILTIN_VPCONFLICTD256,
29796 IX86_BUILTIN_VPCLZCNTQ256,
29797 IX86_BUILTIN_VPCLZCNTD256,
29798 IX86_BUILTIN_UNPCKHPD256_MASK,
29799 IX86_BUILTIN_UNPCKHPD128_MASK,
29800 IX86_BUILTIN_UNPCKHPS256_MASK,
29801 IX86_BUILTIN_UNPCKHPS128_MASK,
29802 IX86_BUILTIN_UNPCKLPD256_MASK,
29803 IX86_BUILTIN_UNPCKLPD128_MASK,
29804 IX86_BUILTIN_UNPCKLPS256_MASK,
29805 IX86_BUILTIN_VPCONFLICTQ128,
29806 IX86_BUILTIN_VPCONFLICTD128,
29807 IX86_BUILTIN_VPCLZCNTQ128,
29808 IX86_BUILTIN_VPCLZCNTD128,
29809 IX86_BUILTIN_UNPCKLPS128_MASK,
29810 IX86_BUILTIN_ALIGND256,
29811 IX86_BUILTIN_ALIGNQ256,
29812 IX86_BUILTIN_ALIGND128,
29813 IX86_BUILTIN_ALIGNQ128,
29814 IX86_BUILTIN_CVTPS2PH256_MASK,
29815 IX86_BUILTIN_CVTPS2PH_MASK,
29816 IX86_BUILTIN_CVTPH2PS_MASK,
29817 IX86_BUILTIN_CVTPH2PS256_MASK,
29818 IX86_BUILTIN_PUNPCKHDQ128_MASK,
29819 IX86_BUILTIN_PUNPCKHDQ256_MASK,
29820 IX86_BUILTIN_PUNPCKHQDQ128_MASK,
29821 IX86_BUILTIN_PUNPCKHQDQ256_MASK,
29822 IX86_BUILTIN_PUNPCKLDQ128_MASK,
29823 IX86_BUILTIN_PUNPCKLDQ256_MASK,
29824 IX86_BUILTIN_PUNPCKLQDQ128_MASK,
29825 IX86_BUILTIN_PUNPCKLQDQ256_MASK,
29826 IX86_BUILTIN_PUNPCKHBW128_MASK,
29827 IX86_BUILTIN_PUNPCKHBW256_MASK,
29828 IX86_BUILTIN_PUNPCKHWD128_MASK,
29829 IX86_BUILTIN_PUNPCKHWD256_MASK,
29830 IX86_BUILTIN_PUNPCKLBW128_MASK,
29831 IX86_BUILTIN_PUNPCKLBW256_MASK,
29832 IX86_BUILTIN_PUNPCKLWD128_MASK,
29833 IX86_BUILTIN_PUNPCKLWD256_MASK,
29834 IX86_BUILTIN_PSLLVV16HI,
29835 IX86_BUILTIN_PSLLVV8HI,
29836 IX86_BUILTIN_PACKSSDW256_MASK,
29837 IX86_BUILTIN_PACKSSDW128_MASK,
29838 IX86_BUILTIN_PACKUSDW256_MASK,
29839 IX86_BUILTIN_PACKUSDW128_MASK,
29840 IX86_BUILTIN_PAVGB256_MASK,
29841 IX86_BUILTIN_PAVGW256_MASK,
29842 IX86_BUILTIN_PAVGB128_MASK,
29843 IX86_BUILTIN_PAVGW128_MASK,
29844 IX86_BUILTIN_VPERMVARSF256_MASK,
29845 IX86_BUILTIN_VPERMVARDF256_MASK,
29846 IX86_BUILTIN_VPERMDF256_MASK,
29847 IX86_BUILTIN_PABSB256_MASK,
29848 IX86_BUILTIN_PABSB128_MASK,
29849 IX86_BUILTIN_PABSW256_MASK,
29850 IX86_BUILTIN_PABSW128_MASK,
29851 IX86_BUILTIN_VPERMILVARPD_MASK,
29852 IX86_BUILTIN_VPERMILVARPS_MASK,
29853 IX86_BUILTIN_VPERMILVARPD256_MASK,
29854 IX86_BUILTIN_VPERMILVARPS256_MASK,
29855 IX86_BUILTIN_VPERMILPD_MASK,
29856 IX86_BUILTIN_VPERMILPS_MASK,
29857 IX86_BUILTIN_VPERMILPD256_MASK,
29858 IX86_BUILTIN_VPERMILPS256_MASK,
29859 IX86_BUILTIN_BLENDMQ256,
29860 IX86_BUILTIN_BLENDMD256,
29861 IX86_BUILTIN_BLENDMPD256,
29862 IX86_BUILTIN_BLENDMPS256,
29863 IX86_BUILTIN_BLENDMQ128,
29864 IX86_BUILTIN_BLENDMD128,
29865 IX86_BUILTIN_BLENDMPD128,
29866 IX86_BUILTIN_BLENDMPS128,
29867 IX86_BUILTIN_BLENDMW256,
29868 IX86_BUILTIN_BLENDMB256,
29869 IX86_BUILTIN_BLENDMW128,
29870 IX86_BUILTIN_BLENDMB128,
29871 IX86_BUILTIN_PMULLD256_MASK,
29872 IX86_BUILTIN_PMULLD128_MASK,
29873 IX86_BUILTIN_PMULUDQ256_MASK,
29874 IX86_BUILTIN_PMULDQ256_MASK,
29875 IX86_BUILTIN_PMULDQ128_MASK,
29876 IX86_BUILTIN_PMULUDQ128_MASK,
29877 IX86_BUILTIN_CVTPD2PS256_MASK,
29878 IX86_BUILTIN_CVTPD2PS_MASK,
29879 IX86_BUILTIN_VPERMVARSI256_MASK,
29880 IX86_BUILTIN_VPERMVARDI256_MASK,
29881 IX86_BUILTIN_VPERMDI256_MASK,
29882 IX86_BUILTIN_CMPQ256,
29883 IX86_BUILTIN_CMPD256,
29884 IX86_BUILTIN_UCMPQ256,
29885 IX86_BUILTIN_UCMPD256,
29886 IX86_BUILTIN_CMPB256,
29887 IX86_BUILTIN_CMPW256,
29888 IX86_BUILTIN_UCMPB256,
29889 IX86_BUILTIN_UCMPW256,
29890 IX86_BUILTIN_CMPPD256_MASK,
29891 IX86_BUILTIN_CMPPS256_MASK,
29892 IX86_BUILTIN_CMPQ128,
29893 IX86_BUILTIN_CMPD128,
29894 IX86_BUILTIN_UCMPQ128,
29895 IX86_BUILTIN_UCMPD128,
29896 IX86_BUILTIN_CMPB128,
29897 IX86_BUILTIN_CMPW128,
29898 IX86_BUILTIN_UCMPB128,
29899 IX86_BUILTIN_UCMPW128,
29900 IX86_BUILTIN_CMPPD128_MASK,
29901 IX86_BUILTIN_CMPPS128_MASK,
29903 IX86_BUILTIN_GATHER3SIV8SF,
29904 IX86_BUILTIN_GATHER3SIV4SF,
29905 IX86_BUILTIN_GATHER3SIV4DF,
29906 IX86_BUILTIN_GATHER3SIV2DF,
29907 IX86_BUILTIN_GATHER3DIV8SF,
29908 IX86_BUILTIN_GATHER3DIV4SF,
29909 IX86_BUILTIN_GATHER3DIV4DF,
29910 IX86_BUILTIN_GATHER3DIV2DF,
29911 IX86_BUILTIN_GATHER3SIV8SI,
29912 IX86_BUILTIN_GATHER3SIV4SI,
29913 IX86_BUILTIN_GATHER3SIV4DI,
29914 IX86_BUILTIN_GATHER3SIV2DI,
29915 IX86_BUILTIN_GATHER3DIV8SI,
29916 IX86_BUILTIN_GATHER3DIV4SI,
29917 IX86_BUILTIN_GATHER3DIV4DI,
29918 IX86_BUILTIN_GATHER3DIV2DI,
29919 IX86_BUILTIN_SCATTERSIV8SF,
29920 IX86_BUILTIN_SCATTERSIV4SF,
29921 IX86_BUILTIN_SCATTERSIV4DF,
29922 IX86_BUILTIN_SCATTERSIV2DF,
29923 IX86_BUILTIN_SCATTERDIV8SF,
29924 IX86_BUILTIN_SCATTERDIV4SF,
29925 IX86_BUILTIN_SCATTERDIV4DF,
29926 IX86_BUILTIN_SCATTERDIV2DF,
29927 IX86_BUILTIN_SCATTERSIV8SI,
29928 IX86_BUILTIN_SCATTERSIV4SI,
29929 IX86_BUILTIN_SCATTERSIV4DI,
29930 IX86_BUILTIN_SCATTERSIV2DI,
29931 IX86_BUILTIN_SCATTERDIV8SI,
29932 IX86_BUILTIN_SCATTERDIV4SI,
29933 IX86_BUILTIN_SCATTERDIV4DI,
29934 IX86_BUILTIN_SCATTERDIV2DI,
29936 /* AVX512DQ. */
29937 IX86_BUILTIN_RANGESD128,
29938 IX86_BUILTIN_RANGESS128,
29939 IX86_BUILTIN_KUNPCKWD,
29940 IX86_BUILTIN_KUNPCKDQ,
29941 IX86_BUILTIN_BROADCASTF32x2_512,
29942 IX86_BUILTIN_BROADCASTI32x2_512,
29943 IX86_BUILTIN_BROADCASTF64X2_512,
29944 IX86_BUILTIN_BROADCASTI64X2_512,
29945 IX86_BUILTIN_BROADCASTF32X8_512,
29946 IX86_BUILTIN_BROADCASTI32X8_512,
29947 IX86_BUILTIN_EXTRACTF64X2_512,
29948 IX86_BUILTIN_EXTRACTF32X8,
29949 IX86_BUILTIN_EXTRACTI64X2_512,
29950 IX86_BUILTIN_EXTRACTI32X8,
29951 IX86_BUILTIN_REDUCEPD512_MASK,
29952 IX86_BUILTIN_REDUCEPS512_MASK,
29953 IX86_BUILTIN_PMULLQ512,
29954 IX86_BUILTIN_XORPD512,
29955 IX86_BUILTIN_XORPS512,
29956 IX86_BUILTIN_ORPD512,
29957 IX86_BUILTIN_ORPS512,
29958 IX86_BUILTIN_ANDPD512,
29959 IX86_BUILTIN_ANDPS512,
29960 IX86_BUILTIN_ANDNPD512,
29961 IX86_BUILTIN_ANDNPS512,
29962 IX86_BUILTIN_INSERTF32X8,
29963 IX86_BUILTIN_INSERTI32X8,
29964 IX86_BUILTIN_INSERTF64X2_512,
29965 IX86_BUILTIN_INSERTI64X2_512,
29966 IX86_BUILTIN_FPCLASSPD512,
29967 IX86_BUILTIN_FPCLASSPS512,
29968 IX86_BUILTIN_CVTD2MASK512,
29969 IX86_BUILTIN_CVTQ2MASK512,
29970 IX86_BUILTIN_CVTMASK2D512,
29971 IX86_BUILTIN_CVTMASK2Q512,
29972 IX86_BUILTIN_CVTPD2QQ512,
29973 IX86_BUILTIN_CVTPS2QQ512,
29974 IX86_BUILTIN_CVTPD2UQQ512,
29975 IX86_BUILTIN_CVTPS2UQQ512,
29976 IX86_BUILTIN_CVTQQ2PS512,
29977 IX86_BUILTIN_CVTUQQ2PS512,
29978 IX86_BUILTIN_CVTQQ2PD512,
29979 IX86_BUILTIN_CVTUQQ2PD512,
29980 IX86_BUILTIN_CVTTPS2QQ512,
29981 IX86_BUILTIN_CVTTPS2UQQ512,
29982 IX86_BUILTIN_CVTTPD2QQ512,
29983 IX86_BUILTIN_CVTTPD2UQQ512,
29984 IX86_BUILTIN_RANGEPS512,
29985 IX86_BUILTIN_RANGEPD512,
29987 /* AVX512BW. */
29988 IX86_BUILTIN_PACKUSDW512,
29989 IX86_BUILTIN_PACKSSDW512,
29990 IX86_BUILTIN_LOADDQUHI512_MASK,
29991 IX86_BUILTIN_LOADDQUQI512_MASK,
29992 IX86_BUILTIN_PSLLDQ512,
29993 IX86_BUILTIN_PSRLDQ512,
29994 IX86_BUILTIN_STOREDQUHI512_MASK,
29995 IX86_BUILTIN_STOREDQUQI512_MASK,
29996 IX86_BUILTIN_PALIGNR512,
29997 IX86_BUILTIN_PALIGNR512_MASK,
29998 IX86_BUILTIN_MOVDQUHI512_MASK,
29999 IX86_BUILTIN_MOVDQUQI512_MASK,
30000 IX86_BUILTIN_PSADBW512,
30001 IX86_BUILTIN_DBPSADBW512,
30002 IX86_BUILTIN_PBROADCASTB512,
30003 IX86_BUILTIN_PBROADCASTB512_GPR,
30004 IX86_BUILTIN_PBROADCASTW512,
30005 IX86_BUILTIN_PBROADCASTW512_GPR,
30006 IX86_BUILTIN_PMOVSXBW512_MASK,
30007 IX86_BUILTIN_PMOVZXBW512_MASK,
30008 IX86_BUILTIN_VPERMVARHI512_MASK,
30009 IX86_BUILTIN_VPERMT2VARHI512,
30010 IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
30011 IX86_BUILTIN_VPERMI2VARHI512,
30012 IX86_BUILTIN_PAVGB512,
30013 IX86_BUILTIN_PAVGW512,
30014 IX86_BUILTIN_PADDB512,
30015 IX86_BUILTIN_PSUBB512,
30016 IX86_BUILTIN_PSUBSB512,
30017 IX86_BUILTIN_PADDSB512,
30018 IX86_BUILTIN_PSUBUSB512,
30019 IX86_BUILTIN_PADDUSB512,
30020 IX86_BUILTIN_PSUBW512,
30021 IX86_BUILTIN_PADDW512,
30022 IX86_BUILTIN_PSUBSW512,
30023 IX86_BUILTIN_PADDSW512,
30024 IX86_BUILTIN_PSUBUSW512,
30025 IX86_BUILTIN_PADDUSW512,
30026 IX86_BUILTIN_PMAXUW512,
30027 IX86_BUILTIN_PMAXSW512,
30028 IX86_BUILTIN_PMINUW512,
30029 IX86_BUILTIN_PMINSW512,
30030 IX86_BUILTIN_PMAXUB512,
30031 IX86_BUILTIN_PMAXSB512,
30032 IX86_BUILTIN_PMINUB512,
30033 IX86_BUILTIN_PMINSB512,
30034 IX86_BUILTIN_PMOVWB512,
30035 IX86_BUILTIN_PMOVSWB512,
30036 IX86_BUILTIN_PMOVUSWB512,
30037 IX86_BUILTIN_PMULHRSW512_MASK,
30038 IX86_BUILTIN_PMULHUW512_MASK,
30039 IX86_BUILTIN_PMULHW512_MASK,
30040 IX86_BUILTIN_PMULLW512_MASK,
30041 IX86_BUILTIN_PSLLWI512_MASK,
30042 IX86_BUILTIN_PSLLW512_MASK,
30043 IX86_BUILTIN_PACKSSWB512,
30044 IX86_BUILTIN_PACKUSWB512,
30045 IX86_BUILTIN_PSRAVV32HI,
30046 IX86_BUILTIN_PMADDUBSW512_MASK,
30047 IX86_BUILTIN_PMADDWD512_MASK,
30048 IX86_BUILTIN_PSRLVV32HI,
30049 IX86_BUILTIN_PUNPCKHBW512,
30050 IX86_BUILTIN_PUNPCKHWD512,
30051 IX86_BUILTIN_PUNPCKLBW512,
30052 IX86_BUILTIN_PUNPCKLWD512,
30053 IX86_BUILTIN_PSHUFB512,
30054 IX86_BUILTIN_PSHUFHW512,
30055 IX86_BUILTIN_PSHUFLW512,
30056 IX86_BUILTIN_PSRAWI512,
30057 IX86_BUILTIN_PSRAW512,
30058 IX86_BUILTIN_PSRLWI512,
30059 IX86_BUILTIN_PSRLW512,
30060 IX86_BUILTIN_CVTB2MASK512,
30061 IX86_BUILTIN_CVTW2MASK512,
30062 IX86_BUILTIN_CVTMASK2B512,
30063 IX86_BUILTIN_CVTMASK2W512,
30064 IX86_BUILTIN_PCMPEQB512_MASK,
30065 IX86_BUILTIN_PCMPEQW512_MASK,
30066 IX86_BUILTIN_PCMPGTB512_MASK,
30067 IX86_BUILTIN_PCMPGTW512_MASK,
30068 IX86_BUILTIN_PTESTMB512,
30069 IX86_BUILTIN_PTESTMW512,
30070 IX86_BUILTIN_PTESTNMB512,
30071 IX86_BUILTIN_PTESTNMW512,
30072 IX86_BUILTIN_PSLLVV32HI,
30073 IX86_BUILTIN_PABSB512,
30074 IX86_BUILTIN_PABSW512,
30075 IX86_BUILTIN_BLENDMW512,
30076 IX86_BUILTIN_BLENDMB512,
30077 IX86_BUILTIN_CMPB512,
30078 IX86_BUILTIN_CMPW512,
30079 IX86_BUILTIN_UCMPB512,
30080 IX86_BUILTIN_UCMPW512,
30082 /* Alternate 4 and 8 element gather/scatter for the vectorizer
30083 where all operands are 32-byte or 64-byte wide respectively. */
30084 IX86_BUILTIN_GATHERALTSIV4DF,
30085 IX86_BUILTIN_GATHERALTDIV8SF,
30086 IX86_BUILTIN_GATHERALTSIV4DI,
30087 IX86_BUILTIN_GATHERALTDIV8SI,
30088 IX86_BUILTIN_GATHER3ALTDIV16SF,
30089 IX86_BUILTIN_GATHER3ALTDIV16SI,
30090 IX86_BUILTIN_GATHER3ALTSIV4DF,
30091 IX86_BUILTIN_GATHER3ALTDIV8SF,
30092 IX86_BUILTIN_GATHER3ALTSIV4DI,
30093 IX86_BUILTIN_GATHER3ALTDIV8SI,
30094 IX86_BUILTIN_GATHER3ALTSIV8DF,
30095 IX86_BUILTIN_GATHER3ALTSIV8DI,
30096 IX86_BUILTIN_GATHER3DIV16SF,
30097 IX86_BUILTIN_GATHER3DIV16SI,
30098 IX86_BUILTIN_GATHER3DIV8DF,
30099 IX86_BUILTIN_GATHER3DIV8DI,
30100 IX86_BUILTIN_GATHER3SIV16SF,
30101 IX86_BUILTIN_GATHER3SIV16SI,
30102 IX86_BUILTIN_GATHER3SIV8DF,
30103 IX86_BUILTIN_GATHER3SIV8DI,
30104 IX86_BUILTIN_SCATTERDIV16SF,
30105 IX86_BUILTIN_SCATTERDIV16SI,
30106 IX86_BUILTIN_SCATTERDIV8DF,
30107 IX86_BUILTIN_SCATTERDIV8DI,
30108 IX86_BUILTIN_SCATTERSIV16SF,
30109 IX86_BUILTIN_SCATTERSIV16SI,
30110 IX86_BUILTIN_SCATTERSIV8DF,
30111 IX86_BUILTIN_SCATTERSIV8DI,
30113 /* AVX512PF */
30114 IX86_BUILTIN_GATHERPFQPD,
30115 IX86_BUILTIN_GATHERPFDPS,
30116 IX86_BUILTIN_GATHERPFDPD,
30117 IX86_BUILTIN_GATHERPFQPS,
30118 IX86_BUILTIN_SCATTERPFDPD,
30119 IX86_BUILTIN_SCATTERPFDPS,
30120 IX86_BUILTIN_SCATTERPFQPD,
30121 IX86_BUILTIN_SCATTERPFQPS,
30123 /* AVX-512ER */
30124 IX86_BUILTIN_EXP2PD_MASK,
30125 IX86_BUILTIN_EXP2PS_MASK,
30126 IX86_BUILTIN_EXP2PS,
30127 IX86_BUILTIN_RCP28PD,
30128 IX86_BUILTIN_RCP28PS,
30129 IX86_BUILTIN_RCP28SD,
30130 IX86_BUILTIN_RCP28SS,
30131 IX86_BUILTIN_RSQRT28PD,
30132 IX86_BUILTIN_RSQRT28PS,
30133 IX86_BUILTIN_RSQRT28SD,
30134 IX86_BUILTIN_RSQRT28SS,
30136 /* AVX-512IFMA */
30137 IX86_BUILTIN_VPMADD52LUQ512,
30138 IX86_BUILTIN_VPMADD52HUQ512,
30139 IX86_BUILTIN_VPMADD52LUQ256,
30140 IX86_BUILTIN_VPMADD52HUQ256,
30141 IX86_BUILTIN_VPMADD52LUQ128,
30142 IX86_BUILTIN_VPMADD52HUQ128,
30143 IX86_BUILTIN_VPMADD52LUQ512_MASKZ,
30144 IX86_BUILTIN_VPMADD52HUQ512_MASKZ,
30145 IX86_BUILTIN_VPMADD52LUQ256_MASKZ,
30146 IX86_BUILTIN_VPMADD52HUQ256_MASKZ,
30147 IX86_BUILTIN_VPMADD52LUQ128_MASKZ,
30148 IX86_BUILTIN_VPMADD52HUQ128_MASKZ,
30150 /* AVX-512VBMI */
30151 IX86_BUILTIN_VPMULTISHIFTQB512,
30152 IX86_BUILTIN_VPMULTISHIFTQB256,
30153 IX86_BUILTIN_VPMULTISHIFTQB128,
30154 IX86_BUILTIN_VPERMVARQI512_MASK,
30155 IX86_BUILTIN_VPERMT2VARQI512,
30156 IX86_BUILTIN_VPERMT2VARQI512_MASKZ,
30157 IX86_BUILTIN_VPERMI2VARQI512,
30158 IX86_BUILTIN_VPERMVARQI256_MASK,
30159 IX86_BUILTIN_VPERMVARQI128_MASK,
30160 IX86_BUILTIN_VPERMT2VARQI256,
30161 IX86_BUILTIN_VPERMT2VARQI256_MASKZ,
30162 IX86_BUILTIN_VPERMT2VARQI128,
30163 IX86_BUILTIN_VPERMT2VARQI128_MASKZ,
30164 IX86_BUILTIN_VPERMI2VARQI256,
30165 IX86_BUILTIN_VPERMI2VARQI128,
30167 /* SHA builtins. */
30168 IX86_BUILTIN_SHA1MSG1,
30169 IX86_BUILTIN_SHA1MSG2,
30170 IX86_BUILTIN_SHA1NEXTE,
30171 IX86_BUILTIN_SHA1RNDS4,
30172 IX86_BUILTIN_SHA256MSG1,
30173 IX86_BUILTIN_SHA256MSG2,
30174 IX86_BUILTIN_SHA256RNDS2,
30176 /* CLWB instructions. */
30177 IX86_BUILTIN_CLWB,
30179 /* PCOMMIT instructions. */
30180 IX86_BUILTIN_PCOMMIT,
30182 /* CLFLUSHOPT instructions. */
30183 IX86_BUILTIN_CLFLUSHOPT,
30185 /* TFmode support builtins. */
30186 IX86_BUILTIN_INFQ,
30187 IX86_BUILTIN_HUGE_VALQ,
30188 IX86_BUILTIN_FABSQ,
30189 IX86_BUILTIN_COPYSIGNQ,
30191 /* Vectorizer support builtins. */
30192 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
30193 IX86_BUILTIN_CPYSGNPS,
30194 IX86_BUILTIN_CPYSGNPD,
30195 IX86_BUILTIN_CPYSGNPS256,
30196 IX86_BUILTIN_CPYSGNPS512,
30197 IX86_BUILTIN_CPYSGNPD256,
30198 IX86_BUILTIN_CPYSGNPD512,
30199 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
30200 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
30203 /* FMA4 instructions. */
30204 IX86_BUILTIN_VFMADDSS,
30205 IX86_BUILTIN_VFMADDSD,
30206 IX86_BUILTIN_VFMADDPS,
30207 IX86_BUILTIN_VFMADDPD,
30208 IX86_BUILTIN_VFMADDPS256,
30209 IX86_BUILTIN_VFMADDPD256,
30210 IX86_BUILTIN_VFMADDSUBPS,
30211 IX86_BUILTIN_VFMADDSUBPD,
30212 IX86_BUILTIN_VFMADDSUBPS256,
30213 IX86_BUILTIN_VFMADDSUBPD256,
30215 /* FMA3 instructions. */
30216 IX86_BUILTIN_VFMADDSS3,
30217 IX86_BUILTIN_VFMADDSD3,
30219 /* XOP instructions. */
30220 IX86_BUILTIN_VPCMOV,
30221 IX86_BUILTIN_VPCMOV_V2DI,
30222 IX86_BUILTIN_VPCMOV_V4SI,
30223 IX86_BUILTIN_VPCMOV_V8HI,
30224 IX86_BUILTIN_VPCMOV_V16QI,
30225 IX86_BUILTIN_VPCMOV_V4SF,
30226 IX86_BUILTIN_VPCMOV_V2DF,
30227 IX86_BUILTIN_VPCMOV256,
30228 IX86_BUILTIN_VPCMOV_V4DI256,
30229 IX86_BUILTIN_VPCMOV_V8SI256,
30230 IX86_BUILTIN_VPCMOV_V16HI256,
30231 IX86_BUILTIN_VPCMOV_V32QI256,
30232 IX86_BUILTIN_VPCMOV_V8SF256,
30233 IX86_BUILTIN_VPCMOV_V4DF256,
30235 IX86_BUILTIN_VPPERM,
30237 IX86_BUILTIN_VPMACSSWW,
30238 IX86_BUILTIN_VPMACSWW,
30239 IX86_BUILTIN_VPMACSSWD,
30240 IX86_BUILTIN_VPMACSWD,
30241 IX86_BUILTIN_VPMACSSDD,
30242 IX86_BUILTIN_VPMACSDD,
30243 IX86_BUILTIN_VPMACSSDQL,
30244 IX86_BUILTIN_VPMACSSDQH,
30245 IX86_BUILTIN_VPMACSDQL,
30246 IX86_BUILTIN_VPMACSDQH,
30247 IX86_BUILTIN_VPMADCSSWD,
30248 IX86_BUILTIN_VPMADCSWD,
30250 IX86_BUILTIN_VPHADDBW,
30251 IX86_BUILTIN_VPHADDBD,
30252 IX86_BUILTIN_VPHADDBQ,
30253 IX86_BUILTIN_VPHADDWD,
30254 IX86_BUILTIN_VPHADDWQ,
30255 IX86_BUILTIN_VPHADDDQ,
30256 IX86_BUILTIN_VPHADDUBW,
30257 IX86_BUILTIN_VPHADDUBD,
30258 IX86_BUILTIN_VPHADDUBQ,
30259 IX86_BUILTIN_VPHADDUWD,
30260 IX86_BUILTIN_VPHADDUWQ,
30261 IX86_BUILTIN_VPHADDUDQ,
30262 IX86_BUILTIN_VPHSUBBW,
30263 IX86_BUILTIN_VPHSUBWD,
30264 IX86_BUILTIN_VPHSUBDQ,
30266 IX86_BUILTIN_VPROTB,
30267 IX86_BUILTIN_VPROTW,
30268 IX86_BUILTIN_VPROTD,
30269 IX86_BUILTIN_VPROTQ,
30270 IX86_BUILTIN_VPROTB_IMM,
30271 IX86_BUILTIN_VPROTW_IMM,
30272 IX86_BUILTIN_VPROTD_IMM,
30273 IX86_BUILTIN_VPROTQ_IMM,
30275 IX86_BUILTIN_VPSHLB,
30276 IX86_BUILTIN_VPSHLW,
30277 IX86_BUILTIN_VPSHLD,
30278 IX86_BUILTIN_VPSHLQ,
30279 IX86_BUILTIN_VPSHAB,
30280 IX86_BUILTIN_VPSHAW,
30281 IX86_BUILTIN_VPSHAD,
30282 IX86_BUILTIN_VPSHAQ,
30284 IX86_BUILTIN_VFRCZSS,
30285 IX86_BUILTIN_VFRCZSD,
30286 IX86_BUILTIN_VFRCZPS,
30287 IX86_BUILTIN_VFRCZPD,
30288 IX86_BUILTIN_VFRCZPS256,
30289 IX86_BUILTIN_VFRCZPD256,
30291 IX86_BUILTIN_VPCOMEQUB,
30292 IX86_BUILTIN_VPCOMNEUB,
30293 IX86_BUILTIN_VPCOMLTUB,
30294 IX86_BUILTIN_VPCOMLEUB,
30295 IX86_BUILTIN_VPCOMGTUB,
30296 IX86_BUILTIN_VPCOMGEUB,
30297 IX86_BUILTIN_VPCOMFALSEUB,
30298 IX86_BUILTIN_VPCOMTRUEUB,
30300 IX86_BUILTIN_VPCOMEQUW,
30301 IX86_BUILTIN_VPCOMNEUW,
30302 IX86_BUILTIN_VPCOMLTUW,
30303 IX86_BUILTIN_VPCOMLEUW,
30304 IX86_BUILTIN_VPCOMGTUW,
30305 IX86_BUILTIN_VPCOMGEUW,
30306 IX86_BUILTIN_VPCOMFALSEUW,
30307 IX86_BUILTIN_VPCOMTRUEUW,
30309 IX86_BUILTIN_VPCOMEQUD,
30310 IX86_BUILTIN_VPCOMNEUD,
30311 IX86_BUILTIN_VPCOMLTUD,
30312 IX86_BUILTIN_VPCOMLEUD,
30313 IX86_BUILTIN_VPCOMGTUD,
30314 IX86_BUILTIN_VPCOMGEUD,
30315 IX86_BUILTIN_VPCOMFALSEUD,
30316 IX86_BUILTIN_VPCOMTRUEUD,
30318 IX86_BUILTIN_VPCOMEQUQ,
30319 IX86_BUILTIN_VPCOMNEUQ,
30320 IX86_BUILTIN_VPCOMLTUQ,
30321 IX86_BUILTIN_VPCOMLEUQ,
30322 IX86_BUILTIN_VPCOMGTUQ,
30323 IX86_BUILTIN_VPCOMGEUQ,
30324 IX86_BUILTIN_VPCOMFALSEUQ,
30325 IX86_BUILTIN_VPCOMTRUEUQ,
30327 IX86_BUILTIN_VPCOMEQB,
30328 IX86_BUILTIN_VPCOMNEB,
30329 IX86_BUILTIN_VPCOMLTB,
30330 IX86_BUILTIN_VPCOMLEB,
30331 IX86_BUILTIN_VPCOMGTB,
30332 IX86_BUILTIN_VPCOMGEB,
30333 IX86_BUILTIN_VPCOMFALSEB,
30334 IX86_BUILTIN_VPCOMTRUEB,
30336 IX86_BUILTIN_VPCOMEQW,
30337 IX86_BUILTIN_VPCOMNEW,
30338 IX86_BUILTIN_VPCOMLTW,
30339 IX86_BUILTIN_VPCOMLEW,
30340 IX86_BUILTIN_VPCOMGTW,
30341 IX86_BUILTIN_VPCOMGEW,
30342 IX86_BUILTIN_VPCOMFALSEW,
30343 IX86_BUILTIN_VPCOMTRUEW,
30345 IX86_BUILTIN_VPCOMEQD,
30346 IX86_BUILTIN_VPCOMNED,
30347 IX86_BUILTIN_VPCOMLTD,
30348 IX86_BUILTIN_VPCOMLED,
30349 IX86_BUILTIN_VPCOMGTD,
30350 IX86_BUILTIN_VPCOMGED,
30351 IX86_BUILTIN_VPCOMFALSED,
30352 IX86_BUILTIN_VPCOMTRUED,
30354 IX86_BUILTIN_VPCOMEQQ,
30355 IX86_BUILTIN_VPCOMNEQ,
30356 IX86_BUILTIN_VPCOMLTQ,
30357 IX86_BUILTIN_VPCOMLEQ,
30358 IX86_BUILTIN_VPCOMGTQ,
30359 IX86_BUILTIN_VPCOMGEQ,
30360 IX86_BUILTIN_VPCOMFALSEQ,
30361 IX86_BUILTIN_VPCOMTRUEQ,
30363 /* LWP instructions. */
30364 IX86_BUILTIN_LLWPCB,
30365 IX86_BUILTIN_SLWPCB,
30366 IX86_BUILTIN_LWPVAL32,
30367 IX86_BUILTIN_LWPVAL64,
30368 IX86_BUILTIN_LWPINS32,
30369 IX86_BUILTIN_LWPINS64,
30371 IX86_BUILTIN_CLZS,
30373 /* RTM */
30374 IX86_BUILTIN_XBEGIN,
30375 IX86_BUILTIN_XEND,
30376 IX86_BUILTIN_XABORT,
30377 IX86_BUILTIN_XTEST,
30379 /* MPX */
30380 IX86_BUILTIN_BNDMK,
30381 IX86_BUILTIN_BNDSTX,
30382 IX86_BUILTIN_BNDLDX,
30383 IX86_BUILTIN_BNDCL,
30384 IX86_BUILTIN_BNDCU,
30385 IX86_BUILTIN_BNDRET,
30386 IX86_BUILTIN_BNDNARROW,
30387 IX86_BUILTIN_BNDINT,
30388 IX86_BUILTIN_SIZEOF,
30389 IX86_BUILTIN_BNDLOWER,
30390 IX86_BUILTIN_BNDUPPER,
30392 /* BMI instructions. */
30393 IX86_BUILTIN_BEXTR32,
30394 IX86_BUILTIN_BEXTR64,
30395 IX86_BUILTIN_CTZS,
30397 /* TBM instructions. */
30398 IX86_BUILTIN_BEXTRI32,
30399 IX86_BUILTIN_BEXTRI64,
30401 /* BMI2 instructions. */
30402 IX86_BUILTIN_BZHI32,
30403 IX86_BUILTIN_BZHI64,
30404 IX86_BUILTIN_PDEP32,
30405 IX86_BUILTIN_PDEP64,
30406 IX86_BUILTIN_PEXT32,
30407 IX86_BUILTIN_PEXT64,
30409 /* ADX instructions. */
30410 IX86_BUILTIN_ADDCARRYX32,
30411 IX86_BUILTIN_ADDCARRYX64,
30413 /* SBB instructions. */
30414 IX86_BUILTIN_SBB32,
30415 IX86_BUILTIN_SBB64,
30417 /* FSGSBASE instructions. */
30418 IX86_BUILTIN_RDFSBASE32,
30419 IX86_BUILTIN_RDFSBASE64,
30420 IX86_BUILTIN_RDGSBASE32,
30421 IX86_BUILTIN_RDGSBASE64,
30422 IX86_BUILTIN_WRFSBASE32,
30423 IX86_BUILTIN_WRFSBASE64,
30424 IX86_BUILTIN_WRGSBASE32,
30425 IX86_BUILTIN_WRGSBASE64,
30427 /* RDRND instructions. */
30428 IX86_BUILTIN_RDRAND16_STEP,
30429 IX86_BUILTIN_RDRAND32_STEP,
30430 IX86_BUILTIN_RDRAND64_STEP,
30432 /* RDSEED instructions. */
30433 IX86_BUILTIN_RDSEED16_STEP,
30434 IX86_BUILTIN_RDSEED32_STEP,
30435 IX86_BUILTIN_RDSEED64_STEP,
30437 /* F16C instructions. */
30438 IX86_BUILTIN_CVTPH2PS,
30439 IX86_BUILTIN_CVTPH2PS256,
30440 IX86_BUILTIN_CVTPS2PH,
30441 IX86_BUILTIN_CVTPS2PH256,
30443 /* CFString built-in for darwin */
30444 IX86_BUILTIN_CFSTRING,
30446 /* Builtins to get CPU type and supported features. */
30447 IX86_BUILTIN_CPU_INIT,
30448 IX86_BUILTIN_CPU_IS,
30449 IX86_BUILTIN_CPU_SUPPORTS,
30451 /* Read/write FLAGS register built-ins. */
30452 IX86_BUILTIN_READ_FLAGS,
30453 IX86_BUILTIN_WRITE_FLAGS,
30455 IX86_BUILTIN_MAX
30456 };
30458 /* Table for the ix86 builtin decls. */
30461 /* Table of all of the builtin functions that are possible with different ISA's
30462 but are waiting to be built until a function is declared to use that
30463 ISA. */
30472 };
30477 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
30478 of which isa_flags to use in the ix86_builtins_isa array. Stores the
30479 function decl in the ix86_builtins array. Returns the function decl or
30480 NULL_TREE, if the builtin was not added.
30482 If the front end has a special hook for builtin functions, delay adding
30483 builtin functions that aren't in the current ISA until the ISA is changed
30484 with function specific optimization. Doing so, can save about 300K for the
30485 default compiler. When the builtin is expanded, check at that time whether
30486 it is valid.
30488 If the front end doesn't have a special hook, record all builtins, even if
30489 it isn't an instruction set in the current ISA in case the user uses
30490 function specific options for a different ISA, so that we don't get scope
30491 errors if a builtin is added in the middle of a function scope. */
30497 {
30501 {
30510 {
30516 }
30517 else
30518 {
30526 }
30527 }
30530 }
30532 /* Like def_builtin, but also marks the function decl "const". */
30537 {
30541 else
30545 }
30547 /* Add any new builtin functions for a given ISA that may not have been
30548 declared. This saves a bit of space compared to adding all of the
30549 declarations to the tree, even if we didn't use them. */
30551 static void
30553 {
30557 {
30560 {
30563 /* Don't define the builtin again. */
30569 NULL_TREE);
30576 NULL_TREE);
30579 }
30580 }
30581 }
30583 /* Bits for builtin_description.flag. */
30585 /* Set when we don't support the comparison natively, and should
30586 swap_comparison in order to support it. */
30587 #define BUILTIN_DESC_SWAP_OPERANDS 1
30589 struct builtin_description
30590 {
30597 };
30600 {
30601 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
30602 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
30603 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
30604 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
30605 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
30606 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
30607 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
30608 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
30609 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
30610 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
30611 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
30612 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
30613 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
30614 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
30615 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
30616 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
30617 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
30618 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
30619 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
30620 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
30621 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
30622 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
30623 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
30624 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
30625 };
30628 {
30629 /* SSE4.2 */
30630 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
30631 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
30632 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
30633 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
30634 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
30635 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
30636 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
30637 };
30640 {
30641 /* SSE4.2 */
30642 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
30643 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
30644 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
30645 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
30646 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
30647 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
30648 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
30649 };
30651 /* Special builtins with variable number of arguments. */
30653 {
30654 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
30655 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
30656 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
30658 /* 80387 (for use internally for atomic compound assignment). */
30659 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
30660 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
30661 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) USHORT_FTYPE_VOID },
30662 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
30664 /* MMX */
30665 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30667 /* 3DNow! */
30668 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30670 /* FXSR, XSAVE, XSAVEOPT, XSAVEC and XSAVES. */
30671 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
30672 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
30673 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30674 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30675 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30676 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xsaves", IX86_BUILTIN_XSAVES, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30677 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xrstors", IX86_BUILTIN_XRSTORS, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30678 { OPTION_MASK_ISA_XSAVEC, CODE_FOR_nothing, "__builtin_ia32_xsavec", IX86_BUILTIN_XSAVEC, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30680 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30681 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30682 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30683 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30684 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30685 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaves64", IX86_BUILTIN_XSAVES64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30686 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30687 { OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30689 /* SSE */
30690 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30691 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30692 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30694 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30695 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30696 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30697 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30699 /* SSE or 3DNow!A */
30700 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30701 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
30703 /* SSE2 */
30704 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30705 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30706 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30707 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
30708 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30709 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
30710 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
30711 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
30712 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
30713 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30715 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30716 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30718 /* SSE3 */
30719 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30721 /* SSE4.1 */
30722 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
30724 /* SSE4A */
30725 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30726 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30728 /* AVX */
30729 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
30730 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
30732 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30733 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30734 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30735 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
30736 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
30738 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30739 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30740 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30741 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30742 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30743 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
30744 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30746 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
30747 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30748 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30750 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
30751 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
30752 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
30753 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
30754 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
30755 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
30756 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
30757 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
30759 /* AVX2 */
30760 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
30761 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
30762 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
30763 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
30764 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
30765 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
30766 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
30767 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
30768 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
30770 /* AVX512F */
30771 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30772 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30773 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30774 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30775 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30776 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30777 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30778 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30779 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30780 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30781 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30782 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30783 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30784 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30785 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30786 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30787 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30788 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30789 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30790 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30791 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
30792 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
30793 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
30794 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
30795 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30796 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30797 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30798 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30799 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30800 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30801 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30802 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30803 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30804 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30805 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30806 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30807 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30808 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30809 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30810 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30811 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30812 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30813 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30814 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30815 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30816 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30817 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30819 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
30820 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
30821 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
30822 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
30823 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
30824 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
30826 /* FSGSBASE */
30827 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30828 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30829 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30830 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30831 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30832 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30833 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30834 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30836 /* RTM */
30837 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30838 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
30839 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
30841 /* AVX512BW */
30842 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_SI },
30843 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_DI },
30844 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_SI },
30845 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_DI },
30847 /* AVX512VL */
30848 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_HI },
30849 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_QI },
30850 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_SI },
30851 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_HI },
30852 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30853 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30854 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30855 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30856 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30857 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30858 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30859 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30860 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30861 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30862 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30863 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30864 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30865 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30866 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30867 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30868 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30869 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30870 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30871 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30872 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30873 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30874 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30875 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30876 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30877 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30878 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30879 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30880 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30881 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30882 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30883 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30884 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_HI },
30885 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_QI },
30886 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_SI },
30887 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_HI },
30888 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30889 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30890 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30891 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30892 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30893 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30894 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30895 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30896 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30897 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30898 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30899 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30900 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30901 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30902 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30903 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30904 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30905 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30906 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30907 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30908 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30909 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30910 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30911 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30912 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask_store, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30913 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask_store, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30914 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask_store, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30915 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask_store, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30916 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask_store, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30917 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask_store, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30918 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30919 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30920 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30921 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30922 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30923 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30924 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30925 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30926 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30927 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30928 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30929 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30930 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30931 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30932 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30933 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30934 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30935 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30936 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30937 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30938 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30939 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30940 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30941 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30943 /* PCOMMIT. */
30944 { OPTION_MASK_ISA_PCOMMIT, CODE_FOR_pcommit, "__builtin_ia32_pcommit", IX86_BUILTIN_PCOMMIT, UNKNOWN, (int) VOID_FTYPE_VOID },
30945 };
30947 /* Builtins with variable number of arguments. */
30949 {
30950 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
30951 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
30952 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
30953 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
30954 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
30955 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
30956 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
30958 /* MMX */
30959 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30960 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30961 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30962 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30963 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30964 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30966 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30967 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30968 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30969 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30970 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30971 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30972 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30973 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30975 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30976 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30978 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30979 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30980 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30981 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30983 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30984 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30985 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30986 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30987 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30988 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30990 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30991 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30992 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30993 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30994 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
30995 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
30997 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
30998 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
30999 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31001 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
31003 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31004 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31005 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31006 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31007 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31008 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31010 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31011 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31012 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31013 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31014 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31015 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31017 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31018 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31019 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31020 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31022 /* 3DNow! */
31023 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31024 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31025 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31026 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31028 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31029 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31030 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31031 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31032 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31033 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31034 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31035 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31036 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31037 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31038 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31039 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31040 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31041 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31042 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31044 /* 3DNow!A */
31045 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31046 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31047 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31048 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31049 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31050 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31052 /* SSE */
31053 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
31054 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31055 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31056 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31057 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31058 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31059 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31060 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31061 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31062 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31063 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31064 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31066 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31068 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31069 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31070 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31071 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31072 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31073 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31074 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31075 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31077 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31078 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31079 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31080 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31081 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31082 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31083 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31084 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31085 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31086 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31087 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
31088 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31089 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31090 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31091 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31092 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31093 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31094 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31095 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31096 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31098 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31099 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31100 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31101 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31103 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31104 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31105 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31106 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31108 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31110 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31111 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31112 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31113 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31114 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31116 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
31117 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
31118 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
31120 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
31122 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31123 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31124 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31126 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
31127 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
31129 /* SSE MMX or 3Dnow!A */
31130 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31131 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31132 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31134 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31135 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31136 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31137 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31139 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
31140 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
31142 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
31144 /* SSE2 */
31145 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31147 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
31148 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
31149 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31150 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
31151 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
31153 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31154 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31155 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
31156 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31157 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31159 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
31161 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31162 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31163 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31164 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31166 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31167 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
31168 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31170 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31171 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31172 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31173 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31174 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31175 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31176 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31177 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31179 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31180 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31181 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31182 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31183 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
31184 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31185 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31186 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31187 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31188 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31189 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31190 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31191 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31192 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31193 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31194 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31195 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31196 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31197 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31198 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31200 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31201 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31202 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31203 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31205 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31206 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31207 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31208 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31210 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31212 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31213 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31214 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31216 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31218 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31219 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31220 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31221 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31222 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31223 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31224 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31225 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31227 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31228 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31229 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31230 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31231 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31232 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31233 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31234 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31236 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31237 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
31239 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31240 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31241 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31242 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31244 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31245 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31247 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31248 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31249 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31250 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31251 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31252 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31254 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31255 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31256 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31257 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31259 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31260 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31261 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31262 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31263 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31264 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31265 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31266 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31268 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31269 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31270 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31272 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31273 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
31275 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
31276 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31278 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
31280 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
31281 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
31282 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
31283 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
31285 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31286 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31287 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31288 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31289 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31290 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31291 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31293 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31294 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31295 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31296 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31297 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31298 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31299 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31301 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31302 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31303 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31304 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31306 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
31307 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31308 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31310 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
31312 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31314 /* SSE2 MMX */
31315 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31316 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31318 /* SSE3 */
31319 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
31320 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31322 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31323 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31324 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31325 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31326 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31327 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31329 /* SSSE3 */
31330 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31331 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
31332 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31333 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
31334 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31335 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31337 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31338 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31339 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31340 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31341 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31342 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31343 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31344 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31345 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31346 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31347 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31348 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31349 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
31350 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
31351 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31352 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31353 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31354 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31355 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31356 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31357 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31358 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31359 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31360 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31362 /* SSSE3. */
31363 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
31364 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
31366 /* SSE4.1 */
31367 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31368 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31369 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
31370 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
31371 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31372 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31373 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31374 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
31375 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
31376 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
31378 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31379 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31380 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31381 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31382 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31383 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31384 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31385 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31386 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31387 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31388 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31389 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31390 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31392 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31393 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31394 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31395 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31396 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31397 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31398 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31399 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31400 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31401 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31402 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31403 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31405 /* SSE4.1 */
31406 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31407 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31408 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31409 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31411 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
31412 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
31413 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
31414 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
31416 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31417 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31419 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31420 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31422 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
31423 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
31424 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
31425 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
31427 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
31428 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
31430 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31431 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31433 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31434 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31435 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31437 /* SSE4.2 */
31438 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31439 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
31440 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
31441 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31442 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31444 /* SSE4A */
31445 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
31446 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
31447 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
31448 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31450 /* AES */
31451 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
31452 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31454 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31455 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31456 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31457 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31459 /* PCLMUL */
31460 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
31462 /* AVX */
31463 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31464 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31465 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31466 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31467 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31468 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31469 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31470 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31471 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31472 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31473 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31474 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31475 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31476 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31477 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31478 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31479 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31480 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31481 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31482 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31483 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31484 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31485 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31486 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31487 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31488 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31490 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
31491 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
31492 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
31493 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31495 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31496 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31497 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
31498 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
31499 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31500 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31501 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31502 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31503 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31504 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31505 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31506 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31507 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31508 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
31509 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
31510 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
31511 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
31512 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
31513 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
31514 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31515 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
31516 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31517 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31518 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31519 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31520 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31521 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31522 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31523 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31524 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31525 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31526 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
31527 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
31528 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
31530 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31531 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31532 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31534 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31535 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31536 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31537 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31538 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31540 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31542 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31543 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31545 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
31546 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
31547 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
31548 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
31550 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31551 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31553 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31554 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31556 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
31557 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
31558 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
31559 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
31561 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
31562 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
31564 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31565 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31567 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31568 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31569 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31570 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31572 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31573 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31574 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31575 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
31576 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
31577 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
31579 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31580 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31581 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31582 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31583 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31584 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31585 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31586 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31587 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31588 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31589 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31590 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31591 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31592 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31593 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31595 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
31596 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
31598 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31599 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31601 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31603 /* AVX2 */
31604 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
31605 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
31606 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
31607 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
31608 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31609 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31610 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31611 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31612 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31613 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31614 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31615 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31616 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31617 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31618 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31619 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31620 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
31621 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31622 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31623 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31624 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31625 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
31626 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
31627 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31628 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31629 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31630 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31631 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31632 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31633 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31634 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31635 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31636 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31637 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31638 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31639 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31640 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31641 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31642 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
31643 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31644 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31645 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31646 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31647 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31648 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31649 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31650 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31651 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31652 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31653 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31654 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31655 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
31656 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31657 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31658 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31659 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31660 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31661 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31662 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31663 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31664 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31665 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31666 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31667 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31668 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31669 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31670 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31671 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31672 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31673 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31674 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31675 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31676 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31677 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31678 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
31679 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31680 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31681 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31682 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31683 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31684 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31685 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31686 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31687 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31688 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31689 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31690 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31691 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31692 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31693 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31694 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31695 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31696 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31697 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31698 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31699 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31700 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31701 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31702 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31703 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31704 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31705 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31706 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31707 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31708 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31709 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31710 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31711 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31712 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31713 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31714 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31715 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31716 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31717 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31718 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31719 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31720 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31721 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31722 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31723 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
31724 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31725 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
31726 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
31727 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31728 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31729 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31730 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31731 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31732 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31733 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31734 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31735 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31736 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
31737 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
31738 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vextractf128v4di, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
31739 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vinsertf128v4di, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
31740 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31741 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31742 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31743 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31744 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31745 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31746 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31747 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31748 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31749 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31751 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31753 /* BMI */
31754 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31755 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31756 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31758 /* TBM */
31759 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31760 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31762 /* F16C */
31763 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
31764 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
31765 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
31766 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
31768 /* BMI2 */
31769 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31770 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31771 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31772 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31773 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31774 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31776 /* AVX512F */
31777 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_256si, "__builtin_ia32_si512_256si", IX86_BUILTIN_SI512_SI256, UNKNOWN, (int) V16SI_FTYPE_V8SI },
31778 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_256ps, "__builtin_ia32_ps512_256ps", IX86_BUILTIN_PS512_PS256, UNKNOWN, (int) V16SF_FTYPE_V8SF },
31779 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_256pd, "__builtin_ia32_pd512_256pd", IX86_BUILTIN_PD512_PD256, UNKNOWN, (int) V8DF_FTYPE_V4DF },
31780 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_si, "__builtin_ia32_si512_si", IX86_BUILTIN_SI512_SI, UNKNOWN, (int) V16SI_FTYPE_V4SI },
31781 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_ps, "__builtin_ia32_ps512_ps", IX86_BUILTIN_PS512_PS, UNKNOWN, (int) V16SF_FTYPE_V4SF },
31782 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_pd, "__builtin_ia32_pd512_pd", IX86_BUILTIN_PD512_PD, UNKNOWN, (int) V8DF_FTYPE_V2DF },
31783 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31784 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31785 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31786 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31787 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31788 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31789 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31790 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
31791 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31792 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
31793 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
31794 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31795 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31796 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31797 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31798 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31799 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31800 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
31801 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31802 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
31803 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31804 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31805 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31806 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31807 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
31808 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
31809 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
31810 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
31811 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
31812 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
31813 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
31814 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
31815 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31816 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31817 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31818 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31819 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31820 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31821 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31822 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31823 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31824 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31825 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31826 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31827 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31828 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31829 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31830 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31831 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
31832 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
31833 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
31834 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
31835 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
31836 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31837 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31838 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31839 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31840 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31841 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31842 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31843 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31844 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31845 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31846 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31847 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31848 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31849 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31850 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31851 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31852 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31853 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31854 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31855 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31856 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31857 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31858 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31859 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31860 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31861 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31862 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31863 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31864 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
31865 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
31866 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
31867 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
31868 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
31869 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31870 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31871 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31872 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31873 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31874 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
31875 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
31876 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
31877 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
31878 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
31879 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
31880 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31881 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
31882 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31883 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31884 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31885 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31886 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31887 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31888 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31889 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31890 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31891 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31892 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31893 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31894 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31895 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31896 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31897 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31898 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31899 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31900 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31901 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31902 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31903 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31904 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31905 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31906 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31907 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31908 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31909 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31910 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31911 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31912 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31913 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31914 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31915 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31916 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31917 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31918 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31919 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31920 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31921 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31922 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31923 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31924 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31925 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31926 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31927 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31928 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31929 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31930 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31931 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
31932 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
31933 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
31934 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
31935 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31936 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31937 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31938 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
31940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
31941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
31942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
31943 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31944 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31945 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31946 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31947 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
31948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31949 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31952 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
31954 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
31955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31956 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31957 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31958 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
31960 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
31961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
31962 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
31963 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31964 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31965 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31966 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31967 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31968 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31969 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
31970 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
31971 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
31972 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
31974 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
31975 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
31976 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
31977 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
31978 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
31979 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
31980 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
31981 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
31983 /* Mask arithmetic operations */
31984 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31985 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31986 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
31987 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31988 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31989 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31990 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
31991 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31992 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31993 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
31995 /* SHA */
31996 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31997 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31998 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31999 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
32000 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32001 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32002 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
32004 /* AVX512VL. */
32005 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT },
32006 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT },
32007 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32008 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32009 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32010 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32011 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32012 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32013 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32014 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32015 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32016 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32017 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32018 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32019 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32020 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32021 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32022 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32023 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32024 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32025 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32026 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32027 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32028 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32029 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32030 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32031 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32032 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32033 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32034 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32035 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32036 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32037 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32038 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32039 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32040 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32041 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32042 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32043 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32044 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32045 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32046 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32047 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32048 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32049 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32050 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32051 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32052 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32053 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32054 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32055 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32056 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32057 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32058 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_QI },
32059 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_QI },
32060 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI },
32061 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI },
32062 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32063 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32064 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32065 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32066 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32067 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32068 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32069 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32070 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32071 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32072 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32073 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32074 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32075 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32076 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32077 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32078 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32079 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32080 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32081 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32082 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32083 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32084 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32085 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32086 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32087 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32088 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32089 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32090 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32091 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32092 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32093 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32094 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_QI },
32095 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_QI },
32096 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_SI },
32097 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_SI },
32098 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32099 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_HI },
32100 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_HI },
32101 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_HI },
32102 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32103 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_QI },
32104 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32105 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_QI },
32106 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32107 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_QI },
32108 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32109 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
32110 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32111 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
32112 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32113 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32114 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32115 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_QI },
32116 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_QI },
32117 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI },
32118 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI },
32119 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32120 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32121 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32122 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32123 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32124 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32125 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32126 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32127 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32128 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32129 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32130 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32131 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32132 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32133 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32134 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32135 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32136 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32137 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32138 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32139 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32140 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32141 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32142 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32143 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32144 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32145 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32146 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32147 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32148 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32149 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32150 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32151 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32152 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32153 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32154 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32155 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32156 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32157 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32158 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32159 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32160 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32161 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32162 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32163 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32164 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32165 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32166 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32167 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32168 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32169 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32170 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32171 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32172 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32173 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32174 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32175 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32176 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32177 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32178 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32179 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32180 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32181 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32182 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32183 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32184 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32185 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32186 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32187 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32188 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32189 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32190 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32191 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32192 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32193 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32194 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32195 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32196 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32197 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32198 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32199 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32200 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32201 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32202 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32203 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32204 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32205 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32206 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32207 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32208 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32209 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32210 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32211 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32212 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32213 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32214 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32215 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32216 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32217 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32218 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32219 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32220 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32221 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32222 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32223 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32224 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32225 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32226 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32227 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32228 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32229 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32230 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32231 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32232 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32233 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32234 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32235 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32236 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32237 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32238 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32239 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32240 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32241 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32242 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32243 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32244 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32245 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32246 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32247 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32248 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32249 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32250 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32251 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32252 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32253 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32254 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32255 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32256 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32257 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32258 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32259 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32260 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32261 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32262 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32263 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32264 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32265 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32266 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32267 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32268 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32269 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32270 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32271 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32272 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32273 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32274 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32275 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32276 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32277 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32278 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32279 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32280 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32281 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32282 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32283 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32284 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32285 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32286 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32287 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32288 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32289 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32290 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32291 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32292 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32293 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32294 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32295 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32296 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32297 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32298 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32299 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32300 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32301 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32302 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32303 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32304 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32305 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32306 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32307 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32308 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32309 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32310 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32311 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32312 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32313 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32314 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32315 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32316 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32317 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32318 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32319 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32320 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32321 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32322 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32323 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32324 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32325 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32326 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32327 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32328 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32329 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32330 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32331 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32332 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32333 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32334 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32335 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32336 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32337 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32338 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32339 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32340 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32341 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32342 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32343 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32344 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32345 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32346 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32347 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32348 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32349 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32350 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32351 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32352 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32353 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32354 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32355 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32356 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32357 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32358 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32359 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32360 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32361 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32362 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32363 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32364 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32365 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32366 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32367 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32368 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32369 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32370 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32371 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32372 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32373 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32374 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32375 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32376 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32377 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32378 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32379 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32380 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32381 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32382 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32383 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32384 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32385 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32386 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32387 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI },
32388 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI },
32389 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32390 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32391 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_HI },
32392 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_QI },
32393 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_QI },
32394 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_QI },
32395 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32396 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32397 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32398 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32399 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32400 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32401 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32402 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32403 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32404 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32405 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32406 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32407 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32408 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32409 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32410 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32411 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32412 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32413 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32414 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32415 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32416 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32417 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32418 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32419 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32420 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32421 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32422 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32423 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32424 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32425 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32426 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32427 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32428 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32429 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32430 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32431 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32432 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32433 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32434 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32435 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32436 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32437 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32438 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32439 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32440 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32441 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32442 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32443 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32444 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32445 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32446 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32447 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32448 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32449 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32450 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32451 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32452 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32453 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32454 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32455 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32456 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32457 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32458 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32459 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32460 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32461 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32462 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32463 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32464 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32465 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32466 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32467 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32468 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32469 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32470 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32471 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32472 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32473 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32474 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32475 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32476 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32477 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32478 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32479 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32480 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32481 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32482 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32483 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32484 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32485 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32486 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32487 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32488 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32489 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32490 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32491 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32492 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32493 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32494 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32495 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_QI },
32496 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_QI },
32497 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
32498 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_QI },
32499 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_QI },
32500 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
32501 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) HI_FTYPE_V16QI },
32502 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) SI_FTYPE_V32QI },
32503 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) QI_FTYPE_V8HI },
32504 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) HI_FTYPE_V16HI },
32505 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) QI_FTYPE_V4SI },
32506 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) QI_FTYPE_V8SI },
32507 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) QI_FTYPE_V2DI },
32508 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) QI_FTYPE_V4DI },
32509 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_HI },
32510 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_SI },
32511 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_QI },
32512 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_HI },
32513 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_QI },
32514 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_QI },
32515 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_QI },
32516 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_QI },
32517 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32518 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32519 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32520 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32521 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32522 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32523 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32524 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32525 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32526 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32527 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32528 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32529 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32530 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32531 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32532 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32533 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32534 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32535 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32536 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32537 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32538 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32539 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32540 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32541 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32542 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32543 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32544 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32545 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32546 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32547 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32548 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32549 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_QI },
32550 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_QI },
32551 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_HI },
32552 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_HI },
32553 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32554 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32555 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32556 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32557 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32558 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32559 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32560 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32561 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32562 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32563 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32564 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32565 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32566 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32567 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32568 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32569 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32570 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32571 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32572 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32573 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32574 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32575 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32576 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32577 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32578 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32579 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32580 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32581 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32582 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32583 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32584 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32585 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32586 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32587 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32588 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32589 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32590 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32591 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32592 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32593 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32594 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32595 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32596 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32597 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32598 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32599 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32600 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32601 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32602 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32603 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32604 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32605 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32606 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32607 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32608 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32609 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32610 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32611 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32612 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32613 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32614 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32615 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32616 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32617 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32618 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32619 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32620 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32621 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32622 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32623 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32624 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32625 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32626 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32627 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI },
32628 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI },
32629 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_QI },
32630 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_QI },
32631 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_QI },
32632 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_QI },
32633 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32634 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32635 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32636 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32637 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32638 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32639 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32640 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32641 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32642 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32643 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32644 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32645 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32646 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32647 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32648 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32649 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32650 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32651 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32652 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32653 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32654 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32655 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32656 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32657 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32658 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32659 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32660 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32661 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32662 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32663 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32664 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32665 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32666 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32667 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32668 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32669 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32670 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32671 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32672 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32673 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32674 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32675 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32676 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32677 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32678 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32679 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32680 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32681 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32682 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32683 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32684 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32685 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32686 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32687 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32688 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32689 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32690 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32691 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32692 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_QI },
32693 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_QI },
32694 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32695 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32696 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32697 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32698 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32699 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32700 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32701 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32702 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32703 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32704 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32705 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_QI },
32706 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_QI },
32707 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32708 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32709 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32710 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32711 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32712 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32713 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32714 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32715 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI },
32716 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI },
32718 /* AVX512DQ. */
32719 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
32720 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
32721 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
32722 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
32723 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_HI },
32724 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_HI },
32725 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_QI },
32726 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_QI },
32727 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_QI },
32728 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_QI },
32729 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32730 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32731 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32732 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32733 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32734 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32735 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32736 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32737 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32738 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI},
32739 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32740 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI },
32741 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI },
32742 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI },
32743 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI },
32744 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_QI },
32745 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_HI },
32746 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) HI_FTYPE_V16SI },
32747 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) QI_FTYPE_V8DI },
32748 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_HI },
32749 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_QI },
32751 /* AVX512BW. */
32752 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) SI_FTYPE_SI_SI },
32753 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) DI_FTYPE_DI_DI },
32754 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32755 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32756 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32757 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32758 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
32759 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT },
32760 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32761 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32762 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
32763 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI },
32764 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_DI },
32765 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_DI },
32766 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_SI },
32767 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_SI },
32768 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32769 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32770 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32771 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32772 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32773 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32774 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32775 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32776 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32777 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32778 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32779 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32780 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32781 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32782 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32783 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32784 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32785 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32786 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32787 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32788 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32789 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32790 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32791 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32792 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32793 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32794 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32795 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32796 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32797 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32798 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32799 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32800 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32801 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32802 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32803 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32804 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32805 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32806 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32807 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32808 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_SI },
32809 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_HI },
32810 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32811 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32812 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32813 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32814 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32815 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32816 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32817 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32818 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32819 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32820 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32821 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32822 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) DI_FTYPE_V64QI },
32823 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) SI_FTYPE_V32HI },
32824 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_DI },
32825 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_SI },
32826 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32827 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32828 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32829 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32830 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32831 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32832 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32833 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32834 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32835 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32836 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32837 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32838 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32839 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32840 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
32841 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32842 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
32844 /* AVX512IFMA */
32845 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_mask, "__builtin_ia32_vpmadd52luq512_mask", IX86_BUILTIN_VPMADD52LUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32846 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_maskz, "__builtin_ia32_vpmadd52luq512_maskz", IX86_BUILTIN_VPMADD52LUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32847 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_mask, "__builtin_ia32_vpmadd52huq512_mask", IX86_BUILTIN_VPMADD52HUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32848 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_maskz, "__builtin_ia32_vpmadd52huq512_maskz", IX86_BUILTIN_VPMADD52HUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32849 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_mask, "__builtin_ia32_vpmadd52luq256_mask", IX86_BUILTIN_VPMADD52LUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32850 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_maskz, "__builtin_ia32_vpmadd52luq256_maskz", IX86_BUILTIN_VPMADD52LUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32851 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_mask, "__builtin_ia32_vpmadd52huq256_mask", IX86_BUILTIN_VPMADD52HUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32852 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_maskz, "__builtin_ia32_vpmadd52huq256_maskz", IX86_BUILTIN_VPMADD52HUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32853 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_mask, "__builtin_ia32_vpmadd52luq128_mask", IX86_BUILTIN_VPMADD52LUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32854 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_maskz, "__builtin_ia32_vpmadd52luq128_maskz", IX86_BUILTIN_VPMADD52LUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32855 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_mask, "__builtin_ia32_vpmadd52huq128_mask", IX86_BUILTIN_VPMADD52HUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32856 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_maskz, "__builtin_ia32_vpmadd52huq128_maskz", IX86_BUILTIN_VPMADD52HUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32858 /* AVX512VBMI */
32859 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_vpmultishiftqbv64qi_mask, "__builtin_ia32_vpmultishiftqb512_mask", IX86_BUILTIN_VPMULTISHIFTQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32860 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv32qi_mask, "__builtin_ia32_vpmultishiftqb256_mask", IX86_BUILTIN_VPMULTISHIFTQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32861 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv16qi_mask, "__builtin_ia32_vpmultishiftqb128_mask", IX86_BUILTIN_VPMULTISHIFTQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32862 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_permvarv64qi_mask, "__builtin_ia32_permvarqi512_mask", IX86_BUILTIN_VPERMVARQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32863 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_mask, "__builtin_ia32_vpermt2varqi512_mask", IX86_BUILTIN_VPERMT2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32864 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_maskz, "__builtin_ia32_vpermt2varqi512_maskz", IX86_BUILTIN_VPERMT2VARQI512_MASKZ, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32865 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermi2varv64qi3_mask, "__builtin_ia32_vpermi2varqi512_mask", IX86_BUILTIN_VPERMI2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32866 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv32qi_mask, "__builtin_ia32_permvarqi256_mask", IX86_BUILTIN_VPERMVARQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32867 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16qi_mask, "__builtin_ia32_permvarqi128_mask", IX86_BUILTIN_VPERMVARQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32868 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_mask, "__builtin_ia32_vpermt2varqi256_mask", IX86_BUILTIN_VPERMT2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32869 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_maskz, "__builtin_ia32_vpermt2varqi256_maskz", IX86_BUILTIN_VPERMT2VARQI256_MASKZ, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32870 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_mask, "__builtin_ia32_vpermt2varqi128_mask", IX86_BUILTIN_VPERMT2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32871 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_maskz, "__builtin_ia32_vpermt2varqi128_maskz", IX86_BUILTIN_VPERMT2VARQI128_MASKZ, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32872 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv32qi3_mask, "__builtin_ia32_vpermi2varqi256_mask", IX86_BUILTIN_VPERMI2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32873 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16qi3_mask, "__builtin_ia32_vpermi2varqi128_mask", IX86_BUILTIN_VPERMI2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32874 };
32876 /* Builtins with rounding support. */
32878 {
32879 /* AVX512F */
32880 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32881 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32882 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32883 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32884 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
32885 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
32886 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
32887 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
32888 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
32889 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
32890 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
32891 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32892 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
32893 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32894 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
32895 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32896 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
32897 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32898 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
32899 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
32900 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
32901 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
32902 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
32903 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32904 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32905 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32906 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32907 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
32908 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
32909 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
32910 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
32911 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32912 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32913 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32914 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32915 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
32916 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
32917 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
32918 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
32919 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
32920 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
32921 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
32922 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
32923 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32924 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32925 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32926 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32927 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
32928 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
32929 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32930 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32931 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32932 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32933 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32934 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32935 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32936 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32937 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32938 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
32944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
32945 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32946 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32947 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32949 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32952 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32954 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32956 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32957 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32958 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
32960 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
32961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
32962 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
32963 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
32964 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
32965 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
32966 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
32967 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
32968 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
32969 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
32970 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
32971 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
32972 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
32973 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
32974 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
32975 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32976 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32977 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32978 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32979 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32980 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32981 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
32982 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
32983 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32984 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32985 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32986 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32987 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32988 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32989 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32990 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32991 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32992 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32993 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32994 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32995 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32996 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32997 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32998 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33000 /* AVX512ER */
33001 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33002 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33003 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33004 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33005 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33006 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33007 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33008 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33009 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33010 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33012 /* AVX512DQ. */
33013 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33014 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33015 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33016 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33017 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33018 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33019 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33020 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33021 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33022 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33023 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33024 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33025 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33026 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33027 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
33028 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
33029 };
33031 /* Bultins for MPX. */
33033 {
33034 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndstx", IX86_BUILTIN_BNDSTX, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND_PCVOID },
33035 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcl", IX86_BUILTIN_BNDCL, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33036 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcu", IX86_BUILTIN_BNDCU, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33037 };
33039 /* Const builtins for MPX. */
33041 {
33042 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndmk", IX86_BUILTIN_BNDMK, UNKNOWN, (int) BND_FTYPE_PCVOID_ULONG },
33043 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndldx", IX86_BUILTIN_BNDLDX, UNKNOWN, (int) BND_FTYPE_PCVOID_PCVOID },
33044 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_narrow_bounds", IX86_BUILTIN_BNDNARROW, UNKNOWN, (int) PVOID_FTYPE_PCVOID_BND_ULONG },
33045 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndint", IX86_BUILTIN_BNDINT, UNKNOWN, (int) BND_FTYPE_BND_BND },
33046 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_sizeof", IX86_BUILTIN_SIZEOF, UNKNOWN, (int) ULONG_FTYPE_VOID },
33047 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndlower", IX86_BUILTIN_BNDLOWER, UNKNOWN, (int) PVOID_FTYPE_BND },
33048 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndupper", IX86_BUILTIN_BNDUPPER, UNKNOWN, (int) PVOID_FTYPE_BND },
33049 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndret", IX86_BUILTIN_BNDRET, UNKNOWN, (int) BND_FTYPE_PCVOID },
33050 };
33052 /* FMA4 and XOP. */
33053 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
33054 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
33055 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
33056 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
33057 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
33058 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
33059 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
33060 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
33061 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
33062 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
33063 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
33064 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
33065 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
33066 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
33067 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
33068 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
33069 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
33070 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
33071 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
33072 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
33073 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
33074 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
33075 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
33076 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
33077 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
33078 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
33079 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
33080 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
33081 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
33082 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
33083 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
33084 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
33085 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
33086 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
33087 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
33088 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
33089 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
33090 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
33091 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
33092 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
33093 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
33094 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
33095 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
33096 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
33097 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
33098 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
33099 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
33100 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
33101 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
33102 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
33103 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
33104 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
33107 {
33148 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
33149 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
33150 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
33151 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
33152 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
33153 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
33154 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
33156 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33157 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33158 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
33159 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
33160 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
33161 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
33162 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
33164 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
33166 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33167 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33168 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33169 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33170 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33171 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33172 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33173 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33174 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33175 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33176 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33177 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33179 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33180 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
33181 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
33182 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
33183 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
33184 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
33185 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
33186 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
33187 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33188 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
33189 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
33190 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
33191 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33192 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
33193 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
33194 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
33196 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
33197 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
33198 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
33199 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
33200 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
33201 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
33203 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33204 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33205 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33206 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33207 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33208 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33209 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33210 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33211 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33212 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33213 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33214 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33215 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33216 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33217 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33219 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
33220 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33221 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33222 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
33223 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
33224 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
33225 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
33227 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
33228 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33229 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33230 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
33231 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
33232 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
33233 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
33235 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
33236 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33237 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33238 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
33239 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
33240 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
33241 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
33243 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33244 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33245 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33246 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
33247 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
33248 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
33249 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
33251 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
33252 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33253 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33254 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
33255 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
33256 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
33257 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
33259 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
33260 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33261 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33262 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
33263 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
33264 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
33265 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
33267 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
33268 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33269 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33270 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
33271 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
33272 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
33273 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
33275 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33276 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33277 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33278 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
33279 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
33280 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
33281 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
33283 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33284 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33285 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33286 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33287 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33288 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33289 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33290 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33292 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33293 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33294 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33295 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33296 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33297 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33298 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33299 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33301 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
33302 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
33303 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
33304 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
33306 };
33307 \f
33308 /* TM vector builtins. */
33310 /* Reuse the existing x86-specific `struct builtin_description' cause
33311 we're lazy. Add casts to make them fit. */
33313 {
33314 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33315 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33316 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33317 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33318 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33319 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33320 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33322 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33323 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33324 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33325 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33326 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33327 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33328 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33330 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33331 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33332 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33333 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33334 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33335 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33336 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33338 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
33339 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
33340 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
33341 };
33343 /* TM callbacks. */
33345 /* Return the builtin decl needed to load a vector of TYPE. */
33347 static tree
33349 {
33351 {
33353 {
33360 }
33361 }
33363 }
33365 /* Return the builtin decl needed to store a vector of TYPE. */
33367 static tree
33369 {
33371 {
33373 {
33380 }
33381 }
33383 }
33384 \f
33385 /* Initialize the transactional memory vector load/store builtins. */
33387 static void
33389 {
33393 tree decl;
33400 /* If there are no builtins defined, we must be compiling in a
33401 language without trans-mem support. */
33405 /* Use whatever attributes a normal TM load has. */
33409 /* Use whatever attributes a normal TM store has. */
33413 /* Use whatever attributes a normal TM log has. */
33421 {
33425 {
33433 {
33436 }
33438 {
33441 }
33442 else
33443 {
33446 }
33448 /* The builtin without the prefix for
33449 calling it directly. */
33451 attrs);
33452 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
33453 set the TYPE_ATTRIBUTES. */
33457 }
33458 }
33459 }
33461 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
33462 in the current target ISA to allow the user to compile particular modules
33463 with different target specific options that differ from the command line
33464 options. */
33465 static void
33467 {
33472 /* Add all special builtins with variable number of operands. */
33476 {
33482 }
33484 /* Add all builtins with variable number of operands. */
33488 {
33494 }
33496 /* Add all builtins with rounding. */
33500 {
33506 }
33508 /* pcmpestr[im] insns. */
33512 {
33515 else
33518 }
33520 /* pcmpistr[im] insns. */
33524 {
33527 else
33530 }
33532 /* comi/ucomi insns. */
33534 {
33537 else
33540 }
33542 /* SSE */
33548 /* SSE or 3DNow!A */
33551 IX86_BUILTIN_MASKMOVQ);
33553 /* SSE2 */
33562 /* SSE3. */
33568 /* AES */
33582 /* PCLMUL */
33586 /* RDRND */
33593 IX86_BUILTIN_RDRAND64_STEP);
33595 /* AVX2 */
33597 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
33598 IX86_BUILTIN_GATHERSIV2DF);
33601 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
33602 IX86_BUILTIN_GATHERSIV4DF);
33605 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
33606 IX86_BUILTIN_GATHERDIV2DF);
33609 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
33610 IX86_BUILTIN_GATHERDIV4DF);
33613 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
33614 IX86_BUILTIN_GATHERSIV4SF);
33617 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
33618 IX86_BUILTIN_GATHERSIV8SF);
33621 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
33622 IX86_BUILTIN_GATHERDIV4SF);
33625 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
33626 IX86_BUILTIN_GATHERDIV8SF);
33629 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
33630 IX86_BUILTIN_GATHERSIV2DI);
33633 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
33634 IX86_BUILTIN_GATHERSIV4DI);
33637 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
33638 IX86_BUILTIN_GATHERDIV2DI);
33641 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
33642 IX86_BUILTIN_GATHERDIV4DI);
33645 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
33646 IX86_BUILTIN_GATHERSIV4SI);
33649 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
33650 IX86_BUILTIN_GATHERSIV8SI);
33653 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
33654 IX86_BUILTIN_GATHERDIV4SI);
33657 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
33658 IX86_BUILTIN_GATHERDIV8SI);
33661 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
33662 IX86_BUILTIN_GATHERALTSIV4DF);
33665 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
33666 IX86_BUILTIN_GATHERALTDIV8SF);
33669 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
33670 IX86_BUILTIN_GATHERALTSIV4DI);
33673 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
33674 IX86_BUILTIN_GATHERALTDIV8SI);
33676 /* AVX512F */
33678 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
33679 IX86_BUILTIN_GATHER3SIV16SF);
33682 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
33683 IX86_BUILTIN_GATHER3SIV8DF);
33686 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
33687 IX86_BUILTIN_GATHER3DIV16SF);
33690 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
33691 IX86_BUILTIN_GATHER3DIV8DF);
33694 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
33695 IX86_BUILTIN_GATHER3SIV16SI);
33698 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
33699 IX86_BUILTIN_GATHER3SIV8DI);
33702 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
33703 IX86_BUILTIN_GATHER3DIV16SI);
33706 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
33707 IX86_BUILTIN_GATHER3DIV8DI);
33710 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
33711 IX86_BUILTIN_GATHER3ALTSIV8DF);
33714 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
33715 IX86_BUILTIN_GATHER3ALTDIV16SF);
33718 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
33719 IX86_BUILTIN_GATHER3ALTSIV8DI);
33722 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
33723 IX86_BUILTIN_GATHER3ALTDIV16SI);
33726 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
33727 IX86_BUILTIN_SCATTERSIV16SF);
33730 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
33731 IX86_BUILTIN_SCATTERSIV8DF);
33734 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
33735 IX86_BUILTIN_SCATTERDIV16SF);
33738 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
33739 IX86_BUILTIN_SCATTERDIV8DF);
33742 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
33743 IX86_BUILTIN_SCATTERSIV16SI);
33746 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
33747 IX86_BUILTIN_SCATTERSIV8DI);
33750 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
33751 IX86_BUILTIN_SCATTERDIV16SI);
33754 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
33755 IX86_BUILTIN_SCATTERDIV8DI);
33757 /* AVX512VL */
33759 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_QI_INT,
33760 IX86_BUILTIN_GATHER3SIV2DF);
33763 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_QI_INT,
33764 IX86_BUILTIN_GATHER3SIV4DF);
33767 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_QI_INT,
33768 IX86_BUILTIN_GATHER3DIV2DF);
33771 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_QI_INT,
33772 IX86_BUILTIN_GATHER3DIV4DF);
33775 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_QI_INT,
33776 IX86_BUILTIN_GATHER3SIV4SF);
33779 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_QI_INT,
33780 IX86_BUILTIN_GATHER3SIV8SF);
33783 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_QI_INT,
33784 IX86_BUILTIN_GATHER3DIV4SF);
33787 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_QI_INT,
33788 IX86_BUILTIN_GATHER3DIV8SF);
33791 V2DI_FTYPE_V2DI_PCINT64_V4SI_QI_INT,
33792 IX86_BUILTIN_GATHER3SIV2DI);
33795 V4DI_FTYPE_V4DI_PCINT64_V4SI_QI_INT,
33796 IX86_BUILTIN_GATHER3SIV4DI);
33799 V2DI_FTYPE_V2DI_PCINT64_V2DI_QI_INT,
33800 IX86_BUILTIN_GATHER3DIV2DI);
33803 V4DI_FTYPE_V4DI_PCINT64_V4DI_QI_INT,
33804 IX86_BUILTIN_GATHER3DIV4DI);
33807 V4SI_FTYPE_V4SI_PCINT_V4SI_QI_INT,
33808 IX86_BUILTIN_GATHER3SIV4SI);
33811 V8SI_FTYPE_V8SI_PCINT_V8SI_QI_INT,
33812 IX86_BUILTIN_GATHER3SIV8SI);
33815 V4SI_FTYPE_V4SI_PCINT_V2DI_QI_INT,
33816 IX86_BUILTIN_GATHER3DIV4SI);
33819 V4SI_FTYPE_V4SI_PCINT_V4DI_QI_INT,
33820 IX86_BUILTIN_GATHER3DIV8SI);
33823 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
33824 IX86_BUILTIN_GATHER3ALTSIV4DF);
33827 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
33828 IX86_BUILTIN_GATHER3ALTDIV8SF);
33831 V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
33832 IX86_BUILTIN_GATHER3ALTSIV4DI);
33835 V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
33836 IX86_BUILTIN_GATHER3ALTDIV8SI);
33839 VOID_FTYPE_PFLOAT_QI_V8SI_V8SF_INT,
33840 IX86_BUILTIN_SCATTERSIV8SF);
33843 VOID_FTYPE_PFLOAT_QI_V4SI_V4SF_INT,
33844 IX86_BUILTIN_SCATTERSIV4SF);
33847 VOID_FTYPE_PDOUBLE_QI_V4SI_V4DF_INT,
33848 IX86_BUILTIN_SCATTERSIV4DF);
33851 VOID_FTYPE_PDOUBLE_QI_V4SI_V2DF_INT,
33852 IX86_BUILTIN_SCATTERSIV2DF);
33855 VOID_FTYPE_PFLOAT_QI_V4DI_V4SF_INT,
33856 IX86_BUILTIN_SCATTERDIV8SF);
33859 VOID_FTYPE_PFLOAT_QI_V2DI_V4SF_INT,
33860 IX86_BUILTIN_SCATTERDIV4SF);
33863 VOID_FTYPE_PDOUBLE_QI_V4DI_V4DF_INT,
33864 IX86_BUILTIN_SCATTERDIV4DF);
33867 VOID_FTYPE_PDOUBLE_QI_V2DI_V2DF_INT,
33868 IX86_BUILTIN_SCATTERDIV2DF);
33871 VOID_FTYPE_PINT_QI_V8SI_V8SI_INT,
33872 IX86_BUILTIN_SCATTERSIV8SI);
33875 VOID_FTYPE_PINT_QI_V4SI_V4SI_INT,
33876 IX86_BUILTIN_SCATTERSIV4SI);
33879 VOID_FTYPE_PLONGLONG_QI_V4SI_V4DI_INT,
33880 IX86_BUILTIN_SCATTERSIV4DI);
33883 VOID_FTYPE_PLONGLONG_QI_V4SI_V2DI_INT,
33884 IX86_BUILTIN_SCATTERSIV2DI);
33887 VOID_FTYPE_PINT_QI_V4DI_V4SI_INT,
33888 IX86_BUILTIN_SCATTERDIV8SI);
33891 VOID_FTYPE_PINT_QI_V2DI_V4SI_INT,
33892 IX86_BUILTIN_SCATTERDIV4SI);
33895 VOID_FTYPE_PLONGLONG_QI_V4DI_V4DI_INT,
33896 IX86_BUILTIN_SCATTERDIV4DI);
33899 VOID_FTYPE_PLONGLONG_QI_V2DI_V2DI_INT,
33900 IX86_BUILTIN_SCATTERDIV2DI);
33902 /* AVX512PF */
33904 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
33905 IX86_BUILTIN_GATHERPFDPD);
33907 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
33908 IX86_BUILTIN_GATHERPFDPS);
33910 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
33911 IX86_BUILTIN_GATHERPFQPD);
33913 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
33914 IX86_BUILTIN_GATHERPFQPS);
33916 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
33917 IX86_BUILTIN_SCATTERPFDPD);
33919 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
33920 IX86_BUILTIN_SCATTERPFDPS);
33922 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
33923 IX86_BUILTIN_SCATTERPFQPD);
33925 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
33926 IX86_BUILTIN_SCATTERPFQPS);
33928 /* SHA */
33944 /* RTM. */
33948 /* MMX access to the vec_init patterns. */
33953 V4HI_FTYPE_HI_HI_HI_HI,
33954 IX86_BUILTIN_VEC_INIT_V4HI);
33957 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
33958 IX86_BUILTIN_VEC_INIT_V8QI);
33960 /* Access to the vec_extract patterns. */
33982 /* Access to the vec_set patterns. */
34003 /* RDSEED */
34012 /* ADCX */
34017 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34018 IX86_BUILTIN_ADDCARRYX64);
34020 /* SBB */
34025 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34026 IX86_BUILTIN_SBB64);
34028 /* Read/write FLAGS. */
34038 /* CLFLUSHOPT. */
34042 /* CLWB. */
34046 /* Add FMA4 multi-arg argument instructions */
34048 {
34054 }
34055 }
34057 static void
34059 {
34062 tree decl;
34068 {
34075 /* With no leaf and nothrow flags for MPX builtins
34076 abnormal edges may follow its call when setjmp
34077 presents in the function. Since we may have a lot
34078 of MPX builtins calls it causes lots of useless
34079 edges and enormous PHI nodes. To avoid this we mark
34080 MPX builtins as leaf and nothrow. */
34082 {
34084 NULL_TREE);
34086 }
34087 else
34088 {
34091 }
34092 }
34097 {
34105 {
34107 NULL_TREE);
34109 }
34110 else
34111 {
34114 }
34115 }
34116 }
34118 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
34119 to return a pointer to VERSION_DECL if the outcome of the expression
34120 formed by PREDICATE_CHAIN is true. This function will be called during
34121 version dispatch to decide which function version to execute. It returns
34122 the basic block at the end, to which more conditions can be added. */
34124 static basic_block
34127 {
34128 gimple return_stmt;
34130 gimple convert_stmt;
34131 gimple call_cond_stmt;
34132 gimple if_else_stmt;
34138 gimple_seq gseq;
34155 {
34163 }
34166 {
34181 else
34182 {
34183 gimple assign_stmt;
34184 /* Use MIN_EXPR to check if any integer is zero?.
34185 and_expr_var = min_expr <cond_var, and_expr_var> */
34193 }
34194 }
34197 integer_zero_node,
34227 }
34229 /* This parses the attribute arguments to target in DECL and determines
34230 the right builtin to use to match the platform specification.
34231 It returns the priority value for this version decl. If PREDICATE_LIST
34232 is not NULL, it stores the list of cpu features that need to be checked
34233 before dispatching this function. */
34235 static unsigned int
34237 {
34238 tree attrs;
34240 tree target_node;
34247 /* Priority of i386 features, greater value is higher priority. This is
34248 used to decide the order in which function dispatch must happen. For
34249 instance, a version specialized for SSE4.2 should be checked for dispatch
34250 before a version for SSE3, as SSE4.2 implies SSE3. */
34251 enum feature_priority
34252 {
34254 P_MMX,
34255 P_SSE,
34256 P_SSE2,
34257 P_SSE3,
34258 P_SSSE3,
34259 P_PROC_SSSE3,
34260 P_SSE4_A,
34261 P_PROC_SSE4_A,
34262 P_SSE4_1,
34263 P_SSE4_2,
34264 P_PROC_SSE4_2,
34265 P_POPCNT,
34266 P_AVX,
34267 P_PROC_AVX,
34268 P_FMA4,
34269 P_XOP,
34270 P_PROC_XOP,
34271 P_FMA,
34272 P_PROC_FMA,
34273 P_AVX2,
34274 P_PROC_AVX2,
34275 P_AVX512F,
34276 P_PROC_AVX512F
34277 };
34281 /* These are the target attribute strings for which a dispatcher is
34282 available, from fold_builtin_cpu. */
34284 static struct _feature_list
34285 {
34288 }
34290 {
34306 };
34309 static unsigned int NUM_FEATURES
34325 /* Return priority zero for default function. */
34329 /* Handle arch= if specified. For priority, set it to be 1 more than
34330 the best instruction set the processor can handle. For instance, if
34331 there is a version for atom and a version for ssse3 (the highest ISA
34332 priority for atom), the atom version must be checked for dispatch
34333 before the ssse3 version. */
34335 {
34345 {
34347 {
34355 else
34356 /* We translate "arch=corei7" and "arch=nehalem" to
34357 "corei7" so that it will be mapped to M_INTEL_COREI7
34358 as cpu type to cover all M_INTEL_COREI7_XXXs. */
34365 else
34372 else
34416 }
34417 }
34422 {
34426 }
34429 {
34431 /* For a C string literal the length includes the trailing NULL. */
34434 predicate_chain);
34435 }
34436 }
34438 /* Process feature name. */
34445 {
34446 /* Do not process "arch=" */
34448 {
34451 }
34453 {
34455 {
34457 {
34462 predicate_chain);
34463 }
34464 /* Find the maximum priority feature. */
34469 }
34470 }
34472 {
34476 }
34478 }
34482 {
34485 attrs_str);
34487 }
34489 {
34492 }
34495 }
34497 /* This compares the priority of target features in function DECL1
34498 and DECL2. It returns positive value if DECL1 is higher priority,
34499 negative value if DECL2 is higher priority and 0 if they are the
34500 same. */
34502 static int
34504 {
34509 }
34511 /* V1 and V2 point to function versions with different priorities
34512 based on the target ISA. This function compares their priorities. */
34514 static int
34516 {
34518 {
34519 tree version_decl;
34520 tree predicate_chain;
34527 }
34529 /* This function generates the dispatch function for
34530 multi-versioned functions. DISPATCH_DECL is the function which will
34531 contain the dispatch logic. FNDECLS are the function choices for
34532 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
34533 in DISPATCH_DECL in which the dispatch code is generated. */
34535 static int
34539 {
34540 tree default_decl;
34541 gimple ifunc_cpu_init_stmt;
34542 gimple_seq gseq;
34544 tree ele;
34550 struct _function_version_info
34551 {
34552 tree version_decl;
34553 tree predicate_chain;
34561 /*fndecls_p is actually a vector. */
34564 /* At least one more version other than the default. */
34571 /* The first version in the vector is the default decl. */
34577 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
34578 constructors, so explicity call __builtin_cpu_init here. */
34589 {
34593 /* Get attribute string, parse it and find the right predicate decl.
34594 The predicate function could be a lengthy combination of many
34595 features, like arch-type and various isa-variants. */
34606 actual_versions++;
34607 }
34609 /* Sort the versions according to descending order of dispatch priority. The
34610 priority is based on the ISA. This is not a perfect solution. There
34611 could still be ambiguity. If more than one function version is suitable
34612 to execute, which one should be dispatched? In future, allow the user
34613 to specify a dispatch priority next to the version. */
34623 /* dispatch default version at the end. */
34629 }
34631 /* Comparator function to be used in qsort routine to sort attribute
34632 specification strings to "target". */
34634 static int
34636 {
34640 }
34642 /* ARGLIST is the argument to target attribute. This function tokenizes
34643 the comma separated arguments, sorts them and returns a string which
34644 is a unique identifier for the comma separated arguments. It also
34645 replaces non-identifier characters "=,-" with "_". */
34649 {
34650 tree arg;
34659 {
34664 argnum++;
34667 argnum++;
34668 }
34673 {
34679 }
34681 /* Replace "=,-" with "_". */
34694 {
34696 i++;
34698 }
34705 {
34710 }
34715 }
34717 /* This function changes the assembler name for functions that are
34718 versions. If DECL is a function version and has a "target"
34719 attribute, it appends the attribute string to its assembler name. */
34721 static tree
34723 {
34724 tree version_attr;
34732 "Function versions cannot be marked as gnu_inline,"
34741 /* target attribute string cannot be NULL. */
34745 version_string
34756 /* Allow assembler name to be modified if already set. */
34764 }
34766 /* This function returns true if FN1 and FN2 are versions of the same function,
34767 that is, the target strings of the function decls are different. This assumes
34768 that FN1 and FN2 have the same signature. */
34770 static bool
34772 {
34784 /* At least one function decl should have the target attribute specified. */
34788 /* Diagnose missing target attribute if one of the decls is already
34789 multi-versioned. */
34791 {
34793 {
34795 {
34800 }
34803 fn2);
34806 /* Prevent diagnosing of the same error multiple times. */
34811 }
34813 }
34818 /* The sorted target strings must be different for fn1 and fn2
34819 to be versions. */
34822 else
34829 }
34831 static tree
34833 {
34834 /* For function version, add the target suffix to the assembler name. */
34838 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
34840 #endif
34843 }
34845 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
34846 is true, append the full path name of the source file. */
34850 {
34858 /* Get a unique name that can be used globally without any chances
34859 of collision at link time. */
34869 /* Use '.' to concatenate names as it is demangler friendly. */
34872 suffix);
34873 else
34877 }
34879 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
34881 /* Make a dispatcher declaration for the multi-versioned function DECL.
34882 Calls to DECL function will be replaced with calls to the dispatcher
34883 by the front-end. Return the decl created. */
34885 static tree
34887 {
34888 tree func_decl;
34908 /* Mark this func as external, the resolver will flip it again if
34909 it gets generated. */
34911 /* This will be of type IFUNCs have to be externally visible. */
34915 }
34917 #endif
34919 /* Returns true if decl is multi-versioned and DECL is the default function,
34920 that is it is not tagged with target specific optimization. */
34922 static bool
34924 {
34933 }
34935 /* Make a dispatcher declaration for the multi-versioned function DECL.
34936 Calls to DECL function will be replaced with calls to the dispatcher
34937 by the front-end. Returns the decl of the dispatcher function. */
34939 static tree
34941 {
34963 /* Find the default version and make it the first node. */
34965 /* Go to the beginning of the chain. */
34970 {
34975 }
34977 /* If there is no default node, just return NULL. */
34981 /* Make default info the first node. */
34983 {
34990 }
34994 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
34996 {
35001 /* Right now, the dispatching is done via ifunc. */
35007 dispatcher_version_info
35012 /* Set the dispatcher for all the versions. */
35015 {
35018 }
35019 }
35020 else
35021 #endif
35022 {
35024 "multiversioning needs ifunc which is not supported "
35026 }
35029 }
35031 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
35032 it to CHAIN. */
35034 static tree
35036 {
35037 tree attr_name;
35038 tree attr_arg_name;
35039 tree attr_args;
35040 tree attr;
35047 }
35049 /* Make the resolver function decl to dispatch the versions of
35050 a multi-versioned function, DEFAULT_DECL. Create an
35051 empty basic block in the resolver and store the pointer in
35052 EMPTY_BB. Return the decl of the resolver function. */
35054 static tree
35058 {
35063 /* IFUNC's have to be globally visible. So, if the default_decl is
35064 not, then the name of the IFUNC should be made unique. */
35068 /* Append the filename to the resolver function if the versions are
35069 not externally visible. This is because the resolver function has
35070 to be externally visible for the loader to find it. So, appending
35071 the filename will prevent conflicts with a resolver function from
35072 another module which is based on the same version name. */
35075 /* The resolver function should return a (void *). */
35086 /* IFUNC resolvers have to be externally visible. */
35090 /* Resolver is not external, body is generated. */
35100 {
35101 /* In this case, each translation unit with a call to this
35102 versioned function will put out a resolver. Ensure it
35103 is comdat to keep just one copy. */
35106 }
35107 /* Build result decl and add to function_decl. */
35123 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
35127 /* Create the alias for dispatch to resolver here. */
35128 /*cgraph_create_function_alias (dispatch_decl, decl);*/
35132 }
35134 /* Generate the dispatching code body to dispatch multi-versioned function
35135 DECL. The target hook is called to process the "target" attributes and
35136 provide the code to dispatch the right function at run-time. NODE points
35137 to the dispatcher decl whose body will be created. */
35139 static tree
35141 {
35142 tree resolver_decl;
35143 basic_block empty_bb;
35144 tree default_ver_decl;
35160 /* The first version in the chain corresponds to the default version. */
35163 /* node is going to be an alias, so remove the finalized bit. */
35177 {
35179 /* Check for virtual functions here again, as by this time it should
35180 have been determined if this function needs a vtable index or
35181 not. This happens for methods in derived classes that override
35182 virtual methods in base classes but are not explicitly marked as
35183 virtual. */
35188 }
35194 }
35195 /* This builds the processor_model struct type defined in
35196 libgcc/config/i386/cpuinfo.c */
35198 static tree
35200 {
35207 /* The first 3 fields are unsigned int. */
35209 {
35215 }
35217 /* The last field is an array of unsigned integers of size one. */
35228 }
35230 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
35232 static tree
35234 {
35235 tree new_decl;
35238 VAR_DECL,
35240 type);
35253 }
35255 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
35256 into an integer defined in libgcc/config/i386/cpuinfo.c */
35258 static tree
35260 {
35266 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
35267 enum processor_features
35268 {
35270 F_MMX,
35271 F_POPCNT,
35272 F_SSE,
35273 F_SSE2,
35274 F_SSE3,
35275 F_SSSE3,
35276 F_SSE4_1,
35277 F_SSE4_2,
35278 F_AVX,
35279 F_AVX2,
35280 F_SSE4_A,
35281 F_FMA4,
35282 F_XOP,
35283 F_FMA,
35284 F_AVX512F,
35285 F_MAX
35286 };
35288 /* These are the values for vendor types and cpu types and subtypes
35289 in cpuinfo.c. Cpu types and subtypes should be subtracted by
35290 the corresponding start value. */
35291 enum processor_model
35292 {
35294 M_AMD,
35295 M_CPU_TYPE_START,
35296 M_INTEL_BONNELL,
35297 M_INTEL_CORE2,
35298 M_INTEL_COREI7,
35299 M_AMDFAM10H,
35300 M_AMDFAM15H,
35301 M_INTEL_SILVERMONT,
35302 M_INTEL_KNL,
35303 M_AMD_BTVER1,
35304 M_AMD_BTVER2,
35305 M_CPU_SUBTYPE_START,
35306 M_INTEL_COREI7_NEHALEM,
35307 M_INTEL_COREI7_WESTMERE,
35308 M_INTEL_COREI7_SANDYBRIDGE,
35309 M_AMDFAM10H_BARCELONA,
35310 M_AMDFAM10H_SHANGHAI,
35311 M_AMDFAM10H_ISTANBUL,
35312 M_AMDFAM15H_BDVER1,
35313 M_AMDFAM15H_BDVER2,
35314 M_AMDFAM15H_BDVER3,
35315 M_AMDFAM15H_BDVER4,
35316 M_INTEL_COREI7_IVYBRIDGE,
35317 M_INTEL_COREI7_HASWELL
35318 };
35320 static struct _arch_names_table
35321 {
35324 }
35326 {
35352 };
35354 static struct _isa_names_table
35355 {
35358 }
35360 {
35377 };
35391 {
35392 /* *args must be a expr that can contain other EXPRS leading to a
35393 STRING_CST. */
35395 {
35398 }
35400 }
35405 {
35406 tree ref;
35407 tree field;
35408 tree final;
35411 unsigned int NUM_ARCH_NAMES
35420 {
35424 }
35429 /* CPU types are stored in the next field. */
35432 {
35435 }
35437 /* CPU subtypes are stored in the next field. */
35439 {
35442 }
35444 /* Get the appropriate field in __cpu_model. */
35448 /* Check the value. */
35452 }
35454 {
35455 tree ref;
35456 tree array_elt;
35457 tree field;
35458 tree final;
35461 unsigned int NUM_ISA_NAMES
35470 {
35474 }
35477 /* Get the last field, which is __cpu_features. */
35481 /* Get the appropriate field: __cpu_model.__cpu_features */
35485 /* Access the 0th element of __cpu_features array. */
35490 /* Return __cpu_model.__cpu_features[0] & field_val */
35494 }
35496 }
35498 static tree
35501 {
35503 {
35508 {
35511 }
35512 }
35514 #ifdef SUBTARGET_FOLD_BUILTIN
35516 #endif
35519 }
35521 /* Make builtins to detect cpu type and features supported. NAME is
35522 the builtin name, CODE is the builtin code, and FTYPE is the function
35523 type of the builtin. */
35525 static void
35528 {
35529 tree decl;
35530 tree type;
35538 }
35540 /* Make builtins to get CPU type and features supported. The created
35541 builtins are :
35543 __builtin_cpu_init (), to detect cpu type and features,
35544 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
35545 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
35546 */
35548 static void
35550 {
35557 }
35559 /* Internal method for ix86_init_builtins. */
35561 static void
35563 {
35575 sysv_va_ref =
35578 fnvoid_va_end_ms =
35580 fnvoid_va_start_ms =
35582 fnvoid_va_end_sysv =
35584 fnvoid_va_start_sysv =
35586 NULL_TREE);
35587 fnvoid_va_copy_ms =
35589 NULL_TREE);
35590 fnvoid_va_copy_sysv =
35606 }
35608 static void
35610 {
35613 /* The __float80 type. */
35616 {
35617 /* The __float80 type. */
35622 }
35625 /* The __float128 type. */
35631 /* This macro is built by i386-builtin-types.awk. */
35632 DEFINE_BUILTIN_PRIMITIVE_TYPES;
35633 }
35635 static void
35637 {
35638 tree t;
35642 /* Builtins to get CPU type and features. */
35645 /* TFmode support builtins. */
35651 /* We will expand them to normal call if SSE isn't available since
35652 they are used by libgcc. */
35672 #ifdef SUBTARGET_INIT_BUILTINS
35673 SUBTARGET_INIT_BUILTINS;
35674 #endif
35675 }
35677 /* Return the ix86 builtin for CODE. */
35679 static tree
35681 {
35686 }
35688 /* Errors in the source file can cause expand_expr to return const0_rtx
35689 where we expect a vector. To avoid crashing, use one of the vector
35690 clear instructions. */
35691 static rtx
35693 {
35697 }
35699 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
35701 static rtx
35703 {
35704 rtx pat;
35724 {
35728 }
35742 }
35744 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
35746 static rtx
35750 {
35751 rtx pat;
35759 rtx op;
35760 machine_mode mode;
35766 {
35846 }
35856 {
35863 {
35865 {
35868 {
35886 xop_rotl:
35888 {
35891 gcc_checking_assert
35893 }
35894 else
35895 {
35896 gcc_checking_assert
35907 }
35911 }
35912 }
35913 }
35914 else
35915 {
35916 non_constant:
35920 /* If we aren't optimizing, only allow one memory operand to be
35921 generated. */
35923 num_memory++;
35931 }
35935 }
35938 {
35949 else
35950 {
35956 }
35969 }
35976 }
35978 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
35979 insns with vec_merge. */
35981 static rtx
35983 rtx target)
35984 {
35985 rtx pat;
36012 }
36014 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
36016 static rtx
36019 {
36020 rtx pat;
36025 rtx op2;
36036 /* Swap operands if we have a comparison that isn't available in
36037 hardware. */
36039 {
36044 }
36064 }
36066 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
36068 static rtx
36070 rtx target)
36071 {
36072 rtx pat;
36086 /* Swap operands if we have a comparison that isn't available in
36087 hardware. */
36110 const0_rtx)));
36113 }
36115 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
36117 static rtx
36119 rtx target)
36120 {
36121 rtx pat;
36146 }
36148 static rtx
36151 {
36152 rtx pat;
36157 rtx op2;
36184 }
36186 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
36188 static rtx
36190 rtx target)
36191 {
36192 rtx pat;
36225 const0_rtx)));
36228 }
36230 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
36232 static rtx
36235 {
36236 rtx pat;
36274 {
36277 }
36280 {
36289 }
36291 {
36300 }
36301 else
36302 {
36309 }
36317 {
36322 emit_insn
36326 FLAGS_REG),
36327 const0_rtx)));
36329 }
36330 else
36332 }
36335 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
36337 static rtx
36340 {
36341 rtx pat;
36369 {
36372 }
36375 {
36384 }
36386 {
36395 }
36396 else
36397 {
36404 }
36412 {
36417 emit_insn
36421 FLAGS_REG),
36422 const0_rtx)));
36424 }
36425 else
36427 }
36429 /* Subroutine of ix86_expand_builtin to take care of insns with
36430 variable number of operands. */
36432 static rtx
36435 {
36441 struct
36442 {
36443 rtx op;
36444 machine_mode mode;
36455 {
37165 }
37170 {
37173 }
37176 {
37183 }
37184 else
37185 {
37188 }
37191 {
37198 {
37199 /* SIMD shift insns take either an 8-bit immediate or
37200 register as count. But builtin functions take int as
37201 count. If count doesn't match, we put it in register. */
37203 {
37207 }
37208 }
37211 {
37214 {
37323 {
37327 {
37330 }
37336 }
37338 }
37339 }
37340 else
37341 {
37345 /* If we aren't optimizing, only allow one memory operand to
37346 be generated. */
37348 num_memory++;
37351 {
37354 }
37355 else
37356 {
37359 }
37360 }
37364 }
37367 {
37392 }
37399 }
37401 /* Transform pattern of following layout:
37402 (parallel [
37403 set (A B)
37404 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
37405 ])
37406 into:
37407 (set (A B))
37409 Or:
37410 (parallel [ A B
37411 ...
37412 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
37413 ...
37414 ])
37415 into:
37416 (parallel [ A B ... ]) */
37418 static rtx
37420 {
37427 {
37436 }
37437 else
37438 {
37444 {
37449 }
37451 /* No more than 1 occurence was removed. */
37455 }
37456 }
37458 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
37459 with rounding. */
37460 static rtx
37463 {
37480 /* See avxintrin.h for values. */
37482 {
37486 };
37488 {
37493 };
37496 {
37499 }
37501 {
37504 }
37507 {
37510 }
37533 ? CODE_FOR_sse_ucomi_round
37540 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
37542 {
37548 }
37549 else
37550 {
37553 }
37559 set_dst,
37560 const0_rtx)));
37563 }
37565 static rtx
37568 {
37569 rtx pat;
37571 struct
37572 {
37573 rtx op;
37574 machine_mode mode;
37583 {
37666 }
37676 {
37683 {
37685 {
37687 {
37703 }
37704 }
37705 }
37707 {
37709 {
37712 }
37714 /* If there is no rounding use normal version of the pattern. */
37717 }
37718 else
37719 {
37724 {
37727 }
37728 else
37729 {
37732 }
37733 }
37737 }
37740 {
37765 }
37775 }
37777 /* Subroutine of ix86_expand_builtin to take care of special insns
37778 with variable number of operands. */
37780 static rtx
37783 {
37784 tree arg;
37788 struct
37789 {
37790 rtx op;
37791 machine_mode mode;
37800 {
37840 {
37848 }
37867 /* Reserve memory operand for target. */
37870 {
37871 /* These builtins and instructions require the memory
37872 to be properly aligned. */
37891 }
37920 {
37921 /* These builtins and instructions require the memory
37922 to be properly aligned. */
37939 }
37940 /* FALLTHRU */
37978 /* Reserve memory operand for target. */
38005 {
38006 /* These builtins and instructions require the memory
38007 to be properly aligned. */
38030 }
38043 }
38048 {
38053 {
38056 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
38057 on it. Try to improve it using get_pointer_alignment,
38058 and if the special builtin is one that requires strict
38059 mode alignment, also from it's GET_MODE_ALIGNMENT.
38060 Failure to do so could lead to ix86_legitimate_combined_insn
38061 rejecting all changes to such insns. */
38067 }
38068 else
38071 }
38072 else
38073 {
38080 }
38083 {
38092 {
38094 {
38100 else
38103 }
38104 }
38105 else
38106 {
38108 {
38109 /* This must be the memory operand. */
38112 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
38113 on it. Try to improve it using get_pointer_alignment,
38114 and if the special builtin is one that requires strict
38115 mode alignment, also from it's GET_MODE_ALIGNMENT.
38116 Failure to do so could lead to ix86_legitimate_combined_insn
38117 rejecting all changes to such insns. */
38123 }
38124 else
38125 {
38126 /* This must be register. */
38132 else
38133 {
38136 }
38137 }
38138 }
38142 }
38145 {
38160 }
38166 }
38168 /* Return the integer constant in ARG. Constrain it to be in the range
38169 of the subparts of VEC_TYPE; issue an error if not. */
38171 static int
38173 {
38178 {
38181 }
38184 }
38186 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38187 ix86_expand_vector_init. We DO have language-level syntax for this, in
38188 the form of (type){ init-list }. Except that since we can't place emms
38189 instructions from inside the compiler, we can't allow the use of MMX
38190 registers unless the user explicitly asks for it. So we do *not* define
38191 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
38192 we have builtins invoked by mmintrin.h that gives us license to emit
38193 these sorts of instructions. */
38195 static rtx
38197 {
38207 {
38210 }
38217 }
38219 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38220 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
38221 had a language-level syntax for referencing vector elements. */
38223 static rtx
38225 {
38229 rtx op0;
38249 }
38251 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38252 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
38253 a language-level syntax for referencing vector elements. */
38255 static rtx
38257 {
38281 /* OP0 is the source of these builtin functions and shouldn't be
38282 modified. Create a copy, use it and return it as target. */
38288 }
38290 /* Emit conditional move of SRC to DST with condition
38291 OP1 CODE OP2. */
38292 static void
38294 {
38295 rtx t;
38298 {
38303 }
38304 else
38305 {
38311 }
38312 }
38314 /* Choose max of DST and SRC and put it to DST. */
38315 static void
38317 {
38319 }
38321 /* Expand an expression EXP that calls a built-in function,
38322 with result going to TARGET if that's convenient
38323 (and in mode MODE if that's convenient).
38324 SUBTARGET may be used as the target for computing one of EXP's operands.
38325 IGNORE is nonzero if the value is to be ignored. */
38327 static rtx
38330 {
38340 /* For CPU builtins that can be folded, fold first and expand the fold. */
38342 {
38344 {
38345 /* Make it call __cpu_indicator_init in libgcc. */
38351 }
38354 {
38359 }
38360 }
38362 /* Determine whether the builtin function is available under the current ISA.
38363 Originally the builtin was not created if it wasn't applicable to the
38364 current ISA based on the command line switches. With function specific
38365 options, we need to check in the context of the function making the call
38366 whether it is supported. */
38369 {
38375 else
38376 {
38380 }
38382 }
38385 {
38403 /* Builtin arg1 is size of block but instruction op1 should
38404 be (size - 1). */
38495 /* If no bounds were specified for returned value,
38496 then use INIT bounds. It usually happens when
38497 some built-in function is expanded. */
38499 {
38508 }
38514 {
38517 /* Return value and lb. */
38519 /* Bounds. */
38521 /* Size. */
38528 /* Size was passed but we need to use (size - 1) as for bndmk. */
38532 /* Add LB to size and inverse to get UB. */
38542 /* We need to move bounds to memory before any computations. */
38545 else
38546 {
38549 }
38551 /* Generate mem expression to be used for access to LB and UB. */
38557 /* Compute LB. */
38562 /* Compute UB. UB is stored in 1's complement form. Therefore
38563 we also use max here. */
38572 }
38575 {
38593 /* Put first bounds to temporaries. */
38597 {
38601 }
38602 else
38603 {
38607 }
38609 /* Put second bounds to temporaries. */
38613 {
38617 }
38618 else
38619 {
38623 }
38625 /* Compute LB. */
38629 /* Compute UB. UB is stored in 1's complement form. Therefore
38630 we also use max here. */
38637 }
38640 {
38641 tree name;
38642 rtx symbol;
38660 }
38663 {
38674 /* We need to move bounds to memory first. */
38677 else
38678 {
38681 }
38683 /* Generate mem expression to access LB and load it. */
38688 }
38691 {
38702 /* We need to move bounds to memory first. */
38705 else
38706 {
38709 }
38711 /* Generate mem expression to access UB. */
38714 /* We need to inverse all bits of UB. */
38721 }
38726 ? CODE_FOR_mmx_maskmovq
38728 /* Note the arg order is different from the operand order. */
38849 {
38850 REAL_VALUE_TYPE inf;
38851 rtx tmp;
38863 }
38873 {
38879 insn = (TARGET_64BIT
38883 }
38885 {
38886 insn = (TARGET_64BIT
38890 }
38891 else
38892 {
38895 insn = (TARGET_64BIT
38903 {
38906 }
38908 }
38911 {
38912 /* mode is VOIDmode if __builtin_rd* has been called
38913 without lhs. */
38917 }
38920 {
38925 }
38938 {
38959 }
38965 {
38968 }
38994 {
38997 }
39003 {
39007 {
39046 }
39051 }
39052 else
39053 {
39055 {
39076 }
39078 }
39108 ? CODE_FOR_tbm_bextri_si
39111 {
39114 }
39115 else
39116 {
39125 }
39141 rdrand_step:
39148 {
39151 }
39157 /* Emit SImode conditional move. */
39159 {
39162 }
39165 else
39173 const0_rtx);
39192 rdseed_step:
39199 {
39202 }
39208 const0_rtx);
39237 addcarryx:
39245 /* Generate CF from input operand. */
39250 /* Gen ADCX instruction to compute X+Y+CF. */
39265 /* Store the result. */
39268 {
39271 }
39274 /* Return current CF value. */
39316 kortest:
39330 /* Emit kortest. */
39332 /* And use setcc to return result from flags. */
39590 gather_gen:
39591 rtx half;
39604 /* Note the arg order is different from the operand order. */
39615 else
39619 {
39643 else
39650 {
39655 }
39664 else
39671 {
39676 }
39680 }
39682 /* Force memory operand only with base register here. But we
39683 don't want to do it on memory operand for other builtin
39684 functions. */
39694 {
39697 }
39698 else
39699 {
39702 }
39704 {
39707 }
39709 /* Optimize. If mask is known to have all high bits set,
39710 replace op0 with pc_rtx to signal that the instruction
39711 overwrites the whole destination and doesn't use its
39712 previous contents. */
39714 {
39716 {
39719 }
39721 {
39724 {
39728 negative++;
39731 negative++;
39732 }
39735 }
39738 {
39739 /* Recognize also when mask is like:
39740 __v2df src = _mm_setzero_pd ();
39741 __v2df mask = _mm_cmpeq_pd (src, src);
39742 or
39743 __v8sf src = _mm256_setzero_ps ();
39744 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
39745 as that is a cheaper way to load all ones into
39746 a register than having to load a constant from
39747 memory. */
39750 {
39755 {
39762 /* FALLTHRU */
39772 }
39773 }
39774 }
39775 }
39783 {
39809 }
39812 scatter_gen:
39828 /* Force memory operand only with base register here. But we
39829 don't want to do it on memory operand for other builtin
39830 functions. */
39837 {
39840 }
39841 else
39842 {
39845 }
39854 {
39857 }
39866 vec_prefetch_gen:
39884 {
39887 }
39889 {
39892 }
39897 /* Force memory operand only with base register here. But we
39898 don't want to do it on memory operand for other builtin
39899 functions. */
39906 {
39909 }
39912 {
39915 }
39931 {
39934 }
39940 }
39953 {
39957 /* Emit a normal call if SSE isn't available. */
39961 }
39990 }
39992 /* This returns the target-specific builtin with code CODE if
39993 current_function_decl has visibility on this builtin, which is checked
39994 using isa flags. Returns NULL_TREE otherwise. */
39997 {
40001 /* Determine the isa flags of current_function_decl. */
40013 else
40015 }
40017 /* Return function decl for target specific builtin
40018 for given MPX builtin passed i FCODE. */
40019 static tree
40021 {
40023 {
40059 }
40062 }
40064 /* Helper function for ix86_load_bounds and ix86_store_bounds.
40066 Return an address to be used to load/store bounds for pointer
40067 passed in SLOT.
40069 SLOT_NO is an integer constant holding number of a target
40070 dependent special slot to be used in case SLOT is not a memory.
40072 SPECIAL_BASE is a pointer to be used as a base of fake address
40073 to access special slots in Bounds Table. SPECIAL_BASE[-1],
40074 SPECIAL_BASE[-2] etc. will be used as fake pointer locations. */
40076 static rtx
40078 {
40081 /* NULL slot means we pass bounds for pointer not passed to the
40082 function at all. Register slot means we pass pointer in a
40083 register. In both these cases bounds are passed via Bounds
40084 Table. Since we do not have actual pointer stored in memory,
40085 we have to use fake addresses to access Bounds Table. We
40086 start with (special_base - sizeof (void*)) and decrease this
40087 address by pointer size to get addresses for other slots. */
40089 {
40093 }
40094 /* If pointer is passed in a memory then its address is used to
40095 access Bounds Table. */
40097 {
40101 }
40102 else
40106 }
40108 /* Expand pass uses this hook to load bounds for function parameter
40109 PTR passed in SLOT in case its bounds are not passed in a register.
40111 If SLOT is a memory, then bounds are loaded as for regular pointer
40112 loaded from memory. PTR may be NULL in case SLOT is a memory.
40113 In such case value of PTR (if required) may be loaded from SLOT.
40115 If SLOT is NULL or a register then SLOT_NO is an integer constant
40116 holding number of the target dependent special slot which should be
40117 used to obtain bounds.
40119 Return loaded bounds. */
40121 static rtx
40123 {
40125 rtx addr;
40127 /* Get address to be used to access Bounds Table. Special slots start
40128 at the location of return address of the current function. */
40131 /* Load pointer value from a memory if we don't have it. */
40133 {
40136 }
40143 }
40145 /* Expand pass uses this hook to store BOUNDS for call argument PTR
40146 passed in SLOT in case BOUNDS are not passed in a register.
40148 If SLOT is a memory, then BOUNDS are stored as for regular pointer
40149 stored in memory. PTR may be NULL in case SLOT is a memory.
40150 In such case value of PTR (if required) may be loaded from SLOT.
40152 If SLOT is NULL or a register then SLOT_NO is an integer constant
40153 holding number of the target dependent special slot which should be
40154 used to store BOUNDS. */
40156 static void
40158 {
40159 rtx addr;
40161 /* Get address to be used to access Bounds Table. Special slots start
40162 at the location of return address of a called function. */
40165 /* Load pointer value from a memory if we don't have it. */
40167 {
40170 }
40179 }
40181 /* Load and return bounds returned by function in SLOT. */
40183 static rtx
40185 {
40186 rtx res;
40193 }
40195 /* Store BOUNDS returned by function into SLOT. */
40197 static void
40199 {
40202 }
40204 /* Returns a function decl for a vectorized version of the builtin function
40205 with builtin function code FN and the result vector type TYPE, or NULL_TREE
40206 if it is not available. */
40208 static tree
40210 tree type_in)
40211 {
40227 {
40230 {
40237 }
40242 {
40245 }
40250 {
40257 }
40263 /* The round insn does not trap on denormals. */
40268 {
40275 }
40281 /* The round insn does not trap on denormals. */
40286 {
40291 }
40297 /* The round insn does not trap on denormals. */
40302 {
40309 }
40315 /* The round insn does not trap on denormals. */
40320 {
40325 }
40332 {
40337 }
40344 {
40349 }
40355 /* The round insn does not trap on denormals. */
40360 {
40367 }
40373 /* The round insn does not trap on denormals. */
40378 {
40383 }
40388 {
40395 }
40400 {
40407 }
40411 /* The round insn does not trap on denormals. */
40416 {
40421 }
40425 /* The round insn does not trap on denormals. */
40430 {
40435 }
40439 /* The round insn does not trap on denormals. */
40444 {
40449 }
40453 /* The round insn does not trap on denormals. */
40458 {
40463 }
40467 /* The round insn does not trap on denormals. */
40472 {
40477 }
40481 /* The round insn does not trap on denormals. */
40486 {
40491 }
40495 /* The round insn does not trap on denormals. */
40500 {
40505 }
40509 /* The round insn does not trap on denormals. */
40514 {
40519 }
40523 /* The round insn does not trap on denormals. */
40528 {
40533 }
40537 /* The round insn does not trap on denormals. */
40542 {
40547 }
40552 {
40557 }
40562 {
40567 }
40572 }
40574 /* Dispatch to a handler for a vectorization library. */
40577 type_in);
40580 }
40582 /* Handler for an SVML-style interface to
40583 a library with vectorized intrinsics. */
40585 static tree
40587 {
40595 /* The SVML is suitable for unsafe math only. */
40608 {
40655 }
40664 {
40667 }
40668 else
40671 /* Convert to uppercase. */
40676 args;
40678 arity++;
40682 else
40685 /* Build a function declaration for the vectorized function. */
40694 }
40696 /* Handler for an ACML-style interface to
40697 a library with vectorized intrinsics. */
40699 static tree
40701 {
40709 /* The ACML is 64bits only and suitable for unsafe math only as
40710 it does not correctly support parts of IEEE with the required
40711 precision such as denormals. */
40725 {
40755 }
40762 args;
40764 arity++;
40768 else
40771 /* Build a function declaration for the vectorized function. */
40780 }
40782 /* Returns a decl of a function that implements gather load with
40783 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
40784 Return NULL_TREE if it is not available. */
40786 static tree
40789 {
40805 /* v*gather* insn sign extends index to pointer mode. */
40817 {
40821 else
40827 else
40833 else
40839 else
40845 else
40851 else
40857 else
40863 else
40869 else
40875 else
40881 else
40887 else
40892 }
40895 }
40897 /* Returns a code for a target-specific builtin that implements
40898 reciprocal of the function, or NULL_TREE if not available. */
40900 static tree
40902 {
40909 /* Machine dependent builtins. */
40911 {
40912 /* Vectorized version of sqrt to rsqrt conversion. */
40921 }
40922 else
40923 /* Normal builtins. */
40925 {
40926 /* Sqrt to rsqrt conversion. */
40932 }
40933 }
40934 \f
40935 /* Helper for avx_vpermilps256_operand et al. This is also used by
40936 the expansion functions to turn the parallel back into a mask.
40937 The return value is 0 for no match and the imm8+1 for a match. */
40939 int
40941 {
40949 /* Validate that all of the elements are constants, and not totally
40950 out of range. Copy the data into an integral array to make the
40951 subsequent checks easier. */
40953 {
40963 }
40966 {
40968 /* In the 512-bit DFmode case, we can only move elements within
40969 a 128-bit lane. First fill the second part of the mask,
40970 then fallthru. */
40972 {
40976 }
40978 {
40982 }
40983 /* FALLTHRU */
40986 /* In the 256-bit DFmode case, we can only move elements within
40987 a 128-bit lane. */
40989 {
40993 }
40995 {
40999 }
41003 /* In 512 bit SFmode case, permutation in the upper 256 bits
41004 must mirror the permutation in the lower 256-bits. */
41008 /* FALLTHRU */
41011 /* In 256 bit SFmode case, we have full freedom of
41012 movement within the low 128-bit lane, but the high 128-bit
41013 lane must mirror the exact same pattern. */
41018 /* FALLTHRU */
41022 /* In the 128-bit case, we've full freedom in the placement of
41023 the elements from the source operand. */
41030 }
41032 /* Make sure success has a non-zero value by adding one. */
41034 }
41036 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
41037 the expansion functions to turn the parallel back into a mask.
41038 The return value is 0 for no match and the imm8+1 for a match. */
41040 int
41042 {
41050 /* Validate that all of the elements are constants, and not totally
41051 out of range. Copy the data into an integral array to make the
41052 subsequent checks easier. */
41054 {
41064 }
41066 /* Validate that the halves of the permute are halves. */
41074 /* Reconstruct the mask. */
41076 {
41082 }
41084 /* Make sure success has a non-zero value by adding one. */
41086 }
41087 \f
41088 /* Return a register priority for hard reg REGNO. */
41089 static int
41091 {
41092 /* ebp and r13 as the base always wants a displacement, r12 as the
41093 base always wants an index. So discourage their usage in an
41094 address. */
41099 /* New x86-64 int registers result in bigger code size. Discourage
41100 them. */
41103 /* New x86-64 SSE registers result in bigger code size. Discourage
41104 them. */
41107 /* Usage of AX register results in smaller code. Prefer it. */
41111 }
41113 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
41115 Put float CONST_DOUBLE in the constant pool instead of fp regs.
41116 QImode must go into class Q_REGS.
41117 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
41118 movdf to do mem-to-mem moves through integer regs. */
41120 static reg_class_t
41122 {
41125 /* We're only allowed to return a subclass of CLASS. Many of the
41126 following checks fail for NO_REGS, so eliminate that early. */
41130 /* All classes can load zeros. */
41134 /* Force constants into memory if we are loading a (nonzero) constant into
41135 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
41136 instructions to load from a constant. */
41143 /* Prefer SSE regs only, if we can use them for math. */
41147 /* Floating-point constants need more complex checks. */
41149 {
41150 /* General regs can load everything. */
41154 /* Floats can load 0 and 1 plus some others. Note that we eliminated
41155 zero above. We only want to wind up preferring 80387 registers if
41156 we plan on doing computation with them. */
41159 {
41160 /* Limit class to non-sse. */
41169 }
41172 }
41174 /* Generally when we see PLUS here, it's the function invariant
41175 (plus soft-fp const_int). Which can only be computed into general
41176 regs. */
41180 /* QImode constants are easy to load, but non-constant QImode data
41181 must go into Q_REGS. */
41183 {
41189 }
41192 }
41194 /* Discourage putting floating-point values in SSE registers unless
41195 SSE math is being used, and likewise for the 387 registers. */
41196 static reg_class_t
41198 {
41201 /* Restrict the output reload class to the register bank that we are doing
41202 math on. If we would like not to return a subset of CLASS, reject this
41203 alternative: if reload cannot do this, it will still use its choice. */
41209 {
41214 else
41216 }
41219 }
41221 static reg_class_t
41224 {
41225 /* Double-word spills from general registers to non-offsettable memory
41226 references (zero-extended addresses) require special handling. */
41232 {
41234 ? CODE_FOR_reload_noff_load
41236 /* Add the cost of moving address to a temporary. */
41240 }
41242 /* QImode spills from non-QI registers require
41243 intermediate register on 32bit targets. */
41249 {
41254 else
41260 /* Return Q_REGS if the operand is in memory. */
41263 }
41265 /* This condition handles corner case where an expression involving
41266 pointers gets vectorized. We're trying to use the address of a
41267 stack slot as a vector initializer.
41269 (set (reg:V2DI 74 [ vect_cst_.2 ])
41270 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
41272 Eventually frame gets turned into sp+offset like this:
41274 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41275 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41276 (const_int 392 [0x188]))))
41278 That later gets turned into:
41280 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41281 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41282 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
41284 We'll have the following reload recorded:
41286 Reload 0: reload_in (DI) =
41287 (plus:DI (reg/f:DI 7 sp)
41288 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
41289 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41290 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
41291 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
41292 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41293 reload_reg_rtx: (reg:V2DI 22 xmm1)
41295 Which isn't going to work since SSE instructions can't handle scalar
41296 additions. Returning GENERAL_REGS forces the addition into integer
41297 register and reload can handle subsequent reloads without problems. */
41305 }
41307 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
41309 static bool
41311 {
41313 {
41329 }
41332 }
41334 /* If we are copying between general and FP registers, we need a memory
41335 location. The same is true for SSE and MMX registers.
41337 To optimize register_move_cost performance, allow inline variant.
41339 The macro can't work reliably when one of the CLASSES is class containing
41340 registers from multiple units (SSE, MMX, integer). We avoid this by never
41341 combining those units in single alternative in the machine description.
41342 Ensure that this constraint holds to avoid unexpected surprises.
41344 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
41345 enforce these sanity checks. */
41350 {
41359 {
41362 }
41367 /* Between mask and general, we have moves no larger than word size. */
41372 /* ??? This is a lie. We do have moves between mmx/general, and for
41373 mmx/sse2. But by saying we need secondary memory we discourage the
41374 register allocator from using the mmx registers unless needed. */
41379 {
41380 /* SSE1 doesn't have any direct moves from other classes. */
41384 /* If the target says that inter-unit moves are more expensive
41385 than moving through memory, then don't generate them. */
41390 /* Between SSE and general, we have moves no larger than word size. */
41393 }
41396 }
41398 bool
41401 {
41403 }
41405 /* Implement the TARGET_CLASS_MAX_NREGS hook.
41407 On the 80386, this is the size of MODE in words,
41408 except in the FP regs, where a single reg is always enough. */
41410 static unsigned char
41412 {
41414 {
41419 else
41421 }
41422 else
41423 {
41426 else
41428 }
41429 }
41431 /* Return true if the registers in CLASS cannot represent the change from
41432 modes FROM to TO. */
41434 bool
41437 {
41441 /* x87 registers can't do subreg at all, as all values are reformatted
41442 to extended precision. */
41447 {
41448 /* Vector registers do not support QI or HImode loads. If we don't
41449 disallow a change to these modes, reload will assume it's ok to
41450 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
41451 the vec_dupv4hi pattern. */
41454 }
41457 }
41459 /* Return the cost of moving data of mode M between a
41460 register and memory. A value of 2 is the default; this cost is
41461 relative to those in `REGISTER_MOVE_COST'.
41463 This function is used extensively by register_move_cost that is used to
41464 build tables at startup. Make it inline in this case.
41465 When IN is 2, return maximum of in and out move cost.
41467 If moving between registers and memory is more expensive than
41468 between two registers, you should define this macro to express the
41469 relative cost.
41471 Model also increased moving costs of QImode registers in non
41472 Q_REGS classes.
41473 */
41477 {
41480 {
41483 {
41495 }
41499 }
41501 {
41504 {
41516 }
41520 }
41522 {
41525 {
41534 }
41538 }
41540 {
41543 {
41549 else
41554 }
41555 else
41556 {
41561 else
41563 }
41570 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
41577 else
41581 }
41582 }
41584 static int
41587 {
41589 }
41592 /* Return the cost of moving data from a register in class CLASS1 to
41593 one in class CLASS2.
41595 It is not required that the cost always equal 2 when FROM is the same as TO;
41596 on some machines it is expensive to move between registers if they are not
41597 general registers. */
41599 static int
41601 reg_class_t class2_i)
41602 {
41606 /* In case we require secondary memory, compute cost of the store followed
41607 by load. In order to avoid bad register allocation choices, we need
41608 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
41611 {
41617 /* In case of copying from general_purpose_register we may emit multiple
41618 stores followed by single load causing memory size mismatch stall.
41619 Count this as arbitrarily high cost of 20. */
41624 /* In the case of FP/MMX moves, the registers actually overlap, and we
41625 have to switch modes in order to treat them differently. */
41631 }
41633 /* Moves between SSE/MMX and integer unit are expensive. */
41637 /* ??? By keeping returned value relatively high, we limit the number
41638 of moves between integer and MMX/SSE registers for all targets.
41639 Additionally, high value prevents problem with x86_modes_tieable_p(),
41640 where integer modes in MMX/SSE registers are not tieable
41641 because of missing QImode and HImode moves to, from or between
41642 MMX/SSE registers. */
41652 }
41654 /* Return TRUE if hard register REGNO can hold a value of machine-mode
41655 MODE. */
41657 bool
41659 {
41660 /* Flags and only flags can only hold CCmode values. */
41676 {
41677 /* We implement the move patterns for all vector modes into and
41678 out of SSE registers, even when no operation instructions
41679 are available. */
41681 /* For AVX-512 we allow, regardless of regno:
41682 - XI mode
41683 - any of 512-bit wide vector mode
41684 - any scalar mode. */
41691 /* TODO check for QI/HI scalars. */
41692 /* AVX512VL allows sse regs16+ for 128/256 bit modes. */
41700 /* xmm16-xmm31 are only available for AVX-512. */
41704 /* OImode and AVX modes are available only when AVX is enabled. */
41711 }
41713 {
41714 /* We implement the move patterns for 3DNOW modes even in MMX mode,
41715 so if the register is available at all, then we can move data of
41716 the given mode into or out of it. */
41719 }
41722 {
41723 /* Take care for QImode values - they can be in non-QI regs,
41724 but then they do cause partial register stalls. */
41729 /* LRA checks if the hard register is OK for the given mode.
41730 QImode values can live in non-QI regs, so we allow all
41731 registers here. */
41735 }
41736 /* We handle both integer and floats in the general purpose registers. */
41743 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
41744 on to use that value in smaller contexts, this can easily force a
41745 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
41746 supporting DImode, allow it. */
41751 }
41753 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
41754 tieable integer mode. */
41756 static bool
41758 {
41760 {
41773 }
41774 }
41776 /* Return true if MODE1 is accessible in a register that can hold MODE2
41777 without copying. That is, all register classes that can hold MODE2
41778 can also hold MODE1. */
41780 bool
41782 {
41790 /* MODE2 being XFmode implies fp stack or general regs, which means we
41791 can tie any smaller floating point modes to it. Note that we do not
41792 tie this with TFmode. */
41796 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
41797 that we can tie it with SFmode. */
41801 /* If MODE2 is only appropriate for an SSE register, then tie with
41802 any other mode acceptable to SSE registers. */
41812 /* If MODE2 is appropriate for an MMX register, then tie
41813 with any other mode acceptable to MMX registers. */
41820 }
41822 /* Return the cost of moving between two registers of mode MODE. */
41824 static int
41826 {
41830 {
41862 }
41864 /* Return the cost of moving between two registers of mode MODE,
41865 assuming that the move will be in pieces of at most UNITS bytes. */
41867 }
41869 /* Compute a (partial) cost for rtx X. Return true if the complete
41870 cost has been computed, and false if subexpressions should be
41871 scanned. In either case, *TOTAL contains the cost result. */
41873 static bool
41876 {
41877 rtx mask;
41884 {
41888 {
41891 }
41903 && !(TARGET_64BIT
41908 else
41914 {
41917 }
41919 {
41929 }
41931 {
41934 {
41943 }
41944 }
41945 /* Fall back to (MEM (SYMBOL_REF)), since that's where
41946 it'll probably end up. Add a penalty for size. */
41953 /* The zero extensions is often completely free on x86_64, so make
41954 it as cheap as possible. */
41960 else
41972 {
41975 {
41978 }
41981 {
41984 }
41985 }
41986 /* FALLTHRU */
41993 {
41994 /* ??? Should be SSE vector operation cost. */
41995 /* At least for published AMD latencies, this really is the same
41996 as the latency for a simple fpu operation like fabs. */
41997 /* V*QImode is emulated with 1-11 insns. */
41999 {
42002 {
42003 /* For XOP we use vpshab, which requires a broadcast of the
42004 value to the variable shift insn. For constants this
42005 means a V16Q const in mem; even when we can perform the
42006 shift with one insn set the cost to prefer paddb. */
42008 {
42013 }
42015 }
42019 }
42020 else
42022 }
42024 {
42026 {
42029 else
42031 }
42032 else
42033 {
42036 else
42038 }
42039 }
42040 else
42041 {
42046 {
42047 /* Return the cost after shift-and truncation. */
42050 }
42051 else
42053 }
42057 {
42058 rtx sub;
42063 /* ??? SSE scalar/vector cost should be used here. */
42064 /* ??? Bald assumption that fma has the same cost as fmul. */
42068 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
42079 }
42083 {
42084 /* ??? SSE scalar cost should be used here. */
42087 }
42089 {
42092 }
42094 {
42095 /* ??? SSE vector cost should be used here. */
42098 }
42100 {
42101 /* V*QImode is emulated with 7-13 insns. */
42103 {
42110 }
42111 /* V*DImode is emulated with 5-8 insns. */
42113 {
42116 else
42118 }
42119 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
42120 insns, including two PMULUDQ. */
42123 else
42126 }
42127 else
42128 {
42133 {
42136 nbits++;
42137 }
42138 else
42139 /* This is arbitrary. */
42142 /* Compute costs correctly for widening multiplication. */
42146 {
42153 {
42157 else
42159 }
42163 }
42171 }
42178 /* ??? SSE cost should be used here. */
42183 /* ??? SSE vector cost should be used here. */
42185 else
42192 {
42197 {
42200 {
42208 }
42209 }
42212 {
42215 {
42221 }
42222 }
42224 {
42232 }
42233 }
42234 /* FALLTHRU */
42238 {
42239 /* ??? SSE cost should be used here. */
42242 }
42244 {
42247 }
42249 {
42250 /* ??? SSE vector cost should be used here. */
42253 }
42254 /* FALLTHRU */
42261 {
42268 }
42269 /* FALLTHRU */
42273 {
42274 /* ??? SSE cost should be used here. */
42277 }
42279 {
42282 }
42284 {
42285 /* ??? SSE vector cost should be used here. */
42288 }
42289 /* FALLTHRU */
42293 {
42294 /* ??? Should be SSE vector operation cost. */
42295 /* At least for published AMD latencies, this really is the same
42296 as the latency for a simple fpu operation like fabs. */
42298 }
42301 else
42310 {
42311 /* This kind of construct is implemented using test[bwl].
42312 Treat it as if we had an AND. */
42317 }
42327 /* ??? SSE cost should be used here. */
42332 /* ??? SSE vector cost should be used here. */
42338 /* ??? SSE cost should be used here. */
42343 /* ??? SSE vector cost should be used here. */
42355 /* ??? Assume all of these vector manipulation patterns are
42356 recognizable. In which case they all pretty much have the
42357 same cost. */
42362 /* This is masked instruction, assume the same cost,
42363 as nonmasked variant. */
42366 else
42372 }
42373 }
42375 #if TARGET_MACHO
42379 /* Given a symbol name and its associated stub, write out the
42380 definition of the stub. */
42382 void
42384 {
42389 /* For 64-bit we shouldn't get here. */
42392 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
42409 else
42416 {
42418 }
42420 {
42421 /* PIC stub. */
42422 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42428 }
42429 else
42432 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
42433 it needs no stub-binding-helper. */
42440 {
42443 }
42444 else
42449 /* N.B. Keep the correspondence of these
42450 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
42451 old-pic/new-pic/non-pic stubs; altering this will break
42452 compatibility with existing dylibs. */
42454 {
42455 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42457 }
42458 else
42459 /* 16-byte -mdynamic-no-pic stub. */
42465 }
42468 /* Order the registers for register allocator. */
42470 void
42472 {
42476 /* First allocate the local general purpose registers. */
42481 /* Global general purpose registers. */
42486 /* x87 registers come first in case we are doing FP math
42487 using them. */
42492 /* SSE registers. */
42498 /* Extended REX SSE registers. */
42502 /* Mask register. */
42506 /* MPX bound registers. */
42510 /* x87 registers. */
42518 /* Initialize the rest of array as we do not allocate some registers
42519 at all. */
42522 }
42524 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
42525 in struct attribute_spec handler. */
42526 static tree
42528 tree args,
42531 {
42536 {
42538 name);
42541 }
42543 {
42545 name);
42548 }
42550 {
42551 tree cst;
42555 {
42558 name);
42560 }
42563 {
42566 name);
42568 }
42571 }
42574 }
42576 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
42577 struct attribute_spec.handler. */
42578 static tree
42581 {
42586 {
42588 name);
42591 }
42593 /* Can combine regparm with all attributes but fastcall. */
42595 {
42597 {
42599 }
42602 }
42604 {
42606 {
42608 }
42611 }
42614 }
42616 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
42617 struct attribute_spec.handler. */
42618 static tree
42621 {
42624 {
42627 }
42628 else
42632 {
42634 name);
42636 }
42642 {
42644 name);
42646 }
42649 }
42651 static tree
42654 {
42656 {
42658 name);
42660 }
42662 }
42664 static bool
42666 {
42670 }
42672 /* Returns an expression indicating where the this parameter is
42673 located on entry to the FUNCTION. */
42675 static rtx
42677 {
42683 {
42688 else
42691 }
42696 {
42703 {
42708 }
42709 else
42710 {
42713 {
42719 }
42720 }
42722 }
42726 }
42728 /* Determine whether x86_output_mi_thunk can succeed. */
42730 static bool
42732 const_tree function)
42733 {
42734 /* 64-bit can handle anything. */
42738 /* For 32-bit, everything's fine if we have one free register. */
42742 /* Need a free register for vcall_offset. */
42746 /* Need a free register for GOT references. */
42750 /* Otherwise ok. */
42752 }
42754 /* Output the assembler code for a thunk function. THUNK_DECL is the
42755 declaration for the thunk function itself, FUNCTION is the decl for
42756 the target function. DELTA is an immediate constant offset to be
42757 added to THIS. If VCALL_OFFSET is nonzero, the word at
42758 *(*this + vcall_offset) should be added to THIS. */
42760 static void
42763 {
42771 else
42772 {
42778 else
42780 }
42784 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
42785 pull it in now and let DELTA benefit. */
42789 {
42790 /* Put the this parameter into %eax. */
42793 }
42794 else
42797 /* Adjust the this parameter by a fixed constant. */
42799 {
42804 {
42806 {
42810 }
42811 }
42814 }
42816 /* Adjust the this parameter by a value stored in the vtable. */
42818 {
42828 /* Adjust the this parameter. */
42832 {
42836 }
42843 vcall_mem));
42844 else
42846 }
42848 /* If necessary, drop THIS back to its stack slot. */
42854 {
42857 ;
42858 else
42859 {
42863 }
42864 }
42865 else
42866 {
42868 ;
42869 #if TARGET_MACHO
42871 {
42874 }
42876 else
42877 {
42885 }
42886 }
42888 /* Our sibling call patterns do not allow memories, because we have no
42889 predicate that can distinguish between frame and non-frame memory.
42890 For our purposes here, we can get away with (ab)using a jump pattern,
42891 because we're going to do no optimization. */
42893 {
42895 {
42901 }
42902 else
42904 }
42905 else
42906 {
42908 {
42909 // CM_LARGE_PIC always uses pseudo PIC register which is
42910 // uninitialized. Since FUNCTION is local and calling it
42911 // doesn't go through PLT, we use scratch register %r11 as
42912 // PIC register and initialize it here.
42917 }
42920 {
42926 }
42932 }
42935 /* Emit just enough of rest_of_compilation to get the insns emitted.
42936 Note that use_thunk calls assemble_start_function et al. */
42942 }
42944 static void
42946 {
42950 #if TARGET_MACHO
42952 #endif
42959 }
42961 int
42963 {
42964 machine_mode mode;
42975 }
42977 /* Print call to TARGET to FILE. */
42979 static void
42981 {
42984 else
42986 }
42988 /* Output assembler code to FILE to increment profiler label # LABELNO
42989 for profiling a function entry. */
42990 void
42992 {
42996 {
42997 #ifndef NO_PROFILE_COUNTERS
42999 #endif
43003 else
43005 }
43007 {
43008 #ifndef NO_PROFILE_COUNTERS
43011 #endif
43013 }
43014 else
43015 {
43016 #ifndef NO_PROFILE_COUNTERS
43019 #endif
43021 }
43024 {
43028 }
43029 }
43031 /* We don't have exact information about the insn sizes, but we may assume
43032 quite safely that we are informed about all 1 byte insns and memory
43033 address sizes. This is enough to eliminate unnecessary padding in
43034 99% of cases. */
43036 static int
43038 {
43044 /* Discard alignments we've emit and jump instructions. */
43049 /* Important case - calls are always 5 bytes.
43050 It is common to have many calls in the row. */
43059 /* For normal instructions we rely on get_attr_length being exact,
43060 with a few exceptions. */
43062 {
43066 {
43076 /* Otherwise trust get_attr_length. */
43078 }
43083 }
43086 else
43088 }
43090 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43092 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
43093 window. */
43095 static void
43097 {
43102 /* Look for all minimal intervals of instructions containing 4 jumps.
43103 The intervals are bounded by START and INSN. NBYTES is the total
43104 size of instructions in the interval including INSN and not including
43105 START. When the NBYTES is smaller than 16 bytes, it is possible
43106 that the end of START and INSN ends up in the same 16byte page.
43108 The smallest offset in the page INSN can start is the case where START
43109 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
43110 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
43112 Don't consider asm goto as jump, while it can contain a jump, it doesn't
43113 have to, control transfer to label(s) can be performed through other
43114 means, and also we estimate minimum length of all asm stmts as 0. */
43116 {
43120 {
43126 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
43127 already in the current 16 byte page, because otherwise
43128 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
43129 bytes to reach 16 byte boundary. */
43137 {
43139 {
43144 else
43147 }
43148 }
43150 }
43159 njumps++;
43160 else
43164 {
43169 else
43172 }
43179 {
43186 }
43187 }
43188 }
43189 #endif
43191 /* AMD Athlon works faster
43192 when RET is not destination of conditional jump or directly preceded
43193 by other jump instruction. We avoid the penalty by inserting NOP just
43194 before the RET instructions in such cases. */
43195 static void
43197 {
43198 edge e;
43199 edge_iterator ei;
43202 {
43215 {
43216 edge e;
43217 edge_iterator ei;
43222 {
43225 }
43226 }
43228 {
43234 /* Empty functions get branch mispredict even when
43235 the jump destination is not visible to us. */
43238 }
43240 {
43243 }
43244 }
43245 }
43247 /* Count the minimum number of instructions in BB. Return 4 if the
43248 number of instructions >= 4. */
43250 static int
43252 {
43256 /* Count number of instructions in this block. Return 4 if the number
43257 of instructions >= 4. */
43259 {
43260 /* Only happen in exit blocks. */
43268 {
43269 insn_count++;
43272 }
43273 }
43276 }
43279 /* Count the minimum number of instructions in code path in BB.
43280 Return 4 if the number of instructions >= 4. */
43282 static int
43284 {
43285 edge e;
43286 edge_iterator ei;
43289 /* Only bother counting instructions along paths with no
43290 more than 2 basic blocks between entry and exit. Given
43291 that BB has an edge to exit, determine if a predecessor
43292 of BB has an edge from entry. If so, compute the number
43293 of instructions in the predecessor block. If there
43294 happen to be multiple such blocks, compute the minimum. */
43297 {
43298 edge prev_e;
43299 edge_iterator prev_ei;
43302 {
43305 }
43307 {
43309 {
43314 }
43315 }
43316 }
43322 }
43324 /* Pad short function to 4 instructions. */
43326 static void
43328 {
43329 edge e;
43330 edge_iterator ei;
43333 {
43336 {
43339 /* Pad short function. */
43341 {
43344 /* Find epilogue. */
43353 /* Two NOPs count as one instruction. */
43356 }
43357 }
43358 }
43359 }
43361 /* Fix up a Windows system unwinder issue. If an EH region falls through into
43362 the epilogue, the Windows system unwinder will apply epilogue logic and
43363 produce incorrect offsets. This can be avoided by adding a nop between
43364 the last insn that can throw and the first insn of the epilogue. */
43366 static void
43368 {
43369 edge e;
43370 edge_iterator ei;
43373 {
43376 /* Find the beginning of the epilogue. */
43383 /* We only care about preceding insns that can throw. */
43388 /* Do not separate calls from their debug information. */
43394 else
43398 }
43399 }
43401 /* Implement machine specific optimizations. We implement padding of returns
43402 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
43403 static void
43405 {
43406 /* We are freeing block_for_insn in the toplev to keep compatibility
43407 with old MDEP_REORGS that are not CFG based. Recompute it now. */
43414 {
43419 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43422 #endif
43423 }
43424 }
43426 /* Return nonzero when QImode register that must be represented via REX prefix
43427 is used. */
43428 bool
43430 {
43438 }
43440 /* Return true when INSN mentions register that must be encoded using REX
43441 prefix. */
43442 bool
43444 {
43447 {
43452 }
43454 }
43456 /* If profitable, negate (without causing overflow) integer constant
43457 of mode MODE at location LOC. Return true in this case. */
43458 bool
43460 {
43461 HOST_WIDE_INT val;
43467 {
43469 /* DImode x86_64 constants must fit in 32 bits. */
43482 }
43484 /* Avoid overflows. */
43490 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
43491 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
43494 {
43497 }
43500 }
43502 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
43503 optabs would emit if we didn't have TFmode patterns. */
43505 void
43507 {
43542 }
43543 \f
43549 /* Get a vector mode of the same size as the original but with elements
43550 twice as wide. This is only guaranteed to apply to integral vectors. */
43554 {
43555 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
43560 }
43562 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
43563 fill target with val via vec_duplicate. */
43565 static bool
43567 {
43570 rtx dup;
43572 /* First attempt to recognize VAL as-is. */
43576 {
43578 /* If that fails, force VAL into a register. */
43589 }
43591 }
43593 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43594 with all elements equal to VAR. Return true if successful. */
43596 static bool
43599 {
43603 {
43608 /* FALLTHRU */
43628 {
43629 rtx x;
43636 }
43649 {
43653 permute:
43661 /* Extend to SImode using a paradoxical SUBREG. */
43665 /* Insert the SImode value as low element of a V4SImode vector. */
43674 }
43685 widen:
43686 /* Replicate the value once into the next wider mode and recurse. */
43687 {
43689 rtx x;
43706 }
43712 else
43713 {
43722 }
43729 else
43730 {
43739 }
43744 }
43745 }
43747 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43748 whose ONE_VAR element is VAR, and other elements are zero. Return true
43749 if successful. */
43751 static bool
43754 {
43755 machine_mode vsimode;
43756 rtx new_target;
43761 {
43763 /* For SSE4.1, we normally use vector set. But if the second
43764 element is zero and inter-unit moves are OK, we use movq
43765 instead. */
43767 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
43789 /* Use ix86_expand_vector_set in 64bit mode only. */
43794 }
43797 {
43802 }
43805 {
43810 /* FALLTHRU */
43825 else
43832 {
43833 /* We need to shuffle the value to the correct position, so
43834 create a new pseudo to store the intermediate result. */
43836 /* With SSE2, we can use the integer shuffle insns. */
43838 {
43840 const1_rtx,
43847 }
43849 /* Otherwise convert the intermediate result to V4SFmode and
43850 use the SSE1 shuffle instructions. */
43852 {
43855 }
43856 else
43860 const1_rtx,
43869 }
43884 widen:
43888 /* Zero extend the variable element to SImode and recurse. */
43901 }
43902 }
43904 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43905 consisting of the values in VALS. It is known that all elements
43906 except ONE_VAR are constants. Return true if successful. */
43908 static bool
43911 {
43913 machine_mode wmode;
43921 {
43926 /* For the two element vectors, it's just as easy to use
43927 the general case. */
43931 /* Use ix86_expand_vector_set in 64bit mode only. */
43953 widen:
43954 /* There's no way to set one QImode entry easily. Combine
43955 the variable value with its adjacent constant value, and
43956 promote to an HImode set. */
43959 {
43964 }
43965 else
43966 {
43969 }
43983 }
43988 }
43990 /* A subroutine of ix86_expand_vector_init_general. Use vector
43991 concatenate to handle the most general case: all values variable,
43992 and none identical. */
43994 static void
43997 {
44000 rtvec v;
44004 {
44007 {
44052 }
44065 {
44080 }
44085 {
44104 }
44109 {
44122 }
44125 half:
44126 /* FIXME: We process inputs backward to help RA. PR 36222. */
44130 {
44135 }
44139 {
44143 {
44147 }
44150 {
44154 }
44157 }
44159 {
44162 {
44166 }
44169 }
44170 else
44176 }
44177 }
44179 /* A subroutine of ix86_expand_vector_init_general. Use vector
44180 interleave to handle the most general case: all values variable,
44181 and none identical. */
44183 static void
44186 {
44195 {
44216 }
44219 {
44220 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
44224 /* Insert the SImode value as low element of V4SImode vector. */
44228 op0),
44230 const1_rtx);
44233 /* Cast the V4SImode vector back to a vector in orignal mode. */
44237 /* Load even elements into the second position. */
44241 const1_rtx));
44243 /* Cast vector to FIRST_IMODE vector. */
44246 }
44248 /* Interleave low FIRST_IMODE vectors. */
44250 {
44254 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
44257 }
44259 /* Interleave low SECOND_IMODE vectors. */
44261 {
44264 {
44269 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
44270 vector. */
44273 }
44276 /* FALLTHRU */
44283 /* Cast the SECOND_IMODE vector back to a vector on original
44284 mode. */
44291 }
44292 }
44294 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
44295 all values variable, and none identical. */
44297 static void
44300 {
44307 {
44312 /* FALLTHRU */
44340 half:
44364 quarter:
44393 /* FALLTHRU */
44399 /* Don't use ix86_expand_vector_init_interleave if we can't
44400 move from GPR to SSE register directly. */
44416 }
44418 {
44420 machine_mode inner_mode;
44430 {
44434 {
44440 else
44441 {
44446 }
44447 }
44450 }
44455 {
44461 }
44463 {
44469 }
44470 else
44472 }
44473 }
44475 /* Initialize vector TARGET via VALS. Suppress the use of MMX
44476 instructions unless MMX_OK is true. */
44478 void
44480 {
44487 rtx x;
44490 {
44500 }
44502 /* Constants are best loaded from the constant pool. */
44504 {
44507 }
44509 /* If all values are identical, broadcast the value. */
44515 /* Values where only one field is non-constant are best loaded from
44516 the pool and overwritten via move later. */
44518 {
44522 one_var))
44527 }
44530 }
44532 void
44534 {
44537 machine_mode half_mode;
44539 rtx tmp;
44541 = {
44548 };
44550 = {
44557 };
44561 {
44565 {
44570 else
44574 }
44586 else
44592 {
44595 /* For the two element vectors, we implement a VEC_CONCAT with
44596 the extraction of the other element. */
44603 else
44608 }
44617 {
44623 /* tmp = target = A B C D */
44625 /* target = A A B B */
44627 /* target = X A B B */
44629 /* target = A X C D */
44636 /* tmp = target = A B C D */
44638 /* tmp = X B C D */
44640 /* target = A B X D */
44647 /* tmp = target = A B C D */
44649 /* tmp = X B C D */
44651 /* target = A B X D */
44659 }
44667 /* Element 0 handled by vec_merge below. */
44669 {
44672 }
44675 {
44676 /* With SSE2, use integer shuffles to swap element 0 and ELT,
44677 store into element 0, then shuffle them back. */
44694 }
44695 else
44696 {
44697 /* For SSE1, we have to reuse the V4SF code. */
44701 }
44754 half:
44755 /* Compute offset. */
44761 /* Extract the half. */
44765 /* Put val in tmp at elt. */
44768 /* Put it back. */
44774 {
44781 }
44782 else
44786 {
44793 }
44794 else
44798 {
44805 }
44806 else
44810 {
44817 }
44818 else
44822 {
44829 }
44830 else
44834 {
44841 }
44842 else
44847 }
44850 {
44854 }
44855 else
44856 {
44865 }
44866 }
44868 void
44870 {
44874 rtx tmp;
44877 {
44882 /* FALLTHRU */
44895 {
44915 }
44927 {
44929 {
44949 }
44953 }
44954 else
44955 {
44956 /* For SSE1, we have to reuse the V4SF code. */
44960 }
44976 {
44980 else
44984 }
44989 {
44993 else
44997 }
45002 {
45006 else
45010 }
45015 {
45019 else
45023 }
45028 {
45032 else
45036 }
45041 {
45045 else
45049 }
45054 {
45058 else
45062 }
45067 {
45071 else
45075 }
45082 else
45091 else
45100 else
45109 else
45115 /* ??? Could extract the appropriate HImode element and shift. */
45118 }
45121 {
45125 /* Let the rtl optimizers know about the zero extension performed. */
45127 {
45130 }
45133 }
45134 else
45135 {
45142 }
45143 }
45145 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
45146 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
45147 The upper bits of DEST are undefined, though they shouldn't cause
45148 exceptions (some bits from src or all zeros are ok). */
45150 static void
45152 {
45155 {
45159 else
45177 else
45184 else
45192 {
45197 const1_rtx);
45198 }
45199 else
45200 {
45204 }
45226 else
45248 }
45252 }
45254 /* Expand a vector reduction. FN is the binary pattern to reduce;
45255 DEST is the destination; IN is the input vector. */
45257 void
45259 {
45264 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
45268 {
45271 }
45276 {
45281 else
45285 }
45286 }
45287 \f
45288 /* Target hook for scalar_mode_supported_p. */
45289 static bool
45291 {
45296 else
45298 }
45300 /* Implements target hook vector_mode_supported_p. */
45301 static bool
45303 {
45317 }
45319 /* Implement target hook libgcc_floating_mode_supported_p. */
45320 static bool
45322 {
45324 {
45331 #ifdef IX86_NO_LIBGCC_TFMODE
45333 #elif defined IX86_MAYBE_NO_LIBGCC_TFMODE
45335 #else
45337 #endif
45341 }
45342 }
45344 /* Target hook for c_mode_for_suffix. */
45345 static machine_mode
45347 {
45354 }
45356 /* Worker function for TARGET_MD_ASM_CLOBBERS.
45358 We do this in the new i386 backend to maintain source compatibility
45359 with the old cc0-based compiler. */
45361 static tree
45363 {
45365 clobbers);
45367 clobbers);
45369 }
45371 /* Implements target vector targetm.asm.encode_section_info. */
45373 static void ATTRIBUTE_UNUSED
45375 {
45380 }
45382 /* Worker function for REVERSE_CONDITION. */
45384 enum rtx_code
45386 {
45390 }
45392 /* Output code to perform an x87 FP register move, from OPERANDS[1]
45393 to OPERANDS[0]. */
45397 {
45399 {
45402 {
45406 }
45410 }
45412 {
45416 else
45417 {
45418 /* There is no non-popping store to memory for XFmode.
45419 So if we need one, follow the store with a load. */
45422 else
45424 }
45425 }
45426 else
45428 }
45430 /* Output code to perform a conditional jump to LABEL, if C2 flag in
45431 FP status register is set. */
45433 void
45435 {
45437 rtx temp;
45442 {
45447 }
45448 else
45449 {
45454 }
45458 pc_rtx);
45463 }
45465 /* Output code to perform a log1p XFmode calculation. */
45468 {
45474 rtx test;
45480 XFmode));
45494 }
45496 /* Emit code for round calculation. */
45498 {
45505 rtx insn;
45510 {
45522 }
45525 {
45546 }
45554 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
45556 /* scratch = fxam(op1) */
45559 UNSPEC_FXAM)));
45560 /* e1 = fabs(op1) */
45563 /* e2 = e1 + 0.5 */
45568 /* res = floor(e2) */
45570 {
45575 }
45576 else
45580 {
45583 {
45590 UNSPEC_TRUNC_NOOP)));
45591 }
45607 }
45609 /* flags = signbit(a) */
45612 /* if (flags) then res = -res */
45616 pc_rtx);
45627 }
45629 /* Output code to perform a Newton-Rhapson approximation of a single precision
45630 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
45633 {
45641 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
45645 /* x0 = rcp(b) estimate */
45649 UNSPEC_RCP14)));
45650 else
45653 UNSPEC_RCP)));
45655 /* e0 = x0 * b */
45659 /* e0 = x0 * e0 */
45663 /* e1 = x0 + x0 */
45667 /* x1 = e1 - e0 */
45671 /* res = a * x1 */
45674 }
45676 /* Output code to perform a Newton-Rhapson approximation of a
45677 single precision floating point [reciprocal] square root. */
45681 {
45683 REAL_VALUE_TYPE r;
45700 {
45703 /* There is no 512-bit rsqrt. There is however rsqrt14. */
45706 }
45708 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
45709 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
45713 /* x0 = rsqrt(a) estimate */
45716 unspec)));
45718 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
45720 {
45728 /* Handle masked compare. */
45730 {
45732 /* Imm value 0x4 corresponds to not-equal comparison. */
45735 }
45736 else
45737 {
45743 }
45744 }
45746 /* e0 = x0 * a */
45749 /* e1 = e0 * x0 */
45753 /* e2 = e1 - 3. */
45760 /* e3 = -.5 * x0 */
45763 else
45764 /* e3 = -.5 * e0 */
45767 /* ret = e2 * e3 */
45770 }
45772 #ifdef TARGET_SOLARIS
45773 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
45775 static void
45777 tree decl)
45778 {
45779 /* With Binutils 2.15, the "@unwind" marker must be specified on
45780 every occurrence of the ".eh_frame" section, not just the first
45781 one. */
45784 {
45788 }
45790 #ifndef USE_GAS
45792 {
45795 }
45796 #endif
45799 }
45802 /* Return the mangling of TYPE if it is an extended fundamental type. */
45806 {
45814 {
45816 /* __float128 is "g". */
45819 /* "long double" or __float80 is "e". */
45823 }
45824 }
45826 /* For 32-bit code we can save PIC register setup by using
45827 __stack_chk_fail_local hidden function instead of calling
45828 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
45829 register, so it is better to call __stack_chk_fail directly. */
45831 static tree ATTRIBUTE_UNUSED
45833 {
45834 return TARGET_64BIT
45837 }
45839 /* Select a format to encode pointers in exception handling data. CODE
45840 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
45841 true if the symbol may be affected by dynamic relocations.
45843 ??? All x86 object file formats are capable of representing this.
45844 After all, the relocation needed is the same as for the call insn.
45845 Whether or not a particular assembler allows us to enter such, I
45846 guess we'll have to see. */
45847 int
45849 {
45851 {
45858 }
45863 }
45864 \f
45865 /* Expand copysign from SIGN to the positive value ABS_VALUE
45866 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
45867 the sign-bit. */
45868 static void
45870 {
45874 {
45875 machine_mode vmode;
45881 else
45886 {
45887 /* We need to generate a scalar mode mask in this case. */
45892 }
45893 }
45894 else
45900 }
45902 /* Expand fabs (OP0) and return a new rtx that holds the result. The
45903 mask for masking out the sign-bit is stored in *SMASK, if that is
45904 non-null. */
45905 static rtx
45907 {
45916 else
45920 {
45921 /* We need to generate a scalar mode mask in this case. */
45926 }
45934 }
45936 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
45937 swapping the operands if SWAP_OPERANDS is true. The expanded
45938 code is a forward jump to a newly created label in case the
45939 comparison is true. The generated label rtx is returned. */
45943 {
45946 rtx tmp;
45962 }
45964 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
45965 using comparison code CODE. Operands are swapped for the comparison if
45966 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
45967 static rtx
45970 {
45983 }
45985 /* Generate and return a rtx of mode MODE for 2**n where n is the number
45986 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
45987 static rtx
45989 {
45990 REAL_VALUE_TYPE TWO52r;
45991 rtx TWO52;
45998 }
46000 /* Expand SSE sequence for computing lround from OP1 storing
46001 into OP0. */
46002 void
46004 {
46005 /* C code for the stuff we're doing below:
46006 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
46007 return (long)tmp;
46008 */
46012 rtx adj;
46014 /* load nextafter (0.5, 0.0) */
46019 /* adj = copysign (0.5, op1) */
46023 /* adj = op1 + adj */
46026 /* op0 = (imode)adj */
46028 }
46030 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
46031 into OPERAND0. */
46032 void
46034 {
46035 /* C code for the stuff we're doing below (for do_floor):
46036 xi = (long)op1;
46037 xi -= (double)xi > op1 ? 1 : 0;
46038 return xi;
46039 */
46045 /* reg = (long)op1 */
46049 /* freg = (double)reg */
46053 /* ireg = (freg > op1) ? ireg - 1 : ireg */
46064 }
46066 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
46067 result in OPERAND0. */
46068 void
46070 {
46071 /* C code for the stuff we're doing below:
46072 xa = fabs (operand1);
46073 if (!isless (xa, 2**52))
46074 return operand1;
46075 xa = xa + 2**52 - 2**52;
46076 return copysign (xa, operand1);
46077 */
46085 /* xa = abs (operand1) */
46088 /* if (!isless (xa, TWO52)) goto label; */
46101 }
46103 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46104 into OPERAND0. */
46105 void
46107 {
46108 /* C code for the stuff we expand below.
46109 double xa = fabs (x), x2;
46110 if (!isless (xa, TWO52))
46111 return x;
46112 xa = xa + TWO52 - TWO52;
46113 x2 = copysign (xa, x);
46114 Compensate. Floor:
46115 if (x2 > x)
46116 x2 -= 1;
46117 Compensate. Ceil:
46118 if (x2 < x)
46119 x2 -= -1;
46120 return x2;
46121 */
46128 /* Temporary for holding the result, initialized to the input
46129 operand to ease control flow. */
46133 /* xa = abs (operand1) */
46136 /* if (!isless (xa, TWO52)) goto label; */
46139 /* xa = xa + TWO52 - TWO52; */
46143 /* xa = copysign (xa, operand1) */
46146 /* generate 1.0 or -1.0 */
46151 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46155 /* We always need to subtract here to preserve signed zero. */
46164 }
46166 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46167 into OPERAND0. */
46168 void
46170 {
46171 /* C code for the stuff we expand below.
46172 double xa = fabs (x), x2;
46173 if (!isless (xa, TWO52))
46174 return x;
46175 x2 = (double)(long)x;
46176 Compensate. Floor:
46177 if (x2 > x)
46178 x2 -= 1;
46179 Compensate. Ceil:
46180 if (x2 < x)
46181 x2 += 1;
46182 if (HONOR_SIGNED_ZEROS (mode))
46183 return copysign (x2, x);
46184 return x2;
46185 */
46192 /* Temporary for holding the result, initialized to the input
46193 operand to ease control flow. */
46197 /* xa = abs (operand1) */
46200 /* if (!isless (xa, TWO52)) goto label; */
46203 /* xa = (double)(long)x */
46208 /* generate 1.0 */
46211 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46226 }
46228 /* Expand SSE sequence for computing round from OPERAND1 storing
46229 into OPERAND0. Sequence that works without relying on DImode truncation
46230 via cvttsd2siq that is only available on 64bit targets. */
46231 void
46233 {
46234 /* C code for the stuff we expand below.
46235 double xa = fabs (x), xa2, x2;
46236 if (!isless (xa, TWO52))
46237 return x;
46238 Using the absolute value and copying back sign makes
46239 -0.0 -> -0.0 correct.
46240 xa2 = xa + TWO52 - TWO52;
46241 Compensate.
46242 dxa = xa2 - xa;
46243 if (dxa <= -0.5)
46244 xa2 += 1;
46245 else if (dxa > 0.5)
46246 xa2 -= 1;
46247 x2 = copysign (xa2, x);
46248 return x2;
46249 */
46256 /* Temporary for holding the result, initialized to the input
46257 operand to ease control flow. */
46261 /* xa = abs (operand1) */
46264 /* if (!isless (xa, TWO52)) goto label; */
46267 /* xa2 = xa + TWO52 - TWO52; */
46271 /* dxa = xa2 - xa; */
46274 /* generate 0.5, 1.0 and -0.5 */
46280 /* Compensate. */
46282 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
46287 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
46293 /* res = copysign (xa2, operand1) */
46300 }
46302 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46303 into OPERAND0. */
46304 void
46306 {
46307 /* C code for SSE variant we expand below.
46308 double xa = fabs (x), x2;
46309 if (!isless (xa, TWO52))
46310 return x;
46311 x2 = (double)(long)x;
46312 if (HONOR_SIGNED_ZEROS (mode))
46313 return copysign (x2, x);
46314 return x2;
46315 */
46322 /* Temporary for holding the result, initialized to the input
46323 operand to ease control flow. */
46327 /* xa = abs (operand1) */
46330 /* if (!isless (xa, TWO52)) goto label; */
46333 /* x = (double)(long)x */
46345 }
46347 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46348 into OPERAND0. */
46349 void
46351 {
46356 /* C code for SSE variant we expand below.
46357 double xa = fabs (x), x2;
46358 if (!isless (xa, TWO52))
46359 return x;
46360 xa2 = xa + TWO52 - TWO52;
46361 Compensate:
46362 if (xa2 > xa)
46363 xa2 -= 1.0;
46364 x2 = copysign (xa2, x);
46365 return x2;
46366 */
46370 /* Temporary for holding the result, initialized to the input
46371 operand to ease control flow. */
46375 /* xa = abs (operand1) */
46378 /* if (!isless (xa, TWO52)) goto label; */
46381 /* res = xa + TWO52 - TWO52; */
46386 /* generate 1.0 */
46389 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
46397 /* res = copysign (res, operand1) */
46404 }
46406 /* Expand SSE sequence for computing round from OPERAND1 storing
46407 into OPERAND0. */
46408 void
46410 {
46411 /* C code for the stuff we're doing below:
46412 double xa = fabs (x);
46413 if (!isless (xa, TWO52))
46414 return x;
46415 xa = (double)(long)(xa + nextafter (0.5, 0.0));
46416 return copysign (xa, x);
46417 */
46424 /* Temporary for holding the result, initialized to the input
46425 operand to ease control flow. */
46433 /* load nextafter (0.5, 0.0) */
46438 /* xa = xa + 0.5 */
46442 /* xa = (double)(int64_t)xa */
46447 /* res = copysign (xa, operand1) */
46454 }
46456 /* Expand SSE sequence for computing round
46457 from OP1 storing into OP0 using sse4 round insn. */
46458 void
46460 {
46469 {
46480 }
46482 /* round (a) = trunc (a + copysign (0.5, a)) */
46484 /* load nextafter (0.5, 0.0) */
46490 /* e1 = copysign (0.5, op1) */
46494 /* e2 = op1 + e1 */
46497 /* res = trunc (e2) */
46502 }
46503 \f
46505 /* Table of valid machine attributes. */
46507 {
46508 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
46509 affects_type_identity } */
46510 /* Stdcall attribute says callee is responsible for popping arguments
46511 if they are not variable. */
46514 /* Fastcall attribute says callee is responsible for popping arguments
46515 if they are not variable. */
46518 /* Thiscall attribute says callee is responsible for popping arguments
46519 if they are not variable. */
46522 /* Cdecl attribute says the callee is a normal C declaration */
46525 /* Regparm attribute specifies how many integer arguments are to be
46526 passed in registers. */
46529 /* Sseregparm attribute says we are using x86_64 calling conventions
46530 for FP arguments. */
46533 /* The transactional memory builtins are implicitly regparm or fastcall
46534 depending on the ABI. Override the generic do-nothing attribute that
46535 these builtins were declared with. */
46538 /* force_align_arg_pointer says this function realigns the stack at entry. */
46541 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46546 #endif
46551 #ifdef SUBTARGET_ATTRIBUTE_TABLE
46552 SUBTARGET_ATTRIBUTE_TABLE,
46553 #endif
46554 /* ms_abi and sysv_abi calling convention function attributes. */
46561 /* End element. */
46563 };
46565 /* Implement targetm.vectorize.builtin_vectorization_cost. */
46566 static int
46569 {
46573 {
46618 }
46619 }
46621 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
46622 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
46623 insn every time. */
46627 /* Initialize vselect_insn. */
46629 static void
46631 {
46633 rtx x;
46644 }
46646 /* Construct (set target (vec_select op0 (parallel perm))) and
46647 return true if that's a valid instruction in the active ISA. */
46649 static bool
46652 {
46678 }
46680 /* Similar, but generate a vec_concat from op0 and op1 as well. */
46682 static bool
46686 {
46687 machine_mode v2mode;
46688 rtx x;
46703 }
46705 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46706 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
46708 static bool
46710 {
46720 ;
46722 ;
46724 ;
46726 ;
46727 else
46730 /* This is a blend, not a permute. Elements must stay in their
46731 respective lanes. */
46733 {
46737 }
46742 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
46743 decision should be extracted elsewhere, so that we only try that
46744 sequence once all budget==3 options have been tried. */
46751 {
46781 /* See if bytes move in pairs so we can use pblendw with
46782 an immediate argument, rather than pblendvb with a vector
46783 argument. */
46786 {
46787 use_pblendvb:
46791 finish_pblendvb:
46797 else
46802 }
46807 /* FALLTHRU */
46809 do_subreg:
46816 /* See if bytes move in pairs. If not, vpblendvb must be used. */
46820 /* See if bytes move in quadruplets. If yes, vpblendd
46821 with immediate can be used. */
46826 {
46827 /* See if bytes move the same in both lanes. If yes,
46828 vpblendw with immediate can be used. */
46833 /* Use vpblendw. */
46838 }
46840 /* Use vpblendd. */
46847 /* See if words move in pairs. If yes, vpblendd can be used. */
46852 {
46853 /* See if words move the same in both lanes. If not,
46854 vpblendvb must be used. */
46857 {
46858 /* Use vpblendvb. */
46868 }
46870 /* Use vpblendw. */
46874 }
46876 /* Use vpblendd. */
46883 /* Use vpblendd. */
46891 }
46893 /* This matches five different patterns with the different modes. */
46901 }
46903 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46904 in terms of the variable form of vpermilps.
46906 Note that we will have already failed the immediate input vpermilps,
46907 which requires that the high and low part shuffle be identical; the
46908 variable form doesn't require that. */
46910 static bool
46912 {
46919 /* We can only permute within the 128-bit lane. */
46921 {
46925 }
46931 {
46934 /* Within each 128-bit lane, the elements of op0 are numbered
46935 from 0 and the elements of op1 are numbered from 4. */
46942 }
46949 }
46951 /* Return true if permutation D can be performed as VMODE permutation
46952 instead. */
46954 static bool
46956 {
46971 else
46977 }
46979 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46980 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
46982 static bool
46984 {
46993 {
46995 {
46998 {
47002 /* Use vperm2i128 insn. The pattern uses
47003 V4DImode instead of V2TImode. */
47016 }
47018 }
47019 }
47020 else
47021 {
47023 {
47026 }
47028 {
47032 /* V4DImode should be already handled through
47033 expand_vselect by vpermq instruction. */
47040 {
47041 /* First see if vpermq can be used for
47042 V8SImode/V16HImode/V32QImode. */
47044 {
47052 {
47056 }
47058 }
47060 /* Next see if vpermd can be used. */
47063 }
47064 /* Or if vpermps can be used. */
47069 {
47070 /* vpshufb only works intra lanes, it is not
47071 possible to shuffle bytes in between the lanes. */
47075 }
47076 }
47078 {
47082 /* If vpermq didn't work, vpshufb won't work either. */
47090 {
47091 /* First see if vpermq can be used for
47092 V16SImode/V32HImode/V64QImode. */
47094 {
47102 {
47106 }
47108 }
47110 /* Next see if vpermd can be used. */
47113 }
47114 /* Or if vpermps can be used. */
47118 {
47119 /* vpshufb only works intra lanes, it is not
47120 possible to shuffle bytes in between the lanes. */
47124 }
47125 }
47126 else
47128 }
47139 else
47140 {
47148 else
47152 {
47156 }
47157 }
47168 {
47183 else
47185 }
47186 else
47187 {
47190 }
47195 }
47197 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
47198 in a single instruction. */
47200 static bool
47202 {
47206 /* Check plain VEC_SELECT first, because AVX has instructions that could
47207 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
47208 input where SEL+CONCAT may not. */
47210 {
47216 {
47222 }
47225 {
47229 }
47231 {
47232 /* Use vpbroadcast{b,w,d}. */
47235 {
47278 /* For other modes prefer other shuffles this function creates. */
47280 }
47282 {
47286 }
47287 }
47292 /* There are plenty of patterns in sse.md that are written for
47293 SEL+CONCAT and are not replicated for a single op. Perhaps
47294 that should be changed, to avoid the nastiness here. */
47296 /* Recognize interleave style patterns, which means incrementing
47297 every other permutation operand. */
47299 {
47302 }
47307 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
47309 {
47311 {
47316 }
47321 }
47322 }
47324 /* Finally, try the fully general two operand permute. */
47329 /* Recognize interleave style patterns with reversed operands. */
47331 {
47333 {
47337 else
47340 }
47345 }
47347 /* Try the SSE4.1 blend variable merge instructions. */
47351 /* Try one of the AVX vpermil variable permutations. */
47355 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
47356 vpshufb, vpermd, vpermps or vpermq variable permutation. */
47360 /* Try the AVX2 vpalignr instruction. */
47364 /* Try the AVX512F vpermi2 instructions. */
47369 }
47371 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47372 in terms of a pair of pshuflw + pshufhw instructions. */
47374 static bool
47376 {
47384 /* The two permutations only operate in 64-bit lanes. */
47395 /* Emit the pshuflw. */
47402 /* Emit the pshufhw. */
47410 }
47412 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47413 the permutation using the SSSE3 palignr instruction. This succeeds
47414 when all of the elements in PERM fit within one vector and we merely
47415 need to shift them down so that a single vector permutation has a
47416 chance to succeed. If SINGLE_INSN_ONLY_P, succeed if only
47417 the vpalignr instruction itself can perform the requested permutation. */
47419 static bool
47421 {
47428 /* Even with AVX, palignr only operates on 128-bit vectors,
47429 in AVX2 palignr operates on both 128-bit lanes. */
47439 {
47443 {
47446 }
47455 }
47458 {
47467 }
47469 /* Given that we have SSSE3, we know we'll be able to implement the
47470 single operand permutation after the palignr with pshufb for
47471 128-bit vectors. If SINGLE_INSN_ONLY_P, in_order has to be computed
47472 first. */
47478 {
47483 }
47487 {
47493 else
47498 }
47504 /* For AVX2, test whether we can permute the result in one instruction. */
47506 {
47511 }
47515 {
47519 }
47520 else
47521 {
47526 shift));
47527 }
47531 /* Test for the degenerate case where the alignment by itself
47532 produces the desired permutation. */
47534 {
47537 }
47543 }
47545 /* A subroutine of ix86_expand_vec_perm_const_1. Try to simplify
47546 the permutation using the SSE4_1 pblendv instruction. Potentially
47547 reduces permutation from 2 pshufb and or to 1 pshufb and pblendv. */
47549 static bool
47551 {
47557 /* Use the same checks as in expand_vec_perm_blend. */
47561 ;
47563 ;
47565 ;
47566 else
47569 /* Figure out where permutation elements stay not in their
47570 respective lanes. */
47572 {
47576 }
47577 /* We can pblend the part where elements stay not in their
47578 respective lanes only when these elements are all in one
47579 half of a permutation.
47580 {0 1 8 3 4 5 9 7} is ok as 8, 9 are at not at their respective
47581 lanes, but both 8 and 9 >= 8
47582 {0 1 8 3 4 5 2 7} is not ok as 2 and 8 are not at their
47583 respective lanes and 8 >= 8, but 2 not. */
47589 /* First we apply one operand permutation to the part where
47590 elements stay not in their respective lanes. */
47594 else
47606 else
47611 /* Next we put permuted elements into their positions. */
47615 else
47625 }
47629 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47630 a two vector permutation into a single vector permutation by using
47631 an interleave operation to merge the vectors. */
47633 static bool
47635 {
47644 {
47647 }
47649 {
47652 /* For 32-byte modes allow even d->one_operand_p.
47653 The lack of cross-lane shuffling in some instructions
47654 might prevent a single insn shuffle. */
47657 /* If expand_vec_perm_interleave3 can expand this into
47658 a 3 insn sequence, give up and let it be expanded as
47659 3 insn sequence. While that is one insn longer,
47660 it doesn't need a memory operand and in the common
47661 case that both interleave low and high permutations
47662 with the same operands are adjacent needs 4 insns
47663 for both after CSE. */
47666 }
47667 else
47670 /* Examine from whence the elements come. */
47679 {
47682 /* Split the two input vectors into 4 halves. */
47688 /* If the elements from the low halves use interleave low, and similarly
47689 for interleave high. If the elements are from mis-matched halves, we
47690 can use shufps for V4SF/V4SI or do a DImode shuffle. */
47692 {
47693 /* punpckl* */
47695 {
47700 }
47703 }
47705 {
47706 /* punpckh* */
47708 {
47713 }
47716 }
47718 {
47719 /* shufps */
47721 {
47726 }
47728 {
47729 /* shufpd */
47734 }
47735 }
47737 {
47738 /* shufps */
47740 {
47745 }
47747 {
47748 /* shufpd */
47753 }
47754 }
47755 else
47757 }
47758 else
47759 {
47764 /* Split the two input vectors into 8 quarters. */
47770 {
47773 }
47776 {
47780 }
47782 {
47785 }
47788 {
47790 {
47791 /* Attempt to increase the likelihood that dfinal
47792 shuffle will be intra-lane. */
47796 }
47798 /* vperm2f128 or vperm2i128. */
47800 {
47805 }
47810 {
47814 {
47817 }
47818 }
47819 }
47824 {
47825 /* vpunpckl* */
47827 {
47836 }
47837 }
47840 {
47841 /* vpunpckh* */
47843 {
47852 }
47853 }
47854 else
47856 }
47858 /* Use the remapping array set up above to move the elements from their
47859 swizzled locations into their final destinations. */
47862 {
47865 /* If same_halves is true, both halves of the remapped vector are the
47866 same. Avoid cross-lane accesses if possible. */
47868 {
47871 }
47872 else
47874 }
47876 {
47879 }
47883 /* Test if the final remap can be done with a single insn. For V4SFmode or
47884 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
47897 {
47900 }
47907 }
47909 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47910 a single vector cross-lane permutation into vpermq followed
47911 by any of the single insn permutations. */
47913 static bool
47915 {
47929 {
47932 }
47935 {
47940 }
47953 {
47960 }
47967 {
47972 ;
47975 else
47977 }
47986 }
47988 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
47989 a vector permutation using two instructions, vperm2f128 resp.
47990 vperm2i128 followed by any single in-lane permutation. */
47992 static bool
47994 {
48008 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
48009 immediate. For perm < 16 the second permutation uses
48010 d->op0 as first operand, for perm >= 16 it uses d->op1
48011 as first operand. The second operand is the result of
48012 vperm2[fi]128. */
48014 {
48015 /* Ignore permutations which do not move anything cross-lane. */
48017 {
48018 /* The second shuffle for e.g. V4DFmode has
48019 0123 and ABCD operands.
48020 Ignore AB23, as 23 is already in the second lane
48021 of the first operand. */
48023 /* And 01CD, as 01 is in the first lane of the first
48024 operand. */
48026 /* And 4567, as then the vperm2[fi]128 doesn't change
48027 anything on the original 4567 second operand. */
48029 }
48030 else
48031 {
48032 /* The second shuffle for e.g. V4DFmode has
48033 4567 and ABCD operands.
48034 Ignore AB67, as 67 is already in the second lane
48035 of the first operand. */
48037 /* And 45CD, as 45 is in the first lane of the first
48038 operand. */
48040 /* And 0123, as then the vperm2[fi]128 doesn't change
48041 anything on the original 0123 first operand. */
48043 }
48046 {
48052 else
48054 }
48057 {
48061 }
48062 else
48066 {
48070 /* Found a usable second shuffle. dfirst will be
48071 vperm2f128 on d->op0 and d->op1. */
48083 /* And dsecond is some single insn shuffle, taking
48084 d->op0 and result of vperm2f128 (if perm < 16) or
48085 d->op1 and result of vperm2f128 (otherwise). */
48094 }
48096 /* For one operand, the only useful vperm2f128 permutation is 0x01
48097 aka lanes swap. */
48100 }
48103 }
48105 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48106 a two vector permutation using 2 intra-lane interleave insns
48107 and cross-lane shuffle for 32-byte vectors. */
48109 static bool
48111 {
48118 ;
48120 ;
48121 else
48136 {
48140 else
48146 else
48152 else
48158 else
48164 else
48170 else
48175 }
48179 }
48181 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
48182 a single vector permutation using a single intra-lane vector
48183 permutation, vperm2f128 swapping the lanes and vblend* insn blending
48184 the non-swapped and swapped vectors together. */
48186 static bool
48188 {
48196 || TARGET_AVX2
48205 {
48212 }
48247 }
48249 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
48250 permutation using two vperm2f128, followed by a vshufpd insn blending
48251 the two vectors together. */
48253 static bool
48255 {
48298 }
48300 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
48301 permutation with two pshufb insns and an ior. We should have already
48302 failed all two instruction sequences. */
48304 static bool
48306 {
48320 /* Generate two permutation masks. If the required element is within
48321 the given vector it is shuffled into the proper lane. If the required
48322 element is in the other vector, force a zero into the lane by setting
48323 bit 7 in the permutation mask. */
48326 {
48333 {
48336 }
48337 }
48361 }
48363 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
48364 with two vpshufb insns, vpermq and vpor. We should have already failed
48365 all two or three instruction sequences. */
48367 static bool
48369 {
48384 /* Generate two permutation masks. If the required element is within
48385 the same lane, it is shuffled in. If the required element from the
48386 other lane, force a zero by setting bit 7 in the permutation mask.
48387 In the other mask the mask has non-negative elements if element
48388 is requested from the other lane, but also moved to the other lane,
48389 so that the result of vpshufb can have the two V2TImode halves
48390 swapped. */
48393 {
48398 {
48401 }
48402 }
48411 /* Swap the 128-byte lanes of h into hp. */
48415 const1_rtx));
48432 }
48434 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48435 and extract-odd permutations of two V32QImode and V16QImode operand
48436 with two vpshufb insns, vpor and vpermq. We should have already
48437 failed all two or three instruction sequences. */
48439 static bool
48441 {
48460 /* Generate two permutation masks. In the first permutation mask
48461 the first quarter will contain indexes for the first half
48462 of the op0, the second quarter will contain bit 7 set, third quarter
48463 will contain indexes for the second half of the op0 and the
48464 last quarter bit 7 set. In the second permutation mask
48465 the first quarter will contain bit 7 set, the second quarter
48466 indexes for the first half of the op1, the third quarter bit 7 set
48467 and last quarter indexes for the second half of the op1.
48468 I.e. the first mask e.g. for V32QImode extract even will be:
48469 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
48470 (all values masked with 0xf except for -128) and second mask
48471 for extract even will be
48472 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
48475 {
48481 {
48484 }
48485 }
48504 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
48512 }
48514 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48515 and extract-odd permutations of two V16QI, V8HI, V16HI or V32QI operands
48516 with two "and" and "pack" or two "shift" and "pack" insns. We should
48517 have already failed all two instruction sequences. */
48519 static bool
48521 {
48525 machine_mode half_mode;
48534 {
48536 /* Required for "pack". */
48547 /* No check as all instructions are SSE2. */
48578 /* Only V8HI, V16QI, V16HI and V32QI modes are more profitable than
48579 general shuffles. */
48581 }
48583 /* Check that permutation is even or odd. */
48598 {
48605 }
48606 else
48607 {
48614 }
48615 /* In AVX2 for 256 bit case we need to permute pack result. */
48617 {
48623 const0_rtx,
48624 const2_rtx,
48625 const1_rtx,
48628 }
48629 else
48633 }
48635 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
48636 and extract-odd permutations. */
48638 static bool
48640 {
48644 {
48651 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48655 /* Now an unpck[lh]pd will produce the result required. */
48658 else
48664 {
48673 /* Shuffle within the 128-bit lanes to produce:
48674 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
48678 /* Shuffle the lanes around to produce:
48679 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
48683 /* Shuffle within the 128-bit lanes to produce:
48684 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
48687 /* Shuffle within the 128-bit lanes to produce:
48688 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
48691 /* Shuffle the lanes around to produce:
48692 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
48695 }
48702 /* These are always directly implementable by expand_vec_perm_1. */
48710 else
48711 {
48714 /* We need 2*log2(N)-1 operations to achieve odd/even
48715 with interleave. */
48724 else
48727 }
48739 {
48744 else
48749 {
48754 }
48756 }
48764 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48768 /* Now an vpunpck[lh]qdq will produce the result required. */
48771 else
48778 {
48783 else
48788 {
48793 }
48795 }
48806 /* Shuffle the lanes around into
48807 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
48815 /* Swap the 2nd and 3rd position in each lane into
48816 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
48822 /* Now an vpunpck[lh]qdq will produce
48823 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
48827 else
48836 }
48839 }
48841 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
48842 extract-even and extract-odd permutations. */
48844 static bool
48846 {
48858 }
48860 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
48861 permutations. We assume that expand_vec_perm_1 has already failed. */
48863 static bool
48865 {
48873 {
48876 /* These are special-cased in sse.md so that we can optionally
48877 use the vbroadcast instruction. They expand to two insns
48878 if the input happens to be in a register. */
48885 /* These are always implementable using standard shuffle patterns. */
48890 /* These can be implemented via interleave. We save one insn by
48891 stopping once we have promoted to V4SImode and then use pshufd. */
48894 do
48895 {
48896 rtx dest;
48902 {
48906 }
48913 }
48929 /* For AVX2 broadcasts of the first element vpbroadcast* or
48930 vpermq should be used by expand_vec_perm_1. */
48936 }
48937 }
48939 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
48940 broadcast permutations. */
48942 static bool
48944 {
48956 }
48958 /* Implement arbitrary permutations of two V64QImode operands
48959 will 2 vpermi2w, 2 vpshufb and one vpor instruction. */
48960 static bool
48962 {
48972 machine_mode vmode;
48978 {
48985 }
48987 /* Prepare permutations such that the first one takes care of
48988 putting the even bytes into the right positions or one higher
48989 positions (ds[0]) and the second one takes care of
48990 putting the odd bytes into the right positions or one below
48991 (ds[1]). */
48994 {
48997 {
49000 }
49001 else
49002 {
49005 }
49006 }
49028 }
49030 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
49031 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
49032 all the shorter instruction sequences. */
49034 static bool
49036 {
49052 /* Generate 4 permutation masks. If the required element is within
49053 the same lane, it is shuffled in. If the required element from the
49054 other lane, force a zero by setting bit 7 in the permutation mask.
49055 In the other mask the mask has non-negative elements if element
49056 is requested from the other lane, but also moved to the other lane,
49057 so that the result of vpshufb can have the two V2TImode halves
49058 swapped. */
49061 {
49066 }
49072 {
49080 }
49083 {
49085 {
49088 }
49095 }
49097 /* Swap the 128-byte lanes of h[X]. */
49099 {
49105 const1_rtx));
49107 }
49110 {
49112 {
49115 }
49121 }
49124 {
49126 {
49130 }
49133 }
49143 }
49145 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
49146 With all of the interface bits taken care of, perform the expansion
49147 in D and return true on success. */
49149 static bool
49151 {
49152 /* Try a single instruction expansion. */
49156 /* Try sequences of two instructions. */
49179 /* Try sequences of three instructions. */
49196 /* Try sequences of four instructions. */
49207 /* ??? Look for narrow permutations whose element orderings would
49208 allow the promotion to a wider mode. */
49210 /* ??? Look for sequences of interleave or a wider permute that place
49211 the data into the correct lanes for a half-vector shuffle like
49212 pshuf[lh]w or vpermilps. */
49214 /* ??? Look for sequences of interleave that produce the desired results.
49215 The combinatorics of punpck[lh] get pretty ugly... */
49220 /* Even longer sequences. */
49225 }
49227 /* If a permutation only uses one operand, make it clear. Returns true
49228 if the permutation references both operands. */
49230 static bool
49232 {
49240 {
49246 {
49249 }
49250 /* The elements of PERM do not suggest that only the first operand
49251 is used, but both operands are identical. Allow easier matching
49252 of the permutation by folding the permutation into the single
49253 input vector. */
49254 /* FALLTHRU */
49265 }
49268 }
49270 bool
49272 {
49277 rtx sel;
49294 {
49299 }
49306 /* If the selector says both arguments are needed, but the operands are the
49307 same, the above tried to expand with one_operand_p and flattened selector.
49308 If that didn't work, retry without one_operand_p; we succeeded with that
49309 during testing. */
49311 {
49315 }
49318 }
49320 /* Implement targetm.vectorize.vec_perm_const_ok. */
49322 static bool
49325 {
49334 /* Given sufficient ISA support we can just return true here
49335 for selected vector modes. */
49337 {
49343 /* All implementable with a single vpermi2 insn. */
49348 /* All implementable with a single vpermi2 insn. */
49353 /* Implementable with 2 vpermi2, 2 vpshufb and 1 or insn. */
49361 /* All implementable with a single vpermi2 insn. */
49366 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49371 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49378 /* All implementable with a single vpperm insn. */
49381 /* All implementable with 2 pshufb + 1 ior. */
49387 /* All implementable with shufpd or unpck[lh]pd. */
49391 }
49393 /* Extract the values from the vector CST into the permutation
49394 array in D. */
49397 {
49401 }
49403 /* For all elements from second vector, fold the elements to first. */
49408 /* Check whether the mask can be applied to the vector type. */
49411 /* Implementable with shufps or pshufd. */
49415 /* Otherwise we have to go through the motions and see if we can
49416 figure out how to generate the requested permutation. */
49427 }
49429 void
49431 {
49446 /* We'll either be able to implement the permutation directly... */
49450 /* ... or we use the special-case patterns. */
49452 }
49454 static void
49456 {
49471 {
49474 }
49476 /* Note that for AVX this isn't one instruction. */
49479 }
49482 /* Expand a vector operation CODE for a V*QImode in terms of the
49483 same operation on V*HImode. */
49485 void
49487 {
49489 machine_mode himode;
49499 {
49517 }
49521 {
49523 /* Unpack data such that we've got a source byte in each low byte of
49524 each word. We don't care what goes into the high byte of each word.
49525 Rather than trying to get zero in there, most convenient is to let
49526 it be a copy of the low byte. */
49531 /* FALLTHRU */
49543 /* FALLTHRU */
49553 }
49555 /* Perform the operation. */
49562 /* Merge the data back into the right place. */
49572 {
49573 /* For SSE2, we used an full interleave, so the desired
49574 results are in the even elements. */
49577 }
49578 else
49579 {
49580 /* For AVX, the interleave used above was not cross-lane. So the
49581 extraction is evens but with the second and third quarter swapped.
49582 Happily, that is even one insn shorter than even extraction. */
49585 }
49592 }
49594 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
49595 if op is CONST_VECTOR with all odd elements equal to their
49596 preceding element. */
49598 static bool
49600 {
49610 }
49612 void
49615 {
49618 rtx x;
49626 /* We only play even/odd games with vectors of SImode. */
49629 /* If we're looking for the odd results, shift those members down to
49630 the even slots. For some cpus this is faster than a PSHUFD. */
49632 {
49633 /* For XOP use vpmacsdqh, but only for smult, as it is only
49634 signed. */
49636 {
49640 }
49651 }
49654 {
49657 else
49659 }
49661 {
49664 else
49666 }
49671 else
49672 {
49675 /* The easiest way to implement this without PMULDQ is to go through
49676 the motions as if we are performing a full 64-bit multiply. With
49677 the exception that we need to do less shuffling of the elements. */
49679 /* Compute the sign-extension, aka highparts, of the two operands. */
49685 /* Multiply LO(A) * HI(B), and vice-versa. */
49691 /* Multiply LO(A) * LO(B). */
49695 /* Combine and shift the highparts into place. */
49700 /* Combine high and low parts. */
49703 }
49705 }
49707 void
49710 {
49716 {
49721 {
49722 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
49723 shuffle the elements once so that all elements are in the right
49724 place for immediate use: { A C B D }. */
49729 }
49730 else
49731 {
49732 /* Put the elements into place for the multiply. */
49736 }
49741 /* Shuffle the elements between the lanes. After this we
49742 have { A B E F | C D G H } for each operand. */
49752 /* Shuffle the elements within the lanes. After this we
49753 have { A A B B | C C D D } or { E E F F | G G H H }. */
49794 }
49795 }
49797 void
49799 {
49809 /* Move the results in element 2 down to element 1; we don't care
49810 what goes in elements 2 and 3. Then we can merge the parts
49811 back together with an interleave.
49813 Note that two other sequences were tried:
49814 (1) Use interleaves at the start instead of psrldq, which allows
49815 us to use a single shufps to merge things back at the end.
49816 (2) Use shufps here to combine the two vectors, then pshufd to
49817 put the elements in the correct order.
49818 In both cases the cost of the reformatting stall was too high
49819 and the overall sequence slower. */
49830 }
49832 void
49834 {
49845 {
49846 /* op1: A,B,C,D, op2: E,F,G,H */
49855 /* t1: B,A,D,C */
49862 /* t2: (B*E),(A*F),(D*G),(C*H) */
49865 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
49868 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
49871 /* Multiply lower parts and add all */
49878 }
49879 else
49880 {
49881 machine_mode nmode;
49885 {
49888 }
49890 {
49893 }
49895 {
49898 }
49899 else
49903 /* Multiply low parts. */
49907 /* Shift input vectors right 32 bits so we can multiply high parts. */
49912 /* Multiply high parts by low parts. */
49918 /* Combine and shift the highparts back. */
49922 /* Combine high and low parts. */
49924 }
49928 }
49930 /* Return 1 if control tansfer instruction INSN
49931 should be encoded with bnd prefix.
49932 If insn is NULL then return 1 when control
49933 transfer instructions should be prefixed with
49934 bnd by default for current function. */
49936 bool
49938 {
49939 /* For call insns check special flag. */
49941 {
49945 }
49947 /* All other insns are prefixed only if function is instrumented. */
49949 }
49951 /* Calculate integer abs() using only SSE2 instructions. */
49953 void
49955 {
49960 {
49961 /* For 32-bit signed integer X, the best way to calculate the absolute
49962 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
49974 /* For 16-bit signed integer X, the best way to calculate the absolute
49975 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
49983 /* For 8-bit signed integer X, the best way to calculate the absolute
49984 value of X is min ((unsigned char) X, (unsigned char) (-X)),
49985 as SSE2 provides the PMINUB insn. */
49995 }
49999 }
50001 /* Expand an insert into a vector register through pinsr insn.
50002 Return true if successful. */
50004 bool
50006 {
50014 {
50017 }
50023 {
50028 {
50035 {
50067 }
50081 }
50085 }
50086 }
50087 \f
50088 /* This function returns the calling abi specific va_list type node.
50089 It returns the FNDECL specific va_list type. */
50091 static tree
50093 {
50100 else
50102 }
50104 /* Returns the canonical va_list type specified by TYPE. If there
50105 is no valid TYPE provided, it return NULL_TREE. */
50107 static tree
50109 {
50112 /* Resolve references and pointers to va_list type. */
50121 {
50126 {
50127 /* If va_list is an array type, the argument may have decayed
50128 to a pointer type, e.g. by being passed to another function.
50129 In that case, unwrap both types so that we can compare the
50130 underlying records. */
50133 {
50136 }
50137 }
50144 {
50145 /* If va_list is an array type, the argument may have decayed
50146 to a pointer type, e.g. by being passed to another function.
50147 In that case, unwrap both types so that we can compare the
50148 underlying records. */
50151 {
50154 }
50155 }
50162 {
50163 /* If va_list is an array type, the argument may have decayed
50164 to a pointer type, e.g. by being passed to another function.
50165 In that case, unwrap both types so that we can compare the
50166 underlying records. */
50169 {
50172 }
50173 }
50177 }
50179 }
50181 /* Iterate through the target-specific builtin types for va_list.
50182 IDX denotes the iterator, *PTREE is set to the result type of
50183 the va_list builtin, and *PNAME to its internal type.
50184 Returns zero if there is no element for this index, otherwise
50185 IDX should be increased upon the next call.
50186 Note, do not iterate a base builtin's name like __builtin_va_list.
50187 Used from c_common_nodes_and_builtins. */
50189 static int
50191 {
50193 {
50195 {
50208 }
50209 }
50212 }
50214 #undef TARGET_SCHED_DISPATCH
50215 #define TARGET_SCHED_DISPATCH has_dispatch
50216 #undef TARGET_SCHED_DISPATCH_DO
50217 #define TARGET_SCHED_DISPATCH_DO do_dispatch
50218 #undef TARGET_SCHED_REASSOCIATION_WIDTH
50219 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
50220 #undef TARGET_SCHED_REORDER
50221 #define TARGET_SCHED_REORDER ix86_sched_reorder
50222 #undef TARGET_SCHED_ADJUST_PRIORITY
50223 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
50224 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
50225 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
50226 ix86_dependencies_evaluation_hook
50228 /* The size of the dispatch window is the total number of bytes of
50229 object code allowed in a window. */
50230 #define DISPATCH_WINDOW_SIZE 16
50232 /* Number of dispatch windows considered for scheduling. */
50233 #define MAX_DISPATCH_WINDOWS 3
50235 /* Maximum number of instructions in a window. */
50236 #define MAX_INSN 4
50238 /* Maximum number of immediate operands in a window. */
50239 #define MAX_IMM 4
50241 /* Maximum number of immediate bits allowed in a window. */
50242 #define MAX_IMM_SIZE 128
50244 /* Maximum number of 32 bit immediates allowed in a window. */
50245 #define MAX_IMM_32 4
50247 /* Maximum number of 64 bit immediates allowed in a window. */
50248 #define MAX_IMM_64 2
50250 /* Maximum total of loads or prefetches allowed in a window. */
50251 #define MAX_LOAD 2
50253 /* Maximum total of stores allowed in a window. */
50254 #define MAX_STORE 1
50256 #undef BIG
50257 #define BIG 100
50260 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
50263 disp_load,
50264 disp_store,
50265 disp_load_store,
50266 disp_prefetch,
50267 disp_imm,
50268 disp_imm_32,
50269 disp_imm_64,
50270 disp_branch,
50271 disp_cmp,
50272 disp_jcc,
50273 disp_last
50274 };
50276 /* Number of allowable groups in a dispatch window. It is an array
50277 indexed by dispatch_group enum. 100 is used as a big number,
50278 because the number of these kind of operations does not have any
50279 effect in dispatch window, but we need them for other reasons in
50280 the table. */
50283 };
50289 };
50291 /* Instruction path. */
50297 last_path
50298 };
50300 /* sched_insn_info defines a window to the instructions scheduled in
50301 the basic block. It contains a pointer to the insn_info table and
50302 the instruction scheduled.
50304 Windows are allocated for each basic block and are linked
50305 together. */
50307 rtx insn;
50314 /* Linked list of dispatch windows. This is a two way list of
50315 dispatch windows of a basic block. It contains information about
50316 the number of uops in the window and the total number of
50317 instructions and of bytes in the object code for this dispatch
50318 window. */
50336 /* Immediate valuse used in an insn. */
50338 {
50347 /* Get dispatch group of insn. */
50349 static enum dispatch_group
50351 {
50367 }
50369 /* Return true if insn is a compare instruction. */
50371 static bool
50373 {
50381 }
50383 /* Return true if a dispatch violation encountered. */
50385 static bool
50387 {
50391 }
50393 /* Return true if insn is a branch instruction. */
50395 static bool
50397 {
50399 }
50401 /* Return true if insn is a prefetch instruction. */
50403 static bool
50405 {
50407 }
50409 /* This function initializes a dispatch window and the list container holding a
50410 pointer to the window. */
50412 static void
50414 {
50420 else
50438 {
50444 }
50446 }
50448 /* This function allocates and initializes a dispatch window and the
50449 list container holding a pointer to the window. */
50453 {
50458 }
50460 /* This routine initializes the dispatch scheduling information. It
50461 initiates building dispatch scheduler tables and constructs the
50462 first dispatch window. */
50464 static void
50466 {
50467 /* Allocate a dispatch list and a window. */
50472 }
50474 /* This function returns true if a branch is detected. End of a basic block
50475 does not have to be a branch, but here we assume only branches end a
50476 window. */
50478 static bool
50480 {
50482 }
50484 /* This function is called when the end of a window processing is reached. */
50486 static void
50488 {
50491 {
50496 }
50498 }
50500 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
50501 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
50502 for 48 bytes of instructions. Note that these windows are not dispatch
50503 windows that their sizes are DISPATCH_WINDOW_SIZE. */
50507 {
50509 {
50514 }
50520 }
50522 /* Compute number of immediate operands of an instruction. */
50524 static void
50526 {
50533 {
50540 else
50551 {
50554 }
50559 }
50560 }
50562 /* Return total size of immediate operands of an instruction along with number
50563 of corresponding immediate-operands. It initializes its parameters to zero
50564 befor calling FIND_CONSTANT.
50565 INSN is the input instruction. IMM is the total of immediates.
50566 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
50567 bit immediates. */
50569 static int
50571 {
50579 }
50581 /* This function indicates if an operand of an instruction is an
50582 immediate. */
50584 static bool
50586 {
50595 }
50597 /* Return single or double path for instructions. */
50599 static enum insn_path
50601 {
50611 }
50613 /* Return insn dispatch group. */
50615 static enum dispatch_group
50617 {
50635 }
50637 /* Count number of GROUP restricted instructions in a dispatch
50638 window WINDOW_LIST. */
50640 static int
50642 {
50653 {
50672 }
50685 }
50687 /* This function returns true if insn satisfies dispatch rules on the
50688 last window scheduled. */
50690 static bool
50692 {
50700 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
50701 instructions should be given the lowest priority in the
50702 scheduling process in Haifa scheduler to make sure they will be
50703 scheduled in the same dispatch window as the reference to them. */
50707 /* Check nonrestricted. */
50711 /* Get last dispatch window. */
50716 {
50721 /* Window 1 is full. Go for next window. */
50723 }
50730 /* See if it fits in the first window. */
50732 {
50733 /* The first widow should have only single and double path
50734 uops. */
50740 }
50742 }
50744 /* Add an instruction INSN with NUM_UOPS micro-operations to the
50745 dispatch window WINDOW_LIST. */
50747 static void
50749 {
50767 /* Initialize window with new instruction. */
50788 {
50791 }
50792 }
50794 /* Adds a scheduled instruction, INSN, to the current dispatch window.
50795 If the total bytes of instructions or the number of instructions in
50796 the window exceed allowable, it allocates a new window. */
50798 static void
50800 {
50823 /* Get the last dispatch window. */
50831 else
50834 /* If current window is full, get a new window.
50835 Window number zero is full, if MAX_INSN uops are scheduled in it.
50836 Window number one is full, if window zero's bytes plus window
50837 one's bytes is 32, or if the bytes of the new instruction added
50838 to the total makes it greater than 48, or it has already MAX_INSN
50839 instructions in it. */
50848 {
50851 }
50854 {
50858 {
50861 }
50862 }
50864 {
50869 {
50872 }
50875 }
50876 else
50880 {
50881 /* End of basic block is reached do end-basic-block process. */
50884 }
50885 }
50887 /* Print the dispatch window, WINDOW_NUM, to FILE. */
50889 DEBUG_FUNCTION static void
50891 {
50897 else
50911 {
50914 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
50920 }
50921 }
50923 /* Print to stdout a dispatch window. */
50925 DEBUG_FUNCTION void
50927 {
50929 }
50931 /* Print INSN dispatch information to FILE. */
50933 DEBUG_FUNCTION static void
50935 {
50958 }
50960 /* Print to STDERR the status of the ready list with respect to
50961 dispatch windows. */
50963 DEBUG_FUNCTION void
50965 {
50973 }
50975 /* This routine is the driver of the dispatch scheduler. */
50977 static void
50979 {
50984 }
50986 /* Return TRUE if Dispatch Scheduling is supported. */
50988 static bool
50990 {
50994 {
51010 }
51013 }
51015 /* Implementation of reassociation_width target hook used by
51016 reassoc phase to identify parallelism level in reassociated
51017 tree. Statements tree_code is passed in OPC. Arguments type
51018 is passed in MODE.
51020 Currently parallel reassociation is enabled for Atom
51021 processors only and we set reassociation width to be 2
51022 because Atom may issue up to 2 instructions per cycle.
51024 Return value should be fixed if parallel reassociation is
51025 enabled for other processors. */
51027 static int
51029 {
51032 /* Vector part. */
51034 {
51037 else
51039 }
51041 /* Scalar part. */
51048 }
51050 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
51051 place emms and femms instructions. */
51053 static machine_mode
51055 {
51060 {
51079 else
51091 /* FALLTHRU */
51095 }
51096 }
51098 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
51099 vectors. If AVX512F is enabled then try vectorizing with 512bit,
51100 256bit and 128bit vectors. */
51102 static unsigned int
51104 {
51107 }
51109 \f
51111 /* Return class of registers which could be used for pseudo of MODE
51112 and of class RCLASS for spilling instead of memory. Return NO_REGS
51113 if it is not possible or non-profitable. */
51114 static reg_class_t
51116 {
51122 }
51124 /* Implement targetm.vectorize.init_cost. */
51128 {
51132 }
51134 /* Implement targetm.vectorize.add_stmt_cost. */
51136 static unsigned
51140 {
51147 /* Statements in an inner loop relative to the loop being
51148 vectorized are weighted more heavily. The value here is
51149 arbitrary and could potentially be improved with analysis. */
51155 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
51156 for Silvermont as it has out of order integer pipeline and can execute
51157 2 scalar instruction per tick, but has in order SIMD pipeline. */
51160 {
51164 }
51169 }
51171 /* Implement targetm.vectorize.finish_cost. */
51173 static void
51176 {
51181 }
51183 /* Implement targetm.vectorize.destroy_cost_data. */
51185 static void
51187 {
51189 }
51191 /* Validate target specific memory model bits in VAL. */
51193 static unsigned HOST_WIDE_INT
51195 {
51202 {
51206 }
51209 {
51213 }
51215 {
51219 }
51221 }
51223 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
51224 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
51225 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
51226 or number of vecsize_mangle variants that should be emitted. */
51228 static int
51232 {
51239 {
51243 }
51248 {
51255 /* case SCmode: */
51256 /* case DCmode: */
51262 }
51264 tree t;
51268 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
51270 {
51277 /* case SCmode: */
51278 /* case DCmode: */
51284 }
51287 {
51288 /* Parse here processor clause. If not present, default to 'b'. */
51290 }
51292 {
51293 /* If the function isn't exported, we can pick up just one ISA
51294 for the clones. */
51299 else
51302 }
51303 else
51304 {
51307 }
51309 {
51322 }
51324 {
51327 else
51332 }
51334 }
51336 /* Add target attribute to SIMD clone NODE if needed. */
51338 static void
51340 {
51344 {
51359 }
51369 }
51371 /* If SIMD clone NODE can't be used in a vectorized loop
51372 in current function, return -1, otherwise return a badness of using it
51373 (0 if it is most desirable from vecsize_mangle point of view, 1
51374 slightly less desirable, etc.). */
51376 static int
51378 {
51380 {
51398 }
51399 }
51401 /* This function adjusts the unroll factor based on
51402 the hardware capabilities. For ex, bdver3 has
51403 a loop buffer which makes unrolling of smaller
51404 loops less important. This function decides the
51405 unroll factor using number of memory references
51406 (value 32 is used) as a heuristic. */
51408 static unsigned
51410 {
51419 /* Count the number of memory references within the loop body.
51420 This value determines the unrolling factor for bdver3 and bdver4
51421 architectures. */
51430 {
51435 else
51437 }
51444 }
51447 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
51449 static bool
51451 {
51452 /* For x87 floating point with standard excess precision handling,
51453 there is no adddf3 pattern (since x87 floating point only has
51454 XFmode operations) so the default hook implementation gets this
51455 wrong. */
51457 }
51459 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
51461 static void
51463 {
51468 {
51483 hold_fnclex);
51496 }
51498 {
51507 mxcsr_orig_var,
51517 ldmxcsr_hold_call);
51520 else
51525 ldmxcsr_clear_call);
51526 else
51530 stxmcsr_update_call);
51532 {
51538 exceptions_assign);
51539 }
51540 else
51545 ldmxcsr_update_call);
51546 }
51547 tree atomic_feraiseexcept
51552 atomic_feraiseexcept_call);
51553 }
51555 /* Return mode to be used for bounds or VOIDmode
51556 if bounds are not supported. */
51558 static enum machine_mode
51560 {
51561 /* Do not support pointer checker if MPX
51562 is not enabled. */
51564 {
51569 }
51572 }
51574 /* Return constant used to statically initialize constant bounds.
51576 This function is used to create special bound values. For now
51577 only INIT bounds and NONE bounds are expected. More special
51578 values may be added later. */
51580 static tree
51582 {
51588 /* This function is supposed to be used to create INIT and
51589 NONE bounds only. */
51594 }
51596 /* Generate a list of statements STMTS to initialize pointer bounds
51597 variable VAR with bounds LB and UB. Return the number of generated
51598 statements. */
51600 static int
51602 {
51620 }
51622 /* Initialize the GCC target structure. */
51623 #undef TARGET_RETURN_IN_MEMORY
51624 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
51626 #undef TARGET_LEGITIMIZE_ADDRESS
51627 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
51629 #undef TARGET_ATTRIBUTE_TABLE
51630 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
51631 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
51632 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
51633 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51634 # undef TARGET_MERGE_DECL_ATTRIBUTES
51635 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
51636 #endif
51638 #undef TARGET_COMP_TYPE_ATTRIBUTES
51639 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
51641 #undef TARGET_INIT_BUILTINS
51642 #define TARGET_INIT_BUILTINS ix86_init_builtins
51643 #undef TARGET_BUILTIN_DECL
51644 #define TARGET_BUILTIN_DECL ix86_builtin_decl
51645 #undef TARGET_EXPAND_BUILTIN
51646 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
51648 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
51649 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
51650 ix86_builtin_vectorized_function
51652 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
51653 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
51655 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
51656 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
51658 #undef TARGET_VECTORIZE_BUILTIN_GATHER
51659 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
51661 #undef TARGET_BUILTIN_RECIPROCAL
51662 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
51664 #undef TARGET_ASM_FUNCTION_EPILOGUE
51665 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
51667 #undef TARGET_ENCODE_SECTION_INFO
51668 #ifndef SUBTARGET_ENCODE_SECTION_INFO
51669 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
51670 #else
51671 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
51672 #endif
51674 #undef TARGET_ASM_OPEN_PAREN
51676 #undef TARGET_ASM_CLOSE_PAREN
51679 #undef TARGET_ASM_BYTE_OP
51680 #define TARGET_ASM_BYTE_OP ASM_BYTE
51682 #undef TARGET_ASM_ALIGNED_HI_OP
51683 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
51684 #undef TARGET_ASM_ALIGNED_SI_OP
51685 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
51686 #ifdef ASM_QUAD
51687 #undef TARGET_ASM_ALIGNED_DI_OP
51688 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
51689 #endif
51691 #undef TARGET_PROFILE_BEFORE_PROLOGUE
51692 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
51694 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
51695 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
51697 #undef TARGET_ASM_UNALIGNED_HI_OP
51698 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
51699 #undef TARGET_ASM_UNALIGNED_SI_OP
51700 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
51701 #undef TARGET_ASM_UNALIGNED_DI_OP
51702 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
51704 #undef TARGET_PRINT_OPERAND
51705 #define TARGET_PRINT_OPERAND ix86_print_operand
51706 #undef TARGET_PRINT_OPERAND_ADDRESS
51707 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
51708 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
51709 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
51710 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
51711 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
51713 #undef TARGET_SCHED_INIT_GLOBAL
51714 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
51715 #undef TARGET_SCHED_ADJUST_COST
51716 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
51717 #undef TARGET_SCHED_ISSUE_RATE
51718 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
51719 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
51720 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
51721 ia32_multipass_dfa_lookahead
51722 #undef TARGET_SCHED_MACRO_FUSION_P
51723 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
51724 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
51725 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
51727 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
51728 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
51730 #undef TARGET_MEMMODEL_CHECK
51731 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
51733 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
51734 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
51736 #ifdef HAVE_AS_TLS
51737 #undef TARGET_HAVE_TLS
51738 #define TARGET_HAVE_TLS true
51739 #endif
51740 #undef TARGET_CANNOT_FORCE_CONST_MEM
51741 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
51742 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
51743 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
51745 #undef TARGET_DELEGITIMIZE_ADDRESS
51746 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
51748 #undef TARGET_MS_BITFIELD_LAYOUT_P
51749 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
51751 #if TARGET_MACHO
51752 #undef TARGET_BINDS_LOCAL_P
51753 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
51754 #endif
51755 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51756 #undef TARGET_BINDS_LOCAL_P
51757 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
51758 #endif
51760 #undef TARGET_ASM_OUTPUT_MI_THUNK
51761 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
51762 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
51763 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
51765 #undef TARGET_ASM_FILE_START
51766 #define TARGET_ASM_FILE_START x86_file_start
51768 #undef TARGET_OPTION_OVERRIDE
51769 #define TARGET_OPTION_OVERRIDE ix86_option_override
51771 #undef TARGET_REGISTER_MOVE_COST
51772 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
51773 #undef TARGET_MEMORY_MOVE_COST
51774 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
51775 #undef TARGET_RTX_COSTS
51776 #define TARGET_RTX_COSTS ix86_rtx_costs
51777 #undef TARGET_ADDRESS_COST
51778 #define TARGET_ADDRESS_COST ix86_address_cost
51780 #undef TARGET_FIXED_CONDITION_CODE_REGS
51781 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
51782 #undef TARGET_CC_MODES_COMPATIBLE
51783 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
51785 #undef TARGET_MACHINE_DEPENDENT_REORG
51786 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
51788 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
51789 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
51791 #undef TARGET_BUILD_BUILTIN_VA_LIST
51792 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
51794 #undef TARGET_FOLD_BUILTIN
51795 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
51797 #undef TARGET_COMPARE_VERSION_PRIORITY
51798 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
51800 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
51801 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
51802 ix86_generate_version_dispatcher_body
51804 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
51805 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
51806 ix86_get_function_versions_dispatcher
51808 #undef TARGET_ENUM_VA_LIST_P
51809 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
51811 #undef TARGET_FN_ABI_VA_LIST
51812 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
51814 #undef TARGET_CANONICAL_VA_LIST_TYPE
51815 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
51817 #undef TARGET_EXPAND_BUILTIN_VA_START
51818 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
51820 #undef TARGET_MD_ASM_CLOBBERS
51821 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
51823 #undef TARGET_PROMOTE_PROTOTYPES
51824 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
51825 #undef TARGET_SETUP_INCOMING_VARARGS
51826 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
51827 #undef TARGET_MUST_PASS_IN_STACK
51828 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
51829 #undef TARGET_FUNCTION_ARG_ADVANCE
51830 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
51831 #undef TARGET_FUNCTION_ARG
51832 #define TARGET_FUNCTION_ARG ix86_function_arg
51833 #undef TARGET_INIT_PIC_REG
51834 #define TARGET_INIT_PIC_REG ix86_init_pic_reg
51835 #undef TARGET_USE_PSEUDO_PIC_REG
51836 #define TARGET_USE_PSEUDO_PIC_REG ix86_use_pseudo_pic_reg
51837 #undef TARGET_FUNCTION_ARG_BOUNDARY
51838 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
51839 #undef TARGET_PASS_BY_REFERENCE
51840 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
51841 #undef TARGET_INTERNAL_ARG_POINTER
51842 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
51843 #undef TARGET_UPDATE_STACK_BOUNDARY
51844 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
51845 #undef TARGET_GET_DRAP_RTX
51846 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
51847 #undef TARGET_STRICT_ARGUMENT_NAMING
51848 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
51849 #undef TARGET_STATIC_CHAIN
51850 #define TARGET_STATIC_CHAIN ix86_static_chain
51851 #undef TARGET_TRAMPOLINE_INIT
51852 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
51853 #undef TARGET_RETURN_POPS_ARGS
51854 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
51856 #undef TARGET_LEGITIMATE_COMBINED_INSN
51857 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
51859 #undef TARGET_ASAN_SHADOW_OFFSET
51860 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
51862 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
51863 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
51865 #undef TARGET_SCALAR_MODE_SUPPORTED_P
51866 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
51868 #undef TARGET_VECTOR_MODE_SUPPORTED_P
51869 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
51871 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
51872 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
51873 ix86_libgcc_floating_mode_supported_p
51875 #undef TARGET_C_MODE_FOR_SUFFIX
51876 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
51878 #ifdef HAVE_AS_TLS
51879 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
51880 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
51881 #endif
51883 #ifdef SUBTARGET_INSERT_ATTRIBUTES
51884 #undef TARGET_INSERT_ATTRIBUTES
51885 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
51886 #endif
51888 #undef TARGET_MANGLE_TYPE
51889 #define TARGET_MANGLE_TYPE ix86_mangle_type
51891 #if !TARGET_MACHO
51892 #undef TARGET_STACK_PROTECT_FAIL
51893 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
51894 #endif
51896 #undef TARGET_FUNCTION_VALUE
51897 #define TARGET_FUNCTION_VALUE ix86_function_value
51899 #undef TARGET_FUNCTION_VALUE_REGNO_P
51900 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
51902 #undef TARGET_PROMOTE_FUNCTION_MODE
51903 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
51905 #undef TARGET_MEMBER_TYPE_FORCES_BLK
51906 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
51908 #undef TARGET_INSTANTIATE_DECLS
51909 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
51911 #undef TARGET_SECONDARY_RELOAD
51912 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
51914 #undef TARGET_CLASS_MAX_NREGS
51915 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
51917 #undef TARGET_PREFERRED_RELOAD_CLASS
51918 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
51919 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
51920 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
51921 #undef TARGET_CLASS_LIKELY_SPILLED_P
51922 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
51924 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
51925 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
51926 ix86_builtin_vectorization_cost
51927 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
51928 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
51929 ix86_vectorize_vec_perm_const_ok
51930 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
51931 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
51932 ix86_preferred_simd_mode
51933 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
51934 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
51935 ix86_autovectorize_vector_sizes
51936 #undef TARGET_VECTORIZE_INIT_COST
51937 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
51938 #undef TARGET_VECTORIZE_ADD_STMT_COST
51939 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
51940 #undef TARGET_VECTORIZE_FINISH_COST
51941 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
51942 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
51943 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
51945 #undef TARGET_SET_CURRENT_FUNCTION
51946 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
51948 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
51949 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
51951 #undef TARGET_OPTION_SAVE
51952 #define TARGET_OPTION_SAVE ix86_function_specific_save
51954 #undef TARGET_OPTION_RESTORE
51955 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
51957 #undef TARGET_OPTION_PRINT
51958 #define TARGET_OPTION_PRINT ix86_function_specific_print
51960 #undef TARGET_OPTION_FUNCTION_VERSIONS
51961 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
51963 #undef TARGET_CAN_INLINE_P
51964 #define TARGET_CAN_INLINE_P ix86_can_inline_p
51966 #undef TARGET_EXPAND_TO_RTL_HOOK
51967 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
51969 #undef TARGET_LEGITIMATE_ADDRESS_P
51970 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
51972 #undef TARGET_LRA_P
51973 #define TARGET_LRA_P hook_bool_void_true
51975 #undef TARGET_REGISTER_PRIORITY
51976 #define TARGET_REGISTER_PRIORITY ix86_register_priority
51978 #undef TARGET_REGISTER_USAGE_LEVELING_P
51979 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
51981 #undef TARGET_LEGITIMATE_CONSTANT_P
51982 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
51984 #undef TARGET_FRAME_POINTER_REQUIRED
51985 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
51987 #undef TARGET_CAN_ELIMINATE
51988 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
51990 #undef TARGET_EXTRA_LIVE_ON_ENTRY
51991 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
51993 #undef TARGET_ASM_CODE_END
51994 #define TARGET_ASM_CODE_END ix86_code_end
51996 #undef TARGET_CONDITIONAL_REGISTER_USAGE
51997 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
51999 #if TARGET_MACHO
52000 #undef TARGET_INIT_LIBFUNCS
52001 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
52002 #endif
52004 #undef TARGET_LOOP_UNROLL_ADJUST
52005 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
52007 #undef TARGET_SPILL_CLASS
52008 #define TARGET_SPILL_CLASS ix86_spill_class
52010 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
52011 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
52012 ix86_simd_clone_compute_vecsize_and_simdlen
52014 #undef TARGET_SIMD_CLONE_ADJUST
52015 #define TARGET_SIMD_CLONE_ADJUST \
52016 ix86_simd_clone_adjust
52018 #undef TARGET_SIMD_CLONE_USABLE
52019 #define TARGET_SIMD_CLONE_USABLE \
52020 ix86_simd_clone_usable
52022 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
52023 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
52024 ix86_float_exceptions_rounding_supported_p
52026 #undef TARGET_MODE_EMIT
52027 #define TARGET_MODE_EMIT ix86_emit_mode_set
52029 #undef TARGET_MODE_NEEDED
52030 #define TARGET_MODE_NEEDED ix86_mode_needed
52032 #undef TARGET_MODE_AFTER
52033 #define TARGET_MODE_AFTER ix86_mode_after
52035 #undef TARGET_MODE_ENTRY
52036 #define TARGET_MODE_ENTRY ix86_mode_entry
52038 #undef TARGET_MODE_EXIT
52039 #define TARGET_MODE_EXIT ix86_mode_exit
52041 #undef TARGET_MODE_PRIORITY
52042 #define TARGET_MODE_PRIORITY ix86_mode_priority
52044 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
52045 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
52047 #undef TARGET_LOAD_BOUNDS_FOR_ARG
52048 #define TARGET_LOAD_BOUNDS_FOR_ARG ix86_load_bounds
52050 #undef TARGET_STORE_BOUNDS_FOR_ARG
52051 #define TARGET_STORE_BOUNDS_FOR_ARG ix86_store_bounds
52053 #undef TARGET_LOAD_RETURNED_BOUNDS
52054 #define TARGET_LOAD_RETURNED_BOUNDS ix86_load_returned_bounds
52056 #undef TARGET_STORE_RETURNED_BOUNDS
52057 #define TARGET_STORE_RETURNED_BOUNDS ix86_store_returned_bounds
52059 #undef TARGET_CHKP_BOUND_MODE
52060 #define TARGET_CHKP_BOUND_MODE ix86_mpx_bound_mode
52062 #undef TARGET_BUILTIN_CHKP_FUNCTION
52063 #define TARGET_BUILTIN_CHKP_FUNCTION ix86_builtin_mpx_function
52065 #undef TARGET_CHKP_FUNCTION_VALUE_BOUNDS
52066 #define TARGET_CHKP_FUNCTION_VALUE_BOUNDS ix86_function_value_bounds
52068 #undef TARGET_CHKP_MAKE_BOUNDS_CONSTANT
52069 #define TARGET_CHKP_MAKE_BOUNDS_CONSTANT ix86_make_bounds_constant
52071 #undef TARGET_CHKP_INITIALIZE_BOUNDS
52072 #define TARGET_CHKP_INITIALIZE_BOUNDS ix86_initialize_bounds
52074 #undef TARGET_SETUP_INCOMING_VARARG_BOUNDS
52075 #define TARGET_SETUP_INCOMING_VARARG_BOUNDS ix86_setup_incoming_vararg_bounds
52077 #undef TARGET_OFFLOAD_OPTIONS
52078 #define TARGET_OFFLOAD_OPTIONS \
52079 ix86_offload_options
52082 \f