| blob | b5aeaed16aa0f0c69d4d3e949936cc3647cce127 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2014 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;;
24 ;; REGNOS
25 ;;
27 (define_constants
28 [(FIRST_GPR_REGNO 0)
29 (STACK_POINTER_REGNUM 1)
30 (TOC_REGNUM 2)
31 (STATIC_CHAIN_REGNUM 11)
32 (HARD_FRAME_POINTER_REGNUM 31)
33 (LAST_GPR_REGNO 31)
34 (FIRST_FPR_REGNO 32)
35 (LAST_FPR_REGNO 63)
36 (LR_REGNO 65)
37 (CTR_REGNO 66)
38 (ARG_POINTER_REGNUM 67)
39 (CR0_REGNO 68)
40 (CR1_REGNO 69)
41 (CR2_REGNO 70)
42 (CR3_REGNO 71)
43 (CR4_REGNO 72)
44 (CR5_REGNO 73)
45 (CR6_REGNO 74)
46 (CR7_REGNO 75)
47 (MAX_CR_REGNO 75)
48 (CA_REGNO 76)
49 (FIRST_ALTIVEC_REGNO 77)
50 (LAST_ALTIVEC_REGNO 108)
51 (VRSAVE_REGNO 109)
52 (VSCR_REGNO 110)
53 (SPE_ACC_REGNO 111)
54 (SPEFSCR_REGNO 112)
55 (FRAME_POINTER_REGNUM 113)
56 (TFHAR_REGNO 114)
57 (TFIAR_REGNO 115)
58 (TEXASR_REGNO 116)
59 (FIRST_SPE_HIGH_REGNO 117)
60 (LAST_SPE_HIGH_REGNO 148)
61 ])
63 ;;
64 ;; UNSPEC usage
65 ;;
67 (define_c_enum "unspec"
68 [UNSPEC_FRSP ; frsp for POWER machines
69 UNSPEC_PROBE_STACK ; probe stack memory reference
70 UNSPEC_TOCPTR ; address of a word pointing to the TOC
71 UNSPEC_TOC ; address of the TOC (more-or-less)
72 UNSPEC_MOVSI_GOT
73 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
74 UNSPEC_FCTIWZ
75 UNSPEC_FRIM
76 UNSPEC_FRIN
77 UNSPEC_FRIP
78 UNSPEC_FRIZ
79 UNSPEC_LD_MPIC ; load_macho_picbase
80 UNSPEC_RELD_MPIC ; re-load_macho_picbase
81 UNSPEC_MPIC_CORRECT ; macho_correct_pic
82 UNSPEC_TLSGD
83 UNSPEC_TLSLD
84 UNSPEC_MOVESI_FROM_CR
85 UNSPEC_MOVESI_TO_CR
86 UNSPEC_TLSDTPREL
87 UNSPEC_TLSDTPRELHA
88 UNSPEC_TLSDTPRELLO
89 UNSPEC_TLSGOTDTPREL
90 UNSPEC_TLSTPREL
91 UNSPEC_TLSTPRELHA
92 UNSPEC_TLSTPRELLO
93 UNSPEC_TLSGOTTPREL
94 UNSPEC_TLSTLS
95 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
96 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
97 UNSPEC_STFIWX
98 UNSPEC_POPCNTB
99 UNSPEC_FRES
100 UNSPEC_SP_SET
101 UNSPEC_SP_TEST
102 UNSPEC_SYNC
103 UNSPEC_LWSYNC
104 UNSPEC_SYNC_OP
105 UNSPEC_ATOMIC
106 UNSPEC_CMPXCHG
107 UNSPEC_XCHG
108 UNSPEC_AND
109 UNSPEC_DLMZB
110 UNSPEC_DLMZB_CR
111 UNSPEC_DLMZB_STRLEN
112 UNSPEC_RSQRT
113 UNSPEC_TOCREL
114 UNSPEC_MACHOPIC_OFFSET
115 UNSPEC_BPERM
116 UNSPEC_COPYSIGN
117 UNSPEC_PARITY
118 UNSPEC_FCTIW
119 UNSPEC_FCTID
120 UNSPEC_LFIWAX
121 UNSPEC_LFIWZX
122 UNSPEC_FCTIWUZ
123 UNSPEC_GRP_END_NOP
124 UNSPEC_P8V_FMRGOW
125 UNSPEC_P8V_MTVSRWZ
126 UNSPEC_P8V_RELOAD_FROM_GPR
127 UNSPEC_P8V_MTVSRD
128 UNSPEC_P8V_XXPERMDI
129 UNSPEC_P8V_RELOAD_FROM_VSX
130 UNSPEC_ADDG6S
131 UNSPEC_CDTBCD
132 UNSPEC_CBCDTD
133 UNSPEC_DIVE
134 UNSPEC_DIVEO
135 UNSPEC_DIVEU
136 UNSPEC_DIVEUO
137 UNSPEC_UNPACK_128BIT
138 UNSPEC_PACK_128BIT
139 UNSPEC_LSQ
140 ])
142 ;;
143 ;; UNSPEC_VOLATILE usage
144 ;;
146 (define_c_enum "unspecv"
147 [UNSPECV_BLOCK
148 UNSPECV_LL ; load-locked
149 UNSPECV_SC ; store-conditional
150 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
151 UNSPECV_EH_RR ; eh_reg_restore
152 UNSPECV_ISYNC ; isync instruction
153 UNSPECV_MFTB ; move from time base
154 UNSPECV_NLGR ; non-local goto receiver
155 UNSPECV_MFFS ; Move from FPSCR
156 UNSPECV_MTFSF ; Move to FPSCR Fields
157 ])
159 \f
160 ;; Define an insn type attribute. This is used in function unit delay
161 ;; computations.
162 (define_attr "type"
163 "integer,two,three,
164 add,logical,shift,insert,
165 mul,halfmul,div,
166 exts,cntlz,popcnt,isel,
167 load,store,fpload,fpstore,vecload,vecstore,
168 cmp,
169 branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
170 compare,
171 cr_logical,delayed_cr,mfcr,mfcrf,mtcr,
172 fpcompare,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,
173 brinc,
174 vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
175 vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto,
176 htm"
177 (const_string "integer"))
179 ;; What data size does this instruction work on?
180 ;; This is used for insert, mul.
181 (define_attr "size" "8,16,32,64" (const_string "32"))
183 ;; Is this instruction record form ("dot", signed compare to 0, writing CR0)?
184 ;; This is used for add, logical, shift, exts, mul.
185 (define_attr "dot" "no,yes" (const_string "no"))
187 ;; Does this instruction sign-extend its result?
188 ;; This is used for load insns.
189 (define_attr "sign_extend" "no,yes" (const_string "no"))
191 ;; Does this instruction use indexed (that is, reg+reg) addressing?
192 ;; This is used for load and store insns. If operand 0 or 1 is a MEM
193 ;; it is automatically set based on that. If a load or store instruction
194 ;; has fewer than two operands it needs to set this attribute manually
195 ;; or the compiler will crash.
196 (define_attr "indexed" "no,yes"
197 (if_then_else (ior (match_operand 0 "indexed_address_mem")
198 (match_operand 1 "indexed_address_mem"))
199 (const_string "yes")
200 (const_string "no")))
202 ;; Does this instruction use update addressing?
203 ;; This is used for load and store insns. See the comments for "indexed".
204 (define_attr "update" "no,yes"
205 (if_then_else (ior (match_operand 0 "update_address_mem")
206 (match_operand 1 "update_address_mem"))
207 (const_string "yes")
208 (const_string "no")))
210 ;; Is this instruction using operands[2] as shift amount, and can that be a
211 ;; register?
212 ;; This is used for shift insns.
213 (define_attr "maybe_var_shift" "no,yes" (const_string "no"))
215 ;; Is this instruction using a shift amount from a register?
216 ;; This is used for shift insns.
217 (define_attr "var_shift" "no,yes"
218 (if_then_else (and (eq_attr "type" "shift")
219 (eq_attr "maybe_var_shift" "yes"))
220 (if_then_else (match_operand 2 "gpc_reg_operand")
221 (const_string "yes")
222 (const_string "no"))
223 (const_string "no")))
225 ;; Define floating point instruction sub-types for use with Xfpu.md
226 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
228 ;; Length (in bytes).
229 ; '(pc)' in the following doesn't include the instruction itself; it is
230 ; calculated as if the instruction had zero size.
231 (define_attr "length" ""
232 (if_then_else (eq_attr "type" "branch")
233 (if_then_else (and (ge (minus (match_dup 0) (pc))
234 (const_int -32768))
235 (lt (minus (match_dup 0) (pc))
236 (const_int 32764)))
237 (const_int 4)
238 (const_int 8))
239 (const_int 4)))
241 ;; Processor type -- this attribute must exactly match the processor_type
242 ;; enumeration in rs6000-opts.h.
243 (define_attr "cpu"
244 "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,
245 ppc750,ppc7400,ppc7450,
246 ppc403,ppc405,ppc440,ppc476,
247 ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
248 power4,power5,power6,power7,power8,
249 rs64a,mpccore,cell,ppca2,titan"
250 (const (symbol_ref "rs6000_cpu_attr")))
253 ;; If this instruction is microcoded on the CELL processor
254 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
255 (define_attr "cell_micro" "not,conditional,always"
256 (if_then_else (ior (eq_attr "type" "compare")
257 (and (eq_attr "type" "shift,exts,mul")
258 (eq_attr "dot" "yes"))
259 (and (eq_attr "type" "load")
260 (eq_attr "sign_extend" "yes"))
261 (and (eq_attr "type" "shift")
262 (eq_attr "var_shift" "yes")))
263 (const_string "always")
264 (const_string "not")))
266 (automata_option "ndfa")
268 (include "rs64.md")
269 (include "mpc.md")
270 (include "40x.md")
271 (include "440.md")
272 (include "476.md")
273 (include "601.md")
274 (include "603.md")
275 (include "6xx.md")
276 (include "7xx.md")
277 (include "7450.md")
278 (include "8540.md")
279 (include "e300c2c3.md")
280 (include "e500mc.md")
281 (include "e500mc64.md")
282 (include "e5500.md")
283 (include "e6500.md")
284 (include "power4.md")
285 (include "power5.md")
286 (include "power6.md")
287 (include "power7.md")
288 (include "power8.md")
289 (include "cell.md")
290 (include "xfpu.md")
291 (include "a2.md")
292 (include "titan.md")
294 (include "predicates.md")
295 (include "constraints.md")
297 (include "darwin.md")
299 \f
300 ;; Mode iterators
302 ; This mode iterator allows :GPR to be used to indicate the allowable size
303 ; of whole values in GPRs.
304 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
306 ; Any supported integer mode.
307 (define_mode_iterator INT [QI HI SI DI TI PTI])
309 ; Any supported integer mode that fits in one register.
310 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
312 ; Everything we can extend QImode to.
313 (define_mode_iterator EXTQI [HI SI (DI "TARGET_POWERPC64")])
315 ; Everything we can extend HImode to.
316 (define_mode_iterator EXTHI [SI (DI "TARGET_POWERPC64")])
318 ; Everything we can extend SImode to.
319 (define_mode_iterator EXTSI [(DI "TARGET_POWERPC64")])
321 ; QImode or HImode for small atomic ops
322 (define_mode_iterator QHI [QI HI])
324 ; HImode or SImode for sign extended fusion ops
325 (define_mode_iterator HSI [HI SI])
327 ; SImode or DImode, even if DImode doesn't fit in GPRs.
328 (define_mode_iterator SDI [SI DI])
330 ; The size of a pointer. Also, the size of the value that a record-condition
331 ; (one with a '.') will compare; and the size used for arithmetic carries.
332 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
334 ; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
335 ; PTImode is GPR only)
336 (define_mode_iterator TI2 [TI PTI])
338 ; Any hardware-supported floating-point mode
339 (define_mode_iterator FP [
340 (SF "TARGET_HARD_FLOAT
341 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
342 (DF "TARGET_HARD_FLOAT
343 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
344 (TF "!TARGET_IEEEQUAD
345 && TARGET_HARD_FLOAT
346 && (TARGET_FPRS || TARGET_E500_DOUBLE)
347 && TARGET_LONG_DOUBLE_128")
348 (DD "TARGET_DFP")
349 (TD "TARGET_DFP")])
351 ; Any fma capable floating-point mode.
352 (define_mode_iterator FMA_F [
353 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
354 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
355 || VECTOR_UNIT_VSX_P (DFmode)")
356 (V2SF "TARGET_PAIRED_FLOAT")
357 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
358 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
359 ])
361 ; Floating point move iterators to combine binary and decimal moves
362 (define_mode_iterator FMOVE32 [SF SD])
363 (define_mode_iterator FMOVE64 [DF DD])
364 (define_mode_iterator FMOVE64X [DI DF DD])
365 (define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128")
366 (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
368 ; Iterators for 128 bit types for direct move
369 (define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")
370 (V16QI "")
371 (V8HI "")
372 (V4SI "")
373 (V4SF "")
374 (V2DI "")
375 (V2DF "")
376 (V1TI "")])
378 ; Whether a floating point move is ok, don't allow SD without hardware FP
379 (define_mode_attr fmove_ok [(SF "")
380 (DF "")
381 (SD "TARGET_HARD_FLOAT && TARGET_FPRS")
382 (DD "")])
384 ; Convert REAL_VALUE to the appropriate bits
385 (define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")
386 (DF "REAL_VALUE_TO_TARGET_DOUBLE")
387 (SD "REAL_VALUE_TO_TARGET_DECIMAL32")
388 (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])
390 ; Definitions for load to 32-bit fpr register
391 (define_mode_attr f32_lr [(SF "f") (SD "wz")])
392 (define_mode_attr f32_lm [(SF "m") (SD "Z")])
393 (define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])
394 (define_mode_attr f32_lv [(SF "lxsspx %x0,%y1") (SD "lxsiwzx %x0,%y1")])
396 ; Definitions for store from 32-bit fpr register
397 (define_mode_attr f32_sr [(SF "f") (SD "wx")])
398 (define_mode_attr f32_sm [(SF "m") (SD "Z")])
399 (define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])
400 (define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])
402 ; Definitions for 32-bit fpr direct move
403 (define_mode_attr f32_dm [(SF "wn") (SD "wh")])
405 ; These modes do not fit in integer registers in 32-bit mode.
406 ; but on e500v2, the gpr are 64 bit registers
407 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
409 ; Iterator for reciprocal estimate instructions
410 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
412 ; Iterator for just SF/DF
413 (define_mode_iterator SFDF [SF DF])
415 ; SF/DF suffix for traditional floating instructions
416 (define_mode_attr Ftrad [(SF "s") (DF "")])
418 ; SF/DF suffix for VSX instructions
419 (define_mode_attr Fvsx [(SF "sp") (DF "dp")])
421 ; SF/DF constraint for arithmetic on traditional floating point registers
422 (define_mode_attr Ff [(SF "f") (DF "d")])
424 ; SF/DF constraint for arithmetic on VSX registers
425 (define_mode_attr Fv [(SF "wy") (DF "ws")])
427 ; s/d suffix for things like fp_addsub_s/fp_addsub_d
428 (define_mode_attr Fs [(SF "s") (DF "d")])
430 ; FRE/FRES support
431 (define_mode_attr Ffre [(SF "fres") (DF "fre")])
432 (define_mode_attr FFRE [(SF "FRES") (DF "FRE")])
434 ; Conditional returns.
435 (define_code_iterator any_return [return simple_return])
436 (define_code_attr return_pred [(return "direct_return ()")
437 (simple_return "1")])
438 (define_code_attr return_str [(return "") (simple_return "simple_")])
440 ; Signed/unsigned variants of ops.
441 (define_code_iterator any_extend [sign_extend zero_extend])
442 (define_code_attr u [(sign_extend "") (zero_extend "u")])
443 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
445 ; Various instructions that come in SI and DI forms.
446 ; A generic w/d attribute, for things like cmpw/cmpd.
447 (define_mode_attr wd [(QI "b")
448 (HI "h")
449 (SI "w")
450 (DI "d")
451 (V16QI "b")
452 (V8HI "h")
453 (V4SI "w")
454 (V2DI "d")])
456 ;; How many bits in this mode?
457 (define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64")])
459 ; DImode bits
460 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
462 ;; ISEL/ISEL64 target selection
463 (define_mode_attr sel [(SI "") (DI "64")])
465 ;; Bitmask for shift instructions
466 (define_mode_attr hH [(SI "h") (DI "H")])
468 ;; A mode twice the size of the given mode
469 (define_mode_attr dmode [(SI "di") (DI "ti")])
470 (define_mode_attr DMODE [(SI "DI") (DI "TI")])
472 ;; Suffix for reload patterns
473 (define_mode_attr ptrsize [(SI "32bit")
474 (DI "64bit")])
476 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
477 (DI "TARGET_64BIT")])
479 (define_mode_attr mptrsize [(SI "si")
480 (DI "di")])
482 (define_mode_attr ptrload [(SI "lwz")
483 (DI "ld")])
485 (define_mode_attr ptrm [(SI "m")
486 (DI "Y")])
488 (define_mode_attr rreg [(SF "f")
489 (DF "ws")
490 (TF "f")
491 (TD "f")
492 (V4SF "wf")
493 (V2DF "wd")])
495 (define_mode_attr rreg2 [(SF "f")
496 (DF "d")])
498 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
499 (DF "TARGET_FCFID")])
501 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
502 (DF "TARGET_E500_DOUBLE")])
504 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
505 (DF "TARGET_DOUBLE_FLOAT")])
507 ;; Mode iterator for logical operations on 128-bit types
508 (define_mode_iterator BOOL_128 [TI
509 PTI
510 (V16QI "TARGET_ALTIVEC")
511 (V8HI "TARGET_ALTIVEC")
512 (V4SI "TARGET_ALTIVEC")
513 (V4SF "TARGET_ALTIVEC")
514 (V2DI "TARGET_ALTIVEC")
515 (V2DF "TARGET_ALTIVEC")
516 (V1TI "TARGET_ALTIVEC")])
518 ;; For the GPRs we use 3 constraints for register outputs, two that are the
519 ;; same as the output register, and a third where the output register is an
520 ;; early clobber, so we don't have to deal with register overlaps. For the
521 ;; vector types, we prefer to use the vector registers. For TI mode, allow
522 ;; either.
524 ;; Mode attribute for boolean operation register constraints for output
525 (define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v")
526 (PTI "&r,r,r")
527 (V16QI "wa,v,&?r,?r,?r")
528 (V8HI "wa,v,&?r,?r,?r")
529 (V4SI "wa,v,&?r,?r,?r")
530 (V4SF "wa,v,&?r,?r,?r")
531 (V2DI "wa,v,&?r,?r,?r")
532 (V2DF "wa,v,&?r,?r,?r")
533 (V1TI "wa,v,&?r,?r,?r")])
535 ;; Mode attribute for boolean operation register constraints for operand1
536 (define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wa,v")
537 (PTI "r,0,r")
538 (V16QI "wa,v,r,0,r")
539 (V8HI "wa,v,r,0,r")
540 (V4SI "wa,v,r,0,r")
541 (V4SF "wa,v,r,0,r")
542 (V2DI "wa,v,r,0,r")
543 (V2DF "wa,v,r,0,r")
544 (V1TI "wa,v,r,0,r")])
546 ;; Mode attribute for boolean operation register constraints for operand2
547 (define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wa,v")
548 (PTI "r,r,0")
549 (V16QI "wa,v,r,r,0")
550 (V8HI "wa,v,r,r,0")
551 (V4SI "wa,v,r,r,0")
552 (V4SF "wa,v,r,r,0")
553 (V2DI "wa,v,r,r,0")
554 (V2DF "wa,v,r,r,0")
555 (V1TI "wa,v,r,r,0")])
557 ;; Mode attribute for boolean operation register constraints for operand1
558 ;; for one_cmpl. To simplify things, we repeat the constraint where 0
559 ;; is used for operand1 or operand2
560 (define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v")
561 (PTI "r,0,0")
562 (V16QI "wa,v,r,0,0")
563 (V8HI "wa,v,r,0,0")
564 (V4SI "wa,v,r,0,0")
565 (V4SF "wa,v,r,0,0")
566 (V2DI "wa,v,r,0,0")
567 (V2DF "wa,v,r,0,0")
568 (V1TI "wa,v,r,0,0")])
569 \f
570 ;; Start with fixed-point load and store insns. Here we put only the more
571 ;; complex forms. Basic data transfer is done later.
573 (define_insn "zero_extendqi<mode>2"
574 [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
575 (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
576 ""
577 "@
578 lbz%U1%X1 %0,%1
579 rlwinm %0,%1,0,0xff"
580 [(set_attr "type" "load,shift")])
582 (define_insn_and_split "*zero_extendqi<mode>2_dot"
583 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
584 (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
585 (const_int 0)))
586 (clobber (match_scratch:EXTQI 0 "=r,r"))]
587 "rs6000_gen_cell_microcode"
588 "@
589 andi. %0,%1,0xff
590 #"
591 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
592 [(set (match_dup 0)
593 (zero_extend:EXTQI (match_dup 1)))
594 (set (match_dup 2)
595 (compare:CC (match_dup 0)
596 (const_int 0)))]
597 ""
598 [(set_attr "type" "logical")
599 (set_attr "dot" "yes")
600 (set_attr "length" "4,8")])
602 (define_insn_and_split "*zero_extendqi<mode>2_dot2"
603 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
604 (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
605 (const_int 0)))
606 (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
607 (zero_extend:EXTQI (match_dup 1)))]
608 "rs6000_gen_cell_microcode"
609 "@
610 andi. %0,%1,0xff
611 #"
612 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
613 [(set (match_dup 0)
614 (zero_extend:EXTQI (match_dup 1)))
615 (set (match_dup 2)
616 (compare:CC (match_dup 0)
617 (const_int 0)))]
618 ""
619 [(set_attr "type" "logical")
620 (set_attr "dot" "yes")
621 (set_attr "length" "4,8")])
624 (define_insn "zero_extendhi<mode>2"
625 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
626 (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
627 ""
628 "@
629 lhz%U1%X1 %0,%1
630 rlwinm %0,%1,0,0xffff"
631 [(set_attr "type" "load,shift")])
633 (define_insn_and_split "*zero_extendhi<mode>2_dot"
634 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
635 (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
636 (const_int 0)))
637 (clobber (match_scratch:EXTHI 0 "=r,r"))]
638 "rs6000_gen_cell_microcode"
639 "@
640 andi. %0,%1,0xffff
641 #"
642 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
643 [(set (match_dup 0)
644 (zero_extend:EXTHI (match_dup 1)))
645 (set (match_dup 2)
646 (compare:CC (match_dup 0)
647 (const_int 0)))]
648 ""
649 [(set_attr "type" "logical")
650 (set_attr "dot" "yes")
651 (set_attr "length" "4,8")])
653 (define_insn_and_split "*zero_extendhi<mode>2_dot2"
654 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
655 (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
656 (const_int 0)))
657 (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
658 (zero_extend:EXTHI (match_dup 1)))]
659 "rs6000_gen_cell_microcode"
660 "@
661 andi. %0,%1,0xffff
662 #"
663 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
664 [(set (match_dup 0)
665 (zero_extend:EXTHI (match_dup 1)))
666 (set (match_dup 2)
667 (compare:CC (match_dup 0)
668 (const_int 0)))]
669 ""
670 [(set_attr "type" "logical")
671 (set_attr "dot" "yes")
672 (set_attr "length" "4,8")])
675 (define_insn "zero_extendsi<mode>2"
676 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu")
677 (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
678 ""
679 "@
680 lwz%U1%X1 %0,%1
681 rldicl %0,%1,0,32
682 mtvsrwz %x0,%1
683 lfiwzx %0,%y1
684 lxsiwzx %x0,%y1"
685 [(set_attr "type" "load,shift,mffgpr,fpload,fpload")])
687 (define_insn_and_split "*zero_extendsi<mode>2_dot"
688 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
689 (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
690 (const_int 0)))
691 (clobber (match_scratch:EXTSI 0 "=r,r"))]
692 "rs6000_gen_cell_microcode"
693 "@
694 rldicl. %0,%1,0,32
695 #"
696 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
697 [(set (match_dup 0)
698 (zero_extend:DI (match_dup 1)))
699 (set (match_dup 2)
700 (compare:CC (match_dup 0)
701 (const_int 0)))]
702 ""
703 [(set_attr "type" "shift")
704 (set_attr "dot" "yes")
705 (set_attr "length" "4,8")])
707 (define_insn_and_split "*zero_extendsi<mode>2_dot2"
708 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
709 (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
710 (const_int 0)))
711 (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
712 (zero_extend:EXTSI (match_dup 1)))]
713 "rs6000_gen_cell_microcode"
714 "@
715 rldicl. %0,%1,0,32
716 #"
717 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
718 [(set (match_dup 0)
719 (zero_extend:EXTSI (match_dup 1)))
720 (set (match_dup 2)
721 (compare:CC (match_dup 0)
722 (const_int 0)))]
723 ""
724 [(set_attr "type" "shift")
725 (set_attr "dot" "yes")
726 (set_attr "length" "4,8")])
729 (define_insn "extendqi<mode>2"
730 [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r")
731 (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r")))]
732 ""
733 "extsb %0,%1"
734 [(set_attr "type" "exts")])
736 (define_insn_and_split "*extendqi<mode>2_dot"
737 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
738 (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
739 (const_int 0)))
740 (clobber (match_scratch:EXTQI 0 "=r,r"))]
741 "rs6000_gen_cell_microcode"
742 "@
743 extsb. %0,%1
744 #"
745 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
746 [(set (match_dup 0)
747 (sign_extend:EXTQI (match_dup 1)))
748 (set (match_dup 2)
749 (compare:CC (match_dup 0)
750 (const_int 0)))]
751 ""
752 [(set_attr "type" "exts")
753 (set_attr "dot" "yes")
754 (set_attr "length" "4,8")])
756 (define_insn_and_split "*extendqi<mode>2_dot2"
757 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
758 (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
759 (const_int 0)))
760 (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
761 (sign_extend:EXTQI (match_dup 1)))]
762 "rs6000_gen_cell_microcode"
763 "@
764 extsb. %0,%1
765 #"
766 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
767 [(set (match_dup 0)
768 (sign_extend:EXTQI (match_dup 1)))
769 (set (match_dup 2)
770 (compare:CC (match_dup 0)
771 (const_int 0)))]
772 ""
773 [(set_attr "type" "exts")
774 (set_attr "dot" "yes")
775 (set_attr "length" "4,8")])
778 (define_expand "extendhi<mode>2"
779 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "")
780 (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "")))]
781 ""
782 "")
784 (define_insn "*extendhi<mode>2"
785 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
786 (sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
787 "rs6000_gen_cell_microcode"
788 "@
789 lha%U1%X1 %0,%1
790 extsh %0,%1"
791 [(set_attr "type" "load,exts")
792 (set_attr "sign_extend" "yes")])
794 (define_insn "*extendhi<mode>2_noload"
795 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r")
796 (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r")))]
797 "!rs6000_gen_cell_microcode"
798 "extsh %0,%1"
799 [(set_attr "type" "exts")])
801 (define_insn_and_split "*extendhi<mode>2_dot"
802 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
803 (compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
804 (const_int 0)))
805 (clobber (match_scratch:EXTHI 0 "=r,r"))]
806 "rs6000_gen_cell_microcode"
807 "@
808 extsh. %0,%1
809 #"
810 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
811 [(set (match_dup 0)
812 (sign_extend:EXTHI (match_dup 1)))
813 (set (match_dup 2)
814 (compare:CC (match_dup 0)
815 (const_int 0)))]
816 ""
817 [(set_attr "type" "exts")
818 (set_attr "dot" "yes")
819 (set_attr "length" "4,8")])
821 (define_insn_and_split "*extendhi<mode>2_dot2"
822 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
823 (compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
824 (const_int 0)))
825 (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
826 (sign_extend:EXTHI (match_dup 1)))]
827 "rs6000_gen_cell_microcode"
828 "@
829 extsh. %0,%1
830 #"
831 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
832 [(set (match_dup 0)
833 (sign_extend:EXTHI (match_dup 1)))
834 (set (match_dup 2)
835 (compare:CC (match_dup 0)
836 (const_int 0)))]
837 ""
838 [(set_attr "type" "exts")
839 (set_attr "dot" "yes")
840 (set_attr "length" "4,8")])
843 (define_insn "extendsi<mode>2"
844 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wl,!wu")
845 (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))]
846 ""
847 "@
848 lwa%U1%X1 %0,%1
849 extsw %0,%1
850 mtvsrwa %x0,%1
851 lfiwax %0,%y1
852 lxsiwax %x0,%y1"
853 [(set_attr "type" "load,exts,mffgpr,fpload,fpload")
854 (set_attr "sign_extend" "yes")])
856 (define_insn_and_split "*extendsi<mode>2_dot"
857 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
858 (compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
859 (const_int 0)))
860 (clobber (match_scratch:EXTSI 0 "=r,r"))]
861 "rs6000_gen_cell_microcode"
862 "@
863 extsw. %0,%1
864 #"
865 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
866 [(set (match_dup 0)
867 (sign_extend:EXTSI (match_dup 1)))
868 (set (match_dup 2)
869 (compare:CC (match_dup 0)
870 (const_int 0)))]
871 ""
872 [(set_attr "type" "exts")
873 (set_attr "dot" "yes")
874 (set_attr "length" "4,8")])
876 (define_insn_and_split "*extendsi<mode>2_dot2"
877 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
878 (compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
879 (const_int 0)))
880 (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
881 (sign_extend:EXTSI (match_dup 1)))]
882 "rs6000_gen_cell_microcode"
883 "@
884 extsw. %0,%1
885 #"
886 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
887 [(set (match_dup 0)
888 (sign_extend:EXTSI (match_dup 1)))
889 (set (match_dup 2)
890 (compare:CC (match_dup 0)
891 (const_int 0)))]
892 ""
893 [(set_attr "type" "exts")
894 (set_attr "dot" "yes")
895 (set_attr "length" "4,8")])
896 \f
897 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
899 (define_insn "*macchwc"
900 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
901 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
902 (match_operand:SI 2 "gpc_reg_operand" "r")
903 (const_int 16))
904 (sign_extend:SI
905 (match_operand:HI 1 "gpc_reg_operand" "r")))
906 (match_operand:SI 4 "gpc_reg_operand" "0"))
907 (const_int 0)))
908 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
909 (plus:SI (mult:SI (ashiftrt:SI
910 (match_dup 2)
911 (const_int 16))
912 (sign_extend:SI
913 (match_dup 1)))
914 (match_dup 4)))]
915 "TARGET_MULHW"
916 "macchw. %0,%1,%2"
917 [(set_attr "type" "halfmul")])
919 (define_insn "*macchw"
920 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
921 (plus:SI (mult:SI (ashiftrt:SI
922 (match_operand:SI 2 "gpc_reg_operand" "r")
923 (const_int 16))
924 (sign_extend:SI
925 (match_operand:HI 1 "gpc_reg_operand" "r")))
926 (match_operand:SI 3 "gpc_reg_operand" "0")))]
927 "TARGET_MULHW"
928 "macchw %0,%1,%2"
929 [(set_attr "type" "halfmul")])
931 (define_insn "*macchwuc"
932 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
933 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
934 (match_operand:SI 2 "gpc_reg_operand" "r")
935 (const_int 16))
936 (zero_extend:SI
937 (match_operand:HI 1 "gpc_reg_operand" "r")))
938 (match_operand:SI 4 "gpc_reg_operand" "0"))
939 (const_int 0)))
940 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
941 (plus:SI (mult:SI (lshiftrt:SI
942 (match_dup 2)
943 (const_int 16))
944 (zero_extend:SI
945 (match_dup 1)))
946 (match_dup 4)))]
947 "TARGET_MULHW"
948 "macchwu. %0,%1,%2"
949 [(set_attr "type" "halfmul")])
951 (define_insn "*macchwu"
952 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
953 (plus:SI (mult:SI (lshiftrt:SI
954 (match_operand:SI 2 "gpc_reg_operand" "r")
955 (const_int 16))
956 (zero_extend:SI
957 (match_operand:HI 1 "gpc_reg_operand" "r")))
958 (match_operand:SI 3 "gpc_reg_operand" "0")))]
959 "TARGET_MULHW"
960 "macchwu %0,%1,%2"
961 [(set_attr "type" "halfmul")])
963 (define_insn "*machhwc"
964 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
965 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
966 (match_operand:SI 1 "gpc_reg_operand" "%r")
967 (const_int 16))
968 (ashiftrt:SI
969 (match_operand:SI 2 "gpc_reg_operand" "r")
970 (const_int 16)))
971 (match_operand:SI 4 "gpc_reg_operand" "0"))
972 (const_int 0)))
973 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
974 (plus:SI (mult:SI (ashiftrt:SI
975 (match_dup 1)
976 (const_int 16))
977 (ashiftrt:SI
978 (match_dup 2)
979 (const_int 16)))
980 (match_dup 4)))]
981 "TARGET_MULHW"
982 "machhw. %0,%1,%2"
983 [(set_attr "type" "halfmul")])
985 (define_insn "*machhw"
986 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
987 (plus:SI (mult:SI (ashiftrt:SI
988 (match_operand:SI 1 "gpc_reg_operand" "%r")
989 (const_int 16))
990 (ashiftrt:SI
991 (match_operand:SI 2 "gpc_reg_operand" "r")
992 (const_int 16)))
993 (match_operand:SI 3 "gpc_reg_operand" "0")))]
994 "TARGET_MULHW"
995 "machhw %0,%1,%2"
996 [(set_attr "type" "halfmul")])
998 (define_insn "*machhwuc"
999 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1000 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1001 (match_operand:SI 1 "gpc_reg_operand" "%r")
1002 (const_int 16))
1003 (lshiftrt:SI
1004 (match_operand:SI 2 "gpc_reg_operand" "r")
1005 (const_int 16)))
1006 (match_operand:SI 4 "gpc_reg_operand" "0"))
1007 (const_int 0)))
1008 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1009 (plus:SI (mult:SI (lshiftrt:SI
1010 (match_dup 1)
1011 (const_int 16))
1012 (lshiftrt:SI
1013 (match_dup 2)
1014 (const_int 16)))
1015 (match_dup 4)))]
1016 "TARGET_MULHW"
1017 "machhwu. %0,%1,%2"
1018 [(set_attr "type" "halfmul")])
1020 (define_insn "*machhwu"
1021 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1022 (plus:SI (mult:SI (lshiftrt:SI
1023 (match_operand:SI 1 "gpc_reg_operand" "%r")
1024 (const_int 16))
1025 (lshiftrt:SI
1026 (match_operand:SI 2 "gpc_reg_operand" "r")
1027 (const_int 16)))
1028 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1029 "TARGET_MULHW"
1030 "machhwu %0,%1,%2"
1031 [(set_attr "type" "halfmul")])
1033 (define_insn "*maclhwc"
1034 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1035 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1036 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1037 (sign_extend:SI
1038 (match_operand:HI 2 "gpc_reg_operand" "r")))
1039 (match_operand:SI 4 "gpc_reg_operand" "0"))
1040 (const_int 0)))
1041 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1042 (plus:SI (mult:SI (sign_extend:SI
1043 (match_dup 1))
1044 (sign_extend:SI
1045 (match_dup 2)))
1046 (match_dup 4)))]
1047 "TARGET_MULHW"
1048 "maclhw. %0,%1,%2"
1049 [(set_attr "type" "halfmul")])
1051 (define_insn "*maclhw"
1052 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1053 (plus:SI (mult:SI (sign_extend:SI
1054 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1055 (sign_extend:SI
1056 (match_operand:HI 2 "gpc_reg_operand" "r")))
1057 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1058 "TARGET_MULHW"
1059 "maclhw %0,%1,%2"
1060 [(set_attr "type" "halfmul")])
1062 (define_insn "*maclhwuc"
1063 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1064 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1065 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1066 (zero_extend:SI
1067 (match_operand:HI 2 "gpc_reg_operand" "r")))
1068 (match_operand:SI 4 "gpc_reg_operand" "0"))
1069 (const_int 0)))
1070 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1071 (plus:SI (mult:SI (zero_extend:SI
1072 (match_dup 1))
1073 (zero_extend:SI
1074 (match_dup 2)))
1075 (match_dup 4)))]
1076 "TARGET_MULHW"
1077 "maclhwu. %0,%1,%2"
1078 [(set_attr "type" "halfmul")])
1080 (define_insn "*maclhwu"
1081 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1082 (plus:SI (mult:SI (zero_extend:SI
1083 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1084 (zero_extend:SI
1085 (match_operand:HI 2 "gpc_reg_operand" "r")))
1086 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1087 "TARGET_MULHW"
1088 "maclhwu %0,%1,%2"
1089 [(set_attr "type" "halfmul")])
1091 (define_insn "*nmacchwc"
1092 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1093 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1094 (mult:SI (ashiftrt:SI
1095 (match_operand:SI 2 "gpc_reg_operand" "r")
1096 (const_int 16))
1097 (sign_extend:SI
1098 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1099 (const_int 0)))
1100 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1101 (minus:SI (match_dup 4)
1102 (mult:SI (ashiftrt:SI
1103 (match_dup 2)
1104 (const_int 16))
1105 (sign_extend:SI
1106 (match_dup 1)))))]
1107 "TARGET_MULHW"
1108 "nmacchw. %0,%1,%2"
1109 [(set_attr "type" "halfmul")])
1111 (define_insn "*nmacchw"
1112 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1113 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1114 (mult:SI (ashiftrt:SI
1115 (match_operand:SI 2 "gpc_reg_operand" "r")
1116 (const_int 16))
1117 (sign_extend:SI
1118 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1119 "TARGET_MULHW"
1120 "nmacchw %0,%1,%2"
1121 [(set_attr "type" "halfmul")])
1123 (define_insn "*nmachhwc"
1124 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1125 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1126 (mult:SI (ashiftrt:SI
1127 (match_operand:SI 1 "gpc_reg_operand" "%r")
1128 (const_int 16))
1129 (ashiftrt:SI
1130 (match_operand:SI 2 "gpc_reg_operand" "r")
1131 (const_int 16))))
1132 (const_int 0)))
1133 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1134 (minus:SI (match_dup 4)
1135 (mult:SI (ashiftrt:SI
1136 (match_dup 1)
1137 (const_int 16))
1138 (ashiftrt:SI
1139 (match_dup 2)
1140 (const_int 16)))))]
1141 "TARGET_MULHW"
1142 "nmachhw. %0,%1,%2"
1143 [(set_attr "type" "halfmul")])
1145 (define_insn "*nmachhw"
1146 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1147 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1148 (mult:SI (ashiftrt:SI
1149 (match_operand:SI 1 "gpc_reg_operand" "%r")
1150 (const_int 16))
1151 (ashiftrt:SI
1152 (match_operand:SI 2 "gpc_reg_operand" "r")
1153 (const_int 16)))))]
1154 "TARGET_MULHW"
1155 "nmachhw %0,%1,%2"
1156 [(set_attr "type" "halfmul")])
1158 (define_insn "*nmaclhwc"
1159 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1160 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1161 (mult:SI (sign_extend:SI
1162 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1163 (sign_extend:SI
1164 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1165 (const_int 0)))
1166 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1167 (minus:SI (match_dup 4)
1168 (mult:SI (sign_extend:SI
1169 (match_dup 1))
1170 (sign_extend:SI
1171 (match_dup 2)))))]
1172 "TARGET_MULHW"
1173 "nmaclhw. %0,%1,%2"
1174 [(set_attr "type" "halfmul")])
1176 (define_insn "*nmaclhw"
1177 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1178 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1179 (mult:SI (sign_extend:SI
1180 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1181 (sign_extend:SI
1182 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1183 "TARGET_MULHW"
1184 "nmaclhw %0,%1,%2"
1185 [(set_attr "type" "halfmul")])
1187 (define_insn "*mulchwc"
1188 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1189 (compare:CC (mult:SI (ashiftrt:SI
1190 (match_operand:SI 2 "gpc_reg_operand" "r")
1191 (const_int 16))
1192 (sign_extend:SI
1193 (match_operand:HI 1 "gpc_reg_operand" "r")))
1194 (const_int 0)))
1195 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1196 (mult:SI (ashiftrt:SI
1197 (match_dup 2)
1198 (const_int 16))
1199 (sign_extend:SI
1200 (match_dup 1))))]
1201 "TARGET_MULHW"
1202 "mulchw. %0,%1,%2"
1203 [(set_attr "type" "halfmul")])
1205 (define_insn "*mulchw"
1206 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1207 (mult:SI (ashiftrt:SI
1208 (match_operand:SI 2 "gpc_reg_operand" "r")
1209 (const_int 16))
1210 (sign_extend:SI
1211 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1212 "TARGET_MULHW"
1213 "mulchw %0,%1,%2"
1214 [(set_attr "type" "halfmul")])
1216 (define_insn "*mulchwuc"
1217 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1218 (compare:CC (mult:SI (lshiftrt:SI
1219 (match_operand:SI 2 "gpc_reg_operand" "r")
1220 (const_int 16))
1221 (zero_extend:SI
1222 (match_operand:HI 1 "gpc_reg_operand" "r")))
1223 (const_int 0)))
1224 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1225 (mult:SI (lshiftrt:SI
1226 (match_dup 2)
1227 (const_int 16))
1228 (zero_extend:SI
1229 (match_dup 1))))]
1230 "TARGET_MULHW"
1231 "mulchwu. %0,%1,%2"
1232 [(set_attr "type" "halfmul")])
1234 (define_insn "*mulchwu"
1235 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1236 (mult:SI (lshiftrt:SI
1237 (match_operand:SI 2 "gpc_reg_operand" "r")
1238 (const_int 16))
1239 (zero_extend:SI
1240 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1241 "TARGET_MULHW"
1242 "mulchwu %0,%1,%2"
1243 [(set_attr "type" "halfmul")])
1245 (define_insn "*mulhhwc"
1246 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1247 (compare:CC (mult:SI (ashiftrt:SI
1248 (match_operand:SI 1 "gpc_reg_operand" "%r")
1249 (const_int 16))
1250 (ashiftrt:SI
1251 (match_operand:SI 2 "gpc_reg_operand" "r")
1252 (const_int 16)))
1253 (const_int 0)))
1254 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1255 (mult:SI (ashiftrt:SI
1256 (match_dup 1)
1257 (const_int 16))
1258 (ashiftrt:SI
1259 (match_dup 2)
1260 (const_int 16))))]
1261 "TARGET_MULHW"
1262 "mulhhw. %0,%1,%2"
1263 [(set_attr "type" "halfmul")])
1265 (define_insn "*mulhhw"
1266 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1267 (mult:SI (ashiftrt:SI
1268 (match_operand:SI 1 "gpc_reg_operand" "%r")
1269 (const_int 16))
1270 (ashiftrt:SI
1271 (match_operand:SI 2 "gpc_reg_operand" "r")
1272 (const_int 16))))]
1273 "TARGET_MULHW"
1274 "mulhhw %0,%1,%2"
1275 [(set_attr "type" "halfmul")])
1277 (define_insn "*mulhhwuc"
1278 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1279 (compare:CC (mult:SI (lshiftrt:SI
1280 (match_operand:SI 1 "gpc_reg_operand" "%r")
1281 (const_int 16))
1282 (lshiftrt:SI
1283 (match_operand:SI 2 "gpc_reg_operand" "r")
1284 (const_int 16)))
1285 (const_int 0)))
1286 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1287 (mult:SI (lshiftrt:SI
1288 (match_dup 1)
1289 (const_int 16))
1290 (lshiftrt:SI
1291 (match_dup 2)
1292 (const_int 16))))]
1293 "TARGET_MULHW"
1294 "mulhhwu. %0,%1,%2"
1295 [(set_attr "type" "halfmul")])
1297 (define_insn "*mulhhwu"
1298 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1299 (mult:SI (lshiftrt:SI
1300 (match_operand:SI 1 "gpc_reg_operand" "%r")
1301 (const_int 16))
1302 (lshiftrt:SI
1303 (match_operand:SI 2 "gpc_reg_operand" "r")
1304 (const_int 16))))]
1305 "TARGET_MULHW"
1306 "mulhhwu %0,%1,%2"
1307 [(set_attr "type" "halfmul")])
1309 (define_insn "*mullhwc"
1310 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1311 (compare:CC (mult:SI (sign_extend:SI
1312 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1313 (sign_extend:SI
1314 (match_operand:HI 2 "gpc_reg_operand" "r")))
1315 (const_int 0)))
1316 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1317 (mult:SI (sign_extend:SI
1318 (match_dup 1))
1319 (sign_extend:SI
1320 (match_dup 2))))]
1321 "TARGET_MULHW"
1322 "mullhw. %0,%1,%2"
1323 [(set_attr "type" "halfmul")])
1325 (define_insn "*mullhw"
1326 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1327 (mult:SI (sign_extend:SI
1328 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1329 (sign_extend:SI
1330 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1331 "TARGET_MULHW"
1332 "mullhw %0,%1,%2"
1333 [(set_attr "type" "halfmul")])
1335 (define_insn "*mullhwuc"
1336 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1337 (compare:CC (mult:SI (zero_extend:SI
1338 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1339 (zero_extend:SI
1340 (match_operand:HI 2 "gpc_reg_operand" "r")))
1341 (const_int 0)))
1342 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1343 (mult:SI (zero_extend:SI
1344 (match_dup 1))
1345 (zero_extend:SI
1346 (match_dup 2))))]
1347 "TARGET_MULHW"
1348 "mullhwu. %0,%1,%2"
1349 [(set_attr "type" "halfmul")])
1351 (define_insn "*mullhwu"
1352 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1353 (mult:SI (zero_extend:SI
1354 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1355 (zero_extend:SI
1356 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1357 "TARGET_MULHW"
1358 "mullhwu %0,%1,%2"
1359 [(set_attr "type" "halfmul")])
1360 \f
1361 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1362 (define_insn "dlmzb"
1363 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1364 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1365 (match_operand:SI 2 "gpc_reg_operand" "r")]
1366 UNSPEC_DLMZB_CR))
1367 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1368 (unspec:SI [(match_dup 1)
1369 (match_dup 2)]
1370 UNSPEC_DLMZB))]
1371 "TARGET_DLMZB"
1372 "dlmzb. %0,%1,%2")
1374 (define_expand "strlensi"
1375 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1376 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1377 (match_operand:QI 2 "const_int_operand" "")
1378 (match_operand 3 "const_int_operand" "")]
1379 UNSPEC_DLMZB_STRLEN))
1380 (clobber (match_scratch:CC 4 "=x"))]
1381 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1382 {
1383 rtx result = operands[0];
1384 rtx src = operands[1];
1385 rtx search_char = operands[2];
1386 rtx align = operands[3];
1387 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1388 rtx loop_label, end_label, mem, cr0, cond;
1389 if (search_char != const0_rtx
1390 || GET_CODE (align) != CONST_INT
1391 || INTVAL (align) < 8)
1392 FAIL;
1393 word1 = gen_reg_rtx (SImode);
1394 word2 = gen_reg_rtx (SImode);
1395 scratch_dlmzb = gen_reg_rtx (SImode);
1396 scratch_string = gen_reg_rtx (Pmode);
1397 loop_label = gen_label_rtx ();
1398 end_label = gen_label_rtx ();
1399 addr = force_reg (Pmode, XEXP (src, 0));
1400 emit_move_insn (scratch_string, addr);
1401 emit_label (loop_label);
1402 mem = change_address (src, SImode, scratch_string);
1403 emit_move_insn (word1, mem);
1404 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1405 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1406 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1407 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1408 emit_jump_insn (gen_rtx_SET (VOIDmode,
1409 pc_rtx,
1410 gen_rtx_IF_THEN_ELSE (VOIDmode,
1411 cond,
1412 gen_rtx_LABEL_REF
1413 (VOIDmode,
1414 end_label),
1415 pc_rtx)));
1416 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1417 emit_jump_insn (gen_rtx_SET (VOIDmode,
1418 pc_rtx,
1419 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1420 emit_barrier ();
1421 emit_label (end_label);
1422 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1423 emit_insn (gen_subsi3 (result, scratch_string, addr));
1424 emit_insn (gen_subsi3 (result, result, const1_rtx));
1425 DONE;
1426 })
1427 \f
1428 ;; Fixed-point arithmetic insns.
1430 (define_expand "add<mode>3"
1431 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1432 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1433 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1434 ""
1435 {
1436 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1437 {
1438 if (non_short_cint_operand (operands[2], DImode))
1439 FAIL;
1440 }
1441 else if (GET_CODE (operands[2]) == CONST_INT
1442 && ! add_operand (operands[2], <MODE>mode))
1443 {
1444 rtx tmp = ((!can_create_pseudo_p ()
1445 || rtx_equal_p (operands[0], operands[1]))
1446 ? operands[0] : gen_reg_rtx (<MODE>mode));
1448 HOST_WIDE_INT val = INTVAL (operands[2]);
1449 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1450 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1452 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1453 FAIL;
1455 /* The ordering here is important for the prolog expander.
1456 When space is allocated from the stack, adding 'low' first may
1457 produce a temporary deallocation (which would be bad). */
1458 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1459 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1460 DONE;
1461 }
1462 })
1464 ;; Discourage ai/addic because of carry but provide it in an alternative
1465 ;; allowing register zero as source.
1466 (define_insn "*add<mode>3_internal1"
1467 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1468 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1469 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1470 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1471 "@
1472 add %0,%1,%2
1473 addi %0,%1,%2
1474 addic %0,%1,%2
1475 addis %0,%1,%v2"
1476 [(set_attr "type" "add")])
1478 (define_insn "addsi3_high"
1479 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1480 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1481 (high:SI (match_operand 2 "" ""))))]
1482 "TARGET_MACHO && !TARGET_64BIT"
1483 "addis %0,%1,ha16(%2)"
1484 [(set_attr "type" "add")])
1486 (define_insn "*add<mode>3_internal2"
1487 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1488 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1489 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1490 (const_int 0)))
1491 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1492 ""
1493 "@
1494 add. %3,%1,%2
1495 addic. %3,%1,%2
1496 #
1497 #"
1498 [(set_attr "type" "add,compare,compare,compare")
1499 (set_attr "dot" "yes")
1500 (set_attr "length" "4,4,8,8")])
1502 (define_split
1503 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1504 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1505 (match_operand:GPR 2 "reg_or_short_operand" ""))
1506 (const_int 0)))
1507 (clobber (match_scratch:GPR 3 ""))]
1508 "reload_completed"
1509 [(set (match_dup 3)
1510 (plus:GPR (match_dup 1)
1511 (match_dup 2)))
1512 (set (match_dup 0)
1513 (compare:CC (match_dup 3)
1514 (const_int 0)))]
1515 "")
1517 (define_insn "*add<mode>3_internal3"
1518 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1519 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1520 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1521 (const_int 0)))
1522 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1523 (plus:P (match_dup 1)
1524 (match_dup 2)))]
1525 ""
1526 "@
1527 add. %0,%1,%2
1528 addic. %0,%1,%2
1529 #
1530 #"
1531 [(set_attr "type" "add,compare,compare,compare")
1532 (set_attr "dot" "yes")
1533 (set_attr "length" "4,4,8,8")])
1535 (define_split
1536 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1537 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1538 (match_operand:P 2 "reg_or_short_operand" ""))
1539 (const_int 0)))
1540 (set (match_operand:P 0 "gpc_reg_operand" "")
1541 (plus:P (match_dup 1) (match_dup 2)))]
1542 "reload_completed"
1543 [(set (match_dup 0)
1544 (plus:P (match_dup 1)
1545 (match_dup 2)))
1546 (set (match_dup 3)
1547 (compare:CC (match_dup 0)
1548 (const_int 0)))]
1549 "")
1551 ;; Split an add that we can't do in one insn into two insns, each of which
1552 ;; does one 16-bit part. This is used by combine. Note that the low-order
1553 ;; add should be last in case the result gets used in an address.
1555 (define_split
1556 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1557 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1558 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1559 ""
1560 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1561 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1562 {
1563 HOST_WIDE_INT val = INTVAL (operands[2]);
1564 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1565 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1567 operands[4] = GEN_INT (low);
1568 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1569 operands[3] = GEN_INT (rest);
1570 else if (can_create_pseudo_p ())
1571 {
1572 operands[3] = gen_reg_rtx (DImode);
1573 emit_move_insn (operands[3], operands[2]);
1574 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1575 DONE;
1576 }
1577 else
1578 FAIL;
1579 })
1581 (define_expand "one_cmpl<mode>2"
1582 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1583 (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1584 ""
1585 {
1586 if (<MODE>mode == DImode && !TARGET_POWERPC64)
1587 {
1588 rs6000_split_logical (operands, NOT, false, false, false);
1589 DONE;
1590 }
1591 })
1593 (define_insn "*one_cmpl<mode>2"
1594 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1595 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1596 ""
1597 "nor %0,%1,%1")
1599 (define_insn ""
1600 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1601 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1602 (const_int 0)))
1603 (clobber (match_scratch:P 2 "=r,r"))]
1604 ""
1605 "@
1606 nor. %2,%1,%1
1607 #"
1608 [(set_attr "type" "logical,compare")
1609 (set_attr "dot" "yes")
1610 (set_attr "length" "4,8")])
1612 (define_split
1613 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1614 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1615 (const_int 0)))
1616 (clobber (match_scratch:P 2 ""))]
1617 "reload_completed"
1618 [(set (match_dup 2)
1619 (not:P (match_dup 1)))
1620 (set (match_dup 0)
1621 (compare:CC (match_dup 2)
1622 (const_int 0)))]
1623 "")
1625 (define_insn ""
1626 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1627 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1628 (const_int 0)))
1629 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1630 (not:P (match_dup 1)))]
1631 ""
1632 "@
1633 nor. %0,%1,%1
1634 #"
1635 [(set_attr "type" "logical,compare")
1636 (set_attr "dot" "yes")
1637 (set_attr "length" "4,8")])
1639 (define_split
1640 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1641 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1642 (const_int 0)))
1643 (set (match_operand:P 0 "gpc_reg_operand" "")
1644 (not:P (match_dup 1)))]
1645 "reload_completed"
1646 [(set (match_dup 0)
1647 (not:P (match_dup 1)))
1648 (set (match_dup 2)
1649 (compare:CC (match_dup 0)
1650 (const_int 0)))]
1651 "")
1653 (define_insn ""
1654 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1655 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1656 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1657 ""
1658 "@
1659 subf %0,%2,%1
1660 subfic %0,%2,%1"
1661 [(set_attr "type" "add")])
1663 (define_insn ""
1664 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1665 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1666 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1667 (const_int 0)))
1668 (clobber (match_scratch:P 3 "=r,r"))]
1669 ""
1670 "@
1671 subf. %3,%2,%1
1672 #"
1673 [(set_attr "type" "add")
1674 (set_attr "dot" "yes")
1675 (set_attr "length" "4,8")])
1677 (define_split
1678 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1679 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1680 (match_operand:P 2 "gpc_reg_operand" ""))
1681 (const_int 0)))
1682 (clobber (match_scratch:P 3 ""))]
1683 "reload_completed"
1684 [(set (match_dup 3)
1685 (minus:P (match_dup 1)
1686 (match_dup 2)))
1687 (set (match_dup 0)
1688 (compare:CC (match_dup 3)
1689 (const_int 0)))]
1690 "")
1692 (define_insn ""
1693 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1694 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1695 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1696 (const_int 0)))
1697 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1698 (minus:P (match_dup 1)
1699 (match_dup 2)))]
1700 ""
1701 "@
1702 subf. %0,%2,%1
1703 #"
1704 [(set_attr "type" "add")
1705 (set_attr "dot" "yes")
1706 (set_attr "length" "4,8")])
1708 (define_split
1709 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1710 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1711 (match_operand:P 2 "gpc_reg_operand" ""))
1712 (const_int 0)))
1713 (set (match_operand:P 0 "gpc_reg_operand" "")
1714 (minus:P (match_dup 1)
1715 (match_dup 2)))]
1716 "reload_completed"
1717 [(set (match_dup 0)
1718 (minus:P (match_dup 1)
1719 (match_dup 2)))
1720 (set (match_dup 3)
1721 (compare:CC (match_dup 0)
1722 (const_int 0)))]
1723 "")
1725 (define_expand "sub<mode>3"
1726 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1727 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1728 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1729 ""
1730 "
1731 {
1732 if (GET_CODE (operands[2]) == CONST_INT)
1733 {
1734 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1735 negate_rtx (<MODE>mode, operands[2])));
1736 DONE;
1737 }
1738 }")
1740 (define_expand "neg<mode>2"
1741 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1742 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1743 ""
1744 "")
1746 (define_insn "*neg<mode>2_internal"
1747 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1748 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1749 ""
1750 "neg %0,%1"
1751 [(set_attr "type" "add")])
1753 (define_insn ""
1754 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1755 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1756 (const_int 0)))
1757 (clobber (match_scratch:P 2 "=r,r"))]
1758 ""
1759 "@
1760 neg. %2,%1
1761 #"
1762 [(set_attr "type" "add")
1763 (set_attr "dot" "yes")
1764 (set_attr "length" "4,8")])
1766 (define_split
1767 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1768 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1769 (const_int 0)))
1770 (clobber (match_scratch:P 2 ""))]
1771 "reload_completed"
1772 [(set (match_dup 2)
1773 (neg:P (match_dup 1)))
1774 (set (match_dup 0)
1775 (compare:CC (match_dup 2)
1776 (const_int 0)))]
1777 "")
1779 (define_insn ""
1780 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1781 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1782 (const_int 0)))
1783 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1784 (neg:P (match_dup 1)))]
1785 ""
1786 "@
1787 neg. %0,%1
1788 #"
1789 [(set_attr "type" "add")
1790 (set_attr "dot" "yes")
1791 (set_attr "length" "4,8")])
1793 (define_split
1794 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1795 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1796 (const_int 0)))
1797 (set (match_operand:P 0 "gpc_reg_operand" "")
1798 (neg:P (match_dup 1)))]
1799 "reload_completed"
1800 [(set (match_dup 0)
1801 (neg:P (match_dup 1)))
1802 (set (match_dup 2)
1803 (compare:CC (match_dup 0)
1804 (const_int 0)))]
1805 "")
1807 (define_insn "clz<mode>2"
1808 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1809 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1810 ""
1811 "cntlz<wd> %0,%1"
1812 [(set_attr "type" "cntlz")])
1814 (define_expand "ctz<mode>2"
1815 [(set (match_dup 2)
1816 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1817 (set (match_dup 3)
1818 (and:GPR (match_dup 1)
1819 (match_dup 2)))
1820 (set (match_dup 4)
1821 (clz:GPR (match_dup 3)))
1822 (set (match_operand:GPR 0 "gpc_reg_operand" "")
1823 (minus:GPR (match_dup 5)
1824 (match_dup 4)))]
1825 ""
1826 {
1827 operands[2] = gen_reg_rtx (<MODE>mode);
1828 operands[3] = gen_reg_rtx (<MODE>mode);
1829 operands[4] = gen_reg_rtx (<MODE>mode);
1830 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1831 })
1833 (define_expand "ffs<mode>2"
1834 [(set (match_dup 2)
1835 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1836 (set (match_dup 3)
1837 (and:GPR (match_dup 1)
1838 (match_dup 2)))
1839 (set (match_dup 4)
1840 (clz:GPR (match_dup 3)))
1841 (set (match_operand:GPR 0 "gpc_reg_operand" "")
1842 (minus:GPR (match_dup 5)
1843 (match_dup 4)))]
1844 ""
1845 {
1846 operands[2] = gen_reg_rtx (<MODE>mode);
1847 operands[3] = gen_reg_rtx (<MODE>mode);
1848 operands[4] = gen_reg_rtx (<MODE>mode);
1849 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1850 })
1852 (define_insn "popcntb<mode>2"
1853 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1854 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1855 UNSPEC_POPCNTB))]
1856 "TARGET_POPCNTB"
1857 "popcntb %0,%1"
1858 [(set_attr "length" "4")
1859 (set_attr "type" "popcnt")])
1861 (define_insn "popcntd<mode>2"
1862 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1863 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1864 "TARGET_POPCNTD"
1865 "popcnt<wd> %0,%1"
1866 [(set_attr "length" "4")
1867 (set_attr "type" "popcnt")])
1869 (define_expand "popcount<mode>2"
1870 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1871 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1872 "TARGET_POPCNTB || TARGET_POPCNTD"
1873 {
1874 rs6000_emit_popcount (operands[0], operands[1]);
1875 DONE;
1876 })
1878 (define_insn "parity<mode>2_cmpb"
1879 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1880 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
1881 "TARGET_CMPB && TARGET_POPCNTB"
1882 "prty<wd> %0,%1"
1883 [(set_attr "length" "4")
1884 (set_attr "type" "popcnt")])
1886 (define_expand "parity<mode>2"
1887 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1888 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1889 "TARGET_POPCNTB"
1890 {
1891 rs6000_emit_parity (operands[0], operands[1]);
1892 DONE;
1893 })
1895 ;; Since the hardware zeros the upper part of the register, save generating the
1896 ;; AND immediate if we are converting to unsigned
1897 (define_insn "*bswaphi2_extenddi"
1898 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1899 (zero_extend:DI
1900 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1901 "TARGET_POWERPC64"
1902 "lhbrx %0,%y1"
1903 [(set_attr "length" "4")
1904 (set_attr "type" "load")])
1906 (define_insn "*bswaphi2_extendsi"
1907 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1908 (zero_extend:SI
1909 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1910 ""
1911 "lhbrx %0,%y1"
1912 [(set_attr "length" "4")
1913 (set_attr "type" "load")])
1915 (define_expand "bswaphi2"
1916 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
1917 (bswap:HI
1918 (match_operand:HI 1 "reg_or_mem_operand" "")))
1919 (clobber (match_scratch:SI 2 ""))])]
1920 ""
1921 {
1922 if (!REG_P (operands[0]) && !REG_P (operands[1]))
1923 operands[1] = force_reg (HImode, operands[1]);
1924 })
1926 (define_insn "bswaphi2_internal"
1927 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
1928 (bswap:HI
1929 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
1930 (clobber (match_scratch:SI 2 "=X,X,&r"))]
1931 ""
1932 "@
1933 lhbrx %0,%y1
1934 sthbrx %1,%y0
1935 #"
1936 [(set_attr "length" "4,4,12")
1937 (set_attr "type" "load,store,*")])
1939 ;; We are always BITS_BIG_ENDIAN, so the (const_int 16) below is
1940 ;; correct for -mlittle as well as -mbig.
1941 (define_split
1942 [(set (match_operand:HI 0 "gpc_reg_operand" "")
1943 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
1944 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
1945 "reload_completed"
1946 [(set (match_dup 3)
1947 (zero_extract:SI (match_dup 4)
1948 (const_int 8)
1949 (const_int 16)))
1950 (set (match_dup 2)
1951 (and:SI (ashift:SI (match_dup 4)
1952 (const_int 8))
1953 (const_int 65280))) ;; 0xff00
1954 (set (match_dup 3)
1955 (ior:SI (match_dup 3)
1956 (match_dup 2)))]
1957 "
1958 {
1959 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
1960 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
1961 }")
1963 (define_insn "*bswapsi2_extenddi"
1964 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1965 (zero_extend:DI
1966 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
1967 "TARGET_POWERPC64"
1968 "lwbrx %0,%y1"
1969 [(set_attr "length" "4")
1970 (set_attr "type" "load")])
1972 (define_expand "bswapsi2"
1973 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
1974 (bswap:SI
1975 (match_operand:SI 1 "reg_or_mem_operand" "")))]
1976 ""
1977 {
1978 if (!REG_P (operands[0]) && !REG_P (operands[1]))
1979 operands[1] = force_reg (SImode, operands[1]);
1980 })
1982 (define_insn "*bswapsi2_internal"
1983 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
1984 (bswap:SI
1985 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
1986 ""
1987 "@
1988 lwbrx %0,%y1
1989 stwbrx %1,%y0
1990 #"
1991 [(set_attr "length" "4,4,12")
1992 (set_attr "type" "load,store,*")])
1994 ;; We are always BITS_BIG_ENDIAN, so the bit positions below in
1995 ;; zero_extract insns do not change for -mlittle.
1996 (define_split
1997 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1998 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1999 "reload_completed"
2000 [(set (match_dup 0)
2001 (rotate:SI (match_dup 1) (const_int 8)))
2002 (set (zero_extract:SI (match_dup 0)
2003 (const_int 8)
2004 (const_int 0))
2005 (match_dup 1))
2006 (set (zero_extract:SI (match_dup 0)
2007 (const_int 8)
2008 (const_int 16))
2009 (rotate:SI (match_dup 1)
2010 (const_int 16)))]
2011 "")
2013 (define_expand "bswapdi2"
2014 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2015 (bswap:DI
2016 (match_operand:DI 1 "reg_or_mem_operand" "")))
2017 (clobber (match_scratch:DI 2 ""))
2018 (clobber (match_scratch:DI 3 ""))
2019 (clobber (match_scratch:DI 4 ""))])]
2020 ""
2021 {
2022 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2023 operands[1] = force_reg (DImode, operands[1]);
2025 if (!TARGET_POWERPC64)
2026 {
2027 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2028 that uses 64-bit registers needs the same scratch registers as 64-bit
2029 mode. */
2030 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2031 DONE;
2032 }
2033 })
2035 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2036 (define_insn "*bswapdi2_ldbrx"
2037 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2038 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2039 (clobber (match_scratch:DI 2 "=X,X,&r"))
2040 (clobber (match_scratch:DI 3 "=X,X,&r"))
2041 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2042 "TARGET_POWERPC64 && TARGET_LDBRX
2043 && (REG_P (operands[0]) || REG_P (operands[1]))"
2044 "@
2045 ldbrx %0,%y1
2046 stdbrx %1,%y0
2047 #"
2048 [(set_attr "length" "4,4,36")
2049 (set_attr "type" "load,store,*")])
2051 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2052 (define_insn "*bswapdi2_64bit"
2053 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2054 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2055 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2056 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2057 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2058 "TARGET_POWERPC64 && !TARGET_LDBRX
2059 && (REG_P (operands[0]) || REG_P (operands[1]))
2060 && !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))
2061 && !(MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))"
2062 "#"
2063 [(set_attr "length" "16,12,36")])
2065 (define_split
2066 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2067 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2068 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2069 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2070 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2071 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2072 [(const_int 0)]
2073 "
2074 {
2075 rtx dest = operands[0];
2076 rtx src = operands[1];
2077 rtx op2 = operands[2];
2078 rtx op3 = operands[3];
2079 rtx op4 = operands[4];
2080 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode,
2081 BYTES_BIG_ENDIAN ? 4 : 0);
2082 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode,
2083 BYTES_BIG_ENDIAN ? 4 : 0);
2084 rtx addr1;
2085 rtx addr2;
2086 rtx word_high;
2087 rtx word_low;
2089 addr1 = XEXP (src, 0);
2090 if (GET_CODE (addr1) == PLUS)
2091 {
2092 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2093 if (TARGET_AVOID_XFORM)
2094 {
2095 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2096 addr2 = op2;
2097 }
2098 else
2099 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2100 }
2101 else if (TARGET_AVOID_XFORM)
2102 {
2103 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2104 addr2 = op2;
2105 }
2106 else
2107 {
2108 emit_move_insn (op2, GEN_INT (4));
2109 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2110 }
2112 if (BYTES_BIG_ENDIAN)
2113 {
2114 word_high = change_address (src, SImode, addr1);
2115 word_low = change_address (src, SImode, addr2);
2116 }
2117 else
2118 {
2119 word_high = change_address (src, SImode, addr2);
2120 word_low = change_address (src, SImode, addr1);
2121 }
2123 emit_insn (gen_bswapsi2 (op3_32, word_low));
2124 emit_insn (gen_bswapsi2 (op4_32, word_high));
2125 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2126 emit_insn (gen_iordi3 (dest, dest, op4));
2127 DONE;
2128 }")
2130 (define_split
2131 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2132 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2133 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2134 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2135 (clobber (match_operand:DI 4 "" ""))]
2136 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2137 [(const_int 0)]
2138 "
2139 {
2140 rtx dest = operands[0];
2141 rtx src = operands[1];
2142 rtx op2 = operands[2];
2143 rtx op3 = operands[3];
2144 rtx src_si = simplify_gen_subreg (SImode, src, DImode,
2145 BYTES_BIG_ENDIAN ? 4 : 0);
2146 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode,
2147 BYTES_BIG_ENDIAN ? 4 : 0);
2148 rtx addr1;
2149 rtx addr2;
2150 rtx word_high;
2151 rtx word_low;
2153 addr1 = XEXP (dest, 0);
2154 if (GET_CODE (addr1) == PLUS)
2155 {
2156 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2157 if (TARGET_AVOID_XFORM)
2158 {
2159 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2160 addr2 = op2;
2161 }
2162 else
2163 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2164 }
2165 else if (TARGET_AVOID_XFORM)
2166 {
2167 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2168 addr2 = op2;
2169 }
2170 else
2171 {
2172 emit_move_insn (op2, GEN_INT (4));
2173 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2174 }
2176 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2177 if (BYTES_BIG_ENDIAN)
2178 {
2179 word_high = change_address (dest, SImode, addr1);
2180 word_low = change_address (dest, SImode, addr2);
2181 }
2182 else
2183 {
2184 word_high = change_address (dest, SImode, addr2);
2185 word_low = change_address (dest, SImode, addr1);
2186 }
2187 emit_insn (gen_bswapsi2 (word_high, src_si));
2188 emit_insn (gen_bswapsi2 (word_low, op3_si));
2189 DONE;
2190 }")
2192 (define_split
2193 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2194 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2195 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2196 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2197 (clobber (match_operand:DI 4 "" ""))]
2198 "TARGET_POWERPC64 && reload_completed"
2199 [(const_int 0)]
2200 "
2201 {
2202 rtx dest = operands[0];
2203 rtx src = operands[1];
2204 rtx op2 = operands[2];
2205 rtx op3 = operands[3];
2206 int lo_off = BYTES_BIG_ENDIAN ? 4 : 0;
2207 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, lo_off);
2208 rtx src_si = simplify_gen_subreg (SImode, src, DImode, lo_off);
2209 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, lo_off);
2210 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off);
2212 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2213 emit_insn (gen_bswapsi2 (dest_si, src_si));
2214 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2215 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2216 emit_insn (gen_iordi3 (dest, dest, op3));
2217 DONE;
2218 }")
2220 (define_insn "bswapdi2_32bit"
2221 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2222 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2223 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2224 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2225 "#"
2226 [(set_attr "length" "16,12,36")])
2228 (define_split
2229 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2230 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2231 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2232 "!TARGET_POWERPC64 && reload_completed"
2233 [(const_int 0)]
2234 "
2235 {
2236 rtx dest = operands[0];
2237 rtx src = operands[1];
2238 rtx op2 = operands[2];
2239 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2240 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2241 rtx addr1;
2242 rtx addr2;
2243 rtx word1;
2244 rtx word2;
2246 addr1 = XEXP (src, 0);
2247 if (GET_CODE (addr1) == PLUS)
2248 {
2249 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2250 if (TARGET_AVOID_XFORM)
2251 {
2252 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2253 addr2 = op2;
2254 }
2255 else
2256 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2257 }
2258 else if (TARGET_AVOID_XFORM)
2259 {
2260 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2261 addr2 = op2;
2262 }
2263 else
2264 {
2265 emit_move_insn (op2, GEN_INT (4));
2266 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2267 }
2269 word1 = change_address (src, SImode, addr1);
2270 word2 = change_address (src, SImode, addr2);
2272 emit_insn (gen_bswapsi2 (dest2, word1));
2273 emit_insn (gen_bswapsi2 (dest1, word2));
2274 DONE;
2275 }")
2277 (define_split
2278 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2279 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2280 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2281 "!TARGET_POWERPC64 && reload_completed"
2282 [(const_int 0)]
2283 "
2284 {
2285 rtx dest = operands[0];
2286 rtx src = operands[1];
2287 rtx op2 = operands[2];
2288 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2289 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2290 rtx addr1;
2291 rtx addr2;
2292 rtx word1;
2293 rtx word2;
2295 addr1 = XEXP (dest, 0);
2296 if (GET_CODE (addr1) == PLUS)
2297 {
2298 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2299 if (TARGET_AVOID_XFORM)
2300 {
2301 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2302 addr2 = op2;
2303 }
2304 else
2305 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2306 }
2307 else if (TARGET_AVOID_XFORM)
2308 {
2309 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2310 addr2 = op2;
2311 }
2312 else
2313 {
2314 emit_move_insn (op2, GEN_INT (4));
2315 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2316 }
2318 word1 = change_address (dest, SImode, addr1);
2319 word2 = change_address (dest, SImode, addr2);
2321 emit_insn (gen_bswapsi2 (word2, src1));
2322 emit_insn (gen_bswapsi2 (word1, src2));
2323 DONE;
2324 }")
2326 (define_split
2327 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2328 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2329 (clobber (match_operand:SI 2 "" ""))]
2330 "!TARGET_POWERPC64 && reload_completed"
2331 [(const_int 0)]
2332 "
2333 {
2334 rtx dest = operands[0];
2335 rtx src = operands[1];
2336 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2337 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2338 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2339 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2341 emit_insn (gen_bswapsi2 (dest1, src2));
2342 emit_insn (gen_bswapsi2 (dest2, src1));
2343 DONE;
2344 }")
2347 (define_insn "mul<mode>3"
2348 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2349 (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2350 (match_operand:GPR 2 "reg_or_short_operand" "r,I")))]
2351 ""
2352 "@
2353 mull<wd> %0,%1,%2
2354 mulli %0,%1,%2"
2355 [(set_attr "type" "mul")
2356 (set (attr "size")
2357 (cond [(match_operand:GPR 2 "s8bit_cint_operand" "")
2358 (const_string "8")
2359 (match_operand:GPR 2 "short_cint_operand" "")
2360 (const_string "16")]
2361 (const_string "<bits>")))])
2363 (define_insn_and_split "*mul<mode>3_dot"
2364 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2365 (compare:CC (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2366 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2367 (const_int 0)))
2368 (clobber (match_scratch:GPR 0 "=r,r"))]
2369 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2370 "@
2371 mull<wd>. %0,%1,%2
2372 #"
2373 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2374 [(set (match_dup 0)
2375 (mult:GPR (match_dup 1)
2376 (match_dup 2)))
2377 (set (match_dup 3)
2378 (compare:CC (match_dup 0)
2379 (const_int 0)))]
2380 ""
2381 [(set_attr "type" "mul")
2382 (set_attr "size" "<bits>")
2383 (set_attr "dot" "yes")
2384 (set_attr "length" "4,8")])
2386 (define_insn_and_split "*mul<mode>3_dot2"
2387 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2388 (compare:CC (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2389 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2390 (const_int 0)))
2391 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2392 (mult:GPR (match_dup 1)
2393 (match_dup 2)))]
2394 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2395 "@
2396 mull<wd>. %0,%1,%2
2397 #"
2398 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2399 [(set (match_dup 0)
2400 (mult:GPR (match_dup 1)
2401 (match_dup 2)))
2402 (set (match_dup 3)
2403 (compare:CC (match_dup 0)
2404 (const_int 0)))]
2405 ""
2406 [(set_attr "type" "mul")
2407 (set_attr "size" "<bits>")
2408 (set_attr "dot" "yes")
2409 (set_attr "length" "4,8")])
2412 (define_expand "<su>mul<mode>3_highpart"
2413 [(set (match_operand:GPR 0 "gpc_reg_operand")
2414 (subreg:GPR
2415 (mult:<DMODE> (any_extend:<DMODE>
2416 (match_operand:GPR 1 "gpc_reg_operand"))
2417 (any_extend:<DMODE>
2418 (match_operand:GPR 2 "gpc_reg_operand")))
2419 0))]
2420 ""
2421 {
2422 if (<MODE>mode == SImode && TARGET_POWERPC64)
2423 {
2424 emit_insn (gen_<su>mulsi3_highpart_64 (operands[0], operands[1],
2425 operands[2]));
2426 DONE;
2427 }
2429 if (!WORDS_BIG_ENDIAN)
2430 {
2431 emit_insn (gen_<su>mul<mode>3_highpart_le (operands[0], operands[1],
2432 operands[2]));
2433 DONE;
2434 }
2435 })
2437 (define_insn "*<su>mul<mode>3_highpart"
2438 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2439 (subreg:GPR
2440 (mult:<DMODE> (any_extend:<DMODE>
2441 (match_operand:GPR 1 "gpc_reg_operand" "r"))
2442 (any_extend:<DMODE>
2443 (match_operand:GPR 2 "gpc_reg_operand" "r")))
2444 0))]
2445 "WORDS_BIG_ENDIAN && !(<MODE>mode == SImode && TARGET_POWERPC64)"
2446 "mulh<wd><u> %0,%1,%2"
2447 [(set_attr "type" "mul")
2448 (set_attr "size" "<bits>")])
2450 (define_insn "<su>mulsi3_highpart_le"
2451 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2452 (subreg:SI
2453 (mult:DI (any_extend:DI
2454 (match_operand:SI 1 "gpc_reg_operand" "r"))
2455 (any_extend:DI
2456 (match_operand:SI 2 "gpc_reg_operand" "r")))
2457 4))]
2458 "!WORDS_BIG_ENDIAN && !TARGET_POWERPC64"
2459 "mulhw<u> %0,%1,%2"
2460 [(set_attr "type" "mul")])
2462 (define_insn "<su>muldi3_highpart_le"
2463 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2464 (subreg:DI
2465 (mult:TI (any_extend:TI
2466 (match_operand:DI 1 "gpc_reg_operand" "r"))
2467 (any_extend:TI
2468 (match_operand:DI 2 "gpc_reg_operand" "r")))
2469 8))]
2470 "!WORDS_BIG_ENDIAN && TARGET_POWERPC64"
2471 "mulhd<u> %0,%1,%2"
2472 [(set_attr "type" "mul")
2473 (set_attr "size" "64")])
2475 (define_insn "<su>mulsi3_highpart_64"
2476 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2477 (truncate:SI
2478 (lshiftrt:DI
2479 (mult:DI (any_extend:DI
2480 (match_operand:SI 1 "gpc_reg_operand" "r"))
2481 (any_extend:DI
2482 (match_operand:SI 2 "gpc_reg_operand" "r")))
2483 (const_int 32))))]
2484 "TARGET_POWERPC64"
2485 "mulhw<u> %0,%1,%2"
2486 [(set_attr "type" "mul")])
2488 (define_expand "<u>mul<mode><dmode>3"
2489 [(set (match_operand:<DMODE> 0 "gpc_reg_operand")
2490 (mult:<DMODE> (any_extend:<DMODE>
2491 (match_operand:GPR 1 "gpc_reg_operand"))
2492 (any_extend:<DMODE>
2493 (match_operand:GPR 2 "gpc_reg_operand"))))]
2494 "!(<MODE>mode == SImode && TARGET_POWERPC64)"
2495 {
2496 rtx l = gen_reg_rtx (<MODE>mode);
2497 rtx h = gen_reg_rtx (<MODE>mode);
2498 emit_insn (gen_mul<mode>3 (l, operands[1], operands[2]));
2499 emit_insn (gen_<su>mul<mode>3_highpart (h, operands[1], operands[2]));
2500 emit_move_insn (gen_lowpart (<MODE>mode, operands[0]), l);
2501 emit_move_insn (gen_highpart (<MODE>mode, operands[0]), h);
2502 DONE;
2503 })
2506 (define_insn "udiv<mode>3"
2507 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2508 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2509 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2510 ""
2511 "div<wd>u %0,%1,%2"
2512 [(set_attr "type" "div")
2513 (set_attr "size" "<bits>")])
2516 ;; For powers of two we can do srai/aze for divide and then adjust for
2517 ;; modulus. If it isn't a power of two, force operands into register and do
2518 ;; a normal divide.
2519 (define_expand "div<mode>3"
2520 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2521 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2522 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2523 ""
2524 {
2525 if (GET_CODE (operands[2]) != CONST_INT
2526 || INTVAL (operands[2]) <= 0
2527 || exact_log2 (INTVAL (operands[2])) < 0)
2528 operands[2] = force_reg (<MODE>mode, operands[2]);
2529 })
2531 (define_insn "*div<mode>3"
2532 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2533 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2534 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2535 ""
2536 "div<wd> %0,%1,%2"
2537 [(set_attr "type" "div")
2538 (set_attr "size" "<bits>")])
2540 (define_expand "mod<mode>3"
2541 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2542 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2543 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2544 ""
2545 "
2546 {
2547 int i;
2548 rtx temp1;
2549 rtx temp2;
2551 if (GET_CODE (operands[2]) != CONST_INT
2552 || INTVAL (operands[2]) <= 0
2553 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2554 FAIL;
2556 temp1 = gen_reg_rtx (<MODE>mode);
2557 temp2 = gen_reg_rtx (<MODE>mode);
2559 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2560 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2561 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2562 DONE;
2563 }")
2565 (define_insn ""
2566 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2567 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2568 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2569 ""
2570 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2571 [(set_attr "type" "two")
2572 (set_attr "length" "8")])
2574 (define_insn ""
2575 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2576 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2577 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2578 (const_int 0)))
2579 (clobber (match_scratch:P 3 "=r,r"))]
2580 ""
2581 "@
2582 sra<wd>i %3,%1,%p2\;addze. %3,%3
2583 #"
2584 [(set_attr "type" "compare")
2585 (set_attr "length" "8,12")
2586 (set_attr "cell_micro" "not")])
2588 (define_split
2589 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2590 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2591 (match_operand:GPR 2 "exact_log2_cint_operand"
2592 ""))
2593 (const_int 0)))
2594 (clobber (match_scratch:GPR 3 ""))]
2595 "reload_completed"
2596 [(set (match_dup 3)
2597 (div:<MODE> (match_dup 1) (match_dup 2)))
2598 (set (match_dup 0)
2599 (compare:CC (match_dup 3)
2600 (const_int 0)))]
2601 "")
2603 (define_insn ""
2604 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2605 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2606 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2607 (const_int 0)))
2608 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2609 (div:P (match_dup 1) (match_dup 2)))]
2610 ""
2611 "@
2612 sra<wd>i %0,%1,%p2\;addze. %0,%0
2613 #"
2614 [(set_attr "type" "compare")
2615 (set_attr "length" "8,12")
2616 (set_attr "cell_micro" "not")])
2618 (define_split
2619 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2620 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2621 (match_operand:GPR 2 "exact_log2_cint_operand"
2622 ""))
2623 (const_int 0)))
2624 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2625 (div:GPR (match_dup 1) (match_dup 2)))]
2626 "reload_completed"
2627 [(set (match_dup 0)
2628 (div:<MODE> (match_dup 1) (match_dup 2)))
2629 (set (match_dup 3)
2630 (compare:CC (match_dup 0)
2631 (const_int 0)))]
2632 "")
2633 \f
2634 ;; Logical instructions
2635 ;; The logical instructions are mostly combined by using match_operator,
2636 ;; but the plain AND insns are somewhat different because there is no
2637 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2638 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2640 (define_expand "and<mode>3"
2641 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2642 (and:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
2643 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
2644 ""
2645 {
2646 if (<MODE>mode == DImode && !TARGET_POWERPC64)
2647 {
2648 rs6000_split_logical (operands, AND, false, false, false);
2649 DONE;
2650 }
2652 if (logical_const_operand (operands[2], <MODE>mode)
2653 && !any_mask_operand (operands[2], <MODE>mode))
2654 {
2655 emit_insn (gen_and<mode>3_imm (operands[0], operands[1], operands[2]));
2656 DONE;
2657 }
2659 if ((<MODE>mode == DImode && !and64_2_operand (operands[2], <MODE>mode))
2660 || (<MODE>mode != DImode && !and_operand (operands[2], <MODE>mode)))
2661 operands[2] = force_reg (<MODE>mode, operands[2]);
2662 })
2665 (define_insn "*and<mode>3"
2666 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2667 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2668 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2669 ""
2670 "and %0,%1,%2"
2671 [(set_attr "type" "logical")])
2673 (define_insn_and_split "*and<mode>3_dot"
2674 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2675 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2676 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2677 (const_int 0)))
2678 (clobber (match_scratch:GPR 0 "=r,r"))]
2679 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2680 "@
2681 and. %0,%1,%2
2682 #"
2683 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2684 [(set (match_dup 0)
2685 (and:GPR (match_dup 1)
2686 (match_dup 2)))
2687 (set (match_dup 3)
2688 (compare:CC (match_dup 0)
2689 (const_int 0)))]
2690 ""
2691 [(set_attr "type" "logical")
2692 (set_attr "dot" "yes")
2693 (set_attr "length" "4,8")])
2695 (define_insn_and_split "*and<mode>3_dot2"
2696 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2697 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2698 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2699 (const_int 0)))
2700 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2701 (and:GPR (match_dup 1)
2702 (match_dup 2)))]
2703 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2704 "@
2705 and. %0,%1,%2
2706 #"
2707 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2708 [(set (match_dup 0)
2709 (and:GPR (match_dup 1)
2710 (match_dup 2)))
2711 (set (match_dup 3)
2712 (compare:CC (match_dup 0)
2713 (const_int 0)))]
2714 ""
2715 [(set_attr "type" "logical")
2716 (set_attr "dot" "yes")
2717 (set_attr "length" "4,8")])
2720 (define_insn "and<mode>3_imm"
2721 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2722 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r")
2723 (match_operand:GPR 2 "logical_const_operand" "n")))
2724 (clobber (match_scratch:CC 3 "=x"))]
2725 "rs6000_gen_cell_microcode
2726 && !any_mask_operand (operands[2], <MODE>mode)"
2727 "andi%e2. %0,%1,%u2"
2728 [(set_attr "type" "logical")
2729 (set_attr "dot" "yes")])
2731 (define_insn_and_split "*and<mode>3_imm_dot"
2732 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2733 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2734 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2735 (const_int 0)))
2736 (clobber (match_scratch:GPR 0 "=r,r"))
2737 (clobber (match_scratch:CC 4 "=X,x"))]
2738 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2739 && rs6000_gen_cell_microcode
2740 && !any_mask_operand (operands[2], <MODE>mode)"
2741 "@
2742 andi%e2. %0,%1,%u2
2743 #"
2744 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2745 [(parallel [(set (match_dup 0)
2746 (and:GPR (match_dup 1)
2747 (match_dup 2)))
2748 (clobber (match_dup 4))])
2749 (set (match_dup 3)
2750 (compare:CC (match_dup 0)
2751 (const_int 0)))]
2752 ""
2753 [(set_attr "type" "logical")
2754 (set_attr "dot" "yes")
2755 (set_attr "length" "4,8")])
2757 (define_insn_and_split "*and<mode>3_imm_dot2"
2758 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2759 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2760 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2761 (const_int 0)))
2762 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2763 (and:GPR (match_dup 1)
2764 (match_dup 2)))
2765 (clobber (match_scratch:CC 4 "=X,x"))]
2766 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2767 && rs6000_gen_cell_microcode
2768 && !any_mask_operand (operands[2], <MODE>mode)"
2769 "@
2770 andi%e2. %0,%1,%u2
2771 #"
2772 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2773 [(parallel [(set (match_dup 0)
2774 (and:GPR (match_dup 1)
2775 (match_dup 2)))
2776 (clobber (match_dup 4))])
2777 (set (match_dup 3)
2778 (compare:CC (match_dup 0)
2779 (const_int 0)))]
2780 ""
2781 [(set_attr "type" "logical")
2782 (set_attr "dot" "yes")
2783 (set_attr "length" "4,8")])
2785 (define_insn_and_split "*and<mode>3_imm_mask_dot"
2786 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2787 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2788 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2789 (const_int 0)))
2790 (clobber (match_scratch:GPR 0 "=r,r"))]
2791 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2792 && rs6000_gen_cell_microcode
2793 && any_mask_operand (operands[2], <MODE>mode)"
2794 "@
2795 andi%e2. %0,%1,%u2
2796 #"
2797 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2798 [(set (match_dup 0)
2799 (and:GPR (match_dup 1)
2800 (match_dup 2)))
2801 (set (match_dup 3)
2802 (compare:CC (match_dup 0)
2803 (const_int 0)))]
2804 ""
2805 [(set_attr "type" "logical")
2806 (set_attr "dot" "yes")
2807 (set_attr "length" "4,8")])
2809 (define_insn_and_split "*and<mode>3_imm_mask_dot2"
2810 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2811 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2812 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2813 (const_int 0)))
2814 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2815 (and:GPR (match_dup 1)
2816 (match_dup 2)))]
2817 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2818 && rs6000_gen_cell_microcode
2819 && any_mask_operand (operands[2], <MODE>mode)"
2820 "@
2821 andi%e2. %0,%1,%u2
2822 #"
2823 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2824 [(set (match_dup 0)
2825 (and:GPR (match_dup 1)
2826 (match_dup 2)))
2827 (set (match_dup 3)
2828 (compare:CC (match_dup 0)
2829 (const_int 0)))]
2830 ""
2831 [(set_attr "type" "logical")
2832 (set_attr "dot" "yes")
2833 (set_attr "length" "4,8")])
2836 (define_insn "*and<mode>3_mask"
2837 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2838 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2839 (match_operand:GPR 2 "any_mask_operand" "S,T")))]
2840 ""
2841 "@
2842 rldic%B2 %0,%1,0,%S2
2843 rlwinm %0,%1,0,%m2,%M2"
2844 [(set_attr "type" "shift")])
2846 (define_insn_and_split "*and<mode>3_mask_dot"
2847 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
2848 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")
2849 (match_operand:GPR 2 "any_mask_operand" "S,T,S,T"))
2850 (const_int 0)))
2851 (clobber (match_scratch:GPR 0 "=r,r,r,r"))]
2852 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2853 && rs6000_gen_cell_microcode
2854 && !logical_const_operand (operands[2], <MODE>mode)"
2855 "@
2856 rldic%B2. %0,%1,0,%S2
2857 rlwinm. %0,%1,0,%m2,%M2
2858 #
2859 #"
2860 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2861 [(set (match_dup 0)
2862 (and:GPR (match_dup 1)
2863 (match_dup 2)))
2864 (set (match_dup 3)
2865 (compare:CC (match_dup 0)
2866 (const_int 0)))]
2867 ""
2868 [(set_attr "type" "shift")
2869 (set_attr "dot" "yes")
2870 (set_attr "length" "4,4,8,8")])
2872 (define_insn_and_split "*and<mode>3_mask_dot2"
2873 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
2874 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")
2875 (match_operand:GPR 2 "any_mask_operand" "S,T,S,T"))
2876 (const_int 0)))
2877 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
2878 (and:GPR (match_dup 1)
2879 (match_dup 2)))]
2880 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2881 && rs6000_gen_cell_microcode
2882 && !logical_const_operand (operands[2], <MODE>mode)"
2883 "@
2884 rldic%B2. %0,%1,0,%S2
2885 rlwinm. %0,%1,0,%m2,%M2
2886 #
2887 #"
2888 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2889 [(set (match_dup 0)
2890 (and:GPR (match_dup 1)
2891 (match_dup 2)))
2892 (set (match_dup 3)
2893 (compare:CC (match_dup 0)
2894 (const_int 0)))]
2895 ""
2896 [(set_attr "type" "shift")
2897 (set_attr "dot" "yes")
2898 (set_attr "length" "4,4,8,8")])
2902 (define_insn "andsi3_internal0_nomc"
2903 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2904 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2905 (match_operand:SI 2 "and_operand" "?r,T")))]
2906 "!rs6000_gen_cell_microcode"
2907 "@
2908 and %0,%1,%2
2909 rlwinm %0,%1,0,%m2,%M2"
2910 [(set_attr "type" "logical,shift")])
2913 ;; Handle the PowerPC64 rlwinm corner case
2915 (define_insn_and_split "*andsi3_internal6"
2916 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2917 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2918 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2919 "TARGET_POWERPC64"
2920 "#"
2921 "TARGET_POWERPC64"
2922 [(set (match_dup 0)
2923 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2924 (match_dup 4)))
2925 (set (match_dup 0)
2926 (rotate:SI (match_dup 0) (match_dup 5)))]
2927 "
2928 {
2929 int mb = extract_MB (operands[2]);
2930 int me = extract_ME (operands[2]);
2931 operands[3] = GEN_INT (me + 1);
2932 operands[5] = GEN_INT (32 - (me + 1));
2933 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2934 }"
2935 [(set_attr "length" "8")])
2938 (define_expand "ior<mode>3"
2939 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2940 (ior:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
2941 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
2942 ""
2943 {
2944 if (<MODE>mode == DImode && !TARGET_POWERPC64)
2945 {
2946 rs6000_split_logical (operands, IOR, false, false, false);
2947 DONE;
2948 }
2950 if (non_logical_cint_operand (operands[2], <MODE>mode))
2951 {
2952 rtx tmp = ((!can_create_pseudo_p ()
2953 || rtx_equal_p (operands[0], operands[1]))
2954 ? operands[0] : gen_reg_rtx (<MODE>mode));
2955 HOST_WIDE_INT value = INTVAL (operands[2]);
2957 emit_insn (gen_ior<mode>3 (tmp, operands[1],
2958 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2960 emit_insn (gen_ior<mode>3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2961 DONE;
2962 }
2964 if (!reg_or_logical_cint_operand (operands[2], <MODE>mode))
2965 operands[2] = force_reg (<MODE>mode, operands[2]);
2966 })
2968 (define_expand "xor<mode>3"
2969 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2970 (xor:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
2971 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
2972 ""
2973 {
2974 if (<MODE>mode == DImode && !TARGET_POWERPC64)
2975 {
2976 rs6000_split_logical (operands, XOR, false, false, false);
2977 DONE;
2978 }
2980 if (non_logical_cint_operand (operands[2], <MODE>mode))
2981 {
2982 rtx tmp = ((!can_create_pseudo_p ()
2983 || rtx_equal_p (operands[0], operands[1]))
2984 ? operands[0] : gen_reg_rtx (<MODE>mode));
2985 HOST_WIDE_INT value = INTVAL (operands[2]);
2987 emit_insn (gen_xor<mode>3 (tmp, operands[1],
2988 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2990 emit_insn (gen_xor<mode>3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2991 DONE;
2992 }
2994 if (!reg_or_logical_cint_operand (operands[2], <MODE>mode))
2995 operands[2] = force_reg (<MODE>mode, operands[2]);
2996 })
2998 (define_insn "*bool<mode>3"
2999 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3000 (match_operator:GPR 3 "boolean_or_operator"
3001 [(match_operand:GPR 1 "gpc_reg_operand" "r")
3002 (match_operand:GPR 2 "gpc_reg_operand" "r")]))]
3003 ""
3004 "%q3 %0,%1,%2"
3005 [(set_attr "type" "logical")])
3007 (define_insn "*bool<mode>3_imm"
3008 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3009 (match_operator:GPR 3 "boolean_or_operator"
3010 [(match_operand:GPR 1 "gpc_reg_operand" "%r")
3011 (match_operand:GPR 2 "logical_const_operand" "n")]))]
3012 ""
3013 "%q3i%e2 %0,%1,%u2"
3014 [(set_attr "type" "logical")])
3016 (define_insn_and_split "*bool<mode>3_dot"
3017 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3018 (compare:CC (match_operator:GPR 3 "boolean_or_operator"
3019 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
3020 (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
3021 (const_int 0)))
3022 (clobber (match_scratch:GPR 0 "=r,r"))]
3023 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3024 "@
3025 %q3. %0,%1,%2
3026 #"
3027 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3028 [(set (match_dup 0)
3029 (match_dup 3))
3030 (set (match_dup 4)
3031 (compare:CC (match_dup 0)
3032 (const_int 0)))]
3033 ""
3034 [(set_attr "type" "logical")
3035 (set_attr "dot" "yes")
3036 (set_attr "length" "4,8")])
3038 (define_insn_and_split "*bool<mode>3_dot2"
3039 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3040 (compare:CC (match_operator:GPR 3 "boolean_or_operator"
3041 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
3042 (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
3043 (const_int 0)))
3044 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3045 (match_dup 3))]
3046 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3047 "@
3048 %q3. %0,%1,%2
3049 #"
3050 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3051 [(set (match_dup 0)
3052 (match_dup 3))
3053 (set (match_dup 4)
3054 (compare:CC (match_dup 0)
3055 (const_int 0)))]
3056 ""
3057 [(set_attr "type" "logical")
3058 (set_attr "dot" "yes")
3059 (set_attr "length" "4,8")])
3061 ;; Split a logical operation that we can't do in one insn into two insns,
3062 ;; each of which does one 16-bit part. This is used by combine.
3064 (define_split
3065 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
3066 (match_operator:GPR 3 "boolean_or_operator"
3067 [(match_operand:GPR 1 "gpc_reg_operand" "")
3068 (match_operand:GPR 2 "non_logical_cint_operand" "")]))]
3069 ""
3070 [(set (match_dup 0) (match_dup 4))
3071 (set (match_dup 0) (match_dup 5))]
3072 {
3073 rtx i;
3074 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3075 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
3076 operands[1], i);
3077 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3078 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
3079 operands[0], i);
3080 })
3083 (define_insn "*boolc<mode>3"
3084 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3085 (match_operator:GPR 3 "boolean_operator"
3086 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))
3087 (match_operand:GPR 1 "gpc_reg_operand" "r")]))]
3088 ""
3089 "%q3 %0,%1,%2"
3090 [(set_attr "type" "logical")])
3092 (define_insn_and_split "*boolc<mode>3_dot"
3093 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3094 (compare:CC (match_operator:GPR 3 "boolean_operator"
3095 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
3096 (match_operand:GPR 1 "gpc_reg_operand" "r,r")])
3097 (const_int 0)))
3098 (clobber (match_scratch:GPR 0 "=r,r"))]
3099 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3100 "@
3101 %q3. %0,%1,%2
3102 #"
3103 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3104 [(set (match_dup 0)
3105 (match_dup 3))
3106 (set (match_dup 4)
3107 (compare:CC (match_dup 0)
3108 (const_int 0)))]
3109 ""
3110 [(set_attr "type" "logical")
3111 (set_attr "dot" "yes")
3112 (set_attr "length" "4,8")])
3114 (define_insn_and_split "*boolc<mode>3_dot2"
3115 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3116 (compare:CC (match_operator:GPR 3 "boolean_operator"
3117 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
3118 (match_operand:GPR 1 "gpc_reg_operand" "r,r")])
3119 (const_int 0)))
3120 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3121 (match_dup 3))]
3122 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3123 "@
3124 %q3. %0,%1,%2
3125 #"
3126 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3127 [(set (match_dup 0)
3128 (match_dup 3))
3129 (set (match_dup 4)
3130 (compare:CC (match_dup 0)
3131 (const_int 0)))]
3132 ""
3133 [(set_attr "type" "logical")
3134 (set_attr "dot" "yes")
3135 (set_attr "length" "4,8")])
3138 (define_insn "*boolcc<mode>3"
3139 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3140 (match_operator:GPR 3 "boolean_operator"
3141 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))
3142 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))]))]
3143 ""
3144 "%q3 %0,%1,%2"
3145 [(set_attr "type" "logical")])
3147 (define_insn_and_split "*boolcc<mode>3_dot"
3148 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3149 (compare:CC (match_operator:GPR 3 "boolean_operator"
3150 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
3151 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
3152 (const_int 0)))
3153 (clobber (match_scratch:GPR 0 "=r,r"))]
3154 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3155 "@
3156 %q3. %0,%1,%2
3157 #"
3158 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3159 [(set (match_dup 0)
3160 (match_dup 3))
3161 (set (match_dup 4)
3162 (compare:CC (match_dup 0)
3163 (const_int 0)))]
3164 ""
3165 [(set_attr "type" "logical")
3166 (set_attr "dot" "yes")
3167 (set_attr "length" "4,8")])
3169 (define_insn_and_split "*boolcc<mode>3_dot2"
3170 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3171 (compare:CC (match_operator:GPR 3 "boolean_operator"
3172 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
3173 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
3174 (const_int 0)))
3175 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3176 (match_dup 3))]
3177 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3178 "@
3179 %q3. %0,%1,%2
3180 #"
3181 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3182 [(set (match_dup 0)
3183 (match_dup 3))
3184 (set (match_dup 4)
3185 (compare:CC (match_dup 0)
3186 (const_int 0)))]
3187 ""
3188 [(set_attr "type" "logical")
3189 (set_attr "dot" "yes")
3190 (set_attr "length" "4,8")])
3193 ;; TODO: Should have dots of this as well.
3194 (define_insn "*eqv<mode>3"
3195 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3196 (not:GPR (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3197 (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
3198 ""
3199 "eqv %0,%1,%2"
3200 [(set_attr "type" "logical")])
3201 \f
3202 ;; Rotate and shift insns, in all their variants. These support shifts,
3203 ;; field inserts and extracts, and various combinations thereof.
3204 (define_expand "insv"
3205 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3206 (match_operand:SI 1 "const_int_operand" "")
3207 (match_operand:SI 2 "const_int_operand" ""))
3208 (match_operand 3 "gpc_reg_operand" ""))]
3209 ""
3210 "
3211 {
3212 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3213 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3214 compiler if the address of the structure is taken later. Likewise, do
3215 not handle invalid E500 subregs. */
3216 if (GET_CODE (operands[0]) == SUBREG
3217 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3218 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3219 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3220 FAIL;
3222 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3223 emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
3224 operands[3]));
3225 else
3226 emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
3227 operands[3]));
3228 DONE;
3229 }")
3231 (define_insn "insvsi_internal"
3232 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3233 (match_operand:SI 1 "const_int_operand" "i")
3234 (match_operand:SI 2 "const_int_operand" "i"))
3235 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3236 ""
3237 "*
3238 {
3239 int start = INTVAL (operands[2]) & 31;
3240 int size = INTVAL (operands[1]) & 31;
3242 operands[4] = GEN_INT (32 - start - size);
3243 operands[1] = GEN_INT (start + size - 1);
3244 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3245 }"
3246 [(set_attr "type" "insert")])
3248 (define_insn "*insvsi_internal1"
3249 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3250 (match_operand:SI 1 "const_int_operand" "i")
3251 (match_operand:SI 2 "const_int_operand" "i"))
3252 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3253 (match_operand:SI 4 "const_int_operand" "i")))]
3254 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3255 "*
3256 {
3257 int shift = INTVAL (operands[4]) & 31;
3258 int start = INTVAL (operands[2]) & 31;
3259 int size = INTVAL (operands[1]) & 31;
3261 operands[4] = GEN_INT (shift - start - size);
3262 operands[1] = GEN_INT (start + size - 1);
3263 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3264 }"
3265 [(set_attr "type" "insert")])
3267 (define_insn "*insvsi_internal2"
3268 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3269 (match_operand:SI 1 "const_int_operand" "i")
3270 (match_operand:SI 2 "const_int_operand" "i"))
3271 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3272 (match_operand:SI 4 "const_int_operand" "i")))]
3273 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3274 "*
3275 {
3276 int shift = INTVAL (operands[4]) & 31;
3277 int start = INTVAL (operands[2]) & 31;
3278 int size = INTVAL (operands[1]) & 31;
3280 operands[4] = GEN_INT (32 - shift - start - size);
3281 operands[1] = GEN_INT (start + size - 1);
3282 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3283 }"
3284 [(set_attr "type" "insert")])
3286 (define_insn "*insvsi_internal3"
3287 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3288 (match_operand:SI 1 "const_int_operand" "i")
3289 (match_operand:SI 2 "const_int_operand" "i"))
3290 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3291 (match_operand:SI 4 "const_int_operand" "i")))]
3292 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3293 "*
3294 {
3295 int shift = INTVAL (operands[4]) & 31;
3296 int start = INTVAL (operands[2]) & 31;
3297 int size = INTVAL (operands[1]) & 31;
3299 operands[4] = GEN_INT (32 - shift - start - size);
3300 operands[1] = GEN_INT (start + size - 1);
3301 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3302 }"
3303 [(set_attr "type" "insert")])
3305 (define_insn "*insvsi_internal4"
3306 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3307 (match_operand:SI 1 "const_int_operand" "i")
3308 (match_operand:SI 2 "const_int_operand" "i"))
3309 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3310 (match_operand:SI 4 "const_int_operand" "i")
3311 (match_operand:SI 5 "const_int_operand" "i")))]
3312 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3313 "*
3314 {
3315 int extract_start = INTVAL (operands[5]) & 31;
3316 int extract_size = INTVAL (operands[4]) & 31;
3317 int insert_start = INTVAL (operands[2]) & 31;
3318 int insert_size = INTVAL (operands[1]) & 31;
3320 /* Align extract field with insert field */
3321 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3322 operands[1] = GEN_INT (insert_start + insert_size - 1);
3323 return \"rlwimi %0,%3,%h5,%h2,%h1\";
3324 }"
3325 [(set_attr "type" "insert")])
3327 ;; combine patterns for rlwimi
3328 (define_insn "*insvsi_internal5"
3329 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3330 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3331 (match_operand:SI 1 "mask_operand" "i"))
3332 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3333 (match_operand:SI 2 "const_int_operand" "i"))
3334 (match_operand:SI 5 "mask_operand" "i"))))]
3335 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3336 "*
3337 {
3338 int me = extract_ME(operands[5]);
3339 int mb = extract_MB(operands[5]);
3340 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3341 operands[2] = GEN_INT(mb);
3342 operands[1] = GEN_INT(me);
3343 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3344 }"
3345 [(set_attr "type" "insert")])
3347 (define_insn "*insvsi_internal6"
3348 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3349 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3350 (match_operand:SI 2 "const_int_operand" "i"))
3351 (match_operand:SI 5 "mask_operand" "i"))
3352 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3353 (match_operand:SI 1 "mask_operand" "i"))))]
3354 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3355 "*
3356 {
3357 int me = extract_ME(operands[5]);
3358 int mb = extract_MB(operands[5]);
3359 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3360 operands[2] = GEN_INT(mb);
3361 operands[1] = GEN_INT(me);
3362 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3363 }"
3364 [(set_attr "type" "insert")])
3366 (define_insn "insvdi_internal"
3367 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3368 (match_operand:SI 1 "const_int_operand" "i")
3369 (match_operand:SI 2 "const_int_operand" "i"))
3370 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3371 "TARGET_POWERPC64"
3372 "*
3373 {
3374 int start = INTVAL (operands[2]) & 63;
3375 int size = INTVAL (operands[1]) & 63;
3377 operands[1] = GEN_INT (64 - start - size);
3378 return \"rldimi %0,%3,%H1,%H2\";
3379 }"
3380 [(set_attr "type" "insert")
3381 (set_attr "size" "64")])
3383 (define_insn "*insvdi_internal2"
3384 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3385 (match_operand:SI 1 "const_int_operand" "i")
3386 (match_operand:SI 2 "const_int_operand" "i"))
3387 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3388 (match_operand:SI 4 "const_int_operand" "i")))]
3389 "TARGET_POWERPC64
3390 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3391 "*
3392 {
3393 int shift = INTVAL (operands[4]) & 63;
3394 int start = (INTVAL (operands[2]) & 63) - 32;
3395 int size = INTVAL (operands[1]) & 63;
3397 operands[4] = GEN_INT (64 - shift - start - size);
3398 operands[2] = GEN_INT (start);
3399 operands[1] = GEN_INT (start + size - 1);
3400 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3401 }")
3403 (define_insn "*insvdi_internal3"
3404 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3405 (match_operand:SI 1 "const_int_operand" "i")
3406 (match_operand:SI 2 "const_int_operand" "i"))
3407 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3408 (match_operand:SI 4 "const_int_operand" "i")))]
3409 "TARGET_POWERPC64
3410 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3411 "*
3412 {
3413 int shift = INTVAL (operands[4]) & 63;
3414 int start = (INTVAL (operands[2]) & 63) - 32;
3415 int size = INTVAL (operands[1]) & 63;
3417 operands[4] = GEN_INT (64 - shift - start - size);
3418 operands[2] = GEN_INT (start);
3419 operands[1] = GEN_INT (start + size - 1);
3420 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3421 }")
3423 (define_expand "extzv"
3424 [(set (match_operand 0 "gpc_reg_operand" "")
3425 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3426 (match_operand:SI 2 "const_int_operand" "")
3427 (match_operand:SI 3 "const_int_operand" "")))]
3428 ""
3429 "
3430 {
3431 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3432 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3433 compiler if the address of the structure is taken later. */
3434 if (GET_CODE (operands[0]) == SUBREG
3435 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3436 FAIL;
3438 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3439 emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
3440 operands[3]));
3441 else
3442 emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
3443 operands[3]));
3444 DONE;
3445 }")
3447 (define_insn "extzvsi_internal"
3448 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3449 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3450 (match_operand:SI 2 "const_int_operand" "i")
3451 (match_operand:SI 3 "const_int_operand" "i")))]
3452 ""
3453 "*
3454 {
3455 int start = INTVAL (operands[3]) & 31;
3456 int size = INTVAL (operands[2]) & 31;
3458 if (start + size >= 32)
3459 operands[3] = const0_rtx;
3460 else
3461 operands[3] = GEN_INT (start + size);
3462 return \"rlwinm %0,%1,%3,%s2,31\";
3463 }"
3464 [(set_attr "type" "shift")])
3466 (define_insn "*extzvsi_internal1"
3467 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3468 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3469 (match_operand:SI 2 "const_int_operand" "i,i")
3470 (match_operand:SI 3 "const_int_operand" "i,i"))
3471 (const_int 0)))
3472 (clobber (match_scratch:SI 4 "=r,r"))]
3473 ""
3474 "*
3475 {
3476 int start = INTVAL (operands[3]) & 31;
3477 int size = INTVAL (operands[2]) & 31;
3479 /* Force split for non-cc0 compare. */
3480 if (which_alternative == 1)
3481 return \"#\";
3483 /* If the bit-field being tested fits in the upper or lower half of a
3484 word, it is possible to use andiu. or andil. to test it. This is
3485 useful because the condition register set-use delay is smaller for
3486 andi[ul]. than for rlinm. This doesn't work when the starting bit
3487 position is 0 because the LT and GT bits may be set wrong. */
3489 if ((start > 0 && start + size <= 16) || start >= 16)
3490 {
3491 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3492 - (1 << (16 - (start & 15) - size))));
3493 if (start < 16)
3494 return \"andis. %4,%1,%3\";
3495 else
3496 return \"andi. %4,%1,%3\";
3497 }
3499 if (start + size >= 32)
3500 operands[3] = const0_rtx;
3501 else
3502 operands[3] = GEN_INT (start + size);
3503 return \"rlwinm. %4,%1,%3,%s2,31\";
3504 }"
3505 [(set_attr "type" "shift")
3506 (set_attr "dot" "yes")
3507 (set_attr "length" "4,8")])
3509 (define_split
3510 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3511 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3512 (match_operand:SI 2 "const_int_operand" "")
3513 (match_operand:SI 3 "const_int_operand" ""))
3514 (const_int 0)))
3515 (clobber (match_scratch:SI 4 ""))]
3516 "reload_completed"
3517 [(set (match_dup 4)
3518 (zero_extract:SI (match_dup 1) (match_dup 2)
3519 (match_dup 3)))
3520 (set (match_dup 0)
3521 (compare:CC (match_dup 4)
3522 (const_int 0)))]
3523 "")
3525 (define_insn "*extzvsi_internal2"
3526 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3527 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3528 (match_operand:SI 2 "const_int_operand" "i,i")
3529 (match_operand:SI 3 "const_int_operand" "i,i"))
3530 (const_int 0)))
3531 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3532 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3533 ""
3534 "*
3535 {
3536 int start = INTVAL (operands[3]) & 31;
3537 int size = INTVAL (operands[2]) & 31;
3539 /* Force split for non-cc0 compare. */
3540 if (which_alternative == 1)
3541 return \"#\";
3543 /* Since we are using the output value, we can't ignore any need for
3544 a shift. The bit-field must end at the LSB. */
3545 if (start >= 16 && start + size == 32)
3546 {
3547 operands[3] = GEN_INT ((1 << size) - 1);
3548 return \"andi. %0,%1,%3\";
3549 }
3551 if (start + size >= 32)
3552 operands[3] = const0_rtx;
3553 else
3554 operands[3] = GEN_INT (start + size);
3555 return \"rlwinm. %0,%1,%3,%s2,31\";
3556 }"
3557 [(set_attr "type" "shift")
3558 (set_attr "dot" "yes")
3559 (set_attr "length" "4,8")])
3561 (define_split
3562 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3563 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3564 (match_operand:SI 2 "const_int_operand" "")
3565 (match_operand:SI 3 "const_int_operand" ""))
3566 (const_int 0)))
3567 (set (match_operand:SI 0 "gpc_reg_operand" "")
3568 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3569 "reload_completed"
3570 [(set (match_dup 0)
3571 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3572 (set (match_dup 4)
3573 (compare:CC (match_dup 0)
3574 (const_int 0)))]
3575 "")
3577 (define_insn "extzvdi_internal"
3578 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3579 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3580 (match_operand:SI 2 "const_int_operand" "i")
3581 (match_operand:SI 3 "const_int_operand" "i")))]
3582 "TARGET_POWERPC64"
3583 "*
3584 {
3585 int start = INTVAL (operands[3]) & 63;
3586 int size = INTVAL (operands[2]) & 63;
3588 if (start + size >= 64)
3589 operands[3] = const0_rtx;
3590 else
3591 operands[3] = GEN_INT (start + size);
3592 operands[2] = GEN_INT (64 - size);
3593 return \"rldicl %0,%1,%3,%2\";
3594 }"
3595 [(set_attr "type" "shift")])
3597 (define_insn "*extzvdi_internal1"
3598 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3599 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3600 (match_operand:SI 2 "const_int_operand" "i")
3601 (match_operand:SI 3 "const_int_operand" "i"))
3602 (const_int 0)))
3603 (clobber (match_scratch:DI 4 "=r"))]
3604 "TARGET_64BIT && rs6000_gen_cell_microcode"
3605 "*
3606 {
3607 int start = INTVAL (operands[3]) & 63;
3608 int size = INTVAL (operands[2]) & 63;
3610 if (start + size >= 64)
3611 operands[3] = const0_rtx;
3612 else
3613 operands[3] = GEN_INT (start + size);
3614 operands[2] = GEN_INT (64 - size);
3615 return \"rldicl. %4,%1,%3,%2\";
3616 }"
3617 [(set_attr "type" "shift")
3618 (set_attr "dot" "yes")])
3620 (define_insn "*extzvdi_internal2"
3621 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3622 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3623 (match_operand:SI 2 "const_int_operand" "i")
3624 (match_operand:SI 3 "const_int_operand" "i"))
3625 (const_int 0)))
3626 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3627 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3628 "TARGET_64BIT && rs6000_gen_cell_microcode"
3629 "*
3630 {
3631 int start = INTVAL (operands[3]) & 63;
3632 int size = INTVAL (operands[2]) & 63;
3634 if (start + size >= 64)
3635 operands[3] = const0_rtx;
3636 else
3637 operands[3] = GEN_INT (start + size);
3638 operands[2] = GEN_INT (64 - size);
3639 return \"rldicl. %0,%1,%3,%2\";
3640 }"
3641 [(set_attr "type" "shift")
3642 (set_attr "dot" "yes")])
3645 (define_insn "rotl<mode>3"
3646 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3647 (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3648 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
3649 ""
3650 "rotl<wd>%I2 %0,%1,%<hH>2"
3651 [(set_attr "type" "shift")
3652 (set_attr "maybe_var_shift" "yes")])
3654 (define_insn "*rotlsi3_64"
3655 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3656 (zero_extend:DI
3657 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3658 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
3659 "TARGET_POWERPC64"
3660 "rotlw%I2 %0,%1,%h2"
3661 [(set_attr "type" "shift")
3662 (set_attr "maybe_var_shift" "yes")])
3664 (define_insn_and_split "*rotl<mode>3_dot"
3665 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3666 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3667 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3668 (const_int 0)))
3669 (clobber (match_scratch:GPR 0 "=r,r"))]
3670 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3671 "@
3672 rotl<wd>%I2. %0,%1,%<hH>2
3673 #"
3674 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3675 [(set (match_dup 0)
3676 (rotate:GPR (match_dup 1)
3677 (match_dup 2)))
3678 (set (match_dup 3)
3679 (compare:CC (match_dup 0)
3680 (const_int 0)))]
3681 ""
3682 [(set_attr "type" "shift")
3683 (set_attr "maybe_var_shift" "yes")
3684 (set_attr "dot" "yes")
3685 (set_attr "length" "4,8")])
3687 (define_insn_and_split "*rotl<mode>3_dot2"
3688 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3689 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3690 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3691 (const_int 0)))
3692 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3693 (rotate:GPR (match_dup 1)
3694 (match_dup 2)))]
3695 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3696 "@
3697 rotl<wd>%I2. %0,%1,%<hH>2
3698 #"
3699 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3700 [(set (match_dup 0)
3701 (rotate:GPR (match_dup 1)
3702 (match_dup 2)))
3703 (set (match_dup 3)
3704 (compare:CC (match_dup 0)
3705 (const_int 0)))]
3706 ""
3707 [(set_attr "type" "shift")
3708 (set_attr "maybe_var_shift" "yes")
3709 (set_attr "dot" "yes")
3710 (set_attr "length" "4,8")])
3713 (define_insn "*rotlsi3_internal4"
3714 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3715 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3716 (match_operand:SI 2 "reg_or_cint_operand" "rn"))
3717 (match_operand:SI 3 "mask_operand" "n")))]
3718 ""
3719 "rlw%I2nm %0,%1,%h2,%m3,%M3"
3720 [(set_attr "type" "shift")
3721 (set_attr "maybe_var_shift" "yes")])
3723 (define_insn "*rotlsi3_internal5"
3724 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3725 (compare:CC (and:SI
3726 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3727 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3728 (match_operand:SI 3 "mask_operand" "n,n"))
3729 (const_int 0)))
3730 (clobber (match_scratch:SI 4 "=r,r"))]
3731 ""
3732 "@
3733 rlw%I2nm. %4,%1,%h2,%m3,%M3
3734 #"
3735 [(set_attr "type" "shift")
3736 (set_attr "maybe_var_shift" "yes")
3737 (set_attr "dot" "yes")
3738 (set_attr "length" "4,8")])
3740 (define_split
3741 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3742 (compare:CC (and:SI
3743 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3744 (match_operand:SI 2 "reg_or_cint_operand" ""))
3745 (match_operand:SI 3 "mask_operand" ""))
3746 (const_int 0)))
3747 (clobber (match_scratch:SI 4 ""))]
3748 "reload_completed"
3749 [(set (match_dup 4)
3750 (and:SI (rotate:SI (match_dup 1)
3751 (match_dup 2))
3752 (match_dup 3)))
3753 (set (match_dup 0)
3754 (compare:CC (match_dup 4)
3755 (const_int 0)))]
3756 "")
3758 (define_insn "*rotlsi3_internal6"
3759 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3760 (compare:CC (and:SI
3761 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3762 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3763 (match_operand:SI 3 "mask_operand" "n,n"))
3764 (const_int 0)))
3765 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3766 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3767 ""
3768 "@
3769 rlw%I2nm. %0,%1,%h2,%m3,%M3
3770 #"
3771 [(set_attr "type" "shift")
3772 (set_attr "maybe_var_shift" "yes")
3773 (set_attr "dot" "yes")
3774 (set_attr "length" "4,8")])
3776 (define_split
3777 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3778 (compare:CC (and:SI
3779 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3780 (match_operand:SI 2 "reg_or_cint_operand" ""))
3781 (match_operand:SI 3 "mask_operand" ""))
3782 (const_int 0)))
3783 (set (match_operand:SI 0 "gpc_reg_operand" "")
3784 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3785 "reload_completed"
3786 [(set (match_dup 0)
3787 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3788 (set (match_dup 4)
3789 (compare:CC (match_dup 0)
3790 (const_int 0)))]
3791 "")
3793 (define_insn "*rotlsi3_internal7le"
3794 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3795 (zero_extend:SI
3796 (subreg:QI
3797 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3798 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3799 "!BYTES_BIG_ENDIAN"
3800 "rlw%I2nm %0,%1,%h2,0xff"
3801 [(set (attr "cell_micro")
3802 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3803 (const_string "not")
3804 (const_string "always")))
3805 (set_attr "type" "shift")])
3807 (define_insn "*rotlsi3_internal7be"
3808 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3809 (zero_extend:SI
3810 (subreg:QI
3811 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3812 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]
3813 "BYTES_BIG_ENDIAN"
3814 "rlw%I2nm %0,%1,%h2,0xff"
3815 [(set (attr "cell_micro")
3816 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3817 (const_string "not")
3818 (const_string "always")))
3819 (set_attr "type" "shift")])
3821 (define_insn "*rotlsi3_internal8le"
3822 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3823 (compare:CC (zero_extend:SI
3824 (subreg:QI
3825 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3826 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3827 (const_int 0)))
3828 (clobber (match_scratch:SI 3 "=r,r"))]
3829 "!BYTES_BIG_ENDIAN"
3830 "@
3831 rlw%I2nm. %3,%1,%h2,0xff
3832 #"
3833 [(set_attr "type" "shift")
3834 (set_attr "maybe_var_shift" "yes")
3835 (set_attr "dot" "yes")
3836 (set_attr "length" "4,8")])
3838 (define_insn "*rotlsi3_internal8be"
3839 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3840 (compare:CC (zero_extend:SI
3841 (subreg:QI
3842 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3843 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3))
3844 (const_int 0)))
3845 (clobber (match_scratch:SI 3 "=r,r"))]
3846 "BYTES_BIG_ENDIAN"
3847 "@
3848 rlw%I2nm. %3,%1,%h2,0xff
3849 #"
3850 [(set_attr "type" "shift")
3851 (set_attr "maybe_var_shift" "yes")
3852 (set_attr "dot" "yes")
3853 (set_attr "length" "4,8")])
3855 (define_split
3856 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3857 (compare:CC (zero_extend:SI
3858 (subreg:QI
3859 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3860 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3861 (const_int 0)))
3862 (clobber (match_scratch:SI 3 ""))]
3863 "!BYTES_BIG_ENDIAN && reload_completed"
3864 [(set (match_dup 3)
3865 (zero_extend:SI (subreg:QI
3866 (rotate:SI (match_dup 1)
3867 (match_dup 2)) 0)))
3868 (set (match_dup 0)
3869 (compare:CC (match_dup 3)
3870 (const_int 0)))]
3871 "")
3873 (define_split
3874 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3875 (compare:CC (zero_extend:SI
3876 (subreg:QI
3877 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3878 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
3879 (const_int 0)))
3880 (clobber (match_scratch:SI 3 ""))]
3881 "BYTES_BIG_ENDIAN && reload_completed"
3882 [(set (match_dup 3)
3883 (zero_extend:SI (subreg:QI
3884 (rotate:SI (match_dup 1)
3885 (match_dup 2)) 3)))
3886 (set (match_dup 0)
3887 (compare:CC (match_dup 3)
3888 (const_int 0)))]
3889 "")
3891 (define_insn "*rotlsi3_internal9le"
3892 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3893 (compare:CC (zero_extend:SI
3894 (subreg:QI
3895 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3896 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3897 (const_int 0)))
3898 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3899 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3900 "!BYTES_BIG_ENDIAN"
3901 "@
3902 rlw%I2nm. %0,%1,%h2,0xff
3903 #"
3904 [(set_attr "type" "shift")
3905 (set_attr "maybe_var_shift" "yes")
3906 (set_attr "dot" "yes")
3907 (set_attr "length" "4,8")])
3909 (define_insn "*rotlsi3_internal9be"
3910 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3911 (compare:CC (zero_extend:SI
3912 (subreg:QI
3913 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3914 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3))
3915 (const_int 0)))
3916 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3917 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
3918 "BYTES_BIG_ENDIAN"
3919 "@
3920 rlw%I2nm. %0,%1,%h2,0xff
3921 #"
3922 [(set_attr "type" "shift")
3923 (set_attr "maybe_var_shift" "yes")
3924 (set_attr "dot" "yes")
3925 (set_attr "length" "4,8")])
3927 (define_split
3928 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3929 (compare:CC (zero_extend:SI
3930 (subreg:QI
3931 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3932 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3933 (const_int 0)))
3934 (set (match_operand:SI 0 "gpc_reg_operand" "")
3935 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3936 "!BYTES_BIG_ENDIAN && reload_completed"
3937 [(set (match_dup 0)
3938 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3939 (set (match_dup 3)
3940 (compare:CC (match_dup 0)
3941 (const_int 0)))]
3942 "")
3944 (define_split
3945 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3946 (compare:CC (zero_extend:SI
3947 (subreg:QI
3948 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3949 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
3950 (const_int 0)))
3951 (set (match_operand:SI 0 "gpc_reg_operand" "")
3952 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
3953 "BYTES_BIG_ENDIAN && reload_completed"
3954 [(set (match_dup 0)
3955 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))
3956 (set (match_dup 3)
3957 (compare:CC (match_dup 0)
3958 (const_int 0)))]
3959 "")
3961 (define_insn "*rotlsi3_internal10le"
3962 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3963 (zero_extend:SI
3964 (subreg:HI
3965 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3966 (match_operand:SI 2 "reg_or_cint_operand" "rn")) 0)))]
3967 "!BYTES_BIG_ENDIAN"
3968 "rlw%I2nm %0,%1,%h2,0xffff"
3969 [(set_attr "type" "shift")
3970 (set_attr "maybe_var_shift" "yes")])
3972 (define_insn "*rotlsi3_internal10be"
3973 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3974 (zero_extend:SI
3975 (subreg:HI
3976 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3977 (match_operand:SI 2 "reg_or_cint_operand" "rn")) 2)))]
3978 "BYTES_BIG_ENDIAN"
3979 "rlw%I2nm %0,%1,%h2,0xffff"
3980 [(set_attr "type" "shift")
3981 (set_attr "maybe_var_shift" "yes")])
3983 (define_insn "*rotlsi3_internal11le"
3984 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3985 (compare:CC (zero_extend:SI
3986 (subreg:HI
3987 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3988 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3989 (const_int 0)))
3990 (clobber (match_scratch:SI 3 "=r,r"))]
3991 "!BYTES_BIG_ENDIAN"
3992 "@
3993 rlw%I2nm. %3,%1,%h2,0xffff
3994 #"
3995 [(set_attr "type" "shift")
3996 (set_attr "maybe_var_shift" "yes")
3997 (set_attr "dot" "yes")
3998 (set_attr "length" "4,8")])
4000 (define_insn "*rotlsi3_internal11be"
4001 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4002 (compare:CC (zero_extend:SI
4003 (subreg:HI
4004 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4005 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2))
4006 (const_int 0)))
4007 (clobber (match_scratch:SI 3 "=r,r"))]
4008 "BYTES_BIG_ENDIAN"
4009 "@
4010 rlw%I2nm. %3,%1,%h2,0xffff
4011 #"
4012 [(set_attr "type" "shift")
4013 (set_attr "maybe_var_shift" "yes")
4014 (set_attr "dot" "yes")
4015 (set_attr "length" "4,8")])
4017 (define_split
4018 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4019 (compare:CC (zero_extend:SI
4020 (subreg:HI
4021 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4022 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4023 (const_int 0)))
4024 (clobber (match_scratch:SI 3 ""))]
4025 "!BYTES_BIG_ENDIAN && reload_completed"
4026 [(set (match_dup 3)
4027 (zero_extend:SI (subreg:HI
4028 (rotate:SI (match_dup 1)
4029 (match_dup 2)) 0)))
4030 (set (match_dup 0)
4031 (compare:CC (match_dup 3)
4032 (const_int 0)))]
4033 "")
4035 (define_split
4036 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4037 (compare:CC (zero_extend:SI
4038 (subreg:HI
4039 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4040 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4041 (const_int 0)))
4042 (clobber (match_scratch:SI 3 ""))]
4043 "BYTES_BIG_ENDIAN && reload_completed"
4044 [(set (match_dup 3)
4045 (zero_extend:SI (subreg:HI
4046 (rotate:SI (match_dup 1)
4047 (match_dup 2)) 2)))
4048 (set (match_dup 0)
4049 (compare:CC (match_dup 3)
4050 (const_int 0)))]
4051 "")
4053 (define_insn "*rotlsi3_internal12le"
4054 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4055 (compare:CC (zero_extend:SI
4056 (subreg:HI
4057 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4058 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
4059 (const_int 0)))
4060 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4061 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4062 "!BYTES_BIG_ENDIAN"
4063 "@
4064 rlw%I2nm. %0,%1,%h2,0xffff
4065 #"
4066 [(set_attr "type" "shift")
4067 (set_attr "maybe_var_shift" "yes")
4068 (set_attr "dot" "yes")
4069 (set_attr "length" "4,8")])
4071 (define_insn "*rotlsi3_internal12be"
4072 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4073 (compare:CC (zero_extend:SI
4074 (subreg:HI
4075 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4076 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2))
4077 (const_int 0)))
4078 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4079 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4080 "BYTES_BIG_ENDIAN"
4081 "@
4082 rlw%I2nm. %0,%1,%h2,0xffff
4083 #"
4084 [(set_attr "type" "shift")
4085 (set_attr "maybe_var_shift" "yes")
4086 (set_attr "dot" "yes")
4087 (set_attr "length" "4,8")])
4089 (define_split
4090 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4091 (compare:CC (zero_extend:SI
4092 (subreg:HI
4093 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4094 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4095 (const_int 0)))
4096 (set (match_operand:SI 0 "gpc_reg_operand" "")
4097 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4098 "!BYTES_BIG_ENDIAN && reload_completed"
4099 [(set (match_dup 0)
4100 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4101 (set (match_dup 3)
4102 (compare:CC (match_dup 0)
4103 (const_int 0)))]
4104 "")
4106 (define_split
4107 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4108 (compare:CC (zero_extend:SI
4109 (subreg:HI
4110 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4111 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4112 (const_int 0)))
4113 (set (match_operand:SI 0 "gpc_reg_operand" "")
4114 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4115 "BYTES_BIG_ENDIAN && reload_completed"
4116 [(set (match_dup 0)
4117 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))
4118 (set (match_dup 3)
4119 (compare:CC (match_dup 0)
4120 (const_int 0)))]
4121 "")
4124 (define_insn "ashl<mode>3"
4125 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4126 (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4127 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4128 ""
4129 "sl<wd>%I2 %0,%1,%<hH>2"
4130 [(set_attr "type" "shift")
4131 (set_attr "maybe_var_shift" "yes")])
4133 (define_insn "*ashlsi3_64"
4134 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4135 (zero_extend:DI
4136 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4137 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4138 "TARGET_POWERPC64"
4139 "slw%I2 %0,%1,%h2"
4140 [(set_attr "type" "shift")
4141 (set_attr "maybe_var_shift" "yes")])
4143 (define_insn_and_split "*ashl<mode>3_dot"
4144 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4145 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4146 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4147 (const_int 0)))
4148 (clobber (match_scratch:GPR 0 "=r,r"))]
4149 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4150 "@
4151 sl<wd>%I2. %0,%1,%<hH>2
4152 #"
4153 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4154 [(set (match_dup 0)
4155 (ashift:GPR (match_dup 1)
4156 (match_dup 2)))
4157 (set (match_dup 3)
4158 (compare:CC (match_dup 0)
4159 (const_int 0)))]
4160 ""
4161 [(set_attr "type" "shift")
4162 (set_attr "maybe_var_shift" "yes")
4163 (set_attr "dot" "yes")
4164 (set_attr "length" "4,8")])
4166 (define_insn_and_split "*ashl<mode>3_dot2"
4167 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4168 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4169 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4170 (const_int 0)))
4171 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4172 (ashift:GPR (match_dup 1)
4173 (match_dup 2)))]
4174 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4175 "@
4176 sl<wd>%I2. %0,%1,%<hH>2
4177 #"
4178 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4179 [(set (match_dup 0)
4180 (ashift:GPR (match_dup 1)
4181 (match_dup 2)))
4182 (set (match_dup 3)
4183 (compare:CC (match_dup 0)
4184 (const_int 0)))]
4185 ""
4186 [(set_attr "type" "shift")
4187 (set_attr "maybe_var_shift" "yes")
4188 (set_attr "dot" "yes")
4189 (set_attr "length" "4,8")])
4192 (define_insn "rlwinm"
4193 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4194 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4195 (match_operand:SI 2 "const_int_operand" "i"))
4196 (match_operand:SI 3 "mask_operand" "n")))]
4197 "includes_lshift_p (operands[2], operands[3])"
4198 "rlwinm %0,%1,%h2,%m3,%M3"
4199 [(set_attr "type" "shift")])
4201 (define_insn ""
4202 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4203 (compare:CC
4204 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4205 (match_operand:SI 2 "const_int_operand" "i,i"))
4206 (match_operand:SI 3 "mask_operand" "n,n"))
4207 (const_int 0)))
4208 (clobber (match_scratch:SI 4 "=r,r"))]
4209 "includes_lshift_p (operands[2], operands[3])"
4210 "@
4211 rlwinm. %4,%1,%h2,%m3,%M3
4212 #"
4213 [(set_attr "type" "shift")
4214 (set_attr "dot" "yes")
4215 (set_attr "length" "4,8")])
4217 (define_split
4218 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4219 (compare:CC
4220 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4221 (match_operand:SI 2 "const_int_operand" ""))
4222 (match_operand:SI 3 "mask_operand" ""))
4223 (const_int 0)))
4224 (clobber (match_scratch:SI 4 ""))]
4225 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4226 [(set (match_dup 4)
4227 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4228 (match_dup 3)))
4229 (set (match_dup 0)
4230 (compare:CC (match_dup 4)
4231 (const_int 0)))]
4232 "")
4234 (define_insn ""
4235 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4236 (compare:CC
4237 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4238 (match_operand:SI 2 "const_int_operand" "i,i"))
4239 (match_operand:SI 3 "mask_operand" "n,n"))
4240 (const_int 0)))
4241 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4242 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4243 "includes_lshift_p (operands[2], operands[3])"
4244 "@
4245 rlwinm. %0,%1,%h2,%m3,%M3
4246 #"
4247 [(set_attr "type" "shift")
4248 (set_attr "dot" "yes")
4249 (set_attr "length" "4,8")])
4251 (define_split
4252 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4253 (compare:CC
4254 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4255 (match_operand:SI 2 "const_int_operand" ""))
4256 (match_operand:SI 3 "mask_operand" ""))
4257 (const_int 0)))
4258 (set (match_operand:SI 0 "gpc_reg_operand" "")
4259 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4260 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4261 [(set (match_dup 0)
4262 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4263 (set (match_dup 4)
4264 (compare:CC (match_dup 0)
4265 (const_int 0)))]
4266 "")
4269 (define_insn "lshr<mode>3"
4270 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4271 (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4272 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4273 ""
4274 "sr<wd>%I2 %0,%1,%<hH>2"
4275 [(set_attr "type" "shift")
4276 (set_attr "maybe_var_shift" "yes")])
4278 (define_insn "*lshrsi3_64"
4279 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4280 (zero_extend:DI
4281 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4282 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4283 "TARGET_POWERPC64"
4284 "srw%I2 %0,%1,%h2"
4285 [(set_attr "type" "shift")
4286 (set_attr "maybe_var_shift" "yes")])
4288 (define_insn_and_split "*lshr<mode>3_dot"
4289 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4290 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4291 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4292 (const_int 0)))
4293 (clobber (match_scratch:GPR 0 "=r,r"))]
4294 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4295 "@
4296 sr<wd>%I2. %0,%1,%<hH>2
4297 #"
4298 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4299 [(set (match_dup 0)
4300 (lshiftrt:GPR (match_dup 1)
4301 (match_dup 2)))
4302 (set (match_dup 3)
4303 (compare:CC (match_dup 0)
4304 (const_int 0)))]
4305 ""
4306 [(set_attr "type" "shift")
4307 (set_attr "maybe_var_shift" "yes")
4308 (set_attr "dot" "yes")
4309 (set_attr "length" "4,8")])
4311 (define_insn_and_split "*lshr<mode>3_dot2"
4312 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4313 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4314 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4315 (const_int 0)))
4316 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4317 (lshiftrt:GPR (match_dup 1)
4318 (match_dup 2)))]
4319 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4320 "@
4321 sr<wd>%I2. %0,%1,%<hH>2
4322 #"
4323 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4324 [(set (match_dup 0)
4325 (lshiftrt:GPR (match_dup 1)
4326 (match_dup 2)))
4327 (set (match_dup 3)
4328 (compare:CC (match_dup 0)
4329 (const_int 0)))]
4330 ""
4331 [(set_attr "type" "shift")
4332 (set_attr "maybe_var_shift" "yes")
4333 (set_attr "dot" "yes")
4334 (set_attr "length" "4,8")])
4337 (define_insn ""
4338 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4339 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4340 (match_operand:SI 2 "const_int_operand" "i"))
4341 (match_operand:SI 3 "mask_operand" "n")))]
4342 "includes_rshift_p (operands[2], operands[3])"
4343 "rlwinm %0,%1,%s2,%m3,%M3"
4344 [(set_attr "type" "shift")])
4346 (define_insn ""
4347 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4348 (compare:CC
4349 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4350 (match_operand:SI 2 "const_int_operand" "i,i"))
4351 (match_operand:SI 3 "mask_operand" "n,n"))
4352 (const_int 0)))
4353 (clobber (match_scratch:SI 4 "=r,r"))]
4354 "includes_rshift_p (operands[2], operands[3])"
4355 "@
4356 rlwinm. %4,%1,%s2,%m3,%M3
4357 #"
4358 [(set_attr "type" "shift")
4359 (set_attr "dot" "yes")
4360 (set_attr "length" "4,8")])
4362 (define_split
4363 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4364 (compare:CC
4365 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4366 (match_operand:SI 2 "const_int_operand" ""))
4367 (match_operand:SI 3 "mask_operand" ""))
4368 (const_int 0)))
4369 (clobber (match_scratch:SI 4 ""))]
4370 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4371 [(set (match_dup 4)
4372 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4373 (match_dup 3)))
4374 (set (match_dup 0)
4375 (compare:CC (match_dup 4)
4376 (const_int 0)))]
4377 "")
4379 (define_insn ""
4380 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4381 (compare:CC
4382 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4383 (match_operand:SI 2 "const_int_operand" "i,i"))
4384 (match_operand:SI 3 "mask_operand" "n,n"))
4385 (const_int 0)))
4386 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4387 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4388 "includes_rshift_p (operands[2], operands[3])"
4389 "@
4390 rlwinm. %0,%1,%s2,%m3,%M3
4391 #"
4392 [(set_attr "type" "shift")
4393 (set_attr "dot" "yes")
4394 (set_attr "length" "4,8")])
4396 (define_split
4397 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4398 (compare:CC
4399 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4400 (match_operand:SI 2 "const_int_operand" ""))
4401 (match_operand:SI 3 "mask_operand" ""))
4402 (const_int 0)))
4403 (set (match_operand:SI 0 "gpc_reg_operand" "")
4404 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4405 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4406 [(set (match_dup 0)
4407 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4408 (set (match_dup 4)
4409 (compare:CC (match_dup 0)
4410 (const_int 0)))]
4411 "")
4413 (define_insn "*lshiftrt_internal1le"
4414 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4415 (zero_extend:SI
4416 (subreg:QI
4417 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4418 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4419 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4420 "rlwinm %0,%1,%s2,0xff"
4421 [(set_attr "type" "shift")])
4423 (define_insn "*lshiftrt_internal1be"
4424 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4425 (zero_extend:SI
4426 (subreg:QI
4427 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4428 (match_operand:SI 2 "const_int_operand" "i")) 3)))]
4429 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4430 "rlwinm %0,%1,%s2,0xff"
4431 [(set_attr "type" "shift")])
4433 (define_insn "*lshiftrt_internal2le"
4434 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4435 (compare:CC
4436 (zero_extend:SI
4437 (subreg:QI
4438 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4439 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4440 (const_int 0)))
4441 (clobber (match_scratch:SI 3 "=r,r"))]
4442 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4443 "@
4444 rlwinm. %3,%1,%s2,0xff
4445 #"
4446 [(set_attr "type" "shift")
4447 (set_attr "dot" "yes")
4448 (set_attr "length" "4,8")])
4450 (define_insn "*lshiftrt_internal2be"
4451 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4452 (compare:CC
4453 (zero_extend:SI
4454 (subreg:QI
4455 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4456 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4457 (const_int 0)))
4458 (clobber (match_scratch:SI 3 "=r,r"))]
4459 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4460 "@
4461 rlwinm. %3,%1,%s2,0xff
4462 #"
4463 [(set_attr "type" "shift")
4464 (set_attr "dot" "yes")
4465 (set_attr "length" "4,8")])
4467 (define_split
4468 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4469 (compare:CC
4470 (zero_extend:SI
4471 (subreg:QI
4472 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4473 (match_operand:SI 2 "const_int_operand" "")) 0))
4474 (const_int 0)))
4475 (clobber (match_scratch:SI 3 ""))]
4476 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4477 [(set (match_dup 3)
4478 (zero_extend:SI (subreg:QI
4479 (lshiftrt:SI (match_dup 1)
4480 (match_dup 2)) 0)))
4481 (set (match_dup 0)
4482 (compare:CC (match_dup 3)
4483 (const_int 0)))]
4484 "")
4486 (define_split
4487 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4488 (compare:CC
4489 (zero_extend:SI
4490 (subreg:QI
4491 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4492 (match_operand:SI 2 "const_int_operand" "")) 3))
4493 (const_int 0)))
4494 (clobber (match_scratch:SI 3 ""))]
4495 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4496 [(set (match_dup 3)
4497 (zero_extend:SI (subreg:QI
4498 (lshiftrt:SI (match_dup 1)
4499 (match_dup 2)) 3)))
4500 (set (match_dup 0)
4501 (compare:CC (match_dup 3)
4502 (const_int 0)))]
4503 "")
4505 (define_insn "*lshiftrt_internal3le"
4506 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4507 (compare:CC
4508 (zero_extend:SI
4509 (subreg:QI
4510 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4511 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4512 (const_int 0)))
4513 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4514 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4515 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4516 "@
4517 rlwinm. %0,%1,%s2,0xff
4518 #"
4519 [(set_attr "type" "shift")
4520 (set_attr "dot" "yes")
4521 (set_attr "length" "4,8")])
4523 (define_insn "*lshiftrt_internal3be"
4524 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4525 (compare:CC
4526 (zero_extend:SI
4527 (subreg:QI
4528 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4529 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4530 (const_int 0)))
4531 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4532 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4533 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4534 "@
4535 rlwinm. %0,%1,%s2,0xff
4536 #"
4537 [(set_attr "type" "shift")
4538 (set_attr "dot" "yes")
4539 (set_attr "length" "4,8")])
4541 (define_split
4542 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4543 (compare:CC
4544 (zero_extend:SI
4545 (subreg:QI
4546 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4547 (match_operand:SI 2 "const_int_operand" "")) 0))
4548 (const_int 0)))
4549 (set (match_operand:SI 0 "gpc_reg_operand" "")
4550 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4551 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4552 [(set (match_dup 0)
4553 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4554 (set (match_dup 3)
4555 (compare:CC (match_dup 0)
4556 (const_int 0)))]
4557 "")
4559 (define_split
4560 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4561 (compare:CC
4562 (zero_extend:SI
4563 (subreg:QI
4564 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4565 (match_operand:SI 2 "const_int_operand" "")) 3))
4566 (const_int 0)))
4567 (set (match_operand:SI 0 "gpc_reg_operand" "")
4568 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4569 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4570 [(set (match_dup 0)
4571 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))
4572 (set (match_dup 3)
4573 (compare:CC (match_dup 0)
4574 (const_int 0)))]
4575 "")
4577 (define_insn "*lshiftrt_internal4le"
4578 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4579 (zero_extend:SI
4580 (subreg:HI
4581 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4582 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4583 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4584 "rlwinm %0,%1,%s2,0xffff"
4585 [(set_attr "type" "shift")])
4587 (define_insn "*lshiftrt_internal4be"
4588 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4589 (zero_extend:SI
4590 (subreg:HI
4591 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4592 (match_operand:SI 2 "const_int_operand" "i")) 2)))]
4593 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4594 "rlwinm %0,%1,%s2,0xffff"
4595 [(set_attr "type" "shift")])
4597 (define_insn "*lshiftrt_internal5le"
4598 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4599 (compare:CC
4600 (zero_extend:SI
4601 (subreg:HI
4602 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4603 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4604 (const_int 0)))
4605 (clobber (match_scratch:SI 3 "=r,r"))]
4606 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4607 "@
4608 rlwinm. %3,%1,%s2,0xffff
4609 #"
4610 [(set_attr "type" "shift")
4611 (set_attr "dot" "yes")
4612 (set_attr "length" "4,8")])
4614 (define_insn "*lshiftrt_internal5be"
4615 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4616 (compare:CC
4617 (zero_extend:SI
4618 (subreg:HI
4619 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4620 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4621 (const_int 0)))
4622 (clobber (match_scratch:SI 3 "=r,r"))]
4623 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4624 "@
4625 rlwinm. %3,%1,%s2,0xffff
4626 #"
4627 [(set_attr "type" "shift")
4628 (set_attr "dot" "yes")
4629 (set_attr "length" "4,8")])
4631 (define_split
4632 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4633 (compare:CC
4634 (zero_extend:SI
4635 (subreg:HI
4636 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4637 (match_operand:SI 2 "const_int_operand" "")) 0))
4638 (const_int 0)))
4639 (clobber (match_scratch:SI 3 ""))]
4640 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4641 [(set (match_dup 3)
4642 (zero_extend:SI (subreg:HI
4643 (lshiftrt:SI (match_dup 1)
4644 (match_dup 2)) 0)))
4645 (set (match_dup 0)
4646 (compare:CC (match_dup 3)
4647 (const_int 0)))]
4648 "")
4650 (define_split
4651 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4652 (compare:CC
4653 (zero_extend:SI
4654 (subreg:HI
4655 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4656 (match_operand:SI 2 "const_int_operand" "")) 2))
4657 (const_int 0)))
4658 (clobber (match_scratch:SI 3 ""))]
4659 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4660 [(set (match_dup 3)
4661 (zero_extend:SI (subreg:HI
4662 (lshiftrt:SI (match_dup 1)
4663 (match_dup 2)) 2)))
4664 (set (match_dup 0)
4665 (compare:CC (match_dup 3)
4666 (const_int 0)))]
4667 "")
4669 (define_insn "*lshiftrt_internal5le"
4670 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4671 (compare:CC
4672 (zero_extend:SI
4673 (subreg:HI
4674 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4675 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4676 (const_int 0)))
4677 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4678 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4679 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4680 "@
4681 rlwinm. %0,%1,%s2,0xffff
4682 #"
4683 [(set_attr "type" "shift")
4684 (set_attr "dot" "yes")
4685 (set_attr "length" "4,8")])
4687 (define_insn "*lshiftrt_internal5be"
4688 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4689 (compare:CC
4690 (zero_extend:SI
4691 (subreg:HI
4692 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4693 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4694 (const_int 0)))
4695 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4696 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4697 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4698 "@
4699 rlwinm. %0,%1,%s2,0xffff
4700 #"
4701 [(set_attr "type" "shift")
4702 (set_attr "dot" "yes")
4703 (set_attr "length" "4,8")])
4705 (define_split
4706 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4707 (compare:CC
4708 (zero_extend:SI
4709 (subreg:HI
4710 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4711 (match_operand:SI 2 "const_int_operand" "")) 0))
4712 (const_int 0)))
4713 (set (match_operand:SI 0 "gpc_reg_operand" "")
4714 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4715 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4716 [(set (match_dup 0)
4717 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4718 (set (match_dup 3)
4719 (compare:CC (match_dup 0)
4720 (const_int 0)))]
4721 "")
4723 (define_split
4724 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4725 (compare:CC
4726 (zero_extend:SI
4727 (subreg:HI
4728 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4729 (match_operand:SI 2 "const_int_operand" "")) 2))
4730 (const_int 0)))
4731 (set (match_operand:SI 0 "gpc_reg_operand" "")
4732 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4733 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4734 [(set (match_dup 0)
4735 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))
4736 (set (match_dup 3)
4737 (compare:CC (match_dup 0)
4738 (const_int 0)))]
4739 "")
4742 (define_expand "ashr<mode>3"
4743 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
4744 (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
4745 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4746 ""
4747 {
4748 /* The generic code does not generate optimal code for the low word
4749 (it should be a rlwimi and a rot). Until we have target code to
4750 solve this generically, keep this expander. */
4752 if (<MODE>mode == DImode && !TARGET_POWERPC64)
4753 {
4754 if (CONST_INT_P (operands[2]))
4755 {
4756 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
4757 DONE;
4758 }
4759 else
4760 FAIL;
4761 }
4762 })
4764 (define_insn "*ashr<mode>3"
4765 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4766 (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4767 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4768 ""
4769 "sra<wd>%I2 %0,%1,%<hH>2"
4770 [(set_attr "type" "shift")
4771 (set_attr "maybe_var_shift" "yes")])
4773 (define_insn "*ashrsi3_64"
4774 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4775 (sign_extend:DI
4776 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4777 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4778 "TARGET_POWERPC64"
4779 "sraw%I2 %0,%1,%h2"
4780 [(set_attr "type" "shift")
4781 (set_attr "maybe_var_shift" "yes")])
4783 (define_insn_and_split "*ashr<mode>3_dot"
4784 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4785 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4786 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4787 (const_int 0)))
4788 (clobber (match_scratch:GPR 0 "=r,r"))]
4789 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4790 "@
4791 sra<wd>%I2. %0,%1,%<hH>2
4792 #"
4793 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4794 [(set (match_dup 0)
4795 (ashiftrt:GPR (match_dup 1)
4796 (match_dup 2)))
4797 (set (match_dup 3)
4798 (compare:CC (match_dup 0)
4799 (const_int 0)))]
4800 ""
4801 [(set_attr "type" "shift")
4802 (set_attr "maybe_var_shift" "yes")
4803 (set_attr "dot" "yes")
4804 (set_attr "length" "4,8")])
4806 (define_insn_and_split "*ashr<mode>3_dot2"
4807 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4808 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4809 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4810 (const_int 0)))
4811 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4812 (ashiftrt:GPR (match_dup 1)
4813 (match_dup 2)))]
4814 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4815 "@
4816 sra<wd>%I2. %0,%1,%<hH>2
4817 #"
4818 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4819 [(set (match_dup 0)
4820 (ashiftrt:GPR (match_dup 1)
4821 (match_dup 2)))
4822 (set (match_dup 3)
4823 (compare:CC (match_dup 0)
4824 (const_int 0)))]
4825 ""
4826 [(set_attr "type" "shift")
4827 (set_attr "maybe_var_shift" "yes")
4828 (set_attr "dot" "yes")
4829 (set_attr "length" "4,8")])
4830 \f
4831 ;; Builtins to replace a division to generate FRE reciprocal estimate
4832 ;; instructions and the necessary fixup instructions
4833 (define_expand "recip<mode>3"
4834 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4835 (match_operand:RECIPF 1 "gpc_reg_operand" "")
4836 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
4837 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
4838 {
4839 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
4840 DONE;
4841 })
4843 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
4844 ;; hardware division. This is only done before register allocation and with
4845 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
4846 (define_split
4847 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
4848 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
4849 (match_operand 2 "gpc_reg_operand" "")))]
4850 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
4851 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
4852 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
4853 [(const_int 0)]
4854 {
4855 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
4856 DONE;
4857 })
4859 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
4860 ;; appropriate fixup.
4861 (define_expand "rsqrt<mode>2"
4862 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4863 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
4864 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4865 {
4866 rs6000_emit_swrsqrt (operands[0], operands[1]);
4867 DONE;
4868 })
4869 \f
4870 ;; Floating-point insns, excluding normal data motion. We combine the SF/DF
4871 ;; modes here, and also add in conditional vsx/power8-vector support to access
4872 ;; values in the traditional Altivec registers if the appropriate
4873 ;; -mupper-regs-{df,sf} option is enabled.
4875 (define_expand "abs<mode>2"
4876 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4877 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
4878 "TARGET_<MODE>_INSN"
4879 "")
4881 (define_insn "*abs<mode>2_fpr"
4882 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4883 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4884 "TARGET_<MODE>_FPR"
4885 "@
4886 fabs %0,%1
4887 xsabsdp %x0,%x1"
4888 [(set_attr "type" "fp")
4889 (set_attr "fp_type" "fp_addsub_<Fs>")])
4891 (define_insn "*nabs<mode>2_fpr"
4892 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4893 (neg:SFDF
4894 (abs:SFDF
4895 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]
4896 "TARGET_<MODE>_FPR"
4897 "@
4898 fnabs %0,%1
4899 xsnabsdp %x0,%x1"
4900 [(set_attr "type" "fp")
4901 (set_attr "fp_type" "fp_addsub_<Fs>")])
4903 (define_expand "neg<mode>2"
4904 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4905 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
4906 "TARGET_<MODE>_INSN"
4907 "")
4909 (define_insn "*neg<mode>2_fpr"
4910 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4911 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4912 "TARGET_<MODE>_FPR"
4913 "@
4914 fneg %0,%1
4915 xsnegdp %x0,%x1"
4916 [(set_attr "type" "fp")
4917 (set_attr "fp_type" "fp_addsub_<Fs>")])
4919 (define_expand "add<mode>3"
4920 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4921 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4922 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4923 "TARGET_<MODE>_INSN"
4924 "")
4926 (define_insn "*add<mode>3_fpr"
4927 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4928 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
4929 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4930 "TARGET_<MODE>_FPR"
4931 "@
4932 fadd<Ftrad> %0,%1,%2
4933 xsadd<Fvsx> %x0,%x1,%x2"
4934 [(set_attr "type" "fp")
4935 (set_attr "fp_type" "fp_addsub_<Fs>")])
4937 (define_expand "sub<mode>3"
4938 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4939 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4940 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4941 "TARGET_<MODE>_INSN"
4942 "")
4944 (define_insn "*sub<mode>3_fpr"
4945 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4946 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
4947 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4948 "TARGET_<MODE>_FPR"
4949 "@
4950 fsub<Ftrad> %0,%1,%2
4951 xssub<Fvsx> %x0,%x1,%x2"
4952 [(set_attr "type" "fp")
4953 (set_attr "fp_type" "fp_addsub_<Fs>")])
4955 (define_expand "mul<mode>3"
4956 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4957 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4958 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4959 "TARGET_<MODE>_INSN"
4960 "")
4962 (define_insn "*mul<mode>3_fpr"
4963 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4964 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
4965 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4966 "TARGET_<MODE>_FPR"
4967 "@
4968 fmul<Ftrad> %0,%1,%2
4969 xsmul<Fvsx> %x0,%x1,%x2"
4970 [(set_attr "type" "dmul")
4971 (set_attr "fp_type" "fp_mul_<Fs>")])
4973 (define_expand "div<mode>3"
4974 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4975 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4976 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4977 "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"
4978 "")
4980 (define_insn "*div<mode>3_fpr"
4981 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4982 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
4983 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4984 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU"
4985 "@
4986 fdiv<Ftrad> %0,%1,%2
4987 xsdiv<Fvsx> %x0,%x1,%x2"
4988 [(set_attr "type" "<Fs>div")
4989 (set_attr "fp_type" "fp_div_<Fs>")])
4991 (define_insn "sqrt<mode>2"
4992 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4993 (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4994 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU
4995 && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"
4996 "@
4997 fsqrt<Ftrad> %0,%1
4998 xssqrt<Fvsx> %x0,%x1"
4999 [(set_attr "type" "<Fs>sqrt")
5000 (set_attr "fp_type" "fp_sqrt_<Fs>")])
5002 ;; Floating point reciprocal approximation
5003 (define_insn "fre<Fs>"
5004 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5005 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5006 UNSPEC_FRES))]
5007 "TARGET_<FFRE>"
5008 "@
5009 fre<Ftrad> %0,%1
5010 xsre<Fvsx> %x0,%x1"
5011 [(set_attr "type" "fp")])
5013 (define_insn "*rsqrt<mode>2"
5014 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5015 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5016 UNSPEC_RSQRT))]
5017 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
5018 "@
5019 frsqrte<Ftrad> %0,%1
5020 xsrsqrte<Fvsx> %x0,%x1"
5021 [(set_attr "type" "fp")])
5023 ;; Floating point comparisons
5024 (define_insn "*cmp<mode>_fpr"
5025 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")
5026 (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5027 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5028 "TARGET_<MODE>_FPR"
5029 "@
5030 fcmpu %0,%1,%2
5031 xscmpudp %0,%x1,%x2"
5032 [(set_attr "type" "fpcompare")])
5034 ;; Floating point conversions
5035 (define_expand "extendsfdf2"
5036 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5037 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5038 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5039 "")
5041 (define_insn_and_split "*extendsfdf2_fpr"
5042 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wv")
5043 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z")))]
5044 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5045 "@
5046 #
5047 fmr %0,%1
5048 lfs%U1%X1 %0,%1
5049 #
5050 xxlor %x0,%x1,%x1
5051 lxsspx %x0,%y1"
5052 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5053 [(const_int 0)]
5054 {
5055 emit_note (NOTE_INSN_DELETED);
5056 DONE;
5057 }
5058 [(set_attr "type" "fp,fp,fpload,fp,vecsimple,fpload")])
5060 (define_expand "truncdfsf2"
5061 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5062 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5063 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5064 "")
5066 (define_insn "*truncdfsf2_fpr"
5067 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5068 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5069 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5070 "frsp %0,%1"
5071 [(set_attr "type" "fp")])
5073 ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in
5074 ;; builtins.c and optabs.c that are not correct for IBM long double
5075 ;; when little-endian.
5076 (define_expand "signbittf2"
5077 [(set (match_dup 2)
5078 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
5079 (set (match_dup 3)
5080 (subreg:DI (match_dup 2) 0))
5081 (set (match_dup 4)
5082 (match_dup 5))
5083 (set (match_operand:SI 0 "gpc_reg_operand" "")
5084 (match_dup 6))]
5085 "!TARGET_IEEEQUAD
5086 && TARGET_HARD_FLOAT
5087 && (TARGET_FPRS || TARGET_E500_DOUBLE)
5088 && TARGET_LONG_DOUBLE_128"
5089 {
5090 operands[2] = gen_reg_rtx (DFmode);
5091 operands[3] = gen_reg_rtx (DImode);
5092 if (TARGET_POWERPC64)
5093 {
5094 operands[4] = gen_reg_rtx (DImode);
5095 operands[5] = gen_rtx_LSHIFTRT (DImode, operands[3], GEN_INT (63));
5096 operands[6] = gen_rtx_SUBREG (SImode, operands[4],
5097 WORDS_BIG_ENDIAN ? 4 : 0);
5098 }
5099 else
5100 {
5101 operands[4] = gen_reg_rtx (SImode);
5102 operands[5] = gen_rtx_SUBREG (SImode, operands[3],
5103 WORDS_BIG_ENDIAN ? 0 : 4);
5104 operands[6] = gen_rtx_LSHIFTRT (SImode, operands[4], GEN_INT (31));
5105 }
5106 })
5108 (define_expand "copysign<mode>3"
5109 [(set (match_dup 3)
5110 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5111 (set (match_dup 4)
5112 (neg:SFDF (abs:SFDF (match_dup 1))))
5113 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5114 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5115 (match_dup 5))
5116 (match_dup 3)
5117 (match_dup 4)))]
5118 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5119 && ((TARGET_PPC_GFXOPT
5120 && !HONOR_NANS (<MODE>mode)
5121 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5122 || TARGET_CMPB
5123 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5124 {
5125 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5126 {
5127 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5128 operands[2]));
5129 DONE;
5130 }
5132 operands[3] = gen_reg_rtx (<MODE>mode);
5133 operands[4] = gen_reg_rtx (<MODE>mode);
5134 operands[5] = CONST0_RTX (<MODE>mode);
5135 })
5137 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
5138 ;; compiler from optimizing -0.0
5139 (define_insn "copysign<mode>3_fcpsgn"
5140 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5141 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5142 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]
5143 UNSPEC_COPYSIGN))]
5144 "TARGET_<MODE>_FPR && TARGET_CMPB"
5145 "@
5146 fcpsgn %0,%2,%1
5147 xscpsgn<Fvsx> %x0,%x2,%x1"
5148 [(set_attr "type" "fp")])
5150 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5151 ;; fsel instruction and some auxiliary computations. Then we just have a
5152 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5153 ;; combine.
5154 ;; For MIN, MAX on non-VSX machines, and conditional move all of the time, we
5155 ;; use DEFINE_EXPAND's that involve a fsel instruction and some auxiliary
5156 ;; computations. Then we just have a single DEFINE_INSN for fsel and the
5157 ;; define_splits to make them if made by combine. On VSX machines we have the
5158 ;; min/max instructions.
5159 ;;
5160 ;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector
5161 ;; to allow either DF/SF to use only traditional registers.
5163 (define_expand "smax<mode>3"
5164 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5165 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5166 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5167 (match_dup 1)
5168 (match_dup 2)))]
5169 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5170 {
5171 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
5172 DONE;
5173 })
5175 (define_insn "*smax<mode>3_vsx"
5176 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5177 (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5178 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5179 "TARGET_<MODE>_FPR && TARGET_VSX"
5180 "xsmaxdp %x0,%x1,%x2"
5181 [(set_attr "type" "fp")])
5183 (define_expand "smin<mode>3"
5184 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5185 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5186 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5187 (match_dup 2)
5188 (match_dup 1)))]
5189 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5190 {
5191 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
5192 DONE;
5193 })
5195 (define_insn "*smin<mode>3_vsx"
5196 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5197 (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5198 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5199 "TARGET_<MODE>_FPR && TARGET_VSX"
5200 "xsmindp %x0,%x1,%x2"
5201 [(set_attr "type" "fp")])
5203 (define_split
5204 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5205 (match_operator:SFDF 3 "min_max_operator"
5206 [(match_operand:SFDF 1 "gpc_reg_operand" "")
5207 (match_operand:SFDF 2 "gpc_reg_operand" "")]))]
5208 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math
5209 && !TARGET_VSX"
5210 [(const_int 0)]
5211 {
5212 rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1],
5213 operands[2]);
5214 DONE;
5215 })
5217 (define_split
5218 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5219 (match_operator:SF 3 "min_max_operator"
5220 [(match_operand:SF 1 "gpc_reg_operand" "")
5221 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5222 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5223 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5224 [(const_int 0)]
5225 "
5226 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5227 operands[1], operands[2]);
5228 DONE;
5229 }")
5231 (define_expand "mov<mode>cc"
5232 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5233 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5234 (match_operand:GPR 2 "gpc_reg_operand" "")
5235 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5236 "TARGET_ISEL<sel>"
5237 "
5238 {
5239 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5240 DONE;
5241 else
5242 FAIL;
5243 }")
5245 ;; We use the BASE_REGS for the isel input operands because, if rA is
5246 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5247 ;; because we may switch the operands and rB may end up being rA.
5248 ;;
5249 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5250 ;; leave out the mode in operand 4 and use one pattern, but reload can
5251 ;; change the mode underneath our feet and then gets confused trying
5252 ;; to reload the value.
5253 (define_insn "isel_signed_<mode>"
5254 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5255 (if_then_else:GPR
5256 (match_operator 1 "scc_comparison_operator"
5257 [(match_operand:CC 4 "cc_reg_operand" "y,y")
5258 (const_int 0)])
5259 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5260 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5261 "TARGET_ISEL<sel>"
5262 "*
5263 { return output_isel (operands); }"
5264 [(set_attr "type" "isel")
5265 (set_attr "length" "4")])
5267 (define_insn "isel_unsigned_<mode>"
5268 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5269 (if_then_else:GPR
5270 (match_operator 1 "scc_comparison_operator"
5271 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
5272 (const_int 0)])
5273 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5274 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5275 "TARGET_ISEL<sel>"
5276 "*
5277 { return output_isel (operands); }"
5278 [(set_attr "type" "isel")
5279 (set_attr "length" "4")])
5281 ;; These patterns can be useful for combine; they let combine know that
5282 ;; isel can handle reversed comparisons so long as the operands are
5283 ;; registers.
5285 (define_insn "*isel_reversed_signed_<mode>"
5286 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5287 (if_then_else:GPR
5288 (match_operator 1 "scc_rev_comparison_operator"
5289 [(match_operand:CC 4 "cc_reg_operand" "y")
5290 (const_int 0)])
5291 (match_operand:GPR 2 "gpc_reg_operand" "b")
5292 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5293 "TARGET_ISEL<sel>"
5294 "*
5295 { return output_isel (operands); }"
5296 [(set_attr "type" "isel")
5297 (set_attr "length" "4")])
5299 (define_insn "*isel_reversed_unsigned_<mode>"
5300 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5301 (if_then_else:GPR
5302 (match_operator 1 "scc_rev_comparison_operator"
5303 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5304 (const_int 0)])
5305 (match_operand:GPR 2 "gpc_reg_operand" "b")
5306 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5307 "TARGET_ISEL<sel>"
5308 "*
5309 { return output_isel (operands); }"
5310 [(set_attr "type" "isel")
5311 (set_attr "length" "4")])
5313 (define_expand "movsfcc"
5314 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5315 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5316 (match_operand:SF 2 "gpc_reg_operand" "")
5317 (match_operand:SF 3 "gpc_reg_operand" "")))]
5318 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5319 "
5320 {
5321 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5322 DONE;
5323 else
5324 FAIL;
5325 }")
5327 (define_insn "*fselsfsf4"
5328 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5329 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5330 (match_operand:SF 4 "zero_fp_constant" "F"))
5331 (match_operand:SF 2 "gpc_reg_operand" "f")
5332 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5333 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5334 "fsel %0,%1,%2,%3"
5335 [(set_attr "type" "fp")])
5337 (define_insn "*fseldfsf4"
5338 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5339 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5340 (match_operand:DF 4 "zero_fp_constant" "F"))
5341 (match_operand:SF 2 "gpc_reg_operand" "f")
5342 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5343 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5344 "fsel %0,%1,%2,%3"
5345 [(set_attr "type" "fp")])
5347 ;; The conditional move instructions allow us to perform max and min
5348 ;; operations even when
5350 (define_split
5351 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5352 (match_operator:DF 3 "min_max_operator"
5353 [(match_operand:DF 1 "gpc_reg_operand" "")
5354 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5355 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5356 && !flag_trapping_math"
5357 [(const_int 0)]
5358 "
5359 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5360 operands[1], operands[2]);
5361 DONE;
5362 }")
5364 (define_expand "movdfcc"
5365 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5366 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5367 (match_operand:DF 2 "gpc_reg_operand" "")
5368 (match_operand:DF 3 "gpc_reg_operand" "")))]
5369 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5370 "
5371 {
5372 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5373 DONE;
5374 else
5375 FAIL;
5376 }")
5378 (define_insn "*fseldfdf4"
5379 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5380 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5381 (match_operand:DF 4 "zero_fp_constant" "F"))
5382 (match_operand:DF 2 "gpc_reg_operand" "d")
5383 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5384 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5385 "fsel %0,%1,%2,%3"
5386 [(set_attr "type" "fp")])
5388 (define_insn "*fselsfdf4"
5389 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5390 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5391 (match_operand:SF 4 "zero_fp_constant" "F"))
5392 (match_operand:DF 2 "gpc_reg_operand" "d")
5393 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5394 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5395 "fsel %0,%1,%2,%3"
5396 [(set_attr "type" "fp")])
5397 \f
5398 ;; Conversions to and from floating-point.
5400 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5401 ; don't want to support putting SImode in FPR registers.
5402 (define_insn "lfiwax"
5403 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
5404 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5405 UNSPEC_LFIWAX))]
5406 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5407 "@
5408 lfiwax %0,%y1
5409 lxsiwax %x0,%y1
5410 mtvsrwa %x0,%1"
5411 [(set_attr "type" "fpload,fpload,mffgpr")])
5413 ; This split must be run before register allocation because it allocates the
5414 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5415 ; it earlier to allow for the combiner to merge insns together where it might
5416 ; not be needed and also in case the insns are deleted as dead code.
5418 (define_insn_and_split "floatsi<mode>2_lfiwax"
5419 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5420 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5421 (clobber (match_scratch:DI 2 "=d"))]
5422 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5423 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5424 "#"
5425 ""
5426 [(pc)]
5427 "
5428 {
5429 rtx dest = operands[0];
5430 rtx src = operands[1];
5431 rtx tmp;
5433 if (!MEM_P (src) && TARGET_POWERPC64
5434 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5435 tmp = convert_to_mode (DImode, src, false);
5436 else
5437 {
5438 tmp = operands[2];
5439 if (GET_CODE (tmp) == SCRATCH)
5440 tmp = gen_reg_rtx (DImode);
5441 if (MEM_P (src))
5442 {
5443 src = rs6000_address_for_fpconvert (src);
5444 emit_insn (gen_lfiwax (tmp, src));
5445 }
5446 else
5447 {
5448 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5449 emit_move_insn (stack, src);
5450 emit_insn (gen_lfiwax (tmp, stack));
5451 }
5452 }
5453 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5454 DONE;
5455 }"
5456 [(set_attr "length" "12")
5457 (set_attr "type" "fpload")])
5459 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5460 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5461 (float:SFDF
5462 (sign_extend:DI
5463 (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
5464 (clobber (match_scratch:DI 2 "=0,d"))]
5465 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5466 && <SI_CONVERT_FP>"
5467 "#"
5468 ""
5469 [(pc)]
5470 "
5471 {
5472 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5473 if (GET_CODE (operands[2]) == SCRATCH)
5474 operands[2] = gen_reg_rtx (DImode);
5475 emit_insn (gen_lfiwax (operands[2], operands[1]));
5476 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5477 DONE;
5478 }"
5479 [(set_attr "length" "8")
5480 (set_attr "type" "fpload")])
5482 (define_insn "lfiwzx"
5483 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
5484 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5485 UNSPEC_LFIWZX))]
5486 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5487 "@
5488 lfiwzx %0,%y1
5489 lxsiwzx %x0,%y1
5490 mtvsrwz %x0,%1"
5491 [(set_attr "type" "fpload,fpload,mftgpr")])
5493 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5494 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5495 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5496 (clobber (match_scratch:DI 2 "=d"))]
5497 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5498 && <SI_CONVERT_FP>"
5499 "#"
5500 ""
5501 [(pc)]
5502 "
5503 {
5504 rtx dest = operands[0];
5505 rtx src = operands[1];
5506 rtx tmp;
5508 if (!MEM_P (src) && TARGET_POWERPC64
5509 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5510 tmp = convert_to_mode (DImode, src, true);
5511 else
5512 {
5513 tmp = operands[2];
5514 if (GET_CODE (tmp) == SCRATCH)
5515 tmp = gen_reg_rtx (DImode);
5516 if (MEM_P (src))
5517 {
5518 src = rs6000_address_for_fpconvert (src);
5519 emit_insn (gen_lfiwzx (tmp, src));
5520 }
5521 else
5522 {
5523 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5524 emit_move_insn (stack, src);
5525 emit_insn (gen_lfiwzx (tmp, stack));
5526 }
5527 }
5528 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5529 DONE;
5530 }"
5531 [(set_attr "length" "12")
5532 (set_attr "type" "fpload")])
5534 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5535 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5536 (unsigned_float:SFDF
5537 (zero_extend:DI
5538 (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
5539 (clobber (match_scratch:DI 2 "=0,d"))]
5540 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5541 && <SI_CONVERT_FP>"
5542 "#"
5543 ""
5544 [(pc)]
5545 "
5546 {
5547 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5548 if (GET_CODE (operands[2]) == SCRATCH)
5549 operands[2] = gen_reg_rtx (DImode);
5550 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5551 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5552 DONE;
5553 }"
5554 [(set_attr "length" "8")
5555 (set_attr "type" "fpload")])
5557 ; For each of these conversions, there is a define_expand, a define_insn
5558 ; with a '#' template, and a define_split (with C code). The idea is
5559 ; to allow constant folding with the template of the define_insn,
5560 ; then to have the insns split later (between sched1 and final).
5562 (define_expand "floatsidf2"
5563 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5564 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5565 (use (match_dup 2))
5566 (use (match_dup 3))
5567 (clobber (match_dup 4))
5568 (clobber (match_dup 5))
5569 (clobber (match_dup 6))])]
5570 "TARGET_HARD_FLOAT
5571 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5572 "
5573 {
5574 if (TARGET_E500_DOUBLE)
5575 {
5576 if (!REG_P (operands[1]))
5577 operands[1] = force_reg (SImode, operands[1]);
5578 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5579 DONE;
5580 }
5581 else if (TARGET_LFIWAX && TARGET_FCFID)
5582 {
5583 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5584 DONE;
5585 }
5586 else if (TARGET_FCFID)
5587 {
5588 rtx dreg = operands[1];
5589 if (!REG_P (dreg))
5590 dreg = force_reg (SImode, dreg);
5591 dreg = convert_to_mode (DImode, dreg, false);
5592 emit_insn (gen_floatdidf2 (operands[0], dreg));
5593 DONE;
5594 }
5596 if (!REG_P (operands[1]))
5597 operands[1] = force_reg (SImode, operands[1]);
5598 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5599 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5600 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5601 operands[5] = gen_reg_rtx (DFmode);
5602 operands[6] = gen_reg_rtx (SImode);
5603 }")
5605 (define_insn_and_split "*floatsidf2_internal"
5606 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5607 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5608 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5609 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5610 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5611 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5612 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5613 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5614 "#"
5615 ""
5616 [(pc)]
5617 "
5618 {
5619 rtx lowword, highword;
5620 gcc_assert (MEM_P (operands[4]));
5621 highword = adjust_address (operands[4], SImode, 0);
5622 lowword = adjust_address (operands[4], SImode, 4);
5623 if (! WORDS_BIG_ENDIAN)
5624 {
5625 rtx tmp;
5626 tmp = highword; highword = lowword; lowword = tmp;
5627 }
5629 emit_insn (gen_xorsi3 (operands[6], operands[1],
5630 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5631 emit_move_insn (lowword, operands[6]);
5632 emit_move_insn (highword, operands[2]);
5633 emit_move_insn (operands[5], operands[4]);
5634 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5635 DONE;
5636 }"
5637 [(set_attr "length" "24")
5638 (set_attr "type" "fp")])
5640 ;; If we don't have a direct conversion to single precision, don't enable this
5641 ;; conversion for 32-bit without fast math, because we don't have the insn to
5642 ;; generate the fixup swizzle to avoid double rounding problems.
5643 (define_expand "floatunssisf2"
5644 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5645 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5646 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5647 && (!TARGET_FPRS
5648 || (TARGET_FPRS
5649 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5650 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5651 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5652 "
5653 {
5654 if (!TARGET_FPRS)
5655 {
5656 if (!REG_P (operands[1]))
5657 operands[1] = force_reg (SImode, operands[1]);
5658 }
5659 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5660 {
5661 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5662 DONE;
5663 }
5664 else
5665 {
5666 rtx dreg = operands[1];
5667 if (!REG_P (dreg))
5668 dreg = force_reg (SImode, dreg);
5669 dreg = convert_to_mode (DImode, dreg, true);
5670 emit_insn (gen_floatdisf2 (operands[0], dreg));
5671 DONE;
5672 }
5673 }")
5675 (define_expand "floatunssidf2"
5676 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5677 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5678 (use (match_dup 2))
5679 (use (match_dup 3))
5680 (clobber (match_dup 4))
5681 (clobber (match_dup 5))])]
5682 "TARGET_HARD_FLOAT
5683 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5684 "
5685 {
5686 if (TARGET_E500_DOUBLE)
5687 {
5688 if (!REG_P (operands[1]))
5689 operands[1] = force_reg (SImode, operands[1]);
5690 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5691 DONE;
5692 }
5693 else if (TARGET_LFIWZX && TARGET_FCFID)
5694 {
5695 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5696 DONE;
5697 }
5698 else if (TARGET_FCFID)
5699 {
5700 rtx dreg = operands[1];
5701 if (!REG_P (dreg))
5702 dreg = force_reg (SImode, dreg);
5703 dreg = convert_to_mode (DImode, dreg, true);
5704 emit_insn (gen_floatdidf2 (operands[0], dreg));
5705 DONE;
5706 }
5708 if (!REG_P (operands[1]))
5709 operands[1] = force_reg (SImode, operands[1]);
5710 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5711 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5712 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5713 operands[5] = gen_reg_rtx (DFmode);
5714 }")
5716 (define_insn_and_split "*floatunssidf2_internal"
5717 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5718 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5719 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5720 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5721 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5722 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5723 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5724 && !(TARGET_FCFID && TARGET_POWERPC64)"
5725 "#"
5726 ""
5727 [(pc)]
5728 "
5729 {
5730 rtx lowword, highword;
5731 gcc_assert (MEM_P (operands[4]));
5732 highword = adjust_address (operands[4], SImode, 0);
5733 lowword = adjust_address (operands[4], SImode, 4);
5734 if (! WORDS_BIG_ENDIAN)
5735 {
5736 rtx tmp;
5737 tmp = highword; highword = lowword; lowword = tmp;
5738 }
5740 emit_move_insn (lowword, operands[1]);
5741 emit_move_insn (highword, operands[2]);
5742 emit_move_insn (operands[5], operands[4]);
5743 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5744 DONE;
5745 }"
5746 [(set_attr "length" "20")
5747 (set_attr "type" "fp")])
5749 (define_expand "fix_trunc<mode>si2"
5750 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5751 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5752 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5753 "
5754 {
5755 if (!<E500_CONVERT>)
5756 {
5757 rtx tmp, stack;
5759 if (TARGET_STFIWX)
5760 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5761 else
5762 {
5763 tmp = gen_reg_rtx (DImode);
5764 stack = rs6000_allocate_stack_temp (DImode, true, false);
5765 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
5766 tmp, stack));
5767 }
5768 DONE;
5769 }
5770 }")
5772 ; Like the convert to float patterns, this insn must be split before
5773 ; register allocation so that it can allocate the memory slot if it
5774 ; needed
5775 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
5776 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5777 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5778 (clobber (match_scratch:DI 2 "=d"))]
5779 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5780 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
5781 && TARGET_STFIWX && can_create_pseudo_p ()"
5782 "#"
5783 ""
5784 [(pc)]
5785 {
5786 rtx dest = operands[0];
5787 rtx src = operands[1];
5788 rtx tmp = operands[2];
5790 if (GET_CODE (tmp) == SCRATCH)
5791 tmp = gen_reg_rtx (DImode);
5793 emit_insn (gen_fctiwz_<mode> (tmp, src));
5794 if (MEM_P (dest))
5795 {
5796 dest = rs6000_address_for_fpconvert (dest);
5797 emit_insn (gen_stfiwx (dest, tmp));
5798 DONE;
5799 }
5800 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5801 {
5802 dest = gen_lowpart (DImode, dest);
5803 emit_move_insn (dest, tmp);
5804 DONE;
5805 }
5806 else
5807 {
5808 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5809 emit_insn (gen_stfiwx (stack, tmp));
5810 emit_move_insn (dest, stack);
5811 DONE;
5812 }
5813 }
5814 [(set_attr "length" "12")
5815 (set_attr "type" "fp")])
5817 (define_insn_and_split "fix_trunc<mode>si2_internal"
5818 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
5819 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
5820 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
5821 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
5822 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5823 "#"
5824 ""
5825 [(pc)]
5826 "
5827 {
5828 rtx lowword;
5829 gcc_assert (MEM_P (operands[3]));
5830 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5832 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
5833 emit_move_insn (operands[3], operands[2]);
5834 emit_move_insn (operands[0], lowword);
5835 DONE;
5836 }"
5837 [(set_attr "length" "16")
5838 (set_attr "type" "fp")])
5840 (define_expand "fix_trunc<mode>di2"
5841 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5842 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5843 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5844 && TARGET_FCFID"
5845 "")
5847 (define_insn "*fix_trunc<mode>di2_fctidz"
5848 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5849 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
5850 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5851 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5852 "fctidz %0,%1"
5853 [(set_attr "type" "fp")])
5855 (define_expand "fixuns_trunc<mode>si2"
5856 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5857 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5858 "TARGET_HARD_FLOAT
5859 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
5860 || <E500_CONVERT>)"
5861 "
5862 {
5863 if (!<E500_CONVERT>)
5864 {
5865 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5866 DONE;
5867 }
5868 }")
5870 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
5871 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5872 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5873 (clobber (match_scratch:DI 2 "=d"))]
5874 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
5875 && TARGET_STFIWX && can_create_pseudo_p ()"
5876 "#"
5877 ""
5878 [(pc)]
5879 {
5880 rtx dest = operands[0];
5881 rtx src = operands[1];
5882 rtx tmp = operands[2];
5884 if (GET_CODE (tmp) == SCRATCH)
5885 tmp = gen_reg_rtx (DImode);
5887 emit_insn (gen_fctiwuz_<mode> (tmp, src));
5888 if (MEM_P (dest))
5889 {
5890 dest = rs6000_address_for_fpconvert (dest);
5891 emit_insn (gen_stfiwx (dest, tmp));
5892 DONE;
5893 }
5894 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5895 {
5896 dest = gen_lowpart (DImode, dest);
5897 emit_move_insn (dest, tmp);
5898 DONE;
5899 }
5900 else
5901 {
5902 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5903 emit_insn (gen_stfiwx (stack, tmp));
5904 emit_move_insn (dest, stack);
5905 DONE;
5906 }
5907 }
5908 [(set_attr "length" "12")
5909 (set_attr "type" "fp")])
5911 (define_expand "fixuns_trunc<mode>di2"
5912 [(set (match_operand:DI 0 "register_operand" "")
5913 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
5914 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
5915 "")
5917 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
5918 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5919 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
5920 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5921 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5922 "fctiduz %0,%1"
5923 [(set_attr "type" "fp")])
5925 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5926 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5927 ; because the first makes it clear that operand 0 is not live
5928 ; before the instruction.
5929 (define_insn "fctiwz_<mode>"
5930 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5931 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
5932 UNSPEC_FCTIWZ))]
5933 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5934 "fctiwz %0,%1"
5935 [(set_attr "type" "fp")])
5937 (define_insn "fctiwuz_<mode>"
5938 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5939 (unspec:DI [(unsigned_fix:SI
5940 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
5941 UNSPEC_FCTIWUZ))]
5942 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
5943 "fctiwuz %0,%1"
5944 [(set_attr "type" "fp")])
5946 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
5947 ;; since the friz instruction does not truncate the value if the floating
5948 ;; point value is < LONG_MIN or > LONG_MAX.
5949 (define_insn "*friz"
5950 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5951 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
5952 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
5953 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
5954 && !flag_trapping_math && TARGET_FRIZ"
5955 "friz %0,%1"
5956 [(set_attr "type" "fp")])
5958 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
5959 ;; load to properly sign extend the value, but at least doing a store, load
5960 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
5961 ;; if we have 32-bit memory ops
5962 (define_insn_and_split "*round32<mode>2_fprs"
5963 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5964 (float:SFDF
5965 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5966 (clobber (match_scratch:DI 2 "=d"))
5967 (clobber (match_scratch:DI 3 "=d"))]
5968 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5969 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
5970 && can_create_pseudo_p ()"
5971 "#"
5972 ""
5973 [(pc)]
5974 {
5975 rtx dest = operands[0];
5976 rtx src = operands[1];
5977 rtx tmp1 = operands[2];
5978 rtx tmp2 = operands[3];
5979 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5981 if (GET_CODE (tmp1) == SCRATCH)
5982 tmp1 = gen_reg_rtx (DImode);
5983 if (GET_CODE (tmp2) == SCRATCH)
5984 tmp2 = gen_reg_rtx (DImode);
5986 emit_insn (gen_fctiwz_<mode> (tmp1, src));
5987 emit_insn (gen_stfiwx (stack, tmp1));
5988 emit_insn (gen_lfiwax (tmp2, stack));
5989 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5990 DONE;
5991 }
5992 [(set_attr "type" "fpload")
5993 (set_attr "length" "16")])
5995 (define_insn_and_split "*roundu32<mode>2_fprs"
5996 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5997 (unsigned_float:SFDF
5998 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5999 (clobber (match_scratch:DI 2 "=d"))
6000 (clobber (match_scratch:DI 3 "=d"))]
6001 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6002 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
6003 && can_create_pseudo_p ()"
6004 "#"
6005 ""
6006 [(pc)]
6007 {
6008 rtx dest = operands[0];
6009 rtx src = operands[1];
6010 rtx tmp1 = operands[2];
6011 rtx tmp2 = operands[3];
6012 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6014 if (GET_CODE (tmp1) == SCRATCH)
6015 tmp1 = gen_reg_rtx (DImode);
6016 if (GET_CODE (tmp2) == SCRATCH)
6017 tmp2 = gen_reg_rtx (DImode);
6019 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
6020 emit_insn (gen_stfiwx (stack, tmp1));
6021 emit_insn (gen_lfiwzx (tmp2, stack));
6022 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6023 DONE;
6024 }
6025 [(set_attr "type" "fpload")
6026 (set_attr "length" "16")])
6028 ;; No VSX equivalent to fctid
6029 (define_insn "lrint<mode>di2"
6030 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6031 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6032 UNSPEC_FCTID))]
6033 "TARGET_<MODE>_FPR && TARGET_FPRND"
6034 "fctid %0,%1"
6035 [(set_attr "type" "fp")])
6037 (define_insn "btrunc<mode>2"
6038 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6039 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6040 UNSPEC_FRIZ))]
6041 "TARGET_<MODE>_FPR && TARGET_FPRND"
6042 "@
6043 friz %0,%1
6044 xsrdpiz %x0,%x1"
6045 [(set_attr "type" "fp")
6046 (set_attr "fp_type" "fp_addsub_<Fs>")])
6048 (define_insn "ceil<mode>2"
6049 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6050 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6051 UNSPEC_FRIP))]
6052 "TARGET_<MODE>_FPR && TARGET_FPRND"
6053 "@
6054 frip %0,%1
6055 xsrdpip %x0,%x1"
6056 [(set_attr "type" "fp")
6057 (set_attr "fp_type" "fp_addsub_<Fs>")])
6059 (define_insn "floor<mode>2"
6060 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6061 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6062 UNSPEC_FRIM))]
6063 "TARGET_<MODE>_FPR && TARGET_FPRND"
6064 "@
6065 frim %0,%1
6066 xsrdpim %x0,%x1"
6067 [(set_attr "type" "fp")
6068 (set_attr "fp_type" "fp_addsub_<Fs>")])
6070 ;; No VSX equivalent to frin
6071 (define_insn "round<mode>2"
6072 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6073 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6074 UNSPEC_FRIN))]
6075 "TARGET_<MODE>_FPR && TARGET_FPRND"
6076 "frin %0,%1"
6077 [(set_attr "type" "fp")
6078 (set_attr "fp_type" "fp_addsub_<Fs>")])
6080 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6081 (define_insn "stfiwx"
6082 [(set (match_operand:SI 0 "memory_operand" "=Z")
6083 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6084 UNSPEC_STFIWX))]
6085 "TARGET_PPC_GFXOPT"
6086 "stfiwx %1,%y0"
6087 [(set_attr "type" "fpstore")])
6089 ;; If we don't have a direct conversion to single precision, don't enable this
6090 ;; conversion for 32-bit without fast math, because we don't have the insn to
6091 ;; generate the fixup swizzle to avoid double rounding problems.
6092 (define_expand "floatsisf2"
6093 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6094 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6095 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6096 && (!TARGET_FPRS
6097 || (TARGET_FPRS
6098 && ((TARGET_FCFIDS && TARGET_LFIWAX)
6099 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6100 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6101 "
6102 {
6103 if (!TARGET_FPRS)
6104 {
6105 if (!REG_P (operands[1]))
6106 operands[1] = force_reg (SImode, operands[1]);
6107 }
6108 else if (TARGET_FCFIDS && TARGET_LFIWAX)
6109 {
6110 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
6111 DONE;
6112 }
6113 else if (TARGET_FCFID && TARGET_LFIWAX)
6114 {
6115 rtx dfreg = gen_reg_rtx (DFmode);
6116 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
6117 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
6118 DONE;
6119 }
6120 else
6121 {
6122 rtx dreg = operands[1];
6123 if (!REG_P (dreg))
6124 dreg = force_reg (SImode, dreg);
6125 dreg = convert_to_mode (DImode, dreg, false);
6126 emit_insn (gen_floatdisf2 (operands[0], dreg));
6127 DONE;
6128 }
6129 }")
6131 (define_expand "floatdidf2"
6132 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6133 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6134 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6135 "")
6137 (define_insn "*floatdidf2_fpr"
6138 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6139 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6140 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6141 && !VECTOR_UNIT_VSX_P (DFmode)"
6142 "fcfid %0,%1"
6143 [(set_attr "type" "fp")])
6145 ; Allow the combiner to merge source memory operands to the conversion so that
6146 ; the optimizer/register allocator doesn't try to load the value too early in a
6147 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
6148 ; hit. We will split after reload to avoid the trip through the GPRs
6150 (define_insn_and_split "*floatdidf2_mem"
6151 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6152 (float:DF (match_operand:DI 1 "memory_operand" "m")))
6153 (clobber (match_scratch:DI 2 "=d"))]
6154 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
6155 "#"
6156 "&& reload_completed"
6157 [(set (match_dup 2) (match_dup 1))
6158 (set (match_dup 0) (float:DF (match_dup 2)))]
6159 ""
6160 [(set_attr "length" "8")
6161 (set_attr "type" "fpload")])
6163 (define_expand "floatunsdidf2"
6164 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6165 (unsigned_float:DF
6166 (match_operand:DI 1 "gpc_reg_operand" "")))]
6167 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6168 "")
6170 (define_insn "*floatunsdidf2_fcfidu"
6171 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6172 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6173 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
6174 "fcfidu %0,%1"
6175 [(set_attr "type" "fp")
6176 (set_attr "length" "4")])
6178 (define_insn_and_split "*floatunsdidf2_mem"
6179 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6180 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
6181 (clobber (match_scratch:DI 2 "=d"))]
6182 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6183 "#"
6184 "&& reload_completed"
6185 [(set (match_dup 2) (match_dup 1))
6186 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
6187 ""
6188 [(set_attr "length" "8")
6189 (set_attr "type" "fpload")])
6191 (define_expand "floatdisf2"
6192 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6193 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6194 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6195 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
6196 "
6197 {
6198 if (!TARGET_FCFIDS)
6199 {
6200 rtx val = operands[1];
6201 if (!flag_unsafe_math_optimizations)
6202 {
6203 rtx label = gen_label_rtx ();
6204 val = gen_reg_rtx (DImode);
6205 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6206 emit_label (label);
6207 }
6208 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6209 DONE;
6210 }
6211 }")
6213 (define_insn "floatdisf2_fcfids"
6214 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6215 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6216 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6217 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6218 "fcfids %0,%1"
6219 [(set_attr "type" "fp")])
6221 (define_insn_and_split "*floatdisf2_mem"
6222 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6223 (float:SF (match_operand:DI 1 "memory_operand" "m")))
6224 (clobber (match_scratch:DI 2 "=f"))]
6225 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6226 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6227 "#"
6228 "&& reload_completed"
6229 [(pc)]
6230 "
6231 {
6232 emit_move_insn (operands[2], operands[1]);
6233 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
6234 DONE;
6235 }"
6236 [(set_attr "length" "8")])
6238 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6239 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6240 ;; from double rounding.
6241 ;; Instead of creating a new cpu type for two FP operations, just use fp
6242 (define_insn_and_split "floatdisf2_internal1"
6243 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6244 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
6245 (clobber (match_scratch:DF 2 "=d"))]
6246 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6247 "#"
6248 "&& reload_completed"
6249 [(set (match_dup 2)
6250 (float:DF (match_dup 1)))
6251 (set (match_dup 0)
6252 (float_truncate:SF (match_dup 2)))]
6253 ""
6254 [(set_attr "length" "8")
6255 (set_attr "type" "fp")])
6257 ;; Twiddles bits to avoid double rounding.
6258 ;; Bits that might be truncated when converting to DFmode are replaced
6259 ;; by a bit that won't be lost at that stage, but is below the SFmode
6260 ;; rounding position.
6261 (define_expand "floatdisf2_internal2"
6262 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6263 (const_int 53)))
6264 (set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6265 (const_int 2047)))
6266 (set (match_dup 3) (plus:DI (match_dup 3)
6267 (const_int 1)))
6268 (set (match_dup 0) (plus:DI (match_dup 0)
6269 (const_int 2047)))
6270 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6271 (const_int 2)))
6272 (set (match_dup 0) (ior:DI (match_dup 0)
6273 (match_dup 1)))
6274 (set (match_dup 0) (and:DI (match_dup 0)
6275 (const_int -2048)))
6276 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6277 (label_ref (match_operand:DI 2 "" ""))
6278 (pc)))
6279 (set (match_dup 0) (match_dup 1))]
6280 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6281 "
6282 {
6283 operands[3] = gen_reg_rtx (DImode);
6284 operands[4] = gen_reg_rtx (CCUNSmode);
6285 }")
6287 (define_expand "floatunsdisf2"
6288 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6289 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6290 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6291 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6292 "")
6294 (define_insn "floatunsdisf2_fcfidus"
6295 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6296 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6297 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6298 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6299 "fcfidus %0,%1"
6300 [(set_attr "type" "fp")])
6302 (define_insn_and_split "*floatunsdisf2_mem"
6303 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6304 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
6305 (clobber (match_scratch:DI 2 "=f"))]
6306 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6307 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6308 "#"
6309 "&& reload_completed"
6310 [(pc)]
6311 "
6312 {
6313 emit_move_insn (operands[2], operands[1]);
6314 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6315 DONE;
6316 }"
6317 [(set_attr "length" "8")
6318 (set_attr "type" "fpload")])
6319 \f
6320 ;; Define the TImode operations that can be done in a small number
6321 ;; of instructions. The & constraints are to prevent the register
6322 ;; allocator from allocating registers that overlap with the inputs
6323 ;; (for example, having an input in 7,8 and an output in 6,7). We
6324 ;; also allow for the output being the same as one of the inputs.
6326 (define_insn "addti3"
6327 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r")
6328 (plus:TI (match_operand:TI 1 "gpc_reg_operand" "%r,r,0,0")
6329 (match_operand:TI 2 "reg_or_short_operand" "r,I,r,I")))]
6330 "TARGET_64BIT"
6331 {
6332 if (WORDS_BIG_ENDIAN)
6333 return (GET_CODE (operands[2])) != CONST_INT
6334 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6335 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6336 else
6337 return (GET_CODE (operands[2])) != CONST_INT
6338 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6339 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6340 }
6341 [(set_attr "type" "two")
6342 (set_attr "length" "8")])
6344 (define_insn "subti3"
6345 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6346 (minus:TI (match_operand:TI 1 "reg_or_short_operand" "r,I,0,r,I")
6347 (match_operand:TI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6348 "TARGET_64BIT"
6349 {
6350 if (WORDS_BIG_ENDIAN)
6351 return (GET_CODE (operands[1]) != CONST_INT)
6352 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6353 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6354 else
6355 return (GET_CODE (operands[1]) != CONST_INT)
6356 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6357 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6358 }
6359 [(set_attr "type" "two")
6360 (set_attr "length" "8")])
6363 ;; Define the DImode operations that can be done in a small number
6364 ;; of instructions. The & constraints are to prevent the register
6365 ;; allocator from allocating registers that overlap with the inputs
6366 ;; (for example, having an input in 7,8 and an output in 6,7). We
6367 ;; also allow for the output being the same as one of the inputs.
6369 (define_insn "*adddi3_noppc64"
6370 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6371 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6372 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6373 "! TARGET_POWERPC64"
6374 "*
6375 {
6376 if (WORDS_BIG_ENDIAN)
6377 return (GET_CODE (operands[2])) != CONST_INT
6378 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6379 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6380 else
6381 return (GET_CODE (operands[2])) != CONST_INT
6382 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6383 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6384 }"
6385 [(set_attr "type" "two")
6386 (set_attr "length" "8")])
6388 (define_insn "*subdi3_noppc64"
6389 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6390 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6391 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6392 "! TARGET_POWERPC64"
6393 "*
6394 {
6395 if (WORDS_BIG_ENDIAN)
6396 return (GET_CODE (operands[1]) != CONST_INT)
6397 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6398 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6399 else
6400 return (GET_CODE (operands[1]) != CONST_INT)
6401 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6402 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6403 }"
6404 [(set_attr "type" "two")
6405 (set_attr "length" "8")])
6407 (define_insn "*negdi2_noppc64"
6408 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6409 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6410 "! TARGET_POWERPC64"
6411 "*
6412 {
6413 return (WORDS_BIG_ENDIAN)
6414 ? \"subfic %L0,%L1,0\;subfze %0,%1\"
6415 : \"subfic %0,%1,0\;subfze %L0,%L1\";
6416 }"
6417 [(set_attr "type" "two")
6418 (set_attr "length" "8")])
6421 ;; Shift by a variable amount is too complex to be worth open-coding. We
6422 ;; just handle shifts by constants.
6423 (define_insn "ashrdi3_no_power"
6424 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6425 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6426 (match_operand:SI 2 "const_int_operand" "M,i")))]
6427 "!TARGET_POWERPC64"
6428 "*
6429 {
6430 switch (which_alternative)
6431 {
6432 default:
6433 gcc_unreachable ();
6434 case 0:
6435 if (WORDS_BIG_ENDIAN)
6436 return \"srawi %0,%1,31\;srawi %L0,%1,%h2\";
6437 else
6438 return \"srawi %L0,%L1,31\;srawi %0,%L1,%h2\";
6439 case 1:
6440 if (WORDS_BIG_ENDIAN)
6441 return \"srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2\";
6442 else
6443 return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\";
6444 }
6445 }"
6446 [(set_attr "type" "two,three")
6447 (set_attr "length" "8,12")])
6449 (define_insn "*ashrdisi3_noppc64be"
6450 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6451 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6452 (const_int 32)) 4))]
6453 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6454 "*
6455 {
6456 if (REGNO (operands[0]) == REGNO (operands[1]))
6457 return \"\";
6458 else
6459 return \"mr %0,%1\";
6460 }"
6461 [(set_attr "length" "4")])
6463 \f
6464 ;; PowerPC64 DImode operations.
6466 (define_insn "*rotldi3_internal4"
6467 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6468 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6469 (match_operand:DI 2 "reg_or_cint_operand" "rn"))
6470 (match_operand:DI 3 "mask64_operand" "n")))]
6471 "TARGET_POWERPC64"
6472 "rld%I2c%B3 %0,%1,%H2,%S3"
6473 [(set_attr "type" "shift")
6474 (set_attr "maybe_var_shift" "yes")])
6476 (define_insn "*rotldi3_internal5"
6477 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6478 (compare:CC (and:DI
6479 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6480 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
6481 (match_operand:DI 3 "mask64_operand" "n,n"))
6482 (const_int 0)))
6483 (clobber (match_scratch:DI 4 "=r,r"))]
6484 "TARGET_64BIT"
6485 "@
6486 rld%I2c%B3. %4,%1,%H2,%S3
6487 #"
6488 [(set_attr "type" "shift")
6489 (set_attr "maybe_var_shift" "yes")
6490 (set_attr "dot" "yes")
6491 (set_attr "length" "4,8")])
6493 (define_split
6494 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6495 (compare:CC (and:DI
6496 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6497 (match_operand:DI 2 "reg_or_cint_operand" ""))
6498 (match_operand:DI 3 "mask64_operand" ""))
6499 (const_int 0)))
6500 (clobber (match_scratch:DI 4 ""))]
6501 "TARGET_POWERPC64 && reload_completed"
6502 [(set (match_dup 4)
6503 (and:DI (rotate:DI (match_dup 1)
6504 (match_dup 2))
6505 (match_dup 3)))
6506 (set (match_dup 0)
6507 (compare:CC (match_dup 4)
6508 (const_int 0)))]
6509 "")
6511 (define_insn "*rotldi3_internal6"
6512 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6513 (compare:CC (and:DI
6514 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6515 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
6516 (match_operand:DI 3 "mask64_operand" "n,n"))
6517 (const_int 0)))
6518 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6519 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6520 "TARGET_64BIT"
6521 "@
6522 rld%I2c%B3. %0,%1,%H2,%S3
6523 #"
6524 [(set_attr "type" "shift")
6525 (set_attr "maybe_var_shift" "yes")
6526 (set_attr "dot" "yes")
6527 (set_attr "length" "4,8")])
6529 (define_split
6530 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6531 (compare:CC (and:DI
6532 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6533 (match_operand:DI 2 "reg_or_cint_operand" ""))
6534 (match_operand:DI 3 "mask64_operand" ""))
6535 (const_int 0)))
6536 (set (match_operand:DI 0 "gpc_reg_operand" "")
6537 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6538 "TARGET_POWERPC64 && reload_completed"
6539 [(set (match_dup 0)
6540 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6541 (set (match_dup 4)
6542 (compare:CC (match_dup 0)
6543 (const_int 0)))]
6544 "")
6546 (define_insn "*rotldi3_internal7le"
6547 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6548 (zero_extend:DI
6549 (subreg:QI
6550 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6551 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6552 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6553 "rld%I2cl %0,%1,%H2,56"
6554 [(set_attr "type" "shift")
6555 (set_attr "maybe_var_shift" "yes")])
6557 (define_insn "*rotldi3_internal7be"
6558 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6559 (zero_extend:DI
6560 (subreg:QI
6561 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6562 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 7)))]
6563 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6564 "rld%I2cl %0,%1,%H2,56"
6565 [(set_attr "type" "shift")
6566 (set_attr "maybe_var_shift" "yes")])
6568 (define_insn "*rotldi3_internal8le"
6569 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6570 (compare:CC (zero_extend:DI
6571 (subreg:QI
6572 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6573 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6574 (const_int 0)))
6575 (clobber (match_scratch:DI 3 "=r,r"))]
6576 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6577 "@
6578 rld%I2cl. %3,%1,%H2,56
6579 #"
6580 [(set_attr "type" "shift")
6581 (set_attr "maybe_var_shift" "yes")
6582 (set_attr "dot" "yes")
6583 (set_attr "length" "4,8")])
6585 (define_insn "*rotldi3_internal8be"
6586 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6587 (compare:CC (zero_extend:DI
6588 (subreg:QI
6589 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6590 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
6591 (const_int 0)))
6592 (clobber (match_scratch:DI 3 "=r,r"))]
6593 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6594 "@
6595 rld%I2cl. %3,%1,%H2,56
6596 #"
6597 [(set_attr "type" "shift")
6598 (set_attr "maybe_var_shift" "yes")
6599 (set_attr "dot" "yes")
6600 (set_attr "length" "4,8")])
6602 (define_split
6603 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6604 (compare:CC (zero_extend:DI
6605 (subreg:QI
6606 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6607 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6608 (const_int 0)))
6609 (clobber (match_scratch:DI 3 ""))]
6610 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6611 [(set (match_dup 3)
6612 (zero_extend:DI (subreg:QI
6613 (rotate:DI (match_dup 1)
6614 (match_dup 2)) 0)))
6615 (set (match_dup 0)
6616 (compare:CC (match_dup 3)
6617 (const_int 0)))]
6618 "")
6620 (define_split
6621 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6622 (compare:CC (zero_extend:DI
6623 (subreg:QI
6624 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6625 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
6626 (const_int 0)))
6627 (clobber (match_scratch:DI 3 ""))]
6628 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6629 [(set (match_dup 3)
6630 (zero_extend:DI (subreg:QI
6631 (rotate:DI (match_dup 1)
6632 (match_dup 2)) 7)))
6633 (set (match_dup 0)
6634 (compare:CC (match_dup 3)
6635 (const_int 0)))]
6636 "")
6638 (define_insn "*rotldi3_internal9le"
6639 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6640 (compare:CC (zero_extend:DI
6641 (subreg:QI
6642 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6643 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6644 (const_int 0)))
6645 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6646 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6647 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6648 "@
6649 rld%I2cl. %0,%1,%H2,56
6650 #"
6651 [(set_attr "type" "shift")
6652 (set_attr "maybe_var_shift" "yes")
6653 (set_attr "dot" "yes")
6654 (set_attr "length" "4,8")])
6656 (define_insn "*rotldi3_internal9be"
6657 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6658 (compare:CC (zero_extend:DI
6659 (subreg:QI
6660 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6661 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
6662 (const_int 0)))
6663 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6664 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
6665 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6666 "@
6667 rld%I2cl. %0,%1,%H2,56
6668 #"
6669 [(set_attr "type" "shift")
6670 (set_attr "maybe_var_shift" "yes")
6671 (set_attr "dot" "yes")
6672 (set_attr "length" "4,8")])
6674 (define_split
6675 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6676 (compare:CC (zero_extend:DI
6677 (subreg:QI
6678 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6679 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6680 (const_int 0)))
6681 (set (match_operand:DI 0 "gpc_reg_operand" "")
6682 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6683 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6684 [(set (match_dup 0)
6685 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6686 (set (match_dup 3)
6687 (compare:CC (match_dup 0)
6688 (const_int 0)))]
6689 "")
6691 (define_split
6692 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6693 (compare:CC (zero_extend:DI
6694 (subreg:QI
6695 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6696 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
6697 (const_int 0)))
6698 (set (match_operand:DI 0 "gpc_reg_operand" "")
6699 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
6700 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6701 [(set (match_dup 0)
6702 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
6703 (set (match_dup 3)
6704 (compare:CC (match_dup 0)
6705 (const_int 0)))]
6706 "")
6708 (define_insn "*rotldi3_internal10le"
6709 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6710 (zero_extend:DI
6711 (subreg:HI
6712 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6713 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6714 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6715 "rld%I2cl %0,%1,%H2,48"
6716 [(set_attr "type" "shift")
6717 (set_attr "maybe_var_shift" "yes")])
6719 (define_insn "*rotldi3_internal10be"
6720 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6721 (zero_extend:DI
6722 (subreg:HI
6723 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6724 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 6)))]
6725 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6726 "rld%I2cl %0,%1,%H2,48"
6727 [(set_attr "type" "shift")
6728 (set_attr "maybe_var_shift" "yes")])
6730 (define_insn "*rotldi3_internal11le"
6731 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6732 (compare:CC (zero_extend:DI
6733 (subreg:HI
6734 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6735 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6736 (const_int 0)))
6737 (clobber (match_scratch:DI 3 "=r,r"))]
6738 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6739 "@
6740 rld%I2cl. %3,%1,%H2,48
6741 #"
6742 [(set_attr "type" "shift")
6743 (set_attr "maybe_var_shift" "yes")
6744 (set_attr "dot" "yes")
6745 (set_attr "length" "4,8")])
6747 (define_insn "*rotldi3_internal11be"
6748 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6749 (compare:CC (zero_extend:DI
6750 (subreg:HI
6751 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6752 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
6753 (const_int 0)))
6754 (clobber (match_scratch:DI 3 "=r,r"))]
6755 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6756 "@
6757 rld%I2cl. %3,%1,%H2,48
6758 #"
6759 [(set_attr "type" "shift")
6760 (set_attr "maybe_var_shift" "yes")
6761 (set_attr "dot" "yes")
6762 (set_attr "length" "4,8")])
6764 (define_split
6765 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6766 (compare:CC (zero_extend:DI
6767 (subreg:HI
6768 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6769 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6770 (const_int 0)))
6771 (clobber (match_scratch:DI 3 ""))]
6772 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6773 [(set (match_dup 3)
6774 (zero_extend:DI (subreg:HI
6775 (rotate:DI (match_dup 1)
6776 (match_dup 2)) 0)))
6777 (set (match_dup 0)
6778 (compare:CC (match_dup 3)
6779 (const_int 0)))]
6780 "")
6782 (define_split
6783 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6784 (compare:CC (zero_extend:DI
6785 (subreg:HI
6786 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6787 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
6788 (const_int 0)))
6789 (clobber (match_scratch:DI 3 ""))]
6790 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6791 [(set (match_dup 3)
6792 (zero_extend:DI (subreg:HI
6793 (rotate:DI (match_dup 1)
6794 (match_dup 2)) 6)))
6795 (set (match_dup 0)
6796 (compare:CC (match_dup 3)
6797 (const_int 0)))]
6798 "")
6800 (define_insn "*rotldi3_internal12le"
6801 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6802 (compare:CC (zero_extend:DI
6803 (subreg:HI
6804 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6805 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6806 (const_int 0)))
6807 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6808 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6809 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6810 "@
6811 rld%I2cl. %0,%1,%H2,48
6812 #"
6813 [(set_attr "type" "shift")
6814 (set_attr "maybe_var_shift" "yes")
6815 (set_attr "dot" "yes")
6816 (set_attr "length" "4,8")])
6818 (define_insn "*rotldi3_internal12be"
6819 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6820 (compare:CC (zero_extend:DI
6821 (subreg:HI
6822 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6823 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
6824 (const_int 0)))
6825 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6826 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
6827 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6828 "@
6829 rld%I2cl. %0,%1,%H2,48
6830 #"
6831 [(set_attr "type" "shift")
6832 (set_attr "maybe_var_shift" "yes")
6833 (set_attr "dot" "yes")
6834 (set_attr "length" "4,8")])
6836 (define_split
6837 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6838 (compare:CC (zero_extend:DI
6839 (subreg:HI
6840 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6841 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6842 (const_int 0)))
6843 (set (match_operand:DI 0 "gpc_reg_operand" "")
6844 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6845 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6846 [(set (match_dup 0)
6847 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6848 (set (match_dup 3)
6849 (compare:CC (match_dup 0)
6850 (const_int 0)))]
6851 "")
6853 (define_split
6854 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6855 (compare:CC (zero_extend:DI
6856 (subreg:HI
6857 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6858 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
6859 (const_int 0)))
6860 (set (match_operand:DI 0 "gpc_reg_operand" "")
6861 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
6862 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6863 [(set (match_dup 0)
6864 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
6865 (set (match_dup 3)
6866 (compare:CC (match_dup 0)
6867 (const_int 0)))]
6868 "")
6870 (define_insn "*rotldi3_internal13le"
6871 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6872 (zero_extend:DI
6873 (subreg:SI
6874 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6875 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6876 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6877 "rld%I2cl %0,%1,%H2,32"
6878 [(set_attr "type" "shift")
6879 (set_attr "maybe_var_shift" "yes")])
6881 (define_insn "*rotldi3_internal13be"
6882 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6883 (zero_extend:DI
6884 (subreg:SI
6885 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6886 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 4)))]
6887 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6888 "rld%I2cl %0,%1,%H2,32"
6889 [(set_attr "type" "shift")
6890 (set_attr "maybe_var_shift" "yes")])
6892 (define_insn "*rotldi3_internal14le"
6893 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6894 (compare:CC (zero_extend:DI
6895 (subreg:SI
6896 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6897 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6898 (const_int 0)))
6899 (clobber (match_scratch:DI 3 "=r,r"))]
6900 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6901 "@
6902 rld%I2cl. %3,%1,%H2,32
6903 #"
6904 [(set_attr "type" "shift")
6905 (set_attr "maybe_var_shift" "yes")
6906 (set_attr "dot" "yes")
6907 (set_attr "length" "4,8")])
6909 (define_insn "*rotldi3_internal14be"
6910 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6911 (compare:CC (zero_extend:DI
6912 (subreg:SI
6913 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6914 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
6915 (const_int 0)))
6916 (clobber (match_scratch:DI 3 "=r,r"))]
6917 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6918 "@
6919 rld%I2cl. %3,%1,%H2,32
6920 #"
6921 [(set_attr "type" "shift")
6922 (set_attr "maybe_var_shift" "yes")
6923 (set_attr "dot" "yes")
6924 (set_attr "length" "4,8")])
6926 (define_split
6927 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6928 (compare:CC (zero_extend:DI
6929 (subreg:SI
6930 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6931 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6932 (const_int 0)))
6933 (clobber (match_scratch:DI 3 ""))]
6934 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6935 [(set (match_dup 3)
6936 (zero_extend:DI (subreg:SI
6937 (rotate:DI (match_dup 1)
6938 (match_dup 2)) 0)))
6939 (set (match_dup 0)
6940 (compare:CC (match_dup 3)
6941 (const_int 0)))]
6942 "")
6944 (define_split
6945 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6946 (compare:CC (zero_extend:DI
6947 (subreg:SI
6948 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6949 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
6950 (const_int 0)))
6951 (clobber (match_scratch:DI 3 ""))]
6952 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6953 [(set (match_dup 3)
6954 (zero_extend:DI (subreg:SI
6955 (rotate:DI (match_dup 1)
6956 (match_dup 2)) 4)))
6957 (set (match_dup 0)
6958 (compare:CC (match_dup 3)
6959 (const_int 0)))]
6960 "")
6962 (define_insn "*rotldi3_internal15le"
6963 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6964 (compare:CC (zero_extend:DI
6965 (subreg:SI
6966 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6967 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6968 (const_int 0)))
6969 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6970 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6971 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6972 "@
6973 rld%I2cl. %0,%1,%H2,32
6974 #"
6975 [(set_attr "type" "shift")
6976 (set_attr "maybe_var_shift" "yes")
6977 (set_attr "dot" "yes")
6978 (set_attr "length" "4,8")])
6980 (define_insn "*rotldi3_internal15be"
6981 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6982 (compare:CC (zero_extend:DI
6983 (subreg:SI
6984 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6985 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
6986 (const_int 0)))
6987 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6988 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
6989 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6990 "@
6991 rld%I2cl. %0,%1,%H2,32
6992 #"
6993 [(set_attr "type" "shift")
6994 (set_attr "maybe_var_shift" "yes")
6995 (set_attr "dot" "yes")
6996 (set_attr "length" "4,8")])
6998 (define_split
6999 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7000 (compare:CC (zero_extend:DI
7001 (subreg:SI
7002 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7003 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7004 (const_int 0)))
7005 (set (match_operand:DI 0 "gpc_reg_operand" "")
7006 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7007 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7008 [(set (match_dup 0)
7009 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7010 (set (match_dup 3)
7011 (compare:CC (match_dup 0)
7012 (const_int 0)))]
7013 "")
7015 (define_split
7016 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7017 (compare:CC (zero_extend:DI
7018 (subreg:SI
7019 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7020 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
7021 (const_int 0)))
7022 (set (match_operand:DI 0 "gpc_reg_operand" "")
7023 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7024 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7025 [(set (match_dup 0)
7026 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
7027 (set (match_dup 3)
7028 (compare:CC (match_dup 0)
7029 (const_int 0)))]
7030 "")
7032 (define_insn "*ashldi3_internal4"
7033 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7034 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7035 (match_operand:SI 2 "const_int_operand" "i"))
7036 (match_operand:DI 3 "const_int_operand" "n")))]
7037 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7038 "rldic %0,%1,%H2,%W3"
7039 [(set_attr "type" "shift")])
7041 (define_insn "ashldi3_internal5"
7042 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7043 (compare:CC
7044 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7045 (match_operand:SI 2 "const_int_operand" "i,i"))
7046 (match_operand:DI 3 "const_int_operand" "n,n"))
7047 (const_int 0)))
7048 (clobber (match_scratch:DI 4 "=r,r"))]
7049 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7050 "@
7051 rldic. %4,%1,%H2,%W3
7052 #"
7053 [(set_attr "type" "shift")
7054 (set_attr "dot" "yes")
7055 (set_attr "length" "4,8")])
7057 (define_split
7058 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7059 (compare:CC
7060 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7061 (match_operand:SI 2 "const_int_operand" ""))
7062 (match_operand:DI 3 "const_int_operand" ""))
7063 (const_int 0)))
7064 (clobber (match_scratch:DI 4 ""))]
7065 "TARGET_POWERPC64 && reload_completed
7066 && includes_rldic_lshift_p (operands[2], operands[3])"
7067 [(set (match_dup 4)
7068 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7069 (match_dup 3)))
7070 (set (match_dup 0)
7071 (compare:CC (match_dup 4)
7072 (const_int 0)))]
7073 "")
7075 (define_insn "*ashldi3_internal6"
7076 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7077 (compare:CC
7078 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7079 (match_operand:SI 2 "const_int_operand" "i,i"))
7080 (match_operand:DI 3 "const_int_operand" "n,n"))
7081 (const_int 0)))
7082 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7083 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7084 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7085 "@
7086 rldic. %0,%1,%H2,%W3
7087 #"
7088 [(set_attr "type" "shift")
7089 (set_attr "dot" "yes")
7090 (set_attr "length" "4,8")])
7092 (define_split
7093 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7094 (compare:CC
7095 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7096 (match_operand:SI 2 "const_int_operand" ""))
7097 (match_operand:DI 3 "const_int_operand" ""))
7098 (const_int 0)))
7099 (set (match_operand:DI 0 "gpc_reg_operand" "")
7100 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7101 "TARGET_POWERPC64 && reload_completed
7102 && includes_rldic_lshift_p (operands[2], operands[3])"
7103 [(set (match_dup 0)
7104 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7105 (match_dup 3)))
7106 (set (match_dup 4)
7107 (compare:CC (match_dup 0)
7108 (const_int 0)))]
7109 "")
7111 (define_insn "*ashldi3_internal7"
7112 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7113 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7114 (match_operand:SI 2 "const_int_operand" "i"))
7115 (match_operand:DI 3 "mask64_operand" "n")))]
7116 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7117 "rldicr %0,%1,%H2,%S3"
7118 [(set_attr "type" "shift")])
7120 (define_insn "ashldi3_internal8"
7121 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7122 (compare:CC
7123 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7124 (match_operand:SI 2 "const_int_operand" "i,i"))
7125 (match_operand:DI 3 "mask64_operand" "n,n"))
7126 (const_int 0)))
7127 (clobber (match_scratch:DI 4 "=r,r"))]
7128 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7129 "@
7130 rldicr. %4,%1,%H2,%S3
7131 #"
7132 [(set_attr "type" "shift")
7133 (set_attr "dot" "yes")
7134 (set_attr "length" "4,8")])
7136 (define_split
7137 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7138 (compare:CC
7139 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7140 (match_operand:SI 2 "const_int_operand" ""))
7141 (match_operand:DI 3 "mask64_operand" ""))
7142 (const_int 0)))
7143 (clobber (match_scratch:DI 4 ""))]
7144 "TARGET_POWERPC64 && reload_completed
7145 && includes_rldicr_lshift_p (operands[2], operands[3])"
7146 [(set (match_dup 4)
7147 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7148 (match_dup 3)))
7149 (set (match_dup 0)
7150 (compare:CC (match_dup 4)
7151 (const_int 0)))]
7152 "")
7154 (define_insn "*ashldi3_internal9"
7155 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7156 (compare:CC
7157 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7158 (match_operand:SI 2 "const_int_operand" "i,i"))
7159 (match_operand:DI 3 "mask64_operand" "n,n"))
7160 (const_int 0)))
7161 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7162 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7163 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7164 "@
7165 rldicr. %0,%1,%H2,%S3
7166 #"
7167 [(set_attr "type" "shift")
7168 (set_attr "dot" "yes")
7169 (set_attr "length" "4,8")])
7171 (define_split
7172 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7173 (compare:CC
7174 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7175 (match_operand:SI 2 "const_int_operand" ""))
7176 (match_operand:DI 3 "mask64_operand" ""))
7177 (const_int 0)))
7178 (set (match_operand:DI 0 "gpc_reg_operand" "")
7179 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7180 "TARGET_POWERPC64 && reload_completed
7181 && includes_rldicr_lshift_p (operands[2], operands[3])"
7182 [(set (match_dup 0)
7183 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7184 (match_dup 3)))
7185 (set (match_dup 4)
7186 (compare:CC (match_dup 0)
7187 (const_int 0)))]
7188 "")
7191 (define_insn_and_split "*anddi3_2rld"
7192 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7193 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
7194 (match_operand:DI 2 "and_2rld_operand" "n")))]
7195 "TARGET_POWERPC64"
7196 "#"
7197 ""
7198 [(set (match_dup 0)
7199 (and:DI (rotate:DI (match_dup 1)
7200 (match_dup 4))
7201 (match_dup 5)))
7202 (set (match_dup 0)
7203 (and:DI (rotate:DI (match_dup 0)
7204 (match_dup 6))
7205 (match_dup 7)))]
7206 {
7207 build_mask64_2_operands (operands[2], &operands[4]);
7208 }
7209 [(set_attr "length" "8")])
7211 (define_insn_and_split "*anddi3_2rld_dot"
7212 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7213 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7214 (match_operand:DI 2 "and_2rld_operand" "n,n"))
7215 (const_int 0)))
7216 (clobber (match_scratch:DI 0 "=r,r"))]
7217 "TARGET_64BIT && rs6000_gen_cell_microcode"
7218 "@
7219 #
7220 #"
7221 "&& reload_completed"
7222 [(set (match_dup 0)
7223 (and:DI (rotate:DI (match_dup 1)
7224 (match_dup 4))
7225 (match_dup 5)))
7226 (parallel [(set (match_dup 3)
7227 (compare:CC (and:DI (rotate:DI (match_dup 0)
7228 (match_dup 6))
7229 (match_dup 7))
7230 (const_int 0)))
7231 (clobber (match_dup 0))])]
7232 {
7233 build_mask64_2_operands (operands[2], &operands[4]);
7234 }
7235 [(set_attr "type" "compare")
7236 (set_attr "dot" "yes")
7237 (set_attr "length" "8,12")])
7239 (define_insn_and_split "*anddi3_2rld_dot2"
7240 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7241 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7242 (match_operand:DI 2 "and_2rld_operand" "n,n"))
7243 (const_int 0)))
7244 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7245 (and:DI (match_dup 1)
7246 (match_dup 2)))]
7247 "TARGET_64BIT && rs6000_gen_cell_microcode"
7248 "@
7249 #
7250 #"
7251 "&& reload_completed"
7252 [(set (match_dup 0)
7253 (and:DI (rotate:DI (match_dup 1)
7254 (match_dup 4))
7255 (match_dup 5)))
7256 (parallel [(set (match_dup 3)
7257 (compare:CC (and:DI (rotate:DI (match_dup 0)
7258 (match_dup 6))
7259 (match_dup 7))
7260 (const_int 0)))
7261 (set (match_dup 0)
7262 (and:DI (rotate:DI (match_dup 0)
7263 (match_dup 6))
7264 (match_dup 7)))])]
7265 {
7266 build_mask64_2_operands (operands[2], &operands[4]);
7267 }
7268 [(set_attr "type" "compare")
7269 (set_attr "dot" "yes")
7270 (set_attr "length" "8,12")])
7271 \f
7272 ;; 128-bit logical operations expanders
7274 (define_expand "and<mode>3"
7275 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7276 (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7277 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7278 ""
7279 "")
7281 (define_expand "ior<mode>3"
7282 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7283 (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7284 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7285 ""
7286 "")
7288 (define_expand "xor<mode>3"
7289 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7290 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7291 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7292 ""
7293 "")
7295 (define_expand "one_cmpl<mode>2"
7296 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7297 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7298 ""
7299 "")
7301 (define_expand "nor<mode>3"
7302 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7303 (and:BOOL_128
7304 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
7305 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7306 ""
7307 "")
7309 (define_expand "andc<mode>3"
7310 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7311 (and:BOOL_128
7312 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
7313 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7314 ""
7315 "")
7317 ;; Power8 vector logical instructions.
7318 (define_expand "eqv<mode>3"
7319 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7320 (not:BOOL_128
7321 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7322 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7323 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7324 "")
7326 ;; Rewrite nand into canonical form
7327 (define_expand "nand<mode>3"
7328 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7329 (ior:BOOL_128
7330 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
7331 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7332 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7333 "")
7335 ;; The canonical form is to have the negated element first, so we need to
7336 ;; reverse arguments.
7337 (define_expand "orc<mode>3"
7338 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7339 (ior:BOOL_128
7340 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
7341 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7342 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7343 "")
7345 ;; 128-bit logical operations insns and split operations
7346 (define_insn_and_split "*and<mode>3_internal"
7347 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7348 (and:BOOL_128
7349 (match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
7350 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))]
7351 ""
7352 {
7353 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7354 return "xxland %x0,%x1,%x2";
7356 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7357 return "vand %0,%1,%2";
7359 return "#";
7360 }
7361 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7362 [(const_int 0)]
7363 {
7364 rs6000_split_logical (operands, AND, false, false, false);
7365 DONE;
7366 }
7367 [(set (attr "type")
7368 (if_then_else
7369 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7370 (const_string "vecsimple")
7371 (const_string "integer")))
7372 (set (attr "length")
7373 (if_then_else
7374 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7375 (const_string "4")
7376 (if_then_else
7377 (match_test "TARGET_POWERPC64")
7378 (const_string "8")
7379 (const_string "16"))))])
7381 ;; 128-bit IOR/XOR
7382 (define_insn_and_split "*bool<mode>3_internal"
7383 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7384 (match_operator:BOOL_128 3 "boolean_or_operator"
7385 [(match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
7386 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
7387 ""
7388 {
7389 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7390 return "xxl%q3 %x0,%x1,%x2";
7392 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7393 return "v%q3 %0,%1,%2";
7395 return "#";
7396 }
7397 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7398 [(const_int 0)]
7399 {
7400 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false);
7401 DONE;
7402 }
7403 [(set (attr "type")
7404 (if_then_else
7405 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7406 (const_string "vecsimple")
7407 (const_string "integer")))
7408 (set (attr "length")
7409 (if_then_else
7410 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7411 (const_string "4")
7412 (if_then_else
7413 (match_test "TARGET_POWERPC64")
7414 (const_string "8")
7415 (const_string "16"))))])
7417 ;; 128-bit ANDC/ORC
7418 (define_insn_and_split "*boolc<mode>3_internal1"
7419 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7420 (match_operator:BOOL_128 3 "boolean_operator"
7421 [(not:BOOL_128
7422 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))
7423 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
7424 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
7425 {
7426 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7427 return "xxl%q3 %x0,%x1,%x2";
7429 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7430 return "v%q3 %0,%1,%2";
7432 return "#";
7433 }
7434 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
7435 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7436 [(const_int 0)]
7437 {
7438 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
7439 DONE;
7440 }
7441 [(set (attr "type")
7442 (if_then_else
7443 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7444 (const_string "vecsimple")
7445 (const_string "integer")))
7446 (set (attr "length")
7447 (if_then_else
7448 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7449 (const_string "4")
7450 (if_then_else
7451 (match_test "TARGET_POWERPC64")
7452 (const_string "8")
7453 (const_string "16"))))])
7455 (define_insn_and_split "*boolc<mode>3_internal2"
7456 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7457 (match_operator:TI2 3 "boolean_operator"
7458 [(not:TI2
7459 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
7460 (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]
7461 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7462 "#"
7463 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7464 [(const_int 0)]
7465 {
7466 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
7467 DONE;
7468 }
7469 [(set_attr "type" "integer")
7470 (set (attr "length")
7471 (if_then_else
7472 (match_test "TARGET_POWERPC64")
7473 (const_string "8")
7474 (const_string "16")))])
7476 ;; 128-bit NAND/NOR
7477 (define_insn_and_split "*boolcc<mode>3_internal1"
7478 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7479 (match_operator:BOOL_128 3 "boolean_operator"
7480 [(not:BOOL_128
7481 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>"))
7482 (not:BOOL_128
7483 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))]))]
7484 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
7485 {
7486 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7487 return "xxl%q3 %x0,%x1,%x2";
7489 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7490 return "v%q3 %0,%1,%2";
7492 return "#";
7493 }
7494 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
7495 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7496 [(const_int 0)]
7497 {
7498 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
7499 DONE;
7500 }
7501 [(set (attr "type")
7502 (if_then_else
7503 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7504 (const_string "vecsimple")
7505 (const_string "integer")))
7506 (set (attr "length")
7507 (if_then_else
7508 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7509 (const_string "4")
7510 (if_then_else
7511 (match_test "TARGET_POWERPC64")
7512 (const_string "8")
7513 (const_string "16"))))])
7515 (define_insn_and_split "*boolcc<mode>3_internal2"
7516 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7517 (match_operator:TI2 3 "boolean_operator"
7518 [(not:TI2
7519 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
7520 (not:TI2
7521 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))]
7522 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7523 "#"
7524 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7525 [(const_int 0)]
7526 {
7527 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
7528 DONE;
7529 }
7530 [(set_attr "type" "integer")
7531 (set (attr "length")
7532 (if_then_else
7533 (match_test "TARGET_POWERPC64")
7534 (const_string "8")
7535 (const_string "16")))])
7538 ;; 128-bit EQV
7539 (define_insn_and_split "*eqv<mode>3_internal1"
7540 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7541 (not:BOOL_128
7542 (xor:BOOL_128
7543 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")
7544 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]
7545 "TARGET_P8_VECTOR"
7546 {
7547 if (vsx_register_operand (operands[0], <MODE>mode))
7548 return "xxleqv %x0,%x1,%x2";
7550 return "#";
7551 }
7552 "TARGET_P8_VECTOR && reload_completed
7553 && int_reg_operand (operands[0], <MODE>mode)"
7554 [(const_int 0)]
7555 {
7556 rs6000_split_logical (operands, XOR, true, false, false);
7557 DONE;
7558 }
7559 [(set (attr "type")
7560 (if_then_else
7561 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7562 (const_string "vecsimple")
7563 (const_string "integer")))
7564 (set (attr "length")
7565 (if_then_else
7566 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7567 (const_string "4")
7568 (if_then_else
7569 (match_test "TARGET_POWERPC64")
7570 (const_string "8")
7571 (const_string "16"))))])
7573 (define_insn_and_split "*eqv<mode>3_internal2"
7574 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7575 (not:TI2
7576 (xor:TI2
7577 (match_operand:TI2 1 "int_reg_operand" "r,0,r")
7578 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))))]
7579 "!TARGET_P8_VECTOR"
7580 "#"
7581 "reload_completed && !TARGET_P8_VECTOR"
7582 [(const_int 0)]
7583 {
7584 rs6000_split_logical (operands, XOR, true, false, false);
7585 DONE;
7586 }
7587 [(set_attr "type" "integer")
7588 (set (attr "length")
7589 (if_then_else
7590 (match_test "TARGET_POWERPC64")
7591 (const_string "8")
7592 (const_string "16")))])
7594 ;; 128-bit one's complement
7595 (define_insn_and_split "*one_cmpl<mode>3_internal"
7596 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7597 (not:BOOL_128
7598 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_UNARY>")))]
7599 ""
7600 {
7601 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7602 return "xxlnor %x0,%x1,%x1";
7604 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7605 return "vnor %0,%1,%1";
7607 return "#";
7608 }
7609 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7610 [(const_int 0)]
7611 {
7612 rs6000_split_logical (operands, NOT, false, false, false);
7613 DONE;
7614 }
7615 [(set (attr "type")
7616 (if_then_else
7617 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7618 (const_string "vecsimple")
7619 (const_string "integer")))
7620 (set (attr "length")
7621 (if_then_else
7622 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7623 (const_string "4")
7624 (if_then_else
7625 (match_test "TARGET_POWERPC64")
7626 (const_string "8")
7627 (const_string "16"))))])
7629 \f
7630 ;; Now define ways of moving data around.
7632 ;; Set up a register with a value from the GOT table
7634 (define_expand "movsi_got"
7635 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7636 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7637 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7638 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7639 "
7640 {
7641 if (GET_CODE (operands[1]) == CONST)
7642 {
7643 rtx offset = const0_rtx;
7644 HOST_WIDE_INT value;
7646 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7647 value = INTVAL (offset);
7648 if (value != 0)
7649 {
7650 rtx tmp = (!can_create_pseudo_p ()
7651 ? operands[0]
7652 : gen_reg_rtx (Pmode));
7653 emit_insn (gen_movsi_got (tmp, operands[1]));
7654 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7655 DONE;
7656 }
7657 }
7659 operands[2] = rs6000_got_register (operands[1]);
7660 }")
7662 (define_insn "*movsi_got_internal"
7663 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7664 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7665 (match_operand:SI 2 "gpc_reg_operand" "b")]
7666 UNSPEC_MOVSI_GOT))]
7667 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7668 "lwz %0,%a1@got(%2)"
7669 [(set_attr "type" "load")])
7671 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7672 ;; didn't get allocated to a hard register.
7673 (define_split
7674 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7675 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7676 (match_operand:SI 2 "memory_operand" "")]
7677 UNSPEC_MOVSI_GOT))]
7678 "DEFAULT_ABI == ABI_V4
7679 && flag_pic == 1
7680 && (reload_in_progress || reload_completed)"
7681 [(set (match_dup 0) (match_dup 2))
7682 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7683 UNSPEC_MOVSI_GOT))]
7684 "")
7686 ;; For SI, we special-case integers that can't be loaded in one insn. We
7687 ;; do the load 16-bits at a time. We could do this by loading from memory,
7688 ;; and this is even supposed to be faster, but it is simpler not to get
7689 ;; integers in the TOC.
7690 (define_insn "movsi_low"
7691 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7692 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7693 (match_operand 2 "" ""))))]
7694 "TARGET_MACHO && ! TARGET_64BIT"
7695 "lwz %0,lo16(%2)(%1)"
7696 [(set_attr "type" "load")
7697 (set_attr "length" "4")])
7699 (define_insn "*movsi_internal1"
7700 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
7701 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
7702 "!TARGET_SINGLE_FPU &&
7703 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7704 "@
7705 mr %0,%1
7706 la %0,%a1
7707 lwz%U1%X1 %0,%1
7708 stw%U0%X0 %1,%0
7709 li %0,%1
7710 lis %0,%v1
7711 #
7712 mf%1 %0
7713 mt%0 %1
7714 mt%0 %1
7715 nop"
7716 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")
7717 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
7719 (define_insn "*movsi_internal1_single"
7720 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
7721 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
7722 "TARGET_SINGLE_FPU &&
7723 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7724 "@
7725 mr %0,%1
7726 la %0,%a1
7727 lwz%U1%X1 %0,%1
7728 stw%U0%X0 %1,%0
7729 li %0,%1
7730 lis %0,%v1
7731 #
7732 mf%1 %0
7733 mt%0 %1
7734 mt%0 %1
7735 nop
7736 stfs%U0%X0 %1,%0
7737 lfs%U1%X1 %0,%1"
7738 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,fpstore,fpload")
7739 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7741 ;; Split a load of a large constant into the appropriate two-insn
7742 ;; sequence.
7744 (define_split
7745 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7746 (match_operand:SI 1 "const_int_operand" ""))]
7747 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7748 && (INTVAL (operands[1]) & 0xffff) != 0"
7749 [(set (match_dup 0)
7750 (match_dup 2))
7751 (set (match_dup 0)
7752 (ior:SI (match_dup 0)
7753 (match_dup 3)))]
7754 "
7755 {
7756 if (rs6000_emit_set_const (operands[0], operands[1]))
7757 DONE;
7758 else
7759 FAIL;
7760 }")
7762 (define_insn "*mov<mode>_internal2"
7763 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7764 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7765 (const_int 0)))
7766 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7767 ""
7768 "@
7769 cmp<wd>i %2,%0,0
7770 mr. %0,%1
7771 #"
7772 [(set_attr "type" "cmp,logical,cmp")
7773 (set_attr "dot" "yes")
7774 (set_attr "length" "4,4,8")])
7776 (define_split
7777 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
7778 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7779 (const_int 0)))
7780 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7781 "reload_completed"
7782 [(set (match_dup 0) (match_dup 1))
7783 (set (match_dup 2)
7784 (compare:CC (match_dup 0)
7785 (const_int 0)))]
7786 "")
7787 \f
7788 (define_insn "*movhi_internal"
7789 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7790 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7791 "gpc_reg_operand (operands[0], HImode)
7792 || gpc_reg_operand (operands[1], HImode)"
7793 "@
7794 mr %0,%1
7795 lhz%U1%X1 %0,%1
7796 sth%U0%X0 %1,%0
7797 li %0,%w1
7798 mf%1 %0
7799 mt%0 %1
7800 nop"
7801 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7803 (define_expand "mov<mode>"
7804 [(set (match_operand:INT 0 "general_operand" "")
7805 (match_operand:INT 1 "any_operand" ""))]
7806 ""
7807 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7809 (define_insn "*movqi_internal"
7810 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7811 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7812 "gpc_reg_operand (operands[0], QImode)
7813 || gpc_reg_operand (operands[1], QImode)"
7814 "@
7815 mr %0,%1
7816 lbz%U1%X1 %0,%1
7817 stb%U0%X0 %1,%0
7818 li %0,%1
7819 mf%1 %0
7820 mt%0 %1
7821 nop"
7822 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7823 \f
7824 ;; Here is how to move condition codes around. When we store CC data in
7825 ;; an integer register or memory, we store just the high-order 4 bits.
7826 ;; This lets us not shift in the most common case of CR0.
7827 (define_expand "movcc"
7828 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7829 (match_operand:CC 1 "nonimmediate_operand" ""))]
7830 ""
7831 "")
7833 (define_insn "*movcc_internal1"
7834 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
7835 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
7836 "register_operand (operands[0], CCmode)
7837 || register_operand (operands[1], CCmode)"
7838 "@
7839 mcrf %0,%1
7840 mtcrf 128,%1
7841 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
7842 crxor %0,%0,%0
7843 mfcr %0%Q1
7844 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
7845 mr %0,%1
7846 li %0,%1
7847 mf%1 %0
7848 mt%0 %1
7849 lwz%U1%X1 %0,%1
7850 stw%U0%X0 %1,%0"
7851 [(set (attr "type")
7852 (cond [(eq_attr "alternative" "0,3")
7853 (const_string "cr_logical")
7854 (eq_attr "alternative" "1,2")
7855 (const_string "mtcr")
7856 (eq_attr "alternative" "6,7")
7857 (const_string "integer")
7858 (eq_attr "alternative" "8")
7859 (const_string "mfjmpr")
7860 (eq_attr "alternative" "9")
7861 (const_string "mtjmpr")
7862 (eq_attr "alternative" "10")
7863 (const_string "load")
7864 (eq_attr "alternative" "11")
7865 (const_string "store")
7866 (match_test "TARGET_MFCRF")
7867 (const_string "mfcrf")
7868 ]
7869 (const_string "mfcr")))
7870 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
7871 \f
7872 ;; For floating-point, we normally deal with the floating-point registers
7873 ;; unless -msoft-float is used. The sole exception is that parameter passing
7874 ;; can produce floating-point values in fixed-point registers. Unless the
7875 ;; value is a simple constant or already in memory, we deal with this by
7876 ;; allocating memory and copying the value explicitly via that memory location.
7878 ;; Move 32-bit binary/decimal floating point
7879 (define_expand "mov<mode>"
7880 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
7881 (match_operand:FMOVE32 1 "any_operand" ""))]
7882 "<fmove_ok>"
7883 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7885 (define_split
7886 [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
7887 (match_operand:FMOVE32 1 "const_double_operand" ""))]
7888 "reload_completed
7889 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7890 || (GET_CODE (operands[0]) == SUBREG
7891 && GET_CODE (SUBREG_REG (operands[0])) == REG
7892 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7893 [(set (match_dup 2) (match_dup 3))]
7894 "
7895 {
7896 long l;
7897 REAL_VALUE_TYPE rv;
7899 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7900 <real_value_to_target> (rv, l);
7902 if (! TARGET_POWERPC64)
7903 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
7904 else
7905 operands[2] = gen_lowpart (SImode, operands[0]);
7907 operands[3] = gen_int_mode (l, SImode);
7908 }")
7910 (define_insn "mov<mode>_hardfloat"
7911 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,wa,wa,<f32_lr>,<f32_sm>,wu,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
7912 (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,wa,j,<f32_lm>,<f32_sr>,Z,wu,r,<f32_dm>,r,h,0,G,Fn"))]
7913 "(gpc_reg_operand (operands[0], <MODE>mode)
7914 || gpc_reg_operand (operands[1], <MODE>mode))
7915 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
7916 "@
7917 mr %0,%1
7918 lwz%U1%X1 %0,%1
7919 stw%U0%X0 %1,%0
7920 fmr %0,%1
7921 xxlor %x0,%x1,%x1
7922 xxlxor %x0,%x0,%x0
7923 <f32_li>
7924 <f32_si>
7925 <f32_lv>
7926 <f32_sv>
7927 mtvsrwz %x0,%1
7928 mfvsrwz %0,%x1
7929 mt%0 %1
7930 mf%1 %0
7931 nop
7932 #
7933 #"
7934 [(set_attr "type" "*,load,store,fp,vecsimple,vecsimple,fpload,fpstore,fpload,fpstore,mftgpr,mffgpr,mtjmpr,mfjmpr,*,*,*")
7935 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")])
7937 (define_insn "*mov<mode>_softfloat"
7938 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
7939 (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
7940 "(gpc_reg_operand (operands[0], <MODE>mode)
7941 || gpc_reg_operand (operands[1], <MODE>mode))
7942 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7943 "@
7944 mr %0,%1
7945 mt%0 %1
7946 mf%1 %0
7947 lwz%U1%X1 %0,%1
7948 stw%U0%X0 %1,%0
7949 li %0,%1
7950 lis %0,%v1
7951 #
7952 #
7953 nop"
7954 [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
7955 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
7957 \f
7958 ;; Move 64-bit binary/decimal floating point
7959 (define_expand "mov<mode>"
7960 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
7961 (match_operand:FMOVE64 1 "any_operand" ""))]
7962 ""
7963 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7965 (define_split
7966 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
7967 (match_operand:FMOVE64 1 "const_int_operand" ""))]
7968 "! TARGET_POWERPC64 && reload_completed
7969 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7970 || (GET_CODE (operands[0]) == SUBREG
7971 && GET_CODE (SUBREG_REG (operands[0])) == REG
7972 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7973 [(set (match_dup 2) (match_dup 4))
7974 (set (match_dup 3) (match_dup 1))]
7975 "
7976 {
7977 int endian = (WORDS_BIG_ENDIAN == 0);
7978 HOST_WIDE_INT value = INTVAL (operands[1]);
7980 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
7981 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
7982 operands[4] = GEN_INT (value >> 32);
7983 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7984 }")
7986 (define_split
7987 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
7988 (match_operand:FMOVE64 1 "const_double_operand" ""))]
7989 "! TARGET_POWERPC64 && reload_completed
7990 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7991 || (GET_CODE (operands[0]) == SUBREG
7992 && GET_CODE (SUBREG_REG (operands[0])) == REG
7993 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7994 [(set (match_dup 2) (match_dup 4))
7995 (set (match_dup 3) (match_dup 5))]
7996 "
7997 {
7998 int endian = (WORDS_BIG_ENDIAN == 0);
7999 long l[2];
8000 REAL_VALUE_TYPE rv;
8002 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8003 <real_value_to_target> (rv, l);
8005 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
8006 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
8007 operands[4] = gen_int_mode (l[endian], SImode);
8008 operands[5] = gen_int_mode (l[1 - endian], SImode);
8009 }")
8011 (define_split
8012 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
8013 (match_operand:FMOVE64 1 "const_double_operand" ""))]
8014 "TARGET_POWERPC64 && reload_completed
8015 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8016 || (GET_CODE (operands[0]) == SUBREG
8017 && GET_CODE (SUBREG_REG (operands[0])) == REG
8018 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8019 [(set (match_dup 2) (match_dup 3))]
8020 "
8021 {
8022 int endian = (WORDS_BIG_ENDIAN == 0);
8023 long l[2];
8024 REAL_VALUE_TYPE rv;
8025 HOST_WIDE_INT val;
8027 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8028 <real_value_to_target> (rv, l);
8030 operands[2] = gen_lowpart (DImode, operands[0]);
8031 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8032 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8033 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8035 operands[3] = gen_int_mode (val, DImode);
8036 }")
8038 ;; Don't have reload use general registers to load a constant. It is
8039 ;; less efficient than loading the constant into an FP register, since
8040 ;; it will probably be used there.
8042 ;; The move constraints are ordered to prefer floating point registers before
8043 ;; general purpose registers to avoid doing a store and a load to get the value
8044 ;; into a floating point register when it is needed for a floating point
8045 ;; operation. Prefer traditional floating point registers over VSX registers,
8046 ;; since the D-form version of the memory instructions does not need a GPR for
8047 ;; reloading.
8049 (define_insn "*mov<mode>_hardfloat32"
8050 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,!r,!r,!r")
8051 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,G,H,F"))]
8052 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8053 && (gpc_reg_operand (operands[0], <MODE>mode)
8054 || gpc_reg_operand (operands[1], <MODE>mode))"
8055 "@
8056 stfd%U0%X0 %1,%0
8057 lfd%U1%X1 %0,%1
8058 fmr %0,%1
8059 lxsd%U1x %x0,%y1
8060 stxsd%U0x %x1,%y0
8061 xxlor %x0,%x1,%x1
8062 xxlxor %x0,%x0,%x0
8063 #
8064 #
8065 #
8066 #
8067 #
8068 #"
8069 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,two,fp,fp,*")
8070 (set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")])
8072 (define_insn "*mov<mode>_softfloat32"
8073 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
8074 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
8075 "! TARGET_POWERPC64
8076 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
8077 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
8078 || (<MODE>mode == DDmode && TARGET_E500_DOUBLE))
8079 && (gpc_reg_operand (operands[0], <MODE>mode)
8080 || gpc_reg_operand (operands[1], <MODE>mode))"
8081 "#"
8082 [(set_attr "type" "store,load,two,*,*,*")
8083 (set_attr "length" "8,8,8,8,12,16")])
8085 ; ld/std require word-aligned displacements -> 'Y' constraint.
8086 ; List Y->r and r->Y before r->r for reload.
8087 (define_insn "*mov<mode>_hardfloat64"
8088 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wk")
8089 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wk,r"))]
8090 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8091 && (gpc_reg_operand (operands[0], <MODE>mode)
8092 || gpc_reg_operand (operands[1], <MODE>mode))"
8093 "@
8094 stfd%U0%X0 %1,%0
8095 lfd%U1%X1 %0,%1
8096 fmr %0,%1
8097 lxsd%U1x %x0,%y1
8098 stxsd%U0x %x1,%y0
8099 xxlor %x0,%x1,%x1
8100 xxlxor %x0,%x0,%x0
8101 std%U0%X0 %1,%0
8102 ld%U1%X1 %0,%1
8103 mr %0,%1
8104 mt%0 %1
8105 mf%1 %0
8106 nop
8107 #
8108 #
8109 #
8110 mftgpr %0,%1
8111 mffgpr %0,%1
8112 mfvsrd %0,%x1
8113 mtvsrd %x0,%1"
8114 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,*,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr,mftgpr,mffgpr")
8115 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")])
8117 (define_insn "*mov<mode>_softfloat64"
8118 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
8119 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
8120 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8121 && (gpc_reg_operand (operands[0], <MODE>mode)
8122 || gpc_reg_operand (operands[1], <MODE>mode))"
8123 "@
8124 std%U0%X0 %1,%0
8125 ld%U1%X1 %0,%1
8126 mr %0,%1
8127 mt%0 %1
8128 mf%1 %0
8129 #
8130 #
8131 #
8132 nop"
8133 [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
8134 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8135 \f
8136 (define_expand "mov<mode>"
8137 [(set (match_operand:FMOVE128 0 "general_operand" "")
8138 (match_operand:FMOVE128 1 "any_operand" ""))]
8139 ""
8140 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8142 ;; It's important to list Y->r and r->Y before r->r because otherwise
8143 ;; reload, given m->r, will try to pick r->r and reload it, which
8144 ;; doesn't make progress.
8146 ;; We can't split little endian direct moves of TDmode, because the words are
8147 ;; not swapped like they are for TImode or TFmode. Subregs therefore are
8148 ;; problematical. Don't allow direct move for this case.
8150 (define_insn_and_split "*mov<mode>_64bit_dm"
8151 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r,r,wm")
8152 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r,wm,r"))]
8153 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
8154 && (<MODE>mode != TDmode || WORDS_BIG_ENDIAN)
8155 && (gpc_reg_operand (operands[0], <MODE>mode)
8156 || gpc_reg_operand (operands[1], <MODE>mode))"
8157 "#"
8158 "&& reload_completed"
8159 [(pc)]
8160 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8161 [(set_attr "length" "8,8,8,12,12,8,8,8")])
8163 (define_insn_and_split "*movtd_64bit_nodm"
8164 [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
8165 (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))]
8166 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
8167 && (gpc_reg_operand (operands[0], TDmode)
8168 || gpc_reg_operand (operands[1], TDmode))"
8169 "#"
8170 "&& reload_completed"
8171 [(pc)]
8172 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8173 [(set_attr "length" "8,8,8,12,12,8")])
8175 (define_insn_and_split "*mov<mode>_32bit"
8176 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
8177 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))]
8178 "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64
8179 && (gpc_reg_operand (operands[0], <MODE>mode)
8180 || gpc_reg_operand (operands[1], <MODE>mode))"
8181 "#"
8182 "&& reload_completed"
8183 [(pc)]
8184 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8185 [(set_attr "length" "8,8,8,20,20,16")])
8187 (define_insn_and_split "*mov<mode>_softfloat"
8188 [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
8189 (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
8190 "(TARGET_SOFT_FLOAT || !TARGET_FPRS)
8191 && (gpc_reg_operand (operands[0], <MODE>mode)
8192 || gpc_reg_operand (operands[1], <MODE>mode))"
8193 "#"
8194 "&& reload_completed"
8195 [(pc)]
8196 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8197 [(set_attr "length" "20,20,16")])
8199 (define_expand "extenddftf2"
8200 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8201 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8202 "!TARGET_IEEEQUAD
8203 && TARGET_HARD_FLOAT
8204 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8205 && TARGET_LONG_DOUBLE_128"
8206 {
8207 if (TARGET_E500_DOUBLE)
8208 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8209 else
8210 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8211 DONE;
8212 })
8214 (define_expand "extenddftf2_fprs"
8215 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8216 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8217 (use (match_dup 2))])]
8218 "!TARGET_IEEEQUAD
8219 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8220 && TARGET_LONG_DOUBLE_128"
8221 {
8222 operands[2] = CONST0_RTX (DFmode);
8223 /* Generate GOT reference early for SVR4 PIC. */
8224 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8225 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8226 })
8228 (define_insn_and_split "*extenddftf2_internal"
8229 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
8230 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
8231 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
8232 "!TARGET_IEEEQUAD
8233 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8234 && TARGET_LONG_DOUBLE_128"
8235 "#"
8236 "&& reload_completed"
8237 [(pc)]
8238 {
8239 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
8240 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
8241 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8242 operands[1]);
8243 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8244 operands[2]);
8245 DONE;
8246 })
8248 (define_expand "extendsftf2"
8249 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8250 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8251 "!TARGET_IEEEQUAD
8252 && TARGET_HARD_FLOAT
8253 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8254 && TARGET_LONG_DOUBLE_128"
8255 {
8256 rtx tmp = gen_reg_rtx (DFmode);
8257 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8258 emit_insn (gen_extenddftf2 (operands[0], tmp));
8259 DONE;
8260 })
8262 (define_expand "trunctfdf2"
8263 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8264 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8265 "!TARGET_IEEEQUAD
8266 && TARGET_HARD_FLOAT
8267 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8268 && TARGET_LONG_DOUBLE_128"
8269 "")
8271 (define_insn_and_split "trunctfdf2_internal1"
8272 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
8273 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
8274 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8275 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8276 "@
8277 #
8278 fmr %0,%1"
8279 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8280 [(const_int 0)]
8281 {
8282 emit_note (NOTE_INSN_DELETED);
8283 DONE;
8284 }
8285 [(set_attr "type" "fp")])
8287 (define_insn "trunctfdf2_internal2"
8288 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8289 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8290 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8291 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8292 && TARGET_LONG_DOUBLE_128"
8293 "fadd %0,%1,%L1"
8294 [(set_attr "type" "fp")
8295 (set_attr "fp_type" "fp_addsub_d")])
8297 (define_expand "trunctfsf2"
8298 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8299 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8300 "!TARGET_IEEEQUAD
8301 && TARGET_HARD_FLOAT
8302 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8303 && TARGET_LONG_DOUBLE_128"
8304 {
8305 if (TARGET_E500_DOUBLE)
8306 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8307 else
8308 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8309 DONE;
8310 })
8312 (define_insn_and_split "trunctfsf2_fprs"
8313 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8314 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
8315 (clobber (match_scratch:DF 2 "=d"))]
8316 "!TARGET_IEEEQUAD
8317 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8318 && TARGET_LONG_DOUBLE_128"
8319 "#"
8320 "&& reload_completed"
8321 [(set (match_dup 2)
8322 (float_truncate:DF (match_dup 1)))
8323 (set (match_dup 0)
8324 (float_truncate:SF (match_dup 2)))]
8325 "")
8327 (define_expand "floatsitf2"
8328 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8329 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8330 "!TARGET_IEEEQUAD
8331 && TARGET_HARD_FLOAT
8332 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8333 && TARGET_LONG_DOUBLE_128"
8334 {
8335 rtx tmp = gen_reg_rtx (DFmode);
8336 expand_float (tmp, operands[1], false);
8337 emit_insn (gen_extenddftf2 (operands[0], tmp));
8338 DONE;
8339 })
8341 ; fadd, but rounding towards zero.
8342 ; This is probably not the optimal code sequence.
8343 (define_insn "fix_trunc_helper"
8344 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8345 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
8346 UNSPEC_FIX_TRUNC_TF))
8347 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
8348 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8349 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8350 [(set_attr "type" "fp")
8351 (set_attr "length" "20")])
8353 (define_expand "fix_trunctfsi2"
8354 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8355 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8356 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
8357 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
8358 {
8359 if (TARGET_E500_DOUBLE)
8360 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8361 else
8362 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8363 DONE;
8364 })
8366 (define_expand "fix_trunctfsi2_fprs"
8367 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8368 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8369 (clobber (match_dup 2))
8370 (clobber (match_dup 3))
8371 (clobber (match_dup 4))
8372 (clobber (match_dup 5))])]
8373 "!TARGET_IEEEQUAD
8374 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8375 {
8376 operands[2] = gen_reg_rtx (DFmode);
8377 operands[3] = gen_reg_rtx (DFmode);
8378 operands[4] = gen_reg_rtx (DImode);
8379 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
8380 })
8382 (define_insn_and_split "*fix_trunctfsi2_internal"
8383 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8384 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
8385 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
8386 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
8387 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
8388 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8389 "!TARGET_IEEEQUAD
8390 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8391 "#"
8392 ""
8393 [(pc)]
8394 {
8395 rtx lowword;
8396 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8398 gcc_assert (MEM_P (operands[5]));
8399 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8401 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
8402 emit_move_insn (operands[5], operands[4]);
8403 emit_move_insn (operands[0], lowword);
8404 DONE;
8405 })
8407 (define_expand "negtf2"
8408 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8409 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8410 "!TARGET_IEEEQUAD
8411 && TARGET_HARD_FLOAT
8412 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8413 && TARGET_LONG_DOUBLE_128"
8414 "")
8416 (define_insn "negtf2_internal"
8417 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
8418 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8419 "!TARGET_IEEEQUAD
8420 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8421 "*
8422 {
8423 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8424 return \"fneg %L0,%L1\;fneg %0,%1\";
8425 else
8426 return \"fneg %0,%1\;fneg %L0,%L1\";
8427 }"
8428 [(set_attr "type" "fp")
8429 (set_attr "length" "8")])
8431 (define_expand "abstf2"
8432 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8433 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8434 "!TARGET_IEEEQUAD
8435 && TARGET_HARD_FLOAT
8436 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8437 && TARGET_LONG_DOUBLE_128"
8438 "
8439 {
8440 rtx label = gen_label_rtx ();
8441 if (TARGET_E500_DOUBLE)
8442 {
8443 if (flag_finite_math_only && !flag_trapping_math)
8444 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8445 else
8446 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8447 }
8448 else
8449 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8450 emit_label (label);
8451 DONE;
8452 }")
8454 (define_expand "abstf2_internal"
8455 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8456 (match_operand:TF 1 "gpc_reg_operand" ""))
8457 (set (match_dup 3) (match_dup 5))
8458 (set (match_dup 5) (abs:DF (match_dup 5)))
8459 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8460 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8461 (label_ref (match_operand 2 "" ""))
8462 (pc)))
8463 (set (match_dup 6) (neg:DF (match_dup 6)))]
8464 "!TARGET_IEEEQUAD
8465 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8466 && TARGET_LONG_DOUBLE_128"
8467 "
8468 {
8469 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
8470 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
8471 operands[3] = gen_reg_rtx (DFmode);
8472 operands[4] = gen_reg_rtx (CCFPmode);
8473 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8474 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8475 }")
8476 \f
8477 ;; Reload helper functions used by rs6000_secondary_reload. The patterns all
8478 ;; must have 3 arguments, and scratch register constraint must be a single
8479 ;; constraint.
8481 ;; Reload patterns to support gpr load/store with misaligned mem.
8482 ;; and multiple gpr load/store at offset >= 0xfffc
8483 (define_expand "reload_<mode>_store"
8484 [(parallel [(match_operand 0 "memory_operand" "=m")
8485 (match_operand 1 "gpc_reg_operand" "r")
8486 (match_operand:GPR 2 "register_operand" "=&b")])]
8487 ""
8488 {
8489 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
8490 DONE;
8491 })
8493 (define_expand "reload_<mode>_load"
8494 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
8495 (match_operand 1 "memory_operand" "m")
8496 (match_operand:GPR 2 "register_operand" "=b")])]
8497 ""
8498 {
8499 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
8500 DONE;
8501 })
8503 \f
8504 ;; Power8 merge instructions to allow direct move to/from floating point
8505 ;; registers in 32-bit mode. We use TF mode to get two registers to move the
8506 ;; individual 32-bit parts across. Subreg doesn't work too well on the TF
8507 ;; value, since it is allocated in reload and not all of the flow information
8508 ;; is setup for it. We have two patterns to do the two moves between gprs and
8509 ;; fprs. There isn't a dependancy between the two, but we could potentially
8510 ;; schedule other instructions between the two instructions. TFmode is
8511 ;; currently limited to traditional FPR registers. If/when this is changed, we
8512 ;; will need to revist %L to make sure it works with VSX registers, or add an
8513 ;; %x version of %L.
8515 (define_insn "p8_fmrgow_<mode>"
8516 [(set (match_operand:FMOVE64X 0 "register_operand" "=d")
8517 (unspec:FMOVE64X [(match_operand:TF 1 "register_operand" "d")]
8518 UNSPEC_P8V_FMRGOW))]
8519 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8520 "fmrgow %0,%1,%L1"
8521 [(set_attr "type" "vecperm")])
8523 (define_insn "p8_mtvsrwz_1"
8524 [(set (match_operand:TF 0 "register_operand" "=d")
8525 (unspec:TF [(match_operand:SI 1 "register_operand" "r")]
8526 UNSPEC_P8V_MTVSRWZ))]
8527 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8528 "mtvsrwz %x0,%1"
8529 [(set_attr "type" "mftgpr")])
8531 (define_insn "p8_mtvsrwz_2"
8532 [(set (match_operand:TF 0 "register_operand" "+d")
8533 (unspec:TF [(match_dup 0)
8534 (match_operand:SI 1 "register_operand" "r")]
8535 UNSPEC_P8V_MTVSRWZ))]
8536 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8537 "mtvsrwz %L0,%1"
8538 [(set_attr "type" "mftgpr")])
8540 (define_insn_and_split "reload_fpr_from_gpr<mode>"
8541 [(set (match_operand:FMOVE64X 0 "register_operand" "=ws")
8542 (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")]
8543 UNSPEC_P8V_RELOAD_FROM_GPR))
8544 (clobber (match_operand:TF 2 "register_operand" "=d"))]
8545 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8546 "#"
8547 "&& reload_completed"
8548 [(const_int 0)]
8549 {
8550 rtx dest = operands[0];
8551 rtx src = operands[1];
8552 rtx tmp = operands[2];
8553 rtx gpr_hi_reg = gen_highpart (SImode, src);
8554 rtx gpr_lo_reg = gen_lowpart (SImode, src);
8556 emit_insn (gen_p8_mtvsrwz_1 (tmp, gpr_hi_reg));
8557 emit_insn (gen_p8_mtvsrwz_2 (tmp, gpr_lo_reg));
8558 emit_insn (gen_p8_fmrgow_<mode> (dest, tmp));
8559 DONE;
8560 }
8561 [(set_attr "length" "12")
8562 (set_attr "type" "three")])
8564 ;; Move 128 bit values from GPRs to VSX registers in 64-bit mode
8565 (define_insn "p8_mtvsrd_1"
8566 [(set (match_operand:TF 0 "register_operand" "=ws")
8567 (unspec:TF [(match_operand:DI 1 "register_operand" "r")]
8568 UNSPEC_P8V_MTVSRD))]
8569 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8570 "mtvsrd %0,%1"
8571 [(set_attr "type" "mftgpr")])
8573 (define_insn "p8_mtvsrd_2"
8574 [(set (match_operand:TF 0 "register_operand" "+ws")
8575 (unspec:TF [(match_dup 0)
8576 (match_operand:DI 1 "register_operand" "r")]
8577 UNSPEC_P8V_MTVSRD))]
8578 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8579 "mtvsrd %L0,%1"
8580 [(set_attr "type" "mftgpr")])
8582 (define_insn "p8_xxpermdi_<mode>"
8583 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
8584 (unspec:FMOVE128_GPR [(match_operand:TF 1 "register_operand" "ws")]
8585 UNSPEC_P8V_XXPERMDI))]
8586 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8587 "xxpermdi %x0,%1,%L1,0"
8588 [(set_attr "type" "vecperm")])
8590 (define_insn_and_split "reload_vsx_from_gpr<mode>"
8591 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
8592 (unspec:FMOVE128_GPR
8593 [(match_operand:FMOVE128_GPR 1 "register_operand" "r")]
8594 UNSPEC_P8V_RELOAD_FROM_GPR))
8595 (clobber (match_operand:TF 2 "register_operand" "=ws"))]
8596 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8597 "#"
8598 "&& reload_completed"
8599 [(const_int 0)]
8600 {
8601 rtx dest = operands[0];
8602 rtx src = operands[1];
8603 rtx tmp = operands[2];
8604 rtx gpr_hi_reg = gen_highpart (DImode, src);
8605 rtx gpr_lo_reg = gen_lowpart (DImode, src);
8607 emit_insn (gen_p8_mtvsrd_1 (tmp, gpr_hi_reg));
8608 emit_insn (gen_p8_mtvsrd_2 (tmp, gpr_lo_reg));
8609 emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp));
8610 }
8611 [(set_attr "length" "12")
8612 (set_attr "type" "three")])
8614 (define_split
8615 [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "")
8616 (match_operand:FMOVE128_GPR 1 "input_operand" ""))]
8617 "reload_completed
8618 && (int_reg_operand (operands[0], <MODE>mode)
8619 || int_reg_operand (operands[1], <MODE>mode))"
8620 [(pc)]
8621 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8623 ;; Move SFmode to a VSX from a GPR register. Because scalar floating point
8624 ;; type is stored internally as double precision in the VSX registers, we have
8625 ;; to convert it from the vector format.
8627 (define_insn_and_split "reload_vsx_from_gprsf"
8628 [(set (match_operand:SF 0 "register_operand" "=wa")
8629 (unspec:SF [(match_operand:SF 1 "register_operand" "r")]
8630 UNSPEC_P8V_RELOAD_FROM_GPR))
8631 (clobber (match_operand:DI 2 "register_operand" "=r"))]
8632 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8633 "#"
8634 "&& reload_completed"
8635 [(const_int 0)]
8636 {
8637 rtx op0 = operands[0];
8638 rtx op1 = operands[1];
8639 rtx op2 = operands[2];
8640 /* Also use the destination register to hold the unconverted DImode value.
8641 This is conceptually a separate value from OP0, so we use gen_rtx_REG
8642 rather than simplify_gen_subreg. */
8643 rtx op0_di = gen_rtx_REG (DImode, REGNO (op0));
8644 rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);
8646 /* Move SF value to upper 32-bits for xscvspdpn. */
8647 emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
8648 emit_move_insn (op0_di, op2);
8649 emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0_di));
8650 DONE;
8651 }
8652 [(set_attr "length" "8")
8653 (set_attr "type" "two")])
8655 ;; Move 128 bit values from VSX registers to GPRs in 64-bit mode by doing a
8656 ;; normal 64-bit move, followed by an xxpermdi to get the bottom 64-bit value,
8657 ;; and then doing a move of that.
8658 (define_insn "p8_mfvsrd_3_<mode>"
8659 [(set (match_operand:DF 0 "register_operand" "=r")
8660 (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
8661 UNSPEC_P8V_RELOAD_FROM_VSX))]
8662 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8663 "mfvsrd %0,%x1"
8664 [(set_attr "type" "mftgpr")])
8666 (define_insn_and_split "reload_gpr_from_vsx<mode>"
8667 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=r")
8668 (unspec:FMOVE128_GPR
8669 [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
8670 UNSPEC_P8V_RELOAD_FROM_VSX))
8671 (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
8672 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8673 "#"
8674 "&& reload_completed"
8675 [(const_int 0)]
8676 {
8677 rtx dest = operands[0];
8678 rtx src = operands[1];
8679 rtx tmp = operands[2];
8680 rtx gpr_hi_reg = gen_highpart (DFmode, dest);
8681 rtx gpr_lo_reg = gen_lowpart (DFmode, dest);
8683 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src));
8684 emit_insn (gen_vsx_xxpermdi_<mode> (tmp, src, src, GEN_INT (3)));
8685 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp));
8686 }
8687 [(set_attr "length" "12")
8688 (set_attr "type" "three")])
8690 ;; Move SFmode to a GPR from a VSX register. Because scalar floating point
8691 ;; type is stored internally as double precision, we have to convert it to the
8692 ;; vector format.
8694 (define_insn_and_split "reload_gpr_from_vsxsf"
8695 [(set (match_operand:SF 0 "register_operand" "=r")
8696 (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
8697 UNSPEC_P8V_RELOAD_FROM_VSX))
8698 (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
8699 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8700 "#"
8701 "&& reload_completed"
8702 [(const_int 0)]
8703 {
8704 rtx op0 = operands[0];
8705 rtx op1 = operands[1];
8706 rtx op2 = operands[2];
8707 rtx diop0 = simplify_gen_subreg (DImode, op0, SFmode, 0);
8709 emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));
8710 emit_insn (gen_p8_mfvsrd_4_disf (diop0, op2));
8711 emit_insn (gen_lshrdi3 (diop0, diop0, GEN_INT (32)));
8712 DONE;
8713 }
8714 [(set_attr "length" "12")
8715 (set_attr "type" "three")])
8717 (define_insn "p8_mfvsrd_4_disf"
8718 [(set (match_operand:DI 0 "register_operand" "=r")
8719 (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]
8720 UNSPEC_P8V_RELOAD_FROM_VSX))]
8721 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8722 "mfvsrd %0,%x1"
8723 [(set_attr "type" "mftgpr")])
8725 \f
8726 ;; Next come the multi-word integer load and store and the load and store
8727 ;; multiple insns.
8729 ;; List r->r after r->Y, otherwise reload will try to reload a
8730 ;; non-offsettable address by using r->r which won't make progress.
8731 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
8732 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
8733 (define_insn "*movdi_internal32"
8734 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r")
8735 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF"))]
8736 "! TARGET_POWERPC64
8737 && (gpc_reg_operand (operands[0], DImode)
8738 || gpc_reg_operand (operands[1], DImode))"
8739 "@
8740 #
8741 #
8742 #
8743 stfd%U0%X0 %1,%0
8744 lfd%U1%X1 %0,%1
8745 fmr %0,%1
8746 #"
8747 [(set_attr "type" "store,load,*,fpstore,fpload,fp,*")])
8749 (define_split
8750 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8751 (match_operand:DI 1 "const_int_operand" ""))]
8752 "! TARGET_POWERPC64 && reload_completed
8753 && gpr_or_gpr_p (operands[0], operands[1])
8754 && !direct_move_p (operands[0], operands[1])"
8755 [(set (match_dup 2) (match_dup 4))
8756 (set (match_dup 3) (match_dup 1))]
8757 "
8758 {
8759 HOST_WIDE_INT value = INTVAL (operands[1]);
8760 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8761 DImode);
8762 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8763 DImode);
8764 operands[4] = GEN_INT (value >> 32);
8765 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8766 }")
8768 (define_split
8769 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
8770 (match_operand:DIFD 1 "input_operand" ""))]
8771 "reload_completed && !TARGET_POWERPC64
8772 && gpr_or_gpr_p (operands[0], operands[1])
8773 && !direct_move_p (operands[0], operands[1])"
8774 [(pc)]
8775 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8777 (define_insn "*movdi_internal64"
8778 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wj,?*wi")
8779 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wj,r,O"))]
8780 "TARGET_POWERPC64
8781 && (gpc_reg_operand (operands[0], DImode)
8782 || gpc_reg_operand (operands[1], DImode))"
8783 "@
8784 std%U0%X0 %1,%0
8785 ld%U1%X1 %0,%1
8786 mr %0,%1
8787 li %0,%1
8788 lis %0,%v1
8789 #
8790 stfd%U0%X0 %1,%0
8791 lfd%U1%X1 %0,%1
8792 fmr %0,%1
8793 mf%1 %0
8794 mt%0 %1
8795 nop
8796 mftgpr %0,%1
8797 mffgpr %0,%1
8798 mfvsrd %0,%x1
8799 mtvsrd %x0,%1
8800 xxlxor %x0,%x0,%x0"
8801 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr,vecsimple")
8802 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4")])
8804 ;; Generate all one-bits and clear left or right.
8805 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8806 (define_split
8807 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8808 (match_operand:DI 1 "mask64_operand" ""))]
8809 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8810 [(set (match_dup 0) (const_int -1))
8811 (set (match_dup 0)
8812 (and:DI (rotate:DI (match_dup 0)
8813 (const_int 0))
8814 (match_dup 1)))]
8815 "")
8817 ;; Split a load of a large constant into the appropriate five-instruction
8818 ;; sequence. Handle anything in a constant number of insns.
8819 ;; When non-easy constants can go in the TOC, this should use
8820 ;; easy_fp_constant predicate.
8821 (define_split
8822 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8823 (match_operand:DI 1 "const_int_operand" ""))]
8824 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8825 [(set (match_dup 0) (match_dup 2))
8826 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8827 "
8828 {
8829 if (rs6000_emit_set_const (operands[0], operands[1]))
8830 DONE;
8831 else
8832 FAIL;
8833 }")
8835 (define_split
8836 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8837 (match_operand:DI 1 "const_scalar_int_operand" ""))]
8838 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8839 [(set (match_dup 0) (match_dup 2))
8840 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8841 "
8842 {
8843 if (rs6000_emit_set_const (operands[0], operands[1]))
8844 DONE;
8845 else
8846 FAIL;
8847 }")
8848 \f
8849 ;; TImode/PTImode is similar, except that we usually want to compute the
8850 ;; address into a register and use lsi/stsi (the exception is during reload).
8852 (define_insn "*mov<mode>_string"
8853 [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
8854 (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]
8855 "! TARGET_POWERPC64
8856 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
8857 && (gpc_reg_operand (operands[0], <MODE>mode)
8858 || gpc_reg_operand (operands[1], <MODE>mode))"
8859 "*
8860 {
8861 switch (which_alternative)
8862 {
8863 default:
8864 gcc_unreachable ();
8865 case 0:
8866 if (TARGET_STRING)
8867 return \"stswi %1,%P0,16\";
8868 case 1:
8869 return \"#\";
8870 case 2:
8871 /* If the address is not used in the output, we can use lsi. Otherwise,
8872 fall through to generating four loads. */
8873 if (TARGET_STRING
8874 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8875 return \"lswi %0,%P1,16\";
8876 /* ... fall through ... */
8877 case 3:
8878 case 4:
8879 case 5:
8880 return \"#\";
8881 }
8882 }"
8883 [(set_attr "type" "store,store,load,load,*,*")
8884 (set_attr "update" "yes")
8885 (set_attr "indexed" "yes")
8886 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
8887 (const_string "always")
8888 (const_string "conditional")))])
8890 (define_insn "*mov<mode>_ppc64"
8891 [(set (match_operand:TI2 0 "nonimmediate_operand" "=wQ,Y,r,r,r,r")
8892 (match_operand:TI2 1 "input_operand" "r,r,wQ,Y,r,n"))]
8893 "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (<MODE>mode)
8894 && (gpc_reg_operand (operands[0], <MODE>mode)
8895 || gpc_reg_operand (operands[1], <MODE>mode)))"
8896 {
8897 return rs6000_output_move_128bit (operands);
8898 }
8899 [(set_attr "type" "store,store,load,load,*,*")
8900 (set_attr "length" "8")])
8902 (define_split
8903 [(set (match_operand:TI2 0 "int_reg_operand" "")
8904 (match_operand:TI2 1 "const_scalar_int_operand" ""))]
8905 "TARGET_POWERPC64
8906 && (VECTOR_MEM_NONE_P (<MODE>mode)
8907 || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
8908 [(set (match_dup 2) (match_dup 4))
8909 (set (match_dup 3) (match_dup 5))]
8910 "
8911 {
8912 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8913 <MODE>mode);
8914 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8915 <MODE>mode);
8916 if (CONST_WIDE_INT_P (operands[1]))
8917 {
8918 operands[4] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 1));
8919 operands[5] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 0));
8920 }
8921 else if (CONST_INT_P (operands[1]))
8922 {
8923 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8924 operands[5] = operands[1];
8925 }
8926 else
8927 FAIL;
8928 }")
8930 (define_split
8931 [(set (match_operand:TI2 0 "nonimmediate_operand" "")
8932 (match_operand:TI2 1 "input_operand" ""))]
8933 "reload_completed
8934 && gpr_or_gpr_p (operands[0], operands[1])
8935 && !direct_move_p (operands[0], operands[1])
8936 && !quad_load_store_p (operands[0], operands[1])"
8937 [(pc)]
8938 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8939 \f
8940 (define_expand "load_multiple"
8941 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8942 (match_operand:SI 1 "" ""))
8943 (use (match_operand:SI 2 "" ""))])]
8944 "TARGET_STRING && !TARGET_POWERPC64"
8945 "
8946 {
8947 int regno;
8948 int count;
8949 rtx op1;
8950 int i;
8952 /* Support only loading a constant number of fixed-point registers from
8953 memory and only bother with this if more than two; the machine
8954 doesn't support more than eight. */
8955 if (GET_CODE (operands[2]) != CONST_INT
8956 || INTVAL (operands[2]) <= 2
8957 || INTVAL (operands[2]) > 8
8958 || GET_CODE (operands[1]) != MEM
8959 || GET_CODE (operands[0]) != REG
8960 || REGNO (operands[0]) >= 32)
8961 FAIL;
8963 count = INTVAL (operands[2]);
8964 regno = REGNO (operands[0]);
8966 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8967 op1 = replace_equiv_address (operands[1],
8968 force_reg (SImode, XEXP (operands[1], 0)));
8970 for (i = 0; i < count; i++)
8971 XVECEXP (operands[3], 0, i)
8972 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8973 adjust_address_nv (op1, SImode, i * 4));
8974 }")
8976 (define_insn "*ldmsi8"
8977 [(match_parallel 0 "load_multiple_operation"
8978 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8979 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8980 (set (match_operand:SI 3 "gpc_reg_operand" "")
8981 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8982 (set (match_operand:SI 4 "gpc_reg_operand" "")
8983 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8984 (set (match_operand:SI 5 "gpc_reg_operand" "")
8985 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8986 (set (match_operand:SI 6 "gpc_reg_operand" "")
8987 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8988 (set (match_operand:SI 7 "gpc_reg_operand" "")
8989 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8990 (set (match_operand:SI 8 "gpc_reg_operand" "")
8991 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8992 (set (match_operand:SI 9 "gpc_reg_operand" "")
8993 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8994 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8995 "*
8996 { return rs6000_output_load_multiple (operands); }"
8997 [(set_attr "type" "load")
8998 (set_attr "update" "yes")
8999 (set_attr "indexed" "yes")
9000 (set_attr "length" "32")])
9002 (define_insn "*ldmsi7"
9003 [(match_parallel 0 "load_multiple_operation"
9004 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9005 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9006 (set (match_operand:SI 3 "gpc_reg_operand" "")
9007 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9008 (set (match_operand:SI 4 "gpc_reg_operand" "")
9009 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9010 (set (match_operand:SI 5 "gpc_reg_operand" "")
9011 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9012 (set (match_operand:SI 6 "gpc_reg_operand" "")
9013 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9014 (set (match_operand:SI 7 "gpc_reg_operand" "")
9015 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9016 (set (match_operand:SI 8 "gpc_reg_operand" "")
9017 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9018 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9019 "*
9020 { return rs6000_output_load_multiple (operands); }"
9021 [(set_attr "type" "load")
9022 (set_attr "update" "yes")
9023 (set_attr "indexed" "yes")
9024 (set_attr "length" "32")])
9026 (define_insn "*ldmsi6"
9027 [(match_parallel 0 "load_multiple_operation"
9028 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9029 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9030 (set (match_operand:SI 3 "gpc_reg_operand" "")
9031 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9032 (set (match_operand:SI 4 "gpc_reg_operand" "")
9033 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9034 (set (match_operand:SI 5 "gpc_reg_operand" "")
9035 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9036 (set (match_operand:SI 6 "gpc_reg_operand" "")
9037 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9038 (set (match_operand:SI 7 "gpc_reg_operand" "")
9039 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9040 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9041 "*
9042 { return rs6000_output_load_multiple (operands); }"
9043 [(set_attr "type" "load")
9044 (set_attr "update" "yes")
9045 (set_attr "indexed" "yes")
9046 (set_attr "length" "32")])
9048 (define_insn "*ldmsi5"
9049 [(match_parallel 0 "load_multiple_operation"
9050 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9051 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9052 (set (match_operand:SI 3 "gpc_reg_operand" "")
9053 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9054 (set (match_operand:SI 4 "gpc_reg_operand" "")
9055 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9056 (set (match_operand:SI 5 "gpc_reg_operand" "")
9057 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9058 (set (match_operand:SI 6 "gpc_reg_operand" "")
9059 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9060 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9061 "*
9062 { return rs6000_output_load_multiple (operands); }"
9063 [(set_attr "type" "load")
9064 (set_attr "update" "yes")
9065 (set_attr "indexed" "yes")
9066 (set_attr "length" "32")])
9068 (define_insn "*ldmsi4"
9069 [(match_parallel 0 "load_multiple_operation"
9070 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9071 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9072 (set (match_operand:SI 3 "gpc_reg_operand" "")
9073 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9074 (set (match_operand:SI 4 "gpc_reg_operand" "")
9075 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9076 (set (match_operand:SI 5 "gpc_reg_operand" "")
9077 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9078 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9079 "*
9080 { return rs6000_output_load_multiple (operands); }"
9081 [(set_attr "type" "load")
9082 (set_attr "update" "yes")
9083 (set_attr "indexed" "yes")
9084 (set_attr "length" "32")])
9086 (define_insn "*ldmsi3"
9087 [(match_parallel 0 "load_multiple_operation"
9088 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9089 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9090 (set (match_operand:SI 3 "gpc_reg_operand" "")
9091 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9092 (set (match_operand:SI 4 "gpc_reg_operand" "")
9093 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9094 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9095 "*
9096 { return rs6000_output_load_multiple (operands); }"
9097 [(set_attr "type" "load")
9098 (set_attr "update" "yes")
9099 (set_attr "indexed" "yes")
9100 (set_attr "length" "32")])
9102 (define_expand "store_multiple"
9103 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9104 (match_operand:SI 1 "" ""))
9105 (clobber (scratch:SI))
9106 (use (match_operand:SI 2 "" ""))])]
9107 "TARGET_STRING && !TARGET_POWERPC64"
9108 "
9109 {
9110 int regno;
9111 int count;
9112 rtx to;
9113 rtx op0;
9114 int i;
9116 /* Support only storing a constant number of fixed-point registers to
9117 memory and only bother with this if more than two; the machine
9118 doesn't support more than eight. */
9119 if (GET_CODE (operands[2]) != CONST_INT
9120 || INTVAL (operands[2]) <= 2
9121 || INTVAL (operands[2]) > 8
9122 || GET_CODE (operands[0]) != MEM
9123 || GET_CODE (operands[1]) != REG
9124 || REGNO (operands[1]) >= 32)
9125 FAIL;
9127 count = INTVAL (operands[2]);
9128 regno = REGNO (operands[1]);
9130 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9131 to = force_reg (SImode, XEXP (operands[0], 0));
9132 op0 = replace_equiv_address (operands[0], to);
9134 XVECEXP (operands[3], 0, 0)
9135 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9136 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9137 gen_rtx_SCRATCH (SImode));
9139 for (i = 1; i < count; i++)
9140 XVECEXP (operands[3], 0, i + 1)
9141 = gen_rtx_SET (VOIDmode,
9142 adjust_address_nv (op0, SImode, i * 4),
9143 gen_rtx_REG (SImode, regno + i));
9144 }")
9146 (define_insn "*stmsi8"
9147 [(match_parallel 0 "store_multiple_operation"
9148 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9149 (match_operand:SI 2 "gpc_reg_operand" "r"))
9150 (clobber (match_scratch:SI 3 "=X"))
9151 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9152 (match_operand:SI 4 "gpc_reg_operand" "r"))
9153 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9154 (match_operand:SI 5 "gpc_reg_operand" "r"))
9155 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9156 (match_operand:SI 6 "gpc_reg_operand" "r"))
9157 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9158 (match_operand:SI 7 "gpc_reg_operand" "r"))
9159 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9160 (match_operand:SI 8 "gpc_reg_operand" "r"))
9161 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9162 (match_operand:SI 9 "gpc_reg_operand" "r"))
9163 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9164 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9165 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
9166 "stswi %2,%1,%O0"
9167 [(set_attr "type" "store")
9168 (set_attr "update" "yes")
9169 (set_attr "indexed" "yes")
9170 (set_attr "cell_micro" "always")])
9172 (define_insn "*stmsi7"
9173 [(match_parallel 0 "store_multiple_operation"
9174 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9175 (match_operand:SI 2 "gpc_reg_operand" "r"))
9176 (clobber (match_scratch:SI 3 "=X"))
9177 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9178 (match_operand:SI 4 "gpc_reg_operand" "r"))
9179 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9180 (match_operand:SI 5 "gpc_reg_operand" "r"))
9181 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9182 (match_operand:SI 6 "gpc_reg_operand" "r"))
9183 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9184 (match_operand:SI 7 "gpc_reg_operand" "r"))
9185 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9186 (match_operand:SI 8 "gpc_reg_operand" "r"))
9187 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9188 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9189 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9190 "stswi %2,%1,%O0"
9191 [(set_attr "type" "store")
9192 (set_attr "update" "yes")
9193 (set_attr "indexed" "yes")
9194 (set_attr "cell_micro" "always")])
9196 (define_insn "*stmsi6"
9197 [(match_parallel 0 "store_multiple_operation"
9198 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9199 (match_operand:SI 2 "gpc_reg_operand" "r"))
9200 (clobber (match_scratch:SI 3 "=X"))
9201 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9202 (match_operand:SI 4 "gpc_reg_operand" "r"))
9203 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9204 (match_operand:SI 5 "gpc_reg_operand" "r"))
9205 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9206 (match_operand:SI 6 "gpc_reg_operand" "r"))
9207 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9208 (match_operand:SI 7 "gpc_reg_operand" "r"))
9209 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9210 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9211 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9212 "stswi %2,%1,%O0"
9213 [(set_attr "type" "store")
9214 (set_attr "update" "yes")
9215 (set_attr "indexed" "yes")
9216 (set_attr "cell_micro" "always")])
9218 (define_insn "*stmsi5"
9219 [(match_parallel 0 "store_multiple_operation"
9220 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9221 (match_operand:SI 2 "gpc_reg_operand" "r"))
9222 (clobber (match_scratch:SI 3 "=X"))
9223 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9224 (match_operand:SI 4 "gpc_reg_operand" "r"))
9225 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9226 (match_operand:SI 5 "gpc_reg_operand" "r"))
9227 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9228 (match_operand:SI 6 "gpc_reg_operand" "r"))
9229 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9230 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9231 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9232 "stswi %2,%1,%O0"
9233 [(set_attr "type" "store")
9234 (set_attr "update" "yes")
9235 (set_attr "indexed" "yes")
9236 (set_attr "cell_micro" "always")])
9238 (define_insn "*stmsi4"
9239 [(match_parallel 0 "store_multiple_operation"
9240 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9241 (match_operand:SI 2 "gpc_reg_operand" "r"))
9242 (clobber (match_scratch:SI 3 "=X"))
9243 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9244 (match_operand:SI 4 "gpc_reg_operand" "r"))
9245 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9246 (match_operand:SI 5 "gpc_reg_operand" "r"))
9247 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9248 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9249 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9250 "stswi %2,%1,%O0"
9251 [(set_attr "type" "store")
9252 (set_attr "update" "yes")
9253 (set_attr "indexed" "yes")
9254 (set_attr "cell_micro" "always")])
9256 (define_insn "*stmsi3"
9257 [(match_parallel 0 "store_multiple_operation"
9258 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9259 (match_operand:SI 2 "gpc_reg_operand" "r"))
9260 (clobber (match_scratch:SI 3 "=X"))
9261 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9262 (match_operand:SI 4 "gpc_reg_operand" "r"))
9263 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9264 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9265 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9266 "stswi %2,%1,%O0"
9267 [(set_attr "type" "store")
9268 (set_attr "update" "yes")
9269 (set_attr "indexed" "yes")
9270 (set_attr "cell_micro" "always")])
9271 \f
9272 (define_expand "setmemsi"
9273 [(parallel [(set (match_operand:BLK 0 "" "")
9274 (match_operand 2 "const_int_operand" ""))
9275 (use (match_operand:SI 1 "" ""))
9276 (use (match_operand:SI 3 "" ""))])]
9277 ""
9278 "
9279 {
9280 /* If value to set is not zero, use the library routine. */
9281 if (operands[2] != const0_rtx)
9282 FAIL;
9284 if (expand_block_clear (operands))
9285 DONE;
9286 else
9287 FAIL;
9288 }")
9290 ;; String/block move insn.
9291 ;; Argument 0 is the destination
9292 ;; Argument 1 is the source
9293 ;; Argument 2 is the length
9294 ;; Argument 3 is the alignment
9296 (define_expand "movmemsi"
9297 [(parallel [(set (match_operand:BLK 0 "" "")
9298 (match_operand:BLK 1 "" ""))
9299 (use (match_operand:SI 2 "" ""))
9300 (use (match_operand:SI 3 "" ""))])]
9301 ""
9302 "
9303 {
9304 if (expand_block_move (operands))
9305 DONE;
9306 else
9307 FAIL;
9308 }")
9310 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9311 ;; register allocator doesn't have a clue about allocating 8 word registers.
9312 ;; rD/rS = r5 is preferred, efficient form.
9313 (define_expand "movmemsi_8reg"
9314 [(parallel [(set (match_operand 0 "" "")
9315 (match_operand 1 "" ""))
9316 (use (match_operand 2 "" ""))
9317 (use (match_operand 3 "" ""))
9318 (clobber (reg:SI 5))
9319 (clobber (reg:SI 6))
9320 (clobber (reg:SI 7))
9321 (clobber (reg:SI 8))
9322 (clobber (reg:SI 9))
9323 (clobber (reg:SI 10))
9324 (clobber (reg:SI 11))
9325 (clobber (reg:SI 12))
9326 (clobber (match_scratch:SI 4 ""))])]
9327 "TARGET_STRING"
9328 "")
9330 (define_insn ""
9331 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9332 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9333 (use (match_operand:SI 2 "immediate_operand" "i"))
9334 (use (match_operand:SI 3 "immediate_operand" "i"))
9335 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9336 (clobber (reg:SI 6))
9337 (clobber (reg:SI 7))
9338 (clobber (reg:SI 8))
9339 (clobber (reg:SI 9))
9340 (clobber (reg:SI 10))
9341 (clobber (reg:SI 11))
9342 (clobber (reg:SI 12))
9343 (clobber (match_scratch:SI 5 "=X"))]
9344 "TARGET_STRING
9345 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9346 || INTVAL (operands[2]) == 0)
9347 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9348 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9349 && REGNO (operands[4]) == 5"
9350 "lswi %4,%1,%2\;stswi %4,%0,%2"
9351 [(set_attr "type" "store")
9352 (set_attr "update" "yes")
9353 (set_attr "indexed" "yes")
9354 (set_attr "cell_micro" "always")
9355 (set_attr "length" "8")])
9357 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9358 ;; register allocator doesn't have a clue about allocating 6 word registers.
9359 ;; rD/rS = r5 is preferred, efficient form.
9360 (define_expand "movmemsi_6reg"
9361 [(parallel [(set (match_operand 0 "" "")
9362 (match_operand 1 "" ""))
9363 (use (match_operand 2 "" ""))
9364 (use (match_operand 3 "" ""))
9365 (clobber (reg:SI 5))
9366 (clobber (reg:SI 6))
9367 (clobber (reg:SI 7))
9368 (clobber (reg:SI 8))
9369 (clobber (reg:SI 9))
9370 (clobber (reg:SI 10))
9371 (clobber (match_scratch:SI 4 ""))])]
9372 "TARGET_STRING"
9373 "")
9375 (define_insn ""
9376 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9377 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9378 (use (match_operand:SI 2 "immediate_operand" "i"))
9379 (use (match_operand:SI 3 "immediate_operand" "i"))
9380 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9381 (clobber (reg:SI 6))
9382 (clobber (reg:SI 7))
9383 (clobber (reg:SI 8))
9384 (clobber (reg:SI 9))
9385 (clobber (reg:SI 10))
9386 (clobber (match_scratch:SI 5 "=X"))]
9387 "TARGET_STRING
9388 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9389 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9390 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9391 && REGNO (operands[4]) == 5"
9392 "lswi %4,%1,%2\;stswi %4,%0,%2"
9393 [(set_attr "type" "store")
9394 (set_attr "update" "yes")
9395 (set_attr "indexed" "yes")
9396 (set_attr "cell_micro" "always")
9397 (set_attr "length" "8")])
9399 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9400 ;; problems with TImode.
9401 ;; rD/rS = r5 is preferred, efficient form.
9402 (define_expand "movmemsi_4reg"
9403 [(parallel [(set (match_operand 0 "" "")
9404 (match_operand 1 "" ""))
9405 (use (match_operand 2 "" ""))
9406 (use (match_operand 3 "" ""))
9407 (clobber (reg:SI 5))
9408 (clobber (reg:SI 6))
9409 (clobber (reg:SI 7))
9410 (clobber (reg:SI 8))
9411 (clobber (match_scratch:SI 4 ""))])]
9412 "TARGET_STRING"
9413 "")
9415 (define_insn ""
9416 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9417 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9418 (use (match_operand:SI 2 "immediate_operand" "i"))
9419 (use (match_operand:SI 3 "immediate_operand" "i"))
9420 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9421 (clobber (reg:SI 6))
9422 (clobber (reg:SI 7))
9423 (clobber (reg:SI 8))
9424 (clobber (match_scratch:SI 5 "=X"))]
9425 "TARGET_STRING
9426 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9427 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9428 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9429 && REGNO (operands[4]) == 5"
9430 "lswi %4,%1,%2\;stswi %4,%0,%2"
9431 [(set_attr "type" "store")
9432 (set_attr "update" "yes")
9433 (set_attr "indexed" "yes")
9434 (set_attr "cell_micro" "always")
9435 (set_attr "length" "8")])
9437 ;; Move up to 8 bytes at a time.
9438 (define_expand "movmemsi_2reg"
9439 [(parallel [(set (match_operand 0 "" "")
9440 (match_operand 1 "" ""))
9441 (use (match_operand 2 "" ""))
9442 (use (match_operand 3 "" ""))
9443 (clobber (match_scratch:DI 4 ""))
9444 (clobber (match_scratch:SI 5 ""))])]
9445 "TARGET_STRING && ! TARGET_POWERPC64"
9446 "")
9448 (define_insn ""
9449 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9450 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9451 (use (match_operand:SI 2 "immediate_operand" "i"))
9452 (use (match_operand:SI 3 "immediate_operand" "i"))
9453 (clobber (match_scratch:DI 4 "=&r"))
9454 (clobber (match_scratch:SI 5 "=X"))]
9455 "TARGET_STRING && ! TARGET_POWERPC64
9456 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9457 "lswi %4,%1,%2\;stswi %4,%0,%2"
9458 [(set_attr "type" "store")
9459 (set_attr "update" "yes")
9460 (set_attr "indexed" "yes")
9461 (set_attr "cell_micro" "always")
9462 (set_attr "length" "8")])
9464 ;; Move up to 4 bytes at a time.
9465 (define_expand "movmemsi_1reg"
9466 [(parallel [(set (match_operand 0 "" "")
9467 (match_operand 1 "" ""))
9468 (use (match_operand 2 "" ""))
9469 (use (match_operand 3 "" ""))
9470 (clobber (match_scratch:SI 4 ""))
9471 (clobber (match_scratch:SI 5 ""))])]
9472 "TARGET_STRING"
9473 "")
9475 (define_insn ""
9476 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9477 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9478 (use (match_operand:SI 2 "immediate_operand" "i"))
9479 (use (match_operand:SI 3 "immediate_operand" "i"))
9480 (clobber (match_scratch:SI 4 "=&r"))
9481 (clobber (match_scratch:SI 5 "=X"))]
9482 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9483 "lswi %4,%1,%2\;stswi %4,%0,%2"
9484 [(set_attr "type" "store")
9485 (set_attr "update" "yes")
9486 (set_attr "indexed" "yes")
9487 (set_attr "cell_micro" "always")
9488 (set_attr "length" "8")])
9489 \f
9490 ;; Define insns that do load or store with update. Some of these we can
9491 ;; get by using pre-decrement or pre-increment, but the hardware can also
9492 ;; do cases where the increment is not the size of the object.
9493 ;;
9494 ;; In all these cases, we use operands 0 and 1 for the register being
9495 ;; incremented because those are the operands that local-alloc will
9496 ;; tie and these are the pair most likely to be tieable (and the ones
9497 ;; that will benefit the most).
9499 (define_insn "*movdi_update1"
9500 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9501 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9502 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9503 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9504 (plus:DI (match_dup 1) (match_dup 2)))]
9505 "TARGET_POWERPC64 && TARGET_UPDATE
9506 && (!avoiding_indexed_address_p (DImode)
9507 || !gpc_reg_operand (operands[2], DImode))"
9508 "@
9509 ldux %3,%0,%2
9510 ldu %3,%2(%0)"
9511 [(set_attr "type" "load")
9512 (set_attr "update" "yes")
9513 (set_attr "indexed" "yes,no")])
9515 (define_insn "movdi_<mode>_update"
9516 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9517 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9518 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9519 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9520 (plus:P (match_dup 1) (match_dup 2)))]
9521 "TARGET_POWERPC64 && TARGET_UPDATE
9522 && (!avoiding_indexed_address_p (Pmode)
9523 || !gpc_reg_operand (operands[2], Pmode)
9524 || (REG_P (operands[0])
9525 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9526 "@
9527 stdux %3,%0,%2
9528 stdu %3,%2(%0)"
9529 [(set_attr "type" "store")
9530 (set_attr "update" "yes")
9531 (set_attr "indexed" "yes,no")])
9533 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
9534 ;; needed for stack allocation, even if the user passes -mno-update.
9535 (define_insn "movdi_<mode>_update_stack"
9536 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9537 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9538 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9539 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9540 (plus:P (match_dup 1) (match_dup 2)))]
9541 "TARGET_POWERPC64"
9542 "@
9543 stdux %3,%0,%2
9544 stdu %3,%2(%0)"
9545 [(set_attr "type" "store")
9546 (set_attr "update" "yes")
9547 (set_attr "indexed" "yes,no")])
9549 (define_insn "*movsi_update1"
9550 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9551 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9552 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9553 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9554 (plus:SI (match_dup 1) (match_dup 2)))]
9555 "TARGET_UPDATE
9556 && (!avoiding_indexed_address_p (SImode)
9557 || !gpc_reg_operand (operands[2], SImode))"
9558 "@
9559 lwzux %3,%0,%2
9560 lwzu %3,%2(%0)"
9561 [(set_attr "type" "load")
9562 (set_attr "update" "yes")
9563 (set_attr "indexed" "yes,no")])
9565 (define_insn "*movsi_update2"
9566 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9567 (sign_extend:DI
9568 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9569 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9570 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9571 (plus:DI (match_dup 1) (match_dup 2)))]
9572 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
9573 && !avoiding_indexed_address_p (DImode)"
9574 "lwaux %3,%0,%2"
9575 [(set_attr "type" "load")
9576 (set_attr "sign_extend" "yes")
9577 (set_attr "update" "yes")
9578 (set_attr "indexed" "yes")])
9580 (define_insn "movsi_update"
9581 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9582 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9583 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9584 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9585 (plus:SI (match_dup 1) (match_dup 2)))]
9586 "TARGET_UPDATE
9587 && (!avoiding_indexed_address_p (SImode)
9588 || !gpc_reg_operand (operands[2], SImode)
9589 || (REG_P (operands[0])
9590 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9591 "@
9592 stwux %3,%0,%2
9593 stwu %3,%2(%0)"
9594 [(set_attr "type" "store")
9595 (set_attr "update" "yes")
9596 (set_attr "indexed" "yes,no")])
9598 ;; This is an unconditional pattern; needed for stack allocation, even
9599 ;; if the user passes -mno-update.
9600 (define_insn "movsi_update_stack"
9601 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9602 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9603 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9604 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9605 (plus:SI (match_dup 1) (match_dup 2)))]
9606 ""
9607 "@
9608 stwux %3,%0,%2
9609 stwu %3,%2(%0)"
9610 [(set_attr "type" "store")
9611 (set_attr "update" "yes")
9612 (set_attr "indexed" "yes,no")])
9614 (define_insn "*movhi_update1"
9615 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9616 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9617 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9618 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9619 (plus:SI (match_dup 1) (match_dup 2)))]
9620 "TARGET_UPDATE
9621 && (!avoiding_indexed_address_p (SImode)
9622 || !gpc_reg_operand (operands[2], SImode))"
9623 "@
9624 lhzux %3,%0,%2
9625 lhzu %3,%2(%0)"
9626 [(set_attr "type" "load")
9627 (set_attr "update" "yes")
9628 (set_attr "indexed" "yes,no")])
9630 (define_insn "*movhi_update2"
9631 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9632 (zero_extend:SI
9633 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9634 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9635 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9636 (plus:SI (match_dup 1) (match_dup 2)))]
9637 "TARGET_UPDATE
9638 && (!avoiding_indexed_address_p (SImode)
9639 || !gpc_reg_operand (operands[2], SImode))"
9640 "@
9641 lhzux %3,%0,%2
9642 lhzu %3,%2(%0)"
9643 [(set_attr "type" "load")
9644 (set_attr "update" "yes")
9645 (set_attr "indexed" "yes,no")])
9647 (define_insn "*movhi_update3"
9648 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9649 (sign_extend:SI
9650 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9651 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9652 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9653 (plus:SI (match_dup 1) (match_dup 2)))]
9654 "TARGET_UPDATE && rs6000_gen_cell_microcode
9655 && (!avoiding_indexed_address_p (SImode)
9656 || !gpc_reg_operand (operands[2], SImode))"
9657 "@
9658 lhaux %3,%0,%2
9659 lhau %3,%2(%0)"
9660 [(set_attr "type" "load")
9661 (set_attr "sign_extend" "yes")
9662 (set_attr "update" "yes")
9663 (set_attr "indexed" "yes,no")])
9665 (define_insn "*movhi_update4"
9666 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9667 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9668 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9669 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9670 (plus:SI (match_dup 1) (match_dup 2)))]
9671 "TARGET_UPDATE
9672 && (!avoiding_indexed_address_p (SImode)
9673 || !gpc_reg_operand (operands[2], SImode))"
9674 "@
9675 sthux %3,%0,%2
9676 sthu %3,%2(%0)"
9677 [(set_attr "type" "store")
9678 (set_attr "update" "yes")
9679 (set_attr "indexed" "yes,no")])
9681 (define_insn "*movqi_update1"
9682 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9683 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9684 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9685 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9686 (plus:SI (match_dup 1) (match_dup 2)))]
9687 "TARGET_UPDATE
9688 && (!avoiding_indexed_address_p (SImode)
9689 || !gpc_reg_operand (operands[2], SImode))"
9690 "@
9691 lbzux %3,%0,%2
9692 lbzu %3,%2(%0)"
9693 [(set_attr "type" "load")
9694 (set_attr "update" "yes")
9695 (set_attr "indexed" "yes,no")])
9697 (define_insn "*movqi_update2"
9698 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9699 (zero_extend:SI
9700 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9701 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9702 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9703 (plus:SI (match_dup 1) (match_dup 2)))]
9704 "TARGET_UPDATE
9705 && (!avoiding_indexed_address_p (SImode)
9706 || !gpc_reg_operand (operands[2], SImode))"
9707 "@
9708 lbzux %3,%0,%2
9709 lbzu %3,%2(%0)"
9710 [(set_attr "type" "load")
9711 (set_attr "update" "yes")
9712 (set_attr "indexed" "yes,no")])
9714 (define_insn "*movqi_update3"
9715 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9716 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9717 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9718 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9719 (plus:SI (match_dup 1) (match_dup 2)))]
9720 "TARGET_UPDATE
9721 && (!avoiding_indexed_address_p (SImode)
9722 || !gpc_reg_operand (operands[2], SImode))"
9723 "@
9724 stbux %3,%0,%2
9725 stbu %3,%2(%0)"
9726 [(set_attr "type" "store")
9727 (set_attr "update" "yes")
9728 (set_attr "indexed" "yes,no")])
9730 (define_insn "*movsf_update1"
9731 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9732 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9733 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9734 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9735 (plus:SI (match_dup 1) (match_dup 2)))]
9736 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9737 && (!avoiding_indexed_address_p (SImode)
9738 || !gpc_reg_operand (operands[2], SImode))"
9739 "@
9740 lfsux %3,%0,%2
9741 lfsu %3,%2(%0)"
9742 [(set_attr "type" "fpload")
9743 (set_attr "update" "yes")
9744 (set_attr "indexed" "yes,no")])
9746 (define_insn "*movsf_update2"
9747 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9748 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9749 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9750 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9751 (plus:SI (match_dup 1) (match_dup 2)))]
9752 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9753 && (!avoiding_indexed_address_p (SImode)
9754 || !gpc_reg_operand (operands[2], SImode))"
9755 "@
9756 stfsux %3,%0,%2
9757 stfsu %3,%2(%0)"
9758 [(set_attr "type" "fpstore")
9759 (set_attr "update" "yes")
9760 (set_attr "indexed" "yes,no")])
9762 (define_insn "*movsf_update3"
9763 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9764 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9765 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9766 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9767 (plus:SI (match_dup 1) (match_dup 2)))]
9768 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9769 && (!avoiding_indexed_address_p (SImode)
9770 || !gpc_reg_operand (operands[2], SImode))"
9771 "@
9772 lwzux %3,%0,%2
9773 lwzu %3,%2(%0)"
9774 [(set_attr "type" "load")
9775 (set_attr "update" "yes")
9776 (set_attr "indexed" "yes,no")])
9778 (define_insn "*movsf_update4"
9779 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9780 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9781 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9782 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9783 (plus:SI (match_dup 1) (match_dup 2)))]
9784 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9785 && (!avoiding_indexed_address_p (SImode)
9786 || !gpc_reg_operand (operands[2], SImode))"
9787 "@
9788 stwux %3,%0,%2
9789 stwu %3,%2(%0)"
9790 [(set_attr "type" "store")
9791 (set_attr "update" "yes")
9792 (set_attr "indexed" "yes,no")])
9794 (define_insn "*movdf_update1"
9795 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
9796 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9797 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9798 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9799 (plus:SI (match_dup 1) (match_dup 2)))]
9800 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9801 && (!avoiding_indexed_address_p (SImode)
9802 || !gpc_reg_operand (operands[2], SImode))"
9803 "@
9804 lfdux %3,%0,%2
9805 lfdu %3,%2(%0)"
9806 [(set_attr "type" "fpload")
9807 (set_attr "update" "yes")
9808 (set_attr "indexed" "yes,no")])
9810 (define_insn "*movdf_update2"
9811 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9812 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9813 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
9814 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9815 (plus:SI (match_dup 1) (match_dup 2)))]
9816 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9817 && (!avoiding_indexed_address_p (SImode)
9818 || !gpc_reg_operand (operands[2], SImode))"
9819 "@
9820 stfdux %3,%0,%2
9821 stfdu %3,%2(%0)"
9822 [(set_attr "type" "fpstore")
9823 (set_attr "update" "yes")
9824 (set_attr "indexed" "yes,no")])
9827 ;; After inserting conditional returns we can sometimes have
9828 ;; unnecessary register moves. Unfortunately we cannot have a
9829 ;; modeless peephole here, because some single SImode sets have early
9830 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9831 ;; sequences, using get_attr_length here will smash the operands
9832 ;; array. Neither is there an early_cobbler_p predicate.
9833 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
9834 (define_peephole2
9835 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9836 (match_operand:DF 1 "any_operand" ""))
9837 (set (match_operand:DF 2 "gpc_reg_operand" "")
9838 (match_dup 0))]
9839 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
9840 && peep2_reg_dead_p (2, operands[0])"
9841 [(set (match_dup 2) (match_dup 1))])
9843 (define_peephole2
9844 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9845 (match_operand:SF 1 "any_operand" ""))
9846 (set (match_operand:SF 2 "gpc_reg_operand" "")
9847 (match_dup 0))]
9848 "peep2_reg_dead_p (2, operands[0])"
9849 [(set (match_dup 2) (match_dup 1))])
9851 \f
9852 ;; TLS support.
9854 ;; Mode attributes for different ABIs.
9855 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
9856 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
9857 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
9858 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
9860 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
9861 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9862 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9863 (match_operand 4 "" "g")))
9864 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9865 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9866 UNSPEC_TLSGD)
9867 (clobber (reg:SI LR_REGNO))]
9868 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
9869 {
9870 if (TARGET_CMODEL != CMODEL_SMALL)
9871 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
9872 "bl %z3\;nop";
9873 else
9874 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
9875 }
9876 "&& TARGET_TLS_MARKERS"
9877 [(set (match_dup 0)
9878 (unspec:TLSmode [(match_dup 1)
9879 (match_dup 2)]
9880 UNSPEC_TLSGD))
9881 (parallel [(set (match_dup 0)
9882 (call (mem:TLSmode (match_dup 3))
9883 (match_dup 4)))
9884 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9885 (clobber (reg:SI LR_REGNO))])]
9886 ""
9887 [(set_attr "type" "two")
9888 (set (attr "length")
9889 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9890 (const_int 16)
9891 (const_int 12)))])
9893 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
9894 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9895 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9896 (match_operand 4 "" "g")))
9897 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9898 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9899 UNSPEC_TLSGD)
9900 (clobber (reg:SI LR_REGNO))]
9901 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
9902 {
9903 if (flag_pic)
9904 {
9905 if (TARGET_SECURE_PLT && flag_pic == 2)
9906 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
9907 else
9908 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
9909 }
9910 else
9911 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
9912 }
9913 "&& TARGET_TLS_MARKERS"
9914 [(set (match_dup 0)
9915 (unspec:TLSmode [(match_dup 1)
9916 (match_dup 2)]
9917 UNSPEC_TLSGD))
9918 (parallel [(set (match_dup 0)
9919 (call (mem:TLSmode (match_dup 3))
9920 (match_dup 4)))
9921 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9922 (clobber (reg:SI LR_REGNO))])]
9923 ""
9924 [(set_attr "type" "two")
9925 (set_attr "length" "8")])
9927 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
9928 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9929 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9930 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9931 UNSPEC_TLSGD))]
9932 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
9933 "addi %0,%1,%2@got@tlsgd"
9934 "&& TARGET_CMODEL != CMODEL_SMALL"
9935 [(set (match_dup 3)
9936 (high:TLSmode
9937 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
9938 (set (match_dup 0)
9939 (lo_sum:TLSmode (match_dup 3)
9940 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))]
9941 "
9942 {
9943 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9944 }"
9945 [(set (attr "length")
9946 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9947 (const_int 8)
9948 (const_int 4)))])
9950 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
9951 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9952 (high:TLSmode
9953 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9954 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9955 UNSPEC_TLSGD)))]
9956 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9957 "addis %0,%1,%2@got@tlsgd@ha"
9958 [(set_attr "length" "4")])
9960 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
9961 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9962 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9963 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
9964 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9965 UNSPEC_TLSGD)))]
9966 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9967 "addi %0,%1,%2@got@tlsgd@l"
9968 [(set_attr "length" "4")])
9970 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
9971 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9972 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9973 (match_operand 2 "" "g")))
9974 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9975 UNSPEC_TLSGD)
9976 (clobber (reg:SI LR_REGNO))]
9977 "HAVE_AS_TLS && TARGET_TLS_MARKERS
9978 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
9979 "bl %z1(%3@tlsgd)\;nop"
9980 [(set_attr "type" "branch")
9981 (set_attr "length" "8")])
9983 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
9984 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9985 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9986 (match_operand 2 "" "g")))
9987 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9988 UNSPEC_TLSGD)
9989 (clobber (reg:SI LR_REGNO))]
9990 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
9991 {
9992 if (flag_pic)
9993 {
9994 if (TARGET_SECURE_PLT && flag_pic == 2)
9995 return "bl %z1+32768(%3@tlsgd)@plt";
9996 return "bl %z1(%3@tlsgd)@plt";
9997 }
9998 return "bl %z1(%3@tlsgd)";
9999 }
10000 [(set_attr "type" "branch")
10001 (set_attr "length" "4")])
10003 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
10004 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10005 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10006 (match_operand 3 "" "g")))
10007 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10008 UNSPEC_TLSLD)
10009 (clobber (reg:SI LR_REGNO))]
10010 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10011 {
10012 if (TARGET_CMODEL != CMODEL_SMALL)
10013 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
10014 "bl %z2\;nop";
10015 else
10016 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
10017 }
10018 "&& TARGET_TLS_MARKERS"
10019 [(set (match_dup 0)
10020 (unspec:TLSmode [(match_dup 1)]
10021 UNSPEC_TLSLD))
10022 (parallel [(set (match_dup 0)
10023 (call (mem:TLSmode (match_dup 2))
10024 (match_dup 3)))
10025 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10026 (clobber (reg:SI LR_REGNO))])]
10027 ""
10028 [(set_attr "type" "two")
10029 (set (attr "length")
10030 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10031 (const_int 16)
10032 (const_int 12)))])
10034 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10035 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10036 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10037 (match_operand 3 "" "g")))
10038 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10039 UNSPEC_TLSLD)
10040 (clobber (reg:SI LR_REGNO))]
10041 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10042 {
10043 if (flag_pic)
10044 {
10045 if (TARGET_SECURE_PLT && flag_pic == 2)
10046 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10047 else
10048 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10049 }
10050 else
10051 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10052 }
10053 "&& TARGET_TLS_MARKERS"
10054 [(set (match_dup 0)
10055 (unspec:TLSmode [(match_dup 1)]
10056 UNSPEC_TLSLD))
10057 (parallel [(set (match_dup 0)
10058 (call (mem:TLSmode (match_dup 2))
10059 (match_dup 3)))
10060 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10061 (clobber (reg:SI LR_REGNO))])]
10062 ""
10063 [(set_attr "length" "8")])
10065 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
10066 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10067 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10068 UNSPEC_TLSLD))]
10069 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10070 "addi %0,%1,%&@got@tlsld"
10071 "&& TARGET_CMODEL != CMODEL_SMALL"
10072 [(set (match_dup 2)
10073 (high:TLSmode
10074 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
10075 (set (match_dup 0)
10076 (lo_sum:TLSmode (match_dup 2)
10077 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))]
10078 "
10079 {
10080 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10081 }"
10082 [(set (attr "length")
10083 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10084 (const_int 8)
10085 (const_int 4)))])
10087 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
10088 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10089 (high:TLSmode
10090 (unspec:TLSmode [(const_int 0)
10091 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10092 UNSPEC_TLSLD)))]
10093 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10094 "addis %0,%1,%&@got@tlsld@ha"
10095 [(set_attr "length" "4")])
10097 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
10098 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10099 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10100 (unspec:TLSmode [(const_int 0)
10101 (match_operand:TLSmode 2 "gpc_reg_operand" "b")]
10102 UNSPEC_TLSLD)))]
10103 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10104 "addi %0,%1,%&@got@tlsld@l"
10105 [(set_attr "length" "4")])
10107 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
10108 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10109 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10110 (match_operand 2 "" "g")))
10111 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10112 (clobber (reg:SI LR_REGNO))]
10113 "HAVE_AS_TLS && TARGET_TLS_MARKERS
10114 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10115 "bl %z1(%&@tlsld)\;nop"
10116 [(set_attr "type" "branch")
10117 (set_attr "length" "8")])
10119 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
10120 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10121 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10122 (match_operand 2 "" "g")))
10123 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10124 (clobber (reg:SI LR_REGNO))]
10125 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10126 {
10127 if (flag_pic)
10128 {
10129 if (TARGET_SECURE_PLT && flag_pic == 2)
10130 return "bl %z1+32768(%&@tlsld)@plt";
10131 return "bl %z1(%&@tlsld)@plt";
10132 }
10133 return "bl %z1(%&@tlsld)";
10134 }
10135 [(set_attr "type" "branch")
10136 (set_attr "length" "4")])
10138 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10139 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10140 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10141 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10142 UNSPEC_TLSDTPREL))]
10143 "HAVE_AS_TLS"
10144 "addi %0,%1,%2@dtprel")
10146 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10147 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10148 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10149 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10150 UNSPEC_TLSDTPRELHA))]
10151 "HAVE_AS_TLS"
10152 "addis %0,%1,%2@dtprel@ha")
10154 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10155 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10156 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10157 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10158 UNSPEC_TLSDTPRELLO))]
10159 "HAVE_AS_TLS"
10160 "addi %0,%1,%2@dtprel@l")
10162 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10163 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10164 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10165 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10166 UNSPEC_TLSGOTDTPREL))]
10167 "HAVE_AS_TLS"
10168 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
10169 "&& TARGET_CMODEL != CMODEL_SMALL"
10170 [(set (match_dup 3)
10171 (high:TLSmode
10172 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
10173 (set (match_dup 0)
10174 (lo_sum:TLSmode (match_dup 3)
10175 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
10176 "
10177 {
10178 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10179 }"
10180 [(set (attr "length")
10181 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10182 (const_int 8)
10183 (const_int 4)))])
10185 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
10186 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10187 (high:TLSmode
10188 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10189 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10190 UNSPEC_TLSGOTDTPREL)))]
10191 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10192 "addis %0,%1,%2@got@dtprel@ha"
10193 [(set_attr "length" "4")])
10195 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
10196 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10197 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10198 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
10199 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10200 UNSPEC_TLSGOTDTPREL)))]
10201 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10202 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
10203 [(set_attr "length" "4")])
10205 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10206 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10207 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10208 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10209 UNSPEC_TLSTPREL))]
10210 "HAVE_AS_TLS"
10211 "addi %0,%1,%2@tprel")
10213 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10214 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10215 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10216 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10217 UNSPEC_TLSTPRELHA))]
10218 "HAVE_AS_TLS"
10219 "addis %0,%1,%2@tprel@ha")
10221 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10222 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10223 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10224 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10225 UNSPEC_TLSTPRELLO))]
10226 "HAVE_AS_TLS"
10227 "addi %0,%1,%2@tprel@l")
10229 ;; "b" output constraint here and on tls_tls input to support linker tls
10230 ;; optimization. The linker may edit the instructions emitted by a
10231 ;; tls_got_tprel/tls_tls pair to addis,addi.
10232 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10233 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10234 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10235 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10236 UNSPEC_TLSGOTTPREL))]
10237 "HAVE_AS_TLS"
10238 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
10239 "&& TARGET_CMODEL != CMODEL_SMALL"
10240 [(set (match_dup 3)
10241 (high:TLSmode
10242 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
10243 (set (match_dup 0)
10244 (lo_sum:TLSmode (match_dup 3)
10245 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))]
10246 "
10247 {
10248 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10249 }"
10250 [(set (attr "length")
10251 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10252 (const_int 8)
10253 (const_int 4)))])
10255 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
10256 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10257 (high:TLSmode
10258 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10259 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10260 UNSPEC_TLSGOTTPREL)))]
10261 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10262 "addis %0,%1,%2@got@tprel@ha"
10263 [(set_attr "length" "4")])
10265 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
10266 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10267 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10268 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
10269 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10270 UNSPEC_TLSGOTTPREL)))]
10271 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10272 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
10273 [(set_attr "length" "4")])
10275 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10276 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10277 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10278 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10279 UNSPEC_TLSTLS))]
10280 "TARGET_ELF && HAVE_AS_TLS"
10281 "add %0,%1,%2@tls")
10283 (define_expand "tls_get_tpointer"
10284 [(set (match_operand:SI 0 "gpc_reg_operand" "")
10285 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
10286 "TARGET_XCOFF && HAVE_AS_TLS"
10287 "
10288 {
10289 emit_insn (gen_tls_get_tpointer_internal ());
10290 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
10291 DONE;
10292 }")
10294 (define_insn "tls_get_tpointer_internal"
10295 [(set (reg:SI 3)
10296 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))
10297 (clobber (reg:SI LR_REGNO))]
10298 "TARGET_XCOFF && HAVE_AS_TLS"
10299 "bla __get_tpointer")
10301 (define_expand "tls_get_addr<mode>"
10302 [(set (match_operand:P 0 "gpc_reg_operand" "")
10303 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
10304 (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
10305 "TARGET_XCOFF && HAVE_AS_TLS"
10306 "
10307 {
10308 emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
10309 emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
10310 emit_insn (gen_tls_get_addr_internal<mode> ());
10311 emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
10312 DONE;
10313 }")
10315 (define_insn "tls_get_addr_internal<mode>"
10316 [(set (reg:P 3)
10317 (unspec:P [(reg:P 3) (reg:P 4)] UNSPEC_TLSTLS))
10318 (clobber (reg:P 0))
10319 (clobber (reg:P 4))
10320 (clobber (reg:P 5))
10321 (clobber (reg:P 11))
10322 (clobber (reg:CC CR0_REGNO))
10323 (clobber (reg:P LR_REGNO))]
10324 "TARGET_XCOFF && HAVE_AS_TLS"
10325 "bla __tls_get_addr")
10326 \f
10327 ;; Next come insns related to the calling sequence.
10328 ;;
10329 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10330 ;; We move the back-chain and decrement the stack pointer.
10332 (define_expand "allocate_stack"
10333 [(set (match_operand 0 "gpc_reg_operand" "")
10334 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10335 (set (reg 1)
10336 (minus (reg 1) (match_dup 1)))]
10337 ""
10338 "
10339 { rtx chain = gen_reg_rtx (Pmode);
10340 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10341 rtx neg_op0;
10342 rtx insn, par, set, mem;
10344 emit_move_insn (chain, stack_bot);
10346 /* Check stack bounds if necessary. */
10347 if (crtl->limit_stack)
10348 {
10349 rtx available;
10350 available = expand_binop (Pmode, sub_optab,
10351 stack_pointer_rtx, stack_limit_rtx,
10352 NULL_RTX, 1, OPTAB_WIDEN);
10353 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10354 }
10356 if (GET_CODE (operands[1]) != CONST_INT
10357 || INTVAL (operands[1]) < -32767
10358 || INTVAL (operands[1]) > 32768)
10359 {
10360 neg_op0 = gen_reg_rtx (Pmode);
10361 if (TARGET_32BIT)
10362 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10363 else
10364 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10365 }
10366 else
10367 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10369 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
10370 : gen_movdi_di_update_stack))
10371 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10372 chain));
10373 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10374 it now and set the alias set/attributes. The above gen_*_update
10375 calls will generate a PARALLEL with the MEM set being the first
10376 operation. */
10377 par = PATTERN (insn);
10378 gcc_assert (GET_CODE (par) == PARALLEL);
10379 set = XVECEXP (par, 0, 0);
10380 gcc_assert (GET_CODE (set) == SET);
10381 mem = SET_DEST (set);
10382 gcc_assert (MEM_P (mem));
10383 MEM_NOTRAP_P (mem) = 1;
10384 set_mem_alias_set (mem, get_frame_alias_set ());
10386 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10387 DONE;
10388 }")
10390 ;; These patterns say how to save and restore the stack pointer. We need not
10391 ;; save the stack pointer at function level since we are careful to
10392 ;; preserve the backchain. At block level, we have to restore the backchain
10393 ;; when we restore the stack pointer.
10394 ;;
10395 ;; For nonlocal gotos, we must save both the stack pointer and its
10396 ;; backchain and restore both. Note that in the nonlocal case, the
10397 ;; save area is a memory location.
10399 (define_expand "save_stack_function"
10400 [(match_operand 0 "any_operand" "")
10401 (match_operand 1 "any_operand" "")]
10402 ""
10403 "DONE;")
10405 (define_expand "restore_stack_function"
10406 [(match_operand 0 "any_operand" "")
10407 (match_operand 1 "any_operand" "")]
10408 ""
10409 "DONE;")
10411 ;; Adjust stack pointer (op0) to a new value (op1).
10412 ;; First copy old stack backchain to new location, and ensure that the
10413 ;; scheduler won't reorder the sp assignment before the backchain write.
10414 (define_expand "restore_stack_block"
10415 [(set (match_dup 2) (match_dup 3))
10416 (set (match_dup 4) (match_dup 2))
10417 (match_dup 5)
10418 (set (match_operand 0 "register_operand" "")
10419 (match_operand 1 "register_operand" ""))]
10420 ""
10421 "
10422 {
10423 rtvec p;
10425 operands[1] = force_reg (Pmode, operands[1]);
10426 operands[2] = gen_reg_rtx (Pmode);
10427 operands[3] = gen_frame_mem (Pmode, operands[0]);
10428 operands[4] = gen_frame_mem (Pmode, operands[1]);
10429 p = rtvec_alloc (1);
10430 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10431 gen_frame_mem (BLKmode, operands[0]),
10432 const0_rtx);
10433 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
10434 }")
10436 (define_expand "save_stack_nonlocal"
10437 [(set (match_dup 3) (match_dup 4))
10438 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10439 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10440 ""
10441 "
10442 {
10443 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10445 /* Copy the backchain to the first word, sp to the second. */
10446 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10447 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10448 operands[3] = gen_reg_rtx (Pmode);
10449 operands[4] = gen_frame_mem (Pmode, operands[1]);
10450 }")
10452 (define_expand "restore_stack_nonlocal"
10453 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10454 (set (match_dup 3) (match_dup 4))
10455 (set (match_dup 5) (match_dup 2))
10456 (match_dup 6)
10457 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10458 ""
10459 "
10460 {
10461 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10462 rtvec p;
10464 /* Restore the backchain from the first word, sp from the second. */
10465 operands[2] = gen_reg_rtx (Pmode);
10466 operands[3] = gen_reg_rtx (Pmode);
10467 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10468 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10469 operands[5] = gen_frame_mem (Pmode, operands[3]);
10470 p = rtvec_alloc (1);
10471 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10472 gen_frame_mem (BLKmode, operands[0]),
10473 const0_rtx);
10474 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
10475 }")
10476 \f
10477 ;; TOC register handling.
10479 ;; Code to initialize the TOC register...
10481 (define_insn "load_toc_aix_si"
10482 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10483 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10484 (use (reg:SI 2))])]
10485 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT"
10486 "*
10487 {
10488 char buf[30];
10489 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10490 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10491 operands[2] = gen_rtx_REG (Pmode, 2);
10492 return \"lwz %0,%1(%2)\";
10493 }"
10494 [(set_attr "type" "load")
10495 (set_attr "update" "no")
10496 (set_attr "indexed" "no")])
10498 (define_insn "load_toc_aix_di"
10499 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10500 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10501 (use (reg:DI 2))])]
10502 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT"
10503 "*
10504 {
10505 char buf[30];
10506 #ifdef TARGET_RELOCATABLE
10507 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10508 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10509 #else
10510 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10511 #endif
10512 if (TARGET_ELF)
10513 strcat (buf, \"@toc\");
10514 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10515 operands[2] = gen_rtx_REG (Pmode, 2);
10516 return \"ld %0,%1(%2)\";
10517 }"
10518 [(set_attr "type" "load")
10519 (set_attr "update" "no")
10520 (set_attr "indexed" "no")])
10522 (define_insn "load_toc_v4_pic_si"
10523 [(set (reg:SI LR_REGNO)
10524 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10525 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10526 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10527 [(set_attr "type" "branch")
10528 (set_attr "length" "4")])
10530 (define_expand "load_toc_v4_PIC_1"
10531 [(parallel [(set (reg:SI LR_REGNO)
10532 (match_operand:SI 0 "immediate_operand" "s"))
10533 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
10534 "TARGET_ELF && DEFAULT_ABI == ABI_V4
10535 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10536 "")
10538 (define_insn "load_toc_v4_PIC_1_normal"
10539 [(set (reg:SI LR_REGNO)
10540 (match_operand:SI 0 "immediate_operand" "s"))
10541 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10542 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
10543 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10544 "bcl 20,31,%0\\n%0:"
10545 [(set_attr "type" "branch")
10546 (set_attr "length" "4")])
10548 (define_insn "load_toc_v4_PIC_1_476"
10549 [(set (reg:SI LR_REGNO)
10550 (match_operand:SI 0 "immediate_operand" "s"))
10551 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10552 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
10553 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10554 "*
10555 {
10556 char name[32];
10557 static char templ[32];
10559 get_ppc476_thunk_name (name);
10560 sprintf (templ, \"bl %s\\n%%0:\", name);
10561 return templ;
10562 }"
10563 [(set_attr "type" "branch")
10564 (set_attr "length" "4")])
10566 (define_expand "load_toc_v4_PIC_1b"
10567 [(parallel [(set (reg:SI LR_REGNO)
10568 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10569 (label_ref (match_operand 1 "" ""))]
10570 UNSPEC_TOCPTR))
10571 (match_dup 1)])]
10572 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10573 "")
10575 (define_insn "load_toc_v4_PIC_1b_normal"
10576 [(set (reg:SI LR_REGNO)
10577 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10578 (label_ref (match_operand 1 "" ""))]
10579 UNSPEC_TOCPTR))
10580 (match_dup 1)]
10581 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10582 "bcl 20,31,$+8\;.long %0-$"
10583 [(set_attr "type" "branch")
10584 (set_attr "length" "8")])
10586 (define_insn "load_toc_v4_PIC_1b_476"
10587 [(set (reg:SI LR_REGNO)
10588 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10589 (label_ref (match_operand 1 "" ""))]
10590 UNSPEC_TOCPTR))
10591 (match_dup 1)]
10592 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10593 "*
10594 {
10595 char name[32];
10596 static char templ[32];
10598 get_ppc476_thunk_name (name);
10599 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
10600 return templ;
10601 }"
10602 [(set_attr "type" "branch")
10603 (set_attr "length" "16")])
10605 (define_insn "load_toc_v4_PIC_2"
10606 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10607 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10608 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10609 (match_operand:SI 3 "immediate_operand" "s")))))]
10610 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10611 "lwz %0,%2-%3(%1)"
10612 [(set_attr "type" "load")])
10614 (define_insn "load_toc_v4_PIC_3b"
10615 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10616 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10617 (high:SI
10618 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10619 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10620 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
10621 "addis %0,%1,%2-%3@ha")
10623 (define_insn "load_toc_v4_PIC_3c"
10624 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10625 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10626 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10627 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10628 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
10629 "addi %0,%1,%2-%3@l")
10631 ;; If the TOC is shared over a translation unit, as happens with all
10632 ;; the kinds of PIC that we support, we need to restore the TOC
10633 ;; pointer only when jumping over units of translation.
10634 ;; On Darwin, we need to reload the picbase.
10636 (define_expand "builtin_setjmp_receiver"
10637 [(use (label_ref (match_operand 0 "" "")))]
10638 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10639 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10640 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10641 "
10642 {
10643 #if TARGET_MACHO
10644 if (DEFAULT_ABI == ABI_DARWIN)
10645 {
10646 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
10647 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10648 rtx tmplabrtx;
10649 char tmplab[20];
10651 crtl->uses_pic_offset_table = 1;
10652 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10653 CODE_LABEL_NUMBER (operands[0]));
10654 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10656 emit_insn (gen_load_macho_picbase (tmplabrtx));
10657 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10658 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10659 }
10660 else
10661 #endif
10662 rs6000_emit_load_toc_table (FALSE);
10663 DONE;
10664 }")
10666 ;; Largetoc support
10667 (define_insn "*largetoc_high"
10668 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10669 (high:DI
10670 (unspec [(match_operand:DI 1 "" "")
10671 (match_operand:DI 2 "gpc_reg_operand" "b")]
10672 UNSPEC_TOCREL)))]
10673 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10674 "addis %0,%2,%1@toc@ha")
10676 (define_insn "*largetoc_high_aix<mode>"
10677 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10678 (high:P
10679 (unspec [(match_operand:P 1 "" "")
10680 (match_operand:P 2 "gpc_reg_operand" "b")]
10681 UNSPEC_TOCREL)))]
10682 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10683 "addis %0,%1@u(%2)")
10685 (define_insn "*largetoc_high_plus"
10686 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10687 (high:DI
10688 (plus:DI
10689 (unspec [(match_operand:DI 1 "" "")
10690 (match_operand:DI 2 "gpc_reg_operand" "b")]
10691 UNSPEC_TOCREL)
10692 (match_operand:DI 3 "add_cint_operand" "n"))))]
10693 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10694 "addis %0,%2,%1+%3@toc@ha")
10696 (define_insn "*largetoc_high_plus_aix<mode>"
10697 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10698 (high:P
10699 (plus:P
10700 (unspec [(match_operand:P 1 "" "")
10701 (match_operand:P 2 "gpc_reg_operand" "b")]
10702 UNSPEC_TOCREL)
10703 (match_operand:P 3 "add_cint_operand" "n"))))]
10704 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10705 "addis %0,%1+%3@u(%2)")
10707 (define_insn "*largetoc_low"
10708 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10709 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
10710 (match_operand:DI 2 "" "")))]
10711 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10712 "@
10713 addi %0,%1,%2@l
10714 addic %0,%1,%2@l")
10716 (define_insn "*largetoc_low_aix<mode>"
10717 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
10718 (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
10719 (match_operand:P 2 "" "")))]
10720 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10721 "la %0,%2@l(%1)")
10723 (define_insn_and_split "*tocref<mode>"
10724 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10725 (match_operand:P 1 "small_toc_ref" "R"))]
10726 "TARGET_TOC"
10727 "la %0,%a1"
10728 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
10729 [(set (match_dup 0) (high:P (match_dup 1)))
10730 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
10732 ;; Elf specific ways of loading addresses for non-PIC code.
10733 ;; The output of this could be r0, but we make a very strong
10734 ;; preference for a base register because it will usually
10735 ;; be needed there.
10736 (define_insn "elf_high"
10737 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10738 (high:SI (match_operand 1 "" "")))]
10739 "TARGET_ELF && ! TARGET_64BIT"
10740 "lis %0,%1@ha")
10742 (define_insn "elf_low"
10743 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10744 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10745 (match_operand 2 "" "")))]
10746 "TARGET_ELF && ! TARGET_64BIT"
10747 "@
10748 la %0,%2@l(%1)
10749 addic %0,%1,%K2")
10750 \f
10751 ;; Call and call_value insns
10752 (define_expand "call"
10753 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10754 (match_operand 1 "" ""))
10755 (use (match_operand 2 "" ""))
10756 (clobber (reg:SI LR_REGNO))])]
10757 ""
10758 "
10759 {
10760 #if TARGET_MACHO
10761 if (MACHOPIC_INDIRECT)
10762 operands[0] = machopic_indirect_call_target (operands[0]);
10763 #endif
10765 gcc_assert (GET_CODE (operands[0]) == MEM);
10766 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10768 operands[0] = XEXP (operands[0], 0);
10770 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10771 {
10772 rs6000_call_aix (NULL_RTX, operands[0], operands[1], operands[2]);
10773 DONE;
10774 }
10776 if (GET_CODE (operands[0]) != SYMBOL_REF
10777 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10778 {
10779 if (INTVAL (operands[2]) & CALL_LONG)
10780 operands[0] = rs6000_longcall_ref (operands[0]);
10782 switch (DEFAULT_ABI)
10783 {
10784 case ABI_V4:
10785 case ABI_DARWIN:
10786 operands[0] = force_reg (Pmode, operands[0]);
10787 break;
10789 default:
10790 gcc_unreachable ();
10791 }
10792 }
10793 }")
10795 (define_expand "call_value"
10796 [(parallel [(set (match_operand 0 "" "")
10797 (call (mem:SI (match_operand 1 "address_operand" ""))
10798 (match_operand 2 "" "")))
10799 (use (match_operand 3 "" ""))
10800 (clobber (reg:SI LR_REGNO))])]
10801 ""
10802 "
10803 {
10804 #if TARGET_MACHO
10805 if (MACHOPIC_INDIRECT)
10806 operands[1] = machopic_indirect_call_target (operands[1]);
10807 #endif
10809 gcc_assert (GET_CODE (operands[1]) == MEM);
10810 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10812 operands[1] = XEXP (operands[1], 0);
10814 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10815 {
10816 rs6000_call_aix (operands[0], operands[1], operands[2], operands[3]);
10817 DONE;
10818 }
10820 if (GET_CODE (operands[1]) != SYMBOL_REF
10821 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10822 {
10823 if (INTVAL (operands[3]) & CALL_LONG)
10824 operands[1] = rs6000_longcall_ref (operands[1]);
10826 switch (DEFAULT_ABI)
10827 {
10828 case ABI_V4:
10829 case ABI_DARWIN:
10830 operands[1] = force_reg (Pmode, operands[1]);
10831 break;
10833 default:
10834 gcc_unreachable ();
10835 }
10836 }
10837 }")
10839 ;; Call to function in current module. No TOC pointer reload needed.
10840 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10841 ;; either the function was not prototyped, or it was prototyped as a
10842 ;; variable argument function. It is > 0 if FP registers were passed
10843 ;; and < 0 if they were not.
10845 (define_insn "*call_local32"
10846 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10847 (match_operand 1 "" "g,g"))
10848 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10849 (clobber (reg:SI LR_REGNO))]
10850 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10851 "*
10852 {
10853 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10854 output_asm_insn (\"crxor 6,6,6\", operands);
10856 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10857 output_asm_insn (\"creqv 6,6,6\", operands);
10859 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10860 }"
10861 [(set_attr "type" "branch")
10862 (set_attr "length" "4,8")])
10864 (define_insn "*call_local64"
10865 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10866 (match_operand 1 "" "g,g"))
10867 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10868 (clobber (reg:SI LR_REGNO))]
10869 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10870 "*
10871 {
10872 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10873 output_asm_insn (\"crxor 6,6,6\", operands);
10875 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10876 output_asm_insn (\"creqv 6,6,6\", operands);
10878 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10879 }"
10880 [(set_attr "type" "branch")
10881 (set_attr "length" "4,8")])
10883 (define_insn "*call_value_local32"
10884 [(set (match_operand 0 "" "")
10885 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10886 (match_operand 2 "" "g,g")))
10887 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10888 (clobber (reg:SI LR_REGNO))]
10889 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10890 "*
10891 {
10892 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10893 output_asm_insn (\"crxor 6,6,6\", operands);
10895 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10896 output_asm_insn (\"creqv 6,6,6\", operands);
10898 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10899 }"
10900 [(set_attr "type" "branch")
10901 (set_attr "length" "4,8")])
10904 (define_insn "*call_value_local64"
10905 [(set (match_operand 0 "" "")
10906 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10907 (match_operand 2 "" "g,g")))
10908 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10909 (clobber (reg:SI LR_REGNO))]
10910 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10911 "*
10912 {
10913 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10914 output_asm_insn (\"crxor 6,6,6\", operands);
10916 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10917 output_asm_insn (\"creqv 6,6,6\", operands);
10919 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10920 }"
10921 [(set_attr "type" "branch")
10922 (set_attr "length" "4,8")])
10925 ;; A function pointer under System V is just a normal pointer
10926 ;; operands[0] is the function pointer
10927 ;; operands[1] is the stack size to clean up
10928 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10929 ;; which indicates how to set cr1
10931 (define_insn "*call_indirect_nonlocal_sysv<mode>"
10932 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
10933 (match_operand 1 "" "g,g,g,g"))
10934 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10935 (clobber (reg:SI LR_REGNO))]
10936 "DEFAULT_ABI == ABI_V4
10937 || DEFAULT_ABI == ABI_DARWIN"
10938 {
10939 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10940 output_asm_insn ("crxor 6,6,6", operands);
10942 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10943 output_asm_insn ("creqv 6,6,6", operands);
10945 return "b%T0l";
10946 }
10947 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10948 (set_attr "length" "4,4,8,8")])
10950 (define_insn_and_split "*call_nonlocal_sysv<mode>"
10951 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10952 (match_operand 1 "" "g,g"))
10953 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10954 (clobber (reg:SI LR_REGNO))]
10955 "(DEFAULT_ABI == ABI_DARWIN
10956 || (DEFAULT_ABI == ABI_V4
10957 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10958 {
10959 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10960 output_asm_insn ("crxor 6,6,6", operands);
10962 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10963 output_asm_insn ("creqv 6,6,6", operands);
10965 #if TARGET_MACHO
10966 return output_call(insn, operands, 0, 2);
10967 #else
10968 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10969 {
10970 gcc_assert (!TARGET_SECURE_PLT);
10971 return "bl %z0@plt";
10972 }
10973 else
10974 return "bl %z0";
10975 #endif
10976 }
10977 "DEFAULT_ABI == ABI_V4
10978 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10979 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10980 [(parallel [(call (mem:SI (match_dup 0))
10981 (match_dup 1))
10982 (use (match_dup 2))
10983 (use (match_dup 3))
10984 (clobber (reg:SI LR_REGNO))])]
10985 {
10986 operands[3] = pic_offset_table_rtx;
10987 }
10988 [(set_attr "type" "branch,branch")
10989 (set_attr "length" "4,8")])
10991 (define_insn "*call_nonlocal_sysv_secure<mode>"
10992 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10993 (match_operand 1 "" "g,g"))
10994 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10995 (use (match_operand:SI 3 "register_operand" "r,r"))
10996 (clobber (reg:SI LR_REGNO))]
10997 "(DEFAULT_ABI == ABI_V4
10998 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10999 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
11000 {
11001 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11002 output_asm_insn ("crxor 6,6,6", operands);
11004 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11005 output_asm_insn ("creqv 6,6,6", operands);
11007 if (flag_pic == 2)
11008 /* The magic 32768 offset here and in the other sysv call insns
11009 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11010 See sysv4.h:toc_section. */
11011 return "bl %z0+32768@plt";
11012 else
11013 return "bl %z0@plt";
11014 }
11015 [(set_attr "type" "branch,branch")
11016 (set_attr "length" "4,8")])
11018 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11019 [(set (match_operand 0 "" "")
11020 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11021 (match_operand 2 "" "g,g,g,g")))
11022 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11023 (clobber (reg:SI LR_REGNO))]
11024 "DEFAULT_ABI == ABI_V4
11025 || DEFAULT_ABI == ABI_DARWIN"
11026 {
11027 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11028 output_asm_insn ("crxor 6,6,6", operands);
11030 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11031 output_asm_insn ("creqv 6,6,6", operands);
11033 return "b%T1l";
11034 }
11035 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11036 (set_attr "length" "4,4,8,8")])
11038 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
11039 [(set (match_operand 0 "" "")
11040 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11041 (match_operand 2 "" "g,g")))
11042 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11043 (clobber (reg:SI LR_REGNO))]
11044 "(DEFAULT_ABI == ABI_DARWIN
11045 || (DEFAULT_ABI == ABI_V4
11046 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11047 {
11048 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11049 output_asm_insn ("crxor 6,6,6", operands);
11051 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11052 output_asm_insn ("creqv 6,6,6", operands);
11054 #if TARGET_MACHO
11055 return output_call(insn, operands, 1, 3);
11056 #else
11057 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11058 {
11059 gcc_assert (!TARGET_SECURE_PLT);
11060 return "bl %z1@plt";
11061 }
11062 else
11063 return "bl %z1";
11064 #endif
11065 }
11066 "DEFAULT_ABI == ABI_V4
11067 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11068 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11069 [(parallel [(set (match_dup 0)
11070 (call (mem:SI (match_dup 1))
11071 (match_dup 2)))
11072 (use (match_dup 3))
11073 (use (match_dup 4))
11074 (clobber (reg:SI LR_REGNO))])]
11075 {
11076 operands[4] = pic_offset_table_rtx;
11077 }
11078 [(set_attr "type" "branch,branch")
11079 (set_attr "length" "4,8")])
11081 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
11082 [(set (match_operand 0 "" "")
11083 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11084 (match_operand 2 "" "g,g")))
11085 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11086 (use (match_operand:SI 4 "register_operand" "r,r"))
11087 (clobber (reg:SI LR_REGNO))]
11088 "(DEFAULT_ABI == ABI_V4
11089 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11090 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
11091 {
11092 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11093 output_asm_insn ("crxor 6,6,6", operands);
11095 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11096 output_asm_insn ("creqv 6,6,6", operands);
11098 if (flag_pic == 2)
11099 return "bl %z1+32768@plt";
11100 else
11101 return "bl %z1@plt";
11102 }
11103 [(set_attr "type" "branch,branch")
11104 (set_attr "length" "4,8")])
11107 ;; Call to AIX abi function in the same module.
11109 (define_insn "*call_local_aix<mode>"
11110 [(call (mem:SI (match_operand:P 0 "current_file_function_operand" "s"))
11111 (match_operand 1 "" "g"))
11112 (clobber (reg:P LR_REGNO))]
11113 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11114 "bl %z0"
11115 [(set_attr "type" "branch")
11116 (set_attr "length" "4")])
11118 (define_insn "*call_value_local_aix<mode>"
11119 [(set (match_operand 0 "" "")
11120 (call (mem:SI (match_operand:P 1 "current_file_function_operand" "s"))
11121 (match_operand 2 "" "g")))
11122 (clobber (reg:P LR_REGNO))]
11123 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11124 "bl %z1"
11125 [(set_attr "type" "branch")
11126 (set_attr "length" "4")])
11128 ;; Call to AIX abi function which may be in another module.
11129 ;; Restore the TOC pointer (r2) after the call.
11131 (define_insn "*call_nonlocal_aix<mode>"
11132 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s"))
11133 (match_operand 1 "" "g"))
11134 (clobber (reg:P LR_REGNO))]
11135 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11136 "bl %z0\;nop"
11137 [(set_attr "type" "branch")
11138 (set_attr "length" "8")])
11140 (define_insn "*call_value_nonlocal_aix<mode>"
11141 [(set (match_operand 0 "" "")
11142 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s"))
11143 (match_operand 2 "" "g")))
11144 (clobber (reg:P LR_REGNO))]
11145 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11146 "bl %z1\;nop"
11147 [(set_attr "type" "branch")
11148 (set_attr "length" "8")])
11150 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
11151 ;; Operand0 is the addresss of the function to call
11152 ;; Operand2 is the location in the function descriptor to load r2 from
11153 ;; Operand3 is the stack location to hold the current TOC pointer
11155 (define_insn "*call_indirect_aix<mode>"
11156 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11157 (match_operand 1 "" "g,g"))
11158 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11159 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11160 (clobber (reg:P LR_REGNO))]
11161 "DEFAULT_ABI == ABI_AIX"
11162 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
11163 [(set_attr "type" "jmpreg")
11164 (set_attr "length" "12")])
11166 (define_insn "*call_value_indirect_aix<mode>"
11167 [(set (match_operand 0 "" "")
11168 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11169 (match_operand 2 "" "g,g")))
11170 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11171 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
11172 (clobber (reg:P LR_REGNO))]
11173 "DEFAULT_ABI == ABI_AIX"
11174 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
11175 [(set_attr "type" "jmpreg")
11176 (set_attr "length" "12")])
11178 ;; Call to indirect functions with the ELFv2 ABI.
11179 ;; Operand0 is the addresss of the function to call
11180 ;; Operand2 is the stack location to hold the current TOC pointer
11182 (define_insn "*call_indirect_elfv2<mode>"
11183 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11184 (match_operand 1 "" "g,g"))
11185 (set (reg:P TOC_REGNUM) (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11186 (clobber (reg:P LR_REGNO))]
11187 "DEFAULT_ABI == ABI_ELFv2"
11188 "b%T0l\;<ptrload> 2,%2"
11189 [(set_attr "type" "jmpreg")
11190 (set_attr "length" "8")])
11192 (define_insn "*call_value_indirect_elfv2<mode>"
11193 [(set (match_operand 0 "" "")
11194 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11195 (match_operand 2 "" "g,g")))
11196 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11197 (clobber (reg:P LR_REGNO))]
11198 "DEFAULT_ABI == ABI_ELFv2"
11199 "b%T1l\;<ptrload> 2,%3"
11200 [(set_attr "type" "jmpreg")
11201 (set_attr "length" "8")])
11204 ;; Call subroutine returning any type.
11205 (define_expand "untyped_call"
11206 [(parallel [(call (match_operand 0 "" "")
11207 (const_int 0))
11208 (match_operand 1 "" "")
11209 (match_operand 2 "" "")])]
11210 ""
11211 "
11212 {
11213 int i;
11215 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11217 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11218 {
11219 rtx set = XVECEXP (operands[2], 0, i);
11220 emit_move_insn (SET_DEST (set), SET_SRC (set));
11221 }
11223 /* The optimizer does not know that the call sets the function value
11224 registers we stored in the result block. We avoid problems by
11225 claiming that all hard registers are used and clobbered at this
11226 point. */
11227 emit_insn (gen_blockage ());
11229 DONE;
11230 }")
11232 ;; sibling call patterns
11233 (define_expand "sibcall"
11234 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11235 (match_operand 1 "" ""))
11236 (use (match_operand 2 "" ""))
11237 (use (reg:SI LR_REGNO))
11238 (simple_return)])]
11239 ""
11240 "
11241 {
11242 #if TARGET_MACHO
11243 if (MACHOPIC_INDIRECT)
11244 operands[0] = machopic_indirect_call_target (operands[0]);
11245 #endif
11247 gcc_assert (GET_CODE (operands[0]) == MEM);
11248 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11250 operands[0] = XEXP (operands[0], 0);
11252 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11253 {
11254 rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]);
11255 DONE;
11256 }
11257 }")
11259 (define_expand "sibcall_value"
11260 [(parallel [(set (match_operand 0 "register_operand" "")
11261 (call (mem:SI (match_operand 1 "address_operand" ""))
11262 (match_operand 2 "" "")))
11263 (use (match_operand 3 "" ""))
11264 (use (reg:SI LR_REGNO))
11265 (simple_return)])]
11266 ""
11267 "
11268 {
11269 #if TARGET_MACHO
11270 if (MACHOPIC_INDIRECT)
11271 operands[1] = machopic_indirect_call_target (operands[1]);
11272 #endif
11274 gcc_assert (GET_CODE (operands[1]) == MEM);
11275 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11277 operands[1] = XEXP (operands[1], 0);
11279 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11280 {
11281 rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]);
11282 DONE;
11283 }
11284 }")
11286 ;; this and similar patterns must be marked as using LR, otherwise
11287 ;; dataflow will try to delete the store into it. This is true
11288 ;; even when the actual reg to jump to is in CTR, when LR was
11289 ;; saved and restored around the PIC-setting BCL.
11290 (define_insn "*sibcall_local32"
11291 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11292 (match_operand 1 "" "g,g"))
11293 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11294 (use (reg:SI LR_REGNO))
11295 (simple_return)]
11296 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11297 "*
11298 {
11299 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11300 output_asm_insn (\"crxor 6,6,6\", operands);
11302 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11303 output_asm_insn (\"creqv 6,6,6\", operands);
11305 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11306 }"
11307 [(set_attr "type" "branch")
11308 (set_attr "length" "4,8")])
11310 (define_insn "*sibcall_local64"
11311 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11312 (match_operand 1 "" "g,g"))
11313 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11314 (use (reg:SI LR_REGNO))
11315 (simple_return)]
11316 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11317 "*
11318 {
11319 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11320 output_asm_insn (\"crxor 6,6,6\", operands);
11322 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11323 output_asm_insn (\"creqv 6,6,6\", operands);
11325 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11326 }"
11327 [(set_attr "type" "branch")
11328 (set_attr "length" "4,8")])
11330 (define_insn "*sibcall_value_local32"
11331 [(set (match_operand 0 "" "")
11332 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11333 (match_operand 2 "" "g,g")))
11334 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11335 (use (reg:SI LR_REGNO))
11336 (simple_return)]
11337 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11338 "*
11339 {
11340 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11341 output_asm_insn (\"crxor 6,6,6\", operands);
11343 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11344 output_asm_insn (\"creqv 6,6,6\", operands);
11346 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11347 }"
11348 [(set_attr "type" "branch")
11349 (set_attr "length" "4,8")])
11351 (define_insn "*sibcall_value_local64"
11352 [(set (match_operand 0 "" "")
11353 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11354 (match_operand 2 "" "g,g")))
11355 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11356 (use (reg:SI LR_REGNO))
11357 (simple_return)]
11358 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11359 "*
11360 {
11361 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11362 output_asm_insn (\"crxor 6,6,6\", operands);
11364 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11365 output_asm_insn (\"creqv 6,6,6\", operands);
11367 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11368 }"
11369 [(set_attr "type" "branch")
11370 (set_attr "length" "4,8")])
11372 (define_insn "*sibcall_nonlocal_sysv<mode>"
11373 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
11374 (match_operand 1 "" ""))
11375 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
11376 (use (reg:SI LR_REGNO))
11377 (simple_return)]
11378 "(DEFAULT_ABI == ABI_DARWIN
11379 || DEFAULT_ABI == ABI_V4)
11380 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11381 "*
11382 {
11383 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11384 output_asm_insn (\"crxor 6,6,6\", operands);
11386 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11387 output_asm_insn (\"creqv 6,6,6\", operands);
11389 if (which_alternative >= 2)
11390 return \"b%T0\";
11391 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11392 {
11393 gcc_assert (!TARGET_SECURE_PLT);
11394 return \"b %z0@plt\";
11395 }
11396 else
11397 return \"b %z0\";
11398 }"
11399 [(set_attr "type" "branch")
11400 (set_attr "length" "4,8,4,8")])
11402 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11403 [(set (match_operand 0 "" "")
11404 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
11405 (match_operand 2 "" "")))
11406 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
11407 (use (reg:SI LR_REGNO))
11408 (simple_return)]
11409 "(DEFAULT_ABI == ABI_DARWIN
11410 || DEFAULT_ABI == ABI_V4)
11411 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11412 "*
11413 {
11414 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11415 output_asm_insn (\"crxor 6,6,6\", operands);
11417 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11418 output_asm_insn (\"creqv 6,6,6\", operands);
11420 if (which_alternative >= 2)
11421 return \"b%T1\";
11422 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11423 {
11424 gcc_assert (!TARGET_SECURE_PLT);
11425 return \"b %z1@plt\";
11426 }
11427 else
11428 return \"b %z1\";
11429 }"
11430 [(set_attr "type" "branch")
11431 (set_attr "length" "4,8,4,8")])
11433 ;; AIX ABI sibling call patterns.
11435 (define_insn "*sibcall_aix<mode>"
11436 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
11437 (match_operand 1 "" "g,g"))
11438 (simple_return)]
11439 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11440 "@
11441 b %z0
11442 b%T0"
11443 [(set_attr "type" "branch")
11444 (set_attr "length" "4")])
11446 (define_insn "*sibcall_value_aix<mode>"
11447 [(set (match_operand 0 "" "")
11448 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
11449 (match_operand 2 "" "g,g")))
11450 (simple_return)]
11451 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11452 "@
11453 b %z1
11454 b%T1"
11455 [(set_attr "type" "branch")
11456 (set_attr "length" "4")])
11458 (define_expand "sibcall_epilogue"
11459 [(use (const_int 0))]
11460 ""
11461 {
11462 if (!TARGET_SCHED_PROLOG)
11463 emit_insn (gen_blockage ());
11464 rs6000_emit_epilogue (TRUE);
11465 DONE;
11466 })
11468 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11469 ;; all of memory. This blocks insns from being moved across this point.
11471 (define_insn "blockage"
11472 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11473 ""
11474 "")
11476 (define_expand "probe_stack"
11477 [(set (match_operand 0 "memory_operand" "=m")
11478 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
11479 ""
11480 {
11481 if (TARGET_64BIT)
11482 emit_insn (gen_probe_stack_di (operands[0]));
11483 else
11484 emit_insn (gen_probe_stack_si (operands[0]));
11485 DONE;
11486 })
11488 (define_insn "probe_stack_<mode>"
11489 [(set (match_operand:P 0 "memory_operand" "=m")
11490 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
11491 ""
11492 {
11493 operands[1] = gen_rtx_REG (Pmode, 0);
11494 return "st<wd>%U0%X0 %1,%0";
11495 }
11496 [(set_attr "type" "store")
11497 (set (attr "update")
11498 (if_then_else (match_operand 0 "update_address_mem")
11499 (const_string "yes")
11500 (const_string "no")))
11501 (set (attr "indexed")
11502 (if_then_else (match_operand 0 "indexed_address_mem")
11503 (const_string "yes")
11504 (const_string "no")))
11505 (set_attr "length" "4")])
11507 (define_insn "probe_stack_range<P:mode>"
11508 [(set (match_operand:P 0 "register_operand" "=r")
11509 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
11510 (match_operand:P 2 "register_operand" "r")]
11511 UNSPECV_PROBE_STACK_RANGE))]
11512 ""
11513 "* return output_probe_stack_range (operands[0], operands[2]);"
11514 [(set_attr "type" "three")])
11515 \f
11516 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11517 ;; signed & unsigned, and one type of branch.
11518 ;;
11519 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11520 ;; insns, and branches.
11522 (define_expand "cbranch<mode>4"
11523 [(use (match_operator 0 "rs6000_cbranch_operator"
11524 [(match_operand:GPR 1 "gpc_reg_operand" "")
11525 (match_operand:GPR 2 "reg_or_short_operand" "")]))
11526 (use (match_operand 3 ""))]
11527 ""
11528 "
11529 {
11530 /* Take care of the possibility that operands[2] might be negative but
11531 this might be a logical operation. That insn doesn't exist. */
11532 if (GET_CODE (operands[2]) == CONST_INT
11533 && INTVAL (operands[2]) < 0)
11534 {
11535 operands[2] = force_reg (<MODE>mode, operands[2]);
11536 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
11537 GET_MODE (operands[0]),
11538 operands[1], operands[2]);
11539 }
11541 rs6000_emit_cbranch (<MODE>mode, operands);
11542 DONE;
11543 }")
11545 (define_expand "cbranch<mode>4"
11546 [(use (match_operator 0 "rs6000_cbranch_operator"
11547 [(match_operand:FP 1 "gpc_reg_operand" "")
11548 (match_operand:FP 2 "gpc_reg_operand" "")]))
11549 (use (match_operand 3 ""))]
11550 ""
11551 "
11552 {
11553 rs6000_emit_cbranch (<MODE>mode, operands);
11554 DONE;
11555 }")
11557 (define_expand "cstore<mode>4"
11558 [(use (match_operator 1 "rs6000_cbranch_operator"
11559 [(match_operand:GPR 2 "gpc_reg_operand" "")
11560 (match_operand:GPR 3 "reg_or_short_operand" "")]))
11561 (clobber (match_operand:SI 0 "register_operand"))]
11562 ""
11563 "
11564 {
11565 /* Take care of the possibility that operands[3] might be negative but
11566 this might be a logical operation. That insn doesn't exist. */
11567 if (GET_CODE (operands[3]) == CONST_INT
11568 && INTVAL (operands[3]) < 0)
11569 {
11570 operands[3] = force_reg (<MODE>mode, operands[3]);
11571 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
11572 GET_MODE (operands[1]),
11573 operands[2], operands[3]);
11574 }
11576 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
11577 For SEQ, likewise, except that comparisons with zero should be done
11578 with an scc insns. However, due to the order that combine see the
11579 resulting insns, we must, in fact, allow SEQ for integers. Fail in
11580 the cases we don't want to handle or are best handled by portable
11581 code. */
11582 if (GET_CODE (operands[1]) == NE)
11583 FAIL;
11584 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
11585 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
11586 && operands[3] == const0_rtx)
11587 FAIL;
11588 rs6000_emit_sCOND (<MODE>mode, operands);
11589 DONE;
11590 }")
11592 (define_expand "cstore<mode>4"
11593 [(use (match_operator 1 "rs6000_cbranch_operator"
11594 [(match_operand:FP 2 "gpc_reg_operand" "")
11595 (match_operand:FP 3 "gpc_reg_operand" "")]))
11596 (clobber (match_operand:SI 0 "register_operand"))]
11597 ""
11598 "
11599 {
11600 rs6000_emit_sCOND (<MODE>mode, operands);
11601 DONE;
11602 }")
11605 (define_expand "stack_protect_set"
11606 [(match_operand 0 "memory_operand" "")
11607 (match_operand 1 "memory_operand" "")]
11608 ""
11609 {
11610 #ifdef TARGET_THREAD_SSP_OFFSET
11611 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11612 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11613 operands[1] = gen_rtx_MEM (Pmode, addr);
11614 #endif
11615 if (TARGET_64BIT)
11616 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11617 else
11618 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11619 DONE;
11620 })
11622 (define_insn "stack_protect_setsi"
11623 [(set (match_operand:SI 0 "memory_operand" "=m")
11624 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11625 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11626 "TARGET_32BIT"
11627 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
11628 [(set_attr "type" "three")
11629 (set_attr "length" "12")])
11631 (define_insn "stack_protect_setdi"
11632 [(set (match_operand:DI 0 "memory_operand" "=Y")
11633 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
11634 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11635 "TARGET_64BIT"
11636 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
11637 [(set_attr "type" "three")
11638 (set_attr "length" "12")])
11640 (define_expand "stack_protect_test"
11641 [(match_operand 0 "memory_operand" "")
11642 (match_operand 1 "memory_operand" "")
11643 (match_operand 2 "" "")]
11644 ""
11645 {
11646 rtx test, op0, op1;
11647 #ifdef TARGET_THREAD_SSP_OFFSET
11648 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11649 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11650 operands[1] = gen_rtx_MEM (Pmode, addr);
11651 #endif
11652 op0 = operands[0];
11653 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
11654 test = gen_rtx_EQ (VOIDmode, op0, op1);
11655 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
11656 DONE;
11657 })
11659 (define_insn "stack_protect_testsi"
11660 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11661 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11662 (match_operand:SI 2 "memory_operand" "m,m")]
11663 UNSPEC_SP_TEST))
11664 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11665 (clobber (match_scratch:SI 3 "=&r,&r"))]
11666 "TARGET_32BIT"
11667 "@
11668 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11669 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
11670 [(set_attr "length" "16,20")])
11672 (define_insn "stack_protect_testdi"
11673 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11674 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
11675 (match_operand:DI 2 "memory_operand" "Y,Y")]
11676 UNSPEC_SP_TEST))
11677 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11678 (clobber (match_scratch:DI 3 "=&r,&r"))]
11679 "TARGET_64BIT"
11680 "@
11681 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11682 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
11683 [(set_attr "length" "16,20")])
11685 \f
11686 ;; Here are the actual compare insns.
11687 (define_insn "*cmp<mode>_internal1"
11688 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11689 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11690 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11691 ""
11692 "cmp<wd>%I2 %0,%1,%2"
11693 [(set_attr "type" "cmp")])
11695 ;; If we are comparing a register for equality with a large constant,
11696 ;; we can do this with an XOR followed by a compare. But this is profitable
11697 ;; only if the large constant is only used for the comparison (and in this
11698 ;; case we already have a register to reuse as scratch).
11699 ;;
11700 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11701 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11703 (define_peephole2
11704 [(set (match_operand:SI 0 "register_operand")
11705 (match_operand:SI 1 "logical_const_operand" ""))
11706 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11707 [(match_dup 0)
11708 (match_operand:SI 2 "logical_const_operand" "")]))
11709 (set (match_operand:CC 4 "cc_reg_operand" "")
11710 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11711 (match_dup 0)))
11712 (set (pc)
11713 (if_then_else (match_operator 6 "equality_operator"
11714 [(match_dup 4) (const_int 0)])
11715 (match_operand 7 "" "")
11716 (match_operand 8 "" "")))]
11717 "peep2_reg_dead_p (3, operands[0])
11718 && peep2_reg_dead_p (4, operands[4])"
11719 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11720 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11721 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11723 {
11724 /* Get the constant we are comparing against, and see what it looks like
11725 when sign-extended from 16 to 32 bits. Then see what constant we could
11726 XOR with SEXTC to get the sign-extended value. */
11727 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11728 SImode,
11729 operands[1], operands[2]);
11730 HOST_WIDE_INT c = INTVAL (cnst);
11731 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11732 HOST_WIDE_INT xorv = c ^ sextc;
11734 operands[9] = GEN_INT (xorv);
11735 operands[10] = GEN_INT (sextc);
11736 })
11738 (define_insn "*cmpsi_internal2"
11739 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11740 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11741 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11742 ""
11743 "cmplw%I2 %0,%1,%b2"
11744 [(set_attr "type" "cmp")])
11746 (define_insn "*cmpdi_internal2"
11747 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11748 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11749 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11750 ""
11751 "cmpld%I2 %0,%1,%b2"
11752 [(set_attr "type" "cmp")])
11754 ;; The following two insns don't exist as single insns, but if we provide
11755 ;; them, we can swap an add and compare, which will enable us to overlap more
11756 ;; of the required delay between a compare and branch. We generate code for
11757 ;; them by splitting.
11759 (define_insn ""
11760 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11761 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11762 (match_operand:SI 2 "short_cint_operand" "i")))
11763 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11764 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11765 ""
11766 "#"
11767 [(set_attr "length" "8")])
11769 (define_insn ""
11770 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11771 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11772 (match_operand:SI 2 "u_short_cint_operand" "i")))
11773 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11774 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11775 ""
11776 "#"
11777 [(set_attr "length" "8")])
11779 (define_split
11780 [(set (match_operand:CC 3 "cc_reg_operand" "")
11781 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11782 (match_operand:SI 2 "short_cint_operand" "")))
11783 (set (match_operand:SI 0 "gpc_reg_operand" "")
11784 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11785 ""
11786 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11787 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11789 (define_split
11790 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11791 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11792 (match_operand:SI 2 "u_short_cint_operand" "")))
11793 (set (match_operand:SI 0 "gpc_reg_operand" "")
11794 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11795 ""
11796 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11797 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11799 ;; Only need to compare second words if first words equal
11800 (define_insn "*cmptf_internal1"
11801 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11802 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11803 (match_operand:TF 2 "gpc_reg_operand" "d")))]
11804 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11805 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11806 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11807 [(set_attr "type" "fpcompare")
11808 (set_attr "length" "12")])
11810 (define_insn_and_split "*cmptf_internal2"
11811 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11812 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11813 (match_operand:TF 2 "gpc_reg_operand" "d")))
11814 (clobber (match_scratch:DF 3 "=d"))
11815 (clobber (match_scratch:DF 4 "=d"))
11816 (clobber (match_scratch:DF 5 "=d"))
11817 (clobber (match_scratch:DF 6 "=d"))
11818 (clobber (match_scratch:DF 7 "=d"))
11819 (clobber (match_scratch:DF 8 "=d"))
11820 (clobber (match_scratch:DF 9 "=d"))
11821 (clobber (match_scratch:DF 10 "=d"))
11822 (clobber (match_scratch:GPR 11 "=b"))]
11823 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11824 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11825 "#"
11826 "&& reload_completed"
11827 [(set (match_dup 3) (match_dup 14))
11828 (set (match_dup 4) (match_dup 15))
11829 (set (match_dup 9) (abs:DF (match_dup 5)))
11830 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11831 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11832 (label_ref (match_dup 12))
11833 (pc)))
11834 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11835 (set (pc) (label_ref (match_dup 13)))
11836 (match_dup 12)
11837 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11838 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11839 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11840 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
11841 (match_dup 13)]
11842 {
11843 REAL_VALUE_TYPE rv;
11844 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
11845 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
11847 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11848 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11849 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11850 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11851 operands[12] = gen_label_rtx ();
11852 operands[13] = gen_label_rtx ();
11853 real_inf (&rv);
11854 operands[14] = force_const_mem (DFmode,
11855 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11856 operands[15] = force_const_mem (DFmode,
11857 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11858 DFmode));
11859 if (TARGET_TOC)
11860 {
11861 rtx tocref;
11862 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
11863 operands[14] = gen_const_mem (DFmode, tocref);
11864 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
11865 operands[15] = gen_const_mem (DFmode, tocref);
11866 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11867 set_mem_alias_set (operands[15], get_TOC_alias_set ());
11868 }
11869 })
11870 \f
11871 ;; Now we have the scc insns. We can do some combinations because of the
11872 ;; way the machine works.
11873 ;;
11874 ;; Note that this is probably faster if we can put an insn between the
11875 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11876 ;; cases the insns below which don't use an intermediate CR field will
11877 ;; be used instead.
11878 (define_insn ""
11879 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11880 (match_operator:SI 1 "scc_comparison_operator"
11881 [(match_operand 2 "cc_reg_operand" "y")
11882 (const_int 0)]))]
11883 ""
11884 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11885 [(set (attr "type")
11886 (cond [(match_test "TARGET_MFCRF")
11887 (const_string "mfcrf")
11888 ]
11889 (const_string "mfcr")))
11890 (set_attr "length" "8")])
11892 ;; Same as above, but get the GT bit.
11893 (define_insn "move_from_CR_gt_bit"
11894 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11895 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11896 "TARGET_HARD_FLOAT && !TARGET_FPRS"
11897 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
11898 [(set_attr "type" "mfcr")
11899 (set_attr "length" "8")])
11901 ;; Same as above, but get the OV/ORDERED bit.
11902 (define_insn "move_from_CR_ov_bit"
11903 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11904 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
11905 UNSPEC_MV_CR_OV))]
11906 "TARGET_ISEL"
11907 "mfcr %0\;rlwinm %0,%0,%t1,1"
11908 [(set_attr "type" "mfcr")
11909 (set_attr "length" "8")])
11911 (define_insn ""
11912 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11913 (match_operator:DI 1 "scc_comparison_operator"
11914 [(match_operand 2 "cc_reg_operand" "y")
11915 (const_int 0)]))]
11916 "TARGET_POWERPC64"
11917 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11918 [(set (attr "type")
11919 (cond [(match_test "TARGET_MFCRF")
11920 (const_string "mfcrf")
11921 ]
11922 (const_string "mfcr")))
11923 (set_attr "length" "8")])
11925 (define_insn ""
11926 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11927 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11928 [(match_operand 2 "cc_reg_operand" "y,y")
11929 (const_int 0)])
11930 (const_int 0)))
11931 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11932 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11933 "TARGET_32BIT"
11934 "@
11935 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
11936 #"
11937 [(set_attr "type" "shift")
11938 (set_attr "dot" "yes")
11939 (set_attr "length" "8,16")])
11941 (define_split
11942 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11943 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11944 [(match_operand 2 "cc_reg_operand" "")
11945 (const_int 0)])
11946 (const_int 0)))
11947 (set (match_operand:SI 3 "gpc_reg_operand" "")
11948 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11949 "TARGET_32BIT && reload_completed"
11950 [(set (match_dup 3)
11951 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11952 (set (match_dup 0)
11953 (compare:CC (match_dup 3)
11954 (const_int 0)))]
11955 "")
11957 (define_insn ""
11958 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11959 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11960 [(match_operand 2 "cc_reg_operand" "y")
11961 (const_int 0)])
11962 (match_operand:SI 3 "const_int_operand" "n")))]
11963 ""
11964 "*
11965 {
11966 int is_bit = ccr_bit (operands[1], 1);
11967 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11968 int count;
11970 if (is_bit >= put_bit)
11971 count = is_bit - put_bit;
11972 else
11973 count = 32 - (put_bit - is_bit);
11975 operands[4] = GEN_INT (count);
11976 operands[5] = GEN_INT (put_bit);
11978 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
11979 }"
11980 [(set (attr "type")
11981 (cond [(match_test "TARGET_MFCRF")
11982 (const_string "mfcrf")
11983 ]
11984 (const_string "mfcr")))
11985 (set_attr "length" "8")])
11987 (define_insn ""
11988 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11989 (compare:CC
11990 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11991 [(match_operand 2 "cc_reg_operand" "y,y")
11992 (const_int 0)])
11993 (match_operand:SI 3 "const_int_operand" "n,n"))
11994 (const_int 0)))
11995 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11996 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11997 (match_dup 3)))]
11998 ""
11999 "*
12000 {
12001 int is_bit = ccr_bit (operands[1], 1);
12002 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12003 int count;
12005 /* Force split for non-cc0 compare. */
12006 if (which_alternative == 1)
12007 return \"#\";
12009 if (is_bit >= put_bit)
12010 count = is_bit - put_bit;
12011 else
12012 count = 32 - (put_bit - is_bit);
12014 operands[5] = GEN_INT (count);
12015 operands[6] = GEN_INT (put_bit);
12017 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
12018 }"
12019 [(set_attr "type" "shift")
12020 (set_attr "dot" "yes")
12021 (set_attr "length" "8,16")])
12023 (define_split
12024 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12025 (compare:CC
12026 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12027 [(match_operand 2 "cc_reg_operand" "")
12028 (const_int 0)])
12029 (match_operand:SI 3 "const_int_operand" ""))
12030 (const_int 0)))
12031 (set (match_operand:SI 4 "gpc_reg_operand" "")
12032 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12033 (match_dup 3)))]
12034 "reload_completed"
12035 [(set (match_dup 4)
12036 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12037 (match_dup 3)))
12038 (set (match_dup 0)
12039 (compare:CC (match_dup 4)
12040 (const_int 0)))]
12041 "")
12043 ;; There is a 3 cycle delay between consecutive mfcr instructions
12044 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12046 (define_peephole
12047 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12048 (match_operator:SI 1 "scc_comparison_operator"
12049 [(match_operand 2 "cc_reg_operand" "y")
12050 (const_int 0)]))
12051 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12052 (match_operator:SI 4 "scc_comparison_operator"
12053 [(match_operand 5 "cc_reg_operand" "y")
12054 (const_int 0)]))]
12055 "REGNO (operands[2]) != REGNO (operands[5])"
12056 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
12057 [(set_attr "type" "mfcr")
12058 (set_attr "length" "12")])
12060 (define_peephole
12061 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12062 (match_operator:DI 1 "scc_comparison_operator"
12063 [(match_operand 2 "cc_reg_operand" "y")
12064 (const_int 0)]))
12065 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12066 (match_operator:DI 4 "scc_comparison_operator"
12067 [(match_operand 5 "cc_reg_operand" "y")
12068 (const_int 0)]))]
12069 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12070 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
12071 [(set_attr "type" "mfcr")
12072 (set_attr "length" "12")])
12074 ;; There are some scc insns that can be done directly, without a compare.
12075 ;; These are faster because they don't involve the communications between
12076 ;; the FXU and branch units. In fact, we will be replacing all of the
12077 ;; integer scc insns here or in the portable methods in emit_store_flag.
12078 ;;
12079 ;; Also support (neg (scc ..)) since that construct is used to replace
12080 ;; branches, (plus (scc ..) ..) since that construct is common and
12081 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12082 ;; cases where it is no more expensive than (neg (scc ..)).
12084 ;; Have reload force a constant into a register for the simple insns that
12085 ;; otherwise won't accept constants. We do this because it is faster than
12086 ;; the cmp/mfcr sequence we would otherwise generate.
12088 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12089 (DI "rKJI")])
12091 (define_insn_and_split "*eq<mode>"
12092 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12093 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12094 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12095 ""
12096 "#"
12097 ""
12098 [(set (match_dup 0)
12099 (clz:GPR (match_dup 3)))
12100 (set (match_dup 0)
12101 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12102 {
12103 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12104 {
12105 /* Use output operand as intermediate. */
12106 operands[3] = operands[0];
12108 if (logical_operand (operands[2], <MODE>mode))
12109 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12110 gen_rtx_XOR (<MODE>mode,
12111 operands[1], operands[2])));
12112 else
12113 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12114 gen_rtx_PLUS (<MODE>mode, operands[1],
12115 negate_rtx (<MODE>mode,
12116 operands[2]))));
12117 }
12118 else
12119 operands[3] = operands[1];
12121 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12122 })
12124 (define_insn_and_split "*eq<mode>_compare"
12125 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12126 (compare:CC
12127 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12128 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12129 (const_int 0)))
12130 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12131 (eq:P (match_dup 1) (match_dup 2)))]
12132 "optimize_size"
12133 "#"
12134 "optimize_size"
12135 [(set (match_dup 0)
12136 (clz:P (match_dup 4)))
12137 (parallel [(set (match_dup 3)
12138 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12139 (const_int 0)))
12140 (set (match_dup 0)
12141 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12142 {
12143 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12144 {
12145 /* Use output operand as intermediate. */
12146 operands[4] = operands[0];
12148 if (logical_operand (operands[2], <MODE>mode))
12149 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12150 gen_rtx_XOR (<MODE>mode,
12151 operands[1], operands[2])));
12152 else
12153 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12154 gen_rtx_PLUS (<MODE>mode, operands[1],
12155 negate_rtx (<MODE>mode,
12156 operands[2]))));
12157 }
12158 else
12159 operands[4] = operands[1];
12161 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12162 })
12164 ;; We have insns of the form shown by the first define_insn below. If
12165 ;; there is something inside the comparison operation, we must split it.
12166 (define_split
12167 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12168 (plus:SI (match_operator 1 "comparison_operator"
12169 [(match_operand:SI 2 "" "")
12170 (match_operand:SI 3
12171 "reg_or_cint_operand" "")])
12172 (match_operand:SI 4 "gpc_reg_operand" "")))
12173 (clobber (match_operand:SI 5 "register_operand" ""))]
12174 "! gpc_reg_operand (operands[2], SImode)"
12175 [(set (match_dup 5) (match_dup 2))
12176 (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)])
12177 (match_dup 4)))])
12179 (define_insn "*plus_eqsi"
12180 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12181 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12182 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12183 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12184 "TARGET_32BIT"
12185 "@
12186 xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3
12187 subfic %0,%1,0\;addze %0,%3
12188 xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3
12189 xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3
12190 subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3"
12191 [(set_attr "type" "three,two,three,three,three")
12192 (set_attr "length" "12,8,12,12,12")])
12194 (define_insn "*compare_plus_eqsi"
12195 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12196 (compare:CC
12197 (plus:SI
12198 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12199 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12200 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12201 (const_int 0)))
12202 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12203 "TARGET_32BIT && optimize_size"
12204 "@
12205 xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
12206 subfic %4,%1,0\;addze. %4,%3
12207 xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3
12208 xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3
12209 subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
12210 #
12211 #
12212 #
12213 #
12214 #"
12215 [(set_attr "type" "compare")
12216 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12218 (define_split
12219 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12220 (compare:CC
12221 (plus:SI
12222 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12223 (match_operand:SI 2 "scc_eq_operand" ""))
12224 (match_operand:SI 3 "gpc_reg_operand" ""))
12225 (const_int 0)))
12226 (clobber (match_scratch:SI 4 ""))]
12227 "TARGET_32BIT && optimize_size && reload_completed"
12228 [(set (match_dup 4)
12229 (plus:SI (eq:SI (match_dup 1)
12230 (match_dup 2))
12231 (match_dup 3)))
12232 (set (match_dup 0)
12233 (compare:CC (match_dup 4)
12234 (const_int 0)))]
12235 "")
12237 (define_insn "*plus_eqsi_compare"
12238 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12239 (compare:CC
12240 (plus:SI
12241 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12242 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12243 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12244 (const_int 0)))
12245 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12246 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12247 "TARGET_32BIT && optimize_size"
12248 "@
12249 xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
12250 subfic %0,%1,0\;addze. %0,%3
12251 xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3
12252 xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3
12253 subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
12254 #
12255 #
12256 #
12257 #
12258 #"
12259 [(set_attr "type" "compare")
12260 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12262 (define_split
12263 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12264 (compare:CC
12265 (plus:SI
12266 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12267 (match_operand:SI 2 "scc_eq_operand" ""))
12268 (match_operand:SI 3 "gpc_reg_operand" ""))
12269 (const_int 0)))
12270 (set (match_operand:SI 0 "gpc_reg_operand" "")
12271 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12272 "TARGET_32BIT && optimize_size && reload_completed"
12273 [(set (match_dup 0)
12274 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12275 (set (match_dup 4)
12276 (compare:CC (match_dup 0)
12277 (const_int 0)))]
12278 "")
12280 (define_insn "*neg_eq0<mode>"
12281 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12282 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12283 (const_int 0))))]
12284 ""
12285 "addic %0,%1,-1\;subfe %0,%0,%0"
12286 [(set_attr "type" "two")
12287 (set_attr "length" "8")])
12289 (define_insn_and_split "*neg_eq<mode>"
12290 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12291 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12292 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12293 ""
12294 "#"
12295 ""
12296 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12297 {
12298 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12299 {
12300 /* Use output operand as intermediate. */
12301 operands[3] = operands[0];
12303 if (logical_operand (operands[2], <MODE>mode))
12304 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12305 gen_rtx_XOR (<MODE>mode,
12306 operands[1], operands[2])));
12307 else
12308 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12309 gen_rtx_PLUS (<MODE>mode, operands[1],
12310 negate_rtx (<MODE>mode,
12311 operands[2]))));
12312 }
12313 else
12314 operands[3] = operands[1];
12315 })
12317 (define_insn "*ne0_<mode>"
12318 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12319 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12320 (const_int 0)))
12321 (clobber (match_scratch:P 2 "=&r"))]
12322 "!(TARGET_32BIT && TARGET_ISEL)"
12323 "addic %2,%1,-1\;subfe %0,%2,%1"
12324 [(set_attr "type" "two")
12325 (set_attr "length" "8")])
12327 (define_insn "*plus_ne0_<mode>"
12328 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12329 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12330 (const_int 0))
12331 (match_operand:P 2 "gpc_reg_operand" "r")))
12332 (clobber (match_scratch:P 3 "=&r"))]
12333 ""
12334 "addic %3,%1,-1\;addze %0,%2"
12335 [(set_attr "type" "two")
12336 (set_attr "length" "8")])
12338 (define_insn "*compare_plus_ne0_<mode>"
12339 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12340 (compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12341 (const_int 0))
12342 (match_operand:P 2 "gpc_reg_operand" "r,r"))
12343 (const_int 0)))
12344 (clobber (match_scratch:P 3 "=&r,&r"))
12345 (clobber (match_scratch:P 4 "=X,&r"))]
12346 ""
12347 "@
12348 addic %3,%1,-1\;addze. %3,%2
12349 #"
12350 [(set_attr "type" "compare")
12351 (set_attr "length" "8,12")])
12353 (define_split
12354 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12355 (compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
12356 (const_int 0))
12357 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
12358 (clobber (match_scratch:P 3 ""))
12359 (clobber (match_scratch:P 4 ""))]
12360 "reload_completed"
12361 [(parallel [(set (match_dup 3)
12362 (plus:P (ne:P (match_dup 1)
12363 (const_int 0))
12364 (match_dup 2)))
12365 (clobber (match_dup 4))])
12366 (set (match_dup 0)
12367 (compare:CC (match_dup 3)
12368 (const_int 0)))]
12369 "")
12371 ; For combine.
12372 (define_insn "*compare_plus_ne0_<mode>_1"
12373 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12374 (compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12375 (const_int 0))
12376 (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
12377 (clobber (match_scratch:P 3 "=&r,&r"))
12378 (clobber (match_scratch:P 4 "=X,&r"))]
12379 ""
12380 "@
12381 addic %3,%1,-1\;addze. %3,%2
12382 #"
12383 [(set_attr "type" "compare")
12384 (set_attr "length" "8,12")])
12386 (define_split
12387 [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
12388 (compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
12389 (const_int 0))
12390 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
12391 (clobber (match_scratch:P 3 ""))
12392 (clobber (match_scratch:P 4 ""))]
12393 "reload_completed"
12394 [(parallel [(set (match_dup 3)
12395 (plus:P (ne:P (match_dup 1)
12396 (const_int 0))
12397 (match_dup 2)))
12398 (clobber (match_dup 4))])
12399 (set (match_dup 0)
12400 (compare:CC (match_dup 3)
12401 (const_int 0)))]
12402 "")
12404 (define_insn "*plus_ne0_<mode>_compare"
12405 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12406 (compare:CC
12407 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12408 (const_int 0))
12409 (match_operand:P 2 "gpc_reg_operand" "r,r"))
12410 (const_int 0)))
12411 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12412 (plus:P (ne:P (match_dup 1)
12413 (const_int 0))
12414 (match_dup 2)))
12415 (clobber (match_scratch:P 3 "=&r,&r"))]
12416 ""
12417 "@
12418 addic %3,%1,-1\;addze. %0,%2
12419 #"
12420 [(set_attr "type" "compare")
12421 (set_attr "length" "8,12")])
12423 (define_split
12424 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
12425 (compare:CC
12426 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "")
12427 (const_int 0))
12428 (match_operand:P 2 "gpc_reg_operand" ""))
12429 (const_int 0)))
12430 (set (match_operand:P 0 "gpc_reg_operand" "")
12431 (plus:P (ne:P (match_dup 1)
12432 (const_int 0))
12433 (match_dup 2)))
12434 (clobber (match_scratch:P 3 ""))]
12435 "reload_completed"
12436 [(parallel [(set (match_dup 0)
12437 (plus:P (ne:P (match_dup 1)
12438 (const_int 0))
12439 (match_dup 2)))
12440 (clobber (match_dup 3))])
12441 (set (match_dup 4)
12442 (compare:CC (match_dup 0)
12443 (const_int 0)))]
12444 "")
12446 (define_insn "*leu<mode>"
12447 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12448 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12449 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12450 ""
12451 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12452 [(set_attr "type" "three")
12453 (set_attr "length" "12")])
12455 (define_insn "*leu<mode>_compare"
12456 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12457 (compare:CC
12458 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12459 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12460 (const_int 0)))
12461 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12462 (leu:P (match_dup 1) (match_dup 2)))]
12463 ""
12464 "@
12465 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12466 #"
12467 [(set_attr "type" "compare")
12468 (set_attr "length" "12,16")])
12470 (define_split
12471 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12472 (compare:CC
12473 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12474 (match_operand:P 2 "reg_or_short_operand" ""))
12475 (const_int 0)))
12476 (set (match_operand:P 0 "gpc_reg_operand" "")
12477 (leu:P (match_dup 1) (match_dup 2)))]
12478 "reload_completed"
12479 [(set (match_dup 0)
12480 (leu:P (match_dup 1) (match_dup 2)))
12481 (set (match_dup 3)
12482 (compare:CC (match_dup 0)
12483 (const_int 0)))]
12484 "")
12486 (define_insn "*plus_leu<mode>"
12487 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12488 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12489 (match_operand:P 2 "reg_or_short_operand" "rI"))
12490 (match_operand:P 3 "gpc_reg_operand" "r")))]
12491 ""
12492 "subf%I2c %0,%1,%2\;addze %0,%3"
12493 [(set_attr "type" "two")
12494 (set_attr "length" "8")])
12496 (define_insn ""
12497 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12498 (compare:CC
12499 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12500 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12501 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12502 (const_int 0)))
12503 (clobber (match_scratch:SI 4 "=&r,&r"))]
12504 "TARGET_32BIT"
12505 "@
12506 subf%I2c %4,%1,%2\;addze. %4,%3
12507 #"
12508 [(set_attr "type" "compare")
12509 (set_attr "length" "8,12")])
12511 (define_split
12512 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12513 (compare:CC
12514 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12515 (match_operand:SI 2 "reg_or_short_operand" ""))
12516 (match_operand:SI 3 "gpc_reg_operand" ""))
12517 (const_int 0)))
12518 (clobber (match_scratch:SI 4 ""))]
12519 "TARGET_32BIT && reload_completed"
12520 [(set (match_dup 4)
12521 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12522 (match_dup 3)))
12523 (set (match_dup 0)
12524 (compare:CC (match_dup 4)
12525 (const_int 0)))]
12526 "")
12528 (define_insn ""
12529 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12530 (compare:CC
12531 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12532 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12533 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12534 (const_int 0)))
12535 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12536 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12537 "TARGET_32BIT"
12538 "@
12539 subf%I2c %0,%1,%2\;addze. %0,%3
12540 #"
12541 [(set_attr "type" "compare")
12542 (set_attr "length" "8,12")])
12544 (define_split
12545 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12546 (compare:CC
12547 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12548 (match_operand:SI 2 "reg_or_short_operand" ""))
12549 (match_operand:SI 3 "gpc_reg_operand" ""))
12550 (const_int 0)))
12551 (set (match_operand:SI 0 "gpc_reg_operand" "")
12552 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12553 "TARGET_32BIT && reload_completed"
12554 [(set (match_dup 0)
12555 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12556 (set (match_dup 4)
12557 (compare:CC (match_dup 0)
12558 (const_int 0)))]
12559 "")
12561 (define_insn "*neg_leu<mode>"
12562 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12563 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12564 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12565 ""
12566 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0"
12567 [(set_attr "type" "three")
12568 (set_attr "length" "12")])
12570 (define_insn "*and_neg_leu<mode>"
12571 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12572 (and:P (neg:P
12573 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12574 (match_operand:P 2 "reg_or_short_operand" "rI")))
12575 (match_operand:P 3 "gpc_reg_operand" "r")))]
12576 ""
12577 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0"
12578 [(set_attr "type" "three")
12579 (set_attr "length" "12")])
12581 (define_insn ""
12582 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12583 (compare:CC
12584 (and:SI (neg:SI
12585 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12586 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12587 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12588 (const_int 0)))
12589 (clobber (match_scratch:SI 4 "=&r,&r"))]
12590 "TARGET_32BIT"
12591 "@
12592 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4
12593 #"
12594 [(set_attr "type" "compare")
12595 (set_attr "length" "12,16")])
12597 (define_split
12598 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12599 (compare:CC
12600 (and:SI (neg:SI
12601 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12602 (match_operand:SI 2 "reg_or_short_operand" "")))
12603 (match_operand:SI 3 "gpc_reg_operand" ""))
12604 (const_int 0)))
12605 (clobber (match_scratch:SI 4 ""))]
12606 "TARGET_32BIT && reload_completed"
12607 [(set (match_dup 4)
12608 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12609 (match_dup 3)))
12610 (set (match_dup 0)
12611 (compare:CC (match_dup 4)
12612 (const_int 0)))]
12613 "")
12615 (define_insn ""
12616 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12617 (compare:CC
12618 (and:SI (neg:SI
12619 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12620 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12621 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12622 (const_int 0)))
12623 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12624 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12625 "TARGET_32BIT"
12626 "@
12627 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0
12628 #"
12629 [(set_attr "type" "compare")
12630 (set_attr "length" "12,16")])
12632 (define_split
12633 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12634 (compare:CC
12635 (and:SI (neg:SI
12636 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12637 (match_operand:SI 2 "reg_or_short_operand" "")))
12638 (match_operand:SI 3 "gpc_reg_operand" ""))
12639 (const_int 0)))
12640 (set (match_operand:SI 0 "gpc_reg_operand" "")
12641 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12642 "TARGET_32BIT && reload_completed"
12643 [(set (match_dup 0)
12644 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12645 (match_dup 3)))
12646 (set (match_dup 4)
12647 (compare:CC (match_dup 0)
12648 (const_int 0)))]
12649 "")
12651 (define_insn_and_split "*ltu<mode>"
12652 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12653 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12654 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12655 ""
12656 "#"
12657 ""
12658 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12659 (set (match_dup 0) (neg:P (match_dup 0)))]
12660 "")
12662 (define_insn_and_split "*ltu<mode>_compare"
12663 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12664 (compare:CC
12665 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12666 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12667 (const_int 0)))
12668 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12669 (ltu:P (match_dup 1) (match_dup 2)))]
12670 ""
12671 "#"
12672 ""
12673 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12674 (parallel [(set (match_dup 3)
12675 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12676 (set (match_dup 0) (neg:P (match_dup 0)))])]
12677 "")
12679 (define_insn_and_split "*plus_ltu<mode>"
12680 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12681 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12682 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12683 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
12684 ""
12685 "#"
12686 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12687 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12688 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12689 "")
12691 (define_insn_and_split "*plus_ltu<mode>_compare"
12692 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12693 (compare:CC
12694 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12695 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12696 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12697 (const_int 0)))
12698 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12699 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12700 ""
12701 "#"
12702 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12703 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12704 (parallel [(set (match_dup 4)
12705 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12706 (const_int 0)))
12707 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12708 "")
12710 (define_insn "*neg_ltu<mode>"
12711 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12712 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12713 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12714 ""
12715 "@
12716 subfc %0,%2,%1\;subfe %0,%0,%0
12717 addic %0,%1,%n2\;subfe %0,%0,%0"
12718 [(set_attr "type" "two")
12719 (set_attr "length" "8")])
12721 (define_insn "*geu<mode>"
12722 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12723 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12724 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12725 ""
12726 "@
12727 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12728 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12729 [(set_attr "type" "three")
12730 (set_attr "length" "12")])
12732 (define_insn "*geu<mode>_compare"
12733 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12734 (compare:CC
12735 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12736 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12737 (const_int 0)))
12738 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12739 (geu:P (match_dup 1) (match_dup 2)))]
12740 ""
12741 "@
12742 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12743 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12744 #
12745 #"
12746 [(set_attr "type" "compare")
12747 (set_attr "length" "12,12,16,16")])
12749 (define_split
12750 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
12751 (compare:CC
12752 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
12753 (match_operand:P 2 "reg_or_neg_short_operand" ""))
12754 (const_int 0)))
12755 (set (match_operand:P 0 "gpc_reg_operand" "")
12756 (geu:P (match_dup 1) (match_dup 2)))]
12757 "reload_completed"
12758 [(set (match_dup 0)
12759 (geu:P (match_dup 1) (match_dup 2)))
12760 (set (match_dup 3)
12761 (compare:CC (match_dup 0)
12762 (const_int 0)))]
12763 "")
12765 (define_insn "*plus_geu<mode>"
12766 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12767 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12768 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12769 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12770 ""
12771 "@
12772 subfc %0,%2,%1\;addze %0,%3
12773 addic %0,%1,%n2\;addze %0,%3"
12774 [(set_attr "type" "two")
12775 (set_attr "length" "8")])
12777 (define_insn ""
12778 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12779 (compare:CC
12780 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12781 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12782 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12783 (const_int 0)))
12784 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12785 "TARGET_32BIT"
12786 "@
12787 subfc %4,%2,%1\;addze. %4,%3
12788 addic %4,%1,%n2\;addze. %4,%3
12789 #
12790 #"
12791 [(set_attr "type" "compare")
12792 (set_attr "length" "8,8,12,12")])
12794 (define_split
12795 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12796 (compare:CC
12797 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12798 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12799 (match_operand:SI 3 "gpc_reg_operand" ""))
12800 (const_int 0)))
12801 (clobber (match_scratch:SI 4 ""))]
12802 "TARGET_32BIT && reload_completed"
12803 [(set (match_dup 4)
12804 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12805 (match_dup 3)))
12806 (set (match_dup 0)
12807 (compare:CC (match_dup 4)
12808 (const_int 0)))]
12809 "")
12811 (define_insn ""
12812 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12813 (compare:CC
12814 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12815 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12816 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12817 (const_int 0)))
12818 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12819 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12820 "TARGET_32BIT"
12821 "@
12822 subfc %0,%2,%1\;addze. %0,%3
12823 addic %0,%1,%n2\;addze. %0,%3
12824 #
12825 #"
12826 [(set_attr "type" "compare")
12827 (set_attr "length" "8,8,12,12")])
12829 (define_split
12830 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12831 (compare:CC
12832 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12833 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12834 (match_operand:SI 3 "gpc_reg_operand" ""))
12835 (const_int 0)))
12836 (set (match_operand:SI 0 "gpc_reg_operand" "")
12837 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12838 "TARGET_32BIT && reload_completed"
12839 [(set (match_dup 0)
12840 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12841 (set (match_dup 4)
12842 (compare:CC (match_dup 0)
12843 (const_int 0)))]
12844 "")
12846 (define_insn "*neg_geu<mode>"
12847 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12848 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12849 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
12850 ""
12851 "@
12852 subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0
12853 subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0"
12854 [(set_attr "type" "three")
12855 (set_attr "length" "12")])
12857 (define_insn "*and_neg_geu<mode>"
12858 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12859 (and:P (neg:P
12860 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12861 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
12862 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12863 ""
12864 "@
12865 subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0
12866 addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0"
12867 [(set_attr "type" "three")
12868 (set_attr "length" "12")])
12870 (define_insn ""
12871 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12872 (compare:CC
12873 (and:SI (neg:SI
12874 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12875 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12876 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12877 (const_int 0)))
12878 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12879 "TARGET_32BIT"
12880 "@
12881 subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4
12882 addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4
12883 #
12884 #"
12885 [(set_attr "type" "compare")
12886 (set_attr "length" "12,12,16,16")])
12888 (define_split
12889 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12890 (compare:CC
12891 (and:SI (neg:SI
12892 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12893 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12894 (match_operand:SI 3 "gpc_reg_operand" ""))
12895 (const_int 0)))
12896 (clobber (match_scratch:SI 4 ""))]
12897 "TARGET_32BIT && reload_completed"
12898 [(set (match_dup 4)
12899 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12900 (match_dup 3)))
12901 (set (match_dup 0)
12902 (compare:CC (match_dup 4)
12903 (const_int 0)))]
12904 "")
12906 (define_insn ""
12907 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12908 (compare:CC
12909 (and:SI (neg:SI
12910 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12911 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12912 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12913 (const_int 0)))
12914 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12915 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12916 "TARGET_32BIT"
12917 "@
12918 subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0
12919 addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0
12920 #
12921 #"
12922 [(set_attr "type" "compare")
12923 (set_attr "length" "12,12,16,16")])
12925 (define_split
12926 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12927 (compare:CC
12928 (and:SI (neg:SI
12929 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12930 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12931 (match_operand:SI 3 "gpc_reg_operand" ""))
12932 (const_int 0)))
12933 (set (match_operand:SI 0 "gpc_reg_operand" "")
12934 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12935 "TARGET_32BIT && reload_completed"
12936 [(set (match_dup 0)
12937 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12938 (set (match_dup 4)
12939 (compare:CC (match_dup 0)
12940 (const_int 0)))]
12941 "")
12943 (define_insn "*plus_gt0<mode>"
12944 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12945 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
12946 (const_int 0))
12947 (match_operand:P 2 "gpc_reg_operand" "r")))]
12948 ""
12949 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
12950 [(set_attr "type" "three")
12951 (set_attr "length" "12")])
12953 (define_insn ""
12954 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12955 (compare:CC
12956 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12957 (const_int 0))
12958 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12959 (const_int 0)))
12960 (clobber (match_scratch:SI 3 "=&r,&r"))]
12961 "TARGET_32BIT"
12962 "@
12963 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12964 #"
12965 [(set_attr "type" "compare")
12966 (set_attr "length" "12,16")])
12968 (define_split
12969 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12970 (compare:CC
12971 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12972 (const_int 0))
12973 (match_operand:SI 2 "gpc_reg_operand" ""))
12974 (const_int 0)))
12975 (clobber (match_scratch:SI 3 ""))]
12976 "TARGET_32BIT && reload_completed"
12977 [(set (match_dup 3)
12978 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12979 (match_dup 2)))
12980 (set (match_dup 0)
12981 (compare:CC (match_dup 3)
12982 (const_int 0)))]
12983 "")
12985 (define_insn ""
12986 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12987 (compare:CC
12988 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12989 (const_int 0))
12990 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12991 (const_int 0)))
12992 (clobber (match_scratch:DI 3 "=&r,&r"))]
12993 "TARGET_64BIT"
12994 "@
12995 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12996 #"
12997 [(set_attr "type" "compare")
12998 (set_attr "length" "12,16")])
13000 (define_split
13001 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13002 (compare:CC
13003 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13004 (const_int 0))
13005 (match_operand:DI 2 "gpc_reg_operand" ""))
13006 (const_int 0)))
13007 (clobber (match_scratch:DI 3 ""))]
13008 "TARGET_64BIT && reload_completed"
13009 [(set (match_dup 3)
13010 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13011 (match_dup 2)))
13012 (set (match_dup 0)
13013 (compare:CC (match_dup 3)
13014 (const_int 0)))]
13015 "")
13017 (define_insn ""
13018 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13019 (compare:CC
13020 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13021 (const_int 0))
13022 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13023 (const_int 0)))
13024 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13025 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13026 "TARGET_32BIT"
13027 "@
13028 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13029 #"
13030 [(set_attr "type" "compare")
13031 (set_attr "length" "12,16")])
13033 (define_split
13034 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13035 (compare:CC
13036 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13037 (const_int 0))
13038 (match_operand:SI 2 "gpc_reg_operand" ""))
13039 (const_int 0)))
13040 (set (match_operand:SI 0 "gpc_reg_operand" "")
13041 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13042 "TARGET_32BIT && reload_completed"
13043 [(set (match_dup 0)
13044 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13045 (set (match_dup 3)
13046 (compare:CC (match_dup 0)
13047 (const_int 0)))]
13048 "")
13050 (define_insn ""
13051 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13052 (compare:CC
13053 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13054 (const_int 0))
13055 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13056 (const_int 0)))
13057 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13058 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13059 "TARGET_64BIT"
13060 "@
13061 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13062 #"
13063 [(set_attr "type" "compare")
13064 (set_attr "length" "12,16")])
13066 (define_split
13067 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
13068 (compare:CC
13069 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13070 (const_int 0))
13071 (match_operand:DI 2 "gpc_reg_operand" ""))
13072 (const_int 0)))
13073 (set (match_operand:DI 0 "gpc_reg_operand" "")
13074 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13075 "TARGET_64BIT && reload_completed"
13076 [(set (match_dup 0)
13077 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13078 (set (match_dup 3)
13079 (compare:CC (match_dup 0)
13080 (const_int 0)))]
13081 "")
13083 (define_insn_and_split "*gtu<mode>"
13084 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13085 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13086 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13087 ""
13088 "#"
13089 ""
13090 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13091 (set (match_dup 0) (neg:P (match_dup 0)))]
13092 "")
13094 (define_insn_and_split "*gtu<mode>_compare"
13095 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13096 (compare:CC
13097 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13098 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13099 (const_int 0)))
13100 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13101 (gtu:P (match_dup 1) (match_dup 2)))]
13102 ""
13103 "#"
13104 ""
13105 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13106 (parallel [(set (match_dup 3)
13107 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13108 (set (match_dup 0) (neg:P (match_dup 0)))])]
13109 "")
13111 (define_insn_and_split "*plus_gtu<mode>"
13112 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13113 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13114 (match_operand:P 2 "reg_or_short_operand" "rI"))
13115 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13116 ""
13117 "#"
13118 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13119 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13120 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13121 "")
13123 (define_insn_and_split "*plus_gtu<mode>_compare"
13124 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13125 (compare:CC
13126 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13127 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13128 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13129 (const_int 0)))
13130 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13131 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13132 ""
13133 "#"
13134 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13135 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13136 (parallel [(set (match_dup 4)
13137 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13138 (const_int 0)))
13139 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13140 "")
13142 (define_insn "*neg_gtu<mode>"
13143 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13144 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13145 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13146 ""
13147 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13148 [(set_attr "type" "two")
13149 (set_attr "length" "8")])
13151 \f
13152 ;; Define both directions of branch and return. If we need a reload
13153 ;; register, we'd rather use CR0 since it is much easier to copy a
13154 ;; register CC value to there.
13156 (define_insn ""
13157 [(set (pc)
13158 (if_then_else (match_operator 1 "branch_comparison_operator"
13159 [(match_operand 2
13160 "cc_reg_operand" "y")
13161 (const_int 0)])
13162 (label_ref (match_operand 0 "" ""))
13163 (pc)))]
13164 ""
13165 "*
13166 {
13167 return output_cbranch (operands[1], \"%l0\", 0, insn);
13168 }"
13169 [(set_attr "type" "branch")])
13171 (define_insn ""
13172 [(set (pc)
13173 (if_then_else (match_operator 0 "branch_comparison_operator"
13174 [(match_operand 1
13175 "cc_reg_operand" "y")
13176 (const_int 0)])
13177 (any_return)
13178 (pc)))]
13179 "<return_pred>"
13180 "*
13181 {
13182 return output_cbranch (operands[0], NULL, 0, insn);
13183 }"
13184 [(set_attr "type" "jmpreg")
13185 (set_attr "length" "4")])
13187 (define_insn ""
13188 [(set (pc)
13189 (if_then_else (match_operator 1 "branch_comparison_operator"
13190 [(match_operand 2
13191 "cc_reg_operand" "y")
13192 (const_int 0)])
13193 (pc)
13194 (label_ref (match_operand 0 "" ""))))]
13195 ""
13196 "*
13197 {
13198 return output_cbranch (operands[1], \"%l0\", 1, insn);
13199 }"
13200 [(set_attr "type" "branch")])
13202 (define_insn ""
13203 [(set (pc)
13204 (if_then_else (match_operator 0 "branch_comparison_operator"
13205 [(match_operand 1
13206 "cc_reg_operand" "y")
13207 (const_int 0)])
13208 (pc)
13209 (any_return)))]
13210 "<return_pred>"
13211 "*
13212 {
13213 return output_cbranch (operands[0], NULL, 1, insn);
13214 }"
13215 [(set_attr "type" "jmpreg")
13216 (set_attr "length" "4")])
13218 ;; Logic on condition register values.
13220 ; This pattern matches things like
13221 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13222 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13223 ; (const_int 1)))
13224 ; which are generated by the branch logic.
13225 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13227 (define_insn "*cceq_ior_compare"
13228 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13229 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13230 [(match_operator:SI 2
13231 "branch_positive_comparison_operator"
13232 [(match_operand 3
13233 "cc_reg_operand" "y,y")
13234 (const_int 0)])
13235 (match_operator:SI 4
13236 "branch_positive_comparison_operator"
13237 [(match_operand 5
13238 "cc_reg_operand" "0,y")
13239 (const_int 0)])])
13240 (const_int 1)))]
13241 ""
13242 "cr%q1 %E0,%j2,%j4"
13243 [(set_attr "type" "cr_logical,delayed_cr")])
13245 ; Why is the constant -1 here, but 1 in the previous pattern?
13246 ; Because ~1 has all but the low bit set.
13247 (define_insn ""
13248 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13249 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13250 [(not:SI (match_operator:SI 2
13251 "branch_positive_comparison_operator"
13252 [(match_operand 3
13253 "cc_reg_operand" "y,y")
13254 (const_int 0)]))
13255 (match_operator:SI 4
13256 "branch_positive_comparison_operator"
13257 [(match_operand 5
13258 "cc_reg_operand" "0,y")
13259 (const_int 0)])])
13260 (const_int -1)))]
13261 ""
13262 "cr%q1 %E0,%j2,%j4"
13263 [(set_attr "type" "cr_logical,delayed_cr")])
13265 (define_insn "*cceq_rev_compare"
13266 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13267 (compare:CCEQ (match_operator:SI 1
13268 "branch_positive_comparison_operator"
13269 [(match_operand 2
13270 "cc_reg_operand" "0,y")
13271 (const_int 0)])
13272 (const_int 0)))]
13273 ""
13274 "crnot %E0,%j1"
13275 [(set_attr "type" "cr_logical,delayed_cr")])
13277 ;; If we are comparing the result of two comparisons, this can be done
13278 ;; using creqv or crxor.
13280 (define_insn_and_split ""
13281 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13282 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13283 [(match_operand 2 "cc_reg_operand" "y")
13284 (const_int 0)])
13285 (match_operator 3 "branch_comparison_operator"
13286 [(match_operand 4 "cc_reg_operand" "y")
13287 (const_int 0)])))]
13288 ""
13289 "#"
13290 ""
13291 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13292 (match_dup 5)))]
13293 "
13294 {
13295 int positive_1, positive_2;
13297 positive_1 = branch_positive_comparison_operator (operands[1],
13298 GET_MODE (operands[1]));
13299 positive_2 = branch_positive_comparison_operator (operands[3],
13300 GET_MODE (operands[3]));
13302 if (! positive_1)
13303 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13304 GET_CODE (operands[1])),
13305 SImode,
13306 operands[2], const0_rtx);
13307 else if (GET_MODE (operands[1]) != SImode)
13308 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13309 operands[2], const0_rtx);
13311 if (! positive_2)
13312 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13313 GET_CODE (operands[3])),
13314 SImode,
13315 operands[4], const0_rtx);
13316 else if (GET_MODE (operands[3]) != SImode)
13317 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13318 operands[4], const0_rtx);
13320 if (positive_1 == positive_2)
13321 {
13322 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13323 operands[5] = constm1_rtx;
13324 }
13325 else
13326 {
13327 operands[5] = const1_rtx;
13328 }
13329 }")
13331 ;; Unconditional branch and return.
13333 (define_insn "jump"
13334 [(set (pc)
13335 (label_ref (match_operand 0 "" "")))]
13336 ""
13337 "b %l0"
13338 [(set_attr "type" "branch")])
13340 (define_insn "<return_str>return"
13341 [(any_return)]
13342 "<return_pred>"
13343 "blr"
13344 [(set_attr "type" "jmpreg")])
13346 (define_expand "indirect_jump"
13347 [(set (pc) (match_operand 0 "register_operand" ""))])
13349 (define_insn "*indirect_jump<mode>"
13350 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13351 ""
13352 "@
13353 bctr
13354 blr"
13355 [(set_attr "type" "jmpreg")])
13357 ;; Table jump for switch statements:
13358 (define_expand "tablejump"
13359 [(use (match_operand 0 "" ""))
13360 (use (label_ref (match_operand 1 "" "")))]
13361 ""
13362 "
13363 {
13364 if (TARGET_32BIT)
13365 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13366 else
13367 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13368 DONE;
13369 }")
13371 (define_expand "tablejumpsi"
13372 [(set (match_dup 3)
13373 (plus:SI (match_operand:SI 0 "" "")
13374 (match_dup 2)))
13375 (parallel [(set (pc) (match_dup 3))
13376 (use (label_ref (match_operand 1 "" "")))])]
13377 "TARGET_32BIT"
13378 "
13379 { operands[0] = force_reg (SImode, operands[0]);
13380 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13381 operands[3] = gen_reg_rtx (SImode);
13382 }")
13384 (define_expand "tablejumpdi"
13385 [(set (match_dup 4)
13386 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
13387 (set (match_dup 3)
13388 (plus:DI (match_dup 4)
13389 (match_dup 2)))
13390 (parallel [(set (pc) (match_dup 3))
13391 (use (label_ref (match_operand 1 "" "")))])]
13392 "TARGET_64BIT"
13393 "
13394 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13395 operands[3] = gen_reg_rtx (DImode);
13396 operands[4] = gen_reg_rtx (DImode);
13397 }")
13399 (define_insn "*tablejump<mode>_internal1"
13400 [(set (pc)
13401 (match_operand:P 0 "register_operand" "c,*l"))
13402 (use (label_ref (match_operand 1 "" "")))]
13403 ""
13404 "@
13405 bctr
13406 blr"
13407 [(set_attr "type" "jmpreg")])
13409 (define_insn "nop"
13410 [(const_int 0)]
13411 ""
13412 "nop")
13414 (define_insn "group_ending_nop"
13415 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
13416 ""
13417 "*
13418 {
13419 if (rs6000_cpu_attr == CPU_POWER6)
13420 return \"ori 1,1,0\";
13421 return \"ori 2,2,0\";
13422 }")
13423 \f
13424 ;; Define the subtract-one-and-jump insns, starting with the template
13425 ;; so loop.c knows what to generate.
13427 (define_expand "doloop_end"
13428 [(use (match_operand 0 "" "")) ; loop pseudo
13429 (use (match_operand 1 "" ""))] ; label
13430 ""
13431 "
13432 {
13433 if (TARGET_64BIT)
13434 {
13435 if (GET_MODE (operands[0]) != DImode)
13436 FAIL;
13437 emit_jump_insn (gen_ctrdi (operands[0], operands[1]));
13438 }
13439 else
13440 {
13441 if (GET_MODE (operands[0]) != SImode)
13442 FAIL;
13443 emit_jump_insn (gen_ctrsi (operands[0], operands[1]));
13444 }
13445 DONE;
13446 }")
13448 (define_expand "ctr<mode>"
13449 [(parallel [(set (pc)
13450 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13451 (const_int 1))
13452 (label_ref (match_operand 1 "" ""))
13453 (pc)))
13454 (set (match_dup 0)
13455 (plus:P (match_dup 0)
13456 (const_int -1)))
13457 (clobber (match_scratch:CC 2 ""))
13458 (clobber (match_scratch:P 3 ""))])]
13459 ""
13460 "")
13462 ;; We need to be able to do this for any operand, including MEM, or we
13463 ;; will cause reload to blow up since we don't allow output reloads on
13464 ;; JUMP_INSNs.
13465 ;; For the length attribute to be calculated correctly, the
13466 ;; label MUST be operand 0.
13468 (define_insn "*ctr<mode>_internal1"
13469 [(set (pc)
13470 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13471 (const_int 1))
13472 (label_ref (match_operand 0 "" ""))
13473 (pc)))
13474 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13475 (plus:P (match_dup 1)
13476 (const_int -1)))
13477 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13478 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13479 ""
13480 "*
13481 {
13482 if (which_alternative != 0)
13483 return \"#\";
13484 else if (get_attr_length (insn) == 4)
13485 return \"bdnz %l0\";
13486 else
13487 return \"bdz $+8\;b %l0\";
13488 }"
13489 [(set_attr "type" "branch")
13490 (set_attr "length" "*,12,16,16")])
13492 (define_insn "*ctr<mode>_internal2"
13493 [(set (pc)
13494 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13495 (const_int 1))
13496 (pc)
13497 (label_ref (match_operand 0 "" ""))))
13498 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13499 (plus:P (match_dup 1)
13500 (const_int -1)))
13501 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13502 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13503 ""
13504 "*
13505 {
13506 if (which_alternative != 0)
13507 return \"#\";
13508 else if (get_attr_length (insn) == 4)
13509 return \"bdz %l0\";
13510 else
13511 return \"bdnz $+8\;b %l0\";
13512 }"
13513 [(set_attr "type" "branch")
13514 (set_attr "length" "*,12,16,16")])
13516 ;; Similar but use EQ
13518 (define_insn "*ctr<mode>_internal5"
13519 [(set (pc)
13520 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13521 (const_int 1))
13522 (label_ref (match_operand 0 "" ""))
13523 (pc)))
13524 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13525 (plus:P (match_dup 1)
13526 (const_int -1)))
13527 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13528 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13529 ""
13530 "*
13531 {
13532 if (which_alternative != 0)
13533 return \"#\";
13534 else if (get_attr_length (insn) == 4)
13535 return \"bdz %l0\";
13536 else
13537 return \"bdnz $+8\;b %l0\";
13538 }"
13539 [(set_attr "type" "branch")
13540 (set_attr "length" "*,12,16,16")])
13542 (define_insn "*ctr<mode>_internal6"
13543 [(set (pc)
13544 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13545 (const_int 1))
13546 (pc)
13547 (label_ref (match_operand 0 "" ""))))
13548 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13549 (plus:P (match_dup 1)
13550 (const_int -1)))
13551 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13552 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13553 ""
13554 "*
13555 {
13556 if (which_alternative != 0)
13557 return \"#\";
13558 else if (get_attr_length (insn) == 4)
13559 return \"bdnz %l0\";
13560 else
13561 return \"bdz $+8\;b %l0\";
13562 }"
13563 [(set_attr "type" "branch")
13564 (set_attr "length" "*,12,16,16")])
13566 ;; Now the splitters if we could not allocate the CTR register
13568 (define_split
13569 [(set (pc)
13570 (if_then_else (match_operator 2 "comparison_operator"
13571 [(match_operand:P 1 "gpc_reg_operand" "")
13572 (const_int 1)])
13573 (match_operand 5 "" "")
13574 (match_operand 6 "" "")))
13575 (set (match_operand:P 0 "gpc_reg_operand" "")
13576 (plus:P (match_dup 1) (const_int -1)))
13577 (clobber (match_scratch:CC 3 ""))
13578 (clobber (match_scratch:P 4 ""))]
13579 "reload_completed"
13580 [(parallel [(set (match_dup 3)
13581 (compare:CC (plus:P (match_dup 1)
13582 (const_int -1))
13583 (const_int 0)))
13584 (set (match_dup 0)
13585 (plus:P (match_dup 1)
13586 (const_int -1)))])
13587 (set (pc) (if_then_else (match_dup 7)
13588 (match_dup 5)
13589 (match_dup 6)))]
13590 "
13591 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13592 operands[3], const0_rtx); }")
13594 (define_split
13595 [(set (pc)
13596 (if_then_else (match_operator 2 "comparison_operator"
13597 [(match_operand:P 1 "gpc_reg_operand" "")
13598 (const_int 1)])
13599 (match_operand 5 "" "")
13600 (match_operand 6 "" "")))
13601 (set (match_operand:P 0 "nonimmediate_operand" "")
13602 (plus:P (match_dup 1) (const_int -1)))
13603 (clobber (match_scratch:CC 3 ""))
13604 (clobber (match_scratch:P 4 ""))]
13605 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13606 [(parallel [(set (match_dup 3)
13607 (compare:CC (plus:P (match_dup 1)
13608 (const_int -1))
13609 (const_int 0)))
13610 (set (match_dup 4)
13611 (plus:P (match_dup 1)
13612 (const_int -1)))])
13613 (set (match_dup 0)
13614 (match_dup 4))
13615 (set (pc) (if_then_else (match_dup 7)
13616 (match_dup 5)
13617 (match_dup 6)))]
13618 "
13619 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13620 operands[3], const0_rtx); }")
13621 \f
13622 (define_insn "trap"
13623 [(trap_if (const_int 1) (const_int 0))]
13624 ""
13625 "trap"
13626 [(set_attr "type" "trap")])
13628 (define_expand "ctrap<mode>4"
13629 [(trap_if (match_operator 0 "ordered_comparison_operator"
13630 [(match_operand:GPR 1 "register_operand")
13631 (match_operand:GPR 2 "reg_or_short_operand")])
13632 (match_operand 3 "zero_constant" ""))]
13633 ""
13634 "")
13636 (define_insn ""
13637 [(trap_if (match_operator 0 "ordered_comparison_operator"
13638 [(match_operand:GPR 1 "register_operand" "r")
13639 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13640 (const_int 0))]
13641 ""
13642 "t<wd>%V0%I2 %1,%2"
13643 [(set_attr "type" "trap")])
13644 \f
13645 ;; Insns related to generating the function prologue and epilogue.
13647 (define_expand "prologue"
13648 [(use (const_int 0))]
13649 ""
13650 {
13651 rs6000_emit_prologue ();
13652 if (!TARGET_SCHED_PROLOG)
13653 emit_insn (gen_blockage ());
13654 DONE;
13655 })
13657 (define_insn "*movesi_from_cr_one"
13658 [(match_parallel 0 "mfcr_operation"
13659 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13660 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13661 (match_operand 3 "immediate_operand" "n")]
13662 UNSPEC_MOVESI_FROM_CR))])]
13663 "TARGET_MFCRF"
13664 "*
13665 {
13666 int mask = 0;
13667 int i;
13668 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13669 {
13670 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13671 operands[4] = GEN_INT (mask);
13672 output_asm_insn (\"mfcr %1,%4\", operands);
13673 }
13674 return \"\";
13675 }"
13676 [(set_attr "type" "mfcrf")])
13678 (define_insn "movesi_from_cr"
13679 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13680 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
13681 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
13682 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
13683 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
13684 UNSPEC_MOVESI_FROM_CR))]
13685 ""
13686 "mfcr %0"
13687 [(set_attr "type" "mfcr")])
13689 (define_insn "*crsave"
13690 [(match_parallel 0 "crsave_operation"
13691 [(set (match_operand:SI 1 "memory_operand" "=m")
13692 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13693 ""
13694 "stw %2,%1"
13695 [(set_attr "type" "store")])
13697 (define_insn "*stmw"
13698 [(match_parallel 0 "stmw_operation"
13699 [(set (match_operand:SI 1 "memory_operand" "=m")
13700 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13701 "TARGET_MULTIPLE"
13702 "stmw %2,%1"
13703 [(set_attr "type" "store")
13704 (set_attr "update" "yes")
13705 (set_attr "indexed" "yes")])
13707 ; The following comment applies to:
13708 ; save_gpregs_*
13709 ; save_fpregs_*
13710 ; restore_gpregs*
13711 ; return_and_restore_gpregs*
13712 ; return_and_restore_fpregs*
13713 ; return_and_restore_fpregs_aix*
13714 ;
13715 ; The out-of-line save / restore functions expects one input argument.
13716 ; Since those are not standard call_insn's, we must avoid using
13717 ; MATCH_OPERAND for that argument. That way the register rename
13718 ; optimization will not try to rename this register.
13719 ; Each pattern is repeated for each possible register number used in
13720 ; various ABIs (r11, r1, and for some functions r12)
13722 (define_insn "*save_gpregs_<mode>_r11"
13723 [(match_parallel 0 "any_parallel_operand"
13724 [(clobber (reg:P 65))
13725 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13726 (use (reg:P 11))
13727 (set (match_operand:P 2 "memory_operand" "=m")
13728 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13729 ""
13730 "bl %1"
13731 [(set_attr "type" "branch")
13732 (set_attr "length" "4")])
13734 (define_insn "*save_gpregs_<mode>_r12"
13735 [(match_parallel 0 "any_parallel_operand"
13736 [(clobber (reg:P 65))
13737 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13738 (use (reg:P 12))
13739 (set (match_operand:P 2 "memory_operand" "=m")
13740 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13741 ""
13742 "bl %1"
13743 [(set_attr "type" "branch")
13744 (set_attr "length" "4")])
13746 (define_insn "*save_gpregs_<mode>_r1"
13747 [(match_parallel 0 "any_parallel_operand"
13748 [(clobber (reg:P 65))
13749 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13750 (use (reg:P 1))
13751 (set (match_operand:P 2 "memory_operand" "=m")
13752 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13753 ""
13754 "bl %1"
13755 [(set_attr "type" "branch")
13756 (set_attr "length" "4")])
13758 (define_insn "*save_fpregs_<mode>_r11"
13759 [(match_parallel 0 "any_parallel_operand"
13760 [(clobber (reg:P 65))
13761 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13762 (use (reg:P 11))
13763 (set (match_operand:DF 2 "memory_operand" "=m")
13764 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13765 ""
13766 "bl %1"
13767 [(set_attr "type" "branch")
13768 (set_attr "length" "4")])
13770 (define_insn "*save_fpregs_<mode>_r12"
13771 [(match_parallel 0 "any_parallel_operand"
13772 [(clobber (reg:P 65))
13773 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13774 (use (reg:P 12))
13775 (set (match_operand:DF 2 "memory_operand" "=m")
13776 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13777 ""
13778 "bl %1"
13779 [(set_attr "type" "branch")
13780 (set_attr "length" "4")])
13782 (define_insn "*save_fpregs_<mode>_r1"
13783 [(match_parallel 0 "any_parallel_operand"
13784 [(clobber (reg:P 65))
13785 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13786 (use (reg:P 1))
13787 (set (match_operand:DF 2 "memory_operand" "=m")
13788 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13789 ""
13790 "bl %1"
13791 [(set_attr "type" "branch")
13792 (set_attr "length" "4")])
13794 ; This is to explain that changes to the stack pointer should
13795 ; not be moved over loads from or stores to stack memory.
13796 (define_insn "stack_tie"
13797 [(match_parallel 0 "tie_operand"
13798 [(set (mem:BLK (reg 1)) (const_int 0))])]
13799 ""
13800 ""
13801 [(set_attr "length" "0")])
13803 (define_expand "epilogue"
13804 [(use (const_int 0))]
13805 ""
13806 {
13807 if (!TARGET_SCHED_PROLOG)
13808 emit_insn (gen_blockage ());
13809 rs6000_emit_epilogue (FALSE);
13810 DONE;
13811 })
13813 ; On some processors, doing the mtcrf one CC register at a time is
13814 ; faster (like on the 604e). On others, doing them all at once is
13815 ; faster; for instance, on the 601 and 750.
13817 (define_expand "movsi_to_cr_one"
13818 [(set (match_operand:CC 0 "cc_reg_operand" "")
13819 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
13820 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
13821 ""
13822 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13824 (define_insn "*movsi_to_cr"
13825 [(match_parallel 0 "mtcrf_operation"
13826 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13827 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13828 (match_operand 3 "immediate_operand" "n")]
13829 UNSPEC_MOVESI_TO_CR))])]
13830 ""
13831 "*
13832 {
13833 int mask = 0;
13834 int i;
13835 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13836 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13837 operands[4] = GEN_INT (mask);
13838 return \"mtcrf %4,%2\";
13839 }"
13840 [(set_attr "type" "mtcr")])
13842 (define_insn "*mtcrfsi"
13843 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13844 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13845 (match_operand 2 "immediate_operand" "n")]
13846 UNSPEC_MOVESI_TO_CR))]
13847 "GET_CODE (operands[0]) == REG
13848 && CR_REGNO_P (REGNO (operands[0]))
13849 && GET_CODE (operands[2]) == CONST_INT
13850 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13851 "mtcrf %R0,%1"
13852 [(set_attr "type" "mtcr")])
13854 ; The load-multiple instructions have similar properties.
13855 ; Note that "load_multiple" is a name known to the machine-independent
13856 ; code that actually corresponds to the PowerPC load-string.
13858 (define_insn "*lmw"
13859 [(match_parallel 0 "lmw_operation"
13860 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13861 (match_operand:SI 2 "memory_operand" "m"))])]
13862 "TARGET_MULTIPLE"
13863 "lmw %1,%2"
13864 [(set_attr "type" "load")
13865 (set_attr "update" "yes")
13866 (set_attr "indexed" "yes")
13867 (set_attr "cell_micro" "always")])
13869 (define_insn "*return_internal_<mode>"
13870 [(simple_return)
13871 (use (match_operand:P 0 "register_operand" "lc"))]
13872 ""
13873 "b%T0"
13874 [(set_attr "type" "jmpreg")])
13876 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13877 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
13879 ; The following comment applies to:
13880 ; save_gpregs_*
13881 ; save_fpregs_*
13882 ; restore_gpregs*
13883 ; return_and_restore_gpregs*
13884 ; return_and_restore_fpregs*
13885 ; return_and_restore_fpregs_aix*
13886 ;
13887 ; The out-of-line save / restore functions expects one input argument.
13888 ; Since those are not standard call_insn's, we must avoid using
13889 ; MATCH_OPERAND for that argument. That way the register rename
13890 ; optimization will not try to rename this register.
13891 ; Each pattern is repeated for each possible register number used in
13892 ; various ABIs (r11, r1, and for some functions r12)
13894 (define_insn "*restore_gpregs_<mode>_r11"
13895 [(match_parallel 0 "any_parallel_operand"
13896 [(clobber (match_operand:P 1 "register_operand" "=l"))
13897 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13898 (use (reg:P 11))
13899 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13900 (match_operand:P 4 "memory_operand" "m"))])]
13901 ""
13902 "bl %2"
13903 [(set_attr "type" "branch")
13904 (set_attr "length" "4")])
13906 (define_insn "*restore_gpregs_<mode>_r12"
13907 [(match_parallel 0 "any_parallel_operand"
13908 [(clobber (match_operand:P 1 "register_operand" "=l"))
13909 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13910 (use (reg:P 12))
13911 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13912 (match_operand:P 4 "memory_operand" "m"))])]
13913 ""
13914 "bl %2"
13915 [(set_attr "type" "branch")
13916 (set_attr "length" "4")])
13918 (define_insn "*restore_gpregs_<mode>_r1"
13919 [(match_parallel 0 "any_parallel_operand"
13920 [(clobber (match_operand:P 1 "register_operand" "=l"))
13921 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13922 (use (reg:P 1))
13923 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13924 (match_operand:P 4 "memory_operand" "m"))])]
13925 ""
13926 "bl %2"
13927 [(set_attr "type" "branch")
13928 (set_attr "length" "4")])
13930 (define_insn "*return_and_restore_gpregs_<mode>_r11"
13931 [(match_parallel 0 "any_parallel_operand"
13932 [(return)
13933 (clobber (match_operand:P 1 "register_operand" "=l"))
13934 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13935 (use (reg:P 11))
13936 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13937 (match_operand:P 4 "memory_operand" "m"))])]
13938 ""
13939 "b %2"
13940 [(set_attr "type" "branch")
13941 (set_attr "length" "4")])
13943 (define_insn "*return_and_restore_gpregs_<mode>_r12"
13944 [(match_parallel 0 "any_parallel_operand"
13945 [(return)
13946 (clobber (match_operand:P 1 "register_operand" "=l"))
13947 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13948 (use (reg:P 12))
13949 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13950 (match_operand:P 4 "memory_operand" "m"))])]
13951 ""
13952 "b %2"
13953 [(set_attr "type" "branch")
13954 (set_attr "length" "4")])
13956 (define_insn "*return_and_restore_gpregs_<mode>_r1"
13957 [(match_parallel 0 "any_parallel_operand"
13958 [(return)
13959 (clobber (match_operand:P 1 "register_operand" "=l"))
13960 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13961 (use (reg:P 1))
13962 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13963 (match_operand:P 4 "memory_operand" "m"))])]
13964 ""
13965 "b %2"
13966 [(set_attr "type" "branch")
13967 (set_attr "length" "4")])
13969 (define_insn "*return_and_restore_fpregs_<mode>_r11"
13970 [(match_parallel 0 "any_parallel_operand"
13971 [(return)
13972 (clobber (match_operand:P 1 "register_operand" "=l"))
13973 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13974 (use (reg:P 11))
13975 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13976 (match_operand:DF 4 "memory_operand" "m"))])]
13977 ""
13978 "b %2"
13979 [(set_attr "type" "branch")
13980 (set_attr "length" "4")])
13982 (define_insn "*return_and_restore_fpregs_<mode>_r12"
13983 [(match_parallel 0 "any_parallel_operand"
13984 [(return)
13985 (clobber (match_operand:P 1 "register_operand" "=l"))
13986 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13987 (use (reg:P 12))
13988 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13989 (match_operand:DF 4 "memory_operand" "m"))])]
13990 ""
13991 "b %2"
13992 [(set_attr "type" "branch")
13993 (set_attr "length" "4")])
13995 (define_insn "*return_and_restore_fpregs_<mode>_r1"
13996 [(match_parallel 0 "any_parallel_operand"
13997 [(return)
13998 (clobber (match_operand:P 1 "register_operand" "=l"))
13999 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14000 (use (reg:P 1))
14001 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14002 (match_operand:DF 4 "memory_operand" "m"))])]
14003 ""
14004 "b %2"
14005 [(set_attr "type" "branch")
14006 (set_attr "length" "4")])
14008 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
14009 [(match_parallel 0 "any_parallel_operand"
14010 [(return)
14011 (use (match_operand:P 1 "register_operand" "l"))
14012 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14013 (use (reg:P 11))
14014 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14015 (match_operand:DF 4 "memory_operand" "m"))])]
14016 ""
14017 "b %2"
14018 [(set_attr "type" "branch")
14019 (set_attr "length" "4")])
14021 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
14022 [(match_parallel 0 "any_parallel_operand"
14023 [(return)
14024 (use (match_operand:P 1 "register_operand" "l"))
14025 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14026 (use (reg:P 1))
14027 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14028 (match_operand:DF 4 "memory_operand" "m"))])]
14029 ""
14030 "b %2"
14031 [(set_attr "type" "branch")
14032 (set_attr "length" "4")])
14034 ; This is used in compiling the unwind routines.
14035 (define_expand "eh_return"
14036 [(use (match_operand 0 "general_operand" ""))]
14037 ""
14038 "
14039 {
14040 if (TARGET_32BIT)
14041 emit_insn (gen_eh_set_lr_si (operands[0]));
14042 else
14043 emit_insn (gen_eh_set_lr_di (operands[0]));
14044 DONE;
14045 }")
14047 ; We can't expand this before we know where the link register is stored.
14048 (define_insn "eh_set_lr_<mode>"
14049 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14050 UNSPECV_EH_RR)
14051 (clobber (match_scratch:P 1 "=&b"))]
14052 ""
14053 "#")
14055 (define_split
14056 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14057 (clobber (match_scratch 1 ""))]
14058 "reload_completed"
14059 [(const_int 0)]
14060 "
14061 {
14062 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14063 DONE;
14064 }")
14066 (define_insn "prefetch"
14067 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14068 (match_operand:SI 1 "const_int_operand" "n")
14069 (match_operand:SI 2 "const_int_operand" "n"))]
14070 ""
14071 "*
14072 {
14073 if (GET_CODE (operands[0]) == REG)
14074 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14075 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14076 }"
14077 [(set_attr "type" "load")])
14078 \f
14079 (define_insn "bpermd_<mode>"
14080 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14081 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
14082 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
14083 "TARGET_POPCNTD"
14084 "bpermd %0,%1,%2"
14085 [(set_attr "type" "popcnt")])
14087 \f
14088 ;; Builtin fma support. Handle
14089 ;; Note that the conditions for expansion are in the FMA_F iterator.
14091 (define_expand "fma<mode>4"
14092 [(set (match_operand:FMA_F 0 "register_operand" "")
14093 (fma:FMA_F
14094 (match_operand:FMA_F 1 "register_operand" "")
14095 (match_operand:FMA_F 2 "register_operand" "")
14096 (match_operand:FMA_F 3 "register_operand" "")))]
14097 ""
14098 "")
14100 (define_insn "*fma<mode>4_fpr"
14101 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14102 (fma:SFDF
14103 (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>,<Fv>")
14104 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14105 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))]
14106 "TARGET_<MODE>_FPR"
14107 "@
14108 fmadd<Ftrad> %0,%1,%2,%3
14109 xsmadda<Fvsx> %x0,%x1,%x2
14110 xsmaddm<Fvsx> %x0,%x1,%x3"
14111 [(set_attr "type" "fp")
14112 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14114 ; Altivec only has fma and nfms.
14115 (define_expand "fms<mode>4"
14116 [(set (match_operand:FMA_F 0 "register_operand" "")
14117 (fma:FMA_F
14118 (match_operand:FMA_F 1 "register_operand" "")
14119 (match_operand:FMA_F 2 "register_operand" "")
14120 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
14121 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14122 "")
14124 (define_insn "*fms<mode>4_fpr"
14125 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14126 (fma:SFDF
14127 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14128 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14129 (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
14130 "TARGET_<MODE>_FPR"
14131 "@
14132 fmsub<Ftrad> %0,%1,%2,%3
14133 xsmsuba<Fvsx> %x0,%x1,%x2
14134 xsmsubm<Fvsx> %x0,%x1,%x3"
14135 [(set_attr "type" "fp")
14136 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14138 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
14139 (define_expand "fnma<mode>4"
14140 [(set (match_operand:FMA_F 0 "register_operand" "")
14141 (neg:FMA_F
14142 (fma:FMA_F
14143 (match_operand:FMA_F 1 "register_operand" "")
14144 (match_operand:FMA_F 2 "register_operand" "")
14145 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14146 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
14147 "")
14149 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
14150 (define_expand "fnms<mode>4"
14151 [(set (match_operand:FMA_F 0 "register_operand" "")
14152 (neg:FMA_F
14153 (fma:FMA_F
14154 (match_operand:FMA_F 1 "register_operand" "")
14155 (match_operand:FMA_F 2 "register_operand" "")
14156 (match_operand:FMA_F 3 "register_operand" ""))))]
14157 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14158 "")
14160 ; Not an official optab name, but used from builtins.
14161 (define_expand "nfma<mode>4"
14162 [(set (match_operand:FMA_F 0 "register_operand" "")
14163 (neg:FMA_F
14164 (fma:FMA_F
14165 (match_operand:FMA_F 1 "register_operand" "")
14166 (match_operand:FMA_F 2 "register_operand" "")
14167 (match_operand:FMA_F 3 "register_operand" ""))))]
14168 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14169 "")
14171 (define_insn "*nfma<mode>4_fpr"
14172 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14173 (neg:SFDF
14174 (fma:SFDF
14175 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14176 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14177 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
14178 "TARGET_<MODE>_FPR"
14179 "@
14180 fnmadd<Ftrad> %0,%1,%2,%3
14181 xsnmadda<Fvsx> %x0,%x1,%x2
14182 xsnmaddm<Fvsx> %x0,%x1,%x3"
14183 [(set_attr "type" "fp")
14184 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14186 ; Not an official optab name, but used from builtins.
14187 (define_expand "nfms<mode>4"
14188 [(set (match_operand:FMA_F 0 "register_operand" "")
14189 (neg:FMA_F
14190 (fma:FMA_F
14191 (match_operand:FMA_F 1 "register_operand" "")
14192 (match_operand:FMA_F 2 "register_operand" "")
14193 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14194 ""
14195 "")
14197 (define_insn "*nfmssf4_fpr"
14198 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14199 (neg:SFDF
14200 (fma:SFDF
14201 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14202 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14203 (neg:SFDF
14204 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))))]
14205 "TARGET_<MODE>_FPR"
14206 "@
14207 fnmsub<Ftrad> %0,%1,%2,%3
14208 xsnmsuba<Fvsx> %x0,%x1,%x2
14209 xsnmsubm<Fvsx> %x0,%x1,%x3"
14210 [(set_attr "type" "fp")
14211 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14213 \f
14214 (define_expand "rs6000_get_timebase"
14215 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
14216 ""
14217 {
14218 if (TARGET_POWERPC64)
14219 emit_insn (gen_rs6000_mftb_di (operands[0]));
14220 else
14221 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
14222 DONE;
14223 })
14225 (define_insn "rs6000_get_timebase_ppc32"
14226 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
14227 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
14228 (clobber (match_scratch:SI 1 "=r"))
14229 (clobber (match_scratch:CC 2 "=y"))]
14230 "!TARGET_POWERPC64"
14231 {
14232 if (WORDS_BIG_ENDIAN)
14233 if (TARGET_MFCRF)
14234 {
14235 return "mfspr %0,269\;"
14236 "mfspr %L0,268\;"
14237 "mfspr %1,269\;"
14238 "cmpw %2,%0,%1\;"
14239 "bne- %2,$-16";
14240 }
14241 else
14242 {
14243 return "mftbu %0\;"
14244 "mftb %L0\;"
14245 "mftbu %1\;"
14246 "cmpw %2,%0,%1\;"
14247 "bne- %2,$-16";
14248 }
14249 else
14250 if (TARGET_MFCRF)
14251 {
14252 return "mfspr %L0,269\;"
14253 "mfspr %0,268\;"
14254 "mfspr %1,269\;"
14255 "cmpw %2,%L0,%1\;"
14256 "bne- %2,$-16";
14257 }
14258 else
14259 {
14260 return "mftbu %L0\;"
14261 "mftb %0\;"
14262 "mftbu %1\;"
14263 "cmpw %2,%L0,%1\;"
14264 "bne- %2,$-16";
14265 }
14266 }
14267 [(set_attr "length" "20")])
14269 (define_insn "rs6000_mftb_<mode>"
14270 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14271 (unspec_volatile:P [(const_int 0)] UNSPECV_MFTB))]
14272 ""
14273 {
14274 if (TARGET_MFCRF)
14275 return "mfspr %0,268";
14276 else
14277 return "mftb %0";
14278 })
14280 \f
14281 (define_insn "rs6000_mffs"
14282 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
14283 (unspec_volatile:DF [(const_int 0)] UNSPECV_MFFS))]
14284 "TARGET_HARD_FLOAT && TARGET_FPRS"
14285 "mffs %0")
14287 (define_insn "rs6000_mtfsf"
14288 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")
14289 (match_operand:DF 1 "gpc_reg_operand" "d")]
14290 UNSPECV_MTFSF)]
14291 "TARGET_HARD_FLOAT && TARGET_FPRS"
14292 "mtfsf %0,%1")
14294 \f
14295 ;; Power8 fusion support for fusing an addis instruction with a D-form load of
14296 ;; a GPR. The addis instruction must be adjacent to the load, and use the same
14297 ;; register that is being loaded. The fused ops must be physically adjacent.
14299 ;; We use define_peephole for the actual addis/load, and the register used to
14300 ;; hold the addis value must be the same as the register being loaded. We use
14301 ;; define_peephole2 to change the register used for addis to be the register
14302 ;; being loaded, since we can look at whether it is dead after the load insn.
14304 (define_peephole
14305 [(set (match_operand:P 0 "base_reg_operand" "")
14306 (match_operand:P 1 "fusion_gpr_addis" ""))
14307 (set (match_operand:INT1 2 "base_reg_operand" "")
14308 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
14309 "TARGET_P8_FUSION && fusion_gpr_load_p (operands, false)"
14310 {
14311 return emit_fusion_gpr_load (operands);
14312 }
14313 [(set_attr "type" "load")
14314 (set_attr "length" "8")])
14316 (define_peephole2
14317 [(set (match_operand:P 0 "base_reg_operand" "")
14318 (match_operand:P 1 "fusion_gpr_addis" ""))
14319 (set (match_operand:INT1 2 "base_reg_operand" "")
14320 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
14321 "TARGET_P8_FUSION
14322 && (REGNO (operands[0]) != REGNO (operands[2])
14323 || GET_CODE (operands[3]) == SIGN_EXTEND)
14324 && fusion_gpr_load_p (operands, true)"
14325 [(const_int 0)]
14326 {
14327 expand_fusion_gpr_load (operands);
14328 DONE;
14329 })
14331 \f
14332 ;; Miscellaneous ISA 2.06 (power7) instructions
14333 (define_insn "addg6s"
14334 [(set (match_operand:SI 0 "register_operand" "=r")
14335 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
14336 (match_operand:SI 2 "register_operand" "r")]
14337 UNSPEC_ADDG6S))]
14338 "TARGET_POPCNTD"
14339 "addg6s %0,%1,%2"
14340 [(set_attr "type" "integer")
14341 (set_attr "length" "4")])
14343 (define_insn "cdtbcd"
14344 [(set (match_operand:SI 0 "register_operand" "=r")
14345 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
14346 UNSPEC_CDTBCD))]
14347 "TARGET_POPCNTD"
14348 "cdtbcd %0,%1"
14349 [(set_attr "type" "integer")
14350 (set_attr "length" "4")])
14352 (define_insn "cbcdtd"
14353 [(set (match_operand:SI 0 "register_operand" "=r")
14354 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
14355 UNSPEC_CBCDTD))]
14356 "TARGET_POPCNTD"
14357 "cbcdtd %0,%1"
14358 [(set_attr "type" "integer")
14359 (set_attr "length" "4")])
14361 (define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE
14362 UNSPEC_DIVEO
14363 UNSPEC_DIVEU
14364 UNSPEC_DIVEUO])
14366 (define_int_attr div_extend [(UNSPEC_DIVE "e")
14367 (UNSPEC_DIVEO "eo")
14368 (UNSPEC_DIVEU "eu")
14369 (UNSPEC_DIVEUO "euo")])
14371 (define_insn "div<div_extend>_<mode>"
14372 [(set (match_operand:GPR 0 "register_operand" "=r")
14373 (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
14374 (match_operand:GPR 2 "register_operand" "r")]
14375 UNSPEC_DIV_EXTEND))]
14376 "TARGET_POPCNTD"
14377 "div<wd><div_extend> %0,%1,%2"
14378 [(set_attr "type" "div")
14379 (set_attr "size" "<bits>")])
14381 \f
14382 ;; Pack/unpack 128-bit floating point types that take 2 scalar registers
14384 ; Type of the 64-bit part when packing/unpacking 128-bit floating point types
14385 (define_mode_attr FP128_64 [(TF "DF") (TD "DI")])
14387 (define_expand "unpack<mode>"
14388 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "")
14389 (unspec:<FP128_64>
14390 [(match_operand:FMOVE128 1 "register_operand" "")
14391 (match_operand:QI 2 "const_0_to_1_operand" "")]
14392 UNSPEC_UNPACK_128BIT))]
14393 ""
14394 "")
14396 (define_insn_and_split "unpack<mode>_dm"
14397 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,d,r,m")
14398 (unspec:<FP128_64>
14399 [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r")
14400 (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")]
14401 UNSPEC_UNPACK_128BIT))]
14402 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
14403 "#"
14404 "&& reload_completed"
14405 [(set (match_dup 0) (match_dup 3))]
14406 {
14407 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
14409 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
14410 {
14411 emit_note (NOTE_INSN_DELETED);
14412 DONE;
14413 }
14415 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
14416 }
14417 [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store")
14418 (set_attr "length" "4")])
14420 (define_insn_and_split "unpack<mode>_nodm"
14421 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m")
14422 (unspec:<FP128_64>
14423 [(match_operand:FMOVE128 1 "register_operand" "d,d")
14424 (match_operand:QI 2 "const_0_to_1_operand" "i,i")]
14425 UNSPEC_UNPACK_128BIT))]
14426 "!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE"
14427 "#"
14428 "&& reload_completed"
14429 [(set (match_dup 0) (match_dup 3))]
14430 {
14431 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
14433 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
14434 {
14435 emit_note (NOTE_INSN_DELETED);
14436 DONE;
14437 }
14439 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
14440 }
14441 [(set_attr "type" "fp,fpstore")
14442 (set_attr "length" "4")])
14444 (define_insn_and_split "pack<mode>"
14445 [(set (match_operand:FMOVE128 0 "register_operand" "=d,&d")
14446 (unspec:FMOVE128
14447 [(match_operand:<FP128_64> 1 "register_operand" "0,d")
14448 (match_operand:<FP128_64> 2 "register_operand" "d,d")]
14449 UNSPEC_PACK_128BIT))]
14450 ""
14451 "@
14452 fmr %L0,%2
14453 #"
14454 "&& reload_completed && REGNO (operands[0]) != REGNO (operands[1])"
14455 [(set (match_dup 3) (match_dup 1))
14456 (set (match_dup 4) (match_dup 2))]
14457 {
14458 unsigned dest_hi = REGNO (operands[0]);
14459 unsigned dest_lo = dest_hi + 1;
14461 gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo));
14462 gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo));
14464 operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi);
14465 operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo);
14466 }
14467 [(set_attr "type" "fp,fp")
14468 (set_attr "length" "4,8")])
14470 (define_insn "unpackv1ti"
14471 [(set (match_operand:DI 0 "register_operand" "=d,d")
14472 (unspec:DI [(match_operand:V1TI 1 "register_operand" "0,wa")
14473 (match_operand:QI 2 "const_0_to_1_operand" "O,i")]
14474 UNSPEC_UNPACK_128BIT))]
14475 "TARGET_VSX"
14476 {
14477 if (REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[2]) == 0)
14478 return ASM_COMMENT_START " xxpermdi to same register";
14480 operands[3] = GEN_INT (INTVAL (operands[2]) == 0 ? 0 : 3);
14481 return "xxpermdi %x0,%x1,%x1,%3";
14482 }
14483 [(set_attr "type" "vecperm")
14484 (set_attr "length" "4")])
14486 (define_insn "packv1ti"
14487 [(set (match_operand:V1TI 0 "register_operand" "=wa")
14488 (unspec:V1TI
14489 [(match_operand:DI 1 "register_operand" "d")
14490 (match_operand:DI 2 "register_operand" "d")]
14491 UNSPEC_PACK_128BIT))]
14492 "TARGET_VSX"
14493 "xxpermdi %x0,%x1,%x2,0"
14494 [(set_attr "type" "vecperm")
14495 (set_attr "length" "4")])
14497 \f
14499 (include "sync.md")
14500 (include "vector.md")
14501 (include "vsx.md")
14502 (include "altivec.md")
14503 (include "spe.md")
14504 (include "dfp.md")
14505 (include "paired.md")
14506 (include "crypto.md")
14507 (include "htm.md")