1 ;; DFA scheduling description of the Synopsys DesignWare ARC HS4x cpu
3 ;; Copyright (C) 2017-2023 Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_automaton "ARCHS4x")
23 (define_cpu_unit "hs4x_issue0" "ARCHS4x")
24 (define_cpu_unit "hs4x_issue1" "ARCHS4x")
25 (define_cpu_unit "hs4x_ld_st" "ARCHS4x")
26 (define_cpu_unit "hs4x_divrem" "ARCHS4x")
27 (define_cpu_unit "hs4x_mult" "ARCHS4x")
28 (define_cpu_unit "hs4x_x1, hs4x_x2" "ARCHS4x")
29 (define_cpu_unit "hs4x_y1, hs4x_y2" "ARCHS4x")
30 (define_cpu_unit "hs4x_brcc0, hs4x_brcc1" "ARCHS4x")
32 (define_insn_reservation "hs4x_brj_op" 1
33 (and (match_test "TARGET_HS")
34 (eq_attr "tune" "archs4x, archs4xd")
35 (eq_attr "type" "call, call_no_delay_slot, uncond_branch, jump, \
39 (define_insn_reservation "hs4x_brcc_op" 1
40 (and (match_test "TARGET_HS")
41 (eq_attr "tune" "archs4x, archs4xd")
42 (eq_attr "type" "brcc,brcc_no_delay_slot,loop_end"))
43 "hs4x_issue0 + hs4x_brcc0 + hs4x_brcc1")
45 (define_insn_reservation "hs4x_data_load_op" 4
46 (and (match_test "TARGET_HS")
47 (eq_attr "tune" "archs4x, archs4xd")
48 (eq_attr "type" "load"))
49 "hs4x_issue1 + hs4x_ld_st,hs4x_ld_st")
51 (define_insn_reservation "hs4x_data_store_op" 1
52 (and (match_test "TARGET_HS")
53 (eq_attr "tune_store" "normal")
54 (eq_attr "type" "store"))
55 "hs4x_issue1 + hs4x_ld_st")
57 (define_insn_reservation "hs4x_data_store_1_op" 2
58 (and (match_test "TARGET_HS")
59 (eq_attr "tune_store" "rel31a")
60 (eq_attr "type" "store"))
61 "hs4x_issue1 + hs4x_ld_st + hs4x_brcc0, hs4x_brcc1")
64 (define_insn_reservation "hs4x_adv_alue_op" 4
65 (and (match_test "TARGET_HS")
66 (eq_attr "tune" "archs4x, archs4xd")
67 (eq_attr "type" "cc_arith, two_cycle_core, shift, lr, sr"))
68 "(hs4x_issue0 | hs4x_issue1), hs4x_x1")
70 (define_insn_reservation "hs4x_adv_alul_op" 6
71 (and (match_test "TARGET_HS")
72 (eq_attr "tune" "archs4xd")
73 (eq_attr "type" "cc_arith, two_cycle_core, shift, lr, sr"))
74 "(hs4x_issue0 | hs4x_issue1), nothing*2, hs4x_x2")
77 (define_insn_reservation "hs4x_basic_alue_op" 1
78 (and (match_test "TARGET_HS")
79 (eq_attr "tune" "archs4x, archs4xd")
80 (eq_attr "type" "move, cmove, unary, binary, compare, misc, add, sub, bxor"))
81 "(hs4x_issue0 | hs4x_issue1) + hs4x_y1")
83 (define_insn_reservation "hs4x_basic_alul_op" 4
84 (and (match_test "TARGET_HS")
85 (eq_attr "tune" "archs4x, archs4xd")
86 (eq_attr "type" "move, cmove, unary, binary, compare, misc"))
87 "(hs4x_issue0 | hs4x_issue1), nothing*2, hs4x_y2")
89 (define_insn_reservation "hs4x_divrem_op" 13
90 (and (match_test "TARGET_HS")
91 (eq_attr "tune" "archs4x, archs4xd")
92 (eq_attr "type" "div_rem"))
93 "hs4x_issue0 + hs4x_divrem, (hs4x_divrem)*12")
95 ;;Consider the DSPMPY fast here
96 (define_insn_reservation "hs4x_mul_fast_op" 7
97 (and (match_test "TARGET_HS")
98 (eq_attr "tune_dspmpy" "fast")
99 (eq_attr "type" "mul16_em, multi, umulti"))
100 "hs4x_issue0 + hs4x_mult")
102 (define_insn_reservation "hs4x_mul_slow_op" 8
103 (and (match_test "TARGET_HS")
104 (eq_attr "tune_dspmpy" "slow")
105 (eq_attr "type" "mul16_em, multi, umulti"))
106 "hs4x_issue0 + hs4x_mult")
109 (define_insn_reservation "hs4x_fpu_op" 8
110 (and (match_test "TARGET_HS")
111 (eq_attr "tune" "archs4x, archs4xd")
112 (eq_attr "type" "fpu"))
116 (define_insn_reservation "hs4x_fpu_fuse_op" 12
117 (and (match_test "TARGET_HS")
118 (eq_attr "tune" "archs4x, archs4xd")
119 (eq_attr "type" "fpu_fuse"))
122 ;; FPU SP SQRT/DIV unit
123 (define_insn_reservation "hs4x_fpu_sdiv_op" 20
124 (and (match_test "TARGET_HS")
125 (eq_attr "tune" "archs4x, archs4xd")
126 (eq_attr "type" "fpu_sdiv"))
129 ;; FPU DP SQRT/DIV unit
130 (define_insn_reservation "hs4x_fpu_ddiv_op" 34
131 (and (match_test "TARGET_HS")
132 (eq_attr "tune" "archs4x, archs4xd")
133 (eq_attr "type" "fpu_ddiv"))
137 (define_insn_reservation "hs4x_fpu_cvt_op" 5
138 (and (match_test "TARGET_HS")
139 (eq_attr "tune" "archs4x, archs4xd")
140 (eq_attr "type" "fpu_cvt"))
143 ;; BYPASS Advanced ALU ->
144 (define_bypass 1 "hs4x_adv_alue_op" "hs4x_divrem_op")
145 (define_bypass 1 "hs4x_adv_alue_op" "hs4x_mul_*op")
146 (define_bypass 2 "hs4x_adv_alue_op" "hs4x_adv_alue_op")
147 (define_bypass 1 "hs4x_adv_alue_op" "hs4x_basic_alue_op")
148 (define_bypass 1 "hs4x_adv_alue_op" "hs4x_basic_alul_op")
149 (define_bypass 1 "hs4x_adv_alue_op" "hs4x_data_load_op")
150 (define_bypass 0 "hs4x_adv_alue_op" "hs4x_data_store_op" "store_data_bypass_p")
151 (define_bypass 2 "hs4x_adv_alue_op" "hs4x_data_store_op")
152 (define_bypass 1 "hs4x_adv_alue_op" "hs4x_fpu_*op")
154 (define_bypass 2 "hs4x_adv_alul_op" "hs4x_basic_alul_op")
155 (define_bypass 2 "hs4x_adv_alul_op" "hs4x_adv_alul_op")
156 (define_bypass 2 "hs4x_adv_alul_op" "hs4x_mul_*op")
157 (define_bypass 0 "hs4x_adv_alul_op" "hs4x_data_store_op" "store_data_bypass_p")
158 (define_bypass 4 "hs4x_adv_alul_op" "hs4x_divrem_op")
159 (define_bypass 5 "hs4x_adv_alul_op" "hs4x_fpu_*op")
161 ;; BYPASS Basic ALU ->
162 (define_bypass 0 "hs4x_basic_alue_op" "hs4x_data_store_op" "store_data_bypass_p")
164 (define_bypass 1 "hs4x_basic_alul_op" "hs4x_basic_alul_op")
165 (define_bypass 1 "hs4x_basic_alul_op" "hs4x_adv_alul_op")
166 (define_bypass 0 "hs4x_basic_alul_op" "hs4x_data_store_op" "store_data_bypass_p")
167 (define_bypass 1 "hs4x_basic_alul_op" "hs4x_mul_*op")
168 (define_bypass 3 "hs4x_basic_alul_op" "hs4x_divrem_op")
169 (define_bypass 3 "hs4x_basic_alul_op" "hs4x_fpu_*op")
172 (define_bypass 1 "hs4x_data_load_op" "hs4x_basic_alul_op")
173 (define_bypass 1 "hs4x_data_load_op" "hs4x_adv_alul_op")
174 (define_bypass 3 "hs4x_data_load_op" "hs4x_divrem_op")
175 (define_bypass 3 "hs4x_data_load_op" "hs4x_data_load_op")
176 (define_bypass 3 "hs4x_data_load_op" "hs4x_mul_*op")
177 (define_bypass 0 "hs4x_data_load_op" "hs4x_data_store_op" "store_data_bypass_p")
178 (define_bypass 3 "hs4x_data_load_op" "hs4x_fpu_*op")
180 ;; BYPASS FAST MPY ->
181 (define_bypass 4 "hs4x_mul_fast_op" "hs4x_basic_alul_op")
182 (define_bypass 4 "hs4x_mul_fast_op" "hs4x_adv_alul_op")
183 (define_bypass 4 "hs4x_mul_fast_op" "hs4x_mul_fast_op")
184 (define_bypass 6 "hs4x_mul_fast_op" "hs4x_divrem_op")
185 (define_bypass 0 "hs4x_mul_fast_op" "hs4x_data_store_op" "store_data_bypass_p")
186 (define_bypass 6 "hs4x_mul_fast_op" "hs4x_fpu_*op")
188 ;; BYPASS SLOW MPY ->
189 (define_bypass 5 "hs4x_mul_slow_op" "hs4x_basic_alul_op")
190 (define_bypass 5 "hs4x_mul_slow_op" "hs4x_adv_alul_op")
191 (define_bypass 5 "hs4x_mul_slow_op" "hs4x_mul_slow_op")
192 (define_bypass 7 "hs4x_mul_slow_op" "hs4x_divrem_op")
193 (define_bypass 0 "hs4x_mul_slow_op" "hs4x_data_store_op" "store_data_bypass_p")
194 (define_bypass 7 "hs4x_mul_slow_op" "hs4x_fpu_*op")
197 (define_bypass 5 "hs4x_fpu_op" "hs4x_basic_alul_op")
198 (define_bypass 5 "hs4x_fpu_op" "hs4x_adv_alul_op")
199 (define_bypass 5 "hs4x_fpu_op" "hs4x_mul_*op")
200 (define_bypass 7 "hs4x_fpu_op" "hs4x_divrem_op")
201 (define_bypass 5 "hs4x_fpu_op" "hs4x_fpu_*op")
202 (define_bypass 0 "hs4x_fpu_op" "hs4x_data_store_op" "store_data_bypass_p")
205 (define_bypass 9 "hs4x_fpu_fuse_op" "hs4x_basic_alul_op")
206 (define_bypass 9 "hs4x_fpu_fuse_op" "hs4x_adv_alul_op")
207 (define_bypass 9 "hs4x_fpu_fuse_op" "hs4x_mul_*op")
208 (define_bypass 11 "hs4x_fpu_fuse_op" "hs4x_divrem_op")
209 (define_bypass 11 "hs4x_fpu_fuse_op" "hs4x_fpu_*op")
210 (define_bypass 0 "hs4x_fpu_fuse_op" "hs4x_data_store_op" "store_data_bypass_p")
212 ;;BYPASS FPU SP DIV ->
213 (define_bypass 16 "hs4x_fpu_sdiv_op" "hs4x_basic_alul_op")
214 (define_bypass 16 "hs4x_fpu_sdiv_op" "hs4x_adv_alul_op")
215 (define_bypass 16 "hs4x_fpu_sdiv_op" "hs4x_mul_*op")
216 (define_bypass 19 "hs4x_fpu_sdiv_op" "hs4x_divrem_op")
217 (define_bypass 19 "hs4x_fpu_sdiv_op" "hs4x_fpu_*op")
218 (define_bypass 0 "hs4x_fpu_sdiv_op" "hs4x_data_store_op" "store_data_bypass_p")
220 ;;BYPASS FPU DP DIV ->
221 (define_bypass 31 "hs4x_fpu_ddiv_op" "hs4x_basic_alul_op")
222 (define_bypass 31 "hs4x_fpu_ddiv_op" "hs4x_adv_alul_op")
223 (define_bypass 31 "hs4x_fpu_ddiv_op" "hs4x_mul_*op")
224 (define_bypass 34 "hs4x_fpu_ddiv_op" "hs4x_divrem_op")
225 (define_bypass 34 "hs4x_fpu_ddiv_op" "hs4x_fpu_*op")
226 (define_bypass 0 "hs4x_fpu_ddiv_op" "hs4x_data_store_op" "store_data_bypass_p")
229 (define_bypass 1 "hs4x_fpu_cvt_op" "hs4x_basic_alul_op")
230 (define_bypass 1 "hs4x_fpu_cvt_op" "hs4x_adv_alul_op")
231 (define_bypass 1 "hs4x_fpu_cvt_op" "hs4x_mul_*op")
232 (define_bypass 4 "hs4x_fpu_cvt_op" "hs4x_divrem_op")
233 (define_bypass 4 "hs4x_fpu_cvt_op" "hs4x_fpu_*op")
234 (define_bypass 0 "hs4x_fpu_cvt_op" "hs4x_data_store_op" "store_data_bypass_p")