1 ;; Predicate definitions for Renesas / SuperH SH.
2 ;; Copyright (C) 2005-2013 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; TODO: Add a comment here.
21 (define_predicate "trapping_target_operand"
22 (match_code "if_then_else")
24 rtx cond, mem, res, tar, and_expr;
26 if (GET_MODE (op) != PDImode)
32 || (GET_CODE (res) != SIGN_EXTEND && GET_CODE (res) != TRUNCATE))
35 if (!rtx_equal_p (XEXP (mem, 0), tar)
36 || GET_MODE (tar) != Pmode)
38 if (GET_CODE (cond) == CONST)
40 cond = XEXP (cond, 0);
41 if (!satisfies_constraint_Csy (tar))
43 if (GET_CODE (tar) == CONST)
46 else if (!arith_reg_operand (tar, VOIDmode)
47 && ! satisfies_constraint_Csy (tar))
49 if (GET_CODE (cond) != EQ)
51 and_expr = XEXP (cond, 0);
52 return (GET_CODE (and_expr) == AND
53 && rtx_equal_p (XEXP (and_expr, 0), tar)
54 && CONST_INT_P (XEXP (and_expr, 1))
55 && CONST_INT_P (XEXP (cond, 1))
56 && INTVAL (XEXP (and_expr, 1)) == 3
57 && INTVAL (XEXP (cond, 1)) == 3);
60 ;; A logical operand that can be used in an shmedia and insn.
61 (define_predicate "and_operand"
62 (match_code "subreg,reg,const_int")
64 if (logical_operand (op, mode))
67 /* Check mshflo.l / mshflhi.l opportunities. */
70 && satisfies_constraint_J16 (op))
76 ;; Like arith_reg_dest, but this predicate is defined with
77 ;; define_special_predicate, not define_predicate.
78 (define_special_predicate "any_arith_reg_dest"
79 (match_code "subreg,reg")
81 return arith_reg_dest (op, mode);
84 ;; Like register_operand, but this predicate is defined with
85 ;; define_special_predicate, not define_predicate.
86 (define_special_predicate "any_register_operand"
87 (match_code "subreg,reg")
89 return register_operand (op, mode);
92 ;; Returns 1 if OP is a valid source operand for an arithmetic insn.
93 (define_predicate "arith_operand"
94 (match_code "subreg,reg,const_int,truncate")
96 if (arith_reg_operand (op, mode))
101 /* FIXME: We should be checking whether the CONST_INT fits in a
102 signed 16-bit here, but this causes reload_cse to crash when
103 attempting to transform a sequence of two 64-bit sets of the
104 same register from literal constants into a set and an add,
105 when the difference is too wide for an add. */
107 || satisfies_constraint_Css (op))
109 else if (GET_CODE (op) == TRUNCATE
110 && REG_P (XEXP (op, 0))
111 && ! system_reg_operand (XEXP (op, 0), VOIDmode)
112 && (mode == VOIDmode || mode == GET_MODE (op))
113 && (GET_MODE_SIZE (GET_MODE (op))
114 < GET_MODE_SIZE (GET_MODE (XEXP (op, 0))))
115 && (! FP_REGISTER_P (REGNO (XEXP (op, 0)))
116 || GET_MODE_SIZE (GET_MODE (op)) == 4))
117 return register_operand (XEXP (op, 0), VOIDmode);
121 else if (satisfies_constraint_I08 (op))
127 ;; Like above, but for DImode destinations: forbid paradoxical DImode
128 ;; subregs, because this would lead to missing sign extensions when
129 ;; truncating from DImode to SImode.
130 (define_predicate "arith_reg_dest"
131 (match_code "subreg,reg")
133 if (mode == DImode && GET_CODE (op) == SUBREG
134 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8
137 return arith_reg_operand (op, mode);
140 ;; Returns 1 if OP is a normal arithmetic register.
141 (define_predicate "arith_reg_operand"
142 (match_code "subreg,reg,sign_extend")
144 if (register_operand (op, mode))
150 else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
151 regno = REGNO (SUBREG_REG (op));
155 return (regno != T_REG && regno != PR_REG
156 && ! TARGET_REGISTER_P (regno)
158 && regno != MACH_REG && regno != MACL_REG);
160 /* Allow a no-op sign extension - compare LOAD_EXTEND_OP.
161 We allow SImode here, as not using an FP register is just a matter of
162 proper register allocation. */
164 && GET_MODE (op) == DImode && GET_CODE (op) == SIGN_EXTEND
165 && GET_MODE (XEXP (op, 0)) == SImode
166 && GET_CODE (XEXP (op, 0)) != SUBREG)
167 return register_operand (XEXP (op, 0), VOIDmode);
168 #if 0 /* Can't do this because of PROMOTE_MODE for unsigned vars. */
169 if (GET_MODE (op) == SImode && GET_CODE (op) == SIGN_EXTEND
170 && GET_MODE (XEXP (op, 0)) == HImode
171 && REG_P (XEXP (op, 0))
172 && REGNO (XEXP (op, 0)) <= LAST_GENERAL_REG)
173 return register_operand (XEXP (op, 0), VOIDmode);
175 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT
176 && GET_CODE (op) == SUBREG
177 && GET_MODE (SUBREG_REG (op)) == DImode
178 && GET_CODE (SUBREG_REG (op)) == SIGN_EXTEND
179 && GET_MODE (XEXP (SUBREG_REG (op), 0)) == SImode
180 && GET_CODE (XEXP (SUBREG_REG (op), 0)) != SUBREG)
181 return register_operand (XEXP (SUBREG_REG (op), 0), VOIDmode);
185 ;; Returns 1 if OP is a valid source operand for a compare insn.
186 (define_predicate "arith_reg_or_0_operand"
187 (match_code "subreg,reg,const_int,const_vector")
189 if (arith_reg_operand (op, mode))
192 if (satisfies_constraint_Z (op))
198 ;; Returns true if OP is either a register or constant 0 or constant 1.
199 (define_predicate "arith_reg_or_0_or_1_operand"
200 (match_code "subreg,reg,const_int,const_vector")
202 return arith_reg_or_0_operand (op, mode) || satisfies_constraint_M (op);
205 ;; Returns true if OP is a suitable constant for the minimum value of a
206 ;; clips.b or clips.w insn.
207 (define_predicate "clips_min_const_int"
208 (and (match_code "const_int")
209 (ior (match_test "INTVAL (op) == -128")
210 (match_test "INTVAL (op) == -32768"))))
212 ;; Returns true if OP is a suitable constant for the maximum value of a
213 ;; clips.b or clips.w insn.
214 (define_predicate "clips_max_const_int"
215 (and (match_code "const_int")
216 (ior (match_test "INTVAL (op) == 127")
217 (match_test "INTVAL (op) == 32767"))))
219 ;; Returns true if OP is a suitable constant for the maximum value of a
220 ;; clipu.b or clipu.w insn.
221 (define_predicate "clipu_max_const_int"
222 (and (match_code "const_int")
223 (ior (match_test "INTVAL (op) == 255")
224 (match_test "INTVAL (op) == 65535"))))
226 ;; Returns 1 if OP is a floating point operator with two operands.
227 (define_predicate "binary_float_operator"
228 (and (match_code "plus,minus,mult,div")
229 (match_test "GET_MODE (op) == mode")))
231 ;; Returns 1 if OP is a logical operator with two operands.
232 (define_predicate "binary_logical_operator"
233 (and (match_code "and,ior,xor")
234 (match_test "GET_MODE (op) == mode")))
236 ;; Return 1 if OP is an address suitable for a cache manipulation operation.
237 ;; MODE has the meaning as in address_operand.
238 (define_special_predicate "cache_address_operand"
239 (match_code "plus,reg")
241 if (GET_CODE (op) == PLUS)
243 if (!REG_P (XEXP (op, 0)))
245 if (!CONST_INT_P (XEXP (op, 1))
246 || (INTVAL (XEXP (op, 1)) & 31))
249 else if (!REG_P (op))
251 return address_operand (op, mode);
254 ;; Returns 1 if OP is a valid source operand for shmedia cmpgt / cmpgtu.
255 (define_predicate "cmp_operand"
256 (match_code "subreg,reg,const_int")
258 if (satisfies_constraint_N (op))
261 && mode != DImode && GET_CODE (op) == SUBREG
262 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
264 return arith_reg_operand (op, mode);
267 ;; Returns true if OP is an operand that can be used as the first operand in
268 ;; the cstoresi4 expander pattern.
269 (define_predicate "cmpsi_operand"
270 (match_code "subreg,reg,const_int")
272 if (REG_P (op) && REGNO (op) == T_REG
273 && GET_MODE (op) == SImode
276 return arith_operand (op, mode);
279 ;; Returns true if OP is a comutative float operator.
280 ;; This predicate is currently unused.
281 ;;(define_predicate "commutative_float_operator"
282 ;; (and (match_code "plus,mult")
283 ;; (match_test "GET_MODE (op) == mode")))
285 ;; Returns true if OP is a equal or not equal operator.
286 (define_predicate "equality_comparison_operator"
287 (match_code "eq,ne"))
289 ;; Returns true if OP is an arithmetic operand that is zero extended during
291 (define_predicate "extend_reg_operand"
292 (match_code "subreg,reg,truncate")
294 return (GET_CODE (op) == TRUNCATE
296 : arith_reg_operand) (op, mode);
299 ;; Like extend_reg_operand, but also allow a constant 0.
300 (define_predicate "extend_reg_or_0_operand"
301 (match_code "subreg,reg,truncate,const_int")
303 return (GET_CODE (op) == TRUNCATE
305 : arith_reg_or_0_operand) (op, mode);
308 ;; Like arith_reg_operand, but this predicate does not accept SIGN_EXTEND.
309 (define_predicate "ext_dest_operand"
310 (match_code "subreg,reg")
312 return arith_reg_operand (op, mode);
315 ;; Returns true if OP can be used as a destination register for shmedia floating
316 ;; point to integer conversions.
317 (define_predicate "fp_arith_reg_dest"
318 (match_code "subreg,reg")
320 if (mode == DImode && GET_CODE (op) == SUBREG
321 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8)
323 return fp_arith_reg_operand (op, mode);
326 ;; Returns true if OP is a floating point register that can be used in floating
327 ;; point arithmetic operations.
328 (define_predicate "fp_arith_reg_operand"
329 (match_code "subreg,reg")
331 if (register_operand (op, mode))
337 else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
338 regno = REGNO (SUBREG_REG (op));
342 return (regno >= FIRST_PSEUDO_REGISTER
343 || FP_REGISTER_P (regno));
348 ;; Returns true if OP is the FPSCR.
349 (define_predicate "fpscr_operand"
353 && (REGNO (op) == FPSCR_REG
354 || (REGNO (op) >= FIRST_PSEUDO_REGISTER
355 && !(reload_in_progress || reload_completed)))
356 && GET_MODE (op) == PSImode);
359 ;; Returns true if OP is an operand that is either the fpul hard reg or
360 ;; a pseudo. This prevents combine from propagating function arguments
361 ;; in hard regs into insns that need the operand in fpul. If it's a pseudo
362 ;; reload can fix it up.
363 (define_predicate "fpul_operand"
367 return fp_arith_reg_operand (op, mode);
370 && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
371 && GET_MODE (op) == mode);
374 ;; Returns true if OP is a valid fpul input operand for the fsca insn.
375 ;; The value in fpul is a fixed-point value and its scaling is described
376 ;; in the fsca insn by a mult:SF. To allow pre-scaled fixed-point inputs
377 ;; in fpul we have to permit things like
379 ;; (fix:SF (float:SF (reg:SI)))
380 (define_predicate "fpul_fsca_operand"
381 (match_code "fix,reg")
383 if (fpul_operand (op, SImode))
385 if (GET_CODE (op) == FIX && GET_MODE (op) == SImode
386 && GET_CODE (XEXP (op, 0)) == FLOAT && GET_MODE (XEXP (op, 0)) == SFmode)
387 return fpul_fsca_operand (XEXP (XEXP (op, 0), 0),
388 GET_MODE (XEXP (XEXP (op, 0), 0)));
392 ;; Returns true if OP is a valid constant scale factor for the fsca insn.
393 (define_predicate "fsca_scale_factor"
394 (and (match_code "const_double")
395 (match_test "op == sh_fsca_int2sf ()")))
397 ;; Returns true if OP is an operand that is zero extended during an operation.
398 (define_predicate "general_extend_operand"
399 (match_code "subreg,reg,mem,truncate")
401 if (GET_CODE (op) == TRUNCATE)
402 return arith_operand (op, mode);
404 if (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op))))
405 return general_movsrc_operand (op, mode);
407 return nonimmediate_operand (op, mode);
410 ;; Returns 1 if OP is a simple register address.
411 (define_predicate "simple_mem_operand"
412 (and (match_code "mem")
413 (match_test "arith_reg_operand (XEXP (op, 0), SImode)")))
415 ;; Returns 1 if OP is a valid displacement address.
416 (define_predicate "displacement_mem_operand"
417 (and (match_code "mem")
418 (match_test "GET_CODE (XEXP (op, 0)) == PLUS")
419 (match_test "arith_reg_operand (XEXP (XEXP (op, 0), 0), SImode)")
420 (match_test "sh_legitimate_index_p (GET_MODE (op),
421 XEXP (XEXP (op, 0), 1),
422 TARGET_SH2A, true)")))
424 ;; Returns 1 if the operand can be used in an SH2A movu.{b|w} insn.
425 (define_predicate "zero_extend_movu_operand"
426 (and (match_operand 0 "displacement_mem_operand")
427 (match_test "GET_MODE (op) == QImode || GET_MODE (op) == HImode")))
429 ;; Returns 1 if the operand can be used in a zero_extend.
430 (define_predicate "zero_extend_operand"
431 (ior (and (match_test "TARGET_SHMEDIA")
432 (match_operand 0 "general_extend_operand"))
433 (and (match_test "! TARGET_SHMEDIA")
434 (match_operand 0 "arith_reg_operand"))
435 (and (match_test "TARGET_SH2A")
436 (match_operand 0 "zero_extend_movu_operand"))))
438 ;; Returns 1 if OP can be source of a simple move operation. Same as
439 ;; general_operand, but a LABEL_REF is valid, PRE_DEC is invalid as
440 ;; are subregs of system registers.
441 (define_predicate "general_movsrc_operand"
442 (match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref,
445 if (t_reg_operand (op, mode))
450 rtx inside = XEXP (op, 0);
452 /* Disallow mems with GBR address here. They have to go through
453 separate special patterns. */
454 if ((REG_P (inside) && REGNO (inside) == GBR_REG)
455 || (GET_CODE (inside) == PLUS && REG_P (XEXP (inside, 0))
456 && REGNO (XEXP (inside, 0)) == GBR_REG))
459 if (GET_CODE (inside) == CONST)
460 inside = XEXP (inside, 0);
462 if (GET_CODE (inside) == LABEL_REF)
465 if (GET_CODE (inside) == PLUS
466 && GET_CODE (XEXP (inside, 0)) == LABEL_REF
467 && CONST_INT_P (XEXP (inside, 1)))
470 /* Only post inc allowed. */
471 if (GET_CODE (inside) == PRE_DEC)
475 if (mode == GET_MODE (op)
476 && (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))))
478 rtx mem_rtx = MEM_P (op) ? op : SUBREG_REG (op);
479 rtx x = XEXP (mem_rtx, 0);
481 if ((mode == QImode || mode == HImode)
482 && GET_CODE (x) == PLUS
483 && REG_P (XEXP (x, 0))
484 && CONST_INT_P (XEXP (x, 1)))
485 return sh_legitimate_index_p (mode, XEXP (x, 1), TARGET_SH2A, false);
487 /* Allow reg+reg addressing here without validating the register
488 numbers. Usually one of the regs must be R0 or a pseudo reg.
489 In some cases it can happen that arguments from hard regs are
490 propagated directly into address expressions. In this cases reload
491 will have to fix it up later. However, allow this only for native
492 1, 2 or 4 byte addresses. */
493 if (can_create_pseudo_p () && GET_CODE (x) == PLUS
494 && GET_MODE_SIZE (mode) <= 4
495 && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1)))
498 /* 'general_operand' does not allow volatile mems during RTL expansion to
499 avoid matching arithmetic that operates on mems, it seems.
500 On SH this leads to redundant sign extensions for QImode or HImode
501 loads. Thus we mimic the behavior but allow volatile mems. */
502 if (memory_address_addr_space_p (GET_MODE (mem_rtx), x,
503 MEM_ADDR_SPACE (mem_rtx)))
508 && (GET_CODE (op) == PARALLEL || GET_CODE (op) == CONST_VECTOR)
509 && sh_rep_vec (op, mode))
511 if (TARGET_SHMEDIA && 1
512 && GET_CODE (op) == SUBREG && GET_MODE (op) == mode
513 && SUBREG_REG (op) == const0_rtx && subreg_lowpart_p (op))
514 /* FIXME */ abort (); /* return 1; */
516 return general_operand (op, mode);
519 ;; Returns 1 if OP is a MEM that does not use displacement addressing.
520 (define_predicate "movsrc_no_disp_mem_operand"
523 return general_movsrc_operand (op, mode) && satisfies_constraint_Snd (op);
526 ;; Returns 1 if OP can be a destination of a move. Same as
527 ;; general_operand, but no preinc allowed.
528 (define_predicate "general_movdst_operand"
529 (match_code "subreg,reg,mem")
531 if (t_reg_operand (op, mode))
536 rtx inside = XEXP (op, 0);
537 /* Disallow mems with GBR address here. They have to go through
538 separate special patterns. */
539 if ((REG_P (inside) && REGNO (inside) == GBR_REG)
540 || (GET_CODE (inside) == PLUS && REG_P (XEXP (inside, 0))
541 && REGNO (XEXP (inside, 0)) == GBR_REG))
545 /* Only pre dec allowed. */
546 if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == POST_INC)
548 if (mode == DImode && TARGET_SHMEDIA && GET_CODE (op) == SUBREG
549 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8
550 && ! (reload_in_progress || reload_completed))
553 if (mode == GET_MODE (op)
554 && (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))))
556 rtx mem_rtx = MEM_P (op) ? op : SUBREG_REG (op);
557 rtx x = XEXP (mem_rtx, 0);
559 if ((mode == QImode || mode == HImode)
560 && GET_CODE (x) == PLUS
561 && REG_P (XEXP (x, 0))
562 && CONST_INT_P (XEXP (x, 1)))
563 return sh_legitimate_index_p (mode, XEXP (x, 1), TARGET_SH2A, false);
565 /* Allow reg+reg addressing here without validating the register
566 numbers. Usually one of the regs must be R0 or a pseudo reg.
567 In some cases it can happen that arguments from hard regs are
568 propagated directly into address expressions. In this cases reload
569 will have to fix it up later. However, allow this only for native
570 1, 2 or 4 byte addresses. */
571 if (can_create_pseudo_p () && GET_CODE (x) == PLUS
572 && GET_MODE_SIZE (mode) <= 4
573 && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1)))
576 /* 'general_operand' does not allow volatile mems during RTL expansion to
577 avoid matching arithmetic that operates on mems, it seems.
578 On SH this leads to redundant sign extensions for QImode or HImode
579 stores. Thus we mimic the behavior but allow volatile mems. */
580 if (memory_address_addr_space_p (GET_MODE (mem_rtx), x,
581 MEM_ADDR_SPACE (mem_rtx)))
585 return general_operand (op, mode);
588 ;; Returns 1 if OP is a POST_INC on stack pointer register.
589 (define_predicate "sh_no_delay_pop_operand"
593 inside = XEXP (op, 0);
595 if (GET_CODE (op) == MEM && GET_MODE (op) == SImode
596 && GET_CODE (inside) == POST_INC
597 && GET_CODE (XEXP (inside, 0)) == REG
598 && REGNO (XEXP (inside, 0)) == SP_REG)
604 ;; Returns 1 if OP is a MEM that can be source of a simple move operation.
605 (define_predicate "unaligned_load_operand"
610 if (!MEM_P (op) || GET_MODE (op) != mode)
613 inside = XEXP (op, 0);
615 if (GET_CODE (inside) == POST_INC)
616 inside = XEXP (inside, 0);
624 ;; Returns 1 if OP is a MEM that can be used in "index_disp" combiner
626 (define_predicate "mem_index_disp_operand"
629 rtx plus0_rtx, plus1_rtx, mult_rtx;
631 plus0_rtx = XEXP (op, 0);
632 if (GET_CODE (plus0_rtx) != PLUS)
635 plus1_rtx = XEXP (plus0_rtx, 0);
636 if (GET_CODE (plus1_rtx) != PLUS)
638 if (! arith_reg_operand (XEXP (plus1_rtx, 1), GET_MODE (XEXP (plus1_rtx, 1))))
641 mult_rtx = XEXP (plus1_rtx, 0);
642 if (GET_CODE (mult_rtx) != MULT)
644 if (! arith_reg_operand (XEXP (mult_rtx, 0), GET_MODE (XEXP (mult_rtx, 0)))
645 || ! CONST_INT_P (XEXP (mult_rtx, 1)))
648 return exact_log2 (INTVAL (XEXP (mult_rtx, 1))) > 0
649 && sh_legitimate_index_p (mode, XEXP (plus0_rtx, 1), TARGET_SH2A, true);
652 ;; Returns true if OP is some kind of greater comparision.
653 (define_predicate "greater_comparison_operator"
654 (match_code "gt,ge,gtu,geu"))
656 ;; Returns true if OP is an operand suitable for shmedia reload_inqi and
657 ;; reload_inhi insns.
658 (define_predicate "inqhi_operand"
659 (match_code "truncate")
661 if (GET_CODE (op) != TRUNCATE || mode != GET_MODE (op))
664 /* Can't use true_regnum here because copy_cost wants to know about
665 SECONDARY_INPUT_RELOAD_CLASS. */
666 return REG_P (op) && FP_REGISTER_P (REGNO (op));
669 ;; Returns true if OP is a general purpose integer register.
670 ;; This predicate is currently unused.
671 ;;(define_special_predicate "int_gpr_dest"
672 ;; (match_code "subreg,reg")
674 ;; enum machine_mode op_mode = GET_MODE (op);
676 ;; if (GET_MODE_CLASS (op_mode) != MODE_INT
677 ;; || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
679 ;; if (! reload_completed)
681 ;; return true_regnum (op) <= LAST_GENERAL_REG;
684 ;; Returns true if OP is some kind of less comparison.
685 (define_predicate "less_comparison_operator"
686 (match_code "lt,le,ltu,leu"))
688 ;; Returns 1 if OP is a valid source operand for a logical operation.
689 (define_predicate "logical_operand"
690 (match_code "subreg,reg,const_int")
693 && mode != DImode && GET_CODE (op) == SUBREG
694 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
697 if (arith_reg_operand (op, mode))
702 if (satisfies_constraint_I10 (op))
707 else if (satisfies_constraint_K08 (op))
713 ;; Like logical_operand but allows additional constant values which can be
714 ;; done with zero extensions. Used for the second operand of and insns.
715 (define_predicate "logical_and_operand"
716 (match_code "subreg,reg,const_int")
718 if (logical_operand (op, mode))
722 && (satisfies_constraint_Jmb (op) || satisfies_constraint_Jmw (op)))
728 ;; Returns true if OP is a logical operator.
729 (define_predicate "logical_operator"
730 (match_code "and,ior,xor"))
732 ;; Like arith_reg_operand, but for register source operands of narrow
733 ;; logical SHMEDIA operations: forbid subregs of DImode / TImode regs.
734 (define_predicate "logical_reg_operand"
735 (match_code "subreg,reg")
738 && GET_CODE (op) == SUBREG
739 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4
742 return arith_reg_operand (op, mode);
745 ;; Returns true if OP is a valid bit offset value for the shmedia mextr insns.
746 (define_predicate "mextr_bit_offset"
747 (match_code "const_int")
751 if (!CONST_INT_P (op))
754 return i >= 1 * 8 && i <= 7 * 8 && (i & 7) == 0;
757 ;; Returns true if OP is a constant -1, 0 or an zero extended register that
758 ;; can be used as an operator in the *subsi3_media insn.
759 (define_predicate "minuend_operand"
760 (match_code "subreg,reg,truncate,const_int")
762 return op == constm1_rtx || extend_reg_or_0_operand (op, mode);
765 ;; Returns true if OP is a noncommutative floating point operator.
766 ;; This predicate is currently unused.
767 ;;(define_predicate "noncommutative_float_operator"
768 ;; (and (match_code "minus,div")
769 ;; (match_test "GET_MODE (op) == mode")))
771 ;; UNORDERED is only supported on SHMEDIA.
773 (define_predicate "sh_float_comparison_operator"
774 (ior (match_operand 0 "ordered_comparison_operator")
775 (and (match_test "TARGET_SHMEDIA")
776 (match_code "unordered"))))
778 (define_predicate "shmedia_cbranch_comparison_operator"
779 (ior (match_operand 0 "equality_comparison_operator")
780 (match_operand 0 "greater_comparison_operator")))
782 ;; Returns true if OP is a constant vector.
783 (define_predicate "sh_const_vec"
784 (match_code "const_vector")
788 if (GET_CODE (op) != CONST_VECTOR
789 || (GET_MODE (op) != mode && mode != VOIDmode))
791 i = XVECLEN (op, 0) - 1;
793 if (!CONST_INT_P (XVECEXP (op, 0, i)))
798 ;; Determine if OP is a constant vector matching MODE with only one
799 ;; element that is not a sign extension. Two byte-sized elements
801 (define_predicate "sh_1el_vec"
802 (match_code "const_vector")
805 int i, last, least, sign_ix;
808 if (GET_CODE (op) != CONST_VECTOR
809 || (GET_MODE (op) != mode && mode != VOIDmode))
811 /* Determine numbers of last and of least significant elements. */
812 last = XVECLEN (op, 0) - 1;
813 least = TARGET_LITTLE_ENDIAN ? 0 : last;
814 if (!CONST_INT_P (XVECEXP (op, 0, least)))
817 if (GET_MODE_UNIT_SIZE (mode) == 1)
818 sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1;
819 if (!CONST_INT_P (XVECEXP (op, 0, sign_ix)))
821 unit_size = GET_MODE_UNIT_SIZE (GET_MODE (op));
822 sign = (INTVAL (XVECEXP (op, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1)
823 ? constm1_rtx : const0_rtx);
824 i = XVECLEN (op, 0) - 1;
826 if (i != least && i != sign_ix && XVECEXP (op, 0, i) != sign)
832 ;; Like register_operand, but take into account that SHMEDIA can use
833 ;; the constant zero like a general register.
834 (define_predicate "sh_register_operand"
835 (match_code "reg,subreg,const_int,const_double")
837 if (op == CONST0_RTX (mode) && TARGET_SHMEDIA)
839 return register_operand (op, mode);
842 ;; Returns true if OP is a vector which is composed of one element that is
844 (define_predicate "sh_rep_vec"
845 (match_code "const_vector,parallel")
850 if ((GET_CODE (op) != CONST_VECTOR && GET_CODE (op) != PARALLEL)
851 || (GET_MODE (op) != mode && mode != VOIDmode))
853 i = XVECLEN (op, 0) - 2;
854 x = XVECEXP (op, 0, i + 1);
855 if (GET_MODE_UNIT_SIZE (mode) == 1)
857 y = XVECEXP (op, 0, i);
858 for (i -= 2; i >= 0; i -= 2)
859 if (! rtx_equal_p (XVECEXP (op, 0, i + 1), x)
860 || ! rtx_equal_p (XVECEXP (op, 0, i), y))
865 if (XVECEXP (op, 0, i) != x)
870 ;; Returns true if OP is a valid shift count operand for shift operations.
871 (define_predicate "shift_count_operand"
872 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,
873 zero_extend,sign_extend")
875 /* Allow T_REG as shift count for dynamic shifts, although it is not
876 really possible. It will then be copied to a general purpose reg. */
877 if (! TARGET_SHMEDIA)
878 return const_int_operand (op, mode) || arith_reg_operand (op, mode)
879 || (TARGET_DYNSHIFT && t_reg_operand (op, mode));
881 return (CONSTANT_P (op)
883 ? (unsigned) INTVAL (op) < GET_MODE_BITSIZE (mode)
884 : nonmemory_operand (op, mode))
885 : shift_count_reg_operand (op, mode));
888 ;; Returns true if OP is a valid shift count operand in a register which can
889 ;; be used by shmedia shift insns.
890 (define_predicate "shift_count_reg_operand"
891 (match_code "subreg,reg,zero_extend,sign_extend")
893 if ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND
894 || (GET_CODE (op) == SUBREG && SUBREG_BYTE (op) == 0))
895 && (mode == VOIDmode || mode == GET_MODE (op))
896 && GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6
897 && GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT)
902 while ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND
903 || GET_CODE (op) == TRUNCATE)
904 && GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6
905 && GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT);
908 return arith_reg_operand (op, mode);
911 ;; Predicates for matching operands that are constant shift
912 ;; amounts 1, 2, 8, 16.
913 (define_predicate "p27_shift_count_operand"
914 (and (match_code "const_int")
915 (match_test "satisfies_constraint_P27 (op)")))
917 (define_predicate "not_p27_shift_count_operand"
918 (and (match_code "const_int")
919 (match_test "! satisfies_constraint_P27 (op)")))
921 ;; For right shifts the constant 1 is a special case because the shlr insn
922 ;; clobbers the T_REG and is handled by the T_REG clobbering version of the
923 ;; insn, which is also used for non-P27 shift sequences.
924 (define_predicate "p27_rshift_count_operand"
925 (and (match_code "const_int")
926 (match_test "satisfies_constraint_P27 (op)")
927 (match_test "! satisfies_constraint_M (op)")))
929 (define_predicate "not_p27_rshift_count_operand"
930 (and (match_code "const_int")
931 (ior (match_test "! satisfies_constraint_P27 (op)")
932 (match_test "satisfies_constraint_M (op)"))))
934 ;; Returns true if OP is some kind of a shift operator.
935 (define_predicate "shift_operator"
936 (match_code "ashift,ashiftrt,lshiftrt"))
938 ;; Returns true if OP is a symbol reference.
939 (define_predicate "symbol_ref_operand"
940 (match_code "symbol_ref"))
942 ;; Same as target_reg_operand, except that label_refs and symbol_refs
943 ;; are accepted before reload.
944 (define_special_predicate "target_operand"
945 (match_code "subreg,reg,label_ref,symbol_ref,const,unspec")
947 if (mode != VOIDmode && mode != Pmode)
950 if ((GET_MODE (op) == Pmode || GET_MODE (op) == VOIDmode)
951 && satisfies_constraint_Csy (op))
952 return ! reload_completed;
954 return target_reg_operand (op, mode);
957 ;; A predicate that accepts pseudos and branch target registers.
958 (define_special_predicate "target_reg_operand"
959 (match_code "subreg,reg")
962 ? GET_MODE (op) != Pmode && GET_MODE (op) != PDImode
963 : mode != GET_MODE (op))
966 if (GET_CODE (op) == SUBREG)
972 /* We must protect ourselves from matching pseudos that are virtual
973 register, because they will eventually be replaced with hardware
974 registers that aren't branch-target registers. */
975 if (REGNO (op) > LAST_VIRTUAL_REGISTER
976 || TARGET_REGISTER_P (REGNO (op)))
982 ;; Returns true if OP is a valid operand for the shmedia mperm.w insn.
983 (define_special_predicate "trunc_hi_operand"
984 (match_code "subreg,reg,truncate")
986 enum machine_mode op_mode = GET_MODE (op);
988 if (op_mode != SImode && op_mode != DImode
989 && op_mode != V4HImode && op_mode != V2SImode)
991 return extend_reg_operand (op, mode);
994 ;; Returns true if OP is an address suitable for an unaligned access
996 (define_special_predicate "ua_address_operand"
997 (match_code "subreg,reg,plus")
999 if (GET_CODE (op) == PLUS
1000 && (! satisfies_constraint_I06 (XEXP (op, 1))))
1002 return address_operand (op, QImode);
1005 ;; Returns true if OP is a valid offset for an unaligned memory address.
1006 (define_predicate "ua_offset"
1007 (match_code "const_int")
1009 return satisfies_constraint_I06 (op);
1012 ;; Returns true if OP is a floating point operator with one operand.
1013 (define_predicate "unary_float_operator"
1014 (and (match_code "abs,neg,sqrt")
1015 (match_test "GET_MODE (op) == mode")))
1017 ;; Return 1 if OP is a valid source operand for xor.
1018 (define_predicate "xor_operand"
1019 (match_code "subreg,reg,const_int")
1021 if (CONST_INT_P (op))
1022 return (TARGET_SHMEDIA
1023 ? (satisfies_constraint_I06 (op)
1024 || (!can_create_pseudo_p () && INTVAL (op) == 0xff))
1025 : satisfies_constraint_K08 (op));
1027 && mode != DImode && GET_CODE (op) == SUBREG
1028 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
1030 return arith_reg_operand (op, mode);
1033 (define_predicate "bitwise_memory_operand"
1038 if (REG_P (XEXP (op, 0)))
1041 if (GET_CODE (XEXP (op, 0)) == PLUS
1042 && REG_P (XEXP (XEXP (op, 0), 0))
1043 && satisfies_constraint_K12 (XEXP (XEXP (op, 0), 1)))
1049 ;; The atomic_* operand predicates are used for the atomic patterns.
1050 ;; Depending on the particular pattern some operands can be immediate
1051 ;; values. Using these predicates avoids the usage of 'force_reg' in the
1053 (define_predicate "atomic_arith_operand"
1054 (ior (match_code "subreg,reg")
1055 (and (match_test "satisfies_constraint_I08 (op)")
1056 (match_test "mode != QImode")
1057 (match_test "mode != HImode")
1058 (match_test "TARGET_SH4A_ARCH"))))
1060 (define_predicate "atomic_logical_operand"
1061 (ior (match_code "subreg,reg")
1062 (and (match_test "satisfies_constraint_K08 (op)")
1063 (match_test "mode != QImode")
1064 (match_test "mode != HImode")
1065 (match_test "TARGET_SH4A_ARCH"))))
1067 ;; A predicate describing the T bit register in any form.
1068 (define_predicate "t_reg_operand"
1069 (match_code "reg,subreg,sign_extend,zero_extend")
1071 switch (GET_CODE (op))
1074 return REGNO (op) == T_REG;
1077 return REG_P (SUBREG_REG (op)) && REGNO (SUBREG_REG (op)) == T_REG;
1081 return GET_CODE (XEXP (op, 0)) == SUBREG
1082 && REG_P (SUBREG_REG (XEXP (op, 0)))
1083 && REGNO (SUBREG_REG (XEXP (op, 0))) == T_REG;
1090 ;; A predicate describing a negated T bit register.
1091 (define_predicate "negt_reg_operand"
1092 (match_code "subreg,xor")
1094 switch (GET_CODE (op))
1097 return t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)))
1098 && satisfies_constraint_M (XEXP (op, 1));
1101 return negt_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)));
1108 ;; A predicate that returns true if OP is a valid construct around the T bit
1109 ;; that can be used as an operand for conditional branches.
1110 (define_predicate "cbranch_treg_value"
1111 (match_code "eq,ne,reg,subreg,xor,sign_extend,zero_extend")
1113 return sh_eval_treg_value (op) >= 0;
1116 ;; Returns true if OP is arith_reg_operand or t_reg_operand.
1117 (define_predicate "arith_reg_or_t_reg_operand"
1118 (ior (match_operand 0 "arith_reg_operand")
1119 (match_operand 0 "t_reg_operand")))
1121 ;; A predicate describing the negated value of the T bit register shifted
1123 (define_predicate "negt_reg_shl31_operand"
1124 (match_code "plus,minus,if_then_else")
1126 /* (plus:SI (mult:SI (match_operand:SI 1 "t_reg_operand")
1127 (const_int -2147483648)) ;; 0xffffffff80000000
1128 (const_int -2147483648))
1130 if (GET_CODE (op) == PLUS && satisfies_constraint_Jhb (XEXP (op, 1))
1131 && GET_CODE (XEXP (op, 0)) == MULT
1132 && t_reg_operand (XEXP (XEXP (op, 0), 0), SImode)
1133 && satisfies_constraint_Jhb (XEXP (XEXP (op, 0), 1)))
1136 /* (minus:SI (const_int -2147483648) ;; 0xffffffff80000000
1137 (mult:SI (match_operand:SI 1 "t_reg_operand")
1138 (const_int -2147483648)))
1140 if (GET_CODE (op) == MINUS
1141 && satisfies_constraint_Jhb (XEXP (op, 0))
1142 && GET_CODE (XEXP (op, 1)) == MULT
1143 && t_reg_operand (XEXP (XEXP (op, 1), 0), SImode)
1144 && satisfies_constraint_Jhb (XEXP (XEXP (op, 1), 1)))
1147 /* (if_then_else:SI (match_operand:SI 1 "t_reg_operand")
1149 (const_int -2147483648)) ;; 0xffffffff80000000
1151 if (GET_CODE (op) == IF_THEN_ELSE && t_reg_operand (XEXP (op, 0), SImode)
1152 && satisfies_constraint_Z (XEXP (op, 1))
1153 && satisfies_constraint_Jhb (XEXP (op, 2)))
1159 ;; A predicate that determines whether a given constant is a valid
1160 ;; displacement for a GBR load/store of the specified mode.
1161 (define_predicate "gbr_displacement"
1162 (match_code "const_int")
1164 const int mode_sz = GET_MODE_SIZE (mode);
1165 const int move_sz = mode_sz > GET_MODE_SIZE (SImode)
1166 ? GET_MODE_SIZE (SImode)
1168 int max_disp = 255 * move_sz;
1169 if (mode_sz > move_sz)
1170 max_disp -= mode_sz - move_sz;
1172 return INTVAL (op) >= 0 && INTVAL (op) <= max_disp;
1175 ;; A predicate that determines whether OP is a valid GBR addressing mode
1176 ;; memory reference.
1177 (define_predicate "gbr_address_mem"
1180 rtx addr = XEXP (op, 0);
1182 if (REG_P (addr) && REGNO (addr) == GBR_REG)
1184 if (GET_CODE (addr) == PLUS
1185 && REG_P (XEXP (addr, 0)) && REGNO (XEXP (addr, 0)) == GBR_REG
1186 && gbr_displacement (XEXP (addr, 1), mode))